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PCI Express cores

Tile PCIE

Cells: 40

Bels PCIE_V6

virtex6 PCIE bel PCIE_V6 pins
PinDirectionPCIE
SYSRSTNinCELL_E[0].IMUX_CTRL[0]
USERCLKinCELL_E[9].IMUX_CLK[0]
USERCLKPREBUFinCELL_E[0].IMUX_CLK[0]
CMRSTNinCELL_E[0].IMUX_CTRL[1]
CMSTICKYRSTNinCELL_E[1].IMUX_CTRL[0]
DLRSTNinCELL_E[2].IMUX_CTRL[1]
TLRSTNinCELL_E[2].IMUX_CTRL[0]
TRNFCSEL[0]inCELL_W[15].IMUX_IMUX_DELAY[1]
TRNFCSEL[1]inCELL_W[15].IMUX_IMUX_DELAY[2]
TRNFCSEL[2]inCELL_W[15].IMUX_IMUX_DELAY[3]
TRNTSOFNinCELL_W[18].IMUX_IMUX_DELAY[3]
TRNTEOFNinCELL_W[17].IMUX_IMUX_DELAY[0]
TRNTD[0]inCELL_E[3].IMUX_IMUX_DELAY[4]
TRNTD[1]inCELL_E[4].IMUX_IMUX_DELAY[0]
TRNTD[2]inCELL_E[4].IMUX_IMUX_DELAY[2]
TRNTD[3]inCELL_E[4].IMUX_IMUX_DELAY[4]
TRNTD[4]inCELL_E[4].IMUX_IMUX_DELAY[5]
TRNTD[5]inCELL_E[5].IMUX_IMUX_DELAY[0]
TRNTD[6]inCELL_E[5].IMUX_IMUX_DELAY[1]
TRNTD[7]inCELL_E[5].IMUX_IMUX_DELAY[2]
TRNTD[8]inCELL_E[5].IMUX_IMUX_DELAY[3]
TRNTD[9]inCELL_E[6].IMUX_IMUX_DELAY[0]
TRNTD[10]inCELL_E[6].IMUX_IMUX_DELAY[1]
TRNTD[11]inCELL_E[6].IMUX_IMUX_DELAY[2]
TRNTD[12]inCELL_E[6].IMUX_IMUX_DELAY[3]
TRNTD[13]inCELL_E[7].IMUX_IMUX_DELAY[0]
TRNTD[14]inCELL_E[7].IMUX_IMUX_DELAY[1]
TRNTD[15]inCELL_E[7].IMUX_IMUX_DELAY[2]
TRNTD[16]inCELL_E[7].IMUX_IMUX_DELAY[3]
TRNTD[17]inCELL_E[8].IMUX_IMUX_DELAY[0]
TRNTD[18]inCELL_E[8].IMUX_IMUX_DELAY[1]
TRNTD[19]inCELL_E[8].IMUX_IMUX_DELAY[2]
TRNTD[20]inCELL_E[8].IMUX_IMUX_DELAY[3]
TRNTD[21]inCELL_E[9].IMUX_IMUX_DELAY[0]
TRNTD[22]inCELL_E[9].IMUX_IMUX_DELAY[1]
TRNTD[23]inCELL_E[9].IMUX_IMUX_DELAY[2]
TRNTD[24]inCELL_E[9].IMUX_IMUX_DELAY[3]
TRNTD[25]inCELL_E[10].IMUX_IMUX_DELAY[0]
TRNTD[26]inCELL_E[11].IMUX_IMUX_DELAY[0]
TRNTD[27]inCELL_E[12].IMUX_IMUX_DELAY[0]
TRNTD[28]inCELL_E[12].IMUX_IMUX_DELAY[2]
TRNTD[29]inCELL_E[12].IMUX_IMUX_DELAY[4]
TRNTD[30]inCELL_E[13].IMUX_IMUX_DELAY[0]
TRNTD[31]inCELL_E[13].IMUX_IMUX_DELAY[2]
TRNTD[32]inCELL_E[13].IMUX_IMUX_DELAY[3]
TRNTD[33]inCELL_E[13].IMUX_IMUX_DELAY[4]
TRNTD[34]inCELL_E[14].IMUX_IMUX_DELAY[0]
TRNTD[35]inCELL_E[14].IMUX_IMUX_DELAY[2]
TRNTD[36]inCELL_E[14].IMUX_IMUX_DELAY[4]
TRNTD[37]inCELL_E[14].IMUX_IMUX_DELAY[5]
TRNTD[38]inCELL_E[15].IMUX_IMUX_DELAY[0]
TRNTD[39]inCELL_E[15].IMUX_IMUX_DELAY[1]
TRNTD[40]inCELL_E[15].IMUX_IMUX_DELAY[2]
TRNTD[41]inCELL_E[15].IMUX_IMUX_DELAY[3]
TRNTD[42]inCELL_E[16].IMUX_IMUX_DELAY[0]
TRNTD[43]inCELL_E[16].IMUX_IMUX_DELAY[1]
TRNTD[44]inCELL_E[16].IMUX_IMUX_DELAY[2]
TRNTD[45]inCELL_E[16].IMUX_IMUX_DELAY[3]
TRNTD[46]inCELL_E[17].IMUX_IMUX_DELAY[0]
TRNTD[47]inCELL_E[17].IMUX_IMUX_DELAY[1]
TRNTD[48]inCELL_E[17].IMUX_IMUX_DELAY[2]
TRNTD[49]inCELL_E[17].IMUX_IMUX_DELAY[3]
TRNTD[50]inCELL_E[18].IMUX_IMUX_DELAY[0]
TRNTD[51]inCELL_E[18].IMUX_IMUX_DELAY[1]
TRNTD[52]inCELL_E[18].IMUX_IMUX_DELAY[2]
TRNTD[53]inCELL_E[18].IMUX_IMUX_DELAY[3]
TRNTD[54]inCELL_E[19].IMUX_IMUX_DELAY[0]
TRNTD[55]inCELL_E[19].IMUX_IMUX_DELAY[1]
TRNTD[56]inCELL_E[19].IMUX_IMUX_DELAY[2]
TRNTD[57]inCELL_E[19].IMUX_IMUX_DELAY[3]
TRNTD[58]inCELL_W[19].IMUX_IMUX_DELAY[0]
TRNTD[59]inCELL_W[19].IMUX_IMUX_DELAY[1]
TRNTD[60]inCELL_W[19].IMUX_IMUX_DELAY[2]
TRNTD[61]inCELL_W[19].IMUX_IMUX_DELAY[3]
TRNTD[62]inCELL_W[18].IMUX_IMUX_DELAY[0]
TRNTD[63]inCELL_W[18].IMUX_IMUX_DELAY[1]
TRNTREMNinCELL_W[18].IMUX_IMUX_DELAY[2]
TRNTSRCRDYNinCELL_W[17].IMUX_IMUX_DELAY[1]
TRNTSRCDSCNinCELL_W[17].IMUX_IMUX_DELAY[2]
TRNTSTRNinCELL_W[16].IMUX_IMUX_DELAY[1]
TRNTCFGGNTNinCELL_W[16].IMUX_IMUX_DELAY[2]
TRNTERRFWDNinCELL_W[17].IMUX_IMUX_DELAY[3]
TRNTECRCGENNinCELL_W[16].IMUX_IMUX_DELAY[0]
TRNTDLLPDATA[0]inCELL_W[13].IMUX_IMUX_DELAY[7]
TRNTDLLPDATA[1]inCELL_W[13].IMUX_IMUX_DELAY[8]
TRNTDLLPDATA[2]inCELL_W[9].IMUX_IMUX_DELAY[4]
TRNTDLLPDATA[3]inCELL_W[9].IMUX_IMUX_DELAY[5]
TRNTDLLPDATA[4]inCELL_W[9].IMUX_IMUX_DELAY[6]
TRNTDLLPDATA[5]inCELL_W[9].IMUX_IMUX_DELAY[7]
TRNTDLLPDATA[6]inCELL_W[8].IMUX_IMUX_DELAY[4]
TRNTDLLPDATA[7]inCELL_W[8].IMUX_IMUX_DELAY[5]
TRNTDLLPDATA[8]inCELL_W[8].IMUX_IMUX_DELAY[6]
TRNTDLLPDATA[9]inCELL_W[8].IMUX_IMUX_DELAY[7]
TRNTDLLPDATA[10]inCELL_W[7].IMUX_IMUX_DELAY[4]
TRNTDLLPDATA[11]inCELL_W[7].IMUX_IMUX_DELAY[5]
TRNTDLLPDATA[12]inCELL_W[7].IMUX_IMUX_DELAY[6]
TRNTDLLPDATA[13]inCELL_W[7].IMUX_IMUX_DELAY[7]
TRNTDLLPDATA[14]inCELL_W[6].IMUX_IMUX_DELAY[4]
TRNTDLLPDATA[15]inCELL_W[6].IMUX_IMUX_DELAY[5]
TRNTDLLPDATA[16]inCELL_W[6].IMUX_IMUX_DELAY[6]
TRNTDLLPDATA[17]inCELL_W[6].IMUX_IMUX_DELAY[7]
TRNTDLLPDATA[18]inCELL_W[5].IMUX_IMUX_DELAY[4]
TRNTDLLPDATA[19]inCELL_W[5].IMUX_IMUX_DELAY[6]
TRNTDLLPDATA[20]inCELL_W[5].IMUX_IMUX_DELAY[7]
TRNTDLLPDATA[21]inCELL_W[5].IMUX_IMUX_DELAY[8]
TRNTDLLPDATA[22]inCELL_W[4].IMUX_IMUX_DELAY[6]
TRNTDLLPDATA[23]inCELL_W[3].IMUX_IMUX_DELAY[5]
TRNTDLLPDATA[24]inCELL_W[3].IMUX_IMUX_DELAY[6]
TRNTDLLPDATA[25]inCELL_W[3].IMUX_IMUX_DELAY[7]
TRNTDLLPDATA[26]inCELL_W[3].IMUX_IMUX_DELAY[8]
TRNTDLLPDATA[27]inCELL_E[3].IMUX_IMUX_DELAY[9]
TRNTDLLPDATA[28]inCELL_E[5].IMUX_IMUX_DELAY[9]
TRNTDLLPDATA[29]inCELL_E[6].IMUX_IMUX_DELAY[8]
TRNTDLLPDATA[30]inCELL_E[6].IMUX_IMUX_DELAY[9]
TRNTDLLPDATA[31]inCELL_E[6].IMUX_IMUX_DELAY[10]
TRNTDLLPSRCRDYNinCELL_E[6].IMUX_IMUX_DELAY[11]
TRNRDSTRDYNinCELL_W[16].IMUX_IMUX_DELAY[3]
TRNRNPOKNinCELL_W[15].IMUX_IMUX_DELAY[0]
PLDIRECTEDLINKAUTONinCELL_E[3].IMUX_IMUX_DELAY[0]
PLDIRECTEDLINKCHANGE[0]inCELL_E[0].IMUX_IMUX_DELAY[0]
PLDIRECTEDLINKCHANGE[1]inCELL_E[1].IMUX_IMUX_DELAY[0]
PLDIRECTEDLINKSPEEDinCELL_E[2].IMUX_IMUX_DELAY[4]
PLDIRECTEDLINKWIDTH[0]inCELL_E[2].IMUX_IMUX_DELAY[0]
PLDIRECTEDLINKWIDTH[1]inCELL_E[2].IMUX_IMUX_DELAY[2]
PLUPSTREAMPREFERDEEMPHinCELL_E[3].IMUX_IMUX_DELAY[2]
PLTRANSMITHOTRSTinCELL_W[14].IMUX_IMUX_DELAY[13]
PL2DIRECTEDLSTATE[0]inCELL_E[8].IMUX_IMUX_DELAY[8]
PL2DIRECTEDLSTATE[1]inCELL_E[8].IMUX_IMUX_DELAY[9]
PL2DIRECTEDLSTATE[2]inCELL_E[8].IMUX_IMUX_DELAY[10]
PL2DIRECTEDLSTATE[3]inCELL_E[8].IMUX_IMUX_DELAY[11]
PL2DIRECTEDLSTATE[4]inCELL_E[9].IMUX_IMUX_DELAY[8]
PLDBGMODE[0]inCELL_E[17].IMUX_IMUX_DELAY[21]
PLDBGMODE[1]inCELL_E[18].IMUX_IMUX_DELAY[21]
PLDBGMODE[2]inCELL_E[19].IMUX_IMUX_DELAY[21]
PLDOWNSTREAMDEEMPHSOURCEinCELL_E[3].IMUX_IMUX_DELAY[3]
PLRSTNinCELL_E[3].IMUX_CTRL[0]
CFGDI[0]inCELL_W[14].IMUX_IMUX_DELAY[14]
CFGDI[1]inCELL_W[14].IMUX_IMUX_DELAY[16]
CFGDI[2]inCELL_W[15].IMUX_IMUX_DELAY[10]
CFGDI[3]inCELL_W[15].IMUX_IMUX_DELAY[12]
CFGDI[4]inCELL_W[15].IMUX_IMUX_DELAY[13]
CFGDI[5]inCELL_W[15].IMUX_IMUX_DELAY[14]
CFGDI[6]inCELL_W[16].IMUX_IMUX_DELAY[9]
CFGDI[7]inCELL_W[16].IMUX_IMUX_DELAY[10]
CFGDI[8]inCELL_W[16].IMUX_IMUX_DELAY[11]
CFGDI[9]inCELL_W[16].IMUX_IMUX_DELAY[12]
CFGDI[10]inCELL_W[17].IMUX_IMUX_DELAY[9]
CFGDI[11]inCELL_W[17].IMUX_IMUX_DELAY[10]
CFGDI[12]inCELL_W[17].IMUX_IMUX_DELAY[11]
CFGDI[13]inCELL_W[17].IMUX_IMUX_DELAY[12]
CFGDI[14]inCELL_W[18].IMUX_IMUX_DELAY[9]
CFGDI[15]inCELL_W[18].IMUX_IMUX_DELAY[10]
CFGDI[16]inCELL_W[18].IMUX_IMUX_DELAY[11]
CFGDI[17]inCELL_W[18].IMUX_IMUX_DELAY[12]
CFGDI[18]inCELL_W[19].IMUX_IMUX_DELAY[9]
CFGDI[19]inCELL_W[19].IMUX_IMUX_DELAY[10]
CFGDI[20]inCELL_W[19].IMUX_IMUX_DELAY[11]
CFGDI[21]inCELL_W[19].IMUX_IMUX_DELAY[12]
CFGDI[22]inCELL_W[18].IMUX_IMUX_DELAY[13]
CFGDI[23]inCELL_W[18].IMUX_IMUX_DELAY[14]
CFGDI[24]inCELL_W[18].IMUX_IMUX_DELAY[15]
CFGDI[25]inCELL_W[18].IMUX_IMUX_DELAY[16]
CFGDI[26]inCELL_W[17].IMUX_IMUX_DELAY[13]
CFGDI[27]inCELL_W[17].IMUX_IMUX_DELAY[14]
CFGDI[28]inCELL_W[17].IMUX_IMUX_DELAY[15]
CFGDI[29]inCELL_W[17].IMUX_IMUX_DELAY[16]
CFGDI[30]inCELL_W[16].IMUX_IMUX_DELAY[13]
CFGDI[31]inCELL_W[16].IMUX_IMUX_DELAY[14]
CFGDWADDR[0]inCELL_W[15].IMUX_IMUX_DELAY[17]
CFGDWADDR[1]inCELL_W[15].IMUX_IMUX_DELAY[18]
CFGDWADDR[2]inCELL_W[14].IMUX_IMUX_DELAY[17]
CFGDWADDR[3]inCELL_W[14].IMUX_IMUX_DELAY[18]
CFGDWADDR[4]inCELL_W[13].IMUX_IMUX_DELAY[9]
CFGDWADDR[5]inCELL_W[13].IMUX_IMUX_DELAY[10]
CFGDWADDR[6]inCELL_W[13].IMUX_IMUX_DELAY[11]
CFGDWADDR[7]inCELL_W[13].IMUX_IMUX_DELAY[12]
CFGDWADDR[8]inCELL_W[12].IMUX_IMUX_DELAY[6]
CFGDWADDR[9]inCELL_W[12].IMUX_IMUX_DELAY[8]
CFGBYTEENN[0]inCELL_W[16].IMUX_IMUX_DELAY[15]
CFGBYTEENN[1]inCELL_W[16].IMUX_IMUX_DELAY[16]
CFGBYTEENN[2]inCELL_W[15].IMUX_IMUX_DELAY[15]
CFGBYTEENN[3]inCELL_W[15].IMUX_IMUX_DELAY[16]
CFGWRENNinCELL_W[11].IMUX_IMUX_DELAY[2]
CFGRDENNinCELL_W[11].IMUX_IMUX_DELAY[4]
CFGWRREADONLYNinCELL_W[12].IMUX_IMUX_DELAY[12]
CFGWRRW1CASRWNinCELL_W[12].IMUX_IMUX_DELAY[10]
CFGTRNPENDINGNinCELL_E[6].IMUX_IMUX_DELAY[18]
CFGDSN[0]inCELL_E[6].IMUX_IMUX_DELAY[19]
CFGDSN[1]inCELL_E[7].IMUX_IMUX_DELAY[16]
CFGDSN[2]inCELL_E[7].IMUX_IMUX_DELAY[17]
CFGDSN[3]inCELL_E[7].IMUX_IMUX_DELAY[18]
CFGDSN[4]inCELL_E[7].IMUX_IMUX_DELAY[19]
CFGDSN[5]inCELL_E[8].IMUX_IMUX_DELAY[16]
CFGDSN[6]inCELL_E[8].IMUX_IMUX_DELAY[17]
CFGDSN[7]inCELL_E[8].IMUX_IMUX_DELAY[18]
CFGDSN[8]inCELL_E[8].IMUX_IMUX_DELAY[19]
CFGDSN[9]inCELL_E[9].IMUX_IMUX_DELAY[16]
CFGDSN[10]inCELL_E[9].IMUX_IMUX_DELAY[17]
CFGDSN[11]inCELL_E[9].IMUX_IMUX_DELAY[18]
CFGDSN[12]inCELL_E[9].IMUX_IMUX_DELAY[19]
CFGDSN[13]inCELL_E[13].IMUX_IMUX_DELAY[14]
CFGDSN[14]inCELL_E[13].IMUX_IMUX_DELAY[16]
CFGDSN[15]inCELL_E[13].IMUX_IMUX_DELAY[17]
CFGDSN[16]inCELL_E[13].IMUX_IMUX_DELAY[18]
CFGDSN[17]inCELL_E[14].IMUX_IMUX_DELAY[18]
CFGDSN[18]inCELL_E[15].IMUX_IMUX_DELAY[15]
CFGDSN[19]inCELL_E[15].IMUX_IMUX_DELAY[16]
CFGDSN[20]inCELL_E[15].IMUX_IMUX_DELAY[17]
CFGDSN[21]inCELL_E[15].IMUX_IMUX_DELAY[18]
CFGDSN[22]inCELL_E[16].IMUX_IMUX_DELAY[13]
CFGDSN[23]inCELL_E[16].IMUX_IMUX_DELAY[14]
CFGDSN[24]inCELL_E[16].IMUX_IMUX_DELAY[15]
CFGDSN[25]inCELL_E[16].IMUX_IMUX_DELAY[16]
CFGDSN[26]inCELL_E[17].IMUX_IMUX_DELAY[13]
CFGDSN[27]inCELL_E[17].IMUX_IMUX_DELAY[14]
CFGDSN[28]inCELL_E[17].IMUX_IMUX_DELAY[15]
CFGDSN[29]inCELL_E[17].IMUX_IMUX_DELAY[16]
CFGDSN[30]inCELL_E[18].IMUX_IMUX_DELAY[13]
CFGDSN[31]inCELL_E[18].IMUX_IMUX_DELAY[14]
CFGDSN[32]inCELL_E[18].IMUX_IMUX_DELAY[15]
CFGDSN[33]inCELL_E[18].IMUX_IMUX_DELAY[16]
CFGDSN[34]inCELL_E[19].IMUX_IMUX_DELAY[13]
CFGDSN[35]inCELL_E[19].IMUX_IMUX_DELAY[14]
CFGDSN[36]inCELL_E[19].IMUX_IMUX_DELAY[15]
CFGDSN[37]inCELL_E[19].IMUX_IMUX_DELAY[16]
CFGDSN[38]inCELL_W[19].IMUX_IMUX_DELAY[17]
CFGDSN[39]inCELL_W[19].IMUX_IMUX_DELAY[18]
CFGDSN[40]inCELL_W[19].IMUX_IMUX_DELAY[19]
CFGDSN[41]inCELL_W[19].IMUX_IMUX_DELAY[20]
CFGDSN[42]inCELL_W[18].IMUX_IMUX_DELAY[21]
CFGDSN[43]inCELL_W[17].IMUX_IMUX_DELAY[21]
CFGDSN[44]inCELL_W[16].IMUX_IMUX_DELAY[21]
CFGDSN[45]inCELL_W[13].IMUX_IMUX_DELAY[18]
CFGDSN[46]inCELL_W[9].IMUX_IMUX_DELAY[16]
CFGDSN[47]inCELL_W[9].IMUX_IMUX_DELAY[17]
CFGDSN[48]inCELL_W[9].IMUX_IMUX_DELAY[18]
CFGDSN[49]inCELL_W[9].IMUX_IMUX_DELAY[19]
CFGDSN[50]inCELL_W[8].IMUX_IMUX_DELAY[16]
CFGDSN[51]inCELL_W[8].IMUX_IMUX_DELAY[17]
CFGDSN[52]inCELL_W[8].IMUX_IMUX_DELAY[18]
CFGDSN[53]inCELL_W[8].IMUX_IMUX_DELAY[19]
CFGDSN[54]inCELL_W[7].IMUX_IMUX_DELAY[16]
CFGDSN[55]inCELL_W[7].IMUX_IMUX_DELAY[17]
CFGDSN[56]inCELL_W[7].IMUX_IMUX_DELAY[18]
CFGDSN[57]inCELL_W[7].IMUX_IMUX_DELAY[19]
CFGDSN[58]inCELL_W[6].IMUX_IMUX_DELAY[16]
CFGDSN[59]inCELL_W[6].IMUX_IMUX_DELAY[17]
CFGDSN[60]inCELL_W[6].IMUX_IMUX_DELAY[18]
CFGDSN[61]inCELL_W[6].IMUX_IMUX_DELAY[19]
CFGDSN[62]inCELL_W[5].IMUX_IMUX_DELAY[18]
CFGDSN[63]inCELL_W[3].IMUX_IMUX_DELAY[18]
CFGPMDIRECTASPML1NinCELL_E[5].IMUX_IMUX_DELAY[16]
CFGPMSENDPMACKNinCELL_E[5].IMUX_IMUX_DELAY[18]
CFGPMSENDPMETONinCELL_E[6].IMUX_IMUX_DELAY[17]
CFGPMSENDPMNAKNinCELL_E[6].IMUX_IMUX_DELAY[16]
CFGPMTURNOFFOKNinCELL_E[5].IMUX_IMUX_DELAY[17]
CFGPMWAKENinCELL_E[5].IMUX_IMUX_DELAY[15]
CFGDSBUSNUMBER[0]inCELL_W[0].IMUX_IMUX_DELAY[10]
CFGDSBUSNUMBER[1]inCELL_W[0].IMUX_IMUX_DELAY[12]
CFGDSBUSNUMBER[2]inCELL_W[0].IMUX_IMUX_DELAY[14]
CFGDSBUSNUMBER[3]inCELL_W[0].IMUX_IMUX_DELAY[16]
CFGDSBUSNUMBER[4]inCELL_E[0].IMUX_IMUX_DELAY[10]
CFGDSBUSNUMBER[5]inCELL_E[0].IMUX_IMUX_DELAY[12]
CFGDSBUSNUMBER[6]inCELL_E[0].IMUX_IMUX_DELAY[14]
CFGDSBUSNUMBER[7]inCELL_E[0].IMUX_IMUX_DELAY[16]
CFGDSDEVICENUMBER[0]inCELL_E[1].IMUX_IMUX_DELAY[10]
CFGDSDEVICENUMBER[1]inCELL_E[1].IMUX_IMUX_DELAY[12]
CFGDSDEVICENUMBER[2]inCELL_E[1].IMUX_IMUX_DELAY[14]
CFGDSDEVICENUMBER[3]inCELL_E[1].IMUX_IMUX_DELAY[16]
CFGDSDEVICENUMBER[4]inCELL_E[2].IMUX_IMUX_DELAY[14]
CFGDSFUNCTIONNUMBER[0]inCELL_E[2].IMUX_IMUX_DELAY[16]
CFGDSFUNCTIONNUMBER[1]inCELL_E[2].IMUX_IMUX_DELAY[18]
CFGDSFUNCTIONNUMBER[2]inCELL_E[2].IMUX_IMUX_DELAY[19]
CFGINTERRUPTNinCELL_W[3].IMUX_IMUX_DELAY[16]
CFGINTERRUPTASSERTNinCELL_W[1].IMUX_IMUX_DELAY[16]
CFGINTERRUPTDI[0]inCELL_W[3].IMUX_IMUX_DELAY[17]
CFGINTERRUPTDI[1]inCELL_W[2].IMUX_IMUX_DELAY[14]
CFGINTERRUPTDI[2]inCELL_W[2].IMUX_IMUX_DELAY[16]
CFGINTERRUPTDI[3]inCELL_W[2].IMUX_IMUX_DELAY[18]
CFGINTERRUPTDI[4]inCELL_W[2].IMUX_IMUX_DELAY[19]
CFGINTERRUPTDI[5]inCELL_W[1].IMUX_IMUX_DELAY[10]
CFGINTERRUPTDI[6]inCELL_W[1].IMUX_IMUX_DELAY[12]
CFGINTERRUPTDI[7]inCELL_W[1].IMUX_IMUX_DELAY[14]
CFGERRECRCNinCELL_W[10].IMUX_IMUX_DELAY[2]
CFGERRURNinCELL_W[11].IMUX_IMUX_DELAY[8]
CFGERRCPLTIMEOUTNinCELL_W[10].IMUX_IMUX_DELAY[4]
CFGERRCPLUNEXPECTNinCELL_W[10].IMUX_IMUX_DELAY[8]
CFGERRCPLABORTNinCELL_W[10].IMUX_IMUX_DELAY[6]
CFGERRPOSTEDNinCELL_W[9].IMUX_IMUX_DELAY[9]
CFGERRCORNinCELL_W[11].IMUX_IMUX_DELAY[6]
CFGERRTLPCPLHEADER[0]inCELL_W[17].IMUX_IMUX_DELAY[20]
CFGERRTLPCPLHEADER[1]inCELL_W[16].IMUX_IMUX_DELAY[17]
CFGERRTLPCPLHEADER[2]inCELL_W[16].IMUX_IMUX_DELAY[18]
CFGERRTLPCPLHEADER[3]inCELL_W[16].IMUX_IMUX_DELAY[19]
CFGERRTLPCPLHEADER[4]inCELL_W[16].IMUX_IMUX_DELAY[20]
CFGERRTLPCPLHEADER[5]inCELL_W[15].IMUX_IMUX_DELAY[20]
CFGERRTLPCPLHEADER[6]inCELL_W[13].IMUX_IMUX_DELAY[13]
CFGERRTLPCPLHEADER[7]inCELL_W[13].IMUX_IMUX_DELAY[14]
CFGERRTLPCPLHEADER[8]inCELL_W[13].IMUX_IMUX_DELAY[16]
CFGERRTLPCPLHEADER[9]inCELL_W[13].IMUX_IMUX_DELAY[17]
CFGERRTLPCPLHEADER[10]inCELL_W[12].IMUX_IMUX_DELAY[14]
CFGERRTLPCPLHEADER[11]inCELL_W[12].IMUX_IMUX_DELAY[16]
CFGERRTLPCPLHEADER[12]inCELL_W[12].IMUX_IMUX_DELAY[18]
CFGERRTLPCPLHEADER[13]inCELL_W[12].IMUX_IMUX_DELAY[19]
CFGERRTLPCPLHEADER[14]inCELL_W[11].IMUX_IMUX_DELAY[10]
CFGERRTLPCPLHEADER[15]inCELL_W[11].IMUX_IMUX_DELAY[12]
CFGERRTLPCPLHEADER[16]inCELL_W[11].IMUX_IMUX_DELAY[14]
CFGERRTLPCPLHEADER[17]inCELL_W[11].IMUX_IMUX_DELAY[16]
CFGERRTLPCPLHEADER[18]inCELL_W[10].IMUX_IMUX_DELAY[10]
CFGERRTLPCPLHEADER[19]inCELL_W[10].IMUX_IMUX_DELAY[12]
CFGERRTLPCPLHEADER[20]inCELL_W[10].IMUX_IMUX_DELAY[14]
CFGERRTLPCPLHEADER[21]inCELL_W[10].IMUX_IMUX_DELAY[16]
CFGERRTLPCPLHEADER[22]inCELL_W[9].IMUX_IMUX_DELAY[12]
CFGERRTLPCPLHEADER[23]inCELL_W[9].IMUX_IMUX_DELAY[13]
CFGERRTLPCPLHEADER[24]inCELL_W[9].IMUX_IMUX_DELAY[14]
CFGERRTLPCPLHEADER[25]inCELL_W[9].IMUX_IMUX_DELAY[15]
CFGERRTLPCPLHEADER[26]inCELL_W[8].IMUX_IMUX_DELAY[12]
CFGERRTLPCPLHEADER[27]inCELL_W[8].IMUX_IMUX_DELAY[13]
CFGERRTLPCPLHEADER[28]inCELL_W[8].IMUX_IMUX_DELAY[14]
CFGERRTLPCPLHEADER[29]inCELL_W[8].IMUX_IMUX_DELAY[15]
CFGERRTLPCPLHEADER[30]inCELL_W[7].IMUX_IMUX_DELAY[12]
CFGERRTLPCPLHEADER[31]inCELL_W[7].IMUX_IMUX_DELAY[13]
CFGERRTLPCPLHEADER[32]inCELL_W[7].IMUX_IMUX_DELAY[14]
CFGERRTLPCPLHEADER[33]inCELL_W[7].IMUX_IMUX_DELAY[15]
CFGERRTLPCPLHEADER[34]inCELL_W[6].IMUX_IMUX_DELAY[12]
CFGERRTLPCPLHEADER[35]inCELL_W[6].IMUX_IMUX_DELAY[13]
CFGERRTLPCPLHEADER[36]inCELL_W[6].IMUX_IMUX_DELAY[14]
CFGERRTLPCPLHEADER[37]inCELL_W[6].IMUX_IMUX_DELAY[15]
CFGERRTLPCPLHEADER[38]inCELL_W[5].IMUX_IMUX_DELAY[14]
CFGERRTLPCPLHEADER[39]inCELL_W[5].IMUX_IMUX_DELAY[15]
CFGERRTLPCPLHEADER[40]inCELL_W[5].IMUX_IMUX_DELAY[16]
CFGERRTLPCPLHEADER[41]inCELL_W[5].IMUX_IMUX_DELAY[17]
CFGERRTLPCPLHEADER[42]inCELL_W[4].IMUX_IMUX_DELAY[13]
CFGERRTLPCPLHEADER[43]inCELL_W[4].IMUX_IMUX_DELAY[14]
CFGERRTLPCPLHEADER[44]inCELL_W[4].IMUX_IMUX_DELAY[16]
CFGERRTLPCPLHEADER[45]inCELL_W[4].IMUX_IMUX_DELAY[17]
CFGERRTLPCPLHEADER[46]inCELL_W[3].IMUX_IMUX_DELAY[13]
CFGERRTLPCPLHEADER[47]inCELL_W[3].IMUX_IMUX_DELAY[14]
CFGERRLOCKEDNinCELL_W[9].IMUX_IMUX_DELAY[10]
CFGERRACSNinCELL_W[9].IMUX_IMUX_DELAY[8]
CFGERRAERHEADERLOG[0]inCELL_W[9].IMUX_IMUX_DELAY[11]
CFGERRAERHEADERLOG[1]inCELL_W[8].IMUX_IMUX_DELAY[8]
CFGERRAERHEADERLOG[2]inCELL_W[8].IMUX_IMUX_DELAY[9]
CFGERRAERHEADERLOG[3]inCELL_W[8].IMUX_IMUX_DELAY[10]
CFGERRAERHEADERLOG[4]inCELL_W[8].IMUX_IMUX_DELAY[11]
CFGERRAERHEADERLOG[5]inCELL_W[7].IMUX_IMUX_DELAY[8]
CFGERRAERHEADERLOG[6]inCELL_W[7].IMUX_IMUX_DELAY[9]
CFGERRAERHEADERLOG[7]inCELL_W[7].IMUX_IMUX_DELAY[10]
CFGERRAERHEADERLOG[8]inCELL_W[7].IMUX_IMUX_DELAY[11]
CFGERRAERHEADERLOG[9]inCELL_W[6].IMUX_IMUX_DELAY[8]
CFGERRAERHEADERLOG[10]inCELL_W[6].IMUX_IMUX_DELAY[9]
CFGERRAERHEADERLOG[11]inCELL_W[6].IMUX_IMUX_DELAY[10]
CFGERRAERHEADERLOG[12]inCELL_W[6].IMUX_IMUX_DELAY[11]
CFGERRAERHEADERLOG[13]inCELL_W[5].IMUX_IMUX_DELAY[9]
CFGERRAERHEADERLOG[14]inCELL_W[5].IMUX_IMUX_DELAY[10]
CFGERRAERHEADERLOG[15]inCELL_W[5].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[16]inCELL_W[5].IMUX_IMUX_DELAY[13]
CFGERRAERHEADERLOG[17]inCELL_W[4].IMUX_IMUX_DELAY[8]
CFGERRAERHEADERLOG[18]inCELL_W[4].IMUX_IMUX_DELAY[9]
CFGERRAERHEADERLOG[19]inCELL_W[4].IMUX_IMUX_DELAY[10]
CFGERRAERHEADERLOG[20]inCELL_W[4].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[21]inCELL_W[3].IMUX_IMUX_DELAY[9]
CFGERRAERHEADERLOG[22]inCELL_W[3].IMUX_IMUX_DELAY[10]
CFGERRAERHEADERLOG[23]inCELL_W[3].IMUX_IMUX_DELAY[11]
CFGERRAERHEADERLOG[24]inCELL_W[3].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[25]inCELL_W[2].IMUX_IMUX_DELAY[6]
CFGERRAERHEADERLOG[26]inCELL_W[2].IMUX_IMUX_DELAY[8]
CFGERRAERHEADERLOG[27]inCELL_W[2].IMUX_IMUX_DELAY[10]
CFGERRAERHEADERLOG[28]inCELL_W[2].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[29]inCELL_W[1].IMUX_IMUX_DELAY[2]
CFGERRAERHEADERLOG[30]inCELL_W[1].IMUX_IMUX_DELAY[4]
CFGERRAERHEADERLOG[31]inCELL_W[1].IMUX_IMUX_DELAY[6]
CFGERRAERHEADERLOG[32]inCELL_W[1].IMUX_IMUX_DELAY[8]
CFGERRAERHEADERLOG[33]inCELL_W[0].IMUX_IMUX_DELAY[2]
CFGERRAERHEADERLOG[34]inCELL_W[0].IMUX_IMUX_DELAY[4]
CFGERRAERHEADERLOG[35]inCELL_W[0].IMUX_IMUX_DELAY[6]
CFGERRAERHEADERLOG[36]inCELL_W[0].IMUX_IMUX_DELAY[8]
CFGERRAERHEADERLOG[37]inCELL_E[0].IMUX_IMUX_DELAY[2]
CFGERRAERHEADERLOG[38]inCELL_E[0].IMUX_IMUX_DELAY[4]
CFGERRAERHEADERLOG[39]inCELL_E[0].IMUX_IMUX_DELAY[6]
CFGERRAERHEADERLOG[40]inCELL_E[0].IMUX_IMUX_DELAY[8]
CFGERRAERHEADERLOG[41]inCELL_E[1].IMUX_IMUX_DELAY[2]
CFGERRAERHEADERLOG[42]inCELL_E[1].IMUX_IMUX_DELAY[4]
CFGERRAERHEADERLOG[43]inCELL_E[1].IMUX_IMUX_DELAY[6]
CFGERRAERHEADERLOG[44]inCELL_E[1].IMUX_IMUX_DELAY[8]
CFGERRAERHEADERLOG[45]inCELL_E[2].IMUX_IMUX_DELAY[6]
CFGERRAERHEADERLOG[46]inCELL_E[2].IMUX_IMUX_DELAY[8]
CFGERRAERHEADERLOG[47]inCELL_E[2].IMUX_IMUX_DELAY[10]
CFGERRAERHEADERLOG[48]inCELL_E[2].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[49]inCELL_E[3].IMUX_IMUX_DELAY[10]
CFGERRAERHEADERLOG[50]inCELL_E[3].IMUX_IMUX_DELAY[11]
CFGERRAERHEADERLOG[51]inCELL_E[3].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[52]inCELL_E[3].IMUX_IMUX_DELAY[13]
CFGERRAERHEADERLOG[53]inCELL_E[4].IMUX_IMUX_DELAY[8]
CFGERRAERHEADERLOG[54]inCELL_E[4].IMUX_IMUX_DELAY[9]
CFGERRAERHEADERLOG[55]inCELL_E[4].IMUX_IMUX_DELAY[10]
CFGERRAERHEADERLOG[56]inCELL_E[4].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[57]inCELL_E[5].IMUX_IMUX_DELAY[10]
CFGERRAERHEADERLOG[58]inCELL_E[5].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[59]inCELL_E[5].IMUX_IMUX_DELAY[13]
CFGERRAERHEADERLOG[60]inCELL_E[5].IMUX_IMUX_DELAY[14]
CFGERRAERHEADERLOG[61]inCELL_E[6].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[62]inCELL_E[6].IMUX_IMUX_DELAY[13]
CFGERRAERHEADERLOG[63]inCELL_E[6].IMUX_IMUX_DELAY[14]
CFGERRAERHEADERLOG[64]inCELL_E[6].IMUX_IMUX_DELAY[15]
CFGERRAERHEADERLOG[65]inCELL_E[7].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[66]inCELL_E[7].IMUX_IMUX_DELAY[13]
CFGERRAERHEADERLOG[67]inCELL_E[7].IMUX_IMUX_DELAY[14]
CFGERRAERHEADERLOG[68]inCELL_E[7].IMUX_IMUX_DELAY[15]
CFGERRAERHEADERLOG[69]inCELL_E[8].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[70]inCELL_E[8].IMUX_IMUX_DELAY[13]
CFGERRAERHEADERLOG[71]inCELL_E[8].IMUX_IMUX_DELAY[14]
CFGERRAERHEADERLOG[72]inCELL_E[8].IMUX_IMUX_DELAY[15]
CFGERRAERHEADERLOG[73]inCELL_E[9].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[74]inCELL_E[9].IMUX_IMUX_DELAY[13]
CFGERRAERHEADERLOG[75]inCELL_E[9].IMUX_IMUX_DELAY[14]
CFGERRAERHEADERLOG[76]inCELL_E[9].IMUX_IMUX_DELAY[15]
CFGERRAERHEADERLOG[77]inCELL_E[10].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[78]inCELL_E[10].IMUX_IMUX_DELAY[14]
CFGERRAERHEADERLOG[79]inCELL_E[10].IMUX_IMUX_DELAY[16]
CFGERRAERHEADERLOG[80]inCELL_E[10].IMUX_IMUX_DELAY[18]
CFGERRAERHEADERLOG[81]inCELL_E[11].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[82]inCELL_E[11].IMUX_IMUX_DELAY[14]
CFGERRAERHEADERLOG[83]inCELL_E[11].IMUX_IMUX_DELAY[16]
CFGERRAERHEADERLOG[84]inCELL_E[11].IMUX_IMUX_DELAY[18]
CFGERRAERHEADERLOG[85]inCELL_E[12].IMUX_IMUX_DELAY[16]
CFGERRAERHEADERLOG[86]inCELL_E[12].IMUX_IMUX_DELAY[18]
CFGERRAERHEADERLOG[87]inCELL_E[12].IMUX_IMUX_DELAY[19]
CFGERRAERHEADERLOG[88]inCELL_E[12].IMUX_IMUX_DELAY[20]
CFGERRAERHEADERLOG[89]inCELL_E[13].IMUX_IMUX_DELAY[10]
CFGERRAERHEADERLOG[90]inCELL_E[13].IMUX_IMUX_DELAY[11]
CFGERRAERHEADERLOG[91]inCELL_E[13].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[92]inCELL_E[13].IMUX_IMUX_DELAY[13]
CFGERRAERHEADERLOG[93]inCELL_E[14].IMUX_IMUX_DELAY[13]
CFGERRAERHEADERLOG[94]inCELL_E[14].IMUX_IMUX_DELAY[14]
CFGERRAERHEADERLOG[95]inCELL_E[14].IMUX_IMUX_DELAY[16]
CFGERRAERHEADERLOG[96]inCELL_E[14].IMUX_IMUX_DELAY[17]
CFGERRAERHEADERLOG[97]inCELL_E[15].IMUX_IMUX_DELAY[10]
CFGERRAERHEADERLOG[98]inCELL_E[15].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[99]inCELL_E[15].IMUX_IMUX_DELAY[13]
CFGERRAERHEADERLOG[100]inCELL_E[15].IMUX_IMUX_DELAY[14]
CFGERRAERHEADERLOG[101]inCELL_E[16].IMUX_IMUX_DELAY[9]
CFGERRAERHEADERLOG[102]inCELL_E[16].IMUX_IMUX_DELAY[10]
CFGERRAERHEADERLOG[103]inCELL_E[16].IMUX_IMUX_DELAY[11]
CFGERRAERHEADERLOG[104]inCELL_E[16].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[105]inCELL_E[17].IMUX_IMUX_DELAY[9]
CFGERRAERHEADERLOG[106]inCELL_E[17].IMUX_IMUX_DELAY[10]
CFGERRAERHEADERLOG[107]inCELL_E[17].IMUX_IMUX_DELAY[11]
CFGERRAERHEADERLOG[108]inCELL_E[17].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[109]inCELL_E[18].IMUX_IMUX_DELAY[9]
CFGERRAERHEADERLOG[110]inCELL_E[18].IMUX_IMUX_DELAY[10]
CFGERRAERHEADERLOG[111]inCELL_E[18].IMUX_IMUX_DELAY[11]
CFGERRAERHEADERLOG[112]inCELL_E[18].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[113]inCELL_E[19].IMUX_IMUX_DELAY[9]
CFGERRAERHEADERLOG[114]inCELL_E[19].IMUX_IMUX_DELAY[10]
CFGERRAERHEADERLOG[115]inCELL_E[19].IMUX_IMUX_DELAY[11]
CFGERRAERHEADERLOG[116]inCELL_E[19].IMUX_IMUX_DELAY[12]
CFGERRAERHEADERLOG[117]inCELL_W[19].IMUX_IMUX_DELAY[13]
CFGERRAERHEADERLOG[118]inCELL_W[19].IMUX_IMUX_DELAY[14]
CFGERRAERHEADERLOG[119]inCELL_W[19].IMUX_IMUX_DELAY[15]
CFGERRAERHEADERLOG[120]inCELL_W[19].IMUX_IMUX_DELAY[16]
CFGERRAERHEADERLOG[121]inCELL_W[18].IMUX_IMUX_DELAY[17]
CFGERRAERHEADERLOG[122]inCELL_W[18].IMUX_IMUX_DELAY[18]
CFGERRAERHEADERLOG[123]inCELL_W[18].IMUX_IMUX_DELAY[19]
CFGERRAERHEADERLOG[124]inCELL_W[18].IMUX_IMUX_DELAY[20]
CFGERRAERHEADERLOG[125]inCELL_W[17].IMUX_IMUX_DELAY[17]
CFGERRAERHEADERLOG[126]inCELL_W[17].IMUX_IMUX_DELAY[18]
CFGERRAERHEADERLOG[127]inCELL_W[17].IMUX_IMUX_DELAY[19]
CFGPORTNUMBER[0]inCELL_E[3].IMUX_IMUX_DELAY[14]
CFGPORTNUMBER[1]inCELL_E[3].IMUX_IMUX_DELAY[16]
CFGPORTNUMBER[2]inCELL_E[3].IMUX_IMUX_DELAY[17]
CFGPORTNUMBER[3]inCELL_E[3].IMUX_IMUX_DELAY[18]
CFGPORTNUMBER[4]inCELL_E[4].IMUX_IMUX_DELAY[13]
CFGPORTNUMBER[5]inCELL_E[4].IMUX_IMUX_DELAY[14]
CFGPORTNUMBER[6]inCELL_E[4].IMUX_IMUX_DELAY[16]
CFGPORTNUMBER[7]inCELL_E[4].IMUX_IMUX_DELAY[17]
DRPCLKinCELL_E[8].IMUX_CLK[0]
DRPDENinCELL_E[6].IMUX_IMUX_DELAY[20]
DRPDWEinCELL_E[7].IMUX_IMUX_DELAY[20]
DRPDADDR[0]inCELL_E[8].IMUX_IMUX_DELAY[20]
DRPDADDR[1]inCELL_E[9].IMUX_IMUX_DELAY[20]
DRPDADDR[2]inCELL_E[9].IMUX_IMUX_DELAY[21]
DRPDADDR[3]inCELL_E[9].IMUX_IMUX_DELAY[22]
DRPDADDR[4]inCELL_E[13].IMUX_IMUX_DELAY[19]
DRPDADDR[5]inCELL_E[15].IMUX_IMUX_DELAY[20]
DRPDADDR[6]inCELL_E[16].IMUX_IMUX_DELAY[17]
DRPDADDR[7]inCELL_E[16].IMUX_IMUX_DELAY[18]
DRPDADDR[8]inCELL_E[16].IMUX_IMUX_DELAY[19]
DRPDI[0]inCELL_E[16].IMUX_IMUX_DELAY[20]
DRPDI[1]inCELL_E[17].IMUX_IMUX_DELAY[17]
DRPDI[2]inCELL_E[17].IMUX_IMUX_DELAY[18]
DRPDI[3]inCELL_E[17].IMUX_IMUX_DELAY[19]
DRPDI[4]inCELL_E[17].IMUX_IMUX_DELAY[20]
DRPDI[5]inCELL_E[18].IMUX_IMUX_DELAY[17]
DRPDI[6]inCELL_E[18].IMUX_IMUX_DELAY[18]
DRPDI[7]inCELL_E[18].IMUX_IMUX_DELAY[19]
DRPDI[8]inCELL_E[18].IMUX_IMUX_DELAY[20]
DRPDI[9]inCELL_E[19].IMUX_IMUX_DELAY[17]
DRPDI[10]inCELL_E[19].IMUX_IMUX_DELAY[18]
DRPDI[11]inCELL_E[19].IMUX_IMUX_DELAY[19]
DRPDI[12]inCELL_E[19].IMUX_IMUX_DELAY[20]
DRPDI[13]inCELL_W[19].IMUX_IMUX_DELAY[21]
DRPDI[14]inCELL_W[9].IMUX_IMUX_DELAY[20]
DRPDI[15]inCELL_W[8].IMUX_IMUX_DELAY[20]
MIMRXRDATA[0]inCELL_E[9].IMUX_IMUX_DELAY[6]
MIMRXRDATA[1]inCELL_E[9].IMUX_IMUX_DELAY[7]
MIMRXRDATA[2]inCELL_E[10].IMUX_IMUX_DELAY[2]
MIMRXRDATA[3]inCELL_E[10].IMUX_IMUX_DELAY[4]
MIMRXRDATA[4]inCELL_E[10].IMUX_IMUX_DELAY[6]
MIMRXRDATA[5]inCELL_E[10].IMUX_IMUX_DELAY[8]
MIMRXRDATA[6]inCELL_E[11].IMUX_IMUX_DELAY[2]
MIMRXRDATA[7]inCELL_E[11].IMUX_IMUX_DELAY[4]
MIMRXRDATA[8]inCELL_E[11].IMUX_IMUX_DELAY[6]
MIMRXRDATA[9]inCELL_E[11].IMUX_IMUX_DELAY[8]
MIMRXRDATA[10]inCELL_E[12].IMUX_IMUX_DELAY[6]
MIMRXRDATA[11]inCELL_E[12].IMUX_IMUX_DELAY[8]
MIMRXRDATA[12]inCELL_E[12].IMUX_IMUX_DELAY[10]
MIMRXRDATA[13]inCELL_E[12].IMUX_IMUX_DELAY[12]
MIMRXRDATA[14]inCELL_E[13].IMUX_IMUX_DELAY[5]
MIMRXRDATA[15]inCELL_E[13].IMUX_IMUX_DELAY[6]
MIMRXRDATA[16]inCELL_E[13].IMUX_IMUX_DELAY[7]
MIMRXRDATA[17]inCELL_E[13].IMUX_IMUX_DELAY[8]
MIMRXRDATA[18]inCELL_E[14].IMUX_IMUX_DELAY[6]
MIMRXRDATA[19]inCELL_E[14].IMUX_IMUX_DELAY[8]
MIMRXRDATA[20]inCELL_E[14].IMUX_IMUX_DELAY[9]
MIMRXRDATA[21]inCELL_E[14].IMUX_IMUX_DELAY[10]
MIMRXRDATA[22]inCELL_E[15].IMUX_IMUX_DELAY[4]
MIMRXRDATA[23]inCELL_E[15].IMUX_IMUX_DELAY[6]
MIMRXRDATA[24]inCELL_E[15].IMUX_IMUX_DELAY[7]
MIMRXRDATA[25]inCELL_E[15].IMUX_IMUX_DELAY[8]
MIMRXRDATA[26]inCELL_E[16].IMUX_IMUX_DELAY[4]
MIMRXRDATA[27]inCELL_E[16].IMUX_IMUX_DELAY[5]
MIMRXRDATA[28]inCELL_E[16].IMUX_IMUX_DELAY[6]
MIMRXRDATA[29]inCELL_E[16].IMUX_IMUX_DELAY[7]
MIMRXRDATA[30]inCELL_E[17].IMUX_IMUX_DELAY[4]
MIMRXRDATA[31]inCELL_E[17].IMUX_IMUX_DELAY[5]
MIMRXRDATA[32]inCELL_E[17].IMUX_IMUX_DELAY[6]
MIMRXRDATA[33]inCELL_E[17].IMUX_IMUX_DELAY[7]
MIMRXRDATA[34]inCELL_E[18].IMUX_IMUX_DELAY[4]
MIMRXRDATA[35]inCELL_E[18].IMUX_IMUX_DELAY[5]
MIMRXRDATA[36]inCELL_E[18].IMUX_IMUX_DELAY[6]
MIMRXRDATA[37]inCELL_E[18].IMUX_IMUX_DELAY[7]
MIMRXRDATA[38]inCELL_E[19].IMUX_IMUX_DELAY[4]
MIMRXRDATA[39]inCELL_E[19].IMUX_IMUX_DELAY[5]
MIMRXRDATA[40]inCELL_E[19].IMUX_IMUX_DELAY[6]
MIMRXRDATA[41]inCELL_E[19].IMUX_IMUX_DELAY[7]
MIMRXRDATA[42]inCELL_W[19].IMUX_IMUX_DELAY[4]
MIMRXRDATA[43]inCELL_W[19].IMUX_IMUX_DELAY[5]
MIMRXRDATA[44]inCELL_W[19].IMUX_IMUX_DELAY[6]
MIMRXRDATA[45]inCELL_W[19].IMUX_IMUX_DELAY[7]
MIMRXRDATA[46]inCELL_W[18].IMUX_IMUX_DELAY[4]
MIMRXRDATA[47]inCELL_W[18].IMUX_IMUX_DELAY[5]
MIMRXRDATA[48]inCELL_W[18].IMUX_IMUX_DELAY[6]
MIMRXRDATA[49]inCELL_W[18].IMUX_IMUX_DELAY[7]
MIMRXRDATA[50]inCELL_W[17].IMUX_IMUX_DELAY[4]
MIMRXRDATA[51]inCELL_W[17].IMUX_IMUX_DELAY[5]
MIMRXRDATA[52]inCELL_W[17].IMUX_IMUX_DELAY[6]
MIMRXRDATA[53]inCELL_W[17].IMUX_IMUX_DELAY[7]
MIMRXRDATA[54]inCELL_W[16].IMUX_IMUX_DELAY[4]
MIMRXRDATA[55]inCELL_W[16].IMUX_IMUX_DELAY[5]
MIMRXRDATA[56]inCELL_W[16].IMUX_IMUX_DELAY[6]
MIMRXRDATA[57]inCELL_W[16].IMUX_IMUX_DELAY[7]
MIMRXRDATA[58]inCELL_W[15].IMUX_IMUX_DELAY[4]
MIMRXRDATA[59]inCELL_W[15].IMUX_IMUX_DELAY[6]
MIMRXRDATA[60]inCELL_W[15].IMUX_IMUX_DELAY[7]
MIMRXRDATA[61]inCELL_W[15].IMUX_IMUX_DELAY[8]
MIMRXRDATA[62]inCELL_W[14].IMUX_IMUX_DELAY[6]
MIMRXRDATA[63]inCELL_W[14].IMUX_IMUX_DELAY[8]
MIMRXRDATA[64]inCELL_W[14].IMUX_IMUX_DELAY[9]
MIMRXRDATA[65]inCELL_W[14].IMUX_IMUX_DELAY[10]
MIMRXRDATA[66]inCELL_W[13].IMUX_IMUX_DELAY[5]
MIMRXRDATA[67]inCELL_W[13].IMUX_IMUX_DELAY[6]
MIMTXRDATA[0]inCELL_W[14].IMUX_IMUX_DELAY[0]
MIMTXRDATA[1]inCELL_W[14].IMUX_IMUX_DELAY[2]
MIMTXRDATA[2]inCELL_W[14].IMUX_IMUX_DELAY[4]
MIMTXRDATA[3]inCELL_W[14].IMUX_IMUX_DELAY[5]
MIMTXRDATA[4]inCELL_W[13].IMUX_IMUX_DELAY[0]
MIMTXRDATA[5]inCELL_W[13].IMUX_IMUX_DELAY[2]
MIMTXRDATA[6]inCELL_W[13].IMUX_IMUX_DELAY[3]
MIMTXRDATA[7]inCELL_W[13].IMUX_IMUX_DELAY[4]
MIMTXRDATA[8]inCELL_W[12].IMUX_IMUX_DELAY[0]
MIMTXRDATA[9]inCELL_W[12].IMUX_IMUX_DELAY[2]
MIMTXRDATA[10]inCELL_W[12].IMUX_IMUX_DELAY[4]
MIMTXRDATA[11]inCELL_W[11].IMUX_IMUX_DELAY[0]
MIMTXRDATA[12]inCELL_W[10].IMUX_IMUX_DELAY[0]
MIMTXRDATA[13]inCELL_W[9].IMUX_IMUX_DELAY[0]
MIMTXRDATA[14]inCELL_W[9].IMUX_IMUX_DELAY[1]
MIMTXRDATA[15]inCELL_W[9].IMUX_IMUX_DELAY[2]
MIMTXRDATA[16]inCELL_W[9].IMUX_IMUX_DELAY[3]
MIMTXRDATA[17]inCELL_W[8].IMUX_IMUX_DELAY[0]
MIMTXRDATA[18]inCELL_W[8].IMUX_IMUX_DELAY[1]
MIMTXRDATA[19]inCELL_W[8].IMUX_IMUX_DELAY[2]
MIMTXRDATA[20]inCELL_W[8].IMUX_IMUX_DELAY[3]
MIMTXRDATA[21]inCELL_W[7].IMUX_IMUX_DELAY[0]
MIMTXRDATA[22]inCELL_W[7].IMUX_IMUX_DELAY[1]
MIMTXRDATA[23]inCELL_W[7].IMUX_IMUX_DELAY[2]
MIMTXRDATA[24]inCELL_W[7].IMUX_IMUX_DELAY[3]
MIMTXRDATA[25]inCELL_W[6].IMUX_IMUX_DELAY[0]
MIMTXRDATA[26]inCELL_W[6].IMUX_IMUX_DELAY[1]
MIMTXRDATA[27]inCELL_W[6].IMUX_IMUX_DELAY[2]
MIMTXRDATA[28]inCELL_W[6].IMUX_IMUX_DELAY[3]
MIMTXRDATA[29]inCELL_W[5].IMUX_IMUX_DELAY[0]
MIMTXRDATA[30]inCELL_W[5].IMUX_IMUX_DELAY[1]
MIMTXRDATA[31]inCELL_W[5].IMUX_IMUX_DELAY[2]
MIMTXRDATA[32]inCELL_W[5].IMUX_IMUX_DELAY[3]
MIMTXRDATA[33]inCELL_W[4].IMUX_IMUX_DELAY[0]
MIMTXRDATA[34]inCELL_W[4].IMUX_IMUX_DELAY[2]
MIMTXRDATA[35]inCELL_W[4].IMUX_IMUX_DELAY[4]
MIMTXRDATA[36]inCELL_W[4].IMUX_IMUX_DELAY[5]
MIMTXRDATA[37]inCELL_W[3].IMUX_IMUX_DELAY[0]
MIMTXRDATA[38]inCELL_W[3].IMUX_IMUX_DELAY[2]
MIMTXRDATA[39]inCELL_W[3].IMUX_IMUX_DELAY[3]
MIMTXRDATA[40]inCELL_W[3].IMUX_IMUX_DELAY[4]
MIMTXRDATA[41]inCELL_W[2].IMUX_IMUX_DELAY[0]
MIMTXRDATA[42]inCELL_W[2].IMUX_IMUX_DELAY[2]
MIMTXRDATA[43]inCELL_W[2].IMUX_IMUX_DELAY[4]
MIMTXRDATA[44]inCELL_W[1].IMUX_IMUX_DELAY[0]
MIMTXRDATA[45]inCELL_W[0].IMUX_IMUX_DELAY[0]
MIMTXRDATA[46]inCELL_E[3].IMUX_IMUX_DELAY[5]
MIMTXRDATA[47]inCELL_E[3].IMUX_IMUX_DELAY[6]
MIMTXRDATA[48]inCELL_E[3].IMUX_IMUX_DELAY[7]
MIMTXRDATA[49]inCELL_E[3].IMUX_IMUX_DELAY[8]
MIMTXRDATA[50]inCELL_E[4].IMUX_IMUX_DELAY[6]
MIMTXRDATA[51]inCELL_E[5].IMUX_IMUX_DELAY[4]
MIMTXRDATA[52]inCELL_E[5].IMUX_IMUX_DELAY[6]
MIMTXRDATA[53]inCELL_E[5].IMUX_IMUX_DELAY[7]
MIMTXRDATA[54]inCELL_E[5].IMUX_IMUX_DELAY[8]
MIMTXRDATA[55]inCELL_E[6].IMUX_IMUX_DELAY[4]
MIMTXRDATA[56]inCELL_E[6].IMUX_IMUX_DELAY[5]
MIMTXRDATA[57]inCELL_E[6].IMUX_IMUX_DELAY[6]
MIMTXRDATA[58]inCELL_E[6].IMUX_IMUX_DELAY[7]
MIMTXRDATA[59]inCELL_E[7].IMUX_IMUX_DELAY[4]
MIMTXRDATA[60]inCELL_E[7].IMUX_IMUX_DELAY[5]
MIMTXRDATA[61]inCELL_E[7].IMUX_IMUX_DELAY[6]
MIMTXRDATA[62]inCELL_E[7].IMUX_IMUX_DELAY[7]
MIMTXRDATA[63]inCELL_E[8].IMUX_IMUX_DELAY[4]
MIMTXRDATA[64]inCELL_E[8].IMUX_IMUX_DELAY[5]
MIMTXRDATA[65]inCELL_E[8].IMUX_IMUX_DELAY[6]
MIMTXRDATA[66]inCELL_E[8].IMUX_IMUX_DELAY[7]
MIMTXRDATA[67]inCELL_E[9].IMUX_IMUX_DELAY[4]
MIMTXRDATA[68]inCELL_E[9].IMUX_IMUX_DELAY[5]
PIPECLKinCELL_E[9].IMUX_CLK[1]
PIPERX0CHANISALIGNEDinCELL_E[13].IMUX_IMUX_DELAY[21]
PIPERX0CHARISK[0]inCELL_E[13].IMUX_IMUX_DELAY[23]
PIPERX0CHARISK[1]inCELL_E[12].IMUX_IMUX_DELAY[1]
PIPERX0DATA[0]inCELL_E[10].IMUX_IMUX_DELAY[3]
PIPERX0DATA[1]inCELL_E[10].IMUX_IMUX_DELAY[5]
PIPERX0DATA[2]inCELL_E[10].IMUX_IMUX_DELAY[15]
PIPERX0DATA[3]inCELL_E[10].IMUX_IMUX_DELAY[19]
PIPERX0DATA[4]inCELL_E[10].IMUX_IMUX_DELAY[1]
PIPERX0DATA[5]inCELL_E[10].IMUX_IMUX_DELAY[9]
PIPERX0DATA[6]inCELL_E[11].IMUX_IMUX_DELAY[1]
PIPERX0DATA[7]inCELL_E[11].IMUX_IMUX_DELAY[9]
PIPERX0DATA[8]inCELL_E[11].IMUX_IMUX_DELAY[3]
PIPERX0DATA[9]inCELL_E[11].IMUX_IMUX_DELAY[5]
PIPERX0DATA[10]inCELL_E[11].IMUX_IMUX_DELAY[7]
PIPERX0DATA[11]inCELL_E[11].IMUX_IMUX_DELAY[15]
PIPERX0DATA[12]inCELL_E[12].IMUX_IMUX_DELAY[5]
PIPERX0DATA[13]inCELL_E[12].IMUX_IMUX_DELAY[7]
PIPERX0DATA[14]inCELL_E[12].IMUX_IMUX_DELAY[11]
PIPERX0DATA[15]inCELL_E[12].IMUX_IMUX_DELAY[9]
PIPERX0ELECIDLEinCELL_E[15].IMUX_IMUX_DELAY[21]
PIPERX0PHYSTATUSinCELL_E[14].IMUX_IMUX_DELAY[11]
PIPERX0STATUS[0]inCELL_E[14].IMUX_IMUX_DELAY[23]
PIPERX0STATUS[1]inCELL_E[14].IMUX_IMUX_DELAY[19]
PIPERX0STATUS[2]inCELL_E[14].IMUX_IMUX_DELAY[21]
PIPERX0VALIDinCELL_E[15].IMUX_IMUX_DELAY[19]
PIPERX1CHANISALIGNEDinCELL_E[3].IMUX_IMUX_DELAY[21]
PIPERX1CHARISK[0]inCELL_E[3].IMUX_IMUX_DELAY[23]
PIPERX1CHARISK[1]inCELL_E[2].IMUX_IMUX_DELAY[1]
PIPERX1DATA[0]inCELL_E[0].IMUX_IMUX_DELAY[3]
PIPERX1DATA[1]inCELL_E[0].IMUX_IMUX_DELAY[5]
PIPERX1DATA[2]inCELL_E[0].IMUX_IMUX_DELAY[15]
PIPERX1DATA[3]inCELL_E[0].IMUX_IMUX_DELAY[19]
PIPERX1DATA[4]inCELL_E[0].IMUX_IMUX_DELAY[1]
PIPERX1DATA[5]inCELL_E[0].IMUX_IMUX_DELAY[9]
PIPERX1DATA[6]inCELL_E[1].IMUX_IMUX_DELAY[1]
PIPERX1DATA[7]inCELL_E[1].IMUX_IMUX_DELAY[9]
PIPERX1DATA[8]inCELL_E[1].IMUX_IMUX_DELAY[3]
PIPERX1DATA[9]inCELL_E[1].IMUX_IMUX_DELAY[5]
PIPERX1DATA[10]inCELL_E[1].IMUX_IMUX_DELAY[7]
PIPERX1DATA[11]inCELL_E[1].IMUX_IMUX_DELAY[15]
PIPERX1DATA[12]inCELL_E[2].IMUX_IMUX_DELAY[5]
PIPERX1DATA[13]inCELL_E[2].IMUX_IMUX_DELAY[7]
PIPERX1DATA[14]inCELL_E[2].IMUX_IMUX_DELAY[11]
PIPERX1DATA[15]inCELL_E[2].IMUX_IMUX_DELAY[9]
PIPERX1ELECIDLEinCELL_E[5].IMUX_IMUX_DELAY[21]
PIPERX1PHYSTATUSinCELL_E[4].IMUX_IMUX_DELAY[11]
PIPERX1STATUS[0]inCELL_E[4].IMUX_IMUX_DELAY[23]
PIPERX1STATUS[1]inCELL_E[4].IMUX_IMUX_DELAY[19]
PIPERX1STATUS[2]inCELL_E[4].IMUX_IMUX_DELAY[21]
PIPERX1VALIDinCELL_E[5].IMUX_IMUX_DELAY[19]
PIPERX2CHANISALIGNEDinCELL_W[13].IMUX_IMUX_DELAY[21]
PIPERX2CHARISK[0]inCELL_W[13].IMUX_IMUX_DELAY[23]
PIPERX2CHARISK[1]inCELL_W[12].IMUX_IMUX_DELAY[1]
PIPERX2DATA[0]inCELL_W[10].IMUX_IMUX_DELAY[3]
PIPERX2DATA[1]inCELL_W[10].IMUX_IMUX_DELAY[5]
PIPERX2DATA[2]inCELL_W[10].IMUX_IMUX_DELAY[15]
PIPERX2DATA[3]inCELL_W[10].IMUX_IMUX_DELAY[19]
PIPERX2DATA[4]inCELL_W[10].IMUX_IMUX_DELAY[1]
PIPERX2DATA[5]inCELL_W[10].IMUX_IMUX_DELAY[9]
PIPERX2DATA[6]inCELL_W[11].IMUX_IMUX_DELAY[1]
PIPERX2DATA[7]inCELL_W[11].IMUX_IMUX_DELAY[9]
PIPERX2DATA[8]inCELL_W[11].IMUX_IMUX_DELAY[3]
PIPERX2DATA[9]inCELL_W[11].IMUX_IMUX_DELAY[5]
PIPERX2DATA[10]inCELL_W[11].IMUX_IMUX_DELAY[7]
PIPERX2DATA[11]inCELL_W[11].IMUX_IMUX_DELAY[15]
PIPERX2DATA[12]inCELL_W[12].IMUX_IMUX_DELAY[5]
PIPERX2DATA[13]inCELL_W[12].IMUX_IMUX_DELAY[7]
PIPERX2DATA[14]inCELL_W[12].IMUX_IMUX_DELAY[11]
PIPERX2DATA[15]inCELL_W[12].IMUX_IMUX_DELAY[9]
PIPERX2ELECIDLEinCELL_W[15].IMUX_IMUX_DELAY[21]
PIPERX2PHYSTATUSinCELL_W[14].IMUX_IMUX_DELAY[11]
PIPERX2STATUS[0]inCELL_W[14].IMUX_IMUX_DELAY[23]
PIPERX2STATUS[1]inCELL_W[14].IMUX_IMUX_DELAY[19]
PIPERX2STATUS[2]inCELL_W[14].IMUX_IMUX_DELAY[21]
PIPERX2VALIDinCELL_W[15].IMUX_IMUX_DELAY[19]
PIPERX3CHANISALIGNEDinCELL_W[3].IMUX_IMUX_DELAY[21]
PIPERX3CHARISK[0]inCELL_W[3].IMUX_IMUX_DELAY[23]
PIPERX3CHARISK[1]inCELL_W[2].IMUX_IMUX_DELAY[1]
PIPERX3DATA[0]inCELL_W[0].IMUX_IMUX_DELAY[3]
PIPERX3DATA[1]inCELL_W[0].IMUX_IMUX_DELAY[5]
PIPERX3DATA[2]inCELL_W[0].IMUX_IMUX_DELAY[15]
PIPERX3DATA[3]inCELL_W[0].IMUX_IMUX_DELAY[19]
PIPERX3DATA[4]inCELL_W[0].IMUX_IMUX_DELAY[1]
PIPERX3DATA[5]inCELL_W[0].IMUX_IMUX_DELAY[9]
PIPERX3DATA[6]inCELL_W[1].IMUX_IMUX_DELAY[1]
PIPERX3DATA[7]inCELL_W[1].IMUX_IMUX_DELAY[9]
PIPERX3DATA[8]inCELL_W[1].IMUX_IMUX_DELAY[3]
PIPERX3DATA[9]inCELL_W[1].IMUX_IMUX_DELAY[5]
PIPERX3DATA[10]inCELL_W[1].IMUX_IMUX_DELAY[7]
PIPERX3DATA[11]inCELL_W[1].IMUX_IMUX_DELAY[15]
PIPERX3DATA[12]inCELL_W[2].IMUX_IMUX_DELAY[5]
PIPERX3DATA[13]inCELL_W[2].IMUX_IMUX_DELAY[7]
PIPERX3DATA[14]inCELL_W[2].IMUX_IMUX_DELAY[11]
PIPERX3DATA[15]inCELL_W[2].IMUX_IMUX_DELAY[9]
PIPERX3ELECIDLEinCELL_W[5].IMUX_IMUX_DELAY[21]
PIPERX3PHYSTATUSinCELL_W[4].IMUX_IMUX_DELAY[11]
PIPERX3STATUS[0]inCELL_W[4].IMUX_IMUX_DELAY[23]
PIPERX3STATUS[1]inCELL_W[4].IMUX_IMUX_DELAY[19]
PIPERX3STATUS[2]inCELL_W[4].IMUX_IMUX_DELAY[21]
PIPERX3VALIDinCELL_W[5].IMUX_IMUX_DELAY[19]
PIPERX4CHANISALIGNEDinCELL_E[13].IMUX_IMUX_DELAY[1]
PIPERX4CHARISK[0]inCELL_E[13].IMUX_IMUX_DELAY[15]
PIPERX4CHARISK[1]inCELL_E[12].IMUX_IMUX_DELAY[17]
PIPERX4DATA[0]inCELL_E[10].IMUX_IMUX_DELAY[11]
PIPERX4DATA[1]inCELL_E[10].IMUX_IMUX_DELAY[13]
PIPERX4DATA[2]inCELL_E[10].IMUX_IMUX_DELAY[7]
PIPERX4DATA[3]inCELL_E[10].IMUX_IMUX_DELAY[23]
PIPERX4DATA[4]inCELL_E[10].IMUX_IMUX_DELAY[17]
PIPERX4DATA[5]inCELL_E[10].IMUX_IMUX_DELAY[21]
PIPERX4DATA[6]inCELL_E[11].IMUX_IMUX_DELAY[17]
PIPERX4DATA[7]inCELL_E[11].IMUX_IMUX_DELAY[21]
PIPERX4DATA[8]inCELL_E[11].IMUX_IMUX_DELAY[11]
PIPERX4DATA[9]inCELL_E[11].IMUX_IMUX_DELAY[13]
PIPERX4DATA[10]inCELL_E[11].IMUX_IMUX_DELAY[19]
PIPERX4DATA[11]inCELL_E[11].IMUX_IMUX_DELAY[23]
PIPERX4DATA[12]inCELL_E[12].IMUX_IMUX_DELAY[13]
PIPERX4DATA[13]inCELL_E[12].IMUX_IMUX_DELAY[3]
PIPERX4DATA[14]inCELL_E[12].IMUX_IMUX_DELAY[15]
PIPERX4DATA[15]inCELL_E[12].IMUX_IMUX_DELAY[21]
PIPERX4ELECIDLEinCELL_E[15].IMUX_IMUX_DELAY[5]
PIPERX4PHYSTATUSinCELL_E[14].IMUX_IMUX_DELAY[15]
PIPERX4STATUS[0]inCELL_E[14].IMUX_IMUX_DELAY[3]
PIPERX4STATUS[1]inCELL_E[14].IMUX_IMUX_DELAY[7]
PIPERX4STATUS[2]inCELL_E[14].IMUX_IMUX_DELAY[1]
PIPERX4VALIDinCELL_E[15].IMUX_IMUX_DELAY[11]
PIPERX5CHANISALIGNEDinCELL_E[3].IMUX_IMUX_DELAY[1]
PIPERX5CHARISK[0]inCELL_E[3].IMUX_IMUX_DELAY[15]
PIPERX5CHARISK[1]inCELL_E[2].IMUX_IMUX_DELAY[17]
PIPERX5DATA[0]inCELL_E[0].IMUX_IMUX_DELAY[11]
PIPERX5DATA[1]inCELL_E[0].IMUX_IMUX_DELAY[13]
PIPERX5DATA[2]inCELL_E[0].IMUX_IMUX_DELAY[7]
PIPERX5DATA[3]inCELL_E[0].IMUX_IMUX_DELAY[23]
PIPERX5DATA[4]inCELL_E[0].IMUX_IMUX_DELAY[17]
PIPERX5DATA[5]inCELL_E[0].IMUX_IMUX_DELAY[21]
PIPERX5DATA[6]inCELL_E[1].IMUX_IMUX_DELAY[17]
PIPERX5DATA[7]inCELL_E[1].IMUX_IMUX_DELAY[21]
PIPERX5DATA[8]inCELL_E[1].IMUX_IMUX_DELAY[11]
PIPERX5DATA[9]inCELL_E[1].IMUX_IMUX_DELAY[13]
PIPERX5DATA[10]inCELL_E[1].IMUX_IMUX_DELAY[19]
PIPERX5DATA[11]inCELL_E[1].IMUX_IMUX_DELAY[23]
PIPERX5DATA[12]inCELL_E[2].IMUX_IMUX_DELAY[13]
PIPERX5DATA[13]inCELL_E[2].IMUX_IMUX_DELAY[3]
PIPERX5DATA[14]inCELL_E[2].IMUX_IMUX_DELAY[15]
PIPERX5DATA[15]inCELL_E[2].IMUX_IMUX_DELAY[21]
PIPERX5ELECIDLEinCELL_E[5].IMUX_IMUX_DELAY[5]
PIPERX5PHYSTATUSinCELL_E[4].IMUX_IMUX_DELAY[15]
PIPERX5STATUS[0]inCELL_E[4].IMUX_IMUX_DELAY[3]
PIPERX5STATUS[1]inCELL_E[4].IMUX_IMUX_DELAY[7]
PIPERX5STATUS[2]inCELL_E[4].IMUX_IMUX_DELAY[1]
PIPERX5VALIDinCELL_E[5].IMUX_IMUX_DELAY[11]
PIPERX6CHANISALIGNEDinCELL_W[13].IMUX_IMUX_DELAY[1]
PIPERX6CHARISK[0]inCELL_W[13].IMUX_IMUX_DELAY[15]
PIPERX6CHARISK[1]inCELL_W[12].IMUX_IMUX_DELAY[17]
PIPERX6DATA[0]inCELL_W[10].IMUX_IMUX_DELAY[11]
PIPERX6DATA[1]inCELL_W[10].IMUX_IMUX_DELAY[13]
PIPERX6DATA[2]inCELL_W[10].IMUX_IMUX_DELAY[7]
PIPERX6DATA[3]inCELL_W[10].IMUX_IMUX_DELAY[23]
PIPERX6DATA[4]inCELL_W[10].IMUX_IMUX_DELAY[17]
PIPERX6DATA[5]inCELL_W[10].IMUX_IMUX_DELAY[21]
PIPERX6DATA[6]inCELL_W[11].IMUX_IMUX_DELAY[17]
PIPERX6DATA[7]inCELL_W[11].IMUX_IMUX_DELAY[21]
PIPERX6DATA[8]inCELL_W[11].IMUX_IMUX_DELAY[11]
PIPERX6DATA[9]inCELL_W[11].IMUX_IMUX_DELAY[13]
PIPERX6DATA[10]inCELL_W[11].IMUX_IMUX_DELAY[19]
PIPERX6DATA[11]inCELL_W[11].IMUX_IMUX_DELAY[23]
PIPERX6DATA[12]inCELL_W[12].IMUX_IMUX_DELAY[13]
PIPERX6DATA[13]inCELL_W[12].IMUX_IMUX_DELAY[3]
PIPERX6DATA[14]inCELL_W[12].IMUX_IMUX_DELAY[15]
PIPERX6DATA[15]inCELL_W[12].IMUX_IMUX_DELAY[21]
PIPERX6ELECIDLEinCELL_W[15].IMUX_IMUX_DELAY[5]
PIPERX6PHYSTATUSinCELL_W[14].IMUX_IMUX_DELAY[15]
PIPERX6STATUS[0]inCELL_W[14].IMUX_IMUX_DELAY[3]
PIPERX6STATUS[1]inCELL_W[14].IMUX_IMUX_DELAY[7]
PIPERX6STATUS[2]inCELL_W[14].IMUX_IMUX_DELAY[1]
PIPERX6VALIDinCELL_W[15].IMUX_IMUX_DELAY[11]
PIPERX7CHANISALIGNEDinCELL_W[3].IMUX_IMUX_DELAY[1]
PIPERX7CHARISK[0]inCELL_W[3].IMUX_IMUX_DELAY[15]
PIPERX7CHARISK[1]inCELL_W[2].IMUX_IMUX_DELAY[17]
PIPERX7DATA[0]inCELL_W[0].IMUX_IMUX_DELAY[11]
PIPERX7DATA[1]inCELL_W[0].IMUX_IMUX_DELAY[13]
PIPERX7DATA[2]inCELL_W[0].IMUX_IMUX_DELAY[7]
PIPERX7DATA[3]inCELL_W[0].IMUX_IMUX_DELAY[23]
PIPERX7DATA[4]inCELL_W[0].IMUX_IMUX_DELAY[17]
PIPERX7DATA[5]inCELL_W[0].IMUX_IMUX_DELAY[21]
PIPERX7DATA[6]inCELL_W[1].IMUX_IMUX_DELAY[17]
PIPERX7DATA[7]inCELL_W[1].IMUX_IMUX_DELAY[21]
PIPERX7DATA[8]inCELL_W[1].IMUX_IMUX_DELAY[11]
PIPERX7DATA[9]inCELL_W[1].IMUX_IMUX_DELAY[13]
PIPERX7DATA[10]inCELL_W[1].IMUX_IMUX_DELAY[19]
PIPERX7DATA[11]inCELL_W[1].IMUX_IMUX_DELAY[23]
PIPERX7DATA[12]inCELL_W[2].IMUX_IMUX_DELAY[13]
PIPERX7DATA[13]inCELL_W[2].IMUX_IMUX_DELAY[3]
PIPERX7DATA[14]inCELL_W[2].IMUX_IMUX_DELAY[15]
PIPERX7DATA[15]inCELL_W[2].IMUX_IMUX_DELAY[21]
PIPERX7ELECIDLEinCELL_W[5].IMUX_IMUX_DELAY[5]
PIPERX7PHYSTATUSinCELL_W[4].IMUX_IMUX_DELAY[15]
PIPERX7STATUS[0]inCELL_W[4].IMUX_IMUX_DELAY[3]
PIPERX7STATUS[1]inCELL_W[4].IMUX_IMUX_DELAY[7]
PIPERX7STATUS[2]inCELL_W[4].IMUX_IMUX_DELAY[1]
PIPERX7VALIDinCELL_W[5].IMUX_IMUX_DELAY[11]
FUNCLVLRSTNinCELL_E[1].IMUX_CTRL[1]
LL2SENDASREQL1NinCELL_E[7].IMUX_IMUX_DELAY[11]
LL2SENDENTERL1NinCELL_E[7].IMUX_IMUX_DELAY[9]
LL2SENDENTERL23NinCELL_E[7].IMUX_IMUX_DELAY[10]
LL2SUSPENDNOWNinCELL_E[9].IMUX_IMUX_DELAY[9]
LL2TLPRCVNinCELL_E[7].IMUX_IMUX_DELAY[8]
TL2ASPMSUSPENDCREDITCHECKNinCELL_E[9].IMUX_IMUX_DELAY[11]
TL2PPMSUSPENDREQNinCELL_E[9].IMUX_IMUX_DELAY[10]
DBGMODE[0]inCELL_W[7].IMUX_IMUX_DELAY[20]
DBGMODE[1]inCELL_W[6].IMUX_IMUX_DELAY[20]
DBGSUBMODEinCELL_E[16].IMUX_IMUX_DELAY[21]
PMVDIVIDE[0]inCELL_W[15].IMUX_IMUX_DELAY[9]
PMVDIVIDE[1]inCELL_W[14].IMUX_IMUX_DELAY[12]
PMVENABLENinCELL_W[19].IMUX_IMUX_DELAY[8]
PMVSELECT[0]inCELL_W[18].IMUX_IMUX_DELAY[8]
PMVSELECT[1]inCELL_W[17].IMUX_IMUX_DELAY[8]
PMVSELECT[2]inCELL_W[16].IMUX_IMUX_DELAY[8]
SCANMODENinCELL_E[10].IMUX_IMUX_DELAY[10]
SCANENABLENinCELL_E[11].IMUX_IMUX_DELAY[10]
SCANIN[0]inCELL_E[12].IMUX_IMUX_DELAY[14]
SCANIN[1]inCELL_E[13].IMUX_IMUX_DELAY[9]
SCANIN[2]inCELL_E[14].IMUX_IMUX_DELAY[12]
SCANIN[3]inCELL_E[15].IMUX_IMUX_DELAY[9]
SCANIN[4]inCELL_E[16].IMUX_IMUX_DELAY[8]
SCANIN[5]inCELL_E[17].IMUX_IMUX_DELAY[8]
SCANIN[6]inCELL_E[18].IMUX_IMUX_DELAY[8]
SCANIN[7]inCELL_E[19].IMUX_IMUX_DELAY[8]
USERRSTNoutCELL_E[2].OUT_BEL[12]
TRNLNKUPNoutCELL_W[12].OUT_BEL[2]
TRNFCPH[0]outCELL_W[12].OUT_BEL[3]
TRNFCPH[1]outCELL_W[11].OUT_BEL[0]
TRNFCPH[2]outCELL_W[11].OUT_BEL[1]
TRNFCPH[3]outCELL_W[11].OUT_BEL[2]
TRNFCPH[4]outCELL_W[11].OUT_BEL[3]
TRNFCPH[5]outCELL_W[10].OUT_BEL[0]
TRNFCPH[6]outCELL_W[10].OUT_BEL[1]
TRNFCPH[7]outCELL_W[10].OUT_BEL[2]
TRNFCPD[0]outCELL_W[10].OUT_BEL[3]
TRNFCPD[1]outCELL_W[9].OUT_BEL[0]
TRNFCPD[2]outCELL_W[9].OUT_BEL[1]
TRNFCPD[3]outCELL_W[9].OUT_BEL[2]
TRNFCPD[4]outCELL_W[9].OUT_BEL[3]
TRNFCPD[5]outCELL_W[8].OUT_BEL[0]
TRNFCPD[6]outCELL_W[8].OUT_BEL[3]
TRNFCPD[7]outCELL_W[8].OUT_BEL[4]
TRNFCPD[8]outCELL_W[8].OUT_BEL[7]
TRNFCPD[9]outCELL_W[7].OUT_BEL[0]
TRNFCPD[10]outCELL_W[7].OUT_BEL[3]
TRNFCPD[11]outCELL_W[7].OUT_BEL[4]
TRNFCNPH[0]outCELL_W[7].OUT_BEL[7]
TRNFCNPH[1]outCELL_W[6].OUT_BEL[0]
TRNFCNPH[2]outCELL_W[6].OUT_BEL[1]
TRNFCNPH[3]outCELL_W[6].OUT_BEL[3]
TRNFCNPH[4]outCELL_W[6].OUT_BEL[4]
TRNFCNPH[5]outCELL_W[5].OUT_BEL[0]
TRNFCNPH[6]outCELL_W[5].OUT_BEL[1]
TRNFCNPH[7]outCELL_W[5].OUT_BEL[2]
TRNFCNPD[0]outCELL_W[5].OUT_BEL[3]
TRNFCNPD[1]outCELL_W[4].OUT_BEL[0]
TRNFCNPD[2]outCELL_W[4].OUT_BEL[2]
TRNFCNPD[3]outCELL_W[4].OUT_BEL[3]
TRNFCNPD[4]outCELL_W[4].OUT_BEL[4]
TRNFCNPD[5]outCELL_W[3].OUT_BEL[0]
TRNFCNPD[6]outCELL_W[3].OUT_BEL[1]
TRNFCNPD[7]outCELL_W[3].OUT_BEL[2]
TRNFCNPD[8]outCELL_W[3].OUT_BEL[3]
TRNFCNPD[9]outCELL_W[2].OUT_BEL[0]
TRNFCNPD[10]outCELL_W[2].OUT_BEL[1]
TRNFCNPD[11]outCELL_W[2].OUT_BEL[2]
TRNFCCPLH[0]outCELL_W[2].OUT_BEL[3]
TRNFCCPLH[1]outCELL_W[1].OUT_BEL[0]
TRNFCCPLH[2]outCELL_W[1].OUT_BEL[1]
TRNFCCPLH[3]outCELL_W[1].OUT_BEL[2]
TRNFCCPLH[4]outCELL_W[1].OUT_BEL[3]
TRNFCCPLH[5]outCELL_W[0].OUT_BEL[0]
TRNFCCPLH[6]outCELL_W[0].OUT_BEL[1]
TRNFCCPLH[7]outCELL_W[0].OUT_BEL[2]
TRNFCCPLD[0]outCELL_W[0].OUT_BEL[3]
TRNFCCPLD[1]outCELL_E[0].OUT_BEL[16]
TRNFCCPLD[2]outCELL_E[0].OUT_BEL[17]
TRNFCCPLD[3]outCELL_E[0].OUT_BEL[18]
TRNFCCPLD[4]outCELL_E[0].OUT_BEL[19]
TRNFCCPLD[5]outCELL_E[1].OUT_BEL[4]
TRNFCCPLD[6]outCELL_E[1].OUT_BEL[5]
TRNFCCPLD[7]outCELL_E[1].OUT_BEL[6]
TRNFCCPLD[8]outCELL_E[1].OUT_BEL[7]
TRNFCCPLD[9]outCELL_E[2].OUT_BEL[4]
TRNFCCPLD[10]outCELL_E[2].OUT_BEL[5]
TRNFCCPLD[11]outCELL_E[2].OUT_BEL[6]
TRNTDSTRDYNoutCELL_E[2].OUT_BEL[3]
TRNTBUFAV[0]outCELL_E[3].OUT_BEL[1]
TRNTBUFAV[1]outCELL_E[3].OUT_BEL[2]
TRNTBUFAV[2]outCELL_E[3].OUT_BEL[3]
TRNTBUFAV[3]outCELL_E[4].OUT_BEL[0]
TRNTBUFAV[4]outCELL_E[4].OUT_BEL[2]
TRNTBUFAV[5]outCELL_E[4].OUT_BEL[3]
TRNTERRDROPNoutCELL_E[3].OUT_BEL[0]
TRNTCFGREQNoutCELL_E[4].OUT_BEL[4]
TRNTDLLPDSTRDYNoutCELL_W[14].OUT_BEL[10]
TRNRSOFNoutCELL_W[15].OUT_BEL[1]
TRNREOFNoutCELL_W[15].OUT_BEL[2]
TRNRD[0]outCELL_E[5].OUT_BEL[0]
TRNRD[1]outCELL_E[5].OUT_BEL[1]
TRNRD[2]outCELL_E[5].OUT_BEL[2]
TRNRD[3]outCELL_E[5].OUT_BEL[3]
TRNRD[4]outCELL_E[6].OUT_BEL[0]
TRNRD[5]outCELL_E[6].OUT_BEL[1]
TRNRD[6]outCELL_E[6].OUT_BEL[3]
TRNRD[7]outCELL_E[6].OUT_BEL[4]
TRNRD[8]outCELL_E[7].OUT_BEL[0]
TRNRD[9]outCELL_E[7].OUT_BEL[3]
TRNRD[10]outCELL_E[8].OUT_BEL[0]
TRNRD[11]outCELL_E[8].OUT_BEL[3]
TRNRD[12]outCELL_E[9].OUT_BEL[0]
TRNRD[13]outCELL_E[9].OUT_BEL[1]
TRNRD[14]outCELL_E[9].OUT_BEL[2]
TRNRD[15]outCELL_E[9].OUT_BEL[3]
TRNRD[16]outCELL_E[10].OUT_BEL[0]
TRNRD[17]outCELL_E[10].OUT_BEL[1]
TRNRD[18]outCELL_E[10].OUT_BEL[2]
TRNRD[19]outCELL_E[10].OUT_BEL[3]
TRNRD[20]outCELL_E[11].OUT_BEL[0]
TRNRD[21]outCELL_E[11].OUT_BEL[1]
TRNRD[22]outCELL_E[11].OUT_BEL[2]
TRNRD[23]outCELL_E[11].OUT_BEL[3]
TRNRD[24]outCELL_E[12].OUT_BEL[0]
TRNRD[25]outCELL_E[12].OUT_BEL[1]
TRNRD[26]outCELL_E[12].OUT_BEL[2]
TRNRD[27]outCELL_E[12].OUT_BEL[3]
TRNRD[28]outCELL_E[13].OUT_BEL[0]
TRNRD[29]outCELL_E[13].OUT_BEL[1]
TRNRD[30]outCELL_E[13].OUT_BEL[2]
TRNRD[31]outCELL_E[13].OUT_BEL[3]
TRNRD[32]outCELL_E[14].OUT_BEL[0]
TRNRD[33]outCELL_E[14].OUT_BEL[2]
TRNRD[34]outCELL_E[14].OUT_BEL[3]
TRNRD[35]outCELL_E[14].OUT_BEL[4]
TRNRD[36]outCELL_E[15].OUT_BEL[0]
TRNRD[37]outCELL_E[15].OUT_BEL[1]
TRNRD[38]outCELL_E[15].OUT_BEL[2]
TRNRD[39]outCELL_E[15].OUT_BEL[3]
TRNRD[40]outCELL_E[16].OUT_BEL[0]
TRNRD[41]outCELL_E[16].OUT_BEL[1]
TRNRD[42]outCELL_E[16].OUT_BEL[3]
TRNRD[43]outCELL_E[16].OUT_BEL[4]
TRNRD[44]outCELL_E[17].OUT_BEL[0]
TRNRD[45]outCELL_E[17].OUT_BEL[3]
TRNRD[46]outCELL_E[18].OUT_BEL[0]
TRNRD[47]outCELL_E[18].OUT_BEL[3]
TRNRD[48]outCELL_E[19].OUT_BEL[0]
TRNRD[49]outCELL_E[19].OUT_BEL[1]
TRNRD[50]outCELL_E[19].OUT_BEL[2]
TRNRD[51]outCELL_E[19].OUT_BEL[3]
TRNRD[52]outCELL_W[19].OUT_BEL[0]
TRNRD[53]outCELL_W[19].OUT_BEL[1]
TRNRD[54]outCELL_W[19].OUT_BEL[2]
TRNRD[55]outCELL_W[19].OUT_BEL[3]
TRNRD[56]outCELL_W[18].OUT_BEL[0]
TRNRD[57]outCELL_W[18].OUT_BEL[3]
TRNRD[58]outCELL_W[17].OUT_BEL[0]
TRNRD[59]outCELL_W[17].OUT_BEL[3]
TRNRD[60]outCELL_W[16].OUT_BEL[0]
TRNRD[61]outCELL_W[16].OUT_BEL[1]
TRNRD[62]outCELL_W[16].OUT_BEL[3]
TRNRD[63]outCELL_W[16].OUT_BEL[4]
TRNRREMNoutCELL_W[15].OUT_BEL[0]
TRNRERRFWDNoutCELL_W[14].OUT_BEL[3]
TRNRSRCRDYNoutCELL_W[15].OUT_BEL[3]
TRNRSRCDSCNoutCELL_W[14].OUT_BEL[0]
TRNRBARHITN[0]outCELL_W[14].OUT_BEL[4]
TRNRBARHITN[1]outCELL_W[13].OUT_BEL[0]
TRNRBARHITN[2]outCELL_W[13].OUT_BEL[1]
TRNRBARHITN[3]outCELL_W[13].OUT_BEL[2]
TRNRBARHITN[4]outCELL_W[13].OUT_BEL[3]
TRNRBARHITN[5]outCELL_W[12].OUT_BEL[0]
TRNRBARHITN[6]outCELL_W[12].OUT_BEL[1]
TRNRECRCERRNoutCELL_W[14].OUT_BEL[2]
TRNRDLLPDATA[0]outCELL_W[13].OUT_BEL[8]
TRNRDLLPDATA[1]outCELL_W[13].OUT_BEL[9]
TRNRDLLPDATA[2]outCELL_W[13].OUT_BEL[10]
TRNRDLLPDATA[3]outCELL_W[13].OUT_BEL[11]
TRNRDLLPDATA[4]outCELL_W[12].OUT_BEL[8]
TRNRDLLPDATA[5]outCELL_W[12].OUT_BEL[9]
TRNRDLLPDATA[6]outCELL_W[12].OUT_BEL[10]
TRNRDLLPDATA[7]outCELL_W[12].OUT_BEL[11]
TRNRDLLPDATA[8]outCELL_W[11].OUT_BEL[8]
TRNRDLLPDATA[9]outCELL_W[11].OUT_BEL[9]
TRNRDLLPDATA[10]outCELL_W[11].OUT_BEL[10]
TRNRDLLPDATA[11]outCELL_W[11].OUT_BEL[11]
TRNRDLLPDATA[12]outCELL_W[10].OUT_BEL[8]
TRNRDLLPDATA[13]outCELL_W[10].OUT_BEL[9]
TRNRDLLPDATA[14]outCELL_W[10].OUT_BEL[10]
TRNRDLLPDATA[15]outCELL_W[10].OUT_BEL[11]
TRNRDLLPDATA[16]outCELL_W[9].OUT_BEL[8]
TRNRDLLPDATA[17]outCELL_W[9].OUT_BEL[9]
TRNRDLLPDATA[18]outCELL_W[9].OUT_BEL[10]
TRNRDLLPDATA[19]outCELL_W[9].OUT_BEL[11]
TRNRDLLPDATA[20]outCELL_W[6].OUT_BEL[10]
TRNRDLLPDATA[21]outCELL_W[6].OUT_BEL[11]
TRNRDLLPDATA[22]outCELL_W[5].OUT_BEL[8]
TRNRDLLPDATA[23]outCELL_W[5].OUT_BEL[9]
TRNRDLLPDATA[24]outCELL_W[5].OUT_BEL[10]
TRNRDLLPDATA[25]outCELL_W[5].OUT_BEL[11]
TRNRDLLPDATA[26]outCELL_W[4].OUT_BEL[10]
TRNRDLLPDATA[27]outCELL_W[4].OUT_BEL[11]
TRNRDLLPDATA[28]outCELL_W[4].OUT_BEL[12]
TRNRDLLPDATA[29]outCELL_W[4].OUT_BEL[13]
TRNRDLLPDATA[30]outCELL_W[3].OUT_BEL[8]
TRNRDLLPDATA[31]outCELL_W[3].OUT_BEL[9]
TRNRDLLPSRCRDYNoutCELL_W[3].OUT_BEL[10]
PLINITIALLINKWIDTH[0]outCELL_E[2].OUT_BEL[0]
PLINITIALLINKWIDTH[1]outCELL_E[2].OUT_BEL[1]
PLINITIALLINKWIDTH[2]outCELL_E[2].OUT_BEL[2]
PLLANEREVERSALMODE[0]outCELL_E[0].OUT_BEL[9]
PLLANEREVERSALMODE[1]outCELL_E[0].OUT_BEL[10]
PLLINKGEN2CAPoutCELL_E[1].OUT_BEL[2]
PLLINKPARTNERGEN2SUPPORTEDoutCELL_E[1].OUT_BEL[3]
PLLINKUPCFGCAPoutCELL_E[1].OUT_BEL[1]
PLSELLNKRATEoutCELL_E[0].OUT_BEL[0]
PLSELLNKWIDTH[0]outCELL_E[0].OUT_BEL[1]
PLSELLNKWIDTH[1]outCELL_E[0].OUT_BEL[2]
PLLTSSMSTATE[0]outCELL_E[0].OUT_BEL[3]
PLLTSSMSTATE[1]outCELL_E[0].OUT_BEL[4]
PLLTSSMSTATE[2]outCELL_E[0].OUT_BEL[5]
PLLTSSMSTATE[3]outCELL_E[0].OUT_BEL[6]
PLLTSSMSTATE[4]outCELL_E[0].OUT_BEL[7]
PLLTSSMSTATE[5]outCELL_E[0].OUT_BEL[8]
PLRECEIVEDHOTRSToutCELL_E[2].OUT_BEL[13]
PL2LINKUPNoutCELL_W[0].OUT_BEL[9]
PL2RECEIVERERRNoutCELL_W[0].OUT_BEL[10]
PL2RECOVERYNoutCELL_W[2].OUT_BEL[10]
PL2RXELECIDLEoutCELL_W[2].OUT_BEL[11]
PL2SUSPENDOKoutCELL_W[2].OUT_BEL[9]
PLDBGVEC[0]outCELL_E[16].OUT_BEL[22]
PLDBGVEC[1]outCELL_E[17].OUT_BEL[15]
PLDBGVEC[2]outCELL_E[18].OUT_BEL[15]
PLDBGVEC[3]outCELL_E[19].OUT_BEL[19]
PLDBGVEC[4]outCELL_E[19].OUT_BEL[20]
PLDBGVEC[5]outCELL_W[19].OUT_BEL[22]
PLDBGVEC[6]outCELL_W[18].OUT_BEL[12]
PLDBGVEC[7]outCELL_W[18].OUT_BEL[13]
PLDBGVEC[8]outCELL_W[17].OUT_BEL[11]
PLDBGVEC[9]outCELL_W[17].OUT_BEL[12]
PLDBGVEC[10]outCELL_W[16].OUT_BEL[12]
PLDBGVEC[11]outCELL_W[16].OUT_BEL[13]
PLPHYLNKUPNoutCELL_E[0].OUT_BEL[11]
PLRXPMSTATE[0]outCELL_E[0].OUT_BEL[15]
PLRXPMSTATE[1]outCELL_E[1].OUT_BEL[0]
PLTXPMSTATE[0]outCELL_E[0].OUT_BEL[12]
PLTXPMSTATE[1]outCELL_E[0].OUT_BEL[13]
PLTXPMSTATE[2]outCELL_E[0].OUT_BEL[14]
CFGDO[0]outCELL_E[2].OUT_BEL[15]
CFGDO[1]outCELL_E[3].OUT_BEL[12]
CFGDO[2]outCELL_E[3].OUT_BEL[13]
CFGDO[3]outCELL_E[3].OUT_BEL[14]
CFGDO[4]outCELL_E[3].OUT_BEL[15]
CFGDO[5]outCELL_E[4].OUT_BEL[14]
CFGDO[6]outCELL_E[5].OUT_BEL[12]
CFGDO[7]outCELL_E[6].OUT_BEL[8]
CFGDO[8]outCELL_E[7].OUT_BEL[4]
CFGDO[9]outCELL_E[8].OUT_BEL[4]
CFGDO[10]outCELL_E[9].OUT_BEL[12]
CFGDO[11]outCELL_E[9].OUT_BEL[13]
CFGDO[12]outCELL_E[9].OUT_BEL[14]
CFGDO[13]outCELL_E[9].OUT_BEL[15]
CFGDO[14]outCELL_E[10].OUT_BEL[12]
CFGDO[15]outCELL_E[10].OUT_BEL[13]
CFGDO[16]outCELL_E[10].OUT_BEL[14]
CFGDO[17]outCELL_E[10].OUT_BEL[15]
CFGDO[18]outCELL_E[11].OUT_BEL[12]
CFGDO[19]outCELL_E[11].OUT_BEL[13]
CFGDO[20]outCELL_E[11].OUT_BEL[14]
CFGDO[21]outCELL_E[11].OUT_BEL[15]
CFGDO[22]outCELL_E[12].OUT_BEL[12]
CFGDO[23]outCELL_E[12].OUT_BEL[13]
CFGDO[24]outCELL_E[12].OUT_BEL[14]
CFGDO[25]outCELL_E[12].OUT_BEL[15]
CFGDO[26]outCELL_E[13].OUT_BEL[12]
CFGDO[27]outCELL_E[13].OUT_BEL[13]
CFGDO[28]outCELL_E[13].OUT_BEL[14]
CFGDO[29]outCELL_E[13].OUT_BEL[15]
CFGDO[30]outCELL_E[14].OUT_BEL[14]
CFGDO[31]outCELL_E[15].OUT_BEL[12]
CFGRDWRDONENoutCELL_E[16].OUT_BEL[8]
CFGCOMMANDIOENABLEoutCELL_W[0].OUT_BEL[13]
CFGCOMMANDMEMENABLEoutCELL_W[0].OUT_BEL[14]
CFGCOMMANDBUSMASTERENABLEoutCELL_W[0].OUT_BEL[15]
CFGCOMMANDINTERRUPTDISABLEoutCELL_E[1].OUT_BEL[16]
CFGCOMMANDSERRENoutCELL_W[0].OUT_BEL[17]
CFGDEVSTATUSCORRERRDETECTEDoutCELL_E[1].OUT_BEL[17]
CFGDEVSTATUSFATALERRDETECTEDoutCELL_E[2].OUT_BEL[17]
CFGDEVSTATUSNONFATALERRDETECTEDoutCELL_E[2].OUT_BEL[16]
CFGDEVSTATUSURDETECTEDoutCELL_E[2].OUT_BEL[18]
CFGDEVCONTROLAUXPOWERENoutCELL_E[11].OUT_BEL[17]
CFGDEVCONTROLCORRERRREPORTINGENoutCELL_E[3].OUT_BEL[16]
CFGDEVCONTROLENABLEROoutCELL_E[9].OUT_BEL[17]
CFGDEVCONTROLEXTTAGENoutCELL_E[10].OUT_BEL[18]
CFGDEVCONTROLFATALERRREPORTINGENoutCELL_E[3].OUT_BEL[18]
CFGDEVCONTROLMAXPAYLOAD[0]outCELL_E[9].OUT_BEL[18]
CFGDEVCONTROLMAXPAYLOAD[1]outCELL_E[10].OUT_BEL[16]
CFGDEVCONTROLMAXPAYLOAD[2]outCELL_E[10].OUT_BEL[17]
CFGDEVCONTROLMAXREADREQ[0]outCELL_E[12].OUT_BEL[17]
CFGDEVCONTROLMAXREADREQ[1]outCELL_E[12].OUT_BEL[18]
CFGDEVCONTROLMAXREADREQ[2]outCELL_E[13].OUT_BEL[16]
CFGDEVCONTROLNONFATALREPORTINGENoutCELL_E[3].OUT_BEL[17]
CFGDEVCONTROLNOSNOOPENoutCELL_E[12].OUT_BEL[16]
CFGDEVCONTROLPHANTOMENoutCELL_E[11].OUT_BEL[16]
CFGDEVCONTROLURERRREPORTINGENoutCELL_E[9].OUT_BEL[16]
CFGDEVCONTROL2CPLTIMEOUTDISoutCELL_W[10].OUT_BEL[16]
CFGDEVCONTROL2CPLTIMEOUTVAL[0]outCELL_W[11].OUT_BEL[16]
CFGDEVCONTROL2CPLTIMEOUTVAL[1]outCELL_W[11].OUT_BEL[17]
CFGDEVCONTROL2CPLTIMEOUTVAL[2]outCELL_W[11].OUT_BEL[19]
CFGDEVCONTROL2CPLTIMEOUTVAL[3]outCELL_W[11].OUT_BEL[20]
CFGLINKSTATUSAUTOBANDWIDTHSTATUSoutCELL_W[18].OUT_BEL[11]
CFGLINKSTATUSBANDWITHSTATUSoutCELL_W[19].OUT_BEL[19]
CFGLINKSTATUSCURRENTSPEED[0]outCELL_E[13].OUT_BEL[17]
CFGLINKSTATUSCURRENTSPEED[1]outCELL_E[13].OUT_BEL[18]
CFGLINKSTATUSDLLACTIVEoutCELL_W[19].OUT_BEL[18]
CFGLINKSTATUSLINKTRAININGoutCELL_W[19].OUT_BEL[17]
CFGLINKSTATUSNEGOTIATEDWIDTH[0]outCELL_E[19].OUT_BEL[16]
CFGLINKSTATUSNEGOTIATEDWIDTH[1]outCELL_E[19].OUT_BEL[17]
CFGLINKSTATUSNEGOTIATEDWIDTH[2]outCELL_E[19].OUT_BEL[18]
CFGLINKSTATUSNEGOTIATEDWIDTH[3]outCELL_W[19].OUT_BEL[16]
CFGLINKCONTROLASPMCONTROL[0]outCELL_W[17].OUT_BEL[10]
CFGLINKCONTROLASPMCONTROL[1]outCELL_W[16].OUT_BEL[11]
CFGLINKCONTROLAUTOBANDWIDTHINTENoutCELL_W[12].OUT_BEL[19]
CFGLINKCONTROLBANDWIDTHINTENoutCELL_W[12].OUT_BEL[18]
CFGLINKCONTROLCLOCKPMENoutCELL_W[12].OUT_BEL[16]
CFGLINKCONTROLCOMMONCLOCKoutCELL_W[13].OUT_BEL[17]
CFGLINKCONTROLEXTENDEDSYNCoutCELL_W[13].OUT_BEL[18]
CFGLINKCONTROLHWAUTOWIDTHDISoutCELL_W[12].OUT_BEL[17]
CFGLINKCONTROLLINKDISABLEoutCELL_W[15].OUT_BEL[13]
CFGLINKCONTROLRCBoutCELL_W[15].OUT_BEL[12]
CFGLINKCONTROLRETRAINLINKoutCELL_W[15].OUT_BEL[14]
CFGPCIELINKSTATE[0]outCELL_W[6].OUT_BEL[12]
CFGPCIELINKSTATE[1]outCELL_W[5].OUT_BEL[12]
CFGPCIELINKSTATE[2]outCELL_W[4].OUT_BEL[14]
CFGPMCSRPMEENoutCELL_W[12].OUT_BEL[21]
CFGPMCSRPMESTATUSoutCELL_W[13].OUT_BEL[20]
CFGPMCSRPOWERSTATE[0]outCELL_W[9].OUT_BEL[23]
CFGPMCSRPOWERSTATE[1]outCELL_W[9].OUT_BEL[22]
CFGPMRCVASREQL1NoutCELL_W[4].OUT_BEL[15]
CFGPMRCVENTERL1NoutCELL_W[3].OUT_BEL[12]
CFGPMRCVENTERL23NoutCELL_W[3].OUT_BEL[13]
CFGPMRCVREQACKNoutCELL_W[3].OUT_BEL[14]
CFGMSGRECEIVEDoutCELL_W[17].OUT_BEL[9]
CFGMSGDATA[0]outCELL_W[16].OUT_BEL[5]
CFGMSGDATA[1]outCELL_W[16].OUT_BEL[7]
CFGMSGDATA[2]outCELL_W[16].OUT_BEL[8]
CFGMSGDATA[3]outCELL_W[16].OUT_BEL[10]
CFGMSGDATA[4]outCELL_W[15].OUT_BEL[8]
CFGMSGDATA[5]outCELL_W[15].OUT_BEL[9]
CFGMSGDATA[6]outCELL_W[15].OUT_BEL[10]
CFGMSGDATA[7]outCELL_W[15].OUT_BEL[11]
CFGMSGDATA[8]outCELL_W[14].OUT_BEL[11]
CFGMSGDATA[9]outCELL_W[14].OUT_BEL[12]
CFGMSGDATA[10]outCELL_W[14].OUT_BEL[13]
CFGMSGDATA[11]outCELL_W[13].OUT_BEL[12]
CFGMSGDATA[12]outCELL_W[13].OUT_BEL[13]
CFGMSGDATA[13]outCELL_W[13].OUT_BEL[14]
CFGMSGDATA[14]outCELL_W[13].OUT_BEL[15]
CFGMSGDATA[15]outCELL_W[12].OUT_BEL[12]
CFGMSGRECEIVEDASSERTINTAoutCELL_W[11].OUT_BEL[12]
CFGMSGRECEIVEDASSERTINTBoutCELL_W[11].OUT_BEL[14]
CFGMSGRECEIVEDASSERTINTCoutCELL_W[10].OUT_BEL[12]
CFGMSGRECEIVEDASSERTINTDoutCELL_W[10].OUT_BEL[14]
CFGMSGRECEIVEDDEASSERTINTAoutCELL_W[11].OUT_BEL[13]
CFGMSGRECEIVEDDEASSERTINTBoutCELL_W[11].OUT_BEL[15]
CFGMSGRECEIVEDDEASSERTINTCoutCELL_W[10].OUT_BEL[13]
CFGMSGRECEIVEDDEASSERTINTDoutCELL_W[10].OUT_BEL[15]
CFGMSGRECEIVEDERRCORoutCELL_W[12].OUT_BEL[13]
CFGMSGRECEIVEDERRFATALoutCELL_W[12].OUT_BEL[15]
CFGMSGRECEIVEDERRNONFATALoutCELL_W[12].OUT_BEL[14]
CFGMSGRECEIVEDPMASNAKoutCELL_W[7].OUT_BEL[10]
CFGMSGRECEIVEDPMETOoutCELL_W[9].OUT_BEL[14]
CFGMSGRECEIVEDPMETOACKoutCELL_W[9].OUT_BEL[13]
CFGMSGRECEIVEDPMPMEoutCELL_W[9].OUT_BEL[12]
CFGMSGRECEIVEDSETSLOTPOWERLIMIToutCELL_W[9].OUT_BEL[15]
CFGMSGRECEIVEDUNLOCKoutCELL_W[8].OUT_BEL[10]
CFGINTERRUPTRDYNoutCELL_E[19].OUT_BEL[12]
CFGINTERRUPTDO[0]outCELL_W[19].OUT_BEL[13]
CFGINTERRUPTDO[1]outCELL_W[19].OUT_BEL[14]
CFGINTERRUPTDO[2]outCELL_W[19].OUT_BEL[15]
CFGINTERRUPTDO[3]outCELL_W[18].OUT_BEL[4]
CFGINTERRUPTDO[4]outCELL_W[18].OUT_BEL[8]
CFGINTERRUPTDO[5]outCELL_W[18].OUT_BEL[9]
CFGINTERRUPTDO[6]outCELL_W[18].OUT_BEL[10]
CFGINTERRUPTDO[7]outCELL_W[17].OUT_BEL[4]
CFGINTERRUPTMMENABLE[0]outCELL_E[19].OUT_BEL[13]
CFGINTERRUPTMMENABLE[1]outCELL_E[19].OUT_BEL[14]
CFGINTERRUPTMMENABLE[2]outCELL_E[19].OUT_BEL[15]
CFGINTERRUPTMSIENABLEoutCELL_W[19].OUT_BEL[12]
CFGINTERRUPTMSIXENABLEoutCELL_W[17].OUT_BEL[7]
CFGINTERRUPTMSIXFMoutCELL_W[17].OUT_BEL[8]
CFGERRCPLRDYNoutCELL_E[18].OUT_BEL[4]
CFGERRAERHEADERLOGSETNoutCELL_E[17].OUT_BEL[4]
CFGAERECRCCHECKENoutCELL_W[10].OUT_BEL[18]
CFGAERECRCGENENoutCELL_W[10].OUT_BEL[19]
CFGSLOTCONTROLELECTROMECHILCTLPULSEoutCELL_W[10].OUT_BEL[17]
CFGTRANSACTIONoutCELL_W[3].OUT_BEL[15]
CFGTRANSACTIONADDR[0]outCELL_W[2].OUT_BEL[13]
CFGTRANSACTIONADDR[1]outCELL_W[2].OUT_BEL[14]
CFGTRANSACTIONADDR[2]outCELL_W[2].OUT_BEL[15]
CFGTRANSACTIONADDR[3]outCELL_W[1].OUT_BEL[12]
CFGTRANSACTIONADDR[4]outCELL_W[1].OUT_BEL[13]
CFGTRANSACTIONADDR[5]outCELL_W[1].OUT_BEL[14]
CFGTRANSACTIONADDR[6]outCELL_W[1].OUT_BEL[15]
CFGTRANSACTIONTYPEoutCELL_W[2].OUT_BEL[12]
CFGVCTCVCMAP[0]outCELL_W[9].OUT_BEL[16]
CFGVCTCVCMAP[1]outCELL_W[9].OUT_BEL[17]
CFGVCTCVCMAP[2]outCELL_W[9].OUT_BEL[18]
CFGVCTCVCMAP[3]outCELL_W[9].OUT_BEL[19]
CFGVCTCVCMAP[4]outCELL_W[8].OUT_BEL[12]
CFGVCTCVCMAP[5]outCELL_W[8].OUT_BEL[13]
CFGVCTCVCMAP[6]outCELL_W[8].OUT_BEL[14]
DRPDRDYoutCELL_W[3].OUT_BEL[16]
DRPDO[0]outCELL_W[3].OUT_BEL[17]
DRPDO[1]outCELL_W[3].OUT_BEL[18]
DRPDO[2]outCELL_W[3].OUT_BEL[19]
DRPDO[3]outCELL_W[2].OUT_BEL[16]
DRPDO[4]outCELL_W[2].OUT_BEL[17]
DRPDO[5]outCELL_W[2].OUT_BEL[18]
DRPDO[6]outCELL_W[2].OUT_BEL[19]
DRPDO[7]outCELL_W[1].OUT_BEL[16]
DRPDO[8]outCELL_W[1].OUT_BEL[17]
DRPDO[9]outCELL_W[1].OUT_BEL[19]
DRPDO[10]outCELL_W[19].OUT_BEL[20]
DRPDO[11]outCELL_W[19].OUT_BEL[21]
DRPDO[12]outCELL_W[12].OUT_BEL[20]
DRPDO[13]outCELL_W[11].OUT_BEL[21]
DRPDO[14]outCELL_W[11].OUT_BEL[23]
DRPDO[15]outCELL_W[10].OUT_BEL[20]
MIMRXRADDR[0]outCELL_E[17].OUT_BEL[9]
MIMRXRADDR[1]outCELL_E[17].OUT_BEL[10]
MIMRXRADDR[2]outCELL_E[18].OUT_BEL[7]
MIMRXRADDR[3]outCELL_E[18].OUT_BEL[8]
MIMRXRADDR[4]outCELL_E[18].OUT_BEL[9]
MIMRXRADDR[5]outCELL_E[18].OUT_BEL[10]
MIMRXRADDR[6]outCELL_E[19].OUT_BEL[8]
MIMRXRADDR[7]outCELL_E[19].OUT_BEL[9]
MIMRXRADDR[8]outCELL_E[19].OUT_BEL[10]
MIMRXRADDR[9]outCELL_E[19].OUT_BEL[11]
MIMRXRADDR[10]outCELL_W[19].OUT_BEL[8]
MIMRXRADDR[11]outCELL_W[19].OUT_BEL[9]
MIMRXRADDR[12]outCELL_W[19].OUT_BEL[10]
MIMRXRCEoutCELL_W[18].OUT_BEL[7]
MIMRXRENoutCELL_W[19].OUT_BEL[11]
MIMRXWADDR[0]outCELL_E[14].OUT_BEL[10]
MIMRXWADDR[1]outCELL_E[14].OUT_BEL[11]
MIMRXWADDR[2]outCELL_E[14].OUT_BEL[12]
MIMRXWADDR[3]outCELL_E[14].OUT_BEL[13]
MIMRXWADDR[4]outCELL_E[15].OUT_BEL[8]
MIMRXWADDR[5]outCELL_E[15].OUT_BEL[9]
MIMRXWADDR[6]outCELL_E[15].OUT_BEL[10]
MIMRXWADDR[7]outCELL_E[15].OUT_BEL[11]
MIMRXWADDR[8]outCELL_E[16].OUT_BEL[9]
MIMRXWADDR[9]outCELL_E[16].OUT_BEL[10]
MIMRXWADDR[10]outCELL_E[16].OUT_BEL[11]
MIMRXWADDR[11]outCELL_E[16].OUT_BEL[12]
MIMRXWADDR[12]outCELL_E[17].OUT_BEL[7]
MIMRXWDATA[0]outCELL_W[3].OUT_BEL[5]
MIMRXWDATA[1]outCELL_W[3].OUT_BEL[6]
MIMRXWDATA[2]outCELL_W[3].OUT_BEL[7]
MIMRXWDATA[3]outCELL_W[2].OUT_BEL[4]
MIMRXWDATA[4]outCELL_W[2].OUT_BEL[5]
MIMRXWDATA[5]outCELL_W[2].OUT_BEL[6]
MIMRXWDATA[6]outCELL_W[2].OUT_BEL[7]
MIMRXWDATA[7]outCELL_W[1].OUT_BEL[4]
MIMRXWDATA[8]outCELL_W[1].OUT_BEL[5]
MIMRXWDATA[9]outCELL_W[1].OUT_BEL[6]
MIMRXWDATA[10]outCELL_W[1].OUT_BEL[7]
MIMRXWDATA[11]outCELL_W[0].OUT_BEL[4]
MIMRXWDATA[12]outCELL_W[0].OUT_BEL[5]
MIMRXWDATA[13]outCELL_W[0].OUT_BEL[7]
MIMRXWDATA[14]outCELL_W[0].OUT_BEL[8]
MIMRXWDATA[15]outCELL_E[0].OUT_BEL[20]
MIMRXWDATA[16]outCELL_E[1].OUT_BEL[8]
MIMRXWDATA[17]outCELL_E[1].OUT_BEL[9]
MIMRXWDATA[18]outCELL_E[1].OUT_BEL[10]
MIMRXWDATA[19]outCELL_E[1].OUT_BEL[11]
MIMRXWDATA[20]outCELL_E[2].OUT_BEL[8]
MIMRXWDATA[21]outCELL_E[2].OUT_BEL[9]
MIMRXWDATA[22]outCELL_E[2].OUT_BEL[10]
MIMRXWDATA[23]outCELL_E[2].OUT_BEL[11]
MIMRXWDATA[24]outCELL_E[3].OUT_BEL[8]
MIMRXWDATA[25]outCELL_E[3].OUT_BEL[9]
MIMRXWDATA[26]outCELL_E[3].OUT_BEL[10]
MIMRXWDATA[27]outCELL_E[3].OUT_BEL[11]
MIMRXWDATA[28]outCELL_E[4].OUT_BEL[10]
MIMRXWDATA[29]outCELL_E[4].OUT_BEL[11]
MIMRXWDATA[30]outCELL_E[4].OUT_BEL[12]
MIMRXWDATA[31]outCELL_E[4].OUT_BEL[13]
MIMRXWDATA[32]outCELL_E[5].OUT_BEL[8]
MIMRXWDATA[33]outCELL_E[5].OUT_BEL[9]
MIMRXWDATA[34]outCELL_E[5].OUT_BEL[10]
MIMRXWDATA[35]outCELL_E[5].OUT_BEL[11]
MIMRXWDATA[36]outCELL_E[6].OUT_BEL[9]
MIMRXWDATA[37]outCELL_E[6].OUT_BEL[10]
MIMRXWDATA[38]outCELL_E[6].OUT_BEL[11]
MIMRXWDATA[39]outCELL_E[6].OUT_BEL[12]
MIMRXWDATA[40]outCELL_E[7].OUT_BEL[7]
MIMRXWDATA[41]outCELL_E[7].OUT_BEL[8]
MIMRXWDATA[42]outCELL_E[7].OUT_BEL[9]
MIMRXWDATA[43]outCELL_E[7].OUT_BEL[10]
MIMRXWDATA[44]outCELL_E[8].OUT_BEL[7]
MIMRXWDATA[45]outCELL_E[8].OUT_BEL[8]
MIMRXWDATA[46]outCELL_E[8].OUT_BEL[9]
MIMRXWDATA[47]outCELL_E[8].OUT_BEL[10]
MIMRXWDATA[48]outCELL_E[9].OUT_BEL[8]
MIMRXWDATA[49]outCELL_E[9].OUT_BEL[9]
MIMRXWDATA[50]outCELL_E[9].OUT_BEL[10]
MIMRXWDATA[51]outCELL_E[9].OUT_BEL[11]
MIMRXWDATA[52]outCELL_E[10].OUT_BEL[8]
MIMRXWDATA[53]outCELL_E[10].OUT_BEL[9]
MIMRXWDATA[54]outCELL_E[10].OUT_BEL[10]
MIMRXWDATA[55]outCELL_E[10].OUT_BEL[11]
MIMRXWDATA[56]outCELL_E[11].OUT_BEL[8]
MIMRXWDATA[57]outCELL_E[11].OUT_BEL[9]
MIMRXWDATA[58]outCELL_E[11].OUT_BEL[10]
MIMRXWDATA[59]outCELL_E[11].OUT_BEL[11]
MIMRXWDATA[60]outCELL_E[12].OUT_BEL[8]
MIMRXWDATA[61]outCELL_E[12].OUT_BEL[9]
MIMRXWDATA[62]outCELL_E[12].OUT_BEL[10]
MIMRXWDATA[63]outCELL_E[12].OUT_BEL[11]
MIMRXWDATA[64]outCELL_E[13].OUT_BEL[8]
MIMRXWDATA[65]outCELL_E[13].OUT_BEL[9]
MIMRXWDATA[66]outCELL_E[13].OUT_BEL[10]
MIMRXWDATA[67]outCELL_E[13].OUT_BEL[11]
MIMRXWENoutCELL_E[17].OUT_BEL[8]
MIMTXRADDR[0]outCELL_W[7].OUT_BEL[8]
MIMTXRADDR[1]outCELL_W[7].OUT_BEL[9]
MIMTXRADDR[2]outCELL_W[6].OUT_BEL[5]
MIMTXRADDR[3]outCELL_W[6].OUT_BEL[7]
MIMTXRADDR[4]outCELL_W[6].OUT_BEL[8]
MIMTXRADDR[5]outCELL_W[6].OUT_BEL[9]
MIMTXRADDR[6]outCELL_W[5].OUT_BEL[4]
MIMTXRADDR[7]outCELL_W[5].OUT_BEL[5]
MIMTXRADDR[8]outCELL_W[5].OUT_BEL[6]
MIMTXRADDR[9]outCELL_W[5].OUT_BEL[7]
MIMTXRADDR[10]outCELL_W[4].OUT_BEL[6]
MIMTXRADDR[11]outCELL_W[4].OUT_BEL[7]
MIMTXRADDR[12]outCELL_W[4].OUT_BEL[8]
MIMTXRCEoutCELL_W[3].OUT_BEL[4]
MIMTXRENoutCELL_W[4].OUT_BEL[9]
MIMTXWADDR[0]outCELL_W[11].OUT_BEL[4]
MIMTXWADDR[1]outCELL_W[11].OUT_BEL[5]
MIMTXWADDR[2]outCELL_W[11].OUT_BEL[6]
MIMTXWADDR[3]outCELL_W[11].OUT_BEL[7]
MIMTXWADDR[4]outCELL_W[10].OUT_BEL[4]
MIMTXWADDR[5]outCELL_W[10].OUT_BEL[5]
MIMTXWADDR[6]outCELL_W[10].OUT_BEL[6]
MIMTXWADDR[7]outCELL_W[10].OUT_BEL[7]
MIMTXWADDR[8]outCELL_W[9].OUT_BEL[4]
MIMTXWADDR[9]outCELL_W[9].OUT_BEL[5]
MIMTXWADDR[10]outCELL_W[9].OUT_BEL[6]
MIMTXWADDR[11]outCELL_W[9].OUT_BEL[7]
MIMTXWADDR[12]outCELL_W[8].OUT_BEL[8]
MIMTXWDATA[0]outCELL_E[2].OUT_BEL[7]
MIMTXWDATA[1]outCELL_E[3].OUT_BEL[4]
MIMTXWDATA[2]outCELL_E[3].OUT_BEL[5]
MIMTXWDATA[3]outCELL_E[3].OUT_BEL[6]
MIMTXWDATA[4]outCELL_E[3].OUT_BEL[7]
MIMTXWDATA[5]outCELL_E[4].OUT_BEL[6]
MIMTXWDATA[6]outCELL_E[4].OUT_BEL[7]
MIMTXWDATA[7]outCELL_E[4].OUT_BEL[8]
MIMTXWDATA[8]outCELL_E[4].OUT_BEL[9]
MIMTXWDATA[9]outCELL_E[5].OUT_BEL[4]
MIMTXWDATA[10]outCELL_E[5].OUT_BEL[5]
MIMTXWDATA[11]outCELL_E[5].OUT_BEL[6]
MIMTXWDATA[12]outCELL_E[5].OUT_BEL[7]
MIMTXWDATA[13]outCELL_E[6].OUT_BEL[5]
MIMTXWDATA[14]outCELL_E[6].OUT_BEL[7]
MIMTXWDATA[15]outCELL_E[9].OUT_BEL[4]
MIMTXWDATA[16]outCELL_E[9].OUT_BEL[5]
MIMTXWDATA[17]outCELL_E[9].OUT_BEL[6]
MIMTXWDATA[18]outCELL_E[9].OUT_BEL[7]
MIMTXWDATA[19]outCELL_E[10].OUT_BEL[4]
MIMTXWDATA[20]outCELL_E[10].OUT_BEL[5]
MIMTXWDATA[21]outCELL_E[10].OUT_BEL[6]
MIMTXWDATA[22]outCELL_E[10].OUT_BEL[7]
MIMTXWDATA[23]outCELL_E[11].OUT_BEL[4]
MIMTXWDATA[24]outCELL_E[11].OUT_BEL[5]
MIMTXWDATA[25]outCELL_E[11].OUT_BEL[6]
MIMTXWDATA[26]outCELL_E[11].OUT_BEL[7]
MIMTXWDATA[27]outCELL_E[12].OUT_BEL[4]
MIMTXWDATA[28]outCELL_E[12].OUT_BEL[5]
MIMTXWDATA[29]outCELL_E[12].OUT_BEL[6]
MIMTXWDATA[30]outCELL_E[12].OUT_BEL[7]
MIMTXWDATA[31]outCELL_E[13].OUT_BEL[4]
MIMTXWDATA[32]outCELL_E[13].OUT_BEL[5]
MIMTXWDATA[33]outCELL_E[13].OUT_BEL[6]
MIMTXWDATA[34]outCELL_E[13].OUT_BEL[7]
MIMTXWDATA[35]outCELL_E[14].OUT_BEL[6]
MIMTXWDATA[36]outCELL_E[14].OUT_BEL[7]
MIMTXWDATA[37]outCELL_E[14].OUT_BEL[8]
MIMTXWDATA[38]outCELL_E[14].OUT_BEL[9]
MIMTXWDATA[39]outCELL_E[15].OUT_BEL[4]
MIMTXWDATA[40]outCELL_E[15].OUT_BEL[5]
MIMTXWDATA[41]outCELL_E[15].OUT_BEL[6]
MIMTXWDATA[42]outCELL_E[15].OUT_BEL[7]
MIMTXWDATA[43]outCELL_E[16].OUT_BEL[5]
MIMTXWDATA[44]outCELL_E[16].OUT_BEL[7]
MIMTXWDATA[45]outCELL_E[19].OUT_BEL[4]
MIMTXWDATA[46]outCELL_E[19].OUT_BEL[5]
MIMTXWDATA[47]outCELL_E[19].OUT_BEL[6]
MIMTXWDATA[48]outCELL_E[19].OUT_BEL[7]
MIMTXWDATA[49]outCELL_W[19].OUT_BEL[4]
MIMTXWDATA[50]outCELL_W[19].OUT_BEL[5]
MIMTXWDATA[51]outCELL_W[19].OUT_BEL[6]
MIMTXWDATA[52]outCELL_W[19].OUT_BEL[7]
MIMTXWDATA[53]outCELL_W[15].OUT_BEL[4]
MIMTXWDATA[54]outCELL_W[15].OUT_BEL[5]
MIMTXWDATA[55]outCELL_W[15].OUT_BEL[6]
MIMTXWDATA[56]outCELL_W[15].OUT_BEL[7]
MIMTXWDATA[57]outCELL_W[14].OUT_BEL[6]
MIMTXWDATA[58]outCELL_W[14].OUT_BEL[7]
MIMTXWDATA[59]outCELL_W[14].OUT_BEL[8]
MIMTXWDATA[60]outCELL_W[14].OUT_BEL[9]
MIMTXWDATA[61]outCELL_W[13].OUT_BEL[4]
MIMTXWDATA[62]outCELL_W[13].OUT_BEL[5]
MIMTXWDATA[63]outCELL_W[13].OUT_BEL[6]
MIMTXWDATA[64]outCELL_W[13].OUT_BEL[7]
MIMTXWDATA[65]outCELL_W[12].OUT_BEL[4]
MIMTXWDATA[66]outCELL_W[12].OUT_BEL[5]
MIMTXWDATA[67]outCELL_W[12].OUT_BEL[6]
MIMTXWDATA[68]outCELL_W[12].OUT_BEL[7]
MIMTXWENoutCELL_W[8].OUT_BEL[9]
PIPETXDEEMPHoutCELL_W[13].OUT_BEL[16]
PIPETXMARGIN[0]outCELL_W[0].OUT_BEL[18]
PIPETXMARGIN[1]outCELL_W[0].OUT_BEL[16]
PIPETXMARGIN[2]outCELL_W[0].OUT_BEL[6]
PIPETXRATEoutCELL_W[16].OUT_BEL[18]
PIPETXRCVRDEToutCELL_W[14].OUT_BEL[15]
PIPETXRESEToutCELL_W[16].OUT_BEL[9]
PIPERX0POLARITYoutCELL_E[11].OUT_BEL[18]
PIPETX0CHARISK[0]outCELL_E[15].OUT_BEL[18]
PIPETX0CHARISK[1]outCELL_E[15].OUT_BEL[23]
PIPETX0COMPLIANCEoutCELL_E[15].OUT_BEL[16]
PIPETX0DATA[0]outCELL_E[18].OUT_BEL[16]
PIPETX0DATA[1]outCELL_E[18].OUT_BEL[21]
PIPETX0DATA[2]outCELL_E[18].OUT_BEL[23]
PIPETX0DATA[3]outCELL_E[18].OUT_BEL[1]
PIPETX0DATA[4]outCELL_E[18].OUT_BEL[6]
PIPETX0DATA[5]outCELL_E[18].OUT_BEL[18]
PIPETX0DATA[6]outCELL_E[17].OUT_BEL[18]
PIPETX0DATA[7]outCELL_E[17].OUT_BEL[16]
PIPETX0DATA[8]outCELL_E[17].OUT_BEL[6]
PIPETX0DATA[9]outCELL_E[17].OUT_BEL[23]
PIPETX0DATA[10]outCELL_E[17].OUT_BEL[21]
PIPETX0DATA[11]outCELL_E[17].OUT_BEL[1]
PIPETX0DATA[12]outCELL_E[16].OUT_BEL[16]
PIPETX0DATA[13]outCELL_E[16].OUT_BEL[6]
PIPETX0DATA[14]outCELL_E[16].OUT_BEL[23]
PIPETX0DATA[15]outCELL_E[16].OUT_BEL[21]
PIPETX0ELECIDLEoutCELL_E[14].OUT_BEL[1]
PIPETX0POWERDOWN[0]outCELL_E[14].OUT_BEL[21]
PIPETX0POWERDOWN[1]outCELL_E[14].OUT_BEL[23]
PIPERX1POLARITYoutCELL_E[1].OUT_BEL[18]
PIPETX1CHARISK[0]outCELL_E[5].OUT_BEL[18]
PIPETX1CHARISK[1]outCELL_E[5].OUT_BEL[23]
PIPETX1COMPLIANCEoutCELL_E[5].OUT_BEL[16]
PIPETX1DATA[0]outCELL_E[8].OUT_BEL[16]
PIPETX1DATA[1]outCELL_E[8].OUT_BEL[21]
PIPETX1DATA[2]outCELL_E[8].OUT_BEL[23]
PIPETX1DATA[3]outCELL_E[8].OUT_BEL[1]
PIPETX1DATA[4]outCELL_E[8].OUT_BEL[6]
PIPETX1DATA[5]outCELL_E[8].OUT_BEL[18]
PIPETX1DATA[6]outCELL_E[7].OUT_BEL[18]
PIPETX1DATA[7]outCELL_E[7].OUT_BEL[16]
PIPETX1DATA[8]outCELL_E[7].OUT_BEL[6]
PIPETX1DATA[9]outCELL_E[7].OUT_BEL[23]
PIPETX1DATA[10]outCELL_E[7].OUT_BEL[21]
PIPETX1DATA[11]outCELL_E[7].OUT_BEL[1]
PIPETX1DATA[12]outCELL_E[6].OUT_BEL[16]
PIPETX1DATA[13]outCELL_E[6].OUT_BEL[6]
PIPETX1DATA[14]outCELL_E[6].OUT_BEL[23]
PIPETX1DATA[15]outCELL_E[6].OUT_BEL[21]
PIPETX1ELECIDLEoutCELL_E[4].OUT_BEL[1]
PIPETX1POWERDOWN[0]outCELL_E[4].OUT_BEL[21]
PIPETX1POWERDOWN[1]outCELL_E[4].OUT_BEL[23]
PIPERX2POLARITYoutCELL_W[11].OUT_BEL[18]
PIPETX2CHARISK[0]outCELL_W[15].OUT_BEL[18]
PIPETX2CHARISK[1]outCELL_W[15].OUT_BEL[23]
PIPETX2COMPLIANCEoutCELL_W[15].OUT_BEL[16]
PIPETX2DATA[0]outCELL_W[18].OUT_BEL[16]
PIPETX2DATA[1]outCELL_W[18].OUT_BEL[21]
PIPETX2DATA[2]outCELL_W[18].OUT_BEL[23]
PIPETX2DATA[3]outCELL_W[18].OUT_BEL[1]
PIPETX2DATA[4]outCELL_W[18].OUT_BEL[6]
PIPETX2DATA[5]outCELL_W[18].OUT_BEL[18]
PIPETX2DATA[6]outCELL_W[17].OUT_BEL[18]
PIPETX2DATA[7]outCELL_W[17].OUT_BEL[16]
PIPETX2DATA[8]outCELL_W[17].OUT_BEL[6]
PIPETX2DATA[9]outCELL_W[17].OUT_BEL[23]
PIPETX2DATA[10]outCELL_W[17].OUT_BEL[21]
PIPETX2DATA[11]outCELL_W[17].OUT_BEL[1]
PIPETX2DATA[12]outCELL_W[16].OUT_BEL[16]
PIPETX2DATA[13]outCELL_W[16].OUT_BEL[6]
PIPETX2DATA[14]outCELL_W[16].OUT_BEL[23]
PIPETX2DATA[15]outCELL_W[16].OUT_BEL[21]
PIPETX2ELECIDLEoutCELL_W[14].OUT_BEL[1]
PIPETX2POWERDOWN[0]outCELL_W[14].OUT_BEL[21]
PIPETX2POWERDOWN[1]outCELL_W[14].OUT_BEL[23]
PIPERX3POLARITYoutCELL_W[1].OUT_BEL[18]
PIPETX3CHARISK[0]outCELL_W[5].OUT_BEL[18]
PIPETX3CHARISK[1]outCELL_W[5].OUT_BEL[23]
PIPETX3COMPLIANCEoutCELL_W[5].OUT_BEL[16]
PIPETX3DATA[0]outCELL_W[8].OUT_BEL[16]
PIPETX3DATA[1]outCELL_W[8].OUT_BEL[21]
PIPETX3DATA[2]outCELL_W[8].OUT_BEL[23]
PIPETX3DATA[3]outCELL_W[8].OUT_BEL[1]
PIPETX3DATA[4]outCELL_W[8].OUT_BEL[6]
PIPETX3DATA[5]outCELL_W[8].OUT_BEL[18]
PIPETX3DATA[6]outCELL_W[7].OUT_BEL[18]
PIPETX3DATA[7]outCELL_W[7].OUT_BEL[16]
PIPETX3DATA[8]outCELL_W[7].OUT_BEL[6]
PIPETX3DATA[9]outCELL_W[7].OUT_BEL[23]
PIPETX3DATA[10]outCELL_W[7].OUT_BEL[21]
PIPETX3DATA[11]outCELL_W[7].OUT_BEL[1]
PIPETX3DATA[12]outCELL_W[6].OUT_BEL[16]
PIPETX3DATA[13]outCELL_W[6].OUT_BEL[6]
PIPETX3DATA[14]outCELL_W[6].OUT_BEL[23]
PIPETX3DATA[15]outCELL_W[6].OUT_BEL[21]
PIPETX3ELECIDLEoutCELL_W[4].OUT_BEL[1]
PIPETX3POWERDOWN[0]outCELL_W[4].OUT_BEL[21]
PIPETX3POWERDOWN[1]outCELL_W[4].OUT_BEL[23]
PIPERX4POLARITYoutCELL_E[11].OUT_BEL[22]
PIPETX4CHARISK[0]outCELL_E[15].OUT_BEL[22]
PIPETX4CHARISK[1]outCELL_E[15].OUT_BEL[19]
PIPETX4COMPLIANCEoutCELL_E[15].OUT_BEL[20]
PIPETX4DATA[0]outCELL_E[18].OUT_BEL[20]
PIPETX4DATA[1]outCELL_E[18].OUT_BEL[17]
PIPETX4DATA[2]outCELL_E[18].OUT_BEL[19]
PIPETX4DATA[3]outCELL_E[18].OUT_BEL[5]
PIPETX4DATA[4]outCELL_E[18].OUT_BEL[2]
PIPETX4DATA[5]outCELL_E[18].OUT_BEL[22]
PIPETX4DATA[6]outCELL_E[17].OUT_BEL[22]
PIPETX4DATA[7]outCELL_E[17].OUT_BEL[20]
PIPETX4DATA[8]outCELL_E[17].OUT_BEL[2]
PIPETX4DATA[9]outCELL_E[17].OUT_BEL[19]
PIPETX4DATA[10]outCELL_E[17].OUT_BEL[17]
PIPETX4DATA[11]outCELL_E[17].OUT_BEL[5]
PIPETX4DATA[12]outCELL_E[16].OUT_BEL[20]
PIPETX4DATA[13]outCELL_E[16].OUT_BEL[2]
PIPETX4DATA[14]outCELL_E[16].OUT_BEL[19]
PIPETX4DATA[15]outCELL_E[16].OUT_BEL[17]
PIPETX4ELECIDLEoutCELL_E[14].OUT_BEL[5]
PIPETX4POWERDOWN[0]outCELL_E[14].OUT_BEL[17]
PIPETX4POWERDOWN[1]outCELL_E[14].OUT_BEL[19]
PIPERX5POLARITYoutCELL_E[1].OUT_BEL[22]
PIPETX5CHARISK[0]outCELL_E[5].OUT_BEL[22]
PIPETX5CHARISK[1]outCELL_E[5].OUT_BEL[19]
PIPETX5COMPLIANCEoutCELL_E[5].OUT_BEL[20]
PIPETX5DATA[0]outCELL_E[8].OUT_BEL[20]
PIPETX5DATA[1]outCELL_E[8].OUT_BEL[17]
PIPETX5DATA[2]outCELL_E[8].OUT_BEL[19]
PIPETX5DATA[3]outCELL_E[8].OUT_BEL[5]
PIPETX5DATA[4]outCELL_E[8].OUT_BEL[2]
PIPETX5DATA[5]outCELL_E[8].OUT_BEL[22]
PIPETX5DATA[6]outCELL_E[7].OUT_BEL[22]
PIPETX5DATA[7]outCELL_E[7].OUT_BEL[20]
PIPETX5DATA[8]outCELL_E[7].OUT_BEL[2]
PIPETX5DATA[9]outCELL_E[7].OUT_BEL[19]
PIPETX5DATA[10]outCELL_E[7].OUT_BEL[17]
PIPETX5DATA[11]outCELL_E[7].OUT_BEL[5]
PIPETX5DATA[12]outCELL_E[6].OUT_BEL[20]
PIPETX5DATA[13]outCELL_E[6].OUT_BEL[2]
PIPETX5DATA[14]outCELL_E[6].OUT_BEL[19]
PIPETX5DATA[15]outCELL_E[6].OUT_BEL[17]
PIPETX5ELECIDLEoutCELL_E[4].OUT_BEL[5]
PIPETX5POWERDOWN[0]outCELL_E[4].OUT_BEL[17]
PIPETX5POWERDOWN[1]outCELL_E[4].OUT_BEL[19]
PIPERX6POLARITYoutCELL_W[11].OUT_BEL[22]
PIPETX6CHARISK[0]outCELL_W[15].OUT_BEL[22]
PIPETX6CHARISK[1]outCELL_W[15].OUT_BEL[19]
PIPETX6COMPLIANCEoutCELL_W[15].OUT_BEL[20]
PIPETX6DATA[0]outCELL_W[18].OUT_BEL[20]
PIPETX6DATA[1]outCELL_W[18].OUT_BEL[17]
PIPETX6DATA[2]outCELL_W[18].OUT_BEL[19]
PIPETX6DATA[3]outCELL_W[18].OUT_BEL[5]
PIPETX6DATA[4]outCELL_W[18].OUT_BEL[2]
PIPETX6DATA[5]outCELL_W[18].OUT_BEL[22]
PIPETX6DATA[6]outCELL_W[17].OUT_BEL[22]
PIPETX6DATA[7]outCELL_W[17].OUT_BEL[20]
PIPETX6DATA[8]outCELL_W[17].OUT_BEL[2]
PIPETX6DATA[9]outCELL_W[17].OUT_BEL[19]
PIPETX6DATA[10]outCELL_W[17].OUT_BEL[17]
PIPETX6DATA[11]outCELL_W[17].OUT_BEL[5]
PIPETX6DATA[12]outCELL_W[16].OUT_BEL[20]
PIPETX6DATA[13]outCELL_W[16].OUT_BEL[2]
PIPETX6DATA[14]outCELL_W[16].OUT_BEL[19]
PIPETX6DATA[15]outCELL_W[16].OUT_BEL[17]
PIPETX6ELECIDLEoutCELL_W[14].OUT_BEL[5]
PIPETX6POWERDOWN[0]outCELL_W[14].OUT_BEL[17]
PIPETX6POWERDOWN[1]outCELL_W[14].OUT_BEL[19]
PIPERX7POLARITYoutCELL_W[1].OUT_BEL[22]
PIPETX7CHARISK[0]outCELL_W[5].OUT_BEL[22]
PIPETX7CHARISK[1]outCELL_W[5].OUT_BEL[19]
PIPETX7COMPLIANCEoutCELL_W[5].OUT_BEL[20]
PIPETX7DATA[0]outCELL_W[8].OUT_BEL[20]
PIPETX7DATA[1]outCELL_W[8].OUT_BEL[17]
PIPETX7DATA[2]outCELL_W[8].OUT_BEL[19]
PIPETX7DATA[3]outCELL_W[8].OUT_BEL[5]
PIPETX7DATA[4]outCELL_W[8].OUT_BEL[2]
PIPETX7DATA[5]outCELL_W[8].OUT_BEL[22]
PIPETX7DATA[6]outCELL_W[7].OUT_BEL[22]
PIPETX7DATA[7]outCELL_W[7].OUT_BEL[20]
PIPETX7DATA[8]outCELL_W[7].OUT_BEL[2]
PIPETX7DATA[9]outCELL_W[7].OUT_BEL[19]
PIPETX7DATA[10]outCELL_W[7].OUT_BEL[17]
PIPETX7DATA[11]outCELL_W[7].OUT_BEL[5]
PIPETX7DATA[12]outCELL_W[6].OUT_BEL[20]
PIPETX7DATA[13]outCELL_W[6].OUT_BEL[2]
PIPETX7DATA[14]outCELL_W[6].OUT_BEL[19]
PIPETX7DATA[15]outCELL_W[6].OUT_BEL[17]
PIPETX7ELECIDLEoutCELL_W[4].OUT_BEL[5]
PIPETX7POWERDOWN[0]outCELL_W[4].OUT_BEL[17]
PIPETX7POWERDOWN[1]outCELL_W[4].OUT_BEL[19]
LNKCLKENoutCELL_W[9].OUT_BEL[21]
RECEIVEDFUNCLVLRSTNoutCELL_E[2].OUT_BEL[14]
LL2BADDLLPERRNoutCELL_E[1].OUT_BEL[12]
LL2BADTLPERRNoutCELL_W[0].OUT_BEL[12]
LL2PROTOCOLERRNoutCELL_W[0].OUT_BEL[11]
LL2REPLAYROERRNoutCELL_E[1].OUT_BEL[13]
LL2REPLAYTOERRNoutCELL_E[1].OUT_BEL[14]
LL2SUSPENDOKNoutCELL_W[1].OUT_BEL[8]
LL2TFCINIT1SEQNoutCELL_W[3].OUT_BEL[11]
LL2TFCINIT2SEQNoutCELL_W[2].OUT_BEL[8]
TL2ASPMSUSPENDCREDITCHECKOKNoutCELL_W[1].OUT_BEL[11]
TL2ASPMSUSPENDREQNoutCELL_W[1].OUT_BEL[10]
TL2PPMSUSPENDOKNoutCELL_W[1].OUT_BEL[9]
DBGSCLRAoutCELL_E[10].OUT_BEL[20]
DBGSCLRBoutCELL_E[11].OUT_BEL[19]
DBGSCLRCoutCELL_E[12].OUT_BEL[19]
DBGSCLRDoutCELL_E[12].OUT_BEL[20]
DBGSCLREoutCELL_E[13].OUT_BEL[19]
DBGSCLRFoutCELL_E[13].OUT_BEL[20]
DBGSCLRGoutCELL_E[14].OUT_BEL[15]
DBGSCLRHoutCELL_E[14].OUT_BEL[16]
DBGSCLRIoutCELL_E[15].OUT_BEL[13]
DBGSCLRJoutCELL_E[15].OUT_BEL[14]
DBGSCLRKoutCELL_E[15].OUT_BEL[15]
DBGVECA[0]outCELL_W[10].OUT_BEL[21]
DBGVECA[1]outCELL_W[10].OUT_BEL[22]
DBGVECA[2]outCELL_W[10].OUT_BEL[23]
DBGVECA[3]outCELL_W[9].OUT_BEL[20]
DBGVECA[4]outCELL_W[7].OUT_BEL[13]
DBGVECA[5]outCELL_W[7].OUT_BEL[14]
DBGVECA[6]outCELL_W[7].OUT_BEL[15]
DBGVECA[7]outCELL_W[6].OUT_BEL[15]
DBGVECA[8]outCELL_W[6].OUT_BEL[18]
DBGVECA[9]outCELL_W[6].OUT_BEL[22]
DBGVECA[10]outCELL_W[5].OUT_BEL[15]
DBGVECA[11]outCELL_W[5].OUT_BEL[17]
DBGVECA[12]outCELL_W[5].OUT_BEL[21]
DBGVECA[13]outCELL_W[4].OUT_BEL[18]
DBGVECA[14]outCELL_W[4].OUT_BEL[20]
DBGVECA[15]outCELL_W[4].OUT_BEL[22]
DBGVECA[16]outCELL_W[3].OUT_BEL[20]
DBGVECA[17]outCELL_W[3].OUT_BEL[21]
DBGVECA[18]outCELL_W[3].OUT_BEL[22]
DBGVECA[19]outCELL_W[3].OUT_BEL[23]
DBGVECA[20]outCELL_W[2].OUT_BEL[20]
DBGVECA[21]outCELL_W[2].OUT_BEL[21]
DBGVECA[22]outCELL_W[2].OUT_BEL[22]
DBGVECA[23]outCELL_W[2].OUT_BEL[23]
DBGVECA[24]outCELL_W[1].OUT_BEL[21]
DBGVECA[25]outCELL_W[1].OUT_BEL[23]
DBGVECA[26]outCELL_W[0].OUT_BEL[19]
DBGVECA[27]outCELL_W[0].OUT_BEL[20]
DBGVECA[28]outCELL_W[0].OUT_BEL[21]
DBGVECA[29]outCELL_W[0].OUT_BEL[22]
DBGVECA[30]outCELL_E[0].OUT_BEL[21]
DBGVECA[31]outCELL_E[0].OUT_BEL[22]
DBGVECA[32]outCELL_E[0].OUT_BEL[23]
DBGVECA[33]outCELL_E[1].OUT_BEL[20]
DBGVECA[34]outCELL_E[1].OUT_BEL[21]
DBGVECA[35]outCELL_E[1].OUT_BEL[23]
DBGVECA[36]outCELL_E[2].OUT_BEL[21]
DBGVECA[37]outCELL_E[2].OUT_BEL[22]
DBGVECA[38]outCELL_E[2].OUT_BEL[23]
DBGVECA[39]outCELL_E[3].OUT_BEL[21]
DBGVECA[40]outCELL_E[3].OUT_BEL[22]
DBGVECA[41]outCELL_E[3].OUT_BEL[23]
DBGVECA[42]outCELL_E[4].OUT_BEL[18]
DBGVECA[43]outCELL_E[4].OUT_BEL[20]
DBGVECA[44]outCELL_E[4].OUT_BEL[22]
DBGVECA[45]outCELL_E[5].OUT_BEL[17]
DBGVECA[46]outCELL_E[5].OUT_BEL[21]
DBGVECA[47]outCELL_E[6].OUT_BEL[13]
DBGVECA[48]outCELL_E[6].OUT_BEL[14]
DBGVECA[49]outCELL_E[6].OUT_BEL[15]
DBGVECA[50]outCELL_E[6].OUT_BEL[18]
DBGVECA[51]outCELL_E[7].OUT_BEL[11]
DBGVECA[52]outCELL_E[7].OUT_BEL[12]
DBGVECA[53]outCELL_E[7].OUT_BEL[13]
DBGVECA[54]outCELL_E[7].OUT_BEL[14]
DBGVECA[55]outCELL_E[8].OUT_BEL[11]
DBGVECA[56]outCELL_E[8].OUT_BEL[12]
DBGVECA[57]outCELL_E[8].OUT_BEL[13]
DBGVECA[58]outCELL_E[8].OUT_BEL[14]
DBGVECA[59]outCELL_E[9].OUT_BEL[21]
DBGVECA[60]outCELL_E[9].OUT_BEL[22]
DBGVECA[61]outCELL_E[9].OUT_BEL[23]
DBGVECA[62]outCELL_E[10].OUT_BEL[21]
DBGVECA[63]outCELL_E[10].OUT_BEL[22]
DBGVECB[0]outCELL_E[10].OUT_BEL[23]
DBGVECB[1]outCELL_E[11].OUT_BEL[20]
DBGVECB[2]outCELL_E[11].OUT_BEL[21]
DBGVECB[3]outCELL_E[11].OUT_BEL[23]
DBGVECB[4]outCELL_E[12].OUT_BEL[21]
DBGVECB[5]outCELL_E[12].OUT_BEL[22]
DBGVECB[6]outCELL_E[12].OUT_BEL[23]
DBGVECB[7]outCELL_E[13].OUT_BEL[21]
DBGVECB[8]outCELL_E[13].OUT_BEL[22]
DBGVECB[9]outCELL_E[13].OUT_BEL[23]
DBGVECB[10]outCELL_E[14].OUT_BEL[18]
DBGVECB[11]outCELL_E[14].OUT_BEL[20]
DBGVECB[12]outCELL_E[14].OUT_BEL[22]
DBGVECB[13]outCELL_E[15].OUT_BEL[17]
DBGVECB[14]outCELL_E[15].OUT_BEL[21]
DBGVECB[15]outCELL_E[16].OUT_BEL[13]
DBGVECB[16]outCELL_E[16].OUT_BEL[14]
DBGVECB[17]outCELL_E[16].OUT_BEL[15]
DBGVECB[18]outCELL_E[16].OUT_BEL[18]
DBGVECB[19]outCELL_E[17].OUT_BEL[11]
DBGVECB[20]outCELL_E[17].OUT_BEL[12]
DBGVECB[21]outCELL_E[17].OUT_BEL[13]
DBGVECB[22]outCELL_E[17].OUT_BEL[14]
DBGVECB[23]outCELL_E[18].OUT_BEL[11]
DBGVECB[24]outCELL_E[18].OUT_BEL[12]
DBGVECB[25]outCELL_E[18].OUT_BEL[13]
DBGVECB[26]outCELL_E[18].OUT_BEL[14]
DBGVECB[27]outCELL_E[19].OUT_BEL[21]
DBGVECB[28]outCELL_E[19].OUT_BEL[22]
DBGVECB[29]outCELL_E[19].OUT_BEL[23]
DBGVECB[30]outCELL_W[19].OUT_BEL[23]
DBGVECB[31]outCELL_W[18].OUT_BEL[14]
DBGVECB[32]outCELL_W[18].OUT_BEL[15]
DBGVECB[33]outCELL_W[17].OUT_BEL[13]
DBGVECB[34]outCELL_W[17].OUT_BEL[14]
DBGVECB[35]outCELL_W[17].OUT_BEL[15]
DBGVECB[36]outCELL_W[16].OUT_BEL[14]
DBGVECB[37]outCELL_W[16].OUT_BEL[15]
DBGVECB[38]outCELL_W[16].OUT_BEL[22]
DBGVECB[39]outCELL_W[15].OUT_BEL[17]
DBGVECB[40]outCELL_W[15].OUT_BEL[21]
DBGVECB[41]outCELL_W[14].OUT_BEL[18]
DBGVECB[42]outCELL_W[14].OUT_BEL[20]
DBGVECB[43]outCELL_W[14].OUT_BEL[22]
DBGVECB[44]outCELL_W[13].OUT_BEL[21]
DBGVECB[45]outCELL_W[13].OUT_BEL[22]
DBGVECB[46]outCELL_W[13].OUT_BEL[23]
DBGVECB[47]outCELL_W[12].OUT_BEL[22]
DBGVECB[48]outCELL_W[12].OUT_BEL[23]
DBGVECB[49]outCELL_W[8].OUT_BEL[11]
DBGVECB[50]outCELL_W[8].OUT_BEL[15]
DBGVECB[51]outCELL_W[7].OUT_BEL[11]
DBGVECB[52]outCELL_W[7].OUT_BEL[12]
DBGVECB[53]outCELL_W[6].OUT_BEL[13]
DBGVECB[54]outCELL_W[6].OUT_BEL[14]
DBGVECB[55]outCELL_W[5].OUT_BEL[13]
DBGVECB[56]outCELL_W[5].OUT_BEL[14]
DBGVECB[57]outCELL_W[4].OUT_BEL[16]
DBGVECB[58]outCELL_W[1].OUT_BEL[20]
DBGVECB[59]outCELL_W[0].OUT_BEL[23]
DBGVECB[60]outCELL_E[1].OUT_BEL[19]
DBGVECB[61]outCELL_E[2].OUT_BEL[19]
DBGVECB[62]outCELL_E[2].OUT_BEL[20]
DBGVECB[63]outCELL_E[3].OUT_BEL[19]
DBGVECC[0]outCELL_E[3].OUT_BEL[20]
DBGVECC[1]outCELL_E[4].OUT_BEL[15]
DBGVECC[2]outCELL_E[4].OUT_BEL[16]
DBGVECC[3]outCELL_E[5].OUT_BEL[13]
DBGVECC[4]outCELL_E[5].OUT_BEL[14]
DBGVECC[5]outCELL_E[5].OUT_BEL[15]
DBGVECC[6]outCELL_E[6].OUT_BEL[22]
DBGVECC[7]outCELL_E[7].OUT_BEL[15]
DBGVECC[8]outCELL_E[8].OUT_BEL[15]
DBGVECC[9]outCELL_E[9].OUT_BEL[19]
DBGVECC[10]outCELL_E[9].OUT_BEL[20]
DBGVECC[11]outCELL_E[10].OUT_BEL[19]
PMVOUToutCELL_E[1].OUT_BEL[15]
XILUNCONNOUT[0]outCELL_W[15].OUT_BEL[15]
XILUNCONNOUT[1]outCELL_W[14].OUT_BEL[14]
XILUNCONNOUT[2]outCELL_W[14].OUT_BEL[16]
XILUNCONNOUT[3]outCELL_W[13].OUT_BEL[19]
virtex6 PCIE bel PCIE_V6 attribute bits
AttributePCIE
DRP[0] bit 0MAIN[0][26][0]
DRP[0] bit 1MAIN[0][27][0]
DRP[0] bit 2MAIN[0][26][1]
DRP[0] bit 3MAIN[0][27][1]
DRP[0] bit 4MAIN[0][26][2]
DRP[0] bit 5MAIN[0][27][2]
DRP[0] bit 6MAIN[0][26][3]
DRP[0] bit 7MAIN[0][27][3]
DRP[0] bit 8MAIN[0][26][4]
DRP[0] bit 9MAIN[0][27][4]
DRP[0] bit 10MAIN[0][26][5]
DRP[0] bit 11MAIN[0][27][5]
DRP[0] bit 12MAIN[0][26][6]
DRP[0] bit 13MAIN[0][27][6]
DRP[0] bit 14MAIN[0][26][7]
DRP[0] bit 15MAIN[0][27][7]
DRP[1] bit 0MAIN[0][26][8]
DRP[1] bit 1MAIN[0][27][8]
DRP[1] bit 2MAIN[0][26][9]
DRP[1] bit 3MAIN[0][27][9]
DRP[1] bit 4MAIN[0][26][10]
DRP[1] bit 5MAIN[0][27][10]
DRP[1] bit 6MAIN[0][26][11]
DRP[1] bit 7MAIN[0][27][11]
DRP[1] bit 8MAIN[0][26][12]
DRP[1] bit 9MAIN[0][27][12]
DRP[1] bit 10MAIN[0][26][13]
DRP[1] bit 11MAIN[0][27][13]
DRP[1] bit 12MAIN[0][26][14]
DRP[1] bit 13MAIN[0][27][14]
DRP[1] bit 14MAIN[0][26][15]
DRP[1] bit 15MAIN[0][27][15]
DRP[2] bit 0MAIN[0][26][16]
DRP[2] bit 1MAIN[0][27][16]
DRP[2] bit 2MAIN[0][26][17]
DRP[2] bit 3MAIN[0][27][17]
DRP[2] bit 4MAIN[0][26][18]
DRP[2] bit 5MAIN[0][27][18]
DRP[2] bit 6MAIN[0][26][19]
DRP[2] bit 7MAIN[0][27][19]
DRP[2] bit 8MAIN[0][26][20]
DRP[2] bit 9MAIN[0][27][20]
DRP[2] bit 10MAIN[0][26][21]
DRP[2] bit 11MAIN[0][27][21]
DRP[2] bit 12MAIN[0][26][22]
DRP[2] bit 13MAIN[0][27][22]
DRP[2] bit 14MAIN[0][26][23]
DRP[2] bit 15MAIN[0][27][23]
DRP[3] bit 0MAIN[0][26][24]
DRP[3] bit 1MAIN[0][27][24]
DRP[3] bit 2MAIN[0][26][25]
DRP[3] bit 3MAIN[0][27][25]
DRP[3] bit 4MAIN[0][26][26]
DRP[3] bit 5MAIN[0][27][26]
DRP[3] bit 6MAIN[0][26][27]
DRP[3] bit 7MAIN[0][27][27]
DRP[3] bit 8MAIN[0][26][28]
DRP[3] bit 9MAIN[0][27][28]
DRP[3] bit 10MAIN[0][26][29]
DRP[3] bit 11MAIN[0][27][29]
DRP[3] bit 12MAIN[0][26][30]
DRP[3] bit 13MAIN[0][27][30]
DRP[3] bit 14MAIN[0][26][31]
DRP[3] bit 15MAIN[0][27][31]
DRP[4] bit 0MAIN[0][26][32]
DRP[4] bit 1MAIN[0][27][32]
DRP[4] bit 2MAIN[0][26][33]
DRP[4] bit 3MAIN[0][27][33]
DRP[4] bit 4MAIN[0][26][34]
DRP[4] bit 5MAIN[0][27][34]
DRP[4] bit 6MAIN[0][26][35]
DRP[4] bit 7MAIN[0][27][35]
DRP[4] bit 8MAIN[0][26][36]
DRP[4] bit 9MAIN[0][27][36]
DRP[4] bit 10MAIN[0][26][37]
DRP[4] bit 11MAIN[0][27][37]
DRP[4] bit 12MAIN[0][26][38]
DRP[4] bit 13MAIN[0][27][38]
DRP[4] bit 14MAIN[0][26][39]
DRP[4] bit 15MAIN[0][27][39]
DRP[5] bit 0MAIN[0][26][40]
DRP[5] bit 1MAIN[0][27][40]
DRP[5] bit 2MAIN[0][26][41]
DRP[5] bit 3MAIN[0][27][41]
DRP[5] bit 4MAIN[0][26][42]
DRP[5] bit 5MAIN[0][27][42]
DRP[5] bit 6MAIN[0][26][43]
DRP[5] bit 7MAIN[0][27][43]
DRP[5] bit 8MAIN[0][26][44]
DRP[5] bit 9MAIN[0][27][44]
DRP[5] bit 10MAIN[0][26][45]
DRP[5] bit 11MAIN[0][27][45]
DRP[5] bit 12MAIN[0][26][46]
DRP[5] bit 13MAIN[0][27][46]
DRP[5] bit 14MAIN[0][26][47]
DRP[5] bit 15MAIN[0][27][47]
DRP[6] bit 0MAIN[1][26][0]
DRP[6] bit 1MAIN[1][27][0]
DRP[6] bit 2MAIN[1][26][1]
DRP[6] bit 3MAIN[1][27][1]
DRP[6] bit 4MAIN[1][26][2]
DRP[6] bit 5MAIN[1][27][2]
DRP[6] bit 6MAIN[1][26][3]
DRP[6] bit 7MAIN[1][27][3]
DRP[6] bit 8MAIN[1][26][4]
DRP[6] bit 9MAIN[1][27][4]
DRP[6] bit 10MAIN[1][26][5]
DRP[6] bit 11MAIN[1][27][5]
DRP[6] bit 12MAIN[1][26][6]
DRP[6] bit 13MAIN[1][27][6]
DRP[6] bit 14MAIN[1][26][7]
DRP[6] bit 15MAIN[1][27][7]
DRP[7] bit 0MAIN[1][26][8]
DRP[7] bit 1MAIN[1][27][8]
DRP[7] bit 2MAIN[1][26][9]
DRP[7] bit 3MAIN[1][27][9]
DRP[7] bit 4MAIN[1][26][10]
DRP[7] bit 5MAIN[1][27][10]
DRP[7] bit 6MAIN[1][26][11]
DRP[7] bit 7MAIN[1][27][11]
DRP[7] bit 8MAIN[1][26][12]
DRP[7] bit 9MAIN[1][27][12]
DRP[7] bit 10MAIN[1][26][13]
DRP[7] bit 11MAIN[1][27][13]
DRP[7] bit 12MAIN[1][26][14]
DRP[7] bit 13MAIN[1][27][14]
DRP[7] bit 14MAIN[1][26][15]
DRP[7] bit 15MAIN[1][27][15]
DRP[8] bit 0MAIN[1][26][16]
DRP[8] bit 1MAIN[1][27][16]
DRP[8] bit 2MAIN[1][26][17]
DRP[8] bit 3MAIN[1][27][17]
DRP[8] bit 4MAIN[1][26][18]
DRP[8] bit 5MAIN[1][27][18]
DRP[8] bit 6MAIN[1][26][19]
DRP[8] bit 7MAIN[1][27][19]
DRP[8] bit 8MAIN[1][26][20]
DRP[8] bit 9MAIN[1][27][20]
DRP[8] bit 10MAIN[1][26][21]
DRP[8] bit 11MAIN[1][27][21]
DRP[8] bit 12MAIN[1][26][22]
DRP[8] bit 13MAIN[1][27][22]
DRP[8] bit 14MAIN[1][26][23]
DRP[8] bit 15MAIN[1][27][23]
DRP[9] bit 0MAIN[1][26][24]
DRP[9] bit 1MAIN[1][27][24]
DRP[9] bit 2MAIN[1][26][25]
DRP[9] bit 3MAIN[1][27][25]
DRP[9] bit 4MAIN[1][26][26]
DRP[9] bit 5MAIN[1][27][26]
DRP[9] bit 6MAIN[1][26][27]
DRP[9] bit 7MAIN[1][27][27]
DRP[9] bit 8MAIN[1][26][28]
DRP[9] bit 9MAIN[1][27][28]
DRP[9] bit 10MAIN[1][26][29]
DRP[9] bit 11MAIN[1][27][29]
DRP[9] bit 12MAIN[1][26][30]
DRP[9] bit 13MAIN[1][27][30]
DRP[9] bit 14MAIN[1][26][31]
DRP[9] bit 15MAIN[1][27][31]
DRP[10] bit 0MAIN[1][26][32]
DRP[10] bit 1MAIN[1][27][32]
DRP[10] bit 2MAIN[1][26][33]
DRP[10] bit 3MAIN[1][27][33]
DRP[10] bit 4MAIN[1][26][34]
DRP[10] bit 5MAIN[1][27][34]
DRP[10] bit 6MAIN[1][26][35]
DRP[10] bit 7MAIN[1][27][35]
DRP[10] bit 8MAIN[1][26][36]
DRP[10] bit 9MAIN[1][27][36]
DRP[10] bit 10MAIN[1][26][37]
DRP[10] bit 11MAIN[1][27][37]
DRP[10] bit 12MAIN[1][26][38]
DRP[10] bit 13MAIN[1][27][38]
DRP[10] bit 14MAIN[1][26][39]
DRP[10] bit 15MAIN[1][27][39]
DRP[11] bit 0MAIN[1][26][40]
DRP[11] bit 1MAIN[1][27][40]
DRP[11] bit 2MAIN[1][26][41]
DRP[11] bit 3MAIN[1][27][41]
DRP[11] bit 4MAIN[1][26][42]
DRP[11] bit 5MAIN[1][27][42]
DRP[11] bit 6MAIN[1][26][43]
DRP[11] bit 7MAIN[1][27][43]
DRP[11] bit 8MAIN[1][26][44]
DRP[11] bit 9MAIN[1][27][44]
DRP[11] bit 10MAIN[1][26][45]
DRP[11] bit 11MAIN[1][27][45]
DRP[11] bit 12MAIN[1][26][46]
DRP[11] bit 13MAIN[1][27][46]
DRP[11] bit 14MAIN[1][26][47]
DRP[11] bit 15MAIN[1][27][47]
DRP[12] bit 0MAIN[2][26][0]
DRP[12] bit 1MAIN[2][27][0]
DRP[12] bit 2MAIN[2][26][1]
DRP[12] bit 3MAIN[2][27][1]
DRP[12] bit 4MAIN[2][26][2]
DRP[12] bit 5MAIN[2][27][2]
DRP[12] bit 6MAIN[2][26][3]
DRP[12] bit 7MAIN[2][27][3]
DRP[12] bit 8MAIN[2][26][4]
DRP[12] bit 9MAIN[2][27][4]
DRP[12] bit 10MAIN[2][26][5]
DRP[12] bit 11MAIN[2][27][5]
DRP[12] bit 12MAIN[2][26][6]
DRP[12] bit 13MAIN[2][27][6]
DRP[12] bit 14MAIN[2][26][7]
DRP[12] bit 15MAIN[2][27][7]
DRP[13] bit 0MAIN[2][26][8]
DRP[13] bit 1MAIN[2][27][8]
DRP[13] bit 2MAIN[2][26][9]
DRP[13] bit 3MAIN[2][27][9]
DRP[13] bit 4MAIN[2][26][10]
DRP[13] bit 5MAIN[2][27][10]
DRP[13] bit 6MAIN[2][26][11]
DRP[13] bit 7MAIN[2][27][11]
DRP[13] bit 8MAIN[2][26][12]
DRP[13] bit 9MAIN[2][27][12]
DRP[13] bit 10MAIN[2][26][13]
DRP[13] bit 11MAIN[2][27][13]
DRP[13] bit 12MAIN[2][26][14]
DRP[13] bit 13MAIN[2][27][14]
DRP[13] bit 14MAIN[2][26][15]
DRP[13] bit 15MAIN[2][27][15]
DRP[14] bit 0MAIN[2][26][16]
DRP[14] bit 1MAIN[2][27][16]
DRP[14] bit 2MAIN[2][26][17]
DRP[14] bit 3MAIN[2][27][17]
DRP[14] bit 4MAIN[2][26][18]
DRP[14] bit 5MAIN[2][27][18]
DRP[14] bit 6MAIN[2][26][19]
DRP[14] bit 7MAIN[2][27][19]
DRP[14] bit 8MAIN[2][26][20]
DRP[14] bit 9MAIN[2][27][20]
DRP[14] bit 10MAIN[2][26][21]
DRP[14] bit 11MAIN[2][27][21]
DRP[14] bit 12MAIN[2][26][22]
DRP[14] bit 13MAIN[2][27][22]
DRP[14] bit 14MAIN[2][26][23]
DRP[14] bit 15MAIN[2][27][23]
DRP[15] bit 0MAIN[2][26][24]
DRP[15] bit 1MAIN[2][27][24]
DRP[15] bit 2MAIN[2][26][25]
DRP[15] bit 3MAIN[2][27][25]
DRP[15] bit 4MAIN[2][26][26]
DRP[15] bit 5MAIN[2][27][26]
DRP[15] bit 6MAIN[2][26][27]
DRP[15] bit 7MAIN[2][27][27]
DRP[15] bit 8MAIN[2][26][28]
DRP[15] bit 9MAIN[2][27][28]
DRP[15] bit 10MAIN[2][26][29]
DRP[15] bit 11MAIN[2][27][29]
DRP[15] bit 12MAIN[2][26][30]
DRP[15] bit 13MAIN[2][27][30]
DRP[15] bit 14MAIN[2][26][31]
DRP[15] bit 15MAIN[2][27][31]
DRP[16] bit 0MAIN[2][26][32]
DRP[16] bit 1MAIN[2][27][32]
DRP[16] bit 2MAIN[2][26][33]
DRP[16] bit 3MAIN[2][27][33]
DRP[16] bit 4MAIN[2][26][34]
DRP[16] bit 5MAIN[2][27][34]
DRP[16] bit 6MAIN[2][26][35]
DRP[16] bit 7MAIN[2][27][35]
DRP[16] bit 8MAIN[2][26][36]
DRP[16] bit 9MAIN[2][27][36]
DRP[16] bit 10MAIN[2][26][37]
DRP[16] bit 11MAIN[2][27][37]
DRP[16] bit 12MAIN[2][26][38]
DRP[16] bit 13MAIN[2][27][38]
DRP[16] bit 14MAIN[2][26][39]
DRP[16] bit 15MAIN[2][27][39]
DRP[17] bit 0MAIN[2][26][40]
DRP[17] bit 1MAIN[2][27][40]
DRP[17] bit 2MAIN[2][26][41]
DRP[17] bit 3MAIN[2][27][41]
DRP[17] bit 4MAIN[2][26][42]
DRP[17] bit 5MAIN[2][27][42]
DRP[17] bit 6MAIN[2][26][43]
DRP[17] bit 7MAIN[2][27][43]
DRP[17] bit 8MAIN[2][26][44]
DRP[17] bit 9MAIN[2][27][44]
DRP[17] bit 10MAIN[2][26][45]
DRP[17] bit 11MAIN[2][27][45]
DRP[17] bit 12MAIN[2][26][46]
DRP[17] bit 13MAIN[2][27][46]
DRP[17] bit 14MAIN[2][26][47]
DRP[17] bit 15MAIN[2][27][47]
DRP[18] bit 0MAIN[3][26][0]
DRP[18] bit 1MAIN[3][27][0]
DRP[18] bit 2MAIN[3][26][1]
DRP[18] bit 3MAIN[3][27][1]
DRP[18] bit 4MAIN[3][26][2]
DRP[18] bit 5MAIN[3][27][2]
DRP[18] bit 6MAIN[3][26][3]
DRP[18] bit 7MAIN[3][27][3]
DRP[18] bit 8MAIN[3][26][4]
DRP[18] bit 9MAIN[3][27][4]
DRP[18] bit 10MAIN[3][26][5]
DRP[18] bit 11MAIN[3][27][5]
DRP[18] bit 12MAIN[3][26][6]
DRP[18] bit 13MAIN[3][27][6]
DRP[18] bit 14MAIN[3][26][7]
DRP[18] bit 15MAIN[3][27][7]
DRP[19] bit 0MAIN[3][26][8]
DRP[19] bit 1MAIN[3][27][8]
DRP[19] bit 2MAIN[3][26][9]
DRP[19] bit 3MAIN[3][27][9]
DRP[19] bit 4MAIN[3][26][10]
DRP[19] bit 5MAIN[3][27][10]
DRP[19] bit 6MAIN[3][26][11]
DRP[19] bit 7MAIN[3][27][11]
DRP[19] bit 8MAIN[3][26][12]
DRP[19] bit 9MAIN[3][27][12]
DRP[19] bit 10MAIN[3][26][13]
DRP[19] bit 11MAIN[3][27][13]
DRP[19] bit 12MAIN[3][26][14]
DRP[19] bit 13MAIN[3][27][14]
DRP[19] bit 14MAIN[3][26][15]
DRP[19] bit 15MAIN[3][27][15]
DRP[20] bit 0MAIN[3][26][16]
DRP[20] bit 1MAIN[3][27][16]
DRP[20] bit 2MAIN[3][26][17]
DRP[20] bit 3MAIN[3][27][17]
DRP[20] bit 4MAIN[3][26][18]
DRP[20] bit 5MAIN[3][27][18]
DRP[20] bit 6MAIN[3][26][19]
DRP[20] bit 7MAIN[3][27][19]
DRP[20] bit 8MAIN[3][26][20]
DRP[20] bit 9MAIN[3][27][20]
DRP[20] bit 10MAIN[3][26][21]
DRP[20] bit 11MAIN[3][27][21]
DRP[20] bit 12MAIN[3][26][22]
DRP[20] bit 13MAIN[3][27][22]
DRP[20] bit 14MAIN[3][26][23]
DRP[20] bit 15MAIN[3][27][23]
DRP[21] bit 0MAIN[3][26][24]
DRP[21] bit 1MAIN[3][27][24]
DRP[21] bit 2MAIN[3][26][25]
DRP[21] bit 3MAIN[3][27][25]
DRP[21] bit 4MAIN[3][26][26]
DRP[21] bit 5MAIN[3][27][26]
DRP[21] bit 6MAIN[3][26][27]
DRP[21] bit 7MAIN[3][27][27]
DRP[21] bit 8MAIN[3][26][28]
DRP[21] bit 9MAIN[3][27][28]
DRP[21] bit 10MAIN[3][26][29]
DRP[21] bit 11MAIN[3][27][29]
DRP[21] bit 12MAIN[3][26][30]
DRP[21] bit 13MAIN[3][27][30]
DRP[21] bit 14MAIN[3][26][31]
DRP[21] bit 15MAIN[3][27][31]
DRP[22] bit 0MAIN[3][26][32]
DRP[22] bit 1MAIN[3][27][32]
DRP[22] bit 2MAIN[3][26][33]
DRP[22] bit 3MAIN[3][27][33]
DRP[22] bit 4MAIN[3][26][34]
DRP[22] bit 5MAIN[3][27][34]
DRP[22] bit 6MAIN[3][26][35]
DRP[22] bit 7MAIN[3][27][35]
DRP[22] bit 8MAIN[3][26][36]
DRP[22] bit 9MAIN[3][27][36]
DRP[22] bit 10MAIN[3][26][37]
DRP[22] bit 11MAIN[3][27][37]
DRP[22] bit 12MAIN[3][26][38]
DRP[22] bit 13MAIN[3][27][38]
DRP[22] bit 14MAIN[3][26][39]
DRP[22] bit 15MAIN[3][27][39]
DRP[23] bit 0MAIN[3][26][40]
DRP[23] bit 1MAIN[3][27][40]
DRP[23] bit 2MAIN[3][26][41]
DRP[23] bit 3MAIN[3][27][41]
DRP[23] bit 4MAIN[3][26][42]
DRP[23] bit 5MAIN[3][27][42]
DRP[23] bit 6MAIN[3][26][43]
DRP[23] bit 7MAIN[3][27][43]
DRP[23] bit 8MAIN[3][26][44]
DRP[23] bit 9MAIN[3][27][44]
DRP[23] bit 10MAIN[3][26][45]
DRP[23] bit 11MAIN[3][27][45]
DRP[23] bit 12MAIN[3][26][46]
DRP[23] bit 13MAIN[3][27][46]
DRP[23] bit 14MAIN[3][26][47]
DRP[23] bit 15MAIN[3][27][47]
DRP[24] bit 0MAIN[4][26][0]
DRP[24] bit 1MAIN[4][27][0]
DRP[24] bit 2MAIN[4][26][1]
DRP[24] bit 3MAIN[4][27][1]
DRP[24] bit 4MAIN[4][26][2]
DRP[24] bit 5MAIN[4][27][2]
DRP[24] bit 6MAIN[4][26][3]
DRP[24] bit 7MAIN[4][27][3]
DRP[24] bit 8MAIN[4][26][4]
DRP[24] bit 9MAIN[4][27][4]
DRP[24] bit 10MAIN[4][26][5]
DRP[24] bit 11MAIN[4][27][5]
DRP[24] bit 12MAIN[4][26][6]
DRP[24] bit 13MAIN[4][27][6]
DRP[24] bit 14MAIN[4][26][7]
DRP[24] bit 15MAIN[4][27][7]
DRP[25] bit 0MAIN[4][26][8]
DRP[25] bit 1MAIN[4][27][8]
DRP[25] bit 2MAIN[4][26][9]
DRP[25] bit 3MAIN[4][27][9]
DRP[25] bit 4MAIN[4][26][10]
DRP[25] bit 5MAIN[4][27][10]
DRP[25] bit 6MAIN[4][26][11]
DRP[25] bit 7MAIN[4][27][11]
DRP[25] bit 8MAIN[4][26][12]
DRP[25] bit 9MAIN[4][27][12]
DRP[25] bit 10MAIN[4][26][13]
DRP[25] bit 11MAIN[4][27][13]
DRP[25] bit 12MAIN[4][26][14]
DRP[25] bit 13MAIN[4][27][14]
DRP[25] bit 14MAIN[4][26][15]
DRP[25] bit 15MAIN[4][27][15]
DRP[26] bit 0MAIN[4][26][16]
DRP[26] bit 1MAIN[4][27][16]
DRP[26] bit 2MAIN[4][26][17]
DRP[26] bit 3MAIN[4][27][17]
DRP[26] bit 4MAIN[4][26][18]
DRP[26] bit 5MAIN[4][27][18]
DRP[26] bit 6MAIN[4][26][19]
DRP[26] bit 7MAIN[4][27][19]
DRP[26] bit 8MAIN[4][26][20]
DRP[26] bit 9MAIN[4][27][20]
DRP[26] bit 10MAIN[4][26][21]
DRP[26] bit 11MAIN[4][27][21]
DRP[26] bit 12MAIN[4][26][22]
DRP[26] bit 13MAIN[4][27][22]
DRP[26] bit 14MAIN[4][26][23]
DRP[26] bit 15MAIN[4][27][23]
DRP[27] bit 0MAIN[4][26][24]
DRP[27] bit 1MAIN[4][27][24]
DRP[27] bit 2MAIN[4][26][25]
DRP[27] bit 3MAIN[4][27][25]
DRP[27] bit 4MAIN[4][26][26]
DRP[27] bit 5MAIN[4][27][26]
DRP[27] bit 6MAIN[4][26][27]
DRP[27] bit 7MAIN[4][27][27]
DRP[27] bit 8MAIN[4][26][28]
DRP[27] bit 9MAIN[4][27][28]
DRP[27] bit 10MAIN[4][26][29]
DRP[27] bit 11MAIN[4][27][29]
DRP[27] bit 12MAIN[4][26][30]
DRP[27] bit 13MAIN[4][27][30]
DRP[27] bit 14MAIN[4][26][31]
DRP[27] bit 15MAIN[4][27][31]
DRP[28] bit 0MAIN[4][26][32]
DRP[28] bit 1MAIN[4][27][32]
DRP[28] bit 2MAIN[4][26][33]
DRP[28] bit 3MAIN[4][27][33]
DRP[28] bit 4MAIN[4][26][34]
DRP[28] bit 5MAIN[4][27][34]
DRP[28] bit 6MAIN[4][26][35]
DRP[28] bit 7MAIN[4][27][35]
DRP[28] bit 8MAIN[4][26][36]
DRP[28] bit 9MAIN[4][27][36]
DRP[28] bit 10MAIN[4][26][37]
DRP[28] bit 11MAIN[4][27][37]
DRP[28] bit 12MAIN[4][26][38]
DRP[28] bit 13MAIN[4][27][38]
DRP[28] bit 14MAIN[4][26][39]
DRP[28] bit 15MAIN[4][27][39]
DRP[29] bit 0MAIN[4][26][40]
DRP[29] bit 1MAIN[4][27][40]
DRP[29] bit 2MAIN[4][26][41]
DRP[29] bit 3MAIN[4][27][41]
DRP[29] bit 4MAIN[4][26][42]
DRP[29] bit 5MAIN[4][27][42]
DRP[29] bit 6MAIN[4][26][43]
DRP[29] bit 7MAIN[4][27][43]
DRP[29] bit 8MAIN[4][26][44]
DRP[29] bit 9MAIN[4][27][44]
DRP[29] bit 10MAIN[4][26][45]
DRP[29] bit 11MAIN[4][27][45]
DRP[29] bit 12MAIN[4][26][46]
DRP[29] bit 13MAIN[4][27][46]
DRP[29] bit 14MAIN[4][26][47]
DRP[29] bit 15MAIN[4][27][47]
DRP[30] bit 0MAIN[5][26][0]
DRP[30] bit 1MAIN[5][27][0]
DRP[30] bit 2MAIN[5][26][1]
DRP[30] bit 3MAIN[5][27][1]
DRP[30] bit 4MAIN[5][26][2]
DRP[30] bit 5MAIN[5][27][2]
DRP[30] bit 6MAIN[5][26][3]
DRP[30] bit 7MAIN[5][27][3]
DRP[30] bit 8MAIN[5][26][4]
DRP[30] bit 9MAIN[5][27][4]
DRP[30] bit 10MAIN[5][26][5]
DRP[30] bit 11MAIN[5][27][5]
DRP[30] bit 12MAIN[5][26][6]
DRP[30] bit 13MAIN[5][27][6]
DRP[30] bit 14MAIN[5][26][7]
DRP[30] bit 15MAIN[5][27][7]
DRP[31] bit 0MAIN[5][26][8]
DRP[31] bit 1MAIN[5][27][8]
DRP[31] bit 2MAIN[5][26][9]
DRP[31] bit 3MAIN[5][27][9]
DRP[31] bit 4MAIN[5][26][10]
DRP[31] bit 5MAIN[5][27][10]
DRP[31] bit 6MAIN[5][26][11]
DRP[31] bit 7MAIN[5][27][11]
DRP[31] bit 8MAIN[5][26][12]
DRP[31] bit 9MAIN[5][27][12]
DRP[31] bit 10MAIN[5][26][13]
DRP[31] bit 11MAIN[5][27][13]
DRP[31] bit 12MAIN[5][26][14]
DRP[31] bit 13MAIN[5][27][14]
DRP[31] bit 14MAIN[5][26][15]
DRP[31] bit 15MAIN[5][27][15]
DRP[32] bit 0MAIN[5][26][16]
DRP[32] bit 1MAIN[5][27][16]
DRP[32] bit 2MAIN[5][26][17]
DRP[32] bit 3MAIN[5][27][17]
DRP[32] bit 4MAIN[5][26][18]
DRP[32] bit 5MAIN[5][27][18]
DRP[32] bit 6MAIN[5][26][19]
DRP[32] bit 7MAIN[5][27][19]
DRP[32] bit 8MAIN[5][26][20]
DRP[32] bit 9MAIN[5][27][20]
DRP[32] bit 10MAIN[5][26][21]
DRP[32] bit 11MAIN[5][27][21]
DRP[32] bit 12MAIN[5][26][22]
DRP[32] bit 13MAIN[5][27][22]
DRP[32] bit 14MAIN[5][26][23]
DRP[32] bit 15MAIN[5][27][23]
DRP[33] bit 0MAIN[5][26][24]
DRP[33] bit 1MAIN[5][27][24]
DRP[33] bit 2MAIN[5][26][25]
DRP[33] bit 3MAIN[5][27][25]
DRP[33] bit 4MAIN[5][26][26]
DRP[33] bit 5MAIN[5][27][26]
DRP[33] bit 6MAIN[5][26][27]
DRP[33] bit 7MAIN[5][27][27]
DRP[33] bit 8MAIN[5][26][28]
DRP[33] bit 9MAIN[5][27][28]
DRP[33] bit 10MAIN[5][26][29]
DRP[33] bit 11MAIN[5][27][29]
DRP[33] bit 12MAIN[5][26][30]
DRP[33] bit 13MAIN[5][27][30]
DRP[33] bit 14MAIN[5][26][31]
DRP[33] bit 15MAIN[5][27][31]
DRP[34] bit 0MAIN[5][26][32]
DRP[34] bit 1MAIN[5][27][32]
DRP[34] bit 2MAIN[5][26][33]
DRP[34] bit 3MAIN[5][27][33]
DRP[34] bit 4MAIN[5][26][34]
DRP[34] bit 5MAIN[5][27][34]
DRP[34] bit 6MAIN[5][26][35]
DRP[34] bit 7MAIN[5][27][35]
DRP[34] bit 8MAIN[5][26][36]
DRP[34] bit 9MAIN[5][27][36]
DRP[34] bit 10MAIN[5][26][37]
DRP[34] bit 11MAIN[5][27][37]
DRP[34] bit 12MAIN[5][26][38]
DRP[34] bit 13MAIN[5][27][38]
DRP[34] bit 14MAIN[5][26][39]
DRP[34] bit 15MAIN[5][27][39]
DRP[35] bit 0MAIN[5][26][40]
DRP[35] bit 1MAIN[5][27][40]
DRP[35] bit 2MAIN[5][26][41]
DRP[35] bit 3MAIN[5][27][41]
DRP[35] bit 4MAIN[5][26][42]
DRP[35] bit 5MAIN[5][27][42]
DRP[35] bit 6MAIN[5][26][43]
DRP[35] bit 7MAIN[5][27][43]
DRP[35] bit 8MAIN[5][26][44]
DRP[35] bit 9MAIN[5][27][44]
DRP[35] bit 10MAIN[5][26][45]
DRP[35] bit 11MAIN[5][27][45]
DRP[35] bit 12MAIN[5][26][46]
DRP[35] bit 13MAIN[5][27][46]
DRP[35] bit 14MAIN[5][26][47]
DRP[35] bit 15MAIN[5][27][47]
DRP[36] bit 0MAIN[6][26][0]
DRP[36] bit 1MAIN[6][27][0]
DRP[36] bit 2MAIN[6][26][1]
DRP[36] bit 3MAIN[6][27][1]
DRP[36] bit 4MAIN[6][26][2]
DRP[36] bit 5MAIN[6][27][2]
DRP[36] bit 6MAIN[6][26][3]
DRP[36] bit 7MAIN[6][27][3]
DRP[36] bit 8MAIN[6][26][4]
DRP[36] bit 9MAIN[6][27][4]
DRP[36] bit 10MAIN[6][26][5]
DRP[36] bit 11MAIN[6][27][5]
DRP[36] bit 12MAIN[6][26][6]
DRP[36] bit 13MAIN[6][27][6]
DRP[36] bit 14MAIN[6][26][7]
DRP[36] bit 15MAIN[6][27][7]
DRP[37] bit 0MAIN[6][26][8]
DRP[37] bit 1MAIN[6][27][8]
DRP[37] bit 2MAIN[6][26][9]
DRP[37] bit 3MAIN[6][27][9]
DRP[37] bit 4MAIN[6][26][10]
DRP[37] bit 5MAIN[6][27][10]
DRP[37] bit 6MAIN[6][26][11]
DRP[37] bit 7MAIN[6][27][11]
DRP[37] bit 8MAIN[6][26][12]
DRP[37] bit 9MAIN[6][27][12]
DRP[37] bit 10MAIN[6][26][13]
DRP[37] bit 11MAIN[6][27][13]
DRP[37] bit 12MAIN[6][26][14]
DRP[37] bit 13MAIN[6][27][14]
DRP[37] bit 14MAIN[6][26][15]
DRP[37] bit 15MAIN[6][27][15]
DRP[38] bit 0MAIN[6][26][16]
DRP[38] bit 1MAIN[6][27][16]
DRP[38] bit 2MAIN[6][26][17]
DRP[38] bit 3MAIN[6][27][17]
DRP[38] bit 4MAIN[6][26][18]
DRP[38] bit 5MAIN[6][27][18]
DRP[38] bit 6MAIN[6][26][19]
DRP[38] bit 7MAIN[6][27][19]
DRP[38] bit 8MAIN[6][26][20]
DRP[38] bit 9MAIN[6][27][20]
DRP[38] bit 10MAIN[6][26][21]
DRP[38] bit 11MAIN[6][27][21]
DRP[38] bit 12MAIN[6][26][22]
DRP[38] bit 13MAIN[6][27][22]
DRP[38] bit 14MAIN[6][26][23]
DRP[38] bit 15MAIN[6][27][23]
DRP[39] bit 0MAIN[6][26][24]
DRP[39] bit 1MAIN[6][27][24]
DRP[39] bit 2MAIN[6][26][25]
DRP[39] bit 3MAIN[6][27][25]
DRP[39] bit 4MAIN[6][26][26]
DRP[39] bit 5MAIN[6][27][26]
DRP[39] bit 6MAIN[6][26][27]
DRP[39] bit 7MAIN[6][27][27]
DRP[39] bit 8MAIN[6][26][28]
DRP[39] bit 9MAIN[6][27][28]
DRP[39] bit 10MAIN[6][26][29]
DRP[39] bit 11MAIN[6][27][29]
DRP[39] bit 12MAIN[6][26][30]
DRP[39] bit 13MAIN[6][27][30]
DRP[39] bit 14MAIN[6][26][31]
DRP[39] bit 15MAIN[6][27][31]
DRP[40] bit 0MAIN[6][26][32]
DRP[40] bit 1MAIN[6][27][32]
DRP[40] bit 2MAIN[6][26][33]
DRP[40] bit 3MAIN[6][27][33]
DRP[40] bit 4MAIN[6][26][34]
DRP[40] bit 5MAIN[6][27][34]
DRP[40] bit 6MAIN[6][26][35]
DRP[40] bit 7MAIN[6][27][35]
DRP[40] bit 8MAIN[6][26][36]
DRP[40] bit 9MAIN[6][27][36]
DRP[40] bit 10MAIN[6][26][37]
DRP[40] bit 11MAIN[6][27][37]
DRP[40] bit 12MAIN[6][26][38]
DRP[40] bit 13MAIN[6][27][38]
DRP[40] bit 14MAIN[6][26][39]
DRP[40] bit 15MAIN[6][27][39]
DRP[41] bit 0MAIN[6][26][40]
DRP[41] bit 1MAIN[6][27][40]
DRP[41] bit 2MAIN[6][26][41]
DRP[41] bit 3MAIN[6][27][41]
DRP[41] bit 4MAIN[6][26][42]
DRP[41] bit 5MAIN[6][27][42]
DRP[41] bit 6MAIN[6][26][43]
DRP[41] bit 7MAIN[6][27][43]
DRP[41] bit 8MAIN[6][26][44]
DRP[41] bit 9MAIN[6][27][44]
DRP[41] bit 10MAIN[6][26][45]
DRP[41] bit 11MAIN[6][27][45]
DRP[41] bit 12MAIN[6][26][46]
DRP[41] bit 13MAIN[6][27][46]
DRP[41] bit 14MAIN[6][26][47]
DRP[41] bit 15MAIN[6][27][47]
DRP[42] bit 0MAIN[7][26][0]
DRP[42] bit 1MAIN[7][27][0]
DRP[42] bit 2MAIN[7][26][1]
DRP[42] bit 3MAIN[7][27][1]
DRP[42] bit 4MAIN[7][26][2]
DRP[42] bit 5MAIN[7][27][2]
DRP[42] bit 6MAIN[7][26][3]
DRP[42] bit 7MAIN[7][27][3]
DRP[42] bit 8MAIN[7][26][4]
DRP[42] bit 9MAIN[7][27][4]
DRP[42] bit 10MAIN[7][26][5]
DRP[42] bit 11MAIN[7][27][5]
DRP[42] bit 12MAIN[7][26][6]
DRP[42] bit 13MAIN[7][27][6]
DRP[42] bit 14MAIN[7][26][7]
DRP[42] bit 15MAIN[7][27][7]
DRP[43] bit 0MAIN[7][26][8]
DRP[43] bit 1MAIN[7][27][8]
DRP[43] bit 2MAIN[7][26][9]
DRP[43] bit 3MAIN[7][27][9]
DRP[43] bit 4MAIN[7][26][10]
DRP[43] bit 5MAIN[7][27][10]
DRP[43] bit 6MAIN[7][26][11]
DRP[43] bit 7MAIN[7][27][11]
DRP[43] bit 8MAIN[7][26][12]
DRP[43] bit 9MAIN[7][27][12]
DRP[43] bit 10MAIN[7][26][13]
DRP[43] bit 11MAIN[7][27][13]
DRP[43] bit 12MAIN[7][26][14]
DRP[43] bit 13MAIN[7][27][14]
DRP[43] bit 14MAIN[7][26][15]
DRP[43] bit 15MAIN[7][27][15]
DRP[44] bit 0MAIN[7][26][16]
DRP[44] bit 1MAIN[7][27][16]
DRP[44] bit 2MAIN[7][26][17]
DRP[44] bit 3MAIN[7][27][17]
DRP[44] bit 4MAIN[7][26][18]
DRP[44] bit 5MAIN[7][27][18]
DRP[44] bit 6MAIN[7][26][19]
DRP[44] bit 7MAIN[7][27][19]
DRP[44] bit 8MAIN[7][26][20]
DRP[44] bit 9MAIN[7][27][20]
DRP[44] bit 10MAIN[7][26][21]
DRP[44] bit 11MAIN[7][27][21]
DRP[44] bit 12MAIN[7][26][22]
DRP[44] bit 13MAIN[7][27][22]
DRP[44] bit 14MAIN[7][26][23]
DRP[44] bit 15MAIN[7][27][23]
DRP[45] bit 0MAIN[7][26][24]
DRP[45] bit 1MAIN[7][27][24]
DRP[45] bit 2MAIN[7][26][25]
DRP[45] bit 3MAIN[7][27][25]
DRP[45] bit 4MAIN[7][26][26]
DRP[45] bit 5MAIN[7][27][26]
DRP[45] bit 6MAIN[7][26][27]
DRP[45] bit 7MAIN[7][27][27]
DRP[45] bit 8MAIN[7][26][28]
DRP[45] bit 9MAIN[7][27][28]
DRP[45] bit 10MAIN[7][26][29]
DRP[45] bit 11MAIN[7][27][29]
DRP[45] bit 12MAIN[7][26][30]
DRP[45] bit 13MAIN[7][27][30]
DRP[45] bit 14MAIN[7][26][31]
DRP[45] bit 15MAIN[7][27][31]
DRP[46] bit 0MAIN[7][26][32]
DRP[46] bit 1MAIN[7][27][32]
DRP[46] bit 2MAIN[7][26][33]
DRP[46] bit 3MAIN[7][27][33]
DRP[46] bit 4MAIN[7][26][34]
DRP[46] bit 5MAIN[7][27][34]
DRP[46] bit 6MAIN[7][26][35]
DRP[46] bit 7MAIN[7][27][35]
DRP[46] bit 8MAIN[7][26][36]
DRP[46] bit 9MAIN[7][27][36]
DRP[46] bit 10MAIN[7][26][37]
DRP[46] bit 11MAIN[7][27][37]
DRP[46] bit 12MAIN[7][26][38]
DRP[46] bit 13MAIN[7][27][38]
DRP[46] bit 14MAIN[7][26][39]
DRP[46] bit 15MAIN[7][27][39]
DRP[47] bit 0MAIN[7][26][40]
DRP[47] bit 1MAIN[7][27][40]
DRP[47] bit 2MAIN[7][26][41]
DRP[47] bit 3MAIN[7][27][41]
DRP[47] bit 4MAIN[7][26][42]
DRP[47] bit 5MAIN[7][27][42]
DRP[47] bit 6MAIN[7][26][43]
DRP[47] bit 7MAIN[7][27][43]
DRP[47] bit 8MAIN[7][26][44]
DRP[47] bit 9MAIN[7][27][44]
DRP[47] bit 10MAIN[7][26][45]
DRP[47] bit 11MAIN[7][27][45]
DRP[47] bit 12MAIN[7][26][46]
DRP[47] bit 13MAIN[7][27][46]
DRP[47] bit 14MAIN[7][26][47]
DRP[47] bit 15MAIN[7][27][47]
DRP[48] bit 0MAIN[8][26][0]
DRP[48] bit 1MAIN[8][27][0]
DRP[48] bit 2MAIN[8][26][1]
DRP[48] bit 3MAIN[8][27][1]
DRP[48] bit 4MAIN[8][26][2]
DRP[48] bit 5MAIN[8][27][2]
DRP[48] bit 6MAIN[8][26][3]
DRP[48] bit 7MAIN[8][27][3]
DRP[48] bit 8MAIN[8][26][4]
DRP[48] bit 9MAIN[8][27][4]
DRP[48] bit 10MAIN[8][26][5]
DRP[48] bit 11MAIN[8][27][5]
DRP[48] bit 12MAIN[8][26][6]
DRP[48] bit 13MAIN[8][27][6]
DRP[48] bit 14MAIN[8][26][7]
DRP[48] bit 15MAIN[8][27][7]
DRP[49] bit 0MAIN[8][26][8]
DRP[49] bit 1MAIN[8][27][8]
DRP[49] bit 2MAIN[8][26][9]
DRP[49] bit 3MAIN[8][27][9]
DRP[49] bit 4MAIN[8][26][10]
DRP[49] bit 5MAIN[8][27][10]
DRP[49] bit 6MAIN[8][26][11]
DRP[49] bit 7MAIN[8][27][11]
DRP[49] bit 8MAIN[8][26][12]
DRP[49] bit 9MAIN[8][27][12]
DRP[49] bit 10MAIN[8][26][13]
DRP[49] bit 11MAIN[8][27][13]
DRP[49] bit 12MAIN[8][26][14]
DRP[49] bit 13MAIN[8][27][14]
DRP[49] bit 14MAIN[8][26][15]
DRP[49] bit 15MAIN[8][27][15]
DRP[50] bit 0MAIN[8][26][16]
DRP[50] bit 1MAIN[8][27][16]
DRP[50] bit 2MAIN[8][26][17]
DRP[50] bit 3MAIN[8][27][17]
DRP[50] bit 4MAIN[8][26][18]
DRP[50] bit 5MAIN[8][27][18]
DRP[50] bit 6MAIN[8][26][19]
DRP[50] bit 7MAIN[8][27][19]
DRP[50] bit 8MAIN[8][26][20]
DRP[50] bit 9MAIN[8][27][20]
DRP[50] bit 10MAIN[8][26][21]
DRP[50] bit 11MAIN[8][27][21]
DRP[50] bit 12MAIN[8][26][22]
DRP[50] bit 13MAIN[8][27][22]
DRP[50] bit 14MAIN[8][26][23]
DRP[50] bit 15MAIN[8][27][23]
DRP[51] bit 0MAIN[8][26][24]
DRP[51] bit 1MAIN[8][27][24]
DRP[51] bit 2MAIN[8][26][25]
DRP[51] bit 3MAIN[8][27][25]
DRP[51] bit 4MAIN[8][26][26]
DRP[51] bit 5MAIN[8][27][26]
DRP[51] bit 6MAIN[8][26][27]
DRP[51] bit 7MAIN[8][27][27]
DRP[51] bit 8MAIN[8][26][28]
DRP[51] bit 9MAIN[8][27][28]
DRP[51] bit 10MAIN[8][26][29]
DRP[51] bit 11MAIN[8][27][29]
DRP[51] bit 12MAIN[8][26][30]
DRP[51] bit 13MAIN[8][27][30]
DRP[51] bit 14MAIN[8][26][31]
DRP[51] bit 15MAIN[8][27][31]
DRP[52] bit 0MAIN[8][26][32]
DRP[52] bit 1MAIN[8][27][32]
DRP[52] bit 2MAIN[8][26][33]
DRP[52] bit 3MAIN[8][27][33]
DRP[52] bit 4MAIN[8][26][34]
DRP[52] bit 5MAIN[8][27][34]
DRP[52] bit 6MAIN[8][26][35]
DRP[52] bit 7MAIN[8][27][35]
DRP[52] bit 8MAIN[8][26][36]
DRP[52] bit 9MAIN[8][27][36]
DRP[52] bit 10MAIN[8][26][37]
DRP[52] bit 11MAIN[8][27][37]
DRP[52] bit 12MAIN[8][26][38]
DRP[52] bit 13MAIN[8][27][38]
DRP[52] bit 14MAIN[8][26][39]
DRP[52] bit 15MAIN[8][27][39]
DRP[53] bit 0MAIN[8][26][40]
DRP[53] bit 1MAIN[8][27][40]
DRP[53] bit 2MAIN[8][26][41]
DRP[53] bit 3MAIN[8][27][41]
DRP[53] bit 4MAIN[8][26][42]
DRP[53] bit 5MAIN[8][27][42]
DRP[53] bit 6MAIN[8][26][43]
DRP[53] bit 7MAIN[8][27][43]
DRP[53] bit 8MAIN[8][26][44]
DRP[53] bit 9MAIN[8][27][44]
DRP[53] bit 10MAIN[8][26][45]
DRP[53] bit 11MAIN[8][27][45]
DRP[53] bit 12MAIN[8][26][46]
DRP[53] bit 13MAIN[8][27][46]
DRP[53] bit 14MAIN[8][26][47]
DRP[53] bit 15MAIN[8][27][47]
DRP[54] bit 0MAIN[9][26][0]
DRP[54] bit 1MAIN[9][27][0]
DRP[54] bit 2MAIN[9][26][1]
DRP[54] bit 3MAIN[9][27][1]
DRP[54] bit 4MAIN[9][26][2]
DRP[54] bit 5MAIN[9][27][2]
DRP[54] bit 6MAIN[9][26][3]
DRP[54] bit 7MAIN[9][27][3]
DRP[54] bit 8MAIN[9][26][4]
DRP[54] bit 9MAIN[9][27][4]
DRP[54] bit 10MAIN[9][26][5]
DRP[54] bit 11MAIN[9][27][5]
DRP[54] bit 12MAIN[9][26][6]
DRP[54] bit 13MAIN[9][27][6]
DRP[54] bit 14MAIN[9][26][7]
DRP[54] bit 15MAIN[9][27][7]
DRP[55] bit 0MAIN[9][26][8]
DRP[55] bit 1MAIN[9][27][8]
DRP[55] bit 2MAIN[9][26][9]
DRP[55] bit 3MAIN[9][27][9]
DRP[55] bit 4MAIN[9][26][10]
DRP[55] bit 5MAIN[9][27][10]
DRP[55] bit 6MAIN[9][26][11]
DRP[55] bit 7MAIN[9][27][11]
DRP[55] bit 8MAIN[9][26][12]
DRP[55] bit 9MAIN[9][27][12]
DRP[55] bit 10MAIN[9][26][13]
DRP[55] bit 11MAIN[9][27][13]
DRP[55] bit 12MAIN[9][26][14]
DRP[55] bit 13MAIN[9][27][14]
DRP[55] bit 14MAIN[9][26][15]
DRP[55] bit 15MAIN[9][27][15]
DRP[56] bit 0MAIN[9][26][16]
DRP[56] bit 1MAIN[9][27][16]
DRP[56] bit 2MAIN[9][26][17]
DRP[56] bit 3MAIN[9][27][17]
DRP[56] bit 4MAIN[9][26][18]
DRP[56] bit 5MAIN[9][27][18]
DRP[56] bit 6MAIN[9][26][19]
DRP[56] bit 7MAIN[9][27][19]
DRP[56] bit 8MAIN[9][26][20]
DRP[56] bit 9MAIN[9][27][20]
DRP[56] bit 10MAIN[9][26][21]
DRP[56] bit 11MAIN[9][27][21]
DRP[56] bit 12MAIN[9][26][22]
DRP[56] bit 13MAIN[9][27][22]
DRP[56] bit 14MAIN[9][26][23]
DRP[56] bit 15MAIN[9][27][23]
DRP[57] bit 0MAIN[9][26][24]
DRP[57] bit 1MAIN[9][27][24]
DRP[57] bit 2MAIN[9][26][25]
DRP[57] bit 3MAIN[9][27][25]
DRP[57] bit 4MAIN[9][26][26]
DRP[57] bit 5MAIN[9][27][26]
DRP[57] bit 6MAIN[9][26][27]
DRP[57] bit 7MAIN[9][27][27]
DRP[57] bit 8MAIN[9][26][28]
DRP[57] bit 9MAIN[9][27][28]
DRP[57] bit 10MAIN[9][26][29]
DRP[57] bit 11MAIN[9][27][29]
DRP[57] bit 12MAIN[9][26][30]
DRP[57] bit 13MAIN[9][27][30]
DRP[57] bit 14MAIN[9][26][31]
DRP[57] bit 15MAIN[9][27][31]
DRP[58] bit 0MAIN[9][26][32]
DRP[58] bit 1MAIN[9][27][32]
DRP[58] bit 2MAIN[9][26][33]
DRP[58] bit 3MAIN[9][27][33]
DRP[58] bit 4MAIN[9][26][34]
DRP[58] bit 5MAIN[9][27][34]
DRP[58] bit 6MAIN[9][26][35]
DRP[58] bit 7MAIN[9][27][35]
DRP[58] bit 8MAIN[9][26][36]
DRP[58] bit 9MAIN[9][27][36]
DRP[58] bit 10MAIN[9][26][37]
DRP[58] bit 11MAIN[9][27][37]
DRP[58] bit 12MAIN[9][26][38]
DRP[58] bit 13MAIN[9][27][38]
DRP[58] bit 14MAIN[9][26][39]
DRP[58] bit 15MAIN[9][27][39]
DRP[59] bit 0MAIN[9][26][40]
DRP[59] bit 1MAIN[9][27][40]
DRP[59] bit 2MAIN[9][26][41]
DRP[59] bit 3MAIN[9][27][41]
DRP[59] bit 4MAIN[9][26][42]
DRP[59] bit 5MAIN[9][27][42]
DRP[59] bit 6MAIN[9][26][43]
DRP[59] bit 7MAIN[9][27][43]
DRP[59] bit 8MAIN[9][26][44]
DRP[59] bit 9MAIN[9][27][44]
DRP[59] bit 10MAIN[9][26][45]
DRP[59] bit 11MAIN[9][27][45]
DRP[59] bit 12MAIN[9][26][46]
DRP[59] bit 13MAIN[9][27][46]
DRP[59] bit 14MAIN[9][26][47]
DRP[59] bit 15MAIN[9][27][47]
DRP[60] bit 0MAIN[10][26][0]
DRP[60] bit 1MAIN[10][27][0]
DRP[60] bit 2MAIN[10][26][1]
DRP[60] bit 3MAIN[10][27][1]
DRP[60] bit 4MAIN[10][26][2]
DRP[60] bit 5MAIN[10][27][2]
DRP[60] bit 6MAIN[10][26][3]
DRP[60] bit 7MAIN[10][27][3]
DRP[60] bit 8MAIN[10][26][4]
DRP[60] bit 9MAIN[10][27][4]
DRP[60] bit 10MAIN[10][26][5]
DRP[60] bit 11MAIN[10][27][5]
DRP[60] bit 12MAIN[10][26][6]
DRP[60] bit 13MAIN[10][27][6]
DRP[60] bit 14MAIN[10][26][7]
DRP[60] bit 15MAIN[10][27][7]
DRP[61] bit 0MAIN[10][26][8]
DRP[61] bit 1MAIN[10][27][8]
DRP[61] bit 2MAIN[10][26][9]
DRP[61] bit 3MAIN[10][27][9]
DRP[61] bit 4MAIN[10][26][10]
DRP[61] bit 5MAIN[10][27][10]
DRP[61] bit 6MAIN[10][26][11]
DRP[61] bit 7MAIN[10][27][11]
DRP[61] bit 8MAIN[10][26][12]
DRP[61] bit 9MAIN[10][27][12]
DRP[61] bit 10MAIN[10][26][13]
DRP[61] bit 11MAIN[10][27][13]
DRP[61] bit 12MAIN[10][26][14]
DRP[61] bit 13MAIN[10][27][14]
DRP[61] bit 14MAIN[10][26][15]
DRP[61] bit 15MAIN[10][27][15]
DRP[62] bit 0MAIN[10][26][16]
DRP[62] bit 1MAIN[10][27][16]
DRP[62] bit 2MAIN[10][26][17]
DRP[62] bit 3MAIN[10][27][17]
DRP[62] bit 4MAIN[10][26][18]
DRP[62] bit 5MAIN[10][27][18]
DRP[62] bit 6MAIN[10][26][19]
DRP[62] bit 7MAIN[10][27][19]
DRP[62] bit 8MAIN[10][26][20]
DRP[62] bit 9MAIN[10][27][20]
DRP[62] bit 10MAIN[10][26][21]
DRP[62] bit 11MAIN[10][27][21]
DRP[62] bit 12MAIN[10][26][22]
DRP[62] bit 13MAIN[10][27][22]
DRP[62] bit 14MAIN[10][26][23]
DRP[62] bit 15MAIN[10][27][23]
DRP[63] bit 0MAIN[10][26][24]
DRP[63] bit 1MAIN[10][27][24]
DRP[63] bit 2MAIN[10][26][25]
DRP[63] bit 3MAIN[10][27][25]
DRP[63] bit 4MAIN[10][26][26]
DRP[63] bit 5MAIN[10][27][26]
DRP[63] bit 6MAIN[10][26][27]
DRP[63] bit 7MAIN[10][27][27]
DRP[63] bit 8MAIN[10][26][28]
DRP[63] bit 9MAIN[10][27][28]
DRP[63] bit 10MAIN[10][26][29]
DRP[63] bit 11MAIN[10][27][29]
DRP[63] bit 12MAIN[10][26][30]
DRP[63] bit 13MAIN[10][27][30]
DRP[63] bit 14MAIN[10][26][31]
DRP[63] bit 15MAIN[10][27][31]
DRP[64] bit 0MAIN[10][26][32]
DRP[64] bit 1MAIN[10][27][32]
DRP[64] bit 2MAIN[10][26][33]
DRP[64] bit 3MAIN[10][27][33]
DRP[64] bit 4MAIN[10][26][34]
DRP[64] bit 5MAIN[10][27][34]
DRP[64] bit 6MAIN[10][26][35]
DRP[64] bit 7MAIN[10][27][35]
DRP[64] bit 8MAIN[10][26][36]
DRP[64] bit 9MAIN[10][27][36]
DRP[64] bit 10MAIN[10][26][37]
DRP[64] bit 11MAIN[10][27][37]
DRP[64] bit 12MAIN[10][26][38]
DRP[64] bit 13MAIN[10][27][38]
DRP[64] bit 14MAIN[10][26][39]
DRP[64] bit 15MAIN[10][27][39]
DRP[65] bit 0MAIN[10][26][40]
DRP[65] bit 1MAIN[10][27][40]
DRP[65] bit 2MAIN[10][26][41]
DRP[65] bit 3MAIN[10][27][41]
DRP[65] bit 4MAIN[10][26][42]
DRP[65] bit 5MAIN[10][27][42]
DRP[65] bit 6MAIN[10][26][43]
DRP[65] bit 7MAIN[10][27][43]
DRP[65] bit 8MAIN[10][26][44]
DRP[65] bit 9MAIN[10][27][44]
DRP[65] bit 10MAIN[10][26][45]
DRP[65] bit 11MAIN[10][27][45]
DRP[65] bit 12MAIN[10][26][46]
DRP[65] bit 13MAIN[10][27][46]
DRP[65] bit 14MAIN[10][26][47]
DRP[65] bit 15MAIN[10][27][47]
DRP[66] bit 0MAIN[11][26][0]
DRP[66] bit 1MAIN[11][27][0]
DRP[66] bit 2MAIN[11][26][1]
DRP[66] bit 3MAIN[11][27][1]
DRP[66] bit 4MAIN[11][26][2]
DRP[66] bit 5MAIN[11][27][2]
DRP[66] bit 6MAIN[11][26][3]
DRP[66] bit 7MAIN[11][27][3]
DRP[66] bit 8MAIN[11][26][4]
DRP[66] bit 9MAIN[11][27][4]
DRP[66] bit 10MAIN[11][26][5]
DRP[66] bit 11MAIN[11][27][5]
DRP[66] bit 12MAIN[11][26][6]
DRP[66] bit 13MAIN[11][27][6]
DRP[66] bit 14MAIN[11][26][7]
DRP[66] bit 15MAIN[11][27][7]
DRP[67] bit 0MAIN[11][26][8]
DRP[67] bit 1MAIN[11][27][8]
DRP[67] bit 2MAIN[11][26][9]
DRP[67] bit 3MAIN[11][27][9]
DRP[67] bit 4MAIN[11][26][10]
DRP[67] bit 5MAIN[11][27][10]
DRP[67] bit 6MAIN[11][26][11]
DRP[67] bit 7MAIN[11][27][11]
DRP[67] bit 8MAIN[11][26][12]
DRP[67] bit 9MAIN[11][27][12]
DRP[67] bit 10MAIN[11][26][13]
DRP[67] bit 11MAIN[11][27][13]
DRP[67] bit 12MAIN[11][26][14]
DRP[67] bit 13MAIN[11][27][14]
DRP[67] bit 14MAIN[11][26][15]
DRP[67] bit 15MAIN[11][27][15]
DRP[68] bit 0MAIN[11][26][16]
DRP[68] bit 1MAIN[11][27][16]
DRP[68] bit 2MAIN[11][26][17]
DRP[68] bit 3MAIN[11][27][17]
DRP[68] bit 4MAIN[11][26][18]
DRP[68] bit 5MAIN[11][27][18]
DRP[68] bit 6MAIN[11][26][19]
DRP[68] bit 7MAIN[11][27][19]
DRP[68] bit 8MAIN[11][26][20]
DRP[68] bit 9MAIN[11][27][20]
DRP[68] bit 10MAIN[11][26][21]
DRP[68] bit 11MAIN[11][27][21]
DRP[68] bit 12MAIN[11][26][22]
DRP[68] bit 13MAIN[11][27][22]
DRP[68] bit 14MAIN[11][26][23]
DRP[68] bit 15MAIN[11][27][23]
DRP[69] bit 0MAIN[11][26][24]
DRP[69] bit 1MAIN[11][27][24]
DRP[69] bit 2MAIN[11][26][25]
DRP[69] bit 3MAIN[11][27][25]
DRP[69] bit 4MAIN[11][26][26]
DRP[69] bit 5MAIN[11][27][26]
DRP[69] bit 6MAIN[11][26][27]
DRP[69] bit 7MAIN[11][27][27]
DRP[69] bit 8MAIN[11][26][28]
DRP[69] bit 9MAIN[11][27][28]
DRP[69] bit 10MAIN[11][26][29]
DRP[69] bit 11MAIN[11][27][29]
DRP[69] bit 12MAIN[11][26][30]
DRP[69] bit 13MAIN[11][27][30]
DRP[69] bit 14MAIN[11][26][31]
DRP[69] bit 15MAIN[11][27][31]
DRP[70] bit 0MAIN[11][26][32]
DRP[70] bit 1MAIN[11][27][32]
DRP[70] bit 2MAIN[11][26][33]
DRP[70] bit 3MAIN[11][27][33]
DRP[70] bit 4MAIN[11][26][34]
DRP[70] bit 5MAIN[11][27][34]
DRP[70] bit 6MAIN[11][26][35]
DRP[70] bit 7MAIN[11][27][35]
DRP[70] bit 8MAIN[11][26][36]
DRP[70] bit 9MAIN[11][27][36]
DRP[70] bit 10MAIN[11][26][37]
DRP[70] bit 11MAIN[11][27][37]
DRP[70] bit 12MAIN[11][26][38]
DRP[70] bit 13MAIN[11][27][38]
DRP[70] bit 14MAIN[11][26][39]
DRP[70] bit 15MAIN[11][27][39]
DRP[71] bit 0MAIN[11][26][40]
DRP[71] bit 1MAIN[11][27][40]
DRP[71] bit 2MAIN[11][26][41]
DRP[71] bit 3MAIN[11][27][41]
DRP[71] bit 4MAIN[11][26][42]
DRP[71] bit 5MAIN[11][27][42]
DRP[71] bit 6MAIN[11][26][43]
DRP[71] bit 7MAIN[11][27][43]
DRP[71] bit 8MAIN[11][26][44]
DRP[71] bit 9MAIN[11][27][44]
DRP[71] bit 10MAIN[11][26][45]
DRP[71] bit 11MAIN[11][27][45]
DRP[71] bit 12MAIN[11][26][46]
DRP[71] bit 13MAIN[11][27][46]
DRP[71] bit 14MAIN[11][26][47]
DRP[71] bit 15MAIN[11][27][47]
DRP[72] bit 0MAIN[12][26][0]
DRP[72] bit 1MAIN[12][27][0]
DRP[72] bit 2MAIN[12][26][1]
DRP[72] bit 3MAIN[12][27][1]
DRP[72] bit 4MAIN[12][26][2]
DRP[72] bit 5MAIN[12][27][2]
DRP[72] bit 6MAIN[12][26][3]
DRP[72] bit 7MAIN[12][27][3]
DRP[72] bit 8MAIN[12][26][4]
DRP[72] bit 9MAIN[12][27][4]
DRP[72] bit 10MAIN[12][26][5]
DRP[72] bit 11MAIN[12][27][5]
DRP[72] bit 12MAIN[12][26][6]
DRP[72] bit 13MAIN[12][27][6]
DRP[72] bit 14MAIN[12][26][7]
DRP[72] bit 15MAIN[12][27][7]
DRP[73] bit 0MAIN[12][26][8]
DRP[73] bit 1MAIN[12][27][8]
DRP[73] bit 2MAIN[12][26][9]
DRP[73] bit 3MAIN[12][27][9]
DRP[73] bit 4MAIN[12][26][10]
DRP[73] bit 5MAIN[12][27][10]
DRP[73] bit 6MAIN[12][26][11]
DRP[73] bit 7MAIN[12][27][11]
DRP[73] bit 8MAIN[12][26][12]
DRP[73] bit 9MAIN[12][27][12]
DRP[73] bit 10MAIN[12][26][13]
DRP[73] bit 11MAIN[12][27][13]
DRP[73] bit 12MAIN[12][26][14]
DRP[73] bit 13MAIN[12][27][14]
DRP[73] bit 14MAIN[12][26][15]
DRP[73] bit 15MAIN[12][27][15]
DRP[74] bit 0MAIN[12][26][16]
DRP[74] bit 1MAIN[12][27][16]
DRP[74] bit 2MAIN[12][26][17]
DRP[74] bit 3MAIN[12][27][17]
DRP[74] bit 4MAIN[12][26][18]
DRP[74] bit 5MAIN[12][27][18]
DRP[74] bit 6MAIN[12][26][19]
DRP[74] bit 7MAIN[12][27][19]
DRP[74] bit 8MAIN[12][26][20]
DRP[74] bit 9MAIN[12][27][20]
DRP[74] bit 10MAIN[12][26][21]
DRP[74] bit 11MAIN[12][27][21]
DRP[74] bit 12MAIN[12][26][22]
DRP[74] bit 13MAIN[12][27][22]
DRP[74] bit 14MAIN[12][26][23]
DRP[74] bit 15MAIN[12][27][23]
DRP[75] bit 0MAIN[12][26][24]
DRP[75] bit 1MAIN[12][27][24]
DRP[75] bit 2MAIN[12][26][25]
DRP[75] bit 3MAIN[12][27][25]
DRP[75] bit 4MAIN[12][26][26]
DRP[75] bit 5MAIN[12][27][26]
DRP[75] bit 6MAIN[12][26][27]
DRP[75] bit 7MAIN[12][27][27]
DRP[75] bit 8MAIN[12][26][28]
DRP[75] bit 9MAIN[12][27][28]
DRP[75] bit 10MAIN[12][26][29]
DRP[75] bit 11MAIN[12][27][29]
DRP[75] bit 12MAIN[12][26][30]
DRP[75] bit 13MAIN[12][27][30]
DRP[75] bit 14MAIN[12][26][31]
DRP[75] bit 15MAIN[12][27][31]
DRP[76] bit 0MAIN[12][26][32]
DRP[76] bit 1MAIN[12][27][32]
DRP[76] bit 2MAIN[12][26][33]
DRP[76] bit 3MAIN[12][27][33]
DRP[76] bit 4MAIN[12][26][34]
DRP[76] bit 5MAIN[12][27][34]
DRP[76] bit 6MAIN[12][26][35]
DRP[76] bit 7MAIN[12][27][35]
DRP[76] bit 8MAIN[12][26][36]
DRP[76] bit 9MAIN[12][27][36]
DRP[76] bit 10MAIN[12][26][37]
DRP[76] bit 11MAIN[12][27][37]
DRP[76] bit 12MAIN[12][26][38]
DRP[76] bit 13MAIN[12][27][38]
DRP[76] bit 14MAIN[12][26][39]
DRP[76] bit 15MAIN[12][27][39]
DRP[77] bit 0MAIN[12][26][40]
DRP[77] bit 1MAIN[12][27][40]
DRP[77] bit 2MAIN[12][26][41]
DRP[77] bit 3MAIN[12][27][41]
DRP[77] bit 4MAIN[12][26][42]
DRP[77] bit 5MAIN[12][27][42]
DRP[77] bit 6MAIN[12][26][43]
DRP[77] bit 7MAIN[12][27][43]
DRP[77] bit 8MAIN[12][26][44]
DRP[77] bit 9MAIN[12][27][44]
DRP[77] bit 10MAIN[12][26][45]
DRP[77] bit 11MAIN[12][27][45]
DRP[77] bit 12MAIN[12][26][46]
DRP[77] bit 13MAIN[12][27][46]
DRP[77] bit 14MAIN[12][26][47]
DRP[77] bit 15MAIN[12][27][47]
DRP[78] bit 0MAIN[13][26][0]
DRP[78] bit 1MAIN[13][27][0]
DRP[78] bit 2MAIN[13][26][1]
DRP[78] bit 3MAIN[13][27][1]
DRP[78] bit 4MAIN[13][26][2]
DRP[78] bit 5MAIN[13][27][2]
DRP[78] bit 6MAIN[13][26][3]
DRP[78] bit 7MAIN[13][27][3]
DRP[78] bit 8MAIN[13][26][4]
DRP[78] bit 9MAIN[13][27][4]
DRP[78] bit 10MAIN[13][26][5]
DRP[78] bit 11MAIN[13][27][5]
DRP[78] bit 12MAIN[13][26][6]
DRP[78] bit 13MAIN[13][27][6]
DRP[78] bit 14MAIN[13][26][7]
DRP[78] bit 15MAIN[13][27][7]
DRP[79] bit 0MAIN[13][26][8]
DRP[79] bit 1MAIN[13][27][8]
DRP[79] bit 2MAIN[13][26][9]
DRP[79] bit 3MAIN[13][27][9]
DRP[79] bit 4MAIN[13][26][10]
DRP[79] bit 5MAIN[13][27][10]
DRP[79] bit 6MAIN[13][26][11]
DRP[79] bit 7MAIN[13][27][11]
DRP[79] bit 8MAIN[13][26][12]
DRP[79] bit 9MAIN[13][27][12]
DRP[79] bit 10MAIN[13][26][13]
DRP[79] bit 11MAIN[13][27][13]
DRP[79] bit 12MAIN[13][26][14]
DRP[79] bit 13MAIN[13][27][14]
DRP[79] bit 14MAIN[13][26][15]
DRP[79] bit 15MAIN[13][27][15]
DRP[80] bit 0MAIN[13][26][16]
DRP[80] bit 1MAIN[13][27][16]
DRP[80] bit 2MAIN[13][26][17]
DRP[80] bit 3MAIN[13][27][17]
DRP[80] bit 4MAIN[13][26][18]
DRP[80] bit 5MAIN[13][27][18]
DRP[80] bit 6MAIN[13][26][19]
DRP[80] bit 7MAIN[13][27][19]
DRP[80] bit 8MAIN[13][26][20]
DRP[80] bit 9MAIN[13][27][20]
DRP[80] bit 10MAIN[13][26][21]
DRP[80] bit 11MAIN[13][27][21]
DRP[80] bit 12MAIN[13][26][22]
DRP[80] bit 13MAIN[13][27][22]
DRP[80] bit 14MAIN[13][26][23]
DRP[80] bit 15MAIN[13][27][23]
DRP[81] bit 0MAIN[13][26][24]
DRP[81] bit 1MAIN[13][27][24]
DRP[81] bit 2MAIN[13][26][25]
DRP[81] bit 3MAIN[13][27][25]
DRP[81] bit 4MAIN[13][26][26]
DRP[81] bit 5MAIN[13][27][26]
DRP[81] bit 6MAIN[13][26][27]
DRP[81] bit 7MAIN[13][27][27]
DRP[81] bit 8MAIN[13][26][28]
DRP[81] bit 9MAIN[13][27][28]
DRP[81] bit 10MAIN[13][26][29]
DRP[81] bit 11MAIN[13][27][29]
DRP[81] bit 12MAIN[13][26][30]
DRP[81] bit 13MAIN[13][27][30]
DRP[81] bit 14MAIN[13][26][31]
DRP[81] bit 15MAIN[13][27][31]
DRP[82] bit 0MAIN[13][26][32]
DRP[82] bit 1MAIN[13][27][32]
DRP[82] bit 2MAIN[13][26][33]
DRP[82] bit 3MAIN[13][27][33]
DRP[82] bit 4MAIN[13][26][34]
DRP[82] bit 5MAIN[13][27][34]
DRP[82] bit 6MAIN[13][26][35]
DRP[82] bit 7MAIN[13][27][35]
DRP[82] bit 8MAIN[13][26][36]
DRP[82] bit 9MAIN[13][27][36]
DRP[82] bit 10MAIN[13][26][37]
DRP[82] bit 11MAIN[13][27][37]
DRP[82] bit 12MAIN[13][26][38]
DRP[82] bit 13MAIN[13][27][38]
DRP[82] bit 14MAIN[13][26][39]
DRP[82] bit 15MAIN[13][27][39]
DRP[83] bit 0MAIN[13][26][40]
DRP[83] bit 1MAIN[13][27][40]
DRP[83] bit 2MAIN[13][26][41]
DRP[83] bit 3MAIN[13][27][41]
DRP[83] bit 4MAIN[13][26][42]
DRP[83] bit 5MAIN[13][27][42]
DRP[83] bit 6MAIN[13][26][43]
DRP[83] bit 7MAIN[13][27][43]
DRP[83] bit 8MAIN[13][26][44]
DRP[83] bit 9MAIN[13][27][44]
DRP[83] bit 10MAIN[13][26][45]
DRP[83] bit 11MAIN[13][27][45]
DRP[83] bit 12MAIN[13][26][46]
DRP[83] bit 13MAIN[13][27][46]
DRP[83] bit 14MAIN[13][26][47]
DRP[83] bit 15MAIN[13][27][47]
DRP[84] bit 0MAIN[14][26][0]
DRP[84] bit 1MAIN[14][27][0]
DRP[84] bit 2MAIN[14][26][1]
DRP[84] bit 3MAIN[14][27][1]
DRP[84] bit 4MAIN[14][26][2]
DRP[84] bit 5MAIN[14][27][2]
DRP[84] bit 6MAIN[14][26][3]
DRP[84] bit 7MAIN[14][27][3]
DRP[84] bit 8MAIN[14][26][4]
DRP[84] bit 9MAIN[14][27][4]
DRP[84] bit 10MAIN[14][26][5]
DRP[84] bit 11MAIN[14][27][5]
DRP[84] bit 12MAIN[14][26][6]
DRP[84] bit 13MAIN[14][27][6]
DRP[84] bit 14MAIN[14][26][7]
DRP[84] bit 15MAIN[14][27][7]
DRP[85] bit 0MAIN[14][26][8]
DRP[85] bit 1MAIN[14][27][8]
DRP[85] bit 2MAIN[14][26][9]
DRP[85] bit 3MAIN[14][27][9]
DRP[85] bit 4MAIN[14][26][10]
DRP[85] bit 5MAIN[14][27][10]
DRP[85] bit 6MAIN[14][26][11]
DRP[85] bit 7MAIN[14][27][11]
DRP[85] bit 8MAIN[14][26][12]
DRP[85] bit 9MAIN[14][27][12]
DRP[85] bit 10MAIN[14][26][13]
DRP[85] bit 11MAIN[14][27][13]
DRP[85] bit 12MAIN[14][26][14]
DRP[85] bit 13MAIN[14][27][14]
DRP[85] bit 14MAIN[14][26][15]
DRP[85] bit 15MAIN[14][27][15]
DRP[86] bit 0MAIN[14][26][16]
DRP[86] bit 1MAIN[14][27][16]
DRP[86] bit 2MAIN[14][26][17]
DRP[86] bit 3MAIN[14][27][17]
DRP[86] bit 4MAIN[14][26][18]
DRP[86] bit 5MAIN[14][27][18]
DRP[86] bit 6MAIN[14][26][19]
DRP[86] bit 7MAIN[14][27][19]
DRP[86] bit 8MAIN[14][26][20]
DRP[86] bit 9MAIN[14][27][20]
DRP[86] bit 10MAIN[14][26][21]
DRP[86] bit 11MAIN[14][27][21]
DRP[86] bit 12MAIN[14][26][22]
DRP[86] bit 13MAIN[14][27][22]
DRP[86] bit 14MAIN[14][26][23]
DRP[86] bit 15MAIN[14][27][23]
DRP[87] bit 0MAIN[14][26][24]
DRP[87] bit 1MAIN[14][27][24]
DRP[87] bit 2MAIN[14][26][25]
DRP[87] bit 3MAIN[14][27][25]
DRP[87] bit 4MAIN[14][26][26]
DRP[87] bit 5MAIN[14][27][26]
DRP[87] bit 6MAIN[14][26][27]
DRP[87] bit 7MAIN[14][27][27]
DRP[87] bit 8MAIN[14][26][28]
DRP[87] bit 9MAIN[14][27][28]
DRP[87] bit 10MAIN[14][26][29]
DRP[87] bit 11MAIN[14][27][29]
DRP[87] bit 12MAIN[14][26][30]
DRP[87] bit 13MAIN[14][27][30]
DRP[87] bit 14MAIN[14][26][31]
DRP[87] bit 15MAIN[14][27][31]
DRP[88] bit 0MAIN[14][26][32]
DRP[88] bit 1MAIN[14][27][32]
DRP[88] bit 2MAIN[14][26][33]
DRP[88] bit 3MAIN[14][27][33]
DRP[88] bit 4MAIN[14][26][34]
DRP[88] bit 5MAIN[14][27][34]
DRP[88] bit 6MAIN[14][26][35]
DRP[88] bit 7MAIN[14][27][35]
DRP[88] bit 8MAIN[14][26][36]
DRP[88] bit 9MAIN[14][27][36]
DRP[88] bit 10MAIN[14][26][37]
DRP[88] bit 11MAIN[14][27][37]
DRP[88] bit 12MAIN[14][26][38]
DRP[88] bit 13MAIN[14][27][38]
DRP[88] bit 14MAIN[14][26][39]
DRP[88] bit 15MAIN[14][27][39]
DRP[89] bit 0MAIN[14][26][40]
DRP[89] bit 1MAIN[14][27][40]
DRP[89] bit 2MAIN[14][26][41]
DRP[89] bit 3MAIN[14][27][41]
DRP[89] bit 4MAIN[14][26][42]
DRP[89] bit 5MAIN[14][27][42]
DRP[89] bit 6MAIN[14][26][43]
DRP[89] bit 7MAIN[14][27][43]
DRP[89] bit 8MAIN[14][26][44]
DRP[89] bit 9MAIN[14][27][44]
DRP[89] bit 10MAIN[14][26][45]
DRP[89] bit 11MAIN[14][27][45]
DRP[89] bit 12MAIN[14][26][46]
DRP[89] bit 13MAIN[14][27][46]
DRP[89] bit 14MAIN[14][26][47]
DRP[89] bit 15MAIN[14][27][47]
DRP[90] bit 0MAIN[15][26][0]
DRP[90] bit 1MAIN[15][27][0]
DRP[90] bit 2MAIN[15][26][1]
DRP[90] bit 3MAIN[15][27][1]
DRP[90] bit 4MAIN[15][26][2]
DRP[90] bit 5MAIN[15][27][2]
DRP[90] bit 6MAIN[15][26][3]
DRP[90] bit 7MAIN[15][27][3]
DRP[90] bit 8MAIN[15][26][4]
DRP[90] bit 9MAIN[15][27][4]
DRP[90] bit 10MAIN[15][26][5]
DRP[90] bit 11MAIN[15][27][5]
DRP[90] bit 12MAIN[15][26][6]
DRP[90] bit 13MAIN[15][27][6]
DRP[90] bit 14MAIN[15][26][7]
DRP[90] bit 15MAIN[15][27][7]
DRP[91] bit 0MAIN[15][26][8]
DRP[91] bit 1MAIN[15][27][8]
DRP[91] bit 2MAIN[15][26][9]
DRP[91] bit 3MAIN[15][27][9]
DRP[91] bit 4MAIN[15][26][10]
DRP[91] bit 5MAIN[15][27][10]
DRP[91] bit 6MAIN[15][26][11]
DRP[91] bit 7MAIN[15][27][11]
DRP[91] bit 8MAIN[15][26][12]
DRP[91] bit 9MAIN[15][27][12]
DRP[91] bit 10MAIN[15][26][13]
DRP[91] bit 11MAIN[15][27][13]
DRP[91] bit 12MAIN[15][26][14]
DRP[91] bit 13MAIN[15][27][14]
DRP[91] bit 14MAIN[15][26][15]
DRP[91] bit 15MAIN[15][27][15]
DRP[92] bit 0MAIN[15][26][16]
DRP[92] bit 1MAIN[15][27][16]
DRP[92] bit 2MAIN[15][26][17]
DRP[92] bit 3MAIN[15][27][17]
DRP[92] bit 4MAIN[15][26][18]
DRP[92] bit 5MAIN[15][27][18]
DRP[92] bit 6MAIN[15][26][19]
DRP[92] bit 7MAIN[15][27][19]
DRP[92] bit 8MAIN[15][26][20]
DRP[92] bit 9MAIN[15][27][20]
DRP[92] bit 10MAIN[15][26][21]
DRP[92] bit 11MAIN[15][27][21]
DRP[92] bit 12MAIN[15][26][22]
DRP[92] bit 13MAIN[15][27][22]
DRP[92] bit 14MAIN[15][26][23]
DRP[92] bit 15MAIN[15][27][23]
DRP[93] bit 0MAIN[15][26][24]
DRP[93] bit 1MAIN[15][27][24]
DRP[93] bit 2MAIN[15][26][25]
DRP[93] bit 3MAIN[15][27][25]
DRP[93] bit 4MAIN[15][26][26]
DRP[93] bit 5MAIN[15][27][26]
DRP[93] bit 6MAIN[15][26][27]
DRP[93] bit 7MAIN[15][27][27]
DRP[93] bit 8MAIN[15][26][28]
DRP[93] bit 9MAIN[15][27][28]
DRP[93] bit 10MAIN[15][26][29]
DRP[93] bit 11MAIN[15][27][29]
DRP[93] bit 12MAIN[15][26][30]
DRP[93] bit 13MAIN[15][27][30]
DRP[93] bit 14MAIN[15][26][31]
DRP[93] bit 15MAIN[15][27][31]
DRP[94] bit 0MAIN[15][26][32]
DRP[94] bit 1MAIN[15][27][32]
DRP[94] bit 2MAIN[15][26][33]
DRP[94] bit 3MAIN[15][27][33]
DRP[94] bit 4MAIN[15][26][34]
DRP[94] bit 5MAIN[15][27][34]
DRP[94] bit 6MAIN[15][26][35]
DRP[94] bit 7MAIN[15][27][35]
DRP[94] bit 8MAIN[15][26][36]
DRP[94] bit 9MAIN[15][27][36]
DRP[94] bit 10MAIN[15][26][37]
DRP[94] bit 11MAIN[15][27][37]
DRP[94] bit 12MAIN[15][26][38]
DRP[94] bit 13MAIN[15][27][38]
DRP[94] bit 14MAIN[15][26][39]
DRP[94] bit 15MAIN[15][27][39]
DRP[95] bit 0MAIN[15][26][40]
DRP[95] bit 1MAIN[15][27][40]
DRP[95] bit 2MAIN[15][26][41]
DRP[95] bit 3MAIN[15][27][41]
DRP[95] bit 4MAIN[15][26][42]
DRP[95] bit 5MAIN[15][27][42]
DRP[95] bit 6MAIN[15][26][43]
DRP[95] bit 7MAIN[15][27][43]
DRP[95] bit 8MAIN[15][26][44]
DRP[95] bit 9MAIN[15][27][44]
DRP[95] bit 10MAIN[15][26][45]
DRP[95] bit 11MAIN[15][27][45]
DRP[95] bit 12MAIN[15][26][46]
DRP[95] bit 13MAIN[15][27][46]
DRP[95] bit 14MAIN[15][26][47]
DRP[95] bit 15MAIN[15][27][47]
DRP[96] bit 0MAIN[16][26][0]
DRP[96] bit 1MAIN[16][27][0]
DRP[96] bit 2MAIN[16][26][1]
DRP[96] bit 3MAIN[16][27][1]
DRP[96] bit 4MAIN[16][26][2]
DRP[96] bit 5MAIN[16][27][2]
DRP[96] bit 6MAIN[16][26][3]
DRP[96] bit 7MAIN[16][27][3]
DRP[96] bit 8MAIN[16][26][4]
DRP[96] bit 9MAIN[16][27][4]
DRP[96] bit 10MAIN[16][26][5]
DRP[96] bit 11MAIN[16][27][5]
DRP[96] bit 12MAIN[16][26][6]
DRP[96] bit 13MAIN[16][27][6]
DRP[96] bit 14MAIN[16][26][7]
DRP[96] bit 15MAIN[16][27][7]
DRP[97] bit 0MAIN[16][26][8]
DRP[97] bit 1MAIN[16][27][8]
DRP[97] bit 2MAIN[16][26][9]
DRP[97] bit 3MAIN[16][27][9]
DRP[97] bit 4MAIN[16][26][10]
DRP[97] bit 5MAIN[16][27][10]
DRP[97] bit 6MAIN[16][26][11]
DRP[97] bit 7MAIN[16][27][11]
DRP[97] bit 8MAIN[16][26][12]
DRP[97] bit 9MAIN[16][27][12]
DRP[97] bit 10MAIN[16][26][13]
DRP[97] bit 11MAIN[16][27][13]
DRP[97] bit 12MAIN[16][26][14]
DRP[97] bit 13MAIN[16][27][14]
DRP[97] bit 14MAIN[16][26][15]
DRP[97] bit 15MAIN[16][27][15]
DRP[98] bit 0MAIN[16][26][16]
DRP[98] bit 1MAIN[16][27][16]
DRP[98] bit 2MAIN[16][26][17]
DRP[98] bit 3MAIN[16][27][17]
DRP[98] bit 4MAIN[16][26][18]
DRP[98] bit 5MAIN[16][27][18]
DRP[98] bit 6MAIN[16][26][19]
DRP[98] bit 7MAIN[16][27][19]
DRP[98] bit 8MAIN[16][26][20]
DRP[98] bit 9MAIN[16][27][20]
DRP[98] bit 10MAIN[16][26][21]
DRP[98] bit 11MAIN[16][27][21]
DRP[98] bit 12MAIN[16][26][22]
DRP[98] bit 13MAIN[16][27][22]
DRP[98] bit 14MAIN[16][26][23]
DRP[98] bit 15MAIN[16][27][23]
DRP[99] bit 0MAIN[16][26][24]
DRP[99] bit 1MAIN[16][27][24]
DRP[99] bit 2MAIN[16][26][25]
DRP[99] bit 3MAIN[16][27][25]
DRP[99] bit 4MAIN[16][26][26]
DRP[99] bit 5MAIN[16][27][26]
DRP[99] bit 6MAIN[16][26][27]
DRP[99] bit 7MAIN[16][27][27]
DRP[99] bit 8MAIN[16][26][28]
DRP[99] bit 9MAIN[16][27][28]
DRP[99] bit 10MAIN[16][26][29]
DRP[99] bit 11MAIN[16][27][29]
DRP[99] bit 12MAIN[16][26][30]
DRP[99] bit 13MAIN[16][27][30]
DRP[99] bit 14MAIN[16][26][31]
DRP[99] bit 15MAIN[16][27][31]
DRP[100] bit 0MAIN[16][26][32]
DRP[100] bit 1MAIN[16][27][32]
DRP[100] bit 2MAIN[16][26][33]
DRP[100] bit 3MAIN[16][27][33]
DRP[100] bit 4MAIN[16][26][34]
DRP[100] bit 5MAIN[16][27][34]
DRP[100] bit 6MAIN[16][26][35]
DRP[100] bit 7MAIN[16][27][35]
DRP[100] bit 8MAIN[16][26][36]
DRP[100] bit 9MAIN[16][27][36]
DRP[100] bit 10MAIN[16][26][37]
DRP[100] bit 11MAIN[16][27][37]
DRP[100] bit 12MAIN[16][26][38]
DRP[100] bit 13MAIN[16][27][38]
DRP[100] bit 14MAIN[16][26][39]
DRP[100] bit 15MAIN[16][27][39]
DRP[101] bit 0MAIN[16][26][40]
DRP[101] bit 1MAIN[16][27][40]
DRP[101] bit 2MAIN[16][26][41]
DRP[101] bit 3MAIN[16][27][41]
DRP[101] bit 4MAIN[16][26][42]
DRP[101] bit 5MAIN[16][27][42]
DRP[101] bit 6MAIN[16][26][43]
DRP[101] bit 7MAIN[16][27][43]
DRP[101] bit 8MAIN[16][26][44]
DRP[101] bit 9MAIN[16][27][44]
DRP[101] bit 10MAIN[16][26][45]
DRP[101] bit 11MAIN[16][27][45]
DRP[101] bit 12MAIN[16][26][46]
DRP[101] bit 13MAIN[16][27][46]
DRP[101] bit 14MAIN[16][26][47]
DRP[101] bit 15MAIN[16][27][47]
DRP[102] bit 0MAIN[17][26][0]
DRP[102] bit 1MAIN[17][27][0]
DRP[102] bit 2MAIN[17][26][1]
DRP[102] bit 3MAIN[17][27][1]
DRP[102] bit 4MAIN[17][26][2]
DRP[102] bit 5MAIN[17][27][2]
DRP[102] bit 6MAIN[17][26][3]
DRP[102] bit 7MAIN[17][27][3]
DRP[102] bit 8MAIN[17][26][4]
DRP[102] bit 9MAIN[17][27][4]
DRP[102] bit 10MAIN[17][26][5]
DRP[102] bit 11MAIN[17][27][5]
DRP[102] bit 12MAIN[17][26][6]
DRP[102] bit 13MAIN[17][27][6]
DRP[102] bit 14MAIN[17][26][7]
DRP[102] bit 15MAIN[17][27][7]
DRP[103] bit 0MAIN[17][26][8]
DRP[103] bit 1MAIN[17][27][8]
DRP[103] bit 2MAIN[17][26][9]
DRP[103] bit 3MAIN[17][27][9]
DRP[103] bit 4MAIN[17][26][10]
DRP[103] bit 5MAIN[17][27][10]
DRP[103] bit 6MAIN[17][26][11]
DRP[103] bit 7MAIN[17][27][11]
DRP[103] bit 8MAIN[17][26][12]
DRP[103] bit 9MAIN[17][27][12]
DRP[103] bit 10MAIN[17][26][13]
DRP[103] bit 11MAIN[17][27][13]
DRP[103] bit 12MAIN[17][26][14]
DRP[103] bit 13MAIN[17][27][14]
DRP[103] bit 14MAIN[17][26][15]
DRP[103] bit 15MAIN[17][27][15]
DRP[104] bit 0MAIN[17][26][16]
DRP[104] bit 1MAIN[17][27][16]
DRP[104] bit 2MAIN[17][26][17]
DRP[104] bit 3MAIN[17][27][17]
DRP[104] bit 4MAIN[17][26][18]
DRP[104] bit 5MAIN[17][27][18]
DRP[104] bit 6MAIN[17][26][19]
DRP[104] bit 7MAIN[17][27][19]
DRP[104] bit 8MAIN[17][26][20]
DRP[104] bit 9MAIN[17][27][20]
DRP[104] bit 10MAIN[17][26][21]
DRP[104] bit 11MAIN[17][27][21]
DRP[104] bit 12MAIN[17][26][22]
DRP[104] bit 13MAIN[17][27][22]
DRP[104] bit 14MAIN[17][26][23]
DRP[104] bit 15MAIN[17][27][23]
DRP[105] bit 0MAIN[17][26][24]
DRP[105] bit 1MAIN[17][27][24]
DRP[105] bit 2MAIN[17][26][25]
DRP[105] bit 3MAIN[17][27][25]
DRP[105] bit 4MAIN[17][26][26]
DRP[105] bit 5MAIN[17][27][26]
DRP[105] bit 6MAIN[17][26][27]
DRP[105] bit 7MAIN[17][27][27]
DRP[105] bit 8MAIN[17][26][28]
DRP[105] bit 9MAIN[17][27][28]
DRP[105] bit 10MAIN[17][26][29]
DRP[105] bit 11MAIN[17][27][29]
DRP[105] bit 12MAIN[17][26][30]
DRP[105] bit 13MAIN[17][27][30]
DRP[105] bit 14MAIN[17][26][31]
DRP[105] bit 15MAIN[17][27][31]
DRP[106] bit 0MAIN[17][26][32]
DRP[106] bit 1MAIN[17][27][32]
DRP[106] bit 2MAIN[17][26][33]
DRP[106] bit 3MAIN[17][27][33]
DRP[106] bit 4MAIN[17][26][34]
DRP[106] bit 5MAIN[17][27][34]
DRP[106] bit 6MAIN[17][26][35]
DRP[106] bit 7MAIN[17][27][35]
DRP[106] bit 8MAIN[17][26][36]
DRP[106] bit 9MAIN[17][27][36]
DRP[106] bit 10MAIN[17][26][37]
DRP[106] bit 11MAIN[17][27][37]
DRP[106] bit 12MAIN[17][26][38]
DRP[106] bit 13MAIN[17][27][38]
DRP[106] bit 14MAIN[17][26][39]
DRP[106] bit 15MAIN[17][27][39]
DRP[107] bit 0MAIN[17][26][40]
DRP[107] bit 1MAIN[17][27][40]
DRP[107] bit 2MAIN[17][26][41]
DRP[107] bit 3MAIN[17][27][41]
DRP[107] bit 4MAIN[17][26][42]
DRP[107] bit 5MAIN[17][27][42]
DRP[107] bit 6MAIN[17][26][43]
DRP[107] bit 7MAIN[17][27][43]
DRP[107] bit 8MAIN[17][26][44]
DRP[107] bit 9MAIN[17][27][44]
DRP[107] bit 10MAIN[17][26][45]
DRP[107] bit 11MAIN[17][27][45]
DRP[107] bit 12MAIN[17][26][46]
DRP[107] bit 13MAIN[17][27][46]
DRP[107] bit 14MAIN[17][26][47]
DRP[107] bit 15MAIN[17][27][47]
DRP[108] bit 0MAIN[18][26][0]
DRP[108] bit 1MAIN[18][27][0]
DRP[108] bit 2MAIN[18][26][1]
DRP[108] bit 3MAIN[18][27][1]
DRP[108] bit 4MAIN[18][26][2]
DRP[108] bit 5MAIN[18][27][2]
DRP[108] bit 6MAIN[18][26][3]
DRP[108] bit 7MAIN[18][27][3]
DRP[108] bit 8MAIN[18][26][4]
DRP[108] bit 9MAIN[18][27][4]
DRP[108] bit 10MAIN[18][26][5]
DRP[108] bit 11MAIN[18][27][5]
DRP[108] bit 12MAIN[18][26][6]
DRP[108] bit 13MAIN[18][27][6]
DRP[108] bit 14MAIN[18][26][7]
DRP[108] bit 15MAIN[18][27][7]
DRP[109] bit 0MAIN[18][26][8]
DRP[109] bit 1MAIN[18][27][8]
DRP[109] bit 2MAIN[18][26][9]
DRP[109] bit 3MAIN[18][27][9]
DRP[109] bit 4MAIN[18][26][10]
DRP[109] bit 5MAIN[18][27][10]
DRP[109] bit 6MAIN[18][26][11]
DRP[109] bit 7MAIN[18][27][11]
DRP[109] bit 8MAIN[18][26][12]
DRP[109] bit 9MAIN[18][27][12]
DRP[109] bit 10MAIN[18][26][13]
DRP[109] bit 11MAIN[18][27][13]
DRP[109] bit 12MAIN[18][26][14]
DRP[109] bit 13MAIN[18][27][14]
DRP[109] bit 14MAIN[18][26][15]
DRP[109] bit 15MAIN[18][27][15]
DRP[110] bit 0MAIN[18][26][16]
DRP[110] bit 1MAIN[18][27][16]
DRP[110] bit 2MAIN[18][26][17]
DRP[110] bit 3MAIN[18][27][17]
DRP[110] bit 4MAIN[18][26][18]
DRP[110] bit 5MAIN[18][27][18]
DRP[110] bit 6MAIN[18][26][19]
DRP[110] bit 7MAIN[18][27][19]
DRP[110] bit 8MAIN[18][26][20]
DRP[110] bit 9MAIN[18][27][20]
DRP[110] bit 10MAIN[18][26][21]
DRP[110] bit 11MAIN[18][27][21]
DRP[110] bit 12MAIN[18][26][22]
DRP[110] bit 13MAIN[18][27][22]
DRP[110] bit 14MAIN[18][26][23]
DRP[110] bit 15MAIN[18][27][23]
DRP[111] bit 0MAIN[18][26][24]
DRP[111] bit 1MAIN[18][27][24]
DRP[111] bit 2MAIN[18][26][25]
DRP[111] bit 3MAIN[18][27][25]
DRP[111] bit 4MAIN[18][26][26]
DRP[111] bit 5MAIN[18][27][26]
DRP[111] bit 6MAIN[18][26][27]
DRP[111] bit 7MAIN[18][27][27]
DRP[111] bit 8MAIN[18][26][28]
DRP[111] bit 9MAIN[18][27][28]
DRP[111] bit 10MAIN[18][26][29]
DRP[111] bit 11MAIN[18][27][29]
DRP[111] bit 12MAIN[18][26][30]
DRP[111] bit 13MAIN[18][27][30]
DRP[111] bit 14MAIN[18][26][31]
DRP[111] bit 15MAIN[18][27][31]
DRP[112] bit 0MAIN[18][26][32]
DRP[112] bit 1MAIN[18][27][32]
DRP[112] bit 2MAIN[18][26][33]
DRP[112] bit 3MAIN[18][27][33]
DRP[112] bit 4MAIN[18][26][34]
DRP[112] bit 5MAIN[18][27][34]
DRP[112] bit 6MAIN[18][26][35]
DRP[112] bit 7MAIN[18][27][35]
DRP[112] bit 8MAIN[18][26][36]
DRP[112] bit 9MAIN[18][27][36]
DRP[112] bit 10MAIN[18][26][37]
DRP[112] bit 11MAIN[18][27][37]
DRP[112] bit 12MAIN[18][26][38]
DRP[112] bit 13MAIN[18][27][38]
DRP[112] bit 14MAIN[18][26][39]
DRP[112] bit 15MAIN[18][27][39]
DRP[113] bit 0MAIN[18][26][40]
DRP[113] bit 1MAIN[18][27][40]
DRP[113] bit 2MAIN[18][26][41]
DRP[113] bit 3MAIN[18][27][41]
DRP[113] bit 4MAIN[18][26][42]
DRP[113] bit 5MAIN[18][27][42]
DRP[113] bit 6MAIN[18][26][43]
DRP[113] bit 7MAIN[18][27][43]
DRP[113] bit 8MAIN[18][26][44]
DRP[113] bit 9MAIN[18][27][44]
DRP[113] bit 10MAIN[18][26][45]
DRP[113] bit 11MAIN[18][27][45]
DRP[113] bit 12MAIN[18][26][46]
DRP[113] bit 13MAIN[18][27][46]
DRP[113] bit 14MAIN[18][26][47]
DRP[113] bit 15MAIN[18][27][47]
DRP[114] bit 0MAIN[19][26][0]
DRP[114] bit 1MAIN[19][27][0]
DRP[114] bit 2MAIN[19][26][1]
DRP[114] bit 3MAIN[19][27][1]
DRP[114] bit 4MAIN[19][26][2]
DRP[114] bit 5MAIN[19][27][2]
DRP[114] bit 6MAIN[19][26][3]
DRP[114] bit 7MAIN[19][27][3]
DRP[114] bit 8MAIN[19][26][4]
DRP[114] bit 9MAIN[19][27][4]
DRP[114] bit 10MAIN[19][26][5]
DRP[114] bit 11MAIN[19][27][5]
DRP[114] bit 12MAIN[19][26][6]
DRP[114] bit 13MAIN[19][27][6]
DRP[114] bit 14MAIN[19][26][7]
DRP[114] bit 15MAIN[19][27][7]
DRP[115] bit 0MAIN[19][26][8]
DRP[115] bit 1MAIN[19][27][8]
DRP[115] bit 2MAIN[19][26][9]
DRP[115] bit 3MAIN[19][27][9]
DRP[115] bit 4MAIN[19][26][10]
DRP[115] bit 5MAIN[19][27][10]
DRP[115] bit 6MAIN[19][26][11]
DRP[115] bit 7MAIN[19][27][11]
DRP[115] bit 8MAIN[19][26][12]
DRP[115] bit 9MAIN[19][27][12]
DRP[115] bit 10MAIN[19][26][13]
DRP[115] bit 11MAIN[19][27][13]
DRP[115] bit 12MAIN[19][26][14]
DRP[115] bit 13MAIN[19][27][14]
DRP[115] bit 14MAIN[19][26][15]
DRP[115] bit 15MAIN[19][27][15]
DRP[116] bit 0MAIN[19][26][16]
DRP[116] bit 1MAIN[19][27][16]
DRP[116] bit 2MAIN[19][26][17]
DRP[116] bit 3MAIN[19][27][17]
DRP[116] bit 4MAIN[19][26][18]
DRP[116] bit 5MAIN[19][27][18]
DRP[116] bit 6MAIN[19][26][19]
DRP[116] bit 7MAIN[19][27][19]
DRP[116] bit 8MAIN[19][26][20]
DRP[116] bit 9MAIN[19][27][20]
DRP[116] bit 10MAIN[19][26][21]
DRP[116] bit 11MAIN[19][27][21]
DRP[116] bit 12MAIN[19][26][22]
DRP[116] bit 13MAIN[19][27][22]
DRP[116] bit 14MAIN[19][26][23]
DRP[116] bit 15MAIN[19][27][23]
DRP[117] bit 0MAIN[19][26][24]
DRP[117] bit 1MAIN[19][27][24]
DRP[117] bit 2MAIN[19][26][25]
DRP[117] bit 3MAIN[19][27][25]
DRP[117] bit 4MAIN[19][26][26]
DRP[117] bit 5MAIN[19][27][26]
DRP[117] bit 6MAIN[19][26][27]
DRP[117] bit 7MAIN[19][27][27]
DRP[117] bit 8MAIN[19][26][28]
DRP[117] bit 9MAIN[19][27][28]
DRP[117] bit 10MAIN[19][26][29]
DRP[117] bit 11MAIN[19][27][29]
DRP[117] bit 12MAIN[19][26][30]
DRP[117] bit 13MAIN[19][27][30]
DRP[117] bit 14MAIN[19][26][31]
DRP[117] bit 15MAIN[19][27][31]
DRP[118] bit 0MAIN[19][26][32]
DRP[118] bit 1MAIN[19][27][32]
DRP[118] bit 2MAIN[19][26][33]
DRP[118] bit 3MAIN[19][27][33]
DRP[118] bit 4MAIN[19][26][34]
DRP[118] bit 5MAIN[19][27][34]
DRP[118] bit 6MAIN[19][26][35]
DRP[118] bit 7MAIN[19][27][35]
DRP[118] bit 8MAIN[19][26][36]
DRP[118] bit 9MAIN[19][27][36]
DRP[118] bit 10MAIN[19][26][37]
DRP[118] bit 11MAIN[19][27][37]
DRP[118] bit 12MAIN[19][26][38]
DRP[118] bit 13MAIN[19][27][38]
DRP[118] bit 14MAIN[19][26][39]
DRP[118] bit 15MAIN[19][27][39]
DRP[119] bit 0MAIN[19][26][40]
DRP[119] bit 1MAIN[19][27][40]
DRP[119] bit 2MAIN[19][26][41]
DRP[119] bit 3MAIN[19][27][41]
DRP[119] bit 4MAIN[19][26][42]
DRP[119] bit 5MAIN[19][27][42]
DRP[119] bit 6MAIN[19][26][43]
DRP[119] bit 7MAIN[19][27][43]
DRP[119] bit 8MAIN[19][26][44]
DRP[119] bit 9MAIN[19][27][44]
DRP[119] bit 10MAIN[19][26][45]
DRP[119] bit 11MAIN[19][27][45]
DRP[119] bit 12MAIN[19][26][46]
DRP[119] bit 13MAIN[19][27][46]
DRP[119] bit 14MAIN[19][26][47]
DRP[119] bit 15MAIN[19][27][47]
VSEC_CAP_ONMAIN[12][27][6]
VSEC_CAP_IS_LINK_VISIBLE
VC0_CPL_INFINITEMAIN[13][27][45]
VC_CAP_REJECT_SNOOP_TRANSACTIONSMAIN[11][26][0]
VC_CAP_ONMAIN[10][26][38]
UR_INV_REQMAIN[14][27][39]
UPSTREAM_FACINGMAIN[13][26][23]
UPCONFIG_CAPABLEMAIN[13][27][22]
TL_TX_CHECKS_DISABLEMAIN[13][27][40]
TL_TFC_DISABLEMAIN[13][26][40]
TL_RBYPASSMAIN[13][26][41]
TEST_MODE_PIN_CHARMAIN[15][27][4]
SLOT_CAP_POWER_INDICATOR_PRESENTMAIN[9][27][47]
SLOT_CAP_POWER_CONTROLLER_PRESENTMAIN[9][26][47]
SLOT_CAP_NO_CMD_COMPLETED_SUPPORTMAIN[9][26][40]
SLOT_CAP_MRL_SENSOR_PRESENTMAIN[9][27][39]
SLOT_CAP_HOTPLUG_SURPRISEMAIN[9][26][39]
SLOT_CAP_HOTPLUG_CAPABLEMAIN[9][27][38]
SLOT_CAP_ELEC_INTERLOCK_PRESENTMAIN[9][26][38]
SLOT_CAP_ATT_INDICATOR_PRESENTMAIN[9][27][37]
SLOT_CAP_ATT_BUTTON_PRESENTMAIN[9][26][37]
SELECT_DLL_IFMAIN[9][27][36]
ROOT_CAP_CRS_SW_VISIBILITYMAIN[9][26][36]
RECRC_CHK_TRIMMAIN[14][26][39]
PM_CSR_NOSOFTRSTMAIN[8][27][38]
PM_CSR_B2B3MAIN[8][27][37]
PM_CSR_BPCCENMAIN[8][26][38]
PM_CAP_PME_CLOCKMAIN[8][27][32]
PM_CAP_ONMAIN[8][26][32]
PM_CAP_D2SUPPORTMAIN[8][26][22]
PM_CAP_D1SUPPORTMAIN[8][27][21]
PM_CAP_DSIMAIN[8][27][22]
PL_FAST_TRAINMAIN[13][26][22]
PCIE_CAP_SLOT_IMPLEMENTEDMAIN[8][27][13]
PCIE_CAP_ONMAIN[8][26][12]
MSIX_CAP_ONMAIN[6][26][44]
MSI_CAP_64_BIT_ADDR_CAPABLEMAIN[6][26][12]
MSI_CAP_PER_VECTOR_MASKING_CAPABLEMAIN[6][27][28]
MSI_CAP_ONMAIN[6][26][28]
LL_REPLAY_TIMEOUT_ENMAIN[12][27][39]
LL_ACK_TIMEOUT_ENMAIN[12][27][23]
LINK_STATUS_SLOT_CLOCK_CONFIG
LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE
LINK_CTRL2_DEEMPHASIS
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE
LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP
LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP
LINK_CAP_CLOCK_POWER_MANAGEMENT
IS_SWITCHMAIN[5][26][24]
EXIT_LOOPBACK_ON_EIMAIN[13][27][23]
ENTER_RVRY_EI_L0MAIN[12][26][42]
ENABLE_RX_TD_ECRC_TRIMMAIN[13][27][37]
DSN_CAP_ONMAIN[4][26][46]
DISABLE_SCRAMBLINGMAIN[12][27][41]
DISABLE_RX_TC_FILTERMAIN[13][27][29]
DISABLE_LANE_REVERSALMAIN[12][26][41]
DISABLE_ID_CHECKMAIN[13][26][29]
DISABLE_BAR_FILTERINGMAIN[13][27][28]
DISABLE_ASPM_L1_TIMERMAIN[13][26][28]
DEV_CONTROL_AUX_POWER_SUPPORTEDMAIN[4][26][12]
DEV_CAP_ROLE_BASED_ERRORMAIN[4][27][6]
DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLEMAIN[4][27][3]
DEV_CAP_EXT_TAG_SUPPORTEDMAIN[4][26][3]
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUEMAIN[3][27][47]
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALEMAIN[3][26][47]
CPL_TIMEOUT_DISABLE_SUPPORTEDMAIN[3][27][44]
CMD_INTX_IMPLEMENTEDMAIN[3][26][44]
ALLOW_X8_GEN2MAIN[13][26][20]
AER_CAP_PERMIT_ROOTERR_UPDATEMAIN[0][26][21]
AER_CAP_ONMAIN[0][26][38]
AER_CAP_ECRC_GEN_CAPABLEMAIN[0][27][0]
AER_CAP_ECRC_CHECK_CAPABLEMAIN[0][26][0]
AER_BASE_PTR bit 0MAIN[0][26][24]
AER_BASE_PTR bit 1MAIN[0][27][24]
AER_BASE_PTR bit 2MAIN[0][26][25]
AER_BASE_PTR bit 3MAIN[0][27][25]
AER_BASE_PTR bit 4MAIN[0][26][26]
AER_BASE_PTR bit 5MAIN[0][27][26]
AER_BASE_PTR bit 6MAIN[0][26][27]
AER_BASE_PTR bit 7MAIN[0][27][27]
AER_BASE_PTR bit 8MAIN[0][26][28]
AER_BASE_PTR bit 9MAIN[0][27][28]
AER_BASE_PTR bit 10MAIN[0][26][29]
AER_BASE_PTR bit 11MAIN[0][27][29]
AER_CAP_ID bit 0MAIN[0][26][8]
AER_CAP_ID bit 1MAIN[0][27][8]
AER_CAP_ID bit 2MAIN[0][26][9]
AER_CAP_ID bit 3MAIN[0][27][9]
AER_CAP_ID bit 4MAIN[0][26][10]
AER_CAP_ID bit 5MAIN[0][27][10]
AER_CAP_ID bit 6MAIN[0][26][11]
AER_CAP_ID bit 7MAIN[0][27][11]
AER_CAP_ID bit 8MAIN[0][26][12]
AER_CAP_ID bit 9MAIN[0][27][12]
AER_CAP_ID bit 10MAIN[0][26][13]
AER_CAP_ID bit 11MAIN[0][27][13]
AER_CAP_ID bit 12MAIN[0][26][14]
AER_CAP_ID bit 13MAIN[0][27][14]
AER_CAP_ID bit 14MAIN[0][26][15]
AER_CAP_ID bit 15MAIN[0][27][15]
AER_CAP_INT_MSG_NUM_MSI bit 0MAIN[0][26][16]
AER_CAP_INT_MSG_NUM_MSI bit 1MAIN[0][27][16]
AER_CAP_INT_MSG_NUM_MSI bit 2MAIN[0][26][17]
AER_CAP_INT_MSG_NUM_MSI bit 3MAIN[0][27][17]
AER_CAP_INT_MSG_NUM_MSI bit 4MAIN[0][26][18]
AER_CAP_INT_MSG_NUM_MSIX bit 0MAIN[0][27][18]
AER_CAP_INT_MSG_NUM_MSIX bit 1MAIN[0][26][19]
AER_CAP_INT_MSG_NUM_MSIX bit 2MAIN[0][27][19]
AER_CAP_INT_MSG_NUM_MSIX bit 3MAIN[0][26][20]
AER_CAP_INT_MSG_NUM_MSIX bit 4MAIN[0][27][20]
AER_CAP_NEXTPTR bit 0MAIN[0][26][32]
AER_CAP_NEXTPTR bit 1MAIN[0][27][32]
AER_CAP_NEXTPTR bit 2MAIN[0][26][33]
AER_CAP_NEXTPTR bit 3MAIN[0][27][33]
AER_CAP_NEXTPTR bit 4MAIN[0][26][34]
AER_CAP_NEXTPTR bit 5MAIN[0][27][34]
AER_CAP_NEXTPTR bit 6MAIN[0][26][35]
AER_CAP_NEXTPTR bit 7MAIN[0][27][35]
AER_CAP_NEXTPTR bit 8MAIN[0][26][36]
AER_CAP_NEXTPTR bit 9MAIN[0][27][36]
AER_CAP_NEXTPTR bit 10MAIN[0][26][37]
AER_CAP_NEXTPTR bit 11MAIN[0][27][37]
AER_CAP_VERSION bit 0MAIN[0][27][21]
AER_CAP_VERSION bit 1MAIN[0][26][22]
AER_CAP_VERSION bit 2MAIN[0][27][22]
AER_CAP_VERSION bit 3MAIN[0][26][23]
BAR0 bit 0MAIN[0][26][40]
BAR0 bit 1MAIN[0][27][40]
BAR0 bit 2MAIN[0][26][41]
BAR0 bit 3MAIN[0][27][41]
BAR0 bit 4MAIN[0][26][42]
BAR0 bit 5MAIN[0][27][42]
BAR0 bit 6MAIN[0][26][43]
BAR0 bit 7MAIN[0][27][43]
BAR0 bit 8MAIN[0][26][44]
BAR0 bit 9MAIN[0][27][44]
BAR0 bit 10MAIN[0][26][45]
BAR0 bit 11MAIN[0][27][45]
BAR0 bit 12MAIN[0][26][46]
BAR0 bit 13MAIN[0][27][46]
BAR0 bit 14MAIN[0][26][47]
BAR0 bit 15MAIN[0][27][47]
BAR0 bit 16MAIN[1][26][0]
BAR0 bit 17MAIN[1][27][0]
BAR0 bit 18MAIN[1][26][1]
BAR0 bit 19MAIN[1][27][1]
BAR0 bit 20MAIN[1][26][2]
BAR0 bit 21MAIN[1][27][2]
BAR0 bit 22MAIN[1][26][3]
BAR0 bit 23MAIN[1][27][3]
BAR0 bit 24MAIN[1][26][4]
BAR0 bit 25MAIN[1][27][4]
BAR0 bit 26MAIN[1][26][5]
BAR0 bit 27MAIN[1][27][5]
BAR0 bit 28MAIN[1][26][6]
BAR0 bit 29MAIN[1][27][6]
BAR0 bit 30MAIN[1][26][7]
BAR0 bit 31MAIN[1][27][7]
BAR1 bit 0MAIN[1][26][8]
BAR1 bit 1MAIN[1][27][8]
BAR1 bit 2MAIN[1][26][9]
BAR1 bit 3MAIN[1][27][9]
BAR1 bit 4MAIN[1][26][10]
BAR1 bit 5MAIN[1][27][10]
BAR1 bit 6MAIN[1][26][11]
BAR1 bit 7MAIN[1][27][11]
BAR1 bit 8MAIN[1][26][12]
BAR1 bit 9MAIN[1][27][12]
BAR1 bit 10MAIN[1][26][13]
BAR1 bit 11MAIN[1][27][13]
BAR1 bit 12MAIN[1][26][14]
BAR1 bit 13MAIN[1][27][14]
BAR1 bit 14MAIN[1][26][15]
BAR1 bit 15MAIN[1][27][15]
BAR1 bit 16MAIN[1][26][16]
BAR1 bit 17MAIN[1][27][16]
BAR1 bit 18MAIN[1][26][17]
BAR1 bit 19MAIN[1][27][17]
BAR1 bit 20MAIN[1][26][18]
BAR1 bit 21MAIN[1][27][18]
BAR1 bit 22MAIN[1][26][19]
BAR1 bit 23MAIN[1][27][19]
BAR1 bit 24MAIN[1][26][20]
BAR1 bit 25MAIN[1][27][20]
BAR1 bit 26MAIN[1][26][21]
BAR1 bit 27MAIN[1][27][21]
BAR1 bit 28MAIN[1][26][22]
BAR1 bit 29MAIN[1][27][22]
BAR1 bit 30MAIN[1][26][23]
BAR1 bit 31MAIN[1][27][23]
BAR2 bit 0MAIN[1][26][24]
BAR2 bit 1MAIN[1][27][24]
BAR2 bit 2MAIN[1][26][25]
BAR2 bit 3MAIN[1][27][25]
BAR2 bit 4MAIN[1][26][26]
BAR2 bit 5MAIN[1][27][26]
BAR2 bit 6MAIN[1][26][27]
BAR2 bit 7MAIN[1][27][27]
BAR2 bit 8MAIN[1][26][28]
BAR2 bit 9MAIN[1][27][28]
BAR2 bit 10MAIN[1][26][29]
BAR2 bit 11MAIN[1][27][29]
BAR2 bit 12MAIN[1][26][30]
BAR2 bit 13MAIN[1][27][30]
BAR2 bit 14MAIN[1][26][31]
BAR2 bit 15MAIN[1][27][31]
BAR2 bit 16MAIN[1][26][32]
BAR2 bit 17MAIN[1][27][32]
BAR2 bit 18MAIN[1][26][33]
BAR2 bit 19MAIN[1][27][33]
BAR2 bit 20MAIN[1][26][34]
BAR2 bit 21MAIN[1][27][34]
BAR2 bit 22MAIN[1][26][35]
BAR2 bit 23MAIN[1][27][35]
BAR2 bit 24MAIN[1][26][36]
BAR2 bit 25MAIN[1][27][36]
BAR2 bit 26MAIN[1][26][37]
BAR2 bit 27MAIN[1][27][37]
BAR2 bit 28MAIN[1][26][38]
BAR2 bit 29MAIN[1][27][38]
BAR2 bit 30MAIN[1][26][39]
BAR2 bit 31MAIN[1][27][39]
BAR3 bit 0MAIN[1][26][40]
BAR3 bit 1MAIN[1][27][40]
BAR3 bit 2MAIN[1][26][41]
BAR3 bit 3MAIN[1][27][41]
BAR3 bit 4MAIN[1][26][42]
BAR3 bit 5MAIN[1][27][42]
BAR3 bit 6MAIN[1][26][43]
BAR3 bit 7MAIN[1][27][43]
BAR3 bit 8MAIN[1][26][44]
BAR3 bit 9MAIN[1][27][44]
BAR3 bit 10MAIN[1][26][45]
BAR3 bit 11MAIN[1][27][45]
BAR3 bit 12MAIN[1][26][46]
BAR3 bit 13MAIN[1][27][46]
BAR3 bit 14MAIN[1][26][47]
BAR3 bit 15MAIN[1][27][47]
BAR3 bit 16MAIN[2][26][0]
BAR3 bit 17MAIN[2][27][0]
BAR3 bit 18MAIN[2][26][1]
BAR3 bit 19MAIN[2][27][1]
BAR3 bit 20MAIN[2][26][2]
BAR3 bit 21MAIN[2][27][2]
BAR3 bit 22MAIN[2][26][3]
BAR3 bit 23MAIN[2][27][3]
BAR3 bit 24MAIN[2][26][4]
BAR3 bit 25MAIN[2][27][4]
BAR3 bit 26MAIN[2][26][5]
BAR3 bit 27MAIN[2][27][5]
BAR3 bit 28MAIN[2][26][6]
BAR3 bit 29MAIN[2][27][6]
BAR3 bit 30MAIN[2][26][7]
BAR3 bit 31MAIN[2][27][7]
BAR4 bit 0MAIN[2][26][8]
BAR4 bit 1MAIN[2][27][8]
BAR4 bit 2MAIN[2][26][9]
BAR4 bit 3MAIN[2][27][9]
BAR4 bit 4MAIN[2][26][10]
BAR4 bit 5MAIN[2][27][10]
BAR4 bit 6MAIN[2][26][11]
BAR4 bit 7MAIN[2][27][11]
BAR4 bit 8MAIN[2][26][12]
BAR4 bit 9MAIN[2][27][12]
BAR4 bit 10MAIN[2][26][13]
BAR4 bit 11MAIN[2][27][13]
BAR4 bit 12MAIN[2][26][14]
BAR4 bit 13MAIN[2][27][14]
BAR4 bit 14MAIN[2][26][15]
BAR4 bit 15MAIN[2][27][15]
BAR4 bit 16MAIN[2][26][16]
BAR4 bit 17MAIN[2][27][16]
BAR4 bit 18MAIN[2][26][17]
BAR4 bit 19MAIN[2][27][17]
BAR4 bit 20MAIN[2][26][18]
BAR4 bit 21MAIN[2][27][18]
BAR4 bit 22MAIN[2][26][19]
BAR4 bit 23MAIN[2][27][19]
BAR4 bit 24MAIN[2][26][20]
BAR4 bit 25MAIN[2][27][20]
BAR4 bit 26MAIN[2][26][21]
BAR4 bit 27MAIN[2][27][21]
BAR4 bit 28MAIN[2][26][22]
BAR4 bit 29MAIN[2][27][22]
BAR4 bit 30MAIN[2][26][23]
BAR4 bit 31MAIN[2][27][23]
BAR5 bit 0MAIN[2][26][24]
BAR5 bit 1MAIN[2][27][24]
BAR5 bit 2MAIN[2][26][25]
BAR5 bit 3MAIN[2][27][25]
BAR5 bit 4MAIN[2][26][26]
BAR5 bit 5MAIN[2][27][26]
BAR5 bit 6MAIN[2][26][27]
BAR5 bit 7MAIN[2][27][27]
BAR5 bit 8MAIN[2][26][28]
BAR5 bit 9MAIN[2][27][28]
BAR5 bit 10MAIN[2][26][29]
BAR5 bit 11MAIN[2][27][29]
BAR5 bit 12MAIN[2][26][30]
BAR5 bit 13MAIN[2][27][30]
BAR5 bit 14MAIN[2][26][31]
BAR5 bit 15MAIN[2][27][31]
BAR5 bit 16MAIN[2][26][32]
BAR5 bit 17MAIN[2][27][32]
BAR5 bit 18MAIN[2][26][33]
BAR5 bit 19MAIN[2][27][33]
BAR5 bit 20MAIN[2][26][34]
BAR5 bit 21MAIN[2][27][34]
BAR5 bit 22MAIN[2][26][35]
BAR5 bit 23MAIN[2][27][35]
BAR5 bit 24MAIN[2][26][36]
BAR5 bit 25MAIN[2][27][36]
BAR5 bit 26MAIN[2][26][37]
BAR5 bit 27MAIN[2][27][37]
BAR5 bit 28MAIN[2][26][38]
BAR5 bit 29MAIN[2][27][38]
BAR5 bit 30MAIN[2][26][39]
BAR5 bit 31MAIN[2][27][39]
CAPABILITIES_PTR bit 0MAIN[3][26][8]
CAPABILITIES_PTR bit 1MAIN[3][27][8]
CAPABILITIES_PTR bit 2MAIN[3][26][9]
CAPABILITIES_PTR bit 3MAIN[3][27][9]
CAPABILITIES_PTR bit 4MAIN[3][26][10]
CAPABILITIES_PTR bit 5MAIN[3][27][10]
CAPABILITIES_PTR bit 6MAIN[3][26][11]
CAPABILITIES_PTR bit 7MAIN[3][27][11]
CARDBUS_CIS_POINTER bit 0MAIN[3][26][16]
CARDBUS_CIS_POINTER bit 1MAIN[3][27][16]
CARDBUS_CIS_POINTER bit 2MAIN[3][26][17]
CARDBUS_CIS_POINTER bit 3MAIN[3][27][17]
CARDBUS_CIS_POINTER bit 4MAIN[3][26][18]
CARDBUS_CIS_POINTER bit 5MAIN[3][27][18]
CARDBUS_CIS_POINTER bit 6MAIN[3][26][19]
CARDBUS_CIS_POINTER bit 7MAIN[3][27][19]
CARDBUS_CIS_POINTER bit 8MAIN[3][26][20]
CARDBUS_CIS_POINTER bit 9MAIN[3][27][20]
CARDBUS_CIS_POINTER bit 10MAIN[3][26][21]
CARDBUS_CIS_POINTER bit 11MAIN[3][27][21]
CARDBUS_CIS_POINTER bit 12MAIN[3][26][22]
CARDBUS_CIS_POINTER bit 13MAIN[3][27][22]
CARDBUS_CIS_POINTER bit 14MAIN[3][26][23]
CARDBUS_CIS_POINTER bit 15MAIN[3][27][23]
CARDBUS_CIS_POINTER bit 16MAIN[3][26][24]
CARDBUS_CIS_POINTER bit 17MAIN[3][27][24]
CARDBUS_CIS_POINTER bit 18MAIN[3][26][25]
CARDBUS_CIS_POINTER bit 19MAIN[3][27][25]
CARDBUS_CIS_POINTER bit 20MAIN[3][26][26]
CARDBUS_CIS_POINTER bit 21MAIN[3][27][26]
CARDBUS_CIS_POINTER bit 22MAIN[3][26][27]
CARDBUS_CIS_POINTER bit 23MAIN[3][27][27]
CARDBUS_CIS_POINTER bit 24MAIN[3][26][28]
CARDBUS_CIS_POINTER bit 25MAIN[3][27][28]
CARDBUS_CIS_POINTER bit 26MAIN[3][26][29]
CARDBUS_CIS_POINTER bit 27MAIN[3][27][29]
CARDBUS_CIS_POINTER bit 28MAIN[3][26][30]
CARDBUS_CIS_POINTER bit 29MAIN[3][27][30]
CARDBUS_CIS_POINTER bit 30MAIN[3][26][31]
CARDBUS_CIS_POINTER bit 31MAIN[3][27][31]
CLASS_CODE bit 0MAIN[3][26][32]
CLASS_CODE bit 1MAIN[3][27][32]
CLASS_CODE bit 2MAIN[3][26][33]
CLASS_CODE bit 3MAIN[3][27][33]
CLASS_CODE bit 4MAIN[3][26][34]
CLASS_CODE bit 5MAIN[3][27][34]
CLASS_CODE bit 6MAIN[3][26][35]
CLASS_CODE bit 7MAIN[3][27][35]
CLASS_CODE bit 8MAIN[3][26][36]
CLASS_CODE bit 9MAIN[3][27][36]
CLASS_CODE bit 10MAIN[3][26][37]
CLASS_CODE bit 11MAIN[3][27][37]
CLASS_CODE bit 12MAIN[3][26][38]
CLASS_CODE bit 13MAIN[3][27][38]
CLASS_CODE bit 14MAIN[3][26][39]
CLASS_CODE bit 15MAIN[3][27][39]
CLASS_CODE bit 16MAIN[3][26][40]
CLASS_CODE bit 17MAIN[3][27][40]
CLASS_CODE bit 18MAIN[3][26][41]
CLASS_CODE bit 19MAIN[3][27][41]
CLASS_CODE bit 20MAIN[3][26][42]
CLASS_CODE bit 21MAIN[3][27][42]
CLASS_CODE bit 22MAIN[3][26][43]
CLASS_CODE bit 23MAIN[3][27][43]
CPL_TIMEOUT_RANGES_SUPPORTED bit 0MAIN[3][26][45]
CPL_TIMEOUT_RANGES_SUPPORTED bit 1MAIN[3][27][45]
CPL_TIMEOUT_RANGES_SUPPORTED bit 2MAIN[3][26][46]
CPL_TIMEOUT_RANGES_SUPPORTED bit 3MAIN[3][27][46]
CRM_MODULE_RSTS bit 0MAIN[12][27][11]
CRM_MODULE_RSTS bit 1MAIN[12][26][12]
CRM_MODULE_RSTS bit 2MAIN[12][27][12]
CRM_MODULE_RSTS bit 3MAIN[12][26][13]
CRM_MODULE_RSTS bit 4MAIN[12][27][13]
CRM_MODULE_RSTS bit 5MAIN[12][26][14]
CRM_MODULE_RSTS bit 6MAIN[12][27][14]
DEVICE_ID bit 0MAIN[4][26][16]
DEVICE_ID bit 1MAIN[4][27][16]
DEVICE_ID bit 2MAIN[4][26][17]
DEVICE_ID bit 3MAIN[4][27][17]
DEVICE_ID bit 4MAIN[4][26][18]
DEVICE_ID bit 5MAIN[4][27][18]
DEVICE_ID bit 6MAIN[4][26][19]
DEVICE_ID bit 7MAIN[4][27][19]
DEVICE_ID bit 8MAIN[4][26][20]
DEVICE_ID bit 9MAIN[4][27][20]
DEVICE_ID bit 10MAIN[4][26][21]
DEVICE_ID bit 11MAIN[4][27][21]
DEVICE_ID bit 12MAIN[4][26][22]
DEVICE_ID bit 13MAIN[4][27][22]
DEVICE_ID bit 14MAIN[4][26][23]
DEVICE_ID bit 15MAIN[4][27][23]
DEV_CAP_ENDPOINT_L0S_LATENCY bit 0MAIN[4][26][0]
DEV_CAP_ENDPOINT_L0S_LATENCY bit 1MAIN[4][27][0]
DEV_CAP_ENDPOINT_L0S_LATENCY bit 2MAIN[4][26][1]
DEV_CAP_ENDPOINT_L1_LATENCY bit 0MAIN[4][27][1]
DEV_CAP_ENDPOINT_L1_LATENCY bit 1MAIN[4][26][2]
DEV_CAP_ENDPOINT_L1_LATENCY bit 2MAIN[4][27][2]
DEV_CAP_MAX_PAYLOAD_SUPPORTED bit 0MAIN[4][26][4]
DEV_CAP_MAX_PAYLOAD_SUPPORTED bit 1MAIN[4][27][4]
DEV_CAP_MAX_PAYLOAD_SUPPORTED bit 2MAIN[4][26][5]
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT bit 0MAIN[4][27][5]
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT bit 1MAIN[4][26][6]
DEV_CAP_RSVD_14_12 bit 0MAIN[4][26][8]
DEV_CAP_RSVD_14_12 bit 1MAIN[4][27][8]
DEV_CAP_RSVD_14_12 bit 2MAIN[4][26][9]
DEV_CAP_RSVD_17_16 bit 0MAIN[4][27][9]
DEV_CAP_RSVD_17_16 bit 1MAIN[4][26][10]
DEV_CAP_RSVD_31_29 bit 0MAIN[4][27][10]
DEV_CAP_RSVD_31_29 bit 1MAIN[4][26][11]
DEV_CAP_RSVD_31_29 bit 2MAIN[4][27][11]
DNSTREAM_LINK_NUM bit 0
DNSTREAM_LINK_NUM bit 1
DNSTREAM_LINK_NUM bit 2
DNSTREAM_LINK_NUM bit 3
DNSTREAM_LINK_NUM bit 4
DNSTREAM_LINK_NUM bit 5
DNSTREAM_LINK_NUM bit 6
DNSTREAM_LINK_NUM bit 7
DSN_BASE_PTR bit 0MAIN[4][26][24]
DSN_BASE_PTR bit 1MAIN[4][27][24]
DSN_BASE_PTR bit 2MAIN[4][26][25]
DSN_BASE_PTR bit 3MAIN[4][27][25]
DSN_BASE_PTR bit 4MAIN[4][26][26]
DSN_BASE_PTR bit 5MAIN[4][27][26]
DSN_BASE_PTR bit 6MAIN[4][26][27]
DSN_BASE_PTR bit 7MAIN[4][27][27]
DSN_BASE_PTR bit 8MAIN[4][26][28]
DSN_BASE_PTR bit 9MAIN[4][27][28]
DSN_BASE_PTR bit 10MAIN[4][26][29]
DSN_BASE_PTR bit 11MAIN[4][27][29]
DSN_CAP_ID bit 0MAIN[4][26][32]
DSN_CAP_ID bit 1MAIN[4][27][32]
DSN_CAP_ID bit 2MAIN[4][26][33]
DSN_CAP_ID bit 3MAIN[4][27][33]
DSN_CAP_ID bit 4MAIN[4][26][34]
DSN_CAP_ID bit 5MAIN[4][27][34]
DSN_CAP_ID bit 6MAIN[4][26][35]
DSN_CAP_ID bit 7MAIN[4][27][35]
DSN_CAP_ID bit 8MAIN[4][26][36]
DSN_CAP_ID bit 9MAIN[4][27][36]
DSN_CAP_ID bit 10MAIN[4][26][37]
DSN_CAP_ID bit 11MAIN[4][27][37]
DSN_CAP_ID bit 12MAIN[4][26][38]
DSN_CAP_ID bit 13MAIN[4][27][38]
DSN_CAP_ID bit 14MAIN[4][26][39]
DSN_CAP_ID bit 15MAIN[4][27][39]
DSN_CAP_NEXTPTR bit 0MAIN[4][26][40]
DSN_CAP_NEXTPTR bit 1MAIN[4][27][40]
DSN_CAP_NEXTPTR bit 2MAIN[4][26][41]
DSN_CAP_NEXTPTR bit 3MAIN[4][27][41]
DSN_CAP_NEXTPTR bit 4MAIN[4][26][42]
DSN_CAP_NEXTPTR bit 5MAIN[4][27][42]
DSN_CAP_NEXTPTR bit 6MAIN[4][26][43]
DSN_CAP_NEXTPTR bit 7MAIN[4][27][43]
DSN_CAP_NEXTPTR bit 8MAIN[4][26][44]
DSN_CAP_NEXTPTR bit 9MAIN[4][27][44]
DSN_CAP_NEXTPTR bit 10MAIN[4][26][45]
DSN_CAP_NEXTPTR bit 11MAIN[4][27][45]
DSN_CAP_VERSION bit 0MAIN[5][26][0]
DSN_CAP_VERSION bit 1MAIN[5][27][0]
DSN_CAP_VERSION bit 2MAIN[5][26][1]
DSN_CAP_VERSION bit 3MAIN[5][27][1]
ENABLE_MSG_ROUTE bit 0MAIN[13][26][32]
ENABLE_MSG_ROUTE bit 1MAIN[13][27][32]
ENABLE_MSG_ROUTE bit 2MAIN[13][26][33]
ENABLE_MSG_ROUTE bit 3MAIN[13][27][33]
ENABLE_MSG_ROUTE bit 4MAIN[13][26][34]
ENABLE_MSG_ROUTE bit 5MAIN[13][27][34]
ENABLE_MSG_ROUTE bit 6MAIN[13][26][35]
ENABLE_MSG_ROUTE bit 7MAIN[13][27][35]
ENABLE_MSG_ROUTE bit 8MAIN[13][26][36]
ENABLE_MSG_ROUTE bit 9MAIN[13][27][36]
ENABLE_MSG_ROUTE bit 10MAIN[13][26][37]
EXPANSION_ROM bit 0MAIN[2][26][40]
EXPANSION_ROM bit 1MAIN[2][27][40]
EXPANSION_ROM bit 2MAIN[2][26][41]
EXPANSION_ROM bit 3MAIN[2][27][41]
EXPANSION_ROM bit 4MAIN[2][26][42]
EXPANSION_ROM bit 5MAIN[2][27][42]
EXPANSION_ROM bit 6MAIN[2][26][43]
EXPANSION_ROM bit 7MAIN[2][27][43]
EXPANSION_ROM bit 8MAIN[2][26][44]
EXPANSION_ROM bit 9MAIN[2][27][44]
EXPANSION_ROM bit 10MAIN[2][26][45]
EXPANSION_ROM bit 11MAIN[2][27][45]
EXPANSION_ROM bit 12MAIN[2][26][46]
EXPANSION_ROM bit 13MAIN[2][27][46]
EXPANSION_ROM bit 14MAIN[2][26][47]
EXPANSION_ROM bit 15MAIN[2][27][47]
EXPANSION_ROM bit 16MAIN[3][26][0]
EXPANSION_ROM bit 17MAIN[3][27][0]
EXPANSION_ROM bit 18MAIN[3][26][1]
EXPANSION_ROM bit 19MAIN[3][27][1]
EXPANSION_ROM bit 20MAIN[3][26][2]
EXPANSION_ROM bit 21MAIN[3][27][2]
EXPANSION_ROM bit 22MAIN[3][26][3]
EXPANSION_ROM bit 23MAIN[3][27][3]
EXPANSION_ROM bit 24MAIN[3][26][4]
EXPANSION_ROM bit 25MAIN[3][27][4]
EXPANSION_ROM bit 26MAIN[3][26][5]
EXPANSION_ROM bit 27MAIN[3][27][5]
EXPANSION_ROM bit 28MAIN[3][26][6]
EXPANSION_ROM bit 29MAIN[3][27][6]
EXPANSION_ROM bit 30MAIN[3][26][7]
EXPANSION_ROM bit 31MAIN[3][27][7]
EXT_CFG_CAP_PTR bit 0MAIN[5][26][2]
EXT_CFG_CAP_PTR bit 1MAIN[5][27][2]
EXT_CFG_CAP_PTR bit 2MAIN[5][26][3]
EXT_CFG_CAP_PTR bit 3MAIN[5][27][3]
EXT_CFG_CAP_PTR bit 4MAIN[5][26][4]
EXT_CFG_CAP_PTR bit 5MAIN[5][27][4]
EXT_CFG_XP_CAP_PTR bit 0MAIN[5][26][8]
EXT_CFG_XP_CAP_PTR bit 1MAIN[5][27][8]
EXT_CFG_XP_CAP_PTR bit 2MAIN[5][26][9]
EXT_CFG_XP_CAP_PTR bit 3MAIN[5][27][9]
EXT_CFG_XP_CAP_PTR bit 4MAIN[5][26][10]
EXT_CFG_XP_CAP_PTR bit 5MAIN[5][27][10]
EXT_CFG_XP_CAP_PTR bit 6MAIN[5][26][11]
EXT_CFG_XP_CAP_PTR bit 7MAIN[5][27][11]
EXT_CFG_XP_CAP_PTR bit 8MAIN[5][26][12]
EXT_CFG_XP_CAP_PTR bit 9MAIN[5][27][12]
HEADER_TYPE bit 0MAIN[5][26][16]
HEADER_TYPE bit 1MAIN[5][27][16]
HEADER_TYPE bit 2MAIN[5][26][17]
HEADER_TYPE bit 3MAIN[5][27][17]
HEADER_TYPE bit 4MAIN[5][26][18]
HEADER_TYPE bit 5MAIN[5][27][18]
HEADER_TYPE bit 6MAIN[5][26][19]
HEADER_TYPE bit 7MAIN[5][27][19]
INFER_EI bit 0MAIN[12][27][42]
INFER_EI bit 1MAIN[12][26][43]
INFER_EI bit 2MAIN[12][27][43]
INFER_EI bit 3MAIN[12][26][44]
INFER_EI bit 4MAIN[12][27][44]
INTERRUPT_PIN bit 0MAIN[5][26][20]
INTERRUPT_PIN bit 1MAIN[5][27][20]
INTERRUPT_PIN bit 2MAIN[5][26][21]
INTERRUPT_PIN bit 3MAIN[5][27][21]
INTERRUPT_PIN bit 4MAIN[5][26][22]
INTERRUPT_PIN bit 5MAIN[5][27][22]
INTERRUPT_PIN bit 6MAIN[5][26][23]
INTERRUPT_PIN bit 7MAIN[5][27][23]
LAST_CONFIG_DWORD bit 0MAIN[5][27][24]
LAST_CONFIG_DWORD bit 1MAIN[5][26][25]
LAST_CONFIG_DWORD bit 2MAIN[5][27][25]
LAST_CONFIG_DWORD bit 3MAIN[5][26][26]
LAST_CONFIG_DWORD bit 4MAIN[5][27][26]
LAST_CONFIG_DWORD bit 5MAIN[5][26][27]
LAST_CONFIG_DWORD bit 6MAIN[5][27][27]
LAST_CONFIG_DWORD bit 7MAIN[5][26][28]
LAST_CONFIG_DWORD bit 8MAIN[5][27][28]
LAST_CONFIG_DWORD bit 9MAIN[5][26][29]
LINK_CAP_ASPM_SUPPORT bit 0
LINK_CAP_ASPM_SUPPORT bit 1
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 bit 0
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 bit 1
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 bit 2
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 bit 0
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 bit 1
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 bit 2
LINK_CAP_L0S_EXIT_LATENCY_GEN1 bit 0
LINK_CAP_L0S_EXIT_LATENCY_GEN1 bit 1
LINK_CAP_L0S_EXIT_LATENCY_GEN1 bit 2
LINK_CAP_L0S_EXIT_LATENCY_GEN2 bit 0
LINK_CAP_L0S_EXIT_LATENCY_GEN2 bit 1
LINK_CAP_L0S_EXIT_LATENCY_GEN2 bit 2
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 bit 0
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 bit 1
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 bit 2
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 bit 0
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 bit 1
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 bit 2
LINK_CAP_L1_EXIT_LATENCY_GEN1 bit 0
LINK_CAP_L1_EXIT_LATENCY_GEN1 bit 1
LINK_CAP_L1_EXIT_LATENCY_GEN1 bit 2
LINK_CAP_L1_EXIT_LATENCY_GEN2 bit 0
LINK_CAP_L1_EXIT_LATENCY_GEN2 bit 1
LINK_CAP_L1_EXIT_LATENCY_GEN2 bit 2
LINK_CAP_MAX_LINK_SPEED bit 0
LINK_CAP_MAX_LINK_SPEED bit 1
LINK_CAP_MAX_LINK_SPEED bit 2
LINK_CAP_MAX_LINK_SPEED bit 3
LINK_CAP_MAX_LINK_WIDTH bit 0
LINK_CAP_MAX_LINK_WIDTH bit 1
LINK_CAP_MAX_LINK_WIDTH bit 2
LINK_CAP_MAX_LINK_WIDTH bit 3
LINK_CAP_MAX_LINK_WIDTH bit 4
LINK_CAP_MAX_LINK_WIDTH bit 5
LINK_CAP_RSVD_23_22 bit 0
LINK_CAP_RSVD_23_22 bit 1
LINK_CONTROL_RCB bit 0
LINK_CTRL2_TARGET_LINK_SPEED bit 0
LINK_CTRL2_TARGET_LINK_SPEED bit 1
LINK_CTRL2_TARGET_LINK_SPEED bit 2
LINK_CTRL2_TARGET_LINK_SPEED bit 3
LL_ACK_TIMEOUT bit 0MAIN[12][26][16]
LL_ACK_TIMEOUT bit 1MAIN[12][27][16]
LL_ACK_TIMEOUT bit 2MAIN[12][26][17]
LL_ACK_TIMEOUT bit 3MAIN[12][27][17]
LL_ACK_TIMEOUT bit 4MAIN[12][26][18]
LL_ACK_TIMEOUT bit 5MAIN[12][27][18]
LL_ACK_TIMEOUT bit 6MAIN[12][26][19]
LL_ACK_TIMEOUT bit 7MAIN[12][27][19]
LL_ACK_TIMEOUT bit 8MAIN[12][26][20]
LL_ACK_TIMEOUT bit 9MAIN[12][27][20]
LL_ACK_TIMEOUT bit 10MAIN[12][26][21]
LL_ACK_TIMEOUT bit 11MAIN[12][27][21]
LL_ACK_TIMEOUT bit 12MAIN[12][26][22]
LL_ACK_TIMEOUT bit 13MAIN[12][27][22]
LL_ACK_TIMEOUT bit 14MAIN[12][26][23]
LL_ACK_TIMEOUT_FUNC bit 0MAIN[12][26][24]
LL_ACK_TIMEOUT_FUNC bit 1MAIN[12][27][24]
LL_REPLAY_TIMEOUT bit 0MAIN[12][26][32]
LL_REPLAY_TIMEOUT bit 1MAIN[12][27][32]
LL_REPLAY_TIMEOUT bit 2MAIN[12][26][33]
LL_REPLAY_TIMEOUT bit 3MAIN[12][27][33]
LL_REPLAY_TIMEOUT bit 4MAIN[12][26][34]
LL_REPLAY_TIMEOUT bit 5MAIN[12][27][34]
LL_REPLAY_TIMEOUT bit 6MAIN[12][26][35]
LL_REPLAY_TIMEOUT bit 7MAIN[12][27][35]
LL_REPLAY_TIMEOUT bit 8MAIN[12][26][36]
LL_REPLAY_TIMEOUT bit 9MAIN[12][27][36]
LL_REPLAY_TIMEOUT bit 10MAIN[12][26][37]
LL_REPLAY_TIMEOUT bit 11MAIN[12][27][37]
LL_REPLAY_TIMEOUT bit 12MAIN[12][26][38]
LL_REPLAY_TIMEOUT bit 13MAIN[12][27][38]
LL_REPLAY_TIMEOUT bit 14MAIN[12][26][39]
LL_REPLAY_TIMEOUT_FUNC bit 0MAIN[12][26][40]
LL_REPLAY_TIMEOUT_FUNC bit 1MAIN[12][27][40]
LTSSM_MAX_LINK_WIDTH bit 0
LTSSM_MAX_LINK_WIDTH bit 1
LTSSM_MAX_LINK_WIDTH bit 2
LTSSM_MAX_LINK_WIDTH bit 3
LTSSM_MAX_LINK_WIDTH bit 4
LTSSM_MAX_LINK_WIDTH bit 5
MSIX_BASE_PTR bit 0MAIN[6][26][32]
MSIX_BASE_PTR bit 1MAIN[6][27][32]
MSIX_BASE_PTR bit 2MAIN[6][26][33]
MSIX_BASE_PTR bit 3MAIN[6][27][33]
MSIX_BASE_PTR bit 4MAIN[6][26][34]
MSIX_BASE_PTR bit 5MAIN[6][27][34]
MSIX_BASE_PTR bit 6MAIN[6][26][35]
MSIX_BASE_PTR bit 7MAIN[6][27][35]
MSIX_CAP_ID bit 0MAIN[6][26][36]
MSIX_CAP_ID bit 1MAIN[6][27][36]
MSIX_CAP_ID bit 2MAIN[6][26][37]
MSIX_CAP_ID bit 3MAIN[6][27][37]
MSIX_CAP_ID bit 4MAIN[6][26][38]
MSIX_CAP_ID bit 5MAIN[6][27][38]
MSIX_CAP_ID bit 6MAIN[6][26][39]
MSIX_CAP_ID bit 7MAIN[6][27][39]
MSIX_CAP_NEXTPTR bit 0MAIN[6][26][40]
MSIX_CAP_NEXTPTR bit 1MAIN[6][27][40]
MSIX_CAP_NEXTPTR bit 2MAIN[6][26][41]
MSIX_CAP_NEXTPTR bit 3MAIN[6][27][41]
MSIX_CAP_NEXTPTR bit 4MAIN[6][26][42]
MSIX_CAP_NEXTPTR bit 5MAIN[6][27][42]
MSIX_CAP_NEXTPTR bit 6MAIN[6][26][43]
MSIX_CAP_NEXTPTR bit 7MAIN[6][27][43]
MSIX_CAP_PBA_BIR bit 0MAIN[6][27][44]
MSIX_CAP_PBA_BIR bit 1MAIN[6][26][45]
MSIX_CAP_PBA_BIR bit 2MAIN[6][27][45]
MSIX_CAP_PBA_OFFSET bit 0MAIN[7][26][0]
MSIX_CAP_PBA_OFFSET bit 1MAIN[7][27][0]
MSIX_CAP_PBA_OFFSET bit 2MAIN[7][26][1]
MSIX_CAP_PBA_OFFSET bit 3MAIN[7][27][1]
MSIX_CAP_PBA_OFFSET bit 4MAIN[7][26][2]
MSIX_CAP_PBA_OFFSET bit 5MAIN[7][27][2]
MSIX_CAP_PBA_OFFSET bit 6MAIN[7][26][3]
MSIX_CAP_PBA_OFFSET bit 7MAIN[7][27][3]
MSIX_CAP_PBA_OFFSET bit 8MAIN[7][26][4]
MSIX_CAP_PBA_OFFSET bit 9MAIN[7][27][4]
MSIX_CAP_PBA_OFFSET bit 10MAIN[7][26][5]
MSIX_CAP_PBA_OFFSET bit 11MAIN[7][27][5]
MSIX_CAP_PBA_OFFSET bit 12MAIN[7][26][6]
MSIX_CAP_PBA_OFFSET bit 13MAIN[7][27][6]
MSIX_CAP_PBA_OFFSET bit 14MAIN[7][26][7]
MSIX_CAP_PBA_OFFSET bit 15MAIN[7][27][7]
MSIX_CAP_PBA_OFFSET bit 16MAIN[7][26][8]
MSIX_CAP_PBA_OFFSET bit 17MAIN[7][27][8]
MSIX_CAP_PBA_OFFSET bit 18MAIN[7][26][9]
MSIX_CAP_PBA_OFFSET bit 19MAIN[7][27][9]
MSIX_CAP_PBA_OFFSET bit 20MAIN[7][26][10]
MSIX_CAP_PBA_OFFSET bit 21MAIN[7][27][10]
MSIX_CAP_PBA_OFFSET bit 22MAIN[7][26][11]
MSIX_CAP_PBA_OFFSET bit 23MAIN[7][27][11]
MSIX_CAP_PBA_OFFSET bit 24MAIN[7][26][12]
MSIX_CAP_PBA_OFFSET bit 25MAIN[7][27][12]
MSIX_CAP_PBA_OFFSET bit 26MAIN[7][26][13]
MSIX_CAP_PBA_OFFSET bit 27MAIN[7][27][13]
MSIX_CAP_PBA_OFFSET bit 28MAIN[7][26][14]
MSIX_CAP_TABLE_BIR bit 0MAIN[7][27][14]
MSIX_CAP_TABLE_BIR bit 1MAIN[7][26][15]
MSIX_CAP_TABLE_BIR bit 2MAIN[7][27][15]
MSIX_CAP_TABLE_OFFSET bit 0MAIN[7][26][16]
MSIX_CAP_TABLE_OFFSET bit 1MAIN[7][27][16]
MSIX_CAP_TABLE_OFFSET bit 2MAIN[7][26][17]
MSIX_CAP_TABLE_OFFSET bit 3MAIN[7][27][17]
MSIX_CAP_TABLE_OFFSET bit 4MAIN[7][26][18]
MSIX_CAP_TABLE_OFFSET bit 5MAIN[7][27][18]
MSIX_CAP_TABLE_OFFSET bit 6MAIN[7][26][19]
MSIX_CAP_TABLE_OFFSET bit 7MAIN[7][27][19]
MSIX_CAP_TABLE_OFFSET bit 8MAIN[7][26][20]
MSIX_CAP_TABLE_OFFSET bit 9MAIN[7][27][20]
MSIX_CAP_TABLE_OFFSET bit 10MAIN[7][26][21]
MSIX_CAP_TABLE_OFFSET bit 11MAIN[7][27][21]
MSIX_CAP_TABLE_OFFSET bit 12MAIN[7][26][22]
MSIX_CAP_TABLE_OFFSET bit 13MAIN[7][27][22]
MSIX_CAP_TABLE_OFFSET bit 14MAIN[7][26][23]
MSIX_CAP_TABLE_OFFSET bit 15MAIN[7][27][23]
MSIX_CAP_TABLE_OFFSET bit 16MAIN[7][26][24]
MSIX_CAP_TABLE_OFFSET bit 17MAIN[7][27][24]
MSIX_CAP_TABLE_OFFSET bit 18MAIN[7][26][25]
MSIX_CAP_TABLE_OFFSET bit 19MAIN[7][27][25]
MSIX_CAP_TABLE_OFFSET bit 20MAIN[7][26][26]
MSIX_CAP_TABLE_OFFSET bit 21MAIN[7][27][26]
MSIX_CAP_TABLE_OFFSET bit 22MAIN[7][26][27]
MSIX_CAP_TABLE_OFFSET bit 23MAIN[7][27][27]
MSIX_CAP_TABLE_OFFSET bit 24MAIN[7][26][28]
MSIX_CAP_TABLE_OFFSET bit 25MAIN[7][27][28]
MSIX_CAP_TABLE_OFFSET bit 26MAIN[7][26][29]
MSIX_CAP_TABLE_OFFSET bit 27MAIN[7][27][29]
MSIX_CAP_TABLE_OFFSET bit 28MAIN[7][26][30]
MSIX_CAP_TABLE_SIZE bit 0MAIN[7][26][32]
MSIX_CAP_TABLE_SIZE bit 1MAIN[7][27][32]
MSIX_CAP_TABLE_SIZE bit 2MAIN[7][26][33]
MSIX_CAP_TABLE_SIZE bit 3MAIN[7][27][33]
MSIX_CAP_TABLE_SIZE bit 4MAIN[7][26][34]
MSIX_CAP_TABLE_SIZE bit 5MAIN[7][27][34]
MSIX_CAP_TABLE_SIZE bit 6MAIN[7][26][35]
MSIX_CAP_TABLE_SIZE bit 7MAIN[7][27][35]
MSIX_CAP_TABLE_SIZE bit 8MAIN[7][26][36]
MSIX_CAP_TABLE_SIZE bit 9MAIN[7][27][36]
MSIX_CAP_TABLE_SIZE bit 10MAIN[7][26][37]
MSI_BASE_PTR bit 0MAIN[6][26][8]
MSI_BASE_PTR bit 1MAIN[6][27][8]
MSI_BASE_PTR bit 2MAIN[6][26][9]
MSI_BASE_PTR bit 3MAIN[6][27][9]
MSI_BASE_PTR bit 4MAIN[6][26][10]
MSI_BASE_PTR bit 5MAIN[6][27][10]
MSI_BASE_PTR bit 6MAIN[6][26][11]
MSI_BASE_PTR bit 7MAIN[6][27][11]
MSI_CAP_ID bit 0MAIN[6][26][16]
MSI_CAP_ID bit 1MAIN[6][27][16]
MSI_CAP_ID bit 2MAIN[6][26][17]
MSI_CAP_ID bit 3MAIN[6][27][17]
MSI_CAP_ID bit 4MAIN[6][26][18]
MSI_CAP_ID bit 5MAIN[6][27][18]
MSI_CAP_ID bit 6MAIN[6][26][19]
MSI_CAP_ID bit 7MAIN[6][27][19]
MSI_CAP_MULTIMSGCAP bit 0MAIN[6][27][20]
MSI_CAP_MULTIMSGCAP bit 1MAIN[6][26][21]
MSI_CAP_MULTIMSGCAP bit 2MAIN[6][27][21]
MSI_CAP_MULTIMSG_EXTENSION bit 0MAIN[6][26][20]
MSI_CAP_NEXTPTR bit 0MAIN[6][26][24]
MSI_CAP_NEXTPTR bit 1MAIN[6][27][24]
MSI_CAP_NEXTPTR bit 2MAIN[6][26][25]
MSI_CAP_NEXTPTR bit 3MAIN[6][27][25]
MSI_CAP_NEXTPTR bit 4MAIN[6][26][26]
MSI_CAP_NEXTPTR bit 5MAIN[6][27][26]
MSI_CAP_NEXTPTR bit 6MAIN[6][26][27]
MSI_CAP_NEXTPTR bit 7MAIN[6][27][27]
PCIE_BASE_PTR bit 0MAIN[7][26][40]
PCIE_BASE_PTR bit 1MAIN[7][27][40]
PCIE_BASE_PTR bit 2MAIN[7][26][41]
PCIE_BASE_PTR bit 3MAIN[7][27][41]
PCIE_BASE_PTR bit 4MAIN[7][26][42]
PCIE_BASE_PTR bit 5MAIN[7][27][42]
PCIE_BASE_PTR bit 6MAIN[7][26][43]
PCIE_BASE_PTR bit 7MAIN[7][27][43]
PCIE_CAP_CAPABILITY_ID bit 0MAIN[7][26][44]
PCIE_CAP_CAPABILITY_ID bit 1MAIN[7][27][44]
PCIE_CAP_CAPABILITY_ID bit 2MAIN[7][26][45]
PCIE_CAP_CAPABILITY_ID bit 3MAIN[7][27][45]
PCIE_CAP_CAPABILITY_ID bit 4MAIN[7][26][46]
PCIE_CAP_CAPABILITY_ID bit 5MAIN[7][27][46]
PCIE_CAP_CAPABILITY_ID bit 6MAIN[7][26][47]
PCIE_CAP_CAPABILITY_ID bit 7MAIN[7][27][47]
PCIE_CAP_CAPABILITY_VERSION bit 0MAIN[8][26][0]
PCIE_CAP_CAPABILITY_VERSION bit 1MAIN[8][27][0]
PCIE_CAP_CAPABILITY_VERSION bit 2MAIN[8][26][1]
PCIE_CAP_CAPABILITY_VERSION bit 3MAIN[8][27][1]
PCIE_CAP_DEVICE_PORT_TYPE bit 0MAIN[8][26][2]
PCIE_CAP_DEVICE_PORT_TYPE bit 1MAIN[8][27][2]
PCIE_CAP_DEVICE_PORT_TYPE bit 2MAIN[8][26][3]
PCIE_CAP_DEVICE_PORT_TYPE bit 3MAIN[8][27][3]
PCIE_CAP_INT_MSG_NUM bit 0MAIN[8][26][4]
PCIE_CAP_INT_MSG_NUM bit 1MAIN[8][27][4]
PCIE_CAP_INT_MSG_NUM bit 2MAIN[8][26][5]
PCIE_CAP_INT_MSG_NUM bit 3MAIN[8][27][5]
PCIE_CAP_INT_MSG_NUM bit 4MAIN[8][26][6]
PCIE_CAP_NEXTPTR bit 0MAIN[8][26][8]
PCIE_CAP_NEXTPTR bit 1MAIN[8][27][8]
PCIE_CAP_NEXTPTR bit 2MAIN[8][26][9]
PCIE_CAP_NEXTPTR bit 3MAIN[8][27][9]
PCIE_CAP_NEXTPTR bit 4MAIN[8][26][10]
PCIE_CAP_NEXTPTR bit 5MAIN[8][27][10]
PCIE_CAP_NEXTPTR bit 6MAIN[8][26][11]
PCIE_CAP_NEXTPTR bit 7MAIN[8][27][11]
PCIE_CAP_RSVD_15_14 bit 0MAIN[8][27][12]
PCIE_CAP_RSVD_15_14 bit 1MAIN[8][26][13]
PGL0_LANE bit 0MAIN[14][26][40]
PGL0_LANE bit 1MAIN[14][27][40]
PGL0_LANE bit 2MAIN[14][26][41]
PGL1_LANE bit 0MAIN[14][27][41]
PGL1_LANE bit 1MAIN[14][26][42]
PGL1_LANE bit 2MAIN[14][27][42]
PGL2_LANE bit 0MAIN[14][26][43]
PGL2_LANE bit 1MAIN[14][27][43]
PGL2_LANE bit 2MAIN[14][26][44]
PGL3_LANE bit 0MAIN[14][27][44]
PGL3_LANE bit 1MAIN[14][26][45]
PGL3_LANE bit 2MAIN[14][27][45]
PGL4_LANE bit 0MAIN[14][26][46]
PGL4_LANE bit 1MAIN[14][27][46]
PGL4_LANE bit 2MAIN[14][26][47]
PGL5_LANE bit 0MAIN[15][26][0]
PGL5_LANE bit 1MAIN[15][27][0]
PGL5_LANE bit 2MAIN[15][26][1]
PGL6_LANE bit 0MAIN[15][27][1]
PGL6_LANE bit 1MAIN[15][26][2]
PGL6_LANE bit 2MAIN[15][27][2]
PGL7_LANE bit 0MAIN[15][26][3]
PGL7_LANE bit 1MAIN[15][27][3]
PGL7_LANE bit 2MAIN[15][26][4]
PL_AUTO_CONFIG bit 0MAIN[13][27][20]
PL_AUTO_CONFIG bit 1MAIN[13][26][21]
PL_AUTO_CONFIG bit 2MAIN[13][27][21]
PM_BASE_PTR bit 0MAIN[8][26][16]
PM_BASE_PTR bit 1MAIN[8][27][16]
PM_BASE_PTR bit 2MAIN[8][26][17]
PM_BASE_PTR bit 3MAIN[8][27][17]
PM_BASE_PTR bit 4MAIN[8][26][18]
PM_BASE_PTR bit 5MAIN[8][27][18]
PM_BASE_PTR bit 6MAIN[8][26][19]
PM_BASE_PTR bit 7MAIN[8][27][19]
PM_CAP_AUXCURRENT bit 0MAIN[8][26][20]
PM_CAP_AUXCURRENT bit 1MAIN[8][27][20]
PM_CAP_AUXCURRENT bit 2MAIN[8][26][21]
PM_CAP_ID bit 0MAIN[8][26][24]
PM_CAP_ID bit 1MAIN[8][27][24]
PM_CAP_ID bit 2MAIN[8][26][25]
PM_CAP_ID bit 3MAIN[8][27][25]
PM_CAP_ID bit 4MAIN[8][26][26]
PM_CAP_ID bit 5MAIN[8][27][26]
PM_CAP_ID bit 6MAIN[8][26][27]
PM_CAP_ID bit 7MAIN[8][27][27]
PM_CAP_NEXTPTR bit 0MAIN[8][26][28]
PM_CAP_NEXTPTR bit 1MAIN[8][27][28]
PM_CAP_NEXTPTR bit 2MAIN[8][26][29]
PM_CAP_NEXTPTR bit 3MAIN[8][27][29]
PM_CAP_NEXTPTR bit 4MAIN[8][26][30]
PM_CAP_NEXTPTR bit 5MAIN[8][27][30]
PM_CAP_NEXTPTR bit 6MAIN[8][26][31]
PM_CAP_NEXTPTR bit 7MAIN[8][27][31]
PM_CAP_PMESUPPORT bit 0MAIN[8][26][33]
PM_CAP_PMESUPPORT bit 1MAIN[8][27][33]
PM_CAP_PMESUPPORT bit 2MAIN[8][26][34]
PM_CAP_PMESUPPORT bit 3MAIN[8][27][34]
PM_CAP_PMESUPPORT bit 4MAIN[8][26][35]
PM_CAP_RSVD_04 bit 0MAIN[8][27][35]
PM_CAP_VERSION bit 0MAIN[8][26][36]
PM_CAP_VERSION bit 1MAIN[8][27][36]
PM_CAP_VERSION bit 2MAIN[8][26][37]
PM_DATA0 bit 0MAIN[9][26][0]
PM_DATA0 bit 1MAIN[9][27][0]
PM_DATA0 bit 2MAIN[9][26][1]
PM_DATA0 bit 3MAIN[9][27][1]
PM_DATA0 bit 4MAIN[9][26][2]
PM_DATA0 bit 5MAIN[9][27][2]
PM_DATA0 bit 6MAIN[9][26][3]
PM_DATA0 bit 7MAIN[9][27][3]
PM_DATA1 bit 0MAIN[9][26][4]
PM_DATA1 bit 1MAIN[9][27][4]
PM_DATA1 bit 2MAIN[9][26][5]
PM_DATA1 bit 3MAIN[9][27][5]
PM_DATA1 bit 4MAIN[9][26][6]
PM_DATA1 bit 5MAIN[9][27][6]
PM_DATA1 bit 6MAIN[9][26][7]
PM_DATA1 bit 7MAIN[9][27][7]
PM_DATA2 bit 0MAIN[9][26][8]
PM_DATA2 bit 1MAIN[9][27][8]
PM_DATA2 bit 2MAIN[9][26][9]
PM_DATA2 bit 3MAIN[9][27][9]
PM_DATA2 bit 4MAIN[9][26][10]
PM_DATA2 bit 5MAIN[9][27][10]
PM_DATA2 bit 6MAIN[9][26][11]
PM_DATA2 bit 7MAIN[9][27][11]
PM_DATA3 bit 0MAIN[9][26][12]
PM_DATA3 bit 1MAIN[9][27][12]
PM_DATA3 bit 2MAIN[9][26][13]
PM_DATA3 bit 3MAIN[9][27][13]
PM_DATA3 bit 4MAIN[9][26][14]
PM_DATA3 bit 5MAIN[9][27][14]
PM_DATA3 bit 6MAIN[9][26][15]
PM_DATA3 bit 7MAIN[9][27][15]
PM_DATA4 bit 0MAIN[9][26][16]
PM_DATA4 bit 1MAIN[9][27][16]
PM_DATA4 bit 2MAIN[9][26][17]
PM_DATA4 bit 3MAIN[9][27][17]
PM_DATA4 bit 4MAIN[9][26][18]
PM_DATA4 bit 5MAIN[9][27][18]
PM_DATA4 bit 6MAIN[9][26][19]
PM_DATA4 bit 7MAIN[9][27][19]
PM_DATA5 bit 0MAIN[9][26][20]
PM_DATA5 bit 1MAIN[9][27][20]
PM_DATA5 bit 2MAIN[9][26][21]
PM_DATA5 bit 3MAIN[9][27][21]
PM_DATA5 bit 4MAIN[9][26][22]
PM_DATA5 bit 5MAIN[9][27][22]
PM_DATA5 bit 6MAIN[9][26][23]
PM_DATA5 bit 7MAIN[9][27][23]
PM_DATA6 bit 0MAIN[9][26][24]
PM_DATA6 bit 1MAIN[9][27][24]
PM_DATA6 bit 2MAIN[9][26][25]
PM_DATA6 bit 3MAIN[9][27][25]
PM_DATA6 bit 4MAIN[9][26][26]
PM_DATA6 bit 5MAIN[9][27][26]
PM_DATA6 bit 6MAIN[9][26][27]
PM_DATA6 bit 7MAIN[9][27][27]
PM_DATA7 bit 0MAIN[9][26][28]
PM_DATA7 bit 1MAIN[9][27][28]
PM_DATA7 bit 2MAIN[9][26][29]
PM_DATA7 bit 3MAIN[9][27][29]
PM_DATA7 bit 4MAIN[9][26][30]
PM_DATA7 bit 5MAIN[9][27][30]
PM_DATA7 bit 6MAIN[9][26][31]
PM_DATA7 bit 7MAIN[9][27][31]
PM_DATA_SCALE0 bit 0MAIN[8][26][39]
PM_DATA_SCALE0 bit 1MAIN[8][27][39]
PM_DATA_SCALE1 bit 0MAIN[8][26][40]
PM_DATA_SCALE1 bit 1MAIN[8][27][40]
PM_DATA_SCALE2 bit 0MAIN[8][26][41]
PM_DATA_SCALE2 bit 1MAIN[8][27][41]
PM_DATA_SCALE3 bit 0MAIN[8][26][42]
PM_DATA_SCALE3 bit 1MAIN[8][27][42]
PM_DATA_SCALE4 bit 0MAIN[8][26][43]
PM_DATA_SCALE4 bit 1MAIN[8][27][43]
PM_DATA_SCALE5 bit 0MAIN[8][26][44]
PM_DATA_SCALE5 bit 1MAIN[8][27][44]
PM_DATA_SCALE6 bit 0MAIN[8][26][45]
PM_DATA_SCALE6 bit 1MAIN[8][27][45]
PM_DATA_SCALE7 bit 0MAIN[8][26][46]
PM_DATA_SCALE7 bit 1MAIN[8][27][46]
RECRC_CHK bit 0MAIN[14][26][38]
RECRC_CHK bit 1MAIN[14][27][38]
REVISION_ID bit 0MAIN[9][26][32]
REVISION_ID bit 1MAIN[9][27][32]
REVISION_ID bit 2MAIN[9][26][33]
REVISION_ID bit 3MAIN[9][27][33]
REVISION_ID bit 4MAIN[9][26][34]
REVISION_ID bit 5MAIN[9][27][34]
REVISION_ID bit 6MAIN[9][26][35]
REVISION_ID bit 7MAIN[9][27][35]
SLOT_CAP_PHYSICAL_SLOT_NUM bit 0MAIN[9][27][40]
SLOT_CAP_PHYSICAL_SLOT_NUM bit 1MAIN[9][26][41]
SLOT_CAP_PHYSICAL_SLOT_NUM bit 2MAIN[9][27][41]
SLOT_CAP_PHYSICAL_SLOT_NUM bit 3MAIN[9][26][42]
SLOT_CAP_PHYSICAL_SLOT_NUM bit 4MAIN[9][27][42]
SLOT_CAP_PHYSICAL_SLOT_NUM bit 5MAIN[9][26][43]
SLOT_CAP_PHYSICAL_SLOT_NUM bit 6MAIN[9][27][43]
SLOT_CAP_PHYSICAL_SLOT_NUM bit 7MAIN[9][26][44]
SLOT_CAP_PHYSICAL_SLOT_NUM bit 8MAIN[9][27][44]
SLOT_CAP_PHYSICAL_SLOT_NUM bit 9MAIN[9][26][45]
SLOT_CAP_PHYSICAL_SLOT_NUM bit 10MAIN[9][27][45]
SLOT_CAP_PHYSICAL_SLOT_NUM bit 11MAIN[9][26][46]
SLOT_CAP_PHYSICAL_SLOT_NUM bit 12MAIN[9][27][46]
SLOT_CAP_SLOT_POWER_LIMIT_SCALE bit 0MAIN[10][26][0]
SLOT_CAP_SLOT_POWER_LIMIT_SCALE bit 1MAIN[10][27][0]
SLOT_CAP_SLOT_POWER_LIMIT_VALUE bit 0MAIN[10][26][1]
SLOT_CAP_SLOT_POWER_LIMIT_VALUE bit 1MAIN[10][27][1]
SLOT_CAP_SLOT_POWER_LIMIT_VALUE bit 2MAIN[10][26][2]
SLOT_CAP_SLOT_POWER_LIMIT_VALUE bit 3MAIN[10][27][2]
SLOT_CAP_SLOT_POWER_LIMIT_VALUE bit 4MAIN[10][26][3]
SLOT_CAP_SLOT_POWER_LIMIT_VALUE bit 5MAIN[10][27][3]
SLOT_CAP_SLOT_POWER_LIMIT_VALUE bit 6MAIN[10][26][4]
SLOT_CAP_SLOT_POWER_LIMIT_VALUE bit 7MAIN[10][27][4]
SPARE_BIT0 bit 0MAIN[15][26][5]
SPARE_BIT1 bit 0MAIN[15][27][5]
SPARE_BIT2 bit 0MAIN[15][26][6]
SPARE_BIT3 bit 0MAIN[15][27][6]
SPARE_BIT4 bit 0MAIN[15][26][7]
SPARE_BIT5 bit 0MAIN[15][27][7]
SPARE_BIT6 bit 0MAIN[15][26][8]
SPARE_BIT7 bit 0MAIN[15][27][8]
SPARE_BIT8 bit 0MAIN[15][26][9]
SPARE_BYTE0 bit 0MAIN[15][27][9]
SPARE_BYTE0 bit 1MAIN[15][26][10]
SPARE_BYTE0 bit 2MAIN[15][27][10]
SPARE_BYTE0 bit 3MAIN[15][26][11]
SPARE_BYTE0 bit 4MAIN[15][27][11]
SPARE_BYTE0 bit 5MAIN[15][26][12]
SPARE_BYTE0 bit 6MAIN[15][27][12]
SPARE_BYTE0 bit 7MAIN[15][26][13]
SPARE_BYTE1 bit 0MAIN[15][26][16]
SPARE_BYTE1 bit 1MAIN[15][27][16]
SPARE_BYTE1 bit 2MAIN[15][26][17]
SPARE_BYTE1 bit 3MAIN[15][27][17]
SPARE_BYTE1 bit 4MAIN[15][26][18]
SPARE_BYTE1 bit 5MAIN[15][27][18]
SPARE_BYTE1 bit 6MAIN[15][26][19]
SPARE_BYTE1 bit 7MAIN[15][27][19]
SPARE_BYTE2 bit 0MAIN[15][26][20]
SPARE_BYTE2 bit 1MAIN[15][27][20]
SPARE_BYTE2 bit 2MAIN[15][26][21]
SPARE_BYTE2 bit 3MAIN[15][27][21]
SPARE_BYTE2 bit 4MAIN[15][26][22]
SPARE_BYTE2 bit 5MAIN[15][27][22]
SPARE_BYTE2 bit 6MAIN[15][26][23]
SPARE_BYTE2 bit 7MAIN[15][27][23]
SPARE_BYTE3 bit 0MAIN[15][26][24]
SPARE_BYTE3 bit 1MAIN[15][27][24]
SPARE_BYTE3 bit 2MAIN[15][26][25]
SPARE_BYTE3 bit 3MAIN[15][27][25]
SPARE_BYTE3 bit 4MAIN[15][26][26]
SPARE_BYTE3 bit 5MAIN[15][27][26]
SPARE_BYTE3 bit 6MAIN[15][26][27]
SPARE_BYTE3 bit 7MAIN[15][27][27]
SPARE_WORD0 bit 0MAIN[15][26][32]
SPARE_WORD0 bit 1MAIN[15][27][32]
SPARE_WORD0 bit 2MAIN[15][26][33]
SPARE_WORD0 bit 3MAIN[15][27][33]
SPARE_WORD0 bit 4MAIN[15][26][34]
SPARE_WORD0 bit 5MAIN[15][27][34]
SPARE_WORD0 bit 6MAIN[15][26][35]
SPARE_WORD0 bit 7MAIN[15][27][35]
SPARE_WORD0 bit 8MAIN[15][26][36]
SPARE_WORD0 bit 9MAIN[15][27][36]
SPARE_WORD0 bit 10MAIN[15][26][37]
SPARE_WORD0 bit 11MAIN[15][27][37]
SPARE_WORD0 bit 12MAIN[15][26][38]
SPARE_WORD0 bit 13MAIN[15][27][38]
SPARE_WORD0 bit 14MAIN[15][26][39]
SPARE_WORD0 bit 15MAIN[15][27][39]
SPARE_WORD0 bit 16MAIN[15][26][40]
SPARE_WORD0 bit 17MAIN[15][27][40]
SPARE_WORD0 bit 18MAIN[15][26][41]
SPARE_WORD0 bit 19MAIN[15][27][41]
SPARE_WORD0 bit 20MAIN[15][26][42]
SPARE_WORD0 bit 21MAIN[15][27][42]
SPARE_WORD0 bit 22MAIN[15][26][43]
SPARE_WORD0 bit 23MAIN[15][27][43]
SPARE_WORD0 bit 24MAIN[15][26][44]
SPARE_WORD0 bit 25MAIN[15][27][44]
SPARE_WORD0 bit 26MAIN[15][26][45]
SPARE_WORD0 bit 27MAIN[15][27][45]
SPARE_WORD0 bit 28MAIN[15][26][46]
SPARE_WORD0 bit 29MAIN[15][27][46]
SPARE_WORD0 bit 30MAIN[15][26][47]
SPARE_WORD0 bit 31MAIN[15][27][47]
SPARE_WORD1 bit 0MAIN[16][26][0]
SPARE_WORD1 bit 1MAIN[16][27][0]
SPARE_WORD1 bit 2MAIN[16][26][1]
SPARE_WORD1 bit 3MAIN[16][27][1]
SPARE_WORD1 bit 4MAIN[16][26][2]
SPARE_WORD1 bit 5MAIN[16][27][2]
SPARE_WORD1 bit 6MAIN[16][26][3]
SPARE_WORD1 bit 7MAIN[16][27][3]
SPARE_WORD1 bit 8MAIN[16][26][4]
SPARE_WORD1 bit 9MAIN[16][27][4]
SPARE_WORD1 bit 10MAIN[16][26][5]
SPARE_WORD1 bit 11MAIN[16][27][5]
SPARE_WORD1 bit 12MAIN[16][26][6]
SPARE_WORD1 bit 13MAIN[16][27][6]
SPARE_WORD1 bit 14MAIN[16][26][7]
SPARE_WORD1 bit 15MAIN[16][27][7]
SPARE_WORD1 bit 16MAIN[16][26][8]
SPARE_WORD1 bit 17MAIN[16][27][8]
SPARE_WORD1 bit 18MAIN[16][26][9]
SPARE_WORD1 bit 19MAIN[16][27][9]
SPARE_WORD1 bit 20MAIN[16][26][10]
SPARE_WORD1 bit 21MAIN[16][27][10]
SPARE_WORD1 bit 22MAIN[16][26][11]
SPARE_WORD1 bit 23MAIN[16][27][11]
SPARE_WORD1 bit 24MAIN[16][26][12]
SPARE_WORD1 bit 25MAIN[16][27][12]
SPARE_WORD1 bit 26MAIN[16][26][13]
SPARE_WORD1 bit 27MAIN[16][27][13]
SPARE_WORD1 bit 28MAIN[16][26][14]
SPARE_WORD1 bit 29MAIN[16][27][14]
SPARE_WORD1 bit 30MAIN[16][26][15]
SPARE_WORD1 bit 31MAIN[16][27][15]
SPARE_WORD2 bit 0MAIN[16][26][16]
SPARE_WORD2 bit 1MAIN[16][27][16]
SPARE_WORD2 bit 2MAIN[16][26][17]
SPARE_WORD2 bit 3MAIN[16][27][17]
SPARE_WORD2 bit 4MAIN[16][26][18]
SPARE_WORD2 bit 5MAIN[16][27][18]
SPARE_WORD2 bit 6MAIN[16][26][19]
SPARE_WORD2 bit 7MAIN[16][27][19]
SPARE_WORD2 bit 8MAIN[16][26][20]
SPARE_WORD2 bit 9MAIN[16][27][20]
SPARE_WORD2 bit 10MAIN[16][26][21]
SPARE_WORD2 bit 11MAIN[16][27][21]
SPARE_WORD2 bit 12MAIN[16][26][22]
SPARE_WORD2 bit 13MAIN[16][27][22]
SPARE_WORD2 bit 14MAIN[16][26][23]
SPARE_WORD2 bit 15MAIN[16][27][23]
SPARE_WORD2 bit 16MAIN[16][26][24]
SPARE_WORD2 bit 17MAIN[16][27][24]
SPARE_WORD2 bit 18MAIN[16][26][25]
SPARE_WORD2 bit 19MAIN[16][27][25]
SPARE_WORD2 bit 20MAIN[16][26][26]
SPARE_WORD2 bit 21MAIN[16][27][26]
SPARE_WORD2 bit 22MAIN[16][26][27]
SPARE_WORD2 bit 23MAIN[16][27][27]
SPARE_WORD2 bit 24MAIN[16][26][28]
SPARE_WORD2 bit 25MAIN[16][27][28]
SPARE_WORD2 bit 26MAIN[16][26][29]
SPARE_WORD2 bit 27MAIN[16][27][29]
SPARE_WORD2 bit 28MAIN[16][26][30]
SPARE_WORD2 bit 29MAIN[16][27][30]
SPARE_WORD2 bit 30MAIN[16][26][31]
SPARE_WORD2 bit 31MAIN[16][27][31]
SPARE_WORD3 bit 0MAIN[16][26][32]
SPARE_WORD3 bit 1MAIN[16][27][32]
SPARE_WORD3 bit 2MAIN[16][26][33]
SPARE_WORD3 bit 3MAIN[16][27][33]
SPARE_WORD3 bit 4MAIN[16][26][34]
SPARE_WORD3 bit 5MAIN[16][27][34]
SPARE_WORD3 bit 6MAIN[16][26][35]
SPARE_WORD3 bit 7MAIN[16][27][35]
SPARE_WORD3 bit 8MAIN[16][26][36]
SPARE_WORD3 bit 9MAIN[16][27][36]
SPARE_WORD3 bit 10MAIN[16][26][37]
SPARE_WORD3 bit 11MAIN[16][27][37]
SPARE_WORD3 bit 12MAIN[16][26][38]
SPARE_WORD3 bit 13MAIN[16][27][38]
SPARE_WORD3 bit 14MAIN[16][26][39]
SPARE_WORD3 bit 15MAIN[16][27][39]
SPARE_WORD3 bit 16MAIN[16][26][40]
SPARE_WORD3 bit 17MAIN[16][27][40]
SPARE_WORD3 bit 18MAIN[16][26][41]
SPARE_WORD3 bit 19MAIN[16][27][41]
SPARE_WORD3 bit 20MAIN[16][26][42]
SPARE_WORD3 bit 21MAIN[16][27][42]
SPARE_WORD3 bit 22MAIN[16][26][43]
SPARE_WORD3 bit 23MAIN[16][27][43]
SPARE_WORD3 bit 24MAIN[16][26][44]
SPARE_WORD3 bit 25MAIN[16][27][44]
SPARE_WORD3 bit 26MAIN[16][26][45]
SPARE_WORD3 bit 27MAIN[16][27][45]
SPARE_WORD3 bit 28MAIN[16][26][46]
SPARE_WORD3 bit 29MAIN[16][27][46]
SPARE_WORD3 bit 30MAIN[16][26][47]
SPARE_WORD3 bit 31MAIN[16][27][47]
SUBSYSTEM_ID bit 0MAIN[10][26][8]
SUBSYSTEM_ID bit 1MAIN[10][27][8]
SUBSYSTEM_ID bit 2MAIN[10][26][9]
SUBSYSTEM_ID bit 3MAIN[10][27][9]
SUBSYSTEM_ID bit 4MAIN[10][26][10]
SUBSYSTEM_ID bit 5MAIN[10][27][10]
SUBSYSTEM_ID bit 6MAIN[10][26][11]
SUBSYSTEM_ID bit 7MAIN[10][27][11]
SUBSYSTEM_ID bit 8MAIN[10][26][12]
SUBSYSTEM_ID bit 9MAIN[10][27][12]
SUBSYSTEM_ID bit 10MAIN[10][26][13]
SUBSYSTEM_ID bit 11MAIN[10][27][13]
SUBSYSTEM_ID bit 12MAIN[10][26][14]
SUBSYSTEM_ID bit 13MAIN[10][27][14]
SUBSYSTEM_ID bit 14MAIN[10][26][15]
SUBSYSTEM_ID bit 15MAIN[10][27][15]
SUBSYSTEM_VENDOR_ID bit 0MAIN[10][26][16]
SUBSYSTEM_VENDOR_ID bit 1MAIN[10][27][16]
SUBSYSTEM_VENDOR_ID bit 2MAIN[10][26][17]
SUBSYSTEM_VENDOR_ID bit 3MAIN[10][27][17]
SUBSYSTEM_VENDOR_ID bit 4MAIN[10][26][18]
SUBSYSTEM_VENDOR_ID bit 5MAIN[10][27][18]
SUBSYSTEM_VENDOR_ID bit 6MAIN[10][26][19]
SUBSYSTEM_VENDOR_ID bit 7MAIN[10][27][19]
SUBSYSTEM_VENDOR_ID bit 8MAIN[10][26][20]
SUBSYSTEM_VENDOR_ID bit 9MAIN[10][27][20]
SUBSYSTEM_VENDOR_ID bit 10MAIN[10][26][21]
SUBSYSTEM_VENDOR_ID bit 11MAIN[10][27][21]
SUBSYSTEM_VENDOR_ID bit 12MAIN[10][26][22]
SUBSYSTEM_VENDOR_ID bit 13MAIN[10][27][22]
SUBSYSTEM_VENDOR_ID bit 14MAIN[10][26][23]
SUBSYSTEM_VENDOR_ID bit 15MAIN[10][27][23]
TL_RX_RAM_RADDR_LATENCY bit 0MAIN[13][26][38]
TL_RX_RAM_RDATA_LATENCY bit 0MAIN[13][27][38]
TL_RX_RAM_RDATA_LATENCY bit 1MAIN[13][26][39]
TL_RX_RAM_WRITE_LATENCY bit 0MAIN[13][27][39]
TL_TX_RAM_RADDR_LATENCY bit 0MAIN[13][27][41]
TL_TX_RAM_RDATA_LATENCY bit 0MAIN[13][26][42]
TL_TX_RAM_RDATA_LATENCY bit 1MAIN[13][27][42]
TL_TX_RAM_WRITE_LATENCY bit 0MAIN[13][26][43]
USER_CLK_FREQ bit 0MAIN[12][26][10]
USER_CLK_FREQ bit 1MAIN[12][27][10]
USER_CLK_FREQ bit 2MAIN[12][26][11]
VC0_RX_RAM_LIMIT bit 0MAIN[14][26][0]
VC0_RX_RAM_LIMIT bit 1MAIN[14][27][0]
VC0_RX_RAM_LIMIT bit 2MAIN[14][26][1]
VC0_RX_RAM_LIMIT bit 3MAIN[14][27][1]
VC0_RX_RAM_LIMIT bit 4MAIN[14][26][2]
VC0_RX_RAM_LIMIT bit 5MAIN[14][27][2]
VC0_RX_RAM_LIMIT bit 6MAIN[14][26][3]
VC0_RX_RAM_LIMIT bit 7MAIN[14][27][3]
VC0_RX_RAM_LIMIT bit 8MAIN[14][26][4]
VC0_RX_RAM_LIMIT bit 9MAIN[14][27][4]
VC0_RX_RAM_LIMIT bit 10MAIN[14][26][5]
VC0_RX_RAM_LIMIT bit 11MAIN[14][27][5]
VC0_RX_RAM_LIMIT bit 12MAIN[14][26][6]
VC_BASE_PTR bit 0MAIN[10][26][24]
VC_BASE_PTR bit 1MAIN[10][27][24]
VC_BASE_PTR bit 2MAIN[10][26][25]
VC_BASE_PTR bit 3MAIN[10][27][25]
VC_BASE_PTR bit 4MAIN[10][26][26]
VC_BASE_PTR bit 5MAIN[10][27][26]
VC_BASE_PTR bit 6MAIN[10][26][27]
VC_BASE_PTR bit 7MAIN[10][27][27]
VC_BASE_PTR bit 8MAIN[10][26][28]
VC_BASE_PTR bit 9MAIN[10][27][28]
VC_BASE_PTR bit 10MAIN[10][26][29]
VC_BASE_PTR bit 11MAIN[10][27][29]
VC_CAP_ID bit 0MAIN[10][26][40]
VC_CAP_ID bit 1MAIN[10][27][40]
VC_CAP_ID bit 2MAIN[10][26][41]
VC_CAP_ID bit 3MAIN[10][27][41]
VC_CAP_ID bit 4MAIN[10][26][42]
VC_CAP_ID bit 5MAIN[10][27][42]
VC_CAP_ID bit 6MAIN[10][26][43]
VC_CAP_ID bit 7MAIN[10][27][43]
VC_CAP_ID bit 8MAIN[10][26][44]
VC_CAP_ID bit 9MAIN[10][27][44]
VC_CAP_ID bit 10MAIN[10][26][45]
VC_CAP_ID bit 11MAIN[10][27][45]
VC_CAP_ID bit 12MAIN[10][26][46]
VC_CAP_ID bit 13MAIN[10][27][46]
VC_CAP_ID bit 14MAIN[10][26][47]
VC_CAP_ID bit 15MAIN[10][27][47]
VC_CAP_NEXTPTR bit 0MAIN[10][26][32]
VC_CAP_NEXTPTR bit 1MAIN[10][27][32]
VC_CAP_NEXTPTR bit 2MAIN[10][26][33]
VC_CAP_NEXTPTR bit 3MAIN[10][27][33]
VC_CAP_NEXTPTR bit 4MAIN[10][26][34]
VC_CAP_NEXTPTR bit 5MAIN[10][27][34]
VC_CAP_NEXTPTR bit 6MAIN[10][26][35]
VC_CAP_NEXTPTR bit 7MAIN[10][27][35]
VC_CAP_NEXTPTR bit 8MAIN[10][26][36]
VC_CAP_NEXTPTR bit 9MAIN[10][27][36]
VC_CAP_NEXTPTR bit 10MAIN[10][26][37]
VC_CAP_NEXTPTR bit 11MAIN[10][27][37]
VC_CAP_VERSION bit 0MAIN[13][27][43]
VC_CAP_VERSION bit 1MAIN[13][26][44]
VC_CAP_VERSION bit 2MAIN[13][27][44]
VC_CAP_VERSION bit 3MAIN[13][26][45]
VENDOR_ID bit 0MAIN[11][26][8]
VENDOR_ID bit 1MAIN[11][27][8]
VENDOR_ID bit 2MAIN[11][26][9]
VENDOR_ID bit 3MAIN[11][27][9]
VENDOR_ID bit 4MAIN[11][26][10]
VENDOR_ID bit 5MAIN[11][27][10]
VENDOR_ID bit 6MAIN[11][26][11]
VENDOR_ID bit 7MAIN[11][27][11]
VENDOR_ID bit 8MAIN[11][26][12]
VENDOR_ID bit 9MAIN[11][27][12]
VENDOR_ID bit 10MAIN[11][26][13]
VENDOR_ID bit 11MAIN[11][27][13]
VENDOR_ID bit 12MAIN[11][26][14]
VENDOR_ID bit 13MAIN[11][27][14]
VENDOR_ID bit 14MAIN[11][26][15]
VENDOR_ID bit 15MAIN[11][27][15]
VSEC_BASE_PTR bit 0MAIN[11][26][16]
VSEC_BASE_PTR bit 1MAIN[11][27][16]
VSEC_BASE_PTR bit 2MAIN[11][26][17]
VSEC_BASE_PTR bit 3MAIN[11][27][17]
VSEC_BASE_PTR bit 4MAIN[11][26][18]
VSEC_BASE_PTR bit 5MAIN[11][27][18]
VSEC_BASE_PTR bit 6MAIN[11][26][19]
VSEC_BASE_PTR bit 7MAIN[11][27][19]
VSEC_BASE_PTR bit 8MAIN[11][26][20]
VSEC_BASE_PTR bit 9MAIN[11][27][20]
VSEC_BASE_PTR bit 10MAIN[11][26][21]
VSEC_BASE_PTR bit 11MAIN[11][27][21]
VSEC_CAP_HDR_ID bit 0MAIN[11][26][24]
VSEC_CAP_HDR_ID bit 1MAIN[11][27][24]
VSEC_CAP_HDR_ID bit 2MAIN[11][26][25]
VSEC_CAP_HDR_ID bit 3MAIN[11][27][25]
VSEC_CAP_HDR_ID bit 4MAIN[11][26][26]
VSEC_CAP_HDR_ID bit 5MAIN[11][27][26]
VSEC_CAP_HDR_ID bit 6MAIN[11][26][27]
VSEC_CAP_HDR_ID bit 7MAIN[11][27][27]
VSEC_CAP_HDR_ID bit 8MAIN[11][26][28]
VSEC_CAP_HDR_ID bit 9MAIN[11][27][28]
VSEC_CAP_HDR_ID bit 10MAIN[11][26][29]
VSEC_CAP_HDR_ID bit 11MAIN[11][27][29]
VSEC_CAP_HDR_ID bit 12MAIN[11][26][30]
VSEC_CAP_HDR_ID bit 13MAIN[11][27][30]
VSEC_CAP_HDR_ID bit 14MAIN[11][26][31]
VSEC_CAP_HDR_ID bit 15MAIN[11][27][31]
VSEC_CAP_HDR_LENGTH bit 0MAIN[11][26][32]
VSEC_CAP_HDR_LENGTH bit 1MAIN[11][27][32]
VSEC_CAP_HDR_LENGTH bit 2MAIN[11][26][33]
VSEC_CAP_HDR_LENGTH bit 3MAIN[11][27][33]
VSEC_CAP_HDR_LENGTH bit 4MAIN[11][26][34]
VSEC_CAP_HDR_LENGTH bit 5MAIN[11][27][34]
VSEC_CAP_HDR_LENGTH bit 6MAIN[11][26][35]
VSEC_CAP_HDR_LENGTH bit 7MAIN[11][27][35]
VSEC_CAP_HDR_LENGTH bit 8MAIN[11][26][36]
VSEC_CAP_HDR_LENGTH bit 9MAIN[11][27][36]
VSEC_CAP_HDR_LENGTH bit 10MAIN[11][26][37]
VSEC_CAP_HDR_LENGTH bit 11MAIN[11][27][37]
VSEC_CAP_HDR_REVISION bit 0MAIN[11][26][38]
VSEC_CAP_HDR_REVISION bit 1MAIN[11][27][38]
VSEC_CAP_HDR_REVISION bit 2MAIN[11][26][39]
VSEC_CAP_HDR_REVISION bit 3MAIN[11][27][39]
VSEC_CAP_ID bit 0MAIN[11][26][40]
VSEC_CAP_ID bit 1MAIN[11][27][40]
VSEC_CAP_ID bit 2MAIN[11][26][41]
VSEC_CAP_ID bit 3MAIN[11][27][41]
VSEC_CAP_ID bit 4MAIN[11][26][42]
VSEC_CAP_ID bit 5MAIN[11][27][42]
VSEC_CAP_ID bit 6MAIN[11][26][43]
VSEC_CAP_ID bit 7MAIN[11][27][43]
VSEC_CAP_ID bit 8MAIN[11][26][44]
VSEC_CAP_ID bit 9MAIN[11][27][44]
VSEC_CAP_ID bit 10MAIN[11][26][45]
VSEC_CAP_ID bit 11MAIN[11][27][45]
VSEC_CAP_ID bit 12MAIN[11][26][46]
VSEC_CAP_ID bit 13MAIN[11][27][46]
VSEC_CAP_ID bit 14MAIN[11][26][47]
VSEC_CAP_ID bit 15MAIN[11][27][47]
VSEC_CAP_NEXTPTR bit 0MAIN[12][27][0]
VSEC_CAP_NEXTPTR bit 1MAIN[12][26][1]
VSEC_CAP_NEXTPTR bit 2MAIN[12][27][1]
VSEC_CAP_NEXTPTR bit 3MAIN[12][26][2]
VSEC_CAP_NEXTPTR bit 4MAIN[12][27][2]
VSEC_CAP_NEXTPTR bit 5MAIN[12][26][3]
VSEC_CAP_NEXTPTR bit 6MAIN[12][27][3]
VSEC_CAP_NEXTPTR bit 7MAIN[12][26][4]
VSEC_CAP_NEXTPTR bit 8MAIN[12][27][4]
VSEC_CAP_NEXTPTR bit 9MAIN[12][26][5]
VSEC_CAP_NEXTPTR bit 10MAIN[12][27][5]
VSEC_CAP_NEXTPTR bit 11MAIN[12][26][6]
VSEC_CAP_VERSION bit 0MAIN[12][26][8]
VSEC_CAP_VERSION bit 1MAIN[12][27][8]
VSEC_CAP_VERSION bit 2MAIN[12][26][9]
VSEC_CAP_VERSION bit 3MAIN[12][27][9]
N_FTS_COMCLK_GEN1 bit 0MAIN[13][26][3]
N_FTS_COMCLK_GEN1 bit 1MAIN[13][27][3]
N_FTS_COMCLK_GEN1 bit 2MAIN[13][26][4]
N_FTS_COMCLK_GEN1 bit 3MAIN[13][27][4]
N_FTS_COMCLK_GEN1 bit 4MAIN[13][26][5]
N_FTS_COMCLK_GEN1 bit 5MAIN[13][27][5]
N_FTS_COMCLK_GEN1 bit 6MAIN[13][26][6]
N_FTS_COMCLK_GEN1 bit 7MAIN[13][27][6]
N_FTS_COMCLK_GEN2 bit 0MAIN[13][26][8]
N_FTS_COMCLK_GEN2 bit 1MAIN[13][27][8]
N_FTS_COMCLK_GEN2 bit 2MAIN[13][26][9]
N_FTS_COMCLK_GEN2 bit 3MAIN[13][27][9]
N_FTS_COMCLK_GEN2 bit 4MAIN[13][26][10]
N_FTS_COMCLK_GEN2 bit 5MAIN[13][27][10]
N_FTS_COMCLK_GEN2 bit 6MAIN[13][26][11]
N_FTS_COMCLK_GEN2 bit 7MAIN[13][27][11]
N_FTS_GEN1 bit 0MAIN[13][26][12]
N_FTS_GEN1 bit 1MAIN[13][27][12]
N_FTS_GEN1 bit 2MAIN[13][26][13]
N_FTS_GEN1 bit 3MAIN[13][27][13]
N_FTS_GEN1 bit 4MAIN[13][26][14]
N_FTS_GEN1 bit 5MAIN[13][27][14]
N_FTS_GEN1 bit 6MAIN[13][26][15]
N_FTS_GEN1 bit 7MAIN[13][27][15]
N_FTS_GEN2 bit 0MAIN[13][26][16]
N_FTS_GEN2 bit 1MAIN[13][27][16]
N_FTS_GEN2 bit 2MAIN[13][26][17]
N_FTS_GEN2 bit 3MAIN[13][27][17]
N_FTS_GEN2 bit 4MAIN[13][26][18]
N_FTS_GEN2 bit 5MAIN[13][27][18]
N_FTS_GEN2 bit 6MAIN[13][26][19]
N_FTS_GEN2 bit 7MAIN[13][27][19]
PCIE_REVISION bit 0MAIN[8][26][14]
PCIE_REVISION bit 1MAIN[8][27][14]
PCIE_REVISION bit 2MAIN[8][26][15]
PCIE_REVISION bit 3MAIN[8][27][15]
VC0_TOTAL_CREDITS_CD bit 0MAIN[14][26][8]
VC0_TOTAL_CREDITS_CD bit 1MAIN[14][27][8]
VC0_TOTAL_CREDITS_CD bit 2MAIN[14][26][9]
VC0_TOTAL_CREDITS_CD bit 3MAIN[14][27][9]
VC0_TOTAL_CREDITS_CD bit 4MAIN[14][26][10]
VC0_TOTAL_CREDITS_CD bit 5MAIN[14][27][10]
VC0_TOTAL_CREDITS_CD bit 6MAIN[14][26][11]
VC0_TOTAL_CREDITS_CD bit 7MAIN[14][27][11]
VC0_TOTAL_CREDITS_CD bit 8MAIN[14][26][12]
VC0_TOTAL_CREDITS_CD bit 9MAIN[14][27][12]
VC0_TOTAL_CREDITS_CD bit 10MAIN[14][26][13]
VC0_TOTAL_CREDITS_CH bit 0MAIN[14][26][16]
VC0_TOTAL_CREDITS_CH bit 1MAIN[14][27][16]
VC0_TOTAL_CREDITS_CH bit 2MAIN[14][26][17]
VC0_TOTAL_CREDITS_CH bit 3MAIN[14][27][17]
VC0_TOTAL_CREDITS_CH bit 4MAIN[14][26][18]
VC0_TOTAL_CREDITS_CH bit 5MAIN[14][27][18]
VC0_TOTAL_CREDITS_CH bit 6MAIN[14][26][19]
VC0_TOTAL_CREDITS_NPH bit 0MAIN[14][27][19]
VC0_TOTAL_CREDITS_NPH bit 1MAIN[14][26][20]
VC0_TOTAL_CREDITS_NPH bit 2MAIN[14][27][20]
VC0_TOTAL_CREDITS_NPH bit 3MAIN[14][26][21]
VC0_TOTAL_CREDITS_NPH bit 4MAIN[14][27][21]
VC0_TOTAL_CREDITS_NPH bit 5MAIN[14][26][22]
VC0_TOTAL_CREDITS_NPH bit 6MAIN[14][27][22]
VC0_TOTAL_CREDITS_PD bit 0MAIN[14][26][24]
VC0_TOTAL_CREDITS_PD bit 1MAIN[14][27][24]
VC0_TOTAL_CREDITS_PD bit 2MAIN[14][26][25]
VC0_TOTAL_CREDITS_PD bit 3MAIN[14][27][25]
VC0_TOTAL_CREDITS_PD bit 4MAIN[14][26][26]
VC0_TOTAL_CREDITS_PD bit 5MAIN[14][27][26]
VC0_TOTAL_CREDITS_PD bit 6MAIN[14][26][27]
VC0_TOTAL_CREDITS_PD bit 7MAIN[14][27][27]
VC0_TOTAL_CREDITS_PD bit 8MAIN[14][26][28]
VC0_TOTAL_CREDITS_PD bit 9MAIN[14][27][28]
VC0_TOTAL_CREDITS_PD bit 10MAIN[14][26][29]
VC0_TOTAL_CREDITS_PH bit 0MAIN[14][26][32]
VC0_TOTAL_CREDITS_PH bit 1MAIN[14][27][32]
VC0_TOTAL_CREDITS_PH bit 2MAIN[14][26][33]
VC0_TOTAL_CREDITS_PH bit 3MAIN[14][27][33]
VC0_TOTAL_CREDITS_PH bit 4MAIN[14][26][34]
VC0_TOTAL_CREDITS_PH bit 5MAIN[14][27][34]
VC0_TOTAL_CREDITS_PH bit 6MAIN[14][26][35]
VC0_TX_LASTPACKET bit 0MAIN[14][27][35]
VC0_TX_LASTPACKET bit 1MAIN[14][26][36]
VC0_TX_LASTPACKET bit 2MAIN[14][27][36]
VC0_TX_LASTPACKET bit 3MAIN[14][26][37]
VC0_TX_LASTPACKET bit 4MAIN[14][27][37]

Bel wires

virtex6 PCIE bel wires
WirePins
CELL_W[0].IMUX_IMUX_DELAY[0]PCIE.MIMTXRDATA[45]
CELL_W[0].IMUX_IMUX_DELAY[1]PCIE.PIPERX3DATA[4]
CELL_W[0].IMUX_IMUX_DELAY[2]PCIE.CFGERRAERHEADERLOG[33]
CELL_W[0].IMUX_IMUX_DELAY[3]PCIE.PIPERX3DATA[0]
CELL_W[0].IMUX_IMUX_DELAY[4]PCIE.CFGERRAERHEADERLOG[34]
CELL_W[0].IMUX_IMUX_DELAY[5]PCIE.PIPERX3DATA[1]
CELL_W[0].IMUX_IMUX_DELAY[6]PCIE.CFGERRAERHEADERLOG[35]
CELL_W[0].IMUX_IMUX_DELAY[7]PCIE.PIPERX7DATA[2]
CELL_W[0].IMUX_IMUX_DELAY[8]PCIE.CFGERRAERHEADERLOG[36]
CELL_W[0].IMUX_IMUX_DELAY[9]PCIE.PIPERX3DATA[5]
CELL_W[0].IMUX_IMUX_DELAY[10]PCIE.CFGDSBUSNUMBER[0]
CELL_W[0].IMUX_IMUX_DELAY[11]PCIE.PIPERX7DATA[0]
CELL_W[0].IMUX_IMUX_DELAY[12]PCIE.CFGDSBUSNUMBER[1]
CELL_W[0].IMUX_IMUX_DELAY[13]PCIE.PIPERX7DATA[1]
CELL_W[0].IMUX_IMUX_DELAY[14]PCIE.CFGDSBUSNUMBER[2]
CELL_W[0].IMUX_IMUX_DELAY[15]PCIE.PIPERX3DATA[2]
CELL_W[0].IMUX_IMUX_DELAY[16]PCIE.CFGDSBUSNUMBER[3]
CELL_W[0].IMUX_IMUX_DELAY[17]PCIE.PIPERX7DATA[4]
CELL_W[0].IMUX_IMUX_DELAY[19]PCIE.PIPERX3DATA[3]
CELL_W[0].IMUX_IMUX_DELAY[21]PCIE.PIPERX7DATA[5]
CELL_W[0].IMUX_IMUX_DELAY[23]PCIE.PIPERX7DATA[3]
CELL_W[0].OUT_BEL[0]PCIE.TRNFCCPLH[5]
CELL_W[0].OUT_BEL[1]PCIE.TRNFCCPLH[6]
CELL_W[0].OUT_BEL[2]PCIE.TRNFCCPLH[7]
CELL_W[0].OUT_BEL[3]PCIE.TRNFCCPLD[0]
CELL_W[0].OUT_BEL[4]PCIE.MIMRXWDATA[11]
CELL_W[0].OUT_BEL[5]PCIE.MIMRXWDATA[12]
CELL_W[0].OUT_BEL[6]PCIE.PIPETXMARGIN[2]
CELL_W[0].OUT_BEL[7]PCIE.MIMRXWDATA[13]
CELL_W[0].OUT_BEL[8]PCIE.MIMRXWDATA[14]
CELL_W[0].OUT_BEL[9]PCIE.PL2LINKUPN
CELL_W[0].OUT_BEL[10]PCIE.PL2RECEIVERERRN
CELL_W[0].OUT_BEL[11]PCIE.LL2PROTOCOLERRN
CELL_W[0].OUT_BEL[12]PCIE.LL2BADTLPERRN
CELL_W[0].OUT_BEL[13]PCIE.CFGCOMMANDIOENABLE
CELL_W[0].OUT_BEL[14]PCIE.CFGCOMMANDMEMENABLE
CELL_W[0].OUT_BEL[15]PCIE.CFGCOMMANDBUSMASTERENABLE
CELL_W[0].OUT_BEL[16]PCIE.PIPETXMARGIN[1]
CELL_W[0].OUT_BEL[17]PCIE.CFGCOMMANDSERREN
CELL_W[0].OUT_BEL[18]PCIE.PIPETXMARGIN[0]
CELL_W[0].OUT_BEL[19]PCIE.DBGVECA[26]
CELL_W[0].OUT_BEL[20]PCIE.DBGVECA[27]
CELL_W[0].OUT_BEL[21]PCIE.DBGVECA[28]
CELL_W[0].OUT_BEL[22]PCIE.DBGVECA[29]
CELL_W[0].OUT_BEL[23]PCIE.DBGVECB[59]
CELL_W[1].IMUX_IMUX_DELAY[0]PCIE.MIMTXRDATA[44]
CELL_W[1].IMUX_IMUX_DELAY[1]PCIE.PIPERX3DATA[6]
CELL_W[1].IMUX_IMUX_DELAY[2]PCIE.CFGERRAERHEADERLOG[29]
CELL_W[1].IMUX_IMUX_DELAY[3]PCIE.PIPERX3DATA[8]
CELL_W[1].IMUX_IMUX_DELAY[4]PCIE.CFGERRAERHEADERLOG[30]
CELL_W[1].IMUX_IMUX_DELAY[5]PCIE.PIPERX3DATA[9]
CELL_W[1].IMUX_IMUX_DELAY[6]PCIE.CFGERRAERHEADERLOG[31]
CELL_W[1].IMUX_IMUX_DELAY[7]PCIE.PIPERX3DATA[10]
CELL_W[1].IMUX_IMUX_DELAY[8]PCIE.CFGERRAERHEADERLOG[32]
CELL_W[1].IMUX_IMUX_DELAY[9]PCIE.PIPERX3DATA[7]
CELL_W[1].IMUX_IMUX_DELAY[10]PCIE.CFGINTERRUPTDI[5]
CELL_W[1].IMUX_IMUX_DELAY[11]PCIE.PIPERX7DATA[8]
CELL_W[1].IMUX_IMUX_DELAY[12]PCIE.CFGINTERRUPTDI[6]
CELL_W[1].IMUX_IMUX_DELAY[13]PCIE.PIPERX7DATA[9]
CELL_W[1].IMUX_IMUX_DELAY[14]PCIE.CFGINTERRUPTDI[7]
CELL_W[1].IMUX_IMUX_DELAY[15]PCIE.PIPERX3DATA[11]
CELL_W[1].IMUX_IMUX_DELAY[16]PCIE.CFGINTERRUPTASSERTN
CELL_W[1].IMUX_IMUX_DELAY[17]PCIE.PIPERX7DATA[6]
CELL_W[1].IMUX_IMUX_DELAY[19]PCIE.PIPERX7DATA[10]
CELL_W[1].IMUX_IMUX_DELAY[21]PCIE.PIPERX7DATA[7]
CELL_W[1].IMUX_IMUX_DELAY[23]PCIE.PIPERX7DATA[11]
CELL_W[1].OUT_BEL[0]PCIE.TRNFCCPLH[1]
CELL_W[1].OUT_BEL[1]PCIE.TRNFCCPLH[2]
CELL_W[1].OUT_BEL[2]PCIE.TRNFCCPLH[3]
CELL_W[1].OUT_BEL[3]PCIE.TRNFCCPLH[4]
CELL_W[1].OUT_BEL[4]PCIE.MIMRXWDATA[7]
CELL_W[1].OUT_BEL[5]PCIE.MIMRXWDATA[8]
CELL_W[1].OUT_BEL[6]PCIE.MIMRXWDATA[9]
CELL_W[1].OUT_BEL[7]PCIE.MIMRXWDATA[10]
CELL_W[1].OUT_BEL[8]PCIE.LL2SUSPENDOKN
CELL_W[1].OUT_BEL[9]PCIE.TL2PPMSUSPENDOKN
CELL_W[1].OUT_BEL[10]PCIE.TL2ASPMSUSPENDREQN
CELL_W[1].OUT_BEL[11]PCIE.TL2ASPMSUSPENDCREDITCHECKOKN
CELL_W[1].OUT_BEL[12]PCIE.CFGTRANSACTIONADDR[3]
CELL_W[1].OUT_BEL[13]PCIE.CFGTRANSACTIONADDR[4]
CELL_W[1].OUT_BEL[14]PCIE.CFGTRANSACTIONADDR[5]
CELL_W[1].OUT_BEL[15]PCIE.CFGTRANSACTIONADDR[6]
CELL_W[1].OUT_BEL[16]PCIE.DRPDO[7]
CELL_W[1].OUT_BEL[17]PCIE.DRPDO[8]
CELL_W[1].OUT_BEL[18]PCIE.PIPERX3POLARITY
CELL_W[1].OUT_BEL[19]PCIE.DRPDO[9]
CELL_W[1].OUT_BEL[20]PCIE.DBGVECB[58]
CELL_W[1].OUT_BEL[21]PCIE.DBGVECA[24]
CELL_W[1].OUT_BEL[22]PCIE.PIPERX7POLARITY
CELL_W[1].OUT_BEL[23]PCIE.DBGVECA[25]
CELL_W[2].IMUX_IMUX_DELAY[0]PCIE.MIMTXRDATA[41]
CELL_W[2].IMUX_IMUX_DELAY[1]PCIE.PIPERX3CHARISK[1]
CELL_W[2].IMUX_IMUX_DELAY[2]PCIE.MIMTXRDATA[42]
CELL_W[2].IMUX_IMUX_DELAY[3]PCIE.PIPERX7DATA[13]
CELL_W[2].IMUX_IMUX_DELAY[4]PCIE.MIMTXRDATA[43]
CELL_W[2].IMUX_IMUX_DELAY[5]PCIE.PIPERX3DATA[12]
CELL_W[2].IMUX_IMUX_DELAY[6]PCIE.CFGERRAERHEADERLOG[25]
CELL_W[2].IMUX_IMUX_DELAY[7]PCIE.PIPERX3DATA[13]
CELL_W[2].IMUX_IMUX_DELAY[8]PCIE.CFGERRAERHEADERLOG[26]
CELL_W[2].IMUX_IMUX_DELAY[9]PCIE.PIPERX3DATA[15]
CELL_W[2].IMUX_IMUX_DELAY[10]PCIE.CFGERRAERHEADERLOG[27]
CELL_W[2].IMUX_IMUX_DELAY[11]PCIE.PIPERX3DATA[14]
CELL_W[2].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[28]
CELL_W[2].IMUX_IMUX_DELAY[13]PCIE.PIPERX7DATA[12]
CELL_W[2].IMUX_IMUX_DELAY[14]PCIE.CFGINTERRUPTDI[1]
CELL_W[2].IMUX_IMUX_DELAY[15]PCIE.PIPERX7DATA[14]
CELL_W[2].IMUX_IMUX_DELAY[16]PCIE.CFGINTERRUPTDI[2]
CELL_W[2].IMUX_IMUX_DELAY[17]PCIE.PIPERX7CHARISK[1]
CELL_W[2].IMUX_IMUX_DELAY[18]PCIE.CFGINTERRUPTDI[3]
CELL_W[2].IMUX_IMUX_DELAY[19]PCIE.CFGINTERRUPTDI[4]
CELL_W[2].IMUX_IMUX_DELAY[21]PCIE.PIPERX7DATA[15]
CELL_W[2].OUT_BEL[0]PCIE.TRNFCNPD[9]
CELL_W[2].OUT_BEL[1]PCIE.TRNFCNPD[10]
CELL_W[2].OUT_BEL[2]PCIE.TRNFCNPD[11]
CELL_W[2].OUT_BEL[3]PCIE.TRNFCCPLH[0]
CELL_W[2].OUT_BEL[4]PCIE.MIMRXWDATA[3]
CELL_W[2].OUT_BEL[5]PCIE.MIMRXWDATA[4]
CELL_W[2].OUT_BEL[6]PCIE.MIMRXWDATA[5]
CELL_W[2].OUT_BEL[7]PCIE.MIMRXWDATA[6]
CELL_W[2].OUT_BEL[8]PCIE.LL2TFCINIT2SEQN
CELL_W[2].OUT_BEL[9]PCIE.PL2SUSPENDOK
CELL_W[2].OUT_BEL[10]PCIE.PL2RECOVERYN
CELL_W[2].OUT_BEL[11]PCIE.PL2RXELECIDLE
CELL_W[2].OUT_BEL[12]PCIE.CFGTRANSACTIONTYPE
CELL_W[2].OUT_BEL[13]PCIE.CFGTRANSACTIONADDR[0]
CELL_W[2].OUT_BEL[14]PCIE.CFGTRANSACTIONADDR[1]
CELL_W[2].OUT_BEL[15]PCIE.CFGTRANSACTIONADDR[2]
CELL_W[2].OUT_BEL[16]PCIE.DRPDO[3]
CELL_W[2].OUT_BEL[17]PCIE.DRPDO[4]
CELL_W[2].OUT_BEL[18]PCIE.DRPDO[5]
CELL_W[2].OUT_BEL[19]PCIE.DRPDO[6]
CELL_W[2].OUT_BEL[20]PCIE.DBGVECA[20]
CELL_W[2].OUT_BEL[21]PCIE.DBGVECA[21]
CELL_W[2].OUT_BEL[22]PCIE.DBGVECA[22]
CELL_W[2].OUT_BEL[23]PCIE.DBGVECA[23]
CELL_W[3].IMUX_IMUX_DELAY[0]PCIE.MIMTXRDATA[37]
CELL_W[3].IMUX_IMUX_DELAY[1]PCIE.PIPERX7CHANISALIGNED
CELL_W[3].IMUX_IMUX_DELAY[2]PCIE.MIMTXRDATA[38]
CELL_W[3].IMUX_IMUX_DELAY[3]PCIE.MIMTXRDATA[39]
CELL_W[3].IMUX_IMUX_DELAY[4]PCIE.MIMTXRDATA[40]
CELL_W[3].IMUX_IMUX_DELAY[5]PCIE.TRNTDLLPDATA[23]
CELL_W[3].IMUX_IMUX_DELAY[6]PCIE.TRNTDLLPDATA[24]
CELL_W[3].IMUX_IMUX_DELAY[7]PCIE.TRNTDLLPDATA[25]
CELL_W[3].IMUX_IMUX_DELAY[8]PCIE.TRNTDLLPDATA[26]
CELL_W[3].IMUX_IMUX_DELAY[9]PCIE.CFGERRAERHEADERLOG[21]
CELL_W[3].IMUX_IMUX_DELAY[10]PCIE.CFGERRAERHEADERLOG[22]
CELL_W[3].IMUX_IMUX_DELAY[11]PCIE.CFGERRAERHEADERLOG[23]
CELL_W[3].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[24]
CELL_W[3].IMUX_IMUX_DELAY[13]PCIE.CFGERRTLPCPLHEADER[46]
CELL_W[3].IMUX_IMUX_DELAY[14]PCIE.CFGERRTLPCPLHEADER[47]
CELL_W[3].IMUX_IMUX_DELAY[15]PCIE.PIPERX7CHARISK[0]
CELL_W[3].IMUX_IMUX_DELAY[16]PCIE.CFGINTERRUPTN
CELL_W[3].IMUX_IMUX_DELAY[17]PCIE.CFGINTERRUPTDI[0]
CELL_W[3].IMUX_IMUX_DELAY[18]PCIE.CFGDSN[63]
CELL_W[3].IMUX_IMUX_DELAY[21]PCIE.PIPERX3CHANISALIGNED
CELL_W[3].IMUX_IMUX_DELAY[23]PCIE.PIPERX3CHARISK[0]
CELL_W[3].OUT_BEL[0]PCIE.TRNFCNPD[5]
CELL_W[3].OUT_BEL[1]PCIE.TRNFCNPD[6]
CELL_W[3].OUT_BEL[2]PCIE.TRNFCNPD[7]
CELL_W[3].OUT_BEL[3]PCIE.TRNFCNPD[8]
CELL_W[3].OUT_BEL[4]PCIE.MIMTXRCE
CELL_W[3].OUT_BEL[5]PCIE.MIMRXWDATA[0]
CELL_W[3].OUT_BEL[6]PCIE.MIMRXWDATA[1]
CELL_W[3].OUT_BEL[7]PCIE.MIMRXWDATA[2]
CELL_W[3].OUT_BEL[8]PCIE.TRNRDLLPDATA[30]
CELL_W[3].OUT_BEL[9]PCIE.TRNRDLLPDATA[31]
CELL_W[3].OUT_BEL[10]PCIE.TRNRDLLPSRCRDYN
CELL_W[3].OUT_BEL[11]PCIE.LL2TFCINIT1SEQN
CELL_W[3].OUT_BEL[12]PCIE.CFGPMRCVENTERL1N
CELL_W[3].OUT_BEL[13]PCIE.CFGPMRCVENTERL23N
CELL_W[3].OUT_BEL[14]PCIE.CFGPMRCVREQACKN
CELL_W[3].OUT_BEL[15]PCIE.CFGTRANSACTION
CELL_W[3].OUT_BEL[16]PCIE.DRPDRDY
CELL_W[3].OUT_BEL[17]PCIE.DRPDO[0]
CELL_W[3].OUT_BEL[18]PCIE.DRPDO[1]
CELL_W[3].OUT_BEL[19]PCIE.DRPDO[2]
CELL_W[3].OUT_BEL[20]PCIE.DBGVECA[16]
CELL_W[3].OUT_BEL[21]PCIE.DBGVECA[17]
CELL_W[3].OUT_BEL[22]PCIE.DBGVECA[18]
CELL_W[3].OUT_BEL[23]PCIE.DBGVECA[19]
CELL_W[4].IMUX_IMUX_DELAY[0]PCIE.MIMTXRDATA[33]
CELL_W[4].IMUX_IMUX_DELAY[1]PCIE.PIPERX7STATUS[2]
CELL_W[4].IMUX_IMUX_DELAY[2]PCIE.MIMTXRDATA[34]
CELL_W[4].IMUX_IMUX_DELAY[3]PCIE.PIPERX7STATUS[0]
CELL_W[4].IMUX_IMUX_DELAY[4]PCIE.MIMTXRDATA[35]
CELL_W[4].IMUX_IMUX_DELAY[5]PCIE.MIMTXRDATA[36]
CELL_W[4].IMUX_IMUX_DELAY[6]PCIE.TRNTDLLPDATA[22]
CELL_W[4].IMUX_IMUX_DELAY[7]PCIE.PIPERX7STATUS[1]
CELL_W[4].IMUX_IMUX_DELAY[8]PCIE.CFGERRAERHEADERLOG[17]
CELL_W[4].IMUX_IMUX_DELAY[9]PCIE.CFGERRAERHEADERLOG[18]
CELL_W[4].IMUX_IMUX_DELAY[10]PCIE.CFGERRAERHEADERLOG[19]
CELL_W[4].IMUX_IMUX_DELAY[11]PCIE.PIPERX3PHYSTATUS
CELL_W[4].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[20]
CELL_W[4].IMUX_IMUX_DELAY[13]PCIE.CFGERRTLPCPLHEADER[42]
CELL_W[4].IMUX_IMUX_DELAY[14]PCIE.CFGERRTLPCPLHEADER[43]
CELL_W[4].IMUX_IMUX_DELAY[15]PCIE.PIPERX7PHYSTATUS
CELL_W[4].IMUX_IMUX_DELAY[16]PCIE.CFGERRTLPCPLHEADER[44]
CELL_W[4].IMUX_IMUX_DELAY[17]PCIE.CFGERRTLPCPLHEADER[45]
CELL_W[4].IMUX_IMUX_DELAY[19]PCIE.PIPERX3STATUS[1]
CELL_W[4].IMUX_IMUX_DELAY[21]PCIE.PIPERX3STATUS[2]
CELL_W[4].IMUX_IMUX_DELAY[23]PCIE.PIPERX3STATUS[0]
CELL_W[4].OUT_BEL[0]PCIE.TRNFCNPD[1]
CELL_W[4].OUT_BEL[1]PCIE.PIPETX3ELECIDLE
CELL_W[4].OUT_BEL[2]PCIE.TRNFCNPD[2]
CELL_W[4].OUT_BEL[3]PCIE.TRNFCNPD[3]
CELL_W[4].OUT_BEL[4]PCIE.TRNFCNPD[4]
CELL_W[4].OUT_BEL[5]PCIE.PIPETX7ELECIDLE
CELL_W[4].OUT_BEL[6]PCIE.MIMTXRADDR[10]
CELL_W[4].OUT_BEL[7]PCIE.MIMTXRADDR[11]
CELL_W[4].OUT_BEL[8]PCIE.MIMTXRADDR[12]
CELL_W[4].OUT_BEL[9]PCIE.MIMTXREN
CELL_W[4].OUT_BEL[10]PCIE.TRNRDLLPDATA[26]
CELL_W[4].OUT_BEL[11]PCIE.TRNRDLLPDATA[27]
CELL_W[4].OUT_BEL[12]PCIE.TRNRDLLPDATA[28]
CELL_W[4].OUT_BEL[13]PCIE.TRNRDLLPDATA[29]
CELL_W[4].OUT_BEL[14]PCIE.CFGPCIELINKSTATE[2]
CELL_W[4].OUT_BEL[15]PCIE.CFGPMRCVASREQL1N
CELL_W[4].OUT_BEL[16]PCIE.DBGVECB[57]
CELL_W[4].OUT_BEL[17]PCIE.PIPETX7POWERDOWN[0]
CELL_W[4].OUT_BEL[18]PCIE.DBGVECA[13]
CELL_W[4].OUT_BEL[19]PCIE.PIPETX7POWERDOWN[1]
CELL_W[4].OUT_BEL[20]PCIE.DBGVECA[14]
CELL_W[4].OUT_BEL[21]PCIE.PIPETX3POWERDOWN[0]
CELL_W[4].OUT_BEL[22]PCIE.DBGVECA[15]
CELL_W[4].OUT_BEL[23]PCIE.PIPETX3POWERDOWN[1]
CELL_W[5].IMUX_IMUX_DELAY[0]PCIE.MIMTXRDATA[29]
CELL_W[5].IMUX_IMUX_DELAY[1]PCIE.MIMTXRDATA[30]
CELL_W[5].IMUX_IMUX_DELAY[2]PCIE.MIMTXRDATA[31]
CELL_W[5].IMUX_IMUX_DELAY[3]PCIE.MIMTXRDATA[32]
CELL_W[5].IMUX_IMUX_DELAY[4]PCIE.TRNTDLLPDATA[18]
CELL_W[5].IMUX_IMUX_DELAY[5]PCIE.PIPERX7ELECIDLE
CELL_W[5].IMUX_IMUX_DELAY[6]PCIE.TRNTDLLPDATA[19]
CELL_W[5].IMUX_IMUX_DELAY[7]PCIE.TRNTDLLPDATA[20]
CELL_W[5].IMUX_IMUX_DELAY[8]PCIE.TRNTDLLPDATA[21]
CELL_W[5].IMUX_IMUX_DELAY[9]PCIE.CFGERRAERHEADERLOG[13]
CELL_W[5].IMUX_IMUX_DELAY[10]PCIE.CFGERRAERHEADERLOG[14]
CELL_W[5].IMUX_IMUX_DELAY[11]PCIE.PIPERX7VALID
CELL_W[5].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[15]
CELL_W[5].IMUX_IMUX_DELAY[13]PCIE.CFGERRAERHEADERLOG[16]
CELL_W[5].IMUX_IMUX_DELAY[14]PCIE.CFGERRTLPCPLHEADER[38]
CELL_W[5].IMUX_IMUX_DELAY[15]PCIE.CFGERRTLPCPLHEADER[39]
CELL_W[5].IMUX_IMUX_DELAY[16]PCIE.CFGERRTLPCPLHEADER[40]
CELL_W[5].IMUX_IMUX_DELAY[17]PCIE.CFGERRTLPCPLHEADER[41]
CELL_W[5].IMUX_IMUX_DELAY[18]PCIE.CFGDSN[62]
CELL_W[5].IMUX_IMUX_DELAY[19]PCIE.PIPERX3VALID
CELL_W[5].IMUX_IMUX_DELAY[21]PCIE.PIPERX3ELECIDLE
CELL_W[5].OUT_BEL[0]PCIE.TRNFCNPH[5]
CELL_W[5].OUT_BEL[1]PCIE.TRNFCNPH[6]
CELL_W[5].OUT_BEL[2]PCIE.TRNFCNPH[7]
CELL_W[5].OUT_BEL[3]PCIE.TRNFCNPD[0]
CELL_W[5].OUT_BEL[4]PCIE.MIMTXRADDR[6]
CELL_W[5].OUT_BEL[5]PCIE.MIMTXRADDR[7]
CELL_W[5].OUT_BEL[6]PCIE.MIMTXRADDR[8]
CELL_W[5].OUT_BEL[7]PCIE.MIMTXRADDR[9]
CELL_W[5].OUT_BEL[8]PCIE.TRNRDLLPDATA[22]
CELL_W[5].OUT_BEL[9]PCIE.TRNRDLLPDATA[23]
CELL_W[5].OUT_BEL[10]PCIE.TRNRDLLPDATA[24]
CELL_W[5].OUT_BEL[11]PCIE.TRNRDLLPDATA[25]
CELL_W[5].OUT_BEL[12]PCIE.CFGPCIELINKSTATE[1]
CELL_W[5].OUT_BEL[13]PCIE.DBGVECB[55]
CELL_W[5].OUT_BEL[14]PCIE.DBGVECB[56]
CELL_W[5].OUT_BEL[15]PCIE.DBGVECA[10]
CELL_W[5].OUT_BEL[16]PCIE.PIPETX3COMPLIANCE
CELL_W[5].OUT_BEL[17]PCIE.DBGVECA[11]
CELL_W[5].OUT_BEL[18]PCIE.PIPETX3CHARISK[0]
CELL_W[5].OUT_BEL[19]PCIE.PIPETX7CHARISK[1]
CELL_W[5].OUT_BEL[20]PCIE.PIPETX7COMPLIANCE
CELL_W[5].OUT_BEL[21]PCIE.DBGVECA[12]
CELL_W[5].OUT_BEL[22]PCIE.PIPETX7CHARISK[0]
CELL_W[5].OUT_BEL[23]PCIE.PIPETX3CHARISK[1]
CELL_W[6].IMUX_IMUX_DELAY[0]PCIE.MIMTXRDATA[25]
CELL_W[6].IMUX_IMUX_DELAY[1]PCIE.MIMTXRDATA[26]
CELL_W[6].IMUX_IMUX_DELAY[2]PCIE.MIMTXRDATA[27]
CELL_W[6].IMUX_IMUX_DELAY[3]PCIE.MIMTXRDATA[28]
CELL_W[6].IMUX_IMUX_DELAY[4]PCIE.TRNTDLLPDATA[14]
CELL_W[6].IMUX_IMUX_DELAY[5]PCIE.TRNTDLLPDATA[15]
CELL_W[6].IMUX_IMUX_DELAY[6]PCIE.TRNTDLLPDATA[16]
CELL_W[6].IMUX_IMUX_DELAY[7]PCIE.TRNTDLLPDATA[17]
CELL_W[6].IMUX_IMUX_DELAY[8]PCIE.CFGERRAERHEADERLOG[9]
CELL_W[6].IMUX_IMUX_DELAY[9]PCIE.CFGERRAERHEADERLOG[10]
CELL_W[6].IMUX_IMUX_DELAY[10]PCIE.CFGERRAERHEADERLOG[11]
CELL_W[6].IMUX_IMUX_DELAY[11]PCIE.CFGERRAERHEADERLOG[12]
CELL_W[6].IMUX_IMUX_DELAY[12]PCIE.CFGERRTLPCPLHEADER[34]
CELL_W[6].IMUX_IMUX_DELAY[13]PCIE.CFGERRTLPCPLHEADER[35]
CELL_W[6].IMUX_IMUX_DELAY[14]PCIE.CFGERRTLPCPLHEADER[36]
CELL_W[6].IMUX_IMUX_DELAY[15]PCIE.CFGERRTLPCPLHEADER[37]
CELL_W[6].IMUX_IMUX_DELAY[16]PCIE.CFGDSN[58]
CELL_W[6].IMUX_IMUX_DELAY[17]PCIE.CFGDSN[59]
CELL_W[6].IMUX_IMUX_DELAY[18]PCIE.CFGDSN[60]
CELL_W[6].IMUX_IMUX_DELAY[19]PCIE.CFGDSN[61]
CELL_W[6].IMUX_IMUX_DELAY[20]PCIE.DBGMODE[1]
CELL_W[6].OUT_BEL[0]PCIE.TRNFCNPH[1]
CELL_W[6].OUT_BEL[1]PCIE.TRNFCNPH[2]
CELL_W[6].OUT_BEL[2]PCIE.PIPETX7DATA[13]
CELL_W[6].OUT_BEL[3]PCIE.TRNFCNPH[3]
CELL_W[6].OUT_BEL[4]PCIE.TRNFCNPH[4]
CELL_W[6].OUT_BEL[5]PCIE.MIMTXRADDR[2]
CELL_W[6].OUT_BEL[6]PCIE.PIPETX3DATA[13]
CELL_W[6].OUT_BEL[7]PCIE.MIMTXRADDR[3]
CELL_W[6].OUT_BEL[8]PCIE.MIMTXRADDR[4]
CELL_W[6].OUT_BEL[9]PCIE.MIMTXRADDR[5]
CELL_W[6].OUT_BEL[10]PCIE.TRNRDLLPDATA[20]
CELL_W[6].OUT_BEL[11]PCIE.TRNRDLLPDATA[21]
CELL_W[6].OUT_BEL[12]PCIE.CFGPCIELINKSTATE[0]
CELL_W[6].OUT_BEL[13]PCIE.DBGVECB[53]
CELL_W[6].OUT_BEL[14]PCIE.DBGVECB[54]
CELL_W[6].OUT_BEL[15]PCIE.DBGVECA[7]
CELL_W[6].OUT_BEL[16]PCIE.PIPETX3DATA[12]
CELL_W[6].OUT_BEL[17]PCIE.PIPETX7DATA[15]
CELL_W[6].OUT_BEL[18]PCIE.DBGVECA[8]
CELL_W[6].OUT_BEL[19]PCIE.PIPETX7DATA[14]
CELL_W[6].OUT_BEL[20]PCIE.PIPETX7DATA[12]
CELL_W[6].OUT_BEL[21]PCIE.PIPETX3DATA[15]
CELL_W[6].OUT_BEL[22]PCIE.DBGVECA[9]
CELL_W[6].OUT_BEL[23]PCIE.PIPETX3DATA[14]
CELL_W[7].IMUX_IMUX_DELAY[0]PCIE.MIMTXRDATA[21]
CELL_W[7].IMUX_IMUX_DELAY[1]PCIE.MIMTXRDATA[22]
CELL_W[7].IMUX_IMUX_DELAY[2]PCIE.MIMTXRDATA[23]
CELL_W[7].IMUX_IMUX_DELAY[3]PCIE.MIMTXRDATA[24]
CELL_W[7].IMUX_IMUX_DELAY[4]PCIE.TRNTDLLPDATA[10]
CELL_W[7].IMUX_IMUX_DELAY[5]PCIE.TRNTDLLPDATA[11]
CELL_W[7].IMUX_IMUX_DELAY[6]PCIE.TRNTDLLPDATA[12]
CELL_W[7].IMUX_IMUX_DELAY[7]PCIE.TRNTDLLPDATA[13]
CELL_W[7].IMUX_IMUX_DELAY[8]PCIE.CFGERRAERHEADERLOG[5]
CELL_W[7].IMUX_IMUX_DELAY[9]PCIE.CFGERRAERHEADERLOG[6]
CELL_W[7].IMUX_IMUX_DELAY[10]PCIE.CFGERRAERHEADERLOG[7]
CELL_W[7].IMUX_IMUX_DELAY[11]PCIE.CFGERRAERHEADERLOG[8]
CELL_W[7].IMUX_IMUX_DELAY[12]PCIE.CFGERRTLPCPLHEADER[30]
CELL_W[7].IMUX_IMUX_DELAY[13]PCIE.CFGERRTLPCPLHEADER[31]
CELL_W[7].IMUX_IMUX_DELAY[14]PCIE.CFGERRTLPCPLHEADER[32]
CELL_W[7].IMUX_IMUX_DELAY[15]PCIE.CFGERRTLPCPLHEADER[33]
CELL_W[7].IMUX_IMUX_DELAY[16]PCIE.CFGDSN[54]
CELL_W[7].IMUX_IMUX_DELAY[17]PCIE.CFGDSN[55]
CELL_W[7].IMUX_IMUX_DELAY[18]PCIE.CFGDSN[56]
CELL_W[7].IMUX_IMUX_DELAY[19]PCIE.CFGDSN[57]
CELL_W[7].IMUX_IMUX_DELAY[20]PCIE.DBGMODE[0]
CELL_W[7].OUT_BEL[0]PCIE.TRNFCPD[9]
CELL_W[7].OUT_BEL[1]PCIE.PIPETX3DATA[11]
CELL_W[7].OUT_BEL[2]PCIE.PIPETX7DATA[8]
CELL_W[7].OUT_BEL[3]PCIE.TRNFCPD[10]
CELL_W[7].OUT_BEL[4]PCIE.TRNFCPD[11]
CELL_W[7].OUT_BEL[5]PCIE.PIPETX7DATA[11]
CELL_W[7].OUT_BEL[6]PCIE.PIPETX3DATA[8]
CELL_W[7].OUT_BEL[7]PCIE.TRNFCNPH[0]
CELL_W[7].OUT_BEL[8]PCIE.MIMTXRADDR[0]
CELL_W[7].OUT_BEL[9]PCIE.MIMTXRADDR[1]
CELL_W[7].OUT_BEL[10]PCIE.CFGMSGRECEIVEDPMASNAK
CELL_W[7].OUT_BEL[11]PCIE.DBGVECB[51]
CELL_W[7].OUT_BEL[12]PCIE.DBGVECB[52]
CELL_W[7].OUT_BEL[13]PCIE.DBGVECA[4]
CELL_W[7].OUT_BEL[14]PCIE.DBGVECA[5]
CELL_W[7].OUT_BEL[15]PCIE.DBGVECA[6]
CELL_W[7].OUT_BEL[16]PCIE.PIPETX3DATA[7]
CELL_W[7].OUT_BEL[17]PCIE.PIPETX7DATA[10]
CELL_W[7].OUT_BEL[18]PCIE.PIPETX3DATA[6]
CELL_W[7].OUT_BEL[19]PCIE.PIPETX7DATA[9]
CELL_W[7].OUT_BEL[20]PCIE.PIPETX7DATA[7]
CELL_W[7].OUT_BEL[21]PCIE.PIPETX3DATA[10]
CELL_W[7].OUT_BEL[22]PCIE.PIPETX7DATA[6]
CELL_W[7].OUT_BEL[23]PCIE.PIPETX3DATA[9]
CELL_W[8].IMUX_IMUX_DELAY[0]PCIE.MIMTXRDATA[17]
CELL_W[8].IMUX_IMUX_DELAY[1]PCIE.MIMTXRDATA[18]
CELL_W[8].IMUX_IMUX_DELAY[2]PCIE.MIMTXRDATA[19]
CELL_W[8].IMUX_IMUX_DELAY[3]PCIE.MIMTXRDATA[20]
CELL_W[8].IMUX_IMUX_DELAY[4]PCIE.TRNTDLLPDATA[6]
CELL_W[8].IMUX_IMUX_DELAY[5]PCIE.TRNTDLLPDATA[7]
CELL_W[8].IMUX_IMUX_DELAY[6]PCIE.TRNTDLLPDATA[8]
CELL_W[8].IMUX_IMUX_DELAY[7]PCIE.TRNTDLLPDATA[9]
CELL_W[8].IMUX_IMUX_DELAY[8]PCIE.CFGERRAERHEADERLOG[1]
CELL_W[8].IMUX_IMUX_DELAY[9]PCIE.CFGERRAERHEADERLOG[2]
CELL_W[8].IMUX_IMUX_DELAY[10]PCIE.CFGERRAERHEADERLOG[3]
CELL_W[8].IMUX_IMUX_DELAY[11]PCIE.CFGERRAERHEADERLOG[4]
CELL_W[8].IMUX_IMUX_DELAY[12]PCIE.CFGERRTLPCPLHEADER[26]
CELL_W[8].IMUX_IMUX_DELAY[13]PCIE.CFGERRTLPCPLHEADER[27]
CELL_W[8].IMUX_IMUX_DELAY[14]PCIE.CFGERRTLPCPLHEADER[28]
CELL_W[8].IMUX_IMUX_DELAY[15]PCIE.CFGERRTLPCPLHEADER[29]
CELL_W[8].IMUX_IMUX_DELAY[16]PCIE.CFGDSN[50]
CELL_W[8].IMUX_IMUX_DELAY[17]PCIE.CFGDSN[51]
CELL_W[8].IMUX_IMUX_DELAY[18]PCIE.CFGDSN[52]
CELL_W[8].IMUX_IMUX_DELAY[19]PCIE.CFGDSN[53]
CELL_W[8].IMUX_IMUX_DELAY[20]PCIE.DRPDI[15]
CELL_W[8].OUT_BEL[0]PCIE.TRNFCPD[5]
CELL_W[8].OUT_BEL[1]PCIE.PIPETX3DATA[3]
CELL_W[8].OUT_BEL[2]PCIE.PIPETX7DATA[4]
CELL_W[8].OUT_BEL[3]PCIE.TRNFCPD[6]
CELL_W[8].OUT_BEL[4]PCIE.TRNFCPD[7]
CELL_W[8].OUT_BEL[5]PCIE.PIPETX7DATA[3]
CELL_W[8].OUT_BEL[6]PCIE.PIPETX3DATA[4]
CELL_W[8].OUT_BEL[7]PCIE.TRNFCPD[8]
CELL_W[8].OUT_BEL[8]PCIE.MIMTXWADDR[12]
CELL_W[8].OUT_BEL[9]PCIE.MIMTXWEN
CELL_W[8].OUT_BEL[10]PCIE.CFGMSGRECEIVEDUNLOCK
CELL_W[8].OUT_BEL[11]PCIE.DBGVECB[49]
CELL_W[8].OUT_BEL[12]PCIE.CFGVCTCVCMAP[4]
CELL_W[8].OUT_BEL[13]PCIE.CFGVCTCVCMAP[5]
CELL_W[8].OUT_BEL[14]PCIE.CFGVCTCVCMAP[6]
CELL_W[8].OUT_BEL[15]PCIE.DBGVECB[50]
CELL_W[8].OUT_BEL[16]PCIE.PIPETX3DATA[0]
CELL_W[8].OUT_BEL[17]PCIE.PIPETX7DATA[1]
CELL_W[8].OUT_BEL[18]PCIE.PIPETX3DATA[5]
CELL_W[8].OUT_BEL[19]PCIE.PIPETX7DATA[2]
CELL_W[8].OUT_BEL[20]PCIE.PIPETX7DATA[0]
CELL_W[8].OUT_BEL[21]PCIE.PIPETX3DATA[1]
CELL_W[8].OUT_BEL[22]PCIE.PIPETX7DATA[5]
CELL_W[8].OUT_BEL[23]PCIE.PIPETX3DATA[2]
CELL_W[9].IMUX_IMUX_DELAY[0]PCIE.MIMTXRDATA[13]
CELL_W[9].IMUX_IMUX_DELAY[1]PCIE.MIMTXRDATA[14]
CELL_W[9].IMUX_IMUX_DELAY[2]PCIE.MIMTXRDATA[15]
CELL_W[9].IMUX_IMUX_DELAY[3]PCIE.MIMTXRDATA[16]
CELL_W[9].IMUX_IMUX_DELAY[4]PCIE.TRNTDLLPDATA[2]
CELL_W[9].IMUX_IMUX_DELAY[5]PCIE.TRNTDLLPDATA[3]
CELL_W[9].IMUX_IMUX_DELAY[6]PCIE.TRNTDLLPDATA[4]
CELL_W[9].IMUX_IMUX_DELAY[7]PCIE.TRNTDLLPDATA[5]
CELL_W[9].IMUX_IMUX_DELAY[8]PCIE.CFGERRACSN
CELL_W[9].IMUX_IMUX_DELAY[9]PCIE.CFGERRPOSTEDN
CELL_W[9].IMUX_IMUX_DELAY[10]PCIE.CFGERRLOCKEDN
CELL_W[9].IMUX_IMUX_DELAY[11]PCIE.CFGERRAERHEADERLOG[0]
CELL_W[9].IMUX_IMUX_DELAY[12]PCIE.CFGERRTLPCPLHEADER[22]
CELL_W[9].IMUX_IMUX_DELAY[13]PCIE.CFGERRTLPCPLHEADER[23]
CELL_W[9].IMUX_IMUX_DELAY[14]PCIE.CFGERRTLPCPLHEADER[24]
CELL_W[9].IMUX_IMUX_DELAY[15]PCIE.CFGERRTLPCPLHEADER[25]
CELL_W[9].IMUX_IMUX_DELAY[16]PCIE.CFGDSN[46]
CELL_W[9].IMUX_IMUX_DELAY[17]PCIE.CFGDSN[47]
CELL_W[9].IMUX_IMUX_DELAY[18]PCIE.CFGDSN[48]
CELL_W[9].IMUX_IMUX_DELAY[19]PCIE.CFGDSN[49]
CELL_W[9].IMUX_IMUX_DELAY[20]PCIE.DRPDI[14]
CELL_W[9].OUT_BEL[0]PCIE.TRNFCPD[1]
CELL_W[9].OUT_BEL[1]PCIE.TRNFCPD[2]
CELL_W[9].OUT_BEL[2]PCIE.TRNFCPD[3]
CELL_W[9].OUT_BEL[3]PCIE.TRNFCPD[4]
CELL_W[9].OUT_BEL[4]PCIE.MIMTXWADDR[8]
CELL_W[9].OUT_BEL[5]PCIE.MIMTXWADDR[9]
CELL_W[9].OUT_BEL[6]PCIE.MIMTXWADDR[10]
CELL_W[9].OUT_BEL[7]PCIE.MIMTXWADDR[11]
CELL_W[9].OUT_BEL[8]PCIE.TRNRDLLPDATA[16]
CELL_W[9].OUT_BEL[9]PCIE.TRNRDLLPDATA[17]
CELL_W[9].OUT_BEL[10]PCIE.TRNRDLLPDATA[18]
CELL_W[9].OUT_BEL[11]PCIE.TRNRDLLPDATA[19]
CELL_W[9].OUT_BEL[12]PCIE.CFGMSGRECEIVEDPMPME
CELL_W[9].OUT_BEL[13]PCIE.CFGMSGRECEIVEDPMETOACK
CELL_W[9].OUT_BEL[14]PCIE.CFGMSGRECEIVEDPMETO
CELL_W[9].OUT_BEL[15]PCIE.CFGMSGRECEIVEDSETSLOTPOWERLIMIT
CELL_W[9].OUT_BEL[16]PCIE.CFGVCTCVCMAP[0]
CELL_W[9].OUT_BEL[17]PCIE.CFGVCTCVCMAP[1]
CELL_W[9].OUT_BEL[18]PCIE.CFGVCTCVCMAP[2]
CELL_W[9].OUT_BEL[19]PCIE.CFGVCTCVCMAP[3]
CELL_W[9].OUT_BEL[20]PCIE.DBGVECA[3]
CELL_W[9].OUT_BEL[21]PCIE.LNKCLKEN
CELL_W[9].OUT_BEL[22]PCIE.CFGPMCSRPOWERSTATE[1]
CELL_W[9].OUT_BEL[23]PCIE.CFGPMCSRPOWERSTATE[0]
CELL_W[10].IMUX_IMUX_DELAY[0]PCIE.MIMTXRDATA[12]
CELL_W[10].IMUX_IMUX_DELAY[1]PCIE.PIPERX2DATA[4]
CELL_W[10].IMUX_IMUX_DELAY[2]PCIE.CFGERRECRCN
CELL_W[10].IMUX_IMUX_DELAY[3]PCIE.PIPERX2DATA[0]
CELL_W[10].IMUX_IMUX_DELAY[4]PCIE.CFGERRCPLTIMEOUTN
CELL_W[10].IMUX_IMUX_DELAY[5]PCIE.PIPERX2DATA[1]
CELL_W[10].IMUX_IMUX_DELAY[6]PCIE.CFGERRCPLABORTN
CELL_W[10].IMUX_IMUX_DELAY[7]PCIE.PIPERX6DATA[2]
CELL_W[10].IMUX_IMUX_DELAY[8]PCIE.CFGERRCPLUNEXPECTN
CELL_W[10].IMUX_IMUX_DELAY[9]PCIE.PIPERX2DATA[5]
CELL_W[10].IMUX_IMUX_DELAY[10]PCIE.CFGERRTLPCPLHEADER[18]
CELL_W[10].IMUX_IMUX_DELAY[11]PCIE.PIPERX6DATA[0]
CELL_W[10].IMUX_IMUX_DELAY[12]PCIE.CFGERRTLPCPLHEADER[19]
CELL_W[10].IMUX_IMUX_DELAY[13]PCIE.PIPERX6DATA[1]
CELL_W[10].IMUX_IMUX_DELAY[14]PCIE.CFGERRTLPCPLHEADER[20]
CELL_W[10].IMUX_IMUX_DELAY[15]PCIE.PIPERX2DATA[2]
CELL_W[10].IMUX_IMUX_DELAY[16]PCIE.CFGERRTLPCPLHEADER[21]
CELL_W[10].IMUX_IMUX_DELAY[17]PCIE.PIPERX6DATA[4]
CELL_W[10].IMUX_IMUX_DELAY[19]PCIE.PIPERX2DATA[3]
CELL_W[10].IMUX_IMUX_DELAY[21]PCIE.PIPERX6DATA[5]
CELL_W[10].IMUX_IMUX_DELAY[23]PCIE.PIPERX6DATA[3]
CELL_W[10].OUT_BEL[0]PCIE.TRNFCPH[5]
CELL_W[10].OUT_BEL[1]PCIE.TRNFCPH[6]
CELL_W[10].OUT_BEL[2]PCIE.TRNFCPH[7]
CELL_W[10].OUT_BEL[3]PCIE.TRNFCPD[0]
CELL_W[10].OUT_BEL[4]PCIE.MIMTXWADDR[4]
CELL_W[10].OUT_BEL[5]PCIE.MIMTXWADDR[5]
CELL_W[10].OUT_BEL[6]PCIE.MIMTXWADDR[6]
CELL_W[10].OUT_BEL[7]PCIE.MIMTXWADDR[7]
CELL_W[10].OUT_BEL[8]PCIE.TRNRDLLPDATA[12]
CELL_W[10].OUT_BEL[9]PCIE.TRNRDLLPDATA[13]
CELL_W[10].OUT_BEL[10]PCIE.TRNRDLLPDATA[14]
CELL_W[10].OUT_BEL[11]PCIE.TRNRDLLPDATA[15]
CELL_W[10].OUT_BEL[12]PCIE.CFGMSGRECEIVEDASSERTINTC
CELL_W[10].OUT_BEL[13]PCIE.CFGMSGRECEIVEDDEASSERTINTC
CELL_W[10].OUT_BEL[14]PCIE.CFGMSGRECEIVEDASSERTINTD
CELL_W[10].OUT_BEL[15]PCIE.CFGMSGRECEIVEDDEASSERTINTD
CELL_W[10].OUT_BEL[16]PCIE.CFGDEVCONTROL2CPLTIMEOUTDIS
CELL_W[10].OUT_BEL[17]PCIE.CFGSLOTCONTROLELECTROMECHILCTLPULSE
CELL_W[10].OUT_BEL[18]PCIE.CFGAERECRCCHECKEN
CELL_W[10].OUT_BEL[19]PCIE.CFGAERECRCGENEN
CELL_W[10].OUT_BEL[20]PCIE.DRPDO[15]
CELL_W[10].OUT_BEL[21]PCIE.DBGVECA[0]
CELL_W[10].OUT_BEL[22]PCIE.DBGVECA[1]
CELL_W[10].OUT_BEL[23]PCIE.DBGVECA[2]
CELL_W[11].IMUX_IMUX_DELAY[0]PCIE.MIMTXRDATA[11]
CELL_W[11].IMUX_IMUX_DELAY[1]PCIE.PIPERX2DATA[6]
CELL_W[11].IMUX_IMUX_DELAY[2]PCIE.CFGWRENN
CELL_W[11].IMUX_IMUX_DELAY[3]PCIE.PIPERX2DATA[8]
CELL_W[11].IMUX_IMUX_DELAY[4]PCIE.CFGRDENN
CELL_W[11].IMUX_IMUX_DELAY[5]PCIE.PIPERX2DATA[9]
CELL_W[11].IMUX_IMUX_DELAY[6]PCIE.CFGERRCORN
CELL_W[11].IMUX_IMUX_DELAY[7]PCIE.PIPERX2DATA[10]
CELL_W[11].IMUX_IMUX_DELAY[8]PCIE.CFGERRURN
CELL_W[11].IMUX_IMUX_DELAY[9]PCIE.PIPERX2DATA[7]
CELL_W[11].IMUX_IMUX_DELAY[10]PCIE.CFGERRTLPCPLHEADER[14]
CELL_W[11].IMUX_IMUX_DELAY[11]PCIE.PIPERX6DATA[8]
CELL_W[11].IMUX_IMUX_DELAY[12]PCIE.CFGERRTLPCPLHEADER[15]
CELL_W[11].IMUX_IMUX_DELAY[13]PCIE.PIPERX6DATA[9]
CELL_W[11].IMUX_IMUX_DELAY[14]PCIE.CFGERRTLPCPLHEADER[16]
CELL_W[11].IMUX_IMUX_DELAY[15]PCIE.PIPERX2DATA[11]
CELL_W[11].IMUX_IMUX_DELAY[16]PCIE.CFGERRTLPCPLHEADER[17]
CELL_W[11].IMUX_IMUX_DELAY[17]PCIE.PIPERX6DATA[6]
CELL_W[11].IMUX_IMUX_DELAY[19]PCIE.PIPERX6DATA[10]
CELL_W[11].IMUX_IMUX_DELAY[21]PCIE.PIPERX6DATA[7]
CELL_W[11].IMUX_IMUX_DELAY[23]PCIE.PIPERX6DATA[11]
CELL_W[11].OUT_BEL[0]PCIE.TRNFCPH[1]
CELL_W[11].OUT_BEL[1]PCIE.TRNFCPH[2]
CELL_W[11].OUT_BEL[2]PCIE.TRNFCPH[3]
CELL_W[11].OUT_BEL[3]PCIE.TRNFCPH[4]
CELL_W[11].OUT_BEL[4]PCIE.MIMTXWADDR[0]
CELL_W[11].OUT_BEL[5]PCIE.MIMTXWADDR[1]
CELL_W[11].OUT_BEL[6]PCIE.MIMTXWADDR[2]
CELL_W[11].OUT_BEL[7]PCIE.MIMTXWADDR[3]
CELL_W[11].OUT_BEL[8]PCIE.TRNRDLLPDATA[8]
CELL_W[11].OUT_BEL[9]PCIE.TRNRDLLPDATA[9]
CELL_W[11].OUT_BEL[10]PCIE.TRNRDLLPDATA[10]
CELL_W[11].OUT_BEL[11]PCIE.TRNRDLLPDATA[11]
CELL_W[11].OUT_BEL[12]PCIE.CFGMSGRECEIVEDASSERTINTA
CELL_W[11].OUT_BEL[13]PCIE.CFGMSGRECEIVEDDEASSERTINTA
CELL_W[11].OUT_BEL[14]PCIE.CFGMSGRECEIVEDASSERTINTB
CELL_W[11].OUT_BEL[15]PCIE.CFGMSGRECEIVEDDEASSERTINTB
CELL_W[11].OUT_BEL[16]PCIE.CFGDEVCONTROL2CPLTIMEOUTVAL[0]
CELL_W[11].OUT_BEL[17]PCIE.CFGDEVCONTROL2CPLTIMEOUTVAL[1]
CELL_W[11].OUT_BEL[18]PCIE.PIPERX2POLARITY
CELL_W[11].OUT_BEL[19]PCIE.CFGDEVCONTROL2CPLTIMEOUTVAL[2]
CELL_W[11].OUT_BEL[20]PCIE.CFGDEVCONTROL2CPLTIMEOUTVAL[3]
CELL_W[11].OUT_BEL[21]PCIE.DRPDO[13]
CELL_W[11].OUT_BEL[22]PCIE.PIPERX6POLARITY
CELL_W[11].OUT_BEL[23]PCIE.DRPDO[14]
CELL_W[12].IMUX_IMUX_DELAY[0]PCIE.MIMTXRDATA[8]
CELL_W[12].IMUX_IMUX_DELAY[1]PCIE.PIPERX2CHARISK[1]
CELL_W[12].IMUX_IMUX_DELAY[2]PCIE.MIMTXRDATA[9]
CELL_W[12].IMUX_IMUX_DELAY[3]PCIE.PIPERX6DATA[13]
CELL_W[12].IMUX_IMUX_DELAY[4]PCIE.MIMTXRDATA[10]
CELL_W[12].IMUX_IMUX_DELAY[5]PCIE.PIPERX2DATA[12]
CELL_W[12].IMUX_IMUX_DELAY[6]PCIE.CFGDWADDR[8]
CELL_W[12].IMUX_IMUX_DELAY[7]PCIE.PIPERX2DATA[13]
CELL_W[12].IMUX_IMUX_DELAY[8]PCIE.CFGDWADDR[9]
CELL_W[12].IMUX_IMUX_DELAY[9]PCIE.PIPERX2DATA[15]
CELL_W[12].IMUX_IMUX_DELAY[10]PCIE.CFGWRRW1CASRWN
CELL_W[12].IMUX_IMUX_DELAY[11]PCIE.PIPERX2DATA[14]
CELL_W[12].IMUX_IMUX_DELAY[12]PCIE.CFGWRREADONLYN
CELL_W[12].IMUX_IMUX_DELAY[13]PCIE.PIPERX6DATA[12]
CELL_W[12].IMUX_IMUX_DELAY[14]PCIE.CFGERRTLPCPLHEADER[10]
CELL_W[12].IMUX_IMUX_DELAY[15]PCIE.PIPERX6DATA[14]
CELL_W[12].IMUX_IMUX_DELAY[16]PCIE.CFGERRTLPCPLHEADER[11]
CELL_W[12].IMUX_IMUX_DELAY[17]PCIE.PIPERX6CHARISK[1]
CELL_W[12].IMUX_IMUX_DELAY[18]PCIE.CFGERRTLPCPLHEADER[12]
CELL_W[12].IMUX_IMUX_DELAY[19]PCIE.CFGERRTLPCPLHEADER[13]
CELL_W[12].IMUX_IMUX_DELAY[21]PCIE.PIPERX6DATA[15]
CELL_W[12].OUT_BEL[0]PCIE.TRNRBARHITN[5]
CELL_W[12].OUT_BEL[1]PCIE.TRNRBARHITN[6]
CELL_W[12].OUT_BEL[2]PCIE.TRNLNKUPN
CELL_W[12].OUT_BEL[3]PCIE.TRNFCPH[0]
CELL_W[12].OUT_BEL[4]PCIE.MIMTXWDATA[65]
CELL_W[12].OUT_BEL[5]PCIE.MIMTXWDATA[66]
CELL_W[12].OUT_BEL[6]PCIE.MIMTXWDATA[67]
CELL_W[12].OUT_BEL[7]PCIE.MIMTXWDATA[68]
CELL_W[12].OUT_BEL[8]PCIE.TRNRDLLPDATA[4]
CELL_W[12].OUT_BEL[9]PCIE.TRNRDLLPDATA[5]
CELL_W[12].OUT_BEL[10]PCIE.TRNRDLLPDATA[6]
CELL_W[12].OUT_BEL[11]PCIE.TRNRDLLPDATA[7]
CELL_W[12].OUT_BEL[12]PCIE.CFGMSGDATA[15]
CELL_W[12].OUT_BEL[13]PCIE.CFGMSGRECEIVEDERRCOR
CELL_W[12].OUT_BEL[14]PCIE.CFGMSGRECEIVEDERRNONFATAL
CELL_W[12].OUT_BEL[15]PCIE.CFGMSGRECEIVEDERRFATAL
CELL_W[12].OUT_BEL[16]PCIE.CFGLINKCONTROLCLOCKPMEN
CELL_W[12].OUT_BEL[17]PCIE.CFGLINKCONTROLHWAUTOWIDTHDIS
CELL_W[12].OUT_BEL[18]PCIE.CFGLINKCONTROLBANDWIDTHINTEN
CELL_W[12].OUT_BEL[19]PCIE.CFGLINKCONTROLAUTOBANDWIDTHINTEN
CELL_W[12].OUT_BEL[20]PCIE.DRPDO[12]
CELL_W[12].OUT_BEL[21]PCIE.CFGPMCSRPMEEN
CELL_W[12].OUT_BEL[22]PCIE.DBGVECB[47]
CELL_W[12].OUT_BEL[23]PCIE.DBGVECB[48]
CELL_W[13].IMUX_IMUX_DELAY[0]PCIE.MIMTXRDATA[4]
CELL_W[13].IMUX_IMUX_DELAY[1]PCIE.PIPERX6CHANISALIGNED
CELL_W[13].IMUX_IMUX_DELAY[2]PCIE.MIMTXRDATA[5]
CELL_W[13].IMUX_IMUX_DELAY[3]PCIE.MIMTXRDATA[6]
CELL_W[13].IMUX_IMUX_DELAY[4]PCIE.MIMTXRDATA[7]
CELL_W[13].IMUX_IMUX_DELAY[5]PCIE.MIMRXRDATA[66]
CELL_W[13].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[67]
CELL_W[13].IMUX_IMUX_DELAY[7]PCIE.TRNTDLLPDATA[0]
CELL_W[13].IMUX_IMUX_DELAY[8]PCIE.TRNTDLLPDATA[1]
CELL_W[13].IMUX_IMUX_DELAY[9]PCIE.CFGDWADDR[4]
CELL_W[13].IMUX_IMUX_DELAY[10]PCIE.CFGDWADDR[5]
CELL_W[13].IMUX_IMUX_DELAY[11]PCIE.CFGDWADDR[6]
CELL_W[13].IMUX_IMUX_DELAY[12]PCIE.CFGDWADDR[7]
CELL_W[13].IMUX_IMUX_DELAY[13]PCIE.CFGERRTLPCPLHEADER[6]
CELL_W[13].IMUX_IMUX_DELAY[14]PCIE.CFGERRTLPCPLHEADER[7]
CELL_W[13].IMUX_IMUX_DELAY[15]PCIE.PIPERX6CHARISK[0]
CELL_W[13].IMUX_IMUX_DELAY[16]PCIE.CFGERRTLPCPLHEADER[8]
CELL_W[13].IMUX_IMUX_DELAY[17]PCIE.CFGERRTLPCPLHEADER[9]
CELL_W[13].IMUX_IMUX_DELAY[18]PCIE.CFGDSN[45]
CELL_W[13].IMUX_IMUX_DELAY[21]PCIE.PIPERX2CHANISALIGNED
CELL_W[13].IMUX_IMUX_DELAY[23]PCIE.PIPERX2CHARISK[0]
CELL_W[13].OUT_BEL[0]PCIE.TRNRBARHITN[1]
CELL_W[13].OUT_BEL[1]PCIE.TRNRBARHITN[2]
CELL_W[13].OUT_BEL[2]PCIE.TRNRBARHITN[3]
CELL_W[13].OUT_BEL[3]PCIE.TRNRBARHITN[4]
CELL_W[13].OUT_BEL[4]PCIE.MIMTXWDATA[61]
CELL_W[13].OUT_BEL[5]PCIE.MIMTXWDATA[62]
CELL_W[13].OUT_BEL[6]PCIE.MIMTXWDATA[63]
CELL_W[13].OUT_BEL[7]PCIE.MIMTXWDATA[64]
CELL_W[13].OUT_BEL[8]PCIE.TRNRDLLPDATA[0]
CELL_W[13].OUT_BEL[9]PCIE.TRNRDLLPDATA[1]
CELL_W[13].OUT_BEL[10]PCIE.TRNRDLLPDATA[2]
CELL_W[13].OUT_BEL[11]PCIE.TRNRDLLPDATA[3]
CELL_W[13].OUT_BEL[12]PCIE.CFGMSGDATA[11]
CELL_W[13].OUT_BEL[13]PCIE.CFGMSGDATA[12]
CELL_W[13].OUT_BEL[14]PCIE.CFGMSGDATA[13]
CELL_W[13].OUT_BEL[15]PCIE.CFGMSGDATA[14]
CELL_W[13].OUT_BEL[16]PCIE.PIPETXDEEMPH
CELL_W[13].OUT_BEL[17]PCIE.CFGLINKCONTROLCOMMONCLOCK
CELL_W[13].OUT_BEL[18]PCIE.CFGLINKCONTROLEXTENDEDSYNC
CELL_W[13].OUT_BEL[19]PCIE.XILUNCONNOUT[3]
CELL_W[13].OUT_BEL[20]PCIE.CFGPMCSRPMESTATUS
CELL_W[13].OUT_BEL[21]PCIE.DBGVECB[44]
CELL_W[13].OUT_BEL[22]PCIE.DBGVECB[45]
CELL_W[13].OUT_BEL[23]PCIE.DBGVECB[46]
CELL_W[14].IMUX_IMUX_DELAY[0]PCIE.MIMTXRDATA[0]
CELL_W[14].IMUX_IMUX_DELAY[1]PCIE.PIPERX6STATUS[2]
CELL_W[14].IMUX_IMUX_DELAY[2]PCIE.MIMTXRDATA[1]
CELL_W[14].IMUX_IMUX_DELAY[3]PCIE.PIPERX6STATUS[0]
CELL_W[14].IMUX_IMUX_DELAY[4]PCIE.MIMTXRDATA[2]
CELL_W[14].IMUX_IMUX_DELAY[5]PCIE.MIMTXRDATA[3]
CELL_W[14].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[62]
CELL_W[14].IMUX_IMUX_DELAY[7]PCIE.PIPERX6STATUS[1]
CELL_W[14].IMUX_IMUX_DELAY[8]PCIE.MIMRXRDATA[63]
CELL_W[14].IMUX_IMUX_DELAY[9]PCIE.MIMRXRDATA[64]
CELL_W[14].IMUX_IMUX_DELAY[10]PCIE.MIMRXRDATA[65]
CELL_W[14].IMUX_IMUX_DELAY[11]PCIE.PIPERX2PHYSTATUS
CELL_W[14].IMUX_IMUX_DELAY[12]PCIE.PMVDIVIDE[1]
CELL_W[14].IMUX_IMUX_DELAY[13]PCIE.PLTRANSMITHOTRST
CELL_W[14].IMUX_IMUX_DELAY[14]PCIE.CFGDI[0]
CELL_W[14].IMUX_IMUX_DELAY[15]PCIE.PIPERX6PHYSTATUS
CELL_W[14].IMUX_IMUX_DELAY[16]PCIE.CFGDI[1]
CELL_W[14].IMUX_IMUX_DELAY[17]PCIE.CFGDWADDR[2]
CELL_W[14].IMUX_IMUX_DELAY[18]PCIE.CFGDWADDR[3]
CELL_W[14].IMUX_IMUX_DELAY[19]PCIE.PIPERX2STATUS[1]
CELL_W[14].IMUX_IMUX_DELAY[21]PCIE.PIPERX2STATUS[2]
CELL_W[14].IMUX_IMUX_DELAY[23]PCIE.PIPERX2STATUS[0]
CELL_W[14].OUT_BEL[0]PCIE.TRNRSRCDSCN
CELL_W[14].OUT_BEL[1]PCIE.PIPETX2ELECIDLE
CELL_W[14].OUT_BEL[2]PCIE.TRNRECRCERRN
CELL_W[14].OUT_BEL[3]PCIE.TRNRERRFWDN
CELL_W[14].OUT_BEL[4]PCIE.TRNRBARHITN[0]
CELL_W[14].OUT_BEL[5]PCIE.PIPETX6ELECIDLE
CELL_W[14].OUT_BEL[6]PCIE.MIMTXWDATA[57]
CELL_W[14].OUT_BEL[7]PCIE.MIMTXWDATA[58]
CELL_W[14].OUT_BEL[8]PCIE.MIMTXWDATA[59]
CELL_W[14].OUT_BEL[9]PCIE.MIMTXWDATA[60]
CELL_W[14].OUT_BEL[10]PCIE.TRNTDLLPDSTRDYN
CELL_W[14].OUT_BEL[11]PCIE.CFGMSGDATA[8]
CELL_W[14].OUT_BEL[12]PCIE.CFGMSGDATA[9]
CELL_W[14].OUT_BEL[13]PCIE.CFGMSGDATA[10]
CELL_W[14].OUT_BEL[14]PCIE.XILUNCONNOUT[1]
CELL_W[14].OUT_BEL[15]PCIE.PIPETXRCVRDET
CELL_W[14].OUT_BEL[16]PCIE.XILUNCONNOUT[2]
CELL_W[14].OUT_BEL[17]PCIE.PIPETX6POWERDOWN[0]
CELL_W[14].OUT_BEL[18]PCIE.DBGVECB[41]
CELL_W[14].OUT_BEL[19]PCIE.PIPETX6POWERDOWN[1]
CELL_W[14].OUT_BEL[20]PCIE.DBGVECB[42]
CELL_W[14].OUT_BEL[21]PCIE.PIPETX2POWERDOWN[0]
CELL_W[14].OUT_BEL[22]PCIE.DBGVECB[43]
CELL_W[14].OUT_BEL[23]PCIE.PIPETX2POWERDOWN[1]
CELL_W[15].IMUX_IMUX_DELAY[0]PCIE.TRNRNPOKN
CELL_W[15].IMUX_IMUX_DELAY[1]PCIE.TRNFCSEL[0]
CELL_W[15].IMUX_IMUX_DELAY[2]PCIE.TRNFCSEL[1]
CELL_W[15].IMUX_IMUX_DELAY[3]PCIE.TRNFCSEL[2]
CELL_W[15].IMUX_IMUX_DELAY[4]PCIE.MIMRXRDATA[58]
CELL_W[15].IMUX_IMUX_DELAY[5]PCIE.PIPERX6ELECIDLE
CELL_W[15].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[59]
CELL_W[15].IMUX_IMUX_DELAY[7]PCIE.MIMRXRDATA[60]
CELL_W[15].IMUX_IMUX_DELAY[8]PCIE.MIMRXRDATA[61]
CELL_W[15].IMUX_IMUX_DELAY[9]PCIE.PMVDIVIDE[0]
CELL_W[15].IMUX_IMUX_DELAY[10]PCIE.CFGDI[2]
CELL_W[15].IMUX_IMUX_DELAY[11]PCIE.PIPERX6VALID
CELL_W[15].IMUX_IMUX_DELAY[12]PCIE.CFGDI[3]
CELL_W[15].IMUX_IMUX_DELAY[13]PCIE.CFGDI[4]
CELL_W[15].IMUX_IMUX_DELAY[14]PCIE.CFGDI[5]
CELL_W[15].IMUX_IMUX_DELAY[15]PCIE.CFGBYTEENN[2]
CELL_W[15].IMUX_IMUX_DELAY[16]PCIE.CFGBYTEENN[3]
CELL_W[15].IMUX_IMUX_DELAY[17]PCIE.CFGDWADDR[0]
CELL_W[15].IMUX_IMUX_DELAY[18]PCIE.CFGDWADDR[1]
CELL_W[15].IMUX_IMUX_DELAY[19]PCIE.PIPERX2VALID
CELL_W[15].IMUX_IMUX_DELAY[20]PCIE.CFGERRTLPCPLHEADER[5]
CELL_W[15].IMUX_IMUX_DELAY[21]PCIE.PIPERX2ELECIDLE
CELL_W[15].OUT_BEL[0]PCIE.TRNRREMN
CELL_W[15].OUT_BEL[1]PCIE.TRNRSOFN
CELL_W[15].OUT_BEL[2]PCIE.TRNREOFN
CELL_W[15].OUT_BEL[3]PCIE.TRNRSRCRDYN
CELL_W[15].OUT_BEL[4]PCIE.MIMTXWDATA[53]
CELL_W[15].OUT_BEL[5]PCIE.MIMTXWDATA[54]
CELL_W[15].OUT_BEL[6]PCIE.MIMTXWDATA[55]
CELL_W[15].OUT_BEL[7]PCIE.MIMTXWDATA[56]
CELL_W[15].OUT_BEL[8]PCIE.CFGMSGDATA[4]
CELL_W[15].OUT_BEL[9]PCIE.CFGMSGDATA[5]
CELL_W[15].OUT_BEL[10]PCIE.CFGMSGDATA[6]
CELL_W[15].OUT_BEL[11]PCIE.CFGMSGDATA[7]
CELL_W[15].OUT_BEL[12]PCIE.CFGLINKCONTROLRCB
CELL_W[15].OUT_BEL[13]PCIE.CFGLINKCONTROLLINKDISABLE
CELL_W[15].OUT_BEL[14]PCIE.CFGLINKCONTROLRETRAINLINK
CELL_W[15].OUT_BEL[15]PCIE.XILUNCONNOUT[0]
CELL_W[15].OUT_BEL[16]PCIE.PIPETX2COMPLIANCE
CELL_W[15].OUT_BEL[17]PCIE.DBGVECB[39]
CELL_W[15].OUT_BEL[18]PCIE.PIPETX2CHARISK[0]
CELL_W[15].OUT_BEL[19]PCIE.PIPETX6CHARISK[1]
CELL_W[15].OUT_BEL[20]PCIE.PIPETX6COMPLIANCE
CELL_W[15].OUT_BEL[21]PCIE.DBGVECB[40]
CELL_W[15].OUT_BEL[22]PCIE.PIPETX6CHARISK[0]
CELL_W[15].OUT_BEL[23]PCIE.PIPETX2CHARISK[1]
CELL_W[16].IMUX_IMUX_DELAY[0]PCIE.TRNTECRCGENN
CELL_W[16].IMUX_IMUX_DELAY[1]PCIE.TRNTSTRN
CELL_W[16].IMUX_IMUX_DELAY[2]PCIE.TRNTCFGGNTN
CELL_W[16].IMUX_IMUX_DELAY[3]PCIE.TRNRDSTRDYN
CELL_W[16].IMUX_IMUX_DELAY[4]PCIE.MIMRXRDATA[54]
CELL_W[16].IMUX_IMUX_DELAY[5]PCIE.MIMRXRDATA[55]
CELL_W[16].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[56]
CELL_W[16].IMUX_IMUX_DELAY[7]PCIE.MIMRXRDATA[57]
CELL_W[16].IMUX_IMUX_DELAY[8]PCIE.PMVSELECT[2]
CELL_W[16].IMUX_IMUX_DELAY[9]PCIE.CFGDI[6]
CELL_W[16].IMUX_IMUX_DELAY[10]PCIE.CFGDI[7]
CELL_W[16].IMUX_IMUX_DELAY[11]PCIE.CFGDI[8]
CELL_W[16].IMUX_IMUX_DELAY[12]PCIE.CFGDI[9]
CELL_W[16].IMUX_IMUX_DELAY[13]PCIE.CFGDI[30]
CELL_W[16].IMUX_IMUX_DELAY[14]PCIE.CFGDI[31]
CELL_W[16].IMUX_IMUX_DELAY[15]PCIE.CFGBYTEENN[0]
CELL_W[16].IMUX_IMUX_DELAY[16]PCIE.CFGBYTEENN[1]
CELL_W[16].IMUX_IMUX_DELAY[17]PCIE.CFGERRTLPCPLHEADER[1]
CELL_W[16].IMUX_IMUX_DELAY[18]PCIE.CFGERRTLPCPLHEADER[2]
CELL_W[16].IMUX_IMUX_DELAY[19]PCIE.CFGERRTLPCPLHEADER[3]
CELL_W[16].IMUX_IMUX_DELAY[20]PCIE.CFGERRTLPCPLHEADER[4]
CELL_W[16].IMUX_IMUX_DELAY[21]PCIE.CFGDSN[44]
CELL_W[16].OUT_BEL[0]PCIE.TRNRD[60]
CELL_W[16].OUT_BEL[1]PCIE.TRNRD[61]
CELL_W[16].OUT_BEL[2]PCIE.PIPETX6DATA[13]
CELL_W[16].OUT_BEL[3]PCIE.TRNRD[62]
CELL_W[16].OUT_BEL[4]PCIE.TRNRD[63]
CELL_W[16].OUT_BEL[5]PCIE.CFGMSGDATA[0]
CELL_W[16].OUT_BEL[6]PCIE.PIPETX2DATA[13]
CELL_W[16].OUT_BEL[7]PCIE.CFGMSGDATA[1]
CELL_W[16].OUT_BEL[8]PCIE.CFGMSGDATA[2]
CELL_W[16].OUT_BEL[9]PCIE.PIPETXRESET
CELL_W[16].OUT_BEL[10]PCIE.CFGMSGDATA[3]
CELL_W[16].OUT_BEL[11]PCIE.CFGLINKCONTROLASPMCONTROL[1]
CELL_W[16].OUT_BEL[12]PCIE.PLDBGVEC[10]
CELL_W[16].OUT_BEL[13]PCIE.PLDBGVEC[11]
CELL_W[16].OUT_BEL[14]PCIE.DBGVECB[36]
CELL_W[16].OUT_BEL[15]PCIE.DBGVECB[37]
CELL_W[16].OUT_BEL[16]PCIE.PIPETX2DATA[12]
CELL_W[16].OUT_BEL[17]PCIE.PIPETX6DATA[15]
CELL_W[16].OUT_BEL[18]PCIE.PIPETXRATE
CELL_W[16].OUT_BEL[19]PCIE.PIPETX6DATA[14]
CELL_W[16].OUT_BEL[20]PCIE.PIPETX6DATA[12]
CELL_W[16].OUT_BEL[21]PCIE.PIPETX2DATA[15]
CELL_W[16].OUT_BEL[22]PCIE.DBGVECB[38]
CELL_W[16].OUT_BEL[23]PCIE.PIPETX2DATA[14]
CELL_W[17].IMUX_IMUX_DELAY[0]PCIE.TRNTEOFN
CELL_W[17].IMUX_IMUX_DELAY[1]PCIE.TRNTSRCRDYN
CELL_W[17].IMUX_IMUX_DELAY[2]PCIE.TRNTSRCDSCN
CELL_W[17].IMUX_IMUX_DELAY[3]PCIE.TRNTERRFWDN
CELL_W[17].IMUX_IMUX_DELAY[4]PCIE.MIMRXRDATA[50]
CELL_W[17].IMUX_IMUX_DELAY[5]PCIE.MIMRXRDATA[51]
CELL_W[17].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[52]
CELL_W[17].IMUX_IMUX_DELAY[7]PCIE.MIMRXRDATA[53]
CELL_W[17].IMUX_IMUX_DELAY[8]PCIE.PMVSELECT[1]
CELL_W[17].IMUX_IMUX_DELAY[9]PCIE.CFGDI[10]
CELL_W[17].IMUX_IMUX_DELAY[10]PCIE.CFGDI[11]
CELL_W[17].IMUX_IMUX_DELAY[11]PCIE.CFGDI[12]
CELL_W[17].IMUX_IMUX_DELAY[12]PCIE.CFGDI[13]
CELL_W[17].IMUX_IMUX_DELAY[13]PCIE.CFGDI[26]
CELL_W[17].IMUX_IMUX_DELAY[14]PCIE.CFGDI[27]
CELL_W[17].IMUX_IMUX_DELAY[15]PCIE.CFGDI[28]
CELL_W[17].IMUX_IMUX_DELAY[16]PCIE.CFGDI[29]
CELL_W[17].IMUX_IMUX_DELAY[17]PCIE.CFGERRAERHEADERLOG[125]
CELL_W[17].IMUX_IMUX_DELAY[18]PCIE.CFGERRAERHEADERLOG[126]
CELL_W[17].IMUX_IMUX_DELAY[19]PCIE.CFGERRAERHEADERLOG[127]
CELL_W[17].IMUX_IMUX_DELAY[20]PCIE.CFGERRTLPCPLHEADER[0]
CELL_W[17].IMUX_IMUX_DELAY[21]PCIE.CFGDSN[43]
CELL_W[17].OUT_BEL[0]PCIE.TRNRD[58]
CELL_W[17].OUT_BEL[1]PCIE.PIPETX2DATA[11]
CELL_W[17].OUT_BEL[2]PCIE.PIPETX6DATA[8]
CELL_W[17].OUT_BEL[3]PCIE.TRNRD[59]
CELL_W[17].OUT_BEL[4]PCIE.CFGINTERRUPTDO[7]
CELL_W[17].OUT_BEL[5]PCIE.PIPETX6DATA[11]
CELL_W[17].OUT_BEL[6]PCIE.PIPETX2DATA[8]
CELL_W[17].OUT_BEL[7]PCIE.CFGINTERRUPTMSIXENABLE
CELL_W[17].OUT_BEL[8]PCIE.CFGINTERRUPTMSIXFM
CELL_W[17].OUT_BEL[9]PCIE.CFGMSGRECEIVED
CELL_W[17].OUT_BEL[10]PCIE.CFGLINKCONTROLASPMCONTROL[0]
CELL_W[17].OUT_BEL[11]PCIE.PLDBGVEC[8]
CELL_W[17].OUT_BEL[12]PCIE.PLDBGVEC[9]
CELL_W[17].OUT_BEL[13]PCIE.DBGVECB[33]
CELL_W[17].OUT_BEL[14]PCIE.DBGVECB[34]
CELL_W[17].OUT_BEL[15]PCIE.DBGVECB[35]
CELL_W[17].OUT_BEL[16]PCIE.PIPETX2DATA[7]
CELL_W[17].OUT_BEL[17]PCIE.PIPETX6DATA[10]
CELL_W[17].OUT_BEL[18]PCIE.PIPETX2DATA[6]
CELL_W[17].OUT_BEL[19]PCIE.PIPETX6DATA[9]
CELL_W[17].OUT_BEL[20]PCIE.PIPETX6DATA[7]
CELL_W[17].OUT_BEL[21]PCIE.PIPETX2DATA[10]
CELL_W[17].OUT_BEL[22]PCIE.PIPETX6DATA[6]
CELL_W[17].OUT_BEL[23]PCIE.PIPETX2DATA[9]
CELL_W[18].IMUX_IMUX_DELAY[0]PCIE.TRNTD[62]
CELL_W[18].IMUX_IMUX_DELAY[1]PCIE.TRNTD[63]
CELL_W[18].IMUX_IMUX_DELAY[2]PCIE.TRNTREMN
CELL_W[18].IMUX_IMUX_DELAY[3]PCIE.TRNTSOFN
CELL_W[18].IMUX_IMUX_DELAY[4]PCIE.MIMRXRDATA[46]
CELL_W[18].IMUX_IMUX_DELAY[5]PCIE.MIMRXRDATA[47]
CELL_W[18].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[48]
CELL_W[18].IMUX_IMUX_DELAY[7]PCIE.MIMRXRDATA[49]
CELL_W[18].IMUX_IMUX_DELAY[8]PCIE.PMVSELECT[0]
CELL_W[18].IMUX_IMUX_DELAY[9]PCIE.CFGDI[14]
CELL_W[18].IMUX_IMUX_DELAY[10]PCIE.CFGDI[15]
CELL_W[18].IMUX_IMUX_DELAY[11]PCIE.CFGDI[16]
CELL_W[18].IMUX_IMUX_DELAY[12]PCIE.CFGDI[17]
CELL_W[18].IMUX_IMUX_DELAY[13]PCIE.CFGDI[22]
CELL_W[18].IMUX_IMUX_DELAY[14]PCIE.CFGDI[23]
CELL_W[18].IMUX_IMUX_DELAY[15]PCIE.CFGDI[24]
CELL_W[18].IMUX_IMUX_DELAY[16]PCIE.CFGDI[25]
CELL_W[18].IMUX_IMUX_DELAY[17]PCIE.CFGERRAERHEADERLOG[121]
CELL_W[18].IMUX_IMUX_DELAY[18]PCIE.CFGERRAERHEADERLOG[122]
CELL_W[18].IMUX_IMUX_DELAY[19]PCIE.CFGERRAERHEADERLOG[123]
CELL_W[18].IMUX_IMUX_DELAY[20]PCIE.CFGERRAERHEADERLOG[124]
CELL_W[18].IMUX_IMUX_DELAY[21]PCIE.CFGDSN[42]
CELL_W[18].OUT_BEL[0]PCIE.TRNRD[56]
CELL_W[18].OUT_BEL[1]PCIE.PIPETX2DATA[3]
CELL_W[18].OUT_BEL[2]PCIE.PIPETX6DATA[4]
CELL_W[18].OUT_BEL[3]PCIE.TRNRD[57]
CELL_W[18].OUT_BEL[4]PCIE.CFGINTERRUPTDO[3]
CELL_W[18].OUT_BEL[5]PCIE.PIPETX6DATA[3]
CELL_W[18].OUT_BEL[6]PCIE.PIPETX2DATA[4]
CELL_W[18].OUT_BEL[7]PCIE.MIMRXRCE
CELL_W[18].OUT_BEL[8]PCIE.CFGINTERRUPTDO[4]
CELL_W[18].OUT_BEL[9]PCIE.CFGINTERRUPTDO[5]
CELL_W[18].OUT_BEL[10]PCIE.CFGINTERRUPTDO[6]
CELL_W[18].OUT_BEL[11]PCIE.CFGLINKSTATUSAUTOBANDWIDTHSTATUS
CELL_W[18].OUT_BEL[12]PCIE.PLDBGVEC[6]
CELL_W[18].OUT_BEL[13]PCIE.PLDBGVEC[7]
CELL_W[18].OUT_BEL[14]PCIE.DBGVECB[31]
CELL_W[18].OUT_BEL[15]PCIE.DBGVECB[32]
CELL_W[18].OUT_BEL[16]PCIE.PIPETX2DATA[0]
CELL_W[18].OUT_BEL[17]PCIE.PIPETX6DATA[1]
CELL_W[18].OUT_BEL[18]PCIE.PIPETX2DATA[5]
CELL_W[18].OUT_BEL[19]PCIE.PIPETX6DATA[2]
CELL_W[18].OUT_BEL[20]PCIE.PIPETX6DATA[0]
CELL_W[18].OUT_BEL[21]PCIE.PIPETX2DATA[1]
CELL_W[18].OUT_BEL[22]PCIE.PIPETX6DATA[5]
CELL_W[18].OUT_BEL[23]PCIE.PIPETX2DATA[2]
CELL_W[19].IMUX_IMUX_DELAY[0]PCIE.TRNTD[58]
CELL_W[19].IMUX_IMUX_DELAY[1]PCIE.TRNTD[59]
CELL_W[19].IMUX_IMUX_DELAY[2]PCIE.TRNTD[60]
CELL_W[19].IMUX_IMUX_DELAY[3]PCIE.TRNTD[61]
CELL_W[19].IMUX_IMUX_DELAY[4]PCIE.MIMRXRDATA[42]
CELL_W[19].IMUX_IMUX_DELAY[5]PCIE.MIMRXRDATA[43]
CELL_W[19].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[44]
CELL_W[19].IMUX_IMUX_DELAY[7]PCIE.MIMRXRDATA[45]
CELL_W[19].IMUX_IMUX_DELAY[8]PCIE.PMVENABLEN
CELL_W[19].IMUX_IMUX_DELAY[9]PCIE.CFGDI[18]
CELL_W[19].IMUX_IMUX_DELAY[10]PCIE.CFGDI[19]
CELL_W[19].IMUX_IMUX_DELAY[11]PCIE.CFGDI[20]
CELL_W[19].IMUX_IMUX_DELAY[12]PCIE.CFGDI[21]
CELL_W[19].IMUX_IMUX_DELAY[13]PCIE.CFGERRAERHEADERLOG[117]
CELL_W[19].IMUX_IMUX_DELAY[14]PCIE.CFGERRAERHEADERLOG[118]
CELL_W[19].IMUX_IMUX_DELAY[15]PCIE.CFGERRAERHEADERLOG[119]
CELL_W[19].IMUX_IMUX_DELAY[16]PCIE.CFGERRAERHEADERLOG[120]
CELL_W[19].IMUX_IMUX_DELAY[17]PCIE.CFGDSN[38]
CELL_W[19].IMUX_IMUX_DELAY[18]PCIE.CFGDSN[39]
CELL_W[19].IMUX_IMUX_DELAY[19]PCIE.CFGDSN[40]
CELL_W[19].IMUX_IMUX_DELAY[20]PCIE.CFGDSN[41]
CELL_W[19].IMUX_IMUX_DELAY[21]PCIE.DRPDI[13]
CELL_W[19].OUT_BEL[0]PCIE.TRNRD[52]
CELL_W[19].OUT_BEL[1]PCIE.TRNRD[53]
CELL_W[19].OUT_BEL[2]PCIE.TRNRD[54]
CELL_W[19].OUT_BEL[3]PCIE.TRNRD[55]
CELL_W[19].OUT_BEL[4]PCIE.MIMTXWDATA[49]
CELL_W[19].OUT_BEL[5]PCIE.MIMTXWDATA[50]
CELL_W[19].OUT_BEL[6]PCIE.MIMTXWDATA[51]
CELL_W[19].OUT_BEL[7]PCIE.MIMTXWDATA[52]
CELL_W[19].OUT_BEL[8]PCIE.MIMRXRADDR[10]
CELL_W[19].OUT_BEL[9]PCIE.MIMRXRADDR[11]
CELL_W[19].OUT_BEL[10]PCIE.MIMRXRADDR[12]
CELL_W[19].OUT_BEL[11]PCIE.MIMRXREN
CELL_W[19].OUT_BEL[12]PCIE.CFGINTERRUPTMSIENABLE
CELL_W[19].OUT_BEL[13]PCIE.CFGINTERRUPTDO[0]
CELL_W[19].OUT_BEL[14]PCIE.CFGINTERRUPTDO[1]
CELL_W[19].OUT_BEL[15]PCIE.CFGINTERRUPTDO[2]
CELL_W[19].OUT_BEL[16]PCIE.CFGLINKSTATUSNEGOTIATEDWIDTH[3]
CELL_W[19].OUT_BEL[17]PCIE.CFGLINKSTATUSLINKTRAINING
CELL_W[19].OUT_BEL[18]PCIE.CFGLINKSTATUSDLLACTIVE
CELL_W[19].OUT_BEL[19]PCIE.CFGLINKSTATUSBANDWITHSTATUS
CELL_W[19].OUT_BEL[20]PCIE.DRPDO[10]
CELL_W[19].OUT_BEL[21]PCIE.DRPDO[11]
CELL_W[19].OUT_BEL[22]PCIE.PLDBGVEC[5]
CELL_W[19].OUT_BEL[23]PCIE.DBGVECB[30]
CELL_E[0].IMUX_CLK[0]PCIE.USERCLKPREBUF
CELL_E[0].IMUX_CTRL[0]PCIE.SYSRSTN
CELL_E[0].IMUX_CTRL[1]PCIE.CMRSTN
CELL_E[0].IMUX_IMUX_DELAY[0]PCIE.PLDIRECTEDLINKCHANGE[0]
CELL_E[0].IMUX_IMUX_DELAY[1]PCIE.PIPERX1DATA[4]
CELL_E[0].IMUX_IMUX_DELAY[2]PCIE.CFGERRAERHEADERLOG[37]
CELL_E[0].IMUX_IMUX_DELAY[3]PCIE.PIPERX1DATA[0]
CELL_E[0].IMUX_IMUX_DELAY[4]PCIE.CFGERRAERHEADERLOG[38]
CELL_E[0].IMUX_IMUX_DELAY[5]PCIE.PIPERX1DATA[1]
CELL_E[0].IMUX_IMUX_DELAY[6]PCIE.CFGERRAERHEADERLOG[39]
CELL_E[0].IMUX_IMUX_DELAY[7]PCIE.PIPERX5DATA[2]
CELL_E[0].IMUX_IMUX_DELAY[8]PCIE.CFGERRAERHEADERLOG[40]
CELL_E[0].IMUX_IMUX_DELAY[9]PCIE.PIPERX1DATA[5]
CELL_E[0].IMUX_IMUX_DELAY[10]PCIE.CFGDSBUSNUMBER[4]
CELL_E[0].IMUX_IMUX_DELAY[11]PCIE.PIPERX5DATA[0]
CELL_E[0].IMUX_IMUX_DELAY[12]PCIE.CFGDSBUSNUMBER[5]
CELL_E[0].IMUX_IMUX_DELAY[13]PCIE.PIPERX5DATA[1]
CELL_E[0].IMUX_IMUX_DELAY[14]PCIE.CFGDSBUSNUMBER[6]
CELL_E[0].IMUX_IMUX_DELAY[15]PCIE.PIPERX1DATA[2]
CELL_E[0].IMUX_IMUX_DELAY[16]PCIE.CFGDSBUSNUMBER[7]
CELL_E[0].IMUX_IMUX_DELAY[17]PCIE.PIPERX5DATA[4]
CELL_E[0].IMUX_IMUX_DELAY[19]PCIE.PIPERX1DATA[3]
CELL_E[0].IMUX_IMUX_DELAY[21]PCIE.PIPERX5DATA[5]
CELL_E[0].IMUX_IMUX_DELAY[23]PCIE.PIPERX5DATA[3]
CELL_E[0].OUT_BEL[0]PCIE.PLSELLNKRATE
CELL_E[0].OUT_BEL[1]PCIE.PLSELLNKWIDTH[0]
CELL_E[0].OUT_BEL[2]PCIE.PLSELLNKWIDTH[1]
CELL_E[0].OUT_BEL[3]PCIE.PLLTSSMSTATE[0]
CELL_E[0].OUT_BEL[4]PCIE.PLLTSSMSTATE[1]
CELL_E[0].OUT_BEL[5]PCIE.PLLTSSMSTATE[2]
CELL_E[0].OUT_BEL[6]PCIE.PLLTSSMSTATE[3]
CELL_E[0].OUT_BEL[7]PCIE.PLLTSSMSTATE[4]
CELL_E[0].OUT_BEL[8]PCIE.PLLTSSMSTATE[5]
CELL_E[0].OUT_BEL[9]PCIE.PLLANEREVERSALMODE[0]
CELL_E[0].OUT_BEL[10]PCIE.PLLANEREVERSALMODE[1]
CELL_E[0].OUT_BEL[11]PCIE.PLPHYLNKUPN
CELL_E[0].OUT_BEL[12]PCIE.PLTXPMSTATE[0]
CELL_E[0].OUT_BEL[13]PCIE.PLTXPMSTATE[1]
CELL_E[0].OUT_BEL[14]PCIE.PLTXPMSTATE[2]
CELL_E[0].OUT_BEL[15]PCIE.PLRXPMSTATE[0]
CELL_E[0].OUT_BEL[16]PCIE.TRNFCCPLD[1]
CELL_E[0].OUT_BEL[17]PCIE.TRNFCCPLD[2]
CELL_E[0].OUT_BEL[18]PCIE.TRNFCCPLD[3]
CELL_E[0].OUT_BEL[19]PCIE.TRNFCCPLD[4]
CELL_E[0].OUT_BEL[20]PCIE.MIMRXWDATA[15]
CELL_E[0].OUT_BEL[21]PCIE.DBGVECA[30]
CELL_E[0].OUT_BEL[22]PCIE.DBGVECA[31]
CELL_E[0].OUT_BEL[23]PCIE.DBGVECA[32]
CELL_E[1].IMUX_CTRL[0]PCIE.CMSTICKYRSTN
CELL_E[1].IMUX_CTRL[1]PCIE.FUNCLVLRSTN
CELL_E[1].IMUX_IMUX_DELAY[0]PCIE.PLDIRECTEDLINKCHANGE[1]
CELL_E[1].IMUX_IMUX_DELAY[1]PCIE.PIPERX1DATA[6]
CELL_E[1].IMUX_IMUX_DELAY[2]PCIE.CFGERRAERHEADERLOG[41]
CELL_E[1].IMUX_IMUX_DELAY[3]PCIE.PIPERX1DATA[8]
CELL_E[1].IMUX_IMUX_DELAY[4]PCIE.CFGERRAERHEADERLOG[42]
CELL_E[1].IMUX_IMUX_DELAY[5]PCIE.PIPERX1DATA[9]
CELL_E[1].IMUX_IMUX_DELAY[6]PCIE.CFGERRAERHEADERLOG[43]
CELL_E[1].IMUX_IMUX_DELAY[7]PCIE.PIPERX1DATA[10]
CELL_E[1].IMUX_IMUX_DELAY[8]PCIE.CFGERRAERHEADERLOG[44]
CELL_E[1].IMUX_IMUX_DELAY[9]PCIE.PIPERX1DATA[7]
CELL_E[1].IMUX_IMUX_DELAY[10]PCIE.CFGDSDEVICENUMBER[0]
CELL_E[1].IMUX_IMUX_DELAY[11]PCIE.PIPERX5DATA[8]
CELL_E[1].IMUX_IMUX_DELAY[12]PCIE.CFGDSDEVICENUMBER[1]
CELL_E[1].IMUX_IMUX_DELAY[13]PCIE.PIPERX5DATA[9]
CELL_E[1].IMUX_IMUX_DELAY[14]PCIE.CFGDSDEVICENUMBER[2]
CELL_E[1].IMUX_IMUX_DELAY[15]PCIE.PIPERX1DATA[11]
CELL_E[1].IMUX_IMUX_DELAY[16]PCIE.CFGDSDEVICENUMBER[3]
CELL_E[1].IMUX_IMUX_DELAY[17]PCIE.PIPERX5DATA[6]
CELL_E[1].IMUX_IMUX_DELAY[19]PCIE.PIPERX5DATA[10]
CELL_E[1].IMUX_IMUX_DELAY[21]PCIE.PIPERX5DATA[7]
CELL_E[1].IMUX_IMUX_DELAY[23]PCIE.PIPERX5DATA[11]
CELL_E[1].OUT_BEL[0]PCIE.PLRXPMSTATE[1]
CELL_E[1].OUT_BEL[1]PCIE.PLLINKUPCFGCAP
CELL_E[1].OUT_BEL[2]PCIE.PLLINKGEN2CAP
CELL_E[1].OUT_BEL[3]PCIE.PLLINKPARTNERGEN2SUPPORTED
CELL_E[1].OUT_BEL[4]PCIE.TRNFCCPLD[5]
CELL_E[1].OUT_BEL[5]PCIE.TRNFCCPLD[6]
CELL_E[1].OUT_BEL[6]PCIE.TRNFCCPLD[7]
CELL_E[1].OUT_BEL[7]PCIE.TRNFCCPLD[8]
CELL_E[1].OUT_BEL[8]PCIE.MIMRXWDATA[16]
CELL_E[1].OUT_BEL[9]PCIE.MIMRXWDATA[17]
CELL_E[1].OUT_BEL[10]PCIE.MIMRXWDATA[18]
CELL_E[1].OUT_BEL[11]PCIE.MIMRXWDATA[19]
CELL_E[1].OUT_BEL[12]PCIE.LL2BADDLLPERRN
CELL_E[1].OUT_BEL[13]PCIE.LL2REPLAYROERRN
CELL_E[1].OUT_BEL[14]PCIE.LL2REPLAYTOERRN
CELL_E[1].OUT_BEL[15]PCIE.PMVOUT
CELL_E[1].OUT_BEL[16]PCIE.CFGCOMMANDINTERRUPTDISABLE
CELL_E[1].OUT_BEL[17]PCIE.CFGDEVSTATUSCORRERRDETECTED
CELL_E[1].OUT_BEL[18]PCIE.PIPERX1POLARITY
CELL_E[1].OUT_BEL[19]PCIE.DBGVECB[60]
CELL_E[1].OUT_BEL[20]PCIE.DBGVECA[33]
CELL_E[1].OUT_BEL[21]PCIE.DBGVECA[34]
CELL_E[1].OUT_BEL[22]PCIE.PIPERX5POLARITY
CELL_E[1].OUT_BEL[23]PCIE.DBGVECA[35]
CELL_E[2].IMUX_CTRL[0]PCIE.TLRSTN
CELL_E[2].IMUX_CTRL[1]PCIE.DLRSTN
CELL_E[2].IMUX_IMUX_DELAY[0]PCIE.PLDIRECTEDLINKWIDTH[0]
CELL_E[2].IMUX_IMUX_DELAY[1]PCIE.PIPERX1CHARISK[1]
CELL_E[2].IMUX_IMUX_DELAY[2]PCIE.PLDIRECTEDLINKWIDTH[1]
CELL_E[2].IMUX_IMUX_DELAY[3]PCIE.PIPERX5DATA[13]
CELL_E[2].IMUX_IMUX_DELAY[4]PCIE.PLDIRECTEDLINKSPEED
CELL_E[2].IMUX_IMUX_DELAY[5]PCIE.PIPERX1DATA[12]
CELL_E[2].IMUX_IMUX_DELAY[6]PCIE.CFGERRAERHEADERLOG[45]
CELL_E[2].IMUX_IMUX_DELAY[7]PCIE.PIPERX1DATA[13]
CELL_E[2].IMUX_IMUX_DELAY[8]PCIE.CFGERRAERHEADERLOG[46]
CELL_E[2].IMUX_IMUX_DELAY[9]PCIE.PIPERX1DATA[15]
CELL_E[2].IMUX_IMUX_DELAY[10]PCIE.CFGERRAERHEADERLOG[47]
CELL_E[2].IMUX_IMUX_DELAY[11]PCIE.PIPERX1DATA[14]
CELL_E[2].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[48]
CELL_E[2].IMUX_IMUX_DELAY[13]PCIE.PIPERX5DATA[12]
CELL_E[2].IMUX_IMUX_DELAY[14]PCIE.CFGDSDEVICENUMBER[4]
CELL_E[2].IMUX_IMUX_DELAY[15]PCIE.PIPERX5DATA[14]
CELL_E[2].IMUX_IMUX_DELAY[16]PCIE.CFGDSFUNCTIONNUMBER[0]
CELL_E[2].IMUX_IMUX_DELAY[17]PCIE.PIPERX5CHARISK[1]
CELL_E[2].IMUX_IMUX_DELAY[18]PCIE.CFGDSFUNCTIONNUMBER[1]
CELL_E[2].IMUX_IMUX_DELAY[19]PCIE.CFGDSFUNCTIONNUMBER[2]
CELL_E[2].IMUX_IMUX_DELAY[21]PCIE.PIPERX5DATA[15]
CELL_E[2].OUT_BEL[0]PCIE.PLINITIALLINKWIDTH[0]
CELL_E[2].OUT_BEL[1]PCIE.PLINITIALLINKWIDTH[1]
CELL_E[2].OUT_BEL[2]PCIE.PLINITIALLINKWIDTH[2]
CELL_E[2].OUT_BEL[3]PCIE.TRNTDSTRDYN
CELL_E[2].OUT_BEL[4]PCIE.TRNFCCPLD[9]
CELL_E[2].OUT_BEL[5]PCIE.TRNFCCPLD[10]
CELL_E[2].OUT_BEL[6]PCIE.TRNFCCPLD[11]
CELL_E[2].OUT_BEL[7]PCIE.MIMTXWDATA[0]
CELL_E[2].OUT_BEL[8]PCIE.MIMRXWDATA[20]
CELL_E[2].OUT_BEL[9]PCIE.MIMRXWDATA[21]
CELL_E[2].OUT_BEL[10]PCIE.MIMRXWDATA[22]
CELL_E[2].OUT_BEL[11]PCIE.MIMRXWDATA[23]
CELL_E[2].OUT_BEL[12]PCIE.USERRSTN
CELL_E[2].OUT_BEL[13]PCIE.PLRECEIVEDHOTRST
CELL_E[2].OUT_BEL[14]PCIE.RECEIVEDFUNCLVLRSTN
CELL_E[2].OUT_BEL[15]PCIE.CFGDO[0]
CELL_E[2].OUT_BEL[16]PCIE.CFGDEVSTATUSNONFATALERRDETECTED
CELL_E[2].OUT_BEL[17]PCIE.CFGDEVSTATUSFATALERRDETECTED
CELL_E[2].OUT_BEL[18]PCIE.CFGDEVSTATUSURDETECTED
CELL_E[2].OUT_BEL[19]PCIE.DBGVECB[61]
CELL_E[2].OUT_BEL[20]PCIE.DBGVECB[62]
CELL_E[2].OUT_BEL[21]PCIE.DBGVECA[36]
CELL_E[2].OUT_BEL[22]PCIE.DBGVECA[37]
CELL_E[2].OUT_BEL[23]PCIE.DBGVECA[38]
CELL_E[3].IMUX_CTRL[0]PCIE.PLRSTN
CELL_E[3].IMUX_IMUX_DELAY[0]PCIE.PLDIRECTEDLINKAUTON
CELL_E[3].IMUX_IMUX_DELAY[1]PCIE.PIPERX5CHANISALIGNED
CELL_E[3].IMUX_IMUX_DELAY[2]PCIE.PLUPSTREAMPREFERDEEMPH
CELL_E[3].IMUX_IMUX_DELAY[3]PCIE.PLDOWNSTREAMDEEMPHSOURCE
CELL_E[3].IMUX_IMUX_DELAY[4]PCIE.TRNTD[0]
CELL_E[3].IMUX_IMUX_DELAY[5]PCIE.MIMTXRDATA[46]
CELL_E[3].IMUX_IMUX_DELAY[6]PCIE.MIMTXRDATA[47]
CELL_E[3].IMUX_IMUX_DELAY[7]PCIE.MIMTXRDATA[48]
CELL_E[3].IMUX_IMUX_DELAY[8]PCIE.MIMTXRDATA[49]
CELL_E[3].IMUX_IMUX_DELAY[9]PCIE.TRNTDLLPDATA[27]
CELL_E[3].IMUX_IMUX_DELAY[10]PCIE.CFGERRAERHEADERLOG[49]
CELL_E[3].IMUX_IMUX_DELAY[11]PCIE.CFGERRAERHEADERLOG[50]
CELL_E[3].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[51]
CELL_E[3].IMUX_IMUX_DELAY[13]PCIE.CFGERRAERHEADERLOG[52]
CELL_E[3].IMUX_IMUX_DELAY[14]PCIE.CFGPORTNUMBER[0]
CELL_E[3].IMUX_IMUX_DELAY[15]PCIE.PIPERX5CHARISK[0]
CELL_E[3].IMUX_IMUX_DELAY[16]PCIE.CFGPORTNUMBER[1]
CELL_E[3].IMUX_IMUX_DELAY[17]PCIE.CFGPORTNUMBER[2]
CELL_E[3].IMUX_IMUX_DELAY[18]PCIE.CFGPORTNUMBER[3]
CELL_E[3].IMUX_IMUX_DELAY[21]PCIE.PIPERX1CHANISALIGNED
CELL_E[3].IMUX_IMUX_DELAY[23]PCIE.PIPERX1CHARISK[0]
CELL_E[3].OUT_BEL[0]PCIE.TRNTERRDROPN
CELL_E[3].OUT_BEL[1]PCIE.TRNTBUFAV[0]
CELL_E[3].OUT_BEL[2]PCIE.TRNTBUFAV[1]
CELL_E[3].OUT_BEL[3]PCIE.TRNTBUFAV[2]
CELL_E[3].OUT_BEL[4]PCIE.MIMTXWDATA[1]
CELL_E[3].OUT_BEL[5]PCIE.MIMTXWDATA[2]
CELL_E[3].OUT_BEL[6]PCIE.MIMTXWDATA[3]
CELL_E[3].OUT_BEL[7]PCIE.MIMTXWDATA[4]
CELL_E[3].OUT_BEL[8]PCIE.MIMRXWDATA[24]
CELL_E[3].OUT_BEL[9]PCIE.MIMRXWDATA[25]
CELL_E[3].OUT_BEL[10]PCIE.MIMRXWDATA[26]
CELL_E[3].OUT_BEL[11]PCIE.MIMRXWDATA[27]
CELL_E[3].OUT_BEL[12]PCIE.CFGDO[1]
CELL_E[3].OUT_BEL[13]PCIE.CFGDO[2]
CELL_E[3].OUT_BEL[14]PCIE.CFGDO[3]
CELL_E[3].OUT_BEL[15]PCIE.CFGDO[4]
CELL_E[3].OUT_BEL[16]PCIE.CFGDEVCONTROLCORRERRREPORTINGEN
CELL_E[3].OUT_BEL[17]PCIE.CFGDEVCONTROLNONFATALREPORTINGEN
CELL_E[3].OUT_BEL[18]PCIE.CFGDEVCONTROLFATALERRREPORTINGEN
CELL_E[3].OUT_BEL[19]PCIE.DBGVECB[63]
CELL_E[3].OUT_BEL[20]PCIE.DBGVECC[0]
CELL_E[3].OUT_BEL[21]PCIE.DBGVECA[39]
CELL_E[3].OUT_BEL[22]PCIE.DBGVECA[40]
CELL_E[3].OUT_BEL[23]PCIE.DBGVECA[41]
CELL_E[4].IMUX_IMUX_DELAY[0]PCIE.TRNTD[1]
CELL_E[4].IMUX_IMUX_DELAY[1]PCIE.PIPERX5STATUS[2]
CELL_E[4].IMUX_IMUX_DELAY[2]PCIE.TRNTD[2]
CELL_E[4].IMUX_IMUX_DELAY[3]PCIE.PIPERX5STATUS[0]
CELL_E[4].IMUX_IMUX_DELAY[4]PCIE.TRNTD[3]
CELL_E[4].IMUX_IMUX_DELAY[5]PCIE.TRNTD[4]
CELL_E[4].IMUX_IMUX_DELAY[6]PCIE.MIMTXRDATA[50]
CELL_E[4].IMUX_IMUX_DELAY[7]PCIE.PIPERX5STATUS[1]
CELL_E[4].IMUX_IMUX_DELAY[8]PCIE.CFGERRAERHEADERLOG[53]
CELL_E[4].IMUX_IMUX_DELAY[9]PCIE.CFGERRAERHEADERLOG[54]
CELL_E[4].IMUX_IMUX_DELAY[10]PCIE.CFGERRAERHEADERLOG[55]
CELL_E[4].IMUX_IMUX_DELAY[11]PCIE.PIPERX1PHYSTATUS
CELL_E[4].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[56]
CELL_E[4].IMUX_IMUX_DELAY[13]PCIE.CFGPORTNUMBER[4]
CELL_E[4].IMUX_IMUX_DELAY[14]PCIE.CFGPORTNUMBER[5]
CELL_E[4].IMUX_IMUX_DELAY[15]PCIE.PIPERX5PHYSTATUS
CELL_E[4].IMUX_IMUX_DELAY[16]PCIE.CFGPORTNUMBER[6]
CELL_E[4].IMUX_IMUX_DELAY[17]PCIE.CFGPORTNUMBER[7]
CELL_E[4].IMUX_IMUX_DELAY[19]PCIE.PIPERX1STATUS[1]
CELL_E[4].IMUX_IMUX_DELAY[21]PCIE.PIPERX1STATUS[2]
CELL_E[4].IMUX_IMUX_DELAY[23]PCIE.PIPERX1STATUS[0]
CELL_E[4].OUT_BEL[0]PCIE.TRNTBUFAV[3]
CELL_E[4].OUT_BEL[1]PCIE.PIPETX1ELECIDLE
CELL_E[4].OUT_BEL[2]PCIE.TRNTBUFAV[4]
CELL_E[4].OUT_BEL[3]PCIE.TRNTBUFAV[5]
CELL_E[4].OUT_BEL[4]PCIE.TRNTCFGREQN
CELL_E[4].OUT_BEL[5]PCIE.PIPETX5ELECIDLE
CELL_E[4].OUT_BEL[6]PCIE.MIMTXWDATA[5]
CELL_E[4].OUT_BEL[7]PCIE.MIMTXWDATA[6]
CELL_E[4].OUT_BEL[8]PCIE.MIMTXWDATA[7]
CELL_E[4].OUT_BEL[9]PCIE.MIMTXWDATA[8]
CELL_E[4].OUT_BEL[10]PCIE.MIMRXWDATA[28]
CELL_E[4].OUT_BEL[11]PCIE.MIMRXWDATA[29]
CELL_E[4].OUT_BEL[12]PCIE.MIMRXWDATA[30]
CELL_E[4].OUT_BEL[13]PCIE.MIMRXWDATA[31]
CELL_E[4].OUT_BEL[14]PCIE.CFGDO[5]
CELL_E[4].OUT_BEL[15]PCIE.DBGVECC[1]
CELL_E[4].OUT_BEL[16]PCIE.DBGVECC[2]
CELL_E[4].OUT_BEL[17]PCIE.PIPETX5POWERDOWN[0]
CELL_E[4].OUT_BEL[18]PCIE.DBGVECA[42]
CELL_E[4].OUT_BEL[19]PCIE.PIPETX5POWERDOWN[1]
CELL_E[4].OUT_BEL[20]PCIE.DBGVECA[43]
CELL_E[4].OUT_BEL[21]PCIE.PIPETX1POWERDOWN[0]
CELL_E[4].OUT_BEL[22]PCIE.DBGVECA[44]
CELL_E[4].OUT_BEL[23]PCIE.PIPETX1POWERDOWN[1]
CELL_E[5].IMUX_IMUX_DELAY[0]PCIE.TRNTD[5]
CELL_E[5].IMUX_IMUX_DELAY[1]PCIE.TRNTD[6]
CELL_E[5].IMUX_IMUX_DELAY[2]PCIE.TRNTD[7]
CELL_E[5].IMUX_IMUX_DELAY[3]PCIE.TRNTD[8]
CELL_E[5].IMUX_IMUX_DELAY[4]PCIE.MIMTXRDATA[51]
CELL_E[5].IMUX_IMUX_DELAY[5]PCIE.PIPERX5ELECIDLE
CELL_E[5].IMUX_IMUX_DELAY[6]PCIE.MIMTXRDATA[52]
CELL_E[5].IMUX_IMUX_DELAY[7]PCIE.MIMTXRDATA[53]
CELL_E[5].IMUX_IMUX_DELAY[8]PCIE.MIMTXRDATA[54]
CELL_E[5].IMUX_IMUX_DELAY[9]PCIE.TRNTDLLPDATA[28]
CELL_E[5].IMUX_IMUX_DELAY[10]PCIE.CFGERRAERHEADERLOG[57]
CELL_E[5].IMUX_IMUX_DELAY[11]PCIE.PIPERX5VALID
CELL_E[5].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[58]
CELL_E[5].IMUX_IMUX_DELAY[13]PCIE.CFGERRAERHEADERLOG[59]
CELL_E[5].IMUX_IMUX_DELAY[14]PCIE.CFGERRAERHEADERLOG[60]
CELL_E[5].IMUX_IMUX_DELAY[15]PCIE.CFGPMWAKEN
CELL_E[5].IMUX_IMUX_DELAY[16]PCIE.CFGPMDIRECTASPML1N
CELL_E[5].IMUX_IMUX_DELAY[17]PCIE.CFGPMTURNOFFOKN
CELL_E[5].IMUX_IMUX_DELAY[18]PCIE.CFGPMSENDPMACKN
CELL_E[5].IMUX_IMUX_DELAY[19]PCIE.PIPERX1VALID
CELL_E[5].IMUX_IMUX_DELAY[21]PCIE.PIPERX1ELECIDLE
CELL_E[5].OUT_BEL[0]PCIE.TRNRD[0]
CELL_E[5].OUT_BEL[1]PCIE.TRNRD[1]
CELL_E[5].OUT_BEL[2]PCIE.TRNRD[2]
CELL_E[5].OUT_BEL[3]PCIE.TRNRD[3]
CELL_E[5].OUT_BEL[4]PCIE.MIMTXWDATA[9]
CELL_E[5].OUT_BEL[5]PCIE.MIMTXWDATA[10]
CELL_E[5].OUT_BEL[6]PCIE.MIMTXWDATA[11]
CELL_E[5].OUT_BEL[7]PCIE.MIMTXWDATA[12]
CELL_E[5].OUT_BEL[8]PCIE.MIMRXWDATA[32]
CELL_E[5].OUT_BEL[9]PCIE.MIMRXWDATA[33]
CELL_E[5].OUT_BEL[10]PCIE.MIMRXWDATA[34]
CELL_E[5].OUT_BEL[11]PCIE.MIMRXWDATA[35]
CELL_E[5].OUT_BEL[12]PCIE.CFGDO[6]
CELL_E[5].OUT_BEL[13]PCIE.DBGVECC[3]
CELL_E[5].OUT_BEL[14]PCIE.DBGVECC[4]
CELL_E[5].OUT_BEL[15]PCIE.DBGVECC[5]
CELL_E[5].OUT_BEL[16]PCIE.PIPETX1COMPLIANCE
CELL_E[5].OUT_BEL[17]PCIE.DBGVECA[45]
CELL_E[5].OUT_BEL[18]PCIE.PIPETX1CHARISK[0]
CELL_E[5].OUT_BEL[19]PCIE.PIPETX5CHARISK[1]
CELL_E[5].OUT_BEL[20]PCIE.PIPETX5COMPLIANCE
CELL_E[5].OUT_BEL[21]PCIE.DBGVECA[46]
CELL_E[5].OUT_BEL[22]PCIE.PIPETX5CHARISK[0]
CELL_E[5].OUT_BEL[23]PCIE.PIPETX1CHARISK[1]
CELL_E[6].IMUX_IMUX_DELAY[0]PCIE.TRNTD[9]
CELL_E[6].IMUX_IMUX_DELAY[1]PCIE.TRNTD[10]
CELL_E[6].IMUX_IMUX_DELAY[2]PCIE.TRNTD[11]
CELL_E[6].IMUX_IMUX_DELAY[3]PCIE.TRNTD[12]
CELL_E[6].IMUX_IMUX_DELAY[4]PCIE.MIMTXRDATA[55]
CELL_E[6].IMUX_IMUX_DELAY[5]PCIE.MIMTXRDATA[56]
CELL_E[6].IMUX_IMUX_DELAY[6]PCIE.MIMTXRDATA[57]
CELL_E[6].IMUX_IMUX_DELAY[7]PCIE.MIMTXRDATA[58]
CELL_E[6].IMUX_IMUX_DELAY[8]PCIE.TRNTDLLPDATA[29]
CELL_E[6].IMUX_IMUX_DELAY[9]PCIE.TRNTDLLPDATA[30]
CELL_E[6].IMUX_IMUX_DELAY[10]PCIE.TRNTDLLPDATA[31]
CELL_E[6].IMUX_IMUX_DELAY[11]PCIE.TRNTDLLPSRCRDYN
CELL_E[6].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[61]
CELL_E[6].IMUX_IMUX_DELAY[13]PCIE.CFGERRAERHEADERLOG[62]
CELL_E[6].IMUX_IMUX_DELAY[14]PCIE.CFGERRAERHEADERLOG[63]
CELL_E[6].IMUX_IMUX_DELAY[15]PCIE.CFGERRAERHEADERLOG[64]
CELL_E[6].IMUX_IMUX_DELAY[16]PCIE.CFGPMSENDPMNAKN
CELL_E[6].IMUX_IMUX_DELAY[17]PCIE.CFGPMSENDPMETON
CELL_E[6].IMUX_IMUX_DELAY[18]PCIE.CFGTRNPENDINGN
CELL_E[6].IMUX_IMUX_DELAY[19]PCIE.CFGDSN[0]
CELL_E[6].IMUX_IMUX_DELAY[20]PCIE.DRPDEN
CELL_E[6].OUT_BEL[0]PCIE.TRNRD[4]
CELL_E[6].OUT_BEL[1]PCIE.TRNRD[5]
CELL_E[6].OUT_BEL[2]PCIE.PIPETX5DATA[13]
CELL_E[6].OUT_BEL[3]PCIE.TRNRD[6]
CELL_E[6].OUT_BEL[4]PCIE.TRNRD[7]
CELL_E[6].OUT_BEL[5]PCIE.MIMTXWDATA[13]
CELL_E[6].OUT_BEL[6]PCIE.PIPETX1DATA[13]
CELL_E[6].OUT_BEL[7]PCIE.MIMTXWDATA[14]
CELL_E[6].OUT_BEL[8]PCIE.CFGDO[7]
CELL_E[6].OUT_BEL[9]PCIE.MIMRXWDATA[36]
CELL_E[6].OUT_BEL[10]PCIE.MIMRXWDATA[37]
CELL_E[6].OUT_BEL[11]PCIE.MIMRXWDATA[38]
CELL_E[6].OUT_BEL[12]PCIE.MIMRXWDATA[39]
CELL_E[6].OUT_BEL[13]PCIE.DBGVECA[47]
CELL_E[6].OUT_BEL[14]PCIE.DBGVECA[48]
CELL_E[6].OUT_BEL[15]PCIE.DBGVECA[49]
CELL_E[6].OUT_BEL[16]PCIE.PIPETX1DATA[12]
CELL_E[6].OUT_BEL[17]PCIE.PIPETX5DATA[15]
CELL_E[6].OUT_BEL[18]PCIE.DBGVECA[50]
CELL_E[6].OUT_BEL[19]PCIE.PIPETX5DATA[14]
CELL_E[6].OUT_BEL[20]PCIE.PIPETX5DATA[12]
CELL_E[6].OUT_BEL[21]PCIE.PIPETX1DATA[15]
CELL_E[6].OUT_BEL[22]PCIE.DBGVECC[6]
CELL_E[6].OUT_BEL[23]PCIE.PIPETX1DATA[14]
CELL_E[7].IMUX_IMUX_DELAY[0]PCIE.TRNTD[13]
CELL_E[7].IMUX_IMUX_DELAY[1]PCIE.TRNTD[14]
CELL_E[7].IMUX_IMUX_DELAY[2]PCIE.TRNTD[15]
CELL_E[7].IMUX_IMUX_DELAY[3]PCIE.TRNTD[16]
CELL_E[7].IMUX_IMUX_DELAY[4]PCIE.MIMTXRDATA[59]
CELL_E[7].IMUX_IMUX_DELAY[5]PCIE.MIMTXRDATA[60]
CELL_E[7].IMUX_IMUX_DELAY[6]PCIE.MIMTXRDATA[61]
CELL_E[7].IMUX_IMUX_DELAY[7]PCIE.MIMTXRDATA[62]
CELL_E[7].IMUX_IMUX_DELAY[8]PCIE.LL2TLPRCVN
CELL_E[7].IMUX_IMUX_DELAY[9]PCIE.LL2SENDENTERL1N
CELL_E[7].IMUX_IMUX_DELAY[10]PCIE.LL2SENDENTERL23N
CELL_E[7].IMUX_IMUX_DELAY[11]PCIE.LL2SENDASREQL1N
CELL_E[7].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[65]
CELL_E[7].IMUX_IMUX_DELAY[13]PCIE.CFGERRAERHEADERLOG[66]
CELL_E[7].IMUX_IMUX_DELAY[14]PCIE.CFGERRAERHEADERLOG[67]
CELL_E[7].IMUX_IMUX_DELAY[15]PCIE.CFGERRAERHEADERLOG[68]
CELL_E[7].IMUX_IMUX_DELAY[16]PCIE.CFGDSN[1]
CELL_E[7].IMUX_IMUX_DELAY[17]PCIE.CFGDSN[2]
CELL_E[7].IMUX_IMUX_DELAY[18]PCIE.CFGDSN[3]
CELL_E[7].IMUX_IMUX_DELAY[19]PCIE.CFGDSN[4]
CELL_E[7].IMUX_IMUX_DELAY[20]PCIE.DRPDWE
CELL_E[7].OUT_BEL[0]PCIE.TRNRD[8]
CELL_E[7].OUT_BEL[1]PCIE.PIPETX1DATA[11]
CELL_E[7].OUT_BEL[2]PCIE.PIPETX5DATA[8]
CELL_E[7].OUT_BEL[3]PCIE.TRNRD[9]
CELL_E[7].OUT_BEL[4]PCIE.CFGDO[8]
CELL_E[7].OUT_BEL[5]PCIE.PIPETX5DATA[11]
CELL_E[7].OUT_BEL[6]PCIE.PIPETX1DATA[8]
CELL_E[7].OUT_BEL[7]PCIE.MIMRXWDATA[40]
CELL_E[7].OUT_BEL[8]PCIE.MIMRXWDATA[41]
CELL_E[7].OUT_BEL[9]PCIE.MIMRXWDATA[42]
CELL_E[7].OUT_BEL[10]PCIE.MIMRXWDATA[43]
CELL_E[7].OUT_BEL[11]PCIE.DBGVECA[51]
CELL_E[7].OUT_BEL[12]PCIE.DBGVECA[52]
CELL_E[7].OUT_BEL[13]PCIE.DBGVECA[53]
CELL_E[7].OUT_BEL[14]PCIE.DBGVECA[54]
CELL_E[7].OUT_BEL[15]PCIE.DBGVECC[7]
CELL_E[7].OUT_BEL[16]PCIE.PIPETX1DATA[7]
CELL_E[7].OUT_BEL[17]PCIE.PIPETX5DATA[10]
CELL_E[7].OUT_BEL[18]PCIE.PIPETX1DATA[6]
CELL_E[7].OUT_BEL[19]PCIE.PIPETX5DATA[9]
CELL_E[7].OUT_BEL[20]PCIE.PIPETX5DATA[7]
CELL_E[7].OUT_BEL[21]PCIE.PIPETX1DATA[10]
CELL_E[7].OUT_BEL[22]PCIE.PIPETX5DATA[6]
CELL_E[7].OUT_BEL[23]PCIE.PIPETX1DATA[9]
CELL_E[8].IMUX_CLK[0]PCIE.DRPCLK
CELL_E[8].IMUX_IMUX_DELAY[0]PCIE.TRNTD[17]
CELL_E[8].IMUX_IMUX_DELAY[1]PCIE.TRNTD[18]
CELL_E[8].IMUX_IMUX_DELAY[2]PCIE.TRNTD[19]
CELL_E[8].IMUX_IMUX_DELAY[3]PCIE.TRNTD[20]
CELL_E[8].IMUX_IMUX_DELAY[4]PCIE.MIMTXRDATA[63]
CELL_E[8].IMUX_IMUX_DELAY[5]PCIE.MIMTXRDATA[64]
CELL_E[8].IMUX_IMUX_DELAY[6]PCIE.MIMTXRDATA[65]
CELL_E[8].IMUX_IMUX_DELAY[7]PCIE.MIMTXRDATA[66]
CELL_E[8].IMUX_IMUX_DELAY[8]PCIE.PL2DIRECTEDLSTATE[0]
CELL_E[8].IMUX_IMUX_DELAY[9]PCIE.PL2DIRECTEDLSTATE[1]
CELL_E[8].IMUX_IMUX_DELAY[10]PCIE.PL2DIRECTEDLSTATE[2]
CELL_E[8].IMUX_IMUX_DELAY[11]PCIE.PL2DIRECTEDLSTATE[3]
CELL_E[8].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[69]
CELL_E[8].IMUX_IMUX_DELAY[13]PCIE.CFGERRAERHEADERLOG[70]
CELL_E[8].IMUX_IMUX_DELAY[14]PCIE.CFGERRAERHEADERLOG[71]
CELL_E[8].IMUX_IMUX_DELAY[15]PCIE.CFGERRAERHEADERLOG[72]
CELL_E[8].IMUX_IMUX_DELAY[16]PCIE.CFGDSN[5]
CELL_E[8].IMUX_IMUX_DELAY[17]PCIE.CFGDSN[6]
CELL_E[8].IMUX_IMUX_DELAY[18]PCIE.CFGDSN[7]
CELL_E[8].IMUX_IMUX_DELAY[19]PCIE.CFGDSN[8]
CELL_E[8].IMUX_IMUX_DELAY[20]PCIE.DRPDADDR[0]
CELL_E[8].OUT_BEL[0]PCIE.TRNRD[10]
CELL_E[8].OUT_BEL[1]PCIE.PIPETX1DATA[3]
CELL_E[8].OUT_BEL[2]PCIE.PIPETX5DATA[4]
CELL_E[8].OUT_BEL[3]PCIE.TRNRD[11]
CELL_E[8].OUT_BEL[4]PCIE.CFGDO[9]
CELL_E[8].OUT_BEL[5]PCIE.PIPETX5DATA[3]
CELL_E[8].OUT_BEL[6]PCIE.PIPETX1DATA[4]
CELL_E[8].OUT_BEL[7]PCIE.MIMRXWDATA[44]
CELL_E[8].OUT_BEL[8]PCIE.MIMRXWDATA[45]
CELL_E[8].OUT_BEL[9]PCIE.MIMRXWDATA[46]
CELL_E[8].OUT_BEL[10]PCIE.MIMRXWDATA[47]
CELL_E[8].OUT_BEL[11]PCIE.DBGVECA[55]
CELL_E[8].OUT_BEL[12]PCIE.DBGVECA[56]
CELL_E[8].OUT_BEL[13]PCIE.DBGVECA[57]
CELL_E[8].OUT_BEL[14]PCIE.DBGVECA[58]
CELL_E[8].OUT_BEL[15]PCIE.DBGVECC[8]
CELL_E[8].OUT_BEL[16]PCIE.PIPETX1DATA[0]
CELL_E[8].OUT_BEL[17]PCIE.PIPETX5DATA[1]
CELL_E[8].OUT_BEL[18]PCIE.PIPETX1DATA[5]
CELL_E[8].OUT_BEL[19]PCIE.PIPETX5DATA[2]
CELL_E[8].OUT_BEL[20]PCIE.PIPETX5DATA[0]
CELL_E[8].OUT_BEL[21]PCIE.PIPETX1DATA[1]
CELL_E[8].OUT_BEL[22]PCIE.PIPETX5DATA[5]
CELL_E[8].OUT_BEL[23]PCIE.PIPETX1DATA[2]
CELL_E[9].IMUX_CLK[0]PCIE.USERCLK
CELL_E[9].IMUX_CLK[1]PCIE.PIPECLK
CELL_E[9].IMUX_IMUX_DELAY[0]PCIE.TRNTD[21]
CELL_E[9].IMUX_IMUX_DELAY[1]PCIE.TRNTD[22]
CELL_E[9].IMUX_IMUX_DELAY[2]PCIE.TRNTD[23]
CELL_E[9].IMUX_IMUX_DELAY[3]PCIE.TRNTD[24]
CELL_E[9].IMUX_IMUX_DELAY[4]PCIE.MIMTXRDATA[67]
CELL_E[9].IMUX_IMUX_DELAY[5]PCIE.MIMTXRDATA[68]
CELL_E[9].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[0]
CELL_E[9].IMUX_IMUX_DELAY[7]PCIE.MIMRXRDATA[1]
CELL_E[9].IMUX_IMUX_DELAY[8]PCIE.PL2DIRECTEDLSTATE[4]
CELL_E[9].IMUX_IMUX_DELAY[9]PCIE.LL2SUSPENDNOWN
CELL_E[9].IMUX_IMUX_DELAY[10]PCIE.TL2PPMSUSPENDREQN
CELL_E[9].IMUX_IMUX_DELAY[11]PCIE.TL2ASPMSUSPENDCREDITCHECKN
CELL_E[9].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[73]
CELL_E[9].IMUX_IMUX_DELAY[13]PCIE.CFGERRAERHEADERLOG[74]
CELL_E[9].IMUX_IMUX_DELAY[14]PCIE.CFGERRAERHEADERLOG[75]
CELL_E[9].IMUX_IMUX_DELAY[15]PCIE.CFGERRAERHEADERLOG[76]
CELL_E[9].IMUX_IMUX_DELAY[16]PCIE.CFGDSN[9]
CELL_E[9].IMUX_IMUX_DELAY[17]PCIE.CFGDSN[10]
CELL_E[9].IMUX_IMUX_DELAY[18]PCIE.CFGDSN[11]
CELL_E[9].IMUX_IMUX_DELAY[19]PCIE.CFGDSN[12]
CELL_E[9].IMUX_IMUX_DELAY[20]PCIE.DRPDADDR[1]
CELL_E[9].IMUX_IMUX_DELAY[21]PCIE.DRPDADDR[2]
CELL_E[9].IMUX_IMUX_DELAY[22]PCIE.DRPDADDR[3]
CELL_E[9].OUT_BEL[0]PCIE.TRNRD[12]
CELL_E[9].OUT_BEL[1]PCIE.TRNRD[13]
CELL_E[9].OUT_BEL[2]PCIE.TRNRD[14]
CELL_E[9].OUT_BEL[3]PCIE.TRNRD[15]
CELL_E[9].OUT_BEL[4]PCIE.MIMTXWDATA[15]
CELL_E[9].OUT_BEL[5]PCIE.MIMTXWDATA[16]
CELL_E[9].OUT_BEL[6]PCIE.MIMTXWDATA[17]
CELL_E[9].OUT_BEL[7]PCIE.MIMTXWDATA[18]
CELL_E[9].OUT_BEL[8]PCIE.MIMRXWDATA[48]
CELL_E[9].OUT_BEL[9]PCIE.MIMRXWDATA[49]
CELL_E[9].OUT_BEL[10]PCIE.MIMRXWDATA[50]
CELL_E[9].OUT_BEL[11]PCIE.MIMRXWDATA[51]
CELL_E[9].OUT_BEL[12]PCIE.CFGDO[10]
CELL_E[9].OUT_BEL[13]PCIE.CFGDO[11]
CELL_E[9].OUT_BEL[14]PCIE.CFGDO[12]
CELL_E[9].OUT_BEL[15]PCIE.CFGDO[13]
CELL_E[9].OUT_BEL[16]PCIE.CFGDEVCONTROLURERRREPORTINGEN
CELL_E[9].OUT_BEL[17]PCIE.CFGDEVCONTROLENABLERO
CELL_E[9].OUT_BEL[18]PCIE.CFGDEVCONTROLMAXPAYLOAD[0]
CELL_E[9].OUT_BEL[19]PCIE.DBGVECC[9]
CELL_E[9].OUT_BEL[20]PCIE.DBGVECC[10]
CELL_E[9].OUT_BEL[21]PCIE.DBGVECA[59]
CELL_E[9].OUT_BEL[22]PCIE.DBGVECA[60]
CELL_E[9].OUT_BEL[23]PCIE.DBGVECA[61]
CELL_E[10].IMUX_IMUX_DELAY[0]PCIE.TRNTD[25]
CELL_E[10].IMUX_IMUX_DELAY[1]PCIE.PIPERX0DATA[4]
CELL_E[10].IMUX_IMUX_DELAY[2]PCIE.MIMRXRDATA[2]
CELL_E[10].IMUX_IMUX_DELAY[3]PCIE.PIPERX0DATA[0]
CELL_E[10].IMUX_IMUX_DELAY[4]PCIE.MIMRXRDATA[3]
CELL_E[10].IMUX_IMUX_DELAY[5]PCIE.PIPERX0DATA[1]
CELL_E[10].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[4]
CELL_E[10].IMUX_IMUX_DELAY[7]PCIE.PIPERX4DATA[2]
CELL_E[10].IMUX_IMUX_DELAY[8]PCIE.MIMRXRDATA[5]
CELL_E[10].IMUX_IMUX_DELAY[9]PCIE.PIPERX0DATA[5]
CELL_E[10].IMUX_IMUX_DELAY[10]PCIE.SCANMODEN
CELL_E[10].IMUX_IMUX_DELAY[11]PCIE.PIPERX4DATA[0]
CELL_E[10].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[77]
CELL_E[10].IMUX_IMUX_DELAY[13]PCIE.PIPERX4DATA[1]
CELL_E[10].IMUX_IMUX_DELAY[14]PCIE.CFGERRAERHEADERLOG[78]
CELL_E[10].IMUX_IMUX_DELAY[15]PCIE.PIPERX0DATA[2]
CELL_E[10].IMUX_IMUX_DELAY[16]PCIE.CFGERRAERHEADERLOG[79]
CELL_E[10].IMUX_IMUX_DELAY[17]PCIE.PIPERX4DATA[4]
CELL_E[10].IMUX_IMUX_DELAY[18]PCIE.CFGERRAERHEADERLOG[80]
CELL_E[10].IMUX_IMUX_DELAY[19]PCIE.PIPERX0DATA[3]
CELL_E[10].IMUX_IMUX_DELAY[21]PCIE.PIPERX4DATA[5]
CELL_E[10].IMUX_IMUX_DELAY[23]PCIE.PIPERX4DATA[3]
CELL_E[10].OUT_BEL[0]PCIE.TRNRD[16]
CELL_E[10].OUT_BEL[1]PCIE.TRNRD[17]
CELL_E[10].OUT_BEL[2]PCIE.TRNRD[18]
CELL_E[10].OUT_BEL[3]PCIE.TRNRD[19]
CELL_E[10].OUT_BEL[4]PCIE.MIMTXWDATA[19]
CELL_E[10].OUT_BEL[5]PCIE.MIMTXWDATA[20]
CELL_E[10].OUT_BEL[6]PCIE.MIMTXWDATA[21]
CELL_E[10].OUT_BEL[7]PCIE.MIMTXWDATA[22]
CELL_E[10].OUT_BEL[8]PCIE.MIMRXWDATA[52]
CELL_E[10].OUT_BEL[9]PCIE.MIMRXWDATA[53]
CELL_E[10].OUT_BEL[10]PCIE.MIMRXWDATA[54]
CELL_E[10].OUT_BEL[11]PCIE.MIMRXWDATA[55]
CELL_E[10].OUT_BEL[12]PCIE.CFGDO[14]
CELL_E[10].OUT_BEL[13]PCIE.CFGDO[15]
CELL_E[10].OUT_BEL[14]PCIE.CFGDO[16]
CELL_E[10].OUT_BEL[15]PCIE.CFGDO[17]
CELL_E[10].OUT_BEL[16]PCIE.CFGDEVCONTROLMAXPAYLOAD[1]
CELL_E[10].OUT_BEL[17]PCIE.CFGDEVCONTROLMAXPAYLOAD[2]
CELL_E[10].OUT_BEL[18]PCIE.CFGDEVCONTROLEXTTAGEN
CELL_E[10].OUT_BEL[19]PCIE.DBGVECC[11]
CELL_E[10].OUT_BEL[20]PCIE.DBGSCLRA
CELL_E[10].OUT_BEL[21]PCIE.DBGVECA[62]
CELL_E[10].OUT_BEL[22]PCIE.DBGVECA[63]
CELL_E[10].OUT_BEL[23]PCIE.DBGVECB[0]
CELL_E[11].IMUX_IMUX_DELAY[0]PCIE.TRNTD[26]
CELL_E[11].IMUX_IMUX_DELAY[1]PCIE.PIPERX0DATA[6]
CELL_E[11].IMUX_IMUX_DELAY[2]PCIE.MIMRXRDATA[6]
CELL_E[11].IMUX_IMUX_DELAY[3]PCIE.PIPERX0DATA[8]
CELL_E[11].IMUX_IMUX_DELAY[4]PCIE.MIMRXRDATA[7]
CELL_E[11].IMUX_IMUX_DELAY[5]PCIE.PIPERX0DATA[9]
CELL_E[11].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[8]
CELL_E[11].IMUX_IMUX_DELAY[7]PCIE.PIPERX0DATA[10]
CELL_E[11].IMUX_IMUX_DELAY[8]PCIE.MIMRXRDATA[9]
CELL_E[11].IMUX_IMUX_DELAY[9]PCIE.PIPERX0DATA[7]
CELL_E[11].IMUX_IMUX_DELAY[10]PCIE.SCANENABLEN
CELL_E[11].IMUX_IMUX_DELAY[11]PCIE.PIPERX4DATA[8]
CELL_E[11].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[81]
CELL_E[11].IMUX_IMUX_DELAY[13]PCIE.PIPERX4DATA[9]
CELL_E[11].IMUX_IMUX_DELAY[14]PCIE.CFGERRAERHEADERLOG[82]
CELL_E[11].IMUX_IMUX_DELAY[15]PCIE.PIPERX0DATA[11]
CELL_E[11].IMUX_IMUX_DELAY[16]PCIE.CFGERRAERHEADERLOG[83]
CELL_E[11].IMUX_IMUX_DELAY[17]PCIE.PIPERX4DATA[6]
CELL_E[11].IMUX_IMUX_DELAY[18]PCIE.CFGERRAERHEADERLOG[84]
CELL_E[11].IMUX_IMUX_DELAY[19]PCIE.PIPERX4DATA[10]
CELL_E[11].IMUX_IMUX_DELAY[21]PCIE.PIPERX4DATA[7]
CELL_E[11].IMUX_IMUX_DELAY[23]PCIE.PIPERX4DATA[11]
CELL_E[11].OUT_BEL[0]PCIE.TRNRD[20]
CELL_E[11].OUT_BEL[1]PCIE.TRNRD[21]
CELL_E[11].OUT_BEL[2]PCIE.TRNRD[22]
CELL_E[11].OUT_BEL[3]PCIE.TRNRD[23]
CELL_E[11].OUT_BEL[4]PCIE.MIMTXWDATA[23]
CELL_E[11].OUT_BEL[5]PCIE.MIMTXWDATA[24]
CELL_E[11].OUT_BEL[6]PCIE.MIMTXWDATA[25]
CELL_E[11].OUT_BEL[7]PCIE.MIMTXWDATA[26]
CELL_E[11].OUT_BEL[8]PCIE.MIMRXWDATA[56]
CELL_E[11].OUT_BEL[9]PCIE.MIMRXWDATA[57]
CELL_E[11].OUT_BEL[10]PCIE.MIMRXWDATA[58]
CELL_E[11].OUT_BEL[11]PCIE.MIMRXWDATA[59]
CELL_E[11].OUT_BEL[12]PCIE.CFGDO[18]
CELL_E[11].OUT_BEL[13]PCIE.CFGDO[19]
CELL_E[11].OUT_BEL[14]PCIE.CFGDO[20]
CELL_E[11].OUT_BEL[15]PCIE.CFGDO[21]
CELL_E[11].OUT_BEL[16]PCIE.CFGDEVCONTROLPHANTOMEN
CELL_E[11].OUT_BEL[17]PCIE.CFGDEVCONTROLAUXPOWEREN
CELL_E[11].OUT_BEL[18]PCIE.PIPERX0POLARITY
CELL_E[11].OUT_BEL[19]PCIE.DBGSCLRB
CELL_E[11].OUT_BEL[20]PCIE.DBGVECB[1]
CELL_E[11].OUT_BEL[21]PCIE.DBGVECB[2]
CELL_E[11].OUT_BEL[22]PCIE.PIPERX4POLARITY
CELL_E[11].OUT_BEL[23]PCIE.DBGVECB[3]
CELL_E[12].IMUX_IMUX_DELAY[0]PCIE.TRNTD[27]
CELL_E[12].IMUX_IMUX_DELAY[1]PCIE.PIPERX0CHARISK[1]
CELL_E[12].IMUX_IMUX_DELAY[2]PCIE.TRNTD[28]
CELL_E[12].IMUX_IMUX_DELAY[3]PCIE.PIPERX4DATA[13]
CELL_E[12].IMUX_IMUX_DELAY[4]PCIE.TRNTD[29]
CELL_E[12].IMUX_IMUX_DELAY[5]PCIE.PIPERX0DATA[12]
CELL_E[12].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[10]
CELL_E[12].IMUX_IMUX_DELAY[7]PCIE.PIPERX0DATA[13]
CELL_E[12].IMUX_IMUX_DELAY[8]PCIE.MIMRXRDATA[11]
CELL_E[12].IMUX_IMUX_DELAY[9]PCIE.PIPERX0DATA[15]
CELL_E[12].IMUX_IMUX_DELAY[10]PCIE.MIMRXRDATA[12]
CELL_E[12].IMUX_IMUX_DELAY[11]PCIE.PIPERX0DATA[14]
CELL_E[12].IMUX_IMUX_DELAY[12]PCIE.MIMRXRDATA[13]
CELL_E[12].IMUX_IMUX_DELAY[13]PCIE.PIPERX4DATA[12]
CELL_E[12].IMUX_IMUX_DELAY[14]PCIE.SCANIN[0]
CELL_E[12].IMUX_IMUX_DELAY[15]PCIE.PIPERX4DATA[14]
CELL_E[12].IMUX_IMUX_DELAY[16]PCIE.CFGERRAERHEADERLOG[85]
CELL_E[12].IMUX_IMUX_DELAY[17]PCIE.PIPERX4CHARISK[1]
CELL_E[12].IMUX_IMUX_DELAY[18]PCIE.CFGERRAERHEADERLOG[86]
CELL_E[12].IMUX_IMUX_DELAY[19]PCIE.CFGERRAERHEADERLOG[87]
CELL_E[12].IMUX_IMUX_DELAY[20]PCIE.CFGERRAERHEADERLOG[88]
CELL_E[12].IMUX_IMUX_DELAY[21]PCIE.PIPERX4DATA[15]
CELL_E[12].OUT_BEL[0]PCIE.TRNRD[24]
CELL_E[12].OUT_BEL[1]PCIE.TRNRD[25]
CELL_E[12].OUT_BEL[2]PCIE.TRNRD[26]
CELL_E[12].OUT_BEL[3]PCIE.TRNRD[27]
CELL_E[12].OUT_BEL[4]PCIE.MIMTXWDATA[27]
CELL_E[12].OUT_BEL[5]PCIE.MIMTXWDATA[28]
CELL_E[12].OUT_BEL[6]PCIE.MIMTXWDATA[29]
CELL_E[12].OUT_BEL[7]PCIE.MIMTXWDATA[30]
CELL_E[12].OUT_BEL[8]PCIE.MIMRXWDATA[60]
CELL_E[12].OUT_BEL[9]PCIE.MIMRXWDATA[61]
CELL_E[12].OUT_BEL[10]PCIE.MIMRXWDATA[62]
CELL_E[12].OUT_BEL[11]PCIE.MIMRXWDATA[63]
CELL_E[12].OUT_BEL[12]PCIE.CFGDO[22]
CELL_E[12].OUT_BEL[13]PCIE.CFGDO[23]
CELL_E[12].OUT_BEL[14]PCIE.CFGDO[24]
CELL_E[12].OUT_BEL[15]PCIE.CFGDO[25]
CELL_E[12].OUT_BEL[16]PCIE.CFGDEVCONTROLNOSNOOPEN
CELL_E[12].OUT_BEL[17]PCIE.CFGDEVCONTROLMAXREADREQ[0]
CELL_E[12].OUT_BEL[18]PCIE.CFGDEVCONTROLMAXREADREQ[1]
CELL_E[12].OUT_BEL[19]PCIE.DBGSCLRC
CELL_E[12].OUT_BEL[20]PCIE.DBGSCLRD
CELL_E[12].OUT_BEL[21]PCIE.DBGVECB[4]
CELL_E[12].OUT_BEL[22]PCIE.DBGVECB[5]
CELL_E[12].OUT_BEL[23]PCIE.DBGVECB[6]
CELL_E[13].IMUX_IMUX_DELAY[0]PCIE.TRNTD[30]
CELL_E[13].IMUX_IMUX_DELAY[1]PCIE.PIPERX4CHANISALIGNED
CELL_E[13].IMUX_IMUX_DELAY[2]PCIE.TRNTD[31]
CELL_E[13].IMUX_IMUX_DELAY[3]PCIE.TRNTD[32]
CELL_E[13].IMUX_IMUX_DELAY[4]PCIE.TRNTD[33]
CELL_E[13].IMUX_IMUX_DELAY[5]PCIE.MIMRXRDATA[14]
CELL_E[13].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[15]
CELL_E[13].IMUX_IMUX_DELAY[7]PCIE.MIMRXRDATA[16]
CELL_E[13].IMUX_IMUX_DELAY[8]PCIE.MIMRXRDATA[17]
CELL_E[13].IMUX_IMUX_DELAY[9]PCIE.SCANIN[1]
CELL_E[13].IMUX_IMUX_DELAY[10]PCIE.CFGERRAERHEADERLOG[89]
CELL_E[13].IMUX_IMUX_DELAY[11]PCIE.CFGERRAERHEADERLOG[90]
CELL_E[13].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[91]
CELL_E[13].IMUX_IMUX_DELAY[13]PCIE.CFGERRAERHEADERLOG[92]
CELL_E[13].IMUX_IMUX_DELAY[14]PCIE.CFGDSN[13]
CELL_E[13].IMUX_IMUX_DELAY[15]PCIE.PIPERX4CHARISK[0]
CELL_E[13].IMUX_IMUX_DELAY[16]PCIE.CFGDSN[14]
CELL_E[13].IMUX_IMUX_DELAY[17]PCIE.CFGDSN[15]
CELL_E[13].IMUX_IMUX_DELAY[18]PCIE.CFGDSN[16]
CELL_E[13].IMUX_IMUX_DELAY[19]PCIE.DRPDADDR[4]
CELL_E[13].IMUX_IMUX_DELAY[21]PCIE.PIPERX0CHANISALIGNED
CELL_E[13].IMUX_IMUX_DELAY[23]PCIE.PIPERX0CHARISK[0]
CELL_E[13].OUT_BEL[0]PCIE.TRNRD[28]
CELL_E[13].OUT_BEL[1]PCIE.TRNRD[29]
CELL_E[13].OUT_BEL[2]PCIE.TRNRD[30]
CELL_E[13].OUT_BEL[3]PCIE.TRNRD[31]
CELL_E[13].OUT_BEL[4]PCIE.MIMTXWDATA[31]
CELL_E[13].OUT_BEL[5]PCIE.MIMTXWDATA[32]
CELL_E[13].OUT_BEL[6]PCIE.MIMTXWDATA[33]
CELL_E[13].OUT_BEL[7]PCIE.MIMTXWDATA[34]
CELL_E[13].OUT_BEL[8]PCIE.MIMRXWDATA[64]
CELL_E[13].OUT_BEL[9]PCIE.MIMRXWDATA[65]
CELL_E[13].OUT_BEL[10]PCIE.MIMRXWDATA[66]
CELL_E[13].OUT_BEL[11]PCIE.MIMRXWDATA[67]
CELL_E[13].OUT_BEL[12]PCIE.CFGDO[26]
CELL_E[13].OUT_BEL[13]PCIE.CFGDO[27]
CELL_E[13].OUT_BEL[14]PCIE.CFGDO[28]
CELL_E[13].OUT_BEL[15]PCIE.CFGDO[29]
CELL_E[13].OUT_BEL[16]PCIE.CFGDEVCONTROLMAXREADREQ[2]
CELL_E[13].OUT_BEL[17]PCIE.CFGLINKSTATUSCURRENTSPEED[0]
CELL_E[13].OUT_BEL[18]PCIE.CFGLINKSTATUSCURRENTSPEED[1]
CELL_E[13].OUT_BEL[19]PCIE.DBGSCLRE
CELL_E[13].OUT_BEL[20]PCIE.DBGSCLRF
CELL_E[13].OUT_BEL[21]PCIE.DBGVECB[7]
CELL_E[13].OUT_BEL[22]PCIE.DBGVECB[8]
CELL_E[13].OUT_BEL[23]PCIE.DBGVECB[9]
CELL_E[14].IMUX_IMUX_DELAY[0]PCIE.TRNTD[34]
CELL_E[14].IMUX_IMUX_DELAY[1]PCIE.PIPERX4STATUS[2]
CELL_E[14].IMUX_IMUX_DELAY[2]PCIE.TRNTD[35]
CELL_E[14].IMUX_IMUX_DELAY[3]PCIE.PIPERX4STATUS[0]
CELL_E[14].IMUX_IMUX_DELAY[4]PCIE.TRNTD[36]
CELL_E[14].IMUX_IMUX_DELAY[5]PCIE.TRNTD[37]
CELL_E[14].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[18]
CELL_E[14].IMUX_IMUX_DELAY[7]PCIE.PIPERX4STATUS[1]
CELL_E[14].IMUX_IMUX_DELAY[8]PCIE.MIMRXRDATA[19]
CELL_E[14].IMUX_IMUX_DELAY[9]PCIE.MIMRXRDATA[20]
CELL_E[14].IMUX_IMUX_DELAY[10]PCIE.MIMRXRDATA[21]
CELL_E[14].IMUX_IMUX_DELAY[11]PCIE.PIPERX0PHYSTATUS
CELL_E[14].IMUX_IMUX_DELAY[12]PCIE.SCANIN[2]
CELL_E[14].IMUX_IMUX_DELAY[13]PCIE.CFGERRAERHEADERLOG[93]
CELL_E[14].IMUX_IMUX_DELAY[14]PCIE.CFGERRAERHEADERLOG[94]
CELL_E[14].IMUX_IMUX_DELAY[15]PCIE.PIPERX4PHYSTATUS
CELL_E[14].IMUX_IMUX_DELAY[16]PCIE.CFGERRAERHEADERLOG[95]
CELL_E[14].IMUX_IMUX_DELAY[17]PCIE.CFGERRAERHEADERLOG[96]
CELL_E[14].IMUX_IMUX_DELAY[18]PCIE.CFGDSN[17]
CELL_E[14].IMUX_IMUX_DELAY[19]PCIE.PIPERX0STATUS[1]
CELL_E[14].IMUX_IMUX_DELAY[21]PCIE.PIPERX0STATUS[2]
CELL_E[14].IMUX_IMUX_DELAY[23]PCIE.PIPERX0STATUS[0]
CELL_E[14].OUT_BEL[0]PCIE.TRNRD[32]
CELL_E[14].OUT_BEL[1]PCIE.PIPETX0ELECIDLE
CELL_E[14].OUT_BEL[2]PCIE.TRNRD[33]
CELL_E[14].OUT_BEL[3]PCIE.TRNRD[34]
CELL_E[14].OUT_BEL[4]PCIE.TRNRD[35]
CELL_E[14].OUT_BEL[5]PCIE.PIPETX4ELECIDLE
CELL_E[14].OUT_BEL[6]PCIE.MIMTXWDATA[35]
CELL_E[14].OUT_BEL[7]PCIE.MIMTXWDATA[36]
CELL_E[14].OUT_BEL[8]PCIE.MIMTXWDATA[37]
CELL_E[14].OUT_BEL[9]PCIE.MIMTXWDATA[38]
CELL_E[14].OUT_BEL[10]PCIE.MIMRXWADDR[0]
CELL_E[14].OUT_BEL[11]PCIE.MIMRXWADDR[1]
CELL_E[14].OUT_BEL[12]PCIE.MIMRXWADDR[2]
CELL_E[14].OUT_BEL[13]PCIE.MIMRXWADDR[3]
CELL_E[14].OUT_BEL[14]PCIE.CFGDO[30]
CELL_E[14].OUT_BEL[15]PCIE.DBGSCLRG
CELL_E[14].OUT_BEL[16]PCIE.DBGSCLRH
CELL_E[14].OUT_BEL[17]PCIE.PIPETX4POWERDOWN[0]
CELL_E[14].OUT_BEL[18]PCIE.DBGVECB[10]
CELL_E[14].OUT_BEL[19]PCIE.PIPETX4POWERDOWN[1]
CELL_E[14].OUT_BEL[20]PCIE.DBGVECB[11]
CELL_E[14].OUT_BEL[21]PCIE.PIPETX0POWERDOWN[0]
CELL_E[14].OUT_BEL[22]PCIE.DBGVECB[12]
CELL_E[14].OUT_BEL[23]PCIE.PIPETX0POWERDOWN[1]
CELL_E[15].IMUX_IMUX_DELAY[0]PCIE.TRNTD[38]
CELL_E[15].IMUX_IMUX_DELAY[1]PCIE.TRNTD[39]
CELL_E[15].IMUX_IMUX_DELAY[2]PCIE.TRNTD[40]
CELL_E[15].IMUX_IMUX_DELAY[3]PCIE.TRNTD[41]
CELL_E[15].IMUX_IMUX_DELAY[4]PCIE.MIMRXRDATA[22]
CELL_E[15].IMUX_IMUX_DELAY[5]PCIE.PIPERX4ELECIDLE
CELL_E[15].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[23]
CELL_E[15].IMUX_IMUX_DELAY[7]PCIE.MIMRXRDATA[24]
CELL_E[15].IMUX_IMUX_DELAY[8]PCIE.MIMRXRDATA[25]
CELL_E[15].IMUX_IMUX_DELAY[9]PCIE.SCANIN[3]
CELL_E[15].IMUX_IMUX_DELAY[10]PCIE.CFGERRAERHEADERLOG[97]
CELL_E[15].IMUX_IMUX_DELAY[11]PCIE.PIPERX4VALID
CELL_E[15].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[98]
CELL_E[15].IMUX_IMUX_DELAY[13]PCIE.CFGERRAERHEADERLOG[99]
CELL_E[15].IMUX_IMUX_DELAY[14]PCIE.CFGERRAERHEADERLOG[100]
CELL_E[15].IMUX_IMUX_DELAY[15]PCIE.CFGDSN[18]
CELL_E[15].IMUX_IMUX_DELAY[16]PCIE.CFGDSN[19]
CELL_E[15].IMUX_IMUX_DELAY[17]PCIE.CFGDSN[20]
CELL_E[15].IMUX_IMUX_DELAY[18]PCIE.CFGDSN[21]
CELL_E[15].IMUX_IMUX_DELAY[19]PCIE.PIPERX0VALID
CELL_E[15].IMUX_IMUX_DELAY[20]PCIE.DRPDADDR[5]
CELL_E[15].IMUX_IMUX_DELAY[21]PCIE.PIPERX0ELECIDLE
CELL_E[15].OUT_BEL[0]PCIE.TRNRD[36]
CELL_E[15].OUT_BEL[1]PCIE.TRNRD[37]
CELL_E[15].OUT_BEL[2]PCIE.TRNRD[38]
CELL_E[15].OUT_BEL[3]PCIE.TRNRD[39]
CELL_E[15].OUT_BEL[4]PCIE.MIMTXWDATA[39]
CELL_E[15].OUT_BEL[5]PCIE.MIMTXWDATA[40]
CELL_E[15].OUT_BEL[6]PCIE.MIMTXWDATA[41]
CELL_E[15].OUT_BEL[7]PCIE.MIMTXWDATA[42]
CELL_E[15].OUT_BEL[8]PCIE.MIMRXWADDR[4]
CELL_E[15].OUT_BEL[9]PCIE.MIMRXWADDR[5]
CELL_E[15].OUT_BEL[10]PCIE.MIMRXWADDR[6]
CELL_E[15].OUT_BEL[11]PCIE.MIMRXWADDR[7]
CELL_E[15].OUT_BEL[12]PCIE.CFGDO[31]
CELL_E[15].OUT_BEL[13]PCIE.DBGSCLRI
CELL_E[15].OUT_BEL[14]PCIE.DBGSCLRJ
CELL_E[15].OUT_BEL[15]PCIE.DBGSCLRK
CELL_E[15].OUT_BEL[16]PCIE.PIPETX0COMPLIANCE
CELL_E[15].OUT_BEL[17]PCIE.DBGVECB[13]
CELL_E[15].OUT_BEL[18]PCIE.PIPETX0CHARISK[0]
CELL_E[15].OUT_BEL[19]PCIE.PIPETX4CHARISK[1]
CELL_E[15].OUT_BEL[20]PCIE.PIPETX4COMPLIANCE
CELL_E[15].OUT_BEL[21]PCIE.DBGVECB[14]
CELL_E[15].OUT_BEL[22]PCIE.PIPETX4CHARISK[0]
CELL_E[15].OUT_BEL[23]PCIE.PIPETX0CHARISK[1]
CELL_E[16].IMUX_IMUX_DELAY[0]PCIE.TRNTD[42]
CELL_E[16].IMUX_IMUX_DELAY[1]PCIE.TRNTD[43]
CELL_E[16].IMUX_IMUX_DELAY[2]PCIE.TRNTD[44]
CELL_E[16].IMUX_IMUX_DELAY[3]PCIE.TRNTD[45]
CELL_E[16].IMUX_IMUX_DELAY[4]PCIE.MIMRXRDATA[26]
CELL_E[16].IMUX_IMUX_DELAY[5]PCIE.MIMRXRDATA[27]
CELL_E[16].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[28]
CELL_E[16].IMUX_IMUX_DELAY[7]PCIE.MIMRXRDATA[29]
CELL_E[16].IMUX_IMUX_DELAY[8]PCIE.SCANIN[4]
CELL_E[16].IMUX_IMUX_DELAY[9]PCIE.CFGERRAERHEADERLOG[101]
CELL_E[16].IMUX_IMUX_DELAY[10]PCIE.CFGERRAERHEADERLOG[102]
CELL_E[16].IMUX_IMUX_DELAY[11]PCIE.CFGERRAERHEADERLOG[103]
CELL_E[16].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[104]
CELL_E[16].IMUX_IMUX_DELAY[13]PCIE.CFGDSN[22]
CELL_E[16].IMUX_IMUX_DELAY[14]PCIE.CFGDSN[23]
CELL_E[16].IMUX_IMUX_DELAY[15]PCIE.CFGDSN[24]
CELL_E[16].IMUX_IMUX_DELAY[16]PCIE.CFGDSN[25]
CELL_E[16].IMUX_IMUX_DELAY[17]PCIE.DRPDADDR[6]
CELL_E[16].IMUX_IMUX_DELAY[18]PCIE.DRPDADDR[7]
CELL_E[16].IMUX_IMUX_DELAY[19]PCIE.DRPDADDR[8]
CELL_E[16].IMUX_IMUX_DELAY[20]PCIE.DRPDI[0]
CELL_E[16].IMUX_IMUX_DELAY[21]PCIE.DBGSUBMODE
CELL_E[16].OUT_BEL[0]PCIE.TRNRD[40]
CELL_E[16].OUT_BEL[1]PCIE.TRNRD[41]
CELL_E[16].OUT_BEL[2]PCIE.PIPETX4DATA[13]
CELL_E[16].OUT_BEL[3]PCIE.TRNRD[42]
CELL_E[16].OUT_BEL[4]PCIE.TRNRD[43]
CELL_E[16].OUT_BEL[5]PCIE.MIMTXWDATA[43]
CELL_E[16].OUT_BEL[6]PCIE.PIPETX0DATA[13]
CELL_E[16].OUT_BEL[7]PCIE.MIMTXWDATA[44]
CELL_E[16].OUT_BEL[8]PCIE.CFGRDWRDONEN
CELL_E[16].OUT_BEL[9]PCIE.MIMRXWADDR[8]
CELL_E[16].OUT_BEL[10]PCIE.MIMRXWADDR[9]
CELL_E[16].OUT_BEL[11]PCIE.MIMRXWADDR[10]
CELL_E[16].OUT_BEL[12]PCIE.MIMRXWADDR[11]
CELL_E[16].OUT_BEL[13]PCIE.DBGVECB[15]
CELL_E[16].OUT_BEL[14]PCIE.DBGVECB[16]
CELL_E[16].OUT_BEL[15]PCIE.DBGVECB[17]
CELL_E[16].OUT_BEL[16]PCIE.PIPETX0DATA[12]
CELL_E[16].OUT_BEL[17]PCIE.PIPETX4DATA[15]
CELL_E[16].OUT_BEL[18]PCIE.DBGVECB[18]
CELL_E[16].OUT_BEL[19]PCIE.PIPETX4DATA[14]
CELL_E[16].OUT_BEL[20]PCIE.PIPETX4DATA[12]
CELL_E[16].OUT_BEL[21]PCIE.PIPETX0DATA[15]
CELL_E[16].OUT_BEL[22]PCIE.PLDBGVEC[0]
CELL_E[16].OUT_BEL[23]PCIE.PIPETX0DATA[14]
CELL_E[17].IMUX_IMUX_DELAY[0]PCIE.TRNTD[46]
CELL_E[17].IMUX_IMUX_DELAY[1]PCIE.TRNTD[47]
CELL_E[17].IMUX_IMUX_DELAY[2]PCIE.TRNTD[48]
CELL_E[17].IMUX_IMUX_DELAY[3]PCIE.TRNTD[49]
CELL_E[17].IMUX_IMUX_DELAY[4]PCIE.MIMRXRDATA[30]
CELL_E[17].IMUX_IMUX_DELAY[5]PCIE.MIMRXRDATA[31]
CELL_E[17].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[32]
CELL_E[17].IMUX_IMUX_DELAY[7]PCIE.MIMRXRDATA[33]
CELL_E[17].IMUX_IMUX_DELAY[8]PCIE.SCANIN[5]
CELL_E[17].IMUX_IMUX_DELAY[9]PCIE.CFGERRAERHEADERLOG[105]
CELL_E[17].IMUX_IMUX_DELAY[10]PCIE.CFGERRAERHEADERLOG[106]
CELL_E[17].IMUX_IMUX_DELAY[11]PCIE.CFGERRAERHEADERLOG[107]
CELL_E[17].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[108]
CELL_E[17].IMUX_IMUX_DELAY[13]PCIE.CFGDSN[26]
CELL_E[17].IMUX_IMUX_DELAY[14]PCIE.CFGDSN[27]
CELL_E[17].IMUX_IMUX_DELAY[15]PCIE.CFGDSN[28]
CELL_E[17].IMUX_IMUX_DELAY[16]PCIE.CFGDSN[29]
CELL_E[17].IMUX_IMUX_DELAY[17]PCIE.DRPDI[1]
CELL_E[17].IMUX_IMUX_DELAY[18]PCIE.DRPDI[2]
CELL_E[17].IMUX_IMUX_DELAY[19]PCIE.DRPDI[3]
CELL_E[17].IMUX_IMUX_DELAY[20]PCIE.DRPDI[4]
CELL_E[17].IMUX_IMUX_DELAY[21]PCIE.PLDBGMODE[0]
CELL_E[17].OUT_BEL[0]PCIE.TRNRD[44]
CELL_E[17].OUT_BEL[1]PCIE.PIPETX0DATA[11]
CELL_E[17].OUT_BEL[2]PCIE.PIPETX4DATA[8]
CELL_E[17].OUT_BEL[3]PCIE.TRNRD[45]
CELL_E[17].OUT_BEL[4]PCIE.CFGERRAERHEADERLOGSETN
CELL_E[17].OUT_BEL[5]PCIE.PIPETX4DATA[11]
CELL_E[17].OUT_BEL[6]PCIE.PIPETX0DATA[8]
CELL_E[17].OUT_BEL[7]PCIE.MIMRXWADDR[12]
CELL_E[17].OUT_BEL[8]PCIE.MIMRXWEN
CELL_E[17].OUT_BEL[9]PCIE.MIMRXRADDR[0]
CELL_E[17].OUT_BEL[10]PCIE.MIMRXRADDR[1]
CELL_E[17].OUT_BEL[11]PCIE.DBGVECB[19]
CELL_E[17].OUT_BEL[12]PCIE.DBGVECB[20]
CELL_E[17].OUT_BEL[13]PCIE.DBGVECB[21]
CELL_E[17].OUT_BEL[14]PCIE.DBGVECB[22]
CELL_E[17].OUT_BEL[15]PCIE.PLDBGVEC[1]
CELL_E[17].OUT_BEL[16]PCIE.PIPETX0DATA[7]
CELL_E[17].OUT_BEL[17]PCIE.PIPETX4DATA[10]
CELL_E[17].OUT_BEL[18]PCIE.PIPETX0DATA[6]
CELL_E[17].OUT_BEL[19]PCIE.PIPETX4DATA[9]
CELL_E[17].OUT_BEL[20]PCIE.PIPETX4DATA[7]
CELL_E[17].OUT_BEL[21]PCIE.PIPETX0DATA[10]
CELL_E[17].OUT_BEL[22]PCIE.PIPETX4DATA[6]
CELL_E[17].OUT_BEL[23]PCIE.PIPETX0DATA[9]
CELL_E[18].IMUX_IMUX_DELAY[0]PCIE.TRNTD[50]
CELL_E[18].IMUX_IMUX_DELAY[1]PCIE.TRNTD[51]
CELL_E[18].IMUX_IMUX_DELAY[2]PCIE.TRNTD[52]
CELL_E[18].IMUX_IMUX_DELAY[3]PCIE.TRNTD[53]
CELL_E[18].IMUX_IMUX_DELAY[4]PCIE.MIMRXRDATA[34]
CELL_E[18].IMUX_IMUX_DELAY[5]PCIE.MIMRXRDATA[35]
CELL_E[18].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[36]
CELL_E[18].IMUX_IMUX_DELAY[7]PCIE.MIMRXRDATA[37]
CELL_E[18].IMUX_IMUX_DELAY[8]PCIE.SCANIN[6]
CELL_E[18].IMUX_IMUX_DELAY[9]PCIE.CFGERRAERHEADERLOG[109]
CELL_E[18].IMUX_IMUX_DELAY[10]PCIE.CFGERRAERHEADERLOG[110]
CELL_E[18].IMUX_IMUX_DELAY[11]PCIE.CFGERRAERHEADERLOG[111]
CELL_E[18].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[112]
CELL_E[18].IMUX_IMUX_DELAY[13]PCIE.CFGDSN[30]
CELL_E[18].IMUX_IMUX_DELAY[14]PCIE.CFGDSN[31]
CELL_E[18].IMUX_IMUX_DELAY[15]PCIE.CFGDSN[32]
CELL_E[18].IMUX_IMUX_DELAY[16]PCIE.CFGDSN[33]
CELL_E[18].IMUX_IMUX_DELAY[17]PCIE.DRPDI[5]
CELL_E[18].IMUX_IMUX_DELAY[18]PCIE.DRPDI[6]
CELL_E[18].IMUX_IMUX_DELAY[19]PCIE.DRPDI[7]
CELL_E[18].IMUX_IMUX_DELAY[20]PCIE.DRPDI[8]
CELL_E[18].IMUX_IMUX_DELAY[21]PCIE.PLDBGMODE[1]
CELL_E[18].OUT_BEL[0]PCIE.TRNRD[46]
CELL_E[18].OUT_BEL[1]PCIE.PIPETX0DATA[3]
CELL_E[18].OUT_BEL[2]PCIE.PIPETX4DATA[4]
CELL_E[18].OUT_BEL[3]PCIE.TRNRD[47]
CELL_E[18].OUT_BEL[4]PCIE.CFGERRCPLRDYN
CELL_E[18].OUT_BEL[5]PCIE.PIPETX4DATA[3]
CELL_E[18].OUT_BEL[6]PCIE.PIPETX0DATA[4]
CELL_E[18].OUT_BEL[7]PCIE.MIMRXRADDR[2]
CELL_E[18].OUT_BEL[8]PCIE.MIMRXRADDR[3]
CELL_E[18].OUT_BEL[9]PCIE.MIMRXRADDR[4]
CELL_E[18].OUT_BEL[10]PCIE.MIMRXRADDR[5]
CELL_E[18].OUT_BEL[11]PCIE.DBGVECB[23]
CELL_E[18].OUT_BEL[12]PCIE.DBGVECB[24]
CELL_E[18].OUT_BEL[13]PCIE.DBGVECB[25]
CELL_E[18].OUT_BEL[14]PCIE.DBGVECB[26]
CELL_E[18].OUT_BEL[15]PCIE.PLDBGVEC[2]
CELL_E[18].OUT_BEL[16]PCIE.PIPETX0DATA[0]
CELL_E[18].OUT_BEL[17]PCIE.PIPETX4DATA[1]
CELL_E[18].OUT_BEL[18]PCIE.PIPETX0DATA[5]
CELL_E[18].OUT_BEL[19]PCIE.PIPETX4DATA[2]
CELL_E[18].OUT_BEL[20]PCIE.PIPETX4DATA[0]
CELL_E[18].OUT_BEL[21]PCIE.PIPETX0DATA[1]
CELL_E[18].OUT_BEL[22]PCIE.PIPETX4DATA[5]
CELL_E[18].OUT_BEL[23]PCIE.PIPETX0DATA[2]
CELL_E[19].IMUX_IMUX_DELAY[0]PCIE.TRNTD[54]
CELL_E[19].IMUX_IMUX_DELAY[1]PCIE.TRNTD[55]
CELL_E[19].IMUX_IMUX_DELAY[2]PCIE.TRNTD[56]
CELL_E[19].IMUX_IMUX_DELAY[3]PCIE.TRNTD[57]
CELL_E[19].IMUX_IMUX_DELAY[4]PCIE.MIMRXRDATA[38]
CELL_E[19].IMUX_IMUX_DELAY[5]PCIE.MIMRXRDATA[39]
CELL_E[19].IMUX_IMUX_DELAY[6]PCIE.MIMRXRDATA[40]
CELL_E[19].IMUX_IMUX_DELAY[7]PCIE.MIMRXRDATA[41]
CELL_E[19].IMUX_IMUX_DELAY[8]PCIE.SCANIN[7]
CELL_E[19].IMUX_IMUX_DELAY[9]PCIE.CFGERRAERHEADERLOG[113]
CELL_E[19].IMUX_IMUX_DELAY[10]PCIE.CFGERRAERHEADERLOG[114]
CELL_E[19].IMUX_IMUX_DELAY[11]PCIE.CFGERRAERHEADERLOG[115]
CELL_E[19].IMUX_IMUX_DELAY[12]PCIE.CFGERRAERHEADERLOG[116]
CELL_E[19].IMUX_IMUX_DELAY[13]PCIE.CFGDSN[34]
CELL_E[19].IMUX_IMUX_DELAY[14]PCIE.CFGDSN[35]
CELL_E[19].IMUX_IMUX_DELAY[15]PCIE.CFGDSN[36]
CELL_E[19].IMUX_IMUX_DELAY[16]PCIE.CFGDSN[37]
CELL_E[19].IMUX_IMUX_DELAY[17]PCIE.DRPDI[9]
CELL_E[19].IMUX_IMUX_DELAY[18]PCIE.DRPDI[10]
CELL_E[19].IMUX_IMUX_DELAY[19]PCIE.DRPDI[11]
CELL_E[19].IMUX_IMUX_DELAY[20]PCIE.DRPDI[12]
CELL_E[19].IMUX_IMUX_DELAY[21]PCIE.PLDBGMODE[2]
CELL_E[19].OUT_BEL[0]PCIE.TRNRD[48]
CELL_E[19].OUT_BEL[1]PCIE.TRNRD[49]
CELL_E[19].OUT_BEL[2]PCIE.TRNRD[50]
CELL_E[19].OUT_BEL[3]PCIE.TRNRD[51]
CELL_E[19].OUT_BEL[4]PCIE.MIMTXWDATA[45]
CELL_E[19].OUT_BEL[5]PCIE.MIMTXWDATA[46]
CELL_E[19].OUT_BEL[6]PCIE.MIMTXWDATA[47]
CELL_E[19].OUT_BEL[7]PCIE.MIMTXWDATA[48]
CELL_E[19].OUT_BEL[8]PCIE.MIMRXRADDR[6]
CELL_E[19].OUT_BEL[9]PCIE.MIMRXRADDR[7]
CELL_E[19].OUT_BEL[10]PCIE.MIMRXRADDR[8]
CELL_E[19].OUT_BEL[11]PCIE.MIMRXRADDR[9]
CELL_E[19].OUT_BEL[12]PCIE.CFGINTERRUPTRDYN
CELL_E[19].OUT_BEL[13]PCIE.CFGINTERRUPTMMENABLE[0]
CELL_E[19].OUT_BEL[14]PCIE.CFGINTERRUPTMMENABLE[1]
CELL_E[19].OUT_BEL[15]PCIE.CFGINTERRUPTMMENABLE[2]
CELL_E[19].OUT_BEL[16]PCIE.CFGLINKSTATUSNEGOTIATEDWIDTH[0]
CELL_E[19].OUT_BEL[17]PCIE.CFGLINKSTATUSNEGOTIATEDWIDTH[1]
CELL_E[19].OUT_BEL[18]PCIE.CFGLINKSTATUSNEGOTIATEDWIDTH[2]
CELL_E[19].OUT_BEL[19]PCIE.PLDBGVEC[3]
CELL_E[19].OUT_BEL[20]PCIE.PLDBGVEC[4]
CELL_E[19].OUT_BEL[21]PCIE.DBGVECB[27]
CELL_E[19].OUT_BEL[22]PCIE.DBGVECB[28]
CELL_E[19].OUT_BEL[23]PCIE.DBGVECB[29]

Bitstream

virtex6 PCIE rect MAIN[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[5] bit 14 PCIE: BAR0 bit 14 PCIE: DRP[5] bit 15 PCIE: BAR0 bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[5] bit 12 PCIE: BAR0 bit 12 PCIE: DRP[5] bit 13 PCIE: BAR0 bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[5] bit 10 PCIE: BAR0 bit 10 PCIE: DRP[5] bit 11 PCIE: BAR0 bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[5] bit 8 PCIE: BAR0 bit 8 PCIE: DRP[5] bit 9 PCIE: BAR0 bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[5] bit 6 PCIE: BAR0 bit 6 PCIE: DRP[5] bit 7 PCIE: BAR0 bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[5] bit 4 PCIE: BAR0 bit 4 PCIE: DRP[5] bit 5 PCIE: BAR0 bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[5] bit 2 PCIE: BAR0 bit 2 PCIE: DRP[5] bit 3 PCIE: BAR0 bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[5] bit 0 PCIE: BAR0 bit 0 PCIE: DRP[5] bit 1 PCIE: BAR0 bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[4] bit 14 PCIE: DRP[4] bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[4] bit 12 PCIE: AER_CAP_ON PCIE: DRP[4] bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[4] bit 10 PCIE: AER_CAP_NEXTPTR bit 10 PCIE: DRP[4] bit 11 PCIE: AER_CAP_NEXTPTR bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[4] bit 8 PCIE: AER_CAP_NEXTPTR bit 8 PCIE: DRP[4] bit 9 PCIE: AER_CAP_NEXTPTR bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[4] bit 6 PCIE: AER_CAP_NEXTPTR bit 6 PCIE: DRP[4] bit 7 PCIE: AER_CAP_NEXTPTR bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[4] bit 4 PCIE: AER_CAP_NEXTPTR bit 4 PCIE: DRP[4] bit 5 PCIE: AER_CAP_NEXTPTR bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[4] bit 2 PCIE: AER_CAP_NEXTPTR bit 2 PCIE: DRP[4] bit 3 PCIE: AER_CAP_NEXTPTR bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[4] bit 0 PCIE: AER_CAP_NEXTPTR bit 0 PCIE: DRP[4] bit 1 PCIE: AER_CAP_NEXTPTR bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[3] bit 14 PCIE: DRP[3] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[3] bit 12 PCIE: DRP[3] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[3] bit 10 PCIE: AER_BASE_PTR bit 10 PCIE: DRP[3] bit 11 PCIE: AER_BASE_PTR bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[3] bit 8 PCIE: AER_BASE_PTR bit 8 PCIE: DRP[3] bit 9 PCIE: AER_BASE_PTR bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[3] bit 6 PCIE: AER_BASE_PTR bit 6 PCIE: DRP[3] bit 7 PCIE: AER_BASE_PTR bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[3] bit 4 PCIE: AER_BASE_PTR bit 4 PCIE: DRP[3] bit 5 PCIE: AER_BASE_PTR bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[3] bit 2 PCIE: AER_BASE_PTR bit 2 PCIE: DRP[3] bit 3 PCIE: AER_BASE_PTR bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[3] bit 0 PCIE: AER_BASE_PTR bit 0 PCIE: DRP[3] bit 1 PCIE: AER_BASE_PTR bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[2] bit 14 PCIE: AER_CAP_VERSION bit 3 PCIE: DRP[2] bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[2] bit 12 PCIE: AER_CAP_VERSION bit 1 PCIE: DRP[2] bit 13 PCIE: AER_CAP_VERSION bit 2
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[2] bit 10 PCIE: AER_CAP_PERMIT_ROOTERR_UPDATE PCIE: DRP[2] bit 11 PCIE: AER_CAP_VERSION bit 0
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[2] bit 8 PCIE: AER_CAP_INT_MSG_NUM_MSIX bit 3 PCIE: DRP[2] bit 9 PCIE: AER_CAP_INT_MSG_NUM_MSIX bit 4
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[2] bit 6 PCIE: AER_CAP_INT_MSG_NUM_MSIX bit 1 PCIE: DRP[2] bit 7 PCIE: AER_CAP_INT_MSG_NUM_MSIX bit 2
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[2] bit 4 PCIE: AER_CAP_INT_MSG_NUM_MSI bit 4 PCIE: DRP[2] bit 5 PCIE: AER_CAP_INT_MSG_NUM_MSIX bit 0
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[2] bit 2 PCIE: AER_CAP_INT_MSG_NUM_MSI bit 2 PCIE: DRP[2] bit 3 PCIE: AER_CAP_INT_MSG_NUM_MSI bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[2] bit 0 PCIE: AER_CAP_INT_MSG_NUM_MSI bit 0 PCIE: DRP[2] bit 1 PCIE: AER_CAP_INT_MSG_NUM_MSI bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[1] bit 14 PCIE: AER_CAP_ID bit 14 PCIE: DRP[1] bit 15 PCIE: AER_CAP_ID bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[1] bit 12 PCIE: AER_CAP_ID bit 12 PCIE: DRP[1] bit 13 PCIE: AER_CAP_ID bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[1] bit 10 PCIE: AER_CAP_ID bit 10 PCIE: DRP[1] bit 11 PCIE: AER_CAP_ID bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[1] bit 8 PCIE: AER_CAP_ID bit 8 PCIE: DRP[1] bit 9 PCIE: AER_CAP_ID bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[1] bit 6 PCIE: AER_CAP_ID bit 6 PCIE: DRP[1] bit 7 PCIE: AER_CAP_ID bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[1] bit 4 PCIE: AER_CAP_ID bit 4 PCIE: DRP[1] bit 5 PCIE: AER_CAP_ID bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[1] bit 2 PCIE: AER_CAP_ID bit 2 PCIE: DRP[1] bit 3 PCIE: AER_CAP_ID bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[1] bit 0 PCIE: AER_CAP_ID bit 0 PCIE: DRP[1] bit 1 PCIE: AER_CAP_ID bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[0] bit 14 PCIE: DRP[0] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[0] bit 12 PCIE: DRP[0] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[0] bit 10 PCIE: DRP[0] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[0] bit 8 PCIE: DRP[0] bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[0] bit 6 PCIE: DRP[0] bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[0] bit 4 PCIE: DRP[0] bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[0] bit 2 PCIE: DRP[0] bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[0] bit 0 PCIE: AER_CAP_ECRC_CHECK_CAPABLE PCIE: DRP[0] bit 1 PCIE: AER_CAP_ECRC_GEN_CAPABLE
virtex6 PCIE rect MAIN[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[11] bit 14 PCIE: BAR3 bit 14 PCIE: DRP[11] bit 15 PCIE: BAR3 bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[11] bit 12 PCIE: BAR3 bit 12 PCIE: DRP[11] bit 13 PCIE: BAR3 bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[11] bit 10 PCIE: BAR3 bit 10 PCIE: DRP[11] bit 11 PCIE: BAR3 bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[11] bit 8 PCIE: BAR3 bit 8 PCIE: DRP[11] bit 9 PCIE: BAR3 bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[11] bit 6 PCIE: BAR3 bit 6 PCIE: DRP[11] bit 7 PCIE: BAR3 bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[11] bit 4 PCIE: BAR3 bit 4 PCIE: DRP[11] bit 5 PCIE: BAR3 bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[11] bit 2 PCIE: BAR3 bit 2 PCIE: DRP[11] bit 3 PCIE: BAR3 bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[11] bit 0 PCIE: BAR3 bit 0 PCIE: DRP[11] bit 1 PCIE: BAR3 bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[10] bit 14 PCIE: BAR2 bit 30 PCIE: DRP[10] bit 15 PCIE: BAR2 bit 31
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[10] bit 12 PCIE: BAR2 bit 28 PCIE: DRP[10] bit 13 PCIE: BAR2 bit 29
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[10] bit 10 PCIE: BAR2 bit 26 PCIE: DRP[10] bit 11 PCIE: BAR2 bit 27
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[10] bit 8 PCIE: BAR2 bit 24 PCIE: DRP[10] bit 9 PCIE: BAR2 bit 25
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[10] bit 6 PCIE: BAR2 bit 22 PCIE: DRP[10] bit 7 PCIE: BAR2 bit 23
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[10] bit 4 PCIE: BAR2 bit 20 PCIE: DRP[10] bit 5 PCIE: BAR2 bit 21
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[10] bit 2 PCIE: BAR2 bit 18 PCIE: DRP[10] bit 3 PCIE: BAR2 bit 19
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[10] bit 0 PCIE: BAR2 bit 16 PCIE: DRP[10] bit 1 PCIE: BAR2 bit 17
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[9] bit 14 PCIE: BAR2 bit 14 PCIE: DRP[9] bit 15 PCIE: BAR2 bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[9] bit 12 PCIE: BAR2 bit 12 PCIE: DRP[9] bit 13 PCIE: BAR2 bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[9] bit 10 PCIE: BAR2 bit 10 PCIE: DRP[9] bit 11 PCIE: BAR2 bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[9] bit 8 PCIE: BAR2 bit 8 PCIE: DRP[9] bit 9 PCIE: BAR2 bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[9] bit 6 PCIE: BAR2 bit 6 PCIE: DRP[9] bit 7 PCIE: BAR2 bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[9] bit 4 PCIE: BAR2 bit 4 PCIE: DRP[9] bit 5 PCIE: BAR2 bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[9] bit 2 PCIE: BAR2 bit 2 PCIE: DRP[9] bit 3 PCIE: BAR2 bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[9] bit 0 PCIE: BAR2 bit 0 PCIE: DRP[9] bit 1 PCIE: BAR2 bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[8] bit 14 PCIE: BAR1 bit 30 PCIE: DRP[8] bit 15 PCIE: BAR1 bit 31
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[8] bit 12 PCIE: BAR1 bit 28 PCIE: DRP[8] bit 13 PCIE: BAR1 bit 29
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[8] bit 10 PCIE: BAR1 bit 26 PCIE: DRP[8] bit 11 PCIE: BAR1 bit 27
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[8] bit 8 PCIE: BAR1 bit 24 PCIE: DRP[8] bit 9 PCIE: BAR1 bit 25
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[8] bit 6 PCIE: BAR1 bit 22 PCIE: DRP[8] bit 7 PCIE: BAR1 bit 23
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[8] bit 4 PCIE: BAR1 bit 20 PCIE: DRP[8] bit 5 PCIE: BAR1 bit 21
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[8] bit 2 PCIE: BAR1 bit 18 PCIE: DRP[8] bit 3 PCIE: BAR1 bit 19
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[8] bit 0 PCIE: BAR1 bit 16 PCIE: DRP[8] bit 1 PCIE: BAR1 bit 17
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[7] bit 14 PCIE: BAR1 bit 14 PCIE: DRP[7] bit 15 PCIE: BAR1 bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[7] bit 12 PCIE: BAR1 bit 12 PCIE: DRP[7] bit 13 PCIE: BAR1 bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[7] bit 10 PCIE: BAR1 bit 10 PCIE: DRP[7] bit 11 PCIE: BAR1 bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[7] bit 8 PCIE: BAR1 bit 8 PCIE: DRP[7] bit 9 PCIE: BAR1 bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[7] bit 6 PCIE: BAR1 bit 6 PCIE: DRP[7] bit 7 PCIE: BAR1 bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[7] bit 4 PCIE: BAR1 bit 4 PCIE: DRP[7] bit 5 PCIE: BAR1 bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[7] bit 2 PCIE: BAR1 bit 2 PCIE: DRP[7] bit 3 PCIE: BAR1 bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[7] bit 0 PCIE: BAR1 bit 0 PCIE: DRP[7] bit 1 PCIE: BAR1 bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[6] bit 14 PCIE: BAR0 bit 30 PCIE: DRP[6] bit 15 PCIE: BAR0 bit 31
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[6] bit 12 PCIE: BAR0 bit 28 PCIE: DRP[6] bit 13 PCIE: BAR0 bit 29
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[6] bit 10 PCIE: BAR0 bit 26 PCIE: DRP[6] bit 11 PCIE: BAR0 bit 27
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[6] bit 8 PCIE: BAR0 bit 24 PCIE: DRP[6] bit 9 PCIE: BAR0 bit 25
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[6] bit 6 PCIE: BAR0 bit 22 PCIE: DRP[6] bit 7 PCIE: BAR0 bit 23
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[6] bit 4 PCIE: BAR0 bit 20 PCIE: DRP[6] bit 5 PCIE: BAR0 bit 21
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[6] bit 2 PCIE: BAR0 bit 18 PCIE: DRP[6] bit 3 PCIE: BAR0 bit 19
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[6] bit 0 PCIE: BAR0 bit 16 PCIE: DRP[6] bit 1 PCIE: BAR0 bit 17
virtex6 PCIE rect MAIN[2]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[17] bit 14 PCIE: EXPANSION_ROM bit 14 PCIE: DRP[17] bit 15 PCIE: EXPANSION_ROM bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[17] bit 12 PCIE: EXPANSION_ROM bit 12 PCIE: DRP[17] bit 13 PCIE: EXPANSION_ROM bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[17] bit 10 PCIE: EXPANSION_ROM bit 10 PCIE: DRP[17] bit 11 PCIE: EXPANSION_ROM bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[17] bit 8 PCIE: EXPANSION_ROM bit 8 PCIE: DRP[17] bit 9 PCIE: EXPANSION_ROM bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[17] bit 6 PCIE: EXPANSION_ROM bit 6 PCIE: DRP[17] bit 7 PCIE: EXPANSION_ROM bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[17] bit 4 PCIE: EXPANSION_ROM bit 4 PCIE: DRP[17] bit 5 PCIE: EXPANSION_ROM bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[17] bit 2 PCIE: EXPANSION_ROM bit 2 PCIE: DRP[17] bit 3 PCIE: EXPANSION_ROM bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[17] bit 0 PCIE: EXPANSION_ROM bit 0 PCIE: DRP[17] bit 1 PCIE: EXPANSION_ROM bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[16] bit 14 PCIE: BAR5 bit 30 PCIE: DRP[16] bit 15 PCIE: BAR5 bit 31
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[16] bit 12 PCIE: BAR5 bit 28 PCIE: DRP[16] bit 13 PCIE: BAR5 bit 29
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[16] bit 10 PCIE: BAR5 bit 26 PCIE: DRP[16] bit 11 PCIE: BAR5 bit 27
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[16] bit 8 PCIE: BAR5 bit 24 PCIE: DRP[16] bit 9 PCIE: BAR5 bit 25
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[16] bit 6 PCIE: BAR5 bit 22 PCIE: DRP[16] bit 7 PCIE: BAR5 bit 23
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[16] bit 4 PCIE: BAR5 bit 20 PCIE: DRP[16] bit 5 PCIE: BAR5 bit 21
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[16] bit 2 PCIE: BAR5 bit 18 PCIE: DRP[16] bit 3 PCIE: BAR5 bit 19
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[16] bit 0 PCIE: BAR5 bit 16 PCIE: DRP[16] bit 1 PCIE: BAR5 bit 17
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[15] bit 14 PCIE: BAR5 bit 14 PCIE: DRP[15] bit 15 PCIE: BAR5 bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[15] bit 12 PCIE: BAR5 bit 12 PCIE: DRP[15] bit 13 PCIE: BAR5 bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[15] bit 10 PCIE: BAR5 bit 10 PCIE: DRP[15] bit 11 PCIE: BAR5 bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[15] bit 8 PCIE: BAR5 bit 8 PCIE: DRP[15] bit 9 PCIE: BAR5 bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[15] bit 6 PCIE: BAR5 bit 6 PCIE: DRP[15] bit 7 PCIE: BAR5 bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[15] bit 4 PCIE: BAR5 bit 4 PCIE: DRP[15] bit 5 PCIE: BAR5 bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[15] bit 2 PCIE: BAR5 bit 2 PCIE: DRP[15] bit 3 PCIE: BAR5 bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[15] bit 0 PCIE: BAR5 bit 0 PCIE: DRP[15] bit 1 PCIE: BAR5 bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[14] bit 14 PCIE: BAR4 bit 30 PCIE: DRP[14] bit 15 PCIE: BAR4 bit 31
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[14] bit 12 PCIE: BAR4 bit 28 PCIE: DRP[14] bit 13 PCIE: BAR4 bit 29
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[14] bit 10 PCIE: BAR4 bit 26 PCIE: DRP[14] bit 11 PCIE: BAR4 bit 27
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[14] bit 8 PCIE: BAR4 bit 24 PCIE: DRP[14] bit 9 PCIE: BAR4 bit 25
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[14] bit 6 PCIE: BAR4 bit 22 PCIE: DRP[14] bit 7 PCIE: BAR4 bit 23
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[14] bit 4 PCIE: BAR4 bit 20 PCIE: DRP[14] bit 5 PCIE: BAR4 bit 21
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[14] bit 2 PCIE: BAR4 bit 18 PCIE: DRP[14] bit 3 PCIE: BAR4 bit 19
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[14] bit 0 PCIE: BAR4 bit 16 PCIE: DRP[14] bit 1 PCIE: BAR4 bit 17
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[13] bit 14 PCIE: BAR4 bit 14 PCIE: DRP[13] bit 15 PCIE: BAR4 bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[13] bit 12 PCIE: BAR4 bit 12 PCIE: DRP[13] bit 13 PCIE: BAR4 bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[13] bit 10 PCIE: BAR4 bit 10 PCIE: DRP[13] bit 11 PCIE: BAR4 bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[13] bit 8 PCIE: BAR4 bit 8 PCIE: DRP[13] bit 9 PCIE: BAR4 bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[13] bit 6 PCIE: BAR4 bit 6 PCIE: DRP[13] bit 7 PCIE: BAR4 bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[13] bit 4 PCIE: BAR4 bit 4 PCIE: DRP[13] bit 5 PCIE: BAR4 bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[13] bit 2 PCIE: BAR4 bit 2 PCIE: DRP[13] bit 3 PCIE: BAR4 bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[13] bit 0 PCIE: BAR4 bit 0 PCIE: DRP[13] bit 1 PCIE: BAR4 bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[12] bit 14 PCIE: BAR3 bit 30 PCIE: DRP[12] bit 15 PCIE: BAR3 bit 31
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[12] bit 12 PCIE: BAR3 bit 28 PCIE: DRP[12] bit 13 PCIE: BAR3 bit 29
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[12] bit 10 PCIE: BAR3 bit 26 PCIE: DRP[12] bit 11 PCIE: BAR3 bit 27
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[12] bit 8 PCIE: BAR3 bit 24 PCIE: DRP[12] bit 9 PCIE: BAR3 bit 25
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[12] bit 6 PCIE: BAR3 bit 22 PCIE: DRP[12] bit 7 PCIE: BAR3 bit 23
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[12] bit 4 PCIE: BAR3 bit 20 PCIE: DRP[12] bit 5 PCIE: BAR3 bit 21
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[12] bit 2 PCIE: BAR3 bit 18 PCIE: DRP[12] bit 3 PCIE: BAR3 bit 19
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[12] bit 0 PCIE: BAR3 bit 16 PCIE: DRP[12] bit 1 PCIE: BAR3 bit 17
virtex6 PCIE rect MAIN[3]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[23] bit 14 PCIE: DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE PCIE: DRP[23] bit 15 PCIE: DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[23] bit 12 PCIE: CPL_TIMEOUT_RANGES_SUPPORTED bit 2 PCIE: DRP[23] bit 13 PCIE: CPL_TIMEOUT_RANGES_SUPPORTED bit 3
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[23] bit 10 PCIE: CPL_TIMEOUT_RANGES_SUPPORTED bit 0 PCIE: DRP[23] bit 11 PCIE: CPL_TIMEOUT_RANGES_SUPPORTED bit 1
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[23] bit 8 PCIE: CMD_INTX_IMPLEMENTED PCIE: DRP[23] bit 9 PCIE: CPL_TIMEOUT_DISABLE_SUPPORTED
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[23] bit 6 PCIE: CLASS_CODE bit 22 PCIE: DRP[23] bit 7 PCIE: CLASS_CODE bit 23
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[23] bit 4 PCIE: CLASS_CODE bit 20 PCIE: DRP[23] bit 5 PCIE: CLASS_CODE bit 21
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[23] bit 2 PCIE: CLASS_CODE bit 18 PCIE: DRP[23] bit 3 PCIE: CLASS_CODE bit 19
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[23] bit 0 PCIE: CLASS_CODE bit 16 PCIE: DRP[23] bit 1 PCIE: CLASS_CODE bit 17
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[22] bit 14 PCIE: CLASS_CODE bit 14 PCIE: DRP[22] bit 15 PCIE: CLASS_CODE bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[22] bit 12 PCIE: CLASS_CODE bit 12 PCIE: DRP[22] bit 13 PCIE: CLASS_CODE bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[22] bit 10 PCIE: CLASS_CODE bit 10 PCIE: DRP[22] bit 11 PCIE: CLASS_CODE bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[22] bit 8 PCIE: CLASS_CODE bit 8 PCIE: DRP[22] bit 9 PCIE: CLASS_CODE bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[22] bit 6 PCIE: CLASS_CODE bit 6 PCIE: DRP[22] bit 7 PCIE: CLASS_CODE bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[22] bit 4 PCIE: CLASS_CODE bit 4 PCIE: DRP[22] bit 5 PCIE: CLASS_CODE bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[22] bit 2 PCIE: CLASS_CODE bit 2 PCIE: DRP[22] bit 3 PCIE: CLASS_CODE bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[22] bit 0 PCIE: CLASS_CODE bit 0 PCIE: DRP[22] bit 1 PCIE: CLASS_CODE bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[21] bit 14 PCIE: CARDBUS_CIS_POINTER bit 30 PCIE: DRP[21] bit 15 PCIE: CARDBUS_CIS_POINTER bit 31
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[21] bit 12 PCIE: CARDBUS_CIS_POINTER bit 28 PCIE: DRP[21] bit 13 PCIE: CARDBUS_CIS_POINTER bit 29
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[21] bit 10 PCIE: CARDBUS_CIS_POINTER bit 26 PCIE: DRP[21] bit 11 PCIE: CARDBUS_CIS_POINTER bit 27
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[21] bit 8 PCIE: CARDBUS_CIS_POINTER bit 24 PCIE: DRP[21] bit 9 PCIE: CARDBUS_CIS_POINTER bit 25
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[21] bit 6 PCIE: CARDBUS_CIS_POINTER bit 22 PCIE: DRP[21] bit 7 PCIE: CARDBUS_CIS_POINTER bit 23
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[21] bit 4 PCIE: CARDBUS_CIS_POINTER bit 20 PCIE: DRP[21] bit 5 PCIE: CARDBUS_CIS_POINTER bit 21
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[21] bit 2 PCIE: CARDBUS_CIS_POINTER bit 18 PCIE: DRP[21] bit 3 PCIE: CARDBUS_CIS_POINTER bit 19
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[21] bit 0 PCIE: CARDBUS_CIS_POINTER bit 16 PCIE: DRP[21] bit 1 PCIE: CARDBUS_CIS_POINTER bit 17
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[20] bit 14 PCIE: CARDBUS_CIS_POINTER bit 14 PCIE: DRP[20] bit 15 PCIE: CARDBUS_CIS_POINTER bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[20] bit 12 PCIE: CARDBUS_CIS_POINTER bit 12 PCIE: DRP[20] bit 13 PCIE: CARDBUS_CIS_POINTER bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[20] bit 10 PCIE: CARDBUS_CIS_POINTER bit 10 PCIE: DRP[20] bit 11 PCIE: CARDBUS_CIS_POINTER bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[20] bit 8 PCIE: CARDBUS_CIS_POINTER bit 8 PCIE: DRP[20] bit 9 PCIE: CARDBUS_CIS_POINTER bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[20] bit 6 PCIE: CARDBUS_CIS_POINTER bit 6 PCIE: DRP[20] bit 7 PCIE: CARDBUS_CIS_POINTER bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[20] bit 4 PCIE: CARDBUS_CIS_POINTER bit 4 PCIE: DRP[20] bit 5 PCIE: CARDBUS_CIS_POINTER bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[20] bit 2 PCIE: CARDBUS_CIS_POINTER bit 2 PCIE: DRP[20] bit 3 PCIE: CARDBUS_CIS_POINTER bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[20] bit 0 PCIE: CARDBUS_CIS_POINTER bit 0 PCIE: DRP[20] bit 1 PCIE: CARDBUS_CIS_POINTER bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[19] bit 14 PCIE: DRP[19] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[19] bit 12 PCIE: DRP[19] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[19] bit 10 PCIE: DRP[19] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[19] bit 8 PCIE: DRP[19] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[19] bit 6 PCIE: CAPABILITIES_PTR bit 6 PCIE: DRP[19] bit 7 PCIE: CAPABILITIES_PTR bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[19] bit 4 PCIE: CAPABILITIES_PTR bit 4 PCIE: DRP[19] bit 5 PCIE: CAPABILITIES_PTR bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[19] bit 2 PCIE: CAPABILITIES_PTR bit 2 PCIE: DRP[19] bit 3 PCIE: CAPABILITIES_PTR bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[19] bit 0 PCIE: CAPABILITIES_PTR bit 0 PCIE: DRP[19] bit 1 PCIE: CAPABILITIES_PTR bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[18] bit 14 PCIE: EXPANSION_ROM bit 30 PCIE: DRP[18] bit 15 PCIE: EXPANSION_ROM bit 31
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[18] bit 12 PCIE: EXPANSION_ROM bit 28 PCIE: DRP[18] bit 13 PCIE: EXPANSION_ROM bit 29
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[18] bit 10 PCIE: EXPANSION_ROM bit 26 PCIE: DRP[18] bit 11 PCIE: EXPANSION_ROM bit 27
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[18] bit 8 PCIE: EXPANSION_ROM bit 24 PCIE: DRP[18] bit 9 PCIE: EXPANSION_ROM bit 25
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[18] bit 6 PCIE: EXPANSION_ROM bit 22 PCIE: DRP[18] bit 7 PCIE: EXPANSION_ROM bit 23
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[18] bit 4 PCIE: EXPANSION_ROM bit 20 PCIE: DRP[18] bit 5 PCIE: EXPANSION_ROM bit 21
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[18] bit 2 PCIE: EXPANSION_ROM bit 18 PCIE: DRP[18] bit 3 PCIE: EXPANSION_ROM bit 19
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[18] bit 0 PCIE: EXPANSION_ROM bit 16 PCIE: DRP[18] bit 1 PCIE: EXPANSION_ROM bit 17
virtex6 PCIE rect MAIN[4]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[29] bit 14 PCIE: DRP[29] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[29] bit 12 PCIE: DSN_CAP_ON PCIE: DRP[29] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[29] bit 10 PCIE: DSN_CAP_NEXTPTR bit 10 PCIE: DRP[29] bit 11 PCIE: DSN_CAP_NEXTPTR bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[29] bit 8 PCIE: DSN_CAP_NEXTPTR bit 8 PCIE: DRP[29] bit 9 PCIE: DSN_CAP_NEXTPTR bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[29] bit 6 PCIE: DSN_CAP_NEXTPTR bit 6 PCIE: DRP[29] bit 7 PCIE: DSN_CAP_NEXTPTR bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[29] bit 4 PCIE: DSN_CAP_NEXTPTR bit 4 PCIE: DRP[29] bit 5 PCIE: DSN_CAP_NEXTPTR bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[29] bit 2 PCIE: DSN_CAP_NEXTPTR bit 2 PCIE: DRP[29] bit 3 PCIE: DSN_CAP_NEXTPTR bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[29] bit 0 PCIE: DSN_CAP_NEXTPTR bit 0 PCIE: DRP[29] bit 1 PCIE: DSN_CAP_NEXTPTR bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[28] bit 14 PCIE: DSN_CAP_ID bit 14 PCIE: DRP[28] bit 15 PCIE: DSN_CAP_ID bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[28] bit 12 PCIE: DSN_CAP_ID bit 12 PCIE: DRP[28] bit 13 PCIE: DSN_CAP_ID bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[28] bit 10 PCIE: DSN_CAP_ID bit 10 PCIE: DRP[28] bit 11 PCIE: DSN_CAP_ID bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[28] bit 8 PCIE: DSN_CAP_ID bit 8 PCIE: DRP[28] bit 9 PCIE: DSN_CAP_ID bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[28] bit 6 PCIE: DSN_CAP_ID bit 6 PCIE: DRP[28] bit 7 PCIE: DSN_CAP_ID bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[28] bit 4 PCIE: DSN_CAP_ID bit 4 PCIE: DRP[28] bit 5 PCIE: DSN_CAP_ID bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[28] bit 2 PCIE: DSN_CAP_ID bit 2 PCIE: DRP[28] bit 3 PCIE: DSN_CAP_ID bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[28] bit 0 PCIE: DSN_CAP_ID bit 0 PCIE: DRP[28] bit 1 PCIE: DSN_CAP_ID bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[27] bit 14 PCIE: DRP[27] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[27] bit 12 PCIE: DRP[27] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[27] bit 10 PCIE: DSN_BASE_PTR bit 10 PCIE: DRP[27] bit 11 PCIE: DSN_BASE_PTR bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[27] bit 8 PCIE: DSN_BASE_PTR bit 8 PCIE: DRP[27] bit 9 PCIE: DSN_BASE_PTR bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[27] bit 6 PCIE: DSN_BASE_PTR bit 6 PCIE: DRP[27] bit 7 PCIE: DSN_BASE_PTR bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[27] bit 4 PCIE: DSN_BASE_PTR bit 4 PCIE: DRP[27] bit 5 PCIE: DSN_BASE_PTR bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[27] bit 2 PCIE: DSN_BASE_PTR bit 2 PCIE: DRP[27] bit 3 PCIE: DSN_BASE_PTR bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[27] bit 0 PCIE: DSN_BASE_PTR bit 0 PCIE: DRP[27] bit 1 PCIE: DSN_BASE_PTR bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[26] bit 14 PCIE: DEVICE_ID bit 14 PCIE: DRP[26] bit 15 PCIE: DEVICE_ID bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[26] bit 12 PCIE: DEVICE_ID bit 12 PCIE: DRP[26] bit 13 PCIE: DEVICE_ID bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[26] bit 10 PCIE: DEVICE_ID bit 10 PCIE: DRP[26] bit 11 PCIE: DEVICE_ID bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[26] bit 8 PCIE: DEVICE_ID bit 8 PCIE: DRP[26] bit 9 PCIE: DEVICE_ID bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[26] bit 6 PCIE: DEVICE_ID bit 6 PCIE: DRP[26] bit 7 PCIE: DEVICE_ID bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[26] bit 4 PCIE: DEVICE_ID bit 4 PCIE: DRP[26] bit 5 PCIE: DEVICE_ID bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[26] bit 2 PCIE: DEVICE_ID bit 2 PCIE: DRP[26] bit 3 PCIE: DEVICE_ID bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[26] bit 0 PCIE: DEVICE_ID bit 0 PCIE: DRP[26] bit 1 PCIE: DEVICE_ID bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[25] bit 14 PCIE: DRP[25] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[25] bit 12 PCIE: DRP[25] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[25] bit 10 PCIE: DRP[25] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[25] bit 8 PCIE: DEV_CONTROL_AUX_POWER_SUPPORTED PCIE: DRP[25] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[25] bit 6 PCIE: DEV_CAP_RSVD_31_29 bit 1 PCIE: DRP[25] bit 7 PCIE: DEV_CAP_RSVD_31_29 bit 2
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[25] bit 4 PCIE: DEV_CAP_RSVD_17_16 bit 1 PCIE: DRP[25] bit 5 PCIE: DEV_CAP_RSVD_31_29 bit 0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[25] bit 2 PCIE: DEV_CAP_RSVD_14_12 bit 2 PCIE: DRP[25] bit 3 PCIE: DEV_CAP_RSVD_17_16 bit 0
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[25] bit 0 PCIE: DEV_CAP_RSVD_14_12 bit 0 PCIE: DRP[25] bit 1 PCIE: DEV_CAP_RSVD_14_12 bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[24] bit 14 PCIE: DRP[24] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[24] bit 12 PCIE: DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT bit 1 PCIE: DRP[24] bit 13 PCIE: DEV_CAP_ROLE_BASED_ERROR
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[24] bit 10 PCIE: DEV_CAP_MAX_PAYLOAD_SUPPORTED bit 2 PCIE: DRP[24] bit 11 PCIE: DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT bit 0
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[24] bit 8 PCIE: DEV_CAP_MAX_PAYLOAD_SUPPORTED bit 0 PCIE: DRP[24] bit 9 PCIE: DEV_CAP_MAX_PAYLOAD_SUPPORTED bit 1
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[24] bit 6 PCIE: DEV_CAP_EXT_TAG_SUPPORTED PCIE: DRP[24] bit 7 PCIE: DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[24] bit 4 PCIE: DEV_CAP_ENDPOINT_L1_LATENCY bit 1 PCIE: DRP[24] bit 5 PCIE: DEV_CAP_ENDPOINT_L1_LATENCY bit 2
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[24] bit 2 PCIE: DEV_CAP_ENDPOINT_L0S_LATENCY bit 2 PCIE: DRP[24] bit 3 PCIE: DEV_CAP_ENDPOINT_L1_LATENCY bit 0
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[24] bit 0 PCIE: DEV_CAP_ENDPOINT_L0S_LATENCY bit 0 PCIE: DRP[24] bit 1 PCIE: DEV_CAP_ENDPOINT_L0S_LATENCY bit 1
virtex6 PCIE rect MAIN[5]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[35] bit 14 PCIE: LINK_CAP_RSVD_23_22 bit 0 PCIE: DRP[35] bit 15 PCIE: LINK_CAP_RSVD_23_22 bit 1
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[35] bit 12 PCIE: LINK_CAP_MAX_LINK_SPEED bit 2 PCIE: DRP[35] bit 13 PCIE: LINK_CAP_MAX_LINK_SPEED bit 3
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[35] bit 10 PCIE: LINK_CAP_MAX_LINK_SPEED bit 0 PCIE: DRP[35] bit 11 PCIE: LINK_CAP_MAX_LINK_SPEED bit 1
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[35] bit 8 PCIE: LINK_CAP_L1_EXIT_LATENCY_GEN2 bit 2 PCIE: DRP[35] bit 9 PCIE: LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[35] bit 6 PCIE: LINK_CAP_L1_EXIT_LATENCY_GEN2 bit 0 PCIE: DRP[35] bit 7 PCIE: LINK_CAP_L1_EXIT_LATENCY_GEN2 bit 1
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[35] bit 4 PCIE: LINK_CAP_L1_EXIT_LATENCY_GEN1 bit 1 PCIE: DRP[35] bit 5 PCIE: LINK_CAP_L1_EXIT_LATENCY_GEN1 bit 2
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[35] bit 2 PCIE: LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 bit 2 PCIE: DRP[35] bit 3 PCIE: LINK_CAP_L1_EXIT_LATENCY_GEN1 bit 0
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[35] bit 0 PCIE: LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 bit 0 PCIE: DRP[35] bit 1 PCIE: LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[34] bit 14 PCIE: LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 bit 2 PCIE: DRP[34] bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[34] bit 12 PCIE: LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 bit 0 PCIE: DRP[34] bit 13 PCIE: LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 bit 1
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[34] bit 10 PCIE: LINK_CAP_L0S_EXIT_LATENCY_GEN2 bit 1 PCIE: DRP[34] bit 11 PCIE: LINK_CAP_L0S_EXIT_LATENCY_GEN2 bit 2
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[34] bit 8 PCIE: LINK_CAP_L0S_EXIT_LATENCY_GEN1 bit 2 PCIE: DRP[34] bit 9 PCIE: LINK_CAP_L0S_EXIT_LATENCY_GEN2 bit 0
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[34] bit 6 PCIE: LINK_CAP_L0S_EXIT_LATENCY_GEN1 bit 0 PCIE: DRP[34] bit 7 PCIE: LINK_CAP_L0S_EXIT_LATENCY_GEN1 bit 1
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[34] bit 4 PCIE: LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 bit 1 PCIE: DRP[34] bit 5 PCIE: LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 bit 2
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[34] bit 2 PCIE: LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 bit 2 PCIE: DRP[34] bit 3 PCIE: LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 bit 0
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[34] bit 0 PCIE: LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 bit 0 PCIE: DRP[34] bit 1 PCIE: LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[33] bit 14 PCIE: LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP PCIE: DRP[33] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[33] bit 12 PCIE: LINK_CAP_ASPM_SUPPORT bit 1 PCIE: DRP[33] bit 13 PCIE: LINK_CAP_CLOCK_POWER_MANAGEMENT
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[33] bit 10 PCIE: LAST_CONFIG_DWORD bit 9 PCIE: DRP[33] bit 11 PCIE: LINK_CAP_ASPM_SUPPORT bit 0
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[33] bit 8 PCIE: LAST_CONFIG_DWORD bit 7 PCIE: DRP[33] bit 9 PCIE: LAST_CONFIG_DWORD bit 8
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[33] bit 6 PCIE: LAST_CONFIG_DWORD bit 5 PCIE: DRP[33] bit 7 PCIE: LAST_CONFIG_DWORD bit 6
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[33] bit 4 PCIE: LAST_CONFIG_DWORD bit 3 PCIE: DRP[33] bit 5 PCIE: LAST_CONFIG_DWORD bit 4
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[33] bit 2 PCIE: LAST_CONFIG_DWORD bit 1 PCIE: DRP[33] bit 3 PCIE: LAST_CONFIG_DWORD bit 2
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[33] bit 0 PCIE: IS_SWITCH PCIE: DRP[33] bit 1 PCIE: LAST_CONFIG_DWORD bit 0
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[32] bit 14 PCIE: INTERRUPT_PIN bit 6 PCIE: DRP[32] bit 15 PCIE: INTERRUPT_PIN bit 7
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[32] bit 12 PCIE: INTERRUPT_PIN bit 4 PCIE: DRP[32] bit 13 PCIE: INTERRUPT_PIN bit 5
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[32] bit 10 PCIE: INTERRUPT_PIN bit 2 PCIE: DRP[32] bit 11 PCIE: INTERRUPT_PIN bit 3
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[32] bit 8 PCIE: INTERRUPT_PIN bit 0 PCIE: DRP[32] bit 9 PCIE: INTERRUPT_PIN bit 1
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[32] bit 6 PCIE: HEADER_TYPE bit 6 PCIE: DRP[32] bit 7 PCIE: HEADER_TYPE bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[32] bit 4 PCIE: HEADER_TYPE bit 4 PCIE: DRP[32] bit 5 PCIE: HEADER_TYPE bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[32] bit 2 PCIE: HEADER_TYPE bit 2 PCIE: DRP[32] bit 3 PCIE: HEADER_TYPE bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[32] bit 0 PCIE: HEADER_TYPE bit 0 PCIE: DRP[32] bit 1 PCIE: HEADER_TYPE bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[31] bit 14 PCIE: DRP[31] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[31] bit 12 PCIE: DRP[31] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[31] bit 10 PCIE: DRP[31] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[31] bit 8 PCIE: EXT_CFG_XP_CAP_PTR bit 8 PCIE: DRP[31] bit 9 PCIE: EXT_CFG_XP_CAP_PTR bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[31] bit 6 PCIE: EXT_CFG_XP_CAP_PTR bit 6 PCIE: DRP[31] bit 7 PCIE: EXT_CFG_XP_CAP_PTR bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[31] bit 4 PCIE: EXT_CFG_XP_CAP_PTR bit 4 PCIE: DRP[31] bit 5 PCIE: EXT_CFG_XP_CAP_PTR bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[31] bit 2 PCIE: EXT_CFG_XP_CAP_PTR bit 2 PCIE: DRP[31] bit 3 PCIE: EXT_CFG_XP_CAP_PTR bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[31] bit 0 PCIE: EXT_CFG_XP_CAP_PTR bit 0 PCIE: DRP[31] bit 1 PCIE: EXT_CFG_XP_CAP_PTR bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[30] bit 14 PCIE: DRP[30] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[30] bit 12 PCIE: DRP[30] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[30] bit 10 PCIE: DRP[30] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[30] bit 8 PCIE: EXT_CFG_CAP_PTR bit 4 PCIE: DRP[30] bit 9 PCIE: EXT_CFG_CAP_PTR bit 5
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[30] bit 6 PCIE: EXT_CFG_CAP_PTR bit 2 PCIE: DRP[30] bit 7 PCIE: EXT_CFG_CAP_PTR bit 3
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[30] bit 4 PCIE: EXT_CFG_CAP_PTR bit 0 PCIE: DRP[30] bit 5 PCIE: EXT_CFG_CAP_PTR bit 1
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[30] bit 2 PCIE: DSN_CAP_VERSION bit 2 PCIE: DRP[30] bit 3 PCIE: DSN_CAP_VERSION bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[30] bit 0 PCIE: DSN_CAP_VERSION bit 0 PCIE: DRP[30] bit 1 PCIE: DSN_CAP_VERSION bit 1
virtex6 PCIE rect MAIN[6]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[41] bit 14 PCIE: DRP[41] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[41] bit 12 PCIE: DRP[41] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[41] bit 10 PCIE: MSIX_CAP_PBA_BIR bit 1 PCIE: DRP[41] bit 11 PCIE: MSIX_CAP_PBA_BIR bit 2
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[41] bit 8 PCIE: MSIX_CAP_ON PCIE: DRP[41] bit 9 PCIE: MSIX_CAP_PBA_BIR bit 0
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[41] bit 6 PCIE: MSIX_CAP_NEXTPTR bit 6 PCIE: DRP[41] bit 7 PCIE: MSIX_CAP_NEXTPTR bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[41] bit 4 PCIE: MSIX_CAP_NEXTPTR bit 4 PCIE: DRP[41] bit 5 PCIE: MSIX_CAP_NEXTPTR bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[41] bit 2 PCIE: MSIX_CAP_NEXTPTR bit 2 PCIE: DRP[41] bit 3 PCIE: MSIX_CAP_NEXTPTR bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[41] bit 0 PCIE: MSIX_CAP_NEXTPTR bit 0 PCIE: DRP[41] bit 1 PCIE: MSIX_CAP_NEXTPTR bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[40] bit 14 PCIE: MSIX_CAP_ID bit 6 PCIE: DRP[40] bit 15 PCIE: MSIX_CAP_ID bit 7
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[40] bit 12 PCIE: MSIX_CAP_ID bit 4 PCIE: DRP[40] bit 13 PCIE: MSIX_CAP_ID bit 5
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[40] bit 10 PCIE: MSIX_CAP_ID bit 2 PCIE: DRP[40] bit 11 PCIE: MSIX_CAP_ID bit 3
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[40] bit 8 PCIE: MSIX_CAP_ID bit 0 PCIE: DRP[40] bit 9 PCIE: MSIX_CAP_ID bit 1
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[40] bit 6 PCIE: MSIX_BASE_PTR bit 6 PCIE: DRP[40] bit 7 PCIE: MSIX_BASE_PTR bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[40] bit 4 PCIE: MSIX_BASE_PTR bit 4 PCIE: DRP[40] bit 5 PCIE: MSIX_BASE_PTR bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[40] bit 2 PCIE: MSIX_BASE_PTR bit 2 PCIE: DRP[40] bit 3 PCIE: MSIX_BASE_PTR bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[40] bit 0 PCIE: MSIX_BASE_PTR bit 0 PCIE: DRP[40] bit 1 PCIE: MSIX_BASE_PTR bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[39] bit 14 PCIE: DRP[39] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[39] bit 12 PCIE: DRP[39] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[39] bit 10 PCIE: DRP[39] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[39] bit 8 PCIE: MSI_CAP_ON PCIE: DRP[39] bit 9 PCIE: MSI_CAP_PER_VECTOR_MASKING_CAPABLE
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[39] bit 6 PCIE: MSI_CAP_NEXTPTR bit 6 PCIE: DRP[39] bit 7 PCIE: MSI_CAP_NEXTPTR bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[39] bit 4 PCIE: MSI_CAP_NEXTPTR bit 4 PCIE: DRP[39] bit 5 PCIE: MSI_CAP_NEXTPTR bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[39] bit 2 PCIE: MSI_CAP_NEXTPTR bit 2 PCIE: DRP[39] bit 3 PCIE: MSI_CAP_NEXTPTR bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[39] bit 0 PCIE: MSI_CAP_NEXTPTR bit 0 PCIE: DRP[39] bit 1 PCIE: MSI_CAP_NEXTPTR bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[38] bit 14 PCIE: DRP[38] bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[38] bit 12 PCIE: DRP[38] bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[38] bit 10 PCIE: MSI_CAP_MULTIMSGCAP bit 1 PCIE: DRP[38] bit 11 PCIE: MSI_CAP_MULTIMSGCAP bit 2
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[38] bit 8 PCIE: MSI_CAP_MULTIMSG_EXTENSION bit 0 PCIE: DRP[38] bit 9 PCIE: MSI_CAP_MULTIMSGCAP bit 0
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[38] bit 6 PCIE: MSI_CAP_ID bit 6 PCIE: DRP[38] bit 7 PCIE: MSI_CAP_ID bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[38] bit 4 PCIE: MSI_CAP_ID bit 4 PCIE: DRP[38] bit 5 PCIE: MSI_CAP_ID bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[38] bit 2 PCIE: MSI_CAP_ID bit 2 PCIE: DRP[38] bit 3 PCIE: MSI_CAP_ID bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[38] bit 0 PCIE: MSI_CAP_ID bit 0 PCIE: DRP[38] bit 1 PCIE: MSI_CAP_ID bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[37] bit 14 PCIE: DRP[37] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[37] bit 12 PCIE: DRP[37] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[37] bit 10 PCIE: DRP[37] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[37] bit 8 PCIE: MSI_CAP_64_BIT_ADDR_CAPABLE PCIE: DRP[37] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[37] bit 6 PCIE: MSI_BASE_PTR bit 6 PCIE: DRP[37] bit 7 PCIE: MSI_BASE_PTR bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[37] bit 4 PCIE: MSI_BASE_PTR bit 4 PCIE: DRP[37] bit 5 PCIE: MSI_BASE_PTR bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[37] bit 2 PCIE: MSI_BASE_PTR bit 2 PCIE: DRP[37] bit 3 PCIE: MSI_BASE_PTR bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[37] bit 0 PCIE: MSI_BASE_PTR bit 0 PCIE: DRP[37] bit 1 PCIE: MSI_BASE_PTR bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[36] bit 14 PCIE: DRP[36] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[36] bit 12 PCIE: DRP[36] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[36] bit 10 PCIE: DRP[36] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[36] bit 8 PCIE: LINK_STATUS_SLOT_CLOCK_CONFIG PCIE: DRP[36] bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[36] bit 6 PCIE: LINK_CTRL2_TARGET_LINK_SPEED bit 2 PCIE: DRP[36] bit 7 PCIE: LINK_CTRL2_TARGET_LINK_SPEED bit 3
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[36] bit 4 PCIE: LINK_CTRL2_TARGET_LINK_SPEED bit 0 PCIE: DRP[36] bit 5 PCIE: LINK_CTRL2_TARGET_LINK_SPEED bit 1
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[36] bit 2 PCIE: LINK_CTRL2_DEEMPHASIS PCIE: DRP[36] bit 3 PCIE: LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[36] bit 0 PCIE: LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE PCIE: DRP[36] bit 1 PCIE: LINK_CONTROL_RCB bit 0
virtex6 PCIE rect MAIN[7]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[47] bit 14 PCIE: PCIE_CAP_CAPABILITY_ID bit 6 PCIE: DRP[47] bit 15 PCIE: PCIE_CAP_CAPABILITY_ID bit 7
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[47] bit 12 PCIE: PCIE_CAP_CAPABILITY_ID bit 4 PCIE: DRP[47] bit 13 PCIE: PCIE_CAP_CAPABILITY_ID bit 5
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[47] bit 10 PCIE: PCIE_CAP_CAPABILITY_ID bit 2 PCIE: DRP[47] bit 11 PCIE: PCIE_CAP_CAPABILITY_ID bit 3
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[47] bit 8 PCIE: PCIE_CAP_CAPABILITY_ID bit 0 PCIE: DRP[47] bit 9 PCIE: PCIE_CAP_CAPABILITY_ID bit 1
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[47] bit 6 PCIE: PCIE_BASE_PTR bit 6 PCIE: DRP[47] bit 7 PCIE: PCIE_BASE_PTR bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[47] bit 4 PCIE: PCIE_BASE_PTR bit 4 PCIE: DRP[47] bit 5 PCIE: PCIE_BASE_PTR bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[47] bit 2 PCIE: PCIE_BASE_PTR bit 2 PCIE: DRP[47] bit 3 PCIE: PCIE_BASE_PTR bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[47] bit 0 PCIE: PCIE_BASE_PTR bit 0 PCIE: DRP[47] bit 1 PCIE: PCIE_BASE_PTR bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[46] bit 14 PCIE: DRP[46] bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[46] bit 12 PCIE: DRP[46] bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[46] bit 10 PCIE: MSIX_CAP_TABLE_SIZE bit 10 PCIE: DRP[46] bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[46] bit 8 PCIE: MSIX_CAP_TABLE_SIZE bit 8 PCIE: DRP[46] bit 9 PCIE: MSIX_CAP_TABLE_SIZE bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[46] bit 6 PCIE: MSIX_CAP_TABLE_SIZE bit 6 PCIE: DRP[46] bit 7 PCIE: MSIX_CAP_TABLE_SIZE bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[46] bit 4 PCIE: MSIX_CAP_TABLE_SIZE bit 4 PCIE: DRP[46] bit 5 PCIE: MSIX_CAP_TABLE_SIZE bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[46] bit 2 PCIE: MSIX_CAP_TABLE_SIZE bit 2 PCIE: DRP[46] bit 3 PCIE: MSIX_CAP_TABLE_SIZE bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[46] bit 0 PCIE: MSIX_CAP_TABLE_SIZE bit 0 PCIE: DRP[46] bit 1 PCIE: MSIX_CAP_TABLE_SIZE bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[45] bit 14 PCIE: DRP[45] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[45] bit 12 PCIE: MSIX_CAP_TABLE_OFFSET bit 28 PCIE: DRP[45] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[45] bit 10 PCIE: MSIX_CAP_TABLE_OFFSET bit 26 PCIE: DRP[45] bit 11 PCIE: MSIX_CAP_TABLE_OFFSET bit 27
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[45] bit 8 PCIE: MSIX_CAP_TABLE_OFFSET bit 24 PCIE: DRP[45] bit 9 PCIE: MSIX_CAP_TABLE_OFFSET bit 25
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[45] bit 6 PCIE: MSIX_CAP_TABLE_OFFSET bit 22 PCIE: DRP[45] bit 7 PCIE: MSIX_CAP_TABLE_OFFSET bit 23
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[45] bit 4 PCIE: MSIX_CAP_TABLE_OFFSET bit 20 PCIE: DRP[45] bit 5 PCIE: MSIX_CAP_TABLE_OFFSET bit 21
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[45] bit 2 PCIE: MSIX_CAP_TABLE_OFFSET bit 18 PCIE: DRP[45] bit 3 PCIE: MSIX_CAP_TABLE_OFFSET bit 19
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[45] bit 0 PCIE: MSIX_CAP_TABLE_OFFSET bit 16 PCIE: DRP[45] bit 1 PCIE: MSIX_CAP_TABLE_OFFSET bit 17
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[44] bit 14 PCIE: MSIX_CAP_TABLE_OFFSET bit 14 PCIE: DRP[44] bit 15 PCIE: MSIX_CAP_TABLE_OFFSET bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[44] bit 12 PCIE: MSIX_CAP_TABLE_OFFSET bit 12 PCIE: DRP[44] bit 13 PCIE: MSIX_CAP_TABLE_OFFSET bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[44] bit 10 PCIE: MSIX_CAP_TABLE_OFFSET bit 10 PCIE: DRP[44] bit 11 PCIE: MSIX_CAP_TABLE_OFFSET bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[44] bit 8 PCIE: MSIX_CAP_TABLE_OFFSET bit 8 PCIE: DRP[44] bit 9 PCIE: MSIX_CAP_TABLE_OFFSET bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[44] bit 6 PCIE: MSIX_CAP_TABLE_OFFSET bit 6 PCIE: DRP[44] bit 7 PCIE: MSIX_CAP_TABLE_OFFSET bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[44] bit 4 PCIE: MSIX_CAP_TABLE_OFFSET bit 4 PCIE: DRP[44] bit 5 PCIE: MSIX_CAP_TABLE_OFFSET bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[44] bit 2 PCIE: MSIX_CAP_TABLE_OFFSET bit 2 PCIE: DRP[44] bit 3 PCIE: MSIX_CAP_TABLE_OFFSET bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[44] bit 0 PCIE: MSIX_CAP_TABLE_OFFSET bit 0 PCIE: DRP[44] bit 1 PCIE: MSIX_CAP_TABLE_OFFSET bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[43] bit 14 PCIE: MSIX_CAP_TABLE_BIR bit 1 PCIE: DRP[43] bit 15 PCIE: MSIX_CAP_TABLE_BIR bit 2
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[43] bit 12 PCIE: MSIX_CAP_PBA_OFFSET bit 28 PCIE: DRP[43] bit 13 PCIE: MSIX_CAP_TABLE_BIR bit 0
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[43] bit 10 PCIE: MSIX_CAP_PBA_OFFSET bit 26 PCIE: DRP[43] bit 11 PCIE: MSIX_CAP_PBA_OFFSET bit 27
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[43] bit 8 PCIE: MSIX_CAP_PBA_OFFSET bit 24 PCIE: DRP[43] bit 9 PCIE: MSIX_CAP_PBA_OFFSET bit 25
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[43] bit 6 PCIE: MSIX_CAP_PBA_OFFSET bit 22 PCIE: DRP[43] bit 7 PCIE: MSIX_CAP_PBA_OFFSET bit 23
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[43] bit 4 PCIE: MSIX_CAP_PBA_OFFSET bit 20 PCIE: DRP[43] bit 5 PCIE: MSIX_CAP_PBA_OFFSET bit 21
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[43] bit 2 PCIE: MSIX_CAP_PBA_OFFSET bit 18 PCIE: DRP[43] bit 3 PCIE: MSIX_CAP_PBA_OFFSET bit 19
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[43] bit 0 PCIE: MSIX_CAP_PBA_OFFSET bit 16 PCIE: DRP[43] bit 1 PCIE: MSIX_CAP_PBA_OFFSET bit 17
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[42] bit 14 PCIE: MSIX_CAP_PBA_OFFSET bit 14 PCIE: DRP[42] bit 15 PCIE: MSIX_CAP_PBA_OFFSET bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[42] bit 12 PCIE: MSIX_CAP_PBA_OFFSET bit 12 PCIE: DRP[42] bit 13 PCIE: MSIX_CAP_PBA_OFFSET bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[42] bit 10 PCIE: MSIX_CAP_PBA_OFFSET bit 10 PCIE: DRP[42] bit 11 PCIE: MSIX_CAP_PBA_OFFSET bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[42] bit 8 PCIE: MSIX_CAP_PBA_OFFSET bit 8 PCIE: DRP[42] bit 9 PCIE: MSIX_CAP_PBA_OFFSET bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[42] bit 6 PCIE: MSIX_CAP_PBA_OFFSET bit 6 PCIE: DRP[42] bit 7 PCIE: MSIX_CAP_PBA_OFFSET bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[42] bit 4 PCIE: MSIX_CAP_PBA_OFFSET bit 4 PCIE: DRP[42] bit 5 PCIE: MSIX_CAP_PBA_OFFSET bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[42] bit 2 PCIE: MSIX_CAP_PBA_OFFSET bit 2 PCIE: DRP[42] bit 3 PCIE: MSIX_CAP_PBA_OFFSET bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[42] bit 0 PCIE: MSIX_CAP_PBA_OFFSET bit 0 PCIE: DRP[42] bit 1 PCIE: MSIX_CAP_PBA_OFFSET bit 1
virtex6 PCIE rect MAIN[8]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[53] bit 14 PCIE: DRP[53] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[53] bit 12 PCIE: PM_DATA_SCALE7 bit 0 PCIE: DRP[53] bit 13 PCIE: PM_DATA_SCALE7 bit 1
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[53] bit 10 PCIE: PM_DATA_SCALE6 bit 0 PCIE: DRP[53] bit 11 PCIE: PM_DATA_SCALE6 bit 1
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[53] bit 8 PCIE: PM_DATA_SCALE5 bit 0 PCIE: DRP[53] bit 9 PCIE: PM_DATA_SCALE5 bit 1
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[53] bit 6 PCIE: PM_DATA_SCALE4 bit 0 PCIE: DRP[53] bit 7 PCIE: PM_DATA_SCALE4 bit 1
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[53] bit 4 PCIE: PM_DATA_SCALE3 bit 0 PCIE: DRP[53] bit 5 PCIE: PM_DATA_SCALE3 bit 1
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[53] bit 2 PCIE: PM_DATA_SCALE2 bit 0 PCIE: DRP[53] bit 3 PCIE: PM_DATA_SCALE2 bit 1
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[53] bit 0 PCIE: PM_DATA_SCALE1 bit 0 PCIE: DRP[53] bit 1 PCIE: PM_DATA_SCALE1 bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[52] bit 14 PCIE: PM_DATA_SCALE0 bit 0 PCIE: DRP[52] bit 15 PCIE: PM_DATA_SCALE0 bit 1
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[52] bit 12 PCIE: PM_CSR_BPCCEN PCIE: DRP[52] bit 13 PCIE: PM_CSR_NOSOFTRST
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[52] bit 10 PCIE: PM_CAP_VERSION bit 2 PCIE: DRP[52] bit 11 PCIE: PM_CSR_B2B3
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[52] bit 8 PCIE: PM_CAP_VERSION bit 0 PCIE: DRP[52] bit 9 PCIE: PM_CAP_VERSION bit 1
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[52] bit 6 PCIE: PM_CAP_PMESUPPORT bit 4 PCIE: DRP[52] bit 7 PCIE: PM_CAP_RSVD_04 bit 0
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[52] bit 4 PCIE: PM_CAP_PMESUPPORT bit 2 PCIE: DRP[52] bit 5 PCIE: PM_CAP_PMESUPPORT bit 3
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[52] bit 2 PCIE: PM_CAP_PMESUPPORT bit 0 PCIE: DRP[52] bit 3 PCIE: PM_CAP_PMESUPPORT bit 1
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[52] bit 0 PCIE: PM_CAP_ON PCIE: DRP[52] bit 1 PCIE: PM_CAP_PME_CLOCK
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[51] bit 14 PCIE: PM_CAP_NEXTPTR bit 6 PCIE: DRP[51] bit 15 PCIE: PM_CAP_NEXTPTR bit 7
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[51] bit 12 PCIE: PM_CAP_NEXTPTR bit 4 PCIE: DRP[51] bit 13 PCIE: PM_CAP_NEXTPTR bit 5
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[51] bit 10 PCIE: PM_CAP_NEXTPTR bit 2 PCIE: DRP[51] bit 11 PCIE: PM_CAP_NEXTPTR bit 3
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[51] bit 8 PCIE: PM_CAP_NEXTPTR bit 0 PCIE: DRP[51] bit 9 PCIE: PM_CAP_NEXTPTR bit 1
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[51] bit 6 PCIE: PM_CAP_ID bit 6 PCIE: DRP[51] bit 7 PCIE: PM_CAP_ID bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[51] bit 4 PCIE: PM_CAP_ID bit 4 PCIE: DRP[51] bit 5 PCIE: PM_CAP_ID bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[51] bit 2 PCIE: PM_CAP_ID bit 2 PCIE: DRP[51] bit 3 PCIE: PM_CAP_ID bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[51] bit 0 PCIE: PM_CAP_ID bit 0 PCIE: DRP[51] bit 1 PCIE: PM_CAP_ID bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[50] bit 14 PCIE: DRP[50] bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[50] bit 12 PCIE: PM_CAP_D2SUPPORT PCIE: DRP[50] bit 13 PCIE: PM_CAP_DSI
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[50] bit 10 PCIE: PM_CAP_AUXCURRENT bit 2 PCIE: DRP[50] bit 11 PCIE: PM_CAP_D1SUPPORT
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[50] bit 8 PCIE: PM_CAP_AUXCURRENT bit 0 PCIE: DRP[50] bit 9 PCIE: PM_CAP_AUXCURRENT bit 1
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[50] bit 6 PCIE: PM_BASE_PTR bit 6 PCIE: DRP[50] bit 7 PCIE: PM_BASE_PTR bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[50] bit 4 PCIE: PM_BASE_PTR bit 4 PCIE: DRP[50] bit 5 PCIE: PM_BASE_PTR bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[50] bit 2 PCIE: PM_BASE_PTR bit 2 PCIE: DRP[50] bit 3 PCIE: PM_BASE_PTR bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[50] bit 0 PCIE: PM_BASE_PTR bit 0 PCIE: DRP[50] bit 1 PCIE: PM_BASE_PTR bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[49] bit 14 PCIE: PCIE_REVISION bit 2 PCIE: DRP[49] bit 15 PCIE: PCIE_REVISION bit 3
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[49] bit 12 PCIE: PCIE_REVISION bit 0 PCIE: DRP[49] bit 13 PCIE: PCIE_REVISION bit 1
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[49] bit 10 PCIE: PCIE_CAP_RSVD_15_14 bit 1 PCIE: DRP[49] bit 11 PCIE: PCIE_CAP_SLOT_IMPLEMENTED
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[49] bit 8 PCIE: PCIE_CAP_ON PCIE: DRP[49] bit 9 PCIE: PCIE_CAP_RSVD_15_14 bit 0
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[49] bit 6 PCIE: PCIE_CAP_NEXTPTR bit 6 PCIE: DRP[49] bit 7 PCIE: PCIE_CAP_NEXTPTR bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[49] bit 4 PCIE: PCIE_CAP_NEXTPTR bit 4 PCIE: DRP[49] bit 5 PCIE: PCIE_CAP_NEXTPTR bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[49] bit 2 PCIE: PCIE_CAP_NEXTPTR bit 2 PCIE: DRP[49] bit 3 PCIE: PCIE_CAP_NEXTPTR bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[49] bit 0 PCIE: PCIE_CAP_NEXTPTR bit 0 PCIE: DRP[49] bit 1 PCIE: PCIE_CAP_NEXTPTR bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[48] bit 14 PCIE: DRP[48] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[48] bit 12 PCIE: PCIE_CAP_INT_MSG_NUM bit 4 PCIE: DRP[48] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[48] bit 10 PCIE: PCIE_CAP_INT_MSG_NUM bit 2 PCIE: DRP[48] bit 11 PCIE: PCIE_CAP_INT_MSG_NUM bit 3
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[48] bit 8 PCIE: PCIE_CAP_INT_MSG_NUM bit 0 PCIE: DRP[48] bit 9 PCIE: PCIE_CAP_INT_MSG_NUM bit 1
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[48] bit 6 PCIE: PCIE_CAP_DEVICE_PORT_TYPE bit 2 PCIE: DRP[48] bit 7 PCIE: PCIE_CAP_DEVICE_PORT_TYPE bit 3
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[48] bit 4 PCIE: PCIE_CAP_DEVICE_PORT_TYPE bit 0 PCIE: DRP[48] bit 5 PCIE: PCIE_CAP_DEVICE_PORT_TYPE bit 1
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[48] bit 2 PCIE: PCIE_CAP_CAPABILITY_VERSION bit 2 PCIE: DRP[48] bit 3 PCIE: PCIE_CAP_CAPABILITY_VERSION bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[48] bit 0 PCIE: PCIE_CAP_CAPABILITY_VERSION bit 0 PCIE: DRP[48] bit 1 PCIE: PCIE_CAP_CAPABILITY_VERSION bit 1
virtex6 PCIE rect MAIN[9]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[59] bit 14 PCIE: SLOT_CAP_POWER_CONTROLLER_PRESENT PCIE: DRP[59] bit 15 PCIE: SLOT_CAP_POWER_INDICATOR_PRESENT
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[59] bit 12 PCIE: SLOT_CAP_PHYSICAL_SLOT_NUM bit 11 PCIE: DRP[59] bit 13 PCIE: SLOT_CAP_PHYSICAL_SLOT_NUM bit 12
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[59] bit 10 PCIE: SLOT_CAP_PHYSICAL_SLOT_NUM bit 9 PCIE: DRP[59] bit 11 PCIE: SLOT_CAP_PHYSICAL_SLOT_NUM bit 10
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[59] bit 8 PCIE: SLOT_CAP_PHYSICAL_SLOT_NUM bit 7 PCIE: DRP[59] bit 9 PCIE: SLOT_CAP_PHYSICAL_SLOT_NUM bit 8
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[59] bit 6 PCIE: SLOT_CAP_PHYSICAL_SLOT_NUM bit 5 PCIE: DRP[59] bit 7 PCIE: SLOT_CAP_PHYSICAL_SLOT_NUM bit 6
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[59] bit 4 PCIE: SLOT_CAP_PHYSICAL_SLOT_NUM bit 3 PCIE: DRP[59] bit 5 PCIE: SLOT_CAP_PHYSICAL_SLOT_NUM bit 4
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[59] bit 2 PCIE: SLOT_CAP_PHYSICAL_SLOT_NUM bit 1 PCIE: DRP[59] bit 3 PCIE: SLOT_CAP_PHYSICAL_SLOT_NUM bit 2
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[59] bit 0 PCIE: SLOT_CAP_NO_CMD_COMPLETED_SUPPORT PCIE: DRP[59] bit 1 PCIE: SLOT_CAP_PHYSICAL_SLOT_NUM bit 0
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[58] bit 14 PCIE: SLOT_CAP_HOTPLUG_SURPRISE PCIE: DRP[58] bit 15 PCIE: SLOT_CAP_MRL_SENSOR_PRESENT
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[58] bit 12 PCIE: SLOT_CAP_ELEC_INTERLOCK_PRESENT PCIE: DRP[58] bit 13 PCIE: SLOT_CAP_HOTPLUG_CAPABLE
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[58] bit 10 PCIE: SLOT_CAP_ATT_BUTTON_PRESENT PCIE: DRP[58] bit 11 PCIE: SLOT_CAP_ATT_INDICATOR_PRESENT
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[58] bit 8 PCIE: ROOT_CAP_CRS_SW_VISIBILITY PCIE: DRP[58] bit 9 PCIE: SELECT_DLL_IF
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[58] bit 6 PCIE: REVISION_ID bit 6 PCIE: DRP[58] bit 7 PCIE: REVISION_ID bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[58] bit 4 PCIE: REVISION_ID bit 4 PCIE: DRP[58] bit 5 PCIE: REVISION_ID bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[58] bit 2 PCIE: REVISION_ID bit 2 PCIE: DRP[58] bit 3 PCIE: REVISION_ID bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[58] bit 0 PCIE: REVISION_ID bit 0 PCIE: DRP[58] bit 1 PCIE: REVISION_ID bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[57] bit 14 PCIE: PM_DATA7 bit 6 PCIE: DRP[57] bit 15 PCIE: PM_DATA7 bit 7
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[57] bit 12 PCIE: PM_DATA7 bit 4 PCIE: DRP[57] bit 13 PCIE: PM_DATA7 bit 5
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[57] bit 10 PCIE: PM_DATA7 bit 2 PCIE: DRP[57] bit 11 PCIE: PM_DATA7 bit 3
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[57] bit 8 PCIE: PM_DATA7 bit 0 PCIE: DRP[57] bit 9 PCIE: PM_DATA7 bit 1
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[57] bit 6 PCIE: PM_DATA6 bit 6 PCIE: DRP[57] bit 7 PCIE: PM_DATA6 bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[57] bit 4 PCIE: PM_DATA6 bit 4 PCIE: DRP[57] bit 5 PCIE: PM_DATA6 bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[57] bit 2 PCIE: PM_DATA6 bit 2 PCIE: DRP[57] bit 3 PCIE: PM_DATA6 bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[57] bit 0 PCIE: PM_DATA6 bit 0 PCIE: DRP[57] bit 1 PCIE: PM_DATA6 bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[56] bit 14 PCIE: PM_DATA5 bit 6 PCIE: DRP[56] bit 15 PCIE: PM_DATA5 bit 7
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[56] bit 12 PCIE: PM_DATA5 bit 4 PCIE: DRP[56] bit 13 PCIE: PM_DATA5 bit 5
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[56] bit 10 PCIE: PM_DATA5 bit 2 PCIE: DRP[56] bit 11 PCIE: PM_DATA5 bit 3
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[56] bit 8 PCIE: PM_DATA5 bit 0 PCIE: DRP[56] bit 9 PCIE: PM_DATA5 bit 1
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[56] bit 6 PCIE: PM_DATA4 bit 6 PCIE: DRP[56] bit 7 PCIE: PM_DATA4 bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[56] bit 4 PCIE: PM_DATA4 bit 4 PCIE: DRP[56] bit 5 PCIE: PM_DATA4 bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[56] bit 2 PCIE: PM_DATA4 bit 2 PCIE: DRP[56] bit 3 PCIE: PM_DATA4 bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[56] bit 0 PCIE: PM_DATA4 bit 0 PCIE: DRP[56] bit 1 PCIE: PM_DATA4 bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[55] bit 14 PCIE: PM_DATA3 bit 6 PCIE: DRP[55] bit 15 PCIE: PM_DATA3 bit 7
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[55] bit 12 PCIE: PM_DATA3 bit 4 PCIE: DRP[55] bit 13 PCIE: PM_DATA3 bit 5
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[55] bit 10 PCIE: PM_DATA3 bit 2 PCIE: DRP[55] bit 11 PCIE: PM_DATA3 bit 3
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[55] bit 8 PCIE: PM_DATA3 bit 0 PCIE: DRP[55] bit 9 PCIE: PM_DATA3 bit 1
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[55] bit 6 PCIE: PM_DATA2 bit 6 PCIE: DRP[55] bit 7 PCIE: PM_DATA2 bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[55] bit 4 PCIE: PM_DATA2 bit 4 PCIE: DRP[55] bit 5 PCIE: PM_DATA2 bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[55] bit 2 PCIE: PM_DATA2 bit 2 PCIE: DRP[55] bit 3 PCIE: PM_DATA2 bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[55] bit 0 PCIE: PM_DATA2 bit 0 PCIE: DRP[55] bit 1 PCIE: PM_DATA2 bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[54] bit 14 PCIE: PM_DATA1 bit 6 PCIE: DRP[54] bit 15 PCIE: PM_DATA1 bit 7
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[54] bit 12 PCIE: PM_DATA1 bit 4 PCIE: DRP[54] bit 13 PCIE: PM_DATA1 bit 5
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[54] bit 10 PCIE: PM_DATA1 bit 2 PCIE: DRP[54] bit 11 PCIE: PM_DATA1 bit 3
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[54] bit 8 PCIE: PM_DATA1 bit 0 PCIE: DRP[54] bit 9 PCIE: PM_DATA1 bit 1
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[54] bit 6 PCIE: PM_DATA0 bit 6 PCIE: DRP[54] bit 7 PCIE: PM_DATA0 bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[54] bit 4 PCIE: PM_DATA0 bit 4 PCIE: DRP[54] bit 5 PCIE: PM_DATA0 bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[54] bit 2 PCIE: PM_DATA0 bit 2 PCIE: DRP[54] bit 3 PCIE: PM_DATA0 bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[54] bit 0 PCIE: PM_DATA0 bit 0 PCIE: DRP[54] bit 1 PCIE: PM_DATA0 bit 1
virtex6 PCIE rect MAIN[10]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[65] bit 14 PCIE: VC_CAP_ID bit 14 PCIE: DRP[65] bit 15 PCIE: VC_CAP_ID bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[65] bit 12 PCIE: VC_CAP_ID bit 12 PCIE: DRP[65] bit 13 PCIE: VC_CAP_ID bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[65] bit 10 PCIE: VC_CAP_ID bit 10 PCIE: DRP[65] bit 11 PCIE: VC_CAP_ID bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[65] bit 8 PCIE: VC_CAP_ID bit 8 PCIE: DRP[65] bit 9 PCIE: VC_CAP_ID bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[65] bit 6 PCIE: VC_CAP_ID bit 6 PCIE: DRP[65] bit 7 PCIE: VC_CAP_ID bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[65] bit 4 PCIE: VC_CAP_ID bit 4 PCIE: DRP[65] bit 5 PCIE: VC_CAP_ID bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[65] bit 2 PCIE: VC_CAP_ID bit 2 PCIE: DRP[65] bit 3 PCIE: VC_CAP_ID bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[65] bit 0 PCIE: VC_CAP_ID bit 0 PCIE: DRP[65] bit 1 PCIE: VC_CAP_ID bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[64] bit 14 PCIE: DRP[64] bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[64] bit 12 PCIE: VC_CAP_ON PCIE: DRP[64] bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[64] bit 10 PCIE: VC_CAP_NEXTPTR bit 10 PCIE: DRP[64] bit 11 PCIE: VC_CAP_NEXTPTR bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[64] bit 8 PCIE: VC_CAP_NEXTPTR bit 8 PCIE: DRP[64] bit 9 PCIE: VC_CAP_NEXTPTR bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[64] bit 6 PCIE: VC_CAP_NEXTPTR bit 6 PCIE: DRP[64] bit 7 PCIE: VC_CAP_NEXTPTR bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[64] bit 4 PCIE: VC_CAP_NEXTPTR bit 4 PCIE: DRP[64] bit 5 PCIE: VC_CAP_NEXTPTR bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[64] bit 2 PCIE: VC_CAP_NEXTPTR bit 2 PCIE: DRP[64] bit 3 PCIE: VC_CAP_NEXTPTR bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[64] bit 0 PCIE: VC_CAP_NEXTPTR bit 0 PCIE: DRP[64] bit 1 PCIE: VC_CAP_NEXTPTR bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[63] bit 14 PCIE: DRP[63] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[63] bit 12 PCIE: DRP[63] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[63] bit 10 PCIE: VC_BASE_PTR bit 10 PCIE: DRP[63] bit 11 PCIE: VC_BASE_PTR bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[63] bit 8 PCIE: VC_BASE_PTR bit 8 PCIE: DRP[63] bit 9 PCIE: VC_BASE_PTR bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[63] bit 6 PCIE: VC_BASE_PTR bit 6 PCIE: DRP[63] bit 7 PCIE: VC_BASE_PTR bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[63] bit 4 PCIE: VC_BASE_PTR bit 4 PCIE: DRP[63] bit 5 PCIE: VC_BASE_PTR bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[63] bit 2 PCIE: VC_BASE_PTR bit 2 PCIE: DRP[63] bit 3 PCIE: VC_BASE_PTR bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[63] bit 0 PCIE: VC_BASE_PTR bit 0 PCIE: DRP[63] bit 1 PCIE: VC_BASE_PTR bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[62] bit 14 PCIE: SUBSYSTEM_VENDOR_ID bit 14 PCIE: DRP[62] bit 15 PCIE: SUBSYSTEM_VENDOR_ID bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[62] bit 12 PCIE: SUBSYSTEM_VENDOR_ID bit 12 PCIE: DRP[62] bit 13 PCIE: SUBSYSTEM_VENDOR_ID bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[62] bit 10 PCIE: SUBSYSTEM_VENDOR_ID bit 10 PCIE: DRP[62] bit 11 PCIE: SUBSYSTEM_VENDOR_ID bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[62] bit 8 PCIE: SUBSYSTEM_VENDOR_ID bit 8 PCIE: DRP[62] bit 9 PCIE: SUBSYSTEM_VENDOR_ID bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[62] bit 6 PCIE: SUBSYSTEM_VENDOR_ID bit 6 PCIE: DRP[62] bit 7 PCIE: SUBSYSTEM_VENDOR_ID bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[62] bit 4 PCIE: SUBSYSTEM_VENDOR_ID bit 4 PCIE: DRP[62] bit 5 PCIE: SUBSYSTEM_VENDOR_ID bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[62] bit 2 PCIE: SUBSYSTEM_VENDOR_ID bit 2 PCIE: DRP[62] bit 3 PCIE: SUBSYSTEM_VENDOR_ID bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[62] bit 0 PCIE: SUBSYSTEM_VENDOR_ID bit 0 PCIE: DRP[62] bit 1 PCIE: SUBSYSTEM_VENDOR_ID bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[61] bit 14 PCIE: SUBSYSTEM_ID bit 14 PCIE: DRP[61] bit 15 PCIE: SUBSYSTEM_ID bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[61] bit 12 PCIE: SUBSYSTEM_ID bit 12 PCIE: DRP[61] bit 13 PCIE: SUBSYSTEM_ID bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[61] bit 10 PCIE: SUBSYSTEM_ID bit 10 PCIE: DRP[61] bit 11 PCIE: SUBSYSTEM_ID bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[61] bit 8 PCIE: SUBSYSTEM_ID bit 8 PCIE: DRP[61] bit 9 PCIE: SUBSYSTEM_ID bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[61] bit 6 PCIE: SUBSYSTEM_ID bit 6 PCIE: DRP[61] bit 7 PCIE: SUBSYSTEM_ID bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[61] bit 4 PCIE: SUBSYSTEM_ID bit 4 PCIE: DRP[61] bit 5 PCIE: SUBSYSTEM_ID bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[61] bit 2 PCIE: SUBSYSTEM_ID bit 2 PCIE: DRP[61] bit 3 PCIE: SUBSYSTEM_ID bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[61] bit 0 PCIE: SUBSYSTEM_ID bit 0 PCIE: DRP[61] bit 1 PCIE: SUBSYSTEM_ID bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[60] bit 14 PCIE: DRP[60] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[60] bit 12 PCIE: DRP[60] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[60] bit 10 PCIE: DRP[60] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[60] bit 8 PCIE: SLOT_CAP_SLOT_POWER_LIMIT_VALUE bit 6 PCIE: DRP[60] bit 9 PCIE: SLOT_CAP_SLOT_POWER_LIMIT_VALUE bit 7
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[60] bit 6 PCIE: SLOT_CAP_SLOT_POWER_LIMIT_VALUE bit 4 PCIE: DRP[60] bit 7 PCIE: SLOT_CAP_SLOT_POWER_LIMIT_VALUE bit 5
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[60] bit 4 PCIE: SLOT_CAP_SLOT_POWER_LIMIT_VALUE bit 2 PCIE: DRP[60] bit 5 PCIE: SLOT_CAP_SLOT_POWER_LIMIT_VALUE bit 3
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[60] bit 2 PCIE: SLOT_CAP_SLOT_POWER_LIMIT_VALUE bit 0 PCIE: DRP[60] bit 3 PCIE: SLOT_CAP_SLOT_POWER_LIMIT_VALUE bit 1
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[60] bit 0 PCIE: SLOT_CAP_SLOT_POWER_LIMIT_SCALE bit 0 PCIE: DRP[60] bit 1 PCIE: SLOT_CAP_SLOT_POWER_LIMIT_SCALE bit 1
virtex6 PCIE rect MAIN[11]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[71] bit 14 PCIE: VSEC_CAP_ID bit 14 PCIE: DRP[71] bit 15 PCIE: VSEC_CAP_ID bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[71] bit 12 PCIE: VSEC_CAP_ID bit 12 PCIE: DRP[71] bit 13 PCIE: VSEC_CAP_ID bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[71] bit 10 PCIE: VSEC_CAP_ID bit 10 PCIE: DRP[71] bit 11 PCIE: VSEC_CAP_ID bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[71] bit 8 PCIE: VSEC_CAP_ID bit 8 PCIE: DRP[71] bit 9 PCIE: VSEC_CAP_ID bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[71] bit 6 PCIE: VSEC_CAP_ID bit 6 PCIE: DRP[71] bit 7 PCIE: VSEC_CAP_ID bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[71] bit 4 PCIE: VSEC_CAP_ID bit 4 PCIE: DRP[71] bit 5 PCIE: VSEC_CAP_ID bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[71] bit 2 PCIE: VSEC_CAP_ID bit 2 PCIE: DRP[71] bit 3 PCIE: VSEC_CAP_ID bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[71] bit 0 PCIE: VSEC_CAP_ID bit 0 PCIE: DRP[71] bit 1 PCIE: VSEC_CAP_ID bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[70] bit 14 PCIE: VSEC_CAP_HDR_REVISION bit 2 PCIE: DRP[70] bit 15 PCIE: VSEC_CAP_HDR_REVISION bit 3
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[70] bit 12 PCIE: VSEC_CAP_HDR_REVISION bit 0 PCIE: DRP[70] bit 13 PCIE: VSEC_CAP_HDR_REVISION bit 1
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[70] bit 10 PCIE: VSEC_CAP_HDR_LENGTH bit 10 PCIE: DRP[70] bit 11 PCIE: VSEC_CAP_HDR_LENGTH bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[70] bit 8 PCIE: VSEC_CAP_HDR_LENGTH bit 8 PCIE: DRP[70] bit 9 PCIE: VSEC_CAP_HDR_LENGTH bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[70] bit 6 PCIE: VSEC_CAP_HDR_LENGTH bit 6 PCIE: DRP[70] bit 7 PCIE: VSEC_CAP_HDR_LENGTH bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[70] bit 4 PCIE: VSEC_CAP_HDR_LENGTH bit 4 PCIE: DRP[70] bit 5 PCIE: VSEC_CAP_HDR_LENGTH bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[70] bit 2 PCIE: VSEC_CAP_HDR_LENGTH bit 2 PCIE: DRP[70] bit 3 PCIE: VSEC_CAP_HDR_LENGTH bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[70] bit 0 PCIE: VSEC_CAP_HDR_LENGTH bit 0 PCIE: DRP[70] bit 1 PCIE: VSEC_CAP_HDR_LENGTH bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[69] bit 14 PCIE: VSEC_CAP_HDR_ID bit 14 PCIE: DRP[69] bit 15 PCIE: VSEC_CAP_HDR_ID bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[69] bit 12 PCIE: VSEC_CAP_HDR_ID bit 12 PCIE: DRP[69] bit 13 PCIE: VSEC_CAP_HDR_ID bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[69] bit 10 PCIE: VSEC_CAP_HDR_ID bit 10 PCIE: DRP[69] bit 11 PCIE: VSEC_CAP_HDR_ID bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[69] bit 8 PCIE: VSEC_CAP_HDR_ID bit 8 PCIE: DRP[69] bit 9 PCIE: VSEC_CAP_HDR_ID bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[69] bit 6 PCIE: VSEC_CAP_HDR_ID bit 6 PCIE: DRP[69] bit 7 PCIE: VSEC_CAP_HDR_ID bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[69] bit 4 PCIE: VSEC_CAP_HDR_ID bit 4 PCIE: DRP[69] bit 5 PCIE: VSEC_CAP_HDR_ID bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[69] bit 2 PCIE: VSEC_CAP_HDR_ID bit 2 PCIE: DRP[69] bit 3 PCIE: VSEC_CAP_HDR_ID bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[69] bit 0 PCIE: VSEC_CAP_HDR_ID bit 0 PCIE: DRP[69] bit 1 PCIE: VSEC_CAP_HDR_ID bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[68] bit 14 PCIE: DRP[68] bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[68] bit 12 PCIE: DRP[68] bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[68] bit 10 PCIE: VSEC_BASE_PTR bit 10 PCIE: DRP[68] bit 11 PCIE: VSEC_BASE_PTR bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[68] bit 8 PCIE: VSEC_BASE_PTR bit 8 PCIE: DRP[68] bit 9 PCIE: VSEC_BASE_PTR bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[68] bit 6 PCIE: VSEC_BASE_PTR bit 6 PCIE: DRP[68] bit 7 PCIE: VSEC_BASE_PTR bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[68] bit 4 PCIE: VSEC_BASE_PTR bit 4 PCIE: DRP[68] bit 5 PCIE: VSEC_BASE_PTR bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[68] bit 2 PCIE: VSEC_BASE_PTR bit 2 PCIE: DRP[68] bit 3 PCIE: VSEC_BASE_PTR bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[68] bit 0 PCIE: VSEC_BASE_PTR bit 0 PCIE: DRP[68] bit 1 PCIE: VSEC_BASE_PTR bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[67] bit 14 PCIE: VENDOR_ID bit 14 PCIE: DRP[67] bit 15 PCIE: VENDOR_ID bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[67] bit 12 PCIE: VENDOR_ID bit 12 PCIE: DRP[67] bit 13 PCIE: VENDOR_ID bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[67] bit 10 PCIE: VENDOR_ID bit 10 PCIE: DRP[67] bit 11 PCIE: VENDOR_ID bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[67] bit 8 PCIE: VENDOR_ID bit 8 PCIE: DRP[67] bit 9 PCIE: VENDOR_ID bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[67] bit 6 PCIE: VENDOR_ID bit 6 PCIE: DRP[67] bit 7 PCIE: VENDOR_ID bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[67] bit 4 PCIE: VENDOR_ID bit 4 PCIE: DRP[67] bit 5 PCIE: VENDOR_ID bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[67] bit 2 PCIE: VENDOR_ID bit 2 PCIE: DRP[67] bit 3 PCIE: VENDOR_ID bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[67] bit 0 PCIE: VENDOR_ID bit 0 PCIE: DRP[67] bit 1 PCIE: VENDOR_ID bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[66] bit 14 PCIE: DRP[66] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[66] bit 12 PCIE: DRP[66] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[66] bit 10 PCIE: DRP[66] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[66] bit 8 PCIE: DRP[66] bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[66] bit 6 PCIE: DRP[66] bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[66] bit 4 PCIE: DRP[66] bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[66] bit 2 PCIE: DRP[66] bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[66] bit 0 PCIE: VC_CAP_REJECT_SNOOP_TRANSACTIONS PCIE: DRP[66] bit 1
virtex6 PCIE rect MAIN[12]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[77] bit 14 PCIE: LINK_CAP_MAX_LINK_WIDTH bit 4 PCIE: DRP[77] bit 15 PCIE: LINK_CAP_MAX_LINK_WIDTH bit 5
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[77] bit 12 PCIE: LINK_CAP_MAX_LINK_WIDTH bit 2 PCIE: DRP[77] bit 13 PCIE: LINK_CAP_MAX_LINK_WIDTH bit 3
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[77] bit 10 PCIE: LINK_CAP_MAX_LINK_WIDTH bit 0 PCIE: DRP[77] bit 11 PCIE: LINK_CAP_MAX_LINK_WIDTH bit 1
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[77] bit 8 PCIE: INFER_EI bit 3 PCIE: DRP[77] bit 9 PCIE: INFER_EI bit 4
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[77] bit 6 PCIE: INFER_EI bit 1 PCIE: DRP[77] bit 7 PCIE: INFER_EI bit 2
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[77] bit 4 PCIE: ENTER_RVRY_EI_L0 PCIE: DRP[77] bit 5 PCIE: INFER_EI bit 0
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[77] bit 2 PCIE: DISABLE_LANE_REVERSAL PCIE: DRP[77] bit 3 PCIE: DISABLE_SCRAMBLING
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[77] bit 0 PCIE: LL_REPLAY_TIMEOUT_FUNC bit 0 PCIE: DRP[77] bit 1 PCIE: LL_REPLAY_TIMEOUT_FUNC bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[76] bit 14 PCIE: LL_REPLAY_TIMEOUT bit 14 PCIE: DRP[76] bit 15 PCIE: LL_REPLAY_TIMEOUT_EN
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[76] bit 12 PCIE: LL_REPLAY_TIMEOUT bit 12 PCIE: DRP[76] bit 13 PCIE: LL_REPLAY_TIMEOUT bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[76] bit 10 PCIE: LL_REPLAY_TIMEOUT bit 10 PCIE: DRP[76] bit 11 PCIE: LL_REPLAY_TIMEOUT bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[76] bit 8 PCIE: LL_REPLAY_TIMEOUT bit 8 PCIE: DRP[76] bit 9 PCIE: LL_REPLAY_TIMEOUT bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[76] bit 6 PCIE: LL_REPLAY_TIMEOUT bit 6 PCIE: DRP[76] bit 7 PCIE: LL_REPLAY_TIMEOUT bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[76] bit 4 PCIE: LL_REPLAY_TIMEOUT bit 4 PCIE: DRP[76] bit 5 PCIE: LL_REPLAY_TIMEOUT bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[76] bit 2 PCIE: LL_REPLAY_TIMEOUT bit 2 PCIE: DRP[76] bit 3 PCIE: LL_REPLAY_TIMEOUT bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[76] bit 0 PCIE: LL_REPLAY_TIMEOUT bit 0 PCIE: DRP[76] bit 1 PCIE: LL_REPLAY_TIMEOUT bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[75] bit 14 PCIE: DRP[75] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[75] bit 12 PCIE: DRP[75] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[75] bit 10 PCIE: DRP[75] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[75] bit 8 PCIE: DRP[75] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[75] bit 6 PCIE: DRP[75] bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[75] bit 4 PCIE: DRP[75] bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[75] bit 2 PCIE: DRP[75] bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[75] bit 0 PCIE: LL_ACK_TIMEOUT_FUNC bit 0 PCIE: DRP[75] bit 1 PCIE: LL_ACK_TIMEOUT_FUNC bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[74] bit 14 PCIE: LL_ACK_TIMEOUT bit 14 PCIE: DRP[74] bit 15 PCIE: LL_ACK_TIMEOUT_EN
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[74] bit 12 PCIE: LL_ACK_TIMEOUT bit 12 PCIE: DRP[74] bit 13 PCIE: LL_ACK_TIMEOUT bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[74] bit 10 PCIE: LL_ACK_TIMEOUT bit 10 PCIE: DRP[74] bit 11 PCIE: LL_ACK_TIMEOUT bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[74] bit 8 PCIE: LL_ACK_TIMEOUT bit 8 PCIE: DRP[74] bit 9 PCIE: LL_ACK_TIMEOUT bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[74] bit 6 PCIE: LL_ACK_TIMEOUT bit 6 PCIE: DRP[74] bit 7 PCIE: LL_ACK_TIMEOUT bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[74] bit 4 PCIE: LL_ACK_TIMEOUT bit 4 PCIE: DRP[74] bit 5 PCIE: LL_ACK_TIMEOUT bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[74] bit 2 PCIE: LL_ACK_TIMEOUT bit 2 PCIE: DRP[74] bit 3 PCIE: LL_ACK_TIMEOUT bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[74] bit 0 PCIE: LL_ACK_TIMEOUT bit 0 PCIE: DRP[74] bit 1 PCIE: LL_ACK_TIMEOUT bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[73] bit 14 PCIE: DRP[73] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[73] bit 12 PCIE: CRM_MODULE_RSTS bit 5 PCIE: DRP[73] bit 13 PCIE: CRM_MODULE_RSTS bit 6
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[73] bit 10 PCIE: CRM_MODULE_RSTS bit 3 PCIE: DRP[73] bit 11 PCIE: CRM_MODULE_RSTS bit 4
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[73] bit 8 PCIE: CRM_MODULE_RSTS bit 1 PCIE: DRP[73] bit 9 PCIE: CRM_MODULE_RSTS bit 2
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[73] bit 6 PCIE: USER_CLK_FREQ bit 2 PCIE: DRP[73] bit 7 PCIE: CRM_MODULE_RSTS bit 0
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[73] bit 4 PCIE: USER_CLK_FREQ bit 0 PCIE: DRP[73] bit 5 PCIE: USER_CLK_FREQ bit 1
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[73] bit 2 PCIE: VSEC_CAP_VERSION bit 2 PCIE: DRP[73] bit 3 PCIE: VSEC_CAP_VERSION bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[73] bit 0 PCIE: VSEC_CAP_VERSION bit 0 PCIE: DRP[73] bit 1 PCIE: VSEC_CAP_VERSION bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[72] bit 14 PCIE: DRP[72] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[72] bit 12 PCIE: VSEC_CAP_NEXTPTR bit 11 PCIE: DRP[72] bit 13 PCIE: VSEC_CAP_ON
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[72] bit 10 PCIE: VSEC_CAP_NEXTPTR bit 9 PCIE: DRP[72] bit 11 PCIE: VSEC_CAP_NEXTPTR bit 10
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[72] bit 8 PCIE: VSEC_CAP_NEXTPTR bit 7 PCIE: DRP[72] bit 9 PCIE: VSEC_CAP_NEXTPTR bit 8
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[72] bit 6 PCIE: VSEC_CAP_NEXTPTR bit 5 PCIE: DRP[72] bit 7 PCIE: VSEC_CAP_NEXTPTR bit 6
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[72] bit 4 PCIE: VSEC_CAP_NEXTPTR bit 3 PCIE: DRP[72] bit 5 PCIE: VSEC_CAP_NEXTPTR bit 4
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[72] bit 2 PCIE: VSEC_CAP_NEXTPTR bit 1 PCIE: DRP[72] bit 3 PCIE: VSEC_CAP_NEXTPTR bit 2
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[72] bit 0 PCIE: VSEC_CAP_IS_LINK_VISIBLE PCIE: DRP[72] bit 1 PCIE: VSEC_CAP_NEXTPTR bit 0
virtex6 PCIE rect MAIN[13]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[83] bit 14 PCIE: DRP[83] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[83] bit 12 PCIE: DRP[83] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[83] bit 10 PCIE: VC_CAP_VERSION bit 3 PCIE: DRP[83] bit 11 PCIE: VC0_CPL_INFINITE
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[83] bit 8 PCIE: VC_CAP_VERSION bit 1 PCIE: DRP[83] bit 9 PCIE: VC_CAP_VERSION bit 2
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[83] bit 6 PCIE: TL_TX_RAM_WRITE_LATENCY bit 0 PCIE: DRP[83] bit 7 PCIE: VC_CAP_VERSION bit 0
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[83] bit 4 PCIE: TL_TX_RAM_RDATA_LATENCY bit 0 PCIE: DRP[83] bit 5 PCIE: TL_TX_RAM_RDATA_LATENCY bit 1
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[83] bit 2 PCIE: TL_RBYPASS PCIE: DRP[83] bit 3 PCIE: TL_TX_RAM_RADDR_LATENCY bit 0
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[83] bit 0 PCIE: TL_TFC_DISABLE PCIE: DRP[83] bit 1 PCIE: TL_TX_CHECKS_DISABLE
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[82] bit 14 PCIE: TL_RX_RAM_RDATA_LATENCY bit 1 PCIE: DRP[82] bit 15 PCIE: TL_RX_RAM_WRITE_LATENCY bit 0
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[82] bit 12 PCIE: TL_RX_RAM_RADDR_LATENCY bit 0 PCIE: DRP[82] bit 13 PCIE: TL_RX_RAM_RDATA_LATENCY bit 0
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[82] bit 10 PCIE: ENABLE_MSG_ROUTE bit 10 PCIE: DRP[82] bit 11 PCIE: ENABLE_RX_TD_ECRC_TRIM
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[82] bit 8 PCIE: ENABLE_MSG_ROUTE bit 8 PCIE: DRP[82] bit 9 PCIE: ENABLE_MSG_ROUTE bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[82] bit 6 PCIE: ENABLE_MSG_ROUTE bit 6 PCIE: DRP[82] bit 7 PCIE: ENABLE_MSG_ROUTE bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[82] bit 4 PCIE: ENABLE_MSG_ROUTE bit 4 PCIE: DRP[82] bit 5 PCIE: ENABLE_MSG_ROUTE bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[82] bit 2 PCIE: ENABLE_MSG_ROUTE bit 2 PCIE: DRP[82] bit 3 PCIE: ENABLE_MSG_ROUTE bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[82] bit 0 PCIE: ENABLE_MSG_ROUTE bit 0 PCIE: DRP[82] bit 1 PCIE: ENABLE_MSG_ROUTE bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[81] bit 14 PCIE: DRP[81] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[81] bit 12 PCIE: DRP[81] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[81] bit 10 PCIE: DISABLE_ID_CHECK PCIE: DRP[81] bit 11 PCIE: DISABLE_RX_TC_FILTER
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[81] bit 8 PCIE: DISABLE_ASPM_L1_TIMER PCIE: DRP[81] bit 9 PCIE: DISABLE_BAR_FILTERING
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[81] bit 6 PCIE: DNSTREAM_LINK_NUM bit 6 PCIE: DRP[81] bit 7 PCIE: DNSTREAM_LINK_NUM bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[81] bit 4 PCIE: DNSTREAM_LINK_NUM bit 4 PCIE: DRP[81] bit 5 PCIE: DNSTREAM_LINK_NUM bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[81] bit 2 PCIE: DNSTREAM_LINK_NUM bit 2 PCIE: DRP[81] bit 3 PCIE: DNSTREAM_LINK_NUM bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[81] bit 0 PCIE: DNSTREAM_LINK_NUM bit 0 PCIE: DRP[81] bit 1 PCIE: DNSTREAM_LINK_NUM bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[80] bit 14 PCIE: UPSTREAM_FACING PCIE: DRP[80] bit 15 PCIE: EXIT_LOOPBACK_ON_EI
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[80] bit 12 PCIE: PL_FAST_TRAIN PCIE: DRP[80] bit 13 PCIE: UPCONFIG_CAPABLE
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[80] bit 10 PCIE: PL_AUTO_CONFIG bit 1 PCIE: DRP[80] bit 11 PCIE: PL_AUTO_CONFIG bit 2
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[80] bit 8 PCIE: ALLOW_X8_GEN2 PCIE: DRP[80] bit 9 PCIE: PL_AUTO_CONFIG bit 0
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[80] bit 6 PCIE: N_FTS_GEN2 bit 6 PCIE: DRP[80] bit 7 PCIE: N_FTS_GEN2 bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[80] bit 4 PCIE: N_FTS_GEN2 bit 4 PCIE: DRP[80] bit 5 PCIE: N_FTS_GEN2 bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[80] bit 2 PCIE: N_FTS_GEN2 bit 2 PCIE: DRP[80] bit 3 PCIE: N_FTS_GEN2 bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[80] bit 0 PCIE: N_FTS_GEN2 bit 0 PCIE: DRP[80] bit 1 PCIE: N_FTS_GEN2 bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[79] bit 14 PCIE: N_FTS_GEN1 bit 6 PCIE: DRP[79] bit 15 PCIE: N_FTS_GEN1 bit 7
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[79] bit 12 PCIE: N_FTS_GEN1 bit 4 PCIE: DRP[79] bit 13 PCIE: N_FTS_GEN1 bit 5
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[79] bit 10 PCIE: N_FTS_GEN1 bit 2 PCIE: DRP[79] bit 11 PCIE: N_FTS_GEN1 bit 3
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[79] bit 8 PCIE: N_FTS_GEN1 bit 0 PCIE: DRP[79] bit 9 PCIE: N_FTS_GEN1 bit 1
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[79] bit 6 PCIE: N_FTS_COMCLK_GEN2 bit 6 PCIE: DRP[79] bit 7 PCIE: N_FTS_COMCLK_GEN2 bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[79] bit 4 PCIE: N_FTS_COMCLK_GEN2 bit 4 PCIE: DRP[79] bit 5 PCIE: N_FTS_COMCLK_GEN2 bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[79] bit 2 PCIE: N_FTS_COMCLK_GEN2 bit 2 PCIE: DRP[79] bit 3 PCIE: N_FTS_COMCLK_GEN2 bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[79] bit 0 PCIE: N_FTS_COMCLK_GEN2 bit 0 PCIE: DRP[79] bit 1 PCIE: N_FTS_COMCLK_GEN2 bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[78] bit 14 PCIE: DRP[78] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[78] bit 12 PCIE: N_FTS_COMCLK_GEN1 bit 6 PCIE: DRP[78] bit 13 PCIE: N_FTS_COMCLK_GEN1 bit 7
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[78] bit 10 PCIE: N_FTS_COMCLK_GEN1 bit 4 PCIE: DRP[78] bit 11 PCIE: N_FTS_COMCLK_GEN1 bit 5
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[78] bit 8 PCIE: N_FTS_COMCLK_GEN1 bit 2 PCIE: DRP[78] bit 9 PCIE: N_FTS_COMCLK_GEN1 bit 3
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[78] bit 6 PCIE: N_FTS_COMCLK_GEN1 bit 0 PCIE: DRP[78] bit 7 PCIE: N_FTS_COMCLK_GEN1 bit 1
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[78] bit 4 PCIE: LTSSM_MAX_LINK_WIDTH bit 4 PCIE: DRP[78] bit 5 PCIE: LTSSM_MAX_LINK_WIDTH bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[78] bit 2 PCIE: LTSSM_MAX_LINK_WIDTH bit 2 PCIE: DRP[78] bit 3 PCIE: LTSSM_MAX_LINK_WIDTH bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[78] bit 0 PCIE: LTSSM_MAX_LINK_WIDTH bit 0 PCIE: DRP[78] bit 1 PCIE: LTSSM_MAX_LINK_WIDTH bit 1
virtex6 PCIE rect MAIN[14]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[89] bit 14 PCIE: PGL4_LANE bit 2 PCIE: DRP[89] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[89] bit 12 PCIE: PGL4_LANE bit 0 PCIE: DRP[89] bit 13 PCIE: PGL4_LANE bit 1
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[89] bit 10 PCIE: PGL3_LANE bit 1 PCIE: DRP[89] bit 11 PCIE: PGL3_LANE bit 2
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[89] bit 8 PCIE: PGL2_LANE bit 2 PCIE: DRP[89] bit 9 PCIE: PGL3_LANE bit 0
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[89] bit 6 PCIE: PGL2_LANE bit 0 PCIE: DRP[89] bit 7 PCIE: PGL2_LANE bit 1
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[89] bit 4 PCIE: PGL1_LANE bit 1 PCIE: DRP[89] bit 5 PCIE: PGL1_LANE bit 2
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[89] bit 2 PCIE: PGL0_LANE bit 2 PCIE: DRP[89] bit 3 PCIE: PGL1_LANE bit 0
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[89] bit 0 PCIE: PGL0_LANE bit 0 PCIE: DRP[89] bit 1 PCIE: PGL0_LANE bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[88] bit 14 PCIE: RECRC_CHK_TRIM PCIE: DRP[88] bit 15 PCIE: UR_INV_REQ
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[88] bit 12 PCIE: RECRC_CHK bit 0 PCIE: DRP[88] bit 13 PCIE: RECRC_CHK bit 1
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[88] bit 10 PCIE: VC0_TX_LASTPACKET bit 3 PCIE: DRP[88] bit 11 PCIE: VC0_TX_LASTPACKET bit 4
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[88] bit 8 PCIE: VC0_TX_LASTPACKET bit 1 PCIE: DRP[88] bit 9 PCIE: VC0_TX_LASTPACKET bit 2
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[88] bit 6 PCIE: VC0_TOTAL_CREDITS_PH bit 6 PCIE: DRP[88] bit 7 PCIE: VC0_TX_LASTPACKET bit 0
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[88] bit 4 PCIE: VC0_TOTAL_CREDITS_PH bit 4 PCIE: DRP[88] bit 5 PCIE: VC0_TOTAL_CREDITS_PH bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[88] bit 2 PCIE: VC0_TOTAL_CREDITS_PH bit 2 PCIE: DRP[88] bit 3 PCIE: VC0_TOTAL_CREDITS_PH bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[88] bit 0 PCIE: VC0_TOTAL_CREDITS_PH bit 0 PCIE: DRP[88] bit 1 PCIE: VC0_TOTAL_CREDITS_PH bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[87] bit 14 PCIE: DRP[87] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[87] bit 12 PCIE: DRP[87] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[87] bit 10 PCIE: VC0_TOTAL_CREDITS_PD bit 10 PCIE: DRP[87] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[87] bit 8 PCIE: VC0_TOTAL_CREDITS_PD bit 8 PCIE: DRP[87] bit 9 PCIE: VC0_TOTAL_CREDITS_PD bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[87] bit 6 PCIE: VC0_TOTAL_CREDITS_PD bit 6 PCIE: DRP[87] bit 7 PCIE: VC0_TOTAL_CREDITS_PD bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[87] bit 4 PCIE: VC0_TOTAL_CREDITS_PD bit 4 PCIE: DRP[87] bit 5 PCIE: VC0_TOTAL_CREDITS_PD bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[87] bit 2 PCIE: VC0_TOTAL_CREDITS_PD bit 2 PCIE: DRP[87] bit 3 PCIE: VC0_TOTAL_CREDITS_PD bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[87] bit 0 PCIE: VC0_TOTAL_CREDITS_PD bit 0 PCIE: DRP[87] bit 1 PCIE: VC0_TOTAL_CREDITS_PD bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[86] bit 14 PCIE: DRP[86] bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[86] bit 12 PCIE: VC0_TOTAL_CREDITS_NPH bit 5 PCIE: DRP[86] bit 13 PCIE: VC0_TOTAL_CREDITS_NPH bit 6
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[86] bit 10 PCIE: VC0_TOTAL_CREDITS_NPH bit 3 PCIE: DRP[86] bit 11 PCIE: VC0_TOTAL_CREDITS_NPH bit 4
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[86] bit 8 PCIE: VC0_TOTAL_CREDITS_NPH bit 1 PCIE: DRP[86] bit 9 PCIE: VC0_TOTAL_CREDITS_NPH bit 2
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[86] bit 6 PCIE: VC0_TOTAL_CREDITS_CH bit 6 PCIE: DRP[86] bit 7 PCIE: VC0_TOTAL_CREDITS_NPH bit 0
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[86] bit 4 PCIE: VC0_TOTAL_CREDITS_CH bit 4 PCIE: DRP[86] bit 5 PCIE: VC0_TOTAL_CREDITS_CH bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[86] bit 2 PCIE: VC0_TOTAL_CREDITS_CH bit 2 PCIE: DRP[86] bit 3 PCIE: VC0_TOTAL_CREDITS_CH bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[86] bit 0 PCIE: VC0_TOTAL_CREDITS_CH bit 0 PCIE: DRP[86] bit 1 PCIE: VC0_TOTAL_CREDITS_CH bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[85] bit 14 PCIE: DRP[85] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[85] bit 12 PCIE: DRP[85] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[85] bit 10 PCIE: VC0_TOTAL_CREDITS_CD bit 10 PCIE: DRP[85] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[85] bit 8 PCIE: VC0_TOTAL_CREDITS_CD bit 8 PCIE: DRP[85] bit 9 PCIE: VC0_TOTAL_CREDITS_CD bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[85] bit 6 PCIE: VC0_TOTAL_CREDITS_CD bit 6 PCIE: DRP[85] bit 7 PCIE: VC0_TOTAL_CREDITS_CD bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[85] bit 4 PCIE: VC0_TOTAL_CREDITS_CD bit 4 PCIE: DRP[85] bit 5 PCIE: VC0_TOTAL_CREDITS_CD bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[85] bit 2 PCIE: VC0_TOTAL_CREDITS_CD bit 2 PCIE: DRP[85] bit 3 PCIE: VC0_TOTAL_CREDITS_CD bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[85] bit 0 PCIE: VC0_TOTAL_CREDITS_CD bit 0 PCIE: DRP[85] bit 1 PCIE: VC0_TOTAL_CREDITS_CD bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[84] bit 14 PCIE: DRP[84] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[84] bit 12 PCIE: VC0_RX_RAM_LIMIT bit 12 PCIE: DRP[84] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[84] bit 10 PCIE: VC0_RX_RAM_LIMIT bit 10 PCIE: DRP[84] bit 11 PCIE: VC0_RX_RAM_LIMIT bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[84] bit 8 PCIE: VC0_RX_RAM_LIMIT bit 8 PCIE: DRP[84] bit 9 PCIE: VC0_RX_RAM_LIMIT bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[84] bit 6 PCIE: VC0_RX_RAM_LIMIT bit 6 PCIE: DRP[84] bit 7 PCIE: VC0_RX_RAM_LIMIT bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[84] bit 4 PCIE: VC0_RX_RAM_LIMIT bit 4 PCIE: DRP[84] bit 5 PCIE: VC0_RX_RAM_LIMIT bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[84] bit 2 PCIE: VC0_RX_RAM_LIMIT bit 2 PCIE: DRP[84] bit 3 PCIE: VC0_RX_RAM_LIMIT bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[84] bit 0 PCIE: VC0_RX_RAM_LIMIT bit 0 PCIE: DRP[84] bit 1 PCIE: VC0_RX_RAM_LIMIT bit 1
virtex6 PCIE rect MAIN[15]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[95] bit 14 PCIE: SPARE_WORD0 bit 30 PCIE: DRP[95] bit 15 PCIE: SPARE_WORD0 bit 31
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[95] bit 12 PCIE: SPARE_WORD0 bit 28 PCIE: DRP[95] bit 13 PCIE: SPARE_WORD0 bit 29
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[95] bit 10 PCIE: SPARE_WORD0 bit 26 PCIE: DRP[95] bit 11 PCIE: SPARE_WORD0 bit 27
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[95] bit 8 PCIE: SPARE_WORD0 bit 24 PCIE: DRP[95] bit 9 PCIE: SPARE_WORD0 bit 25
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[95] bit 6 PCIE: SPARE_WORD0 bit 22 PCIE: DRP[95] bit 7 PCIE: SPARE_WORD0 bit 23
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[95] bit 4 PCIE: SPARE_WORD0 bit 20 PCIE: DRP[95] bit 5 PCIE: SPARE_WORD0 bit 21
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[95] bit 2 PCIE: SPARE_WORD0 bit 18 PCIE: DRP[95] bit 3 PCIE: SPARE_WORD0 bit 19
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[95] bit 0 PCIE: SPARE_WORD0 bit 16 PCIE: DRP[95] bit 1 PCIE: SPARE_WORD0 bit 17
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[94] bit 14 PCIE: SPARE_WORD0 bit 14 PCIE: DRP[94] bit 15 PCIE: SPARE_WORD0 bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[94] bit 12 PCIE: SPARE_WORD0 bit 12 PCIE: DRP[94] bit 13 PCIE: SPARE_WORD0 bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[94] bit 10 PCIE: SPARE_WORD0 bit 10 PCIE: DRP[94] bit 11 PCIE: SPARE_WORD0 bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[94] bit 8 PCIE: SPARE_WORD0 bit 8 PCIE: DRP[94] bit 9 PCIE: SPARE_WORD0 bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[94] bit 6 PCIE: SPARE_WORD0 bit 6 PCIE: DRP[94] bit 7 PCIE: SPARE_WORD0 bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[94] bit 4 PCIE: SPARE_WORD0 bit 4 PCIE: DRP[94] bit 5 PCIE: SPARE_WORD0 bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[94] bit 2 PCIE: SPARE_WORD0 bit 2 PCIE: DRP[94] bit 3 PCIE: SPARE_WORD0 bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[94] bit 0 PCIE: SPARE_WORD0 bit 0 PCIE: DRP[94] bit 1 PCIE: SPARE_WORD0 bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[93] bit 14 PCIE: DRP[93] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[93] bit 12 PCIE: DRP[93] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[93] bit 10 PCIE: DRP[93] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[93] bit 8 PCIE: DRP[93] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[93] bit 6 PCIE: SPARE_BYTE3 bit 6 PCIE: DRP[93] bit 7 PCIE: SPARE_BYTE3 bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[93] bit 4 PCIE: SPARE_BYTE3 bit 4 PCIE: DRP[93] bit 5 PCIE: SPARE_BYTE3 bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[93] bit 2 PCIE: SPARE_BYTE3 bit 2 PCIE: DRP[93] bit 3 PCIE: SPARE_BYTE3 bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[93] bit 0 PCIE: SPARE_BYTE3 bit 0 PCIE: DRP[93] bit 1 PCIE: SPARE_BYTE3 bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[92] bit 14 PCIE: SPARE_BYTE2 bit 6 PCIE: DRP[92] bit 15 PCIE: SPARE_BYTE2 bit 7
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[92] bit 12 PCIE: SPARE_BYTE2 bit 4 PCIE: DRP[92] bit 13 PCIE: SPARE_BYTE2 bit 5
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[92] bit 10 PCIE: SPARE_BYTE2 bit 2 PCIE: DRP[92] bit 11 PCIE: SPARE_BYTE2 bit 3
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[92] bit 8 PCIE: SPARE_BYTE2 bit 0 PCIE: DRP[92] bit 9 PCIE: SPARE_BYTE2 bit 1
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[92] bit 6 PCIE: SPARE_BYTE1 bit 6 PCIE: DRP[92] bit 7 PCIE: SPARE_BYTE1 bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[92] bit 4 PCIE: SPARE_BYTE1 bit 4 PCIE: DRP[92] bit 5 PCIE: SPARE_BYTE1 bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[92] bit 2 PCIE: SPARE_BYTE1 bit 2 PCIE: DRP[92] bit 3 PCIE: SPARE_BYTE1 bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[92] bit 0 PCIE: SPARE_BYTE1 bit 0 PCIE: DRP[92] bit 1 PCIE: SPARE_BYTE1 bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[91] bit 14 PCIE: DRP[91] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[91] bit 12 PCIE: DRP[91] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[91] bit 10 PCIE: SPARE_BYTE0 bit 7 PCIE: DRP[91] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[91] bit 8 PCIE: SPARE_BYTE0 bit 5 PCIE: DRP[91] bit 9 PCIE: SPARE_BYTE0 bit 6
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[91] bit 6 PCIE: SPARE_BYTE0 bit 3 PCIE: DRP[91] bit 7 PCIE: SPARE_BYTE0 bit 4
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[91] bit 4 PCIE: SPARE_BYTE0 bit 1 PCIE: DRP[91] bit 5 PCIE: SPARE_BYTE0 bit 2
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[91] bit 2 PCIE: SPARE_BIT8 bit 0 PCIE: DRP[91] bit 3 PCIE: SPARE_BYTE0 bit 0
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[91] bit 0 PCIE: SPARE_BIT6 bit 0 PCIE: DRP[91] bit 1 PCIE: SPARE_BIT7 bit 0
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[90] bit 14 PCIE: SPARE_BIT4 bit 0 PCIE: DRP[90] bit 15 PCIE: SPARE_BIT5 bit 0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[90] bit 12 PCIE: SPARE_BIT2 bit 0 PCIE: DRP[90] bit 13 PCIE: SPARE_BIT3 bit 0
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[90] bit 10 PCIE: SPARE_BIT0 bit 0 PCIE: DRP[90] bit 11 PCIE: SPARE_BIT1 bit 0
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[90] bit 8 PCIE: PGL7_LANE bit 2 PCIE: DRP[90] bit 9 PCIE: TEST_MODE_PIN_CHAR
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[90] bit 6 PCIE: PGL7_LANE bit 0 PCIE: DRP[90] bit 7 PCIE: PGL7_LANE bit 1
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[90] bit 4 PCIE: PGL6_LANE bit 1 PCIE: DRP[90] bit 5 PCIE: PGL6_LANE bit 2
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[90] bit 2 PCIE: PGL5_LANE bit 2 PCIE: DRP[90] bit 3 PCIE: PGL6_LANE bit 0
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[90] bit 0 PCIE: PGL5_LANE bit 0 PCIE: DRP[90] bit 1 PCIE: PGL5_LANE bit 1
virtex6 PCIE rect MAIN[16]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[101] bit 14 PCIE: SPARE_WORD3 bit 30 PCIE: DRP[101] bit 15 PCIE: SPARE_WORD3 bit 31
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[101] bit 12 PCIE: SPARE_WORD3 bit 28 PCIE: DRP[101] bit 13 PCIE: SPARE_WORD3 bit 29
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[101] bit 10 PCIE: SPARE_WORD3 bit 26 PCIE: DRP[101] bit 11 PCIE: SPARE_WORD3 bit 27
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[101] bit 8 PCIE: SPARE_WORD3 bit 24 PCIE: DRP[101] bit 9 PCIE: SPARE_WORD3 bit 25
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[101] bit 6 PCIE: SPARE_WORD3 bit 22 PCIE: DRP[101] bit 7 PCIE: SPARE_WORD3 bit 23
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[101] bit 4 PCIE: SPARE_WORD3 bit 20 PCIE: DRP[101] bit 5 PCIE: SPARE_WORD3 bit 21
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[101] bit 2 PCIE: SPARE_WORD3 bit 18 PCIE: DRP[101] bit 3 PCIE: SPARE_WORD3 bit 19
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[101] bit 0 PCIE: SPARE_WORD3 bit 16 PCIE: DRP[101] bit 1 PCIE: SPARE_WORD3 bit 17
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[100] bit 14 PCIE: SPARE_WORD3 bit 14 PCIE: DRP[100] bit 15 PCIE: SPARE_WORD3 bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[100] bit 12 PCIE: SPARE_WORD3 bit 12 PCIE: DRP[100] bit 13 PCIE: SPARE_WORD3 bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[100] bit 10 PCIE: SPARE_WORD3 bit 10 PCIE: DRP[100] bit 11 PCIE: SPARE_WORD3 bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[100] bit 8 PCIE: SPARE_WORD3 bit 8 PCIE: DRP[100] bit 9 PCIE: SPARE_WORD3 bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[100] bit 6 PCIE: SPARE_WORD3 bit 6 PCIE: DRP[100] bit 7 PCIE: SPARE_WORD3 bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[100] bit 4 PCIE: SPARE_WORD3 bit 4 PCIE: DRP[100] bit 5 PCIE: SPARE_WORD3 bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[100] bit 2 PCIE: SPARE_WORD3 bit 2 PCIE: DRP[100] bit 3 PCIE: SPARE_WORD3 bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[100] bit 0 PCIE: SPARE_WORD3 bit 0 PCIE: DRP[100] bit 1 PCIE: SPARE_WORD3 bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[99] bit 14 PCIE: SPARE_WORD2 bit 30 PCIE: DRP[99] bit 15 PCIE: SPARE_WORD2 bit 31
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[99] bit 12 PCIE: SPARE_WORD2 bit 28 PCIE: DRP[99] bit 13 PCIE: SPARE_WORD2 bit 29
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[99] bit 10 PCIE: SPARE_WORD2 bit 26 PCIE: DRP[99] bit 11 PCIE: SPARE_WORD2 bit 27
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[99] bit 8 PCIE: SPARE_WORD2 bit 24 PCIE: DRP[99] bit 9 PCIE: SPARE_WORD2 bit 25
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[99] bit 6 PCIE: SPARE_WORD2 bit 22 PCIE: DRP[99] bit 7 PCIE: SPARE_WORD2 bit 23
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[99] bit 4 PCIE: SPARE_WORD2 bit 20 PCIE: DRP[99] bit 5 PCIE: SPARE_WORD2 bit 21
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[99] bit 2 PCIE: SPARE_WORD2 bit 18 PCIE: DRP[99] bit 3 PCIE: SPARE_WORD2 bit 19
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[99] bit 0 PCIE: SPARE_WORD2 bit 16 PCIE: DRP[99] bit 1 PCIE: SPARE_WORD2 bit 17
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[98] bit 14 PCIE: SPARE_WORD2 bit 14 PCIE: DRP[98] bit 15 PCIE: SPARE_WORD2 bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[98] bit 12 PCIE: SPARE_WORD2 bit 12 PCIE: DRP[98] bit 13 PCIE: SPARE_WORD2 bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[98] bit 10 PCIE: SPARE_WORD2 bit 10 PCIE: DRP[98] bit 11 PCIE: SPARE_WORD2 bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[98] bit 8 PCIE: SPARE_WORD2 bit 8 PCIE: DRP[98] bit 9 PCIE: SPARE_WORD2 bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[98] bit 6 PCIE: SPARE_WORD2 bit 6 PCIE: DRP[98] bit 7 PCIE: SPARE_WORD2 bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[98] bit 4 PCIE: SPARE_WORD2 bit 4 PCIE: DRP[98] bit 5 PCIE: SPARE_WORD2 bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[98] bit 2 PCIE: SPARE_WORD2 bit 2 PCIE: DRP[98] bit 3 PCIE: SPARE_WORD2 bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[98] bit 0 PCIE: SPARE_WORD2 bit 0 PCIE: DRP[98] bit 1 PCIE: SPARE_WORD2 bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[97] bit 14 PCIE: SPARE_WORD1 bit 30 PCIE: DRP[97] bit 15 PCIE: SPARE_WORD1 bit 31
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[97] bit 12 PCIE: SPARE_WORD1 bit 28 PCIE: DRP[97] bit 13 PCIE: SPARE_WORD1 bit 29
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[97] bit 10 PCIE: SPARE_WORD1 bit 26 PCIE: DRP[97] bit 11 PCIE: SPARE_WORD1 bit 27
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[97] bit 8 PCIE: SPARE_WORD1 bit 24 PCIE: DRP[97] bit 9 PCIE: SPARE_WORD1 bit 25
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[97] bit 6 PCIE: SPARE_WORD1 bit 22 PCIE: DRP[97] bit 7 PCIE: SPARE_WORD1 bit 23
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[97] bit 4 PCIE: SPARE_WORD1 bit 20 PCIE: DRP[97] bit 5 PCIE: SPARE_WORD1 bit 21
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[97] bit 2 PCIE: SPARE_WORD1 bit 18 PCIE: DRP[97] bit 3 PCIE: SPARE_WORD1 bit 19
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[97] bit 0 PCIE: SPARE_WORD1 bit 16 PCIE: DRP[97] bit 1 PCIE: SPARE_WORD1 bit 17
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[96] bit 14 PCIE: SPARE_WORD1 bit 14 PCIE: DRP[96] bit 15 PCIE: SPARE_WORD1 bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[96] bit 12 PCIE: SPARE_WORD1 bit 12 PCIE: DRP[96] bit 13 PCIE: SPARE_WORD1 bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[96] bit 10 PCIE: SPARE_WORD1 bit 10 PCIE: DRP[96] bit 11 PCIE: SPARE_WORD1 bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[96] bit 8 PCIE: SPARE_WORD1 bit 8 PCIE: DRP[96] bit 9 PCIE: SPARE_WORD1 bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[96] bit 6 PCIE: SPARE_WORD1 bit 6 PCIE: DRP[96] bit 7 PCIE: SPARE_WORD1 bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[96] bit 4 PCIE: SPARE_WORD1 bit 4 PCIE: DRP[96] bit 5 PCIE: SPARE_WORD1 bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[96] bit 2 PCIE: SPARE_WORD1 bit 2 PCIE: DRP[96] bit 3 PCIE: SPARE_WORD1 bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[96] bit 0 PCIE: SPARE_WORD1 bit 0 PCIE: DRP[96] bit 1 PCIE: SPARE_WORD1 bit 1
virtex6 PCIE rect MAIN[17]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[107] bit 14 PCIE: DRP[107] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[107] bit 12 PCIE: DRP[107] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[107] bit 10 PCIE: DRP[107] bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[107] bit 8 PCIE: DRP[107] bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[107] bit 6 PCIE: DRP[107] bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[107] bit 4 PCIE: DRP[107] bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[107] bit 2 PCIE: DRP[107] bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[107] bit 0 PCIE: DRP[107] bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[106] bit 14 PCIE: DRP[106] bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[106] bit 12 PCIE: DRP[106] bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[106] bit 10 PCIE: DRP[106] bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[106] bit 8 PCIE: DRP[106] bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[106] bit 6 PCIE: DRP[106] bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[106] bit 4 PCIE: DRP[106] bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[106] bit 2 PCIE: DRP[106] bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[106] bit 0 PCIE: DRP[106] bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[105] bit 14 PCIE: DRP[105] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[105] bit 12 PCIE: DRP[105] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[105] bit 10 PCIE: DRP[105] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[105] bit 8 PCIE: DRP[105] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[105] bit 6 PCIE: DRP[105] bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[105] bit 4 PCIE: DRP[105] bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[105] bit 2 PCIE: DRP[105] bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[105] bit 0 PCIE: DRP[105] bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[104] bit 14 PCIE: DRP[104] bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[104] bit 12 PCIE: DRP[104] bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[104] bit 10 PCIE: DRP[104] bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[104] bit 8 PCIE: DRP[104] bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[104] bit 6 PCIE: DRP[104] bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[104] bit 4 PCIE: DRP[104] bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[104] bit 2 PCIE: DRP[104] bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[104] bit 0 PCIE: DRP[104] bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[103] bit 14 PCIE: DRP[103] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[103] bit 12 PCIE: DRP[103] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[103] bit 10 PCIE: DRP[103] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[103] bit 8 PCIE: DRP[103] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[103] bit 6 PCIE: DRP[103] bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[103] bit 4 PCIE: DRP[103] bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[103] bit 2 PCIE: DRP[103] bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[103] bit 0 PCIE: DRP[103] bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[102] bit 14 PCIE: DRP[102] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[102] bit 12 PCIE: DRP[102] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[102] bit 10 PCIE: DRP[102] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[102] bit 8 PCIE: DRP[102] bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[102] bit 6 PCIE: DRP[102] bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[102] bit 4 PCIE: DRP[102] bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[102] bit 2 PCIE: DRP[102] bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[102] bit 0 PCIE: DRP[102] bit 1
virtex6 PCIE rect MAIN[18]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[113] bit 14 PCIE: DRP[113] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[113] bit 12 PCIE: DRP[113] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[113] bit 10 PCIE: DRP[113] bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[113] bit 8 PCIE: DRP[113] bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[113] bit 6 PCIE: DRP[113] bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[113] bit 4 PCIE: DRP[113] bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[113] bit 2 PCIE: DRP[113] bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[113] bit 0 PCIE: DRP[113] bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[112] bit 14 PCIE: DRP[112] bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[112] bit 12 PCIE: DRP[112] bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[112] bit 10 PCIE: DRP[112] bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[112] bit 8 PCIE: DRP[112] bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[112] bit 6 PCIE: DRP[112] bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[112] bit 4 PCIE: DRP[112] bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[112] bit 2 PCIE: DRP[112] bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[112] bit 0 PCIE: DRP[112] bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[111] bit 14 PCIE: DRP[111] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[111] bit 12 PCIE: DRP[111] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[111] bit 10 PCIE: DRP[111] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[111] bit 8 PCIE: DRP[111] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[111] bit 6 PCIE: DRP[111] bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[111] bit 4 PCIE: DRP[111] bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[111] bit 2 PCIE: DRP[111] bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[111] bit 0 PCIE: DRP[111] bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[110] bit 14 PCIE: DRP[110] bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[110] bit 12 PCIE: DRP[110] bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[110] bit 10 PCIE: DRP[110] bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[110] bit 8 PCIE: DRP[110] bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[110] bit 6 PCIE: DRP[110] bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[110] bit 4 PCIE: DRP[110] bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[110] bit 2 PCIE: DRP[110] bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[110] bit 0 PCIE: DRP[110] bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[109] bit 14 PCIE: DRP[109] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[109] bit 12 PCIE: DRP[109] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[109] bit 10 PCIE: DRP[109] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[109] bit 8 PCIE: DRP[109] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[109] bit 6 PCIE: DRP[109] bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[109] bit 4 PCIE: DRP[109] bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[109] bit 2 PCIE: DRP[109] bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[109] bit 0 PCIE: DRP[109] bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[108] bit 14 PCIE: DRP[108] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[108] bit 12 PCIE: DRP[108] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[108] bit 10 PCIE: DRP[108] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[108] bit 8 PCIE: DRP[108] bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[108] bit 6 PCIE: DRP[108] bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[108] bit 4 PCIE: DRP[108] bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[108] bit 2 PCIE: DRP[108] bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[108] bit 0 PCIE: DRP[108] bit 1
virtex6 PCIE rect MAIN[19]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[119] bit 14 PCIE: DRP[119] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[119] bit 12 PCIE: DRP[119] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[119] bit 10 PCIE: DRP[119] bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[119] bit 8 PCIE: DRP[119] bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[119] bit 6 PCIE: DRP[119] bit 7
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[119] bit 4 PCIE: DRP[119] bit 5
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[119] bit 2 PCIE: DRP[119] bit 3
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[119] bit 0 PCIE: DRP[119] bit 1
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[118] bit 14 PCIE: DRP[118] bit 15
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[118] bit 12 PCIE: DRP[118] bit 13
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[118] bit 10 PCIE: DRP[118] bit 11
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[118] bit 8 PCIE: DRP[118] bit 9
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[118] bit 6 PCIE: DRP[118] bit 7
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[118] bit 4 PCIE: DRP[118] bit 5
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[118] bit 2 PCIE: DRP[118] bit 3
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[118] bit 0 PCIE: DRP[118] bit 1
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[117] bit 14 PCIE: DRP[117] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[117] bit 12 PCIE: DRP[117] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[117] bit 10 PCIE: DRP[117] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[117] bit 8 PCIE: DRP[117] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[117] bit 6 PCIE: DRP[117] bit 7
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[117] bit 4 PCIE: DRP[117] bit 5
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[117] bit 2 PCIE: DRP[117] bit 3
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[117] bit 0 PCIE: DRP[117] bit 1
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[116] bit 14 PCIE: DRP[116] bit 15
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[116] bit 12 PCIE: DRP[116] bit 13
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[116] bit 10 PCIE: DRP[116] bit 11
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[116] bit 8 PCIE: DRP[116] bit 9
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[116] bit 6 PCIE: DRP[116] bit 7
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[116] bit 4 PCIE: DRP[116] bit 5
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[116] bit 2 PCIE: DRP[116] bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[116] bit 0 PCIE: DRP[116] bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[115] bit 14 PCIE: DRP[115] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[115] bit 12 PCIE: DRP[115] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[115] bit 10 PCIE: DRP[115] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[115] bit 8 PCIE: DRP[115] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[115] bit 6 PCIE: DRP[115] bit 7
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[115] bit 4 PCIE: DRP[115] bit 5
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[115] bit 2 PCIE: DRP[115] bit 3
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[115] bit 0 PCIE: DRP[115] bit 1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[114] bit 14 PCIE: DRP[114] bit 15
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[114] bit 12 PCIE: DRP[114] bit 13
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[114] bit 10 PCIE: DRP[114] bit 11
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[114] bit 8 PCIE: DRP[114] bit 9
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[114] bit 6 PCIE: DRP[114] bit 7
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[114] bit 4 PCIE: DRP[114] bit 5
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[114] bit 2 PCIE: DRP[114] bit 3
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE: DRP[114] bit 0 PCIE: DRP[114] bit 1