PCI Express cores
Tile PCIE
Cells: 40
Bel PCIE
| Pin | Direction | Wires |
|---|---|---|
| CFGAERECRCCHECKEN | output | TCELL10:OUT18.TMIN |
| CFGAERECRCGENEN | output | TCELL10:OUT19.TMIN |
| CFGBYTEENN0 | input | TCELL16:IMUX.IMUX15.DELAY |
| CFGBYTEENN1 | input | TCELL16:IMUX.IMUX16.DELAY |
| CFGBYTEENN2 | input | TCELL15:IMUX.IMUX15.DELAY |
| CFGBYTEENN3 | input | TCELL15:IMUX.IMUX16.DELAY |
| CFGCOMMANDBUSMASTERENABLE | output | TCELL0:OUT15.TMIN |
| CFGCOMMANDINTERRUPTDISABLE | output | TCELL21:OUT16.TMIN |
| CFGCOMMANDIOENABLE | output | TCELL0:OUT13.TMIN |
| CFGCOMMANDMEMENABLE | output | TCELL0:OUT14.TMIN |
| CFGCOMMANDSERREN | output | TCELL0:OUT17.TMIN |
| CFGDEVCONTROL2CPLTIMEOUTDIS | output | TCELL10:OUT16.TMIN |
| CFGDEVCONTROL2CPLTIMEOUTVAL0 | output | TCELL11:OUT16.TMIN |
| CFGDEVCONTROL2CPLTIMEOUTVAL1 | output | TCELL11:OUT17.TMIN |
| CFGDEVCONTROL2CPLTIMEOUTVAL2 | output | TCELL11:OUT19.TMIN |
| CFGDEVCONTROL2CPLTIMEOUTVAL3 | output | TCELL11:OUT20.TMIN |
| CFGDEVCONTROLAUXPOWEREN | output | TCELL31:OUT17.TMIN |
| CFGDEVCONTROLCORRERRREPORTINGEN | output | TCELL23:OUT16.TMIN |
| CFGDEVCONTROLENABLERO | output | TCELL29:OUT17.TMIN |
| CFGDEVCONTROLEXTTAGEN | output | TCELL30:OUT18.TMIN |
| CFGDEVCONTROLFATALERRREPORTINGEN | output | TCELL23:OUT18.TMIN |
| CFGDEVCONTROLMAXPAYLOAD0 | output | TCELL29:OUT18.TMIN |
| CFGDEVCONTROLMAXPAYLOAD1 | output | TCELL30:OUT16.TMIN |
| CFGDEVCONTROLMAXPAYLOAD2 | output | TCELL30:OUT17.TMIN |
| CFGDEVCONTROLMAXREADREQ0 | output | TCELL32:OUT17.TMIN |
| CFGDEVCONTROLMAXREADREQ1 | output | TCELL32:OUT18.TMIN |
| CFGDEVCONTROLMAXREADREQ2 | output | TCELL33:OUT16.TMIN |
| CFGDEVCONTROLNONFATALREPORTINGEN | output | TCELL23:OUT17.TMIN |
| CFGDEVCONTROLNOSNOOPEN | output | TCELL32:OUT16.TMIN |
| CFGDEVCONTROLPHANTOMEN | output | TCELL31:OUT16.TMIN |
| CFGDEVCONTROLURERRREPORTINGEN | output | TCELL29:OUT16.TMIN |
| CFGDEVSTATUSCORRERRDETECTED | output | TCELL21:OUT17.TMIN |
| CFGDEVSTATUSFATALERRDETECTED | output | TCELL22:OUT17.TMIN |
| CFGDEVSTATUSNONFATALERRDETECTED | output | TCELL22:OUT16.TMIN |
| CFGDEVSTATUSURDETECTED | output | TCELL22:OUT18.TMIN |
| CFGDI0 | input | TCELL14:IMUX.IMUX14.DELAY |
| CFGDI1 | input | TCELL14:IMUX.IMUX16.DELAY |
| CFGDI10 | input | TCELL17:IMUX.IMUX9.DELAY |
| CFGDI11 | input | TCELL17:IMUX.IMUX10.DELAY |
| CFGDI12 | input | TCELL17:IMUX.IMUX11.DELAY |
| CFGDI13 | input | TCELL17:IMUX.IMUX12.DELAY |
| CFGDI14 | input | TCELL18:IMUX.IMUX9.DELAY |
| CFGDI15 | input | TCELL18:IMUX.IMUX10.DELAY |
| CFGDI16 | input | TCELL18:IMUX.IMUX11.DELAY |
| CFGDI17 | input | TCELL18:IMUX.IMUX12.DELAY |
| CFGDI18 | input | TCELL19:IMUX.IMUX9.DELAY |
| CFGDI19 | input | TCELL19:IMUX.IMUX10.DELAY |
| CFGDI2 | input | TCELL15:IMUX.IMUX10.DELAY |
| CFGDI20 | input | TCELL19:IMUX.IMUX11.DELAY |
| CFGDI21 | input | TCELL19:IMUX.IMUX12.DELAY |
| CFGDI22 | input | TCELL18:IMUX.IMUX13.DELAY |
| CFGDI23 | input | TCELL18:IMUX.IMUX14.DELAY |
| CFGDI24 | input | TCELL18:IMUX.IMUX15.DELAY |
| CFGDI25 | input | TCELL18:IMUX.IMUX16.DELAY |
| CFGDI26 | input | TCELL17:IMUX.IMUX13.DELAY |
| CFGDI27 | input | TCELL17:IMUX.IMUX14.DELAY |
| CFGDI28 | input | TCELL17:IMUX.IMUX15.DELAY |
| CFGDI29 | input | TCELL17:IMUX.IMUX16.DELAY |
| CFGDI3 | input | TCELL15:IMUX.IMUX12.DELAY |
| CFGDI30 | input | TCELL16:IMUX.IMUX13.DELAY |
| CFGDI31 | input | TCELL16:IMUX.IMUX14.DELAY |
| CFGDI4 | input | TCELL15:IMUX.IMUX13.DELAY |
| CFGDI5 | input | TCELL15:IMUX.IMUX14.DELAY |
| CFGDI6 | input | TCELL16:IMUX.IMUX9.DELAY |
| CFGDI7 | input | TCELL16:IMUX.IMUX10.DELAY |
| CFGDI8 | input | TCELL16:IMUX.IMUX11.DELAY |
| CFGDI9 | input | TCELL16:IMUX.IMUX12.DELAY |
| CFGDO0 | output | TCELL22:OUT15.TMIN |
| CFGDO1 | output | TCELL23:OUT12.TMIN |
| CFGDO10 | output | TCELL29:OUT12.TMIN |
| CFGDO11 | output | TCELL29:OUT13.TMIN |
| CFGDO12 | output | TCELL29:OUT14.TMIN |
| CFGDO13 | output | TCELL29:OUT15.TMIN |
| CFGDO14 | output | TCELL30:OUT12.TMIN |
| CFGDO15 | output | TCELL30:OUT13.TMIN |
| CFGDO16 | output | TCELL30:OUT14.TMIN |
| CFGDO17 | output | TCELL30:OUT15.TMIN |
| CFGDO18 | output | TCELL31:OUT12.TMIN |
| CFGDO19 | output | TCELL31:OUT13.TMIN |
| CFGDO2 | output | TCELL23:OUT13.TMIN |
| CFGDO20 | output | TCELL31:OUT14.TMIN |
| CFGDO21 | output | TCELL31:OUT15.TMIN |
| CFGDO22 | output | TCELL32:OUT12.TMIN |
| CFGDO23 | output | TCELL32:OUT13.TMIN |
| CFGDO24 | output | TCELL32:OUT14.TMIN |
| CFGDO25 | output | TCELL32:OUT15.TMIN |
| CFGDO26 | output | TCELL33:OUT12.TMIN |
| CFGDO27 | output | TCELL33:OUT13.TMIN |
| CFGDO28 | output | TCELL33:OUT14.TMIN |
| CFGDO29 | output | TCELL33:OUT15.TMIN |
| CFGDO3 | output | TCELL23:OUT14.TMIN |
| CFGDO30 | output | TCELL34:OUT14.TMIN |
| CFGDO31 | output | TCELL35:OUT12.TMIN |
| CFGDO4 | output | TCELL23:OUT15.TMIN |
| CFGDO5 | output | TCELL24:OUT14.TMIN |
| CFGDO6 | output | TCELL25:OUT12.TMIN |
| CFGDO7 | output | TCELL26:OUT8.TMIN |
| CFGDO8 | output | TCELL27:OUT4.TMIN |
| CFGDO9 | output | TCELL28:OUT4.TMIN |
| CFGDSBUSNUMBER0 | input | TCELL0:IMUX.IMUX10.DELAY |
| CFGDSBUSNUMBER1 | input | TCELL0:IMUX.IMUX12.DELAY |
| CFGDSBUSNUMBER2 | input | TCELL0:IMUX.IMUX14.DELAY |
| CFGDSBUSNUMBER3 | input | TCELL0:IMUX.IMUX16.DELAY |
| CFGDSBUSNUMBER4 | input | TCELL20:IMUX.IMUX10.DELAY |
| CFGDSBUSNUMBER5 | input | TCELL20:IMUX.IMUX12.DELAY |
| CFGDSBUSNUMBER6 | input | TCELL20:IMUX.IMUX14.DELAY |
| CFGDSBUSNUMBER7 | input | TCELL20:IMUX.IMUX16.DELAY |
| CFGDSDEVICENUMBER0 | input | TCELL21:IMUX.IMUX10.DELAY |
| CFGDSDEVICENUMBER1 | input | TCELL21:IMUX.IMUX12.DELAY |
| CFGDSDEVICENUMBER2 | input | TCELL21:IMUX.IMUX14.DELAY |
| CFGDSDEVICENUMBER3 | input | TCELL21:IMUX.IMUX16.DELAY |
| CFGDSDEVICENUMBER4 | input | TCELL22:IMUX.IMUX14.DELAY |
| CFGDSFUNCTIONNUMBER0 | input | TCELL22:IMUX.IMUX16.DELAY |
| CFGDSFUNCTIONNUMBER1 | input | TCELL22:IMUX.IMUX18.DELAY |
| CFGDSFUNCTIONNUMBER2 | input | TCELL22:IMUX.IMUX19.DELAY |
| CFGDSN0 | input | TCELL26:IMUX.IMUX19.DELAY |
| CFGDSN1 | input | TCELL27:IMUX.IMUX16.DELAY |
| CFGDSN10 | input | TCELL29:IMUX.IMUX17.DELAY |
| CFGDSN11 | input | TCELL29:IMUX.IMUX18.DELAY |
| CFGDSN12 | input | TCELL29:IMUX.IMUX19.DELAY |
| CFGDSN13 | input | TCELL33:IMUX.IMUX14.DELAY |
| CFGDSN14 | input | TCELL33:IMUX.IMUX16.DELAY |
| CFGDSN15 | input | TCELL33:IMUX.IMUX17.DELAY |
| CFGDSN16 | input | TCELL33:IMUX.IMUX18.DELAY |
| CFGDSN17 | input | TCELL34:IMUX.IMUX18.DELAY |
| CFGDSN18 | input | TCELL35:IMUX.IMUX15.DELAY |
| CFGDSN19 | input | TCELL35:IMUX.IMUX16.DELAY |
| CFGDSN2 | input | TCELL27:IMUX.IMUX17.DELAY |
| CFGDSN20 | input | TCELL35:IMUX.IMUX17.DELAY |
| CFGDSN21 | input | TCELL35:IMUX.IMUX18.DELAY |
| CFGDSN22 | input | TCELL36:IMUX.IMUX13.DELAY |
| CFGDSN23 | input | TCELL36:IMUX.IMUX14.DELAY |
| CFGDSN24 | input | TCELL36:IMUX.IMUX15.DELAY |
| CFGDSN25 | input | TCELL36:IMUX.IMUX16.DELAY |
| CFGDSN26 | input | TCELL37:IMUX.IMUX13.DELAY |
| CFGDSN27 | input | TCELL37:IMUX.IMUX14.DELAY |
| CFGDSN28 | input | TCELL37:IMUX.IMUX15.DELAY |
| CFGDSN29 | input | TCELL37:IMUX.IMUX16.DELAY |
| CFGDSN3 | input | TCELL27:IMUX.IMUX18.DELAY |
| CFGDSN30 | input | TCELL38:IMUX.IMUX13.DELAY |
| CFGDSN31 | input | TCELL38:IMUX.IMUX14.DELAY |
| CFGDSN32 | input | TCELL38:IMUX.IMUX15.DELAY |
| CFGDSN33 | input | TCELL38:IMUX.IMUX16.DELAY |
| CFGDSN34 | input | TCELL39:IMUX.IMUX13.DELAY |
| CFGDSN35 | input | TCELL39:IMUX.IMUX14.DELAY |
| CFGDSN36 | input | TCELL39:IMUX.IMUX15.DELAY |
| CFGDSN37 | input | TCELL39:IMUX.IMUX16.DELAY |
| CFGDSN38 | input | TCELL19:IMUX.IMUX17.DELAY |
| CFGDSN39 | input | TCELL19:IMUX.IMUX18.DELAY |
| CFGDSN4 | input | TCELL27:IMUX.IMUX19.DELAY |
| CFGDSN40 | input | TCELL19:IMUX.IMUX19.DELAY |
| CFGDSN41 | input | TCELL19:IMUX.IMUX20.DELAY |
| CFGDSN42 | input | TCELL18:IMUX.IMUX21.DELAY |
| CFGDSN43 | input | TCELL17:IMUX.IMUX21.DELAY |
| CFGDSN44 | input | TCELL16:IMUX.IMUX21.DELAY |
| CFGDSN45 | input | TCELL13:IMUX.IMUX18.DELAY |
| CFGDSN46 | input | TCELL9:IMUX.IMUX16.DELAY |
| CFGDSN47 | input | TCELL9:IMUX.IMUX17.DELAY |
| CFGDSN48 | input | TCELL9:IMUX.IMUX18.DELAY |
| CFGDSN49 | input | TCELL9:IMUX.IMUX19.DELAY |
| CFGDSN5 | input | TCELL28:IMUX.IMUX16.DELAY |
| CFGDSN50 | input | TCELL8:IMUX.IMUX16.DELAY |
| CFGDSN51 | input | TCELL8:IMUX.IMUX17.DELAY |
| CFGDSN52 | input | TCELL8:IMUX.IMUX18.DELAY |
| CFGDSN53 | input | TCELL8:IMUX.IMUX19.DELAY |
| CFGDSN54 | input | TCELL7:IMUX.IMUX16.DELAY |
| CFGDSN55 | input | TCELL7:IMUX.IMUX17.DELAY |
| CFGDSN56 | input | TCELL7:IMUX.IMUX18.DELAY |
| CFGDSN57 | input | TCELL7:IMUX.IMUX19.DELAY |
| CFGDSN58 | input | TCELL6:IMUX.IMUX16.DELAY |
| CFGDSN59 | input | TCELL6:IMUX.IMUX17.DELAY |
| CFGDSN6 | input | TCELL28:IMUX.IMUX17.DELAY |
| CFGDSN60 | input | TCELL6:IMUX.IMUX18.DELAY |
| CFGDSN61 | input | TCELL6:IMUX.IMUX19.DELAY |
| CFGDSN62 | input | TCELL5:IMUX.IMUX18.DELAY |
| CFGDSN63 | input | TCELL3:IMUX.IMUX18.DELAY |
| CFGDSN7 | input | TCELL28:IMUX.IMUX18.DELAY |
| CFGDSN8 | input | TCELL28:IMUX.IMUX19.DELAY |
| CFGDSN9 | input | TCELL29:IMUX.IMUX16.DELAY |
| CFGDWADDR0 | input | TCELL15:IMUX.IMUX17.DELAY |
| CFGDWADDR1 | input | TCELL15:IMUX.IMUX18.DELAY |
| CFGDWADDR2 | input | TCELL14:IMUX.IMUX17.DELAY |
| CFGDWADDR3 | input | TCELL14:IMUX.IMUX18.DELAY |
| CFGDWADDR4 | input | TCELL13:IMUX.IMUX9.DELAY |
| CFGDWADDR5 | input | TCELL13:IMUX.IMUX10.DELAY |
| CFGDWADDR6 | input | TCELL13:IMUX.IMUX11.DELAY |
| CFGDWADDR7 | input | TCELL13:IMUX.IMUX12.DELAY |
| CFGDWADDR8 | input | TCELL12:IMUX.IMUX6.DELAY |
| CFGDWADDR9 | input | TCELL12:IMUX.IMUX8.DELAY |
| CFGERRACSN | input | TCELL9:IMUX.IMUX8.DELAY |
| CFGERRAERHEADERLOG0 | input | TCELL9:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG1 | input | TCELL8:IMUX.IMUX8.DELAY |
| CFGERRAERHEADERLOG10 | input | TCELL6:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG100 | input | TCELL35:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG101 | input | TCELL36:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG102 | input | TCELL36:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG103 | input | TCELL36:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG104 | input | TCELL36:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG105 | input | TCELL37:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG106 | input | TCELL37:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG107 | input | TCELL37:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG108 | input | TCELL37:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG109 | input | TCELL38:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG11 | input | TCELL6:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG110 | input | TCELL38:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG111 | input | TCELL38:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG112 | input | TCELL38:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG113 | input | TCELL39:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG114 | input | TCELL39:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG115 | input | TCELL39:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG116 | input | TCELL39:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG117 | input | TCELL19:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG118 | input | TCELL19:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG119 | input | TCELL19:IMUX.IMUX15.DELAY |
| CFGERRAERHEADERLOG12 | input | TCELL6:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG120 | input | TCELL19:IMUX.IMUX16.DELAY |
| CFGERRAERHEADERLOG121 | input | TCELL18:IMUX.IMUX17.DELAY |
| CFGERRAERHEADERLOG122 | input | TCELL18:IMUX.IMUX18.DELAY |
| CFGERRAERHEADERLOG123 | input | TCELL18:IMUX.IMUX19.DELAY |
| CFGERRAERHEADERLOG124 | input | TCELL18:IMUX.IMUX20.DELAY |
| CFGERRAERHEADERLOG125 | input | TCELL17:IMUX.IMUX17.DELAY |
| CFGERRAERHEADERLOG126 | input | TCELL17:IMUX.IMUX18.DELAY |
| CFGERRAERHEADERLOG127 | input | TCELL17:IMUX.IMUX19.DELAY |
| CFGERRAERHEADERLOG13 | input | TCELL5:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG14 | input | TCELL5:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG15 | input | TCELL5:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG16 | input | TCELL5:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG17 | input | TCELL4:IMUX.IMUX8.DELAY |
| CFGERRAERHEADERLOG18 | input | TCELL4:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG19 | input | TCELL4:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG2 | input | TCELL8:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG20 | input | TCELL4:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG21 | input | TCELL3:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG22 | input | TCELL3:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG23 | input | TCELL3:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG24 | input | TCELL3:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG25 | input | TCELL2:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG26 | input | TCELL2:IMUX.IMUX8.DELAY |
| CFGERRAERHEADERLOG27 | input | TCELL2:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG28 | input | TCELL2:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG29 | input | TCELL1:IMUX.IMUX2.DELAY |
| CFGERRAERHEADERLOG3 | input | TCELL8:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG30 | input | TCELL1:IMUX.IMUX4.DELAY |
| CFGERRAERHEADERLOG31 | input | TCELL1:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG32 | input | TCELL1:IMUX.IMUX8.DELAY |
| CFGERRAERHEADERLOG33 | input | TCELL0:IMUX.IMUX2.DELAY |
| CFGERRAERHEADERLOG34 | input | TCELL0:IMUX.IMUX4.DELAY |
| CFGERRAERHEADERLOG35 | input | TCELL0:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG36 | input | TCELL0:IMUX.IMUX8.DELAY |
| CFGERRAERHEADERLOG37 | input | TCELL20:IMUX.IMUX2.DELAY |
| CFGERRAERHEADERLOG38 | input | TCELL20:IMUX.IMUX4.DELAY |
| CFGERRAERHEADERLOG39 | input | TCELL20:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG4 | input | TCELL8:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG40 | input | TCELL20:IMUX.IMUX8.DELAY |
| CFGERRAERHEADERLOG41 | input | TCELL21:IMUX.IMUX2.DELAY |
| CFGERRAERHEADERLOG42 | input | TCELL21:IMUX.IMUX4.DELAY |
| CFGERRAERHEADERLOG43 | input | TCELL21:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG44 | input | TCELL21:IMUX.IMUX8.DELAY |
| CFGERRAERHEADERLOG45 | input | TCELL22:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG46 | input | TCELL22:IMUX.IMUX8.DELAY |
| CFGERRAERHEADERLOG47 | input | TCELL22:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG48 | input | TCELL22:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG49 | input | TCELL23:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG5 | input | TCELL7:IMUX.IMUX8.DELAY |
| CFGERRAERHEADERLOG50 | input | TCELL23:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG51 | input | TCELL23:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG52 | input | TCELL23:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG53 | input | TCELL24:IMUX.IMUX8.DELAY |
| CFGERRAERHEADERLOG54 | input | TCELL24:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG55 | input | TCELL24:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG56 | input | TCELL24:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG57 | input | TCELL25:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG58 | input | TCELL25:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG59 | input | TCELL25:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG6 | input | TCELL7:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG60 | input | TCELL25:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG61 | input | TCELL26:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG62 | input | TCELL26:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG63 | input | TCELL26:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG64 | input | TCELL26:IMUX.IMUX15.DELAY |
| CFGERRAERHEADERLOG65 | input | TCELL27:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG66 | input | TCELL27:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG67 | input | TCELL27:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG68 | input | TCELL27:IMUX.IMUX15.DELAY |
| CFGERRAERHEADERLOG69 | input | TCELL28:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG7 | input | TCELL7:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG70 | input | TCELL28:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG71 | input | TCELL28:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG72 | input | TCELL28:IMUX.IMUX15.DELAY |
| CFGERRAERHEADERLOG73 | input | TCELL29:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG74 | input | TCELL29:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG75 | input | TCELL29:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG76 | input | TCELL29:IMUX.IMUX15.DELAY |
| CFGERRAERHEADERLOG77 | input | TCELL30:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG78 | input | TCELL30:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG79 | input | TCELL30:IMUX.IMUX16.DELAY |
| CFGERRAERHEADERLOG8 | input | TCELL7:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG80 | input | TCELL30:IMUX.IMUX18.DELAY |
| CFGERRAERHEADERLOG81 | input | TCELL31:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG82 | input | TCELL31:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG83 | input | TCELL31:IMUX.IMUX16.DELAY |
| CFGERRAERHEADERLOG84 | input | TCELL31:IMUX.IMUX18.DELAY |
| CFGERRAERHEADERLOG85 | input | TCELL32:IMUX.IMUX16.DELAY |
| CFGERRAERHEADERLOG86 | input | TCELL32:IMUX.IMUX18.DELAY |
| CFGERRAERHEADERLOG87 | input | TCELL32:IMUX.IMUX19.DELAY |
| CFGERRAERHEADERLOG88 | input | TCELL32:IMUX.IMUX20.DELAY |
| CFGERRAERHEADERLOG89 | input | TCELL33:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG9 | input | TCELL6:IMUX.IMUX8.DELAY |
| CFGERRAERHEADERLOG90 | input | TCELL33:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG91 | input | TCELL33:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG92 | input | TCELL33:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG93 | input | TCELL34:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG94 | input | TCELL34:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG95 | input | TCELL34:IMUX.IMUX16.DELAY |
| CFGERRAERHEADERLOG96 | input | TCELL34:IMUX.IMUX17.DELAY |
| CFGERRAERHEADERLOG97 | input | TCELL35:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG98 | input | TCELL35:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG99 | input | TCELL35:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOGSETN | output | TCELL37:OUT4.TMIN |
| CFGERRCORN | input | TCELL11:IMUX.IMUX6.DELAY |
| CFGERRCPLABORTN | input | TCELL10:IMUX.IMUX6.DELAY |
| CFGERRCPLRDYN | output | TCELL38:OUT4.TMIN |
| CFGERRCPLTIMEOUTN | input | TCELL10:IMUX.IMUX4.DELAY |
| CFGERRCPLUNEXPECTN | input | TCELL10:IMUX.IMUX8.DELAY |
| CFGERRECRCN | input | TCELL10:IMUX.IMUX2.DELAY |
| CFGERRLOCKEDN | input | TCELL9:IMUX.IMUX10.DELAY |
| CFGERRPOSTEDN | input | TCELL9:IMUX.IMUX9.DELAY |
| CFGERRTLPCPLHEADER0 | input | TCELL17:IMUX.IMUX20.DELAY |
| CFGERRTLPCPLHEADER1 | input | TCELL16:IMUX.IMUX17.DELAY |
| CFGERRTLPCPLHEADER10 | input | TCELL12:IMUX.IMUX14.DELAY |
| CFGERRTLPCPLHEADER11 | input | TCELL12:IMUX.IMUX16.DELAY |
| CFGERRTLPCPLHEADER12 | input | TCELL12:IMUX.IMUX18.DELAY |
| CFGERRTLPCPLHEADER13 | input | TCELL12:IMUX.IMUX19.DELAY |
| CFGERRTLPCPLHEADER14 | input | TCELL11:IMUX.IMUX10.DELAY |
| CFGERRTLPCPLHEADER15 | input | TCELL11:IMUX.IMUX12.DELAY |
| CFGERRTLPCPLHEADER16 | input | TCELL11:IMUX.IMUX14.DELAY |
| CFGERRTLPCPLHEADER17 | input | TCELL11:IMUX.IMUX16.DELAY |
| CFGERRTLPCPLHEADER18 | input | TCELL10:IMUX.IMUX10.DELAY |
| CFGERRTLPCPLHEADER19 | input | TCELL10:IMUX.IMUX12.DELAY |
| CFGERRTLPCPLHEADER2 | input | TCELL16:IMUX.IMUX18.DELAY |
| CFGERRTLPCPLHEADER20 | input | TCELL10:IMUX.IMUX14.DELAY |
| CFGERRTLPCPLHEADER21 | input | TCELL10:IMUX.IMUX16.DELAY |
| CFGERRTLPCPLHEADER22 | input | TCELL9:IMUX.IMUX12.DELAY |
| CFGERRTLPCPLHEADER23 | input | TCELL9:IMUX.IMUX13.DELAY |
| CFGERRTLPCPLHEADER24 | input | TCELL9:IMUX.IMUX14.DELAY |
| CFGERRTLPCPLHEADER25 | input | TCELL9:IMUX.IMUX15.DELAY |
| CFGERRTLPCPLHEADER26 | input | TCELL8:IMUX.IMUX12.DELAY |
| CFGERRTLPCPLHEADER27 | input | TCELL8:IMUX.IMUX13.DELAY |
| CFGERRTLPCPLHEADER28 | input | TCELL8:IMUX.IMUX14.DELAY |
| CFGERRTLPCPLHEADER29 | input | TCELL8:IMUX.IMUX15.DELAY |
| CFGERRTLPCPLHEADER3 | input | TCELL16:IMUX.IMUX19.DELAY |
| CFGERRTLPCPLHEADER30 | input | TCELL7:IMUX.IMUX12.DELAY |
| CFGERRTLPCPLHEADER31 | input | TCELL7:IMUX.IMUX13.DELAY |
| CFGERRTLPCPLHEADER32 | input | TCELL7:IMUX.IMUX14.DELAY |
| CFGERRTLPCPLHEADER33 | input | TCELL7:IMUX.IMUX15.DELAY |
| CFGERRTLPCPLHEADER34 | input | TCELL6:IMUX.IMUX12.DELAY |
| CFGERRTLPCPLHEADER35 | input | TCELL6:IMUX.IMUX13.DELAY |
| CFGERRTLPCPLHEADER36 | input | TCELL6:IMUX.IMUX14.DELAY |
| CFGERRTLPCPLHEADER37 | input | TCELL6:IMUX.IMUX15.DELAY |
| CFGERRTLPCPLHEADER38 | input | TCELL5:IMUX.IMUX14.DELAY |
| CFGERRTLPCPLHEADER39 | input | TCELL5:IMUX.IMUX15.DELAY |
| CFGERRTLPCPLHEADER4 | input | TCELL16:IMUX.IMUX20.DELAY |
| CFGERRTLPCPLHEADER40 | input | TCELL5:IMUX.IMUX16.DELAY |
| CFGERRTLPCPLHEADER41 | input | TCELL5:IMUX.IMUX17.DELAY |
| CFGERRTLPCPLHEADER42 | input | TCELL4:IMUX.IMUX13.DELAY |
| CFGERRTLPCPLHEADER43 | input | TCELL4:IMUX.IMUX14.DELAY |
| CFGERRTLPCPLHEADER44 | input | TCELL4:IMUX.IMUX16.DELAY |
| CFGERRTLPCPLHEADER45 | input | TCELL4:IMUX.IMUX17.DELAY |
| CFGERRTLPCPLHEADER46 | input | TCELL3:IMUX.IMUX13.DELAY |
| CFGERRTLPCPLHEADER47 | input | TCELL3:IMUX.IMUX14.DELAY |
| CFGERRTLPCPLHEADER5 | input | TCELL15:IMUX.IMUX20.DELAY |
| CFGERRTLPCPLHEADER6 | input | TCELL13:IMUX.IMUX13.DELAY |
| CFGERRTLPCPLHEADER7 | input | TCELL13:IMUX.IMUX14.DELAY |
| CFGERRTLPCPLHEADER8 | input | TCELL13:IMUX.IMUX16.DELAY |
| CFGERRTLPCPLHEADER9 | input | TCELL13:IMUX.IMUX17.DELAY |
| CFGERRURN | input | TCELL11:IMUX.IMUX8.DELAY |
| CFGINTERRUPTASSERTN | input | TCELL1:IMUX.IMUX16.DELAY |
| CFGINTERRUPTDI0 | input | TCELL3:IMUX.IMUX17.DELAY |
| CFGINTERRUPTDI1 | input | TCELL2:IMUX.IMUX14.DELAY |
| CFGINTERRUPTDI2 | input | TCELL2:IMUX.IMUX16.DELAY |
| CFGINTERRUPTDI3 | input | TCELL2:IMUX.IMUX18.DELAY |
| CFGINTERRUPTDI4 | input | TCELL2:IMUX.IMUX19.DELAY |
| CFGINTERRUPTDI5 | input | TCELL1:IMUX.IMUX10.DELAY |
| CFGINTERRUPTDI6 | input | TCELL1:IMUX.IMUX12.DELAY |
| CFGINTERRUPTDI7 | input | TCELL1:IMUX.IMUX14.DELAY |
| CFGINTERRUPTDO0 | output | TCELL19:OUT13.TMIN |
| CFGINTERRUPTDO1 | output | TCELL19:OUT14.TMIN |
| CFGINTERRUPTDO2 | output | TCELL19:OUT15.TMIN |
| CFGINTERRUPTDO3 | output | TCELL18:OUT4.TMIN |
| CFGINTERRUPTDO4 | output | TCELL18:OUT8.TMIN |
| CFGINTERRUPTDO5 | output | TCELL18:OUT9.TMIN |
| CFGINTERRUPTDO6 | output | TCELL18:OUT10.TMIN |
| CFGINTERRUPTDO7 | output | TCELL17:OUT4.TMIN |
| CFGINTERRUPTMMENABLE0 | output | TCELL39:OUT13.TMIN |
| CFGINTERRUPTMMENABLE1 | output | TCELL39:OUT14.TMIN |
| CFGINTERRUPTMMENABLE2 | output | TCELL39:OUT15.TMIN |
| CFGINTERRUPTMSIENABLE | output | TCELL19:OUT12.TMIN |
| CFGINTERRUPTMSIXENABLE | output | TCELL17:OUT7.TMIN |
| CFGINTERRUPTMSIXFM | output | TCELL17:OUT8.TMIN |
| CFGINTERRUPTN | input | TCELL3:IMUX.IMUX16.DELAY |
| CFGINTERRUPTRDYN | output | TCELL39:OUT12.TMIN |
| CFGLINKCONTROLASPMCONTROL0 | output | TCELL17:OUT10.TMIN |
| CFGLINKCONTROLASPMCONTROL1 | output | TCELL16:OUT11.TMIN |
| CFGLINKCONTROLAUTOBANDWIDTHINTEN | output | TCELL12:OUT19.TMIN |
| CFGLINKCONTROLBANDWIDTHINTEN | output | TCELL12:OUT18.TMIN |
| CFGLINKCONTROLCLOCKPMEN | output | TCELL12:OUT16.TMIN |
| CFGLINKCONTROLCOMMONCLOCK | output | TCELL13:OUT17.TMIN |
| CFGLINKCONTROLEXTENDEDSYNC | output | TCELL13:OUT18.TMIN |
| CFGLINKCONTROLHWAUTOWIDTHDIS | output | TCELL12:OUT17.TMIN |
| CFGLINKCONTROLLINKDISABLE | output | TCELL15:OUT13.TMIN |
| CFGLINKCONTROLRCB | output | TCELL15:OUT12.TMIN |
| CFGLINKCONTROLRETRAINLINK | output | TCELL15:OUT14.TMIN |
| CFGLINKSTATUSAUTOBANDWIDTHSTATUS | output | TCELL18:OUT11.TMIN |
| CFGLINKSTATUSBANDWITHSTATUS | output | TCELL19:OUT19.TMIN |
| CFGLINKSTATUSCURRENTSPEED0 | output | TCELL33:OUT17.TMIN |
| CFGLINKSTATUSCURRENTSPEED1 | output | TCELL33:OUT18.TMIN |
| CFGLINKSTATUSDLLACTIVE | output | TCELL19:OUT18.TMIN |
| CFGLINKSTATUSLINKTRAINING | output | TCELL19:OUT17.TMIN |
| CFGLINKSTATUSNEGOTIATEDWIDTH0 | output | TCELL39:OUT16.TMIN |
| CFGLINKSTATUSNEGOTIATEDWIDTH1 | output | TCELL39:OUT17.TMIN |
| CFGLINKSTATUSNEGOTIATEDWIDTH2 | output | TCELL39:OUT18.TMIN |
| CFGLINKSTATUSNEGOTIATEDWIDTH3 | output | TCELL19:OUT16.TMIN |
| CFGMSGDATA0 | output | TCELL16:OUT5.TMIN |
| CFGMSGDATA1 | output | TCELL16:OUT7.TMIN |
| CFGMSGDATA10 | output | TCELL14:OUT13.TMIN |
| CFGMSGDATA11 | output | TCELL13:OUT12.TMIN |
| CFGMSGDATA12 | output | TCELL13:OUT13.TMIN |
| CFGMSGDATA13 | output | TCELL13:OUT14.TMIN |
| CFGMSGDATA14 | output | TCELL13:OUT15.TMIN |
| CFGMSGDATA15 | output | TCELL12:OUT12.TMIN |
| CFGMSGDATA2 | output | TCELL16:OUT8.TMIN |
| CFGMSGDATA3 | output | TCELL16:OUT10.TMIN |
| CFGMSGDATA4 | output | TCELL15:OUT8.TMIN |
| CFGMSGDATA5 | output | TCELL15:OUT9.TMIN |
| CFGMSGDATA6 | output | TCELL15:OUT10.TMIN |
| CFGMSGDATA7 | output | TCELL15:OUT11.TMIN |
| CFGMSGDATA8 | output | TCELL14:OUT11.TMIN |
| CFGMSGDATA9 | output | TCELL14:OUT12.TMIN |
| CFGMSGRECEIVED | output | TCELL17:OUT9.TMIN |
| CFGMSGRECEIVEDASSERTINTA | output | TCELL11:OUT12.TMIN |
| CFGMSGRECEIVEDASSERTINTB | output | TCELL11:OUT14.TMIN |
| CFGMSGRECEIVEDASSERTINTC | output | TCELL10:OUT12.TMIN |
| CFGMSGRECEIVEDASSERTINTD | output | TCELL10:OUT14.TMIN |
| CFGMSGRECEIVEDDEASSERTINTA | output | TCELL11:OUT13.TMIN |
| CFGMSGRECEIVEDDEASSERTINTB | output | TCELL11:OUT15.TMIN |
| CFGMSGRECEIVEDDEASSERTINTC | output | TCELL10:OUT13.TMIN |
| CFGMSGRECEIVEDDEASSERTINTD | output | TCELL10:OUT15.TMIN |
| CFGMSGRECEIVEDERRCOR | output | TCELL12:OUT13.TMIN |
| CFGMSGRECEIVEDERRFATAL | output | TCELL12:OUT15.TMIN |
| CFGMSGRECEIVEDERRNONFATAL | output | TCELL12:OUT14.TMIN |
| CFGMSGRECEIVEDPMASNAK | output | TCELL7:OUT10.TMIN |
| CFGMSGRECEIVEDPMETO | output | TCELL9:OUT14.TMIN |
| CFGMSGRECEIVEDPMETOACK | output | TCELL9:OUT13.TMIN |
| CFGMSGRECEIVEDPMPME | output | TCELL9:OUT12.TMIN |
| CFGMSGRECEIVEDSETSLOTPOWERLIMIT | output | TCELL9:OUT15.TMIN |
| CFGMSGRECEIVEDUNLOCK | output | TCELL8:OUT10.TMIN |
| CFGPCIELINKSTATE0 | output | TCELL6:OUT12.TMIN |
| CFGPCIELINKSTATE1 | output | TCELL5:OUT12.TMIN |
| CFGPCIELINKSTATE2 | output | TCELL4:OUT14.TMIN |
| CFGPMCSRPMEEN | output | TCELL12:OUT21.TMIN |
| CFGPMCSRPMESTATUS | output | TCELL13:OUT20.TMIN |
| CFGPMCSRPOWERSTATE0 | output | TCELL9:OUT23.TMIN |
| CFGPMCSRPOWERSTATE1 | output | TCELL9:OUT22.TMIN |
| CFGPMDIRECTASPML1N | input | TCELL25:IMUX.IMUX16.DELAY |
| CFGPMRCVASREQL1N | output | TCELL4:OUT15.TMIN |
| CFGPMRCVENTERL1N | output | TCELL3:OUT12.TMIN |
| CFGPMRCVENTERL23N | output | TCELL3:OUT13.TMIN |
| CFGPMRCVREQACKN | output | TCELL3:OUT14.TMIN |
| CFGPMSENDPMACKN | input | TCELL25:IMUX.IMUX18.DELAY |
| CFGPMSENDPMETON | input | TCELL26:IMUX.IMUX17.DELAY |
| CFGPMSENDPMNAKN | input | TCELL26:IMUX.IMUX16.DELAY |
| CFGPMTURNOFFOKN | input | TCELL25:IMUX.IMUX17.DELAY |
| CFGPMWAKEN | input | TCELL25:IMUX.IMUX15.DELAY |
| CFGPORTNUMBER0 | input | TCELL23:IMUX.IMUX14.DELAY |
| CFGPORTNUMBER1 | input | TCELL23:IMUX.IMUX16.DELAY |
| CFGPORTNUMBER2 | input | TCELL23:IMUX.IMUX17.DELAY |
| CFGPORTNUMBER3 | input | TCELL23:IMUX.IMUX18.DELAY |
| CFGPORTNUMBER4 | input | TCELL24:IMUX.IMUX13.DELAY |
| CFGPORTNUMBER5 | input | TCELL24:IMUX.IMUX14.DELAY |
| CFGPORTNUMBER6 | input | TCELL24:IMUX.IMUX16.DELAY |
| CFGPORTNUMBER7 | input | TCELL24:IMUX.IMUX17.DELAY |
| CFGRDENN | input | TCELL11:IMUX.IMUX4.DELAY |
| CFGRDWRDONEN | output | TCELL36:OUT8.TMIN |
| CFGSLOTCONTROLELECTROMECHILCTLPULSE | output | TCELL10:OUT17.TMIN |
| CFGTRANSACTION | output | TCELL3:OUT15.TMIN |
| CFGTRANSACTIONADDR0 | output | TCELL2:OUT13.TMIN |
| CFGTRANSACTIONADDR1 | output | TCELL2:OUT14.TMIN |
| CFGTRANSACTIONADDR2 | output | TCELL2:OUT15.TMIN |
| CFGTRANSACTIONADDR3 | output | TCELL1:OUT12.TMIN |
| CFGTRANSACTIONADDR4 | output | TCELL1:OUT13.TMIN |
| CFGTRANSACTIONADDR5 | output | TCELL1:OUT14.TMIN |
| CFGTRANSACTIONADDR6 | output | TCELL1:OUT15.TMIN |
| CFGTRANSACTIONTYPE | output | TCELL2:OUT12.TMIN |
| CFGTRNPENDINGN | input | TCELL26:IMUX.IMUX18.DELAY |
| CFGVCTCVCMAP0 | output | TCELL9:OUT16.TMIN |
| CFGVCTCVCMAP1 | output | TCELL9:OUT17.TMIN |
| CFGVCTCVCMAP2 | output | TCELL9:OUT18.TMIN |
| CFGVCTCVCMAP3 | output | TCELL9:OUT19.TMIN |
| CFGVCTCVCMAP4 | output | TCELL8:OUT12.TMIN |
| CFGVCTCVCMAP5 | output | TCELL8:OUT13.TMIN |
| CFGVCTCVCMAP6 | output | TCELL8:OUT14.TMIN |
| CFGWRENN | input | TCELL11:IMUX.IMUX2.DELAY |
| CFGWRREADONLYN | input | TCELL12:IMUX.IMUX12.DELAY |
| CFGWRRW1CASRWN | input | TCELL12:IMUX.IMUX10.DELAY |
| CMRSTN | input | TCELL20:IMUX.CTRL1 |
| CMSTICKYRSTN | input | TCELL21:IMUX.CTRL0 |
| DBGMODE0 | input | TCELL7:IMUX.IMUX20.DELAY |
| DBGMODE1 | input | TCELL6:IMUX.IMUX20.DELAY |
| DBGSCLRA | output | TCELL30:OUT20.TMIN |
| DBGSCLRB | output | TCELL31:OUT19.TMIN |
| DBGSCLRC | output | TCELL32:OUT19.TMIN |
| DBGSCLRD | output | TCELL32:OUT20.TMIN |
| DBGSCLRE | output | TCELL33:OUT19.TMIN |
| DBGSCLRF | output | TCELL33:OUT20.TMIN |
| DBGSCLRG | output | TCELL34:OUT15.TMIN |
| DBGSCLRH | output | TCELL34:OUT16.TMIN |
| DBGSCLRI | output | TCELL35:OUT13.TMIN |
| DBGSCLRJ | output | TCELL35:OUT14.TMIN |
| DBGSCLRK | output | TCELL35:OUT15.TMIN |
| DBGSUBMODE | input | TCELL36:IMUX.IMUX21.DELAY |
| DBGVECA0 | output | TCELL10:OUT21.TMIN |
| DBGVECA1 | output | TCELL10:OUT22.TMIN |
| DBGVECA10 | output | TCELL5:OUT15.TMIN |
| DBGVECA11 | output | TCELL5:OUT17.TMIN |
| DBGVECA12 | output | TCELL5:OUT21.TMIN |
| DBGVECA13 | output | TCELL4:OUT18.TMIN |
| DBGVECA14 | output | TCELL4:OUT20.TMIN |
| DBGVECA15 | output | TCELL4:OUT22.TMIN |
| DBGVECA16 | output | TCELL3:OUT20.TMIN |
| DBGVECA17 | output | TCELL3:OUT21.TMIN |
| DBGVECA18 | output | TCELL3:OUT22.TMIN |
| DBGVECA19 | output | TCELL3:OUT23.TMIN |
| DBGVECA2 | output | TCELL10:OUT23.TMIN |
| DBGVECA20 | output | TCELL2:OUT20.TMIN |
| DBGVECA21 | output | TCELL2:OUT21.TMIN |
| DBGVECA22 | output | TCELL2:OUT22.TMIN |
| DBGVECA23 | output | TCELL2:OUT23.TMIN |
| DBGVECA24 | output | TCELL1:OUT21.TMIN |
| DBGVECA25 | output | TCELL1:OUT23.TMIN |
| DBGVECA26 | output | TCELL0:OUT19.TMIN |
| DBGVECA27 | output | TCELL0:OUT20.TMIN |
| DBGVECA28 | output | TCELL0:OUT21.TMIN |
| DBGVECA29 | output | TCELL0:OUT22.TMIN |
| DBGVECA3 | output | TCELL9:OUT20.TMIN |
| DBGVECA30 | output | TCELL20:OUT21.TMIN |
| DBGVECA31 | output | TCELL20:OUT22.TMIN |
| DBGVECA32 | output | TCELL20:OUT23.TMIN |
| DBGVECA33 | output | TCELL21:OUT20.TMIN |
| DBGVECA34 | output | TCELL21:OUT21.TMIN |
| DBGVECA35 | output | TCELL21:OUT23.TMIN |
| DBGVECA36 | output | TCELL22:OUT21.TMIN |
| DBGVECA37 | output | TCELL22:OUT22.TMIN |
| DBGVECA38 | output | TCELL22:OUT23.TMIN |
| DBGVECA39 | output | TCELL23:OUT21.TMIN |
| DBGVECA4 | output | TCELL7:OUT13.TMIN |
| DBGVECA40 | output | TCELL23:OUT22.TMIN |
| DBGVECA41 | output | TCELL23:OUT23.TMIN |
| DBGVECA42 | output | TCELL24:OUT18.TMIN |
| DBGVECA43 | output | TCELL24:OUT20.TMIN |
| DBGVECA44 | output | TCELL24:OUT22.TMIN |
| DBGVECA45 | output | TCELL25:OUT17.TMIN |
| DBGVECA46 | output | TCELL25:OUT21.TMIN |
| DBGVECA47 | output | TCELL26:OUT13.TMIN |
| DBGVECA48 | output | TCELL26:OUT14.TMIN |
| DBGVECA49 | output | TCELL26:OUT15.TMIN |
| DBGVECA5 | output | TCELL7:OUT14.TMIN |
| DBGVECA50 | output | TCELL26:OUT18.TMIN |
| DBGVECA51 | output | TCELL27:OUT11.TMIN |
| DBGVECA52 | output | TCELL27:OUT12.TMIN |
| DBGVECA53 | output | TCELL27:OUT13.TMIN |
| DBGVECA54 | output | TCELL27:OUT14.TMIN |
| DBGVECA55 | output | TCELL28:OUT11.TMIN |
| DBGVECA56 | output | TCELL28:OUT12.TMIN |
| DBGVECA57 | output | TCELL28:OUT13.TMIN |
| DBGVECA58 | output | TCELL28:OUT14.TMIN |
| DBGVECA59 | output | TCELL29:OUT21.TMIN |
| DBGVECA6 | output | TCELL7:OUT15.TMIN |
| DBGVECA60 | output | TCELL29:OUT22.TMIN |
| DBGVECA61 | output | TCELL29:OUT23.TMIN |
| DBGVECA62 | output | TCELL30:OUT21.TMIN |
| DBGVECA63 | output | TCELL30:OUT22.TMIN |
| DBGVECA7 | output | TCELL6:OUT15.TMIN |
| DBGVECA8 | output | TCELL6:OUT18.TMIN |
| DBGVECA9 | output | TCELL6:OUT22.TMIN |
| DBGVECB0 | output | TCELL30:OUT23.TMIN |
| DBGVECB1 | output | TCELL31:OUT20.TMIN |
| DBGVECB10 | output | TCELL34:OUT18.TMIN |
| DBGVECB11 | output | TCELL34:OUT20.TMIN |
| DBGVECB12 | output | TCELL34:OUT22.TMIN |
| DBGVECB13 | output | TCELL35:OUT17.TMIN |
| DBGVECB14 | output | TCELL35:OUT21.TMIN |
| DBGVECB15 | output | TCELL36:OUT13.TMIN |
| DBGVECB16 | output | TCELL36:OUT14.TMIN |
| DBGVECB17 | output | TCELL36:OUT15.TMIN |
| DBGVECB18 | output | TCELL36:OUT18.TMIN |
| DBGVECB19 | output | TCELL37:OUT11.TMIN |
| DBGVECB2 | output | TCELL31:OUT21.TMIN |
| DBGVECB20 | output | TCELL37:OUT12.TMIN |
| DBGVECB21 | output | TCELL37:OUT13.TMIN |
| DBGVECB22 | output | TCELL37:OUT14.TMIN |
| DBGVECB23 | output | TCELL38:OUT11.TMIN |
| DBGVECB24 | output | TCELL38:OUT12.TMIN |
| DBGVECB25 | output | TCELL38:OUT13.TMIN |
| DBGVECB26 | output | TCELL38:OUT14.TMIN |
| DBGVECB27 | output | TCELL39:OUT21.TMIN |
| DBGVECB28 | output | TCELL39:OUT22.TMIN |
| DBGVECB29 | output | TCELL39:OUT23.TMIN |
| DBGVECB3 | output | TCELL31:OUT23.TMIN |
| DBGVECB30 | output | TCELL19:OUT23.TMIN |
| DBGVECB31 | output | TCELL18:OUT14.TMIN |
| DBGVECB32 | output | TCELL18:OUT15.TMIN |
| DBGVECB33 | output | TCELL17:OUT13.TMIN |
| DBGVECB34 | output | TCELL17:OUT14.TMIN |
| DBGVECB35 | output | TCELL17:OUT15.TMIN |
| DBGVECB36 | output | TCELL16:OUT14.TMIN |
| DBGVECB37 | output | TCELL16:OUT15.TMIN |
| DBGVECB38 | output | TCELL16:OUT22.TMIN |
| DBGVECB39 | output | TCELL15:OUT17.TMIN |
| DBGVECB4 | output | TCELL32:OUT21.TMIN |
| DBGVECB40 | output | TCELL15:OUT21.TMIN |
| DBGVECB41 | output | TCELL14:OUT18.TMIN |
| DBGVECB42 | output | TCELL14:OUT20.TMIN |
| DBGVECB43 | output | TCELL14:OUT22.TMIN |
| DBGVECB44 | output | TCELL13:OUT21.TMIN |
| DBGVECB45 | output | TCELL13:OUT22.TMIN |
| DBGVECB46 | output | TCELL13:OUT23.TMIN |
| DBGVECB47 | output | TCELL12:OUT22.TMIN |
| DBGVECB48 | output | TCELL12:OUT23.TMIN |
| DBGVECB49 | output | TCELL8:OUT11.TMIN |
| DBGVECB5 | output | TCELL32:OUT22.TMIN |
| DBGVECB50 | output | TCELL8:OUT15.TMIN |
| DBGVECB51 | output | TCELL7:OUT11.TMIN |
| DBGVECB52 | output | TCELL7:OUT12.TMIN |
| DBGVECB53 | output | TCELL6:OUT13.TMIN |
| DBGVECB54 | output | TCELL6:OUT14.TMIN |
| DBGVECB55 | output | TCELL5:OUT13.TMIN |
| DBGVECB56 | output | TCELL5:OUT14.TMIN |
| DBGVECB57 | output | TCELL4:OUT16.TMIN |
| DBGVECB58 | output | TCELL1:OUT20.TMIN |
| DBGVECB59 | output | TCELL0:OUT23.TMIN |
| DBGVECB6 | output | TCELL32:OUT23.TMIN |
| DBGVECB60 | output | TCELL21:OUT19.TMIN |
| DBGVECB61 | output | TCELL22:OUT19.TMIN |
| DBGVECB62 | output | TCELL22:OUT20.TMIN |
| DBGVECB63 | output | TCELL23:OUT19.TMIN |
| DBGVECB7 | output | TCELL33:OUT21.TMIN |
| DBGVECB8 | output | TCELL33:OUT22.TMIN |
| DBGVECB9 | output | TCELL33:OUT23.TMIN |
| DBGVECC0 | output | TCELL23:OUT20.TMIN |
| DBGVECC1 | output | TCELL24:OUT15.TMIN |
| DBGVECC10 | output | TCELL29:OUT20.TMIN |
| DBGVECC11 | output | TCELL30:OUT19.TMIN |
| DBGVECC2 | output | TCELL24:OUT16.TMIN |
| DBGVECC3 | output | TCELL25:OUT13.TMIN |
| DBGVECC4 | output | TCELL25:OUT14.TMIN |
| DBGVECC5 | output | TCELL25:OUT15.TMIN |
| DBGVECC6 | output | TCELL26:OUT22.TMIN |
| DBGVECC7 | output | TCELL27:OUT15.TMIN |
| DBGVECC8 | output | TCELL28:OUT15.TMIN |
| DBGVECC9 | output | TCELL29:OUT19.TMIN |
| DLRSTN | input | TCELL22:IMUX.CTRL1 |
| DRPCLK | input | TCELL28:IMUX.CLK0 |
| DRPDADDR0 | input | TCELL28:IMUX.IMUX20.DELAY |
| DRPDADDR1 | input | TCELL29:IMUX.IMUX20.DELAY |
| DRPDADDR2 | input | TCELL29:IMUX.IMUX21.DELAY |
| DRPDADDR3 | input | TCELL29:IMUX.IMUX22.DELAY |
| DRPDADDR4 | input | TCELL33:IMUX.IMUX19.DELAY |
| DRPDADDR5 | input | TCELL35:IMUX.IMUX20.DELAY |
| DRPDADDR6 | input | TCELL36:IMUX.IMUX17.DELAY |
| DRPDADDR7 | input | TCELL36:IMUX.IMUX18.DELAY |
| DRPDADDR8 | input | TCELL36:IMUX.IMUX19.DELAY |
| DRPDEN | input | TCELL26:IMUX.IMUX20.DELAY |
| DRPDI0 | input | TCELL36:IMUX.IMUX20.DELAY |
| DRPDI1 | input | TCELL37:IMUX.IMUX17.DELAY |
| DRPDI10 | input | TCELL39:IMUX.IMUX18.DELAY |
| DRPDI11 | input | TCELL39:IMUX.IMUX19.DELAY |
| DRPDI12 | input | TCELL39:IMUX.IMUX20.DELAY |
| DRPDI13 | input | TCELL19:IMUX.IMUX21.DELAY |
| DRPDI14 | input | TCELL9:IMUX.IMUX20.DELAY |
| DRPDI15 | input | TCELL8:IMUX.IMUX20.DELAY |
| DRPDI2 | input | TCELL37:IMUX.IMUX18.DELAY |
| DRPDI3 | input | TCELL37:IMUX.IMUX19.DELAY |
| DRPDI4 | input | TCELL37:IMUX.IMUX20.DELAY |
| DRPDI5 | input | TCELL38:IMUX.IMUX17.DELAY |
| DRPDI6 | input | TCELL38:IMUX.IMUX18.DELAY |
| DRPDI7 | input | TCELL38:IMUX.IMUX19.DELAY |
| DRPDI8 | input | TCELL38:IMUX.IMUX20.DELAY |
| DRPDI9 | input | TCELL39:IMUX.IMUX17.DELAY |
| DRPDO0 | output | TCELL3:OUT17.TMIN |
| DRPDO1 | output | TCELL3:OUT18.TMIN |
| DRPDO10 | output | TCELL19:OUT20.TMIN |
| DRPDO11 | output | TCELL19:OUT21.TMIN |
| DRPDO12 | output | TCELL12:OUT20.TMIN |
| DRPDO13 | output | TCELL11:OUT21.TMIN |
| DRPDO14 | output | TCELL11:OUT23.TMIN |
| DRPDO15 | output | TCELL10:OUT20.TMIN |
| DRPDO2 | output | TCELL3:OUT19.TMIN |
| DRPDO3 | output | TCELL2:OUT16.TMIN |
| DRPDO4 | output | TCELL2:OUT17.TMIN |
| DRPDO5 | output | TCELL2:OUT18.TMIN |
| DRPDO6 | output | TCELL2:OUT19.TMIN |
| DRPDO7 | output | TCELL1:OUT16.TMIN |
| DRPDO8 | output | TCELL1:OUT17.TMIN |
| DRPDO9 | output | TCELL1:OUT19.TMIN |
| DRPDRDY | output | TCELL3:OUT16.TMIN |
| DRPDWE | input | TCELL27:IMUX.IMUX20.DELAY |
| FUNCLVLRSTN | input | TCELL21:IMUX.CTRL1 |
| LL2BADDLLPERRN | output | TCELL21:OUT12.TMIN |
| LL2BADTLPERRN | output | TCELL0:OUT12.TMIN |
| LL2PROTOCOLERRN | output | TCELL0:OUT11.TMIN |
| LL2REPLAYROERRN | output | TCELL21:OUT13.TMIN |
| LL2REPLAYTOERRN | output | TCELL21:OUT14.TMIN |
| LL2SENDASREQL1N | input | TCELL27:IMUX.IMUX11.DELAY |
| LL2SENDENTERL1N | input | TCELL27:IMUX.IMUX9.DELAY |
| LL2SENDENTERL23N | input | TCELL27:IMUX.IMUX10.DELAY |
| LL2SUSPENDNOWN | input | TCELL29:IMUX.IMUX9.DELAY |
| LL2SUSPENDOKN | output | TCELL1:OUT8.TMIN |
| LL2TFCINIT1SEQN | output | TCELL3:OUT11.TMIN |
| LL2TFCINIT2SEQN | output | TCELL2:OUT8.TMIN |
| LL2TLPRCVN | input | TCELL27:IMUX.IMUX8.DELAY |
| LNKCLKEN | output | TCELL9:OUT21.TMIN |
| MIMRXRADDR0 | output | TCELL37:OUT9.TMIN |
| MIMRXRADDR1 | output | TCELL37:OUT10.TMIN |
| MIMRXRADDR10 | output | TCELL19:OUT8.TMIN |
| MIMRXRADDR11 | output | TCELL19:OUT9.TMIN |
| MIMRXRADDR12 | output | TCELL19:OUT10.TMIN |
| MIMRXRADDR2 | output | TCELL38:OUT7.TMIN |
| MIMRXRADDR3 | output | TCELL38:OUT8.TMIN |
| MIMRXRADDR4 | output | TCELL38:OUT9.TMIN |
| MIMRXRADDR5 | output | TCELL38:OUT10.TMIN |
| MIMRXRADDR6 | output | TCELL39:OUT8.TMIN |
| MIMRXRADDR7 | output | TCELL39:OUT9.TMIN |
| MIMRXRADDR8 | output | TCELL39:OUT10.TMIN |
| MIMRXRADDR9 | output | TCELL39:OUT11.TMIN |
| MIMRXRCE | output | TCELL18:OUT7.TMIN |
| MIMRXRDATA0 | input | TCELL29:IMUX.IMUX6.DELAY |
| MIMRXRDATA1 | input | TCELL29:IMUX.IMUX7.DELAY |
| MIMRXRDATA10 | input | TCELL32:IMUX.IMUX6.DELAY |
| MIMRXRDATA11 | input | TCELL32:IMUX.IMUX8.DELAY |
| MIMRXRDATA12 | input | TCELL32:IMUX.IMUX10.DELAY |
| MIMRXRDATA13 | input | TCELL32:IMUX.IMUX12.DELAY |
| MIMRXRDATA14 | input | TCELL33:IMUX.IMUX5.DELAY |
| MIMRXRDATA15 | input | TCELL33:IMUX.IMUX6.DELAY |
| MIMRXRDATA16 | input | TCELL33:IMUX.IMUX7.DELAY |
| MIMRXRDATA17 | input | TCELL33:IMUX.IMUX8.DELAY |
| MIMRXRDATA18 | input | TCELL34:IMUX.IMUX6.DELAY |
| MIMRXRDATA19 | input | TCELL34:IMUX.IMUX8.DELAY |
| MIMRXRDATA2 | input | TCELL30:IMUX.IMUX2.DELAY |
| MIMRXRDATA20 | input | TCELL34:IMUX.IMUX9.DELAY |
| MIMRXRDATA21 | input | TCELL34:IMUX.IMUX10.DELAY |
| MIMRXRDATA22 | input | TCELL35:IMUX.IMUX4.DELAY |
| MIMRXRDATA23 | input | TCELL35:IMUX.IMUX6.DELAY |
| MIMRXRDATA24 | input | TCELL35:IMUX.IMUX7.DELAY |
| MIMRXRDATA25 | input | TCELL35:IMUX.IMUX8.DELAY |
| MIMRXRDATA26 | input | TCELL36:IMUX.IMUX4.DELAY |
| MIMRXRDATA27 | input | TCELL36:IMUX.IMUX5.DELAY |
| MIMRXRDATA28 | input | TCELL36:IMUX.IMUX6.DELAY |
| MIMRXRDATA29 | input | TCELL36:IMUX.IMUX7.DELAY |
| MIMRXRDATA3 | input | TCELL30:IMUX.IMUX4.DELAY |
| MIMRXRDATA30 | input | TCELL37:IMUX.IMUX4.DELAY |
| MIMRXRDATA31 | input | TCELL37:IMUX.IMUX5.DELAY |
| MIMRXRDATA32 | input | TCELL37:IMUX.IMUX6.DELAY |
| MIMRXRDATA33 | input | TCELL37:IMUX.IMUX7.DELAY |
| MIMRXRDATA34 | input | TCELL38:IMUX.IMUX4.DELAY |
| MIMRXRDATA35 | input | TCELL38:IMUX.IMUX5.DELAY |
| MIMRXRDATA36 | input | TCELL38:IMUX.IMUX6.DELAY |
| MIMRXRDATA37 | input | TCELL38:IMUX.IMUX7.DELAY |
| MIMRXRDATA38 | input | TCELL39:IMUX.IMUX4.DELAY |
| MIMRXRDATA39 | input | TCELL39:IMUX.IMUX5.DELAY |
| MIMRXRDATA4 | input | TCELL30:IMUX.IMUX6.DELAY |
| MIMRXRDATA40 | input | TCELL39:IMUX.IMUX6.DELAY |
| MIMRXRDATA41 | input | TCELL39:IMUX.IMUX7.DELAY |
| MIMRXRDATA42 | input | TCELL19:IMUX.IMUX4.DELAY |
| MIMRXRDATA43 | input | TCELL19:IMUX.IMUX5.DELAY |
| MIMRXRDATA44 | input | TCELL19:IMUX.IMUX6.DELAY |
| MIMRXRDATA45 | input | TCELL19:IMUX.IMUX7.DELAY |
| MIMRXRDATA46 | input | TCELL18:IMUX.IMUX4.DELAY |
| MIMRXRDATA47 | input | TCELL18:IMUX.IMUX5.DELAY |
| MIMRXRDATA48 | input | TCELL18:IMUX.IMUX6.DELAY |
| MIMRXRDATA49 | input | TCELL18:IMUX.IMUX7.DELAY |
| MIMRXRDATA5 | input | TCELL30:IMUX.IMUX8.DELAY |
| MIMRXRDATA50 | input | TCELL17:IMUX.IMUX4.DELAY |
| MIMRXRDATA51 | input | TCELL17:IMUX.IMUX5.DELAY |
| MIMRXRDATA52 | input | TCELL17:IMUX.IMUX6.DELAY |
| MIMRXRDATA53 | input | TCELL17:IMUX.IMUX7.DELAY |
| MIMRXRDATA54 | input | TCELL16:IMUX.IMUX4.DELAY |
| MIMRXRDATA55 | input | TCELL16:IMUX.IMUX5.DELAY |
| MIMRXRDATA56 | input | TCELL16:IMUX.IMUX6.DELAY |
| MIMRXRDATA57 | input | TCELL16:IMUX.IMUX7.DELAY |
| MIMRXRDATA58 | input | TCELL15:IMUX.IMUX4.DELAY |
| MIMRXRDATA59 | input | TCELL15:IMUX.IMUX6.DELAY |
| MIMRXRDATA6 | input | TCELL31:IMUX.IMUX2.DELAY |
| MIMRXRDATA60 | input | TCELL15:IMUX.IMUX7.DELAY |
| MIMRXRDATA61 | input | TCELL15:IMUX.IMUX8.DELAY |
| MIMRXRDATA62 | input | TCELL14:IMUX.IMUX6.DELAY |
| MIMRXRDATA63 | input | TCELL14:IMUX.IMUX8.DELAY |
| MIMRXRDATA64 | input | TCELL14:IMUX.IMUX9.DELAY |
| MIMRXRDATA65 | input | TCELL14:IMUX.IMUX10.DELAY |
| MIMRXRDATA66 | input | TCELL13:IMUX.IMUX5.DELAY |
| MIMRXRDATA67 | input | TCELL13:IMUX.IMUX6.DELAY |
| MIMRXRDATA7 | input | TCELL31:IMUX.IMUX4.DELAY |
| MIMRXRDATA8 | input | TCELL31:IMUX.IMUX6.DELAY |
| MIMRXRDATA9 | input | TCELL31:IMUX.IMUX8.DELAY |
| MIMRXREN | output | TCELL19:OUT11.TMIN |
| MIMRXWADDR0 | output | TCELL34:OUT10.TMIN |
| MIMRXWADDR1 | output | TCELL34:OUT11.TMIN |
| MIMRXWADDR10 | output | TCELL36:OUT11.TMIN |
| MIMRXWADDR11 | output | TCELL36:OUT12.TMIN |
| MIMRXWADDR12 | output | TCELL37:OUT7.TMIN |
| MIMRXWADDR2 | output | TCELL34:OUT12.TMIN |
| MIMRXWADDR3 | output | TCELL34:OUT13.TMIN |
| MIMRXWADDR4 | output | TCELL35:OUT8.TMIN |
| MIMRXWADDR5 | output | TCELL35:OUT9.TMIN |
| MIMRXWADDR6 | output | TCELL35:OUT10.TMIN |
| MIMRXWADDR7 | output | TCELL35:OUT11.TMIN |
| MIMRXWADDR8 | output | TCELL36:OUT9.TMIN |
| MIMRXWADDR9 | output | TCELL36:OUT10.TMIN |
| MIMRXWDATA0 | output | TCELL3:OUT5.TMIN |
| MIMRXWDATA1 | output | TCELL3:OUT6.TMIN |
| MIMRXWDATA10 | output | TCELL1:OUT7.TMIN |
| MIMRXWDATA11 | output | TCELL0:OUT4.TMIN |
| MIMRXWDATA12 | output | TCELL0:OUT5.TMIN |
| MIMRXWDATA13 | output | TCELL0:OUT7.TMIN |
| MIMRXWDATA14 | output | TCELL0:OUT8.TMIN |
| MIMRXWDATA15 | output | TCELL20:OUT20.TMIN |
| MIMRXWDATA16 | output | TCELL21:OUT8.TMIN |
| MIMRXWDATA17 | output | TCELL21:OUT9.TMIN |
| MIMRXWDATA18 | output | TCELL21:OUT10.TMIN |
| MIMRXWDATA19 | output | TCELL21:OUT11.TMIN |
| MIMRXWDATA2 | output | TCELL3:OUT7.TMIN |
| MIMRXWDATA20 | output | TCELL22:OUT8.TMIN |
| MIMRXWDATA21 | output | TCELL22:OUT9.TMIN |
| MIMRXWDATA22 | output | TCELL22:OUT10.TMIN |
| MIMRXWDATA23 | output | TCELL22:OUT11.TMIN |
| MIMRXWDATA24 | output | TCELL23:OUT8.TMIN |
| MIMRXWDATA25 | output | TCELL23:OUT9.TMIN |
| MIMRXWDATA26 | output | TCELL23:OUT10.TMIN |
| MIMRXWDATA27 | output | TCELL23:OUT11.TMIN |
| MIMRXWDATA28 | output | TCELL24:OUT10.TMIN |
| MIMRXWDATA29 | output | TCELL24:OUT11.TMIN |
| MIMRXWDATA3 | output | TCELL2:OUT4.TMIN |
| MIMRXWDATA30 | output | TCELL24:OUT12.TMIN |
| MIMRXWDATA31 | output | TCELL24:OUT13.TMIN |
| MIMRXWDATA32 | output | TCELL25:OUT8.TMIN |
| MIMRXWDATA33 | output | TCELL25:OUT9.TMIN |
| MIMRXWDATA34 | output | TCELL25:OUT10.TMIN |
| MIMRXWDATA35 | output | TCELL25:OUT11.TMIN |
| MIMRXWDATA36 | output | TCELL26:OUT9.TMIN |
| MIMRXWDATA37 | output | TCELL26:OUT10.TMIN |
| MIMRXWDATA38 | output | TCELL26:OUT11.TMIN |
| MIMRXWDATA39 | output | TCELL26:OUT12.TMIN |
| MIMRXWDATA4 | output | TCELL2:OUT5.TMIN |
| MIMRXWDATA40 | output | TCELL27:OUT7.TMIN |
| MIMRXWDATA41 | output | TCELL27:OUT8.TMIN |
| MIMRXWDATA42 | output | TCELL27:OUT9.TMIN |
| MIMRXWDATA43 | output | TCELL27:OUT10.TMIN |
| MIMRXWDATA44 | output | TCELL28:OUT7.TMIN |
| MIMRXWDATA45 | output | TCELL28:OUT8.TMIN |
| MIMRXWDATA46 | output | TCELL28:OUT9.TMIN |
| MIMRXWDATA47 | output | TCELL28:OUT10.TMIN |
| MIMRXWDATA48 | output | TCELL29:OUT8.TMIN |
| MIMRXWDATA49 | output | TCELL29:OUT9.TMIN |
| MIMRXWDATA5 | output | TCELL2:OUT6.TMIN |
| MIMRXWDATA50 | output | TCELL29:OUT10.TMIN |
| MIMRXWDATA51 | output | TCELL29:OUT11.TMIN |
| MIMRXWDATA52 | output | TCELL30:OUT8.TMIN |
| MIMRXWDATA53 | output | TCELL30:OUT9.TMIN |
| MIMRXWDATA54 | output | TCELL30:OUT10.TMIN |
| MIMRXWDATA55 | output | TCELL30:OUT11.TMIN |
| MIMRXWDATA56 | output | TCELL31:OUT8.TMIN |
| MIMRXWDATA57 | output | TCELL31:OUT9.TMIN |
| MIMRXWDATA58 | output | TCELL31:OUT10.TMIN |
| MIMRXWDATA59 | output | TCELL31:OUT11.TMIN |
| MIMRXWDATA6 | output | TCELL2:OUT7.TMIN |
| MIMRXWDATA60 | output | TCELL32:OUT8.TMIN |
| MIMRXWDATA61 | output | TCELL32:OUT9.TMIN |
| MIMRXWDATA62 | output | TCELL32:OUT10.TMIN |
| MIMRXWDATA63 | output | TCELL32:OUT11.TMIN |
| MIMRXWDATA64 | output | TCELL33:OUT8.TMIN |
| MIMRXWDATA65 | output | TCELL33:OUT9.TMIN |
| MIMRXWDATA66 | output | TCELL33:OUT10.TMIN |
| MIMRXWDATA67 | output | TCELL33:OUT11.TMIN |
| MIMRXWDATA7 | output | TCELL1:OUT4.TMIN |
| MIMRXWDATA8 | output | TCELL1:OUT5.TMIN |
| MIMRXWDATA9 | output | TCELL1:OUT6.TMIN |
| MIMRXWEN | output | TCELL37:OUT8.TMIN |
| MIMTXRADDR0 | output | TCELL7:OUT8.TMIN |
| MIMTXRADDR1 | output | TCELL7:OUT9.TMIN |
| MIMTXRADDR10 | output | TCELL4:OUT6.TMIN |
| MIMTXRADDR11 | output | TCELL4:OUT7.TMIN |
| MIMTXRADDR12 | output | TCELL4:OUT8.TMIN |
| MIMTXRADDR2 | output | TCELL6:OUT5.TMIN |
| MIMTXRADDR3 | output | TCELL6:OUT7.TMIN |
| MIMTXRADDR4 | output | TCELL6:OUT8.TMIN |
| MIMTXRADDR5 | output | TCELL6:OUT9.TMIN |
| MIMTXRADDR6 | output | TCELL5:OUT4.TMIN |
| MIMTXRADDR7 | output | TCELL5:OUT5.TMIN |
| MIMTXRADDR8 | output | TCELL5:OUT6.TMIN |
| MIMTXRADDR9 | output | TCELL5:OUT7.TMIN |
| MIMTXRCE | output | TCELL3:OUT4.TMIN |
| MIMTXRDATA0 | input | TCELL14:IMUX.IMUX0.DELAY |
| MIMTXRDATA1 | input | TCELL14:IMUX.IMUX2.DELAY |
| MIMTXRDATA10 | input | TCELL12:IMUX.IMUX4.DELAY |
| MIMTXRDATA11 | input | TCELL11:IMUX.IMUX0.DELAY |
| MIMTXRDATA12 | input | TCELL10:IMUX.IMUX0.DELAY |
| MIMTXRDATA13 | input | TCELL9:IMUX.IMUX0.DELAY |
| MIMTXRDATA14 | input | TCELL9:IMUX.IMUX1.DELAY |
| MIMTXRDATA15 | input | TCELL9:IMUX.IMUX2.DELAY |
| MIMTXRDATA16 | input | TCELL9:IMUX.IMUX3.DELAY |
| MIMTXRDATA17 | input | TCELL8:IMUX.IMUX0.DELAY |
| MIMTXRDATA18 | input | TCELL8:IMUX.IMUX1.DELAY |
| MIMTXRDATA19 | input | TCELL8:IMUX.IMUX2.DELAY |
| MIMTXRDATA2 | input | TCELL14:IMUX.IMUX4.DELAY |
| MIMTXRDATA20 | input | TCELL8:IMUX.IMUX3.DELAY |
| MIMTXRDATA21 | input | TCELL7:IMUX.IMUX0.DELAY |
| MIMTXRDATA22 | input | TCELL7:IMUX.IMUX1.DELAY |
| MIMTXRDATA23 | input | TCELL7:IMUX.IMUX2.DELAY |
| MIMTXRDATA24 | input | TCELL7:IMUX.IMUX3.DELAY |
| MIMTXRDATA25 | input | TCELL6:IMUX.IMUX0.DELAY |
| MIMTXRDATA26 | input | TCELL6:IMUX.IMUX1.DELAY |
| MIMTXRDATA27 | input | TCELL6:IMUX.IMUX2.DELAY |
| MIMTXRDATA28 | input | TCELL6:IMUX.IMUX3.DELAY |
| MIMTXRDATA29 | input | TCELL5:IMUX.IMUX0.DELAY |
| MIMTXRDATA3 | input | TCELL14:IMUX.IMUX5.DELAY |
| MIMTXRDATA30 | input | TCELL5:IMUX.IMUX1.DELAY |
| MIMTXRDATA31 | input | TCELL5:IMUX.IMUX2.DELAY |
| MIMTXRDATA32 | input | TCELL5:IMUX.IMUX3.DELAY |
| MIMTXRDATA33 | input | TCELL4:IMUX.IMUX0.DELAY |
| MIMTXRDATA34 | input | TCELL4:IMUX.IMUX2.DELAY |
| MIMTXRDATA35 | input | TCELL4:IMUX.IMUX4.DELAY |
| MIMTXRDATA36 | input | TCELL4:IMUX.IMUX5.DELAY |
| MIMTXRDATA37 | input | TCELL3:IMUX.IMUX0.DELAY |
| MIMTXRDATA38 | input | TCELL3:IMUX.IMUX2.DELAY |
| MIMTXRDATA39 | input | TCELL3:IMUX.IMUX3.DELAY |
| MIMTXRDATA4 | input | TCELL13:IMUX.IMUX0.DELAY |
| MIMTXRDATA40 | input | TCELL3:IMUX.IMUX4.DELAY |
| MIMTXRDATA41 | input | TCELL2:IMUX.IMUX0.DELAY |
| MIMTXRDATA42 | input | TCELL2:IMUX.IMUX2.DELAY |
| MIMTXRDATA43 | input | TCELL2:IMUX.IMUX4.DELAY |
| MIMTXRDATA44 | input | TCELL1:IMUX.IMUX0.DELAY |
| MIMTXRDATA45 | input | TCELL0:IMUX.IMUX0.DELAY |
| MIMTXRDATA46 | input | TCELL23:IMUX.IMUX5.DELAY |
| MIMTXRDATA47 | input | TCELL23:IMUX.IMUX6.DELAY |
| MIMTXRDATA48 | input | TCELL23:IMUX.IMUX7.DELAY |
| MIMTXRDATA49 | input | TCELL23:IMUX.IMUX8.DELAY |
| MIMTXRDATA5 | input | TCELL13:IMUX.IMUX2.DELAY |
| MIMTXRDATA50 | input | TCELL24:IMUX.IMUX6.DELAY |
| MIMTXRDATA51 | input | TCELL25:IMUX.IMUX4.DELAY |
| MIMTXRDATA52 | input | TCELL25:IMUX.IMUX6.DELAY |
| MIMTXRDATA53 | input | TCELL25:IMUX.IMUX7.DELAY |
| MIMTXRDATA54 | input | TCELL25:IMUX.IMUX8.DELAY |
| MIMTXRDATA55 | input | TCELL26:IMUX.IMUX4.DELAY |
| MIMTXRDATA56 | input | TCELL26:IMUX.IMUX5.DELAY |
| MIMTXRDATA57 | input | TCELL26:IMUX.IMUX6.DELAY |
| MIMTXRDATA58 | input | TCELL26:IMUX.IMUX7.DELAY |
| MIMTXRDATA59 | input | TCELL27:IMUX.IMUX4.DELAY |
| MIMTXRDATA6 | input | TCELL13:IMUX.IMUX3.DELAY |
| MIMTXRDATA60 | input | TCELL27:IMUX.IMUX5.DELAY |
| MIMTXRDATA61 | input | TCELL27:IMUX.IMUX6.DELAY |
| MIMTXRDATA62 | input | TCELL27:IMUX.IMUX7.DELAY |
| MIMTXRDATA63 | input | TCELL28:IMUX.IMUX4.DELAY |
| MIMTXRDATA64 | input | TCELL28:IMUX.IMUX5.DELAY |
| MIMTXRDATA65 | input | TCELL28:IMUX.IMUX6.DELAY |
| MIMTXRDATA66 | input | TCELL28:IMUX.IMUX7.DELAY |
| MIMTXRDATA67 | input | TCELL29:IMUX.IMUX4.DELAY |
| MIMTXRDATA68 | input | TCELL29:IMUX.IMUX5.DELAY |
| MIMTXRDATA7 | input | TCELL13:IMUX.IMUX4.DELAY |
| MIMTXRDATA8 | input | TCELL12:IMUX.IMUX0.DELAY |
| MIMTXRDATA9 | input | TCELL12:IMUX.IMUX2.DELAY |
| MIMTXREN | output | TCELL4:OUT9.TMIN |
| MIMTXWADDR0 | output | TCELL11:OUT4.TMIN |
| MIMTXWADDR1 | output | TCELL11:OUT5.TMIN |
| MIMTXWADDR10 | output | TCELL9:OUT6.TMIN |
| MIMTXWADDR11 | output | TCELL9:OUT7.TMIN |
| MIMTXWADDR12 | output | TCELL8:OUT8.TMIN |
| MIMTXWADDR2 | output | TCELL11:OUT6.TMIN |
| MIMTXWADDR3 | output | TCELL11:OUT7.TMIN |
| MIMTXWADDR4 | output | TCELL10:OUT4.TMIN |
| MIMTXWADDR5 | output | TCELL10:OUT5.TMIN |
| MIMTXWADDR6 | output | TCELL10:OUT6.TMIN |
| MIMTXWADDR7 | output | TCELL10:OUT7.TMIN |
| MIMTXWADDR8 | output | TCELL9:OUT4.TMIN |
| MIMTXWADDR9 | output | TCELL9:OUT5.TMIN |
| MIMTXWDATA0 | output | TCELL22:OUT7.TMIN |
| MIMTXWDATA1 | output | TCELL23:OUT4.TMIN |
| MIMTXWDATA10 | output | TCELL25:OUT5.TMIN |
| MIMTXWDATA11 | output | TCELL25:OUT6.TMIN |
| MIMTXWDATA12 | output | TCELL25:OUT7.TMIN |
| MIMTXWDATA13 | output | TCELL26:OUT5.TMIN |
| MIMTXWDATA14 | output | TCELL26:OUT7.TMIN |
| MIMTXWDATA15 | output | TCELL29:OUT4.TMIN |
| MIMTXWDATA16 | output | TCELL29:OUT5.TMIN |
| MIMTXWDATA17 | output | TCELL29:OUT6.TMIN |
| MIMTXWDATA18 | output | TCELL29:OUT7.TMIN |
| MIMTXWDATA19 | output | TCELL30:OUT4.TMIN |
| MIMTXWDATA2 | output | TCELL23:OUT5.TMIN |
| MIMTXWDATA20 | output | TCELL30:OUT5.TMIN |
| MIMTXWDATA21 | output | TCELL30:OUT6.TMIN |
| MIMTXWDATA22 | output | TCELL30:OUT7.TMIN |
| MIMTXWDATA23 | output | TCELL31:OUT4.TMIN |
| MIMTXWDATA24 | output | TCELL31:OUT5.TMIN |
| MIMTXWDATA25 | output | TCELL31:OUT6.TMIN |
| MIMTXWDATA26 | output | TCELL31:OUT7.TMIN |
| MIMTXWDATA27 | output | TCELL32:OUT4.TMIN |
| MIMTXWDATA28 | output | TCELL32:OUT5.TMIN |
| MIMTXWDATA29 | output | TCELL32:OUT6.TMIN |
| MIMTXWDATA3 | output | TCELL23:OUT6.TMIN |
| MIMTXWDATA30 | output | TCELL32:OUT7.TMIN |
| MIMTXWDATA31 | output | TCELL33:OUT4.TMIN |
| MIMTXWDATA32 | output | TCELL33:OUT5.TMIN |
| MIMTXWDATA33 | output | TCELL33:OUT6.TMIN |
| MIMTXWDATA34 | output | TCELL33:OUT7.TMIN |
| MIMTXWDATA35 | output | TCELL34:OUT6.TMIN |
| MIMTXWDATA36 | output | TCELL34:OUT7.TMIN |
| MIMTXWDATA37 | output | TCELL34:OUT8.TMIN |
| MIMTXWDATA38 | output | TCELL34:OUT9.TMIN |
| MIMTXWDATA39 | output | TCELL35:OUT4.TMIN |
| MIMTXWDATA4 | output | TCELL23:OUT7.TMIN |
| MIMTXWDATA40 | output | TCELL35:OUT5.TMIN |
| MIMTXWDATA41 | output | TCELL35:OUT6.TMIN |
| MIMTXWDATA42 | output | TCELL35:OUT7.TMIN |
| MIMTXWDATA43 | output | TCELL36:OUT5.TMIN |
| MIMTXWDATA44 | output | TCELL36:OUT7.TMIN |
| MIMTXWDATA45 | output | TCELL39:OUT4.TMIN |
| MIMTXWDATA46 | output | TCELL39:OUT5.TMIN |
| MIMTXWDATA47 | output | TCELL39:OUT6.TMIN |
| MIMTXWDATA48 | output | TCELL39:OUT7.TMIN |
| MIMTXWDATA49 | output | TCELL19:OUT4.TMIN |
| MIMTXWDATA5 | output | TCELL24:OUT6.TMIN |
| MIMTXWDATA50 | output | TCELL19:OUT5.TMIN |
| MIMTXWDATA51 | output | TCELL19:OUT6.TMIN |
| MIMTXWDATA52 | output | TCELL19:OUT7.TMIN |
| MIMTXWDATA53 | output | TCELL15:OUT4.TMIN |
| MIMTXWDATA54 | output | TCELL15:OUT5.TMIN |
| MIMTXWDATA55 | output | TCELL15:OUT6.TMIN |
| MIMTXWDATA56 | output | TCELL15:OUT7.TMIN |
| MIMTXWDATA57 | output | TCELL14:OUT6.TMIN |
| MIMTXWDATA58 | output | TCELL14:OUT7.TMIN |
| MIMTXWDATA59 | output | TCELL14:OUT8.TMIN |
| MIMTXWDATA6 | output | TCELL24:OUT7.TMIN |
| MIMTXWDATA60 | output | TCELL14:OUT9.TMIN |
| MIMTXWDATA61 | output | TCELL13:OUT4.TMIN |
| MIMTXWDATA62 | output | TCELL13:OUT5.TMIN |
| MIMTXWDATA63 | output | TCELL13:OUT6.TMIN |
| MIMTXWDATA64 | output | TCELL13:OUT7.TMIN |
| MIMTXWDATA65 | output | TCELL12:OUT4.TMIN |
| MIMTXWDATA66 | output | TCELL12:OUT5.TMIN |
| MIMTXWDATA67 | output | TCELL12:OUT6.TMIN |
| MIMTXWDATA68 | output | TCELL12:OUT7.TMIN |
| MIMTXWDATA7 | output | TCELL24:OUT8.TMIN |
| MIMTXWDATA8 | output | TCELL24:OUT9.TMIN |
| MIMTXWDATA9 | output | TCELL25:OUT4.TMIN |
| MIMTXWEN | output | TCELL8:OUT9.TMIN |
| PIPECLK | input | TCELL29:IMUX.CLK1 |
| PIPERX0CHANISALIGNED | input | TCELL33:IMUX.IMUX21.DELAY |
| PIPERX0CHARISK0 | input | TCELL33:IMUX.IMUX23.DELAY |
| PIPERX0CHARISK1 | input | TCELL32:IMUX.IMUX1.DELAY |
| PIPERX0DATA0 | input | TCELL30:IMUX.IMUX3.DELAY |
| PIPERX0DATA1 | input | TCELL30:IMUX.IMUX5.DELAY |
| PIPERX0DATA10 | input | TCELL31:IMUX.IMUX7.DELAY |
| PIPERX0DATA11 | input | TCELL31:IMUX.IMUX15.DELAY |
| PIPERX0DATA12 | input | TCELL32:IMUX.IMUX5.DELAY |
| PIPERX0DATA13 | input | TCELL32:IMUX.IMUX7.DELAY |
| PIPERX0DATA14 | input | TCELL32:IMUX.IMUX11.DELAY |
| PIPERX0DATA15 | input | TCELL32:IMUX.IMUX9.DELAY |
| PIPERX0DATA2 | input | TCELL30:IMUX.IMUX15.DELAY |
| PIPERX0DATA3 | input | TCELL30:IMUX.IMUX19.DELAY |
| PIPERX0DATA4 | input | TCELL30:IMUX.IMUX1.DELAY |
| PIPERX0DATA5 | input | TCELL30:IMUX.IMUX9.DELAY |
| PIPERX0DATA6 | input | TCELL31:IMUX.IMUX1.DELAY |
| PIPERX0DATA7 | input | TCELL31:IMUX.IMUX9.DELAY |
| PIPERX0DATA8 | input | TCELL31:IMUX.IMUX3.DELAY |
| PIPERX0DATA9 | input | TCELL31:IMUX.IMUX5.DELAY |
| PIPERX0ELECIDLE | input | TCELL35:IMUX.IMUX21.DELAY |
| PIPERX0PHYSTATUS | input | TCELL34:IMUX.IMUX11.DELAY |
| PIPERX0POLARITY | output | TCELL31:OUT18.TMIN |
| PIPERX0STATUS0 | input | TCELL34:IMUX.IMUX23.DELAY |
| PIPERX0STATUS1 | input | TCELL34:IMUX.IMUX19.DELAY |
| PIPERX0STATUS2 | input | TCELL34:IMUX.IMUX21.DELAY |
| PIPERX0VALID | input | TCELL35:IMUX.IMUX19.DELAY |
| PIPERX1CHANISALIGNED | input | TCELL23:IMUX.IMUX21.DELAY |
| PIPERX1CHARISK0 | input | TCELL23:IMUX.IMUX23.DELAY |
| PIPERX1CHARISK1 | input | TCELL22:IMUX.IMUX1.DELAY |
| PIPERX1DATA0 | input | TCELL20:IMUX.IMUX3.DELAY |
| PIPERX1DATA1 | input | TCELL20:IMUX.IMUX5.DELAY |
| PIPERX1DATA10 | input | TCELL21:IMUX.IMUX7.DELAY |
| PIPERX1DATA11 | input | TCELL21:IMUX.IMUX15.DELAY |
| PIPERX1DATA12 | input | TCELL22:IMUX.IMUX5.DELAY |
| PIPERX1DATA13 | input | TCELL22:IMUX.IMUX7.DELAY |
| PIPERX1DATA14 | input | TCELL22:IMUX.IMUX11.DELAY |
| PIPERX1DATA15 | input | TCELL22:IMUX.IMUX9.DELAY |
| PIPERX1DATA2 | input | TCELL20:IMUX.IMUX15.DELAY |
| PIPERX1DATA3 | input | TCELL20:IMUX.IMUX19.DELAY |
| PIPERX1DATA4 | input | TCELL20:IMUX.IMUX1.DELAY |
| PIPERX1DATA5 | input | TCELL20:IMUX.IMUX9.DELAY |
| PIPERX1DATA6 | input | TCELL21:IMUX.IMUX1.DELAY |
| PIPERX1DATA7 | input | TCELL21:IMUX.IMUX9.DELAY |
| PIPERX1DATA8 | input | TCELL21:IMUX.IMUX3.DELAY |
| PIPERX1DATA9 | input | TCELL21:IMUX.IMUX5.DELAY |
| PIPERX1ELECIDLE | input | TCELL25:IMUX.IMUX21.DELAY |
| PIPERX1PHYSTATUS | input | TCELL24:IMUX.IMUX11.DELAY |
| PIPERX1POLARITY | output | TCELL21:OUT18.TMIN |
| PIPERX1STATUS0 | input | TCELL24:IMUX.IMUX23.DELAY |
| PIPERX1STATUS1 | input | TCELL24:IMUX.IMUX19.DELAY |
| PIPERX1STATUS2 | input | TCELL24:IMUX.IMUX21.DELAY |
| PIPERX1VALID | input | TCELL25:IMUX.IMUX19.DELAY |
| PIPERX2CHANISALIGNED | input | TCELL13:IMUX.IMUX21.DELAY |
| PIPERX2CHARISK0 | input | TCELL13:IMUX.IMUX23.DELAY |
| PIPERX2CHARISK1 | input | TCELL12:IMUX.IMUX1.DELAY |
| PIPERX2DATA0 | input | TCELL10:IMUX.IMUX3.DELAY |
| PIPERX2DATA1 | input | TCELL10:IMUX.IMUX5.DELAY |
| PIPERX2DATA10 | input | TCELL11:IMUX.IMUX7.DELAY |
| PIPERX2DATA11 | input | TCELL11:IMUX.IMUX15.DELAY |
| PIPERX2DATA12 | input | TCELL12:IMUX.IMUX5.DELAY |
| PIPERX2DATA13 | input | TCELL12:IMUX.IMUX7.DELAY |
| PIPERX2DATA14 | input | TCELL12:IMUX.IMUX11.DELAY |
| PIPERX2DATA15 | input | TCELL12:IMUX.IMUX9.DELAY |
| PIPERX2DATA2 | input | TCELL10:IMUX.IMUX15.DELAY |
| PIPERX2DATA3 | input | TCELL10:IMUX.IMUX19.DELAY |
| PIPERX2DATA4 | input | TCELL10:IMUX.IMUX1.DELAY |
| PIPERX2DATA5 | input | TCELL10:IMUX.IMUX9.DELAY |
| PIPERX2DATA6 | input | TCELL11:IMUX.IMUX1.DELAY |
| PIPERX2DATA7 | input | TCELL11:IMUX.IMUX9.DELAY |
| PIPERX2DATA8 | input | TCELL11:IMUX.IMUX3.DELAY |
| PIPERX2DATA9 | input | TCELL11:IMUX.IMUX5.DELAY |
| PIPERX2ELECIDLE | input | TCELL15:IMUX.IMUX21.DELAY |
| PIPERX2PHYSTATUS | input | TCELL14:IMUX.IMUX11.DELAY |
| PIPERX2POLARITY | output | TCELL11:OUT18.TMIN |
| PIPERX2STATUS0 | input | TCELL14:IMUX.IMUX23.DELAY |
| PIPERX2STATUS1 | input | TCELL14:IMUX.IMUX19.DELAY |
| PIPERX2STATUS2 | input | TCELL14:IMUX.IMUX21.DELAY |
| PIPERX2VALID | input | TCELL15:IMUX.IMUX19.DELAY |
| PIPERX3CHANISALIGNED | input | TCELL3:IMUX.IMUX21.DELAY |
| PIPERX3CHARISK0 | input | TCELL3:IMUX.IMUX23.DELAY |
| PIPERX3CHARISK1 | input | TCELL2:IMUX.IMUX1.DELAY |
| PIPERX3DATA0 | input | TCELL0:IMUX.IMUX3.DELAY |
| PIPERX3DATA1 | input | TCELL0:IMUX.IMUX5.DELAY |
| PIPERX3DATA10 | input | TCELL1:IMUX.IMUX7.DELAY |
| PIPERX3DATA11 | input | TCELL1:IMUX.IMUX15.DELAY |
| PIPERX3DATA12 | input | TCELL2:IMUX.IMUX5.DELAY |
| PIPERX3DATA13 | input | TCELL2:IMUX.IMUX7.DELAY |
| PIPERX3DATA14 | input | TCELL2:IMUX.IMUX11.DELAY |
| PIPERX3DATA15 | input | TCELL2:IMUX.IMUX9.DELAY |
| PIPERX3DATA2 | input | TCELL0:IMUX.IMUX15.DELAY |
| PIPERX3DATA3 | input | TCELL0:IMUX.IMUX19.DELAY |
| PIPERX3DATA4 | input | TCELL0:IMUX.IMUX1.DELAY |
| PIPERX3DATA5 | input | TCELL0:IMUX.IMUX9.DELAY |
| PIPERX3DATA6 | input | TCELL1:IMUX.IMUX1.DELAY |
| PIPERX3DATA7 | input | TCELL1:IMUX.IMUX9.DELAY |
| PIPERX3DATA8 | input | TCELL1:IMUX.IMUX3.DELAY |
| PIPERX3DATA9 | input | TCELL1:IMUX.IMUX5.DELAY |
| PIPERX3ELECIDLE | input | TCELL5:IMUX.IMUX21.DELAY |
| PIPERX3PHYSTATUS | input | TCELL4:IMUX.IMUX11.DELAY |
| PIPERX3POLARITY | output | TCELL1:OUT18.TMIN |
| PIPERX3STATUS0 | input | TCELL4:IMUX.IMUX23.DELAY |
| PIPERX3STATUS1 | input | TCELL4:IMUX.IMUX19.DELAY |
| PIPERX3STATUS2 | input | TCELL4:IMUX.IMUX21.DELAY |
| PIPERX3VALID | input | TCELL5:IMUX.IMUX19.DELAY |
| PIPERX4CHANISALIGNED | input | TCELL33:IMUX.IMUX1.DELAY |
| PIPERX4CHARISK0 | input | TCELL33:IMUX.IMUX15.DELAY |
| PIPERX4CHARISK1 | input | TCELL32:IMUX.IMUX17.DELAY |
| PIPERX4DATA0 | input | TCELL30:IMUX.IMUX11.DELAY |
| PIPERX4DATA1 | input | TCELL30:IMUX.IMUX13.DELAY |
| PIPERX4DATA10 | input | TCELL31:IMUX.IMUX19.DELAY |
| PIPERX4DATA11 | input | TCELL31:IMUX.IMUX23.DELAY |
| PIPERX4DATA12 | input | TCELL32:IMUX.IMUX13.DELAY |
| PIPERX4DATA13 | input | TCELL32:IMUX.IMUX3.DELAY |
| PIPERX4DATA14 | input | TCELL32:IMUX.IMUX15.DELAY |
| PIPERX4DATA15 | input | TCELL32:IMUX.IMUX21.DELAY |
| PIPERX4DATA2 | input | TCELL30:IMUX.IMUX7.DELAY |
| PIPERX4DATA3 | input | TCELL30:IMUX.IMUX23.DELAY |
| PIPERX4DATA4 | input | TCELL30:IMUX.IMUX17.DELAY |
| PIPERX4DATA5 | input | TCELL30:IMUX.IMUX21.DELAY |
| PIPERX4DATA6 | input | TCELL31:IMUX.IMUX17.DELAY |
| PIPERX4DATA7 | input | TCELL31:IMUX.IMUX21.DELAY |
| PIPERX4DATA8 | input | TCELL31:IMUX.IMUX11.DELAY |
| PIPERX4DATA9 | input | TCELL31:IMUX.IMUX13.DELAY |
| PIPERX4ELECIDLE | input | TCELL35:IMUX.IMUX5.DELAY |
| PIPERX4PHYSTATUS | input | TCELL34:IMUX.IMUX15.DELAY |
| PIPERX4POLARITY | output | TCELL31:OUT22.TMIN |
| PIPERX4STATUS0 | input | TCELL34:IMUX.IMUX3.DELAY |
| PIPERX4STATUS1 | input | TCELL34:IMUX.IMUX7.DELAY |
| PIPERX4STATUS2 | input | TCELL34:IMUX.IMUX1.DELAY |
| PIPERX4VALID | input | TCELL35:IMUX.IMUX11.DELAY |
| PIPERX5CHANISALIGNED | input | TCELL23:IMUX.IMUX1.DELAY |
| PIPERX5CHARISK0 | input | TCELL23:IMUX.IMUX15.DELAY |
| PIPERX5CHARISK1 | input | TCELL22:IMUX.IMUX17.DELAY |
| PIPERX5DATA0 | input | TCELL20:IMUX.IMUX11.DELAY |
| PIPERX5DATA1 | input | TCELL20:IMUX.IMUX13.DELAY |
| PIPERX5DATA10 | input | TCELL21:IMUX.IMUX19.DELAY |
| PIPERX5DATA11 | input | TCELL21:IMUX.IMUX23.DELAY |
| PIPERX5DATA12 | input | TCELL22:IMUX.IMUX13.DELAY |
| PIPERX5DATA13 | input | TCELL22:IMUX.IMUX3.DELAY |
| PIPERX5DATA14 | input | TCELL22:IMUX.IMUX15.DELAY |
| PIPERX5DATA15 | input | TCELL22:IMUX.IMUX21.DELAY |
| PIPERX5DATA2 | input | TCELL20:IMUX.IMUX7.DELAY |
| PIPERX5DATA3 | input | TCELL20:IMUX.IMUX23.DELAY |
| PIPERX5DATA4 | input | TCELL20:IMUX.IMUX17.DELAY |
| PIPERX5DATA5 | input | TCELL20:IMUX.IMUX21.DELAY |
| PIPERX5DATA6 | input | TCELL21:IMUX.IMUX17.DELAY |
| PIPERX5DATA7 | input | TCELL21:IMUX.IMUX21.DELAY |
| PIPERX5DATA8 | input | TCELL21:IMUX.IMUX11.DELAY |
| PIPERX5DATA9 | input | TCELL21:IMUX.IMUX13.DELAY |
| PIPERX5ELECIDLE | input | TCELL25:IMUX.IMUX5.DELAY |
| PIPERX5PHYSTATUS | input | TCELL24:IMUX.IMUX15.DELAY |
| PIPERX5POLARITY | output | TCELL21:OUT22.TMIN |
| PIPERX5STATUS0 | input | TCELL24:IMUX.IMUX3.DELAY |
| PIPERX5STATUS1 | input | TCELL24:IMUX.IMUX7.DELAY |
| PIPERX5STATUS2 | input | TCELL24:IMUX.IMUX1.DELAY |
| PIPERX5VALID | input | TCELL25:IMUX.IMUX11.DELAY |
| PIPERX6CHANISALIGNED | input | TCELL13:IMUX.IMUX1.DELAY |
| PIPERX6CHARISK0 | input | TCELL13:IMUX.IMUX15.DELAY |
| PIPERX6CHARISK1 | input | TCELL12:IMUX.IMUX17.DELAY |
| PIPERX6DATA0 | input | TCELL10:IMUX.IMUX11.DELAY |
| PIPERX6DATA1 | input | TCELL10:IMUX.IMUX13.DELAY |
| PIPERX6DATA10 | input | TCELL11:IMUX.IMUX19.DELAY |
| PIPERX6DATA11 | input | TCELL11:IMUX.IMUX23.DELAY |
| PIPERX6DATA12 | input | TCELL12:IMUX.IMUX13.DELAY |
| PIPERX6DATA13 | input | TCELL12:IMUX.IMUX3.DELAY |
| PIPERX6DATA14 | input | TCELL12:IMUX.IMUX15.DELAY |
| PIPERX6DATA15 | input | TCELL12:IMUX.IMUX21.DELAY |
| PIPERX6DATA2 | input | TCELL10:IMUX.IMUX7.DELAY |
| PIPERX6DATA3 | input | TCELL10:IMUX.IMUX23.DELAY |
| PIPERX6DATA4 | input | TCELL10:IMUX.IMUX17.DELAY |
| PIPERX6DATA5 | input | TCELL10:IMUX.IMUX21.DELAY |
| PIPERX6DATA6 | input | TCELL11:IMUX.IMUX17.DELAY |
| PIPERX6DATA7 | input | TCELL11:IMUX.IMUX21.DELAY |
| PIPERX6DATA8 | input | TCELL11:IMUX.IMUX11.DELAY |
| PIPERX6DATA9 | input | TCELL11:IMUX.IMUX13.DELAY |
| PIPERX6ELECIDLE | input | TCELL15:IMUX.IMUX5.DELAY |
| PIPERX6PHYSTATUS | input | TCELL14:IMUX.IMUX15.DELAY |
| PIPERX6POLARITY | output | TCELL11:OUT22.TMIN |
| PIPERX6STATUS0 | input | TCELL14:IMUX.IMUX3.DELAY |
| PIPERX6STATUS1 | input | TCELL14:IMUX.IMUX7.DELAY |
| PIPERX6STATUS2 | input | TCELL14:IMUX.IMUX1.DELAY |
| PIPERX6VALID | input | TCELL15:IMUX.IMUX11.DELAY |
| PIPERX7CHANISALIGNED | input | TCELL3:IMUX.IMUX1.DELAY |
| PIPERX7CHARISK0 | input | TCELL3:IMUX.IMUX15.DELAY |
| PIPERX7CHARISK1 | input | TCELL2:IMUX.IMUX17.DELAY |
| PIPERX7DATA0 | input | TCELL0:IMUX.IMUX11.DELAY |
| PIPERX7DATA1 | input | TCELL0:IMUX.IMUX13.DELAY |
| PIPERX7DATA10 | input | TCELL1:IMUX.IMUX19.DELAY |
| PIPERX7DATA11 | input | TCELL1:IMUX.IMUX23.DELAY |
| PIPERX7DATA12 | input | TCELL2:IMUX.IMUX13.DELAY |
| PIPERX7DATA13 | input | TCELL2:IMUX.IMUX3.DELAY |
| PIPERX7DATA14 | input | TCELL2:IMUX.IMUX15.DELAY |
| PIPERX7DATA15 | input | TCELL2:IMUX.IMUX21.DELAY |
| PIPERX7DATA2 | input | TCELL0:IMUX.IMUX7.DELAY |
| PIPERX7DATA3 | input | TCELL0:IMUX.IMUX23.DELAY |
| PIPERX7DATA4 | input | TCELL0:IMUX.IMUX17.DELAY |
| PIPERX7DATA5 | input | TCELL0:IMUX.IMUX21.DELAY |
| PIPERX7DATA6 | input | TCELL1:IMUX.IMUX17.DELAY |
| PIPERX7DATA7 | input | TCELL1:IMUX.IMUX21.DELAY |
| PIPERX7DATA8 | input | TCELL1:IMUX.IMUX11.DELAY |
| PIPERX7DATA9 | input | TCELL1:IMUX.IMUX13.DELAY |
| PIPERX7ELECIDLE | input | TCELL5:IMUX.IMUX5.DELAY |
| PIPERX7PHYSTATUS | input | TCELL4:IMUX.IMUX15.DELAY |
| PIPERX7POLARITY | output | TCELL1:OUT22.TMIN |
| PIPERX7STATUS0 | input | TCELL4:IMUX.IMUX3.DELAY |
| PIPERX7STATUS1 | input | TCELL4:IMUX.IMUX7.DELAY |
| PIPERX7STATUS2 | input | TCELL4:IMUX.IMUX1.DELAY |
| PIPERX7VALID | input | TCELL5:IMUX.IMUX11.DELAY |
| PIPETX0CHARISK0 | output | TCELL35:OUT18.TMIN |
| PIPETX0CHARISK1 | output | TCELL35:OUT23.TMIN |
| PIPETX0COMPLIANCE | output | TCELL35:OUT16.TMIN |
| PIPETX0DATA0 | output | TCELL38:OUT16.TMIN |
| PIPETX0DATA1 | output | TCELL38:OUT21.TMIN |
| PIPETX0DATA10 | output | TCELL37:OUT21.TMIN |
| PIPETX0DATA11 | output | TCELL37:OUT1.TMIN |
| PIPETX0DATA12 | output | TCELL36:OUT16.TMIN |
| PIPETX0DATA13 | output | TCELL36:OUT6.TMIN |
| PIPETX0DATA14 | output | TCELL36:OUT23.TMIN |
| PIPETX0DATA15 | output | TCELL36:OUT21.TMIN |
| PIPETX0DATA2 | output | TCELL38:OUT23.TMIN |
| PIPETX0DATA3 | output | TCELL38:OUT1.TMIN |
| PIPETX0DATA4 | output | TCELL38:OUT6.TMIN |
| PIPETX0DATA5 | output | TCELL38:OUT18.TMIN |
| PIPETX0DATA6 | output | TCELL37:OUT18.TMIN |
| PIPETX0DATA7 | output | TCELL37:OUT16.TMIN |
| PIPETX0DATA8 | output | TCELL37:OUT6.TMIN |
| PIPETX0DATA9 | output | TCELL37:OUT23.TMIN |
| PIPETX0ELECIDLE | output | TCELL34:OUT1.TMIN |
| PIPETX0POWERDOWN0 | output | TCELL34:OUT21.TMIN |
| PIPETX0POWERDOWN1 | output | TCELL34:OUT23.TMIN |
| PIPETX1CHARISK0 | output | TCELL25:OUT18.TMIN |
| PIPETX1CHARISK1 | output | TCELL25:OUT23.TMIN |
| PIPETX1COMPLIANCE | output | TCELL25:OUT16.TMIN |
| PIPETX1DATA0 | output | TCELL28:OUT16.TMIN |
| PIPETX1DATA1 | output | TCELL28:OUT21.TMIN |
| PIPETX1DATA10 | output | TCELL27:OUT21.TMIN |
| PIPETX1DATA11 | output | TCELL27:OUT1.TMIN |
| PIPETX1DATA12 | output | TCELL26:OUT16.TMIN |
| PIPETX1DATA13 | output | TCELL26:OUT6.TMIN |
| PIPETX1DATA14 | output | TCELL26:OUT23.TMIN |
| PIPETX1DATA15 | output | TCELL26:OUT21.TMIN |
| PIPETX1DATA2 | output | TCELL28:OUT23.TMIN |
| PIPETX1DATA3 | output | TCELL28:OUT1.TMIN |
| PIPETX1DATA4 | output | TCELL28:OUT6.TMIN |
| PIPETX1DATA5 | output | TCELL28:OUT18.TMIN |
| PIPETX1DATA6 | output | TCELL27:OUT18.TMIN |
| PIPETX1DATA7 | output | TCELL27:OUT16.TMIN |
| PIPETX1DATA8 | output | TCELL27:OUT6.TMIN |
| PIPETX1DATA9 | output | TCELL27:OUT23.TMIN |
| PIPETX1ELECIDLE | output | TCELL24:OUT1.TMIN |
| PIPETX1POWERDOWN0 | output | TCELL24:OUT21.TMIN |
| PIPETX1POWERDOWN1 | output | TCELL24:OUT23.TMIN |
| PIPETX2CHARISK0 | output | TCELL15:OUT18.TMIN |
| PIPETX2CHARISK1 | output | TCELL15:OUT23.TMIN |
| PIPETX2COMPLIANCE | output | TCELL15:OUT16.TMIN |
| PIPETX2DATA0 | output | TCELL18:OUT16.TMIN |
| PIPETX2DATA1 | output | TCELL18:OUT21.TMIN |
| PIPETX2DATA10 | output | TCELL17:OUT21.TMIN |
| PIPETX2DATA11 | output | TCELL17:OUT1.TMIN |
| PIPETX2DATA12 | output | TCELL16:OUT16.TMIN |
| PIPETX2DATA13 | output | TCELL16:OUT6.TMIN |
| PIPETX2DATA14 | output | TCELL16:OUT23.TMIN |
| PIPETX2DATA15 | output | TCELL16:OUT21.TMIN |
| PIPETX2DATA2 | output | TCELL18:OUT23.TMIN |
| PIPETX2DATA3 | output | TCELL18:OUT1.TMIN |
| PIPETX2DATA4 | output | TCELL18:OUT6.TMIN |
| PIPETX2DATA5 | output | TCELL18:OUT18.TMIN |
| PIPETX2DATA6 | output | TCELL17:OUT18.TMIN |
| PIPETX2DATA7 | output | TCELL17:OUT16.TMIN |
| PIPETX2DATA8 | output | TCELL17:OUT6.TMIN |
| PIPETX2DATA9 | output | TCELL17:OUT23.TMIN |
| PIPETX2ELECIDLE | output | TCELL14:OUT1.TMIN |
| PIPETX2POWERDOWN0 | output | TCELL14:OUT21.TMIN |
| PIPETX2POWERDOWN1 | output | TCELL14:OUT23.TMIN |
| PIPETX3CHARISK0 | output | TCELL5:OUT18.TMIN |
| PIPETX3CHARISK1 | output | TCELL5:OUT23.TMIN |
| PIPETX3COMPLIANCE | output | TCELL5:OUT16.TMIN |
| PIPETX3DATA0 | output | TCELL8:OUT16.TMIN |
| PIPETX3DATA1 | output | TCELL8:OUT21.TMIN |
| PIPETX3DATA10 | output | TCELL7:OUT21.TMIN |
| PIPETX3DATA11 | output | TCELL7:OUT1.TMIN |
| PIPETX3DATA12 | output | TCELL6:OUT16.TMIN |
| PIPETX3DATA13 | output | TCELL6:OUT6.TMIN |
| PIPETX3DATA14 | output | TCELL6:OUT23.TMIN |
| PIPETX3DATA15 | output | TCELL6:OUT21.TMIN |
| PIPETX3DATA2 | output | TCELL8:OUT23.TMIN |
| PIPETX3DATA3 | output | TCELL8:OUT1.TMIN |
| PIPETX3DATA4 | output | TCELL8:OUT6.TMIN |
| PIPETX3DATA5 | output | TCELL8:OUT18.TMIN |
| PIPETX3DATA6 | output | TCELL7:OUT18.TMIN |
| PIPETX3DATA7 | output | TCELL7:OUT16.TMIN |
| PIPETX3DATA8 | output | TCELL7:OUT6.TMIN |
| PIPETX3DATA9 | output | TCELL7:OUT23.TMIN |
| PIPETX3ELECIDLE | output | TCELL4:OUT1.TMIN |
| PIPETX3POWERDOWN0 | output | TCELL4:OUT21.TMIN |
| PIPETX3POWERDOWN1 | output | TCELL4:OUT23.TMIN |
| PIPETX4CHARISK0 | output | TCELL35:OUT22.TMIN |
| PIPETX4CHARISK1 | output | TCELL35:OUT19.TMIN |
| PIPETX4COMPLIANCE | output | TCELL35:OUT20.TMIN |
| PIPETX4DATA0 | output | TCELL38:OUT20.TMIN |
| PIPETX4DATA1 | output | TCELL38:OUT17.TMIN |
| PIPETX4DATA10 | output | TCELL37:OUT17.TMIN |
| PIPETX4DATA11 | output | TCELL37:OUT5.TMIN |
| PIPETX4DATA12 | output | TCELL36:OUT20.TMIN |
| PIPETX4DATA13 | output | TCELL36:OUT2.TMIN |
| PIPETX4DATA14 | output | TCELL36:OUT19.TMIN |
| PIPETX4DATA15 | output | TCELL36:OUT17.TMIN |
| PIPETX4DATA2 | output | TCELL38:OUT19.TMIN |
| PIPETX4DATA3 | output | TCELL38:OUT5.TMIN |
| PIPETX4DATA4 | output | TCELL38:OUT2.TMIN |
| PIPETX4DATA5 | output | TCELL38:OUT22.TMIN |
| PIPETX4DATA6 | output | TCELL37:OUT22.TMIN |
| PIPETX4DATA7 | output | TCELL37:OUT20.TMIN |
| PIPETX4DATA8 | output | TCELL37:OUT2.TMIN |
| PIPETX4DATA9 | output | TCELL37:OUT19.TMIN |
| PIPETX4ELECIDLE | output | TCELL34:OUT5.TMIN |
| PIPETX4POWERDOWN0 | output | TCELL34:OUT17.TMIN |
| PIPETX4POWERDOWN1 | output | TCELL34:OUT19.TMIN |
| PIPETX5CHARISK0 | output | TCELL25:OUT22.TMIN |
| PIPETX5CHARISK1 | output | TCELL25:OUT19.TMIN |
| PIPETX5COMPLIANCE | output | TCELL25:OUT20.TMIN |
| PIPETX5DATA0 | output | TCELL28:OUT20.TMIN |
| PIPETX5DATA1 | output | TCELL28:OUT17.TMIN |
| PIPETX5DATA10 | output | TCELL27:OUT17.TMIN |
| PIPETX5DATA11 | output | TCELL27:OUT5.TMIN |
| PIPETX5DATA12 | output | TCELL26:OUT20.TMIN |
| PIPETX5DATA13 | output | TCELL26:OUT2.TMIN |
| PIPETX5DATA14 | output | TCELL26:OUT19.TMIN |
| PIPETX5DATA15 | output | TCELL26:OUT17.TMIN |
| PIPETX5DATA2 | output | TCELL28:OUT19.TMIN |
| PIPETX5DATA3 | output | TCELL28:OUT5.TMIN |
| PIPETX5DATA4 | output | TCELL28:OUT2.TMIN |
| PIPETX5DATA5 | output | TCELL28:OUT22.TMIN |
| PIPETX5DATA6 | output | TCELL27:OUT22.TMIN |
| PIPETX5DATA7 | output | TCELL27:OUT20.TMIN |
| PIPETX5DATA8 | output | TCELL27:OUT2.TMIN |
| PIPETX5DATA9 | output | TCELL27:OUT19.TMIN |
| PIPETX5ELECIDLE | output | TCELL24:OUT5.TMIN |
| PIPETX5POWERDOWN0 | output | TCELL24:OUT17.TMIN |
| PIPETX5POWERDOWN1 | output | TCELL24:OUT19.TMIN |
| PIPETX6CHARISK0 | output | TCELL15:OUT22.TMIN |
| PIPETX6CHARISK1 | output | TCELL15:OUT19.TMIN |
| PIPETX6COMPLIANCE | output | TCELL15:OUT20.TMIN |
| PIPETX6DATA0 | output | TCELL18:OUT20.TMIN |
| PIPETX6DATA1 | output | TCELL18:OUT17.TMIN |
| PIPETX6DATA10 | output | TCELL17:OUT17.TMIN |
| PIPETX6DATA11 | output | TCELL17:OUT5.TMIN |
| PIPETX6DATA12 | output | TCELL16:OUT20.TMIN |
| PIPETX6DATA13 | output | TCELL16:OUT2.TMIN |
| PIPETX6DATA14 | output | TCELL16:OUT19.TMIN |
| PIPETX6DATA15 | output | TCELL16:OUT17.TMIN |
| PIPETX6DATA2 | output | TCELL18:OUT19.TMIN |
| PIPETX6DATA3 | output | TCELL18:OUT5.TMIN |
| PIPETX6DATA4 | output | TCELL18:OUT2.TMIN |
| PIPETX6DATA5 | output | TCELL18:OUT22.TMIN |
| PIPETX6DATA6 | output | TCELL17:OUT22.TMIN |
| PIPETX6DATA7 | output | TCELL17:OUT20.TMIN |
| PIPETX6DATA8 | output | TCELL17:OUT2.TMIN |
| PIPETX6DATA9 | output | TCELL17:OUT19.TMIN |
| PIPETX6ELECIDLE | output | TCELL14:OUT5.TMIN |
| PIPETX6POWERDOWN0 | output | TCELL14:OUT17.TMIN |
| PIPETX6POWERDOWN1 | output | TCELL14:OUT19.TMIN |
| PIPETX7CHARISK0 | output | TCELL5:OUT22.TMIN |
| PIPETX7CHARISK1 | output | TCELL5:OUT19.TMIN |
| PIPETX7COMPLIANCE | output | TCELL5:OUT20.TMIN |
| PIPETX7DATA0 | output | TCELL8:OUT20.TMIN |
| PIPETX7DATA1 | output | TCELL8:OUT17.TMIN |
| PIPETX7DATA10 | output | TCELL7:OUT17.TMIN |
| PIPETX7DATA11 | output | TCELL7:OUT5.TMIN |
| PIPETX7DATA12 | output | TCELL6:OUT20.TMIN |
| PIPETX7DATA13 | output | TCELL6:OUT2.TMIN |
| PIPETX7DATA14 | output | TCELL6:OUT19.TMIN |
| PIPETX7DATA15 | output | TCELL6:OUT17.TMIN |
| PIPETX7DATA2 | output | TCELL8:OUT19.TMIN |
| PIPETX7DATA3 | output | TCELL8:OUT5.TMIN |
| PIPETX7DATA4 | output | TCELL8:OUT2.TMIN |
| PIPETX7DATA5 | output | TCELL8:OUT22.TMIN |
| PIPETX7DATA6 | output | TCELL7:OUT22.TMIN |
| PIPETX7DATA7 | output | TCELL7:OUT20.TMIN |
| PIPETX7DATA8 | output | TCELL7:OUT2.TMIN |
| PIPETX7DATA9 | output | TCELL7:OUT19.TMIN |
| PIPETX7ELECIDLE | output | TCELL4:OUT5.TMIN |
| PIPETX7POWERDOWN0 | output | TCELL4:OUT17.TMIN |
| PIPETX7POWERDOWN1 | output | TCELL4:OUT19.TMIN |
| PIPETXDEEMPH | output | TCELL13:OUT16.TMIN |
| PIPETXMARGIN0 | output | TCELL0:OUT18.TMIN |
| PIPETXMARGIN1 | output | TCELL0:OUT16.TMIN |
| PIPETXMARGIN2 | output | TCELL0:OUT6.TMIN |
| PIPETXRATE | output | TCELL16:OUT18.TMIN |
| PIPETXRCVRDET | output | TCELL14:OUT15.TMIN |
| PIPETXRESET | output | TCELL16:OUT9.TMIN |
| PL2DIRECTEDLSTATE0 | input | TCELL28:IMUX.IMUX8.DELAY |
| PL2DIRECTEDLSTATE1 | input | TCELL28:IMUX.IMUX9.DELAY |
| PL2DIRECTEDLSTATE2 | input | TCELL28:IMUX.IMUX10.DELAY |
| PL2DIRECTEDLSTATE3 | input | TCELL28:IMUX.IMUX11.DELAY |
| PL2DIRECTEDLSTATE4 | input | TCELL29:IMUX.IMUX8.DELAY |
| PL2LINKUPN | output | TCELL0:OUT9.TMIN |
| PL2RECEIVERERRN | output | TCELL0:OUT10.TMIN |
| PL2RECOVERYN | output | TCELL2:OUT10.TMIN |
| PL2RXELECIDLE | output | TCELL2:OUT11.TMIN |
| PL2SUSPENDOK | output | TCELL2:OUT9.TMIN |
| PLDBGMODE0 | input | TCELL37:IMUX.IMUX21.DELAY |
| PLDBGMODE1 | input | TCELL38:IMUX.IMUX21.DELAY |
| PLDBGMODE2 | input | TCELL39:IMUX.IMUX21.DELAY |
| PLDBGVEC0 | output | TCELL36:OUT22.TMIN |
| PLDBGVEC1 | output | TCELL37:OUT15.TMIN |
| PLDBGVEC10 | output | TCELL16:OUT12.TMIN |
| PLDBGVEC11 | output | TCELL16:OUT13.TMIN |
| PLDBGVEC2 | output | TCELL38:OUT15.TMIN |
| PLDBGVEC3 | output | TCELL39:OUT19.TMIN |
| PLDBGVEC4 | output | TCELL39:OUT20.TMIN |
| PLDBGVEC5 | output | TCELL19:OUT22.TMIN |
| PLDBGVEC6 | output | TCELL18:OUT12.TMIN |
| PLDBGVEC7 | output | TCELL18:OUT13.TMIN |
| PLDBGVEC8 | output | TCELL17:OUT11.TMIN |
| PLDBGVEC9 | output | TCELL17:OUT12.TMIN |
| PLDIRECTEDLINKAUTON | input | TCELL23:IMUX.IMUX0.DELAY |
| PLDIRECTEDLINKCHANGE0 | input | TCELL20:IMUX.IMUX0.DELAY |
| PLDIRECTEDLINKCHANGE1 | input | TCELL21:IMUX.IMUX0.DELAY |
| PLDIRECTEDLINKSPEED | input | TCELL22:IMUX.IMUX4.DELAY |
| PLDIRECTEDLINKWIDTH0 | input | TCELL22:IMUX.IMUX0.DELAY |
| PLDIRECTEDLINKWIDTH1 | input | TCELL22:IMUX.IMUX2.DELAY |
| PLDOWNSTREAMDEEMPHSOURCE | input | TCELL23:IMUX.IMUX3.DELAY |
| PLINITIALLINKWIDTH0 | output | TCELL22:OUT0.TMIN |
| PLINITIALLINKWIDTH1 | output | TCELL22:OUT1.TMIN |
| PLINITIALLINKWIDTH2 | output | TCELL22:OUT2.TMIN |
| PLLANEREVERSALMODE0 | output | TCELL20:OUT9.TMIN |
| PLLANEREVERSALMODE1 | output | TCELL20:OUT10.TMIN |
| PLLINKGEN2CAP | output | TCELL21:OUT2.TMIN |
| PLLINKPARTNERGEN2SUPPORTED | output | TCELL21:OUT3.TMIN |
| PLLINKUPCFGCAP | output | TCELL21:OUT1.TMIN |
| PLLTSSMSTATE0 | output | TCELL20:OUT3.TMIN |
| PLLTSSMSTATE1 | output | TCELL20:OUT4.TMIN |
| PLLTSSMSTATE2 | output | TCELL20:OUT5.TMIN |
| PLLTSSMSTATE3 | output | TCELL20:OUT6.TMIN |
| PLLTSSMSTATE4 | output | TCELL20:OUT7.TMIN |
| PLLTSSMSTATE5 | output | TCELL20:OUT8.TMIN |
| PLPHYLNKUPN | output | TCELL20:OUT11.TMIN |
| PLRECEIVEDHOTRST | output | TCELL22:OUT13.TMIN |
| PLRSTN | input | TCELL23:IMUX.CTRL0 |
| PLRXPMSTATE0 | output | TCELL20:OUT15.TMIN |
| PLRXPMSTATE1 | output | TCELL21:OUT0.TMIN |
| PLSELLNKRATE | output | TCELL20:OUT0.TMIN |
| PLSELLNKWIDTH0 | output | TCELL20:OUT1.TMIN |
| PLSELLNKWIDTH1 | output | TCELL20:OUT2.TMIN |
| PLTRANSMITHOTRST | input | TCELL14:IMUX.IMUX13.DELAY |
| PLTXPMSTATE0 | output | TCELL20:OUT12.TMIN |
| PLTXPMSTATE1 | output | TCELL20:OUT13.TMIN |
| PLTXPMSTATE2 | output | TCELL20:OUT14.TMIN |
| PLUPSTREAMPREFERDEEMPH | input | TCELL23:IMUX.IMUX2.DELAY |
| PMVDIVIDE0 | input | TCELL15:IMUX.IMUX9.DELAY |
| PMVDIVIDE1 | input | TCELL14:IMUX.IMUX12.DELAY |
| PMVENABLEN | input | TCELL19:IMUX.IMUX8.DELAY |
| PMVOUT | output | TCELL21:OUT15.TMIN |
| PMVSELECT0 | input | TCELL18:IMUX.IMUX8.DELAY |
| PMVSELECT1 | input | TCELL17:IMUX.IMUX8.DELAY |
| PMVSELECT2 | input | TCELL16:IMUX.IMUX8.DELAY |
| RECEIVEDFUNCLVLRSTN | output | TCELL22:OUT14.TMIN |
| SCANENABLEN | input | TCELL31:IMUX.IMUX10.DELAY |
| SCANIN0 | input | TCELL32:IMUX.IMUX14.DELAY |
| SCANIN1 | input | TCELL33:IMUX.IMUX9.DELAY |
| SCANIN2 | input | TCELL34:IMUX.IMUX12.DELAY |
| SCANIN3 | input | TCELL35:IMUX.IMUX9.DELAY |
| SCANIN4 | input | TCELL36:IMUX.IMUX8.DELAY |
| SCANIN5 | input | TCELL37:IMUX.IMUX8.DELAY |
| SCANIN6 | input | TCELL38:IMUX.IMUX8.DELAY |
| SCANIN7 | input | TCELL39:IMUX.IMUX8.DELAY |
| SCANMODEN | input | TCELL30:IMUX.IMUX10.DELAY |
| SYSRSTN | input | TCELL20:IMUX.CTRL0 |
| TL2ASPMSUSPENDCREDITCHECKN | input | TCELL29:IMUX.IMUX11.DELAY |
| TL2ASPMSUSPENDCREDITCHECKOKN | output | TCELL1:OUT11.TMIN |
| TL2ASPMSUSPENDREQN | output | TCELL1:OUT10.TMIN |
| TL2PPMSUSPENDOKN | output | TCELL1:OUT9.TMIN |
| TL2PPMSUSPENDREQN | input | TCELL29:IMUX.IMUX10.DELAY |
| TLRSTN | input | TCELL22:IMUX.CTRL0 |
| TRNFCCPLD0 | output | TCELL0:OUT3.TMIN |
| TRNFCCPLD1 | output | TCELL20:OUT16.TMIN |
| TRNFCCPLD10 | output | TCELL22:OUT5.TMIN |
| TRNFCCPLD11 | output | TCELL22:OUT6.TMIN |
| TRNFCCPLD2 | output | TCELL20:OUT17.TMIN |
| TRNFCCPLD3 | output | TCELL20:OUT18.TMIN |
| TRNFCCPLD4 | output | TCELL20:OUT19.TMIN |
| TRNFCCPLD5 | output | TCELL21:OUT4.TMIN |
| TRNFCCPLD6 | output | TCELL21:OUT5.TMIN |
| TRNFCCPLD7 | output | TCELL21:OUT6.TMIN |
| TRNFCCPLD8 | output | TCELL21:OUT7.TMIN |
| TRNFCCPLD9 | output | TCELL22:OUT4.TMIN |
| TRNFCCPLH0 | output | TCELL2:OUT3.TMIN |
| TRNFCCPLH1 | output | TCELL1:OUT0.TMIN |
| TRNFCCPLH2 | output | TCELL1:OUT1.TMIN |
| TRNFCCPLH3 | output | TCELL1:OUT2.TMIN |
| TRNFCCPLH4 | output | TCELL1:OUT3.TMIN |
| TRNFCCPLH5 | output | TCELL0:OUT0.TMIN |
| TRNFCCPLH6 | output | TCELL0:OUT1.TMIN |
| TRNFCCPLH7 | output | TCELL0:OUT2.TMIN |
| TRNFCNPD0 | output | TCELL5:OUT3.TMIN |
| TRNFCNPD1 | output | TCELL4:OUT0.TMIN |
| TRNFCNPD10 | output | TCELL2:OUT1.TMIN |
| TRNFCNPD11 | output | TCELL2:OUT2.TMIN |
| TRNFCNPD2 | output | TCELL4:OUT2.TMIN |
| TRNFCNPD3 | output | TCELL4:OUT3.TMIN |
| TRNFCNPD4 | output | TCELL4:OUT4.TMIN |
| TRNFCNPD5 | output | TCELL3:OUT0.TMIN |
| TRNFCNPD6 | output | TCELL3:OUT1.TMIN |
| TRNFCNPD7 | output | TCELL3:OUT2.TMIN |
| TRNFCNPD8 | output | TCELL3:OUT3.TMIN |
| TRNFCNPD9 | output | TCELL2:OUT0.TMIN |
| TRNFCNPH0 | output | TCELL7:OUT7.TMIN |
| TRNFCNPH1 | output | TCELL6:OUT0.TMIN |
| TRNFCNPH2 | output | TCELL6:OUT1.TMIN |
| TRNFCNPH3 | output | TCELL6:OUT3.TMIN |
| TRNFCNPH4 | output | TCELL6:OUT4.TMIN |
| TRNFCNPH5 | output | TCELL5:OUT0.TMIN |
| TRNFCNPH6 | output | TCELL5:OUT1.TMIN |
| TRNFCNPH7 | output | TCELL5:OUT2.TMIN |
| TRNFCPD0 | output | TCELL10:OUT3.TMIN |
| TRNFCPD1 | output | TCELL9:OUT0.TMIN |
| TRNFCPD10 | output | TCELL7:OUT3.TMIN |
| TRNFCPD11 | output | TCELL7:OUT4.TMIN |
| TRNFCPD2 | output | TCELL9:OUT1.TMIN |
| TRNFCPD3 | output | TCELL9:OUT2.TMIN |
| TRNFCPD4 | output | TCELL9:OUT3.TMIN |
| TRNFCPD5 | output | TCELL8:OUT0.TMIN |
| TRNFCPD6 | output | TCELL8:OUT3.TMIN |
| TRNFCPD7 | output | TCELL8:OUT4.TMIN |
| TRNFCPD8 | output | TCELL8:OUT7.TMIN |
| TRNFCPD9 | output | TCELL7:OUT0.TMIN |
| TRNFCPH0 | output | TCELL12:OUT3.TMIN |
| TRNFCPH1 | output | TCELL11:OUT0.TMIN |
| TRNFCPH2 | output | TCELL11:OUT1.TMIN |
| TRNFCPH3 | output | TCELL11:OUT2.TMIN |
| TRNFCPH4 | output | TCELL11:OUT3.TMIN |
| TRNFCPH5 | output | TCELL10:OUT0.TMIN |
| TRNFCPH6 | output | TCELL10:OUT1.TMIN |
| TRNFCPH7 | output | TCELL10:OUT2.TMIN |
| TRNFCSEL0 | input | TCELL15:IMUX.IMUX1.DELAY |
| TRNFCSEL1 | input | TCELL15:IMUX.IMUX2.DELAY |
| TRNFCSEL2 | input | TCELL15:IMUX.IMUX3.DELAY |
| TRNLNKUPN | output | TCELL12:OUT2.TMIN |
| TRNRBARHITN0 | output | TCELL14:OUT4.TMIN |
| TRNRBARHITN1 | output | TCELL13:OUT0.TMIN |
| TRNRBARHITN2 | output | TCELL13:OUT1.TMIN |
| TRNRBARHITN3 | output | TCELL13:OUT2.TMIN |
| TRNRBARHITN4 | output | TCELL13:OUT3.TMIN |
| TRNRBARHITN5 | output | TCELL12:OUT0.TMIN |
| TRNRBARHITN6 | output | TCELL12:OUT1.TMIN |
| TRNRD0 | output | TCELL25:OUT0.TMIN |
| TRNRD1 | output | TCELL25:OUT1.TMIN |
| TRNRD10 | output | TCELL28:OUT0.TMIN |
| TRNRD11 | output | TCELL28:OUT3.TMIN |
| TRNRD12 | output | TCELL29:OUT0.TMIN |
| TRNRD13 | output | TCELL29:OUT1.TMIN |
| TRNRD14 | output | TCELL29:OUT2.TMIN |
| TRNRD15 | output | TCELL29:OUT3.TMIN |
| TRNRD16 | output | TCELL30:OUT0.TMIN |
| TRNRD17 | output | TCELL30:OUT1.TMIN |
| TRNRD18 | output | TCELL30:OUT2.TMIN |
| TRNRD19 | output | TCELL30:OUT3.TMIN |
| TRNRD2 | output | TCELL25:OUT2.TMIN |
| TRNRD20 | output | TCELL31:OUT0.TMIN |
| TRNRD21 | output | TCELL31:OUT1.TMIN |
| TRNRD22 | output | TCELL31:OUT2.TMIN |
| TRNRD23 | output | TCELL31:OUT3.TMIN |
| TRNRD24 | output | TCELL32:OUT0.TMIN |
| TRNRD25 | output | TCELL32:OUT1.TMIN |
| TRNRD26 | output | TCELL32:OUT2.TMIN |
| TRNRD27 | output | TCELL32:OUT3.TMIN |
| TRNRD28 | output | TCELL33:OUT0.TMIN |
| TRNRD29 | output | TCELL33:OUT1.TMIN |
| TRNRD3 | output | TCELL25:OUT3.TMIN |
| TRNRD30 | output | TCELL33:OUT2.TMIN |
| TRNRD31 | output | TCELL33:OUT3.TMIN |
| TRNRD32 | output | TCELL34:OUT0.TMIN |
| TRNRD33 | output | TCELL34:OUT2.TMIN |
| TRNRD34 | output | TCELL34:OUT3.TMIN |
| TRNRD35 | output | TCELL34:OUT4.TMIN |
| TRNRD36 | output | TCELL35:OUT0.TMIN |
| TRNRD37 | output | TCELL35:OUT1.TMIN |
| TRNRD38 | output | TCELL35:OUT2.TMIN |
| TRNRD39 | output | TCELL35:OUT3.TMIN |
| TRNRD4 | output | TCELL26:OUT0.TMIN |
| TRNRD40 | output | TCELL36:OUT0.TMIN |
| TRNRD41 | output | TCELL36:OUT1.TMIN |
| TRNRD42 | output | TCELL36:OUT3.TMIN |
| TRNRD43 | output | TCELL36:OUT4.TMIN |
| TRNRD44 | output | TCELL37:OUT0.TMIN |
| TRNRD45 | output | TCELL37:OUT3.TMIN |
| TRNRD46 | output | TCELL38:OUT0.TMIN |
| TRNRD47 | output | TCELL38:OUT3.TMIN |
| TRNRD48 | output | TCELL39:OUT0.TMIN |
| TRNRD49 | output | TCELL39:OUT1.TMIN |
| TRNRD5 | output | TCELL26:OUT1.TMIN |
| TRNRD50 | output | TCELL39:OUT2.TMIN |
| TRNRD51 | output | TCELL39:OUT3.TMIN |
| TRNRD52 | output | TCELL19:OUT0.TMIN |
| TRNRD53 | output | TCELL19:OUT1.TMIN |
| TRNRD54 | output | TCELL19:OUT2.TMIN |
| TRNRD55 | output | TCELL19:OUT3.TMIN |
| TRNRD56 | output | TCELL18:OUT0.TMIN |
| TRNRD57 | output | TCELL18:OUT3.TMIN |
| TRNRD58 | output | TCELL17:OUT0.TMIN |
| TRNRD59 | output | TCELL17:OUT3.TMIN |
| TRNRD6 | output | TCELL26:OUT3.TMIN |
| TRNRD60 | output | TCELL16:OUT0.TMIN |
| TRNRD61 | output | TCELL16:OUT1.TMIN |
| TRNRD62 | output | TCELL16:OUT3.TMIN |
| TRNRD63 | output | TCELL16:OUT4.TMIN |
| TRNRD7 | output | TCELL26:OUT4.TMIN |
| TRNRD8 | output | TCELL27:OUT0.TMIN |
| TRNRD9 | output | TCELL27:OUT3.TMIN |
| TRNRDLLPDATA0 | output | TCELL13:OUT8.TMIN |
| TRNRDLLPDATA1 | output | TCELL13:OUT9.TMIN |
| TRNRDLLPDATA10 | output | TCELL11:OUT10.TMIN |
| TRNRDLLPDATA11 | output | TCELL11:OUT11.TMIN |
| TRNRDLLPDATA12 | output | TCELL10:OUT8.TMIN |
| TRNRDLLPDATA13 | output | TCELL10:OUT9.TMIN |
| TRNRDLLPDATA14 | output | TCELL10:OUT10.TMIN |
| TRNRDLLPDATA15 | output | TCELL10:OUT11.TMIN |
| TRNRDLLPDATA16 | output | TCELL9:OUT8.TMIN |
| TRNRDLLPDATA17 | output | TCELL9:OUT9.TMIN |
| TRNRDLLPDATA18 | output | TCELL9:OUT10.TMIN |
| TRNRDLLPDATA19 | output | TCELL9:OUT11.TMIN |
| TRNRDLLPDATA2 | output | TCELL13:OUT10.TMIN |
| TRNRDLLPDATA20 | output | TCELL6:OUT10.TMIN |
| TRNRDLLPDATA21 | output | TCELL6:OUT11.TMIN |
| TRNRDLLPDATA22 | output | TCELL5:OUT8.TMIN |
| TRNRDLLPDATA23 | output | TCELL5:OUT9.TMIN |
| TRNRDLLPDATA24 | output | TCELL5:OUT10.TMIN |
| TRNRDLLPDATA25 | output | TCELL5:OUT11.TMIN |
| TRNRDLLPDATA26 | output | TCELL4:OUT10.TMIN |
| TRNRDLLPDATA27 | output | TCELL4:OUT11.TMIN |
| TRNRDLLPDATA28 | output | TCELL4:OUT12.TMIN |
| TRNRDLLPDATA29 | output | TCELL4:OUT13.TMIN |
| TRNRDLLPDATA3 | output | TCELL13:OUT11.TMIN |
| TRNRDLLPDATA30 | output | TCELL3:OUT8.TMIN |
| TRNRDLLPDATA31 | output | TCELL3:OUT9.TMIN |
| TRNRDLLPDATA4 | output | TCELL12:OUT8.TMIN |
| TRNRDLLPDATA5 | output | TCELL12:OUT9.TMIN |
| TRNRDLLPDATA6 | output | TCELL12:OUT10.TMIN |
| TRNRDLLPDATA7 | output | TCELL12:OUT11.TMIN |
| TRNRDLLPDATA8 | output | TCELL11:OUT8.TMIN |
| TRNRDLLPDATA9 | output | TCELL11:OUT9.TMIN |
| TRNRDLLPSRCRDYN | output | TCELL3:OUT10.TMIN |
| TRNRDSTRDYN | input | TCELL16:IMUX.IMUX3.DELAY |
| TRNRECRCERRN | output | TCELL14:OUT2.TMIN |
| TRNREOFN | output | TCELL15:OUT2.TMIN |
| TRNRERRFWDN | output | TCELL14:OUT3.TMIN |
| TRNRNPOKN | input | TCELL15:IMUX.IMUX0.DELAY |
| TRNRREMN | output | TCELL15:OUT0.TMIN |
| TRNRSOFN | output | TCELL15:OUT1.TMIN |
| TRNRSRCDSCN | output | TCELL14:OUT0.TMIN |
| TRNRSRCRDYN | output | TCELL15:OUT3.TMIN |
| TRNTBUFAV0 | output | TCELL23:OUT1.TMIN |
| TRNTBUFAV1 | output | TCELL23:OUT2.TMIN |
| TRNTBUFAV2 | output | TCELL23:OUT3.TMIN |
| TRNTBUFAV3 | output | TCELL24:OUT0.TMIN |
| TRNTBUFAV4 | output | TCELL24:OUT2.TMIN |
| TRNTBUFAV5 | output | TCELL24:OUT3.TMIN |
| TRNTCFGGNTN | input | TCELL16:IMUX.IMUX2.DELAY |
| TRNTCFGREQN | output | TCELL24:OUT4.TMIN |
| TRNTD0 | input | TCELL23:IMUX.IMUX4.DELAY |
| TRNTD1 | input | TCELL24:IMUX.IMUX0.DELAY |
| TRNTD10 | input | TCELL26:IMUX.IMUX1.DELAY |
| TRNTD11 | input | TCELL26:IMUX.IMUX2.DELAY |
| TRNTD12 | input | TCELL26:IMUX.IMUX3.DELAY |
| TRNTD13 | input | TCELL27:IMUX.IMUX0.DELAY |
| TRNTD14 | input | TCELL27:IMUX.IMUX1.DELAY |
| TRNTD15 | input | TCELL27:IMUX.IMUX2.DELAY |
| TRNTD16 | input | TCELL27:IMUX.IMUX3.DELAY |
| TRNTD17 | input | TCELL28:IMUX.IMUX0.DELAY |
| TRNTD18 | input | TCELL28:IMUX.IMUX1.DELAY |
| TRNTD19 | input | TCELL28:IMUX.IMUX2.DELAY |
| TRNTD2 | input | TCELL24:IMUX.IMUX2.DELAY |
| TRNTD20 | input | TCELL28:IMUX.IMUX3.DELAY |
| TRNTD21 | input | TCELL29:IMUX.IMUX0.DELAY |
| TRNTD22 | input | TCELL29:IMUX.IMUX1.DELAY |
| TRNTD23 | input | TCELL29:IMUX.IMUX2.DELAY |
| TRNTD24 | input | TCELL29:IMUX.IMUX3.DELAY |
| TRNTD25 | input | TCELL30:IMUX.IMUX0.DELAY |
| TRNTD26 | input | TCELL31:IMUX.IMUX0.DELAY |
| TRNTD27 | input | TCELL32:IMUX.IMUX0.DELAY |
| TRNTD28 | input | TCELL32:IMUX.IMUX2.DELAY |
| TRNTD29 | input | TCELL32:IMUX.IMUX4.DELAY |
| TRNTD3 | input | TCELL24:IMUX.IMUX4.DELAY |
| TRNTD30 | input | TCELL33:IMUX.IMUX0.DELAY |
| TRNTD31 | input | TCELL33:IMUX.IMUX2.DELAY |
| TRNTD32 | input | TCELL33:IMUX.IMUX3.DELAY |
| TRNTD33 | input | TCELL33:IMUX.IMUX4.DELAY |
| TRNTD34 | input | TCELL34:IMUX.IMUX0.DELAY |
| TRNTD35 | input | TCELL34:IMUX.IMUX2.DELAY |
| TRNTD36 | input | TCELL34:IMUX.IMUX4.DELAY |
| TRNTD37 | input | TCELL34:IMUX.IMUX5.DELAY |
| TRNTD38 | input | TCELL35:IMUX.IMUX0.DELAY |
| TRNTD39 | input | TCELL35:IMUX.IMUX1.DELAY |
| TRNTD4 | input | TCELL24:IMUX.IMUX5.DELAY |
| TRNTD40 | input | TCELL35:IMUX.IMUX2.DELAY |
| TRNTD41 | input | TCELL35:IMUX.IMUX3.DELAY |
| TRNTD42 | input | TCELL36:IMUX.IMUX0.DELAY |
| TRNTD43 | input | TCELL36:IMUX.IMUX1.DELAY |
| TRNTD44 | input | TCELL36:IMUX.IMUX2.DELAY |
| TRNTD45 | input | TCELL36:IMUX.IMUX3.DELAY |
| TRNTD46 | input | TCELL37:IMUX.IMUX0.DELAY |
| TRNTD47 | input | TCELL37:IMUX.IMUX1.DELAY |
| TRNTD48 | input | TCELL37:IMUX.IMUX2.DELAY |
| TRNTD49 | input | TCELL37:IMUX.IMUX3.DELAY |
| TRNTD5 | input | TCELL25:IMUX.IMUX0.DELAY |
| TRNTD50 | input | TCELL38:IMUX.IMUX0.DELAY |
| TRNTD51 | input | TCELL38:IMUX.IMUX1.DELAY |
| TRNTD52 | input | TCELL38:IMUX.IMUX2.DELAY |
| TRNTD53 | input | TCELL38:IMUX.IMUX3.DELAY |
| TRNTD54 | input | TCELL39:IMUX.IMUX0.DELAY |
| TRNTD55 | input | TCELL39:IMUX.IMUX1.DELAY |
| TRNTD56 | input | TCELL39:IMUX.IMUX2.DELAY |
| TRNTD57 | input | TCELL39:IMUX.IMUX3.DELAY |
| TRNTD58 | input | TCELL19:IMUX.IMUX0.DELAY |
| TRNTD59 | input | TCELL19:IMUX.IMUX1.DELAY |
| TRNTD6 | input | TCELL25:IMUX.IMUX1.DELAY |
| TRNTD60 | input | TCELL19:IMUX.IMUX2.DELAY |
| TRNTD61 | input | TCELL19:IMUX.IMUX3.DELAY |
| TRNTD62 | input | TCELL18:IMUX.IMUX0.DELAY |
| TRNTD63 | input | TCELL18:IMUX.IMUX1.DELAY |
| TRNTD7 | input | TCELL25:IMUX.IMUX2.DELAY |
| TRNTD8 | input | TCELL25:IMUX.IMUX3.DELAY |
| TRNTD9 | input | TCELL26:IMUX.IMUX0.DELAY |
| TRNTDLLPDATA0 | input | TCELL13:IMUX.IMUX7.DELAY |
| TRNTDLLPDATA1 | input | TCELL13:IMUX.IMUX8.DELAY |
| TRNTDLLPDATA10 | input | TCELL7:IMUX.IMUX4.DELAY |
| TRNTDLLPDATA11 | input | TCELL7:IMUX.IMUX5.DELAY |
| TRNTDLLPDATA12 | input | TCELL7:IMUX.IMUX6.DELAY |
| TRNTDLLPDATA13 | input | TCELL7:IMUX.IMUX7.DELAY |
| TRNTDLLPDATA14 | input | TCELL6:IMUX.IMUX4.DELAY |
| TRNTDLLPDATA15 | input | TCELL6:IMUX.IMUX5.DELAY |
| TRNTDLLPDATA16 | input | TCELL6:IMUX.IMUX6.DELAY |
| TRNTDLLPDATA17 | input | TCELL6:IMUX.IMUX7.DELAY |
| TRNTDLLPDATA18 | input | TCELL5:IMUX.IMUX4.DELAY |
| TRNTDLLPDATA19 | input | TCELL5:IMUX.IMUX6.DELAY |
| TRNTDLLPDATA2 | input | TCELL9:IMUX.IMUX4.DELAY |
| TRNTDLLPDATA20 | input | TCELL5:IMUX.IMUX7.DELAY |
| TRNTDLLPDATA21 | input | TCELL5:IMUX.IMUX8.DELAY |
| TRNTDLLPDATA22 | input | TCELL4:IMUX.IMUX6.DELAY |
| TRNTDLLPDATA23 | input | TCELL3:IMUX.IMUX5.DELAY |
| TRNTDLLPDATA24 | input | TCELL3:IMUX.IMUX6.DELAY |
| TRNTDLLPDATA25 | input | TCELL3:IMUX.IMUX7.DELAY |
| TRNTDLLPDATA26 | input | TCELL3:IMUX.IMUX8.DELAY |
| TRNTDLLPDATA27 | input | TCELL23:IMUX.IMUX9.DELAY |
| TRNTDLLPDATA28 | input | TCELL25:IMUX.IMUX9.DELAY |
| TRNTDLLPDATA29 | input | TCELL26:IMUX.IMUX8.DELAY |
| TRNTDLLPDATA3 | input | TCELL9:IMUX.IMUX5.DELAY |
| TRNTDLLPDATA30 | input | TCELL26:IMUX.IMUX9.DELAY |
| TRNTDLLPDATA31 | input | TCELL26:IMUX.IMUX10.DELAY |
| TRNTDLLPDATA4 | input | TCELL9:IMUX.IMUX6.DELAY |
| TRNTDLLPDATA5 | input | TCELL9:IMUX.IMUX7.DELAY |
| TRNTDLLPDATA6 | input | TCELL8:IMUX.IMUX4.DELAY |
| TRNTDLLPDATA7 | input | TCELL8:IMUX.IMUX5.DELAY |
| TRNTDLLPDATA8 | input | TCELL8:IMUX.IMUX6.DELAY |
| TRNTDLLPDATA9 | input | TCELL8:IMUX.IMUX7.DELAY |
| TRNTDLLPDSTRDYN | output | TCELL14:OUT10.TMIN |
| TRNTDLLPSRCRDYN | input | TCELL26:IMUX.IMUX11.DELAY |
| TRNTDSTRDYN | output | TCELL22:OUT3.TMIN |
| TRNTECRCGENN | input | TCELL16:IMUX.IMUX0.DELAY |
| TRNTEOFN | input | TCELL17:IMUX.IMUX0.DELAY |
| TRNTERRDROPN | output | TCELL23:OUT0.TMIN |
| TRNTERRFWDN | input | TCELL17:IMUX.IMUX3.DELAY |
| TRNTREMN | input | TCELL18:IMUX.IMUX2.DELAY |
| TRNTSOFN | input | TCELL18:IMUX.IMUX3.DELAY |
| TRNTSRCDSCN | input | TCELL17:IMUX.IMUX2.DELAY |
| TRNTSRCRDYN | input | TCELL17:IMUX.IMUX1.DELAY |
| TRNTSTRN | input | TCELL16:IMUX.IMUX1.DELAY |
| USERCLK | input | TCELL29:IMUX.CLK0 |
| USERCLKPREBUF | input | TCELL20:IMUX.CLK0 |
| USERRSTN | output | TCELL22:OUT12.TMIN |
| XILUNCONNOUT0 | output | TCELL15:OUT15.TMIN |
| XILUNCONNOUT1 | output | TCELL14:OUT14.TMIN |
| XILUNCONNOUT2 | output | TCELL14:OUT16.TMIN |
| XILUNCONNOUT3 | output | TCELL13:OUT19.TMIN |
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA45 |
| TCELL0:IMUX.IMUX1.DELAY | PCIE.PIPERX3DATA4 |
| TCELL0:IMUX.IMUX2.DELAY | PCIE.CFGERRAERHEADERLOG33 |
| TCELL0:IMUX.IMUX3.DELAY | PCIE.PIPERX3DATA0 |
| TCELL0:IMUX.IMUX4.DELAY | PCIE.CFGERRAERHEADERLOG34 |
| TCELL0:IMUX.IMUX5.DELAY | PCIE.PIPERX3DATA1 |
| TCELL0:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG35 |
| TCELL0:IMUX.IMUX7.DELAY | PCIE.PIPERX7DATA2 |
| TCELL0:IMUX.IMUX8.DELAY | PCIE.CFGERRAERHEADERLOG36 |
| TCELL0:IMUX.IMUX9.DELAY | PCIE.PIPERX3DATA5 |
| TCELL0:IMUX.IMUX10.DELAY | PCIE.CFGDSBUSNUMBER0 |
| TCELL0:IMUX.IMUX11.DELAY | PCIE.PIPERX7DATA0 |
| TCELL0:IMUX.IMUX12.DELAY | PCIE.CFGDSBUSNUMBER1 |
| TCELL0:IMUX.IMUX13.DELAY | PCIE.PIPERX7DATA1 |
| TCELL0:IMUX.IMUX14.DELAY | PCIE.CFGDSBUSNUMBER2 |
| TCELL0:IMUX.IMUX15.DELAY | PCIE.PIPERX3DATA2 |
| TCELL0:IMUX.IMUX16.DELAY | PCIE.CFGDSBUSNUMBER3 |
| TCELL0:IMUX.IMUX17.DELAY | PCIE.PIPERX7DATA4 |
| TCELL0:IMUX.IMUX19.DELAY | PCIE.PIPERX3DATA3 |
| TCELL0:IMUX.IMUX21.DELAY | PCIE.PIPERX7DATA5 |
| TCELL0:IMUX.IMUX23.DELAY | PCIE.PIPERX7DATA3 |
| TCELL0:OUT0.TMIN | PCIE.TRNFCCPLH5 |
| TCELL0:OUT1.TMIN | PCIE.TRNFCCPLH6 |
| TCELL0:OUT2.TMIN | PCIE.TRNFCCPLH7 |
| TCELL0:OUT3.TMIN | PCIE.TRNFCCPLD0 |
| TCELL0:OUT4.TMIN | PCIE.MIMRXWDATA11 |
| TCELL0:OUT5.TMIN | PCIE.MIMRXWDATA12 |
| TCELL0:OUT6.TMIN | PCIE.PIPETXMARGIN2 |
| TCELL0:OUT7.TMIN | PCIE.MIMRXWDATA13 |
| TCELL0:OUT8.TMIN | PCIE.MIMRXWDATA14 |
| TCELL0:OUT9.TMIN | PCIE.PL2LINKUPN |
| TCELL0:OUT10.TMIN | PCIE.PL2RECEIVERERRN |
| TCELL0:OUT11.TMIN | PCIE.LL2PROTOCOLERRN |
| TCELL0:OUT12.TMIN | PCIE.LL2BADTLPERRN |
| TCELL0:OUT13.TMIN | PCIE.CFGCOMMANDIOENABLE |
| TCELL0:OUT14.TMIN | PCIE.CFGCOMMANDMEMENABLE |
| TCELL0:OUT15.TMIN | PCIE.CFGCOMMANDBUSMASTERENABLE |
| TCELL0:OUT16.TMIN | PCIE.PIPETXMARGIN1 |
| TCELL0:OUT17.TMIN | PCIE.CFGCOMMANDSERREN |
| TCELL0:OUT18.TMIN | PCIE.PIPETXMARGIN0 |
| TCELL0:OUT19.TMIN | PCIE.DBGVECA26 |
| TCELL0:OUT20.TMIN | PCIE.DBGVECA27 |
| TCELL0:OUT21.TMIN | PCIE.DBGVECA28 |
| TCELL0:OUT22.TMIN | PCIE.DBGVECA29 |
| TCELL0:OUT23.TMIN | PCIE.DBGVECB59 |
| TCELL1:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA44 |
| TCELL1:IMUX.IMUX1.DELAY | PCIE.PIPERX3DATA6 |
| TCELL1:IMUX.IMUX2.DELAY | PCIE.CFGERRAERHEADERLOG29 |
| TCELL1:IMUX.IMUX3.DELAY | PCIE.PIPERX3DATA8 |
| TCELL1:IMUX.IMUX4.DELAY | PCIE.CFGERRAERHEADERLOG30 |
| TCELL1:IMUX.IMUX5.DELAY | PCIE.PIPERX3DATA9 |
| TCELL1:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG31 |
| TCELL1:IMUX.IMUX7.DELAY | PCIE.PIPERX3DATA10 |
| TCELL1:IMUX.IMUX8.DELAY | PCIE.CFGERRAERHEADERLOG32 |
| TCELL1:IMUX.IMUX9.DELAY | PCIE.PIPERX3DATA7 |
| TCELL1:IMUX.IMUX10.DELAY | PCIE.CFGINTERRUPTDI5 |
| TCELL1:IMUX.IMUX11.DELAY | PCIE.PIPERX7DATA8 |
| TCELL1:IMUX.IMUX12.DELAY | PCIE.CFGINTERRUPTDI6 |
| TCELL1:IMUX.IMUX13.DELAY | PCIE.PIPERX7DATA9 |
| TCELL1:IMUX.IMUX14.DELAY | PCIE.CFGINTERRUPTDI7 |
| TCELL1:IMUX.IMUX15.DELAY | PCIE.PIPERX3DATA11 |
| TCELL1:IMUX.IMUX16.DELAY | PCIE.CFGINTERRUPTASSERTN |
| TCELL1:IMUX.IMUX17.DELAY | PCIE.PIPERX7DATA6 |
| TCELL1:IMUX.IMUX19.DELAY | PCIE.PIPERX7DATA10 |
| TCELL1:IMUX.IMUX21.DELAY | PCIE.PIPERX7DATA7 |
| TCELL1:IMUX.IMUX23.DELAY | PCIE.PIPERX7DATA11 |
| TCELL1:OUT0.TMIN | PCIE.TRNFCCPLH1 |
| TCELL1:OUT1.TMIN | PCIE.TRNFCCPLH2 |
| TCELL1:OUT2.TMIN | PCIE.TRNFCCPLH3 |
| TCELL1:OUT3.TMIN | PCIE.TRNFCCPLH4 |
| TCELL1:OUT4.TMIN | PCIE.MIMRXWDATA7 |
| TCELL1:OUT5.TMIN | PCIE.MIMRXWDATA8 |
| TCELL1:OUT6.TMIN | PCIE.MIMRXWDATA9 |
| TCELL1:OUT7.TMIN | PCIE.MIMRXWDATA10 |
| TCELL1:OUT8.TMIN | PCIE.LL2SUSPENDOKN |
| TCELL1:OUT9.TMIN | PCIE.TL2PPMSUSPENDOKN |
| TCELL1:OUT10.TMIN | PCIE.TL2ASPMSUSPENDREQN |
| TCELL1:OUT11.TMIN | PCIE.TL2ASPMSUSPENDCREDITCHECKOKN |
| TCELL1:OUT12.TMIN | PCIE.CFGTRANSACTIONADDR3 |
| TCELL1:OUT13.TMIN | PCIE.CFGTRANSACTIONADDR4 |
| TCELL1:OUT14.TMIN | PCIE.CFGTRANSACTIONADDR5 |
| TCELL1:OUT15.TMIN | PCIE.CFGTRANSACTIONADDR6 |
| TCELL1:OUT16.TMIN | PCIE.DRPDO7 |
| TCELL1:OUT17.TMIN | PCIE.DRPDO8 |
| TCELL1:OUT18.TMIN | PCIE.PIPERX3POLARITY |
| TCELL1:OUT19.TMIN | PCIE.DRPDO9 |
| TCELL1:OUT20.TMIN | PCIE.DBGVECB58 |
| TCELL1:OUT21.TMIN | PCIE.DBGVECA24 |
| TCELL1:OUT22.TMIN | PCIE.PIPERX7POLARITY |
| TCELL1:OUT23.TMIN | PCIE.DBGVECA25 |
| TCELL2:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA41 |
| TCELL2:IMUX.IMUX1.DELAY | PCIE.PIPERX3CHARISK1 |
| TCELL2:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA42 |
| TCELL2:IMUX.IMUX3.DELAY | PCIE.PIPERX7DATA13 |
| TCELL2:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA43 |
| TCELL2:IMUX.IMUX5.DELAY | PCIE.PIPERX3DATA12 |
| TCELL2:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG25 |
| TCELL2:IMUX.IMUX7.DELAY | PCIE.PIPERX3DATA13 |
| TCELL2:IMUX.IMUX8.DELAY | PCIE.CFGERRAERHEADERLOG26 |
| TCELL2:IMUX.IMUX9.DELAY | PCIE.PIPERX3DATA15 |
| TCELL2:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG27 |
| TCELL2:IMUX.IMUX11.DELAY | PCIE.PIPERX3DATA14 |
| TCELL2:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG28 |
| TCELL2:IMUX.IMUX13.DELAY | PCIE.PIPERX7DATA12 |
| TCELL2:IMUX.IMUX14.DELAY | PCIE.CFGINTERRUPTDI1 |
| TCELL2:IMUX.IMUX15.DELAY | PCIE.PIPERX7DATA14 |
| TCELL2:IMUX.IMUX16.DELAY | PCIE.CFGINTERRUPTDI2 |
| TCELL2:IMUX.IMUX17.DELAY | PCIE.PIPERX7CHARISK1 |
| TCELL2:IMUX.IMUX18.DELAY | PCIE.CFGINTERRUPTDI3 |
| TCELL2:IMUX.IMUX19.DELAY | PCIE.CFGINTERRUPTDI4 |
| TCELL2:IMUX.IMUX21.DELAY | PCIE.PIPERX7DATA15 |
| TCELL2:OUT0.TMIN | PCIE.TRNFCNPD9 |
| TCELL2:OUT1.TMIN | PCIE.TRNFCNPD10 |
| TCELL2:OUT2.TMIN | PCIE.TRNFCNPD11 |
| TCELL2:OUT3.TMIN | PCIE.TRNFCCPLH0 |
| TCELL2:OUT4.TMIN | PCIE.MIMRXWDATA3 |
| TCELL2:OUT5.TMIN | PCIE.MIMRXWDATA4 |
| TCELL2:OUT6.TMIN | PCIE.MIMRXWDATA5 |
| TCELL2:OUT7.TMIN | PCIE.MIMRXWDATA6 |
| TCELL2:OUT8.TMIN | PCIE.LL2TFCINIT2SEQN |
| TCELL2:OUT9.TMIN | PCIE.PL2SUSPENDOK |
| TCELL2:OUT10.TMIN | PCIE.PL2RECOVERYN |
| TCELL2:OUT11.TMIN | PCIE.PL2RXELECIDLE |
| TCELL2:OUT12.TMIN | PCIE.CFGTRANSACTIONTYPE |
| TCELL2:OUT13.TMIN | PCIE.CFGTRANSACTIONADDR0 |
| TCELL2:OUT14.TMIN | PCIE.CFGTRANSACTIONADDR1 |
| TCELL2:OUT15.TMIN | PCIE.CFGTRANSACTIONADDR2 |
| TCELL2:OUT16.TMIN | PCIE.DRPDO3 |
| TCELL2:OUT17.TMIN | PCIE.DRPDO4 |
| TCELL2:OUT18.TMIN | PCIE.DRPDO5 |
| TCELL2:OUT19.TMIN | PCIE.DRPDO6 |
| TCELL2:OUT20.TMIN | PCIE.DBGVECA20 |
| TCELL2:OUT21.TMIN | PCIE.DBGVECA21 |
| TCELL2:OUT22.TMIN | PCIE.DBGVECA22 |
| TCELL2:OUT23.TMIN | PCIE.DBGVECA23 |
| TCELL3:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA37 |
| TCELL3:IMUX.IMUX1.DELAY | PCIE.PIPERX7CHANISALIGNED |
| TCELL3:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA38 |
| TCELL3:IMUX.IMUX3.DELAY | PCIE.MIMTXRDATA39 |
| TCELL3:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA40 |
| TCELL3:IMUX.IMUX5.DELAY | PCIE.TRNTDLLPDATA23 |
| TCELL3:IMUX.IMUX6.DELAY | PCIE.TRNTDLLPDATA24 |
| TCELL3:IMUX.IMUX7.DELAY | PCIE.TRNTDLLPDATA25 |
| TCELL3:IMUX.IMUX8.DELAY | PCIE.TRNTDLLPDATA26 |
| TCELL3:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG21 |
| TCELL3:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG22 |
| TCELL3:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG23 |
| TCELL3:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG24 |
| TCELL3:IMUX.IMUX13.DELAY | PCIE.CFGERRTLPCPLHEADER46 |
| TCELL3:IMUX.IMUX14.DELAY | PCIE.CFGERRTLPCPLHEADER47 |
| TCELL3:IMUX.IMUX15.DELAY | PCIE.PIPERX7CHARISK0 |
| TCELL3:IMUX.IMUX16.DELAY | PCIE.CFGINTERRUPTN |
| TCELL3:IMUX.IMUX17.DELAY | PCIE.CFGINTERRUPTDI0 |
| TCELL3:IMUX.IMUX18.DELAY | PCIE.CFGDSN63 |
| TCELL3:IMUX.IMUX21.DELAY | PCIE.PIPERX3CHANISALIGNED |
| TCELL3:IMUX.IMUX23.DELAY | PCIE.PIPERX3CHARISK0 |
| TCELL3:OUT0.TMIN | PCIE.TRNFCNPD5 |
| TCELL3:OUT1.TMIN | PCIE.TRNFCNPD6 |
| TCELL3:OUT2.TMIN | PCIE.TRNFCNPD7 |
| TCELL3:OUT3.TMIN | PCIE.TRNFCNPD8 |
| TCELL3:OUT4.TMIN | PCIE.MIMTXRCE |
| TCELL3:OUT5.TMIN | PCIE.MIMRXWDATA0 |
| TCELL3:OUT6.TMIN | PCIE.MIMRXWDATA1 |
| TCELL3:OUT7.TMIN | PCIE.MIMRXWDATA2 |
| TCELL3:OUT8.TMIN | PCIE.TRNRDLLPDATA30 |
| TCELL3:OUT9.TMIN | PCIE.TRNRDLLPDATA31 |
| TCELL3:OUT10.TMIN | PCIE.TRNRDLLPSRCRDYN |
| TCELL3:OUT11.TMIN | PCIE.LL2TFCINIT1SEQN |
| TCELL3:OUT12.TMIN | PCIE.CFGPMRCVENTERL1N |
| TCELL3:OUT13.TMIN | PCIE.CFGPMRCVENTERL23N |
| TCELL3:OUT14.TMIN | PCIE.CFGPMRCVREQACKN |
| TCELL3:OUT15.TMIN | PCIE.CFGTRANSACTION |
| TCELL3:OUT16.TMIN | PCIE.DRPDRDY |
| TCELL3:OUT17.TMIN | PCIE.DRPDO0 |
| TCELL3:OUT18.TMIN | PCIE.DRPDO1 |
| TCELL3:OUT19.TMIN | PCIE.DRPDO2 |
| TCELL3:OUT20.TMIN | PCIE.DBGVECA16 |
| TCELL3:OUT21.TMIN | PCIE.DBGVECA17 |
| TCELL3:OUT22.TMIN | PCIE.DBGVECA18 |
| TCELL3:OUT23.TMIN | PCIE.DBGVECA19 |
| TCELL4:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA33 |
| TCELL4:IMUX.IMUX1.DELAY | PCIE.PIPERX7STATUS2 |
| TCELL4:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA34 |
| TCELL4:IMUX.IMUX3.DELAY | PCIE.PIPERX7STATUS0 |
| TCELL4:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA35 |
| TCELL4:IMUX.IMUX5.DELAY | PCIE.MIMTXRDATA36 |
| TCELL4:IMUX.IMUX6.DELAY | PCIE.TRNTDLLPDATA22 |
| TCELL4:IMUX.IMUX7.DELAY | PCIE.PIPERX7STATUS1 |
| TCELL4:IMUX.IMUX8.DELAY | PCIE.CFGERRAERHEADERLOG17 |
| TCELL4:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG18 |
| TCELL4:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG19 |
| TCELL4:IMUX.IMUX11.DELAY | PCIE.PIPERX3PHYSTATUS |
| TCELL4:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG20 |
| TCELL4:IMUX.IMUX13.DELAY | PCIE.CFGERRTLPCPLHEADER42 |
| TCELL4:IMUX.IMUX14.DELAY | PCIE.CFGERRTLPCPLHEADER43 |
| TCELL4:IMUX.IMUX15.DELAY | PCIE.PIPERX7PHYSTATUS |
| TCELL4:IMUX.IMUX16.DELAY | PCIE.CFGERRTLPCPLHEADER44 |
| TCELL4:IMUX.IMUX17.DELAY | PCIE.CFGERRTLPCPLHEADER45 |
| TCELL4:IMUX.IMUX19.DELAY | PCIE.PIPERX3STATUS1 |
| TCELL4:IMUX.IMUX21.DELAY | PCIE.PIPERX3STATUS2 |
| TCELL4:IMUX.IMUX23.DELAY | PCIE.PIPERX3STATUS0 |
| TCELL4:OUT0.TMIN | PCIE.TRNFCNPD1 |
| TCELL4:OUT1.TMIN | PCIE.PIPETX3ELECIDLE |
| TCELL4:OUT2.TMIN | PCIE.TRNFCNPD2 |
| TCELL4:OUT3.TMIN | PCIE.TRNFCNPD3 |
| TCELL4:OUT4.TMIN | PCIE.TRNFCNPD4 |
| TCELL4:OUT5.TMIN | PCIE.PIPETX7ELECIDLE |
| TCELL4:OUT6.TMIN | PCIE.MIMTXRADDR10 |
| TCELL4:OUT7.TMIN | PCIE.MIMTXRADDR11 |
| TCELL4:OUT8.TMIN | PCIE.MIMTXRADDR12 |
| TCELL4:OUT9.TMIN | PCIE.MIMTXREN |
| TCELL4:OUT10.TMIN | PCIE.TRNRDLLPDATA26 |
| TCELL4:OUT11.TMIN | PCIE.TRNRDLLPDATA27 |
| TCELL4:OUT12.TMIN | PCIE.TRNRDLLPDATA28 |
| TCELL4:OUT13.TMIN | PCIE.TRNRDLLPDATA29 |
| TCELL4:OUT14.TMIN | PCIE.CFGPCIELINKSTATE2 |
| TCELL4:OUT15.TMIN | PCIE.CFGPMRCVASREQL1N |
| TCELL4:OUT16.TMIN | PCIE.DBGVECB57 |
| TCELL4:OUT17.TMIN | PCIE.PIPETX7POWERDOWN0 |
| TCELL4:OUT18.TMIN | PCIE.DBGVECA13 |
| TCELL4:OUT19.TMIN | PCIE.PIPETX7POWERDOWN1 |
| TCELL4:OUT20.TMIN | PCIE.DBGVECA14 |
| TCELL4:OUT21.TMIN | PCIE.PIPETX3POWERDOWN0 |
| TCELL4:OUT22.TMIN | PCIE.DBGVECA15 |
| TCELL4:OUT23.TMIN | PCIE.PIPETX3POWERDOWN1 |
| TCELL5:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA29 |
| TCELL5:IMUX.IMUX1.DELAY | PCIE.MIMTXRDATA30 |
| TCELL5:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA31 |
| TCELL5:IMUX.IMUX3.DELAY | PCIE.MIMTXRDATA32 |
| TCELL5:IMUX.IMUX4.DELAY | PCIE.TRNTDLLPDATA18 |
| TCELL5:IMUX.IMUX5.DELAY | PCIE.PIPERX7ELECIDLE |
| TCELL5:IMUX.IMUX6.DELAY | PCIE.TRNTDLLPDATA19 |
| TCELL5:IMUX.IMUX7.DELAY | PCIE.TRNTDLLPDATA20 |
| TCELL5:IMUX.IMUX8.DELAY | PCIE.TRNTDLLPDATA21 |
| TCELL5:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG13 |
| TCELL5:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG14 |
| TCELL5:IMUX.IMUX11.DELAY | PCIE.PIPERX7VALID |
| TCELL5:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG15 |
| TCELL5:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG16 |
| TCELL5:IMUX.IMUX14.DELAY | PCIE.CFGERRTLPCPLHEADER38 |
| TCELL5:IMUX.IMUX15.DELAY | PCIE.CFGERRTLPCPLHEADER39 |
| TCELL5:IMUX.IMUX16.DELAY | PCIE.CFGERRTLPCPLHEADER40 |
| TCELL5:IMUX.IMUX17.DELAY | PCIE.CFGERRTLPCPLHEADER41 |
| TCELL5:IMUX.IMUX18.DELAY | PCIE.CFGDSN62 |
| TCELL5:IMUX.IMUX19.DELAY | PCIE.PIPERX3VALID |
| TCELL5:IMUX.IMUX21.DELAY | PCIE.PIPERX3ELECIDLE |
| TCELL5:OUT0.TMIN | PCIE.TRNFCNPH5 |
| TCELL5:OUT1.TMIN | PCIE.TRNFCNPH6 |
| TCELL5:OUT2.TMIN | PCIE.TRNFCNPH7 |
| TCELL5:OUT3.TMIN | PCIE.TRNFCNPD0 |
| TCELL5:OUT4.TMIN | PCIE.MIMTXRADDR6 |
| TCELL5:OUT5.TMIN | PCIE.MIMTXRADDR7 |
| TCELL5:OUT6.TMIN | PCIE.MIMTXRADDR8 |
| TCELL5:OUT7.TMIN | PCIE.MIMTXRADDR9 |
| TCELL5:OUT8.TMIN | PCIE.TRNRDLLPDATA22 |
| TCELL5:OUT9.TMIN | PCIE.TRNRDLLPDATA23 |
| TCELL5:OUT10.TMIN | PCIE.TRNRDLLPDATA24 |
| TCELL5:OUT11.TMIN | PCIE.TRNRDLLPDATA25 |
| TCELL5:OUT12.TMIN | PCIE.CFGPCIELINKSTATE1 |
| TCELL5:OUT13.TMIN | PCIE.DBGVECB55 |
| TCELL5:OUT14.TMIN | PCIE.DBGVECB56 |
| TCELL5:OUT15.TMIN | PCIE.DBGVECA10 |
| TCELL5:OUT16.TMIN | PCIE.PIPETX3COMPLIANCE |
| TCELL5:OUT17.TMIN | PCIE.DBGVECA11 |
| TCELL5:OUT18.TMIN | PCIE.PIPETX3CHARISK0 |
| TCELL5:OUT19.TMIN | PCIE.PIPETX7CHARISK1 |
| TCELL5:OUT20.TMIN | PCIE.PIPETX7COMPLIANCE |
| TCELL5:OUT21.TMIN | PCIE.DBGVECA12 |
| TCELL5:OUT22.TMIN | PCIE.PIPETX7CHARISK0 |
| TCELL5:OUT23.TMIN | PCIE.PIPETX3CHARISK1 |
| TCELL6:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA25 |
| TCELL6:IMUX.IMUX1.DELAY | PCIE.MIMTXRDATA26 |
| TCELL6:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA27 |
| TCELL6:IMUX.IMUX3.DELAY | PCIE.MIMTXRDATA28 |
| TCELL6:IMUX.IMUX4.DELAY | PCIE.TRNTDLLPDATA14 |
| TCELL6:IMUX.IMUX5.DELAY | PCIE.TRNTDLLPDATA15 |
| TCELL6:IMUX.IMUX6.DELAY | PCIE.TRNTDLLPDATA16 |
| TCELL6:IMUX.IMUX7.DELAY | PCIE.TRNTDLLPDATA17 |
| TCELL6:IMUX.IMUX8.DELAY | PCIE.CFGERRAERHEADERLOG9 |
| TCELL6:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG10 |
| TCELL6:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG11 |
| TCELL6:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG12 |
| TCELL6:IMUX.IMUX12.DELAY | PCIE.CFGERRTLPCPLHEADER34 |
| TCELL6:IMUX.IMUX13.DELAY | PCIE.CFGERRTLPCPLHEADER35 |
| TCELL6:IMUX.IMUX14.DELAY | PCIE.CFGERRTLPCPLHEADER36 |
| TCELL6:IMUX.IMUX15.DELAY | PCIE.CFGERRTLPCPLHEADER37 |
| TCELL6:IMUX.IMUX16.DELAY | PCIE.CFGDSN58 |
| TCELL6:IMUX.IMUX17.DELAY | PCIE.CFGDSN59 |
| TCELL6:IMUX.IMUX18.DELAY | PCIE.CFGDSN60 |
| TCELL6:IMUX.IMUX19.DELAY | PCIE.CFGDSN61 |
| TCELL6:IMUX.IMUX20.DELAY | PCIE.DBGMODE1 |
| TCELL6:OUT0.TMIN | PCIE.TRNFCNPH1 |
| TCELL6:OUT1.TMIN | PCIE.TRNFCNPH2 |
| TCELL6:OUT2.TMIN | PCIE.PIPETX7DATA13 |
| TCELL6:OUT3.TMIN | PCIE.TRNFCNPH3 |
| TCELL6:OUT4.TMIN | PCIE.TRNFCNPH4 |
| TCELL6:OUT5.TMIN | PCIE.MIMTXRADDR2 |
| TCELL6:OUT6.TMIN | PCIE.PIPETX3DATA13 |
| TCELL6:OUT7.TMIN | PCIE.MIMTXRADDR3 |
| TCELL6:OUT8.TMIN | PCIE.MIMTXRADDR4 |
| TCELL6:OUT9.TMIN | PCIE.MIMTXRADDR5 |
| TCELL6:OUT10.TMIN | PCIE.TRNRDLLPDATA20 |
| TCELL6:OUT11.TMIN | PCIE.TRNRDLLPDATA21 |
| TCELL6:OUT12.TMIN | PCIE.CFGPCIELINKSTATE0 |
| TCELL6:OUT13.TMIN | PCIE.DBGVECB53 |
| TCELL6:OUT14.TMIN | PCIE.DBGVECB54 |
| TCELL6:OUT15.TMIN | PCIE.DBGVECA7 |
| TCELL6:OUT16.TMIN | PCIE.PIPETX3DATA12 |
| TCELL6:OUT17.TMIN | PCIE.PIPETX7DATA15 |
| TCELL6:OUT18.TMIN | PCIE.DBGVECA8 |
| TCELL6:OUT19.TMIN | PCIE.PIPETX7DATA14 |
| TCELL6:OUT20.TMIN | PCIE.PIPETX7DATA12 |
| TCELL6:OUT21.TMIN | PCIE.PIPETX3DATA15 |
| TCELL6:OUT22.TMIN | PCIE.DBGVECA9 |
| TCELL6:OUT23.TMIN | PCIE.PIPETX3DATA14 |
| TCELL7:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA21 |
| TCELL7:IMUX.IMUX1.DELAY | PCIE.MIMTXRDATA22 |
| TCELL7:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA23 |
| TCELL7:IMUX.IMUX3.DELAY | PCIE.MIMTXRDATA24 |
| TCELL7:IMUX.IMUX4.DELAY | PCIE.TRNTDLLPDATA10 |
| TCELL7:IMUX.IMUX5.DELAY | PCIE.TRNTDLLPDATA11 |
| TCELL7:IMUX.IMUX6.DELAY | PCIE.TRNTDLLPDATA12 |
| TCELL7:IMUX.IMUX7.DELAY | PCIE.TRNTDLLPDATA13 |
| TCELL7:IMUX.IMUX8.DELAY | PCIE.CFGERRAERHEADERLOG5 |
| TCELL7:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG6 |
| TCELL7:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG7 |
| TCELL7:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG8 |
| TCELL7:IMUX.IMUX12.DELAY | PCIE.CFGERRTLPCPLHEADER30 |
| TCELL7:IMUX.IMUX13.DELAY | PCIE.CFGERRTLPCPLHEADER31 |
| TCELL7:IMUX.IMUX14.DELAY | PCIE.CFGERRTLPCPLHEADER32 |
| TCELL7:IMUX.IMUX15.DELAY | PCIE.CFGERRTLPCPLHEADER33 |
| TCELL7:IMUX.IMUX16.DELAY | PCIE.CFGDSN54 |
| TCELL7:IMUX.IMUX17.DELAY | PCIE.CFGDSN55 |
| TCELL7:IMUX.IMUX18.DELAY | PCIE.CFGDSN56 |
| TCELL7:IMUX.IMUX19.DELAY | PCIE.CFGDSN57 |
| TCELL7:IMUX.IMUX20.DELAY | PCIE.DBGMODE0 |
| TCELL7:OUT0.TMIN | PCIE.TRNFCPD9 |
| TCELL7:OUT1.TMIN | PCIE.PIPETX3DATA11 |
| TCELL7:OUT2.TMIN | PCIE.PIPETX7DATA8 |
| TCELL7:OUT3.TMIN | PCIE.TRNFCPD10 |
| TCELL7:OUT4.TMIN | PCIE.TRNFCPD11 |
| TCELL7:OUT5.TMIN | PCIE.PIPETX7DATA11 |
| TCELL7:OUT6.TMIN | PCIE.PIPETX3DATA8 |
| TCELL7:OUT7.TMIN | PCIE.TRNFCNPH0 |
| TCELL7:OUT8.TMIN | PCIE.MIMTXRADDR0 |
| TCELL7:OUT9.TMIN | PCIE.MIMTXRADDR1 |
| TCELL7:OUT10.TMIN | PCIE.CFGMSGRECEIVEDPMASNAK |
| TCELL7:OUT11.TMIN | PCIE.DBGVECB51 |
| TCELL7:OUT12.TMIN | PCIE.DBGVECB52 |
| TCELL7:OUT13.TMIN | PCIE.DBGVECA4 |
| TCELL7:OUT14.TMIN | PCIE.DBGVECA5 |
| TCELL7:OUT15.TMIN | PCIE.DBGVECA6 |
| TCELL7:OUT16.TMIN | PCIE.PIPETX3DATA7 |
| TCELL7:OUT17.TMIN | PCIE.PIPETX7DATA10 |
| TCELL7:OUT18.TMIN | PCIE.PIPETX3DATA6 |
| TCELL7:OUT19.TMIN | PCIE.PIPETX7DATA9 |
| TCELL7:OUT20.TMIN | PCIE.PIPETX7DATA7 |
| TCELL7:OUT21.TMIN | PCIE.PIPETX3DATA10 |
| TCELL7:OUT22.TMIN | PCIE.PIPETX7DATA6 |
| TCELL7:OUT23.TMIN | PCIE.PIPETX3DATA9 |
| TCELL8:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA17 |
| TCELL8:IMUX.IMUX1.DELAY | PCIE.MIMTXRDATA18 |
| TCELL8:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA19 |
| TCELL8:IMUX.IMUX3.DELAY | PCIE.MIMTXRDATA20 |
| TCELL8:IMUX.IMUX4.DELAY | PCIE.TRNTDLLPDATA6 |
| TCELL8:IMUX.IMUX5.DELAY | PCIE.TRNTDLLPDATA7 |
| TCELL8:IMUX.IMUX6.DELAY | PCIE.TRNTDLLPDATA8 |
| TCELL8:IMUX.IMUX7.DELAY | PCIE.TRNTDLLPDATA9 |
| TCELL8:IMUX.IMUX8.DELAY | PCIE.CFGERRAERHEADERLOG1 |
| TCELL8:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG2 |
| TCELL8:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG3 |
| TCELL8:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG4 |
| TCELL8:IMUX.IMUX12.DELAY | PCIE.CFGERRTLPCPLHEADER26 |
| TCELL8:IMUX.IMUX13.DELAY | PCIE.CFGERRTLPCPLHEADER27 |
| TCELL8:IMUX.IMUX14.DELAY | PCIE.CFGERRTLPCPLHEADER28 |
| TCELL8:IMUX.IMUX15.DELAY | PCIE.CFGERRTLPCPLHEADER29 |
| TCELL8:IMUX.IMUX16.DELAY | PCIE.CFGDSN50 |
| TCELL8:IMUX.IMUX17.DELAY | PCIE.CFGDSN51 |
| TCELL8:IMUX.IMUX18.DELAY | PCIE.CFGDSN52 |
| TCELL8:IMUX.IMUX19.DELAY | PCIE.CFGDSN53 |
| TCELL8:IMUX.IMUX20.DELAY | PCIE.DRPDI15 |
| TCELL8:OUT0.TMIN | PCIE.TRNFCPD5 |
| TCELL8:OUT1.TMIN | PCIE.PIPETX3DATA3 |
| TCELL8:OUT2.TMIN | PCIE.PIPETX7DATA4 |
| TCELL8:OUT3.TMIN | PCIE.TRNFCPD6 |
| TCELL8:OUT4.TMIN | PCIE.TRNFCPD7 |
| TCELL8:OUT5.TMIN | PCIE.PIPETX7DATA3 |
| TCELL8:OUT6.TMIN | PCIE.PIPETX3DATA4 |
| TCELL8:OUT7.TMIN | PCIE.TRNFCPD8 |
| TCELL8:OUT8.TMIN | PCIE.MIMTXWADDR12 |
| TCELL8:OUT9.TMIN | PCIE.MIMTXWEN |
| TCELL8:OUT10.TMIN | PCIE.CFGMSGRECEIVEDUNLOCK |
| TCELL8:OUT11.TMIN | PCIE.DBGVECB49 |
| TCELL8:OUT12.TMIN | PCIE.CFGVCTCVCMAP4 |
| TCELL8:OUT13.TMIN | PCIE.CFGVCTCVCMAP5 |
| TCELL8:OUT14.TMIN | PCIE.CFGVCTCVCMAP6 |
| TCELL8:OUT15.TMIN | PCIE.DBGVECB50 |
| TCELL8:OUT16.TMIN | PCIE.PIPETX3DATA0 |
| TCELL8:OUT17.TMIN | PCIE.PIPETX7DATA1 |
| TCELL8:OUT18.TMIN | PCIE.PIPETX3DATA5 |
| TCELL8:OUT19.TMIN | PCIE.PIPETX7DATA2 |
| TCELL8:OUT20.TMIN | PCIE.PIPETX7DATA0 |
| TCELL8:OUT21.TMIN | PCIE.PIPETX3DATA1 |
| TCELL8:OUT22.TMIN | PCIE.PIPETX7DATA5 |
| TCELL8:OUT23.TMIN | PCIE.PIPETX3DATA2 |
| TCELL9:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA13 |
| TCELL9:IMUX.IMUX1.DELAY | PCIE.MIMTXRDATA14 |
| TCELL9:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA15 |
| TCELL9:IMUX.IMUX3.DELAY | PCIE.MIMTXRDATA16 |
| TCELL9:IMUX.IMUX4.DELAY | PCIE.TRNTDLLPDATA2 |
| TCELL9:IMUX.IMUX5.DELAY | PCIE.TRNTDLLPDATA3 |
| TCELL9:IMUX.IMUX6.DELAY | PCIE.TRNTDLLPDATA4 |
| TCELL9:IMUX.IMUX7.DELAY | PCIE.TRNTDLLPDATA5 |
| TCELL9:IMUX.IMUX8.DELAY | PCIE.CFGERRACSN |
| TCELL9:IMUX.IMUX9.DELAY | PCIE.CFGERRPOSTEDN |
| TCELL9:IMUX.IMUX10.DELAY | PCIE.CFGERRLOCKEDN |
| TCELL9:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG0 |
| TCELL9:IMUX.IMUX12.DELAY | PCIE.CFGERRTLPCPLHEADER22 |
| TCELL9:IMUX.IMUX13.DELAY | PCIE.CFGERRTLPCPLHEADER23 |
| TCELL9:IMUX.IMUX14.DELAY | PCIE.CFGERRTLPCPLHEADER24 |
| TCELL9:IMUX.IMUX15.DELAY | PCIE.CFGERRTLPCPLHEADER25 |
| TCELL9:IMUX.IMUX16.DELAY | PCIE.CFGDSN46 |
| TCELL9:IMUX.IMUX17.DELAY | PCIE.CFGDSN47 |
| TCELL9:IMUX.IMUX18.DELAY | PCIE.CFGDSN48 |
| TCELL9:IMUX.IMUX19.DELAY | PCIE.CFGDSN49 |
| TCELL9:IMUX.IMUX20.DELAY | PCIE.DRPDI14 |
| TCELL9:OUT0.TMIN | PCIE.TRNFCPD1 |
| TCELL9:OUT1.TMIN | PCIE.TRNFCPD2 |
| TCELL9:OUT2.TMIN | PCIE.TRNFCPD3 |
| TCELL9:OUT3.TMIN | PCIE.TRNFCPD4 |
| TCELL9:OUT4.TMIN | PCIE.MIMTXWADDR8 |
| TCELL9:OUT5.TMIN | PCIE.MIMTXWADDR9 |
| TCELL9:OUT6.TMIN | PCIE.MIMTXWADDR10 |
| TCELL9:OUT7.TMIN | PCIE.MIMTXWADDR11 |
| TCELL9:OUT8.TMIN | PCIE.TRNRDLLPDATA16 |
| TCELL9:OUT9.TMIN | PCIE.TRNRDLLPDATA17 |
| TCELL9:OUT10.TMIN | PCIE.TRNRDLLPDATA18 |
| TCELL9:OUT11.TMIN | PCIE.TRNRDLLPDATA19 |
| TCELL9:OUT12.TMIN | PCIE.CFGMSGRECEIVEDPMPME |
| TCELL9:OUT13.TMIN | PCIE.CFGMSGRECEIVEDPMETOACK |
| TCELL9:OUT14.TMIN | PCIE.CFGMSGRECEIVEDPMETO |
| TCELL9:OUT15.TMIN | PCIE.CFGMSGRECEIVEDSETSLOTPOWERLIMIT |
| TCELL9:OUT16.TMIN | PCIE.CFGVCTCVCMAP0 |
| TCELL9:OUT17.TMIN | PCIE.CFGVCTCVCMAP1 |
| TCELL9:OUT18.TMIN | PCIE.CFGVCTCVCMAP2 |
| TCELL9:OUT19.TMIN | PCIE.CFGVCTCVCMAP3 |
| TCELL9:OUT20.TMIN | PCIE.DBGVECA3 |
| TCELL9:OUT21.TMIN | PCIE.LNKCLKEN |
| TCELL9:OUT22.TMIN | PCIE.CFGPMCSRPOWERSTATE1 |
| TCELL9:OUT23.TMIN | PCIE.CFGPMCSRPOWERSTATE0 |
| TCELL10:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA12 |
| TCELL10:IMUX.IMUX1.DELAY | PCIE.PIPERX2DATA4 |
| TCELL10:IMUX.IMUX2.DELAY | PCIE.CFGERRECRCN |
| TCELL10:IMUX.IMUX3.DELAY | PCIE.PIPERX2DATA0 |
| TCELL10:IMUX.IMUX4.DELAY | PCIE.CFGERRCPLTIMEOUTN |
| TCELL10:IMUX.IMUX5.DELAY | PCIE.PIPERX2DATA1 |
| TCELL10:IMUX.IMUX6.DELAY | PCIE.CFGERRCPLABORTN |
| TCELL10:IMUX.IMUX7.DELAY | PCIE.PIPERX6DATA2 |
| TCELL10:IMUX.IMUX8.DELAY | PCIE.CFGERRCPLUNEXPECTN |
| TCELL10:IMUX.IMUX9.DELAY | PCIE.PIPERX2DATA5 |
| TCELL10:IMUX.IMUX10.DELAY | PCIE.CFGERRTLPCPLHEADER18 |
| TCELL10:IMUX.IMUX11.DELAY | PCIE.PIPERX6DATA0 |
| TCELL10:IMUX.IMUX12.DELAY | PCIE.CFGERRTLPCPLHEADER19 |
| TCELL10:IMUX.IMUX13.DELAY | PCIE.PIPERX6DATA1 |
| TCELL10:IMUX.IMUX14.DELAY | PCIE.CFGERRTLPCPLHEADER20 |
| TCELL10:IMUX.IMUX15.DELAY | PCIE.PIPERX2DATA2 |
| TCELL10:IMUX.IMUX16.DELAY | PCIE.CFGERRTLPCPLHEADER21 |
| TCELL10:IMUX.IMUX17.DELAY | PCIE.PIPERX6DATA4 |
| TCELL10:IMUX.IMUX19.DELAY | PCIE.PIPERX2DATA3 |
| TCELL10:IMUX.IMUX21.DELAY | PCIE.PIPERX6DATA5 |
| TCELL10:IMUX.IMUX23.DELAY | PCIE.PIPERX6DATA3 |
| TCELL10:OUT0.TMIN | PCIE.TRNFCPH5 |
| TCELL10:OUT1.TMIN | PCIE.TRNFCPH6 |
| TCELL10:OUT2.TMIN | PCIE.TRNFCPH7 |
| TCELL10:OUT3.TMIN | PCIE.TRNFCPD0 |
| TCELL10:OUT4.TMIN | PCIE.MIMTXWADDR4 |
| TCELL10:OUT5.TMIN | PCIE.MIMTXWADDR5 |
| TCELL10:OUT6.TMIN | PCIE.MIMTXWADDR6 |
| TCELL10:OUT7.TMIN | PCIE.MIMTXWADDR7 |
| TCELL10:OUT8.TMIN | PCIE.TRNRDLLPDATA12 |
| TCELL10:OUT9.TMIN | PCIE.TRNRDLLPDATA13 |
| TCELL10:OUT10.TMIN | PCIE.TRNRDLLPDATA14 |
| TCELL10:OUT11.TMIN | PCIE.TRNRDLLPDATA15 |
| TCELL10:OUT12.TMIN | PCIE.CFGMSGRECEIVEDASSERTINTC |
| TCELL10:OUT13.TMIN | PCIE.CFGMSGRECEIVEDDEASSERTINTC |
| TCELL10:OUT14.TMIN | PCIE.CFGMSGRECEIVEDASSERTINTD |
| TCELL10:OUT15.TMIN | PCIE.CFGMSGRECEIVEDDEASSERTINTD |
| TCELL10:OUT16.TMIN | PCIE.CFGDEVCONTROL2CPLTIMEOUTDIS |
| TCELL10:OUT17.TMIN | PCIE.CFGSLOTCONTROLELECTROMECHILCTLPULSE |
| TCELL10:OUT18.TMIN | PCIE.CFGAERECRCCHECKEN |
| TCELL10:OUT19.TMIN | PCIE.CFGAERECRCGENEN |
| TCELL10:OUT20.TMIN | PCIE.DRPDO15 |
| TCELL10:OUT21.TMIN | PCIE.DBGVECA0 |
| TCELL10:OUT22.TMIN | PCIE.DBGVECA1 |
| TCELL10:OUT23.TMIN | PCIE.DBGVECA2 |
| TCELL11:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA11 |
| TCELL11:IMUX.IMUX1.DELAY | PCIE.PIPERX2DATA6 |
| TCELL11:IMUX.IMUX2.DELAY | PCIE.CFGWRENN |
| TCELL11:IMUX.IMUX3.DELAY | PCIE.PIPERX2DATA8 |
| TCELL11:IMUX.IMUX4.DELAY | PCIE.CFGRDENN |
| TCELL11:IMUX.IMUX5.DELAY | PCIE.PIPERX2DATA9 |
| TCELL11:IMUX.IMUX6.DELAY | PCIE.CFGERRCORN |
| TCELL11:IMUX.IMUX7.DELAY | PCIE.PIPERX2DATA10 |
| TCELL11:IMUX.IMUX8.DELAY | PCIE.CFGERRURN |
| TCELL11:IMUX.IMUX9.DELAY | PCIE.PIPERX2DATA7 |
| TCELL11:IMUX.IMUX10.DELAY | PCIE.CFGERRTLPCPLHEADER14 |
| TCELL11:IMUX.IMUX11.DELAY | PCIE.PIPERX6DATA8 |
| TCELL11:IMUX.IMUX12.DELAY | PCIE.CFGERRTLPCPLHEADER15 |
| TCELL11:IMUX.IMUX13.DELAY | PCIE.PIPERX6DATA9 |
| TCELL11:IMUX.IMUX14.DELAY | PCIE.CFGERRTLPCPLHEADER16 |
| TCELL11:IMUX.IMUX15.DELAY | PCIE.PIPERX2DATA11 |
| TCELL11:IMUX.IMUX16.DELAY | PCIE.CFGERRTLPCPLHEADER17 |
| TCELL11:IMUX.IMUX17.DELAY | PCIE.PIPERX6DATA6 |
| TCELL11:IMUX.IMUX19.DELAY | PCIE.PIPERX6DATA10 |
| TCELL11:IMUX.IMUX21.DELAY | PCIE.PIPERX6DATA7 |
| TCELL11:IMUX.IMUX23.DELAY | PCIE.PIPERX6DATA11 |
| TCELL11:OUT0.TMIN | PCIE.TRNFCPH1 |
| TCELL11:OUT1.TMIN | PCIE.TRNFCPH2 |
| TCELL11:OUT2.TMIN | PCIE.TRNFCPH3 |
| TCELL11:OUT3.TMIN | PCIE.TRNFCPH4 |
| TCELL11:OUT4.TMIN | PCIE.MIMTXWADDR0 |
| TCELL11:OUT5.TMIN | PCIE.MIMTXWADDR1 |
| TCELL11:OUT6.TMIN | PCIE.MIMTXWADDR2 |
| TCELL11:OUT7.TMIN | PCIE.MIMTXWADDR3 |
| TCELL11:OUT8.TMIN | PCIE.TRNRDLLPDATA8 |
| TCELL11:OUT9.TMIN | PCIE.TRNRDLLPDATA9 |
| TCELL11:OUT10.TMIN | PCIE.TRNRDLLPDATA10 |
| TCELL11:OUT11.TMIN | PCIE.TRNRDLLPDATA11 |
| TCELL11:OUT12.TMIN | PCIE.CFGMSGRECEIVEDASSERTINTA |
| TCELL11:OUT13.TMIN | PCIE.CFGMSGRECEIVEDDEASSERTINTA |
| TCELL11:OUT14.TMIN | PCIE.CFGMSGRECEIVEDASSERTINTB |
| TCELL11:OUT15.TMIN | PCIE.CFGMSGRECEIVEDDEASSERTINTB |
| TCELL11:OUT16.TMIN | PCIE.CFGDEVCONTROL2CPLTIMEOUTVAL0 |
| TCELL11:OUT17.TMIN | PCIE.CFGDEVCONTROL2CPLTIMEOUTVAL1 |
| TCELL11:OUT18.TMIN | PCIE.PIPERX2POLARITY |
| TCELL11:OUT19.TMIN | PCIE.CFGDEVCONTROL2CPLTIMEOUTVAL2 |
| TCELL11:OUT20.TMIN | PCIE.CFGDEVCONTROL2CPLTIMEOUTVAL3 |
| TCELL11:OUT21.TMIN | PCIE.DRPDO13 |
| TCELL11:OUT22.TMIN | PCIE.PIPERX6POLARITY |
| TCELL11:OUT23.TMIN | PCIE.DRPDO14 |
| TCELL12:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA8 |
| TCELL12:IMUX.IMUX1.DELAY | PCIE.PIPERX2CHARISK1 |
| TCELL12:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA9 |
| TCELL12:IMUX.IMUX3.DELAY | PCIE.PIPERX6DATA13 |
| TCELL12:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA10 |
| TCELL12:IMUX.IMUX5.DELAY | PCIE.PIPERX2DATA12 |
| TCELL12:IMUX.IMUX6.DELAY | PCIE.CFGDWADDR8 |
| TCELL12:IMUX.IMUX7.DELAY | PCIE.PIPERX2DATA13 |
| TCELL12:IMUX.IMUX8.DELAY | PCIE.CFGDWADDR9 |
| TCELL12:IMUX.IMUX9.DELAY | PCIE.PIPERX2DATA15 |
| TCELL12:IMUX.IMUX10.DELAY | PCIE.CFGWRRW1CASRWN |
| TCELL12:IMUX.IMUX11.DELAY | PCIE.PIPERX2DATA14 |
| TCELL12:IMUX.IMUX12.DELAY | PCIE.CFGWRREADONLYN |
| TCELL12:IMUX.IMUX13.DELAY | PCIE.PIPERX6DATA12 |
| TCELL12:IMUX.IMUX14.DELAY | PCIE.CFGERRTLPCPLHEADER10 |
| TCELL12:IMUX.IMUX15.DELAY | PCIE.PIPERX6DATA14 |
| TCELL12:IMUX.IMUX16.DELAY | PCIE.CFGERRTLPCPLHEADER11 |
| TCELL12:IMUX.IMUX17.DELAY | PCIE.PIPERX6CHARISK1 |
| TCELL12:IMUX.IMUX18.DELAY | PCIE.CFGERRTLPCPLHEADER12 |
| TCELL12:IMUX.IMUX19.DELAY | PCIE.CFGERRTLPCPLHEADER13 |
| TCELL12:IMUX.IMUX21.DELAY | PCIE.PIPERX6DATA15 |
| TCELL12:OUT0.TMIN | PCIE.TRNRBARHITN5 |
| TCELL12:OUT1.TMIN | PCIE.TRNRBARHITN6 |
| TCELL12:OUT2.TMIN | PCIE.TRNLNKUPN |
| TCELL12:OUT3.TMIN | PCIE.TRNFCPH0 |
| TCELL12:OUT4.TMIN | PCIE.MIMTXWDATA65 |
| TCELL12:OUT5.TMIN | PCIE.MIMTXWDATA66 |
| TCELL12:OUT6.TMIN | PCIE.MIMTXWDATA67 |
| TCELL12:OUT7.TMIN | PCIE.MIMTXWDATA68 |
| TCELL12:OUT8.TMIN | PCIE.TRNRDLLPDATA4 |
| TCELL12:OUT9.TMIN | PCIE.TRNRDLLPDATA5 |
| TCELL12:OUT10.TMIN | PCIE.TRNRDLLPDATA6 |
| TCELL12:OUT11.TMIN | PCIE.TRNRDLLPDATA7 |
| TCELL12:OUT12.TMIN | PCIE.CFGMSGDATA15 |
| TCELL12:OUT13.TMIN | PCIE.CFGMSGRECEIVEDERRCOR |
| TCELL12:OUT14.TMIN | PCIE.CFGMSGRECEIVEDERRNONFATAL |
| TCELL12:OUT15.TMIN | PCIE.CFGMSGRECEIVEDERRFATAL |
| TCELL12:OUT16.TMIN | PCIE.CFGLINKCONTROLCLOCKPMEN |
| TCELL12:OUT17.TMIN | PCIE.CFGLINKCONTROLHWAUTOWIDTHDIS |
| TCELL12:OUT18.TMIN | PCIE.CFGLINKCONTROLBANDWIDTHINTEN |
| TCELL12:OUT19.TMIN | PCIE.CFGLINKCONTROLAUTOBANDWIDTHINTEN |
| TCELL12:OUT20.TMIN | PCIE.DRPDO12 |
| TCELL12:OUT21.TMIN | PCIE.CFGPMCSRPMEEN |
| TCELL12:OUT22.TMIN | PCIE.DBGVECB47 |
| TCELL12:OUT23.TMIN | PCIE.DBGVECB48 |
| TCELL13:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA4 |
| TCELL13:IMUX.IMUX1.DELAY | PCIE.PIPERX6CHANISALIGNED |
| TCELL13:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA5 |
| TCELL13:IMUX.IMUX3.DELAY | PCIE.MIMTXRDATA6 |
| TCELL13:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA7 |
| TCELL13:IMUX.IMUX5.DELAY | PCIE.MIMRXRDATA66 |
| TCELL13:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA67 |
| TCELL13:IMUX.IMUX7.DELAY | PCIE.TRNTDLLPDATA0 |
| TCELL13:IMUX.IMUX8.DELAY | PCIE.TRNTDLLPDATA1 |
| TCELL13:IMUX.IMUX9.DELAY | PCIE.CFGDWADDR4 |
| TCELL13:IMUX.IMUX10.DELAY | PCIE.CFGDWADDR5 |
| TCELL13:IMUX.IMUX11.DELAY | PCIE.CFGDWADDR6 |
| TCELL13:IMUX.IMUX12.DELAY | PCIE.CFGDWADDR7 |
| TCELL13:IMUX.IMUX13.DELAY | PCIE.CFGERRTLPCPLHEADER6 |
| TCELL13:IMUX.IMUX14.DELAY | PCIE.CFGERRTLPCPLHEADER7 |
| TCELL13:IMUX.IMUX15.DELAY | PCIE.PIPERX6CHARISK0 |
| TCELL13:IMUX.IMUX16.DELAY | PCIE.CFGERRTLPCPLHEADER8 |
| TCELL13:IMUX.IMUX17.DELAY | PCIE.CFGERRTLPCPLHEADER9 |
| TCELL13:IMUX.IMUX18.DELAY | PCIE.CFGDSN45 |
| TCELL13:IMUX.IMUX21.DELAY | PCIE.PIPERX2CHANISALIGNED |
| TCELL13:IMUX.IMUX23.DELAY | PCIE.PIPERX2CHARISK0 |
| TCELL13:OUT0.TMIN | PCIE.TRNRBARHITN1 |
| TCELL13:OUT1.TMIN | PCIE.TRNRBARHITN2 |
| TCELL13:OUT2.TMIN | PCIE.TRNRBARHITN3 |
| TCELL13:OUT3.TMIN | PCIE.TRNRBARHITN4 |
| TCELL13:OUT4.TMIN | PCIE.MIMTXWDATA61 |
| TCELL13:OUT5.TMIN | PCIE.MIMTXWDATA62 |
| TCELL13:OUT6.TMIN | PCIE.MIMTXWDATA63 |
| TCELL13:OUT7.TMIN | PCIE.MIMTXWDATA64 |
| TCELL13:OUT8.TMIN | PCIE.TRNRDLLPDATA0 |
| TCELL13:OUT9.TMIN | PCIE.TRNRDLLPDATA1 |
| TCELL13:OUT10.TMIN | PCIE.TRNRDLLPDATA2 |
| TCELL13:OUT11.TMIN | PCIE.TRNRDLLPDATA3 |
| TCELL13:OUT12.TMIN | PCIE.CFGMSGDATA11 |
| TCELL13:OUT13.TMIN | PCIE.CFGMSGDATA12 |
| TCELL13:OUT14.TMIN | PCIE.CFGMSGDATA13 |
| TCELL13:OUT15.TMIN | PCIE.CFGMSGDATA14 |
| TCELL13:OUT16.TMIN | PCIE.PIPETXDEEMPH |
| TCELL13:OUT17.TMIN | PCIE.CFGLINKCONTROLCOMMONCLOCK |
| TCELL13:OUT18.TMIN | PCIE.CFGLINKCONTROLEXTENDEDSYNC |
| TCELL13:OUT19.TMIN | PCIE.XILUNCONNOUT3 |
| TCELL13:OUT20.TMIN | PCIE.CFGPMCSRPMESTATUS |
| TCELL13:OUT21.TMIN | PCIE.DBGVECB44 |
| TCELL13:OUT22.TMIN | PCIE.DBGVECB45 |
| TCELL13:OUT23.TMIN | PCIE.DBGVECB46 |
| TCELL14:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA0 |
| TCELL14:IMUX.IMUX1.DELAY | PCIE.PIPERX6STATUS2 |
| TCELL14:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA1 |
| TCELL14:IMUX.IMUX3.DELAY | PCIE.PIPERX6STATUS0 |
| TCELL14:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA2 |
| TCELL14:IMUX.IMUX5.DELAY | PCIE.MIMTXRDATA3 |
| TCELL14:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA62 |
| TCELL14:IMUX.IMUX7.DELAY | PCIE.PIPERX6STATUS1 |
| TCELL14:IMUX.IMUX8.DELAY | PCIE.MIMRXRDATA63 |
| TCELL14:IMUX.IMUX9.DELAY | PCIE.MIMRXRDATA64 |
| TCELL14:IMUX.IMUX10.DELAY | PCIE.MIMRXRDATA65 |
| TCELL14:IMUX.IMUX11.DELAY | PCIE.PIPERX2PHYSTATUS |
| TCELL14:IMUX.IMUX12.DELAY | PCIE.PMVDIVIDE1 |
| TCELL14:IMUX.IMUX13.DELAY | PCIE.PLTRANSMITHOTRST |
| TCELL14:IMUX.IMUX14.DELAY | PCIE.CFGDI0 |
| TCELL14:IMUX.IMUX15.DELAY | PCIE.PIPERX6PHYSTATUS |
| TCELL14:IMUX.IMUX16.DELAY | PCIE.CFGDI1 |
| TCELL14:IMUX.IMUX17.DELAY | PCIE.CFGDWADDR2 |
| TCELL14:IMUX.IMUX18.DELAY | PCIE.CFGDWADDR3 |
| TCELL14:IMUX.IMUX19.DELAY | PCIE.PIPERX2STATUS1 |
| TCELL14:IMUX.IMUX21.DELAY | PCIE.PIPERX2STATUS2 |
| TCELL14:IMUX.IMUX23.DELAY | PCIE.PIPERX2STATUS0 |
| TCELL14:OUT0.TMIN | PCIE.TRNRSRCDSCN |
| TCELL14:OUT1.TMIN | PCIE.PIPETX2ELECIDLE |
| TCELL14:OUT2.TMIN | PCIE.TRNRECRCERRN |
| TCELL14:OUT3.TMIN | PCIE.TRNRERRFWDN |
| TCELL14:OUT4.TMIN | PCIE.TRNRBARHITN0 |
| TCELL14:OUT5.TMIN | PCIE.PIPETX6ELECIDLE |
| TCELL14:OUT6.TMIN | PCIE.MIMTXWDATA57 |
| TCELL14:OUT7.TMIN | PCIE.MIMTXWDATA58 |
| TCELL14:OUT8.TMIN | PCIE.MIMTXWDATA59 |
| TCELL14:OUT9.TMIN | PCIE.MIMTXWDATA60 |
| TCELL14:OUT10.TMIN | PCIE.TRNTDLLPDSTRDYN |
| TCELL14:OUT11.TMIN | PCIE.CFGMSGDATA8 |
| TCELL14:OUT12.TMIN | PCIE.CFGMSGDATA9 |
| TCELL14:OUT13.TMIN | PCIE.CFGMSGDATA10 |
| TCELL14:OUT14.TMIN | PCIE.XILUNCONNOUT1 |
| TCELL14:OUT15.TMIN | PCIE.PIPETXRCVRDET |
| TCELL14:OUT16.TMIN | PCIE.XILUNCONNOUT2 |
| TCELL14:OUT17.TMIN | PCIE.PIPETX6POWERDOWN0 |
| TCELL14:OUT18.TMIN | PCIE.DBGVECB41 |
| TCELL14:OUT19.TMIN | PCIE.PIPETX6POWERDOWN1 |
| TCELL14:OUT20.TMIN | PCIE.DBGVECB42 |
| TCELL14:OUT21.TMIN | PCIE.PIPETX2POWERDOWN0 |
| TCELL14:OUT22.TMIN | PCIE.DBGVECB43 |
| TCELL14:OUT23.TMIN | PCIE.PIPETX2POWERDOWN1 |
| TCELL15:IMUX.IMUX0.DELAY | PCIE.TRNRNPOKN |
| TCELL15:IMUX.IMUX1.DELAY | PCIE.TRNFCSEL0 |
| TCELL15:IMUX.IMUX2.DELAY | PCIE.TRNFCSEL1 |
| TCELL15:IMUX.IMUX3.DELAY | PCIE.TRNFCSEL2 |
| TCELL15:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA58 |
| TCELL15:IMUX.IMUX5.DELAY | PCIE.PIPERX6ELECIDLE |
| TCELL15:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA59 |
| TCELL15:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA60 |
| TCELL15:IMUX.IMUX8.DELAY | PCIE.MIMRXRDATA61 |
| TCELL15:IMUX.IMUX9.DELAY | PCIE.PMVDIVIDE0 |
| TCELL15:IMUX.IMUX10.DELAY | PCIE.CFGDI2 |
| TCELL15:IMUX.IMUX11.DELAY | PCIE.PIPERX6VALID |
| TCELL15:IMUX.IMUX12.DELAY | PCIE.CFGDI3 |
| TCELL15:IMUX.IMUX13.DELAY | PCIE.CFGDI4 |
| TCELL15:IMUX.IMUX14.DELAY | PCIE.CFGDI5 |
| TCELL15:IMUX.IMUX15.DELAY | PCIE.CFGBYTEENN2 |
| TCELL15:IMUX.IMUX16.DELAY | PCIE.CFGBYTEENN3 |
| TCELL15:IMUX.IMUX17.DELAY | PCIE.CFGDWADDR0 |
| TCELL15:IMUX.IMUX18.DELAY | PCIE.CFGDWADDR1 |
| TCELL15:IMUX.IMUX19.DELAY | PCIE.PIPERX2VALID |
| TCELL15:IMUX.IMUX20.DELAY | PCIE.CFGERRTLPCPLHEADER5 |
| TCELL15:IMUX.IMUX21.DELAY | PCIE.PIPERX2ELECIDLE |
| TCELL15:OUT0.TMIN | PCIE.TRNRREMN |
| TCELL15:OUT1.TMIN | PCIE.TRNRSOFN |
| TCELL15:OUT2.TMIN | PCIE.TRNREOFN |
| TCELL15:OUT3.TMIN | PCIE.TRNRSRCRDYN |
| TCELL15:OUT4.TMIN | PCIE.MIMTXWDATA53 |
| TCELL15:OUT5.TMIN | PCIE.MIMTXWDATA54 |
| TCELL15:OUT6.TMIN | PCIE.MIMTXWDATA55 |
| TCELL15:OUT7.TMIN | PCIE.MIMTXWDATA56 |
| TCELL15:OUT8.TMIN | PCIE.CFGMSGDATA4 |
| TCELL15:OUT9.TMIN | PCIE.CFGMSGDATA5 |
| TCELL15:OUT10.TMIN | PCIE.CFGMSGDATA6 |
| TCELL15:OUT11.TMIN | PCIE.CFGMSGDATA7 |
| TCELL15:OUT12.TMIN | PCIE.CFGLINKCONTROLRCB |
| TCELL15:OUT13.TMIN | PCIE.CFGLINKCONTROLLINKDISABLE |
| TCELL15:OUT14.TMIN | PCIE.CFGLINKCONTROLRETRAINLINK |
| TCELL15:OUT15.TMIN | PCIE.XILUNCONNOUT0 |
| TCELL15:OUT16.TMIN | PCIE.PIPETX2COMPLIANCE |
| TCELL15:OUT17.TMIN | PCIE.DBGVECB39 |
| TCELL15:OUT18.TMIN | PCIE.PIPETX2CHARISK0 |
| TCELL15:OUT19.TMIN | PCIE.PIPETX6CHARISK1 |
| TCELL15:OUT20.TMIN | PCIE.PIPETX6COMPLIANCE |
| TCELL15:OUT21.TMIN | PCIE.DBGVECB40 |
| TCELL15:OUT22.TMIN | PCIE.PIPETX6CHARISK0 |
| TCELL15:OUT23.TMIN | PCIE.PIPETX2CHARISK1 |
| TCELL16:IMUX.IMUX0.DELAY | PCIE.TRNTECRCGENN |
| TCELL16:IMUX.IMUX1.DELAY | PCIE.TRNTSTRN |
| TCELL16:IMUX.IMUX2.DELAY | PCIE.TRNTCFGGNTN |
| TCELL16:IMUX.IMUX3.DELAY | PCIE.TRNRDSTRDYN |
| TCELL16:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA54 |
| TCELL16:IMUX.IMUX5.DELAY | PCIE.MIMRXRDATA55 |
| TCELL16:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA56 |
| TCELL16:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA57 |
| TCELL16:IMUX.IMUX8.DELAY | PCIE.PMVSELECT2 |
| TCELL16:IMUX.IMUX9.DELAY | PCIE.CFGDI6 |
| TCELL16:IMUX.IMUX10.DELAY | PCIE.CFGDI7 |
| TCELL16:IMUX.IMUX11.DELAY | PCIE.CFGDI8 |
| TCELL16:IMUX.IMUX12.DELAY | PCIE.CFGDI9 |
| TCELL16:IMUX.IMUX13.DELAY | PCIE.CFGDI30 |
| TCELL16:IMUX.IMUX14.DELAY | PCIE.CFGDI31 |
| TCELL16:IMUX.IMUX15.DELAY | PCIE.CFGBYTEENN0 |
| TCELL16:IMUX.IMUX16.DELAY | PCIE.CFGBYTEENN1 |
| TCELL16:IMUX.IMUX17.DELAY | PCIE.CFGERRTLPCPLHEADER1 |
| TCELL16:IMUX.IMUX18.DELAY | PCIE.CFGERRTLPCPLHEADER2 |
| TCELL16:IMUX.IMUX19.DELAY | PCIE.CFGERRTLPCPLHEADER3 |
| TCELL16:IMUX.IMUX20.DELAY | PCIE.CFGERRTLPCPLHEADER4 |
| TCELL16:IMUX.IMUX21.DELAY | PCIE.CFGDSN44 |
| TCELL16:OUT0.TMIN | PCIE.TRNRD60 |
| TCELL16:OUT1.TMIN | PCIE.TRNRD61 |
| TCELL16:OUT2.TMIN | PCIE.PIPETX6DATA13 |
| TCELL16:OUT3.TMIN | PCIE.TRNRD62 |
| TCELL16:OUT4.TMIN | PCIE.TRNRD63 |
| TCELL16:OUT5.TMIN | PCIE.CFGMSGDATA0 |
| TCELL16:OUT6.TMIN | PCIE.PIPETX2DATA13 |
| TCELL16:OUT7.TMIN | PCIE.CFGMSGDATA1 |
| TCELL16:OUT8.TMIN | PCIE.CFGMSGDATA2 |
| TCELL16:OUT9.TMIN | PCIE.PIPETXRESET |
| TCELL16:OUT10.TMIN | PCIE.CFGMSGDATA3 |
| TCELL16:OUT11.TMIN | PCIE.CFGLINKCONTROLASPMCONTROL1 |
| TCELL16:OUT12.TMIN | PCIE.PLDBGVEC10 |
| TCELL16:OUT13.TMIN | PCIE.PLDBGVEC11 |
| TCELL16:OUT14.TMIN | PCIE.DBGVECB36 |
| TCELL16:OUT15.TMIN | PCIE.DBGVECB37 |
| TCELL16:OUT16.TMIN | PCIE.PIPETX2DATA12 |
| TCELL16:OUT17.TMIN | PCIE.PIPETX6DATA15 |
| TCELL16:OUT18.TMIN | PCIE.PIPETXRATE |
| TCELL16:OUT19.TMIN | PCIE.PIPETX6DATA14 |
| TCELL16:OUT20.TMIN | PCIE.PIPETX6DATA12 |
| TCELL16:OUT21.TMIN | PCIE.PIPETX2DATA15 |
| TCELL16:OUT22.TMIN | PCIE.DBGVECB38 |
| TCELL16:OUT23.TMIN | PCIE.PIPETX2DATA14 |
| TCELL17:IMUX.IMUX0.DELAY | PCIE.TRNTEOFN |
| TCELL17:IMUX.IMUX1.DELAY | PCIE.TRNTSRCRDYN |
| TCELL17:IMUX.IMUX2.DELAY | PCIE.TRNTSRCDSCN |
| TCELL17:IMUX.IMUX3.DELAY | PCIE.TRNTERRFWDN |
| TCELL17:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA50 |
| TCELL17:IMUX.IMUX5.DELAY | PCIE.MIMRXRDATA51 |
| TCELL17:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA52 |
| TCELL17:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA53 |
| TCELL17:IMUX.IMUX8.DELAY | PCIE.PMVSELECT1 |
| TCELL17:IMUX.IMUX9.DELAY | PCIE.CFGDI10 |
| TCELL17:IMUX.IMUX10.DELAY | PCIE.CFGDI11 |
| TCELL17:IMUX.IMUX11.DELAY | PCIE.CFGDI12 |
| TCELL17:IMUX.IMUX12.DELAY | PCIE.CFGDI13 |
| TCELL17:IMUX.IMUX13.DELAY | PCIE.CFGDI26 |
| TCELL17:IMUX.IMUX14.DELAY | PCIE.CFGDI27 |
| TCELL17:IMUX.IMUX15.DELAY | PCIE.CFGDI28 |
| TCELL17:IMUX.IMUX16.DELAY | PCIE.CFGDI29 |
| TCELL17:IMUX.IMUX17.DELAY | PCIE.CFGERRAERHEADERLOG125 |
| TCELL17:IMUX.IMUX18.DELAY | PCIE.CFGERRAERHEADERLOG126 |
| TCELL17:IMUX.IMUX19.DELAY | PCIE.CFGERRAERHEADERLOG127 |
| TCELL17:IMUX.IMUX20.DELAY | PCIE.CFGERRTLPCPLHEADER0 |
| TCELL17:IMUX.IMUX21.DELAY | PCIE.CFGDSN43 |
| TCELL17:OUT0.TMIN | PCIE.TRNRD58 |
| TCELL17:OUT1.TMIN | PCIE.PIPETX2DATA11 |
| TCELL17:OUT2.TMIN | PCIE.PIPETX6DATA8 |
| TCELL17:OUT3.TMIN | PCIE.TRNRD59 |
| TCELL17:OUT4.TMIN | PCIE.CFGINTERRUPTDO7 |
| TCELL17:OUT5.TMIN | PCIE.PIPETX6DATA11 |
| TCELL17:OUT6.TMIN | PCIE.PIPETX2DATA8 |
| TCELL17:OUT7.TMIN | PCIE.CFGINTERRUPTMSIXENABLE |
| TCELL17:OUT8.TMIN | PCIE.CFGINTERRUPTMSIXFM |
| TCELL17:OUT9.TMIN | PCIE.CFGMSGRECEIVED |
| TCELL17:OUT10.TMIN | PCIE.CFGLINKCONTROLASPMCONTROL0 |
| TCELL17:OUT11.TMIN | PCIE.PLDBGVEC8 |
| TCELL17:OUT12.TMIN | PCIE.PLDBGVEC9 |
| TCELL17:OUT13.TMIN | PCIE.DBGVECB33 |
| TCELL17:OUT14.TMIN | PCIE.DBGVECB34 |
| TCELL17:OUT15.TMIN | PCIE.DBGVECB35 |
| TCELL17:OUT16.TMIN | PCIE.PIPETX2DATA7 |
| TCELL17:OUT17.TMIN | PCIE.PIPETX6DATA10 |
| TCELL17:OUT18.TMIN | PCIE.PIPETX2DATA6 |
| TCELL17:OUT19.TMIN | PCIE.PIPETX6DATA9 |
| TCELL17:OUT20.TMIN | PCIE.PIPETX6DATA7 |
| TCELL17:OUT21.TMIN | PCIE.PIPETX2DATA10 |
| TCELL17:OUT22.TMIN | PCIE.PIPETX6DATA6 |
| TCELL17:OUT23.TMIN | PCIE.PIPETX2DATA9 |
| TCELL18:IMUX.IMUX0.DELAY | PCIE.TRNTD62 |
| TCELL18:IMUX.IMUX1.DELAY | PCIE.TRNTD63 |
| TCELL18:IMUX.IMUX2.DELAY | PCIE.TRNTREMN |
| TCELL18:IMUX.IMUX3.DELAY | PCIE.TRNTSOFN |
| TCELL18:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA46 |
| TCELL18:IMUX.IMUX5.DELAY | PCIE.MIMRXRDATA47 |
| TCELL18:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA48 |
| TCELL18:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA49 |
| TCELL18:IMUX.IMUX8.DELAY | PCIE.PMVSELECT0 |
| TCELL18:IMUX.IMUX9.DELAY | PCIE.CFGDI14 |
| TCELL18:IMUX.IMUX10.DELAY | PCIE.CFGDI15 |
| TCELL18:IMUX.IMUX11.DELAY | PCIE.CFGDI16 |
| TCELL18:IMUX.IMUX12.DELAY | PCIE.CFGDI17 |
| TCELL18:IMUX.IMUX13.DELAY | PCIE.CFGDI22 |
| TCELL18:IMUX.IMUX14.DELAY | PCIE.CFGDI23 |
| TCELL18:IMUX.IMUX15.DELAY | PCIE.CFGDI24 |
| TCELL18:IMUX.IMUX16.DELAY | PCIE.CFGDI25 |
| TCELL18:IMUX.IMUX17.DELAY | PCIE.CFGERRAERHEADERLOG121 |
| TCELL18:IMUX.IMUX18.DELAY | PCIE.CFGERRAERHEADERLOG122 |
| TCELL18:IMUX.IMUX19.DELAY | PCIE.CFGERRAERHEADERLOG123 |
| TCELL18:IMUX.IMUX20.DELAY | PCIE.CFGERRAERHEADERLOG124 |
| TCELL18:IMUX.IMUX21.DELAY | PCIE.CFGDSN42 |
| TCELL18:OUT0.TMIN | PCIE.TRNRD56 |
| TCELL18:OUT1.TMIN | PCIE.PIPETX2DATA3 |
| TCELL18:OUT2.TMIN | PCIE.PIPETX6DATA4 |
| TCELL18:OUT3.TMIN | PCIE.TRNRD57 |
| TCELL18:OUT4.TMIN | PCIE.CFGINTERRUPTDO3 |
| TCELL18:OUT5.TMIN | PCIE.PIPETX6DATA3 |
| TCELL18:OUT6.TMIN | PCIE.PIPETX2DATA4 |
| TCELL18:OUT7.TMIN | PCIE.MIMRXRCE |
| TCELL18:OUT8.TMIN | PCIE.CFGINTERRUPTDO4 |
| TCELL18:OUT9.TMIN | PCIE.CFGINTERRUPTDO5 |
| TCELL18:OUT10.TMIN | PCIE.CFGINTERRUPTDO6 |
| TCELL18:OUT11.TMIN | PCIE.CFGLINKSTATUSAUTOBANDWIDTHSTATUS |
| TCELL18:OUT12.TMIN | PCIE.PLDBGVEC6 |
| TCELL18:OUT13.TMIN | PCIE.PLDBGVEC7 |
| TCELL18:OUT14.TMIN | PCIE.DBGVECB31 |
| TCELL18:OUT15.TMIN | PCIE.DBGVECB32 |
| TCELL18:OUT16.TMIN | PCIE.PIPETX2DATA0 |
| TCELL18:OUT17.TMIN | PCIE.PIPETX6DATA1 |
| TCELL18:OUT18.TMIN | PCIE.PIPETX2DATA5 |
| TCELL18:OUT19.TMIN | PCIE.PIPETX6DATA2 |
| TCELL18:OUT20.TMIN | PCIE.PIPETX6DATA0 |
| TCELL18:OUT21.TMIN | PCIE.PIPETX2DATA1 |
| TCELL18:OUT22.TMIN | PCIE.PIPETX6DATA5 |
| TCELL18:OUT23.TMIN | PCIE.PIPETX2DATA2 |
| TCELL19:IMUX.IMUX0.DELAY | PCIE.TRNTD58 |
| TCELL19:IMUX.IMUX1.DELAY | PCIE.TRNTD59 |
| TCELL19:IMUX.IMUX2.DELAY | PCIE.TRNTD60 |
| TCELL19:IMUX.IMUX3.DELAY | PCIE.TRNTD61 |
| TCELL19:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA42 |
| TCELL19:IMUX.IMUX5.DELAY | PCIE.MIMRXRDATA43 |
| TCELL19:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA44 |
| TCELL19:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA45 |
| TCELL19:IMUX.IMUX8.DELAY | PCIE.PMVENABLEN |
| TCELL19:IMUX.IMUX9.DELAY | PCIE.CFGDI18 |
| TCELL19:IMUX.IMUX10.DELAY | PCIE.CFGDI19 |
| TCELL19:IMUX.IMUX11.DELAY | PCIE.CFGDI20 |
| TCELL19:IMUX.IMUX12.DELAY | PCIE.CFGDI21 |
| TCELL19:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG117 |
| TCELL19:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG118 |
| TCELL19:IMUX.IMUX15.DELAY | PCIE.CFGERRAERHEADERLOG119 |
| TCELL19:IMUX.IMUX16.DELAY | PCIE.CFGERRAERHEADERLOG120 |
| TCELL19:IMUX.IMUX17.DELAY | PCIE.CFGDSN38 |
| TCELL19:IMUX.IMUX18.DELAY | PCIE.CFGDSN39 |
| TCELL19:IMUX.IMUX19.DELAY | PCIE.CFGDSN40 |
| TCELL19:IMUX.IMUX20.DELAY | PCIE.CFGDSN41 |
| TCELL19:IMUX.IMUX21.DELAY | PCIE.DRPDI13 |
| TCELL19:OUT0.TMIN | PCIE.TRNRD52 |
| TCELL19:OUT1.TMIN | PCIE.TRNRD53 |
| TCELL19:OUT2.TMIN | PCIE.TRNRD54 |
| TCELL19:OUT3.TMIN | PCIE.TRNRD55 |
| TCELL19:OUT4.TMIN | PCIE.MIMTXWDATA49 |
| TCELL19:OUT5.TMIN | PCIE.MIMTXWDATA50 |
| TCELL19:OUT6.TMIN | PCIE.MIMTXWDATA51 |
| TCELL19:OUT7.TMIN | PCIE.MIMTXWDATA52 |
| TCELL19:OUT8.TMIN | PCIE.MIMRXRADDR10 |
| TCELL19:OUT9.TMIN | PCIE.MIMRXRADDR11 |
| TCELL19:OUT10.TMIN | PCIE.MIMRXRADDR12 |
| TCELL19:OUT11.TMIN | PCIE.MIMRXREN |
| TCELL19:OUT12.TMIN | PCIE.CFGINTERRUPTMSIENABLE |
| TCELL19:OUT13.TMIN | PCIE.CFGINTERRUPTDO0 |
| TCELL19:OUT14.TMIN | PCIE.CFGINTERRUPTDO1 |
| TCELL19:OUT15.TMIN | PCIE.CFGINTERRUPTDO2 |
| TCELL19:OUT16.TMIN | PCIE.CFGLINKSTATUSNEGOTIATEDWIDTH3 |
| TCELL19:OUT17.TMIN | PCIE.CFGLINKSTATUSLINKTRAINING |
| TCELL19:OUT18.TMIN | PCIE.CFGLINKSTATUSDLLACTIVE |
| TCELL19:OUT19.TMIN | PCIE.CFGLINKSTATUSBANDWITHSTATUS |
| TCELL19:OUT20.TMIN | PCIE.DRPDO10 |
| TCELL19:OUT21.TMIN | PCIE.DRPDO11 |
| TCELL19:OUT22.TMIN | PCIE.PLDBGVEC5 |
| TCELL19:OUT23.TMIN | PCIE.DBGVECB30 |
| TCELL20:IMUX.CLK0 | PCIE.USERCLKPREBUF |
| TCELL20:IMUX.CTRL0 | PCIE.SYSRSTN |
| TCELL20:IMUX.CTRL1 | PCIE.CMRSTN |
| TCELL20:IMUX.IMUX0.DELAY | PCIE.PLDIRECTEDLINKCHANGE0 |
| TCELL20:IMUX.IMUX1.DELAY | PCIE.PIPERX1DATA4 |
| TCELL20:IMUX.IMUX2.DELAY | PCIE.CFGERRAERHEADERLOG37 |
| TCELL20:IMUX.IMUX3.DELAY | PCIE.PIPERX1DATA0 |
| TCELL20:IMUX.IMUX4.DELAY | PCIE.CFGERRAERHEADERLOG38 |
| TCELL20:IMUX.IMUX5.DELAY | PCIE.PIPERX1DATA1 |
| TCELL20:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG39 |
| TCELL20:IMUX.IMUX7.DELAY | PCIE.PIPERX5DATA2 |
| TCELL20:IMUX.IMUX8.DELAY | PCIE.CFGERRAERHEADERLOG40 |
| TCELL20:IMUX.IMUX9.DELAY | PCIE.PIPERX1DATA5 |
| TCELL20:IMUX.IMUX10.DELAY | PCIE.CFGDSBUSNUMBER4 |
| TCELL20:IMUX.IMUX11.DELAY | PCIE.PIPERX5DATA0 |
| TCELL20:IMUX.IMUX12.DELAY | PCIE.CFGDSBUSNUMBER5 |
| TCELL20:IMUX.IMUX13.DELAY | PCIE.PIPERX5DATA1 |
| TCELL20:IMUX.IMUX14.DELAY | PCIE.CFGDSBUSNUMBER6 |
| TCELL20:IMUX.IMUX15.DELAY | PCIE.PIPERX1DATA2 |
| TCELL20:IMUX.IMUX16.DELAY | PCIE.CFGDSBUSNUMBER7 |
| TCELL20:IMUX.IMUX17.DELAY | PCIE.PIPERX5DATA4 |
| TCELL20:IMUX.IMUX19.DELAY | PCIE.PIPERX1DATA3 |
| TCELL20:IMUX.IMUX21.DELAY | PCIE.PIPERX5DATA5 |
| TCELL20:IMUX.IMUX23.DELAY | PCIE.PIPERX5DATA3 |
| TCELL20:OUT0.TMIN | PCIE.PLSELLNKRATE |
| TCELL20:OUT1.TMIN | PCIE.PLSELLNKWIDTH0 |
| TCELL20:OUT2.TMIN | PCIE.PLSELLNKWIDTH1 |
| TCELL20:OUT3.TMIN | PCIE.PLLTSSMSTATE0 |
| TCELL20:OUT4.TMIN | PCIE.PLLTSSMSTATE1 |
| TCELL20:OUT5.TMIN | PCIE.PLLTSSMSTATE2 |
| TCELL20:OUT6.TMIN | PCIE.PLLTSSMSTATE3 |
| TCELL20:OUT7.TMIN | PCIE.PLLTSSMSTATE4 |
| TCELL20:OUT8.TMIN | PCIE.PLLTSSMSTATE5 |
| TCELL20:OUT9.TMIN | PCIE.PLLANEREVERSALMODE0 |
| TCELL20:OUT10.TMIN | PCIE.PLLANEREVERSALMODE1 |
| TCELL20:OUT11.TMIN | PCIE.PLPHYLNKUPN |
| TCELL20:OUT12.TMIN | PCIE.PLTXPMSTATE0 |
| TCELL20:OUT13.TMIN | PCIE.PLTXPMSTATE1 |
| TCELL20:OUT14.TMIN | PCIE.PLTXPMSTATE2 |
| TCELL20:OUT15.TMIN | PCIE.PLRXPMSTATE0 |
| TCELL20:OUT16.TMIN | PCIE.TRNFCCPLD1 |
| TCELL20:OUT17.TMIN | PCIE.TRNFCCPLD2 |
| TCELL20:OUT18.TMIN | PCIE.TRNFCCPLD3 |
| TCELL20:OUT19.TMIN | PCIE.TRNFCCPLD4 |
| TCELL20:OUT20.TMIN | PCIE.MIMRXWDATA15 |
| TCELL20:OUT21.TMIN | PCIE.DBGVECA30 |
| TCELL20:OUT22.TMIN | PCIE.DBGVECA31 |
| TCELL20:OUT23.TMIN | PCIE.DBGVECA32 |
| TCELL21:IMUX.CTRL0 | PCIE.CMSTICKYRSTN |
| TCELL21:IMUX.CTRL1 | PCIE.FUNCLVLRSTN |
| TCELL21:IMUX.IMUX0.DELAY | PCIE.PLDIRECTEDLINKCHANGE1 |
| TCELL21:IMUX.IMUX1.DELAY | PCIE.PIPERX1DATA6 |
| TCELL21:IMUX.IMUX2.DELAY | PCIE.CFGERRAERHEADERLOG41 |
| TCELL21:IMUX.IMUX3.DELAY | PCIE.PIPERX1DATA8 |
| TCELL21:IMUX.IMUX4.DELAY | PCIE.CFGERRAERHEADERLOG42 |
| TCELL21:IMUX.IMUX5.DELAY | PCIE.PIPERX1DATA9 |
| TCELL21:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG43 |
| TCELL21:IMUX.IMUX7.DELAY | PCIE.PIPERX1DATA10 |
| TCELL21:IMUX.IMUX8.DELAY | PCIE.CFGERRAERHEADERLOG44 |
| TCELL21:IMUX.IMUX9.DELAY | PCIE.PIPERX1DATA7 |
| TCELL21:IMUX.IMUX10.DELAY | PCIE.CFGDSDEVICENUMBER0 |
| TCELL21:IMUX.IMUX11.DELAY | PCIE.PIPERX5DATA8 |
| TCELL21:IMUX.IMUX12.DELAY | PCIE.CFGDSDEVICENUMBER1 |
| TCELL21:IMUX.IMUX13.DELAY | PCIE.PIPERX5DATA9 |
| TCELL21:IMUX.IMUX14.DELAY | PCIE.CFGDSDEVICENUMBER2 |
| TCELL21:IMUX.IMUX15.DELAY | PCIE.PIPERX1DATA11 |
| TCELL21:IMUX.IMUX16.DELAY | PCIE.CFGDSDEVICENUMBER3 |
| TCELL21:IMUX.IMUX17.DELAY | PCIE.PIPERX5DATA6 |
| TCELL21:IMUX.IMUX19.DELAY | PCIE.PIPERX5DATA10 |
| TCELL21:IMUX.IMUX21.DELAY | PCIE.PIPERX5DATA7 |
| TCELL21:IMUX.IMUX23.DELAY | PCIE.PIPERX5DATA11 |
| TCELL21:OUT0.TMIN | PCIE.PLRXPMSTATE1 |
| TCELL21:OUT1.TMIN | PCIE.PLLINKUPCFGCAP |
| TCELL21:OUT2.TMIN | PCIE.PLLINKGEN2CAP |
| TCELL21:OUT3.TMIN | PCIE.PLLINKPARTNERGEN2SUPPORTED |
| TCELL21:OUT4.TMIN | PCIE.TRNFCCPLD5 |
| TCELL21:OUT5.TMIN | PCIE.TRNFCCPLD6 |
| TCELL21:OUT6.TMIN | PCIE.TRNFCCPLD7 |
| TCELL21:OUT7.TMIN | PCIE.TRNFCCPLD8 |
| TCELL21:OUT8.TMIN | PCIE.MIMRXWDATA16 |
| TCELL21:OUT9.TMIN | PCIE.MIMRXWDATA17 |
| TCELL21:OUT10.TMIN | PCIE.MIMRXWDATA18 |
| TCELL21:OUT11.TMIN | PCIE.MIMRXWDATA19 |
| TCELL21:OUT12.TMIN | PCIE.LL2BADDLLPERRN |
| TCELL21:OUT13.TMIN | PCIE.LL2REPLAYROERRN |
| TCELL21:OUT14.TMIN | PCIE.LL2REPLAYTOERRN |
| TCELL21:OUT15.TMIN | PCIE.PMVOUT |
| TCELL21:OUT16.TMIN | PCIE.CFGCOMMANDINTERRUPTDISABLE |
| TCELL21:OUT17.TMIN | PCIE.CFGDEVSTATUSCORRERRDETECTED |
| TCELL21:OUT18.TMIN | PCIE.PIPERX1POLARITY |
| TCELL21:OUT19.TMIN | PCIE.DBGVECB60 |
| TCELL21:OUT20.TMIN | PCIE.DBGVECA33 |
| TCELL21:OUT21.TMIN | PCIE.DBGVECA34 |
| TCELL21:OUT22.TMIN | PCIE.PIPERX5POLARITY |
| TCELL21:OUT23.TMIN | PCIE.DBGVECA35 |
| TCELL22:IMUX.CTRL0 | PCIE.TLRSTN |
| TCELL22:IMUX.CTRL1 | PCIE.DLRSTN |
| TCELL22:IMUX.IMUX0.DELAY | PCIE.PLDIRECTEDLINKWIDTH0 |
| TCELL22:IMUX.IMUX1.DELAY | PCIE.PIPERX1CHARISK1 |
| TCELL22:IMUX.IMUX2.DELAY | PCIE.PLDIRECTEDLINKWIDTH1 |
| TCELL22:IMUX.IMUX3.DELAY | PCIE.PIPERX5DATA13 |
| TCELL22:IMUX.IMUX4.DELAY | PCIE.PLDIRECTEDLINKSPEED |
| TCELL22:IMUX.IMUX5.DELAY | PCIE.PIPERX1DATA12 |
| TCELL22:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG45 |
| TCELL22:IMUX.IMUX7.DELAY | PCIE.PIPERX1DATA13 |
| TCELL22:IMUX.IMUX8.DELAY | PCIE.CFGERRAERHEADERLOG46 |
| TCELL22:IMUX.IMUX9.DELAY | PCIE.PIPERX1DATA15 |
| TCELL22:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG47 |
| TCELL22:IMUX.IMUX11.DELAY | PCIE.PIPERX1DATA14 |
| TCELL22:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG48 |
| TCELL22:IMUX.IMUX13.DELAY | PCIE.PIPERX5DATA12 |
| TCELL22:IMUX.IMUX14.DELAY | PCIE.CFGDSDEVICENUMBER4 |
| TCELL22:IMUX.IMUX15.DELAY | PCIE.PIPERX5DATA14 |
| TCELL22:IMUX.IMUX16.DELAY | PCIE.CFGDSFUNCTIONNUMBER0 |
| TCELL22:IMUX.IMUX17.DELAY | PCIE.PIPERX5CHARISK1 |
| TCELL22:IMUX.IMUX18.DELAY | PCIE.CFGDSFUNCTIONNUMBER1 |
| TCELL22:IMUX.IMUX19.DELAY | PCIE.CFGDSFUNCTIONNUMBER2 |
| TCELL22:IMUX.IMUX21.DELAY | PCIE.PIPERX5DATA15 |
| TCELL22:OUT0.TMIN | PCIE.PLINITIALLINKWIDTH0 |
| TCELL22:OUT1.TMIN | PCIE.PLINITIALLINKWIDTH1 |
| TCELL22:OUT2.TMIN | PCIE.PLINITIALLINKWIDTH2 |
| TCELL22:OUT3.TMIN | PCIE.TRNTDSTRDYN |
| TCELL22:OUT4.TMIN | PCIE.TRNFCCPLD9 |
| TCELL22:OUT5.TMIN | PCIE.TRNFCCPLD10 |
| TCELL22:OUT6.TMIN | PCIE.TRNFCCPLD11 |
| TCELL22:OUT7.TMIN | PCIE.MIMTXWDATA0 |
| TCELL22:OUT8.TMIN | PCIE.MIMRXWDATA20 |
| TCELL22:OUT9.TMIN | PCIE.MIMRXWDATA21 |
| TCELL22:OUT10.TMIN | PCIE.MIMRXWDATA22 |
| TCELL22:OUT11.TMIN | PCIE.MIMRXWDATA23 |
| TCELL22:OUT12.TMIN | PCIE.USERRSTN |
| TCELL22:OUT13.TMIN | PCIE.PLRECEIVEDHOTRST |
| TCELL22:OUT14.TMIN | PCIE.RECEIVEDFUNCLVLRSTN |
| TCELL22:OUT15.TMIN | PCIE.CFGDO0 |
| TCELL22:OUT16.TMIN | PCIE.CFGDEVSTATUSNONFATALERRDETECTED |
| TCELL22:OUT17.TMIN | PCIE.CFGDEVSTATUSFATALERRDETECTED |
| TCELL22:OUT18.TMIN | PCIE.CFGDEVSTATUSURDETECTED |
| TCELL22:OUT19.TMIN | PCIE.DBGVECB61 |
| TCELL22:OUT20.TMIN | PCIE.DBGVECB62 |
| TCELL22:OUT21.TMIN | PCIE.DBGVECA36 |
| TCELL22:OUT22.TMIN | PCIE.DBGVECA37 |
| TCELL22:OUT23.TMIN | PCIE.DBGVECA38 |
| TCELL23:IMUX.CTRL0 | PCIE.PLRSTN |
| TCELL23:IMUX.IMUX0.DELAY | PCIE.PLDIRECTEDLINKAUTON |
| TCELL23:IMUX.IMUX1.DELAY | PCIE.PIPERX5CHANISALIGNED |
| TCELL23:IMUX.IMUX2.DELAY | PCIE.PLUPSTREAMPREFERDEEMPH |
| TCELL23:IMUX.IMUX3.DELAY | PCIE.PLDOWNSTREAMDEEMPHSOURCE |
| TCELL23:IMUX.IMUX4.DELAY | PCIE.TRNTD0 |
| TCELL23:IMUX.IMUX5.DELAY | PCIE.MIMTXRDATA46 |
| TCELL23:IMUX.IMUX6.DELAY | PCIE.MIMTXRDATA47 |
| TCELL23:IMUX.IMUX7.DELAY | PCIE.MIMTXRDATA48 |
| TCELL23:IMUX.IMUX8.DELAY | PCIE.MIMTXRDATA49 |
| TCELL23:IMUX.IMUX9.DELAY | PCIE.TRNTDLLPDATA27 |
| TCELL23:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG49 |
| TCELL23:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG50 |
| TCELL23:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG51 |
| TCELL23:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG52 |
| TCELL23:IMUX.IMUX14.DELAY | PCIE.CFGPORTNUMBER0 |
| TCELL23:IMUX.IMUX15.DELAY | PCIE.PIPERX5CHARISK0 |
| TCELL23:IMUX.IMUX16.DELAY | PCIE.CFGPORTNUMBER1 |
| TCELL23:IMUX.IMUX17.DELAY | PCIE.CFGPORTNUMBER2 |
| TCELL23:IMUX.IMUX18.DELAY | PCIE.CFGPORTNUMBER3 |
| TCELL23:IMUX.IMUX21.DELAY | PCIE.PIPERX1CHANISALIGNED |
| TCELL23:IMUX.IMUX23.DELAY | PCIE.PIPERX1CHARISK0 |
| TCELL23:OUT0.TMIN | PCIE.TRNTERRDROPN |
| TCELL23:OUT1.TMIN | PCIE.TRNTBUFAV0 |
| TCELL23:OUT2.TMIN | PCIE.TRNTBUFAV1 |
| TCELL23:OUT3.TMIN | PCIE.TRNTBUFAV2 |
| TCELL23:OUT4.TMIN | PCIE.MIMTXWDATA1 |
| TCELL23:OUT5.TMIN | PCIE.MIMTXWDATA2 |
| TCELL23:OUT6.TMIN | PCIE.MIMTXWDATA3 |
| TCELL23:OUT7.TMIN | PCIE.MIMTXWDATA4 |
| TCELL23:OUT8.TMIN | PCIE.MIMRXWDATA24 |
| TCELL23:OUT9.TMIN | PCIE.MIMRXWDATA25 |
| TCELL23:OUT10.TMIN | PCIE.MIMRXWDATA26 |
| TCELL23:OUT11.TMIN | PCIE.MIMRXWDATA27 |
| TCELL23:OUT12.TMIN | PCIE.CFGDO1 |
| TCELL23:OUT13.TMIN | PCIE.CFGDO2 |
| TCELL23:OUT14.TMIN | PCIE.CFGDO3 |
| TCELL23:OUT15.TMIN | PCIE.CFGDO4 |
| TCELL23:OUT16.TMIN | PCIE.CFGDEVCONTROLCORRERRREPORTINGEN |
| TCELL23:OUT17.TMIN | PCIE.CFGDEVCONTROLNONFATALREPORTINGEN |
| TCELL23:OUT18.TMIN | PCIE.CFGDEVCONTROLFATALERRREPORTINGEN |
| TCELL23:OUT19.TMIN | PCIE.DBGVECB63 |
| TCELL23:OUT20.TMIN | PCIE.DBGVECC0 |
| TCELL23:OUT21.TMIN | PCIE.DBGVECA39 |
| TCELL23:OUT22.TMIN | PCIE.DBGVECA40 |
| TCELL23:OUT23.TMIN | PCIE.DBGVECA41 |
| TCELL24:IMUX.IMUX0.DELAY | PCIE.TRNTD1 |
| TCELL24:IMUX.IMUX1.DELAY | PCIE.PIPERX5STATUS2 |
| TCELL24:IMUX.IMUX2.DELAY | PCIE.TRNTD2 |
| TCELL24:IMUX.IMUX3.DELAY | PCIE.PIPERX5STATUS0 |
| TCELL24:IMUX.IMUX4.DELAY | PCIE.TRNTD3 |
| TCELL24:IMUX.IMUX5.DELAY | PCIE.TRNTD4 |
| TCELL24:IMUX.IMUX6.DELAY | PCIE.MIMTXRDATA50 |
| TCELL24:IMUX.IMUX7.DELAY | PCIE.PIPERX5STATUS1 |
| TCELL24:IMUX.IMUX8.DELAY | PCIE.CFGERRAERHEADERLOG53 |
| TCELL24:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG54 |
| TCELL24:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG55 |
| TCELL24:IMUX.IMUX11.DELAY | PCIE.PIPERX1PHYSTATUS |
| TCELL24:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG56 |
| TCELL24:IMUX.IMUX13.DELAY | PCIE.CFGPORTNUMBER4 |
| TCELL24:IMUX.IMUX14.DELAY | PCIE.CFGPORTNUMBER5 |
| TCELL24:IMUX.IMUX15.DELAY | PCIE.PIPERX5PHYSTATUS |
| TCELL24:IMUX.IMUX16.DELAY | PCIE.CFGPORTNUMBER6 |
| TCELL24:IMUX.IMUX17.DELAY | PCIE.CFGPORTNUMBER7 |
| TCELL24:IMUX.IMUX19.DELAY | PCIE.PIPERX1STATUS1 |
| TCELL24:IMUX.IMUX21.DELAY | PCIE.PIPERX1STATUS2 |
| TCELL24:IMUX.IMUX23.DELAY | PCIE.PIPERX1STATUS0 |
| TCELL24:OUT0.TMIN | PCIE.TRNTBUFAV3 |
| TCELL24:OUT1.TMIN | PCIE.PIPETX1ELECIDLE |
| TCELL24:OUT2.TMIN | PCIE.TRNTBUFAV4 |
| TCELL24:OUT3.TMIN | PCIE.TRNTBUFAV5 |
| TCELL24:OUT4.TMIN | PCIE.TRNTCFGREQN |
| TCELL24:OUT5.TMIN | PCIE.PIPETX5ELECIDLE |
| TCELL24:OUT6.TMIN | PCIE.MIMTXWDATA5 |
| TCELL24:OUT7.TMIN | PCIE.MIMTXWDATA6 |
| TCELL24:OUT8.TMIN | PCIE.MIMTXWDATA7 |
| TCELL24:OUT9.TMIN | PCIE.MIMTXWDATA8 |
| TCELL24:OUT10.TMIN | PCIE.MIMRXWDATA28 |
| TCELL24:OUT11.TMIN | PCIE.MIMRXWDATA29 |
| TCELL24:OUT12.TMIN | PCIE.MIMRXWDATA30 |
| TCELL24:OUT13.TMIN | PCIE.MIMRXWDATA31 |
| TCELL24:OUT14.TMIN | PCIE.CFGDO5 |
| TCELL24:OUT15.TMIN | PCIE.DBGVECC1 |
| TCELL24:OUT16.TMIN | PCIE.DBGVECC2 |
| TCELL24:OUT17.TMIN | PCIE.PIPETX5POWERDOWN0 |
| TCELL24:OUT18.TMIN | PCIE.DBGVECA42 |
| TCELL24:OUT19.TMIN | PCIE.PIPETX5POWERDOWN1 |
| TCELL24:OUT20.TMIN | PCIE.DBGVECA43 |
| TCELL24:OUT21.TMIN | PCIE.PIPETX1POWERDOWN0 |
| TCELL24:OUT22.TMIN | PCIE.DBGVECA44 |
| TCELL24:OUT23.TMIN | PCIE.PIPETX1POWERDOWN1 |
| TCELL25:IMUX.IMUX0.DELAY | PCIE.TRNTD5 |
| TCELL25:IMUX.IMUX1.DELAY | PCIE.TRNTD6 |
| TCELL25:IMUX.IMUX2.DELAY | PCIE.TRNTD7 |
| TCELL25:IMUX.IMUX3.DELAY | PCIE.TRNTD8 |
| TCELL25:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA51 |
| TCELL25:IMUX.IMUX5.DELAY | PCIE.PIPERX5ELECIDLE |
| TCELL25:IMUX.IMUX6.DELAY | PCIE.MIMTXRDATA52 |
| TCELL25:IMUX.IMUX7.DELAY | PCIE.MIMTXRDATA53 |
| TCELL25:IMUX.IMUX8.DELAY | PCIE.MIMTXRDATA54 |
| TCELL25:IMUX.IMUX9.DELAY | PCIE.TRNTDLLPDATA28 |
| TCELL25:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG57 |
| TCELL25:IMUX.IMUX11.DELAY | PCIE.PIPERX5VALID |
| TCELL25:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG58 |
| TCELL25:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG59 |
| TCELL25:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG60 |
| TCELL25:IMUX.IMUX15.DELAY | PCIE.CFGPMWAKEN |
| TCELL25:IMUX.IMUX16.DELAY | PCIE.CFGPMDIRECTASPML1N |
| TCELL25:IMUX.IMUX17.DELAY | PCIE.CFGPMTURNOFFOKN |
| TCELL25:IMUX.IMUX18.DELAY | PCIE.CFGPMSENDPMACKN |
| TCELL25:IMUX.IMUX19.DELAY | PCIE.PIPERX1VALID |
| TCELL25:IMUX.IMUX21.DELAY | PCIE.PIPERX1ELECIDLE |
| TCELL25:OUT0.TMIN | PCIE.TRNRD0 |
| TCELL25:OUT1.TMIN | PCIE.TRNRD1 |
| TCELL25:OUT2.TMIN | PCIE.TRNRD2 |
| TCELL25:OUT3.TMIN | PCIE.TRNRD3 |
| TCELL25:OUT4.TMIN | PCIE.MIMTXWDATA9 |
| TCELL25:OUT5.TMIN | PCIE.MIMTXWDATA10 |
| TCELL25:OUT6.TMIN | PCIE.MIMTXWDATA11 |
| TCELL25:OUT7.TMIN | PCIE.MIMTXWDATA12 |
| TCELL25:OUT8.TMIN | PCIE.MIMRXWDATA32 |
| TCELL25:OUT9.TMIN | PCIE.MIMRXWDATA33 |
| TCELL25:OUT10.TMIN | PCIE.MIMRXWDATA34 |
| TCELL25:OUT11.TMIN | PCIE.MIMRXWDATA35 |
| TCELL25:OUT12.TMIN | PCIE.CFGDO6 |
| TCELL25:OUT13.TMIN | PCIE.DBGVECC3 |
| TCELL25:OUT14.TMIN | PCIE.DBGVECC4 |
| TCELL25:OUT15.TMIN | PCIE.DBGVECC5 |
| TCELL25:OUT16.TMIN | PCIE.PIPETX1COMPLIANCE |
| TCELL25:OUT17.TMIN | PCIE.DBGVECA45 |
| TCELL25:OUT18.TMIN | PCIE.PIPETX1CHARISK0 |
| TCELL25:OUT19.TMIN | PCIE.PIPETX5CHARISK1 |
| TCELL25:OUT20.TMIN | PCIE.PIPETX5COMPLIANCE |
| TCELL25:OUT21.TMIN | PCIE.DBGVECA46 |
| TCELL25:OUT22.TMIN | PCIE.PIPETX5CHARISK0 |
| TCELL25:OUT23.TMIN | PCIE.PIPETX1CHARISK1 |
| TCELL26:IMUX.IMUX0.DELAY | PCIE.TRNTD9 |
| TCELL26:IMUX.IMUX1.DELAY | PCIE.TRNTD10 |
| TCELL26:IMUX.IMUX2.DELAY | PCIE.TRNTD11 |
| TCELL26:IMUX.IMUX3.DELAY | PCIE.TRNTD12 |
| TCELL26:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA55 |
| TCELL26:IMUX.IMUX5.DELAY | PCIE.MIMTXRDATA56 |
| TCELL26:IMUX.IMUX6.DELAY | PCIE.MIMTXRDATA57 |
| TCELL26:IMUX.IMUX7.DELAY | PCIE.MIMTXRDATA58 |
| TCELL26:IMUX.IMUX8.DELAY | PCIE.TRNTDLLPDATA29 |
| TCELL26:IMUX.IMUX9.DELAY | PCIE.TRNTDLLPDATA30 |
| TCELL26:IMUX.IMUX10.DELAY | PCIE.TRNTDLLPDATA31 |
| TCELL26:IMUX.IMUX11.DELAY | PCIE.TRNTDLLPSRCRDYN |
| TCELL26:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG61 |
| TCELL26:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG62 |
| TCELL26:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG63 |
| TCELL26:IMUX.IMUX15.DELAY | PCIE.CFGERRAERHEADERLOG64 |
| TCELL26:IMUX.IMUX16.DELAY | PCIE.CFGPMSENDPMNAKN |
| TCELL26:IMUX.IMUX17.DELAY | PCIE.CFGPMSENDPMETON |
| TCELL26:IMUX.IMUX18.DELAY | PCIE.CFGTRNPENDINGN |
| TCELL26:IMUX.IMUX19.DELAY | PCIE.CFGDSN0 |
| TCELL26:IMUX.IMUX20.DELAY | PCIE.DRPDEN |
| TCELL26:OUT0.TMIN | PCIE.TRNRD4 |
| TCELL26:OUT1.TMIN | PCIE.TRNRD5 |
| TCELL26:OUT2.TMIN | PCIE.PIPETX5DATA13 |
| TCELL26:OUT3.TMIN | PCIE.TRNRD6 |
| TCELL26:OUT4.TMIN | PCIE.TRNRD7 |
| TCELL26:OUT5.TMIN | PCIE.MIMTXWDATA13 |
| TCELL26:OUT6.TMIN | PCIE.PIPETX1DATA13 |
| TCELL26:OUT7.TMIN | PCIE.MIMTXWDATA14 |
| TCELL26:OUT8.TMIN | PCIE.CFGDO7 |
| TCELL26:OUT9.TMIN | PCIE.MIMRXWDATA36 |
| TCELL26:OUT10.TMIN | PCIE.MIMRXWDATA37 |
| TCELL26:OUT11.TMIN | PCIE.MIMRXWDATA38 |
| TCELL26:OUT12.TMIN | PCIE.MIMRXWDATA39 |
| TCELL26:OUT13.TMIN | PCIE.DBGVECA47 |
| TCELL26:OUT14.TMIN | PCIE.DBGVECA48 |
| TCELL26:OUT15.TMIN | PCIE.DBGVECA49 |
| TCELL26:OUT16.TMIN | PCIE.PIPETX1DATA12 |
| TCELL26:OUT17.TMIN | PCIE.PIPETX5DATA15 |
| TCELL26:OUT18.TMIN | PCIE.DBGVECA50 |
| TCELL26:OUT19.TMIN | PCIE.PIPETX5DATA14 |
| TCELL26:OUT20.TMIN | PCIE.PIPETX5DATA12 |
| TCELL26:OUT21.TMIN | PCIE.PIPETX1DATA15 |
| TCELL26:OUT22.TMIN | PCIE.DBGVECC6 |
| TCELL26:OUT23.TMIN | PCIE.PIPETX1DATA14 |
| TCELL27:IMUX.IMUX0.DELAY | PCIE.TRNTD13 |
| TCELL27:IMUX.IMUX1.DELAY | PCIE.TRNTD14 |
| TCELL27:IMUX.IMUX2.DELAY | PCIE.TRNTD15 |
| TCELL27:IMUX.IMUX3.DELAY | PCIE.TRNTD16 |
| TCELL27:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA59 |
| TCELL27:IMUX.IMUX5.DELAY | PCIE.MIMTXRDATA60 |
| TCELL27:IMUX.IMUX6.DELAY | PCIE.MIMTXRDATA61 |
| TCELL27:IMUX.IMUX7.DELAY | PCIE.MIMTXRDATA62 |
| TCELL27:IMUX.IMUX8.DELAY | PCIE.LL2TLPRCVN |
| TCELL27:IMUX.IMUX9.DELAY | PCIE.LL2SENDENTERL1N |
| TCELL27:IMUX.IMUX10.DELAY | PCIE.LL2SENDENTERL23N |
| TCELL27:IMUX.IMUX11.DELAY | PCIE.LL2SENDASREQL1N |
| TCELL27:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG65 |
| TCELL27:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG66 |
| TCELL27:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG67 |
| TCELL27:IMUX.IMUX15.DELAY | PCIE.CFGERRAERHEADERLOG68 |
| TCELL27:IMUX.IMUX16.DELAY | PCIE.CFGDSN1 |
| TCELL27:IMUX.IMUX17.DELAY | PCIE.CFGDSN2 |
| TCELL27:IMUX.IMUX18.DELAY | PCIE.CFGDSN3 |
| TCELL27:IMUX.IMUX19.DELAY | PCIE.CFGDSN4 |
| TCELL27:IMUX.IMUX20.DELAY | PCIE.DRPDWE |
| TCELL27:OUT0.TMIN | PCIE.TRNRD8 |
| TCELL27:OUT1.TMIN | PCIE.PIPETX1DATA11 |
| TCELL27:OUT2.TMIN | PCIE.PIPETX5DATA8 |
| TCELL27:OUT3.TMIN | PCIE.TRNRD9 |
| TCELL27:OUT4.TMIN | PCIE.CFGDO8 |
| TCELL27:OUT5.TMIN | PCIE.PIPETX5DATA11 |
| TCELL27:OUT6.TMIN | PCIE.PIPETX1DATA8 |
| TCELL27:OUT7.TMIN | PCIE.MIMRXWDATA40 |
| TCELL27:OUT8.TMIN | PCIE.MIMRXWDATA41 |
| TCELL27:OUT9.TMIN | PCIE.MIMRXWDATA42 |
| TCELL27:OUT10.TMIN | PCIE.MIMRXWDATA43 |
| TCELL27:OUT11.TMIN | PCIE.DBGVECA51 |
| TCELL27:OUT12.TMIN | PCIE.DBGVECA52 |
| TCELL27:OUT13.TMIN | PCIE.DBGVECA53 |
| TCELL27:OUT14.TMIN | PCIE.DBGVECA54 |
| TCELL27:OUT15.TMIN | PCIE.DBGVECC7 |
| TCELL27:OUT16.TMIN | PCIE.PIPETX1DATA7 |
| TCELL27:OUT17.TMIN | PCIE.PIPETX5DATA10 |
| TCELL27:OUT18.TMIN | PCIE.PIPETX1DATA6 |
| TCELL27:OUT19.TMIN | PCIE.PIPETX5DATA9 |
| TCELL27:OUT20.TMIN | PCIE.PIPETX5DATA7 |
| TCELL27:OUT21.TMIN | PCIE.PIPETX1DATA10 |
| TCELL27:OUT22.TMIN | PCIE.PIPETX5DATA6 |
| TCELL27:OUT23.TMIN | PCIE.PIPETX1DATA9 |
| TCELL28:IMUX.CLK0 | PCIE.DRPCLK |
| TCELL28:IMUX.IMUX0.DELAY | PCIE.TRNTD17 |
| TCELL28:IMUX.IMUX1.DELAY | PCIE.TRNTD18 |
| TCELL28:IMUX.IMUX2.DELAY | PCIE.TRNTD19 |
| TCELL28:IMUX.IMUX3.DELAY | PCIE.TRNTD20 |
| TCELL28:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA63 |
| TCELL28:IMUX.IMUX5.DELAY | PCIE.MIMTXRDATA64 |
| TCELL28:IMUX.IMUX6.DELAY | PCIE.MIMTXRDATA65 |
| TCELL28:IMUX.IMUX7.DELAY | PCIE.MIMTXRDATA66 |
| TCELL28:IMUX.IMUX8.DELAY | PCIE.PL2DIRECTEDLSTATE0 |
| TCELL28:IMUX.IMUX9.DELAY | PCIE.PL2DIRECTEDLSTATE1 |
| TCELL28:IMUX.IMUX10.DELAY | PCIE.PL2DIRECTEDLSTATE2 |
| TCELL28:IMUX.IMUX11.DELAY | PCIE.PL2DIRECTEDLSTATE3 |
| TCELL28:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG69 |
| TCELL28:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG70 |
| TCELL28:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG71 |
| TCELL28:IMUX.IMUX15.DELAY | PCIE.CFGERRAERHEADERLOG72 |
| TCELL28:IMUX.IMUX16.DELAY | PCIE.CFGDSN5 |
| TCELL28:IMUX.IMUX17.DELAY | PCIE.CFGDSN6 |
| TCELL28:IMUX.IMUX18.DELAY | PCIE.CFGDSN7 |
| TCELL28:IMUX.IMUX19.DELAY | PCIE.CFGDSN8 |
| TCELL28:IMUX.IMUX20.DELAY | PCIE.DRPDADDR0 |
| TCELL28:OUT0.TMIN | PCIE.TRNRD10 |
| TCELL28:OUT1.TMIN | PCIE.PIPETX1DATA3 |
| TCELL28:OUT2.TMIN | PCIE.PIPETX5DATA4 |
| TCELL28:OUT3.TMIN | PCIE.TRNRD11 |
| TCELL28:OUT4.TMIN | PCIE.CFGDO9 |
| TCELL28:OUT5.TMIN | PCIE.PIPETX5DATA3 |
| TCELL28:OUT6.TMIN | PCIE.PIPETX1DATA4 |
| TCELL28:OUT7.TMIN | PCIE.MIMRXWDATA44 |
| TCELL28:OUT8.TMIN | PCIE.MIMRXWDATA45 |
| TCELL28:OUT9.TMIN | PCIE.MIMRXWDATA46 |
| TCELL28:OUT10.TMIN | PCIE.MIMRXWDATA47 |
| TCELL28:OUT11.TMIN | PCIE.DBGVECA55 |
| TCELL28:OUT12.TMIN | PCIE.DBGVECA56 |
| TCELL28:OUT13.TMIN | PCIE.DBGVECA57 |
| TCELL28:OUT14.TMIN | PCIE.DBGVECA58 |
| TCELL28:OUT15.TMIN | PCIE.DBGVECC8 |
| TCELL28:OUT16.TMIN | PCIE.PIPETX1DATA0 |
| TCELL28:OUT17.TMIN | PCIE.PIPETX5DATA1 |
| TCELL28:OUT18.TMIN | PCIE.PIPETX1DATA5 |
| TCELL28:OUT19.TMIN | PCIE.PIPETX5DATA2 |
| TCELL28:OUT20.TMIN | PCIE.PIPETX5DATA0 |
| TCELL28:OUT21.TMIN | PCIE.PIPETX1DATA1 |
| TCELL28:OUT22.TMIN | PCIE.PIPETX5DATA5 |
| TCELL28:OUT23.TMIN | PCIE.PIPETX1DATA2 |
| TCELL29:IMUX.CLK0 | PCIE.USERCLK |
| TCELL29:IMUX.CLK1 | PCIE.PIPECLK |
| TCELL29:IMUX.IMUX0.DELAY | PCIE.TRNTD21 |
| TCELL29:IMUX.IMUX1.DELAY | PCIE.TRNTD22 |
| TCELL29:IMUX.IMUX2.DELAY | PCIE.TRNTD23 |
| TCELL29:IMUX.IMUX3.DELAY | PCIE.TRNTD24 |
| TCELL29:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA67 |
| TCELL29:IMUX.IMUX5.DELAY | PCIE.MIMTXRDATA68 |
| TCELL29:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA0 |
| TCELL29:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA1 |
| TCELL29:IMUX.IMUX8.DELAY | PCIE.PL2DIRECTEDLSTATE4 |
| TCELL29:IMUX.IMUX9.DELAY | PCIE.LL2SUSPENDNOWN |
| TCELL29:IMUX.IMUX10.DELAY | PCIE.TL2PPMSUSPENDREQN |
| TCELL29:IMUX.IMUX11.DELAY | PCIE.TL2ASPMSUSPENDCREDITCHECKN |
| TCELL29:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG73 |
| TCELL29:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG74 |
| TCELL29:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG75 |
| TCELL29:IMUX.IMUX15.DELAY | PCIE.CFGERRAERHEADERLOG76 |
| TCELL29:IMUX.IMUX16.DELAY | PCIE.CFGDSN9 |
| TCELL29:IMUX.IMUX17.DELAY | PCIE.CFGDSN10 |
| TCELL29:IMUX.IMUX18.DELAY | PCIE.CFGDSN11 |
| TCELL29:IMUX.IMUX19.DELAY | PCIE.CFGDSN12 |
| TCELL29:IMUX.IMUX20.DELAY | PCIE.DRPDADDR1 |
| TCELL29:IMUX.IMUX21.DELAY | PCIE.DRPDADDR2 |
| TCELL29:IMUX.IMUX22.DELAY | PCIE.DRPDADDR3 |
| TCELL29:OUT0.TMIN | PCIE.TRNRD12 |
| TCELL29:OUT1.TMIN | PCIE.TRNRD13 |
| TCELL29:OUT2.TMIN | PCIE.TRNRD14 |
| TCELL29:OUT3.TMIN | PCIE.TRNRD15 |
| TCELL29:OUT4.TMIN | PCIE.MIMTXWDATA15 |
| TCELL29:OUT5.TMIN | PCIE.MIMTXWDATA16 |
| TCELL29:OUT6.TMIN | PCIE.MIMTXWDATA17 |
| TCELL29:OUT7.TMIN | PCIE.MIMTXWDATA18 |
| TCELL29:OUT8.TMIN | PCIE.MIMRXWDATA48 |
| TCELL29:OUT9.TMIN | PCIE.MIMRXWDATA49 |
| TCELL29:OUT10.TMIN | PCIE.MIMRXWDATA50 |
| TCELL29:OUT11.TMIN | PCIE.MIMRXWDATA51 |
| TCELL29:OUT12.TMIN | PCIE.CFGDO10 |
| TCELL29:OUT13.TMIN | PCIE.CFGDO11 |
| TCELL29:OUT14.TMIN | PCIE.CFGDO12 |
| TCELL29:OUT15.TMIN | PCIE.CFGDO13 |
| TCELL29:OUT16.TMIN | PCIE.CFGDEVCONTROLURERRREPORTINGEN |
| TCELL29:OUT17.TMIN | PCIE.CFGDEVCONTROLENABLERO |
| TCELL29:OUT18.TMIN | PCIE.CFGDEVCONTROLMAXPAYLOAD0 |
| TCELL29:OUT19.TMIN | PCIE.DBGVECC9 |
| TCELL29:OUT20.TMIN | PCIE.DBGVECC10 |
| TCELL29:OUT21.TMIN | PCIE.DBGVECA59 |
| TCELL29:OUT22.TMIN | PCIE.DBGVECA60 |
| TCELL29:OUT23.TMIN | PCIE.DBGVECA61 |
| TCELL30:IMUX.IMUX0.DELAY | PCIE.TRNTD25 |
| TCELL30:IMUX.IMUX1.DELAY | PCIE.PIPERX0DATA4 |
| TCELL30:IMUX.IMUX2.DELAY | PCIE.MIMRXRDATA2 |
| TCELL30:IMUX.IMUX3.DELAY | PCIE.PIPERX0DATA0 |
| TCELL30:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA3 |
| TCELL30:IMUX.IMUX5.DELAY | PCIE.PIPERX0DATA1 |
| TCELL30:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA4 |
| TCELL30:IMUX.IMUX7.DELAY | PCIE.PIPERX4DATA2 |
| TCELL30:IMUX.IMUX8.DELAY | PCIE.MIMRXRDATA5 |
| TCELL30:IMUX.IMUX9.DELAY | PCIE.PIPERX0DATA5 |
| TCELL30:IMUX.IMUX10.DELAY | PCIE.SCANMODEN |
| TCELL30:IMUX.IMUX11.DELAY | PCIE.PIPERX4DATA0 |
| TCELL30:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG77 |
| TCELL30:IMUX.IMUX13.DELAY | PCIE.PIPERX4DATA1 |
| TCELL30:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG78 |
| TCELL30:IMUX.IMUX15.DELAY | PCIE.PIPERX0DATA2 |
| TCELL30:IMUX.IMUX16.DELAY | PCIE.CFGERRAERHEADERLOG79 |
| TCELL30:IMUX.IMUX17.DELAY | PCIE.PIPERX4DATA4 |
| TCELL30:IMUX.IMUX18.DELAY | PCIE.CFGERRAERHEADERLOG80 |
| TCELL30:IMUX.IMUX19.DELAY | PCIE.PIPERX0DATA3 |
| TCELL30:IMUX.IMUX21.DELAY | PCIE.PIPERX4DATA5 |
| TCELL30:IMUX.IMUX23.DELAY | PCIE.PIPERX4DATA3 |
| TCELL30:OUT0.TMIN | PCIE.TRNRD16 |
| TCELL30:OUT1.TMIN | PCIE.TRNRD17 |
| TCELL30:OUT2.TMIN | PCIE.TRNRD18 |
| TCELL30:OUT3.TMIN | PCIE.TRNRD19 |
| TCELL30:OUT4.TMIN | PCIE.MIMTXWDATA19 |
| TCELL30:OUT5.TMIN | PCIE.MIMTXWDATA20 |
| TCELL30:OUT6.TMIN | PCIE.MIMTXWDATA21 |
| TCELL30:OUT7.TMIN | PCIE.MIMTXWDATA22 |
| TCELL30:OUT8.TMIN | PCIE.MIMRXWDATA52 |
| TCELL30:OUT9.TMIN | PCIE.MIMRXWDATA53 |
| TCELL30:OUT10.TMIN | PCIE.MIMRXWDATA54 |
| TCELL30:OUT11.TMIN | PCIE.MIMRXWDATA55 |
| TCELL30:OUT12.TMIN | PCIE.CFGDO14 |
| TCELL30:OUT13.TMIN | PCIE.CFGDO15 |
| TCELL30:OUT14.TMIN | PCIE.CFGDO16 |
| TCELL30:OUT15.TMIN | PCIE.CFGDO17 |
| TCELL30:OUT16.TMIN | PCIE.CFGDEVCONTROLMAXPAYLOAD1 |
| TCELL30:OUT17.TMIN | PCIE.CFGDEVCONTROLMAXPAYLOAD2 |
| TCELL30:OUT18.TMIN | PCIE.CFGDEVCONTROLEXTTAGEN |
| TCELL30:OUT19.TMIN | PCIE.DBGVECC11 |
| TCELL30:OUT20.TMIN | PCIE.DBGSCLRA |
| TCELL30:OUT21.TMIN | PCIE.DBGVECA62 |
| TCELL30:OUT22.TMIN | PCIE.DBGVECA63 |
| TCELL30:OUT23.TMIN | PCIE.DBGVECB0 |
| TCELL31:IMUX.IMUX0.DELAY | PCIE.TRNTD26 |
| TCELL31:IMUX.IMUX1.DELAY | PCIE.PIPERX0DATA6 |
| TCELL31:IMUX.IMUX2.DELAY | PCIE.MIMRXRDATA6 |
| TCELL31:IMUX.IMUX3.DELAY | PCIE.PIPERX0DATA8 |
| TCELL31:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA7 |
| TCELL31:IMUX.IMUX5.DELAY | PCIE.PIPERX0DATA9 |
| TCELL31:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA8 |
| TCELL31:IMUX.IMUX7.DELAY | PCIE.PIPERX0DATA10 |
| TCELL31:IMUX.IMUX8.DELAY | PCIE.MIMRXRDATA9 |
| TCELL31:IMUX.IMUX9.DELAY | PCIE.PIPERX0DATA7 |
| TCELL31:IMUX.IMUX10.DELAY | PCIE.SCANENABLEN |
| TCELL31:IMUX.IMUX11.DELAY | PCIE.PIPERX4DATA8 |
| TCELL31:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG81 |
| TCELL31:IMUX.IMUX13.DELAY | PCIE.PIPERX4DATA9 |
| TCELL31:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG82 |
| TCELL31:IMUX.IMUX15.DELAY | PCIE.PIPERX0DATA11 |
| TCELL31:IMUX.IMUX16.DELAY | PCIE.CFGERRAERHEADERLOG83 |
| TCELL31:IMUX.IMUX17.DELAY | PCIE.PIPERX4DATA6 |
| TCELL31:IMUX.IMUX18.DELAY | PCIE.CFGERRAERHEADERLOG84 |
| TCELL31:IMUX.IMUX19.DELAY | PCIE.PIPERX4DATA10 |
| TCELL31:IMUX.IMUX21.DELAY | PCIE.PIPERX4DATA7 |
| TCELL31:IMUX.IMUX23.DELAY | PCIE.PIPERX4DATA11 |
| TCELL31:OUT0.TMIN | PCIE.TRNRD20 |
| TCELL31:OUT1.TMIN | PCIE.TRNRD21 |
| TCELL31:OUT2.TMIN | PCIE.TRNRD22 |
| TCELL31:OUT3.TMIN | PCIE.TRNRD23 |
| TCELL31:OUT4.TMIN | PCIE.MIMTXWDATA23 |
| TCELL31:OUT5.TMIN | PCIE.MIMTXWDATA24 |
| TCELL31:OUT6.TMIN | PCIE.MIMTXWDATA25 |
| TCELL31:OUT7.TMIN | PCIE.MIMTXWDATA26 |
| TCELL31:OUT8.TMIN | PCIE.MIMRXWDATA56 |
| TCELL31:OUT9.TMIN | PCIE.MIMRXWDATA57 |
| TCELL31:OUT10.TMIN | PCIE.MIMRXWDATA58 |
| TCELL31:OUT11.TMIN | PCIE.MIMRXWDATA59 |
| TCELL31:OUT12.TMIN | PCIE.CFGDO18 |
| TCELL31:OUT13.TMIN | PCIE.CFGDO19 |
| TCELL31:OUT14.TMIN | PCIE.CFGDO20 |
| TCELL31:OUT15.TMIN | PCIE.CFGDO21 |
| TCELL31:OUT16.TMIN | PCIE.CFGDEVCONTROLPHANTOMEN |
| TCELL31:OUT17.TMIN | PCIE.CFGDEVCONTROLAUXPOWEREN |
| TCELL31:OUT18.TMIN | PCIE.PIPERX0POLARITY |
| TCELL31:OUT19.TMIN | PCIE.DBGSCLRB |
| TCELL31:OUT20.TMIN | PCIE.DBGVECB1 |
| TCELL31:OUT21.TMIN | PCIE.DBGVECB2 |
| TCELL31:OUT22.TMIN | PCIE.PIPERX4POLARITY |
| TCELL31:OUT23.TMIN | PCIE.DBGVECB3 |
| TCELL32:IMUX.IMUX0.DELAY | PCIE.TRNTD27 |
| TCELL32:IMUX.IMUX1.DELAY | PCIE.PIPERX0CHARISK1 |
| TCELL32:IMUX.IMUX2.DELAY | PCIE.TRNTD28 |
| TCELL32:IMUX.IMUX3.DELAY | PCIE.PIPERX4DATA13 |
| TCELL32:IMUX.IMUX4.DELAY | PCIE.TRNTD29 |
| TCELL32:IMUX.IMUX5.DELAY | PCIE.PIPERX0DATA12 |
| TCELL32:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA10 |
| TCELL32:IMUX.IMUX7.DELAY | PCIE.PIPERX0DATA13 |
| TCELL32:IMUX.IMUX8.DELAY | PCIE.MIMRXRDATA11 |
| TCELL32:IMUX.IMUX9.DELAY | PCIE.PIPERX0DATA15 |
| TCELL32:IMUX.IMUX10.DELAY | PCIE.MIMRXRDATA12 |
| TCELL32:IMUX.IMUX11.DELAY | PCIE.PIPERX0DATA14 |
| TCELL32:IMUX.IMUX12.DELAY | PCIE.MIMRXRDATA13 |
| TCELL32:IMUX.IMUX13.DELAY | PCIE.PIPERX4DATA12 |
| TCELL32:IMUX.IMUX14.DELAY | PCIE.SCANIN0 |
| TCELL32:IMUX.IMUX15.DELAY | PCIE.PIPERX4DATA14 |
| TCELL32:IMUX.IMUX16.DELAY | PCIE.CFGERRAERHEADERLOG85 |
| TCELL32:IMUX.IMUX17.DELAY | PCIE.PIPERX4CHARISK1 |
| TCELL32:IMUX.IMUX18.DELAY | PCIE.CFGERRAERHEADERLOG86 |
| TCELL32:IMUX.IMUX19.DELAY | PCIE.CFGERRAERHEADERLOG87 |
| TCELL32:IMUX.IMUX20.DELAY | PCIE.CFGERRAERHEADERLOG88 |
| TCELL32:IMUX.IMUX21.DELAY | PCIE.PIPERX4DATA15 |
| TCELL32:OUT0.TMIN | PCIE.TRNRD24 |
| TCELL32:OUT1.TMIN | PCIE.TRNRD25 |
| TCELL32:OUT2.TMIN | PCIE.TRNRD26 |
| TCELL32:OUT3.TMIN | PCIE.TRNRD27 |
| TCELL32:OUT4.TMIN | PCIE.MIMTXWDATA27 |
| TCELL32:OUT5.TMIN | PCIE.MIMTXWDATA28 |
| TCELL32:OUT6.TMIN | PCIE.MIMTXWDATA29 |
| TCELL32:OUT7.TMIN | PCIE.MIMTXWDATA30 |
| TCELL32:OUT8.TMIN | PCIE.MIMRXWDATA60 |
| TCELL32:OUT9.TMIN | PCIE.MIMRXWDATA61 |
| TCELL32:OUT10.TMIN | PCIE.MIMRXWDATA62 |
| TCELL32:OUT11.TMIN | PCIE.MIMRXWDATA63 |
| TCELL32:OUT12.TMIN | PCIE.CFGDO22 |
| TCELL32:OUT13.TMIN | PCIE.CFGDO23 |
| TCELL32:OUT14.TMIN | PCIE.CFGDO24 |
| TCELL32:OUT15.TMIN | PCIE.CFGDO25 |
| TCELL32:OUT16.TMIN | PCIE.CFGDEVCONTROLNOSNOOPEN |
| TCELL32:OUT17.TMIN | PCIE.CFGDEVCONTROLMAXREADREQ0 |
| TCELL32:OUT18.TMIN | PCIE.CFGDEVCONTROLMAXREADREQ1 |
| TCELL32:OUT19.TMIN | PCIE.DBGSCLRC |
| TCELL32:OUT20.TMIN | PCIE.DBGSCLRD |
| TCELL32:OUT21.TMIN | PCIE.DBGVECB4 |
| TCELL32:OUT22.TMIN | PCIE.DBGVECB5 |
| TCELL32:OUT23.TMIN | PCIE.DBGVECB6 |
| TCELL33:IMUX.IMUX0.DELAY | PCIE.TRNTD30 |
| TCELL33:IMUX.IMUX1.DELAY | PCIE.PIPERX4CHANISALIGNED |
| TCELL33:IMUX.IMUX2.DELAY | PCIE.TRNTD31 |
| TCELL33:IMUX.IMUX3.DELAY | PCIE.TRNTD32 |
| TCELL33:IMUX.IMUX4.DELAY | PCIE.TRNTD33 |
| TCELL33:IMUX.IMUX5.DELAY | PCIE.MIMRXRDATA14 |
| TCELL33:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA15 |
| TCELL33:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA16 |
| TCELL33:IMUX.IMUX8.DELAY | PCIE.MIMRXRDATA17 |
| TCELL33:IMUX.IMUX9.DELAY | PCIE.SCANIN1 |
| TCELL33:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG89 |
| TCELL33:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG90 |
| TCELL33:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG91 |
| TCELL33:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG92 |
| TCELL33:IMUX.IMUX14.DELAY | PCIE.CFGDSN13 |
| TCELL33:IMUX.IMUX15.DELAY | PCIE.PIPERX4CHARISK0 |
| TCELL33:IMUX.IMUX16.DELAY | PCIE.CFGDSN14 |
| TCELL33:IMUX.IMUX17.DELAY | PCIE.CFGDSN15 |
| TCELL33:IMUX.IMUX18.DELAY | PCIE.CFGDSN16 |
| TCELL33:IMUX.IMUX19.DELAY | PCIE.DRPDADDR4 |
| TCELL33:IMUX.IMUX21.DELAY | PCIE.PIPERX0CHANISALIGNED |
| TCELL33:IMUX.IMUX23.DELAY | PCIE.PIPERX0CHARISK0 |
| TCELL33:OUT0.TMIN | PCIE.TRNRD28 |
| TCELL33:OUT1.TMIN | PCIE.TRNRD29 |
| TCELL33:OUT2.TMIN | PCIE.TRNRD30 |
| TCELL33:OUT3.TMIN | PCIE.TRNRD31 |
| TCELL33:OUT4.TMIN | PCIE.MIMTXWDATA31 |
| TCELL33:OUT5.TMIN | PCIE.MIMTXWDATA32 |
| TCELL33:OUT6.TMIN | PCIE.MIMTXWDATA33 |
| TCELL33:OUT7.TMIN | PCIE.MIMTXWDATA34 |
| TCELL33:OUT8.TMIN | PCIE.MIMRXWDATA64 |
| TCELL33:OUT9.TMIN | PCIE.MIMRXWDATA65 |
| TCELL33:OUT10.TMIN | PCIE.MIMRXWDATA66 |
| TCELL33:OUT11.TMIN | PCIE.MIMRXWDATA67 |
| TCELL33:OUT12.TMIN | PCIE.CFGDO26 |
| TCELL33:OUT13.TMIN | PCIE.CFGDO27 |
| TCELL33:OUT14.TMIN | PCIE.CFGDO28 |
| TCELL33:OUT15.TMIN | PCIE.CFGDO29 |
| TCELL33:OUT16.TMIN | PCIE.CFGDEVCONTROLMAXREADREQ2 |
| TCELL33:OUT17.TMIN | PCIE.CFGLINKSTATUSCURRENTSPEED0 |
| TCELL33:OUT18.TMIN | PCIE.CFGLINKSTATUSCURRENTSPEED1 |
| TCELL33:OUT19.TMIN | PCIE.DBGSCLRE |
| TCELL33:OUT20.TMIN | PCIE.DBGSCLRF |
| TCELL33:OUT21.TMIN | PCIE.DBGVECB7 |
| TCELL33:OUT22.TMIN | PCIE.DBGVECB8 |
| TCELL33:OUT23.TMIN | PCIE.DBGVECB9 |
| TCELL34:IMUX.IMUX0.DELAY | PCIE.TRNTD34 |
| TCELL34:IMUX.IMUX1.DELAY | PCIE.PIPERX4STATUS2 |
| TCELL34:IMUX.IMUX2.DELAY | PCIE.TRNTD35 |
| TCELL34:IMUX.IMUX3.DELAY | PCIE.PIPERX4STATUS0 |
| TCELL34:IMUX.IMUX4.DELAY | PCIE.TRNTD36 |
| TCELL34:IMUX.IMUX5.DELAY | PCIE.TRNTD37 |
| TCELL34:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA18 |
| TCELL34:IMUX.IMUX7.DELAY | PCIE.PIPERX4STATUS1 |
| TCELL34:IMUX.IMUX8.DELAY | PCIE.MIMRXRDATA19 |
| TCELL34:IMUX.IMUX9.DELAY | PCIE.MIMRXRDATA20 |
| TCELL34:IMUX.IMUX10.DELAY | PCIE.MIMRXRDATA21 |
| TCELL34:IMUX.IMUX11.DELAY | PCIE.PIPERX0PHYSTATUS |
| TCELL34:IMUX.IMUX12.DELAY | PCIE.SCANIN2 |
| TCELL34:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG93 |
| TCELL34:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG94 |
| TCELL34:IMUX.IMUX15.DELAY | PCIE.PIPERX4PHYSTATUS |
| TCELL34:IMUX.IMUX16.DELAY | PCIE.CFGERRAERHEADERLOG95 |
| TCELL34:IMUX.IMUX17.DELAY | PCIE.CFGERRAERHEADERLOG96 |
| TCELL34:IMUX.IMUX18.DELAY | PCIE.CFGDSN17 |
| TCELL34:IMUX.IMUX19.DELAY | PCIE.PIPERX0STATUS1 |
| TCELL34:IMUX.IMUX21.DELAY | PCIE.PIPERX0STATUS2 |
| TCELL34:IMUX.IMUX23.DELAY | PCIE.PIPERX0STATUS0 |
| TCELL34:OUT0.TMIN | PCIE.TRNRD32 |
| TCELL34:OUT1.TMIN | PCIE.PIPETX0ELECIDLE |
| TCELL34:OUT2.TMIN | PCIE.TRNRD33 |
| TCELL34:OUT3.TMIN | PCIE.TRNRD34 |
| TCELL34:OUT4.TMIN | PCIE.TRNRD35 |
| TCELL34:OUT5.TMIN | PCIE.PIPETX4ELECIDLE |
| TCELL34:OUT6.TMIN | PCIE.MIMTXWDATA35 |
| TCELL34:OUT7.TMIN | PCIE.MIMTXWDATA36 |
| TCELL34:OUT8.TMIN | PCIE.MIMTXWDATA37 |
| TCELL34:OUT9.TMIN | PCIE.MIMTXWDATA38 |
| TCELL34:OUT10.TMIN | PCIE.MIMRXWADDR0 |
| TCELL34:OUT11.TMIN | PCIE.MIMRXWADDR1 |
| TCELL34:OUT12.TMIN | PCIE.MIMRXWADDR2 |
| TCELL34:OUT13.TMIN | PCIE.MIMRXWADDR3 |
| TCELL34:OUT14.TMIN | PCIE.CFGDO30 |
| TCELL34:OUT15.TMIN | PCIE.DBGSCLRG |
| TCELL34:OUT16.TMIN | PCIE.DBGSCLRH |
| TCELL34:OUT17.TMIN | PCIE.PIPETX4POWERDOWN0 |
| TCELL34:OUT18.TMIN | PCIE.DBGVECB10 |
| TCELL34:OUT19.TMIN | PCIE.PIPETX4POWERDOWN1 |
| TCELL34:OUT20.TMIN | PCIE.DBGVECB11 |
| TCELL34:OUT21.TMIN | PCIE.PIPETX0POWERDOWN0 |
| TCELL34:OUT22.TMIN | PCIE.DBGVECB12 |
| TCELL34:OUT23.TMIN | PCIE.PIPETX0POWERDOWN1 |
| TCELL35:IMUX.IMUX0.DELAY | PCIE.TRNTD38 |
| TCELL35:IMUX.IMUX1.DELAY | PCIE.TRNTD39 |
| TCELL35:IMUX.IMUX2.DELAY | PCIE.TRNTD40 |
| TCELL35:IMUX.IMUX3.DELAY | PCIE.TRNTD41 |
| TCELL35:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA22 |
| TCELL35:IMUX.IMUX5.DELAY | PCIE.PIPERX4ELECIDLE |
| TCELL35:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA23 |
| TCELL35:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA24 |
| TCELL35:IMUX.IMUX8.DELAY | PCIE.MIMRXRDATA25 |
| TCELL35:IMUX.IMUX9.DELAY | PCIE.SCANIN3 |
| TCELL35:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG97 |
| TCELL35:IMUX.IMUX11.DELAY | PCIE.PIPERX4VALID |
| TCELL35:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG98 |
| TCELL35:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG99 |
| TCELL35:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG100 |
| TCELL35:IMUX.IMUX15.DELAY | PCIE.CFGDSN18 |
| TCELL35:IMUX.IMUX16.DELAY | PCIE.CFGDSN19 |
| TCELL35:IMUX.IMUX17.DELAY | PCIE.CFGDSN20 |
| TCELL35:IMUX.IMUX18.DELAY | PCIE.CFGDSN21 |
| TCELL35:IMUX.IMUX19.DELAY | PCIE.PIPERX0VALID |
| TCELL35:IMUX.IMUX20.DELAY | PCIE.DRPDADDR5 |
| TCELL35:IMUX.IMUX21.DELAY | PCIE.PIPERX0ELECIDLE |
| TCELL35:OUT0.TMIN | PCIE.TRNRD36 |
| TCELL35:OUT1.TMIN | PCIE.TRNRD37 |
| TCELL35:OUT2.TMIN | PCIE.TRNRD38 |
| TCELL35:OUT3.TMIN | PCIE.TRNRD39 |
| TCELL35:OUT4.TMIN | PCIE.MIMTXWDATA39 |
| TCELL35:OUT5.TMIN | PCIE.MIMTXWDATA40 |
| TCELL35:OUT6.TMIN | PCIE.MIMTXWDATA41 |
| TCELL35:OUT7.TMIN | PCIE.MIMTXWDATA42 |
| TCELL35:OUT8.TMIN | PCIE.MIMRXWADDR4 |
| TCELL35:OUT9.TMIN | PCIE.MIMRXWADDR5 |
| TCELL35:OUT10.TMIN | PCIE.MIMRXWADDR6 |
| TCELL35:OUT11.TMIN | PCIE.MIMRXWADDR7 |
| TCELL35:OUT12.TMIN | PCIE.CFGDO31 |
| TCELL35:OUT13.TMIN | PCIE.DBGSCLRI |
| TCELL35:OUT14.TMIN | PCIE.DBGSCLRJ |
| TCELL35:OUT15.TMIN | PCIE.DBGSCLRK |
| TCELL35:OUT16.TMIN | PCIE.PIPETX0COMPLIANCE |
| TCELL35:OUT17.TMIN | PCIE.DBGVECB13 |
| TCELL35:OUT18.TMIN | PCIE.PIPETX0CHARISK0 |
| TCELL35:OUT19.TMIN | PCIE.PIPETX4CHARISK1 |
| TCELL35:OUT20.TMIN | PCIE.PIPETX4COMPLIANCE |
| TCELL35:OUT21.TMIN | PCIE.DBGVECB14 |
| TCELL35:OUT22.TMIN | PCIE.PIPETX4CHARISK0 |
| TCELL35:OUT23.TMIN | PCIE.PIPETX0CHARISK1 |
| TCELL36:IMUX.IMUX0.DELAY | PCIE.TRNTD42 |
| TCELL36:IMUX.IMUX1.DELAY | PCIE.TRNTD43 |
| TCELL36:IMUX.IMUX2.DELAY | PCIE.TRNTD44 |
| TCELL36:IMUX.IMUX3.DELAY | PCIE.TRNTD45 |
| TCELL36:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA26 |
| TCELL36:IMUX.IMUX5.DELAY | PCIE.MIMRXRDATA27 |
| TCELL36:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA28 |
| TCELL36:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA29 |
| TCELL36:IMUX.IMUX8.DELAY | PCIE.SCANIN4 |
| TCELL36:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG101 |
| TCELL36:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG102 |
| TCELL36:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG103 |
| TCELL36:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG104 |
| TCELL36:IMUX.IMUX13.DELAY | PCIE.CFGDSN22 |
| TCELL36:IMUX.IMUX14.DELAY | PCIE.CFGDSN23 |
| TCELL36:IMUX.IMUX15.DELAY | PCIE.CFGDSN24 |
| TCELL36:IMUX.IMUX16.DELAY | PCIE.CFGDSN25 |
| TCELL36:IMUX.IMUX17.DELAY | PCIE.DRPDADDR6 |
| TCELL36:IMUX.IMUX18.DELAY | PCIE.DRPDADDR7 |
| TCELL36:IMUX.IMUX19.DELAY | PCIE.DRPDADDR8 |
| TCELL36:IMUX.IMUX20.DELAY | PCIE.DRPDI0 |
| TCELL36:IMUX.IMUX21.DELAY | PCIE.DBGSUBMODE |
| TCELL36:OUT0.TMIN | PCIE.TRNRD40 |
| TCELL36:OUT1.TMIN | PCIE.TRNRD41 |
| TCELL36:OUT2.TMIN | PCIE.PIPETX4DATA13 |
| TCELL36:OUT3.TMIN | PCIE.TRNRD42 |
| TCELL36:OUT4.TMIN | PCIE.TRNRD43 |
| TCELL36:OUT5.TMIN | PCIE.MIMTXWDATA43 |
| TCELL36:OUT6.TMIN | PCIE.PIPETX0DATA13 |
| TCELL36:OUT7.TMIN | PCIE.MIMTXWDATA44 |
| TCELL36:OUT8.TMIN | PCIE.CFGRDWRDONEN |
| TCELL36:OUT9.TMIN | PCIE.MIMRXWADDR8 |
| TCELL36:OUT10.TMIN | PCIE.MIMRXWADDR9 |
| TCELL36:OUT11.TMIN | PCIE.MIMRXWADDR10 |
| TCELL36:OUT12.TMIN | PCIE.MIMRXWADDR11 |
| TCELL36:OUT13.TMIN | PCIE.DBGVECB15 |
| TCELL36:OUT14.TMIN | PCIE.DBGVECB16 |
| TCELL36:OUT15.TMIN | PCIE.DBGVECB17 |
| TCELL36:OUT16.TMIN | PCIE.PIPETX0DATA12 |
| TCELL36:OUT17.TMIN | PCIE.PIPETX4DATA15 |
| TCELL36:OUT18.TMIN | PCIE.DBGVECB18 |
| TCELL36:OUT19.TMIN | PCIE.PIPETX4DATA14 |
| TCELL36:OUT20.TMIN | PCIE.PIPETX4DATA12 |
| TCELL36:OUT21.TMIN | PCIE.PIPETX0DATA15 |
| TCELL36:OUT22.TMIN | PCIE.PLDBGVEC0 |
| TCELL36:OUT23.TMIN | PCIE.PIPETX0DATA14 |
| TCELL37:IMUX.IMUX0.DELAY | PCIE.TRNTD46 |
| TCELL37:IMUX.IMUX1.DELAY | PCIE.TRNTD47 |
| TCELL37:IMUX.IMUX2.DELAY | PCIE.TRNTD48 |
| TCELL37:IMUX.IMUX3.DELAY | PCIE.TRNTD49 |
| TCELL37:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA30 |
| TCELL37:IMUX.IMUX5.DELAY | PCIE.MIMRXRDATA31 |
| TCELL37:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA32 |
| TCELL37:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA33 |
| TCELL37:IMUX.IMUX8.DELAY | PCIE.SCANIN5 |
| TCELL37:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG105 |
| TCELL37:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG106 |
| TCELL37:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG107 |
| TCELL37:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG108 |
| TCELL37:IMUX.IMUX13.DELAY | PCIE.CFGDSN26 |
| TCELL37:IMUX.IMUX14.DELAY | PCIE.CFGDSN27 |
| TCELL37:IMUX.IMUX15.DELAY | PCIE.CFGDSN28 |
| TCELL37:IMUX.IMUX16.DELAY | PCIE.CFGDSN29 |
| TCELL37:IMUX.IMUX17.DELAY | PCIE.DRPDI1 |
| TCELL37:IMUX.IMUX18.DELAY | PCIE.DRPDI2 |
| TCELL37:IMUX.IMUX19.DELAY | PCIE.DRPDI3 |
| TCELL37:IMUX.IMUX20.DELAY | PCIE.DRPDI4 |
| TCELL37:IMUX.IMUX21.DELAY | PCIE.PLDBGMODE0 |
| TCELL37:OUT0.TMIN | PCIE.TRNRD44 |
| TCELL37:OUT1.TMIN | PCIE.PIPETX0DATA11 |
| TCELL37:OUT2.TMIN | PCIE.PIPETX4DATA8 |
| TCELL37:OUT3.TMIN | PCIE.TRNRD45 |
| TCELL37:OUT4.TMIN | PCIE.CFGERRAERHEADERLOGSETN |
| TCELL37:OUT5.TMIN | PCIE.PIPETX4DATA11 |
| TCELL37:OUT6.TMIN | PCIE.PIPETX0DATA8 |
| TCELL37:OUT7.TMIN | PCIE.MIMRXWADDR12 |
| TCELL37:OUT8.TMIN | PCIE.MIMRXWEN |
| TCELL37:OUT9.TMIN | PCIE.MIMRXRADDR0 |
| TCELL37:OUT10.TMIN | PCIE.MIMRXRADDR1 |
| TCELL37:OUT11.TMIN | PCIE.DBGVECB19 |
| TCELL37:OUT12.TMIN | PCIE.DBGVECB20 |
| TCELL37:OUT13.TMIN | PCIE.DBGVECB21 |
| TCELL37:OUT14.TMIN | PCIE.DBGVECB22 |
| TCELL37:OUT15.TMIN | PCIE.PLDBGVEC1 |
| TCELL37:OUT16.TMIN | PCIE.PIPETX0DATA7 |
| TCELL37:OUT17.TMIN | PCIE.PIPETX4DATA10 |
| TCELL37:OUT18.TMIN | PCIE.PIPETX0DATA6 |
| TCELL37:OUT19.TMIN | PCIE.PIPETX4DATA9 |
| TCELL37:OUT20.TMIN | PCIE.PIPETX4DATA7 |
| TCELL37:OUT21.TMIN | PCIE.PIPETX0DATA10 |
| TCELL37:OUT22.TMIN | PCIE.PIPETX4DATA6 |
| TCELL37:OUT23.TMIN | PCIE.PIPETX0DATA9 |
| TCELL38:IMUX.IMUX0.DELAY | PCIE.TRNTD50 |
| TCELL38:IMUX.IMUX1.DELAY | PCIE.TRNTD51 |
| TCELL38:IMUX.IMUX2.DELAY | PCIE.TRNTD52 |
| TCELL38:IMUX.IMUX3.DELAY | PCIE.TRNTD53 |
| TCELL38:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA34 |
| TCELL38:IMUX.IMUX5.DELAY | PCIE.MIMRXRDATA35 |
| TCELL38:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA36 |
| TCELL38:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA37 |
| TCELL38:IMUX.IMUX8.DELAY | PCIE.SCANIN6 |
| TCELL38:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG109 |
| TCELL38:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG110 |
| TCELL38:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG111 |
| TCELL38:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG112 |
| TCELL38:IMUX.IMUX13.DELAY | PCIE.CFGDSN30 |
| TCELL38:IMUX.IMUX14.DELAY | PCIE.CFGDSN31 |
| TCELL38:IMUX.IMUX15.DELAY | PCIE.CFGDSN32 |
| TCELL38:IMUX.IMUX16.DELAY | PCIE.CFGDSN33 |
| TCELL38:IMUX.IMUX17.DELAY | PCIE.DRPDI5 |
| TCELL38:IMUX.IMUX18.DELAY | PCIE.DRPDI6 |
| TCELL38:IMUX.IMUX19.DELAY | PCIE.DRPDI7 |
| TCELL38:IMUX.IMUX20.DELAY | PCIE.DRPDI8 |
| TCELL38:IMUX.IMUX21.DELAY | PCIE.PLDBGMODE1 |
| TCELL38:OUT0.TMIN | PCIE.TRNRD46 |
| TCELL38:OUT1.TMIN | PCIE.PIPETX0DATA3 |
| TCELL38:OUT2.TMIN | PCIE.PIPETX4DATA4 |
| TCELL38:OUT3.TMIN | PCIE.TRNRD47 |
| TCELL38:OUT4.TMIN | PCIE.CFGERRCPLRDYN |
| TCELL38:OUT5.TMIN | PCIE.PIPETX4DATA3 |
| TCELL38:OUT6.TMIN | PCIE.PIPETX0DATA4 |
| TCELL38:OUT7.TMIN | PCIE.MIMRXRADDR2 |
| TCELL38:OUT8.TMIN | PCIE.MIMRXRADDR3 |
| TCELL38:OUT9.TMIN | PCIE.MIMRXRADDR4 |
| TCELL38:OUT10.TMIN | PCIE.MIMRXRADDR5 |
| TCELL38:OUT11.TMIN | PCIE.DBGVECB23 |
| TCELL38:OUT12.TMIN | PCIE.DBGVECB24 |
| TCELL38:OUT13.TMIN | PCIE.DBGVECB25 |
| TCELL38:OUT14.TMIN | PCIE.DBGVECB26 |
| TCELL38:OUT15.TMIN | PCIE.PLDBGVEC2 |
| TCELL38:OUT16.TMIN | PCIE.PIPETX0DATA0 |
| TCELL38:OUT17.TMIN | PCIE.PIPETX4DATA1 |
| TCELL38:OUT18.TMIN | PCIE.PIPETX0DATA5 |
| TCELL38:OUT19.TMIN | PCIE.PIPETX4DATA2 |
| TCELL38:OUT20.TMIN | PCIE.PIPETX4DATA0 |
| TCELL38:OUT21.TMIN | PCIE.PIPETX0DATA1 |
| TCELL38:OUT22.TMIN | PCIE.PIPETX4DATA5 |
| TCELL38:OUT23.TMIN | PCIE.PIPETX0DATA2 |
| TCELL39:IMUX.IMUX0.DELAY | PCIE.TRNTD54 |
| TCELL39:IMUX.IMUX1.DELAY | PCIE.TRNTD55 |
| TCELL39:IMUX.IMUX2.DELAY | PCIE.TRNTD56 |
| TCELL39:IMUX.IMUX3.DELAY | PCIE.TRNTD57 |
| TCELL39:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA38 |
| TCELL39:IMUX.IMUX5.DELAY | PCIE.MIMRXRDATA39 |
| TCELL39:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA40 |
| TCELL39:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA41 |
| TCELL39:IMUX.IMUX8.DELAY | PCIE.SCANIN7 |
| TCELL39:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG113 |
| TCELL39:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG114 |
| TCELL39:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG115 |
| TCELL39:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG116 |
| TCELL39:IMUX.IMUX13.DELAY | PCIE.CFGDSN34 |
| TCELL39:IMUX.IMUX14.DELAY | PCIE.CFGDSN35 |
| TCELL39:IMUX.IMUX15.DELAY | PCIE.CFGDSN36 |
| TCELL39:IMUX.IMUX16.DELAY | PCIE.CFGDSN37 |
| TCELL39:IMUX.IMUX17.DELAY | PCIE.DRPDI9 |
| TCELL39:IMUX.IMUX18.DELAY | PCIE.DRPDI10 |
| TCELL39:IMUX.IMUX19.DELAY | PCIE.DRPDI11 |
| TCELL39:IMUX.IMUX20.DELAY | PCIE.DRPDI12 |
| TCELL39:IMUX.IMUX21.DELAY | PCIE.PLDBGMODE2 |
| TCELL39:OUT0.TMIN | PCIE.TRNRD48 |
| TCELL39:OUT1.TMIN | PCIE.TRNRD49 |
| TCELL39:OUT2.TMIN | PCIE.TRNRD50 |
| TCELL39:OUT3.TMIN | PCIE.TRNRD51 |
| TCELL39:OUT4.TMIN | PCIE.MIMTXWDATA45 |
| TCELL39:OUT5.TMIN | PCIE.MIMTXWDATA46 |
| TCELL39:OUT6.TMIN | PCIE.MIMTXWDATA47 |
| TCELL39:OUT7.TMIN | PCIE.MIMTXWDATA48 |
| TCELL39:OUT8.TMIN | PCIE.MIMRXRADDR6 |
| TCELL39:OUT9.TMIN | PCIE.MIMRXRADDR7 |
| TCELL39:OUT10.TMIN | PCIE.MIMRXRADDR8 |
| TCELL39:OUT11.TMIN | PCIE.MIMRXRADDR9 |
| TCELL39:OUT12.TMIN | PCIE.CFGINTERRUPTRDYN |
| TCELL39:OUT13.TMIN | PCIE.CFGINTERRUPTMMENABLE0 |
| TCELL39:OUT14.TMIN | PCIE.CFGINTERRUPTMMENABLE1 |
| TCELL39:OUT15.TMIN | PCIE.CFGINTERRUPTMMENABLE2 |
| TCELL39:OUT16.TMIN | PCIE.CFGLINKSTATUSNEGOTIATEDWIDTH0 |
| TCELL39:OUT17.TMIN | PCIE.CFGLINKSTATUSNEGOTIATEDWIDTH1 |
| TCELL39:OUT18.TMIN | PCIE.CFGLINKSTATUSNEGOTIATEDWIDTH2 |
| TCELL39:OUT19.TMIN | PCIE.PLDBGVEC3 |
| TCELL39:OUT20.TMIN | PCIE.PLDBGVEC4 |
| TCELL39:OUT21.TMIN | PCIE.DBGVECB27 |
| TCELL39:OUT22.TMIN | PCIE.DBGVECB28 |
| TCELL39:OUT23.TMIN | PCIE.DBGVECB29 |
Bitstream
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[14] PCIE:DRP05[14] | PCIE:BAR0[15] PCIE:DRP05[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[12] PCIE:DRP05[12] | PCIE:BAR0[13] PCIE:DRP05[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[10] PCIE:DRP05[10] | PCIE:BAR0[11] PCIE:DRP05[11] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[8] PCIE:DRP05[8] | PCIE:BAR0[9] PCIE:DRP05[9] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[6] PCIE:DRP05[6] | PCIE:BAR0[7] PCIE:DRP05[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[4] PCIE:DRP05[4] | PCIE:BAR0[5] PCIE:DRP05[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[2] PCIE:DRP05[2] | PCIE:BAR0[3] PCIE:DRP05[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[0] PCIE:DRP05[0] | PCIE:BAR0[1] PCIE:DRP05[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP04[14] | PCIE:DRP04[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ON PCIE:DRP04[12] | PCIE:DRP04[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_NEXTPTR[10] PCIE:DRP04[10] | PCIE:AER_CAP_NEXTPTR[11] PCIE:DRP04[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_NEXTPTR[8] PCIE:DRP04[8] | PCIE:AER_CAP_NEXTPTR[9] PCIE:DRP04[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_NEXTPTR[6] PCIE:DRP04[6] | PCIE:AER_CAP_NEXTPTR[7] PCIE:DRP04[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_NEXTPTR[4] PCIE:DRP04[4] | PCIE:AER_CAP_NEXTPTR[5] PCIE:DRP04[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_NEXTPTR[2] PCIE:DRP04[2] | PCIE:AER_CAP_NEXTPTR[3] PCIE:DRP04[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_NEXTPTR[0] PCIE:DRP04[0] | PCIE:AER_CAP_NEXTPTR[1] PCIE:DRP04[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP03[14] | PCIE:DRP03[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP03[12] | PCIE:DRP03[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_BASE_PTR[10] PCIE:DRP03[10] | PCIE:AER_BASE_PTR[11] PCIE:DRP03[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_BASE_PTR[8] PCIE:DRP03[8] | PCIE:AER_BASE_PTR[9] PCIE:DRP03[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_BASE_PTR[6] PCIE:DRP03[6] | PCIE:AER_BASE_PTR[7] PCIE:DRP03[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_BASE_PTR[4] PCIE:DRP03[4] | PCIE:AER_BASE_PTR[5] PCIE:DRP03[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_BASE_PTR[2] PCIE:DRP03[2] | PCIE:AER_BASE_PTR[3] PCIE:DRP03[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_BASE_PTR[0] PCIE:DRP03[0] | PCIE:AER_BASE_PTR[1] PCIE:DRP03[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_VERSION[3] PCIE:DRP02[14] | PCIE:DRP02[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_VERSION[1] PCIE:DRP02[12] | PCIE:AER_CAP_VERSION[2] PCIE:DRP02[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_PERMIT_ROOTERR_UPDATE PCIE:DRP02[10] | PCIE:AER_CAP_VERSION[0] PCIE:DRP02[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_INT_MSG_NUM_MSIX[3] PCIE:DRP02[8] | PCIE:AER_CAP_INT_MSG_NUM_MSIX[4] PCIE:DRP02[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_INT_MSG_NUM_MSIX[1] PCIE:DRP02[6] | PCIE:AER_CAP_INT_MSG_NUM_MSIX[2] PCIE:DRP02[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_INT_MSG_NUM_MSI[4] PCIE:DRP02[4] | PCIE:AER_CAP_INT_MSG_NUM_MSIX[0] PCIE:DRP02[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_INT_MSG_NUM_MSI[2] PCIE:DRP02[2] | PCIE:AER_CAP_INT_MSG_NUM_MSI[3] PCIE:DRP02[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_INT_MSG_NUM_MSI[0] PCIE:DRP02[0] | PCIE:AER_CAP_INT_MSG_NUM_MSI[1] PCIE:DRP02[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ID[14] PCIE:DRP01[14] | PCIE:AER_CAP_ID[15] PCIE:DRP01[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ID[12] PCIE:DRP01[12] | PCIE:AER_CAP_ID[13] PCIE:DRP01[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ID[10] PCIE:DRP01[10] | PCIE:AER_CAP_ID[11] PCIE:DRP01[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ID[8] PCIE:DRP01[8] | PCIE:AER_CAP_ID[9] PCIE:DRP01[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ID[6] PCIE:DRP01[6] | PCIE:AER_CAP_ID[7] PCIE:DRP01[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ID[4] PCIE:DRP01[4] | PCIE:AER_CAP_ID[5] PCIE:DRP01[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ID[2] PCIE:DRP01[2] | PCIE:AER_CAP_ID[3] PCIE:DRP01[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ID[0] PCIE:DRP01[0] | PCIE:AER_CAP_ID[1] PCIE:DRP01[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP00[14] | PCIE:DRP00[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP00[12] | PCIE:DRP00[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP00[10] | PCIE:DRP00[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP00[8] | PCIE:DRP00[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP00[6] | PCIE:DRP00[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP00[4] | PCIE:DRP00[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP00[2] | PCIE:DRP00[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ECRC_CHECK_CAPABLE PCIE:DRP00[0] | PCIE:AER_CAP_ECRC_GEN_CAPABLE PCIE:DRP00[1] |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[14] PCIE:DRP0B[14] | PCIE:BAR3[15] PCIE:DRP0B[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[12] PCIE:DRP0B[12] | PCIE:BAR3[13] PCIE:DRP0B[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[10] PCIE:DRP0B[10] | PCIE:BAR3[11] PCIE:DRP0B[11] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[8] PCIE:DRP0B[8] | PCIE:BAR3[9] PCIE:DRP0B[9] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[6] PCIE:DRP0B[6] | PCIE:BAR3[7] PCIE:DRP0B[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[4] PCIE:DRP0B[4] | PCIE:BAR3[5] PCIE:DRP0B[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[2] PCIE:DRP0B[2] | PCIE:BAR3[3] PCIE:DRP0B[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[0] PCIE:DRP0B[0] | PCIE:BAR3[1] PCIE:DRP0B[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[30] PCIE:DRP0A[14] | PCIE:BAR2[31] PCIE:DRP0A[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[28] PCIE:DRP0A[12] | PCIE:BAR2[29] PCIE:DRP0A[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[26] PCIE:DRP0A[10] | PCIE:BAR2[27] PCIE:DRP0A[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[24] PCIE:DRP0A[8] | PCIE:BAR2[25] PCIE:DRP0A[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[22] PCIE:DRP0A[6] | PCIE:BAR2[23] PCIE:DRP0A[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[20] PCIE:DRP0A[4] | PCIE:BAR2[21] PCIE:DRP0A[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[18] PCIE:DRP0A[2] | PCIE:BAR2[19] PCIE:DRP0A[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[16] PCIE:DRP0A[0] | PCIE:BAR2[17] PCIE:DRP0A[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[14] PCIE:DRP09[14] | PCIE:BAR2[15] PCIE:DRP09[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[12] PCIE:DRP09[12] | PCIE:BAR2[13] PCIE:DRP09[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[10] PCIE:DRP09[10] | PCIE:BAR2[11] PCIE:DRP09[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[8] PCIE:DRP09[8] | PCIE:BAR2[9] PCIE:DRP09[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[6] PCIE:DRP09[6] | PCIE:BAR2[7] PCIE:DRP09[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[4] PCIE:DRP09[4] | PCIE:BAR2[5] PCIE:DRP09[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[2] PCIE:DRP09[2] | PCIE:BAR2[3] PCIE:DRP09[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[0] PCIE:DRP09[0] | PCIE:BAR2[1] PCIE:DRP09[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[30] PCIE:DRP08[14] | PCIE:BAR1[31] PCIE:DRP08[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[28] PCIE:DRP08[12] | PCIE:BAR1[29] PCIE:DRP08[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[26] PCIE:DRP08[10] | PCIE:BAR1[27] PCIE:DRP08[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[24] PCIE:DRP08[8] | PCIE:BAR1[25] PCIE:DRP08[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[22] PCIE:DRP08[6] | PCIE:BAR1[23] PCIE:DRP08[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[20] PCIE:DRP08[4] | PCIE:BAR1[21] PCIE:DRP08[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[18] PCIE:DRP08[2] | PCIE:BAR1[19] PCIE:DRP08[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[16] PCIE:DRP08[0] | PCIE:BAR1[17] PCIE:DRP08[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[14] PCIE:DRP07[14] | PCIE:BAR1[15] PCIE:DRP07[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[12] PCIE:DRP07[12] | PCIE:BAR1[13] PCIE:DRP07[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[10] PCIE:DRP07[10] | PCIE:BAR1[11] PCIE:DRP07[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[8] PCIE:DRP07[8] | PCIE:BAR1[9] PCIE:DRP07[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[6] PCIE:DRP07[6] | PCIE:BAR1[7] PCIE:DRP07[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[4] PCIE:DRP07[4] | PCIE:BAR1[5] PCIE:DRP07[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[2] PCIE:DRP07[2] | PCIE:BAR1[3] PCIE:DRP07[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[0] PCIE:DRP07[0] | PCIE:BAR1[1] PCIE:DRP07[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[30] PCIE:DRP06[14] | PCIE:BAR0[31] PCIE:DRP06[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[28] PCIE:DRP06[12] | PCIE:BAR0[29] PCIE:DRP06[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[26] PCIE:DRP06[10] | PCIE:BAR0[27] PCIE:DRP06[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[24] PCIE:DRP06[8] | PCIE:BAR0[25] PCIE:DRP06[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[22] PCIE:DRP06[6] | PCIE:BAR0[23] PCIE:DRP06[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[20] PCIE:DRP06[4] | PCIE:BAR0[21] PCIE:DRP06[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[18] PCIE:DRP06[2] | PCIE:BAR0[19] PCIE:DRP06[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[16] PCIE:DRP06[0] | PCIE:BAR0[17] PCIE:DRP06[1] |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP11[14] PCIE:EXPANSION_ROM[14] | PCIE:DRP11[15] PCIE:EXPANSION_ROM[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP11[12] PCIE:EXPANSION_ROM[12] | PCIE:DRP11[13] PCIE:EXPANSION_ROM[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP11[10] PCIE:EXPANSION_ROM[10] | PCIE:DRP11[11] PCIE:EXPANSION_ROM[11] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP11[8] PCIE:EXPANSION_ROM[8] | PCIE:DRP11[9] PCIE:EXPANSION_ROM[9] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP11[6] PCIE:EXPANSION_ROM[6] | PCIE:DRP11[7] PCIE:EXPANSION_ROM[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP11[4] PCIE:EXPANSION_ROM[4] | PCIE:DRP11[5] PCIE:EXPANSION_ROM[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP11[2] PCIE:EXPANSION_ROM[2] | PCIE:DRP11[3] PCIE:EXPANSION_ROM[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP11[0] PCIE:EXPANSION_ROM[0] | PCIE:DRP11[1] PCIE:EXPANSION_ROM[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[30] PCIE:DRP10[14] | PCIE:BAR5[31] PCIE:DRP10[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[28] PCIE:DRP10[12] | PCIE:BAR5[29] PCIE:DRP10[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[26] PCIE:DRP10[10] | PCIE:BAR5[27] PCIE:DRP10[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[24] PCIE:DRP10[8] | PCIE:BAR5[25] PCIE:DRP10[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[22] PCIE:DRP10[6] | PCIE:BAR5[23] PCIE:DRP10[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[20] PCIE:DRP10[4] | PCIE:BAR5[21] PCIE:DRP10[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[18] PCIE:DRP10[2] | PCIE:BAR5[19] PCIE:DRP10[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[16] PCIE:DRP10[0] | PCIE:BAR5[17] PCIE:DRP10[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[14] PCIE:DRP0F[14] | PCIE:BAR5[15] PCIE:DRP0F[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[12] PCIE:DRP0F[12] | PCIE:BAR5[13] PCIE:DRP0F[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[10] PCIE:DRP0F[10] | PCIE:BAR5[11] PCIE:DRP0F[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[8] PCIE:DRP0F[8] | PCIE:BAR5[9] PCIE:DRP0F[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[6] PCIE:DRP0F[6] | PCIE:BAR5[7] PCIE:DRP0F[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[4] PCIE:DRP0F[4] | PCIE:BAR5[5] PCIE:DRP0F[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[2] PCIE:DRP0F[2] | PCIE:BAR5[3] PCIE:DRP0F[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[0] PCIE:DRP0F[0] | PCIE:BAR5[1] PCIE:DRP0F[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[30] PCIE:DRP0E[14] | PCIE:BAR4[31] PCIE:DRP0E[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[28] PCIE:DRP0E[12] | PCIE:BAR4[29] PCIE:DRP0E[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[26] PCIE:DRP0E[10] | PCIE:BAR4[27] PCIE:DRP0E[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[24] PCIE:DRP0E[8] | PCIE:BAR4[25] PCIE:DRP0E[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[22] PCIE:DRP0E[6] | PCIE:BAR4[23] PCIE:DRP0E[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[20] PCIE:DRP0E[4] | PCIE:BAR4[21] PCIE:DRP0E[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[18] PCIE:DRP0E[2] | PCIE:BAR4[19] PCIE:DRP0E[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[16] PCIE:DRP0E[0] | PCIE:BAR4[17] PCIE:DRP0E[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[14] PCIE:DRP0D[14] | PCIE:BAR4[15] PCIE:DRP0D[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[12] PCIE:DRP0D[12] | PCIE:BAR4[13] PCIE:DRP0D[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[10] PCIE:DRP0D[10] | PCIE:BAR4[11] PCIE:DRP0D[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[8] PCIE:DRP0D[8] | PCIE:BAR4[9] PCIE:DRP0D[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[6] PCIE:DRP0D[6] | PCIE:BAR4[7] PCIE:DRP0D[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[4] PCIE:DRP0D[4] | PCIE:BAR4[5] PCIE:DRP0D[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[2] PCIE:DRP0D[2] | PCIE:BAR4[3] PCIE:DRP0D[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[0] PCIE:DRP0D[0] | PCIE:BAR4[1] PCIE:DRP0D[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[30] PCIE:DRP0C[14] | PCIE:BAR3[31] PCIE:DRP0C[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[28] PCIE:DRP0C[12] | PCIE:BAR3[29] PCIE:DRP0C[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[26] PCIE:DRP0C[10] | PCIE:BAR3[27] PCIE:DRP0C[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[24] PCIE:DRP0C[8] | PCIE:BAR3[25] PCIE:DRP0C[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[22] PCIE:DRP0C[6] | PCIE:BAR3[23] PCIE:DRP0C[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[20] PCIE:DRP0C[4] | PCIE:BAR3[21] PCIE:DRP0C[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[18] PCIE:DRP0C[2] | PCIE:BAR3[19] PCIE:DRP0C[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[16] PCIE:DRP0C[0] | PCIE:BAR3[17] PCIE:DRP0C[1] |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP29[14] | PCIE:DRP29[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP29[12] | PCIE:DRP29[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP29[10] PCIE:MSIX_CAP_PBA_BIR[1] | PCIE:DRP29[11] PCIE:MSIX_CAP_PBA_BIR[2] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP29[8] PCIE:MSIX_CAP_ON | PCIE:DRP29[9] PCIE:MSIX_CAP_PBA_BIR[0] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP29[6] PCIE:MSIX_CAP_NEXTPTR[6] | PCIE:DRP29[7] PCIE:MSIX_CAP_NEXTPTR[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP29[4] PCIE:MSIX_CAP_NEXTPTR[4] | PCIE:DRP29[5] PCIE:MSIX_CAP_NEXTPTR[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP29[2] PCIE:MSIX_CAP_NEXTPTR[2] | PCIE:DRP29[3] PCIE:MSIX_CAP_NEXTPTR[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP29[0] PCIE:MSIX_CAP_NEXTPTR[0] | PCIE:DRP29[1] PCIE:MSIX_CAP_NEXTPTR[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP28[14] PCIE:MSIX_CAP_ID[6] | PCIE:DRP28[15] PCIE:MSIX_CAP_ID[7] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP28[12] PCIE:MSIX_CAP_ID[4] | PCIE:DRP28[13] PCIE:MSIX_CAP_ID[5] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP28[10] PCIE:MSIX_CAP_ID[2] | PCIE:DRP28[11] PCIE:MSIX_CAP_ID[3] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP28[8] PCIE:MSIX_CAP_ID[0] | PCIE:DRP28[9] PCIE:MSIX_CAP_ID[1] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP28[6] PCIE:MSIX_BASE_PTR[6] | PCIE:DRP28[7] PCIE:MSIX_BASE_PTR[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP28[4] PCIE:MSIX_BASE_PTR[4] | PCIE:DRP28[5] PCIE:MSIX_BASE_PTR[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP28[2] PCIE:MSIX_BASE_PTR[2] | PCIE:DRP28[3] PCIE:MSIX_BASE_PTR[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP28[0] PCIE:MSIX_BASE_PTR[0] | PCIE:DRP28[1] PCIE:MSIX_BASE_PTR[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP27[14] | PCIE:DRP27[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP27[12] | PCIE:DRP27[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP27[10] | PCIE:DRP27[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP27[8] PCIE:MSI_CAP_ON | PCIE:DRP27[9] PCIE:MSI_CAP_PER_VECTOR_MASKING_CAPABLE |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP27[6] PCIE:MSI_CAP_NEXTPTR[6] | PCIE:DRP27[7] PCIE:MSI_CAP_NEXTPTR[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP27[4] PCIE:MSI_CAP_NEXTPTR[4] | PCIE:DRP27[5] PCIE:MSI_CAP_NEXTPTR[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP27[2] PCIE:MSI_CAP_NEXTPTR[2] | PCIE:DRP27[3] PCIE:MSI_CAP_NEXTPTR[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP27[0] PCIE:MSI_CAP_NEXTPTR[0] | PCIE:DRP27[1] PCIE:MSI_CAP_NEXTPTR[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP26[14] | PCIE:DRP26[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP26[12] | PCIE:DRP26[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP26[10] PCIE:MSI_CAP_MULTIMSGCAP[1] | PCIE:DRP26[11] PCIE:MSI_CAP_MULTIMSGCAP[2] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP26[8] PCIE:MSI_CAP_MULTIMSG_EXTENSION | PCIE:DRP26[9] PCIE:MSI_CAP_MULTIMSGCAP[0] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP26[6] PCIE:MSI_CAP_ID[6] | PCIE:DRP26[7] PCIE:MSI_CAP_ID[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP26[4] PCIE:MSI_CAP_ID[4] | PCIE:DRP26[5] PCIE:MSI_CAP_ID[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP26[2] PCIE:MSI_CAP_ID[2] | PCIE:DRP26[3] PCIE:MSI_CAP_ID[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP26[0] PCIE:MSI_CAP_ID[0] | PCIE:DRP26[1] PCIE:MSI_CAP_ID[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP25[14] | PCIE:DRP25[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP25[12] | PCIE:DRP25[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP25[10] | PCIE:DRP25[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP25[8] PCIE:MSI_CAP_64_BIT_ADDR_CAPABLE | PCIE:DRP25[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP25[6] PCIE:MSI_BASE_PTR[6] | PCIE:DRP25[7] PCIE:MSI_BASE_PTR[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP25[4] PCIE:MSI_BASE_PTR[4] | PCIE:DRP25[5] PCIE:MSI_BASE_PTR[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP25[2] PCIE:MSI_BASE_PTR[2] | PCIE:DRP25[3] PCIE:MSI_BASE_PTR[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP25[0] PCIE:MSI_BASE_PTR[0] | PCIE:DRP25[1] PCIE:MSI_BASE_PTR[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP24[14] | PCIE:DRP24[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP24[12] | PCIE:DRP24[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP24[10] | PCIE:DRP24[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP24[8] PCIE:LINK_STATUS_SLOT_CLOCK_CONFIG | PCIE:DRP24[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP24[6] PCIE:LINK_CTRL2_TARGET_LINK_SPEED[2] | PCIE:DRP24[7] PCIE:LINK_CTRL2_TARGET_LINK_SPEED[3] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP24[4] PCIE:LINK_CTRL2_TARGET_LINK_SPEED[0] | PCIE:DRP24[5] PCIE:LINK_CTRL2_TARGET_LINK_SPEED[1] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP24[2] PCIE:LINK_CTRL2_DEEMPHASIS | PCIE:DRP24[3] PCIE:LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP24[0] PCIE:LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE | PCIE:DRP24[1] PCIE:LINK_CONTROL_RCB |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5F[14] PCIE:SPARE_WORD0[30] | PCIE:DRP5F[15] PCIE:SPARE_WORD0[31] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5F[12] PCIE:SPARE_WORD0[28] | PCIE:DRP5F[13] PCIE:SPARE_WORD0[29] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5F[10] PCIE:SPARE_WORD0[26] | PCIE:DRP5F[11] PCIE:SPARE_WORD0[27] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5F[8] PCIE:SPARE_WORD0[24] | PCIE:DRP5F[9] PCIE:SPARE_WORD0[25] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5F[6] PCIE:SPARE_WORD0[22] | PCIE:DRP5F[7] PCIE:SPARE_WORD0[23] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5F[4] PCIE:SPARE_WORD0[20] | PCIE:DRP5F[5] PCIE:SPARE_WORD0[21] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5F[2] PCIE:SPARE_WORD0[18] | PCIE:DRP5F[3] PCIE:SPARE_WORD0[19] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5F[0] PCIE:SPARE_WORD0[16] | PCIE:DRP5F[1] PCIE:SPARE_WORD0[17] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5E[14] PCIE:SPARE_WORD0[14] | PCIE:DRP5E[15] PCIE:SPARE_WORD0[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5E[12] PCIE:SPARE_WORD0[12] | PCIE:DRP5E[13] PCIE:SPARE_WORD0[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5E[10] PCIE:SPARE_WORD0[10] | PCIE:DRP5E[11] PCIE:SPARE_WORD0[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5E[8] PCIE:SPARE_WORD0[8] | PCIE:DRP5E[9] PCIE:SPARE_WORD0[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5E[6] PCIE:SPARE_WORD0[6] | PCIE:DRP5E[7] PCIE:SPARE_WORD0[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5E[4] PCIE:SPARE_WORD0[4] | PCIE:DRP5E[5] PCIE:SPARE_WORD0[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5E[2] PCIE:SPARE_WORD0[2] | PCIE:DRP5E[3] PCIE:SPARE_WORD0[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5E[0] PCIE:SPARE_WORD0[0] | PCIE:DRP5E[1] PCIE:SPARE_WORD0[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5D[14] | PCIE:DRP5D[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5D[12] | PCIE:DRP5D[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5D[10] | PCIE:DRP5D[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5D[8] | PCIE:DRP5D[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5D[6] PCIE:SPARE_BYTE3[6] | PCIE:DRP5D[7] PCIE:SPARE_BYTE3[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5D[4] PCIE:SPARE_BYTE3[4] | PCIE:DRP5D[5] PCIE:SPARE_BYTE3[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5D[2] PCIE:SPARE_BYTE3[2] | PCIE:DRP5D[3] PCIE:SPARE_BYTE3[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5D[0] PCIE:SPARE_BYTE3[0] | PCIE:DRP5D[1] PCIE:SPARE_BYTE3[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5C[14] PCIE:SPARE_BYTE2[6] | PCIE:DRP5C[15] PCIE:SPARE_BYTE2[7] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5C[12] PCIE:SPARE_BYTE2[4] | PCIE:DRP5C[13] PCIE:SPARE_BYTE2[5] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5C[10] PCIE:SPARE_BYTE2[2] | PCIE:DRP5C[11] PCIE:SPARE_BYTE2[3] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5C[8] PCIE:SPARE_BYTE2[0] | PCIE:DRP5C[9] PCIE:SPARE_BYTE2[1] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5C[6] PCIE:SPARE_BYTE1[6] | PCIE:DRP5C[7] PCIE:SPARE_BYTE1[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5C[4] PCIE:SPARE_BYTE1[4] | PCIE:DRP5C[5] PCIE:SPARE_BYTE1[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5C[2] PCIE:SPARE_BYTE1[2] | PCIE:DRP5C[3] PCIE:SPARE_BYTE1[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5C[0] PCIE:SPARE_BYTE1[0] | PCIE:DRP5C[1] PCIE:SPARE_BYTE1[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5B[14] | PCIE:DRP5B[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5B[12] | PCIE:DRP5B[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5B[10] PCIE:SPARE_BYTE0[7] | PCIE:DRP5B[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5B[8] PCIE:SPARE_BYTE0[5] | PCIE:DRP5B[9] PCIE:SPARE_BYTE0[6] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5B[6] PCIE:SPARE_BYTE0[3] | PCIE:DRP5B[7] PCIE:SPARE_BYTE0[4] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5B[4] PCIE:SPARE_BYTE0[1] | PCIE:DRP5B[5] PCIE:SPARE_BYTE0[2] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5B[2] PCIE:SPARE_BIT8 | PCIE:DRP5B[3] PCIE:SPARE_BYTE0[0] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5B[0] PCIE:SPARE_BIT6 | PCIE:DRP5B[1] PCIE:SPARE_BIT7 |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5A[14] PCIE:SPARE_BIT4 | PCIE:DRP5A[15] PCIE:SPARE_BIT5 |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5A[12] PCIE:SPARE_BIT2 | PCIE:DRP5A[13] PCIE:SPARE_BIT3 |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5A[10] PCIE:SPARE_BIT0 | PCIE:DRP5A[11] PCIE:SPARE_BIT1 |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5A[8] PCIE:PGL7_LANE[2] | PCIE:DRP5A[9] PCIE:TEST_MODE_PIN_CHAR |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5A[6] PCIE:PGL7_LANE[0] | PCIE:DRP5A[7] PCIE:PGL7_LANE[1] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5A[4] PCIE:PGL6_LANE[1] | PCIE:DRP5A[5] PCIE:PGL6_LANE[2] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5A[2] PCIE:PGL5_LANE[2] | PCIE:DRP5A[3] PCIE:PGL6_LANE[0] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5A[0] PCIE:PGL5_LANE[0] | PCIE:DRP5A[1] PCIE:PGL5_LANE[1] |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6B[14] | PCIE:DRP6B[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6B[12] | PCIE:DRP6B[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6B[10] | PCIE:DRP6B[11] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6B[8] | PCIE:DRP6B[9] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6B[6] | PCIE:DRP6B[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6B[4] | PCIE:DRP6B[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6B[2] | PCIE:DRP6B[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6B[0] | PCIE:DRP6B[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6A[14] | PCIE:DRP6A[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6A[12] | PCIE:DRP6A[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6A[10] | PCIE:DRP6A[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6A[8] | PCIE:DRP6A[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6A[6] | PCIE:DRP6A[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6A[4] | PCIE:DRP6A[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6A[2] | PCIE:DRP6A[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6A[0] | PCIE:DRP6A[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP69[14] | PCIE:DRP69[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP69[12] | PCIE:DRP69[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP69[10] | PCIE:DRP69[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP69[8] | PCIE:DRP69[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP69[6] | PCIE:DRP69[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP69[4] | PCIE:DRP69[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP69[2] | PCIE:DRP69[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP69[0] | PCIE:DRP69[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP68[14] | PCIE:DRP68[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP68[12] | PCIE:DRP68[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP68[10] | PCIE:DRP68[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP68[8] | PCIE:DRP68[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP68[6] | PCIE:DRP68[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP68[4] | PCIE:DRP68[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP68[2] | PCIE:DRP68[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP68[0] | PCIE:DRP68[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP67[14] | PCIE:DRP67[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP67[12] | PCIE:DRP67[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP67[10] | PCIE:DRP67[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP67[8] | PCIE:DRP67[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP67[6] | PCIE:DRP67[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP67[4] | PCIE:DRP67[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP67[2] | PCIE:DRP67[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP67[0] | PCIE:DRP67[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP66[14] | PCIE:DRP66[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP66[12] | PCIE:DRP66[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP66[10] | PCIE:DRP66[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP66[8] | PCIE:DRP66[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP66[6] | PCIE:DRP66[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP66[4] | PCIE:DRP66[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP66[2] | PCIE:DRP66[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP66[0] | PCIE:DRP66[1] |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP71[14] | PCIE:DRP71[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP71[12] | PCIE:DRP71[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP71[10] | PCIE:DRP71[11] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP71[8] | PCIE:DRP71[9] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP71[6] | PCIE:DRP71[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP71[4] | PCIE:DRP71[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP71[2] | PCIE:DRP71[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP71[0] | PCIE:DRP71[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP70[14] | PCIE:DRP70[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP70[12] | PCIE:DRP70[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP70[10] | PCIE:DRP70[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP70[8] | PCIE:DRP70[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP70[6] | PCIE:DRP70[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP70[4] | PCIE:DRP70[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP70[2] | PCIE:DRP70[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP70[0] | PCIE:DRP70[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6F[14] | PCIE:DRP6F[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6F[12] | PCIE:DRP6F[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6F[10] | PCIE:DRP6F[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6F[8] | PCIE:DRP6F[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6F[6] | PCIE:DRP6F[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6F[4] | PCIE:DRP6F[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6F[2] | PCIE:DRP6F[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6F[0] | PCIE:DRP6F[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6E[14] | PCIE:DRP6E[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6E[12] | PCIE:DRP6E[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6E[10] | PCIE:DRP6E[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6E[8] | PCIE:DRP6E[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6E[6] | PCIE:DRP6E[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6E[4] | PCIE:DRP6E[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6E[2] | PCIE:DRP6E[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6E[0] | PCIE:DRP6E[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6D[14] | PCIE:DRP6D[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6D[12] | PCIE:DRP6D[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6D[10] | PCIE:DRP6D[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6D[8] | PCIE:DRP6D[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6D[6] | PCIE:DRP6D[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6D[4] | PCIE:DRP6D[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6D[2] | PCIE:DRP6D[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6D[0] | PCIE:DRP6D[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6C[14] | PCIE:DRP6C[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6C[12] | PCIE:DRP6C[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6C[10] | PCIE:DRP6C[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6C[8] | PCIE:DRP6C[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6C[6] | PCIE:DRP6C[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6C[4] | PCIE:DRP6C[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6C[2] | PCIE:DRP6C[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6C[0] | PCIE:DRP6C[1] |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP77[14] | PCIE:DRP77[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP77[12] | PCIE:DRP77[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP77[10] | PCIE:DRP77[11] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP77[8] | PCIE:DRP77[9] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP77[6] | PCIE:DRP77[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP77[4] | PCIE:DRP77[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP77[2] | PCIE:DRP77[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP77[0] | PCIE:DRP77[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP76[14] | PCIE:DRP76[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP76[12] | PCIE:DRP76[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP76[10] | PCIE:DRP76[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP76[8] | PCIE:DRP76[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP76[6] | PCIE:DRP76[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP76[4] | PCIE:DRP76[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP76[2] | PCIE:DRP76[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP76[0] | PCIE:DRP76[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP75[14] | PCIE:DRP75[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP75[12] | PCIE:DRP75[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP75[10] | PCIE:DRP75[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP75[8] | PCIE:DRP75[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP75[6] | PCIE:DRP75[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP75[4] | PCIE:DRP75[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP75[2] | PCIE:DRP75[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP75[0] | PCIE:DRP75[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP74[14] | PCIE:DRP74[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP74[12] | PCIE:DRP74[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP74[10] | PCIE:DRP74[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP74[8] | PCIE:DRP74[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP74[6] | PCIE:DRP74[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP74[4] | PCIE:DRP74[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP74[2] | PCIE:DRP74[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP74[0] | PCIE:DRP74[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP73[14] | PCIE:DRP73[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP73[12] | PCIE:DRP73[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP73[10] | PCIE:DRP73[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP73[8] | PCIE:DRP73[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP73[6] | PCIE:DRP73[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP73[4] | PCIE:DRP73[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP73[2] | PCIE:DRP73[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP73[0] | PCIE:DRP73[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP72[14] | PCIE:DRP72[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP72[12] | PCIE:DRP72[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP72[10] | PCIE:DRP72[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP72[8] | PCIE:DRP72[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP72[6] | PCIE:DRP72[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP72[4] | PCIE:DRP72[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP72[2] | PCIE:DRP72[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP72[0] | PCIE:DRP72[1] |
| PCIE:AER_BASE_PTR | 0.27.29 | 0.26.29 | 0.27.28 | 0.26.28 | 0.27.27 | 0.26.27 | 0.27.26 | 0.26.26 | 0.27.25 | 0.26.25 | 0.27.24 | 0.26.24 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:AER_CAP_NEXTPTR | 0.27.37 | 0.26.37 | 0.27.36 | 0.26.36 | 0.27.35 | 0.26.35 | 0.27.34 | 0.26.34 | 0.27.33 | 0.26.33 | 0.27.32 | 0.26.32 |
| PCIE:DSN_BASE_PTR | 4.27.29 | 4.26.29 | 4.27.28 | 4.26.28 | 4.27.27 | 4.26.27 | 4.27.26 | 4.26.26 | 4.27.25 | 4.26.25 | 4.27.24 | 4.26.24 |
| PCIE:DSN_CAP_NEXTPTR | 4.27.45 | 4.26.45 | 4.27.44 | 4.26.44 | 4.27.43 | 4.26.43 | 4.27.42 | 4.26.42 | 4.27.41 | 4.26.41 | 4.27.40 | 4.26.40 |
| PCIE:VC_BASE_PTR | 10.27.29 | 10.26.29 | 10.27.28 | 10.26.28 | 10.27.27 | 10.26.27 | 10.27.26 | 10.26.26 | 10.27.25 | 10.26.25 | 10.27.24 | 10.26.24 |
| PCIE:VC_CAP_NEXTPTR | 10.27.37 | 10.26.37 | 10.27.36 | 10.26.36 | 10.27.35 | 10.26.35 | 10.27.34 | 10.26.34 | 10.27.33 | 10.26.33 | 10.27.32 | 10.26.32 |
| PCIE:VSEC_BASE_PTR | 11.27.21 | 11.26.21 | 11.27.20 | 11.26.20 | 11.27.19 | 11.26.19 | 11.27.18 | 11.26.18 | 11.27.17 | 11.26.17 | 11.27.16 | 11.26.16 |
| PCIE:VSEC_CAP_HDR_LENGTH | 11.27.37 | 11.26.37 | 11.27.36 | 11.26.36 | 11.27.35 | 11.26.35 | 11.27.34 | 11.26.34 | 11.27.33 | 11.26.33 | 11.27.32 | 11.26.32 |
| PCIE:VSEC_CAP_NEXTPTR | 12.26.6 | 12.27.5 | 12.26.5 | 12.27.4 | 12.26.4 | 12.27.3 | 12.26.3 | 12.27.2 | 12.26.2 | 12.27.1 | 12.26.1 | 12.27.0 |
| non-inverted | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:AER_CAP_ECRC_CHECK_CAPABLE | 0.26.0 |
|---|---|
| PCIE:AER_CAP_ECRC_GEN_CAPABLE | 0.27.0 |
| PCIE:AER_CAP_ON | 0.26.38 |
| PCIE:AER_CAP_PERMIT_ROOTERR_UPDATE | 0.26.21 |
| PCIE:ALLOW_X8_GEN2 | 13.26.20 |
| PCIE:CMD_INTX_IMPLEMENTED | 3.26.44 |
| PCIE:CPL_TIMEOUT_DISABLE_SUPPORTED | 3.27.44 |
| PCIE:DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE | 3.26.47 |
| PCIE:DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE | 3.27.47 |
| PCIE:DEV_CAP_EXT_TAG_SUPPORTED | 4.26.3 |
| PCIE:DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE | 4.27.3 |
| PCIE:DEV_CAP_ROLE_BASED_ERROR | 4.27.6 |
| PCIE:DEV_CONTROL_AUX_POWER_SUPPORTED | 4.26.12 |
| PCIE:DISABLE_ASPM_L1_TIMER | 13.26.28 |
| PCIE:DISABLE_BAR_FILTERING | 13.27.28 |
| PCIE:DISABLE_ID_CHECK | 13.26.29 |
| PCIE:DISABLE_LANE_REVERSAL | 12.26.41 |
| PCIE:DISABLE_RX_TC_FILTER | 13.27.29 |
| PCIE:DISABLE_SCRAMBLING | 12.27.41 |
| PCIE:DSN_CAP_ON | 4.26.46 |
| PCIE:ENABLE_RX_TD_ECRC_TRIM | 13.27.37 |
| PCIE:ENTER_RVRY_EI_L0 | 12.26.42 |
| PCIE:EXIT_LOOPBACK_ON_EI | 13.27.23 |
| PCIE:IS_SWITCH | 5.26.24 |
| PCIE:LINK_CAP_CLOCK_POWER_MANAGEMENT | 5.27.30 |
| PCIE:LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP | 5.26.31 |
| PCIE:LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP | 5.27.44 |
| PCIE:LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE | 6.26.0 |
| PCIE:LINK_CONTROL_RCB | 6.27.0 |
| PCIE:LINK_CTRL2_DEEMPHASIS | 6.26.1 |
| PCIE:LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE | 6.27.1 |
| PCIE:LINK_STATUS_SLOT_CLOCK_CONFIG | 6.26.4 |
| PCIE:LL_ACK_TIMEOUT_EN | 12.27.23 |
| PCIE:LL_REPLAY_TIMEOUT_EN | 12.27.39 |
| PCIE:MSIX_CAP_ON | 6.26.44 |
| PCIE:MSI_CAP_64_BIT_ADDR_CAPABLE | 6.26.12 |
| PCIE:MSI_CAP_MULTIMSG_EXTENSION | 6.26.20 |
| PCIE:MSI_CAP_ON | 6.26.28 |
| PCIE:MSI_CAP_PER_VECTOR_MASKING_CAPABLE | 6.27.28 |
| PCIE:PCIE_CAP_ON | 8.26.12 |
| PCIE:PCIE_CAP_SLOT_IMPLEMENTED | 8.27.13 |
| PCIE:PL_FAST_TRAIN | 13.26.22 |
| PCIE:PM_CAP_D1SUPPORT | 8.27.21 |
| PCIE:PM_CAP_D2SUPPORT | 8.26.22 |
| PCIE:PM_CAP_DSI | 8.27.22 |
| PCIE:PM_CAP_ON | 8.26.32 |
| PCIE:PM_CAP_PME_CLOCK | 8.27.32 |
| PCIE:PM_CAP_RSVD_04 | 8.27.35 |
| PCIE:PM_CSR_B2B3 | 8.27.37 |
| PCIE:PM_CSR_BPCCEN | 8.26.38 |
| PCIE:PM_CSR_NOSOFTRST | 8.27.38 |
| PCIE:RECRC_CHK_TRIM | 14.26.39 |
| PCIE:ROOT_CAP_CRS_SW_VISIBILITY | 9.26.36 |
| PCIE:SELECT_DLL_IF | 9.27.36 |
| PCIE:SLOT_CAP_ATT_BUTTON_PRESENT | 9.26.37 |
| PCIE:SLOT_CAP_ATT_INDICATOR_PRESENT | 9.27.37 |
| PCIE:SLOT_CAP_ELEC_INTERLOCK_PRESENT | 9.26.38 |
| PCIE:SLOT_CAP_HOTPLUG_CAPABLE | 9.27.38 |
| PCIE:SLOT_CAP_HOTPLUG_SURPRISE | 9.26.39 |
| PCIE:SLOT_CAP_MRL_SENSOR_PRESENT | 9.27.39 |
| PCIE:SLOT_CAP_NO_CMD_COMPLETED_SUPPORT | 9.26.40 |
| PCIE:SLOT_CAP_POWER_CONTROLLER_PRESENT | 9.26.47 |
| PCIE:SLOT_CAP_POWER_INDICATOR_PRESENT | 9.27.47 |
| PCIE:SPARE_BIT0 | 15.26.5 |
| PCIE:SPARE_BIT1 | 15.27.5 |
| PCIE:SPARE_BIT2 | 15.26.6 |
| PCIE:SPARE_BIT3 | 15.27.6 |
| PCIE:SPARE_BIT4 | 15.26.7 |
| PCIE:SPARE_BIT5 | 15.27.7 |
| PCIE:SPARE_BIT6 | 15.26.8 |
| PCIE:SPARE_BIT7 | 15.27.8 |
| PCIE:SPARE_BIT8 | 15.26.9 |
| PCIE:TEST_MODE_PIN_CHAR | 15.27.4 |
| PCIE:TL_RBYPASS | 13.26.41 |
| PCIE:TL_RX_RAM_RADDR_LATENCY | 13.26.38 |
| PCIE:TL_RX_RAM_WRITE_LATENCY | 13.27.39 |
| PCIE:TL_TFC_DISABLE | 13.26.40 |
| PCIE:TL_TX_CHECKS_DISABLE | 13.27.40 |
| PCIE:TL_TX_RAM_RADDR_LATENCY | 13.27.41 |
| PCIE:TL_TX_RAM_WRITE_LATENCY | 13.26.43 |
| PCIE:UPCONFIG_CAPABLE | 13.27.22 |
| PCIE:UPSTREAM_FACING | 13.26.23 |
| PCIE:UR_INV_REQ | 14.27.39 |
| PCIE:VC0_CPL_INFINITE | 13.27.45 |
| PCIE:VC_CAP_ON | 10.26.38 |
| PCIE:VC_CAP_REJECT_SNOOP_TRANSACTIONS | 11.26.0 |
| PCIE:VSEC_CAP_IS_LINK_VISIBLE | 12.26.0 |
| PCIE:VSEC_CAP_ON | 12.27.6 |
| non-inverted | [0] |
| PCIE:AER_CAP_ID | 0.27.15 | 0.26.15 | 0.27.14 | 0.26.14 | 0.27.13 | 0.26.13 | 0.27.12 | 0.26.12 | 0.27.11 | 0.26.11 | 0.27.10 | 0.26.10 | 0.27.9 | 0.26.9 | 0.27.8 | 0.26.8 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:DEVICE_ID | 4.27.23 | 4.26.23 | 4.27.22 | 4.26.22 | 4.27.21 | 4.26.21 | 4.27.20 | 4.26.20 | 4.27.19 | 4.26.19 | 4.27.18 | 4.26.18 | 4.27.17 | 4.26.17 | 4.27.16 | 4.26.16 |
| PCIE:DRP00 | 0.27.7 | 0.26.7 | 0.27.6 | 0.26.6 | 0.27.5 | 0.26.5 | 0.27.4 | 0.26.4 | 0.27.3 | 0.26.3 | 0.27.2 | 0.26.2 | 0.27.1 | 0.26.1 | 0.27.0 | 0.26.0 |
| PCIE:DRP01 | 0.27.15 | 0.26.15 | 0.27.14 | 0.26.14 | 0.27.13 | 0.26.13 | 0.27.12 | 0.26.12 | 0.27.11 | 0.26.11 | 0.27.10 | 0.26.10 | 0.27.9 | 0.26.9 | 0.27.8 | 0.26.8 |
| PCIE:DRP02 | 0.27.23 | 0.26.23 | 0.27.22 | 0.26.22 | 0.27.21 | 0.26.21 | 0.27.20 | 0.26.20 | 0.27.19 | 0.26.19 | 0.27.18 | 0.26.18 | 0.27.17 | 0.26.17 | 0.27.16 | 0.26.16 |
| PCIE:DRP03 | 0.27.31 | 0.26.31 | 0.27.30 | 0.26.30 | 0.27.29 | 0.26.29 | 0.27.28 | 0.26.28 | 0.27.27 | 0.26.27 | 0.27.26 | 0.26.26 | 0.27.25 | 0.26.25 | 0.27.24 | 0.26.24 |
| PCIE:DRP04 | 0.27.39 | 0.26.39 | 0.27.38 | 0.26.38 | 0.27.37 | 0.26.37 | 0.27.36 | 0.26.36 | 0.27.35 | 0.26.35 | 0.27.34 | 0.26.34 | 0.27.33 | 0.26.33 | 0.27.32 | 0.26.32 |
| PCIE:DRP05 | 0.27.47 | 0.26.47 | 0.27.46 | 0.26.46 | 0.27.45 | 0.26.45 | 0.27.44 | 0.26.44 | 0.27.43 | 0.26.43 | 0.27.42 | 0.26.42 | 0.27.41 | 0.26.41 | 0.27.40 | 0.26.40 |
| PCIE:DRP06 | 1.27.7 | 1.26.7 | 1.27.6 | 1.26.6 | 1.27.5 | 1.26.5 | 1.27.4 | 1.26.4 | 1.27.3 | 1.26.3 | 1.27.2 | 1.26.2 | 1.27.1 | 1.26.1 | 1.27.0 | 1.26.0 |
| PCIE:DRP07 | 1.27.15 | 1.26.15 | 1.27.14 | 1.26.14 | 1.27.13 | 1.26.13 | 1.27.12 | 1.26.12 | 1.27.11 | 1.26.11 | 1.27.10 | 1.26.10 | 1.27.9 | 1.26.9 | 1.27.8 | 1.26.8 |
| PCIE:DRP08 | 1.27.23 | 1.26.23 | 1.27.22 | 1.26.22 | 1.27.21 | 1.26.21 | 1.27.20 | 1.26.20 | 1.27.19 | 1.26.19 | 1.27.18 | 1.26.18 | 1.27.17 | 1.26.17 | 1.27.16 | 1.26.16 |
| PCIE:DRP09 | 1.27.31 | 1.26.31 | 1.27.30 | 1.26.30 | 1.27.29 | 1.26.29 | 1.27.28 | 1.26.28 | 1.27.27 | 1.26.27 | 1.27.26 | 1.26.26 | 1.27.25 | 1.26.25 | 1.27.24 | 1.26.24 |
| PCIE:DRP0A | 1.27.39 | 1.26.39 | 1.27.38 | 1.26.38 | 1.27.37 | 1.26.37 | 1.27.36 | 1.26.36 | 1.27.35 | 1.26.35 | 1.27.34 | 1.26.34 | 1.27.33 | 1.26.33 | 1.27.32 | 1.26.32 |
| PCIE:DRP0B | 1.27.47 | 1.26.47 | 1.27.46 | 1.26.46 | 1.27.45 | 1.26.45 | 1.27.44 | 1.26.44 | 1.27.43 | 1.26.43 | 1.27.42 | 1.26.42 | 1.27.41 | 1.26.41 | 1.27.40 | 1.26.40 |
| PCIE:DRP0C | 2.27.7 | 2.26.7 | 2.27.6 | 2.26.6 | 2.27.5 | 2.26.5 | 2.27.4 | 2.26.4 | 2.27.3 | 2.26.3 | 2.27.2 | 2.26.2 | 2.27.1 | 2.26.1 | 2.27.0 | 2.26.0 |
| PCIE:DRP0D | 2.27.15 | 2.26.15 | 2.27.14 | 2.26.14 | 2.27.13 | 2.26.13 | 2.27.12 | 2.26.12 | 2.27.11 | 2.26.11 | 2.27.10 | 2.26.10 | 2.27.9 | 2.26.9 | 2.27.8 | 2.26.8 |
| PCIE:DRP0E | 2.27.23 | 2.26.23 | 2.27.22 | 2.26.22 | 2.27.21 | 2.26.21 | 2.27.20 | 2.26.20 | 2.27.19 | 2.26.19 | 2.27.18 | 2.26.18 | 2.27.17 | 2.26.17 | 2.27.16 | 2.26.16 |
| PCIE:DRP0F | 2.27.31 | 2.26.31 | 2.27.30 | 2.26.30 | 2.27.29 | 2.26.29 | 2.27.28 | 2.26.28 | 2.27.27 | 2.26.27 | 2.27.26 | 2.26.26 | 2.27.25 | 2.26.25 | 2.27.24 | 2.26.24 |
| PCIE:DRP10 | 2.27.39 | 2.26.39 | 2.27.38 | 2.26.38 | 2.27.37 | 2.26.37 | 2.27.36 | 2.26.36 | 2.27.35 | 2.26.35 | 2.27.34 | 2.26.34 | 2.27.33 | 2.26.33 | 2.27.32 | 2.26.32 |
| PCIE:DRP11 | 2.27.47 | 2.26.47 | 2.27.46 | 2.26.46 | 2.27.45 | 2.26.45 | 2.27.44 | 2.26.44 | 2.27.43 | 2.26.43 | 2.27.42 | 2.26.42 | 2.27.41 | 2.26.41 | 2.27.40 | 2.26.40 |
| PCIE:DRP12 | 3.27.7 | 3.26.7 | 3.27.6 | 3.26.6 | 3.27.5 | 3.26.5 | 3.27.4 | 3.26.4 | 3.27.3 | 3.26.3 | 3.27.2 | 3.26.2 | 3.27.1 | 3.26.1 | 3.27.0 | 3.26.0 |
| PCIE:DRP13 | 3.27.15 | 3.26.15 | 3.27.14 | 3.26.14 | 3.27.13 | 3.26.13 | 3.27.12 | 3.26.12 | 3.27.11 | 3.26.11 | 3.27.10 | 3.26.10 | 3.27.9 | 3.26.9 | 3.27.8 | 3.26.8 |
| PCIE:DRP14 | 3.27.23 | 3.26.23 | 3.27.22 | 3.26.22 | 3.27.21 | 3.26.21 | 3.27.20 | 3.26.20 | 3.27.19 | 3.26.19 | 3.27.18 | 3.26.18 | 3.27.17 | 3.26.17 | 3.27.16 | 3.26.16 |
| PCIE:DRP15 | 3.27.31 | 3.26.31 | 3.27.30 | 3.26.30 | 3.27.29 | 3.26.29 | 3.27.28 | 3.26.28 | 3.27.27 | 3.26.27 | 3.27.26 | 3.26.26 | 3.27.25 | 3.26.25 | 3.27.24 | 3.26.24 |
| PCIE:DRP16 | 3.27.39 | 3.26.39 | 3.27.38 | 3.26.38 | 3.27.37 | 3.26.37 | 3.27.36 | 3.26.36 | 3.27.35 | 3.26.35 | 3.27.34 | 3.26.34 | 3.27.33 | 3.26.33 | 3.27.32 | 3.26.32 |
| PCIE:DRP17 | 3.27.47 | 3.26.47 | 3.27.46 | 3.26.46 | 3.27.45 | 3.26.45 | 3.27.44 | 3.26.44 | 3.27.43 | 3.26.43 | 3.27.42 | 3.26.42 | 3.27.41 | 3.26.41 | 3.27.40 | 3.26.40 |
| PCIE:DRP18 | 4.27.7 | 4.26.7 | 4.27.6 | 4.26.6 | 4.27.5 | 4.26.5 | 4.27.4 | 4.26.4 | 4.27.3 | 4.26.3 | 4.27.2 | 4.26.2 | 4.27.1 | 4.26.1 | 4.27.0 | 4.26.0 |
| PCIE:DRP19 | 4.27.15 | 4.26.15 | 4.27.14 | 4.26.14 | 4.27.13 | 4.26.13 | 4.27.12 | 4.26.12 | 4.27.11 | 4.26.11 | 4.27.10 | 4.26.10 | 4.27.9 | 4.26.9 | 4.27.8 | 4.26.8 |
| PCIE:DRP1A | 4.27.23 | 4.26.23 | 4.27.22 | 4.26.22 | 4.27.21 | 4.26.21 | 4.27.20 | 4.26.20 | 4.27.19 | 4.26.19 | 4.27.18 | 4.26.18 | 4.27.17 | 4.26.17 | 4.27.16 | 4.26.16 |
| PCIE:DRP1B | 4.27.31 | 4.26.31 | 4.27.30 | 4.26.30 | 4.27.29 | 4.26.29 | 4.27.28 | 4.26.28 | 4.27.27 | 4.26.27 | 4.27.26 | 4.26.26 | 4.27.25 | 4.26.25 | 4.27.24 | 4.26.24 |
| PCIE:DRP1C | 4.27.39 | 4.26.39 | 4.27.38 | 4.26.38 | 4.27.37 | 4.26.37 | 4.27.36 | 4.26.36 | 4.27.35 | 4.26.35 | 4.27.34 | 4.26.34 | 4.27.33 | 4.26.33 | 4.27.32 | 4.26.32 |
| PCIE:DRP1D | 4.27.47 | 4.26.47 | 4.27.46 | 4.26.46 | 4.27.45 | 4.26.45 | 4.27.44 | 4.26.44 | 4.27.43 | 4.26.43 | 4.27.42 | 4.26.42 | 4.27.41 | 4.26.41 | 4.27.40 | 4.26.40 |
| PCIE:DRP1E | 5.27.7 | 5.26.7 | 5.27.6 | 5.26.6 | 5.27.5 | 5.26.5 | 5.27.4 | 5.26.4 | 5.27.3 | 5.26.3 | 5.27.2 | 5.26.2 | 5.27.1 | 5.26.1 | 5.27.0 | 5.26.0 |
| PCIE:DRP1F | 5.27.15 | 5.26.15 | 5.27.14 | 5.26.14 | 5.27.13 | 5.26.13 | 5.27.12 | 5.26.12 | 5.27.11 | 5.26.11 | 5.27.10 | 5.26.10 | 5.27.9 | 5.26.9 | 5.27.8 | 5.26.8 |
| PCIE:DRP20 | 5.27.23 | 5.26.23 | 5.27.22 | 5.26.22 | 5.27.21 | 5.26.21 | 5.27.20 | 5.26.20 | 5.27.19 | 5.26.19 | 5.27.18 | 5.26.18 | 5.27.17 | 5.26.17 | 5.27.16 | 5.26.16 |
| PCIE:DRP21 | 5.27.31 | 5.26.31 | 5.27.30 | 5.26.30 | 5.27.29 | 5.26.29 | 5.27.28 | 5.26.28 | 5.27.27 | 5.26.27 | 5.27.26 | 5.26.26 | 5.27.25 | 5.26.25 | 5.27.24 | 5.26.24 |
| PCIE:DRP22 | 5.27.39 | 5.26.39 | 5.27.38 | 5.26.38 | 5.27.37 | 5.26.37 | 5.27.36 | 5.26.36 | 5.27.35 | 5.26.35 | 5.27.34 | 5.26.34 | 5.27.33 | 5.26.33 | 5.27.32 | 5.26.32 |
| PCIE:DRP23 | 5.27.47 | 5.26.47 | 5.27.46 | 5.26.46 | 5.27.45 | 5.26.45 | 5.27.44 | 5.26.44 | 5.27.43 | 5.26.43 | 5.27.42 | 5.26.42 | 5.27.41 | 5.26.41 | 5.27.40 | 5.26.40 |
| PCIE:DRP24 | 6.27.7 | 6.26.7 | 6.27.6 | 6.26.6 | 6.27.5 | 6.26.5 | 6.27.4 | 6.26.4 | 6.27.3 | 6.26.3 | 6.27.2 | 6.26.2 | 6.27.1 | 6.26.1 | 6.27.0 | 6.26.0 |
| PCIE:DRP25 | 6.27.15 | 6.26.15 | 6.27.14 | 6.26.14 | 6.27.13 | 6.26.13 | 6.27.12 | 6.26.12 | 6.27.11 | 6.26.11 | 6.27.10 | 6.26.10 | 6.27.9 | 6.26.9 | 6.27.8 | 6.26.8 |
| PCIE:DRP26 | 6.27.23 | 6.26.23 | 6.27.22 | 6.26.22 | 6.27.21 | 6.26.21 | 6.27.20 | 6.26.20 | 6.27.19 | 6.26.19 | 6.27.18 | 6.26.18 | 6.27.17 | 6.26.17 | 6.27.16 | 6.26.16 |
| PCIE:DRP27 | 6.27.31 | 6.26.31 | 6.27.30 | 6.26.30 | 6.27.29 | 6.26.29 | 6.27.28 | 6.26.28 | 6.27.27 | 6.26.27 | 6.27.26 | 6.26.26 | 6.27.25 | 6.26.25 | 6.27.24 | 6.26.24 |
| PCIE:DRP28 | 6.27.39 | 6.26.39 | 6.27.38 | 6.26.38 | 6.27.37 | 6.26.37 | 6.27.36 | 6.26.36 | 6.27.35 | 6.26.35 | 6.27.34 | 6.26.34 | 6.27.33 | 6.26.33 | 6.27.32 | 6.26.32 |
| PCIE:DRP29 | 6.27.47 | 6.26.47 | 6.27.46 | 6.26.46 | 6.27.45 | 6.26.45 | 6.27.44 | 6.26.44 | 6.27.43 | 6.26.43 | 6.27.42 | 6.26.42 | 6.27.41 | 6.26.41 | 6.27.40 | 6.26.40 |
| PCIE:DRP2A | 7.27.7 | 7.26.7 | 7.27.6 | 7.26.6 | 7.27.5 | 7.26.5 | 7.27.4 | 7.26.4 | 7.27.3 | 7.26.3 | 7.27.2 | 7.26.2 | 7.27.1 | 7.26.1 | 7.27.0 | 7.26.0 |
| PCIE:DRP2B | 7.27.15 | 7.26.15 | 7.27.14 | 7.26.14 | 7.27.13 | 7.26.13 | 7.27.12 | 7.26.12 | 7.27.11 | 7.26.11 | 7.27.10 | 7.26.10 | 7.27.9 | 7.26.9 | 7.27.8 | 7.26.8 |
| PCIE:DRP2C | 7.27.23 | 7.26.23 | 7.27.22 | 7.26.22 | 7.27.21 | 7.26.21 | 7.27.20 | 7.26.20 | 7.27.19 | 7.26.19 | 7.27.18 | 7.26.18 | 7.27.17 | 7.26.17 | 7.27.16 | 7.26.16 |
| PCIE:DRP2D | 7.27.31 | 7.26.31 | 7.27.30 | 7.26.30 | 7.27.29 | 7.26.29 | 7.27.28 | 7.26.28 | 7.27.27 | 7.26.27 | 7.27.26 | 7.26.26 | 7.27.25 | 7.26.25 | 7.27.24 | 7.26.24 |
| PCIE:DRP2E | 7.27.39 | 7.26.39 | 7.27.38 | 7.26.38 | 7.27.37 | 7.26.37 | 7.27.36 | 7.26.36 | 7.27.35 | 7.26.35 | 7.27.34 | 7.26.34 | 7.27.33 | 7.26.33 | 7.27.32 | 7.26.32 |
| PCIE:DRP2F | 7.27.47 | 7.26.47 | 7.27.46 | 7.26.46 | 7.27.45 | 7.26.45 | 7.27.44 | 7.26.44 | 7.27.43 | 7.26.43 | 7.27.42 | 7.26.42 | 7.27.41 | 7.26.41 | 7.27.40 | 7.26.40 |
| PCIE:DRP30 | 8.27.7 | 8.26.7 | 8.27.6 | 8.26.6 | 8.27.5 | 8.26.5 | 8.27.4 | 8.26.4 | 8.27.3 | 8.26.3 | 8.27.2 | 8.26.2 | 8.27.1 | 8.26.1 | 8.27.0 | 8.26.0 |
| PCIE:DRP31 | 8.27.15 | 8.26.15 | 8.27.14 | 8.26.14 | 8.27.13 | 8.26.13 | 8.27.12 | 8.26.12 | 8.27.11 | 8.26.11 | 8.27.10 | 8.26.10 | 8.27.9 | 8.26.9 | 8.27.8 | 8.26.8 |
| PCIE:DRP32 | 8.27.23 | 8.26.23 | 8.27.22 | 8.26.22 | 8.27.21 | 8.26.21 | 8.27.20 | 8.26.20 | 8.27.19 | 8.26.19 | 8.27.18 | 8.26.18 | 8.27.17 | 8.26.17 | 8.27.16 | 8.26.16 |
| PCIE:DRP33 | 8.27.31 | 8.26.31 | 8.27.30 | 8.26.30 | 8.27.29 | 8.26.29 | 8.27.28 | 8.26.28 | 8.27.27 | 8.26.27 | 8.27.26 | 8.26.26 | 8.27.25 | 8.26.25 | 8.27.24 | 8.26.24 |
| PCIE:DRP34 | 8.27.39 | 8.26.39 | 8.27.38 | 8.26.38 | 8.27.37 | 8.26.37 | 8.27.36 | 8.26.36 | 8.27.35 | 8.26.35 | 8.27.34 | 8.26.34 | 8.27.33 | 8.26.33 | 8.27.32 | 8.26.32 |
| PCIE:DRP35 | 8.27.47 | 8.26.47 | 8.27.46 | 8.26.46 | 8.27.45 | 8.26.45 | 8.27.44 | 8.26.44 | 8.27.43 | 8.26.43 | 8.27.42 | 8.26.42 | 8.27.41 | 8.26.41 | 8.27.40 | 8.26.40 |
| PCIE:DRP36 | 9.27.7 | 9.26.7 | 9.27.6 | 9.26.6 | 9.27.5 | 9.26.5 | 9.27.4 | 9.26.4 | 9.27.3 | 9.26.3 | 9.27.2 | 9.26.2 | 9.27.1 | 9.26.1 | 9.27.0 | 9.26.0 |
| PCIE:DRP37 | 9.27.15 | 9.26.15 | 9.27.14 | 9.26.14 | 9.27.13 | 9.26.13 | 9.27.12 | 9.26.12 | 9.27.11 | 9.26.11 | 9.27.10 | 9.26.10 | 9.27.9 | 9.26.9 | 9.27.8 | 9.26.8 |
| PCIE:DRP38 | 9.27.23 | 9.26.23 | 9.27.22 | 9.26.22 | 9.27.21 | 9.26.21 | 9.27.20 | 9.26.20 | 9.27.19 | 9.26.19 | 9.27.18 | 9.26.18 | 9.27.17 | 9.26.17 | 9.27.16 | 9.26.16 |
| PCIE:DRP39 | 9.27.31 | 9.26.31 | 9.27.30 | 9.26.30 | 9.27.29 | 9.26.29 | 9.27.28 | 9.26.28 | 9.27.27 | 9.26.27 | 9.27.26 | 9.26.26 | 9.27.25 | 9.26.25 | 9.27.24 | 9.26.24 |
| PCIE:DRP3A | 9.27.39 | 9.26.39 | 9.27.38 | 9.26.38 | 9.27.37 | 9.26.37 | 9.27.36 | 9.26.36 | 9.27.35 | 9.26.35 | 9.27.34 | 9.26.34 | 9.27.33 | 9.26.33 | 9.27.32 | 9.26.32 |
| PCIE:DRP3B | 9.27.47 | 9.26.47 | 9.27.46 | 9.26.46 | 9.27.45 | 9.26.45 | 9.27.44 | 9.26.44 | 9.27.43 | 9.26.43 | 9.27.42 | 9.26.42 | 9.27.41 | 9.26.41 | 9.27.40 | 9.26.40 |
| PCIE:DRP3C | 10.27.7 | 10.26.7 | 10.27.6 | 10.26.6 | 10.27.5 | 10.26.5 | 10.27.4 | 10.26.4 | 10.27.3 | 10.26.3 | 10.27.2 | 10.26.2 | 10.27.1 | 10.26.1 | 10.27.0 | 10.26.0 |
| PCIE:DRP3D | 10.27.15 | 10.26.15 | 10.27.14 | 10.26.14 | 10.27.13 | 10.26.13 | 10.27.12 | 10.26.12 | 10.27.11 | 10.26.11 | 10.27.10 | 10.26.10 | 10.27.9 | 10.26.9 | 10.27.8 | 10.26.8 |
| PCIE:DRP3E | 10.27.23 | 10.26.23 | 10.27.22 | 10.26.22 | 10.27.21 | 10.26.21 | 10.27.20 | 10.26.20 | 10.27.19 | 10.26.19 | 10.27.18 | 10.26.18 | 10.27.17 | 10.26.17 | 10.27.16 | 10.26.16 |
| PCIE:DRP3F | 10.27.31 | 10.26.31 | 10.27.30 | 10.26.30 | 10.27.29 | 10.26.29 | 10.27.28 | 10.26.28 | 10.27.27 | 10.26.27 | 10.27.26 | 10.26.26 | 10.27.25 | 10.26.25 | 10.27.24 | 10.26.24 |
| PCIE:DRP40 | 10.27.39 | 10.26.39 | 10.27.38 | 10.26.38 | 10.27.37 | 10.26.37 | 10.27.36 | 10.26.36 | 10.27.35 | 10.26.35 | 10.27.34 | 10.26.34 | 10.27.33 | 10.26.33 | 10.27.32 | 10.26.32 |
| PCIE:DRP41 | 10.27.47 | 10.26.47 | 10.27.46 | 10.26.46 | 10.27.45 | 10.26.45 | 10.27.44 | 10.26.44 | 10.27.43 | 10.26.43 | 10.27.42 | 10.26.42 | 10.27.41 | 10.26.41 | 10.27.40 | 10.26.40 |
| PCIE:DRP42 | 11.27.7 | 11.26.7 | 11.27.6 | 11.26.6 | 11.27.5 | 11.26.5 | 11.27.4 | 11.26.4 | 11.27.3 | 11.26.3 | 11.27.2 | 11.26.2 | 11.27.1 | 11.26.1 | 11.27.0 | 11.26.0 |
| PCIE:DRP43 | 11.27.15 | 11.26.15 | 11.27.14 | 11.26.14 | 11.27.13 | 11.26.13 | 11.27.12 | 11.26.12 | 11.27.11 | 11.26.11 | 11.27.10 | 11.26.10 | 11.27.9 | 11.26.9 | 11.27.8 | 11.26.8 |
| PCIE:DRP44 | 11.27.23 | 11.26.23 | 11.27.22 | 11.26.22 | 11.27.21 | 11.26.21 | 11.27.20 | 11.26.20 | 11.27.19 | 11.26.19 | 11.27.18 | 11.26.18 | 11.27.17 | 11.26.17 | 11.27.16 | 11.26.16 |
| PCIE:DRP45 | 11.27.31 | 11.26.31 | 11.27.30 | 11.26.30 | 11.27.29 | 11.26.29 | 11.27.28 | 11.26.28 | 11.27.27 | 11.26.27 | 11.27.26 | 11.26.26 | 11.27.25 | 11.26.25 | 11.27.24 | 11.26.24 |
| PCIE:DRP46 | 11.27.39 | 11.26.39 | 11.27.38 | 11.26.38 | 11.27.37 | 11.26.37 | 11.27.36 | 11.26.36 | 11.27.35 | 11.26.35 | 11.27.34 | 11.26.34 | 11.27.33 | 11.26.33 | 11.27.32 | 11.26.32 |
| PCIE:DRP47 | 11.27.47 | 11.26.47 | 11.27.46 | 11.26.46 | 11.27.45 | 11.26.45 | 11.27.44 | 11.26.44 | 11.27.43 | 11.26.43 | 11.27.42 | 11.26.42 | 11.27.41 | 11.26.41 | 11.27.40 | 11.26.40 |
| PCIE:DRP48 | 12.27.7 | 12.26.7 | 12.27.6 | 12.26.6 | 12.27.5 | 12.26.5 | 12.27.4 | 12.26.4 | 12.27.3 | 12.26.3 | 12.27.2 | 12.26.2 | 12.27.1 | 12.26.1 | 12.27.0 | 12.26.0 |
| PCIE:DRP49 | 12.27.15 | 12.26.15 | 12.27.14 | 12.26.14 | 12.27.13 | 12.26.13 | 12.27.12 | 12.26.12 | 12.27.11 | 12.26.11 | 12.27.10 | 12.26.10 | 12.27.9 | 12.26.9 | 12.27.8 | 12.26.8 |
| PCIE:DRP4A | 12.27.23 | 12.26.23 | 12.27.22 | 12.26.22 | 12.27.21 | 12.26.21 | 12.27.20 | 12.26.20 | 12.27.19 | 12.26.19 | 12.27.18 | 12.26.18 | 12.27.17 | 12.26.17 | 12.27.16 | 12.26.16 |
| PCIE:DRP4B | 12.27.31 | 12.26.31 | 12.27.30 | 12.26.30 | 12.27.29 | 12.26.29 | 12.27.28 | 12.26.28 | 12.27.27 | 12.26.27 | 12.27.26 | 12.26.26 | 12.27.25 | 12.26.25 | 12.27.24 | 12.26.24 |
| PCIE:DRP4C | 12.27.39 | 12.26.39 | 12.27.38 | 12.26.38 | 12.27.37 | 12.26.37 | 12.27.36 | 12.26.36 | 12.27.35 | 12.26.35 | 12.27.34 | 12.26.34 | 12.27.33 | 12.26.33 | 12.27.32 | 12.26.32 |
| PCIE:DRP4D | 12.27.47 | 12.26.47 | 12.27.46 | 12.26.46 | 12.27.45 | 12.26.45 | 12.27.44 | 12.26.44 | 12.27.43 | 12.26.43 | 12.27.42 | 12.26.42 | 12.27.41 | 12.26.41 | 12.27.40 | 12.26.40 |
| PCIE:DRP4E | 13.27.7 | 13.26.7 | 13.27.6 | 13.26.6 | 13.27.5 | 13.26.5 | 13.27.4 | 13.26.4 | 13.27.3 | 13.26.3 | 13.27.2 | 13.26.2 | 13.27.1 | 13.26.1 | 13.27.0 | 13.26.0 |
| PCIE:DRP4F | 13.27.15 | 13.26.15 | 13.27.14 | 13.26.14 | 13.27.13 | 13.26.13 | 13.27.12 | 13.26.12 | 13.27.11 | 13.26.11 | 13.27.10 | 13.26.10 | 13.27.9 | 13.26.9 | 13.27.8 | 13.26.8 |
| PCIE:DRP50 | 13.27.23 | 13.26.23 | 13.27.22 | 13.26.22 | 13.27.21 | 13.26.21 | 13.27.20 | 13.26.20 | 13.27.19 | 13.26.19 | 13.27.18 | 13.26.18 | 13.27.17 | 13.26.17 | 13.27.16 | 13.26.16 |
| PCIE:DRP51 | 13.27.31 | 13.26.31 | 13.27.30 | 13.26.30 | 13.27.29 | 13.26.29 | 13.27.28 | 13.26.28 | 13.27.27 | 13.26.27 | 13.27.26 | 13.26.26 | 13.27.25 | 13.26.25 | 13.27.24 | 13.26.24 |
| PCIE:DRP52 | 13.27.39 | 13.26.39 | 13.27.38 | 13.26.38 | 13.27.37 | 13.26.37 | 13.27.36 | 13.26.36 | 13.27.35 | 13.26.35 | 13.27.34 | 13.26.34 | 13.27.33 | 13.26.33 | 13.27.32 | 13.26.32 |
| PCIE:DRP53 | 13.27.47 | 13.26.47 | 13.27.46 | 13.26.46 | 13.27.45 | 13.26.45 | 13.27.44 | 13.26.44 | 13.27.43 | 13.26.43 | 13.27.42 | 13.26.42 | 13.27.41 | 13.26.41 | 13.27.40 | 13.26.40 |
| PCIE:DRP54 | 14.27.7 | 14.26.7 | 14.27.6 | 14.26.6 | 14.27.5 | 14.26.5 | 14.27.4 | 14.26.4 | 14.27.3 | 14.26.3 | 14.27.2 | 14.26.2 | 14.27.1 | 14.26.1 | 14.27.0 | 14.26.0 |
| PCIE:DRP55 | 14.27.15 | 14.26.15 | 14.27.14 | 14.26.14 | 14.27.13 | 14.26.13 | 14.27.12 | 14.26.12 | 14.27.11 | 14.26.11 | 14.27.10 | 14.26.10 | 14.27.9 | 14.26.9 | 14.27.8 | 14.26.8 |
| PCIE:DRP56 | 14.27.23 | 14.26.23 | 14.27.22 | 14.26.22 | 14.27.21 | 14.26.21 | 14.27.20 | 14.26.20 | 14.27.19 | 14.26.19 | 14.27.18 | 14.26.18 | 14.27.17 | 14.26.17 | 14.27.16 | 14.26.16 |
| PCIE:DRP57 | 14.27.31 | 14.26.31 | 14.27.30 | 14.26.30 | 14.27.29 | 14.26.29 | 14.27.28 | 14.26.28 | 14.27.27 | 14.26.27 | 14.27.26 | 14.26.26 | 14.27.25 | 14.26.25 | 14.27.24 | 14.26.24 |
| PCIE:DRP58 | 14.27.39 | 14.26.39 | 14.27.38 | 14.26.38 | 14.27.37 | 14.26.37 | 14.27.36 | 14.26.36 | 14.27.35 | 14.26.35 | 14.27.34 | 14.26.34 | 14.27.33 | 14.26.33 | 14.27.32 | 14.26.32 |
| PCIE:DRP59 | 14.27.47 | 14.26.47 | 14.27.46 | 14.26.46 | 14.27.45 | 14.26.45 | 14.27.44 | 14.26.44 | 14.27.43 | 14.26.43 | 14.27.42 | 14.26.42 | 14.27.41 | 14.26.41 | 14.27.40 | 14.26.40 |
| PCIE:DRP5A | 15.27.7 | 15.26.7 | 15.27.6 | 15.26.6 | 15.27.5 | 15.26.5 | 15.27.4 | 15.26.4 | 15.27.3 | 15.26.3 | 15.27.2 | 15.26.2 | 15.27.1 | 15.26.1 | 15.27.0 | 15.26.0 |
| PCIE:DRP5B | 15.27.15 | 15.26.15 | 15.27.14 | 15.26.14 | 15.27.13 | 15.26.13 | 15.27.12 | 15.26.12 | 15.27.11 | 15.26.11 | 15.27.10 | 15.26.10 | 15.27.9 | 15.26.9 | 15.27.8 | 15.26.8 |
| PCIE:DRP5C | 15.27.23 | 15.26.23 | 15.27.22 | 15.26.22 | 15.27.21 | 15.26.21 | 15.27.20 | 15.26.20 | 15.27.19 | 15.26.19 | 15.27.18 | 15.26.18 | 15.27.17 | 15.26.17 | 15.27.16 | 15.26.16 |
| PCIE:DRP5D | 15.27.31 | 15.26.31 | 15.27.30 | 15.26.30 | 15.27.29 | 15.26.29 | 15.27.28 | 15.26.28 | 15.27.27 | 15.26.27 | 15.27.26 | 15.26.26 | 15.27.25 | 15.26.25 | 15.27.24 | 15.26.24 |
| PCIE:DRP5E | 15.27.39 | 15.26.39 | 15.27.38 | 15.26.38 | 15.27.37 | 15.26.37 | 15.27.36 | 15.26.36 | 15.27.35 | 15.26.35 | 15.27.34 | 15.26.34 | 15.27.33 | 15.26.33 | 15.27.32 | 15.26.32 |
| PCIE:DRP5F | 15.27.47 | 15.26.47 | 15.27.46 | 15.26.46 | 15.27.45 | 15.26.45 | 15.27.44 | 15.26.44 | 15.27.43 | 15.26.43 | 15.27.42 | 15.26.42 | 15.27.41 | 15.26.41 | 15.27.40 | 15.26.40 |
| PCIE:DRP60 | 16.27.7 | 16.26.7 | 16.27.6 | 16.26.6 | 16.27.5 | 16.26.5 | 16.27.4 | 16.26.4 | 16.27.3 | 16.26.3 | 16.27.2 | 16.26.2 | 16.27.1 | 16.26.1 | 16.27.0 | 16.26.0 |
| PCIE:DRP61 | 16.27.15 | 16.26.15 | 16.27.14 | 16.26.14 | 16.27.13 | 16.26.13 | 16.27.12 | 16.26.12 | 16.27.11 | 16.26.11 | 16.27.10 | 16.26.10 | 16.27.9 | 16.26.9 | 16.27.8 | 16.26.8 |
| PCIE:DRP62 | 16.27.23 | 16.26.23 | 16.27.22 | 16.26.22 | 16.27.21 | 16.26.21 | 16.27.20 | 16.26.20 | 16.27.19 | 16.26.19 | 16.27.18 | 16.26.18 | 16.27.17 | 16.26.17 | 16.27.16 | 16.26.16 |
| PCIE:DRP63 | 16.27.31 | 16.26.31 | 16.27.30 | 16.26.30 | 16.27.29 | 16.26.29 | 16.27.28 | 16.26.28 | 16.27.27 | 16.26.27 | 16.27.26 | 16.26.26 | 16.27.25 | 16.26.25 | 16.27.24 | 16.26.24 |
| PCIE:DRP64 | 16.27.39 | 16.26.39 | 16.27.38 | 16.26.38 | 16.27.37 | 16.26.37 | 16.27.36 | 16.26.36 | 16.27.35 | 16.26.35 | 16.27.34 | 16.26.34 | 16.27.33 | 16.26.33 | 16.27.32 | 16.26.32 |
| PCIE:DRP65 | 16.27.47 | 16.26.47 | 16.27.46 | 16.26.46 | 16.27.45 | 16.26.45 | 16.27.44 | 16.26.44 | 16.27.43 | 16.26.43 | 16.27.42 | 16.26.42 | 16.27.41 | 16.26.41 | 16.27.40 | 16.26.40 |
| PCIE:DRP66 | 17.27.7 | 17.26.7 | 17.27.6 | 17.26.6 | 17.27.5 | 17.26.5 | 17.27.4 | 17.26.4 | 17.27.3 | 17.26.3 | 17.27.2 | 17.26.2 | 17.27.1 | 17.26.1 | 17.27.0 | 17.26.0 |
| PCIE:DRP67 | 17.27.15 | 17.26.15 | 17.27.14 | 17.26.14 | 17.27.13 | 17.26.13 | 17.27.12 | 17.26.12 | 17.27.11 | 17.26.11 | 17.27.10 | 17.26.10 | 17.27.9 | 17.26.9 | 17.27.8 | 17.26.8 |
| PCIE:DRP68 | 17.27.23 | 17.26.23 | 17.27.22 | 17.26.22 | 17.27.21 | 17.26.21 | 17.27.20 | 17.26.20 | 17.27.19 | 17.26.19 | 17.27.18 | 17.26.18 | 17.27.17 | 17.26.17 | 17.27.16 | 17.26.16 |
| PCIE:DRP69 | 17.27.31 | 17.26.31 | 17.27.30 | 17.26.30 | 17.27.29 | 17.26.29 | 17.27.28 | 17.26.28 | 17.27.27 | 17.26.27 | 17.27.26 | 17.26.26 | 17.27.25 | 17.26.25 | 17.27.24 | 17.26.24 |
| PCIE:DRP6A | 17.27.39 | 17.26.39 | 17.27.38 | 17.26.38 | 17.27.37 | 17.26.37 | 17.27.36 | 17.26.36 | 17.27.35 | 17.26.35 | 17.27.34 | 17.26.34 | 17.27.33 | 17.26.33 | 17.27.32 | 17.26.32 |
| PCIE:DRP6B | 17.27.47 | 17.26.47 | 17.27.46 | 17.26.46 | 17.27.45 | 17.26.45 | 17.27.44 | 17.26.44 | 17.27.43 | 17.26.43 | 17.27.42 | 17.26.42 | 17.27.41 | 17.26.41 | 17.27.40 | 17.26.40 |
| PCIE:DRP6C | 18.27.7 | 18.26.7 | 18.27.6 | 18.26.6 | 18.27.5 | 18.26.5 | 18.27.4 | 18.26.4 | 18.27.3 | 18.26.3 | 18.27.2 | 18.26.2 | 18.27.1 | 18.26.1 | 18.27.0 | 18.26.0 |
| PCIE:DRP6D | 18.27.15 | 18.26.15 | 18.27.14 | 18.26.14 | 18.27.13 | 18.26.13 | 18.27.12 | 18.26.12 | 18.27.11 | 18.26.11 | 18.27.10 | 18.26.10 | 18.27.9 | 18.26.9 | 18.27.8 | 18.26.8 |
| PCIE:DRP6E | 18.27.23 | 18.26.23 | 18.27.22 | 18.26.22 | 18.27.21 | 18.26.21 | 18.27.20 | 18.26.20 | 18.27.19 | 18.26.19 | 18.27.18 | 18.26.18 | 18.27.17 | 18.26.17 | 18.27.16 | 18.26.16 |
| PCIE:DRP6F | 18.27.31 | 18.26.31 | 18.27.30 | 18.26.30 | 18.27.29 | 18.26.29 | 18.27.28 | 18.26.28 | 18.27.27 | 18.26.27 | 18.27.26 | 18.26.26 | 18.27.25 | 18.26.25 | 18.27.24 | 18.26.24 |
| PCIE:DRP70 | 18.27.39 | 18.26.39 | 18.27.38 | 18.26.38 | 18.27.37 | 18.26.37 | 18.27.36 | 18.26.36 | 18.27.35 | 18.26.35 | 18.27.34 | 18.26.34 | 18.27.33 | 18.26.33 | 18.27.32 | 18.26.32 |
| PCIE:DRP71 | 18.27.47 | 18.26.47 | 18.27.46 | 18.26.46 | 18.27.45 | 18.26.45 | 18.27.44 | 18.26.44 | 18.27.43 | 18.26.43 | 18.27.42 | 18.26.42 | 18.27.41 | 18.26.41 | 18.27.40 | 18.26.40 |
| PCIE:DRP72 | 19.27.7 | 19.26.7 | 19.27.6 | 19.26.6 | 19.27.5 | 19.26.5 | 19.27.4 | 19.26.4 | 19.27.3 | 19.26.3 | 19.27.2 | 19.26.2 | 19.27.1 | 19.26.1 | 19.27.0 | 19.26.0 |
| PCIE:DRP73 | 19.27.15 | 19.26.15 | 19.27.14 | 19.26.14 | 19.27.13 | 19.26.13 | 19.27.12 | 19.26.12 | 19.27.11 | 19.26.11 | 19.27.10 | 19.26.10 | 19.27.9 | 19.26.9 | 19.27.8 | 19.26.8 |
| PCIE:DRP74 | 19.27.23 | 19.26.23 | 19.27.22 | 19.26.22 | 19.27.21 | 19.26.21 | 19.27.20 | 19.26.20 | 19.27.19 | 19.26.19 | 19.27.18 | 19.26.18 | 19.27.17 | 19.26.17 | 19.27.16 | 19.26.16 |
| PCIE:DRP75 | 19.27.31 | 19.26.31 | 19.27.30 | 19.26.30 | 19.27.29 | 19.26.29 | 19.27.28 | 19.26.28 | 19.27.27 | 19.26.27 | 19.27.26 | 19.26.26 | 19.27.25 | 19.26.25 | 19.27.24 | 19.26.24 |
| PCIE:DRP76 | 19.27.39 | 19.26.39 | 19.27.38 | 19.26.38 | 19.27.37 | 19.26.37 | 19.27.36 | 19.26.36 | 19.27.35 | 19.26.35 | 19.27.34 | 19.26.34 | 19.27.33 | 19.26.33 | 19.27.32 | 19.26.32 |
| PCIE:DRP77 | 19.27.47 | 19.26.47 | 19.27.46 | 19.26.46 | 19.27.45 | 19.26.45 | 19.27.44 | 19.26.44 | 19.27.43 | 19.26.43 | 19.27.42 | 19.26.42 | 19.27.41 | 19.26.41 | 19.27.40 | 19.26.40 |
| PCIE:DSN_CAP_ID | 4.27.39 | 4.26.39 | 4.27.38 | 4.26.38 | 4.27.37 | 4.26.37 | 4.27.36 | 4.26.36 | 4.27.35 | 4.26.35 | 4.27.34 | 4.26.34 | 4.27.33 | 4.26.33 | 4.27.32 | 4.26.32 |
| PCIE:SUBSYSTEM_ID | 10.27.15 | 10.26.15 | 10.27.14 | 10.26.14 | 10.27.13 | 10.26.13 | 10.27.12 | 10.26.12 | 10.27.11 | 10.26.11 | 10.27.10 | 10.26.10 | 10.27.9 | 10.26.9 | 10.27.8 | 10.26.8 |
| PCIE:SUBSYSTEM_VENDOR_ID | 10.27.23 | 10.26.23 | 10.27.22 | 10.26.22 | 10.27.21 | 10.26.21 | 10.27.20 | 10.26.20 | 10.27.19 | 10.26.19 | 10.27.18 | 10.26.18 | 10.27.17 | 10.26.17 | 10.27.16 | 10.26.16 |
| PCIE:VC_CAP_ID | 10.27.47 | 10.26.47 | 10.27.46 | 10.26.46 | 10.27.45 | 10.26.45 | 10.27.44 | 10.26.44 | 10.27.43 | 10.26.43 | 10.27.42 | 10.26.42 | 10.27.41 | 10.26.41 | 10.27.40 | 10.26.40 |
| PCIE:VENDOR_ID | 11.27.15 | 11.26.15 | 11.27.14 | 11.26.14 | 11.27.13 | 11.26.13 | 11.27.12 | 11.26.12 | 11.27.11 | 11.26.11 | 11.27.10 | 11.26.10 | 11.27.9 | 11.26.9 | 11.27.8 | 11.26.8 |
| PCIE:VSEC_CAP_HDR_ID | 11.27.31 | 11.26.31 | 11.27.30 | 11.26.30 | 11.27.29 | 11.26.29 | 11.27.28 | 11.26.28 | 11.27.27 | 11.26.27 | 11.27.26 | 11.26.26 | 11.27.25 | 11.26.25 | 11.27.24 | 11.26.24 |
| PCIE:VSEC_CAP_ID | 11.27.47 | 11.26.47 | 11.27.46 | 11.26.46 | 11.27.45 | 11.26.45 | 11.27.44 | 11.26.44 | 11.27.43 | 11.26.43 | 11.27.42 | 11.26.42 | 11.27.41 | 11.26.41 | 11.27.40 | 11.26.40 |
| non-inverted | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:AER_CAP_INT_MSG_NUM_MSI | 0.26.18 | 0.27.17 | 0.26.17 | 0.27.16 | 0.26.16 |
|---|---|---|---|---|---|
| PCIE:AER_CAP_INT_MSG_NUM_MSIX | 0.27.20 | 0.26.20 | 0.27.19 | 0.26.19 | 0.27.18 |
| PCIE:INFER_EI | 12.27.44 | 12.26.44 | 12.27.43 | 12.26.43 | 12.27.42 |
| PCIE:PCIE_CAP_INT_MSG_NUM | 8.26.6 | 8.27.5 | 8.26.5 | 8.27.4 | 8.26.4 |
| PCIE:PM_CAP_PMESUPPORT | 8.26.35 | 8.27.34 | 8.26.34 | 8.27.33 | 8.26.33 |
| PCIE:VC0_TX_LASTPACKET | 14.27.37 | 14.26.37 | 14.27.36 | 14.26.36 | 14.27.35 |
| non-inverted | [4] | [3] | [2] | [1] | [0] |
| PCIE:AER_CAP_VERSION | 0.26.23 | 0.27.22 | 0.26.22 | 0.27.21 |
|---|---|---|---|---|
| PCIE:CPL_TIMEOUT_RANGES_SUPPORTED | 3.27.46 | 3.26.46 | 3.27.45 | 3.26.45 |
| PCIE:DSN_CAP_VERSION | 5.27.1 | 5.26.1 | 5.27.0 | 5.26.0 |
| PCIE:LINK_CAP_MAX_LINK_SPEED | 5.27.46 | 5.26.46 | 5.27.45 | 5.26.45 |
| PCIE:LINK_CTRL2_TARGET_LINK_SPEED | 6.27.3 | 6.26.3 | 6.27.2 | 6.26.2 |
| PCIE:PCIE_CAP_CAPABILITY_VERSION | 8.27.1 | 8.26.1 | 8.27.0 | 8.26.0 |
| PCIE:PCIE_CAP_DEVICE_PORT_TYPE | 8.27.3 | 8.26.3 | 8.27.2 | 8.26.2 |
| PCIE:PCIE_REVISION | 8.27.15 | 8.26.15 | 8.27.14 | 8.26.14 |
| PCIE:VC_CAP_VERSION | 13.26.45 | 13.27.44 | 13.26.44 | 13.27.43 |
| PCIE:VSEC_CAP_HDR_REVISION | 11.27.39 | 11.26.39 | 11.27.38 | 11.26.38 |
| PCIE:VSEC_CAP_VERSION | 12.27.9 | 12.26.9 | 12.27.8 | 12.26.8 |
| non-inverted | [3] | [2] | [1] | [0] |
| PCIE:BAR0 | 1.27.7 | 1.26.7 | 1.27.6 | 1.26.6 | 1.27.5 | 1.26.5 | 1.27.4 | 1.26.4 | 1.27.3 | 1.26.3 | 1.27.2 | 1.26.2 | 1.27.1 | 1.26.1 | 1.27.0 | 1.26.0 | 0.27.47 | 0.26.47 | 0.27.46 | 0.26.46 | 0.27.45 | 0.26.45 | 0.27.44 | 0.26.44 | 0.27.43 | 0.26.43 | 0.27.42 | 0.26.42 | 0.27.41 | 0.26.41 | 0.27.40 | 0.26.40 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:BAR1 | 1.27.23 | 1.26.23 | 1.27.22 | 1.26.22 | 1.27.21 | 1.26.21 | 1.27.20 | 1.26.20 | 1.27.19 | 1.26.19 | 1.27.18 | 1.26.18 | 1.27.17 | 1.26.17 | 1.27.16 | 1.26.16 | 1.27.15 | 1.26.15 | 1.27.14 | 1.26.14 | 1.27.13 | 1.26.13 | 1.27.12 | 1.26.12 | 1.27.11 | 1.26.11 | 1.27.10 | 1.26.10 | 1.27.9 | 1.26.9 | 1.27.8 | 1.26.8 |
| PCIE:BAR2 | 1.27.39 | 1.26.39 | 1.27.38 | 1.26.38 | 1.27.37 | 1.26.37 | 1.27.36 | 1.26.36 | 1.27.35 | 1.26.35 | 1.27.34 | 1.26.34 | 1.27.33 | 1.26.33 | 1.27.32 | 1.26.32 | 1.27.31 | 1.26.31 | 1.27.30 | 1.26.30 | 1.27.29 | 1.26.29 | 1.27.28 | 1.26.28 | 1.27.27 | 1.26.27 | 1.27.26 | 1.26.26 | 1.27.25 | 1.26.25 | 1.27.24 | 1.26.24 |
| PCIE:BAR3 | 2.27.7 | 2.26.7 | 2.27.6 | 2.26.6 | 2.27.5 | 2.26.5 | 2.27.4 | 2.26.4 | 2.27.3 | 2.26.3 | 2.27.2 | 2.26.2 | 2.27.1 | 2.26.1 | 2.27.0 | 2.26.0 | 1.27.47 | 1.26.47 | 1.27.46 | 1.26.46 | 1.27.45 | 1.26.45 | 1.27.44 | 1.26.44 | 1.27.43 | 1.26.43 | 1.27.42 | 1.26.42 | 1.27.41 | 1.26.41 | 1.27.40 | 1.26.40 |
| PCIE:BAR4 | 2.27.23 | 2.26.23 | 2.27.22 | 2.26.22 | 2.27.21 | 2.26.21 | 2.27.20 | 2.26.20 | 2.27.19 | 2.26.19 | 2.27.18 | 2.26.18 | 2.27.17 | 2.26.17 | 2.27.16 | 2.26.16 | 2.27.15 | 2.26.15 | 2.27.14 | 2.26.14 | 2.27.13 | 2.26.13 | 2.27.12 | 2.26.12 | 2.27.11 | 2.26.11 | 2.27.10 | 2.26.10 | 2.27.9 | 2.26.9 | 2.27.8 | 2.26.8 |
| PCIE:BAR5 | 2.27.39 | 2.26.39 | 2.27.38 | 2.26.38 | 2.27.37 | 2.26.37 | 2.27.36 | 2.26.36 | 2.27.35 | 2.26.35 | 2.27.34 | 2.26.34 | 2.27.33 | 2.26.33 | 2.27.32 | 2.26.32 | 2.27.31 | 2.26.31 | 2.27.30 | 2.26.30 | 2.27.29 | 2.26.29 | 2.27.28 | 2.26.28 | 2.27.27 | 2.26.27 | 2.27.26 | 2.26.26 | 2.27.25 | 2.26.25 | 2.27.24 | 2.26.24 |
| PCIE:CARDBUS_CIS_POINTER | 3.27.31 | 3.26.31 | 3.27.30 | 3.26.30 | 3.27.29 | 3.26.29 | 3.27.28 | 3.26.28 | 3.27.27 | 3.26.27 | 3.27.26 | 3.26.26 | 3.27.25 | 3.26.25 | 3.27.24 | 3.26.24 | 3.27.23 | 3.26.23 | 3.27.22 | 3.26.22 | 3.27.21 | 3.26.21 | 3.27.20 | 3.26.20 | 3.27.19 | 3.26.19 | 3.27.18 | 3.26.18 | 3.27.17 | 3.26.17 | 3.27.16 | 3.26.16 |
| PCIE:EXPANSION_ROM | 3.27.7 | 3.26.7 | 3.27.6 | 3.26.6 | 3.27.5 | 3.26.5 | 3.27.4 | 3.26.4 | 3.27.3 | 3.26.3 | 3.27.2 | 3.26.2 | 3.27.1 | 3.26.1 | 3.27.0 | 3.26.0 | 2.27.47 | 2.26.47 | 2.27.46 | 2.26.46 | 2.27.45 | 2.26.45 | 2.27.44 | 2.26.44 | 2.27.43 | 2.26.43 | 2.27.42 | 2.26.42 | 2.27.41 | 2.26.41 | 2.27.40 | 2.26.40 |
| PCIE:SPARE_WORD0 | 15.27.47 | 15.26.47 | 15.27.46 | 15.26.46 | 15.27.45 | 15.26.45 | 15.27.44 | 15.26.44 | 15.27.43 | 15.26.43 | 15.27.42 | 15.26.42 | 15.27.41 | 15.26.41 | 15.27.40 | 15.26.40 | 15.27.39 | 15.26.39 | 15.27.38 | 15.26.38 | 15.27.37 | 15.26.37 | 15.27.36 | 15.26.36 | 15.27.35 | 15.26.35 | 15.27.34 | 15.26.34 | 15.27.33 | 15.26.33 | 15.27.32 | 15.26.32 |
| PCIE:SPARE_WORD1 | 16.27.15 | 16.26.15 | 16.27.14 | 16.26.14 | 16.27.13 | 16.26.13 | 16.27.12 | 16.26.12 | 16.27.11 | 16.26.11 | 16.27.10 | 16.26.10 | 16.27.9 | 16.26.9 | 16.27.8 | 16.26.8 | 16.27.7 | 16.26.7 | 16.27.6 | 16.26.6 | 16.27.5 | 16.26.5 | 16.27.4 | 16.26.4 | 16.27.3 | 16.26.3 | 16.27.2 | 16.26.2 | 16.27.1 | 16.26.1 | 16.27.0 | 16.26.0 |
| PCIE:SPARE_WORD2 | 16.27.31 | 16.26.31 | 16.27.30 | 16.26.30 | 16.27.29 | 16.26.29 | 16.27.28 | 16.26.28 | 16.27.27 | 16.26.27 | 16.27.26 | 16.26.26 | 16.27.25 | 16.26.25 | 16.27.24 | 16.26.24 | 16.27.23 | 16.26.23 | 16.27.22 | 16.26.22 | 16.27.21 | 16.26.21 | 16.27.20 | 16.26.20 | 16.27.19 | 16.26.19 | 16.27.18 | 16.26.18 | 16.27.17 | 16.26.17 | 16.27.16 | 16.26.16 |
| PCIE:SPARE_WORD3 | 16.27.47 | 16.26.47 | 16.27.46 | 16.26.46 | 16.27.45 | 16.26.45 | 16.27.44 | 16.26.44 | 16.27.43 | 16.26.43 | 16.27.42 | 16.26.42 | 16.27.41 | 16.26.41 | 16.27.40 | 16.26.40 | 16.27.39 | 16.26.39 | 16.27.38 | 16.26.38 | 16.27.37 | 16.26.37 | 16.27.36 | 16.26.36 | 16.27.35 | 16.26.35 | 16.27.34 | 16.26.34 | 16.27.33 | 16.26.33 | 16.27.32 | 16.26.32 |
| non-inverted | [31] | [30] | [29] | [28] | [27] | [26] | [25] | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:CAPABILITIES_PTR | 3.27.11 | 3.26.11 | 3.27.10 | 3.26.10 | 3.27.9 | 3.26.9 | 3.27.8 | 3.26.8 |
|---|---|---|---|---|---|---|---|---|
| PCIE:DNSTREAM_LINK_NUM | 13.27.27 | 13.26.27 | 13.27.26 | 13.26.26 | 13.27.25 | 13.26.25 | 13.27.24 | 13.26.24 |
| PCIE:HEADER_TYPE | 5.27.19 | 5.26.19 | 5.27.18 | 5.26.18 | 5.27.17 | 5.26.17 | 5.27.16 | 5.26.16 |
| PCIE:INTERRUPT_PIN | 5.27.23 | 5.26.23 | 5.27.22 | 5.26.22 | 5.27.21 | 5.26.21 | 5.27.20 | 5.26.20 |
| PCIE:MSIX_BASE_PTR | 6.27.35 | 6.26.35 | 6.27.34 | 6.26.34 | 6.27.33 | 6.26.33 | 6.27.32 | 6.26.32 |
| PCIE:MSIX_CAP_ID | 6.27.39 | 6.26.39 | 6.27.38 | 6.26.38 | 6.27.37 | 6.26.37 | 6.27.36 | 6.26.36 |
| PCIE:MSIX_CAP_NEXTPTR | 6.27.43 | 6.26.43 | 6.27.42 | 6.26.42 | 6.27.41 | 6.26.41 | 6.27.40 | 6.26.40 |
| PCIE:MSI_BASE_PTR | 6.27.11 | 6.26.11 | 6.27.10 | 6.26.10 | 6.27.9 | 6.26.9 | 6.27.8 | 6.26.8 |
| PCIE:MSI_CAP_ID | 6.27.19 | 6.26.19 | 6.27.18 | 6.26.18 | 6.27.17 | 6.26.17 | 6.27.16 | 6.26.16 |
| PCIE:MSI_CAP_NEXTPTR | 6.27.27 | 6.26.27 | 6.27.26 | 6.26.26 | 6.27.25 | 6.26.25 | 6.27.24 | 6.26.24 |
| PCIE:N_FTS_COMCLK_GEN1 | 13.27.6 | 13.26.6 | 13.27.5 | 13.26.5 | 13.27.4 | 13.26.4 | 13.27.3 | 13.26.3 |
| PCIE:N_FTS_COMCLK_GEN2 | 13.27.11 | 13.26.11 | 13.27.10 | 13.26.10 | 13.27.9 | 13.26.9 | 13.27.8 | 13.26.8 |
| PCIE:N_FTS_GEN1 | 13.27.15 | 13.26.15 | 13.27.14 | 13.26.14 | 13.27.13 | 13.26.13 | 13.27.12 | 13.26.12 |
| PCIE:N_FTS_GEN2 | 13.27.19 | 13.26.19 | 13.27.18 | 13.26.18 | 13.27.17 | 13.26.17 | 13.27.16 | 13.26.16 |
| PCIE:PCIE_BASE_PTR | 7.27.43 | 7.26.43 | 7.27.42 | 7.26.42 | 7.27.41 | 7.26.41 | 7.27.40 | 7.26.40 |
| PCIE:PCIE_CAP_CAPABILITY_ID | 7.27.47 | 7.26.47 | 7.27.46 | 7.26.46 | 7.27.45 | 7.26.45 | 7.27.44 | 7.26.44 |
| PCIE:PCIE_CAP_NEXTPTR | 8.27.11 | 8.26.11 | 8.27.10 | 8.26.10 | 8.27.9 | 8.26.9 | 8.27.8 | 8.26.8 |
| PCIE:PM_BASE_PTR | 8.27.19 | 8.26.19 | 8.27.18 | 8.26.18 | 8.27.17 | 8.26.17 | 8.27.16 | 8.26.16 |
| PCIE:PM_CAP_ID | 8.27.27 | 8.26.27 | 8.27.26 | 8.26.26 | 8.27.25 | 8.26.25 | 8.27.24 | 8.26.24 |
| PCIE:PM_CAP_NEXTPTR | 8.27.31 | 8.26.31 | 8.27.30 | 8.26.30 | 8.27.29 | 8.26.29 | 8.27.28 | 8.26.28 |
| PCIE:PM_DATA0 | 9.27.3 | 9.26.3 | 9.27.2 | 9.26.2 | 9.27.1 | 9.26.1 | 9.27.0 | 9.26.0 |
| PCIE:PM_DATA1 | 9.27.7 | 9.26.7 | 9.27.6 | 9.26.6 | 9.27.5 | 9.26.5 | 9.27.4 | 9.26.4 |
| PCIE:PM_DATA2 | 9.27.11 | 9.26.11 | 9.27.10 | 9.26.10 | 9.27.9 | 9.26.9 | 9.27.8 | 9.26.8 |
| PCIE:PM_DATA3 | 9.27.15 | 9.26.15 | 9.27.14 | 9.26.14 | 9.27.13 | 9.26.13 | 9.27.12 | 9.26.12 |
| PCIE:PM_DATA4 | 9.27.19 | 9.26.19 | 9.27.18 | 9.26.18 | 9.27.17 | 9.26.17 | 9.27.16 | 9.26.16 |
| PCIE:PM_DATA5 | 9.27.23 | 9.26.23 | 9.27.22 | 9.26.22 | 9.27.21 | 9.26.21 | 9.27.20 | 9.26.20 |
| PCIE:PM_DATA6 | 9.27.27 | 9.26.27 | 9.27.26 | 9.26.26 | 9.27.25 | 9.26.25 | 9.27.24 | 9.26.24 |
| PCIE:PM_DATA7 | 9.27.31 | 9.26.31 | 9.27.30 | 9.26.30 | 9.27.29 | 9.26.29 | 9.27.28 | 9.26.28 |
| PCIE:REVISION_ID | 9.27.35 | 9.26.35 | 9.27.34 | 9.26.34 | 9.27.33 | 9.26.33 | 9.27.32 | 9.26.32 |
| PCIE:SLOT_CAP_SLOT_POWER_LIMIT_VALUE | 10.27.4 | 10.26.4 | 10.27.3 | 10.26.3 | 10.27.2 | 10.26.2 | 10.27.1 | 10.26.1 |
| PCIE:SPARE_BYTE0 | 15.26.13 | 15.27.12 | 15.26.12 | 15.27.11 | 15.26.11 | 15.27.10 | 15.26.10 | 15.27.9 |
| PCIE:SPARE_BYTE1 | 15.27.19 | 15.26.19 | 15.27.18 | 15.26.18 | 15.27.17 | 15.26.17 | 15.27.16 | 15.26.16 |
| PCIE:SPARE_BYTE2 | 15.27.23 | 15.26.23 | 15.27.22 | 15.26.22 | 15.27.21 | 15.26.21 | 15.27.20 | 15.26.20 |
| PCIE:SPARE_BYTE3 | 15.27.27 | 15.26.27 | 15.27.26 | 15.26.26 | 15.27.25 | 15.26.25 | 15.27.24 | 15.26.24 |
| non-inverted | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:CLASS_CODE | 3.27.43 | 3.26.43 | 3.27.42 | 3.26.42 | 3.27.41 | 3.26.41 | 3.27.40 | 3.26.40 | 3.27.39 | 3.26.39 | 3.27.38 | 3.26.38 | 3.27.37 | 3.26.37 | 3.27.36 | 3.26.36 | 3.27.35 | 3.26.35 | 3.27.34 | 3.26.34 | 3.27.33 | 3.26.33 | 3.27.32 | 3.26.32 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| non-inverted | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:CRM_MODULE_RSTS | 12.27.14 | 12.26.14 | 12.27.13 | 12.26.13 | 12.27.12 | 12.26.12 | 12.27.11 |
|---|---|---|---|---|---|---|---|
| PCIE:VC0_TOTAL_CREDITS_CH | 14.26.19 | 14.27.18 | 14.26.18 | 14.27.17 | 14.26.17 | 14.27.16 | 14.26.16 |
| PCIE:VC0_TOTAL_CREDITS_NPH | 14.27.22 | 14.26.22 | 14.27.21 | 14.26.21 | 14.27.20 | 14.26.20 | 14.27.19 |
| PCIE:VC0_TOTAL_CREDITS_PH | 14.26.35 | 14.27.34 | 14.26.34 | 14.27.33 | 14.26.33 | 14.27.32 | 14.26.32 |
| non-inverted | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:DEV_CAP_ENDPOINT_L0S_LATENCY | 4.26.1 | 4.27.0 | 4.26.0 |
|---|---|---|---|
| PCIE:DEV_CAP_ENDPOINT_L1_LATENCY | 4.27.2 | 4.26.2 | 4.27.1 |
| PCIE:DEV_CAP_MAX_PAYLOAD_SUPPORTED | 4.26.5 | 4.27.4 | 4.26.4 |
| PCIE:DEV_CAP_RSVD_14_12 | 4.26.9 | 4.27.8 | 4.26.8 |
| PCIE:DEV_CAP_RSVD_31_29 | 4.27.11 | 4.26.11 | 4.27.10 |
| PCIE:LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 | 5.26.33 | 5.27.32 | 5.26.32 |
| PCIE:LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 | 5.27.34 | 5.26.34 | 5.27.33 |
| PCIE:LINK_CAP_L0S_EXIT_LATENCY_GEN1 | 5.26.36 | 5.27.35 | 5.26.35 |
| PCIE:LINK_CAP_L0S_EXIT_LATENCY_GEN2 | 5.27.37 | 5.26.37 | 5.27.36 |
| PCIE:LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 | 5.26.39 | 5.27.38 | 5.26.38 |
| PCIE:LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 | 5.26.41 | 5.27.40 | 5.26.40 |
| PCIE:LINK_CAP_L1_EXIT_LATENCY_GEN1 | 5.27.42 | 5.26.42 | 5.27.41 |
| PCIE:LINK_CAP_L1_EXIT_LATENCY_GEN2 | 5.26.44 | 5.27.43 | 5.26.43 |
| PCIE:MSIX_CAP_PBA_BIR | 6.27.45 | 6.26.45 | 6.27.44 |
| PCIE:MSIX_CAP_TABLE_BIR | 7.27.15 | 7.26.15 | 7.27.14 |
| PCIE:MSI_CAP_MULTIMSGCAP | 6.27.21 | 6.26.21 | 6.27.20 |
| PCIE:PGL0_LANE | 14.26.41 | 14.27.40 | 14.26.40 |
| PCIE:PGL1_LANE | 14.27.42 | 14.26.42 | 14.27.41 |
| PCIE:PGL2_LANE | 14.26.44 | 14.27.43 | 14.26.43 |
| PCIE:PGL3_LANE | 14.27.45 | 14.26.45 | 14.27.44 |
| PCIE:PGL4_LANE | 14.26.47 | 14.27.46 | 14.26.46 |
| PCIE:PGL5_LANE | 15.26.1 | 15.27.0 | 15.26.0 |
| PCIE:PGL6_LANE | 15.27.2 | 15.26.2 | 15.27.1 |
| PCIE:PGL7_LANE | 15.26.4 | 15.27.3 | 15.26.3 |
| PCIE:PL_AUTO_CONFIG | 13.27.21 | 13.26.21 | 13.27.20 |
| PCIE:PM_CAP_AUXCURRENT | 8.26.21 | 8.27.20 | 8.26.20 |
| PCIE:PM_CAP_VERSION | 8.26.37 | 8.27.36 | 8.26.36 |
| PCIE:USER_CLK_FREQ | 12.26.11 | 12.27.10 | 12.26.10 |
| non-inverted | [2] | [1] | [0] |
| PCIE:DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT | 4.26.6 | 4.27.5 |
|---|---|---|
| PCIE:DEV_CAP_RSVD_17_16 | 4.26.10 | 4.27.9 |
| PCIE:LINK_CAP_ASPM_SUPPORT | 5.26.30 | 5.27.29 |
| PCIE:LINK_CAP_RSVD_23_22 | 5.27.47 | 5.26.47 |
| PCIE:LL_ACK_TIMEOUT_FUNC | 12.27.24 | 12.26.24 |
| PCIE:LL_REPLAY_TIMEOUT_FUNC | 12.27.40 | 12.26.40 |
| PCIE:PCIE_CAP_RSVD_15_14 | 8.26.13 | 8.27.12 |
| PCIE:PM_DATA_SCALE0 | 8.27.39 | 8.26.39 |
| PCIE:PM_DATA_SCALE1 | 8.27.40 | 8.26.40 |
| PCIE:PM_DATA_SCALE2 | 8.27.41 | 8.26.41 |
| PCIE:PM_DATA_SCALE3 | 8.27.42 | 8.26.42 |
| PCIE:PM_DATA_SCALE4 | 8.27.43 | 8.26.43 |
| PCIE:PM_DATA_SCALE5 | 8.27.44 | 8.26.44 |
| PCIE:PM_DATA_SCALE6 | 8.27.45 | 8.26.45 |
| PCIE:PM_DATA_SCALE7 | 8.27.46 | 8.26.46 |
| PCIE:RECRC_CHK | 14.27.38 | 14.26.38 |
| PCIE:SLOT_CAP_SLOT_POWER_LIMIT_SCALE | 10.27.0 | 10.26.0 |
| PCIE:TL_RX_RAM_RDATA_LATENCY | 13.26.39 | 13.27.38 |
| PCIE:TL_TX_RAM_RDATA_LATENCY | 13.27.42 | 13.26.42 |
| non-inverted | [1] | [0] |
| PCIE:ENABLE_MSG_ROUTE | 13.26.37 | 13.27.36 | 13.26.36 | 13.27.35 | 13.26.35 | 13.27.34 | 13.26.34 | 13.27.33 | 13.26.33 | 13.27.32 | 13.26.32 |
|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:MSIX_CAP_TABLE_SIZE | 7.26.37 | 7.27.36 | 7.26.36 | 7.27.35 | 7.26.35 | 7.27.34 | 7.26.34 | 7.27.33 | 7.26.33 | 7.27.32 | 7.26.32 |
| PCIE:VC0_TOTAL_CREDITS_CD | 14.26.13 | 14.27.12 | 14.26.12 | 14.27.11 | 14.26.11 | 14.27.10 | 14.26.10 | 14.27.9 | 14.26.9 | 14.27.8 | 14.26.8 |
| PCIE:VC0_TOTAL_CREDITS_PD | 14.26.29 | 14.27.28 | 14.26.28 | 14.27.27 | 14.26.27 | 14.27.26 | 14.26.26 | 14.27.25 | 14.26.25 | 14.27.24 | 14.26.24 |
| non-inverted | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:EXT_CFG_CAP_PTR | 5.27.4 | 5.26.4 | 5.27.3 | 5.26.3 | 5.27.2 | 5.26.2 |
|---|---|---|---|---|---|---|
| PCIE:LINK_CAP_MAX_LINK_WIDTH | 12.27.47 | 12.26.47 | 12.27.46 | 12.26.46 | 12.27.45 | 12.26.45 |
| PCIE:LTSSM_MAX_LINK_WIDTH | 13.27.2 | 13.26.2 | 13.27.1 | 13.26.1 | 13.27.0 | 13.26.0 |
| non-inverted | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:EXT_CFG_XP_CAP_PTR | 5.27.12 | 5.26.12 | 5.27.11 | 5.26.11 | 5.27.10 | 5.26.10 | 5.27.9 | 5.26.9 | 5.27.8 | 5.26.8 |
|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:LAST_CONFIG_DWORD | 5.26.29 | 5.27.28 | 5.26.28 | 5.27.27 | 5.26.27 | 5.27.26 | 5.26.26 | 5.27.25 | 5.26.25 | 5.27.24 |
| non-inverted | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:LL_ACK_TIMEOUT | 12.26.23 | 12.27.22 | 12.26.22 | 12.27.21 | 12.26.21 | 12.27.20 | 12.26.20 | 12.27.19 | 12.26.19 | 12.27.18 | 12.26.18 | 12.27.17 | 12.26.17 | 12.27.16 | 12.26.16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:LL_REPLAY_TIMEOUT | 12.26.39 | 12.27.38 | 12.26.38 | 12.27.37 | 12.26.37 | 12.27.36 | 12.26.36 | 12.27.35 | 12.26.35 | 12.27.34 | 12.26.34 | 12.27.33 | 12.26.33 | 12.27.32 | 12.26.32 |
| non-inverted | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:MSIX_CAP_PBA_OFFSET | 7.26.14 | 7.27.13 | 7.26.13 | 7.27.12 | 7.26.12 | 7.27.11 | 7.26.11 | 7.27.10 | 7.26.10 | 7.27.9 | 7.26.9 | 7.27.8 | 7.26.8 | 7.27.7 | 7.26.7 | 7.27.6 | 7.26.6 | 7.27.5 | 7.26.5 | 7.27.4 | 7.26.4 | 7.27.3 | 7.26.3 | 7.27.2 | 7.26.2 | 7.27.1 | 7.26.1 | 7.27.0 | 7.26.0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:MSIX_CAP_TABLE_OFFSET | 7.26.30 | 7.27.29 | 7.26.29 | 7.27.28 | 7.26.28 | 7.27.27 | 7.26.27 | 7.27.26 | 7.26.26 | 7.27.25 | 7.26.25 | 7.27.24 | 7.26.24 | 7.27.23 | 7.26.23 | 7.27.22 | 7.26.22 | 7.27.21 | 7.26.21 | 7.27.20 | 7.26.20 | 7.27.19 | 7.26.19 | 7.27.18 | 7.26.18 | 7.27.17 | 7.26.17 | 7.27.16 | 7.26.16 |
| non-inverted | [28] | [27] | [26] | [25] | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:SLOT_CAP_PHYSICAL_SLOT_NUM | 9.27.46 | 9.26.46 | 9.27.45 | 9.26.45 | 9.27.44 | 9.26.44 | 9.27.43 | 9.26.43 | 9.27.42 | 9.26.42 | 9.27.41 | 9.26.41 | 9.27.40 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:VC0_RX_RAM_LIMIT | 14.26.6 | 14.27.5 | 14.26.5 | 14.27.4 | 14.26.4 | 14.27.3 | 14.26.3 | 14.27.2 | 14.26.2 | 14.27.1 | 14.26.1 | 14.27.0 | 14.26.0 |
| non-inverted | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |