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PCI Express cores

Tile PCIE

Cells: 40

Bel PCIE

virtex6 PCIE bel PCIE
PinDirectionWires
CFGAERECRCCHECKENoutputTCELL10:OUT18.TMIN
CFGAERECRCGENENoutputTCELL10:OUT19.TMIN
CFGBYTEENN0inputTCELL16:IMUX.IMUX15.DELAY
CFGBYTEENN1inputTCELL16:IMUX.IMUX16.DELAY
CFGBYTEENN2inputTCELL15:IMUX.IMUX15.DELAY
CFGBYTEENN3inputTCELL15:IMUX.IMUX16.DELAY
CFGCOMMANDBUSMASTERENABLEoutputTCELL0:OUT15.TMIN
CFGCOMMANDINTERRUPTDISABLEoutputTCELL21:OUT16.TMIN
CFGCOMMANDIOENABLEoutputTCELL0:OUT13.TMIN
CFGCOMMANDMEMENABLEoutputTCELL0:OUT14.TMIN
CFGCOMMANDSERRENoutputTCELL0:OUT17.TMIN
CFGDEVCONTROL2CPLTIMEOUTDISoutputTCELL10:OUT16.TMIN
CFGDEVCONTROL2CPLTIMEOUTVAL0outputTCELL11:OUT16.TMIN
CFGDEVCONTROL2CPLTIMEOUTVAL1outputTCELL11:OUT17.TMIN
CFGDEVCONTROL2CPLTIMEOUTVAL2outputTCELL11:OUT19.TMIN
CFGDEVCONTROL2CPLTIMEOUTVAL3outputTCELL11:OUT20.TMIN
CFGDEVCONTROLAUXPOWERENoutputTCELL31:OUT17.TMIN
CFGDEVCONTROLCORRERRREPORTINGENoutputTCELL23:OUT16.TMIN
CFGDEVCONTROLENABLEROoutputTCELL29:OUT17.TMIN
CFGDEVCONTROLEXTTAGENoutputTCELL30:OUT18.TMIN
CFGDEVCONTROLFATALERRREPORTINGENoutputTCELL23:OUT18.TMIN
CFGDEVCONTROLMAXPAYLOAD0outputTCELL29:OUT18.TMIN
CFGDEVCONTROLMAXPAYLOAD1outputTCELL30:OUT16.TMIN
CFGDEVCONTROLMAXPAYLOAD2outputTCELL30:OUT17.TMIN
CFGDEVCONTROLMAXREADREQ0outputTCELL32:OUT17.TMIN
CFGDEVCONTROLMAXREADREQ1outputTCELL32:OUT18.TMIN
CFGDEVCONTROLMAXREADREQ2outputTCELL33:OUT16.TMIN
CFGDEVCONTROLNONFATALREPORTINGENoutputTCELL23:OUT17.TMIN
CFGDEVCONTROLNOSNOOPENoutputTCELL32:OUT16.TMIN
CFGDEVCONTROLPHANTOMENoutputTCELL31:OUT16.TMIN
CFGDEVCONTROLURERRREPORTINGENoutputTCELL29:OUT16.TMIN
CFGDEVSTATUSCORRERRDETECTEDoutputTCELL21:OUT17.TMIN
CFGDEVSTATUSFATALERRDETECTEDoutputTCELL22:OUT17.TMIN
CFGDEVSTATUSNONFATALERRDETECTEDoutputTCELL22:OUT16.TMIN
CFGDEVSTATUSURDETECTEDoutputTCELL22:OUT18.TMIN
CFGDI0inputTCELL14:IMUX.IMUX14.DELAY
CFGDI1inputTCELL14:IMUX.IMUX16.DELAY
CFGDI10inputTCELL17:IMUX.IMUX9.DELAY
CFGDI11inputTCELL17:IMUX.IMUX10.DELAY
CFGDI12inputTCELL17:IMUX.IMUX11.DELAY
CFGDI13inputTCELL17:IMUX.IMUX12.DELAY
CFGDI14inputTCELL18:IMUX.IMUX9.DELAY
CFGDI15inputTCELL18:IMUX.IMUX10.DELAY
CFGDI16inputTCELL18:IMUX.IMUX11.DELAY
CFGDI17inputTCELL18:IMUX.IMUX12.DELAY
CFGDI18inputTCELL19:IMUX.IMUX9.DELAY
CFGDI19inputTCELL19:IMUX.IMUX10.DELAY
CFGDI2inputTCELL15:IMUX.IMUX10.DELAY
CFGDI20inputTCELL19:IMUX.IMUX11.DELAY
CFGDI21inputTCELL19:IMUX.IMUX12.DELAY
CFGDI22inputTCELL18:IMUX.IMUX13.DELAY
CFGDI23inputTCELL18:IMUX.IMUX14.DELAY
CFGDI24inputTCELL18:IMUX.IMUX15.DELAY
CFGDI25inputTCELL18:IMUX.IMUX16.DELAY
CFGDI26inputTCELL17:IMUX.IMUX13.DELAY
CFGDI27inputTCELL17:IMUX.IMUX14.DELAY
CFGDI28inputTCELL17:IMUX.IMUX15.DELAY
CFGDI29inputTCELL17:IMUX.IMUX16.DELAY
CFGDI3inputTCELL15:IMUX.IMUX12.DELAY
CFGDI30inputTCELL16:IMUX.IMUX13.DELAY
CFGDI31inputTCELL16:IMUX.IMUX14.DELAY
CFGDI4inputTCELL15:IMUX.IMUX13.DELAY
CFGDI5inputTCELL15:IMUX.IMUX14.DELAY
CFGDI6inputTCELL16:IMUX.IMUX9.DELAY
CFGDI7inputTCELL16:IMUX.IMUX10.DELAY
CFGDI8inputTCELL16:IMUX.IMUX11.DELAY
CFGDI9inputTCELL16:IMUX.IMUX12.DELAY
CFGDO0outputTCELL22:OUT15.TMIN
CFGDO1outputTCELL23:OUT12.TMIN
CFGDO10outputTCELL29:OUT12.TMIN
CFGDO11outputTCELL29:OUT13.TMIN
CFGDO12outputTCELL29:OUT14.TMIN
CFGDO13outputTCELL29:OUT15.TMIN
CFGDO14outputTCELL30:OUT12.TMIN
CFGDO15outputTCELL30:OUT13.TMIN
CFGDO16outputTCELL30:OUT14.TMIN
CFGDO17outputTCELL30:OUT15.TMIN
CFGDO18outputTCELL31:OUT12.TMIN
CFGDO19outputTCELL31:OUT13.TMIN
CFGDO2outputTCELL23:OUT13.TMIN
CFGDO20outputTCELL31:OUT14.TMIN
CFGDO21outputTCELL31:OUT15.TMIN
CFGDO22outputTCELL32:OUT12.TMIN
CFGDO23outputTCELL32:OUT13.TMIN
CFGDO24outputTCELL32:OUT14.TMIN
CFGDO25outputTCELL32:OUT15.TMIN
CFGDO26outputTCELL33:OUT12.TMIN
CFGDO27outputTCELL33:OUT13.TMIN
CFGDO28outputTCELL33:OUT14.TMIN
CFGDO29outputTCELL33:OUT15.TMIN
CFGDO3outputTCELL23:OUT14.TMIN
CFGDO30outputTCELL34:OUT14.TMIN
CFGDO31outputTCELL35:OUT12.TMIN
CFGDO4outputTCELL23:OUT15.TMIN
CFGDO5outputTCELL24:OUT14.TMIN
CFGDO6outputTCELL25:OUT12.TMIN
CFGDO7outputTCELL26:OUT8.TMIN
CFGDO8outputTCELL27:OUT4.TMIN
CFGDO9outputTCELL28:OUT4.TMIN
CFGDSBUSNUMBER0inputTCELL0:IMUX.IMUX10.DELAY
CFGDSBUSNUMBER1inputTCELL0:IMUX.IMUX12.DELAY
CFGDSBUSNUMBER2inputTCELL0:IMUX.IMUX14.DELAY
CFGDSBUSNUMBER3inputTCELL0:IMUX.IMUX16.DELAY
CFGDSBUSNUMBER4inputTCELL20:IMUX.IMUX10.DELAY
CFGDSBUSNUMBER5inputTCELL20:IMUX.IMUX12.DELAY
CFGDSBUSNUMBER6inputTCELL20:IMUX.IMUX14.DELAY
CFGDSBUSNUMBER7inputTCELL20:IMUX.IMUX16.DELAY
CFGDSDEVICENUMBER0inputTCELL21:IMUX.IMUX10.DELAY
CFGDSDEVICENUMBER1inputTCELL21:IMUX.IMUX12.DELAY
CFGDSDEVICENUMBER2inputTCELL21:IMUX.IMUX14.DELAY
CFGDSDEVICENUMBER3inputTCELL21:IMUX.IMUX16.DELAY
CFGDSDEVICENUMBER4inputTCELL22:IMUX.IMUX14.DELAY
CFGDSFUNCTIONNUMBER0inputTCELL22:IMUX.IMUX16.DELAY
CFGDSFUNCTIONNUMBER1inputTCELL22:IMUX.IMUX18.DELAY
CFGDSFUNCTIONNUMBER2inputTCELL22:IMUX.IMUX19.DELAY
CFGDSN0inputTCELL26:IMUX.IMUX19.DELAY
CFGDSN1inputTCELL27:IMUX.IMUX16.DELAY
CFGDSN10inputTCELL29:IMUX.IMUX17.DELAY
CFGDSN11inputTCELL29:IMUX.IMUX18.DELAY
CFGDSN12inputTCELL29:IMUX.IMUX19.DELAY
CFGDSN13inputTCELL33:IMUX.IMUX14.DELAY
CFGDSN14inputTCELL33:IMUX.IMUX16.DELAY
CFGDSN15inputTCELL33:IMUX.IMUX17.DELAY
CFGDSN16inputTCELL33:IMUX.IMUX18.DELAY
CFGDSN17inputTCELL34:IMUX.IMUX18.DELAY
CFGDSN18inputTCELL35:IMUX.IMUX15.DELAY
CFGDSN19inputTCELL35:IMUX.IMUX16.DELAY
CFGDSN2inputTCELL27:IMUX.IMUX17.DELAY
CFGDSN20inputTCELL35:IMUX.IMUX17.DELAY
CFGDSN21inputTCELL35:IMUX.IMUX18.DELAY
CFGDSN22inputTCELL36:IMUX.IMUX13.DELAY
CFGDSN23inputTCELL36:IMUX.IMUX14.DELAY
CFGDSN24inputTCELL36:IMUX.IMUX15.DELAY
CFGDSN25inputTCELL36:IMUX.IMUX16.DELAY
CFGDSN26inputTCELL37:IMUX.IMUX13.DELAY
CFGDSN27inputTCELL37:IMUX.IMUX14.DELAY
CFGDSN28inputTCELL37:IMUX.IMUX15.DELAY
CFGDSN29inputTCELL37:IMUX.IMUX16.DELAY
CFGDSN3inputTCELL27:IMUX.IMUX18.DELAY
CFGDSN30inputTCELL38:IMUX.IMUX13.DELAY
CFGDSN31inputTCELL38:IMUX.IMUX14.DELAY
CFGDSN32inputTCELL38:IMUX.IMUX15.DELAY
CFGDSN33inputTCELL38:IMUX.IMUX16.DELAY
CFGDSN34inputTCELL39:IMUX.IMUX13.DELAY
CFGDSN35inputTCELL39:IMUX.IMUX14.DELAY
CFGDSN36inputTCELL39:IMUX.IMUX15.DELAY
CFGDSN37inputTCELL39:IMUX.IMUX16.DELAY
CFGDSN38inputTCELL19:IMUX.IMUX17.DELAY
CFGDSN39inputTCELL19:IMUX.IMUX18.DELAY
CFGDSN4inputTCELL27:IMUX.IMUX19.DELAY
CFGDSN40inputTCELL19:IMUX.IMUX19.DELAY
CFGDSN41inputTCELL19:IMUX.IMUX20.DELAY
CFGDSN42inputTCELL18:IMUX.IMUX21.DELAY
CFGDSN43inputTCELL17:IMUX.IMUX21.DELAY
CFGDSN44inputTCELL16:IMUX.IMUX21.DELAY
CFGDSN45inputTCELL13:IMUX.IMUX18.DELAY
CFGDSN46inputTCELL9:IMUX.IMUX16.DELAY
CFGDSN47inputTCELL9:IMUX.IMUX17.DELAY
CFGDSN48inputTCELL9:IMUX.IMUX18.DELAY
CFGDSN49inputTCELL9:IMUX.IMUX19.DELAY
CFGDSN5inputTCELL28:IMUX.IMUX16.DELAY
CFGDSN50inputTCELL8:IMUX.IMUX16.DELAY
CFGDSN51inputTCELL8:IMUX.IMUX17.DELAY
CFGDSN52inputTCELL8:IMUX.IMUX18.DELAY
CFGDSN53inputTCELL8:IMUX.IMUX19.DELAY
CFGDSN54inputTCELL7:IMUX.IMUX16.DELAY
CFGDSN55inputTCELL7:IMUX.IMUX17.DELAY
CFGDSN56inputTCELL7:IMUX.IMUX18.DELAY
CFGDSN57inputTCELL7:IMUX.IMUX19.DELAY
CFGDSN58inputTCELL6:IMUX.IMUX16.DELAY
CFGDSN59inputTCELL6:IMUX.IMUX17.DELAY
CFGDSN6inputTCELL28:IMUX.IMUX17.DELAY
CFGDSN60inputTCELL6:IMUX.IMUX18.DELAY
CFGDSN61inputTCELL6:IMUX.IMUX19.DELAY
CFGDSN62inputTCELL5:IMUX.IMUX18.DELAY
CFGDSN63inputTCELL3:IMUX.IMUX18.DELAY
CFGDSN7inputTCELL28:IMUX.IMUX18.DELAY
CFGDSN8inputTCELL28:IMUX.IMUX19.DELAY
CFGDSN9inputTCELL29:IMUX.IMUX16.DELAY
CFGDWADDR0inputTCELL15:IMUX.IMUX17.DELAY
CFGDWADDR1inputTCELL15:IMUX.IMUX18.DELAY
CFGDWADDR2inputTCELL14:IMUX.IMUX17.DELAY
CFGDWADDR3inputTCELL14:IMUX.IMUX18.DELAY
CFGDWADDR4inputTCELL13:IMUX.IMUX9.DELAY
CFGDWADDR5inputTCELL13:IMUX.IMUX10.DELAY
CFGDWADDR6inputTCELL13:IMUX.IMUX11.DELAY
CFGDWADDR7inputTCELL13:IMUX.IMUX12.DELAY
CFGDWADDR8inputTCELL12:IMUX.IMUX6.DELAY
CFGDWADDR9inputTCELL12:IMUX.IMUX8.DELAY
CFGERRACSNinputTCELL9:IMUX.IMUX8.DELAY
CFGERRAERHEADERLOG0inputTCELL9:IMUX.IMUX11.DELAY
CFGERRAERHEADERLOG1inputTCELL8:IMUX.IMUX8.DELAY
CFGERRAERHEADERLOG10inputTCELL6:IMUX.IMUX9.DELAY
CFGERRAERHEADERLOG100inputTCELL35:IMUX.IMUX14.DELAY
CFGERRAERHEADERLOG101inputTCELL36:IMUX.IMUX9.DELAY
CFGERRAERHEADERLOG102inputTCELL36:IMUX.IMUX10.DELAY
CFGERRAERHEADERLOG103inputTCELL36:IMUX.IMUX11.DELAY
CFGERRAERHEADERLOG104inputTCELL36:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG105inputTCELL37:IMUX.IMUX9.DELAY
CFGERRAERHEADERLOG106inputTCELL37:IMUX.IMUX10.DELAY
CFGERRAERHEADERLOG107inputTCELL37:IMUX.IMUX11.DELAY
CFGERRAERHEADERLOG108inputTCELL37:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG109inputTCELL38:IMUX.IMUX9.DELAY
CFGERRAERHEADERLOG11inputTCELL6:IMUX.IMUX10.DELAY
CFGERRAERHEADERLOG110inputTCELL38:IMUX.IMUX10.DELAY
CFGERRAERHEADERLOG111inputTCELL38:IMUX.IMUX11.DELAY
CFGERRAERHEADERLOG112inputTCELL38:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG113inputTCELL39:IMUX.IMUX9.DELAY
CFGERRAERHEADERLOG114inputTCELL39:IMUX.IMUX10.DELAY
CFGERRAERHEADERLOG115inputTCELL39:IMUX.IMUX11.DELAY
CFGERRAERHEADERLOG116inputTCELL39:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG117inputTCELL19:IMUX.IMUX13.DELAY
CFGERRAERHEADERLOG118inputTCELL19:IMUX.IMUX14.DELAY
CFGERRAERHEADERLOG119inputTCELL19:IMUX.IMUX15.DELAY
CFGERRAERHEADERLOG12inputTCELL6:IMUX.IMUX11.DELAY
CFGERRAERHEADERLOG120inputTCELL19:IMUX.IMUX16.DELAY
CFGERRAERHEADERLOG121inputTCELL18:IMUX.IMUX17.DELAY
CFGERRAERHEADERLOG122inputTCELL18:IMUX.IMUX18.DELAY
CFGERRAERHEADERLOG123inputTCELL18:IMUX.IMUX19.DELAY
CFGERRAERHEADERLOG124inputTCELL18:IMUX.IMUX20.DELAY
CFGERRAERHEADERLOG125inputTCELL17:IMUX.IMUX17.DELAY
CFGERRAERHEADERLOG126inputTCELL17:IMUX.IMUX18.DELAY
CFGERRAERHEADERLOG127inputTCELL17:IMUX.IMUX19.DELAY
CFGERRAERHEADERLOG13inputTCELL5:IMUX.IMUX9.DELAY
CFGERRAERHEADERLOG14inputTCELL5:IMUX.IMUX10.DELAY
CFGERRAERHEADERLOG15inputTCELL5:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG16inputTCELL5:IMUX.IMUX13.DELAY
CFGERRAERHEADERLOG17inputTCELL4:IMUX.IMUX8.DELAY
CFGERRAERHEADERLOG18inputTCELL4:IMUX.IMUX9.DELAY
CFGERRAERHEADERLOG19inputTCELL4:IMUX.IMUX10.DELAY
CFGERRAERHEADERLOG2inputTCELL8:IMUX.IMUX9.DELAY
CFGERRAERHEADERLOG20inputTCELL4:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG21inputTCELL3:IMUX.IMUX9.DELAY
CFGERRAERHEADERLOG22inputTCELL3:IMUX.IMUX10.DELAY
CFGERRAERHEADERLOG23inputTCELL3:IMUX.IMUX11.DELAY
CFGERRAERHEADERLOG24inputTCELL3:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG25inputTCELL2:IMUX.IMUX6.DELAY
CFGERRAERHEADERLOG26inputTCELL2:IMUX.IMUX8.DELAY
CFGERRAERHEADERLOG27inputTCELL2:IMUX.IMUX10.DELAY
CFGERRAERHEADERLOG28inputTCELL2:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG29inputTCELL1:IMUX.IMUX2.DELAY
CFGERRAERHEADERLOG3inputTCELL8:IMUX.IMUX10.DELAY
CFGERRAERHEADERLOG30inputTCELL1:IMUX.IMUX4.DELAY
CFGERRAERHEADERLOG31inputTCELL1:IMUX.IMUX6.DELAY
CFGERRAERHEADERLOG32inputTCELL1:IMUX.IMUX8.DELAY
CFGERRAERHEADERLOG33inputTCELL0:IMUX.IMUX2.DELAY
CFGERRAERHEADERLOG34inputTCELL0:IMUX.IMUX4.DELAY
CFGERRAERHEADERLOG35inputTCELL0:IMUX.IMUX6.DELAY
CFGERRAERHEADERLOG36inputTCELL0:IMUX.IMUX8.DELAY
CFGERRAERHEADERLOG37inputTCELL20:IMUX.IMUX2.DELAY
CFGERRAERHEADERLOG38inputTCELL20:IMUX.IMUX4.DELAY
CFGERRAERHEADERLOG39inputTCELL20:IMUX.IMUX6.DELAY
CFGERRAERHEADERLOG4inputTCELL8:IMUX.IMUX11.DELAY
CFGERRAERHEADERLOG40inputTCELL20:IMUX.IMUX8.DELAY
CFGERRAERHEADERLOG41inputTCELL21:IMUX.IMUX2.DELAY
CFGERRAERHEADERLOG42inputTCELL21:IMUX.IMUX4.DELAY
CFGERRAERHEADERLOG43inputTCELL21:IMUX.IMUX6.DELAY
CFGERRAERHEADERLOG44inputTCELL21:IMUX.IMUX8.DELAY
CFGERRAERHEADERLOG45inputTCELL22:IMUX.IMUX6.DELAY
CFGERRAERHEADERLOG46inputTCELL22:IMUX.IMUX8.DELAY
CFGERRAERHEADERLOG47inputTCELL22:IMUX.IMUX10.DELAY
CFGERRAERHEADERLOG48inputTCELL22:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG49inputTCELL23:IMUX.IMUX10.DELAY
CFGERRAERHEADERLOG5inputTCELL7:IMUX.IMUX8.DELAY
CFGERRAERHEADERLOG50inputTCELL23:IMUX.IMUX11.DELAY
CFGERRAERHEADERLOG51inputTCELL23:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG52inputTCELL23:IMUX.IMUX13.DELAY
CFGERRAERHEADERLOG53inputTCELL24:IMUX.IMUX8.DELAY
CFGERRAERHEADERLOG54inputTCELL24:IMUX.IMUX9.DELAY
CFGERRAERHEADERLOG55inputTCELL24:IMUX.IMUX10.DELAY
CFGERRAERHEADERLOG56inputTCELL24:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG57inputTCELL25:IMUX.IMUX10.DELAY
CFGERRAERHEADERLOG58inputTCELL25:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG59inputTCELL25:IMUX.IMUX13.DELAY
CFGERRAERHEADERLOG6inputTCELL7:IMUX.IMUX9.DELAY
CFGERRAERHEADERLOG60inputTCELL25:IMUX.IMUX14.DELAY
CFGERRAERHEADERLOG61inputTCELL26:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG62inputTCELL26:IMUX.IMUX13.DELAY
CFGERRAERHEADERLOG63inputTCELL26:IMUX.IMUX14.DELAY
CFGERRAERHEADERLOG64inputTCELL26:IMUX.IMUX15.DELAY
CFGERRAERHEADERLOG65inputTCELL27:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG66inputTCELL27:IMUX.IMUX13.DELAY
CFGERRAERHEADERLOG67inputTCELL27:IMUX.IMUX14.DELAY
CFGERRAERHEADERLOG68inputTCELL27:IMUX.IMUX15.DELAY
CFGERRAERHEADERLOG69inputTCELL28:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG7inputTCELL7:IMUX.IMUX10.DELAY
CFGERRAERHEADERLOG70inputTCELL28:IMUX.IMUX13.DELAY
CFGERRAERHEADERLOG71inputTCELL28:IMUX.IMUX14.DELAY
CFGERRAERHEADERLOG72inputTCELL28:IMUX.IMUX15.DELAY
CFGERRAERHEADERLOG73inputTCELL29:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG74inputTCELL29:IMUX.IMUX13.DELAY
CFGERRAERHEADERLOG75inputTCELL29:IMUX.IMUX14.DELAY
CFGERRAERHEADERLOG76inputTCELL29:IMUX.IMUX15.DELAY
CFGERRAERHEADERLOG77inputTCELL30:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG78inputTCELL30:IMUX.IMUX14.DELAY
CFGERRAERHEADERLOG79inputTCELL30:IMUX.IMUX16.DELAY
CFGERRAERHEADERLOG8inputTCELL7:IMUX.IMUX11.DELAY
CFGERRAERHEADERLOG80inputTCELL30:IMUX.IMUX18.DELAY
CFGERRAERHEADERLOG81inputTCELL31:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG82inputTCELL31:IMUX.IMUX14.DELAY
CFGERRAERHEADERLOG83inputTCELL31:IMUX.IMUX16.DELAY
CFGERRAERHEADERLOG84inputTCELL31:IMUX.IMUX18.DELAY
CFGERRAERHEADERLOG85inputTCELL32:IMUX.IMUX16.DELAY
CFGERRAERHEADERLOG86inputTCELL32:IMUX.IMUX18.DELAY
CFGERRAERHEADERLOG87inputTCELL32:IMUX.IMUX19.DELAY
CFGERRAERHEADERLOG88inputTCELL32:IMUX.IMUX20.DELAY
CFGERRAERHEADERLOG89inputTCELL33:IMUX.IMUX10.DELAY
CFGERRAERHEADERLOG9inputTCELL6:IMUX.IMUX8.DELAY
CFGERRAERHEADERLOG90inputTCELL33:IMUX.IMUX11.DELAY
CFGERRAERHEADERLOG91inputTCELL33:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG92inputTCELL33:IMUX.IMUX13.DELAY
CFGERRAERHEADERLOG93inputTCELL34:IMUX.IMUX13.DELAY
CFGERRAERHEADERLOG94inputTCELL34:IMUX.IMUX14.DELAY
CFGERRAERHEADERLOG95inputTCELL34:IMUX.IMUX16.DELAY
CFGERRAERHEADERLOG96inputTCELL34:IMUX.IMUX17.DELAY
CFGERRAERHEADERLOG97inputTCELL35:IMUX.IMUX10.DELAY
CFGERRAERHEADERLOG98inputTCELL35:IMUX.IMUX12.DELAY
CFGERRAERHEADERLOG99inputTCELL35:IMUX.IMUX13.DELAY
CFGERRAERHEADERLOGSETNoutputTCELL37:OUT4.TMIN
CFGERRCORNinputTCELL11:IMUX.IMUX6.DELAY
CFGERRCPLABORTNinputTCELL10:IMUX.IMUX6.DELAY
CFGERRCPLRDYNoutputTCELL38:OUT4.TMIN
CFGERRCPLTIMEOUTNinputTCELL10:IMUX.IMUX4.DELAY
CFGERRCPLUNEXPECTNinputTCELL10:IMUX.IMUX8.DELAY
CFGERRECRCNinputTCELL10:IMUX.IMUX2.DELAY
CFGERRLOCKEDNinputTCELL9:IMUX.IMUX10.DELAY
CFGERRPOSTEDNinputTCELL9:IMUX.IMUX9.DELAY
CFGERRTLPCPLHEADER0inputTCELL17:IMUX.IMUX20.DELAY
CFGERRTLPCPLHEADER1inputTCELL16:IMUX.IMUX17.DELAY
CFGERRTLPCPLHEADER10inputTCELL12:IMUX.IMUX14.DELAY
CFGERRTLPCPLHEADER11inputTCELL12:IMUX.IMUX16.DELAY
CFGERRTLPCPLHEADER12inputTCELL12:IMUX.IMUX18.DELAY
CFGERRTLPCPLHEADER13inputTCELL12:IMUX.IMUX19.DELAY
CFGERRTLPCPLHEADER14inputTCELL11:IMUX.IMUX10.DELAY
CFGERRTLPCPLHEADER15inputTCELL11:IMUX.IMUX12.DELAY
CFGERRTLPCPLHEADER16inputTCELL11:IMUX.IMUX14.DELAY
CFGERRTLPCPLHEADER17inputTCELL11:IMUX.IMUX16.DELAY
CFGERRTLPCPLHEADER18inputTCELL10:IMUX.IMUX10.DELAY
CFGERRTLPCPLHEADER19inputTCELL10:IMUX.IMUX12.DELAY
CFGERRTLPCPLHEADER2inputTCELL16:IMUX.IMUX18.DELAY
CFGERRTLPCPLHEADER20inputTCELL10:IMUX.IMUX14.DELAY
CFGERRTLPCPLHEADER21inputTCELL10:IMUX.IMUX16.DELAY
CFGERRTLPCPLHEADER22inputTCELL9:IMUX.IMUX12.DELAY
CFGERRTLPCPLHEADER23inputTCELL9:IMUX.IMUX13.DELAY
CFGERRTLPCPLHEADER24inputTCELL9:IMUX.IMUX14.DELAY
CFGERRTLPCPLHEADER25inputTCELL9:IMUX.IMUX15.DELAY
CFGERRTLPCPLHEADER26inputTCELL8:IMUX.IMUX12.DELAY
CFGERRTLPCPLHEADER27inputTCELL8:IMUX.IMUX13.DELAY
CFGERRTLPCPLHEADER28inputTCELL8:IMUX.IMUX14.DELAY
CFGERRTLPCPLHEADER29inputTCELL8:IMUX.IMUX15.DELAY
CFGERRTLPCPLHEADER3inputTCELL16:IMUX.IMUX19.DELAY
CFGERRTLPCPLHEADER30inputTCELL7:IMUX.IMUX12.DELAY
CFGERRTLPCPLHEADER31inputTCELL7:IMUX.IMUX13.DELAY
CFGERRTLPCPLHEADER32inputTCELL7:IMUX.IMUX14.DELAY
CFGERRTLPCPLHEADER33inputTCELL7:IMUX.IMUX15.DELAY
CFGERRTLPCPLHEADER34inputTCELL6:IMUX.IMUX12.DELAY
CFGERRTLPCPLHEADER35inputTCELL6:IMUX.IMUX13.DELAY
CFGERRTLPCPLHEADER36inputTCELL6:IMUX.IMUX14.DELAY
CFGERRTLPCPLHEADER37inputTCELL6:IMUX.IMUX15.DELAY
CFGERRTLPCPLHEADER38inputTCELL5:IMUX.IMUX14.DELAY
CFGERRTLPCPLHEADER39inputTCELL5:IMUX.IMUX15.DELAY
CFGERRTLPCPLHEADER4inputTCELL16:IMUX.IMUX20.DELAY
CFGERRTLPCPLHEADER40inputTCELL5:IMUX.IMUX16.DELAY
CFGERRTLPCPLHEADER41inputTCELL5:IMUX.IMUX17.DELAY
CFGERRTLPCPLHEADER42inputTCELL4:IMUX.IMUX13.DELAY
CFGERRTLPCPLHEADER43inputTCELL4:IMUX.IMUX14.DELAY
CFGERRTLPCPLHEADER44inputTCELL4:IMUX.IMUX16.DELAY
CFGERRTLPCPLHEADER45inputTCELL4:IMUX.IMUX17.DELAY
CFGERRTLPCPLHEADER46inputTCELL3:IMUX.IMUX13.DELAY
CFGERRTLPCPLHEADER47inputTCELL3:IMUX.IMUX14.DELAY
CFGERRTLPCPLHEADER5inputTCELL15:IMUX.IMUX20.DELAY
CFGERRTLPCPLHEADER6inputTCELL13:IMUX.IMUX13.DELAY
CFGERRTLPCPLHEADER7inputTCELL13:IMUX.IMUX14.DELAY
CFGERRTLPCPLHEADER8inputTCELL13:IMUX.IMUX16.DELAY
CFGERRTLPCPLHEADER9inputTCELL13:IMUX.IMUX17.DELAY
CFGERRURNinputTCELL11:IMUX.IMUX8.DELAY
CFGINTERRUPTASSERTNinputTCELL1:IMUX.IMUX16.DELAY
CFGINTERRUPTDI0inputTCELL3:IMUX.IMUX17.DELAY
CFGINTERRUPTDI1inputTCELL2:IMUX.IMUX14.DELAY
CFGINTERRUPTDI2inputTCELL2:IMUX.IMUX16.DELAY
CFGINTERRUPTDI3inputTCELL2:IMUX.IMUX18.DELAY
CFGINTERRUPTDI4inputTCELL2:IMUX.IMUX19.DELAY
CFGINTERRUPTDI5inputTCELL1:IMUX.IMUX10.DELAY
CFGINTERRUPTDI6inputTCELL1:IMUX.IMUX12.DELAY
CFGINTERRUPTDI7inputTCELL1:IMUX.IMUX14.DELAY
CFGINTERRUPTDO0outputTCELL19:OUT13.TMIN
CFGINTERRUPTDO1outputTCELL19:OUT14.TMIN
CFGINTERRUPTDO2outputTCELL19:OUT15.TMIN
CFGINTERRUPTDO3outputTCELL18:OUT4.TMIN
CFGINTERRUPTDO4outputTCELL18:OUT8.TMIN
CFGINTERRUPTDO5outputTCELL18:OUT9.TMIN
CFGINTERRUPTDO6outputTCELL18:OUT10.TMIN
CFGINTERRUPTDO7outputTCELL17:OUT4.TMIN
CFGINTERRUPTMMENABLE0outputTCELL39:OUT13.TMIN
CFGINTERRUPTMMENABLE1outputTCELL39:OUT14.TMIN
CFGINTERRUPTMMENABLE2outputTCELL39:OUT15.TMIN
CFGINTERRUPTMSIENABLEoutputTCELL19:OUT12.TMIN
CFGINTERRUPTMSIXENABLEoutputTCELL17:OUT7.TMIN
CFGINTERRUPTMSIXFMoutputTCELL17:OUT8.TMIN
CFGINTERRUPTNinputTCELL3:IMUX.IMUX16.DELAY
CFGINTERRUPTRDYNoutputTCELL39:OUT12.TMIN
CFGLINKCONTROLASPMCONTROL0outputTCELL17:OUT10.TMIN
CFGLINKCONTROLASPMCONTROL1outputTCELL16:OUT11.TMIN
CFGLINKCONTROLAUTOBANDWIDTHINTENoutputTCELL12:OUT19.TMIN
CFGLINKCONTROLBANDWIDTHINTENoutputTCELL12:OUT18.TMIN
CFGLINKCONTROLCLOCKPMENoutputTCELL12:OUT16.TMIN
CFGLINKCONTROLCOMMONCLOCKoutputTCELL13:OUT17.TMIN
CFGLINKCONTROLEXTENDEDSYNCoutputTCELL13:OUT18.TMIN
CFGLINKCONTROLHWAUTOWIDTHDISoutputTCELL12:OUT17.TMIN
CFGLINKCONTROLLINKDISABLEoutputTCELL15:OUT13.TMIN
CFGLINKCONTROLRCBoutputTCELL15:OUT12.TMIN
CFGLINKCONTROLRETRAINLINKoutputTCELL15:OUT14.TMIN
CFGLINKSTATUSAUTOBANDWIDTHSTATUSoutputTCELL18:OUT11.TMIN
CFGLINKSTATUSBANDWITHSTATUSoutputTCELL19:OUT19.TMIN
CFGLINKSTATUSCURRENTSPEED0outputTCELL33:OUT17.TMIN
CFGLINKSTATUSCURRENTSPEED1outputTCELL33:OUT18.TMIN
CFGLINKSTATUSDLLACTIVEoutputTCELL19:OUT18.TMIN
CFGLINKSTATUSLINKTRAININGoutputTCELL19:OUT17.TMIN
CFGLINKSTATUSNEGOTIATEDWIDTH0outputTCELL39:OUT16.TMIN
CFGLINKSTATUSNEGOTIATEDWIDTH1outputTCELL39:OUT17.TMIN
CFGLINKSTATUSNEGOTIATEDWIDTH2outputTCELL39:OUT18.TMIN
CFGLINKSTATUSNEGOTIATEDWIDTH3outputTCELL19:OUT16.TMIN
CFGMSGDATA0outputTCELL16:OUT5.TMIN
CFGMSGDATA1outputTCELL16:OUT7.TMIN
CFGMSGDATA10outputTCELL14:OUT13.TMIN
CFGMSGDATA11outputTCELL13:OUT12.TMIN
CFGMSGDATA12outputTCELL13:OUT13.TMIN
CFGMSGDATA13outputTCELL13:OUT14.TMIN
CFGMSGDATA14outputTCELL13:OUT15.TMIN
CFGMSGDATA15outputTCELL12:OUT12.TMIN
CFGMSGDATA2outputTCELL16:OUT8.TMIN
CFGMSGDATA3outputTCELL16:OUT10.TMIN
CFGMSGDATA4outputTCELL15:OUT8.TMIN
CFGMSGDATA5outputTCELL15:OUT9.TMIN
CFGMSGDATA6outputTCELL15:OUT10.TMIN
CFGMSGDATA7outputTCELL15:OUT11.TMIN
CFGMSGDATA8outputTCELL14:OUT11.TMIN
CFGMSGDATA9outputTCELL14:OUT12.TMIN
CFGMSGRECEIVEDoutputTCELL17:OUT9.TMIN
CFGMSGRECEIVEDASSERTINTAoutputTCELL11:OUT12.TMIN
CFGMSGRECEIVEDASSERTINTBoutputTCELL11:OUT14.TMIN
CFGMSGRECEIVEDASSERTINTCoutputTCELL10:OUT12.TMIN
CFGMSGRECEIVEDASSERTINTDoutputTCELL10:OUT14.TMIN
CFGMSGRECEIVEDDEASSERTINTAoutputTCELL11:OUT13.TMIN
CFGMSGRECEIVEDDEASSERTINTBoutputTCELL11:OUT15.TMIN
CFGMSGRECEIVEDDEASSERTINTCoutputTCELL10:OUT13.TMIN
CFGMSGRECEIVEDDEASSERTINTDoutputTCELL10:OUT15.TMIN
CFGMSGRECEIVEDERRCORoutputTCELL12:OUT13.TMIN
CFGMSGRECEIVEDERRFATALoutputTCELL12:OUT15.TMIN
CFGMSGRECEIVEDERRNONFATALoutputTCELL12:OUT14.TMIN
CFGMSGRECEIVEDPMASNAKoutputTCELL7:OUT10.TMIN
CFGMSGRECEIVEDPMETOoutputTCELL9:OUT14.TMIN
CFGMSGRECEIVEDPMETOACKoutputTCELL9:OUT13.TMIN
CFGMSGRECEIVEDPMPMEoutputTCELL9:OUT12.TMIN
CFGMSGRECEIVEDSETSLOTPOWERLIMIToutputTCELL9:OUT15.TMIN
CFGMSGRECEIVEDUNLOCKoutputTCELL8:OUT10.TMIN
CFGPCIELINKSTATE0outputTCELL6:OUT12.TMIN
CFGPCIELINKSTATE1outputTCELL5:OUT12.TMIN
CFGPCIELINKSTATE2outputTCELL4:OUT14.TMIN
CFGPMCSRPMEENoutputTCELL12:OUT21.TMIN
CFGPMCSRPMESTATUSoutputTCELL13:OUT20.TMIN
CFGPMCSRPOWERSTATE0outputTCELL9:OUT23.TMIN
CFGPMCSRPOWERSTATE1outputTCELL9:OUT22.TMIN
CFGPMDIRECTASPML1NinputTCELL25:IMUX.IMUX16.DELAY
CFGPMRCVASREQL1NoutputTCELL4:OUT15.TMIN
CFGPMRCVENTERL1NoutputTCELL3:OUT12.TMIN
CFGPMRCVENTERL23NoutputTCELL3:OUT13.TMIN
CFGPMRCVREQACKNoutputTCELL3:OUT14.TMIN
CFGPMSENDPMACKNinputTCELL25:IMUX.IMUX18.DELAY
CFGPMSENDPMETONinputTCELL26:IMUX.IMUX17.DELAY
CFGPMSENDPMNAKNinputTCELL26:IMUX.IMUX16.DELAY
CFGPMTURNOFFOKNinputTCELL25:IMUX.IMUX17.DELAY
CFGPMWAKENinputTCELL25:IMUX.IMUX15.DELAY
CFGPORTNUMBER0inputTCELL23:IMUX.IMUX14.DELAY
CFGPORTNUMBER1inputTCELL23:IMUX.IMUX16.DELAY
CFGPORTNUMBER2inputTCELL23:IMUX.IMUX17.DELAY
CFGPORTNUMBER3inputTCELL23:IMUX.IMUX18.DELAY
CFGPORTNUMBER4inputTCELL24:IMUX.IMUX13.DELAY
CFGPORTNUMBER5inputTCELL24:IMUX.IMUX14.DELAY
CFGPORTNUMBER6inputTCELL24:IMUX.IMUX16.DELAY
CFGPORTNUMBER7inputTCELL24:IMUX.IMUX17.DELAY
CFGRDENNinputTCELL11:IMUX.IMUX4.DELAY
CFGRDWRDONENoutputTCELL36:OUT8.TMIN
CFGSLOTCONTROLELECTROMECHILCTLPULSEoutputTCELL10:OUT17.TMIN
CFGTRANSACTIONoutputTCELL3:OUT15.TMIN
CFGTRANSACTIONADDR0outputTCELL2:OUT13.TMIN
CFGTRANSACTIONADDR1outputTCELL2:OUT14.TMIN
CFGTRANSACTIONADDR2outputTCELL2:OUT15.TMIN
CFGTRANSACTIONADDR3outputTCELL1:OUT12.TMIN
CFGTRANSACTIONADDR4outputTCELL1:OUT13.TMIN
CFGTRANSACTIONADDR5outputTCELL1:OUT14.TMIN
CFGTRANSACTIONADDR6outputTCELL1:OUT15.TMIN
CFGTRANSACTIONTYPEoutputTCELL2:OUT12.TMIN
CFGTRNPENDINGNinputTCELL26:IMUX.IMUX18.DELAY
CFGVCTCVCMAP0outputTCELL9:OUT16.TMIN
CFGVCTCVCMAP1outputTCELL9:OUT17.TMIN
CFGVCTCVCMAP2outputTCELL9:OUT18.TMIN
CFGVCTCVCMAP3outputTCELL9:OUT19.TMIN
CFGVCTCVCMAP4outputTCELL8:OUT12.TMIN
CFGVCTCVCMAP5outputTCELL8:OUT13.TMIN
CFGVCTCVCMAP6outputTCELL8:OUT14.TMIN
CFGWRENNinputTCELL11:IMUX.IMUX2.DELAY
CFGWRREADONLYNinputTCELL12:IMUX.IMUX12.DELAY
CFGWRRW1CASRWNinputTCELL12:IMUX.IMUX10.DELAY
CMRSTNinputTCELL20:IMUX.CTRL1
CMSTICKYRSTNinputTCELL21:IMUX.CTRL0
DBGMODE0inputTCELL7:IMUX.IMUX20.DELAY
DBGMODE1inputTCELL6:IMUX.IMUX20.DELAY
DBGSCLRAoutputTCELL30:OUT20.TMIN
DBGSCLRBoutputTCELL31:OUT19.TMIN
DBGSCLRCoutputTCELL32:OUT19.TMIN
DBGSCLRDoutputTCELL32:OUT20.TMIN
DBGSCLREoutputTCELL33:OUT19.TMIN
DBGSCLRFoutputTCELL33:OUT20.TMIN
DBGSCLRGoutputTCELL34:OUT15.TMIN
DBGSCLRHoutputTCELL34:OUT16.TMIN
DBGSCLRIoutputTCELL35:OUT13.TMIN
DBGSCLRJoutputTCELL35:OUT14.TMIN
DBGSCLRKoutputTCELL35:OUT15.TMIN
DBGSUBMODEinputTCELL36:IMUX.IMUX21.DELAY
DBGVECA0outputTCELL10:OUT21.TMIN
DBGVECA1outputTCELL10:OUT22.TMIN
DBGVECA10outputTCELL5:OUT15.TMIN
DBGVECA11outputTCELL5:OUT17.TMIN
DBGVECA12outputTCELL5:OUT21.TMIN
DBGVECA13outputTCELL4:OUT18.TMIN
DBGVECA14outputTCELL4:OUT20.TMIN
DBGVECA15outputTCELL4:OUT22.TMIN
DBGVECA16outputTCELL3:OUT20.TMIN
DBGVECA17outputTCELL3:OUT21.TMIN
DBGVECA18outputTCELL3:OUT22.TMIN
DBGVECA19outputTCELL3:OUT23.TMIN
DBGVECA2outputTCELL10:OUT23.TMIN
DBGVECA20outputTCELL2:OUT20.TMIN
DBGVECA21outputTCELL2:OUT21.TMIN
DBGVECA22outputTCELL2:OUT22.TMIN
DBGVECA23outputTCELL2:OUT23.TMIN
DBGVECA24outputTCELL1:OUT21.TMIN
DBGVECA25outputTCELL1:OUT23.TMIN
DBGVECA26outputTCELL0:OUT19.TMIN
DBGVECA27outputTCELL0:OUT20.TMIN
DBGVECA28outputTCELL0:OUT21.TMIN
DBGVECA29outputTCELL0:OUT22.TMIN
DBGVECA3outputTCELL9:OUT20.TMIN
DBGVECA30outputTCELL20:OUT21.TMIN
DBGVECA31outputTCELL20:OUT22.TMIN
DBGVECA32outputTCELL20:OUT23.TMIN
DBGVECA33outputTCELL21:OUT20.TMIN
DBGVECA34outputTCELL21:OUT21.TMIN
DBGVECA35outputTCELL21:OUT23.TMIN
DBGVECA36outputTCELL22:OUT21.TMIN
DBGVECA37outputTCELL22:OUT22.TMIN
DBGVECA38outputTCELL22:OUT23.TMIN
DBGVECA39outputTCELL23:OUT21.TMIN
DBGVECA4outputTCELL7:OUT13.TMIN
DBGVECA40outputTCELL23:OUT22.TMIN
DBGVECA41outputTCELL23:OUT23.TMIN
DBGVECA42outputTCELL24:OUT18.TMIN
DBGVECA43outputTCELL24:OUT20.TMIN
DBGVECA44outputTCELL24:OUT22.TMIN
DBGVECA45outputTCELL25:OUT17.TMIN
DBGVECA46outputTCELL25:OUT21.TMIN
DBGVECA47outputTCELL26:OUT13.TMIN
DBGVECA48outputTCELL26:OUT14.TMIN
DBGVECA49outputTCELL26:OUT15.TMIN
DBGVECA5outputTCELL7:OUT14.TMIN
DBGVECA50outputTCELL26:OUT18.TMIN
DBGVECA51outputTCELL27:OUT11.TMIN
DBGVECA52outputTCELL27:OUT12.TMIN
DBGVECA53outputTCELL27:OUT13.TMIN
DBGVECA54outputTCELL27:OUT14.TMIN
DBGVECA55outputTCELL28:OUT11.TMIN
DBGVECA56outputTCELL28:OUT12.TMIN
DBGVECA57outputTCELL28:OUT13.TMIN
DBGVECA58outputTCELL28:OUT14.TMIN
DBGVECA59outputTCELL29:OUT21.TMIN
DBGVECA6outputTCELL7:OUT15.TMIN
DBGVECA60outputTCELL29:OUT22.TMIN
DBGVECA61outputTCELL29:OUT23.TMIN
DBGVECA62outputTCELL30:OUT21.TMIN
DBGVECA63outputTCELL30:OUT22.TMIN
DBGVECA7outputTCELL6:OUT15.TMIN
DBGVECA8outputTCELL6:OUT18.TMIN
DBGVECA9outputTCELL6:OUT22.TMIN
DBGVECB0outputTCELL30:OUT23.TMIN
DBGVECB1outputTCELL31:OUT20.TMIN
DBGVECB10outputTCELL34:OUT18.TMIN
DBGVECB11outputTCELL34:OUT20.TMIN
DBGVECB12outputTCELL34:OUT22.TMIN
DBGVECB13outputTCELL35:OUT17.TMIN
DBGVECB14outputTCELL35:OUT21.TMIN
DBGVECB15outputTCELL36:OUT13.TMIN
DBGVECB16outputTCELL36:OUT14.TMIN
DBGVECB17outputTCELL36:OUT15.TMIN
DBGVECB18outputTCELL36:OUT18.TMIN
DBGVECB19outputTCELL37:OUT11.TMIN
DBGVECB2outputTCELL31:OUT21.TMIN
DBGVECB20outputTCELL37:OUT12.TMIN
DBGVECB21outputTCELL37:OUT13.TMIN
DBGVECB22outputTCELL37:OUT14.TMIN
DBGVECB23outputTCELL38:OUT11.TMIN
DBGVECB24outputTCELL38:OUT12.TMIN
DBGVECB25outputTCELL38:OUT13.TMIN
DBGVECB26outputTCELL38:OUT14.TMIN
DBGVECB27outputTCELL39:OUT21.TMIN
DBGVECB28outputTCELL39:OUT22.TMIN
DBGVECB29outputTCELL39:OUT23.TMIN
DBGVECB3outputTCELL31:OUT23.TMIN
DBGVECB30outputTCELL19:OUT23.TMIN
DBGVECB31outputTCELL18:OUT14.TMIN
DBGVECB32outputTCELL18:OUT15.TMIN
DBGVECB33outputTCELL17:OUT13.TMIN
DBGVECB34outputTCELL17:OUT14.TMIN
DBGVECB35outputTCELL17:OUT15.TMIN
DBGVECB36outputTCELL16:OUT14.TMIN
DBGVECB37outputTCELL16:OUT15.TMIN
DBGVECB38outputTCELL16:OUT22.TMIN
DBGVECB39outputTCELL15:OUT17.TMIN
DBGVECB4outputTCELL32:OUT21.TMIN
DBGVECB40outputTCELL15:OUT21.TMIN
DBGVECB41outputTCELL14:OUT18.TMIN
DBGVECB42outputTCELL14:OUT20.TMIN
DBGVECB43outputTCELL14:OUT22.TMIN
DBGVECB44outputTCELL13:OUT21.TMIN
DBGVECB45outputTCELL13:OUT22.TMIN
DBGVECB46outputTCELL13:OUT23.TMIN
DBGVECB47outputTCELL12:OUT22.TMIN
DBGVECB48outputTCELL12:OUT23.TMIN
DBGVECB49outputTCELL8:OUT11.TMIN
DBGVECB5outputTCELL32:OUT22.TMIN
DBGVECB50outputTCELL8:OUT15.TMIN
DBGVECB51outputTCELL7:OUT11.TMIN
DBGVECB52outputTCELL7:OUT12.TMIN
DBGVECB53outputTCELL6:OUT13.TMIN
DBGVECB54outputTCELL6:OUT14.TMIN
DBGVECB55outputTCELL5:OUT13.TMIN
DBGVECB56outputTCELL5:OUT14.TMIN
DBGVECB57outputTCELL4:OUT16.TMIN
DBGVECB58outputTCELL1:OUT20.TMIN
DBGVECB59outputTCELL0:OUT23.TMIN
DBGVECB6outputTCELL32:OUT23.TMIN
DBGVECB60outputTCELL21:OUT19.TMIN
DBGVECB61outputTCELL22:OUT19.TMIN
DBGVECB62outputTCELL22:OUT20.TMIN
DBGVECB63outputTCELL23:OUT19.TMIN
DBGVECB7outputTCELL33:OUT21.TMIN
DBGVECB8outputTCELL33:OUT22.TMIN
DBGVECB9outputTCELL33:OUT23.TMIN
DBGVECC0outputTCELL23:OUT20.TMIN
DBGVECC1outputTCELL24:OUT15.TMIN
DBGVECC10outputTCELL29:OUT20.TMIN
DBGVECC11outputTCELL30:OUT19.TMIN
DBGVECC2outputTCELL24:OUT16.TMIN
DBGVECC3outputTCELL25:OUT13.TMIN
DBGVECC4outputTCELL25:OUT14.TMIN
DBGVECC5outputTCELL25:OUT15.TMIN
DBGVECC6outputTCELL26:OUT22.TMIN
DBGVECC7outputTCELL27:OUT15.TMIN
DBGVECC8outputTCELL28:OUT15.TMIN
DBGVECC9outputTCELL29:OUT19.TMIN
DLRSTNinputTCELL22:IMUX.CTRL1
DRPCLKinputTCELL28:IMUX.CLK0
DRPDADDR0inputTCELL28:IMUX.IMUX20.DELAY
DRPDADDR1inputTCELL29:IMUX.IMUX20.DELAY
DRPDADDR2inputTCELL29:IMUX.IMUX21.DELAY
DRPDADDR3inputTCELL29:IMUX.IMUX22.DELAY
DRPDADDR4inputTCELL33:IMUX.IMUX19.DELAY
DRPDADDR5inputTCELL35:IMUX.IMUX20.DELAY
DRPDADDR6inputTCELL36:IMUX.IMUX17.DELAY
DRPDADDR7inputTCELL36:IMUX.IMUX18.DELAY
DRPDADDR8inputTCELL36:IMUX.IMUX19.DELAY
DRPDENinputTCELL26:IMUX.IMUX20.DELAY
DRPDI0inputTCELL36:IMUX.IMUX20.DELAY
DRPDI1inputTCELL37:IMUX.IMUX17.DELAY
DRPDI10inputTCELL39:IMUX.IMUX18.DELAY
DRPDI11inputTCELL39:IMUX.IMUX19.DELAY
DRPDI12inputTCELL39:IMUX.IMUX20.DELAY
DRPDI13inputTCELL19:IMUX.IMUX21.DELAY
DRPDI14inputTCELL9:IMUX.IMUX20.DELAY
DRPDI15inputTCELL8:IMUX.IMUX20.DELAY
DRPDI2inputTCELL37:IMUX.IMUX18.DELAY
DRPDI3inputTCELL37:IMUX.IMUX19.DELAY
DRPDI4inputTCELL37:IMUX.IMUX20.DELAY
DRPDI5inputTCELL38:IMUX.IMUX17.DELAY
DRPDI6inputTCELL38:IMUX.IMUX18.DELAY
DRPDI7inputTCELL38:IMUX.IMUX19.DELAY
DRPDI8inputTCELL38:IMUX.IMUX20.DELAY
DRPDI9inputTCELL39:IMUX.IMUX17.DELAY
DRPDO0outputTCELL3:OUT17.TMIN
DRPDO1outputTCELL3:OUT18.TMIN
DRPDO10outputTCELL19:OUT20.TMIN
DRPDO11outputTCELL19:OUT21.TMIN
DRPDO12outputTCELL12:OUT20.TMIN
DRPDO13outputTCELL11:OUT21.TMIN
DRPDO14outputTCELL11:OUT23.TMIN
DRPDO15outputTCELL10:OUT20.TMIN
DRPDO2outputTCELL3:OUT19.TMIN
DRPDO3outputTCELL2:OUT16.TMIN
DRPDO4outputTCELL2:OUT17.TMIN
DRPDO5outputTCELL2:OUT18.TMIN
DRPDO6outputTCELL2:OUT19.TMIN
DRPDO7outputTCELL1:OUT16.TMIN
DRPDO8outputTCELL1:OUT17.TMIN
DRPDO9outputTCELL1:OUT19.TMIN
DRPDRDYoutputTCELL3:OUT16.TMIN
DRPDWEinputTCELL27:IMUX.IMUX20.DELAY
FUNCLVLRSTNinputTCELL21:IMUX.CTRL1
LL2BADDLLPERRNoutputTCELL21:OUT12.TMIN
LL2BADTLPERRNoutputTCELL0:OUT12.TMIN
LL2PROTOCOLERRNoutputTCELL0:OUT11.TMIN
LL2REPLAYROERRNoutputTCELL21:OUT13.TMIN
LL2REPLAYTOERRNoutputTCELL21:OUT14.TMIN
LL2SENDASREQL1NinputTCELL27:IMUX.IMUX11.DELAY
LL2SENDENTERL1NinputTCELL27:IMUX.IMUX9.DELAY
LL2SENDENTERL23NinputTCELL27:IMUX.IMUX10.DELAY
LL2SUSPENDNOWNinputTCELL29:IMUX.IMUX9.DELAY
LL2SUSPENDOKNoutputTCELL1:OUT8.TMIN
LL2TFCINIT1SEQNoutputTCELL3:OUT11.TMIN
LL2TFCINIT2SEQNoutputTCELL2:OUT8.TMIN
LL2TLPRCVNinputTCELL27:IMUX.IMUX8.DELAY
LNKCLKENoutputTCELL9:OUT21.TMIN
MIMRXRADDR0outputTCELL37:OUT9.TMIN
MIMRXRADDR1outputTCELL37:OUT10.TMIN
MIMRXRADDR10outputTCELL19:OUT8.TMIN
MIMRXRADDR11outputTCELL19:OUT9.TMIN
MIMRXRADDR12outputTCELL19:OUT10.TMIN
MIMRXRADDR2outputTCELL38:OUT7.TMIN
MIMRXRADDR3outputTCELL38:OUT8.TMIN
MIMRXRADDR4outputTCELL38:OUT9.TMIN
MIMRXRADDR5outputTCELL38:OUT10.TMIN
MIMRXRADDR6outputTCELL39:OUT8.TMIN
MIMRXRADDR7outputTCELL39:OUT9.TMIN
MIMRXRADDR8outputTCELL39:OUT10.TMIN
MIMRXRADDR9outputTCELL39:OUT11.TMIN
MIMRXRCEoutputTCELL18:OUT7.TMIN
MIMRXRDATA0inputTCELL29:IMUX.IMUX6.DELAY
MIMRXRDATA1inputTCELL29:IMUX.IMUX7.DELAY
MIMRXRDATA10inputTCELL32:IMUX.IMUX6.DELAY
MIMRXRDATA11inputTCELL32:IMUX.IMUX8.DELAY
MIMRXRDATA12inputTCELL32:IMUX.IMUX10.DELAY
MIMRXRDATA13inputTCELL32:IMUX.IMUX12.DELAY
MIMRXRDATA14inputTCELL33:IMUX.IMUX5.DELAY
MIMRXRDATA15inputTCELL33:IMUX.IMUX6.DELAY
MIMRXRDATA16inputTCELL33:IMUX.IMUX7.DELAY
MIMRXRDATA17inputTCELL33:IMUX.IMUX8.DELAY
MIMRXRDATA18inputTCELL34:IMUX.IMUX6.DELAY
MIMRXRDATA19inputTCELL34:IMUX.IMUX8.DELAY
MIMRXRDATA2inputTCELL30:IMUX.IMUX2.DELAY
MIMRXRDATA20inputTCELL34:IMUX.IMUX9.DELAY
MIMRXRDATA21inputTCELL34:IMUX.IMUX10.DELAY
MIMRXRDATA22inputTCELL35:IMUX.IMUX4.DELAY
MIMRXRDATA23inputTCELL35:IMUX.IMUX6.DELAY
MIMRXRDATA24inputTCELL35:IMUX.IMUX7.DELAY
MIMRXRDATA25inputTCELL35:IMUX.IMUX8.DELAY
MIMRXRDATA26inputTCELL36:IMUX.IMUX4.DELAY
MIMRXRDATA27inputTCELL36:IMUX.IMUX5.DELAY
MIMRXRDATA28inputTCELL36:IMUX.IMUX6.DELAY
MIMRXRDATA29inputTCELL36:IMUX.IMUX7.DELAY
MIMRXRDATA3inputTCELL30:IMUX.IMUX4.DELAY
MIMRXRDATA30inputTCELL37:IMUX.IMUX4.DELAY
MIMRXRDATA31inputTCELL37:IMUX.IMUX5.DELAY
MIMRXRDATA32inputTCELL37:IMUX.IMUX6.DELAY
MIMRXRDATA33inputTCELL37:IMUX.IMUX7.DELAY
MIMRXRDATA34inputTCELL38:IMUX.IMUX4.DELAY
MIMRXRDATA35inputTCELL38:IMUX.IMUX5.DELAY
MIMRXRDATA36inputTCELL38:IMUX.IMUX6.DELAY
MIMRXRDATA37inputTCELL38:IMUX.IMUX7.DELAY
MIMRXRDATA38inputTCELL39:IMUX.IMUX4.DELAY
MIMRXRDATA39inputTCELL39:IMUX.IMUX5.DELAY
MIMRXRDATA4inputTCELL30:IMUX.IMUX6.DELAY
MIMRXRDATA40inputTCELL39:IMUX.IMUX6.DELAY
MIMRXRDATA41inputTCELL39:IMUX.IMUX7.DELAY
MIMRXRDATA42inputTCELL19:IMUX.IMUX4.DELAY
MIMRXRDATA43inputTCELL19:IMUX.IMUX5.DELAY
MIMRXRDATA44inputTCELL19:IMUX.IMUX6.DELAY
MIMRXRDATA45inputTCELL19:IMUX.IMUX7.DELAY
MIMRXRDATA46inputTCELL18:IMUX.IMUX4.DELAY
MIMRXRDATA47inputTCELL18:IMUX.IMUX5.DELAY
MIMRXRDATA48inputTCELL18:IMUX.IMUX6.DELAY
MIMRXRDATA49inputTCELL18:IMUX.IMUX7.DELAY
MIMRXRDATA5inputTCELL30:IMUX.IMUX8.DELAY
MIMRXRDATA50inputTCELL17:IMUX.IMUX4.DELAY
MIMRXRDATA51inputTCELL17:IMUX.IMUX5.DELAY
MIMRXRDATA52inputTCELL17:IMUX.IMUX6.DELAY
MIMRXRDATA53inputTCELL17:IMUX.IMUX7.DELAY
MIMRXRDATA54inputTCELL16:IMUX.IMUX4.DELAY
MIMRXRDATA55inputTCELL16:IMUX.IMUX5.DELAY
MIMRXRDATA56inputTCELL16:IMUX.IMUX6.DELAY
MIMRXRDATA57inputTCELL16:IMUX.IMUX7.DELAY
MIMRXRDATA58inputTCELL15:IMUX.IMUX4.DELAY
MIMRXRDATA59inputTCELL15:IMUX.IMUX6.DELAY
MIMRXRDATA6inputTCELL31:IMUX.IMUX2.DELAY
MIMRXRDATA60inputTCELL15:IMUX.IMUX7.DELAY
MIMRXRDATA61inputTCELL15:IMUX.IMUX8.DELAY
MIMRXRDATA62inputTCELL14:IMUX.IMUX6.DELAY
MIMRXRDATA63inputTCELL14:IMUX.IMUX8.DELAY
MIMRXRDATA64inputTCELL14:IMUX.IMUX9.DELAY
MIMRXRDATA65inputTCELL14:IMUX.IMUX10.DELAY
MIMRXRDATA66inputTCELL13:IMUX.IMUX5.DELAY
MIMRXRDATA67inputTCELL13:IMUX.IMUX6.DELAY
MIMRXRDATA7inputTCELL31:IMUX.IMUX4.DELAY
MIMRXRDATA8inputTCELL31:IMUX.IMUX6.DELAY
MIMRXRDATA9inputTCELL31:IMUX.IMUX8.DELAY
MIMRXRENoutputTCELL19:OUT11.TMIN
MIMRXWADDR0outputTCELL34:OUT10.TMIN
MIMRXWADDR1outputTCELL34:OUT11.TMIN
MIMRXWADDR10outputTCELL36:OUT11.TMIN
MIMRXWADDR11outputTCELL36:OUT12.TMIN
MIMRXWADDR12outputTCELL37:OUT7.TMIN
MIMRXWADDR2outputTCELL34:OUT12.TMIN
MIMRXWADDR3outputTCELL34:OUT13.TMIN
MIMRXWADDR4outputTCELL35:OUT8.TMIN
MIMRXWADDR5outputTCELL35:OUT9.TMIN
MIMRXWADDR6outputTCELL35:OUT10.TMIN
MIMRXWADDR7outputTCELL35:OUT11.TMIN
MIMRXWADDR8outputTCELL36:OUT9.TMIN
MIMRXWADDR9outputTCELL36:OUT10.TMIN
MIMRXWDATA0outputTCELL3:OUT5.TMIN
MIMRXWDATA1outputTCELL3:OUT6.TMIN
MIMRXWDATA10outputTCELL1:OUT7.TMIN
MIMRXWDATA11outputTCELL0:OUT4.TMIN
MIMRXWDATA12outputTCELL0:OUT5.TMIN
MIMRXWDATA13outputTCELL0:OUT7.TMIN
MIMRXWDATA14outputTCELL0:OUT8.TMIN
MIMRXWDATA15outputTCELL20:OUT20.TMIN
MIMRXWDATA16outputTCELL21:OUT8.TMIN
MIMRXWDATA17outputTCELL21:OUT9.TMIN
MIMRXWDATA18outputTCELL21:OUT10.TMIN
MIMRXWDATA19outputTCELL21:OUT11.TMIN
MIMRXWDATA2outputTCELL3:OUT7.TMIN
MIMRXWDATA20outputTCELL22:OUT8.TMIN
MIMRXWDATA21outputTCELL22:OUT9.TMIN
MIMRXWDATA22outputTCELL22:OUT10.TMIN
MIMRXWDATA23outputTCELL22:OUT11.TMIN
MIMRXWDATA24outputTCELL23:OUT8.TMIN
MIMRXWDATA25outputTCELL23:OUT9.TMIN
MIMRXWDATA26outputTCELL23:OUT10.TMIN
MIMRXWDATA27outputTCELL23:OUT11.TMIN
MIMRXWDATA28outputTCELL24:OUT10.TMIN
MIMRXWDATA29outputTCELL24:OUT11.TMIN
MIMRXWDATA3outputTCELL2:OUT4.TMIN
MIMRXWDATA30outputTCELL24:OUT12.TMIN
MIMRXWDATA31outputTCELL24:OUT13.TMIN
MIMRXWDATA32outputTCELL25:OUT8.TMIN
MIMRXWDATA33outputTCELL25:OUT9.TMIN
MIMRXWDATA34outputTCELL25:OUT10.TMIN
MIMRXWDATA35outputTCELL25:OUT11.TMIN
MIMRXWDATA36outputTCELL26:OUT9.TMIN
MIMRXWDATA37outputTCELL26:OUT10.TMIN
MIMRXWDATA38outputTCELL26:OUT11.TMIN
MIMRXWDATA39outputTCELL26:OUT12.TMIN
MIMRXWDATA4outputTCELL2:OUT5.TMIN
MIMRXWDATA40outputTCELL27:OUT7.TMIN
MIMRXWDATA41outputTCELL27:OUT8.TMIN
MIMRXWDATA42outputTCELL27:OUT9.TMIN
MIMRXWDATA43outputTCELL27:OUT10.TMIN
MIMRXWDATA44outputTCELL28:OUT7.TMIN
MIMRXWDATA45outputTCELL28:OUT8.TMIN
MIMRXWDATA46outputTCELL28:OUT9.TMIN
MIMRXWDATA47outputTCELL28:OUT10.TMIN
MIMRXWDATA48outputTCELL29:OUT8.TMIN
MIMRXWDATA49outputTCELL29:OUT9.TMIN
MIMRXWDATA5outputTCELL2:OUT6.TMIN
MIMRXWDATA50outputTCELL29:OUT10.TMIN
MIMRXWDATA51outputTCELL29:OUT11.TMIN
MIMRXWDATA52outputTCELL30:OUT8.TMIN
MIMRXWDATA53outputTCELL30:OUT9.TMIN
MIMRXWDATA54outputTCELL30:OUT10.TMIN
MIMRXWDATA55outputTCELL30:OUT11.TMIN
MIMRXWDATA56outputTCELL31:OUT8.TMIN
MIMRXWDATA57outputTCELL31:OUT9.TMIN
MIMRXWDATA58outputTCELL31:OUT10.TMIN
MIMRXWDATA59outputTCELL31:OUT11.TMIN
MIMRXWDATA6outputTCELL2:OUT7.TMIN
MIMRXWDATA60outputTCELL32:OUT8.TMIN
MIMRXWDATA61outputTCELL32:OUT9.TMIN
MIMRXWDATA62outputTCELL32:OUT10.TMIN
MIMRXWDATA63outputTCELL32:OUT11.TMIN
MIMRXWDATA64outputTCELL33:OUT8.TMIN
MIMRXWDATA65outputTCELL33:OUT9.TMIN
MIMRXWDATA66outputTCELL33:OUT10.TMIN
MIMRXWDATA67outputTCELL33:OUT11.TMIN
MIMRXWDATA7outputTCELL1:OUT4.TMIN
MIMRXWDATA8outputTCELL1:OUT5.TMIN
MIMRXWDATA9outputTCELL1:OUT6.TMIN
MIMRXWENoutputTCELL37:OUT8.TMIN
MIMTXRADDR0outputTCELL7:OUT8.TMIN
MIMTXRADDR1outputTCELL7:OUT9.TMIN
MIMTXRADDR10outputTCELL4:OUT6.TMIN
MIMTXRADDR11outputTCELL4:OUT7.TMIN
MIMTXRADDR12outputTCELL4:OUT8.TMIN
MIMTXRADDR2outputTCELL6:OUT5.TMIN
MIMTXRADDR3outputTCELL6:OUT7.TMIN
MIMTXRADDR4outputTCELL6:OUT8.TMIN
MIMTXRADDR5outputTCELL6:OUT9.TMIN
MIMTXRADDR6outputTCELL5:OUT4.TMIN
MIMTXRADDR7outputTCELL5:OUT5.TMIN
MIMTXRADDR8outputTCELL5:OUT6.TMIN
MIMTXRADDR9outputTCELL5:OUT7.TMIN
MIMTXRCEoutputTCELL3:OUT4.TMIN
MIMTXRDATA0inputTCELL14:IMUX.IMUX0.DELAY
MIMTXRDATA1inputTCELL14:IMUX.IMUX2.DELAY
MIMTXRDATA10inputTCELL12:IMUX.IMUX4.DELAY
MIMTXRDATA11inputTCELL11:IMUX.IMUX0.DELAY
MIMTXRDATA12inputTCELL10:IMUX.IMUX0.DELAY
MIMTXRDATA13inputTCELL9:IMUX.IMUX0.DELAY
MIMTXRDATA14inputTCELL9:IMUX.IMUX1.DELAY
MIMTXRDATA15inputTCELL9:IMUX.IMUX2.DELAY
MIMTXRDATA16inputTCELL9:IMUX.IMUX3.DELAY
MIMTXRDATA17inputTCELL8:IMUX.IMUX0.DELAY
MIMTXRDATA18inputTCELL8:IMUX.IMUX1.DELAY
MIMTXRDATA19inputTCELL8:IMUX.IMUX2.DELAY
MIMTXRDATA2inputTCELL14:IMUX.IMUX4.DELAY
MIMTXRDATA20inputTCELL8:IMUX.IMUX3.DELAY
MIMTXRDATA21inputTCELL7:IMUX.IMUX0.DELAY
MIMTXRDATA22inputTCELL7:IMUX.IMUX1.DELAY
MIMTXRDATA23inputTCELL7:IMUX.IMUX2.DELAY
MIMTXRDATA24inputTCELL7:IMUX.IMUX3.DELAY
MIMTXRDATA25inputTCELL6:IMUX.IMUX0.DELAY
MIMTXRDATA26inputTCELL6:IMUX.IMUX1.DELAY
MIMTXRDATA27inputTCELL6:IMUX.IMUX2.DELAY
MIMTXRDATA28inputTCELL6:IMUX.IMUX3.DELAY
MIMTXRDATA29inputTCELL5:IMUX.IMUX0.DELAY
MIMTXRDATA3inputTCELL14:IMUX.IMUX5.DELAY
MIMTXRDATA30inputTCELL5:IMUX.IMUX1.DELAY
MIMTXRDATA31inputTCELL5:IMUX.IMUX2.DELAY
MIMTXRDATA32inputTCELL5:IMUX.IMUX3.DELAY
MIMTXRDATA33inputTCELL4:IMUX.IMUX0.DELAY
MIMTXRDATA34inputTCELL4:IMUX.IMUX2.DELAY
MIMTXRDATA35inputTCELL4:IMUX.IMUX4.DELAY
MIMTXRDATA36inputTCELL4:IMUX.IMUX5.DELAY
MIMTXRDATA37inputTCELL3:IMUX.IMUX0.DELAY
MIMTXRDATA38inputTCELL3:IMUX.IMUX2.DELAY
MIMTXRDATA39inputTCELL3:IMUX.IMUX3.DELAY
MIMTXRDATA4inputTCELL13:IMUX.IMUX0.DELAY
MIMTXRDATA40inputTCELL3:IMUX.IMUX4.DELAY
MIMTXRDATA41inputTCELL2:IMUX.IMUX0.DELAY
MIMTXRDATA42inputTCELL2:IMUX.IMUX2.DELAY
MIMTXRDATA43inputTCELL2:IMUX.IMUX4.DELAY
MIMTXRDATA44inputTCELL1:IMUX.IMUX0.DELAY
MIMTXRDATA45inputTCELL0:IMUX.IMUX0.DELAY
MIMTXRDATA46inputTCELL23:IMUX.IMUX5.DELAY
MIMTXRDATA47inputTCELL23:IMUX.IMUX6.DELAY
MIMTXRDATA48inputTCELL23:IMUX.IMUX7.DELAY
MIMTXRDATA49inputTCELL23:IMUX.IMUX8.DELAY
MIMTXRDATA5inputTCELL13:IMUX.IMUX2.DELAY
MIMTXRDATA50inputTCELL24:IMUX.IMUX6.DELAY
MIMTXRDATA51inputTCELL25:IMUX.IMUX4.DELAY
MIMTXRDATA52inputTCELL25:IMUX.IMUX6.DELAY
MIMTXRDATA53inputTCELL25:IMUX.IMUX7.DELAY
MIMTXRDATA54inputTCELL25:IMUX.IMUX8.DELAY
MIMTXRDATA55inputTCELL26:IMUX.IMUX4.DELAY
MIMTXRDATA56inputTCELL26:IMUX.IMUX5.DELAY
MIMTXRDATA57inputTCELL26:IMUX.IMUX6.DELAY
MIMTXRDATA58inputTCELL26:IMUX.IMUX7.DELAY
MIMTXRDATA59inputTCELL27:IMUX.IMUX4.DELAY
MIMTXRDATA6inputTCELL13:IMUX.IMUX3.DELAY
MIMTXRDATA60inputTCELL27:IMUX.IMUX5.DELAY
MIMTXRDATA61inputTCELL27:IMUX.IMUX6.DELAY
MIMTXRDATA62inputTCELL27:IMUX.IMUX7.DELAY
MIMTXRDATA63inputTCELL28:IMUX.IMUX4.DELAY
MIMTXRDATA64inputTCELL28:IMUX.IMUX5.DELAY
MIMTXRDATA65inputTCELL28:IMUX.IMUX6.DELAY
MIMTXRDATA66inputTCELL28:IMUX.IMUX7.DELAY
MIMTXRDATA67inputTCELL29:IMUX.IMUX4.DELAY
MIMTXRDATA68inputTCELL29:IMUX.IMUX5.DELAY
MIMTXRDATA7inputTCELL13:IMUX.IMUX4.DELAY
MIMTXRDATA8inputTCELL12:IMUX.IMUX0.DELAY
MIMTXRDATA9inputTCELL12:IMUX.IMUX2.DELAY
MIMTXRENoutputTCELL4:OUT9.TMIN
MIMTXWADDR0outputTCELL11:OUT4.TMIN
MIMTXWADDR1outputTCELL11:OUT5.TMIN
MIMTXWADDR10outputTCELL9:OUT6.TMIN
MIMTXWADDR11outputTCELL9:OUT7.TMIN
MIMTXWADDR12outputTCELL8:OUT8.TMIN
MIMTXWADDR2outputTCELL11:OUT6.TMIN
MIMTXWADDR3outputTCELL11:OUT7.TMIN
MIMTXWADDR4outputTCELL10:OUT4.TMIN
MIMTXWADDR5outputTCELL10:OUT5.TMIN
MIMTXWADDR6outputTCELL10:OUT6.TMIN
MIMTXWADDR7outputTCELL10:OUT7.TMIN
MIMTXWADDR8outputTCELL9:OUT4.TMIN
MIMTXWADDR9outputTCELL9:OUT5.TMIN
MIMTXWDATA0outputTCELL22:OUT7.TMIN
MIMTXWDATA1outputTCELL23:OUT4.TMIN
MIMTXWDATA10outputTCELL25:OUT5.TMIN
MIMTXWDATA11outputTCELL25:OUT6.TMIN
MIMTXWDATA12outputTCELL25:OUT7.TMIN
MIMTXWDATA13outputTCELL26:OUT5.TMIN
MIMTXWDATA14outputTCELL26:OUT7.TMIN
MIMTXWDATA15outputTCELL29:OUT4.TMIN
MIMTXWDATA16outputTCELL29:OUT5.TMIN
MIMTXWDATA17outputTCELL29:OUT6.TMIN
MIMTXWDATA18outputTCELL29:OUT7.TMIN
MIMTXWDATA19outputTCELL30:OUT4.TMIN
MIMTXWDATA2outputTCELL23:OUT5.TMIN
MIMTXWDATA20outputTCELL30:OUT5.TMIN
MIMTXWDATA21outputTCELL30:OUT6.TMIN
MIMTXWDATA22outputTCELL30:OUT7.TMIN
MIMTXWDATA23outputTCELL31:OUT4.TMIN
MIMTXWDATA24outputTCELL31:OUT5.TMIN
MIMTXWDATA25outputTCELL31:OUT6.TMIN
MIMTXWDATA26outputTCELL31:OUT7.TMIN
MIMTXWDATA27outputTCELL32:OUT4.TMIN
MIMTXWDATA28outputTCELL32:OUT5.TMIN
MIMTXWDATA29outputTCELL32:OUT6.TMIN
MIMTXWDATA3outputTCELL23:OUT6.TMIN
MIMTXWDATA30outputTCELL32:OUT7.TMIN
MIMTXWDATA31outputTCELL33:OUT4.TMIN
MIMTXWDATA32outputTCELL33:OUT5.TMIN
MIMTXWDATA33outputTCELL33:OUT6.TMIN
MIMTXWDATA34outputTCELL33:OUT7.TMIN
MIMTXWDATA35outputTCELL34:OUT6.TMIN
MIMTXWDATA36outputTCELL34:OUT7.TMIN
MIMTXWDATA37outputTCELL34:OUT8.TMIN
MIMTXWDATA38outputTCELL34:OUT9.TMIN
MIMTXWDATA39outputTCELL35:OUT4.TMIN
MIMTXWDATA4outputTCELL23:OUT7.TMIN
MIMTXWDATA40outputTCELL35:OUT5.TMIN
MIMTXWDATA41outputTCELL35:OUT6.TMIN
MIMTXWDATA42outputTCELL35:OUT7.TMIN
MIMTXWDATA43outputTCELL36:OUT5.TMIN
MIMTXWDATA44outputTCELL36:OUT7.TMIN
MIMTXWDATA45outputTCELL39:OUT4.TMIN
MIMTXWDATA46outputTCELL39:OUT5.TMIN
MIMTXWDATA47outputTCELL39:OUT6.TMIN
MIMTXWDATA48outputTCELL39:OUT7.TMIN
MIMTXWDATA49outputTCELL19:OUT4.TMIN
MIMTXWDATA5outputTCELL24:OUT6.TMIN
MIMTXWDATA50outputTCELL19:OUT5.TMIN
MIMTXWDATA51outputTCELL19:OUT6.TMIN
MIMTXWDATA52outputTCELL19:OUT7.TMIN
MIMTXWDATA53outputTCELL15:OUT4.TMIN
MIMTXWDATA54outputTCELL15:OUT5.TMIN
MIMTXWDATA55outputTCELL15:OUT6.TMIN
MIMTXWDATA56outputTCELL15:OUT7.TMIN
MIMTXWDATA57outputTCELL14:OUT6.TMIN
MIMTXWDATA58outputTCELL14:OUT7.TMIN
MIMTXWDATA59outputTCELL14:OUT8.TMIN
MIMTXWDATA6outputTCELL24:OUT7.TMIN
MIMTXWDATA60outputTCELL14:OUT9.TMIN
MIMTXWDATA61outputTCELL13:OUT4.TMIN
MIMTXWDATA62outputTCELL13:OUT5.TMIN
MIMTXWDATA63outputTCELL13:OUT6.TMIN
MIMTXWDATA64outputTCELL13:OUT7.TMIN
MIMTXWDATA65outputTCELL12:OUT4.TMIN
MIMTXWDATA66outputTCELL12:OUT5.TMIN
MIMTXWDATA67outputTCELL12:OUT6.TMIN
MIMTXWDATA68outputTCELL12:OUT7.TMIN
MIMTXWDATA7outputTCELL24:OUT8.TMIN
MIMTXWDATA8outputTCELL24:OUT9.TMIN
MIMTXWDATA9outputTCELL25:OUT4.TMIN
MIMTXWENoutputTCELL8:OUT9.TMIN
PIPECLKinputTCELL29:IMUX.CLK1
PIPERX0CHANISALIGNEDinputTCELL33:IMUX.IMUX21.DELAY
PIPERX0CHARISK0inputTCELL33:IMUX.IMUX23.DELAY
PIPERX0CHARISK1inputTCELL32:IMUX.IMUX1.DELAY
PIPERX0DATA0inputTCELL30:IMUX.IMUX3.DELAY
PIPERX0DATA1inputTCELL30:IMUX.IMUX5.DELAY
PIPERX0DATA10inputTCELL31:IMUX.IMUX7.DELAY
PIPERX0DATA11inputTCELL31:IMUX.IMUX15.DELAY
PIPERX0DATA12inputTCELL32:IMUX.IMUX5.DELAY
PIPERX0DATA13inputTCELL32:IMUX.IMUX7.DELAY
PIPERX0DATA14inputTCELL32:IMUX.IMUX11.DELAY
PIPERX0DATA15inputTCELL32:IMUX.IMUX9.DELAY
PIPERX0DATA2inputTCELL30:IMUX.IMUX15.DELAY
PIPERX0DATA3inputTCELL30:IMUX.IMUX19.DELAY
PIPERX0DATA4inputTCELL30:IMUX.IMUX1.DELAY
PIPERX0DATA5inputTCELL30:IMUX.IMUX9.DELAY
PIPERX0DATA6inputTCELL31:IMUX.IMUX1.DELAY
PIPERX0DATA7inputTCELL31:IMUX.IMUX9.DELAY
PIPERX0DATA8inputTCELL31:IMUX.IMUX3.DELAY
PIPERX0DATA9inputTCELL31:IMUX.IMUX5.DELAY
PIPERX0ELECIDLEinputTCELL35:IMUX.IMUX21.DELAY
PIPERX0PHYSTATUSinputTCELL34:IMUX.IMUX11.DELAY
PIPERX0POLARITYoutputTCELL31:OUT18.TMIN
PIPERX0STATUS0inputTCELL34:IMUX.IMUX23.DELAY
PIPERX0STATUS1inputTCELL34:IMUX.IMUX19.DELAY
PIPERX0STATUS2inputTCELL34:IMUX.IMUX21.DELAY
PIPERX0VALIDinputTCELL35:IMUX.IMUX19.DELAY
PIPERX1CHANISALIGNEDinputTCELL23:IMUX.IMUX21.DELAY
PIPERX1CHARISK0inputTCELL23:IMUX.IMUX23.DELAY
PIPERX1CHARISK1inputTCELL22:IMUX.IMUX1.DELAY
PIPERX1DATA0inputTCELL20:IMUX.IMUX3.DELAY
PIPERX1DATA1inputTCELL20:IMUX.IMUX5.DELAY
PIPERX1DATA10inputTCELL21:IMUX.IMUX7.DELAY
PIPERX1DATA11inputTCELL21:IMUX.IMUX15.DELAY
PIPERX1DATA12inputTCELL22:IMUX.IMUX5.DELAY
PIPERX1DATA13inputTCELL22:IMUX.IMUX7.DELAY
PIPERX1DATA14inputTCELL22:IMUX.IMUX11.DELAY
PIPERX1DATA15inputTCELL22:IMUX.IMUX9.DELAY
PIPERX1DATA2inputTCELL20:IMUX.IMUX15.DELAY
PIPERX1DATA3inputTCELL20:IMUX.IMUX19.DELAY
PIPERX1DATA4inputTCELL20:IMUX.IMUX1.DELAY
PIPERX1DATA5inputTCELL20:IMUX.IMUX9.DELAY
PIPERX1DATA6inputTCELL21:IMUX.IMUX1.DELAY
PIPERX1DATA7inputTCELL21:IMUX.IMUX9.DELAY
PIPERX1DATA8inputTCELL21:IMUX.IMUX3.DELAY
PIPERX1DATA9inputTCELL21:IMUX.IMUX5.DELAY
PIPERX1ELECIDLEinputTCELL25:IMUX.IMUX21.DELAY
PIPERX1PHYSTATUSinputTCELL24:IMUX.IMUX11.DELAY
PIPERX1POLARITYoutputTCELL21:OUT18.TMIN
PIPERX1STATUS0inputTCELL24:IMUX.IMUX23.DELAY
PIPERX1STATUS1inputTCELL24:IMUX.IMUX19.DELAY
PIPERX1STATUS2inputTCELL24:IMUX.IMUX21.DELAY
PIPERX1VALIDinputTCELL25:IMUX.IMUX19.DELAY
PIPERX2CHANISALIGNEDinputTCELL13:IMUX.IMUX21.DELAY
PIPERX2CHARISK0inputTCELL13:IMUX.IMUX23.DELAY
PIPERX2CHARISK1inputTCELL12:IMUX.IMUX1.DELAY
PIPERX2DATA0inputTCELL10:IMUX.IMUX3.DELAY
PIPERX2DATA1inputTCELL10:IMUX.IMUX5.DELAY
PIPERX2DATA10inputTCELL11:IMUX.IMUX7.DELAY
PIPERX2DATA11inputTCELL11:IMUX.IMUX15.DELAY
PIPERX2DATA12inputTCELL12:IMUX.IMUX5.DELAY
PIPERX2DATA13inputTCELL12:IMUX.IMUX7.DELAY
PIPERX2DATA14inputTCELL12:IMUX.IMUX11.DELAY
PIPERX2DATA15inputTCELL12:IMUX.IMUX9.DELAY
PIPERX2DATA2inputTCELL10:IMUX.IMUX15.DELAY
PIPERX2DATA3inputTCELL10:IMUX.IMUX19.DELAY
PIPERX2DATA4inputTCELL10:IMUX.IMUX1.DELAY
PIPERX2DATA5inputTCELL10:IMUX.IMUX9.DELAY
PIPERX2DATA6inputTCELL11:IMUX.IMUX1.DELAY
PIPERX2DATA7inputTCELL11:IMUX.IMUX9.DELAY
PIPERX2DATA8inputTCELL11:IMUX.IMUX3.DELAY
PIPERX2DATA9inputTCELL11:IMUX.IMUX5.DELAY
PIPERX2ELECIDLEinputTCELL15:IMUX.IMUX21.DELAY
PIPERX2PHYSTATUSinputTCELL14:IMUX.IMUX11.DELAY
PIPERX2POLARITYoutputTCELL11:OUT18.TMIN
PIPERX2STATUS0inputTCELL14:IMUX.IMUX23.DELAY
PIPERX2STATUS1inputTCELL14:IMUX.IMUX19.DELAY
PIPERX2STATUS2inputTCELL14:IMUX.IMUX21.DELAY
PIPERX2VALIDinputTCELL15:IMUX.IMUX19.DELAY
PIPERX3CHANISALIGNEDinputTCELL3:IMUX.IMUX21.DELAY
PIPERX3CHARISK0inputTCELL3:IMUX.IMUX23.DELAY
PIPERX3CHARISK1inputTCELL2:IMUX.IMUX1.DELAY
PIPERX3DATA0inputTCELL0:IMUX.IMUX3.DELAY
PIPERX3DATA1inputTCELL0:IMUX.IMUX5.DELAY
PIPERX3DATA10inputTCELL1:IMUX.IMUX7.DELAY
PIPERX3DATA11inputTCELL1:IMUX.IMUX15.DELAY
PIPERX3DATA12inputTCELL2:IMUX.IMUX5.DELAY
PIPERX3DATA13inputTCELL2:IMUX.IMUX7.DELAY
PIPERX3DATA14inputTCELL2:IMUX.IMUX11.DELAY
PIPERX3DATA15inputTCELL2:IMUX.IMUX9.DELAY
PIPERX3DATA2inputTCELL0:IMUX.IMUX15.DELAY
PIPERX3DATA3inputTCELL0:IMUX.IMUX19.DELAY
PIPERX3DATA4inputTCELL0:IMUX.IMUX1.DELAY
PIPERX3DATA5inputTCELL0:IMUX.IMUX9.DELAY
PIPERX3DATA6inputTCELL1:IMUX.IMUX1.DELAY
PIPERX3DATA7inputTCELL1:IMUX.IMUX9.DELAY
PIPERX3DATA8inputTCELL1:IMUX.IMUX3.DELAY
PIPERX3DATA9inputTCELL1:IMUX.IMUX5.DELAY
PIPERX3ELECIDLEinputTCELL5:IMUX.IMUX21.DELAY
PIPERX3PHYSTATUSinputTCELL4:IMUX.IMUX11.DELAY
PIPERX3POLARITYoutputTCELL1:OUT18.TMIN
PIPERX3STATUS0inputTCELL4:IMUX.IMUX23.DELAY
PIPERX3STATUS1inputTCELL4:IMUX.IMUX19.DELAY
PIPERX3STATUS2inputTCELL4:IMUX.IMUX21.DELAY
PIPERX3VALIDinputTCELL5:IMUX.IMUX19.DELAY
PIPERX4CHANISALIGNEDinputTCELL33:IMUX.IMUX1.DELAY
PIPERX4CHARISK0inputTCELL33:IMUX.IMUX15.DELAY
PIPERX4CHARISK1inputTCELL32:IMUX.IMUX17.DELAY
PIPERX4DATA0inputTCELL30:IMUX.IMUX11.DELAY
PIPERX4DATA1inputTCELL30:IMUX.IMUX13.DELAY
PIPERX4DATA10inputTCELL31:IMUX.IMUX19.DELAY
PIPERX4DATA11inputTCELL31:IMUX.IMUX23.DELAY
PIPERX4DATA12inputTCELL32:IMUX.IMUX13.DELAY
PIPERX4DATA13inputTCELL32:IMUX.IMUX3.DELAY
PIPERX4DATA14inputTCELL32:IMUX.IMUX15.DELAY
PIPERX4DATA15inputTCELL32:IMUX.IMUX21.DELAY
PIPERX4DATA2inputTCELL30:IMUX.IMUX7.DELAY
PIPERX4DATA3inputTCELL30:IMUX.IMUX23.DELAY
PIPERX4DATA4inputTCELL30:IMUX.IMUX17.DELAY
PIPERX4DATA5inputTCELL30:IMUX.IMUX21.DELAY
PIPERX4DATA6inputTCELL31:IMUX.IMUX17.DELAY
PIPERX4DATA7inputTCELL31:IMUX.IMUX21.DELAY
PIPERX4DATA8inputTCELL31:IMUX.IMUX11.DELAY
PIPERX4DATA9inputTCELL31:IMUX.IMUX13.DELAY
PIPERX4ELECIDLEinputTCELL35:IMUX.IMUX5.DELAY
PIPERX4PHYSTATUSinputTCELL34:IMUX.IMUX15.DELAY
PIPERX4POLARITYoutputTCELL31:OUT22.TMIN
PIPERX4STATUS0inputTCELL34:IMUX.IMUX3.DELAY
PIPERX4STATUS1inputTCELL34:IMUX.IMUX7.DELAY
PIPERX4STATUS2inputTCELL34:IMUX.IMUX1.DELAY
PIPERX4VALIDinputTCELL35:IMUX.IMUX11.DELAY
PIPERX5CHANISALIGNEDinputTCELL23:IMUX.IMUX1.DELAY
PIPERX5CHARISK0inputTCELL23:IMUX.IMUX15.DELAY
PIPERX5CHARISK1inputTCELL22:IMUX.IMUX17.DELAY
PIPERX5DATA0inputTCELL20:IMUX.IMUX11.DELAY
PIPERX5DATA1inputTCELL20:IMUX.IMUX13.DELAY
PIPERX5DATA10inputTCELL21:IMUX.IMUX19.DELAY
PIPERX5DATA11inputTCELL21:IMUX.IMUX23.DELAY
PIPERX5DATA12inputTCELL22:IMUX.IMUX13.DELAY
PIPERX5DATA13inputTCELL22:IMUX.IMUX3.DELAY
PIPERX5DATA14inputTCELL22:IMUX.IMUX15.DELAY
PIPERX5DATA15inputTCELL22:IMUX.IMUX21.DELAY
PIPERX5DATA2inputTCELL20:IMUX.IMUX7.DELAY
PIPERX5DATA3inputTCELL20:IMUX.IMUX23.DELAY
PIPERX5DATA4inputTCELL20:IMUX.IMUX17.DELAY
PIPERX5DATA5inputTCELL20:IMUX.IMUX21.DELAY
PIPERX5DATA6inputTCELL21:IMUX.IMUX17.DELAY
PIPERX5DATA7inputTCELL21:IMUX.IMUX21.DELAY
PIPERX5DATA8inputTCELL21:IMUX.IMUX11.DELAY
PIPERX5DATA9inputTCELL21:IMUX.IMUX13.DELAY
PIPERX5ELECIDLEinputTCELL25:IMUX.IMUX5.DELAY
PIPERX5PHYSTATUSinputTCELL24:IMUX.IMUX15.DELAY
PIPERX5POLARITYoutputTCELL21:OUT22.TMIN
PIPERX5STATUS0inputTCELL24:IMUX.IMUX3.DELAY
PIPERX5STATUS1inputTCELL24:IMUX.IMUX7.DELAY
PIPERX5STATUS2inputTCELL24:IMUX.IMUX1.DELAY
PIPERX5VALIDinputTCELL25:IMUX.IMUX11.DELAY
PIPERX6CHANISALIGNEDinputTCELL13:IMUX.IMUX1.DELAY
PIPERX6CHARISK0inputTCELL13:IMUX.IMUX15.DELAY
PIPERX6CHARISK1inputTCELL12:IMUX.IMUX17.DELAY
PIPERX6DATA0inputTCELL10:IMUX.IMUX11.DELAY
PIPERX6DATA1inputTCELL10:IMUX.IMUX13.DELAY
PIPERX6DATA10inputTCELL11:IMUX.IMUX19.DELAY
PIPERX6DATA11inputTCELL11:IMUX.IMUX23.DELAY
PIPERX6DATA12inputTCELL12:IMUX.IMUX13.DELAY
PIPERX6DATA13inputTCELL12:IMUX.IMUX3.DELAY
PIPERX6DATA14inputTCELL12:IMUX.IMUX15.DELAY
PIPERX6DATA15inputTCELL12:IMUX.IMUX21.DELAY
PIPERX6DATA2inputTCELL10:IMUX.IMUX7.DELAY
PIPERX6DATA3inputTCELL10:IMUX.IMUX23.DELAY
PIPERX6DATA4inputTCELL10:IMUX.IMUX17.DELAY
PIPERX6DATA5inputTCELL10:IMUX.IMUX21.DELAY
PIPERX6DATA6inputTCELL11:IMUX.IMUX17.DELAY
PIPERX6DATA7inputTCELL11:IMUX.IMUX21.DELAY
PIPERX6DATA8inputTCELL11:IMUX.IMUX11.DELAY
PIPERX6DATA9inputTCELL11:IMUX.IMUX13.DELAY
PIPERX6ELECIDLEinputTCELL15:IMUX.IMUX5.DELAY
PIPERX6PHYSTATUSinputTCELL14:IMUX.IMUX15.DELAY
PIPERX6POLARITYoutputTCELL11:OUT22.TMIN
PIPERX6STATUS0inputTCELL14:IMUX.IMUX3.DELAY
PIPERX6STATUS1inputTCELL14:IMUX.IMUX7.DELAY
PIPERX6STATUS2inputTCELL14:IMUX.IMUX1.DELAY
PIPERX6VALIDinputTCELL15:IMUX.IMUX11.DELAY
PIPERX7CHANISALIGNEDinputTCELL3:IMUX.IMUX1.DELAY
PIPERX7CHARISK0inputTCELL3:IMUX.IMUX15.DELAY
PIPERX7CHARISK1inputTCELL2:IMUX.IMUX17.DELAY
PIPERX7DATA0inputTCELL0:IMUX.IMUX11.DELAY
PIPERX7DATA1inputTCELL0:IMUX.IMUX13.DELAY
PIPERX7DATA10inputTCELL1:IMUX.IMUX19.DELAY
PIPERX7DATA11inputTCELL1:IMUX.IMUX23.DELAY
PIPERX7DATA12inputTCELL2:IMUX.IMUX13.DELAY
PIPERX7DATA13inputTCELL2:IMUX.IMUX3.DELAY
PIPERX7DATA14inputTCELL2:IMUX.IMUX15.DELAY
PIPERX7DATA15inputTCELL2:IMUX.IMUX21.DELAY
PIPERX7DATA2inputTCELL0:IMUX.IMUX7.DELAY
PIPERX7DATA3inputTCELL0:IMUX.IMUX23.DELAY
PIPERX7DATA4inputTCELL0:IMUX.IMUX17.DELAY
PIPERX7DATA5inputTCELL0:IMUX.IMUX21.DELAY
PIPERX7DATA6inputTCELL1:IMUX.IMUX17.DELAY
PIPERX7DATA7inputTCELL1:IMUX.IMUX21.DELAY
PIPERX7DATA8inputTCELL1:IMUX.IMUX11.DELAY
PIPERX7DATA9inputTCELL1:IMUX.IMUX13.DELAY
PIPERX7ELECIDLEinputTCELL5:IMUX.IMUX5.DELAY
PIPERX7PHYSTATUSinputTCELL4:IMUX.IMUX15.DELAY
PIPERX7POLARITYoutputTCELL1:OUT22.TMIN
PIPERX7STATUS0inputTCELL4:IMUX.IMUX3.DELAY
PIPERX7STATUS1inputTCELL4:IMUX.IMUX7.DELAY
PIPERX7STATUS2inputTCELL4:IMUX.IMUX1.DELAY
PIPERX7VALIDinputTCELL5:IMUX.IMUX11.DELAY
PIPETX0CHARISK0outputTCELL35:OUT18.TMIN
PIPETX0CHARISK1outputTCELL35:OUT23.TMIN
PIPETX0COMPLIANCEoutputTCELL35:OUT16.TMIN
PIPETX0DATA0outputTCELL38:OUT16.TMIN
PIPETX0DATA1outputTCELL38:OUT21.TMIN
PIPETX0DATA10outputTCELL37:OUT21.TMIN
PIPETX0DATA11outputTCELL37:OUT1.TMIN
PIPETX0DATA12outputTCELL36:OUT16.TMIN
PIPETX0DATA13outputTCELL36:OUT6.TMIN
PIPETX0DATA14outputTCELL36:OUT23.TMIN
PIPETX0DATA15outputTCELL36:OUT21.TMIN
PIPETX0DATA2outputTCELL38:OUT23.TMIN
PIPETX0DATA3outputTCELL38:OUT1.TMIN
PIPETX0DATA4outputTCELL38:OUT6.TMIN
PIPETX0DATA5outputTCELL38:OUT18.TMIN
PIPETX0DATA6outputTCELL37:OUT18.TMIN
PIPETX0DATA7outputTCELL37:OUT16.TMIN
PIPETX0DATA8outputTCELL37:OUT6.TMIN
PIPETX0DATA9outputTCELL37:OUT23.TMIN
PIPETX0ELECIDLEoutputTCELL34:OUT1.TMIN
PIPETX0POWERDOWN0outputTCELL34:OUT21.TMIN
PIPETX0POWERDOWN1outputTCELL34:OUT23.TMIN
PIPETX1CHARISK0outputTCELL25:OUT18.TMIN
PIPETX1CHARISK1outputTCELL25:OUT23.TMIN
PIPETX1COMPLIANCEoutputTCELL25:OUT16.TMIN
PIPETX1DATA0outputTCELL28:OUT16.TMIN
PIPETX1DATA1outputTCELL28:OUT21.TMIN
PIPETX1DATA10outputTCELL27:OUT21.TMIN
PIPETX1DATA11outputTCELL27:OUT1.TMIN
PIPETX1DATA12outputTCELL26:OUT16.TMIN
PIPETX1DATA13outputTCELL26:OUT6.TMIN
PIPETX1DATA14outputTCELL26:OUT23.TMIN
PIPETX1DATA15outputTCELL26:OUT21.TMIN
PIPETX1DATA2outputTCELL28:OUT23.TMIN
PIPETX1DATA3outputTCELL28:OUT1.TMIN
PIPETX1DATA4outputTCELL28:OUT6.TMIN
PIPETX1DATA5outputTCELL28:OUT18.TMIN
PIPETX1DATA6outputTCELL27:OUT18.TMIN
PIPETX1DATA7outputTCELL27:OUT16.TMIN
PIPETX1DATA8outputTCELL27:OUT6.TMIN
PIPETX1DATA9outputTCELL27:OUT23.TMIN
PIPETX1ELECIDLEoutputTCELL24:OUT1.TMIN
PIPETX1POWERDOWN0outputTCELL24:OUT21.TMIN
PIPETX1POWERDOWN1outputTCELL24:OUT23.TMIN
PIPETX2CHARISK0outputTCELL15:OUT18.TMIN
PIPETX2CHARISK1outputTCELL15:OUT23.TMIN
PIPETX2COMPLIANCEoutputTCELL15:OUT16.TMIN
PIPETX2DATA0outputTCELL18:OUT16.TMIN
PIPETX2DATA1outputTCELL18:OUT21.TMIN
PIPETX2DATA10outputTCELL17:OUT21.TMIN
PIPETX2DATA11outputTCELL17:OUT1.TMIN
PIPETX2DATA12outputTCELL16:OUT16.TMIN
PIPETX2DATA13outputTCELL16:OUT6.TMIN
PIPETX2DATA14outputTCELL16:OUT23.TMIN
PIPETX2DATA15outputTCELL16:OUT21.TMIN
PIPETX2DATA2outputTCELL18:OUT23.TMIN
PIPETX2DATA3outputTCELL18:OUT1.TMIN
PIPETX2DATA4outputTCELL18:OUT6.TMIN
PIPETX2DATA5outputTCELL18:OUT18.TMIN
PIPETX2DATA6outputTCELL17:OUT18.TMIN
PIPETX2DATA7outputTCELL17:OUT16.TMIN
PIPETX2DATA8outputTCELL17:OUT6.TMIN
PIPETX2DATA9outputTCELL17:OUT23.TMIN
PIPETX2ELECIDLEoutputTCELL14:OUT1.TMIN
PIPETX2POWERDOWN0outputTCELL14:OUT21.TMIN
PIPETX2POWERDOWN1outputTCELL14:OUT23.TMIN
PIPETX3CHARISK0outputTCELL5:OUT18.TMIN
PIPETX3CHARISK1outputTCELL5:OUT23.TMIN
PIPETX3COMPLIANCEoutputTCELL5:OUT16.TMIN
PIPETX3DATA0outputTCELL8:OUT16.TMIN
PIPETX3DATA1outputTCELL8:OUT21.TMIN
PIPETX3DATA10outputTCELL7:OUT21.TMIN
PIPETX3DATA11outputTCELL7:OUT1.TMIN
PIPETX3DATA12outputTCELL6:OUT16.TMIN
PIPETX3DATA13outputTCELL6:OUT6.TMIN
PIPETX3DATA14outputTCELL6:OUT23.TMIN
PIPETX3DATA15outputTCELL6:OUT21.TMIN
PIPETX3DATA2outputTCELL8:OUT23.TMIN
PIPETX3DATA3outputTCELL8:OUT1.TMIN
PIPETX3DATA4outputTCELL8:OUT6.TMIN
PIPETX3DATA5outputTCELL8:OUT18.TMIN
PIPETX3DATA6outputTCELL7:OUT18.TMIN
PIPETX3DATA7outputTCELL7:OUT16.TMIN
PIPETX3DATA8outputTCELL7:OUT6.TMIN
PIPETX3DATA9outputTCELL7:OUT23.TMIN
PIPETX3ELECIDLEoutputTCELL4:OUT1.TMIN
PIPETX3POWERDOWN0outputTCELL4:OUT21.TMIN
PIPETX3POWERDOWN1outputTCELL4:OUT23.TMIN
PIPETX4CHARISK0outputTCELL35:OUT22.TMIN
PIPETX4CHARISK1outputTCELL35:OUT19.TMIN
PIPETX4COMPLIANCEoutputTCELL35:OUT20.TMIN
PIPETX4DATA0outputTCELL38:OUT20.TMIN
PIPETX4DATA1outputTCELL38:OUT17.TMIN
PIPETX4DATA10outputTCELL37:OUT17.TMIN
PIPETX4DATA11outputTCELL37:OUT5.TMIN
PIPETX4DATA12outputTCELL36:OUT20.TMIN
PIPETX4DATA13outputTCELL36:OUT2.TMIN
PIPETX4DATA14outputTCELL36:OUT19.TMIN
PIPETX4DATA15outputTCELL36:OUT17.TMIN
PIPETX4DATA2outputTCELL38:OUT19.TMIN
PIPETX4DATA3outputTCELL38:OUT5.TMIN
PIPETX4DATA4outputTCELL38:OUT2.TMIN
PIPETX4DATA5outputTCELL38:OUT22.TMIN
PIPETX4DATA6outputTCELL37:OUT22.TMIN
PIPETX4DATA7outputTCELL37:OUT20.TMIN
PIPETX4DATA8outputTCELL37:OUT2.TMIN
PIPETX4DATA9outputTCELL37:OUT19.TMIN
PIPETX4ELECIDLEoutputTCELL34:OUT5.TMIN
PIPETX4POWERDOWN0outputTCELL34:OUT17.TMIN
PIPETX4POWERDOWN1outputTCELL34:OUT19.TMIN
PIPETX5CHARISK0outputTCELL25:OUT22.TMIN
PIPETX5CHARISK1outputTCELL25:OUT19.TMIN
PIPETX5COMPLIANCEoutputTCELL25:OUT20.TMIN
PIPETX5DATA0outputTCELL28:OUT20.TMIN
PIPETX5DATA1outputTCELL28:OUT17.TMIN
PIPETX5DATA10outputTCELL27:OUT17.TMIN
PIPETX5DATA11outputTCELL27:OUT5.TMIN
PIPETX5DATA12outputTCELL26:OUT20.TMIN
PIPETX5DATA13outputTCELL26:OUT2.TMIN
PIPETX5DATA14outputTCELL26:OUT19.TMIN
PIPETX5DATA15outputTCELL26:OUT17.TMIN
PIPETX5DATA2outputTCELL28:OUT19.TMIN
PIPETX5DATA3outputTCELL28:OUT5.TMIN
PIPETX5DATA4outputTCELL28:OUT2.TMIN
PIPETX5DATA5outputTCELL28:OUT22.TMIN
PIPETX5DATA6outputTCELL27:OUT22.TMIN
PIPETX5DATA7outputTCELL27:OUT20.TMIN
PIPETX5DATA8outputTCELL27:OUT2.TMIN
PIPETX5DATA9outputTCELL27:OUT19.TMIN
PIPETX5ELECIDLEoutputTCELL24:OUT5.TMIN
PIPETX5POWERDOWN0outputTCELL24:OUT17.TMIN
PIPETX5POWERDOWN1outputTCELL24:OUT19.TMIN
PIPETX6CHARISK0outputTCELL15:OUT22.TMIN
PIPETX6CHARISK1outputTCELL15:OUT19.TMIN
PIPETX6COMPLIANCEoutputTCELL15:OUT20.TMIN
PIPETX6DATA0outputTCELL18:OUT20.TMIN
PIPETX6DATA1outputTCELL18:OUT17.TMIN
PIPETX6DATA10outputTCELL17:OUT17.TMIN
PIPETX6DATA11outputTCELL17:OUT5.TMIN
PIPETX6DATA12outputTCELL16:OUT20.TMIN
PIPETX6DATA13outputTCELL16:OUT2.TMIN
PIPETX6DATA14outputTCELL16:OUT19.TMIN
PIPETX6DATA15outputTCELL16:OUT17.TMIN
PIPETX6DATA2outputTCELL18:OUT19.TMIN
PIPETX6DATA3outputTCELL18:OUT5.TMIN
PIPETX6DATA4outputTCELL18:OUT2.TMIN
PIPETX6DATA5outputTCELL18:OUT22.TMIN
PIPETX6DATA6outputTCELL17:OUT22.TMIN
PIPETX6DATA7outputTCELL17:OUT20.TMIN
PIPETX6DATA8outputTCELL17:OUT2.TMIN
PIPETX6DATA9outputTCELL17:OUT19.TMIN
PIPETX6ELECIDLEoutputTCELL14:OUT5.TMIN
PIPETX6POWERDOWN0outputTCELL14:OUT17.TMIN
PIPETX6POWERDOWN1outputTCELL14:OUT19.TMIN
PIPETX7CHARISK0outputTCELL5:OUT22.TMIN
PIPETX7CHARISK1outputTCELL5:OUT19.TMIN
PIPETX7COMPLIANCEoutputTCELL5:OUT20.TMIN
PIPETX7DATA0outputTCELL8:OUT20.TMIN
PIPETX7DATA1outputTCELL8:OUT17.TMIN
PIPETX7DATA10outputTCELL7:OUT17.TMIN
PIPETX7DATA11outputTCELL7:OUT5.TMIN
PIPETX7DATA12outputTCELL6:OUT20.TMIN
PIPETX7DATA13outputTCELL6:OUT2.TMIN
PIPETX7DATA14outputTCELL6:OUT19.TMIN
PIPETX7DATA15outputTCELL6:OUT17.TMIN
PIPETX7DATA2outputTCELL8:OUT19.TMIN
PIPETX7DATA3outputTCELL8:OUT5.TMIN
PIPETX7DATA4outputTCELL8:OUT2.TMIN
PIPETX7DATA5outputTCELL8:OUT22.TMIN
PIPETX7DATA6outputTCELL7:OUT22.TMIN
PIPETX7DATA7outputTCELL7:OUT20.TMIN
PIPETX7DATA8outputTCELL7:OUT2.TMIN
PIPETX7DATA9outputTCELL7:OUT19.TMIN
PIPETX7ELECIDLEoutputTCELL4:OUT5.TMIN
PIPETX7POWERDOWN0outputTCELL4:OUT17.TMIN
PIPETX7POWERDOWN1outputTCELL4:OUT19.TMIN
PIPETXDEEMPHoutputTCELL13:OUT16.TMIN
PIPETXMARGIN0outputTCELL0:OUT18.TMIN
PIPETXMARGIN1outputTCELL0:OUT16.TMIN
PIPETXMARGIN2outputTCELL0:OUT6.TMIN
PIPETXRATEoutputTCELL16:OUT18.TMIN
PIPETXRCVRDEToutputTCELL14:OUT15.TMIN
PIPETXRESEToutputTCELL16:OUT9.TMIN
PL2DIRECTEDLSTATE0inputTCELL28:IMUX.IMUX8.DELAY
PL2DIRECTEDLSTATE1inputTCELL28:IMUX.IMUX9.DELAY
PL2DIRECTEDLSTATE2inputTCELL28:IMUX.IMUX10.DELAY
PL2DIRECTEDLSTATE3inputTCELL28:IMUX.IMUX11.DELAY
PL2DIRECTEDLSTATE4inputTCELL29:IMUX.IMUX8.DELAY
PL2LINKUPNoutputTCELL0:OUT9.TMIN
PL2RECEIVERERRNoutputTCELL0:OUT10.TMIN
PL2RECOVERYNoutputTCELL2:OUT10.TMIN
PL2RXELECIDLEoutputTCELL2:OUT11.TMIN
PL2SUSPENDOKoutputTCELL2:OUT9.TMIN
PLDBGMODE0inputTCELL37:IMUX.IMUX21.DELAY
PLDBGMODE1inputTCELL38:IMUX.IMUX21.DELAY
PLDBGMODE2inputTCELL39:IMUX.IMUX21.DELAY
PLDBGVEC0outputTCELL36:OUT22.TMIN
PLDBGVEC1outputTCELL37:OUT15.TMIN
PLDBGVEC10outputTCELL16:OUT12.TMIN
PLDBGVEC11outputTCELL16:OUT13.TMIN
PLDBGVEC2outputTCELL38:OUT15.TMIN
PLDBGVEC3outputTCELL39:OUT19.TMIN
PLDBGVEC4outputTCELL39:OUT20.TMIN
PLDBGVEC5outputTCELL19:OUT22.TMIN
PLDBGVEC6outputTCELL18:OUT12.TMIN
PLDBGVEC7outputTCELL18:OUT13.TMIN
PLDBGVEC8outputTCELL17:OUT11.TMIN
PLDBGVEC9outputTCELL17:OUT12.TMIN
PLDIRECTEDLINKAUTONinputTCELL23:IMUX.IMUX0.DELAY
PLDIRECTEDLINKCHANGE0inputTCELL20:IMUX.IMUX0.DELAY
PLDIRECTEDLINKCHANGE1inputTCELL21:IMUX.IMUX0.DELAY
PLDIRECTEDLINKSPEEDinputTCELL22:IMUX.IMUX4.DELAY
PLDIRECTEDLINKWIDTH0inputTCELL22:IMUX.IMUX0.DELAY
PLDIRECTEDLINKWIDTH1inputTCELL22:IMUX.IMUX2.DELAY
PLDOWNSTREAMDEEMPHSOURCEinputTCELL23:IMUX.IMUX3.DELAY
PLINITIALLINKWIDTH0outputTCELL22:OUT0.TMIN
PLINITIALLINKWIDTH1outputTCELL22:OUT1.TMIN
PLINITIALLINKWIDTH2outputTCELL22:OUT2.TMIN
PLLANEREVERSALMODE0outputTCELL20:OUT9.TMIN
PLLANEREVERSALMODE1outputTCELL20:OUT10.TMIN
PLLINKGEN2CAPoutputTCELL21:OUT2.TMIN
PLLINKPARTNERGEN2SUPPORTEDoutputTCELL21:OUT3.TMIN
PLLINKUPCFGCAPoutputTCELL21:OUT1.TMIN
PLLTSSMSTATE0outputTCELL20:OUT3.TMIN
PLLTSSMSTATE1outputTCELL20:OUT4.TMIN
PLLTSSMSTATE2outputTCELL20:OUT5.TMIN
PLLTSSMSTATE3outputTCELL20:OUT6.TMIN
PLLTSSMSTATE4outputTCELL20:OUT7.TMIN
PLLTSSMSTATE5outputTCELL20:OUT8.TMIN
PLPHYLNKUPNoutputTCELL20:OUT11.TMIN
PLRECEIVEDHOTRSToutputTCELL22:OUT13.TMIN
PLRSTNinputTCELL23:IMUX.CTRL0
PLRXPMSTATE0outputTCELL20:OUT15.TMIN
PLRXPMSTATE1outputTCELL21:OUT0.TMIN
PLSELLNKRATEoutputTCELL20:OUT0.TMIN
PLSELLNKWIDTH0outputTCELL20:OUT1.TMIN
PLSELLNKWIDTH1outputTCELL20:OUT2.TMIN
PLTRANSMITHOTRSTinputTCELL14:IMUX.IMUX13.DELAY
PLTXPMSTATE0outputTCELL20:OUT12.TMIN
PLTXPMSTATE1outputTCELL20:OUT13.TMIN
PLTXPMSTATE2outputTCELL20:OUT14.TMIN
PLUPSTREAMPREFERDEEMPHinputTCELL23:IMUX.IMUX2.DELAY
PMVDIVIDE0inputTCELL15:IMUX.IMUX9.DELAY
PMVDIVIDE1inputTCELL14:IMUX.IMUX12.DELAY
PMVENABLENinputTCELL19:IMUX.IMUX8.DELAY
PMVOUToutputTCELL21:OUT15.TMIN
PMVSELECT0inputTCELL18:IMUX.IMUX8.DELAY
PMVSELECT1inputTCELL17:IMUX.IMUX8.DELAY
PMVSELECT2inputTCELL16:IMUX.IMUX8.DELAY
RECEIVEDFUNCLVLRSTNoutputTCELL22:OUT14.TMIN
SCANENABLENinputTCELL31:IMUX.IMUX10.DELAY
SCANIN0inputTCELL32:IMUX.IMUX14.DELAY
SCANIN1inputTCELL33:IMUX.IMUX9.DELAY
SCANIN2inputTCELL34:IMUX.IMUX12.DELAY
SCANIN3inputTCELL35:IMUX.IMUX9.DELAY
SCANIN4inputTCELL36:IMUX.IMUX8.DELAY
SCANIN5inputTCELL37:IMUX.IMUX8.DELAY
SCANIN6inputTCELL38:IMUX.IMUX8.DELAY
SCANIN7inputTCELL39:IMUX.IMUX8.DELAY
SCANMODENinputTCELL30:IMUX.IMUX10.DELAY
SYSRSTNinputTCELL20:IMUX.CTRL0
TL2ASPMSUSPENDCREDITCHECKNinputTCELL29:IMUX.IMUX11.DELAY
TL2ASPMSUSPENDCREDITCHECKOKNoutputTCELL1:OUT11.TMIN
TL2ASPMSUSPENDREQNoutputTCELL1:OUT10.TMIN
TL2PPMSUSPENDOKNoutputTCELL1:OUT9.TMIN
TL2PPMSUSPENDREQNinputTCELL29:IMUX.IMUX10.DELAY
TLRSTNinputTCELL22:IMUX.CTRL0
TRNFCCPLD0outputTCELL0:OUT3.TMIN
TRNFCCPLD1outputTCELL20:OUT16.TMIN
TRNFCCPLD10outputTCELL22:OUT5.TMIN
TRNFCCPLD11outputTCELL22:OUT6.TMIN
TRNFCCPLD2outputTCELL20:OUT17.TMIN
TRNFCCPLD3outputTCELL20:OUT18.TMIN
TRNFCCPLD4outputTCELL20:OUT19.TMIN
TRNFCCPLD5outputTCELL21:OUT4.TMIN
TRNFCCPLD6outputTCELL21:OUT5.TMIN
TRNFCCPLD7outputTCELL21:OUT6.TMIN
TRNFCCPLD8outputTCELL21:OUT7.TMIN
TRNFCCPLD9outputTCELL22:OUT4.TMIN
TRNFCCPLH0outputTCELL2:OUT3.TMIN
TRNFCCPLH1outputTCELL1:OUT0.TMIN
TRNFCCPLH2outputTCELL1:OUT1.TMIN
TRNFCCPLH3outputTCELL1:OUT2.TMIN
TRNFCCPLH4outputTCELL1:OUT3.TMIN
TRNFCCPLH5outputTCELL0:OUT0.TMIN
TRNFCCPLH6outputTCELL0:OUT1.TMIN
TRNFCCPLH7outputTCELL0:OUT2.TMIN
TRNFCNPD0outputTCELL5:OUT3.TMIN
TRNFCNPD1outputTCELL4:OUT0.TMIN
TRNFCNPD10outputTCELL2:OUT1.TMIN
TRNFCNPD11outputTCELL2:OUT2.TMIN
TRNFCNPD2outputTCELL4:OUT2.TMIN
TRNFCNPD3outputTCELL4:OUT3.TMIN
TRNFCNPD4outputTCELL4:OUT4.TMIN
TRNFCNPD5outputTCELL3:OUT0.TMIN
TRNFCNPD6outputTCELL3:OUT1.TMIN
TRNFCNPD7outputTCELL3:OUT2.TMIN
TRNFCNPD8outputTCELL3:OUT3.TMIN
TRNFCNPD9outputTCELL2:OUT0.TMIN
TRNFCNPH0outputTCELL7:OUT7.TMIN
TRNFCNPH1outputTCELL6:OUT0.TMIN
TRNFCNPH2outputTCELL6:OUT1.TMIN
TRNFCNPH3outputTCELL6:OUT3.TMIN
TRNFCNPH4outputTCELL6:OUT4.TMIN
TRNFCNPH5outputTCELL5:OUT0.TMIN
TRNFCNPH6outputTCELL5:OUT1.TMIN
TRNFCNPH7outputTCELL5:OUT2.TMIN
TRNFCPD0outputTCELL10:OUT3.TMIN
TRNFCPD1outputTCELL9:OUT0.TMIN
TRNFCPD10outputTCELL7:OUT3.TMIN
TRNFCPD11outputTCELL7:OUT4.TMIN
TRNFCPD2outputTCELL9:OUT1.TMIN
TRNFCPD3outputTCELL9:OUT2.TMIN
TRNFCPD4outputTCELL9:OUT3.TMIN
TRNFCPD5outputTCELL8:OUT0.TMIN
TRNFCPD6outputTCELL8:OUT3.TMIN
TRNFCPD7outputTCELL8:OUT4.TMIN
TRNFCPD8outputTCELL8:OUT7.TMIN
TRNFCPD9outputTCELL7:OUT0.TMIN
TRNFCPH0outputTCELL12:OUT3.TMIN
TRNFCPH1outputTCELL11:OUT0.TMIN
TRNFCPH2outputTCELL11:OUT1.TMIN
TRNFCPH3outputTCELL11:OUT2.TMIN
TRNFCPH4outputTCELL11:OUT3.TMIN
TRNFCPH5outputTCELL10:OUT0.TMIN
TRNFCPH6outputTCELL10:OUT1.TMIN
TRNFCPH7outputTCELL10:OUT2.TMIN
TRNFCSEL0inputTCELL15:IMUX.IMUX1.DELAY
TRNFCSEL1inputTCELL15:IMUX.IMUX2.DELAY
TRNFCSEL2inputTCELL15:IMUX.IMUX3.DELAY
TRNLNKUPNoutputTCELL12:OUT2.TMIN
TRNRBARHITN0outputTCELL14:OUT4.TMIN
TRNRBARHITN1outputTCELL13:OUT0.TMIN
TRNRBARHITN2outputTCELL13:OUT1.TMIN
TRNRBARHITN3outputTCELL13:OUT2.TMIN
TRNRBARHITN4outputTCELL13:OUT3.TMIN
TRNRBARHITN5outputTCELL12:OUT0.TMIN
TRNRBARHITN6outputTCELL12:OUT1.TMIN
TRNRD0outputTCELL25:OUT0.TMIN
TRNRD1outputTCELL25:OUT1.TMIN
TRNRD10outputTCELL28:OUT0.TMIN
TRNRD11outputTCELL28:OUT3.TMIN
TRNRD12outputTCELL29:OUT0.TMIN
TRNRD13outputTCELL29:OUT1.TMIN
TRNRD14outputTCELL29:OUT2.TMIN
TRNRD15outputTCELL29:OUT3.TMIN
TRNRD16outputTCELL30:OUT0.TMIN
TRNRD17outputTCELL30:OUT1.TMIN
TRNRD18outputTCELL30:OUT2.TMIN
TRNRD19outputTCELL30:OUT3.TMIN
TRNRD2outputTCELL25:OUT2.TMIN
TRNRD20outputTCELL31:OUT0.TMIN
TRNRD21outputTCELL31:OUT1.TMIN
TRNRD22outputTCELL31:OUT2.TMIN
TRNRD23outputTCELL31:OUT3.TMIN
TRNRD24outputTCELL32:OUT0.TMIN
TRNRD25outputTCELL32:OUT1.TMIN
TRNRD26outputTCELL32:OUT2.TMIN
TRNRD27outputTCELL32:OUT3.TMIN
TRNRD28outputTCELL33:OUT0.TMIN
TRNRD29outputTCELL33:OUT1.TMIN
TRNRD3outputTCELL25:OUT3.TMIN
TRNRD30outputTCELL33:OUT2.TMIN
TRNRD31outputTCELL33:OUT3.TMIN
TRNRD32outputTCELL34:OUT0.TMIN
TRNRD33outputTCELL34:OUT2.TMIN
TRNRD34outputTCELL34:OUT3.TMIN
TRNRD35outputTCELL34:OUT4.TMIN
TRNRD36outputTCELL35:OUT0.TMIN
TRNRD37outputTCELL35:OUT1.TMIN
TRNRD38outputTCELL35:OUT2.TMIN
TRNRD39outputTCELL35:OUT3.TMIN
TRNRD4outputTCELL26:OUT0.TMIN
TRNRD40outputTCELL36:OUT0.TMIN
TRNRD41outputTCELL36:OUT1.TMIN
TRNRD42outputTCELL36:OUT3.TMIN
TRNRD43outputTCELL36:OUT4.TMIN
TRNRD44outputTCELL37:OUT0.TMIN
TRNRD45outputTCELL37:OUT3.TMIN
TRNRD46outputTCELL38:OUT0.TMIN
TRNRD47outputTCELL38:OUT3.TMIN
TRNRD48outputTCELL39:OUT0.TMIN
TRNRD49outputTCELL39:OUT1.TMIN
TRNRD5outputTCELL26:OUT1.TMIN
TRNRD50outputTCELL39:OUT2.TMIN
TRNRD51outputTCELL39:OUT3.TMIN
TRNRD52outputTCELL19:OUT0.TMIN
TRNRD53outputTCELL19:OUT1.TMIN
TRNRD54outputTCELL19:OUT2.TMIN
TRNRD55outputTCELL19:OUT3.TMIN
TRNRD56outputTCELL18:OUT0.TMIN
TRNRD57outputTCELL18:OUT3.TMIN
TRNRD58outputTCELL17:OUT0.TMIN
TRNRD59outputTCELL17:OUT3.TMIN
TRNRD6outputTCELL26:OUT3.TMIN
TRNRD60outputTCELL16:OUT0.TMIN
TRNRD61outputTCELL16:OUT1.TMIN
TRNRD62outputTCELL16:OUT3.TMIN
TRNRD63outputTCELL16:OUT4.TMIN
TRNRD7outputTCELL26:OUT4.TMIN
TRNRD8outputTCELL27:OUT0.TMIN
TRNRD9outputTCELL27:OUT3.TMIN
TRNRDLLPDATA0outputTCELL13:OUT8.TMIN
TRNRDLLPDATA1outputTCELL13:OUT9.TMIN
TRNRDLLPDATA10outputTCELL11:OUT10.TMIN
TRNRDLLPDATA11outputTCELL11:OUT11.TMIN
TRNRDLLPDATA12outputTCELL10:OUT8.TMIN
TRNRDLLPDATA13outputTCELL10:OUT9.TMIN
TRNRDLLPDATA14outputTCELL10:OUT10.TMIN
TRNRDLLPDATA15outputTCELL10:OUT11.TMIN
TRNRDLLPDATA16outputTCELL9:OUT8.TMIN
TRNRDLLPDATA17outputTCELL9:OUT9.TMIN
TRNRDLLPDATA18outputTCELL9:OUT10.TMIN
TRNRDLLPDATA19outputTCELL9:OUT11.TMIN
TRNRDLLPDATA2outputTCELL13:OUT10.TMIN
TRNRDLLPDATA20outputTCELL6:OUT10.TMIN
TRNRDLLPDATA21outputTCELL6:OUT11.TMIN
TRNRDLLPDATA22outputTCELL5:OUT8.TMIN
TRNRDLLPDATA23outputTCELL5:OUT9.TMIN
TRNRDLLPDATA24outputTCELL5:OUT10.TMIN
TRNRDLLPDATA25outputTCELL5:OUT11.TMIN
TRNRDLLPDATA26outputTCELL4:OUT10.TMIN
TRNRDLLPDATA27outputTCELL4:OUT11.TMIN
TRNRDLLPDATA28outputTCELL4:OUT12.TMIN
TRNRDLLPDATA29outputTCELL4:OUT13.TMIN
TRNRDLLPDATA3outputTCELL13:OUT11.TMIN
TRNRDLLPDATA30outputTCELL3:OUT8.TMIN
TRNRDLLPDATA31outputTCELL3:OUT9.TMIN
TRNRDLLPDATA4outputTCELL12:OUT8.TMIN
TRNRDLLPDATA5outputTCELL12:OUT9.TMIN
TRNRDLLPDATA6outputTCELL12:OUT10.TMIN
TRNRDLLPDATA7outputTCELL12:OUT11.TMIN
TRNRDLLPDATA8outputTCELL11:OUT8.TMIN
TRNRDLLPDATA9outputTCELL11:OUT9.TMIN
TRNRDLLPSRCRDYNoutputTCELL3:OUT10.TMIN
TRNRDSTRDYNinputTCELL16:IMUX.IMUX3.DELAY
TRNRECRCERRNoutputTCELL14:OUT2.TMIN
TRNREOFNoutputTCELL15:OUT2.TMIN
TRNRERRFWDNoutputTCELL14:OUT3.TMIN
TRNRNPOKNinputTCELL15:IMUX.IMUX0.DELAY
TRNRREMNoutputTCELL15:OUT0.TMIN
TRNRSOFNoutputTCELL15:OUT1.TMIN
TRNRSRCDSCNoutputTCELL14:OUT0.TMIN
TRNRSRCRDYNoutputTCELL15:OUT3.TMIN
TRNTBUFAV0outputTCELL23:OUT1.TMIN
TRNTBUFAV1outputTCELL23:OUT2.TMIN
TRNTBUFAV2outputTCELL23:OUT3.TMIN
TRNTBUFAV3outputTCELL24:OUT0.TMIN
TRNTBUFAV4outputTCELL24:OUT2.TMIN
TRNTBUFAV5outputTCELL24:OUT3.TMIN
TRNTCFGGNTNinputTCELL16:IMUX.IMUX2.DELAY
TRNTCFGREQNoutputTCELL24:OUT4.TMIN
TRNTD0inputTCELL23:IMUX.IMUX4.DELAY
TRNTD1inputTCELL24:IMUX.IMUX0.DELAY
TRNTD10inputTCELL26:IMUX.IMUX1.DELAY
TRNTD11inputTCELL26:IMUX.IMUX2.DELAY
TRNTD12inputTCELL26:IMUX.IMUX3.DELAY
TRNTD13inputTCELL27:IMUX.IMUX0.DELAY
TRNTD14inputTCELL27:IMUX.IMUX1.DELAY
TRNTD15inputTCELL27:IMUX.IMUX2.DELAY
TRNTD16inputTCELL27:IMUX.IMUX3.DELAY
TRNTD17inputTCELL28:IMUX.IMUX0.DELAY
TRNTD18inputTCELL28:IMUX.IMUX1.DELAY
TRNTD19inputTCELL28:IMUX.IMUX2.DELAY
TRNTD2inputTCELL24:IMUX.IMUX2.DELAY
TRNTD20inputTCELL28:IMUX.IMUX3.DELAY
TRNTD21inputTCELL29:IMUX.IMUX0.DELAY
TRNTD22inputTCELL29:IMUX.IMUX1.DELAY
TRNTD23inputTCELL29:IMUX.IMUX2.DELAY
TRNTD24inputTCELL29:IMUX.IMUX3.DELAY
TRNTD25inputTCELL30:IMUX.IMUX0.DELAY
TRNTD26inputTCELL31:IMUX.IMUX0.DELAY
TRNTD27inputTCELL32:IMUX.IMUX0.DELAY
TRNTD28inputTCELL32:IMUX.IMUX2.DELAY
TRNTD29inputTCELL32:IMUX.IMUX4.DELAY
TRNTD3inputTCELL24:IMUX.IMUX4.DELAY
TRNTD30inputTCELL33:IMUX.IMUX0.DELAY
TRNTD31inputTCELL33:IMUX.IMUX2.DELAY
TRNTD32inputTCELL33:IMUX.IMUX3.DELAY
TRNTD33inputTCELL33:IMUX.IMUX4.DELAY
TRNTD34inputTCELL34:IMUX.IMUX0.DELAY
TRNTD35inputTCELL34:IMUX.IMUX2.DELAY
TRNTD36inputTCELL34:IMUX.IMUX4.DELAY
TRNTD37inputTCELL34:IMUX.IMUX5.DELAY
TRNTD38inputTCELL35:IMUX.IMUX0.DELAY
TRNTD39inputTCELL35:IMUX.IMUX1.DELAY
TRNTD4inputTCELL24:IMUX.IMUX5.DELAY
TRNTD40inputTCELL35:IMUX.IMUX2.DELAY
TRNTD41inputTCELL35:IMUX.IMUX3.DELAY
TRNTD42inputTCELL36:IMUX.IMUX0.DELAY
TRNTD43inputTCELL36:IMUX.IMUX1.DELAY
TRNTD44inputTCELL36:IMUX.IMUX2.DELAY
TRNTD45inputTCELL36:IMUX.IMUX3.DELAY
TRNTD46inputTCELL37:IMUX.IMUX0.DELAY
TRNTD47inputTCELL37:IMUX.IMUX1.DELAY
TRNTD48inputTCELL37:IMUX.IMUX2.DELAY
TRNTD49inputTCELL37:IMUX.IMUX3.DELAY
TRNTD5inputTCELL25:IMUX.IMUX0.DELAY
TRNTD50inputTCELL38:IMUX.IMUX0.DELAY
TRNTD51inputTCELL38:IMUX.IMUX1.DELAY
TRNTD52inputTCELL38:IMUX.IMUX2.DELAY
TRNTD53inputTCELL38:IMUX.IMUX3.DELAY
TRNTD54inputTCELL39:IMUX.IMUX0.DELAY
TRNTD55inputTCELL39:IMUX.IMUX1.DELAY
TRNTD56inputTCELL39:IMUX.IMUX2.DELAY
TRNTD57inputTCELL39:IMUX.IMUX3.DELAY
TRNTD58inputTCELL19:IMUX.IMUX0.DELAY
TRNTD59inputTCELL19:IMUX.IMUX1.DELAY
TRNTD6inputTCELL25:IMUX.IMUX1.DELAY
TRNTD60inputTCELL19:IMUX.IMUX2.DELAY
TRNTD61inputTCELL19:IMUX.IMUX3.DELAY
TRNTD62inputTCELL18:IMUX.IMUX0.DELAY
TRNTD63inputTCELL18:IMUX.IMUX1.DELAY
TRNTD7inputTCELL25:IMUX.IMUX2.DELAY
TRNTD8inputTCELL25:IMUX.IMUX3.DELAY
TRNTD9inputTCELL26:IMUX.IMUX0.DELAY
TRNTDLLPDATA0inputTCELL13:IMUX.IMUX7.DELAY
TRNTDLLPDATA1inputTCELL13:IMUX.IMUX8.DELAY
TRNTDLLPDATA10inputTCELL7:IMUX.IMUX4.DELAY
TRNTDLLPDATA11inputTCELL7:IMUX.IMUX5.DELAY
TRNTDLLPDATA12inputTCELL7:IMUX.IMUX6.DELAY
TRNTDLLPDATA13inputTCELL7:IMUX.IMUX7.DELAY
TRNTDLLPDATA14inputTCELL6:IMUX.IMUX4.DELAY
TRNTDLLPDATA15inputTCELL6:IMUX.IMUX5.DELAY
TRNTDLLPDATA16inputTCELL6:IMUX.IMUX6.DELAY
TRNTDLLPDATA17inputTCELL6:IMUX.IMUX7.DELAY
TRNTDLLPDATA18inputTCELL5:IMUX.IMUX4.DELAY
TRNTDLLPDATA19inputTCELL5:IMUX.IMUX6.DELAY
TRNTDLLPDATA2inputTCELL9:IMUX.IMUX4.DELAY
TRNTDLLPDATA20inputTCELL5:IMUX.IMUX7.DELAY
TRNTDLLPDATA21inputTCELL5:IMUX.IMUX8.DELAY
TRNTDLLPDATA22inputTCELL4:IMUX.IMUX6.DELAY
TRNTDLLPDATA23inputTCELL3:IMUX.IMUX5.DELAY
TRNTDLLPDATA24inputTCELL3:IMUX.IMUX6.DELAY
TRNTDLLPDATA25inputTCELL3:IMUX.IMUX7.DELAY
TRNTDLLPDATA26inputTCELL3:IMUX.IMUX8.DELAY
TRNTDLLPDATA27inputTCELL23:IMUX.IMUX9.DELAY
TRNTDLLPDATA28inputTCELL25:IMUX.IMUX9.DELAY
TRNTDLLPDATA29inputTCELL26:IMUX.IMUX8.DELAY
TRNTDLLPDATA3inputTCELL9:IMUX.IMUX5.DELAY
TRNTDLLPDATA30inputTCELL26:IMUX.IMUX9.DELAY
TRNTDLLPDATA31inputTCELL26:IMUX.IMUX10.DELAY
TRNTDLLPDATA4inputTCELL9:IMUX.IMUX6.DELAY
TRNTDLLPDATA5inputTCELL9:IMUX.IMUX7.DELAY
TRNTDLLPDATA6inputTCELL8:IMUX.IMUX4.DELAY
TRNTDLLPDATA7inputTCELL8:IMUX.IMUX5.DELAY
TRNTDLLPDATA8inputTCELL8:IMUX.IMUX6.DELAY
TRNTDLLPDATA9inputTCELL8:IMUX.IMUX7.DELAY
TRNTDLLPDSTRDYNoutputTCELL14:OUT10.TMIN
TRNTDLLPSRCRDYNinputTCELL26:IMUX.IMUX11.DELAY
TRNTDSTRDYNoutputTCELL22:OUT3.TMIN
TRNTECRCGENNinputTCELL16:IMUX.IMUX0.DELAY
TRNTEOFNinputTCELL17:IMUX.IMUX0.DELAY
TRNTERRDROPNoutputTCELL23:OUT0.TMIN
TRNTERRFWDNinputTCELL17:IMUX.IMUX3.DELAY
TRNTREMNinputTCELL18:IMUX.IMUX2.DELAY
TRNTSOFNinputTCELL18:IMUX.IMUX3.DELAY
TRNTSRCDSCNinputTCELL17:IMUX.IMUX2.DELAY
TRNTSRCRDYNinputTCELL17:IMUX.IMUX1.DELAY
TRNTSTRNinputTCELL16:IMUX.IMUX1.DELAY
USERCLKinputTCELL29:IMUX.CLK0
USERCLKPREBUFinputTCELL20:IMUX.CLK0
USERRSTNoutputTCELL22:OUT12.TMIN
XILUNCONNOUT0outputTCELL15:OUT15.TMIN
XILUNCONNOUT1outputTCELL14:OUT14.TMIN
XILUNCONNOUT2outputTCELL14:OUT16.TMIN
XILUNCONNOUT3outputTCELL13:OUT19.TMIN

Bel wires

virtex6 PCIE bel wires
WirePins
TCELL0:IMUX.IMUX0.DELAYPCIE.MIMTXRDATA45
TCELL0:IMUX.IMUX1.DELAYPCIE.PIPERX3DATA4
TCELL0:IMUX.IMUX2.DELAYPCIE.CFGERRAERHEADERLOG33
TCELL0:IMUX.IMUX3.DELAYPCIE.PIPERX3DATA0
TCELL0:IMUX.IMUX4.DELAYPCIE.CFGERRAERHEADERLOG34
TCELL0:IMUX.IMUX5.DELAYPCIE.PIPERX3DATA1
TCELL0:IMUX.IMUX6.DELAYPCIE.CFGERRAERHEADERLOG35
TCELL0:IMUX.IMUX7.DELAYPCIE.PIPERX7DATA2
TCELL0:IMUX.IMUX8.DELAYPCIE.CFGERRAERHEADERLOG36
TCELL0:IMUX.IMUX9.DELAYPCIE.PIPERX3DATA5
TCELL0:IMUX.IMUX10.DELAYPCIE.CFGDSBUSNUMBER0
TCELL0:IMUX.IMUX11.DELAYPCIE.PIPERX7DATA0
TCELL0:IMUX.IMUX12.DELAYPCIE.CFGDSBUSNUMBER1
TCELL0:IMUX.IMUX13.DELAYPCIE.PIPERX7DATA1
TCELL0:IMUX.IMUX14.DELAYPCIE.CFGDSBUSNUMBER2
TCELL0:IMUX.IMUX15.DELAYPCIE.PIPERX3DATA2
TCELL0:IMUX.IMUX16.DELAYPCIE.CFGDSBUSNUMBER3
TCELL0:IMUX.IMUX17.DELAYPCIE.PIPERX7DATA4
TCELL0:IMUX.IMUX19.DELAYPCIE.PIPERX3DATA3
TCELL0:IMUX.IMUX21.DELAYPCIE.PIPERX7DATA5
TCELL0:IMUX.IMUX23.DELAYPCIE.PIPERX7DATA3
TCELL0:OUT0.TMINPCIE.TRNFCCPLH5
TCELL0:OUT1.TMINPCIE.TRNFCCPLH6
TCELL0:OUT2.TMINPCIE.TRNFCCPLH7
TCELL0:OUT3.TMINPCIE.TRNFCCPLD0
TCELL0:OUT4.TMINPCIE.MIMRXWDATA11
TCELL0:OUT5.TMINPCIE.MIMRXWDATA12
TCELL0:OUT6.TMINPCIE.PIPETXMARGIN2
TCELL0:OUT7.TMINPCIE.MIMRXWDATA13
TCELL0:OUT8.TMINPCIE.MIMRXWDATA14
TCELL0:OUT9.TMINPCIE.PL2LINKUPN
TCELL0:OUT10.TMINPCIE.PL2RECEIVERERRN
TCELL0:OUT11.TMINPCIE.LL2PROTOCOLERRN
TCELL0:OUT12.TMINPCIE.LL2BADTLPERRN
TCELL0:OUT13.TMINPCIE.CFGCOMMANDIOENABLE
TCELL0:OUT14.TMINPCIE.CFGCOMMANDMEMENABLE
TCELL0:OUT15.TMINPCIE.CFGCOMMANDBUSMASTERENABLE
TCELL0:OUT16.TMINPCIE.PIPETXMARGIN1
TCELL0:OUT17.TMINPCIE.CFGCOMMANDSERREN
TCELL0:OUT18.TMINPCIE.PIPETXMARGIN0
TCELL0:OUT19.TMINPCIE.DBGVECA26
TCELL0:OUT20.TMINPCIE.DBGVECA27
TCELL0:OUT21.TMINPCIE.DBGVECA28
TCELL0:OUT22.TMINPCIE.DBGVECA29
TCELL0:OUT23.TMINPCIE.DBGVECB59
TCELL1:IMUX.IMUX0.DELAYPCIE.MIMTXRDATA44
TCELL1:IMUX.IMUX1.DELAYPCIE.PIPERX3DATA6
TCELL1:IMUX.IMUX2.DELAYPCIE.CFGERRAERHEADERLOG29
TCELL1:IMUX.IMUX3.DELAYPCIE.PIPERX3DATA8
TCELL1:IMUX.IMUX4.DELAYPCIE.CFGERRAERHEADERLOG30
TCELL1:IMUX.IMUX5.DELAYPCIE.PIPERX3DATA9
TCELL1:IMUX.IMUX6.DELAYPCIE.CFGERRAERHEADERLOG31
TCELL1:IMUX.IMUX7.DELAYPCIE.PIPERX3DATA10
TCELL1:IMUX.IMUX8.DELAYPCIE.CFGERRAERHEADERLOG32
TCELL1:IMUX.IMUX9.DELAYPCIE.PIPERX3DATA7
TCELL1:IMUX.IMUX10.DELAYPCIE.CFGINTERRUPTDI5
TCELL1:IMUX.IMUX11.DELAYPCIE.PIPERX7DATA8
TCELL1:IMUX.IMUX12.DELAYPCIE.CFGINTERRUPTDI6
TCELL1:IMUX.IMUX13.DELAYPCIE.PIPERX7DATA9
TCELL1:IMUX.IMUX14.DELAYPCIE.CFGINTERRUPTDI7
TCELL1:IMUX.IMUX15.DELAYPCIE.PIPERX3DATA11
TCELL1:IMUX.IMUX16.DELAYPCIE.CFGINTERRUPTASSERTN
TCELL1:IMUX.IMUX17.DELAYPCIE.PIPERX7DATA6
TCELL1:IMUX.IMUX19.DELAYPCIE.PIPERX7DATA10
TCELL1:IMUX.IMUX21.DELAYPCIE.PIPERX7DATA7
TCELL1:IMUX.IMUX23.DELAYPCIE.PIPERX7DATA11
TCELL1:OUT0.TMINPCIE.TRNFCCPLH1
TCELL1:OUT1.TMINPCIE.TRNFCCPLH2
TCELL1:OUT2.TMINPCIE.TRNFCCPLH3
TCELL1:OUT3.TMINPCIE.TRNFCCPLH4
TCELL1:OUT4.TMINPCIE.MIMRXWDATA7
TCELL1:OUT5.TMINPCIE.MIMRXWDATA8
TCELL1:OUT6.TMINPCIE.MIMRXWDATA9
TCELL1:OUT7.TMINPCIE.MIMRXWDATA10
TCELL1:OUT8.TMINPCIE.LL2SUSPENDOKN
TCELL1:OUT9.TMINPCIE.TL2PPMSUSPENDOKN
TCELL1:OUT10.TMINPCIE.TL2ASPMSUSPENDREQN
TCELL1:OUT11.TMINPCIE.TL2ASPMSUSPENDCREDITCHECKOKN
TCELL1:OUT12.TMINPCIE.CFGTRANSACTIONADDR3
TCELL1:OUT13.TMINPCIE.CFGTRANSACTIONADDR4
TCELL1:OUT14.TMINPCIE.CFGTRANSACTIONADDR5
TCELL1:OUT15.TMINPCIE.CFGTRANSACTIONADDR6
TCELL1:OUT16.TMINPCIE.DRPDO7
TCELL1:OUT17.TMINPCIE.DRPDO8
TCELL1:OUT18.TMINPCIE.PIPERX3POLARITY
TCELL1:OUT19.TMINPCIE.DRPDO9
TCELL1:OUT20.TMINPCIE.DBGVECB58
TCELL1:OUT21.TMINPCIE.DBGVECA24
TCELL1:OUT22.TMINPCIE.PIPERX7POLARITY
TCELL1:OUT23.TMINPCIE.DBGVECA25
TCELL2:IMUX.IMUX0.DELAYPCIE.MIMTXRDATA41
TCELL2:IMUX.IMUX1.DELAYPCIE.PIPERX3CHARISK1
TCELL2:IMUX.IMUX2.DELAYPCIE.MIMTXRDATA42
TCELL2:IMUX.IMUX3.DELAYPCIE.PIPERX7DATA13
TCELL2:IMUX.IMUX4.DELAYPCIE.MIMTXRDATA43
TCELL2:IMUX.IMUX5.DELAYPCIE.PIPERX3DATA12
TCELL2:IMUX.IMUX6.DELAYPCIE.CFGERRAERHEADERLOG25
TCELL2:IMUX.IMUX7.DELAYPCIE.PIPERX3DATA13
TCELL2:IMUX.IMUX8.DELAYPCIE.CFGERRAERHEADERLOG26
TCELL2:IMUX.IMUX9.DELAYPCIE.PIPERX3DATA15
TCELL2:IMUX.IMUX10.DELAYPCIE.CFGERRAERHEADERLOG27
TCELL2:IMUX.IMUX11.DELAYPCIE.PIPERX3DATA14
TCELL2:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG28
TCELL2:IMUX.IMUX13.DELAYPCIE.PIPERX7DATA12
TCELL2:IMUX.IMUX14.DELAYPCIE.CFGINTERRUPTDI1
TCELL2:IMUX.IMUX15.DELAYPCIE.PIPERX7DATA14
TCELL2:IMUX.IMUX16.DELAYPCIE.CFGINTERRUPTDI2
TCELL2:IMUX.IMUX17.DELAYPCIE.PIPERX7CHARISK1
TCELL2:IMUX.IMUX18.DELAYPCIE.CFGINTERRUPTDI3
TCELL2:IMUX.IMUX19.DELAYPCIE.CFGINTERRUPTDI4
TCELL2:IMUX.IMUX21.DELAYPCIE.PIPERX7DATA15
TCELL2:OUT0.TMINPCIE.TRNFCNPD9
TCELL2:OUT1.TMINPCIE.TRNFCNPD10
TCELL2:OUT2.TMINPCIE.TRNFCNPD11
TCELL2:OUT3.TMINPCIE.TRNFCCPLH0
TCELL2:OUT4.TMINPCIE.MIMRXWDATA3
TCELL2:OUT5.TMINPCIE.MIMRXWDATA4
TCELL2:OUT6.TMINPCIE.MIMRXWDATA5
TCELL2:OUT7.TMINPCIE.MIMRXWDATA6
TCELL2:OUT8.TMINPCIE.LL2TFCINIT2SEQN
TCELL2:OUT9.TMINPCIE.PL2SUSPENDOK
TCELL2:OUT10.TMINPCIE.PL2RECOVERYN
TCELL2:OUT11.TMINPCIE.PL2RXELECIDLE
TCELL2:OUT12.TMINPCIE.CFGTRANSACTIONTYPE
TCELL2:OUT13.TMINPCIE.CFGTRANSACTIONADDR0
TCELL2:OUT14.TMINPCIE.CFGTRANSACTIONADDR1
TCELL2:OUT15.TMINPCIE.CFGTRANSACTIONADDR2
TCELL2:OUT16.TMINPCIE.DRPDO3
TCELL2:OUT17.TMINPCIE.DRPDO4
TCELL2:OUT18.TMINPCIE.DRPDO5
TCELL2:OUT19.TMINPCIE.DRPDO6
TCELL2:OUT20.TMINPCIE.DBGVECA20
TCELL2:OUT21.TMINPCIE.DBGVECA21
TCELL2:OUT22.TMINPCIE.DBGVECA22
TCELL2:OUT23.TMINPCIE.DBGVECA23
TCELL3:IMUX.IMUX0.DELAYPCIE.MIMTXRDATA37
TCELL3:IMUX.IMUX1.DELAYPCIE.PIPERX7CHANISALIGNED
TCELL3:IMUX.IMUX2.DELAYPCIE.MIMTXRDATA38
TCELL3:IMUX.IMUX3.DELAYPCIE.MIMTXRDATA39
TCELL3:IMUX.IMUX4.DELAYPCIE.MIMTXRDATA40
TCELL3:IMUX.IMUX5.DELAYPCIE.TRNTDLLPDATA23
TCELL3:IMUX.IMUX6.DELAYPCIE.TRNTDLLPDATA24
TCELL3:IMUX.IMUX7.DELAYPCIE.TRNTDLLPDATA25
TCELL3:IMUX.IMUX8.DELAYPCIE.TRNTDLLPDATA26
TCELL3:IMUX.IMUX9.DELAYPCIE.CFGERRAERHEADERLOG21
TCELL3:IMUX.IMUX10.DELAYPCIE.CFGERRAERHEADERLOG22
TCELL3:IMUX.IMUX11.DELAYPCIE.CFGERRAERHEADERLOG23
TCELL3:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG24
TCELL3:IMUX.IMUX13.DELAYPCIE.CFGERRTLPCPLHEADER46
TCELL3:IMUX.IMUX14.DELAYPCIE.CFGERRTLPCPLHEADER47
TCELL3:IMUX.IMUX15.DELAYPCIE.PIPERX7CHARISK0
TCELL3:IMUX.IMUX16.DELAYPCIE.CFGINTERRUPTN
TCELL3:IMUX.IMUX17.DELAYPCIE.CFGINTERRUPTDI0
TCELL3:IMUX.IMUX18.DELAYPCIE.CFGDSN63
TCELL3:IMUX.IMUX21.DELAYPCIE.PIPERX3CHANISALIGNED
TCELL3:IMUX.IMUX23.DELAYPCIE.PIPERX3CHARISK0
TCELL3:OUT0.TMINPCIE.TRNFCNPD5
TCELL3:OUT1.TMINPCIE.TRNFCNPD6
TCELL3:OUT2.TMINPCIE.TRNFCNPD7
TCELL3:OUT3.TMINPCIE.TRNFCNPD8
TCELL3:OUT4.TMINPCIE.MIMTXRCE
TCELL3:OUT5.TMINPCIE.MIMRXWDATA0
TCELL3:OUT6.TMINPCIE.MIMRXWDATA1
TCELL3:OUT7.TMINPCIE.MIMRXWDATA2
TCELL3:OUT8.TMINPCIE.TRNRDLLPDATA30
TCELL3:OUT9.TMINPCIE.TRNRDLLPDATA31
TCELL3:OUT10.TMINPCIE.TRNRDLLPSRCRDYN
TCELL3:OUT11.TMINPCIE.LL2TFCINIT1SEQN
TCELL3:OUT12.TMINPCIE.CFGPMRCVENTERL1N
TCELL3:OUT13.TMINPCIE.CFGPMRCVENTERL23N
TCELL3:OUT14.TMINPCIE.CFGPMRCVREQACKN
TCELL3:OUT15.TMINPCIE.CFGTRANSACTION
TCELL3:OUT16.TMINPCIE.DRPDRDY
TCELL3:OUT17.TMINPCIE.DRPDO0
TCELL3:OUT18.TMINPCIE.DRPDO1
TCELL3:OUT19.TMINPCIE.DRPDO2
TCELL3:OUT20.TMINPCIE.DBGVECA16
TCELL3:OUT21.TMINPCIE.DBGVECA17
TCELL3:OUT22.TMINPCIE.DBGVECA18
TCELL3:OUT23.TMINPCIE.DBGVECA19
TCELL4:IMUX.IMUX0.DELAYPCIE.MIMTXRDATA33
TCELL4:IMUX.IMUX1.DELAYPCIE.PIPERX7STATUS2
TCELL4:IMUX.IMUX2.DELAYPCIE.MIMTXRDATA34
TCELL4:IMUX.IMUX3.DELAYPCIE.PIPERX7STATUS0
TCELL4:IMUX.IMUX4.DELAYPCIE.MIMTXRDATA35
TCELL4:IMUX.IMUX5.DELAYPCIE.MIMTXRDATA36
TCELL4:IMUX.IMUX6.DELAYPCIE.TRNTDLLPDATA22
TCELL4:IMUX.IMUX7.DELAYPCIE.PIPERX7STATUS1
TCELL4:IMUX.IMUX8.DELAYPCIE.CFGERRAERHEADERLOG17
TCELL4:IMUX.IMUX9.DELAYPCIE.CFGERRAERHEADERLOG18
TCELL4:IMUX.IMUX10.DELAYPCIE.CFGERRAERHEADERLOG19
TCELL4:IMUX.IMUX11.DELAYPCIE.PIPERX3PHYSTATUS
TCELL4:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG20
TCELL4:IMUX.IMUX13.DELAYPCIE.CFGERRTLPCPLHEADER42
TCELL4:IMUX.IMUX14.DELAYPCIE.CFGERRTLPCPLHEADER43
TCELL4:IMUX.IMUX15.DELAYPCIE.PIPERX7PHYSTATUS
TCELL4:IMUX.IMUX16.DELAYPCIE.CFGERRTLPCPLHEADER44
TCELL4:IMUX.IMUX17.DELAYPCIE.CFGERRTLPCPLHEADER45
TCELL4:IMUX.IMUX19.DELAYPCIE.PIPERX3STATUS1
TCELL4:IMUX.IMUX21.DELAYPCIE.PIPERX3STATUS2
TCELL4:IMUX.IMUX23.DELAYPCIE.PIPERX3STATUS0
TCELL4:OUT0.TMINPCIE.TRNFCNPD1
TCELL4:OUT1.TMINPCIE.PIPETX3ELECIDLE
TCELL4:OUT2.TMINPCIE.TRNFCNPD2
TCELL4:OUT3.TMINPCIE.TRNFCNPD3
TCELL4:OUT4.TMINPCIE.TRNFCNPD4
TCELL4:OUT5.TMINPCIE.PIPETX7ELECIDLE
TCELL4:OUT6.TMINPCIE.MIMTXRADDR10
TCELL4:OUT7.TMINPCIE.MIMTXRADDR11
TCELL4:OUT8.TMINPCIE.MIMTXRADDR12
TCELL4:OUT9.TMINPCIE.MIMTXREN
TCELL4:OUT10.TMINPCIE.TRNRDLLPDATA26
TCELL4:OUT11.TMINPCIE.TRNRDLLPDATA27
TCELL4:OUT12.TMINPCIE.TRNRDLLPDATA28
TCELL4:OUT13.TMINPCIE.TRNRDLLPDATA29
TCELL4:OUT14.TMINPCIE.CFGPCIELINKSTATE2
TCELL4:OUT15.TMINPCIE.CFGPMRCVASREQL1N
TCELL4:OUT16.TMINPCIE.DBGVECB57
TCELL4:OUT17.TMINPCIE.PIPETX7POWERDOWN0
TCELL4:OUT18.TMINPCIE.DBGVECA13
TCELL4:OUT19.TMINPCIE.PIPETX7POWERDOWN1
TCELL4:OUT20.TMINPCIE.DBGVECA14
TCELL4:OUT21.TMINPCIE.PIPETX3POWERDOWN0
TCELL4:OUT22.TMINPCIE.DBGVECA15
TCELL4:OUT23.TMINPCIE.PIPETX3POWERDOWN1
TCELL5:IMUX.IMUX0.DELAYPCIE.MIMTXRDATA29
TCELL5:IMUX.IMUX1.DELAYPCIE.MIMTXRDATA30
TCELL5:IMUX.IMUX2.DELAYPCIE.MIMTXRDATA31
TCELL5:IMUX.IMUX3.DELAYPCIE.MIMTXRDATA32
TCELL5:IMUX.IMUX4.DELAYPCIE.TRNTDLLPDATA18
TCELL5:IMUX.IMUX5.DELAYPCIE.PIPERX7ELECIDLE
TCELL5:IMUX.IMUX6.DELAYPCIE.TRNTDLLPDATA19
TCELL5:IMUX.IMUX7.DELAYPCIE.TRNTDLLPDATA20
TCELL5:IMUX.IMUX8.DELAYPCIE.TRNTDLLPDATA21
TCELL5:IMUX.IMUX9.DELAYPCIE.CFGERRAERHEADERLOG13
TCELL5:IMUX.IMUX10.DELAYPCIE.CFGERRAERHEADERLOG14
TCELL5:IMUX.IMUX11.DELAYPCIE.PIPERX7VALID
TCELL5:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG15
TCELL5:IMUX.IMUX13.DELAYPCIE.CFGERRAERHEADERLOG16
TCELL5:IMUX.IMUX14.DELAYPCIE.CFGERRTLPCPLHEADER38
TCELL5:IMUX.IMUX15.DELAYPCIE.CFGERRTLPCPLHEADER39
TCELL5:IMUX.IMUX16.DELAYPCIE.CFGERRTLPCPLHEADER40
TCELL5:IMUX.IMUX17.DELAYPCIE.CFGERRTLPCPLHEADER41
TCELL5:IMUX.IMUX18.DELAYPCIE.CFGDSN62
TCELL5:IMUX.IMUX19.DELAYPCIE.PIPERX3VALID
TCELL5:IMUX.IMUX21.DELAYPCIE.PIPERX3ELECIDLE
TCELL5:OUT0.TMINPCIE.TRNFCNPH5
TCELL5:OUT1.TMINPCIE.TRNFCNPH6
TCELL5:OUT2.TMINPCIE.TRNFCNPH7
TCELL5:OUT3.TMINPCIE.TRNFCNPD0
TCELL5:OUT4.TMINPCIE.MIMTXRADDR6
TCELL5:OUT5.TMINPCIE.MIMTXRADDR7
TCELL5:OUT6.TMINPCIE.MIMTXRADDR8
TCELL5:OUT7.TMINPCIE.MIMTXRADDR9
TCELL5:OUT8.TMINPCIE.TRNRDLLPDATA22
TCELL5:OUT9.TMINPCIE.TRNRDLLPDATA23
TCELL5:OUT10.TMINPCIE.TRNRDLLPDATA24
TCELL5:OUT11.TMINPCIE.TRNRDLLPDATA25
TCELL5:OUT12.TMINPCIE.CFGPCIELINKSTATE1
TCELL5:OUT13.TMINPCIE.DBGVECB55
TCELL5:OUT14.TMINPCIE.DBGVECB56
TCELL5:OUT15.TMINPCIE.DBGVECA10
TCELL5:OUT16.TMINPCIE.PIPETX3COMPLIANCE
TCELL5:OUT17.TMINPCIE.DBGVECA11
TCELL5:OUT18.TMINPCIE.PIPETX3CHARISK0
TCELL5:OUT19.TMINPCIE.PIPETX7CHARISK1
TCELL5:OUT20.TMINPCIE.PIPETX7COMPLIANCE
TCELL5:OUT21.TMINPCIE.DBGVECA12
TCELL5:OUT22.TMINPCIE.PIPETX7CHARISK0
TCELL5:OUT23.TMINPCIE.PIPETX3CHARISK1
TCELL6:IMUX.IMUX0.DELAYPCIE.MIMTXRDATA25
TCELL6:IMUX.IMUX1.DELAYPCIE.MIMTXRDATA26
TCELL6:IMUX.IMUX2.DELAYPCIE.MIMTXRDATA27
TCELL6:IMUX.IMUX3.DELAYPCIE.MIMTXRDATA28
TCELL6:IMUX.IMUX4.DELAYPCIE.TRNTDLLPDATA14
TCELL6:IMUX.IMUX5.DELAYPCIE.TRNTDLLPDATA15
TCELL6:IMUX.IMUX6.DELAYPCIE.TRNTDLLPDATA16
TCELL6:IMUX.IMUX7.DELAYPCIE.TRNTDLLPDATA17
TCELL6:IMUX.IMUX8.DELAYPCIE.CFGERRAERHEADERLOG9
TCELL6:IMUX.IMUX9.DELAYPCIE.CFGERRAERHEADERLOG10
TCELL6:IMUX.IMUX10.DELAYPCIE.CFGERRAERHEADERLOG11
TCELL6:IMUX.IMUX11.DELAYPCIE.CFGERRAERHEADERLOG12
TCELL6:IMUX.IMUX12.DELAYPCIE.CFGERRTLPCPLHEADER34
TCELL6:IMUX.IMUX13.DELAYPCIE.CFGERRTLPCPLHEADER35
TCELL6:IMUX.IMUX14.DELAYPCIE.CFGERRTLPCPLHEADER36
TCELL6:IMUX.IMUX15.DELAYPCIE.CFGERRTLPCPLHEADER37
TCELL6:IMUX.IMUX16.DELAYPCIE.CFGDSN58
TCELL6:IMUX.IMUX17.DELAYPCIE.CFGDSN59
TCELL6:IMUX.IMUX18.DELAYPCIE.CFGDSN60
TCELL6:IMUX.IMUX19.DELAYPCIE.CFGDSN61
TCELL6:IMUX.IMUX20.DELAYPCIE.DBGMODE1
TCELL6:OUT0.TMINPCIE.TRNFCNPH1
TCELL6:OUT1.TMINPCIE.TRNFCNPH2
TCELL6:OUT2.TMINPCIE.PIPETX7DATA13
TCELL6:OUT3.TMINPCIE.TRNFCNPH3
TCELL6:OUT4.TMINPCIE.TRNFCNPH4
TCELL6:OUT5.TMINPCIE.MIMTXRADDR2
TCELL6:OUT6.TMINPCIE.PIPETX3DATA13
TCELL6:OUT7.TMINPCIE.MIMTXRADDR3
TCELL6:OUT8.TMINPCIE.MIMTXRADDR4
TCELL6:OUT9.TMINPCIE.MIMTXRADDR5
TCELL6:OUT10.TMINPCIE.TRNRDLLPDATA20
TCELL6:OUT11.TMINPCIE.TRNRDLLPDATA21
TCELL6:OUT12.TMINPCIE.CFGPCIELINKSTATE0
TCELL6:OUT13.TMINPCIE.DBGVECB53
TCELL6:OUT14.TMINPCIE.DBGVECB54
TCELL6:OUT15.TMINPCIE.DBGVECA7
TCELL6:OUT16.TMINPCIE.PIPETX3DATA12
TCELL6:OUT17.TMINPCIE.PIPETX7DATA15
TCELL6:OUT18.TMINPCIE.DBGVECA8
TCELL6:OUT19.TMINPCIE.PIPETX7DATA14
TCELL6:OUT20.TMINPCIE.PIPETX7DATA12
TCELL6:OUT21.TMINPCIE.PIPETX3DATA15
TCELL6:OUT22.TMINPCIE.DBGVECA9
TCELL6:OUT23.TMINPCIE.PIPETX3DATA14
TCELL7:IMUX.IMUX0.DELAYPCIE.MIMTXRDATA21
TCELL7:IMUX.IMUX1.DELAYPCIE.MIMTXRDATA22
TCELL7:IMUX.IMUX2.DELAYPCIE.MIMTXRDATA23
TCELL7:IMUX.IMUX3.DELAYPCIE.MIMTXRDATA24
TCELL7:IMUX.IMUX4.DELAYPCIE.TRNTDLLPDATA10
TCELL7:IMUX.IMUX5.DELAYPCIE.TRNTDLLPDATA11
TCELL7:IMUX.IMUX6.DELAYPCIE.TRNTDLLPDATA12
TCELL7:IMUX.IMUX7.DELAYPCIE.TRNTDLLPDATA13
TCELL7:IMUX.IMUX8.DELAYPCIE.CFGERRAERHEADERLOG5
TCELL7:IMUX.IMUX9.DELAYPCIE.CFGERRAERHEADERLOG6
TCELL7:IMUX.IMUX10.DELAYPCIE.CFGERRAERHEADERLOG7
TCELL7:IMUX.IMUX11.DELAYPCIE.CFGERRAERHEADERLOG8
TCELL7:IMUX.IMUX12.DELAYPCIE.CFGERRTLPCPLHEADER30
TCELL7:IMUX.IMUX13.DELAYPCIE.CFGERRTLPCPLHEADER31
TCELL7:IMUX.IMUX14.DELAYPCIE.CFGERRTLPCPLHEADER32
TCELL7:IMUX.IMUX15.DELAYPCIE.CFGERRTLPCPLHEADER33
TCELL7:IMUX.IMUX16.DELAYPCIE.CFGDSN54
TCELL7:IMUX.IMUX17.DELAYPCIE.CFGDSN55
TCELL7:IMUX.IMUX18.DELAYPCIE.CFGDSN56
TCELL7:IMUX.IMUX19.DELAYPCIE.CFGDSN57
TCELL7:IMUX.IMUX20.DELAYPCIE.DBGMODE0
TCELL7:OUT0.TMINPCIE.TRNFCPD9
TCELL7:OUT1.TMINPCIE.PIPETX3DATA11
TCELL7:OUT2.TMINPCIE.PIPETX7DATA8
TCELL7:OUT3.TMINPCIE.TRNFCPD10
TCELL7:OUT4.TMINPCIE.TRNFCPD11
TCELL7:OUT5.TMINPCIE.PIPETX7DATA11
TCELL7:OUT6.TMINPCIE.PIPETX3DATA8
TCELL7:OUT7.TMINPCIE.TRNFCNPH0
TCELL7:OUT8.TMINPCIE.MIMTXRADDR0
TCELL7:OUT9.TMINPCIE.MIMTXRADDR1
TCELL7:OUT10.TMINPCIE.CFGMSGRECEIVEDPMASNAK
TCELL7:OUT11.TMINPCIE.DBGVECB51
TCELL7:OUT12.TMINPCIE.DBGVECB52
TCELL7:OUT13.TMINPCIE.DBGVECA4
TCELL7:OUT14.TMINPCIE.DBGVECA5
TCELL7:OUT15.TMINPCIE.DBGVECA6
TCELL7:OUT16.TMINPCIE.PIPETX3DATA7
TCELL7:OUT17.TMINPCIE.PIPETX7DATA10
TCELL7:OUT18.TMINPCIE.PIPETX3DATA6
TCELL7:OUT19.TMINPCIE.PIPETX7DATA9
TCELL7:OUT20.TMINPCIE.PIPETX7DATA7
TCELL7:OUT21.TMINPCIE.PIPETX3DATA10
TCELL7:OUT22.TMINPCIE.PIPETX7DATA6
TCELL7:OUT23.TMINPCIE.PIPETX3DATA9
TCELL8:IMUX.IMUX0.DELAYPCIE.MIMTXRDATA17
TCELL8:IMUX.IMUX1.DELAYPCIE.MIMTXRDATA18
TCELL8:IMUX.IMUX2.DELAYPCIE.MIMTXRDATA19
TCELL8:IMUX.IMUX3.DELAYPCIE.MIMTXRDATA20
TCELL8:IMUX.IMUX4.DELAYPCIE.TRNTDLLPDATA6
TCELL8:IMUX.IMUX5.DELAYPCIE.TRNTDLLPDATA7
TCELL8:IMUX.IMUX6.DELAYPCIE.TRNTDLLPDATA8
TCELL8:IMUX.IMUX7.DELAYPCIE.TRNTDLLPDATA9
TCELL8:IMUX.IMUX8.DELAYPCIE.CFGERRAERHEADERLOG1
TCELL8:IMUX.IMUX9.DELAYPCIE.CFGERRAERHEADERLOG2
TCELL8:IMUX.IMUX10.DELAYPCIE.CFGERRAERHEADERLOG3
TCELL8:IMUX.IMUX11.DELAYPCIE.CFGERRAERHEADERLOG4
TCELL8:IMUX.IMUX12.DELAYPCIE.CFGERRTLPCPLHEADER26
TCELL8:IMUX.IMUX13.DELAYPCIE.CFGERRTLPCPLHEADER27
TCELL8:IMUX.IMUX14.DELAYPCIE.CFGERRTLPCPLHEADER28
TCELL8:IMUX.IMUX15.DELAYPCIE.CFGERRTLPCPLHEADER29
TCELL8:IMUX.IMUX16.DELAYPCIE.CFGDSN50
TCELL8:IMUX.IMUX17.DELAYPCIE.CFGDSN51
TCELL8:IMUX.IMUX18.DELAYPCIE.CFGDSN52
TCELL8:IMUX.IMUX19.DELAYPCIE.CFGDSN53
TCELL8:IMUX.IMUX20.DELAYPCIE.DRPDI15
TCELL8:OUT0.TMINPCIE.TRNFCPD5
TCELL8:OUT1.TMINPCIE.PIPETX3DATA3
TCELL8:OUT2.TMINPCIE.PIPETX7DATA4
TCELL8:OUT3.TMINPCIE.TRNFCPD6
TCELL8:OUT4.TMINPCIE.TRNFCPD7
TCELL8:OUT5.TMINPCIE.PIPETX7DATA3
TCELL8:OUT6.TMINPCIE.PIPETX3DATA4
TCELL8:OUT7.TMINPCIE.TRNFCPD8
TCELL8:OUT8.TMINPCIE.MIMTXWADDR12
TCELL8:OUT9.TMINPCIE.MIMTXWEN
TCELL8:OUT10.TMINPCIE.CFGMSGRECEIVEDUNLOCK
TCELL8:OUT11.TMINPCIE.DBGVECB49
TCELL8:OUT12.TMINPCIE.CFGVCTCVCMAP4
TCELL8:OUT13.TMINPCIE.CFGVCTCVCMAP5
TCELL8:OUT14.TMINPCIE.CFGVCTCVCMAP6
TCELL8:OUT15.TMINPCIE.DBGVECB50
TCELL8:OUT16.TMINPCIE.PIPETX3DATA0
TCELL8:OUT17.TMINPCIE.PIPETX7DATA1
TCELL8:OUT18.TMINPCIE.PIPETX3DATA5
TCELL8:OUT19.TMINPCIE.PIPETX7DATA2
TCELL8:OUT20.TMINPCIE.PIPETX7DATA0
TCELL8:OUT21.TMINPCIE.PIPETX3DATA1
TCELL8:OUT22.TMINPCIE.PIPETX7DATA5
TCELL8:OUT23.TMINPCIE.PIPETX3DATA2
TCELL9:IMUX.IMUX0.DELAYPCIE.MIMTXRDATA13
TCELL9:IMUX.IMUX1.DELAYPCIE.MIMTXRDATA14
TCELL9:IMUX.IMUX2.DELAYPCIE.MIMTXRDATA15
TCELL9:IMUX.IMUX3.DELAYPCIE.MIMTXRDATA16
TCELL9:IMUX.IMUX4.DELAYPCIE.TRNTDLLPDATA2
TCELL9:IMUX.IMUX5.DELAYPCIE.TRNTDLLPDATA3
TCELL9:IMUX.IMUX6.DELAYPCIE.TRNTDLLPDATA4
TCELL9:IMUX.IMUX7.DELAYPCIE.TRNTDLLPDATA5
TCELL9:IMUX.IMUX8.DELAYPCIE.CFGERRACSN
TCELL9:IMUX.IMUX9.DELAYPCIE.CFGERRPOSTEDN
TCELL9:IMUX.IMUX10.DELAYPCIE.CFGERRLOCKEDN
TCELL9:IMUX.IMUX11.DELAYPCIE.CFGERRAERHEADERLOG0
TCELL9:IMUX.IMUX12.DELAYPCIE.CFGERRTLPCPLHEADER22
TCELL9:IMUX.IMUX13.DELAYPCIE.CFGERRTLPCPLHEADER23
TCELL9:IMUX.IMUX14.DELAYPCIE.CFGERRTLPCPLHEADER24
TCELL9:IMUX.IMUX15.DELAYPCIE.CFGERRTLPCPLHEADER25
TCELL9:IMUX.IMUX16.DELAYPCIE.CFGDSN46
TCELL9:IMUX.IMUX17.DELAYPCIE.CFGDSN47
TCELL9:IMUX.IMUX18.DELAYPCIE.CFGDSN48
TCELL9:IMUX.IMUX19.DELAYPCIE.CFGDSN49
TCELL9:IMUX.IMUX20.DELAYPCIE.DRPDI14
TCELL9:OUT0.TMINPCIE.TRNFCPD1
TCELL9:OUT1.TMINPCIE.TRNFCPD2
TCELL9:OUT2.TMINPCIE.TRNFCPD3
TCELL9:OUT3.TMINPCIE.TRNFCPD4
TCELL9:OUT4.TMINPCIE.MIMTXWADDR8
TCELL9:OUT5.TMINPCIE.MIMTXWADDR9
TCELL9:OUT6.TMINPCIE.MIMTXWADDR10
TCELL9:OUT7.TMINPCIE.MIMTXWADDR11
TCELL9:OUT8.TMINPCIE.TRNRDLLPDATA16
TCELL9:OUT9.TMINPCIE.TRNRDLLPDATA17
TCELL9:OUT10.TMINPCIE.TRNRDLLPDATA18
TCELL9:OUT11.TMINPCIE.TRNRDLLPDATA19
TCELL9:OUT12.TMINPCIE.CFGMSGRECEIVEDPMPME
TCELL9:OUT13.TMINPCIE.CFGMSGRECEIVEDPMETOACK
TCELL9:OUT14.TMINPCIE.CFGMSGRECEIVEDPMETO
TCELL9:OUT15.TMINPCIE.CFGMSGRECEIVEDSETSLOTPOWERLIMIT
TCELL9:OUT16.TMINPCIE.CFGVCTCVCMAP0
TCELL9:OUT17.TMINPCIE.CFGVCTCVCMAP1
TCELL9:OUT18.TMINPCIE.CFGVCTCVCMAP2
TCELL9:OUT19.TMINPCIE.CFGVCTCVCMAP3
TCELL9:OUT20.TMINPCIE.DBGVECA3
TCELL9:OUT21.TMINPCIE.LNKCLKEN
TCELL9:OUT22.TMINPCIE.CFGPMCSRPOWERSTATE1
TCELL9:OUT23.TMINPCIE.CFGPMCSRPOWERSTATE0
TCELL10:IMUX.IMUX0.DELAYPCIE.MIMTXRDATA12
TCELL10:IMUX.IMUX1.DELAYPCIE.PIPERX2DATA4
TCELL10:IMUX.IMUX2.DELAYPCIE.CFGERRECRCN
TCELL10:IMUX.IMUX3.DELAYPCIE.PIPERX2DATA0
TCELL10:IMUX.IMUX4.DELAYPCIE.CFGERRCPLTIMEOUTN
TCELL10:IMUX.IMUX5.DELAYPCIE.PIPERX2DATA1
TCELL10:IMUX.IMUX6.DELAYPCIE.CFGERRCPLABORTN
TCELL10:IMUX.IMUX7.DELAYPCIE.PIPERX6DATA2
TCELL10:IMUX.IMUX8.DELAYPCIE.CFGERRCPLUNEXPECTN
TCELL10:IMUX.IMUX9.DELAYPCIE.PIPERX2DATA5
TCELL10:IMUX.IMUX10.DELAYPCIE.CFGERRTLPCPLHEADER18
TCELL10:IMUX.IMUX11.DELAYPCIE.PIPERX6DATA0
TCELL10:IMUX.IMUX12.DELAYPCIE.CFGERRTLPCPLHEADER19
TCELL10:IMUX.IMUX13.DELAYPCIE.PIPERX6DATA1
TCELL10:IMUX.IMUX14.DELAYPCIE.CFGERRTLPCPLHEADER20
TCELL10:IMUX.IMUX15.DELAYPCIE.PIPERX2DATA2
TCELL10:IMUX.IMUX16.DELAYPCIE.CFGERRTLPCPLHEADER21
TCELL10:IMUX.IMUX17.DELAYPCIE.PIPERX6DATA4
TCELL10:IMUX.IMUX19.DELAYPCIE.PIPERX2DATA3
TCELL10:IMUX.IMUX21.DELAYPCIE.PIPERX6DATA5
TCELL10:IMUX.IMUX23.DELAYPCIE.PIPERX6DATA3
TCELL10:OUT0.TMINPCIE.TRNFCPH5
TCELL10:OUT1.TMINPCIE.TRNFCPH6
TCELL10:OUT2.TMINPCIE.TRNFCPH7
TCELL10:OUT3.TMINPCIE.TRNFCPD0
TCELL10:OUT4.TMINPCIE.MIMTXWADDR4
TCELL10:OUT5.TMINPCIE.MIMTXWADDR5
TCELL10:OUT6.TMINPCIE.MIMTXWADDR6
TCELL10:OUT7.TMINPCIE.MIMTXWADDR7
TCELL10:OUT8.TMINPCIE.TRNRDLLPDATA12
TCELL10:OUT9.TMINPCIE.TRNRDLLPDATA13
TCELL10:OUT10.TMINPCIE.TRNRDLLPDATA14
TCELL10:OUT11.TMINPCIE.TRNRDLLPDATA15
TCELL10:OUT12.TMINPCIE.CFGMSGRECEIVEDASSERTINTC
TCELL10:OUT13.TMINPCIE.CFGMSGRECEIVEDDEASSERTINTC
TCELL10:OUT14.TMINPCIE.CFGMSGRECEIVEDASSERTINTD
TCELL10:OUT15.TMINPCIE.CFGMSGRECEIVEDDEASSERTINTD
TCELL10:OUT16.TMINPCIE.CFGDEVCONTROL2CPLTIMEOUTDIS
TCELL10:OUT17.TMINPCIE.CFGSLOTCONTROLELECTROMECHILCTLPULSE
TCELL10:OUT18.TMINPCIE.CFGAERECRCCHECKEN
TCELL10:OUT19.TMINPCIE.CFGAERECRCGENEN
TCELL10:OUT20.TMINPCIE.DRPDO15
TCELL10:OUT21.TMINPCIE.DBGVECA0
TCELL10:OUT22.TMINPCIE.DBGVECA1
TCELL10:OUT23.TMINPCIE.DBGVECA2
TCELL11:IMUX.IMUX0.DELAYPCIE.MIMTXRDATA11
TCELL11:IMUX.IMUX1.DELAYPCIE.PIPERX2DATA6
TCELL11:IMUX.IMUX2.DELAYPCIE.CFGWRENN
TCELL11:IMUX.IMUX3.DELAYPCIE.PIPERX2DATA8
TCELL11:IMUX.IMUX4.DELAYPCIE.CFGRDENN
TCELL11:IMUX.IMUX5.DELAYPCIE.PIPERX2DATA9
TCELL11:IMUX.IMUX6.DELAYPCIE.CFGERRCORN
TCELL11:IMUX.IMUX7.DELAYPCIE.PIPERX2DATA10
TCELL11:IMUX.IMUX8.DELAYPCIE.CFGERRURN
TCELL11:IMUX.IMUX9.DELAYPCIE.PIPERX2DATA7
TCELL11:IMUX.IMUX10.DELAYPCIE.CFGERRTLPCPLHEADER14
TCELL11:IMUX.IMUX11.DELAYPCIE.PIPERX6DATA8
TCELL11:IMUX.IMUX12.DELAYPCIE.CFGERRTLPCPLHEADER15
TCELL11:IMUX.IMUX13.DELAYPCIE.PIPERX6DATA9
TCELL11:IMUX.IMUX14.DELAYPCIE.CFGERRTLPCPLHEADER16
TCELL11:IMUX.IMUX15.DELAYPCIE.PIPERX2DATA11
TCELL11:IMUX.IMUX16.DELAYPCIE.CFGERRTLPCPLHEADER17
TCELL11:IMUX.IMUX17.DELAYPCIE.PIPERX6DATA6
TCELL11:IMUX.IMUX19.DELAYPCIE.PIPERX6DATA10
TCELL11:IMUX.IMUX21.DELAYPCIE.PIPERX6DATA7
TCELL11:IMUX.IMUX23.DELAYPCIE.PIPERX6DATA11
TCELL11:OUT0.TMINPCIE.TRNFCPH1
TCELL11:OUT1.TMINPCIE.TRNFCPH2
TCELL11:OUT2.TMINPCIE.TRNFCPH3
TCELL11:OUT3.TMINPCIE.TRNFCPH4
TCELL11:OUT4.TMINPCIE.MIMTXWADDR0
TCELL11:OUT5.TMINPCIE.MIMTXWADDR1
TCELL11:OUT6.TMINPCIE.MIMTXWADDR2
TCELL11:OUT7.TMINPCIE.MIMTXWADDR3
TCELL11:OUT8.TMINPCIE.TRNRDLLPDATA8
TCELL11:OUT9.TMINPCIE.TRNRDLLPDATA9
TCELL11:OUT10.TMINPCIE.TRNRDLLPDATA10
TCELL11:OUT11.TMINPCIE.TRNRDLLPDATA11
TCELL11:OUT12.TMINPCIE.CFGMSGRECEIVEDASSERTINTA
TCELL11:OUT13.TMINPCIE.CFGMSGRECEIVEDDEASSERTINTA
TCELL11:OUT14.TMINPCIE.CFGMSGRECEIVEDASSERTINTB
TCELL11:OUT15.TMINPCIE.CFGMSGRECEIVEDDEASSERTINTB
TCELL11:OUT16.TMINPCIE.CFGDEVCONTROL2CPLTIMEOUTVAL0
TCELL11:OUT17.TMINPCIE.CFGDEVCONTROL2CPLTIMEOUTVAL1
TCELL11:OUT18.TMINPCIE.PIPERX2POLARITY
TCELL11:OUT19.TMINPCIE.CFGDEVCONTROL2CPLTIMEOUTVAL2
TCELL11:OUT20.TMINPCIE.CFGDEVCONTROL2CPLTIMEOUTVAL3
TCELL11:OUT21.TMINPCIE.DRPDO13
TCELL11:OUT22.TMINPCIE.PIPERX6POLARITY
TCELL11:OUT23.TMINPCIE.DRPDO14
TCELL12:IMUX.IMUX0.DELAYPCIE.MIMTXRDATA8
TCELL12:IMUX.IMUX1.DELAYPCIE.PIPERX2CHARISK1
TCELL12:IMUX.IMUX2.DELAYPCIE.MIMTXRDATA9
TCELL12:IMUX.IMUX3.DELAYPCIE.PIPERX6DATA13
TCELL12:IMUX.IMUX4.DELAYPCIE.MIMTXRDATA10
TCELL12:IMUX.IMUX5.DELAYPCIE.PIPERX2DATA12
TCELL12:IMUX.IMUX6.DELAYPCIE.CFGDWADDR8
TCELL12:IMUX.IMUX7.DELAYPCIE.PIPERX2DATA13
TCELL12:IMUX.IMUX8.DELAYPCIE.CFGDWADDR9
TCELL12:IMUX.IMUX9.DELAYPCIE.PIPERX2DATA15
TCELL12:IMUX.IMUX10.DELAYPCIE.CFGWRRW1CASRWN
TCELL12:IMUX.IMUX11.DELAYPCIE.PIPERX2DATA14
TCELL12:IMUX.IMUX12.DELAYPCIE.CFGWRREADONLYN
TCELL12:IMUX.IMUX13.DELAYPCIE.PIPERX6DATA12
TCELL12:IMUX.IMUX14.DELAYPCIE.CFGERRTLPCPLHEADER10
TCELL12:IMUX.IMUX15.DELAYPCIE.PIPERX6DATA14
TCELL12:IMUX.IMUX16.DELAYPCIE.CFGERRTLPCPLHEADER11
TCELL12:IMUX.IMUX17.DELAYPCIE.PIPERX6CHARISK1
TCELL12:IMUX.IMUX18.DELAYPCIE.CFGERRTLPCPLHEADER12
TCELL12:IMUX.IMUX19.DELAYPCIE.CFGERRTLPCPLHEADER13
TCELL12:IMUX.IMUX21.DELAYPCIE.PIPERX6DATA15
TCELL12:OUT0.TMINPCIE.TRNRBARHITN5
TCELL12:OUT1.TMINPCIE.TRNRBARHITN6
TCELL12:OUT2.TMINPCIE.TRNLNKUPN
TCELL12:OUT3.TMINPCIE.TRNFCPH0
TCELL12:OUT4.TMINPCIE.MIMTXWDATA65
TCELL12:OUT5.TMINPCIE.MIMTXWDATA66
TCELL12:OUT6.TMINPCIE.MIMTXWDATA67
TCELL12:OUT7.TMINPCIE.MIMTXWDATA68
TCELL12:OUT8.TMINPCIE.TRNRDLLPDATA4
TCELL12:OUT9.TMINPCIE.TRNRDLLPDATA5
TCELL12:OUT10.TMINPCIE.TRNRDLLPDATA6
TCELL12:OUT11.TMINPCIE.TRNRDLLPDATA7
TCELL12:OUT12.TMINPCIE.CFGMSGDATA15
TCELL12:OUT13.TMINPCIE.CFGMSGRECEIVEDERRCOR
TCELL12:OUT14.TMINPCIE.CFGMSGRECEIVEDERRNONFATAL
TCELL12:OUT15.TMINPCIE.CFGMSGRECEIVEDERRFATAL
TCELL12:OUT16.TMINPCIE.CFGLINKCONTROLCLOCKPMEN
TCELL12:OUT17.TMINPCIE.CFGLINKCONTROLHWAUTOWIDTHDIS
TCELL12:OUT18.TMINPCIE.CFGLINKCONTROLBANDWIDTHINTEN
TCELL12:OUT19.TMINPCIE.CFGLINKCONTROLAUTOBANDWIDTHINTEN
TCELL12:OUT20.TMINPCIE.DRPDO12
TCELL12:OUT21.TMINPCIE.CFGPMCSRPMEEN
TCELL12:OUT22.TMINPCIE.DBGVECB47
TCELL12:OUT23.TMINPCIE.DBGVECB48
TCELL13:IMUX.IMUX0.DELAYPCIE.MIMTXRDATA4
TCELL13:IMUX.IMUX1.DELAYPCIE.PIPERX6CHANISALIGNED
TCELL13:IMUX.IMUX2.DELAYPCIE.MIMTXRDATA5
TCELL13:IMUX.IMUX3.DELAYPCIE.MIMTXRDATA6
TCELL13:IMUX.IMUX4.DELAYPCIE.MIMTXRDATA7
TCELL13:IMUX.IMUX5.DELAYPCIE.MIMRXRDATA66
TCELL13:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA67
TCELL13:IMUX.IMUX7.DELAYPCIE.TRNTDLLPDATA0
TCELL13:IMUX.IMUX8.DELAYPCIE.TRNTDLLPDATA1
TCELL13:IMUX.IMUX9.DELAYPCIE.CFGDWADDR4
TCELL13:IMUX.IMUX10.DELAYPCIE.CFGDWADDR5
TCELL13:IMUX.IMUX11.DELAYPCIE.CFGDWADDR6
TCELL13:IMUX.IMUX12.DELAYPCIE.CFGDWADDR7
TCELL13:IMUX.IMUX13.DELAYPCIE.CFGERRTLPCPLHEADER6
TCELL13:IMUX.IMUX14.DELAYPCIE.CFGERRTLPCPLHEADER7
TCELL13:IMUX.IMUX15.DELAYPCIE.PIPERX6CHARISK0
TCELL13:IMUX.IMUX16.DELAYPCIE.CFGERRTLPCPLHEADER8
TCELL13:IMUX.IMUX17.DELAYPCIE.CFGERRTLPCPLHEADER9
TCELL13:IMUX.IMUX18.DELAYPCIE.CFGDSN45
TCELL13:IMUX.IMUX21.DELAYPCIE.PIPERX2CHANISALIGNED
TCELL13:IMUX.IMUX23.DELAYPCIE.PIPERX2CHARISK0
TCELL13:OUT0.TMINPCIE.TRNRBARHITN1
TCELL13:OUT1.TMINPCIE.TRNRBARHITN2
TCELL13:OUT2.TMINPCIE.TRNRBARHITN3
TCELL13:OUT3.TMINPCIE.TRNRBARHITN4
TCELL13:OUT4.TMINPCIE.MIMTXWDATA61
TCELL13:OUT5.TMINPCIE.MIMTXWDATA62
TCELL13:OUT6.TMINPCIE.MIMTXWDATA63
TCELL13:OUT7.TMINPCIE.MIMTXWDATA64
TCELL13:OUT8.TMINPCIE.TRNRDLLPDATA0
TCELL13:OUT9.TMINPCIE.TRNRDLLPDATA1
TCELL13:OUT10.TMINPCIE.TRNRDLLPDATA2
TCELL13:OUT11.TMINPCIE.TRNRDLLPDATA3
TCELL13:OUT12.TMINPCIE.CFGMSGDATA11
TCELL13:OUT13.TMINPCIE.CFGMSGDATA12
TCELL13:OUT14.TMINPCIE.CFGMSGDATA13
TCELL13:OUT15.TMINPCIE.CFGMSGDATA14
TCELL13:OUT16.TMINPCIE.PIPETXDEEMPH
TCELL13:OUT17.TMINPCIE.CFGLINKCONTROLCOMMONCLOCK
TCELL13:OUT18.TMINPCIE.CFGLINKCONTROLEXTENDEDSYNC
TCELL13:OUT19.TMINPCIE.XILUNCONNOUT3
TCELL13:OUT20.TMINPCIE.CFGPMCSRPMESTATUS
TCELL13:OUT21.TMINPCIE.DBGVECB44
TCELL13:OUT22.TMINPCIE.DBGVECB45
TCELL13:OUT23.TMINPCIE.DBGVECB46
TCELL14:IMUX.IMUX0.DELAYPCIE.MIMTXRDATA0
TCELL14:IMUX.IMUX1.DELAYPCIE.PIPERX6STATUS2
TCELL14:IMUX.IMUX2.DELAYPCIE.MIMTXRDATA1
TCELL14:IMUX.IMUX3.DELAYPCIE.PIPERX6STATUS0
TCELL14:IMUX.IMUX4.DELAYPCIE.MIMTXRDATA2
TCELL14:IMUX.IMUX5.DELAYPCIE.MIMTXRDATA3
TCELL14:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA62
TCELL14:IMUX.IMUX7.DELAYPCIE.PIPERX6STATUS1
TCELL14:IMUX.IMUX8.DELAYPCIE.MIMRXRDATA63
TCELL14:IMUX.IMUX9.DELAYPCIE.MIMRXRDATA64
TCELL14:IMUX.IMUX10.DELAYPCIE.MIMRXRDATA65
TCELL14:IMUX.IMUX11.DELAYPCIE.PIPERX2PHYSTATUS
TCELL14:IMUX.IMUX12.DELAYPCIE.PMVDIVIDE1
TCELL14:IMUX.IMUX13.DELAYPCIE.PLTRANSMITHOTRST
TCELL14:IMUX.IMUX14.DELAYPCIE.CFGDI0
TCELL14:IMUX.IMUX15.DELAYPCIE.PIPERX6PHYSTATUS
TCELL14:IMUX.IMUX16.DELAYPCIE.CFGDI1
TCELL14:IMUX.IMUX17.DELAYPCIE.CFGDWADDR2
TCELL14:IMUX.IMUX18.DELAYPCIE.CFGDWADDR3
TCELL14:IMUX.IMUX19.DELAYPCIE.PIPERX2STATUS1
TCELL14:IMUX.IMUX21.DELAYPCIE.PIPERX2STATUS2
TCELL14:IMUX.IMUX23.DELAYPCIE.PIPERX2STATUS0
TCELL14:OUT0.TMINPCIE.TRNRSRCDSCN
TCELL14:OUT1.TMINPCIE.PIPETX2ELECIDLE
TCELL14:OUT2.TMINPCIE.TRNRECRCERRN
TCELL14:OUT3.TMINPCIE.TRNRERRFWDN
TCELL14:OUT4.TMINPCIE.TRNRBARHITN0
TCELL14:OUT5.TMINPCIE.PIPETX6ELECIDLE
TCELL14:OUT6.TMINPCIE.MIMTXWDATA57
TCELL14:OUT7.TMINPCIE.MIMTXWDATA58
TCELL14:OUT8.TMINPCIE.MIMTXWDATA59
TCELL14:OUT9.TMINPCIE.MIMTXWDATA60
TCELL14:OUT10.TMINPCIE.TRNTDLLPDSTRDYN
TCELL14:OUT11.TMINPCIE.CFGMSGDATA8
TCELL14:OUT12.TMINPCIE.CFGMSGDATA9
TCELL14:OUT13.TMINPCIE.CFGMSGDATA10
TCELL14:OUT14.TMINPCIE.XILUNCONNOUT1
TCELL14:OUT15.TMINPCIE.PIPETXRCVRDET
TCELL14:OUT16.TMINPCIE.XILUNCONNOUT2
TCELL14:OUT17.TMINPCIE.PIPETX6POWERDOWN0
TCELL14:OUT18.TMINPCIE.DBGVECB41
TCELL14:OUT19.TMINPCIE.PIPETX6POWERDOWN1
TCELL14:OUT20.TMINPCIE.DBGVECB42
TCELL14:OUT21.TMINPCIE.PIPETX2POWERDOWN0
TCELL14:OUT22.TMINPCIE.DBGVECB43
TCELL14:OUT23.TMINPCIE.PIPETX2POWERDOWN1
TCELL15:IMUX.IMUX0.DELAYPCIE.TRNRNPOKN
TCELL15:IMUX.IMUX1.DELAYPCIE.TRNFCSEL0
TCELL15:IMUX.IMUX2.DELAYPCIE.TRNFCSEL1
TCELL15:IMUX.IMUX3.DELAYPCIE.TRNFCSEL2
TCELL15:IMUX.IMUX4.DELAYPCIE.MIMRXRDATA58
TCELL15:IMUX.IMUX5.DELAYPCIE.PIPERX6ELECIDLE
TCELL15:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA59
TCELL15:IMUX.IMUX7.DELAYPCIE.MIMRXRDATA60
TCELL15:IMUX.IMUX8.DELAYPCIE.MIMRXRDATA61
TCELL15:IMUX.IMUX9.DELAYPCIE.PMVDIVIDE0
TCELL15:IMUX.IMUX10.DELAYPCIE.CFGDI2
TCELL15:IMUX.IMUX11.DELAYPCIE.PIPERX6VALID
TCELL15:IMUX.IMUX12.DELAYPCIE.CFGDI3
TCELL15:IMUX.IMUX13.DELAYPCIE.CFGDI4
TCELL15:IMUX.IMUX14.DELAYPCIE.CFGDI5
TCELL15:IMUX.IMUX15.DELAYPCIE.CFGBYTEENN2
TCELL15:IMUX.IMUX16.DELAYPCIE.CFGBYTEENN3
TCELL15:IMUX.IMUX17.DELAYPCIE.CFGDWADDR0
TCELL15:IMUX.IMUX18.DELAYPCIE.CFGDWADDR1
TCELL15:IMUX.IMUX19.DELAYPCIE.PIPERX2VALID
TCELL15:IMUX.IMUX20.DELAYPCIE.CFGERRTLPCPLHEADER5
TCELL15:IMUX.IMUX21.DELAYPCIE.PIPERX2ELECIDLE
TCELL15:OUT0.TMINPCIE.TRNRREMN
TCELL15:OUT1.TMINPCIE.TRNRSOFN
TCELL15:OUT2.TMINPCIE.TRNREOFN
TCELL15:OUT3.TMINPCIE.TRNRSRCRDYN
TCELL15:OUT4.TMINPCIE.MIMTXWDATA53
TCELL15:OUT5.TMINPCIE.MIMTXWDATA54
TCELL15:OUT6.TMINPCIE.MIMTXWDATA55
TCELL15:OUT7.TMINPCIE.MIMTXWDATA56
TCELL15:OUT8.TMINPCIE.CFGMSGDATA4
TCELL15:OUT9.TMINPCIE.CFGMSGDATA5
TCELL15:OUT10.TMINPCIE.CFGMSGDATA6
TCELL15:OUT11.TMINPCIE.CFGMSGDATA7
TCELL15:OUT12.TMINPCIE.CFGLINKCONTROLRCB
TCELL15:OUT13.TMINPCIE.CFGLINKCONTROLLINKDISABLE
TCELL15:OUT14.TMINPCIE.CFGLINKCONTROLRETRAINLINK
TCELL15:OUT15.TMINPCIE.XILUNCONNOUT0
TCELL15:OUT16.TMINPCIE.PIPETX2COMPLIANCE
TCELL15:OUT17.TMINPCIE.DBGVECB39
TCELL15:OUT18.TMINPCIE.PIPETX2CHARISK0
TCELL15:OUT19.TMINPCIE.PIPETX6CHARISK1
TCELL15:OUT20.TMINPCIE.PIPETX6COMPLIANCE
TCELL15:OUT21.TMINPCIE.DBGVECB40
TCELL15:OUT22.TMINPCIE.PIPETX6CHARISK0
TCELL15:OUT23.TMINPCIE.PIPETX2CHARISK1
TCELL16:IMUX.IMUX0.DELAYPCIE.TRNTECRCGENN
TCELL16:IMUX.IMUX1.DELAYPCIE.TRNTSTRN
TCELL16:IMUX.IMUX2.DELAYPCIE.TRNTCFGGNTN
TCELL16:IMUX.IMUX3.DELAYPCIE.TRNRDSTRDYN
TCELL16:IMUX.IMUX4.DELAYPCIE.MIMRXRDATA54
TCELL16:IMUX.IMUX5.DELAYPCIE.MIMRXRDATA55
TCELL16:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA56
TCELL16:IMUX.IMUX7.DELAYPCIE.MIMRXRDATA57
TCELL16:IMUX.IMUX8.DELAYPCIE.PMVSELECT2
TCELL16:IMUX.IMUX9.DELAYPCIE.CFGDI6
TCELL16:IMUX.IMUX10.DELAYPCIE.CFGDI7
TCELL16:IMUX.IMUX11.DELAYPCIE.CFGDI8
TCELL16:IMUX.IMUX12.DELAYPCIE.CFGDI9
TCELL16:IMUX.IMUX13.DELAYPCIE.CFGDI30
TCELL16:IMUX.IMUX14.DELAYPCIE.CFGDI31
TCELL16:IMUX.IMUX15.DELAYPCIE.CFGBYTEENN0
TCELL16:IMUX.IMUX16.DELAYPCIE.CFGBYTEENN1
TCELL16:IMUX.IMUX17.DELAYPCIE.CFGERRTLPCPLHEADER1
TCELL16:IMUX.IMUX18.DELAYPCIE.CFGERRTLPCPLHEADER2
TCELL16:IMUX.IMUX19.DELAYPCIE.CFGERRTLPCPLHEADER3
TCELL16:IMUX.IMUX20.DELAYPCIE.CFGERRTLPCPLHEADER4
TCELL16:IMUX.IMUX21.DELAYPCIE.CFGDSN44
TCELL16:OUT0.TMINPCIE.TRNRD60
TCELL16:OUT1.TMINPCIE.TRNRD61
TCELL16:OUT2.TMINPCIE.PIPETX6DATA13
TCELL16:OUT3.TMINPCIE.TRNRD62
TCELL16:OUT4.TMINPCIE.TRNRD63
TCELL16:OUT5.TMINPCIE.CFGMSGDATA0
TCELL16:OUT6.TMINPCIE.PIPETX2DATA13
TCELL16:OUT7.TMINPCIE.CFGMSGDATA1
TCELL16:OUT8.TMINPCIE.CFGMSGDATA2
TCELL16:OUT9.TMINPCIE.PIPETXRESET
TCELL16:OUT10.TMINPCIE.CFGMSGDATA3
TCELL16:OUT11.TMINPCIE.CFGLINKCONTROLASPMCONTROL1
TCELL16:OUT12.TMINPCIE.PLDBGVEC10
TCELL16:OUT13.TMINPCIE.PLDBGVEC11
TCELL16:OUT14.TMINPCIE.DBGVECB36
TCELL16:OUT15.TMINPCIE.DBGVECB37
TCELL16:OUT16.TMINPCIE.PIPETX2DATA12
TCELL16:OUT17.TMINPCIE.PIPETX6DATA15
TCELL16:OUT18.TMINPCIE.PIPETXRATE
TCELL16:OUT19.TMINPCIE.PIPETX6DATA14
TCELL16:OUT20.TMINPCIE.PIPETX6DATA12
TCELL16:OUT21.TMINPCIE.PIPETX2DATA15
TCELL16:OUT22.TMINPCIE.DBGVECB38
TCELL16:OUT23.TMINPCIE.PIPETX2DATA14
TCELL17:IMUX.IMUX0.DELAYPCIE.TRNTEOFN
TCELL17:IMUX.IMUX1.DELAYPCIE.TRNTSRCRDYN
TCELL17:IMUX.IMUX2.DELAYPCIE.TRNTSRCDSCN
TCELL17:IMUX.IMUX3.DELAYPCIE.TRNTERRFWDN
TCELL17:IMUX.IMUX4.DELAYPCIE.MIMRXRDATA50
TCELL17:IMUX.IMUX5.DELAYPCIE.MIMRXRDATA51
TCELL17:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA52
TCELL17:IMUX.IMUX7.DELAYPCIE.MIMRXRDATA53
TCELL17:IMUX.IMUX8.DELAYPCIE.PMVSELECT1
TCELL17:IMUX.IMUX9.DELAYPCIE.CFGDI10
TCELL17:IMUX.IMUX10.DELAYPCIE.CFGDI11
TCELL17:IMUX.IMUX11.DELAYPCIE.CFGDI12
TCELL17:IMUX.IMUX12.DELAYPCIE.CFGDI13
TCELL17:IMUX.IMUX13.DELAYPCIE.CFGDI26
TCELL17:IMUX.IMUX14.DELAYPCIE.CFGDI27
TCELL17:IMUX.IMUX15.DELAYPCIE.CFGDI28
TCELL17:IMUX.IMUX16.DELAYPCIE.CFGDI29
TCELL17:IMUX.IMUX17.DELAYPCIE.CFGERRAERHEADERLOG125
TCELL17:IMUX.IMUX18.DELAYPCIE.CFGERRAERHEADERLOG126
TCELL17:IMUX.IMUX19.DELAYPCIE.CFGERRAERHEADERLOG127
TCELL17:IMUX.IMUX20.DELAYPCIE.CFGERRTLPCPLHEADER0
TCELL17:IMUX.IMUX21.DELAYPCIE.CFGDSN43
TCELL17:OUT0.TMINPCIE.TRNRD58
TCELL17:OUT1.TMINPCIE.PIPETX2DATA11
TCELL17:OUT2.TMINPCIE.PIPETX6DATA8
TCELL17:OUT3.TMINPCIE.TRNRD59
TCELL17:OUT4.TMINPCIE.CFGINTERRUPTDO7
TCELL17:OUT5.TMINPCIE.PIPETX6DATA11
TCELL17:OUT6.TMINPCIE.PIPETX2DATA8
TCELL17:OUT7.TMINPCIE.CFGINTERRUPTMSIXENABLE
TCELL17:OUT8.TMINPCIE.CFGINTERRUPTMSIXFM
TCELL17:OUT9.TMINPCIE.CFGMSGRECEIVED
TCELL17:OUT10.TMINPCIE.CFGLINKCONTROLASPMCONTROL0
TCELL17:OUT11.TMINPCIE.PLDBGVEC8
TCELL17:OUT12.TMINPCIE.PLDBGVEC9
TCELL17:OUT13.TMINPCIE.DBGVECB33
TCELL17:OUT14.TMINPCIE.DBGVECB34
TCELL17:OUT15.TMINPCIE.DBGVECB35
TCELL17:OUT16.TMINPCIE.PIPETX2DATA7
TCELL17:OUT17.TMINPCIE.PIPETX6DATA10
TCELL17:OUT18.TMINPCIE.PIPETX2DATA6
TCELL17:OUT19.TMINPCIE.PIPETX6DATA9
TCELL17:OUT20.TMINPCIE.PIPETX6DATA7
TCELL17:OUT21.TMINPCIE.PIPETX2DATA10
TCELL17:OUT22.TMINPCIE.PIPETX6DATA6
TCELL17:OUT23.TMINPCIE.PIPETX2DATA9
TCELL18:IMUX.IMUX0.DELAYPCIE.TRNTD62
TCELL18:IMUX.IMUX1.DELAYPCIE.TRNTD63
TCELL18:IMUX.IMUX2.DELAYPCIE.TRNTREMN
TCELL18:IMUX.IMUX3.DELAYPCIE.TRNTSOFN
TCELL18:IMUX.IMUX4.DELAYPCIE.MIMRXRDATA46
TCELL18:IMUX.IMUX5.DELAYPCIE.MIMRXRDATA47
TCELL18:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA48
TCELL18:IMUX.IMUX7.DELAYPCIE.MIMRXRDATA49
TCELL18:IMUX.IMUX8.DELAYPCIE.PMVSELECT0
TCELL18:IMUX.IMUX9.DELAYPCIE.CFGDI14
TCELL18:IMUX.IMUX10.DELAYPCIE.CFGDI15
TCELL18:IMUX.IMUX11.DELAYPCIE.CFGDI16
TCELL18:IMUX.IMUX12.DELAYPCIE.CFGDI17
TCELL18:IMUX.IMUX13.DELAYPCIE.CFGDI22
TCELL18:IMUX.IMUX14.DELAYPCIE.CFGDI23
TCELL18:IMUX.IMUX15.DELAYPCIE.CFGDI24
TCELL18:IMUX.IMUX16.DELAYPCIE.CFGDI25
TCELL18:IMUX.IMUX17.DELAYPCIE.CFGERRAERHEADERLOG121
TCELL18:IMUX.IMUX18.DELAYPCIE.CFGERRAERHEADERLOG122
TCELL18:IMUX.IMUX19.DELAYPCIE.CFGERRAERHEADERLOG123
TCELL18:IMUX.IMUX20.DELAYPCIE.CFGERRAERHEADERLOG124
TCELL18:IMUX.IMUX21.DELAYPCIE.CFGDSN42
TCELL18:OUT0.TMINPCIE.TRNRD56
TCELL18:OUT1.TMINPCIE.PIPETX2DATA3
TCELL18:OUT2.TMINPCIE.PIPETX6DATA4
TCELL18:OUT3.TMINPCIE.TRNRD57
TCELL18:OUT4.TMINPCIE.CFGINTERRUPTDO3
TCELL18:OUT5.TMINPCIE.PIPETX6DATA3
TCELL18:OUT6.TMINPCIE.PIPETX2DATA4
TCELL18:OUT7.TMINPCIE.MIMRXRCE
TCELL18:OUT8.TMINPCIE.CFGINTERRUPTDO4
TCELL18:OUT9.TMINPCIE.CFGINTERRUPTDO5
TCELL18:OUT10.TMINPCIE.CFGINTERRUPTDO6
TCELL18:OUT11.TMINPCIE.CFGLINKSTATUSAUTOBANDWIDTHSTATUS
TCELL18:OUT12.TMINPCIE.PLDBGVEC6
TCELL18:OUT13.TMINPCIE.PLDBGVEC7
TCELL18:OUT14.TMINPCIE.DBGVECB31
TCELL18:OUT15.TMINPCIE.DBGVECB32
TCELL18:OUT16.TMINPCIE.PIPETX2DATA0
TCELL18:OUT17.TMINPCIE.PIPETX6DATA1
TCELL18:OUT18.TMINPCIE.PIPETX2DATA5
TCELL18:OUT19.TMINPCIE.PIPETX6DATA2
TCELL18:OUT20.TMINPCIE.PIPETX6DATA0
TCELL18:OUT21.TMINPCIE.PIPETX2DATA1
TCELL18:OUT22.TMINPCIE.PIPETX6DATA5
TCELL18:OUT23.TMINPCIE.PIPETX2DATA2
TCELL19:IMUX.IMUX0.DELAYPCIE.TRNTD58
TCELL19:IMUX.IMUX1.DELAYPCIE.TRNTD59
TCELL19:IMUX.IMUX2.DELAYPCIE.TRNTD60
TCELL19:IMUX.IMUX3.DELAYPCIE.TRNTD61
TCELL19:IMUX.IMUX4.DELAYPCIE.MIMRXRDATA42
TCELL19:IMUX.IMUX5.DELAYPCIE.MIMRXRDATA43
TCELL19:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA44
TCELL19:IMUX.IMUX7.DELAYPCIE.MIMRXRDATA45
TCELL19:IMUX.IMUX8.DELAYPCIE.PMVENABLEN
TCELL19:IMUX.IMUX9.DELAYPCIE.CFGDI18
TCELL19:IMUX.IMUX10.DELAYPCIE.CFGDI19
TCELL19:IMUX.IMUX11.DELAYPCIE.CFGDI20
TCELL19:IMUX.IMUX12.DELAYPCIE.CFGDI21
TCELL19:IMUX.IMUX13.DELAYPCIE.CFGERRAERHEADERLOG117
TCELL19:IMUX.IMUX14.DELAYPCIE.CFGERRAERHEADERLOG118
TCELL19:IMUX.IMUX15.DELAYPCIE.CFGERRAERHEADERLOG119
TCELL19:IMUX.IMUX16.DELAYPCIE.CFGERRAERHEADERLOG120
TCELL19:IMUX.IMUX17.DELAYPCIE.CFGDSN38
TCELL19:IMUX.IMUX18.DELAYPCIE.CFGDSN39
TCELL19:IMUX.IMUX19.DELAYPCIE.CFGDSN40
TCELL19:IMUX.IMUX20.DELAYPCIE.CFGDSN41
TCELL19:IMUX.IMUX21.DELAYPCIE.DRPDI13
TCELL19:OUT0.TMINPCIE.TRNRD52
TCELL19:OUT1.TMINPCIE.TRNRD53
TCELL19:OUT2.TMINPCIE.TRNRD54
TCELL19:OUT3.TMINPCIE.TRNRD55
TCELL19:OUT4.TMINPCIE.MIMTXWDATA49
TCELL19:OUT5.TMINPCIE.MIMTXWDATA50
TCELL19:OUT6.TMINPCIE.MIMTXWDATA51
TCELL19:OUT7.TMINPCIE.MIMTXWDATA52
TCELL19:OUT8.TMINPCIE.MIMRXRADDR10
TCELL19:OUT9.TMINPCIE.MIMRXRADDR11
TCELL19:OUT10.TMINPCIE.MIMRXRADDR12
TCELL19:OUT11.TMINPCIE.MIMRXREN
TCELL19:OUT12.TMINPCIE.CFGINTERRUPTMSIENABLE
TCELL19:OUT13.TMINPCIE.CFGINTERRUPTDO0
TCELL19:OUT14.TMINPCIE.CFGINTERRUPTDO1
TCELL19:OUT15.TMINPCIE.CFGINTERRUPTDO2
TCELL19:OUT16.TMINPCIE.CFGLINKSTATUSNEGOTIATEDWIDTH3
TCELL19:OUT17.TMINPCIE.CFGLINKSTATUSLINKTRAINING
TCELL19:OUT18.TMINPCIE.CFGLINKSTATUSDLLACTIVE
TCELL19:OUT19.TMINPCIE.CFGLINKSTATUSBANDWITHSTATUS
TCELL19:OUT20.TMINPCIE.DRPDO10
TCELL19:OUT21.TMINPCIE.DRPDO11
TCELL19:OUT22.TMINPCIE.PLDBGVEC5
TCELL19:OUT23.TMINPCIE.DBGVECB30
TCELL20:IMUX.CLK0PCIE.USERCLKPREBUF
TCELL20:IMUX.CTRL0PCIE.SYSRSTN
TCELL20:IMUX.CTRL1PCIE.CMRSTN
TCELL20:IMUX.IMUX0.DELAYPCIE.PLDIRECTEDLINKCHANGE0
TCELL20:IMUX.IMUX1.DELAYPCIE.PIPERX1DATA4
TCELL20:IMUX.IMUX2.DELAYPCIE.CFGERRAERHEADERLOG37
TCELL20:IMUX.IMUX3.DELAYPCIE.PIPERX1DATA0
TCELL20:IMUX.IMUX4.DELAYPCIE.CFGERRAERHEADERLOG38
TCELL20:IMUX.IMUX5.DELAYPCIE.PIPERX1DATA1
TCELL20:IMUX.IMUX6.DELAYPCIE.CFGERRAERHEADERLOG39
TCELL20:IMUX.IMUX7.DELAYPCIE.PIPERX5DATA2
TCELL20:IMUX.IMUX8.DELAYPCIE.CFGERRAERHEADERLOG40
TCELL20:IMUX.IMUX9.DELAYPCIE.PIPERX1DATA5
TCELL20:IMUX.IMUX10.DELAYPCIE.CFGDSBUSNUMBER4
TCELL20:IMUX.IMUX11.DELAYPCIE.PIPERX5DATA0
TCELL20:IMUX.IMUX12.DELAYPCIE.CFGDSBUSNUMBER5
TCELL20:IMUX.IMUX13.DELAYPCIE.PIPERX5DATA1
TCELL20:IMUX.IMUX14.DELAYPCIE.CFGDSBUSNUMBER6
TCELL20:IMUX.IMUX15.DELAYPCIE.PIPERX1DATA2
TCELL20:IMUX.IMUX16.DELAYPCIE.CFGDSBUSNUMBER7
TCELL20:IMUX.IMUX17.DELAYPCIE.PIPERX5DATA4
TCELL20:IMUX.IMUX19.DELAYPCIE.PIPERX1DATA3
TCELL20:IMUX.IMUX21.DELAYPCIE.PIPERX5DATA5
TCELL20:IMUX.IMUX23.DELAYPCIE.PIPERX5DATA3
TCELL20:OUT0.TMINPCIE.PLSELLNKRATE
TCELL20:OUT1.TMINPCIE.PLSELLNKWIDTH0
TCELL20:OUT2.TMINPCIE.PLSELLNKWIDTH1
TCELL20:OUT3.TMINPCIE.PLLTSSMSTATE0
TCELL20:OUT4.TMINPCIE.PLLTSSMSTATE1
TCELL20:OUT5.TMINPCIE.PLLTSSMSTATE2
TCELL20:OUT6.TMINPCIE.PLLTSSMSTATE3
TCELL20:OUT7.TMINPCIE.PLLTSSMSTATE4
TCELL20:OUT8.TMINPCIE.PLLTSSMSTATE5
TCELL20:OUT9.TMINPCIE.PLLANEREVERSALMODE0
TCELL20:OUT10.TMINPCIE.PLLANEREVERSALMODE1
TCELL20:OUT11.TMINPCIE.PLPHYLNKUPN
TCELL20:OUT12.TMINPCIE.PLTXPMSTATE0
TCELL20:OUT13.TMINPCIE.PLTXPMSTATE1
TCELL20:OUT14.TMINPCIE.PLTXPMSTATE2
TCELL20:OUT15.TMINPCIE.PLRXPMSTATE0
TCELL20:OUT16.TMINPCIE.TRNFCCPLD1
TCELL20:OUT17.TMINPCIE.TRNFCCPLD2
TCELL20:OUT18.TMINPCIE.TRNFCCPLD3
TCELL20:OUT19.TMINPCIE.TRNFCCPLD4
TCELL20:OUT20.TMINPCIE.MIMRXWDATA15
TCELL20:OUT21.TMINPCIE.DBGVECA30
TCELL20:OUT22.TMINPCIE.DBGVECA31
TCELL20:OUT23.TMINPCIE.DBGVECA32
TCELL21:IMUX.CTRL0PCIE.CMSTICKYRSTN
TCELL21:IMUX.CTRL1PCIE.FUNCLVLRSTN
TCELL21:IMUX.IMUX0.DELAYPCIE.PLDIRECTEDLINKCHANGE1
TCELL21:IMUX.IMUX1.DELAYPCIE.PIPERX1DATA6
TCELL21:IMUX.IMUX2.DELAYPCIE.CFGERRAERHEADERLOG41
TCELL21:IMUX.IMUX3.DELAYPCIE.PIPERX1DATA8
TCELL21:IMUX.IMUX4.DELAYPCIE.CFGERRAERHEADERLOG42
TCELL21:IMUX.IMUX5.DELAYPCIE.PIPERX1DATA9
TCELL21:IMUX.IMUX6.DELAYPCIE.CFGERRAERHEADERLOG43
TCELL21:IMUX.IMUX7.DELAYPCIE.PIPERX1DATA10
TCELL21:IMUX.IMUX8.DELAYPCIE.CFGERRAERHEADERLOG44
TCELL21:IMUX.IMUX9.DELAYPCIE.PIPERX1DATA7
TCELL21:IMUX.IMUX10.DELAYPCIE.CFGDSDEVICENUMBER0
TCELL21:IMUX.IMUX11.DELAYPCIE.PIPERX5DATA8
TCELL21:IMUX.IMUX12.DELAYPCIE.CFGDSDEVICENUMBER1
TCELL21:IMUX.IMUX13.DELAYPCIE.PIPERX5DATA9
TCELL21:IMUX.IMUX14.DELAYPCIE.CFGDSDEVICENUMBER2
TCELL21:IMUX.IMUX15.DELAYPCIE.PIPERX1DATA11
TCELL21:IMUX.IMUX16.DELAYPCIE.CFGDSDEVICENUMBER3
TCELL21:IMUX.IMUX17.DELAYPCIE.PIPERX5DATA6
TCELL21:IMUX.IMUX19.DELAYPCIE.PIPERX5DATA10
TCELL21:IMUX.IMUX21.DELAYPCIE.PIPERX5DATA7
TCELL21:IMUX.IMUX23.DELAYPCIE.PIPERX5DATA11
TCELL21:OUT0.TMINPCIE.PLRXPMSTATE1
TCELL21:OUT1.TMINPCIE.PLLINKUPCFGCAP
TCELL21:OUT2.TMINPCIE.PLLINKGEN2CAP
TCELL21:OUT3.TMINPCIE.PLLINKPARTNERGEN2SUPPORTED
TCELL21:OUT4.TMINPCIE.TRNFCCPLD5
TCELL21:OUT5.TMINPCIE.TRNFCCPLD6
TCELL21:OUT6.TMINPCIE.TRNFCCPLD7
TCELL21:OUT7.TMINPCIE.TRNFCCPLD8
TCELL21:OUT8.TMINPCIE.MIMRXWDATA16
TCELL21:OUT9.TMINPCIE.MIMRXWDATA17
TCELL21:OUT10.TMINPCIE.MIMRXWDATA18
TCELL21:OUT11.TMINPCIE.MIMRXWDATA19
TCELL21:OUT12.TMINPCIE.LL2BADDLLPERRN
TCELL21:OUT13.TMINPCIE.LL2REPLAYROERRN
TCELL21:OUT14.TMINPCIE.LL2REPLAYTOERRN
TCELL21:OUT15.TMINPCIE.PMVOUT
TCELL21:OUT16.TMINPCIE.CFGCOMMANDINTERRUPTDISABLE
TCELL21:OUT17.TMINPCIE.CFGDEVSTATUSCORRERRDETECTED
TCELL21:OUT18.TMINPCIE.PIPERX1POLARITY
TCELL21:OUT19.TMINPCIE.DBGVECB60
TCELL21:OUT20.TMINPCIE.DBGVECA33
TCELL21:OUT21.TMINPCIE.DBGVECA34
TCELL21:OUT22.TMINPCIE.PIPERX5POLARITY
TCELL21:OUT23.TMINPCIE.DBGVECA35
TCELL22:IMUX.CTRL0PCIE.TLRSTN
TCELL22:IMUX.CTRL1PCIE.DLRSTN
TCELL22:IMUX.IMUX0.DELAYPCIE.PLDIRECTEDLINKWIDTH0
TCELL22:IMUX.IMUX1.DELAYPCIE.PIPERX1CHARISK1
TCELL22:IMUX.IMUX2.DELAYPCIE.PLDIRECTEDLINKWIDTH1
TCELL22:IMUX.IMUX3.DELAYPCIE.PIPERX5DATA13
TCELL22:IMUX.IMUX4.DELAYPCIE.PLDIRECTEDLINKSPEED
TCELL22:IMUX.IMUX5.DELAYPCIE.PIPERX1DATA12
TCELL22:IMUX.IMUX6.DELAYPCIE.CFGERRAERHEADERLOG45
TCELL22:IMUX.IMUX7.DELAYPCIE.PIPERX1DATA13
TCELL22:IMUX.IMUX8.DELAYPCIE.CFGERRAERHEADERLOG46
TCELL22:IMUX.IMUX9.DELAYPCIE.PIPERX1DATA15
TCELL22:IMUX.IMUX10.DELAYPCIE.CFGERRAERHEADERLOG47
TCELL22:IMUX.IMUX11.DELAYPCIE.PIPERX1DATA14
TCELL22:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG48
TCELL22:IMUX.IMUX13.DELAYPCIE.PIPERX5DATA12
TCELL22:IMUX.IMUX14.DELAYPCIE.CFGDSDEVICENUMBER4
TCELL22:IMUX.IMUX15.DELAYPCIE.PIPERX5DATA14
TCELL22:IMUX.IMUX16.DELAYPCIE.CFGDSFUNCTIONNUMBER0
TCELL22:IMUX.IMUX17.DELAYPCIE.PIPERX5CHARISK1
TCELL22:IMUX.IMUX18.DELAYPCIE.CFGDSFUNCTIONNUMBER1
TCELL22:IMUX.IMUX19.DELAYPCIE.CFGDSFUNCTIONNUMBER2
TCELL22:IMUX.IMUX21.DELAYPCIE.PIPERX5DATA15
TCELL22:OUT0.TMINPCIE.PLINITIALLINKWIDTH0
TCELL22:OUT1.TMINPCIE.PLINITIALLINKWIDTH1
TCELL22:OUT2.TMINPCIE.PLINITIALLINKWIDTH2
TCELL22:OUT3.TMINPCIE.TRNTDSTRDYN
TCELL22:OUT4.TMINPCIE.TRNFCCPLD9
TCELL22:OUT5.TMINPCIE.TRNFCCPLD10
TCELL22:OUT6.TMINPCIE.TRNFCCPLD11
TCELL22:OUT7.TMINPCIE.MIMTXWDATA0
TCELL22:OUT8.TMINPCIE.MIMRXWDATA20
TCELL22:OUT9.TMINPCIE.MIMRXWDATA21
TCELL22:OUT10.TMINPCIE.MIMRXWDATA22
TCELL22:OUT11.TMINPCIE.MIMRXWDATA23
TCELL22:OUT12.TMINPCIE.USERRSTN
TCELL22:OUT13.TMINPCIE.PLRECEIVEDHOTRST
TCELL22:OUT14.TMINPCIE.RECEIVEDFUNCLVLRSTN
TCELL22:OUT15.TMINPCIE.CFGDO0
TCELL22:OUT16.TMINPCIE.CFGDEVSTATUSNONFATALERRDETECTED
TCELL22:OUT17.TMINPCIE.CFGDEVSTATUSFATALERRDETECTED
TCELL22:OUT18.TMINPCIE.CFGDEVSTATUSURDETECTED
TCELL22:OUT19.TMINPCIE.DBGVECB61
TCELL22:OUT20.TMINPCIE.DBGVECB62
TCELL22:OUT21.TMINPCIE.DBGVECA36
TCELL22:OUT22.TMINPCIE.DBGVECA37
TCELL22:OUT23.TMINPCIE.DBGVECA38
TCELL23:IMUX.CTRL0PCIE.PLRSTN
TCELL23:IMUX.IMUX0.DELAYPCIE.PLDIRECTEDLINKAUTON
TCELL23:IMUX.IMUX1.DELAYPCIE.PIPERX5CHANISALIGNED
TCELL23:IMUX.IMUX2.DELAYPCIE.PLUPSTREAMPREFERDEEMPH
TCELL23:IMUX.IMUX3.DELAYPCIE.PLDOWNSTREAMDEEMPHSOURCE
TCELL23:IMUX.IMUX4.DELAYPCIE.TRNTD0
TCELL23:IMUX.IMUX5.DELAYPCIE.MIMTXRDATA46
TCELL23:IMUX.IMUX6.DELAYPCIE.MIMTXRDATA47
TCELL23:IMUX.IMUX7.DELAYPCIE.MIMTXRDATA48
TCELL23:IMUX.IMUX8.DELAYPCIE.MIMTXRDATA49
TCELL23:IMUX.IMUX9.DELAYPCIE.TRNTDLLPDATA27
TCELL23:IMUX.IMUX10.DELAYPCIE.CFGERRAERHEADERLOG49
TCELL23:IMUX.IMUX11.DELAYPCIE.CFGERRAERHEADERLOG50
TCELL23:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG51
TCELL23:IMUX.IMUX13.DELAYPCIE.CFGERRAERHEADERLOG52
TCELL23:IMUX.IMUX14.DELAYPCIE.CFGPORTNUMBER0
TCELL23:IMUX.IMUX15.DELAYPCIE.PIPERX5CHARISK0
TCELL23:IMUX.IMUX16.DELAYPCIE.CFGPORTNUMBER1
TCELL23:IMUX.IMUX17.DELAYPCIE.CFGPORTNUMBER2
TCELL23:IMUX.IMUX18.DELAYPCIE.CFGPORTNUMBER3
TCELL23:IMUX.IMUX21.DELAYPCIE.PIPERX1CHANISALIGNED
TCELL23:IMUX.IMUX23.DELAYPCIE.PIPERX1CHARISK0
TCELL23:OUT0.TMINPCIE.TRNTERRDROPN
TCELL23:OUT1.TMINPCIE.TRNTBUFAV0
TCELL23:OUT2.TMINPCIE.TRNTBUFAV1
TCELL23:OUT3.TMINPCIE.TRNTBUFAV2
TCELL23:OUT4.TMINPCIE.MIMTXWDATA1
TCELL23:OUT5.TMINPCIE.MIMTXWDATA2
TCELL23:OUT6.TMINPCIE.MIMTXWDATA3
TCELL23:OUT7.TMINPCIE.MIMTXWDATA4
TCELL23:OUT8.TMINPCIE.MIMRXWDATA24
TCELL23:OUT9.TMINPCIE.MIMRXWDATA25
TCELL23:OUT10.TMINPCIE.MIMRXWDATA26
TCELL23:OUT11.TMINPCIE.MIMRXWDATA27
TCELL23:OUT12.TMINPCIE.CFGDO1
TCELL23:OUT13.TMINPCIE.CFGDO2
TCELL23:OUT14.TMINPCIE.CFGDO3
TCELL23:OUT15.TMINPCIE.CFGDO4
TCELL23:OUT16.TMINPCIE.CFGDEVCONTROLCORRERRREPORTINGEN
TCELL23:OUT17.TMINPCIE.CFGDEVCONTROLNONFATALREPORTINGEN
TCELL23:OUT18.TMINPCIE.CFGDEVCONTROLFATALERRREPORTINGEN
TCELL23:OUT19.TMINPCIE.DBGVECB63
TCELL23:OUT20.TMINPCIE.DBGVECC0
TCELL23:OUT21.TMINPCIE.DBGVECA39
TCELL23:OUT22.TMINPCIE.DBGVECA40
TCELL23:OUT23.TMINPCIE.DBGVECA41
TCELL24:IMUX.IMUX0.DELAYPCIE.TRNTD1
TCELL24:IMUX.IMUX1.DELAYPCIE.PIPERX5STATUS2
TCELL24:IMUX.IMUX2.DELAYPCIE.TRNTD2
TCELL24:IMUX.IMUX3.DELAYPCIE.PIPERX5STATUS0
TCELL24:IMUX.IMUX4.DELAYPCIE.TRNTD3
TCELL24:IMUX.IMUX5.DELAYPCIE.TRNTD4
TCELL24:IMUX.IMUX6.DELAYPCIE.MIMTXRDATA50
TCELL24:IMUX.IMUX7.DELAYPCIE.PIPERX5STATUS1
TCELL24:IMUX.IMUX8.DELAYPCIE.CFGERRAERHEADERLOG53
TCELL24:IMUX.IMUX9.DELAYPCIE.CFGERRAERHEADERLOG54
TCELL24:IMUX.IMUX10.DELAYPCIE.CFGERRAERHEADERLOG55
TCELL24:IMUX.IMUX11.DELAYPCIE.PIPERX1PHYSTATUS
TCELL24:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG56
TCELL24:IMUX.IMUX13.DELAYPCIE.CFGPORTNUMBER4
TCELL24:IMUX.IMUX14.DELAYPCIE.CFGPORTNUMBER5
TCELL24:IMUX.IMUX15.DELAYPCIE.PIPERX5PHYSTATUS
TCELL24:IMUX.IMUX16.DELAYPCIE.CFGPORTNUMBER6
TCELL24:IMUX.IMUX17.DELAYPCIE.CFGPORTNUMBER7
TCELL24:IMUX.IMUX19.DELAYPCIE.PIPERX1STATUS1
TCELL24:IMUX.IMUX21.DELAYPCIE.PIPERX1STATUS2
TCELL24:IMUX.IMUX23.DELAYPCIE.PIPERX1STATUS0
TCELL24:OUT0.TMINPCIE.TRNTBUFAV3
TCELL24:OUT1.TMINPCIE.PIPETX1ELECIDLE
TCELL24:OUT2.TMINPCIE.TRNTBUFAV4
TCELL24:OUT3.TMINPCIE.TRNTBUFAV5
TCELL24:OUT4.TMINPCIE.TRNTCFGREQN
TCELL24:OUT5.TMINPCIE.PIPETX5ELECIDLE
TCELL24:OUT6.TMINPCIE.MIMTXWDATA5
TCELL24:OUT7.TMINPCIE.MIMTXWDATA6
TCELL24:OUT8.TMINPCIE.MIMTXWDATA7
TCELL24:OUT9.TMINPCIE.MIMTXWDATA8
TCELL24:OUT10.TMINPCIE.MIMRXWDATA28
TCELL24:OUT11.TMINPCIE.MIMRXWDATA29
TCELL24:OUT12.TMINPCIE.MIMRXWDATA30
TCELL24:OUT13.TMINPCIE.MIMRXWDATA31
TCELL24:OUT14.TMINPCIE.CFGDO5
TCELL24:OUT15.TMINPCIE.DBGVECC1
TCELL24:OUT16.TMINPCIE.DBGVECC2
TCELL24:OUT17.TMINPCIE.PIPETX5POWERDOWN0
TCELL24:OUT18.TMINPCIE.DBGVECA42
TCELL24:OUT19.TMINPCIE.PIPETX5POWERDOWN1
TCELL24:OUT20.TMINPCIE.DBGVECA43
TCELL24:OUT21.TMINPCIE.PIPETX1POWERDOWN0
TCELL24:OUT22.TMINPCIE.DBGVECA44
TCELL24:OUT23.TMINPCIE.PIPETX1POWERDOWN1
TCELL25:IMUX.IMUX0.DELAYPCIE.TRNTD5
TCELL25:IMUX.IMUX1.DELAYPCIE.TRNTD6
TCELL25:IMUX.IMUX2.DELAYPCIE.TRNTD7
TCELL25:IMUX.IMUX3.DELAYPCIE.TRNTD8
TCELL25:IMUX.IMUX4.DELAYPCIE.MIMTXRDATA51
TCELL25:IMUX.IMUX5.DELAYPCIE.PIPERX5ELECIDLE
TCELL25:IMUX.IMUX6.DELAYPCIE.MIMTXRDATA52
TCELL25:IMUX.IMUX7.DELAYPCIE.MIMTXRDATA53
TCELL25:IMUX.IMUX8.DELAYPCIE.MIMTXRDATA54
TCELL25:IMUX.IMUX9.DELAYPCIE.TRNTDLLPDATA28
TCELL25:IMUX.IMUX10.DELAYPCIE.CFGERRAERHEADERLOG57
TCELL25:IMUX.IMUX11.DELAYPCIE.PIPERX5VALID
TCELL25:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG58
TCELL25:IMUX.IMUX13.DELAYPCIE.CFGERRAERHEADERLOG59
TCELL25:IMUX.IMUX14.DELAYPCIE.CFGERRAERHEADERLOG60
TCELL25:IMUX.IMUX15.DELAYPCIE.CFGPMWAKEN
TCELL25:IMUX.IMUX16.DELAYPCIE.CFGPMDIRECTASPML1N
TCELL25:IMUX.IMUX17.DELAYPCIE.CFGPMTURNOFFOKN
TCELL25:IMUX.IMUX18.DELAYPCIE.CFGPMSENDPMACKN
TCELL25:IMUX.IMUX19.DELAYPCIE.PIPERX1VALID
TCELL25:IMUX.IMUX21.DELAYPCIE.PIPERX1ELECIDLE
TCELL25:OUT0.TMINPCIE.TRNRD0
TCELL25:OUT1.TMINPCIE.TRNRD1
TCELL25:OUT2.TMINPCIE.TRNRD2
TCELL25:OUT3.TMINPCIE.TRNRD3
TCELL25:OUT4.TMINPCIE.MIMTXWDATA9
TCELL25:OUT5.TMINPCIE.MIMTXWDATA10
TCELL25:OUT6.TMINPCIE.MIMTXWDATA11
TCELL25:OUT7.TMINPCIE.MIMTXWDATA12
TCELL25:OUT8.TMINPCIE.MIMRXWDATA32
TCELL25:OUT9.TMINPCIE.MIMRXWDATA33
TCELL25:OUT10.TMINPCIE.MIMRXWDATA34
TCELL25:OUT11.TMINPCIE.MIMRXWDATA35
TCELL25:OUT12.TMINPCIE.CFGDO6
TCELL25:OUT13.TMINPCIE.DBGVECC3
TCELL25:OUT14.TMINPCIE.DBGVECC4
TCELL25:OUT15.TMINPCIE.DBGVECC5
TCELL25:OUT16.TMINPCIE.PIPETX1COMPLIANCE
TCELL25:OUT17.TMINPCIE.DBGVECA45
TCELL25:OUT18.TMINPCIE.PIPETX1CHARISK0
TCELL25:OUT19.TMINPCIE.PIPETX5CHARISK1
TCELL25:OUT20.TMINPCIE.PIPETX5COMPLIANCE
TCELL25:OUT21.TMINPCIE.DBGVECA46
TCELL25:OUT22.TMINPCIE.PIPETX5CHARISK0
TCELL25:OUT23.TMINPCIE.PIPETX1CHARISK1
TCELL26:IMUX.IMUX0.DELAYPCIE.TRNTD9
TCELL26:IMUX.IMUX1.DELAYPCIE.TRNTD10
TCELL26:IMUX.IMUX2.DELAYPCIE.TRNTD11
TCELL26:IMUX.IMUX3.DELAYPCIE.TRNTD12
TCELL26:IMUX.IMUX4.DELAYPCIE.MIMTXRDATA55
TCELL26:IMUX.IMUX5.DELAYPCIE.MIMTXRDATA56
TCELL26:IMUX.IMUX6.DELAYPCIE.MIMTXRDATA57
TCELL26:IMUX.IMUX7.DELAYPCIE.MIMTXRDATA58
TCELL26:IMUX.IMUX8.DELAYPCIE.TRNTDLLPDATA29
TCELL26:IMUX.IMUX9.DELAYPCIE.TRNTDLLPDATA30
TCELL26:IMUX.IMUX10.DELAYPCIE.TRNTDLLPDATA31
TCELL26:IMUX.IMUX11.DELAYPCIE.TRNTDLLPSRCRDYN
TCELL26:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG61
TCELL26:IMUX.IMUX13.DELAYPCIE.CFGERRAERHEADERLOG62
TCELL26:IMUX.IMUX14.DELAYPCIE.CFGERRAERHEADERLOG63
TCELL26:IMUX.IMUX15.DELAYPCIE.CFGERRAERHEADERLOG64
TCELL26:IMUX.IMUX16.DELAYPCIE.CFGPMSENDPMNAKN
TCELL26:IMUX.IMUX17.DELAYPCIE.CFGPMSENDPMETON
TCELL26:IMUX.IMUX18.DELAYPCIE.CFGTRNPENDINGN
TCELL26:IMUX.IMUX19.DELAYPCIE.CFGDSN0
TCELL26:IMUX.IMUX20.DELAYPCIE.DRPDEN
TCELL26:OUT0.TMINPCIE.TRNRD4
TCELL26:OUT1.TMINPCIE.TRNRD5
TCELL26:OUT2.TMINPCIE.PIPETX5DATA13
TCELL26:OUT3.TMINPCIE.TRNRD6
TCELL26:OUT4.TMINPCIE.TRNRD7
TCELL26:OUT5.TMINPCIE.MIMTXWDATA13
TCELL26:OUT6.TMINPCIE.PIPETX1DATA13
TCELL26:OUT7.TMINPCIE.MIMTXWDATA14
TCELL26:OUT8.TMINPCIE.CFGDO7
TCELL26:OUT9.TMINPCIE.MIMRXWDATA36
TCELL26:OUT10.TMINPCIE.MIMRXWDATA37
TCELL26:OUT11.TMINPCIE.MIMRXWDATA38
TCELL26:OUT12.TMINPCIE.MIMRXWDATA39
TCELL26:OUT13.TMINPCIE.DBGVECA47
TCELL26:OUT14.TMINPCIE.DBGVECA48
TCELL26:OUT15.TMINPCIE.DBGVECA49
TCELL26:OUT16.TMINPCIE.PIPETX1DATA12
TCELL26:OUT17.TMINPCIE.PIPETX5DATA15
TCELL26:OUT18.TMINPCIE.DBGVECA50
TCELL26:OUT19.TMINPCIE.PIPETX5DATA14
TCELL26:OUT20.TMINPCIE.PIPETX5DATA12
TCELL26:OUT21.TMINPCIE.PIPETX1DATA15
TCELL26:OUT22.TMINPCIE.DBGVECC6
TCELL26:OUT23.TMINPCIE.PIPETX1DATA14
TCELL27:IMUX.IMUX0.DELAYPCIE.TRNTD13
TCELL27:IMUX.IMUX1.DELAYPCIE.TRNTD14
TCELL27:IMUX.IMUX2.DELAYPCIE.TRNTD15
TCELL27:IMUX.IMUX3.DELAYPCIE.TRNTD16
TCELL27:IMUX.IMUX4.DELAYPCIE.MIMTXRDATA59
TCELL27:IMUX.IMUX5.DELAYPCIE.MIMTXRDATA60
TCELL27:IMUX.IMUX6.DELAYPCIE.MIMTXRDATA61
TCELL27:IMUX.IMUX7.DELAYPCIE.MIMTXRDATA62
TCELL27:IMUX.IMUX8.DELAYPCIE.LL2TLPRCVN
TCELL27:IMUX.IMUX9.DELAYPCIE.LL2SENDENTERL1N
TCELL27:IMUX.IMUX10.DELAYPCIE.LL2SENDENTERL23N
TCELL27:IMUX.IMUX11.DELAYPCIE.LL2SENDASREQL1N
TCELL27:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG65
TCELL27:IMUX.IMUX13.DELAYPCIE.CFGERRAERHEADERLOG66
TCELL27:IMUX.IMUX14.DELAYPCIE.CFGERRAERHEADERLOG67
TCELL27:IMUX.IMUX15.DELAYPCIE.CFGERRAERHEADERLOG68
TCELL27:IMUX.IMUX16.DELAYPCIE.CFGDSN1
TCELL27:IMUX.IMUX17.DELAYPCIE.CFGDSN2
TCELL27:IMUX.IMUX18.DELAYPCIE.CFGDSN3
TCELL27:IMUX.IMUX19.DELAYPCIE.CFGDSN4
TCELL27:IMUX.IMUX20.DELAYPCIE.DRPDWE
TCELL27:OUT0.TMINPCIE.TRNRD8
TCELL27:OUT1.TMINPCIE.PIPETX1DATA11
TCELL27:OUT2.TMINPCIE.PIPETX5DATA8
TCELL27:OUT3.TMINPCIE.TRNRD9
TCELL27:OUT4.TMINPCIE.CFGDO8
TCELL27:OUT5.TMINPCIE.PIPETX5DATA11
TCELL27:OUT6.TMINPCIE.PIPETX1DATA8
TCELL27:OUT7.TMINPCIE.MIMRXWDATA40
TCELL27:OUT8.TMINPCIE.MIMRXWDATA41
TCELL27:OUT9.TMINPCIE.MIMRXWDATA42
TCELL27:OUT10.TMINPCIE.MIMRXWDATA43
TCELL27:OUT11.TMINPCIE.DBGVECA51
TCELL27:OUT12.TMINPCIE.DBGVECA52
TCELL27:OUT13.TMINPCIE.DBGVECA53
TCELL27:OUT14.TMINPCIE.DBGVECA54
TCELL27:OUT15.TMINPCIE.DBGVECC7
TCELL27:OUT16.TMINPCIE.PIPETX1DATA7
TCELL27:OUT17.TMINPCIE.PIPETX5DATA10
TCELL27:OUT18.TMINPCIE.PIPETX1DATA6
TCELL27:OUT19.TMINPCIE.PIPETX5DATA9
TCELL27:OUT20.TMINPCIE.PIPETX5DATA7
TCELL27:OUT21.TMINPCIE.PIPETX1DATA10
TCELL27:OUT22.TMINPCIE.PIPETX5DATA6
TCELL27:OUT23.TMINPCIE.PIPETX1DATA9
TCELL28:IMUX.CLK0PCIE.DRPCLK
TCELL28:IMUX.IMUX0.DELAYPCIE.TRNTD17
TCELL28:IMUX.IMUX1.DELAYPCIE.TRNTD18
TCELL28:IMUX.IMUX2.DELAYPCIE.TRNTD19
TCELL28:IMUX.IMUX3.DELAYPCIE.TRNTD20
TCELL28:IMUX.IMUX4.DELAYPCIE.MIMTXRDATA63
TCELL28:IMUX.IMUX5.DELAYPCIE.MIMTXRDATA64
TCELL28:IMUX.IMUX6.DELAYPCIE.MIMTXRDATA65
TCELL28:IMUX.IMUX7.DELAYPCIE.MIMTXRDATA66
TCELL28:IMUX.IMUX8.DELAYPCIE.PL2DIRECTEDLSTATE0
TCELL28:IMUX.IMUX9.DELAYPCIE.PL2DIRECTEDLSTATE1
TCELL28:IMUX.IMUX10.DELAYPCIE.PL2DIRECTEDLSTATE2
TCELL28:IMUX.IMUX11.DELAYPCIE.PL2DIRECTEDLSTATE3
TCELL28:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG69
TCELL28:IMUX.IMUX13.DELAYPCIE.CFGERRAERHEADERLOG70
TCELL28:IMUX.IMUX14.DELAYPCIE.CFGERRAERHEADERLOG71
TCELL28:IMUX.IMUX15.DELAYPCIE.CFGERRAERHEADERLOG72
TCELL28:IMUX.IMUX16.DELAYPCIE.CFGDSN5
TCELL28:IMUX.IMUX17.DELAYPCIE.CFGDSN6
TCELL28:IMUX.IMUX18.DELAYPCIE.CFGDSN7
TCELL28:IMUX.IMUX19.DELAYPCIE.CFGDSN8
TCELL28:IMUX.IMUX20.DELAYPCIE.DRPDADDR0
TCELL28:OUT0.TMINPCIE.TRNRD10
TCELL28:OUT1.TMINPCIE.PIPETX1DATA3
TCELL28:OUT2.TMINPCIE.PIPETX5DATA4
TCELL28:OUT3.TMINPCIE.TRNRD11
TCELL28:OUT4.TMINPCIE.CFGDO9
TCELL28:OUT5.TMINPCIE.PIPETX5DATA3
TCELL28:OUT6.TMINPCIE.PIPETX1DATA4
TCELL28:OUT7.TMINPCIE.MIMRXWDATA44
TCELL28:OUT8.TMINPCIE.MIMRXWDATA45
TCELL28:OUT9.TMINPCIE.MIMRXWDATA46
TCELL28:OUT10.TMINPCIE.MIMRXWDATA47
TCELL28:OUT11.TMINPCIE.DBGVECA55
TCELL28:OUT12.TMINPCIE.DBGVECA56
TCELL28:OUT13.TMINPCIE.DBGVECA57
TCELL28:OUT14.TMINPCIE.DBGVECA58
TCELL28:OUT15.TMINPCIE.DBGVECC8
TCELL28:OUT16.TMINPCIE.PIPETX1DATA0
TCELL28:OUT17.TMINPCIE.PIPETX5DATA1
TCELL28:OUT18.TMINPCIE.PIPETX1DATA5
TCELL28:OUT19.TMINPCIE.PIPETX5DATA2
TCELL28:OUT20.TMINPCIE.PIPETX5DATA0
TCELL28:OUT21.TMINPCIE.PIPETX1DATA1
TCELL28:OUT22.TMINPCIE.PIPETX5DATA5
TCELL28:OUT23.TMINPCIE.PIPETX1DATA2
TCELL29:IMUX.CLK0PCIE.USERCLK
TCELL29:IMUX.CLK1PCIE.PIPECLK
TCELL29:IMUX.IMUX0.DELAYPCIE.TRNTD21
TCELL29:IMUX.IMUX1.DELAYPCIE.TRNTD22
TCELL29:IMUX.IMUX2.DELAYPCIE.TRNTD23
TCELL29:IMUX.IMUX3.DELAYPCIE.TRNTD24
TCELL29:IMUX.IMUX4.DELAYPCIE.MIMTXRDATA67
TCELL29:IMUX.IMUX5.DELAYPCIE.MIMTXRDATA68
TCELL29:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA0
TCELL29:IMUX.IMUX7.DELAYPCIE.MIMRXRDATA1
TCELL29:IMUX.IMUX8.DELAYPCIE.PL2DIRECTEDLSTATE4
TCELL29:IMUX.IMUX9.DELAYPCIE.LL2SUSPENDNOWN
TCELL29:IMUX.IMUX10.DELAYPCIE.TL2PPMSUSPENDREQN
TCELL29:IMUX.IMUX11.DELAYPCIE.TL2ASPMSUSPENDCREDITCHECKN
TCELL29:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG73
TCELL29:IMUX.IMUX13.DELAYPCIE.CFGERRAERHEADERLOG74
TCELL29:IMUX.IMUX14.DELAYPCIE.CFGERRAERHEADERLOG75
TCELL29:IMUX.IMUX15.DELAYPCIE.CFGERRAERHEADERLOG76
TCELL29:IMUX.IMUX16.DELAYPCIE.CFGDSN9
TCELL29:IMUX.IMUX17.DELAYPCIE.CFGDSN10
TCELL29:IMUX.IMUX18.DELAYPCIE.CFGDSN11
TCELL29:IMUX.IMUX19.DELAYPCIE.CFGDSN12
TCELL29:IMUX.IMUX20.DELAYPCIE.DRPDADDR1
TCELL29:IMUX.IMUX21.DELAYPCIE.DRPDADDR2
TCELL29:IMUX.IMUX22.DELAYPCIE.DRPDADDR3
TCELL29:OUT0.TMINPCIE.TRNRD12
TCELL29:OUT1.TMINPCIE.TRNRD13
TCELL29:OUT2.TMINPCIE.TRNRD14
TCELL29:OUT3.TMINPCIE.TRNRD15
TCELL29:OUT4.TMINPCIE.MIMTXWDATA15
TCELL29:OUT5.TMINPCIE.MIMTXWDATA16
TCELL29:OUT6.TMINPCIE.MIMTXWDATA17
TCELL29:OUT7.TMINPCIE.MIMTXWDATA18
TCELL29:OUT8.TMINPCIE.MIMRXWDATA48
TCELL29:OUT9.TMINPCIE.MIMRXWDATA49
TCELL29:OUT10.TMINPCIE.MIMRXWDATA50
TCELL29:OUT11.TMINPCIE.MIMRXWDATA51
TCELL29:OUT12.TMINPCIE.CFGDO10
TCELL29:OUT13.TMINPCIE.CFGDO11
TCELL29:OUT14.TMINPCIE.CFGDO12
TCELL29:OUT15.TMINPCIE.CFGDO13
TCELL29:OUT16.TMINPCIE.CFGDEVCONTROLURERRREPORTINGEN
TCELL29:OUT17.TMINPCIE.CFGDEVCONTROLENABLERO
TCELL29:OUT18.TMINPCIE.CFGDEVCONTROLMAXPAYLOAD0
TCELL29:OUT19.TMINPCIE.DBGVECC9
TCELL29:OUT20.TMINPCIE.DBGVECC10
TCELL29:OUT21.TMINPCIE.DBGVECA59
TCELL29:OUT22.TMINPCIE.DBGVECA60
TCELL29:OUT23.TMINPCIE.DBGVECA61
TCELL30:IMUX.IMUX0.DELAYPCIE.TRNTD25
TCELL30:IMUX.IMUX1.DELAYPCIE.PIPERX0DATA4
TCELL30:IMUX.IMUX2.DELAYPCIE.MIMRXRDATA2
TCELL30:IMUX.IMUX3.DELAYPCIE.PIPERX0DATA0
TCELL30:IMUX.IMUX4.DELAYPCIE.MIMRXRDATA3
TCELL30:IMUX.IMUX5.DELAYPCIE.PIPERX0DATA1
TCELL30:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA4
TCELL30:IMUX.IMUX7.DELAYPCIE.PIPERX4DATA2
TCELL30:IMUX.IMUX8.DELAYPCIE.MIMRXRDATA5
TCELL30:IMUX.IMUX9.DELAYPCIE.PIPERX0DATA5
TCELL30:IMUX.IMUX10.DELAYPCIE.SCANMODEN
TCELL30:IMUX.IMUX11.DELAYPCIE.PIPERX4DATA0
TCELL30:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG77
TCELL30:IMUX.IMUX13.DELAYPCIE.PIPERX4DATA1
TCELL30:IMUX.IMUX14.DELAYPCIE.CFGERRAERHEADERLOG78
TCELL30:IMUX.IMUX15.DELAYPCIE.PIPERX0DATA2
TCELL30:IMUX.IMUX16.DELAYPCIE.CFGERRAERHEADERLOG79
TCELL30:IMUX.IMUX17.DELAYPCIE.PIPERX4DATA4
TCELL30:IMUX.IMUX18.DELAYPCIE.CFGERRAERHEADERLOG80
TCELL30:IMUX.IMUX19.DELAYPCIE.PIPERX0DATA3
TCELL30:IMUX.IMUX21.DELAYPCIE.PIPERX4DATA5
TCELL30:IMUX.IMUX23.DELAYPCIE.PIPERX4DATA3
TCELL30:OUT0.TMINPCIE.TRNRD16
TCELL30:OUT1.TMINPCIE.TRNRD17
TCELL30:OUT2.TMINPCIE.TRNRD18
TCELL30:OUT3.TMINPCIE.TRNRD19
TCELL30:OUT4.TMINPCIE.MIMTXWDATA19
TCELL30:OUT5.TMINPCIE.MIMTXWDATA20
TCELL30:OUT6.TMINPCIE.MIMTXWDATA21
TCELL30:OUT7.TMINPCIE.MIMTXWDATA22
TCELL30:OUT8.TMINPCIE.MIMRXWDATA52
TCELL30:OUT9.TMINPCIE.MIMRXWDATA53
TCELL30:OUT10.TMINPCIE.MIMRXWDATA54
TCELL30:OUT11.TMINPCIE.MIMRXWDATA55
TCELL30:OUT12.TMINPCIE.CFGDO14
TCELL30:OUT13.TMINPCIE.CFGDO15
TCELL30:OUT14.TMINPCIE.CFGDO16
TCELL30:OUT15.TMINPCIE.CFGDO17
TCELL30:OUT16.TMINPCIE.CFGDEVCONTROLMAXPAYLOAD1
TCELL30:OUT17.TMINPCIE.CFGDEVCONTROLMAXPAYLOAD2
TCELL30:OUT18.TMINPCIE.CFGDEVCONTROLEXTTAGEN
TCELL30:OUT19.TMINPCIE.DBGVECC11
TCELL30:OUT20.TMINPCIE.DBGSCLRA
TCELL30:OUT21.TMINPCIE.DBGVECA62
TCELL30:OUT22.TMINPCIE.DBGVECA63
TCELL30:OUT23.TMINPCIE.DBGVECB0
TCELL31:IMUX.IMUX0.DELAYPCIE.TRNTD26
TCELL31:IMUX.IMUX1.DELAYPCIE.PIPERX0DATA6
TCELL31:IMUX.IMUX2.DELAYPCIE.MIMRXRDATA6
TCELL31:IMUX.IMUX3.DELAYPCIE.PIPERX0DATA8
TCELL31:IMUX.IMUX4.DELAYPCIE.MIMRXRDATA7
TCELL31:IMUX.IMUX5.DELAYPCIE.PIPERX0DATA9
TCELL31:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA8
TCELL31:IMUX.IMUX7.DELAYPCIE.PIPERX0DATA10
TCELL31:IMUX.IMUX8.DELAYPCIE.MIMRXRDATA9
TCELL31:IMUX.IMUX9.DELAYPCIE.PIPERX0DATA7
TCELL31:IMUX.IMUX10.DELAYPCIE.SCANENABLEN
TCELL31:IMUX.IMUX11.DELAYPCIE.PIPERX4DATA8
TCELL31:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG81
TCELL31:IMUX.IMUX13.DELAYPCIE.PIPERX4DATA9
TCELL31:IMUX.IMUX14.DELAYPCIE.CFGERRAERHEADERLOG82
TCELL31:IMUX.IMUX15.DELAYPCIE.PIPERX0DATA11
TCELL31:IMUX.IMUX16.DELAYPCIE.CFGERRAERHEADERLOG83
TCELL31:IMUX.IMUX17.DELAYPCIE.PIPERX4DATA6
TCELL31:IMUX.IMUX18.DELAYPCIE.CFGERRAERHEADERLOG84
TCELL31:IMUX.IMUX19.DELAYPCIE.PIPERX4DATA10
TCELL31:IMUX.IMUX21.DELAYPCIE.PIPERX4DATA7
TCELL31:IMUX.IMUX23.DELAYPCIE.PIPERX4DATA11
TCELL31:OUT0.TMINPCIE.TRNRD20
TCELL31:OUT1.TMINPCIE.TRNRD21
TCELL31:OUT2.TMINPCIE.TRNRD22
TCELL31:OUT3.TMINPCIE.TRNRD23
TCELL31:OUT4.TMINPCIE.MIMTXWDATA23
TCELL31:OUT5.TMINPCIE.MIMTXWDATA24
TCELL31:OUT6.TMINPCIE.MIMTXWDATA25
TCELL31:OUT7.TMINPCIE.MIMTXWDATA26
TCELL31:OUT8.TMINPCIE.MIMRXWDATA56
TCELL31:OUT9.TMINPCIE.MIMRXWDATA57
TCELL31:OUT10.TMINPCIE.MIMRXWDATA58
TCELL31:OUT11.TMINPCIE.MIMRXWDATA59
TCELL31:OUT12.TMINPCIE.CFGDO18
TCELL31:OUT13.TMINPCIE.CFGDO19
TCELL31:OUT14.TMINPCIE.CFGDO20
TCELL31:OUT15.TMINPCIE.CFGDO21
TCELL31:OUT16.TMINPCIE.CFGDEVCONTROLPHANTOMEN
TCELL31:OUT17.TMINPCIE.CFGDEVCONTROLAUXPOWEREN
TCELL31:OUT18.TMINPCIE.PIPERX0POLARITY
TCELL31:OUT19.TMINPCIE.DBGSCLRB
TCELL31:OUT20.TMINPCIE.DBGVECB1
TCELL31:OUT21.TMINPCIE.DBGVECB2
TCELL31:OUT22.TMINPCIE.PIPERX4POLARITY
TCELL31:OUT23.TMINPCIE.DBGVECB3
TCELL32:IMUX.IMUX0.DELAYPCIE.TRNTD27
TCELL32:IMUX.IMUX1.DELAYPCIE.PIPERX0CHARISK1
TCELL32:IMUX.IMUX2.DELAYPCIE.TRNTD28
TCELL32:IMUX.IMUX3.DELAYPCIE.PIPERX4DATA13
TCELL32:IMUX.IMUX4.DELAYPCIE.TRNTD29
TCELL32:IMUX.IMUX5.DELAYPCIE.PIPERX0DATA12
TCELL32:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA10
TCELL32:IMUX.IMUX7.DELAYPCIE.PIPERX0DATA13
TCELL32:IMUX.IMUX8.DELAYPCIE.MIMRXRDATA11
TCELL32:IMUX.IMUX9.DELAYPCIE.PIPERX0DATA15
TCELL32:IMUX.IMUX10.DELAYPCIE.MIMRXRDATA12
TCELL32:IMUX.IMUX11.DELAYPCIE.PIPERX0DATA14
TCELL32:IMUX.IMUX12.DELAYPCIE.MIMRXRDATA13
TCELL32:IMUX.IMUX13.DELAYPCIE.PIPERX4DATA12
TCELL32:IMUX.IMUX14.DELAYPCIE.SCANIN0
TCELL32:IMUX.IMUX15.DELAYPCIE.PIPERX4DATA14
TCELL32:IMUX.IMUX16.DELAYPCIE.CFGERRAERHEADERLOG85
TCELL32:IMUX.IMUX17.DELAYPCIE.PIPERX4CHARISK1
TCELL32:IMUX.IMUX18.DELAYPCIE.CFGERRAERHEADERLOG86
TCELL32:IMUX.IMUX19.DELAYPCIE.CFGERRAERHEADERLOG87
TCELL32:IMUX.IMUX20.DELAYPCIE.CFGERRAERHEADERLOG88
TCELL32:IMUX.IMUX21.DELAYPCIE.PIPERX4DATA15
TCELL32:OUT0.TMINPCIE.TRNRD24
TCELL32:OUT1.TMINPCIE.TRNRD25
TCELL32:OUT2.TMINPCIE.TRNRD26
TCELL32:OUT3.TMINPCIE.TRNRD27
TCELL32:OUT4.TMINPCIE.MIMTXWDATA27
TCELL32:OUT5.TMINPCIE.MIMTXWDATA28
TCELL32:OUT6.TMINPCIE.MIMTXWDATA29
TCELL32:OUT7.TMINPCIE.MIMTXWDATA30
TCELL32:OUT8.TMINPCIE.MIMRXWDATA60
TCELL32:OUT9.TMINPCIE.MIMRXWDATA61
TCELL32:OUT10.TMINPCIE.MIMRXWDATA62
TCELL32:OUT11.TMINPCIE.MIMRXWDATA63
TCELL32:OUT12.TMINPCIE.CFGDO22
TCELL32:OUT13.TMINPCIE.CFGDO23
TCELL32:OUT14.TMINPCIE.CFGDO24
TCELL32:OUT15.TMINPCIE.CFGDO25
TCELL32:OUT16.TMINPCIE.CFGDEVCONTROLNOSNOOPEN
TCELL32:OUT17.TMINPCIE.CFGDEVCONTROLMAXREADREQ0
TCELL32:OUT18.TMINPCIE.CFGDEVCONTROLMAXREADREQ1
TCELL32:OUT19.TMINPCIE.DBGSCLRC
TCELL32:OUT20.TMINPCIE.DBGSCLRD
TCELL32:OUT21.TMINPCIE.DBGVECB4
TCELL32:OUT22.TMINPCIE.DBGVECB5
TCELL32:OUT23.TMINPCIE.DBGVECB6
TCELL33:IMUX.IMUX0.DELAYPCIE.TRNTD30
TCELL33:IMUX.IMUX1.DELAYPCIE.PIPERX4CHANISALIGNED
TCELL33:IMUX.IMUX2.DELAYPCIE.TRNTD31
TCELL33:IMUX.IMUX3.DELAYPCIE.TRNTD32
TCELL33:IMUX.IMUX4.DELAYPCIE.TRNTD33
TCELL33:IMUX.IMUX5.DELAYPCIE.MIMRXRDATA14
TCELL33:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA15
TCELL33:IMUX.IMUX7.DELAYPCIE.MIMRXRDATA16
TCELL33:IMUX.IMUX8.DELAYPCIE.MIMRXRDATA17
TCELL33:IMUX.IMUX9.DELAYPCIE.SCANIN1
TCELL33:IMUX.IMUX10.DELAYPCIE.CFGERRAERHEADERLOG89
TCELL33:IMUX.IMUX11.DELAYPCIE.CFGERRAERHEADERLOG90
TCELL33:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG91
TCELL33:IMUX.IMUX13.DELAYPCIE.CFGERRAERHEADERLOG92
TCELL33:IMUX.IMUX14.DELAYPCIE.CFGDSN13
TCELL33:IMUX.IMUX15.DELAYPCIE.PIPERX4CHARISK0
TCELL33:IMUX.IMUX16.DELAYPCIE.CFGDSN14
TCELL33:IMUX.IMUX17.DELAYPCIE.CFGDSN15
TCELL33:IMUX.IMUX18.DELAYPCIE.CFGDSN16
TCELL33:IMUX.IMUX19.DELAYPCIE.DRPDADDR4
TCELL33:IMUX.IMUX21.DELAYPCIE.PIPERX0CHANISALIGNED
TCELL33:IMUX.IMUX23.DELAYPCIE.PIPERX0CHARISK0
TCELL33:OUT0.TMINPCIE.TRNRD28
TCELL33:OUT1.TMINPCIE.TRNRD29
TCELL33:OUT2.TMINPCIE.TRNRD30
TCELL33:OUT3.TMINPCIE.TRNRD31
TCELL33:OUT4.TMINPCIE.MIMTXWDATA31
TCELL33:OUT5.TMINPCIE.MIMTXWDATA32
TCELL33:OUT6.TMINPCIE.MIMTXWDATA33
TCELL33:OUT7.TMINPCIE.MIMTXWDATA34
TCELL33:OUT8.TMINPCIE.MIMRXWDATA64
TCELL33:OUT9.TMINPCIE.MIMRXWDATA65
TCELL33:OUT10.TMINPCIE.MIMRXWDATA66
TCELL33:OUT11.TMINPCIE.MIMRXWDATA67
TCELL33:OUT12.TMINPCIE.CFGDO26
TCELL33:OUT13.TMINPCIE.CFGDO27
TCELL33:OUT14.TMINPCIE.CFGDO28
TCELL33:OUT15.TMINPCIE.CFGDO29
TCELL33:OUT16.TMINPCIE.CFGDEVCONTROLMAXREADREQ2
TCELL33:OUT17.TMINPCIE.CFGLINKSTATUSCURRENTSPEED0
TCELL33:OUT18.TMINPCIE.CFGLINKSTATUSCURRENTSPEED1
TCELL33:OUT19.TMINPCIE.DBGSCLRE
TCELL33:OUT20.TMINPCIE.DBGSCLRF
TCELL33:OUT21.TMINPCIE.DBGVECB7
TCELL33:OUT22.TMINPCIE.DBGVECB8
TCELL33:OUT23.TMINPCIE.DBGVECB9
TCELL34:IMUX.IMUX0.DELAYPCIE.TRNTD34
TCELL34:IMUX.IMUX1.DELAYPCIE.PIPERX4STATUS2
TCELL34:IMUX.IMUX2.DELAYPCIE.TRNTD35
TCELL34:IMUX.IMUX3.DELAYPCIE.PIPERX4STATUS0
TCELL34:IMUX.IMUX4.DELAYPCIE.TRNTD36
TCELL34:IMUX.IMUX5.DELAYPCIE.TRNTD37
TCELL34:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA18
TCELL34:IMUX.IMUX7.DELAYPCIE.PIPERX4STATUS1
TCELL34:IMUX.IMUX8.DELAYPCIE.MIMRXRDATA19
TCELL34:IMUX.IMUX9.DELAYPCIE.MIMRXRDATA20
TCELL34:IMUX.IMUX10.DELAYPCIE.MIMRXRDATA21
TCELL34:IMUX.IMUX11.DELAYPCIE.PIPERX0PHYSTATUS
TCELL34:IMUX.IMUX12.DELAYPCIE.SCANIN2
TCELL34:IMUX.IMUX13.DELAYPCIE.CFGERRAERHEADERLOG93
TCELL34:IMUX.IMUX14.DELAYPCIE.CFGERRAERHEADERLOG94
TCELL34:IMUX.IMUX15.DELAYPCIE.PIPERX4PHYSTATUS
TCELL34:IMUX.IMUX16.DELAYPCIE.CFGERRAERHEADERLOG95
TCELL34:IMUX.IMUX17.DELAYPCIE.CFGERRAERHEADERLOG96
TCELL34:IMUX.IMUX18.DELAYPCIE.CFGDSN17
TCELL34:IMUX.IMUX19.DELAYPCIE.PIPERX0STATUS1
TCELL34:IMUX.IMUX21.DELAYPCIE.PIPERX0STATUS2
TCELL34:IMUX.IMUX23.DELAYPCIE.PIPERX0STATUS0
TCELL34:OUT0.TMINPCIE.TRNRD32
TCELL34:OUT1.TMINPCIE.PIPETX0ELECIDLE
TCELL34:OUT2.TMINPCIE.TRNRD33
TCELL34:OUT3.TMINPCIE.TRNRD34
TCELL34:OUT4.TMINPCIE.TRNRD35
TCELL34:OUT5.TMINPCIE.PIPETX4ELECIDLE
TCELL34:OUT6.TMINPCIE.MIMTXWDATA35
TCELL34:OUT7.TMINPCIE.MIMTXWDATA36
TCELL34:OUT8.TMINPCIE.MIMTXWDATA37
TCELL34:OUT9.TMINPCIE.MIMTXWDATA38
TCELL34:OUT10.TMINPCIE.MIMRXWADDR0
TCELL34:OUT11.TMINPCIE.MIMRXWADDR1
TCELL34:OUT12.TMINPCIE.MIMRXWADDR2
TCELL34:OUT13.TMINPCIE.MIMRXWADDR3
TCELL34:OUT14.TMINPCIE.CFGDO30
TCELL34:OUT15.TMINPCIE.DBGSCLRG
TCELL34:OUT16.TMINPCIE.DBGSCLRH
TCELL34:OUT17.TMINPCIE.PIPETX4POWERDOWN0
TCELL34:OUT18.TMINPCIE.DBGVECB10
TCELL34:OUT19.TMINPCIE.PIPETX4POWERDOWN1
TCELL34:OUT20.TMINPCIE.DBGVECB11
TCELL34:OUT21.TMINPCIE.PIPETX0POWERDOWN0
TCELL34:OUT22.TMINPCIE.DBGVECB12
TCELL34:OUT23.TMINPCIE.PIPETX0POWERDOWN1
TCELL35:IMUX.IMUX0.DELAYPCIE.TRNTD38
TCELL35:IMUX.IMUX1.DELAYPCIE.TRNTD39
TCELL35:IMUX.IMUX2.DELAYPCIE.TRNTD40
TCELL35:IMUX.IMUX3.DELAYPCIE.TRNTD41
TCELL35:IMUX.IMUX4.DELAYPCIE.MIMRXRDATA22
TCELL35:IMUX.IMUX5.DELAYPCIE.PIPERX4ELECIDLE
TCELL35:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA23
TCELL35:IMUX.IMUX7.DELAYPCIE.MIMRXRDATA24
TCELL35:IMUX.IMUX8.DELAYPCIE.MIMRXRDATA25
TCELL35:IMUX.IMUX9.DELAYPCIE.SCANIN3
TCELL35:IMUX.IMUX10.DELAYPCIE.CFGERRAERHEADERLOG97
TCELL35:IMUX.IMUX11.DELAYPCIE.PIPERX4VALID
TCELL35:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG98
TCELL35:IMUX.IMUX13.DELAYPCIE.CFGERRAERHEADERLOG99
TCELL35:IMUX.IMUX14.DELAYPCIE.CFGERRAERHEADERLOG100
TCELL35:IMUX.IMUX15.DELAYPCIE.CFGDSN18
TCELL35:IMUX.IMUX16.DELAYPCIE.CFGDSN19
TCELL35:IMUX.IMUX17.DELAYPCIE.CFGDSN20
TCELL35:IMUX.IMUX18.DELAYPCIE.CFGDSN21
TCELL35:IMUX.IMUX19.DELAYPCIE.PIPERX0VALID
TCELL35:IMUX.IMUX20.DELAYPCIE.DRPDADDR5
TCELL35:IMUX.IMUX21.DELAYPCIE.PIPERX0ELECIDLE
TCELL35:OUT0.TMINPCIE.TRNRD36
TCELL35:OUT1.TMINPCIE.TRNRD37
TCELL35:OUT2.TMINPCIE.TRNRD38
TCELL35:OUT3.TMINPCIE.TRNRD39
TCELL35:OUT4.TMINPCIE.MIMTXWDATA39
TCELL35:OUT5.TMINPCIE.MIMTXWDATA40
TCELL35:OUT6.TMINPCIE.MIMTXWDATA41
TCELL35:OUT7.TMINPCIE.MIMTXWDATA42
TCELL35:OUT8.TMINPCIE.MIMRXWADDR4
TCELL35:OUT9.TMINPCIE.MIMRXWADDR5
TCELL35:OUT10.TMINPCIE.MIMRXWADDR6
TCELL35:OUT11.TMINPCIE.MIMRXWADDR7
TCELL35:OUT12.TMINPCIE.CFGDO31
TCELL35:OUT13.TMINPCIE.DBGSCLRI
TCELL35:OUT14.TMINPCIE.DBGSCLRJ
TCELL35:OUT15.TMINPCIE.DBGSCLRK
TCELL35:OUT16.TMINPCIE.PIPETX0COMPLIANCE
TCELL35:OUT17.TMINPCIE.DBGVECB13
TCELL35:OUT18.TMINPCIE.PIPETX0CHARISK0
TCELL35:OUT19.TMINPCIE.PIPETX4CHARISK1
TCELL35:OUT20.TMINPCIE.PIPETX4COMPLIANCE
TCELL35:OUT21.TMINPCIE.DBGVECB14
TCELL35:OUT22.TMINPCIE.PIPETX4CHARISK0
TCELL35:OUT23.TMINPCIE.PIPETX0CHARISK1
TCELL36:IMUX.IMUX0.DELAYPCIE.TRNTD42
TCELL36:IMUX.IMUX1.DELAYPCIE.TRNTD43
TCELL36:IMUX.IMUX2.DELAYPCIE.TRNTD44
TCELL36:IMUX.IMUX3.DELAYPCIE.TRNTD45
TCELL36:IMUX.IMUX4.DELAYPCIE.MIMRXRDATA26
TCELL36:IMUX.IMUX5.DELAYPCIE.MIMRXRDATA27
TCELL36:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA28
TCELL36:IMUX.IMUX7.DELAYPCIE.MIMRXRDATA29
TCELL36:IMUX.IMUX8.DELAYPCIE.SCANIN4
TCELL36:IMUX.IMUX9.DELAYPCIE.CFGERRAERHEADERLOG101
TCELL36:IMUX.IMUX10.DELAYPCIE.CFGERRAERHEADERLOG102
TCELL36:IMUX.IMUX11.DELAYPCIE.CFGERRAERHEADERLOG103
TCELL36:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG104
TCELL36:IMUX.IMUX13.DELAYPCIE.CFGDSN22
TCELL36:IMUX.IMUX14.DELAYPCIE.CFGDSN23
TCELL36:IMUX.IMUX15.DELAYPCIE.CFGDSN24
TCELL36:IMUX.IMUX16.DELAYPCIE.CFGDSN25
TCELL36:IMUX.IMUX17.DELAYPCIE.DRPDADDR6
TCELL36:IMUX.IMUX18.DELAYPCIE.DRPDADDR7
TCELL36:IMUX.IMUX19.DELAYPCIE.DRPDADDR8
TCELL36:IMUX.IMUX20.DELAYPCIE.DRPDI0
TCELL36:IMUX.IMUX21.DELAYPCIE.DBGSUBMODE
TCELL36:OUT0.TMINPCIE.TRNRD40
TCELL36:OUT1.TMINPCIE.TRNRD41
TCELL36:OUT2.TMINPCIE.PIPETX4DATA13
TCELL36:OUT3.TMINPCIE.TRNRD42
TCELL36:OUT4.TMINPCIE.TRNRD43
TCELL36:OUT5.TMINPCIE.MIMTXWDATA43
TCELL36:OUT6.TMINPCIE.PIPETX0DATA13
TCELL36:OUT7.TMINPCIE.MIMTXWDATA44
TCELL36:OUT8.TMINPCIE.CFGRDWRDONEN
TCELL36:OUT9.TMINPCIE.MIMRXWADDR8
TCELL36:OUT10.TMINPCIE.MIMRXWADDR9
TCELL36:OUT11.TMINPCIE.MIMRXWADDR10
TCELL36:OUT12.TMINPCIE.MIMRXWADDR11
TCELL36:OUT13.TMINPCIE.DBGVECB15
TCELL36:OUT14.TMINPCIE.DBGVECB16
TCELL36:OUT15.TMINPCIE.DBGVECB17
TCELL36:OUT16.TMINPCIE.PIPETX0DATA12
TCELL36:OUT17.TMINPCIE.PIPETX4DATA15
TCELL36:OUT18.TMINPCIE.DBGVECB18
TCELL36:OUT19.TMINPCIE.PIPETX4DATA14
TCELL36:OUT20.TMINPCIE.PIPETX4DATA12
TCELL36:OUT21.TMINPCIE.PIPETX0DATA15
TCELL36:OUT22.TMINPCIE.PLDBGVEC0
TCELL36:OUT23.TMINPCIE.PIPETX0DATA14
TCELL37:IMUX.IMUX0.DELAYPCIE.TRNTD46
TCELL37:IMUX.IMUX1.DELAYPCIE.TRNTD47
TCELL37:IMUX.IMUX2.DELAYPCIE.TRNTD48
TCELL37:IMUX.IMUX3.DELAYPCIE.TRNTD49
TCELL37:IMUX.IMUX4.DELAYPCIE.MIMRXRDATA30
TCELL37:IMUX.IMUX5.DELAYPCIE.MIMRXRDATA31
TCELL37:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA32
TCELL37:IMUX.IMUX7.DELAYPCIE.MIMRXRDATA33
TCELL37:IMUX.IMUX8.DELAYPCIE.SCANIN5
TCELL37:IMUX.IMUX9.DELAYPCIE.CFGERRAERHEADERLOG105
TCELL37:IMUX.IMUX10.DELAYPCIE.CFGERRAERHEADERLOG106
TCELL37:IMUX.IMUX11.DELAYPCIE.CFGERRAERHEADERLOG107
TCELL37:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG108
TCELL37:IMUX.IMUX13.DELAYPCIE.CFGDSN26
TCELL37:IMUX.IMUX14.DELAYPCIE.CFGDSN27
TCELL37:IMUX.IMUX15.DELAYPCIE.CFGDSN28
TCELL37:IMUX.IMUX16.DELAYPCIE.CFGDSN29
TCELL37:IMUX.IMUX17.DELAYPCIE.DRPDI1
TCELL37:IMUX.IMUX18.DELAYPCIE.DRPDI2
TCELL37:IMUX.IMUX19.DELAYPCIE.DRPDI3
TCELL37:IMUX.IMUX20.DELAYPCIE.DRPDI4
TCELL37:IMUX.IMUX21.DELAYPCIE.PLDBGMODE0
TCELL37:OUT0.TMINPCIE.TRNRD44
TCELL37:OUT1.TMINPCIE.PIPETX0DATA11
TCELL37:OUT2.TMINPCIE.PIPETX4DATA8
TCELL37:OUT3.TMINPCIE.TRNRD45
TCELL37:OUT4.TMINPCIE.CFGERRAERHEADERLOGSETN
TCELL37:OUT5.TMINPCIE.PIPETX4DATA11
TCELL37:OUT6.TMINPCIE.PIPETX0DATA8
TCELL37:OUT7.TMINPCIE.MIMRXWADDR12
TCELL37:OUT8.TMINPCIE.MIMRXWEN
TCELL37:OUT9.TMINPCIE.MIMRXRADDR0
TCELL37:OUT10.TMINPCIE.MIMRXRADDR1
TCELL37:OUT11.TMINPCIE.DBGVECB19
TCELL37:OUT12.TMINPCIE.DBGVECB20
TCELL37:OUT13.TMINPCIE.DBGVECB21
TCELL37:OUT14.TMINPCIE.DBGVECB22
TCELL37:OUT15.TMINPCIE.PLDBGVEC1
TCELL37:OUT16.TMINPCIE.PIPETX0DATA7
TCELL37:OUT17.TMINPCIE.PIPETX4DATA10
TCELL37:OUT18.TMINPCIE.PIPETX0DATA6
TCELL37:OUT19.TMINPCIE.PIPETX4DATA9
TCELL37:OUT20.TMINPCIE.PIPETX4DATA7
TCELL37:OUT21.TMINPCIE.PIPETX0DATA10
TCELL37:OUT22.TMINPCIE.PIPETX4DATA6
TCELL37:OUT23.TMINPCIE.PIPETX0DATA9
TCELL38:IMUX.IMUX0.DELAYPCIE.TRNTD50
TCELL38:IMUX.IMUX1.DELAYPCIE.TRNTD51
TCELL38:IMUX.IMUX2.DELAYPCIE.TRNTD52
TCELL38:IMUX.IMUX3.DELAYPCIE.TRNTD53
TCELL38:IMUX.IMUX4.DELAYPCIE.MIMRXRDATA34
TCELL38:IMUX.IMUX5.DELAYPCIE.MIMRXRDATA35
TCELL38:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA36
TCELL38:IMUX.IMUX7.DELAYPCIE.MIMRXRDATA37
TCELL38:IMUX.IMUX8.DELAYPCIE.SCANIN6
TCELL38:IMUX.IMUX9.DELAYPCIE.CFGERRAERHEADERLOG109
TCELL38:IMUX.IMUX10.DELAYPCIE.CFGERRAERHEADERLOG110
TCELL38:IMUX.IMUX11.DELAYPCIE.CFGERRAERHEADERLOG111
TCELL38:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG112
TCELL38:IMUX.IMUX13.DELAYPCIE.CFGDSN30
TCELL38:IMUX.IMUX14.DELAYPCIE.CFGDSN31
TCELL38:IMUX.IMUX15.DELAYPCIE.CFGDSN32
TCELL38:IMUX.IMUX16.DELAYPCIE.CFGDSN33
TCELL38:IMUX.IMUX17.DELAYPCIE.DRPDI5
TCELL38:IMUX.IMUX18.DELAYPCIE.DRPDI6
TCELL38:IMUX.IMUX19.DELAYPCIE.DRPDI7
TCELL38:IMUX.IMUX20.DELAYPCIE.DRPDI8
TCELL38:IMUX.IMUX21.DELAYPCIE.PLDBGMODE1
TCELL38:OUT0.TMINPCIE.TRNRD46
TCELL38:OUT1.TMINPCIE.PIPETX0DATA3
TCELL38:OUT2.TMINPCIE.PIPETX4DATA4
TCELL38:OUT3.TMINPCIE.TRNRD47
TCELL38:OUT4.TMINPCIE.CFGERRCPLRDYN
TCELL38:OUT5.TMINPCIE.PIPETX4DATA3
TCELL38:OUT6.TMINPCIE.PIPETX0DATA4
TCELL38:OUT7.TMINPCIE.MIMRXRADDR2
TCELL38:OUT8.TMINPCIE.MIMRXRADDR3
TCELL38:OUT9.TMINPCIE.MIMRXRADDR4
TCELL38:OUT10.TMINPCIE.MIMRXRADDR5
TCELL38:OUT11.TMINPCIE.DBGVECB23
TCELL38:OUT12.TMINPCIE.DBGVECB24
TCELL38:OUT13.TMINPCIE.DBGVECB25
TCELL38:OUT14.TMINPCIE.DBGVECB26
TCELL38:OUT15.TMINPCIE.PLDBGVEC2
TCELL38:OUT16.TMINPCIE.PIPETX0DATA0
TCELL38:OUT17.TMINPCIE.PIPETX4DATA1
TCELL38:OUT18.TMINPCIE.PIPETX0DATA5
TCELL38:OUT19.TMINPCIE.PIPETX4DATA2
TCELL38:OUT20.TMINPCIE.PIPETX4DATA0
TCELL38:OUT21.TMINPCIE.PIPETX0DATA1
TCELL38:OUT22.TMINPCIE.PIPETX4DATA5
TCELL38:OUT23.TMINPCIE.PIPETX0DATA2
TCELL39:IMUX.IMUX0.DELAYPCIE.TRNTD54
TCELL39:IMUX.IMUX1.DELAYPCIE.TRNTD55
TCELL39:IMUX.IMUX2.DELAYPCIE.TRNTD56
TCELL39:IMUX.IMUX3.DELAYPCIE.TRNTD57
TCELL39:IMUX.IMUX4.DELAYPCIE.MIMRXRDATA38
TCELL39:IMUX.IMUX5.DELAYPCIE.MIMRXRDATA39
TCELL39:IMUX.IMUX6.DELAYPCIE.MIMRXRDATA40
TCELL39:IMUX.IMUX7.DELAYPCIE.MIMRXRDATA41
TCELL39:IMUX.IMUX8.DELAYPCIE.SCANIN7
TCELL39:IMUX.IMUX9.DELAYPCIE.CFGERRAERHEADERLOG113
TCELL39:IMUX.IMUX10.DELAYPCIE.CFGERRAERHEADERLOG114
TCELL39:IMUX.IMUX11.DELAYPCIE.CFGERRAERHEADERLOG115
TCELL39:IMUX.IMUX12.DELAYPCIE.CFGERRAERHEADERLOG116
TCELL39:IMUX.IMUX13.DELAYPCIE.CFGDSN34
TCELL39:IMUX.IMUX14.DELAYPCIE.CFGDSN35
TCELL39:IMUX.IMUX15.DELAYPCIE.CFGDSN36
TCELL39:IMUX.IMUX16.DELAYPCIE.CFGDSN37
TCELL39:IMUX.IMUX17.DELAYPCIE.DRPDI9
TCELL39:IMUX.IMUX18.DELAYPCIE.DRPDI10
TCELL39:IMUX.IMUX19.DELAYPCIE.DRPDI11
TCELL39:IMUX.IMUX20.DELAYPCIE.DRPDI12
TCELL39:IMUX.IMUX21.DELAYPCIE.PLDBGMODE2
TCELL39:OUT0.TMINPCIE.TRNRD48
TCELL39:OUT1.TMINPCIE.TRNRD49
TCELL39:OUT2.TMINPCIE.TRNRD50
TCELL39:OUT3.TMINPCIE.TRNRD51
TCELL39:OUT4.TMINPCIE.MIMTXWDATA45
TCELL39:OUT5.TMINPCIE.MIMTXWDATA46
TCELL39:OUT6.TMINPCIE.MIMTXWDATA47
TCELL39:OUT7.TMINPCIE.MIMTXWDATA48
TCELL39:OUT8.TMINPCIE.MIMRXRADDR6
TCELL39:OUT9.TMINPCIE.MIMRXRADDR7
TCELL39:OUT10.TMINPCIE.MIMRXRADDR8
TCELL39:OUT11.TMINPCIE.MIMRXRADDR9
TCELL39:OUT12.TMINPCIE.CFGINTERRUPTRDYN
TCELL39:OUT13.TMINPCIE.CFGINTERRUPTMMENABLE0
TCELL39:OUT14.TMINPCIE.CFGINTERRUPTMMENABLE1
TCELL39:OUT15.TMINPCIE.CFGINTERRUPTMMENABLE2
TCELL39:OUT16.TMINPCIE.CFGLINKSTATUSNEGOTIATEDWIDTH0
TCELL39:OUT17.TMINPCIE.CFGLINKSTATUSNEGOTIATEDWIDTH1
TCELL39:OUT18.TMINPCIE.CFGLINKSTATUSNEGOTIATEDWIDTH2
TCELL39:OUT19.TMINPCIE.PLDBGVEC3
TCELL39:OUT20.TMINPCIE.PLDBGVEC4
TCELL39:OUT21.TMINPCIE.DBGVECB27
TCELL39:OUT22.TMINPCIE.DBGVECB28
TCELL39:OUT23.TMINPCIE.DBGVECB29

Bitstream

virtex6 PCIE bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR0[14] PCIE:DRP05[14] PCIE:BAR0[15] PCIE:DRP05[15]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR0[12] PCIE:DRP05[12] PCIE:BAR0[13] PCIE:DRP05[13]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR0[10] PCIE:DRP05[10] PCIE:BAR0[11] PCIE:DRP05[11]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR0[8] PCIE:DRP05[8] PCIE:BAR0[9] PCIE:DRP05[9]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR0[6] PCIE:DRP05[6] PCIE:BAR0[7] PCIE:DRP05[7]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR0[4] PCIE:DRP05[4] PCIE:BAR0[5] PCIE:DRP05[5]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR0[2] PCIE:DRP05[2] PCIE:BAR0[3] PCIE:DRP05[3]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR0[0] PCIE:DRP05[0] PCIE:BAR0[1] PCIE:DRP05[1]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP04[14] PCIE:DRP04[15]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_ON PCIE:DRP04[12] PCIE:DRP04[13]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_NEXTPTR[10] PCIE:DRP04[10] PCIE:AER_CAP_NEXTPTR[11] PCIE:DRP04[11]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_NEXTPTR[8] PCIE:DRP04[8] PCIE:AER_CAP_NEXTPTR[9] PCIE:DRP04[9]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_NEXTPTR[6] PCIE:DRP04[6] PCIE:AER_CAP_NEXTPTR[7] PCIE:DRP04[7]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_NEXTPTR[4] PCIE:DRP04[4] PCIE:AER_CAP_NEXTPTR[5] PCIE:DRP04[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_NEXTPTR[2] PCIE:DRP04[2] PCIE:AER_CAP_NEXTPTR[3] PCIE:DRP04[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_NEXTPTR[0] PCIE:DRP04[0] PCIE:AER_CAP_NEXTPTR[1] PCIE:DRP04[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP03[14] PCIE:DRP03[15]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP03[12] PCIE:DRP03[13]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_BASE_PTR[10] PCIE:DRP03[10] PCIE:AER_BASE_PTR[11] PCIE:DRP03[11]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_BASE_PTR[8] PCIE:DRP03[8] PCIE:AER_BASE_PTR[9] PCIE:DRP03[9]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_BASE_PTR[6] PCIE:DRP03[6] PCIE:AER_BASE_PTR[7] PCIE:DRP03[7]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_BASE_PTR[4] PCIE:DRP03[4] PCIE:AER_BASE_PTR[5] PCIE:DRP03[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_BASE_PTR[2] PCIE:DRP03[2] PCIE:AER_BASE_PTR[3] PCIE:DRP03[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_BASE_PTR[0] PCIE:DRP03[0] PCIE:AER_BASE_PTR[1] PCIE:DRP03[1]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_VERSION[3] PCIE:DRP02[14] PCIE:DRP02[15]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_VERSION[1] PCIE:DRP02[12] PCIE:AER_CAP_VERSION[2] PCIE:DRP02[13]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_PERMIT_ROOTERR_UPDATE PCIE:DRP02[10] PCIE:AER_CAP_VERSION[0] PCIE:DRP02[11]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_INT_MSG_NUM_MSIX[3] PCIE:DRP02[8] PCIE:AER_CAP_INT_MSG_NUM_MSIX[4] PCIE:DRP02[9]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_INT_MSG_NUM_MSIX[1] PCIE:DRP02[6] PCIE:AER_CAP_INT_MSG_NUM_MSIX[2] PCIE:DRP02[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_INT_MSG_NUM_MSI[4] PCIE:DRP02[4] PCIE:AER_CAP_INT_MSG_NUM_MSIX[0] PCIE:DRP02[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_INT_MSG_NUM_MSI[2] PCIE:DRP02[2] PCIE:AER_CAP_INT_MSG_NUM_MSI[3] PCIE:DRP02[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_INT_MSG_NUM_MSI[0] PCIE:DRP02[0] PCIE:AER_CAP_INT_MSG_NUM_MSI[1] PCIE:DRP02[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_ID[14] PCIE:DRP01[14] PCIE:AER_CAP_ID[15] PCIE:DRP01[15]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_ID[12] PCIE:DRP01[12] PCIE:AER_CAP_ID[13] PCIE:DRP01[13]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_ID[10] PCIE:DRP01[10] PCIE:AER_CAP_ID[11] PCIE:DRP01[11]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_ID[8] PCIE:DRP01[8] PCIE:AER_CAP_ID[9] PCIE:DRP01[9]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_ID[6] PCIE:DRP01[6] PCIE:AER_CAP_ID[7] PCIE:DRP01[7]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_ID[4] PCIE:DRP01[4] PCIE:AER_CAP_ID[5] PCIE:DRP01[5]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_ID[2] PCIE:DRP01[2] PCIE:AER_CAP_ID[3] PCIE:DRP01[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_ID[0] PCIE:DRP01[0] PCIE:AER_CAP_ID[1] PCIE:DRP01[1]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP00[14] PCIE:DRP00[15]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP00[12] PCIE:DRP00[13]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP00[10] PCIE:DRP00[11]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP00[8] PCIE:DRP00[9]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP00[6] PCIE:DRP00[7]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP00[4] PCIE:DRP00[5]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP00[2] PCIE:DRP00[3]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:AER_CAP_ECRC_CHECK_CAPABLE PCIE:DRP00[0] PCIE:AER_CAP_ECRC_GEN_CAPABLE PCIE:DRP00[1]
virtex6 PCIE bittile 1
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR3[14] PCIE:DRP0B[14] PCIE:BAR3[15] PCIE:DRP0B[15]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR3[12] PCIE:DRP0B[12] PCIE:BAR3[13] PCIE:DRP0B[13]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR3[10] PCIE:DRP0B[10] PCIE:BAR3[11] PCIE:DRP0B[11]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR3[8] PCIE:DRP0B[8] PCIE:BAR3[9] PCIE:DRP0B[9]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR3[6] PCIE:DRP0B[6] PCIE:BAR3[7] PCIE:DRP0B[7]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR3[4] PCIE:DRP0B[4] PCIE:BAR3[5] PCIE:DRP0B[5]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR3[2] PCIE:DRP0B[2] PCIE:BAR3[3] PCIE:DRP0B[3]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR3[0] PCIE:DRP0B[0] PCIE:BAR3[1] PCIE:DRP0B[1]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR2[30] PCIE:DRP0A[14] PCIE:BAR2[31] PCIE:DRP0A[15]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR2[28] PCIE:DRP0A[12] PCIE:BAR2[29] PCIE:DRP0A[13]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR2[26] PCIE:DRP0A[10] PCIE:BAR2[27] PCIE:DRP0A[11]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR2[24] PCIE:DRP0A[8] PCIE:BAR2[25] PCIE:DRP0A[9]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR2[22] PCIE:DRP0A[6] PCIE:BAR2[23] PCIE:DRP0A[7]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR2[20] PCIE:DRP0A[4] PCIE:BAR2[21] PCIE:DRP0A[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR2[18] PCIE:DRP0A[2] PCIE:BAR2[19] PCIE:DRP0A[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR2[16] PCIE:DRP0A[0] PCIE:BAR2[17] PCIE:DRP0A[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR2[14] PCIE:DRP09[14] PCIE:BAR2[15] PCIE:DRP09[15]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR2[12] PCIE:DRP09[12] PCIE:BAR2[13] PCIE:DRP09[13]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR2[10] PCIE:DRP09[10] PCIE:BAR2[11] PCIE:DRP09[11]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR2[8] PCIE:DRP09[8] PCIE:BAR2[9] PCIE:DRP09[9]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR2[6] PCIE:DRP09[6] PCIE:BAR2[7] PCIE:DRP09[7]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR2[4] PCIE:DRP09[4] PCIE:BAR2[5] PCIE:DRP09[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR2[2] PCIE:DRP09[2] PCIE:BAR2[3] PCIE:DRP09[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR2[0] PCIE:DRP09[0] PCIE:BAR2[1] PCIE:DRP09[1]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR1[30] PCIE:DRP08[14] PCIE:BAR1[31] PCIE:DRP08[15]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR1[28] PCIE:DRP08[12] PCIE:BAR1[29] PCIE:DRP08[13]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR1[26] PCIE:DRP08[10] PCIE:BAR1[27] PCIE:DRP08[11]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR1[24] PCIE:DRP08[8] PCIE:BAR1[25] PCIE:DRP08[9]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR1[22] PCIE:DRP08[6] PCIE:BAR1[23] PCIE:DRP08[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR1[20] PCIE:DRP08[4] PCIE:BAR1[21] PCIE:DRP08[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR1[18] PCIE:DRP08[2] PCIE:BAR1[19] PCIE:DRP08[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR1[16] PCIE:DRP08[0] PCIE:BAR1[17] PCIE:DRP08[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR1[14] PCIE:DRP07[14] PCIE:BAR1[15] PCIE:DRP07[15]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR1[12] PCIE:DRP07[12] PCIE:BAR1[13] PCIE:DRP07[13]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR1[10] PCIE:DRP07[10] PCIE:BAR1[11] PCIE:DRP07[11]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR1[8] PCIE:DRP07[8] PCIE:BAR1[9] PCIE:DRP07[9]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR1[6] PCIE:DRP07[6] PCIE:BAR1[7] PCIE:DRP07[7]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR1[4] PCIE:DRP07[4] PCIE:BAR1[5] PCIE:DRP07[5]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR1[2] PCIE:DRP07[2] PCIE:BAR1[3] PCIE:DRP07[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR1[0] PCIE:DRP07[0] PCIE:BAR1[1] PCIE:DRP07[1]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR0[30] PCIE:DRP06[14] PCIE:BAR0[31] PCIE:DRP06[15]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR0[28] PCIE:DRP06[12] PCIE:BAR0[29] PCIE:DRP06[13]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR0[26] PCIE:DRP06[10] PCIE:BAR0[27] PCIE:DRP06[11]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR0[24] PCIE:DRP06[8] PCIE:BAR0[25] PCIE:DRP06[9]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR0[22] PCIE:DRP06[6] PCIE:BAR0[23] PCIE:DRP06[7]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR0[20] PCIE:DRP06[4] PCIE:BAR0[21] PCIE:DRP06[5]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR0[18] PCIE:DRP06[2] PCIE:BAR0[19] PCIE:DRP06[3]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR0[16] PCIE:DRP06[0] PCIE:BAR0[17] PCIE:DRP06[1]
virtex6 PCIE bittile 2
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP11[14] PCIE:EXPANSION_ROM[14] PCIE:DRP11[15] PCIE:EXPANSION_ROM[15]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP11[12] PCIE:EXPANSION_ROM[12] PCIE:DRP11[13] PCIE:EXPANSION_ROM[13]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP11[10] PCIE:EXPANSION_ROM[10] PCIE:DRP11[11] PCIE:EXPANSION_ROM[11]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP11[8] PCIE:EXPANSION_ROM[8] PCIE:DRP11[9] PCIE:EXPANSION_ROM[9]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP11[6] PCIE:EXPANSION_ROM[6] PCIE:DRP11[7] PCIE:EXPANSION_ROM[7]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP11[4] PCIE:EXPANSION_ROM[4] PCIE:DRP11[5] PCIE:EXPANSION_ROM[5]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP11[2] PCIE:EXPANSION_ROM[2] PCIE:DRP11[3] PCIE:EXPANSION_ROM[3]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP11[0] PCIE:EXPANSION_ROM[0] PCIE:DRP11[1] PCIE:EXPANSION_ROM[1]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR5[30] PCIE:DRP10[14] PCIE:BAR5[31] PCIE:DRP10[15]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR5[28] PCIE:DRP10[12] PCIE:BAR5[29] PCIE:DRP10[13]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR5[26] PCIE:DRP10[10] PCIE:BAR5[27] PCIE:DRP10[11]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR5[24] PCIE:DRP10[8] PCIE:BAR5[25] PCIE:DRP10[9]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR5[22] PCIE:DRP10[6] PCIE:BAR5[23] PCIE:DRP10[7]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR5[20] PCIE:DRP10[4] PCIE:BAR5[21] PCIE:DRP10[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR5[18] PCIE:DRP10[2] PCIE:BAR5[19] PCIE:DRP10[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR5[16] PCIE:DRP10[0] PCIE:BAR5[17] PCIE:DRP10[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR5[14] PCIE:DRP0F[14] PCIE:BAR5[15] PCIE:DRP0F[15]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR5[12] PCIE:DRP0F[12] PCIE:BAR5[13] PCIE:DRP0F[13]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR5[10] PCIE:DRP0F[10] PCIE:BAR5[11] PCIE:DRP0F[11]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR5[8] PCIE:DRP0F[8] PCIE:BAR5[9] PCIE:DRP0F[9]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR5[6] PCIE:DRP0F[6] PCIE:BAR5[7] PCIE:DRP0F[7]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR5[4] PCIE:DRP0F[4] PCIE:BAR5[5] PCIE:DRP0F[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR5[2] PCIE:DRP0F[2] PCIE:BAR5[3] PCIE:DRP0F[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR5[0] PCIE:DRP0F[0] PCIE:BAR5[1] PCIE:DRP0F[1]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR4[30] PCIE:DRP0E[14] PCIE:BAR4[31] PCIE:DRP0E[15]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR4[28] PCIE:DRP0E[12] PCIE:BAR4[29] PCIE:DRP0E[13]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR4[26] PCIE:DRP0E[10] PCIE:BAR4[27] PCIE:DRP0E[11]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR4[24] PCIE:DRP0E[8] PCIE:BAR4[25] PCIE:DRP0E[9]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR4[22] PCIE:DRP0E[6] PCIE:BAR4[23] PCIE:DRP0E[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR4[20] PCIE:DRP0E[4] PCIE:BAR4[21] PCIE:DRP0E[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR4[18] PCIE:DRP0E[2] PCIE:BAR4[19] PCIE:DRP0E[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR4[16] PCIE:DRP0E[0] PCIE:BAR4[17] PCIE:DRP0E[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR4[14] PCIE:DRP0D[14] PCIE:BAR4[15] PCIE:DRP0D[15]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR4[12] PCIE:DRP0D[12] PCIE:BAR4[13] PCIE:DRP0D[13]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR4[10] PCIE:DRP0D[10] PCIE:BAR4[11] PCIE:DRP0D[11]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR4[8] PCIE:DRP0D[8] PCIE:BAR4[9] PCIE:DRP0D[9]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR4[6] PCIE:DRP0D[6] PCIE:BAR4[7] PCIE:DRP0D[7]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR4[4] PCIE:DRP0D[4] PCIE:BAR4[5] PCIE:DRP0D[5]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR4[2] PCIE:DRP0D[2] PCIE:BAR4[3] PCIE:DRP0D[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR4[0] PCIE:DRP0D[0] PCIE:BAR4[1] PCIE:DRP0D[1]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR3[30] PCIE:DRP0C[14] PCIE:BAR3[31] PCIE:DRP0C[15]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR3[28] PCIE:DRP0C[12] PCIE:BAR3[29] PCIE:DRP0C[13]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR3[26] PCIE:DRP0C[10] PCIE:BAR3[27] PCIE:DRP0C[11]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR3[24] PCIE:DRP0C[8] PCIE:BAR3[25] PCIE:DRP0C[9]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR3[22] PCIE:DRP0C[6] PCIE:BAR3[23] PCIE:DRP0C[7]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR3[20] PCIE:DRP0C[4] PCIE:BAR3[21] PCIE:DRP0C[5]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR3[18] PCIE:DRP0C[2] PCIE:BAR3[19] PCIE:DRP0C[3]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:BAR3[16] PCIE:DRP0C[0] PCIE:BAR3[17] PCIE:DRP0C[1]
virtex6 PCIE bittile 3
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE PCIE:DRP17[14] PCIE:DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE PCIE:DRP17[15]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CPL_TIMEOUT_RANGES_SUPPORTED[2] PCIE:DRP17[12] PCIE:CPL_TIMEOUT_RANGES_SUPPORTED[3] PCIE:DRP17[13]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CPL_TIMEOUT_RANGES_SUPPORTED[0] PCIE:DRP17[10] PCIE:CPL_TIMEOUT_RANGES_SUPPORTED[1] PCIE:DRP17[11]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CMD_INTX_IMPLEMENTED PCIE:DRP17[8] PCIE:CPL_TIMEOUT_DISABLE_SUPPORTED PCIE:DRP17[9]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CLASS_CODE[22] PCIE:DRP17[6] PCIE:CLASS_CODE[23] PCIE:DRP17[7]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CLASS_CODE[20] PCIE:DRP17[4] PCIE:CLASS_CODE[21] PCIE:DRP17[5]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CLASS_CODE[18] PCIE:DRP17[2] PCIE:CLASS_CODE[19] PCIE:DRP17[3]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CLASS_CODE[16] PCIE:DRP17[0] PCIE:CLASS_CODE[17] PCIE:DRP17[1]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CLASS_CODE[14] PCIE:DRP16[14] PCIE:CLASS_CODE[15] PCIE:DRP16[15]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CLASS_CODE[12] PCIE:DRP16[12] PCIE:CLASS_CODE[13] PCIE:DRP16[13]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CLASS_CODE[10] PCIE:DRP16[10] PCIE:CLASS_CODE[11] PCIE:DRP16[11]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CLASS_CODE[8] PCIE:DRP16[8] PCIE:CLASS_CODE[9] PCIE:DRP16[9]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CLASS_CODE[6] PCIE:DRP16[6] PCIE:CLASS_CODE[7] PCIE:DRP16[7]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CLASS_CODE[4] PCIE:DRP16[4] PCIE:CLASS_CODE[5] PCIE:DRP16[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CLASS_CODE[2] PCIE:DRP16[2] PCIE:CLASS_CODE[3] PCIE:DRP16[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CLASS_CODE[0] PCIE:DRP16[0] PCIE:CLASS_CODE[1] PCIE:DRP16[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CARDBUS_CIS_POINTER[30] PCIE:DRP15[14] PCIE:CARDBUS_CIS_POINTER[31] PCIE:DRP15[15]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CARDBUS_CIS_POINTER[28] PCIE:DRP15[12] PCIE:CARDBUS_CIS_POINTER[29] PCIE:DRP15[13]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CARDBUS_CIS_POINTER[26] PCIE:DRP15[10] PCIE:CARDBUS_CIS_POINTER[27] PCIE:DRP15[11]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CARDBUS_CIS_POINTER[24] PCIE:DRP15[8] PCIE:CARDBUS_CIS_POINTER[25] PCIE:DRP15[9]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CARDBUS_CIS_POINTER[22] PCIE:DRP15[6] PCIE:CARDBUS_CIS_POINTER[23] PCIE:DRP15[7]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CARDBUS_CIS_POINTER[20] PCIE:DRP15[4] PCIE:CARDBUS_CIS_POINTER[21] PCIE:DRP15[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CARDBUS_CIS_POINTER[18] PCIE:DRP15[2] PCIE:CARDBUS_CIS_POINTER[19] PCIE:DRP15[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CARDBUS_CIS_POINTER[16] PCIE:DRP15[0] PCIE:CARDBUS_CIS_POINTER[17] PCIE:DRP15[1]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CARDBUS_CIS_POINTER[14] PCIE:DRP14[14] PCIE:CARDBUS_CIS_POINTER[15] PCIE:DRP14[15]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CARDBUS_CIS_POINTER[12] PCIE:DRP14[12] PCIE:CARDBUS_CIS_POINTER[13] PCIE:DRP14[13]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CARDBUS_CIS_POINTER[10] PCIE:DRP14[10] PCIE:CARDBUS_CIS_POINTER[11] PCIE:DRP14[11]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CARDBUS_CIS_POINTER[8] PCIE:DRP14[8] PCIE:CARDBUS_CIS_POINTER[9] PCIE:DRP14[9]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CARDBUS_CIS_POINTER[6] PCIE:DRP14[6] PCIE:CARDBUS_CIS_POINTER[7] PCIE:DRP14[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CARDBUS_CIS_POINTER[4] PCIE:DRP14[4] PCIE:CARDBUS_CIS_POINTER[5] PCIE:DRP14[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CARDBUS_CIS_POINTER[2] PCIE:DRP14[2] PCIE:CARDBUS_CIS_POINTER[3] PCIE:DRP14[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CARDBUS_CIS_POINTER[0] PCIE:DRP14[0] PCIE:CARDBUS_CIS_POINTER[1] PCIE:DRP14[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP13[14] PCIE:DRP13[15]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP13[12] PCIE:DRP13[13]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP13[10] PCIE:DRP13[11]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP13[8] PCIE:DRP13[9]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CAPABILITIES_PTR[6] PCIE:DRP13[6] PCIE:CAPABILITIES_PTR[7] PCIE:DRP13[7]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CAPABILITIES_PTR[4] PCIE:DRP13[4] PCIE:CAPABILITIES_PTR[5] PCIE:DRP13[5]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CAPABILITIES_PTR[2] PCIE:DRP13[2] PCIE:CAPABILITIES_PTR[3] PCIE:DRP13[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CAPABILITIES_PTR[0] PCIE:DRP13[0] PCIE:CAPABILITIES_PTR[1] PCIE:DRP13[1]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP12[14] PCIE:EXPANSION_ROM[30] PCIE:DRP12[15] PCIE:EXPANSION_ROM[31]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP12[12] PCIE:EXPANSION_ROM[28] PCIE:DRP12[13] PCIE:EXPANSION_ROM[29]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP12[10] PCIE:EXPANSION_ROM[26] PCIE:DRP12[11] PCIE:EXPANSION_ROM[27]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP12[8] PCIE:EXPANSION_ROM[24] PCIE:DRP12[9] PCIE:EXPANSION_ROM[25]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP12[6] PCIE:EXPANSION_ROM[22] PCIE:DRP12[7] PCIE:EXPANSION_ROM[23]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP12[4] PCIE:EXPANSION_ROM[20] PCIE:DRP12[5] PCIE:EXPANSION_ROM[21]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP12[2] PCIE:EXPANSION_ROM[18] PCIE:DRP12[3] PCIE:EXPANSION_ROM[19]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP12[0] PCIE:EXPANSION_ROM[16] PCIE:DRP12[1] PCIE:EXPANSION_ROM[17]
virtex6 PCIE bittile 4
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1D[14] PCIE:DRP1D[15]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1D[12] PCIE:DSN_CAP_ON PCIE:DRP1D[13]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1D[10] PCIE:DSN_CAP_NEXTPTR[10] PCIE:DRP1D[11] PCIE:DSN_CAP_NEXTPTR[11]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1D[8] PCIE:DSN_CAP_NEXTPTR[8] PCIE:DRP1D[9] PCIE:DSN_CAP_NEXTPTR[9]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1D[6] PCIE:DSN_CAP_NEXTPTR[6] PCIE:DRP1D[7] PCIE:DSN_CAP_NEXTPTR[7]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1D[4] PCIE:DSN_CAP_NEXTPTR[4] PCIE:DRP1D[5] PCIE:DSN_CAP_NEXTPTR[5]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1D[2] PCIE:DSN_CAP_NEXTPTR[2] PCIE:DRP1D[3] PCIE:DSN_CAP_NEXTPTR[3]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1D[0] PCIE:DSN_CAP_NEXTPTR[0] PCIE:DRP1D[1] PCIE:DSN_CAP_NEXTPTR[1]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1C[14] PCIE:DSN_CAP_ID[14] PCIE:DRP1C[15] PCIE:DSN_CAP_ID[15]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1C[12] PCIE:DSN_CAP_ID[12] PCIE:DRP1C[13] PCIE:DSN_CAP_ID[13]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1C[10] PCIE:DSN_CAP_ID[10] PCIE:DRP1C[11] PCIE:DSN_CAP_ID[11]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1C[8] PCIE:DSN_CAP_ID[8] PCIE:DRP1C[9] PCIE:DSN_CAP_ID[9]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1C[6] PCIE:DSN_CAP_ID[6] PCIE:DRP1C[7] PCIE:DSN_CAP_ID[7]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1C[4] PCIE:DSN_CAP_ID[4] PCIE:DRP1C[5] PCIE:DSN_CAP_ID[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1C[2] PCIE:DSN_CAP_ID[2] PCIE:DRP1C[3] PCIE:DSN_CAP_ID[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1C[0] PCIE:DSN_CAP_ID[0] PCIE:DRP1C[1] PCIE:DSN_CAP_ID[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1B[14] PCIE:DRP1B[15]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1B[12] PCIE:DRP1B[13]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1B[10] PCIE:DSN_BASE_PTR[10] PCIE:DRP1B[11] PCIE:DSN_BASE_PTR[11]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1B[8] PCIE:DSN_BASE_PTR[8] PCIE:DRP1B[9] PCIE:DSN_BASE_PTR[9]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1B[6] PCIE:DSN_BASE_PTR[6] PCIE:DRP1B[7] PCIE:DSN_BASE_PTR[7]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1B[4] PCIE:DSN_BASE_PTR[4] PCIE:DRP1B[5] PCIE:DSN_BASE_PTR[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1B[2] PCIE:DSN_BASE_PTR[2] PCIE:DRP1B[3] PCIE:DSN_BASE_PTR[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1B[0] PCIE:DSN_BASE_PTR[0] PCIE:DRP1B[1] PCIE:DSN_BASE_PTR[1]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEVICE_ID[14] PCIE:DRP1A[14] PCIE:DEVICE_ID[15] PCIE:DRP1A[15]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEVICE_ID[12] PCIE:DRP1A[12] PCIE:DEVICE_ID[13] PCIE:DRP1A[13]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEVICE_ID[10] PCIE:DRP1A[10] PCIE:DEVICE_ID[11] PCIE:DRP1A[11]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEVICE_ID[8] PCIE:DRP1A[8] PCIE:DEVICE_ID[9] PCIE:DRP1A[9]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEVICE_ID[6] PCIE:DRP1A[6] PCIE:DEVICE_ID[7] PCIE:DRP1A[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEVICE_ID[4] PCIE:DRP1A[4] PCIE:DEVICE_ID[5] PCIE:DRP1A[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEVICE_ID[2] PCIE:DRP1A[2] PCIE:DEVICE_ID[3] PCIE:DRP1A[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEVICE_ID[0] PCIE:DRP1A[0] PCIE:DEVICE_ID[1] PCIE:DRP1A[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP19[14] PCIE:DRP19[15]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP19[12] PCIE:DRP19[13]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP19[10] PCIE:DRP19[11]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEV_CONTROL_AUX_POWER_SUPPORTED PCIE:DRP19[8] PCIE:DRP19[9]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEV_CAP_RSVD_31_29[1] PCIE:DRP19[6] PCIE:DEV_CAP_RSVD_31_29[2] PCIE:DRP19[7]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEV_CAP_RSVD_17_16[1] PCIE:DRP19[4] PCIE:DEV_CAP_RSVD_31_29[0] PCIE:DRP19[5]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEV_CAP_RSVD_14_12[2] PCIE:DRP19[2] PCIE:DEV_CAP_RSVD_17_16[0] PCIE:DRP19[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEV_CAP_RSVD_14_12[0] PCIE:DRP19[0] PCIE:DEV_CAP_RSVD_14_12[1] PCIE:DRP19[1]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP18[14] PCIE:DRP18[15]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT[1] PCIE:DRP18[12] PCIE:DEV_CAP_ROLE_BASED_ERROR PCIE:DRP18[13]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEV_CAP_MAX_PAYLOAD_SUPPORTED[2] PCIE:DRP18[10] PCIE:DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT[0] PCIE:DRP18[11]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEV_CAP_MAX_PAYLOAD_SUPPORTED[0] PCIE:DRP18[8] PCIE:DEV_CAP_MAX_PAYLOAD_SUPPORTED[1] PCIE:DRP18[9]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEV_CAP_EXT_TAG_SUPPORTED PCIE:DRP18[6] PCIE:DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE PCIE:DRP18[7]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEV_CAP_ENDPOINT_L1_LATENCY[1] PCIE:DRP18[4] PCIE:DEV_CAP_ENDPOINT_L1_LATENCY[2] PCIE:DRP18[5]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEV_CAP_ENDPOINT_L0S_LATENCY[2] PCIE:DRP18[2] PCIE:DEV_CAP_ENDPOINT_L1_LATENCY[0] PCIE:DRP18[3]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DEV_CAP_ENDPOINT_L0S_LATENCY[0] PCIE:DRP18[0] PCIE:DEV_CAP_ENDPOINT_L0S_LATENCY[1] PCIE:DRP18[1]
virtex6 PCIE bittile 5
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP23[14] PCIE:LINK_CAP_RSVD_23_22[0] PCIE:DRP23[15] PCIE:LINK_CAP_RSVD_23_22[1]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP23[12] PCIE:LINK_CAP_MAX_LINK_SPEED[2] PCIE:DRP23[13] PCIE:LINK_CAP_MAX_LINK_SPEED[3]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP23[10] PCIE:LINK_CAP_MAX_LINK_SPEED[0] PCIE:DRP23[11] PCIE:LINK_CAP_MAX_LINK_SPEED[1]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP23[8] PCIE:LINK_CAP_L1_EXIT_LATENCY_GEN2[2] PCIE:DRP23[9] PCIE:LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP23[6] PCIE:LINK_CAP_L1_EXIT_LATENCY_GEN2[0] PCIE:DRP23[7] PCIE:LINK_CAP_L1_EXIT_LATENCY_GEN2[1]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP23[4] PCIE:LINK_CAP_L1_EXIT_LATENCY_GEN1[1] PCIE:DRP23[5] PCIE:LINK_CAP_L1_EXIT_LATENCY_GEN1[2]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP23[2] PCIE:LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2[2] PCIE:DRP23[3] PCIE:LINK_CAP_L1_EXIT_LATENCY_GEN1[0]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP23[0] PCIE:LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2[0] PCIE:DRP23[1] PCIE:LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2[1]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP22[14] PCIE:LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1[2] PCIE:DRP22[15]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP22[12] PCIE:LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1[0] PCIE:DRP22[13] PCIE:LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1[1]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP22[10] PCIE:LINK_CAP_L0S_EXIT_LATENCY_GEN2[1] PCIE:DRP22[11] PCIE:LINK_CAP_L0S_EXIT_LATENCY_GEN2[2]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP22[8] PCIE:LINK_CAP_L0S_EXIT_LATENCY_GEN1[2] PCIE:DRP22[9] PCIE:LINK_CAP_L0S_EXIT_LATENCY_GEN2[0]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP22[6] PCIE:LINK_CAP_L0S_EXIT_LATENCY_GEN1[0] PCIE:DRP22[7] PCIE:LINK_CAP_L0S_EXIT_LATENCY_GEN1[1]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP22[4] PCIE:LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2[1] PCIE:DRP22[5] PCIE:LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2[2]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP22[2] PCIE:LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1[2] PCIE:DRP22[3] PCIE:LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2[0]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP22[0] PCIE:LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1[0] PCIE:DRP22[1] PCIE:LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP21[14] PCIE:LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP PCIE:DRP21[15]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP21[12] PCIE:LINK_CAP_ASPM_SUPPORT[1] PCIE:DRP21[13] PCIE:LINK_CAP_CLOCK_POWER_MANAGEMENT
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP21[10] PCIE:LAST_CONFIG_DWORD[9] PCIE:DRP21[11] PCIE:LINK_CAP_ASPM_SUPPORT[0]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP21[8] PCIE:LAST_CONFIG_DWORD[7] PCIE:DRP21[9] PCIE:LAST_CONFIG_DWORD[8]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP21[6] PCIE:LAST_CONFIG_DWORD[5] PCIE:DRP21[7] PCIE:LAST_CONFIG_DWORD[6]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP21[4] PCIE:LAST_CONFIG_DWORD[3] PCIE:DRP21[5] PCIE:LAST_CONFIG_DWORD[4]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP21[2] PCIE:LAST_CONFIG_DWORD[1] PCIE:DRP21[3] PCIE:LAST_CONFIG_DWORD[2]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP21[0] PCIE:IS_SWITCH PCIE:DRP21[1] PCIE:LAST_CONFIG_DWORD[0]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP20[14] PCIE:INTERRUPT_PIN[6] PCIE:DRP20[15] PCIE:INTERRUPT_PIN[7]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP20[12] PCIE:INTERRUPT_PIN[4] PCIE:DRP20[13] PCIE:INTERRUPT_PIN[5]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP20[10] PCIE:INTERRUPT_PIN[2] PCIE:DRP20[11] PCIE:INTERRUPT_PIN[3]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP20[8] PCIE:INTERRUPT_PIN[0] PCIE:DRP20[9] PCIE:INTERRUPT_PIN[1]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP20[6] PCIE:HEADER_TYPE[6] PCIE:DRP20[7] PCIE:HEADER_TYPE[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP20[4] PCIE:HEADER_TYPE[4] PCIE:DRP20[5] PCIE:HEADER_TYPE[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP20[2] PCIE:HEADER_TYPE[2] PCIE:DRP20[3] PCIE:HEADER_TYPE[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP20[0] PCIE:HEADER_TYPE[0] PCIE:DRP20[1] PCIE:HEADER_TYPE[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1F[14] PCIE:DRP1F[15]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1F[12] PCIE:DRP1F[13]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1F[10] PCIE:DRP1F[11]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1F[8] PCIE:EXT_CFG_XP_CAP_PTR[8] PCIE:DRP1F[9] PCIE:EXT_CFG_XP_CAP_PTR[9]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1F[6] PCIE:EXT_CFG_XP_CAP_PTR[6] PCIE:DRP1F[7] PCIE:EXT_CFG_XP_CAP_PTR[7]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1F[4] PCIE:EXT_CFG_XP_CAP_PTR[4] PCIE:DRP1F[5] PCIE:EXT_CFG_XP_CAP_PTR[5]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1F[2] PCIE:EXT_CFG_XP_CAP_PTR[2] PCIE:DRP1F[3] PCIE:EXT_CFG_XP_CAP_PTR[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1F[0] PCIE:EXT_CFG_XP_CAP_PTR[0] PCIE:DRP1F[1] PCIE:EXT_CFG_XP_CAP_PTR[1]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1E[14] PCIE:DRP1E[15]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1E[12] PCIE:DRP1E[13]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1E[10] PCIE:DRP1E[11]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1E[8] PCIE:EXT_CFG_CAP_PTR[4] PCIE:DRP1E[9] PCIE:EXT_CFG_CAP_PTR[5]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1E[6] PCIE:EXT_CFG_CAP_PTR[2] PCIE:DRP1E[7] PCIE:EXT_CFG_CAP_PTR[3]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1E[4] PCIE:EXT_CFG_CAP_PTR[0] PCIE:DRP1E[5] PCIE:EXT_CFG_CAP_PTR[1]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1E[2] PCIE:DSN_CAP_VERSION[2] PCIE:DRP1E[3] PCIE:DSN_CAP_VERSION[3]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP1E[0] PCIE:DSN_CAP_VERSION[0] PCIE:DRP1E[1] PCIE:DSN_CAP_VERSION[1]
virtex6 PCIE bittile 6
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP29[14] PCIE:DRP29[15]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP29[12] PCIE:DRP29[13]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP29[10] PCIE:MSIX_CAP_PBA_BIR[1] PCIE:DRP29[11] PCIE:MSIX_CAP_PBA_BIR[2]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP29[8] PCIE:MSIX_CAP_ON PCIE:DRP29[9] PCIE:MSIX_CAP_PBA_BIR[0]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP29[6] PCIE:MSIX_CAP_NEXTPTR[6] PCIE:DRP29[7] PCIE:MSIX_CAP_NEXTPTR[7]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP29[4] PCIE:MSIX_CAP_NEXTPTR[4] PCIE:DRP29[5] PCIE:MSIX_CAP_NEXTPTR[5]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP29[2] PCIE:MSIX_CAP_NEXTPTR[2] PCIE:DRP29[3] PCIE:MSIX_CAP_NEXTPTR[3]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP29[0] PCIE:MSIX_CAP_NEXTPTR[0] PCIE:DRP29[1] PCIE:MSIX_CAP_NEXTPTR[1]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP28[14] PCIE:MSIX_CAP_ID[6] PCIE:DRP28[15] PCIE:MSIX_CAP_ID[7]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP28[12] PCIE:MSIX_CAP_ID[4] PCIE:DRP28[13] PCIE:MSIX_CAP_ID[5]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP28[10] PCIE:MSIX_CAP_ID[2] PCIE:DRP28[11] PCIE:MSIX_CAP_ID[3]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP28[8] PCIE:MSIX_CAP_ID[0] PCIE:DRP28[9] PCIE:MSIX_CAP_ID[1]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP28[6] PCIE:MSIX_BASE_PTR[6] PCIE:DRP28[7] PCIE:MSIX_BASE_PTR[7]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP28[4] PCIE:MSIX_BASE_PTR[4] PCIE:DRP28[5] PCIE:MSIX_BASE_PTR[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP28[2] PCIE:MSIX_BASE_PTR[2] PCIE:DRP28[3] PCIE:MSIX_BASE_PTR[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP28[0] PCIE:MSIX_BASE_PTR[0] PCIE:DRP28[1] PCIE:MSIX_BASE_PTR[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP27[14] PCIE:DRP27[15]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP27[12] PCIE:DRP27[13]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP27[10] PCIE:DRP27[11]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP27[8] PCIE:MSI_CAP_ON PCIE:DRP27[9] PCIE:MSI_CAP_PER_VECTOR_MASKING_CAPABLE
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP27[6] PCIE:MSI_CAP_NEXTPTR[6] PCIE:DRP27[7] PCIE:MSI_CAP_NEXTPTR[7]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP27[4] PCIE:MSI_CAP_NEXTPTR[4] PCIE:DRP27[5] PCIE:MSI_CAP_NEXTPTR[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP27[2] PCIE:MSI_CAP_NEXTPTR[2] PCIE:DRP27[3] PCIE:MSI_CAP_NEXTPTR[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP27[0] PCIE:MSI_CAP_NEXTPTR[0] PCIE:DRP27[1] PCIE:MSI_CAP_NEXTPTR[1]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP26[14] PCIE:DRP26[15]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP26[12] PCIE:DRP26[13]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP26[10] PCIE:MSI_CAP_MULTIMSGCAP[1] PCIE:DRP26[11] PCIE:MSI_CAP_MULTIMSGCAP[2]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP26[8] PCIE:MSI_CAP_MULTIMSG_EXTENSION PCIE:DRP26[9] PCIE:MSI_CAP_MULTIMSGCAP[0]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP26[6] PCIE:MSI_CAP_ID[6] PCIE:DRP26[7] PCIE:MSI_CAP_ID[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP26[4] PCIE:MSI_CAP_ID[4] PCIE:DRP26[5] PCIE:MSI_CAP_ID[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP26[2] PCIE:MSI_CAP_ID[2] PCIE:DRP26[3] PCIE:MSI_CAP_ID[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP26[0] PCIE:MSI_CAP_ID[0] PCIE:DRP26[1] PCIE:MSI_CAP_ID[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP25[14] PCIE:DRP25[15]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP25[12] PCIE:DRP25[13]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP25[10] PCIE:DRP25[11]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP25[8] PCIE:MSI_CAP_64_BIT_ADDR_CAPABLE PCIE:DRP25[9]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP25[6] PCIE:MSI_BASE_PTR[6] PCIE:DRP25[7] PCIE:MSI_BASE_PTR[7]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP25[4] PCIE:MSI_BASE_PTR[4] PCIE:DRP25[5] PCIE:MSI_BASE_PTR[5]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP25[2] PCIE:MSI_BASE_PTR[2] PCIE:DRP25[3] PCIE:MSI_BASE_PTR[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP25[0] PCIE:MSI_BASE_PTR[0] PCIE:DRP25[1] PCIE:MSI_BASE_PTR[1]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP24[14] PCIE:DRP24[15]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP24[12] PCIE:DRP24[13]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP24[10] PCIE:DRP24[11]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP24[8] PCIE:LINK_STATUS_SLOT_CLOCK_CONFIG PCIE:DRP24[9]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP24[6] PCIE:LINK_CTRL2_TARGET_LINK_SPEED[2] PCIE:DRP24[7] PCIE:LINK_CTRL2_TARGET_LINK_SPEED[3]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP24[4] PCIE:LINK_CTRL2_TARGET_LINK_SPEED[0] PCIE:DRP24[5] PCIE:LINK_CTRL2_TARGET_LINK_SPEED[1]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP24[2] PCIE:LINK_CTRL2_DEEMPHASIS PCIE:DRP24[3] PCIE:LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP24[0] PCIE:LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE PCIE:DRP24[1] PCIE:LINK_CONTROL_RCB
virtex6 PCIE bittile 7
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2F[14] PCIE:PCIE_CAP_CAPABILITY_ID[6] PCIE:DRP2F[15] PCIE:PCIE_CAP_CAPABILITY_ID[7]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2F[12] PCIE:PCIE_CAP_CAPABILITY_ID[4] PCIE:DRP2F[13] PCIE:PCIE_CAP_CAPABILITY_ID[5]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2F[10] PCIE:PCIE_CAP_CAPABILITY_ID[2] PCIE:DRP2F[11] PCIE:PCIE_CAP_CAPABILITY_ID[3]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2F[8] PCIE:PCIE_CAP_CAPABILITY_ID[0] PCIE:DRP2F[9] PCIE:PCIE_CAP_CAPABILITY_ID[1]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2F[6] PCIE:PCIE_BASE_PTR[6] PCIE:DRP2F[7] PCIE:PCIE_BASE_PTR[7]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2F[4] PCIE:PCIE_BASE_PTR[4] PCIE:DRP2F[5] PCIE:PCIE_BASE_PTR[5]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2F[2] PCIE:PCIE_BASE_PTR[2] PCIE:DRP2F[3] PCIE:PCIE_BASE_PTR[3]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2F[0] PCIE:PCIE_BASE_PTR[0] PCIE:DRP2F[1] PCIE:PCIE_BASE_PTR[1]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2E[14] PCIE:DRP2E[15]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2E[12] PCIE:DRP2E[13]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2E[10] PCIE:MSIX_CAP_TABLE_SIZE[10] PCIE:DRP2E[11]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2E[8] PCIE:MSIX_CAP_TABLE_SIZE[8] PCIE:DRP2E[9] PCIE:MSIX_CAP_TABLE_SIZE[9]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2E[6] PCIE:MSIX_CAP_TABLE_SIZE[6] PCIE:DRP2E[7] PCIE:MSIX_CAP_TABLE_SIZE[7]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2E[4] PCIE:MSIX_CAP_TABLE_SIZE[4] PCIE:DRP2E[5] PCIE:MSIX_CAP_TABLE_SIZE[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2E[2] PCIE:MSIX_CAP_TABLE_SIZE[2] PCIE:DRP2E[3] PCIE:MSIX_CAP_TABLE_SIZE[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2E[0] PCIE:MSIX_CAP_TABLE_SIZE[0] PCIE:DRP2E[1] PCIE:MSIX_CAP_TABLE_SIZE[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2D[14] PCIE:DRP2D[15]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2D[12] PCIE:MSIX_CAP_TABLE_OFFSET[28] PCIE:DRP2D[13]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2D[10] PCIE:MSIX_CAP_TABLE_OFFSET[26] PCIE:DRP2D[11] PCIE:MSIX_CAP_TABLE_OFFSET[27]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2D[8] PCIE:MSIX_CAP_TABLE_OFFSET[24] PCIE:DRP2D[9] PCIE:MSIX_CAP_TABLE_OFFSET[25]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2D[6] PCIE:MSIX_CAP_TABLE_OFFSET[22] PCIE:DRP2D[7] PCIE:MSIX_CAP_TABLE_OFFSET[23]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2D[4] PCIE:MSIX_CAP_TABLE_OFFSET[20] PCIE:DRP2D[5] PCIE:MSIX_CAP_TABLE_OFFSET[21]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2D[2] PCIE:MSIX_CAP_TABLE_OFFSET[18] PCIE:DRP2D[3] PCIE:MSIX_CAP_TABLE_OFFSET[19]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2D[0] PCIE:MSIX_CAP_TABLE_OFFSET[16] PCIE:DRP2D[1] PCIE:MSIX_CAP_TABLE_OFFSET[17]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2C[14] PCIE:MSIX_CAP_TABLE_OFFSET[14] PCIE:DRP2C[15] PCIE:MSIX_CAP_TABLE_OFFSET[15]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2C[12] PCIE:MSIX_CAP_TABLE_OFFSET[12] PCIE:DRP2C[13] PCIE:MSIX_CAP_TABLE_OFFSET[13]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2C[10] PCIE:MSIX_CAP_TABLE_OFFSET[10] PCIE:DRP2C[11] PCIE:MSIX_CAP_TABLE_OFFSET[11]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2C[8] PCIE:MSIX_CAP_TABLE_OFFSET[8] PCIE:DRP2C[9] PCIE:MSIX_CAP_TABLE_OFFSET[9]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2C[6] PCIE:MSIX_CAP_TABLE_OFFSET[6] PCIE:DRP2C[7] PCIE:MSIX_CAP_TABLE_OFFSET[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2C[4] PCIE:MSIX_CAP_TABLE_OFFSET[4] PCIE:DRP2C[5] PCIE:MSIX_CAP_TABLE_OFFSET[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2C[2] PCIE:MSIX_CAP_TABLE_OFFSET[2] PCIE:DRP2C[3] PCIE:MSIX_CAP_TABLE_OFFSET[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2C[0] PCIE:MSIX_CAP_TABLE_OFFSET[0] PCIE:DRP2C[1] PCIE:MSIX_CAP_TABLE_OFFSET[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2B[14] PCIE:MSIX_CAP_TABLE_BIR[1] PCIE:DRP2B[15] PCIE:MSIX_CAP_TABLE_BIR[2]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2B[12] PCIE:MSIX_CAP_PBA_OFFSET[28] PCIE:DRP2B[13] PCIE:MSIX_CAP_TABLE_BIR[0]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2B[10] PCIE:MSIX_CAP_PBA_OFFSET[26] PCIE:DRP2B[11] PCIE:MSIX_CAP_PBA_OFFSET[27]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2B[8] PCIE:MSIX_CAP_PBA_OFFSET[24] PCIE:DRP2B[9] PCIE:MSIX_CAP_PBA_OFFSET[25]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2B[6] PCIE:MSIX_CAP_PBA_OFFSET[22] PCIE:DRP2B[7] PCIE:MSIX_CAP_PBA_OFFSET[23]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2B[4] PCIE:MSIX_CAP_PBA_OFFSET[20] PCIE:DRP2B[5] PCIE:MSIX_CAP_PBA_OFFSET[21]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2B[2] PCIE:MSIX_CAP_PBA_OFFSET[18] PCIE:DRP2B[3] PCIE:MSIX_CAP_PBA_OFFSET[19]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2B[0] PCIE:MSIX_CAP_PBA_OFFSET[16] PCIE:DRP2B[1] PCIE:MSIX_CAP_PBA_OFFSET[17]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2A[14] PCIE:MSIX_CAP_PBA_OFFSET[14] PCIE:DRP2A[15] PCIE:MSIX_CAP_PBA_OFFSET[15]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2A[12] PCIE:MSIX_CAP_PBA_OFFSET[12] PCIE:DRP2A[13] PCIE:MSIX_CAP_PBA_OFFSET[13]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2A[10] PCIE:MSIX_CAP_PBA_OFFSET[10] PCIE:DRP2A[11] PCIE:MSIX_CAP_PBA_OFFSET[11]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2A[8] PCIE:MSIX_CAP_PBA_OFFSET[8] PCIE:DRP2A[9] PCIE:MSIX_CAP_PBA_OFFSET[9]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2A[6] PCIE:MSIX_CAP_PBA_OFFSET[6] PCIE:DRP2A[7] PCIE:MSIX_CAP_PBA_OFFSET[7]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2A[4] PCIE:MSIX_CAP_PBA_OFFSET[4] PCIE:DRP2A[5] PCIE:MSIX_CAP_PBA_OFFSET[5]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2A[2] PCIE:MSIX_CAP_PBA_OFFSET[2] PCIE:DRP2A[3] PCIE:MSIX_CAP_PBA_OFFSET[3]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP2A[0] PCIE:MSIX_CAP_PBA_OFFSET[0] PCIE:DRP2A[1] PCIE:MSIX_CAP_PBA_OFFSET[1]
virtex6 PCIE bittile 8
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP35[14] PCIE:DRP35[15]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP35[12] PCIE:PM_DATA_SCALE7[0] PCIE:DRP35[13] PCIE:PM_DATA_SCALE7[1]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP35[10] PCIE:PM_DATA_SCALE6[0] PCIE:DRP35[11] PCIE:PM_DATA_SCALE6[1]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP35[8] PCIE:PM_DATA_SCALE5[0] PCIE:DRP35[9] PCIE:PM_DATA_SCALE5[1]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP35[6] PCIE:PM_DATA_SCALE4[0] PCIE:DRP35[7] PCIE:PM_DATA_SCALE4[1]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP35[4] PCIE:PM_DATA_SCALE3[0] PCIE:DRP35[5] PCIE:PM_DATA_SCALE3[1]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP35[2] PCIE:PM_DATA_SCALE2[0] PCIE:DRP35[3] PCIE:PM_DATA_SCALE2[1]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP35[0] PCIE:PM_DATA_SCALE1[0] PCIE:DRP35[1] PCIE:PM_DATA_SCALE1[1]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP34[14] PCIE:PM_DATA_SCALE0[0] PCIE:DRP34[15] PCIE:PM_DATA_SCALE0[1]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP34[12] PCIE:PM_CSR_BPCCEN PCIE:DRP34[13] PCIE:PM_CSR_NOSOFTRST
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP34[10] PCIE:PM_CAP_VERSION[2] PCIE:DRP34[11] PCIE:PM_CSR_B2B3
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP34[8] PCIE:PM_CAP_VERSION[0] PCIE:DRP34[9] PCIE:PM_CAP_VERSION[1]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP34[6] PCIE:PM_CAP_PMESUPPORT[4] PCIE:DRP34[7] PCIE:PM_CAP_RSVD_04
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP34[4] PCIE:PM_CAP_PMESUPPORT[2] PCIE:DRP34[5] PCIE:PM_CAP_PMESUPPORT[3]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP34[2] PCIE:PM_CAP_PMESUPPORT[0] PCIE:DRP34[3] PCIE:PM_CAP_PMESUPPORT[1]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP34[0] PCIE:PM_CAP_ON PCIE:DRP34[1] PCIE:PM_CAP_PME_CLOCK
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP33[14] PCIE:PM_CAP_NEXTPTR[6] PCIE:DRP33[15] PCIE:PM_CAP_NEXTPTR[7]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP33[12] PCIE:PM_CAP_NEXTPTR[4] PCIE:DRP33[13] PCIE:PM_CAP_NEXTPTR[5]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP33[10] PCIE:PM_CAP_NEXTPTR[2] PCIE:DRP33[11] PCIE:PM_CAP_NEXTPTR[3]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP33[8] PCIE:PM_CAP_NEXTPTR[0] PCIE:DRP33[9] PCIE:PM_CAP_NEXTPTR[1]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP33[6] PCIE:PM_CAP_ID[6] PCIE:DRP33[7] PCIE:PM_CAP_ID[7]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP33[4] PCIE:PM_CAP_ID[4] PCIE:DRP33[5] PCIE:PM_CAP_ID[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP33[2] PCIE:PM_CAP_ID[2] PCIE:DRP33[3] PCIE:PM_CAP_ID[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP33[0] PCIE:PM_CAP_ID[0] PCIE:DRP33[1] PCIE:PM_CAP_ID[1]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP32[14] PCIE:DRP32[15]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP32[12] PCIE:PM_CAP_D2SUPPORT PCIE:DRP32[13] PCIE:PM_CAP_DSI
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP32[10] PCIE:PM_CAP_AUXCURRENT[2] PCIE:DRP32[11] PCIE:PM_CAP_D1SUPPORT
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP32[8] PCIE:PM_CAP_AUXCURRENT[0] PCIE:DRP32[9] PCIE:PM_CAP_AUXCURRENT[1]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP32[6] PCIE:PM_BASE_PTR[6] PCIE:DRP32[7] PCIE:PM_BASE_PTR[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP32[4] PCIE:PM_BASE_PTR[4] PCIE:DRP32[5] PCIE:PM_BASE_PTR[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP32[2] PCIE:PM_BASE_PTR[2] PCIE:DRP32[3] PCIE:PM_BASE_PTR[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP32[0] PCIE:PM_BASE_PTR[0] PCIE:DRP32[1] PCIE:PM_BASE_PTR[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP31[14] PCIE:PCIE_REVISION[2] PCIE:DRP31[15] PCIE:PCIE_REVISION[3]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP31[12] PCIE:PCIE_REVISION[0] PCIE:DRP31[13] PCIE:PCIE_REVISION[1]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP31[10] PCIE:PCIE_CAP_RSVD_15_14[1] PCIE:DRP31[11] PCIE:PCIE_CAP_SLOT_IMPLEMENTED
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP31[8] PCIE:PCIE_CAP_ON PCIE:DRP31[9] PCIE:PCIE_CAP_RSVD_15_14[0]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP31[6] PCIE:PCIE_CAP_NEXTPTR[6] PCIE:DRP31[7] PCIE:PCIE_CAP_NEXTPTR[7]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP31[4] PCIE:PCIE_CAP_NEXTPTR[4] PCIE:DRP31[5] PCIE:PCIE_CAP_NEXTPTR[5]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP31[2] PCIE:PCIE_CAP_NEXTPTR[2] PCIE:DRP31[3] PCIE:PCIE_CAP_NEXTPTR[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP31[0] PCIE:PCIE_CAP_NEXTPTR[0] PCIE:DRP31[1] PCIE:PCIE_CAP_NEXTPTR[1]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP30[14] PCIE:DRP30[15]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP30[12] PCIE:PCIE_CAP_INT_MSG_NUM[4] PCIE:DRP30[13]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP30[10] PCIE:PCIE_CAP_INT_MSG_NUM[2] PCIE:DRP30[11] PCIE:PCIE_CAP_INT_MSG_NUM[3]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP30[8] PCIE:PCIE_CAP_INT_MSG_NUM[0] PCIE:DRP30[9] PCIE:PCIE_CAP_INT_MSG_NUM[1]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP30[6] PCIE:PCIE_CAP_DEVICE_PORT_TYPE[2] PCIE:DRP30[7] PCIE:PCIE_CAP_DEVICE_PORT_TYPE[3]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP30[4] PCIE:PCIE_CAP_DEVICE_PORT_TYPE[0] PCIE:DRP30[5] PCIE:PCIE_CAP_DEVICE_PORT_TYPE[1]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP30[2] PCIE:PCIE_CAP_CAPABILITY_VERSION[2] PCIE:DRP30[3] PCIE:PCIE_CAP_CAPABILITY_VERSION[3]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP30[0] PCIE:PCIE_CAP_CAPABILITY_VERSION[0] PCIE:DRP30[1] PCIE:PCIE_CAP_CAPABILITY_VERSION[1]
virtex6 PCIE bittile 9
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3B[14] PCIE:SLOT_CAP_POWER_CONTROLLER_PRESENT PCIE:DRP3B[15] PCIE:SLOT_CAP_POWER_INDICATOR_PRESENT
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3B[12] PCIE:SLOT_CAP_PHYSICAL_SLOT_NUM[11] PCIE:DRP3B[13] PCIE:SLOT_CAP_PHYSICAL_SLOT_NUM[12]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3B[10] PCIE:SLOT_CAP_PHYSICAL_SLOT_NUM[9] PCIE:DRP3B[11] PCIE:SLOT_CAP_PHYSICAL_SLOT_NUM[10]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3B[8] PCIE:SLOT_CAP_PHYSICAL_SLOT_NUM[7] PCIE:DRP3B[9] PCIE:SLOT_CAP_PHYSICAL_SLOT_NUM[8]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3B[6] PCIE:SLOT_CAP_PHYSICAL_SLOT_NUM[5] PCIE:DRP3B[7] PCIE:SLOT_CAP_PHYSICAL_SLOT_NUM[6]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3B[4] PCIE:SLOT_CAP_PHYSICAL_SLOT_NUM[3] PCIE:DRP3B[5] PCIE:SLOT_CAP_PHYSICAL_SLOT_NUM[4]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3B[2] PCIE:SLOT_CAP_PHYSICAL_SLOT_NUM[1] PCIE:DRP3B[3] PCIE:SLOT_CAP_PHYSICAL_SLOT_NUM[2]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3B[0] PCIE:SLOT_CAP_NO_CMD_COMPLETED_SUPPORT PCIE:DRP3B[1] PCIE:SLOT_CAP_PHYSICAL_SLOT_NUM[0]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3A[14] PCIE:SLOT_CAP_HOTPLUG_SURPRISE PCIE:DRP3A[15] PCIE:SLOT_CAP_MRL_SENSOR_PRESENT
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3A[12] PCIE:SLOT_CAP_ELEC_INTERLOCK_PRESENT PCIE:DRP3A[13] PCIE:SLOT_CAP_HOTPLUG_CAPABLE
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3A[10] PCIE:SLOT_CAP_ATT_BUTTON_PRESENT PCIE:DRP3A[11] PCIE:SLOT_CAP_ATT_INDICATOR_PRESENT
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3A[8] PCIE:ROOT_CAP_CRS_SW_VISIBILITY PCIE:DRP3A[9] PCIE:SELECT_DLL_IF
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3A[6] PCIE:REVISION_ID[6] PCIE:DRP3A[7] PCIE:REVISION_ID[7]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3A[4] PCIE:REVISION_ID[4] PCIE:DRP3A[5] PCIE:REVISION_ID[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3A[2] PCIE:REVISION_ID[2] PCIE:DRP3A[3] PCIE:REVISION_ID[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3A[0] PCIE:REVISION_ID[0] PCIE:DRP3A[1] PCIE:REVISION_ID[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP39[14] PCIE:PM_DATA7[6] PCIE:DRP39[15] PCIE:PM_DATA7[7]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP39[12] PCIE:PM_DATA7[4] PCIE:DRP39[13] PCIE:PM_DATA7[5]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP39[10] PCIE:PM_DATA7[2] PCIE:DRP39[11] PCIE:PM_DATA7[3]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP39[8] PCIE:PM_DATA7[0] PCIE:DRP39[9] PCIE:PM_DATA7[1]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP39[6] PCIE:PM_DATA6[6] PCIE:DRP39[7] PCIE:PM_DATA6[7]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP39[4] PCIE:PM_DATA6[4] PCIE:DRP39[5] PCIE:PM_DATA6[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP39[2] PCIE:PM_DATA6[2] PCIE:DRP39[3] PCIE:PM_DATA6[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP39[0] PCIE:PM_DATA6[0] PCIE:DRP39[1] PCIE:PM_DATA6[1]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP38[14] PCIE:PM_DATA5[6] PCIE:DRP38[15] PCIE:PM_DATA5[7]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP38[12] PCIE:PM_DATA5[4] PCIE:DRP38[13] PCIE:PM_DATA5[5]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP38[10] PCIE:PM_DATA5[2] PCIE:DRP38[11] PCIE:PM_DATA5[3]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP38[8] PCIE:PM_DATA5[0] PCIE:DRP38[9] PCIE:PM_DATA5[1]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP38[6] PCIE:PM_DATA4[6] PCIE:DRP38[7] PCIE:PM_DATA4[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP38[4] PCIE:PM_DATA4[4] PCIE:DRP38[5] PCIE:PM_DATA4[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP38[2] PCIE:PM_DATA4[2] PCIE:DRP38[3] PCIE:PM_DATA4[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP38[0] PCIE:PM_DATA4[0] PCIE:DRP38[1] PCIE:PM_DATA4[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP37[14] PCIE:PM_DATA3[6] PCIE:DRP37[15] PCIE:PM_DATA3[7]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP37[12] PCIE:PM_DATA3[4] PCIE:DRP37[13] PCIE:PM_DATA3[5]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP37[10] PCIE:PM_DATA3[2] PCIE:DRP37[11] PCIE:PM_DATA3[3]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP37[8] PCIE:PM_DATA3[0] PCIE:DRP37[9] PCIE:PM_DATA3[1]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP37[6] PCIE:PM_DATA2[6] PCIE:DRP37[7] PCIE:PM_DATA2[7]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP37[4] PCIE:PM_DATA2[4] PCIE:DRP37[5] PCIE:PM_DATA2[5]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP37[2] PCIE:PM_DATA2[2] PCIE:DRP37[3] PCIE:PM_DATA2[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP37[0] PCIE:PM_DATA2[0] PCIE:DRP37[1] PCIE:PM_DATA2[1]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP36[14] PCIE:PM_DATA1[6] PCIE:DRP36[15] PCIE:PM_DATA1[7]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP36[12] PCIE:PM_DATA1[4] PCIE:DRP36[13] PCIE:PM_DATA1[5]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP36[10] PCIE:PM_DATA1[2] PCIE:DRP36[11] PCIE:PM_DATA1[3]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP36[8] PCIE:PM_DATA1[0] PCIE:DRP36[9] PCIE:PM_DATA1[1]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP36[6] PCIE:PM_DATA0[6] PCIE:DRP36[7] PCIE:PM_DATA0[7]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP36[4] PCIE:PM_DATA0[4] PCIE:DRP36[5] PCIE:PM_DATA0[5]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP36[2] PCIE:PM_DATA0[2] PCIE:DRP36[3] PCIE:PM_DATA0[3]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP36[0] PCIE:PM_DATA0[0] PCIE:DRP36[1] PCIE:PM_DATA0[1]
virtex6 PCIE bittile 10
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP41[14] PCIE:VC_CAP_ID[14] PCIE:DRP41[15] PCIE:VC_CAP_ID[15]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP41[12] PCIE:VC_CAP_ID[12] PCIE:DRP41[13] PCIE:VC_CAP_ID[13]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP41[10] PCIE:VC_CAP_ID[10] PCIE:DRP41[11] PCIE:VC_CAP_ID[11]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP41[8] PCIE:VC_CAP_ID[8] PCIE:DRP41[9] PCIE:VC_CAP_ID[9]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP41[6] PCIE:VC_CAP_ID[6] PCIE:DRP41[7] PCIE:VC_CAP_ID[7]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP41[4] PCIE:VC_CAP_ID[4] PCIE:DRP41[5] PCIE:VC_CAP_ID[5]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP41[2] PCIE:VC_CAP_ID[2] PCIE:DRP41[3] PCIE:VC_CAP_ID[3]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP41[0] PCIE:VC_CAP_ID[0] PCIE:DRP41[1] PCIE:VC_CAP_ID[1]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP40[14] PCIE:DRP40[15]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP40[12] PCIE:VC_CAP_ON PCIE:DRP40[13]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP40[10] PCIE:VC_CAP_NEXTPTR[10] PCIE:DRP40[11] PCIE:VC_CAP_NEXTPTR[11]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP40[8] PCIE:VC_CAP_NEXTPTR[8] PCIE:DRP40[9] PCIE:VC_CAP_NEXTPTR[9]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP40[6] PCIE:VC_CAP_NEXTPTR[6] PCIE:DRP40[7] PCIE:VC_CAP_NEXTPTR[7]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP40[4] PCIE:VC_CAP_NEXTPTR[4] PCIE:DRP40[5] PCIE:VC_CAP_NEXTPTR[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP40[2] PCIE:VC_CAP_NEXTPTR[2] PCIE:DRP40[3] PCIE:VC_CAP_NEXTPTR[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP40[0] PCIE:VC_CAP_NEXTPTR[0] PCIE:DRP40[1] PCIE:VC_CAP_NEXTPTR[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3F[14] PCIE:DRP3F[15]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3F[12] PCIE:DRP3F[13]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3F[10] PCIE:VC_BASE_PTR[10] PCIE:DRP3F[11] PCIE:VC_BASE_PTR[11]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3F[8] PCIE:VC_BASE_PTR[8] PCIE:DRP3F[9] PCIE:VC_BASE_PTR[9]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3F[6] PCIE:VC_BASE_PTR[6] PCIE:DRP3F[7] PCIE:VC_BASE_PTR[7]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3F[4] PCIE:VC_BASE_PTR[4] PCIE:DRP3F[5] PCIE:VC_BASE_PTR[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3F[2] PCIE:VC_BASE_PTR[2] PCIE:DRP3F[3] PCIE:VC_BASE_PTR[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3F[0] PCIE:VC_BASE_PTR[0] PCIE:DRP3F[1] PCIE:VC_BASE_PTR[1]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3E[14] PCIE:SUBSYSTEM_VENDOR_ID[14] PCIE:DRP3E[15] PCIE:SUBSYSTEM_VENDOR_ID[15]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3E[12] PCIE:SUBSYSTEM_VENDOR_ID[12] PCIE:DRP3E[13] PCIE:SUBSYSTEM_VENDOR_ID[13]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3E[10] PCIE:SUBSYSTEM_VENDOR_ID[10] PCIE:DRP3E[11] PCIE:SUBSYSTEM_VENDOR_ID[11]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3E[8] PCIE:SUBSYSTEM_VENDOR_ID[8] PCIE:DRP3E[9] PCIE:SUBSYSTEM_VENDOR_ID[9]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3E[6] PCIE:SUBSYSTEM_VENDOR_ID[6] PCIE:DRP3E[7] PCIE:SUBSYSTEM_VENDOR_ID[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3E[4] PCIE:SUBSYSTEM_VENDOR_ID[4] PCIE:DRP3E[5] PCIE:SUBSYSTEM_VENDOR_ID[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3E[2] PCIE:SUBSYSTEM_VENDOR_ID[2] PCIE:DRP3E[3] PCIE:SUBSYSTEM_VENDOR_ID[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3E[0] PCIE:SUBSYSTEM_VENDOR_ID[0] PCIE:DRP3E[1] PCIE:SUBSYSTEM_VENDOR_ID[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3D[14] PCIE:SUBSYSTEM_ID[14] PCIE:DRP3D[15] PCIE:SUBSYSTEM_ID[15]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3D[12] PCIE:SUBSYSTEM_ID[12] PCIE:DRP3D[13] PCIE:SUBSYSTEM_ID[13]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3D[10] PCIE:SUBSYSTEM_ID[10] PCIE:DRP3D[11] PCIE:SUBSYSTEM_ID[11]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3D[8] PCIE:SUBSYSTEM_ID[8] PCIE:DRP3D[9] PCIE:SUBSYSTEM_ID[9]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3D[6] PCIE:SUBSYSTEM_ID[6] PCIE:DRP3D[7] PCIE:SUBSYSTEM_ID[7]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3D[4] PCIE:SUBSYSTEM_ID[4] PCIE:DRP3D[5] PCIE:SUBSYSTEM_ID[5]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3D[2] PCIE:SUBSYSTEM_ID[2] PCIE:DRP3D[3] PCIE:SUBSYSTEM_ID[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3D[0] PCIE:SUBSYSTEM_ID[0] PCIE:DRP3D[1] PCIE:SUBSYSTEM_ID[1]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3C[14] PCIE:DRP3C[15]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3C[12] PCIE:DRP3C[13]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3C[10] PCIE:DRP3C[11]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3C[8] PCIE:SLOT_CAP_SLOT_POWER_LIMIT_VALUE[6] PCIE:DRP3C[9] PCIE:SLOT_CAP_SLOT_POWER_LIMIT_VALUE[7]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3C[6] PCIE:SLOT_CAP_SLOT_POWER_LIMIT_VALUE[4] PCIE:DRP3C[7] PCIE:SLOT_CAP_SLOT_POWER_LIMIT_VALUE[5]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3C[4] PCIE:SLOT_CAP_SLOT_POWER_LIMIT_VALUE[2] PCIE:DRP3C[5] PCIE:SLOT_CAP_SLOT_POWER_LIMIT_VALUE[3]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3C[2] PCIE:SLOT_CAP_SLOT_POWER_LIMIT_VALUE[0] PCIE:DRP3C[3] PCIE:SLOT_CAP_SLOT_POWER_LIMIT_VALUE[1]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP3C[0] PCIE:SLOT_CAP_SLOT_POWER_LIMIT_SCALE[0] PCIE:DRP3C[1] PCIE:SLOT_CAP_SLOT_POWER_LIMIT_SCALE[1]
virtex6 PCIE bittile 11
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP47[14] PCIE:VSEC_CAP_ID[14] PCIE:DRP47[15] PCIE:VSEC_CAP_ID[15]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP47[12] PCIE:VSEC_CAP_ID[12] PCIE:DRP47[13] PCIE:VSEC_CAP_ID[13]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP47[10] PCIE:VSEC_CAP_ID[10] PCIE:DRP47[11] PCIE:VSEC_CAP_ID[11]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP47[8] PCIE:VSEC_CAP_ID[8] PCIE:DRP47[9] PCIE:VSEC_CAP_ID[9]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP47[6] PCIE:VSEC_CAP_ID[6] PCIE:DRP47[7] PCIE:VSEC_CAP_ID[7]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP47[4] PCIE:VSEC_CAP_ID[4] PCIE:DRP47[5] PCIE:VSEC_CAP_ID[5]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP47[2] PCIE:VSEC_CAP_ID[2] PCIE:DRP47[3] PCIE:VSEC_CAP_ID[3]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP47[0] PCIE:VSEC_CAP_ID[0] PCIE:DRP47[1] PCIE:VSEC_CAP_ID[1]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP46[14] PCIE:VSEC_CAP_HDR_REVISION[2] PCIE:DRP46[15] PCIE:VSEC_CAP_HDR_REVISION[3]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP46[12] PCIE:VSEC_CAP_HDR_REVISION[0] PCIE:DRP46[13] PCIE:VSEC_CAP_HDR_REVISION[1]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP46[10] PCIE:VSEC_CAP_HDR_LENGTH[10] PCIE:DRP46[11] PCIE:VSEC_CAP_HDR_LENGTH[11]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP46[8] PCIE:VSEC_CAP_HDR_LENGTH[8] PCIE:DRP46[9] PCIE:VSEC_CAP_HDR_LENGTH[9]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP46[6] PCIE:VSEC_CAP_HDR_LENGTH[6] PCIE:DRP46[7] PCIE:VSEC_CAP_HDR_LENGTH[7]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP46[4] PCIE:VSEC_CAP_HDR_LENGTH[4] PCIE:DRP46[5] PCIE:VSEC_CAP_HDR_LENGTH[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP46[2] PCIE:VSEC_CAP_HDR_LENGTH[2] PCIE:DRP46[3] PCIE:VSEC_CAP_HDR_LENGTH[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP46[0] PCIE:VSEC_CAP_HDR_LENGTH[0] PCIE:DRP46[1] PCIE:VSEC_CAP_HDR_LENGTH[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP45[14] PCIE:VSEC_CAP_HDR_ID[14] PCIE:DRP45[15] PCIE:VSEC_CAP_HDR_ID[15]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP45[12] PCIE:VSEC_CAP_HDR_ID[12] PCIE:DRP45[13] PCIE:VSEC_CAP_HDR_ID[13]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP45[10] PCIE:VSEC_CAP_HDR_ID[10] PCIE:DRP45[11] PCIE:VSEC_CAP_HDR_ID[11]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP45[8] PCIE:VSEC_CAP_HDR_ID[8] PCIE:DRP45[9] PCIE:VSEC_CAP_HDR_ID[9]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP45[6] PCIE:VSEC_CAP_HDR_ID[6] PCIE:DRP45[7] PCIE:VSEC_CAP_HDR_ID[7]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP45[4] PCIE:VSEC_CAP_HDR_ID[4] PCIE:DRP45[5] PCIE:VSEC_CAP_HDR_ID[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP45[2] PCIE:VSEC_CAP_HDR_ID[2] PCIE:DRP45[3] PCIE:VSEC_CAP_HDR_ID[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP45[0] PCIE:VSEC_CAP_HDR_ID[0] PCIE:DRP45[1] PCIE:VSEC_CAP_HDR_ID[1]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP44[14] PCIE:DRP44[15]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP44[12] PCIE:DRP44[13]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP44[10] PCIE:VSEC_BASE_PTR[10] PCIE:DRP44[11] PCIE:VSEC_BASE_PTR[11]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP44[8] PCIE:VSEC_BASE_PTR[8] PCIE:DRP44[9] PCIE:VSEC_BASE_PTR[9]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP44[6] PCIE:VSEC_BASE_PTR[6] PCIE:DRP44[7] PCIE:VSEC_BASE_PTR[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP44[4] PCIE:VSEC_BASE_PTR[4] PCIE:DRP44[5] PCIE:VSEC_BASE_PTR[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP44[2] PCIE:VSEC_BASE_PTR[2] PCIE:DRP44[3] PCIE:VSEC_BASE_PTR[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP44[0] PCIE:VSEC_BASE_PTR[0] PCIE:DRP44[1] PCIE:VSEC_BASE_PTR[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP43[14] PCIE:VENDOR_ID[14] PCIE:DRP43[15] PCIE:VENDOR_ID[15]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP43[12] PCIE:VENDOR_ID[12] PCIE:DRP43[13] PCIE:VENDOR_ID[13]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP43[10] PCIE:VENDOR_ID[10] PCIE:DRP43[11] PCIE:VENDOR_ID[11]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP43[8] PCIE:VENDOR_ID[8] PCIE:DRP43[9] PCIE:VENDOR_ID[9]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP43[6] PCIE:VENDOR_ID[6] PCIE:DRP43[7] PCIE:VENDOR_ID[7]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP43[4] PCIE:VENDOR_ID[4] PCIE:DRP43[5] PCIE:VENDOR_ID[5]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP43[2] PCIE:VENDOR_ID[2] PCIE:DRP43[3] PCIE:VENDOR_ID[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP43[0] PCIE:VENDOR_ID[0] PCIE:DRP43[1] PCIE:VENDOR_ID[1]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP42[14] PCIE:DRP42[15]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP42[12] PCIE:DRP42[13]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP42[10] PCIE:DRP42[11]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP42[8] PCIE:DRP42[9]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP42[6] PCIE:DRP42[7]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP42[4] PCIE:DRP42[5]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP42[2] PCIE:DRP42[3]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP42[0] PCIE:VC_CAP_REJECT_SNOOP_TRANSACTIONS PCIE:DRP42[1]
virtex6 PCIE bittile 12
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4D[14] PCIE:LINK_CAP_MAX_LINK_WIDTH[4] PCIE:DRP4D[15] PCIE:LINK_CAP_MAX_LINK_WIDTH[5]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4D[12] PCIE:LINK_CAP_MAX_LINK_WIDTH[2] PCIE:DRP4D[13] PCIE:LINK_CAP_MAX_LINK_WIDTH[3]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4D[10] PCIE:LINK_CAP_MAX_LINK_WIDTH[0] PCIE:DRP4D[11] PCIE:LINK_CAP_MAX_LINK_WIDTH[1]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4D[8] PCIE:INFER_EI[3] PCIE:DRP4D[9] PCIE:INFER_EI[4]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4D[6] PCIE:INFER_EI[1] PCIE:DRP4D[7] PCIE:INFER_EI[2]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4D[4] PCIE:ENTER_RVRY_EI_L0 PCIE:DRP4D[5] PCIE:INFER_EI[0]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DISABLE_LANE_REVERSAL PCIE:DRP4D[2] PCIE:DISABLE_SCRAMBLING PCIE:DRP4D[3]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4D[0] PCIE:LL_REPLAY_TIMEOUT_FUNC[0] PCIE:DRP4D[1] PCIE:LL_REPLAY_TIMEOUT_FUNC[1]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4C[14] PCIE:LL_REPLAY_TIMEOUT[14] PCIE:DRP4C[15] PCIE:LL_REPLAY_TIMEOUT_EN
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4C[12] PCIE:LL_REPLAY_TIMEOUT[12] PCIE:DRP4C[13] PCIE:LL_REPLAY_TIMEOUT[13]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4C[10] PCIE:LL_REPLAY_TIMEOUT[10] PCIE:DRP4C[11] PCIE:LL_REPLAY_TIMEOUT[11]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4C[8] PCIE:LL_REPLAY_TIMEOUT[8] PCIE:DRP4C[9] PCIE:LL_REPLAY_TIMEOUT[9]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4C[6] PCIE:LL_REPLAY_TIMEOUT[6] PCIE:DRP4C[7] PCIE:LL_REPLAY_TIMEOUT[7]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4C[4] PCIE:LL_REPLAY_TIMEOUT[4] PCIE:DRP4C[5] PCIE:LL_REPLAY_TIMEOUT[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4C[2] PCIE:LL_REPLAY_TIMEOUT[2] PCIE:DRP4C[3] PCIE:LL_REPLAY_TIMEOUT[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4C[0] PCIE:LL_REPLAY_TIMEOUT[0] PCIE:DRP4C[1] PCIE:LL_REPLAY_TIMEOUT[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4B[14] PCIE:DRP4B[15]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4B[12] PCIE:DRP4B[13]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4B[10] PCIE:DRP4B[11]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4B[8] PCIE:DRP4B[9]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4B[6] PCIE:DRP4B[7]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4B[4] PCIE:DRP4B[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4B[2] PCIE:DRP4B[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4B[0] PCIE:LL_ACK_TIMEOUT_FUNC[0] PCIE:DRP4B[1] PCIE:LL_ACK_TIMEOUT_FUNC[1]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4A[14] PCIE:LL_ACK_TIMEOUT[14] PCIE:DRP4A[15] PCIE:LL_ACK_TIMEOUT_EN
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4A[12] PCIE:LL_ACK_TIMEOUT[12] PCIE:DRP4A[13] PCIE:LL_ACK_TIMEOUT[13]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4A[10] PCIE:LL_ACK_TIMEOUT[10] PCIE:DRP4A[11] PCIE:LL_ACK_TIMEOUT[11]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4A[8] PCIE:LL_ACK_TIMEOUT[8] PCIE:DRP4A[9] PCIE:LL_ACK_TIMEOUT[9]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4A[6] PCIE:LL_ACK_TIMEOUT[6] PCIE:DRP4A[7] PCIE:LL_ACK_TIMEOUT[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4A[4] PCIE:LL_ACK_TIMEOUT[4] PCIE:DRP4A[5] PCIE:LL_ACK_TIMEOUT[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4A[2] PCIE:LL_ACK_TIMEOUT[2] PCIE:DRP4A[3] PCIE:LL_ACK_TIMEOUT[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4A[0] PCIE:LL_ACK_TIMEOUT[0] PCIE:DRP4A[1] PCIE:LL_ACK_TIMEOUT[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP49[14] PCIE:DRP49[15]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CRM_MODULE_RSTS[5] PCIE:DRP49[12] PCIE:CRM_MODULE_RSTS[6] PCIE:DRP49[13]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CRM_MODULE_RSTS[3] PCIE:DRP49[10] PCIE:CRM_MODULE_RSTS[4] PCIE:DRP49[11]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:CRM_MODULE_RSTS[1] PCIE:DRP49[8] PCIE:CRM_MODULE_RSTS[2] PCIE:DRP49[9]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP49[6] PCIE:USER_CLK_FREQ[2] PCIE:CRM_MODULE_RSTS[0] PCIE:DRP49[7]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP49[4] PCIE:USER_CLK_FREQ[0] PCIE:DRP49[5] PCIE:USER_CLK_FREQ[1]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP49[2] PCIE:VSEC_CAP_VERSION[2] PCIE:DRP49[3] PCIE:VSEC_CAP_VERSION[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP49[0] PCIE:VSEC_CAP_VERSION[0] PCIE:DRP49[1] PCIE:VSEC_CAP_VERSION[1]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP48[14] PCIE:DRP48[15]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP48[12] PCIE:VSEC_CAP_NEXTPTR[11] PCIE:DRP48[13] PCIE:VSEC_CAP_ON
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP48[10] PCIE:VSEC_CAP_NEXTPTR[9] PCIE:DRP48[11] PCIE:VSEC_CAP_NEXTPTR[10]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP48[8] PCIE:VSEC_CAP_NEXTPTR[7] PCIE:DRP48[9] PCIE:VSEC_CAP_NEXTPTR[8]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP48[6] PCIE:VSEC_CAP_NEXTPTR[5] PCIE:DRP48[7] PCIE:VSEC_CAP_NEXTPTR[6]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP48[4] PCIE:VSEC_CAP_NEXTPTR[3] PCIE:DRP48[5] PCIE:VSEC_CAP_NEXTPTR[4]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP48[2] PCIE:VSEC_CAP_NEXTPTR[1] PCIE:DRP48[3] PCIE:VSEC_CAP_NEXTPTR[2]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP48[0] PCIE:VSEC_CAP_IS_LINK_VISIBLE PCIE:DRP48[1] PCIE:VSEC_CAP_NEXTPTR[0]
virtex6 PCIE bittile 13
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP53[14] PCIE:DRP53[15]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP53[12] PCIE:DRP53[13]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP53[10] PCIE:VC_CAP_VERSION[3] PCIE:DRP53[11] PCIE:VC0_CPL_INFINITE
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP53[8] PCIE:VC_CAP_VERSION[1] PCIE:DRP53[9] PCIE:VC_CAP_VERSION[2]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP53[6] PCIE:TL_TX_RAM_WRITE_LATENCY PCIE:DRP53[7] PCIE:VC_CAP_VERSION[0]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP53[4] PCIE:TL_TX_RAM_RDATA_LATENCY[0] PCIE:DRP53[5] PCIE:TL_TX_RAM_RDATA_LATENCY[1]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP53[2] PCIE:TL_RBYPASS PCIE:DRP53[3] PCIE:TL_TX_RAM_RADDR_LATENCY
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP53[0] PCIE:TL_TFC_DISABLE PCIE:DRP53[1] PCIE:TL_TX_CHECKS_DISABLE
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP52[14] PCIE:TL_RX_RAM_RDATA_LATENCY[1] PCIE:DRP52[15] PCIE:TL_RX_RAM_WRITE_LATENCY
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP52[12] PCIE:TL_RX_RAM_RADDR_LATENCY PCIE:DRP52[13] PCIE:TL_RX_RAM_RDATA_LATENCY[0]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP52[10] PCIE:ENABLE_MSG_ROUTE[10] PCIE:DRP52[11] PCIE:ENABLE_RX_TD_ECRC_TRIM
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP52[8] PCIE:ENABLE_MSG_ROUTE[8] PCIE:DRP52[9] PCIE:ENABLE_MSG_ROUTE[9]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP52[6] PCIE:ENABLE_MSG_ROUTE[6] PCIE:DRP52[7] PCIE:ENABLE_MSG_ROUTE[7]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP52[4] PCIE:ENABLE_MSG_ROUTE[4] PCIE:DRP52[5] PCIE:ENABLE_MSG_ROUTE[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP52[2] PCIE:ENABLE_MSG_ROUTE[2] PCIE:DRP52[3] PCIE:ENABLE_MSG_ROUTE[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP52[0] PCIE:ENABLE_MSG_ROUTE[0] PCIE:DRP52[1] PCIE:ENABLE_MSG_ROUTE[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP51[14] PCIE:DRP51[15]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP51[12] PCIE:DRP51[13]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DISABLE_ID_CHECK PCIE:DRP51[10] PCIE:DISABLE_RX_TC_FILTER PCIE:DRP51[11]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DISABLE_ASPM_L1_TIMER PCIE:DRP51[8] PCIE:DISABLE_BAR_FILTERING PCIE:DRP51[9]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DNSTREAM_LINK_NUM[6] PCIE:DRP51[6] PCIE:DNSTREAM_LINK_NUM[7] PCIE:DRP51[7]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DNSTREAM_LINK_NUM[4] PCIE:DRP51[4] PCIE:DNSTREAM_LINK_NUM[5] PCIE:DRP51[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DNSTREAM_LINK_NUM[2] PCIE:DRP51[2] PCIE:DNSTREAM_LINK_NUM[3] PCIE:DRP51[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DNSTREAM_LINK_NUM[0] PCIE:DRP51[0] PCIE:DNSTREAM_LINK_NUM[1] PCIE:DRP51[1]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP50[14] PCIE:UPSTREAM_FACING PCIE:DRP50[15] PCIE:EXIT_LOOPBACK_ON_EI
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP50[12] PCIE:PL_FAST_TRAIN PCIE:DRP50[13] PCIE:UPCONFIG_CAPABLE
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP50[10] PCIE:PL_AUTO_CONFIG[1] PCIE:DRP50[11] PCIE:PL_AUTO_CONFIG[2]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:ALLOW_X8_GEN2 PCIE:DRP50[8] PCIE:DRP50[9] PCIE:PL_AUTO_CONFIG[0]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP50[6] PCIE:N_FTS_GEN2[6] PCIE:DRP50[7] PCIE:N_FTS_GEN2[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP50[4] PCIE:N_FTS_GEN2[4] PCIE:DRP50[5] PCIE:N_FTS_GEN2[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP50[2] PCIE:N_FTS_GEN2[2] PCIE:DRP50[3] PCIE:N_FTS_GEN2[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP50[0] PCIE:N_FTS_GEN2[0] PCIE:DRP50[1] PCIE:N_FTS_GEN2[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4F[14] PCIE:N_FTS_GEN1[6] PCIE:DRP4F[15] PCIE:N_FTS_GEN1[7]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4F[12] PCIE:N_FTS_GEN1[4] PCIE:DRP4F[13] PCIE:N_FTS_GEN1[5]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4F[10] PCIE:N_FTS_GEN1[2] PCIE:DRP4F[11] PCIE:N_FTS_GEN1[3]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4F[8] PCIE:N_FTS_GEN1[0] PCIE:DRP4F[9] PCIE:N_FTS_GEN1[1]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4F[6] PCIE:N_FTS_COMCLK_GEN2[6] PCIE:DRP4F[7] PCIE:N_FTS_COMCLK_GEN2[7]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4F[4] PCIE:N_FTS_COMCLK_GEN2[4] PCIE:DRP4F[5] PCIE:N_FTS_COMCLK_GEN2[5]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4F[2] PCIE:N_FTS_COMCLK_GEN2[2] PCIE:DRP4F[3] PCIE:N_FTS_COMCLK_GEN2[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4F[0] PCIE:N_FTS_COMCLK_GEN2[0] PCIE:DRP4F[1] PCIE:N_FTS_COMCLK_GEN2[1]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4E[14] PCIE:DRP4E[15]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4E[12] PCIE:N_FTS_COMCLK_GEN1[6] PCIE:DRP4E[13] PCIE:N_FTS_COMCLK_GEN1[7]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4E[10] PCIE:N_FTS_COMCLK_GEN1[4] PCIE:DRP4E[11] PCIE:N_FTS_COMCLK_GEN1[5]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4E[8] PCIE:N_FTS_COMCLK_GEN1[2] PCIE:DRP4E[9] PCIE:N_FTS_COMCLK_GEN1[3]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4E[6] PCIE:N_FTS_COMCLK_GEN1[0] PCIE:DRP4E[7] PCIE:N_FTS_COMCLK_GEN1[1]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4E[4] PCIE:LTSSM_MAX_LINK_WIDTH[4] PCIE:DRP4E[5] PCIE:LTSSM_MAX_LINK_WIDTH[5]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4E[2] PCIE:LTSSM_MAX_LINK_WIDTH[2] PCIE:DRP4E[3] PCIE:LTSSM_MAX_LINK_WIDTH[3]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP4E[0] PCIE:LTSSM_MAX_LINK_WIDTH[0] PCIE:DRP4E[1] PCIE:LTSSM_MAX_LINK_WIDTH[1]
virtex6 PCIE bittile 14
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP59[14] PCIE:PGL4_LANE[2] PCIE:DRP59[15]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP59[12] PCIE:PGL4_LANE[0] PCIE:DRP59[13] PCIE:PGL4_LANE[1]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP59[10] PCIE:PGL3_LANE[1] PCIE:DRP59[11] PCIE:PGL3_LANE[2]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP59[8] PCIE:PGL2_LANE[2] PCIE:DRP59[9] PCIE:PGL3_LANE[0]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP59[6] PCIE:PGL2_LANE[0] PCIE:DRP59[7] PCIE:PGL2_LANE[1]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP59[4] PCIE:PGL1_LANE[1] PCIE:DRP59[5] PCIE:PGL1_LANE[2]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP59[2] PCIE:PGL0_LANE[2] PCIE:DRP59[3] PCIE:PGL1_LANE[0]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP59[0] PCIE:PGL0_LANE[0] PCIE:DRP59[1] PCIE:PGL0_LANE[1]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP58[14] PCIE:RECRC_CHK_TRIM PCIE:DRP58[15] PCIE:UR_INV_REQ
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP58[12] PCIE:RECRC_CHK[0] PCIE:DRP58[13] PCIE:RECRC_CHK[1]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP58[10] PCIE:VC0_TX_LASTPACKET[3] PCIE:DRP58[11] PCIE:VC0_TX_LASTPACKET[4]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP58[8] PCIE:VC0_TX_LASTPACKET[1] PCIE:DRP58[9] PCIE:VC0_TX_LASTPACKET[2]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP58[6] PCIE:VC0_TOTAL_CREDITS_PH[6] PCIE:DRP58[7] PCIE:VC0_TX_LASTPACKET[0]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP58[4] PCIE:VC0_TOTAL_CREDITS_PH[4] PCIE:DRP58[5] PCIE:VC0_TOTAL_CREDITS_PH[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP58[2] PCIE:VC0_TOTAL_CREDITS_PH[2] PCIE:DRP58[3] PCIE:VC0_TOTAL_CREDITS_PH[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP58[0] PCIE:VC0_TOTAL_CREDITS_PH[0] PCIE:DRP58[1] PCIE:VC0_TOTAL_CREDITS_PH[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP57[14] PCIE:DRP57[15]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP57[12] PCIE:DRP57[13]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP57[10] PCIE:VC0_TOTAL_CREDITS_PD[10] PCIE:DRP57[11]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP57[8] PCIE:VC0_TOTAL_CREDITS_PD[8] PCIE:DRP57[9] PCIE:VC0_TOTAL_CREDITS_PD[9]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP57[6] PCIE:VC0_TOTAL_CREDITS_PD[6] PCIE:DRP57[7] PCIE:VC0_TOTAL_CREDITS_PD[7]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP57[4] PCIE:VC0_TOTAL_CREDITS_PD[4] PCIE:DRP57[5] PCIE:VC0_TOTAL_CREDITS_PD[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP57[2] PCIE:VC0_TOTAL_CREDITS_PD[2] PCIE:DRP57[3] PCIE:VC0_TOTAL_CREDITS_PD[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP57[0] PCIE:VC0_TOTAL_CREDITS_PD[0] PCIE:DRP57[1] PCIE:VC0_TOTAL_CREDITS_PD[1]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP56[14] PCIE:DRP56[15]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP56[12] PCIE:VC0_TOTAL_CREDITS_NPH[5] PCIE:DRP56[13] PCIE:VC0_TOTAL_CREDITS_NPH[6]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP56[10] PCIE:VC0_TOTAL_CREDITS_NPH[3] PCIE:DRP56[11] PCIE:VC0_TOTAL_CREDITS_NPH[4]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP56[8] PCIE:VC0_TOTAL_CREDITS_NPH[1] PCIE:DRP56[9] PCIE:VC0_TOTAL_CREDITS_NPH[2]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP56[6] PCIE:VC0_TOTAL_CREDITS_CH[6] PCIE:DRP56[7] PCIE:VC0_TOTAL_CREDITS_NPH[0]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP56[4] PCIE:VC0_TOTAL_CREDITS_CH[4] PCIE:DRP56[5] PCIE:VC0_TOTAL_CREDITS_CH[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP56[2] PCIE:VC0_TOTAL_CREDITS_CH[2] PCIE:DRP56[3] PCIE:VC0_TOTAL_CREDITS_CH[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP56[0] PCIE:VC0_TOTAL_CREDITS_CH[0] PCIE:DRP56[1] PCIE:VC0_TOTAL_CREDITS_CH[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP55[14] PCIE:DRP55[15]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP55[12] PCIE:DRP55[13]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP55[10] PCIE:VC0_TOTAL_CREDITS_CD[10] PCIE:DRP55[11]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP55[8] PCIE:VC0_TOTAL_CREDITS_CD[8] PCIE:DRP55[9] PCIE:VC0_TOTAL_CREDITS_CD[9]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP55[6] PCIE:VC0_TOTAL_CREDITS_CD[6] PCIE:DRP55[7] PCIE:VC0_TOTAL_CREDITS_CD[7]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP55[4] PCIE:VC0_TOTAL_CREDITS_CD[4] PCIE:DRP55[5] PCIE:VC0_TOTAL_CREDITS_CD[5]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP55[2] PCIE:VC0_TOTAL_CREDITS_CD[2] PCIE:DRP55[3] PCIE:VC0_TOTAL_CREDITS_CD[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP55[0] PCIE:VC0_TOTAL_CREDITS_CD[0] PCIE:DRP55[1] PCIE:VC0_TOTAL_CREDITS_CD[1]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP54[14] PCIE:DRP54[15]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP54[12] PCIE:VC0_RX_RAM_LIMIT[12] PCIE:DRP54[13]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP54[10] PCIE:VC0_RX_RAM_LIMIT[10] PCIE:DRP54[11] PCIE:VC0_RX_RAM_LIMIT[11]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP54[8] PCIE:VC0_RX_RAM_LIMIT[8] PCIE:DRP54[9] PCIE:VC0_RX_RAM_LIMIT[9]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP54[6] PCIE:VC0_RX_RAM_LIMIT[6] PCIE:DRP54[7] PCIE:VC0_RX_RAM_LIMIT[7]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP54[4] PCIE:VC0_RX_RAM_LIMIT[4] PCIE:DRP54[5] PCIE:VC0_RX_RAM_LIMIT[5]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP54[2] PCIE:VC0_RX_RAM_LIMIT[2] PCIE:DRP54[3] PCIE:VC0_RX_RAM_LIMIT[3]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP54[0] PCIE:VC0_RX_RAM_LIMIT[0] PCIE:DRP54[1] PCIE:VC0_RX_RAM_LIMIT[1]
virtex6 PCIE bittile 15
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5F[14] PCIE:SPARE_WORD0[30] PCIE:DRP5F[15] PCIE:SPARE_WORD0[31]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5F[12] PCIE:SPARE_WORD0[28] PCIE:DRP5F[13] PCIE:SPARE_WORD0[29]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5F[10] PCIE:SPARE_WORD0[26] PCIE:DRP5F[11] PCIE:SPARE_WORD0[27]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5F[8] PCIE:SPARE_WORD0[24] PCIE:DRP5F[9] PCIE:SPARE_WORD0[25]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5F[6] PCIE:SPARE_WORD0[22] PCIE:DRP5F[7] PCIE:SPARE_WORD0[23]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5F[4] PCIE:SPARE_WORD0[20] PCIE:DRP5F[5] PCIE:SPARE_WORD0[21]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5F[2] PCIE:SPARE_WORD0[18] PCIE:DRP5F[3] PCIE:SPARE_WORD0[19]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5F[0] PCIE:SPARE_WORD0[16] PCIE:DRP5F[1] PCIE:SPARE_WORD0[17]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5E[14] PCIE:SPARE_WORD0[14] PCIE:DRP5E[15] PCIE:SPARE_WORD0[15]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5E[12] PCIE:SPARE_WORD0[12] PCIE:DRP5E[13] PCIE:SPARE_WORD0[13]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5E[10] PCIE:SPARE_WORD0[10] PCIE:DRP5E[11] PCIE:SPARE_WORD0[11]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5E[8] PCIE:SPARE_WORD0[8] PCIE:DRP5E[9] PCIE:SPARE_WORD0[9]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5E[6] PCIE:SPARE_WORD0[6] PCIE:DRP5E[7] PCIE:SPARE_WORD0[7]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5E[4] PCIE:SPARE_WORD0[4] PCIE:DRP5E[5] PCIE:SPARE_WORD0[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5E[2] PCIE:SPARE_WORD0[2] PCIE:DRP5E[3] PCIE:SPARE_WORD0[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5E[0] PCIE:SPARE_WORD0[0] PCIE:DRP5E[1] PCIE:SPARE_WORD0[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5D[14] PCIE:DRP5D[15]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5D[12] PCIE:DRP5D[13]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5D[10] PCIE:DRP5D[11]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5D[8] PCIE:DRP5D[9]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5D[6] PCIE:SPARE_BYTE3[6] PCIE:DRP5D[7] PCIE:SPARE_BYTE3[7]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5D[4] PCIE:SPARE_BYTE3[4] PCIE:DRP5D[5] PCIE:SPARE_BYTE3[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5D[2] PCIE:SPARE_BYTE3[2] PCIE:DRP5D[3] PCIE:SPARE_BYTE3[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5D[0] PCIE:SPARE_BYTE3[0] PCIE:DRP5D[1] PCIE:SPARE_BYTE3[1]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5C[14] PCIE:SPARE_BYTE2[6] PCIE:DRP5C[15] PCIE:SPARE_BYTE2[7]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5C[12] PCIE:SPARE_BYTE2[4] PCIE:DRP5C[13] PCIE:SPARE_BYTE2[5]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5C[10] PCIE:SPARE_BYTE2[2] PCIE:DRP5C[11] PCIE:SPARE_BYTE2[3]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5C[8] PCIE:SPARE_BYTE2[0] PCIE:DRP5C[9] PCIE:SPARE_BYTE2[1]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5C[6] PCIE:SPARE_BYTE1[6] PCIE:DRP5C[7] PCIE:SPARE_BYTE1[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5C[4] PCIE:SPARE_BYTE1[4] PCIE:DRP5C[5] PCIE:SPARE_BYTE1[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5C[2] PCIE:SPARE_BYTE1[2] PCIE:DRP5C[3] PCIE:SPARE_BYTE1[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5C[0] PCIE:SPARE_BYTE1[0] PCIE:DRP5C[1] PCIE:SPARE_BYTE1[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5B[14] PCIE:DRP5B[15]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5B[12] PCIE:DRP5B[13]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5B[10] PCIE:SPARE_BYTE0[7] PCIE:DRP5B[11]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5B[8] PCIE:SPARE_BYTE0[5] PCIE:DRP5B[9] PCIE:SPARE_BYTE0[6]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5B[6] PCIE:SPARE_BYTE0[3] PCIE:DRP5B[7] PCIE:SPARE_BYTE0[4]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5B[4] PCIE:SPARE_BYTE0[1] PCIE:DRP5B[5] PCIE:SPARE_BYTE0[2]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5B[2] PCIE:SPARE_BIT8 PCIE:DRP5B[3] PCIE:SPARE_BYTE0[0]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5B[0] PCIE:SPARE_BIT6 PCIE:DRP5B[1] PCIE:SPARE_BIT7
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5A[14] PCIE:SPARE_BIT4 PCIE:DRP5A[15] PCIE:SPARE_BIT5
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5A[12] PCIE:SPARE_BIT2 PCIE:DRP5A[13] PCIE:SPARE_BIT3
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5A[10] PCIE:SPARE_BIT0 PCIE:DRP5A[11] PCIE:SPARE_BIT1
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5A[8] PCIE:PGL7_LANE[2] PCIE:DRP5A[9] PCIE:TEST_MODE_PIN_CHAR
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5A[6] PCIE:PGL7_LANE[0] PCIE:DRP5A[7] PCIE:PGL7_LANE[1]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5A[4] PCIE:PGL6_LANE[1] PCIE:DRP5A[5] PCIE:PGL6_LANE[2]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5A[2] PCIE:PGL5_LANE[2] PCIE:DRP5A[3] PCIE:PGL6_LANE[0]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP5A[0] PCIE:PGL5_LANE[0] PCIE:DRP5A[1] PCIE:PGL5_LANE[1]
virtex6 PCIE bittile 16
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP65[14] PCIE:SPARE_WORD3[30] PCIE:DRP65[15] PCIE:SPARE_WORD3[31]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP65[12] PCIE:SPARE_WORD3[28] PCIE:DRP65[13] PCIE:SPARE_WORD3[29]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP65[10] PCIE:SPARE_WORD3[26] PCIE:DRP65[11] PCIE:SPARE_WORD3[27]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP65[8] PCIE:SPARE_WORD3[24] PCIE:DRP65[9] PCIE:SPARE_WORD3[25]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP65[6] PCIE:SPARE_WORD3[22] PCIE:DRP65[7] PCIE:SPARE_WORD3[23]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP65[4] PCIE:SPARE_WORD3[20] PCIE:DRP65[5] PCIE:SPARE_WORD3[21]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP65[2] PCIE:SPARE_WORD3[18] PCIE:DRP65[3] PCIE:SPARE_WORD3[19]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP65[0] PCIE:SPARE_WORD3[16] PCIE:DRP65[1] PCIE:SPARE_WORD3[17]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP64[14] PCIE:SPARE_WORD3[14] PCIE:DRP64[15] PCIE:SPARE_WORD3[15]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP64[12] PCIE:SPARE_WORD3[12] PCIE:DRP64[13] PCIE:SPARE_WORD3[13]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP64[10] PCIE:SPARE_WORD3[10] PCIE:DRP64[11] PCIE:SPARE_WORD3[11]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP64[8] PCIE:SPARE_WORD3[8] PCIE:DRP64[9] PCIE:SPARE_WORD3[9]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP64[6] PCIE:SPARE_WORD3[6] PCIE:DRP64[7] PCIE:SPARE_WORD3[7]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP64[4] PCIE:SPARE_WORD3[4] PCIE:DRP64[5] PCIE:SPARE_WORD3[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP64[2] PCIE:SPARE_WORD3[2] PCIE:DRP64[3] PCIE:SPARE_WORD3[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP64[0] PCIE:SPARE_WORD3[0] PCIE:DRP64[1] PCIE:SPARE_WORD3[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP63[14] PCIE:SPARE_WORD2[30] PCIE:DRP63[15] PCIE:SPARE_WORD2[31]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP63[12] PCIE:SPARE_WORD2[28] PCIE:DRP63[13] PCIE:SPARE_WORD2[29]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP63[10] PCIE:SPARE_WORD2[26] PCIE:DRP63[11] PCIE:SPARE_WORD2[27]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP63[8] PCIE:SPARE_WORD2[24] PCIE:DRP63[9] PCIE:SPARE_WORD2[25]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP63[6] PCIE:SPARE_WORD2[22] PCIE:DRP63[7] PCIE:SPARE_WORD2[23]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP63[4] PCIE:SPARE_WORD2[20] PCIE:DRP63[5] PCIE:SPARE_WORD2[21]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP63[2] PCIE:SPARE_WORD2[18] PCIE:DRP63[3] PCIE:SPARE_WORD2[19]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP63[0] PCIE:SPARE_WORD2[16] PCIE:DRP63[1] PCIE:SPARE_WORD2[17]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP62[14] PCIE:SPARE_WORD2[14] PCIE:DRP62[15] PCIE:SPARE_WORD2[15]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP62[12] PCIE:SPARE_WORD2[12] PCIE:DRP62[13] PCIE:SPARE_WORD2[13]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP62[10] PCIE:SPARE_WORD2[10] PCIE:DRP62[11] PCIE:SPARE_WORD2[11]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP62[8] PCIE:SPARE_WORD2[8] PCIE:DRP62[9] PCIE:SPARE_WORD2[9]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP62[6] PCIE:SPARE_WORD2[6] PCIE:DRP62[7] PCIE:SPARE_WORD2[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP62[4] PCIE:SPARE_WORD2[4] PCIE:DRP62[5] PCIE:SPARE_WORD2[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP62[2] PCIE:SPARE_WORD2[2] PCIE:DRP62[3] PCIE:SPARE_WORD2[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP62[0] PCIE:SPARE_WORD2[0] PCIE:DRP62[1] PCIE:SPARE_WORD2[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP61[14] PCIE:SPARE_WORD1[30] PCIE:DRP61[15] PCIE:SPARE_WORD1[31]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP61[12] PCIE:SPARE_WORD1[28] PCIE:DRP61[13] PCIE:SPARE_WORD1[29]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP61[10] PCIE:SPARE_WORD1[26] PCIE:DRP61[11] PCIE:SPARE_WORD1[27]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP61[8] PCIE:SPARE_WORD1[24] PCIE:DRP61[9] PCIE:SPARE_WORD1[25]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP61[6] PCIE:SPARE_WORD1[22] PCIE:DRP61[7] PCIE:SPARE_WORD1[23]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP61[4] PCIE:SPARE_WORD1[20] PCIE:DRP61[5] PCIE:SPARE_WORD1[21]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP61[2] PCIE:SPARE_WORD1[18] PCIE:DRP61[3] PCIE:SPARE_WORD1[19]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP61[0] PCIE:SPARE_WORD1[16] PCIE:DRP61[1] PCIE:SPARE_WORD1[17]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP60[14] PCIE:SPARE_WORD1[14] PCIE:DRP60[15] PCIE:SPARE_WORD1[15]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP60[12] PCIE:SPARE_WORD1[12] PCIE:DRP60[13] PCIE:SPARE_WORD1[13]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP60[10] PCIE:SPARE_WORD1[10] PCIE:DRP60[11] PCIE:SPARE_WORD1[11]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP60[8] PCIE:SPARE_WORD1[8] PCIE:DRP60[9] PCIE:SPARE_WORD1[9]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP60[6] PCIE:SPARE_WORD1[6] PCIE:DRP60[7] PCIE:SPARE_WORD1[7]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP60[4] PCIE:SPARE_WORD1[4] PCIE:DRP60[5] PCIE:SPARE_WORD1[5]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP60[2] PCIE:SPARE_WORD1[2] PCIE:DRP60[3] PCIE:SPARE_WORD1[3]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP60[0] PCIE:SPARE_WORD1[0] PCIE:DRP60[1] PCIE:SPARE_WORD1[1]
virtex6 PCIE bittile 17
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6B[14] PCIE:DRP6B[15]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6B[12] PCIE:DRP6B[13]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6B[10] PCIE:DRP6B[11]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6B[8] PCIE:DRP6B[9]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6B[6] PCIE:DRP6B[7]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6B[4] PCIE:DRP6B[5]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6B[2] PCIE:DRP6B[3]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6B[0] PCIE:DRP6B[1]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6A[14] PCIE:DRP6A[15]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6A[12] PCIE:DRP6A[13]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6A[10] PCIE:DRP6A[11]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6A[8] PCIE:DRP6A[9]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6A[6] PCIE:DRP6A[7]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6A[4] PCIE:DRP6A[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6A[2] PCIE:DRP6A[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6A[0] PCIE:DRP6A[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP69[14] PCIE:DRP69[15]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP69[12] PCIE:DRP69[13]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP69[10] PCIE:DRP69[11]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP69[8] PCIE:DRP69[9]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP69[6] PCIE:DRP69[7]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP69[4] PCIE:DRP69[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP69[2] PCIE:DRP69[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP69[0] PCIE:DRP69[1]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP68[14] PCIE:DRP68[15]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP68[12] PCIE:DRP68[13]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP68[10] PCIE:DRP68[11]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP68[8] PCIE:DRP68[9]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP68[6] PCIE:DRP68[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP68[4] PCIE:DRP68[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP68[2] PCIE:DRP68[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP68[0] PCIE:DRP68[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP67[14] PCIE:DRP67[15]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP67[12] PCIE:DRP67[13]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP67[10] PCIE:DRP67[11]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP67[8] PCIE:DRP67[9]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP67[6] PCIE:DRP67[7]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP67[4] PCIE:DRP67[5]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP67[2] PCIE:DRP67[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP67[0] PCIE:DRP67[1]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP66[14] PCIE:DRP66[15]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP66[12] PCIE:DRP66[13]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP66[10] PCIE:DRP66[11]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP66[8] PCIE:DRP66[9]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP66[6] PCIE:DRP66[7]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP66[4] PCIE:DRP66[5]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP66[2] PCIE:DRP66[3]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP66[0] PCIE:DRP66[1]
virtex6 PCIE bittile 18
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP71[14] PCIE:DRP71[15]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP71[12] PCIE:DRP71[13]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP71[10] PCIE:DRP71[11]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP71[8] PCIE:DRP71[9]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP71[6] PCIE:DRP71[7]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP71[4] PCIE:DRP71[5]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP71[2] PCIE:DRP71[3]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP71[0] PCIE:DRP71[1]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP70[14] PCIE:DRP70[15]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP70[12] PCIE:DRP70[13]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP70[10] PCIE:DRP70[11]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP70[8] PCIE:DRP70[9]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP70[6] PCIE:DRP70[7]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP70[4] PCIE:DRP70[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP70[2] PCIE:DRP70[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP70[0] PCIE:DRP70[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6F[14] PCIE:DRP6F[15]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6F[12] PCIE:DRP6F[13]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6F[10] PCIE:DRP6F[11]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6F[8] PCIE:DRP6F[9]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6F[6] PCIE:DRP6F[7]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6F[4] PCIE:DRP6F[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6F[2] PCIE:DRP6F[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6F[0] PCIE:DRP6F[1]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6E[14] PCIE:DRP6E[15]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6E[12] PCIE:DRP6E[13]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6E[10] PCIE:DRP6E[11]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6E[8] PCIE:DRP6E[9]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6E[6] PCIE:DRP6E[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6E[4] PCIE:DRP6E[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6E[2] PCIE:DRP6E[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6E[0] PCIE:DRP6E[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6D[14] PCIE:DRP6D[15]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6D[12] PCIE:DRP6D[13]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6D[10] PCIE:DRP6D[11]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6D[8] PCIE:DRP6D[9]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6D[6] PCIE:DRP6D[7]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6D[4] PCIE:DRP6D[5]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6D[2] PCIE:DRP6D[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6D[0] PCIE:DRP6D[1]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6C[14] PCIE:DRP6C[15]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6C[12] PCIE:DRP6C[13]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6C[10] PCIE:DRP6C[11]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6C[8] PCIE:DRP6C[9]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6C[6] PCIE:DRP6C[7]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6C[4] PCIE:DRP6C[5]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6C[2] PCIE:DRP6C[3]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP6C[0] PCIE:DRP6C[1]
virtex6 PCIE bittile 19
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
47 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP77[14] PCIE:DRP77[15]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP77[12] PCIE:DRP77[13]
45 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP77[10] PCIE:DRP77[11]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP77[8] PCIE:DRP77[9]
43 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP77[6] PCIE:DRP77[7]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP77[4] PCIE:DRP77[5]
41 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP77[2] PCIE:DRP77[3]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP77[0] PCIE:DRP77[1]
39 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP76[14] PCIE:DRP76[15]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP76[12] PCIE:DRP76[13]
37 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP76[10] PCIE:DRP76[11]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP76[8] PCIE:DRP76[9]
35 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP76[6] PCIE:DRP76[7]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP76[4] PCIE:DRP76[5]
33 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP76[2] PCIE:DRP76[3]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP76[0] PCIE:DRP76[1]
31 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP75[14] PCIE:DRP75[15]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP75[12] PCIE:DRP75[13]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP75[10] PCIE:DRP75[11]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP75[8] PCIE:DRP75[9]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP75[6] PCIE:DRP75[7]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP75[4] PCIE:DRP75[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP75[2] PCIE:DRP75[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP75[0] PCIE:DRP75[1]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP74[14] PCIE:DRP74[15]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP74[12] PCIE:DRP74[13]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP74[10] PCIE:DRP74[11]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP74[8] PCIE:DRP74[9]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP74[6] PCIE:DRP74[7]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP74[4] PCIE:DRP74[5]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP74[2] PCIE:DRP74[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP74[0] PCIE:DRP74[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP73[14] PCIE:DRP73[15]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP73[12] PCIE:DRP73[13]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP73[10] PCIE:DRP73[11]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP73[8] PCIE:DRP73[9]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP73[6] PCIE:DRP73[7]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP73[4] PCIE:DRP73[5]
9 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP73[2] PCIE:DRP73[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP73[0] PCIE:DRP73[1]
7 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP72[14] PCIE:DRP72[15]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP72[12] PCIE:DRP72[13]
5 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP72[10] PCIE:DRP72[11]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP72[8] PCIE:DRP72[9]
3 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP72[6] PCIE:DRP72[7]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP72[4] PCIE:DRP72[5]
1 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP72[2] PCIE:DRP72[3]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - PCIE:DRP72[0] PCIE:DRP72[1]
PCIE:AER_BASE_PTR 0.27.29 0.26.29 0.27.28 0.26.28 0.27.27 0.26.27 0.27.26 0.26.26 0.27.25 0.26.25 0.27.24 0.26.24
PCIE:AER_CAP_NEXTPTR 0.27.37 0.26.37 0.27.36 0.26.36 0.27.35 0.26.35 0.27.34 0.26.34 0.27.33 0.26.33 0.27.32 0.26.32
PCIE:DSN_BASE_PTR 4.27.29 4.26.29 4.27.28 4.26.28 4.27.27 4.26.27 4.27.26 4.26.26 4.27.25 4.26.25 4.27.24 4.26.24
PCIE:DSN_CAP_NEXTPTR 4.27.45 4.26.45 4.27.44 4.26.44 4.27.43 4.26.43 4.27.42 4.26.42 4.27.41 4.26.41 4.27.40 4.26.40
PCIE:VC_BASE_PTR 10.27.29 10.26.29 10.27.28 10.26.28 10.27.27 10.26.27 10.27.26 10.26.26 10.27.25 10.26.25 10.27.24 10.26.24
PCIE:VC_CAP_NEXTPTR 10.27.37 10.26.37 10.27.36 10.26.36 10.27.35 10.26.35 10.27.34 10.26.34 10.27.33 10.26.33 10.27.32 10.26.32
PCIE:VSEC_BASE_PTR 11.27.21 11.26.21 11.27.20 11.26.20 11.27.19 11.26.19 11.27.18 11.26.18 11.27.17 11.26.17 11.27.16 11.26.16
PCIE:VSEC_CAP_HDR_LENGTH 11.27.37 11.26.37 11.27.36 11.26.36 11.27.35 11.26.35 11.27.34 11.26.34 11.27.33 11.26.33 11.27.32 11.26.32
PCIE:VSEC_CAP_NEXTPTR 12.26.6 12.27.5 12.26.5 12.27.4 12.26.4 12.27.3 12.26.3 12.27.2 12.26.2 12.27.1 12.26.1 12.27.0
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
PCIE:AER_CAP_ECRC_CHECK_CAPABLE 0.26.0
PCIE:AER_CAP_ECRC_GEN_CAPABLE 0.27.0
PCIE:AER_CAP_ON 0.26.38
PCIE:AER_CAP_PERMIT_ROOTERR_UPDATE 0.26.21
PCIE:ALLOW_X8_GEN2 13.26.20
PCIE:CMD_INTX_IMPLEMENTED 3.26.44
PCIE:CPL_TIMEOUT_DISABLE_SUPPORTED 3.27.44
PCIE:DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE 3.26.47
PCIE:DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE 3.27.47
PCIE:DEV_CAP_EXT_TAG_SUPPORTED 4.26.3
PCIE:DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE 4.27.3
PCIE:DEV_CAP_ROLE_BASED_ERROR 4.27.6
PCIE:DEV_CONTROL_AUX_POWER_SUPPORTED 4.26.12
PCIE:DISABLE_ASPM_L1_TIMER 13.26.28
PCIE:DISABLE_BAR_FILTERING 13.27.28
PCIE:DISABLE_ID_CHECK 13.26.29
PCIE:DISABLE_LANE_REVERSAL 12.26.41
PCIE:DISABLE_RX_TC_FILTER 13.27.29
PCIE:DISABLE_SCRAMBLING 12.27.41
PCIE:DSN_CAP_ON 4.26.46
PCIE:ENABLE_RX_TD_ECRC_TRIM 13.27.37
PCIE:ENTER_RVRY_EI_L0 12.26.42
PCIE:EXIT_LOOPBACK_ON_EI 13.27.23
PCIE:IS_SWITCH 5.26.24
PCIE:LINK_CAP_CLOCK_POWER_MANAGEMENT 5.27.30
PCIE:LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP 5.26.31
PCIE:LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 5.27.44
PCIE:LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE 6.26.0
PCIE:LINK_CONTROL_RCB 6.27.0
PCIE:LINK_CTRL2_DEEMPHASIS 6.26.1
PCIE:LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE 6.27.1
PCIE:LINK_STATUS_SLOT_CLOCK_CONFIG 6.26.4
PCIE:LL_ACK_TIMEOUT_EN 12.27.23
PCIE:LL_REPLAY_TIMEOUT_EN 12.27.39
PCIE:MSIX_CAP_ON 6.26.44
PCIE:MSI_CAP_64_BIT_ADDR_CAPABLE 6.26.12
PCIE:MSI_CAP_MULTIMSG_EXTENSION 6.26.20
PCIE:MSI_CAP_ON 6.26.28
PCIE:MSI_CAP_PER_VECTOR_MASKING_CAPABLE 6.27.28
PCIE:PCIE_CAP_ON 8.26.12
PCIE:PCIE_CAP_SLOT_IMPLEMENTED 8.27.13
PCIE:PL_FAST_TRAIN 13.26.22
PCIE:PM_CAP_D1SUPPORT 8.27.21
PCIE:PM_CAP_D2SUPPORT 8.26.22
PCIE:PM_CAP_DSI 8.27.22
PCIE:PM_CAP_ON 8.26.32
PCIE:PM_CAP_PME_CLOCK 8.27.32
PCIE:PM_CAP_RSVD_04 8.27.35
PCIE:PM_CSR_B2B3 8.27.37
PCIE:PM_CSR_BPCCEN 8.26.38
PCIE:PM_CSR_NOSOFTRST 8.27.38
PCIE:RECRC_CHK_TRIM 14.26.39
PCIE:ROOT_CAP_CRS_SW_VISIBILITY 9.26.36
PCIE:SELECT_DLL_IF 9.27.36
PCIE:SLOT_CAP_ATT_BUTTON_PRESENT 9.26.37
PCIE:SLOT_CAP_ATT_INDICATOR_PRESENT 9.27.37
PCIE:SLOT_CAP_ELEC_INTERLOCK_PRESENT 9.26.38
PCIE:SLOT_CAP_HOTPLUG_CAPABLE 9.27.38
PCIE:SLOT_CAP_HOTPLUG_SURPRISE 9.26.39
PCIE:SLOT_CAP_MRL_SENSOR_PRESENT 9.27.39
PCIE:SLOT_CAP_NO_CMD_COMPLETED_SUPPORT 9.26.40
PCIE:SLOT_CAP_POWER_CONTROLLER_PRESENT 9.26.47
PCIE:SLOT_CAP_POWER_INDICATOR_PRESENT 9.27.47
PCIE:SPARE_BIT0 15.26.5
PCIE:SPARE_BIT1 15.27.5
PCIE:SPARE_BIT2 15.26.6
PCIE:SPARE_BIT3 15.27.6
PCIE:SPARE_BIT4 15.26.7
PCIE:SPARE_BIT5 15.27.7
PCIE:SPARE_BIT6 15.26.8
PCIE:SPARE_BIT7 15.27.8
PCIE:SPARE_BIT8 15.26.9
PCIE:TEST_MODE_PIN_CHAR 15.27.4
PCIE:TL_RBYPASS 13.26.41
PCIE:TL_RX_RAM_RADDR_LATENCY 13.26.38
PCIE:TL_RX_RAM_WRITE_LATENCY 13.27.39
PCIE:TL_TFC_DISABLE 13.26.40
PCIE:TL_TX_CHECKS_DISABLE 13.27.40
PCIE:TL_TX_RAM_RADDR_LATENCY 13.27.41
PCIE:TL_TX_RAM_WRITE_LATENCY 13.26.43
PCIE:UPCONFIG_CAPABLE 13.27.22
PCIE:UPSTREAM_FACING 13.26.23
PCIE:UR_INV_REQ 14.27.39
PCIE:VC0_CPL_INFINITE 13.27.45
PCIE:VC_CAP_ON 10.26.38
PCIE:VC_CAP_REJECT_SNOOP_TRANSACTIONS 11.26.0
PCIE:VSEC_CAP_IS_LINK_VISIBLE 12.26.0
PCIE:VSEC_CAP_ON 12.27.6
non-inverted [0]
PCIE:AER_CAP_ID 0.27.15 0.26.15 0.27.14 0.26.14 0.27.13 0.26.13 0.27.12 0.26.12 0.27.11 0.26.11 0.27.10 0.26.10 0.27.9 0.26.9 0.27.8 0.26.8
PCIE:DEVICE_ID 4.27.23 4.26.23 4.27.22 4.26.22 4.27.21 4.26.21 4.27.20 4.26.20 4.27.19 4.26.19 4.27.18 4.26.18 4.27.17 4.26.17 4.27.16 4.26.16
PCIE:DRP00 0.27.7 0.26.7 0.27.6 0.26.6 0.27.5 0.26.5 0.27.4 0.26.4 0.27.3 0.26.3 0.27.2 0.26.2 0.27.1 0.26.1 0.27.0 0.26.0
PCIE:DRP01 0.27.15 0.26.15 0.27.14 0.26.14 0.27.13 0.26.13 0.27.12 0.26.12 0.27.11 0.26.11 0.27.10 0.26.10 0.27.9 0.26.9 0.27.8 0.26.8
PCIE:DRP02 0.27.23 0.26.23 0.27.22 0.26.22 0.27.21 0.26.21 0.27.20 0.26.20 0.27.19 0.26.19 0.27.18 0.26.18 0.27.17 0.26.17 0.27.16 0.26.16
PCIE:DRP03 0.27.31 0.26.31 0.27.30 0.26.30 0.27.29 0.26.29 0.27.28 0.26.28 0.27.27 0.26.27 0.27.26 0.26.26 0.27.25 0.26.25 0.27.24 0.26.24
PCIE:DRP04 0.27.39 0.26.39 0.27.38 0.26.38 0.27.37 0.26.37 0.27.36 0.26.36 0.27.35 0.26.35 0.27.34 0.26.34 0.27.33 0.26.33 0.27.32 0.26.32
PCIE:DRP05 0.27.47 0.26.47 0.27.46 0.26.46 0.27.45 0.26.45 0.27.44 0.26.44 0.27.43 0.26.43 0.27.42 0.26.42 0.27.41 0.26.41 0.27.40 0.26.40
PCIE:DRP06 1.27.7 1.26.7 1.27.6 1.26.6 1.27.5 1.26.5 1.27.4 1.26.4 1.27.3 1.26.3 1.27.2 1.26.2 1.27.1 1.26.1 1.27.0 1.26.0
PCIE:DRP07 1.27.15 1.26.15 1.27.14 1.26.14 1.27.13 1.26.13 1.27.12 1.26.12 1.27.11 1.26.11 1.27.10 1.26.10 1.27.9 1.26.9 1.27.8 1.26.8
PCIE:DRP08 1.27.23 1.26.23 1.27.22 1.26.22 1.27.21 1.26.21 1.27.20 1.26.20 1.27.19 1.26.19 1.27.18 1.26.18 1.27.17 1.26.17 1.27.16 1.26.16
PCIE:DRP09 1.27.31 1.26.31 1.27.30 1.26.30 1.27.29 1.26.29 1.27.28 1.26.28 1.27.27 1.26.27 1.27.26 1.26.26 1.27.25 1.26.25 1.27.24 1.26.24
PCIE:DRP0A 1.27.39 1.26.39 1.27.38 1.26.38 1.27.37 1.26.37 1.27.36 1.26.36 1.27.35 1.26.35 1.27.34 1.26.34 1.27.33 1.26.33 1.27.32 1.26.32
PCIE:DRP0B 1.27.47 1.26.47 1.27.46 1.26.46 1.27.45 1.26.45 1.27.44 1.26.44 1.27.43 1.26.43 1.27.42 1.26.42 1.27.41 1.26.41 1.27.40 1.26.40
PCIE:DRP0C 2.27.7 2.26.7 2.27.6 2.26.6 2.27.5 2.26.5 2.27.4 2.26.4 2.27.3 2.26.3 2.27.2 2.26.2 2.27.1 2.26.1 2.27.0 2.26.0
PCIE:DRP0D 2.27.15 2.26.15 2.27.14 2.26.14 2.27.13 2.26.13 2.27.12 2.26.12 2.27.11 2.26.11 2.27.10 2.26.10 2.27.9 2.26.9 2.27.8 2.26.8
PCIE:DRP0E 2.27.23 2.26.23 2.27.22 2.26.22 2.27.21 2.26.21 2.27.20 2.26.20 2.27.19 2.26.19 2.27.18 2.26.18 2.27.17 2.26.17 2.27.16 2.26.16
PCIE:DRP0F 2.27.31 2.26.31 2.27.30 2.26.30 2.27.29 2.26.29 2.27.28 2.26.28 2.27.27 2.26.27 2.27.26 2.26.26 2.27.25 2.26.25 2.27.24 2.26.24
PCIE:DRP10 2.27.39 2.26.39 2.27.38 2.26.38 2.27.37 2.26.37 2.27.36 2.26.36 2.27.35 2.26.35 2.27.34 2.26.34 2.27.33 2.26.33 2.27.32 2.26.32
PCIE:DRP11 2.27.47 2.26.47 2.27.46 2.26.46 2.27.45 2.26.45 2.27.44 2.26.44 2.27.43 2.26.43 2.27.42 2.26.42 2.27.41 2.26.41 2.27.40 2.26.40
PCIE:DRP12 3.27.7 3.26.7 3.27.6 3.26.6 3.27.5 3.26.5 3.27.4 3.26.4 3.27.3 3.26.3 3.27.2 3.26.2 3.27.1 3.26.1 3.27.0 3.26.0
PCIE:DRP13 3.27.15 3.26.15 3.27.14 3.26.14 3.27.13 3.26.13 3.27.12 3.26.12 3.27.11 3.26.11 3.27.10 3.26.10 3.27.9 3.26.9 3.27.8 3.26.8
PCIE:DRP14 3.27.23 3.26.23 3.27.22 3.26.22 3.27.21 3.26.21 3.27.20 3.26.20 3.27.19 3.26.19 3.27.18 3.26.18 3.27.17 3.26.17 3.27.16 3.26.16
PCIE:DRP15 3.27.31 3.26.31 3.27.30 3.26.30 3.27.29 3.26.29 3.27.28 3.26.28 3.27.27 3.26.27 3.27.26 3.26.26 3.27.25 3.26.25 3.27.24 3.26.24
PCIE:DRP16 3.27.39 3.26.39 3.27.38 3.26.38 3.27.37 3.26.37 3.27.36 3.26.36 3.27.35 3.26.35 3.27.34 3.26.34 3.27.33 3.26.33 3.27.32 3.26.32
PCIE:DRP17 3.27.47 3.26.47 3.27.46 3.26.46 3.27.45 3.26.45 3.27.44 3.26.44 3.27.43 3.26.43 3.27.42 3.26.42 3.27.41 3.26.41 3.27.40 3.26.40
PCIE:DRP18 4.27.7 4.26.7 4.27.6 4.26.6 4.27.5 4.26.5 4.27.4 4.26.4 4.27.3 4.26.3 4.27.2 4.26.2 4.27.1 4.26.1 4.27.0 4.26.0
PCIE:DRP19 4.27.15 4.26.15 4.27.14 4.26.14 4.27.13 4.26.13 4.27.12 4.26.12 4.27.11 4.26.11 4.27.10 4.26.10 4.27.9 4.26.9 4.27.8 4.26.8
PCIE:DRP1A 4.27.23 4.26.23 4.27.22 4.26.22 4.27.21 4.26.21 4.27.20 4.26.20 4.27.19 4.26.19 4.27.18 4.26.18 4.27.17 4.26.17 4.27.16 4.26.16
PCIE:DRP1B 4.27.31 4.26.31 4.27.30 4.26.30 4.27.29 4.26.29 4.27.28 4.26.28 4.27.27 4.26.27 4.27.26 4.26.26 4.27.25 4.26.25 4.27.24 4.26.24
PCIE:DRP1C 4.27.39 4.26.39 4.27.38 4.26.38 4.27.37 4.26.37 4.27.36 4.26.36 4.27.35 4.26.35 4.27.34 4.26.34 4.27.33 4.26.33 4.27.32 4.26.32
PCIE:DRP1D 4.27.47 4.26.47 4.27.46 4.26.46 4.27.45 4.26.45 4.27.44 4.26.44 4.27.43 4.26.43 4.27.42 4.26.42 4.27.41 4.26.41 4.27.40 4.26.40
PCIE:DRP1E 5.27.7 5.26.7 5.27.6 5.26.6 5.27.5 5.26.5 5.27.4 5.26.4 5.27.3 5.26.3 5.27.2 5.26.2 5.27.1 5.26.1 5.27.0 5.26.0
PCIE:DRP1F 5.27.15 5.26.15 5.27.14 5.26.14 5.27.13 5.26.13 5.27.12 5.26.12 5.27.11 5.26.11 5.27.10 5.26.10 5.27.9 5.26.9 5.27.8 5.26.8
PCIE:DRP20 5.27.23 5.26.23 5.27.22 5.26.22 5.27.21 5.26.21 5.27.20 5.26.20 5.27.19 5.26.19 5.27.18 5.26.18 5.27.17 5.26.17 5.27.16 5.26.16
PCIE:DRP21 5.27.31 5.26.31 5.27.30 5.26.30 5.27.29 5.26.29 5.27.28 5.26.28 5.27.27 5.26.27 5.27.26 5.26.26 5.27.25 5.26.25 5.27.24 5.26.24
PCIE:DRP22 5.27.39 5.26.39 5.27.38 5.26.38 5.27.37 5.26.37 5.27.36 5.26.36 5.27.35 5.26.35 5.27.34 5.26.34 5.27.33 5.26.33 5.27.32 5.26.32
PCIE:DRP23 5.27.47 5.26.47 5.27.46 5.26.46 5.27.45 5.26.45 5.27.44 5.26.44 5.27.43 5.26.43 5.27.42 5.26.42 5.27.41 5.26.41 5.27.40 5.26.40
PCIE:DRP24 6.27.7 6.26.7 6.27.6 6.26.6 6.27.5 6.26.5 6.27.4 6.26.4 6.27.3 6.26.3 6.27.2 6.26.2 6.27.1 6.26.1 6.27.0 6.26.0
PCIE:DRP25 6.27.15 6.26.15 6.27.14 6.26.14 6.27.13 6.26.13 6.27.12 6.26.12 6.27.11 6.26.11 6.27.10 6.26.10 6.27.9 6.26.9 6.27.8 6.26.8
PCIE:DRP26 6.27.23 6.26.23 6.27.22 6.26.22 6.27.21 6.26.21 6.27.20 6.26.20 6.27.19 6.26.19 6.27.18 6.26.18 6.27.17 6.26.17 6.27.16 6.26.16
PCIE:DRP27 6.27.31 6.26.31 6.27.30 6.26.30 6.27.29 6.26.29 6.27.28 6.26.28 6.27.27 6.26.27 6.27.26 6.26.26 6.27.25 6.26.25 6.27.24 6.26.24
PCIE:DRP28 6.27.39 6.26.39 6.27.38 6.26.38 6.27.37 6.26.37 6.27.36 6.26.36 6.27.35 6.26.35 6.27.34 6.26.34 6.27.33 6.26.33 6.27.32 6.26.32
PCIE:DRP29 6.27.47 6.26.47 6.27.46 6.26.46 6.27.45 6.26.45 6.27.44 6.26.44 6.27.43 6.26.43 6.27.42 6.26.42 6.27.41 6.26.41 6.27.40 6.26.40
PCIE:DRP2A 7.27.7 7.26.7 7.27.6 7.26.6 7.27.5 7.26.5 7.27.4 7.26.4 7.27.3 7.26.3 7.27.2 7.26.2 7.27.1 7.26.1 7.27.0 7.26.0
PCIE:DRP2B 7.27.15 7.26.15 7.27.14 7.26.14 7.27.13 7.26.13 7.27.12 7.26.12 7.27.11 7.26.11 7.27.10 7.26.10 7.27.9 7.26.9 7.27.8 7.26.8
PCIE:DRP2C 7.27.23 7.26.23 7.27.22 7.26.22 7.27.21 7.26.21 7.27.20 7.26.20 7.27.19 7.26.19 7.27.18 7.26.18 7.27.17 7.26.17 7.27.16 7.26.16
PCIE:DRP2D 7.27.31 7.26.31 7.27.30 7.26.30 7.27.29 7.26.29 7.27.28 7.26.28 7.27.27 7.26.27 7.27.26 7.26.26 7.27.25 7.26.25 7.27.24 7.26.24
PCIE:DRP2E 7.27.39 7.26.39 7.27.38 7.26.38 7.27.37 7.26.37 7.27.36 7.26.36 7.27.35 7.26.35 7.27.34 7.26.34 7.27.33 7.26.33 7.27.32 7.26.32
PCIE:DRP2F 7.27.47 7.26.47 7.27.46 7.26.46 7.27.45 7.26.45 7.27.44 7.26.44 7.27.43 7.26.43 7.27.42 7.26.42 7.27.41 7.26.41 7.27.40 7.26.40
PCIE:DRP30 8.27.7 8.26.7 8.27.6 8.26.6 8.27.5 8.26.5 8.27.4 8.26.4 8.27.3 8.26.3 8.27.2 8.26.2 8.27.1 8.26.1 8.27.0 8.26.0
PCIE:DRP31 8.27.15 8.26.15 8.27.14 8.26.14 8.27.13 8.26.13 8.27.12 8.26.12 8.27.11 8.26.11 8.27.10 8.26.10 8.27.9 8.26.9 8.27.8 8.26.8
PCIE:DRP32 8.27.23 8.26.23 8.27.22 8.26.22 8.27.21 8.26.21 8.27.20 8.26.20 8.27.19 8.26.19 8.27.18 8.26.18 8.27.17 8.26.17 8.27.16 8.26.16
PCIE:DRP33 8.27.31 8.26.31 8.27.30 8.26.30 8.27.29 8.26.29 8.27.28 8.26.28 8.27.27 8.26.27 8.27.26 8.26.26 8.27.25 8.26.25 8.27.24 8.26.24
PCIE:DRP34 8.27.39 8.26.39 8.27.38 8.26.38 8.27.37 8.26.37 8.27.36 8.26.36 8.27.35 8.26.35 8.27.34 8.26.34 8.27.33 8.26.33 8.27.32 8.26.32
PCIE:DRP35 8.27.47 8.26.47 8.27.46 8.26.46 8.27.45 8.26.45 8.27.44 8.26.44 8.27.43 8.26.43 8.27.42 8.26.42 8.27.41 8.26.41 8.27.40 8.26.40
PCIE:DRP36 9.27.7 9.26.7 9.27.6 9.26.6 9.27.5 9.26.5 9.27.4 9.26.4 9.27.3 9.26.3 9.27.2 9.26.2 9.27.1 9.26.1 9.27.0 9.26.0
PCIE:DRP37 9.27.15 9.26.15 9.27.14 9.26.14 9.27.13 9.26.13 9.27.12 9.26.12 9.27.11 9.26.11 9.27.10 9.26.10 9.27.9 9.26.9 9.27.8 9.26.8
PCIE:DRP38 9.27.23 9.26.23 9.27.22 9.26.22 9.27.21 9.26.21 9.27.20 9.26.20 9.27.19 9.26.19 9.27.18 9.26.18 9.27.17 9.26.17 9.27.16 9.26.16
PCIE:DRP39 9.27.31 9.26.31 9.27.30 9.26.30 9.27.29 9.26.29 9.27.28 9.26.28 9.27.27 9.26.27 9.27.26 9.26.26 9.27.25 9.26.25 9.27.24 9.26.24
PCIE:DRP3A 9.27.39 9.26.39 9.27.38 9.26.38 9.27.37 9.26.37 9.27.36 9.26.36 9.27.35 9.26.35 9.27.34 9.26.34 9.27.33 9.26.33 9.27.32 9.26.32
PCIE:DRP3B 9.27.47 9.26.47 9.27.46 9.26.46 9.27.45 9.26.45 9.27.44 9.26.44 9.27.43 9.26.43 9.27.42 9.26.42 9.27.41 9.26.41 9.27.40 9.26.40
PCIE:DRP3C 10.27.7 10.26.7 10.27.6 10.26.6 10.27.5 10.26.5 10.27.4 10.26.4 10.27.3 10.26.3 10.27.2 10.26.2 10.27.1 10.26.1 10.27.0 10.26.0
PCIE:DRP3D 10.27.15 10.26.15 10.27.14 10.26.14 10.27.13 10.26.13 10.27.12 10.26.12 10.27.11 10.26.11 10.27.10 10.26.10 10.27.9 10.26.9 10.27.8 10.26.8
PCIE:DRP3E 10.27.23 10.26.23 10.27.22 10.26.22 10.27.21 10.26.21 10.27.20 10.26.20 10.27.19 10.26.19 10.27.18 10.26.18 10.27.17 10.26.17 10.27.16 10.26.16
PCIE:DRP3F 10.27.31 10.26.31 10.27.30 10.26.30 10.27.29 10.26.29 10.27.28 10.26.28 10.27.27 10.26.27 10.27.26 10.26.26 10.27.25 10.26.25 10.27.24 10.26.24
PCIE:DRP40 10.27.39 10.26.39 10.27.38 10.26.38 10.27.37 10.26.37 10.27.36 10.26.36 10.27.35 10.26.35 10.27.34 10.26.34 10.27.33 10.26.33 10.27.32 10.26.32
PCIE:DRP41 10.27.47 10.26.47 10.27.46 10.26.46 10.27.45 10.26.45 10.27.44 10.26.44 10.27.43 10.26.43 10.27.42 10.26.42 10.27.41 10.26.41 10.27.40 10.26.40
PCIE:DRP42 11.27.7 11.26.7 11.27.6 11.26.6 11.27.5 11.26.5 11.27.4 11.26.4 11.27.3 11.26.3 11.27.2 11.26.2 11.27.1 11.26.1 11.27.0 11.26.0
PCIE:DRP43 11.27.15 11.26.15 11.27.14 11.26.14 11.27.13 11.26.13 11.27.12 11.26.12 11.27.11 11.26.11 11.27.10 11.26.10 11.27.9 11.26.9 11.27.8 11.26.8
PCIE:DRP44 11.27.23 11.26.23 11.27.22 11.26.22 11.27.21 11.26.21 11.27.20 11.26.20 11.27.19 11.26.19 11.27.18 11.26.18 11.27.17 11.26.17 11.27.16 11.26.16
PCIE:DRP45 11.27.31 11.26.31 11.27.30 11.26.30 11.27.29 11.26.29 11.27.28 11.26.28 11.27.27 11.26.27 11.27.26 11.26.26 11.27.25 11.26.25 11.27.24 11.26.24
PCIE:DRP46 11.27.39 11.26.39 11.27.38 11.26.38 11.27.37 11.26.37 11.27.36 11.26.36 11.27.35 11.26.35 11.27.34 11.26.34 11.27.33 11.26.33 11.27.32 11.26.32
PCIE:DRP47 11.27.47 11.26.47 11.27.46 11.26.46 11.27.45 11.26.45 11.27.44 11.26.44 11.27.43 11.26.43 11.27.42 11.26.42 11.27.41 11.26.41 11.27.40 11.26.40
PCIE:DRP48 12.27.7 12.26.7 12.27.6 12.26.6 12.27.5 12.26.5 12.27.4 12.26.4 12.27.3 12.26.3 12.27.2 12.26.2 12.27.1 12.26.1 12.27.0 12.26.0
PCIE:DRP49 12.27.15 12.26.15 12.27.14 12.26.14 12.27.13 12.26.13 12.27.12 12.26.12 12.27.11 12.26.11 12.27.10 12.26.10 12.27.9 12.26.9 12.27.8 12.26.8
PCIE:DRP4A 12.27.23 12.26.23 12.27.22 12.26.22 12.27.21 12.26.21 12.27.20 12.26.20 12.27.19 12.26.19 12.27.18 12.26.18 12.27.17 12.26.17 12.27.16 12.26.16
PCIE:DRP4B 12.27.31 12.26.31 12.27.30 12.26.30 12.27.29 12.26.29 12.27.28 12.26.28 12.27.27 12.26.27 12.27.26 12.26.26 12.27.25 12.26.25 12.27.24 12.26.24
PCIE:DRP4C 12.27.39 12.26.39 12.27.38 12.26.38 12.27.37 12.26.37 12.27.36 12.26.36 12.27.35 12.26.35 12.27.34 12.26.34 12.27.33 12.26.33 12.27.32 12.26.32
PCIE:DRP4D 12.27.47 12.26.47 12.27.46 12.26.46 12.27.45 12.26.45 12.27.44 12.26.44 12.27.43 12.26.43 12.27.42 12.26.42 12.27.41 12.26.41 12.27.40 12.26.40
PCIE:DRP4E 13.27.7 13.26.7 13.27.6 13.26.6 13.27.5 13.26.5 13.27.4 13.26.4 13.27.3 13.26.3 13.27.2 13.26.2 13.27.1 13.26.1 13.27.0 13.26.0
PCIE:DRP4F 13.27.15 13.26.15 13.27.14 13.26.14 13.27.13 13.26.13 13.27.12 13.26.12 13.27.11 13.26.11 13.27.10 13.26.10 13.27.9 13.26.9 13.27.8 13.26.8
PCIE:DRP50 13.27.23 13.26.23 13.27.22 13.26.22 13.27.21 13.26.21 13.27.20 13.26.20 13.27.19 13.26.19 13.27.18 13.26.18 13.27.17 13.26.17 13.27.16 13.26.16
PCIE:DRP51 13.27.31 13.26.31 13.27.30 13.26.30 13.27.29 13.26.29 13.27.28 13.26.28 13.27.27 13.26.27 13.27.26 13.26.26 13.27.25 13.26.25 13.27.24 13.26.24
PCIE:DRP52 13.27.39 13.26.39 13.27.38 13.26.38 13.27.37 13.26.37 13.27.36 13.26.36 13.27.35 13.26.35 13.27.34 13.26.34 13.27.33 13.26.33 13.27.32 13.26.32
PCIE:DRP53 13.27.47 13.26.47 13.27.46 13.26.46 13.27.45 13.26.45 13.27.44 13.26.44 13.27.43 13.26.43 13.27.42 13.26.42 13.27.41 13.26.41 13.27.40 13.26.40
PCIE:DRP54 14.27.7 14.26.7 14.27.6 14.26.6 14.27.5 14.26.5 14.27.4 14.26.4 14.27.3 14.26.3 14.27.2 14.26.2 14.27.1 14.26.1 14.27.0 14.26.0
PCIE:DRP55 14.27.15 14.26.15 14.27.14 14.26.14 14.27.13 14.26.13 14.27.12 14.26.12 14.27.11 14.26.11 14.27.10 14.26.10 14.27.9 14.26.9 14.27.8 14.26.8
PCIE:DRP56 14.27.23 14.26.23 14.27.22 14.26.22 14.27.21 14.26.21 14.27.20 14.26.20 14.27.19 14.26.19 14.27.18 14.26.18 14.27.17 14.26.17 14.27.16 14.26.16
PCIE:DRP57 14.27.31 14.26.31 14.27.30 14.26.30 14.27.29 14.26.29 14.27.28 14.26.28 14.27.27 14.26.27 14.27.26 14.26.26 14.27.25 14.26.25 14.27.24 14.26.24
PCIE:DRP58 14.27.39 14.26.39 14.27.38 14.26.38 14.27.37 14.26.37 14.27.36 14.26.36 14.27.35 14.26.35 14.27.34 14.26.34 14.27.33 14.26.33 14.27.32 14.26.32
PCIE:DRP59 14.27.47 14.26.47 14.27.46 14.26.46 14.27.45 14.26.45 14.27.44 14.26.44 14.27.43 14.26.43 14.27.42 14.26.42 14.27.41 14.26.41 14.27.40 14.26.40
PCIE:DRP5A 15.27.7 15.26.7 15.27.6 15.26.6 15.27.5 15.26.5 15.27.4 15.26.4 15.27.3 15.26.3 15.27.2 15.26.2 15.27.1 15.26.1 15.27.0 15.26.0
PCIE:DRP5B 15.27.15 15.26.15 15.27.14 15.26.14 15.27.13 15.26.13 15.27.12 15.26.12 15.27.11 15.26.11 15.27.10 15.26.10 15.27.9 15.26.9 15.27.8 15.26.8
PCIE:DRP5C 15.27.23 15.26.23 15.27.22 15.26.22 15.27.21 15.26.21 15.27.20 15.26.20 15.27.19 15.26.19 15.27.18 15.26.18 15.27.17 15.26.17 15.27.16 15.26.16
PCIE:DRP5D 15.27.31 15.26.31 15.27.30 15.26.30 15.27.29 15.26.29 15.27.28 15.26.28 15.27.27 15.26.27 15.27.26 15.26.26 15.27.25 15.26.25 15.27.24 15.26.24
PCIE:DRP5E 15.27.39 15.26.39 15.27.38 15.26.38 15.27.37 15.26.37 15.27.36 15.26.36 15.27.35 15.26.35 15.27.34 15.26.34 15.27.33 15.26.33 15.27.32 15.26.32
PCIE:DRP5F 15.27.47 15.26.47 15.27.46 15.26.46 15.27.45 15.26.45 15.27.44 15.26.44 15.27.43 15.26.43 15.27.42 15.26.42 15.27.41 15.26.41 15.27.40 15.26.40
PCIE:DRP60 16.27.7 16.26.7 16.27.6 16.26.6 16.27.5 16.26.5 16.27.4 16.26.4 16.27.3 16.26.3 16.27.2 16.26.2 16.27.1 16.26.1 16.27.0 16.26.0
PCIE:DRP61 16.27.15 16.26.15 16.27.14 16.26.14 16.27.13 16.26.13 16.27.12 16.26.12 16.27.11 16.26.11 16.27.10 16.26.10 16.27.9 16.26.9 16.27.8 16.26.8
PCIE:DRP62 16.27.23 16.26.23 16.27.22 16.26.22 16.27.21 16.26.21 16.27.20 16.26.20 16.27.19 16.26.19 16.27.18 16.26.18 16.27.17 16.26.17 16.27.16 16.26.16
PCIE:DRP63 16.27.31 16.26.31 16.27.30 16.26.30 16.27.29 16.26.29 16.27.28 16.26.28 16.27.27 16.26.27 16.27.26 16.26.26 16.27.25 16.26.25 16.27.24 16.26.24
PCIE:DRP64 16.27.39 16.26.39 16.27.38 16.26.38 16.27.37 16.26.37 16.27.36 16.26.36 16.27.35 16.26.35 16.27.34 16.26.34 16.27.33 16.26.33 16.27.32 16.26.32
PCIE:DRP65 16.27.47 16.26.47 16.27.46 16.26.46 16.27.45 16.26.45 16.27.44 16.26.44 16.27.43 16.26.43 16.27.42 16.26.42 16.27.41 16.26.41 16.27.40 16.26.40
PCIE:DRP66 17.27.7 17.26.7 17.27.6 17.26.6 17.27.5 17.26.5 17.27.4 17.26.4 17.27.3 17.26.3 17.27.2 17.26.2 17.27.1 17.26.1 17.27.0 17.26.0
PCIE:DRP67 17.27.15 17.26.15 17.27.14 17.26.14 17.27.13 17.26.13 17.27.12 17.26.12 17.27.11 17.26.11 17.27.10 17.26.10 17.27.9 17.26.9 17.27.8 17.26.8
PCIE:DRP68 17.27.23 17.26.23 17.27.22 17.26.22 17.27.21 17.26.21 17.27.20 17.26.20 17.27.19 17.26.19 17.27.18 17.26.18 17.27.17 17.26.17 17.27.16 17.26.16
PCIE:DRP69 17.27.31 17.26.31 17.27.30 17.26.30 17.27.29 17.26.29 17.27.28 17.26.28 17.27.27 17.26.27 17.27.26 17.26.26 17.27.25 17.26.25 17.27.24 17.26.24
PCIE:DRP6A 17.27.39 17.26.39 17.27.38 17.26.38 17.27.37 17.26.37 17.27.36 17.26.36 17.27.35 17.26.35 17.27.34 17.26.34 17.27.33 17.26.33 17.27.32 17.26.32
PCIE:DRP6B 17.27.47 17.26.47 17.27.46 17.26.46 17.27.45 17.26.45 17.27.44 17.26.44 17.27.43 17.26.43 17.27.42 17.26.42 17.27.41 17.26.41 17.27.40 17.26.40
PCIE:DRP6C 18.27.7 18.26.7 18.27.6 18.26.6 18.27.5 18.26.5 18.27.4 18.26.4 18.27.3 18.26.3 18.27.2 18.26.2 18.27.1 18.26.1 18.27.0 18.26.0
PCIE:DRP6D 18.27.15 18.26.15 18.27.14 18.26.14 18.27.13 18.26.13 18.27.12 18.26.12 18.27.11 18.26.11 18.27.10 18.26.10 18.27.9 18.26.9 18.27.8 18.26.8
PCIE:DRP6E 18.27.23 18.26.23 18.27.22 18.26.22 18.27.21 18.26.21 18.27.20 18.26.20 18.27.19 18.26.19 18.27.18 18.26.18 18.27.17 18.26.17 18.27.16 18.26.16
PCIE:DRP6F 18.27.31 18.26.31 18.27.30 18.26.30 18.27.29 18.26.29 18.27.28 18.26.28 18.27.27 18.26.27 18.27.26 18.26.26 18.27.25 18.26.25 18.27.24 18.26.24
PCIE:DRP70 18.27.39 18.26.39 18.27.38 18.26.38 18.27.37 18.26.37 18.27.36 18.26.36 18.27.35 18.26.35 18.27.34 18.26.34 18.27.33 18.26.33 18.27.32 18.26.32
PCIE:DRP71 18.27.47 18.26.47 18.27.46 18.26.46 18.27.45 18.26.45 18.27.44 18.26.44 18.27.43 18.26.43 18.27.42 18.26.42 18.27.41 18.26.41 18.27.40 18.26.40
PCIE:DRP72 19.27.7 19.26.7 19.27.6 19.26.6 19.27.5 19.26.5 19.27.4 19.26.4 19.27.3 19.26.3 19.27.2 19.26.2 19.27.1 19.26.1 19.27.0 19.26.0
PCIE:DRP73 19.27.15 19.26.15 19.27.14 19.26.14 19.27.13 19.26.13 19.27.12 19.26.12 19.27.11 19.26.11 19.27.10 19.26.10 19.27.9 19.26.9 19.27.8 19.26.8
PCIE:DRP74 19.27.23 19.26.23 19.27.22 19.26.22 19.27.21 19.26.21 19.27.20 19.26.20 19.27.19 19.26.19 19.27.18 19.26.18 19.27.17 19.26.17 19.27.16 19.26.16
PCIE:DRP75 19.27.31 19.26.31 19.27.30 19.26.30 19.27.29 19.26.29 19.27.28 19.26.28 19.27.27 19.26.27 19.27.26 19.26.26 19.27.25 19.26.25 19.27.24 19.26.24
PCIE:DRP76 19.27.39 19.26.39 19.27.38 19.26.38 19.27.37 19.26.37 19.27.36 19.26.36 19.27.35 19.26.35 19.27.34 19.26.34 19.27.33 19.26.33 19.27.32 19.26.32
PCIE:DRP77 19.27.47 19.26.47 19.27.46 19.26.46 19.27.45 19.26.45 19.27.44 19.26.44 19.27.43 19.26.43 19.27.42 19.26.42 19.27.41 19.26.41 19.27.40 19.26.40
PCIE:DSN_CAP_ID 4.27.39 4.26.39 4.27.38 4.26.38 4.27.37 4.26.37 4.27.36 4.26.36 4.27.35 4.26.35 4.27.34 4.26.34 4.27.33 4.26.33 4.27.32 4.26.32
PCIE:SUBSYSTEM_ID 10.27.15 10.26.15 10.27.14 10.26.14 10.27.13 10.26.13 10.27.12 10.26.12 10.27.11 10.26.11 10.27.10 10.26.10 10.27.9 10.26.9 10.27.8 10.26.8
PCIE:SUBSYSTEM_VENDOR_ID 10.27.23 10.26.23 10.27.22 10.26.22 10.27.21 10.26.21 10.27.20 10.26.20 10.27.19 10.26.19 10.27.18 10.26.18 10.27.17 10.26.17 10.27.16 10.26.16
PCIE:VC_CAP_ID 10.27.47 10.26.47 10.27.46 10.26.46 10.27.45 10.26.45 10.27.44 10.26.44 10.27.43 10.26.43 10.27.42 10.26.42 10.27.41 10.26.41 10.27.40 10.26.40
PCIE:VENDOR_ID 11.27.15 11.26.15 11.27.14 11.26.14 11.27.13 11.26.13 11.27.12 11.26.12 11.27.11 11.26.11 11.27.10 11.26.10 11.27.9 11.26.9 11.27.8 11.26.8
PCIE:VSEC_CAP_HDR_ID 11.27.31 11.26.31 11.27.30 11.26.30 11.27.29 11.26.29 11.27.28 11.26.28 11.27.27 11.26.27 11.27.26 11.26.26 11.27.25 11.26.25 11.27.24 11.26.24
PCIE:VSEC_CAP_ID 11.27.47 11.26.47 11.27.46 11.26.46 11.27.45 11.26.45 11.27.44 11.26.44 11.27.43 11.26.43 11.27.42 11.26.42 11.27.41 11.26.41 11.27.40 11.26.40
non-inverted [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
PCIE:AER_CAP_INT_MSG_NUM_MSI 0.26.18 0.27.17 0.26.17 0.27.16 0.26.16
PCIE:AER_CAP_INT_MSG_NUM_MSIX 0.27.20 0.26.20 0.27.19 0.26.19 0.27.18
PCIE:INFER_EI 12.27.44 12.26.44 12.27.43 12.26.43 12.27.42
PCIE:PCIE_CAP_INT_MSG_NUM 8.26.6 8.27.5 8.26.5 8.27.4 8.26.4
PCIE:PM_CAP_PMESUPPORT 8.26.35 8.27.34 8.26.34 8.27.33 8.26.33
PCIE:VC0_TX_LASTPACKET 14.27.37 14.26.37 14.27.36 14.26.36 14.27.35
non-inverted [4] [3] [2] [1] [0]
PCIE:AER_CAP_VERSION 0.26.23 0.27.22 0.26.22 0.27.21
PCIE:CPL_TIMEOUT_RANGES_SUPPORTED 3.27.46 3.26.46 3.27.45 3.26.45
PCIE:DSN_CAP_VERSION 5.27.1 5.26.1 5.27.0 5.26.0
PCIE:LINK_CAP_MAX_LINK_SPEED 5.27.46 5.26.46 5.27.45 5.26.45
PCIE:LINK_CTRL2_TARGET_LINK_SPEED 6.27.3 6.26.3 6.27.2 6.26.2
PCIE:PCIE_CAP_CAPABILITY_VERSION 8.27.1 8.26.1 8.27.0 8.26.0
PCIE:PCIE_CAP_DEVICE_PORT_TYPE 8.27.3 8.26.3 8.27.2 8.26.2
PCIE:PCIE_REVISION 8.27.15 8.26.15 8.27.14 8.26.14
PCIE:VC_CAP_VERSION 13.26.45 13.27.44 13.26.44 13.27.43
PCIE:VSEC_CAP_HDR_REVISION 11.27.39 11.26.39 11.27.38 11.26.38
PCIE:VSEC_CAP_VERSION 12.27.9 12.26.9 12.27.8 12.26.8
non-inverted [3] [2] [1] [0]
PCIE:BAR0 1.27.7 1.26.7 1.27.6 1.26.6 1.27.5 1.26.5 1.27.4 1.26.4 1.27.3 1.26.3 1.27.2 1.26.2 1.27.1 1.26.1 1.27.0 1.26.0 0.27.47 0.26.47 0.27.46 0.26.46 0.27.45 0.26.45 0.27.44 0.26.44 0.27.43 0.26.43 0.27.42 0.26.42 0.27.41 0.26.41 0.27.40 0.26.40
PCIE:BAR1 1.27.23 1.26.23 1.27.22 1.26.22 1.27.21 1.26.21 1.27.20 1.26.20 1.27.19 1.26.19 1.27.18 1.26.18 1.27.17 1.26.17 1.27.16 1.26.16 1.27.15 1.26.15 1.27.14 1.26.14 1.27.13 1.26.13 1.27.12 1.26.12 1.27.11 1.26.11 1.27.10 1.26.10 1.27.9 1.26.9 1.27.8 1.26.8
PCIE:BAR2 1.27.39 1.26.39 1.27.38 1.26.38 1.27.37 1.26.37 1.27.36 1.26.36 1.27.35 1.26.35 1.27.34 1.26.34 1.27.33 1.26.33 1.27.32 1.26.32 1.27.31 1.26.31 1.27.30 1.26.30 1.27.29 1.26.29 1.27.28 1.26.28 1.27.27 1.26.27 1.27.26 1.26.26 1.27.25 1.26.25 1.27.24 1.26.24
PCIE:BAR3 2.27.7 2.26.7 2.27.6 2.26.6 2.27.5 2.26.5 2.27.4 2.26.4 2.27.3 2.26.3 2.27.2 2.26.2 2.27.1 2.26.1 2.27.0 2.26.0 1.27.47 1.26.47 1.27.46 1.26.46 1.27.45 1.26.45 1.27.44 1.26.44 1.27.43 1.26.43 1.27.42 1.26.42 1.27.41 1.26.41 1.27.40 1.26.40
PCIE:BAR4 2.27.23 2.26.23 2.27.22 2.26.22 2.27.21 2.26.21 2.27.20 2.26.20 2.27.19 2.26.19 2.27.18 2.26.18 2.27.17 2.26.17 2.27.16 2.26.16 2.27.15 2.26.15 2.27.14 2.26.14 2.27.13 2.26.13 2.27.12 2.26.12 2.27.11 2.26.11 2.27.10 2.26.10 2.27.9 2.26.9 2.27.8 2.26.8
PCIE:BAR5 2.27.39 2.26.39 2.27.38 2.26.38 2.27.37 2.26.37 2.27.36 2.26.36 2.27.35 2.26.35 2.27.34 2.26.34 2.27.33 2.26.33 2.27.32 2.26.32 2.27.31 2.26.31 2.27.30 2.26.30 2.27.29 2.26.29 2.27.28 2.26.28 2.27.27 2.26.27 2.27.26 2.26.26 2.27.25 2.26.25 2.27.24 2.26.24
PCIE:CARDBUS_CIS_POINTER 3.27.31 3.26.31 3.27.30 3.26.30 3.27.29 3.26.29 3.27.28 3.26.28 3.27.27 3.26.27 3.27.26 3.26.26 3.27.25 3.26.25 3.27.24 3.26.24 3.27.23 3.26.23 3.27.22 3.26.22 3.27.21 3.26.21 3.27.20 3.26.20 3.27.19 3.26.19 3.27.18 3.26.18 3.27.17 3.26.17 3.27.16 3.26.16
PCIE:EXPANSION_ROM 3.27.7 3.26.7 3.27.6 3.26.6 3.27.5 3.26.5 3.27.4 3.26.4 3.27.3 3.26.3 3.27.2 3.26.2 3.27.1 3.26.1 3.27.0 3.26.0 2.27.47 2.26.47 2.27.46 2.26.46 2.27.45 2.26.45 2.27.44 2.26.44 2.27.43 2.26.43 2.27.42 2.26.42 2.27.41 2.26.41 2.27.40 2.26.40
PCIE:SPARE_WORD0 15.27.47 15.26.47 15.27.46 15.26.46 15.27.45 15.26.45 15.27.44 15.26.44 15.27.43 15.26.43 15.27.42 15.26.42 15.27.41 15.26.41 15.27.40 15.26.40 15.27.39 15.26.39 15.27.38 15.26.38 15.27.37 15.26.37 15.27.36 15.26.36 15.27.35 15.26.35 15.27.34 15.26.34 15.27.33 15.26.33 15.27.32 15.26.32
PCIE:SPARE_WORD1 16.27.15 16.26.15 16.27.14 16.26.14 16.27.13 16.26.13 16.27.12 16.26.12 16.27.11 16.26.11 16.27.10 16.26.10 16.27.9 16.26.9 16.27.8 16.26.8 16.27.7 16.26.7 16.27.6 16.26.6 16.27.5 16.26.5 16.27.4 16.26.4 16.27.3 16.26.3 16.27.2 16.26.2 16.27.1 16.26.1 16.27.0 16.26.0
PCIE:SPARE_WORD2 16.27.31 16.26.31 16.27.30 16.26.30 16.27.29 16.26.29 16.27.28 16.26.28 16.27.27 16.26.27 16.27.26 16.26.26 16.27.25 16.26.25 16.27.24 16.26.24 16.27.23 16.26.23 16.27.22 16.26.22 16.27.21 16.26.21 16.27.20 16.26.20 16.27.19 16.26.19 16.27.18 16.26.18 16.27.17 16.26.17 16.27.16 16.26.16
PCIE:SPARE_WORD3 16.27.47 16.26.47 16.27.46 16.26.46 16.27.45 16.26.45 16.27.44 16.26.44 16.27.43 16.26.43 16.27.42 16.26.42 16.27.41 16.26.41 16.27.40 16.26.40 16.27.39 16.26.39 16.27.38 16.26.38 16.27.37 16.26.37 16.27.36 16.26.36 16.27.35 16.26.35 16.27.34 16.26.34 16.27.33 16.26.33 16.27.32 16.26.32
non-inverted [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
PCIE:CAPABILITIES_PTR 3.27.11 3.26.11 3.27.10 3.26.10 3.27.9 3.26.9 3.27.8 3.26.8
PCIE:DNSTREAM_LINK_NUM 13.27.27 13.26.27 13.27.26 13.26.26 13.27.25 13.26.25 13.27.24 13.26.24
PCIE:HEADER_TYPE 5.27.19 5.26.19 5.27.18 5.26.18 5.27.17 5.26.17 5.27.16 5.26.16
PCIE:INTERRUPT_PIN 5.27.23 5.26.23 5.27.22 5.26.22 5.27.21 5.26.21 5.27.20 5.26.20
PCIE:MSIX_BASE_PTR 6.27.35 6.26.35 6.27.34 6.26.34 6.27.33 6.26.33 6.27.32 6.26.32
PCIE:MSIX_CAP_ID 6.27.39 6.26.39 6.27.38 6.26.38 6.27.37 6.26.37 6.27.36 6.26.36
PCIE:MSIX_CAP_NEXTPTR 6.27.43 6.26.43 6.27.42 6.26.42 6.27.41 6.26.41 6.27.40 6.26.40
PCIE:MSI_BASE_PTR 6.27.11 6.26.11 6.27.10 6.26.10 6.27.9 6.26.9 6.27.8 6.26.8
PCIE:MSI_CAP_ID 6.27.19 6.26.19 6.27.18 6.26.18 6.27.17 6.26.17 6.27.16 6.26.16
PCIE:MSI_CAP_NEXTPTR 6.27.27 6.26.27 6.27.26 6.26.26 6.27.25 6.26.25 6.27.24 6.26.24
PCIE:N_FTS_COMCLK_GEN1 13.27.6 13.26.6 13.27.5 13.26.5 13.27.4 13.26.4 13.27.3 13.26.3
PCIE:N_FTS_COMCLK_GEN2 13.27.11 13.26.11 13.27.10 13.26.10 13.27.9 13.26.9 13.27.8 13.26.8
PCIE:N_FTS_GEN1 13.27.15 13.26.15 13.27.14 13.26.14 13.27.13 13.26.13 13.27.12 13.26.12
PCIE:N_FTS_GEN2 13.27.19 13.26.19 13.27.18 13.26.18 13.27.17 13.26.17 13.27.16 13.26.16
PCIE:PCIE_BASE_PTR 7.27.43 7.26.43 7.27.42 7.26.42 7.27.41 7.26.41 7.27.40 7.26.40
PCIE:PCIE_CAP_CAPABILITY_ID 7.27.47 7.26.47 7.27.46 7.26.46 7.27.45 7.26.45 7.27.44 7.26.44
PCIE:PCIE_CAP_NEXTPTR 8.27.11 8.26.11 8.27.10 8.26.10 8.27.9 8.26.9 8.27.8 8.26.8
PCIE:PM_BASE_PTR 8.27.19 8.26.19 8.27.18 8.26.18 8.27.17 8.26.17 8.27.16 8.26.16
PCIE:PM_CAP_ID 8.27.27 8.26.27 8.27.26 8.26.26 8.27.25 8.26.25 8.27.24 8.26.24
PCIE:PM_CAP_NEXTPTR 8.27.31 8.26.31 8.27.30 8.26.30 8.27.29 8.26.29 8.27.28 8.26.28
PCIE:PM_DATA0 9.27.3 9.26.3 9.27.2 9.26.2 9.27.1 9.26.1 9.27.0 9.26.0
PCIE:PM_DATA1 9.27.7 9.26.7 9.27.6 9.26.6 9.27.5 9.26.5 9.27.4 9.26.4
PCIE:PM_DATA2 9.27.11 9.26.11 9.27.10 9.26.10 9.27.9 9.26.9 9.27.8 9.26.8
PCIE:PM_DATA3 9.27.15 9.26.15 9.27.14 9.26.14 9.27.13 9.26.13 9.27.12 9.26.12
PCIE:PM_DATA4 9.27.19 9.26.19 9.27.18 9.26.18 9.27.17 9.26.17 9.27.16 9.26.16
PCIE:PM_DATA5 9.27.23 9.26.23 9.27.22 9.26.22 9.27.21 9.26.21 9.27.20 9.26.20
PCIE:PM_DATA6 9.27.27 9.26.27 9.27.26 9.26.26 9.27.25 9.26.25 9.27.24 9.26.24
PCIE:PM_DATA7 9.27.31 9.26.31 9.27.30 9.26.30 9.27.29 9.26.29 9.27.28 9.26.28
PCIE:REVISION_ID 9.27.35 9.26.35 9.27.34 9.26.34 9.27.33 9.26.33 9.27.32 9.26.32
PCIE:SLOT_CAP_SLOT_POWER_LIMIT_VALUE 10.27.4 10.26.4 10.27.3 10.26.3 10.27.2 10.26.2 10.27.1 10.26.1
PCIE:SPARE_BYTE0 15.26.13 15.27.12 15.26.12 15.27.11 15.26.11 15.27.10 15.26.10 15.27.9
PCIE:SPARE_BYTE1 15.27.19 15.26.19 15.27.18 15.26.18 15.27.17 15.26.17 15.27.16 15.26.16
PCIE:SPARE_BYTE2 15.27.23 15.26.23 15.27.22 15.26.22 15.27.21 15.26.21 15.27.20 15.26.20
PCIE:SPARE_BYTE3 15.27.27 15.26.27 15.27.26 15.26.26 15.27.25 15.26.25 15.27.24 15.26.24
non-inverted [7] [6] [5] [4] [3] [2] [1] [0]
PCIE:CLASS_CODE 3.27.43 3.26.43 3.27.42 3.26.42 3.27.41 3.26.41 3.27.40 3.26.40 3.27.39 3.26.39 3.27.38 3.26.38 3.27.37 3.26.37 3.27.36 3.26.36 3.27.35 3.26.35 3.27.34 3.26.34 3.27.33 3.26.33 3.27.32 3.26.32
non-inverted [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
PCIE:CRM_MODULE_RSTS 12.27.14 12.26.14 12.27.13 12.26.13 12.27.12 12.26.12 12.27.11
PCIE:VC0_TOTAL_CREDITS_CH 14.26.19 14.27.18 14.26.18 14.27.17 14.26.17 14.27.16 14.26.16
PCIE:VC0_TOTAL_CREDITS_NPH 14.27.22 14.26.22 14.27.21 14.26.21 14.27.20 14.26.20 14.27.19
PCIE:VC0_TOTAL_CREDITS_PH 14.26.35 14.27.34 14.26.34 14.27.33 14.26.33 14.27.32 14.26.32
non-inverted [6] [5] [4] [3] [2] [1] [0]
PCIE:DEV_CAP_ENDPOINT_L0S_LATENCY 4.26.1 4.27.0 4.26.0
PCIE:DEV_CAP_ENDPOINT_L1_LATENCY 4.27.2 4.26.2 4.27.1
PCIE:DEV_CAP_MAX_PAYLOAD_SUPPORTED 4.26.5 4.27.4 4.26.4
PCIE:DEV_CAP_RSVD_14_12 4.26.9 4.27.8 4.26.8
PCIE:DEV_CAP_RSVD_31_29 4.27.11 4.26.11 4.27.10
PCIE:LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 5.26.33 5.27.32 5.26.32
PCIE:LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 5.27.34 5.26.34 5.27.33
PCIE:LINK_CAP_L0S_EXIT_LATENCY_GEN1 5.26.36 5.27.35 5.26.35
PCIE:LINK_CAP_L0S_EXIT_LATENCY_GEN2 5.27.37 5.26.37 5.27.36
PCIE:LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 5.26.39 5.27.38 5.26.38
PCIE:LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 5.26.41 5.27.40 5.26.40
PCIE:LINK_CAP_L1_EXIT_LATENCY_GEN1 5.27.42 5.26.42 5.27.41
PCIE:LINK_CAP_L1_EXIT_LATENCY_GEN2 5.26.44 5.27.43 5.26.43
PCIE:MSIX_CAP_PBA_BIR 6.27.45 6.26.45 6.27.44
PCIE:MSIX_CAP_TABLE_BIR 7.27.15 7.26.15 7.27.14
PCIE:MSI_CAP_MULTIMSGCAP 6.27.21 6.26.21 6.27.20
PCIE:PGL0_LANE 14.26.41 14.27.40 14.26.40
PCIE:PGL1_LANE 14.27.42 14.26.42 14.27.41
PCIE:PGL2_LANE 14.26.44 14.27.43 14.26.43
PCIE:PGL3_LANE 14.27.45 14.26.45 14.27.44
PCIE:PGL4_LANE 14.26.47 14.27.46 14.26.46
PCIE:PGL5_LANE 15.26.1 15.27.0 15.26.0
PCIE:PGL6_LANE 15.27.2 15.26.2 15.27.1
PCIE:PGL7_LANE 15.26.4 15.27.3 15.26.3
PCIE:PL_AUTO_CONFIG 13.27.21 13.26.21 13.27.20
PCIE:PM_CAP_AUXCURRENT 8.26.21 8.27.20 8.26.20
PCIE:PM_CAP_VERSION 8.26.37 8.27.36 8.26.36
PCIE:USER_CLK_FREQ 12.26.11 12.27.10 12.26.10
non-inverted [2] [1] [0]
PCIE:DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT 4.26.6 4.27.5
PCIE:DEV_CAP_RSVD_17_16 4.26.10 4.27.9
PCIE:LINK_CAP_ASPM_SUPPORT 5.26.30 5.27.29
PCIE:LINK_CAP_RSVD_23_22 5.27.47 5.26.47
PCIE:LL_ACK_TIMEOUT_FUNC 12.27.24 12.26.24
PCIE:LL_REPLAY_TIMEOUT_FUNC 12.27.40 12.26.40
PCIE:PCIE_CAP_RSVD_15_14 8.26.13 8.27.12
PCIE:PM_DATA_SCALE0 8.27.39 8.26.39
PCIE:PM_DATA_SCALE1 8.27.40 8.26.40
PCIE:PM_DATA_SCALE2 8.27.41 8.26.41
PCIE:PM_DATA_SCALE3 8.27.42 8.26.42
PCIE:PM_DATA_SCALE4 8.27.43 8.26.43
PCIE:PM_DATA_SCALE5 8.27.44 8.26.44
PCIE:PM_DATA_SCALE6 8.27.45 8.26.45
PCIE:PM_DATA_SCALE7 8.27.46 8.26.46
PCIE:RECRC_CHK 14.27.38 14.26.38
PCIE:SLOT_CAP_SLOT_POWER_LIMIT_SCALE 10.27.0 10.26.0
PCIE:TL_RX_RAM_RDATA_LATENCY 13.26.39 13.27.38
PCIE:TL_TX_RAM_RDATA_LATENCY 13.27.42 13.26.42
non-inverted [1] [0]
PCIE:ENABLE_MSG_ROUTE 13.26.37 13.27.36 13.26.36 13.27.35 13.26.35 13.27.34 13.26.34 13.27.33 13.26.33 13.27.32 13.26.32
PCIE:MSIX_CAP_TABLE_SIZE 7.26.37 7.27.36 7.26.36 7.27.35 7.26.35 7.27.34 7.26.34 7.27.33 7.26.33 7.27.32 7.26.32
PCIE:VC0_TOTAL_CREDITS_CD 14.26.13 14.27.12 14.26.12 14.27.11 14.26.11 14.27.10 14.26.10 14.27.9 14.26.9 14.27.8 14.26.8
PCIE:VC0_TOTAL_CREDITS_PD 14.26.29 14.27.28 14.26.28 14.27.27 14.26.27 14.27.26 14.26.26 14.27.25 14.26.25 14.27.24 14.26.24
non-inverted [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
PCIE:EXT_CFG_CAP_PTR 5.27.4 5.26.4 5.27.3 5.26.3 5.27.2 5.26.2
PCIE:LINK_CAP_MAX_LINK_WIDTH 12.27.47 12.26.47 12.27.46 12.26.46 12.27.45 12.26.45
PCIE:LTSSM_MAX_LINK_WIDTH 13.27.2 13.26.2 13.27.1 13.26.1 13.27.0 13.26.0
non-inverted [5] [4] [3] [2] [1] [0]
PCIE:EXT_CFG_XP_CAP_PTR 5.27.12 5.26.12 5.27.11 5.26.11 5.27.10 5.26.10 5.27.9 5.26.9 5.27.8 5.26.8
PCIE:LAST_CONFIG_DWORD 5.26.29 5.27.28 5.26.28 5.27.27 5.26.27 5.27.26 5.26.26 5.27.25 5.26.25 5.27.24
non-inverted [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
PCIE:LL_ACK_TIMEOUT 12.26.23 12.27.22 12.26.22 12.27.21 12.26.21 12.27.20 12.26.20 12.27.19 12.26.19 12.27.18 12.26.18 12.27.17 12.26.17 12.27.16 12.26.16
PCIE:LL_REPLAY_TIMEOUT 12.26.39 12.27.38 12.26.38 12.27.37 12.26.37 12.27.36 12.26.36 12.27.35 12.26.35 12.27.34 12.26.34 12.27.33 12.26.33 12.27.32 12.26.32
non-inverted [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
PCIE:MSIX_CAP_PBA_OFFSET 7.26.14 7.27.13 7.26.13 7.27.12 7.26.12 7.27.11 7.26.11 7.27.10 7.26.10 7.27.9 7.26.9 7.27.8 7.26.8 7.27.7 7.26.7 7.27.6 7.26.6 7.27.5 7.26.5 7.27.4 7.26.4 7.27.3 7.26.3 7.27.2 7.26.2 7.27.1 7.26.1 7.27.0 7.26.0
PCIE:MSIX_CAP_TABLE_OFFSET 7.26.30 7.27.29 7.26.29 7.27.28 7.26.28 7.27.27 7.26.27 7.27.26 7.26.26 7.27.25 7.26.25 7.27.24 7.26.24 7.27.23 7.26.23 7.27.22 7.26.22 7.27.21 7.26.21 7.27.20 7.26.20 7.27.19 7.26.19 7.27.18 7.26.18 7.27.17 7.26.17 7.27.16 7.26.16
non-inverted [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
PCIE:SLOT_CAP_PHYSICAL_SLOT_NUM 9.27.46 9.26.46 9.27.45 9.26.45 9.27.44 9.26.44 9.27.43 9.26.43 9.27.42 9.26.42 9.27.41 9.26.41 9.27.40
PCIE:VC0_RX_RAM_LIMIT 14.26.6 14.27.5 14.26.5 14.27.4 14.26.4 14.27.3 14.26.3 14.27.2 14.26.2 14.27.1 14.26.1 14.27.0 14.26.0
non-inverted [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]