GTX transceivers

TODO: document

Tile GTX

Cells: 40

Switchbox SPEC_INT

virtex6 GTX switchbox SPEC_INT muxes IMUX_GTX_PERFCLK
Bits			Destination
MAIN[14][29][22]	MAIN[14][28][22]	MAIN[14][28][23]	CELL[20].IMUX_GTX_PERFCLK
			Source
0	0	0	off
0	0	1	CELL[20].PERF_ROW[0]
0	1	1	CELL[20].PERF_ROW[1]
1	0	1	CELL[20].PERF_ROW[2]
1	1	1	CELL[20].PERF_ROW[3]

Bels HCLK_GTX

virtex6 GTX bel HCLK_GTX pins
Pin	Direction	HCLK_GTX

virtex6 GTX bel HCLK_GTX attribute bits
Attribute	HCLK_GTX
MUX_SOUTHREFCLKOUT0	[enum: HCLK_GTX_MUX_SOUTHREFCLKOUT0]
MUX_SOUTHREFCLKOUT1	[enum: HCLK_GTX_MUX_SOUTHREFCLKOUT1]
MUX_NORTHREFCLKOUT0	[enum: HCLK_GTX_MUX_NORTHREFCLKOUT0]
MUX_NORTHREFCLKOUT1	[enum: HCLK_GTX_MUX_NORTHREFCLKOUT1]

virtex6 GTX enum HCLK_GTX_MUX_SOUTHREFCLKOUT0
HCLK_GTX.MUX_SOUTHREFCLKOUT0	MAIN[34][28][19]	MAIN[34][29][19]
NONE	0	0
MGTREFCLKIN0	0	1
MGTREFCLKIN1	1	1
SOUTHREFCLKIN0	1	0

virtex6 GTX enum HCLK_GTX_MUX_SOUTHREFCLKOUT1
HCLK_GTX.MUX_SOUTHREFCLKOUT1	MAIN[34][29][20]	MAIN[34][28][21]
NONE	0	0
MGTREFCLKIN0	0	1
MGTREFCLKIN1	1	1
SOUTHREFCLKIN1	1	0

virtex6 GTX enum HCLK_GTX_MUX_NORTHREFCLKOUT0
HCLK_GTX.MUX_NORTHREFCLKOUT0	MAIN[34][28][16]	MAIN[34][29][16]
NONE	0	0
MGTREFCLKIN0	0	1
MGTREFCLKIN1	1	1
NORTHREFCLKIN0	1	0

virtex6 GTX enum HCLK_GTX_MUX_NORTHREFCLKOUT1
HCLK_GTX.MUX_NORTHREFCLKOUT1	MAIN[34][29][17]	MAIN[34][28][18]
NONE	0	0
MGTREFCLKIN0	0	1
MGTREFCLKIN1	1	1
NORTHREFCLKIN1	1	0

Bels GTCLK

virtex6 GTX bel GTCLK pins
Pin	Direction	GTCLK[0]	GTCLK[1]
CEB	in	CELL[19].IMUX_IMUX_DELAY[31]	CELL[19].IMUX_IMUX_DELAY[30]
CLKTESTSIG	in	CELL[12].IMUX_IMUX_DELAY[17]	CELL[12].IMUX_IMUX_DELAY[16]
CLKOUT	out	CELL[20].MGT_ROW[4]	CELL[20].MGT_ROW[5]

virtex6 GTX bel GTCLK attribute bits
Attribute	GTCLK[0]	GTCLK[1]
CLKCM_CFG	MAIN[11][28][39]	MAIN[11][29][39]
CLKRCV_TRST	MAIN[15][28][30]	MAIN[15][29][30]
MUX_CLKOUT	[enum: GTCLK_MUX_CLKOUT]	[enum: GTCLK_MUX_CLKOUT]
REFCLKOUT_DLY bit 0	MAIN[19][28][0]	MAIN[19][28][8]
REFCLKOUT_DLY bit 1	MAIN[19][29][0]	MAIN[19][29][8]
REFCLKOUT_DLY bit 2	MAIN[19][28][1]	MAIN[19][28][9]
REFCLKOUT_DLY bit 3	MAIN[19][29][1]	MAIN[19][29][9]
REFCLKOUT_DLY bit 4	MAIN[19][28][2]	MAIN[19][28][10]
REFCLKOUT_DLY bit 5	MAIN[19][29][2]	MAIN[19][29][10]
REFCLKOUT_DLY bit 6	MAIN[19][28][3]	MAIN[19][28][11]
REFCLKOUT_DLY bit 7	MAIN[19][29][3]	MAIN[19][29][11]
REFCLKOUT_DLY bit 8	MAIN[19][28][4]	MAIN[19][28][12]
REFCLKOUT_DLY bit 9	MAIN[19][29][4]	MAIN[19][29][12]

virtex6 GTX enum GTCLK_MUX_CLKOUT
GTCLK[0].MUX_CLKOUT	MAIN[18][28][27]	MAIN[18][29][27]
GTCLK[1].MUX_CLKOUT	MAIN[18][28][28]	MAIN[18][29][28]
O	0	0
ODIV2	1	0
NONE	0	1
CLKTESTSIG	1	1

Bels GTX

virtex6 GTX bel GTX pins
Pin	Direction	GTX[0]	GTX[1]	GTX[2]	GTX[3]
DCLK	in	CELL[9].IMUX_CLK[0] invert by !MAIN[7][29][7]	CELL[19].IMUX_CLK[0] invert by !MAIN[17][29][7]	CELL[29].IMUX_CLK[0] invert by !MAIN[27][29][7]	CELL[39].IMUX_CLK[0] invert by !MAIN[37][29][7]
DEN	in	CELL[8].IMUX_IMUX_DELAY[16]	CELL[18].IMUX_IMUX_DELAY[16]	CELL[28].IMUX_IMUX_DELAY[16]	CELL[38].IMUX_IMUX_DELAY[16]
DWE	in	CELL[8].IMUX_IMUX_DELAY[8]	CELL[18].IMUX_IMUX_DELAY[8]	CELL[28].IMUX_IMUX_DELAY[8]	CELL[38].IMUX_IMUX_DELAY[8]
DADDR[0]	in	CELL[9].IMUX_IMUX_DELAY[32]	CELL[19].IMUX_IMUX_DELAY[32]	CELL[29].IMUX_IMUX_DELAY[32]	CELL[39].IMUX_IMUX_DELAY[32]
DADDR[1]	in	CELL[9].IMUX_IMUX_DELAY[33]	CELL[19].IMUX_IMUX_DELAY[33]	CELL[29].IMUX_IMUX_DELAY[33]	CELL[39].IMUX_IMUX_DELAY[33]
DADDR[2]	in	CELL[9].IMUX_IMUX_DELAY[34]	CELL[19].IMUX_IMUX_DELAY[34]	CELL[29].IMUX_IMUX_DELAY[34]	CELL[39].IMUX_IMUX_DELAY[34]
DADDR[3]	in	CELL[9].IMUX_IMUX_DELAY[35]	CELL[19].IMUX_IMUX_DELAY[35]	CELL[29].IMUX_IMUX_DELAY[35]	CELL[39].IMUX_IMUX_DELAY[35]
DADDR[4]	in	CELL[9].IMUX_IMUX_DELAY[36]	CELL[19].IMUX_IMUX_DELAY[36]	CELL[29].IMUX_IMUX_DELAY[36]	CELL[39].IMUX_IMUX_DELAY[36]
DADDR[5]	in	CELL[9].IMUX_IMUX_DELAY[37]	CELL[19].IMUX_IMUX_DELAY[37]	CELL[29].IMUX_IMUX_DELAY[37]	CELL[39].IMUX_IMUX_DELAY[37]
DADDR[6]	in	CELL[9].IMUX_IMUX_DELAY[38]	CELL[19].IMUX_IMUX_DELAY[38]	CELL[29].IMUX_IMUX_DELAY[38]	CELL[39].IMUX_IMUX_DELAY[38]
DADDR[7]	in	CELL[9].IMUX_IMUX_DELAY[39]	CELL[19].IMUX_IMUX_DELAY[39]	CELL[29].IMUX_IMUX_DELAY[39]	CELL[39].IMUX_IMUX_DELAY[39]
DI[0]	in	CELL[9].IMUX_IMUX_DELAY[8]	CELL[19].IMUX_IMUX_DELAY[8]	CELL[29].IMUX_IMUX_DELAY[8]	CELL[39].IMUX_IMUX_DELAY[8]
DI[1]	in	CELL[9].IMUX_IMUX_DELAY[9]	CELL[19].IMUX_IMUX_DELAY[9]	CELL[29].IMUX_IMUX_DELAY[9]	CELL[39].IMUX_IMUX_DELAY[9]
DI[2]	in	CELL[9].IMUX_IMUX_DELAY[10]	CELL[19].IMUX_IMUX_DELAY[10]	CELL[29].IMUX_IMUX_DELAY[10]	CELL[39].IMUX_IMUX_DELAY[10]
DI[3]	in	CELL[9].IMUX_IMUX_DELAY[11]	CELL[19].IMUX_IMUX_DELAY[11]	CELL[29].IMUX_IMUX_DELAY[11]	CELL[39].IMUX_IMUX_DELAY[11]
DI[4]	in	CELL[9].IMUX_IMUX_DELAY[12]	CELL[19].IMUX_IMUX_DELAY[12]	CELL[29].IMUX_IMUX_DELAY[12]	CELL[39].IMUX_IMUX_DELAY[12]
DI[5]	in	CELL[9].IMUX_IMUX_DELAY[13]	CELL[19].IMUX_IMUX_DELAY[13]	CELL[29].IMUX_IMUX_DELAY[13]	CELL[39].IMUX_IMUX_DELAY[13]
DI[6]	in	CELL[9].IMUX_IMUX_DELAY[14]	CELL[19].IMUX_IMUX_DELAY[14]	CELL[29].IMUX_IMUX_DELAY[14]	CELL[39].IMUX_IMUX_DELAY[14]
DI[7]	in	CELL[9].IMUX_IMUX_DELAY[15]	CELL[19].IMUX_IMUX_DELAY[15]	CELL[29].IMUX_IMUX_DELAY[15]	CELL[39].IMUX_IMUX_DELAY[15]
DI[8]	in	CELL[9].IMUX_IMUX_DELAY[16]	CELL[19].IMUX_IMUX_DELAY[16]	CELL[29].IMUX_IMUX_DELAY[16]	CELL[39].IMUX_IMUX_DELAY[16]
DI[9]	in	CELL[9].IMUX_IMUX_DELAY[17]	CELL[19].IMUX_IMUX_DELAY[17]	CELL[29].IMUX_IMUX_DELAY[17]	CELL[39].IMUX_IMUX_DELAY[17]
DI[10]	in	CELL[9].IMUX_IMUX_DELAY[18]	CELL[19].IMUX_IMUX_DELAY[18]	CELL[29].IMUX_IMUX_DELAY[18]	CELL[39].IMUX_IMUX_DELAY[18]
DI[11]	in	CELL[9].IMUX_IMUX_DELAY[19]	CELL[19].IMUX_IMUX_DELAY[19]	CELL[29].IMUX_IMUX_DELAY[19]	CELL[39].IMUX_IMUX_DELAY[19]
DI[12]	in	CELL[9].IMUX_IMUX_DELAY[20]	CELL[19].IMUX_IMUX_DELAY[20]	CELL[29].IMUX_IMUX_DELAY[20]	CELL[39].IMUX_IMUX_DELAY[20]
DI[13]	in	CELL[9].IMUX_IMUX_DELAY[21]	CELL[19].IMUX_IMUX_DELAY[21]	CELL[29].IMUX_IMUX_DELAY[21]	CELL[39].IMUX_IMUX_DELAY[21]
DI[14]	in	CELL[9].IMUX_IMUX_DELAY[22]	CELL[19].IMUX_IMUX_DELAY[22]	CELL[29].IMUX_IMUX_DELAY[22]	CELL[39].IMUX_IMUX_DELAY[22]
DI[15]	in	CELL[9].IMUX_IMUX_DELAY[23]	CELL[19].IMUX_IMUX_DELAY[23]	CELL[29].IMUX_IMUX_DELAY[23]	CELL[39].IMUX_IMUX_DELAY[23]
PLLRXRESET	in	CELL[3].IMUX_CTRL[0]	CELL[13].IMUX_CTRL[0]	CELL[23].IMUX_CTRL[0]	CELL[33].IMUX_CTRL[0]
RXPLLLKDETEN	in	CELL[2].IMUX_IMUX_DELAY[20]	CELL[12].IMUX_IMUX_DELAY[20]	CELL[22].IMUX_IMUX_DELAY[20]	CELL[32].IMUX_IMUX_DELAY[20]
RXPLLPOWERDOWN	in	CELL[2].IMUX_IMUX_DELAY[21]	CELL[12].IMUX_IMUX_DELAY[21]	CELL[22].IMUX_IMUX_DELAY[21]	CELL[32].IMUX_IMUX_DELAY[21]
RXPLLREFSELDY[0]	in	CELL[3].IMUX_IMUX_DELAY[37]	CELL[13].IMUX_IMUX_DELAY[37]	CELL[23].IMUX_IMUX_DELAY[37]	CELL[33].IMUX_IMUX_DELAY[37]
RXPLLREFSELDY[1]	in	CELL[3].IMUX_IMUX_DELAY[22]	CELL[13].IMUX_IMUX_DELAY[22]	CELL[23].IMUX_IMUX_DELAY[22]	CELL[33].IMUX_IMUX_DELAY[22]
RXPLLREFSELDY[2]	in	CELL[3].IMUX_IMUX_DELAY[39]	CELL[13].IMUX_IMUX_DELAY[39]	CELL[23].IMUX_IMUX_DELAY[39]	CELL[33].IMUX_IMUX_DELAY[39]
PLLTXRESET	in	CELL[5].IMUX_CTRL[1]	CELL[15].IMUX_CTRL[1]	CELL[25].IMUX_CTRL[1]	CELL[35].IMUX_CTRL[1]
TXPLLLKDETEN	in	CELL[7].IMUX_IMUX_DELAY[12]	CELL[17].IMUX_IMUX_DELAY[12]	CELL[27].IMUX_IMUX_DELAY[12]	CELL[37].IMUX_IMUX_DELAY[12]
TXPLLPOWERDOWN	in	CELL[7].IMUX_IMUX_DELAY[29]	CELL[17].IMUX_IMUX_DELAY[29]	CELL[27].IMUX_IMUX_DELAY[29]	CELL[37].IMUX_IMUX_DELAY[29]
TXPLLREFSELDY[0]	in	CELL[7].IMUX_IMUX_DELAY[37]	CELL[17].IMUX_IMUX_DELAY[37]	CELL[27].IMUX_IMUX_DELAY[37]	CELL[37].IMUX_IMUX_DELAY[37]
TXPLLREFSELDY[1]	in	CELL[7].IMUX_IMUX_DELAY[38]	CELL[17].IMUX_IMUX_DELAY[38]	CELL[27].IMUX_IMUX_DELAY[38]	CELL[37].IMUX_IMUX_DELAY[38]
TXPLLREFSELDY[2]	in	CELL[7].IMUX_IMUX_DELAY[39]	CELL[17].IMUX_IMUX_DELAY[39]	CELL[27].IMUX_IMUX_DELAY[39]	CELL[37].IMUX_IMUX_DELAY[39]
GREFCLKRX	in	CELL[3].IMUX_CLK[0] invert by !MAIN[8][29][31]	CELL[13].IMUX_CLK[0] invert by !MAIN[18][29][31]	CELL[23].IMUX_CLK[0] invert by !MAIN[28][29][31]	CELL[33].IMUX_CLK[0] invert by !MAIN[38][29][31]
GREFCLKTX	in	CELL[7].IMUX_CLK[0] invert by !MAIN[8][28][31]	CELL[17].IMUX_CLK[0] invert by !MAIN[18][28][31]	CELL[27].IMUX_CLK[0] invert by !MAIN[28][28][31]	CELL[37].IMUX_CLK[0] invert by !MAIN[38][28][31]
PERFCLKRX	in	CELL[20].IMUX_GTX_PERFCLK	CELL[20].IMUX_GTX_PERFCLK	CELL[20].IMUX_GTX_PERFCLK	CELL[20].IMUX_GTX_PERFCLK
PERFCLKTX	in	CELL[20].IMUX_GTX_PERFCLK	CELL[20].IMUX_GTX_PERFCLK	CELL[20].IMUX_GTX_PERFCLK	CELL[20].IMUX_GTX_PERFCLK
GTXRXRESET	in	CELL[1].IMUX_CTRL[0]	CELL[11].IMUX_CTRL[0]	CELL[21].IMUX_CTRL[0]	CELL[31].IMUX_CTRL[0]
GTXTXRESET	in	CELL[6].IMUX_CTRL[1]	CELL[16].IMUX_CTRL[1]	CELL[26].IMUX_CTRL[1]	CELL[36].IMUX_CTRL[1]
GTXTEST[0]	in	CELL[2].IMUX_IMUX_DELAY[39]	CELL[12].IMUX_IMUX_DELAY[39]	CELL[22].IMUX_IMUX_DELAY[39]	CELL[32].IMUX_IMUX_DELAY[39]
GTXTEST[1]	in	CELL[2].IMUX_IMUX_DELAY[38]	CELL[12].IMUX_IMUX_DELAY[38]	CELL[22].IMUX_IMUX_DELAY[38]	CELL[32].IMUX_IMUX_DELAY[38]
GTXTEST[2]	in	CELL[2].IMUX_IMUX_DELAY[37]	CELL[12].IMUX_IMUX_DELAY[37]	CELL[22].IMUX_IMUX_DELAY[37]	CELL[32].IMUX_IMUX_DELAY[37]
GTXTEST[3]	in	CELL[2].IMUX_IMUX_DELAY[36]	CELL[12].IMUX_IMUX_DELAY[36]	CELL[22].IMUX_IMUX_DELAY[36]	CELL[32].IMUX_IMUX_DELAY[36]
GTXTEST[4]	in	CELL[2].IMUX_IMUX_DELAY[35]	CELL[12].IMUX_IMUX_DELAY[35]	CELL[22].IMUX_IMUX_DELAY[35]	CELL[32].IMUX_IMUX_DELAY[35]
GTXTEST[5]	in	CELL[2].IMUX_IMUX_DELAY[34]	CELL[12].IMUX_IMUX_DELAY[34]	CELL[22].IMUX_IMUX_DELAY[34]	CELL[32].IMUX_IMUX_DELAY[34]
GTXTEST[6]	in	CELL[2].IMUX_IMUX_DELAY[33]	CELL[12].IMUX_IMUX_DELAY[33]	CELL[22].IMUX_IMUX_DELAY[33]	CELL[32].IMUX_IMUX_DELAY[33]
GTXTEST[7]	in	CELL[2].IMUX_IMUX_DELAY[32]	CELL[12].IMUX_IMUX_DELAY[32]	CELL[22].IMUX_IMUX_DELAY[32]	CELL[32].IMUX_IMUX_DELAY[32]
GTXTEST[8]	in	CELL[2].IMUX_IMUX_DELAY[31]	CELL[12].IMUX_IMUX_DELAY[31]	CELL[22].IMUX_IMUX_DELAY[31]	CELL[32].IMUX_IMUX_DELAY[31]
GTXTEST[9]	in	CELL[2].IMUX_IMUX_DELAY[30]	CELL[12].IMUX_IMUX_DELAY[30]	CELL[22].IMUX_IMUX_DELAY[30]	CELL[32].IMUX_IMUX_DELAY[30]
GTXTEST[10]	in	CELL[2].IMUX_IMUX_DELAY[29]	CELL[12].IMUX_IMUX_DELAY[29]	CELL[22].IMUX_IMUX_DELAY[29]	CELL[32].IMUX_IMUX_DELAY[29]
GTXTEST[11]	in	CELL[2].IMUX_IMUX_DELAY[28]	CELL[12].IMUX_IMUX_DELAY[28]	CELL[22].IMUX_IMUX_DELAY[28]	CELL[32].IMUX_IMUX_DELAY[28]
GTXTEST[12]	in	CELL[2].IMUX_IMUX_DELAY[27]	CELL[12].IMUX_IMUX_DELAY[27]	CELL[22].IMUX_IMUX_DELAY[27]	CELL[32].IMUX_IMUX_DELAY[27]
LOOPBACK[0]	in	CELL[3].IMUX_IMUX_DELAY[24]	CELL[13].IMUX_IMUX_DELAY[24]	CELL[23].IMUX_IMUX_DELAY[24]	CELL[33].IMUX_IMUX_DELAY[24]
LOOPBACK[1]	in	CELL[3].IMUX_IMUX_DELAY[11]	CELL[13].IMUX_IMUX_DELAY[11]	CELL[23].IMUX_IMUX_DELAY[11]	CELL[33].IMUX_IMUX_DELAY[11]
LOOPBACK[2]	in	CELL[3].IMUX_IMUX_DELAY[27]	CELL[13].IMUX_IMUX_DELAY[27]	CELL[23].IMUX_IMUX_DELAY[27]	CELL[33].IMUX_IMUX_DELAY[27]
CLKTESTSIG[0]	in	CELL[2].IMUX_IMUX_DELAY[19]	CELL[12].IMUX_IMUX_DELAY[19]	CELL[22].IMUX_IMUX_DELAY[19]	CELL[32].IMUX_IMUX_DELAY[19]
CLKTESTSIG[1]	in	CELL[2].IMUX_IMUX_DELAY[18]	CELL[12].IMUX_IMUX_DELAY[18]	CELL[22].IMUX_IMUX_DELAY[18]	CELL[32].IMUX_IMUX_DELAY[18]
USRCODEERR	in	CELL[2].IMUX_IMUX_DELAY[14]	CELL[12].IMUX_IMUX_DELAY[14]	CELL[22].IMUX_IMUX_DELAY[14]	CELL[32].IMUX_IMUX_DELAY[14]
RXRESET	in	CELL[2].IMUX_CTRL[1]	CELL[12].IMUX_CTRL[1]	CELL[22].IMUX_CTRL[1]	CELL[32].IMUX_CTRL[1]
RXUSRCLK	in	CELL[2].IMUX_CLK[0] invert by !MAIN[0][28][47]	CELL[12].IMUX_CLK[0] invert by !MAIN[10][28][47]	CELL[22].IMUX_CLK[0] invert by !MAIN[20][28][47]	CELL[32].IMUX_CLK[0] invert by !MAIN[30][28][47]
RXUSRCLK2	in	CELL[2].IMUX_CLK[1] invert by !MAIN[0][29][47]	CELL[12].IMUX_CLK[1] invert by !MAIN[10][29][47]	CELL[22].IMUX_CLK[1] invert by !MAIN[20][29][47]	CELL[32].IMUX_CLK[1] invert by !MAIN[30][29][47]
GATERXELECIDLE	in	CELL[6].IMUX_IMUX_DELAY[32]	CELL[16].IMUX_IMUX_DELAY[32]	CELL[26].IMUX_IMUX_DELAY[32]	CELL[36].IMUX_IMUX_DELAY[32]
IGNORESIGDET	in	CELL[6].IMUX_IMUX_DELAY[37]	CELL[16].IMUX_IMUX_DELAY[37]	CELL[26].IMUX_IMUX_DELAY[37]	CELL[36].IMUX_IMUX_DELAY[37]
RXPOWERDOWN[0]	in	CELL[4].IMUX_IMUX_DELAY[13]	CELL[14].IMUX_IMUX_DELAY[13]	CELL[24].IMUX_IMUX_DELAY[13]	CELL[34].IMUX_IMUX_DELAY[13]
RXPOWERDOWN[1]	in	CELL[4].IMUX_IMUX_DELAY[21]	CELL[14].IMUX_IMUX_DELAY[21]	CELL[24].IMUX_IMUX_DELAY[21]	CELL[34].IMUX_IMUX_DELAY[21]
DFECLKDLYADJ[0]	in	CELL[4].IMUX_IMUX_DELAY[35]	CELL[14].IMUX_IMUX_DELAY[35]	CELL[24].IMUX_IMUX_DELAY[35]	CELL[34].IMUX_IMUX_DELAY[35]
DFECLKDLYADJ[1]	in	CELL[4].IMUX_IMUX_DELAY[19]	CELL[14].IMUX_IMUX_DELAY[19]	CELL[24].IMUX_IMUX_DELAY[19]	CELL[34].IMUX_IMUX_DELAY[19]
DFECLKDLYADJ[2]	in	CELL[4].IMUX_IMUX_DELAY[18]	CELL[14].IMUX_IMUX_DELAY[18]	CELL[24].IMUX_IMUX_DELAY[18]	CELL[34].IMUX_IMUX_DELAY[18]
DFECLKDLYADJ[3]	in	CELL[4].IMUX_IMUX_DELAY[33]	CELL[14].IMUX_IMUX_DELAY[33]	CELL[24].IMUX_IMUX_DELAY[33]	CELL[34].IMUX_IMUX_DELAY[33]
DFECLKDLYADJ[4]	in	CELL[4].IMUX_IMUX_DELAY[17]	CELL[14].IMUX_IMUX_DELAY[17]	CELL[24].IMUX_IMUX_DELAY[17]	CELL[34].IMUX_IMUX_DELAY[17]
DFECLKDLYADJ[5]	in	CELL[4].IMUX_IMUX_DELAY[16]	CELL[14].IMUX_IMUX_DELAY[16]	CELL[24].IMUX_IMUX_DELAY[16]	CELL[34].IMUX_IMUX_DELAY[16]
DFEDLYOVRD	in	CELL[4].IMUX_IMUX_DELAY[29]	CELL[14].IMUX_IMUX_DELAY[29]	CELL[24].IMUX_IMUX_DELAY[29]	CELL[34].IMUX_IMUX_DELAY[29]
DFETAP1[0]	in	CELL[4].IMUX_IMUX_DELAY[8]	CELL[14].IMUX_IMUX_DELAY[8]	CELL[24].IMUX_IMUX_DELAY[8]	CELL[34].IMUX_IMUX_DELAY[8]
DFETAP1[1]	in	CELL[4].IMUX_IMUX_DELAY[10]	CELL[14].IMUX_IMUX_DELAY[10]	CELL[24].IMUX_IMUX_DELAY[10]	CELL[34].IMUX_IMUX_DELAY[10]
DFETAP1[2]	in	CELL[4].IMUX_IMUX_DELAY[14]	CELL[14].IMUX_IMUX_DELAY[14]	CELL[24].IMUX_IMUX_DELAY[14]	CELL[34].IMUX_IMUX_DELAY[14]
DFETAP1[3]	in	CELL[4].IMUX_IMUX_DELAY[15]	CELL[14].IMUX_IMUX_DELAY[15]	CELL[24].IMUX_IMUX_DELAY[15]	CELL[34].IMUX_IMUX_DELAY[15]
DFETAP1[4]	in	CELL[4].IMUX_IMUX_DELAY[38]	CELL[14].IMUX_IMUX_DELAY[38]	CELL[24].IMUX_IMUX_DELAY[38]	CELL[34].IMUX_IMUX_DELAY[38]
DFETAP2[0]	in	CELL[4].IMUX_IMUX_DELAY[24]	CELL[14].IMUX_IMUX_DELAY[24]	CELL[24].IMUX_IMUX_DELAY[24]	CELL[34].IMUX_IMUX_DELAY[24]
DFETAP2[1]	in	CELL[4].IMUX_IMUX_DELAY[25]	CELL[14].IMUX_IMUX_DELAY[25]	CELL[24].IMUX_IMUX_DELAY[25]	CELL[34].IMUX_IMUX_DELAY[25]
DFETAP2[2]	in	CELL[4].IMUX_IMUX_DELAY[30]	CELL[14].IMUX_IMUX_DELAY[30]	CELL[24].IMUX_IMUX_DELAY[30]	CELL[34].IMUX_IMUX_DELAY[30]
DFETAP2[3]	in	CELL[4].IMUX_IMUX_DELAY[31]	CELL[14].IMUX_IMUX_DELAY[31]	CELL[24].IMUX_IMUX_DELAY[31]	CELL[34].IMUX_IMUX_DELAY[31]
DFETAP2[4]	in	CELL[4].IMUX_IMUX_DELAY[39]	CELL[14].IMUX_IMUX_DELAY[39]	CELL[24].IMUX_IMUX_DELAY[39]	CELL[34].IMUX_IMUX_DELAY[39]
DFETAP3[0]	in	CELL[6].IMUX_IMUX_DELAY[10]	CELL[16].IMUX_IMUX_DELAY[10]	CELL[26].IMUX_IMUX_DELAY[10]	CELL[36].IMUX_IMUX_DELAY[10]
DFETAP3[1]	in	CELL[6].IMUX_IMUX_DELAY[9]	CELL[16].IMUX_IMUX_DELAY[9]	CELL[26].IMUX_IMUX_DELAY[9]	CELL[36].IMUX_IMUX_DELAY[9]
DFETAP3[2]	in	CELL[6].IMUX_IMUX_DELAY[12]	CELL[16].IMUX_IMUX_DELAY[12]	CELL[26].IMUX_IMUX_DELAY[12]	CELL[36].IMUX_IMUX_DELAY[12]
DFETAP3[3]	in	CELL[6].IMUX_IMUX_DELAY[17]	CELL[16].IMUX_IMUX_DELAY[17]	CELL[26].IMUX_IMUX_DELAY[17]	CELL[36].IMUX_IMUX_DELAY[17]
DFETAP4[0]	in	CELL[6].IMUX_IMUX_DELAY[26]	CELL[16].IMUX_IMUX_DELAY[26]	CELL[26].IMUX_IMUX_DELAY[26]	CELL[36].IMUX_IMUX_DELAY[26]
DFETAP4[1]	in	CELL[6].IMUX_IMUX_DELAY[25]	CELL[16].IMUX_IMUX_DELAY[25]	CELL[26].IMUX_IMUX_DELAY[25]	CELL[36].IMUX_IMUX_DELAY[25]
DFETAP4[2]	in	CELL[6].IMUX_IMUX_DELAY[28]	CELL[16].IMUX_IMUX_DELAY[28]	CELL[26].IMUX_IMUX_DELAY[28]	CELL[36].IMUX_IMUX_DELAY[28]
DFETAP4[3]	in	CELL[6].IMUX_IMUX_DELAY[20]	CELL[16].IMUX_IMUX_DELAY[20]	CELL[26].IMUX_IMUX_DELAY[20]	CELL[36].IMUX_IMUX_DELAY[20]
DFETAPOVRD	in	CELL[4].IMUX_IMUX_DELAY[37]	CELL[14].IMUX_IMUX_DELAY[37]	CELL[24].IMUX_IMUX_DELAY[37]	CELL[34].IMUX_IMUX_DELAY[37]
RXEQMIX[0]	in	CELL[1].IMUX_IMUX_DELAY[14]	CELL[11].IMUX_IMUX_DELAY[14]	CELL[21].IMUX_IMUX_DELAY[14]	CELL[31].IMUX_IMUX_DELAY[14]
RXEQMIX[1]	in	CELL[1].IMUX_IMUX_DELAY[15]	CELL[11].IMUX_IMUX_DELAY[15]	CELL[21].IMUX_IMUX_DELAY[15]	CELL[31].IMUX_IMUX_DELAY[15]
RXEQMIX[2]	in	CELL[1].IMUX_IMUX_DELAY[30]	CELL[11].IMUX_IMUX_DELAY[30]	CELL[21].IMUX_IMUX_DELAY[30]	CELL[31].IMUX_IMUX_DELAY[30]
RXEQMIX[3]	in	CELL[1].IMUX_IMUX_DELAY[22]	CELL[11].IMUX_IMUX_DELAY[22]	CELL[21].IMUX_IMUX_DELAY[22]	CELL[31].IMUX_IMUX_DELAY[22]
RXEQMIX[4]	in	CELL[1].IMUX_IMUX_DELAY[29]	CELL[11].IMUX_IMUX_DELAY[29]	CELL[21].IMUX_IMUX_DELAY[29]	CELL[31].IMUX_IMUX_DELAY[29]
RXEQMIX[5]	in	CELL[1].IMUX_IMUX_DELAY[21]	CELL[11].IMUX_IMUX_DELAY[21]	CELL[21].IMUX_IMUX_DELAY[21]	CELL[31].IMUX_IMUX_DELAY[21]
RXEQMIX[6]	in	CELL[1].IMUX_IMUX_DELAY[28]	CELL[11].IMUX_IMUX_DELAY[28]	CELL[21].IMUX_IMUX_DELAY[28]	CELL[31].IMUX_IMUX_DELAY[28]
RXEQMIX[7]	in	CELL[1].IMUX_IMUX_DELAY[20]	CELL[11].IMUX_IMUX_DELAY[20]	CELL[21].IMUX_IMUX_DELAY[20]	CELL[31].IMUX_IMUX_DELAY[20]
RXEQMIX[8]	in	CELL[1].IMUX_IMUX_DELAY[27]	CELL[11].IMUX_IMUX_DELAY[27]	CELL[21].IMUX_IMUX_DELAY[27]	CELL[31].IMUX_IMUX_DELAY[27]
RXEQMIX[9]	in	CELL[1].IMUX_IMUX_DELAY[19]	CELL[11].IMUX_IMUX_DELAY[19]	CELL[21].IMUX_IMUX_DELAY[19]	CELL[31].IMUX_IMUX_DELAY[19]
RXCDRRESET	in	CELL[1].IMUX_CTRL[1]	CELL[11].IMUX_CTRL[1]	CELL[21].IMUX_CTRL[1]	CELL[31].IMUX_CTRL[1]
RXRATE[0]	in	CELL[6].IMUX_IMUX_DELAY[42]	CELL[16].IMUX_IMUX_DELAY[42]	CELL[26].IMUX_IMUX_DELAY[42]	CELL[36].IMUX_IMUX_DELAY[42]
RXRATE[1]	in	CELL[6].IMUX_IMUX_DELAY[41]	CELL[16].IMUX_IMUX_DELAY[41]	CELL[26].IMUX_IMUX_DELAY[41]	CELL[36].IMUX_IMUX_DELAY[41]
RXPOLARITY	in	CELL[1].IMUX_IMUX_DELAY[26]	CELL[11].IMUX_IMUX_DELAY[26]	CELL[21].IMUX_IMUX_DELAY[26]	CELL[31].IMUX_IMUX_DELAY[26]
RXENSAMPLEALIGN	in	CELL[1].IMUX_IMUX_DELAY[32]	CELL[11].IMUX_IMUX_DELAY[32]	CELL[21].IMUX_IMUX_DELAY[32]	CELL[31].IMUX_IMUX_DELAY[32]
PRBSCNTRESET	in	CELL[0].IMUX_CTRL[1]	CELL[10].IMUX_CTRL[1]	CELL[20].IMUX_CTRL[1]	CELL[30].IMUX_CTRL[1]
RXENPRBSTST[0]	in	CELL[1].IMUX_IMUX_DELAY[33]	CELL[11].IMUX_IMUX_DELAY[33]	CELL[21].IMUX_IMUX_DELAY[33]	CELL[31].IMUX_IMUX_DELAY[33]
RXENPRBSTST[1]	in	CELL[1].IMUX_IMUX_DELAY[34]	CELL[11].IMUX_IMUX_DELAY[34]	CELL[21].IMUX_IMUX_DELAY[34]	CELL[31].IMUX_IMUX_DELAY[34]
RXENPRBSTST[2]	in	CELL[1].IMUX_IMUX_DELAY[18]	CELL[11].IMUX_IMUX_DELAY[18]	CELL[21].IMUX_IMUX_DELAY[18]	CELL[31].IMUX_IMUX_DELAY[18]
RXCOMMADETUSE	in	CELL[3].IMUX_IMUX_DELAY[36]	CELL[13].IMUX_IMUX_DELAY[36]	CELL[23].IMUX_IMUX_DELAY[36]	CELL[33].IMUX_IMUX_DELAY[36]
RXENMCOMMAALIGN	in	CELL[1].IMUX_IMUX_DELAY[36]	CELL[11].IMUX_IMUX_DELAY[36]	CELL[21].IMUX_IMUX_DELAY[36]	CELL[31].IMUX_IMUX_DELAY[36]
RXENPCOMMAALIGN	in	CELL[1].IMUX_IMUX_DELAY[37]	CELL[11].IMUX_IMUX_DELAY[37]	CELL[21].IMUX_IMUX_DELAY[37]	CELL[31].IMUX_IMUX_DELAY[37]
RXSLIDE	in	CELL[1].IMUX_IMUX_DELAY[9]	CELL[11].IMUX_IMUX_DELAY[9]	CELL[21].IMUX_IMUX_DELAY[9]	CELL[31].IMUX_IMUX_DELAY[9]
RXDEC8B10BUSE	in	CELL[1].IMUX_IMUX_DELAY[39]	CELL[11].IMUX_IMUX_DELAY[39]	CELL[21].IMUX_IMUX_DELAY[39]	CELL[31].IMUX_IMUX_DELAY[39]
RXDLYALIGNDISABLE	in	CELL[5].IMUX_IMUX_DELAY[14]	CELL[15].IMUX_IMUX_DELAY[14]	CELL[25].IMUX_IMUX_DELAY[14]	CELL[35].IMUX_IMUX_DELAY[14]
RXDLYALIGNFORCEROTATEB	in	CELL[3].IMUX_IMUX_DELAY[25]	CELL[13].IMUX_IMUX_DELAY[25]	CELL[23].IMUX_IMUX_DELAY[25]	CELL[33].IMUX_IMUX_DELAY[25]
RXDLYALIGNMONENB	in	CELL[3].IMUX_IMUX_DELAY[28]	CELL[13].IMUX_IMUX_DELAY[28]	CELL[23].IMUX_IMUX_DELAY[28]	CELL[33].IMUX_IMUX_DELAY[28]
RXDLYALIGNOVERRIDE	in	CELL[5].IMUX_IMUX_DELAY[33]	CELL[15].IMUX_IMUX_DELAY[33]	CELL[25].IMUX_IMUX_DELAY[33]	CELL[35].IMUX_IMUX_DELAY[33]
RXDLYALIGNRESET	in	CELL[5].IMUX_IMUX_DELAY[29]	CELL[15].IMUX_IMUX_DELAY[29]	CELL[25].IMUX_IMUX_DELAY[29]	CELL[35].IMUX_IMUX_DELAY[29]
RXDLYALIGNSWPPRECURB	in	CELL[3].IMUX_IMUX_DELAY[29]	CELL[13].IMUX_IMUX_DELAY[29]	CELL[23].IMUX_IMUX_DELAY[29]	CELL[33].IMUX_IMUX_DELAY[29]
RXDLYALIGNTESTMODEENB	in	CELL[3].IMUX_IMUX_DELAY[12]	CELL[13].IMUX_IMUX_DELAY[12]	CELL[23].IMUX_IMUX_DELAY[12]	CELL[33].IMUX_IMUX_DELAY[12]
RXDLYALIGNUPDSW	in	CELL[5].IMUX_IMUX_DELAY[10]	CELL[15].IMUX_IMUX_DELAY[10]	CELL[25].IMUX_IMUX_DELAY[10]	CELL[35].IMUX_IMUX_DELAY[10]
RXENPMAPHASEALIGN	in	CELL[1].IMUX_IMUX_DELAY[35]	CELL[11].IMUX_IMUX_DELAY[35]	CELL[21].IMUX_IMUX_DELAY[35]	CELL[31].IMUX_IMUX_DELAY[35]
RXPMASETPHASE	in	CELL[1].IMUX_IMUX_DELAY[11]	CELL[11].IMUX_IMUX_DELAY[11]	CELL[21].IMUX_IMUX_DELAY[11]	CELL[31].IMUX_IMUX_DELAY[11]
RXBUFRESET	in	CELL[2].IMUX_CTRL[0]	CELL[12].IMUX_CTRL[0]	CELL[22].IMUX_CTRL[0]	CELL[32].IMUX_CTRL[0]
RXBUFWE	in	CELL[1].IMUX_IMUX_DELAY[24]	CELL[11].IMUX_IMUX_DELAY[24]	CELL[21].IMUX_IMUX_DELAY[24]	CELL[31].IMUX_IMUX_DELAY[24]
RXCHBONDI[0]	in	CELL[3].IMUX_IMUX_DELAY[32]	CELL[13].IMUX_IMUX_DELAY[32]	CELL[23].IMUX_IMUX_DELAY[32]	CELL[33].IMUX_IMUX_DELAY[32]
RXCHBONDI[1]	in	CELL[3].IMUX_IMUX_DELAY[33]	CELL[13].IMUX_IMUX_DELAY[33]	CELL[23].IMUX_IMUX_DELAY[33]	CELL[33].IMUX_IMUX_DELAY[33]
RXCHBONDI[2]	in	CELL[3].IMUX_IMUX_DELAY[34]	CELL[13].IMUX_IMUX_DELAY[34]	CELL[23].IMUX_IMUX_DELAY[34]	CELL[33].IMUX_IMUX_DELAY[34]
RXCHBONDI[3]	in	CELL[3].IMUX_IMUX_DELAY[35]	CELL[13].IMUX_IMUX_DELAY[35]	CELL[23].IMUX_IMUX_DELAY[35]	CELL[33].IMUX_IMUX_DELAY[35]
RXCHBONDLEVEL[0]	in	CELL[2].IMUX_IMUX_DELAY[10]	CELL[12].IMUX_IMUX_DELAY[10]	CELL[22].IMUX_IMUX_DELAY[10]	CELL[32].IMUX_IMUX_DELAY[10]
RXCHBONDLEVEL[1]	in	CELL[2].IMUX_IMUX_DELAY[26]	CELL[12].IMUX_IMUX_DELAY[26]	CELL[22].IMUX_IMUX_DELAY[26]	CELL[32].IMUX_IMUX_DELAY[26]
RXCHBONDLEVEL[2]	in	CELL[2].IMUX_IMUX_DELAY[11]	CELL[12].IMUX_IMUX_DELAY[11]	CELL[22].IMUX_IMUX_DELAY[11]	CELL[32].IMUX_IMUX_DELAY[11]
RXCHBONDMASTER	in	CELL[2].IMUX_IMUX_DELAY[24]	CELL[12].IMUX_IMUX_DELAY[24]	CELL[22].IMUX_IMUX_DELAY[24]	CELL[32].IMUX_IMUX_DELAY[24]
RXCHBONDSLAVE	in	CELL[2].IMUX_IMUX_DELAY[8]	CELL[12].IMUX_IMUX_DELAY[8]	CELL[22].IMUX_IMUX_DELAY[8]	CELL[32].IMUX_IMUX_DELAY[8]
RXENCHANSYNC	in	CELL[1].IMUX_IMUX_DELAY[38]	CELL[11].IMUX_IMUX_DELAY[38]	CELL[21].IMUX_IMUX_DELAY[38]	CELL[31].IMUX_IMUX_DELAY[38]
RXGEARBOXSLIP	in	CELL[1].IMUX_IMUX_DELAY[12]	CELL[11].IMUX_IMUX_DELAY[12]	CELL[21].IMUX_IMUX_DELAY[12]	CELL[31].IMUX_IMUX_DELAY[12]
TXUSRCLK	in	CELL[6].IMUX_CLK[0] invert by !MAIN[6][28][7]	CELL[16].IMUX_CLK[0] invert by !MAIN[16][28][7]	CELL[26].IMUX_CLK[0] invert by !MAIN[26][28][7]	CELL[36].IMUX_CLK[0] invert by !MAIN[36][28][7]
TXUSRCLK2	in	CELL[6].IMUX_CLK[1] invert by !MAIN[6][29][7]	CELL[16].IMUX_CLK[1] invert by !MAIN[16][29][7]	CELL[26].IMUX_CLK[1] invert by !MAIN[26][29][7]	CELL[36].IMUX_CLK[1] invert by !MAIN[36][29][7]
TXRESET	in	CELL[6].IMUX_CTRL[0]	CELL[16].IMUX_CTRL[0]	CELL[26].IMUX_CTRL[0]	CELL[36].IMUX_CTRL[0]
TXDATA[0]	in	CELL[8].IMUX_IMUX_DELAY[38]	CELL[18].IMUX_IMUX_DELAY[38]	CELL[28].IMUX_IMUX_DELAY[38]	CELL[38].IMUX_IMUX_DELAY[38]
TXDATA[1]	in	CELL[8].IMUX_IMUX_DELAY[36]	CELL[18].IMUX_IMUX_DELAY[36]	CELL[28].IMUX_IMUX_DELAY[36]	CELL[38].IMUX_IMUX_DELAY[36]
TXDATA[2]	in	CELL[8].IMUX_IMUX_DELAY[28]	CELL[18].IMUX_IMUX_DELAY[28]	CELL[28].IMUX_IMUX_DELAY[28]	CELL[38].IMUX_IMUX_DELAY[28]
TXDATA[3]	in	CELL[8].IMUX_IMUX_DELAY[32]	CELL[18].IMUX_IMUX_DELAY[32]	CELL[28].IMUX_IMUX_DELAY[32]	CELL[38].IMUX_IMUX_DELAY[32]
TXDATA[4]	in	CELL[8].IMUX_IMUX_DELAY[26]	CELL[18].IMUX_IMUX_DELAY[26]	CELL[28].IMUX_IMUX_DELAY[26]	CELL[38].IMUX_IMUX_DELAY[26]
TXDATA[5]	in	CELL[8].IMUX_IMUX_DELAY[34]	CELL[18].IMUX_IMUX_DELAY[34]	CELL[28].IMUX_IMUX_DELAY[34]	CELL[38].IMUX_IMUX_DELAY[34]
TXDATA[6]	in	CELL[7].IMUX_IMUX_DELAY[34]	CELL[17].IMUX_IMUX_DELAY[34]	CELL[27].IMUX_IMUX_DELAY[34]	CELL[37].IMUX_IMUX_DELAY[34]
TXDATA[7]	in	CELL[7].IMUX_IMUX_DELAY[26]	CELL[17].IMUX_IMUX_DELAY[26]	CELL[27].IMUX_IMUX_DELAY[26]	CELL[37].IMUX_IMUX_DELAY[26]
TXDATA[8]	in	CELL[7].IMUX_IMUX_DELAY[15]	CELL[17].IMUX_IMUX_DELAY[15]	CELL[27].IMUX_IMUX_DELAY[15]	CELL[37].IMUX_IMUX_DELAY[15]
TXDATA[9]	in	CELL[7].IMUX_IMUX_DELAY[21]	CELL[17].IMUX_IMUX_DELAY[21]	CELL[27].IMUX_IMUX_DELAY[21]	CELL[37].IMUX_IMUX_DELAY[21]
TXDATA[10]	in	CELL[7].IMUX_IMUX_DELAY[13]	CELL[17].IMUX_IMUX_DELAY[13]	CELL[27].IMUX_IMUX_DELAY[13]	CELL[37].IMUX_IMUX_DELAY[13]
TXDATA[11]	in	CELL[7].IMUX_IMUX_DELAY[40]	CELL[17].IMUX_IMUX_DELAY[40]	CELL[27].IMUX_IMUX_DELAY[40]	CELL[37].IMUX_IMUX_DELAY[40]
TXDATA[12]	in	CELL[6].IMUX_IMUX_DELAY[3]	CELL[16].IMUX_IMUX_DELAY[3]	CELL[26].IMUX_IMUX_DELAY[3]	CELL[36].IMUX_IMUX_DELAY[3]
TXDATA[13]	in	CELL[6].IMUX_IMUX_DELAY[30]	CELL[16].IMUX_IMUX_DELAY[30]	CELL[26].IMUX_IMUX_DELAY[30]	CELL[36].IMUX_IMUX_DELAY[30]
TXDATA[14]	in	CELL[6].IMUX_IMUX_DELAY[5]	CELL[16].IMUX_IMUX_DELAY[5]	CELL[26].IMUX_IMUX_DELAY[5]	CELL[36].IMUX_IMUX_DELAY[5]
TXDATA[15]	in	CELL[6].IMUX_IMUX_DELAY[13]	CELL[16].IMUX_IMUX_DELAY[13]	CELL[26].IMUX_IMUX_DELAY[13]	CELL[36].IMUX_IMUX_DELAY[13]
TXDATA[16]	in	CELL[8].IMUX_IMUX_DELAY[31]	CELL[18].IMUX_IMUX_DELAY[31]	CELL[28].IMUX_IMUX_DELAY[31]	CELL[38].IMUX_IMUX_DELAY[31]
TXDATA[17]	in	CELL[8].IMUX_IMUX_DELAY[30]	CELL[18].IMUX_IMUX_DELAY[30]	CELL[28].IMUX_IMUX_DELAY[30]	CELL[38].IMUX_IMUX_DELAY[30]
TXDATA[18]	in	CELL[8].IMUX_IMUX_DELAY[29]	CELL[18].IMUX_IMUX_DELAY[29]	CELL[28].IMUX_IMUX_DELAY[29]	CELL[38].IMUX_IMUX_DELAY[29]
TXDATA[19]	in	CELL[8].IMUX_IMUX_DELAY[27]	CELL[18].IMUX_IMUX_DELAY[27]	CELL[28].IMUX_IMUX_DELAY[27]	CELL[38].IMUX_IMUX_DELAY[27]
TXDATA[20]	in	CELL[7].IMUX_IMUX_DELAY[27]	CELL[17].IMUX_IMUX_DELAY[27]	CELL[27].IMUX_IMUX_DELAY[27]	CELL[37].IMUX_IMUX_DELAY[27]
TXDATA[21]	in	CELL[7].IMUX_IMUX_DELAY[28]	CELL[17].IMUX_IMUX_DELAY[28]	CELL[27].IMUX_IMUX_DELAY[28]	CELL[37].IMUX_IMUX_DELAY[28]
TXDATA[22]	in	CELL[7].IMUX_IMUX_DELAY[25]	CELL[17].IMUX_IMUX_DELAY[25]	CELL[27].IMUX_IMUX_DELAY[25]	CELL[37].IMUX_IMUX_DELAY[25]
TXDATA[23]	in	CELL[7].IMUX_IMUX_DELAY[24]	CELL[17].IMUX_IMUX_DELAY[24]	CELL[27].IMUX_IMUX_DELAY[24]	CELL[37].IMUX_IMUX_DELAY[24]
TXDATA[24]	in	CELL[8].IMUX_IMUX_DELAY[39]	CELL[18].IMUX_IMUX_DELAY[39]	CELL[28].IMUX_IMUX_DELAY[39]	CELL[38].IMUX_IMUX_DELAY[39]
TXDATA[25]	in	CELL[8].IMUX_IMUX_DELAY[19]	CELL[18].IMUX_IMUX_DELAY[19]	CELL[28].IMUX_IMUX_DELAY[19]	CELL[38].IMUX_IMUX_DELAY[19]
TXDATA[26]	in	CELL[8].IMUX_IMUX_DELAY[37]	CELL[18].IMUX_IMUX_DELAY[37]	CELL[28].IMUX_IMUX_DELAY[37]	CELL[38].IMUX_IMUX_DELAY[37]
TXDATA[27]	in	CELL[8].IMUX_IMUX_DELAY[35]	CELL[18].IMUX_IMUX_DELAY[35]	CELL[28].IMUX_IMUX_DELAY[35]	CELL[38].IMUX_IMUX_DELAY[35]
TXDATA[28]	in	CELL[7].IMUX_IMUX_DELAY[35]	CELL[17].IMUX_IMUX_DELAY[35]	CELL[27].IMUX_IMUX_DELAY[35]	CELL[37].IMUX_IMUX_DELAY[35]
TXDATA[29]	in	CELL[7].IMUX_IMUX_DELAY[36]	CELL[17].IMUX_IMUX_DELAY[36]	CELL[27].IMUX_IMUX_DELAY[36]	CELL[37].IMUX_IMUX_DELAY[36]
TXDATA[30]	in	CELL[7].IMUX_IMUX_DELAY[33]	CELL[17].IMUX_IMUX_DELAY[33]	CELL[27].IMUX_IMUX_DELAY[33]	CELL[37].IMUX_IMUX_DELAY[33]
TXDATA[31]	in	CELL[7].IMUX_IMUX_DELAY[32]	CELL[17].IMUX_IMUX_DELAY[32]	CELL[27].IMUX_IMUX_DELAY[32]	CELL[37].IMUX_IMUX_DELAY[32]
TXBYPASS8B10B[0]	in	CELL[5].IMUX_IMUX_DELAY[11]	CELL[15].IMUX_IMUX_DELAY[11]	CELL[25].IMUX_IMUX_DELAY[11]	CELL[35].IMUX_IMUX_DELAY[11]
TXBYPASS8B10B[1]	in	CELL[5].IMUX_IMUX_DELAY[27]	CELL[15].IMUX_IMUX_DELAY[27]	CELL[25].IMUX_IMUX_DELAY[27]	CELL[35].IMUX_IMUX_DELAY[27]
TXBYPASS8B10B[2]	in	CELL[5].IMUX_IMUX_DELAY[35]	CELL[15].IMUX_IMUX_DELAY[35]	CELL[25].IMUX_IMUX_DELAY[35]	CELL[35].IMUX_IMUX_DELAY[35]
TXBYPASS8B10B[3]	in	CELL[5].IMUX_IMUX_DELAY[19]	CELL[15].IMUX_IMUX_DELAY[19]	CELL[25].IMUX_IMUX_DELAY[19]	CELL[35].IMUX_IMUX_DELAY[19]
TXCHARDISPMODE[0]	in	CELL[5].IMUX_IMUX_DELAY[34]	CELL[15].IMUX_IMUX_DELAY[34]	CELL[25].IMUX_IMUX_DELAY[34]	CELL[35].IMUX_IMUX_DELAY[34]
TXCHARDISPMODE[1]	in	CELL[5].IMUX_IMUX_DELAY[28]	CELL[15].IMUX_IMUX_DELAY[28]	CELL[25].IMUX_IMUX_DELAY[28]	CELL[35].IMUX_IMUX_DELAY[28]
TXCHARDISPMODE[2]	in	CELL[5].IMUX_IMUX_DELAY[37]	CELL[15].IMUX_IMUX_DELAY[37]	CELL[25].IMUX_IMUX_DELAY[37]	CELL[35].IMUX_IMUX_DELAY[37]
TXCHARDISPMODE[3]	in	CELL[5].IMUX_IMUX_DELAY[21]	CELL[15].IMUX_IMUX_DELAY[21]	CELL[25].IMUX_IMUX_DELAY[21]	CELL[35].IMUX_IMUX_DELAY[21]
TXCHARDISPVAL[0]	in	CELL[5].IMUX_IMUX_DELAY[44]	CELL[15].IMUX_IMUX_DELAY[44]	CELL[25].IMUX_IMUX_DELAY[44]	CELL[35].IMUX_IMUX_DELAY[44]
TXCHARDISPVAL[1]	in	CELL[5].IMUX_IMUX_DELAY[30]	CELL[15].IMUX_IMUX_DELAY[30]	CELL[25].IMUX_IMUX_DELAY[30]	CELL[35].IMUX_IMUX_DELAY[30]
TXCHARDISPVAL[2]	in	CELL[5].IMUX_IMUX_DELAY[38]	CELL[15].IMUX_IMUX_DELAY[38]	CELL[25].IMUX_IMUX_DELAY[38]	CELL[35].IMUX_IMUX_DELAY[38]
TXCHARDISPVAL[3]	in	CELL[5].IMUX_IMUX_DELAY[22]	CELL[15].IMUX_IMUX_DELAY[22]	CELL[25].IMUX_IMUX_DELAY[22]	CELL[35].IMUX_IMUX_DELAY[22]
TXCHARISK[0]	in	CELL[5].IMUX_IMUX_DELAY[26]	CELL[15].IMUX_IMUX_DELAY[26]	CELL[25].IMUX_IMUX_DELAY[26]	CELL[35].IMUX_IMUX_DELAY[26]
TXCHARISK[1]	in	CELL[5].IMUX_IMUX_DELAY[36]	CELL[15].IMUX_IMUX_DELAY[36]	CELL[25].IMUX_IMUX_DELAY[36]	CELL[35].IMUX_IMUX_DELAY[36]
TXCHARISK[2]	in	CELL[5].IMUX_IMUX_DELAY[39]	CELL[15].IMUX_IMUX_DELAY[39]	CELL[25].IMUX_IMUX_DELAY[39]	CELL[35].IMUX_IMUX_DELAY[39]
TXCHARISK[3]	in	CELL[5].IMUX_IMUX_DELAY[23]	CELL[15].IMUX_IMUX_DELAY[23]	CELL[25].IMUX_IMUX_DELAY[23]	CELL[35].IMUX_IMUX_DELAY[23]
TXENC8B10BUSE	in	CELL[7].IMUX_IMUX_DELAY[22]	CELL[17].IMUX_IMUX_DELAY[22]	CELL[27].IMUX_IMUX_DELAY[22]	CELL[37].IMUX_IMUX_DELAY[22]
TXHEADER[0]	in	CELL[5].IMUX_IMUX_DELAY[8]	CELL[15].IMUX_IMUX_DELAY[8]	CELL[25].IMUX_IMUX_DELAY[8]	CELL[35].IMUX_IMUX_DELAY[8]
TXHEADER[1]	in	CELL[5].IMUX_IMUX_DELAY[16]	CELL[15].IMUX_IMUX_DELAY[16]	CELL[25].IMUX_IMUX_DELAY[16]	CELL[35].IMUX_IMUX_DELAY[16]
TXHEADER[2]	in	CELL[5].IMUX_IMUX_DELAY[32]	CELL[15].IMUX_IMUX_DELAY[32]	CELL[25].IMUX_IMUX_DELAY[32]	CELL[35].IMUX_IMUX_DELAY[32]
TXSEQUENCE[0]	in	CELL[6].IMUX_IMUX_DELAY[11]	CELL[16].IMUX_IMUX_DELAY[11]	CELL[26].IMUX_IMUX_DELAY[11]	CELL[36].IMUX_IMUX_DELAY[11]
TXSEQUENCE[1]	in	CELL[6].IMUX_IMUX_DELAY[19]	CELL[16].IMUX_IMUX_DELAY[19]	CELL[26].IMUX_IMUX_DELAY[19]	CELL[36].IMUX_IMUX_DELAY[19]
TXSEQUENCE[2]	in	CELL[6].IMUX_IMUX_DELAY[35]	CELL[16].IMUX_IMUX_DELAY[35]	CELL[26].IMUX_IMUX_DELAY[35]	CELL[36].IMUX_IMUX_DELAY[35]
TXSEQUENCE[3]	in	CELL[6].IMUX_IMUX_DELAY[8]	CELL[16].IMUX_IMUX_DELAY[8]	CELL[26].IMUX_IMUX_DELAY[8]	CELL[36].IMUX_IMUX_DELAY[8]
TXSEQUENCE[4]	in	CELL[6].IMUX_IMUX_DELAY[24]	CELL[16].IMUX_IMUX_DELAY[24]	CELL[26].IMUX_IMUX_DELAY[24]	CELL[36].IMUX_IMUX_DELAY[24]
TXSEQUENCE[5]	in	CELL[6].IMUX_IMUX_DELAY[22]	CELL[16].IMUX_IMUX_DELAY[22]	CELL[26].IMUX_IMUX_DELAY[22]	CELL[36].IMUX_IMUX_DELAY[22]
TXSEQUENCE[6]	in	CELL[6].IMUX_IMUX_DELAY[38]	CELL[16].IMUX_IMUX_DELAY[38]	CELL[26].IMUX_IMUX_DELAY[38]	CELL[36].IMUX_IMUX_DELAY[38]
TXSTARTSEQ	in	CELL[7].IMUX_IMUX_DELAY[14]	CELL[17].IMUX_IMUX_DELAY[14]	CELL[27].IMUX_IMUX_DELAY[14]	CELL[37].IMUX_IMUX_DELAY[14]
TXDLYALIGNDISABLE	in	CELL[5].IMUX_IMUX_DELAY[46]	CELL[15].IMUX_IMUX_DELAY[46]	CELL[25].IMUX_IMUX_DELAY[46]	CELL[35].IMUX_IMUX_DELAY[46]
TXDLYALIGNMONENB	in	CELL[7].IMUX_IMUX_DELAY[11]	CELL[17].IMUX_IMUX_DELAY[11]	CELL[27].IMUX_IMUX_DELAY[11]	CELL[37].IMUX_IMUX_DELAY[11]
TXDLYALIGNOVERRIDE	in	CELL[5].IMUX_IMUX_DELAY[25]	CELL[15].IMUX_IMUX_DELAY[25]	CELL[25].IMUX_IMUX_DELAY[25]	CELL[35].IMUX_IMUX_DELAY[25]
TXDLYALIGNRESET	in	CELL[5].IMUX_IMUX_DELAY[13]	CELL[15].IMUX_IMUX_DELAY[13]	CELL[25].IMUX_IMUX_DELAY[13]	CELL[35].IMUX_IMUX_DELAY[13]
TXDLYALIGNUPDSW	in	CELL[5].IMUX_IMUX_DELAY[2]	CELL[15].IMUX_IMUX_DELAY[2]	CELL[25].IMUX_IMUX_DELAY[2]	CELL[35].IMUX_IMUX_DELAY[2]
TXDLYALIGNFORCEROTATEB	in	CELL[7].IMUX_IMUX_DELAY[9]	CELL[17].IMUX_IMUX_DELAY[9]	CELL[27].IMUX_IMUX_DELAY[9]	CELL[37].IMUX_IMUX_DELAY[9]
TXDLYALIGNTESTMODEENB	in	CELL[7].IMUX_IMUX_DELAY[30]	CELL[17].IMUX_IMUX_DELAY[30]	CELL[27].IMUX_IMUX_DELAY[30]	CELL[37].IMUX_IMUX_DELAY[30]
TXENPMAPHASEALIGN	in	CELL[8].IMUX_IMUX_DELAY[17]	CELL[18].IMUX_IMUX_DELAY[17]	CELL[28].IMUX_IMUX_DELAY[17]	CELL[38].IMUX_IMUX_DELAY[17]
TXPMASETPHASE	in	CELL[5].IMUX_IMUX_DELAY[18]	CELL[15].IMUX_IMUX_DELAY[18]	CELL[25].IMUX_IMUX_DELAY[18]	CELL[35].IMUX_IMUX_DELAY[18]
TXENPRBSTST[0]	in	CELL[6].IMUX_IMUX_DELAY[39]	CELL[16].IMUX_IMUX_DELAY[39]	CELL[26].IMUX_IMUX_DELAY[39]	CELL[36].IMUX_IMUX_DELAY[39]
TXENPRBSTST[1]	in	CELL[6].IMUX_IMUX_DELAY[23]	CELL[16].IMUX_IMUX_DELAY[23]	CELL[26].IMUX_IMUX_DELAY[23]	CELL[36].IMUX_IMUX_DELAY[23]
TXENPRBSTST[2]	in	CELL[6].IMUX_IMUX_DELAY[15]	CELL[16].IMUX_IMUX_DELAY[15]	CELL[26].IMUX_IMUX_DELAY[15]	CELL[36].IMUX_IMUX_DELAY[15]
TXPRBSFORCEERR	in	CELL[8].IMUX_IMUX_DELAY[13]	CELL[18].IMUX_IMUX_DELAY[13]	CELL[28].IMUX_IMUX_DELAY[13]	CELL[38].IMUX_IMUX_DELAY[13]
TXPOLARITY	in	CELL[5].IMUX_IMUX_DELAY[9]	CELL[15].IMUX_IMUX_DELAY[9]	CELL[25].IMUX_IMUX_DELAY[9]	CELL[35].IMUX_IMUX_DELAY[9]
TXRATE[0]	in	CELL[6].IMUX_IMUX_DELAY[34]	CELL[16].IMUX_IMUX_DELAY[34]	CELL[26].IMUX_IMUX_DELAY[34]	CELL[36].IMUX_IMUX_DELAY[34]
TXRATE[1]	in	CELL[6].IMUX_IMUX_DELAY[33]	CELL[16].IMUX_IMUX_DELAY[33]	CELL[26].IMUX_IMUX_DELAY[33]	CELL[36].IMUX_IMUX_DELAY[33]
TXBUFDIFFCTRL[0]	in	CELL[3].IMUX_IMUX_DELAY[0]	CELL[13].IMUX_IMUX_DELAY[0]	CELL[23].IMUX_IMUX_DELAY[0]	CELL[33].IMUX_IMUX_DELAY[0]
TXBUFDIFFCTRL[1]	in	CELL[3].IMUX_IMUX_DELAY[16]	CELL[13].IMUX_IMUX_DELAY[16]	CELL[23].IMUX_IMUX_DELAY[16]	CELL[33].IMUX_IMUX_DELAY[16]
TXBUFDIFFCTRL[2]	in	CELL[3].IMUX_IMUX_DELAY[18]	CELL[13].IMUX_IMUX_DELAY[18]	CELL[23].IMUX_IMUX_DELAY[18]	CELL[33].IMUX_IMUX_DELAY[18]
TXDEEMPH	in	CELL[3].IMUX_IMUX_DELAY[3]	CELL[13].IMUX_IMUX_DELAY[3]	CELL[23].IMUX_IMUX_DELAY[3]	CELL[33].IMUX_IMUX_DELAY[3]
TXDIFFCTRL[0]	in	CELL[3].IMUX_IMUX_DELAY[21]	CELL[13].IMUX_IMUX_DELAY[21]	CELL[23].IMUX_IMUX_DELAY[21]	CELL[33].IMUX_IMUX_DELAY[21]
TXDIFFCTRL[1]	in	CELL[3].IMUX_IMUX_DELAY[38]	CELL[13].IMUX_IMUX_DELAY[38]	CELL[23].IMUX_IMUX_DELAY[38]	CELL[33].IMUX_IMUX_DELAY[38]
TXDIFFCTRL[2]	in	CELL[3].IMUX_IMUX_DELAY[5]	CELL[13].IMUX_IMUX_DELAY[5]	CELL[23].IMUX_IMUX_DELAY[5]	CELL[33].IMUX_IMUX_DELAY[5]
TXDIFFCTRL[3]	in	CELL[3].IMUX_IMUX_DELAY[30]	CELL[13].IMUX_IMUX_DELAY[30]	CELL[23].IMUX_IMUX_DELAY[30]	CELL[33].IMUX_IMUX_DELAY[30]
TXELECIDLE	in	CELL[4].IMUX_IMUX_DELAY[32]	CELL[14].IMUX_IMUX_DELAY[32]	CELL[24].IMUX_IMUX_DELAY[32]	CELL[34].IMUX_IMUX_DELAY[32]
TXINHIBIT	in	CELL[5].IMUX_IMUX_DELAY[17]	CELL[15].IMUX_IMUX_DELAY[17]	CELL[25].IMUX_IMUX_DELAY[17]	CELL[35].IMUX_IMUX_DELAY[17]
TXMARGIN[0]	in	CELL[4].IMUX_IMUX_DELAY[11]	CELL[14].IMUX_IMUX_DELAY[11]	CELL[24].IMUX_IMUX_DELAY[11]	CELL[34].IMUX_IMUX_DELAY[11]
TXMARGIN[1]	in	CELL[4].IMUX_IMUX_DELAY[26]	CELL[14].IMUX_IMUX_DELAY[26]	CELL[24].IMUX_IMUX_DELAY[26]	CELL[34].IMUX_IMUX_DELAY[26]
TXMARGIN[2]	in	CELL[5].IMUX_IMUX_DELAY[15]	CELL[15].IMUX_IMUX_DELAY[15]	CELL[25].IMUX_IMUX_DELAY[15]	CELL[35].IMUX_IMUX_DELAY[15]
TXPDOWNASYNCH	in	CELL[8].IMUX_IMUX_DELAY[15]	CELL[18].IMUX_IMUX_DELAY[15]	CELL[28].IMUX_IMUX_DELAY[15]	CELL[38].IMUX_IMUX_DELAY[15]
TXPOSTEMPHASIS[0]	in	CELL[8].IMUX_IMUX_DELAY[10]	CELL[18].IMUX_IMUX_DELAY[10]	CELL[28].IMUX_IMUX_DELAY[10]	CELL[38].IMUX_IMUX_DELAY[10]
TXPOSTEMPHASIS[1]	in	CELL[8].IMUX_IMUX_DELAY[18]	CELL[18].IMUX_IMUX_DELAY[18]	CELL[28].IMUX_IMUX_DELAY[18]	CELL[38].IMUX_IMUX_DELAY[18]
TXPOSTEMPHASIS[2]	in	CELL[8].IMUX_IMUX_DELAY[12]	CELL[18].IMUX_IMUX_DELAY[12]	CELL[28].IMUX_IMUX_DELAY[12]	CELL[38].IMUX_IMUX_DELAY[12]
TXPOSTEMPHASIS[3]	in	CELL[8].IMUX_IMUX_DELAY[20]	CELL[18].IMUX_IMUX_DELAY[20]	CELL[28].IMUX_IMUX_DELAY[20]	CELL[38].IMUX_IMUX_DELAY[20]
TXPOSTEMPHASIS[4]	in	CELL[8].IMUX_IMUX_DELAY[22]	CELL[18].IMUX_IMUX_DELAY[22]	CELL[28].IMUX_IMUX_DELAY[22]	CELL[38].IMUX_IMUX_DELAY[22]
TXPREEMPHASIS[0]	in	CELL[3].IMUX_IMUX_DELAY[26]	CELL[13].IMUX_IMUX_DELAY[26]	CELL[23].IMUX_IMUX_DELAY[26]	CELL[33].IMUX_IMUX_DELAY[26]
TXPREEMPHASIS[1]	in	CELL[3].IMUX_IMUX_DELAY[19]	CELL[13].IMUX_IMUX_DELAY[19]	CELL[23].IMUX_IMUX_DELAY[19]	CELL[33].IMUX_IMUX_DELAY[19]
TXPREEMPHASIS[2]	in	CELL[3].IMUX_IMUX_DELAY[17]	CELL[13].IMUX_IMUX_DELAY[17]	CELL[23].IMUX_IMUX_DELAY[17]	CELL[33].IMUX_IMUX_DELAY[17]
TXPREEMPHASIS[3]	in	CELL[3].IMUX_IMUX_DELAY[9]	CELL[13].IMUX_IMUX_DELAY[9]	CELL[23].IMUX_IMUX_DELAY[9]	CELL[33].IMUX_IMUX_DELAY[9]
TXSWING	in	CELL[3].IMUX_IMUX_DELAY[13]	CELL[13].IMUX_IMUX_DELAY[13]	CELL[23].IMUX_IMUX_DELAY[13]	CELL[33].IMUX_IMUX_DELAY[13]
TXCOMINIT	in	CELL[7].IMUX_IMUX_DELAY[18]	CELL[17].IMUX_IMUX_DELAY[18]	CELL[27].IMUX_IMUX_DELAY[18]	CELL[37].IMUX_IMUX_DELAY[18]
TXCOMSAS	in	CELL[7].IMUX_IMUX_DELAY[19]	CELL[17].IMUX_IMUX_DELAY[19]	CELL[27].IMUX_IMUX_DELAY[19]	CELL[37].IMUX_IMUX_DELAY[19]
TXCOMWAKE	in	CELL[7].IMUX_IMUX_DELAY[10]	CELL[17].IMUX_IMUX_DELAY[10]	CELL[27].IMUX_IMUX_DELAY[10]	CELL[37].IMUX_IMUX_DELAY[10]
TXPOWERDOWN[0]	in	CELL[4].IMUX_IMUX_DELAY[28]	CELL[14].IMUX_IMUX_DELAY[28]	CELL[24].IMUX_IMUX_DELAY[28]	CELL[34].IMUX_IMUX_DELAY[28]
TXPOWERDOWN[1]	in	CELL[4].IMUX_IMUX_DELAY[36]	CELL[14].IMUX_IMUX_DELAY[36]	CELL[24].IMUX_IMUX_DELAY[36]	CELL[34].IMUX_IMUX_DELAY[36]
TXDETECTRX	in	CELL[4].IMUX_IMUX_DELAY[9]	CELL[14].IMUX_IMUX_DELAY[9]	CELL[24].IMUX_IMUX_DELAY[9]	CELL[34].IMUX_IMUX_DELAY[9]
TSTCLK[0]	in	CELL[3].IMUX_CLK[1] invert by !MAIN[8][28][29]	CELL[13].IMUX_CLK[1] invert by !MAIN[18][28][29]	CELL[23].IMUX_CLK[1] invert by !MAIN[28][28][29]	CELL[33].IMUX_CLK[1] invert by !MAIN[38][28][29]
TSTCLK[1]	in	CELL[5].IMUX_CLK[1] invert by !MAIN[8][29][29]	CELL[15].IMUX_CLK[1] invert by !MAIN[18][29][29]	CELL[25].IMUX_CLK[1] invert by !MAIN[28][29][29]	CELL[35].IMUX_CLK[1] invert by !MAIN[38][29][29]
TSTIN[0]	in	CELL[0].IMUX_IMUX_DELAY[30]	CELL[10].IMUX_IMUX_DELAY[30]	CELL[20].IMUX_IMUX_DELAY[30]	CELL[30].IMUX_IMUX_DELAY[30]
TSTIN[1]	in	CELL[0].IMUX_IMUX_DELAY[14]	CELL[10].IMUX_IMUX_DELAY[14]	CELL[20].IMUX_IMUX_DELAY[14]	CELL[30].IMUX_IMUX_DELAY[14]
TSTIN[2]	in	CELL[0].IMUX_IMUX_DELAY[27]	CELL[10].IMUX_IMUX_DELAY[27]	CELL[20].IMUX_IMUX_DELAY[27]	CELL[30].IMUX_IMUX_DELAY[27]
TSTIN[3]	in	CELL[0].IMUX_IMUX_DELAY[11]	CELL[10].IMUX_IMUX_DELAY[11]	CELL[20].IMUX_IMUX_DELAY[11]	CELL[30].IMUX_IMUX_DELAY[11]
TSTIN[4]	in	CELL[0].IMUX_IMUX_DELAY[26]	CELL[10].IMUX_IMUX_DELAY[26]	CELL[20].IMUX_IMUX_DELAY[26]	CELL[30].IMUX_IMUX_DELAY[26]
TSTIN[5]	in	CELL[0].IMUX_IMUX_DELAY[10]	CELL[10].IMUX_IMUX_DELAY[10]	CELL[20].IMUX_IMUX_DELAY[10]	CELL[30].IMUX_IMUX_DELAY[10]
TSTIN[6]	in	CELL[0].IMUX_IMUX_DELAY[25]	CELL[10].IMUX_IMUX_DELAY[25]	CELL[20].IMUX_IMUX_DELAY[25]	CELL[30].IMUX_IMUX_DELAY[25]
TSTIN[7]	in	CELL[0].IMUX_IMUX_DELAY[9]	CELL[10].IMUX_IMUX_DELAY[9]	CELL[20].IMUX_IMUX_DELAY[9]	CELL[30].IMUX_IMUX_DELAY[9]
TSTIN[8]	in	CELL[0].IMUX_IMUX_DELAY[24]	CELL[10].IMUX_IMUX_DELAY[24]	CELL[20].IMUX_IMUX_DELAY[24]	CELL[30].IMUX_IMUX_DELAY[24]
TSTIN[9]	in	CELL[0].IMUX_IMUX_DELAY[8]	CELL[10].IMUX_IMUX_DELAY[8]	CELL[20].IMUX_IMUX_DELAY[8]	CELL[30].IMUX_IMUX_DELAY[8]
TSTIN[10]	in	CELL[0].IMUX_IMUX_DELAY[31]	CELL[10].IMUX_IMUX_DELAY[31]	CELL[20].IMUX_IMUX_DELAY[31]	CELL[30].IMUX_IMUX_DELAY[31]
TSTIN[11]	in	CELL[0].IMUX_IMUX_DELAY[21]	CELL[10].IMUX_IMUX_DELAY[21]	CELL[20].IMUX_IMUX_DELAY[21]	CELL[30].IMUX_IMUX_DELAY[21]
TSTIN[12]	in	CELL[0].IMUX_IMUX_DELAY[13]	CELL[10].IMUX_IMUX_DELAY[13]	CELL[20].IMUX_IMUX_DELAY[13]	CELL[30].IMUX_IMUX_DELAY[13]
TSTIN[13]	in	CELL[0].IMUX_IMUX_DELAY[28]	CELL[10].IMUX_IMUX_DELAY[28]	CELL[20].IMUX_IMUX_DELAY[28]	CELL[30].IMUX_IMUX_DELAY[28]
TSTIN[14]	in	CELL[0].IMUX_IMUX_DELAY[32]	CELL[10].IMUX_IMUX_DELAY[32]	CELL[20].IMUX_IMUX_DELAY[32]	CELL[30].IMUX_IMUX_DELAY[32]
TSTIN[15]	in	CELL[0].IMUX_IMUX_DELAY[16]	CELL[10].IMUX_IMUX_DELAY[16]	CELL[20].IMUX_IMUX_DELAY[16]	CELL[30].IMUX_IMUX_DELAY[16]
TSTIN[16]	in	CELL[0].IMUX_IMUX_DELAY[40]	CELL[10].IMUX_IMUX_DELAY[40]	CELL[20].IMUX_IMUX_DELAY[40]	CELL[30].IMUX_IMUX_DELAY[40]
TSTIN[17]	in	CELL[0].IMUX_IMUX_DELAY[0]	CELL[10].IMUX_IMUX_DELAY[0]	CELL[20].IMUX_IMUX_DELAY[0]	CELL[30].IMUX_IMUX_DELAY[0]
TSTIN[18]	in	CELL[0].IMUX_IMUX_DELAY[1]	CELL[10].IMUX_IMUX_DELAY[1]	CELL[20].IMUX_IMUX_DELAY[1]	CELL[30].IMUX_IMUX_DELAY[1]
TSTIN[19]	in	CELL[0].IMUX_IMUX_DELAY[41]	CELL[10].IMUX_IMUX_DELAY[41]	CELL[20].IMUX_IMUX_DELAY[41]	CELL[30].IMUX_IMUX_DELAY[41]
TSTPWRDN[0]	in	CELL[0].IMUX_IMUX_DELAY[33]	CELL[10].IMUX_IMUX_DELAY[33]	CELL[20].IMUX_IMUX_DELAY[33]	CELL[30].IMUX_IMUX_DELAY[33]
TSTPWRDN[1]	in	CELL[0].IMUX_IMUX_DELAY[18]	CELL[10].IMUX_IMUX_DELAY[18]	CELL[20].IMUX_IMUX_DELAY[18]	CELL[30].IMUX_IMUX_DELAY[18]
TSTPWRDN[2]	in	CELL[0].IMUX_IMUX_DELAY[34]	CELL[10].IMUX_IMUX_DELAY[34]	CELL[20].IMUX_IMUX_DELAY[34]	CELL[30].IMUX_IMUX_DELAY[34]
TSTPWRDN[3]	in	CELL[0].IMUX_IMUX_DELAY[19]	CELL[10].IMUX_IMUX_DELAY[19]	CELL[20].IMUX_IMUX_DELAY[19]	CELL[30].IMUX_IMUX_DELAY[19]
TSTPWRDN[4]	in	CELL[0].IMUX_IMUX_DELAY[35]	CELL[10].IMUX_IMUX_DELAY[35]	CELL[20].IMUX_IMUX_DELAY[35]	CELL[30].IMUX_IMUX_DELAY[35]
TSTPWRDNOVRD	in	CELL[0].IMUX_IMUX_DELAY[17]	CELL[10].IMUX_IMUX_DELAY[17]	CELL[20].IMUX_IMUX_DELAY[17]	CELL[30].IMUX_IMUX_DELAY[17]
SCANCLK	in	CELL[4].IMUX_CLK[1] invert by !MAIN[8][29][30]	CELL[14].IMUX_CLK[1] invert by !MAIN[18][29][30]	CELL[24].IMUX_CLK[1] invert by !MAIN[28][29][30]	CELL[34].IMUX_CLK[1] invert by !MAIN[38][29][30]
SCANENB	in	CELL[0].IMUX_IMUX_DELAY[37]	CELL[10].IMUX_IMUX_DELAY[37]	CELL[20].IMUX_IMUX_DELAY[37]	CELL[30].IMUX_IMUX_DELAY[37]
SCANIN[0]	in	CELL[8].IMUX_IMUX_DELAY[33]	CELL[18].IMUX_IMUX_DELAY[33]	CELL[28].IMUX_IMUX_DELAY[33]	CELL[38].IMUX_IMUX_DELAY[33]
SCANIN[1]	in	CELL[8].IMUX_IMUX_DELAY[25]	CELL[18].IMUX_IMUX_DELAY[25]	CELL[28].IMUX_IMUX_DELAY[25]	CELL[38].IMUX_IMUX_DELAY[25]
SCANIN[2]	in	CELL[0].IMUX_IMUX_DELAY[38]	CELL[10].IMUX_IMUX_DELAY[38]	CELL[20].IMUX_IMUX_DELAY[38]	CELL[30].IMUX_IMUX_DELAY[38]
SCANIN[3]	in	CELL[0].IMUX_IMUX_DELAY[22]	CELL[10].IMUX_IMUX_DELAY[22]	CELL[20].IMUX_IMUX_DELAY[22]	CELL[30].IMUX_IMUX_DELAY[22]
SCANIN[4]	in	CELL[8].IMUX_IMUX_DELAY[9]	CELL[18].IMUX_IMUX_DELAY[9]	CELL[28].IMUX_IMUX_DELAY[9]	CELL[38].IMUX_IMUX_DELAY[9]
SCANMODEB	in	CELL[0].IMUX_IMUX_DELAY[29]	CELL[10].IMUX_IMUX_DELAY[29]	CELL[20].IMUX_IMUX_DELAY[29]	CELL[30].IMUX_IMUX_DELAY[29]
DRDY	out	CELL[8].OUT_BEL[0]	CELL[18].OUT_BEL[0]	CELL[28].OUT_BEL[0]	CELL[38].OUT_BEL[0]
DRPDO[0]	out	CELL[9].OUT_BEL[3]	CELL[19].OUT_BEL[3]	CELL[29].OUT_BEL[3]	CELL[39].OUT_BEL[3]
DRPDO[1]	out	CELL[9].OUT_BEL[7]	CELL[19].OUT_BEL[7]	CELL[29].OUT_BEL[7]	CELL[39].OUT_BEL[7]
DRPDO[2]	out	CELL[9].OUT_BEL[6]	CELL[19].OUT_BEL[6]	CELL[29].OUT_BEL[6]	CELL[39].OUT_BEL[6]
DRPDO[3]	out	CELL[9].OUT_BEL[2]	CELL[19].OUT_BEL[2]	CELL[29].OUT_BEL[2]	CELL[39].OUT_BEL[2]
DRPDO[4]	out	CELL[9].OUT_BEL[1]	CELL[19].OUT_BEL[1]	CELL[29].OUT_BEL[1]	CELL[39].OUT_BEL[1]
DRPDO[5]	out	CELL[9].OUT_BEL[5]	CELL[19].OUT_BEL[5]	CELL[29].OUT_BEL[5]	CELL[39].OUT_BEL[5]
DRPDO[6]	out	CELL[9].OUT_BEL[4]	CELL[19].OUT_BEL[4]	CELL[29].OUT_BEL[4]	CELL[39].OUT_BEL[4]
DRPDO[7]	out	CELL[9].OUT_BEL[0]	CELL[19].OUT_BEL[0]	CELL[29].OUT_BEL[0]	CELL[39].OUT_BEL[0]
DRPDO[8]	out	CELL[9].OUT_BEL[15]	CELL[19].OUT_BEL[15]	CELL[29].OUT_BEL[15]	CELL[39].OUT_BEL[15]
DRPDO[9]	out	CELL[9].OUT_BEL[11]	CELL[19].OUT_BEL[11]	CELL[29].OUT_BEL[11]	CELL[39].OUT_BEL[11]
DRPDO[10]	out	CELL[9].OUT_BEL[10]	CELL[19].OUT_BEL[10]	CELL[29].OUT_BEL[10]	CELL[39].OUT_BEL[10]
DRPDO[11]	out	CELL[9].OUT_BEL[14]	CELL[19].OUT_BEL[14]	CELL[29].OUT_BEL[14]	CELL[39].OUT_BEL[14]
DRPDO[12]	out	CELL[9].OUT_BEL[13]	CELL[19].OUT_BEL[13]	CELL[29].OUT_BEL[13]	CELL[39].OUT_BEL[13]
DRPDO[13]	out	CELL[9].OUT_BEL[9]	CELL[19].OUT_BEL[9]	CELL[29].OUT_BEL[9]	CELL[39].OUT_BEL[9]
DRPDO[14]	out	CELL[9].OUT_BEL[8]	CELL[19].OUT_BEL[8]	CELL[29].OUT_BEL[8]	CELL[39].OUT_BEL[8]
DRPDO[15]	out	CELL[9].OUT_BEL[12]	CELL[19].OUT_BEL[12]	CELL[29].OUT_BEL[12]	CELL[39].OUT_BEL[12]
RXPLLLKDET	out	CELL[4].OUT_BEL[5]	CELL[14].OUT_BEL[5]	CELL[24].OUT_BEL[5]	CELL[34].OUT_BEL[5]
TXPLLLKDET	out	CELL[8].OUT_BEL[5]	CELL[18].OUT_BEL[5]	CELL[28].OUT_BEL[5]	CELL[38].OUT_BEL[5]
MGTREFCLKFAB[0]	out	CELL[4].OUT_BEL[0]	CELL[14].OUT_BEL[0]	CELL[24].OUT_BEL[0]	CELL[34].OUT_BEL[0]
MGTREFCLKFAB[1]	out	CELL[4].OUT_BEL[12]	CELL[14].OUT_BEL[12]	CELL[24].OUT_BEL[12]	CELL[34].OUT_BEL[12]
PHYSTATUS	out	CELL[4].OUT_BEL[8]	CELL[14].OUT_BEL[8]	CELL[24].OUT_BEL[8]	CELL[34].OUT_BEL[8]
RXRESETDONE	out	CELL[5].OUT_BEL[22]	CELL[15].OUT_BEL[22]	CELL[25].OUT_BEL[22]	CELL[35].OUT_BEL[22]
RXRECCLK	out	CELL[20].MGT_ROW[0]	CELL[20].MGT_ROW[1]	CELL[20].MGT_ROW[6]	CELL[20].MGT_ROW[7]
RXRECCLKPCS	out	CELL[5].OUT_BEL[5]	CELL[15].OUT_BEL[5]	CELL[25].OUT_BEL[5]	CELL[35].OUT_BEL[5]
COMINITDET	out	CELL[2].OUT_BEL[20]	CELL[12].OUT_BEL[20]	CELL[22].OUT_BEL[20]	CELL[32].OUT_BEL[20]
COMSASDET	out	CELL[2].OUT_BEL[19]	CELL[12].OUT_BEL[19]	CELL[22].OUT_BEL[19]	CELL[32].OUT_BEL[19]
COMWAKEDET	out	CELL[2].OUT_BEL[23]	CELL[12].OUT_BEL[23]	CELL[22].OUT_BEL[23]	CELL[32].OUT_BEL[23]
RXELECIDLE	out	CELL[5].OUT_BEL[3]	CELL[15].OUT_BEL[3]	CELL[25].OUT_BEL[3]	CELL[35].OUT_BEL[3]
RXSTATUS[0]	out	CELL[4].OUT_BEL[14]	CELL[14].OUT_BEL[14]	CELL[24].OUT_BEL[14]	CELL[34].OUT_BEL[14]
RXSTATUS[1]	out	CELL[4].OUT_BEL[16]	CELL[14].OUT_BEL[16]	CELL[24].OUT_BEL[16]	CELL[34].OUT_BEL[16]
RXSTATUS[2]	out	CELL[4].OUT_BEL[13]	CELL[14].OUT_BEL[13]	CELL[24].OUT_BEL[13]	CELL[34].OUT_BEL[13]
RXVALID	out	CELL[5].OUT_BEL[4]	CELL[15].OUT_BEL[4]	CELL[25].OUT_BEL[4]	CELL[35].OUT_BEL[4]
DFECLKDLYADJMON[0]	out	CELL[6].OUT_BEL[5]	CELL[16].OUT_BEL[5]	CELL[26].OUT_BEL[5]	CELL[36].OUT_BEL[5]
DFECLKDLYADJMON[1]	out	CELL[6].OUT_BEL[1]	CELL[16].OUT_BEL[1]	CELL[26].OUT_BEL[1]	CELL[36].OUT_BEL[1]
DFECLKDLYADJMON[2]	out	CELL[6].OUT_BEL[2]	CELL[16].OUT_BEL[2]	CELL[26].OUT_BEL[2]	CELL[36].OUT_BEL[2]
DFECLKDLYADJMON[3]	out	CELL[6].OUT_BEL[6]	CELL[16].OUT_BEL[6]	CELL[26].OUT_BEL[6]	CELL[36].OUT_BEL[6]
DFECLKDLYADJMON[4]	out	CELL[6].OUT_BEL[7]	CELL[16].OUT_BEL[7]	CELL[26].OUT_BEL[7]	CELL[36].OUT_BEL[7]
DFECLKDLYADJMON[5]	out	CELL[6].OUT_BEL[3]	CELL[16].OUT_BEL[3]	CELL[26].OUT_BEL[3]	CELL[36].OUT_BEL[3]
DFEEYEDACMON[0]	out	CELL[6].OUT_BEL[13]	CELL[16].OUT_BEL[13]	CELL[26].OUT_BEL[13]	CELL[36].OUT_BEL[13]
DFEEYEDACMON[1]	out	CELL[6].OUT_BEL[14]	CELL[16].OUT_BEL[14]	CELL[26].OUT_BEL[14]	CELL[36].OUT_BEL[14]
DFEEYEDACMON[2]	out	CELL[6].OUT_BEL[10]	CELL[16].OUT_BEL[10]	CELL[26].OUT_BEL[10]	CELL[36].OUT_BEL[10]
DFEEYEDACMON[3]	out	CELL[6].OUT_BEL[11]	CELL[16].OUT_BEL[11]	CELL[26].OUT_BEL[11]	CELL[36].OUT_BEL[11]
DFEEYEDACMON[4]	out	CELL[6].OUT_BEL[15]	CELL[16].OUT_BEL[15]	CELL[26].OUT_BEL[15]	CELL[36].OUT_BEL[15]
DFESENSCAL[0]	out	CELL[6].OUT_BEL[19]	CELL[16].OUT_BEL[19]	CELL[26].OUT_BEL[19]	CELL[36].OUT_BEL[19]
DFESENSCAL[1]	out	CELL[6].OUT_BEL[18]	CELL[16].OUT_BEL[18]	CELL[26].OUT_BEL[18]	CELL[36].OUT_BEL[18]
DFESENSCAL[2]	out	CELL[6].OUT_BEL[22]	CELL[16].OUT_BEL[22]	CELL[26].OUT_BEL[22]	CELL[36].OUT_BEL[22]
DFETAP1MONITOR[0]	out	CELL[8].OUT_BEL[1]	CELL[18].OUT_BEL[1]	CELL[28].OUT_BEL[1]	CELL[38].OUT_BEL[1]
DFETAP1MONITOR[1]	out	CELL[8].OUT_BEL[2]	CELL[18].OUT_BEL[2]	CELL[28].OUT_BEL[2]	CELL[38].OUT_BEL[2]
DFETAP1MONITOR[2]	out	CELL[8].OUT_BEL[6]	CELL[18].OUT_BEL[6]	CELL[28].OUT_BEL[6]	CELL[38].OUT_BEL[6]
DFETAP1MONITOR[3]	out	CELL[8].OUT_BEL[7]	CELL[18].OUT_BEL[7]	CELL[28].OUT_BEL[7]	CELL[38].OUT_BEL[7]
DFETAP1MONITOR[4]	out	CELL[8].OUT_BEL[3]	CELL[18].OUT_BEL[3]	CELL[28].OUT_BEL[3]	CELL[38].OUT_BEL[3]
DFETAP2MONITOR[0]	out	CELL[7].OUT_BEL[1]	CELL[17].OUT_BEL[1]	CELL[27].OUT_BEL[1]	CELL[37].OUT_BEL[1]
DFETAP2MONITOR[1]	out	CELL[7].OUT_BEL[2]	CELL[17].OUT_BEL[2]	CELL[27].OUT_BEL[2]	CELL[37].OUT_BEL[2]
DFETAP2MONITOR[2]	out	CELL[7].OUT_BEL[6]	CELL[17].OUT_BEL[6]	CELL[27].OUT_BEL[6]	CELL[37].OUT_BEL[6]
DFETAP2MONITOR[3]	out	CELL[7].OUT_BEL[7]	CELL[17].OUT_BEL[7]	CELL[27].OUT_BEL[7]	CELL[37].OUT_BEL[7]
DFETAP2MONITOR[4]	out	CELL[7].OUT_BEL[3]	CELL[17].OUT_BEL[3]	CELL[27].OUT_BEL[3]	CELL[37].OUT_BEL[3]
DFETAP3MONITOR[0]	out	CELL[8].OUT_BEL[12]	CELL[18].OUT_BEL[12]	CELL[28].OUT_BEL[12]	CELL[38].OUT_BEL[12]
DFETAP3MONITOR[1]	out	CELL[8].OUT_BEL[8]	CELL[18].OUT_BEL[8]	CELL[28].OUT_BEL[8]	CELL[38].OUT_BEL[8]
DFETAP3MONITOR[2]	out	CELL[8].OUT_BEL[9]	CELL[18].OUT_BEL[9]	CELL[28].OUT_BEL[9]	CELL[38].OUT_BEL[9]
DFETAP3MONITOR[3]	out	CELL[8].OUT_BEL[13]	CELL[18].OUT_BEL[13]	CELL[28].OUT_BEL[13]	CELL[38].OUT_BEL[13]
DFETAP4MONITOR[0]	out	CELL[7].OUT_BEL[12]	CELL[17].OUT_BEL[12]	CELL[27].OUT_BEL[12]	CELL[37].OUT_BEL[12]
DFETAP4MONITOR[1]	out	CELL[7].OUT_BEL[8]	CELL[17].OUT_BEL[8]	CELL[27].OUT_BEL[8]	CELL[37].OUT_BEL[8]
DFETAP4MONITOR[2]	out	CELL[7].OUT_BEL[9]	CELL[17].OUT_BEL[9]	CELL[27].OUT_BEL[9]	CELL[37].OUT_BEL[9]
DFETAP4MONITOR[3]	out	CELL[7].OUT_BEL[13]	CELL[17].OUT_BEL[13]	CELL[27].OUT_BEL[13]	CELL[37].OUT_BEL[13]
RXRATEDONE	out	CELL[6].OUT_BEL[20]	CELL[16].OUT_BEL[20]	CELL[26].OUT_BEL[20]	CELL[36].OUT_BEL[20]
RXOVERSAMPLEERR	out	CELL[4].OUT_BEL[22]	CELL[14].OUT_BEL[22]	CELL[24].OUT_BEL[22]	CELL[34].OUT_BEL[22]
RXPRBSERR	out	CELL[5].OUT_BEL[2]	CELL[15].OUT_BEL[2]	CELL[25].OUT_BEL[2]	CELL[35].OUT_BEL[2]
RXBYTEISALIGNED	out	CELL[2].OUT_BEL[13]	CELL[12].OUT_BEL[13]	CELL[22].OUT_BEL[13]	CELL[32].OUT_BEL[13]
RXBYTEREALIGN	out	CELL[2].OUT_BEL[10]	CELL[12].OUT_BEL[10]	CELL[22].OUT_BEL[10]	CELL[32].OUT_BEL[10]
RXCOMMADET	out	CELL[5].OUT_BEL[12]	CELL[15].OUT_BEL[12]	CELL[25].OUT_BEL[12]	CELL[35].OUT_BEL[12]
RXLOSSOFSYNC[0]	out	CELL[2].OUT_BEL[0]	CELL[12].OUT_BEL[0]	CELL[22].OUT_BEL[0]	CELL[32].OUT_BEL[0]
RXLOSSOFSYNC[1]	out	CELL[2].OUT_BEL[22]	CELL[12].OUT_BEL[22]	CELL[22].OUT_BEL[22]	CELL[32].OUT_BEL[22]
RXCHARISCOMMA[0]	out	CELL[3].OUT_BEL[14]	CELL[13].OUT_BEL[14]	CELL[23].OUT_BEL[14]	CELL[33].OUT_BEL[14]
RXCHARISCOMMA[1]	out	CELL[3].OUT_BEL[2]	CELL[13].OUT_BEL[2]	CELL[23].OUT_BEL[2]	CELL[33].OUT_BEL[2]
RXCHARISCOMMA[2]	out	CELL[2].OUT_BEL[8]	CELL[12].OUT_BEL[8]	CELL[22].OUT_BEL[8]	CELL[32].OUT_BEL[8]
RXCHARISCOMMA[3]	out	CELL[2].OUT_BEL[18]	CELL[12].OUT_BEL[18]	CELL[22].OUT_BEL[18]	CELL[32].OUT_BEL[18]
RXCHARISK[0]	out	CELL[3].OUT_BEL[16]	CELL[13].OUT_BEL[16]	CELL[23].OUT_BEL[16]	CELL[33].OUT_BEL[16]
RXCHARISK[1]	out	CELL[2].OUT_BEL[5]	CELL[12].OUT_BEL[5]	CELL[22].OUT_BEL[5]	CELL[32].OUT_BEL[5]
RXCHARISK[2]	out	CELL[2].OUT_BEL[15]	CELL[12].OUT_BEL[15]	CELL[22].OUT_BEL[15]	CELL[32].OUT_BEL[15]
RXCHARISK[3]	out	CELL[2].OUT_BEL[3]	CELL[12].OUT_BEL[3]	CELL[22].OUT_BEL[3]	CELL[32].OUT_BEL[3]
RXDISPERR[0]	out	CELL[3].OUT_BEL[4]	CELL[13].OUT_BEL[4]	CELL[23].OUT_BEL[4]	CELL[33].OUT_BEL[4]
RXDISPERR[1]	out	CELL[3].OUT_BEL[8]	CELL[13].OUT_BEL[8]	CELL[23].OUT_BEL[8]	CELL[33].OUT_BEL[8]
RXDISPERR[2]	out	CELL[3].OUT_BEL[0]	CELL[13].OUT_BEL[0]	CELL[23].OUT_BEL[0]	CELL[33].OUT_BEL[0]
RXDISPERR[3]	out	CELL[3].OUT_BEL[22]	CELL[13].OUT_BEL[22]	CELL[23].OUT_BEL[22]	CELL[33].OUT_BEL[22]
RXNOTINTABLE[0]	out	CELL[3].OUT_BEL[11]	CELL[13].OUT_BEL[11]	CELL[23].OUT_BEL[11]	CELL[33].OUT_BEL[11]
RXNOTINTABLE[1]	out	CELL[3].OUT_BEL[7]	CELL[13].OUT_BEL[7]	CELL[23].OUT_BEL[7]	CELL[33].OUT_BEL[7]
RXNOTINTABLE[2]	out	CELL[3].OUT_BEL[15]	CELL[13].OUT_BEL[15]	CELL[23].OUT_BEL[15]	CELL[33].OUT_BEL[15]
RXNOTINTABLE[3]	out	CELL[3].OUT_BEL[3]	CELL[13].OUT_BEL[3]	CELL[23].OUT_BEL[3]	CELL[33].OUT_BEL[3]
RXRUNDISP[0]	out	CELL[3].OUT_BEL[9]	CELL[13].OUT_BEL[9]	CELL[23].OUT_BEL[9]	CELL[33].OUT_BEL[9]
RXRUNDISP[1]	out	CELL[3].OUT_BEL[5]	CELL[13].OUT_BEL[5]	CELL[23].OUT_BEL[5]	CELL[33].OUT_BEL[5]
RXRUNDISP[2]	out	CELL[3].OUT_BEL[19]	CELL[13].OUT_BEL[19]	CELL[23].OUT_BEL[19]	CELL[33].OUT_BEL[19]
RXRUNDISP[3]	out	CELL[3].OUT_BEL[1]	CELL[13].OUT_BEL[1]	CELL[23].OUT_BEL[1]	CELL[33].OUT_BEL[1]
RXDLYALIGNMONITOR[0]	out	CELL[5].OUT_BEL[21]	CELL[15].OUT_BEL[21]	CELL[25].OUT_BEL[21]	CELL[35].OUT_BEL[21]
RXDLYALIGNMONITOR[1]	out	CELL[5].OUT_BEL[15]	CELL[15].OUT_BEL[15]	CELL[25].OUT_BEL[15]	CELL[35].OUT_BEL[15]
RXDLYALIGNMONITOR[2]	out	CELL[5].OUT_BEL[7]	CELL[15].OUT_BEL[7]	CELL[25].OUT_BEL[7]	CELL[35].OUT_BEL[7]
RXDLYALIGNMONITOR[3]	out	CELL[5].OUT_BEL[20]	CELL[15].OUT_BEL[20]	CELL[25].OUT_BEL[20]	CELL[35].OUT_BEL[20]
RXDLYALIGNMONITOR[4]	out	CELL[5].OUT_BEL[23]	CELL[15].OUT_BEL[23]	CELL[25].OUT_BEL[23]	CELL[35].OUT_BEL[23]
RXDLYALIGNMONITOR[5]	out	CELL[5].OUT_BEL[19]	CELL[15].OUT_BEL[19]	CELL[25].OUT_BEL[19]	CELL[35].OUT_BEL[19]
RXDLYALIGNMONITOR[6]	out	CELL[5].OUT_BEL[18]	CELL[15].OUT_BEL[18]	CELL[25].OUT_BEL[18]	CELL[35].OUT_BEL[18]
RXDLYALIGNMONITOR[7]	out	CELL[5].OUT_BEL[0]	CELL[15].OUT_BEL[0]	CELL[25].OUT_BEL[0]	CELL[35].OUT_BEL[0]
RXBUFSTATUS[0]	out	CELL[4].OUT_BEL[6]	CELL[14].OUT_BEL[6]	CELL[24].OUT_BEL[6]	CELL[34].OUT_BEL[6]
RXBUFSTATUS[1]	out	CELL[4].OUT_BEL[7]	CELL[14].OUT_BEL[7]	CELL[24].OUT_BEL[7]	CELL[34].OUT_BEL[7]
RXBUFSTATUS[2]	out	CELL[4].OUT_BEL[3]	CELL[14].OUT_BEL[3]	CELL[24].OUT_BEL[3]	CELL[34].OUT_BEL[3]
RXCLKCORCNT[0]	out	CELL[5].OUT_BEL[8]	CELL[15].OUT_BEL[8]	CELL[25].OUT_BEL[8]	CELL[35].OUT_BEL[8]
RXCLKCORCNT[1]	out	CELL[5].OUT_BEL[9]	CELL[15].OUT_BEL[9]	CELL[25].OUT_BEL[9]	CELL[35].OUT_BEL[9]
RXCLKCORCNT[2]	out	CELL[5].OUT_BEL[6]	CELL[15].OUT_BEL[6]	CELL[25].OUT_BEL[6]	CELL[35].OUT_BEL[6]
RXCHANBONDSEQ	out	CELL[5].OUT_BEL[14]	CELL[15].OUT_BEL[14]	CELL[25].OUT_BEL[14]	CELL[35].OUT_BEL[14]
RXCHANISALIGNED	out	CELL[3].OUT_BEL[13]	CELL[13].OUT_BEL[13]	CELL[23].OUT_BEL[13]	CELL[33].OUT_BEL[13]
RXCHANREALIGN	out	CELL[2].OUT_BEL[14]	CELL[12].OUT_BEL[14]	CELL[22].OUT_BEL[14]	CELL[32].OUT_BEL[14]
RXCHBONDO[0]	out	CELL[4].OUT_BEL[17]	CELL[14].OUT_BEL[17]	CELL[24].OUT_BEL[17]	CELL[34].OUT_BEL[17]
RXCHBONDO[1]	out	CELL[4].OUT_BEL[10]	CELL[14].OUT_BEL[10]	CELL[24].OUT_BEL[10]	CELL[34].OUT_BEL[10]
RXCHBONDO[2]	out	CELL[4].OUT_BEL[11]	CELL[14].OUT_BEL[11]	CELL[24].OUT_BEL[11]	CELL[34].OUT_BEL[11]
RXCHBONDO[3]	out	CELL[4].OUT_BEL[15]	CELL[14].OUT_BEL[15]	CELL[24].OUT_BEL[15]	CELL[34].OUT_BEL[15]
RXDATAVALID	out	CELL[2].OUT_BEL[4]	CELL[12].OUT_BEL[4]	CELL[22].OUT_BEL[4]	CELL[32].OUT_BEL[4]
RXHEADER[0]	out	CELL[5].OUT_BEL[10]	CELL[15].OUT_BEL[10]	CELL[25].OUT_BEL[10]	CELL[35].OUT_BEL[10]
RXHEADER[1]	out	CELL[5].OUT_BEL[16]	CELL[15].OUT_BEL[16]	CELL[25].OUT_BEL[16]	CELL[35].OUT_BEL[16]
RXHEADER[2]	out	CELL[5].OUT_BEL[17]	CELL[15].OUT_BEL[17]	CELL[25].OUT_BEL[17]	CELL[35].OUT_BEL[17]
RXHEADERVALID	out	CELL[5].OUT_BEL[11]	CELL[15].OUT_BEL[11]	CELL[25].OUT_BEL[11]	CELL[35].OUT_BEL[11]
RXSTARTOFSEQ	out	CELL[5].OUT_BEL[1]	CELL[15].OUT_BEL[1]	CELL[25].OUT_BEL[1]	CELL[35].OUT_BEL[1]
RXDATA[0]	out	CELL[0].OUT_BEL[4]	CELL[10].OUT_BEL[4]	CELL[20].OUT_BEL[4]	CELL[30].OUT_BEL[4]
RXDATA[1]	out	CELL[0].OUT_BEL[7]	CELL[10].OUT_BEL[7]	CELL[20].OUT_BEL[7]	CELL[30].OUT_BEL[7]
RXDATA[2]	out	CELL[0].OUT_BEL[6]	CELL[10].OUT_BEL[6]	CELL[20].OUT_BEL[6]	CELL[30].OUT_BEL[6]
RXDATA[3]	out	CELL[0].OUT_BEL[2]	CELL[10].OUT_BEL[2]	CELL[20].OUT_BEL[2]	CELL[30].OUT_BEL[2]
RXDATA[4]	out	CELL[0].OUT_BEL[1]	CELL[10].OUT_BEL[1]	CELL[20].OUT_BEL[1]	CELL[30].OUT_BEL[1]
RXDATA[5]	out	CELL[0].OUT_BEL[5]	CELL[10].OUT_BEL[5]	CELL[20].OUT_BEL[5]	CELL[30].OUT_BEL[5]
RXDATA[6]	out	CELL[1].OUT_BEL[1]	CELL[11].OUT_BEL[1]	CELL[21].OUT_BEL[1]	CELL[31].OUT_BEL[1]
RXDATA[7]	out	CELL[1].OUT_BEL[5]	CELL[11].OUT_BEL[5]	CELL[21].OUT_BEL[5]	CELL[31].OUT_BEL[5]
RXDATA[8]	out	CELL[1].OUT_BEL[4]	CELL[11].OUT_BEL[4]	CELL[21].OUT_BEL[4]	CELL[31].OUT_BEL[4]
RXDATA[9]	out	CELL[1].OUT_BEL[7]	CELL[11].OUT_BEL[7]	CELL[21].OUT_BEL[7]	CELL[31].OUT_BEL[7]
RXDATA[10]	out	CELL[1].OUT_BEL[6]	CELL[11].OUT_BEL[6]	CELL[21].OUT_BEL[6]	CELL[31].OUT_BEL[6]
RXDATA[11]	out	CELL[1].OUT_BEL[2]	CELL[11].OUT_BEL[2]	CELL[21].OUT_BEL[2]	CELL[31].OUT_BEL[2]
RXDATA[12]	out	CELL[2].OUT_BEL[7]	CELL[12].OUT_BEL[7]	CELL[22].OUT_BEL[7]	CELL[32].OUT_BEL[7]
RXDATA[13]	out	CELL[2].OUT_BEL[6]	CELL[12].OUT_BEL[6]	CELL[22].OUT_BEL[6]	CELL[32].OUT_BEL[6]
RXDATA[14]	out	CELL[2].OUT_BEL[2]	CELL[12].OUT_BEL[2]	CELL[22].OUT_BEL[2]	CELL[32].OUT_BEL[2]
RXDATA[15]	out	CELL[2].OUT_BEL[1]	CELL[12].OUT_BEL[1]	CELL[22].OUT_BEL[1]	CELL[32].OUT_BEL[1]
RXDATA[16]	out	CELL[0].OUT_BEL[15]	CELL[10].OUT_BEL[15]	CELL[20].OUT_BEL[15]	CELL[30].OUT_BEL[15]
RXDATA[17]	out	CELL[0].OUT_BEL[3]	CELL[10].OUT_BEL[3]	CELL[20].OUT_BEL[3]	CELL[30].OUT_BEL[3]
RXDATA[18]	out	CELL[0].OUT_BEL[0]	CELL[10].OUT_BEL[0]	CELL[20].OUT_BEL[0]	CELL[30].OUT_BEL[0]
RXDATA[19]	out	CELL[0].OUT_BEL[22]	CELL[10].OUT_BEL[22]	CELL[20].OUT_BEL[22]	CELL[30].OUT_BEL[22]
RXDATA[20]	out	CELL[0].OUT_BEL[18]	CELL[10].OUT_BEL[18]	CELL[20].OUT_BEL[18]	CELL[30].OUT_BEL[18]
RXDATA[21]	out	CELL[0].OUT_BEL[17]	CELL[10].OUT_BEL[17]	CELL[20].OUT_BEL[17]	CELL[30].OUT_BEL[17]
RXDATA[22]	out	CELL[0].OUT_BEL[16]	CELL[10].OUT_BEL[16]	CELL[20].OUT_BEL[16]	CELL[30].OUT_BEL[16]
RXDATA[23]	out	CELL[0].OUT_BEL[20]	CELL[10].OUT_BEL[20]	CELL[20].OUT_BEL[20]	CELL[30].OUT_BEL[20]
RXDATA[24]	out	CELL[1].OUT_BEL[0]	CELL[11].OUT_BEL[0]	CELL[21].OUT_BEL[0]	CELL[31].OUT_BEL[0]
RXDATA[25]	out	CELL[1].OUT_BEL[22]	CELL[11].OUT_BEL[22]	CELL[21].OUT_BEL[22]	CELL[31].OUT_BEL[22]
RXDATA[26]	out	CELL[1].OUT_BEL[18]	CELL[11].OUT_BEL[18]	CELL[21].OUT_BEL[18]	CELL[31].OUT_BEL[18]
RXDATA[27]	out	CELL[1].OUT_BEL[9]	CELL[11].OUT_BEL[9]	CELL[21].OUT_BEL[9]	CELL[31].OUT_BEL[9]
RXDATA[28]	out	CELL[1].OUT_BEL[16]	CELL[11].OUT_BEL[16]	CELL[21].OUT_BEL[16]	CELL[31].OUT_BEL[16]
RXDATA[29]	out	CELL[1].OUT_BEL[11]	CELL[11].OUT_BEL[11]	CELL[21].OUT_BEL[11]	CELL[31].OUT_BEL[11]
RXDATA[30]	out	CELL[1].OUT_BEL[15]	CELL[11].OUT_BEL[15]	CELL[21].OUT_BEL[15]	CELL[31].OUT_BEL[15]
RXDATA[31]	out	CELL[1].OUT_BEL[3]	CELL[11].OUT_BEL[3]	CELL[21].OUT_BEL[3]	CELL[31].OUT_BEL[3]
TXOUTCLK	out	CELL[20].MGT_ROW[2]	CELL[20].MGT_ROW[3]	CELL[20].MGT_ROW[8]	CELL[20].MGT_ROW[9]
TXOUTCLKPCS	out	CELL[6].OUT_BEL[8]	CELL[16].OUT_BEL[8]	CELL[26].OUT_BEL[8]	CELL[36].OUT_BEL[8]
TXRESETDONE	out	CELL[7].OUT_BEL[22]	CELL[17].OUT_BEL[22]	CELL[27].OUT_BEL[22]	CELL[37].OUT_BEL[22]
TXKERR[0]	out	CELL[7].OUT_BEL[14]	CELL[17].OUT_BEL[14]	CELL[27].OUT_BEL[14]	CELL[37].OUT_BEL[14]
TXKERR[1]	out	CELL[7].OUT_BEL[10]	CELL[17].OUT_BEL[10]	CELL[27].OUT_BEL[10]	CELL[37].OUT_BEL[10]
TXKERR[2]	out	CELL[7].OUT_BEL[11]	CELL[17].OUT_BEL[11]	CELL[27].OUT_BEL[11]	CELL[37].OUT_BEL[11]
TXKERR[3]	out	CELL[7].OUT_BEL[15]	CELL[17].OUT_BEL[15]	CELL[27].OUT_BEL[15]	CELL[37].OUT_BEL[15]
TXRUNDISP[0]	out	CELL[8].OUT_BEL[14]	CELL[18].OUT_BEL[14]	CELL[28].OUT_BEL[14]	CELL[38].OUT_BEL[14]
TXRUNDISP[1]	out	CELL[8].OUT_BEL[10]	CELL[18].OUT_BEL[10]	CELL[28].OUT_BEL[10]	CELL[38].OUT_BEL[10]
TXRUNDISP[2]	out	CELL[8].OUT_BEL[11]	CELL[18].OUT_BEL[11]	CELL[28].OUT_BEL[11]	CELL[38].OUT_BEL[11]
TXRUNDISP[3]	out	CELL[8].OUT_BEL[15]	CELL[18].OUT_BEL[15]	CELL[28].OUT_BEL[15]	CELL[38].OUT_BEL[15]
TXGEARBOXREADY	out	CELL[6].OUT_BEL[4]	CELL[16].OUT_BEL[4]	CELL[26].OUT_BEL[4]	CELL[36].OUT_BEL[4]
TXBUFSTATUS[0]	out	CELL[7].OUT_BEL[5]	CELL[17].OUT_BEL[5]	CELL[27].OUT_BEL[5]	CELL[37].OUT_BEL[5]
TXBUFSTATUS[1]	out	CELL[7].OUT_BEL[17]	CELL[17].OUT_BEL[17]	CELL[27].OUT_BEL[17]	CELL[37].OUT_BEL[17]
TXDLYALIGNMONITOR[0]	out	CELL[7].OUT_BEL[21]	CELL[17].OUT_BEL[21]	CELL[27].OUT_BEL[21]	CELL[37].OUT_BEL[21]
TXDLYALIGNMONITOR[1]	out	CELL[7].OUT_BEL[16]	CELL[17].OUT_BEL[16]	CELL[27].OUT_BEL[16]	CELL[37].OUT_BEL[16]
TXDLYALIGNMONITOR[2]	out	CELL[7].OUT_BEL[4]	CELL[17].OUT_BEL[4]	CELL[27].OUT_BEL[4]	CELL[37].OUT_BEL[4]
TXDLYALIGNMONITOR[3]	out	CELL[7].OUT_BEL[20]	CELL[17].OUT_BEL[20]	CELL[27].OUT_BEL[20]	CELL[37].OUT_BEL[20]
TXDLYALIGNMONITOR[4]	out	CELL[7].OUT_BEL[23]	CELL[17].OUT_BEL[23]	CELL[27].OUT_BEL[23]	CELL[37].OUT_BEL[23]
TXDLYALIGNMONITOR[5]	out	CELL[7].OUT_BEL[19]	CELL[17].OUT_BEL[19]	CELL[27].OUT_BEL[19]	CELL[37].OUT_BEL[19]
TXDLYALIGNMONITOR[6]	out	CELL[7].OUT_BEL[18]	CELL[17].OUT_BEL[18]	CELL[27].OUT_BEL[18]	CELL[37].OUT_BEL[18]
TXDLYALIGNMONITOR[7]	out	CELL[7].OUT_BEL[0]	CELL[17].OUT_BEL[0]	CELL[27].OUT_BEL[0]	CELL[37].OUT_BEL[0]
TXRATEDONE	out	CELL[6].OUT_BEL[23]	CELL[16].OUT_BEL[23]	CELL[26].OUT_BEL[23]	CELL[36].OUT_BEL[23]
COMFINISH	out	CELL[8].OUT_BEL[18]	CELL[18].OUT_BEL[18]	CELL[28].OUT_BEL[18]	CELL[38].OUT_BEL[18]
TSTOUT[0]	out	CELL[1].OUT_BEL[21]	CELL[11].OUT_BEL[21]	CELL[21].OUT_BEL[21]	CELL[31].OUT_BEL[21]
TSTOUT[1]	out	CELL[1].OUT_BEL[17]	CELL[11].OUT_BEL[17]	CELL[21].OUT_BEL[17]	CELL[31].OUT_BEL[17]
TSTOUT[2]	out	CELL[1].OUT_BEL[10]	CELL[11].OUT_BEL[10]	CELL[21].OUT_BEL[10]	CELL[31].OUT_BEL[10]
TSTOUT[3]	out	CELL[1].OUT_BEL[20]	CELL[11].OUT_BEL[20]	CELL[21].OUT_BEL[20]	CELL[31].OUT_BEL[20]
TSTOUT[4]	out	CELL[1].OUT_BEL[14]	CELL[11].OUT_BEL[14]	CELL[21].OUT_BEL[14]	CELL[31].OUT_BEL[14]
TSTOUT[5]	out	CELL[1].OUT_BEL[23]	CELL[11].OUT_BEL[23]	CELL[21].OUT_BEL[23]	CELL[31].OUT_BEL[23]
TSTOUT[6]	out	CELL[1].OUT_BEL[13]	CELL[11].OUT_BEL[13]	CELL[21].OUT_BEL[13]	CELL[31].OUT_BEL[13]
TSTOUT[7]	out	CELL[1].OUT_BEL[19]	CELL[11].OUT_BEL[19]	CELL[21].OUT_BEL[19]	CELL[31].OUT_BEL[19]
TSTOUT[8]	out	CELL[1].OUT_BEL[8]	CELL[11].OUT_BEL[8]	CELL[21].OUT_BEL[8]	CELL[31].OUT_BEL[8]
TSTOUT[9]	out	CELL[1].OUT_BEL[12]	CELL[11].OUT_BEL[12]	CELL[21].OUT_BEL[12]	CELL[31].OUT_BEL[12]
SCANOUT[0]	out	CELL[4].OUT_BEL[18]	CELL[14].OUT_BEL[18]	CELL[24].OUT_BEL[18]	CELL[34].OUT_BEL[18]
SCANOUT[1]	out	CELL[4].OUT_BEL[4]	CELL[14].OUT_BEL[4]	CELL[24].OUT_BEL[4]	CELL[34].OUT_BEL[4]
SCANOUT[2]	out	CELL[0].OUT_BEL[23]	CELL[10].OUT_BEL[23]	CELL[20].OUT_BEL[23]	CELL[30].OUT_BEL[23]
SCANOUT[3]	out	CELL[0].OUT_BEL[13]	CELL[10].OUT_BEL[13]	CELL[20].OUT_BEL[13]	CELL[30].OUT_BEL[13]
SCANOUT[4]	out	CELL[0].OUT_BEL[8]	CELL[10].OUT_BEL[8]	CELL[20].OUT_BEL[8]	CELL[30].OUT_BEL[8]

virtex6 GTX bel GTX attribute bits
Attribute	GTX[0]	GTX[1]	GTX[2]	GTX[3]
DRP[0] bit 0	MAIN[0][28][0]	MAIN[10][28][0]	MAIN[20][28][0]	MAIN[30][28][0]
DRP[0] bit 1	MAIN[0][29][0]	MAIN[10][29][0]	MAIN[20][29][0]	MAIN[30][29][0]
DRP[0] bit 2	MAIN[0][28][1]	MAIN[10][28][1]	MAIN[20][28][1]	MAIN[30][28][1]
DRP[0] bit 3	MAIN[0][29][1]	MAIN[10][29][1]	MAIN[20][29][1]	MAIN[30][29][1]
DRP[0] bit 4	MAIN[0][28][2]	MAIN[10][28][2]	MAIN[20][28][2]	MAIN[30][28][2]
DRP[0] bit 5	MAIN[0][29][2]	MAIN[10][29][2]	MAIN[20][29][2]	MAIN[30][29][2]
DRP[0] bit 6	MAIN[0][28][3]	MAIN[10][28][3]	MAIN[20][28][3]	MAIN[30][28][3]
DRP[0] bit 7	MAIN[0][29][3]	MAIN[10][29][3]	MAIN[20][29][3]	MAIN[30][29][3]
DRP[0] bit 8	MAIN[0][28][4]	MAIN[10][28][4]	MAIN[20][28][4]	MAIN[30][28][4]
DRP[0] bit 9	MAIN[0][29][4]	MAIN[10][29][4]	MAIN[20][29][4]	MAIN[30][29][4]
DRP[0] bit 10	MAIN[0][28][5]	MAIN[10][28][5]	MAIN[20][28][5]	MAIN[30][28][5]
DRP[0] bit 11	MAIN[0][29][5]	MAIN[10][29][5]	MAIN[20][29][5]	MAIN[30][29][5]
DRP[0] bit 12	MAIN[0][28][6]	MAIN[10][28][6]	MAIN[20][28][6]	MAIN[30][28][6]
DRP[0] bit 13	MAIN[0][29][6]	MAIN[10][29][6]	MAIN[20][29][6]	MAIN[30][29][6]
DRP[0] bit 14	MAIN[0][28][7]	MAIN[10][28][7]	MAIN[20][28][7]	MAIN[30][28][7]
DRP[0] bit 15	MAIN[0][29][7]	MAIN[10][29][7]	MAIN[20][29][7]	MAIN[30][29][7]
DRP[1] bit 0	MAIN[0][28][8]	MAIN[10][28][8]	MAIN[20][28][8]	MAIN[30][28][8]
DRP[1] bit 1	MAIN[0][29][8]	MAIN[10][29][8]	MAIN[20][29][8]	MAIN[30][29][8]
DRP[1] bit 2	MAIN[0][28][9]	MAIN[10][28][9]	MAIN[20][28][9]	MAIN[30][28][9]
DRP[1] bit 3	MAIN[0][29][9]	MAIN[10][29][9]	MAIN[20][29][9]	MAIN[30][29][9]
DRP[1] bit 4	MAIN[0][28][10]	MAIN[10][28][10]	MAIN[20][28][10]	MAIN[30][28][10]
DRP[1] bit 5	MAIN[0][29][10]	MAIN[10][29][10]	MAIN[20][29][10]	MAIN[30][29][10]
DRP[1] bit 6	MAIN[0][28][11]	MAIN[10][28][11]	MAIN[20][28][11]	MAIN[30][28][11]
DRP[1] bit 7	MAIN[0][29][11]	MAIN[10][29][11]	MAIN[20][29][11]	MAIN[30][29][11]
DRP[1] bit 8	MAIN[0][28][12]	MAIN[10][28][12]	MAIN[20][28][12]	MAIN[30][28][12]
DRP[1] bit 9	MAIN[0][29][12]	MAIN[10][29][12]	MAIN[20][29][12]	MAIN[30][29][12]
DRP[1] bit 10	MAIN[0][28][13]	MAIN[10][28][13]	MAIN[20][28][13]	MAIN[30][28][13]
DRP[1] bit 11	MAIN[0][29][13]	MAIN[10][29][13]	MAIN[20][29][13]	MAIN[30][29][13]
DRP[1] bit 12	MAIN[0][28][14]	MAIN[10][28][14]	MAIN[20][28][14]	MAIN[30][28][14]
DRP[1] bit 13	MAIN[0][29][14]	MAIN[10][29][14]	MAIN[20][29][14]	MAIN[30][29][14]
DRP[1] bit 14	MAIN[0][28][15]	MAIN[10][28][15]	MAIN[20][28][15]	MAIN[30][28][15]
DRP[1] bit 15	MAIN[0][29][15]	MAIN[10][29][15]	MAIN[20][29][15]	MAIN[30][29][15]
DRP[2] bit 0	MAIN[0][28][16]	MAIN[10][28][16]	MAIN[20][28][16]	MAIN[30][28][16]
DRP[2] bit 1	MAIN[0][29][16]	MAIN[10][29][16]	MAIN[20][29][16]	MAIN[30][29][16]
DRP[2] bit 2	MAIN[0][28][17]	MAIN[10][28][17]	MAIN[20][28][17]	MAIN[30][28][17]
DRP[2] bit 3	MAIN[0][29][17]	MAIN[10][29][17]	MAIN[20][29][17]	MAIN[30][29][17]
DRP[2] bit 4	MAIN[0][28][18]	MAIN[10][28][18]	MAIN[20][28][18]	MAIN[30][28][18]
DRP[2] bit 5	MAIN[0][29][18]	MAIN[10][29][18]	MAIN[20][29][18]	MAIN[30][29][18]
DRP[2] bit 6	MAIN[0][28][19]	MAIN[10][28][19]	MAIN[20][28][19]	MAIN[30][28][19]
DRP[2] bit 7	MAIN[0][29][19]	MAIN[10][29][19]	MAIN[20][29][19]	MAIN[30][29][19]
DRP[2] bit 8	MAIN[0][28][20]	MAIN[10][28][20]	MAIN[20][28][20]	MAIN[30][28][20]
DRP[2] bit 9	MAIN[0][29][20]	MAIN[10][29][20]	MAIN[20][29][20]	MAIN[30][29][20]
DRP[2] bit 10	MAIN[0][28][21]	MAIN[10][28][21]	MAIN[20][28][21]	MAIN[30][28][21]
DRP[2] bit 11	MAIN[0][29][21]	MAIN[10][29][21]	MAIN[20][29][21]	MAIN[30][29][21]
DRP[2] bit 12	MAIN[0][28][22]	MAIN[10][28][22]	MAIN[20][28][22]	MAIN[30][28][22]
DRP[2] bit 13	MAIN[0][29][22]	MAIN[10][29][22]	MAIN[20][29][22]	MAIN[30][29][22]
DRP[2] bit 14	MAIN[0][28][23]	MAIN[10][28][23]	MAIN[20][28][23]	MAIN[30][28][23]
DRP[2] bit 15	MAIN[0][29][23]	MAIN[10][29][23]	MAIN[20][29][23]	MAIN[30][29][23]
DRP[3] bit 0	MAIN[0][28][24]	MAIN[10][28][24]	MAIN[20][28][24]	MAIN[30][28][24]
DRP[3] bit 1	MAIN[0][29][24]	MAIN[10][29][24]	MAIN[20][29][24]	MAIN[30][29][24]
DRP[3] bit 2	MAIN[0][28][25]	MAIN[10][28][25]	MAIN[20][28][25]	MAIN[30][28][25]
DRP[3] bit 3	MAIN[0][29][25]	MAIN[10][29][25]	MAIN[20][29][25]	MAIN[30][29][25]
DRP[3] bit 4	MAIN[0][28][26]	MAIN[10][28][26]	MAIN[20][28][26]	MAIN[30][28][26]
DRP[3] bit 5	MAIN[0][29][26]	MAIN[10][29][26]	MAIN[20][29][26]	MAIN[30][29][26]
DRP[3] bit 6	MAIN[0][28][27]	MAIN[10][28][27]	MAIN[20][28][27]	MAIN[30][28][27]
DRP[3] bit 7	MAIN[0][29][27]	MAIN[10][29][27]	MAIN[20][29][27]	MAIN[30][29][27]
DRP[3] bit 8	MAIN[0][28][28]	MAIN[10][28][28]	MAIN[20][28][28]	MAIN[30][28][28]
DRP[3] bit 9	MAIN[0][29][28]	MAIN[10][29][28]	MAIN[20][29][28]	MAIN[30][29][28]
DRP[3] bit 10	MAIN[0][28][29]	MAIN[10][28][29]	MAIN[20][28][29]	MAIN[30][28][29]
DRP[3] bit 11	MAIN[0][29][29]	MAIN[10][29][29]	MAIN[20][29][29]	MAIN[30][29][29]
DRP[3] bit 12	MAIN[0][28][30]	MAIN[10][28][30]	MAIN[20][28][30]	MAIN[30][28][30]
DRP[3] bit 13	MAIN[0][29][30]	MAIN[10][29][30]	MAIN[20][29][30]	MAIN[30][29][30]
DRP[3] bit 14	MAIN[0][28][31]	MAIN[10][28][31]	MAIN[20][28][31]	MAIN[30][28][31]
DRP[3] bit 15	MAIN[0][29][31]	MAIN[10][29][31]	MAIN[20][29][31]	MAIN[30][29][31]
DRP[4] bit 0	MAIN[0][28][32]	MAIN[10][28][32]	MAIN[20][28][32]	MAIN[30][28][32]
DRP[4] bit 1	MAIN[0][29][32]	MAIN[10][29][32]	MAIN[20][29][32]	MAIN[30][29][32]
DRP[4] bit 2	MAIN[0][28][33]	MAIN[10][28][33]	MAIN[20][28][33]	MAIN[30][28][33]
DRP[4] bit 3	MAIN[0][29][33]	MAIN[10][29][33]	MAIN[20][29][33]	MAIN[30][29][33]
DRP[4] bit 4	MAIN[0][28][34]	MAIN[10][28][34]	MAIN[20][28][34]	MAIN[30][28][34]
DRP[4] bit 5	MAIN[0][29][34]	MAIN[10][29][34]	MAIN[20][29][34]	MAIN[30][29][34]
DRP[4] bit 6	MAIN[0][28][35]	MAIN[10][28][35]	MAIN[20][28][35]	MAIN[30][28][35]
DRP[4] bit 7	MAIN[0][29][35]	MAIN[10][29][35]	MAIN[20][29][35]	MAIN[30][29][35]
DRP[4] bit 8	MAIN[0][28][36]	MAIN[10][28][36]	MAIN[20][28][36]	MAIN[30][28][36]
DRP[4] bit 9	MAIN[0][29][36]	MAIN[10][29][36]	MAIN[20][29][36]	MAIN[30][29][36]
DRP[4] bit 10	MAIN[0][28][37]	MAIN[10][28][37]	MAIN[20][28][37]	MAIN[30][28][37]
DRP[4] bit 11	MAIN[0][29][37]	MAIN[10][29][37]	MAIN[20][29][37]	MAIN[30][29][37]
DRP[4] bit 12	MAIN[0][28][38]	MAIN[10][28][38]	MAIN[20][28][38]	MAIN[30][28][38]
DRP[4] bit 13	MAIN[0][29][38]	MAIN[10][29][38]	MAIN[20][29][38]	MAIN[30][29][38]
DRP[4] bit 14	MAIN[0][28][39]	MAIN[10][28][39]	MAIN[20][28][39]	MAIN[30][28][39]
DRP[4] bit 15	MAIN[0][29][39]	MAIN[10][29][39]	MAIN[20][29][39]	MAIN[30][29][39]
DRP[5] bit 0	MAIN[0][28][40]	MAIN[10][28][40]	MAIN[20][28][40]	MAIN[30][28][40]
DRP[5] bit 1	MAIN[0][29][40]	MAIN[10][29][40]	MAIN[20][29][40]	MAIN[30][29][40]
DRP[5] bit 2	MAIN[0][28][41]	MAIN[10][28][41]	MAIN[20][28][41]	MAIN[30][28][41]
DRP[5] bit 3	MAIN[0][29][41]	MAIN[10][29][41]	MAIN[20][29][41]	MAIN[30][29][41]
DRP[5] bit 4	MAIN[0][28][42]	MAIN[10][28][42]	MAIN[20][28][42]	MAIN[30][28][42]
DRP[5] bit 5	MAIN[0][29][42]	MAIN[10][29][42]	MAIN[20][29][42]	MAIN[30][29][42]
DRP[5] bit 6	MAIN[0][28][43]	MAIN[10][28][43]	MAIN[20][28][43]	MAIN[30][28][43]
DRP[5] bit 7	MAIN[0][29][43]	MAIN[10][29][43]	MAIN[20][29][43]	MAIN[30][29][43]
DRP[5] bit 8	MAIN[0][28][44]	MAIN[10][28][44]	MAIN[20][28][44]	MAIN[30][28][44]
DRP[5] bit 9	MAIN[0][29][44]	MAIN[10][29][44]	MAIN[20][29][44]	MAIN[30][29][44]
DRP[5] bit 10	MAIN[0][28][45]	MAIN[10][28][45]	MAIN[20][28][45]	MAIN[30][28][45]
DRP[5] bit 11	MAIN[0][29][45]	MAIN[10][29][45]	MAIN[20][29][45]	MAIN[30][29][45]
DRP[5] bit 12	MAIN[0][28][46]	MAIN[10][28][46]	MAIN[20][28][46]	MAIN[30][28][46]
DRP[5] bit 13	MAIN[0][29][46]	MAIN[10][29][46]	MAIN[20][29][46]	MAIN[30][29][46]
DRP[5] bit 14	MAIN[0][28][47]	MAIN[10][28][47]	MAIN[20][28][47]	MAIN[30][28][47]
DRP[5] bit 15	MAIN[0][29][47]	MAIN[10][29][47]	MAIN[20][29][47]	MAIN[30][29][47]
DRP[6] bit 0	MAIN[0][28][48]	MAIN[10][28][48]	MAIN[20][28][48]	MAIN[30][28][48]
DRP[6] bit 1	MAIN[0][29][48]	MAIN[10][29][48]	MAIN[20][29][48]	MAIN[30][29][48]
DRP[6] bit 2	MAIN[0][28][49]	MAIN[10][28][49]	MAIN[20][28][49]	MAIN[30][28][49]
DRP[6] bit 3	MAIN[0][29][49]	MAIN[10][29][49]	MAIN[20][29][49]	MAIN[30][29][49]
DRP[6] bit 4	MAIN[0][28][50]	MAIN[10][28][50]	MAIN[20][28][50]	MAIN[30][28][50]
DRP[6] bit 5	MAIN[0][29][50]	MAIN[10][29][50]	MAIN[20][29][50]	MAIN[30][29][50]
DRP[6] bit 6	MAIN[0][28][51]	MAIN[10][28][51]	MAIN[20][28][51]	MAIN[30][28][51]
DRP[6] bit 7	MAIN[0][29][51]	MAIN[10][29][51]	MAIN[20][29][51]	MAIN[30][29][51]
DRP[6] bit 8	MAIN[0][28][52]	MAIN[10][28][52]	MAIN[20][28][52]	MAIN[30][28][52]
DRP[6] bit 9	MAIN[0][29][52]	MAIN[10][29][52]	MAIN[20][29][52]	MAIN[30][29][52]
DRP[6] bit 10	MAIN[0][28][53]	MAIN[10][28][53]	MAIN[20][28][53]	MAIN[30][28][53]
DRP[6] bit 11	MAIN[0][29][53]	MAIN[10][29][53]	MAIN[20][29][53]	MAIN[30][29][53]
DRP[6] bit 12	MAIN[0][28][54]	MAIN[10][28][54]	MAIN[20][28][54]	MAIN[30][28][54]
DRP[6] bit 13	MAIN[0][29][54]	MAIN[10][29][54]	MAIN[20][29][54]	MAIN[30][29][54]
DRP[6] bit 14	MAIN[0][28][55]	MAIN[10][28][55]	MAIN[20][28][55]	MAIN[30][28][55]
DRP[6] bit 15	MAIN[0][29][55]	MAIN[10][29][55]	MAIN[20][29][55]	MAIN[30][29][55]
DRP[7] bit 0	MAIN[0][28][56]	MAIN[10][28][56]	MAIN[20][28][56]	MAIN[30][28][56]
DRP[7] bit 1	MAIN[0][29][56]	MAIN[10][29][56]	MAIN[20][29][56]	MAIN[30][29][56]
DRP[7] bit 2	MAIN[0][28][57]	MAIN[10][28][57]	MAIN[20][28][57]	MAIN[30][28][57]
DRP[7] bit 3	MAIN[0][29][57]	MAIN[10][29][57]	MAIN[20][29][57]	MAIN[30][29][57]
DRP[7] bit 4	MAIN[0][28][58]	MAIN[10][28][58]	MAIN[20][28][58]	MAIN[30][28][58]
DRP[7] bit 5	MAIN[0][29][58]	MAIN[10][29][58]	MAIN[20][29][58]	MAIN[30][29][58]
DRP[7] bit 6	MAIN[0][28][59]	MAIN[10][28][59]	MAIN[20][28][59]	MAIN[30][28][59]
DRP[7] bit 7	MAIN[0][29][59]	MAIN[10][29][59]	MAIN[20][29][59]	MAIN[30][29][59]
DRP[7] bit 8	MAIN[0][28][60]	MAIN[10][28][60]	MAIN[20][28][60]	MAIN[30][28][60]
DRP[7] bit 9	MAIN[0][29][60]	MAIN[10][29][60]	MAIN[20][29][60]	MAIN[30][29][60]
DRP[7] bit 10	MAIN[0][28][61]	MAIN[10][28][61]	MAIN[20][28][61]	MAIN[30][28][61]
DRP[7] bit 11	MAIN[0][29][61]	MAIN[10][29][61]	MAIN[20][29][61]	MAIN[30][29][61]
DRP[7] bit 12	MAIN[0][28][62]	MAIN[10][28][62]	MAIN[20][28][62]	MAIN[30][28][62]
DRP[7] bit 13	MAIN[0][29][62]	MAIN[10][29][62]	MAIN[20][29][62]	MAIN[30][29][62]
DRP[7] bit 14	MAIN[0][28][63]	MAIN[10][28][63]	MAIN[20][28][63]	MAIN[30][28][63]
DRP[7] bit 15	MAIN[0][29][63]	MAIN[10][29][63]	MAIN[20][29][63]	MAIN[30][29][63]
DRP[8] bit 0	MAIN[1][28][0]	MAIN[11][28][0]	MAIN[21][28][0]	MAIN[31][28][0]
DRP[8] bit 1	MAIN[1][29][0]	MAIN[11][29][0]	MAIN[21][29][0]	MAIN[31][29][0]
DRP[8] bit 2	MAIN[1][28][1]	MAIN[11][28][1]	MAIN[21][28][1]	MAIN[31][28][1]
DRP[8] bit 3	MAIN[1][29][1]	MAIN[11][29][1]	MAIN[21][29][1]	MAIN[31][29][1]
DRP[8] bit 4	MAIN[1][28][2]	MAIN[11][28][2]	MAIN[21][28][2]	MAIN[31][28][2]
DRP[8] bit 5	MAIN[1][29][2]	MAIN[11][29][2]	MAIN[21][29][2]	MAIN[31][29][2]
DRP[8] bit 6	MAIN[1][28][3]	MAIN[11][28][3]	MAIN[21][28][3]	MAIN[31][28][3]
DRP[8] bit 7	MAIN[1][29][3]	MAIN[11][29][3]	MAIN[21][29][3]	MAIN[31][29][3]
DRP[8] bit 8	MAIN[1][28][4]	MAIN[11][28][4]	MAIN[21][28][4]	MAIN[31][28][4]
DRP[8] bit 9	MAIN[1][29][4]	MAIN[11][29][4]	MAIN[21][29][4]	MAIN[31][29][4]
DRP[8] bit 10	MAIN[1][28][5]	MAIN[11][28][5]	MAIN[21][28][5]	MAIN[31][28][5]
DRP[8] bit 11	MAIN[1][29][5]	MAIN[11][29][5]	MAIN[21][29][5]	MAIN[31][29][5]
DRP[8] bit 12	MAIN[1][28][6]	MAIN[11][28][6]	MAIN[21][28][6]	MAIN[31][28][6]
DRP[8] bit 13	MAIN[1][29][6]	MAIN[11][29][6]	MAIN[21][29][6]	MAIN[31][29][6]
DRP[8] bit 14	MAIN[1][28][7]	MAIN[11][28][7]	MAIN[21][28][7]	MAIN[31][28][7]
DRP[8] bit 15	MAIN[1][29][7]	MAIN[11][29][7]	MAIN[21][29][7]	MAIN[31][29][7]
DRP[9] bit 0	MAIN[1][28][8]	MAIN[11][28][8]	MAIN[21][28][8]	MAIN[31][28][8]
DRP[9] bit 1	MAIN[1][29][8]	MAIN[11][29][8]	MAIN[21][29][8]	MAIN[31][29][8]
DRP[9] bit 2	MAIN[1][28][9]	MAIN[11][28][9]	MAIN[21][28][9]	MAIN[31][28][9]
DRP[9] bit 3	MAIN[1][29][9]	MAIN[11][29][9]	MAIN[21][29][9]	MAIN[31][29][9]
DRP[9] bit 4	MAIN[1][28][10]	MAIN[11][28][10]	MAIN[21][28][10]	MAIN[31][28][10]
DRP[9] bit 5	MAIN[1][29][10]	MAIN[11][29][10]	MAIN[21][29][10]	MAIN[31][29][10]
DRP[9] bit 6	MAIN[1][28][11]	MAIN[11][28][11]	MAIN[21][28][11]	MAIN[31][28][11]
DRP[9] bit 7	MAIN[1][29][11]	MAIN[11][29][11]	MAIN[21][29][11]	MAIN[31][29][11]
DRP[9] bit 8	MAIN[1][28][12]	MAIN[11][28][12]	MAIN[21][28][12]	MAIN[31][28][12]
DRP[9] bit 9	MAIN[1][29][12]	MAIN[11][29][12]	MAIN[21][29][12]	MAIN[31][29][12]
DRP[9] bit 10	MAIN[1][28][13]	MAIN[11][28][13]	MAIN[21][28][13]	MAIN[31][28][13]
DRP[9] bit 11	MAIN[1][29][13]	MAIN[11][29][13]	MAIN[21][29][13]	MAIN[31][29][13]
DRP[9] bit 12	MAIN[1][28][14]	MAIN[11][28][14]	MAIN[21][28][14]	MAIN[31][28][14]
DRP[9] bit 13	MAIN[1][29][14]	MAIN[11][29][14]	MAIN[21][29][14]	MAIN[31][29][14]
DRP[9] bit 14	MAIN[1][28][15]	MAIN[11][28][15]	MAIN[21][28][15]	MAIN[31][28][15]
DRP[9] bit 15	MAIN[1][29][15]	MAIN[11][29][15]	MAIN[21][29][15]	MAIN[31][29][15]
DRP[10] bit 0	MAIN[1][28][16]	MAIN[11][28][16]	MAIN[21][28][16]	MAIN[31][28][16]
DRP[10] bit 1	MAIN[1][29][16]	MAIN[11][29][16]	MAIN[21][29][16]	MAIN[31][29][16]
DRP[10] bit 2	MAIN[1][28][17]	MAIN[11][28][17]	MAIN[21][28][17]	MAIN[31][28][17]
DRP[10] bit 3	MAIN[1][29][17]	MAIN[11][29][17]	MAIN[21][29][17]	MAIN[31][29][17]
DRP[10] bit 4	MAIN[1][28][18]	MAIN[11][28][18]	MAIN[21][28][18]	MAIN[31][28][18]
DRP[10] bit 5	MAIN[1][29][18]	MAIN[11][29][18]	MAIN[21][29][18]	MAIN[31][29][18]
DRP[10] bit 6	MAIN[1][28][19]	MAIN[11][28][19]	MAIN[21][28][19]	MAIN[31][28][19]
DRP[10] bit 7	MAIN[1][29][19]	MAIN[11][29][19]	MAIN[21][29][19]	MAIN[31][29][19]
DRP[10] bit 8	MAIN[1][28][20]	MAIN[11][28][20]	MAIN[21][28][20]	MAIN[31][28][20]
DRP[10] bit 9	MAIN[1][29][20]	MAIN[11][29][20]	MAIN[21][29][20]	MAIN[31][29][20]
DRP[10] bit 10	MAIN[1][28][21]	MAIN[11][28][21]	MAIN[21][28][21]	MAIN[31][28][21]
DRP[10] bit 11	MAIN[1][29][21]	MAIN[11][29][21]	MAIN[21][29][21]	MAIN[31][29][21]
DRP[10] bit 12	MAIN[1][28][22]	MAIN[11][28][22]	MAIN[21][28][22]	MAIN[31][28][22]
DRP[10] bit 13	MAIN[1][29][22]	MAIN[11][29][22]	MAIN[21][29][22]	MAIN[31][29][22]
DRP[10] bit 14	MAIN[1][28][23]	MAIN[11][28][23]	MAIN[21][28][23]	MAIN[31][28][23]
DRP[10] bit 15	MAIN[1][29][23]	MAIN[11][29][23]	MAIN[21][29][23]	MAIN[31][29][23]
DRP[11] bit 0	MAIN[1][28][24]	MAIN[11][28][24]	MAIN[21][28][24]	MAIN[31][28][24]
DRP[11] bit 1	MAIN[1][29][24]	MAIN[11][29][24]	MAIN[21][29][24]	MAIN[31][29][24]
DRP[11] bit 2	MAIN[1][28][25]	MAIN[11][28][25]	MAIN[21][28][25]	MAIN[31][28][25]
DRP[11] bit 3	MAIN[1][29][25]	MAIN[11][29][25]	MAIN[21][29][25]	MAIN[31][29][25]
DRP[11] bit 4	MAIN[1][28][26]	MAIN[11][28][26]	MAIN[21][28][26]	MAIN[31][28][26]
DRP[11] bit 5	MAIN[1][29][26]	MAIN[11][29][26]	MAIN[21][29][26]	MAIN[31][29][26]
DRP[11] bit 6	MAIN[1][28][27]	MAIN[11][28][27]	MAIN[21][28][27]	MAIN[31][28][27]
DRP[11] bit 7	MAIN[1][29][27]	MAIN[11][29][27]	MAIN[21][29][27]	MAIN[31][29][27]
DRP[11] bit 8	MAIN[1][28][28]	MAIN[11][28][28]	MAIN[21][28][28]	MAIN[31][28][28]
DRP[11] bit 9	MAIN[1][29][28]	MAIN[11][29][28]	MAIN[21][29][28]	MAIN[31][29][28]
DRP[11] bit 10	MAIN[1][28][29]	MAIN[11][28][29]	MAIN[21][28][29]	MAIN[31][28][29]
DRP[11] bit 11	MAIN[1][29][29]	MAIN[11][29][29]	MAIN[21][29][29]	MAIN[31][29][29]
DRP[11] bit 12	MAIN[1][28][30]	MAIN[11][28][30]	MAIN[21][28][30]	MAIN[31][28][30]
DRP[11] bit 13	MAIN[1][29][30]	MAIN[11][29][30]	MAIN[21][29][30]	MAIN[31][29][30]
DRP[11] bit 14	MAIN[1][28][31]	MAIN[11][28][31]	MAIN[21][28][31]	MAIN[31][28][31]
DRP[11] bit 15	MAIN[1][29][31]	MAIN[11][29][31]	MAIN[21][29][31]	MAIN[31][29][31]
DRP[12] bit 0	MAIN[1][28][32]	MAIN[11][28][32]	MAIN[21][28][32]	MAIN[31][28][32]
DRP[12] bit 1	MAIN[1][29][32]	MAIN[11][29][32]	MAIN[21][29][32]	MAIN[31][29][32]
DRP[12] bit 2	MAIN[1][28][33]	MAIN[11][28][33]	MAIN[21][28][33]	MAIN[31][28][33]
DRP[12] bit 3	MAIN[1][29][33]	MAIN[11][29][33]	MAIN[21][29][33]	MAIN[31][29][33]
DRP[12] bit 4	MAIN[1][28][34]	MAIN[11][28][34]	MAIN[21][28][34]	MAIN[31][28][34]
DRP[12] bit 5	MAIN[1][29][34]	MAIN[11][29][34]	MAIN[21][29][34]	MAIN[31][29][34]
DRP[12] bit 6	MAIN[1][28][35]	MAIN[11][28][35]	MAIN[21][28][35]	MAIN[31][28][35]
DRP[12] bit 7	MAIN[1][29][35]	MAIN[11][29][35]	MAIN[21][29][35]	MAIN[31][29][35]
DRP[12] bit 8	MAIN[1][28][36]	MAIN[11][28][36]	MAIN[21][28][36]	MAIN[31][28][36]
DRP[12] bit 9	MAIN[1][29][36]	MAIN[11][29][36]	MAIN[21][29][36]	MAIN[31][29][36]
DRP[12] bit 10	MAIN[1][28][37]	MAIN[11][28][37]	MAIN[21][28][37]	MAIN[31][28][37]
DRP[12] bit 11	MAIN[1][29][37]	MAIN[11][29][37]	MAIN[21][29][37]	MAIN[31][29][37]
DRP[12] bit 12	MAIN[1][28][38]	MAIN[11][28][38]	MAIN[21][28][38]	MAIN[31][28][38]
DRP[12] bit 13	MAIN[1][29][38]	MAIN[11][29][38]	MAIN[21][29][38]	MAIN[31][29][38]
DRP[12] bit 14	MAIN[1][28][39]	MAIN[11][28][39]	MAIN[21][28][39]	MAIN[31][28][39]
DRP[12] bit 15	MAIN[1][29][39]	MAIN[11][29][39]	MAIN[21][29][39]	MAIN[31][29][39]
DRP[13] bit 0	MAIN[1][28][40]	MAIN[11][28][40]	MAIN[21][28][40]	MAIN[31][28][40]
DRP[13] bit 1	MAIN[1][29][40]	MAIN[11][29][40]	MAIN[21][29][40]	MAIN[31][29][40]
DRP[13] bit 2	MAIN[1][28][41]	MAIN[11][28][41]	MAIN[21][28][41]	MAIN[31][28][41]
DRP[13] bit 3	MAIN[1][29][41]	MAIN[11][29][41]	MAIN[21][29][41]	MAIN[31][29][41]
DRP[13] bit 4	MAIN[1][28][42]	MAIN[11][28][42]	MAIN[21][28][42]	MAIN[31][28][42]
DRP[13] bit 5	MAIN[1][29][42]	MAIN[11][29][42]	MAIN[21][29][42]	MAIN[31][29][42]
DRP[13] bit 6	MAIN[1][28][43]	MAIN[11][28][43]	MAIN[21][28][43]	MAIN[31][28][43]
DRP[13] bit 7	MAIN[1][29][43]	MAIN[11][29][43]	MAIN[21][29][43]	MAIN[31][29][43]
DRP[13] bit 8	MAIN[1][28][44]	MAIN[11][28][44]	MAIN[21][28][44]	MAIN[31][28][44]
DRP[13] bit 9	MAIN[1][29][44]	MAIN[11][29][44]	MAIN[21][29][44]	MAIN[31][29][44]
DRP[13] bit 10	MAIN[1][28][45]	MAIN[11][28][45]	MAIN[21][28][45]	MAIN[31][28][45]
DRP[13] bit 11	MAIN[1][29][45]	MAIN[11][29][45]	MAIN[21][29][45]	MAIN[31][29][45]
DRP[13] bit 12	MAIN[1][28][46]	MAIN[11][28][46]	MAIN[21][28][46]	MAIN[31][28][46]
DRP[13] bit 13	MAIN[1][29][46]	MAIN[11][29][46]	MAIN[21][29][46]	MAIN[31][29][46]
DRP[13] bit 14	MAIN[1][28][47]	MAIN[11][28][47]	MAIN[21][28][47]	MAIN[31][28][47]
DRP[13] bit 15	MAIN[1][29][47]	MAIN[11][29][47]	MAIN[21][29][47]	MAIN[31][29][47]
DRP[14] bit 0	MAIN[1][28][48]	MAIN[11][28][48]	MAIN[21][28][48]	MAIN[31][28][48]
DRP[14] bit 1	MAIN[1][29][48]	MAIN[11][29][48]	MAIN[21][29][48]	MAIN[31][29][48]
DRP[14] bit 2	MAIN[1][28][49]	MAIN[11][28][49]	MAIN[21][28][49]	MAIN[31][28][49]
DRP[14] bit 3	MAIN[1][29][49]	MAIN[11][29][49]	MAIN[21][29][49]	MAIN[31][29][49]
DRP[14] bit 4	MAIN[1][28][50]	MAIN[11][28][50]	MAIN[21][28][50]	MAIN[31][28][50]
DRP[14] bit 5	MAIN[1][29][50]	MAIN[11][29][50]	MAIN[21][29][50]	MAIN[31][29][50]
DRP[14] bit 6	MAIN[1][28][51]	MAIN[11][28][51]	MAIN[21][28][51]	MAIN[31][28][51]
DRP[14] bit 7	MAIN[1][29][51]	MAIN[11][29][51]	MAIN[21][29][51]	MAIN[31][29][51]
DRP[14] bit 8	MAIN[1][28][52]	MAIN[11][28][52]	MAIN[21][28][52]	MAIN[31][28][52]
DRP[14] bit 9	MAIN[1][29][52]	MAIN[11][29][52]	MAIN[21][29][52]	MAIN[31][29][52]
DRP[14] bit 10	MAIN[1][28][53]	MAIN[11][28][53]	MAIN[21][28][53]	MAIN[31][28][53]
DRP[14] bit 11	MAIN[1][29][53]	MAIN[11][29][53]	MAIN[21][29][53]	MAIN[31][29][53]
DRP[14] bit 12	MAIN[1][28][54]	MAIN[11][28][54]	MAIN[21][28][54]	MAIN[31][28][54]
DRP[14] bit 13	MAIN[1][29][54]	MAIN[11][29][54]	MAIN[21][29][54]	MAIN[31][29][54]
DRP[14] bit 14	MAIN[1][28][55]	MAIN[11][28][55]	MAIN[21][28][55]	MAIN[31][28][55]
DRP[14] bit 15	MAIN[1][29][55]	MAIN[11][29][55]	MAIN[21][29][55]	MAIN[31][29][55]
DRP[15] bit 0	MAIN[1][28][56]	MAIN[11][28][56]	MAIN[21][28][56]	MAIN[31][28][56]
DRP[15] bit 1	MAIN[1][29][56]	MAIN[11][29][56]	MAIN[21][29][56]	MAIN[31][29][56]
DRP[15] bit 2	MAIN[1][28][57]	MAIN[11][28][57]	MAIN[21][28][57]	MAIN[31][28][57]
DRP[15] bit 3	MAIN[1][29][57]	MAIN[11][29][57]	MAIN[21][29][57]	MAIN[31][29][57]
DRP[15] bit 4	MAIN[1][28][58]	MAIN[11][28][58]	MAIN[21][28][58]	MAIN[31][28][58]
DRP[15] bit 5	MAIN[1][29][58]	MAIN[11][29][58]	MAIN[21][29][58]	MAIN[31][29][58]
DRP[15] bit 6	MAIN[1][28][59]	MAIN[11][28][59]	MAIN[21][28][59]	MAIN[31][28][59]
DRP[15] bit 7	MAIN[1][29][59]	MAIN[11][29][59]	MAIN[21][29][59]	MAIN[31][29][59]
DRP[15] bit 8	MAIN[1][28][60]	MAIN[11][28][60]	MAIN[21][28][60]	MAIN[31][28][60]
DRP[15] bit 9	MAIN[1][29][60]	MAIN[11][29][60]	MAIN[21][29][60]	MAIN[31][29][60]
DRP[15] bit 10	MAIN[1][28][61]	MAIN[11][28][61]	MAIN[21][28][61]	MAIN[31][28][61]
DRP[15] bit 11	MAIN[1][29][61]	MAIN[11][29][61]	MAIN[21][29][61]	MAIN[31][29][61]
DRP[15] bit 12	MAIN[1][28][62]	MAIN[11][28][62]	MAIN[21][28][62]	MAIN[31][28][62]
DRP[15] bit 13	MAIN[1][29][62]	MAIN[11][29][62]	MAIN[21][29][62]	MAIN[31][29][62]
DRP[15] bit 14	MAIN[1][28][63]	MAIN[11][28][63]	MAIN[21][28][63]	MAIN[31][28][63]
DRP[15] bit 15	MAIN[1][29][63]	MAIN[11][29][63]	MAIN[21][29][63]	MAIN[31][29][63]
DRP[16] bit 0	MAIN[2][28][0]	MAIN[12][28][0]	MAIN[22][28][0]	MAIN[32][28][0]
DRP[16] bit 1	MAIN[2][29][0]	MAIN[12][29][0]	MAIN[22][29][0]	MAIN[32][29][0]
DRP[16] bit 2	MAIN[2][28][1]	MAIN[12][28][1]	MAIN[22][28][1]	MAIN[32][28][1]
DRP[16] bit 3	MAIN[2][29][1]	MAIN[12][29][1]	MAIN[22][29][1]	MAIN[32][29][1]
DRP[16] bit 4	MAIN[2][28][2]	MAIN[12][28][2]	MAIN[22][28][2]	MAIN[32][28][2]
DRP[16] bit 5	MAIN[2][29][2]	MAIN[12][29][2]	MAIN[22][29][2]	MAIN[32][29][2]
DRP[16] bit 6	MAIN[2][28][3]	MAIN[12][28][3]	MAIN[22][28][3]	MAIN[32][28][3]
DRP[16] bit 7	MAIN[2][29][3]	MAIN[12][29][3]	MAIN[22][29][3]	MAIN[32][29][3]
DRP[16] bit 8	MAIN[2][28][4]	MAIN[12][28][4]	MAIN[22][28][4]	MAIN[32][28][4]
DRP[16] bit 9	MAIN[2][29][4]	MAIN[12][29][4]	MAIN[22][29][4]	MAIN[32][29][4]
DRP[16] bit 10	MAIN[2][28][5]	MAIN[12][28][5]	MAIN[22][28][5]	MAIN[32][28][5]
DRP[16] bit 11	MAIN[2][29][5]	MAIN[12][29][5]	MAIN[22][29][5]	MAIN[32][29][5]
DRP[16] bit 12	MAIN[2][28][6]	MAIN[12][28][6]	MAIN[22][28][6]	MAIN[32][28][6]
DRP[16] bit 13	MAIN[2][29][6]	MAIN[12][29][6]	MAIN[22][29][6]	MAIN[32][29][6]
DRP[16] bit 14	MAIN[2][28][7]	MAIN[12][28][7]	MAIN[22][28][7]	MAIN[32][28][7]
DRP[16] bit 15	MAIN[2][29][7]	MAIN[12][29][7]	MAIN[22][29][7]	MAIN[32][29][7]
DRP[17] bit 0	MAIN[2][28][8]	MAIN[12][28][8]	MAIN[22][28][8]	MAIN[32][28][8]
DRP[17] bit 1	MAIN[2][29][8]	MAIN[12][29][8]	MAIN[22][29][8]	MAIN[32][29][8]
DRP[17] bit 2	MAIN[2][28][9]	MAIN[12][28][9]	MAIN[22][28][9]	MAIN[32][28][9]
DRP[17] bit 3	MAIN[2][29][9]	MAIN[12][29][9]	MAIN[22][29][9]	MAIN[32][29][9]
DRP[17] bit 4	MAIN[2][28][10]	MAIN[12][28][10]	MAIN[22][28][10]	MAIN[32][28][10]
DRP[17] bit 5	MAIN[2][29][10]	MAIN[12][29][10]	MAIN[22][29][10]	MAIN[32][29][10]
DRP[17] bit 6	MAIN[2][28][11]	MAIN[12][28][11]	MAIN[22][28][11]	MAIN[32][28][11]
DRP[17] bit 7	MAIN[2][29][11]	MAIN[12][29][11]	MAIN[22][29][11]	MAIN[32][29][11]
DRP[17] bit 8	MAIN[2][28][12]	MAIN[12][28][12]	MAIN[22][28][12]	MAIN[32][28][12]
DRP[17] bit 9	MAIN[2][29][12]	MAIN[12][29][12]	MAIN[22][29][12]	MAIN[32][29][12]
DRP[17] bit 10	MAIN[2][28][13]	MAIN[12][28][13]	MAIN[22][28][13]	MAIN[32][28][13]
DRP[17] bit 11	MAIN[2][29][13]	MAIN[12][29][13]	MAIN[22][29][13]	MAIN[32][29][13]
DRP[17] bit 12	MAIN[2][28][14]	MAIN[12][28][14]	MAIN[22][28][14]	MAIN[32][28][14]
DRP[17] bit 13	MAIN[2][29][14]	MAIN[12][29][14]	MAIN[22][29][14]	MAIN[32][29][14]
DRP[17] bit 14	MAIN[2][28][15]	MAIN[12][28][15]	MAIN[22][28][15]	MAIN[32][28][15]
DRP[17] bit 15	MAIN[2][29][15]	MAIN[12][29][15]	MAIN[22][29][15]	MAIN[32][29][15]
DRP[18] bit 0	MAIN[2][28][16]	MAIN[12][28][16]	MAIN[22][28][16]	MAIN[32][28][16]
DRP[18] bit 1	MAIN[2][29][16]	MAIN[12][29][16]	MAIN[22][29][16]	MAIN[32][29][16]
DRP[18] bit 2	MAIN[2][28][17]	MAIN[12][28][17]	MAIN[22][28][17]	MAIN[32][28][17]
DRP[18] bit 3	MAIN[2][29][17]	MAIN[12][29][17]	MAIN[22][29][17]	MAIN[32][29][17]
DRP[18] bit 4	MAIN[2][28][18]	MAIN[12][28][18]	MAIN[22][28][18]	MAIN[32][28][18]
DRP[18] bit 5	MAIN[2][29][18]	MAIN[12][29][18]	MAIN[22][29][18]	MAIN[32][29][18]
DRP[18] bit 6	MAIN[2][28][19]	MAIN[12][28][19]	MAIN[22][28][19]	MAIN[32][28][19]
DRP[18] bit 7	MAIN[2][29][19]	MAIN[12][29][19]	MAIN[22][29][19]	MAIN[32][29][19]
DRP[18] bit 8	MAIN[2][28][20]	MAIN[12][28][20]	MAIN[22][28][20]	MAIN[32][28][20]
DRP[18] bit 9	MAIN[2][29][20]	MAIN[12][29][20]	MAIN[22][29][20]	MAIN[32][29][20]
DRP[18] bit 10	MAIN[2][28][21]	MAIN[12][28][21]	MAIN[22][28][21]	MAIN[32][28][21]
DRP[18] bit 11	MAIN[2][29][21]	MAIN[12][29][21]	MAIN[22][29][21]	MAIN[32][29][21]
DRP[18] bit 12	MAIN[2][28][22]	MAIN[12][28][22]	MAIN[22][28][22]	MAIN[32][28][22]
DRP[18] bit 13	MAIN[2][29][22]	MAIN[12][29][22]	MAIN[22][29][22]	MAIN[32][29][22]
DRP[18] bit 14	MAIN[2][28][23]	MAIN[12][28][23]	MAIN[22][28][23]	MAIN[32][28][23]
DRP[18] bit 15	MAIN[2][29][23]	MAIN[12][29][23]	MAIN[22][29][23]	MAIN[32][29][23]
DRP[19] bit 0	MAIN[2][28][24]	MAIN[12][28][24]	MAIN[22][28][24]	MAIN[32][28][24]
DRP[19] bit 1	MAIN[2][29][24]	MAIN[12][29][24]	MAIN[22][29][24]	MAIN[32][29][24]
DRP[19] bit 2	MAIN[2][28][25]	MAIN[12][28][25]	MAIN[22][28][25]	MAIN[32][28][25]
DRP[19] bit 3	MAIN[2][29][25]	MAIN[12][29][25]	MAIN[22][29][25]	MAIN[32][29][25]
DRP[19] bit 4	MAIN[2][28][26]	MAIN[12][28][26]	MAIN[22][28][26]	MAIN[32][28][26]
DRP[19] bit 5	MAIN[2][29][26]	MAIN[12][29][26]	MAIN[22][29][26]	MAIN[32][29][26]
DRP[19] bit 6	MAIN[2][28][27]	MAIN[12][28][27]	MAIN[22][28][27]	MAIN[32][28][27]
DRP[19] bit 7	MAIN[2][29][27]	MAIN[12][29][27]	MAIN[22][29][27]	MAIN[32][29][27]
DRP[19] bit 8	MAIN[2][28][28]	MAIN[12][28][28]	MAIN[22][28][28]	MAIN[32][28][28]
DRP[19] bit 9	MAIN[2][29][28]	MAIN[12][29][28]	MAIN[22][29][28]	MAIN[32][29][28]
DRP[19] bit 10	MAIN[2][28][29]	MAIN[12][28][29]	MAIN[22][28][29]	MAIN[32][28][29]
DRP[19] bit 11	MAIN[2][29][29]	MAIN[12][29][29]	MAIN[22][29][29]	MAIN[32][29][29]
DRP[19] bit 12	MAIN[2][28][30]	MAIN[12][28][30]	MAIN[22][28][30]	MAIN[32][28][30]
DRP[19] bit 13	MAIN[2][29][30]	MAIN[12][29][30]	MAIN[22][29][30]	MAIN[32][29][30]
DRP[19] bit 14	MAIN[2][28][31]	MAIN[12][28][31]	MAIN[22][28][31]	MAIN[32][28][31]
DRP[19] bit 15	MAIN[2][29][31]	MAIN[12][29][31]	MAIN[22][29][31]	MAIN[32][29][31]
DRP[20] bit 0	MAIN[2][28][32]	MAIN[12][28][32]	MAIN[22][28][32]	MAIN[32][28][32]
DRP[20] bit 1	MAIN[2][29][32]	MAIN[12][29][32]	MAIN[22][29][32]	MAIN[32][29][32]
DRP[20] bit 2	MAIN[2][28][33]	MAIN[12][28][33]	MAIN[22][28][33]	MAIN[32][28][33]
DRP[20] bit 3	MAIN[2][29][33]	MAIN[12][29][33]	MAIN[22][29][33]	MAIN[32][29][33]
DRP[20] bit 4	MAIN[2][28][34]	MAIN[12][28][34]	MAIN[22][28][34]	MAIN[32][28][34]
DRP[20] bit 5	MAIN[2][29][34]	MAIN[12][29][34]	MAIN[22][29][34]	MAIN[32][29][34]
DRP[20] bit 6	MAIN[2][28][35]	MAIN[12][28][35]	MAIN[22][28][35]	MAIN[32][28][35]
DRP[20] bit 7	MAIN[2][29][35]	MAIN[12][29][35]	MAIN[22][29][35]	MAIN[32][29][35]
DRP[20] bit 8	MAIN[2][28][36]	MAIN[12][28][36]	MAIN[22][28][36]	MAIN[32][28][36]
DRP[20] bit 9	MAIN[2][29][36]	MAIN[12][29][36]	MAIN[22][29][36]	MAIN[32][29][36]
DRP[20] bit 10	MAIN[2][28][37]	MAIN[12][28][37]	MAIN[22][28][37]	MAIN[32][28][37]
DRP[20] bit 11	MAIN[2][29][37]	MAIN[12][29][37]	MAIN[22][29][37]	MAIN[32][29][37]
DRP[20] bit 12	MAIN[2][28][38]	MAIN[12][28][38]	MAIN[22][28][38]	MAIN[32][28][38]
DRP[20] bit 13	MAIN[2][29][38]	MAIN[12][29][38]	MAIN[22][29][38]	MAIN[32][29][38]
DRP[20] bit 14	MAIN[2][28][39]	MAIN[12][28][39]	MAIN[22][28][39]	MAIN[32][28][39]
DRP[20] bit 15	MAIN[2][29][39]	MAIN[12][29][39]	MAIN[22][29][39]	MAIN[32][29][39]
DRP[21] bit 0	MAIN[2][28][40]	MAIN[12][28][40]	MAIN[22][28][40]	MAIN[32][28][40]
DRP[21] bit 1	MAIN[2][29][40]	MAIN[12][29][40]	MAIN[22][29][40]	MAIN[32][29][40]
DRP[21] bit 2	MAIN[2][28][41]	MAIN[12][28][41]	MAIN[22][28][41]	MAIN[32][28][41]
DRP[21] bit 3	MAIN[2][29][41]	MAIN[12][29][41]	MAIN[22][29][41]	MAIN[32][29][41]
DRP[21] bit 4	MAIN[2][28][42]	MAIN[12][28][42]	MAIN[22][28][42]	MAIN[32][28][42]
DRP[21] bit 5	MAIN[2][29][42]	MAIN[12][29][42]	MAIN[22][29][42]	MAIN[32][29][42]
DRP[21] bit 6	MAIN[2][28][43]	MAIN[12][28][43]	MAIN[22][28][43]	MAIN[32][28][43]
DRP[21] bit 7	MAIN[2][29][43]	MAIN[12][29][43]	MAIN[22][29][43]	MAIN[32][29][43]
DRP[21] bit 8	MAIN[2][28][44]	MAIN[12][28][44]	MAIN[22][28][44]	MAIN[32][28][44]
DRP[21] bit 9	MAIN[2][29][44]	MAIN[12][29][44]	MAIN[22][29][44]	MAIN[32][29][44]
DRP[21] bit 10	MAIN[2][28][45]	MAIN[12][28][45]	MAIN[22][28][45]	MAIN[32][28][45]
DRP[21] bit 11	MAIN[2][29][45]	MAIN[12][29][45]	MAIN[22][29][45]	MAIN[32][29][45]
DRP[21] bit 12	MAIN[2][28][46]	MAIN[12][28][46]	MAIN[22][28][46]	MAIN[32][28][46]
DRP[21] bit 13	MAIN[2][29][46]	MAIN[12][29][46]	MAIN[22][29][46]	MAIN[32][29][46]
DRP[21] bit 14	MAIN[2][28][47]	MAIN[12][28][47]	MAIN[22][28][47]	MAIN[32][28][47]
DRP[21] bit 15	MAIN[2][29][47]	MAIN[12][29][47]	MAIN[22][29][47]	MAIN[32][29][47]
DRP[22] bit 0	MAIN[2][28][48]	MAIN[12][28][48]	MAIN[22][28][48]	MAIN[32][28][48]
DRP[22] bit 1	MAIN[2][29][48]	MAIN[12][29][48]	MAIN[22][29][48]	MAIN[32][29][48]
DRP[22] bit 2	MAIN[2][28][49]	MAIN[12][28][49]	MAIN[22][28][49]	MAIN[32][28][49]
DRP[22] bit 3	MAIN[2][29][49]	MAIN[12][29][49]	MAIN[22][29][49]	MAIN[32][29][49]
DRP[22] bit 4	MAIN[2][28][50]	MAIN[12][28][50]	MAIN[22][28][50]	MAIN[32][28][50]
DRP[22] bit 5	MAIN[2][29][50]	MAIN[12][29][50]	MAIN[22][29][50]	MAIN[32][29][50]
DRP[22] bit 6	MAIN[2][28][51]	MAIN[12][28][51]	MAIN[22][28][51]	MAIN[32][28][51]
DRP[22] bit 7	MAIN[2][29][51]	MAIN[12][29][51]	MAIN[22][29][51]	MAIN[32][29][51]
DRP[22] bit 8	MAIN[2][28][52]	MAIN[12][28][52]	MAIN[22][28][52]	MAIN[32][28][52]
DRP[22] bit 9	MAIN[2][29][52]	MAIN[12][29][52]	MAIN[22][29][52]	MAIN[32][29][52]
DRP[22] bit 10	MAIN[2][28][53]	MAIN[12][28][53]	MAIN[22][28][53]	MAIN[32][28][53]
DRP[22] bit 11	MAIN[2][29][53]	MAIN[12][29][53]	MAIN[22][29][53]	MAIN[32][29][53]
DRP[22] bit 12	MAIN[2][28][54]	MAIN[12][28][54]	MAIN[22][28][54]	MAIN[32][28][54]
DRP[22] bit 13	MAIN[2][29][54]	MAIN[12][29][54]	MAIN[22][29][54]	MAIN[32][29][54]
DRP[22] bit 14	MAIN[2][28][55]	MAIN[12][28][55]	MAIN[22][28][55]	MAIN[32][28][55]
DRP[22] bit 15	MAIN[2][29][55]	MAIN[12][29][55]	MAIN[22][29][55]	MAIN[32][29][55]
DRP[23] bit 0	MAIN[2][28][56]	MAIN[12][28][56]	MAIN[22][28][56]	MAIN[32][28][56]
DRP[23] bit 1	MAIN[2][29][56]	MAIN[12][29][56]	MAIN[22][29][56]	MAIN[32][29][56]
DRP[23] bit 2	MAIN[2][28][57]	MAIN[12][28][57]	MAIN[22][28][57]	MAIN[32][28][57]
DRP[23] bit 3	MAIN[2][29][57]	MAIN[12][29][57]	MAIN[22][29][57]	MAIN[32][29][57]
DRP[23] bit 4	MAIN[2][28][58]	MAIN[12][28][58]	MAIN[22][28][58]	MAIN[32][28][58]
DRP[23] bit 5	MAIN[2][29][58]	MAIN[12][29][58]	MAIN[22][29][58]	MAIN[32][29][58]
DRP[23] bit 6	MAIN[2][28][59]	MAIN[12][28][59]	MAIN[22][28][59]	MAIN[32][28][59]
DRP[23] bit 7	MAIN[2][29][59]	MAIN[12][29][59]	MAIN[22][29][59]	MAIN[32][29][59]
DRP[23] bit 8	MAIN[2][28][60]	MAIN[12][28][60]	MAIN[22][28][60]	MAIN[32][28][60]
DRP[23] bit 9	MAIN[2][29][60]	MAIN[12][29][60]	MAIN[22][29][60]	MAIN[32][29][60]
DRP[23] bit 10	MAIN[2][28][61]	MAIN[12][28][61]	MAIN[22][28][61]	MAIN[32][28][61]
DRP[23] bit 11	MAIN[2][29][61]	MAIN[12][29][61]	MAIN[22][29][61]	MAIN[32][29][61]
DRP[23] bit 12	MAIN[2][28][62]	MAIN[12][28][62]	MAIN[22][28][62]	MAIN[32][28][62]
DRP[23] bit 13	MAIN[2][29][62]	MAIN[12][29][62]	MAIN[22][29][62]	MAIN[32][29][62]
DRP[23] bit 14	MAIN[2][28][63]	MAIN[12][28][63]	MAIN[22][28][63]	MAIN[32][28][63]
DRP[23] bit 15	MAIN[2][29][63]	MAIN[12][29][63]	MAIN[22][29][63]	MAIN[32][29][63]
DRP[24] bit 0	MAIN[3][28][0]	MAIN[13][28][0]	MAIN[23][28][0]	MAIN[33][28][0]
DRP[24] bit 1	MAIN[3][29][0]	MAIN[13][29][0]	MAIN[23][29][0]	MAIN[33][29][0]
DRP[24] bit 2	MAIN[3][28][1]	MAIN[13][28][1]	MAIN[23][28][1]	MAIN[33][28][1]
DRP[24] bit 3	MAIN[3][29][1]	MAIN[13][29][1]	MAIN[23][29][1]	MAIN[33][29][1]
DRP[24] bit 4	MAIN[3][28][2]	MAIN[13][28][2]	MAIN[23][28][2]	MAIN[33][28][2]
DRP[24] bit 5	MAIN[3][29][2]	MAIN[13][29][2]	MAIN[23][29][2]	MAIN[33][29][2]
DRP[24] bit 6	MAIN[3][28][3]	MAIN[13][28][3]	MAIN[23][28][3]	MAIN[33][28][3]
DRP[24] bit 7	MAIN[3][29][3]	MAIN[13][29][3]	MAIN[23][29][3]	MAIN[33][29][3]
DRP[24] bit 8	MAIN[3][28][4]	MAIN[13][28][4]	MAIN[23][28][4]	MAIN[33][28][4]
DRP[24] bit 9	MAIN[3][29][4]	MAIN[13][29][4]	MAIN[23][29][4]	MAIN[33][29][4]
DRP[24] bit 10	MAIN[3][28][5]	MAIN[13][28][5]	MAIN[23][28][5]	MAIN[33][28][5]
DRP[24] bit 11	MAIN[3][29][5]	MAIN[13][29][5]	MAIN[23][29][5]	MAIN[33][29][5]
DRP[24] bit 12	MAIN[3][28][6]	MAIN[13][28][6]	MAIN[23][28][6]	MAIN[33][28][6]
DRP[24] bit 13	MAIN[3][29][6]	MAIN[13][29][6]	MAIN[23][29][6]	MAIN[33][29][6]
DRP[24] bit 14	MAIN[3][28][7]	MAIN[13][28][7]	MAIN[23][28][7]	MAIN[33][28][7]
DRP[24] bit 15	MAIN[3][29][7]	MAIN[13][29][7]	MAIN[23][29][7]	MAIN[33][29][7]
DRP[25] bit 0	MAIN[3][28][8]	MAIN[13][28][8]	MAIN[23][28][8]	MAIN[33][28][8]
DRP[25] bit 1	MAIN[3][29][8]	MAIN[13][29][8]	MAIN[23][29][8]	MAIN[33][29][8]
DRP[25] bit 2	MAIN[3][28][9]	MAIN[13][28][9]	MAIN[23][28][9]	MAIN[33][28][9]
DRP[25] bit 3	MAIN[3][29][9]	MAIN[13][29][9]	MAIN[23][29][9]	MAIN[33][29][9]
DRP[25] bit 4	MAIN[3][28][10]	MAIN[13][28][10]	MAIN[23][28][10]	MAIN[33][28][10]
DRP[25] bit 5	MAIN[3][29][10]	MAIN[13][29][10]	MAIN[23][29][10]	MAIN[33][29][10]
DRP[25] bit 6	MAIN[3][28][11]	MAIN[13][28][11]	MAIN[23][28][11]	MAIN[33][28][11]
DRP[25] bit 7	MAIN[3][29][11]	MAIN[13][29][11]	MAIN[23][29][11]	MAIN[33][29][11]
DRP[25] bit 8	MAIN[3][28][12]	MAIN[13][28][12]	MAIN[23][28][12]	MAIN[33][28][12]
DRP[25] bit 9	MAIN[3][29][12]	MAIN[13][29][12]	MAIN[23][29][12]	MAIN[33][29][12]
DRP[25] bit 10	MAIN[3][28][13]	MAIN[13][28][13]	MAIN[23][28][13]	MAIN[33][28][13]
DRP[25] bit 11	MAIN[3][29][13]	MAIN[13][29][13]	MAIN[23][29][13]	MAIN[33][29][13]
DRP[25] bit 12	MAIN[3][28][14]	MAIN[13][28][14]	MAIN[23][28][14]	MAIN[33][28][14]
DRP[25] bit 13	MAIN[3][29][14]	MAIN[13][29][14]	MAIN[23][29][14]	MAIN[33][29][14]
DRP[25] bit 14	MAIN[3][28][15]	MAIN[13][28][15]	MAIN[23][28][15]	MAIN[33][28][15]
DRP[25] bit 15	MAIN[3][29][15]	MAIN[13][29][15]	MAIN[23][29][15]	MAIN[33][29][15]
DRP[26] bit 0	MAIN[3][28][16]	MAIN[13][28][16]	MAIN[23][28][16]	MAIN[33][28][16]
DRP[26] bit 1	MAIN[3][29][16]	MAIN[13][29][16]	MAIN[23][29][16]	MAIN[33][29][16]
DRP[26] bit 2	MAIN[3][28][17]	MAIN[13][28][17]	MAIN[23][28][17]	MAIN[33][28][17]
DRP[26] bit 3	MAIN[3][29][17]	MAIN[13][29][17]	MAIN[23][29][17]	MAIN[33][29][17]
DRP[26] bit 4	MAIN[3][28][18]	MAIN[13][28][18]	MAIN[23][28][18]	MAIN[33][28][18]
DRP[26] bit 5	MAIN[3][29][18]	MAIN[13][29][18]	MAIN[23][29][18]	MAIN[33][29][18]
DRP[26] bit 6	MAIN[3][28][19]	MAIN[13][28][19]	MAIN[23][28][19]	MAIN[33][28][19]
DRP[26] bit 7	MAIN[3][29][19]	MAIN[13][29][19]	MAIN[23][29][19]	MAIN[33][29][19]
DRP[26] bit 8	MAIN[3][28][20]	MAIN[13][28][20]	MAIN[23][28][20]	MAIN[33][28][20]
DRP[26] bit 9	MAIN[3][29][20]	MAIN[13][29][20]	MAIN[23][29][20]	MAIN[33][29][20]
DRP[26] bit 10	MAIN[3][28][21]	MAIN[13][28][21]	MAIN[23][28][21]	MAIN[33][28][21]
DRP[26] bit 11	MAIN[3][29][21]	MAIN[13][29][21]	MAIN[23][29][21]	MAIN[33][29][21]
DRP[26] bit 12	MAIN[3][28][22]	MAIN[13][28][22]	MAIN[23][28][22]	MAIN[33][28][22]
DRP[26] bit 13	MAIN[3][29][22]	MAIN[13][29][22]	MAIN[23][29][22]	MAIN[33][29][22]
DRP[26] bit 14	MAIN[3][28][23]	MAIN[13][28][23]	MAIN[23][28][23]	MAIN[33][28][23]
DRP[26] bit 15	MAIN[3][29][23]	MAIN[13][29][23]	MAIN[23][29][23]	MAIN[33][29][23]
DRP[27] bit 0	MAIN[3][28][24]	MAIN[13][28][24]	MAIN[23][28][24]	MAIN[33][28][24]
DRP[27] bit 1	MAIN[3][29][24]	MAIN[13][29][24]	MAIN[23][29][24]	MAIN[33][29][24]
DRP[27] bit 2	MAIN[3][28][25]	MAIN[13][28][25]	MAIN[23][28][25]	MAIN[33][28][25]
DRP[27] bit 3	MAIN[3][29][25]	MAIN[13][29][25]	MAIN[23][29][25]	MAIN[33][29][25]
DRP[27] bit 4	MAIN[3][28][26]	MAIN[13][28][26]	MAIN[23][28][26]	MAIN[33][28][26]
DRP[27] bit 5	MAIN[3][29][26]	MAIN[13][29][26]	MAIN[23][29][26]	MAIN[33][29][26]
DRP[27] bit 6	MAIN[3][28][27]	MAIN[13][28][27]	MAIN[23][28][27]	MAIN[33][28][27]
DRP[27] bit 7	MAIN[3][29][27]	MAIN[13][29][27]	MAIN[23][29][27]	MAIN[33][29][27]
DRP[27] bit 8	MAIN[3][28][28]	MAIN[13][28][28]	MAIN[23][28][28]	MAIN[33][28][28]
DRP[27] bit 9	MAIN[3][29][28]	MAIN[13][29][28]	MAIN[23][29][28]	MAIN[33][29][28]
DRP[27] bit 10	MAIN[3][28][29]	MAIN[13][28][29]	MAIN[23][28][29]	MAIN[33][28][29]
DRP[27] bit 11	MAIN[3][29][29]	MAIN[13][29][29]	MAIN[23][29][29]	MAIN[33][29][29]
DRP[27] bit 12	MAIN[3][28][30]	MAIN[13][28][30]	MAIN[23][28][30]	MAIN[33][28][30]
DRP[27] bit 13	MAIN[3][29][30]	MAIN[13][29][30]	MAIN[23][29][30]	MAIN[33][29][30]
DRP[27] bit 14	MAIN[3][28][31]	MAIN[13][28][31]	MAIN[23][28][31]	MAIN[33][28][31]
DRP[27] bit 15	MAIN[3][29][31]	MAIN[13][29][31]	MAIN[23][29][31]	MAIN[33][29][31]
DRP[28] bit 0	MAIN[3][28][32]	MAIN[13][28][32]	MAIN[23][28][32]	MAIN[33][28][32]
DRP[28] bit 1	MAIN[3][29][32]	MAIN[13][29][32]	MAIN[23][29][32]	MAIN[33][29][32]
DRP[28] bit 2	MAIN[3][28][33]	MAIN[13][28][33]	MAIN[23][28][33]	MAIN[33][28][33]
DRP[28] bit 3	MAIN[3][29][33]	MAIN[13][29][33]	MAIN[23][29][33]	MAIN[33][29][33]
DRP[28] bit 4	MAIN[3][28][34]	MAIN[13][28][34]	MAIN[23][28][34]	MAIN[33][28][34]
DRP[28] bit 5	MAIN[3][29][34]	MAIN[13][29][34]	MAIN[23][29][34]	MAIN[33][29][34]
DRP[28] bit 6	MAIN[3][28][35]	MAIN[13][28][35]	MAIN[23][28][35]	MAIN[33][28][35]
DRP[28] bit 7	MAIN[3][29][35]	MAIN[13][29][35]	MAIN[23][29][35]	MAIN[33][29][35]
DRP[28] bit 8	MAIN[3][28][36]	MAIN[13][28][36]	MAIN[23][28][36]	MAIN[33][28][36]
DRP[28] bit 9	MAIN[3][29][36]	MAIN[13][29][36]	MAIN[23][29][36]	MAIN[33][29][36]
DRP[28] bit 10	MAIN[3][28][37]	MAIN[13][28][37]	MAIN[23][28][37]	MAIN[33][28][37]
DRP[28] bit 11	MAIN[3][29][37]	MAIN[13][29][37]	MAIN[23][29][37]	MAIN[33][29][37]
DRP[28] bit 12	MAIN[3][28][38]	MAIN[13][28][38]	MAIN[23][28][38]	MAIN[33][28][38]
DRP[28] bit 13	MAIN[3][29][38]	MAIN[13][29][38]	MAIN[23][29][38]	MAIN[33][29][38]
DRP[28] bit 14	MAIN[3][28][39]	MAIN[13][28][39]	MAIN[23][28][39]	MAIN[33][28][39]
DRP[28] bit 15	MAIN[3][29][39]	MAIN[13][29][39]	MAIN[23][29][39]	MAIN[33][29][39]
DRP[29] bit 0	MAIN[3][28][40]	MAIN[13][28][40]	MAIN[23][28][40]	MAIN[33][28][40]
DRP[29] bit 1	MAIN[3][29][40]	MAIN[13][29][40]	MAIN[23][29][40]	MAIN[33][29][40]
DRP[29] bit 2	MAIN[3][28][41]	MAIN[13][28][41]	MAIN[23][28][41]	MAIN[33][28][41]
DRP[29] bit 3	MAIN[3][29][41]	MAIN[13][29][41]	MAIN[23][29][41]	MAIN[33][29][41]
DRP[29] bit 4	MAIN[3][28][42]	MAIN[13][28][42]	MAIN[23][28][42]	MAIN[33][28][42]
DRP[29] bit 5	MAIN[3][29][42]	MAIN[13][29][42]	MAIN[23][29][42]	MAIN[33][29][42]
DRP[29] bit 6	MAIN[3][28][43]	MAIN[13][28][43]	MAIN[23][28][43]	MAIN[33][28][43]
DRP[29] bit 7	MAIN[3][29][43]	MAIN[13][29][43]	MAIN[23][29][43]	MAIN[33][29][43]
DRP[29] bit 8	MAIN[3][28][44]	MAIN[13][28][44]	MAIN[23][28][44]	MAIN[33][28][44]
DRP[29] bit 9	MAIN[3][29][44]	MAIN[13][29][44]	MAIN[23][29][44]	MAIN[33][29][44]
DRP[29] bit 10	MAIN[3][28][45]	MAIN[13][28][45]	MAIN[23][28][45]	MAIN[33][28][45]
DRP[29] bit 11	MAIN[3][29][45]	MAIN[13][29][45]	MAIN[23][29][45]	MAIN[33][29][45]
DRP[29] bit 12	MAIN[3][28][46]	MAIN[13][28][46]	MAIN[23][28][46]	MAIN[33][28][46]
DRP[29] bit 13	MAIN[3][29][46]	MAIN[13][29][46]	MAIN[23][29][46]	MAIN[33][29][46]
DRP[29] bit 14	MAIN[3][28][47]	MAIN[13][28][47]	MAIN[23][28][47]	MAIN[33][28][47]
DRP[29] bit 15	MAIN[3][29][47]	MAIN[13][29][47]	MAIN[23][29][47]	MAIN[33][29][47]
DRP[30] bit 0	MAIN[3][28][48]	MAIN[13][28][48]	MAIN[23][28][48]	MAIN[33][28][48]
DRP[30] bit 1	MAIN[3][29][48]	MAIN[13][29][48]	MAIN[23][29][48]	MAIN[33][29][48]
DRP[30] bit 2	MAIN[3][28][49]	MAIN[13][28][49]	MAIN[23][28][49]	MAIN[33][28][49]
DRP[30] bit 3	MAIN[3][29][49]	MAIN[13][29][49]	MAIN[23][29][49]	MAIN[33][29][49]
DRP[30] bit 4	MAIN[3][28][50]	MAIN[13][28][50]	MAIN[23][28][50]	MAIN[33][28][50]
DRP[30] bit 5	MAIN[3][29][50]	MAIN[13][29][50]	MAIN[23][29][50]	MAIN[33][29][50]
DRP[30] bit 6	MAIN[3][28][51]	MAIN[13][28][51]	MAIN[23][28][51]	MAIN[33][28][51]
DRP[30] bit 7	MAIN[3][29][51]	MAIN[13][29][51]	MAIN[23][29][51]	MAIN[33][29][51]
DRP[30] bit 8	MAIN[3][28][52]	MAIN[13][28][52]	MAIN[23][28][52]	MAIN[33][28][52]
DRP[30] bit 9	MAIN[3][29][52]	MAIN[13][29][52]	MAIN[23][29][52]	MAIN[33][29][52]
DRP[30] bit 10	MAIN[3][28][53]	MAIN[13][28][53]	MAIN[23][28][53]	MAIN[33][28][53]
DRP[30] bit 11	MAIN[3][29][53]	MAIN[13][29][53]	MAIN[23][29][53]	MAIN[33][29][53]
DRP[30] bit 12	MAIN[3][28][54]	MAIN[13][28][54]	MAIN[23][28][54]	MAIN[33][28][54]
DRP[30] bit 13	MAIN[3][29][54]	MAIN[13][29][54]	MAIN[23][29][54]	MAIN[33][29][54]
DRP[30] bit 14	MAIN[3][28][55]	MAIN[13][28][55]	MAIN[23][28][55]	MAIN[33][28][55]
DRP[30] bit 15	MAIN[3][29][55]	MAIN[13][29][55]	MAIN[23][29][55]	MAIN[33][29][55]
DRP[31] bit 0	MAIN[3][28][56]	MAIN[13][28][56]	MAIN[23][28][56]	MAIN[33][28][56]
DRP[31] bit 1	MAIN[3][29][56]	MAIN[13][29][56]	MAIN[23][29][56]	MAIN[33][29][56]
DRP[31] bit 2	MAIN[3][28][57]	MAIN[13][28][57]	MAIN[23][28][57]	MAIN[33][28][57]
DRP[31] bit 3	MAIN[3][29][57]	MAIN[13][29][57]	MAIN[23][29][57]	MAIN[33][29][57]
DRP[31] bit 4	MAIN[3][28][58]	MAIN[13][28][58]	MAIN[23][28][58]	MAIN[33][28][58]
DRP[31] bit 5	MAIN[3][29][58]	MAIN[13][29][58]	MAIN[23][29][58]	MAIN[33][29][58]
DRP[31] bit 6	MAIN[3][28][59]	MAIN[13][28][59]	MAIN[23][28][59]	MAIN[33][28][59]
DRP[31] bit 7	MAIN[3][29][59]	MAIN[13][29][59]	MAIN[23][29][59]	MAIN[33][29][59]
DRP[31] bit 8	MAIN[3][28][60]	MAIN[13][28][60]	MAIN[23][28][60]	MAIN[33][28][60]
DRP[31] bit 9	MAIN[3][29][60]	MAIN[13][29][60]	MAIN[23][29][60]	MAIN[33][29][60]
DRP[31] bit 10	MAIN[3][28][61]	MAIN[13][28][61]	MAIN[23][28][61]	MAIN[33][28][61]
DRP[31] bit 11	MAIN[3][29][61]	MAIN[13][29][61]	MAIN[23][29][61]	MAIN[33][29][61]
DRP[31] bit 12	MAIN[3][28][62]	MAIN[13][28][62]	MAIN[23][28][62]	MAIN[33][28][62]
DRP[31] bit 13	MAIN[3][29][62]	MAIN[13][29][62]	MAIN[23][29][62]	MAIN[33][29][62]
DRP[31] bit 14	MAIN[3][28][63]	MAIN[13][28][63]	MAIN[23][28][63]	MAIN[33][28][63]
DRP[31] bit 15	MAIN[3][29][63]	MAIN[13][29][63]	MAIN[23][29][63]	MAIN[33][29][63]
DRP[32] bit 0	MAIN[4][28][0]	MAIN[14][28][0]	MAIN[24][28][0]	MAIN[34][28][0]
DRP[32] bit 1	MAIN[4][29][0]	MAIN[14][29][0]	MAIN[24][29][0]	MAIN[34][29][0]
DRP[32] bit 2	MAIN[4][28][1]	MAIN[14][28][1]	MAIN[24][28][1]	MAIN[34][28][1]
DRP[32] bit 3	MAIN[4][29][1]	MAIN[14][29][1]	MAIN[24][29][1]	MAIN[34][29][1]
DRP[32] bit 4	MAIN[4][28][2]	MAIN[14][28][2]	MAIN[24][28][2]	MAIN[34][28][2]
DRP[32] bit 5	MAIN[4][29][2]	MAIN[14][29][2]	MAIN[24][29][2]	MAIN[34][29][2]
DRP[32] bit 6	MAIN[4][28][3]	MAIN[14][28][3]	MAIN[24][28][3]	MAIN[34][28][3]
DRP[32] bit 7	MAIN[4][29][3]	MAIN[14][29][3]	MAIN[24][29][3]	MAIN[34][29][3]
DRP[32] bit 8	MAIN[4][28][4]	MAIN[14][28][4]	MAIN[24][28][4]	MAIN[34][28][4]
DRP[32] bit 9	MAIN[4][29][4]	MAIN[14][29][4]	MAIN[24][29][4]	MAIN[34][29][4]
DRP[32] bit 10	MAIN[4][28][5]	MAIN[14][28][5]	MAIN[24][28][5]	MAIN[34][28][5]
DRP[32] bit 11	MAIN[4][29][5]	MAIN[14][29][5]	MAIN[24][29][5]	MAIN[34][29][5]
DRP[32] bit 12	MAIN[4][28][6]	MAIN[14][28][6]	MAIN[24][28][6]	MAIN[34][28][6]
DRP[32] bit 13	MAIN[4][29][6]	MAIN[14][29][6]	MAIN[24][29][6]	MAIN[34][29][6]
DRP[32] bit 14	MAIN[4][28][7]	MAIN[14][28][7]	MAIN[24][28][7]	MAIN[34][28][7]
DRP[32] bit 15	MAIN[4][29][7]	MAIN[14][29][7]	MAIN[24][29][7]	MAIN[34][29][7]
DRP[33] bit 0	MAIN[4][28][8]	MAIN[14][28][8]	MAIN[24][28][8]	MAIN[34][28][8]
DRP[33] bit 1	MAIN[4][29][8]	MAIN[14][29][8]	MAIN[24][29][8]	MAIN[34][29][8]
DRP[33] bit 2	MAIN[4][28][9]	MAIN[14][28][9]	MAIN[24][28][9]	MAIN[34][28][9]
DRP[33] bit 3	MAIN[4][29][9]	MAIN[14][29][9]	MAIN[24][29][9]	MAIN[34][29][9]
DRP[33] bit 4	MAIN[4][28][10]	MAIN[14][28][10]	MAIN[24][28][10]	MAIN[34][28][10]
DRP[33] bit 5	MAIN[4][29][10]	MAIN[14][29][10]	MAIN[24][29][10]	MAIN[34][29][10]
DRP[33] bit 6	MAIN[4][28][11]	MAIN[14][28][11]	MAIN[24][28][11]	MAIN[34][28][11]
DRP[33] bit 7	MAIN[4][29][11]	MAIN[14][29][11]	MAIN[24][29][11]	MAIN[34][29][11]
DRP[33] bit 8	MAIN[4][28][12]	MAIN[14][28][12]	MAIN[24][28][12]	MAIN[34][28][12]
DRP[33] bit 9	MAIN[4][29][12]	MAIN[14][29][12]	MAIN[24][29][12]	MAIN[34][29][12]
DRP[33] bit 10	MAIN[4][28][13]	MAIN[14][28][13]	MAIN[24][28][13]	MAIN[34][28][13]
DRP[33] bit 11	MAIN[4][29][13]	MAIN[14][29][13]	MAIN[24][29][13]	MAIN[34][29][13]
DRP[33] bit 12	MAIN[4][28][14]	MAIN[14][28][14]	MAIN[24][28][14]	MAIN[34][28][14]
DRP[33] bit 13	MAIN[4][29][14]	MAIN[14][29][14]	MAIN[24][29][14]	MAIN[34][29][14]
DRP[33] bit 14	MAIN[4][28][15]	MAIN[14][28][15]	MAIN[24][28][15]	MAIN[34][28][15]
DRP[33] bit 15	MAIN[4][29][15]	MAIN[14][29][15]	MAIN[24][29][15]	MAIN[34][29][15]
DRP[34] bit 0	MAIN[4][28][16]	MAIN[14][28][16]	MAIN[24][28][16]	MAIN[34][28][16]
DRP[34] bit 1	MAIN[4][29][16]	MAIN[14][29][16]	MAIN[24][29][16]	MAIN[34][29][16]
DRP[34] bit 2	MAIN[4][28][17]	MAIN[14][28][17]	MAIN[24][28][17]	MAIN[34][28][17]
DRP[34] bit 3	MAIN[4][29][17]	MAIN[14][29][17]	MAIN[24][29][17]	MAIN[34][29][17]
DRP[34] bit 4	MAIN[4][28][18]	MAIN[14][28][18]	MAIN[24][28][18]	MAIN[34][28][18]
DRP[34] bit 5	MAIN[4][29][18]	MAIN[14][29][18]	MAIN[24][29][18]	MAIN[34][29][18]
DRP[34] bit 6	MAIN[4][28][19]	MAIN[14][28][19]	MAIN[24][28][19]	MAIN[34][28][19]
DRP[34] bit 7	MAIN[4][29][19]	MAIN[14][29][19]	MAIN[24][29][19]	MAIN[34][29][19]
DRP[34] bit 8	MAIN[4][28][20]	MAIN[14][28][20]	MAIN[24][28][20]	MAIN[34][28][20]
DRP[34] bit 9	MAIN[4][29][20]	MAIN[14][29][20]	MAIN[24][29][20]	MAIN[34][29][20]
DRP[34] bit 10	MAIN[4][28][21]	MAIN[14][28][21]	MAIN[24][28][21]	MAIN[34][28][21]
DRP[34] bit 11	MAIN[4][29][21]	MAIN[14][29][21]	MAIN[24][29][21]	MAIN[34][29][21]
DRP[34] bit 12	MAIN[4][28][22]	MAIN[14][28][22]	MAIN[24][28][22]	MAIN[34][28][22]
DRP[34] bit 13	MAIN[4][29][22]	MAIN[14][29][22]	MAIN[24][29][22]	MAIN[34][29][22]
DRP[34] bit 14	MAIN[4][28][23]	MAIN[14][28][23]	MAIN[24][28][23]	MAIN[34][28][23]
DRP[34] bit 15	MAIN[4][29][23]	MAIN[14][29][23]	MAIN[24][29][23]	MAIN[34][29][23]
DRP[35] bit 0	MAIN[4][28][24]	MAIN[14][28][24]	MAIN[24][28][24]	MAIN[34][28][24]
DRP[35] bit 1	MAIN[4][29][24]	MAIN[14][29][24]	MAIN[24][29][24]	MAIN[34][29][24]
DRP[35] bit 2	MAIN[4][28][25]	MAIN[14][28][25]	MAIN[24][28][25]	MAIN[34][28][25]
DRP[35] bit 3	MAIN[4][29][25]	MAIN[14][29][25]	MAIN[24][29][25]	MAIN[34][29][25]
DRP[35] bit 4	MAIN[4][28][26]	MAIN[14][28][26]	MAIN[24][28][26]	MAIN[34][28][26]
DRP[35] bit 5	MAIN[4][29][26]	MAIN[14][29][26]	MAIN[24][29][26]	MAIN[34][29][26]
DRP[35] bit 6	MAIN[4][28][27]	MAIN[14][28][27]	MAIN[24][28][27]	MAIN[34][28][27]
DRP[35] bit 7	MAIN[4][29][27]	MAIN[14][29][27]	MAIN[24][29][27]	MAIN[34][29][27]
DRP[35] bit 8	MAIN[4][28][28]	MAIN[14][28][28]	MAIN[24][28][28]	MAIN[34][28][28]
DRP[35] bit 9	MAIN[4][29][28]	MAIN[14][29][28]	MAIN[24][29][28]	MAIN[34][29][28]
DRP[35] bit 10	MAIN[4][28][29]	MAIN[14][28][29]	MAIN[24][28][29]	MAIN[34][28][29]
DRP[35] bit 11	MAIN[4][29][29]	MAIN[14][29][29]	MAIN[24][29][29]	MAIN[34][29][29]
DRP[35] bit 12	MAIN[4][28][30]	MAIN[14][28][30]	MAIN[24][28][30]	MAIN[34][28][30]
DRP[35] bit 13	MAIN[4][29][30]	MAIN[14][29][30]	MAIN[24][29][30]	MAIN[34][29][30]
DRP[35] bit 14	MAIN[4][28][31]	MAIN[14][28][31]	MAIN[24][28][31]	MAIN[34][28][31]
DRP[35] bit 15	MAIN[4][29][31]	MAIN[14][29][31]	MAIN[24][29][31]	MAIN[34][29][31]
DRP[36] bit 0	MAIN[4][28][32]	MAIN[14][28][32]	MAIN[24][28][32]	MAIN[34][28][32]
DRP[36] bit 1	MAIN[4][29][32]	MAIN[14][29][32]	MAIN[24][29][32]	MAIN[34][29][32]
DRP[36] bit 2	MAIN[4][28][33]	MAIN[14][28][33]	MAIN[24][28][33]	MAIN[34][28][33]
DRP[36] bit 3	MAIN[4][29][33]	MAIN[14][29][33]	MAIN[24][29][33]	MAIN[34][29][33]
DRP[36] bit 4	MAIN[4][28][34]	MAIN[14][28][34]	MAIN[24][28][34]	MAIN[34][28][34]
DRP[36] bit 5	MAIN[4][29][34]	MAIN[14][29][34]	MAIN[24][29][34]	MAIN[34][29][34]
DRP[36] bit 6	MAIN[4][28][35]	MAIN[14][28][35]	MAIN[24][28][35]	MAIN[34][28][35]
DRP[36] bit 7	MAIN[4][29][35]	MAIN[14][29][35]	MAIN[24][29][35]	MAIN[34][29][35]
DRP[36] bit 8	MAIN[4][28][36]	MAIN[14][28][36]	MAIN[24][28][36]	MAIN[34][28][36]
DRP[36] bit 9	MAIN[4][29][36]	MAIN[14][29][36]	MAIN[24][29][36]	MAIN[34][29][36]
DRP[36] bit 10	MAIN[4][28][37]	MAIN[14][28][37]	MAIN[24][28][37]	MAIN[34][28][37]
DRP[36] bit 11	MAIN[4][29][37]	MAIN[14][29][37]	MAIN[24][29][37]	MAIN[34][29][37]
DRP[36] bit 12	MAIN[4][28][38]	MAIN[14][28][38]	MAIN[24][28][38]	MAIN[34][28][38]
DRP[36] bit 13	MAIN[4][29][38]	MAIN[14][29][38]	MAIN[24][29][38]	MAIN[34][29][38]
DRP[36] bit 14	MAIN[4][28][39]	MAIN[14][28][39]	MAIN[24][28][39]	MAIN[34][28][39]
DRP[36] bit 15	MAIN[4][29][39]	MAIN[14][29][39]	MAIN[24][29][39]	MAIN[34][29][39]
DRP[37] bit 0	MAIN[4][28][40]	MAIN[14][28][40]	MAIN[24][28][40]	MAIN[34][28][40]
DRP[37] bit 1	MAIN[4][29][40]	MAIN[14][29][40]	MAIN[24][29][40]	MAIN[34][29][40]
DRP[37] bit 2	MAIN[4][28][41]	MAIN[14][28][41]	MAIN[24][28][41]	MAIN[34][28][41]
DRP[37] bit 3	MAIN[4][29][41]	MAIN[14][29][41]	MAIN[24][29][41]	MAIN[34][29][41]
DRP[37] bit 4	MAIN[4][28][42]	MAIN[14][28][42]	MAIN[24][28][42]	MAIN[34][28][42]
DRP[37] bit 5	MAIN[4][29][42]	MAIN[14][29][42]	MAIN[24][29][42]	MAIN[34][29][42]
DRP[37] bit 6	MAIN[4][28][43]	MAIN[14][28][43]	MAIN[24][28][43]	MAIN[34][28][43]
DRP[37] bit 7	MAIN[4][29][43]	MAIN[14][29][43]	MAIN[24][29][43]	MAIN[34][29][43]
DRP[37] bit 8	MAIN[4][28][44]	MAIN[14][28][44]	MAIN[24][28][44]	MAIN[34][28][44]
DRP[37] bit 9	MAIN[4][29][44]	MAIN[14][29][44]	MAIN[24][29][44]	MAIN[34][29][44]
DRP[37] bit 10	MAIN[4][28][45]	MAIN[14][28][45]	MAIN[24][28][45]	MAIN[34][28][45]
DRP[37] bit 11	MAIN[4][29][45]	MAIN[14][29][45]	MAIN[24][29][45]	MAIN[34][29][45]
DRP[37] bit 12	MAIN[4][28][46]	MAIN[14][28][46]	MAIN[24][28][46]	MAIN[34][28][46]
DRP[37] bit 13	MAIN[4][29][46]	MAIN[14][29][46]	MAIN[24][29][46]	MAIN[34][29][46]
DRP[37] bit 14	MAIN[4][28][47]	MAIN[14][28][47]	MAIN[24][28][47]	MAIN[34][28][47]
DRP[37] bit 15	MAIN[4][29][47]	MAIN[14][29][47]	MAIN[24][29][47]	MAIN[34][29][47]
DRP[38] bit 0	MAIN[4][28][48]	MAIN[14][28][48]	MAIN[24][28][48]	MAIN[34][28][48]
DRP[38] bit 1	MAIN[4][29][48]	MAIN[14][29][48]	MAIN[24][29][48]	MAIN[34][29][48]
DRP[38] bit 2	MAIN[4][28][49]	MAIN[14][28][49]	MAIN[24][28][49]	MAIN[34][28][49]
DRP[38] bit 3	MAIN[4][29][49]	MAIN[14][29][49]	MAIN[24][29][49]	MAIN[34][29][49]
DRP[38] bit 4	MAIN[4][28][50]	MAIN[14][28][50]	MAIN[24][28][50]	MAIN[34][28][50]
DRP[38] bit 5	MAIN[4][29][50]	MAIN[14][29][50]	MAIN[24][29][50]	MAIN[34][29][50]
DRP[38] bit 6	MAIN[4][28][51]	MAIN[14][28][51]	MAIN[24][28][51]	MAIN[34][28][51]
DRP[38] bit 7	MAIN[4][29][51]	MAIN[14][29][51]	MAIN[24][29][51]	MAIN[34][29][51]
DRP[38] bit 8	MAIN[4][28][52]	MAIN[14][28][52]	MAIN[24][28][52]	MAIN[34][28][52]
DRP[38] bit 9	MAIN[4][29][52]	MAIN[14][29][52]	MAIN[24][29][52]	MAIN[34][29][52]
DRP[38] bit 10	MAIN[4][28][53]	MAIN[14][28][53]	MAIN[24][28][53]	MAIN[34][28][53]
DRP[38] bit 11	MAIN[4][29][53]	MAIN[14][29][53]	MAIN[24][29][53]	MAIN[34][29][53]
DRP[38] bit 12	MAIN[4][28][54]	MAIN[14][28][54]	MAIN[24][28][54]	MAIN[34][28][54]
DRP[38] bit 13	MAIN[4][29][54]	MAIN[14][29][54]	MAIN[24][29][54]	MAIN[34][29][54]
DRP[38] bit 14	MAIN[4][28][55]	MAIN[14][28][55]	MAIN[24][28][55]	MAIN[34][28][55]
DRP[38] bit 15	MAIN[4][29][55]	MAIN[14][29][55]	MAIN[24][29][55]	MAIN[34][29][55]
DRP[39] bit 0	MAIN[4][28][56]	MAIN[14][28][56]	MAIN[24][28][56]	MAIN[34][28][56]
DRP[39] bit 1	MAIN[4][29][56]	MAIN[14][29][56]	MAIN[24][29][56]	MAIN[34][29][56]
DRP[39] bit 2	MAIN[4][28][57]	MAIN[14][28][57]	MAIN[24][28][57]	MAIN[34][28][57]
DRP[39] bit 3	MAIN[4][29][57]	MAIN[14][29][57]	MAIN[24][29][57]	MAIN[34][29][57]
DRP[39] bit 4	MAIN[4][28][58]	MAIN[14][28][58]	MAIN[24][28][58]	MAIN[34][28][58]
DRP[39] bit 5	MAIN[4][29][58]	MAIN[14][29][58]	MAIN[24][29][58]	MAIN[34][29][58]
DRP[39] bit 6	MAIN[4][28][59]	MAIN[14][28][59]	MAIN[24][28][59]	MAIN[34][28][59]
DRP[39] bit 7	MAIN[4][29][59]	MAIN[14][29][59]	MAIN[24][29][59]	MAIN[34][29][59]
DRP[39] bit 8	MAIN[4][28][60]	MAIN[14][28][60]	MAIN[24][28][60]	MAIN[34][28][60]
DRP[39] bit 9	MAIN[4][29][60]	MAIN[14][29][60]	MAIN[24][29][60]	MAIN[34][29][60]
DRP[39] bit 10	MAIN[4][28][61]	MAIN[14][28][61]	MAIN[24][28][61]	MAIN[34][28][61]
DRP[39] bit 11	MAIN[4][29][61]	MAIN[14][29][61]	MAIN[24][29][61]	MAIN[34][29][61]
DRP[39] bit 12	MAIN[4][28][62]	MAIN[14][28][62]	MAIN[24][28][62]	MAIN[34][28][62]
DRP[39] bit 13	MAIN[4][29][62]	MAIN[14][29][62]	MAIN[24][29][62]	MAIN[34][29][62]
DRP[39] bit 14	MAIN[4][28][63]	MAIN[14][28][63]	MAIN[24][28][63]	MAIN[34][28][63]
DRP[39] bit 15	MAIN[4][29][63]	MAIN[14][29][63]	MAIN[24][29][63]	MAIN[34][29][63]
DRP[40] bit 0	MAIN[5][28][0]	MAIN[15][28][0]	MAIN[25][28][0]	MAIN[35][28][0]
DRP[40] bit 1	MAIN[5][29][0]	MAIN[15][29][0]	MAIN[25][29][0]	MAIN[35][29][0]
DRP[40] bit 2	MAIN[5][28][1]	MAIN[15][28][1]	MAIN[25][28][1]	MAIN[35][28][1]
DRP[40] bit 3	MAIN[5][29][1]	MAIN[15][29][1]	MAIN[25][29][1]	MAIN[35][29][1]
DRP[40] bit 4	MAIN[5][28][2]	MAIN[15][28][2]	MAIN[25][28][2]	MAIN[35][28][2]
DRP[40] bit 5	MAIN[5][29][2]	MAIN[15][29][2]	MAIN[25][29][2]	MAIN[35][29][2]
DRP[40] bit 6	MAIN[5][28][3]	MAIN[15][28][3]	MAIN[25][28][3]	MAIN[35][28][3]
DRP[40] bit 7	MAIN[5][29][3]	MAIN[15][29][3]	MAIN[25][29][3]	MAIN[35][29][3]
DRP[40] bit 8	MAIN[5][28][4]	MAIN[15][28][4]	MAIN[25][28][4]	MAIN[35][28][4]
DRP[40] bit 9	MAIN[5][29][4]	MAIN[15][29][4]	MAIN[25][29][4]	MAIN[35][29][4]
DRP[40] bit 10	MAIN[5][28][5]	MAIN[15][28][5]	MAIN[25][28][5]	MAIN[35][28][5]
DRP[40] bit 11	MAIN[5][29][5]	MAIN[15][29][5]	MAIN[25][29][5]	MAIN[35][29][5]
DRP[40] bit 12	MAIN[5][28][6]	MAIN[15][28][6]	MAIN[25][28][6]	MAIN[35][28][6]
DRP[40] bit 13	MAIN[5][29][6]	MAIN[15][29][6]	MAIN[25][29][6]	MAIN[35][29][6]
DRP[40] bit 14	MAIN[5][28][7]	MAIN[15][28][7]	MAIN[25][28][7]	MAIN[35][28][7]
DRP[40] bit 15	MAIN[5][29][7]	MAIN[15][29][7]	MAIN[25][29][7]	MAIN[35][29][7]
DRP[41] bit 0	MAIN[5][28][8]	MAIN[15][28][8]	MAIN[25][28][8]	MAIN[35][28][8]
DRP[41] bit 1	MAIN[5][29][8]	MAIN[15][29][8]	MAIN[25][29][8]	MAIN[35][29][8]
DRP[41] bit 2	MAIN[5][28][9]	MAIN[15][28][9]	MAIN[25][28][9]	MAIN[35][28][9]
DRP[41] bit 3	MAIN[5][29][9]	MAIN[15][29][9]	MAIN[25][29][9]	MAIN[35][29][9]
DRP[41] bit 4	MAIN[5][28][10]	MAIN[15][28][10]	MAIN[25][28][10]	MAIN[35][28][10]
DRP[41] bit 5	MAIN[5][29][10]	MAIN[15][29][10]	MAIN[25][29][10]	MAIN[35][29][10]
DRP[41] bit 6	MAIN[5][28][11]	MAIN[15][28][11]	MAIN[25][28][11]	MAIN[35][28][11]
DRP[41] bit 7	MAIN[5][29][11]	MAIN[15][29][11]	MAIN[25][29][11]	MAIN[35][29][11]
DRP[41] bit 8	MAIN[5][28][12]	MAIN[15][28][12]	MAIN[25][28][12]	MAIN[35][28][12]
DRP[41] bit 9	MAIN[5][29][12]	MAIN[15][29][12]	MAIN[25][29][12]	MAIN[35][29][12]
DRP[41] bit 10	MAIN[5][28][13]	MAIN[15][28][13]	MAIN[25][28][13]	MAIN[35][28][13]
DRP[41] bit 11	MAIN[5][29][13]	MAIN[15][29][13]	MAIN[25][29][13]	MAIN[35][29][13]
DRP[41] bit 12	MAIN[5][28][14]	MAIN[15][28][14]	MAIN[25][28][14]	MAIN[35][28][14]
DRP[41] bit 13	MAIN[5][29][14]	MAIN[15][29][14]	MAIN[25][29][14]	MAIN[35][29][14]
DRP[41] bit 14	MAIN[5][28][15]	MAIN[15][28][15]	MAIN[25][28][15]	MAIN[35][28][15]
DRP[41] bit 15	MAIN[5][29][15]	MAIN[15][29][15]	MAIN[25][29][15]	MAIN[35][29][15]
DRP[42] bit 0	MAIN[5][28][16]	MAIN[15][28][16]	MAIN[25][28][16]	MAIN[35][28][16]
DRP[42] bit 1	MAIN[5][29][16]	MAIN[15][29][16]	MAIN[25][29][16]	MAIN[35][29][16]
DRP[42] bit 2	MAIN[5][28][17]	MAIN[15][28][17]	MAIN[25][28][17]	MAIN[35][28][17]
DRP[42] bit 3	MAIN[5][29][17]	MAIN[15][29][17]	MAIN[25][29][17]	MAIN[35][29][17]
DRP[42] bit 4	MAIN[5][28][18]	MAIN[15][28][18]	MAIN[25][28][18]	MAIN[35][28][18]
DRP[42] bit 5	MAIN[5][29][18]	MAIN[15][29][18]	MAIN[25][29][18]	MAIN[35][29][18]
DRP[42] bit 6	MAIN[5][28][19]	MAIN[15][28][19]	MAIN[25][28][19]	MAIN[35][28][19]
DRP[42] bit 7	MAIN[5][29][19]	MAIN[15][29][19]	MAIN[25][29][19]	MAIN[35][29][19]
DRP[42] bit 8	MAIN[5][28][20]	MAIN[15][28][20]	MAIN[25][28][20]	MAIN[35][28][20]
DRP[42] bit 9	MAIN[5][29][20]	MAIN[15][29][20]	MAIN[25][29][20]	MAIN[35][29][20]
DRP[42] bit 10	MAIN[5][28][21]	MAIN[15][28][21]	MAIN[25][28][21]	MAIN[35][28][21]
DRP[42] bit 11	MAIN[5][29][21]	MAIN[15][29][21]	MAIN[25][29][21]	MAIN[35][29][21]
DRP[42] bit 12	MAIN[5][28][22]	MAIN[15][28][22]	MAIN[25][28][22]	MAIN[35][28][22]
DRP[42] bit 13	MAIN[5][29][22]	MAIN[15][29][22]	MAIN[25][29][22]	MAIN[35][29][22]
DRP[42] bit 14	MAIN[5][28][23]	MAIN[15][28][23]	MAIN[25][28][23]	MAIN[35][28][23]
DRP[42] bit 15	MAIN[5][29][23]	MAIN[15][29][23]	MAIN[25][29][23]	MAIN[35][29][23]
DRP[43] bit 0	MAIN[5][28][24]	MAIN[15][28][24]	MAIN[25][28][24]	MAIN[35][28][24]
DRP[43] bit 1	MAIN[5][29][24]	MAIN[15][29][24]	MAIN[25][29][24]	MAIN[35][29][24]
DRP[43] bit 2	MAIN[5][28][25]	MAIN[15][28][25]	MAIN[25][28][25]	MAIN[35][28][25]
DRP[43] bit 3	MAIN[5][29][25]	MAIN[15][29][25]	MAIN[25][29][25]	MAIN[35][29][25]
DRP[43] bit 4	MAIN[5][28][26]	MAIN[15][28][26]	MAIN[25][28][26]	MAIN[35][28][26]
DRP[43] bit 5	MAIN[5][29][26]	MAIN[15][29][26]	MAIN[25][29][26]	MAIN[35][29][26]
DRP[43] bit 6	MAIN[5][28][27]	MAIN[15][28][27]	MAIN[25][28][27]	MAIN[35][28][27]
DRP[43] bit 7	MAIN[5][29][27]	MAIN[15][29][27]	MAIN[25][29][27]	MAIN[35][29][27]
DRP[43] bit 8	MAIN[5][28][28]	MAIN[15][28][28]	MAIN[25][28][28]	MAIN[35][28][28]
DRP[43] bit 9	MAIN[5][29][28]	MAIN[15][29][28]	MAIN[25][29][28]	MAIN[35][29][28]
DRP[43] bit 10	MAIN[5][28][29]	MAIN[15][28][29]	MAIN[25][28][29]	MAIN[35][28][29]
DRP[43] bit 11	MAIN[5][29][29]	MAIN[15][29][29]	MAIN[25][29][29]	MAIN[35][29][29]
DRP[43] bit 12	MAIN[5][28][30]	MAIN[15][28][30]	MAIN[25][28][30]	MAIN[35][28][30]
DRP[43] bit 13	MAIN[5][29][30]	MAIN[15][29][30]	MAIN[25][29][30]	MAIN[35][29][30]
DRP[43] bit 14	MAIN[5][28][31]	MAIN[15][28][31]	MAIN[25][28][31]	MAIN[35][28][31]
DRP[43] bit 15	MAIN[5][29][31]	MAIN[15][29][31]	MAIN[25][29][31]	MAIN[35][29][31]
DRP[44] bit 0	MAIN[5][28][32]	MAIN[15][28][32]	MAIN[25][28][32]	MAIN[35][28][32]
DRP[44] bit 1	MAIN[5][29][32]	MAIN[15][29][32]	MAIN[25][29][32]	MAIN[35][29][32]
DRP[44] bit 2	MAIN[5][28][33]	MAIN[15][28][33]	MAIN[25][28][33]	MAIN[35][28][33]
DRP[44] bit 3	MAIN[5][29][33]	MAIN[15][29][33]	MAIN[25][29][33]	MAIN[35][29][33]
DRP[44] bit 4	MAIN[5][28][34]	MAIN[15][28][34]	MAIN[25][28][34]	MAIN[35][28][34]
DRP[44] bit 5	MAIN[5][29][34]	MAIN[15][29][34]	MAIN[25][29][34]	MAIN[35][29][34]
DRP[44] bit 6	MAIN[5][28][35]	MAIN[15][28][35]	MAIN[25][28][35]	MAIN[35][28][35]
DRP[44] bit 7	MAIN[5][29][35]	MAIN[15][29][35]	MAIN[25][29][35]	MAIN[35][29][35]
DRP[44] bit 8	MAIN[5][28][36]	MAIN[15][28][36]	MAIN[25][28][36]	MAIN[35][28][36]
DRP[44] bit 9	MAIN[5][29][36]	MAIN[15][29][36]	MAIN[25][29][36]	MAIN[35][29][36]
DRP[44] bit 10	MAIN[5][28][37]	MAIN[15][28][37]	MAIN[25][28][37]	MAIN[35][28][37]
DRP[44] bit 11	MAIN[5][29][37]	MAIN[15][29][37]	MAIN[25][29][37]	MAIN[35][29][37]
DRP[44] bit 12	MAIN[5][28][38]	MAIN[15][28][38]	MAIN[25][28][38]	MAIN[35][28][38]
DRP[44] bit 13	MAIN[5][29][38]	MAIN[15][29][38]	MAIN[25][29][38]	MAIN[35][29][38]
DRP[44] bit 14	MAIN[5][28][39]	MAIN[15][28][39]	MAIN[25][28][39]	MAIN[35][28][39]
DRP[44] bit 15	MAIN[5][29][39]	MAIN[15][29][39]	MAIN[25][29][39]	MAIN[35][29][39]
DRP[45] bit 0	MAIN[5][28][40]	MAIN[15][28][40]	MAIN[25][28][40]	MAIN[35][28][40]
DRP[45] bit 1	MAIN[5][29][40]	MAIN[15][29][40]	MAIN[25][29][40]	MAIN[35][29][40]
DRP[45] bit 2	MAIN[5][28][41]	MAIN[15][28][41]	MAIN[25][28][41]	MAIN[35][28][41]
DRP[45] bit 3	MAIN[5][29][41]	MAIN[15][29][41]	MAIN[25][29][41]	MAIN[35][29][41]
DRP[45] bit 4	MAIN[5][28][42]	MAIN[15][28][42]	MAIN[25][28][42]	MAIN[35][28][42]
DRP[45] bit 5	MAIN[5][29][42]	MAIN[15][29][42]	MAIN[25][29][42]	MAIN[35][29][42]
DRP[45] bit 6	MAIN[5][28][43]	MAIN[15][28][43]	MAIN[25][28][43]	MAIN[35][28][43]
DRP[45] bit 7	MAIN[5][29][43]	MAIN[15][29][43]	MAIN[25][29][43]	MAIN[35][29][43]
DRP[45] bit 8	MAIN[5][28][44]	MAIN[15][28][44]	MAIN[25][28][44]	MAIN[35][28][44]
DRP[45] bit 9	MAIN[5][29][44]	MAIN[15][29][44]	MAIN[25][29][44]	MAIN[35][29][44]
DRP[45] bit 10	MAIN[5][28][45]	MAIN[15][28][45]	MAIN[25][28][45]	MAIN[35][28][45]
DRP[45] bit 11	MAIN[5][29][45]	MAIN[15][29][45]	MAIN[25][29][45]	MAIN[35][29][45]
DRP[45] bit 12	MAIN[5][28][46]	MAIN[15][28][46]	MAIN[25][28][46]	MAIN[35][28][46]
DRP[45] bit 13	MAIN[5][29][46]	MAIN[15][29][46]	MAIN[25][29][46]	MAIN[35][29][46]
DRP[45] bit 14	MAIN[5][28][47]	MAIN[15][28][47]	MAIN[25][28][47]	MAIN[35][28][47]
DRP[45] bit 15	MAIN[5][29][47]	MAIN[15][29][47]	MAIN[25][29][47]	MAIN[35][29][47]
DRP[46] bit 0	MAIN[5][28][48]	MAIN[15][28][48]	MAIN[25][28][48]	MAIN[35][28][48]
DRP[46] bit 1	MAIN[5][29][48]	MAIN[15][29][48]	MAIN[25][29][48]	MAIN[35][29][48]
DRP[46] bit 2	MAIN[5][28][49]	MAIN[15][28][49]	MAIN[25][28][49]	MAIN[35][28][49]
DRP[46] bit 3	MAIN[5][29][49]	MAIN[15][29][49]	MAIN[25][29][49]	MAIN[35][29][49]
DRP[46] bit 4	MAIN[5][28][50]	MAIN[15][28][50]	MAIN[25][28][50]	MAIN[35][28][50]
DRP[46] bit 5	MAIN[5][29][50]	MAIN[15][29][50]	MAIN[25][29][50]	MAIN[35][29][50]
DRP[46] bit 6	MAIN[5][28][51]	MAIN[15][28][51]	MAIN[25][28][51]	MAIN[35][28][51]
DRP[46] bit 7	MAIN[5][29][51]	MAIN[15][29][51]	MAIN[25][29][51]	MAIN[35][29][51]
DRP[46] bit 8	MAIN[5][28][52]	MAIN[15][28][52]	MAIN[25][28][52]	MAIN[35][28][52]
DRP[46] bit 9	MAIN[5][29][52]	MAIN[15][29][52]	MAIN[25][29][52]	MAIN[35][29][52]
DRP[46] bit 10	MAIN[5][28][53]	MAIN[15][28][53]	MAIN[25][28][53]	MAIN[35][28][53]
DRP[46] bit 11	MAIN[5][29][53]	MAIN[15][29][53]	MAIN[25][29][53]	MAIN[35][29][53]
DRP[46] bit 12	MAIN[5][28][54]	MAIN[15][28][54]	MAIN[25][28][54]	MAIN[35][28][54]
DRP[46] bit 13	MAIN[5][29][54]	MAIN[15][29][54]	MAIN[25][29][54]	MAIN[35][29][54]
DRP[46] bit 14	MAIN[5][28][55]	MAIN[15][28][55]	MAIN[25][28][55]	MAIN[35][28][55]
DRP[46] bit 15	MAIN[5][29][55]	MAIN[15][29][55]	MAIN[25][29][55]	MAIN[35][29][55]
DRP[47] bit 0	MAIN[5][28][56]	MAIN[15][28][56]	MAIN[25][28][56]	MAIN[35][28][56]
DRP[47] bit 1	MAIN[5][29][56]	MAIN[15][29][56]	MAIN[25][29][56]	MAIN[35][29][56]
DRP[47] bit 2	MAIN[5][28][57]	MAIN[15][28][57]	MAIN[25][28][57]	MAIN[35][28][57]
DRP[47] bit 3	MAIN[5][29][57]	MAIN[15][29][57]	MAIN[25][29][57]	MAIN[35][29][57]
DRP[47] bit 4	MAIN[5][28][58]	MAIN[15][28][58]	MAIN[25][28][58]	MAIN[35][28][58]
DRP[47] bit 5	MAIN[5][29][58]	MAIN[15][29][58]	MAIN[25][29][58]	MAIN[35][29][58]
DRP[47] bit 6	MAIN[5][28][59]	MAIN[15][28][59]	MAIN[25][28][59]	MAIN[35][28][59]
DRP[47] bit 7	MAIN[5][29][59]	MAIN[15][29][59]	MAIN[25][29][59]	MAIN[35][29][59]
DRP[47] bit 8	MAIN[5][28][60]	MAIN[15][28][60]	MAIN[25][28][60]	MAIN[35][28][60]
DRP[47] bit 9	MAIN[5][29][60]	MAIN[15][29][60]	MAIN[25][29][60]	MAIN[35][29][60]
DRP[47] bit 10	MAIN[5][28][61]	MAIN[15][28][61]	MAIN[25][28][61]	MAIN[35][28][61]
DRP[47] bit 11	MAIN[5][29][61]	MAIN[15][29][61]	MAIN[25][29][61]	MAIN[35][29][61]
DRP[47] bit 12	MAIN[5][28][62]	MAIN[15][28][62]	MAIN[25][28][62]	MAIN[35][28][62]
DRP[47] bit 13	MAIN[5][29][62]	MAIN[15][29][62]	MAIN[25][29][62]	MAIN[35][29][62]
DRP[47] bit 14	MAIN[5][28][63]	MAIN[15][28][63]	MAIN[25][28][63]	MAIN[35][28][63]
DRP[47] bit 15	MAIN[5][29][63]	MAIN[15][29][63]	MAIN[25][29][63]	MAIN[35][29][63]
DRP[48] bit 0	MAIN[6][28][0]	MAIN[16][28][0]	MAIN[26][28][0]	MAIN[36][28][0]
DRP[48] bit 1	MAIN[6][29][0]	MAIN[16][29][0]	MAIN[26][29][0]	MAIN[36][29][0]
DRP[48] bit 2	MAIN[6][28][1]	MAIN[16][28][1]	MAIN[26][28][1]	MAIN[36][28][1]
DRP[48] bit 3	MAIN[6][29][1]	MAIN[16][29][1]	MAIN[26][29][1]	MAIN[36][29][1]
DRP[48] bit 4	MAIN[6][28][2]	MAIN[16][28][2]	MAIN[26][28][2]	MAIN[36][28][2]
DRP[48] bit 5	MAIN[6][29][2]	MAIN[16][29][2]	MAIN[26][29][2]	MAIN[36][29][2]
DRP[48] bit 6	MAIN[6][28][3]	MAIN[16][28][3]	MAIN[26][28][3]	MAIN[36][28][3]
DRP[48] bit 7	MAIN[6][29][3]	MAIN[16][29][3]	MAIN[26][29][3]	MAIN[36][29][3]
DRP[48] bit 8	MAIN[6][28][4]	MAIN[16][28][4]	MAIN[26][28][4]	MAIN[36][28][4]
DRP[48] bit 9	MAIN[6][29][4]	MAIN[16][29][4]	MAIN[26][29][4]	MAIN[36][29][4]
DRP[48] bit 10	MAIN[6][28][5]	MAIN[16][28][5]	MAIN[26][28][5]	MAIN[36][28][5]
DRP[48] bit 11	MAIN[6][29][5]	MAIN[16][29][5]	MAIN[26][29][5]	MAIN[36][29][5]
DRP[48] bit 12	MAIN[6][28][6]	MAIN[16][28][6]	MAIN[26][28][6]	MAIN[36][28][6]
DRP[48] bit 13	MAIN[6][29][6]	MAIN[16][29][6]	MAIN[26][29][6]	MAIN[36][29][6]
DRP[48] bit 14	MAIN[6][28][7]	MAIN[16][28][7]	MAIN[26][28][7]	MAIN[36][28][7]
DRP[48] bit 15	MAIN[6][29][7]	MAIN[16][29][7]	MAIN[26][29][7]	MAIN[36][29][7]
DRP[49] bit 0	MAIN[6][28][8]	MAIN[16][28][8]	MAIN[26][28][8]	MAIN[36][28][8]
DRP[49] bit 1	MAIN[6][29][8]	MAIN[16][29][8]	MAIN[26][29][8]	MAIN[36][29][8]
DRP[49] bit 2	MAIN[6][28][9]	MAIN[16][28][9]	MAIN[26][28][9]	MAIN[36][28][9]
DRP[49] bit 3	MAIN[6][29][9]	MAIN[16][29][9]	MAIN[26][29][9]	MAIN[36][29][9]
DRP[49] bit 4	MAIN[6][28][10]	MAIN[16][28][10]	MAIN[26][28][10]	MAIN[36][28][10]
DRP[49] bit 5	MAIN[6][29][10]	MAIN[16][29][10]	MAIN[26][29][10]	MAIN[36][29][10]
DRP[49] bit 6	MAIN[6][28][11]	MAIN[16][28][11]	MAIN[26][28][11]	MAIN[36][28][11]
DRP[49] bit 7	MAIN[6][29][11]	MAIN[16][29][11]	MAIN[26][29][11]	MAIN[36][29][11]
DRP[49] bit 8	MAIN[6][28][12]	MAIN[16][28][12]	MAIN[26][28][12]	MAIN[36][28][12]
DRP[49] bit 9	MAIN[6][29][12]	MAIN[16][29][12]	MAIN[26][29][12]	MAIN[36][29][12]
DRP[49] bit 10	MAIN[6][28][13]	MAIN[16][28][13]	MAIN[26][28][13]	MAIN[36][28][13]
DRP[49] bit 11	MAIN[6][29][13]	MAIN[16][29][13]	MAIN[26][29][13]	MAIN[36][29][13]
DRP[49] bit 12	MAIN[6][28][14]	MAIN[16][28][14]	MAIN[26][28][14]	MAIN[36][28][14]
DRP[49] bit 13	MAIN[6][29][14]	MAIN[16][29][14]	MAIN[26][29][14]	MAIN[36][29][14]
DRP[49] bit 14	MAIN[6][28][15]	MAIN[16][28][15]	MAIN[26][28][15]	MAIN[36][28][15]
DRP[49] bit 15	MAIN[6][29][15]	MAIN[16][29][15]	MAIN[26][29][15]	MAIN[36][29][15]
DRP[50] bit 0	MAIN[6][28][16]	MAIN[16][28][16]	MAIN[26][28][16]	MAIN[36][28][16]
DRP[50] bit 1	MAIN[6][29][16]	MAIN[16][29][16]	MAIN[26][29][16]	MAIN[36][29][16]
DRP[50] bit 2	MAIN[6][28][17]	MAIN[16][28][17]	MAIN[26][28][17]	MAIN[36][28][17]
DRP[50] bit 3	MAIN[6][29][17]	MAIN[16][29][17]	MAIN[26][29][17]	MAIN[36][29][17]
DRP[50] bit 4	MAIN[6][28][18]	MAIN[16][28][18]	MAIN[26][28][18]	MAIN[36][28][18]
DRP[50] bit 5	MAIN[6][29][18]	MAIN[16][29][18]	MAIN[26][29][18]	MAIN[36][29][18]
DRP[50] bit 6	MAIN[6][28][19]	MAIN[16][28][19]	MAIN[26][28][19]	MAIN[36][28][19]
DRP[50] bit 7	MAIN[6][29][19]	MAIN[16][29][19]	MAIN[26][29][19]	MAIN[36][29][19]
DRP[50] bit 8	MAIN[6][28][20]	MAIN[16][28][20]	MAIN[26][28][20]	MAIN[36][28][20]
DRP[50] bit 9	MAIN[6][29][20]	MAIN[16][29][20]	MAIN[26][29][20]	MAIN[36][29][20]
DRP[50] bit 10	MAIN[6][28][21]	MAIN[16][28][21]	MAIN[26][28][21]	MAIN[36][28][21]
DRP[50] bit 11	MAIN[6][29][21]	MAIN[16][29][21]	MAIN[26][29][21]	MAIN[36][29][21]
DRP[50] bit 12	MAIN[6][28][22]	MAIN[16][28][22]	MAIN[26][28][22]	MAIN[36][28][22]
DRP[50] bit 13	MAIN[6][29][22]	MAIN[16][29][22]	MAIN[26][29][22]	MAIN[36][29][22]
DRP[50] bit 14	MAIN[6][28][23]	MAIN[16][28][23]	MAIN[26][28][23]	MAIN[36][28][23]
DRP[50] bit 15	MAIN[6][29][23]	MAIN[16][29][23]	MAIN[26][29][23]	MAIN[36][29][23]
DRP[51] bit 0	MAIN[6][28][24]	MAIN[16][28][24]	MAIN[26][28][24]	MAIN[36][28][24]
DRP[51] bit 1	MAIN[6][29][24]	MAIN[16][29][24]	MAIN[26][29][24]	MAIN[36][29][24]
DRP[51] bit 2	MAIN[6][28][25]	MAIN[16][28][25]	MAIN[26][28][25]	MAIN[36][28][25]
DRP[51] bit 3	MAIN[6][29][25]	MAIN[16][29][25]	MAIN[26][29][25]	MAIN[36][29][25]
DRP[51] bit 4	MAIN[6][28][26]	MAIN[16][28][26]	MAIN[26][28][26]	MAIN[36][28][26]
DRP[51] bit 5	MAIN[6][29][26]	MAIN[16][29][26]	MAIN[26][29][26]	MAIN[36][29][26]
DRP[51] bit 6	MAIN[6][28][27]	MAIN[16][28][27]	MAIN[26][28][27]	MAIN[36][28][27]
DRP[51] bit 7	MAIN[6][29][27]	MAIN[16][29][27]	MAIN[26][29][27]	MAIN[36][29][27]
DRP[51] bit 8	MAIN[6][28][28]	MAIN[16][28][28]	MAIN[26][28][28]	MAIN[36][28][28]
DRP[51] bit 9	MAIN[6][29][28]	MAIN[16][29][28]	MAIN[26][29][28]	MAIN[36][29][28]
DRP[51] bit 10	MAIN[6][28][29]	MAIN[16][28][29]	MAIN[26][28][29]	MAIN[36][28][29]
DRP[51] bit 11	MAIN[6][29][29]	MAIN[16][29][29]	MAIN[26][29][29]	MAIN[36][29][29]
DRP[51] bit 12	MAIN[6][28][30]	MAIN[16][28][30]	MAIN[26][28][30]	MAIN[36][28][30]
DRP[51] bit 13	MAIN[6][29][30]	MAIN[16][29][30]	MAIN[26][29][30]	MAIN[36][29][30]
DRP[51] bit 14	MAIN[6][28][31]	MAIN[16][28][31]	MAIN[26][28][31]	MAIN[36][28][31]
DRP[51] bit 15	MAIN[6][29][31]	MAIN[16][29][31]	MAIN[26][29][31]	MAIN[36][29][31]
DRP[52] bit 0	MAIN[6][28][32]	MAIN[16][28][32]	MAIN[26][28][32]	MAIN[36][28][32]
DRP[52] bit 1	MAIN[6][29][32]	MAIN[16][29][32]	MAIN[26][29][32]	MAIN[36][29][32]
DRP[52] bit 2	MAIN[6][28][33]	MAIN[16][28][33]	MAIN[26][28][33]	MAIN[36][28][33]
DRP[52] bit 3	MAIN[6][29][33]	MAIN[16][29][33]	MAIN[26][29][33]	MAIN[36][29][33]
DRP[52] bit 4	MAIN[6][28][34]	MAIN[16][28][34]	MAIN[26][28][34]	MAIN[36][28][34]
DRP[52] bit 5	MAIN[6][29][34]	MAIN[16][29][34]	MAIN[26][29][34]	MAIN[36][29][34]
DRP[52] bit 6	MAIN[6][28][35]	MAIN[16][28][35]	MAIN[26][28][35]	MAIN[36][28][35]
DRP[52] bit 7	MAIN[6][29][35]	MAIN[16][29][35]	MAIN[26][29][35]	MAIN[36][29][35]
DRP[52] bit 8	MAIN[6][28][36]	MAIN[16][28][36]	MAIN[26][28][36]	MAIN[36][28][36]
DRP[52] bit 9	MAIN[6][29][36]	MAIN[16][29][36]	MAIN[26][29][36]	MAIN[36][29][36]
DRP[52] bit 10	MAIN[6][28][37]	MAIN[16][28][37]	MAIN[26][28][37]	MAIN[36][28][37]
DRP[52] bit 11	MAIN[6][29][37]	MAIN[16][29][37]	MAIN[26][29][37]	MAIN[36][29][37]
DRP[52] bit 12	MAIN[6][28][38]	MAIN[16][28][38]	MAIN[26][28][38]	MAIN[36][28][38]
DRP[52] bit 13	MAIN[6][29][38]	MAIN[16][29][38]	MAIN[26][29][38]	MAIN[36][29][38]
DRP[52] bit 14	MAIN[6][28][39]	MAIN[16][28][39]	MAIN[26][28][39]	MAIN[36][28][39]
DRP[52] bit 15	MAIN[6][29][39]	MAIN[16][29][39]	MAIN[26][29][39]	MAIN[36][29][39]
DRP[53] bit 0	MAIN[6][28][40]	MAIN[16][28][40]	MAIN[26][28][40]	MAIN[36][28][40]
DRP[53] bit 1	MAIN[6][29][40]	MAIN[16][29][40]	MAIN[26][29][40]	MAIN[36][29][40]
DRP[53] bit 2	MAIN[6][28][41]	MAIN[16][28][41]	MAIN[26][28][41]	MAIN[36][28][41]
DRP[53] bit 3	MAIN[6][29][41]	MAIN[16][29][41]	MAIN[26][29][41]	MAIN[36][29][41]
DRP[53] bit 4	MAIN[6][28][42]	MAIN[16][28][42]	MAIN[26][28][42]	MAIN[36][28][42]
DRP[53] bit 5	MAIN[6][29][42]	MAIN[16][29][42]	MAIN[26][29][42]	MAIN[36][29][42]
DRP[53] bit 6	MAIN[6][28][43]	MAIN[16][28][43]	MAIN[26][28][43]	MAIN[36][28][43]
DRP[53] bit 7	MAIN[6][29][43]	MAIN[16][29][43]	MAIN[26][29][43]	MAIN[36][29][43]
DRP[53] bit 8	MAIN[6][28][44]	MAIN[16][28][44]	MAIN[26][28][44]	MAIN[36][28][44]
DRP[53] bit 9	MAIN[6][29][44]	MAIN[16][29][44]	MAIN[26][29][44]	MAIN[36][29][44]
DRP[53] bit 10	MAIN[6][28][45]	MAIN[16][28][45]	MAIN[26][28][45]	MAIN[36][28][45]
DRP[53] bit 11	MAIN[6][29][45]	MAIN[16][29][45]	MAIN[26][29][45]	MAIN[36][29][45]
DRP[53] bit 12	MAIN[6][28][46]	MAIN[16][28][46]	MAIN[26][28][46]	MAIN[36][28][46]
DRP[53] bit 13	MAIN[6][29][46]	MAIN[16][29][46]	MAIN[26][29][46]	MAIN[36][29][46]
DRP[53] bit 14	MAIN[6][28][47]	MAIN[16][28][47]	MAIN[26][28][47]	MAIN[36][28][47]
DRP[53] bit 15	MAIN[6][29][47]	MAIN[16][29][47]	MAIN[26][29][47]	MAIN[36][29][47]
DRP[54] bit 0	MAIN[6][28][48]	MAIN[16][28][48]	MAIN[26][28][48]	MAIN[36][28][48]
DRP[54] bit 1	MAIN[6][29][48]	MAIN[16][29][48]	MAIN[26][29][48]	MAIN[36][29][48]
DRP[54] bit 2	MAIN[6][28][49]	MAIN[16][28][49]	MAIN[26][28][49]	MAIN[36][28][49]
DRP[54] bit 3	MAIN[6][29][49]	MAIN[16][29][49]	MAIN[26][29][49]	MAIN[36][29][49]
DRP[54] bit 4	MAIN[6][28][50]	MAIN[16][28][50]	MAIN[26][28][50]	MAIN[36][28][50]
DRP[54] bit 5	MAIN[6][29][50]	MAIN[16][29][50]	MAIN[26][29][50]	MAIN[36][29][50]
DRP[54] bit 6	MAIN[6][28][51]	MAIN[16][28][51]	MAIN[26][28][51]	MAIN[36][28][51]
DRP[54] bit 7	MAIN[6][29][51]	MAIN[16][29][51]	MAIN[26][29][51]	MAIN[36][29][51]
DRP[54] bit 8	MAIN[6][28][52]	MAIN[16][28][52]	MAIN[26][28][52]	MAIN[36][28][52]
DRP[54] bit 9	MAIN[6][29][52]	MAIN[16][29][52]	MAIN[26][29][52]	MAIN[36][29][52]
DRP[54] bit 10	MAIN[6][28][53]	MAIN[16][28][53]	MAIN[26][28][53]	MAIN[36][28][53]
DRP[54] bit 11	MAIN[6][29][53]	MAIN[16][29][53]	MAIN[26][29][53]	MAIN[36][29][53]
DRP[54] bit 12	MAIN[6][28][54]	MAIN[16][28][54]	MAIN[26][28][54]	MAIN[36][28][54]
DRP[54] bit 13	MAIN[6][29][54]	MAIN[16][29][54]	MAIN[26][29][54]	MAIN[36][29][54]
DRP[54] bit 14	MAIN[6][28][55]	MAIN[16][28][55]	MAIN[26][28][55]	MAIN[36][28][55]
DRP[54] bit 15	MAIN[6][29][55]	MAIN[16][29][55]	MAIN[26][29][55]	MAIN[36][29][55]
DRP[55] bit 0	MAIN[6][28][56]	MAIN[16][28][56]	MAIN[26][28][56]	MAIN[36][28][56]
DRP[55] bit 1	MAIN[6][29][56]	MAIN[16][29][56]	MAIN[26][29][56]	MAIN[36][29][56]
DRP[55] bit 2	MAIN[6][28][57]	MAIN[16][28][57]	MAIN[26][28][57]	MAIN[36][28][57]
DRP[55] bit 3	MAIN[6][29][57]	MAIN[16][29][57]	MAIN[26][29][57]	MAIN[36][29][57]
DRP[55] bit 4	MAIN[6][28][58]	MAIN[16][28][58]	MAIN[26][28][58]	MAIN[36][28][58]
DRP[55] bit 5	MAIN[6][29][58]	MAIN[16][29][58]	MAIN[26][29][58]	MAIN[36][29][58]
DRP[55] bit 6	MAIN[6][28][59]	MAIN[16][28][59]	MAIN[26][28][59]	MAIN[36][28][59]
DRP[55] bit 7	MAIN[6][29][59]	MAIN[16][29][59]	MAIN[26][29][59]	MAIN[36][29][59]
DRP[55] bit 8	MAIN[6][28][60]	MAIN[16][28][60]	MAIN[26][28][60]	MAIN[36][28][60]
DRP[55] bit 9	MAIN[6][29][60]	MAIN[16][29][60]	MAIN[26][29][60]	MAIN[36][29][60]
DRP[55] bit 10	MAIN[6][28][61]	MAIN[16][28][61]	MAIN[26][28][61]	MAIN[36][28][61]
DRP[55] bit 11	MAIN[6][29][61]	MAIN[16][29][61]	MAIN[26][29][61]	MAIN[36][29][61]
DRP[55] bit 12	MAIN[6][28][62]	MAIN[16][28][62]	MAIN[26][28][62]	MAIN[36][28][62]
DRP[55] bit 13	MAIN[6][29][62]	MAIN[16][29][62]	MAIN[26][29][62]	MAIN[36][29][62]
DRP[55] bit 14	MAIN[6][28][63]	MAIN[16][28][63]	MAIN[26][28][63]	MAIN[36][28][63]
DRP[55] bit 15	MAIN[6][29][63]	MAIN[16][29][63]	MAIN[26][29][63]	MAIN[36][29][63]
DRP[56] bit 0	MAIN[7][28][0]	MAIN[17][28][0]	MAIN[27][28][0]	MAIN[37][28][0]
DRP[56] bit 1	MAIN[7][29][0]	MAIN[17][29][0]	MAIN[27][29][0]	MAIN[37][29][0]
DRP[56] bit 2	MAIN[7][28][1]	MAIN[17][28][1]	MAIN[27][28][1]	MAIN[37][28][1]
DRP[56] bit 3	MAIN[7][29][1]	MAIN[17][29][1]	MAIN[27][29][1]	MAIN[37][29][1]
DRP[56] bit 4	MAIN[7][28][2]	MAIN[17][28][2]	MAIN[27][28][2]	MAIN[37][28][2]
DRP[56] bit 5	MAIN[7][29][2]	MAIN[17][29][2]	MAIN[27][29][2]	MAIN[37][29][2]
DRP[56] bit 6	MAIN[7][28][3]	MAIN[17][28][3]	MAIN[27][28][3]	MAIN[37][28][3]
DRP[56] bit 7	MAIN[7][29][3]	MAIN[17][29][3]	MAIN[27][29][3]	MAIN[37][29][3]
DRP[56] bit 8	MAIN[7][28][4]	MAIN[17][28][4]	MAIN[27][28][4]	MAIN[37][28][4]
DRP[56] bit 9	MAIN[7][29][4]	MAIN[17][29][4]	MAIN[27][29][4]	MAIN[37][29][4]
DRP[56] bit 10	MAIN[7][28][5]	MAIN[17][28][5]	MAIN[27][28][5]	MAIN[37][28][5]
DRP[56] bit 11	MAIN[7][29][5]	MAIN[17][29][5]	MAIN[27][29][5]	MAIN[37][29][5]
DRP[56] bit 12	MAIN[7][28][6]	MAIN[17][28][6]	MAIN[27][28][6]	MAIN[37][28][6]
DRP[56] bit 13	MAIN[7][29][6]	MAIN[17][29][6]	MAIN[27][29][6]	MAIN[37][29][6]
DRP[56] bit 14	MAIN[7][28][7]	MAIN[17][28][7]	MAIN[27][28][7]	MAIN[37][28][7]
DRP[56] bit 15	MAIN[7][29][7]	MAIN[17][29][7]	MAIN[27][29][7]	MAIN[37][29][7]
DRP[57] bit 0	MAIN[7][28][8]	MAIN[17][28][8]	MAIN[27][28][8]	MAIN[37][28][8]
DRP[57] bit 1	MAIN[7][29][8]	MAIN[17][29][8]	MAIN[27][29][8]	MAIN[37][29][8]
DRP[57] bit 2	MAIN[7][28][9]	MAIN[17][28][9]	MAIN[27][28][9]	MAIN[37][28][9]
DRP[57] bit 3	MAIN[7][29][9]	MAIN[17][29][9]	MAIN[27][29][9]	MAIN[37][29][9]
DRP[57] bit 4	MAIN[7][28][10]	MAIN[17][28][10]	MAIN[27][28][10]	MAIN[37][28][10]
DRP[57] bit 5	MAIN[7][29][10]	MAIN[17][29][10]	MAIN[27][29][10]	MAIN[37][29][10]
DRP[57] bit 6	MAIN[7][28][11]	MAIN[17][28][11]	MAIN[27][28][11]	MAIN[37][28][11]
DRP[57] bit 7	MAIN[7][29][11]	MAIN[17][29][11]	MAIN[27][29][11]	MAIN[37][29][11]
DRP[57] bit 8	MAIN[7][28][12]	MAIN[17][28][12]	MAIN[27][28][12]	MAIN[37][28][12]
DRP[57] bit 9	MAIN[7][29][12]	MAIN[17][29][12]	MAIN[27][29][12]	MAIN[37][29][12]
DRP[57] bit 10	MAIN[7][28][13]	MAIN[17][28][13]	MAIN[27][28][13]	MAIN[37][28][13]
DRP[57] bit 11	MAIN[7][29][13]	MAIN[17][29][13]	MAIN[27][29][13]	MAIN[37][29][13]
DRP[57] bit 12	MAIN[7][28][14]	MAIN[17][28][14]	MAIN[27][28][14]	MAIN[37][28][14]
DRP[57] bit 13	MAIN[7][29][14]	MAIN[17][29][14]	MAIN[27][29][14]	MAIN[37][29][14]
DRP[57] bit 14	MAIN[7][28][15]	MAIN[17][28][15]	MAIN[27][28][15]	MAIN[37][28][15]
DRP[57] bit 15	MAIN[7][29][15]	MAIN[17][29][15]	MAIN[27][29][15]	MAIN[37][29][15]
DRP[58] bit 0	MAIN[7][28][16]	MAIN[17][28][16]	MAIN[27][28][16]	MAIN[37][28][16]
DRP[58] bit 1	MAIN[7][29][16]	MAIN[17][29][16]	MAIN[27][29][16]	MAIN[37][29][16]
DRP[58] bit 2	MAIN[7][28][17]	MAIN[17][28][17]	MAIN[27][28][17]	MAIN[37][28][17]
DRP[58] bit 3	MAIN[7][29][17]	MAIN[17][29][17]	MAIN[27][29][17]	MAIN[37][29][17]
DRP[58] bit 4	MAIN[7][28][18]	MAIN[17][28][18]	MAIN[27][28][18]	MAIN[37][28][18]
DRP[58] bit 5	MAIN[7][29][18]	MAIN[17][29][18]	MAIN[27][29][18]	MAIN[37][29][18]
DRP[58] bit 6	MAIN[7][28][19]	MAIN[17][28][19]	MAIN[27][28][19]	MAIN[37][28][19]
DRP[58] bit 7	MAIN[7][29][19]	MAIN[17][29][19]	MAIN[27][29][19]	MAIN[37][29][19]
DRP[58] bit 8	MAIN[7][28][20]	MAIN[17][28][20]	MAIN[27][28][20]	MAIN[37][28][20]
DRP[58] bit 9	MAIN[7][29][20]	MAIN[17][29][20]	MAIN[27][29][20]	MAIN[37][29][20]
DRP[58] bit 10	MAIN[7][28][21]	MAIN[17][28][21]	MAIN[27][28][21]	MAIN[37][28][21]
DRP[58] bit 11	MAIN[7][29][21]	MAIN[17][29][21]	MAIN[27][29][21]	MAIN[37][29][21]
DRP[58] bit 12	MAIN[7][28][22]	MAIN[17][28][22]	MAIN[27][28][22]	MAIN[37][28][22]
DRP[58] bit 13	MAIN[7][29][22]	MAIN[17][29][22]	MAIN[27][29][22]	MAIN[37][29][22]
DRP[58] bit 14	MAIN[7][28][23]	MAIN[17][28][23]	MAIN[27][28][23]	MAIN[37][28][23]
DRP[58] bit 15	MAIN[7][29][23]	MAIN[17][29][23]	MAIN[27][29][23]	MAIN[37][29][23]
DRP[59] bit 0	MAIN[7][28][24]	MAIN[17][28][24]	MAIN[27][28][24]	MAIN[37][28][24]
DRP[59] bit 1	MAIN[7][29][24]	MAIN[17][29][24]	MAIN[27][29][24]	MAIN[37][29][24]
DRP[59] bit 2	MAIN[7][28][25]	MAIN[17][28][25]	MAIN[27][28][25]	MAIN[37][28][25]
DRP[59] bit 3	MAIN[7][29][25]	MAIN[17][29][25]	MAIN[27][29][25]	MAIN[37][29][25]
DRP[59] bit 4	MAIN[7][28][26]	MAIN[17][28][26]	MAIN[27][28][26]	MAIN[37][28][26]
DRP[59] bit 5	MAIN[7][29][26]	MAIN[17][29][26]	MAIN[27][29][26]	MAIN[37][29][26]
DRP[59] bit 6	MAIN[7][28][27]	MAIN[17][28][27]	MAIN[27][28][27]	MAIN[37][28][27]
DRP[59] bit 7	MAIN[7][29][27]	MAIN[17][29][27]	MAIN[27][29][27]	MAIN[37][29][27]
DRP[59] bit 8	MAIN[7][28][28]	MAIN[17][28][28]	MAIN[27][28][28]	MAIN[37][28][28]
DRP[59] bit 9	MAIN[7][29][28]	MAIN[17][29][28]	MAIN[27][29][28]	MAIN[37][29][28]
DRP[59] bit 10	MAIN[7][28][29]	MAIN[17][28][29]	MAIN[27][28][29]	MAIN[37][28][29]
DRP[59] bit 11	MAIN[7][29][29]	MAIN[17][29][29]	MAIN[27][29][29]	MAIN[37][29][29]
DRP[59] bit 12	MAIN[7][28][30]	MAIN[17][28][30]	MAIN[27][28][30]	MAIN[37][28][30]
DRP[59] bit 13	MAIN[7][29][30]	MAIN[17][29][30]	MAIN[27][29][30]	MAIN[37][29][30]
DRP[59] bit 14	MAIN[7][28][31]	MAIN[17][28][31]	MAIN[27][28][31]	MAIN[37][28][31]
DRP[59] bit 15	MAIN[7][29][31]	MAIN[17][29][31]	MAIN[27][29][31]	MAIN[37][29][31]
DRP[60] bit 0	MAIN[7][28][32]	MAIN[17][28][32]	MAIN[27][28][32]	MAIN[37][28][32]
DRP[60] bit 1	MAIN[7][29][32]	MAIN[17][29][32]	MAIN[27][29][32]	MAIN[37][29][32]
DRP[60] bit 2	MAIN[7][28][33]	MAIN[17][28][33]	MAIN[27][28][33]	MAIN[37][28][33]
DRP[60] bit 3	MAIN[7][29][33]	MAIN[17][29][33]	MAIN[27][29][33]	MAIN[37][29][33]
DRP[60] bit 4	MAIN[7][28][34]	MAIN[17][28][34]	MAIN[27][28][34]	MAIN[37][28][34]
DRP[60] bit 5	MAIN[7][29][34]	MAIN[17][29][34]	MAIN[27][29][34]	MAIN[37][29][34]
DRP[60] bit 6	MAIN[7][28][35]	MAIN[17][28][35]	MAIN[27][28][35]	MAIN[37][28][35]
DRP[60] bit 7	MAIN[7][29][35]	MAIN[17][29][35]	MAIN[27][29][35]	MAIN[37][29][35]
DRP[60] bit 8	MAIN[7][28][36]	MAIN[17][28][36]	MAIN[27][28][36]	MAIN[37][28][36]
DRP[60] bit 9	MAIN[7][29][36]	MAIN[17][29][36]	MAIN[27][29][36]	MAIN[37][29][36]
DRP[60] bit 10	MAIN[7][28][37]	MAIN[17][28][37]	MAIN[27][28][37]	MAIN[37][28][37]
DRP[60] bit 11	MAIN[7][29][37]	MAIN[17][29][37]	MAIN[27][29][37]	MAIN[37][29][37]
DRP[60] bit 12	MAIN[7][28][38]	MAIN[17][28][38]	MAIN[27][28][38]	MAIN[37][28][38]
DRP[60] bit 13	MAIN[7][29][38]	MAIN[17][29][38]	MAIN[27][29][38]	MAIN[37][29][38]
DRP[60] bit 14	MAIN[7][28][39]	MAIN[17][28][39]	MAIN[27][28][39]	MAIN[37][28][39]
DRP[60] bit 15	MAIN[7][29][39]	MAIN[17][29][39]	MAIN[27][29][39]	MAIN[37][29][39]
DRP[61] bit 0	MAIN[7][28][40]	MAIN[17][28][40]	MAIN[27][28][40]	MAIN[37][28][40]
DRP[61] bit 1	MAIN[7][29][40]	MAIN[17][29][40]	MAIN[27][29][40]	MAIN[37][29][40]
DRP[61] bit 2	MAIN[7][28][41]	MAIN[17][28][41]	MAIN[27][28][41]	MAIN[37][28][41]
DRP[61] bit 3	MAIN[7][29][41]	MAIN[17][29][41]	MAIN[27][29][41]	MAIN[37][29][41]
DRP[61] bit 4	MAIN[7][28][42]	MAIN[17][28][42]	MAIN[27][28][42]	MAIN[37][28][42]
DRP[61] bit 5	MAIN[7][29][42]	MAIN[17][29][42]	MAIN[27][29][42]	MAIN[37][29][42]
DRP[61] bit 6	MAIN[7][28][43]	MAIN[17][28][43]	MAIN[27][28][43]	MAIN[37][28][43]
DRP[61] bit 7	MAIN[7][29][43]	MAIN[17][29][43]	MAIN[27][29][43]	MAIN[37][29][43]
DRP[61] bit 8	MAIN[7][28][44]	MAIN[17][28][44]	MAIN[27][28][44]	MAIN[37][28][44]
DRP[61] bit 9	MAIN[7][29][44]	MAIN[17][29][44]	MAIN[27][29][44]	MAIN[37][29][44]
DRP[61] bit 10	MAIN[7][28][45]	MAIN[17][28][45]	MAIN[27][28][45]	MAIN[37][28][45]
DRP[61] bit 11	MAIN[7][29][45]	MAIN[17][29][45]	MAIN[27][29][45]	MAIN[37][29][45]
DRP[61] bit 12	MAIN[7][28][46]	MAIN[17][28][46]	MAIN[27][28][46]	MAIN[37][28][46]
DRP[61] bit 13	MAIN[7][29][46]	MAIN[17][29][46]	MAIN[27][29][46]	MAIN[37][29][46]
DRP[61] bit 14	MAIN[7][28][47]	MAIN[17][28][47]	MAIN[27][28][47]	MAIN[37][28][47]
DRP[61] bit 15	MAIN[7][29][47]	MAIN[17][29][47]	MAIN[27][29][47]	MAIN[37][29][47]
DRP[62] bit 0	MAIN[7][28][48]	MAIN[17][28][48]	MAIN[27][28][48]	MAIN[37][28][48]
DRP[62] bit 1	MAIN[7][29][48]	MAIN[17][29][48]	MAIN[27][29][48]	MAIN[37][29][48]
DRP[62] bit 2	MAIN[7][28][49]	MAIN[17][28][49]	MAIN[27][28][49]	MAIN[37][28][49]
DRP[62] bit 3	MAIN[7][29][49]	MAIN[17][29][49]	MAIN[27][29][49]	MAIN[37][29][49]
DRP[62] bit 4	MAIN[7][28][50]	MAIN[17][28][50]	MAIN[27][28][50]	MAIN[37][28][50]
DRP[62] bit 5	MAIN[7][29][50]	MAIN[17][29][50]	MAIN[27][29][50]	MAIN[37][29][50]
DRP[62] bit 6	MAIN[7][28][51]	MAIN[17][28][51]	MAIN[27][28][51]	MAIN[37][28][51]
DRP[62] bit 7	MAIN[7][29][51]	MAIN[17][29][51]	MAIN[27][29][51]	MAIN[37][29][51]
DRP[62] bit 8	MAIN[7][28][52]	MAIN[17][28][52]	MAIN[27][28][52]	MAIN[37][28][52]
DRP[62] bit 9	MAIN[7][29][52]	MAIN[17][29][52]	MAIN[27][29][52]	MAIN[37][29][52]
DRP[62] bit 10	MAIN[7][28][53]	MAIN[17][28][53]	MAIN[27][28][53]	MAIN[37][28][53]
DRP[62] bit 11	MAIN[7][29][53]	MAIN[17][29][53]	MAIN[27][29][53]	MAIN[37][29][53]
DRP[62] bit 12	MAIN[7][28][54]	MAIN[17][28][54]	MAIN[27][28][54]	MAIN[37][28][54]
DRP[62] bit 13	MAIN[7][29][54]	MAIN[17][29][54]	MAIN[27][29][54]	MAIN[37][29][54]
DRP[62] bit 14	MAIN[7][28][55]	MAIN[17][28][55]	MAIN[27][28][55]	MAIN[37][28][55]
DRP[62] bit 15	MAIN[7][29][55]	MAIN[17][29][55]	MAIN[27][29][55]	MAIN[37][29][55]
DRP[63] bit 0	MAIN[7][28][56]	MAIN[17][28][56]	MAIN[27][28][56]	MAIN[37][28][56]
DRP[63] bit 1	MAIN[7][29][56]	MAIN[17][29][56]	MAIN[27][29][56]	MAIN[37][29][56]
DRP[63] bit 2	MAIN[7][28][57]	MAIN[17][28][57]	MAIN[27][28][57]	MAIN[37][28][57]
DRP[63] bit 3	MAIN[7][29][57]	MAIN[17][29][57]	MAIN[27][29][57]	MAIN[37][29][57]
DRP[63] bit 4	MAIN[7][28][58]	MAIN[17][28][58]	MAIN[27][28][58]	MAIN[37][28][58]
DRP[63] bit 5	MAIN[7][29][58]	MAIN[17][29][58]	MAIN[27][29][58]	MAIN[37][29][58]
DRP[63] bit 6	MAIN[7][28][59]	MAIN[17][28][59]	MAIN[27][28][59]	MAIN[37][28][59]
DRP[63] bit 7	MAIN[7][29][59]	MAIN[17][29][59]	MAIN[27][29][59]	MAIN[37][29][59]
DRP[63] bit 8	MAIN[7][28][60]	MAIN[17][28][60]	MAIN[27][28][60]	MAIN[37][28][60]
DRP[63] bit 9	MAIN[7][29][60]	MAIN[17][29][60]	MAIN[27][29][60]	MAIN[37][29][60]
DRP[63] bit 10	MAIN[7][28][61]	MAIN[17][28][61]	MAIN[27][28][61]	MAIN[37][28][61]
DRP[63] bit 11	MAIN[7][29][61]	MAIN[17][29][61]	MAIN[27][29][61]	MAIN[37][29][61]
DRP[63] bit 12	MAIN[7][28][62]	MAIN[17][28][62]	MAIN[27][28][62]	MAIN[37][28][62]
DRP[63] bit 13	MAIN[7][29][62]	MAIN[17][29][62]	MAIN[27][29][62]	MAIN[37][29][62]
DRP[63] bit 14	MAIN[7][28][63]	MAIN[17][28][63]	MAIN[27][28][63]	MAIN[37][28][63]
DRP[63] bit 15	MAIN[7][29][63]	MAIN[17][29][63]	MAIN[27][29][63]	MAIN[37][29][63]
DRP[64] bit 0	MAIN[8][28][0]	MAIN[18][28][0]	MAIN[28][28][0]	MAIN[38][28][0]
DRP[64] bit 1	MAIN[8][29][0]	MAIN[18][29][0]	MAIN[28][29][0]	MAIN[38][29][0]
DRP[64] bit 2	MAIN[8][28][1]	MAIN[18][28][1]	MAIN[28][28][1]	MAIN[38][28][1]
DRP[64] bit 3	MAIN[8][29][1]	MAIN[18][29][1]	MAIN[28][29][1]	MAIN[38][29][1]
DRP[64] bit 4	MAIN[8][28][2]	MAIN[18][28][2]	MAIN[28][28][2]	MAIN[38][28][2]
DRP[64] bit 5	MAIN[8][29][2]	MAIN[18][29][2]	MAIN[28][29][2]	MAIN[38][29][2]
DRP[64] bit 6	MAIN[8][28][3]	MAIN[18][28][3]	MAIN[28][28][3]	MAIN[38][28][3]
DRP[64] bit 7	MAIN[8][29][3]	MAIN[18][29][3]	MAIN[28][29][3]	MAIN[38][29][3]
DRP[64] bit 8	MAIN[8][28][4]	MAIN[18][28][4]	MAIN[28][28][4]	MAIN[38][28][4]
DRP[64] bit 9	MAIN[8][29][4]	MAIN[18][29][4]	MAIN[28][29][4]	MAIN[38][29][4]
DRP[64] bit 10	MAIN[8][28][5]	MAIN[18][28][5]	MAIN[28][28][5]	MAIN[38][28][5]
DRP[64] bit 11	MAIN[8][29][5]	MAIN[18][29][5]	MAIN[28][29][5]	MAIN[38][29][5]
DRP[64] bit 12	MAIN[8][28][6]	MAIN[18][28][6]	MAIN[28][28][6]	MAIN[38][28][6]
DRP[64] bit 13	MAIN[8][29][6]	MAIN[18][29][6]	MAIN[28][29][6]	MAIN[38][29][6]
DRP[64] bit 14	MAIN[8][28][7]	MAIN[18][28][7]	MAIN[28][28][7]	MAIN[38][28][7]
DRP[64] bit 15	MAIN[8][29][7]	MAIN[18][29][7]	MAIN[28][29][7]	MAIN[38][29][7]
DRP[65] bit 0	MAIN[8][28][8]	MAIN[18][28][8]	MAIN[28][28][8]	MAIN[38][28][8]
DRP[65] bit 1	MAIN[8][29][8]	MAIN[18][29][8]	MAIN[28][29][8]	MAIN[38][29][8]
DRP[65] bit 2	MAIN[8][28][9]	MAIN[18][28][9]	MAIN[28][28][9]	MAIN[38][28][9]
DRP[65] bit 3	MAIN[8][29][9]	MAIN[18][29][9]	MAIN[28][29][9]	MAIN[38][29][9]
DRP[65] bit 4	MAIN[8][28][10]	MAIN[18][28][10]	MAIN[28][28][10]	MAIN[38][28][10]
DRP[65] bit 5	MAIN[8][29][10]	MAIN[18][29][10]	MAIN[28][29][10]	MAIN[38][29][10]
DRP[65] bit 6	MAIN[8][28][11]	MAIN[18][28][11]	MAIN[28][28][11]	MAIN[38][28][11]
DRP[65] bit 7	MAIN[8][29][11]	MAIN[18][29][11]	MAIN[28][29][11]	MAIN[38][29][11]
DRP[65] bit 8	MAIN[8][28][12]	MAIN[18][28][12]	MAIN[28][28][12]	MAIN[38][28][12]
DRP[65] bit 9	MAIN[8][29][12]	MAIN[18][29][12]	MAIN[28][29][12]	MAIN[38][29][12]
DRP[65] bit 10	MAIN[8][28][13]	MAIN[18][28][13]	MAIN[28][28][13]	MAIN[38][28][13]
DRP[65] bit 11	MAIN[8][29][13]	MAIN[18][29][13]	MAIN[28][29][13]	MAIN[38][29][13]
DRP[65] bit 12	MAIN[8][28][14]	MAIN[18][28][14]	MAIN[28][28][14]	MAIN[38][28][14]
DRP[65] bit 13	MAIN[8][29][14]	MAIN[18][29][14]	MAIN[28][29][14]	MAIN[38][29][14]
DRP[65] bit 14	MAIN[8][28][15]	MAIN[18][28][15]	MAIN[28][28][15]	MAIN[38][28][15]
DRP[65] bit 15	MAIN[8][29][15]	MAIN[18][29][15]	MAIN[28][29][15]	MAIN[38][29][15]
DRP[66] bit 0	MAIN[8][28][16]	MAIN[18][28][16]	MAIN[28][28][16]	MAIN[38][28][16]
DRP[66] bit 1	MAIN[8][29][16]	MAIN[18][29][16]	MAIN[28][29][16]	MAIN[38][29][16]
DRP[66] bit 2	MAIN[8][28][17]	MAIN[18][28][17]	MAIN[28][28][17]	MAIN[38][28][17]
DRP[66] bit 3	MAIN[8][29][17]	MAIN[18][29][17]	MAIN[28][29][17]	MAIN[38][29][17]
DRP[66] bit 4	MAIN[8][28][18]	MAIN[18][28][18]	MAIN[28][28][18]	MAIN[38][28][18]
DRP[66] bit 5	MAIN[8][29][18]	MAIN[18][29][18]	MAIN[28][29][18]	MAIN[38][29][18]
DRP[66] bit 6	MAIN[8][28][19]	MAIN[18][28][19]	MAIN[28][28][19]	MAIN[38][28][19]
DRP[66] bit 7	MAIN[8][29][19]	MAIN[18][29][19]	MAIN[28][29][19]	MAIN[38][29][19]
DRP[66] bit 8	MAIN[8][28][20]	MAIN[18][28][20]	MAIN[28][28][20]	MAIN[38][28][20]
DRP[66] bit 9	MAIN[8][29][20]	MAIN[18][29][20]	MAIN[28][29][20]	MAIN[38][29][20]
DRP[66] bit 10	MAIN[8][28][21]	MAIN[18][28][21]	MAIN[28][28][21]	MAIN[38][28][21]
DRP[66] bit 11	MAIN[8][29][21]	MAIN[18][29][21]	MAIN[28][29][21]	MAIN[38][29][21]
DRP[66] bit 12	MAIN[8][28][22]	MAIN[18][28][22]	MAIN[28][28][22]	MAIN[38][28][22]
DRP[66] bit 13	MAIN[8][29][22]	MAIN[18][29][22]	MAIN[28][29][22]	MAIN[38][29][22]
DRP[66] bit 14	MAIN[8][28][23]	MAIN[18][28][23]	MAIN[28][28][23]	MAIN[38][28][23]
DRP[66] bit 15	MAIN[8][29][23]	MAIN[18][29][23]	MAIN[28][29][23]	MAIN[38][29][23]
DRP[67] bit 0	MAIN[8][28][24]	MAIN[18][28][24]	MAIN[28][28][24]	MAIN[38][28][24]
DRP[67] bit 1	MAIN[8][29][24]	MAIN[18][29][24]	MAIN[28][29][24]	MAIN[38][29][24]
DRP[67] bit 2	MAIN[8][28][25]	MAIN[18][28][25]	MAIN[28][28][25]	MAIN[38][28][25]
DRP[67] bit 3	MAIN[8][29][25]	MAIN[18][29][25]	MAIN[28][29][25]	MAIN[38][29][25]
DRP[67] bit 4	MAIN[8][28][26]	MAIN[18][28][26]	MAIN[28][28][26]	MAIN[38][28][26]
DRP[67] bit 5	MAIN[8][29][26]	MAIN[18][29][26]	MAIN[28][29][26]	MAIN[38][29][26]
DRP[67] bit 6	MAIN[8][28][27]	MAIN[18][28][27]	MAIN[28][28][27]	MAIN[38][28][27]
DRP[67] bit 7	MAIN[8][29][27]	MAIN[18][29][27]	MAIN[28][29][27]	MAIN[38][29][27]
DRP[67] bit 8	MAIN[8][28][28]	MAIN[18][28][28]	MAIN[28][28][28]	MAIN[38][28][28]
DRP[67] bit 9	MAIN[8][29][28]	MAIN[18][29][28]	MAIN[28][29][28]	MAIN[38][29][28]
DRP[67] bit 10	MAIN[8][28][29]	MAIN[18][28][29]	MAIN[28][28][29]	MAIN[38][28][29]
DRP[67] bit 11	MAIN[8][29][29]	MAIN[18][29][29]	MAIN[28][29][29]	MAIN[38][29][29]
DRP[67] bit 12	MAIN[8][28][30]	MAIN[18][28][30]	MAIN[28][28][30]	MAIN[38][28][30]
DRP[67] bit 13	MAIN[8][29][30]	MAIN[18][29][30]	MAIN[28][29][30]	MAIN[38][29][30]
DRP[67] bit 14	MAIN[8][28][31]	MAIN[18][28][31]	MAIN[28][28][31]	MAIN[38][28][31]
DRP[67] bit 15	MAIN[8][29][31]	MAIN[18][29][31]	MAIN[28][29][31]	MAIN[38][29][31]
DRP[68] bit 0	MAIN[8][28][32]	MAIN[18][28][32]	MAIN[28][28][32]	MAIN[38][28][32]
DRP[68] bit 1	MAIN[8][29][32]	MAIN[18][29][32]	MAIN[28][29][32]	MAIN[38][29][32]
DRP[68] bit 2	MAIN[8][28][33]	MAIN[18][28][33]	MAIN[28][28][33]	MAIN[38][28][33]
DRP[68] bit 3	MAIN[8][29][33]	MAIN[18][29][33]	MAIN[28][29][33]	MAIN[38][29][33]
DRP[68] bit 4	MAIN[8][28][34]	MAIN[18][28][34]	MAIN[28][28][34]	MAIN[38][28][34]
DRP[68] bit 5	MAIN[8][29][34]	MAIN[18][29][34]	MAIN[28][29][34]	MAIN[38][29][34]
DRP[68] bit 6	MAIN[8][28][35]	MAIN[18][28][35]	MAIN[28][28][35]	MAIN[38][28][35]
DRP[68] bit 7	MAIN[8][29][35]	MAIN[18][29][35]	MAIN[28][29][35]	MAIN[38][29][35]
DRP[68] bit 8	MAIN[8][28][36]	MAIN[18][28][36]	MAIN[28][28][36]	MAIN[38][28][36]
DRP[68] bit 9	MAIN[8][29][36]	MAIN[18][29][36]	MAIN[28][29][36]	MAIN[38][29][36]
DRP[68] bit 10	MAIN[8][28][37]	MAIN[18][28][37]	MAIN[28][28][37]	MAIN[38][28][37]
DRP[68] bit 11	MAIN[8][29][37]	MAIN[18][29][37]	MAIN[28][29][37]	MAIN[38][29][37]
DRP[68] bit 12	MAIN[8][28][38]	MAIN[18][28][38]	MAIN[28][28][38]	MAIN[38][28][38]
DRP[68] bit 13	MAIN[8][29][38]	MAIN[18][29][38]	MAIN[28][29][38]	MAIN[38][29][38]
DRP[68] bit 14	MAIN[8][28][39]	MAIN[18][28][39]	MAIN[28][28][39]	MAIN[38][28][39]
DRP[68] bit 15	MAIN[8][29][39]	MAIN[18][29][39]	MAIN[28][29][39]	MAIN[38][29][39]
DRP[69] bit 0	MAIN[8][28][40]	MAIN[18][28][40]	MAIN[28][28][40]	MAIN[38][28][40]
DRP[69] bit 1	MAIN[8][29][40]	MAIN[18][29][40]	MAIN[28][29][40]	MAIN[38][29][40]
DRP[69] bit 2	MAIN[8][28][41]	MAIN[18][28][41]	MAIN[28][28][41]	MAIN[38][28][41]
DRP[69] bit 3	MAIN[8][29][41]	MAIN[18][29][41]	MAIN[28][29][41]	MAIN[38][29][41]
DRP[69] bit 4	MAIN[8][28][42]	MAIN[18][28][42]	MAIN[28][28][42]	MAIN[38][28][42]
DRP[69] bit 5	MAIN[8][29][42]	MAIN[18][29][42]	MAIN[28][29][42]	MAIN[38][29][42]
DRP[69] bit 6	MAIN[8][28][43]	MAIN[18][28][43]	MAIN[28][28][43]	MAIN[38][28][43]
DRP[69] bit 7	MAIN[8][29][43]	MAIN[18][29][43]	MAIN[28][29][43]	MAIN[38][29][43]
DRP[69] bit 8	MAIN[8][28][44]	MAIN[18][28][44]	MAIN[28][28][44]	MAIN[38][28][44]
DRP[69] bit 9	MAIN[8][29][44]	MAIN[18][29][44]	MAIN[28][29][44]	MAIN[38][29][44]
DRP[69] bit 10	MAIN[8][28][45]	MAIN[18][28][45]	MAIN[28][28][45]	MAIN[38][28][45]
DRP[69] bit 11	MAIN[8][29][45]	MAIN[18][29][45]	MAIN[28][29][45]	MAIN[38][29][45]
DRP[69] bit 12	MAIN[8][28][46]	MAIN[18][28][46]	MAIN[28][28][46]	MAIN[38][28][46]
DRP[69] bit 13	MAIN[8][29][46]	MAIN[18][29][46]	MAIN[28][29][46]	MAIN[38][29][46]
DRP[69] bit 14	MAIN[8][28][47]	MAIN[18][28][47]	MAIN[28][28][47]	MAIN[38][28][47]
DRP[69] bit 15	MAIN[8][29][47]	MAIN[18][29][47]	MAIN[28][29][47]	MAIN[38][29][47]
DRP[70] bit 0	MAIN[8][28][48]	MAIN[18][28][48]	MAIN[28][28][48]	MAIN[38][28][48]
DRP[70] bit 1	MAIN[8][29][48]	MAIN[18][29][48]	MAIN[28][29][48]	MAIN[38][29][48]
DRP[70] bit 2	MAIN[8][28][49]	MAIN[18][28][49]	MAIN[28][28][49]	MAIN[38][28][49]
DRP[70] bit 3	MAIN[8][29][49]	MAIN[18][29][49]	MAIN[28][29][49]	MAIN[38][29][49]
DRP[70] bit 4	MAIN[8][28][50]	MAIN[18][28][50]	MAIN[28][28][50]	MAIN[38][28][50]
DRP[70] bit 5	MAIN[8][29][50]	MAIN[18][29][50]	MAIN[28][29][50]	MAIN[38][29][50]
DRP[70] bit 6	MAIN[8][28][51]	MAIN[18][28][51]	MAIN[28][28][51]	MAIN[38][28][51]
DRP[70] bit 7	MAIN[8][29][51]	MAIN[18][29][51]	MAIN[28][29][51]	MAIN[38][29][51]
DRP[70] bit 8	MAIN[8][28][52]	MAIN[18][28][52]	MAIN[28][28][52]	MAIN[38][28][52]
DRP[70] bit 9	MAIN[8][29][52]	MAIN[18][29][52]	MAIN[28][29][52]	MAIN[38][29][52]
DRP[70] bit 10	MAIN[8][28][53]	MAIN[18][28][53]	MAIN[28][28][53]	MAIN[38][28][53]
DRP[70] bit 11	MAIN[8][29][53]	MAIN[18][29][53]	MAIN[28][29][53]	MAIN[38][29][53]
DRP[70] bit 12	MAIN[8][28][54]	MAIN[18][28][54]	MAIN[28][28][54]	MAIN[38][28][54]
DRP[70] bit 13	MAIN[8][29][54]	MAIN[18][29][54]	MAIN[28][29][54]	MAIN[38][29][54]
DRP[70] bit 14	MAIN[8][28][55]	MAIN[18][28][55]	MAIN[28][28][55]	MAIN[38][28][55]
DRP[70] bit 15	MAIN[8][29][55]	MAIN[18][29][55]	MAIN[28][29][55]	MAIN[38][29][55]
DRP[71] bit 0	MAIN[8][28][56]	MAIN[18][28][56]	MAIN[28][28][56]	MAIN[38][28][56]
DRP[71] bit 1	MAIN[8][29][56]	MAIN[18][29][56]	MAIN[28][29][56]	MAIN[38][29][56]
DRP[71] bit 2	MAIN[8][28][57]	MAIN[18][28][57]	MAIN[28][28][57]	MAIN[38][28][57]
DRP[71] bit 3	MAIN[8][29][57]	MAIN[18][29][57]	MAIN[28][29][57]	MAIN[38][29][57]
DRP[71] bit 4	MAIN[8][28][58]	MAIN[18][28][58]	MAIN[28][28][58]	MAIN[38][28][58]
DRP[71] bit 5	MAIN[8][29][58]	MAIN[18][29][58]	MAIN[28][29][58]	MAIN[38][29][58]
DRP[71] bit 6	MAIN[8][28][59]	MAIN[18][28][59]	MAIN[28][28][59]	MAIN[38][28][59]
DRP[71] bit 7	MAIN[8][29][59]	MAIN[18][29][59]	MAIN[28][29][59]	MAIN[38][29][59]
DRP[71] bit 8	MAIN[8][28][60]	MAIN[18][28][60]	MAIN[28][28][60]	MAIN[38][28][60]
DRP[71] bit 9	MAIN[8][29][60]	MAIN[18][29][60]	MAIN[28][29][60]	MAIN[38][29][60]
DRP[71] bit 10	MAIN[8][28][61]	MAIN[18][28][61]	MAIN[28][28][61]	MAIN[38][28][61]
DRP[71] bit 11	MAIN[8][29][61]	MAIN[18][29][61]	MAIN[28][29][61]	MAIN[38][29][61]
DRP[71] bit 12	MAIN[8][28][62]	MAIN[18][28][62]	MAIN[28][28][62]	MAIN[38][28][62]
DRP[71] bit 13	MAIN[8][29][62]	MAIN[18][29][62]	MAIN[28][29][62]	MAIN[38][29][62]
DRP[71] bit 14	MAIN[8][28][63]	MAIN[18][28][63]	MAIN[28][28][63]	MAIN[38][28][63]
DRP[71] bit 15	MAIN[8][29][63]	MAIN[18][29][63]	MAIN[28][29][63]	MAIN[38][29][63]
DRP[72] bit 0	MAIN[9][28][0]	MAIN[19][28][0]	MAIN[29][28][0]	MAIN[39][28][0]
DRP[72] bit 1	MAIN[9][29][0]	MAIN[19][29][0]	MAIN[29][29][0]	MAIN[39][29][0]
DRP[72] bit 2	MAIN[9][28][1]	MAIN[19][28][1]	MAIN[29][28][1]	MAIN[39][28][1]
DRP[72] bit 3	MAIN[9][29][1]	MAIN[19][29][1]	MAIN[29][29][1]	MAIN[39][29][1]
DRP[72] bit 4	MAIN[9][28][2]	MAIN[19][28][2]	MAIN[29][28][2]	MAIN[39][28][2]
DRP[72] bit 5	MAIN[9][29][2]	MAIN[19][29][2]	MAIN[29][29][2]	MAIN[39][29][2]
DRP[72] bit 6	MAIN[9][28][3]	MAIN[19][28][3]	MAIN[29][28][3]	MAIN[39][28][3]
DRP[72] bit 7	MAIN[9][29][3]	MAIN[19][29][3]	MAIN[29][29][3]	MAIN[39][29][3]
DRP[72] bit 8	MAIN[9][28][4]	MAIN[19][28][4]	MAIN[29][28][4]	MAIN[39][28][4]
DRP[72] bit 9	MAIN[9][29][4]	MAIN[19][29][4]	MAIN[29][29][4]	MAIN[39][29][4]
DRP[72] bit 10	MAIN[9][28][5]	MAIN[19][28][5]	MAIN[29][28][5]	MAIN[39][28][5]
DRP[72] bit 11	MAIN[9][29][5]	MAIN[19][29][5]	MAIN[29][29][5]	MAIN[39][29][5]
DRP[72] bit 12	MAIN[9][28][6]	MAIN[19][28][6]	MAIN[29][28][6]	MAIN[39][28][6]
DRP[72] bit 13	MAIN[9][29][6]	MAIN[19][29][6]	MAIN[29][29][6]	MAIN[39][29][6]
DRP[72] bit 14	MAIN[9][28][7]	MAIN[19][28][7]	MAIN[29][28][7]	MAIN[39][28][7]
DRP[72] bit 15	MAIN[9][29][7]	MAIN[19][29][7]	MAIN[29][29][7]	MAIN[39][29][7]
DRP[73] bit 0	MAIN[9][28][8]	MAIN[19][28][8]	MAIN[29][28][8]	MAIN[39][28][8]
DRP[73] bit 1	MAIN[9][29][8]	MAIN[19][29][8]	MAIN[29][29][8]	MAIN[39][29][8]
DRP[73] bit 2	MAIN[9][28][9]	MAIN[19][28][9]	MAIN[29][28][9]	MAIN[39][28][9]
DRP[73] bit 3	MAIN[9][29][9]	MAIN[19][29][9]	MAIN[29][29][9]	MAIN[39][29][9]
DRP[73] bit 4	MAIN[9][28][10]	MAIN[19][28][10]	MAIN[29][28][10]	MAIN[39][28][10]
DRP[73] bit 5	MAIN[9][29][10]	MAIN[19][29][10]	MAIN[29][29][10]	MAIN[39][29][10]
DRP[73] bit 6	MAIN[9][28][11]	MAIN[19][28][11]	MAIN[29][28][11]	MAIN[39][28][11]
DRP[73] bit 7	MAIN[9][29][11]	MAIN[19][29][11]	MAIN[29][29][11]	MAIN[39][29][11]
DRP[73] bit 8	MAIN[9][28][12]	MAIN[19][28][12]	MAIN[29][28][12]	MAIN[39][28][12]
DRP[73] bit 9	MAIN[9][29][12]	MAIN[19][29][12]	MAIN[29][29][12]	MAIN[39][29][12]
DRP[73] bit 10	MAIN[9][28][13]	MAIN[19][28][13]	MAIN[29][28][13]	MAIN[39][28][13]
DRP[73] bit 11	MAIN[9][29][13]	MAIN[19][29][13]	MAIN[29][29][13]	MAIN[39][29][13]
DRP[73] bit 12	MAIN[9][28][14]	MAIN[19][28][14]	MAIN[29][28][14]	MAIN[39][28][14]
DRP[73] bit 13	MAIN[9][29][14]	MAIN[19][29][14]	MAIN[29][29][14]	MAIN[39][29][14]
DRP[73] bit 14	MAIN[9][28][15]	MAIN[19][28][15]	MAIN[29][28][15]	MAIN[39][28][15]
DRP[73] bit 15	MAIN[9][29][15]	MAIN[19][29][15]	MAIN[29][29][15]	MAIN[39][29][15]
DRP[74] bit 0	MAIN[9][28][16]	MAIN[19][28][16]	MAIN[29][28][16]	MAIN[39][28][16]
DRP[74] bit 1	MAIN[9][29][16]	MAIN[19][29][16]	MAIN[29][29][16]	MAIN[39][29][16]
DRP[74] bit 2	MAIN[9][28][17]	MAIN[19][28][17]	MAIN[29][28][17]	MAIN[39][28][17]
DRP[74] bit 3	MAIN[9][29][17]	MAIN[19][29][17]	MAIN[29][29][17]	MAIN[39][29][17]
DRP[74] bit 4	MAIN[9][28][18]	MAIN[19][28][18]	MAIN[29][28][18]	MAIN[39][28][18]
DRP[74] bit 5	MAIN[9][29][18]	MAIN[19][29][18]	MAIN[29][29][18]	MAIN[39][29][18]
DRP[74] bit 6	MAIN[9][28][19]	MAIN[19][28][19]	MAIN[29][28][19]	MAIN[39][28][19]
DRP[74] bit 7	MAIN[9][29][19]	MAIN[19][29][19]	MAIN[29][29][19]	MAIN[39][29][19]
DRP[74] bit 8	MAIN[9][28][20]	MAIN[19][28][20]	MAIN[29][28][20]	MAIN[39][28][20]
DRP[74] bit 9	MAIN[9][29][20]	MAIN[19][29][20]	MAIN[29][29][20]	MAIN[39][29][20]
DRP[74] bit 10	MAIN[9][28][21]	MAIN[19][28][21]	MAIN[29][28][21]	MAIN[39][28][21]
DRP[74] bit 11	MAIN[9][29][21]	MAIN[19][29][21]	MAIN[29][29][21]	MAIN[39][29][21]
DRP[74] bit 12	MAIN[9][28][22]	MAIN[19][28][22]	MAIN[29][28][22]	MAIN[39][28][22]
DRP[74] bit 13	MAIN[9][29][22]	MAIN[19][29][22]	MAIN[29][29][22]	MAIN[39][29][22]
DRP[74] bit 14	MAIN[9][28][23]	MAIN[19][28][23]	MAIN[29][28][23]	MAIN[39][28][23]
DRP[74] bit 15	MAIN[9][29][23]	MAIN[19][29][23]	MAIN[29][29][23]	MAIN[39][29][23]
DRP[75] bit 0	MAIN[9][28][24]	MAIN[19][28][24]	MAIN[29][28][24]	MAIN[39][28][24]
DRP[75] bit 1	MAIN[9][29][24]	MAIN[19][29][24]	MAIN[29][29][24]	MAIN[39][29][24]
DRP[75] bit 2	MAIN[9][28][25]	MAIN[19][28][25]	MAIN[29][28][25]	MAIN[39][28][25]
DRP[75] bit 3	MAIN[9][29][25]	MAIN[19][29][25]	MAIN[29][29][25]	MAIN[39][29][25]
DRP[75] bit 4	MAIN[9][28][26]	MAIN[19][28][26]	MAIN[29][28][26]	MAIN[39][28][26]
DRP[75] bit 5	MAIN[9][29][26]	MAIN[19][29][26]	MAIN[29][29][26]	MAIN[39][29][26]
DRP[75] bit 6	MAIN[9][28][27]	MAIN[19][28][27]	MAIN[29][28][27]	MAIN[39][28][27]
DRP[75] bit 7	MAIN[9][29][27]	MAIN[19][29][27]	MAIN[29][29][27]	MAIN[39][29][27]
DRP[75] bit 8	MAIN[9][28][28]	MAIN[19][28][28]	MAIN[29][28][28]	MAIN[39][28][28]
DRP[75] bit 9	MAIN[9][29][28]	MAIN[19][29][28]	MAIN[29][29][28]	MAIN[39][29][28]
DRP[75] bit 10	MAIN[9][28][29]	MAIN[19][28][29]	MAIN[29][28][29]	MAIN[39][28][29]
DRP[75] bit 11	MAIN[9][29][29]	MAIN[19][29][29]	MAIN[29][29][29]	MAIN[39][29][29]
DRP[75] bit 12	MAIN[9][28][30]	MAIN[19][28][30]	MAIN[29][28][30]	MAIN[39][28][30]
DRP[75] bit 13	MAIN[9][29][30]	MAIN[19][29][30]	MAIN[29][29][30]	MAIN[39][29][30]
DRP[75] bit 14	MAIN[9][28][31]	MAIN[19][28][31]	MAIN[29][28][31]	MAIN[39][28][31]
DRP[75] bit 15	MAIN[9][29][31]	MAIN[19][29][31]	MAIN[29][29][31]	MAIN[39][29][31]
DRP[76] bit 0	MAIN[9][28][32]	MAIN[19][28][32]	MAIN[29][28][32]	MAIN[39][28][32]
DRP[76] bit 1	MAIN[9][29][32]	MAIN[19][29][32]	MAIN[29][29][32]	MAIN[39][29][32]
DRP[76] bit 2	MAIN[9][28][33]	MAIN[19][28][33]	MAIN[29][28][33]	MAIN[39][28][33]
DRP[76] bit 3	MAIN[9][29][33]	MAIN[19][29][33]	MAIN[29][29][33]	MAIN[39][29][33]
DRP[76] bit 4	MAIN[9][28][34]	MAIN[19][28][34]	MAIN[29][28][34]	MAIN[39][28][34]
DRP[76] bit 5	MAIN[9][29][34]	MAIN[19][29][34]	MAIN[29][29][34]	MAIN[39][29][34]
DRP[76] bit 6	MAIN[9][28][35]	MAIN[19][28][35]	MAIN[29][28][35]	MAIN[39][28][35]
DRP[76] bit 7	MAIN[9][29][35]	MAIN[19][29][35]	MAIN[29][29][35]	MAIN[39][29][35]
DRP[76] bit 8	MAIN[9][28][36]	MAIN[19][28][36]	MAIN[29][28][36]	MAIN[39][28][36]
DRP[76] bit 9	MAIN[9][29][36]	MAIN[19][29][36]	MAIN[29][29][36]	MAIN[39][29][36]
DRP[76] bit 10	MAIN[9][28][37]	MAIN[19][28][37]	MAIN[29][28][37]	MAIN[39][28][37]
DRP[76] bit 11	MAIN[9][29][37]	MAIN[19][29][37]	MAIN[29][29][37]	MAIN[39][29][37]
DRP[76] bit 12	MAIN[9][28][38]	MAIN[19][28][38]	MAIN[29][28][38]	MAIN[39][28][38]
DRP[76] bit 13	MAIN[9][29][38]	MAIN[19][29][38]	MAIN[29][29][38]	MAIN[39][29][38]
DRP[76] bit 14	MAIN[9][28][39]	MAIN[19][28][39]	MAIN[29][28][39]	MAIN[39][28][39]
DRP[76] bit 15	MAIN[9][29][39]	MAIN[19][29][39]	MAIN[29][29][39]	MAIN[39][29][39]
DRP[77] bit 0	MAIN[9][28][40]	MAIN[19][28][40]	MAIN[29][28][40]	MAIN[39][28][40]
DRP[77] bit 1	MAIN[9][29][40]	MAIN[19][29][40]	MAIN[29][29][40]	MAIN[39][29][40]
DRP[77] bit 2	MAIN[9][28][41]	MAIN[19][28][41]	MAIN[29][28][41]	MAIN[39][28][41]
DRP[77] bit 3	MAIN[9][29][41]	MAIN[19][29][41]	MAIN[29][29][41]	MAIN[39][29][41]
DRP[77] bit 4	MAIN[9][28][42]	MAIN[19][28][42]	MAIN[29][28][42]	MAIN[39][28][42]
DRP[77] bit 5	MAIN[9][29][42]	MAIN[19][29][42]	MAIN[29][29][42]	MAIN[39][29][42]
DRP[77] bit 6	MAIN[9][28][43]	MAIN[19][28][43]	MAIN[29][28][43]	MAIN[39][28][43]
DRP[77] bit 7	MAIN[9][29][43]	MAIN[19][29][43]	MAIN[29][29][43]	MAIN[39][29][43]
DRP[77] bit 8	MAIN[9][28][44]	MAIN[19][28][44]	MAIN[29][28][44]	MAIN[39][28][44]
DRP[77] bit 9	MAIN[9][29][44]	MAIN[19][29][44]	MAIN[29][29][44]	MAIN[39][29][44]
DRP[77] bit 10	MAIN[9][28][45]	MAIN[19][28][45]	MAIN[29][28][45]	MAIN[39][28][45]
DRP[77] bit 11	MAIN[9][29][45]	MAIN[19][29][45]	MAIN[29][29][45]	MAIN[39][29][45]
DRP[77] bit 12	MAIN[9][28][46]	MAIN[19][28][46]	MAIN[29][28][46]	MAIN[39][28][46]
DRP[77] bit 13	MAIN[9][29][46]	MAIN[19][29][46]	MAIN[29][29][46]	MAIN[39][29][46]
DRP[77] bit 14	MAIN[9][28][47]	MAIN[19][28][47]	MAIN[29][28][47]	MAIN[39][28][47]
DRP[77] bit 15	MAIN[9][29][47]	MAIN[19][29][47]	MAIN[29][29][47]	MAIN[39][29][47]
DRP[78] bit 0	MAIN[9][28][48]	MAIN[19][28][48]	MAIN[29][28][48]	MAIN[39][28][48]
DRP[78] bit 1	MAIN[9][29][48]	MAIN[19][29][48]	MAIN[29][29][48]	MAIN[39][29][48]
DRP[78] bit 2	MAIN[9][28][49]	MAIN[19][28][49]	MAIN[29][28][49]	MAIN[39][28][49]
DRP[78] bit 3	MAIN[9][29][49]	MAIN[19][29][49]	MAIN[29][29][49]	MAIN[39][29][49]
DRP[78] bit 4	MAIN[9][28][50]	MAIN[19][28][50]	MAIN[29][28][50]	MAIN[39][28][50]
DRP[78] bit 5	MAIN[9][29][50]	MAIN[19][29][50]	MAIN[29][29][50]	MAIN[39][29][50]
DRP[78] bit 6	MAIN[9][28][51]	MAIN[19][28][51]	MAIN[29][28][51]	MAIN[39][28][51]
DRP[78] bit 7	MAIN[9][29][51]	MAIN[19][29][51]	MAIN[29][29][51]	MAIN[39][29][51]
DRP[78] bit 8	MAIN[9][28][52]	MAIN[19][28][52]	MAIN[29][28][52]	MAIN[39][28][52]
DRP[78] bit 9	MAIN[9][29][52]	MAIN[19][29][52]	MAIN[29][29][52]	MAIN[39][29][52]
DRP[78] bit 10	MAIN[9][28][53]	MAIN[19][28][53]	MAIN[29][28][53]	MAIN[39][28][53]
DRP[78] bit 11	MAIN[9][29][53]	MAIN[19][29][53]	MAIN[29][29][53]	MAIN[39][29][53]
DRP[78] bit 12	MAIN[9][28][54]	MAIN[19][28][54]	MAIN[29][28][54]	MAIN[39][28][54]
DRP[78] bit 13	MAIN[9][29][54]	MAIN[19][29][54]	MAIN[29][29][54]	MAIN[39][29][54]
DRP[78] bit 14	MAIN[9][28][55]	MAIN[19][28][55]	MAIN[29][28][55]	MAIN[39][28][55]
DRP[78] bit 15	MAIN[9][29][55]	MAIN[19][29][55]	MAIN[29][29][55]	MAIN[39][29][55]
DRP[79] bit 0	MAIN[9][28][56]	MAIN[19][28][56]	MAIN[29][28][56]	MAIN[39][28][56]
DRP[79] bit 1	MAIN[9][29][56]	MAIN[19][29][56]	MAIN[29][29][56]	MAIN[39][29][56]
DRP[79] bit 2	MAIN[9][28][57]	MAIN[19][28][57]	MAIN[29][28][57]	MAIN[39][28][57]
DRP[79] bit 3	MAIN[9][29][57]	MAIN[19][29][57]	MAIN[29][29][57]	MAIN[39][29][57]
DRP[79] bit 4	MAIN[9][28][58]	MAIN[19][28][58]	MAIN[29][28][58]	MAIN[39][28][58]
DRP[79] bit 5	MAIN[9][29][58]	MAIN[19][29][58]	MAIN[29][29][58]	MAIN[39][29][58]
DRP[79] bit 6	MAIN[9][28][59]	MAIN[19][28][59]	MAIN[29][28][59]	MAIN[39][28][59]
DRP[79] bit 7	MAIN[9][29][59]	MAIN[19][29][59]	MAIN[29][29][59]	MAIN[39][29][59]
DRP[79] bit 8	MAIN[9][28][60]	MAIN[19][28][60]	MAIN[29][28][60]	MAIN[39][28][60]
DRP[79] bit 9	MAIN[9][29][60]	MAIN[19][29][60]	MAIN[29][29][60]	MAIN[39][29][60]
DRP[79] bit 10	MAIN[9][28][61]	MAIN[19][28][61]	MAIN[29][28][61]	MAIN[39][28][61]
DRP[79] bit 11	MAIN[9][29][61]	MAIN[19][29][61]	MAIN[29][29][61]	MAIN[39][29][61]
DRP[79] bit 12	MAIN[9][28][62]	MAIN[19][28][62]	MAIN[29][28][62]	MAIN[39][28][62]
DRP[79] bit 13	MAIN[9][29][62]	MAIN[19][29][62]	MAIN[29][29][62]	MAIN[39][29][62]
DRP[79] bit 14	MAIN[9][28][63]	MAIN[19][28][63]	MAIN[29][28][63]	MAIN[39][28][63]
DRP[79] bit 15	MAIN[9][29][63]	MAIN[19][29][63]	MAIN[29][29][63]	MAIN[39][29][63]
PMA_CAS_CLK_EN	MAIN[4][29][23]	MAIN[14][29][23]	MAIN[24][29][23]	MAIN[34][29][23]
RXPLLREFSEL_STATIC_VAL	[enum: GTX_PLLREFSEL]	[enum: GTX_PLLREFSEL]	[enum: GTX_PLLREFSEL]	[enum: GTX_PLLREFSEL]
RXPLLREFSEL_MODE_DYNAMIC	MAIN[3][28][35]	MAIN[13][28][35]	MAIN[23][28][35]	MAIN[33][28][35]
RXPLLREFSEL_TESTCLK	[enum: GTX_PLLREFSEL_TESTCLK]	[enum: GTX_PLLREFSEL_TESTCLK]	[enum: GTX_PLLREFSEL_TESTCLK]	[enum: GTX_PLLREFSEL_TESTCLK]
TXPLLREFSEL_STATIC_VAL	[enum: GTX_PLLREFSEL]	[enum: GTX_PLLREFSEL]	[enum: GTX_PLLREFSEL]	[enum: GTX_PLLREFSEL]
TXPLLREFSEL_MODE_DYNAMIC	MAIN[4][28][3]	MAIN[14][28][3]	MAIN[24][28][3]	MAIN[34][28][3]
TXPLLREFSEL_TESTCLK	[enum: GTX_PLLREFSEL_TESTCLK]	[enum: GTX_PLLREFSEL_TESTCLK]	[enum: GTX_PLLREFSEL_TESTCLK]	[enum: GTX_PLLREFSEL_TESTCLK]
AC_CAP_DIS	MAIN[2][28][58]	MAIN[12][28][58]	MAIN[22][28][58]	MAIN[32][28][58]
CHAN_BOND_KEEP_ALIGN	MAIN[1][28][15]	MAIN[11][28][15]	MAIN[21][28][15]	MAIN[31][28][15]
CHAN_BOND_SEQ_2_USE	MAIN[1][28][23]	MAIN[11][28][23]	MAIN[21][28][23]	MAIN[31][28][23]
CLK_COR_INSERT_IDLE_FLAG	MAIN[2][29][15]	MAIN[12][29][15]	MAIN[22][29][15]	MAIN[32][29][15]
CLK_COR_KEEP_IDLE	MAIN[1][29][55]	MAIN[11][29][55]	MAIN[21][29][55]	MAIN[31][29][55]
CLK_COR_PRECEDENCE	MAIN[1][29][47]	MAIN[11][29][47]	MAIN[21][29][47]	MAIN[31][29][47]
CLK_CORRECT_USE	MAIN[1][28][47]	MAIN[11][28][47]	MAIN[21][28][47]	MAIN[31][28][47]
CLK_COR_SEQ_2_USE	MAIN[2][28][15]	MAIN[12][28][15]	MAIN[22][28][15]	MAIN[32][28][15]
COMMA_DOUBLE	MAIN[5][28][61]	MAIN[15][28][61]	MAIN[25][28][61]	MAIN[35][28][61]
DEC_MCOMMA_DETECT	MAIN[2][29][37]	MAIN[12][29][37]	MAIN[22][29][37]	MAIN[32][29][37]
DEC_PCOMMA_DETECT	MAIN[2][28][37]	MAIN[12][28][37]	MAIN[22][28][37]	MAIN[32][28][37]
DEC_VALID_COMMA_ONLY	MAIN[2][29][39]	MAIN[12][29][39]	MAIN[22][29][39]	MAIN[32][29][39]
DFE_DRP_EN	MAIN[5][29][39]	MAIN[15][29][39]	MAIN[25][29][39]	MAIN[35][29][39]
GEN_RXUSRCLK	MAIN[2][29][63]	MAIN[12][29][63]	MAIN[22][29][63]	MAIN[32][29][63]
GEN_TXUSRCLK	MAIN[6][29][15]	MAIN[16][29][15]	MAIN[26][29][15]	MAIN[36][29][15]
GTX_CFG_PWRUP	MAIN[2][29][57]	MAIN[12][29][57]	MAIN[22][29][57]	MAIN[32][29][57]
LOOPBACK_DRP_EN	MAIN[5][28][16]	MAIN[15][28][16]	MAIN[25][28][16]	MAIN[35][28][16]
MASTER_DRP_EN	MAIN[3][29][7]	MAIN[13][29][7]	MAIN[23][29][7]	MAIN[33][29][7]
MCOMMA_DETECT	MAIN[6][28][5]	MAIN[16][28][5]	MAIN[26][28][5]	MAIN[36][28][5]
PCI_EXPRESS_MODE	MAIN[4][29][15]	MAIN[14][29][15]	MAIN[24][29][15]	MAIN[34][29][15]
PCOMMA_DETECT	MAIN[6][28][13]	MAIN[16][28][13]	MAIN[26][28][13]	MAIN[36][28][13]
PDELIDLE_DRP_EN	MAIN[4][29][6]	MAIN[14][29][6]	MAIN[24][29][6]	MAIN[34][29][6]
PHASEALIGN_DRP_EN	MAIN[5][29][15]	MAIN[15][29][15]	MAIN[25][29][15]	MAIN[35][29][15]
PLL_DRP_EN	MAIN[3][29][38]	MAIN[13][29][38]	MAIN[23][29][38]	MAIN[33][29][38]
POLARITY_DRP_EN	MAIN[4][28][46]	MAIN[14][28][46]	MAIN[24][28][46]	MAIN[34][28][46]
PRBS_DRP_EN	MAIN[5][29][23]	MAIN[15][29][23]	MAIN[25][29][23]	MAIN[35][29][23]
RCV_TERM_GND	MAIN[5][29][51]	MAIN[15][29][51]	MAIN[25][29][51]	MAIN[35][29][51]
RCV_TERM_VTTRX	MAIN[5][28][52]	MAIN[15][28][52]	MAIN[25][28][52]	MAIN[35][28][52]
RESET_DRP_EN	MAIN[3][28][7]	MAIN[13][28][7]	MAIN[23][28][7]	MAIN[33][28][7]
RX_BUFFER_USE	MAIN[0][28][39]	MAIN[10][28][39]	MAIN[20][28][39]	MAIN[30][28][39]
RXBUF_OVRD_THRESH	MAIN[1][28][38]	MAIN[11][28][38]	MAIN[21][28][38]	MAIN[31][28][38]
RX_CDR_FORCE_ROTATE	MAIN[2][29][23]	MAIN[12][29][23]	MAIN[22][29][23]	MAIN[32][29][23]
RX_DECODE_SEQ_MATCH	MAIN[2][29][38]	MAIN[12][29][38]	MAIN[22][29][38]	MAIN[32][29][38]
RX_EN_IDLE_HOLD_CDR	MAIN[5][29][28]	MAIN[15][29][28]	MAIN[25][29][28]	MAIN[35][29][28]
RX_EN_IDLE_HOLD_DFE	MAIN[5][29][29]	MAIN[15][29][29]	MAIN[25][29][29]	MAIN[35][29][29]
RX_EN_IDLE_RESET_BUF	MAIN[1][28][29]	MAIN[11][28][29]	MAIN[21][28][29]	MAIN[31][28][29]
RX_EN_IDLE_RESET_FR	MAIN[5][28][29]	MAIN[15][28][29]	MAIN[25][28][29]	MAIN[35][28][29]
RX_EN_IDLE_RESET_PH	MAIN[1][29][23]	MAIN[11][29][23]	MAIN[21][29][23]	MAIN[31][29][23]
RX_EN_MODE_RESET_BUF	MAIN[1][29][15]	MAIN[11][29][15]	MAIN[21][29][15]	MAIN[31][29][15]
RX_EN_RATE_RESET_BUF	MAIN[1][29][7]	MAIN[11][29][7]	MAIN[21][29][7]	MAIN[31][29][7]
RX_EN_REALIGN_RESET_BUF2	MAIN[9][28][31]	MAIN[19][28][31]	MAIN[29][28][31]	MAIN[39][28][31]
RX_EN_REALIGN_RESET_BUF	MAIN[1][28][7]	MAIN[11][28][7]	MAIN[21][28][7]	MAIN[31][28][7]
RXGEARBOX_USE	MAIN[3][29][1]	MAIN[13][29][1]	MAIN[23][29][1]	MAIN[33][29][1]
RX_LOSS_OF_SYNC_FSM	MAIN[0][29][39]	MAIN[10][29][39]	MAIN[20][29][39]	MAIN[30][29][39]
RX_OVERSAMPLE_MODE	MAIN[3][29][39]	MAIN[13][29][39]	MAIN[23][29][39]	MAIN[33][29][39]
RXPLL_STARTUP_EN	MAIN[3][29][27]	MAIN[13][29][27]	MAIN[23][29][27]	MAIN[33][29][27]
SHOW_REALIGN_COMMA	MAIN[2][28][23]	MAIN[12][28][23]	MAIN[22][28][23]	MAIN[32][28][23]
TERMINATION_OVRD	MAIN[5][28][51]	MAIN[15][28][51]	MAIN[25][28][51]	MAIN[35][28][51]
TX_BUFFER_USE	MAIN[6][29][13]	MAIN[16][29][13]	MAIN[26][29][13]	MAIN[36][29][13]
TXDRIVE_DRP_EN	MAIN[7][28][39]	MAIN[17][28][39]	MAIN[27][28][39]	MAIN[37][28][39]
TXDRIVE_LOOPBACK_HIZ	!MAIN[7][28][23]	!MAIN[17][28][23]	!MAIN[27][28][23]	!MAIN[37][28][23]
TXDRIVE_LOOPBACK_PD	!MAIN[7][29][23]	!MAIN[17][29][23]	!MAIN[27][29][23]	!MAIN[37][29][23]
TX_EN_RATE_RESET_BUF	MAIN[4][29][63]	MAIN[14][29][63]	MAIN[24][29][63]	MAIN[34][29][63]
TXGEARBOX_USE	MAIN[5][29][63]	MAIN[15][29][63]	MAIN[25][29][63]	MAIN[35][29][63]
TX_OVERSAMPLE_MODE	MAIN[4][29][7]	MAIN[14][29][7]	MAIN[24][29][7]	MAIN[34][29][7]
TXPLL_STARTUP_EN	MAIN[3][29][59]	MAIN[13][29][59]	MAIN[23][29][59]	MAIN[33][29][59]
ALIGN_COMMA_WORD	[enum: GTP_ALIGN_COMMA_WORD]	[enum: GTP_ALIGN_COMMA_WORD]	[enum: GTP_ALIGN_COMMA_WORD]	[enum: GTP_ALIGN_COMMA_WORD]
CHAN_BOND_SEQ_LEN	[enum: GTP_SEQ_LEN]	[enum: GTP_SEQ_LEN]	[enum: GTP_SEQ_LEN]	[enum: GTP_SEQ_LEN]
CLK_COR_ADJ_LEN	[enum: GTP_SEQ_LEN]	[enum: GTP_SEQ_LEN]	[enum: GTP_SEQ_LEN]	[enum: GTP_SEQ_LEN]
CLK_COR_DET_LEN	[enum: GTP_SEQ_LEN]	[enum: GTP_SEQ_LEN]	[enum: GTP_SEQ_LEN]	[enum: GTP_SEQ_LEN]
RX_DATA_WIDTH	[enum: GTX_DATA_WIDTH]	[enum: GTX_DATA_WIDTH]	[enum: GTX_DATA_WIDTH]	[enum: GTX_DATA_WIDTH]
RX_FIFO_ADDR_MODE	[enum: GTX_RX_FIFO_ADDR_MODE]	[enum: GTX_RX_FIFO_ADDR_MODE]	[enum: GTX_RX_FIFO_ADDR_MODE]	[enum: GTX_RX_FIFO_ADDR_MODE]
RX_LOS_INVALID_INCR	[enum: GT_RX_LOS_INVALID_INCR]	[enum: GT_RX_LOS_INVALID_INCR]	[enum: GT_RX_LOS_INVALID_INCR]	[enum: GT_RX_LOS_INVALID_INCR]
RX_LOS_THRESHOLD	[enum: GT_RX_LOS_THRESHOLD]	[enum: GT_RX_LOS_THRESHOLD]	[enum: GT_RX_LOS_THRESHOLD]	[enum: GT_RX_LOS_THRESHOLD]
RXPLL_DIVSEL45_FB	[enum: GTX_PLL_DIVSEL45_FB]	[enum: GTX_PLL_DIVSEL45_FB]	[enum: GTX_PLL_DIVSEL45_FB]	[enum: GTX_PLL_DIVSEL45_FB]
RXPLL_DIVSEL_FB	[enum: GTP_PLL_DIVSEL_REF]	[enum: GTP_PLL_DIVSEL_REF]	[enum: GTP_PLL_DIVSEL_REF]	[enum: GTP_PLL_DIVSEL_REF]
RXPLL_DIVSEL_OUT	[enum: GTP_PLL_DIVSEL_OUT]	[enum: GTP_PLL_DIVSEL_OUT]	[enum: GTP_PLL_DIVSEL_OUT]	[enum: GTP_PLL_DIVSEL_OUT]
RXPLL_DIVSEL_REF	[enum: GTP_PLL_DIVSEL_REF]	[enum: GTP_PLL_DIVSEL_REF]	[enum: GTP_PLL_DIVSEL_REF]	[enum: GTP_PLL_DIVSEL_REF]
RXRECCLK_CTRL	[enum: GTX_RXRECCLK_CTRL]	[enum: GTX_RXRECCLK_CTRL]	[enum: GTX_RXRECCLK_CTRL]	[enum: GTX_RXRECCLK_CTRL]
RX_SLIDE_MODE	[enum: GTX_RX_SLIDE_MODE]	[enum: GTX_RX_SLIDE_MODE]	[enum: GTX_RX_SLIDE_MODE]	[enum: GTX_RX_SLIDE_MODE]
RX_XCLK_SEL	[enum: GTP_RX_XCLK_SEL]	[enum: GTP_RX_XCLK_SEL]	[enum: GTP_RX_XCLK_SEL]	[enum: GTP_RX_XCLK_SEL]
TX_CLK_SOURCE	[enum: GTX_TX_CLK_SOURCE]	[enum: GTX_TX_CLK_SOURCE]	[enum: GTX_TX_CLK_SOURCE]	[enum: GTX_TX_CLK_SOURCE]
TX_DATA_WIDTH	[enum: GTX_DATA_WIDTH]	[enum: GTX_DATA_WIDTH]	[enum: GTX_DATA_WIDTH]	[enum: GTX_DATA_WIDTH]
TX_DRIVE_MODE	[enum: GTX_TX_DRIVE_MODE]	[enum: GTX_TX_DRIVE_MODE]	[enum: GTX_TX_DRIVE_MODE]	[enum: GTX_TX_DRIVE_MODE]
TXOUTCLK_CTRL	[enum: GTX_TXOUTCLK_CTRL]	[enum: GTX_TXOUTCLK_CTRL]	[enum: GTX_TXOUTCLK_CTRL]	[enum: GTX_TXOUTCLK_CTRL]
TXPLL_DIVSEL45_FB	[enum: GTX_PLL_DIVSEL45_FB]	[enum: GTX_PLL_DIVSEL45_FB]	[enum: GTX_PLL_DIVSEL45_FB]	[enum: GTX_PLL_DIVSEL45_FB]
TXPLL_DIVSEL_FB	[enum: GTP_PLL_DIVSEL_REF]	[enum: GTP_PLL_DIVSEL_REF]	[enum: GTP_PLL_DIVSEL_REF]	[enum: GTP_PLL_DIVSEL_REF]
TXPLL_DIVSEL_OUT	[enum: GTP_PLL_DIVSEL_OUT]	[enum: GTP_PLL_DIVSEL_OUT]	[enum: GTP_PLL_DIVSEL_OUT]	[enum: GTP_PLL_DIVSEL_OUT]
TXPLL_DIVSEL_REF	[enum: GTP_PLL_DIVSEL_REF]	[enum: GTP_PLL_DIVSEL_REF]	[enum: GTP_PLL_DIVSEL_REF]	[enum: GTP_PLL_DIVSEL_REF]
TX_XCLK_SEL	[enum: GTP_TX_XCLK_SEL]	[enum: GTP_TX_XCLK_SEL]	[enum: GTP_TX_XCLK_SEL]	[enum: GTP_TX_XCLK_SEL]
RX_CLK25_DIVIDER bit 0	MAIN[2][29][58]	MAIN[12][29][58]	MAIN[22][29][58]	MAIN[32][29][58]
RX_CLK25_DIVIDER bit 1	MAIN[2][28][59]	MAIN[12][28][59]	MAIN[22][28][59]	MAIN[32][28][59]
RX_CLK25_DIVIDER bit 2	MAIN[2][29][59]	MAIN[12][29][59]	MAIN[22][29][59]	MAIN[32][29][59]
RX_CLK25_DIVIDER bit 3	MAIN[2][28][60]	MAIN[12][28][60]	MAIN[22][28][60]	MAIN[32][28][60]
RX_CLK25_DIVIDER bit 4	MAIN[2][29][60]	MAIN[12][29][60]	MAIN[22][29][60]	MAIN[32][29][60]
TX_CLK25_DIVIDER bit 0	MAIN[4][28][29]	MAIN[14][28][29]	MAIN[24][28][29]	MAIN[34][28][29]
TX_CLK25_DIVIDER bit 1	MAIN[4][29][29]	MAIN[14][29][29]	MAIN[24][29][29]	MAIN[34][29][29]
TX_CLK25_DIVIDER bit 2	MAIN[4][28][30]	MAIN[14][28][30]	MAIN[24][28][30]	MAIN[34][28][30]
TX_CLK25_DIVIDER bit 3	MAIN[4][29][30]	MAIN[14][29][30]	MAIN[24][29][30]	MAIN[34][29][30]
TX_CLK25_DIVIDER bit 4	MAIN[4][28][31]	MAIN[14][28][31]	MAIN[24][28][31]	MAIN[34][28][31]
CHAN_BOND_1_MAX_SKEW bit 0	MAIN[0][28][45]	MAIN[10][28][45]	MAIN[20][28][45]	MAIN[30][28][45]
CHAN_BOND_1_MAX_SKEW bit 1	MAIN[0][29][45]	MAIN[10][29][45]	MAIN[20][29][45]	MAIN[30][29][45]
CHAN_BOND_1_MAX_SKEW bit 2	MAIN[0][28][46]	MAIN[10][28][46]	MAIN[20][28][46]	MAIN[30][28][46]
CHAN_BOND_1_MAX_SKEW bit 3	MAIN[0][29][46]	MAIN[10][29][46]	MAIN[20][29][46]	MAIN[30][29][46]
CHAN_BOND_2_MAX_SKEW bit 0	MAIN[1][28][13]	MAIN[11][28][13]	MAIN[21][28][13]	MAIN[31][28][13]
CHAN_BOND_2_MAX_SKEW bit 1	MAIN[1][29][13]	MAIN[11][29][13]	MAIN[21][29][13]	MAIN[31][29][13]
CHAN_BOND_2_MAX_SKEW bit 2	MAIN[1][28][14]	MAIN[11][28][14]	MAIN[21][28][14]	MAIN[31][28][14]
CHAN_BOND_2_MAX_SKEW bit 3	MAIN[1][29][14]	MAIN[11][29][14]	MAIN[21][29][14]	MAIN[31][29][14]
CLK_COR_MAX_LAT bit 0	MAIN[2][28][5]	MAIN[12][28][5]	MAIN[22][28][5]	MAIN[32][28][5]
CLK_COR_MAX_LAT bit 1	MAIN[2][29][5]	MAIN[12][29][5]	MAIN[22][29][5]	MAIN[32][29][5]
CLK_COR_MAX_LAT bit 2	MAIN[2][28][6]	MAIN[12][28][6]	MAIN[22][28][6]	MAIN[32][28][6]
CLK_COR_MAX_LAT bit 3	MAIN[2][29][6]	MAIN[12][29][6]	MAIN[22][29][6]	MAIN[32][29][6]
CLK_COR_MAX_LAT bit 4	MAIN[2][28][7]	MAIN[12][28][7]	MAIN[22][28][7]	MAIN[32][28][7]
CLK_COR_MAX_LAT bit 5	MAIN[2][29][7]	MAIN[12][29][7]	MAIN[22][29][7]	MAIN[32][29][7]
CLK_COR_MIN_LAT bit 0	MAIN[1][28][61]	MAIN[11][28][61]	MAIN[21][28][61]	MAIN[31][28][61]
CLK_COR_MIN_LAT bit 1	MAIN[1][29][61]	MAIN[11][29][61]	MAIN[21][29][61]	MAIN[31][29][61]
CLK_COR_MIN_LAT bit 2	MAIN[1][28][62]	MAIN[11][28][62]	MAIN[21][28][62]	MAIN[31][28][62]
CLK_COR_MIN_LAT bit 3	MAIN[1][29][62]	MAIN[11][29][62]	MAIN[21][29][62]	MAIN[31][29][62]
CLK_COR_MIN_LAT bit 4	MAIN[1][28][63]	MAIN[11][28][63]	MAIN[21][28][63]	MAIN[31][28][63]
CLK_COR_MIN_LAT bit 5	MAIN[1][29][63]	MAIN[11][29][63]	MAIN[21][29][63]	MAIN[31][29][63]
SAS_MAX_COMSAS bit 0	MAIN[5][28][8]	MAIN[15][28][8]	MAIN[25][28][8]	MAIN[35][28][8]
SAS_MAX_COMSAS bit 1	MAIN[5][29][8]	MAIN[15][29][8]	MAIN[25][29][8]	MAIN[35][29][8]
SAS_MAX_COMSAS bit 2	MAIN[5][28][9]	MAIN[15][28][9]	MAIN[25][28][9]	MAIN[35][28][9]
SAS_MAX_COMSAS bit 3	MAIN[5][29][9]	MAIN[15][29][9]	MAIN[25][29][9]	MAIN[35][29][9]
SAS_MAX_COMSAS bit 4	MAIN[5][28][10]	MAIN[15][28][10]	MAIN[25][28][10]	MAIN[35][28][10]
SAS_MAX_COMSAS bit 5	MAIN[5][29][10]	MAIN[15][29][10]	MAIN[25][29][10]	MAIN[35][29][10]
SAS_MIN_COMSAS bit 0	MAIN[5][28][11]	MAIN[15][28][11]	MAIN[25][28][11]	MAIN[35][28][11]
SAS_MIN_COMSAS bit 1	MAIN[5][29][11]	MAIN[15][29][11]	MAIN[25][29][11]	MAIN[35][29][11]
SAS_MIN_COMSAS bit 2	MAIN[5][28][12]	MAIN[15][28][12]	MAIN[25][28][12]	MAIN[35][28][12]
SAS_MIN_COMSAS bit 3	MAIN[5][29][12]	MAIN[15][29][12]	MAIN[25][29][12]	MAIN[35][29][12]
SAS_MIN_COMSAS bit 4	MAIN[5][28][13]	MAIN[15][28][13]	MAIN[25][28][13]	MAIN[35][28][13]
SAS_MIN_COMSAS bit 5	MAIN[5][29][13]	MAIN[15][29][13]	MAIN[25][29][13]	MAIN[35][29][13]
SATA_MAX_BURST bit 0	MAIN[5][28][0]	MAIN[15][28][0]	MAIN[25][28][0]	MAIN[35][28][0]
SATA_MAX_BURST bit 1	MAIN[5][29][0]	MAIN[15][29][0]	MAIN[25][29][0]	MAIN[35][29][0]
SATA_MAX_BURST bit 2	MAIN[5][28][1]	MAIN[15][28][1]	MAIN[25][28][1]	MAIN[35][28][1]
SATA_MAX_BURST bit 3	MAIN[5][29][1]	MAIN[15][29][1]	MAIN[25][29][1]	MAIN[35][29][1]
SATA_MAX_BURST bit 4	MAIN[5][28][2]	MAIN[15][28][2]	MAIN[25][28][2]	MAIN[35][28][2]
SATA_MAX_BURST bit 5	MAIN[5][29][2]	MAIN[15][29][2]	MAIN[25][29][2]	MAIN[35][29][2]
SATA_MAX_INIT bit 0	MAIN[4][28][56]	MAIN[14][28][56]	MAIN[24][28][56]	MAIN[34][28][56]
SATA_MAX_INIT bit 1	MAIN[4][29][56]	MAIN[14][29][56]	MAIN[24][29][56]	MAIN[34][29][56]
SATA_MAX_INIT bit 2	MAIN[4][28][57]	MAIN[14][28][57]	MAIN[24][28][57]	MAIN[34][28][57]
SATA_MAX_INIT bit 3	MAIN[4][29][57]	MAIN[14][29][57]	MAIN[24][29][57]	MAIN[34][29][57]
SATA_MAX_INIT bit 4	MAIN[4][28][58]	MAIN[14][28][58]	MAIN[24][28][58]	MAIN[34][28][58]
SATA_MAX_INIT bit 5	MAIN[4][29][58]	MAIN[14][29][58]	MAIN[24][29][58]	MAIN[34][29][58]
SATA_MAX_WAKE bit 0	MAIN[4][28][48]	MAIN[14][28][48]	MAIN[24][28][48]	MAIN[34][28][48]
SATA_MAX_WAKE bit 1	MAIN[4][29][48]	MAIN[14][29][48]	MAIN[24][29][48]	MAIN[34][29][48]
SATA_MAX_WAKE bit 2	MAIN[4][28][49]	MAIN[14][28][49]	MAIN[24][28][49]	MAIN[34][28][49]
SATA_MAX_WAKE bit 3	MAIN[4][29][49]	MAIN[14][29][49]	MAIN[24][29][49]	MAIN[34][29][49]
SATA_MAX_WAKE bit 4	MAIN[4][28][50]	MAIN[14][28][50]	MAIN[24][28][50]	MAIN[34][28][50]
SATA_MAX_WAKE bit 5	MAIN[4][29][50]	MAIN[14][29][50]	MAIN[24][29][50]	MAIN[34][29][50]
SATA_MIN_BURST bit 0	MAIN[5][28][3]	MAIN[15][28][3]	MAIN[25][28][3]	MAIN[35][28][3]
SATA_MIN_BURST bit 1	MAIN[5][29][3]	MAIN[15][29][3]	MAIN[25][29][3]	MAIN[35][29][3]
SATA_MIN_BURST bit 2	MAIN[5][28][4]	MAIN[15][28][4]	MAIN[25][28][4]	MAIN[35][28][4]
SATA_MIN_BURST bit 3	MAIN[5][29][4]	MAIN[15][29][4]	MAIN[25][29][4]	MAIN[35][29][4]
SATA_MIN_BURST bit 4	MAIN[5][28][5]	MAIN[15][28][5]	MAIN[25][28][5]	MAIN[35][28][5]
SATA_MIN_BURST bit 5	MAIN[5][29][5]	MAIN[15][29][5]	MAIN[25][29][5]	MAIN[35][29][5]
SATA_MIN_INIT bit 0	MAIN[4][28][59]	MAIN[14][28][59]	MAIN[24][28][59]	MAIN[34][28][59]
SATA_MIN_INIT bit 1	MAIN[4][29][59]	MAIN[14][29][59]	MAIN[24][29][59]	MAIN[34][29][59]
SATA_MIN_INIT bit 2	MAIN[4][28][60]	MAIN[14][28][60]	MAIN[24][28][60]	MAIN[34][28][60]
SATA_MIN_INIT bit 3	MAIN[4][29][60]	MAIN[14][29][60]	MAIN[24][29][60]	MAIN[34][29][60]
SATA_MIN_INIT bit 4	MAIN[4][28][61]	MAIN[14][28][61]	MAIN[24][28][61]	MAIN[34][28][61]
SATA_MIN_INIT bit 5	MAIN[4][29][61]	MAIN[14][29][61]	MAIN[24][29][61]	MAIN[34][29][61]
SATA_MIN_WAKE bit 0	MAIN[4][28][51]	MAIN[14][28][51]	MAIN[24][28][51]	MAIN[34][28][51]
SATA_MIN_WAKE bit 1	MAIN[4][29][51]	MAIN[14][29][51]	MAIN[24][29][51]	MAIN[34][29][51]
SATA_MIN_WAKE bit 2	MAIN[4][28][52]	MAIN[14][28][52]	MAIN[24][28][52]	MAIN[34][28][52]
SATA_MIN_WAKE bit 3	MAIN[4][29][52]	MAIN[14][29][52]	MAIN[24][29][52]	MAIN[34][29][52]
SATA_MIN_WAKE bit 4	MAIN[4][28][53]	MAIN[14][28][53]	MAIN[24][28][53]	MAIN[34][28][53]
SATA_MIN_WAKE bit 5	MAIN[4][29][53]	MAIN[14][29][53]	MAIN[24][29][53]	MAIN[34][29][53]
CLK_COR_REPEAT_WAIT bit 0	MAIN[1][28][53]	MAIN[11][28][53]	MAIN[21][28][53]	MAIN[31][28][53]
CLK_COR_REPEAT_WAIT bit 1	MAIN[1][29][53]	MAIN[11][29][53]	MAIN[21][29][53]	MAIN[31][29][53]
CLK_COR_REPEAT_WAIT bit 2	MAIN[1][28][54]	MAIN[11][28][54]	MAIN[21][28][54]	MAIN[31][28][54]
CLK_COR_REPEAT_WAIT bit 3	MAIN[1][29][54]	MAIN[11][29][54]	MAIN[21][29][54]	MAIN[31][29][54]
CLK_COR_REPEAT_WAIT bit 4	MAIN[1][28][55]	MAIN[11][28][55]	MAIN[21][28][55]	MAIN[31][28][55]
RXBUF_OVFL_THRESH bit 0	MAIN[1][28][32]	MAIN[11][28][32]	MAIN[21][28][32]	MAIN[31][28][32]
RXBUF_OVFL_THRESH bit 1	MAIN[1][29][32]	MAIN[11][29][32]	MAIN[21][29][32]	MAIN[31][29][32]
RXBUF_OVFL_THRESH bit 2	MAIN[1][28][33]	MAIN[11][28][33]	MAIN[21][28][33]	MAIN[31][28][33]
RXBUF_OVFL_THRESH bit 3	MAIN[1][29][33]	MAIN[11][29][33]	MAIN[21][29][33]	MAIN[31][29][33]
RXBUF_OVFL_THRESH bit 4	MAIN[1][28][34]	MAIN[11][28][34]	MAIN[21][28][34]	MAIN[31][28][34]
RXBUF_OVFL_THRESH bit 5	MAIN[1][29][34]	MAIN[11][29][34]	MAIN[21][29][34]	MAIN[31][29][34]
RXBUF_UDFL_THRESH bit 0	MAIN[1][28][35]	MAIN[11][28][35]	MAIN[21][28][35]	MAIN[31][28][35]
RXBUF_UDFL_THRESH bit 1	MAIN[1][29][35]	MAIN[11][29][35]	MAIN[21][29][35]	MAIN[31][29][35]
RXBUF_UDFL_THRESH bit 2	MAIN[1][28][36]	MAIN[11][28][36]	MAIN[21][28][36]	MAIN[31][28][36]
RXBUF_UDFL_THRESH bit 3	MAIN[1][29][36]	MAIN[11][29][36]	MAIN[21][29][36]	MAIN[31][29][36]
RXBUF_UDFL_THRESH bit 4	MAIN[1][28][37]	MAIN[11][28][37]	MAIN[21][28][37]	MAIN[31][28][37]
RXBUF_UDFL_THRESH bit 5	MAIN[1][29][37]	MAIN[11][29][37]	MAIN[21][29][37]	MAIN[31][29][37]
RX_SLIDE_AUTO_WAIT bit 0	MAIN[2][28][30]	MAIN[12][28][30]	MAIN[22][28][30]	MAIN[32][28][30]
RX_SLIDE_AUTO_WAIT bit 1	MAIN[2][29][30]	MAIN[12][29][30]	MAIN[22][29][30]	MAIN[32][29][30]
RX_SLIDE_AUTO_WAIT bit 2	MAIN[2][28][31]	MAIN[12][28][31]	MAIN[22][28][31]	MAIN[32][28][31]
RX_SLIDE_AUTO_WAIT bit 3	MAIN[2][29][31]	MAIN[12][29][31]	MAIN[22][29][31]	MAIN[32][29][31]
TXOUTCLKPCS_SEL bit 0	MAIN[7][28][7]	MAIN[17][28][7]	MAIN[27][28][7]	MAIN[37][28][7]
A_DFECLKDLYADJ bit 0	MAIN[5][29][36]	MAIN[15][29][36]	MAIN[25][29][36]	MAIN[35][29][36]
A_DFECLKDLYADJ bit 1	MAIN[5][28][37]	MAIN[15][28][37]	MAIN[25][28][37]	MAIN[35][28][37]
A_DFECLKDLYADJ bit 2	MAIN[5][29][37]	MAIN[15][29][37]	MAIN[25][29][37]	MAIN[35][29][37]
A_DFECLKDLYADJ bit 3	MAIN[5][28][38]	MAIN[15][28][38]	MAIN[25][28][38]	MAIN[35][28][38]
A_DFECLKDLYADJ bit 4	MAIN[5][29][38]	MAIN[15][29][38]	MAIN[25][29][38]	MAIN[35][29][38]
A_DFECLKDLYADJ bit 5	MAIN[5][28][39]	MAIN[15][28][39]	MAIN[25][28][39]	MAIN[35][28][39]
A_DFEDLYOVRD bit 0	MAIN[5][28][31]	MAIN[15][28][31]	MAIN[25][28][31]	MAIN[35][28][31]
A_DFETAP1 bit 0	MAIN[5][28][24]	MAIN[15][28][24]	MAIN[25][28][24]	MAIN[35][28][24]
A_DFETAP1 bit 1	MAIN[5][29][24]	MAIN[15][29][24]	MAIN[25][29][24]	MAIN[35][29][24]
A_DFETAP1 bit 2	MAIN[5][28][25]	MAIN[15][28][25]	MAIN[25][28][25]	MAIN[35][28][25]
A_DFETAP1 bit 3	MAIN[5][29][25]	MAIN[15][29][25]	MAIN[25][29][25]	MAIN[35][29][25]
A_DFETAP1 bit 4	MAIN[5][28][26]	MAIN[15][28][26]	MAIN[25][28][26]	MAIN[35][28][26]
A_DFETAP2 bit 0	MAIN[5][28][32]	MAIN[15][28][32]	MAIN[25][28][32]	MAIN[35][28][32]
A_DFETAP2 bit 1	MAIN[5][29][32]	MAIN[15][29][32]	MAIN[25][29][32]	MAIN[35][29][32]
A_DFETAP2 bit 2	MAIN[5][28][33]	MAIN[15][28][33]	MAIN[25][28][33]	MAIN[35][28][33]
A_DFETAP2 bit 3	MAIN[5][29][33]	MAIN[15][29][33]	MAIN[25][29][33]	MAIN[35][29][33]
A_DFETAP2 bit 4	MAIN[5][28][34]	MAIN[15][28][34]	MAIN[25][28][34]	MAIN[35][28][34]
A_DFETAP3 bit 0	MAIN[5][29][26]	MAIN[15][29][26]	MAIN[25][29][26]	MAIN[35][29][26]
A_DFETAP3 bit 1	MAIN[5][28][27]	MAIN[15][28][27]	MAIN[25][28][27]	MAIN[35][28][27]
A_DFETAP3 bit 2	MAIN[5][29][27]	MAIN[15][29][27]	MAIN[25][29][27]	MAIN[35][29][27]
A_DFETAP3 bit 3	MAIN[5][28][28]	MAIN[15][28][28]	MAIN[25][28][28]	MAIN[35][28][28]
A_DFETAP4 bit 0	MAIN[5][29][34]	MAIN[15][29][34]	MAIN[25][29][34]	MAIN[35][29][34]
A_DFETAP4 bit 1	MAIN[5][28][35]	MAIN[15][28][35]	MAIN[25][28][35]	MAIN[35][28][35]
A_DFETAP4 bit 2	MAIN[5][29][35]	MAIN[15][29][35]	MAIN[25][29][35]	MAIN[35][29][35]
A_DFETAP4 bit 3	MAIN[5][28][36]	MAIN[15][28][36]	MAIN[25][28][36]	MAIN[35][28][36]
A_DFETAPOVRD bit 0	MAIN[5][29][31]	MAIN[15][29][31]	MAIN[25][29][31]	MAIN[35][29][31]
A_GTXRXRESET bit 0	MAIN[3][28][3]	MAIN[13][28][3]	MAIN[23][28][3]	MAIN[33][28][3]
A_GTXTXRESET bit 0	MAIN[3][29][2]	MAIN[13][29][2]	MAIN[23][29][2]	MAIN[33][29][2]
A_LOOPBACK bit 0	MAIN[5][29][16]	MAIN[15][29][16]	MAIN[25][29][16]	MAIN[35][29][16]
A_LOOPBACK bit 1	MAIN[5][28][17]	MAIN[15][28][17]	MAIN[25][28][17]	MAIN[35][28][17]
A_LOOPBACK bit 2	MAIN[5][29][17]	MAIN[15][29][17]	MAIN[25][29][17]	MAIN[35][29][17]
A_PLLCLKRXRESET bit 0	MAIN[3][28][38]	MAIN[13][28][38]	MAIN[23][28][38]	MAIN[33][28][38]
A_PLLCLKTXRESET bit 0	MAIN[4][28][6]	MAIN[14][28][6]	MAIN[24][28][6]	MAIN[34][28][6]
A_PLLRXRESET bit 0	MAIN[3][28][37]	MAIN[13][28][37]	MAIN[23][28][37]	MAIN[33][28][37]
A_PLLTXRESET bit 0	MAIN[4][28][5]	MAIN[14][28][5]	MAIN[24][28][5]	MAIN[34][28][5]
A_PRBSCNTRESET bit 0	MAIN[5][28][23]	MAIN[15][28][23]	MAIN[25][28][23]	MAIN[35][28][23]
A_RXBUFRESET bit 0	MAIN[3][29][3]	MAIN[13][29][3]	MAIN[23][29][3]	MAIN[33][29][3]
A_RXCDRFREQRESET bit 0	MAIN[3][29][5]	MAIN[13][29][5]	MAIN[23][29][5]	MAIN[33][29][5]
A_RXCDRHOLD bit 0	MAIN[3][28][5]	MAIN[13][28][5]	MAIN[23][28][5]	MAIN[33][28][5]
A_RXCDRPHASERESET bit 0	MAIN[3][28][6]	MAIN[13][28][6]	MAIN[23][28][6]	MAIN[33][28][6]
A_RXCDRRESET bit 0	MAIN[3][28][2]	MAIN[13][28][2]	MAIN[23][28][2]	MAIN[33][28][2]
A_RXDFERESET bit 0	MAIN[3][29][6]	MAIN[13][29][6]	MAIN[23][29][6]	MAIN[33][29][6]
A_RXENPMAPHASEALIGN bit 0	MAIN[4][28][47]	MAIN[14][28][47]	MAIN[24][28][47]	MAIN[34][28][47]
A_RXENPRBSTST bit 0	MAIN[5][29][18]	MAIN[15][29][18]	MAIN[25][29][18]	MAIN[35][29][18]
A_RXENPRBSTST bit 1	MAIN[5][28][19]	MAIN[15][28][19]	MAIN[25][28][19]	MAIN[35][28][19]
A_RXENPRBSTST bit 2	MAIN[5][29][19]	MAIN[15][29][19]	MAIN[25][29][19]	MAIN[35][29][19]
A_RXENSAMPLEALIGN bit 0	MAIN[5][28][15]	MAIN[15][28][15]	MAIN[25][28][15]	MAIN[35][28][15]
A_RXEQMIX bit 0	MAIN[8][28][0]	MAIN[18][28][0]	MAIN[28][28][0]	MAIN[38][28][0]
A_RXEQMIX bit 1	MAIN[8][29][0]	MAIN[18][29][0]	MAIN[28][29][0]	MAIN[38][29][0]
A_RXEQMIX bit 2	MAIN[8][28][1]	MAIN[18][28][1]	MAIN[28][28][1]	MAIN[38][28][1]
A_RXEQMIX bit 3	MAIN[8][29][1]	MAIN[18][29][1]	MAIN[28][29][1]	MAIN[38][29][1]
A_RXEQMIX bit 4	MAIN[8][28][2]	MAIN[18][28][2]	MAIN[28][28][2]	MAIN[38][28][2]
A_RXEQMIX bit 5	MAIN[8][29][2]	MAIN[18][29][2]	MAIN[28][29][2]	MAIN[38][29][2]
A_RXEQMIX bit 6	MAIN[8][28][3]	MAIN[18][28][3]	MAIN[28][28][3]	MAIN[38][28][3]
A_RXEQMIX bit 7	MAIN[8][29][3]	MAIN[18][29][3]	MAIN[28][29][3]	MAIN[38][29][3]
A_RXEQMIX bit 8	MAIN[8][28][4]	MAIN[18][28][4]	MAIN[28][28][4]	MAIN[38][28][4]
A_RXEQMIX bit 9	MAIN[8][29][4]	MAIN[18][29][4]	MAIN[28][29][4]	MAIN[38][29][4]
A_RXPLLLKDETEN bit 0	MAIN[3][29][37]	MAIN[13][29][37]	MAIN[23][29][37]	MAIN[33][29][37]
A_RXPLLPOWERDOWN bit 0	MAIN[3][28][39]	MAIN[13][28][39]	MAIN[23][28][39]	MAIN[33][28][39]
A_RXPMASETPHASE bit 0	MAIN[4][29][46]	MAIN[14][29][46]	MAIN[24][29][46]	MAIN[34][29][46]
A_RXPOLARITY bit 0	MAIN[4][28][45]	MAIN[14][28][45]	MAIN[24][28][45]	MAIN[34][28][45]
A_RXPOWERDOWN bit 0	MAIN[3][29][28]	MAIN[13][29][28]	MAIN[23][29][28]	MAIN[33][29][28]
A_RXPOWERDOWN bit 1	MAIN[3][28][29]	MAIN[13][28][29]	MAIN[23][28][29]	MAIN[33][28][29]
A_RXRESET bit 0	MAIN[3][28][4]	MAIN[13][28][4]	MAIN[23][28][4]	MAIN[33][28][4]
A_TXBUFDIFFCTRL bit 0	MAIN[7][28][42]	MAIN[17][28][42]	MAIN[27][28][42]	MAIN[37][28][42]
A_TXBUFDIFFCTRL bit 1	MAIN[7][29][42]	MAIN[17][29][42]	MAIN[27][29][42]	MAIN[37][29][42]
A_TXBUFDIFFCTRL bit 2	MAIN[7][28][43]	MAIN[17][28][43]	MAIN[27][28][43]	MAIN[37][28][43]
A_TXDEEMPH bit 0	MAIN[7][29][31]	MAIN[17][29][31]	MAIN[27][29][31]	MAIN[37][29][31]
A_TXDIFFCTRL bit 0	MAIN[7][28][40]	MAIN[17][28][40]	MAIN[27][28][40]	MAIN[37][28][40]
A_TXDIFFCTRL bit 1	MAIN[7][29][40]	MAIN[17][29][40]	MAIN[27][29][40]	MAIN[37][29][40]
A_TXDIFFCTRL bit 2	MAIN[7][28][41]	MAIN[17][28][41]	MAIN[27][28][41]	MAIN[37][28][41]
A_TXDIFFCTRL bit 3	MAIN[7][29][41]	MAIN[17][29][41]	MAIN[27][29][41]	MAIN[37][29][41]
A_TXELECIDLE bit 0	MAIN[4][28][15]	MAIN[14][28][15]	MAIN[24][28][15]	MAIN[34][28][15]
A_TXENPMAPHASEALIGN bit 0	MAIN[5][29][14]	MAIN[15][29][14]	MAIN[25][29][14]	MAIN[35][29][14]
A_TXENPRBSTST bit 0	MAIN[5][29][21]	MAIN[15][29][21]	MAIN[25][29][21]	MAIN[35][29][21]
A_TXENPRBSTST bit 1	MAIN[5][28][22]	MAIN[15][28][22]	MAIN[25][28][22]	MAIN[35][28][22]
A_TXENPRBSTST bit 2	MAIN[5][29][22]	MAIN[15][29][22]	MAIN[25][29][22]	MAIN[35][29][22]
A_TXMARGIN bit 0	MAIN[7][29][54]	MAIN[17][29][54]	MAIN[27][29][54]	MAIN[37][29][54]
A_TXMARGIN bit 1	MAIN[7][28][55]	MAIN[17][28][55]	MAIN[27][28][55]	MAIN[37][28][55]
A_TXMARGIN bit 2	MAIN[7][29][55]	MAIN[17][29][55]	MAIN[27][29][55]	MAIN[37][29][55]
A_TXPLLLKDETEN bit 0	MAIN[4][29][5]	MAIN[14][29][5]	MAIN[24][29][5]	MAIN[34][29][5]
A_TXPLLPOWERDOWN bit 0	MAIN[4][28][7]	MAIN[14][28][7]	MAIN[24][28][7]	MAIN[34][28][7]
A_TXPMASETPHASE bit 0	MAIN[5][28][14]	MAIN[15][28][14]	MAIN[25][28][14]	MAIN[35][28][14]
A_TXPOLARITY bit 0	MAIN[4][29][45]	MAIN[14][29][45]	MAIN[24][29][45]	MAIN[34][29][45]
A_TXPOSTEMPHASIS bit 0	MAIN[7][29][45]	MAIN[17][29][45]	MAIN[27][29][45]	MAIN[37][29][45]
A_TXPOSTEMPHASIS bit 1	MAIN[7][28][46]	MAIN[17][28][46]	MAIN[27][28][46]	MAIN[37][28][46]
A_TXPOSTEMPHASIS bit 2	MAIN[7][29][46]	MAIN[17][29][46]	MAIN[27][29][46]	MAIN[37][29][46]
A_TXPOSTEMPHASIS bit 3	MAIN[7][28][47]	MAIN[17][28][47]	MAIN[27][28][47]	MAIN[37][28][47]
A_TXPOSTEMPHASIS bit 4	MAIN[7][29][47]	MAIN[17][29][47]	MAIN[27][29][47]	MAIN[37][29][47]
A_TXPOWERDOWN bit 0	MAIN[3][29][60]	MAIN[13][29][60]	MAIN[23][29][60]	MAIN[33][29][60]
A_TXPOWERDOWN bit 1	MAIN[3][28][61]	MAIN[13][28][61]	MAIN[23][28][61]	MAIN[33][28][61]
A_TXPRBSFORCEERR bit 0	MAIN[5][28][21]	MAIN[15][28][21]	MAIN[25][28][21]	MAIN[35][28][21]
A_TXPREEMPHASIS bit 0	MAIN[7][29][43]	MAIN[17][29][43]	MAIN[27][29][43]	MAIN[37][29][43]
A_TXPREEMPHASIS bit 1	MAIN[7][28][44]	MAIN[17][28][44]	MAIN[27][28][44]	MAIN[37][28][44]
A_TXPREEMPHASIS bit 2	MAIN[7][29][44]	MAIN[17][29][44]	MAIN[27][29][44]	MAIN[37][29][44]
A_TXPREEMPHASIS bit 3	MAIN[7][28][45]	MAIN[17][28][45]	MAIN[27][28][45]	MAIN[37][28][45]
A_TXRESET bit 0	MAIN[3][29][4]	MAIN[13][29][4]	MAIN[23][29][4]	MAIN[33][29][4]
A_TXSWING bit 0	MAIN[7][28][31]	MAIN[17][28][31]	MAIN[27][28][31]	MAIN[37][28][31]
BGTEST_CFG bit 0	MAIN[4][28][55]	MAIN[14][28][55]	MAIN[24][28][55]	MAIN[34][28][55]
BGTEST_CFG bit 1	MAIN[4][29][55]	MAIN[14][29][55]	MAIN[24][29][55]	MAIN[34][29][55]
CDR_PH_ADJ_TIME bit 0	MAIN[2][29][53]	MAIN[12][29][53]	MAIN[22][29][53]	MAIN[32][29][53]
CDR_PH_ADJ_TIME bit 1	MAIN[2][28][54]	MAIN[12][28][54]	MAIN[22][28][54]	MAIN[32][28][54]
CDR_PH_ADJ_TIME bit 2	MAIN[2][29][54]	MAIN[12][29][54]	MAIN[22][29][54]	MAIN[32][29][54]
CDR_PH_ADJ_TIME bit 3	MAIN[2][28][55]	MAIN[12][28][55]	MAIN[22][28][55]	MAIN[32][28][55]
CDR_PH_ADJ_TIME bit 4	MAIN[2][29][55]	MAIN[12][29][55]	MAIN[22][29][55]	MAIN[32][29][55]
CHAN_BOND_SEQ_1_1 bit 0	MAIN[0][28][32]	MAIN[10][28][32]	MAIN[20][28][32]	MAIN[30][28][32]
CHAN_BOND_SEQ_1_1 bit 1	MAIN[0][29][32]	MAIN[10][29][32]	MAIN[20][29][32]	MAIN[30][29][32]
CHAN_BOND_SEQ_1_1 bit 2	MAIN[0][28][33]	MAIN[10][28][33]	MAIN[20][28][33]	MAIN[30][28][33]
CHAN_BOND_SEQ_1_1 bit 3	MAIN[0][29][33]	MAIN[10][29][33]	MAIN[20][29][33]	MAIN[30][29][33]
CHAN_BOND_SEQ_1_1 bit 4	MAIN[0][28][34]	MAIN[10][28][34]	MAIN[20][28][34]	MAIN[30][28][34]
CHAN_BOND_SEQ_1_1 bit 5	MAIN[0][29][34]	MAIN[10][29][34]	MAIN[20][29][34]	MAIN[30][29][34]
CHAN_BOND_SEQ_1_1 bit 6	MAIN[0][28][35]	MAIN[10][28][35]	MAIN[20][28][35]	MAIN[30][28][35]
CHAN_BOND_SEQ_1_1 bit 7	MAIN[0][29][35]	MAIN[10][29][35]	MAIN[20][29][35]	MAIN[30][29][35]
CHAN_BOND_SEQ_1_1 bit 8	MAIN[0][28][36]	MAIN[10][28][36]	MAIN[20][28][36]	MAIN[30][28][36]
CHAN_BOND_SEQ_1_1 bit 9	MAIN[0][29][36]	MAIN[10][29][36]	MAIN[20][29][36]	MAIN[30][29][36]
CHAN_BOND_SEQ_1_2 bit 0	MAIN[0][28][40]	MAIN[10][28][40]	MAIN[20][28][40]	MAIN[30][28][40]
CHAN_BOND_SEQ_1_2 bit 1	MAIN[0][29][40]	MAIN[10][29][40]	MAIN[20][29][40]	MAIN[30][29][40]
CHAN_BOND_SEQ_1_2 bit 2	MAIN[0][28][41]	MAIN[10][28][41]	MAIN[20][28][41]	MAIN[30][28][41]
CHAN_BOND_SEQ_1_2 bit 3	MAIN[0][29][41]	MAIN[10][29][41]	MAIN[20][29][41]	MAIN[30][29][41]
CHAN_BOND_SEQ_1_2 bit 4	MAIN[0][28][42]	MAIN[10][28][42]	MAIN[20][28][42]	MAIN[30][28][42]
CHAN_BOND_SEQ_1_2 bit 5	MAIN[0][29][42]	MAIN[10][29][42]	MAIN[20][29][42]	MAIN[30][29][42]
CHAN_BOND_SEQ_1_2 bit 6	MAIN[0][28][43]	MAIN[10][28][43]	MAIN[20][28][43]	MAIN[30][28][43]
CHAN_BOND_SEQ_1_2 bit 7	MAIN[0][29][43]	MAIN[10][29][43]	MAIN[20][29][43]	MAIN[30][29][43]
CHAN_BOND_SEQ_1_2 bit 8	MAIN[0][28][44]	MAIN[10][28][44]	MAIN[20][28][44]	MAIN[30][28][44]
CHAN_BOND_SEQ_1_2 bit 9	MAIN[0][29][44]	MAIN[10][29][44]	MAIN[20][29][44]	MAIN[30][29][44]
CHAN_BOND_SEQ_1_3 bit 0	MAIN[0][28][48]	MAIN[10][28][48]	MAIN[20][28][48]	MAIN[30][28][48]
CHAN_BOND_SEQ_1_3 bit 1	MAIN[0][29][48]	MAIN[10][29][48]	MAIN[20][29][48]	MAIN[30][29][48]
CHAN_BOND_SEQ_1_3 bit 2	MAIN[0][28][49]	MAIN[10][28][49]	MAIN[20][28][49]	MAIN[30][28][49]
CHAN_BOND_SEQ_1_3 bit 3	MAIN[0][29][49]	MAIN[10][29][49]	MAIN[20][29][49]	MAIN[30][29][49]
CHAN_BOND_SEQ_1_3 bit 4	MAIN[0][28][50]	MAIN[10][28][50]	MAIN[20][28][50]	MAIN[30][28][50]
CHAN_BOND_SEQ_1_3 bit 5	MAIN[0][29][50]	MAIN[10][29][50]	MAIN[20][29][50]	MAIN[30][29][50]
CHAN_BOND_SEQ_1_3 bit 6	MAIN[0][28][51]	MAIN[10][28][51]	MAIN[20][28][51]	MAIN[30][28][51]
CHAN_BOND_SEQ_1_3 bit 7	MAIN[0][29][51]	MAIN[10][29][51]	MAIN[20][29][51]	MAIN[30][29][51]
CHAN_BOND_SEQ_1_3 bit 8	MAIN[0][28][52]	MAIN[10][28][52]	MAIN[20][28][52]	MAIN[30][28][52]
CHAN_BOND_SEQ_1_3 bit 9	MAIN[0][29][52]	MAIN[10][29][52]	MAIN[20][29][52]	MAIN[30][29][52]
CHAN_BOND_SEQ_1_4 bit 0	MAIN[0][28][56]	MAIN[10][28][56]	MAIN[20][28][56]	MAIN[30][28][56]
CHAN_BOND_SEQ_1_4 bit 1	MAIN[0][29][56]	MAIN[10][29][56]	MAIN[20][29][56]	MAIN[30][29][56]
CHAN_BOND_SEQ_1_4 bit 2	MAIN[0][28][57]	MAIN[10][28][57]	MAIN[20][28][57]	MAIN[30][28][57]
CHAN_BOND_SEQ_1_4 bit 3	MAIN[0][29][57]	MAIN[10][29][57]	MAIN[20][29][57]	MAIN[30][29][57]
CHAN_BOND_SEQ_1_4 bit 4	MAIN[0][28][58]	MAIN[10][28][58]	MAIN[20][28][58]	MAIN[30][28][58]
CHAN_BOND_SEQ_1_4 bit 5	MAIN[0][29][58]	MAIN[10][29][58]	MAIN[20][29][58]	MAIN[30][29][58]
CHAN_BOND_SEQ_1_4 bit 6	MAIN[0][28][59]	MAIN[10][28][59]	MAIN[20][28][59]	MAIN[30][28][59]
CHAN_BOND_SEQ_1_4 bit 7	MAIN[0][29][59]	MAIN[10][29][59]	MAIN[20][29][59]	MAIN[30][29][59]
CHAN_BOND_SEQ_1_4 bit 8	MAIN[0][28][60]	MAIN[10][28][60]	MAIN[20][28][60]	MAIN[30][28][60]
CHAN_BOND_SEQ_1_4 bit 9	MAIN[0][29][60]	MAIN[10][29][60]	MAIN[20][29][60]	MAIN[30][29][60]
CHAN_BOND_SEQ_1_ENABLE bit 0	MAIN[0][28][37]	MAIN[10][28][37]	MAIN[20][28][37]	MAIN[30][28][37]
CHAN_BOND_SEQ_1_ENABLE bit 1	MAIN[0][29][37]	MAIN[10][29][37]	MAIN[20][29][37]	MAIN[30][29][37]
CHAN_BOND_SEQ_1_ENABLE bit 2	MAIN[0][28][38]	MAIN[10][28][38]	MAIN[20][28][38]	MAIN[30][28][38]
CHAN_BOND_SEQ_1_ENABLE bit 3	MAIN[0][29][38]	MAIN[10][29][38]	MAIN[20][29][38]	MAIN[30][29][38]
CHAN_BOND_SEQ_2_1 bit 0	MAIN[1][28][0]	MAIN[11][28][0]	MAIN[21][28][0]	MAIN[31][28][0]
CHAN_BOND_SEQ_2_1 bit 1	MAIN[1][29][0]	MAIN[11][29][0]	MAIN[21][29][0]	MAIN[31][29][0]
CHAN_BOND_SEQ_2_1 bit 2	MAIN[1][28][1]	MAIN[11][28][1]	MAIN[21][28][1]	MAIN[31][28][1]
CHAN_BOND_SEQ_2_1 bit 3	MAIN[1][29][1]	MAIN[11][29][1]	MAIN[21][29][1]	MAIN[31][29][1]
CHAN_BOND_SEQ_2_1 bit 4	MAIN[1][28][2]	MAIN[11][28][2]	MAIN[21][28][2]	MAIN[31][28][2]
CHAN_BOND_SEQ_2_1 bit 5	MAIN[1][29][2]	MAIN[11][29][2]	MAIN[21][29][2]	MAIN[31][29][2]
CHAN_BOND_SEQ_2_1 bit 6	MAIN[1][28][3]	MAIN[11][28][3]	MAIN[21][28][3]	MAIN[31][28][3]
CHAN_BOND_SEQ_2_1 bit 7	MAIN[1][29][3]	MAIN[11][29][3]	MAIN[21][29][3]	MAIN[31][29][3]
CHAN_BOND_SEQ_2_1 bit 8	MAIN[1][28][4]	MAIN[11][28][4]	MAIN[21][28][4]	MAIN[31][28][4]
CHAN_BOND_SEQ_2_1 bit 9	MAIN[1][29][4]	MAIN[11][29][4]	MAIN[21][29][4]	MAIN[31][29][4]
CHAN_BOND_SEQ_2_2 bit 0	MAIN[1][28][8]	MAIN[11][28][8]	MAIN[21][28][8]	MAIN[31][28][8]
CHAN_BOND_SEQ_2_2 bit 1	MAIN[1][29][8]	MAIN[11][29][8]	MAIN[21][29][8]	MAIN[31][29][8]
CHAN_BOND_SEQ_2_2 bit 2	MAIN[1][28][9]	MAIN[11][28][9]	MAIN[21][28][9]	MAIN[31][28][9]
CHAN_BOND_SEQ_2_2 bit 3	MAIN[1][29][9]	MAIN[11][29][9]	MAIN[21][29][9]	MAIN[31][29][9]
CHAN_BOND_SEQ_2_2 bit 4	MAIN[1][28][10]	MAIN[11][28][10]	MAIN[21][28][10]	MAIN[31][28][10]
CHAN_BOND_SEQ_2_2 bit 5	MAIN[1][29][10]	MAIN[11][29][10]	MAIN[21][29][10]	MAIN[31][29][10]
CHAN_BOND_SEQ_2_2 bit 6	MAIN[1][28][11]	MAIN[11][28][11]	MAIN[21][28][11]	MAIN[31][28][11]
CHAN_BOND_SEQ_2_2 bit 7	MAIN[1][29][11]	MAIN[11][29][11]	MAIN[21][29][11]	MAIN[31][29][11]
CHAN_BOND_SEQ_2_2 bit 8	MAIN[1][28][12]	MAIN[11][28][12]	MAIN[21][28][12]	MAIN[31][28][12]
CHAN_BOND_SEQ_2_2 bit 9	MAIN[1][29][12]	MAIN[11][29][12]	MAIN[21][29][12]	MAIN[31][29][12]
CHAN_BOND_SEQ_2_3 bit 0	MAIN[1][28][16]	MAIN[11][28][16]	MAIN[21][28][16]	MAIN[31][28][16]
CHAN_BOND_SEQ_2_3 bit 1	MAIN[1][29][16]	MAIN[11][29][16]	MAIN[21][29][16]	MAIN[31][29][16]
CHAN_BOND_SEQ_2_3 bit 2	MAIN[1][28][17]	MAIN[11][28][17]	MAIN[21][28][17]	MAIN[31][28][17]
CHAN_BOND_SEQ_2_3 bit 3	MAIN[1][29][17]	MAIN[11][29][17]	MAIN[21][29][17]	MAIN[31][29][17]
CHAN_BOND_SEQ_2_3 bit 4	MAIN[1][28][18]	MAIN[11][28][18]	MAIN[21][28][18]	MAIN[31][28][18]
CHAN_BOND_SEQ_2_3 bit 5	MAIN[1][29][18]	MAIN[11][29][18]	MAIN[21][29][18]	MAIN[31][29][18]
CHAN_BOND_SEQ_2_3 bit 6	MAIN[1][28][19]	MAIN[11][28][19]	MAIN[21][28][19]	MAIN[31][28][19]
CHAN_BOND_SEQ_2_3 bit 7	MAIN[1][29][19]	MAIN[11][29][19]	MAIN[21][29][19]	MAIN[31][29][19]
CHAN_BOND_SEQ_2_3 bit 8	MAIN[1][28][20]	MAIN[11][28][20]	MAIN[21][28][20]	MAIN[31][28][20]
CHAN_BOND_SEQ_2_3 bit 9	MAIN[1][29][20]	MAIN[11][29][20]	MAIN[21][29][20]	MAIN[31][29][20]
CHAN_BOND_SEQ_2_4 bit 0	MAIN[1][28][24]	MAIN[11][28][24]	MAIN[21][28][24]	MAIN[31][28][24]
CHAN_BOND_SEQ_2_4 bit 1	MAIN[1][29][24]	MAIN[11][29][24]	MAIN[21][29][24]	MAIN[31][29][24]
CHAN_BOND_SEQ_2_4 bit 2	MAIN[1][28][25]	MAIN[11][28][25]	MAIN[21][28][25]	MAIN[31][28][25]
CHAN_BOND_SEQ_2_4 bit 3	MAIN[1][29][25]	MAIN[11][29][25]	MAIN[21][29][25]	MAIN[31][29][25]
CHAN_BOND_SEQ_2_4 bit 4	MAIN[1][28][26]	MAIN[11][28][26]	MAIN[21][28][26]	MAIN[31][28][26]
CHAN_BOND_SEQ_2_4 bit 5	MAIN[1][29][26]	MAIN[11][29][26]	MAIN[21][29][26]	MAIN[31][29][26]
CHAN_BOND_SEQ_2_4 bit 6	MAIN[1][28][27]	MAIN[11][28][27]	MAIN[21][28][27]	MAIN[31][28][27]
CHAN_BOND_SEQ_2_4 bit 7	MAIN[1][29][27]	MAIN[11][29][27]	MAIN[21][29][27]	MAIN[31][29][27]
CHAN_BOND_SEQ_2_4 bit 8	MAIN[1][28][28]	MAIN[11][28][28]	MAIN[21][28][28]	MAIN[31][28][28]
CHAN_BOND_SEQ_2_4 bit 9	MAIN[1][29][28]	MAIN[11][29][28]	MAIN[21][29][28]	MAIN[31][29][28]
CHAN_BOND_SEQ_2_CFG bit 0	MAIN[1][28][21]	MAIN[11][28][21]	MAIN[21][28][21]	MAIN[31][28][21]
CHAN_BOND_SEQ_2_CFG bit 1	MAIN[1][29][21]	MAIN[11][29][21]	MAIN[21][29][21]	MAIN[31][29][21]
CHAN_BOND_SEQ_2_CFG bit 2	MAIN[1][28][22]	MAIN[11][28][22]	MAIN[21][28][22]	MAIN[31][28][22]
CHAN_BOND_SEQ_2_CFG bit 3	MAIN[1][29][22]	MAIN[11][29][22]	MAIN[21][29][22]	MAIN[31][29][22]
CHAN_BOND_SEQ_2_CFG bit 4	MAIN[2][29][61]	MAIN[12][29][61]	MAIN[22][29][61]	MAIN[32][29][61]
CHAN_BOND_SEQ_2_ENABLE bit 0	MAIN[1][28][5]	MAIN[11][28][5]	MAIN[21][28][5]	MAIN[31][28][5]
CHAN_BOND_SEQ_2_ENABLE bit 1	MAIN[1][29][5]	MAIN[11][29][5]	MAIN[21][29][5]	MAIN[31][29][5]
CHAN_BOND_SEQ_2_ENABLE bit 2	MAIN[1][28][6]	MAIN[11][28][6]	MAIN[21][28][6]	MAIN[31][28][6]
CHAN_BOND_SEQ_2_ENABLE bit 3	MAIN[1][29][6]	MAIN[11][29][6]	MAIN[21][29][6]	MAIN[31][29][6]
CLK_COR_SEQ_1_1 bit 0	MAIN[1][28][40]	MAIN[11][28][40]	MAIN[21][28][40]	MAIN[31][28][40]
CLK_COR_SEQ_1_1 bit 1	MAIN[1][29][40]	MAIN[11][29][40]	MAIN[21][29][40]	MAIN[31][29][40]
CLK_COR_SEQ_1_1 bit 2	MAIN[1][28][41]	MAIN[11][28][41]	MAIN[21][28][41]	MAIN[31][28][41]
CLK_COR_SEQ_1_1 bit 3	MAIN[1][29][41]	MAIN[11][29][41]	MAIN[21][29][41]	MAIN[31][29][41]
CLK_COR_SEQ_1_1 bit 4	MAIN[1][28][42]	MAIN[11][28][42]	MAIN[21][28][42]	MAIN[31][28][42]
CLK_COR_SEQ_1_1 bit 5	MAIN[1][29][42]	MAIN[11][29][42]	MAIN[21][29][42]	MAIN[31][29][42]
CLK_COR_SEQ_1_1 bit 6	MAIN[1][28][43]	MAIN[11][28][43]	MAIN[21][28][43]	MAIN[31][28][43]
CLK_COR_SEQ_1_1 bit 7	MAIN[1][29][43]	MAIN[11][29][43]	MAIN[21][29][43]	MAIN[31][29][43]
CLK_COR_SEQ_1_1 bit 8	MAIN[1][28][44]	MAIN[11][28][44]	MAIN[21][28][44]	MAIN[31][28][44]
CLK_COR_SEQ_1_1 bit 9	MAIN[1][29][44]	MAIN[11][29][44]	MAIN[21][29][44]	MAIN[31][29][44]
CLK_COR_SEQ_1_2 bit 0	MAIN[1][28][48]	MAIN[11][28][48]	MAIN[21][28][48]	MAIN[31][28][48]
CLK_COR_SEQ_1_2 bit 1	MAIN[1][29][48]	MAIN[11][29][48]	MAIN[21][29][48]	MAIN[31][29][48]
CLK_COR_SEQ_1_2 bit 2	MAIN[1][28][49]	MAIN[11][28][49]	MAIN[21][28][49]	MAIN[31][28][49]
CLK_COR_SEQ_1_2 bit 3	MAIN[1][29][49]	MAIN[11][29][49]	MAIN[21][29][49]	MAIN[31][29][49]
CLK_COR_SEQ_1_2 bit 4	MAIN[1][28][50]	MAIN[11][28][50]	MAIN[21][28][50]	MAIN[31][28][50]
CLK_COR_SEQ_1_2 bit 5	MAIN[1][29][50]	MAIN[11][29][50]	MAIN[21][29][50]	MAIN[31][29][50]
CLK_COR_SEQ_1_2 bit 6	MAIN[1][28][51]	MAIN[11][28][51]	MAIN[21][28][51]	MAIN[31][28][51]
CLK_COR_SEQ_1_2 bit 7	MAIN[1][29][51]	MAIN[11][29][51]	MAIN[21][29][51]	MAIN[31][29][51]
CLK_COR_SEQ_1_2 bit 8	MAIN[1][28][52]	MAIN[11][28][52]	MAIN[21][28][52]	MAIN[31][28][52]
CLK_COR_SEQ_1_2 bit 9	MAIN[1][29][52]	MAIN[11][29][52]	MAIN[21][29][52]	MAIN[31][29][52]
CLK_COR_SEQ_1_3 bit 0	MAIN[1][28][56]	MAIN[11][28][56]	MAIN[21][28][56]	MAIN[31][28][56]
CLK_COR_SEQ_1_3 bit 1	MAIN[1][29][56]	MAIN[11][29][56]	MAIN[21][29][56]	MAIN[31][29][56]
CLK_COR_SEQ_1_3 bit 2	MAIN[1][28][57]	MAIN[11][28][57]	MAIN[21][28][57]	MAIN[31][28][57]
CLK_COR_SEQ_1_3 bit 3	MAIN[1][29][57]	MAIN[11][29][57]	MAIN[21][29][57]	MAIN[31][29][57]
CLK_COR_SEQ_1_3 bit 4	MAIN[1][28][58]	MAIN[11][28][58]	MAIN[21][28][58]	MAIN[31][28][58]
CLK_COR_SEQ_1_3 bit 5	MAIN[1][29][58]	MAIN[11][29][58]	MAIN[21][29][58]	MAIN[31][29][58]
CLK_COR_SEQ_1_3 bit 6	MAIN[1][28][59]	MAIN[11][28][59]	MAIN[21][28][59]	MAIN[31][28][59]
CLK_COR_SEQ_1_3 bit 7	MAIN[1][29][59]	MAIN[11][29][59]	MAIN[21][29][59]	MAIN[31][29][59]
CLK_COR_SEQ_1_3 bit 8	MAIN[1][28][60]	MAIN[11][28][60]	MAIN[21][28][60]	MAIN[31][28][60]
CLK_COR_SEQ_1_3 bit 9	MAIN[1][29][60]	MAIN[11][29][60]	MAIN[21][29][60]	MAIN[31][29][60]
CLK_COR_SEQ_1_4 bit 0	MAIN[2][28][0]	MAIN[12][28][0]	MAIN[22][28][0]	MAIN[32][28][0]
CLK_COR_SEQ_1_4 bit 1	MAIN[2][29][0]	MAIN[12][29][0]	MAIN[22][29][0]	MAIN[32][29][0]
CLK_COR_SEQ_1_4 bit 2	MAIN[2][28][1]	MAIN[12][28][1]	MAIN[22][28][1]	MAIN[32][28][1]
CLK_COR_SEQ_1_4 bit 3	MAIN[2][29][1]	MAIN[12][29][1]	MAIN[22][29][1]	MAIN[32][29][1]
CLK_COR_SEQ_1_4 bit 4	MAIN[2][28][2]	MAIN[12][28][2]	MAIN[22][28][2]	MAIN[32][28][2]
CLK_COR_SEQ_1_4 bit 5	MAIN[2][29][2]	MAIN[12][29][2]	MAIN[22][29][2]	MAIN[32][29][2]
CLK_COR_SEQ_1_4 bit 6	MAIN[2][28][3]	MAIN[12][28][3]	MAIN[22][28][3]	MAIN[32][28][3]
CLK_COR_SEQ_1_4 bit 7	MAIN[2][29][3]	MAIN[12][29][3]	MAIN[22][29][3]	MAIN[32][29][3]
CLK_COR_SEQ_1_4 bit 8	MAIN[2][28][4]	MAIN[12][28][4]	MAIN[22][28][4]	MAIN[32][28][4]
CLK_COR_SEQ_1_4 bit 9	MAIN[2][29][4]	MAIN[12][29][4]	MAIN[22][29][4]	MAIN[32][29][4]
CLK_COR_SEQ_1_ENABLE bit 0	MAIN[1][28][45]	MAIN[11][28][45]	MAIN[21][28][45]	MAIN[31][28][45]
CLK_COR_SEQ_1_ENABLE bit 1	MAIN[1][29][45]	MAIN[11][29][45]	MAIN[21][29][45]	MAIN[31][29][45]
CLK_COR_SEQ_1_ENABLE bit 2	MAIN[1][28][46]	MAIN[11][28][46]	MAIN[21][28][46]	MAIN[31][28][46]
CLK_COR_SEQ_1_ENABLE bit 3	MAIN[1][29][46]	MAIN[11][29][46]	MAIN[21][29][46]	MAIN[31][29][46]
CLK_COR_SEQ_2_1 bit 0	MAIN[2][28][8]	MAIN[12][28][8]	MAIN[22][28][8]	MAIN[32][28][8]
CLK_COR_SEQ_2_1 bit 1	MAIN[2][29][8]	MAIN[12][29][8]	MAIN[22][29][8]	MAIN[32][29][8]
CLK_COR_SEQ_2_1 bit 2	MAIN[2][28][9]	MAIN[12][28][9]	MAIN[22][28][9]	MAIN[32][28][9]
CLK_COR_SEQ_2_1 bit 3	MAIN[2][29][9]	MAIN[12][29][9]	MAIN[22][29][9]	MAIN[32][29][9]
CLK_COR_SEQ_2_1 bit 4	MAIN[2][28][10]	MAIN[12][28][10]	MAIN[22][28][10]	MAIN[32][28][10]
CLK_COR_SEQ_2_1 bit 5	MAIN[2][29][10]	MAIN[12][29][10]	MAIN[22][29][10]	MAIN[32][29][10]
CLK_COR_SEQ_2_1 bit 6	MAIN[2][28][11]	MAIN[12][28][11]	MAIN[22][28][11]	MAIN[32][28][11]
CLK_COR_SEQ_2_1 bit 7	MAIN[2][29][11]	MAIN[12][29][11]	MAIN[22][29][11]	MAIN[32][29][11]
CLK_COR_SEQ_2_1 bit 8	MAIN[2][28][12]	MAIN[12][28][12]	MAIN[22][28][12]	MAIN[32][28][12]
CLK_COR_SEQ_2_1 bit 9	MAIN[2][29][12]	MAIN[12][29][12]	MAIN[22][29][12]	MAIN[32][29][12]
CLK_COR_SEQ_2_2 bit 0	MAIN[2][28][16]	MAIN[12][28][16]	MAIN[22][28][16]	MAIN[32][28][16]
CLK_COR_SEQ_2_2 bit 1	MAIN[2][29][16]	MAIN[12][29][16]	MAIN[22][29][16]	MAIN[32][29][16]
CLK_COR_SEQ_2_2 bit 2	MAIN[2][28][17]	MAIN[12][28][17]	MAIN[22][28][17]	MAIN[32][28][17]
CLK_COR_SEQ_2_2 bit 3	MAIN[2][29][17]	MAIN[12][29][17]	MAIN[22][29][17]	MAIN[32][29][17]
CLK_COR_SEQ_2_2 bit 4	MAIN[2][28][18]	MAIN[12][28][18]	MAIN[22][28][18]	MAIN[32][28][18]
CLK_COR_SEQ_2_2 bit 5	MAIN[2][29][18]	MAIN[12][29][18]	MAIN[22][29][18]	MAIN[32][29][18]
CLK_COR_SEQ_2_2 bit 6	MAIN[2][28][19]	MAIN[12][28][19]	MAIN[22][28][19]	MAIN[32][28][19]
CLK_COR_SEQ_2_2 bit 7	MAIN[2][29][19]	MAIN[12][29][19]	MAIN[22][29][19]	MAIN[32][29][19]
CLK_COR_SEQ_2_2 bit 8	MAIN[2][28][20]	MAIN[12][28][20]	MAIN[22][28][20]	MAIN[32][28][20]
CLK_COR_SEQ_2_2 bit 9	MAIN[2][29][20]	MAIN[12][29][20]	MAIN[22][29][20]	MAIN[32][29][20]
CLK_COR_SEQ_2_3 bit 0	MAIN[2][28][24]	MAIN[12][28][24]	MAIN[22][28][24]	MAIN[32][28][24]
CLK_COR_SEQ_2_3 bit 1	MAIN[2][29][24]	MAIN[12][29][24]	MAIN[22][29][24]	MAIN[32][29][24]
CLK_COR_SEQ_2_3 bit 2	MAIN[2][28][25]	MAIN[12][28][25]	MAIN[22][28][25]	MAIN[32][28][25]
CLK_COR_SEQ_2_3 bit 3	MAIN[2][29][25]	MAIN[12][29][25]	MAIN[22][29][25]	MAIN[32][29][25]
CLK_COR_SEQ_2_3 bit 4	MAIN[2][28][26]	MAIN[12][28][26]	MAIN[22][28][26]	MAIN[32][28][26]
CLK_COR_SEQ_2_3 bit 5	MAIN[2][29][26]	MAIN[12][29][26]	MAIN[22][29][26]	MAIN[32][29][26]
CLK_COR_SEQ_2_3 bit 6	MAIN[2][28][27]	MAIN[12][28][27]	MAIN[22][28][27]	MAIN[32][28][27]
CLK_COR_SEQ_2_3 bit 7	MAIN[2][29][27]	MAIN[12][29][27]	MAIN[22][29][27]	MAIN[32][29][27]
CLK_COR_SEQ_2_3 bit 8	MAIN[2][28][28]	MAIN[12][28][28]	MAIN[22][28][28]	MAIN[32][28][28]
CLK_COR_SEQ_2_3 bit 9	MAIN[2][29][28]	MAIN[12][29][28]	MAIN[22][29][28]	MAIN[32][29][28]
CLK_COR_SEQ_2_4 bit 0	MAIN[2][28][32]	MAIN[12][28][32]	MAIN[22][28][32]	MAIN[32][28][32]
CLK_COR_SEQ_2_4 bit 1	MAIN[2][29][32]	MAIN[12][29][32]	MAIN[22][29][32]	MAIN[32][29][32]
CLK_COR_SEQ_2_4 bit 2	MAIN[2][28][33]	MAIN[12][28][33]	MAIN[22][28][33]	MAIN[32][28][33]
CLK_COR_SEQ_2_4 bit 3	MAIN[2][29][33]	MAIN[12][29][33]	MAIN[22][29][33]	MAIN[32][29][33]
CLK_COR_SEQ_2_4 bit 4	MAIN[2][28][34]	MAIN[12][28][34]	MAIN[22][28][34]	MAIN[32][28][34]
CLK_COR_SEQ_2_4 bit 5	MAIN[2][29][34]	MAIN[12][29][34]	MAIN[22][29][34]	MAIN[32][29][34]
CLK_COR_SEQ_2_4 bit 6	MAIN[2][28][35]	MAIN[12][28][35]	MAIN[22][28][35]	MAIN[32][28][35]
CLK_COR_SEQ_2_4 bit 7	MAIN[2][29][35]	MAIN[12][29][35]	MAIN[22][29][35]	MAIN[32][29][35]
CLK_COR_SEQ_2_4 bit 8	MAIN[2][28][36]	MAIN[12][28][36]	MAIN[22][28][36]	MAIN[32][28][36]
CLK_COR_SEQ_2_4 bit 9	MAIN[2][29][36]	MAIN[12][29][36]	MAIN[22][29][36]	MAIN[32][29][36]
CLK_COR_SEQ_2_ENABLE bit 0	MAIN[2][28][13]	MAIN[12][28][13]	MAIN[22][28][13]	MAIN[32][28][13]
CLK_COR_SEQ_2_ENABLE bit 1	MAIN[2][29][13]	MAIN[12][29][13]	MAIN[22][29][13]	MAIN[32][29][13]
CLK_COR_SEQ_2_ENABLE bit 2	MAIN[2][28][14]	MAIN[12][28][14]	MAIN[22][28][14]	MAIN[32][28][14]
CLK_COR_SEQ_2_ENABLE bit 3	MAIN[2][29][14]	MAIN[12][29][14]	MAIN[22][29][14]	MAIN[32][29][14]
CM_TRIM bit 0	MAIN[4][28][44]	MAIN[14][28][44]	MAIN[24][28][44]	MAIN[34][28][44]
CM_TRIM bit 1	MAIN[4][29][44]	MAIN[14][29][44]	MAIN[24][29][44]	MAIN[34][29][44]
COMMA_10B_ENABLE bit 0	MAIN[5][28][56]	MAIN[15][28][56]	MAIN[25][28][56]	MAIN[35][28][56]
COMMA_10B_ENABLE bit 1	MAIN[5][29][56]	MAIN[15][29][56]	MAIN[25][29][56]	MAIN[35][29][56]
COMMA_10B_ENABLE bit 2	MAIN[5][28][57]	MAIN[15][28][57]	MAIN[25][28][57]	MAIN[35][28][57]
COMMA_10B_ENABLE bit 3	MAIN[5][29][57]	MAIN[15][29][57]	MAIN[25][29][57]	MAIN[35][29][57]
COMMA_10B_ENABLE bit 4	MAIN[5][28][58]	MAIN[15][28][58]	MAIN[25][28][58]	MAIN[35][28][58]
COMMA_10B_ENABLE bit 5	MAIN[5][29][58]	MAIN[15][29][58]	MAIN[25][29][58]	MAIN[35][29][58]
COMMA_10B_ENABLE bit 6	MAIN[5][28][59]	MAIN[15][28][59]	MAIN[25][28][59]	MAIN[35][28][59]
COMMA_10B_ENABLE bit 7	MAIN[5][29][59]	MAIN[15][29][59]	MAIN[25][29][59]	MAIN[35][29][59]
COMMA_10B_ENABLE bit 8	MAIN[5][28][60]	MAIN[15][28][60]	MAIN[25][28][60]	MAIN[35][28][60]
COMMA_10B_ENABLE bit 9	MAIN[5][29][60]	MAIN[15][29][60]	MAIN[25][29][60]	MAIN[35][29][60]
COM_BURST_VAL bit 0	MAIN[4][28][38]	MAIN[14][28][38]	MAIN[24][28][38]	MAIN[34][28][38]
COM_BURST_VAL bit 1	MAIN[4][29][38]	MAIN[14][29][38]	MAIN[24][29][38]	MAIN[34][29][38]
COM_BURST_VAL bit 2	MAIN[4][28][39]	MAIN[14][28][39]	MAIN[24][28][39]	MAIN[34][28][39]
COM_BURST_VAL bit 3	MAIN[4][29][39]	MAIN[14][29][39]	MAIN[24][29][39]	MAIN[34][29][39]
DFE_CAL_TIME bit 0	MAIN[5][29][53]	MAIN[15][29][53]	MAIN[25][29][53]	MAIN[35][29][53]
DFE_CAL_TIME bit 1	MAIN[5][28][54]	MAIN[15][28][54]	MAIN[25][28][54]	MAIN[35][28][54]
DFE_CAL_TIME bit 2	MAIN[5][29][54]	MAIN[15][29][54]	MAIN[25][29][54]	MAIN[35][29][54]
DFE_CAL_TIME bit 3	MAIN[5][28][55]	MAIN[15][28][55]	MAIN[25][28][55]	MAIN[35][28][55]
DFE_CAL_TIME bit 4	MAIN[5][29][55]	MAIN[15][29][55]	MAIN[25][29][55]	MAIN[35][29][55]
DFE_CFG bit 0	MAIN[5][28][40]	MAIN[15][28][40]	MAIN[25][28][40]	MAIN[35][28][40]
DFE_CFG bit 1	MAIN[5][29][40]	MAIN[15][29][40]	MAIN[25][29][40]	MAIN[35][29][40]
DFE_CFG bit 2	MAIN[5][28][41]	MAIN[15][28][41]	MAIN[25][28][41]	MAIN[35][28][41]
DFE_CFG bit 3	MAIN[5][29][41]	MAIN[15][29][41]	MAIN[25][29][41]	MAIN[35][29][41]
DFE_CFG bit 4	MAIN[5][28][42]	MAIN[15][28][42]	MAIN[25][28][42]	MAIN[35][28][42]
DFE_CFG bit 5	MAIN[5][29][42]	MAIN[15][29][42]	MAIN[25][29][42]	MAIN[35][29][42]
DFE_CFG bit 6	MAIN[5][28][43]	MAIN[15][28][43]	MAIN[25][28][43]	MAIN[35][28][43]
DFE_CFG bit 7	MAIN[5][29][43]	MAIN[15][29][43]	MAIN[25][29][43]	MAIN[35][29][43]
GEARBOX_ENDEC bit 0	MAIN[3][28][0]	MAIN[13][28][0]	MAIN[23][28][0]	MAIN[33][28][0]
GEARBOX_ENDEC bit 1	MAIN[3][29][0]	MAIN[13][29][0]	MAIN[23][29][0]	MAIN[33][29][0]
GEARBOX_ENDEC bit 2	MAIN[3][28][1]	MAIN[13][28][1]	MAIN[23][28][1]	MAIN[33][28][1]
MCOMMA_10B_VALUE bit 0	MAIN[6][28][0]	MAIN[16][28][0]	MAIN[26][28][0]	MAIN[36][28][0]
MCOMMA_10B_VALUE bit 1	MAIN[6][29][0]	MAIN[16][29][0]	MAIN[26][29][0]	MAIN[36][29][0]
MCOMMA_10B_VALUE bit 2	MAIN[6][28][1]	MAIN[16][28][1]	MAIN[26][28][1]	MAIN[36][28][1]
MCOMMA_10B_VALUE bit 3	MAIN[6][29][1]	MAIN[16][29][1]	MAIN[26][29][1]	MAIN[36][29][1]
MCOMMA_10B_VALUE bit 4	MAIN[6][28][2]	MAIN[16][28][2]	MAIN[26][28][2]	MAIN[36][28][2]
MCOMMA_10B_VALUE bit 5	MAIN[6][29][2]	MAIN[16][29][2]	MAIN[26][29][2]	MAIN[36][29][2]
MCOMMA_10B_VALUE bit 6	MAIN[6][28][3]	MAIN[16][28][3]	MAIN[26][28][3]	MAIN[36][28][3]
MCOMMA_10B_VALUE bit 7	MAIN[6][29][3]	MAIN[16][29][3]	MAIN[26][29][3]	MAIN[36][29][3]
MCOMMA_10B_VALUE bit 8	MAIN[6][28][4]	MAIN[16][28][4]	MAIN[26][28][4]	MAIN[36][28][4]
MCOMMA_10B_VALUE bit 9	MAIN[6][29][4]	MAIN[16][29][4]	MAIN[26][29][4]	MAIN[36][29][4]
OOBDETECT_THRESHOLD bit 0	MAIN[2][28][56]	MAIN[12][28][56]	MAIN[22][28][56]	MAIN[32][28][56]
OOBDETECT_THRESHOLD bit 1	MAIN[2][29][56]	MAIN[12][29][56]	MAIN[22][29][56]	MAIN[32][29][56]
OOBDETECT_THRESHOLD bit 2	MAIN[2][28][57]	MAIN[12][28][57]	MAIN[22][28][57]	MAIN[32][28][57]
PCOMMA_10B_VALUE bit 0	MAIN[6][28][8]	MAIN[16][28][8]	MAIN[26][28][8]	MAIN[36][28][8]
PCOMMA_10B_VALUE bit 1	MAIN[6][29][8]	MAIN[16][29][8]	MAIN[26][29][8]	MAIN[36][29][8]
PCOMMA_10B_VALUE bit 2	MAIN[6][28][9]	MAIN[16][28][9]	MAIN[26][28][9]	MAIN[36][28][9]
PCOMMA_10B_VALUE bit 3	MAIN[6][29][9]	MAIN[16][29][9]	MAIN[26][29][9]	MAIN[36][29][9]
PCOMMA_10B_VALUE bit 4	MAIN[6][28][10]	MAIN[16][28][10]	MAIN[26][28][10]	MAIN[36][28][10]
PCOMMA_10B_VALUE bit 5	MAIN[6][29][10]	MAIN[16][29][10]	MAIN[26][29][10]	MAIN[36][29][10]
PCOMMA_10B_VALUE bit 6	MAIN[6][28][11]	MAIN[16][28][11]	MAIN[26][28][11]	MAIN[36][28][11]
PCOMMA_10B_VALUE bit 7	MAIN[6][29][11]	MAIN[16][29][11]	MAIN[26][29][11]	MAIN[36][29][11]
PCOMMA_10B_VALUE bit 8	MAIN[6][28][12]	MAIN[16][28][12]	MAIN[26][28][12]	MAIN[36][28][12]
PCOMMA_10B_VALUE bit 9	MAIN[6][29][12]	MAIN[16][29][12]	MAIN[26][29][12]	MAIN[36][29][12]
POWER_SAVE bit 0	MAIN[8][28][32]	MAIN[18][28][32]	MAIN[28][28][32]	MAIN[38][28][32]
POWER_SAVE bit 1	MAIN[8][29][32]	MAIN[18][29][32]	MAIN[28][29][32]	MAIN[38][29][32]
POWER_SAVE bit 2	MAIN[8][28][33]	MAIN[18][28][33]	MAIN[28][28][33]	MAIN[38][28][33]
POWER_SAVE bit 3	MAIN[8][29][33]	MAIN[18][29][33]	MAIN[28][29][33]	MAIN[38][29][33]
POWER_SAVE bit 4	MAIN[8][28][34]	MAIN[18][28][34]	MAIN[28][28][34]	MAIN[38][28][34]
POWER_SAVE bit 5	MAIN[8][29][34]	MAIN[18][29][34]	MAIN[28][29][34]	MAIN[38][29][34]
POWER_SAVE bit 6	MAIN[8][28][35]	MAIN[18][28][35]	MAIN[28][28][35]	MAIN[38][28][35]
POWER_SAVE bit 7	MAIN[8][29][35]	MAIN[18][29][35]	MAIN[28][29][35]	MAIN[38][29][35]
POWER_SAVE bit 8	MAIN[8][28][36]	MAIN[18][28][36]	MAIN[28][28][36]	MAIN[38][28][36]
POWER_SAVE bit 9	MAIN[8][29][36]	MAIN[18][29][36]	MAIN[28][29][36]	MAIN[38][29][36]
RXPLL_LKDET_CFG bit 0	MAIN[3][29][29]	MAIN[13][29][29]	MAIN[23][29][29]	MAIN[33][29][29]
RXPLL_LKDET_CFG bit 1	MAIN[3][28][30]	MAIN[13][28][30]	MAIN[23][28][30]	MAIN[33][28][30]
RXPLL_LKDET_CFG bit 2	MAIN[3][29][30]	MAIN[13][29][30]	MAIN[23][29][30]	MAIN[33][29][30]
RXPRBSERR_LOOPBACK bit 0	MAIN[5][28][20]	MAIN[15][28][20]	MAIN[25][28][20]	MAIN[35][28][20]
RXRECCLK_DLY bit 0	MAIN[8][28][48]	MAIN[18][28][48]	MAIN[28][28][48]	MAIN[38][28][48]
RXRECCLK_DLY bit 1	MAIN[8][29][48]	MAIN[18][29][48]	MAIN[28][29][48]	MAIN[38][29][48]
RXRECCLK_DLY bit 2	MAIN[8][28][49]	MAIN[18][28][49]	MAIN[28][28][49]	MAIN[38][28][49]
RXRECCLK_DLY bit 3	MAIN[8][29][49]	MAIN[18][29][49]	MAIN[28][29][49]	MAIN[38][29][49]
RXRECCLK_DLY bit 4	MAIN[8][28][50]	MAIN[18][28][50]	MAIN[28][28][50]	MAIN[38][28][50]
RXRECCLK_DLY bit 5	MAIN[8][29][50]	MAIN[18][29][50]	MAIN[28][29][50]	MAIN[38][29][50]
RXRECCLK_DLY bit 6	MAIN[8][28][51]	MAIN[18][28][51]	MAIN[28][28][51]	MAIN[38][28][51]
RXRECCLK_DLY bit 7	MAIN[8][29][51]	MAIN[18][29][51]	MAIN[28][29][51]	MAIN[38][29][51]
RXRECCLK_DLY bit 8	MAIN[8][28][52]	MAIN[18][28][52]	MAIN[28][28][52]	MAIN[38][28][52]
RXRECCLK_DLY bit 9	MAIN[8][29][52]	MAIN[18][29][52]	MAIN[28][29][52]	MAIN[38][29][52]
RX_DLYALIGN_CTRINC bit 0	MAIN[9][28][40]	MAIN[19][28][40]	MAIN[29][28][40]	MAIN[39][28][40]
RX_DLYALIGN_CTRINC bit 1	MAIN[9][29][40]	MAIN[19][29][40]	MAIN[29][29][40]	MAIN[39][29][40]
RX_DLYALIGN_CTRINC bit 2	MAIN[9][28][41]	MAIN[19][28][41]	MAIN[29][28][41]	MAIN[39][28][41]
RX_DLYALIGN_CTRINC bit 3	MAIN[9][29][41]	MAIN[19][29][41]	MAIN[29][29][41]	MAIN[39][29][41]
RX_DLYALIGN_EDGESET bit 0	MAIN[9][28][27]	MAIN[19][28][27]	MAIN[29][28][27]	MAIN[39][28][27]
RX_DLYALIGN_EDGESET bit 1	MAIN[9][29][27]	MAIN[19][29][27]	MAIN[29][29][27]	MAIN[39][29][27]
RX_DLYALIGN_EDGESET bit 2	MAIN[9][28][28]	MAIN[19][28][28]	MAIN[29][28][28]	MAIN[39][28][28]
RX_DLYALIGN_EDGESET bit 3	MAIN[9][29][28]	MAIN[19][29][28]	MAIN[29][29][28]	MAIN[39][29][28]
RX_DLYALIGN_EDGESET bit 4	MAIN[9][28][29]	MAIN[19][28][29]	MAIN[29][28][29]	MAIN[39][28][29]
RX_DLYALIGN_LPFINC bit 0	MAIN[9][28][42]	MAIN[19][28][42]	MAIN[29][28][42]	MAIN[39][28][42]
RX_DLYALIGN_LPFINC bit 1	MAIN[9][29][42]	MAIN[19][29][42]	MAIN[29][29][42]	MAIN[39][29][42]
RX_DLYALIGN_LPFINC bit 2	MAIN[9][28][43]	MAIN[19][28][43]	MAIN[29][28][43]	MAIN[39][28][43]
RX_DLYALIGN_LPFINC bit 3	MAIN[9][29][43]	MAIN[19][29][43]	MAIN[29][29][43]	MAIN[39][29][43]
RX_DLYALIGN_MONSEL bit 0	MAIN[9][28][24]	MAIN[19][28][24]	MAIN[29][28][24]	MAIN[39][28][24]
RX_DLYALIGN_MONSEL bit 1	MAIN[9][29][24]	MAIN[19][29][24]	MAIN[29][29][24]	MAIN[39][29][24]
RX_DLYALIGN_MONSEL bit 2	MAIN[9][28][25]	MAIN[19][28][25]	MAIN[29][28][25]	MAIN[39][28][25]
RX_DLYALIGN_OVRDSETTING bit 0	MAIN[9][28][44]	MAIN[19][28][44]	MAIN[29][28][44]	MAIN[39][28][44]
RX_DLYALIGN_OVRDSETTING bit 1	MAIN[9][29][44]	MAIN[19][29][44]	MAIN[29][29][44]	MAIN[39][29][44]
RX_DLYALIGN_OVRDSETTING bit 2	MAIN[9][28][45]	MAIN[19][28][45]	MAIN[29][28][45]	MAIN[39][28][45]
RX_DLYALIGN_OVRDSETTING bit 3	MAIN[9][29][45]	MAIN[19][29][45]	MAIN[29][29][45]	MAIN[39][29][45]
RX_DLYALIGN_OVRDSETTING bit 4	MAIN[9][28][46]	MAIN[19][28][46]	MAIN[29][28][46]	MAIN[39][28][46]
RX_DLYALIGN_OVRDSETTING bit 5	MAIN[9][29][46]	MAIN[19][29][46]	MAIN[29][29][46]	MAIN[39][29][46]
RX_DLYALIGN_OVRDSETTING bit 6	MAIN[9][28][47]	MAIN[19][28][47]	MAIN[29][28][47]	MAIN[39][28][47]
RX_DLYALIGN_OVRDSETTING bit 7	MAIN[9][29][47]	MAIN[19][29][47]	MAIN[29][29][47]	MAIN[39][29][47]
RX_EYE_SCANMODE bit 0	MAIN[5][29][52]	MAIN[15][29][52]	MAIN[25][29][52]	MAIN[35][29][52]
RX_EYE_SCANMODE bit 1	MAIN[5][28][53]	MAIN[15][28][53]	MAIN[25][28][53]	MAIN[35][28][53]
RX_IDLE_HI_CNT bit 0	MAIN[1][28][30]	MAIN[11][28][30]	MAIN[21][28][30]	MAIN[31][28][30]
RX_IDLE_HI_CNT bit 1	MAIN[1][29][30]	MAIN[11][29][30]	MAIN[21][29][30]	MAIN[31][29][30]
RX_IDLE_HI_CNT bit 2	MAIN[1][28][31]	MAIN[11][28][31]	MAIN[21][28][31]	MAIN[31][28][31]
RX_IDLE_HI_CNT bit 3	MAIN[1][29][31]	MAIN[11][29][31]	MAIN[21][29][31]	MAIN[31][29][31]
RX_IDLE_LO_CNT bit 0	MAIN[0][28][62]	MAIN[10][28][62]	MAIN[20][28][62]	MAIN[30][28][62]
RX_IDLE_LO_CNT bit 1	MAIN[0][29][62]	MAIN[10][29][62]	MAIN[20][29][62]	MAIN[30][29][62]
RX_IDLE_LO_CNT bit 2	MAIN[0][28][63]	MAIN[10][28][63]	MAIN[20][28][63]	MAIN[30][28][63]
RX_IDLE_LO_CNT bit 3	MAIN[0][29][63]	MAIN[10][29][63]	MAIN[20][29][63]	MAIN[30][29][63]
SATA_BURST_VAL bit 0	MAIN[5][28][6]	MAIN[15][28][6]	MAIN[25][28][6]	MAIN[35][28][6]
SATA_BURST_VAL bit 1	MAIN[5][29][6]	MAIN[15][29][6]	MAIN[25][29][6]	MAIN[35][29][6]
SATA_BURST_VAL bit 2	MAIN[5][28][7]	MAIN[15][28][7]	MAIN[25][28][7]	MAIN[35][28][7]
SATA_IDLE_VAL bit 0	MAIN[4][28][62]	MAIN[14][28][62]	MAIN[24][28][62]	MAIN[34][28][62]
SATA_IDLE_VAL bit 1	MAIN[4][29][62]	MAIN[14][29][62]	MAIN[24][29][62]	MAIN[34][29][62]
SATA_IDLE_VAL bit 2	MAIN[4][28][63]	MAIN[14][28][63]	MAIN[24][28][63]	MAIN[34][28][63]
TERMINATION_CTRL bit 0	MAIN[5][28][48]	MAIN[15][28][48]	MAIN[25][28][48]	MAIN[35][28][48]
TERMINATION_CTRL bit 1	MAIN[5][29][48]	MAIN[15][29][48]	MAIN[25][29][48]	MAIN[35][29][48]
TERMINATION_CTRL bit 2	MAIN[5][28][49]	MAIN[15][28][49]	MAIN[25][28][49]	MAIN[35][28][49]
TERMINATION_CTRL bit 3	MAIN[5][29][49]	MAIN[15][29][49]	MAIN[25][29][49]	MAIN[35][29][49]
TERMINATION_CTRL bit 4	MAIN[5][28][50]	MAIN[15][28][50]	MAIN[25][28][50]	MAIN[35][28][50]
TXOUTCLK_DLY bit 0	MAIN[8][28][56]	MAIN[18][28][56]	MAIN[28][28][56]	MAIN[38][28][56]
TXOUTCLK_DLY bit 1	MAIN[8][29][56]	MAIN[18][29][56]	MAIN[28][29][56]	MAIN[38][29][56]
TXOUTCLK_DLY bit 2	MAIN[8][28][57]	MAIN[18][28][57]	MAIN[28][28][57]	MAIN[38][28][57]
TXOUTCLK_DLY bit 3	MAIN[8][29][57]	MAIN[18][29][57]	MAIN[28][29][57]	MAIN[38][29][57]
TXOUTCLK_DLY bit 4	MAIN[8][28][58]	MAIN[18][28][58]	MAIN[28][28][58]	MAIN[38][28][58]
TXOUTCLK_DLY bit 5	MAIN[8][29][58]	MAIN[18][29][58]	MAIN[28][29][58]	MAIN[38][29][58]
TXOUTCLK_DLY bit 6	MAIN[8][28][59]	MAIN[18][28][59]	MAIN[28][28][59]	MAIN[38][28][59]
TXOUTCLK_DLY bit 7	MAIN[8][29][59]	MAIN[18][29][59]	MAIN[28][29][59]	MAIN[38][29][59]
TXOUTCLK_DLY bit 8	MAIN[8][28][60]	MAIN[18][28][60]	MAIN[28][28][60]	MAIN[38][28][60]
TXOUTCLK_DLY bit 9	MAIN[8][29][60]	MAIN[18][29][60]	MAIN[28][29][60]	MAIN[38][29][60]
TXPLL_LKDET_CFG bit 0	MAIN[3][29][61]	MAIN[13][29][61]	MAIN[23][29][61]	MAIN[33][29][61]
TXPLL_LKDET_CFG bit 1	MAIN[3][28][62]	MAIN[13][28][62]	MAIN[23][28][62]	MAIN[33][28][62]
TXPLL_LKDET_CFG bit 2	MAIN[3][29][62]	MAIN[13][29][62]	MAIN[23][29][62]	MAIN[33][29][62]
TXPLL_SATA bit 0	MAIN[4][28][54]	MAIN[14][28][54]	MAIN[24][28][54]	MAIN[34][28][54]
TXPLL_SATA bit 1	MAIN[4][29][54]	MAIN[14][29][54]	MAIN[24][29][54]	MAIN[34][29][54]
TX_DEEMPH_0 bit 0	MAIN[7][28][48]	MAIN[17][28][48]	MAIN[27][28][48]	MAIN[37][28][48]
TX_DEEMPH_0 bit 1	MAIN[7][29][48]	MAIN[17][29][48]	MAIN[27][29][48]	MAIN[37][29][48]
TX_DEEMPH_0 bit 2	MAIN[7][28][49]	MAIN[17][28][49]	MAIN[27][28][49]	MAIN[37][28][49]
TX_DEEMPH_0 bit 3	MAIN[7][29][49]	MAIN[17][29][49]	MAIN[27][29][49]	MAIN[37][29][49]
TX_DEEMPH_0 bit 4	MAIN[7][28][50]	MAIN[17][28][50]	MAIN[27][28][50]	MAIN[37][28][50]
TX_DEEMPH_1 bit 0	MAIN[7][29][50]	MAIN[17][29][50]	MAIN[27][29][50]	MAIN[37][29][50]
TX_DEEMPH_1 bit 1	MAIN[7][28][51]	MAIN[17][28][51]	MAIN[27][28][51]	MAIN[37][28][51]
TX_DEEMPH_1 bit 2	MAIN[7][29][51]	MAIN[17][29][51]	MAIN[27][29][51]	MAIN[37][29][51]
TX_DEEMPH_1 bit 3	MAIN[7][28][52]	MAIN[17][28][52]	MAIN[27][28][52]	MAIN[37][28][52]
TX_DEEMPH_1 bit 4	MAIN[7][29][52]	MAIN[17][29][52]	MAIN[27][29][52]	MAIN[37][29][52]
TX_DLYALIGN_CTRINC bit 0	MAIN[9][28][32]	MAIN[19][28][32]	MAIN[29][28][32]	MAIN[39][28][32]
TX_DLYALIGN_CTRINC bit 1	MAIN[9][29][32]	MAIN[19][29][32]	MAIN[29][29][32]	MAIN[39][29][32]
TX_DLYALIGN_CTRINC bit 2	MAIN[9][28][33]	MAIN[19][28][33]	MAIN[29][28][33]	MAIN[39][28][33]
TX_DLYALIGN_CTRINC bit 3	MAIN[9][29][33]	MAIN[19][29][33]	MAIN[29][29][33]	MAIN[39][29][33]
TX_DLYALIGN_LPFINC bit 0	MAIN[9][28][34]	MAIN[19][28][34]	MAIN[29][28][34]	MAIN[39][28][34]
TX_DLYALIGN_LPFINC bit 1	MAIN[9][29][34]	MAIN[19][29][34]	MAIN[29][29][34]	MAIN[39][29][34]
TX_DLYALIGN_LPFINC bit 2	MAIN[9][28][35]	MAIN[19][28][35]	MAIN[29][28][35]	MAIN[39][28][35]
TX_DLYALIGN_LPFINC bit 3	MAIN[9][29][35]	MAIN[19][29][35]	MAIN[29][29][35]	MAIN[39][29][35]
TX_DLYALIGN_MONSEL bit 0	MAIN[9][29][25]	MAIN[19][29][25]	MAIN[29][29][25]	MAIN[39][29][25]
TX_DLYALIGN_MONSEL bit 1	MAIN[9][28][26]	MAIN[19][28][26]	MAIN[29][28][26]	MAIN[39][28][26]
TX_DLYALIGN_MONSEL bit 2	MAIN[9][29][26]	MAIN[19][29][26]	MAIN[29][29][26]	MAIN[39][29][26]
TX_DLYALIGN_OVRDSETTING bit 0	MAIN[9][28][36]	MAIN[19][28][36]	MAIN[29][28][36]	MAIN[39][28][36]
TX_DLYALIGN_OVRDSETTING bit 1	MAIN[9][29][36]	MAIN[19][29][36]	MAIN[29][29][36]	MAIN[39][29][36]
TX_DLYALIGN_OVRDSETTING bit 2	MAIN[9][28][37]	MAIN[19][28][37]	MAIN[29][28][37]	MAIN[39][28][37]
TX_DLYALIGN_OVRDSETTING bit 3	MAIN[9][29][37]	MAIN[19][29][37]	MAIN[29][29][37]	MAIN[39][29][37]
TX_DLYALIGN_OVRDSETTING bit 4	MAIN[9][28][38]	MAIN[19][28][38]	MAIN[29][28][38]	MAIN[39][28][38]
TX_DLYALIGN_OVRDSETTING bit 5	MAIN[9][29][38]	MAIN[19][29][38]	MAIN[29][29][38]	MAIN[39][29][38]
TX_DLYALIGN_OVRDSETTING bit 6	MAIN[9][28][39]	MAIN[19][28][39]	MAIN[29][28][39]	MAIN[39][28][39]
TX_DLYALIGN_OVRDSETTING bit 7	MAIN[9][29][39]	MAIN[19][29][39]	MAIN[29][29][39]	MAIN[39][29][39]
TX_IDLE_ASSERT_DELAY bit 0	MAIN[5][29][61]	MAIN[15][29][61]	MAIN[25][29][61]	MAIN[35][29][61]
TX_IDLE_ASSERT_DELAY bit 1	MAIN[5][28][62]	MAIN[15][28][62]	MAIN[25][28][62]	MAIN[35][28][62]
TX_IDLE_ASSERT_DELAY bit 2	MAIN[5][29][62]	MAIN[15][29][62]	MAIN[25][29][62]	MAIN[35][29][62]
TX_IDLE_DEASSERT_DELAY bit 0	MAIN[6][29][5]	MAIN[16][29][5]	MAIN[26][29][5]	MAIN[36][29][5]
TX_IDLE_DEASSERT_DELAY bit 1	MAIN[6][28][6]	MAIN[16][28][6]	MAIN[26][28][6]	MAIN[36][28][6]
TX_IDLE_DEASSERT_DELAY bit 2	MAIN[6][29][6]	MAIN[16][29][6]	MAIN[26][29][6]	MAIN[36][29][6]
TX_MARGIN_FULL_0 bit 0	MAIN[7][29][3]	MAIN[17][29][3]	MAIN[27][29][3]	MAIN[37][29][3]
TX_MARGIN_FULL_0 bit 1	MAIN[7][28][4]	MAIN[17][28][4]	MAIN[27][28][4]	MAIN[37][28][4]
TX_MARGIN_FULL_0 bit 2	MAIN[7][29][4]	MAIN[17][29][4]	MAIN[27][29][4]	MAIN[37][29][4]
TX_MARGIN_FULL_0 bit 3	MAIN[7][28][5]	MAIN[17][28][5]	MAIN[27][28][5]	MAIN[37][28][5]
TX_MARGIN_FULL_0 bit 4	MAIN[7][29][5]	MAIN[17][29][5]	MAIN[27][29][5]	MAIN[37][29][5]
TX_MARGIN_FULL_0 bit 5	MAIN[7][28][6]	MAIN[17][28][6]	MAIN[27][28][6]	MAIN[37][28][6]
TX_MARGIN_FULL_0 bit 6	MAIN[7][29][6]	MAIN[17][29][6]	MAIN[27][29][6]	MAIN[37][29][6]
TX_MARGIN_FULL_1 bit 0	MAIN[7][29][11]	MAIN[17][29][11]	MAIN[27][29][11]	MAIN[37][29][11]
TX_MARGIN_FULL_1 bit 1	MAIN[7][28][12]	MAIN[17][28][12]	MAIN[27][28][12]	MAIN[37][28][12]
TX_MARGIN_FULL_1 bit 2	MAIN[7][29][12]	MAIN[17][29][12]	MAIN[27][29][12]	MAIN[37][29][12]
TX_MARGIN_FULL_1 bit 3	MAIN[7][28][13]	MAIN[17][28][13]	MAIN[27][28][13]	MAIN[37][28][13]
TX_MARGIN_FULL_1 bit 4	MAIN[7][29][13]	MAIN[17][29][13]	MAIN[27][29][13]	MAIN[37][29][13]
TX_MARGIN_FULL_1 bit 5	MAIN[7][28][14]	MAIN[17][28][14]	MAIN[27][28][14]	MAIN[37][28][14]
TX_MARGIN_FULL_1 bit 6	MAIN[7][29][14]	MAIN[17][29][14]	MAIN[27][29][14]	MAIN[37][29][14]
TX_MARGIN_FULL_2 bit 0	MAIN[7][29][19]	MAIN[17][29][19]	MAIN[27][29][19]	MAIN[37][29][19]
TX_MARGIN_FULL_2 bit 1	MAIN[7][28][20]	MAIN[17][28][20]	MAIN[27][28][20]	MAIN[37][28][20]
TX_MARGIN_FULL_2 bit 2	MAIN[7][29][20]	MAIN[17][29][20]	MAIN[27][29][20]	MAIN[37][29][20]
TX_MARGIN_FULL_2 bit 3	MAIN[7][28][21]	MAIN[17][28][21]	MAIN[27][28][21]	MAIN[37][28][21]
TX_MARGIN_FULL_2 bit 4	MAIN[7][29][21]	MAIN[17][29][21]	MAIN[27][29][21]	MAIN[37][29][21]
TX_MARGIN_FULL_2 bit 5	MAIN[7][28][22]	MAIN[17][28][22]	MAIN[27][28][22]	MAIN[37][28][22]
TX_MARGIN_FULL_2 bit 6	MAIN[7][29][22]	MAIN[17][29][22]	MAIN[27][29][22]	MAIN[37][29][22]
TX_MARGIN_FULL_3 bit 0	MAIN[7][29][27]	MAIN[17][29][27]	MAIN[27][29][27]	MAIN[37][29][27]
TX_MARGIN_FULL_3 bit 1	MAIN[7][28][28]	MAIN[17][28][28]	MAIN[27][28][28]	MAIN[37][28][28]
TX_MARGIN_FULL_3 bit 2	MAIN[7][29][28]	MAIN[17][29][28]	MAIN[27][29][28]	MAIN[37][29][28]
TX_MARGIN_FULL_3 bit 3	MAIN[7][28][29]	MAIN[17][28][29]	MAIN[27][28][29]	MAIN[37][28][29]
TX_MARGIN_FULL_3 bit 4	MAIN[7][29][29]	MAIN[17][29][29]	MAIN[27][29][29]	MAIN[37][29][29]
TX_MARGIN_FULL_3 bit 5	MAIN[7][28][30]	MAIN[17][28][30]	MAIN[27][28][30]	MAIN[37][28][30]
TX_MARGIN_FULL_3 bit 6	MAIN[7][29][30]	MAIN[17][29][30]	MAIN[27][29][30]	MAIN[37][29][30]
TX_MARGIN_FULL_4 bit 0	MAIN[7][29][35]	MAIN[17][29][35]	MAIN[27][29][35]	MAIN[37][29][35]
TX_MARGIN_FULL_4 bit 1	MAIN[7][28][36]	MAIN[17][28][36]	MAIN[27][28][36]	MAIN[37][28][36]
TX_MARGIN_FULL_4 bit 2	MAIN[7][29][36]	MAIN[17][29][36]	MAIN[27][29][36]	MAIN[37][29][36]
TX_MARGIN_FULL_4 bit 3	MAIN[7][28][37]	MAIN[17][28][37]	MAIN[27][28][37]	MAIN[37][28][37]
TX_MARGIN_FULL_4 bit 4	MAIN[7][29][37]	MAIN[17][29][37]	MAIN[27][29][37]	MAIN[37][29][37]
TX_MARGIN_FULL_4 bit 5	MAIN[7][28][38]	MAIN[17][28][38]	MAIN[27][28][38]	MAIN[37][28][38]
TX_MARGIN_FULL_4 bit 6	MAIN[7][29][38]	MAIN[17][29][38]	MAIN[27][29][38]	MAIN[37][29][38]
TX_MARGIN_LOW_0 bit 0	MAIN[7][28][0]	MAIN[17][28][0]	MAIN[27][28][0]	MAIN[37][28][0]
TX_MARGIN_LOW_0 bit 1	MAIN[7][29][0]	MAIN[17][29][0]	MAIN[27][29][0]	MAIN[37][29][0]
TX_MARGIN_LOW_0 bit 2	MAIN[7][28][1]	MAIN[17][28][1]	MAIN[27][28][1]	MAIN[37][28][1]
TX_MARGIN_LOW_0 bit 3	MAIN[7][29][1]	MAIN[17][29][1]	MAIN[27][29][1]	MAIN[37][29][1]
TX_MARGIN_LOW_0 bit 4	MAIN[7][28][2]	MAIN[17][28][2]	MAIN[27][28][2]	MAIN[37][28][2]
TX_MARGIN_LOW_0 bit 5	MAIN[7][29][2]	MAIN[17][29][2]	MAIN[27][29][2]	MAIN[37][29][2]
TX_MARGIN_LOW_0 bit 6	MAIN[7][28][3]	MAIN[17][28][3]	MAIN[27][28][3]	MAIN[37][28][3]
TX_MARGIN_LOW_1 bit 0	MAIN[7][28][8]	MAIN[17][28][8]	MAIN[27][28][8]	MAIN[37][28][8]
TX_MARGIN_LOW_1 bit 1	MAIN[7][29][8]	MAIN[17][29][8]	MAIN[27][29][8]	MAIN[37][29][8]
TX_MARGIN_LOW_1 bit 2	MAIN[7][28][9]	MAIN[17][28][9]	MAIN[27][28][9]	MAIN[37][28][9]
TX_MARGIN_LOW_1 bit 3	MAIN[7][29][9]	MAIN[17][29][9]	MAIN[27][29][9]	MAIN[37][29][9]
TX_MARGIN_LOW_1 bit 4	MAIN[7][28][10]	MAIN[17][28][10]	MAIN[27][28][10]	MAIN[37][28][10]
TX_MARGIN_LOW_1 bit 5	MAIN[7][29][10]	MAIN[17][29][10]	MAIN[27][29][10]	MAIN[37][29][10]
TX_MARGIN_LOW_1 bit 6	MAIN[7][28][11]	MAIN[17][28][11]	MAIN[27][28][11]	MAIN[37][28][11]
TX_MARGIN_LOW_2 bit 0	MAIN[7][28][16]	MAIN[17][28][16]	MAIN[27][28][16]	MAIN[37][28][16]
TX_MARGIN_LOW_2 bit 1	MAIN[7][29][16]	MAIN[17][29][16]	MAIN[27][29][16]	MAIN[37][29][16]
TX_MARGIN_LOW_2 bit 2	MAIN[7][28][17]	MAIN[17][28][17]	MAIN[27][28][17]	MAIN[37][28][17]
TX_MARGIN_LOW_2 bit 3	MAIN[7][29][17]	MAIN[17][29][17]	MAIN[27][29][17]	MAIN[37][29][17]
TX_MARGIN_LOW_2 bit 4	MAIN[7][28][18]	MAIN[17][28][18]	MAIN[27][28][18]	MAIN[37][28][18]
TX_MARGIN_LOW_2 bit 5	MAIN[7][29][18]	MAIN[17][29][18]	MAIN[27][29][18]	MAIN[37][29][18]
TX_MARGIN_LOW_2 bit 6	MAIN[7][28][19]	MAIN[17][28][19]	MAIN[27][28][19]	MAIN[37][28][19]
TX_MARGIN_LOW_3 bit 0	MAIN[7][28][24]	MAIN[17][28][24]	MAIN[27][28][24]	MAIN[37][28][24]
TX_MARGIN_LOW_3 bit 1	MAIN[7][29][24]	MAIN[17][29][24]	MAIN[27][29][24]	MAIN[37][29][24]
TX_MARGIN_LOW_3 bit 2	MAIN[7][28][25]	MAIN[17][28][25]	MAIN[27][28][25]	MAIN[37][28][25]
TX_MARGIN_LOW_3 bit 3	MAIN[7][29][25]	MAIN[17][29][25]	MAIN[27][29][25]	MAIN[37][29][25]
TX_MARGIN_LOW_3 bit 4	MAIN[7][28][26]	MAIN[17][28][26]	MAIN[27][28][26]	MAIN[37][28][26]
TX_MARGIN_LOW_3 bit 5	MAIN[7][29][26]	MAIN[17][29][26]	MAIN[27][29][26]	MAIN[37][29][26]
TX_MARGIN_LOW_3 bit 6	MAIN[7][28][27]	MAIN[17][28][27]	MAIN[27][28][27]	MAIN[37][28][27]
TX_MARGIN_LOW_4 bit 0	MAIN[7][28][32]	MAIN[17][28][32]	MAIN[27][28][32]	MAIN[37][28][32]
TX_MARGIN_LOW_4 bit 1	MAIN[7][29][32]	MAIN[17][29][32]	MAIN[27][29][32]	MAIN[37][29][32]
TX_MARGIN_LOW_4 bit 2	MAIN[7][28][33]	MAIN[17][28][33]	MAIN[27][28][33]	MAIN[37][28][33]
TX_MARGIN_LOW_4 bit 3	MAIN[7][29][33]	MAIN[17][29][33]	MAIN[27][29][33]	MAIN[37][29][33]
TX_MARGIN_LOW_4 bit 4	MAIN[7][28][34]	MAIN[17][28][34]	MAIN[27][28][34]	MAIN[37][28][34]
TX_MARGIN_LOW_4 bit 5	MAIN[7][29][34]	MAIN[17][29][34]	MAIN[27][29][34]	MAIN[37][29][34]
TX_MARGIN_LOW_4 bit 6	MAIN[7][28][35]	MAIN[17][28][35]	MAIN[27][28][35]	MAIN[37][28][35]
TX_PMADATA_OPT bit 0	MAIN[4][29][47]	MAIN[14][29][47]	MAIN[24][29][47]	MAIN[34][29][47]
TX_TDCC_CFG bit 0	MAIN[7][28][15]	MAIN[17][28][15]	MAIN[27][28][15]	MAIN[37][28][15]
TX_TDCC_CFG bit 1	MAIN[7][29][15]	MAIN[17][29][15]	MAIN[27][29][15]	MAIN[37][29][15]
USR_CODE_ERR_CLR bit 0	MAIN[2][28][38]	MAIN[12][28][38]	MAIN[22][28][38]	MAIN[32][28][38]
BIAS_CFG bit 0	MAIN[0][28][24]	MAIN[10][28][24]	MAIN[20][28][24]	MAIN[30][28][24]
BIAS_CFG bit 1	MAIN[0][29][24]	MAIN[10][29][24]	MAIN[20][29][24]	MAIN[30][29][24]
BIAS_CFG bit 2	MAIN[0][28][25]	MAIN[10][28][25]	MAIN[20][28][25]	MAIN[30][28][25]
BIAS_CFG bit 3	MAIN[0][29][25]	MAIN[10][29][25]	MAIN[20][29][25]	MAIN[30][29][25]
BIAS_CFG bit 4	MAIN[0][28][26]	MAIN[10][28][26]	MAIN[20][28][26]	MAIN[30][28][26]
BIAS_CFG bit 5	MAIN[0][29][26]	MAIN[10][29][26]	MAIN[20][29][26]	MAIN[30][29][26]
BIAS_CFG bit 6	MAIN[0][28][27]	MAIN[10][28][27]	MAIN[20][28][27]	MAIN[30][28][27]
BIAS_CFG bit 7	MAIN[0][29][27]	MAIN[10][29][27]	MAIN[20][29][27]	MAIN[30][29][27]
BIAS_CFG bit 8	MAIN[0][28][28]	MAIN[10][28][28]	MAIN[20][28][28]	MAIN[30][28][28]
BIAS_CFG bit 9	MAIN[0][29][28]	MAIN[10][29][28]	MAIN[20][29][28]	MAIN[30][29][28]
BIAS_CFG bit 10	MAIN[0][28][29]	MAIN[10][28][29]	MAIN[20][28][29]	MAIN[30][28][29]
BIAS_CFG bit 11	MAIN[0][29][29]	MAIN[10][29][29]	MAIN[20][29][29]	MAIN[30][29][29]
BIAS_CFG bit 12	MAIN[0][28][30]	MAIN[10][28][30]	MAIN[20][28][30]	MAIN[30][28][30]
BIAS_CFG bit 13	MAIN[0][29][30]	MAIN[10][29][30]	MAIN[20][29][30]	MAIN[30][29][30]
BIAS_CFG bit 14	MAIN[0][28][31]	MAIN[10][28][31]	MAIN[20][28][31]	MAIN[30][28][31]
BIAS_CFG bit 15	MAIN[0][29][31]	MAIN[10][29][31]	MAIN[20][29][31]	MAIN[30][29][31]
BIAS_CFG bit 16	MAIN[2][28][61]	MAIN[12][28][61]	MAIN[22][28][61]	MAIN[32][28][61]
PMA_CDR_SCAN bit 0	MAIN[2][28][40]	MAIN[12][28][40]	MAIN[22][28][40]	MAIN[32][28][40]
PMA_CDR_SCAN bit 1	MAIN[2][29][40]	MAIN[12][29][40]	MAIN[22][29][40]	MAIN[32][29][40]
PMA_CDR_SCAN bit 2	MAIN[2][28][41]	MAIN[12][28][41]	MAIN[22][28][41]	MAIN[32][28][41]
PMA_CDR_SCAN bit 3	MAIN[2][29][41]	MAIN[12][29][41]	MAIN[22][29][41]	MAIN[32][29][41]
PMA_CDR_SCAN bit 4	MAIN[2][28][42]	MAIN[12][28][42]	MAIN[22][28][42]	MAIN[32][28][42]
PMA_CDR_SCAN bit 5	MAIN[2][29][42]	MAIN[12][29][42]	MAIN[22][29][42]	MAIN[32][29][42]
PMA_CDR_SCAN bit 6	MAIN[2][28][43]	MAIN[12][28][43]	MAIN[22][28][43]	MAIN[32][28][43]
PMA_CDR_SCAN bit 7	MAIN[2][29][43]	MAIN[12][29][43]	MAIN[22][29][43]	MAIN[32][29][43]
PMA_CDR_SCAN bit 8	MAIN[2][28][44]	MAIN[12][28][44]	MAIN[22][28][44]	MAIN[32][28][44]
PMA_CDR_SCAN bit 9	MAIN[2][29][44]	MAIN[12][29][44]	MAIN[22][29][44]	MAIN[32][29][44]
PMA_CDR_SCAN bit 10	MAIN[2][28][45]	MAIN[12][28][45]	MAIN[22][28][45]	MAIN[32][28][45]
PMA_CDR_SCAN bit 11	MAIN[2][29][45]	MAIN[12][29][45]	MAIN[22][29][45]	MAIN[32][29][45]
PMA_CDR_SCAN bit 12	MAIN[2][28][46]	MAIN[12][28][46]	MAIN[22][28][46]	MAIN[32][28][46]
PMA_CDR_SCAN bit 13	MAIN[2][29][46]	MAIN[12][29][46]	MAIN[22][29][46]	MAIN[32][29][46]
PMA_CDR_SCAN bit 14	MAIN[2][28][47]	MAIN[12][28][47]	MAIN[22][28][47]	MAIN[32][28][47]
PMA_CDR_SCAN bit 15	MAIN[2][29][47]	MAIN[12][29][47]	MAIN[22][29][47]	MAIN[32][29][47]
PMA_CDR_SCAN bit 16	MAIN[2][28][48]	MAIN[12][28][48]	MAIN[22][28][48]	MAIN[32][28][48]
PMA_CDR_SCAN bit 17	MAIN[2][29][48]	MAIN[12][29][48]	MAIN[22][29][48]	MAIN[32][29][48]
PMA_CDR_SCAN bit 18	MAIN[2][28][49]	MAIN[12][28][49]	MAIN[22][28][49]	MAIN[32][28][49]
PMA_CDR_SCAN bit 19	MAIN[2][29][49]	MAIN[12][29][49]	MAIN[22][29][49]	MAIN[32][29][49]
PMA_CDR_SCAN bit 20	MAIN[2][28][50]	MAIN[12][28][50]	MAIN[22][28][50]	MAIN[32][28][50]
PMA_CDR_SCAN bit 21	MAIN[2][29][50]	MAIN[12][29][50]	MAIN[22][29][50]	MAIN[32][29][50]
PMA_CDR_SCAN bit 22	MAIN[2][28][51]	MAIN[12][28][51]	MAIN[22][28][51]	MAIN[32][28][51]
PMA_CDR_SCAN bit 23	MAIN[2][29][51]	MAIN[12][29][51]	MAIN[22][29][51]	MAIN[32][29][51]
PMA_CDR_SCAN bit 24	MAIN[2][28][52]	MAIN[12][28][52]	MAIN[22][28][52]	MAIN[32][28][52]
PMA_CDR_SCAN bit 25	MAIN[2][29][52]	MAIN[12][29][52]	MAIN[22][29][52]	MAIN[32][29][52]
PMA_CDR_SCAN bit 26	MAIN[2][28][53]	MAIN[12][28][53]	MAIN[22][28][53]	MAIN[32][28][53]
PMA_CFG bit 0	MAIN[6][28][16]	MAIN[16][28][16]	MAIN[26][28][16]	MAIN[36][28][16]
PMA_CFG bit 1	MAIN[6][29][16]	MAIN[16][29][16]	MAIN[26][29][16]	MAIN[36][29][16]
PMA_CFG bit 2	MAIN[6][28][17]	MAIN[16][28][17]	MAIN[26][28][17]	MAIN[36][28][17]
PMA_CFG bit 3	MAIN[6][29][17]	MAIN[16][29][17]	MAIN[26][29][17]	MAIN[36][29][17]
PMA_CFG bit 4	MAIN[6][28][18]	MAIN[16][28][18]	MAIN[26][28][18]	MAIN[36][28][18]
PMA_CFG bit 5	MAIN[6][29][18]	MAIN[16][29][18]	MAIN[26][29][18]	MAIN[36][29][18]
PMA_CFG bit 6	MAIN[6][28][19]	MAIN[16][28][19]	MAIN[26][28][19]	MAIN[36][28][19]
PMA_CFG bit 7	MAIN[6][29][19]	MAIN[16][29][19]	MAIN[26][29][19]	MAIN[36][29][19]
PMA_CFG bit 8	MAIN[6][28][20]	MAIN[16][28][20]	MAIN[26][28][20]	MAIN[36][28][20]
PMA_CFG bit 9	MAIN[6][29][20]	MAIN[16][29][20]	MAIN[26][29][20]	MAIN[36][29][20]
PMA_CFG bit 10	MAIN[6][28][21]	MAIN[16][28][21]	MAIN[26][28][21]	MAIN[36][28][21]
PMA_CFG bit 11	MAIN[6][29][21]	MAIN[16][29][21]	MAIN[26][29][21]	MAIN[36][29][21]
PMA_CFG bit 12	MAIN[6][28][22]	MAIN[16][28][22]	MAIN[26][28][22]	MAIN[36][28][22]
PMA_CFG bit 13	MAIN[6][29][22]	MAIN[16][29][22]	MAIN[26][29][22]	MAIN[36][29][22]
PMA_CFG bit 14	MAIN[6][28][23]	MAIN[16][28][23]	MAIN[26][28][23]	MAIN[36][28][23]
PMA_CFG bit 15	MAIN[6][29][23]	MAIN[16][29][23]	MAIN[26][29][23]	MAIN[36][29][23]
PMA_CFG bit 16	MAIN[6][28][24]	MAIN[16][28][24]	MAIN[26][28][24]	MAIN[36][28][24]
PMA_CFG bit 17	MAIN[6][29][24]	MAIN[16][29][24]	MAIN[26][29][24]	MAIN[36][29][24]
PMA_CFG bit 18	MAIN[6][28][25]	MAIN[16][28][25]	MAIN[26][28][25]	MAIN[36][28][25]
PMA_CFG bit 19	MAIN[6][29][25]	MAIN[16][29][25]	MAIN[26][29][25]	MAIN[36][29][25]
PMA_CFG bit 20	MAIN[6][28][26]	MAIN[16][28][26]	MAIN[26][28][26]	MAIN[36][28][26]
PMA_CFG bit 21	MAIN[6][29][26]	MAIN[16][29][26]	MAIN[26][29][26]	MAIN[36][29][26]
PMA_CFG bit 22	MAIN[6][28][27]	MAIN[16][28][27]	MAIN[26][28][27]	MAIN[36][28][27]
PMA_CFG bit 23	MAIN[6][29][27]	MAIN[16][29][27]	MAIN[26][29][27]	MAIN[36][29][27]
PMA_CFG bit 24	MAIN[6][28][28]	MAIN[16][28][28]	MAIN[26][28][28]	MAIN[36][28][28]
PMA_CFG bit 25	MAIN[6][29][28]	MAIN[16][29][28]	MAIN[26][29][28]	MAIN[36][29][28]
PMA_CFG bit 26	MAIN[6][28][29]	MAIN[16][28][29]	MAIN[26][28][29]	MAIN[36][28][29]
PMA_CFG bit 27	MAIN[6][29][29]	MAIN[16][29][29]	MAIN[26][29][29]	MAIN[36][29][29]
PMA_CFG bit 28	MAIN[6][28][30]	MAIN[16][28][30]	MAIN[26][28][30]	MAIN[36][28][30]
PMA_CFG bit 29	MAIN[6][29][30]	MAIN[16][29][30]	MAIN[26][29][30]	MAIN[36][29][30]
PMA_CFG bit 30	MAIN[6][28][31]	MAIN[16][28][31]	MAIN[26][28][31]	MAIN[36][28][31]
PMA_CFG bit 31	MAIN[6][29][31]	MAIN[16][29][31]	MAIN[26][29][31]	MAIN[36][29][31]
PMA_CFG bit 32	MAIN[6][28][32]	MAIN[16][28][32]	MAIN[26][28][32]	MAIN[36][28][32]
PMA_CFG bit 33	MAIN[6][29][32]	MAIN[16][29][32]	MAIN[26][29][32]	MAIN[36][29][32]
PMA_CFG bit 34	MAIN[6][28][33]	MAIN[16][28][33]	MAIN[26][28][33]	MAIN[36][28][33]
PMA_CFG bit 35	MAIN[6][29][33]	MAIN[16][29][33]	MAIN[26][29][33]	MAIN[36][29][33]
PMA_CFG bit 36	MAIN[6][28][34]	MAIN[16][28][34]	MAIN[26][28][34]	MAIN[36][28][34]
PMA_CFG bit 37	MAIN[6][29][34]	MAIN[16][29][34]	MAIN[26][29][34]	MAIN[36][29][34]
PMA_CFG bit 38	MAIN[6][28][35]	MAIN[16][28][35]	MAIN[26][28][35]	MAIN[36][28][35]
PMA_CFG bit 39	MAIN[6][29][35]	MAIN[16][29][35]	MAIN[26][29][35]	MAIN[36][29][35]
PMA_CFG bit 40	MAIN[6][28][36]	MAIN[16][28][36]	MAIN[26][28][36]	MAIN[36][28][36]
PMA_CFG bit 41	MAIN[6][29][36]	MAIN[16][29][36]	MAIN[26][29][36]	MAIN[36][29][36]
PMA_CFG bit 42	MAIN[6][28][37]	MAIN[16][28][37]	MAIN[26][28][37]	MAIN[36][28][37]
PMA_CFG bit 43	MAIN[6][29][37]	MAIN[16][29][37]	MAIN[26][29][37]	MAIN[36][29][37]
PMA_CFG bit 44	MAIN[6][28][38]	MAIN[16][28][38]	MAIN[26][28][38]	MAIN[36][28][38]
PMA_CFG bit 45	MAIN[6][29][38]	MAIN[16][29][38]	MAIN[26][29][38]	MAIN[36][29][38]
PMA_CFG bit 46	MAIN[6][28][39]	MAIN[16][28][39]	MAIN[26][28][39]	MAIN[36][28][39]
PMA_CFG bit 47	MAIN[6][29][39]	MAIN[16][29][39]	MAIN[26][29][39]	MAIN[36][29][39]
PMA_CFG bit 48	MAIN[6][28][40]	MAIN[16][28][40]	MAIN[26][28][40]	MAIN[36][28][40]
PMA_CFG bit 49	MAIN[6][29][40]	MAIN[16][29][40]	MAIN[26][29][40]	MAIN[36][29][40]
PMA_CFG bit 50	MAIN[6][28][41]	MAIN[16][28][41]	MAIN[26][28][41]	MAIN[36][28][41]
PMA_CFG bit 51	MAIN[6][29][41]	MAIN[16][29][41]	MAIN[26][29][41]	MAIN[36][29][41]
PMA_CFG bit 52	MAIN[6][28][42]	MAIN[16][28][42]	MAIN[26][28][42]	MAIN[36][28][42]
PMA_CFG bit 53	MAIN[6][29][42]	MAIN[16][29][42]	MAIN[26][29][42]	MAIN[36][29][42]
PMA_CFG bit 54	MAIN[6][28][43]	MAIN[16][28][43]	MAIN[26][28][43]	MAIN[36][28][43]
PMA_CFG bit 55	MAIN[6][29][43]	MAIN[16][29][43]	MAIN[26][29][43]	MAIN[36][29][43]
PMA_CFG bit 56	MAIN[6][28][44]	MAIN[16][28][44]	MAIN[26][28][44]	MAIN[36][28][44]
PMA_CFG bit 57	MAIN[6][29][44]	MAIN[16][29][44]	MAIN[26][29][44]	MAIN[36][29][44]
PMA_CFG bit 58	MAIN[6][28][45]	MAIN[16][28][45]	MAIN[26][28][45]	MAIN[36][28][45]
PMA_CFG bit 59	MAIN[6][29][45]	MAIN[16][29][45]	MAIN[26][29][45]	MAIN[36][29][45]
PMA_CFG bit 60	MAIN[6][28][46]	MAIN[16][28][46]	MAIN[26][28][46]	MAIN[36][28][46]
PMA_CFG bit 61	MAIN[6][29][46]	MAIN[16][29][46]	MAIN[26][29][46]	MAIN[36][29][46]
PMA_CFG bit 62	MAIN[6][28][47]	MAIN[16][28][47]	MAIN[26][28][47]	MAIN[36][28][47]
PMA_CFG bit 63	MAIN[6][29][47]	MAIN[16][29][47]	MAIN[26][29][47]	MAIN[36][29][47]
PMA_CFG bit 64	MAIN[6][28][50]	MAIN[16][28][50]	MAIN[26][28][50]	MAIN[36][28][50]
PMA_CFG bit 65	MAIN[6][29][50]	MAIN[16][29][50]	MAIN[26][29][50]	MAIN[36][29][50]
PMA_CFG bit 66	MAIN[6][28][51]	MAIN[16][28][51]	MAIN[26][28][51]	MAIN[36][28][51]
PMA_CFG bit 67	MAIN[6][29][51]	MAIN[16][29][51]	MAIN[26][29][51]	MAIN[36][29][51]
PMA_CFG bit 68	MAIN[6][28][52]	MAIN[16][28][52]	MAIN[26][28][52]	MAIN[36][28][52]
PMA_CFG bit 69	MAIN[6][29][52]	MAIN[16][29][52]	MAIN[26][29][52]	MAIN[36][29][52]
PMA_CFG bit 70	MAIN[6][28][53]	MAIN[16][28][53]	MAIN[26][28][53]	MAIN[36][28][53]
PMA_CFG bit 71	MAIN[6][29][53]	MAIN[16][29][53]	MAIN[26][29][53]	MAIN[36][29][53]
PMA_CFG bit 72	MAIN[6][28][54]	MAIN[16][28][54]	MAIN[26][28][54]	MAIN[36][28][54]
PMA_CFG bit 73	MAIN[6][29][54]	MAIN[16][29][54]	MAIN[26][29][54]	MAIN[36][29][54]
PMA_CFG bit 74	MAIN[6][28][55]	MAIN[16][28][55]	MAIN[26][28][55]	MAIN[36][28][55]
PMA_CFG bit 75	MAIN[6][29][55]	MAIN[16][29][55]	MAIN[26][29][55]	MAIN[36][29][55]
PMA_RXSYNC_CFG bit 0	MAIN[0][29][12]	MAIN[10][29][12]	MAIN[20][29][12]	MAIN[30][29][12]
PMA_RXSYNC_CFG bit 1	MAIN[0][28][13]	MAIN[10][28][13]	MAIN[20][28][13]	MAIN[30][28][13]
PMA_RXSYNC_CFG bit 2	MAIN[0][29][13]	MAIN[10][29][13]	MAIN[20][29][13]	MAIN[30][29][13]
PMA_RXSYNC_CFG bit 3	MAIN[0][28][14]	MAIN[10][28][14]	MAIN[20][28][14]	MAIN[30][28][14]
PMA_RXSYNC_CFG bit 4	MAIN[0][29][14]	MAIN[10][29][14]	MAIN[20][29][14]	MAIN[30][29][14]
PMA_RXSYNC_CFG bit 5	MAIN[0][28][15]	MAIN[10][28][15]	MAIN[20][28][15]	MAIN[30][28][15]
PMA_RXSYNC_CFG bit 6	MAIN[0][29][15]	MAIN[10][29][15]	MAIN[20][29][15]	MAIN[30][29][15]
PMA_RX_CFG bit 0	MAIN[0][28][0]	MAIN[10][28][0]	MAIN[20][28][0]	MAIN[30][28][0]
PMA_RX_CFG bit 1	MAIN[0][29][0]	MAIN[10][29][0]	MAIN[20][29][0]	MAIN[30][29][0]
PMA_RX_CFG bit 2	MAIN[0][28][1]	MAIN[10][28][1]	MAIN[20][28][1]	MAIN[30][28][1]
PMA_RX_CFG bit 3	MAIN[0][29][1]	MAIN[10][29][1]	MAIN[20][29][1]	MAIN[30][29][1]
PMA_RX_CFG bit 4	MAIN[0][28][2]	MAIN[10][28][2]	MAIN[20][28][2]	MAIN[30][28][2]
PMA_RX_CFG bit 5	MAIN[0][29][2]	MAIN[10][29][2]	MAIN[20][29][2]	MAIN[30][29][2]
PMA_RX_CFG bit 6	MAIN[0][28][3]	MAIN[10][28][3]	MAIN[20][28][3]	MAIN[30][28][3]
PMA_RX_CFG bit 7	MAIN[0][29][3]	MAIN[10][29][3]	MAIN[20][29][3]	MAIN[30][29][3]
PMA_RX_CFG bit 8	MAIN[0][28][4]	MAIN[10][28][4]	MAIN[20][28][4]	MAIN[30][28][4]
PMA_RX_CFG bit 9	MAIN[0][29][4]	MAIN[10][29][4]	MAIN[20][29][4]	MAIN[30][29][4]
PMA_RX_CFG bit 10	MAIN[0][28][5]	MAIN[10][28][5]	MAIN[20][28][5]	MAIN[30][28][5]
PMA_RX_CFG bit 11	MAIN[0][29][5]	MAIN[10][29][5]	MAIN[20][29][5]	MAIN[30][29][5]
PMA_RX_CFG bit 12	MAIN[0][28][6]	MAIN[10][28][6]	MAIN[20][28][6]	MAIN[30][28][6]
PMA_RX_CFG bit 13	MAIN[0][29][6]	MAIN[10][29][6]	MAIN[20][29][6]	MAIN[30][29][6]
PMA_RX_CFG bit 14	MAIN[0][28][7]	MAIN[10][28][7]	MAIN[20][28][7]	MAIN[30][28][7]
PMA_RX_CFG bit 15	MAIN[0][29][7]	MAIN[10][29][7]	MAIN[20][29][7]	MAIN[30][29][7]
PMA_RX_CFG bit 16	MAIN[0][28][8]	MAIN[10][28][8]	MAIN[20][28][8]	MAIN[30][28][8]
PMA_RX_CFG bit 17	MAIN[0][29][8]	MAIN[10][29][8]	MAIN[20][29][8]	MAIN[30][29][8]
PMA_RX_CFG bit 18	MAIN[0][28][9]	MAIN[10][28][9]	MAIN[20][28][9]	MAIN[30][28][9]
PMA_RX_CFG bit 19	MAIN[0][29][9]	MAIN[10][29][9]	MAIN[20][29][9]	MAIN[30][29][9]
PMA_RX_CFG bit 20	MAIN[0][28][10]	MAIN[10][28][10]	MAIN[20][28][10]	MAIN[30][28][10]
PMA_RX_CFG bit 21	MAIN[0][29][10]	MAIN[10][29][10]	MAIN[20][29][10]	MAIN[30][29][10]
PMA_RX_CFG bit 22	MAIN[0][28][11]	MAIN[10][28][11]	MAIN[20][28][11]	MAIN[30][28][11]
PMA_RX_CFG bit 23	MAIN[0][29][11]	MAIN[10][29][11]	MAIN[20][29][11]	MAIN[30][29][11]
PMA_RX_CFG bit 24	MAIN[0][28][12]	MAIN[10][28][12]	MAIN[20][28][12]	MAIN[30][28][12]
PMA_TX_CFG bit 0	MAIN[6][28][56]	MAIN[16][28][56]	MAIN[26][28][56]	MAIN[36][28][56]
PMA_TX_CFG bit 1	MAIN[6][29][56]	MAIN[16][29][56]	MAIN[26][29][56]	MAIN[36][29][56]
PMA_TX_CFG bit 2	MAIN[6][28][57]	MAIN[16][28][57]	MAIN[26][28][57]	MAIN[36][28][57]
PMA_TX_CFG bit 3	MAIN[6][29][57]	MAIN[16][29][57]	MAIN[26][29][57]	MAIN[36][29][57]
PMA_TX_CFG bit 4	MAIN[6][28][58]	MAIN[16][28][58]	MAIN[26][28][58]	MAIN[36][28][58]
PMA_TX_CFG bit 5	MAIN[6][29][58]	MAIN[16][29][58]	MAIN[26][29][58]	MAIN[36][29][58]
PMA_TX_CFG bit 6	MAIN[6][28][59]	MAIN[16][28][59]	MAIN[26][28][59]	MAIN[36][28][59]
PMA_TX_CFG bit 7	MAIN[6][29][59]	MAIN[16][29][59]	MAIN[26][29][59]	MAIN[36][29][59]
PMA_TX_CFG bit 8	MAIN[6][28][60]	MAIN[16][28][60]	MAIN[26][28][60]	MAIN[36][28][60]
PMA_TX_CFG bit 9	MAIN[6][29][60]	MAIN[16][29][60]	MAIN[26][29][60]	MAIN[36][29][60]
PMA_TX_CFG bit 10	MAIN[6][28][61]	MAIN[16][28][61]	MAIN[26][28][61]	MAIN[36][28][61]
PMA_TX_CFG bit 11	MAIN[6][29][61]	MAIN[16][29][61]	MAIN[26][29][61]	MAIN[36][29][61]
PMA_TX_CFG bit 12	MAIN[6][28][62]	MAIN[16][28][62]	MAIN[26][28][62]	MAIN[36][28][62]
PMA_TX_CFG bit 13	MAIN[6][29][62]	MAIN[16][29][62]	MAIN[26][29][62]	MAIN[36][29][62]
PMA_TX_CFG bit 14	MAIN[6][28][63]	MAIN[16][28][63]	MAIN[26][28][63]	MAIN[36][28][63]
PMA_TX_CFG bit 15	MAIN[6][29][63]	MAIN[16][29][63]	MAIN[26][29][63]	MAIN[36][29][63]
PMA_TX_CFG bit 16	MAIN[6][28][48]	MAIN[16][28][48]	MAIN[26][28][48]	MAIN[36][28][48]
PMA_TX_CFG bit 17	MAIN[6][29][48]	MAIN[16][29][48]	MAIN[26][29][48]	MAIN[36][29][48]
PMA_TX_CFG bit 18	MAIN[6][28][49]	MAIN[16][28][49]	MAIN[26][28][49]	MAIN[36][28][49]
PMA_TX_CFG bit 19	MAIN[6][29][49]	MAIN[16][29][49]	MAIN[26][29][49]	MAIN[36][29][49]
RXPLL_COM_CFG bit 0	MAIN[3][28][8]	MAIN[13][28][8]	MAIN[23][28][8]	MAIN[33][28][8]
RXPLL_COM_CFG bit 1	MAIN[3][29][8]	MAIN[13][29][8]	MAIN[23][29][8]	MAIN[33][29][8]
RXPLL_COM_CFG bit 2	MAIN[3][28][9]	MAIN[13][28][9]	MAIN[23][28][9]	MAIN[33][28][9]
RXPLL_COM_CFG bit 3	MAIN[3][29][9]	MAIN[13][29][9]	MAIN[23][29][9]	MAIN[33][29][9]
RXPLL_COM_CFG bit 4	MAIN[3][28][10]	MAIN[13][28][10]	MAIN[23][28][10]	MAIN[33][28][10]
RXPLL_COM_CFG bit 5	MAIN[3][29][10]	MAIN[13][29][10]	MAIN[23][29][10]	MAIN[33][29][10]
RXPLL_COM_CFG bit 6	MAIN[3][28][11]	MAIN[13][28][11]	MAIN[23][28][11]	MAIN[33][28][11]
RXPLL_COM_CFG bit 7	MAIN[3][29][11]	MAIN[13][29][11]	MAIN[23][29][11]	MAIN[33][29][11]
RXPLL_COM_CFG bit 8	MAIN[3][28][12]	MAIN[13][28][12]	MAIN[23][28][12]	MAIN[33][28][12]
RXPLL_COM_CFG bit 9	MAIN[3][29][12]	MAIN[13][29][12]	MAIN[23][29][12]	MAIN[33][29][12]
RXPLL_COM_CFG bit 10	MAIN[3][28][13]	MAIN[13][28][13]	MAIN[23][28][13]	MAIN[33][28][13]
RXPLL_COM_CFG bit 11	MAIN[3][29][13]	MAIN[13][29][13]	MAIN[23][29][13]	MAIN[33][29][13]
RXPLL_COM_CFG bit 12	MAIN[3][28][14]	MAIN[13][28][14]	MAIN[23][28][14]	MAIN[33][28][14]
RXPLL_COM_CFG bit 13	MAIN[3][29][14]	MAIN[13][29][14]	MAIN[23][29][14]	MAIN[33][29][14]
RXPLL_COM_CFG bit 14	MAIN[3][28][15]	MAIN[13][28][15]	MAIN[23][28][15]	MAIN[33][28][15]
RXPLL_COM_CFG bit 15	MAIN[3][29][15]	MAIN[13][29][15]	MAIN[23][29][15]	MAIN[33][29][15]
RXPLL_COM_CFG bit 16	MAIN[3][28][16]	MAIN[13][28][16]	MAIN[23][28][16]	MAIN[33][28][16]
RXPLL_COM_CFG bit 17	MAIN[3][29][16]	MAIN[13][29][16]	MAIN[23][29][16]	MAIN[33][29][16]
RXPLL_COM_CFG bit 18	MAIN[3][28][17]	MAIN[13][28][17]	MAIN[23][28][17]	MAIN[33][28][17]
RXPLL_COM_CFG bit 19	MAIN[3][29][17]	MAIN[13][29][17]	MAIN[23][29][17]	MAIN[33][29][17]
RXPLL_COM_CFG bit 20	MAIN[3][28][18]	MAIN[13][28][18]	MAIN[23][28][18]	MAIN[33][28][18]
RXPLL_COM_CFG bit 21	MAIN[3][29][18]	MAIN[13][29][18]	MAIN[23][29][18]	MAIN[33][29][18]
RXPLL_COM_CFG bit 22	MAIN[3][28][19]	MAIN[13][28][19]	MAIN[23][28][19]	MAIN[33][28][19]
RXPLL_COM_CFG bit 23	MAIN[3][29][19]	MAIN[13][29][19]	MAIN[23][29][19]	MAIN[33][29][19]
RXPLL_CP_CFG bit 0	MAIN[3][28][20]	MAIN[13][28][20]	MAIN[23][28][20]	MAIN[33][28][20]
RXPLL_CP_CFG bit 1	MAIN[3][29][20]	MAIN[13][29][20]	MAIN[23][29][20]	MAIN[33][29][20]
RXPLL_CP_CFG bit 2	MAIN[3][28][21]	MAIN[13][28][21]	MAIN[23][28][21]	MAIN[33][28][21]
RXPLL_CP_CFG bit 3	MAIN[3][29][21]	MAIN[13][29][21]	MAIN[23][29][21]	MAIN[33][29][21]
RXPLL_CP_CFG bit 4	MAIN[3][28][22]	MAIN[13][28][22]	MAIN[23][28][22]	MAIN[33][28][22]
RXPLL_CP_CFG bit 5	MAIN[3][29][22]	MAIN[13][29][22]	MAIN[23][29][22]	MAIN[33][29][22]
RXPLL_CP_CFG bit 6	MAIN[3][28][23]	MAIN[13][28][23]	MAIN[23][28][23]	MAIN[33][28][23]
RXPLL_CP_CFG bit 7	MAIN[3][29][23]	MAIN[13][29][23]	MAIN[23][29][23]	MAIN[33][29][23]
RXUSRCLK_DLY bit 0	MAIN[0][28][16]	MAIN[10][28][16]	MAIN[20][28][16]	MAIN[30][28][16]
RXUSRCLK_DLY bit 1	MAIN[0][29][16]	MAIN[10][29][16]	MAIN[20][29][16]	MAIN[30][29][16]
RXUSRCLK_DLY bit 2	MAIN[0][28][17]	MAIN[10][28][17]	MAIN[20][28][17]	MAIN[30][28][17]
RXUSRCLK_DLY bit 3	MAIN[0][29][17]	MAIN[10][29][17]	MAIN[20][29][17]	MAIN[30][29][17]
RXUSRCLK_DLY bit 4	MAIN[0][28][18]	MAIN[10][28][18]	MAIN[20][28][18]	MAIN[30][28][18]
RXUSRCLK_DLY bit 5	MAIN[0][29][18]	MAIN[10][29][18]	MAIN[20][29][18]	MAIN[30][29][18]
RXUSRCLK_DLY bit 6	MAIN[0][28][19]	MAIN[10][28][19]	MAIN[20][28][19]	MAIN[30][28][19]
RXUSRCLK_DLY bit 7	MAIN[0][29][19]	MAIN[10][29][19]	MAIN[20][29][19]	MAIN[30][29][19]
RXUSRCLK_DLY bit 8	MAIN[0][28][20]	MAIN[10][28][20]	MAIN[20][28][20]	MAIN[30][28][20]
RXUSRCLK_DLY bit 9	MAIN[0][29][20]	MAIN[10][29][20]	MAIN[20][29][20]	MAIN[30][29][20]
RXUSRCLK_DLY bit 10	MAIN[0][28][21]	MAIN[10][28][21]	MAIN[20][28][21]	MAIN[30][28][21]
RXUSRCLK_DLY bit 11	MAIN[0][29][21]	MAIN[10][29][21]	MAIN[20][29][21]	MAIN[30][29][21]
RXUSRCLK_DLY bit 12	MAIN[0][28][22]	MAIN[10][28][22]	MAIN[20][28][22]	MAIN[30][28][22]
RXUSRCLK_DLY bit 13	MAIN[0][29][22]	MAIN[10][29][22]	MAIN[20][29][22]	MAIN[30][29][22]
RXUSRCLK_DLY bit 14	MAIN[0][28][23]	MAIN[10][28][23]	MAIN[20][28][23]	MAIN[30][28][23]
RXUSRCLK_DLY bit 15	MAIN[0][29][23]	MAIN[10][29][23]	MAIN[20][29][23]	MAIN[30][29][23]
RX_EYE_OFFSET bit 0	MAIN[5][28][44]	MAIN[15][28][44]	MAIN[25][28][44]	MAIN[35][28][44]
RX_EYE_OFFSET bit 1	MAIN[5][29][44]	MAIN[15][29][44]	MAIN[25][29][44]	MAIN[35][29][44]
RX_EYE_OFFSET bit 2	MAIN[5][28][45]	MAIN[15][28][45]	MAIN[25][28][45]	MAIN[35][28][45]
RX_EYE_OFFSET bit 3	MAIN[5][29][45]	MAIN[15][29][45]	MAIN[25][29][45]	MAIN[35][29][45]
RX_EYE_OFFSET bit 4	MAIN[5][28][46]	MAIN[15][28][46]	MAIN[25][28][46]	MAIN[35][28][46]
RX_EYE_OFFSET bit 5	MAIN[5][29][46]	MAIN[15][29][46]	MAIN[25][29][46]	MAIN[35][29][46]
RX_EYE_OFFSET bit 6	MAIN[5][28][47]	MAIN[15][28][47]	MAIN[25][28][47]	MAIN[35][28][47]
RX_EYE_OFFSET bit 7	MAIN[5][29][47]	MAIN[15][29][47]	MAIN[25][29][47]	MAIN[35][29][47]
TRANS_TIME_FROM_P2 bit 0	MAIN[4][28][32]	MAIN[14][28][32]	MAIN[24][28][32]	MAIN[34][28][32]
TRANS_TIME_FROM_P2 bit 1	MAIN[4][29][32]	MAIN[14][29][32]	MAIN[24][29][32]	MAIN[34][29][32]
TRANS_TIME_FROM_P2 bit 2	MAIN[4][28][33]	MAIN[14][28][33]	MAIN[24][28][33]	MAIN[34][28][33]
TRANS_TIME_FROM_P2 bit 3	MAIN[4][29][33]	MAIN[14][29][33]	MAIN[24][29][33]	MAIN[34][29][33]
TRANS_TIME_FROM_P2 bit 4	MAIN[4][28][34]	MAIN[14][28][34]	MAIN[24][28][34]	MAIN[34][28][34]
TRANS_TIME_FROM_P2 bit 5	MAIN[4][29][34]	MAIN[14][29][34]	MAIN[24][29][34]	MAIN[34][29][34]
TRANS_TIME_FROM_P2 bit 6	MAIN[4][28][35]	MAIN[14][28][35]	MAIN[24][28][35]	MAIN[34][28][35]
TRANS_TIME_FROM_P2 bit 7	MAIN[4][29][35]	MAIN[14][29][35]	MAIN[24][29][35]	MAIN[34][29][35]
TRANS_TIME_FROM_P2 bit 8	MAIN[4][28][36]	MAIN[14][28][36]	MAIN[24][28][36]	MAIN[34][28][36]
TRANS_TIME_FROM_P2 bit 9	MAIN[4][29][36]	MAIN[14][29][36]	MAIN[24][29][36]	MAIN[34][29][36]
TRANS_TIME_FROM_P2 bit 10	MAIN[4][28][37]	MAIN[14][28][37]	MAIN[24][28][37]	MAIN[34][28][37]
TRANS_TIME_FROM_P2 bit 11	MAIN[4][29][37]	MAIN[14][29][37]	MAIN[24][29][37]	MAIN[34][29][37]
TRANS_TIME_NON_P2 bit 0	MAIN[4][28][40]	MAIN[14][28][40]	MAIN[24][28][40]	MAIN[34][28][40]
TRANS_TIME_NON_P2 bit 1	MAIN[4][29][40]	MAIN[14][29][40]	MAIN[24][29][40]	MAIN[34][29][40]
TRANS_TIME_NON_P2 bit 2	MAIN[4][28][41]	MAIN[14][28][41]	MAIN[24][28][41]	MAIN[34][28][41]
TRANS_TIME_NON_P2 bit 3	MAIN[4][29][41]	MAIN[14][29][41]	MAIN[24][29][41]	MAIN[34][29][41]
TRANS_TIME_NON_P2 bit 4	MAIN[4][28][42]	MAIN[14][28][42]	MAIN[24][28][42]	MAIN[34][28][42]
TRANS_TIME_NON_P2 bit 5	MAIN[4][29][42]	MAIN[14][29][42]	MAIN[24][29][42]	MAIN[34][29][42]
TRANS_TIME_NON_P2 bit 6	MAIN[4][28][43]	MAIN[14][28][43]	MAIN[24][28][43]	MAIN[34][28][43]
TRANS_TIME_NON_P2 bit 7	MAIN[4][29][43]	MAIN[14][29][43]	MAIN[24][29][43]	MAIN[34][29][43]
TRANS_TIME_RATE bit 0	MAIN[7][28][56]	MAIN[17][28][56]	MAIN[27][28][56]	MAIN[37][28][56]
TRANS_TIME_RATE bit 1	MAIN[7][29][56]	MAIN[17][29][56]	MAIN[27][29][56]	MAIN[37][29][56]
TRANS_TIME_RATE bit 2	MAIN[7][28][57]	MAIN[17][28][57]	MAIN[27][28][57]	MAIN[37][28][57]
TRANS_TIME_RATE bit 3	MAIN[7][29][57]	MAIN[17][29][57]	MAIN[27][29][57]	MAIN[37][29][57]
TRANS_TIME_RATE bit 4	MAIN[7][28][58]	MAIN[17][28][58]	MAIN[27][28][58]	MAIN[37][28][58]
TRANS_TIME_RATE bit 5	MAIN[7][29][58]	MAIN[17][29][58]	MAIN[27][29][58]	MAIN[37][29][58]
TRANS_TIME_RATE bit 6	MAIN[7][28][59]	MAIN[17][28][59]	MAIN[27][28][59]	MAIN[37][28][59]
TRANS_TIME_RATE bit 7	MAIN[7][29][59]	MAIN[17][29][59]	MAIN[27][29][59]	MAIN[37][29][59]
TRANS_TIME_TO_P2 bit 0	MAIN[4][28][24]	MAIN[14][28][24]	MAIN[24][28][24]	MAIN[34][28][24]
TRANS_TIME_TO_P2 bit 1	MAIN[4][29][24]	MAIN[14][29][24]	MAIN[24][29][24]	MAIN[34][29][24]
TRANS_TIME_TO_P2 bit 2	MAIN[4][28][25]	MAIN[14][28][25]	MAIN[24][28][25]	MAIN[34][28][25]
TRANS_TIME_TO_P2 bit 3	MAIN[4][29][25]	MAIN[14][29][25]	MAIN[24][29][25]	MAIN[34][29][25]
TRANS_TIME_TO_P2 bit 4	MAIN[4][28][26]	MAIN[14][28][26]	MAIN[24][28][26]	MAIN[34][28][26]
TRANS_TIME_TO_P2 bit 5	MAIN[4][29][26]	MAIN[14][29][26]	MAIN[24][29][26]	MAIN[34][29][26]
TRANS_TIME_TO_P2 bit 6	MAIN[4][28][27]	MAIN[14][28][27]	MAIN[24][28][27]	MAIN[34][28][27]
TRANS_TIME_TO_P2 bit 7	MAIN[4][29][27]	MAIN[14][29][27]	MAIN[24][29][27]	MAIN[34][29][27]
TRANS_TIME_TO_P2 bit 8	MAIN[4][28][28]	MAIN[14][28][28]	MAIN[24][28][28]	MAIN[34][28][28]
TRANS_TIME_TO_P2 bit 9	MAIN[4][29][28]	MAIN[14][29][28]	MAIN[24][29][28]	MAIN[34][29][28]
TST_ATTR bit 0	MAIN[8][28][16]	MAIN[18][28][16]	MAIN[28][28][16]	MAIN[38][28][16]
TST_ATTR bit 1	MAIN[8][29][16]	MAIN[18][29][16]	MAIN[28][29][16]	MAIN[38][29][16]
TST_ATTR bit 2	MAIN[8][28][17]	MAIN[18][28][17]	MAIN[28][28][17]	MAIN[38][28][17]
TST_ATTR bit 3	MAIN[8][29][17]	MAIN[18][29][17]	MAIN[28][29][17]	MAIN[38][29][17]
TST_ATTR bit 4	MAIN[8][28][18]	MAIN[18][28][18]	MAIN[28][28][18]	MAIN[38][28][18]
TST_ATTR bit 5	MAIN[8][29][18]	MAIN[18][29][18]	MAIN[28][29][18]	MAIN[38][29][18]
TST_ATTR bit 6	MAIN[8][28][19]	MAIN[18][28][19]	MAIN[28][28][19]	MAIN[38][28][19]
TST_ATTR bit 7	MAIN[8][29][19]	MAIN[18][29][19]	MAIN[28][29][19]	MAIN[38][29][19]
TST_ATTR bit 8	MAIN[8][28][20]	MAIN[18][28][20]	MAIN[28][28][20]	MAIN[38][28][20]
TST_ATTR bit 9	MAIN[8][29][20]	MAIN[18][29][20]	MAIN[28][29][20]	MAIN[38][29][20]
TST_ATTR bit 10	MAIN[8][28][21]	MAIN[18][28][21]	MAIN[28][28][21]	MAIN[38][28][21]
TST_ATTR bit 11	MAIN[8][29][21]	MAIN[18][29][21]	MAIN[28][29][21]	MAIN[38][29][21]
TST_ATTR bit 12	MAIN[8][28][22]	MAIN[18][28][22]	MAIN[28][28][22]	MAIN[38][28][22]
TST_ATTR bit 13	MAIN[8][29][22]	MAIN[18][29][22]	MAIN[28][29][22]	MAIN[38][29][22]
TST_ATTR bit 14	MAIN[8][28][23]	MAIN[18][28][23]	MAIN[28][28][23]	MAIN[38][28][23]
TST_ATTR bit 15	MAIN[8][29][23]	MAIN[18][29][23]	MAIN[28][29][23]	MAIN[38][29][23]
TST_ATTR bit 16	MAIN[8][28][8]	MAIN[18][28][8]	MAIN[28][28][8]	MAIN[38][28][8]
TST_ATTR bit 17	MAIN[8][29][8]	MAIN[18][29][8]	MAIN[28][29][8]	MAIN[38][29][8]
TST_ATTR bit 18	MAIN[8][28][9]	MAIN[18][28][9]	MAIN[28][28][9]	MAIN[38][28][9]
TST_ATTR bit 19	MAIN[8][29][9]	MAIN[18][29][9]	MAIN[28][29][9]	MAIN[38][29][9]
TST_ATTR bit 20	MAIN[8][28][10]	MAIN[18][28][10]	MAIN[28][28][10]	MAIN[38][28][10]
TST_ATTR bit 21	MAIN[8][29][10]	MAIN[18][29][10]	MAIN[28][29][10]	MAIN[38][29][10]
TST_ATTR bit 22	MAIN[8][28][11]	MAIN[18][28][11]	MAIN[28][28][11]	MAIN[38][28][11]
TST_ATTR bit 23	MAIN[8][29][11]	MAIN[18][29][11]	MAIN[28][29][11]	MAIN[38][29][11]
TST_ATTR bit 24	MAIN[8][28][12]	MAIN[18][28][12]	MAIN[28][28][12]	MAIN[38][28][12]
TST_ATTR bit 25	MAIN[8][29][12]	MAIN[18][29][12]	MAIN[28][29][12]	MAIN[38][29][12]
TST_ATTR bit 26	MAIN[8][28][13]	MAIN[18][28][13]	MAIN[28][28][13]	MAIN[38][28][13]
TST_ATTR bit 27	MAIN[8][29][13]	MAIN[18][29][13]	MAIN[28][29][13]	MAIN[38][29][13]
TST_ATTR bit 28	MAIN[8][28][14]	MAIN[18][28][14]	MAIN[28][28][14]	MAIN[38][28][14]
TST_ATTR bit 29	MAIN[8][29][14]	MAIN[18][29][14]	MAIN[28][29][14]	MAIN[38][29][14]
TST_ATTR bit 30	MAIN[8][28][15]	MAIN[18][28][15]	MAIN[28][28][15]	MAIN[38][28][15]
TST_ATTR bit 31	MAIN[8][29][15]	MAIN[18][29][15]	MAIN[28][29][15]	MAIN[38][29][15]
TXPLL_COM_CFG bit 0	MAIN[3][28][40]	MAIN[13][28][40]	MAIN[23][28][40]	MAIN[33][28][40]
TXPLL_COM_CFG bit 1	MAIN[3][29][40]	MAIN[13][29][40]	MAIN[23][29][40]	MAIN[33][29][40]
TXPLL_COM_CFG bit 2	MAIN[3][28][41]	MAIN[13][28][41]	MAIN[23][28][41]	MAIN[33][28][41]
TXPLL_COM_CFG bit 3	MAIN[3][29][41]	MAIN[13][29][41]	MAIN[23][29][41]	MAIN[33][29][41]
TXPLL_COM_CFG bit 4	MAIN[3][28][42]	MAIN[13][28][42]	MAIN[23][28][42]	MAIN[33][28][42]
TXPLL_COM_CFG bit 5	MAIN[3][29][42]	MAIN[13][29][42]	MAIN[23][29][42]	MAIN[33][29][42]
TXPLL_COM_CFG bit 6	MAIN[3][28][43]	MAIN[13][28][43]	MAIN[23][28][43]	MAIN[33][28][43]
TXPLL_COM_CFG bit 7	MAIN[3][29][43]	MAIN[13][29][43]	MAIN[23][29][43]	MAIN[33][29][43]
TXPLL_COM_CFG bit 8	MAIN[3][28][44]	MAIN[13][28][44]	MAIN[23][28][44]	MAIN[33][28][44]
TXPLL_COM_CFG bit 9	MAIN[3][29][44]	MAIN[13][29][44]	MAIN[23][29][44]	MAIN[33][29][44]
TXPLL_COM_CFG bit 10	MAIN[3][28][45]	MAIN[13][28][45]	MAIN[23][28][45]	MAIN[33][28][45]
TXPLL_COM_CFG bit 11	MAIN[3][29][45]	MAIN[13][29][45]	MAIN[23][29][45]	MAIN[33][29][45]
TXPLL_COM_CFG bit 12	MAIN[3][28][46]	MAIN[13][28][46]	MAIN[23][28][46]	MAIN[33][28][46]
TXPLL_COM_CFG bit 13	MAIN[3][29][46]	MAIN[13][29][46]	MAIN[23][29][46]	MAIN[33][29][46]
TXPLL_COM_CFG bit 14	MAIN[3][28][47]	MAIN[13][28][47]	MAIN[23][28][47]	MAIN[33][28][47]
TXPLL_COM_CFG bit 15	MAIN[3][29][47]	MAIN[13][29][47]	MAIN[23][29][47]	MAIN[33][29][47]
TXPLL_COM_CFG bit 16	MAIN[3][28][48]	MAIN[13][28][48]	MAIN[23][28][48]	MAIN[33][28][48]
TXPLL_COM_CFG bit 17	MAIN[3][29][48]	MAIN[13][29][48]	MAIN[23][29][48]	MAIN[33][29][48]
TXPLL_COM_CFG bit 18	MAIN[3][28][49]	MAIN[13][28][49]	MAIN[23][28][49]	MAIN[33][28][49]
TXPLL_COM_CFG bit 19	MAIN[3][29][49]	MAIN[13][29][49]	MAIN[23][29][49]	MAIN[33][29][49]
TXPLL_COM_CFG bit 20	MAIN[3][28][50]	MAIN[13][28][50]	MAIN[23][28][50]	MAIN[33][28][50]
TXPLL_COM_CFG bit 21	MAIN[3][29][50]	MAIN[13][29][50]	MAIN[23][29][50]	MAIN[33][29][50]
TXPLL_COM_CFG bit 22	MAIN[3][28][51]	MAIN[13][28][51]	MAIN[23][28][51]	MAIN[33][28][51]
TXPLL_COM_CFG bit 23	MAIN[3][29][51]	MAIN[13][29][51]	MAIN[23][29][51]	MAIN[33][29][51]
TXPLL_CP_CFG bit 0	MAIN[3][28][52]	MAIN[13][28][52]	MAIN[23][28][52]	MAIN[33][28][52]
TXPLL_CP_CFG bit 1	MAIN[3][29][52]	MAIN[13][29][52]	MAIN[23][29][52]	MAIN[33][29][52]
TXPLL_CP_CFG bit 2	MAIN[3][28][53]	MAIN[13][28][53]	MAIN[23][28][53]	MAIN[33][28][53]
TXPLL_CP_CFG bit 3	MAIN[3][29][53]	MAIN[13][29][53]	MAIN[23][29][53]	MAIN[33][29][53]
TXPLL_CP_CFG bit 4	MAIN[3][28][54]	MAIN[13][28][54]	MAIN[23][28][54]	MAIN[33][28][54]
TXPLL_CP_CFG bit 5	MAIN[3][29][54]	MAIN[13][29][54]	MAIN[23][29][54]	MAIN[33][29][54]
TXPLL_CP_CFG bit 6	MAIN[3][28][55]	MAIN[13][28][55]	MAIN[23][28][55]	MAIN[33][28][55]
TXPLL_CP_CFG bit 7	MAIN[3][29][55]	MAIN[13][29][55]	MAIN[23][29][55]	MAIN[33][29][55]
TX_BYTECLK_CFG bit 0	MAIN[8][28][40]	MAIN[18][28][40]	MAIN[28][28][40]	MAIN[38][28][40]
TX_BYTECLK_CFG bit 1	MAIN[8][29][40]	MAIN[18][29][40]	MAIN[28][29][40]	MAIN[38][29][40]
TX_BYTECLK_CFG bit 2	MAIN[8][28][41]	MAIN[18][28][41]	MAIN[28][28][41]	MAIN[38][28][41]
TX_BYTECLK_CFG bit 3	MAIN[8][29][41]	MAIN[18][29][41]	MAIN[28][29][41]	MAIN[38][29][41]
TX_BYTECLK_CFG bit 4	MAIN[8][28][42]	MAIN[18][28][42]	MAIN[28][28][42]	MAIN[38][28][42]
TX_BYTECLK_CFG bit 5	MAIN[8][29][42]	MAIN[18][29][42]	MAIN[28][29][42]	MAIN[38][29][42]
TX_DETECT_RX_CFG bit 0	MAIN[4][28][8]	MAIN[14][28][8]	MAIN[24][28][8]	MAIN[34][28][8]
TX_DETECT_RX_CFG bit 1	MAIN[4][29][8]	MAIN[14][29][8]	MAIN[24][29][8]	MAIN[34][29][8]
TX_DETECT_RX_CFG bit 2	MAIN[4][28][9]	MAIN[14][28][9]	MAIN[24][28][9]	MAIN[34][28][9]
TX_DETECT_RX_CFG bit 3	MAIN[4][29][9]	MAIN[14][29][9]	MAIN[24][29][9]	MAIN[34][29][9]
TX_DETECT_RX_CFG bit 4	MAIN[4][28][10]	MAIN[14][28][10]	MAIN[24][28][10]	MAIN[34][28][10]
TX_DETECT_RX_CFG bit 5	MAIN[4][29][10]	MAIN[14][29][10]	MAIN[24][29][10]	MAIN[34][29][10]
TX_DETECT_RX_CFG bit 6	MAIN[4][28][11]	MAIN[14][28][11]	MAIN[24][28][11]	MAIN[34][28][11]
TX_DETECT_RX_CFG bit 7	MAIN[4][29][11]	MAIN[14][29][11]	MAIN[24][29][11]	MAIN[34][29][11]
TX_DETECT_RX_CFG bit 8	MAIN[4][28][12]	MAIN[14][28][12]	MAIN[24][28][12]	MAIN[34][28][12]
TX_DETECT_RX_CFG bit 9	MAIN[4][29][12]	MAIN[14][29][12]	MAIN[24][29][12]	MAIN[34][29][12]
TX_DETECT_RX_CFG bit 10	MAIN[4][28][13]	MAIN[14][28][13]	MAIN[24][28][13]	MAIN[34][28][13]
TX_DETECT_RX_CFG bit 11	MAIN[4][29][13]	MAIN[14][29][13]	MAIN[24][29][13]	MAIN[34][29][13]
TX_DETECT_RX_CFG bit 12	MAIN[4][28][14]	MAIN[14][28][14]	MAIN[24][28][14]	MAIN[34][28][14]
TX_DETECT_RX_CFG bit 13	MAIN[4][29][14]	MAIN[14][29][14]	MAIN[24][29][14]	MAIN[34][29][14]
TX_USRCLK_CFG bit 0	MAIN[8][28][43]	MAIN[18][28][43]	MAIN[28][28][43]	MAIN[38][28][43]
TX_USRCLK_CFG bit 1	MAIN[8][29][43]	MAIN[18][29][43]	MAIN[28][29][43]	MAIN[38][29][43]
TX_USRCLK_CFG bit 2	MAIN[8][28][44]	MAIN[18][28][44]	MAIN[28][28][44]	MAIN[38][28][44]
TX_USRCLK_CFG bit 3	MAIN[8][29][44]	MAIN[18][29][44]	MAIN[28][29][44]	MAIN[38][29][44]
TX_USRCLK_CFG bit 4	MAIN[8][28][45]	MAIN[18][28][45]	MAIN[28][28][45]	MAIN[38][28][45]
TX_USRCLK_CFG bit 5	MAIN[8][29][45]	MAIN[18][29][45]	MAIN[28][29][45]	MAIN[38][29][45]

virtex6 GTX enum GTX_PLLREFSEL
GTX[0].RXPLLREFSEL_STATIC_VAL	MAIN[3][29][36]	MAIN[3][28][36]	MAIN[3][29][35]
GTX[1].RXPLLREFSEL_STATIC_VAL	MAIN[13][29][36]	MAIN[13][28][36]	MAIN[13][29][35]
GTX[2].RXPLLREFSEL_STATIC_VAL	MAIN[23][29][36]	MAIN[23][28][36]	MAIN[23][29][35]
GTX[3].RXPLLREFSEL_STATIC_VAL	MAIN[33][29][36]	MAIN[33][28][36]	MAIN[33][29][35]
GTX[0].TXPLLREFSEL_STATIC_VAL	MAIN[4][29][4]	MAIN[4][28][4]	MAIN[4][29][3]
GTX[1].TXPLLREFSEL_STATIC_VAL	MAIN[14][29][4]	MAIN[14][28][4]	MAIN[14][29][3]
GTX[2].TXPLLREFSEL_STATIC_VAL	MAIN[24][29][4]	MAIN[24][28][4]	MAIN[24][29][3]
GTX[3].TXPLLREFSEL_STATIC_VAL	MAIN[34][29][4]	MAIN[34][28][4]	MAIN[34][29][3]
MGTREFCLK0	0	0	0
MGTREFCLK1	0	0	1
NORTHREFCLK0	0	1	0
NORTHREFCLK1	0	1	1
SOUTHREFCLK0	1	0	0
SOUTHREFCLK1	1	0	1
CAS_CLK	1	1	0
TESTCLK	1	1	1

virtex6 GTX enum GTX_PLLREFSEL_TESTCLK
GTX[0].RXPLLREFSEL_TESTCLK	MAIN[3][28][32]
GTX[1].RXPLLREFSEL_TESTCLK	MAIN[13][28][32]
GTX[2].RXPLLREFSEL_TESTCLK	MAIN[23][28][32]
GTX[3].RXPLLREFSEL_TESTCLK	MAIN[33][28][32]
GTX[0].TXPLLREFSEL_TESTCLK	MAIN[4][28][0]
GTX[1].TXPLLREFSEL_TESTCLK	MAIN[14][28][0]
GTX[2].TXPLLREFSEL_TESTCLK	MAIN[24][28][0]
GTX[3].TXPLLREFSEL_TESTCLK	MAIN[34][28][0]
GREFCLK	0
PERFCLK	1

virtex6 GTX enum GTP_ALIGN_COMMA_WORD
GTX[0].ALIGN_COMMA_WORD	MAIN[2][28][39]
GTX[1].ALIGN_COMMA_WORD	MAIN[12][28][39]
GTX[2].ALIGN_COMMA_WORD	MAIN[22][28][39]
GTX[3].ALIGN_COMMA_WORD	MAIN[32][28][39]
_1	0
_2	1

virtex6 GTX enum GTP_SEQ_LEN
GTX[0].CHAN_BOND_SEQ_LEN	MAIN[0][29][61]	MAIN[0][28][61]
GTX[1].CHAN_BOND_SEQ_LEN	MAIN[10][29][61]	MAIN[10][28][61]
GTX[2].CHAN_BOND_SEQ_LEN	MAIN[20][29][61]	MAIN[20][28][61]
GTX[3].CHAN_BOND_SEQ_LEN	MAIN[30][29][61]	MAIN[30][28][61]
GTX[0].CLK_COR_ADJ_LEN	MAIN[2][29][21]	MAIN[2][28][21]
GTX[1].CLK_COR_ADJ_LEN	MAIN[12][29][21]	MAIN[12][28][21]
GTX[2].CLK_COR_ADJ_LEN	MAIN[22][29][21]	MAIN[22][28][21]
GTX[3].CLK_COR_ADJ_LEN	MAIN[32][29][21]	MAIN[32][28][21]
GTX[0].CLK_COR_DET_LEN	MAIN[2][29][29]	MAIN[2][28][29]
GTX[1].CLK_COR_DET_LEN	MAIN[12][29][29]	MAIN[12][28][29]
GTX[2].CLK_COR_DET_LEN	MAIN[22][29][29]	MAIN[22][28][29]
GTX[3].CLK_COR_DET_LEN	MAIN[32][29][29]	MAIN[32][28][29]
_1	0	0
_2	0	1
_3	1	0
_4	1	1

virtex6 GTX enum GTX_DATA_WIDTH
GTX[0].RX_DATA_WIDTH	MAIN[2][28][63]	MAIN[2][29][62]	MAIN[2][28][62]
GTX[1].RX_DATA_WIDTH	MAIN[12][28][63]	MAIN[12][29][62]	MAIN[12][28][62]
GTX[2].RX_DATA_WIDTH	MAIN[22][28][63]	MAIN[22][29][62]	MAIN[22][28][62]
GTX[3].RX_DATA_WIDTH	MAIN[32][28][63]	MAIN[32][29][62]	MAIN[32][28][62]
GTX[0].TX_DATA_WIDTH	MAIN[6][28][15]	MAIN[6][29][14]	MAIN[6][28][14]
GTX[1].TX_DATA_WIDTH	MAIN[16][28][15]	MAIN[16][29][14]	MAIN[16][28][14]
GTX[2].TX_DATA_WIDTH	MAIN[26][28][15]	MAIN[26][29][14]	MAIN[26][28][14]
GTX[3].TX_DATA_WIDTH	MAIN[36][28][15]	MAIN[36][29][14]	MAIN[36][28][14]
_8	0	0	0
_10	0	0	1
_16	0	1	0
_20	0	1	1
_32	1	0	0
_40	1	0	1

virtex6 GTX enum GTX_RX_FIFO_ADDR_MODE
GTX[0].RX_FIFO_ADDR_MODE	MAIN[1][29][38]
GTX[1].RX_FIFO_ADDR_MODE	MAIN[11][29][38]
GTX[2].RX_FIFO_ADDR_MODE	MAIN[21][29][38]
GTX[3].RX_FIFO_ADDR_MODE	MAIN[31][29][38]
FULL	0
FAST	1

virtex6 GTX enum GT_RX_LOS_INVALID_INCR
GTX[0].RX_LOS_INVALID_INCR	MAIN[0][29][55]	MAIN[0][28][55]	MAIN[0][29][54]
GTX[1].RX_LOS_INVALID_INCR	MAIN[10][29][55]	MAIN[10][28][55]	MAIN[10][29][54]
GTX[2].RX_LOS_INVALID_INCR	MAIN[20][29][55]	MAIN[20][28][55]	MAIN[20][29][54]
GTX[3].RX_LOS_INVALID_INCR	MAIN[30][29][55]	MAIN[30][28][55]	MAIN[30][29][54]
_1	0	0	0
_2	0	0	1
_4	0	1	0
_8	0	1	1
_16	1	0	0
_32	1	0	1
_64	1	1	0
_128	1	1	1

virtex6 GTX enum GT_RX_LOS_THRESHOLD
GTX[0].RX_LOS_THRESHOLD	MAIN[0][28][54]	MAIN[0][29][53]	MAIN[0][28][53]
GTX[1].RX_LOS_THRESHOLD	MAIN[10][28][54]	MAIN[10][29][53]	MAIN[10][28][53]
GTX[2].RX_LOS_THRESHOLD	MAIN[20][28][54]	MAIN[20][29][53]	MAIN[20][28][53]
GTX[3].RX_LOS_THRESHOLD	MAIN[30][28][54]	MAIN[30][29][53]	MAIN[30][28][53]
_4	0	0	0
_8	0	0	1
_16	0	1	0
_32	0	1	1
_64	1	0	0
_128	1	0	1
_256	1	1	0
_512	1	1	1

virtex6 GTX enum GTX_PLL_DIVSEL45_FB
GTX[0].RXPLL_DIVSEL45_FB	MAIN[3][28][27]
GTX[1].RXPLL_DIVSEL45_FB	MAIN[13][28][27]
GTX[2].RXPLL_DIVSEL45_FB	MAIN[23][28][27]
GTX[3].RXPLL_DIVSEL45_FB	MAIN[33][28][27]
GTX[0].TXPLL_DIVSEL45_FB	MAIN[3][28][59]
GTX[1].TXPLL_DIVSEL45_FB	MAIN[13][28][59]
GTX[2].TXPLL_DIVSEL45_FB	MAIN[23][28][59]
GTX[3].TXPLL_DIVSEL45_FB	MAIN[33][28][59]
_4	0
_5	1

virtex6 GTX enum GTP_PLL_DIVSEL_REF
GTX[0].RXPLL_DIVSEL_FB	MAIN[3][29][26]	MAIN[3][28][26]	MAIN[3][29][25]	MAIN[3][28][25]	MAIN[3][29][24]
GTX[1].RXPLL_DIVSEL_FB	MAIN[13][29][26]	MAIN[13][28][26]	MAIN[13][29][25]	MAIN[13][28][25]	MAIN[13][29][24]
GTX[2].RXPLL_DIVSEL_FB	MAIN[23][29][26]	MAIN[23][28][26]	MAIN[23][29][25]	MAIN[23][28][25]	MAIN[23][29][24]
GTX[3].RXPLL_DIVSEL_FB	MAIN[33][29][26]	MAIN[33][28][26]	MAIN[33][29][25]	MAIN[33][28][25]	MAIN[33][29][24]
GTX[0].RXPLL_DIVSEL_REF	MAIN[3][29][34]	MAIN[3][28][34]	MAIN[3][29][33]	MAIN[3][28][33]	MAIN[3][29][32]
GTX[1].RXPLL_DIVSEL_REF	MAIN[13][29][34]	MAIN[13][28][34]	MAIN[13][29][33]	MAIN[13][28][33]	MAIN[13][29][32]
GTX[2].RXPLL_DIVSEL_REF	MAIN[23][29][34]	MAIN[23][28][34]	MAIN[23][29][33]	MAIN[23][28][33]	MAIN[23][29][32]
GTX[3].RXPLL_DIVSEL_REF	MAIN[33][29][34]	MAIN[33][28][34]	MAIN[33][29][33]	MAIN[33][28][33]	MAIN[33][29][32]
GTX[0].TXPLL_DIVSEL_FB	MAIN[3][29][58]	MAIN[3][28][58]	MAIN[3][29][57]	MAIN[3][28][57]	MAIN[3][29][56]
GTX[1].TXPLL_DIVSEL_FB	MAIN[13][29][58]	MAIN[13][28][58]	MAIN[13][29][57]	MAIN[13][28][57]	MAIN[13][29][56]
GTX[2].TXPLL_DIVSEL_FB	MAIN[23][29][58]	MAIN[23][28][58]	MAIN[23][29][57]	MAIN[23][28][57]	MAIN[23][29][56]
GTX[3].TXPLL_DIVSEL_FB	MAIN[33][29][58]	MAIN[33][28][58]	MAIN[33][29][57]	MAIN[33][28][57]	MAIN[33][29][56]
GTX[0].TXPLL_DIVSEL_REF	MAIN[4][29][2]	MAIN[4][28][2]	MAIN[4][29][1]	MAIN[4][28][1]	MAIN[4][29][0]
GTX[1].TXPLL_DIVSEL_REF	MAIN[14][29][2]	MAIN[14][28][2]	MAIN[14][29][1]	MAIN[14][28][1]	MAIN[14][29][0]
GTX[2].TXPLL_DIVSEL_REF	MAIN[24][29][2]	MAIN[24][28][2]	MAIN[24][29][1]	MAIN[24][28][1]	MAIN[24][29][0]
GTX[3].TXPLL_DIVSEL_REF	MAIN[34][29][2]	MAIN[34][28][2]	MAIN[34][29][1]	MAIN[34][28][1]	MAIN[34][29][0]
_1	1	0	0	0	0
_2	0	0	0	0	0
_3	0	0	0	0	1
_4	0	0	0	1	0
_5	0	0	0	1	1
_6	0	0	1	0	1
_8	0	0	1	1	0
_10	0	0	1	1	1
_12	0	1	1	0	1
_16	0	1	1	1	0
_20	0	1	1	1	1

virtex6 GTX enum GTP_PLL_DIVSEL_OUT
GTX[0].RXPLL_DIVSEL_OUT	MAIN[3][29][31]	MAIN[3][28][31]
GTX[1].RXPLL_DIVSEL_OUT	MAIN[13][29][31]	MAIN[13][28][31]
GTX[2].RXPLL_DIVSEL_OUT	MAIN[23][29][31]	MAIN[23][28][31]
GTX[3].RXPLL_DIVSEL_OUT	MAIN[33][29][31]	MAIN[33][28][31]
GTX[0].TXPLL_DIVSEL_OUT	MAIN[3][29][63]	MAIN[3][28][63]
GTX[1].TXPLL_DIVSEL_OUT	MAIN[13][29][63]	MAIN[13][28][63]
GTX[2].TXPLL_DIVSEL_OUT	MAIN[23][29][63]	MAIN[23][28][63]
GTX[3].TXPLL_DIVSEL_OUT	MAIN[33][29][63]	MAIN[33][28][63]
_1	0	0
_2	0	1
_4	1	0

virtex6 GTX enum GTX_RXRECCLK_CTRL
GTX[0].RXRECCLK_CTRL	MAIN[8][29][26]	MAIN[8][28][26]	MAIN[8][29][25]
GTX[1].RXRECCLK_CTRL	MAIN[18][29][26]	MAIN[18][28][26]	MAIN[18][29][25]
GTX[2].RXRECCLK_CTRL	MAIN[28][29][26]	MAIN[28][28][26]	MAIN[28][29][25]
GTX[3].RXRECCLK_CTRL	MAIN[38][29][26]	MAIN[38][28][26]	MAIN[38][29][25]
RXRECCLKPCS	0	0	0
RXRECCLKPMA_DIV1	0	0	1
RXRECCLKPMA_DIV2	0	1	0
RXPLLREFCLK_DIV1	0	1	1
RXPLLREFCLK_DIV2	1	0	0
OFF_LOW	1	0	1
OFF_HIGH	1	1	0
CLKTESTSIG1	1	1	1

virtex6 GTX enum GTX_RX_SLIDE_MODE
GTX[0].RX_SLIDE_MODE	MAIN[2][29][22]	MAIN[2][28][22]
GTX[1].RX_SLIDE_MODE	MAIN[12][29][22]	MAIN[12][28][22]
GTX[2].RX_SLIDE_MODE	MAIN[22][29][22]	MAIN[22][28][22]
GTX[3].RX_SLIDE_MODE	MAIN[32][29][22]	MAIN[32][28][22]
NONE	0	0
AUTO	0	1
PCS	1	0
PMA	1	1

virtex6 GTX enum GTP_RX_XCLK_SEL
GTX[0].RX_XCLK_SEL	MAIN[1][29][29]
GTX[1].RX_XCLK_SEL	MAIN[11][29][29]
GTX[2].RX_XCLK_SEL	MAIN[21][29][29]
GTX[3].RX_XCLK_SEL	MAIN[31][29][29]
RXUSR	1
RXREC	0

virtex6 GTX enum GTX_TX_CLK_SOURCE
GTX[0].TX_CLK_SOURCE	MAIN[3][28][60]
GTX[1].TX_CLK_SOURCE	MAIN[13][28][60]
GTX[2].TX_CLK_SOURCE	MAIN[23][28][60]
GTX[3].TX_CLK_SOURCE	MAIN[33][28][60]
TXPLL	0
RXPLL	1

virtex6 GTX enum GTX_TX_DRIVE_MODE
GTX[0].TX_DRIVE_MODE	MAIN[7][29][39]
GTX[1].TX_DRIVE_MODE	MAIN[17][29][39]
GTX[2].TX_DRIVE_MODE	MAIN[27][29][39]
GTX[3].TX_DRIVE_MODE	MAIN[37][29][39]
DIRECT	0
PIPE	1

virtex6 GTX enum GTX_TXOUTCLK_CTRL
GTX[0].TXOUTCLK_CTRL	MAIN[8][28][25]	MAIN[8][29][24]	MAIN[8][28][24]
GTX[1].TXOUTCLK_CTRL	MAIN[18][28][25]	MAIN[18][29][24]	MAIN[18][28][24]
GTX[2].TXOUTCLK_CTRL	MAIN[28][28][25]	MAIN[28][29][24]	MAIN[28][28][24]
GTX[3].TXOUTCLK_CTRL	MAIN[38][28][25]	MAIN[38][29][24]	MAIN[38][28][24]
TXOUTCLKPCS	0	0	0
TXOUTCLKPMA_DIV1	0	0	1
TXOUTCLKPMA_DIV2	0	1	0
TXPLLREFCLK_DIV1	0	1	1
TXPLLREFCLK_DIV2	1	0	0
OFF_LOW	1	0	1
OFF_HIGH	1	1	0
CLKTESTSIG0	1	1	1

virtex6 GTX enum GTP_TX_XCLK_SEL
GTX[0].TX_XCLK_SEL	MAIN[5][28][63]
GTX[1].TX_XCLK_SEL	MAIN[15][28][63]
GTX[2].TX_XCLK_SEL	MAIN[25][28][63]
GTX[3].TX_XCLK_SEL	MAIN[35][28][63]
TXUSR	1
TXOUT	0

Bel wires

virtex6 GTX bel wires
Wire	Pins
CELL[0].IMUX_CTRL[1]	GTX[0].PRBSCNTRESET
CELL[0].IMUX_IMUX_DELAY[0]	GTX[0].TSTIN[17]
CELL[0].IMUX_IMUX_DELAY[1]	GTX[0].TSTIN[18]
CELL[0].IMUX_IMUX_DELAY[8]	GTX[0].TSTIN[9]
CELL[0].IMUX_IMUX_DELAY[9]	GTX[0].TSTIN[7]
CELL[0].IMUX_IMUX_DELAY[10]	GTX[0].TSTIN[5]
CELL[0].IMUX_IMUX_DELAY[11]	GTX[0].TSTIN[3]
CELL[0].IMUX_IMUX_DELAY[13]	GTX[0].TSTIN[12]
CELL[0].IMUX_IMUX_DELAY[14]	GTX[0].TSTIN[1]
CELL[0].IMUX_IMUX_DELAY[16]	GTX[0].TSTIN[15]
CELL[0].IMUX_IMUX_DELAY[17]	GTX[0].TSTPWRDNOVRD
CELL[0].IMUX_IMUX_DELAY[18]	GTX[0].TSTPWRDN[1]
CELL[0].IMUX_IMUX_DELAY[19]	GTX[0].TSTPWRDN[3]
CELL[0].IMUX_IMUX_DELAY[21]	GTX[0].TSTIN[11]
CELL[0].IMUX_IMUX_DELAY[22]	GTX[0].SCANIN[3]
CELL[0].IMUX_IMUX_DELAY[24]	GTX[0].TSTIN[8]
CELL[0].IMUX_IMUX_DELAY[25]	GTX[0].TSTIN[6]
CELL[0].IMUX_IMUX_DELAY[26]	GTX[0].TSTIN[4]
CELL[0].IMUX_IMUX_DELAY[27]	GTX[0].TSTIN[2]
CELL[0].IMUX_IMUX_DELAY[28]	GTX[0].TSTIN[13]
CELL[0].IMUX_IMUX_DELAY[29]	GTX[0].SCANMODEB
CELL[0].IMUX_IMUX_DELAY[30]	GTX[0].TSTIN[0]
CELL[0].IMUX_IMUX_DELAY[31]	GTX[0].TSTIN[10]
CELL[0].IMUX_IMUX_DELAY[32]	GTX[0].TSTIN[14]
CELL[0].IMUX_IMUX_DELAY[33]	GTX[0].TSTPWRDN[0]
CELL[0].IMUX_IMUX_DELAY[34]	GTX[0].TSTPWRDN[2]
CELL[0].IMUX_IMUX_DELAY[35]	GTX[0].TSTPWRDN[4]
CELL[0].IMUX_IMUX_DELAY[37]	GTX[0].SCANENB
CELL[0].IMUX_IMUX_DELAY[38]	GTX[0].SCANIN[2]
CELL[0].IMUX_IMUX_DELAY[40]	GTX[0].TSTIN[16]
CELL[0].IMUX_IMUX_DELAY[41]	GTX[0].TSTIN[19]
CELL[0].OUT_BEL[0]	GTX[0].RXDATA[18]
CELL[0].OUT_BEL[1]	GTX[0].RXDATA[4]
CELL[0].OUT_BEL[2]	GTX[0].RXDATA[3]
CELL[0].OUT_BEL[3]	GTX[0].RXDATA[17]
CELL[0].OUT_BEL[4]	GTX[0].RXDATA[0]
CELL[0].OUT_BEL[5]	GTX[0].RXDATA[5]
CELL[0].OUT_BEL[6]	GTX[0].RXDATA[2]
CELL[0].OUT_BEL[7]	GTX[0].RXDATA[1]
CELL[0].OUT_BEL[8]	GTX[0].SCANOUT[4]
CELL[0].OUT_BEL[13]	GTX[0].SCANOUT[3]
CELL[0].OUT_BEL[15]	GTX[0].RXDATA[16]
CELL[0].OUT_BEL[16]	GTX[0].RXDATA[22]
CELL[0].OUT_BEL[17]	GTX[0].RXDATA[21]
CELL[0].OUT_BEL[18]	GTX[0].RXDATA[20]
CELL[0].OUT_BEL[20]	GTX[0].RXDATA[23]
CELL[0].OUT_BEL[22]	GTX[0].RXDATA[19]
CELL[0].OUT_BEL[23]	GTX[0].SCANOUT[2]
CELL[1].IMUX_CTRL[0]	GTX[0].GTXRXRESET
CELL[1].IMUX_CTRL[1]	GTX[0].RXCDRRESET
CELL[1].IMUX_IMUX_DELAY[9]	GTX[0].RXSLIDE
CELL[1].IMUX_IMUX_DELAY[11]	GTX[0].RXPMASETPHASE
CELL[1].IMUX_IMUX_DELAY[12]	GTX[0].RXGEARBOXSLIP
CELL[1].IMUX_IMUX_DELAY[14]	GTX[0].RXEQMIX[0]
CELL[1].IMUX_IMUX_DELAY[15]	GTX[0].RXEQMIX[1]
CELL[1].IMUX_IMUX_DELAY[18]	GTX[0].RXENPRBSTST[2]
CELL[1].IMUX_IMUX_DELAY[19]	GTX[0].RXEQMIX[9]
CELL[1].IMUX_IMUX_DELAY[20]	GTX[0].RXEQMIX[7]
CELL[1].IMUX_IMUX_DELAY[21]	GTX[0].RXEQMIX[5]
CELL[1].IMUX_IMUX_DELAY[22]	GTX[0].RXEQMIX[3]
CELL[1].IMUX_IMUX_DELAY[24]	GTX[0].RXBUFWE
CELL[1].IMUX_IMUX_DELAY[26]	GTX[0].RXPOLARITY
CELL[1].IMUX_IMUX_DELAY[27]	GTX[0].RXEQMIX[8]
CELL[1].IMUX_IMUX_DELAY[28]	GTX[0].RXEQMIX[6]
CELL[1].IMUX_IMUX_DELAY[29]	GTX[0].RXEQMIX[4]
CELL[1].IMUX_IMUX_DELAY[30]	GTX[0].RXEQMIX[2]
CELL[1].IMUX_IMUX_DELAY[32]	GTX[0].RXENSAMPLEALIGN
CELL[1].IMUX_IMUX_DELAY[33]	GTX[0].RXENPRBSTST[0]
CELL[1].IMUX_IMUX_DELAY[34]	GTX[0].RXENPRBSTST[1]
CELL[1].IMUX_IMUX_DELAY[35]	GTX[0].RXENPMAPHASEALIGN
CELL[1].IMUX_IMUX_DELAY[36]	GTX[0].RXENMCOMMAALIGN
CELL[1].IMUX_IMUX_DELAY[37]	GTX[0].RXENPCOMMAALIGN
CELL[1].IMUX_IMUX_DELAY[38]	GTX[0].RXENCHANSYNC
CELL[1].IMUX_IMUX_DELAY[39]	GTX[0].RXDEC8B10BUSE
CELL[1].OUT_BEL[0]	GTX[0].RXDATA[24]
CELL[1].OUT_BEL[1]	GTX[0].RXDATA[6]
CELL[1].OUT_BEL[2]	GTX[0].RXDATA[11]
CELL[1].OUT_BEL[3]	GTX[0].RXDATA[31]
CELL[1].OUT_BEL[4]	GTX[0].RXDATA[8]
CELL[1].OUT_BEL[5]	GTX[0].RXDATA[7]
CELL[1].OUT_BEL[6]	GTX[0].RXDATA[10]
CELL[1].OUT_BEL[7]	GTX[0].RXDATA[9]
CELL[1].OUT_BEL[8]	GTX[0].TSTOUT[8]
CELL[1].OUT_BEL[9]	GTX[0].RXDATA[27]
CELL[1].OUT_BEL[10]	GTX[0].TSTOUT[2]
CELL[1].OUT_BEL[11]	GTX[0].RXDATA[29]
CELL[1].OUT_BEL[12]	GTX[0].TSTOUT[9]
CELL[1].OUT_BEL[13]	GTX[0].TSTOUT[6]
CELL[1].OUT_BEL[14]	GTX[0].TSTOUT[4]
CELL[1].OUT_BEL[15]	GTX[0].RXDATA[30]
CELL[1].OUT_BEL[16]	GTX[0].RXDATA[28]
CELL[1].OUT_BEL[17]	GTX[0].TSTOUT[1]
CELL[1].OUT_BEL[18]	GTX[0].RXDATA[26]
CELL[1].OUT_BEL[19]	GTX[0].TSTOUT[7]
CELL[1].OUT_BEL[20]	GTX[0].TSTOUT[3]
CELL[1].OUT_BEL[21]	GTX[0].TSTOUT[0]
CELL[1].OUT_BEL[22]	GTX[0].RXDATA[25]
CELL[1].OUT_BEL[23]	GTX[0].TSTOUT[5]
CELL[2].IMUX_CLK[0]	GTX[0].RXUSRCLK
CELL[2].IMUX_CLK[1]	GTX[0].RXUSRCLK2
CELL[2].IMUX_CTRL[0]	GTX[0].RXBUFRESET
CELL[2].IMUX_CTRL[1]	GTX[0].RXRESET
CELL[2].IMUX_IMUX_DELAY[8]	GTX[0].RXCHBONDSLAVE
CELL[2].IMUX_IMUX_DELAY[10]	GTX[0].RXCHBONDLEVEL[0]
CELL[2].IMUX_IMUX_DELAY[11]	GTX[0].RXCHBONDLEVEL[2]
CELL[2].IMUX_IMUX_DELAY[14]	GTX[0].USRCODEERR
CELL[2].IMUX_IMUX_DELAY[18]	GTX[0].CLKTESTSIG[1]
CELL[2].IMUX_IMUX_DELAY[19]	GTX[0].CLKTESTSIG[0]
CELL[2].IMUX_IMUX_DELAY[20]	GTX[0].RXPLLLKDETEN
CELL[2].IMUX_IMUX_DELAY[21]	GTX[0].RXPLLPOWERDOWN
CELL[2].IMUX_IMUX_DELAY[24]	GTX[0].RXCHBONDMASTER
CELL[2].IMUX_IMUX_DELAY[26]	GTX[0].RXCHBONDLEVEL[1]
CELL[2].IMUX_IMUX_DELAY[27]	GTX[0].GTXTEST[12]
CELL[2].IMUX_IMUX_DELAY[28]	GTX[0].GTXTEST[11]
CELL[2].IMUX_IMUX_DELAY[29]	GTX[0].GTXTEST[10]
CELL[2].IMUX_IMUX_DELAY[30]	GTX[0].GTXTEST[9]
CELL[2].IMUX_IMUX_DELAY[31]	GTX[0].GTXTEST[8]
CELL[2].IMUX_IMUX_DELAY[32]	GTX[0].GTXTEST[7]
CELL[2].IMUX_IMUX_DELAY[33]	GTX[0].GTXTEST[6]
CELL[2].IMUX_IMUX_DELAY[34]	GTX[0].GTXTEST[5]
CELL[2].IMUX_IMUX_DELAY[35]	GTX[0].GTXTEST[4]
CELL[2].IMUX_IMUX_DELAY[36]	GTX[0].GTXTEST[3]
CELL[2].IMUX_IMUX_DELAY[37]	GTX[0].GTXTEST[2]
CELL[2].IMUX_IMUX_DELAY[38]	GTX[0].GTXTEST[1]
CELL[2].IMUX_IMUX_DELAY[39]	GTX[0].GTXTEST[0]
CELL[2].OUT_BEL[0]	GTX[0].RXLOSSOFSYNC[0]
CELL[2].OUT_BEL[1]	GTX[0].RXDATA[15]
CELL[2].OUT_BEL[2]	GTX[0].RXDATA[14]
CELL[2].OUT_BEL[3]	GTX[0].RXCHARISK[3]
CELL[2].OUT_BEL[4]	GTX[0].RXDATAVALID
CELL[2].OUT_BEL[5]	GTX[0].RXCHARISK[1]
CELL[2].OUT_BEL[6]	GTX[0].RXDATA[13]
CELL[2].OUT_BEL[7]	GTX[0].RXDATA[12]
CELL[2].OUT_BEL[8]	GTX[0].RXCHARISCOMMA[2]
CELL[2].OUT_BEL[10]	GTX[0].RXBYTEREALIGN
CELL[2].OUT_BEL[13]	GTX[0].RXBYTEISALIGNED
CELL[2].OUT_BEL[14]	GTX[0].RXCHANREALIGN
CELL[2].OUT_BEL[15]	GTX[0].RXCHARISK[2]
CELL[2].OUT_BEL[18]	GTX[0].RXCHARISCOMMA[3]
CELL[2].OUT_BEL[19]	GTX[0].COMSASDET
CELL[2].OUT_BEL[20]	GTX[0].COMINITDET
CELL[2].OUT_BEL[22]	GTX[0].RXLOSSOFSYNC[1]
CELL[2].OUT_BEL[23]	GTX[0].COMWAKEDET
CELL[3].IMUX_CLK[0]	GTX[0].GREFCLKRX
CELL[3].IMUX_CLK[1]	GTX[0].TSTCLK[0]
CELL[3].IMUX_CTRL[0]	GTX[0].PLLRXRESET
CELL[3].IMUX_IMUX_DELAY[0]	GTX[0].TXBUFDIFFCTRL[0]
CELL[3].IMUX_IMUX_DELAY[3]	GTX[0].TXDEEMPH
CELL[3].IMUX_IMUX_DELAY[5]	GTX[0].TXDIFFCTRL[2]
CELL[3].IMUX_IMUX_DELAY[9]	GTX[0].TXPREEMPHASIS[3]
CELL[3].IMUX_IMUX_DELAY[11]	GTX[0].LOOPBACK[1]
CELL[3].IMUX_IMUX_DELAY[12]	GTX[0].RXDLYALIGNTESTMODEENB
CELL[3].IMUX_IMUX_DELAY[13]	GTX[0].TXSWING
CELL[3].IMUX_IMUX_DELAY[16]	GTX[0].TXBUFDIFFCTRL[1]
CELL[3].IMUX_IMUX_DELAY[17]	GTX[0].TXPREEMPHASIS[2]
CELL[3].IMUX_IMUX_DELAY[18]	GTX[0].TXBUFDIFFCTRL[2]
CELL[3].IMUX_IMUX_DELAY[19]	GTX[0].TXPREEMPHASIS[1]
CELL[3].IMUX_IMUX_DELAY[21]	GTX[0].TXDIFFCTRL[0]
CELL[3].IMUX_IMUX_DELAY[22]	GTX[0].RXPLLREFSELDY[1]
CELL[3].IMUX_IMUX_DELAY[24]	GTX[0].LOOPBACK[0]
CELL[3].IMUX_IMUX_DELAY[25]	GTX[0].RXDLYALIGNFORCEROTATEB
CELL[3].IMUX_IMUX_DELAY[26]	GTX[0].TXPREEMPHASIS[0]
CELL[3].IMUX_IMUX_DELAY[27]	GTX[0].LOOPBACK[2]
CELL[3].IMUX_IMUX_DELAY[28]	GTX[0].RXDLYALIGNMONENB
CELL[3].IMUX_IMUX_DELAY[29]	GTX[0].RXDLYALIGNSWPPRECURB
CELL[3].IMUX_IMUX_DELAY[30]	GTX[0].TXDIFFCTRL[3]
CELL[3].IMUX_IMUX_DELAY[32]	GTX[0].RXCHBONDI[0]
CELL[3].IMUX_IMUX_DELAY[33]	GTX[0].RXCHBONDI[1]
CELL[3].IMUX_IMUX_DELAY[34]	GTX[0].RXCHBONDI[2]
CELL[3].IMUX_IMUX_DELAY[35]	GTX[0].RXCHBONDI[3]
CELL[3].IMUX_IMUX_DELAY[36]	GTX[0].RXCOMMADETUSE
CELL[3].IMUX_IMUX_DELAY[37]	GTX[0].RXPLLREFSELDY[0]
CELL[3].IMUX_IMUX_DELAY[38]	GTX[0].TXDIFFCTRL[1]
CELL[3].IMUX_IMUX_DELAY[39]	GTX[0].RXPLLREFSELDY[2]
CELL[3].OUT_BEL[0]	GTX[0].RXDISPERR[2]
CELL[3].OUT_BEL[1]	GTX[0].RXRUNDISP[3]
CELL[3].OUT_BEL[2]	GTX[0].RXCHARISCOMMA[1]
CELL[3].OUT_BEL[3]	GTX[0].RXNOTINTABLE[3]
CELL[3].OUT_BEL[4]	GTX[0].RXDISPERR[0]
CELL[3].OUT_BEL[5]	GTX[0].RXRUNDISP[1]
CELL[3].OUT_BEL[7]	GTX[0].RXNOTINTABLE[1]
CELL[3].OUT_BEL[8]	GTX[0].RXDISPERR[1]
CELL[3].OUT_BEL[9]	GTX[0].RXRUNDISP[0]
CELL[3].OUT_BEL[11]	GTX[0].RXNOTINTABLE[0]
CELL[3].OUT_BEL[13]	GTX[0].RXCHANISALIGNED
CELL[3].OUT_BEL[14]	GTX[0].RXCHARISCOMMA[0]
CELL[3].OUT_BEL[15]	GTX[0].RXNOTINTABLE[2]
CELL[3].OUT_BEL[16]	GTX[0].RXCHARISK[0]
CELL[3].OUT_BEL[19]	GTX[0].RXRUNDISP[2]
CELL[3].OUT_BEL[22]	GTX[0].RXDISPERR[3]
CELL[4].IMUX_CLK[1]	GTX[0].SCANCLK
CELL[4].IMUX_IMUX_DELAY[8]	GTX[0].DFETAP1[0]
CELL[4].IMUX_IMUX_DELAY[9]	GTX[0].TXDETECTRX
CELL[4].IMUX_IMUX_DELAY[10]	GTX[0].DFETAP1[1]
CELL[4].IMUX_IMUX_DELAY[11]	GTX[0].TXMARGIN[0]
CELL[4].IMUX_IMUX_DELAY[13]	GTX[0].RXPOWERDOWN[0]
CELL[4].IMUX_IMUX_DELAY[14]	GTX[0].DFETAP1[2]
CELL[4].IMUX_IMUX_DELAY[15]	GTX[0].DFETAP1[3]
CELL[4].IMUX_IMUX_DELAY[16]	GTX[0].DFECLKDLYADJ[5]
CELL[4].IMUX_IMUX_DELAY[17]	GTX[0].DFECLKDLYADJ[4]
CELL[4].IMUX_IMUX_DELAY[18]	GTX[0].DFECLKDLYADJ[2]
CELL[4].IMUX_IMUX_DELAY[19]	GTX[0].DFECLKDLYADJ[1]
CELL[4].IMUX_IMUX_DELAY[21]	GTX[0].RXPOWERDOWN[1]
CELL[4].IMUX_IMUX_DELAY[24]	GTX[0].DFETAP2[0]
CELL[4].IMUX_IMUX_DELAY[25]	GTX[0].DFETAP2[1]
CELL[4].IMUX_IMUX_DELAY[26]	GTX[0].TXMARGIN[1]
CELL[4].IMUX_IMUX_DELAY[28]	GTX[0].TXPOWERDOWN[0]
CELL[4].IMUX_IMUX_DELAY[29]	GTX[0].DFEDLYOVRD
CELL[4].IMUX_IMUX_DELAY[30]	GTX[0].DFETAP2[2]
CELL[4].IMUX_IMUX_DELAY[31]	GTX[0].DFETAP2[3]
CELL[4].IMUX_IMUX_DELAY[32]	GTX[0].TXELECIDLE
CELL[4].IMUX_IMUX_DELAY[33]	GTX[0].DFECLKDLYADJ[3]
CELL[4].IMUX_IMUX_DELAY[35]	GTX[0].DFECLKDLYADJ[0]
CELL[4].IMUX_IMUX_DELAY[36]	GTX[0].TXPOWERDOWN[1]
CELL[4].IMUX_IMUX_DELAY[37]	GTX[0].DFETAPOVRD
CELL[4].IMUX_IMUX_DELAY[38]	GTX[0].DFETAP1[4]
CELL[4].IMUX_IMUX_DELAY[39]	GTX[0].DFETAP2[4]
CELL[4].OUT_BEL[0]	GTX[0].MGTREFCLKFAB[0]
CELL[4].OUT_BEL[3]	GTX[0].RXBUFSTATUS[2]
CELL[4].OUT_BEL[4]	GTX[0].SCANOUT[1]
CELL[4].OUT_BEL[5]	GTX[0].RXPLLLKDET
CELL[4].OUT_BEL[6]	GTX[0].RXBUFSTATUS[0]
CELL[4].OUT_BEL[7]	GTX[0].RXBUFSTATUS[1]
CELL[4].OUT_BEL[8]	GTX[0].PHYSTATUS
CELL[4].OUT_BEL[10]	GTX[0].RXCHBONDO[1]
CELL[4].OUT_BEL[11]	GTX[0].RXCHBONDO[2]
CELL[4].OUT_BEL[12]	GTX[0].MGTREFCLKFAB[1]
CELL[4].OUT_BEL[13]	GTX[0].RXSTATUS[2]
CELL[4].OUT_BEL[14]	GTX[0].RXSTATUS[0]
CELL[4].OUT_BEL[15]	GTX[0].RXCHBONDO[3]
CELL[4].OUT_BEL[16]	GTX[0].RXSTATUS[1]
CELL[4].OUT_BEL[17]	GTX[0].RXCHBONDO[0]
CELL[4].OUT_BEL[18]	GTX[0].SCANOUT[0]
CELL[4].OUT_BEL[22]	GTX[0].RXOVERSAMPLEERR
CELL[5].IMUX_CLK[1]	GTX[0].TSTCLK[1]
CELL[5].IMUX_CTRL[1]	GTX[0].PLLTXRESET
CELL[5].IMUX_IMUX_DELAY[2]	GTX[0].TXDLYALIGNUPDSW
CELL[5].IMUX_IMUX_DELAY[8]	GTX[0].TXHEADER[0]
CELL[5].IMUX_IMUX_DELAY[9]	GTX[0].TXPOLARITY
CELL[5].IMUX_IMUX_DELAY[10]	GTX[0].RXDLYALIGNUPDSW
CELL[5].IMUX_IMUX_DELAY[11]	GTX[0].TXBYPASS8B10B[0]
CELL[5].IMUX_IMUX_DELAY[13]	GTX[0].TXDLYALIGNRESET
CELL[5].IMUX_IMUX_DELAY[14]	GTX[0].RXDLYALIGNDISABLE
CELL[5].IMUX_IMUX_DELAY[15]	GTX[0].TXMARGIN[2]
CELL[5].IMUX_IMUX_DELAY[16]	GTX[0].TXHEADER[1]
CELL[5].IMUX_IMUX_DELAY[17]	GTX[0].TXINHIBIT
CELL[5].IMUX_IMUX_DELAY[18]	GTX[0].TXPMASETPHASE
CELL[5].IMUX_IMUX_DELAY[19]	GTX[0].TXBYPASS8B10B[3]
CELL[5].IMUX_IMUX_DELAY[21]	GTX[0].TXCHARDISPMODE[3]
CELL[5].IMUX_IMUX_DELAY[22]	GTX[0].TXCHARDISPVAL[3]
CELL[5].IMUX_IMUX_DELAY[23]	GTX[0].TXCHARISK[3]
CELL[5].IMUX_IMUX_DELAY[25]	GTX[0].TXDLYALIGNOVERRIDE
CELL[5].IMUX_IMUX_DELAY[26]	GTX[0].TXCHARISK[0]
CELL[5].IMUX_IMUX_DELAY[27]	GTX[0].TXBYPASS8B10B[1]
CELL[5].IMUX_IMUX_DELAY[28]	GTX[0].TXCHARDISPMODE[1]
CELL[5].IMUX_IMUX_DELAY[29]	GTX[0].RXDLYALIGNRESET
CELL[5].IMUX_IMUX_DELAY[30]	GTX[0].TXCHARDISPVAL[1]
CELL[5].IMUX_IMUX_DELAY[32]	GTX[0].TXHEADER[2]
CELL[5].IMUX_IMUX_DELAY[33]	GTX[0].RXDLYALIGNOVERRIDE
CELL[5].IMUX_IMUX_DELAY[34]	GTX[0].TXCHARDISPMODE[0]
CELL[5].IMUX_IMUX_DELAY[35]	GTX[0].TXBYPASS8B10B[2]
CELL[5].IMUX_IMUX_DELAY[36]	GTX[0].TXCHARISK[1]
CELL[5].IMUX_IMUX_DELAY[37]	GTX[0].TXCHARDISPMODE[2]
CELL[5].IMUX_IMUX_DELAY[38]	GTX[0].TXCHARDISPVAL[2]
CELL[5].IMUX_IMUX_DELAY[39]	GTX[0].TXCHARISK[2]
CELL[5].IMUX_IMUX_DELAY[44]	GTX[0].TXCHARDISPVAL[0]
CELL[5].IMUX_IMUX_DELAY[46]	GTX[0].TXDLYALIGNDISABLE
CELL[5].OUT_BEL[0]	GTX[0].RXDLYALIGNMONITOR[7]
CELL[5].OUT_BEL[1]	GTX[0].RXSTARTOFSEQ
CELL[5].OUT_BEL[2]	GTX[0].RXPRBSERR
CELL[5].OUT_BEL[3]	GTX[0].RXELECIDLE
CELL[5].OUT_BEL[4]	GTX[0].RXVALID
CELL[5].OUT_BEL[5]	GTX[0].RXRECCLKPCS
CELL[5].OUT_BEL[6]	GTX[0].RXCLKCORCNT[2]
CELL[5].OUT_BEL[7]	GTX[0].RXDLYALIGNMONITOR[2]
CELL[5].OUT_BEL[8]	GTX[0].RXCLKCORCNT[0]
CELL[5].OUT_BEL[9]	GTX[0].RXCLKCORCNT[1]
CELL[5].OUT_BEL[10]	GTX[0].RXHEADER[0]
CELL[5].OUT_BEL[11]	GTX[0].RXHEADERVALID
CELL[5].OUT_BEL[12]	GTX[0].RXCOMMADET
CELL[5].OUT_BEL[14]	GTX[0].RXCHANBONDSEQ
CELL[5].OUT_BEL[15]	GTX[0].RXDLYALIGNMONITOR[1]
CELL[5].OUT_BEL[16]	GTX[0].RXHEADER[1]
CELL[5].OUT_BEL[17]	GTX[0].RXHEADER[2]
CELL[5].OUT_BEL[18]	GTX[0].RXDLYALIGNMONITOR[6]
CELL[5].OUT_BEL[19]	GTX[0].RXDLYALIGNMONITOR[5]
CELL[5].OUT_BEL[20]	GTX[0].RXDLYALIGNMONITOR[3]
CELL[5].OUT_BEL[21]	GTX[0].RXDLYALIGNMONITOR[0]
CELL[5].OUT_BEL[22]	GTX[0].RXRESETDONE
CELL[5].OUT_BEL[23]	GTX[0].RXDLYALIGNMONITOR[4]
CELL[6].IMUX_CLK[0]	GTX[0].TXUSRCLK
CELL[6].IMUX_CLK[1]	GTX[0].TXUSRCLK2
CELL[6].IMUX_CTRL[0]	GTX[0].TXRESET
CELL[6].IMUX_CTRL[1]	GTX[0].GTXTXRESET
CELL[6].IMUX_IMUX_DELAY[3]	GTX[0].TXDATA[12]
CELL[6].IMUX_IMUX_DELAY[5]	GTX[0].TXDATA[14]
CELL[6].IMUX_IMUX_DELAY[8]	GTX[0].TXSEQUENCE[3]
CELL[6].IMUX_IMUX_DELAY[9]	GTX[0].DFETAP3[1]
CELL[6].IMUX_IMUX_DELAY[10]	GTX[0].DFETAP3[0]
CELL[6].IMUX_IMUX_DELAY[11]	GTX[0].TXSEQUENCE[0]
CELL[6].IMUX_IMUX_DELAY[12]	GTX[0].DFETAP3[2]
CELL[6].IMUX_IMUX_DELAY[13]	GTX[0].TXDATA[15]
CELL[6].IMUX_IMUX_DELAY[15]	GTX[0].TXENPRBSTST[2]
CELL[6].IMUX_IMUX_DELAY[17]	GTX[0].DFETAP3[3]
CELL[6].IMUX_IMUX_DELAY[19]	GTX[0].TXSEQUENCE[1]
CELL[6].IMUX_IMUX_DELAY[20]	GTX[0].DFETAP4[3]
CELL[6].IMUX_IMUX_DELAY[22]	GTX[0].TXSEQUENCE[5]
CELL[6].IMUX_IMUX_DELAY[23]	GTX[0].TXENPRBSTST[1]
CELL[6].IMUX_IMUX_DELAY[24]	GTX[0].TXSEQUENCE[4]
CELL[6].IMUX_IMUX_DELAY[25]	GTX[0].DFETAP4[1]
CELL[6].IMUX_IMUX_DELAY[26]	GTX[0].DFETAP4[0]
CELL[6].IMUX_IMUX_DELAY[28]	GTX[0].DFETAP4[2]
CELL[6].IMUX_IMUX_DELAY[30]	GTX[0].TXDATA[13]
CELL[6].IMUX_IMUX_DELAY[32]	GTX[0].GATERXELECIDLE
CELL[6].IMUX_IMUX_DELAY[33]	GTX[0].TXRATE[1]
CELL[6].IMUX_IMUX_DELAY[34]	GTX[0].TXRATE[0]
CELL[6].IMUX_IMUX_DELAY[35]	GTX[0].TXSEQUENCE[2]
CELL[6].IMUX_IMUX_DELAY[37]	GTX[0].IGNORESIGDET
CELL[6].IMUX_IMUX_DELAY[38]	GTX[0].TXSEQUENCE[6]
CELL[6].IMUX_IMUX_DELAY[39]	GTX[0].TXENPRBSTST[0]
CELL[6].IMUX_IMUX_DELAY[41]	GTX[0].RXRATE[1]
CELL[6].IMUX_IMUX_DELAY[42]	GTX[0].RXRATE[0]
CELL[6].OUT_BEL[1]	GTX[0].DFECLKDLYADJMON[1]
CELL[6].OUT_BEL[2]	GTX[0].DFECLKDLYADJMON[2]
CELL[6].OUT_BEL[3]	GTX[0].DFECLKDLYADJMON[5]
CELL[6].OUT_BEL[4]	GTX[0].TXGEARBOXREADY
CELL[6].OUT_BEL[5]	GTX[0].DFECLKDLYADJMON[0]
CELL[6].OUT_BEL[6]	GTX[0].DFECLKDLYADJMON[3]
CELL[6].OUT_BEL[7]	GTX[0].DFECLKDLYADJMON[4]
CELL[6].OUT_BEL[8]	GTX[0].TXOUTCLKPCS
CELL[6].OUT_BEL[10]	GTX[0].DFEEYEDACMON[2]
CELL[6].OUT_BEL[11]	GTX[0].DFEEYEDACMON[3]
CELL[6].OUT_BEL[13]	GTX[0].DFEEYEDACMON[0]
CELL[6].OUT_BEL[14]	GTX[0].DFEEYEDACMON[1]
CELL[6].OUT_BEL[15]	GTX[0].DFEEYEDACMON[4]
CELL[6].OUT_BEL[18]	GTX[0].DFESENSCAL[1]
CELL[6].OUT_BEL[19]	GTX[0].DFESENSCAL[0]
CELL[6].OUT_BEL[20]	GTX[0].RXRATEDONE
CELL[6].OUT_BEL[22]	GTX[0].DFESENSCAL[2]
CELL[6].OUT_BEL[23]	GTX[0].TXRATEDONE
CELL[7].IMUX_CLK[0]	GTX[0].GREFCLKTX
CELL[7].IMUX_IMUX_DELAY[9]	GTX[0].TXDLYALIGNFORCEROTATEB
CELL[7].IMUX_IMUX_DELAY[10]	GTX[0].TXCOMWAKE
CELL[7].IMUX_IMUX_DELAY[11]	GTX[0].TXDLYALIGNMONENB
CELL[7].IMUX_IMUX_DELAY[12]	GTX[0].TXPLLLKDETEN
CELL[7].IMUX_IMUX_DELAY[13]	GTX[0].TXDATA[10]
CELL[7].IMUX_IMUX_DELAY[14]	GTX[0].TXSTARTSEQ
CELL[7].IMUX_IMUX_DELAY[15]	GTX[0].TXDATA[8]
CELL[7].IMUX_IMUX_DELAY[18]	GTX[0].TXCOMINIT
CELL[7].IMUX_IMUX_DELAY[19]	GTX[0].TXCOMSAS
CELL[7].IMUX_IMUX_DELAY[21]	GTX[0].TXDATA[9]
CELL[7].IMUX_IMUX_DELAY[22]	GTX[0].TXENC8B10BUSE
CELL[7].IMUX_IMUX_DELAY[24]	GTX[0].TXDATA[23]
CELL[7].IMUX_IMUX_DELAY[25]	GTX[0].TXDATA[22]
CELL[7].IMUX_IMUX_DELAY[26]	GTX[0].TXDATA[7]
CELL[7].IMUX_IMUX_DELAY[27]	GTX[0].TXDATA[20]
CELL[7].IMUX_IMUX_DELAY[28]	GTX[0].TXDATA[21]
CELL[7].IMUX_IMUX_DELAY[29]	GTX[0].TXPLLPOWERDOWN
CELL[7].IMUX_IMUX_DELAY[30]	GTX[0].TXDLYALIGNTESTMODEENB
CELL[7].IMUX_IMUX_DELAY[32]	GTX[0].TXDATA[31]
CELL[7].IMUX_IMUX_DELAY[33]	GTX[0].TXDATA[30]
CELL[7].IMUX_IMUX_DELAY[34]	GTX[0].TXDATA[6]
CELL[7].IMUX_IMUX_DELAY[35]	GTX[0].TXDATA[28]
CELL[7].IMUX_IMUX_DELAY[36]	GTX[0].TXDATA[29]
CELL[7].IMUX_IMUX_DELAY[37]	GTX[0].TXPLLREFSELDY[0]
CELL[7].IMUX_IMUX_DELAY[38]	GTX[0].TXPLLREFSELDY[1]
CELL[7].IMUX_IMUX_DELAY[39]	GTX[0].TXPLLREFSELDY[2]
CELL[7].IMUX_IMUX_DELAY[40]	GTX[0].TXDATA[11]
CELL[7].OUT_BEL[0]	GTX[0].TXDLYALIGNMONITOR[7]
CELL[7].OUT_BEL[1]	GTX[0].DFETAP2MONITOR[0]
CELL[7].OUT_BEL[2]	GTX[0].DFETAP2MONITOR[1]
CELL[7].OUT_BEL[3]	GTX[0].DFETAP2MONITOR[4]
CELL[7].OUT_BEL[4]	GTX[0].TXDLYALIGNMONITOR[2]
CELL[7].OUT_BEL[5]	GTX[0].TXBUFSTATUS[0]
CELL[7].OUT_BEL[6]	GTX[0].DFETAP2MONITOR[2]
CELL[7].OUT_BEL[7]	GTX[0].DFETAP2MONITOR[3]
CELL[7].OUT_BEL[8]	GTX[0].DFETAP4MONITOR[1]
CELL[7].OUT_BEL[9]	GTX[0].DFETAP4MONITOR[2]
CELL[7].OUT_BEL[10]	GTX[0].TXKERR[1]
CELL[7].OUT_BEL[11]	GTX[0].TXKERR[2]
CELL[7].OUT_BEL[12]	GTX[0].DFETAP4MONITOR[0]
CELL[7].OUT_BEL[13]	GTX[0].DFETAP4MONITOR[3]
CELL[7].OUT_BEL[14]	GTX[0].TXKERR[0]
CELL[7].OUT_BEL[15]	GTX[0].TXKERR[3]
CELL[7].OUT_BEL[16]	GTX[0].TXDLYALIGNMONITOR[1]
CELL[7].OUT_BEL[17]	GTX[0].TXBUFSTATUS[1]
CELL[7].OUT_BEL[18]	GTX[0].TXDLYALIGNMONITOR[6]
CELL[7].OUT_BEL[19]	GTX[0].TXDLYALIGNMONITOR[5]
CELL[7].OUT_BEL[20]	GTX[0].TXDLYALIGNMONITOR[3]
CELL[7].OUT_BEL[21]	GTX[0].TXDLYALIGNMONITOR[0]
CELL[7].OUT_BEL[22]	GTX[0].TXRESETDONE
CELL[7].OUT_BEL[23]	GTX[0].TXDLYALIGNMONITOR[4]
CELL[8].IMUX_IMUX_DELAY[8]	GTX[0].DWE
CELL[8].IMUX_IMUX_DELAY[9]	GTX[0].SCANIN[4]
CELL[8].IMUX_IMUX_DELAY[10]	GTX[0].TXPOSTEMPHASIS[0]
CELL[8].IMUX_IMUX_DELAY[12]	GTX[0].TXPOSTEMPHASIS[2]
CELL[8].IMUX_IMUX_DELAY[13]	GTX[0].TXPRBSFORCEERR
CELL[8].IMUX_IMUX_DELAY[15]	GTX[0].TXPDOWNASYNCH
CELL[8].IMUX_IMUX_DELAY[16]	GTX[0].DEN
CELL[8].IMUX_IMUX_DELAY[17]	GTX[0].TXENPMAPHASEALIGN
CELL[8].IMUX_IMUX_DELAY[18]	GTX[0].TXPOSTEMPHASIS[1]
CELL[8].IMUX_IMUX_DELAY[19]	GTX[0].TXDATA[25]
CELL[8].IMUX_IMUX_DELAY[20]	GTX[0].TXPOSTEMPHASIS[3]
CELL[8].IMUX_IMUX_DELAY[22]	GTX[0].TXPOSTEMPHASIS[4]
CELL[8].IMUX_IMUX_DELAY[25]	GTX[0].SCANIN[1]
CELL[8].IMUX_IMUX_DELAY[26]	GTX[0].TXDATA[4]
CELL[8].IMUX_IMUX_DELAY[27]	GTX[0].TXDATA[19]
CELL[8].IMUX_IMUX_DELAY[28]	GTX[0].TXDATA[2]
CELL[8].IMUX_IMUX_DELAY[29]	GTX[0].TXDATA[18]
CELL[8].IMUX_IMUX_DELAY[30]	GTX[0].TXDATA[17]
CELL[8].IMUX_IMUX_DELAY[31]	GTX[0].TXDATA[16]
CELL[8].IMUX_IMUX_DELAY[32]	GTX[0].TXDATA[3]
CELL[8].IMUX_IMUX_DELAY[33]	GTX[0].SCANIN[0]
CELL[8].IMUX_IMUX_DELAY[34]	GTX[0].TXDATA[5]
CELL[8].IMUX_IMUX_DELAY[35]	GTX[0].TXDATA[27]
CELL[8].IMUX_IMUX_DELAY[36]	GTX[0].TXDATA[1]
CELL[8].IMUX_IMUX_DELAY[37]	GTX[0].TXDATA[26]
CELL[8].IMUX_IMUX_DELAY[38]	GTX[0].TXDATA[0]
CELL[8].IMUX_IMUX_DELAY[39]	GTX[0].TXDATA[24]
CELL[8].OUT_BEL[0]	GTX[0].DRDY
CELL[8].OUT_BEL[1]	GTX[0].DFETAP1MONITOR[0]
CELL[8].OUT_BEL[2]	GTX[0].DFETAP1MONITOR[1]
CELL[8].OUT_BEL[3]	GTX[0].DFETAP1MONITOR[4]
CELL[8].OUT_BEL[5]	GTX[0].TXPLLLKDET
CELL[8].OUT_BEL[6]	GTX[0].DFETAP1MONITOR[2]
CELL[8].OUT_BEL[7]	GTX[0].DFETAP1MONITOR[3]
CELL[8].OUT_BEL[8]	GTX[0].DFETAP3MONITOR[1]
CELL[8].OUT_BEL[9]	GTX[0].DFETAP3MONITOR[2]
CELL[8].OUT_BEL[10]	GTX[0].TXRUNDISP[1]
CELL[8].OUT_BEL[11]	GTX[0].TXRUNDISP[2]
CELL[8].OUT_BEL[12]	GTX[0].DFETAP3MONITOR[0]
CELL[8].OUT_BEL[13]	GTX[0].DFETAP3MONITOR[3]
CELL[8].OUT_BEL[14]	GTX[0].TXRUNDISP[0]
CELL[8].OUT_BEL[15]	GTX[0].TXRUNDISP[3]
CELL[8].OUT_BEL[18]	GTX[0].COMFINISH
CELL[9].IMUX_CLK[0]	GTX[0].DCLK
CELL[9].IMUX_IMUX_DELAY[8]	GTX[0].DI[0]
CELL[9].IMUX_IMUX_DELAY[9]	GTX[0].DI[1]
CELL[9].IMUX_IMUX_DELAY[10]	GTX[0].DI[2]
CELL[9].IMUX_IMUX_DELAY[11]	GTX[0].DI[3]
CELL[9].IMUX_IMUX_DELAY[12]	GTX[0].DI[4]
CELL[9].IMUX_IMUX_DELAY[13]	GTX[0].DI[5]
CELL[9].IMUX_IMUX_DELAY[14]	GTX[0].DI[6]
CELL[9].IMUX_IMUX_DELAY[15]	GTX[0].DI[7]
CELL[9].IMUX_IMUX_DELAY[16]	GTX[0].DI[8]
CELL[9].IMUX_IMUX_DELAY[17]	GTX[0].DI[9]
CELL[9].IMUX_IMUX_DELAY[18]	GTX[0].DI[10]
CELL[9].IMUX_IMUX_DELAY[19]	GTX[0].DI[11]
CELL[9].IMUX_IMUX_DELAY[20]	GTX[0].DI[12]
CELL[9].IMUX_IMUX_DELAY[21]	GTX[0].DI[13]
CELL[9].IMUX_IMUX_DELAY[22]	GTX[0].DI[14]
CELL[9].IMUX_IMUX_DELAY[23]	GTX[0].DI[15]
CELL[9].IMUX_IMUX_DELAY[32]	GTX[0].DADDR[0]
CELL[9].IMUX_IMUX_DELAY[33]	GTX[0].DADDR[1]
CELL[9].IMUX_IMUX_DELAY[34]	GTX[0].DADDR[2]
CELL[9].IMUX_IMUX_DELAY[35]	GTX[0].DADDR[3]
CELL[9].IMUX_IMUX_DELAY[36]	GTX[0].DADDR[4]
CELL[9].IMUX_IMUX_DELAY[37]	GTX[0].DADDR[5]
CELL[9].IMUX_IMUX_DELAY[38]	GTX[0].DADDR[6]
CELL[9].IMUX_IMUX_DELAY[39]	GTX[0].DADDR[7]
CELL[9].OUT_BEL[0]	GTX[0].DRPDO[7]
CELL[9].OUT_BEL[1]	GTX[0].DRPDO[4]
CELL[9].OUT_BEL[2]	GTX[0].DRPDO[3]
CELL[9].OUT_BEL[3]	GTX[0].DRPDO[0]
CELL[9].OUT_BEL[4]	GTX[0].DRPDO[6]
CELL[9].OUT_BEL[5]	GTX[0].DRPDO[5]
CELL[9].OUT_BEL[6]	GTX[0].DRPDO[2]
CELL[9].OUT_BEL[7]	GTX[0].DRPDO[1]
CELL[9].OUT_BEL[8]	GTX[0].DRPDO[14]
CELL[9].OUT_BEL[9]	GTX[0].DRPDO[13]
CELL[9].OUT_BEL[10]	GTX[0].DRPDO[10]
CELL[9].OUT_BEL[11]	GTX[0].DRPDO[9]
CELL[9].OUT_BEL[12]	GTX[0].DRPDO[15]
CELL[9].OUT_BEL[13]	GTX[0].DRPDO[12]
CELL[9].OUT_BEL[14]	GTX[0].DRPDO[11]
CELL[9].OUT_BEL[15]	GTX[0].DRPDO[8]
CELL[10].IMUX_CTRL[1]	GTX[1].PRBSCNTRESET
CELL[10].IMUX_IMUX_DELAY[0]	GTX[1].TSTIN[17]
CELL[10].IMUX_IMUX_DELAY[1]	GTX[1].TSTIN[18]
CELL[10].IMUX_IMUX_DELAY[8]	GTX[1].TSTIN[9]
CELL[10].IMUX_IMUX_DELAY[9]	GTX[1].TSTIN[7]
CELL[10].IMUX_IMUX_DELAY[10]	GTX[1].TSTIN[5]
CELL[10].IMUX_IMUX_DELAY[11]	GTX[1].TSTIN[3]
CELL[10].IMUX_IMUX_DELAY[13]	GTX[1].TSTIN[12]
CELL[10].IMUX_IMUX_DELAY[14]	GTX[1].TSTIN[1]
CELL[10].IMUX_IMUX_DELAY[16]	GTX[1].TSTIN[15]
CELL[10].IMUX_IMUX_DELAY[17]	GTX[1].TSTPWRDNOVRD
CELL[10].IMUX_IMUX_DELAY[18]	GTX[1].TSTPWRDN[1]
CELL[10].IMUX_IMUX_DELAY[19]	GTX[1].TSTPWRDN[3]
CELL[10].IMUX_IMUX_DELAY[21]	GTX[1].TSTIN[11]
CELL[10].IMUX_IMUX_DELAY[22]	GTX[1].SCANIN[3]
CELL[10].IMUX_IMUX_DELAY[24]	GTX[1].TSTIN[8]
CELL[10].IMUX_IMUX_DELAY[25]	GTX[1].TSTIN[6]
CELL[10].IMUX_IMUX_DELAY[26]	GTX[1].TSTIN[4]
CELL[10].IMUX_IMUX_DELAY[27]	GTX[1].TSTIN[2]
CELL[10].IMUX_IMUX_DELAY[28]	GTX[1].TSTIN[13]
CELL[10].IMUX_IMUX_DELAY[29]	GTX[1].SCANMODEB
CELL[10].IMUX_IMUX_DELAY[30]	GTX[1].TSTIN[0]
CELL[10].IMUX_IMUX_DELAY[31]	GTX[1].TSTIN[10]
CELL[10].IMUX_IMUX_DELAY[32]	GTX[1].TSTIN[14]
CELL[10].IMUX_IMUX_DELAY[33]	GTX[1].TSTPWRDN[0]
CELL[10].IMUX_IMUX_DELAY[34]	GTX[1].TSTPWRDN[2]
CELL[10].IMUX_IMUX_DELAY[35]	GTX[1].TSTPWRDN[4]
CELL[10].IMUX_IMUX_DELAY[37]	GTX[1].SCANENB
CELL[10].IMUX_IMUX_DELAY[38]	GTX[1].SCANIN[2]
CELL[10].IMUX_IMUX_DELAY[40]	GTX[1].TSTIN[16]
CELL[10].IMUX_IMUX_DELAY[41]	GTX[1].TSTIN[19]
CELL[10].OUT_BEL[0]	GTX[1].RXDATA[18]
CELL[10].OUT_BEL[1]	GTX[1].RXDATA[4]
CELL[10].OUT_BEL[2]	GTX[1].RXDATA[3]
CELL[10].OUT_BEL[3]	GTX[1].RXDATA[17]
CELL[10].OUT_BEL[4]	GTX[1].RXDATA[0]
CELL[10].OUT_BEL[5]	GTX[1].RXDATA[5]
CELL[10].OUT_BEL[6]	GTX[1].RXDATA[2]
CELL[10].OUT_BEL[7]	GTX[1].RXDATA[1]
CELL[10].OUT_BEL[8]	GTX[1].SCANOUT[4]
CELL[10].OUT_BEL[13]	GTX[1].SCANOUT[3]
CELL[10].OUT_BEL[15]	GTX[1].RXDATA[16]
CELL[10].OUT_BEL[16]	GTX[1].RXDATA[22]
CELL[10].OUT_BEL[17]	GTX[1].RXDATA[21]
CELL[10].OUT_BEL[18]	GTX[1].RXDATA[20]
CELL[10].OUT_BEL[20]	GTX[1].RXDATA[23]
CELL[10].OUT_BEL[22]	GTX[1].RXDATA[19]
CELL[10].OUT_BEL[23]	GTX[1].SCANOUT[2]
CELL[11].IMUX_CTRL[0]	GTX[1].GTXRXRESET
CELL[11].IMUX_CTRL[1]	GTX[1].RXCDRRESET
CELL[11].IMUX_IMUX_DELAY[9]	GTX[1].RXSLIDE
CELL[11].IMUX_IMUX_DELAY[11]	GTX[1].RXPMASETPHASE
CELL[11].IMUX_IMUX_DELAY[12]	GTX[1].RXGEARBOXSLIP
CELL[11].IMUX_IMUX_DELAY[14]	GTX[1].RXEQMIX[0]
CELL[11].IMUX_IMUX_DELAY[15]	GTX[1].RXEQMIX[1]
CELL[11].IMUX_IMUX_DELAY[18]	GTX[1].RXENPRBSTST[2]
CELL[11].IMUX_IMUX_DELAY[19]	GTX[1].RXEQMIX[9]
CELL[11].IMUX_IMUX_DELAY[20]	GTX[1].RXEQMIX[7]
CELL[11].IMUX_IMUX_DELAY[21]	GTX[1].RXEQMIX[5]
CELL[11].IMUX_IMUX_DELAY[22]	GTX[1].RXEQMIX[3]
CELL[11].IMUX_IMUX_DELAY[24]	GTX[1].RXBUFWE
CELL[11].IMUX_IMUX_DELAY[26]	GTX[1].RXPOLARITY
CELL[11].IMUX_IMUX_DELAY[27]	GTX[1].RXEQMIX[8]
CELL[11].IMUX_IMUX_DELAY[28]	GTX[1].RXEQMIX[6]
CELL[11].IMUX_IMUX_DELAY[29]	GTX[1].RXEQMIX[4]
CELL[11].IMUX_IMUX_DELAY[30]	GTX[1].RXEQMIX[2]
CELL[11].IMUX_IMUX_DELAY[32]	GTX[1].RXENSAMPLEALIGN
CELL[11].IMUX_IMUX_DELAY[33]	GTX[1].RXENPRBSTST[0]
CELL[11].IMUX_IMUX_DELAY[34]	GTX[1].RXENPRBSTST[1]
CELL[11].IMUX_IMUX_DELAY[35]	GTX[1].RXENPMAPHASEALIGN
CELL[11].IMUX_IMUX_DELAY[36]	GTX[1].RXENMCOMMAALIGN
CELL[11].IMUX_IMUX_DELAY[37]	GTX[1].RXENPCOMMAALIGN
CELL[11].IMUX_IMUX_DELAY[38]	GTX[1].RXENCHANSYNC
CELL[11].IMUX_IMUX_DELAY[39]	GTX[1].RXDEC8B10BUSE
CELL[11].OUT_BEL[0]	GTX[1].RXDATA[24]
CELL[11].OUT_BEL[1]	GTX[1].RXDATA[6]
CELL[11].OUT_BEL[2]	GTX[1].RXDATA[11]
CELL[11].OUT_BEL[3]	GTX[1].RXDATA[31]
CELL[11].OUT_BEL[4]	GTX[1].RXDATA[8]
CELL[11].OUT_BEL[5]	GTX[1].RXDATA[7]
CELL[11].OUT_BEL[6]	GTX[1].RXDATA[10]
CELL[11].OUT_BEL[7]	GTX[1].RXDATA[9]
CELL[11].OUT_BEL[8]	GTX[1].TSTOUT[8]
CELL[11].OUT_BEL[9]	GTX[1].RXDATA[27]
CELL[11].OUT_BEL[10]	GTX[1].TSTOUT[2]
CELL[11].OUT_BEL[11]	GTX[1].RXDATA[29]
CELL[11].OUT_BEL[12]	GTX[1].TSTOUT[9]
CELL[11].OUT_BEL[13]	GTX[1].TSTOUT[6]
CELL[11].OUT_BEL[14]	GTX[1].TSTOUT[4]
CELL[11].OUT_BEL[15]	GTX[1].RXDATA[30]
CELL[11].OUT_BEL[16]	GTX[1].RXDATA[28]
CELL[11].OUT_BEL[17]	GTX[1].TSTOUT[1]
CELL[11].OUT_BEL[18]	GTX[1].RXDATA[26]
CELL[11].OUT_BEL[19]	GTX[1].TSTOUT[7]
CELL[11].OUT_BEL[20]	GTX[1].TSTOUT[3]
CELL[11].OUT_BEL[21]	GTX[1].TSTOUT[0]
CELL[11].OUT_BEL[22]	GTX[1].RXDATA[25]
CELL[11].OUT_BEL[23]	GTX[1].TSTOUT[5]
CELL[12].IMUX_CLK[0]	GTX[1].RXUSRCLK
CELL[12].IMUX_CLK[1]	GTX[1].RXUSRCLK2
CELL[12].IMUX_CTRL[0]	GTX[1].RXBUFRESET
CELL[12].IMUX_CTRL[1]	GTX[1].RXRESET
CELL[12].IMUX_IMUX_DELAY[8]	GTX[1].RXCHBONDSLAVE
CELL[12].IMUX_IMUX_DELAY[10]	GTX[1].RXCHBONDLEVEL[0]
CELL[12].IMUX_IMUX_DELAY[11]	GTX[1].RXCHBONDLEVEL[2]
CELL[12].IMUX_IMUX_DELAY[14]	GTX[1].USRCODEERR
CELL[12].IMUX_IMUX_DELAY[16]	GTCLK[1].CLKTESTSIG
CELL[12].IMUX_IMUX_DELAY[17]	GTCLK[0].CLKTESTSIG
CELL[12].IMUX_IMUX_DELAY[18]	GTX[1].CLKTESTSIG[1]
CELL[12].IMUX_IMUX_DELAY[19]	GTX[1].CLKTESTSIG[0]
CELL[12].IMUX_IMUX_DELAY[20]	GTX[1].RXPLLLKDETEN
CELL[12].IMUX_IMUX_DELAY[21]	GTX[1].RXPLLPOWERDOWN
CELL[12].IMUX_IMUX_DELAY[24]	GTX[1].RXCHBONDMASTER
CELL[12].IMUX_IMUX_DELAY[26]	GTX[1].RXCHBONDLEVEL[1]
CELL[12].IMUX_IMUX_DELAY[27]	GTX[1].GTXTEST[12]
CELL[12].IMUX_IMUX_DELAY[28]	GTX[1].GTXTEST[11]
CELL[12].IMUX_IMUX_DELAY[29]	GTX[1].GTXTEST[10]
CELL[12].IMUX_IMUX_DELAY[30]	GTX[1].GTXTEST[9]
CELL[12].IMUX_IMUX_DELAY[31]	GTX[1].GTXTEST[8]
CELL[12].IMUX_IMUX_DELAY[32]	GTX[1].GTXTEST[7]
CELL[12].IMUX_IMUX_DELAY[33]	GTX[1].GTXTEST[6]
CELL[12].IMUX_IMUX_DELAY[34]	GTX[1].GTXTEST[5]
CELL[12].IMUX_IMUX_DELAY[35]	GTX[1].GTXTEST[4]
CELL[12].IMUX_IMUX_DELAY[36]	GTX[1].GTXTEST[3]
CELL[12].IMUX_IMUX_DELAY[37]	GTX[1].GTXTEST[2]
CELL[12].IMUX_IMUX_DELAY[38]	GTX[1].GTXTEST[1]
CELL[12].IMUX_IMUX_DELAY[39]	GTX[1].GTXTEST[0]
CELL[12].OUT_BEL[0]	GTX[1].RXLOSSOFSYNC[0]
CELL[12].OUT_BEL[1]	GTX[1].RXDATA[15]
CELL[12].OUT_BEL[2]	GTX[1].RXDATA[14]
CELL[12].OUT_BEL[3]	GTX[1].RXCHARISK[3]
CELL[12].OUT_BEL[4]	GTX[1].RXDATAVALID
CELL[12].OUT_BEL[5]	GTX[1].RXCHARISK[1]
CELL[12].OUT_BEL[6]	GTX[1].RXDATA[13]
CELL[12].OUT_BEL[7]	GTX[1].RXDATA[12]
CELL[12].OUT_BEL[8]	GTX[1].RXCHARISCOMMA[2]
CELL[12].OUT_BEL[10]	GTX[1].RXBYTEREALIGN
CELL[12].OUT_BEL[13]	GTX[1].RXBYTEISALIGNED
CELL[12].OUT_BEL[14]	GTX[1].RXCHANREALIGN
CELL[12].OUT_BEL[15]	GTX[1].RXCHARISK[2]
CELL[12].OUT_BEL[18]	GTX[1].RXCHARISCOMMA[3]
CELL[12].OUT_BEL[19]	GTX[1].COMSASDET
CELL[12].OUT_BEL[20]	GTX[1].COMINITDET
CELL[12].OUT_BEL[22]	GTX[1].RXLOSSOFSYNC[1]
CELL[12].OUT_BEL[23]	GTX[1].COMWAKEDET
CELL[13].IMUX_CLK[0]	GTX[1].GREFCLKRX
CELL[13].IMUX_CLK[1]	GTX[1].TSTCLK[0]
CELL[13].IMUX_CTRL[0]	GTX[1].PLLRXRESET
CELL[13].IMUX_IMUX_DELAY[0]	GTX[1].TXBUFDIFFCTRL[0]
CELL[13].IMUX_IMUX_DELAY[3]	GTX[1].TXDEEMPH
CELL[13].IMUX_IMUX_DELAY[5]	GTX[1].TXDIFFCTRL[2]
CELL[13].IMUX_IMUX_DELAY[9]	GTX[1].TXPREEMPHASIS[3]
CELL[13].IMUX_IMUX_DELAY[11]	GTX[1].LOOPBACK[1]
CELL[13].IMUX_IMUX_DELAY[12]	GTX[1].RXDLYALIGNTESTMODEENB
CELL[13].IMUX_IMUX_DELAY[13]	GTX[1].TXSWING
CELL[13].IMUX_IMUX_DELAY[16]	GTX[1].TXBUFDIFFCTRL[1]
CELL[13].IMUX_IMUX_DELAY[17]	GTX[1].TXPREEMPHASIS[2]
CELL[13].IMUX_IMUX_DELAY[18]	GTX[1].TXBUFDIFFCTRL[2]
CELL[13].IMUX_IMUX_DELAY[19]	GTX[1].TXPREEMPHASIS[1]
CELL[13].IMUX_IMUX_DELAY[21]	GTX[1].TXDIFFCTRL[0]
CELL[13].IMUX_IMUX_DELAY[22]	GTX[1].RXPLLREFSELDY[1]
CELL[13].IMUX_IMUX_DELAY[24]	GTX[1].LOOPBACK[0]
CELL[13].IMUX_IMUX_DELAY[25]	GTX[1].RXDLYALIGNFORCEROTATEB
CELL[13].IMUX_IMUX_DELAY[26]	GTX[1].TXPREEMPHASIS[0]
CELL[13].IMUX_IMUX_DELAY[27]	GTX[1].LOOPBACK[2]
CELL[13].IMUX_IMUX_DELAY[28]	GTX[1].RXDLYALIGNMONENB
CELL[13].IMUX_IMUX_DELAY[29]	GTX[1].RXDLYALIGNSWPPRECURB
CELL[13].IMUX_IMUX_DELAY[30]	GTX[1].TXDIFFCTRL[3]
CELL[13].IMUX_IMUX_DELAY[32]	GTX[1].RXCHBONDI[0]
CELL[13].IMUX_IMUX_DELAY[33]	GTX[1].RXCHBONDI[1]
CELL[13].IMUX_IMUX_DELAY[34]	GTX[1].RXCHBONDI[2]
CELL[13].IMUX_IMUX_DELAY[35]	GTX[1].RXCHBONDI[3]
CELL[13].IMUX_IMUX_DELAY[36]	GTX[1].RXCOMMADETUSE
CELL[13].IMUX_IMUX_DELAY[37]	GTX[1].RXPLLREFSELDY[0]
CELL[13].IMUX_IMUX_DELAY[38]	GTX[1].TXDIFFCTRL[1]
CELL[13].IMUX_IMUX_DELAY[39]	GTX[1].RXPLLREFSELDY[2]
CELL[13].OUT_BEL[0]	GTX[1].RXDISPERR[2]
CELL[13].OUT_BEL[1]	GTX[1].RXRUNDISP[3]
CELL[13].OUT_BEL[2]	GTX[1].RXCHARISCOMMA[1]
CELL[13].OUT_BEL[3]	GTX[1].RXNOTINTABLE[3]
CELL[13].OUT_BEL[4]	GTX[1].RXDISPERR[0]
CELL[13].OUT_BEL[5]	GTX[1].RXRUNDISP[1]
CELL[13].OUT_BEL[7]	GTX[1].RXNOTINTABLE[1]
CELL[13].OUT_BEL[8]	GTX[1].RXDISPERR[1]
CELL[13].OUT_BEL[9]	GTX[1].RXRUNDISP[0]
CELL[13].OUT_BEL[11]	GTX[1].RXNOTINTABLE[0]
CELL[13].OUT_BEL[13]	GTX[1].RXCHANISALIGNED
CELL[13].OUT_BEL[14]	GTX[1].RXCHARISCOMMA[0]
CELL[13].OUT_BEL[15]	GTX[1].RXNOTINTABLE[2]
CELL[13].OUT_BEL[16]	GTX[1].RXCHARISK[0]
CELL[13].OUT_BEL[19]	GTX[1].RXRUNDISP[2]
CELL[13].OUT_BEL[22]	GTX[1].RXDISPERR[3]
CELL[14].IMUX_CLK[1]	GTX[1].SCANCLK
CELL[14].IMUX_IMUX_DELAY[8]	GTX[1].DFETAP1[0]
CELL[14].IMUX_IMUX_DELAY[9]	GTX[1].TXDETECTRX
CELL[14].IMUX_IMUX_DELAY[10]	GTX[1].DFETAP1[1]
CELL[14].IMUX_IMUX_DELAY[11]	GTX[1].TXMARGIN[0]
CELL[14].IMUX_IMUX_DELAY[13]	GTX[1].RXPOWERDOWN[0]
CELL[14].IMUX_IMUX_DELAY[14]	GTX[1].DFETAP1[2]
CELL[14].IMUX_IMUX_DELAY[15]	GTX[1].DFETAP1[3]
CELL[14].IMUX_IMUX_DELAY[16]	GTX[1].DFECLKDLYADJ[5]
CELL[14].IMUX_IMUX_DELAY[17]	GTX[1].DFECLKDLYADJ[4]
CELL[14].IMUX_IMUX_DELAY[18]	GTX[1].DFECLKDLYADJ[2]
CELL[14].IMUX_IMUX_DELAY[19]	GTX[1].DFECLKDLYADJ[1]
CELL[14].IMUX_IMUX_DELAY[21]	GTX[1].RXPOWERDOWN[1]
CELL[14].IMUX_IMUX_DELAY[24]	GTX[1].DFETAP2[0]
CELL[14].IMUX_IMUX_DELAY[25]	GTX[1].DFETAP2[1]
CELL[14].IMUX_IMUX_DELAY[26]	GTX[1].TXMARGIN[1]
CELL[14].IMUX_IMUX_DELAY[28]	GTX[1].TXPOWERDOWN[0]
CELL[14].IMUX_IMUX_DELAY[29]	GTX[1].DFEDLYOVRD
CELL[14].IMUX_IMUX_DELAY[30]	GTX[1].DFETAP2[2]
CELL[14].IMUX_IMUX_DELAY[31]	GTX[1].DFETAP2[3]
CELL[14].IMUX_IMUX_DELAY[32]	GTX[1].TXELECIDLE
CELL[14].IMUX_IMUX_DELAY[33]	GTX[1].DFECLKDLYADJ[3]
CELL[14].IMUX_IMUX_DELAY[35]	GTX[1].DFECLKDLYADJ[0]
CELL[14].IMUX_IMUX_DELAY[36]	GTX[1].TXPOWERDOWN[1]
CELL[14].IMUX_IMUX_DELAY[37]	GTX[1].DFETAPOVRD
CELL[14].IMUX_IMUX_DELAY[38]	GTX[1].DFETAP1[4]
CELL[14].IMUX_IMUX_DELAY[39]	GTX[1].DFETAP2[4]
CELL[14].OUT_BEL[0]	GTX[1].MGTREFCLKFAB[0]
CELL[14].OUT_BEL[3]	GTX[1].RXBUFSTATUS[2]
CELL[14].OUT_BEL[4]	GTX[1].SCANOUT[1]
CELL[14].OUT_BEL[5]	GTX[1].RXPLLLKDET
CELL[14].OUT_BEL[6]	GTX[1].RXBUFSTATUS[0]
CELL[14].OUT_BEL[7]	GTX[1].RXBUFSTATUS[1]
CELL[14].OUT_BEL[8]	GTX[1].PHYSTATUS
CELL[14].OUT_BEL[10]	GTX[1].RXCHBONDO[1]
CELL[14].OUT_BEL[11]	GTX[1].RXCHBONDO[2]
CELL[14].OUT_BEL[12]	GTX[1].MGTREFCLKFAB[1]
CELL[14].OUT_BEL[13]	GTX[1].RXSTATUS[2]
CELL[14].OUT_BEL[14]	GTX[1].RXSTATUS[0]
CELL[14].OUT_BEL[15]	GTX[1].RXCHBONDO[3]
CELL[14].OUT_BEL[16]	GTX[1].RXSTATUS[1]
CELL[14].OUT_BEL[17]	GTX[1].RXCHBONDO[0]
CELL[14].OUT_BEL[18]	GTX[1].SCANOUT[0]
CELL[14].OUT_BEL[22]	GTX[1].RXOVERSAMPLEERR
CELL[15].IMUX_CLK[1]	GTX[1].TSTCLK[1]
CELL[15].IMUX_CTRL[1]	GTX[1].PLLTXRESET
CELL[15].IMUX_IMUX_DELAY[2]	GTX[1].TXDLYALIGNUPDSW
CELL[15].IMUX_IMUX_DELAY[8]	GTX[1].TXHEADER[0]
CELL[15].IMUX_IMUX_DELAY[9]	GTX[1].TXPOLARITY
CELL[15].IMUX_IMUX_DELAY[10]	GTX[1].RXDLYALIGNUPDSW
CELL[15].IMUX_IMUX_DELAY[11]	GTX[1].TXBYPASS8B10B[0]
CELL[15].IMUX_IMUX_DELAY[13]	GTX[1].TXDLYALIGNRESET
CELL[15].IMUX_IMUX_DELAY[14]	GTX[1].RXDLYALIGNDISABLE
CELL[15].IMUX_IMUX_DELAY[15]	GTX[1].TXMARGIN[2]
CELL[15].IMUX_IMUX_DELAY[16]	GTX[1].TXHEADER[1]
CELL[15].IMUX_IMUX_DELAY[17]	GTX[1].TXINHIBIT
CELL[15].IMUX_IMUX_DELAY[18]	GTX[1].TXPMASETPHASE
CELL[15].IMUX_IMUX_DELAY[19]	GTX[1].TXBYPASS8B10B[3]
CELL[15].IMUX_IMUX_DELAY[21]	GTX[1].TXCHARDISPMODE[3]
CELL[15].IMUX_IMUX_DELAY[22]	GTX[1].TXCHARDISPVAL[3]
CELL[15].IMUX_IMUX_DELAY[23]	GTX[1].TXCHARISK[3]
CELL[15].IMUX_IMUX_DELAY[25]	GTX[1].TXDLYALIGNOVERRIDE
CELL[15].IMUX_IMUX_DELAY[26]	GTX[1].TXCHARISK[0]
CELL[15].IMUX_IMUX_DELAY[27]	GTX[1].TXBYPASS8B10B[1]
CELL[15].IMUX_IMUX_DELAY[28]	GTX[1].TXCHARDISPMODE[1]
CELL[15].IMUX_IMUX_DELAY[29]	GTX[1].RXDLYALIGNRESET
CELL[15].IMUX_IMUX_DELAY[30]	GTX[1].TXCHARDISPVAL[1]
CELL[15].IMUX_IMUX_DELAY[32]	GTX[1].TXHEADER[2]
CELL[15].IMUX_IMUX_DELAY[33]	GTX[1].RXDLYALIGNOVERRIDE
CELL[15].IMUX_IMUX_DELAY[34]	GTX[1].TXCHARDISPMODE[0]
CELL[15].IMUX_IMUX_DELAY[35]	GTX[1].TXBYPASS8B10B[2]
CELL[15].IMUX_IMUX_DELAY[36]	GTX[1].TXCHARISK[1]
CELL[15].IMUX_IMUX_DELAY[37]	GTX[1].TXCHARDISPMODE[2]
CELL[15].IMUX_IMUX_DELAY[38]	GTX[1].TXCHARDISPVAL[2]
CELL[15].IMUX_IMUX_DELAY[39]	GTX[1].TXCHARISK[2]
CELL[15].IMUX_IMUX_DELAY[44]	GTX[1].TXCHARDISPVAL[0]
CELL[15].IMUX_IMUX_DELAY[46]	GTX[1].TXDLYALIGNDISABLE
CELL[15].OUT_BEL[0]	GTX[1].RXDLYALIGNMONITOR[7]
CELL[15].OUT_BEL[1]	GTX[1].RXSTARTOFSEQ
CELL[15].OUT_BEL[2]	GTX[1].RXPRBSERR
CELL[15].OUT_BEL[3]	GTX[1].RXELECIDLE
CELL[15].OUT_BEL[4]	GTX[1].RXVALID
CELL[15].OUT_BEL[5]	GTX[1].RXRECCLKPCS
CELL[15].OUT_BEL[6]	GTX[1].RXCLKCORCNT[2]
CELL[15].OUT_BEL[7]	GTX[1].RXDLYALIGNMONITOR[2]
CELL[15].OUT_BEL[8]	GTX[1].RXCLKCORCNT[0]
CELL[15].OUT_BEL[9]	GTX[1].RXCLKCORCNT[1]
CELL[15].OUT_BEL[10]	GTX[1].RXHEADER[0]
CELL[15].OUT_BEL[11]	GTX[1].RXHEADERVALID
CELL[15].OUT_BEL[12]	GTX[1].RXCOMMADET
CELL[15].OUT_BEL[14]	GTX[1].RXCHANBONDSEQ
CELL[15].OUT_BEL[15]	GTX[1].RXDLYALIGNMONITOR[1]
CELL[15].OUT_BEL[16]	GTX[1].RXHEADER[1]
CELL[15].OUT_BEL[17]	GTX[1].RXHEADER[2]
CELL[15].OUT_BEL[18]	GTX[1].RXDLYALIGNMONITOR[6]
CELL[15].OUT_BEL[19]	GTX[1].RXDLYALIGNMONITOR[5]
CELL[15].OUT_BEL[20]	GTX[1].RXDLYALIGNMONITOR[3]
CELL[15].OUT_BEL[21]	GTX[1].RXDLYALIGNMONITOR[0]
CELL[15].OUT_BEL[22]	GTX[1].RXRESETDONE
CELL[15].OUT_BEL[23]	GTX[1].RXDLYALIGNMONITOR[4]
CELL[16].IMUX_CLK[0]	GTX[1].TXUSRCLK
CELL[16].IMUX_CLK[1]	GTX[1].TXUSRCLK2
CELL[16].IMUX_CTRL[0]	GTX[1].TXRESET
CELL[16].IMUX_CTRL[1]	GTX[1].GTXTXRESET
CELL[16].IMUX_IMUX_DELAY[3]	GTX[1].TXDATA[12]
CELL[16].IMUX_IMUX_DELAY[5]	GTX[1].TXDATA[14]
CELL[16].IMUX_IMUX_DELAY[8]	GTX[1].TXSEQUENCE[3]
CELL[16].IMUX_IMUX_DELAY[9]	GTX[1].DFETAP3[1]
CELL[16].IMUX_IMUX_DELAY[10]	GTX[1].DFETAP3[0]
CELL[16].IMUX_IMUX_DELAY[11]	GTX[1].TXSEQUENCE[0]
CELL[16].IMUX_IMUX_DELAY[12]	GTX[1].DFETAP3[2]
CELL[16].IMUX_IMUX_DELAY[13]	GTX[1].TXDATA[15]
CELL[16].IMUX_IMUX_DELAY[15]	GTX[1].TXENPRBSTST[2]
CELL[16].IMUX_IMUX_DELAY[17]	GTX[1].DFETAP3[3]
CELL[16].IMUX_IMUX_DELAY[19]	GTX[1].TXSEQUENCE[1]
CELL[16].IMUX_IMUX_DELAY[20]	GTX[1].DFETAP4[3]
CELL[16].IMUX_IMUX_DELAY[22]	GTX[1].TXSEQUENCE[5]
CELL[16].IMUX_IMUX_DELAY[23]	GTX[1].TXENPRBSTST[1]
CELL[16].IMUX_IMUX_DELAY[24]	GTX[1].TXSEQUENCE[4]
CELL[16].IMUX_IMUX_DELAY[25]	GTX[1].DFETAP4[1]
CELL[16].IMUX_IMUX_DELAY[26]	GTX[1].DFETAP4[0]
CELL[16].IMUX_IMUX_DELAY[28]	GTX[1].DFETAP4[2]
CELL[16].IMUX_IMUX_DELAY[30]	GTX[1].TXDATA[13]
CELL[16].IMUX_IMUX_DELAY[32]	GTX[1].GATERXELECIDLE
CELL[16].IMUX_IMUX_DELAY[33]	GTX[1].TXRATE[1]
CELL[16].IMUX_IMUX_DELAY[34]	GTX[1].TXRATE[0]
CELL[16].IMUX_IMUX_DELAY[35]	GTX[1].TXSEQUENCE[2]
CELL[16].IMUX_IMUX_DELAY[37]	GTX[1].IGNORESIGDET
CELL[16].IMUX_IMUX_DELAY[38]	GTX[1].TXSEQUENCE[6]
CELL[16].IMUX_IMUX_DELAY[39]	GTX[1].TXENPRBSTST[0]
CELL[16].IMUX_IMUX_DELAY[41]	GTX[1].RXRATE[1]
CELL[16].IMUX_IMUX_DELAY[42]	GTX[1].RXRATE[0]
CELL[16].OUT_BEL[1]	GTX[1].DFECLKDLYADJMON[1]
CELL[16].OUT_BEL[2]	GTX[1].DFECLKDLYADJMON[2]
CELL[16].OUT_BEL[3]	GTX[1].DFECLKDLYADJMON[5]
CELL[16].OUT_BEL[4]	GTX[1].TXGEARBOXREADY
CELL[16].OUT_BEL[5]	GTX[1].DFECLKDLYADJMON[0]
CELL[16].OUT_BEL[6]	GTX[1].DFECLKDLYADJMON[3]
CELL[16].OUT_BEL[7]	GTX[1].DFECLKDLYADJMON[4]
CELL[16].OUT_BEL[8]	GTX[1].TXOUTCLKPCS
CELL[16].OUT_BEL[10]	GTX[1].DFEEYEDACMON[2]
CELL[16].OUT_BEL[11]	GTX[1].DFEEYEDACMON[3]
CELL[16].OUT_BEL[13]	GTX[1].DFEEYEDACMON[0]
CELL[16].OUT_BEL[14]	GTX[1].DFEEYEDACMON[1]
CELL[16].OUT_BEL[15]	GTX[1].DFEEYEDACMON[4]
CELL[16].OUT_BEL[18]	GTX[1].DFESENSCAL[1]
CELL[16].OUT_BEL[19]	GTX[1].DFESENSCAL[0]
CELL[16].OUT_BEL[20]	GTX[1].RXRATEDONE
CELL[16].OUT_BEL[22]	GTX[1].DFESENSCAL[2]
CELL[16].OUT_BEL[23]	GTX[1].TXRATEDONE
CELL[17].IMUX_CLK[0]	GTX[1].GREFCLKTX
CELL[17].IMUX_IMUX_DELAY[9]	GTX[1].TXDLYALIGNFORCEROTATEB
CELL[17].IMUX_IMUX_DELAY[10]	GTX[1].TXCOMWAKE
CELL[17].IMUX_IMUX_DELAY[11]	GTX[1].TXDLYALIGNMONENB
CELL[17].IMUX_IMUX_DELAY[12]	GTX[1].TXPLLLKDETEN
CELL[17].IMUX_IMUX_DELAY[13]	GTX[1].TXDATA[10]
CELL[17].IMUX_IMUX_DELAY[14]	GTX[1].TXSTARTSEQ
CELL[17].IMUX_IMUX_DELAY[15]	GTX[1].TXDATA[8]
CELL[17].IMUX_IMUX_DELAY[18]	GTX[1].TXCOMINIT
CELL[17].IMUX_IMUX_DELAY[19]	GTX[1].TXCOMSAS
CELL[17].IMUX_IMUX_DELAY[21]	GTX[1].TXDATA[9]
CELL[17].IMUX_IMUX_DELAY[22]	GTX[1].TXENC8B10BUSE
CELL[17].IMUX_IMUX_DELAY[24]	GTX[1].TXDATA[23]
CELL[17].IMUX_IMUX_DELAY[25]	GTX[1].TXDATA[22]
CELL[17].IMUX_IMUX_DELAY[26]	GTX[1].TXDATA[7]
CELL[17].IMUX_IMUX_DELAY[27]	GTX[1].TXDATA[20]
CELL[17].IMUX_IMUX_DELAY[28]	GTX[1].TXDATA[21]
CELL[17].IMUX_IMUX_DELAY[29]	GTX[1].TXPLLPOWERDOWN
CELL[17].IMUX_IMUX_DELAY[30]	GTX[1].TXDLYALIGNTESTMODEENB
CELL[17].IMUX_IMUX_DELAY[32]	GTX[1].TXDATA[31]
CELL[17].IMUX_IMUX_DELAY[33]	GTX[1].TXDATA[30]
CELL[17].IMUX_IMUX_DELAY[34]	GTX[1].TXDATA[6]
CELL[17].IMUX_IMUX_DELAY[35]	GTX[1].TXDATA[28]
CELL[17].IMUX_IMUX_DELAY[36]	GTX[1].TXDATA[29]
CELL[17].IMUX_IMUX_DELAY[37]	GTX[1].TXPLLREFSELDY[0]
CELL[17].IMUX_IMUX_DELAY[38]	GTX[1].TXPLLREFSELDY[1]
CELL[17].IMUX_IMUX_DELAY[39]	GTX[1].TXPLLREFSELDY[2]
CELL[17].IMUX_IMUX_DELAY[40]	GTX[1].TXDATA[11]
CELL[17].OUT_BEL[0]	GTX[1].TXDLYALIGNMONITOR[7]
CELL[17].OUT_BEL[1]	GTX[1].DFETAP2MONITOR[0]
CELL[17].OUT_BEL[2]	GTX[1].DFETAP2MONITOR[1]
CELL[17].OUT_BEL[3]	GTX[1].DFETAP2MONITOR[4]
CELL[17].OUT_BEL[4]	GTX[1].TXDLYALIGNMONITOR[2]
CELL[17].OUT_BEL[5]	GTX[1].TXBUFSTATUS[0]
CELL[17].OUT_BEL[6]	GTX[1].DFETAP2MONITOR[2]
CELL[17].OUT_BEL[7]	GTX[1].DFETAP2MONITOR[3]
CELL[17].OUT_BEL[8]	GTX[1].DFETAP4MONITOR[1]
CELL[17].OUT_BEL[9]	GTX[1].DFETAP4MONITOR[2]
CELL[17].OUT_BEL[10]	GTX[1].TXKERR[1]
CELL[17].OUT_BEL[11]	GTX[1].TXKERR[2]
CELL[17].OUT_BEL[12]	GTX[1].DFETAP4MONITOR[0]
CELL[17].OUT_BEL[13]	GTX[1].DFETAP4MONITOR[3]
CELL[17].OUT_BEL[14]	GTX[1].TXKERR[0]
CELL[17].OUT_BEL[15]	GTX[1].TXKERR[3]
CELL[17].OUT_BEL[16]	GTX[1].TXDLYALIGNMONITOR[1]
CELL[17].OUT_BEL[17]	GTX[1].TXBUFSTATUS[1]
CELL[17].OUT_BEL[18]	GTX[1].TXDLYALIGNMONITOR[6]
CELL[17].OUT_BEL[19]	GTX[1].TXDLYALIGNMONITOR[5]
CELL[17].OUT_BEL[20]	GTX[1].TXDLYALIGNMONITOR[3]
CELL[17].OUT_BEL[21]	GTX[1].TXDLYALIGNMONITOR[0]
CELL[17].OUT_BEL[22]	GTX[1].TXRESETDONE
CELL[17].OUT_BEL[23]	GTX[1].TXDLYALIGNMONITOR[4]
CELL[18].IMUX_IMUX_DELAY[8]	GTX[1].DWE
CELL[18].IMUX_IMUX_DELAY[9]	GTX[1].SCANIN[4]
CELL[18].IMUX_IMUX_DELAY[10]	GTX[1].TXPOSTEMPHASIS[0]
CELL[18].IMUX_IMUX_DELAY[12]	GTX[1].TXPOSTEMPHASIS[2]
CELL[18].IMUX_IMUX_DELAY[13]	GTX[1].TXPRBSFORCEERR
CELL[18].IMUX_IMUX_DELAY[15]	GTX[1].TXPDOWNASYNCH
CELL[18].IMUX_IMUX_DELAY[16]	GTX[1].DEN
CELL[18].IMUX_IMUX_DELAY[17]	GTX[1].TXENPMAPHASEALIGN
CELL[18].IMUX_IMUX_DELAY[18]	GTX[1].TXPOSTEMPHASIS[1]
CELL[18].IMUX_IMUX_DELAY[19]	GTX[1].TXDATA[25]
CELL[18].IMUX_IMUX_DELAY[20]	GTX[1].TXPOSTEMPHASIS[3]
CELL[18].IMUX_IMUX_DELAY[22]	GTX[1].TXPOSTEMPHASIS[4]
CELL[18].IMUX_IMUX_DELAY[25]	GTX[1].SCANIN[1]
CELL[18].IMUX_IMUX_DELAY[26]	GTX[1].TXDATA[4]
CELL[18].IMUX_IMUX_DELAY[27]	GTX[1].TXDATA[19]
CELL[18].IMUX_IMUX_DELAY[28]	GTX[1].TXDATA[2]
CELL[18].IMUX_IMUX_DELAY[29]	GTX[1].TXDATA[18]
CELL[18].IMUX_IMUX_DELAY[30]	GTX[1].TXDATA[17]
CELL[18].IMUX_IMUX_DELAY[31]	GTX[1].TXDATA[16]
CELL[18].IMUX_IMUX_DELAY[32]	GTX[1].TXDATA[3]
CELL[18].IMUX_IMUX_DELAY[33]	GTX[1].SCANIN[0]
CELL[18].IMUX_IMUX_DELAY[34]	GTX[1].TXDATA[5]
CELL[18].IMUX_IMUX_DELAY[35]	GTX[1].TXDATA[27]
CELL[18].IMUX_IMUX_DELAY[36]	GTX[1].TXDATA[1]
CELL[18].IMUX_IMUX_DELAY[37]	GTX[1].TXDATA[26]
CELL[18].IMUX_IMUX_DELAY[38]	GTX[1].TXDATA[0]
CELL[18].IMUX_IMUX_DELAY[39]	GTX[1].TXDATA[24]
CELL[18].OUT_BEL[0]	GTX[1].DRDY
CELL[18].OUT_BEL[1]	GTX[1].DFETAP1MONITOR[0]
CELL[18].OUT_BEL[2]	GTX[1].DFETAP1MONITOR[1]
CELL[18].OUT_BEL[3]	GTX[1].DFETAP1MONITOR[4]
CELL[18].OUT_BEL[5]	GTX[1].TXPLLLKDET
CELL[18].OUT_BEL[6]	GTX[1].DFETAP1MONITOR[2]
CELL[18].OUT_BEL[7]	GTX[1].DFETAP1MONITOR[3]
CELL[18].OUT_BEL[8]	GTX[1].DFETAP3MONITOR[1]
CELL[18].OUT_BEL[9]	GTX[1].DFETAP3MONITOR[2]
CELL[18].OUT_BEL[10]	GTX[1].TXRUNDISP[1]
CELL[18].OUT_BEL[11]	GTX[1].TXRUNDISP[2]
CELL[18].OUT_BEL[12]	GTX[1].DFETAP3MONITOR[0]
CELL[18].OUT_BEL[13]	GTX[1].DFETAP3MONITOR[3]
CELL[18].OUT_BEL[14]	GTX[1].TXRUNDISP[0]
CELL[18].OUT_BEL[15]	GTX[1].TXRUNDISP[3]
CELL[18].OUT_BEL[18]	GTX[1].COMFINISH
CELL[19].IMUX_CLK[0]	GTX[1].DCLK
CELL[19].IMUX_IMUX_DELAY[8]	GTX[1].DI[0]
CELL[19].IMUX_IMUX_DELAY[9]	GTX[1].DI[1]
CELL[19].IMUX_IMUX_DELAY[10]	GTX[1].DI[2]
CELL[19].IMUX_IMUX_DELAY[11]	GTX[1].DI[3]
CELL[19].IMUX_IMUX_DELAY[12]	GTX[1].DI[4]
CELL[19].IMUX_IMUX_DELAY[13]	GTX[1].DI[5]
CELL[19].IMUX_IMUX_DELAY[14]	GTX[1].DI[6]
CELL[19].IMUX_IMUX_DELAY[15]	GTX[1].DI[7]
CELL[19].IMUX_IMUX_DELAY[16]	GTX[1].DI[8]
CELL[19].IMUX_IMUX_DELAY[17]	GTX[1].DI[9]
CELL[19].IMUX_IMUX_DELAY[18]	GTX[1].DI[10]
CELL[19].IMUX_IMUX_DELAY[19]	GTX[1].DI[11]
CELL[19].IMUX_IMUX_DELAY[20]	GTX[1].DI[12]
CELL[19].IMUX_IMUX_DELAY[21]	GTX[1].DI[13]
CELL[19].IMUX_IMUX_DELAY[22]	GTX[1].DI[14]
CELL[19].IMUX_IMUX_DELAY[23]	GTX[1].DI[15]
CELL[19].IMUX_IMUX_DELAY[30]	GTCLK[1].CEB
CELL[19].IMUX_IMUX_DELAY[31]	GTCLK[0].CEB
CELL[19].IMUX_IMUX_DELAY[32]	GTX[1].DADDR[0]
CELL[19].IMUX_IMUX_DELAY[33]	GTX[1].DADDR[1]
CELL[19].IMUX_IMUX_DELAY[34]	GTX[1].DADDR[2]
CELL[19].IMUX_IMUX_DELAY[35]	GTX[1].DADDR[3]
CELL[19].IMUX_IMUX_DELAY[36]	GTX[1].DADDR[4]
CELL[19].IMUX_IMUX_DELAY[37]	GTX[1].DADDR[5]
CELL[19].IMUX_IMUX_DELAY[38]	GTX[1].DADDR[6]
CELL[19].IMUX_IMUX_DELAY[39]	GTX[1].DADDR[7]
CELL[19].OUT_BEL[0]	GTX[1].DRPDO[7]
CELL[19].OUT_BEL[1]	GTX[1].DRPDO[4]
CELL[19].OUT_BEL[2]	GTX[1].DRPDO[3]
CELL[19].OUT_BEL[3]	GTX[1].DRPDO[0]
CELL[19].OUT_BEL[4]	GTX[1].DRPDO[6]
CELL[19].OUT_BEL[5]	GTX[1].DRPDO[5]
CELL[19].OUT_BEL[6]	GTX[1].DRPDO[2]
CELL[19].OUT_BEL[7]	GTX[1].DRPDO[1]
CELL[19].OUT_BEL[8]	GTX[1].DRPDO[14]
CELL[19].OUT_BEL[9]	GTX[1].DRPDO[13]
CELL[19].OUT_BEL[10]	GTX[1].DRPDO[10]
CELL[19].OUT_BEL[11]	GTX[1].DRPDO[9]
CELL[19].OUT_BEL[12]	GTX[1].DRPDO[15]
CELL[19].OUT_BEL[13]	GTX[1].DRPDO[12]
CELL[19].OUT_BEL[14]	GTX[1].DRPDO[11]
CELL[19].OUT_BEL[15]	GTX[1].DRPDO[8]
CELL[20].IMUX_CTRL[1]	GTX[2].PRBSCNTRESET
CELL[20].IMUX_IMUX_DELAY[0]	GTX[2].TSTIN[17]
CELL[20].IMUX_IMUX_DELAY[1]	GTX[2].TSTIN[18]
CELL[20].IMUX_IMUX_DELAY[8]	GTX[2].TSTIN[9]
CELL[20].IMUX_IMUX_DELAY[9]	GTX[2].TSTIN[7]
CELL[20].IMUX_IMUX_DELAY[10]	GTX[2].TSTIN[5]
CELL[20].IMUX_IMUX_DELAY[11]	GTX[2].TSTIN[3]
CELL[20].IMUX_IMUX_DELAY[13]	GTX[2].TSTIN[12]
CELL[20].IMUX_IMUX_DELAY[14]	GTX[2].TSTIN[1]
CELL[20].IMUX_IMUX_DELAY[16]	GTX[2].TSTIN[15]
CELL[20].IMUX_IMUX_DELAY[17]	GTX[2].TSTPWRDNOVRD
CELL[20].IMUX_IMUX_DELAY[18]	GTX[2].TSTPWRDN[1]
CELL[20].IMUX_IMUX_DELAY[19]	GTX[2].TSTPWRDN[3]
CELL[20].IMUX_IMUX_DELAY[21]	GTX[2].TSTIN[11]
CELL[20].IMUX_IMUX_DELAY[22]	GTX[2].SCANIN[3]
CELL[20].IMUX_IMUX_DELAY[24]	GTX[2].TSTIN[8]
CELL[20].IMUX_IMUX_DELAY[25]	GTX[2].TSTIN[6]
CELL[20].IMUX_IMUX_DELAY[26]	GTX[2].TSTIN[4]
CELL[20].IMUX_IMUX_DELAY[27]	GTX[2].TSTIN[2]
CELL[20].IMUX_IMUX_DELAY[28]	GTX[2].TSTIN[13]
CELL[20].IMUX_IMUX_DELAY[29]	GTX[2].SCANMODEB
CELL[20].IMUX_IMUX_DELAY[30]	GTX[2].TSTIN[0]
CELL[20].IMUX_IMUX_DELAY[31]	GTX[2].TSTIN[10]
CELL[20].IMUX_IMUX_DELAY[32]	GTX[2].TSTIN[14]
CELL[20].IMUX_IMUX_DELAY[33]	GTX[2].TSTPWRDN[0]
CELL[20].IMUX_IMUX_DELAY[34]	GTX[2].TSTPWRDN[2]
CELL[20].IMUX_IMUX_DELAY[35]	GTX[2].TSTPWRDN[4]
CELL[20].IMUX_IMUX_DELAY[37]	GTX[2].SCANENB
CELL[20].IMUX_IMUX_DELAY[38]	GTX[2].SCANIN[2]
CELL[20].IMUX_IMUX_DELAY[40]	GTX[2].TSTIN[16]
CELL[20].IMUX_IMUX_DELAY[41]	GTX[2].TSTIN[19]
CELL[20].OUT_BEL[0]	GTX[2].RXDATA[18]
CELL[20].OUT_BEL[1]	GTX[2].RXDATA[4]
CELL[20].OUT_BEL[2]	GTX[2].RXDATA[3]
CELL[20].OUT_BEL[3]	GTX[2].RXDATA[17]
CELL[20].OUT_BEL[4]	GTX[2].RXDATA[0]
CELL[20].OUT_BEL[5]	GTX[2].RXDATA[5]
CELL[20].OUT_BEL[6]	GTX[2].RXDATA[2]
CELL[20].OUT_BEL[7]	GTX[2].RXDATA[1]
CELL[20].OUT_BEL[8]	GTX[2].SCANOUT[4]
CELL[20].OUT_BEL[13]	GTX[2].SCANOUT[3]
CELL[20].OUT_BEL[15]	GTX[2].RXDATA[16]
CELL[20].OUT_BEL[16]	GTX[2].RXDATA[22]
CELL[20].OUT_BEL[17]	GTX[2].RXDATA[21]
CELL[20].OUT_BEL[18]	GTX[2].RXDATA[20]
CELL[20].OUT_BEL[20]	GTX[2].RXDATA[23]
CELL[20].OUT_BEL[22]	GTX[2].RXDATA[19]
CELL[20].OUT_BEL[23]	GTX[2].SCANOUT[2]
CELL[20].MGT_ROW[0]	GTX[0].RXRECCLK
CELL[20].MGT_ROW[1]	GTX[1].RXRECCLK
CELL[20].MGT_ROW[2]	GTX[0].TXOUTCLK
CELL[20].MGT_ROW[3]	GTX[1].TXOUTCLK
CELL[20].MGT_ROW[4]	GTCLK[0].CLKOUT
CELL[20].MGT_ROW[5]	GTCLK[1].CLKOUT
CELL[20].MGT_ROW[6]	GTX[2].RXRECCLK
CELL[20].MGT_ROW[7]	GTX[3].RXRECCLK
CELL[20].MGT_ROW[8]	GTX[2].TXOUTCLK
CELL[20].MGT_ROW[9]	GTX[3].TXOUTCLK
CELL[20].IMUX_GTX_PERFCLK	GTX[0].PERFCLKRX, GTX[1].PERFCLKRX, GTX[2].PERFCLKRX, GTX[3].PERFCLKRX, GTX[0].PERFCLKTX, GTX[1].PERFCLKTX, GTX[2].PERFCLKTX, GTX[3].PERFCLKTX
CELL[21].IMUX_CTRL[0]	GTX[2].GTXRXRESET
CELL[21].IMUX_CTRL[1]	GTX[2].RXCDRRESET
CELL[21].IMUX_IMUX_DELAY[9]	GTX[2].RXSLIDE
CELL[21].IMUX_IMUX_DELAY[11]	GTX[2].RXPMASETPHASE
CELL[21].IMUX_IMUX_DELAY[12]	GTX[2].RXGEARBOXSLIP
CELL[21].IMUX_IMUX_DELAY[14]	GTX[2].RXEQMIX[0]
CELL[21].IMUX_IMUX_DELAY[15]	GTX[2].RXEQMIX[1]
CELL[21].IMUX_IMUX_DELAY[18]	GTX[2].RXENPRBSTST[2]
CELL[21].IMUX_IMUX_DELAY[19]	GTX[2].RXEQMIX[9]
CELL[21].IMUX_IMUX_DELAY[20]	GTX[2].RXEQMIX[7]
CELL[21].IMUX_IMUX_DELAY[21]	GTX[2].RXEQMIX[5]
CELL[21].IMUX_IMUX_DELAY[22]	GTX[2].RXEQMIX[3]
CELL[21].IMUX_IMUX_DELAY[24]	GTX[2].RXBUFWE
CELL[21].IMUX_IMUX_DELAY[26]	GTX[2].RXPOLARITY
CELL[21].IMUX_IMUX_DELAY[27]	GTX[2].RXEQMIX[8]
CELL[21].IMUX_IMUX_DELAY[28]	GTX[2].RXEQMIX[6]
CELL[21].IMUX_IMUX_DELAY[29]	GTX[2].RXEQMIX[4]
CELL[21].IMUX_IMUX_DELAY[30]	GTX[2].RXEQMIX[2]
CELL[21].IMUX_IMUX_DELAY[32]	GTX[2].RXENSAMPLEALIGN
CELL[21].IMUX_IMUX_DELAY[33]	GTX[2].RXENPRBSTST[0]
CELL[21].IMUX_IMUX_DELAY[34]	GTX[2].RXENPRBSTST[1]
CELL[21].IMUX_IMUX_DELAY[35]	GTX[2].RXENPMAPHASEALIGN
CELL[21].IMUX_IMUX_DELAY[36]	GTX[2].RXENMCOMMAALIGN
CELL[21].IMUX_IMUX_DELAY[37]	GTX[2].RXENPCOMMAALIGN
CELL[21].IMUX_IMUX_DELAY[38]	GTX[2].RXENCHANSYNC
CELL[21].IMUX_IMUX_DELAY[39]	GTX[2].RXDEC8B10BUSE
CELL[21].OUT_BEL[0]	GTX[2].RXDATA[24]
CELL[21].OUT_BEL[1]	GTX[2].RXDATA[6]
CELL[21].OUT_BEL[2]	GTX[2].RXDATA[11]
CELL[21].OUT_BEL[3]	GTX[2].RXDATA[31]
CELL[21].OUT_BEL[4]	GTX[2].RXDATA[8]
CELL[21].OUT_BEL[5]	GTX[2].RXDATA[7]
CELL[21].OUT_BEL[6]	GTX[2].RXDATA[10]
CELL[21].OUT_BEL[7]	GTX[2].RXDATA[9]
CELL[21].OUT_BEL[8]	GTX[2].TSTOUT[8]
CELL[21].OUT_BEL[9]	GTX[2].RXDATA[27]
CELL[21].OUT_BEL[10]	GTX[2].TSTOUT[2]
CELL[21].OUT_BEL[11]	GTX[2].RXDATA[29]
CELL[21].OUT_BEL[12]	GTX[2].TSTOUT[9]
CELL[21].OUT_BEL[13]	GTX[2].TSTOUT[6]
CELL[21].OUT_BEL[14]	GTX[2].TSTOUT[4]
CELL[21].OUT_BEL[15]	GTX[2].RXDATA[30]
CELL[21].OUT_BEL[16]	GTX[2].RXDATA[28]
CELL[21].OUT_BEL[17]	GTX[2].TSTOUT[1]
CELL[21].OUT_BEL[18]	GTX[2].RXDATA[26]
CELL[21].OUT_BEL[19]	GTX[2].TSTOUT[7]
CELL[21].OUT_BEL[20]	GTX[2].TSTOUT[3]
CELL[21].OUT_BEL[21]	GTX[2].TSTOUT[0]
CELL[21].OUT_BEL[22]	GTX[2].RXDATA[25]
CELL[21].OUT_BEL[23]	GTX[2].TSTOUT[5]
CELL[22].IMUX_CLK[0]	GTX[2].RXUSRCLK
CELL[22].IMUX_CLK[1]	GTX[2].RXUSRCLK2
CELL[22].IMUX_CTRL[0]	GTX[2].RXBUFRESET
CELL[22].IMUX_CTRL[1]	GTX[2].RXRESET
CELL[22].IMUX_IMUX_DELAY[8]	GTX[2].RXCHBONDSLAVE
CELL[22].IMUX_IMUX_DELAY[10]	GTX[2].RXCHBONDLEVEL[0]
CELL[22].IMUX_IMUX_DELAY[11]	GTX[2].RXCHBONDLEVEL[2]
CELL[22].IMUX_IMUX_DELAY[14]	GTX[2].USRCODEERR
CELL[22].IMUX_IMUX_DELAY[18]	GTX[2].CLKTESTSIG[1]
CELL[22].IMUX_IMUX_DELAY[19]	GTX[2].CLKTESTSIG[0]
CELL[22].IMUX_IMUX_DELAY[20]	GTX[2].RXPLLLKDETEN
CELL[22].IMUX_IMUX_DELAY[21]	GTX[2].RXPLLPOWERDOWN
CELL[22].IMUX_IMUX_DELAY[24]	GTX[2].RXCHBONDMASTER
CELL[22].IMUX_IMUX_DELAY[26]	GTX[2].RXCHBONDLEVEL[1]
CELL[22].IMUX_IMUX_DELAY[27]	GTX[2].GTXTEST[12]
CELL[22].IMUX_IMUX_DELAY[28]	GTX[2].GTXTEST[11]
CELL[22].IMUX_IMUX_DELAY[29]	GTX[2].GTXTEST[10]
CELL[22].IMUX_IMUX_DELAY[30]	GTX[2].GTXTEST[9]
CELL[22].IMUX_IMUX_DELAY[31]	GTX[2].GTXTEST[8]
CELL[22].IMUX_IMUX_DELAY[32]	GTX[2].GTXTEST[7]
CELL[22].IMUX_IMUX_DELAY[33]	GTX[2].GTXTEST[6]
CELL[22].IMUX_IMUX_DELAY[34]	GTX[2].GTXTEST[5]
CELL[22].IMUX_IMUX_DELAY[35]	GTX[2].GTXTEST[4]
CELL[22].IMUX_IMUX_DELAY[36]	GTX[2].GTXTEST[3]
CELL[22].IMUX_IMUX_DELAY[37]	GTX[2].GTXTEST[2]
CELL[22].IMUX_IMUX_DELAY[38]	GTX[2].GTXTEST[1]
CELL[22].IMUX_IMUX_DELAY[39]	GTX[2].GTXTEST[0]
CELL[22].OUT_BEL[0]	GTX[2].RXLOSSOFSYNC[0]
CELL[22].OUT_BEL[1]	GTX[2].RXDATA[15]
CELL[22].OUT_BEL[2]	GTX[2].RXDATA[14]
CELL[22].OUT_BEL[3]	GTX[2].RXCHARISK[3]
CELL[22].OUT_BEL[4]	GTX[2].RXDATAVALID
CELL[22].OUT_BEL[5]	GTX[2].RXCHARISK[1]
CELL[22].OUT_BEL[6]	GTX[2].RXDATA[13]
CELL[22].OUT_BEL[7]	GTX[2].RXDATA[12]
CELL[22].OUT_BEL[8]	GTX[2].RXCHARISCOMMA[2]
CELL[22].OUT_BEL[10]	GTX[2].RXBYTEREALIGN
CELL[22].OUT_BEL[13]	GTX[2].RXBYTEISALIGNED
CELL[22].OUT_BEL[14]	GTX[2].RXCHANREALIGN
CELL[22].OUT_BEL[15]	GTX[2].RXCHARISK[2]
CELL[22].OUT_BEL[18]	GTX[2].RXCHARISCOMMA[3]
CELL[22].OUT_BEL[19]	GTX[2].COMSASDET
CELL[22].OUT_BEL[20]	GTX[2].COMINITDET
CELL[22].OUT_BEL[22]	GTX[2].RXLOSSOFSYNC[1]
CELL[22].OUT_BEL[23]	GTX[2].COMWAKEDET
CELL[23].IMUX_CLK[0]	GTX[2].GREFCLKRX
CELL[23].IMUX_CLK[1]	GTX[2].TSTCLK[0]
CELL[23].IMUX_CTRL[0]	GTX[2].PLLRXRESET
CELL[23].IMUX_IMUX_DELAY[0]	GTX[2].TXBUFDIFFCTRL[0]
CELL[23].IMUX_IMUX_DELAY[3]	GTX[2].TXDEEMPH
CELL[23].IMUX_IMUX_DELAY[5]	GTX[2].TXDIFFCTRL[2]
CELL[23].IMUX_IMUX_DELAY[9]	GTX[2].TXPREEMPHASIS[3]
CELL[23].IMUX_IMUX_DELAY[11]	GTX[2].LOOPBACK[1]
CELL[23].IMUX_IMUX_DELAY[12]	GTX[2].RXDLYALIGNTESTMODEENB
CELL[23].IMUX_IMUX_DELAY[13]	GTX[2].TXSWING
CELL[23].IMUX_IMUX_DELAY[16]	GTX[2].TXBUFDIFFCTRL[1]
CELL[23].IMUX_IMUX_DELAY[17]	GTX[2].TXPREEMPHASIS[2]
CELL[23].IMUX_IMUX_DELAY[18]	GTX[2].TXBUFDIFFCTRL[2]
CELL[23].IMUX_IMUX_DELAY[19]	GTX[2].TXPREEMPHASIS[1]
CELL[23].IMUX_IMUX_DELAY[21]	GTX[2].TXDIFFCTRL[0]
CELL[23].IMUX_IMUX_DELAY[22]	GTX[2].RXPLLREFSELDY[1]
CELL[23].IMUX_IMUX_DELAY[24]	GTX[2].LOOPBACK[0]
CELL[23].IMUX_IMUX_DELAY[25]	GTX[2].RXDLYALIGNFORCEROTATEB
CELL[23].IMUX_IMUX_DELAY[26]	GTX[2].TXPREEMPHASIS[0]
CELL[23].IMUX_IMUX_DELAY[27]	GTX[2].LOOPBACK[2]
CELL[23].IMUX_IMUX_DELAY[28]	GTX[2].RXDLYALIGNMONENB
CELL[23].IMUX_IMUX_DELAY[29]	GTX[2].RXDLYALIGNSWPPRECURB
CELL[23].IMUX_IMUX_DELAY[30]	GTX[2].TXDIFFCTRL[3]
CELL[23].IMUX_IMUX_DELAY[32]	GTX[2].RXCHBONDI[0]
CELL[23].IMUX_IMUX_DELAY[33]	GTX[2].RXCHBONDI[1]
CELL[23].IMUX_IMUX_DELAY[34]	GTX[2].RXCHBONDI[2]
CELL[23].IMUX_IMUX_DELAY[35]	GTX[2].RXCHBONDI[3]
CELL[23].IMUX_IMUX_DELAY[36]	GTX[2].RXCOMMADETUSE
CELL[23].IMUX_IMUX_DELAY[37]	GTX[2].RXPLLREFSELDY[0]
CELL[23].IMUX_IMUX_DELAY[38]	GTX[2].TXDIFFCTRL[1]
CELL[23].IMUX_IMUX_DELAY[39]	GTX[2].RXPLLREFSELDY[2]
CELL[23].OUT_BEL[0]	GTX[2].RXDISPERR[2]
CELL[23].OUT_BEL[1]	GTX[2].RXRUNDISP[3]
CELL[23].OUT_BEL[2]	GTX[2].RXCHARISCOMMA[1]
CELL[23].OUT_BEL[3]	GTX[2].RXNOTINTABLE[3]
CELL[23].OUT_BEL[4]	GTX[2].RXDISPERR[0]
CELL[23].OUT_BEL[5]	GTX[2].RXRUNDISP[1]
CELL[23].OUT_BEL[7]	GTX[2].RXNOTINTABLE[1]
CELL[23].OUT_BEL[8]	GTX[2].RXDISPERR[1]
CELL[23].OUT_BEL[9]	GTX[2].RXRUNDISP[0]
CELL[23].OUT_BEL[11]	GTX[2].RXNOTINTABLE[0]
CELL[23].OUT_BEL[13]	GTX[2].RXCHANISALIGNED
CELL[23].OUT_BEL[14]	GTX[2].RXCHARISCOMMA[0]
CELL[23].OUT_BEL[15]	GTX[2].RXNOTINTABLE[2]
CELL[23].OUT_BEL[16]	GTX[2].RXCHARISK[0]
CELL[23].OUT_BEL[19]	GTX[2].RXRUNDISP[2]
CELL[23].OUT_BEL[22]	GTX[2].RXDISPERR[3]
CELL[24].IMUX_CLK[1]	GTX[2].SCANCLK
CELL[24].IMUX_IMUX_DELAY[8]	GTX[2].DFETAP1[0]
CELL[24].IMUX_IMUX_DELAY[9]	GTX[2].TXDETECTRX
CELL[24].IMUX_IMUX_DELAY[10]	GTX[2].DFETAP1[1]
CELL[24].IMUX_IMUX_DELAY[11]	GTX[2].TXMARGIN[0]
CELL[24].IMUX_IMUX_DELAY[13]	GTX[2].RXPOWERDOWN[0]
CELL[24].IMUX_IMUX_DELAY[14]	GTX[2].DFETAP1[2]
CELL[24].IMUX_IMUX_DELAY[15]	GTX[2].DFETAP1[3]
CELL[24].IMUX_IMUX_DELAY[16]	GTX[2].DFECLKDLYADJ[5]
CELL[24].IMUX_IMUX_DELAY[17]	GTX[2].DFECLKDLYADJ[4]
CELL[24].IMUX_IMUX_DELAY[18]	GTX[2].DFECLKDLYADJ[2]
CELL[24].IMUX_IMUX_DELAY[19]	GTX[2].DFECLKDLYADJ[1]
CELL[24].IMUX_IMUX_DELAY[21]	GTX[2].RXPOWERDOWN[1]
CELL[24].IMUX_IMUX_DELAY[24]	GTX[2].DFETAP2[0]
CELL[24].IMUX_IMUX_DELAY[25]	GTX[2].DFETAP2[1]
CELL[24].IMUX_IMUX_DELAY[26]	GTX[2].TXMARGIN[1]
CELL[24].IMUX_IMUX_DELAY[28]	GTX[2].TXPOWERDOWN[0]
CELL[24].IMUX_IMUX_DELAY[29]	GTX[2].DFEDLYOVRD
CELL[24].IMUX_IMUX_DELAY[30]	GTX[2].DFETAP2[2]
CELL[24].IMUX_IMUX_DELAY[31]	GTX[2].DFETAP2[3]
CELL[24].IMUX_IMUX_DELAY[32]	GTX[2].TXELECIDLE
CELL[24].IMUX_IMUX_DELAY[33]	GTX[2].DFECLKDLYADJ[3]
CELL[24].IMUX_IMUX_DELAY[35]	GTX[2].DFECLKDLYADJ[0]
CELL[24].IMUX_IMUX_DELAY[36]	GTX[2].TXPOWERDOWN[1]
CELL[24].IMUX_IMUX_DELAY[37]	GTX[2].DFETAPOVRD
CELL[24].IMUX_IMUX_DELAY[38]	GTX[2].DFETAP1[4]
CELL[24].IMUX_IMUX_DELAY[39]	GTX[2].DFETAP2[4]
CELL[24].OUT_BEL[0]	GTX[2].MGTREFCLKFAB[0]
CELL[24].OUT_BEL[3]	GTX[2].RXBUFSTATUS[2]
CELL[24].OUT_BEL[4]	GTX[2].SCANOUT[1]
CELL[24].OUT_BEL[5]	GTX[2].RXPLLLKDET
CELL[24].OUT_BEL[6]	GTX[2].RXBUFSTATUS[0]
CELL[24].OUT_BEL[7]	GTX[2].RXBUFSTATUS[1]
CELL[24].OUT_BEL[8]	GTX[2].PHYSTATUS
CELL[24].OUT_BEL[10]	GTX[2].RXCHBONDO[1]
CELL[24].OUT_BEL[11]	GTX[2].RXCHBONDO[2]
CELL[24].OUT_BEL[12]	GTX[2].MGTREFCLKFAB[1]
CELL[24].OUT_BEL[13]	GTX[2].RXSTATUS[2]
CELL[24].OUT_BEL[14]	GTX[2].RXSTATUS[0]
CELL[24].OUT_BEL[15]	GTX[2].RXCHBONDO[3]
CELL[24].OUT_BEL[16]	GTX[2].RXSTATUS[1]
CELL[24].OUT_BEL[17]	GTX[2].RXCHBONDO[0]
CELL[24].OUT_BEL[18]	GTX[2].SCANOUT[0]
CELL[24].OUT_BEL[22]	GTX[2].RXOVERSAMPLEERR
CELL[25].IMUX_CLK[1]	GTX[2].TSTCLK[1]
CELL[25].IMUX_CTRL[1]	GTX[2].PLLTXRESET
CELL[25].IMUX_IMUX_DELAY[2]	GTX[2].TXDLYALIGNUPDSW
CELL[25].IMUX_IMUX_DELAY[8]	GTX[2].TXHEADER[0]
CELL[25].IMUX_IMUX_DELAY[9]	GTX[2].TXPOLARITY
CELL[25].IMUX_IMUX_DELAY[10]	GTX[2].RXDLYALIGNUPDSW
CELL[25].IMUX_IMUX_DELAY[11]	GTX[2].TXBYPASS8B10B[0]
CELL[25].IMUX_IMUX_DELAY[13]	GTX[2].TXDLYALIGNRESET
CELL[25].IMUX_IMUX_DELAY[14]	GTX[2].RXDLYALIGNDISABLE
CELL[25].IMUX_IMUX_DELAY[15]	GTX[2].TXMARGIN[2]
CELL[25].IMUX_IMUX_DELAY[16]	GTX[2].TXHEADER[1]
CELL[25].IMUX_IMUX_DELAY[17]	GTX[2].TXINHIBIT
CELL[25].IMUX_IMUX_DELAY[18]	GTX[2].TXPMASETPHASE
CELL[25].IMUX_IMUX_DELAY[19]	GTX[2].TXBYPASS8B10B[3]
CELL[25].IMUX_IMUX_DELAY[21]	GTX[2].TXCHARDISPMODE[3]
CELL[25].IMUX_IMUX_DELAY[22]	GTX[2].TXCHARDISPVAL[3]
CELL[25].IMUX_IMUX_DELAY[23]	GTX[2].TXCHARISK[3]
CELL[25].IMUX_IMUX_DELAY[25]	GTX[2].TXDLYALIGNOVERRIDE
CELL[25].IMUX_IMUX_DELAY[26]	GTX[2].TXCHARISK[0]
CELL[25].IMUX_IMUX_DELAY[27]	GTX[2].TXBYPASS8B10B[1]
CELL[25].IMUX_IMUX_DELAY[28]	GTX[2].TXCHARDISPMODE[1]
CELL[25].IMUX_IMUX_DELAY[29]	GTX[2].RXDLYALIGNRESET
CELL[25].IMUX_IMUX_DELAY[30]	GTX[2].TXCHARDISPVAL[1]
CELL[25].IMUX_IMUX_DELAY[32]	GTX[2].TXHEADER[2]
CELL[25].IMUX_IMUX_DELAY[33]	GTX[2].RXDLYALIGNOVERRIDE
CELL[25].IMUX_IMUX_DELAY[34]	GTX[2].TXCHARDISPMODE[0]
CELL[25].IMUX_IMUX_DELAY[35]	GTX[2].TXBYPASS8B10B[2]
CELL[25].IMUX_IMUX_DELAY[36]	GTX[2].TXCHARISK[1]
CELL[25].IMUX_IMUX_DELAY[37]	GTX[2].TXCHARDISPMODE[2]
CELL[25].IMUX_IMUX_DELAY[38]	GTX[2].TXCHARDISPVAL[2]
CELL[25].IMUX_IMUX_DELAY[39]	GTX[2].TXCHARISK[2]
CELL[25].IMUX_IMUX_DELAY[44]	GTX[2].TXCHARDISPVAL[0]
CELL[25].IMUX_IMUX_DELAY[46]	GTX[2].TXDLYALIGNDISABLE
CELL[25].OUT_BEL[0]	GTX[2].RXDLYALIGNMONITOR[7]
CELL[25].OUT_BEL[1]	GTX[2].RXSTARTOFSEQ
CELL[25].OUT_BEL[2]	GTX[2].RXPRBSERR
CELL[25].OUT_BEL[3]	GTX[2].RXELECIDLE
CELL[25].OUT_BEL[4]	GTX[2].RXVALID
CELL[25].OUT_BEL[5]	GTX[2].RXRECCLKPCS
CELL[25].OUT_BEL[6]	GTX[2].RXCLKCORCNT[2]
CELL[25].OUT_BEL[7]	GTX[2].RXDLYALIGNMONITOR[2]
CELL[25].OUT_BEL[8]	GTX[2].RXCLKCORCNT[0]
CELL[25].OUT_BEL[9]	GTX[2].RXCLKCORCNT[1]
CELL[25].OUT_BEL[10]	GTX[2].RXHEADER[0]
CELL[25].OUT_BEL[11]	GTX[2].RXHEADERVALID
CELL[25].OUT_BEL[12]	GTX[2].RXCOMMADET
CELL[25].OUT_BEL[14]	GTX[2].RXCHANBONDSEQ
CELL[25].OUT_BEL[15]	GTX[2].RXDLYALIGNMONITOR[1]
CELL[25].OUT_BEL[16]	GTX[2].RXHEADER[1]
CELL[25].OUT_BEL[17]	GTX[2].RXHEADER[2]
CELL[25].OUT_BEL[18]	GTX[2].RXDLYALIGNMONITOR[6]
CELL[25].OUT_BEL[19]	GTX[2].RXDLYALIGNMONITOR[5]
CELL[25].OUT_BEL[20]	GTX[2].RXDLYALIGNMONITOR[3]
CELL[25].OUT_BEL[21]	GTX[2].RXDLYALIGNMONITOR[0]
CELL[25].OUT_BEL[22]	GTX[2].RXRESETDONE
CELL[25].OUT_BEL[23]	GTX[2].RXDLYALIGNMONITOR[4]
CELL[26].IMUX_CLK[0]	GTX[2].TXUSRCLK
CELL[26].IMUX_CLK[1]	GTX[2].TXUSRCLK2
CELL[26].IMUX_CTRL[0]	GTX[2].TXRESET
CELL[26].IMUX_CTRL[1]	GTX[2].GTXTXRESET
CELL[26].IMUX_IMUX_DELAY[3]	GTX[2].TXDATA[12]
CELL[26].IMUX_IMUX_DELAY[5]	GTX[2].TXDATA[14]
CELL[26].IMUX_IMUX_DELAY[8]	GTX[2].TXSEQUENCE[3]
CELL[26].IMUX_IMUX_DELAY[9]	GTX[2].DFETAP3[1]
CELL[26].IMUX_IMUX_DELAY[10]	GTX[2].DFETAP3[0]
CELL[26].IMUX_IMUX_DELAY[11]	GTX[2].TXSEQUENCE[0]
CELL[26].IMUX_IMUX_DELAY[12]	GTX[2].DFETAP3[2]
CELL[26].IMUX_IMUX_DELAY[13]	GTX[2].TXDATA[15]
CELL[26].IMUX_IMUX_DELAY[15]	GTX[2].TXENPRBSTST[2]
CELL[26].IMUX_IMUX_DELAY[17]	GTX[2].DFETAP3[3]
CELL[26].IMUX_IMUX_DELAY[19]	GTX[2].TXSEQUENCE[1]
CELL[26].IMUX_IMUX_DELAY[20]	GTX[2].DFETAP4[3]
CELL[26].IMUX_IMUX_DELAY[22]	GTX[2].TXSEQUENCE[5]
CELL[26].IMUX_IMUX_DELAY[23]	GTX[2].TXENPRBSTST[1]
CELL[26].IMUX_IMUX_DELAY[24]	GTX[2].TXSEQUENCE[4]
CELL[26].IMUX_IMUX_DELAY[25]	GTX[2].DFETAP4[1]
CELL[26].IMUX_IMUX_DELAY[26]	GTX[2].DFETAP4[0]
CELL[26].IMUX_IMUX_DELAY[28]	GTX[2].DFETAP4[2]
CELL[26].IMUX_IMUX_DELAY[30]	GTX[2].TXDATA[13]
CELL[26].IMUX_IMUX_DELAY[32]	GTX[2].GATERXELECIDLE
CELL[26].IMUX_IMUX_DELAY[33]	GTX[2].TXRATE[1]
CELL[26].IMUX_IMUX_DELAY[34]	GTX[2].TXRATE[0]
CELL[26].IMUX_IMUX_DELAY[35]	GTX[2].TXSEQUENCE[2]
CELL[26].IMUX_IMUX_DELAY[37]	GTX[2].IGNORESIGDET
CELL[26].IMUX_IMUX_DELAY[38]	GTX[2].TXSEQUENCE[6]
CELL[26].IMUX_IMUX_DELAY[39]	GTX[2].TXENPRBSTST[0]
CELL[26].IMUX_IMUX_DELAY[41]	GTX[2].RXRATE[1]
CELL[26].IMUX_IMUX_DELAY[42]	GTX[2].RXRATE[0]
CELL[26].OUT_BEL[1]	GTX[2].DFECLKDLYADJMON[1]
CELL[26].OUT_BEL[2]	GTX[2].DFECLKDLYADJMON[2]
CELL[26].OUT_BEL[3]	GTX[2].DFECLKDLYADJMON[5]
CELL[26].OUT_BEL[4]	GTX[2].TXGEARBOXREADY
CELL[26].OUT_BEL[5]	GTX[2].DFECLKDLYADJMON[0]
CELL[26].OUT_BEL[6]	GTX[2].DFECLKDLYADJMON[3]
CELL[26].OUT_BEL[7]	GTX[2].DFECLKDLYADJMON[4]
CELL[26].OUT_BEL[8]	GTX[2].TXOUTCLKPCS
CELL[26].OUT_BEL[10]	GTX[2].DFEEYEDACMON[2]
CELL[26].OUT_BEL[11]	GTX[2].DFEEYEDACMON[3]
CELL[26].OUT_BEL[13]	GTX[2].DFEEYEDACMON[0]
CELL[26].OUT_BEL[14]	GTX[2].DFEEYEDACMON[1]
CELL[26].OUT_BEL[15]	GTX[2].DFEEYEDACMON[4]
CELL[26].OUT_BEL[18]	GTX[2].DFESENSCAL[1]
CELL[26].OUT_BEL[19]	GTX[2].DFESENSCAL[0]
CELL[26].OUT_BEL[20]	GTX[2].RXRATEDONE
CELL[26].OUT_BEL[22]	GTX[2].DFESENSCAL[2]
CELL[26].OUT_BEL[23]	GTX[2].TXRATEDONE
CELL[27].IMUX_CLK[0]	GTX[2].GREFCLKTX
CELL[27].IMUX_IMUX_DELAY[9]	GTX[2].TXDLYALIGNFORCEROTATEB
CELL[27].IMUX_IMUX_DELAY[10]	GTX[2].TXCOMWAKE
CELL[27].IMUX_IMUX_DELAY[11]	GTX[2].TXDLYALIGNMONENB
CELL[27].IMUX_IMUX_DELAY[12]	GTX[2].TXPLLLKDETEN
CELL[27].IMUX_IMUX_DELAY[13]	GTX[2].TXDATA[10]
CELL[27].IMUX_IMUX_DELAY[14]	GTX[2].TXSTARTSEQ
CELL[27].IMUX_IMUX_DELAY[15]	GTX[2].TXDATA[8]
CELL[27].IMUX_IMUX_DELAY[18]	GTX[2].TXCOMINIT
CELL[27].IMUX_IMUX_DELAY[19]	GTX[2].TXCOMSAS
CELL[27].IMUX_IMUX_DELAY[21]	GTX[2].TXDATA[9]
CELL[27].IMUX_IMUX_DELAY[22]	GTX[2].TXENC8B10BUSE
CELL[27].IMUX_IMUX_DELAY[24]	GTX[2].TXDATA[23]
CELL[27].IMUX_IMUX_DELAY[25]	GTX[2].TXDATA[22]
CELL[27].IMUX_IMUX_DELAY[26]	GTX[2].TXDATA[7]
CELL[27].IMUX_IMUX_DELAY[27]	GTX[2].TXDATA[20]
CELL[27].IMUX_IMUX_DELAY[28]	GTX[2].TXDATA[21]
CELL[27].IMUX_IMUX_DELAY[29]	GTX[2].TXPLLPOWERDOWN
CELL[27].IMUX_IMUX_DELAY[30]	GTX[2].TXDLYALIGNTESTMODEENB
CELL[27].IMUX_IMUX_DELAY[32]	GTX[2].TXDATA[31]
CELL[27].IMUX_IMUX_DELAY[33]	GTX[2].TXDATA[30]
CELL[27].IMUX_IMUX_DELAY[34]	GTX[2].TXDATA[6]
CELL[27].IMUX_IMUX_DELAY[35]	GTX[2].TXDATA[28]
CELL[27].IMUX_IMUX_DELAY[36]	GTX[2].TXDATA[29]
CELL[27].IMUX_IMUX_DELAY[37]	GTX[2].TXPLLREFSELDY[0]
CELL[27].IMUX_IMUX_DELAY[38]	GTX[2].TXPLLREFSELDY[1]
CELL[27].IMUX_IMUX_DELAY[39]	GTX[2].TXPLLREFSELDY[2]
CELL[27].IMUX_IMUX_DELAY[40]	GTX[2].TXDATA[11]
CELL[27].OUT_BEL[0]	GTX[2].TXDLYALIGNMONITOR[7]
CELL[27].OUT_BEL[1]	GTX[2].DFETAP2MONITOR[0]
CELL[27].OUT_BEL[2]	GTX[2].DFETAP2MONITOR[1]
CELL[27].OUT_BEL[3]	GTX[2].DFETAP2MONITOR[4]
CELL[27].OUT_BEL[4]	GTX[2].TXDLYALIGNMONITOR[2]
CELL[27].OUT_BEL[5]	GTX[2].TXBUFSTATUS[0]
CELL[27].OUT_BEL[6]	GTX[2].DFETAP2MONITOR[2]
CELL[27].OUT_BEL[7]	GTX[2].DFETAP2MONITOR[3]
CELL[27].OUT_BEL[8]	GTX[2].DFETAP4MONITOR[1]
CELL[27].OUT_BEL[9]	GTX[2].DFETAP4MONITOR[2]
CELL[27].OUT_BEL[10]	GTX[2].TXKERR[1]
CELL[27].OUT_BEL[11]	GTX[2].TXKERR[2]
CELL[27].OUT_BEL[12]	GTX[2].DFETAP4MONITOR[0]
CELL[27].OUT_BEL[13]	GTX[2].DFETAP4MONITOR[3]
CELL[27].OUT_BEL[14]	GTX[2].TXKERR[0]
CELL[27].OUT_BEL[15]	GTX[2].TXKERR[3]
CELL[27].OUT_BEL[16]	GTX[2].TXDLYALIGNMONITOR[1]
CELL[27].OUT_BEL[17]	GTX[2].TXBUFSTATUS[1]
CELL[27].OUT_BEL[18]	GTX[2].TXDLYALIGNMONITOR[6]
CELL[27].OUT_BEL[19]	GTX[2].TXDLYALIGNMONITOR[5]
CELL[27].OUT_BEL[20]	GTX[2].TXDLYALIGNMONITOR[3]
CELL[27].OUT_BEL[21]	GTX[2].TXDLYALIGNMONITOR[0]
CELL[27].OUT_BEL[22]	GTX[2].TXRESETDONE
CELL[27].OUT_BEL[23]	GTX[2].TXDLYALIGNMONITOR[4]
CELL[28].IMUX_IMUX_DELAY[8]	GTX[2].DWE
CELL[28].IMUX_IMUX_DELAY[9]	GTX[2].SCANIN[4]
CELL[28].IMUX_IMUX_DELAY[10]	GTX[2].TXPOSTEMPHASIS[0]
CELL[28].IMUX_IMUX_DELAY[12]	GTX[2].TXPOSTEMPHASIS[2]
CELL[28].IMUX_IMUX_DELAY[13]	GTX[2].TXPRBSFORCEERR
CELL[28].IMUX_IMUX_DELAY[15]	GTX[2].TXPDOWNASYNCH
CELL[28].IMUX_IMUX_DELAY[16]	GTX[2].DEN
CELL[28].IMUX_IMUX_DELAY[17]	GTX[2].TXENPMAPHASEALIGN
CELL[28].IMUX_IMUX_DELAY[18]	GTX[2].TXPOSTEMPHASIS[1]
CELL[28].IMUX_IMUX_DELAY[19]	GTX[2].TXDATA[25]
CELL[28].IMUX_IMUX_DELAY[20]	GTX[2].TXPOSTEMPHASIS[3]
CELL[28].IMUX_IMUX_DELAY[22]	GTX[2].TXPOSTEMPHASIS[4]
CELL[28].IMUX_IMUX_DELAY[25]	GTX[2].SCANIN[1]
CELL[28].IMUX_IMUX_DELAY[26]	GTX[2].TXDATA[4]
CELL[28].IMUX_IMUX_DELAY[27]	GTX[2].TXDATA[19]
CELL[28].IMUX_IMUX_DELAY[28]	GTX[2].TXDATA[2]
CELL[28].IMUX_IMUX_DELAY[29]	GTX[2].TXDATA[18]
CELL[28].IMUX_IMUX_DELAY[30]	GTX[2].TXDATA[17]
CELL[28].IMUX_IMUX_DELAY[31]	GTX[2].TXDATA[16]
CELL[28].IMUX_IMUX_DELAY[32]	GTX[2].TXDATA[3]
CELL[28].IMUX_IMUX_DELAY[33]	GTX[2].SCANIN[0]
CELL[28].IMUX_IMUX_DELAY[34]	GTX[2].TXDATA[5]
CELL[28].IMUX_IMUX_DELAY[35]	GTX[2].TXDATA[27]
CELL[28].IMUX_IMUX_DELAY[36]	GTX[2].TXDATA[1]
CELL[28].IMUX_IMUX_DELAY[37]	GTX[2].TXDATA[26]
CELL[28].IMUX_IMUX_DELAY[38]	GTX[2].TXDATA[0]
CELL[28].IMUX_IMUX_DELAY[39]	GTX[2].TXDATA[24]
CELL[28].OUT_BEL[0]	GTX[2].DRDY
CELL[28].OUT_BEL[1]	GTX[2].DFETAP1MONITOR[0]
CELL[28].OUT_BEL[2]	GTX[2].DFETAP1MONITOR[1]
CELL[28].OUT_BEL[3]	GTX[2].DFETAP1MONITOR[4]
CELL[28].OUT_BEL[5]	GTX[2].TXPLLLKDET
CELL[28].OUT_BEL[6]	GTX[2].DFETAP1MONITOR[2]
CELL[28].OUT_BEL[7]	GTX[2].DFETAP1MONITOR[3]
CELL[28].OUT_BEL[8]	GTX[2].DFETAP3MONITOR[1]
CELL[28].OUT_BEL[9]	GTX[2].DFETAP3MONITOR[2]
CELL[28].OUT_BEL[10]	GTX[2].TXRUNDISP[1]
CELL[28].OUT_BEL[11]	GTX[2].TXRUNDISP[2]
CELL[28].OUT_BEL[12]	GTX[2].DFETAP3MONITOR[0]
CELL[28].OUT_BEL[13]	GTX[2].DFETAP3MONITOR[3]
CELL[28].OUT_BEL[14]	GTX[2].TXRUNDISP[0]
CELL[28].OUT_BEL[15]	GTX[2].TXRUNDISP[3]
CELL[28].OUT_BEL[18]	GTX[2].COMFINISH
CELL[29].IMUX_CLK[0]	GTX[2].DCLK
CELL[29].IMUX_IMUX_DELAY[8]	GTX[2].DI[0]
CELL[29].IMUX_IMUX_DELAY[9]	GTX[2].DI[1]
CELL[29].IMUX_IMUX_DELAY[10]	GTX[2].DI[2]
CELL[29].IMUX_IMUX_DELAY[11]	GTX[2].DI[3]
CELL[29].IMUX_IMUX_DELAY[12]	GTX[2].DI[4]
CELL[29].IMUX_IMUX_DELAY[13]	GTX[2].DI[5]
CELL[29].IMUX_IMUX_DELAY[14]	GTX[2].DI[6]
CELL[29].IMUX_IMUX_DELAY[15]	GTX[2].DI[7]
CELL[29].IMUX_IMUX_DELAY[16]	GTX[2].DI[8]
CELL[29].IMUX_IMUX_DELAY[17]	GTX[2].DI[9]
CELL[29].IMUX_IMUX_DELAY[18]	GTX[2].DI[10]
CELL[29].IMUX_IMUX_DELAY[19]	GTX[2].DI[11]
CELL[29].IMUX_IMUX_DELAY[20]	GTX[2].DI[12]
CELL[29].IMUX_IMUX_DELAY[21]	GTX[2].DI[13]
CELL[29].IMUX_IMUX_DELAY[22]	GTX[2].DI[14]
CELL[29].IMUX_IMUX_DELAY[23]	GTX[2].DI[15]
CELL[29].IMUX_IMUX_DELAY[32]	GTX[2].DADDR[0]
CELL[29].IMUX_IMUX_DELAY[33]	GTX[2].DADDR[1]
CELL[29].IMUX_IMUX_DELAY[34]	GTX[2].DADDR[2]
CELL[29].IMUX_IMUX_DELAY[35]	GTX[2].DADDR[3]
CELL[29].IMUX_IMUX_DELAY[36]	GTX[2].DADDR[4]
CELL[29].IMUX_IMUX_DELAY[37]	GTX[2].DADDR[5]
CELL[29].IMUX_IMUX_DELAY[38]	GTX[2].DADDR[6]
CELL[29].IMUX_IMUX_DELAY[39]	GTX[2].DADDR[7]
CELL[29].OUT_BEL[0]	GTX[2].DRPDO[7]
CELL[29].OUT_BEL[1]	GTX[2].DRPDO[4]
CELL[29].OUT_BEL[2]	GTX[2].DRPDO[3]
CELL[29].OUT_BEL[3]	GTX[2].DRPDO[0]
CELL[29].OUT_BEL[4]	GTX[2].DRPDO[6]
CELL[29].OUT_BEL[5]	GTX[2].DRPDO[5]
CELL[29].OUT_BEL[6]	GTX[2].DRPDO[2]
CELL[29].OUT_BEL[7]	GTX[2].DRPDO[1]
CELL[29].OUT_BEL[8]	GTX[2].DRPDO[14]
CELL[29].OUT_BEL[9]	GTX[2].DRPDO[13]
CELL[29].OUT_BEL[10]	GTX[2].DRPDO[10]
CELL[29].OUT_BEL[11]	GTX[2].DRPDO[9]
CELL[29].OUT_BEL[12]	GTX[2].DRPDO[15]
CELL[29].OUT_BEL[13]	GTX[2].DRPDO[12]
CELL[29].OUT_BEL[14]	GTX[2].DRPDO[11]
CELL[29].OUT_BEL[15]	GTX[2].DRPDO[8]
CELL[30].IMUX_CTRL[1]	GTX[3].PRBSCNTRESET
CELL[30].IMUX_IMUX_DELAY[0]	GTX[3].TSTIN[17]
CELL[30].IMUX_IMUX_DELAY[1]	GTX[3].TSTIN[18]
CELL[30].IMUX_IMUX_DELAY[8]	GTX[3].TSTIN[9]
CELL[30].IMUX_IMUX_DELAY[9]	GTX[3].TSTIN[7]
CELL[30].IMUX_IMUX_DELAY[10]	GTX[3].TSTIN[5]
CELL[30].IMUX_IMUX_DELAY[11]	GTX[3].TSTIN[3]
CELL[30].IMUX_IMUX_DELAY[13]	GTX[3].TSTIN[12]
CELL[30].IMUX_IMUX_DELAY[14]	GTX[3].TSTIN[1]
CELL[30].IMUX_IMUX_DELAY[16]	GTX[3].TSTIN[15]
CELL[30].IMUX_IMUX_DELAY[17]	GTX[3].TSTPWRDNOVRD
CELL[30].IMUX_IMUX_DELAY[18]	GTX[3].TSTPWRDN[1]
CELL[30].IMUX_IMUX_DELAY[19]	GTX[3].TSTPWRDN[3]
CELL[30].IMUX_IMUX_DELAY[21]	GTX[3].TSTIN[11]
CELL[30].IMUX_IMUX_DELAY[22]	GTX[3].SCANIN[3]
CELL[30].IMUX_IMUX_DELAY[24]	GTX[3].TSTIN[8]
CELL[30].IMUX_IMUX_DELAY[25]	GTX[3].TSTIN[6]
CELL[30].IMUX_IMUX_DELAY[26]	GTX[3].TSTIN[4]
CELL[30].IMUX_IMUX_DELAY[27]	GTX[3].TSTIN[2]
CELL[30].IMUX_IMUX_DELAY[28]	GTX[3].TSTIN[13]
CELL[30].IMUX_IMUX_DELAY[29]	GTX[3].SCANMODEB
CELL[30].IMUX_IMUX_DELAY[30]	GTX[3].TSTIN[0]
CELL[30].IMUX_IMUX_DELAY[31]	GTX[3].TSTIN[10]
CELL[30].IMUX_IMUX_DELAY[32]	GTX[3].TSTIN[14]
CELL[30].IMUX_IMUX_DELAY[33]	GTX[3].TSTPWRDN[0]
CELL[30].IMUX_IMUX_DELAY[34]	GTX[3].TSTPWRDN[2]
CELL[30].IMUX_IMUX_DELAY[35]	GTX[3].TSTPWRDN[4]
CELL[30].IMUX_IMUX_DELAY[37]	GTX[3].SCANENB
CELL[30].IMUX_IMUX_DELAY[38]	GTX[3].SCANIN[2]
CELL[30].IMUX_IMUX_DELAY[40]	GTX[3].TSTIN[16]
CELL[30].IMUX_IMUX_DELAY[41]	GTX[3].TSTIN[19]
CELL[30].OUT_BEL[0]	GTX[3].RXDATA[18]
CELL[30].OUT_BEL[1]	GTX[3].RXDATA[4]
CELL[30].OUT_BEL[2]	GTX[3].RXDATA[3]
CELL[30].OUT_BEL[3]	GTX[3].RXDATA[17]
CELL[30].OUT_BEL[4]	GTX[3].RXDATA[0]
CELL[30].OUT_BEL[5]	GTX[3].RXDATA[5]
CELL[30].OUT_BEL[6]	GTX[3].RXDATA[2]
CELL[30].OUT_BEL[7]	GTX[3].RXDATA[1]
CELL[30].OUT_BEL[8]	GTX[3].SCANOUT[4]
CELL[30].OUT_BEL[13]	GTX[3].SCANOUT[3]
CELL[30].OUT_BEL[15]	GTX[3].RXDATA[16]
CELL[30].OUT_BEL[16]	GTX[3].RXDATA[22]
CELL[30].OUT_BEL[17]	GTX[3].RXDATA[21]
CELL[30].OUT_BEL[18]	GTX[3].RXDATA[20]
CELL[30].OUT_BEL[20]	GTX[3].RXDATA[23]
CELL[30].OUT_BEL[22]	GTX[3].RXDATA[19]
CELL[30].OUT_BEL[23]	GTX[3].SCANOUT[2]
CELL[31].IMUX_CTRL[0]	GTX[3].GTXRXRESET
CELL[31].IMUX_CTRL[1]	GTX[3].RXCDRRESET
CELL[31].IMUX_IMUX_DELAY[9]	GTX[3].RXSLIDE
CELL[31].IMUX_IMUX_DELAY[11]	GTX[3].RXPMASETPHASE
CELL[31].IMUX_IMUX_DELAY[12]	GTX[3].RXGEARBOXSLIP
CELL[31].IMUX_IMUX_DELAY[14]	GTX[3].RXEQMIX[0]
CELL[31].IMUX_IMUX_DELAY[15]	GTX[3].RXEQMIX[1]
CELL[31].IMUX_IMUX_DELAY[18]	GTX[3].RXENPRBSTST[2]
CELL[31].IMUX_IMUX_DELAY[19]	GTX[3].RXEQMIX[9]
CELL[31].IMUX_IMUX_DELAY[20]	GTX[3].RXEQMIX[7]
CELL[31].IMUX_IMUX_DELAY[21]	GTX[3].RXEQMIX[5]
CELL[31].IMUX_IMUX_DELAY[22]	GTX[3].RXEQMIX[3]
CELL[31].IMUX_IMUX_DELAY[24]	GTX[3].RXBUFWE
CELL[31].IMUX_IMUX_DELAY[26]	GTX[3].RXPOLARITY
CELL[31].IMUX_IMUX_DELAY[27]	GTX[3].RXEQMIX[8]
CELL[31].IMUX_IMUX_DELAY[28]	GTX[3].RXEQMIX[6]
CELL[31].IMUX_IMUX_DELAY[29]	GTX[3].RXEQMIX[4]
CELL[31].IMUX_IMUX_DELAY[30]	GTX[3].RXEQMIX[2]
CELL[31].IMUX_IMUX_DELAY[32]	GTX[3].RXENSAMPLEALIGN
CELL[31].IMUX_IMUX_DELAY[33]	GTX[3].RXENPRBSTST[0]
CELL[31].IMUX_IMUX_DELAY[34]	GTX[3].RXENPRBSTST[1]
CELL[31].IMUX_IMUX_DELAY[35]	GTX[3].RXENPMAPHASEALIGN
CELL[31].IMUX_IMUX_DELAY[36]	GTX[3].RXENMCOMMAALIGN
CELL[31].IMUX_IMUX_DELAY[37]	GTX[3].RXENPCOMMAALIGN
CELL[31].IMUX_IMUX_DELAY[38]	GTX[3].RXENCHANSYNC
CELL[31].IMUX_IMUX_DELAY[39]	GTX[3].RXDEC8B10BUSE
CELL[31].OUT_BEL[0]	GTX[3].RXDATA[24]
CELL[31].OUT_BEL[1]	GTX[3].RXDATA[6]
CELL[31].OUT_BEL[2]	GTX[3].RXDATA[11]
CELL[31].OUT_BEL[3]	GTX[3].RXDATA[31]
CELL[31].OUT_BEL[4]	GTX[3].RXDATA[8]
CELL[31].OUT_BEL[5]	GTX[3].RXDATA[7]
CELL[31].OUT_BEL[6]	GTX[3].RXDATA[10]
CELL[31].OUT_BEL[7]	GTX[3].RXDATA[9]
CELL[31].OUT_BEL[8]	GTX[3].TSTOUT[8]
CELL[31].OUT_BEL[9]	GTX[3].RXDATA[27]
CELL[31].OUT_BEL[10]	GTX[3].TSTOUT[2]
CELL[31].OUT_BEL[11]	GTX[3].RXDATA[29]
CELL[31].OUT_BEL[12]	GTX[3].TSTOUT[9]
CELL[31].OUT_BEL[13]	GTX[3].TSTOUT[6]
CELL[31].OUT_BEL[14]	GTX[3].TSTOUT[4]
CELL[31].OUT_BEL[15]	GTX[3].RXDATA[30]
CELL[31].OUT_BEL[16]	GTX[3].RXDATA[28]
CELL[31].OUT_BEL[17]	GTX[3].TSTOUT[1]
CELL[31].OUT_BEL[18]	GTX[3].RXDATA[26]
CELL[31].OUT_BEL[19]	GTX[3].TSTOUT[7]
CELL[31].OUT_BEL[20]	GTX[3].TSTOUT[3]
CELL[31].OUT_BEL[21]	GTX[3].TSTOUT[0]
CELL[31].OUT_BEL[22]	GTX[3].RXDATA[25]
CELL[31].OUT_BEL[23]	GTX[3].TSTOUT[5]
CELL[32].IMUX_CLK[0]	GTX[3].RXUSRCLK
CELL[32].IMUX_CLK[1]	GTX[3].RXUSRCLK2
CELL[32].IMUX_CTRL[0]	GTX[3].RXBUFRESET
CELL[32].IMUX_CTRL[1]	GTX[3].RXRESET
CELL[32].IMUX_IMUX_DELAY[8]	GTX[3].RXCHBONDSLAVE
CELL[32].IMUX_IMUX_DELAY[10]	GTX[3].RXCHBONDLEVEL[0]
CELL[32].IMUX_IMUX_DELAY[11]	GTX[3].RXCHBONDLEVEL[2]
CELL[32].IMUX_IMUX_DELAY[14]	GTX[3].USRCODEERR
CELL[32].IMUX_IMUX_DELAY[18]	GTX[3].CLKTESTSIG[1]
CELL[32].IMUX_IMUX_DELAY[19]	GTX[3].CLKTESTSIG[0]
CELL[32].IMUX_IMUX_DELAY[20]	GTX[3].RXPLLLKDETEN
CELL[32].IMUX_IMUX_DELAY[21]	GTX[3].RXPLLPOWERDOWN
CELL[32].IMUX_IMUX_DELAY[24]	GTX[3].RXCHBONDMASTER
CELL[32].IMUX_IMUX_DELAY[26]	GTX[3].RXCHBONDLEVEL[1]
CELL[32].IMUX_IMUX_DELAY[27]	GTX[3].GTXTEST[12]
CELL[32].IMUX_IMUX_DELAY[28]	GTX[3].GTXTEST[11]
CELL[32].IMUX_IMUX_DELAY[29]	GTX[3].GTXTEST[10]
CELL[32].IMUX_IMUX_DELAY[30]	GTX[3].GTXTEST[9]
CELL[32].IMUX_IMUX_DELAY[31]	GTX[3].GTXTEST[8]
CELL[32].IMUX_IMUX_DELAY[32]	GTX[3].GTXTEST[7]
CELL[32].IMUX_IMUX_DELAY[33]	GTX[3].GTXTEST[6]
CELL[32].IMUX_IMUX_DELAY[34]	GTX[3].GTXTEST[5]
CELL[32].IMUX_IMUX_DELAY[35]	GTX[3].GTXTEST[4]
CELL[32].IMUX_IMUX_DELAY[36]	GTX[3].GTXTEST[3]
CELL[32].IMUX_IMUX_DELAY[37]	GTX[3].GTXTEST[2]
CELL[32].IMUX_IMUX_DELAY[38]	GTX[3].GTXTEST[1]
CELL[32].IMUX_IMUX_DELAY[39]	GTX[3].GTXTEST[0]
CELL[32].OUT_BEL[0]	GTX[3].RXLOSSOFSYNC[0]
CELL[32].OUT_BEL[1]	GTX[3].RXDATA[15]
CELL[32].OUT_BEL[2]	GTX[3].RXDATA[14]
CELL[32].OUT_BEL[3]	GTX[3].RXCHARISK[3]
CELL[32].OUT_BEL[4]	GTX[3].RXDATAVALID
CELL[32].OUT_BEL[5]	GTX[3].RXCHARISK[1]
CELL[32].OUT_BEL[6]	GTX[3].RXDATA[13]
CELL[32].OUT_BEL[7]	GTX[3].RXDATA[12]
CELL[32].OUT_BEL[8]	GTX[3].RXCHARISCOMMA[2]
CELL[32].OUT_BEL[10]	GTX[3].RXBYTEREALIGN
CELL[32].OUT_BEL[13]	GTX[3].RXBYTEISALIGNED
CELL[32].OUT_BEL[14]	GTX[3].RXCHANREALIGN
CELL[32].OUT_BEL[15]	GTX[3].RXCHARISK[2]
CELL[32].OUT_BEL[18]	GTX[3].RXCHARISCOMMA[3]
CELL[32].OUT_BEL[19]	GTX[3].COMSASDET
CELL[32].OUT_BEL[20]	GTX[3].COMINITDET
CELL[32].OUT_BEL[22]	GTX[3].RXLOSSOFSYNC[1]
CELL[32].OUT_BEL[23]	GTX[3].COMWAKEDET
CELL[33].IMUX_CLK[0]	GTX[3].GREFCLKRX
CELL[33].IMUX_CLK[1]	GTX[3].TSTCLK[0]
CELL[33].IMUX_CTRL[0]	GTX[3].PLLRXRESET
CELL[33].IMUX_IMUX_DELAY[0]	GTX[3].TXBUFDIFFCTRL[0]
CELL[33].IMUX_IMUX_DELAY[3]	GTX[3].TXDEEMPH
CELL[33].IMUX_IMUX_DELAY[5]	GTX[3].TXDIFFCTRL[2]
CELL[33].IMUX_IMUX_DELAY[9]	GTX[3].TXPREEMPHASIS[3]
CELL[33].IMUX_IMUX_DELAY[11]	GTX[3].LOOPBACK[1]
CELL[33].IMUX_IMUX_DELAY[12]	GTX[3].RXDLYALIGNTESTMODEENB
CELL[33].IMUX_IMUX_DELAY[13]	GTX[3].TXSWING
CELL[33].IMUX_IMUX_DELAY[16]	GTX[3].TXBUFDIFFCTRL[1]
CELL[33].IMUX_IMUX_DELAY[17]	GTX[3].TXPREEMPHASIS[2]
CELL[33].IMUX_IMUX_DELAY[18]	GTX[3].TXBUFDIFFCTRL[2]
CELL[33].IMUX_IMUX_DELAY[19]	GTX[3].TXPREEMPHASIS[1]
CELL[33].IMUX_IMUX_DELAY[21]	GTX[3].TXDIFFCTRL[0]
CELL[33].IMUX_IMUX_DELAY[22]	GTX[3].RXPLLREFSELDY[1]
CELL[33].IMUX_IMUX_DELAY[24]	GTX[3].LOOPBACK[0]
CELL[33].IMUX_IMUX_DELAY[25]	GTX[3].RXDLYALIGNFORCEROTATEB
CELL[33].IMUX_IMUX_DELAY[26]	GTX[3].TXPREEMPHASIS[0]
CELL[33].IMUX_IMUX_DELAY[27]	GTX[3].LOOPBACK[2]
CELL[33].IMUX_IMUX_DELAY[28]	GTX[3].RXDLYALIGNMONENB
CELL[33].IMUX_IMUX_DELAY[29]	GTX[3].RXDLYALIGNSWPPRECURB
CELL[33].IMUX_IMUX_DELAY[30]	GTX[3].TXDIFFCTRL[3]
CELL[33].IMUX_IMUX_DELAY[32]	GTX[3].RXCHBONDI[0]
CELL[33].IMUX_IMUX_DELAY[33]	GTX[3].RXCHBONDI[1]
CELL[33].IMUX_IMUX_DELAY[34]	GTX[3].RXCHBONDI[2]
CELL[33].IMUX_IMUX_DELAY[35]	GTX[3].RXCHBONDI[3]
CELL[33].IMUX_IMUX_DELAY[36]	GTX[3].RXCOMMADETUSE
CELL[33].IMUX_IMUX_DELAY[37]	GTX[3].RXPLLREFSELDY[0]
CELL[33].IMUX_IMUX_DELAY[38]	GTX[3].TXDIFFCTRL[1]
CELL[33].IMUX_IMUX_DELAY[39]	GTX[3].RXPLLREFSELDY[2]
CELL[33].OUT_BEL[0]	GTX[3].RXDISPERR[2]
CELL[33].OUT_BEL[1]	GTX[3].RXRUNDISP[3]
CELL[33].OUT_BEL[2]	GTX[3].RXCHARISCOMMA[1]
CELL[33].OUT_BEL[3]	GTX[3].RXNOTINTABLE[3]
CELL[33].OUT_BEL[4]	GTX[3].RXDISPERR[0]
CELL[33].OUT_BEL[5]	GTX[3].RXRUNDISP[1]
CELL[33].OUT_BEL[7]	GTX[3].RXNOTINTABLE[1]
CELL[33].OUT_BEL[8]	GTX[3].RXDISPERR[1]
CELL[33].OUT_BEL[9]	GTX[3].RXRUNDISP[0]
CELL[33].OUT_BEL[11]	GTX[3].RXNOTINTABLE[0]
CELL[33].OUT_BEL[13]	GTX[3].RXCHANISALIGNED
CELL[33].OUT_BEL[14]	GTX[3].RXCHARISCOMMA[0]
CELL[33].OUT_BEL[15]	GTX[3].RXNOTINTABLE[2]
CELL[33].OUT_BEL[16]	GTX[3].RXCHARISK[0]
CELL[33].OUT_BEL[19]	GTX[3].RXRUNDISP[2]
CELL[33].OUT_BEL[22]	GTX[3].RXDISPERR[3]
CELL[34].IMUX_CLK[1]	GTX[3].SCANCLK
CELL[34].IMUX_IMUX_DELAY[8]	GTX[3].DFETAP1[0]
CELL[34].IMUX_IMUX_DELAY[9]	GTX[3].TXDETECTRX
CELL[34].IMUX_IMUX_DELAY[10]	GTX[3].DFETAP1[1]
CELL[34].IMUX_IMUX_DELAY[11]	GTX[3].TXMARGIN[0]
CELL[34].IMUX_IMUX_DELAY[13]	GTX[3].RXPOWERDOWN[0]
CELL[34].IMUX_IMUX_DELAY[14]	GTX[3].DFETAP1[2]
CELL[34].IMUX_IMUX_DELAY[15]	GTX[3].DFETAP1[3]
CELL[34].IMUX_IMUX_DELAY[16]	GTX[3].DFECLKDLYADJ[5]
CELL[34].IMUX_IMUX_DELAY[17]	GTX[3].DFECLKDLYADJ[4]
CELL[34].IMUX_IMUX_DELAY[18]	GTX[3].DFECLKDLYADJ[2]
CELL[34].IMUX_IMUX_DELAY[19]	GTX[3].DFECLKDLYADJ[1]
CELL[34].IMUX_IMUX_DELAY[21]	GTX[3].RXPOWERDOWN[1]
CELL[34].IMUX_IMUX_DELAY[24]	GTX[3].DFETAP2[0]
CELL[34].IMUX_IMUX_DELAY[25]	GTX[3].DFETAP2[1]
CELL[34].IMUX_IMUX_DELAY[26]	GTX[3].TXMARGIN[1]
CELL[34].IMUX_IMUX_DELAY[28]	GTX[3].TXPOWERDOWN[0]
CELL[34].IMUX_IMUX_DELAY[29]	GTX[3].DFEDLYOVRD
CELL[34].IMUX_IMUX_DELAY[30]	GTX[3].DFETAP2[2]
CELL[34].IMUX_IMUX_DELAY[31]	GTX[3].DFETAP2[3]
CELL[34].IMUX_IMUX_DELAY[32]	GTX[3].TXELECIDLE
CELL[34].IMUX_IMUX_DELAY[33]	GTX[3].DFECLKDLYADJ[3]
CELL[34].IMUX_IMUX_DELAY[35]	GTX[3].DFECLKDLYADJ[0]
CELL[34].IMUX_IMUX_DELAY[36]	GTX[3].TXPOWERDOWN[1]
CELL[34].IMUX_IMUX_DELAY[37]	GTX[3].DFETAPOVRD
CELL[34].IMUX_IMUX_DELAY[38]	GTX[3].DFETAP1[4]
CELL[34].IMUX_IMUX_DELAY[39]	GTX[3].DFETAP2[4]
CELL[34].OUT_BEL[0]	GTX[3].MGTREFCLKFAB[0]
CELL[34].OUT_BEL[3]	GTX[3].RXBUFSTATUS[2]
CELL[34].OUT_BEL[4]	GTX[3].SCANOUT[1]
CELL[34].OUT_BEL[5]	GTX[3].RXPLLLKDET
CELL[34].OUT_BEL[6]	GTX[3].RXBUFSTATUS[0]
CELL[34].OUT_BEL[7]	GTX[3].RXBUFSTATUS[1]
CELL[34].OUT_BEL[8]	GTX[3].PHYSTATUS
CELL[34].OUT_BEL[10]	GTX[3].RXCHBONDO[1]
CELL[34].OUT_BEL[11]	GTX[3].RXCHBONDO[2]
CELL[34].OUT_BEL[12]	GTX[3].MGTREFCLKFAB[1]
CELL[34].OUT_BEL[13]	GTX[3].RXSTATUS[2]
CELL[34].OUT_BEL[14]	GTX[3].RXSTATUS[0]
CELL[34].OUT_BEL[15]	GTX[3].RXCHBONDO[3]
CELL[34].OUT_BEL[16]	GTX[3].RXSTATUS[1]
CELL[34].OUT_BEL[17]	GTX[3].RXCHBONDO[0]
CELL[34].OUT_BEL[18]	GTX[3].SCANOUT[0]
CELL[34].OUT_BEL[22]	GTX[3].RXOVERSAMPLEERR
CELL[35].IMUX_CLK[1]	GTX[3].TSTCLK[1]
CELL[35].IMUX_CTRL[1]	GTX[3].PLLTXRESET
CELL[35].IMUX_IMUX_DELAY[2]	GTX[3].TXDLYALIGNUPDSW
CELL[35].IMUX_IMUX_DELAY[8]	GTX[3].TXHEADER[0]
CELL[35].IMUX_IMUX_DELAY[9]	GTX[3].TXPOLARITY
CELL[35].IMUX_IMUX_DELAY[10]	GTX[3].RXDLYALIGNUPDSW
CELL[35].IMUX_IMUX_DELAY[11]	GTX[3].TXBYPASS8B10B[0]
CELL[35].IMUX_IMUX_DELAY[13]	GTX[3].TXDLYALIGNRESET
CELL[35].IMUX_IMUX_DELAY[14]	GTX[3].RXDLYALIGNDISABLE
CELL[35].IMUX_IMUX_DELAY[15]	GTX[3].TXMARGIN[2]
CELL[35].IMUX_IMUX_DELAY[16]	GTX[3].TXHEADER[1]
CELL[35].IMUX_IMUX_DELAY[17]	GTX[3].TXINHIBIT
CELL[35].IMUX_IMUX_DELAY[18]	GTX[3].TXPMASETPHASE
CELL[35].IMUX_IMUX_DELAY[19]	GTX[3].TXBYPASS8B10B[3]
CELL[35].IMUX_IMUX_DELAY[21]	GTX[3].TXCHARDISPMODE[3]
CELL[35].IMUX_IMUX_DELAY[22]	GTX[3].TXCHARDISPVAL[3]
CELL[35].IMUX_IMUX_DELAY[23]	GTX[3].TXCHARISK[3]
CELL[35].IMUX_IMUX_DELAY[25]	GTX[3].TXDLYALIGNOVERRIDE
CELL[35].IMUX_IMUX_DELAY[26]	GTX[3].TXCHARISK[0]
CELL[35].IMUX_IMUX_DELAY[27]	GTX[3].TXBYPASS8B10B[1]
CELL[35].IMUX_IMUX_DELAY[28]	GTX[3].TXCHARDISPMODE[1]
CELL[35].IMUX_IMUX_DELAY[29]	GTX[3].RXDLYALIGNRESET
CELL[35].IMUX_IMUX_DELAY[30]	GTX[3].TXCHARDISPVAL[1]
CELL[35].IMUX_IMUX_DELAY[32]	GTX[3].TXHEADER[2]
CELL[35].IMUX_IMUX_DELAY[33]	GTX[3].RXDLYALIGNOVERRIDE
CELL[35].IMUX_IMUX_DELAY[34]	GTX[3].TXCHARDISPMODE[0]
CELL[35].IMUX_IMUX_DELAY[35]	GTX[3].TXBYPASS8B10B[2]
CELL[35].IMUX_IMUX_DELAY[36]	GTX[3].TXCHARISK[1]
CELL[35].IMUX_IMUX_DELAY[37]	GTX[3].TXCHARDISPMODE[2]
CELL[35].IMUX_IMUX_DELAY[38]	GTX[3].TXCHARDISPVAL[2]
CELL[35].IMUX_IMUX_DELAY[39]	GTX[3].TXCHARISK[2]
CELL[35].IMUX_IMUX_DELAY[44]	GTX[3].TXCHARDISPVAL[0]
CELL[35].IMUX_IMUX_DELAY[46]	GTX[3].TXDLYALIGNDISABLE
CELL[35].OUT_BEL[0]	GTX[3].RXDLYALIGNMONITOR[7]
CELL[35].OUT_BEL[1]	GTX[3].RXSTARTOFSEQ
CELL[35].OUT_BEL[2]	GTX[3].RXPRBSERR
CELL[35].OUT_BEL[3]	GTX[3].RXELECIDLE
CELL[35].OUT_BEL[4]	GTX[3].RXVALID
CELL[35].OUT_BEL[5]	GTX[3].RXRECCLKPCS
CELL[35].OUT_BEL[6]	GTX[3].RXCLKCORCNT[2]
CELL[35].OUT_BEL[7]	GTX[3].RXDLYALIGNMONITOR[2]
CELL[35].OUT_BEL[8]	GTX[3].RXCLKCORCNT[0]
CELL[35].OUT_BEL[9]	GTX[3].RXCLKCORCNT[1]
CELL[35].OUT_BEL[10]	GTX[3].RXHEADER[0]
CELL[35].OUT_BEL[11]	GTX[3].RXHEADERVALID
CELL[35].OUT_BEL[12]	GTX[3].RXCOMMADET
CELL[35].OUT_BEL[14]	GTX[3].RXCHANBONDSEQ
CELL[35].OUT_BEL[15]	GTX[3].RXDLYALIGNMONITOR[1]
CELL[35].OUT_BEL[16]	GTX[3].RXHEADER[1]
CELL[35].OUT_BEL[17]	GTX[3].RXHEADER[2]
CELL[35].OUT_BEL[18]	GTX[3].RXDLYALIGNMONITOR[6]
CELL[35].OUT_BEL[19]	GTX[3].RXDLYALIGNMONITOR[5]
CELL[35].OUT_BEL[20]	GTX[3].RXDLYALIGNMONITOR[3]
CELL[35].OUT_BEL[21]	GTX[3].RXDLYALIGNMONITOR[0]
CELL[35].OUT_BEL[22]	GTX[3].RXRESETDONE
CELL[35].OUT_BEL[23]	GTX[3].RXDLYALIGNMONITOR[4]
CELL[36].IMUX_CLK[0]	GTX[3].TXUSRCLK
CELL[36].IMUX_CLK[1]	GTX[3].TXUSRCLK2
CELL[36].IMUX_CTRL[0]	GTX[3].TXRESET
CELL[36].IMUX_CTRL[1]	GTX[3].GTXTXRESET
CELL[36].IMUX_IMUX_DELAY[3]	GTX[3].TXDATA[12]
CELL[36].IMUX_IMUX_DELAY[5]	GTX[3].TXDATA[14]
CELL[36].IMUX_IMUX_DELAY[8]	GTX[3].TXSEQUENCE[3]
CELL[36].IMUX_IMUX_DELAY[9]	GTX[3].DFETAP3[1]
CELL[36].IMUX_IMUX_DELAY[10]	GTX[3].DFETAP3[0]
CELL[36].IMUX_IMUX_DELAY[11]	GTX[3].TXSEQUENCE[0]
CELL[36].IMUX_IMUX_DELAY[12]	GTX[3].DFETAP3[2]
CELL[36].IMUX_IMUX_DELAY[13]	GTX[3].TXDATA[15]
CELL[36].IMUX_IMUX_DELAY[15]	GTX[3].TXENPRBSTST[2]
CELL[36].IMUX_IMUX_DELAY[17]	GTX[3].DFETAP3[3]
CELL[36].IMUX_IMUX_DELAY[19]	GTX[3].TXSEQUENCE[1]
CELL[36].IMUX_IMUX_DELAY[20]	GTX[3].DFETAP4[3]
CELL[36].IMUX_IMUX_DELAY[22]	GTX[3].TXSEQUENCE[5]
CELL[36].IMUX_IMUX_DELAY[23]	GTX[3].TXENPRBSTST[1]
CELL[36].IMUX_IMUX_DELAY[24]	GTX[3].TXSEQUENCE[4]
CELL[36].IMUX_IMUX_DELAY[25]	GTX[3].DFETAP4[1]
CELL[36].IMUX_IMUX_DELAY[26]	GTX[3].DFETAP4[0]
CELL[36].IMUX_IMUX_DELAY[28]	GTX[3].DFETAP4[2]
CELL[36].IMUX_IMUX_DELAY[30]	GTX[3].TXDATA[13]
CELL[36].IMUX_IMUX_DELAY[32]	GTX[3].GATERXELECIDLE
CELL[36].IMUX_IMUX_DELAY[33]	GTX[3].TXRATE[1]
CELL[36].IMUX_IMUX_DELAY[34]	GTX[3].TXRATE[0]
CELL[36].IMUX_IMUX_DELAY[35]	GTX[3].TXSEQUENCE[2]
CELL[36].IMUX_IMUX_DELAY[37]	GTX[3].IGNORESIGDET
CELL[36].IMUX_IMUX_DELAY[38]	GTX[3].TXSEQUENCE[6]
CELL[36].IMUX_IMUX_DELAY[39]	GTX[3].TXENPRBSTST[0]
CELL[36].IMUX_IMUX_DELAY[41]	GTX[3].RXRATE[1]
CELL[36].IMUX_IMUX_DELAY[42]	GTX[3].RXRATE[0]
CELL[36].OUT_BEL[1]	GTX[3].DFECLKDLYADJMON[1]
CELL[36].OUT_BEL[2]	GTX[3].DFECLKDLYADJMON[2]
CELL[36].OUT_BEL[3]	GTX[3].DFECLKDLYADJMON[5]
CELL[36].OUT_BEL[4]	GTX[3].TXGEARBOXREADY
CELL[36].OUT_BEL[5]	GTX[3].DFECLKDLYADJMON[0]
CELL[36].OUT_BEL[6]	GTX[3].DFECLKDLYADJMON[3]
CELL[36].OUT_BEL[7]	GTX[3].DFECLKDLYADJMON[4]
CELL[36].OUT_BEL[8]	GTX[3].TXOUTCLKPCS
CELL[36].OUT_BEL[10]	GTX[3].DFEEYEDACMON[2]
CELL[36].OUT_BEL[11]	GTX[3].DFEEYEDACMON[3]
CELL[36].OUT_BEL[13]	GTX[3].DFEEYEDACMON[0]
CELL[36].OUT_BEL[14]	GTX[3].DFEEYEDACMON[1]
CELL[36].OUT_BEL[15]	GTX[3].DFEEYEDACMON[4]
CELL[36].OUT_BEL[18]	GTX[3].DFESENSCAL[1]
CELL[36].OUT_BEL[19]	GTX[3].DFESENSCAL[0]
CELL[36].OUT_BEL[20]	GTX[3].RXRATEDONE
CELL[36].OUT_BEL[22]	GTX[3].DFESENSCAL[2]
CELL[36].OUT_BEL[23]	GTX[3].TXRATEDONE
CELL[37].IMUX_CLK[0]	GTX[3].GREFCLKTX
CELL[37].IMUX_IMUX_DELAY[9]	GTX[3].TXDLYALIGNFORCEROTATEB
CELL[37].IMUX_IMUX_DELAY[10]	GTX[3].TXCOMWAKE
CELL[37].IMUX_IMUX_DELAY[11]	GTX[3].TXDLYALIGNMONENB
CELL[37].IMUX_IMUX_DELAY[12]	GTX[3].TXPLLLKDETEN
CELL[37].IMUX_IMUX_DELAY[13]	GTX[3].TXDATA[10]
CELL[37].IMUX_IMUX_DELAY[14]	GTX[3].TXSTARTSEQ
CELL[37].IMUX_IMUX_DELAY[15]	GTX[3].TXDATA[8]
CELL[37].IMUX_IMUX_DELAY[18]	GTX[3].TXCOMINIT
CELL[37].IMUX_IMUX_DELAY[19]	GTX[3].TXCOMSAS
CELL[37].IMUX_IMUX_DELAY[21]	GTX[3].TXDATA[9]
CELL[37].IMUX_IMUX_DELAY[22]	GTX[3].TXENC8B10BUSE
CELL[37].IMUX_IMUX_DELAY[24]	GTX[3].TXDATA[23]
CELL[37].IMUX_IMUX_DELAY[25]	GTX[3].TXDATA[22]
CELL[37].IMUX_IMUX_DELAY[26]	GTX[3].TXDATA[7]
CELL[37].IMUX_IMUX_DELAY[27]	GTX[3].TXDATA[20]
CELL[37].IMUX_IMUX_DELAY[28]	GTX[3].TXDATA[21]
CELL[37].IMUX_IMUX_DELAY[29]	GTX[3].TXPLLPOWERDOWN
CELL[37].IMUX_IMUX_DELAY[30]	GTX[3].TXDLYALIGNTESTMODEENB
CELL[37].IMUX_IMUX_DELAY[32]	GTX[3].TXDATA[31]
CELL[37].IMUX_IMUX_DELAY[33]	GTX[3].TXDATA[30]
CELL[37].IMUX_IMUX_DELAY[34]	GTX[3].TXDATA[6]
CELL[37].IMUX_IMUX_DELAY[35]	GTX[3].TXDATA[28]
CELL[37].IMUX_IMUX_DELAY[36]	GTX[3].TXDATA[29]
CELL[37].IMUX_IMUX_DELAY[37]	GTX[3].TXPLLREFSELDY[0]
CELL[37].IMUX_IMUX_DELAY[38]	GTX[3].TXPLLREFSELDY[1]
CELL[37].IMUX_IMUX_DELAY[39]	GTX[3].TXPLLREFSELDY[2]
CELL[37].IMUX_IMUX_DELAY[40]	GTX[3].TXDATA[11]
CELL[37].OUT_BEL[0]	GTX[3].TXDLYALIGNMONITOR[7]
CELL[37].OUT_BEL[1]	GTX[3].DFETAP2MONITOR[0]
CELL[37].OUT_BEL[2]	GTX[3].DFETAP2MONITOR[1]
CELL[37].OUT_BEL[3]	GTX[3].DFETAP2MONITOR[4]
CELL[37].OUT_BEL[4]	GTX[3].TXDLYALIGNMONITOR[2]
CELL[37].OUT_BEL[5]	GTX[3].TXBUFSTATUS[0]
CELL[37].OUT_BEL[6]	GTX[3].DFETAP2MONITOR[2]
CELL[37].OUT_BEL[7]	GTX[3].DFETAP2MONITOR[3]
CELL[37].OUT_BEL[8]	GTX[3].DFETAP4MONITOR[1]
CELL[37].OUT_BEL[9]	GTX[3].DFETAP4MONITOR[2]
CELL[37].OUT_BEL[10]	GTX[3].TXKERR[1]
CELL[37].OUT_BEL[11]	GTX[3].TXKERR[2]
CELL[37].OUT_BEL[12]	GTX[3].DFETAP4MONITOR[0]
CELL[37].OUT_BEL[13]	GTX[3].DFETAP4MONITOR[3]
CELL[37].OUT_BEL[14]	GTX[3].TXKERR[0]
CELL[37].OUT_BEL[15]	GTX[3].TXKERR[3]
CELL[37].OUT_BEL[16]	GTX[3].TXDLYALIGNMONITOR[1]
CELL[37].OUT_BEL[17]	GTX[3].TXBUFSTATUS[1]
CELL[37].OUT_BEL[18]	GTX[3].TXDLYALIGNMONITOR[6]
CELL[37].OUT_BEL[19]	GTX[3].TXDLYALIGNMONITOR[5]
CELL[37].OUT_BEL[20]	GTX[3].TXDLYALIGNMONITOR[3]
CELL[37].OUT_BEL[21]	GTX[3].TXDLYALIGNMONITOR[0]
CELL[37].OUT_BEL[22]	GTX[3].TXRESETDONE
CELL[37].OUT_BEL[23]	GTX[3].TXDLYALIGNMONITOR[4]
CELL[38].IMUX_IMUX_DELAY[8]	GTX[3].DWE
CELL[38].IMUX_IMUX_DELAY[9]	GTX[3].SCANIN[4]
CELL[38].IMUX_IMUX_DELAY[10]	GTX[3].TXPOSTEMPHASIS[0]
CELL[38].IMUX_IMUX_DELAY[12]	GTX[3].TXPOSTEMPHASIS[2]
CELL[38].IMUX_IMUX_DELAY[13]	GTX[3].TXPRBSFORCEERR
CELL[38].IMUX_IMUX_DELAY[15]	GTX[3].TXPDOWNASYNCH
CELL[38].IMUX_IMUX_DELAY[16]	GTX[3].DEN
CELL[38].IMUX_IMUX_DELAY[17]	GTX[3].TXENPMAPHASEALIGN
CELL[38].IMUX_IMUX_DELAY[18]	GTX[3].TXPOSTEMPHASIS[1]
CELL[38].IMUX_IMUX_DELAY[19]	GTX[3].TXDATA[25]
CELL[38].IMUX_IMUX_DELAY[20]	GTX[3].TXPOSTEMPHASIS[3]
CELL[38].IMUX_IMUX_DELAY[22]	GTX[3].TXPOSTEMPHASIS[4]
CELL[38].IMUX_IMUX_DELAY[25]	GTX[3].SCANIN[1]
CELL[38].IMUX_IMUX_DELAY[26]	GTX[3].TXDATA[4]
CELL[38].IMUX_IMUX_DELAY[27]	GTX[3].TXDATA[19]
CELL[38].IMUX_IMUX_DELAY[28]	GTX[3].TXDATA[2]
CELL[38].IMUX_IMUX_DELAY[29]	GTX[3].TXDATA[18]
CELL[38].IMUX_IMUX_DELAY[30]	GTX[3].TXDATA[17]
CELL[38].IMUX_IMUX_DELAY[31]	GTX[3].TXDATA[16]
CELL[38].IMUX_IMUX_DELAY[32]	GTX[3].TXDATA[3]
CELL[38].IMUX_IMUX_DELAY[33]	GTX[3].SCANIN[0]
CELL[38].IMUX_IMUX_DELAY[34]	GTX[3].TXDATA[5]
CELL[38].IMUX_IMUX_DELAY[35]	GTX[3].TXDATA[27]
CELL[38].IMUX_IMUX_DELAY[36]	GTX[3].TXDATA[1]
CELL[38].IMUX_IMUX_DELAY[37]	GTX[3].TXDATA[26]
CELL[38].IMUX_IMUX_DELAY[38]	GTX[3].TXDATA[0]
CELL[38].IMUX_IMUX_DELAY[39]	GTX[3].TXDATA[24]
CELL[38].OUT_BEL[0]	GTX[3].DRDY
CELL[38].OUT_BEL[1]	GTX[3].DFETAP1MONITOR[0]
CELL[38].OUT_BEL[2]	GTX[3].DFETAP1MONITOR[1]
CELL[38].OUT_BEL[3]	GTX[3].DFETAP1MONITOR[4]
CELL[38].OUT_BEL[5]	GTX[3].TXPLLLKDET
CELL[38].OUT_BEL[6]	GTX[3].DFETAP1MONITOR[2]
CELL[38].OUT_BEL[7]	GTX[3].DFETAP1MONITOR[3]
CELL[38].OUT_BEL[8]	GTX[3].DFETAP3MONITOR[1]
CELL[38].OUT_BEL[9]	GTX[3].DFETAP3MONITOR[2]
CELL[38].OUT_BEL[10]	GTX[3].TXRUNDISP[1]
CELL[38].OUT_BEL[11]	GTX[3].TXRUNDISP[2]
CELL[38].OUT_BEL[12]	GTX[3].DFETAP3MONITOR[0]
CELL[38].OUT_BEL[13]	GTX[3].DFETAP3MONITOR[3]
CELL[38].OUT_BEL[14]	GTX[3].TXRUNDISP[0]
CELL[38].OUT_BEL[15]	GTX[3].TXRUNDISP[3]
CELL[38].OUT_BEL[18]	GTX[3].COMFINISH
CELL[39].IMUX_CLK[0]	GTX[3].DCLK
CELL[39].IMUX_IMUX_DELAY[8]	GTX[3].DI[0]
CELL[39].IMUX_IMUX_DELAY[9]	GTX[3].DI[1]
CELL[39].IMUX_IMUX_DELAY[10]	GTX[3].DI[2]
CELL[39].IMUX_IMUX_DELAY[11]	GTX[3].DI[3]
CELL[39].IMUX_IMUX_DELAY[12]	GTX[3].DI[4]
CELL[39].IMUX_IMUX_DELAY[13]	GTX[3].DI[5]
CELL[39].IMUX_IMUX_DELAY[14]	GTX[3].DI[6]
CELL[39].IMUX_IMUX_DELAY[15]	GTX[3].DI[7]
CELL[39].IMUX_IMUX_DELAY[16]	GTX[3].DI[8]
CELL[39].IMUX_IMUX_DELAY[17]	GTX[3].DI[9]
CELL[39].IMUX_IMUX_DELAY[18]	GTX[3].DI[10]
CELL[39].IMUX_IMUX_DELAY[19]	GTX[3].DI[11]
CELL[39].IMUX_IMUX_DELAY[20]	GTX[3].DI[12]
CELL[39].IMUX_IMUX_DELAY[21]	GTX[3].DI[13]
CELL[39].IMUX_IMUX_DELAY[22]	GTX[3].DI[14]
CELL[39].IMUX_IMUX_DELAY[23]	GTX[3].DI[15]
CELL[39].IMUX_IMUX_DELAY[32]	GTX[3].DADDR[0]
CELL[39].IMUX_IMUX_DELAY[33]	GTX[3].DADDR[1]
CELL[39].IMUX_IMUX_DELAY[34]	GTX[3].DADDR[2]
CELL[39].IMUX_IMUX_DELAY[35]	GTX[3].DADDR[3]
CELL[39].IMUX_IMUX_DELAY[36]	GTX[3].DADDR[4]
CELL[39].IMUX_IMUX_DELAY[37]	GTX[3].DADDR[5]
CELL[39].IMUX_IMUX_DELAY[38]	GTX[3].DADDR[6]
CELL[39].IMUX_IMUX_DELAY[39]	GTX[3].DADDR[7]
CELL[39].OUT_BEL[0]	GTX[3].DRPDO[7]
CELL[39].OUT_BEL[1]	GTX[3].DRPDO[4]
CELL[39].OUT_BEL[2]	GTX[3].DRPDO[3]
CELL[39].OUT_BEL[3]	GTX[3].DRPDO[0]
CELL[39].OUT_BEL[4]	GTX[3].DRPDO[6]
CELL[39].OUT_BEL[5]	GTX[3].DRPDO[5]
CELL[39].OUT_BEL[6]	GTX[3].DRPDO[2]
CELL[39].OUT_BEL[7]	GTX[3].DRPDO[1]
CELL[39].OUT_BEL[8]	GTX[3].DRPDO[14]
CELL[39].OUT_BEL[9]	GTX[3].DRPDO[13]
CELL[39].OUT_BEL[10]	GTX[3].DRPDO[10]
CELL[39].OUT_BEL[11]	GTX[3].DRPDO[9]
CELL[39].OUT_BEL[12]	GTX[3].DRPDO[15]
CELL[39].OUT_BEL[13]	GTX[3].DRPDO[12]
CELL[39].OUT_BEL[14]	GTX[3].DRPDO[11]
CELL[39].OUT_BEL[15]	GTX[3].DRPDO[8]

Bitstream

virtex6 GTX rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[7] bit 14 GTX[0]: RX_IDLE_LO_CNT bit 2	GTX[0]: DRP[7] bit 15 GTX[0]: RX_IDLE_LO_CNT bit 3
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[7] bit 12 GTX[0]: RX_IDLE_LO_CNT bit 0	GTX[0]: DRP[7] bit 13 GTX[0]: RX_IDLE_LO_CNT bit 1
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[7] bit 10 GTX[0]: CHAN_BOND_SEQ_LEN bit 0	GTX[0]: DRP[7] bit 11 GTX[0]: CHAN_BOND_SEQ_LEN bit 1
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[7] bit 8 GTX[0]: CHAN_BOND_SEQ_1_4 bit 8	GTX[0]: DRP[7] bit 9 GTX[0]: CHAN_BOND_SEQ_1_4 bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[7] bit 6 GTX[0]: CHAN_BOND_SEQ_1_4 bit 6	GTX[0]: DRP[7] bit 7 GTX[0]: CHAN_BOND_SEQ_1_4 bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[7] bit 4 GTX[0]: CHAN_BOND_SEQ_1_4 bit 4	GTX[0]: DRP[7] bit 5 GTX[0]: CHAN_BOND_SEQ_1_4 bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[7] bit 2 GTX[0]: CHAN_BOND_SEQ_1_4 bit 2	GTX[0]: DRP[7] bit 3 GTX[0]: CHAN_BOND_SEQ_1_4 bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[7] bit 0 GTX[0]: CHAN_BOND_SEQ_1_4 bit 0	GTX[0]: DRP[7] bit 1 GTX[0]: CHAN_BOND_SEQ_1_4 bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[6] bit 14 GTX[0]: RX_LOS_INVALID_INCR bit 1	GTX[0]: DRP[6] bit 15 GTX[0]: RX_LOS_INVALID_INCR bit 2
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[6] bit 12 GTX[0]: RX_LOS_THRESHOLD bit 2	GTX[0]: DRP[6] bit 13 GTX[0]: RX_LOS_INVALID_INCR bit 0
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[6] bit 10 GTX[0]: RX_LOS_THRESHOLD bit 0	GTX[0]: DRP[6] bit 11 GTX[0]: RX_LOS_THRESHOLD bit 1
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[6] bit 8 GTX[0]: CHAN_BOND_SEQ_1_3 bit 8	GTX[0]: DRP[6] bit 9 GTX[0]: CHAN_BOND_SEQ_1_3 bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[6] bit 6 GTX[0]: CHAN_BOND_SEQ_1_3 bit 6	GTX[0]: DRP[6] bit 7 GTX[0]: CHAN_BOND_SEQ_1_3 bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[6] bit 4 GTX[0]: CHAN_BOND_SEQ_1_3 bit 4	GTX[0]: DRP[6] bit 5 GTX[0]: CHAN_BOND_SEQ_1_3 bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[6] bit 2 GTX[0]: CHAN_BOND_SEQ_1_3 bit 2	GTX[0]: DRP[6] bit 3 GTX[0]: CHAN_BOND_SEQ_1_3 bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[6] bit 0 GTX[0]: CHAN_BOND_SEQ_1_3 bit 0	GTX[0]: DRP[6] bit 1 GTX[0]: CHAN_BOND_SEQ_1_3 bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: !invert RXUSRCLK GTX[0]: DRP[5] bit 14	GTX[0]: !invert RXUSRCLK2 GTX[0]: DRP[5] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[5] bit 12 GTX[0]: CHAN_BOND_1_MAX_SKEW bit 2	GTX[0]: DRP[5] bit 13 GTX[0]: CHAN_BOND_1_MAX_SKEW bit 3
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[5] bit 10 GTX[0]: CHAN_BOND_1_MAX_SKEW bit 0	GTX[0]: DRP[5] bit 11 GTX[0]: CHAN_BOND_1_MAX_SKEW bit 1
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[5] bit 8 GTX[0]: CHAN_BOND_SEQ_1_2 bit 8	GTX[0]: DRP[5] bit 9 GTX[0]: CHAN_BOND_SEQ_1_2 bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[5] bit 6 GTX[0]: CHAN_BOND_SEQ_1_2 bit 6	GTX[0]: DRP[5] bit 7 GTX[0]: CHAN_BOND_SEQ_1_2 bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[5] bit 4 GTX[0]: CHAN_BOND_SEQ_1_2 bit 4	GTX[0]: DRP[5] bit 5 GTX[0]: CHAN_BOND_SEQ_1_2 bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[5] bit 2 GTX[0]: CHAN_BOND_SEQ_1_2 bit 2	GTX[0]: DRP[5] bit 3 GTX[0]: CHAN_BOND_SEQ_1_2 bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[5] bit 0 GTX[0]: CHAN_BOND_SEQ_1_2 bit 0	GTX[0]: DRP[5] bit 1 GTX[0]: CHAN_BOND_SEQ_1_2 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[4] bit 14 GTX[0]: RX_BUFFER_USE	GTX[0]: DRP[4] bit 15 GTX[0]: RX_LOSS_OF_SYNC_FSM
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[4] bit 12 GTX[0]: CHAN_BOND_SEQ_1_ENABLE bit 2	GTX[0]: DRP[4] bit 13 GTX[0]: CHAN_BOND_SEQ_1_ENABLE bit 3
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[4] bit 10 GTX[0]: CHAN_BOND_SEQ_1_ENABLE bit 0	GTX[0]: DRP[4] bit 11 GTX[0]: CHAN_BOND_SEQ_1_ENABLE bit 1
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[4] bit 8 GTX[0]: CHAN_BOND_SEQ_1_1 bit 8	GTX[0]: DRP[4] bit 9 GTX[0]: CHAN_BOND_SEQ_1_1 bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[4] bit 6 GTX[0]: CHAN_BOND_SEQ_1_1 bit 6	GTX[0]: DRP[4] bit 7 GTX[0]: CHAN_BOND_SEQ_1_1 bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[4] bit 4 GTX[0]: CHAN_BOND_SEQ_1_1 bit 4	GTX[0]: DRP[4] bit 5 GTX[0]: CHAN_BOND_SEQ_1_1 bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[4] bit 2 GTX[0]: CHAN_BOND_SEQ_1_1 bit 2	GTX[0]: DRP[4] bit 3 GTX[0]: CHAN_BOND_SEQ_1_1 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[4] bit 0 GTX[0]: CHAN_BOND_SEQ_1_1 bit 0	GTX[0]: DRP[4] bit 1 GTX[0]: CHAN_BOND_SEQ_1_1 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[3] bit 14 GTX[0]: BIAS_CFG bit 14	GTX[0]: DRP[3] bit 15 GTX[0]: BIAS_CFG bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[3] bit 12 GTX[0]: BIAS_CFG bit 12	GTX[0]: DRP[3] bit 13 GTX[0]: BIAS_CFG bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[3] bit 10 GTX[0]: BIAS_CFG bit 10	GTX[0]: DRP[3] bit 11 GTX[0]: BIAS_CFG bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[3] bit 8 GTX[0]: BIAS_CFG bit 8	GTX[0]: DRP[3] bit 9 GTX[0]: BIAS_CFG bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[3] bit 6 GTX[0]: BIAS_CFG bit 6	GTX[0]: DRP[3] bit 7 GTX[0]: BIAS_CFG bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[3] bit 4 GTX[0]: BIAS_CFG bit 4	GTX[0]: DRP[3] bit 5 GTX[0]: BIAS_CFG bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[3] bit 2 GTX[0]: BIAS_CFG bit 2	GTX[0]: DRP[3] bit 3 GTX[0]: BIAS_CFG bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[3] bit 0 GTX[0]: BIAS_CFG bit 0	GTX[0]: DRP[3] bit 1 GTX[0]: BIAS_CFG bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[2] bit 14 GTX[0]: RXUSRCLK_DLY bit 14	GTX[0]: DRP[2] bit 15 GTX[0]: RXUSRCLK_DLY bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[2] bit 12 GTX[0]: RXUSRCLK_DLY bit 12	GTX[0]: DRP[2] bit 13 GTX[0]: RXUSRCLK_DLY bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[2] bit 10 GTX[0]: RXUSRCLK_DLY bit 10	GTX[0]: DRP[2] bit 11 GTX[0]: RXUSRCLK_DLY bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[2] bit 8 GTX[0]: RXUSRCLK_DLY bit 8	GTX[0]: DRP[2] bit 9 GTX[0]: RXUSRCLK_DLY bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[2] bit 6 GTX[0]: RXUSRCLK_DLY bit 6	GTX[0]: DRP[2] bit 7 GTX[0]: RXUSRCLK_DLY bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[2] bit 4 GTX[0]: RXUSRCLK_DLY bit 4	GTX[0]: DRP[2] bit 5 GTX[0]: RXUSRCLK_DLY bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[2] bit 2 GTX[0]: RXUSRCLK_DLY bit 2	GTX[0]: DRP[2] bit 3 GTX[0]: RXUSRCLK_DLY bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[2] bit 0 GTX[0]: RXUSRCLK_DLY bit 0	GTX[0]: DRP[2] bit 1 GTX[0]: RXUSRCLK_DLY bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[1] bit 14 GTX[0]: PMA_RXSYNC_CFG bit 5	GTX[0]: DRP[1] bit 15 GTX[0]: PMA_RXSYNC_CFG bit 6
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[1] bit 12 GTX[0]: PMA_RXSYNC_CFG bit 3	GTX[0]: DRP[1] bit 13 GTX[0]: PMA_RXSYNC_CFG bit 4
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[1] bit 10 GTX[0]: PMA_RXSYNC_CFG bit 1	GTX[0]: DRP[1] bit 11 GTX[0]: PMA_RXSYNC_CFG bit 2
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[1] bit 8 GTX[0]: PMA_RX_CFG bit 24	GTX[0]: DRP[1] bit 9 GTX[0]: PMA_RXSYNC_CFG bit 0
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[1] bit 6 GTX[0]: PMA_RX_CFG bit 22	GTX[0]: DRP[1] bit 7 GTX[0]: PMA_RX_CFG bit 23
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[1] bit 4 GTX[0]: PMA_RX_CFG bit 20	GTX[0]: DRP[1] bit 5 GTX[0]: PMA_RX_CFG bit 21
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[1] bit 2 GTX[0]: PMA_RX_CFG bit 18	GTX[0]: DRP[1] bit 3 GTX[0]: PMA_RX_CFG bit 19
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[1] bit 0 GTX[0]: PMA_RX_CFG bit 16	GTX[0]: DRP[1] bit 1 GTX[0]: PMA_RX_CFG bit 17
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[0] bit 14 GTX[0]: PMA_RX_CFG bit 14	GTX[0]: DRP[0] bit 15 GTX[0]: PMA_RX_CFG bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[0] bit 12 GTX[0]: PMA_RX_CFG bit 12	GTX[0]: DRP[0] bit 13 GTX[0]: PMA_RX_CFG bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[0] bit 10 GTX[0]: PMA_RX_CFG bit 10	GTX[0]: DRP[0] bit 11 GTX[0]: PMA_RX_CFG bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[0] bit 8 GTX[0]: PMA_RX_CFG bit 8	GTX[0]: DRP[0] bit 9 GTX[0]: PMA_RX_CFG bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[0] bit 6 GTX[0]: PMA_RX_CFG bit 6	GTX[0]: DRP[0] bit 7 GTX[0]: PMA_RX_CFG bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[0] bit 4 GTX[0]: PMA_RX_CFG bit 4	GTX[0]: DRP[0] bit 5 GTX[0]: PMA_RX_CFG bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[0] bit 2 GTX[0]: PMA_RX_CFG bit 2	GTX[0]: DRP[0] bit 3 GTX[0]: PMA_RX_CFG bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[0] bit 0 GTX[0]: PMA_RX_CFG bit 0	GTX[0]: DRP[0] bit 1 GTX[0]: PMA_RX_CFG bit 1

virtex6 GTX rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[15] bit 14 GTX[0]: CLK_COR_MIN_LAT bit 4	GTX[0]: DRP[15] bit 15 GTX[0]: CLK_COR_MIN_LAT bit 5
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[15] bit 12 GTX[0]: CLK_COR_MIN_LAT bit 2	GTX[0]: DRP[15] bit 13 GTX[0]: CLK_COR_MIN_LAT bit 3
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[15] bit 10 GTX[0]: CLK_COR_MIN_LAT bit 0	GTX[0]: DRP[15] bit 11 GTX[0]: CLK_COR_MIN_LAT bit 1
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[15] bit 8 GTX[0]: CLK_COR_SEQ_1_3 bit 8	GTX[0]: DRP[15] bit 9 GTX[0]: CLK_COR_SEQ_1_3 bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[15] bit 6 GTX[0]: CLK_COR_SEQ_1_3 bit 6	GTX[0]: DRP[15] bit 7 GTX[0]: CLK_COR_SEQ_1_3 bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[15] bit 4 GTX[0]: CLK_COR_SEQ_1_3 bit 4	GTX[0]: DRP[15] bit 5 GTX[0]: CLK_COR_SEQ_1_3 bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[15] bit 2 GTX[0]: CLK_COR_SEQ_1_3 bit 2	GTX[0]: DRP[15] bit 3 GTX[0]: CLK_COR_SEQ_1_3 bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[15] bit 0 GTX[0]: CLK_COR_SEQ_1_3 bit 0	GTX[0]: DRP[15] bit 1 GTX[0]: CLK_COR_SEQ_1_3 bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[14] bit 14 GTX[0]: CLK_COR_REPEAT_WAIT bit 4	GTX[0]: DRP[14] bit 15 GTX[0]: CLK_COR_KEEP_IDLE
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[14] bit 12 GTX[0]: CLK_COR_REPEAT_WAIT bit 2	GTX[0]: DRP[14] bit 13 GTX[0]: CLK_COR_REPEAT_WAIT bit 3
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[14] bit 10 GTX[0]: CLK_COR_REPEAT_WAIT bit 0	GTX[0]: DRP[14] bit 11 GTX[0]: CLK_COR_REPEAT_WAIT bit 1
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[14] bit 8 GTX[0]: CLK_COR_SEQ_1_2 bit 8	GTX[0]: DRP[14] bit 9 GTX[0]: CLK_COR_SEQ_1_2 bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[14] bit 6 GTX[0]: CLK_COR_SEQ_1_2 bit 6	GTX[0]: DRP[14] bit 7 GTX[0]: CLK_COR_SEQ_1_2 bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[14] bit 4 GTX[0]: CLK_COR_SEQ_1_2 bit 4	GTX[0]: DRP[14] bit 5 GTX[0]: CLK_COR_SEQ_1_2 bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[14] bit 2 GTX[0]: CLK_COR_SEQ_1_2 bit 2	GTX[0]: DRP[14] bit 3 GTX[0]: CLK_COR_SEQ_1_2 bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[14] bit 0 GTX[0]: CLK_COR_SEQ_1_2 bit 0	GTX[0]: DRP[14] bit 1 GTX[0]: CLK_COR_SEQ_1_2 bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[13] bit 14 GTX[0]: CLK_CORRECT_USE	GTX[0]: DRP[13] bit 15 GTX[0]: CLK_COR_PRECEDENCE
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[13] bit 12 GTX[0]: CLK_COR_SEQ_1_ENABLE bit 2	GTX[0]: DRP[13] bit 13 GTX[0]: CLK_COR_SEQ_1_ENABLE bit 3
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[13] bit 10 GTX[0]: CLK_COR_SEQ_1_ENABLE bit 0	GTX[0]: DRP[13] bit 11 GTX[0]: CLK_COR_SEQ_1_ENABLE bit 1
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[13] bit 8 GTX[0]: CLK_COR_SEQ_1_1 bit 8	GTX[0]: DRP[13] bit 9 GTX[0]: CLK_COR_SEQ_1_1 bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[13] bit 6 GTX[0]: CLK_COR_SEQ_1_1 bit 6	GTX[0]: DRP[13] bit 7 GTX[0]: CLK_COR_SEQ_1_1 bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[13] bit 4 GTX[0]: CLK_COR_SEQ_1_1 bit 4	GTX[0]: DRP[13] bit 5 GTX[0]: CLK_COR_SEQ_1_1 bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[13] bit 2 GTX[0]: CLK_COR_SEQ_1_1 bit 2	GTX[0]: DRP[13] bit 3 GTX[0]: CLK_COR_SEQ_1_1 bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[13] bit 0 GTX[0]: CLK_COR_SEQ_1_1 bit 0	GTX[0]: DRP[13] bit 1 GTX[0]: CLK_COR_SEQ_1_1 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[12] bit 14	GTX[0]: DRP[12] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[12] bit 12 GTX[0]: RXBUF_OVRD_THRESH	GTX[0]: DRP[12] bit 13 GTX[0]: RX_FIFO_ADDR_MODE bit 0
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[12] bit 10 GTX[0]: RXBUF_UDFL_THRESH bit 4	GTX[0]: DRP[12] bit 11 GTX[0]: RXBUF_UDFL_THRESH bit 5
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[12] bit 8 GTX[0]: RXBUF_UDFL_THRESH bit 2	GTX[0]: DRP[12] bit 9 GTX[0]: RXBUF_UDFL_THRESH bit 3
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[12] bit 6 GTX[0]: RXBUF_UDFL_THRESH bit 0	GTX[0]: DRP[12] bit 7 GTX[0]: RXBUF_UDFL_THRESH bit 1
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[12] bit 4 GTX[0]: RXBUF_OVFL_THRESH bit 4	GTX[0]: DRP[12] bit 5 GTX[0]: RXBUF_OVFL_THRESH bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[12] bit 2 GTX[0]: RXBUF_OVFL_THRESH bit 2	GTX[0]: DRP[12] bit 3 GTX[0]: RXBUF_OVFL_THRESH bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[12] bit 0 GTX[0]: RXBUF_OVFL_THRESH bit 0	GTX[0]: DRP[12] bit 1 GTX[0]: RXBUF_OVFL_THRESH bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[11] bit 14 GTX[0]: RX_IDLE_HI_CNT bit 2	GTX[0]: DRP[11] bit 15 GTX[0]: RX_IDLE_HI_CNT bit 3
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[11] bit 12 GTX[0]: RX_IDLE_HI_CNT bit 0	GTX[0]: DRP[11] bit 13 GTX[0]: RX_IDLE_HI_CNT bit 1
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[11] bit 10 GTX[0]: RX_EN_IDLE_RESET_BUF	GTX[0]: DRP[11] bit 11 GTX[0]: RX_XCLK_SEL bit 0
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[11] bit 8 GTX[0]: CHAN_BOND_SEQ_2_4 bit 8	GTX[0]: DRP[11] bit 9 GTX[0]: CHAN_BOND_SEQ_2_4 bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[11] bit 6 GTX[0]: CHAN_BOND_SEQ_2_4 bit 6	GTX[0]: DRP[11] bit 7 GTX[0]: CHAN_BOND_SEQ_2_4 bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[11] bit 4 GTX[0]: CHAN_BOND_SEQ_2_4 bit 4	GTX[0]: DRP[11] bit 5 GTX[0]: CHAN_BOND_SEQ_2_4 bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[11] bit 2 GTX[0]: CHAN_BOND_SEQ_2_4 bit 2	GTX[0]: DRP[11] bit 3 GTX[0]: CHAN_BOND_SEQ_2_4 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[11] bit 0 GTX[0]: CHAN_BOND_SEQ_2_4 bit 0	GTX[0]: DRP[11] bit 1 GTX[0]: CHAN_BOND_SEQ_2_4 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[10] bit 14 GTX[0]: CHAN_BOND_SEQ_2_USE	GTX[0]: DRP[10] bit 15 GTX[0]: RX_EN_IDLE_RESET_PH
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[10] bit 12 GTX[0]: CHAN_BOND_SEQ_2_CFG bit 2	GTX[0]: DRP[10] bit 13 GTX[0]: CHAN_BOND_SEQ_2_CFG bit 3
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[10] bit 10 GTX[0]: CHAN_BOND_SEQ_2_CFG bit 0	GTX[0]: DRP[10] bit 11 GTX[0]: CHAN_BOND_SEQ_2_CFG bit 1
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[10] bit 8 GTX[0]: CHAN_BOND_SEQ_2_3 bit 8	GTX[0]: DRP[10] bit 9 GTX[0]: CHAN_BOND_SEQ_2_3 bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[10] bit 6 GTX[0]: CHAN_BOND_SEQ_2_3 bit 6	GTX[0]: DRP[10] bit 7 GTX[0]: CHAN_BOND_SEQ_2_3 bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[10] bit 4 GTX[0]: CHAN_BOND_SEQ_2_3 bit 4	GTX[0]: DRP[10] bit 5 GTX[0]: CHAN_BOND_SEQ_2_3 bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[10] bit 2 GTX[0]: CHAN_BOND_SEQ_2_3 bit 2	GTX[0]: DRP[10] bit 3 GTX[0]: CHAN_BOND_SEQ_2_3 bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[10] bit 0 GTX[0]: CHAN_BOND_SEQ_2_3 bit 0	GTX[0]: DRP[10] bit 1 GTX[0]: CHAN_BOND_SEQ_2_3 bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[9] bit 14 GTX[0]: CHAN_BOND_KEEP_ALIGN	GTX[0]: DRP[9] bit 15 GTX[0]: RX_EN_MODE_RESET_BUF
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[9] bit 12 GTX[0]: CHAN_BOND_2_MAX_SKEW bit 2	GTX[0]: DRP[9] bit 13 GTX[0]: CHAN_BOND_2_MAX_SKEW bit 3
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[9] bit 10 GTX[0]: CHAN_BOND_2_MAX_SKEW bit 0	GTX[0]: DRP[9] bit 11 GTX[0]: CHAN_BOND_2_MAX_SKEW bit 1
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[9] bit 8 GTX[0]: CHAN_BOND_SEQ_2_2 bit 8	GTX[0]: DRP[9] bit 9 GTX[0]: CHAN_BOND_SEQ_2_2 bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[9] bit 6 GTX[0]: CHAN_BOND_SEQ_2_2 bit 6	GTX[0]: DRP[9] bit 7 GTX[0]: CHAN_BOND_SEQ_2_2 bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[9] bit 4 GTX[0]: CHAN_BOND_SEQ_2_2 bit 4	GTX[0]: DRP[9] bit 5 GTX[0]: CHAN_BOND_SEQ_2_2 bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[9] bit 2 GTX[0]: CHAN_BOND_SEQ_2_2 bit 2	GTX[0]: DRP[9] bit 3 GTX[0]: CHAN_BOND_SEQ_2_2 bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[9] bit 0 GTX[0]: CHAN_BOND_SEQ_2_2 bit 0	GTX[0]: DRP[9] bit 1 GTX[0]: CHAN_BOND_SEQ_2_2 bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[8] bit 14 GTX[0]: RX_EN_REALIGN_RESET_BUF	GTX[0]: DRP[8] bit 15 GTX[0]: RX_EN_RATE_RESET_BUF
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[8] bit 12 GTX[0]: CHAN_BOND_SEQ_2_ENABLE bit 2	GTX[0]: DRP[8] bit 13 GTX[0]: CHAN_BOND_SEQ_2_ENABLE bit 3
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[8] bit 10 GTX[0]: CHAN_BOND_SEQ_2_ENABLE bit 0	GTX[0]: DRP[8] bit 11 GTX[0]: CHAN_BOND_SEQ_2_ENABLE bit 1
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[8] bit 8 GTX[0]: CHAN_BOND_SEQ_2_1 bit 8	GTX[0]: DRP[8] bit 9 GTX[0]: CHAN_BOND_SEQ_2_1 bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[8] bit 6 GTX[0]: CHAN_BOND_SEQ_2_1 bit 6	GTX[0]: DRP[8] bit 7 GTX[0]: CHAN_BOND_SEQ_2_1 bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[8] bit 4 GTX[0]: CHAN_BOND_SEQ_2_1 bit 4	GTX[0]: DRP[8] bit 5 GTX[0]: CHAN_BOND_SEQ_2_1 bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[8] bit 2 GTX[0]: CHAN_BOND_SEQ_2_1 bit 2	GTX[0]: DRP[8] bit 3 GTX[0]: CHAN_BOND_SEQ_2_1 bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[8] bit 0 GTX[0]: CHAN_BOND_SEQ_2_1 bit 0	GTX[0]: DRP[8] bit 1 GTX[0]: CHAN_BOND_SEQ_2_1 bit 1

virtex6 GTX rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[23] bit 14 GTX[0]: RX_DATA_WIDTH bit 2	GTX[0]: DRP[23] bit 15 GTX[0]: GEN_RXUSRCLK
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[23] bit 12 GTX[0]: RX_DATA_WIDTH bit 0	GTX[0]: DRP[23] bit 13 GTX[0]: RX_DATA_WIDTH bit 1
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[23] bit 10 GTX[0]: BIAS_CFG bit 16	GTX[0]: DRP[23] bit 11 GTX[0]: CHAN_BOND_SEQ_2_CFG bit 4
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[23] bit 8 GTX[0]: RX_CLK25_DIVIDER bit 3	GTX[0]: DRP[23] bit 9 GTX[0]: RX_CLK25_DIVIDER bit 4
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[23] bit 6 GTX[0]: RX_CLK25_DIVIDER bit 1	GTX[0]: DRP[23] bit 7 GTX[0]: RX_CLK25_DIVIDER bit 2
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[23] bit 4 GTX[0]: AC_CAP_DIS	GTX[0]: DRP[23] bit 5 GTX[0]: RX_CLK25_DIVIDER bit 0
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[23] bit 2 GTX[0]: OOBDETECT_THRESHOLD bit 2	GTX[0]: DRP[23] bit 3 GTX[0]: GTX_CFG_PWRUP
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[23] bit 0 GTX[0]: OOBDETECT_THRESHOLD bit 0	GTX[0]: DRP[23] bit 1 GTX[0]: OOBDETECT_THRESHOLD bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[22] bit 14 GTX[0]: CDR_PH_ADJ_TIME bit 3	GTX[0]: DRP[22] bit 15 GTX[0]: CDR_PH_ADJ_TIME bit 4
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[22] bit 12 GTX[0]: CDR_PH_ADJ_TIME bit 1	GTX[0]: DRP[22] bit 13 GTX[0]: CDR_PH_ADJ_TIME bit 2
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[22] bit 10 GTX[0]: PMA_CDR_SCAN bit 26	GTX[0]: DRP[22] bit 11 GTX[0]: CDR_PH_ADJ_TIME bit 0
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[22] bit 8 GTX[0]: PMA_CDR_SCAN bit 24	GTX[0]: DRP[22] bit 9 GTX[0]: PMA_CDR_SCAN bit 25
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[22] bit 6 GTX[0]: PMA_CDR_SCAN bit 22	GTX[0]: DRP[22] bit 7 GTX[0]: PMA_CDR_SCAN bit 23
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[22] bit 4 GTX[0]: PMA_CDR_SCAN bit 20	GTX[0]: DRP[22] bit 5 GTX[0]: PMA_CDR_SCAN bit 21
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[22] bit 2 GTX[0]: PMA_CDR_SCAN bit 18	GTX[0]: DRP[22] bit 3 GTX[0]: PMA_CDR_SCAN bit 19
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[22] bit 0 GTX[0]: PMA_CDR_SCAN bit 16	GTX[0]: DRP[22] bit 1 GTX[0]: PMA_CDR_SCAN bit 17
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[21] bit 14 GTX[0]: PMA_CDR_SCAN bit 14	GTX[0]: DRP[21] bit 15 GTX[0]: PMA_CDR_SCAN bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[21] bit 12 GTX[0]: PMA_CDR_SCAN bit 12	GTX[0]: DRP[21] bit 13 GTX[0]: PMA_CDR_SCAN bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[21] bit 10 GTX[0]: PMA_CDR_SCAN bit 10	GTX[0]: DRP[21] bit 11 GTX[0]: PMA_CDR_SCAN bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[21] bit 8 GTX[0]: PMA_CDR_SCAN bit 8	GTX[0]: DRP[21] bit 9 GTX[0]: PMA_CDR_SCAN bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[21] bit 6 GTX[0]: PMA_CDR_SCAN bit 6	GTX[0]: DRP[21] bit 7 GTX[0]: PMA_CDR_SCAN bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[21] bit 4 GTX[0]: PMA_CDR_SCAN bit 4	GTX[0]: DRP[21] bit 5 GTX[0]: PMA_CDR_SCAN bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[21] bit 2 GTX[0]: PMA_CDR_SCAN bit 2	GTX[0]: DRP[21] bit 3 GTX[0]: PMA_CDR_SCAN bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[21] bit 0 GTX[0]: PMA_CDR_SCAN bit 0	GTX[0]: DRP[21] bit 1 GTX[0]: PMA_CDR_SCAN bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[20] bit 14 GTX[0]: ALIGN_COMMA_WORD bit 0	GTX[0]: DRP[20] bit 15 GTX[0]: DEC_VALID_COMMA_ONLY
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[20] bit 12 GTX[0]: USR_CODE_ERR_CLR bit 0	GTX[0]: DRP[20] bit 13 GTX[0]: RX_DECODE_SEQ_MATCH
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[20] bit 10 GTX[0]: DEC_PCOMMA_DETECT	GTX[0]: DRP[20] bit 11 GTX[0]: DEC_MCOMMA_DETECT
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[20] bit 8 GTX[0]: CLK_COR_SEQ_2_4 bit 8	GTX[0]: DRP[20] bit 9 GTX[0]: CLK_COR_SEQ_2_4 bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[20] bit 6 GTX[0]: CLK_COR_SEQ_2_4 bit 6	GTX[0]: DRP[20] bit 7 GTX[0]: CLK_COR_SEQ_2_4 bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[20] bit 4 GTX[0]: CLK_COR_SEQ_2_4 bit 4	GTX[0]: DRP[20] bit 5 GTX[0]: CLK_COR_SEQ_2_4 bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[20] bit 2 GTX[0]: CLK_COR_SEQ_2_4 bit 2	GTX[0]: DRP[20] bit 3 GTX[0]: CLK_COR_SEQ_2_4 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[20] bit 0 GTX[0]: CLK_COR_SEQ_2_4 bit 0	GTX[0]: DRP[20] bit 1 GTX[0]: CLK_COR_SEQ_2_4 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[19] bit 14 GTX[0]: RX_SLIDE_AUTO_WAIT bit 2	GTX[0]: DRP[19] bit 15 GTX[0]: RX_SLIDE_AUTO_WAIT bit 3
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[19] bit 12 GTX[0]: RX_SLIDE_AUTO_WAIT bit 0	GTX[0]: DRP[19] bit 13 GTX[0]: RX_SLIDE_AUTO_WAIT bit 1
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[19] bit 10 GTX[0]: CLK_COR_DET_LEN bit 0	GTX[0]: DRP[19] bit 11 GTX[0]: CLK_COR_DET_LEN bit 1
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[19] bit 8 GTX[0]: CLK_COR_SEQ_2_3 bit 8	GTX[0]: DRP[19] bit 9 GTX[0]: CLK_COR_SEQ_2_3 bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[19] bit 6 GTX[0]: CLK_COR_SEQ_2_3 bit 6	GTX[0]: DRP[19] bit 7 GTX[0]: CLK_COR_SEQ_2_3 bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[19] bit 4 GTX[0]: CLK_COR_SEQ_2_3 bit 4	GTX[0]: DRP[19] bit 5 GTX[0]: CLK_COR_SEQ_2_3 bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[19] bit 2 GTX[0]: CLK_COR_SEQ_2_3 bit 2	GTX[0]: DRP[19] bit 3 GTX[0]: CLK_COR_SEQ_2_3 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[19] bit 0 GTX[0]: CLK_COR_SEQ_2_3 bit 0	GTX[0]: DRP[19] bit 1 GTX[0]: CLK_COR_SEQ_2_3 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[18] bit 14 GTX[0]: SHOW_REALIGN_COMMA	GTX[0]: DRP[18] bit 15 GTX[0]: RX_CDR_FORCE_ROTATE
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[18] bit 12 GTX[0]: RX_SLIDE_MODE bit 0	GTX[0]: DRP[18] bit 13 GTX[0]: RX_SLIDE_MODE bit 1
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[18] bit 10 GTX[0]: CLK_COR_ADJ_LEN bit 0	GTX[0]: DRP[18] bit 11 GTX[0]: CLK_COR_ADJ_LEN bit 1
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[18] bit 8 GTX[0]: CLK_COR_SEQ_2_2 bit 8	GTX[0]: DRP[18] bit 9 GTX[0]: CLK_COR_SEQ_2_2 bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[18] bit 6 GTX[0]: CLK_COR_SEQ_2_2 bit 6	GTX[0]: DRP[18] bit 7 GTX[0]: CLK_COR_SEQ_2_2 bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[18] bit 4 GTX[0]: CLK_COR_SEQ_2_2 bit 4	GTX[0]: DRP[18] bit 5 GTX[0]: CLK_COR_SEQ_2_2 bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[18] bit 2 GTX[0]: CLK_COR_SEQ_2_2 bit 2	GTX[0]: DRP[18] bit 3 GTX[0]: CLK_COR_SEQ_2_2 bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[18] bit 0 GTX[0]: CLK_COR_SEQ_2_2 bit 0	GTX[0]: DRP[18] bit 1 GTX[0]: CLK_COR_SEQ_2_2 bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[17] bit 14 GTX[0]: CLK_COR_SEQ_2_USE	GTX[0]: DRP[17] bit 15 GTX[0]: CLK_COR_INSERT_IDLE_FLAG
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[17] bit 12 GTX[0]: CLK_COR_SEQ_2_ENABLE bit 2	GTX[0]: DRP[17] bit 13 GTX[0]: CLK_COR_SEQ_2_ENABLE bit 3
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[17] bit 10 GTX[0]: CLK_COR_SEQ_2_ENABLE bit 0	GTX[0]: DRP[17] bit 11 GTX[0]: CLK_COR_SEQ_2_ENABLE bit 1
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[17] bit 8 GTX[0]: CLK_COR_SEQ_2_1 bit 8	GTX[0]: DRP[17] bit 9 GTX[0]: CLK_COR_SEQ_2_1 bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[17] bit 6 GTX[0]: CLK_COR_SEQ_2_1 bit 6	GTX[0]: DRP[17] bit 7 GTX[0]: CLK_COR_SEQ_2_1 bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[17] bit 4 GTX[0]: CLK_COR_SEQ_2_1 bit 4	GTX[0]: DRP[17] bit 5 GTX[0]: CLK_COR_SEQ_2_1 bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[17] bit 2 GTX[0]: CLK_COR_SEQ_2_1 bit 2	GTX[0]: DRP[17] bit 3 GTX[0]: CLK_COR_SEQ_2_1 bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[17] bit 0 GTX[0]: CLK_COR_SEQ_2_1 bit 0	GTX[0]: DRP[17] bit 1 GTX[0]: CLK_COR_SEQ_2_1 bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[16] bit 14 GTX[0]: CLK_COR_MAX_LAT bit 4	GTX[0]: DRP[16] bit 15 GTX[0]: CLK_COR_MAX_LAT bit 5
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[16] bit 12 GTX[0]: CLK_COR_MAX_LAT bit 2	GTX[0]: DRP[16] bit 13 GTX[0]: CLK_COR_MAX_LAT bit 3
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[16] bit 10 GTX[0]: CLK_COR_MAX_LAT bit 0	GTX[0]: DRP[16] bit 11 GTX[0]: CLK_COR_MAX_LAT bit 1
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[16] bit 8 GTX[0]: CLK_COR_SEQ_1_4 bit 8	GTX[0]: DRP[16] bit 9 GTX[0]: CLK_COR_SEQ_1_4 bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[16] bit 6 GTX[0]: CLK_COR_SEQ_1_4 bit 6	GTX[0]: DRP[16] bit 7 GTX[0]: CLK_COR_SEQ_1_4 bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[16] bit 4 GTX[0]: CLK_COR_SEQ_1_4 bit 4	GTX[0]: DRP[16] bit 5 GTX[0]: CLK_COR_SEQ_1_4 bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[16] bit 2 GTX[0]: CLK_COR_SEQ_1_4 bit 2	GTX[0]: DRP[16] bit 3 GTX[0]: CLK_COR_SEQ_1_4 bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[16] bit 0 GTX[0]: CLK_COR_SEQ_1_4 bit 0	GTX[0]: DRP[16] bit 1 GTX[0]: CLK_COR_SEQ_1_4 bit 1

virtex6 GTX rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[31] bit 14 GTX[0]: TXPLL_DIVSEL_OUT bit 0	GTX[0]: DRP[31] bit 15 GTX[0]: TXPLL_DIVSEL_OUT bit 1
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[31] bit 12 GTX[0]: TXPLL_LKDET_CFG bit 1	GTX[0]: DRP[31] bit 13 GTX[0]: TXPLL_LKDET_CFG bit 2
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[31] bit 10 GTX[0]: A_TXPOWERDOWN bit 1	GTX[0]: DRP[31] bit 11 GTX[0]: TXPLL_LKDET_CFG bit 0
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[31] bit 8 GTX[0]: TX_CLK_SOURCE bit 0	GTX[0]: DRP[31] bit 9 GTX[0]: A_TXPOWERDOWN bit 0
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[31] bit 6 GTX[0]: TXPLL_DIVSEL45_FB bit 0	GTX[0]: DRP[31] bit 7 GTX[0]: TXPLL_STARTUP_EN
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[31] bit 4 GTX[0]: TXPLL_DIVSEL_FB bit 3	GTX[0]: DRP[31] bit 5 GTX[0]: TXPLL_DIVSEL_FB bit 4
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[31] bit 2 GTX[0]: TXPLL_DIVSEL_FB bit 1	GTX[0]: DRP[31] bit 3 GTX[0]: TXPLL_DIVSEL_FB bit 2
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[31] bit 0	GTX[0]: DRP[31] bit 1 GTX[0]: TXPLL_DIVSEL_FB bit 0
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[30] bit 14 GTX[0]: TXPLL_CP_CFG bit 6	GTX[0]: DRP[30] bit 15 GTX[0]: TXPLL_CP_CFG bit 7
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[30] bit 12 GTX[0]: TXPLL_CP_CFG bit 4	GTX[0]: DRP[30] bit 13 GTX[0]: TXPLL_CP_CFG bit 5
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[30] bit 10 GTX[0]: TXPLL_CP_CFG bit 2	GTX[0]: DRP[30] bit 11 GTX[0]: TXPLL_CP_CFG bit 3
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[30] bit 8 GTX[0]: TXPLL_CP_CFG bit 0	GTX[0]: DRP[30] bit 9 GTX[0]: TXPLL_CP_CFG bit 1
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[30] bit 6 GTX[0]: TXPLL_COM_CFG bit 22	GTX[0]: DRP[30] bit 7 GTX[0]: TXPLL_COM_CFG bit 23
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[30] bit 4 GTX[0]: TXPLL_COM_CFG bit 20	GTX[0]: DRP[30] bit 5 GTX[0]: TXPLL_COM_CFG bit 21
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[30] bit 2 GTX[0]: TXPLL_COM_CFG bit 18	GTX[0]: DRP[30] bit 3 GTX[0]: TXPLL_COM_CFG bit 19
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[30] bit 0 GTX[0]: TXPLL_COM_CFG bit 16	GTX[0]: DRP[30] bit 1 GTX[0]: TXPLL_COM_CFG bit 17
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[29] bit 14 GTX[0]: TXPLL_COM_CFG bit 14	GTX[0]: DRP[29] bit 15 GTX[0]: TXPLL_COM_CFG bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[29] bit 12 GTX[0]: TXPLL_COM_CFG bit 12	GTX[0]: DRP[29] bit 13 GTX[0]: TXPLL_COM_CFG bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[29] bit 10 GTX[0]: TXPLL_COM_CFG bit 10	GTX[0]: DRP[29] bit 11 GTX[0]: TXPLL_COM_CFG bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[29] bit 8 GTX[0]: TXPLL_COM_CFG bit 8	GTX[0]: DRP[29] bit 9 GTX[0]: TXPLL_COM_CFG bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[29] bit 6 GTX[0]: TXPLL_COM_CFG bit 6	GTX[0]: DRP[29] bit 7 GTX[0]: TXPLL_COM_CFG bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[29] bit 4 GTX[0]: TXPLL_COM_CFG bit 4	GTX[0]: DRP[29] bit 5 GTX[0]: TXPLL_COM_CFG bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[29] bit 2 GTX[0]: TXPLL_COM_CFG bit 2	GTX[0]: DRP[29] bit 3 GTX[0]: TXPLL_COM_CFG bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[29] bit 0 GTX[0]: TXPLL_COM_CFG bit 0	GTX[0]: DRP[29] bit 1 GTX[0]: TXPLL_COM_CFG bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[28] bit 14 GTX[0]: A_RXPLLPOWERDOWN bit 0	GTX[0]: DRP[28] bit 15 GTX[0]: RX_OVERSAMPLE_MODE
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[28] bit 12 GTX[0]: A_PLLCLKRXRESET bit 0	GTX[0]: DRP[28] bit 13 GTX[0]: PLL_DRP_EN
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[28] bit 10 GTX[0]: A_PLLRXRESET bit 0	GTX[0]: DRP[28] bit 11 GTX[0]: A_RXPLLLKDETEN bit 0
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[28] bit 8 GTX[0]: RXPLLREFSEL_STATIC_VAL bit 1	GTX[0]: DRP[28] bit 9 GTX[0]: RXPLLREFSEL_STATIC_VAL bit 2
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[28] bit 6 GTX[0]: RXPLLREFSEL_MODE_DYNAMIC	GTX[0]: DRP[28] bit 7 GTX[0]: RXPLLREFSEL_STATIC_VAL bit 0
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[28] bit 4 GTX[0]: RXPLL_DIVSEL_REF bit 3	GTX[0]: DRP[28] bit 5 GTX[0]: RXPLL_DIVSEL_REF bit 4
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[28] bit 2 GTX[0]: RXPLL_DIVSEL_REF bit 1	GTX[0]: DRP[28] bit 3 GTX[0]: RXPLL_DIVSEL_REF bit 2
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[28] bit 0 GTX[0]: RXPLLREFSEL_TESTCLK bit 0	GTX[0]: DRP[28] bit 1 GTX[0]: RXPLL_DIVSEL_REF bit 0
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[27] bit 14 GTX[0]: RXPLL_DIVSEL_OUT bit 0	GTX[0]: DRP[27] bit 15 GTX[0]: RXPLL_DIVSEL_OUT bit 1
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[27] bit 12 GTX[0]: RXPLL_LKDET_CFG bit 1	GTX[0]: DRP[27] bit 13 GTX[0]: RXPLL_LKDET_CFG bit 2
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[27] bit 10 GTX[0]: A_RXPOWERDOWN bit 1	GTX[0]: DRP[27] bit 11 GTX[0]: RXPLL_LKDET_CFG bit 0
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[27] bit 8	GTX[0]: DRP[27] bit 9 GTX[0]: A_RXPOWERDOWN bit 0
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[27] bit 6 GTX[0]: RXPLL_DIVSEL45_FB bit 0	GTX[0]: DRP[27] bit 7 GTX[0]: RXPLL_STARTUP_EN
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[27] bit 4 GTX[0]: RXPLL_DIVSEL_FB bit 3	GTX[0]: DRP[27] bit 5 GTX[0]: RXPLL_DIVSEL_FB bit 4
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[27] bit 2 GTX[0]: RXPLL_DIVSEL_FB bit 1	GTX[0]: DRP[27] bit 3 GTX[0]: RXPLL_DIVSEL_FB bit 2
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[27] bit 0	GTX[0]: DRP[27] bit 1 GTX[0]: RXPLL_DIVSEL_FB bit 0
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[26] bit 14 GTX[0]: RXPLL_CP_CFG bit 6	GTX[0]: DRP[26] bit 15 GTX[0]: RXPLL_CP_CFG bit 7
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[26] bit 12 GTX[0]: RXPLL_CP_CFG bit 4	GTX[0]: DRP[26] bit 13 GTX[0]: RXPLL_CP_CFG bit 5
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[26] bit 10 GTX[0]: RXPLL_CP_CFG bit 2	GTX[0]: DRP[26] bit 11 GTX[0]: RXPLL_CP_CFG bit 3
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[26] bit 8 GTX[0]: RXPLL_CP_CFG bit 0	GTX[0]: DRP[26] bit 9 GTX[0]: RXPLL_CP_CFG bit 1
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[26] bit 6 GTX[0]: RXPLL_COM_CFG bit 22	GTX[0]: DRP[26] bit 7 GTX[0]: RXPLL_COM_CFG bit 23
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[26] bit 4 GTX[0]: RXPLL_COM_CFG bit 20	GTX[0]: DRP[26] bit 5 GTX[0]: RXPLL_COM_CFG bit 21
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[26] bit 2 GTX[0]: RXPLL_COM_CFG bit 18	GTX[0]: DRP[26] bit 3 GTX[0]: RXPLL_COM_CFG bit 19
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[26] bit 0 GTX[0]: RXPLL_COM_CFG bit 16	GTX[0]: DRP[26] bit 1 GTX[0]: RXPLL_COM_CFG bit 17
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[25] bit 14 GTX[0]: RXPLL_COM_CFG bit 14	GTX[0]: DRP[25] bit 15 GTX[0]: RXPLL_COM_CFG bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[25] bit 12 GTX[0]: RXPLL_COM_CFG bit 12	GTX[0]: DRP[25] bit 13 GTX[0]: RXPLL_COM_CFG bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[25] bit 10 GTX[0]: RXPLL_COM_CFG bit 10	GTX[0]: DRP[25] bit 11 GTX[0]: RXPLL_COM_CFG bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[25] bit 8 GTX[0]: RXPLL_COM_CFG bit 8	GTX[0]: DRP[25] bit 9 GTX[0]: RXPLL_COM_CFG bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[25] bit 6 GTX[0]: RXPLL_COM_CFG bit 6	GTX[0]: DRP[25] bit 7 GTX[0]: RXPLL_COM_CFG bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[25] bit 4 GTX[0]: RXPLL_COM_CFG bit 4	GTX[0]: DRP[25] bit 5 GTX[0]: RXPLL_COM_CFG bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[25] bit 2 GTX[0]: RXPLL_COM_CFG bit 2	GTX[0]: DRP[25] bit 3 GTX[0]: RXPLL_COM_CFG bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[25] bit 0 GTX[0]: RXPLL_COM_CFG bit 0	GTX[0]: DRP[25] bit 1 GTX[0]: RXPLL_COM_CFG bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[24] bit 14 GTX[0]: RESET_DRP_EN	GTX[0]: DRP[24] bit 15 GTX[0]: MASTER_DRP_EN
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[24] bit 12 GTX[0]: A_RXCDRPHASERESET bit 0	GTX[0]: DRP[24] bit 13 GTX[0]: A_RXDFERESET bit 0
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[24] bit 10 GTX[0]: A_RXCDRHOLD bit 0	GTX[0]: DRP[24] bit 11 GTX[0]: A_RXCDRFREQRESET bit 0
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[24] bit 8 GTX[0]: A_RXRESET bit 0	GTX[0]: DRP[24] bit 9 GTX[0]: A_TXRESET bit 0
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[24] bit 6 GTX[0]: A_GTXRXRESET bit 0	GTX[0]: DRP[24] bit 7 GTX[0]: A_RXBUFRESET bit 0
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[24] bit 4 GTX[0]: A_RXCDRRESET bit 0	GTX[0]: DRP[24] bit 5 GTX[0]: A_GTXTXRESET bit 0
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[24] bit 2 GTX[0]: GEARBOX_ENDEC bit 2	GTX[0]: DRP[24] bit 3 GTX[0]: RXGEARBOX_USE
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[24] bit 0 GTX[0]: GEARBOX_ENDEC bit 0	GTX[0]: DRP[24] bit 1 GTX[0]: GEARBOX_ENDEC bit 1

virtex6 GTX rect MAIN[4]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[39] bit 14 GTX[0]: SATA_IDLE_VAL bit 2	GTX[0]: DRP[39] bit 15 GTX[0]: TX_EN_RATE_RESET_BUF
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[39] bit 12 GTX[0]: SATA_IDLE_VAL bit 0	GTX[0]: DRP[39] bit 13 GTX[0]: SATA_IDLE_VAL bit 1
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[39] bit 10 GTX[0]: SATA_MIN_INIT bit 4	GTX[0]: DRP[39] bit 11 GTX[0]: SATA_MIN_INIT bit 5
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[39] bit 8 GTX[0]: SATA_MIN_INIT bit 2	GTX[0]: DRP[39] bit 9 GTX[0]: SATA_MIN_INIT bit 3
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[39] bit 6 GTX[0]: SATA_MIN_INIT bit 0	GTX[0]: DRP[39] bit 7 GTX[0]: SATA_MIN_INIT bit 1
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[39] bit 4 GTX[0]: SATA_MAX_INIT bit 4	GTX[0]: DRP[39] bit 5 GTX[0]: SATA_MAX_INIT bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[39] bit 2 GTX[0]: SATA_MAX_INIT bit 2	GTX[0]: DRP[39] bit 3 GTX[0]: SATA_MAX_INIT bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[39] bit 0 GTX[0]: SATA_MAX_INIT bit 0	GTX[0]: DRP[39] bit 1 GTX[0]: SATA_MAX_INIT bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[38] bit 14 GTX[0]: BGTEST_CFG bit 0	GTX[0]: DRP[38] bit 15 GTX[0]: BGTEST_CFG bit 1
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[38] bit 12 GTX[0]: TXPLL_SATA bit 0	GTX[0]: DRP[38] bit 13 GTX[0]: TXPLL_SATA bit 1
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[38] bit 10 GTX[0]: SATA_MIN_WAKE bit 4	GTX[0]: DRP[38] bit 11 GTX[0]: SATA_MIN_WAKE bit 5
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[38] bit 8 GTX[0]: SATA_MIN_WAKE bit 2	GTX[0]: DRP[38] bit 9 GTX[0]: SATA_MIN_WAKE bit 3
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[38] bit 6 GTX[0]: SATA_MIN_WAKE bit 0	GTX[0]: DRP[38] bit 7 GTX[0]: SATA_MIN_WAKE bit 1
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[38] bit 4 GTX[0]: SATA_MAX_WAKE bit 4	GTX[0]: DRP[38] bit 5 GTX[0]: SATA_MAX_WAKE bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[38] bit 2 GTX[0]: SATA_MAX_WAKE bit 2	GTX[0]: DRP[38] bit 3 GTX[0]: SATA_MAX_WAKE bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[38] bit 0 GTX[0]: SATA_MAX_WAKE bit 0	GTX[0]: DRP[38] bit 1 GTX[0]: SATA_MAX_WAKE bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[37] bit 14 GTX[0]: A_RXENPMAPHASEALIGN bit 0	GTX[0]: DRP[37] bit 15 GTX[0]: TX_PMADATA_OPT bit 0
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[37] bit 12 GTX[0]: POLARITY_DRP_EN	GTX[0]: DRP[37] bit 13 GTX[0]: A_RXPMASETPHASE bit 0
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[37] bit 10 GTX[0]: A_RXPOLARITY bit 0	GTX[0]: DRP[37] bit 11 GTX[0]: A_TXPOLARITY bit 0
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[37] bit 8 GTX[0]: CM_TRIM bit 0	GTX[0]: DRP[37] bit 9 GTX[0]: CM_TRIM bit 1
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[37] bit 6 GTX[0]: TRANS_TIME_NON_P2 bit 6	GTX[0]: DRP[37] bit 7 GTX[0]: TRANS_TIME_NON_P2 bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[37] bit 4 GTX[0]: TRANS_TIME_NON_P2 bit 4	GTX[0]: DRP[37] bit 5 GTX[0]: TRANS_TIME_NON_P2 bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[37] bit 2 GTX[0]: TRANS_TIME_NON_P2 bit 2	GTX[0]: DRP[37] bit 3 GTX[0]: TRANS_TIME_NON_P2 bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[37] bit 0 GTX[0]: TRANS_TIME_NON_P2 bit 0	GTX[0]: DRP[37] bit 1 GTX[0]: TRANS_TIME_NON_P2 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[36] bit 14 GTX[0]: COM_BURST_VAL bit 2	GTX[0]: DRP[36] bit 15 GTX[0]: COM_BURST_VAL bit 3
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[36] bit 12 GTX[0]: COM_BURST_VAL bit 0	GTX[0]: DRP[36] bit 13 GTX[0]: COM_BURST_VAL bit 1
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[36] bit 10 GTX[0]: TRANS_TIME_FROM_P2 bit 10	GTX[0]: DRP[36] bit 11 GTX[0]: TRANS_TIME_FROM_P2 bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[36] bit 8 GTX[0]: TRANS_TIME_FROM_P2 bit 8	GTX[0]: DRP[36] bit 9 GTX[0]: TRANS_TIME_FROM_P2 bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[36] bit 6 GTX[0]: TRANS_TIME_FROM_P2 bit 6	GTX[0]: DRP[36] bit 7 GTX[0]: TRANS_TIME_FROM_P2 bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[36] bit 4 GTX[0]: TRANS_TIME_FROM_P2 bit 4	GTX[0]: DRP[36] bit 5 GTX[0]: TRANS_TIME_FROM_P2 bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[36] bit 2 GTX[0]: TRANS_TIME_FROM_P2 bit 2	GTX[0]: DRP[36] bit 3 GTX[0]: TRANS_TIME_FROM_P2 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[36] bit 0 GTX[0]: TRANS_TIME_FROM_P2 bit 0	GTX[0]: DRP[36] bit 1 GTX[0]: TRANS_TIME_FROM_P2 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[35] bit 14 GTX[0]: TX_CLK25_DIVIDER bit 4	GTX[0]: DRP[35] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[35] bit 12 GTX[0]: TX_CLK25_DIVIDER bit 2	GTX[0]: DRP[35] bit 13 GTX[0]: TX_CLK25_DIVIDER bit 3
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[35] bit 10 GTX[0]: TX_CLK25_DIVIDER bit 0	GTX[0]: DRP[35] bit 11 GTX[0]: TX_CLK25_DIVIDER bit 1
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[35] bit 8 GTX[0]: TRANS_TIME_TO_P2 bit 8	GTX[0]: DRP[35] bit 9 GTX[0]: TRANS_TIME_TO_P2 bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[35] bit 6 GTX[0]: TRANS_TIME_TO_P2 bit 6	GTX[0]: DRP[35] bit 7 GTX[0]: TRANS_TIME_TO_P2 bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[35] bit 4 GTX[0]: TRANS_TIME_TO_P2 bit 4	GTX[0]: DRP[35] bit 5 GTX[0]: TRANS_TIME_TO_P2 bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[35] bit 2 GTX[0]: TRANS_TIME_TO_P2 bit 2	GTX[0]: DRP[35] bit 3 GTX[0]: TRANS_TIME_TO_P2 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[35] bit 0 GTX[0]: TRANS_TIME_TO_P2 bit 0	GTX[0]: DRP[35] bit 1 GTX[0]: TRANS_TIME_TO_P2 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[34] bit 14	GTX[0]: DRP[34] bit 15 GTX[0]: PMA_CAS_CLK_EN
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[34] bit 12	GTX[0]: DRP[34] bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[34] bit 10	GTX[0]: DRP[34] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[34] bit 8	GTX[0]: DRP[34] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[34] bit 6	GTX[0]: DRP[34] bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[34] bit 4	GTX[0]: DRP[34] bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[34] bit 2	GTX[0]: DRP[34] bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[34] bit 0	GTX[0]: DRP[34] bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[33] bit 14 GTX[0]: A_TXELECIDLE bit 0	GTX[0]: DRP[33] bit 15 GTX[0]: PCI_EXPRESS_MODE
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[33] bit 12 GTX[0]: TX_DETECT_RX_CFG bit 12	GTX[0]: DRP[33] bit 13 GTX[0]: TX_DETECT_RX_CFG bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[33] bit 10 GTX[0]: TX_DETECT_RX_CFG bit 10	GTX[0]: DRP[33] bit 11 GTX[0]: TX_DETECT_RX_CFG bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[33] bit 8 GTX[0]: TX_DETECT_RX_CFG bit 8	GTX[0]: DRP[33] bit 9 GTX[0]: TX_DETECT_RX_CFG bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[33] bit 6 GTX[0]: TX_DETECT_RX_CFG bit 6	GTX[0]: DRP[33] bit 7 GTX[0]: TX_DETECT_RX_CFG bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[33] bit 4 GTX[0]: TX_DETECT_RX_CFG bit 4	GTX[0]: DRP[33] bit 5 GTX[0]: TX_DETECT_RX_CFG bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[33] bit 2 GTX[0]: TX_DETECT_RX_CFG bit 2	GTX[0]: DRP[33] bit 3 GTX[0]: TX_DETECT_RX_CFG bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[33] bit 0 GTX[0]: TX_DETECT_RX_CFG bit 0	GTX[0]: DRP[33] bit 1 GTX[0]: TX_DETECT_RX_CFG bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[32] bit 14 GTX[0]: A_TXPLLPOWERDOWN bit 0	GTX[0]: DRP[32] bit 15 GTX[0]: TX_OVERSAMPLE_MODE
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[32] bit 12 GTX[0]: A_PLLCLKTXRESET bit 0	GTX[0]: DRP[32] bit 13 GTX[0]: PDELIDLE_DRP_EN
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[32] bit 10 GTX[0]: A_PLLTXRESET bit 0	GTX[0]: DRP[32] bit 11 GTX[0]: A_TXPLLLKDETEN bit 0
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[32] bit 8 GTX[0]: TXPLLREFSEL_STATIC_VAL bit 1	GTX[0]: DRP[32] bit 9 GTX[0]: TXPLLREFSEL_STATIC_VAL bit 2
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[32] bit 6 GTX[0]: TXPLLREFSEL_MODE_DYNAMIC	GTX[0]: DRP[32] bit 7 GTX[0]: TXPLLREFSEL_STATIC_VAL bit 0
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[32] bit 4 GTX[0]: TXPLL_DIVSEL_REF bit 3	GTX[0]: DRP[32] bit 5 GTX[0]: TXPLL_DIVSEL_REF bit 4
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[32] bit 2 GTX[0]: TXPLL_DIVSEL_REF bit 1	GTX[0]: DRP[32] bit 3 GTX[0]: TXPLL_DIVSEL_REF bit 2
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[32] bit 0 GTX[0]: TXPLLREFSEL_TESTCLK bit 0	GTX[0]: DRP[32] bit 1 GTX[0]: TXPLL_DIVSEL_REF bit 0

virtex6 GTX rect MAIN[5]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[47] bit 14 GTX[0]: TX_XCLK_SEL bit 0	GTX[0]: DRP[47] bit 15 GTX[0]: TXGEARBOX_USE
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[47] bit 12 GTX[0]: TX_IDLE_ASSERT_DELAY bit 1	GTX[0]: DRP[47] bit 13 GTX[0]: TX_IDLE_ASSERT_DELAY bit 2
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[47] bit 10 GTX[0]: COMMA_DOUBLE	GTX[0]: DRP[47] bit 11 GTX[0]: TX_IDLE_ASSERT_DELAY bit 0
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[47] bit 8 GTX[0]: COMMA_10B_ENABLE bit 8	GTX[0]: DRP[47] bit 9 GTX[0]: COMMA_10B_ENABLE bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[47] bit 6 GTX[0]: COMMA_10B_ENABLE bit 6	GTX[0]: DRP[47] bit 7 GTX[0]: COMMA_10B_ENABLE bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[47] bit 4 GTX[0]: COMMA_10B_ENABLE bit 4	GTX[0]: DRP[47] bit 5 GTX[0]: COMMA_10B_ENABLE bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[47] bit 2 GTX[0]: COMMA_10B_ENABLE bit 2	GTX[0]: DRP[47] bit 3 GTX[0]: COMMA_10B_ENABLE bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[47] bit 0 GTX[0]: COMMA_10B_ENABLE bit 0	GTX[0]: DRP[47] bit 1 GTX[0]: COMMA_10B_ENABLE bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[46] bit 14 GTX[0]: DFE_CAL_TIME bit 3	GTX[0]: DRP[46] bit 15 GTX[0]: DFE_CAL_TIME bit 4
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[46] bit 12 GTX[0]: DFE_CAL_TIME bit 1	GTX[0]: DRP[46] bit 13 GTX[0]: DFE_CAL_TIME bit 2
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[46] bit 10 GTX[0]: RX_EYE_SCANMODE bit 1	GTX[0]: DRP[46] bit 11 GTX[0]: DFE_CAL_TIME bit 0
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[46] bit 8 GTX[0]: RCV_TERM_VTTRX	GTX[0]: DRP[46] bit 9 GTX[0]: RX_EYE_SCANMODE bit 0
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[46] bit 6 GTX[0]: TERMINATION_OVRD	GTX[0]: DRP[46] bit 7 GTX[0]: RCV_TERM_GND
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[46] bit 4 GTX[0]: TERMINATION_CTRL bit 4	GTX[0]: DRP[46] bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[46] bit 2 GTX[0]: TERMINATION_CTRL bit 2	GTX[0]: DRP[46] bit 3 GTX[0]: TERMINATION_CTRL bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[46] bit 0 GTX[0]: TERMINATION_CTRL bit 0	GTX[0]: DRP[46] bit 1 GTX[0]: TERMINATION_CTRL bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[45] bit 14 GTX[0]: RX_EYE_OFFSET bit 6	GTX[0]: DRP[45] bit 15 GTX[0]: RX_EYE_OFFSET bit 7
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[45] bit 12 GTX[0]: RX_EYE_OFFSET bit 4	GTX[0]: DRP[45] bit 13 GTX[0]: RX_EYE_OFFSET bit 5
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[45] bit 10 GTX[0]: RX_EYE_OFFSET bit 2	GTX[0]: DRP[45] bit 11 GTX[0]: RX_EYE_OFFSET bit 3
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[45] bit 8 GTX[0]: RX_EYE_OFFSET bit 0	GTX[0]: DRP[45] bit 9 GTX[0]: RX_EYE_OFFSET bit 1
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[45] bit 6 GTX[0]: DFE_CFG bit 6	GTX[0]: DRP[45] bit 7 GTX[0]: DFE_CFG bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[45] bit 4 GTX[0]: DFE_CFG bit 4	GTX[0]: DRP[45] bit 5 GTX[0]: DFE_CFG bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[45] bit 2 GTX[0]: DFE_CFG bit 2	GTX[0]: DRP[45] bit 3 GTX[0]: DFE_CFG bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[45] bit 0 GTX[0]: DFE_CFG bit 0	GTX[0]: DRP[45] bit 1 GTX[0]: DFE_CFG bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[44] bit 14 GTX[0]: A_DFECLKDLYADJ bit 5	GTX[0]: DRP[44] bit 15 GTX[0]: DFE_DRP_EN
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[44] bit 12 GTX[0]: A_DFECLKDLYADJ bit 3	GTX[0]: DRP[44] bit 13 GTX[0]: A_DFECLKDLYADJ bit 4
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[44] bit 10 GTX[0]: A_DFECLKDLYADJ bit 1	GTX[0]: DRP[44] bit 11 GTX[0]: A_DFECLKDLYADJ bit 2
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[44] bit 8 GTX[0]: A_DFETAP4 bit 3	GTX[0]: DRP[44] bit 9 GTX[0]: A_DFECLKDLYADJ bit 0
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[44] bit 6 GTX[0]: A_DFETAP4 bit 1	GTX[0]: DRP[44] bit 7 GTX[0]: A_DFETAP4 bit 2
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[44] bit 4 GTX[0]: A_DFETAP2 bit 4	GTX[0]: DRP[44] bit 5 GTX[0]: A_DFETAP4 bit 0
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[44] bit 2 GTX[0]: A_DFETAP2 bit 2	GTX[0]: DRP[44] bit 3 GTX[0]: A_DFETAP2 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[44] bit 0 GTX[0]: A_DFETAP2 bit 0	GTX[0]: DRP[44] bit 1 GTX[0]: A_DFETAP2 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[43] bit 14 GTX[0]: A_DFEDLYOVRD bit 0	GTX[0]: DRP[43] bit 15 GTX[0]: A_DFETAPOVRD bit 0
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[43] bit 12	GTX[0]: DRP[43] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[43] bit 10 GTX[0]: RX_EN_IDLE_RESET_FR	GTX[0]: DRP[43] bit 11 GTX[0]: RX_EN_IDLE_HOLD_DFE
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[43] bit 8 GTX[0]: A_DFETAP3 bit 3	GTX[0]: DRP[43] bit 9 GTX[0]: RX_EN_IDLE_HOLD_CDR
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[43] bit 6 GTX[0]: A_DFETAP3 bit 1	GTX[0]: DRP[43] bit 7 GTX[0]: A_DFETAP3 bit 2
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[43] bit 4 GTX[0]: A_DFETAP1 bit 4	GTX[0]: DRP[43] bit 5 GTX[0]: A_DFETAP3 bit 0
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[43] bit 2 GTX[0]: A_DFETAP1 bit 2	GTX[0]: DRP[43] bit 3 GTX[0]: A_DFETAP1 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[43] bit 0 GTX[0]: A_DFETAP1 bit 0	GTX[0]: DRP[43] bit 1 GTX[0]: A_DFETAP1 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[42] bit 14 GTX[0]: A_PRBSCNTRESET bit 0	GTX[0]: DRP[42] bit 15 GTX[0]: PRBS_DRP_EN
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[42] bit 12 GTX[0]: A_TXENPRBSTST bit 1	GTX[0]: DRP[42] bit 13 GTX[0]: A_TXENPRBSTST bit 2
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[42] bit 10 GTX[0]: A_TXPRBSFORCEERR bit 0	GTX[0]: DRP[42] bit 11 GTX[0]: A_TXENPRBSTST bit 0
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[42] bit 8 GTX[0]: RXPRBSERR_LOOPBACK bit 0	GTX[0]: DRP[42] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[42] bit 6 GTX[0]: A_RXENPRBSTST bit 1	GTX[0]: DRP[42] bit 7 GTX[0]: A_RXENPRBSTST bit 2
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[42] bit 4	GTX[0]: DRP[42] bit 5 GTX[0]: A_RXENPRBSTST bit 0
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[42] bit 2 GTX[0]: A_LOOPBACK bit 1	GTX[0]: DRP[42] bit 3 GTX[0]: A_LOOPBACK bit 2
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[42] bit 0 GTX[0]: LOOPBACK_DRP_EN	GTX[0]: DRP[42] bit 1 GTX[0]: A_LOOPBACK bit 0
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[41] bit 14 GTX[0]: A_RXENSAMPLEALIGN bit 0	GTX[0]: DRP[41] bit 15 GTX[0]: PHASEALIGN_DRP_EN
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[41] bit 12 GTX[0]: A_TXPMASETPHASE bit 0	GTX[0]: DRP[41] bit 13 GTX[0]: A_TXENPMAPHASEALIGN bit 0
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[41] bit 10 GTX[0]: SAS_MIN_COMSAS bit 4	GTX[0]: DRP[41] bit 11 GTX[0]: SAS_MIN_COMSAS bit 5
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[41] bit 8 GTX[0]: SAS_MIN_COMSAS bit 2	GTX[0]: DRP[41] bit 9 GTX[0]: SAS_MIN_COMSAS bit 3
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[41] bit 6 GTX[0]: SAS_MIN_COMSAS bit 0	GTX[0]: DRP[41] bit 7 GTX[0]: SAS_MIN_COMSAS bit 1
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[41] bit 4 GTX[0]: SAS_MAX_COMSAS bit 4	GTX[0]: DRP[41] bit 5 GTX[0]: SAS_MAX_COMSAS bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[41] bit 2 GTX[0]: SAS_MAX_COMSAS bit 2	GTX[0]: DRP[41] bit 3 GTX[0]: SAS_MAX_COMSAS bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[41] bit 0 GTX[0]: SAS_MAX_COMSAS bit 0	GTX[0]: DRP[41] bit 1 GTX[0]: SAS_MAX_COMSAS bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[40] bit 14 GTX[0]: SATA_BURST_VAL bit 2	GTX[0]: DRP[40] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[40] bit 12 GTX[0]: SATA_BURST_VAL bit 0	GTX[0]: DRP[40] bit 13 GTX[0]: SATA_BURST_VAL bit 1
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[40] bit 10 GTX[0]: SATA_MIN_BURST bit 4	GTX[0]: DRP[40] bit 11 GTX[0]: SATA_MIN_BURST bit 5
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[40] bit 8 GTX[0]: SATA_MIN_BURST bit 2	GTX[0]: DRP[40] bit 9 GTX[0]: SATA_MIN_BURST bit 3
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[40] bit 6 GTX[0]: SATA_MIN_BURST bit 0	GTX[0]: DRP[40] bit 7 GTX[0]: SATA_MIN_BURST bit 1
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[40] bit 4 GTX[0]: SATA_MAX_BURST bit 4	GTX[0]: DRP[40] bit 5 GTX[0]: SATA_MAX_BURST bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[40] bit 2 GTX[0]: SATA_MAX_BURST bit 2	GTX[0]: DRP[40] bit 3 GTX[0]: SATA_MAX_BURST bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[40] bit 0 GTX[0]: SATA_MAX_BURST bit 0	GTX[0]: DRP[40] bit 1 GTX[0]: SATA_MAX_BURST bit 1

virtex6 GTX rect MAIN[6]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[55] bit 14 GTX[0]: PMA_TX_CFG bit 14	GTX[0]: DRP[55] bit 15 GTX[0]: PMA_TX_CFG bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[55] bit 12 GTX[0]: PMA_TX_CFG bit 12	GTX[0]: DRP[55] bit 13 GTX[0]: PMA_TX_CFG bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[55] bit 10 GTX[0]: PMA_TX_CFG bit 10	GTX[0]: DRP[55] bit 11 GTX[0]: PMA_TX_CFG bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[55] bit 8 GTX[0]: PMA_TX_CFG bit 8	GTX[0]: DRP[55] bit 9 GTX[0]: PMA_TX_CFG bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[55] bit 6 GTX[0]: PMA_TX_CFG bit 6	GTX[0]: DRP[55] bit 7 GTX[0]: PMA_TX_CFG bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[55] bit 4 GTX[0]: PMA_TX_CFG bit 4	GTX[0]: DRP[55] bit 5 GTX[0]: PMA_TX_CFG bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[55] bit 2 GTX[0]: PMA_TX_CFG bit 2	GTX[0]: DRP[55] bit 3 GTX[0]: PMA_TX_CFG bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[55] bit 0 GTX[0]: PMA_TX_CFG bit 0	GTX[0]: DRP[55] bit 1 GTX[0]: PMA_TX_CFG bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[54] bit 14 GTX[0]: PMA_CFG bit 74	GTX[0]: DRP[54] bit 15 GTX[0]: PMA_CFG bit 75
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[54] bit 12 GTX[0]: PMA_CFG bit 72	GTX[0]: DRP[54] bit 13 GTX[0]: PMA_CFG bit 73
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[54] bit 10 GTX[0]: PMA_CFG bit 70	GTX[0]: DRP[54] bit 11 GTX[0]: PMA_CFG bit 71
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[54] bit 8 GTX[0]: PMA_CFG bit 68	GTX[0]: DRP[54] bit 9 GTX[0]: PMA_CFG bit 69
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[54] bit 6 GTX[0]: PMA_CFG bit 66	GTX[0]: DRP[54] bit 7 GTX[0]: PMA_CFG bit 67
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[54] bit 4 GTX[0]: PMA_CFG bit 64	GTX[0]: DRP[54] bit 5 GTX[0]: PMA_CFG bit 65
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[54] bit 2 GTX[0]: PMA_TX_CFG bit 18	GTX[0]: DRP[54] bit 3 GTX[0]: PMA_TX_CFG bit 19
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[54] bit 0 GTX[0]: PMA_TX_CFG bit 16	GTX[0]: DRP[54] bit 1 GTX[0]: PMA_TX_CFG bit 17
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[53] bit 14 GTX[0]: PMA_CFG bit 62	GTX[0]: DRP[53] bit 15 GTX[0]: PMA_CFG bit 63
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[53] bit 12 GTX[0]: PMA_CFG bit 60	GTX[0]: DRP[53] bit 13 GTX[0]: PMA_CFG bit 61
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[53] bit 10 GTX[0]: PMA_CFG bit 58	GTX[0]: DRP[53] bit 11 GTX[0]: PMA_CFG bit 59
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[53] bit 8 GTX[0]: PMA_CFG bit 56	GTX[0]: DRP[53] bit 9 GTX[0]: PMA_CFG bit 57
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[53] bit 6 GTX[0]: PMA_CFG bit 54	GTX[0]: DRP[53] bit 7 GTX[0]: PMA_CFG bit 55
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[53] bit 4 GTX[0]: PMA_CFG bit 52	GTX[0]: DRP[53] bit 5 GTX[0]: PMA_CFG bit 53
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[53] bit 2 GTX[0]: PMA_CFG bit 50	GTX[0]: DRP[53] bit 3 GTX[0]: PMA_CFG bit 51
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[53] bit 0 GTX[0]: PMA_CFG bit 48	GTX[0]: DRP[53] bit 1 GTX[0]: PMA_CFG bit 49
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[52] bit 14 GTX[0]: PMA_CFG bit 46	GTX[0]: DRP[52] bit 15 GTX[0]: PMA_CFG bit 47
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[52] bit 12 GTX[0]: PMA_CFG bit 44	GTX[0]: DRP[52] bit 13 GTX[0]: PMA_CFG bit 45
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[52] bit 10 GTX[0]: PMA_CFG bit 42	GTX[0]: DRP[52] bit 11 GTX[0]: PMA_CFG bit 43
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[52] bit 8 GTX[0]: PMA_CFG bit 40	GTX[0]: DRP[52] bit 9 GTX[0]: PMA_CFG bit 41
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[52] bit 6 GTX[0]: PMA_CFG bit 38	GTX[0]: DRP[52] bit 7 GTX[0]: PMA_CFG bit 39
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[52] bit 4 GTX[0]: PMA_CFG bit 36	GTX[0]: DRP[52] bit 5 GTX[0]: PMA_CFG bit 37
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[52] bit 2 GTX[0]: PMA_CFG bit 34	GTX[0]: DRP[52] bit 3 GTX[0]: PMA_CFG bit 35
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[52] bit 0 GTX[0]: PMA_CFG bit 32	GTX[0]: DRP[52] bit 1 GTX[0]: PMA_CFG bit 33
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[51] bit 14 GTX[0]: PMA_CFG bit 30	GTX[0]: DRP[51] bit 15 GTX[0]: PMA_CFG bit 31
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[51] bit 12 GTX[0]: PMA_CFG bit 28	GTX[0]: DRP[51] bit 13 GTX[0]: PMA_CFG bit 29
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[51] bit 10 GTX[0]: PMA_CFG bit 26	GTX[0]: DRP[51] bit 11 GTX[0]: PMA_CFG bit 27
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[51] bit 8 GTX[0]: PMA_CFG bit 24	GTX[0]: DRP[51] bit 9 GTX[0]: PMA_CFG bit 25
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[51] bit 6 GTX[0]: PMA_CFG bit 22	GTX[0]: DRP[51] bit 7 GTX[0]: PMA_CFG bit 23
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[51] bit 4 GTX[0]: PMA_CFG bit 20	GTX[0]: DRP[51] bit 5 GTX[0]: PMA_CFG bit 21
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[51] bit 2 GTX[0]: PMA_CFG bit 18	GTX[0]: DRP[51] bit 3 GTX[0]: PMA_CFG bit 19
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[51] bit 0 GTX[0]: PMA_CFG bit 16	GTX[0]: DRP[51] bit 1 GTX[0]: PMA_CFG bit 17
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[50] bit 14 GTX[0]: PMA_CFG bit 14	GTX[0]: DRP[50] bit 15 GTX[0]: PMA_CFG bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[50] bit 12 GTX[0]: PMA_CFG bit 12	GTX[0]: DRP[50] bit 13 GTX[0]: PMA_CFG bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[50] bit 10 GTX[0]: PMA_CFG bit 10	GTX[0]: DRP[50] bit 11 GTX[0]: PMA_CFG bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[50] bit 8 GTX[0]: PMA_CFG bit 8	GTX[0]: DRP[50] bit 9 GTX[0]: PMA_CFG bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[50] bit 6 GTX[0]: PMA_CFG bit 6	GTX[0]: DRP[50] bit 7 GTX[0]: PMA_CFG bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[50] bit 4 GTX[0]: PMA_CFG bit 4	GTX[0]: DRP[50] bit 5 GTX[0]: PMA_CFG bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[50] bit 2 GTX[0]: PMA_CFG bit 2	GTX[0]: DRP[50] bit 3 GTX[0]: PMA_CFG bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[50] bit 0 GTX[0]: PMA_CFG bit 0	GTX[0]: DRP[50] bit 1 GTX[0]: PMA_CFG bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[49] bit 14 GTX[0]: TX_DATA_WIDTH bit 2	GTX[0]: DRP[49] bit 15 GTX[0]: GEN_TXUSRCLK
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[49] bit 12 GTX[0]: TX_DATA_WIDTH bit 0	GTX[0]: DRP[49] bit 13 GTX[0]: TX_DATA_WIDTH bit 1
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[49] bit 10 GTX[0]: PCOMMA_DETECT	GTX[0]: DRP[49] bit 11 GTX[0]: TX_BUFFER_USE
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[49] bit 8 GTX[0]: PCOMMA_10B_VALUE bit 8	GTX[0]: DRP[49] bit 9 GTX[0]: PCOMMA_10B_VALUE bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[49] bit 6 GTX[0]: PCOMMA_10B_VALUE bit 6	GTX[0]: DRP[49] bit 7 GTX[0]: PCOMMA_10B_VALUE bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[49] bit 4 GTX[0]: PCOMMA_10B_VALUE bit 4	GTX[0]: DRP[49] bit 5 GTX[0]: PCOMMA_10B_VALUE bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[49] bit 2 GTX[0]: PCOMMA_10B_VALUE bit 2	GTX[0]: DRP[49] bit 3 GTX[0]: PCOMMA_10B_VALUE bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[49] bit 0 GTX[0]: PCOMMA_10B_VALUE bit 0	GTX[0]: DRP[49] bit 1 GTX[0]: PCOMMA_10B_VALUE bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: !invert TXUSRCLK GTX[0]: DRP[48] bit 14	GTX[0]: !invert TXUSRCLK2 GTX[0]: DRP[48] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[48] bit 12 GTX[0]: TX_IDLE_DEASSERT_DELAY bit 1	GTX[0]: DRP[48] bit 13 GTX[0]: TX_IDLE_DEASSERT_DELAY bit 2
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[48] bit 10 GTX[0]: MCOMMA_DETECT	GTX[0]: DRP[48] bit 11 GTX[0]: TX_IDLE_DEASSERT_DELAY bit 0
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[48] bit 8 GTX[0]: MCOMMA_10B_VALUE bit 8	GTX[0]: DRP[48] bit 9 GTX[0]: MCOMMA_10B_VALUE bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[48] bit 6 GTX[0]: MCOMMA_10B_VALUE bit 6	GTX[0]: DRP[48] bit 7 GTX[0]: MCOMMA_10B_VALUE bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[48] bit 4 GTX[0]: MCOMMA_10B_VALUE bit 4	GTX[0]: DRP[48] bit 5 GTX[0]: MCOMMA_10B_VALUE bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[48] bit 2 GTX[0]: MCOMMA_10B_VALUE bit 2	GTX[0]: DRP[48] bit 3 GTX[0]: MCOMMA_10B_VALUE bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[48] bit 0 GTX[0]: MCOMMA_10B_VALUE bit 0	GTX[0]: DRP[48] bit 1 GTX[0]: MCOMMA_10B_VALUE bit 1

virtex6 GTX rect MAIN[7]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[63] bit 14	GTX[0]: DRP[63] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[63] bit 12	GTX[0]: DRP[63] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[63] bit 10	GTX[0]: DRP[63] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[63] bit 8	GTX[0]: DRP[63] bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[63] bit 6 GTX[0]: TRANS_TIME_RATE bit 6	GTX[0]: DRP[63] bit 7 GTX[0]: TRANS_TIME_RATE bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[63] bit 4 GTX[0]: TRANS_TIME_RATE bit 4	GTX[0]: DRP[63] bit 5 GTX[0]: TRANS_TIME_RATE bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[63] bit 2 GTX[0]: TRANS_TIME_RATE bit 2	GTX[0]: DRP[63] bit 3 GTX[0]: TRANS_TIME_RATE bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[63] bit 0 GTX[0]: TRANS_TIME_RATE bit 0	GTX[0]: DRP[63] bit 1 GTX[0]: TRANS_TIME_RATE bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[62] bit 14 GTX[0]: A_TXMARGIN bit 1	GTX[0]: DRP[62] bit 15 GTX[0]: A_TXMARGIN bit 2
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[62] bit 12	GTX[0]: DRP[62] bit 13 GTX[0]: A_TXMARGIN bit 0
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[62] bit 10	GTX[0]: DRP[62] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[62] bit 8 GTX[0]: TX_DEEMPH_1 bit 3	GTX[0]: DRP[62] bit 9 GTX[0]: TX_DEEMPH_1 bit 4
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[62] bit 6 GTX[0]: TX_DEEMPH_1 bit 1	GTX[0]: DRP[62] bit 7 GTX[0]: TX_DEEMPH_1 bit 2
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[62] bit 4 GTX[0]: TX_DEEMPH_0 bit 4	GTX[0]: DRP[62] bit 5 GTX[0]: TX_DEEMPH_1 bit 0
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[62] bit 2 GTX[0]: TX_DEEMPH_0 bit 2	GTX[0]: DRP[62] bit 3 GTX[0]: TX_DEEMPH_0 bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[62] bit 0 GTX[0]: TX_DEEMPH_0 bit 0	GTX[0]: DRP[62] bit 1 GTX[0]: TX_DEEMPH_0 bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[61] bit 14 GTX[0]: A_TXPOSTEMPHASIS bit 3	GTX[0]: DRP[61] bit 15 GTX[0]: A_TXPOSTEMPHASIS bit 4
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[61] bit 12 GTX[0]: A_TXPOSTEMPHASIS bit 1	GTX[0]: DRP[61] bit 13 GTX[0]: A_TXPOSTEMPHASIS bit 2
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[61] bit 10 GTX[0]: A_TXPREEMPHASIS bit 3	GTX[0]: DRP[61] bit 11 GTX[0]: A_TXPOSTEMPHASIS bit 0
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[61] bit 8 GTX[0]: A_TXPREEMPHASIS bit 1	GTX[0]: DRP[61] bit 9 GTX[0]: A_TXPREEMPHASIS bit 2
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[61] bit 6 GTX[0]: A_TXBUFDIFFCTRL bit 2	GTX[0]: DRP[61] bit 7 GTX[0]: A_TXPREEMPHASIS bit 0
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[61] bit 4 GTX[0]: A_TXBUFDIFFCTRL bit 0	GTX[0]: DRP[61] bit 5 GTX[0]: A_TXBUFDIFFCTRL bit 1
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[61] bit 2 GTX[0]: A_TXDIFFCTRL bit 2	GTX[0]: DRP[61] bit 3 GTX[0]: A_TXDIFFCTRL bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[61] bit 0 GTX[0]: A_TXDIFFCTRL bit 0	GTX[0]: DRP[61] bit 1 GTX[0]: A_TXDIFFCTRL bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[60] bit 14 GTX[0]: TXDRIVE_DRP_EN	GTX[0]: DRP[60] bit 15 GTX[0]: TX_DRIVE_MODE bit 0
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[60] bit 12 GTX[0]: TX_MARGIN_FULL_4 bit 5	GTX[0]: DRP[60] bit 13 GTX[0]: TX_MARGIN_FULL_4 bit 6
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[60] bit 10 GTX[0]: TX_MARGIN_FULL_4 bit 3	GTX[0]: DRP[60] bit 11 GTX[0]: TX_MARGIN_FULL_4 bit 4
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[60] bit 8 GTX[0]: TX_MARGIN_FULL_4 bit 1	GTX[0]: DRP[60] bit 9 GTX[0]: TX_MARGIN_FULL_4 bit 2
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[60] bit 6 GTX[0]: TX_MARGIN_LOW_4 bit 6	GTX[0]: DRP[60] bit 7 GTX[0]: TX_MARGIN_FULL_4 bit 0
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[60] bit 4 GTX[0]: TX_MARGIN_LOW_4 bit 4	GTX[0]: DRP[60] bit 5 GTX[0]: TX_MARGIN_LOW_4 bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[60] bit 2 GTX[0]: TX_MARGIN_LOW_4 bit 2	GTX[0]: DRP[60] bit 3 GTX[0]: TX_MARGIN_LOW_4 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[60] bit 0 GTX[0]: TX_MARGIN_LOW_4 bit 0	GTX[0]: DRP[60] bit 1 GTX[0]: TX_MARGIN_LOW_4 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[59] bit 14 GTX[0]: A_TXSWING bit 0	GTX[0]: DRP[59] bit 15 GTX[0]: A_TXDEEMPH bit 0
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[59] bit 12 GTX[0]: TX_MARGIN_FULL_3 bit 5	GTX[0]: DRP[59] bit 13 GTX[0]: TX_MARGIN_FULL_3 bit 6
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[59] bit 10 GTX[0]: TX_MARGIN_FULL_3 bit 3	GTX[0]: DRP[59] bit 11 GTX[0]: TX_MARGIN_FULL_3 bit 4
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[59] bit 8 GTX[0]: TX_MARGIN_FULL_3 bit 1	GTX[0]: DRP[59] bit 9 GTX[0]: TX_MARGIN_FULL_3 bit 2
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[59] bit 6 GTX[0]: TX_MARGIN_LOW_3 bit 6	GTX[0]: DRP[59] bit 7 GTX[0]: TX_MARGIN_FULL_3 bit 0
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[59] bit 4 GTX[0]: TX_MARGIN_LOW_3 bit 4	GTX[0]: DRP[59] bit 5 GTX[0]: TX_MARGIN_LOW_3 bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[59] bit 2 GTX[0]: TX_MARGIN_LOW_3 bit 2	GTX[0]: DRP[59] bit 3 GTX[0]: TX_MARGIN_LOW_3 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[59] bit 0 GTX[0]: TX_MARGIN_LOW_3 bit 0	GTX[0]: DRP[59] bit 1 GTX[0]: TX_MARGIN_LOW_3 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[58] bit 14 GTX[0]: ! TXDRIVE_LOOPBACK_HIZ	GTX[0]: DRP[58] bit 15 GTX[0]: ! TXDRIVE_LOOPBACK_PD
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[58] bit 12 GTX[0]: TX_MARGIN_FULL_2 bit 5	GTX[0]: DRP[58] bit 13 GTX[0]: TX_MARGIN_FULL_2 bit 6
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[58] bit 10 GTX[0]: TX_MARGIN_FULL_2 bit 3	GTX[0]: DRP[58] bit 11 GTX[0]: TX_MARGIN_FULL_2 bit 4
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[58] bit 8 GTX[0]: TX_MARGIN_FULL_2 bit 1	GTX[0]: DRP[58] bit 9 GTX[0]: TX_MARGIN_FULL_2 bit 2
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[58] bit 6 GTX[0]: TX_MARGIN_LOW_2 bit 6	GTX[0]: DRP[58] bit 7 GTX[0]: TX_MARGIN_FULL_2 bit 0
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[58] bit 4 GTX[0]: TX_MARGIN_LOW_2 bit 4	GTX[0]: DRP[58] bit 5 GTX[0]: TX_MARGIN_LOW_2 bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[58] bit 2 GTX[0]: TX_MARGIN_LOW_2 bit 2	GTX[0]: DRP[58] bit 3 GTX[0]: TX_MARGIN_LOW_2 bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[58] bit 0 GTX[0]: TX_MARGIN_LOW_2 bit 0	GTX[0]: DRP[58] bit 1 GTX[0]: TX_MARGIN_LOW_2 bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[57] bit 14 GTX[0]: TX_TDCC_CFG bit 0	GTX[0]: DRP[57] bit 15 GTX[0]: TX_TDCC_CFG bit 1
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[57] bit 12 GTX[0]: TX_MARGIN_FULL_1 bit 5	GTX[0]: DRP[57] bit 13 GTX[0]: TX_MARGIN_FULL_1 bit 6
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[57] bit 10 GTX[0]: TX_MARGIN_FULL_1 bit 3	GTX[0]: DRP[57] bit 11 GTX[0]: TX_MARGIN_FULL_1 bit 4
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[57] bit 8 GTX[0]: TX_MARGIN_FULL_1 bit 1	GTX[0]: DRP[57] bit 9 GTX[0]: TX_MARGIN_FULL_1 bit 2
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[57] bit 6 GTX[0]: TX_MARGIN_LOW_1 bit 6	GTX[0]: DRP[57] bit 7 GTX[0]: TX_MARGIN_FULL_1 bit 0
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[57] bit 4 GTX[0]: TX_MARGIN_LOW_1 bit 4	GTX[0]: DRP[57] bit 5 GTX[0]: TX_MARGIN_LOW_1 bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[57] bit 2 GTX[0]: TX_MARGIN_LOW_1 bit 2	GTX[0]: DRP[57] bit 3 GTX[0]: TX_MARGIN_LOW_1 bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[57] bit 0 GTX[0]: TX_MARGIN_LOW_1 bit 0	GTX[0]: DRP[57] bit 1 GTX[0]: TX_MARGIN_LOW_1 bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[56] bit 14 GTX[0]: TXOUTCLKPCS_SEL bit 0	GTX[0]: !invert DCLK GTX[0]: DRP[56] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[56] bit 12 GTX[0]: TX_MARGIN_FULL_0 bit 5	GTX[0]: DRP[56] bit 13 GTX[0]: TX_MARGIN_FULL_0 bit 6
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[56] bit 10 GTX[0]: TX_MARGIN_FULL_0 bit 3	GTX[0]: DRP[56] bit 11 GTX[0]: TX_MARGIN_FULL_0 bit 4
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[56] bit 8 GTX[0]: TX_MARGIN_FULL_0 bit 1	GTX[0]: DRP[56] bit 9 GTX[0]: TX_MARGIN_FULL_0 bit 2
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[56] bit 6 GTX[0]: TX_MARGIN_LOW_0 bit 6	GTX[0]: DRP[56] bit 7 GTX[0]: TX_MARGIN_FULL_0 bit 0
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[56] bit 4 GTX[0]: TX_MARGIN_LOW_0 bit 4	GTX[0]: DRP[56] bit 5 GTX[0]: TX_MARGIN_LOW_0 bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[56] bit 2 GTX[0]: TX_MARGIN_LOW_0 bit 2	GTX[0]: DRP[56] bit 3 GTX[0]: TX_MARGIN_LOW_0 bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[56] bit 0 GTX[0]: TX_MARGIN_LOW_0 bit 0	GTX[0]: DRP[56] bit 1 GTX[0]: TX_MARGIN_LOW_0 bit 1

virtex6 GTX rect MAIN[8]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[71] bit 14	GTX[0]: DRP[71] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[71] bit 12	GTX[0]: DRP[71] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[71] bit 10	GTX[0]: DRP[71] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[71] bit 8 GTX[0]: TXOUTCLK_DLY bit 8	GTX[0]: DRP[71] bit 9 GTX[0]: TXOUTCLK_DLY bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[71] bit 6 GTX[0]: TXOUTCLK_DLY bit 6	GTX[0]: DRP[71] bit 7 GTX[0]: TXOUTCLK_DLY bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[71] bit 4 GTX[0]: TXOUTCLK_DLY bit 4	GTX[0]: DRP[71] bit 5 GTX[0]: TXOUTCLK_DLY bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[71] bit 2 GTX[0]: TXOUTCLK_DLY bit 2	GTX[0]: DRP[71] bit 3 GTX[0]: TXOUTCLK_DLY bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[71] bit 0 GTX[0]: TXOUTCLK_DLY bit 0	GTX[0]: DRP[71] bit 1 GTX[0]: TXOUTCLK_DLY bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[70] bit 14	GTX[0]: DRP[70] bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[70] bit 12	GTX[0]: DRP[70] bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[70] bit 10	GTX[0]: DRP[70] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[70] bit 8 GTX[0]: RXRECCLK_DLY bit 8	GTX[0]: DRP[70] bit 9 GTX[0]: RXRECCLK_DLY bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[70] bit 6 GTX[0]: RXRECCLK_DLY bit 6	GTX[0]: DRP[70] bit 7 GTX[0]: RXRECCLK_DLY bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[70] bit 4 GTX[0]: RXRECCLK_DLY bit 4	GTX[0]: DRP[70] bit 5 GTX[0]: RXRECCLK_DLY bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[70] bit 2 GTX[0]: RXRECCLK_DLY bit 2	GTX[0]: DRP[70] bit 3 GTX[0]: RXRECCLK_DLY bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[70] bit 0 GTX[0]: RXRECCLK_DLY bit 0	GTX[0]: DRP[70] bit 1 GTX[0]: RXRECCLK_DLY bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[69] bit 14	GTX[0]: DRP[69] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[69] bit 12	GTX[0]: DRP[69] bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[69] bit 10 GTX[0]: TX_USRCLK_CFG bit 4	GTX[0]: DRP[69] bit 11 GTX[0]: TX_USRCLK_CFG bit 5
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[69] bit 8 GTX[0]: TX_USRCLK_CFG bit 2	GTX[0]: DRP[69] bit 9 GTX[0]: TX_USRCLK_CFG bit 3
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[69] bit 6 GTX[0]: TX_USRCLK_CFG bit 0	GTX[0]: DRP[69] bit 7 GTX[0]: TX_USRCLK_CFG bit 1
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[69] bit 4 GTX[0]: TX_BYTECLK_CFG bit 4	GTX[0]: DRP[69] bit 5 GTX[0]: TX_BYTECLK_CFG bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[69] bit 2 GTX[0]: TX_BYTECLK_CFG bit 2	GTX[0]: DRP[69] bit 3 GTX[0]: TX_BYTECLK_CFG bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[69] bit 0 GTX[0]: TX_BYTECLK_CFG bit 0	GTX[0]: DRP[69] bit 1 GTX[0]: TX_BYTECLK_CFG bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[68] bit 14	GTX[0]: DRP[68] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[68] bit 12	GTX[0]: DRP[68] bit 13
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[68] bit 10	GTX[0]: DRP[68] bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[68] bit 8 GTX[0]: POWER_SAVE bit 8	GTX[0]: DRP[68] bit 9 GTX[0]: POWER_SAVE bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[68] bit 6 GTX[0]: POWER_SAVE bit 6	GTX[0]: DRP[68] bit 7 GTX[0]: POWER_SAVE bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[68] bit 4 GTX[0]: POWER_SAVE bit 4	GTX[0]: DRP[68] bit 5 GTX[0]: POWER_SAVE bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[68] bit 2 GTX[0]: POWER_SAVE bit 2	GTX[0]: DRP[68] bit 3 GTX[0]: POWER_SAVE bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[68] bit 0 GTX[0]: POWER_SAVE bit 0	GTX[0]: DRP[68] bit 1 GTX[0]: POWER_SAVE bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: !invert GREFCLKTX GTX[0]: DRP[67] bit 14	GTX[0]: !invert GREFCLKRX GTX[0]: DRP[67] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[67] bit 12	GTX[0]: !invert SCANCLK GTX[0]: DRP[67] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: !invert TSTCLK[0] GTX[0]: DRP[67] bit 10	GTX[0]: !invert TSTCLK[1] GTX[0]: DRP[67] bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[67] bit 8	GTX[0]: DRP[67] bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[67] bit 6	GTX[0]: DRP[67] bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[67] bit 4 GTX[0]: RXRECCLK_CTRL bit 1	GTX[0]: DRP[67] bit 5 GTX[0]: RXRECCLK_CTRL bit 2
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[67] bit 2 GTX[0]: TXOUTCLK_CTRL bit 2	GTX[0]: DRP[67] bit 3 GTX[0]: RXRECCLK_CTRL bit 0
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[67] bit 0 GTX[0]: TXOUTCLK_CTRL bit 0	GTX[0]: DRP[67] bit 1 GTX[0]: TXOUTCLK_CTRL bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[66] bit 14 GTX[0]: TST_ATTR bit 14	GTX[0]: DRP[66] bit 15 GTX[0]: TST_ATTR bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[66] bit 12 GTX[0]: TST_ATTR bit 12	GTX[0]: DRP[66] bit 13 GTX[0]: TST_ATTR bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[66] bit 10 GTX[0]: TST_ATTR bit 10	GTX[0]: DRP[66] bit 11 GTX[0]: TST_ATTR bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[66] bit 8 GTX[0]: TST_ATTR bit 8	GTX[0]: DRP[66] bit 9 GTX[0]: TST_ATTR bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[66] bit 6 GTX[0]: TST_ATTR bit 6	GTX[0]: DRP[66] bit 7 GTX[0]: TST_ATTR bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[66] bit 4 GTX[0]: TST_ATTR bit 4	GTX[0]: DRP[66] bit 5 GTX[0]: TST_ATTR bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[66] bit 2 GTX[0]: TST_ATTR bit 2	GTX[0]: DRP[66] bit 3 GTX[0]: TST_ATTR bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[66] bit 0 GTX[0]: TST_ATTR bit 0	GTX[0]: DRP[66] bit 1 GTX[0]: TST_ATTR bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[65] bit 14 GTX[0]: TST_ATTR bit 30	GTX[0]: DRP[65] bit 15 GTX[0]: TST_ATTR bit 31
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[65] bit 12 GTX[0]: TST_ATTR bit 28	GTX[0]: DRP[65] bit 13 GTX[0]: TST_ATTR bit 29
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[65] bit 10 GTX[0]: TST_ATTR bit 26	GTX[0]: DRP[65] bit 11 GTX[0]: TST_ATTR bit 27
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[65] bit 8 GTX[0]: TST_ATTR bit 24	GTX[0]: DRP[65] bit 9 GTX[0]: TST_ATTR bit 25
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[65] bit 6 GTX[0]: TST_ATTR bit 22	GTX[0]: DRP[65] bit 7 GTX[0]: TST_ATTR bit 23
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[65] bit 4 GTX[0]: TST_ATTR bit 20	GTX[0]: DRP[65] bit 5 GTX[0]: TST_ATTR bit 21
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[65] bit 2 GTX[0]: TST_ATTR bit 18	GTX[0]: DRP[65] bit 3 GTX[0]: TST_ATTR bit 19
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[65] bit 0 GTX[0]: TST_ATTR bit 16	GTX[0]: DRP[65] bit 1 GTX[0]: TST_ATTR bit 17
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[64] bit 14	GTX[0]: DRP[64] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[64] bit 12	GTX[0]: DRP[64] bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[64] bit 10	GTX[0]: DRP[64] bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[64] bit 8 GTX[0]: A_RXEQMIX bit 8	GTX[0]: DRP[64] bit 9 GTX[0]: A_RXEQMIX bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[64] bit 6 GTX[0]: A_RXEQMIX bit 6	GTX[0]: DRP[64] bit 7 GTX[0]: A_RXEQMIX bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[64] bit 4 GTX[0]: A_RXEQMIX bit 4	GTX[0]: DRP[64] bit 5 GTX[0]: A_RXEQMIX bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[64] bit 2 GTX[0]: A_RXEQMIX bit 2	GTX[0]: DRP[64] bit 3 GTX[0]: A_RXEQMIX bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[64] bit 0 GTX[0]: A_RXEQMIX bit 0	GTX[0]: DRP[64] bit 1 GTX[0]: A_RXEQMIX bit 1

virtex6 GTX rect MAIN[9]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[79] bit 14	GTX[0]: DRP[79] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[79] bit 12	GTX[0]: DRP[79] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[79] bit 10	GTX[0]: DRP[79] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[79] bit 8	GTX[0]: DRP[79] bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[79] bit 6	GTX[0]: DRP[79] bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[79] bit 4	GTX[0]: DRP[79] bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[79] bit 2	GTX[0]: DRP[79] bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[79] bit 0	GTX[0]: DRP[79] bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[78] bit 14	GTX[0]: DRP[78] bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[78] bit 12	GTX[0]: DRP[78] bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[78] bit 10	GTX[0]: DRP[78] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[78] bit 8	GTX[0]: DRP[78] bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[78] bit 6	GTX[0]: DRP[78] bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[78] bit 4	GTX[0]: DRP[78] bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[78] bit 2	GTX[0]: DRP[78] bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[78] bit 0	GTX[0]: DRP[78] bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[77] bit 14 GTX[0]: RX_DLYALIGN_OVRDSETTING bit 6	GTX[0]: DRP[77] bit 15 GTX[0]: RX_DLYALIGN_OVRDSETTING bit 7
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[77] bit 12 GTX[0]: RX_DLYALIGN_OVRDSETTING bit 4	GTX[0]: DRP[77] bit 13 GTX[0]: RX_DLYALIGN_OVRDSETTING bit 5
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[77] bit 10 GTX[0]: RX_DLYALIGN_OVRDSETTING bit 2	GTX[0]: DRP[77] bit 11 GTX[0]: RX_DLYALIGN_OVRDSETTING bit 3
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[77] bit 8 GTX[0]: RX_DLYALIGN_OVRDSETTING bit 0	GTX[0]: DRP[77] bit 9 GTX[0]: RX_DLYALIGN_OVRDSETTING bit 1
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[77] bit 6 GTX[0]: RX_DLYALIGN_LPFINC bit 2	GTX[0]: DRP[77] bit 7 GTX[0]: RX_DLYALIGN_LPFINC bit 3
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[77] bit 4 GTX[0]: RX_DLYALIGN_LPFINC bit 0	GTX[0]: DRP[77] bit 5 GTX[0]: RX_DLYALIGN_LPFINC bit 1
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[77] bit 2 GTX[0]: RX_DLYALIGN_CTRINC bit 2	GTX[0]: DRP[77] bit 3 GTX[0]: RX_DLYALIGN_CTRINC bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[77] bit 0 GTX[0]: RX_DLYALIGN_CTRINC bit 0	GTX[0]: DRP[77] bit 1 GTX[0]: RX_DLYALIGN_CTRINC bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[76] bit 14 GTX[0]: TX_DLYALIGN_OVRDSETTING bit 6	GTX[0]: DRP[76] bit 15 GTX[0]: TX_DLYALIGN_OVRDSETTING bit 7
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[76] bit 12 GTX[0]: TX_DLYALIGN_OVRDSETTING bit 4	GTX[0]: DRP[76] bit 13 GTX[0]: TX_DLYALIGN_OVRDSETTING bit 5
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[76] bit 10 GTX[0]: TX_DLYALIGN_OVRDSETTING bit 2	GTX[0]: DRP[76] bit 11 GTX[0]: TX_DLYALIGN_OVRDSETTING bit 3
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[76] bit 8 GTX[0]: TX_DLYALIGN_OVRDSETTING bit 0	GTX[0]: DRP[76] bit 9 GTX[0]: TX_DLYALIGN_OVRDSETTING bit 1
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[76] bit 6 GTX[0]: TX_DLYALIGN_LPFINC bit 2	GTX[0]: DRP[76] bit 7 GTX[0]: TX_DLYALIGN_LPFINC bit 3
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[76] bit 4 GTX[0]: TX_DLYALIGN_LPFINC bit 0	GTX[0]: DRP[76] bit 5 GTX[0]: TX_DLYALIGN_LPFINC bit 1
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[76] bit 2 GTX[0]: TX_DLYALIGN_CTRINC bit 2	GTX[0]: DRP[76] bit 3 GTX[0]: TX_DLYALIGN_CTRINC bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[76] bit 0 GTX[0]: TX_DLYALIGN_CTRINC bit 0	GTX[0]: DRP[76] bit 1 GTX[0]: TX_DLYALIGN_CTRINC bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[75] bit 14 GTX[0]: RX_EN_REALIGN_RESET_BUF2	GTX[0]: DRP[75] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[75] bit 12	GTX[0]: DRP[75] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[75] bit 10 GTX[0]: RX_DLYALIGN_EDGESET bit 4	GTX[0]: DRP[75] bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[75] bit 8 GTX[0]: RX_DLYALIGN_EDGESET bit 2	GTX[0]: DRP[75] bit 9 GTX[0]: RX_DLYALIGN_EDGESET bit 3
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[75] bit 6 GTX[0]: RX_DLYALIGN_EDGESET bit 0	GTX[0]: DRP[75] bit 7 GTX[0]: RX_DLYALIGN_EDGESET bit 1
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[75] bit 4 GTX[0]: TX_DLYALIGN_MONSEL bit 1	GTX[0]: DRP[75] bit 5 GTX[0]: TX_DLYALIGN_MONSEL bit 2
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[75] bit 2 GTX[0]: RX_DLYALIGN_MONSEL bit 2	GTX[0]: DRP[75] bit 3 GTX[0]: TX_DLYALIGN_MONSEL bit 0
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[75] bit 0 GTX[0]: RX_DLYALIGN_MONSEL bit 0	GTX[0]: DRP[75] bit 1 GTX[0]: RX_DLYALIGN_MONSEL bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[74] bit 14	GTX[0]: DRP[74] bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[74] bit 12	GTX[0]: DRP[74] bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[74] bit 10	GTX[0]: DRP[74] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[74] bit 8	GTX[0]: DRP[74] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[74] bit 6	GTX[0]: DRP[74] bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[74] bit 4	GTX[0]: DRP[74] bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[74] bit 2	GTX[0]: DRP[74] bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[74] bit 0	GTX[0]: DRP[74] bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[73] bit 14	GTX[0]: DRP[73] bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[73] bit 12	GTX[0]: DRP[73] bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[73] bit 10	GTX[0]: DRP[73] bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[73] bit 8	GTX[0]: DRP[73] bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[73] bit 6	GTX[0]: DRP[73] bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[73] bit 4	GTX[0]: DRP[73] bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[73] bit 2	GTX[0]: DRP[73] bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[73] bit 0	GTX[0]: DRP[73] bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[72] bit 14	GTX[0]: DRP[72] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[72] bit 12	GTX[0]: DRP[72] bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[72] bit 10	GTX[0]: DRP[72] bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[72] bit 8	GTX[0]: DRP[72] bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[72] bit 6	GTX[0]: DRP[72] bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[72] bit 4	GTX[0]: DRP[72] bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[72] bit 2	GTX[0]: DRP[72] bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[0]: DRP[72] bit 0	GTX[0]: DRP[72] bit 1

virtex6 GTX rect MAIN[10]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[7] bit 14 GTX[1]: RX_IDLE_LO_CNT bit 2	GTX[1]: DRP[7] bit 15 GTX[1]: RX_IDLE_LO_CNT bit 3
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[7] bit 12 GTX[1]: RX_IDLE_LO_CNT bit 0	GTX[1]: DRP[7] bit 13 GTX[1]: RX_IDLE_LO_CNT bit 1
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[7] bit 10 GTX[1]: CHAN_BOND_SEQ_LEN bit 0	GTX[1]: DRP[7] bit 11 GTX[1]: CHAN_BOND_SEQ_LEN bit 1
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[7] bit 8 GTX[1]: CHAN_BOND_SEQ_1_4 bit 8	GTX[1]: DRP[7] bit 9 GTX[1]: CHAN_BOND_SEQ_1_4 bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[7] bit 6 GTX[1]: CHAN_BOND_SEQ_1_4 bit 6	GTX[1]: DRP[7] bit 7 GTX[1]: CHAN_BOND_SEQ_1_4 bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[7] bit 4 GTX[1]: CHAN_BOND_SEQ_1_4 bit 4	GTX[1]: DRP[7] bit 5 GTX[1]: CHAN_BOND_SEQ_1_4 bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[7] bit 2 GTX[1]: CHAN_BOND_SEQ_1_4 bit 2	GTX[1]: DRP[7] bit 3 GTX[1]: CHAN_BOND_SEQ_1_4 bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[7] bit 0 GTX[1]: CHAN_BOND_SEQ_1_4 bit 0	GTX[1]: DRP[7] bit 1 GTX[1]: CHAN_BOND_SEQ_1_4 bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[6] bit 14 GTX[1]: RX_LOS_INVALID_INCR bit 1	GTX[1]: DRP[6] bit 15 GTX[1]: RX_LOS_INVALID_INCR bit 2
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[6] bit 12 GTX[1]: RX_LOS_THRESHOLD bit 2	GTX[1]: DRP[6] bit 13 GTX[1]: RX_LOS_INVALID_INCR bit 0
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[6] bit 10 GTX[1]: RX_LOS_THRESHOLD bit 0	GTX[1]: DRP[6] bit 11 GTX[1]: RX_LOS_THRESHOLD bit 1
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[6] bit 8 GTX[1]: CHAN_BOND_SEQ_1_3 bit 8	GTX[1]: DRP[6] bit 9 GTX[1]: CHAN_BOND_SEQ_1_3 bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[6] bit 6 GTX[1]: CHAN_BOND_SEQ_1_3 bit 6	GTX[1]: DRP[6] bit 7 GTX[1]: CHAN_BOND_SEQ_1_3 bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[6] bit 4 GTX[1]: CHAN_BOND_SEQ_1_3 bit 4	GTX[1]: DRP[6] bit 5 GTX[1]: CHAN_BOND_SEQ_1_3 bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[6] bit 2 GTX[1]: CHAN_BOND_SEQ_1_3 bit 2	GTX[1]: DRP[6] bit 3 GTX[1]: CHAN_BOND_SEQ_1_3 bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[6] bit 0 GTX[1]: CHAN_BOND_SEQ_1_3 bit 0	GTX[1]: DRP[6] bit 1 GTX[1]: CHAN_BOND_SEQ_1_3 bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: !invert RXUSRCLK GTX[1]: DRP[5] bit 14	GTX[1]: !invert RXUSRCLK2 GTX[1]: DRP[5] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[5] bit 12 GTX[1]: CHAN_BOND_1_MAX_SKEW bit 2	GTX[1]: DRP[5] bit 13 GTX[1]: CHAN_BOND_1_MAX_SKEW bit 3
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[5] bit 10 GTX[1]: CHAN_BOND_1_MAX_SKEW bit 0	GTX[1]: DRP[5] bit 11 GTX[1]: CHAN_BOND_1_MAX_SKEW bit 1
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[5] bit 8 GTX[1]: CHAN_BOND_SEQ_1_2 bit 8	GTX[1]: DRP[5] bit 9 GTX[1]: CHAN_BOND_SEQ_1_2 bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[5] bit 6 GTX[1]: CHAN_BOND_SEQ_1_2 bit 6	GTX[1]: DRP[5] bit 7 GTX[1]: CHAN_BOND_SEQ_1_2 bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[5] bit 4 GTX[1]: CHAN_BOND_SEQ_1_2 bit 4	GTX[1]: DRP[5] bit 5 GTX[1]: CHAN_BOND_SEQ_1_2 bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[5] bit 2 GTX[1]: CHAN_BOND_SEQ_1_2 bit 2	GTX[1]: DRP[5] bit 3 GTX[1]: CHAN_BOND_SEQ_1_2 bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[5] bit 0 GTX[1]: CHAN_BOND_SEQ_1_2 bit 0	GTX[1]: DRP[5] bit 1 GTX[1]: CHAN_BOND_SEQ_1_2 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[4] bit 14 GTX[1]: RX_BUFFER_USE	GTX[1]: DRP[4] bit 15 GTX[1]: RX_LOSS_OF_SYNC_FSM
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[4] bit 12 GTX[1]: CHAN_BOND_SEQ_1_ENABLE bit 2	GTX[1]: DRP[4] bit 13 GTX[1]: CHAN_BOND_SEQ_1_ENABLE bit 3
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[4] bit 10 GTX[1]: CHAN_BOND_SEQ_1_ENABLE bit 0	GTX[1]: DRP[4] bit 11 GTX[1]: CHAN_BOND_SEQ_1_ENABLE bit 1
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[4] bit 8 GTX[1]: CHAN_BOND_SEQ_1_1 bit 8	GTX[1]: DRP[4] bit 9 GTX[1]: CHAN_BOND_SEQ_1_1 bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[4] bit 6 GTX[1]: CHAN_BOND_SEQ_1_1 bit 6	GTX[1]: DRP[4] bit 7 GTX[1]: CHAN_BOND_SEQ_1_1 bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[4] bit 4 GTX[1]: CHAN_BOND_SEQ_1_1 bit 4	GTX[1]: DRP[4] bit 5 GTX[1]: CHAN_BOND_SEQ_1_1 bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[4] bit 2 GTX[1]: CHAN_BOND_SEQ_1_1 bit 2	GTX[1]: DRP[4] bit 3 GTX[1]: CHAN_BOND_SEQ_1_1 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[4] bit 0 GTX[1]: CHAN_BOND_SEQ_1_1 bit 0	GTX[1]: DRP[4] bit 1 GTX[1]: CHAN_BOND_SEQ_1_1 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[3] bit 14 GTX[1]: BIAS_CFG bit 14	GTX[1]: DRP[3] bit 15 GTX[1]: BIAS_CFG bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[3] bit 12 GTX[1]: BIAS_CFG bit 12	GTX[1]: DRP[3] bit 13 GTX[1]: BIAS_CFG bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[3] bit 10 GTX[1]: BIAS_CFG bit 10	GTX[1]: DRP[3] bit 11 GTX[1]: BIAS_CFG bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[3] bit 8 GTX[1]: BIAS_CFG bit 8	GTX[1]: DRP[3] bit 9 GTX[1]: BIAS_CFG bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[3] bit 6 GTX[1]: BIAS_CFG bit 6	GTX[1]: DRP[3] bit 7 GTX[1]: BIAS_CFG bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[3] bit 4 GTX[1]: BIAS_CFG bit 4	GTX[1]: DRP[3] bit 5 GTX[1]: BIAS_CFG bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[3] bit 2 GTX[1]: BIAS_CFG bit 2	GTX[1]: DRP[3] bit 3 GTX[1]: BIAS_CFG bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[3] bit 0 GTX[1]: BIAS_CFG bit 0	GTX[1]: DRP[3] bit 1 GTX[1]: BIAS_CFG bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[2] bit 14 GTX[1]: RXUSRCLK_DLY bit 14	GTX[1]: DRP[2] bit 15 GTX[1]: RXUSRCLK_DLY bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[2] bit 12 GTX[1]: RXUSRCLK_DLY bit 12	GTX[1]: DRP[2] bit 13 GTX[1]: RXUSRCLK_DLY bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[2] bit 10 GTX[1]: RXUSRCLK_DLY bit 10	GTX[1]: DRP[2] bit 11 GTX[1]: RXUSRCLK_DLY bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[2] bit 8 GTX[1]: RXUSRCLK_DLY bit 8	GTX[1]: DRP[2] bit 9 GTX[1]: RXUSRCLK_DLY bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[2] bit 6 GTX[1]: RXUSRCLK_DLY bit 6	GTX[1]: DRP[2] bit 7 GTX[1]: RXUSRCLK_DLY bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[2] bit 4 GTX[1]: RXUSRCLK_DLY bit 4	GTX[1]: DRP[2] bit 5 GTX[1]: RXUSRCLK_DLY bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[2] bit 2 GTX[1]: RXUSRCLK_DLY bit 2	GTX[1]: DRP[2] bit 3 GTX[1]: RXUSRCLK_DLY bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[2] bit 0 GTX[1]: RXUSRCLK_DLY bit 0	GTX[1]: DRP[2] bit 1 GTX[1]: RXUSRCLK_DLY bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[1] bit 14 GTX[1]: PMA_RXSYNC_CFG bit 5	GTX[1]: DRP[1] bit 15 GTX[1]: PMA_RXSYNC_CFG bit 6
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[1] bit 12 GTX[1]: PMA_RXSYNC_CFG bit 3	GTX[1]: DRP[1] bit 13 GTX[1]: PMA_RXSYNC_CFG bit 4
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[1] bit 10 GTX[1]: PMA_RXSYNC_CFG bit 1	GTX[1]: DRP[1] bit 11 GTX[1]: PMA_RXSYNC_CFG bit 2
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[1] bit 8 GTX[1]: PMA_RX_CFG bit 24	GTX[1]: DRP[1] bit 9 GTX[1]: PMA_RXSYNC_CFG bit 0
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[1] bit 6 GTX[1]: PMA_RX_CFG bit 22	GTX[1]: DRP[1] bit 7 GTX[1]: PMA_RX_CFG bit 23
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[1] bit 4 GTX[1]: PMA_RX_CFG bit 20	GTX[1]: DRP[1] bit 5 GTX[1]: PMA_RX_CFG bit 21
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[1] bit 2 GTX[1]: PMA_RX_CFG bit 18	GTX[1]: DRP[1] bit 3 GTX[1]: PMA_RX_CFG bit 19
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[1] bit 0 GTX[1]: PMA_RX_CFG bit 16	GTX[1]: DRP[1] bit 1 GTX[1]: PMA_RX_CFG bit 17
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[0] bit 14 GTX[1]: PMA_RX_CFG bit 14	GTX[1]: DRP[0] bit 15 GTX[1]: PMA_RX_CFG bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[0] bit 12 GTX[1]: PMA_RX_CFG bit 12	GTX[1]: DRP[0] bit 13 GTX[1]: PMA_RX_CFG bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[0] bit 10 GTX[1]: PMA_RX_CFG bit 10	GTX[1]: DRP[0] bit 11 GTX[1]: PMA_RX_CFG bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[0] bit 8 GTX[1]: PMA_RX_CFG bit 8	GTX[1]: DRP[0] bit 9 GTX[1]: PMA_RX_CFG bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[0] bit 6 GTX[1]: PMA_RX_CFG bit 6	GTX[1]: DRP[0] bit 7 GTX[1]: PMA_RX_CFG bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[0] bit 4 GTX[1]: PMA_RX_CFG bit 4	GTX[1]: DRP[0] bit 5 GTX[1]: PMA_RX_CFG bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[0] bit 2 GTX[1]: PMA_RX_CFG bit 2	GTX[1]: DRP[0] bit 3 GTX[1]: PMA_RX_CFG bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[0] bit 0 GTX[1]: PMA_RX_CFG bit 0	GTX[1]: DRP[0] bit 1 GTX[1]: PMA_RX_CFG bit 1

virtex6 GTX rect MAIN[11]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[15] bit 14 GTX[1]: CLK_COR_MIN_LAT bit 4	GTX[1]: DRP[15] bit 15 GTX[1]: CLK_COR_MIN_LAT bit 5
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[15] bit 12 GTX[1]: CLK_COR_MIN_LAT bit 2	GTX[1]: DRP[15] bit 13 GTX[1]: CLK_COR_MIN_LAT bit 3
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[15] bit 10 GTX[1]: CLK_COR_MIN_LAT bit 0	GTX[1]: DRP[15] bit 11 GTX[1]: CLK_COR_MIN_LAT bit 1
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[15] bit 8 GTX[1]: CLK_COR_SEQ_1_3 bit 8	GTX[1]: DRP[15] bit 9 GTX[1]: CLK_COR_SEQ_1_3 bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[15] bit 6 GTX[1]: CLK_COR_SEQ_1_3 bit 6	GTX[1]: DRP[15] bit 7 GTX[1]: CLK_COR_SEQ_1_3 bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[15] bit 4 GTX[1]: CLK_COR_SEQ_1_3 bit 4	GTX[1]: DRP[15] bit 5 GTX[1]: CLK_COR_SEQ_1_3 bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[15] bit 2 GTX[1]: CLK_COR_SEQ_1_3 bit 2	GTX[1]: DRP[15] bit 3 GTX[1]: CLK_COR_SEQ_1_3 bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[15] bit 0 GTX[1]: CLK_COR_SEQ_1_3 bit 0	GTX[1]: DRP[15] bit 1 GTX[1]: CLK_COR_SEQ_1_3 bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[14] bit 14 GTX[1]: CLK_COR_REPEAT_WAIT bit 4	GTX[1]: DRP[14] bit 15 GTX[1]: CLK_COR_KEEP_IDLE
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[14] bit 12 GTX[1]: CLK_COR_REPEAT_WAIT bit 2	GTX[1]: DRP[14] bit 13 GTX[1]: CLK_COR_REPEAT_WAIT bit 3
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[14] bit 10 GTX[1]: CLK_COR_REPEAT_WAIT bit 0	GTX[1]: DRP[14] bit 11 GTX[1]: CLK_COR_REPEAT_WAIT bit 1
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[14] bit 8 GTX[1]: CLK_COR_SEQ_1_2 bit 8	GTX[1]: DRP[14] bit 9 GTX[1]: CLK_COR_SEQ_1_2 bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[14] bit 6 GTX[1]: CLK_COR_SEQ_1_2 bit 6	GTX[1]: DRP[14] bit 7 GTX[1]: CLK_COR_SEQ_1_2 bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[14] bit 4 GTX[1]: CLK_COR_SEQ_1_2 bit 4	GTX[1]: DRP[14] bit 5 GTX[1]: CLK_COR_SEQ_1_2 bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[14] bit 2 GTX[1]: CLK_COR_SEQ_1_2 bit 2	GTX[1]: DRP[14] bit 3 GTX[1]: CLK_COR_SEQ_1_2 bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[14] bit 0 GTX[1]: CLK_COR_SEQ_1_2 bit 0	GTX[1]: DRP[14] bit 1 GTX[1]: CLK_COR_SEQ_1_2 bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[13] bit 14 GTX[1]: CLK_CORRECT_USE	GTX[1]: DRP[13] bit 15 GTX[1]: CLK_COR_PRECEDENCE
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[13] bit 12 GTX[1]: CLK_COR_SEQ_1_ENABLE bit 2	GTX[1]: DRP[13] bit 13 GTX[1]: CLK_COR_SEQ_1_ENABLE bit 3
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[13] bit 10 GTX[1]: CLK_COR_SEQ_1_ENABLE bit 0	GTX[1]: DRP[13] bit 11 GTX[1]: CLK_COR_SEQ_1_ENABLE bit 1
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[13] bit 8 GTX[1]: CLK_COR_SEQ_1_1 bit 8	GTX[1]: DRP[13] bit 9 GTX[1]: CLK_COR_SEQ_1_1 bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[13] bit 6 GTX[1]: CLK_COR_SEQ_1_1 bit 6	GTX[1]: DRP[13] bit 7 GTX[1]: CLK_COR_SEQ_1_1 bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[13] bit 4 GTX[1]: CLK_COR_SEQ_1_1 bit 4	GTX[1]: DRP[13] bit 5 GTX[1]: CLK_COR_SEQ_1_1 bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[13] bit 2 GTX[1]: CLK_COR_SEQ_1_1 bit 2	GTX[1]: DRP[13] bit 3 GTX[1]: CLK_COR_SEQ_1_1 bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[13] bit 0 GTX[1]: CLK_COR_SEQ_1_1 bit 0	GTX[1]: DRP[13] bit 1 GTX[1]: CLK_COR_SEQ_1_1 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTCLK[0]: CLKCM_CFG GTX[1]: DRP[12] bit 14	GTCLK[1]: CLKCM_CFG GTX[1]: DRP[12] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[12] bit 12 GTX[1]: RXBUF_OVRD_THRESH	GTX[1]: DRP[12] bit 13 GTX[1]: RX_FIFO_ADDR_MODE bit 0
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[12] bit 10 GTX[1]: RXBUF_UDFL_THRESH bit 4	GTX[1]: DRP[12] bit 11 GTX[1]: RXBUF_UDFL_THRESH bit 5
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[12] bit 8 GTX[1]: RXBUF_UDFL_THRESH bit 2	GTX[1]: DRP[12] bit 9 GTX[1]: RXBUF_UDFL_THRESH bit 3
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[12] bit 6 GTX[1]: RXBUF_UDFL_THRESH bit 0	GTX[1]: DRP[12] bit 7 GTX[1]: RXBUF_UDFL_THRESH bit 1
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[12] bit 4 GTX[1]: RXBUF_OVFL_THRESH bit 4	GTX[1]: DRP[12] bit 5 GTX[1]: RXBUF_OVFL_THRESH bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[12] bit 2 GTX[1]: RXBUF_OVFL_THRESH bit 2	GTX[1]: DRP[12] bit 3 GTX[1]: RXBUF_OVFL_THRESH bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[12] bit 0 GTX[1]: RXBUF_OVFL_THRESH bit 0	GTX[1]: DRP[12] bit 1 GTX[1]: RXBUF_OVFL_THRESH bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[11] bit 14 GTX[1]: RX_IDLE_HI_CNT bit 2	GTX[1]: DRP[11] bit 15 GTX[1]: RX_IDLE_HI_CNT bit 3
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[11] bit 12 GTX[1]: RX_IDLE_HI_CNT bit 0	GTX[1]: DRP[11] bit 13 GTX[1]: RX_IDLE_HI_CNT bit 1
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[11] bit 10 GTX[1]: RX_EN_IDLE_RESET_BUF	GTX[1]: DRP[11] bit 11 GTX[1]: RX_XCLK_SEL bit 0
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[11] bit 8 GTX[1]: CHAN_BOND_SEQ_2_4 bit 8	GTX[1]: DRP[11] bit 9 GTX[1]: CHAN_BOND_SEQ_2_4 bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[11] bit 6 GTX[1]: CHAN_BOND_SEQ_2_4 bit 6	GTX[1]: DRP[11] bit 7 GTX[1]: CHAN_BOND_SEQ_2_4 bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[11] bit 4 GTX[1]: CHAN_BOND_SEQ_2_4 bit 4	GTX[1]: DRP[11] bit 5 GTX[1]: CHAN_BOND_SEQ_2_4 bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[11] bit 2 GTX[1]: CHAN_BOND_SEQ_2_4 bit 2	GTX[1]: DRP[11] bit 3 GTX[1]: CHAN_BOND_SEQ_2_4 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[11] bit 0 GTX[1]: CHAN_BOND_SEQ_2_4 bit 0	GTX[1]: DRP[11] bit 1 GTX[1]: CHAN_BOND_SEQ_2_4 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[10] bit 14 GTX[1]: CHAN_BOND_SEQ_2_USE	GTX[1]: DRP[10] bit 15 GTX[1]: RX_EN_IDLE_RESET_PH
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[10] bit 12 GTX[1]: CHAN_BOND_SEQ_2_CFG bit 2	GTX[1]: DRP[10] bit 13 GTX[1]: CHAN_BOND_SEQ_2_CFG bit 3
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[10] bit 10 GTX[1]: CHAN_BOND_SEQ_2_CFG bit 0	GTX[1]: DRP[10] bit 11 GTX[1]: CHAN_BOND_SEQ_2_CFG bit 1
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[10] bit 8 GTX[1]: CHAN_BOND_SEQ_2_3 bit 8	GTX[1]: DRP[10] bit 9 GTX[1]: CHAN_BOND_SEQ_2_3 bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[10] bit 6 GTX[1]: CHAN_BOND_SEQ_2_3 bit 6	GTX[1]: DRP[10] bit 7 GTX[1]: CHAN_BOND_SEQ_2_3 bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[10] bit 4 GTX[1]: CHAN_BOND_SEQ_2_3 bit 4	GTX[1]: DRP[10] bit 5 GTX[1]: CHAN_BOND_SEQ_2_3 bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[10] bit 2 GTX[1]: CHAN_BOND_SEQ_2_3 bit 2	GTX[1]: DRP[10] bit 3 GTX[1]: CHAN_BOND_SEQ_2_3 bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[10] bit 0 GTX[1]: CHAN_BOND_SEQ_2_3 bit 0	GTX[1]: DRP[10] bit 1 GTX[1]: CHAN_BOND_SEQ_2_3 bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[9] bit 14 GTX[1]: CHAN_BOND_KEEP_ALIGN	GTX[1]: DRP[9] bit 15 GTX[1]: RX_EN_MODE_RESET_BUF
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[9] bit 12 GTX[1]: CHAN_BOND_2_MAX_SKEW bit 2	GTX[1]: DRP[9] bit 13 GTX[1]: CHAN_BOND_2_MAX_SKEW bit 3
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[9] bit 10 GTX[1]: CHAN_BOND_2_MAX_SKEW bit 0	GTX[1]: DRP[9] bit 11 GTX[1]: CHAN_BOND_2_MAX_SKEW bit 1
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[9] bit 8 GTX[1]: CHAN_BOND_SEQ_2_2 bit 8	GTX[1]: DRP[9] bit 9 GTX[1]: CHAN_BOND_SEQ_2_2 bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[9] bit 6 GTX[1]: CHAN_BOND_SEQ_2_2 bit 6	GTX[1]: DRP[9] bit 7 GTX[1]: CHAN_BOND_SEQ_2_2 bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[9] bit 4 GTX[1]: CHAN_BOND_SEQ_2_2 bit 4	GTX[1]: DRP[9] bit 5 GTX[1]: CHAN_BOND_SEQ_2_2 bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[9] bit 2 GTX[1]: CHAN_BOND_SEQ_2_2 bit 2	GTX[1]: DRP[9] bit 3 GTX[1]: CHAN_BOND_SEQ_2_2 bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[9] bit 0 GTX[1]: CHAN_BOND_SEQ_2_2 bit 0	GTX[1]: DRP[9] bit 1 GTX[1]: CHAN_BOND_SEQ_2_2 bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[8] bit 14 GTX[1]: RX_EN_REALIGN_RESET_BUF	GTX[1]: DRP[8] bit 15 GTX[1]: RX_EN_RATE_RESET_BUF
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[8] bit 12 GTX[1]: CHAN_BOND_SEQ_2_ENABLE bit 2	GTX[1]: DRP[8] bit 13 GTX[1]: CHAN_BOND_SEQ_2_ENABLE bit 3
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[8] bit 10 GTX[1]: CHAN_BOND_SEQ_2_ENABLE bit 0	GTX[1]: DRP[8] bit 11 GTX[1]: CHAN_BOND_SEQ_2_ENABLE bit 1
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[8] bit 8 GTX[1]: CHAN_BOND_SEQ_2_1 bit 8	GTX[1]: DRP[8] bit 9 GTX[1]: CHAN_BOND_SEQ_2_1 bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[8] bit 6 GTX[1]: CHAN_BOND_SEQ_2_1 bit 6	GTX[1]: DRP[8] bit 7 GTX[1]: CHAN_BOND_SEQ_2_1 bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[8] bit 4 GTX[1]: CHAN_BOND_SEQ_2_1 bit 4	GTX[1]: DRP[8] bit 5 GTX[1]: CHAN_BOND_SEQ_2_1 bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[8] bit 2 GTX[1]: CHAN_BOND_SEQ_2_1 bit 2	GTX[1]: DRP[8] bit 3 GTX[1]: CHAN_BOND_SEQ_2_1 bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[8] bit 0 GTX[1]: CHAN_BOND_SEQ_2_1 bit 0	GTX[1]: DRP[8] bit 1 GTX[1]: CHAN_BOND_SEQ_2_1 bit 1

virtex6 GTX rect MAIN[12]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[23] bit 14 GTX[1]: RX_DATA_WIDTH bit 2	GTX[1]: DRP[23] bit 15 GTX[1]: GEN_RXUSRCLK
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[23] bit 12 GTX[1]: RX_DATA_WIDTH bit 0	GTX[1]: DRP[23] bit 13 GTX[1]: RX_DATA_WIDTH bit 1
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[23] bit 10 GTX[1]: BIAS_CFG bit 16	GTX[1]: DRP[23] bit 11 GTX[1]: CHAN_BOND_SEQ_2_CFG bit 4
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[23] bit 8 GTX[1]: RX_CLK25_DIVIDER bit 3	GTX[1]: DRP[23] bit 9 GTX[1]: RX_CLK25_DIVIDER bit 4
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[23] bit 6 GTX[1]: RX_CLK25_DIVIDER bit 1	GTX[1]: DRP[23] bit 7 GTX[1]: RX_CLK25_DIVIDER bit 2
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[23] bit 4 GTX[1]: AC_CAP_DIS	GTX[1]: DRP[23] bit 5 GTX[1]: RX_CLK25_DIVIDER bit 0
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[23] bit 2 GTX[1]: OOBDETECT_THRESHOLD bit 2	GTX[1]: DRP[23] bit 3 GTX[1]: GTX_CFG_PWRUP
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[23] bit 0 GTX[1]: OOBDETECT_THRESHOLD bit 0	GTX[1]: DRP[23] bit 1 GTX[1]: OOBDETECT_THRESHOLD bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[22] bit 14 GTX[1]: CDR_PH_ADJ_TIME bit 3	GTX[1]: DRP[22] bit 15 GTX[1]: CDR_PH_ADJ_TIME bit 4
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[22] bit 12 GTX[1]: CDR_PH_ADJ_TIME bit 1	GTX[1]: DRP[22] bit 13 GTX[1]: CDR_PH_ADJ_TIME bit 2
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[22] bit 10 GTX[1]: PMA_CDR_SCAN bit 26	GTX[1]: DRP[22] bit 11 GTX[1]: CDR_PH_ADJ_TIME bit 0
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[22] bit 8 GTX[1]: PMA_CDR_SCAN bit 24	GTX[1]: DRP[22] bit 9 GTX[1]: PMA_CDR_SCAN bit 25
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[22] bit 6 GTX[1]: PMA_CDR_SCAN bit 22	GTX[1]: DRP[22] bit 7 GTX[1]: PMA_CDR_SCAN bit 23
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[22] bit 4 GTX[1]: PMA_CDR_SCAN bit 20	GTX[1]: DRP[22] bit 5 GTX[1]: PMA_CDR_SCAN bit 21
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[22] bit 2 GTX[1]: PMA_CDR_SCAN bit 18	GTX[1]: DRP[22] bit 3 GTX[1]: PMA_CDR_SCAN bit 19
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[22] bit 0 GTX[1]: PMA_CDR_SCAN bit 16	GTX[1]: DRP[22] bit 1 GTX[1]: PMA_CDR_SCAN bit 17
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[21] bit 14 GTX[1]: PMA_CDR_SCAN bit 14	GTX[1]: DRP[21] bit 15 GTX[1]: PMA_CDR_SCAN bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[21] bit 12 GTX[1]: PMA_CDR_SCAN bit 12	GTX[1]: DRP[21] bit 13 GTX[1]: PMA_CDR_SCAN bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[21] bit 10 GTX[1]: PMA_CDR_SCAN bit 10	GTX[1]: DRP[21] bit 11 GTX[1]: PMA_CDR_SCAN bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[21] bit 8 GTX[1]: PMA_CDR_SCAN bit 8	GTX[1]: DRP[21] bit 9 GTX[1]: PMA_CDR_SCAN bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[21] bit 6 GTX[1]: PMA_CDR_SCAN bit 6	GTX[1]: DRP[21] bit 7 GTX[1]: PMA_CDR_SCAN bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[21] bit 4 GTX[1]: PMA_CDR_SCAN bit 4	GTX[1]: DRP[21] bit 5 GTX[1]: PMA_CDR_SCAN bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[21] bit 2 GTX[1]: PMA_CDR_SCAN bit 2	GTX[1]: DRP[21] bit 3 GTX[1]: PMA_CDR_SCAN bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[21] bit 0 GTX[1]: PMA_CDR_SCAN bit 0	GTX[1]: DRP[21] bit 1 GTX[1]: PMA_CDR_SCAN bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[20] bit 14 GTX[1]: ALIGN_COMMA_WORD bit 0	GTX[1]: DRP[20] bit 15 GTX[1]: DEC_VALID_COMMA_ONLY
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[20] bit 12 GTX[1]: USR_CODE_ERR_CLR bit 0	GTX[1]: DRP[20] bit 13 GTX[1]: RX_DECODE_SEQ_MATCH
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[20] bit 10 GTX[1]: DEC_PCOMMA_DETECT	GTX[1]: DRP[20] bit 11 GTX[1]: DEC_MCOMMA_DETECT
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[20] bit 8 GTX[1]: CLK_COR_SEQ_2_4 bit 8	GTX[1]: DRP[20] bit 9 GTX[1]: CLK_COR_SEQ_2_4 bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[20] bit 6 GTX[1]: CLK_COR_SEQ_2_4 bit 6	GTX[1]: DRP[20] bit 7 GTX[1]: CLK_COR_SEQ_2_4 bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[20] bit 4 GTX[1]: CLK_COR_SEQ_2_4 bit 4	GTX[1]: DRP[20] bit 5 GTX[1]: CLK_COR_SEQ_2_4 bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[20] bit 2 GTX[1]: CLK_COR_SEQ_2_4 bit 2	GTX[1]: DRP[20] bit 3 GTX[1]: CLK_COR_SEQ_2_4 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[20] bit 0 GTX[1]: CLK_COR_SEQ_2_4 bit 0	GTX[1]: DRP[20] bit 1 GTX[1]: CLK_COR_SEQ_2_4 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[19] bit 14 GTX[1]: RX_SLIDE_AUTO_WAIT bit 2	GTX[1]: DRP[19] bit 15 GTX[1]: RX_SLIDE_AUTO_WAIT bit 3
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[19] bit 12 GTX[1]: RX_SLIDE_AUTO_WAIT bit 0	GTX[1]: DRP[19] bit 13 GTX[1]: RX_SLIDE_AUTO_WAIT bit 1
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[19] bit 10 GTX[1]: CLK_COR_DET_LEN bit 0	GTX[1]: DRP[19] bit 11 GTX[1]: CLK_COR_DET_LEN bit 1
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[19] bit 8 GTX[1]: CLK_COR_SEQ_2_3 bit 8	GTX[1]: DRP[19] bit 9 GTX[1]: CLK_COR_SEQ_2_3 bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[19] bit 6 GTX[1]: CLK_COR_SEQ_2_3 bit 6	GTX[1]: DRP[19] bit 7 GTX[1]: CLK_COR_SEQ_2_3 bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[19] bit 4 GTX[1]: CLK_COR_SEQ_2_3 bit 4	GTX[1]: DRP[19] bit 5 GTX[1]: CLK_COR_SEQ_2_3 bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[19] bit 2 GTX[1]: CLK_COR_SEQ_2_3 bit 2	GTX[1]: DRP[19] bit 3 GTX[1]: CLK_COR_SEQ_2_3 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[19] bit 0 GTX[1]: CLK_COR_SEQ_2_3 bit 0	GTX[1]: DRP[19] bit 1 GTX[1]: CLK_COR_SEQ_2_3 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[18] bit 14 GTX[1]: SHOW_REALIGN_COMMA	GTX[1]: DRP[18] bit 15 GTX[1]: RX_CDR_FORCE_ROTATE
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[18] bit 12 GTX[1]: RX_SLIDE_MODE bit 0	GTX[1]: DRP[18] bit 13 GTX[1]: RX_SLIDE_MODE bit 1
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[18] bit 10 GTX[1]: CLK_COR_ADJ_LEN bit 0	GTX[1]: DRP[18] bit 11 GTX[1]: CLK_COR_ADJ_LEN bit 1
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[18] bit 8 GTX[1]: CLK_COR_SEQ_2_2 bit 8	GTX[1]: DRP[18] bit 9 GTX[1]: CLK_COR_SEQ_2_2 bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[18] bit 6 GTX[1]: CLK_COR_SEQ_2_2 bit 6	GTX[1]: DRP[18] bit 7 GTX[1]: CLK_COR_SEQ_2_2 bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[18] bit 4 GTX[1]: CLK_COR_SEQ_2_2 bit 4	GTX[1]: DRP[18] bit 5 GTX[1]: CLK_COR_SEQ_2_2 bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[18] bit 2 GTX[1]: CLK_COR_SEQ_2_2 bit 2	GTX[1]: DRP[18] bit 3 GTX[1]: CLK_COR_SEQ_2_2 bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[18] bit 0 GTX[1]: CLK_COR_SEQ_2_2 bit 0	GTX[1]: DRP[18] bit 1 GTX[1]: CLK_COR_SEQ_2_2 bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[17] bit 14 GTX[1]: CLK_COR_SEQ_2_USE	GTX[1]: DRP[17] bit 15 GTX[1]: CLK_COR_INSERT_IDLE_FLAG
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[17] bit 12 GTX[1]: CLK_COR_SEQ_2_ENABLE bit 2	GTX[1]: DRP[17] bit 13 GTX[1]: CLK_COR_SEQ_2_ENABLE bit 3
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[17] bit 10 GTX[1]: CLK_COR_SEQ_2_ENABLE bit 0	GTX[1]: DRP[17] bit 11 GTX[1]: CLK_COR_SEQ_2_ENABLE bit 1
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[17] bit 8 GTX[1]: CLK_COR_SEQ_2_1 bit 8	GTX[1]: DRP[17] bit 9 GTX[1]: CLK_COR_SEQ_2_1 bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[17] bit 6 GTX[1]: CLK_COR_SEQ_2_1 bit 6	GTX[1]: DRP[17] bit 7 GTX[1]: CLK_COR_SEQ_2_1 bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[17] bit 4 GTX[1]: CLK_COR_SEQ_2_1 bit 4	GTX[1]: DRP[17] bit 5 GTX[1]: CLK_COR_SEQ_2_1 bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[17] bit 2 GTX[1]: CLK_COR_SEQ_2_1 bit 2	GTX[1]: DRP[17] bit 3 GTX[1]: CLK_COR_SEQ_2_1 bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[17] bit 0 GTX[1]: CLK_COR_SEQ_2_1 bit 0	GTX[1]: DRP[17] bit 1 GTX[1]: CLK_COR_SEQ_2_1 bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[16] bit 14 GTX[1]: CLK_COR_MAX_LAT bit 4	GTX[1]: DRP[16] bit 15 GTX[1]: CLK_COR_MAX_LAT bit 5
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[16] bit 12 GTX[1]: CLK_COR_MAX_LAT bit 2	GTX[1]: DRP[16] bit 13 GTX[1]: CLK_COR_MAX_LAT bit 3
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[16] bit 10 GTX[1]: CLK_COR_MAX_LAT bit 0	GTX[1]: DRP[16] bit 11 GTX[1]: CLK_COR_MAX_LAT bit 1
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[16] bit 8 GTX[1]: CLK_COR_SEQ_1_4 bit 8	GTX[1]: DRP[16] bit 9 GTX[1]: CLK_COR_SEQ_1_4 bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[16] bit 6 GTX[1]: CLK_COR_SEQ_1_4 bit 6	GTX[1]: DRP[16] bit 7 GTX[1]: CLK_COR_SEQ_1_4 bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[16] bit 4 GTX[1]: CLK_COR_SEQ_1_4 bit 4	GTX[1]: DRP[16] bit 5 GTX[1]: CLK_COR_SEQ_1_4 bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[16] bit 2 GTX[1]: CLK_COR_SEQ_1_4 bit 2	GTX[1]: DRP[16] bit 3 GTX[1]: CLK_COR_SEQ_1_4 bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[16] bit 0 GTX[1]: CLK_COR_SEQ_1_4 bit 0	GTX[1]: DRP[16] bit 1 GTX[1]: CLK_COR_SEQ_1_4 bit 1

virtex6 GTX rect MAIN[13]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[31] bit 14 GTX[1]: TXPLL_DIVSEL_OUT bit 0	GTX[1]: DRP[31] bit 15 GTX[1]: TXPLL_DIVSEL_OUT bit 1
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[31] bit 12 GTX[1]: TXPLL_LKDET_CFG bit 1	GTX[1]: DRP[31] bit 13 GTX[1]: TXPLL_LKDET_CFG bit 2
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[31] bit 10 GTX[1]: A_TXPOWERDOWN bit 1	GTX[1]: DRP[31] bit 11 GTX[1]: TXPLL_LKDET_CFG bit 0
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[31] bit 8 GTX[1]: TX_CLK_SOURCE bit 0	GTX[1]: DRP[31] bit 9 GTX[1]: A_TXPOWERDOWN bit 0
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[31] bit 6 GTX[1]: TXPLL_DIVSEL45_FB bit 0	GTX[1]: DRP[31] bit 7 GTX[1]: TXPLL_STARTUP_EN
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[31] bit 4 GTX[1]: TXPLL_DIVSEL_FB bit 3	GTX[1]: DRP[31] bit 5 GTX[1]: TXPLL_DIVSEL_FB bit 4
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[31] bit 2 GTX[1]: TXPLL_DIVSEL_FB bit 1	GTX[1]: DRP[31] bit 3 GTX[1]: TXPLL_DIVSEL_FB bit 2
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[31] bit 0	GTX[1]: DRP[31] bit 1 GTX[1]: TXPLL_DIVSEL_FB bit 0
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[30] bit 14 GTX[1]: TXPLL_CP_CFG bit 6	GTX[1]: DRP[30] bit 15 GTX[1]: TXPLL_CP_CFG bit 7
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[30] bit 12 GTX[1]: TXPLL_CP_CFG bit 4	GTX[1]: DRP[30] bit 13 GTX[1]: TXPLL_CP_CFG bit 5
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[30] bit 10 GTX[1]: TXPLL_CP_CFG bit 2	GTX[1]: DRP[30] bit 11 GTX[1]: TXPLL_CP_CFG bit 3
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[30] bit 8 GTX[1]: TXPLL_CP_CFG bit 0	GTX[1]: DRP[30] bit 9 GTX[1]: TXPLL_CP_CFG bit 1
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[30] bit 6 GTX[1]: TXPLL_COM_CFG bit 22	GTX[1]: DRP[30] bit 7 GTX[1]: TXPLL_COM_CFG bit 23
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[30] bit 4 GTX[1]: TXPLL_COM_CFG bit 20	GTX[1]: DRP[30] bit 5 GTX[1]: TXPLL_COM_CFG bit 21
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[30] bit 2 GTX[1]: TXPLL_COM_CFG bit 18	GTX[1]: DRP[30] bit 3 GTX[1]: TXPLL_COM_CFG bit 19
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[30] bit 0 GTX[1]: TXPLL_COM_CFG bit 16	GTX[1]: DRP[30] bit 1 GTX[1]: TXPLL_COM_CFG bit 17
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[29] bit 14 GTX[1]: TXPLL_COM_CFG bit 14	GTX[1]: DRP[29] bit 15 GTX[1]: TXPLL_COM_CFG bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[29] bit 12 GTX[1]: TXPLL_COM_CFG bit 12	GTX[1]: DRP[29] bit 13 GTX[1]: TXPLL_COM_CFG bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[29] bit 10 GTX[1]: TXPLL_COM_CFG bit 10	GTX[1]: DRP[29] bit 11 GTX[1]: TXPLL_COM_CFG bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[29] bit 8 GTX[1]: TXPLL_COM_CFG bit 8	GTX[1]: DRP[29] bit 9 GTX[1]: TXPLL_COM_CFG bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[29] bit 6 GTX[1]: TXPLL_COM_CFG bit 6	GTX[1]: DRP[29] bit 7 GTX[1]: TXPLL_COM_CFG bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[29] bit 4 GTX[1]: TXPLL_COM_CFG bit 4	GTX[1]: DRP[29] bit 5 GTX[1]: TXPLL_COM_CFG bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[29] bit 2 GTX[1]: TXPLL_COM_CFG bit 2	GTX[1]: DRP[29] bit 3 GTX[1]: TXPLL_COM_CFG bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[29] bit 0 GTX[1]: TXPLL_COM_CFG bit 0	GTX[1]: DRP[29] bit 1 GTX[1]: TXPLL_COM_CFG bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[28] bit 14 GTX[1]: A_RXPLLPOWERDOWN bit 0	GTX[1]: DRP[28] bit 15 GTX[1]: RX_OVERSAMPLE_MODE
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[28] bit 12 GTX[1]: A_PLLCLKRXRESET bit 0	GTX[1]: DRP[28] bit 13 GTX[1]: PLL_DRP_EN
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[28] bit 10 GTX[1]: A_PLLRXRESET bit 0	GTX[1]: DRP[28] bit 11 GTX[1]: A_RXPLLLKDETEN bit 0
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[28] bit 8 GTX[1]: RXPLLREFSEL_STATIC_VAL bit 1	GTX[1]: DRP[28] bit 9 GTX[1]: RXPLLREFSEL_STATIC_VAL bit 2
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[28] bit 6 GTX[1]: RXPLLREFSEL_MODE_DYNAMIC	GTX[1]: DRP[28] bit 7 GTX[1]: RXPLLREFSEL_STATIC_VAL bit 0
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[28] bit 4 GTX[1]: RXPLL_DIVSEL_REF bit 3	GTX[1]: DRP[28] bit 5 GTX[1]: RXPLL_DIVSEL_REF bit 4
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[28] bit 2 GTX[1]: RXPLL_DIVSEL_REF bit 1	GTX[1]: DRP[28] bit 3 GTX[1]: RXPLL_DIVSEL_REF bit 2
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[28] bit 0 GTX[1]: RXPLLREFSEL_TESTCLK bit 0	GTX[1]: DRP[28] bit 1 GTX[1]: RXPLL_DIVSEL_REF bit 0
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[27] bit 14 GTX[1]: RXPLL_DIVSEL_OUT bit 0	GTX[1]: DRP[27] bit 15 GTX[1]: RXPLL_DIVSEL_OUT bit 1
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[27] bit 12 GTX[1]: RXPLL_LKDET_CFG bit 1	GTX[1]: DRP[27] bit 13 GTX[1]: RXPLL_LKDET_CFG bit 2
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[27] bit 10 GTX[1]: A_RXPOWERDOWN bit 1	GTX[1]: DRP[27] bit 11 GTX[1]: RXPLL_LKDET_CFG bit 0
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[27] bit 8	GTX[1]: DRP[27] bit 9 GTX[1]: A_RXPOWERDOWN bit 0
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[27] bit 6 GTX[1]: RXPLL_DIVSEL45_FB bit 0	GTX[1]: DRP[27] bit 7 GTX[1]: RXPLL_STARTUP_EN
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[27] bit 4 GTX[1]: RXPLL_DIVSEL_FB bit 3	GTX[1]: DRP[27] bit 5 GTX[1]: RXPLL_DIVSEL_FB bit 4
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[27] bit 2 GTX[1]: RXPLL_DIVSEL_FB bit 1	GTX[1]: DRP[27] bit 3 GTX[1]: RXPLL_DIVSEL_FB bit 2
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[27] bit 0	GTX[1]: DRP[27] bit 1 GTX[1]: RXPLL_DIVSEL_FB bit 0
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[26] bit 14 GTX[1]: RXPLL_CP_CFG bit 6	GTX[1]: DRP[26] bit 15 GTX[1]: RXPLL_CP_CFG bit 7
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[26] bit 12 GTX[1]: RXPLL_CP_CFG bit 4	GTX[1]: DRP[26] bit 13 GTX[1]: RXPLL_CP_CFG bit 5
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[26] bit 10 GTX[1]: RXPLL_CP_CFG bit 2	GTX[1]: DRP[26] bit 11 GTX[1]: RXPLL_CP_CFG bit 3
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[26] bit 8 GTX[1]: RXPLL_CP_CFG bit 0	GTX[1]: DRP[26] bit 9 GTX[1]: RXPLL_CP_CFG bit 1
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[26] bit 6 GTX[1]: RXPLL_COM_CFG bit 22	GTX[1]: DRP[26] bit 7 GTX[1]: RXPLL_COM_CFG bit 23
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[26] bit 4 GTX[1]: RXPLL_COM_CFG bit 20	GTX[1]: DRP[26] bit 5 GTX[1]: RXPLL_COM_CFG bit 21
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[26] bit 2 GTX[1]: RXPLL_COM_CFG bit 18	GTX[1]: DRP[26] bit 3 GTX[1]: RXPLL_COM_CFG bit 19
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[26] bit 0 GTX[1]: RXPLL_COM_CFG bit 16	GTX[1]: DRP[26] bit 1 GTX[1]: RXPLL_COM_CFG bit 17
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[25] bit 14 GTX[1]: RXPLL_COM_CFG bit 14	GTX[1]: DRP[25] bit 15 GTX[1]: RXPLL_COM_CFG bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[25] bit 12 GTX[1]: RXPLL_COM_CFG bit 12	GTX[1]: DRP[25] bit 13 GTX[1]: RXPLL_COM_CFG bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[25] bit 10 GTX[1]: RXPLL_COM_CFG bit 10	GTX[1]: DRP[25] bit 11 GTX[1]: RXPLL_COM_CFG bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[25] bit 8 GTX[1]: RXPLL_COM_CFG bit 8	GTX[1]: DRP[25] bit 9 GTX[1]: RXPLL_COM_CFG bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[25] bit 6 GTX[1]: RXPLL_COM_CFG bit 6	GTX[1]: DRP[25] bit 7 GTX[1]: RXPLL_COM_CFG bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[25] bit 4 GTX[1]: RXPLL_COM_CFG bit 4	GTX[1]: DRP[25] bit 5 GTX[1]: RXPLL_COM_CFG bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[25] bit 2 GTX[1]: RXPLL_COM_CFG bit 2	GTX[1]: DRP[25] bit 3 GTX[1]: RXPLL_COM_CFG bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[25] bit 0 GTX[1]: RXPLL_COM_CFG bit 0	GTX[1]: DRP[25] bit 1 GTX[1]: RXPLL_COM_CFG bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[24] bit 14 GTX[1]: RESET_DRP_EN	GTX[1]: DRP[24] bit 15 GTX[1]: MASTER_DRP_EN
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[24] bit 12 GTX[1]: A_RXCDRPHASERESET bit 0	GTX[1]: DRP[24] bit 13 GTX[1]: A_RXDFERESET bit 0
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[24] bit 10 GTX[1]: A_RXCDRHOLD bit 0	GTX[1]: DRP[24] bit 11 GTX[1]: A_RXCDRFREQRESET bit 0
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[24] bit 8 GTX[1]: A_RXRESET bit 0	GTX[1]: DRP[24] bit 9 GTX[1]: A_TXRESET bit 0
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[24] bit 6 GTX[1]: A_GTXRXRESET bit 0	GTX[1]: DRP[24] bit 7 GTX[1]: A_RXBUFRESET bit 0
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[24] bit 4 GTX[1]: A_RXCDRRESET bit 0	GTX[1]: DRP[24] bit 5 GTX[1]: A_GTXTXRESET bit 0
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[24] bit 2 GTX[1]: GEARBOX_ENDEC bit 2	GTX[1]: DRP[24] bit 3 GTX[1]: RXGEARBOX_USE
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[24] bit 0 GTX[1]: GEARBOX_ENDEC bit 0	GTX[1]: DRP[24] bit 1 GTX[1]: GEARBOX_ENDEC bit 1

virtex6 GTX rect MAIN[14]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[39] bit 14 GTX[1]: SATA_IDLE_VAL bit 2	GTX[1]: DRP[39] bit 15 GTX[1]: TX_EN_RATE_RESET_BUF
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[39] bit 12 GTX[1]: SATA_IDLE_VAL bit 0	GTX[1]: DRP[39] bit 13 GTX[1]: SATA_IDLE_VAL bit 1
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[39] bit 10 GTX[1]: SATA_MIN_INIT bit 4	GTX[1]: DRP[39] bit 11 GTX[1]: SATA_MIN_INIT bit 5
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[39] bit 8 GTX[1]: SATA_MIN_INIT bit 2	GTX[1]: DRP[39] bit 9 GTX[1]: SATA_MIN_INIT bit 3
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[39] bit 6 GTX[1]: SATA_MIN_INIT bit 0	GTX[1]: DRP[39] bit 7 GTX[1]: SATA_MIN_INIT bit 1
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[39] bit 4 GTX[1]: SATA_MAX_INIT bit 4	GTX[1]: DRP[39] bit 5 GTX[1]: SATA_MAX_INIT bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[39] bit 2 GTX[1]: SATA_MAX_INIT bit 2	GTX[1]: DRP[39] bit 3 GTX[1]: SATA_MAX_INIT bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[39] bit 0 GTX[1]: SATA_MAX_INIT bit 0	GTX[1]: DRP[39] bit 1 GTX[1]: SATA_MAX_INIT bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[38] bit 14 GTX[1]: BGTEST_CFG bit 0	GTX[1]: DRP[38] bit 15 GTX[1]: BGTEST_CFG bit 1
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[38] bit 12 GTX[1]: TXPLL_SATA bit 0	GTX[1]: DRP[38] bit 13 GTX[1]: TXPLL_SATA bit 1
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[38] bit 10 GTX[1]: SATA_MIN_WAKE bit 4	GTX[1]: DRP[38] bit 11 GTX[1]: SATA_MIN_WAKE bit 5
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[38] bit 8 GTX[1]: SATA_MIN_WAKE bit 2	GTX[1]: DRP[38] bit 9 GTX[1]: SATA_MIN_WAKE bit 3
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[38] bit 6 GTX[1]: SATA_MIN_WAKE bit 0	GTX[1]: DRP[38] bit 7 GTX[1]: SATA_MIN_WAKE bit 1
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[38] bit 4 GTX[1]: SATA_MAX_WAKE bit 4	GTX[1]: DRP[38] bit 5 GTX[1]: SATA_MAX_WAKE bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[38] bit 2 GTX[1]: SATA_MAX_WAKE bit 2	GTX[1]: DRP[38] bit 3 GTX[1]: SATA_MAX_WAKE bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[38] bit 0 GTX[1]: SATA_MAX_WAKE bit 0	GTX[1]: DRP[38] bit 1 GTX[1]: SATA_MAX_WAKE bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[37] bit 14 GTX[1]: A_RXENPMAPHASEALIGN bit 0	GTX[1]: DRP[37] bit 15 GTX[1]: TX_PMADATA_OPT bit 0
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[37] bit 12 GTX[1]: POLARITY_DRP_EN	GTX[1]: DRP[37] bit 13 GTX[1]: A_RXPMASETPHASE bit 0
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[37] bit 10 GTX[1]: A_RXPOLARITY bit 0	GTX[1]: DRP[37] bit 11 GTX[1]: A_TXPOLARITY bit 0
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[37] bit 8 GTX[1]: CM_TRIM bit 0	GTX[1]: DRP[37] bit 9 GTX[1]: CM_TRIM bit 1
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[37] bit 6 GTX[1]: TRANS_TIME_NON_P2 bit 6	GTX[1]: DRP[37] bit 7 GTX[1]: TRANS_TIME_NON_P2 bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[37] bit 4 GTX[1]: TRANS_TIME_NON_P2 bit 4	GTX[1]: DRP[37] bit 5 GTX[1]: TRANS_TIME_NON_P2 bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[37] bit 2 GTX[1]: TRANS_TIME_NON_P2 bit 2	GTX[1]: DRP[37] bit 3 GTX[1]: TRANS_TIME_NON_P2 bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[37] bit 0 GTX[1]: TRANS_TIME_NON_P2 bit 0	GTX[1]: DRP[37] bit 1 GTX[1]: TRANS_TIME_NON_P2 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[36] bit 14 GTX[1]: COM_BURST_VAL bit 2	GTX[1]: DRP[36] bit 15 GTX[1]: COM_BURST_VAL bit 3
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[36] bit 12 GTX[1]: COM_BURST_VAL bit 0	GTX[1]: DRP[36] bit 13 GTX[1]: COM_BURST_VAL bit 1
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[36] bit 10 GTX[1]: TRANS_TIME_FROM_P2 bit 10	GTX[1]: DRP[36] bit 11 GTX[1]: TRANS_TIME_FROM_P2 bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[36] bit 8 GTX[1]: TRANS_TIME_FROM_P2 bit 8	GTX[1]: DRP[36] bit 9 GTX[1]: TRANS_TIME_FROM_P2 bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[36] bit 6 GTX[1]: TRANS_TIME_FROM_P2 bit 6	GTX[1]: DRP[36] bit 7 GTX[1]: TRANS_TIME_FROM_P2 bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[36] bit 4 GTX[1]: TRANS_TIME_FROM_P2 bit 4	GTX[1]: DRP[36] bit 5 GTX[1]: TRANS_TIME_FROM_P2 bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[36] bit 2 GTX[1]: TRANS_TIME_FROM_P2 bit 2	GTX[1]: DRP[36] bit 3 GTX[1]: TRANS_TIME_FROM_P2 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[36] bit 0 GTX[1]: TRANS_TIME_FROM_P2 bit 0	GTX[1]: DRP[36] bit 1 GTX[1]: TRANS_TIME_FROM_P2 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[35] bit 14 GTX[1]: TX_CLK25_DIVIDER bit 4	GTX[1]: DRP[35] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[35] bit 12 GTX[1]: TX_CLK25_DIVIDER bit 2	GTX[1]: DRP[35] bit 13 GTX[1]: TX_CLK25_DIVIDER bit 3
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[35] bit 10 GTX[1]: TX_CLK25_DIVIDER bit 0	GTX[1]: DRP[35] bit 11 GTX[1]: TX_CLK25_DIVIDER bit 1
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[35] bit 8 GTX[1]: TRANS_TIME_TO_P2 bit 8	GTX[1]: DRP[35] bit 9 GTX[1]: TRANS_TIME_TO_P2 bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[35] bit 6 GTX[1]: TRANS_TIME_TO_P2 bit 6	GTX[1]: DRP[35] bit 7 GTX[1]: TRANS_TIME_TO_P2 bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[35] bit 4 GTX[1]: TRANS_TIME_TO_P2 bit 4	GTX[1]: DRP[35] bit 5 GTX[1]: TRANS_TIME_TO_P2 bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[35] bit 2 GTX[1]: TRANS_TIME_TO_P2 bit 2	GTX[1]: DRP[35] bit 3 GTX[1]: TRANS_TIME_TO_P2 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[35] bit 0 GTX[1]: TRANS_TIME_TO_P2 bit 0	GTX[1]: DRP[35] bit 1 GTX[1]: TRANS_TIME_TO_P2 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[20].IMUX_GTX_PERFCLK bit 0 GTX[1]: DRP[34] bit 14	GTX[1]: DRP[34] bit 15 GTX[1]: PMA_CAS_CLK_EN
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[20].IMUX_GTX_PERFCLK bit 1 GTX[1]: DRP[34] bit 12	SPEC_INT: mux CELL[20].IMUX_GTX_PERFCLK bit 2 GTX[1]: DRP[34] bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[34] bit 10	GTX[1]: DRP[34] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[34] bit 8	GTX[1]: DRP[34] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[34] bit 6	GTX[1]: DRP[34] bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[34] bit 4	GTX[1]: DRP[34] bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[34] bit 2	GTX[1]: DRP[34] bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[34] bit 0	GTX[1]: DRP[34] bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[33] bit 14 GTX[1]: A_TXELECIDLE bit 0	GTX[1]: DRP[33] bit 15 GTX[1]: PCI_EXPRESS_MODE
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[33] bit 12 GTX[1]: TX_DETECT_RX_CFG bit 12	GTX[1]: DRP[33] bit 13 GTX[1]: TX_DETECT_RX_CFG bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[33] bit 10 GTX[1]: TX_DETECT_RX_CFG bit 10	GTX[1]: DRP[33] bit 11 GTX[1]: TX_DETECT_RX_CFG bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[33] bit 8 GTX[1]: TX_DETECT_RX_CFG bit 8	GTX[1]: DRP[33] bit 9 GTX[1]: TX_DETECT_RX_CFG bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[33] bit 6 GTX[1]: TX_DETECT_RX_CFG bit 6	GTX[1]: DRP[33] bit 7 GTX[1]: TX_DETECT_RX_CFG bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[33] bit 4 GTX[1]: TX_DETECT_RX_CFG bit 4	GTX[1]: DRP[33] bit 5 GTX[1]: TX_DETECT_RX_CFG bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[33] bit 2 GTX[1]: TX_DETECT_RX_CFG bit 2	GTX[1]: DRP[33] bit 3 GTX[1]: TX_DETECT_RX_CFG bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[33] bit 0 GTX[1]: TX_DETECT_RX_CFG bit 0	GTX[1]: DRP[33] bit 1 GTX[1]: TX_DETECT_RX_CFG bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[32] bit 14 GTX[1]: A_TXPLLPOWERDOWN bit 0	GTX[1]: DRP[32] bit 15 GTX[1]: TX_OVERSAMPLE_MODE
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[32] bit 12 GTX[1]: A_PLLCLKTXRESET bit 0	GTX[1]: DRP[32] bit 13 GTX[1]: PDELIDLE_DRP_EN
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[32] bit 10 GTX[1]: A_PLLTXRESET bit 0	GTX[1]: DRP[32] bit 11 GTX[1]: A_TXPLLLKDETEN bit 0
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[32] bit 8 GTX[1]: TXPLLREFSEL_STATIC_VAL bit 1	GTX[1]: DRP[32] bit 9 GTX[1]: TXPLLREFSEL_STATIC_VAL bit 2
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[32] bit 6 GTX[1]: TXPLLREFSEL_MODE_DYNAMIC	GTX[1]: DRP[32] bit 7 GTX[1]: TXPLLREFSEL_STATIC_VAL bit 0
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[32] bit 4 GTX[1]: TXPLL_DIVSEL_REF bit 3	GTX[1]: DRP[32] bit 5 GTX[1]: TXPLL_DIVSEL_REF bit 4
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[32] bit 2 GTX[1]: TXPLL_DIVSEL_REF bit 1	GTX[1]: DRP[32] bit 3 GTX[1]: TXPLL_DIVSEL_REF bit 2
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[32] bit 0 GTX[1]: TXPLLREFSEL_TESTCLK bit 0	GTX[1]: DRP[32] bit 1 GTX[1]: TXPLL_DIVSEL_REF bit 0

virtex6 GTX rect MAIN[15]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[47] bit 14 GTX[1]: TX_XCLK_SEL bit 0	GTX[1]: DRP[47] bit 15 GTX[1]: TXGEARBOX_USE
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[47] bit 12 GTX[1]: TX_IDLE_ASSERT_DELAY bit 1	GTX[1]: DRP[47] bit 13 GTX[1]: TX_IDLE_ASSERT_DELAY bit 2
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[47] bit 10 GTX[1]: COMMA_DOUBLE	GTX[1]: DRP[47] bit 11 GTX[1]: TX_IDLE_ASSERT_DELAY bit 0
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[47] bit 8 GTX[1]: COMMA_10B_ENABLE bit 8	GTX[1]: DRP[47] bit 9 GTX[1]: COMMA_10B_ENABLE bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[47] bit 6 GTX[1]: COMMA_10B_ENABLE bit 6	GTX[1]: DRP[47] bit 7 GTX[1]: COMMA_10B_ENABLE bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[47] bit 4 GTX[1]: COMMA_10B_ENABLE bit 4	GTX[1]: DRP[47] bit 5 GTX[1]: COMMA_10B_ENABLE bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[47] bit 2 GTX[1]: COMMA_10B_ENABLE bit 2	GTX[1]: DRP[47] bit 3 GTX[1]: COMMA_10B_ENABLE bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[47] bit 0 GTX[1]: COMMA_10B_ENABLE bit 0	GTX[1]: DRP[47] bit 1 GTX[1]: COMMA_10B_ENABLE bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[46] bit 14 GTX[1]: DFE_CAL_TIME bit 3	GTX[1]: DRP[46] bit 15 GTX[1]: DFE_CAL_TIME bit 4
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[46] bit 12 GTX[1]: DFE_CAL_TIME bit 1	GTX[1]: DRP[46] bit 13 GTX[1]: DFE_CAL_TIME bit 2
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[46] bit 10 GTX[1]: RX_EYE_SCANMODE bit 1	GTX[1]: DRP[46] bit 11 GTX[1]: DFE_CAL_TIME bit 0
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[46] bit 8 GTX[1]: RCV_TERM_VTTRX	GTX[1]: DRP[46] bit 9 GTX[1]: RX_EYE_SCANMODE bit 0
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[46] bit 6 GTX[1]: TERMINATION_OVRD	GTX[1]: DRP[46] bit 7 GTX[1]: RCV_TERM_GND
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[46] bit 4 GTX[1]: TERMINATION_CTRL bit 4	GTX[1]: DRP[46] bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[46] bit 2 GTX[1]: TERMINATION_CTRL bit 2	GTX[1]: DRP[46] bit 3 GTX[1]: TERMINATION_CTRL bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[46] bit 0 GTX[1]: TERMINATION_CTRL bit 0	GTX[1]: DRP[46] bit 1 GTX[1]: TERMINATION_CTRL bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[45] bit 14 GTX[1]: RX_EYE_OFFSET bit 6	GTX[1]: DRP[45] bit 15 GTX[1]: RX_EYE_OFFSET bit 7
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[45] bit 12 GTX[1]: RX_EYE_OFFSET bit 4	GTX[1]: DRP[45] bit 13 GTX[1]: RX_EYE_OFFSET bit 5
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[45] bit 10 GTX[1]: RX_EYE_OFFSET bit 2	GTX[1]: DRP[45] bit 11 GTX[1]: RX_EYE_OFFSET bit 3
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[45] bit 8 GTX[1]: RX_EYE_OFFSET bit 0	GTX[1]: DRP[45] bit 9 GTX[1]: RX_EYE_OFFSET bit 1
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[45] bit 6 GTX[1]: DFE_CFG bit 6	GTX[1]: DRP[45] bit 7 GTX[1]: DFE_CFG bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[45] bit 4 GTX[1]: DFE_CFG bit 4	GTX[1]: DRP[45] bit 5 GTX[1]: DFE_CFG bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[45] bit 2 GTX[1]: DFE_CFG bit 2	GTX[1]: DRP[45] bit 3 GTX[1]: DFE_CFG bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[45] bit 0 GTX[1]: DFE_CFG bit 0	GTX[1]: DRP[45] bit 1 GTX[1]: DFE_CFG bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[44] bit 14 GTX[1]: A_DFECLKDLYADJ bit 5	GTX[1]: DRP[44] bit 15 GTX[1]: DFE_DRP_EN
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[44] bit 12 GTX[1]: A_DFECLKDLYADJ bit 3	GTX[1]: DRP[44] bit 13 GTX[1]: A_DFECLKDLYADJ bit 4
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[44] bit 10 GTX[1]: A_DFECLKDLYADJ bit 1	GTX[1]: DRP[44] bit 11 GTX[1]: A_DFECLKDLYADJ bit 2
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[44] bit 8 GTX[1]: A_DFETAP4 bit 3	GTX[1]: DRP[44] bit 9 GTX[1]: A_DFECLKDLYADJ bit 0
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[44] bit 6 GTX[1]: A_DFETAP4 bit 1	GTX[1]: DRP[44] bit 7 GTX[1]: A_DFETAP4 bit 2
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[44] bit 4 GTX[1]: A_DFETAP2 bit 4	GTX[1]: DRP[44] bit 5 GTX[1]: A_DFETAP4 bit 0
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[44] bit 2 GTX[1]: A_DFETAP2 bit 2	GTX[1]: DRP[44] bit 3 GTX[1]: A_DFETAP2 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[44] bit 0 GTX[1]: A_DFETAP2 bit 0	GTX[1]: DRP[44] bit 1 GTX[1]: A_DFETAP2 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[43] bit 14 GTX[1]: A_DFEDLYOVRD bit 0	GTX[1]: DRP[43] bit 15 GTX[1]: A_DFETAPOVRD bit 0
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTCLK[0]: CLKRCV_TRST GTX[1]: DRP[43] bit 12	GTCLK[1]: CLKRCV_TRST GTX[1]: DRP[43] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[43] bit 10 GTX[1]: RX_EN_IDLE_RESET_FR	GTX[1]: DRP[43] bit 11 GTX[1]: RX_EN_IDLE_HOLD_DFE
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[43] bit 8 GTX[1]: A_DFETAP3 bit 3	GTX[1]: DRP[43] bit 9 GTX[1]: RX_EN_IDLE_HOLD_CDR
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[43] bit 6 GTX[1]: A_DFETAP3 bit 1	GTX[1]: DRP[43] bit 7 GTX[1]: A_DFETAP3 bit 2
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[43] bit 4 GTX[1]: A_DFETAP1 bit 4	GTX[1]: DRP[43] bit 5 GTX[1]: A_DFETAP3 bit 0
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[43] bit 2 GTX[1]: A_DFETAP1 bit 2	GTX[1]: DRP[43] bit 3 GTX[1]: A_DFETAP1 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[43] bit 0 GTX[1]: A_DFETAP1 bit 0	GTX[1]: DRP[43] bit 1 GTX[1]: A_DFETAP1 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[42] bit 14 GTX[1]: A_PRBSCNTRESET bit 0	GTX[1]: DRP[42] bit 15 GTX[1]: PRBS_DRP_EN
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[42] bit 12 GTX[1]: A_TXENPRBSTST bit 1	GTX[1]: DRP[42] bit 13 GTX[1]: A_TXENPRBSTST bit 2
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[42] bit 10 GTX[1]: A_TXPRBSFORCEERR bit 0	GTX[1]: DRP[42] bit 11 GTX[1]: A_TXENPRBSTST bit 0
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[42] bit 8 GTX[1]: RXPRBSERR_LOOPBACK bit 0	GTX[1]: DRP[42] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[42] bit 6 GTX[1]: A_RXENPRBSTST bit 1	GTX[1]: DRP[42] bit 7 GTX[1]: A_RXENPRBSTST bit 2
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[42] bit 4	GTX[1]: DRP[42] bit 5 GTX[1]: A_RXENPRBSTST bit 0
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[42] bit 2 GTX[1]: A_LOOPBACK bit 1	GTX[1]: DRP[42] bit 3 GTX[1]: A_LOOPBACK bit 2
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[42] bit 0 GTX[1]: LOOPBACK_DRP_EN	GTX[1]: DRP[42] bit 1 GTX[1]: A_LOOPBACK bit 0
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[41] bit 14 GTX[1]: A_RXENSAMPLEALIGN bit 0	GTX[1]: DRP[41] bit 15 GTX[1]: PHASEALIGN_DRP_EN
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[41] bit 12 GTX[1]: A_TXPMASETPHASE bit 0	GTX[1]: DRP[41] bit 13 GTX[1]: A_TXENPMAPHASEALIGN bit 0
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[41] bit 10 GTX[1]: SAS_MIN_COMSAS bit 4	GTX[1]: DRP[41] bit 11 GTX[1]: SAS_MIN_COMSAS bit 5
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[41] bit 8 GTX[1]: SAS_MIN_COMSAS bit 2	GTX[1]: DRP[41] bit 9 GTX[1]: SAS_MIN_COMSAS bit 3
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[41] bit 6 GTX[1]: SAS_MIN_COMSAS bit 0	GTX[1]: DRP[41] bit 7 GTX[1]: SAS_MIN_COMSAS bit 1
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[41] bit 4 GTX[1]: SAS_MAX_COMSAS bit 4	GTX[1]: DRP[41] bit 5 GTX[1]: SAS_MAX_COMSAS bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[41] bit 2 GTX[1]: SAS_MAX_COMSAS bit 2	GTX[1]: DRP[41] bit 3 GTX[1]: SAS_MAX_COMSAS bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[41] bit 0 GTX[1]: SAS_MAX_COMSAS bit 0	GTX[1]: DRP[41] bit 1 GTX[1]: SAS_MAX_COMSAS bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[40] bit 14 GTX[1]: SATA_BURST_VAL bit 2	GTX[1]: DRP[40] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[40] bit 12 GTX[1]: SATA_BURST_VAL bit 0	GTX[1]: DRP[40] bit 13 GTX[1]: SATA_BURST_VAL bit 1
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[40] bit 10 GTX[1]: SATA_MIN_BURST bit 4	GTX[1]: DRP[40] bit 11 GTX[1]: SATA_MIN_BURST bit 5
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[40] bit 8 GTX[1]: SATA_MIN_BURST bit 2	GTX[1]: DRP[40] bit 9 GTX[1]: SATA_MIN_BURST bit 3
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[40] bit 6 GTX[1]: SATA_MIN_BURST bit 0	GTX[1]: DRP[40] bit 7 GTX[1]: SATA_MIN_BURST bit 1
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[40] bit 4 GTX[1]: SATA_MAX_BURST bit 4	GTX[1]: DRP[40] bit 5 GTX[1]: SATA_MAX_BURST bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[40] bit 2 GTX[1]: SATA_MAX_BURST bit 2	GTX[1]: DRP[40] bit 3 GTX[1]: SATA_MAX_BURST bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[40] bit 0 GTX[1]: SATA_MAX_BURST bit 0	GTX[1]: DRP[40] bit 1 GTX[1]: SATA_MAX_BURST bit 1

virtex6 GTX rect MAIN[16]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[55] bit 14 GTX[1]: PMA_TX_CFG bit 14	GTX[1]: DRP[55] bit 15 GTX[1]: PMA_TX_CFG bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[55] bit 12 GTX[1]: PMA_TX_CFG bit 12	GTX[1]: DRP[55] bit 13 GTX[1]: PMA_TX_CFG bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[55] bit 10 GTX[1]: PMA_TX_CFG bit 10	GTX[1]: DRP[55] bit 11 GTX[1]: PMA_TX_CFG bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[55] bit 8 GTX[1]: PMA_TX_CFG bit 8	GTX[1]: DRP[55] bit 9 GTX[1]: PMA_TX_CFG bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[55] bit 6 GTX[1]: PMA_TX_CFG bit 6	GTX[1]: DRP[55] bit 7 GTX[1]: PMA_TX_CFG bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[55] bit 4 GTX[1]: PMA_TX_CFG bit 4	GTX[1]: DRP[55] bit 5 GTX[1]: PMA_TX_CFG bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[55] bit 2 GTX[1]: PMA_TX_CFG bit 2	GTX[1]: DRP[55] bit 3 GTX[1]: PMA_TX_CFG bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[55] bit 0 GTX[1]: PMA_TX_CFG bit 0	GTX[1]: DRP[55] bit 1 GTX[1]: PMA_TX_CFG bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[54] bit 14 GTX[1]: PMA_CFG bit 74	GTX[1]: DRP[54] bit 15 GTX[1]: PMA_CFG bit 75
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[54] bit 12 GTX[1]: PMA_CFG bit 72	GTX[1]: DRP[54] bit 13 GTX[1]: PMA_CFG bit 73
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[54] bit 10 GTX[1]: PMA_CFG bit 70	GTX[1]: DRP[54] bit 11 GTX[1]: PMA_CFG bit 71
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[54] bit 8 GTX[1]: PMA_CFG bit 68	GTX[1]: DRP[54] bit 9 GTX[1]: PMA_CFG bit 69
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[54] bit 6 GTX[1]: PMA_CFG bit 66	GTX[1]: DRP[54] bit 7 GTX[1]: PMA_CFG bit 67
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[54] bit 4 GTX[1]: PMA_CFG bit 64	GTX[1]: DRP[54] bit 5 GTX[1]: PMA_CFG bit 65
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[54] bit 2 GTX[1]: PMA_TX_CFG bit 18	GTX[1]: DRP[54] bit 3 GTX[1]: PMA_TX_CFG bit 19
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[54] bit 0 GTX[1]: PMA_TX_CFG bit 16	GTX[1]: DRP[54] bit 1 GTX[1]: PMA_TX_CFG bit 17
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[53] bit 14 GTX[1]: PMA_CFG bit 62	GTX[1]: DRP[53] bit 15 GTX[1]: PMA_CFG bit 63
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[53] bit 12 GTX[1]: PMA_CFG bit 60	GTX[1]: DRP[53] bit 13 GTX[1]: PMA_CFG bit 61
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[53] bit 10 GTX[1]: PMA_CFG bit 58	GTX[1]: DRP[53] bit 11 GTX[1]: PMA_CFG bit 59
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[53] bit 8 GTX[1]: PMA_CFG bit 56	GTX[1]: DRP[53] bit 9 GTX[1]: PMA_CFG bit 57
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[53] bit 6 GTX[1]: PMA_CFG bit 54	GTX[1]: DRP[53] bit 7 GTX[1]: PMA_CFG bit 55
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[53] bit 4 GTX[1]: PMA_CFG bit 52	GTX[1]: DRP[53] bit 5 GTX[1]: PMA_CFG bit 53
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[53] bit 2 GTX[1]: PMA_CFG bit 50	GTX[1]: DRP[53] bit 3 GTX[1]: PMA_CFG bit 51
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[53] bit 0 GTX[1]: PMA_CFG bit 48	GTX[1]: DRP[53] bit 1 GTX[1]: PMA_CFG bit 49
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[52] bit 14 GTX[1]: PMA_CFG bit 46	GTX[1]: DRP[52] bit 15 GTX[1]: PMA_CFG bit 47
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[52] bit 12 GTX[1]: PMA_CFG bit 44	GTX[1]: DRP[52] bit 13 GTX[1]: PMA_CFG bit 45
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[52] bit 10 GTX[1]: PMA_CFG bit 42	GTX[1]: DRP[52] bit 11 GTX[1]: PMA_CFG bit 43
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[52] bit 8 GTX[1]: PMA_CFG bit 40	GTX[1]: DRP[52] bit 9 GTX[1]: PMA_CFG bit 41
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[52] bit 6 GTX[1]: PMA_CFG bit 38	GTX[1]: DRP[52] bit 7 GTX[1]: PMA_CFG bit 39
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[52] bit 4 GTX[1]: PMA_CFG bit 36	GTX[1]: DRP[52] bit 5 GTX[1]: PMA_CFG bit 37
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[52] bit 2 GTX[1]: PMA_CFG bit 34	GTX[1]: DRP[52] bit 3 GTX[1]: PMA_CFG bit 35
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[52] bit 0 GTX[1]: PMA_CFG bit 32	GTX[1]: DRP[52] bit 1 GTX[1]: PMA_CFG bit 33
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[51] bit 14 GTX[1]: PMA_CFG bit 30	GTX[1]: DRP[51] bit 15 GTX[1]: PMA_CFG bit 31
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[51] bit 12 GTX[1]: PMA_CFG bit 28	GTX[1]: DRP[51] bit 13 GTX[1]: PMA_CFG bit 29
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[51] bit 10 GTX[1]: PMA_CFG bit 26	GTX[1]: DRP[51] bit 11 GTX[1]: PMA_CFG bit 27
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[51] bit 8 GTX[1]: PMA_CFG bit 24	GTX[1]: DRP[51] bit 9 GTX[1]: PMA_CFG bit 25
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[51] bit 6 GTX[1]: PMA_CFG bit 22	GTX[1]: DRP[51] bit 7 GTX[1]: PMA_CFG bit 23
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[51] bit 4 GTX[1]: PMA_CFG bit 20	GTX[1]: DRP[51] bit 5 GTX[1]: PMA_CFG bit 21
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[51] bit 2 GTX[1]: PMA_CFG bit 18	GTX[1]: DRP[51] bit 3 GTX[1]: PMA_CFG bit 19
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[51] bit 0 GTX[1]: PMA_CFG bit 16	GTX[1]: DRP[51] bit 1 GTX[1]: PMA_CFG bit 17
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[50] bit 14 GTX[1]: PMA_CFG bit 14	GTX[1]: DRP[50] bit 15 GTX[1]: PMA_CFG bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[50] bit 12 GTX[1]: PMA_CFG bit 12	GTX[1]: DRP[50] bit 13 GTX[1]: PMA_CFG bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[50] bit 10 GTX[1]: PMA_CFG bit 10	GTX[1]: DRP[50] bit 11 GTX[1]: PMA_CFG bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[50] bit 8 GTX[1]: PMA_CFG bit 8	GTX[1]: DRP[50] bit 9 GTX[1]: PMA_CFG bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[50] bit 6 GTX[1]: PMA_CFG bit 6	GTX[1]: DRP[50] bit 7 GTX[1]: PMA_CFG bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[50] bit 4 GTX[1]: PMA_CFG bit 4	GTX[1]: DRP[50] bit 5 GTX[1]: PMA_CFG bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[50] bit 2 GTX[1]: PMA_CFG bit 2	GTX[1]: DRP[50] bit 3 GTX[1]: PMA_CFG bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[50] bit 0 GTX[1]: PMA_CFG bit 0	GTX[1]: DRP[50] bit 1 GTX[1]: PMA_CFG bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[49] bit 14 GTX[1]: TX_DATA_WIDTH bit 2	GTX[1]: DRP[49] bit 15 GTX[1]: GEN_TXUSRCLK
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[49] bit 12 GTX[1]: TX_DATA_WIDTH bit 0	GTX[1]: DRP[49] bit 13 GTX[1]: TX_DATA_WIDTH bit 1
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[49] bit 10 GTX[1]: PCOMMA_DETECT	GTX[1]: DRP[49] bit 11 GTX[1]: TX_BUFFER_USE
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[49] bit 8 GTX[1]: PCOMMA_10B_VALUE bit 8	GTX[1]: DRP[49] bit 9 GTX[1]: PCOMMA_10B_VALUE bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[49] bit 6 GTX[1]: PCOMMA_10B_VALUE bit 6	GTX[1]: DRP[49] bit 7 GTX[1]: PCOMMA_10B_VALUE bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[49] bit 4 GTX[1]: PCOMMA_10B_VALUE bit 4	GTX[1]: DRP[49] bit 5 GTX[1]: PCOMMA_10B_VALUE bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[49] bit 2 GTX[1]: PCOMMA_10B_VALUE bit 2	GTX[1]: DRP[49] bit 3 GTX[1]: PCOMMA_10B_VALUE bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[49] bit 0 GTX[1]: PCOMMA_10B_VALUE bit 0	GTX[1]: DRP[49] bit 1 GTX[1]: PCOMMA_10B_VALUE bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: !invert TXUSRCLK GTX[1]: DRP[48] bit 14	GTX[1]: !invert TXUSRCLK2 GTX[1]: DRP[48] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[48] bit 12 GTX[1]: TX_IDLE_DEASSERT_DELAY bit 1	GTX[1]: DRP[48] bit 13 GTX[1]: TX_IDLE_DEASSERT_DELAY bit 2
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[48] bit 10 GTX[1]: MCOMMA_DETECT	GTX[1]: DRP[48] bit 11 GTX[1]: TX_IDLE_DEASSERT_DELAY bit 0
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[48] bit 8 GTX[1]: MCOMMA_10B_VALUE bit 8	GTX[1]: DRP[48] bit 9 GTX[1]: MCOMMA_10B_VALUE bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[48] bit 6 GTX[1]: MCOMMA_10B_VALUE bit 6	GTX[1]: DRP[48] bit 7 GTX[1]: MCOMMA_10B_VALUE bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[48] bit 4 GTX[1]: MCOMMA_10B_VALUE bit 4	GTX[1]: DRP[48] bit 5 GTX[1]: MCOMMA_10B_VALUE bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[48] bit 2 GTX[1]: MCOMMA_10B_VALUE bit 2	GTX[1]: DRP[48] bit 3 GTX[1]: MCOMMA_10B_VALUE bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[48] bit 0 GTX[1]: MCOMMA_10B_VALUE bit 0	GTX[1]: DRP[48] bit 1 GTX[1]: MCOMMA_10B_VALUE bit 1

virtex6 GTX rect MAIN[17]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[63] bit 14	GTX[1]: DRP[63] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[63] bit 12	GTX[1]: DRP[63] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[63] bit 10	GTX[1]: DRP[63] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[63] bit 8	GTX[1]: DRP[63] bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[63] bit 6 GTX[1]: TRANS_TIME_RATE bit 6	GTX[1]: DRP[63] bit 7 GTX[1]: TRANS_TIME_RATE bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[63] bit 4 GTX[1]: TRANS_TIME_RATE bit 4	GTX[1]: DRP[63] bit 5 GTX[1]: TRANS_TIME_RATE bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[63] bit 2 GTX[1]: TRANS_TIME_RATE bit 2	GTX[1]: DRP[63] bit 3 GTX[1]: TRANS_TIME_RATE bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[63] bit 0 GTX[1]: TRANS_TIME_RATE bit 0	GTX[1]: DRP[63] bit 1 GTX[1]: TRANS_TIME_RATE bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[62] bit 14 GTX[1]: A_TXMARGIN bit 1	GTX[1]: DRP[62] bit 15 GTX[1]: A_TXMARGIN bit 2
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[62] bit 12	GTX[1]: DRP[62] bit 13 GTX[1]: A_TXMARGIN bit 0
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[62] bit 10	GTX[1]: DRP[62] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[62] bit 8 GTX[1]: TX_DEEMPH_1 bit 3	GTX[1]: DRP[62] bit 9 GTX[1]: TX_DEEMPH_1 bit 4
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[62] bit 6 GTX[1]: TX_DEEMPH_1 bit 1	GTX[1]: DRP[62] bit 7 GTX[1]: TX_DEEMPH_1 bit 2
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[62] bit 4 GTX[1]: TX_DEEMPH_0 bit 4	GTX[1]: DRP[62] bit 5 GTX[1]: TX_DEEMPH_1 bit 0
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[62] bit 2 GTX[1]: TX_DEEMPH_0 bit 2	GTX[1]: DRP[62] bit 3 GTX[1]: TX_DEEMPH_0 bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[62] bit 0 GTX[1]: TX_DEEMPH_0 bit 0	GTX[1]: DRP[62] bit 1 GTX[1]: TX_DEEMPH_0 bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[61] bit 14 GTX[1]: A_TXPOSTEMPHASIS bit 3	GTX[1]: DRP[61] bit 15 GTX[1]: A_TXPOSTEMPHASIS bit 4
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[61] bit 12 GTX[1]: A_TXPOSTEMPHASIS bit 1	GTX[1]: DRP[61] bit 13 GTX[1]: A_TXPOSTEMPHASIS bit 2
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[61] bit 10 GTX[1]: A_TXPREEMPHASIS bit 3	GTX[1]: DRP[61] bit 11 GTX[1]: A_TXPOSTEMPHASIS bit 0
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[61] bit 8 GTX[1]: A_TXPREEMPHASIS bit 1	GTX[1]: DRP[61] bit 9 GTX[1]: A_TXPREEMPHASIS bit 2
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[61] bit 6 GTX[1]: A_TXBUFDIFFCTRL bit 2	GTX[1]: DRP[61] bit 7 GTX[1]: A_TXPREEMPHASIS bit 0
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[61] bit 4 GTX[1]: A_TXBUFDIFFCTRL bit 0	GTX[1]: DRP[61] bit 5 GTX[1]: A_TXBUFDIFFCTRL bit 1
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[61] bit 2 GTX[1]: A_TXDIFFCTRL bit 2	GTX[1]: DRP[61] bit 3 GTX[1]: A_TXDIFFCTRL bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[61] bit 0 GTX[1]: A_TXDIFFCTRL bit 0	GTX[1]: DRP[61] bit 1 GTX[1]: A_TXDIFFCTRL bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[60] bit 14 GTX[1]: TXDRIVE_DRP_EN	GTX[1]: DRP[60] bit 15 GTX[1]: TX_DRIVE_MODE bit 0
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[60] bit 12 GTX[1]: TX_MARGIN_FULL_4 bit 5	GTX[1]: DRP[60] bit 13 GTX[1]: TX_MARGIN_FULL_4 bit 6
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[60] bit 10 GTX[1]: TX_MARGIN_FULL_4 bit 3	GTX[1]: DRP[60] bit 11 GTX[1]: TX_MARGIN_FULL_4 bit 4
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[60] bit 8 GTX[1]: TX_MARGIN_FULL_4 bit 1	GTX[1]: DRP[60] bit 9 GTX[1]: TX_MARGIN_FULL_4 bit 2
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[60] bit 6 GTX[1]: TX_MARGIN_LOW_4 bit 6	GTX[1]: DRP[60] bit 7 GTX[1]: TX_MARGIN_FULL_4 bit 0
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[60] bit 4 GTX[1]: TX_MARGIN_LOW_4 bit 4	GTX[1]: DRP[60] bit 5 GTX[1]: TX_MARGIN_LOW_4 bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[60] bit 2 GTX[1]: TX_MARGIN_LOW_4 bit 2	GTX[1]: DRP[60] bit 3 GTX[1]: TX_MARGIN_LOW_4 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[60] bit 0 GTX[1]: TX_MARGIN_LOW_4 bit 0	GTX[1]: DRP[60] bit 1 GTX[1]: TX_MARGIN_LOW_4 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[59] bit 14 GTX[1]: A_TXSWING bit 0	GTX[1]: DRP[59] bit 15 GTX[1]: A_TXDEEMPH bit 0
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[59] bit 12 GTX[1]: TX_MARGIN_FULL_3 bit 5	GTX[1]: DRP[59] bit 13 GTX[1]: TX_MARGIN_FULL_3 bit 6
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[59] bit 10 GTX[1]: TX_MARGIN_FULL_3 bit 3	GTX[1]: DRP[59] bit 11 GTX[1]: TX_MARGIN_FULL_3 bit 4
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[59] bit 8 GTX[1]: TX_MARGIN_FULL_3 bit 1	GTX[1]: DRP[59] bit 9 GTX[1]: TX_MARGIN_FULL_3 bit 2
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[59] bit 6 GTX[1]: TX_MARGIN_LOW_3 bit 6	GTX[1]: DRP[59] bit 7 GTX[1]: TX_MARGIN_FULL_3 bit 0
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[59] bit 4 GTX[1]: TX_MARGIN_LOW_3 bit 4	GTX[1]: DRP[59] bit 5 GTX[1]: TX_MARGIN_LOW_3 bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[59] bit 2 GTX[1]: TX_MARGIN_LOW_3 bit 2	GTX[1]: DRP[59] bit 3 GTX[1]: TX_MARGIN_LOW_3 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[59] bit 0 GTX[1]: TX_MARGIN_LOW_3 bit 0	GTX[1]: DRP[59] bit 1 GTX[1]: TX_MARGIN_LOW_3 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[58] bit 14 GTX[1]: ! TXDRIVE_LOOPBACK_HIZ	GTX[1]: DRP[58] bit 15 GTX[1]: ! TXDRIVE_LOOPBACK_PD
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[58] bit 12 GTX[1]: TX_MARGIN_FULL_2 bit 5	GTX[1]: DRP[58] bit 13 GTX[1]: TX_MARGIN_FULL_2 bit 6
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[58] bit 10 GTX[1]: TX_MARGIN_FULL_2 bit 3	GTX[1]: DRP[58] bit 11 GTX[1]: TX_MARGIN_FULL_2 bit 4
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[58] bit 8 GTX[1]: TX_MARGIN_FULL_2 bit 1	GTX[1]: DRP[58] bit 9 GTX[1]: TX_MARGIN_FULL_2 bit 2
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[58] bit 6 GTX[1]: TX_MARGIN_LOW_2 bit 6	GTX[1]: DRP[58] bit 7 GTX[1]: TX_MARGIN_FULL_2 bit 0
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[58] bit 4 GTX[1]: TX_MARGIN_LOW_2 bit 4	GTX[1]: DRP[58] bit 5 GTX[1]: TX_MARGIN_LOW_2 bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[58] bit 2 GTX[1]: TX_MARGIN_LOW_2 bit 2	GTX[1]: DRP[58] bit 3 GTX[1]: TX_MARGIN_LOW_2 bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[58] bit 0 GTX[1]: TX_MARGIN_LOW_2 bit 0	GTX[1]: DRP[58] bit 1 GTX[1]: TX_MARGIN_LOW_2 bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[57] bit 14 GTX[1]: TX_TDCC_CFG bit 0	GTX[1]: DRP[57] bit 15 GTX[1]: TX_TDCC_CFG bit 1
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[57] bit 12 GTX[1]: TX_MARGIN_FULL_1 bit 5	GTX[1]: DRP[57] bit 13 GTX[1]: TX_MARGIN_FULL_1 bit 6
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[57] bit 10 GTX[1]: TX_MARGIN_FULL_1 bit 3	GTX[1]: DRP[57] bit 11 GTX[1]: TX_MARGIN_FULL_1 bit 4
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[57] bit 8 GTX[1]: TX_MARGIN_FULL_1 bit 1	GTX[1]: DRP[57] bit 9 GTX[1]: TX_MARGIN_FULL_1 bit 2
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[57] bit 6 GTX[1]: TX_MARGIN_LOW_1 bit 6	GTX[1]: DRP[57] bit 7 GTX[1]: TX_MARGIN_FULL_1 bit 0
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[57] bit 4 GTX[1]: TX_MARGIN_LOW_1 bit 4	GTX[1]: DRP[57] bit 5 GTX[1]: TX_MARGIN_LOW_1 bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[57] bit 2 GTX[1]: TX_MARGIN_LOW_1 bit 2	GTX[1]: DRP[57] bit 3 GTX[1]: TX_MARGIN_LOW_1 bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[57] bit 0 GTX[1]: TX_MARGIN_LOW_1 bit 0	GTX[1]: DRP[57] bit 1 GTX[1]: TX_MARGIN_LOW_1 bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[56] bit 14 GTX[1]: TXOUTCLKPCS_SEL bit 0	GTX[1]: !invert DCLK GTX[1]: DRP[56] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[56] bit 12 GTX[1]: TX_MARGIN_FULL_0 bit 5	GTX[1]: DRP[56] bit 13 GTX[1]: TX_MARGIN_FULL_0 bit 6
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[56] bit 10 GTX[1]: TX_MARGIN_FULL_0 bit 3	GTX[1]: DRP[56] bit 11 GTX[1]: TX_MARGIN_FULL_0 bit 4
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[56] bit 8 GTX[1]: TX_MARGIN_FULL_0 bit 1	GTX[1]: DRP[56] bit 9 GTX[1]: TX_MARGIN_FULL_0 bit 2
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[56] bit 6 GTX[1]: TX_MARGIN_LOW_0 bit 6	GTX[1]: DRP[56] bit 7 GTX[1]: TX_MARGIN_FULL_0 bit 0
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[56] bit 4 GTX[1]: TX_MARGIN_LOW_0 bit 4	GTX[1]: DRP[56] bit 5 GTX[1]: TX_MARGIN_LOW_0 bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[56] bit 2 GTX[1]: TX_MARGIN_LOW_0 bit 2	GTX[1]: DRP[56] bit 3 GTX[1]: TX_MARGIN_LOW_0 bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[56] bit 0 GTX[1]: TX_MARGIN_LOW_0 bit 0	GTX[1]: DRP[56] bit 1 GTX[1]: TX_MARGIN_LOW_0 bit 1

virtex6 GTX rect MAIN[18]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[71] bit 14	GTX[1]: DRP[71] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[71] bit 12	GTX[1]: DRP[71] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[71] bit 10	GTX[1]: DRP[71] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[71] bit 8 GTX[1]: TXOUTCLK_DLY bit 8	GTX[1]: DRP[71] bit 9 GTX[1]: TXOUTCLK_DLY bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[71] bit 6 GTX[1]: TXOUTCLK_DLY bit 6	GTX[1]: DRP[71] bit 7 GTX[1]: TXOUTCLK_DLY bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[71] bit 4 GTX[1]: TXOUTCLK_DLY bit 4	GTX[1]: DRP[71] bit 5 GTX[1]: TXOUTCLK_DLY bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[71] bit 2 GTX[1]: TXOUTCLK_DLY bit 2	GTX[1]: DRP[71] bit 3 GTX[1]: TXOUTCLK_DLY bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[71] bit 0 GTX[1]: TXOUTCLK_DLY bit 0	GTX[1]: DRP[71] bit 1 GTX[1]: TXOUTCLK_DLY bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[70] bit 14	GTX[1]: DRP[70] bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[70] bit 12	GTX[1]: DRP[70] bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[70] bit 10	GTX[1]: DRP[70] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[70] bit 8 GTX[1]: RXRECCLK_DLY bit 8	GTX[1]: DRP[70] bit 9 GTX[1]: RXRECCLK_DLY bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[70] bit 6 GTX[1]: RXRECCLK_DLY bit 6	GTX[1]: DRP[70] bit 7 GTX[1]: RXRECCLK_DLY bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[70] bit 4 GTX[1]: RXRECCLK_DLY bit 4	GTX[1]: DRP[70] bit 5 GTX[1]: RXRECCLK_DLY bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[70] bit 2 GTX[1]: RXRECCLK_DLY bit 2	GTX[1]: DRP[70] bit 3 GTX[1]: RXRECCLK_DLY bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[70] bit 0 GTX[1]: RXRECCLK_DLY bit 0	GTX[1]: DRP[70] bit 1 GTX[1]: RXRECCLK_DLY bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[69] bit 14	GTX[1]: DRP[69] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[69] bit 12	GTX[1]: DRP[69] bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[69] bit 10 GTX[1]: TX_USRCLK_CFG bit 4	GTX[1]: DRP[69] bit 11 GTX[1]: TX_USRCLK_CFG bit 5
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[69] bit 8 GTX[1]: TX_USRCLK_CFG bit 2	GTX[1]: DRP[69] bit 9 GTX[1]: TX_USRCLK_CFG bit 3
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[69] bit 6 GTX[1]: TX_USRCLK_CFG bit 0	GTX[1]: DRP[69] bit 7 GTX[1]: TX_USRCLK_CFG bit 1
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[69] bit 4 GTX[1]: TX_BYTECLK_CFG bit 4	GTX[1]: DRP[69] bit 5 GTX[1]: TX_BYTECLK_CFG bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[69] bit 2 GTX[1]: TX_BYTECLK_CFG bit 2	GTX[1]: DRP[69] bit 3 GTX[1]: TX_BYTECLK_CFG bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[69] bit 0 GTX[1]: TX_BYTECLK_CFG bit 0	GTX[1]: DRP[69] bit 1 GTX[1]: TX_BYTECLK_CFG bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[68] bit 14	GTX[1]: DRP[68] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[68] bit 12	GTX[1]: DRP[68] bit 13
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[68] bit 10	GTX[1]: DRP[68] bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[68] bit 8 GTX[1]: POWER_SAVE bit 8	GTX[1]: DRP[68] bit 9 GTX[1]: POWER_SAVE bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[68] bit 6 GTX[1]: POWER_SAVE bit 6	GTX[1]: DRP[68] bit 7 GTX[1]: POWER_SAVE bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[68] bit 4 GTX[1]: POWER_SAVE bit 4	GTX[1]: DRP[68] bit 5 GTX[1]: POWER_SAVE bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[68] bit 2 GTX[1]: POWER_SAVE bit 2	GTX[1]: DRP[68] bit 3 GTX[1]: POWER_SAVE bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[68] bit 0 GTX[1]: POWER_SAVE bit 0	GTX[1]: DRP[68] bit 1 GTX[1]: POWER_SAVE bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: !invert GREFCLKTX GTX[1]: DRP[67] bit 14	GTX[1]: !invert GREFCLKRX GTX[1]: DRP[67] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[67] bit 12	GTX[1]: !invert SCANCLK GTX[1]: DRP[67] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: !invert TSTCLK[0] GTX[1]: DRP[67] bit 10	GTX[1]: !invert TSTCLK[1] GTX[1]: DRP[67] bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTCLK[1]: MUX_CLKOUT bit 1 GTX[1]: DRP[67] bit 8	GTCLK[1]: MUX_CLKOUT bit 0 GTX[1]: DRP[67] bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTCLK[0]: MUX_CLKOUT bit 1 GTX[1]: DRP[67] bit 6	GTCLK[0]: MUX_CLKOUT bit 0 GTX[1]: DRP[67] bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[67] bit 4 GTX[1]: RXRECCLK_CTRL bit 1	GTX[1]: DRP[67] bit 5 GTX[1]: RXRECCLK_CTRL bit 2
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[67] bit 2 GTX[1]: TXOUTCLK_CTRL bit 2	GTX[1]: DRP[67] bit 3 GTX[1]: RXRECCLK_CTRL bit 0
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[67] bit 0 GTX[1]: TXOUTCLK_CTRL bit 0	GTX[1]: DRP[67] bit 1 GTX[1]: TXOUTCLK_CTRL bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[66] bit 14 GTX[1]: TST_ATTR bit 14	GTX[1]: DRP[66] bit 15 GTX[1]: TST_ATTR bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[66] bit 12 GTX[1]: TST_ATTR bit 12	GTX[1]: DRP[66] bit 13 GTX[1]: TST_ATTR bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[66] bit 10 GTX[1]: TST_ATTR bit 10	GTX[1]: DRP[66] bit 11 GTX[1]: TST_ATTR bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[66] bit 8 GTX[1]: TST_ATTR bit 8	GTX[1]: DRP[66] bit 9 GTX[1]: TST_ATTR bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[66] bit 6 GTX[1]: TST_ATTR bit 6	GTX[1]: DRP[66] bit 7 GTX[1]: TST_ATTR bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[66] bit 4 GTX[1]: TST_ATTR bit 4	GTX[1]: DRP[66] bit 5 GTX[1]: TST_ATTR bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[66] bit 2 GTX[1]: TST_ATTR bit 2	GTX[1]: DRP[66] bit 3 GTX[1]: TST_ATTR bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[66] bit 0 GTX[1]: TST_ATTR bit 0	GTX[1]: DRP[66] bit 1 GTX[1]: TST_ATTR bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[65] bit 14 GTX[1]: TST_ATTR bit 30	GTX[1]: DRP[65] bit 15 GTX[1]: TST_ATTR bit 31
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[65] bit 12 GTX[1]: TST_ATTR bit 28	GTX[1]: DRP[65] bit 13 GTX[1]: TST_ATTR bit 29
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[65] bit 10 GTX[1]: TST_ATTR bit 26	GTX[1]: DRP[65] bit 11 GTX[1]: TST_ATTR bit 27
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[65] bit 8 GTX[1]: TST_ATTR bit 24	GTX[1]: DRP[65] bit 9 GTX[1]: TST_ATTR bit 25
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[65] bit 6 GTX[1]: TST_ATTR bit 22	GTX[1]: DRP[65] bit 7 GTX[1]: TST_ATTR bit 23
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[65] bit 4 GTX[1]: TST_ATTR bit 20	GTX[1]: DRP[65] bit 5 GTX[1]: TST_ATTR bit 21
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[65] bit 2 GTX[1]: TST_ATTR bit 18	GTX[1]: DRP[65] bit 3 GTX[1]: TST_ATTR bit 19
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[65] bit 0 GTX[1]: TST_ATTR bit 16	GTX[1]: DRP[65] bit 1 GTX[1]: TST_ATTR bit 17
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[64] bit 14	GTX[1]: DRP[64] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[64] bit 12	GTX[1]: DRP[64] bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[64] bit 10	GTX[1]: DRP[64] bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[64] bit 8 GTX[1]: A_RXEQMIX bit 8	GTX[1]: DRP[64] bit 9 GTX[1]: A_RXEQMIX bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[64] bit 6 GTX[1]: A_RXEQMIX bit 6	GTX[1]: DRP[64] bit 7 GTX[1]: A_RXEQMIX bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[64] bit 4 GTX[1]: A_RXEQMIX bit 4	GTX[1]: DRP[64] bit 5 GTX[1]: A_RXEQMIX bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[64] bit 2 GTX[1]: A_RXEQMIX bit 2	GTX[1]: DRP[64] bit 3 GTX[1]: A_RXEQMIX bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[64] bit 0 GTX[1]: A_RXEQMIX bit 0	GTX[1]: DRP[64] bit 1 GTX[1]: A_RXEQMIX bit 1

virtex6 GTX rect MAIN[19]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[79] bit 14	GTX[1]: DRP[79] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[79] bit 12	GTX[1]: DRP[79] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[79] bit 10	GTX[1]: DRP[79] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[79] bit 8	GTX[1]: DRP[79] bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[79] bit 6	GTX[1]: DRP[79] bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[79] bit 4	GTX[1]: DRP[79] bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[79] bit 2	GTX[1]: DRP[79] bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[79] bit 0	GTX[1]: DRP[79] bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[78] bit 14	GTX[1]: DRP[78] bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[78] bit 12	GTX[1]: DRP[78] bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[78] bit 10	GTX[1]: DRP[78] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[78] bit 8	GTX[1]: DRP[78] bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[78] bit 6	GTX[1]: DRP[78] bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[78] bit 4	GTX[1]: DRP[78] bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[78] bit 2	GTX[1]: DRP[78] bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[78] bit 0	GTX[1]: DRP[78] bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[77] bit 14 GTX[1]: RX_DLYALIGN_OVRDSETTING bit 6	GTX[1]: DRP[77] bit 15 GTX[1]: RX_DLYALIGN_OVRDSETTING bit 7
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[77] bit 12 GTX[1]: RX_DLYALIGN_OVRDSETTING bit 4	GTX[1]: DRP[77] bit 13 GTX[1]: RX_DLYALIGN_OVRDSETTING bit 5
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[77] bit 10 GTX[1]: RX_DLYALIGN_OVRDSETTING bit 2	GTX[1]: DRP[77] bit 11 GTX[1]: RX_DLYALIGN_OVRDSETTING bit 3
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[77] bit 8 GTX[1]: RX_DLYALIGN_OVRDSETTING bit 0	GTX[1]: DRP[77] bit 9 GTX[1]: RX_DLYALIGN_OVRDSETTING bit 1
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[77] bit 6 GTX[1]: RX_DLYALIGN_LPFINC bit 2	GTX[1]: DRP[77] bit 7 GTX[1]: RX_DLYALIGN_LPFINC bit 3
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[77] bit 4 GTX[1]: RX_DLYALIGN_LPFINC bit 0	GTX[1]: DRP[77] bit 5 GTX[1]: RX_DLYALIGN_LPFINC bit 1
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[77] bit 2 GTX[1]: RX_DLYALIGN_CTRINC bit 2	GTX[1]: DRP[77] bit 3 GTX[1]: RX_DLYALIGN_CTRINC bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[77] bit 0 GTX[1]: RX_DLYALIGN_CTRINC bit 0	GTX[1]: DRP[77] bit 1 GTX[1]: RX_DLYALIGN_CTRINC bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[76] bit 14 GTX[1]: TX_DLYALIGN_OVRDSETTING bit 6	GTX[1]: DRP[76] bit 15 GTX[1]: TX_DLYALIGN_OVRDSETTING bit 7
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[76] bit 12 GTX[1]: TX_DLYALIGN_OVRDSETTING bit 4	GTX[1]: DRP[76] bit 13 GTX[1]: TX_DLYALIGN_OVRDSETTING bit 5
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[76] bit 10 GTX[1]: TX_DLYALIGN_OVRDSETTING bit 2	GTX[1]: DRP[76] bit 11 GTX[1]: TX_DLYALIGN_OVRDSETTING bit 3
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[76] bit 8 GTX[1]: TX_DLYALIGN_OVRDSETTING bit 0	GTX[1]: DRP[76] bit 9 GTX[1]: TX_DLYALIGN_OVRDSETTING bit 1
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[76] bit 6 GTX[1]: TX_DLYALIGN_LPFINC bit 2	GTX[1]: DRP[76] bit 7 GTX[1]: TX_DLYALIGN_LPFINC bit 3
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[76] bit 4 GTX[1]: TX_DLYALIGN_LPFINC bit 0	GTX[1]: DRP[76] bit 5 GTX[1]: TX_DLYALIGN_LPFINC bit 1
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[76] bit 2 GTX[1]: TX_DLYALIGN_CTRINC bit 2	GTX[1]: DRP[76] bit 3 GTX[1]: TX_DLYALIGN_CTRINC bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[76] bit 0 GTX[1]: TX_DLYALIGN_CTRINC bit 0	GTX[1]: DRP[76] bit 1 GTX[1]: TX_DLYALIGN_CTRINC bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[75] bit 14 GTX[1]: RX_EN_REALIGN_RESET_BUF2	GTX[1]: DRP[75] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[75] bit 12	GTX[1]: DRP[75] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[75] bit 10 GTX[1]: RX_DLYALIGN_EDGESET bit 4	GTX[1]: DRP[75] bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[75] bit 8 GTX[1]: RX_DLYALIGN_EDGESET bit 2	GTX[1]: DRP[75] bit 9 GTX[1]: RX_DLYALIGN_EDGESET bit 3
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[75] bit 6 GTX[1]: RX_DLYALIGN_EDGESET bit 0	GTX[1]: DRP[75] bit 7 GTX[1]: RX_DLYALIGN_EDGESET bit 1
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[75] bit 4 GTX[1]: TX_DLYALIGN_MONSEL bit 1	GTX[1]: DRP[75] bit 5 GTX[1]: TX_DLYALIGN_MONSEL bit 2
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[75] bit 2 GTX[1]: RX_DLYALIGN_MONSEL bit 2	GTX[1]: DRP[75] bit 3 GTX[1]: TX_DLYALIGN_MONSEL bit 0
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[75] bit 0 GTX[1]: RX_DLYALIGN_MONSEL bit 0	GTX[1]: DRP[75] bit 1 GTX[1]: RX_DLYALIGN_MONSEL bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[74] bit 14	GTX[1]: DRP[74] bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[74] bit 12	GTX[1]: DRP[74] bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[74] bit 10	GTX[1]: DRP[74] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[74] bit 8	GTX[1]: DRP[74] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[74] bit 6	GTX[1]: DRP[74] bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[74] bit 4	GTX[1]: DRP[74] bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[74] bit 2	GTX[1]: DRP[74] bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[74] bit 0	GTX[1]: DRP[74] bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[73] bit 14	GTX[1]: DRP[73] bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[73] bit 12	GTX[1]: DRP[73] bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[73] bit 10	GTX[1]: DRP[73] bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTCLK[1]: REFCLKOUT_DLY bit 8 GTX[1]: DRP[73] bit 8	GTCLK[1]: REFCLKOUT_DLY bit 9 GTX[1]: DRP[73] bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTCLK[1]: REFCLKOUT_DLY bit 6 GTX[1]: DRP[73] bit 6	GTCLK[1]: REFCLKOUT_DLY bit 7 GTX[1]: DRP[73] bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTCLK[1]: REFCLKOUT_DLY bit 4 GTX[1]: DRP[73] bit 4	GTCLK[1]: REFCLKOUT_DLY bit 5 GTX[1]: DRP[73] bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTCLK[1]: REFCLKOUT_DLY bit 2 GTX[1]: DRP[73] bit 2	GTCLK[1]: REFCLKOUT_DLY bit 3 GTX[1]: DRP[73] bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTCLK[1]: REFCLKOUT_DLY bit 0 GTX[1]: DRP[73] bit 0	GTCLK[1]: REFCLKOUT_DLY bit 1 GTX[1]: DRP[73] bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[72] bit 14	GTX[1]: DRP[72] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[72] bit 12	GTX[1]: DRP[72] bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[1]: DRP[72] bit 10	GTX[1]: DRP[72] bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTCLK[0]: REFCLKOUT_DLY bit 8 GTX[1]: DRP[72] bit 8	GTCLK[0]: REFCLKOUT_DLY bit 9 GTX[1]: DRP[72] bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTCLK[0]: REFCLKOUT_DLY bit 6 GTX[1]: DRP[72] bit 6	GTCLK[0]: REFCLKOUT_DLY bit 7 GTX[1]: DRP[72] bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTCLK[0]: REFCLKOUT_DLY bit 4 GTX[1]: DRP[72] bit 4	GTCLK[0]: REFCLKOUT_DLY bit 5 GTX[1]: DRP[72] bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTCLK[0]: REFCLKOUT_DLY bit 2 GTX[1]: DRP[72] bit 2	GTCLK[0]: REFCLKOUT_DLY bit 3 GTX[1]: DRP[72] bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTCLK[0]: REFCLKOUT_DLY bit 0 GTX[1]: DRP[72] bit 0	GTCLK[0]: REFCLKOUT_DLY bit 1 GTX[1]: DRP[72] bit 1

virtex6 GTX rect MAIN[20]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[7] bit 14 GTX[2]: RX_IDLE_LO_CNT bit 2	GTX[2]: DRP[7] bit 15 GTX[2]: RX_IDLE_LO_CNT bit 3
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[7] bit 12 GTX[2]: RX_IDLE_LO_CNT bit 0	GTX[2]: DRP[7] bit 13 GTX[2]: RX_IDLE_LO_CNT bit 1
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[7] bit 10 GTX[2]: CHAN_BOND_SEQ_LEN bit 0	GTX[2]: DRP[7] bit 11 GTX[2]: CHAN_BOND_SEQ_LEN bit 1
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[7] bit 8 GTX[2]: CHAN_BOND_SEQ_1_4 bit 8	GTX[2]: DRP[7] bit 9 GTX[2]: CHAN_BOND_SEQ_1_4 bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[7] bit 6 GTX[2]: CHAN_BOND_SEQ_1_4 bit 6	GTX[2]: DRP[7] bit 7 GTX[2]: CHAN_BOND_SEQ_1_4 bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[7] bit 4 GTX[2]: CHAN_BOND_SEQ_1_4 bit 4	GTX[2]: DRP[7] bit 5 GTX[2]: CHAN_BOND_SEQ_1_4 bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[7] bit 2 GTX[2]: CHAN_BOND_SEQ_1_4 bit 2	GTX[2]: DRP[7] bit 3 GTX[2]: CHAN_BOND_SEQ_1_4 bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[7] bit 0 GTX[2]: CHAN_BOND_SEQ_1_4 bit 0	GTX[2]: DRP[7] bit 1 GTX[2]: CHAN_BOND_SEQ_1_4 bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[6] bit 14 GTX[2]: RX_LOS_INVALID_INCR bit 1	GTX[2]: DRP[6] bit 15 GTX[2]: RX_LOS_INVALID_INCR bit 2
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[6] bit 12 GTX[2]: RX_LOS_THRESHOLD bit 2	GTX[2]: DRP[6] bit 13 GTX[2]: RX_LOS_INVALID_INCR bit 0
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[6] bit 10 GTX[2]: RX_LOS_THRESHOLD bit 0	GTX[2]: DRP[6] bit 11 GTX[2]: RX_LOS_THRESHOLD bit 1
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[6] bit 8 GTX[2]: CHAN_BOND_SEQ_1_3 bit 8	GTX[2]: DRP[6] bit 9 GTX[2]: CHAN_BOND_SEQ_1_3 bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[6] bit 6 GTX[2]: CHAN_BOND_SEQ_1_3 bit 6	GTX[2]: DRP[6] bit 7 GTX[2]: CHAN_BOND_SEQ_1_3 bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[6] bit 4 GTX[2]: CHAN_BOND_SEQ_1_3 bit 4	GTX[2]: DRP[6] bit 5 GTX[2]: CHAN_BOND_SEQ_1_3 bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[6] bit 2 GTX[2]: CHAN_BOND_SEQ_1_3 bit 2	GTX[2]: DRP[6] bit 3 GTX[2]: CHAN_BOND_SEQ_1_3 bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[6] bit 0 GTX[2]: CHAN_BOND_SEQ_1_3 bit 0	GTX[2]: DRP[6] bit 1 GTX[2]: CHAN_BOND_SEQ_1_3 bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: !invert RXUSRCLK GTX[2]: DRP[5] bit 14	GTX[2]: !invert RXUSRCLK2 GTX[2]: DRP[5] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[5] bit 12 GTX[2]: CHAN_BOND_1_MAX_SKEW bit 2	GTX[2]: DRP[5] bit 13 GTX[2]: CHAN_BOND_1_MAX_SKEW bit 3
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[5] bit 10 GTX[2]: CHAN_BOND_1_MAX_SKEW bit 0	GTX[2]: DRP[5] bit 11 GTX[2]: CHAN_BOND_1_MAX_SKEW bit 1
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[5] bit 8 GTX[2]: CHAN_BOND_SEQ_1_2 bit 8	GTX[2]: DRP[5] bit 9 GTX[2]: CHAN_BOND_SEQ_1_2 bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[5] bit 6 GTX[2]: CHAN_BOND_SEQ_1_2 bit 6	GTX[2]: DRP[5] bit 7 GTX[2]: CHAN_BOND_SEQ_1_2 bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[5] bit 4 GTX[2]: CHAN_BOND_SEQ_1_2 bit 4	GTX[2]: DRP[5] bit 5 GTX[2]: CHAN_BOND_SEQ_1_2 bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[5] bit 2 GTX[2]: CHAN_BOND_SEQ_1_2 bit 2	GTX[2]: DRP[5] bit 3 GTX[2]: CHAN_BOND_SEQ_1_2 bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[5] bit 0 GTX[2]: CHAN_BOND_SEQ_1_2 bit 0	GTX[2]: DRP[5] bit 1 GTX[2]: CHAN_BOND_SEQ_1_2 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[4] bit 14 GTX[2]: RX_BUFFER_USE	GTX[2]: DRP[4] bit 15 GTX[2]: RX_LOSS_OF_SYNC_FSM
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[4] bit 12 GTX[2]: CHAN_BOND_SEQ_1_ENABLE bit 2	GTX[2]: DRP[4] bit 13 GTX[2]: CHAN_BOND_SEQ_1_ENABLE bit 3
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[4] bit 10 GTX[2]: CHAN_BOND_SEQ_1_ENABLE bit 0	GTX[2]: DRP[4] bit 11 GTX[2]: CHAN_BOND_SEQ_1_ENABLE bit 1
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[4] bit 8 GTX[2]: CHAN_BOND_SEQ_1_1 bit 8	GTX[2]: DRP[4] bit 9 GTX[2]: CHAN_BOND_SEQ_1_1 bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[4] bit 6 GTX[2]: CHAN_BOND_SEQ_1_1 bit 6	GTX[2]: DRP[4] bit 7 GTX[2]: CHAN_BOND_SEQ_1_1 bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[4] bit 4 GTX[2]: CHAN_BOND_SEQ_1_1 bit 4	GTX[2]: DRP[4] bit 5 GTX[2]: CHAN_BOND_SEQ_1_1 bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[4] bit 2 GTX[2]: CHAN_BOND_SEQ_1_1 bit 2	GTX[2]: DRP[4] bit 3 GTX[2]: CHAN_BOND_SEQ_1_1 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[4] bit 0 GTX[2]: CHAN_BOND_SEQ_1_1 bit 0	GTX[2]: DRP[4] bit 1 GTX[2]: CHAN_BOND_SEQ_1_1 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[3] bit 14 GTX[2]: BIAS_CFG bit 14	GTX[2]: DRP[3] bit 15 GTX[2]: BIAS_CFG bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[3] bit 12 GTX[2]: BIAS_CFG bit 12	GTX[2]: DRP[3] bit 13 GTX[2]: BIAS_CFG bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[3] bit 10 GTX[2]: BIAS_CFG bit 10	GTX[2]: DRP[3] bit 11 GTX[2]: BIAS_CFG bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[3] bit 8 GTX[2]: BIAS_CFG bit 8	GTX[2]: DRP[3] bit 9 GTX[2]: BIAS_CFG bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[3] bit 6 GTX[2]: BIAS_CFG bit 6	GTX[2]: DRP[3] bit 7 GTX[2]: BIAS_CFG bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[3] bit 4 GTX[2]: BIAS_CFG bit 4	GTX[2]: DRP[3] bit 5 GTX[2]: BIAS_CFG bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[3] bit 2 GTX[2]: BIAS_CFG bit 2	GTX[2]: DRP[3] bit 3 GTX[2]: BIAS_CFG bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[3] bit 0 GTX[2]: BIAS_CFG bit 0	GTX[2]: DRP[3] bit 1 GTX[2]: BIAS_CFG bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[2] bit 14 GTX[2]: RXUSRCLK_DLY bit 14	GTX[2]: DRP[2] bit 15 GTX[2]: RXUSRCLK_DLY bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[2] bit 12 GTX[2]: RXUSRCLK_DLY bit 12	GTX[2]: DRP[2] bit 13 GTX[2]: RXUSRCLK_DLY bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[2] bit 10 GTX[2]: RXUSRCLK_DLY bit 10	GTX[2]: DRP[2] bit 11 GTX[2]: RXUSRCLK_DLY bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[2] bit 8 GTX[2]: RXUSRCLK_DLY bit 8	GTX[2]: DRP[2] bit 9 GTX[2]: RXUSRCLK_DLY bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[2] bit 6 GTX[2]: RXUSRCLK_DLY bit 6	GTX[2]: DRP[2] bit 7 GTX[2]: RXUSRCLK_DLY bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[2] bit 4 GTX[2]: RXUSRCLK_DLY bit 4	GTX[2]: DRP[2] bit 5 GTX[2]: RXUSRCLK_DLY bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[2] bit 2 GTX[2]: RXUSRCLK_DLY bit 2	GTX[2]: DRP[2] bit 3 GTX[2]: RXUSRCLK_DLY bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[2] bit 0 GTX[2]: RXUSRCLK_DLY bit 0	GTX[2]: DRP[2] bit 1 GTX[2]: RXUSRCLK_DLY bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[1] bit 14 GTX[2]: PMA_RXSYNC_CFG bit 5	GTX[2]: DRP[1] bit 15 GTX[2]: PMA_RXSYNC_CFG bit 6
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[1] bit 12 GTX[2]: PMA_RXSYNC_CFG bit 3	GTX[2]: DRP[1] bit 13 GTX[2]: PMA_RXSYNC_CFG bit 4
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[1] bit 10 GTX[2]: PMA_RXSYNC_CFG bit 1	GTX[2]: DRP[1] bit 11 GTX[2]: PMA_RXSYNC_CFG bit 2
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[1] bit 8 GTX[2]: PMA_RX_CFG bit 24	GTX[2]: DRP[1] bit 9 GTX[2]: PMA_RXSYNC_CFG bit 0
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[1] bit 6 GTX[2]: PMA_RX_CFG bit 22	GTX[2]: DRP[1] bit 7 GTX[2]: PMA_RX_CFG bit 23
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[1] bit 4 GTX[2]: PMA_RX_CFG bit 20	GTX[2]: DRP[1] bit 5 GTX[2]: PMA_RX_CFG bit 21
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[1] bit 2 GTX[2]: PMA_RX_CFG bit 18	GTX[2]: DRP[1] bit 3 GTX[2]: PMA_RX_CFG bit 19
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[1] bit 0 GTX[2]: PMA_RX_CFG bit 16	GTX[2]: DRP[1] bit 1 GTX[2]: PMA_RX_CFG bit 17
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[0] bit 14 GTX[2]: PMA_RX_CFG bit 14	GTX[2]: DRP[0] bit 15 GTX[2]: PMA_RX_CFG bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[0] bit 12 GTX[2]: PMA_RX_CFG bit 12	GTX[2]: DRP[0] bit 13 GTX[2]: PMA_RX_CFG bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[0] bit 10 GTX[2]: PMA_RX_CFG bit 10	GTX[2]: DRP[0] bit 11 GTX[2]: PMA_RX_CFG bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[0] bit 8 GTX[2]: PMA_RX_CFG bit 8	GTX[2]: DRP[0] bit 9 GTX[2]: PMA_RX_CFG bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[0] bit 6 GTX[2]: PMA_RX_CFG bit 6	GTX[2]: DRP[0] bit 7 GTX[2]: PMA_RX_CFG bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[0] bit 4 GTX[2]: PMA_RX_CFG bit 4	GTX[2]: DRP[0] bit 5 GTX[2]: PMA_RX_CFG bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[0] bit 2 GTX[2]: PMA_RX_CFG bit 2	GTX[2]: DRP[0] bit 3 GTX[2]: PMA_RX_CFG bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[0] bit 0 GTX[2]: PMA_RX_CFG bit 0	GTX[2]: DRP[0] bit 1 GTX[2]: PMA_RX_CFG bit 1

virtex6 GTX rect MAIN[21]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[15] bit 14 GTX[2]: CLK_COR_MIN_LAT bit 4	GTX[2]: DRP[15] bit 15 GTX[2]: CLK_COR_MIN_LAT bit 5
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[15] bit 12 GTX[2]: CLK_COR_MIN_LAT bit 2	GTX[2]: DRP[15] bit 13 GTX[2]: CLK_COR_MIN_LAT bit 3
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[15] bit 10 GTX[2]: CLK_COR_MIN_LAT bit 0	GTX[2]: DRP[15] bit 11 GTX[2]: CLK_COR_MIN_LAT bit 1
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[15] bit 8 GTX[2]: CLK_COR_SEQ_1_3 bit 8	GTX[2]: DRP[15] bit 9 GTX[2]: CLK_COR_SEQ_1_3 bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[15] bit 6 GTX[2]: CLK_COR_SEQ_1_3 bit 6	GTX[2]: DRP[15] bit 7 GTX[2]: CLK_COR_SEQ_1_3 bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[15] bit 4 GTX[2]: CLK_COR_SEQ_1_3 bit 4	GTX[2]: DRP[15] bit 5 GTX[2]: CLK_COR_SEQ_1_3 bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[15] bit 2 GTX[2]: CLK_COR_SEQ_1_3 bit 2	GTX[2]: DRP[15] bit 3 GTX[2]: CLK_COR_SEQ_1_3 bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[15] bit 0 GTX[2]: CLK_COR_SEQ_1_3 bit 0	GTX[2]: DRP[15] bit 1 GTX[2]: CLK_COR_SEQ_1_3 bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[14] bit 14 GTX[2]: CLK_COR_REPEAT_WAIT bit 4	GTX[2]: DRP[14] bit 15 GTX[2]: CLK_COR_KEEP_IDLE
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[14] bit 12 GTX[2]: CLK_COR_REPEAT_WAIT bit 2	GTX[2]: DRP[14] bit 13 GTX[2]: CLK_COR_REPEAT_WAIT bit 3
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[14] bit 10 GTX[2]: CLK_COR_REPEAT_WAIT bit 0	GTX[2]: DRP[14] bit 11 GTX[2]: CLK_COR_REPEAT_WAIT bit 1
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[14] bit 8 GTX[2]: CLK_COR_SEQ_1_2 bit 8	GTX[2]: DRP[14] bit 9 GTX[2]: CLK_COR_SEQ_1_2 bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[14] bit 6 GTX[2]: CLK_COR_SEQ_1_2 bit 6	GTX[2]: DRP[14] bit 7 GTX[2]: CLK_COR_SEQ_1_2 bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[14] bit 4 GTX[2]: CLK_COR_SEQ_1_2 bit 4	GTX[2]: DRP[14] bit 5 GTX[2]: CLK_COR_SEQ_1_2 bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[14] bit 2 GTX[2]: CLK_COR_SEQ_1_2 bit 2	GTX[2]: DRP[14] bit 3 GTX[2]: CLK_COR_SEQ_1_2 bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[14] bit 0 GTX[2]: CLK_COR_SEQ_1_2 bit 0	GTX[2]: DRP[14] bit 1 GTX[2]: CLK_COR_SEQ_1_2 bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[13] bit 14 GTX[2]: CLK_CORRECT_USE	GTX[2]: DRP[13] bit 15 GTX[2]: CLK_COR_PRECEDENCE
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[13] bit 12 GTX[2]: CLK_COR_SEQ_1_ENABLE bit 2	GTX[2]: DRP[13] bit 13 GTX[2]: CLK_COR_SEQ_1_ENABLE bit 3
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[13] bit 10 GTX[2]: CLK_COR_SEQ_1_ENABLE bit 0	GTX[2]: DRP[13] bit 11 GTX[2]: CLK_COR_SEQ_1_ENABLE bit 1
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[13] bit 8 GTX[2]: CLK_COR_SEQ_1_1 bit 8	GTX[2]: DRP[13] bit 9 GTX[2]: CLK_COR_SEQ_1_1 bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[13] bit 6 GTX[2]: CLK_COR_SEQ_1_1 bit 6	GTX[2]: DRP[13] bit 7 GTX[2]: CLK_COR_SEQ_1_1 bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[13] bit 4 GTX[2]: CLK_COR_SEQ_1_1 bit 4	GTX[2]: DRP[13] bit 5 GTX[2]: CLK_COR_SEQ_1_1 bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[13] bit 2 GTX[2]: CLK_COR_SEQ_1_1 bit 2	GTX[2]: DRP[13] bit 3 GTX[2]: CLK_COR_SEQ_1_1 bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[13] bit 0 GTX[2]: CLK_COR_SEQ_1_1 bit 0	GTX[2]: DRP[13] bit 1 GTX[2]: CLK_COR_SEQ_1_1 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[12] bit 14	GTX[2]: DRP[12] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[12] bit 12 GTX[2]: RXBUF_OVRD_THRESH	GTX[2]: DRP[12] bit 13 GTX[2]: RX_FIFO_ADDR_MODE bit 0
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[12] bit 10 GTX[2]: RXBUF_UDFL_THRESH bit 4	GTX[2]: DRP[12] bit 11 GTX[2]: RXBUF_UDFL_THRESH bit 5
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[12] bit 8 GTX[2]: RXBUF_UDFL_THRESH bit 2	GTX[2]: DRP[12] bit 9 GTX[2]: RXBUF_UDFL_THRESH bit 3
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[12] bit 6 GTX[2]: RXBUF_UDFL_THRESH bit 0	GTX[2]: DRP[12] bit 7 GTX[2]: RXBUF_UDFL_THRESH bit 1
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[12] bit 4 GTX[2]: RXBUF_OVFL_THRESH bit 4	GTX[2]: DRP[12] bit 5 GTX[2]: RXBUF_OVFL_THRESH bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[12] bit 2 GTX[2]: RXBUF_OVFL_THRESH bit 2	GTX[2]: DRP[12] bit 3 GTX[2]: RXBUF_OVFL_THRESH bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[12] bit 0 GTX[2]: RXBUF_OVFL_THRESH bit 0	GTX[2]: DRP[12] bit 1 GTX[2]: RXBUF_OVFL_THRESH bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[11] bit 14 GTX[2]: RX_IDLE_HI_CNT bit 2	GTX[2]: DRP[11] bit 15 GTX[2]: RX_IDLE_HI_CNT bit 3
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[11] bit 12 GTX[2]: RX_IDLE_HI_CNT bit 0	GTX[2]: DRP[11] bit 13 GTX[2]: RX_IDLE_HI_CNT bit 1
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[11] bit 10 GTX[2]: RX_EN_IDLE_RESET_BUF	GTX[2]: DRP[11] bit 11 GTX[2]: RX_XCLK_SEL bit 0
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[11] bit 8 GTX[2]: CHAN_BOND_SEQ_2_4 bit 8	GTX[2]: DRP[11] bit 9 GTX[2]: CHAN_BOND_SEQ_2_4 bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[11] bit 6 GTX[2]: CHAN_BOND_SEQ_2_4 bit 6	GTX[2]: DRP[11] bit 7 GTX[2]: CHAN_BOND_SEQ_2_4 bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[11] bit 4 GTX[2]: CHAN_BOND_SEQ_2_4 bit 4	GTX[2]: DRP[11] bit 5 GTX[2]: CHAN_BOND_SEQ_2_4 bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[11] bit 2 GTX[2]: CHAN_BOND_SEQ_2_4 bit 2	GTX[2]: DRP[11] bit 3 GTX[2]: CHAN_BOND_SEQ_2_4 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[11] bit 0 GTX[2]: CHAN_BOND_SEQ_2_4 bit 0	GTX[2]: DRP[11] bit 1 GTX[2]: CHAN_BOND_SEQ_2_4 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[10] bit 14 GTX[2]: CHAN_BOND_SEQ_2_USE	GTX[2]: DRP[10] bit 15 GTX[2]: RX_EN_IDLE_RESET_PH
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[10] bit 12 GTX[2]: CHAN_BOND_SEQ_2_CFG bit 2	GTX[2]: DRP[10] bit 13 GTX[2]: CHAN_BOND_SEQ_2_CFG bit 3
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[10] bit 10 GTX[2]: CHAN_BOND_SEQ_2_CFG bit 0	GTX[2]: DRP[10] bit 11 GTX[2]: CHAN_BOND_SEQ_2_CFG bit 1
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[10] bit 8 GTX[2]: CHAN_BOND_SEQ_2_3 bit 8	GTX[2]: DRP[10] bit 9 GTX[2]: CHAN_BOND_SEQ_2_3 bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[10] bit 6 GTX[2]: CHAN_BOND_SEQ_2_3 bit 6	GTX[2]: DRP[10] bit 7 GTX[2]: CHAN_BOND_SEQ_2_3 bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[10] bit 4 GTX[2]: CHAN_BOND_SEQ_2_3 bit 4	GTX[2]: DRP[10] bit 5 GTX[2]: CHAN_BOND_SEQ_2_3 bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[10] bit 2 GTX[2]: CHAN_BOND_SEQ_2_3 bit 2	GTX[2]: DRP[10] bit 3 GTX[2]: CHAN_BOND_SEQ_2_3 bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[10] bit 0 GTX[2]: CHAN_BOND_SEQ_2_3 bit 0	GTX[2]: DRP[10] bit 1 GTX[2]: CHAN_BOND_SEQ_2_3 bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[9] bit 14 GTX[2]: CHAN_BOND_KEEP_ALIGN	GTX[2]: DRP[9] bit 15 GTX[2]: RX_EN_MODE_RESET_BUF
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[9] bit 12 GTX[2]: CHAN_BOND_2_MAX_SKEW bit 2	GTX[2]: DRP[9] bit 13 GTX[2]: CHAN_BOND_2_MAX_SKEW bit 3
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[9] bit 10 GTX[2]: CHAN_BOND_2_MAX_SKEW bit 0	GTX[2]: DRP[9] bit 11 GTX[2]: CHAN_BOND_2_MAX_SKEW bit 1
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[9] bit 8 GTX[2]: CHAN_BOND_SEQ_2_2 bit 8	GTX[2]: DRP[9] bit 9 GTX[2]: CHAN_BOND_SEQ_2_2 bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[9] bit 6 GTX[2]: CHAN_BOND_SEQ_2_2 bit 6	GTX[2]: DRP[9] bit 7 GTX[2]: CHAN_BOND_SEQ_2_2 bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[9] bit 4 GTX[2]: CHAN_BOND_SEQ_2_2 bit 4	GTX[2]: DRP[9] bit 5 GTX[2]: CHAN_BOND_SEQ_2_2 bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[9] bit 2 GTX[2]: CHAN_BOND_SEQ_2_2 bit 2	GTX[2]: DRP[9] bit 3 GTX[2]: CHAN_BOND_SEQ_2_2 bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[9] bit 0 GTX[2]: CHAN_BOND_SEQ_2_2 bit 0	GTX[2]: DRP[9] bit 1 GTX[2]: CHAN_BOND_SEQ_2_2 bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[8] bit 14 GTX[2]: RX_EN_REALIGN_RESET_BUF	GTX[2]: DRP[8] bit 15 GTX[2]: RX_EN_RATE_RESET_BUF
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[8] bit 12 GTX[2]: CHAN_BOND_SEQ_2_ENABLE bit 2	GTX[2]: DRP[8] bit 13 GTX[2]: CHAN_BOND_SEQ_2_ENABLE bit 3
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[8] bit 10 GTX[2]: CHAN_BOND_SEQ_2_ENABLE bit 0	GTX[2]: DRP[8] bit 11 GTX[2]: CHAN_BOND_SEQ_2_ENABLE bit 1
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[8] bit 8 GTX[2]: CHAN_BOND_SEQ_2_1 bit 8	GTX[2]: DRP[8] bit 9 GTX[2]: CHAN_BOND_SEQ_2_1 bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[8] bit 6 GTX[2]: CHAN_BOND_SEQ_2_1 bit 6	GTX[2]: DRP[8] bit 7 GTX[2]: CHAN_BOND_SEQ_2_1 bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[8] bit 4 GTX[2]: CHAN_BOND_SEQ_2_1 bit 4	GTX[2]: DRP[8] bit 5 GTX[2]: CHAN_BOND_SEQ_2_1 bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[8] bit 2 GTX[2]: CHAN_BOND_SEQ_2_1 bit 2	GTX[2]: DRP[8] bit 3 GTX[2]: CHAN_BOND_SEQ_2_1 bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[8] bit 0 GTX[2]: CHAN_BOND_SEQ_2_1 bit 0	GTX[2]: DRP[8] bit 1 GTX[2]: CHAN_BOND_SEQ_2_1 bit 1

virtex6 GTX rect MAIN[22]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[23] bit 14 GTX[2]: RX_DATA_WIDTH bit 2	GTX[2]: DRP[23] bit 15 GTX[2]: GEN_RXUSRCLK
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[23] bit 12 GTX[2]: RX_DATA_WIDTH bit 0	GTX[2]: DRP[23] bit 13 GTX[2]: RX_DATA_WIDTH bit 1
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[23] bit 10 GTX[2]: BIAS_CFG bit 16	GTX[2]: DRP[23] bit 11 GTX[2]: CHAN_BOND_SEQ_2_CFG bit 4
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[23] bit 8 GTX[2]: RX_CLK25_DIVIDER bit 3	GTX[2]: DRP[23] bit 9 GTX[2]: RX_CLK25_DIVIDER bit 4
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[23] bit 6 GTX[2]: RX_CLK25_DIVIDER bit 1	GTX[2]: DRP[23] bit 7 GTX[2]: RX_CLK25_DIVIDER bit 2
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[23] bit 4 GTX[2]: AC_CAP_DIS	GTX[2]: DRP[23] bit 5 GTX[2]: RX_CLK25_DIVIDER bit 0
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[23] bit 2 GTX[2]: OOBDETECT_THRESHOLD bit 2	GTX[2]: DRP[23] bit 3 GTX[2]: GTX_CFG_PWRUP
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[23] bit 0 GTX[2]: OOBDETECT_THRESHOLD bit 0	GTX[2]: DRP[23] bit 1 GTX[2]: OOBDETECT_THRESHOLD bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[22] bit 14 GTX[2]: CDR_PH_ADJ_TIME bit 3	GTX[2]: DRP[22] bit 15 GTX[2]: CDR_PH_ADJ_TIME bit 4
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[22] bit 12 GTX[2]: CDR_PH_ADJ_TIME bit 1	GTX[2]: DRP[22] bit 13 GTX[2]: CDR_PH_ADJ_TIME bit 2
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[22] bit 10 GTX[2]: PMA_CDR_SCAN bit 26	GTX[2]: DRP[22] bit 11 GTX[2]: CDR_PH_ADJ_TIME bit 0
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[22] bit 8 GTX[2]: PMA_CDR_SCAN bit 24	GTX[2]: DRP[22] bit 9 GTX[2]: PMA_CDR_SCAN bit 25
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[22] bit 6 GTX[2]: PMA_CDR_SCAN bit 22	GTX[2]: DRP[22] bit 7 GTX[2]: PMA_CDR_SCAN bit 23
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[22] bit 4 GTX[2]: PMA_CDR_SCAN bit 20	GTX[2]: DRP[22] bit 5 GTX[2]: PMA_CDR_SCAN bit 21
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[22] bit 2 GTX[2]: PMA_CDR_SCAN bit 18	GTX[2]: DRP[22] bit 3 GTX[2]: PMA_CDR_SCAN bit 19
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[22] bit 0 GTX[2]: PMA_CDR_SCAN bit 16	GTX[2]: DRP[22] bit 1 GTX[2]: PMA_CDR_SCAN bit 17
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[21] bit 14 GTX[2]: PMA_CDR_SCAN bit 14	GTX[2]: DRP[21] bit 15 GTX[2]: PMA_CDR_SCAN bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[21] bit 12 GTX[2]: PMA_CDR_SCAN bit 12	GTX[2]: DRP[21] bit 13 GTX[2]: PMA_CDR_SCAN bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[21] bit 10 GTX[2]: PMA_CDR_SCAN bit 10	GTX[2]: DRP[21] bit 11 GTX[2]: PMA_CDR_SCAN bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[21] bit 8 GTX[2]: PMA_CDR_SCAN bit 8	GTX[2]: DRP[21] bit 9 GTX[2]: PMA_CDR_SCAN bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[21] bit 6 GTX[2]: PMA_CDR_SCAN bit 6	GTX[2]: DRP[21] bit 7 GTX[2]: PMA_CDR_SCAN bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[21] bit 4 GTX[2]: PMA_CDR_SCAN bit 4	GTX[2]: DRP[21] bit 5 GTX[2]: PMA_CDR_SCAN bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[21] bit 2 GTX[2]: PMA_CDR_SCAN bit 2	GTX[2]: DRP[21] bit 3 GTX[2]: PMA_CDR_SCAN bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[21] bit 0 GTX[2]: PMA_CDR_SCAN bit 0	GTX[2]: DRP[21] bit 1 GTX[2]: PMA_CDR_SCAN bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[20] bit 14 GTX[2]: ALIGN_COMMA_WORD bit 0	GTX[2]: DRP[20] bit 15 GTX[2]: DEC_VALID_COMMA_ONLY
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[20] bit 12 GTX[2]: USR_CODE_ERR_CLR bit 0	GTX[2]: DRP[20] bit 13 GTX[2]: RX_DECODE_SEQ_MATCH
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[20] bit 10 GTX[2]: DEC_PCOMMA_DETECT	GTX[2]: DRP[20] bit 11 GTX[2]: DEC_MCOMMA_DETECT
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[20] bit 8 GTX[2]: CLK_COR_SEQ_2_4 bit 8	GTX[2]: DRP[20] bit 9 GTX[2]: CLK_COR_SEQ_2_4 bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[20] bit 6 GTX[2]: CLK_COR_SEQ_2_4 bit 6	GTX[2]: DRP[20] bit 7 GTX[2]: CLK_COR_SEQ_2_4 bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[20] bit 4 GTX[2]: CLK_COR_SEQ_2_4 bit 4	GTX[2]: DRP[20] bit 5 GTX[2]: CLK_COR_SEQ_2_4 bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[20] bit 2 GTX[2]: CLK_COR_SEQ_2_4 bit 2	GTX[2]: DRP[20] bit 3 GTX[2]: CLK_COR_SEQ_2_4 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[20] bit 0 GTX[2]: CLK_COR_SEQ_2_4 bit 0	GTX[2]: DRP[20] bit 1 GTX[2]: CLK_COR_SEQ_2_4 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[19] bit 14 GTX[2]: RX_SLIDE_AUTO_WAIT bit 2	GTX[2]: DRP[19] bit 15 GTX[2]: RX_SLIDE_AUTO_WAIT bit 3
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[19] bit 12 GTX[2]: RX_SLIDE_AUTO_WAIT bit 0	GTX[2]: DRP[19] bit 13 GTX[2]: RX_SLIDE_AUTO_WAIT bit 1
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[19] bit 10 GTX[2]: CLK_COR_DET_LEN bit 0	GTX[2]: DRP[19] bit 11 GTX[2]: CLK_COR_DET_LEN bit 1
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[19] bit 8 GTX[2]: CLK_COR_SEQ_2_3 bit 8	GTX[2]: DRP[19] bit 9 GTX[2]: CLK_COR_SEQ_2_3 bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[19] bit 6 GTX[2]: CLK_COR_SEQ_2_3 bit 6	GTX[2]: DRP[19] bit 7 GTX[2]: CLK_COR_SEQ_2_3 bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[19] bit 4 GTX[2]: CLK_COR_SEQ_2_3 bit 4	GTX[2]: DRP[19] bit 5 GTX[2]: CLK_COR_SEQ_2_3 bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[19] bit 2 GTX[2]: CLK_COR_SEQ_2_3 bit 2	GTX[2]: DRP[19] bit 3 GTX[2]: CLK_COR_SEQ_2_3 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[19] bit 0 GTX[2]: CLK_COR_SEQ_2_3 bit 0	GTX[2]: DRP[19] bit 1 GTX[2]: CLK_COR_SEQ_2_3 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[18] bit 14 GTX[2]: SHOW_REALIGN_COMMA	GTX[2]: DRP[18] bit 15 GTX[2]: RX_CDR_FORCE_ROTATE
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[18] bit 12 GTX[2]: RX_SLIDE_MODE bit 0	GTX[2]: DRP[18] bit 13 GTX[2]: RX_SLIDE_MODE bit 1
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[18] bit 10 GTX[2]: CLK_COR_ADJ_LEN bit 0	GTX[2]: DRP[18] bit 11 GTX[2]: CLK_COR_ADJ_LEN bit 1
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[18] bit 8 GTX[2]: CLK_COR_SEQ_2_2 bit 8	GTX[2]: DRP[18] bit 9 GTX[2]: CLK_COR_SEQ_2_2 bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[18] bit 6 GTX[2]: CLK_COR_SEQ_2_2 bit 6	GTX[2]: DRP[18] bit 7 GTX[2]: CLK_COR_SEQ_2_2 bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[18] bit 4 GTX[2]: CLK_COR_SEQ_2_2 bit 4	GTX[2]: DRP[18] bit 5 GTX[2]: CLK_COR_SEQ_2_2 bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[18] bit 2 GTX[2]: CLK_COR_SEQ_2_2 bit 2	GTX[2]: DRP[18] bit 3 GTX[2]: CLK_COR_SEQ_2_2 bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[18] bit 0 GTX[2]: CLK_COR_SEQ_2_2 bit 0	GTX[2]: DRP[18] bit 1 GTX[2]: CLK_COR_SEQ_2_2 bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[17] bit 14 GTX[2]: CLK_COR_SEQ_2_USE	GTX[2]: DRP[17] bit 15 GTX[2]: CLK_COR_INSERT_IDLE_FLAG
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[17] bit 12 GTX[2]: CLK_COR_SEQ_2_ENABLE bit 2	GTX[2]: DRP[17] bit 13 GTX[2]: CLK_COR_SEQ_2_ENABLE bit 3
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[17] bit 10 GTX[2]: CLK_COR_SEQ_2_ENABLE bit 0	GTX[2]: DRP[17] bit 11 GTX[2]: CLK_COR_SEQ_2_ENABLE bit 1
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[17] bit 8 GTX[2]: CLK_COR_SEQ_2_1 bit 8	GTX[2]: DRP[17] bit 9 GTX[2]: CLK_COR_SEQ_2_1 bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[17] bit 6 GTX[2]: CLK_COR_SEQ_2_1 bit 6	GTX[2]: DRP[17] bit 7 GTX[2]: CLK_COR_SEQ_2_1 bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[17] bit 4 GTX[2]: CLK_COR_SEQ_2_1 bit 4	GTX[2]: DRP[17] bit 5 GTX[2]: CLK_COR_SEQ_2_1 bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[17] bit 2 GTX[2]: CLK_COR_SEQ_2_1 bit 2	GTX[2]: DRP[17] bit 3 GTX[2]: CLK_COR_SEQ_2_1 bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[17] bit 0 GTX[2]: CLK_COR_SEQ_2_1 bit 0	GTX[2]: DRP[17] bit 1 GTX[2]: CLK_COR_SEQ_2_1 bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[16] bit 14 GTX[2]: CLK_COR_MAX_LAT bit 4	GTX[2]: DRP[16] bit 15 GTX[2]: CLK_COR_MAX_LAT bit 5
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[16] bit 12 GTX[2]: CLK_COR_MAX_LAT bit 2	GTX[2]: DRP[16] bit 13 GTX[2]: CLK_COR_MAX_LAT bit 3
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[16] bit 10 GTX[2]: CLK_COR_MAX_LAT bit 0	GTX[2]: DRP[16] bit 11 GTX[2]: CLK_COR_MAX_LAT bit 1
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[16] bit 8 GTX[2]: CLK_COR_SEQ_1_4 bit 8	GTX[2]: DRP[16] bit 9 GTX[2]: CLK_COR_SEQ_1_4 bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[16] bit 6 GTX[2]: CLK_COR_SEQ_1_4 bit 6	GTX[2]: DRP[16] bit 7 GTX[2]: CLK_COR_SEQ_1_4 bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[16] bit 4 GTX[2]: CLK_COR_SEQ_1_4 bit 4	GTX[2]: DRP[16] bit 5 GTX[2]: CLK_COR_SEQ_1_4 bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[16] bit 2 GTX[2]: CLK_COR_SEQ_1_4 bit 2	GTX[2]: DRP[16] bit 3 GTX[2]: CLK_COR_SEQ_1_4 bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[16] bit 0 GTX[2]: CLK_COR_SEQ_1_4 bit 0	GTX[2]: DRP[16] bit 1 GTX[2]: CLK_COR_SEQ_1_4 bit 1

virtex6 GTX rect MAIN[23]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[31] bit 14 GTX[2]: TXPLL_DIVSEL_OUT bit 0	GTX[2]: DRP[31] bit 15 GTX[2]: TXPLL_DIVSEL_OUT bit 1
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[31] bit 12 GTX[2]: TXPLL_LKDET_CFG bit 1	GTX[2]: DRP[31] bit 13 GTX[2]: TXPLL_LKDET_CFG bit 2
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[31] bit 10 GTX[2]: A_TXPOWERDOWN bit 1	GTX[2]: DRP[31] bit 11 GTX[2]: TXPLL_LKDET_CFG bit 0
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[31] bit 8 GTX[2]: TX_CLK_SOURCE bit 0	GTX[2]: DRP[31] bit 9 GTX[2]: A_TXPOWERDOWN bit 0
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[31] bit 6 GTX[2]: TXPLL_DIVSEL45_FB bit 0	GTX[2]: DRP[31] bit 7 GTX[2]: TXPLL_STARTUP_EN
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[31] bit 4 GTX[2]: TXPLL_DIVSEL_FB bit 3	GTX[2]: DRP[31] bit 5 GTX[2]: TXPLL_DIVSEL_FB bit 4
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[31] bit 2 GTX[2]: TXPLL_DIVSEL_FB bit 1	GTX[2]: DRP[31] bit 3 GTX[2]: TXPLL_DIVSEL_FB bit 2
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[31] bit 0	GTX[2]: DRP[31] bit 1 GTX[2]: TXPLL_DIVSEL_FB bit 0
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[30] bit 14 GTX[2]: TXPLL_CP_CFG bit 6	GTX[2]: DRP[30] bit 15 GTX[2]: TXPLL_CP_CFG bit 7
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[30] bit 12 GTX[2]: TXPLL_CP_CFG bit 4	GTX[2]: DRP[30] bit 13 GTX[2]: TXPLL_CP_CFG bit 5
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[30] bit 10 GTX[2]: TXPLL_CP_CFG bit 2	GTX[2]: DRP[30] bit 11 GTX[2]: TXPLL_CP_CFG bit 3
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[30] bit 8 GTX[2]: TXPLL_CP_CFG bit 0	GTX[2]: DRP[30] bit 9 GTX[2]: TXPLL_CP_CFG bit 1
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[30] bit 6 GTX[2]: TXPLL_COM_CFG bit 22	GTX[2]: DRP[30] bit 7 GTX[2]: TXPLL_COM_CFG bit 23
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[30] bit 4 GTX[2]: TXPLL_COM_CFG bit 20	GTX[2]: DRP[30] bit 5 GTX[2]: TXPLL_COM_CFG bit 21
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[30] bit 2 GTX[2]: TXPLL_COM_CFG bit 18	GTX[2]: DRP[30] bit 3 GTX[2]: TXPLL_COM_CFG bit 19
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[30] bit 0 GTX[2]: TXPLL_COM_CFG bit 16	GTX[2]: DRP[30] bit 1 GTX[2]: TXPLL_COM_CFG bit 17
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[29] bit 14 GTX[2]: TXPLL_COM_CFG bit 14	GTX[2]: DRP[29] bit 15 GTX[2]: TXPLL_COM_CFG bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[29] bit 12 GTX[2]: TXPLL_COM_CFG bit 12	GTX[2]: DRP[29] bit 13 GTX[2]: TXPLL_COM_CFG bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[29] bit 10 GTX[2]: TXPLL_COM_CFG bit 10	GTX[2]: DRP[29] bit 11 GTX[2]: TXPLL_COM_CFG bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[29] bit 8 GTX[2]: TXPLL_COM_CFG bit 8	GTX[2]: DRP[29] bit 9 GTX[2]: TXPLL_COM_CFG bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[29] bit 6 GTX[2]: TXPLL_COM_CFG bit 6	GTX[2]: DRP[29] bit 7 GTX[2]: TXPLL_COM_CFG bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[29] bit 4 GTX[2]: TXPLL_COM_CFG bit 4	GTX[2]: DRP[29] bit 5 GTX[2]: TXPLL_COM_CFG bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[29] bit 2 GTX[2]: TXPLL_COM_CFG bit 2	GTX[2]: DRP[29] bit 3 GTX[2]: TXPLL_COM_CFG bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[29] bit 0 GTX[2]: TXPLL_COM_CFG bit 0	GTX[2]: DRP[29] bit 1 GTX[2]: TXPLL_COM_CFG bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[28] bit 14 GTX[2]: A_RXPLLPOWERDOWN bit 0	GTX[2]: DRP[28] bit 15 GTX[2]: RX_OVERSAMPLE_MODE
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[28] bit 12 GTX[2]: A_PLLCLKRXRESET bit 0	GTX[2]: DRP[28] bit 13 GTX[2]: PLL_DRP_EN
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[28] bit 10 GTX[2]: A_PLLRXRESET bit 0	GTX[2]: DRP[28] bit 11 GTX[2]: A_RXPLLLKDETEN bit 0
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[28] bit 8 GTX[2]: RXPLLREFSEL_STATIC_VAL bit 1	GTX[2]: DRP[28] bit 9 GTX[2]: RXPLLREFSEL_STATIC_VAL bit 2
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[28] bit 6 GTX[2]: RXPLLREFSEL_MODE_DYNAMIC	GTX[2]: DRP[28] bit 7 GTX[2]: RXPLLREFSEL_STATIC_VAL bit 0
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[28] bit 4 GTX[2]: RXPLL_DIVSEL_REF bit 3	GTX[2]: DRP[28] bit 5 GTX[2]: RXPLL_DIVSEL_REF bit 4
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[28] bit 2 GTX[2]: RXPLL_DIVSEL_REF bit 1	GTX[2]: DRP[28] bit 3 GTX[2]: RXPLL_DIVSEL_REF bit 2
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[28] bit 0 GTX[2]: RXPLLREFSEL_TESTCLK bit 0	GTX[2]: DRP[28] bit 1 GTX[2]: RXPLL_DIVSEL_REF bit 0
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[27] bit 14 GTX[2]: RXPLL_DIVSEL_OUT bit 0	GTX[2]: DRP[27] bit 15 GTX[2]: RXPLL_DIVSEL_OUT bit 1
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[27] bit 12 GTX[2]: RXPLL_LKDET_CFG bit 1	GTX[2]: DRP[27] bit 13 GTX[2]: RXPLL_LKDET_CFG bit 2
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[27] bit 10 GTX[2]: A_RXPOWERDOWN bit 1	GTX[2]: DRP[27] bit 11 GTX[2]: RXPLL_LKDET_CFG bit 0
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[27] bit 8	GTX[2]: DRP[27] bit 9 GTX[2]: A_RXPOWERDOWN bit 0
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[27] bit 6 GTX[2]: RXPLL_DIVSEL45_FB bit 0	GTX[2]: DRP[27] bit 7 GTX[2]: RXPLL_STARTUP_EN
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[27] bit 4 GTX[2]: RXPLL_DIVSEL_FB bit 3	GTX[2]: DRP[27] bit 5 GTX[2]: RXPLL_DIVSEL_FB bit 4
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[27] bit 2 GTX[2]: RXPLL_DIVSEL_FB bit 1	GTX[2]: DRP[27] bit 3 GTX[2]: RXPLL_DIVSEL_FB bit 2
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[27] bit 0	GTX[2]: DRP[27] bit 1 GTX[2]: RXPLL_DIVSEL_FB bit 0
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[26] bit 14 GTX[2]: RXPLL_CP_CFG bit 6	GTX[2]: DRP[26] bit 15 GTX[2]: RXPLL_CP_CFG bit 7
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[26] bit 12 GTX[2]: RXPLL_CP_CFG bit 4	GTX[2]: DRP[26] bit 13 GTX[2]: RXPLL_CP_CFG bit 5
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[26] bit 10 GTX[2]: RXPLL_CP_CFG bit 2	GTX[2]: DRP[26] bit 11 GTX[2]: RXPLL_CP_CFG bit 3
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[26] bit 8 GTX[2]: RXPLL_CP_CFG bit 0	GTX[2]: DRP[26] bit 9 GTX[2]: RXPLL_CP_CFG bit 1
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[26] bit 6 GTX[2]: RXPLL_COM_CFG bit 22	GTX[2]: DRP[26] bit 7 GTX[2]: RXPLL_COM_CFG bit 23
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[26] bit 4 GTX[2]: RXPLL_COM_CFG bit 20	GTX[2]: DRP[26] bit 5 GTX[2]: RXPLL_COM_CFG bit 21
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[26] bit 2 GTX[2]: RXPLL_COM_CFG bit 18	GTX[2]: DRP[26] bit 3 GTX[2]: RXPLL_COM_CFG bit 19
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[26] bit 0 GTX[2]: RXPLL_COM_CFG bit 16	GTX[2]: DRP[26] bit 1 GTX[2]: RXPLL_COM_CFG bit 17
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[25] bit 14 GTX[2]: RXPLL_COM_CFG bit 14	GTX[2]: DRP[25] bit 15 GTX[2]: RXPLL_COM_CFG bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[25] bit 12 GTX[2]: RXPLL_COM_CFG bit 12	GTX[2]: DRP[25] bit 13 GTX[2]: RXPLL_COM_CFG bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[25] bit 10 GTX[2]: RXPLL_COM_CFG bit 10	GTX[2]: DRP[25] bit 11 GTX[2]: RXPLL_COM_CFG bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[25] bit 8 GTX[2]: RXPLL_COM_CFG bit 8	GTX[2]: DRP[25] bit 9 GTX[2]: RXPLL_COM_CFG bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[25] bit 6 GTX[2]: RXPLL_COM_CFG bit 6	GTX[2]: DRP[25] bit 7 GTX[2]: RXPLL_COM_CFG bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[25] bit 4 GTX[2]: RXPLL_COM_CFG bit 4	GTX[2]: DRP[25] bit 5 GTX[2]: RXPLL_COM_CFG bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[25] bit 2 GTX[2]: RXPLL_COM_CFG bit 2	GTX[2]: DRP[25] bit 3 GTX[2]: RXPLL_COM_CFG bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[25] bit 0 GTX[2]: RXPLL_COM_CFG bit 0	GTX[2]: DRP[25] bit 1 GTX[2]: RXPLL_COM_CFG bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[24] bit 14 GTX[2]: RESET_DRP_EN	GTX[2]: DRP[24] bit 15 GTX[2]: MASTER_DRP_EN
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[24] bit 12 GTX[2]: A_RXCDRPHASERESET bit 0	GTX[2]: DRP[24] bit 13 GTX[2]: A_RXDFERESET bit 0
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[24] bit 10 GTX[2]: A_RXCDRHOLD bit 0	GTX[2]: DRP[24] bit 11 GTX[2]: A_RXCDRFREQRESET bit 0
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[24] bit 8 GTX[2]: A_RXRESET bit 0	GTX[2]: DRP[24] bit 9 GTX[2]: A_TXRESET bit 0
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[24] bit 6 GTX[2]: A_GTXRXRESET bit 0	GTX[2]: DRP[24] bit 7 GTX[2]: A_RXBUFRESET bit 0
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[24] bit 4 GTX[2]: A_RXCDRRESET bit 0	GTX[2]: DRP[24] bit 5 GTX[2]: A_GTXTXRESET bit 0
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[24] bit 2 GTX[2]: GEARBOX_ENDEC bit 2	GTX[2]: DRP[24] bit 3 GTX[2]: RXGEARBOX_USE
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[24] bit 0 GTX[2]: GEARBOX_ENDEC bit 0	GTX[2]: DRP[24] bit 1 GTX[2]: GEARBOX_ENDEC bit 1

virtex6 GTX rect MAIN[24]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[39] bit 14 GTX[2]: SATA_IDLE_VAL bit 2	GTX[2]: DRP[39] bit 15 GTX[2]: TX_EN_RATE_RESET_BUF
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[39] bit 12 GTX[2]: SATA_IDLE_VAL bit 0	GTX[2]: DRP[39] bit 13 GTX[2]: SATA_IDLE_VAL bit 1
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[39] bit 10 GTX[2]: SATA_MIN_INIT bit 4	GTX[2]: DRP[39] bit 11 GTX[2]: SATA_MIN_INIT bit 5
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[39] bit 8 GTX[2]: SATA_MIN_INIT bit 2	GTX[2]: DRP[39] bit 9 GTX[2]: SATA_MIN_INIT bit 3
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[39] bit 6 GTX[2]: SATA_MIN_INIT bit 0	GTX[2]: DRP[39] bit 7 GTX[2]: SATA_MIN_INIT bit 1
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[39] bit 4 GTX[2]: SATA_MAX_INIT bit 4	GTX[2]: DRP[39] bit 5 GTX[2]: SATA_MAX_INIT bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[39] bit 2 GTX[2]: SATA_MAX_INIT bit 2	GTX[2]: DRP[39] bit 3 GTX[2]: SATA_MAX_INIT bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[39] bit 0 GTX[2]: SATA_MAX_INIT bit 0	GTX[2]: DRP[39] bit 1 GTX[2]: SATA_MAX_INIT bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[38] bit 14 GTX[2]: BGTEST_CFG bit 0	GTX[2]: DRP[38] bit 15 GTX[2]: BGTEST_CFG bit 1
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[38] bit 12 GTX[2]: TXPLL_SATA bit 0	GTX[2]: DRP[38] bit 13 GTX[2]: TXPLL_SATA bit 1
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[38] bit 10 GTX[2]: SATA_MIN_WAKE bit 4	GTX[2]: DRP[38] bit 11 GTX[2]: SATA_MIN_WAKE bit 5
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[38] bit 8 GTX[2]: SATA_MIN_WAKE bit 2	GTX[2]: DRP[38] bit 9 GTX[2]: SATA_MIN_WAKE bit 3
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[38] bit 6 GTX[2]: SATA_MIN_WAKE bit 0	GTX[2]: DRP[38] bit 7 GTX[2]: SATA_MIN_WAKE bit 1
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[38] bit 4 GTX[2]: SATA_MAX_WAKE bit 4	GTX[2]: DRP[38] bit 5 GTX[2]: SATA_MAX_WAKE bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[38] bit 2 GTX[2]: SATA_MAX_WAKE bit 2	GTX[2]: DRP[38] bit 3 GTX[2]: SATA_MAX_WAKE bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[38] bit 0 GTX[2]: SATA_MAX_WAKE bit 0	GTX[2]: DRP[38] bit 1 GTX[2]: SATA_MAX_WAKE bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[37] bit 14 GTX[2]: A_RXENPMAPHASEALIGN bit 0	GTX[2]: DRP[37] bit 15 GTX[2]: TX_PMADATA_OPT bit 0
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[37] bit 12 GTX[2]: POLARITY_DRP_EN	GTX[2]: DRP[37] bit 13 GTX[2]: A_RXPMASETPHASE bit 0
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[37] bit 10 GTX[2]: A_RXPOLARITY bit 0	GTX[2]: DRP[37] bit 11 GTX[2]: A_TXPOLARITY bit 0
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[37] bit 8 GTX[2]: CM_TRIM bit 0	GTX[2]: DRP[37] bit 9 GTX[2]: CM_TRIM bit 1
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[37] bit 6 GTX[2]: TRANS_TIME_NON_P2 bit 6	GTX[2]: DRP[37] bit 7 GTX[2]: TRANS_TIME_NON_P2 bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[37] bit 4 GTX[2]: TRANS_TIME_NON_P2 bit 4	GTX[2]: DRP[37] bit 5 GTX[2]: TRANS_TIME_NON_P2 bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[37] bit 2 GTX[2]: TRANS_TIME_NON_P2 bit 2	GTX[2]: DRP[37] bit 3 GTX[2]: TRANS_TIME_NON_P2 bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[37] bit 0 GTX[2]: TRANS_TIME_NON_P2 bit 0	GTX[2]: DRP[37] bit 1 GTX[2]: TRANS_TIME_NON_P2 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[36] bit 14 GTX[2]: COM_BURST_VAL bit 2	GTX[2]: DRP[36] bit 15 GTX[2]: COM_BURST_VAL bit 3
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[36] bit 12 GTX[2]: COM_BURST_VAL bit 0	GTX[2]: DRP[36] bit 13 GTX[2]: COM_BURST_VAL bit 1
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[36] bit 10 GTX[2]: TRANS_TIME_FROM_P2 bit 10	GTX[2]: DRP[36] bit 11 GTX[2]: TRANS_TIME_FROM_P2 bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[36] bit 8 GTX[2]: TRANS_TIME_FROM_P2 bit 8	GTX[2]: DRP[36] bit 9 GTX[2]: TRANS_TIME_FROM_P2 bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[36] bit 6 GTX[2]: TRANS_TIME_FROM_P2 bit 6	GTX[2]: DRP[36] bit 7 GTX[2]: TRANS_TIME_FROM_P2 bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[36] bit 4 GTX[2]: TRANS_TIME_FROM_P2 bit 4	GTX[2]: DRP[36] bit 5 GTX[2]: TRANS_TIME_FROM_P2 bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[36] bit 2 GTX[2]: TRANS_TIME_FROM_P2 bit 2	GTX[2]: DRP[36] bit 3 GTX[2]: TRANS_TIME_FROM_P2 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[36] bit 0 GTX[2]: TRANS_TIME_FROM_P2 bit 0	GTX[2]: DRP[36] bit 1 GTX[2]: TRANS_TIME_FROM_P2 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[35] bit 14 GTX[2]: TX_CLK25_DIVIDER bit 4	GTX[2]: DRP[35] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[35] bit 12 GTX[2]: TX_CLK25_DIVIDER bit 2	GTX[2]: DRP[35] bit 13 GTX[2]: TX_CLK25_DIVIDER bit 3
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[35] bit 10 GTX[2]: TX_CLK25_DIVIDER bit 0	GTX[2]: DRP[35] bit 11 GTX[2]: TX_CLK25_DIVIDER bit 1
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[35] bit 8 GTX[2]: TRANS_TIME_TO_P2 bit 8	GTX[2]: DRP[35] bit 9 GTX[2]: TRANS_TIME_TO_P2 bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[35] bit 6 GTX[2]: TRANS_TIME_TO_P2 bit 6	GTX[2]: DRP[35] bit 7 GTX[2]: TRANS_TIME_TO_P2 bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[35] bit 4 GTX[2]: TRANS_TIME_TO_P2 bit 4	GTX[2]: DRP[35] bit 5 GTX[2]: TRANS_TIME_TO_P2 bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[35] bit 2 GTX[2]: TRANS_TIME_TO_P2 bit 2	GTX[2]: DRP[35] bit 3 GTX[2]: TRANS_TIME_TO_P2 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[35] bit 0 GTX[2]: TRANS_TIME_TO_P2 bit 0	GTX[2]: DRP[35] bit 1 GTX[2]: TRANS_TIME_TO_P2 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[34] bit 14	GTX[2]: DRP[34] bit 15 GTX[2]: PMA_CAS_CLK_EN
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[34] bit 12	GTX[2]: DRP[34] bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[34] bit 10	GTX[2]: DRP[34] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[34] bit 8	GTX[2]: DRP[34] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[34] bit 6	GTX[2]: DRP[34] bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[34] bit 4	GTX[2]: DRP[34] bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[34] bit 2	GTX[2]: DRP[34] bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[34] bit 0	GTX[2]: DRP[34] bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[33] bit 14 GTX[2]: A_TXELECIDLE bit 0	GTX[2]: DRP[33] bit 15 GTX[2]: PCI_EXPRESS_MODE
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[33] bit 12 GTX[2]: TX_DETECT_RX_CFG bit 12	GTX[2]: DRP[33] bit 13 GTX[2]: TX_DETECT_RX_CFG bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[33] bit 10 GTX[2]: TX_DETECT_RX_CFG bit 10	GTX[2]: DRP[33] bit 11 GTX[2]: TX_DETECT_RX_CFG bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[33] bit 8 GTX[2]: TX_DETECT_RX_CFG bit 8	GTX[2]: DRP[33] bit 9 GTX[2]: TX_DETECT_RX_CFG bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[33] bit 6 GTX[2]: TX_DETECT_RX_CFG bit 6	GTX[2]: DRP[33] bit 7 GTX[2]: TX_DETECT_RX_CFG bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[33] bit 4 GTX[2]: TX_DETECT_RX_CFG bit 4	GTX[2]: DRP[33] bit 5 GTX[2]: TX_DETECT_RX_CFG bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[33] bit 2 GTX[2]: TX_DETECT_RX_CFG bit 2	GTX[2]: DRP[33] bit 3 GTX[2]: TX_DETECT_RX_CFG bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[33] bit 0 GTX[2]: TX_DETECT_RX_CFG bit 0	GTX[2]: DRP[33] bit 1 GTX[2]: TX_DETECT_RX_CFG bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[32] bit 14 GTX[2]: A_TXPLLPOWERDOWN bit 0	GTX[2]: DRP[32] bit 15 GTX[2]: TX_OVERSAMPLE_MODE
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[32] bit 12 GTX[2]: A_PLLCLKTXRESET bit 0	GTX[2]: DRP[32] bit 13 GTX[2]: PDELIDLE_DRP_EN
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[32] bit 10 GTX[2]: A_PLLTXRESET bit 0	GTX[2]: DRP[32] bit 11 GTX[2]: A_TXPLLLKDETEN bit 0
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[32] bit 8 GTX[2]: TXPLLREFSEL_STATIC_VAL bit 1	GTX[2]: DRP[32] bit 9 GTX[2]: TXPLLREFSEL_STATIC_VAL bit 2
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[32] bit 6 GTX[2]: TXPLLREFSEL_MODE_DYNAMIC	GTX[2]: DRP[32] bit 7 GTX[2]: TXPLLREFSEL_STATIC_VAL bit 0
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[32] bit 4 GTX[2]: TXPLL_DIVSEL_REF bit 3	GTX[2]: DRP[32] bit 5 GTX[2]: TXPLL_DIVSEL_REF bit 4
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[32] bit 2 GTX[2]: TXPLL_DIVSEL_REF bit 1	GTX[2]: DRP[32] bit 3 GTX[2]: TXPLL_DIVSEL_REF bit 2
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[32] bit 0 GTX[2]: TXPLLREFSEL_TESTCLK bit 0	GTX[2]: DRP[32] bit 1 GTX[2]: TXPLL_DIVSEL_REF bit 0

virtex6 GTX rect MAIN[25]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[47] bit 14 GTX[2]: TX_XCLK_SEL bit 0	GTX[2]: DRP[47] bit 15 GTX[2]: TXGEARBOX_USE
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[47] bit 12 GTX[2]: TX_IDLE_ASSERT_DELAY bit 1	GTX[2]: DRP[47] bit 13 GTX[2]: TX_IDLE_ASSERT_DELAY bit 2
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[47] bit 10 GTX[2]: COMMA_DOUBLE	GTX[2]: DRP[47] bit 11 GTX[2]: TX_IDLE_ASSERT_DELAY bit 0
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[47] bit 8 GTX[2]: COMMA_10B_ENABLE bit 8	GTX[2]: DRP[47] bit 9 GTX[2]: COMMA_10B_ENABLE bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[47] bit 6 GTX[2]: COMMA_10B_ENABLE bit 6	GTX[2]: DRP[47] bit 7 GTX[2]: COMMA_10B_ENABLE bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[47] bit 4 GTX[2]: COMMA_10B_ENABLE bit 4	GTX[2]: DRP[47] bit 5 GTX[2]: COMMA_10B_ENABLE bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[47] bit 2 GTX[2]: COMMA_10B_ENABLE bit 2	GTX[2]: DRP[47] bit 3 GTX[2]: COMMA_10B_ENABLE bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[47] bit 0 GTX[2]: COMMA_10B_ENABLE bit 0	GTX[2]: DRP[47] bit 1 GTX[2]: COMMA_10B_ENABLE bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[46] bit 14 GTX[2]: DFE_CAL_TIME bit 3	GTX[2]: DRP[46] bit 15 GTX[2]: DFE_CAL_TIME bit 4
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[46] bit 12 GTX[2]: DFE_CAL_TIME bit 1	GTX[2]: DRP[46] bit 13 GTX[2]: DFE_CAL_TIME bit 2
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[46] bit 10 GTX[2]: RX_EYE_SCANMODE bit 1	GTX[2]: DRP[46] bit 11 GTX[2]: DFE_CAL_TIME bit 0
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[46] bit 8 GTX[2]: RCV_TERM_VTTRX	GTX[2]: DRP[46] bit 9 GTX[2]: RX_EYE_SCANMODE bit 0
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[46] bit 6 GTX[2]: TERMINATION_OVRD	GTX[2]: DRP[46] bit 7 GTX[2]: RCV_TERM_GND
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[46] bit 4 GTX[2]: TERMINATION_CTRL bit 4	GTX[2]: DRP[46] bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[46] bit 2 GTX[2]: TERMINATION_CTRL bit 2	GTX[2]: DRP[46] bit 3 GTX[2]: TERMINATION_CTRL bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[46] bit 0 GTX[2]: TERMINATION_CTRL bit 0	GTX[2]: DRP[46] bit 1 GTX[2]: TERMINATION_CTRL bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[45] bit 14 GTX[2]: RX_EYE_OFFSET bit 6	GTX[2]: DRP[45] bit 15 GTX[2]: RX_EYE_OFFSET bit 7
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[45] bit 12 GTX[2]: RX_EYE_OFFSET bit 4	GTX[2]: DRP[45] bit 13 GTX[2]: RX_EYE_OFFSET bit 5
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[45] bit 10 GTX[2]: RX_EYE_OFFSET bit 2	GTX[2]: DRP[45] bit 11 GTX[2]: RX_EYE_OFFSET bit 3
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[45] bit 8 GTX[2]: RX_EYE_OFFSET bit 0	GTX[2]: DRP[45] bit 9 GTX[2]: RX_EYE_OFFSET bit 1
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[45] bit 6 GTX[2]: DFE_CFG bit 6	GTX[2]: DRP[45] bit 7 GTX[2]: DFE_CFG bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[45] bit 4 GTX[2]: DFE_CFG bit 4	GTX[2]: DRP[45] bit 5 GTX[2]: DFE_CFG bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[45] bit 2 GTX[2]: DFE_CFG bit 2	GTX[2]: DRP[45] bit 3 GTX[2]: DFE_CFG bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[45] bit 0 GTX[2]: DFE_CFG bit 0	GTX[2]: DRP[45] bit 1 GTX[2]: DFE_CFG bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[44] bit 14 GTX[2]: A_DFECLKDLYADJ bit 5	GTX[2]: DRP[44] bit 15 GTX[2]: DFE_DRP_EN
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[44] bit 12 GTX[2]: A_DFECLKDLYADJ bit 3	GTX[2]: DRP[44] bit 13 GTX[2]: A_DFECLKDLYADJ bit 4
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[44] bit 10 GTX[2]: A_DFECLKDLYADJ bit 1	GTX[2]: DRP[44] bit 11 GTX[2]: A_DFECLKDLYADJ bit 2
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[44] bit 8 GTX[2]: A_DFETAP4 bit 3	GTX[2]: DRP[44] bit 9 GTX[2]: A_DFECLKDLYADJ bit 0
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[44] bit 6 GTX[2]: A_DFETAP4 bit 1	GTX[2]: DRP[44] bit 7 GTX[2]: A_DFETAP4 bit 2
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[44] bit 4 GTX[2]: A_DFETAP2 bit 4	GTX[2]: DRP[44] bit 5 GTX[2]: A_DFETAP4 bit 0
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[44] bit 2 GTX[2]: A_DFETAP2 bit 2	GTX[2]: DRP[44] bit 3 GTX[2]: A_DFETAP2 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[44] bit 0 GTX[2]: A_DFETAP2 bit 0	GTX[2]: DRP[44] bit 1 GTX[2]: A_DFETAP2 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[43] bit 14 GTX[2]: A_DFEDLYOVRD bit 0	GTX[2]: DRP[43] bit 15 GTX[2]: A_DFETAPOVRD bit 0
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[43] bit 12	GTX[2]: DRP[43] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[43] bit 10 GTX[2]: RX_EN_IDLE_RESET_FR	GTX[2]: DRP[43] bit 11 GTX[2]: RX_EN_IDLE_HOLD_DFE
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[43] bit 8 GTX[2]: A_DFETAP3 bit 3	GTX[2]: DRP[43] bit 9 GTX[2]: RX_EN_IDLE_HOLD_CDR
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[43] bit 6 GTX[2]: A_DFETAP3 bit 1	GTX[2]: DRP[43] bit 7 GTX[2]: A_DFETAP3 bit 2
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[43] bit 4 GTX[2]: A_DFETAP1 bit 4	GTX[2]: DRP[43] bit 5 GTX[2]: A_DFETAP3 bit 0
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[43] bit 2 GTX[2]: A_DFETAP1 bit 2	GTX[2]: DRP[43] bit 3 GTX[2]: A_DFETAP1 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[43] bit 0 GTX[2]: A_DFETAP1 bit 0	GTX[2]: DRP[43] bit 1 GTX[2]: A_DFETAP1 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[42] bit 14 GTX[2]: A_PRBSCNTRESET bit 0	GTX[2]: DRP[42] bit 15 GTX[2]: PRBS_DRP_EN
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[42] bit 12 GTX[2]: A_TXENPRBSTST bit 1	GTX[2]: DRP[42] bit 13 GTX[2]: A_TXENPRBSTST bit 2
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[42] bit 10 GTX[2]: A_TXPRBSFORCEERR bit 0	GTX[2]: DRP[42] bit 11 GTX[2]: A_TXENPRBSTST bit 0
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[42] bit 8 GTX[2]: RXPRBSERR_LOOPBACK bit 0	GTX[2]: DRP[42] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[42] bit 6 GTX[2]: A_RXENPRBSTST bit 1	GTX[2]: DRP[42] bit 7 GTX[2]: A_RXENPRBSTST bit 2
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[42] bit 4	GTX[2]: DRP[42] bit 5 GTX[2]: A_RXENPRBSTST bit 0
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[42] bit 2 GTX[2]: A_LOOPBACK bit 1	GTX[2]: DRP[42] bit 3 GTX[2]: A_LOOPBACK bit 2
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[42] bit 0 GTX[2]: LOOPBACK_DRP_EN	GTX[2]: DRP[42] bit 1 GTX[2]: A_LOOPBACK bit 0
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[41] bit 14 GTX[2]: A_RXENSAMPLEALIGN bit 0	GTX[2]: DRP[41] bit 15 GTX[2]: PHASEALIGN_DRP_EN
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[41] bit 12 GTX[2]: A_TXPMASETPHASE bit 0	GTX[2]: DRP[41] bit 13 GTX[2]: A_TXENPMAPHASEALIGN bit 0
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[41] bit 10 GTX[2]: SAS_MIN_COMSAS bit 4	GTX[2]: DRP[41] bit 11 GTX[2]: SAS_MIN_COMSAS bit 5
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[41] bit 8 GTX[2]: SAS_MIN_COMSAS bit 2	GTX[2]: DRP[41] bit 9 GTX[2]: SAS_MIN_COMSAS bit 3
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[41] bit 6 GTX[2]: SAS_MIN_COMSAS bit 0	GTX[2]: DRP[41] bit 7 GTX[2]: SAS_MIN_COMSAS bit 1
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[41] bit 4 GTX[2]: SAS_MAX_COMSAS bit 4	GTX[2]: DRP[41] bit 5 GTX[2]: SAS_MAX_COMSAS bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[41] bit 2 GTX[2]: SAS_MAX_COMSAS bit 2	GTX[2]: DRP[41] bit 3 GTX[2]: SAS_MAX_COMSAS bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[41] bit 0 GTX[2]: SAS_MAX_COMSAS bit 0	GTX[2]: DRP[41] bit 1 GTX[2]: SAS_MAX_COMSAS bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[40] bit 14 GTX[2]: SATA_BURST_VAL bit 2	GTX[2]: DRP[40] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[40] bit 12 GTX[2]: SATA_BURST_VAL bit 0	GTX[2]: DRP[40] bit 13 GTX[2]: SATA_BURST_VAL bit 1
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[40] bit 10 GTX[2]: SATA_MIN_BURST bit 4	GTX[2]: DRP[40] bit 11 GTX[2]: SATA_MIN_BURST bit 5
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[40] bit 8 GTX[2]: SATA_MIN_BURST bit 2	GTX[2]: DRP[40] bit 9 GTX[2]: SATA_MIN_BURST bit 3
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[40] bit 6 GTX[2]: SATA_MIN_BURST bit 0	GTX[2]: DRP[40] bit 7 GTX[2]: SATA_MIN_BURST bit 1
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[40] bit 4 GTX[2]: SATA_MAX_BURST bit 4	GTX[2]: DRP[40] bit 5 GTX[2]: SATA_MAX_BURST bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[40] bit 2 GTX[2]: SATA_MAX_BURST bit 2	GTX[2]: DRP[40] bit 3 GTX[2]: SATA_MAX_BURST bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[40] bit 0 GTX[2]: SATA_MAX_BURST bit 0	GTX[2]: DRP[40] bit 1 GTX[2]: SATA_MAX_BURST bit 1

virtex6 GTX rect MAIN[26]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[55] bit 14 GTX[2]: PMA_TX_CFG bit 14	GTX[2]: DRP[55] bit 15 GTX[2]: PMA_TX_CFG bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[55] bit 12 GTX[2]: PMA_TX_CFG bit 12	GTX[2]: DRP[55] bit 13 GTX[2]: PMA_TX_CFG bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[55] bit 10 GTX[2]: PMA_TX_CFG bit 10	GTX[2]: DRP[55] bit 11 GTX[2]: PMA_TX_CFG bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[55] bit 8 GTX[2]: PMA_TX_CFG bit 8	GTX[2]: DRP[55] bit 9 GTX[2]: PMA_TX_CFG bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[55] bit 6 GTX[2]: PMA_TX_CFG bit 6	GTX[2]: DRP[55] bit 7 GTX[2]: PMA_TX_CFG bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[55] bit 4 GTX[2]: PMA_TX_CFG bit 4	GTX[2]: DRP[55] bit 5 GTX[2]: PMA_TX_CFG bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[55] bit 2 GTX[2]: PMA_TX_CFG bit 2	GTX[2]: DRP[55] bit 3 GTX[2]: PMA_TX_CFG bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[55] bit 0 GTX[2]: PMA_TX_CFG bit 0	GTX[2]: DRP[55] bit 1 GTX[2]: PMA_TX_CFG bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[54] bit 14 GTX[2]: PMA_CFG bit 74	GTX[2]: DRP[54] bit 15 GTX[2]: PMA_CFG bit 75
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[54] bit 12 GTX[2]: PMA_CFG bit 72	GTX[2]: DRP[54] bit 13 GTX[2]: PMA_CFG bit 73
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[54] bit 10 GTX[2]: PMA_CFG bit 70	GTX[2]: DRP[54] bit 11 GTX[2]: PMA_CFG bit 71
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[54] bit 8 GTX[2]: PMA_CFG bit 68	GTX[2]: DRP[54] bit 9 GTX[2]: PMA_CFG bit 69
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[54] bit 6 GTX[2]: PMA_CFG bit 66	GTX[2]: DRP[54] bit 7 GTX[2]: PMA_CFG bit 67
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[54] bit 4 GTX[2]: PMA_CFG bit 64	GTX[2]: DRP[54] bit 5 GTX[2]: PMA_CFG bit 65
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[54] bit 2 GTX[2]: PMA_TX_CFG bit 18	GTX[2]: DRP[54] bit 3 GTX[2]: PMA_TX_CFG bit 19
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[54] bit 0 GTX[2]: PMA_TX_CFG bit 16	GTX[2]: DRP[54] bit 1 GTX[2]: PMA_TX_CFG bit 17
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[53] bit 14 GTX[2]: PMA_CFG bit 62	GTX[2]: DRP[53] bit 15 GTX[2]: PMA_CFG bit 63
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[53] bit 12 GTX[2]: PMA_CFG bit 60	GTX[2]: DRP[53] bit 13 GTX[2]: PMA_CFG bit 61
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[53] bit 10 GTX[2]: PMA_CFG bit 58	GTX[2]: DRP[53] bit 11 GTX[2]: PMA_CFG bit 59
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[53] bit 8 GTX[2]: PMA_CFG bit 56	GTX[2]: DRP[53] bit 9 GTX[2]: PMA_CFG bit 57
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[53] bit 6 GTX[2]: PMA_CFG bit 54	GTX[2]: DRP[53] bit 7 GTX[2]: PMA_CFG bit 55
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[53] bit 4 GTX[2]: PMA_CFG bit 52	GTX[2]: DRP[53] bit 5 GTX[2]: PMA_CFG bit 53
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[53] bit 2 GTX[2]: PMA_CFG bit 50	GTX[2]: DRP[53] bit 3 GTX[2]: PMA_CFG bit 51
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[53] bit 0 GTX[2]: PMA_CFG bit 48	GTX[2]: DRP[53] bit 1 GTX[2]: PMA_CFG bit 49
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[52] bit 14 GTX[2]: PMA_CFG bit 46	GTX[2]: DRP[52] bit 15 GTX[2]: PMA_CFG bit 47
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[52] bit 12 GTX[2]: PMA_CFG bit 44	GTX[2]: DRP[52] bit 13 GTX[2]: PMA_CFG bit 45
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[52] bit 10 GTX[2]: PMA_CFG bit 42	GTX[2]: DRP[52] bit 11 GTX[2]: PMA_CFG bit 43
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[52] bit 8 GTX[2]: PMA_CFG bit 40	GTX[2]: DRP[52] bit 9 GTX[2]: PMA_CFG bit 41
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[52] bit 6 GTX[2]: PMA_CFG bit 38	GTX[2]: DRP[52] bit 7 GTX[2]: PMA_CFG bit 39
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[52] bit 4 GTX[2]: PMA_CFG bit 36	GTX[2]: DRP[52] bit 5 GTX[2]: PMA_CFG bit 37
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[52] bit 2 GTX[2]: PMA_CFG bit 34	GTX[2]: DRP[52] bit 3 GTX[2]: PMA_CFG bit 35
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[52] bit 0 GTX[2]: PMA_CFG bit 32	GTX[2]: DRP[52] bit 1 GTX[2]: PMA_CFG bit 33
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[51] bit 14 GTX[2]: PMA_CFG bit 30	GTX[2]: DRP[51] bit 15 GTX[2]: PMA_CFG bit 31
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[51] bit 12 GTX[2]: PMA_CFG bit 28	GTX[2]: DRP[51] bit 13 GTX[2]: PMA_CFG bit 29
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[51] bit 10 GTX[2]: PMA_CFG bit 26	GTX[2]: DRP[51] bit 11 GTX[2]: PMA_CFG bit 27
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[51] bit 8 GTX[2]: PMA_CFG bit 24	GTX[2]: DRP[51] bit 9 GTX[2]: PMA_CFG bit 25
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[51] bit 6 GTX[2]: PMA_CFG bit 22	GTX[2]: DRP[51] bit 7 GTX[2]: PMA_CFG bit 23
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[51] bit 4 GTX[2]: PMA_CFG bit 20	GTX[2]: DRP[51] bit 5 GTX[2]: PMA_CFG bit 21
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[51] bit 2 GTX[2]: PMA_CFG bit 18	GTX[2]: DRP[51] bit 3 GTX[2]: PMA_CFG bit 19
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[51] bit 0 GTX[2]: PMA_CFG bit 16	GTX[2]: DRP[51] bit 1 GTX[2]: PMA_CFG bit 17
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[50] bit 14 GTX[2]: PMA_CFG bit 14	GTX[2]: DRP[50] bit 15 GTX[2]: PMA_CFG bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[50] bit 12 GTX[2]: PMA_CFG bit 12	GTX[2]: DRP[50] bit 13 GTX[2]: PMA_CFG bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[50] bit 10 GTX[2]: PMA_CFG bit 10	GTX[2]: DRP[50] bit 11 GTX[2]: PMA_CFG bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[50] bit 8 GTX[2]: PMA_CFG bit 8	GTX[2]: DRP[50] bit 9 GTX[2]: PMA_CFG bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[50] bit 6 GTX[2]: PMA_CFG bit 6	GTX[2]: DRP[50] bit 7 GTX[2]: PMA_CFG bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[50] bit 4 GTX[2]: PMA_CFG bit 4	GTX[2]: DRP[50] bit 5 GTX[2]: PMA_CFG bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[50] bit 2 GTX[2]: PMA_CFG bit 2	GTX[2]: DRP[50] bit 3 GTX[2]: PMA_CFG bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[50] bit 0 GTX[2]: PMA_CFG bit 0	GTX[2]: DRP[50] bit 1 GTX[2]: PMA_CFG bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[49] bit 14 GTX[2]: TX_DATA_WIDTH bit 2	GTX[2]: DRP[49] bit 15 GTX[2]: GEN_TXUSRCLK
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[49] bit 12 GTX[2]: TX_DATA_WIDTH bit 0	GTX[2]: DRP[49] bit 13 GTX[2]: TX_DATA_WIDTH bit 1
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[49] bit 10 GTX[2]: PCOMMA_DETECT	GTX[2]: DRP[49] bit 11 GTX[2]: TX_BUFFER_USE
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[49] bit 8 GTX[2]: PCOMMA_10B_VALUE bit 8	GTX[2]: DRP[49] bit 9 GTX[2]: PCOMMA_10B_VALUE bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[49] bit 6 GTX[2]: PCOMMA_10B_VALUE bit 6	GTX[2]: DRP[49] bit 7 GTX[2]: PCOMMA_10B_VALUE bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[49] bit 4 GTX[2]: PCOMMA_10B_VALUE bit 4	GTX[2]: DRP[49] bit 5 GTX[2]: PCOMMA_10B_VALUE bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[49] bit 2 GTX[2]: PCOMMA_10B_VALUE bit 2	GTX[2]: DRP[49] bit 3 GTX[2]: PCOMMA_10B_VALUE bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[49] bit 0 GTX[2]: PCOMMA_10B_VALUE bit 0	GTX[2]: DRP[49] bit 1 GTX[2]: PCOMMA_10B_VALUE bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: !invert TXUSRCLK GTX[2]: DRP[48] bit 14	GTX[2]: !invert TXUSRCLK2 GTX[2]: DRP[48] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[48] bit 12 GTX[2]: TX_IDLE_DEASSERT_DELAY bit 1	GTX[2]: DRP[48] bit 13 GTX[2]: TX_IDLE_DEASSERT_DELAY bit 2
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[48] bit 10 GTX[2]: MCOMMA_DETECT	GTX[2]: DRP[48] bit 11 GTX[2]: TX_IDLE_DEASSERT_DELAY bit 0
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[48] bit 8 GTX[2]: MCOMMA_10B_VALUE bit 8	GTX[2]: DRP[48] bit 9 GTX[2]: MCOMMA_10B_VALUE bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[48] bit 6 GTX[2]: MCOMMA_10B_VALUE bit 6	GTX[2]: DRP[48] bit 7 GTX[2]: MCOMMA_10B_VALUE bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[48] bit 4 GTX[2]: MCOMMA_10B_VALUE bit 4	GTX[2]: DRP[48] bit 5 GTX[2]: MCOMMA_10B_VALUE bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[48] bit 2 GTX[2]: MCOMMA_10B_VALUE bit 2	GTX[2]: DRP[48] bit 3 GTX[2]: MCOMMA_10B_VALUE bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[48] bit 0 GTX[2]: MCOMMA_10B_VALUE bit 0	GTX[2]: DRP[48] bit 1 GTX[2]: MCOMMA_10B_VALUE bit 1

virtex6 GTX rect MAIN[27]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[63] bit 14	GTX[2]: DRP[63] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[63] bit 12	GTX[2]: DRP[63] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[63] bit 10	GTX[2]: DRP[63] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[63] bit 8	GTX[2]: DRP[63] bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[63] bit 6 GTX[2]: TRANS_TIME_RATE bit 6	GTX[2]: DRP[63] bit 7 GTX[2]: TRANS_TIME_RATE bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[63] bit 4 GTX[2]: TRANS_TIME_RATE bit 4	GTX[2]: DRP[63] bit 5 GTX[2]: TRANS_TIME_RATE bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[63] bit 2 GTX[2]: TRANS_TIME_RATE bit 2	GTX[2]: DRP[63] bit 3 GTX[2]: TRANS_TIME_RATE bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[63] bit 0 GTX[2]: TRANS_TIME_RATE bit 0	GTX[2]: DRP[63] bit 1 GTX[2]: TRANS_TIME_RATE bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[62] bit 14 GTX[2]: A_TXMARGIN bit 1	GTX[2]: DRP[62] bit 15 GTX[2]: A_TXMARGIN bit 2
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[62] bit 12	GTX[2]: DRP[62] bit 13 GTX[2]: A_TXMARGIN bit 0
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[62] bit 10	GTX[2]: DRP[62] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[62] bit 8 GTX[2]: TX_DEEMPH_1 bit 3	GTX[2]: DRP[62] bit 9 GTX[2]: TX_DEEMPH_1 bit 4
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[62] bit 6 GTX[2]: TX_DEEMPH_1 bit 1	GTX[2]: DRP[62] bit 7 GTX[2]: TX_DEEMPH_1 bit 2
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[62] bit 4 GTX[2]: TX_DEEMPH_0 bit 4	GTX[2]: DRP[62] bit 5 GTX[2]: TX_DEEMPH_1 bit 0
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[62] bit 2 GTX[2]: TX_DEEMPH_0 bit 2	GTX[2]: DRP[62] bit 3 GTX[2]: TX_DEEMPH_0 bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[62] bit 0 GTX[2]: TX_DEEMPH_0 bit 0	GTX[2]: DRP[62] bit 1 GTX[2]: TX_DEEMPH_0 bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[61] bit 14 GTX[2]: A_TXPOSTEMPHASIS bit 3	GTX[2]: DRP[61] bit 15 GTX[2]: A_TXPOSTEMPHASIS bit 4
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[61] bit 12 GTX[2]: A_TXPOSTEMPHASIS bit 1	GTX[2]: DRP[61] bit 13 GTX[2]: A_TXPOSTEMPHASIS bit 2
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[61] bit 10 GTX[2]: A_TXPREEMPHASIS bit 3	GTX[2]: DRP[61] bit 11 GTX[2]: A_TXPOSTEMPHASIS bit 0
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[61] bit 8 GTX[2]: A_TXPREEMPHASIS bit 1	GTX[2]: DRP[61] bit 9 GTX[2]: A_TXPREEMPHASIS bit 2
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[61] bit 6 GTX[2]: A_TXBUFDIFFCTRL bit 2	GTX[2]: DRP[61] bit 7 GTX[2]: A_TXPREEMPHASIS bit 0
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[61] bit 4 GTX[2]: A_TXBUFDIFFCTRL bit 0	GTX[2]: DRP[61] bit 5 GTX[2]: A_TXBUFDIFFCTRL bit 1
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[61] bit 2 GTX[2]: A_TXDIFFCTRL bit 2	GTX[2]: DRP[61] bit 3 GTX[2]: A_TXDIFFCTRL bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[61] bit 0 GTX[2]: A_TXDIFFCTRL bit 0	GTX[2]: DRP[61] bit 1 GTX[2]: A_TXDIFFCTRL bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[60] bit 14 GTX[2]: TXDRIVE_DRP_EN	GTX[2]: DRP[60] bit 15 GTX[2]: TX_DRIVE_MODE bit 0
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[60] bit 12 GTX[2]: TX_MARGIN_FULL_4 bit 5	GTX[2]: DRP[60] bit 13 GTX[2]: TX_MARGIN_FULL_4 bit 6
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[60] bit 10 GTX[2]: TX_MARGIN_FULL_4 bit 3	GTX[2]: DRP[60] bit 11 GTX[2]: TX_MARGIN_FULL_4 bit 4
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[60] bit 8 GTX[2]: TX_MARGIN_FULL_4 bit 1	GTX[2]: DRP[60] bit 9 GTX[2]: TX_MARGIN_FULL_4 bit 2
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[60] bit 6 GTX[2]: TX_MARGIN_LOW_4 bit 6	GTX[2]: DRP[60] bit 7 GTX[2]: TX_MARGIN_FULL_4 bit 0
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[60] bit 4 GTX[2]: TX_MARGIN_LOW_4 bit 4	GTX[2]: DRP[60] bit 5 GTX[2]: TX_MARGIN_LOW_4 bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[60] bit 2 GTX[2]: TX_MARGIN_LOW_4 bit 2	GTX[2]: DRP[60] bit 3 GTX[2]: TX_MARGIN_LOW_4 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[60] bit 0 GTX[2]: TX_MARGIN_LOW_4 bit 0	GTX[2]: DRP[60] bit 1 GTX[2]: TX_MARGIN_LOW_4 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[59] bit 14 GTX[2]: A_TXSWING bit 0	GTX[2]: DRP[59] bit 15 GTX[2]: A_TXDEEMPH bit 0
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[59] bit 12 GTX[2]: TX_MARGIN_FULL_3 bit 5	GTX[2]: DRP[59] bit 13 GTX[2]: TX_MARGIN_FULL_3 bit 6
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[59] bit 10 GTX[2]: TX_MARGIN_FULL_3 bit 3	GTX[2]: DRP[59] bit 11 GTX[2]: TX_MARGIN_FULL_3 bit 4
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[59] bit 8 GTX[2]: TX_MARGIN_FULL_3 bit 1	GTX[2]: DRP[59] bit 9 GTX[2]: TX_MARGIN_FULL_3 bit 2
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[59] bit 6 GTX[2]: TX_MARGIN_LOW_3 bit 6	GTX[2]: DRP[59] bit 7 GTX[2]: TX_MARGIN_FULL_3 bit 0
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[59] bit 4 GTX[2]: TX_MARGIN_LOW_3 bit 4	GTX[2]: DRP[59] bit 5 GTX[2]: TX_MARGIN_LOW_3 bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[59] bit 2 GTX[2]: TX_MARGIN_LOW_3 bit 2	GTX[2]: DRP[59] bit 3 GTX[2]: TX_MARGIN_LOW_3 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[59] bit 0 GTX[2]: TX_MARGIN_LOW_3 bit 0	GTX[2]: DRP[59] bit 1 GTX[2]: TX_MARGIN_LOW_3 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[58] bit 14 GTX[2]: ! TXDRIVE_LOOPBACK_HIZ	GTX[2]: DRP[58] bit 15 GTX[2]: ! TXDRIVE_LOOPBACK_PD
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[58] bit 12 GTX[2]: TX_MARGIN_FULL_2 bit 5	GTX[2]: DRP[58] bit 13 GTX[2]: TX_MARGIN_FULL_2 bit 6
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[58] bit 10 GTX[2]: TX_MARGIN_FULL_2 bit 3	GTX[2]: DRP[58] bit 11 GTX[2]: TX_MARGIN_FULL_2 bit 4
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[58] bit 8 GTX[2]: TX_MARGIN_FULL_2 bit 1	GTX[2]: DRP[58] bit 9 GTX[2]: TX_MARGIN_FULL_2 bit 2
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[58] bit 6 GTX[2]: TX_MARGIN_LOW_2 bit 6	GTX[2]: DRP[58] bit 7 GTX[2]: TX_MARGIN_FULL_2 bit 0
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[58] bit 4 GTX[2]: TX_MARGIN_LOW_2 bit 4	GTX[2]: DRP[58] bit 5 GTX[2]: TX_MARGIN_LOW_2 bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[58] bit 2 GTX[2]: TX_MARGIN_LOW_2 bit 2	GTX[2]: DRP[58] bit 3 GTX[2]: TX_MARGIN_LOW_2 bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[58] bit 0 GTX[2]: TX_MARGIN_LOW_2 bit 0	GTX[2]: DRP[58] bit 1 GTX[2]: TX_MARGIN_LOW_2 bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[57] bit 14 GTX[2]: TX_TDCC_CFG bit 0	GTX[2]: DRP[57] bit 15 GTX[2]: TX_TDCC_CFG bit 1
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[57] bit 12 GTX[2]: TX_MARGIN_FULL_1 bit 5	GTX[2]: DRP[57] bit 13 GTX[2]: TX_MARGIN_FULL_1 bit 6
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[57] bit 10 GTX[2]: TX_MARGIN_FULL_1 bit 3	GTX[2]: DRP[57] bit 11 GTX[2]: TX_MARGIN_FULL_1 bit 4
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[57] bit 8 GTX[2]: TX_MARGIN_FULL_1 bit 1	GTX[2]: DRP[57] bit 9 GTX[2]: TX_MARGIN_FULL_1 bit 2
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[57] bit 6 GTX[2]: TX_MARGIN_LOW_1 bit 6	GTX[2]: DRP[57] bit 7 GTX[2]: TX_MARGIN_FULL_1 bit 0
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[57] bit 4 GTX[2]: TX_MARGIN_LOW_1 bit 4	GTX[2]: DRP[57] bit 5 GTX[2]: TX_MARGIN_LOW_1 bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[57] bit 2 GTX[2]: TX_MARGIN_LOW_1 bit 2	GTX[2]: DRP[57] bit 3 GTX[2]: TX_MARGIN_LOW_1 bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[57] bit 0 GTX[2]: TX_MARGIN_LOW_1 bit 0	GTX[2]: DRP[57] bit 1 GTX[2]: TX_MARGIN_LOW_1 bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[56] bit 14 GTX[2]: TXOUTCLKPCS_SEL bit 0	GTX[2]: !invert DCLK GTX[2]: DRP[56] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[56] bit 12 GTX[2]: TX_MARGIN_FULL_0 bit 5	GTX[2]: DRP[56] bit 13 GTX[2]: TX_MARGIN_FULL_0 bit 6
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[56] bit 10 GTX[2]: TX_MARGIN_FULL_0 bit 3	GTX[2]: DRP[56] bit 11 GTX[2]: TX_MARGIN_FULL_0 bit 4
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[56] bit 8 GTX[2]: TX_MARGIN_FULL_0 bit 1	GTX[2]: DRP[56] bit 9 GTX[2]: TX_MARGIN_FULL_0 bit 2
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[56] bit 6 GTX[2]: TX_MARGIN_LOW_0 bit 6	GTX[2]: DRP[56] bit 7 GTX[2]: TX_MARGIN_FULL_0 bit 0
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[56] bit 4 GTX[2]: TX_MARGIN_LOW_0 bit 4	GTX[2]: DRP[56] bit 5 GTX[2]: TX_MARGIN_LOW_0 bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[56] bit 2 GTX[2]: TX_MARGIN_LOW_0 bit 2	GTX[2]: DRP[56] bit 3 GTX[2]: TX_MARGIN_LOW_0 bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[56] bit 0 GTX[2]: TX_MARGIN_LOW_0 bit 0	GTX[2]: DRP[56] bit 1 GTX[2]: TX_MARGIN_LOW_0 bit 1

virtex6 GTX rect MAIN[28]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[71] bit 14	GTX[2]: DRP[71] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[71] bit 12	GTX[2]: DRP[71] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[71] bit 10	GTX[2]: DRP[71] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[71] bit 8 GTX[2]: TXOUTCLK_DLY bit 8	GTX[2]: DRP[71] bit 9 GTX[2]: TXOUTCLK_DLY bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[71] bit 6 GTX[2]: TXOUTCLK_DLY bit 6	GTX[2]: DRP[71] bit 7 GTX[2]: TXOUTCLK_DLY bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[71] bit 4 GTX[2]: TXOUTCLK_DLY bit 4	GTX[2]: DRP[71] bit 5 GTX[2]: TXOUTCLK_DLY bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[71] bit 2 GTX[2]: TXOUTCLK_DLY bit 2	GTX[2]: DRP[71] bit 3 GTX[2]: TXOUTCLK_DLY bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[71] bit 0 GTX[2]: TXOUTCLK_DLY bit 0	GTX[2]: DRP[71] bit 1 GTX[2]: TXOUTCLK_DLY bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[70] bit 14	GTX[2]: DRP[70] bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[70] bit 12	GTX[2]: DRP[70] bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[70] bit 10	GTX[2]: DRP[70] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[70] bit 8 GTX[2]: RXRECCLK_DLY bit 8	GTX[2]: DRP[70] bit 9 GTX[2]: RXRECCLK_DLY bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[70] bit 6 GTX[2]: RXRECCLK_DLY bit 6	GTX[2]: DRP[70] bit 7 GTX[2]: RXRECCLK_DLY bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[70] bit 4 GTX[2]: RXRECCLK_DLY bit 4	GTX[2]: DRP[70] bit 5 GTX[2]: RXRECCLK_DLY bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[70] bit 2 GTX[2]: RXRECCLK_DLY bit 2	GTX[2]: DRP[70] bit 3 GTX[2]: RXRECCLK_DLY bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[70] bit 0 GTX[2]: RXRECCLK_DLY bit 0	GTX[2]: DRP[70] bit 1 GTX[2]: RXRECCLK_DLY bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[69] bit 14	GTX[2]: DRP[69] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[69] bit 12	GTX[2]: DRP[69] bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[69] bit 10 GTX[2]: TX_USRCLK_CFG bit 4	GTX[2]: DRP[69] bit 11 GTX[2]: TX_USRCLK_CFG bit 5
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[69] bit 8 GTX[2]: TX_USRCLK_CFG bit 2	GTX[2]: DRP[69] bit 9 GTX[2]: TX_USRCLK_CFG bit 3
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[69] bit 6 GTX[2]: TX_USRCLK_CFG bit 0	GTX[2]: DRP[69] bit 7 GTX[2]: TX_USRCLK_CFG bit 1
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[69] bit 4 GTX[2]: TX_BYTECLK_CFG bit 4	GTX[2]: DRP[69] bit 5 GTX[2]: TX_BYTECLK_CFG bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[69] bit 2 GTX[2]: TX_BYTECLK_CFG bit 2	GTX[2]: DRP[69] bit 3 GTX[2]: TX_BYTECLK_CFG bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[69] bit 0 GTX[2]: TX_BYTECLK_CFG bit 0	GTX[2]: DRP[69] bit 1 GTX[2]: TX_BYTECLK_CFG bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[68] bit 14	GTX[2]: DRP[68] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[68] bit 12	GTX[2]: DRP[68] bit 13
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[68] bit 10	GTX[2]: DRP[68] bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[68] bit 8 GTX[2]: POWER_SAVE bit 8	GTX[2]: DRP[68] bit 9 GTX[2]: POWER_SAVE bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[68] bit 6 GTX[2]: POWER_SAVE bit 6	GTX[2]: DRP[68] bit 7 GTX[2]: POWER_SAVE bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[68] bit 4 GTX[2]: POWER_SAVE bit 4	GTX[2]: DRP[68] bit 5 GTX[2]: POWER_SAVE bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[68] bit 2 GTX[2]: POWER_SAVE bit 2	GTX[2]: DRP[68] bit 3 GTX[2]: POWER_SAVE bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[68] bit 0 GTX[2]: POWER_SAVE bit 0	GTX[2]: DRP[68] bit 1 GTX[2]: POWER_SAVE bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: !invert GREFCLKTX GTX[2]: DRP[67] bit 14	GTX[2]: !invert GREFCLKRX GTX[2]: DRP[67] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[67] bit 12	GTX[2]: !invert SCANCLK GTX[2]: DRP[67] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: !invert TSTCLK[0] GTX[2]: DRP[67] bit 10	GTX[2]: !invert TSTCLK[1] GTX[2]: DRP[67] bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[67] bit 8	GTX[2]: DRP[67] bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[67] bit 6	GTX[2]: DRP[67] bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[67] bit 4 GTX[2]: RXRECCLK_CTRL bit 1	GTX[2]: DRP[67] bit 5 GTX[2]: RXRECCLK_CTRL bit 2
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[67] bit 2 GTX[2]: TXOUTCLK_CTRL bit 2	GTX[2]: DRP[67] bit 3 GTX[2]: RXRECCLK_CTRL bit 0
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[67] bit 0 GTX[2]: TXOUTCLK_CTRL bit 0	GTX[2]: DRP[67] bit 1 GTX[2]: TXOUTCLK_CTRL bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[66] bit 14 GTX[2]: TST_ATTR bit 14	GTX[2]: DRP[66] bit 15 GTX[2]: TST_ATTR bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[66] bit 12 GTX[2]: TST_ATTR bit 12	GTX[2]: DRP[66] bit 13 GTX[2]: TST_ATTR bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[66] bit 10 GTX[2]: TST_ATTR bit 10	GTX[2]: DRP[66] bit 11 GTX[2]: TST_ATTR bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[66] bit 8 GTX[2]: TST_ATTR bit 8	GTX[2]: DRP[66] bit 9 GTX[2]: TST_ATTR bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[66] bit 6 GTX[2]: TST_ATTR bit 6	GTX[2]: DRP[66] bit 7 GTX[2]: TST_ATTR bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[66] bit 4 GTX[2]: TST_ATTR bit 4	GTX[2]: DRP[66] bit 5 GTX[2]: TST_ATTR bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[66] bit 2 GTX[2]: TST_ATTR bit 2	GTX[2]: DRP[66] bit 3 GTX[2]: TST_ATTR bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[66] bit 0 GTX[2]: TST_ATTR bit 0	GTX[2]: DRP[66] bit 1 GTX[2]: TST_ATTR bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[65] bit 14 GTX[2]: TST_ATTR bit 30	GTX[2]: DRP[65] bit 15 GTX[2]: TST_ATTR bit 31
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[65] bit 12 GTX[2]: TST_ATTR bit 28	GTX[2]: DRP[65] bit 13 GTX[2]: TST_ATTR bit 29
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[65] bit 10 GTX[2]: TST_ATTR bit 26	GTX[2]: DRP[65] bit 11 GTX[2]: TST_ATTR bit 27
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[65] bit 8 GTX[2]: TST_ATTR bit 24	GTX[2]: DRP[65] bit 9 GTX[2]: TST_ATTR bit 25
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[65] bit 6 GTX[2]: TST_ATTR bit 22	GTX[2]: DRP[65] bit 7 GTX[2]: TST_ATTR bit 23
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[65] bit 4 GTX[2]: TST_ATTR bit 20	GTX[2]: DRP[65] bit 5 GTX[2]: TST_ATTR bit 21
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[65] bit 2 GTX[2]: TST_ATTR bit 18	GTX[2]: DRP[65] bit 3 GTX[2]: TST_ATTR bit 19
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[65] bit 0 GTX[2]: TST_ATTR bit 16	GTX[2]: DRP[65] bit 1 GTX[2]: TST_ATTR bit 17
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[64] bit 14	GTX[2]: DRP[64] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[64] bit 12	GTX[2]: DRP[64] bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[64] bit 10	GTX[2]: DRP[64] bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[64] bit 8 GTX[2]: A_RXEQMIX bit 8	GTX[2]: DRP[64] bit 9 GTX[2]: A_RXEQMIX bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[64] bit 6 GTX[2]: A_RXEQMIX bit 6	GTX[2]: DRP[64] bit 7 GTX[2]: A_RXEQMIX bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[64] bit 4 GTX[2]: A_RXEQMIX bit 4	GTX[2]: DRP[64] bit 5 GTX[2]: A_RXEQMIX bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[64] bit 2 GTX[2]: A_RXEQMIX bit 2	GTX[2]: DRP[64] bit 3 GTX[2]: A_RXEQMIX bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[64] bit 0 GTX[2]: A_RXEQMIX bit 0	GTX[2]: DRP[64] bit 1 GTX[2]: A_RXEQMIX bit 1

virtex6 GTX rect MAIN[29]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[79] bit 14	GTX[2]: DRP[79] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[79] bit 12	GTX[2]: DRP[79] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[79] bit 10	GTX[2]: DRP[79] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[79] bit 8	GTX[2]: DRP[79] bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[79] bit 6	GTX[2]: DRP[79] bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[79] bit 4	GTX[2]: DRP[79] bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[79] bit 2	GTX[2]: DRP[79] bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[79] bit 0	GTX[2]: DRP[79] bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[78] bit 14	GTX[2]: DRP[78] bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[78] bit 12	GTX[2]: DRP[78] bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[78] bit 10	GTX[2]: DRP[78] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[78] bit 8	GTX[2]: DRP[78] bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[78] bit 6	GTX[2]: DRP[78] bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[78] bit 4	GTX[2]: DRP[78] bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[78] bit 2	GTX[2]: DRP[78] bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[78] bit 0	GTX[2]: DRP[78] bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[77] bit 14 GTX[2]: RX_DLYALIGN_OVRDSETTING bit 6	GTX[2]: DRP[77] bit 15 GTX[2]: RX_DLYALIGN_OVRDSETTING bit 7
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[77] bit 12 GTX[2]: RX_DLYALIGN_OVRDSETTING bit 4	GTX[2]: DRP[77] bit 13 GTX[2]: RX_DLYALIGN_OVRDSETTING bit 5
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[77] bit 10 GTX[2]: RX_DLYALIGN_OVRDSETTING bit 2	GTX[2]: DRP[77] bit 11 GTX[2]: RX_DLYALIGN_OVRDSETTING bit 3
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[77] bit 8 GTX[2]: RX_DLYALIGN_OVRDSETTING bit 0	GTX[2]: DRP[77] bit 9 GTX[2]: RX_DLYALIGN_OVRDSETTING bit 1
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[77] bit 6 GTX[2]: RX_DLYALIGN_LPFINC bit 2	GTX[2]: DRP[77] bit 7 GTX[2]: RX_DLYALIGN_LPFINC bit 3
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[77] bit 4 GTX[2]: RX_DLYALIGN_LPFINC bit 0	GTX[2]: DRP[77] bit 5 GTX[2]: RX_DLYALIGN_LPFINC bit 1
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[77] bit 2 GTX[2]: RX_DLYALIGN_CTRINC bit 2	GTX[2]: DRP[77] bit 3 GTX[2]: RX_DLYALIGN_CTRINC bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[77] bit 0 GTX[2]: RX_DLYALIGN_CTRINC bit 0	GTX[2]: DRP[77] bit 1 GTX[2]: RX_DLYALIGN_CTRINC bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[76] bit 14 GTX[2]: TX_DLYALIGN_OVRDSETTING bit 6	GTX[2]: DRP[76] bit 15 GTX[2]: TX_DLYALIGN_OVRDSETTING bit 7
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[76] bit 12 GTX[2]: TX_DLYALIGN_OVRDSETTING bit 4	GTX[2]: DRP[76] bit 13 GTX[2]: TX_DLYALIGN_OVRDSETTING bit 5
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[76] bit 10 GTX[2]: TX_DLYALIGN_OVRDSETTING bit 2	GTX[2]: DRP[76] bit 11 GTX[2]: TX_DLYALIGN_OVRDSETTING bit 3
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[76] bit 8 GTX[2]: TX_DLYALIGN_OVRDSETTING bit 0	GTX[2]: DRP[76] bit 9 GTX[2]: TX_DLYALIGN_OVRDSETTING bit 1
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[76] bit 6 GTX[2]: TX_DLYALIGN_LPFINC bit 2	GTX[2]: DRP[76] bit 7 GTX[2]: TX_DLYALIGN_LPFINC bit 3
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[76] bit 4 GTX[2]: TX_DLYALIGN_LPFINC bit 0	GTX[2]: DRP[76] bit 5 GTX[2]: TX_DLYALIGN_LPFINC bit 1
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[76] bit 2 GTX[2]: TX_DLYALIGN_CTRINC bit 2	GTX[2]: DRP[76] bit 3 GTX[2]: TX_DLYALIGN_CTRINC bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[76] bit 0 GTX[2]: TX_DLYALIGN_CTRINC bit 0	GTX[2]: DRP[76] bit 1 GTX[2]: TX_DLYALIGN_CTRINC bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[75] bit 14 GTX[2]: RX_EN_REALIGN_RESET_BUF2	GTX[2]: DRP[75] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[75] bit 12	GTX[2]: DRP[75] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[75] bit 10 GTX[2]: RX_DLYALIGN_EDGESET bit 4	GTX[2]: DRP[75] bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[75] bit 8 GTX[2]: RX_DLYALIGN_EDGESET bit 2	GTX[2]: DRP[75] bit 9 GTX[2]: RX_DLYALIGN_EDGESET bit 3
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[75] bit 6 GTX[2]: RX_DLYALIGN_EDGESET bit 0	GTX[2]: DRP[75] bit 7 GTX[2]: RX_DLYALIGN_EDGESET bit 1
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[75] bit 4 GTX[2]: TX_DLYALIGN_MONSEL bit 1	GTX[2]: DRP[75] bit 5 GTX[2]: TX_DLYALIGN_MONSEL bit 2
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[75] bit 2 GTX[2]: RX_DLYALIGN_MONSEL bit 2	GTX[2]: DRP[75] bit 3 GTX[2]: TX_DLYALIGN_MONSEL bit 0
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[75] bit 0 GTX[2]: RX_DLYALIGN_MONSEL bit 0	GTX[2]: DRP[75] bit 1 GTX[2]: RX_DLYALIGN_MONSEL bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[74] bit 14	GTX[2]: DRP[74] bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[74] bit 12	GTX[2]: DRP[74] bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[74] bit 10	GTX[2]: DRP[74] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[74] bit 8	GTX[2]: DRP[74] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[74] bit 6	GTX[2]: DRP[74] bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[74] bit 4	GTX[2]: DRP[74] bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[74] bit 2	GTX[2]: DRP[74] bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[74] bit 0	GTX[2]: DRP[74] bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[73] bit 14	GTX[2]: DRP[73] bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[73] bit 12	GTX[2]: DRP[73] bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[73] bit 10	GTX[2]: DRP[73] bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[73] bit 8	GTX[2]: DRP[73] bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[73] bit 6	GTX[2]: DRP[73] bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[73] bit 4	GTX[2]: DRP[73] bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[73] bit 2	GTX[2]: DRP[73] bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[73] bit 0	GTX[2]: DRP[73] bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[72] bit 14	GTX[2]: DRP[72] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[72] bit 12	GTX[2]: DRP[72] bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[72] bit 10	GTX[2]: DRP[72] bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[72] bit 8	GTX[2]: DRP[72] bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[72] bit 6	GTX[2]: DRP[72] bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[72] bit 4	GTX[2]: DRP[72] bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[72] bit 2	GTX[2]: DRP[72] bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[2]: DRP[72] bit 0	GTX[2]: DRP[72] bit 1

virtex6 GTX rect MAIN[30]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[7] bit 14 GTX[3]: RX_IDLE_LO_CNT bit 2	GTX[3]: DRP[7] bit 15 GTX[3]: RX_IDLE_LO_CNT bit 3
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[7] bit 12 GTX[3]: RX_IDLE_LO_CNT bit 0	GTX[3]: DRP[7] bit 13 GTX[3]: RX_IDLE_LO_CNT bit 1
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[7] bit 10 GTX[3]: CHAN_BOND_SEQ_LEN bit 0	GTX[3]: DRP[7] bit 11 GTX[3]: CHAN_BOND_SEQ_LEN bit 1
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[7] bit 8 GTX[3]: CHAN_BOND_SEQ_1_4 bit 8	GTX[3]: DRP[7] bit 9 GTX[3]: CHAN_BOND_SEQ_1_4 bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[7] bit 6 GTX[3]: CHAN_BOND_SEQ_1_4 bit 6	GTX[3]: DRP[7] bit 7 GTX[3]: CHAN_BOND_SEQ_1_4 bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[7] bit 4 GTX[3]: CHAN_BOND_SEQ_1_4 bit 4	GTX[3]: DRP[7] bit 5 GTX[3]: CHAN_BOND_SEQ_1_4 bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[7] bit 2 GTX[3]: CHAN_BOND_SEQ_1_4 bit 2	GTX[3]: DRP[7] bit 3 GTX[3]: CHAN_BOND_SEQ_1_4 bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[7] bit 0 GTX[3]: CHAN_BOND_SEQ_1_4 bit 0	GTX[3]: DRP[7] bit 1 GTX[3]: CHAN_BOND_SEQ_1_4 bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[6] bit 14 GTX[3]: RX_LOS_INVALID_INCR bit 1	GTX[3]: DRP[6] bit 15 GTX[3]: RX_LOS_INVALID_INCR bit 2
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[6] bit 12 GTX[3]: RX_LOS_THRESHOLD bit 2	GTX[3]: DRP[6] bit 13 GTX[3]: RX_LOS_INVALID_INCR bit 0
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[6] bit 10 GTX[3]: RX_LOS_THRESHOLD bit 0	GTX[3]: DRP[6] bit 11 GTX[3]: RX_LOS_THRESHOLD bit 1
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[6] bit 8 GTX[3]: CHAN_BOND_SEQ_1_3 bit 8	GTX[3]: DRP[6] bit 9 GTX[3]: CHAN_BOND_SEQ_1_3 bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[6] bit 6 GTX[3]: CHAN_BOND_SEQ_1_3 bit 6	GTX[3]: DRP[6] bit 7 GTX[3]: CHAN_BOND_SEQ_1_3 bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[6] bit 4 GTX[3]: CHAN_BOND_SEQ_1_3 bit 4	GTX[3]: DRP[6] bit 5 GTX[3]: CHAN_BOND_SEQ_1_3 bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[6] bit 2 GTX[3]: CHAN_BOND_SEQ_1_3 bit 2	GTX[3]: DRP[6] bit 3 GTX[3]: CHAN_BOND_SEQ_1_3 bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[6] bit 0 GTX[3]: CHAN_BOND_SEQ_1_3 bit 0	GTX[3]: DRP[6] bit 1 GTX[3]: CHAN_BOND_SEQ_1_3 bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: !invert RXUSRCLK GTX[3]: DRP[5] bit 14	GTX[3]: !invert RXUSRCLK2 GTX[3]: DRP[5] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[5] bit 12 GTX[3]: CHAN_BOND_1_MAX_SKEW bit 2	GTX[3]: DRP[5] bit 13 GTX[3]: CHAN_BOND_1_MAX_SKEW bit 3
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[5] bit 10 GTX[3]: CHAN_BOND_1_MAX_SKEW bit 0	GTX[3]: DRP[5] bit 11 GTX[3]: CHAN_BOND_1_MAX_SKEW bit 1
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[5] bit 8 GTX[3]: CHAN_BOND_SEQ_1_2 bit 8	GTX[3]: DRP[5] bit 9 GTX[3]: CHAN_BOND_SEQ_1_2 bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[5] bit 6 GTX[3]: CHAN_BOND_SEQ_1_2 bit 6	GTX[3]: DRP[5] bit 7 GTX[3]: CHAN_BOND_SEQ_1_2 bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[5] bit 4 GTX[3]: CHAN_BOND_SEQ_1_2 bit 4	GTX[3]: DRP[5] bit 5 GTX[3]: CHAN_BOND_SEQ_1_2 bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[5] bit 2 GTX[3]: CHAN_BOND_SEQ_1_2 bit 2	GTX[3]: DRP[5] bit 3 GTX[3]: CHAN_BOND_SEQ_1_2 bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[5] bit 0 GTX[3]: CHAN_BOND_SEQ_1_2 bit 0	GTX[3]: DRP[5] bit 1 GTX[3]: CHAN_BOND_SEQ_1_2 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[4] bit 14 GTX[3]: RX_BUFFER_USE	GTX[3]: DRP[4] bit 15 GTX[3]: RX_LOSS_OF_SYNC_FSM
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[4] bit 12 GTX[3]: CHAN_BOND_SEQ_1_ENABLE bit 2	GTX[3]: DRP[4] bit 13 GTX[3]: CHAN_BOND_SEQ_1_ENABLE bit 3
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[4] bit 10 GTX[3]: CHAN_BOND_SEQ_1_ENABLE bit 0	GTX[3]: DRP[4] bit 11 GTX[3]: CHAN_BOND_SEQ_1_ENABLE bit 1
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[4] bit 8 GTX[3]: CHAN_BOND_SEQ_1_1 bit 8	GTX[3]: DRP[4] bit 9 GTX[3]: CHAN_BOND_SEQ_1_1 bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[4] bit 6 GTX[3]: CHAN_BOND_SEQ_1_1 bit 6	GTX[3]: DRP[4] bit 7 GTX[3]: CHAN_BOND_SEQ_1_1 bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[4] bit 4 GTX[3]: CHAN_BOND_SEQ_1_1 bit 4	GTX[3]: DRP[4] bit 5 GTX[3]: CHAN_BOND_SEQ_1_1 bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[4] bit 2 GTX[3]: CHAN_BOND_SEQ_1_1 bit 2	GTX[3]: DRP[4] bit 3 GTX[3]: CHAN_BOND_SEQ_1_1 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[4] bit 0 GTX[3]: CHAN_BOND_SEQ_1_1 bit 0	GTX[3]: DRP[4] bit 1 GTX[3]: CHAN_BOND_SEQ_1_1 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[3] bit 14 GTX[3]: BIAS_CFG bit 14	GTX[3]: DRP[3] bit 15 GTX[3]: BIAS_CFG bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[3] bit 12 GTX[3]: BIAS_CFG bit 12	GTX[3]: DRP[3] bit 13 GTX[3]: BIAS_CFG bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[3] bit 10 GTX[3]: BIAS_CFG bit 10	GTX[3]: DRP[3] bit 11 GTX[3]: BIAS_CFG bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[3] bit 8 GTX[3]: BIAS_CFG bit 8	GTX[3]: DRP[3] bit 9 GTX[3]: BIAS_CFG bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[3] bit 6 GTX[3]: BIAS_CFG bit 6	GTX[3]: DRP[3] bit 7 GTX[3]: BIAS_CFG bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[3] bit 4 GTX[3]: BIAS_CFG bit 4	GTX[3]: DRP[3] bit 5 GTX[3]: BIAS_CFG bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[3] bit 2 GTX[3]: BIAS_CFG bit 2	GTX[3]: DRP[3] bit 3 GTX[3]: BIAS_CFG bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[3] bit 0 GTX[3]: BIAS_CFG bit 0	GTX[3]: DRP[3] bit 1 GTX[3]: BIAS_CFG bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[2] bit 14 GTX[3]: RXUSRCLK_DLY bit 14	GTX[3]: DRP[2] bit 15 GTX[3]: RXUSRCLK_DLY bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[2] bit 12 GTX[3]: RXUSRCLK_DLY bit 12	GTX[3]: DRP[2] bit 13 GTX[3]: RXUSRCLK_DLY bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[2] bit 10 GTX[3]: RXUSRCLK_DLY bit 10	GTX[3]: DRP[2] bit 11 GTX[3]: RXUSRCLK_DLY bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[2] bit 8 GTX[3]: RXUSRCLK_DLY bit 8	GTX[3]: DRP[2] bit 9 GTX[3]: RXUSRCLK_DLY bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[2] bit 6 GTX[3]: RXUSRCLK_DLY bit 6	GTX[3]: DRP[2] bit 7 GTX[3]: RXUSRCLK_DLY bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[2] bit 4 GTX[3]: RXUSRCLK_DLY bit 4	GTX[3]: DRP[2] bit 5 GTX[3]: RXUSRCLK_DLY bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[2] bit 2 GTX[3]: RXUSRCLK_DLY bit 2	GTX[3]: DRP[2] bit 3 GTX[3]: RXUSRCLK_DLY bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[2] bit 0 GTX[3]: RXUSRCLK_DLY bit 0	GTX[3]: DRP[2] bit 1 GTX[3]: RXUSRCLK_DLY bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[1] bit 14 GTX[3]: PMA_RXSYNC_CFG bit 5	GTX[3]: DRP[1] bit 15 GTX[3]: PMA_RXSYNC_CFG bit 6
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[1] bit 12 GTX[3]: PMA_RXSYNC_CFG bit 3	GTX[3]: DRP[1] bit 13 GTX[3]: PMA_RXSYNC_CFG bit 4
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[1] bit 10 GTX[3]: PMA_RXSYNC_CFG bit 1	GTX[3]: DRP[1] bit 11 GTX[3]: PMA_RXSYNC_CFG bit 2
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[1] bit 8 GTX[3]: PMA_RX_CFG bit 24	GTX[3]: DRP[1] bit 9 GTX[3]: PMA_RXSYNC_CFG bit 0
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[1] bit 6 GTX[3]: PMA_RX_CFG bit 22	GTX[3]: DRP[1] bit 7 GTX[3]: PMA_RX_CFG bit 23
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[1] bit 4 GTX[3]: PMA_RX_CFG bit 20	GTX[3]: DRP[1] bit 5 GTX[3]: PMA_RX_CFG bit 21
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[1] bit 2 GTX[3]: PMA_RX_CFG bit 18	GTX[3]: DRP[1] bit 3 GTX[3]: PMA_RX_CFG bit 19
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[1] bit 0 GTX[3]: PMA_RX_CFG bit 16	GTX[3]: DRP[1] bit 1 GTX[3]: PMA_RX_CFG bit 17
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[0] bit 14 GTX[3]: PMA_RX_CFG bit 14	GTX[3]: DRP[0] bit 15 GTX[3]: PMA_RX_CFG bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[0] bit 12 GTX[3]: PMA_RX_CFG bit 12	GTX[3]: DRP[0] bit 13 GTX[3]: PMA_RX_CFG bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[0] bit 10 GTX[3]: PMA_RX_CFG bit 10	GTX[3]: DRP[0] bit 11 GTX[3]: PMA_RX_CFG bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[0] bit 8 GTX[3]: PMA_RX_CFG bit 8	GTX[3]: DRP[0] bit 9 GTX[3]: PMA_RX_CFG bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[0] bit 6 GTX[3]: PMA_RX_CFG bit 6	GTX[3]: DRP[0] bit 7 GTX[3]: PMA_RX_CFG bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[0] bit 4 GTX[3]: PMA_RX_CFG bit 4	GTX[3]: DRP[0] bit 5 GTX[3]: PMA_RX_CFG bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[0] bit 2 GTX[3]: PMA_RX_CFG bit 2	GTX[3]: DRP[0] bit 3 GTX[3]: PMA_RX_CFG bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[0] bit 0 GTX[3]: PMA_RX_CFG bit 0	GTX[3]: DRP[0] bit 1 GTX[3]: PMA_RX_CFG bit 1

virtex6 GTX rect MAIN[31]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[15] bit 14 GTX[3]: CLK_COR_MIN_LAT bit 4	GTX[3]: DRP[15] bit 15 GTX[3]: CLK_COR_MIN_LAT bit 5
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[15] bit 12 GTX[3]: CLK_COR_MIN_LAT bit 2	GTX[3]: DRP[15] bit 13 GTX[3]: CLK_COR_MIN_LAT bit 3
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[15] bit 10 GTX[3]: CLK_COR_MIN_LAT bit 0	GTX[3]: DRP[15] bit 11 GTX[3]: CLK_COR_MIN_LAT bit 1
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[15] bit 8 GTX[3]: CLK_COR_SEQ_1_3 bit 8	GTX[3]: DRP[15] bit 9 GTX[3]: CLK_COR_SEQ_1_3 bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[15] bit 6 GTX[3]: CLK_COR_SEQ_1_3 bit 6	GTX[3]: DRP[15] bit 7 GTX[3]: CLK_COR_SEQ_1_3 bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[15] bit 4 GTX[3]: CLK_COR_SEQ_1_3 bit 4	GTX[3]: DRP[15] bit 5 GTX[3]: CLK_COR_SEQ_1_3 bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[15] bit 2 GTX[3]: CLK_COR_SEQ_1_3 bit 2	GTX[3]: DRP[15] bit 3 GTX[3]: CLK_COR_SEQ_1_3 bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[15] bit 0 GTX[3]: CLK_COR_SEQ_1_3 bit 0	GTX[3]: DRP[15] bit 1 GTX[3]: CLK_COR_SEQ_1_3 bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[14] bit 14 GTX[3]: CLK_COR_REPEAT_WAIT bit 4	GTX[3]: DRP[14] bit 15 GTX[3]: CLK_COR_KEEP_IDLE
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[14] bit 12 GTX[3]: CLK_COR_REPEAT_WAIT bit 2	GTX[3]: DRP[14] bit 13 GTX[3]: CLK_COR_REPEAT_WAIT bit 3
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[14] bit 10 GTX[3]: CLK_COR_REPEAT_WAIT bit 0	GTX[3]: DRP[14] bit 11 GTX[3]: CLK_COR_REPEAT_WAIT bit 1
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[14] bit 8 GTX[3]: CLK_COR_SEQ_1_2 bit 8	GTX[3]: DRP[14] bit 9 GTX[3]: CLK_COR_SEQ_1_2 bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[14] bit 6 GTX[3]: CLK_COR_SEQ_1_2 bit 6	GTX[3]: DRP[14] bit 7 GTX[3]: CLK_COR_SEQ_1_2 bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[14] bit 4 GTX[3]: CLK_COR_SEQ_1_2 bit 4	GTX[3]: DRP[14] bit 5 GTX[3]: CLK_COR_SEQ_1_2 bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[14] bit 2 GTX[3]: CLK_COR_SEQ_1_2 bit 2	GTX[3]: DRP[14] bit 3 GTX[3]: CLK_COR_SEQ_1_2 bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[14] bit 0 GTX[3]: CLK_COR_SEQ_1_2 bit 0	GTX[3]: DRP[14] bit 1 GTX[3]: CLK_COR_SEQ_1_2 bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[13] bit 14 GTX[3]: CLK_CORRECT_USE	GTX[3]: DRP[13] bit 15 GTX[3]: CLK_COR_PRECEDENCE
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[13] bit 12 GTX[3]: CLK_COR_SEQ_1_ENABLE bit 2	GTX[3]: DRP[13] bit 13 GTX[3]: CLK_COR_SEQ_1_ENABLE bit 3
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[13] bit 10 GTX[3]: CLK_COR_SEQ_1_ENABLE bit 0	GTX[3]: DRP[13] bit 11 GTX[3]: CLK_COR_SEQ_1_ENABLE bit 1
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[13] bit 8 GTX[3]: CLK_COR_SEQ_1_1 bit 8	GTX[3]: DRP[13] bit 9 GTX[3]: CLK_COR_SEQ_1_1 bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[13] bit 6 GTX[3]: CLK_COR_SEQ_1_1 bit 6	GTX[3]: DRP[13] bit 7 GTX[3]: CLK_COR_SEQ_1_1 bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[13] bit 4 GTX[3]: CLK_COR_SEQ_1_1 bit 4	GTX[3]: DRP[13] bit 5 GTX[3]: CLK_COR_SEQ_1_1 bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[13] bit 2 GTX[3]: CLK_COR_SEQ_1_1 bit 2	GTX[3]: DRP[13] bit 3 GTX[3]: CLK_COR_SEQ_1_1 bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[13] bit 0 GTX[3]: CLK_COR_SEQ_1_1 bit 0	GTX[3]: DRP[13] bit 1 GTX[3]: CLK_COR_SEQ_1_1 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[12] bit 14	GTX[3]: DRP[12] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[12] bit 12 GTX[3]: RXBUF_OVRD_THRESH	GTX[3]: DRP[12] bit 13 GTX[3]: RX_FIFO_ADDR_MODE bit 0
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[12] bit 10 GTX[3]: RXBUF_UDFL_THRESH bit 4	GTX[3]: DRP[12] bit 11 GTX[3]: RXBUF_UDFL_THRESH bit 5
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[12] bit 8 GTX[3]: RXBUF_UDFL_THRESH bit 2	GTX[3]: DRP[12] bit 9 GTX[3]: RXBUF_UDFL_THRESH bit 3
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[12] bit 6 GTX[3]: RXBUF_UDFL_THRESH bit 0	GTX[3]: DRP[12] bit 7 GTX[3]: RXBUF_UDFL_THRESH bit 1
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[12] bit 4 GTX[3]: RXBUF_OVFL_THRESH bit 4	GTX[3]: DRP[12] bit 5 GTX[3]: RXBUF_OVFL_THRESH bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[12] bit 2 GTX[3]: RXBUF_OVFL_THRESH bit 2	GTX[3]: DRP[12] bit 3 GTX[3]: RXBUF_OVFL_THRESH bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[12] bit 0 GTX[3]: RXBUF_OVFL_THRESH bit 0	GTX[3]: DRP[12] bit 1 GTX[3]: RXBUF_OVFL_THRESH bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[11] bit 14 GTX[3]: RX_IDLE_HI_CNT bit 2	GTX[3]: DRP[11] bit 15 GTX[3]: RX_IDLE_HI_CNT bit 3
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[11] bit 12 GTX[3]: RX_IDLE_HI_CNT bit 0	GTX[3]: DRP[11] bit 13 GTX[3]: RX_IDLE_HI_CNT bit 1
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[11] bit 10 GTX[3]: RX_EN_IDLE_RESET_BUF	GTX[3]: DRP[11] bit 11 GTX[3]: RX_XCLK_SEL bit 0
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[11] bit 8 GTX[3]: CHAN_BOND_SEQ_2_4 bit 8	GTX[3]: DRP[11] bit 9 GTX[3]: CHAN_BOND_SEQ_2_4 bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[11] bit 6 GTX[3]: CHAN_BOND_SEQ_2_4 bit 6	GTX[3]: DRP[11] bit 7 GTX[3]: CHAN_BOND_SEQ_2_4 bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[11] bit 4 GTX[3]: CHAN_BOND_SEQ_2_4 bit 4	GTX[3]: DRP[11] bit 5 GTX[3]: CHAN_BOND_SEQ_2_4 bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[11] bit 2 GTX[3]: CHAN_BOND_SEQ_2_4 bit 2	GTX[3]: DRP[11] bit 3 GTX[3]: CHAN_BOND_SEQ_2_4 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[11] bit 0 GTX[3]: CHAN_BOND_SEQ_2_4 bit 0	GTX[3]: DRP[11] bit 1 GTX[3]: CHAN_BOND_SEQ_2_4 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[10] bit 14 GTX[3]: CHAN_BOND_SEQ_2_USE	GTX[3]: DRP[10] bit 15 GTX[3]: RX_EN_IDLE_RESET_PH
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[10] bit 12 GTX[3]: CHAN_BOND_SEQ_2_CFG bit 2	GTX[3]: DRP[10] bit 13 GTX[3]: CHAN_BOND_SEQ_2_CFG bit 3
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[10] bit 10 GTX[3]: CHAN_BOND_SEQ_2_CFG bit 0	GTX[3]: DRP[10] bit 11 GTX[3]: CHAN_BOND_SEQ_2_CFG bit 1
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[10] bit 8 GTX[3]: CHAN_BOND_SEQ_2_3 bit 8	GTX[3]: DRP[10] bit 9 GTX[3]: CHAN_BOND_SEQ_2_3 bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[10] bit 6 GTX[3]: CHAN_BOND_SEQ_2_3 bit 6	GTX[3]: DRP[10] bit 7 GTX[3]: CHAN_BOND_SEQ_2_3 bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[10] bit 4 GTX[3]: CHAN_BOND_SEQ_2_3 bit 4	GTX[3]: DRP[10] bit 5 GTX[3]: CHAN_BOND_SEQ_2_3 bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[10] bit 2 GTX[3]: CHAN_BOND_SEQ_2_3 bit 2	GTX[3]: DRP[10] bit 3 GTX[3]: CHAN_BOND_SEQ_2_3 bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[10] bit 0 GTX[3]: CHAN_BOND_SEQ_2_3 bit 0	GTX[3]: DRP[10] bit 1 GTX[3]: CHAN_BOND_SEQ_2_3 bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[9] bit 14 GTX[3]: CHAN_BOND_KEEP_ALIGN	GTX[3]: DRP[9] bit 15 GTX[3]: RX_EN_MODE_RESET_BUF
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[9] bit 12 GTX[3]: CHAN_BOND_2_MAX_SKEW bit 2	GTX[3]: DRP[9] bit 13 GTX[3]: CHAN_BOND_2_MAX_SKEW bit 3
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[9] bit 10 GTX[3]: CHAN_BOND_2_MAX_SKEW bit 0	GTX[3]: DRP[9] bit 11 GTX[3]: CHAN_BOND_2_MAX_SKEW bit 1
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[9] bit 8 GTX[3]: CHAN_BOND_SEQ_2_2 bit 8	GTX[3]: DRP[9] bit 9 GTX[3]: CHAN_BOND_SEQ_2_2 bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[9] bit 6 GTX[3]: CHAN_BOND_SEQ_2_2 bit 6	GTX[3]: DRP[9] bit 7 GTX[3]: CHAN_BOND_SEQ_2_2 bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[9] bit 4 GTX[3]: CHAN_BOND_SEQ_2_2 bit 4	GTX[3]: DRP[9] bit 5 GTX[3]: CHAN_BOND_SEQ_2_2 bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[9] bit 2 GTX[3]: CHAN_BOND_SEQ_2_2 bit 2	GTX[3]: DRP[9] bit 3 GTX[3]: CHAN_BOND_SEQ_2_2 bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[9] bit 0 GTX[3]: CHAN_BOND_SEQ_2_2 bit 0	GTX[3]: DRP[9] bit 1 GTX[3]: CHAN_BOND_SEQ_2_2 bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[8] bit 14 GTX[3]: RX_EN_REALIGN_RESET_BUF	GTX[3]: DRP[8] bit 15 GTX[3]: RX_EN_RATE_RESET_BUF
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[8] bit 12 GTX[3]: CHAN_BOND_SEQ_2_ENABLE bit 2	GTX[3]: DRP[8] bit 13 GTX[3]: CHAN_BOND_SEQ_2_ENABLE bit 3
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[8] bit 10 GTX[3]: CHAN_BOND_SEQ_2_ENABLE bit 0	GTX[3]: DRP[8] bit 11 GTX[3]: CHAN_BOND_SEQ_2_ENABLE bit 1
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[8] bit 8 GTX[3]: CHAN_BOND_SEQ_2_1 bit 8	GTX[3]: DRP[8] bit 9 GTX[3]: CHAN_BOND_SEQ_2_1 bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[8] bit 6 GTX[3]: CHAN_BOND_SEQ_2_1 bit 6	GTX[3]: DRP[8] bit 7 GTX[3]: CHAN_BOND_SEQ_2_1 bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[8] bit 4 GTX[3]: CHAN_BOND_SEQ_2_1 bit 4	GTX[3]: DRP[8] bit 5 GTX[3]: CHAN_BOND_SEQ_2_1 bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[8] bit 2 GTX[3]: CHAN_BOND_SEQ_2_1 bit 2	GTX[3]: DRP[8] bit 3 GTX[3]: CHAN_BOND_SEQ_2_1 bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[8] bit 0 GTX[3]: CHAN_BOND_SEQ_2_1 bit 0	GTX[3]: DRP[8] bit 1 GTX[3]: CHAN_BOND_SEQ_2_1 bit 1

virtex6 GTX rect MAIN[32]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[23] bit 14 GTX[3]: RX_DATA_WIDTH bit 2	GTX[3]: DRP[23] bit 15 GTX[3]: GEN_RXUSRCLK
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[23] bit 12 GTX[3]: RX_DATA_WIDTH bit 0	GTX[3]: DRP[23] bit 13 GTX[3]: RX_DATA_WIDTH bit 1
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[23] bit 10 GTX[3]: BIAS_CFG bit 16	GTX[3]: DRP[23] bit 11 GTX[3]: CHAN_BOND_SEQ_2_CFG bit 4
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[23] bit 8 GTX[3]: RX_CLK25_DIVIDER bit 3	GTX[3]: DRP[23] bit 9 GTX[3]: RX_CLK25_DIVIDER bit 4
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[23] bit 6 GTX[3]: RX_CLK25_DIVIDER bit 1	GTX[3]: DRP[23] bit 7 GTX[3]: RX_CLK25_DIVIDER bit 2
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[23] bit 4 GTX[3]: AC_CAP_DIS	GTX[3]: DRP[23] bit 5 GTX[3]: RX_CLK25_DIVIDER bit 0
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[23] bit 2 GTX[3]: OOBDETECT_THRESHOLD bit 2	GTX[3]: DRP[23] bit 3 GTX[3]: GTX_CFG_PWRUP
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[23] bit 0 GTX[3]: OOBDETECT_THRESHOLD bit 0	GTX[3]: DRP[23] bit 1 GTX[3]: OOBDETECT_THRESHOLD bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[22] bit 14 GTX[3]: CDR_PH_ADJ_TIME bit 3	GTX[3]: DRP[22] bit 15 GTX[3]: CDR_PH_ADJ_TIME bit 4
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[22] bit 12 GTX[3]: CDR_PH_ADJ_TIME bit 1	GTX[3]: DRP[22] bit 13 GTX[3]: CDR_PH_ADJ_TIME bit 2
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[22] bit 10 GTX[3]: PMA_CDR_SCAN bit 26	GTX[3]: DRP[22] bit 11 GTX[3]: CDR_PH_ADJ_TIME bit 0
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[22] bit 8 GTX[3]: PMA_CDR_SCAN bit 24	GTX[3]: DRP[22] bit 9 GTX[3]: PMA_CDR_SCAN bit 25
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[22] bit 6 GTX[3]: PMA_CDR_SCAN bit 22	GTX[3]: DRP[22] bit 7 GTX[3]: PMA_CDR_SCAN bit 23
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[22] bit 4 GTX[3]: PMA_CDR_SCAN bit 20	GTX[3]: DRP[22] bit 5 GTX[3]: PMA_CDR_SCAN bit 21
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[22] bit 2 GTX[3]: PMA_CDR_SCAN bit 18	GTX[3]: DRP[22] bit 3 GTX[3]: PMA_CDR_SCAN bit 19
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[22] bit 0 GTX[3]: PMA_CDR_SCAN bit 16	GTX[3]: DRP[22] bit 1 GTX[3]: PMA_CDR_SCAN bit 17
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[21] bit 14 GTX[3]: PMA_CDR_SCAN bit 14	GTX[3]: DRP[21] bit 15 GTX[3]: PMA_CDR_SCAN bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[21] bit 12 GTX[3]: PMA_CDR_SCAN bit 12	GTX[3]: DRP[21] bit 13 GTX[3]: PMA_CDR_SCAN bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[21] bit 10 GTX[3]: PMA_CDR_SCAN bit 10	GTX[3]: DRP[21] bit 11 GTX[3]: PMA_CDR_SCAN bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[21] bit 8 GTX[3]: PMA_CDR_SCAN bit 8	GTX[3]: DRP[21] bit 9 GTX[3]: PMA_CDR_SCAN bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[21] bit 6 GTX[3]: PMA_CDR_SCAN bit 6	GTX[3]: DRP[21] bit 7 GTX[3]: PMA_CDR_SCAN bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[21] bit 4 GTX[3]: PMA_CDR_SCAN bit 4	GTX[3]: DRP[21] bit 5 GTX[3]: PMA_CDR_SCAN bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[21] bit 2 GTX[3]: PMA_CDR_SCAN bit 2	GTX[3]: DRP[21] bit 3 GTX[3]: PMA_CDR_SCAN bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[21] bit 0 GTX[3]: PMA_CDR_SCAN bit 0	GTX[3]: DRP[21] bit 1 GTX[3]: PMA_CDR_SCAN bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[20] bit 14 GTX[3]: ALIGN_COMMA_WORD bit 0	GTX[3]: DRP[20] bit 15 GTX[3]: DEC_VALID_COMMA_ONLY
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[20] bit 12 GTX[3]: USR_CODE_ERR_CLR bit 0	GTX[3]: DRP[20] bit 13 GTX[3]: RX_DECODE_SEQ_MATCH
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[20] bit 10 GTX[3]: DEC_PCOMMA_DETECT	GTX[3]: DRP[20] bit 11 GTX[3]: DEC_MCOMMA_DETECT
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[20] bit 8 GTX[3]: CLK_COR_SEQ_2_4 bit 8	GTX[3]: DRP[20] bit 9 GTX[3]: CLK_COR_SEQ_2_4 bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[20] bit 6 GTX[3]: CLK_COR_SEQ_2_4 bit 6	GTX[3]: DRP[20] bit 7 GTX[3]: CLK_COR_SEQ_2_4 bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[20] bit 4 GTX[3]: CLK_COR_SEQ_2_4 bit 4	GTX[3]: DRP[20] bit 5 GTX[3]: CLK_COR_SEQ_2_4 bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[20] bit 2 GTX[3]: CLK_COR_SEQ_2_4 bit 2	GTX[3]: DRP[20] bit 3 GTX[3]: CLK_COR_SEQ_2_4 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[20] bit 0 GTX[3]: CLK_COR_SEQ_2_4 bit 0	GTX[3]: DRP[20] bit 1 GTX[3]: CLK_COR_SEQ_2_4 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[19] bit 14 GTX[3]: RX_SLIDE_AUTO_WAIT bit 2	GTX[3]: DRP[19] bit 15 GTX[3]: RX_SLIDE_AUTO_WAIT bit 3
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[19] bit 12 GTX[3]: RX_SLIDE_AUTO_WAIT bit 0	GTX[3]: DRP[19] bit 13 GTX[3]: RX_SLIDE_AUTO_WAIT bit 1
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[19] bit 10 GTX[3]: CLK_COR_DET_LEN bit 0	GTX[3]: DRP[19] bit 11 GTX[3]: CLK_COR_DET_LEN bit 1
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[19] bit 8 GTX[3]: CLK_COR_SEQ_2_3 bit 8	GTX[3]: DRP[19] bit 9 GTX[3]: CLK_COR_SEQ_2_3 bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[19] bit 6 GTX[3]: CLK_COR_SEQ_2_3 bit 6	GTX[3]: DRP[19] bit 7 GTX[3]: CLK_COR_SEQ_2_3 bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[19] bit 4 GTX[3]: CLK_COR_SEQ_2_3 bit 4	GTX[3]: DRP[19] bit 5 GTX[3]: CLK_COR_SEQ_2_3 bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[19] bit 2 GTX[3]: CLK_COR_SEQ_2_3 bit 2	GTX[3]: DRP[19] bit 3 GTX[3]: CLK_COR_SEQ_2_3 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[19] bit 0 GTX[3]: CLK_COR_SEQ_2_3 bit 0	GTX[3]: DRP[19] bit 1 GTX[3]: CLK_COR_SEQ_2_3 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[18] bit 14 GTX[3]: SHOW_REALIGN_COMMA	GTX[3]: DRP[18] bit 15 GTX[3]: RX_CDR_FORCE_ROTATE
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[18] bit 12 GTX[3]: RX_SLIDE_MODE bit 0	GTX[3]: DRP[18] bit 13 GTX[3]: RX_SLIDE_MODE bit 1
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[18] bit 10 GTX[3]: CLK_COR_ADJ_LEN bit 0	GTX[3]: DRP[18] bit 11 GTX[3]: CLK_COR_ADJ_LEN bit 1
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[18] bit 8 GTX[3]: CLK_COR_SEQ_2_2 bit 8	GTX[3]: DRP[18] bit 9 GTX[3]: CLK_COR_SEQ_2_2 bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[18] bit 6 GTX[3]: CLK_COR_SEQ_2_2 bit 6	GTX[3]: DRP[18] bit 7 GTX[3]: CLK_COR_SEQ_2_2 bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[18] bit 4 GTX[3]: CLK_COR_SEQ_2_2 bit 4	GTX[3]: DRP[18] bit 5 GTX[3]: CLK_COR_SEQ_2_2 bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[18] bit 2 GTX[3]: CLK_COR_SEQ_2_2 bit 2	GTX[3]: DRP[18] bit 3 GTX[3]: CLK_COR_SEQ_2_2 bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[18] bit 0 GTX[3]: CLK_COR_SEQ_2_2 bit 0	GTX[3]: DRP[18] bit 1 GTX[3]: CLK_COR_SEQ_2_2 bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[17] bit 14 GTX[3]: CLK_COR_SEQ_2_USE	GTX[3]: DRP[17] bit 15 GTX[3]: CLK_COR_INSERT_IDLE_FLAG
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[17] bit 12 GTX[3]: CLK_COR_SEQ_2_ENABLE bit 2	GTX[3]: DRP[17] bit 13 GTX[3]: CLK_COR_SEQ_2_ENABLE bit 3
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[17] bit 10 GTX[3]: CLK_COR_SEQ_2_ENABLE bit 0	GTX[3]: DRP[17] bit 11 GTX[3]: CLK_COR_SEQ_2_ENABLE bit 1
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[17] bit 8 GTX[3]: CLK_COR_SEQ_2_1 bit 8	GTX[3]: DRP[17] bit 9 GTX[3]: CLK_COR_SEQ_2_1 bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[17] bit 6 GTX[3]: CLK_COR_SEQ_2_1 bit 6	GTX[3]: DRP[17] bit 7 GTX[3]: CLK_COR_SEQ_2_1 bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[17] bit 4 GTX[3]: CLK_COR_SEQ_2_1 bit 4	GTX[3]: DRP[17] bit 5 GTX[3]: CLK_COR_SEQ_2_1 bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[17] bit 2 GTX[3]: CLK_COR_SEQ_2_1 bit 2	GTX[3]: DRP[17] bit 3 GTX[3]: CLK_COR_SEQ_2_1 bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[17] bit 0 GTX[3]: CLK_COR_SEQ_2_1 bit 0	GTX[3]: DRP[17] bit 1 GTX[3]: CLK_COR_SEQ_2_1 bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[16] bit 14 GTX[3]: CLK_COR_MAX_LAT bit 4	GTX[3]: DRP[16] bit 15 GTX[3]: CLK_COR_MAX_LAT bit 5
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[16] bit 12 GTX[3]: CLK_COR_MAX_LAT bit 2	GTX[3]: DRP[16] bit 13 GTX[3]: CLK_COR_MAX_LAT bit 3
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[16] bit 10 GTX[3]: CLK_COR_MAX_LAT bit 0	GTX[3]: DRP[16] bit 11 GTX[3]: CLK_COR_MAX_LAT bit 1
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[16] bit 8 GTX[3]: CLK_COR_SEQ_1_4 bit 8	GTX[3]: DRP[16] bit 9 GTX[3]: CLK_COR_SEQ_1_4 bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[16] bit 6 GTX[3]: CLK_COR_SEQ_1_4 bit 6	GTX[3]: DRP[16] bit 7 GTX[3]: CLK_COR_SEQ_1_4 bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[16] bit 4 GTX[3]: CLK_COR_SEQ_1_4 bit 4	GTX[3]: DRP[16] bit 5 GTX[3]: CLK_COR_SEQ_1_4 bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[16] bit 2 GTX[3]: CLK_COR_SEQ_1_4 bit 2	GTX[3]: DRP[16] bit 3 GTX[3]: CLK_COR_SEQ_1_4 bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[16] bit 0 GTX[3]: CLK_COR_SEQ_1_4 bit 0	GTX[3]: DRP[16] bit 1 GTX[3]: CLK_COR_SEQ_1_4 bit 1

virtex6 GTX rect MAIN[33]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[31] bit 14 GTX[3]: TXPLL_DIVSEL_OUT bit 0	GTX[3]: DRP[31] bit 15 GTX[3]: TXPLL_DIVSEL_OUT bit 1
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[31] bit 12 GTX[3]: TXPLL_LKDET_CFG bit 1	GTX[3]: DRP[31] bit 13 GTX[3]: TXPLL_LKDET_CFG bit 2
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[31] bit 10 GTX[3]: A_TXPOWERDOWN bit 1	GTX[3]: DRP[31] bit 11 GTX[3]: TXPLL_LKDET_CFG bit 0
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[31] bit 8 GTX[3]: TX_CLK_SOURCE bit 0	GTX[3]: DRP[31] bit 9 GTX[3]: A_TXPOWERDOWN bit 0
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[31] bit 6 GTX[3]: TXPLL_DIVSEL45_FB bit 0	GTX[3]: DRP[31] bit 7 GTX[3]: TXPLL_STARTUP_EN
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[31] bit 4 GTX[3]: TXPLL_DIVSEL_FB bit 3	GTX[3]: DRP[31] bit 5 GTX[3]: TXPLL_DIVSEL_FB bit 4
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[31] bit 2 GTX[3]: TXPLL_DIVSEL_FB bit 1	GTX[3]: DRP[31] bit 3 GTX[3]: TXPLL_DIVSEL_FB bit 2
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[31] bit 0	GTX[3]: DRP[31] bit 1 GTX[3]: TXPLL_DIVSEL_FB bit 0
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[30] bit 14 GTX[3]: TXPLL_CP_CFG bit 6	GTX[3]: DRP[30] bit 15 GTX[3]: TXPLL_CP_CFG bit 7
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[30] bit 12 GTX[3]: TXPLL_CP_CFG bit 4	GTX[3]: DRP[30] bit 13 GTX[3]: TXPLL_CP_CFG bit 5
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[30] bit 10 GTX[3]: TXPLL_CP_CFG bit 2	GTX[3]: DRP[30] bit 11 GTX[3]: TXPLL_CP_CFG bit 3
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[30] bit 8 GTX[3]: TXPLL_CP_CFG bit 0	GTX[3]: DRP[30] bit 9 GTX[3]: TXPLL_CP_CFG bit 1
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[30] bit 6 GTX[3]: TXPLL_COM_CFG bit 22	GTX[3]: DRP[30] bit 7 GTX[3]: TXPLL_COM_CFG bit 23
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[30] bit 4 GTX[3]: TXPLL_COM_CFG bit 20	GTX[3]: DRP[30] bit 5 GTX[3]: TXPLL_COM_CFG bit 21
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[30] bit 2 GTX[3]: TXPLL_COM_CFG bit 18	GTX[3]: DRP[30] bit 3 GTX[3]: TXPLL_COM_CFG bit 19
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[30] bit 0 GTX[3]: TXPLL_COM_CFG bit 16	GTX[3]: DRP[30] bit 1 GTX[3]: TXPLL_COM_CFG bit 17
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[29] bit 14 GTX[3]: TXPLL_COM_CFG bit 14	GTX[3]: DRP[29] bit 15 GTX[3]: TXPLL_COM_CFG bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[29] bit 12 GTX[3]: TXPLL_COM_CFG bit 12	GTX[3]: DRP[29] bit 13 GTX[3]: TXPLL_COM_CFG bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[29] bit 10 GTX[3]: TXPLL_COM_CFG bit 10	GTX[3]: DRP[29] bit 11 GTX[3]: TXPLL_COM_CFG bit 11
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[29] bit 8 GTX[3]: TXPLL_COM_CFG bit 8	GTX[3]: DRP[29] bit 9 GTX[3]: TXPLL_COM_CFG bit 9
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[29] bit 6 GTX[3]: TXPLL_COM_CFG bit 6	GTX[3]: DRP[29] bit 7 GTX[3]: TXPLL_COM_CFG bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[29] bit 4 GTX[3]: TXPLL_COM_CFG bit 4	GTX[3]: DRP[29] bit 5 GTX[3]: TXPLL_COM_CFG bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[29] bit 2 GTX[3]: TXPLL_COM_CFG bit 2	GTX[3]: DRP[29] bit 3 GTX[3]: TXPLL_COM_CFG bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[29] bit 0 GTX[3]: TXPLL_COM_CFG bit 0	GTX[3]: DRP[29] bit 1 GTX[3]: TXPLL_COM_CFG bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[28] bit 14 GTX[3]: A_RXPLLPOWERDOWN bit 0	GTX[3]: DRP[28] bit 15 GTX[3]: RX_OVERSAMPLE_MODE
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[28] bit 12 GTX[3]: A_PLLCLKRXRESET bit 0	GTX[3]: DRP[28] bit 13 GTX[3]: PLL_DRP_EN
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[28] bit 10 GTX[3]: A_PLLRXRESET bit 0	GTX[3]: DRP[28] bit 11 GTX[3]: A_RXPLLLKDETEN bit 0
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[28] bit 8 GTX[3]: RXPLLREFSEL_STATIC_VAL bit 1	GTX[3]: DRP[28] bit 9 GTX[3]: RXPLLREFSEL_STATIC_VAL bit 2
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[28] bit 6 GTX[3]: RXPLLREFSEL_MODE_DYNAMIC	GTX[3]: DRP[28] bit 7 GTX[3]: RXPLLREFSEL_STATIC_VAL bit 0
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[28] bit 4 GTX[3]: RXPLL_DIVSEL_REF bit 3	GTX[3]: DRP[28] bit 5 GTX[3]: RXPLL_DIVSEL_REF bit 4
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[28] bit 2 GTX[3]: RXPLL_DIVSEL_REF bit 1	GTX[3]: DRP[28] bit 3 GTX[3]: RXPLL_DIVSEL_REF bit 2
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[28] bit 0 GTX[3]: RXPLLREFSEL_TESTCLK bit 0	GTX[3]: DRP[28] bit 1 GTX[3]: RXPLL_DIVSEL_REF bit 0
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[27] bit 14 GTX[3]: RXPLL_DIVSEL_OUT bit 0	GTX[3]: DRP[27] bit 15 GTX[3]: RXPLL_DIVSEL_OUT bit 1
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[27] bit 12 GTX[3]: RXPLL_LKDET_CFG bit 1	GTX[3]: DRP[27] bit 13 GTX[3]: RXPLL_LKDET_CFG bit 2
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[27] bit 10 GTX[3]: A_RXPOWERDOWN bit 1	GTX[3]: DRP[27] bit 11 GTX[3]: RXPLL_LKDET_CFG bit 0
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[27] bit 8	GTX[3]: DRP[27] bit 9 GTX[3]: A_RXPOWERDOWN bit 0
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[27] bit 6 GTX[3]: RXPLL_DIVSEL45_FB bit 0	GTX[3]: DRP[27] bit 7 GTX[3]: RXPLL_STARTUP_EN
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[27] bit 4 GTX[3]: RXPLL_DIVSEL_FB bit 3	GTX[3]: DRP[27] bit 5 GTX[3]: RXPLL_DIVSEL_FB bit 4
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[27] bit 2 GTX[3]: RXPLL_DIVSEL_FB bit 1	GTX[3]: DRP[27] bit 3 GTX[3]: RXPLL_DIVSEL_FB bit 2
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[27] bit 0	GTX[3]: DRP[27] bit 1 GTX[3]: RXPLL_DIVSEL_FB bit 0
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[26] bit 14 GTX[3]: RXPLL_CP_CFG bit 6	GTX[3]: DRP[26] bit 15 GTX[3]: RXPLL_CP_CFG bit 7
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[26] bit 12 GTX[3]: RXPLL_CP_CFG bit 4	GTX[3]: DRP[26] bit 13 GTX[3]: RXPLL_CP_CFG bit 5
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[26] bit 10 GTX[3]: RXPLL_CP_CFG bit 2	GTX[3]: DRP[26] bit 11 GTX[3]: RXPLL_CP_CFG bit 3
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[26] bit 8 GTX[3]: RXPLL_CP_CFG bit 0	GTX[3]: DRP[26] bit 9 GTX[3]: RXPLL_CP_CFG bit 1
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[26] bit 6 GTX[3]: RXPLL_COM_CFG bit 22	GTX[3]: DRP[26] bit 7 GTX[3]: RXPLL_COM_CFG bit 23
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[26] bit 4 GTX[3]: RXPLL_COM_CFG bit 20	GTX[3]: DRP[26] bit 5 GTX[3]: RXPLL_COM_CFG bit 21
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[26] bit 2 GTX[3]: RXPLL_COM_CFG bit 18	GTX[3]: DRP[26] bit 3 GTX[3]: RXPLL_COM_CFG bit 19
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[26] bit 0 GTX[3]: RXPLL_COM_CFG bit 16	GTX[3]: DRP[26] bit 1 GTX[3]: RXPLL_COM_CFG bit 17
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[25] bit 14 GTX[3]: RXPLL_COM_CFG bit 14	GTX[3]: DRP[25] bit 15 GTX[3]: RXPLL_COM_CFG bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[25] bit 12 GTX[3]: RXPLL_COM_CFG bit 12	GTX[3]: DRP[25] bit 13 GTX[3]: RXPLL_COM_CFG bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[25] bit 10 GTX[3]: RXPLL_COM_CFG bit 10	GTX[3]: DRP[25] bit 11 GTX[3]: RXPLL_COM_CFG bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[25] bit 8 GTX[3]: RXPLL_COM_CFG bit 8	GTX[3]: DRP[25] bit 9 GTX[3]: RXPLL_COM_CFG bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[25] bit 6 GTX[3]: RXPLL_COM_CFG bit 6	GTX[3]: DRP[25] bit 7 GTX[3]: RXPLL_COM_CFG bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[25] bit 4 GTX[3]: RXPLL_COM_CFG bit 4	GTX[3]: DRP[25] bit 5 GTX[3]: RXPLL_COM_CFG bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[25] bit 2 GTX[3]: RXPLL_COM_CFG bit 2	GTX[3]: DRP[25] bit 3 GTX[3]: RXPLL_COM_CFG bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[25] bit 0 GTX[3]: RXPLL_COM_CFG bit 0	GTX[3]: DRP[25] bit 1 GTX[3]: RXPLL_COM_CFG bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[24] bit 14 GTX[3]: RESET_DRP_EN	GTX[3]: DRP[24] bit 15 GTX[3]: MASTER_DRP_EN
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[24] bit 12 GTX[3]: A_RXCDRPHASERESET bit 0	GTX[3]: DRP[24] bit 13 GTX[3]: A_RXDFERESET bit 0
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[24] bit 10 GTX[3]: A_RXCDRHOLD bit 0	GTX[3]: DRP[24] bit 11 GTX[3]: A_RXCDRFREQRESET bit 0
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[24] bit 8 GTX[3]: A_RXRESET bit 0	GTX[3]: DRP[24] bit 9 GTX[3]: A_TXRESET bit 0
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[24] bit 6 GTX[3]: A_GTXRXRESET bit 0	GTX[3]: DRP[24] bit 7 GTX[3]: A_RXBUFRESET bit 0
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[24] bit 4 GTX[3]: A_RXCDRRESET bit 0	GTX[3]: DRP[24] bit 5 GTX[3]: A_GTXTXRESET bit 0
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[24] bit 2 GTX[3]: GEARBOX_ENDEC bit 2	GTX[3]: DRP[24] bit 3 GTX[3]: RXGEARBOX_USE
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[24] bit 0 GTX[3]: GEARBOX_ENDEC bit 0	GTX[3]: DRP[24] bit 1 GTX[3]: GEARBOX_ENDEC bit 1

virtex6 GTX rect MAIN[34]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[39] bit 14 GTX[3]: SATA_IDLE_VAL bit 2	GTX[3]: DRP[39] bit 15 GTX[3]: TX_EN_RATE_RESET_BUF
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[39] bit 12 GTX[3]: SATA_IDLE_VAL bit 0	GTX[3]: DRP[39] bit 13 GTX[3]: SATA_IDLE_VAL bit 1
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[39] bit 10 GTX[3]: SATA_MIN_INIT bit 4	GTX[3]: DRP[39] bit 11 GTX[3]: SATA_MIN_INIT bit 5
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[39] bit 8 GTX[3]: SATA_MIN_INIT bit 2	GTX[3]: DRP[39] bit 9 GTX[3]: SATA_MIN_INIT bit 3
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[39] bit 6 GTX[3]: SATA_MIN_INIT bit 0	GTX[3]: DRP[39] bit 7 GTX[3]: SATA_MIN_INIT bit 1
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[39] bit 4 GTX[3]: SATA_MAX_INIT bit 4	GTX[3]: DRP[39] bit 5 GTX[3]: SATA_MAX_INIT bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[39] bit 2 GTX[3]: SATA_MAX_INIT bit 2	GTX[3]: DRP[39] bit 3 GTX[3]: SATA_MAX_INIT bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[39] bit 0 GTX[3]: SATA_MAX_INIT bit 0	GTX[3]: DRP[39] bit 1 GTX[3]: SATA_MAX_INIT bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[38] bit 14 GTX[3]: BGTEST_CFG bit 0	GTX[3]: DRP[38] bit 15 GTX[3]: BGTEST_CFG bit 1
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[38] bit 12 GTX[3]: TXPLL_SATA bit 0	GTX[3]: DRP[38] bit 13 GTX[3]: TXPLL_SATA bit 1
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[38] bit 10 GTX[3]: SATA_MIN_WAKE bit 4	GTX[3]: DRP[38] bit 11 GTX[3]: SATA_MIN_WAKE bit 5
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[38] bit 8 GTX[3]: SATA_MIN_WAKE bit 2	GTX[3]: DRP[38] bit 9 GTX[3]: SATA_MIN_WAKE bit 3
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[38] bit 6 GTX[3]: SATA_MIN_WAKE bit 0	GTX[3]: DRP[38] bit 7 GTX[3]: SATA_MIN_WAKE bit 1
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[38] bit 4 GTX[3]: SATA_MAX_WAKE bit 4	GTX[3]: DRP[38] bit 5 GTX[3]: SATA_MAX_WAKE bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[38] bit 2 GTX[3]: SATA_MAX_WAKE bit 2	GTX[3]: DRP[38] bit 3 GTX[3]: SATA_MAX_WAKE bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[38] bit 0 GTX[3]: SATA_MAX_WAKE bit 0	GTX[3]: DRP[38] bit 1 GTX[3]: SATA_MAX_WAKE bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[37] bit 14 GTX[3]: A_RXENPMAPHASEALIGN bit 0	GTX[3]: DRP[37] bit 15 GTX[3]: TX_PMADATA_OPT bit 0
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[37] bit 12 GTX[3]: POLARITY_DRP_EN	GTX[3]: DRP[37] bit 13 GTX[3]: A_RXPMASETPHASE bit 0
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[37] bit 10 GTX[3]: A_RXPOLARITY bit 0	GTX[3]: DRP[37] bit 11 GTX[3]: A_TXPOLARITY bit 0
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[37] bit 8 GTX[3]: CM_TRIM bit 0	GTX[3]: DRP[37] bit 9 GTX[3]: CM_TRIM bit 1
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[37] bit 6 GTX[3]: TRANS_TIME_NON_P2 bit 6	GTX[3]: DRP[37] bit 7 GTX[3]: TRANS_TIME_NON_P2 bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[37] bit 4 GTX[3]: TRANS_TIME_NON_P2 bit 4	GTX[3]: DRP[37] bit 5 GTX[3]: TRANS_TIME_NON_P2 bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[37] bit 2 GTX[3]: TRANS_TIME_NON_P2 bit 2	GTX[3]: DRP[37] bit 3 GTX[3]: TRANS_TIME_NON_P2 bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[37] bit 0 GTX[3]: TRANS_TIME_NON_P2 bit 0	GTX[3]: DRP[37] bit 1 GTX[3]: TRANS_TIME_NON_P2 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[36] bit 14 GTX[3]: COM_BURST_VAL bit 2	GTX[3]: DRP[36] bit 15 GTX[3]: COM_BURST_VAL bit 3
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[36] bit 12 GTX[3]: COM_BURST_VAL bit 0	GTX[3]: DRP[36] bit 13 GTX[3]: COM_BURST_VAL bit 1
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[36] bit 10 GTX[3]: TRANS_TIME_FROM_P2 bit 10	GTX[3]: DRP[36] bit 11 GTX[3]: TRANS_TIME_FROM_P2 bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[36] bit 8 GTX[3]: TRANS_TIME_FROM_P2 bit 8	GTX[3]: DRP[36] bit 9 GTX[3]: TRANS_TIME_FROM_P2 bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[36] bit 6 GTX[3]: TRANS_TIME_FROM_P2 bit 6	GTX[3]: DRP[36] bit 7 GTX[3]: TRANS_TIME_FROM_P2 bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[36] bit 4 GTX[3]: TRANS_TIME_FROM_P2 bit 4	GTX[3]: DRP[36] bit 5 GTX[3]: TRANS_TIME_FROM_P2 bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[36] bit 2 GTX[3]: TRANS_TIME_FROM_P2 bit 2	GTX[3]: DRP[36] bit 3 GTX[3]: TRANS_TIME_FROM_P2 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[36] bit 0 GTX[3]: TRANS_TIME_FROM_P2 bit 0	GTX[3]: DRP[36] bit 1 GTX[3]: TRANS_TIME_FROM_P2 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[35] bit 14 GTX[3]: TX_CLK25_DIVIDER bit 4	GTX[3]: DRP[35] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[35] bit 12 GTX[3]: TX_CLK25_DIVIDER bit 2	GTX[3]: DRP[35] bit 13 GTX[3]: TX_CLK25_DIVIDER bit 3
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[35] bit 10 GTX[3]: TX_CLK25_DIVIDER bit 0	GTX[3]: DRP[35] bit 11 GTX[3]: TX_CLK25_DIVIDER bit 1
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[35] bit 8 GTX[3]: TRANS_TIME_TO_P2 bit 8	GTX[3]: DRP[35] bit 9 GTX[3]: TRANS_TIME_TO_P2 bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[35] bit 6 GTX[3]: TRANS_TIME_TO_P2 bit 6	GTX[3]: DRP[35] bit 7 GTX[3]: TRANS_TIME_TO_P2 bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[35] bit 4 GTX[3]: TRANS_TIME_TO_P2 bit 4	GTX[3]: DRP[35] bit 5 GTX[3]: TRANS_TIME_TO_P2 bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[35] bit 2 GTX[3]: TRANS_TIME_TO_P2 bit 2	GTX[3]: DRP[35] bit 3 GTX[3]: TRANS_TIME_TO_P2 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[35] bit 0 GTX[3]: TRANS_TIME_TO_P2 bit 0	GTX[3]: DRP[35] bit 1 GTX[3]: TRANS_TIME_TO_P2 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[34] bit 14	GTX[3]: DRP[34] bit 15 GTX[3]: PMA_CAS_CLK_EN
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[34] bit 12	GTX[3]: DRP[34] bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_GTX: MUX_SOUTHREFCLKOUT1 bit 0 GTX[3]: DRP[34] bit 10	GTX[3]: DRP[34] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[34] bit 8	HCLK_GTX: MUX_SOUTHREFCLKOUT1 bit 1 GTX[3]: DRP[34] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_GTX: MUX_SOUTHREFCLKOUT0 bit 1 GTX[3]: DRP[34] bit 6	HCLK_GTX: MUX_SOUTHREFCLKOUT0 bit 0 GTX[3]: DRP[34] bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_GTX: MUX_NORTHREFCLKOUT1 bit 0 GTX[3]: DRP[34] bit 4	GTX[3]: DRP[34] bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[34] bit 2	HCLK_GTX: MUX_NORTHREFCLKOUT1 bit 1 GTX[3]: DRP[34] bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_GTX: MUX_NORTHREFCLKOUT0 bit 1 GTX[3]: DRP[34] bit 0	HCLK_GTX: MUX_NORTHREFCLKOUT0 bit 0 GTX[3]: DRP[34] bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[33] bit 14 GTX[3]: A_TXELECIDLE bit 0	GTX[3]: DRP[33] bit 15 GTX[3]: PCI_EXPRESS_MODE
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[33] bit 12 GTX[3]: TX_DETECT_RX_CFG bit 12	GTX[3]: DRP[33] bit 13 GTX[3]: TX_DETECT_RX_CFG bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[33] bit 10 GTX[3]: TX_DETECT_RX_CFG bit 10	GTX[3]: DRP[33] bit 11 GTX[3]: TX_DETECT_RX_CFG bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[33] bit 8 GTX[3]: TX_DETECT_RX_CFG bit 8	GTX[3]: DRP[33] bit 9 GTX[3]: TX_DETECT_RX_CFG bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[33] bit 6 GTX[3]: TX_DETECT_RX_CFG bit 6	GTX[3]: DRP[33] bit 7 GTX[3]: TX_DETECT_RX_CFG bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[33] bit 4 GTX[3]: TX_DETECT_RX_CFG bit 4	GTX[3]: DRP[33] bit 5 GTX[3]: TX_DETECT_RX_CFG bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[33] bit 2 GTX[3]: TX_DETECT_RX_CFG bit 2	GTX[3]: DRP[33] bit 3 GTX[3]: TX_DETECT_RX_CFG bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[33] bit 0 GTX[3]: TX_DETECT_RX_CFG bit 0	GTX[3]: DRP[33] bit 1 GTX[3]: TX_DETECT_RX_CFG bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[32] bit 14 GTX[3]: A_TXPLLPOWERDOWN bit 0	GTX[3]: DRP[32] bit 15 GTX[3]: TX_OVERSAMPLE_MODE
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[32] bit 12 GTX[3]: A_PLLCLKTXRESET bit 0	GTX[3]: DRP[32] bit 13 GTX[3]: PDELIDLE_DRP_EN
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[32] bit 10 GTX[3]: A_PLLTXRESET bit 0	GTX[3]: DRP[32] bit 11 GTX[3]: A_TXPLLLKDETEN bit 0
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[32] bit 8 GTX[3]: TXPLLREFSEL_STATIC_VAL bit 1	GTX[3]: DRP[32] bit 9 GTX[3]: TXPLLREFSEL_STATIC_VAL bit 2
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[32] bit 6 GTX[3]: TXPLLREFSEL_MODE_DYNAMIC	GTX[3]: DRP[32] bit 7 GTX[3]: TXPLLREFSEL_STATIC_VAL bit 0
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[32] bit 4 GTX[3]: TXPLL_DIVSEL_REF bit 3	GTX[3]: DRP[32] bit 5 GTX[3]: TXPLL_DIVSEL_REF bit 4
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[32] bit 2 GTX[3]: TXPLL_DIVSEL_REF bit 1	GTX[3]: DRP[32] bit 3 GTX[3]: TXPLL_DIVSEL_REF bit 2
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[32] bit 0 GTX[3]: TXPLLREFSEL_TESTCLK bit 0	GTX[3]: DRP[32] bit 1 GTX[3]: TXPLL_DIVSEL_REF bit 0

virtex6 GTX rect MAIN[35]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[47] bit 14 GTX[3]: TX_XCLK_SEL bit 0	GTX[3]: DRP[47] bit 15 GTX[3]: TXGEARBOX_USE
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[47] bit 12 GTX[3]: TX_IDLE_ASSERT_DELAY bit 1	GTX[3]: DRP[47] bit 13 GTX[3]: TX_IDLE_ASSERT_DELAY bit 2
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[47] bit 10 GTX[3]: COMMA_DOUBLE	GTX[3]: DRP[47] bit 11 GTX[3]: TX_IDLE_ASSERT_DELAY bit 0
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[47] bit 8 GTX[3]: COMMA_10B_ENABLE bit 8	GTX[3]: DRP[47] bit 9 GTX[3]: COMMA_10B_ENABLE bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[47] bit 6 GTX[3]: COMMA_10B_ENABLE bit 6	GTX[3]: DRP[47] bit 7 GTX[3]: COMMA_10B_ENABLE bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[47] bit 4 GTX[3]: COMMA_10B_ENABLE bit 4	GTX[3]: DRP[47] bit 5 GTX[3]: COMMA_10B_ENABLE bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[47] bit 2 GTX[3]: COMMA_10B_ENABLE bit 2	GTX[3]: DRP[47] bit 3 GTX[3]: COMMA_10B_ENABLE bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[47] bit 0 GTX[3]: COMMA_10B_ENABLE bit 0	GTX[3]: DRP[47] bit 1 GTX[3]: COMMA_10B_ENABLE bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[46] bit 14 GTX[3]: DFE_CAL_TIME bit 3	GTX[3]: DRP[46] bit 15 GTX[3]: DFE_CAL_TIME bit 4
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[46] bit 12 GTX[3]: DFE_CAL_TIME bit 1	GTX[3]: DRP[46] bit 13 GTX[3]: DFE_CAL_TIME bit 2
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[46] bit 10 GTX[3]: RX_EYE_SCANMODE bit 1	GTX[3]: DRP[46] bit 11 GTX[3]: DFE_CAL_TIME bit 0
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[46] bit 8 GTX[3]: RCV_TERM_VTTRX	GTX[3]: DRP[46] bit 9 GTX[3]: RX_EYE_SCANMODE bit 0
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[46] bit 6 GTX[3]: TERMINATION_OVRD	GTX[3]: DRP[46] bit 7 GTX[3]: RCV_TERM_GND
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[46] bit 4 GTX[3]: TERMINATION_CTRL bit 4	GTX[3]: DRP[46] bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[46] bit 2 GTX[3]: TERMINATION_CTRL bit 2	GTX[3]: DRP[46] bit 3 GTX[3]: TERMINATION_CTRL bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[46] bit 0 GTX[3]: TERMINATION_CTRL bit 0	GTX[3]: DRP[46] bit 1 GTX[3]: TERMINATION_CTRL bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[45] bit 14 GTX[3]: RX_EYE_OFFSET bit 6	GTX[3]: DRP[45] bit 15 GTX[3]: RX_EYE_OFFSET bit 7
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[45] bit 12 GTX[3]: RX_EYE_OFFSET bit 4	GTX[3]: DRP[45] bit 13 GTX[3]: RX_EYE_OFFSET bit 5
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[45] bit 10 GTX[3]: RX_EYE_OFFSET bit 2	GTX[3]: DRP[45] bit 11 GTX[3]: RX_EYE_OFFSET bit 3
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[45] bit 8 GTX[3]: RX_EYE_OFFSET bit 0	GTX[3]: DRP[45] bit 9 GTX[3]: RX_EYE_OFFSET bit 1
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[45] bit 6 GTX[3]: DFE_CFG bit 6	GTX[3]: DRP[45] bit 7 GTX[3]: DFE_CFG bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[45] bit 4 GTX[3]: DFE_CFG bit 4	GTX[3]: DRP[45] bit 5 GTX[3]: DFE_CFG bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[45] bit 2 GTX[3]: DFE_CFG bit 2	GTX[3]: DRP[45] bit 3 GTX[3]: DFE_CFG bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[45] bit 0 GTX[3]: DFE_CFG bit 0	GTX[3]: DRP[45] bit 1 GTX[3]: DFE_CFG bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[44] bit 14 GTX[3]: A_DFECLKDLYADJ bit 5	GTX[3]: DRP[44] bit 15 GTX[3]: DFE_DRP_EN
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[44] bit 12 GTX[3]: A_DFECLKDLYADJ bit 3	GTX[3]: DRP[44] bit 13 GTX[3]: A_DFECLKDLYADJ bit 4
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[44] bit 10 GTX[3]: A_DFECLKDLYADJ bit 1	GTX[3]: DRP[44] bit 11 GTX[3]: A_DFECLKDLYADJ bit 2
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[44] bit 8 GTX[3]: A_DFETAP4 bit 3	GTX[3]: DRP[44] bit 9 GTX[3]: A_DFECLKDLYADJ bit 0
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[44] bit 6 GTX[3]: A_DFETAP4 bit 1	GTX[3]: DRP[44] bit 7 GTX[3]: A_DFETAP4 bit 2
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[44] bit 4 GTX[3]: A_DFETAP2 bit 4	GTX[3]: DRP[44] bit 5 GTX[3]: A_DFETAP4 bit 0
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[44] bit 2 GTX[3]: A_DFETAP2 bit 2	GTX[3]: DRP[44] bit 3 GTX[3]: A_DFETAP2 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[44] bit 0 GTX[3]: A_DFETAP2 bit 0	GTX[3]: DRP[44] bit 1 GTX[3]: A_DFETAP2 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[43] bit 14 GTX[3]: A_DFEDLYOVRD bit 0	GTX[3]: DRP[43] bit 15 GTX[3]: A_DFETAPOVRD bit 0
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[43] bit 12	GTX[3]: DRP[43] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[43] bit 10 GTX[3]: RX_EN_IDLE_RESET_FR	GTX[3]: DRP[43] bit 11 GTX[3]: RX_EN_IDLE_HOLD_DFE
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[43] bit 8 GTX[3]: A_DFETAP3 bit 3	GTX[3]: DRP[43] bit 9 GTX[3]: RX_EN_IDLE_HOLD_CDR
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[43] bit 6 GTX[3]: A_DFETAP3 bit 1	GTX[3]: DRP[43] bit 7 GTX[3]: A_DFETAP3 bit 2
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[43] bit 4 GTX[3]: A_DFETAP1 bit 4	GTX[3]: DRP[43] bit 5 GTX[3]: A_DFETAP3 bit 0
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[43] bit 2 GTX[3]: A_DFETAP1 bit 2	GTX[3]: DRP[43] bit 3 GTX[3]: A_DFETAP1 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[43] bit 0 GTX[3]: A_DFETAP1 bit 0	GTX[3]: DRP[43] bit 1 GTX[3]: A_DFETAP1 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[42] bit 14 GTX[3]: A_PRBSCNTRESET bit 0	GTX[3]: DRP[42] bit 15 GTX[3]: PRBS_DRP_EN
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[42] bit 12 GTX[3]: A_TXENPRBSTST bit 1	GTX[3]: DRP[42] bit 13 GTX[3]: A_TXENPRBSTST bit 2
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[42] bit 10 GTX[3]: A_TXPRBSFORCEERR bit 0	GTX[3]: DRP[42] bit 11 GTX[3]: A_TXENPRBSTST bit 0
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[42] bit 8 GTX[3]: RXPRBSERR_LOOPBACK bit 0	GTX[3]: DRP[42] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[42] bit 6 GTX[3]: A_RXENPRBSTST bit 1	GTX[3]: DRP[42] bit 7 GTX[3]: A_RXENPRBSTST bit 2
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[42] bit 4	GTX[3]: DRP[42] bit 5 GTX[3]: A_RXENPRBSTST bit 0
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[42] bit 2 GTX[3]: A_LOOPBACK bit 1	GTX[3]: DRP[42] bit 3 GTX[3]: A_LOOPBACK bit 2
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[42] bit 0 GTX[3]: LOOPBACK_DRP_EN	GTX[3]: DRP[42] bit 1 GTX[3]: A_LOOPBACK bit 0
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[41] bit 14 GTX[3]: A_RXENSAMPLEALIGN bit 0	GTX[3]: DRP[41] bit 15 GTX[3]: PHASEALIGN_DRP_EN
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[41] bit 12 GTX[3]: A_TXPMASETPHASE bit 0	GTX[3]: DRP[41] bit 13 GTX[3]: A_TXENPMAPHASEALIGN bit 0
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[41] bit 10 GTX[3]: SAS_MIN_COMSAS bit 4	GTX[3]: DRP[41] bit 11 GTX[3]: SAS_MIN_COMSAS bit 5
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[41] bit 8 GTX[3]: SAS_MIN_COMSAS bit 2	GTX[3]: DRP[41] bit 9 GTX[3]: SAS_MIN_COMSAS bit 3
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[41] bit 6 GTX[3]: SAS_MIN_COMSAS bit 0	GTX[3]: DRP[41] bit 7 GTX[3]: SAS_MIN_COMSAS bit 1
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[41] bit 4 GTX[3]: SAS_MAX_COMSAS bit 4	GTX[3]: DRP[41] bit 5 GTX[3]: SAS_MAX_COMSAS bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[41] bit 2 GTX[3]: SAS_MAX_COMSAS bit 2	GTX[3]: DRP[41] bit 3 GTX[3]: SAS_MAX_COMSAS bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[41] bit 0 GTX[3]: SAS_MAX_COMSAS bit 0	GTX[3]: DRP[41] bit 1 GTX[3]: SAS_MAX_COMSAS bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[40] bit 14 GTX[3]: SATA_BURST_VAL bit 2	GTX[3]: DRP[40] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[40] bit 12 GTX[3]: SATA_BURST_VAL bit 0	GTX[3]: DRP[40] bit 13 GTX[3]: SATA_BURST_VAL bit 1
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[40] bit 10 GTX[3]: SATA_MIN_BURST bit 4	GTX[3]: DRP[40] bit 11 GTX[3]: SATA_MIN_BURST bit 5
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[40] bit 8 GTX[3]: SATA_MIN_BURST bit 2	GTX[3]: DRP[40] bit 9 GTX[3]: SATA_MIN_BURST bit 3
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[40] bit 6 GTX[3]: SATA_MIN_BURST bit 0	GTX[3]: DRP[40] bit 7 GTX[3]: SATA_MIN_BURST bit 1
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[40] bit 4 GTX[3]: SATA_MAX_BURST bit 4	GTX[3]: DRP[40] bit 5 GTX[3]: SATA_MAX_BURST bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[40] bit 2 GTX[3]: SATA_MAX_BURST bit 2	GTX[3]: DRP[40] bit 3 GTX[3]: SATA_MAX_BURST bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[40] bit 0 GTX[3]: SATA_MAX_BURST bit 0	GTX[3]: DRP[40] bit 1 GTX[3]: SATA_MAX_BURST bit 1

virtex6 GTX rect MAIN[36]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[55] bit 14 GTX[3]: PMA_TX_CFG bit 14	GTX[3]: DRP[55] bit 15 GTX[3]: PMA_TX_CFG bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[55] bit 12 GTX[3]: PMA_TX_CFG bit 12	GTX[3]: DRP[55] bit 13 GTX[3]: PMA_TX_CFG bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[55] bit 10 GTX[3]: PMA_TX_CFG bit 10	GTX[3]: DRP[55] bit 11 GTX[3]: PMA_TX_CFG bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[55] bit 8 GTX[3]: PMA_TX_CFG bit 8	GTX[3]: DRP[55] bit 9 GTX[3]: PMA_TX_CFG bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[55] bit 6 GTX[3]: PMA_TX_CFG bit 6	GTX[3]: DRP[55] bit 7 GTX[3]: PMA_TX_CFG bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[55] bit 4 GTX[3]: PMA_TX_CFG bit 4	GTX[3]: DRP[55] bit 5 GTX[3]: PMA_TX_CFG bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[55] bit 2 GTX[3]: PMA_TX_CFG bit 2	GTX[3]: DRP[55] bit 3 GTX[3]: PMA_TX_CFG bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[55] bit 0 GTX[3]: PMA_TX_CFG bit 0	GTX[3]: DRP[55] bit 1 GTX[3]: PMA_TX_CFG bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[54] bit 14 GTX[3]: PMA_CFG bit 74	GTX[3]: DRP[54] bit 15 GTX[3]: PMA_CFG bit 75
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[54] bit 12 GTX[3]: PMA_CFG bit 72	GTX[3]: DRP[54] bit 13 GTX[3]: PMA_CFG bit 73
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[54] bit 10 GTX[3]: PMA_CFG bit 70	GTX[3]: DRP[54] bit 11 GTX[3]: PMA_CFG bit 71
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[54] bit 8 GTX[3]: PMA_CFG bit 68	GTX[3]: DRP[54] bit 9 GTX[3]: PMA_CFG bit 69
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[54] bit 6 GTX[3]: PMA_CFG bit 66	GTX[3]: DRP[54] bit 7 GTX[3]: PMA_CFG bit 67
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[54] bit 4 GTX[3]: PMA_CFG bit 64	GTX[3]: DRP[54] bit 5 GTX[3]: PMA_CFG bit 65
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[54] bit 2 GTX[3]: PMA_TX_CFG bit 18	GTX[3]: DRP[54] bit 3 GTX[3]: PMA_TX_CFG bit 19
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[54] bit 0 GTX[3]: PMA_TX_CFG bit 16	GTX[3]: DRP[54] bit 1 GTX[3]: PMA_TX_CFG bit 17
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[53] bit 14 GTX[3]: PMA_CFG bit 62	GTX[3]: DRP[53] bit 15 GTX[3]: PMA_CFG bit 63
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[53] bit 12 GTX[3]: PMA_CFG bit 60	GTX[3]: DRP[53] bit 13 GTX[3]: PMA_CFG bit 61
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[53] bit 10 GTX[3]: PMA_CFG bit 58	GTX[3]: DRP[53] bit 11 GTX[3]: PMA_CFG bit 59
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[53] bit 8 GTX[3]: PMA_CFG bit 56	GTX[3]: DRP[53] bit 9 GTX[3]: PMA_CFG bit 57
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[53] bit 6 GTX[3]: PMA_CFG bit 54	GTX[3]: DRP[53] bit 7 GTX[3]: PMA_CFG bit 55
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[53] bit 4 GTX[3]: PMA_CFG bit 52	GTX[3]: DRP[53] bit 5 GTX[3]: PMA_CFG bit 53
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[53] bit 2 GTX[3]: PMA_CFG bit 50	GTX[3]: DRP[53] bit 3 GTX[3]: PMA_CFG bit 51
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[53] bit 0 GTX[3]: PMA_CFG bit 48	GTX[3]: DRP[53] bit 1 GTX[3]: PMA_CFG bit 49
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[52] bit 14 GTX[3]: PMA_CFG bit 46	GTX[3]: DRP[52] bit 15 GTX[3]: PMA_CFG bit 47
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[52] bit 12 GTX[3]: PMA_CFG bit 44	GTX[3]: DRP[52] bit 13 GTX[3]: PMA_CFG bit 45
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[52] bit 10 GTX[3]: PMA_CFG bit 42	GTX[3]: DRP[52] bit 11 GTX[3]: PMA_CFG bit 43
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[52] bit 8 GTX[3]: PMA_CFG bit 40	GTX[3]: DRP[52] bit 9 GTX[3]: PMA_CFG bit 41
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[52] bit 6 GTX[3]: PMA_CFG bit 38	GTX[3]: DRP[52] bit 7 GTX[3]: PMA_CFG bit 39
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[52] bit 4 GTX[3]: PMA_CFG bit 36	GTX[3]: DRP[52] bit 5 GTX[3]: PMA_CFG bit 37
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[52] bit 2 GTX[3]: PMA_CFG bit 34	GTX[3]: DRP[52] bit 3 GTX[3]: PMA_CFG bit 35
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[52] bit 0 GTX[3]: PMA_CFG bit 32	GTX[3]: DRP[52] bit 1 GTX[3]: PMA_CFG bit 33
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[51] bit 14 GTX[3]: PMA_CFG bit 30	GTX[3]: DRP[51] bit 15 GTX[3]: PMA_CFG bit 31
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[51] bit 12 GTX[3]: PMA_CFG bit 28	GTX[3]: DRP[51] bit 13 GTX[3]: PMA_CFG bit 29
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[51] bit 10 GTX[3]: PMA_CFG bit 26	GTX[3]: DRP[51] bit 11 GTX[3]: PMA_CFG bit 27
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[51] bit 8 GTX[3]: PMA_CFG bit 24	GTX[3]: DRP[51] bit 9 GTX[3]: PMA_CFG bit 25
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[51] bit 6 GTX[3]: PMA_CFG bit 22	GTX[3]: DRP[51] bit 7 GTX[3]: PMA_CFG bit 23
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[51] bit 4 GTX[3]: PMA_CFG bit 20	GTX[3]: DRP[51] bit 5 GTX[3]: PMA_CFG bit 21
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[51] bit 2 GTX[3]: PMA_CFG bit 18	GTX[3]: DRP[51] bit 3 GTX[3]: PMA_CFG bit 19
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[51] bit 0 GTX[3]: PMA_CFG bit 16	GTX[3]: DRP[51] bit 1 GTX[3]: PMA_CFG bit 17
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[50] bit 14 GTX[3]: PMA_CFG bit 14	GTX[3]: DRP[50] bit 15 GTX[3]: PMA_CFG bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[50] bit 12 GTX[3]: PMA_CFG bit 12	GTX[3]: DRP[50] bit 13 GTX[3]: PMA_CFG bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[50] bit 10 GTX[3]: PMA_CFG bit 10	GTX[3]: DRP[50] bit 11 GTX[3]: PMA_CFG bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[50] bit 8 GTX[3]: PMA_CFG bit 8	GTX[3]: DRP[50] bit 9 GTX[3]: PMA_CFG bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[50] bit 6 GTX[3]: PMA_CFG bit 6	GTX[3]: DRP[50] bit 7 GTX[3]: PMA_CFG bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[50] bit 4 GTX[3]: PMA_CFG bit 4	GTX[3]: DRP[50] bit 5 GTX[3]: PMA_CFG bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[50] bit 2 GTX[3]: PMA_CFG bit 2	GTX[3]: DRP[50] bit 3 GTX[3]: PMA_CFG bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[50] bit 0 GTX[3]: PMA_CFG bit 0	GTX[3]: DRP[50] bit 1 GTX[3]: PMA_CFG bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[49] bit 14 GTX[3]: TX_DATA_WIDTH bit 2	GTX[3]: DRP[49] bit 15 GTX[3]: GEN_TXUSRCLK
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[49] bit 12 GTX[3]: TX_DATA_WIDTH bit 0	GTX[3]: DRP[49] bit 13 GTX[3]: TX_DATA_WIDTH bit 1
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[49] bit 10 GTX[3]: PCOMMA_DETECT	GTX[3]: DRP[49] bit 11 GTX[3]: TX_BUFFER_USE
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[49] bit 8 GTX[3]: PCOMMA_10B_VALUE bit 8	GTX[3]: DRP[49] bit 9 GTX[3]: PCOMMA_10B_VALUE bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[49] bit 6 GTX[3]: PCOMMA_10B_VALUE bit 6	GTX[3]: DRP[49] bit 7 GTX[3]: PCOMMA_10B_VALUE bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[49] bit 4 GTX[3]: PCOMMA_10B_VALUE bit 4	GTX[3]: DRP[49] bit 5 GTX[3]: PCOMMA_10B_VALUE bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[49] bit 2 GTX[3]: PCOMMA_10B_VALUE bit 2	GTX[3]: DRP[49] bit 3 GTX[3]: PCOMMA_10B_VALUE bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[49] bit 0 GTX[3]: PCOMMA_10B_VALUE bit 0	GTX[3]: DRP[49] bit 1 GTX[3]: PCOMMA_10B_VALUE bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: !invert TXUSRCLK GTX[3]: DRP[48] bit 14	GTX[3]: !invert TXUSRCLK2 GTX[3]: DRP[48] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[48] bit 12 GTX[3]: TX_IDLE_DEASSERT_DELAY bit 1	GTX[3]: DRP[48] bit 13 GTX[3]: TX_IDLE_DEASSERT_DELAY bit 2
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[48] bit 10 GTX[3]: MCOMMA_DETECT	GTX[3]: DRP[48] bit 11 GTX[3]: TX_IDLE_DEASSERT_DELAY bit 0
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[48] bit 8 GTX[3]: MCOMMA_10B_VALUE bit 8	GTX[3]: DRP[48] bit 9 GTX[3]: MCOMMA_10B_VALUE bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[48] bit 6 GTX[3]: MCOMMA_10B_VALUE bit 6	GTX[3]: DRP[48] bit 7 GTX[3]: MCOMMA_10B_VALUE bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[48] bit 4 GTX[3]: MCOMMA_10B_VALUE bit 4	GTX[3]: DRP[48] bit 5 GTX[3]: MCOMMA_10B_VALUE bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[48] bit 2 GTX[3]: MCOMMA_10B_VALUE bit 2	GTX[3]: DRP[48] bit 3 GTX[3]: MCOMMA_10B_VALUE bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[48] bit 0 GTX[3]: MCOMMA_10B_VALUE bit 0	GTX[3]: DRP[48] bit 1 GTX[3]: MCOMMA_10B_VALUE bit 1

virtex6 GTX rect MAIN[37]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[63] bit 14	GTX[3]: DRP[63] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[63] bit 12	GTX[3]: DRP[63] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[63] bit 10	GTX[3]: DRP[63] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[63] bit 8	GTX[3]: DRP[63] bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[63] bit 6 GTX[3]: TRANS_TIME_RATE bit 6	GTX[3]: DRP[63] bit 7 GTX[3]: TRANS_TIME_RATE bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[63] bit 4 GTX[3]: TRANS_TIME_RATE bit 4	GTX[3]: DRP[63] bit 5 GTX[3]: TRANS_TIME_RATE bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[63] bit 2 GTX[3]: TRANS_TIME_RATE bit 2	GTX[3]: DRP[63] bit 3 GTX[3]: TRANS_TIME_RATE bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[63] bit 0 GTX[3]: TRANS_TIME_RATE bit 0	GTX[3]: DRP[63] bit 1 GTX[3]: TRANS_TIME_RATE bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[62] bit 14 GTX[3]: A_TXMARGIN bit 1	GTX[3]: DRP[62] bit 15 GTX[3]: A_TXMARGIN bit 2
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[62] bit 12	GTX[3]: DRP[62] bit 13 GTX[3]: A_TXMARGIN bit 0
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[62] bit 10	GTX[3]: DRP[62] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[62] bit 8 GTX[3]: TX_DEEMPH_1 bit 3	GTX[3]: DRP[62] bit 9 GTX[3]: TX_DEEMPH_1 bit 4
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[62] bit 6 GTX[3]: TX_DEEMPH_1 bit 1	GTX[3]: DRP[62] bit 7 GTX[3]: TX_DEEMPH_1 bit 2
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[62] bit 4 GTX[3]: TX_DEEMPH_0 bit 4	GTX[3]: DRP[62] bit 5 GTX[3]: TX_DEEMPH_1 bit 0
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[62] bit 2 GTX[3]: TX_DEEMPH_0 bit 2	GTX[3]: DRP[62] bit 3 GTX[3]: TX_DEEMPH_0 bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[62] bit 0 GTX[3]: TX_DEEMPH_0 bit 0	GTX[3]: DRP[62] bit 1 GTX[3]: TX_DEEMPH_0 bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[61] bit 14 GTX[3]: A_TXPOSTEMPHASIS bit 3	GTX[3]: DRP[61] bit 15 GTX[3]: A_TXPOSTEMPHASIS bit 4
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[61] bit 12 GTX[3]: A_TXPOSTEMPHASIS bit 1	GTX[3]: DRP[61] bit 13 GTX[3]: A_TXPOSTEMPHASIS bit 2
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[61] bit 10 GTX[3]: A_TXPREEMPHASIS bit 3	GTX[3]: DRP[61] bit 11 GTX[3]: A_TXPOSTEMPHASIS bit 0
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[61] bit 8 GTX[3]: A_TXPREEMPHASIS bit 1	GTX[3]: DRP[61] bit 9 GTX[3]: A_TXPREEMPHASIS bit 2
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[61] bit 6 GTX[3]: A_TXBUFDIFFCTRL bit 2	GTX[3]: DRP[61] bit 7 GTX[3]: A_TXPREEMPHASIS bit 0
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[61] bit 4 GTX[3]: A_TXBUFDIFFCTRL bit 0	GTX[3]: DRP[61] bit 5 GTX[3]: A_TXBUFDIFFCTRL bit 1
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[61] bit 2 GTX[3]: A_TXDIFFCTRL bit 2	GTX[3]: DRP[61] bit 3 GTX[3]: A_TXDIFFCTRL bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[61] bit 0 GTX[3]: A_TXDIFFCTRL bit 0	GTX[3]: DRP[61] bit 1 GTX[3]: A_TXDIFFCTRL bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[60] bit 14 GTX[3]: TXDRIVE_DRP_EN	GTX[3]: DRP[60] bit 15 GTX[3]: TX_DRIVE_MODE bit 0
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[60] bit 12 GTX[3]: TX_MARGIN_FULL_4 bit 5	GTX[3]: DRP[60] bit 13 GTX[3]: TX_MARGIN_FULL_4 bit 6
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[60] bit 10 GTX[3]: TX_MARGIN_FULL_4 bit 3	GTX[3]: DRP[60] bit 11 GTX[3]: TX_MARGIN_FULL_4 bit 4
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[60] bit 8 GTX[3]: TX_MARGIN_FULL_4 bit 1	GTX[3]: DRP[60] bit 9 GTX[3]: TX_MARGIN_FULL_4 bit 2
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[60] bit 6 GTX[3]: TX_MARGIN_LOW_4 bit 6	GTX[3]: DRP[60] bit 7 GTX[3]: TX_MARGIN_FULL_4 bit 0
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[60] bit 4 GTX[3]: TX_MARGIN_LOW_4 bit 4	GTX[3]: DRP[60] bit 5 GTX[3]: TX_MARGIN_LOW_4 bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[60] bit 2 GTX[3]: TX_MARGIN_LOW_4 bit 2	GTX[3]: DRP[60] bit 3 GTX[3]: TX_MARGIN_LOW_4 bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[60] bit 0 GTX[3]: TX_MARGIN_LOW_4 bit 0	GTX[3]: DRP[60] bit 1 GTX[3]: TX_MARGIN_LOW_4 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[59] bit 14 GTX[3]: A_TXSWING bit 0	GTX[3]: DRP[59] bit 15 GTX[3]: A_TXDEEMPH bit 0
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[59] bit 12 GTX[3]: TX_MARGIN_FULL_3 bit 5	GTX[3]: DRP[59] bit 13 GTX[3]: TX_MARGIN_FULL_3 bit 6
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[59] bit 10 GTX[3]: TX_MARGIN_FULL_3 bit 3	GTX[3]: DRP[59] bit 11 GTX[3]: TX_MARGIN_FULL_3 bit 4
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[59] bit 8 GTX[3]: TX_MARGIN_FULL_3 bit 1	GTX[3]: DRP[59] bit 9 GTX[3]: TX_MARGIN_FULL_3 bit 2
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[59] bit 6 GTX[3]: TX_MARGIN_LOW_3 bit 6	GTX[3]: DRP[59] bit 7 GTX[3]: TX_MARGIN_FULL_3 bit 0
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[59] bit 4 GTX[3]: TX_MARGIN_LOW_3 bit 4	GTX[3]: DRP[59] bit 5 GTX[3]: TX_MARGIN_LOW_3 bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[59] bit 2 GTX[3]: TX_MARGIN_LOW_3 bit 2	GTX[3]: DRP[59] bit 3 GTX[3]: TX_MARGIN_LOW_3 bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[59] bit 0 GTX[3]: TX_MARGIN_LOW_3 bit 0	GTX[3]: DRP[59] bit 1 GTX[3]: TX_MARGIN_LOW_3 bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[58] bit 14 GTX[3]: ! TXDRIVE_LOOPBACK_HIZ	GTX[3]: DRP[58] bit 15 GTX[3]: ! TXDRIVE_LOOPBACK_PD
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[58] bit 12 GTX[3]: TX_MARGIN_FULL_2 bit 5	GTX[3]: DRP[58] bit 13 GTX[3]: TX_MARGIN_FULL_2 bit 6
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[58] bit 10 GTX[3]: TX_MARGIN_FULL_2 bit 3	GTX[3]: DRP[58] bit 11 GTX[3]: TX_MARGIN_FULL_2 bit 4
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[58] bit 8 GTX[3]: TX_MARGIN_FULL_2 bit 1	GTX[3]: DRP[58] bit 9 GTX[3]: TX_MARGIN_FULL_2 bit 2
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[58] bit 6 GTX[3]: TX_MARGIN_LOW_2 bit 6	GTX[3]: DRP[58] bit 7 GTX[3]: TX_MARGIN_FULL_2 bit 0
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[58] bit 4 GTX[3]: TX_MARGIN_LOW_2 bit 4	GTX[3]: DRP[58] bit 5 GTX[3]: TX_MARGIN_LOW_2 bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[58] bit 2 GTX[3]: TX_MARGIN_LOW_2 bit 2	GTX[3]: DRP[58] bit 3 GTX[3]: TX_MARGIN_LOW_2 bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[58] bit 0 GTX[3]: TX_MARGIN_LOW_2 bit 0	GTX[3]: DRP[58] bit 1 GTX[3]: TX_MARGIN_LOW_2 bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[57] bit 14 GTX[3]: TX_TDCC_CFG bit 0	GTX[3]: DRP[57] bit 15 GTX[3]: TX_TDCC_CFG bit 1
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[57] bit 12 GTX[3]: TX_MARGIN_FULL_1 bit 5	GTX[3]: DRP[57] bit 13 GTX[3]: TX_MARGIN_FULL_1 bit 6
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[57] bit 10 GTX[3]: TX_MARGIN_FULL_1 bit 3	GTX[3]: DRP[57] bit 11 GTX[3]: TX_MARGIN_FULL_1 bit 4
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[57] bit 8 GTX[3]: TX_MARGIN_FULL_1 bit 1	GTX[3]: DRP[57] bit 9 GTX[3]: TX_MARGIN_FULL_1 bit 2
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[57] bit 6 GTX[3]: TX_MARGIN_LOW_1 bit 6	GTX[3]: DRP[57] bit 7 GTX[3]: TX_MARGIN_FULL_1 bit 0
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[57] bit 4 GTX[3]: TX_MARGIN_LOW_1 bit 4	GTX[3]: DRP[57] bit 5 GTX[3]: TX_MARGIN_LOW_1 bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[57] bit 2 GTX[3]: TX_MARGIN_LOW_1 bit 2	GTX[3]: DRP[57] bit 3 GTX[3]: TX_MARGIN_LOW_1 bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[57] bit 0 GTX[3]: TX_MARGIN_LOW_1 bit 0	GTX[3]: DRP[57] bit 1 GTX[3]: TX_MARGIN_LOW_1 bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[56] bit 14 GTX[3]: TXOUTCLKPCS_SEL bit 0	GTX[3]: !invert DCLK GTX[3]: DRP[56] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[56] bit 12 GTX[3]: TX_MARGIN_FULL_0 bit 5	GTX[3]: DRP[56] bit 13 GTX[3]: TX_MARGIN_FULL_0 bit 6
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[56] bit 10 GTX[3]: TX_MARGIN_FULL_0 bit 3	GTX[3]: DRP[56] bit 11 GTX[3]: TX_MARGIN_FULL_0 bit 4
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[56] bit 8 GTX[3]: TX_MARGIN_FULL_0 bit 1	GTX[3]: DRP[56] bit 9 GTX[3]: TX_MARGIN_FULL_0 bit 2
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[56] bit 6 GTX[3]: TX_MARGIN_LOW_0 bit 6	GTX[3]: DRP[56] bit 7 GTX[3]: TX_MARGIN_FULL_0 bit 0
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[56] bit 4 GTX[3]: TX_MARGIN_LOW_0 bit 4	GTX[3]: DRP[56] bit 5 GTX[3]: TX_MARGIN_LOW_0 bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[56] bit 2 GTX[3]: TX_MARGIN_LOW_0 bit 2	GTX[3]: DRP[56] bit 3 GTX[3]: TX_MARGIN_LOW_0 bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[56] bit 0 GTX[3]: TX_MARGIN_LOW_0 bit 0	GTX[3]: DRP[56] bit 1 GTX[3]: TX_MARGIN_LOW_0 bit 1

virtex6 GTX rect MAIN[38]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[71] bit 14	GTX[3]: DRP[71] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[71] bit 12	GTX[3]: DRP[71] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[71] bit 10	GTX[3]: DRP[71] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[71] bit 8 GTX[3]: TXOUTCLK_DLY bit 8	GTX[3]: DRP[71] bit 9 GTX[3]: TXOUTCLK_DLY bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[71] bit 6 GTX[3]: TXOUTCLK_DLY bit 6	GTX[3]: DRP[71] bit 7 GTX[3]: TXOUTCLK_DLY bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[71] bit 4 GTX[3]: TXOUTCLK_DLY bit 4	GTX[3]: DRP[71] bit 5 GTX[3]: TXOUTCLK_DLY bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[71] bit 2 GTX[3]: TXOUTCLK_DLY bit 2	GTX[3]: DRP[71] bit 3 GTX[3]: TXOUTCLK_DLY bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[71] bit 0 GTX[3]: TXOUTCLK_DLY bit 0	GTX[3]: DRP[71] bit 1 GTX[3]: TXOUTCLK_DLY bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[70] bit 14	GTX[3]: DRP[70] bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[70] bit 12	GTX[3]: DRP[70] bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[70] bit 10	GTX[3]: DRP[70] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[70] bit 8 GTX[3]: RXRECCLK_DLY bit 8	GTX[3]: DRP[70] bit 9 GTX[3]: RXRECCLK_DLY bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[70] bit 6 GTX[3]: RXRECCLK_DLY bit 6	GTX[3]: DRP[70] bit 7 GTX[3]: RXRECCLK_DLY bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[70] bit 4 GTX[3]: RXRECCLK_DLY bit 4	GTX[3]: DRP[70] bit 5 GTX[3]: RXRECCLK_DLY bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[70] bit 2 GTX[3]: RXRECCLK_DLY bit 2	GTX[3]: DRP[70] bit 3 GTX[3]: RXRECCLK_DLY bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[70] bit 0 GTX[3]: RXRECCLK_DLY bit 0	GTX[3]: DRP[70] bit 1 GTX[3]: RXRECCLK_DLY bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[69] bit 14	GTX[3]: DRP[69] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[69] bit 12	GTX[3]: DRP[69] bit 13
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[69] bit 10 GTX[3]: TX_USRCLK_CFG bit 4	GTX[3]: DRP[69] bit 11 GTX[3]: TX_USRCLK_CFG bit 5
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[69] bit 8 GTX[3]: TX_USRCLK_CFG bit 2	GTX[3]: DRP[69] bit 9 GTX[3]: TX_USRCLK_CFG bit 3
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[69] bit 6 GTX[3]: TX_USRCLK_CFG bit 0	GTX[3]: DRP[69] bit 7 GTX[3]: TX_USRCLK_CFG bit 1
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[69] bit 4 GTX[3]: TX_BYTECLK_CFG bit 4	GTX[3]: DRP[69] bit 5 GTX[3]: TX_BYTECLK_CFG bit 5
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[69] bit 2 GTX[3]: TX_BYTECLK_CFG bit 2	GTX[3]: DRP[69] bit 3 GTX[3]: TX_BYTECLK_CFG bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[69] bit 0 GTX[3]: TX_BYTECLK_CFG bit 0	GTX[3]: DRP[69] bit 1 GTX[3]: TX_BYTECLK_CFG bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[68] bit 14	GTX[3]: DRP[68] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[68] bit 12	GTX[3]: DRP[68] bit 13
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[68] bit 10	GTX[3]: DRP[68] bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[68] bit 8 GTX[3]: POWER_SAVE bit 8	GTX[3]: DRP[68] bit 9 GTX[3]: POWER_SAVE bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[68] bit 6 GTX[3]: POWER_SAVE bit 6	GTX[3]: DRP[68] bit 7 GTX[3]: POWER_SAVE bit 7
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[68] bit 4 GTX[3]: POWER_SAVE bit 4	GTX[3]: DRP[68] bit 5 GTX[3]: POWER_SAVE bit 5
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[68] bit 2 GTX[3]: POWER_SAVE bit 2	GTX[3]: DRP[68] bit 3 GTX[3]: POWER_SAVE bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[68] bit 0 GTX[3]: POWER_SAVE bit 0	GTX[3]: DRP[68] bit 1 GTX[3]: POWER_SAVE bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: !invert GREFCLKTX GTX[3]: DRP[67] bit 14	GTX[3]: !invert GREFCLKRX GTX[3]: DRP[67] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[67] bit 12	GTX[3]: !invert SCANCLK GTX[3]: DRP[67] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: !invert TSTCLK[0] GTX[3]: DRP[67] bit 10	GTX[3]: !invert TSTCLK[1] GTX[3]: DRP[67] bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[67] bit 8	GTX[3]: DRP[67] bit 9
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[67] bit 6	GTX[3]: DRP[67] bit 7
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[67] bit 4 GTX[3]: RXRECCLK_CTRL bit 1	GTX[3]: DRP[67] bit 5 GTX[3]: RXRECCLK_CTRL bit 2
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[67] bit 2 GTX[3]: TXOUTCLK_CTRL bit 2	GTX[3]: DRP[67] bit 3 GTX[3]: RXRECCLK_CTRL bit 0
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[67] bit 0 GTX[3]: TXOUTCLK_CTRL bit 0	GTX[3]: DRP[67] bit 1 GTX[3]: TXOUTCLK_CTRL bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[66] bit 14 GTX[3]: TST_ATTR bit 14	GTX[3]: DRP[66] bit 15 GTX[3]: TST_ATTR bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[66] bit 12 GTX[3]: TST_ATTR bit 12	GTX[3]: DRP[66] bit 13 GTX[3]: TST_ATTR bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[66] bit 10 GTX[3]: TST_ATTR bit 10	GTX[3]: DRP[66] bit 11 GTX[3]: TST_ATTR bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[66] bit 8 GTX[3]: TST_ATTR bit 8	GTX[3]: DRP[66] bit 9 GTX[3]: TST_ATTR bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[66] bit 6 GTX[3]: TST_ATTR bit 6	GTX[3]: DRP[66] bit 7 GTX[3]: TST_ATTR bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[66] bit 4 GTX[3]: TST_ATTR bit 4	GTX[3]: DRP[66] bit 5 GTX[3]: TST_ATTR bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[66] bit 2 GTX[3]: TST_ATTR bit 2	GTX[3]: DRP[66] bit 3 GTX[3]: TST_ATTR bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[66] bit 0 GTX[3]: TST_ATTR bit 0	GTX[3]: DRP[66] bit 1 GTX[3]: TST_ATTR bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[65] bit 14 GTX[3]: TST_ATTR bit 30	GTX[3]: DRP[65] bit 15 GTX[3]: TST_ATTR bit 31
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[65] bit 12 GTX[3]: TST_ATTR bit 28	GTX[3]: DRP[65] bit 13 GTX[3]: TST_ATTR bit 29
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[65] bit 10 GTX[3]: TST_ATTR bit 26	GTX[3]: DRP[65] bit 11 GTX[3]: TST_ATTR bit 27
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[65] bit 8 GTX[3]: TST_ATTR bit 24	GTX[3]: DRP[65] bit 9 GTX[3]: TST_ATTR bit 25
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[65] bit 6 GTX[3]: TST_ATTR bit 22	GTX[3]: DRP[65] bit 7 GTX[3]: TST_ATTR bit 23
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[65] bit 4 GTX[3]: TST_ATTR bit 20	GTX[3]: DRP[65] bit 5 GTX[3]: TST_ATTR bit 21
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[65] bit 2 GTX[3]: TST_ATTR bit 18	GTX[3]: DRP[65] bit 3 GTX[3]: TST_ATTR bit 19
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[65] bit 0 GTX[3]: TST_ATTR bit 16	GTX[3]: DRP[65] bit 1 GTX[3]: TST_ATTR bit 17
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[64] bit 14	GTX[3]: DRP[64] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[64] bit 12	GTX[3]: DRP[64] bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[64] bit 10	GTX[3]: DRP[64] bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[64] bit 8 GTX[3]: A_RXEQMIX bit 8	GTX[3]: DRP[64] bit 9 GTX[3]: A_RXEQMIX bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[64] bit 6 GTX[3]: A_RXEQMIX bit 6	GTX[3]: DRP[64] bit 7 GTX[3]: A_RXEQMIX bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[64] bit 4 GTX[3]: A_RXEQMIX bit 4	GTX[3]: DRP[64] bit 5 GTX[3]: A_RXEQMIX bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[64] bit 2 GTX[3]: A_RXEQMIX bit 2	GTX[3]: DRP[64] bit 3 GTX[3]: A_RXEQMIX bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[64] bit 0 GTX[3]: A_RXEQMIX bit 0	GTX[3]: DRP[64] bit 1 GTX[3]: A_RXEQMIX bit 1

virtex6 GTX rect MAIN[39]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[79] bit 14	GTX[3]: DRP[79] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[79] bit 12	GTX[3]: DRP[79] bit 13
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[79] bit 10	GTX[3]: DRP[79] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[79] bit 8	GTX[3]: DRP[79] bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[79] bit 6	GTX[3]: DRP[79] bit 7
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[79] bit 4	GTX[3]: DRP[79] bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[79] bit 2	GTX[3]: DRP[79] bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[79] bit 0	GTX[3]: DRP[79] bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[78] bit 14	GTX[3]: DRP[78] bit 15
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[78] bit 12	GTX[3]: DRP[78] bit 13
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[78] bit 10	GTX[3]: DRP[78] bit 11
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[78] bit 8	GTX[3]: DRP[78] bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[78] bit 6	GTX[3]: DRP[78] bit 7
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[78] bit 4	GTX[3]: DRP[78] bit 5
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[78] bit 2	GTX[3]: DRP[78] bit 3
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[78] bit 0	GTX[3]: DRP[78] bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[77] bit 14 GTX[3]: RX_DLYALIGN_OVRDSETTING bit 6	GTX[3]: DRP[77] bit 15 GTX[3]: RX_DLYALIGN_OVRDSETTING bit 7
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[77] bit 12 GTX[3]: RX_DLYALIGN_OVRDSETTING bit 4	GTX[3]: DRP[77] bit 13 GTX[3]: RX_DLYALIGN_OVRDSETTING bit 5
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[77] bit 10 GTX[3]: RX_DLYALIGN_OVRDSETTING bit 2	GTX[3]: DRP[77] bit 11 GTX[3]: RX_DLYALIGN_OVRDSETTING bit 3
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[77] bit 8 GTX[3]: RX_DLYALIGN_OVRDSETTING bit 0	GTX[3]: DRP[77] bit 9 GTX[3]: RX_DLYALIGN_OVRDSETTING bit 1
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[77] bit 6 GTX[3]: RX_DLYALIGN_LPFINC bit 2	GTX[3]: DRP[77] bit 7 GTX[3]: RX_DLYALIGN_LPFINC bit 3
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[77] bit 4 GTX[3]: RX_DLYALIGN_LPFINC bit 0	GTX[3]: DRP[77] bit 5 GTX[3]: RX_DLYALIGN_LPFINC bit 1
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[77] bit 2 GTX[3]: RX_DLYALIGN_CTRINC bit 2	GTX[3]: DRP[77] bit 3 GTX[3]: RX_DLYALIGN_CTRINC bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[77] bit 0 GTX[3]: RX_DLYALIGN_CTRINC bit 0	GTX[3]: DRP[77] bit 1 GTX[3]: RX_DLYALIGN_CTRINC bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[76] bit 14 GTX[3]: TX_DLYALIGN_OVRDSETTING bit 6	GTX[3]: DRP[76] bit 15 GTX[3]: TX_DLYALIGN_OVRDSETTING bit 7
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[76] bit 12 GTX[3]: TX_DLYALIGN_OVRDSETTING bit 4	GTX[3]: DRP[76] bit 13 GTX[3]: TX_DLYALIGN_OVRDSETTING bit 5
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[76] bit 10 GTX[3]: TX_DLYALIGN_OVRDSETTING bit 2	GTX[3]: DRP[76] bit 11 GTX[3]: TX_DLYALIGN_OVRDSETTING bit 3
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[76] bit 8 GTX[3]: TX_DLYALIGN_OVRDSETTING bit 0	GTX[3]: DRP[76] bit 9 GTX[3]: TX_DLYALIGN_OVRDSETTING bit 1
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[76] bit 6 GTX[3]: TX_DLYALIGN_LPFINC bit 2	GTX[3]: DRP[76] bit 7 GTX[3]: TX_DLYALIGN_LPFINC bit 3
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[76] bit 4 GTX[3]: TX_DLYALIGN_LPFINC bit 0	GTX[3]: DRP[76] bit 5 GTX[3]: TX_DLYALIGN_LPFINC bit 1
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[76] bit 2 GTX[3]: TX_DLYALIGN_CTRINC bit 2	GTX[3]: DRP[76] bit 3 GTX[3]: TX_DLYALIGN_CTRINC bit 3
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[76] bit 0 GTX[3]: TX_DLYALIGN_CTRINC bit 0	GTX[3]: DRP[76] bit 1 GTX[3]: TX_DLYALIGN_CTRINC bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[75] bit 14 GTX[3]: RX_EN_REALIGN_RESET_BUF2	GTX[3]: DRP[75] bit 15
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[75] bit 12	GTX[3]: DRP[75] bit 13
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[75] bit 10 GTX[3]: RX_DLYALIGN_EDGESET bit 4	GTX[3]: DRP[75] bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[75] bit 8 GTX[3]: RX_DLYALIGN_EDGESET bit 2	GTX[3]: DRP[75] bit 9 GTX[3]: RX_DLYALIGN_EDGESET bit 3
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[75] bit 6 GTX[3]: RX_DLYALIGN_EDGESET bit 0	GTX[3]: DRP[75] bit 7 GTX[3]: RX_DLYALIGN_EDGESET bit 1
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[75] bit 4 GTX[3]: TX_DLYALIGN_MONSEL bit 1	GTX[3]: DRP[75] bit 5 GTX[3]: TX_DLYALIGN_MONSEL bit 2
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[75] bit 2 GTX[3]: RX_DLYALIGN_MONSEL bit 2	GTX[3]: DRP[75] bit 3 GTX[3]: TX_DLYALIGN_MONSEL bit 0
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[75] bit 0 GTX[3]: RX_DLYALIGN_MONSEL bit 0	GTX[3]: DRP[75] bit 1 GTX[3]: RX_DLYALIGN_MONSEL bit 1
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[74] bit 14	GTX[3]: DRP[74] bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[74] bit 12	GTX[3]: DRP[74] bit 13
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[74] bit 10	GTX[3]: DRP[74] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[74] bit 8	GTX[3]: DRP[74] bit 9
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[74] bit 6	GTX[3]: DRP[74] bit 7
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[74] bit 4	GTX[3]: DRP[74] bit 5
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[74] bit 2	GTX[3]: DRP[74] bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[74] bit 0	GTX[3]: DRP[74] bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[73] bit 14	GTX[3]: DRP[73] bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[73] bit 12	GTX[3]: DRP[73] bit 13
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[73] bit 10	GTX[3]: DRP[73] bit 11
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[73] bit 8	GTX[3]: DRP[73] bit 9
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[73] bit 6	GTX[3]: DRP[73] bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[73] bit 4	GTX[3]: DRP[73] bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[73] bit 2	GTX[3]: DRP[73] bit 3
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[73] bit 0	GTX[3]: DRP[73] bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[72] bit 14	GTX[3]: DRP[72] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[72] bit 12	GTX[3]: DRP[72] bit 13
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[72] bit 10	GTX[3]: DRP[72] bit 11
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[72] bit 8	GTX[3]: DRP[72] bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[72] bit 6	GTX[3]: DRP[72] bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[72] bit 4	GTX[3]: DRP[72] bit 5
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[72] bit 2	GTX[3]: DRP[72] bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX[3]: DRP[72] bit 0	GTX[3]: DRP[72] bit 1

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