GTX transceivers
TODO: document
Tile GTX
Cells: 40
Bel GTX0
| Pin | Direction | Wires |
|---|---|---|
| CLKTESTSIG0 | input | TCELL2:IMUX.IMUX19.DELAY |
| CLKTESTSIG1 | input | TCELL2:IMUX.IMUX18.DELAY |
| COMFINISH | output | TCELL8:OUT18.TMIN |
| COMINITDET | output | TCELL2:OUT20.TMIN |
| COMSASDET | output | TCELL2:OUT19.TMIN |
| COMWAKEDET | output | TCELL2:OUT23.TMIN |
| DADDR0 | input | TCELL9:IMUX.IMUX32.DELAY |
| DADDR1 | input | TCELL9:IMUX.IMUX33.DELAY |
| DADDR2 | input | TCELL9:IMUX.IMUX34.DELAY |
| DADDR3 | input | TCELL9:IMUX.IMUX35.DELAY |
| DADDR4 | input | TCELL9:IMUX.IMUX36.DELAY |
| DADDR5 | input | TCELL9:IMUX.IMUX37.DELAY |
| DADDR6 | input | TCELL9:IMUX.IMUX38.DELAY |
| DADDR7 | input | TCELL9:IMUX.IMUX39.DELAY |
| DCLK | input | TCELL9:IMUX.CLK0 |
| DEN | input | TCELL8:IMUX.IMUX16.DELAY |
| DFECLKDLYADJ0 | input | TCELL4:IMUX.IMUX35.DELAY |
| DFECLKDLYADJ1 | input | TCELL4:IMUX.IMUX19.DELAY |
| DFECLKDLYADJ2 | input | TCELL4:IMUX.IMUX18.DELAY |
| DFECLKDLYADJ3 | input | TCELL4:IMUX.IMUX33.DELAY |
| DFECLKDLYADJ4 | input | TCELL4:IMUX.IMUX17.DELAY |
| DFECLKDLYADJ5 | input | TCELL4:IMUX.IMUX16.DELAY |
| DFECLKDLYADJMON0 | output | TCELL6:OUT5.TMIN |
| DFECLKDLYADJMON1 | output | TCELL6:OUT1.TMIN |
| DFECLKDLYADJMON2 | output | TCELL6:OUT2.TMIN |
| DFECLKDLYADJMON3 | output | TCELL6:OUT6.TMIN |
| DFECLKDLYADJMON4 | output | TCELL6:OUT7.TMIN |
| DFECLKDLYADJMON5 | output | TCELL6:OUT3.TMIN |
| DFEDLYOVRD | input | TCELL4:IMUX.IMUX29.DELAY |
| DFEEYEDACMON0 | output | TCELL6:OUT13.TMIN |
| DFEEYEDACMON1 | output | TCELL6:OUT14.TMIN |
| DFEEYEDACMON2 | output | TCELL6:OUT10.TMIN |
| DFEEYEDACMON3 | output | TCELL6:OUT11.TMIN |
| DFEEYEDACMON4 | output | TCELL6:OUT15.TMIN |
| DFESENSCAL0 | output | TCELL6:OUT19.TMIN |
| DFESENSCAL1 | output | TCELL6:OUT18.TMIN |
| DFESENSCAL2 | output | TCELL6:OUT22.TMIN |
| DFETAP10 | input | TCELL4:IMUX.IMUX8.DELAY |
| DFETAP11 | input | TCELL4:IMUX.IMUX10.DELAY |
| DFETAP12 | input | TCELL4:IMUX.IMUX14.DELAY |
| DFETAP13 | input | TCELL4:IMUX.IMUX15.DELAY |
| DFETAP14 | input | TCELL4:IMUX.IMUX38.DELAY |
| DFETAP1MONITOR0 | output | TCELL8:OUT1.TMIN |
| DFETAP1MONITOR1 | output | TCELL8:OUT2.TMIN |
| DFETAP1MONITOR2 | output | TCELL8:OUT6.TMIN |
| DFETAP1MONITOR3 | output | TCELL8:OUT7.TMIN |
| DFETAP1MONITOR4 | output | TCELL8:OUT3.TMIN |
| DFETAP20 | input | TCELL4:IMUX.IMUX24.DELAY |
| DFETAP21 | input | TCELL4:IMUX.IMUX25.DELAY |
| DFETAP22 | input | TCELL4:IMUX.IMUX30.DELAY |
| DFETAP23 | input | TCELL4:IMUX.IMUX31.DELAY |
| DFETAP24 | input | TCELL4:IMUX.IMUX39.DELAY |
| DFETAP2MONITOR0 | output | TCELL7:OUT1.TMIN |
| DFETAP2MONITOR1 | output | TCELL7:OUT2.TMIN |
| DFETAP2MONITOR2 | output | TCELL7:OUT6.TMIN |
| DFETAP2MONITOR3 | output | TCELL7:OUT7.TMIN |
| DFETAP2MONITOR4 | output | TCELL7:OUT3.TMIN |
| DFETAP30 | input | TCELL6:IMUX.IMUX10.DELAY |
| DFETAP31 | input | TCELL6:IMUX.IMUX9.DELAY |
| DFETAP32 | input | TCELL6:IMUX.IMUX12.DELAY |
| DFETAP33 | input | TCELL6:IMUX.IMUX17.DELAY |
| DFETAP3MONITOR0 | output | TCELL8:OUT12.TMIN |
| DFETAP3MONITOR1 | output | TCELL8:OUT8.TMIN |
| DFETAP3MONITOR2 | output | TCELL8:OUT9.TMIN |
| DFETAP3MONITOR3 | output | TCELL8:OUT13.TMIN |
| DFETAP40 | input | TCELL6:IMUX.IMUX26.DELAY |
| DFETAP41 | input | TCELL6:IMUX.IMUX25.DELAY |
| DFETAP42 | input | TCELL6:IMUX.IMUX28.DELAY |
| DFETAP43 | input | TCELL6:IMUX.IMUX20.DELAY |
| DFETAP4MONITOR0 | output | TCELL7:OUT12.TMIN |
| DFETAP4MONITOR1 | output | TCELL7:OUT8.TMIN |
| DFETAP4MONITOR2 | output | TCELL7:OUT9.TMIN |
| DFETAP4MONITOR3 | output | TCELL7:OUT13.TMIN |
| DFETAPOVRD | input | TCELL4:IMUX.IMUX37.DELAY |
| DI0 | input | TCELL9:IMUX.IMUX8.DELAY |
| DI1 | input | TCELL9:IMUX.IMUX9.DELAY |
| DI10 | input | TCELL9:IMUX.IMUX18.DELAY |
| DI11 | input | TCELL9:IMUX.IMUX19.DELAY |
| DI12 | input | TCELL9:IMUX.IMUX20.DELAY |
| DI13 | input | TCELL9:IMUX.IMUX21.DELAY |
| DI14 | input | TCELL9:IMUX.IMUX22.DELAY |
| DI15 | input | TCELL9:IMUX.IMUX23.DELAY |
| DI2 | input | TCELL9:IMUX.IMUX10.DELAY |
| DI3 | input | TCELL9:IMUX.IMUX11.DELAY |
| DI4 | input | TCELL9:IMUX.IMUX12.DELAY |
| DI5 | input | TCELL9:IMUX.IMUX13.DELAY |
| DI6 | input | TCELL9:IMUX.IMUX14.DELAY |
| DI7 | input | TCELL9:IMUX.IMUX15.DELAY |
| DI8 | input | TCELL9:IMUX.IMUX16.DELAY |
| DI9 | input | TCELL9:IMUX.IMUX17.DELAY |
| DRDY | output | TCELL8:OUT0.TMIN |
| DRPDO0 | output | TCELL9:OUT3.TMIN |
| DRPDO1 | output | TCELL9:OUT7.TMIN |
| DRPDO10 | output | TCELL9:OUT10.TMIN |
| DRPDO11 | output | TCELL9:OUT14.TMIN |
| DRPDO12 | output | TCELL9:OUT13.TMIN |
| DRPDO13 | output | TCELL9:OUT9.TMIN |
| DRPDO14 | output | TCELL9:OUT8.TMIN |
| DRPDO15 | output | TCELL9:OUT12.TMIN |
| DRPDO2 | output | TCELL9:OUT6.TMIN |
| DRPDO3 | output | TCELL9:OUT2.TMIN |
| DRPDO4 | output | TCELL9:OUT1.TMIN |
| DRPDO5 | output | TCELL9:OUT5.TMIN |
| DRPDO6 | output | TCELL9:OUT4.TMIN |
| DRPDO7 | output | TCELL9:OUT0.TMIN |
| DRPDO8 | output | TCELL9:OUT15.TMIN |
| DRPDO9 | output | TCELL9:OUT11.TMIN |
| DWE | input | TCELL8:IMUX.IMUX8.DELAY |
| GATERXELECIDLE | input | TCELL6:IMUX.IMUX32.DELAY |
| GREFCLKRX | input | TCELL3:IMUX.CLK0 |
| GREFCLKTX | input | TCELL7:IMUX.CLK0 |
| GTXRXRESET | input | TCELL1:IMUX.CTRL0 |
| GTXTEST0 | input | TCELL2:IMUX.IMUX39.DELAY |
| GTXTEST1 | input | TCELL2:IMUX.IMUX38.DELAY |
| GTXTEST10 | input | TCELL2:IMUX.IMUX29.DELAY |
| GTXTEST11 | input | TCELL2:IMUX.IMUX28.DELAY |
| GTXTEST12 | input | TCELL2:IMUX.IMUX27.DELAY |
| GTXTEST2 | input | TCELL2:IMUX.IMUX37.DELAY |
| GTXTEST3 | input | TCELL2:IMUX.IMUX36.DELAY |
| GTXTEST4 | input | TCELL2:IMUX.IMUX35.DELAY |
| GTXTEST5 | input | TCELL2:IMUX.IMUX34.DELAY |
| GTXTEST6 | input | TCELL2:IMUX.IMUX33.DELAY |
| GTXTEST7 | input | TCELL2:IMUX.IMUX32.DELAY |
| GTXTEST8 | input | TCELL2:IMUX.IMUX31.DELAY |
| GTXTEST9 | input | TCELL2:IMUX.IMUX30.DELAY |
| GTXTXRESET | input | TCELL6:IMUX.CTRL1 |
| IGNORESIGDET | input | TCELL6:IMUX.IMUX37.DELAY |
| LOOPBACK0 | input | TCELL3:IMUX.IMUX24.DELAY |
| LOOPBACK1 | input | TCELL3:IMUX.IMUX11.DELAY |
| LOOPBACK2 | input | TCELL3:IMUX.IMUX27.DELAY |
| MGTREFCLKFAB0 | output | TCELL4:OUT0.TMIN |
| MGTREFCLKFAB1 | output | TCELL4:OUT12.TMIN |
| PHYSTATUS | output | TCELL4:OUT8.TMIN |
| PLLRXRESET | input | TCELL3:IMUX.CTRL0 |
| PLLTXRESET | input | TCELL5:IMUX.CTRL1 |
| PRBSCNTRESET | input | TCELL0:IMUX.CTRL1 |
| RXBUFRESET | input | TCELL2:IMUX.CTRL0 |
| RXBUFSTATUS0 | output | TCELL4:OUT6.TMIN |
| RXBUFSTATUS1 | output | TCELL4:OUT7.TMIN |
| RXBUFSTATUS2 | output | TCELL4:OUT3.TMIN |
| RXBUFWE | input | TCELL1:IMUX.IMUX24.DELAY |
| RXBYTEISALIGNED | output | TCELL2:OUT13.TMIN |
| RXBYTEREALIGN | output | TCELL2:OUT10.TMIN |
| RXCDRRESET | input | TCELL1:IMUX.CTRL1 |
| RXCHANBONDSEQ | output | TCELL5:OUT14.TMIN |
| RXCHANISALIGNED | output | TCELL3:OUT13.TMIN |
| RXCHANREALIGN | output | TCELL2:OUT14.TMIN |
| RXCHARISCOMMA0 | output | TCELL3:OUT14.TMIN |
| RXCHARISCOMMA1 | output | TCELL3:OUT2.TMIN |
| RXCHARISCOMMA2 | output | TCELL2:OUT8.TMIN |
| RXCHARISCOMMA3 | output | TCELL2:OUT18.TMIN |
| RXCHARISK0 | output | TCELL3:OUT16.TMIN |
| RXCHARISK1 | output | TCELL2:OUT5.TMIN |
| RXCHARISK2 | output | TCELL2:OUT15.TMIN |
| RXCHARISK3 | output | TCELL2:OUT3.TMIN |
| RXCHBONDI0 | input | TCELL3:IMUX.IMUX32.DELAY |
| RXCHBONDI1 | input | TCELL3:IMUX.IMUX33.DELAY |
| RXCHBONDI2 | input | TCELL3:IMUX.IMUX34.DELAY |
| RXCHBONDI3 | input | TCELL3:IMUX.IMUX35.DELAY |
| RXCHBONDLEVEL0 | input | TCELL2:IMUX.IMUX10.DELAY |
| RXCHBONDLEVEL1 | input | TCELL2:IMUX.IMUX26.DELAY |
| RXCHBONDLEVEL2 | input | TCELL2:IMUX.IMUX11.DELAY |
| RXCHBONDMASTER | input | TCELL2:IMUX.IMUX24.DELAY |
| RXCHBONDO0 | output | TCELL4:OUT17.TMIN |
| RXCHBONDO1 | output | TCELL4:OUT10.TMIN |
| RXCHBONDO2 | output | TCELL4:OUT11.TMIN |
| RXCHBONDO3 | output | TCELL4:OUT15.TMIN |
| RXCHBONDSLAVE | input | TCELL2:IMUX.IMUX8.DELAY |
| RXCLKCORCNT0 | output | TCELL5:OUT8.TMIN |
| RXCLKCORCNT1 | output | TCELL5:OUT9.TMIN |
| RXCLKCORCNT2 | output | TCELL5:OUT6.TMIN |
| RXCOMMADET | output | TCELL5:OUT12.TMIN |
| RXCOMMADETUSE | input | TCELL3:IMUX.IMUX36.DELAY |
| RXDATA0 | output | TCELL0:OUT4.TMIN |
| RXDATA1 | output | TCELL0:OUT7.TMIN |
| RXDATA10 | output | TCELL1:OUT6.TMIN |
| RXDATA11 | output | TCELL1:OUT2.TMIN |
| RXDATA12 | output | TCELL2:OUT7.TMIN |
| RXDATA13 | output | TCELL2:OUT6.TMIN |
| RXDATA14 | output | TCELL2:OUT2.TMIN |
| RXDATA15 | output | TCELL2:OUT1.TMIN |
| RXDATA16 | output | TCELL0:OUT15.TMIN |
| RXDATA17 | output | TCELL0:OUT3.TMIN |
| RXDATA18 | output | TCELL0:OUT0.TMIN |
| RXDATA19 | output | TCELL0:OUT22.TMIN |
| RXDATA2 | output | TCELL0:OUT6.TMIN |
| RXDATA20 | output | TCELL0:OUT18.TMIN |
| RXDATA21 | output | TCELL0:OUT17.TMIN |
| RXDATA22 | output | TCELL0:OUT16.TMIN |
| RXDATA23 | output | TCELL0:OUT20.TMIN |
| RXDATA24 | output | TCELL1:OUT0.TMIN |
| RXDATA25 | output | TCELL1:OUT22.TMIN |
| RXDATA26 | output | TCELL1:OUT18.TMIN |
| RXDATA27 | output | TCELL1:OUT9.TMIN |
| RXDATA28 | output | TCELL1:OUT16.TMIN |
| RXDATA29 | output | TCELL1:OUT11.TMIN |
| RXDATA3 | output | TCELL0:OUT2.TMIN |
| RXDATA30 | output | TCELL1:OUT15.TMIN |
| RXDATA31 | output | TCELL1:OUT3.TMIN |
| RXDATA4 | output | TCELL0:OUT1.TMIN |
| RXDATA5 | output | TCELL0:OUT5.TMIN |
| RXDATA6 | output | TCELL1:OUT1.TMIN |
| RXDATA7 | output | TCELL1:OUT5.TMIN |
| RXDATA8 | output | TCELL1:OUT4.TMIN |
| RXDATA9 | output | TCELL1:OUT7.TMIN |
| RXDATAVALID | output | TCELL2:OUT4.TMIN |
| RXDEC8B10BUSE | input | TCELL1:IMUX.IMUX39.DELAY |
| RXDISPERR0 | output | TCELL3:OUT4.TMIN |
| RXDISPERR1 | output | TCELL3:OUT8.TMIN |
| RXDISPERR2 | output | TCELL3:OUT0.TMIN |
| RXDISPERR3 | output | TCELL3:OUT22.TMIN |
| RXDLYALIGNDISABLE | input | TCELL5:IMUX.IMUX14.DELAY |
| RXDLYALIGNFORCEROTATEB | input | TCELL3:IMUX.IMUX25.DELAY |
| RXDLYALIGNMONENB | input | TCELL3:IMUX.IMUX28.DELAY |
| RXDLYALIGNMONITOR0 | output | TCELL5:OUT21.TMIN |
| RXDLYALIGNMONITOR1 | output | TCELL5:OUT15.TMIN |
| RXDLYALIGNMONITOR2 | output | TCELL5:OUT7.TMIN |
| RXDLYALIGNMONITOR3 | output | TCELL5:OUT20.TMIN |
| RXDLYALIGNMONITOR4 | output | TCELL5:OUT23.TMIN |
| RXDLYALIGNMONITOR5 | output | TCELL5:OUT19.TMIN |
| RXDLYALIGNMONITOR6 | output | TCELL5:OUT18.TMIN |
| RXDLYALIGNMONITOR7 | output | TCELL5:OUT0.TMIN |
| RXDLYALIGNOVERRIDE | input | TCELL5:IMUX.IMUX33.DELAY |
| RXDLYALIGNRESET | input | TCELL5:IMUX.IMUX29.DELAY |
| RXDLYALIGNSWPPRECURB | input | TCELL3:IMUX.IMUX29.DELAY |
| RXDLYALIGNTESTMODEENB | input | TCELL3:IMUX.IMUX12.DELAY |
| RXDLYALIGNUPDSW | input | TCELL5:IMUX.IMUX10.DELAY |
| RXELECIDLE | output | TCELL5:OUT3.TMIN |
| RXENCHANSYNC | input | TCELL1:IMUX.IMUX38.DELAY |
| RXENMCOMMAALIGN | input | TCELL1:IMUX.IMUX36.DELAY |
| RXENPCOMMAALIGN | input | TCELL1:IMUX.IMUX37.DELAY |
| RXENPMAPHASEALIGN | input | TCELL1:IMUX.IMUX35.DELAY |
| RXENPRBSTST0 | input | TCELL1:IMUX.IMUX33.DELAY |
| RXENPRBSTST1 | input | TCELL1:IMUX.IMUX34.DELAY |
| RXENPRBSTST2 | input | TCELL1:IMUX.IMUX18.DELAY |
| RXENSAMPLEALIGN | input | TCELL1:IMUX.IMUX32.DELAY |
| RXEQMIX0 | input | TCELL1:IMUX.IMUX14.DELAY |
| RXEQMIX1 | input | TCELL1:IMUX.IMUX15.DELAY |
| RXEQMIX2 | input | TCELL1:IMUX.IMUX30.DELAY |
| RXEQMIX3 | input | TCELL1:IMUX.IMUX22.DELAY |
| RXEQMIX4 | input | TCELL1:IMUX.IMUX29.DELAY |
| RXEQMIX5 | input | TCELL1:IMUX.IMUX21.DELAY |
| RXEQMIX6 | input | TCELL1:IMUX.IMUX28.DELAY |
| RXEQMIX7 | input | TCELL1:IMUX.IMUX20.DELAY |
| RXEQMIX8 | input | TCELL1:IMUX.IMUX27.DELAY |
| RXEQMIX9 | input | TCELL1:IMUX.IMUX19.DELAY |
| RXGEARBOXSLIP | input | TCELL1:IMUX.IMUX12.DELAY |
| RXHEADER0 | output | TCELL5:OUT10.TMIN |
| RXHEADER1 | output | TCELL5:OUT16.TMIN |
| RXHEADER2 | output | TCELL5:OUT17.TMIN |
| RXHEADERVALID | output | TCELL5:OUT11.TMIN |
| RXLOSSOFSYNC0 | output | TCELL2:OUT0.TMIN |
| RXLOSSOFSYNC1 | output | TCELL2:OUT22.TMIN |
| RXNOTINTABLE0 | output | TCELL3:OUT11.TMIN |
| RXNOTINTABLE1 | output | TCELL3:OUT7.TMIN |
| RXNOTINTABLE2 | output | TCELL3:OUT15.TMIN |
| RXNOTINTABLE3 | output | TCELL3:OUT3.TMIN |
| RXOVERSAMPLEERR | output | TCELL4:OUT22.TMIN |
| RXPLLLKDET | output | TCELL4:OUT5.TMIN |
| RXPLLLKDETEN | input | TCELL2:IMUX.IMUX20.DELAY |
| RXPLLPOWERDOWN | input | TCELL2:IMUX.IMUX21.DELAY |
| RXPLLREFSELDY0 | input | TCELL3:IMUX.IMUX37.DELAY |
| RXPLLREFSELDY1 | input | TCELL3:IMUX.IMUX22.DELAY |
| RXPLLREFSELDY2 | input | TCELL3:IMUX.IMUX39.DELAY |
| RXPMASETPHASE | input | TCELL1:IMUX.IMUX11.DELAY |
| RXPOLARITY | input | TCELL1:IMUX.IMUX26.DELAY |
| RXPOWERDOWN0 | input | TCELL4:IMUX.IMUX13.DELAY |
| RXPOWERDOWN1 | input | TCELL4:IMUX.IMUX21.DELAY |
| RXPRBSERR | output | TCELL5:OUT2.TMIN |
| RXRATE0 | input | TCELL6:IMUX.IMUX42.DELAY |
| RXRATE1 | input | TCELL6:IMUX.IMUX41.DELAY |
| RXRATEDONE | output | TCELL6:OUT20.TMIN |
| RXRECCLKPCS | output | TCELL5:OUT5.TMIN |
| RXRESET | input | TCELL2:IMUX.CTRL1 |
| RXRESETDONE | output | TCELL5:OUT22.TMIN |
| RXRUNDISP0 | output | TCELL3:OUT9.TMIN |
| RXRUNDISP1 | output | TCELL3:OUT5.TMIN |
| RXRUNDISP2 | output | TCELL3:OUT19.TMIN |
| RXRUNDISP3 | output | TCELL3:OUT1.TMIN |
| RXSLIDE | input | TCELL1:IMUX.IMUX9.DELAY |
| RXSTARTOFSEQ | output | TCELL5:OUT1.TMIN |
| RXSTATUS0 | output | TCELL4:OUT14.TMIN |
| RXSTATUS1 | output | TCELL4:OUT16.TMIN |
| RXSTATUS2 | output | TCELL4:OUT13.TMIN |
| RXUSRCLK | input | TCELL2:IMUX.CLK0 |
| RXUSRCLK2 | input | TCELL2:IMUX.CLK1 |
| RXVALID | output | TCELL5:OUT4.TMIN |
| SCANCLK | input | TCELL4:IMUX.CLK1 |
| SCANENB | input | TCELL0:IMUX.IMUX37.DELAY |
| SCANIN0 | input | TCELL8:IMUX.IMUX33.DELAY |
| SCANIN1 | input | TCELL8:IMUX.IMUX25.DELAY |
| SCANIN2 | input | TCELL0:IMUX.IMUX38.DELAY |
| SCANIN3 | input | TCELL0:IMUX.IMUX22.DELAY |
| SCANIN4 | input | TCELL8:IMUX.IMUX9.DELAY |
| SCANMODEB | input | TCELL0:IMUX.IMUX29.DELAY |
| SCANOUT0 | output | TCELL4:OUT18.TMIN |
| SCANOUT1 | output | TCELL4:OUT4.TMIN |
| SCANOUT2 | output | TCELL0:OUT23.TMIN |
| SCANOUT3 | output | TCELL0:OUT13.TMIN |
| SCANOUT4 | output | TCELL0:OUT8.TMIN |
| TSTCLK0 | input | TCELL3:IMUX.CLK1 |
| TSTCLK1 | input | TCELL5:IMUX.CLK1 |
| TSTIN0 | input | TCELL0:IMUX.IMUX30.DELAY |
| TSTIN1 | input | TCELL0:IMUX.IMUX14.DELAY |
| TSTIN10 | input | TCELL0:IMUX.IMUX31.DELAY |
| TSTIN11 | input | TCELL0:IMUX.IMUX21.DELAY |
| TSTIN12 | input | TCELL0:IMUX.IMUX13.DELAY |
| TSTIN13 | input | TCELL0:IMUX.IMUX28.DELAY |
| TSTIN14 | input | TCELL0:IMUX.IMUX32.DELAY |
| TSTIN15 | input | TCELL0:IMUX.IMUX16.DELAY |
| TSTIN16 | input | TCELL0:IMUX.IMUX40.DELAY |
| TSTIN17 | input | TCELL0:IMUX.IMUX0.DELAY |
| TSTIN18 | input | TCELL0:IMUX.IMUX1.DELAY |
| TSTIN19 | input | TCELL0:IMUX.IMUX41.DELAY |
| TSTIN2 | input | TCELL0:IMUX.IMUX27.DELAY |
| TSTIN3 | input | TCELL0:IMUX.IMUX11.DELAY |
| TSTIN4 | input | TCELL0:IMUX.IMUX26.DELAY |
| TSTIN5 | input | TCELL0:IMUX.IMUX10.DELAY |
| TSTIN6 | input | TCELL0:IMUX.IMUX25.DELAY |
| TSTIN7 | input | TCELL0:IMUX.IMUX9.DELAY |
| TSTIN8 | input | TCELL0:IMUX.IMUX24.DELAY |
| TSTIN9 | input | TCELL0:IMUX.IMUX8.DELAY |
| TSTOUT0 | output | TCELL1:OUT21.TMIN |
| TSTOUT1 | output | TCELL1:OUT17.TMIN |
| TSTOUT2 | output | TCELL1:OUT10.TMIN |
| TSTOUT3 | output | TCELL1:OUT20.TMIN |
| TSTOUT4 | output | TCELL1:OUT14.TMIN |
| TSTOUT5 | output | TCELL1:OUT23.TMIN |
| TSTOUT6 | output | TCELL1:OUT13.TMIN |
| TSTOUT7 | output | TCELL1:OUT19.TMIN |
| TSTOUT8 | output | TCELL1:OUT8.TMIN |
| TSTOUT9 | output | TCELL1:OUT12.TMIN |
| TSTPWRDN0 | input | TCELL0:IMUX.IMUX33.DELAY |
| TSTPWRDN1 | input | TCELL0:IMUX.IMUX18.DELAY |
| TSTPWRDN2 | input | TCELL0:IMUX.IMUX34.DELAY |
| TSTPWRDN3 | input | TCELL0:IMUX.IMUX19.DELAY |
| TSTPWRDN4 | input | TCELL0:IMUX.IMUX35.DELAY |
| TSTPWRDNOVRD | input | TCELL0:IMUX.IMUX17.DELAY |
| TXBUFDIFFCTRL0 | input | TCELL3:IMUX.IMUX0.DELAY |
| TXBUFDIFFCTRL1 | input | TCELL3:IMUX.IMUX16.DELAY |
| TXBUFDIFFCTRL2 | input | TCELL3:IMUX.IMUX18.DELAY |
| TXBUFSTATUS0 | output | TCELL7:OUT5.TMIN |
| TXBUFSTATUS1 | output | TCELL7:OUT17.TMIN |
| TXBYPASS8B10B0 | input | TCELL5:IMUX.IMUX11.DELAY |
| TXBYPASS8B10B1 | input | TCELL5:IMUX.IMUX27.DELAY |
| TXBYPASS8B10B2 | input | TCELL5:IMUX.IMUX35.DELAY |
| TXBYPASS8B10B3 | input | TCELL5:IMUX.IMUX19.DELAY |
| TXCHARDISPMODE0 | input | TCELL5:IMUX.IMUX34.DELAY |
| TXCHARDISPMODE1 | input | TCELL5:IMUX.IMUX28.DELAY |
| TXCHARDISPMODE2 | input | TCELL5:IMUX.IMUX37.DELAY |
| TXCHARDISPMODE3 | input | TCELL5:IMUX.IMUX21.DELAY |
| TXCHARDISPVAL0 | input | TCELL5:IMUX.IMUX44.DELAY |
| TXCHARDISPVAL1 | input | TCELL5:IMUX.IMUX30.DELAY |
| TXCHARDISPVAL2 | input | TCELL5:IMUX.IMUX38.DELAY |
| TXCHARDISPVAL3 | input | TCELL5:IMUX.IMUX22.DELAY |
| TXCHARISK0 | input | TCELL5:IMUX.IMUX26.DELAY |
| TXCHARISK1 | input | TCELL5:IMUX.IMUX36.DELAY |
| TXCHARISK2 | input | TCELL5:IMUX.IMUX39.DELAY |
| TXCHARISK3 | input | TCELL5:IMUX.IMUX23.DELAY |
| TXCOMINIT | input | TCELL7:IMUX.IMUX18.DELAY |
| TXCOMSAS | input | TCELL7:IMUX.IMUX19.DELAY |
| TXCOMWAKE | input | TCELL7:IMUX.IMUX10.DELAY |
| TXDATA0 | input | TCELL8:IMUX.IMUX38.DELAY |
| TXDATA1 | input | TCELL8:IMUX.IMUX36.DELAY |
| TXDATA10 | input | TCELL7:IMUX.IMUX13.DELAY |
| TXDATA11 | input | TCELL7:IMUX.IMUX40.DELAY |
| TXDATA12 | input | TCELL6:IMUX.IMUX3.DELAY |
| TXDATA13 | input | TCELL6:IMUX.IMUX30.DELAY |
| TXDATA14 | input | TCELL6:IMUX.IMUX5.DELAY |
| TXDATA15 | input | TCELL6:IMUX.IMUX13.DELAY |
| TXDATA16 | input | TCELL8:IMUX.IMUX31.DELAY |
| TXDATA17 | input | TCELL8:IMUX.IMUX30.DELAY |
| TXDATA18 | input | TCELL8:IMUX.IMUX29.DELAY |
| TXDATA19 | input | TCELL8:IMUX.IMUX27.DELAY |
| TXDATA2 | input | TCELL8:IMUX.IMUX28.DELAY |
| TXDATA20 | input | TCELL7:IMUX.IMUX27.DELAY |
| TXDATA21 | input | TCELL7:IMUX.IMUX28.DELAY |
| TXDATA22 | input | TCELL7:IMUX.IMUX25.DELAY |
| TXDATA23 | input | TCELL7:IMUX.IMUX24.DELAY |
| TXDATA24 | input | TCELL8:IMUX.IMUX39.DELAY |
| TXDATA25 | input | TCELL8:IMUX.IMUX19.DELAY |
| TXDATA26 | input | TCELL8:IMUX.IMUX37.DELAY |
| TXDATA27 | input | TCELL8:IMUX.IMUX35.DELAY |
| TXDATA28 | input | TCELL7:IMUX.IMUX35.DELAY |
| TXDATA29 | input | TCELL7:IMUX.IMUX36.DELAY |
| TXDATA3 | input | TCELL8:IMUX.IMUX32.DELAY |
| TXDATA30 | input | TCELL7:IMUX.IMUX33.DELAY |
| TXDATA31 | input | TCELL7:IMUX.IMUX32.DELAY |
| TXDATA4 | input | TCELL8:IMUX.IMUX26.DELAY |
| TXDATA5 | input | TCELL8:IMUX.IMUX34.DELAY |
| TXDATA6 | input | TCELL7:IMUX.IMUX34.DELAY |
| TXDATA7 | input | TCELL7:IMUX.IMUX26.DELAY |
| TXDATA8 | input | TCELL7:IMUX.IMUX15.DELAY |
| TXDATA9 | input | TCELL7:IMUX.IMUX21.DELAY |
| TXDEEMPH | input | TCELL3:IMUX.IMUX3.DELAY |
| TXDETECTRX | input | TCELL4:IMUX.IMUX9.DELAY |
| TXDIFFCTRL0 | input | TCELL3:IMUX.IMUX21.DELAY |
| TXDIFFCTRL1 | input | TCELL3:IMUX.IMUX38.DELAY |
| TXDIFFCTRL2 | input | TCELL3:IMUX.IMUX5.DELAY |
| TXDIFFCTRL3 | input | TCELL3:IMUX.IMUX30.DELAY |
| TXDLYALIGNDISABLE | input | TCELL5:IMUX.IMUX46.DELAY |
| TXDLYALIGNFORCEROTATEB | input | TCELL7:IMUX.IMUX9.DELAY |
| TXDLYALIGNMONENB | input | TCELL7:IMUX.IMUX11.DELAY |
| TXDLYALIGNMONITOR0 | output | TCELL7:OUT21.TMIN |
| TXDLYALIGNMONITOR1 | output | TCELL7:OUT16.TMIN |
| TXDLYALIGNMONITOR2 | output | TCELL7:OUT4.TMIN |
| TXDLYALIGNMONITOR3 | output | TCELL7:OUT20.TMIN |
| TXDLYALIGNMONITOR4 | output | TCELL7:OUT23.TMIN |
| TXDLYALIGNMONITOR5 | output | TCELL7:OUT19.TMIN |
| TXDLYALIGNMONITOR6 | output | TCELL7:OUT18.TMIN |
| TXDLYALIGNMONITOR7 | output | TCELL7:OUT0.TMIN |
| TXDLYALIGNOVERRIDE | input | TCELL5:IMUX.IMUX25.DELAY |
| TXDLYALIGNRESET | input | TCELL5:IMUX.IMUX13.DELAY |
| TXDLYALIGNTESTMODEENB | input | TCELL7:IMUX.IMUX30.DELAY |
| TXDLYALIGNUPDSW | input | TCELL5:IMUX.IMUX2.DELAY |
| TXELECIDLE | input | TCELL4:IMUX.IMUX32.DELAY |
| TXENC8B10BUSE | input | TCELL7:IMUX.IMUX22.DELAY |
| TXENPMAPHASEALIGN | input | TCELL8:IMUX.IMUX17.DELAY |
| TXENPRBSTST0 | input | TCELL6:IMUX.IMUX39.DELAY |
| TXENPRBSTST1 | input | TCELL6:IMUX.IMUX23.DELAY |
| TXENPRBSTST2 | input | TCELL6:IMUX.IMUX15.DELAY |
| TXGEARBOXREADY | output | TCELL6:OUT4.TMIN |
| TXHEADER0 | input | TCELL5:IMUX.IMUX8.DELAY |
| TXHEADER1 | input | TCELL5:IMUX.IMUX16.DELAY |
| TXHEADER2 | input | TCELL5:IMUX.IMUX32.DELAY |
| TXINHIBIT | input | TCELL5:IMUX.IMUX17.DELAY |
| TXKERR0 | output | TCELL7:OUT14.TMIN |
| TXKERR1 | output | TCELL7:OUT10.TMIN |
| TXKERR2 | output | TCELL7:OUT11.TMIN |
| TXKERR3 | output | TCELL7:OUT15.TMIN |
| TXMARGIN0 | input | TCELL4:IMUX.IMUX11.DELAY |
| TXMARGIN1 | input | TCELL4:IMUX.IMUX26.DELAY |
| TXMARGIN2 | input | TCELL5:IMUX.IMUX15.DELAY |
| TXOUTCLKPCS | output | TCELL6:OUT8.TMIN |
| TXPDOWNASYNCH | input | TCELL8:IMUX.IMUX15.DELAY |
| TXPLLLKDET | output | TCELL8:OUT5.TMIN |
| TXPLLLKDETEN | input | TCELL7:IMUX.IMUX12.DELAY |
| TXPLLPOWERDOWN | input | TCELL7:IMUX.IMUX29.DELAY |
| TXPLLREFSELDY0 | input | TCELL7:IMUX.IMUX37.DELAY |
| TXPLLREFSELDY1 | input | TCELL7:IMUX.IMUX38.DELAY |
| TXPLLREFSELDY2 | input | TCELL7:IMUX.IMUX39.DELAY |
| TXPMASETPHASE | input | TCELL5:IMUX.IMUX18.DELAY |
| TXPOLARITY | input | TCELL5:IMUX.IMUX9.DELAY |
| TXPOSTEMPHASIS0 | input | TCELL8:IMUX.IMUX10.DELAY |
| TXPOSTEMPHASIS1 | input | TCELL8:IMUX.IMUX18.DELAY |
| TXPOSTEMPHASIS2 | input | TCELL8:IMUX.IMUX12.DELAY |
| TXPOSTEMPHASIS3 | input | TCELL8:IMUX.IMUX20.DELAY |
| TXPOSTEMPHASIS4 | input | TCELL8:IMUX.IMUX22.DELAY |
| TXPOWERDOWN0 | input | TCELL4:IMUX.IMUX28.DELAY |
| TXPOWERDOWN1 | input | TCELL4:IMUX.IMUX36.DELAY |
| TXPRBSFORCEERR | input | TCELL8:IMUX.IMUX13.DELAY |
| TXPREEMPHASIS0 | input | TCELL3:IMUX.IMUX26.DELAY |
| TXPREEMPHASIS1 | input | TCELL3:IMUX.IMUX19.DELAY |
| TXPREEMPHASIS2 | input | TCELL3:IMUX.IMUX17.DELAY |
| TXPREEMPHASIS3 | input | TCELL3:IMUX.IMUX9.DELAY |
| TXRATE0 | input | TCELL6:IMUX.IMUX34.DELAY |
| TXRATE1 | input | TCELL6:IMUX.IMUX33.DELAY |
| TXRATEDONE | output | TCELL6:OUT23.TMIN |
| TXRESET | input | TCELL6:IMUX.CTRL0 |
| TXRESETDONE | output | TCELL7:OUT22.TMIN |
| TXRUNDISP0 | output | TCELL8:OUT14.TMIN |
| TXRUNDISP1 | output | TCELL8:OUT10.TMIN |
| TXRUNDISP2 | output | TCELL8:OUT11.TMIN |
| TXRUNDISP3 | output | TCELL8:OUT15.TMIN |
| TXSEQUENCE0 | input | TCELL6:IMUX.IMUX11.DELAY |
| TXSEQUENCE1 | input | TCELL6:IMUX.IMUX19.DELAY |
| TXSEQUENCE2 | input | TCELL6:IMUX.IMUX35.DELAY |
| TXSEQUENCE3 | input | TCELL6:IMUX.IMUX8.DELAY |
| TXSEQUENCE4 | input | TCELL6:IMUX.IMUX24.DELAY |
| TXSEQUENCE5 | input | TCELL6:IMUX.IMUX22.DELAY |
| TXSEQUENCE6 | input | TCELL6:IMUX.IMUX38.DELAY |
| TXSTARTSEQ | input | TCELL7:IMUX.IMUX14.DELAY |
| TXSWING | input | TCELL3:IMUX.IMUX13.DELAY |
| TXUSRCLK | input | TCELL6:IMUX.CLK0 |
| TXUSRCLK2 | input | TCELL6:IMUX.CLK1 |
| USRCODEERR | input | TCELL2:IMUX.IMUX14.DELAY |
Bel GTX1
| Pin | Direction | Wires |
|---|---|---|
| CLKTESTSIG0 | input | TCELL12:IMUX.IMUX19.DELAY |
| CLKTESTSIG1 | input | TCELL12:IMUX.IMUX18.DELAY |
| COMFINISH | output | TCELL18:OUT18.TMIN |
| COMINITDET | output | TCELL12:OUT20.TMIN |
| COMSASDET | output | TCELL12:OUT19.TMIN |
| COMWAKEDET | output | TCELL12:OUT23.TMIN |
| DADDR0 | input | TCELL19:IMUX.IMUX32.DELAY |
| DADDR1 | input | TCELL19:IMUX.IMUX33.DELAY |
| DADDR2 | input | TCELL19:IMUX.IMUX34.DELAY |
| DADDR3 | input | TCELL19:IMUX.IMUX35.DELAY |
| DADDR4 | input | TCELL19:IMUX.IMUX36.DELAY |
| DADDR5 | input | TCELL19:IMUX.IMUX37.DELAY |
| DADDR6 | input | TCELL19:IMUX.IMUX38.DELAY |
| DADDR7 | input | TCELL19:IMUX.IMUX39.DELAY |
| DCLK | input | TCELL19:IMUX.CLK0 |
| DEN | input | TCELL18:IMUX.IMUX16.DELAY |
| DFECLKDLYADJ0 | input | TCELL14:IMUX.IMUX35.DELAY |
| DFECLKDLYADJ1 | input | TCELL14:IMUX.IMUX19.DELAY |
| DFECLKDLYADJ2 | input | TCELL14:IMUX.IMUX18.DELAY |
| DFECLKDLYADJ3 | input | TCELL14:IMUX.IMUX33.DELAY |
| DFECLKDLYADJ4 | input | TCELL14:IMUX.IMUX17.DELAY |
| DFECLKDLYADJ5 | input | TCELL14:IMUX.IMUX16.DELAY |
| DFECLKDLYADJMON0 | output | TCELL16:OUT5.TMIN |
| DFECLKDLYADJMON1 | output | TCELL16:OUT1.TMIN |
| DFECLKDLYADJMON2 | output | TCELL16:OUT2.TMIN |
| DFECLKDLYADJMON3 | output | TCELL16:OUT6.TMIN |
| DFECLKDLYADJMON4 | output | TCELL16:OUT7.TMIN |
| DFECLKDLYADJMON5 | output | TCELL16:OUT3.TMIN |
| DFEDLYOVRD | input | TCELL14:IMUX.IMUX29.DELAY |
| DFEEYEDACMON0 | output | TCELL16:OUT13.TMIN |
| DFEEYEDACMON1 | output | TCELL16:OUT14.TMIN |
| DFEEYEDACMON2 | output | TCELL16:OUT10.TMIN |
| DFEEYEDACMON3 | output | TCELL16:OUT11.TMIN |
| DFEEYEDACMON4 | output | TCELL16:OUT15.TMIN |
| DFESENSCAL0 | output | TCELL16:OUT19.TMIN |
| DFESENSCAL1 | output | TCELL16:OUT18.TMIN |
| DFESENSCAL2 | output | TCELL16:OUT22.TMIN |
| DFETAP10 | input | TCELL14:IMUX.IMUX8.DELAY |
| DFETAP11 | input | TCELL14:IMUX.IMUX10.DELAY |
| DFETAP12 | input | TCELL14:IMUX.IMUX14.DELAY |
| DFETAP13 | input | TCELL14:IMUX.IMUX15.DELAY |
| DFETAP14 | input | TCELL14:IMUX.IMUX38.DELAY |
| DFETAP1MONITOR0 | output | TCELL18:OUT1.TMIN |
| DFETAP1MONITOR1 | output | TCELL18:OUT2.TMIN |
| DFETAP1MONITOR2 | output | TCELL18:OUT6.TMIN |
| DFETAP1MONITOR3 | output | TCELL18:OUT7.TMIN |
| DFETAP1MONITOR4 | output | TCELL18:OUT3.TMIN |
| DFETAP20 | input | TCELL14:IMUX.IMUX24.DELAY |
| DFETAP21 | input | TCELL14:IMUX.IMUX25.DELAY |
| DFETAP22 | input | TCELL14:IMUX.IMUX30.DELAY |
| DFETAP23 | input | TCELL14:IMUX.IMUX31.DELAY |
| DFETAP24 | input | TCELL14:IMUX.IMUX39.DELAY |
| DFETAP2MONITOR0 | output | TCELL17:OUT1.TMIN |
| DFETAP2MONITOR1 | output | TCELL17:OUT2.TMIN |
| DFETAP2MONITOR2 | output | TCELL17:OUT6.TMIN |
| DFETAP2MONITOR3 | output | TCELL17:OUT7.TMIN |
| DFETAP2MONITOR4 | output | TCELL17:OUT3.TMIN |
| DFETAP30 | input | TCELL16:IMUX.IMUX10.DELAY |
| DFETAP31 | input | TCELL16:IMUX.IMUX9.DELAY |
| DFETAP32 | input | TCELL16:IMUX.IMUX12.DELAY |
| DFETAP33 | input | TCELL16:IMUX.IMUX17.DELAY |
| DFETAP3MONITOR0 | output | TCELL18:OUT12.TMIN |
| DFETAP3MONITOR1 | output | TCELL18:OUT8.TMIN |
| DFETAP3MONITOR2 | output | TCELL18:OUT9.TMIN |
| DFETAP3MONITOR3 | output | TCELL18:OUT13.TMIN |
| DFETAP40 | input | TCELL16:IMUX.IMUX26.DELAY |
| DFETAP41 | input | TCELL16:IMUX.IMUX25.DELAY |
| DFETAP42 | input | TCELL16:IMUX.IMUX28.DELAY |
| DFETAP43 | input | TCELL16:IMUX.IMUX20.DELAY |
| DFETAP4MONITOR0 | output | TCELL17:OUT12.TMIN |
| DFETAP4MONITOR1 | output | TCELL17:OUT8.TMIN |
| DFETAP4MONITOR2 | output | TCELL17:OUT9.TMIN |
| DFETAP4MONITOR3 | output | TCELL17:OUT13.TMIN |
| DFETAPOVRD | input | TCELL14:IMUX.IMUX37.DELAY |
| DI0 | input | TCELL19:IMUX.IMUX8.DELAY |
| DI1 | input | TCELL19:IMUX.IMUX9.DELAY |
| DI10 | input | TCELL19:IMUX.IMUX18.DELAY |
| DI11 | input | TCELL19:IMUX.IMUX19.DELAY |
| DI12 | input | TCELL19:IMUX.IMUX20.DELAY |
| DI13 | input | TCELL19:IMUX.IMUX21.DELAY |
| DI14 | input | TCELL19:IMUX.IMUX22.DELAY |
| DI15 | input | TCELL19:IMUX.IMUX23.DELAY |
| DI2 | input | TCELL19:IMUX.IMUX10.DELAY |
| DI3 | input | TCELL19:IMUX.IMUX11.DELAY |
| DI4 | input | TCELL19:IMUX.IMUX12.DELAY |
| DI5 | input | TCELL19:IMUX.IMUX13.DELAY |
| DI6 | input | TCELL19:IMUX.IMUX14.DELAY |
| DI7 | input | TCELL19:IMUX.IMUX15.DELAY |
| DI8 | input | TCELL19:IMUX.IMUX16.DELAY |
| DI9 | input | TCELL19:IMUX.IMUX17.DELAY |
| DRDY | output | TCELL18:OUT0.TMIN |
| DRPDO0 | output | TCELL19:OUT3.TMIN |
| DRPDO1 | output | TCELL19:OUT7.TMIN |
| DRPDO10 | output | TCELL19:OUT10.TMIN |
| DRPDO11 | output | TCELL19:OUT14.TMIN |
| DRPDO12 | output | TCELL19:OUT13.TMIN |
| DRPDO13 | output | TCELL19:OUT9.TMIN |
| DRPDO14 | output | TCELL19:OUT8.TMIN |
| DRPDO15 | output | TCELL19:OUT12.TMIN |
| DRPDO2 | output | TCELL19:OUT6.TMIN |
| DRPDO3 | output | TCELL19:OUT2.TMIN |
| DRPDO4 | output | TCELL19:OUT1.TMIN |
| DRPDO5 | output | TCELL19:OUT5.TMIN |
| DRPDO6 | output | TCELL19:OUT4.TMIN |
| DRPDO7 | output | TCELL19:OUT0.TMIN |
| DRPDO8 | output | TCELL19:OUT15.TMIN |
| DRPDO9 | output | TCELL19:OUT11.TMIN |
| DWE | input | TCELL18:IMUX.IMUX8.DELAY |
| GATERXELECIDLE | input | TCELL16:IMUX.IMUX32.DELAY |
| GREFCLKRX | input | TCELL13:IMUX.CLK0 |
| GREFCLKTX | input | TCELL17:IMUX.CLK0 |
| GTXRXRESET | input | TCELL11:IMUX.CTRL0 |
| GTXTEST0 | input | TCELL12:IMUX.IMUX39.DELAY |
| GTXTEST1 | input | TCELL12:IMUX.IMUX38.DELAY |
| GTXTEST10 | input | TCELL12:IMUX.IMUX29.DELAY |
| GTXTEST11 | input | TCELL12:IMUX.IMUX28.DELAY |
| GTXTEST12 | input | TCELL12:IMUX.IMUX27.DELAY |
| GTXTEST2 | input | TCELL12:IMUX.IMUX37.DELAY |
| GTXTEST3 | input | TCELL12:IMUX.IMUX36.DELAY |
| GTXTEST4 | input | TCELL12:IMUX.IMUX35.DELAY |
| GTXTEST5 | input | TCELL12:IMUX.IMUX34.DELAY |
| GTXTEST6 | input | TCELL12:IMUX.IMUX33.DELAY |
| GTXTEST7 | input | TCELL12:IMUX.IMUX32.DELAY |
| GTXTEST8 | input | TCELL12:IMUX.IMUX31.DELAY |
| GTXTEST9 | input | TCELL12:IMUX.IMUX30.DELAY |
| GTXTXRESET | input | TCELL16:IMUX.CTRL1 |
| IGNORESIGDET | input | TCELL16:IMUX.IMUX37.DELAY |
| LOOPBACK0 | input | TCELL13:IMUX.IMUX24.DELAY |
| LOOPBACK1 | input | TCELL13:IMUX.IMUX11.DELAY |
| LOOPBACK2 | input | TCELL13:IMUX.IMUX27.DELAY |
| MGTREFCLKFAB0 | output | TCELL14:OUT0.TMIN |
| MGTREFCLKFAB1 | output | TCELL14:OUT12.TMIN |
| PHYSTATUS | output | TCELL14:OUT8.TMIN |
| PLLRXRESET | input | TCELL13:IMUX.CTRL0 |
| PLLTXRESET | input | TCELL15:IMUX.CTRL1 |
| PRBSCNTRESET | input | TCELL10:IMUX.CTRL1 |
| RXBUFRESET | input | TCELL12:IMUX.CTRL0 |
| RXBUFSTATUS0 | output | TCELL14:OUT6.TMIN |
| RXBUFSTATUS1 | output | TCELL14:OUT7.TMIN |
| RXBUFSTATUS2 | output | TCELL14:OUT3.TMIN |
| RXBUFWE | input | TCELL11:IMUX.IMUX24.DELAY |
| RXBYTEISALIGNED | output | TCELL12:OUT13.TMIN |
| RXBYTEREALIGN | output | TCELL12:OUT10.TMIN |
| RXCDRRESET | input | TCELL11:IMUX.CTRL1 |
| RXCHANBONDSEQ | output | TCELL15:OUT14.TMIN |
| RXCHANISALIGNED | output | TCELL13:OUT13.TMIN |
| RXCHANREALIGN | output | TCELL12:OUT14.TMIN |
| RXCHARISCOMMA0 | output | TCELL13:OUT14.TMIN |
| RXCHARISCOMMA1 | output | TCELL13:OUT2.TMIN |
| RXCHARISCOMMA2 | output | TCELL12:OUT8.TMIN |
| RXCHARISCOMMA3 | output | TCELL12:OUT18.TMIN |
| RXCHARISK0 | output | TCELL13:OUT16.TMIN |
| RXCHARISK1 | output | TCELL12:OUT5.TMIN |
| RXCHARISK2 | output | TCELL12:OUT15.TMIN |
| RXCHARISK3 | output | TCELL12:OUT3.TMIN |
| RXCHBONDI0 | input | TCELL13:IMUX.IMUX32.DELAY |
| RXCHBONDI1 | input | TCELL13:IMUX.IMUX33.DELAY |
| RXCHBONDI2 | input | TCELL13:IMUX.IMUX34.DELAY |
| RXCHBONDI3 | input | TCELL13:IMUX.IMUX35.DELAY |
| RXCHBONDLEVEL0 | input | TCELL12:IMUX.IMUX10.DELAY |
| RXCHBONDLEVEL1 | input | TCELL12:IMUX.IMUX26.DELAY |
| RXCHBONDLEVEL2 | input | TCELL12:IMUX.IMUX11.DELAY |
| RXCHBONDMASTER | input | TCELL12:IMUX.IMUX24.DELAY |
| RXCHBONDO0 | output | TCELL14:OUT17.TMIN |
| RXCHBONDO1 | output | TCELL14:OUT10.TMIN |
| RXCHBONDO2 | output | TCELL14:OUT11.TMIN |
| RXCHBONDO3 | output | TCELL14:OUT15.TMIN |
| RXCHBONDSLAVE | input | TCELL12:IMUX.IMUX8.DELAY |
| RXCLKCORCNT0 | output | TCELL15:OUT8.TMIN |
| RXCLKCORCNT1 | output | TCELL15:OUT9.TMIN |
| RXCLKCORCNT2 | output | TCELL15:OUT6.TMIN |
| RXCOMMADET | output | TCELL15:OUT12.TMIN |
| RXCOMMADETUSE | input | TCELL13:IMUX.IMUX36.DELAY |
| RXDATA0 | output | TCELL10:OUT4.TMIN |
| RXDATA1 | output | TCELL10:OUT7.TMIN |
| RXDATA10 | output | TCELL11:OUT6.TMIN |
| RXDATA11 | output | TCELL11:OUT2.TMIN |
| RXDATA12 | output | TCELL12:OUT7.TMIN |
| RXDATA13 | output | TCELL12:OUT6.TMIN |
| RXDATA14 | output | TCELL12:OUT2.TMIN |
| RXDATA15 | output | TCELL12:OUT1.TMIN |
| RXDATA16 | output | TCELL10:OUT15.TMIN |
| RXDATA17 | output | TCELL10:OUT3.TMIN |
| RXDATA18 | output | TCELL10:OUT0.TMIN |
| RXDATA19 | output | TCELL10:OUT22.TMIN |
| RXDATA2 | output | TCELL10:OUT6.TMIN |
| RXDATA20 | output | TCELL10:OUT18.TMIN |
| RXDATA21 | output | TCELL10:OUT17.TMIN |
| RXDATA22 | output | TCELL10:OUT16.TMIN |
| RXDATA23 | output | TCELL10:OUT20.TMIN |
| RXDATA24 | output | TCELL11:OUT0.TMIN |
| RXDATA25 | output | TCELL11:OUT22.TMIN |
| RXDATA26 | output | TCELL11:OUT18.TMIN |
| RXDATA27 | output | TCELL11:OUT9.TMIN |
| RXDATA28 | output | TCELL11:OUT16.TMIN |
| RXDATA29 | output | TCELL11:OUT11.TMIN |
| RXDATA3 | output | TCELL10:OUT2.TMIN |
| RXDATA30 | output | TCELL11:OUT15.TMIN |
| RXDATA31 | output | TCELL11:OUT3.TMIN |
| RXDATA4 | output | TCELL10:OUT1.TMIN |
| RXDATA5 | output | TCELL10:OUT5.TMIN |
| RXDATA6 | output | TCELL11:OUT1.TMIN |
| RXDATA7 | output | TCELL11:OUT5.TMIN |
| RXDATA8 | output | TCELL11:OUT4.TMIN |
| RXDATA9 | output | TCELL11:OUT7.TMIN |
| RXDATAVALID | output | TCELL12:OUT4.TMIN |
| RXDEC8B10BUSE | input | TCELL11:IMUX.IMUX39.DELAY |
| RXDISPERR0 | output | TCELL13:OUT4.TMIN |
| RXDISPERR1 | output | TCELL13:OUT8.TMIN |
| RXDISPERR2 | output | TCELL13:OUT0.TMIN |
| RXDISPERR3 | output | TCELL13:OUT22.TMIN |
| RXDLYALIGNDISABLE | input | TCELL15:IMUX.IMUX14.DELAY |
| RXDLYALIGNFORCEROTATEB | input | TCELL13:IMUX.IMUX25.DELAY |
| RXDLYALIGNMONENB | input | TCELL13:IMUX.IMUX28.DELAY |
| RXDLYALIGNMONITOR0 | output | TCELL15:OUT21.TMIN |
| RXDLYALIGNMONITOR1 | output | TCELL15:OUT15.TMIN |
| RXDLYALIGNMONITOR2 | output | TCELL15:OUT7.TMIN |
| RXDLYALIGNMONITOR3 | output | TCELL15:OUT20.TMIN |
| RXDLYALIGNMONITOR4 | output | TCELL15:OUT23.TMIN |
| RXDLYALIGNMONITOR5 | output | TCELL15:OUT19.TMIN |
| RXDLYALIGNMONITOR6 | output | TCELL15:OUT18.TMIN |
| RXDLYALIGNMONITOR7 | output | TCELL15:OUT0.TMIN |
| RXDLYALIGNOVERRIDE | input | TCELL15:IMUX.IMUX33.DELAY |
| RXDLYALIGNRESET | input | TCELL15:IMUX.IMUX29.DELAY |
| RXDLYALIGNSWPPRECURB | input | TCELL13:IMUX.IMUX29.DELAY |
| RXDLYALIGNTESTMODEENB | input | TCELL13:IMUX.IMUX12.DELAY |
| RXDLYALIGNUPDSW | input | TCELL15:IMUX.IMUX10.DELAY |
| RXELECIDLE | output | TCELL15:OUT3.TMIN |
| RXENCHANSYNC | input | TCELL11:IMUX.IMUX38.DELAY |
| RXENMCOMMAALIGN | input | TCELL11:IMUX.IMUX36.DELAY |
| RXENPCOMMAALIGN | input | TCELL11:IMUX.IMUX37.DELAY |
| RXENPMAPHASEALIGN | input | TCELL11:IMUX.IMUX35.DELAY |
| RXENPRBSTST0 | input | TCELL11:IMUX.IMUX33.DELAY |
| RXENPRBSTST1 | input | TCELL11:IMUX.IMUX34.DELAY |
| RXENPRBSTST2 | input | TCELL11:IMUX.IMUX18.DELAY |
| RXENSAMPLEALIGN | input | TCELL11:IMUX.IMUX32.DELAY |
| RXEQMIX0 | input | TCELL11:IMUX.IMUX14.DELAY |
| RXEQMIX1 | input | TCELL11:IMUX.IMUX15.DELAY |
| RXEQMIX2 | input | TCELL11:IMUX.IMUX30.DELAY |
| RXEQMIX3 | input | TCELL11:IMUX.IMUX22.DELAY |
| RXEQMIX4 | input | TCELL11:IMUX.IMUX29.DELAY |
| RXEQMIX5 | input | TCELL11:IMUX.IMUX21.DELAY |
| RXEQMIX6 | input | TCELL11:IMUX.IMUX28.DELAY |
| RXEQMIX7 | input | TCELL11:IMUX.IMUX20.DELAY |
| RXEQMIX8 | input | TCELL11:IMUX.IMUX27.DELAY |
| RXEQMIX9 | input | TCELL11:IMUX.IMUX19.DELAY |
| RXGEARBOXSLIP | input | TCELL11:IMUX.IMUX12.DELAY |
| RXHEADER0 | output | TCELL15:OUT10.TMIN |
| RXHEADER1 | output | TCELL15:OUT16.TMIN |
| RXHEADER2 | output | TCELL15:OUT17.TMIN |
| RXHEADERVALID | output | TCELL15:OUT11.TMIN |
| RXLOSSOFSYNC0 | output | TCELL12:OUT0.TMIN |
| RXLOSSOFSYNC1 | output | TCELL12:OUT22.TMIN |
| RXNOTINTABLE0 | output | TCELL13:OUT11.TMIN |
| RXNOTINTABLE1 | output | TCELL13:OUT7.TMIN |
| RXNOTINTABLE2 | output | TCELL13:OUT15.TMIN |
| RXNOTINTABLE3 | output | TCELL13:OUT3.TMIN |
| RXOVERSAMPLEERR | output | TCELL14:OUT22.TMIN |
| RXPLLLKDET | output | TCELL14:OUT5.TMIN |
| RXPLLLKDETEN | input | TCELL12:IMUX.IMUX20.DELAY |
| RXPLLPOWERDOWN | input | TCELL12:IMUX.IMUX21.DELAY |
| RXPLLREFSELDY0 | input | TCELL13:IMUX.IMUX37.DELAY |
| RXPLLREFSELDY1 | input | TCELL13:IMUX.IMUX22.DELAY |
| RXPLLREFSELDY2 | input | TCELL13:IMUX.IMUX39.DELAY |
| RXPMASETPHASE | input | TCELL11:IMUX.IMUX11.DELAY |
| RXPOLARITY | input | TCELL11:IMUX.IMUX26.DELAY |
| RXPOWERDOWN0 | input | TCELL14:IMUX.IMUX13.DELAY |
| RXPOWERDOWN1 | input | TCELL14:IMUX.IMUX21.DELAY |
| RXPRBSERR | output | TCELL15:OUT2.TMIN |
| RXRATE0 | input | TCELL16:IMUX.IMUX42.DELAY |
| RXRATE1 | input | TCELL16:IMUX.IMUX41.DELAY |
| RXRATEDONE | output | TCELL16:OUT20.TMIN |
| RXRECCLKPCS | output | TCELL15:OUT5.TMIN |
| RXRESET | input | TCELL12:IMUX.CTRL1 |
| RXRESETDONE | output | TCELL15:OUT22.TMIN |
| RXRUNDISP0 | output | TCELL13:OUT9.TMIN |
| RXRUNDISP1 | output | TCELL13:OUT5.TMIN |
| RXRUNDISP2 | output | TCELL13:OUT19.TMIN |
| RXRUNDISP3 | output | TCELL13:OUT1.TMIN |
| RXSLIDE | input | TCELL11:IMUX.IMUX9.DELAY |
| RXSTARTOFSEQ | output | TCELL15:OUT1.TMIN |
| RXSTATUS0 | output | TCELL14:OUT14.TMIN |
| RXSTATUS1 | output | TCELL14:OUT16.TMIN |
| RXSTATUS2 | output | TCELL14:OUT13.TMIN |
| RXUSRCLK | input | TCELL12:IMUX.CLK0 |
| RXUSRCLK2 | input | TCELL12:IMUX.CLK1 |
| RXVALID | output | TCELL15:OUT4.TMIN |
| SCANCLK | input | TCELL14:IMUX.CLK1 |
| SCANENB | input | TCELL10:IMUX.IMUX37.DELAY |
| SCANIN0 | input | TCELL18:IMUX.IMUX33.DELAY |
| SCANIN1 | input | TCELL18:IMUX.IMUX25.DELAY |
| SCANIN2 | input | TCELL10:IMUX.IMUX38.DELAY |
| SCANIN3 | input | TCELL10:IMUX.IMUX22.DELAY |
| SCANIN4 | input | TCELL18:IMUX.IMUX9.DELAY |
| SCANMODEB | input | TCELL10:IMUX.IMUX29.DELAY |
| SCANOUT0 | output | TCELL14:OUT18.TMIN |
| SCANOUT1 | output | TCELL14:OUT4.TMIN |
| SCANOUT2 | output | TCELL10:OUT23.TMIN |
| SCANOUT3 | output | TCELL10:OUT13.TMIN |
| SCANOUT4 | output | TCELL10:OUT8.TMIN |
| TSTCLK0 | input | TCELL13:IMUX.CLK1 |
| TSTCLK1 | input | TCELL15:IMUX.CLK1 |
| TSTIN0 | input | TCELL10:IMUX.IMUX30.DELAY |
| TSTIN1 | input | TCELL10:IMUX.IMUX14.DELAY |
| TSTIN10 | input | TCELL10:IMUX.IMUX31.DELAY |
| TSTIN11 | input | TCELL10:IMUX.IMUX21.DELAY |
| TSTIN12 | input | TCELL10:IMUX.IMUX13.DELAY |
| TSTIN13 | input | TCELL10:IMUX.IMUX28.DELAY |
| TSTIN14 | input | TCELL10:IMUX.IMUX32.DELAY |
| TSTIN15 | input | TCELL10:IMUX.IMUX16.DELAY |
| TSTIN16 | input | TCELL10:IMUX.IMUX40.DELAY |
| TSTIN17 | input | TCELL10:IMUX.IMUX0.DELAY |
| TSTIN18 | input | TCELL10:IMUX.IMUX1.DELAY |
| TSTIN19 | input | TCELL10:IMUX.IMUX41.DELAY |
| TSTIN2 | input | TCELL10:IMUX.IMUX27.DELAY |
| TSTIN3 | input | TCELL10:IMUX.IMUX11.DELAY |
| TSTIN4 | input | TCELL10:IMUX.IMUX26.DELAY |
| TSTIN5 | input | TCELL10:IMUX.IMUX10.DELAY |
| TSTIN6 | input | TCELL10:IMUX.IMUX25.DELAY |
| TSTIN7 | input | TCELL10:IMUX.IMUX9.DELAY |
| TSTIN8 | input | TCELL10:IMUX.IMUX24.DELAY |
| TSTIN9 | input | TCELL10:IMUX.IMUX8.DELAY |
| TSTOUT0 | output | TCELL11:OUT21.TMIN |
| TSTOUT1 | output | TCELL11:OUT17.TMIN |
| TSTOUT2 | output | TCELL11:OUT10.TMIN |
| TSTOUT3 | output | TCELL11:OUT20.TMIN |
| TSTOUT4 | output | TCELL11:OUT14.TMIN |
| TSTOUT5 | output | TCELL11:OUT23.TMIN |
| TSTOUT6 | output | TCELL11:OUT13.TMIN |
| TSTOUT7 | output | TCELL11:OUT19.TMIN |
| TSTOUT8 | output | TCELL11:OUT8.TMIN |
| TSTOUT9 | output | TCELL11:OUT12.TMIN |
| TSTPWRDN0 | input | TCELL10:IMUX.IMUX33.DELAY |
| TSTPWRDN1 | input | TCELL10:IMUX.IMUX18.DELAY |
| TSTPWRDN2 | input | TCELL10:IMUX.IMUX34.DELAY |
| TSTPWRDN3 | input | TCELL10:IMUX.IMUX19.DELAY |
| TSTPWRDN4 | input | TCELL10:IMUX.IMUX35.DELAY |
| TSTPWRDNOVRD | input | TCELL10:IMUX.IMUX17.DELAY |
| TXBUFDIFFCTRL0 | input | TCELL13:IMUX.IMUX0.DELAY |
| TXBUFDIFFCTRL1 | input | TCELL13:IMUX.IMUX16.DELAY |
| TXBUFDIFFCTRL2 | input | TCELL13:IMUX.IMUX18.DELAY |
| TXBUFSTATUS0 | output | TCELL17:OUT5.TMIN |
| TXBUFSTATUS1 | output | TCELL17:OUT17.TMIN |
| TXBYPASS8B10B0 | input | TCELL15:IMUX.IMUX11.DELAY |
| TXBYPASS8B10B1 | input | TCELL15:IMUX.IMUX27.DELAY |
| TXBYPASS8B10B2 | input | TCELL15:IMUX.IMUX35.DELAY |
| TXBYPASS8B10B3 | input | TCELL15:IMUX.IMUX19.DELAY |
| TXCHARDISPMODE0 | input | TCELL15:IMUX.IMUX34.DELAY |
| TXCHARDISPMODE1 | input | TCELL15:IMUX.IMUX28.DELAY |
| TXCHARDISPMODE2 | input | TCELL15:IMUX.IMUX37.DELAY |
| TXCHARDISPMODE3 | input | TCELL15:IMUX.IMUX21.DELAY |
| TXCHARDISPVAL0 | input | TCELL15:IMUX.IMUX44.DELAY |
| TXCHARDISPVAL1 | input | TCELL15:IMUX.IMUX30.DELAY |
| TXCHARDISPVAL2 | input | TCELL15:IMUX.IMUX38.DELAY |
| TXCHARDISPVAL3 | input | TCELL15:IMUX.IMUX22.DELAY |
| TXCHARISK0 | input | TCELL15:IMUX.IMUX26.DELAY |
| TXCHARISK1 | input | TCELL15:IMUX.IMUX36.DELAY |
| TXCHARISK2 | input | TCELL15:IMUX.IMUX39.DELAY |
| TXCHARISK3 | input | TCELL15:IMUX.IMUX23.DELAY |
| TXCOMINIT | input | TCELL17:IMUX.IMUX18.DELAY |
| TXCOMSAS | input | TCELL17:IMUX.IMUX19.DELAY |
| TXCOMWAKE | input | TCELL17:IMUX.IMUX10.DELAY |
| TXDATA0 | input | TCELL18:IMUX.IMUX38.DELAY |
| TXDATA1 | input | TCELL18:IMUX.IMUX36.DELAY |
| TXDATA10 | input | TCELL17:IMUX.IMUX13.DELAY |
| TXDATA11 | input | TCELL17:IMUX.IMUX40.DELAY |
| TXDATA12 | input | TCELL16:IMUX.IMUX3.DELAY |
| TXDATA13 | input | TCELL16:IMUX.IMUX30.DELAY |
| TXDATA14 | input | TCELL16:IMUX.IMUX5.DELAY |
| TXDATA15 | input | TCELL16:IMUX.IMUX13.DELAY |
| TXDATA16 | input | TCELL18:IMUX.IMUX31.DELAY |
| TXDATA17 | input | TCELL18:IMUX.IMUX30.DELAY |
| TXDATA18 | input | TCELL18:IMUX.IMUX29.DELAY |
| TXDATA19 | input | TCELL18:IMUX.IMUX27.DELAY |
| TXDATA2 | input | TCELL18:IMUX.IMUX28.DELAY |
| TXDATA20 | input | TCELL17:IMUX.IMUX27.DELAY |
| TXDATA21 | input | TCELL17:IMUX.IMUX28.DELAY |
| TXDATA22 | input | TCELL17:IMUX.IMUX25.DELAY |
| TXDATA23 | input | TCELL17:IMUX.IMUX24.DELAY |
| TXDATA24 | input | TCELL18:IMUX.IMUX39.DELAY |
| TXDATA25 | input | TCELL18:IMUX.IMUX19.DELAY |
| TXDATA26 | input | TCELL18:IMUX.IMUX37.DELAY |
| TXDATA27 | input | TCELL18:IMUX.IMUX35.DELAY |
| TXDATA28 | input | TCELL17:IMUX.IMUX35.DELAY |
| TXDATA29 | input | TCELL17:IMUX.IMUX36.DELAY |
| TXDATA3 | input | TCELL18:IMUX.IMUX32.DELAY |
| TXDATA30 | input | TCELL17:IMUX.IMUX33.DELAY |
| TXDATA31 | input | TCELL17:IMUX.IMUX32.DELAY |
| TXDATA4 | input | TCELL18:IMUX.IMUX26.DELAY |
| TXDATA5 | input | TCELL18:IMUX.IMUX34.DELAY |
| TXDATA6 | input | TCELL17:IMUX.IMUX34.DELAY |
| TXDATA7 | input | TCELL17:IMUX.IMUX26.DELAY |
| TXDATA8 | input | TCELL17:IMUX.IMUX15.DELAY |
| TXDATA9 | input | TCELL17:IMUX.IMUX21.DELAY |
| TXDEEMPH | input | TCELL13:IMUX.IMUX3.DELAY |
| TXDETECTRX | input | TCELL14:IMUX.IMUX9.DELAY |
| TXDIFFCTRL0 | input | TCELL13:IMUX.IMUX21.DELAY |
| TXDIFFCTRL1 | input | TCELL13:IMUX.IMUX38.DELAY |
| TXDIFFCTRL2 | input | TCELL13:IMUX.IMUX5.DELAY |
| TXDIFFCTRL3 | input | TCELL13:IMUX.IMUX30.DELAY |
| TXDLYALIGNDISABLE | input | TCELL15:IMUX.IMUX46.DELAY |
| TXDLYALIGNFORCEROTATEB | input | TCELL17:IMUX.IMUX9.DELAY |
| TXDLYALIGNMONENB | input | TCELL17:IMUX.IMUX11.DELAY |
| TXDLYALIGNMONITOR0 | output | TCELL17:OUT21.TMIN |
| TXDLYALIGNMONITOR1 | output | TCELL17:OUT16.TMIN |
| TXDLYALIGNMONITOR2 | output | TCELL17:OUT4.TMIN |
| TXDLYALIGNMONITOR3 | output | TCELL17:OUT20.TMIN |
| TXDLYALIGNMONITOR4 | output | TCELL17:OUT23.TMIN |
| TXDLYALIGNMONITOR5 | output | TCELL17:OUT19.TMIN |
| TXDLYALIGNMONITOR6 | output | TCELL17:OUT18.TMIN |
| TXDLYALIGNMONITOR7 | output | TCELL17:OUT0.TMIN |
| TXDLYALIGNOVERRIDE | input | TCELL15:IMUX.IMUX25.DELAY |
| TXDLYALIGNRESET | input | TCELL15:IMUX.IMUX13.DELAY |
| TXDLYALIGNTESTMODEENB | input | TCELL17:IMUX.IMUX30.DELAY |
| TXDLYALIGNUPDSW | input | TCELL15:IMUX.IMUX2.DELAY |
| TXELECIDLE | input | TCELL14:IMUX.IMUX32.DELAY |
| TXENC8B10BUSE | input | TCELL17:IMUX.IMUX22.DELAY |
| TXENPMAPHASEALIGN | input | TCELL18:IMUX.IMUX17.DELAY |
| TXENPRBSTST0 | input | TCELL16:IMUX.IMUX39.DELAY |
| TXENPRBSTST1 | input | TCELL16:IMUX.IMUX23.DELAY |
| TXENPRBSTST2 | input | TCELL16:IMUX.IMUX15.DELAY |
| TXGEARBOXREADY | output | TCELL16:OUT4.TMIN |
| TXHEADER0 | input | TCELL15:IMUX.IMUX8.DELAY |
| TXHEADER1 | input | TCELL15:IMUX.IMUX16.DELAY |
| TXHEADER2 | input | TCELL15:IMUX.IMUX32.DELAY |
| TXINHIBIT | input | TCELL15:IMUX.IMUX17.DELAY |
| TXKERR0 | output | TCELL17:OUT14.TMIN |
| TXKERR1 | output | TCELL17:OUT10.TMIN |
| TXKERR2 | output | TCELL17:OUT11.TMIN |
| TXKERR3 | output | TCELL17:OUT15.TMIN |
| TXMARGIN0 | input | TCELL14:IMUX.IMUX11.DELAY |
| TXMARGIN1 | input | TCELL14:IMUX.IMUX26.DELAY |
| TXMARGIN2 | input | TCELL15:IMUX.IMUX15.DELAY |
| TXOUTCLKPCS | output | TCELL16:OUT8.TMIN |
| TXPDOWNASYNCH | input | TCELL18:IMUX.IMUX15.DELAY |
| TXPLLLKDET | output | TCELL18:OUT5.TMIN |
| TXPLLLKDETEN | input | TCELL17:IMUX.IMUX12.DELAY |
| TXPLLPOWERDOWN | input | TCELL17:IMUX.IMUX29.DELAY |
| TXPLLREFSELDY0 | input | TCELL17:IMUX.IMUX37.DELAY |
| TXPLLREFSELDY1 | input | TCELL17:IMUX.IMUX38.DELAY |
| TXPLLREFSELDY2 | input | TCELL17:IMUX.IMUX39.DELAY |
| TXPMASETPHASE | input | TCELL15:IMUX.IMUX18.DELAY |
| TXPOLARITY | input | TCELL15:IMUX.IMUX9.DELAY |
| TXPOSTEMPHASIS0 | input | TCELL18:IMUX.IMUX10.DELAY |
| TXPOSTEMPHASIS1 | input | TCELL18:IMUX.IMUX18.DELAY |
| TXPOSTEMPHASIS2 | input | TCELL18:IMUX.IMUX12.DELAY |
| TXPOSTEMPHASIS3 | input | TCELL18:IMUX.IMUX20.DELAY |
| TXPOSTEMPHASIS4 | input | TCELL18:IMUX.IMUX22.DELAY |
| TXPOWERDOWN0 | input | TCELL14:IMUX.IMUX28.DELAY |
| TXPOWERDOWN1 | input | TCELL14:IMUX.IMUX36.DELAY |
| TXPRBSFORCEERR | input | TCELL18:IMUX.IMUX13.DELAY |
| TXPREEMPHASIS0 | input | TCELL13:IMUX.IMUX26.DELAY |
| TXPREEMPHASIS1 | input | TCELL13:IMUX.IMUX19.DELAY |
| TXPREEMPHASIS2 | input | TCELL13:IMUX.IMUX17.DELAY |
| TXPREEMPHASIS3 | input | TCELL13:IMUX.IMUX9.DELAY |
| TXRATE0 | input | TCELL16:IMUX.IMUX34.DELAY |
| TXRATE1 | input | TCELL16:IMUX.IMUX33.DELAY |
| TXRATEDONE | output | TCELL16:OUT23.TMIN |
| TXRESET | input | TCELL16:IMUX.CTRL0 |
| TXRESETDONE | output | TCELL17:OUT22.TMIN |
| TXRUNDISP0 | output | TCELL18:OUT14.TMIN |
| TXRUNDISP1 | output | TCELL18:OUT10.TMIN |
| TXRUNDISP2 | output | TCELL18:OUT11.TMIN |
| TXRUNDISP3 | output | TCELL18:OUT15.TMIN |
| TXSEQUENCE0 | input | TCELL16:IMUX.IMUX11.DELAY |
| TXSEQUENCE1 | input | TCELL16:IMUX.IMUX19.DELAY |
| TXSEQUENCE2 | input | TCELL16:IMUX.IMUX35.DELAY |
| TXSEQUENCE3 | input | TCELL16:IMUX.IMUX8.DELAY |
| TXSEQUENCE4 | input | TCELL16:IMUX.IMUX24.DELAY |
| TXSEQUENCE5 | input | TCELL16:IMUX.IMUX22.DELAY |
| TXSEQUENCE6 | input | TCELL16:IMUX.IMUX38.DELAY |
| TXSTARTSEQ | input | TCELL17:IMUX.IMUX14.DELAY |
| TXSWING | input | TCELL13:IMUX.IMUX13.DELAY |
| TXUSRCLK | input | TCELL16:IMUX.CLK0 |
| TXUSRCLK2 | input | TCELL16:IMUX.CLK1 |
| USRCODEERR | input | TCELL12:IMUX.IMUX14.DELAY |
Bel GTX2
| Pin | Direction | Wires |
|---|---|---|
| CLKTESTSIG0 | input | TCELL22:IMUX.IMUX19.DELAY |
| CLKTESTSIG1 | input | TCELL22:IMUX.IMUX18.DELAY |
| COMFINISH | output | TCELL28:OUT18.TMIN |
| COMINITDET | output | TCELL22:OUT20.TMIN |
| COMSASDET | output | TCELL22:OUT19.TMIN |
| COMWAKEDET | output | TCELL22:OUT23.TMIN |
| DADDR0 | input | TCELL29:IMUX.IMUX32.DELAY |
| DADDR1 | input | TCELL29:IMUX.IMUX33.DELAY |
| DADDR2 | input | TCELL29:IMUX.IMUX34.DELAY |
| DADDR3 | input | TCELL29:IMUX.IMUX35.DELAY |
| DADDR4 | input | TCELL29:IMUX.IMUX36.DELAY |
| DADDR5 | input | TCELL29:IMUX.IMUX37.DELAY |
| DADDR6 | input | TCELL29:IMUX.IMUX38.DELAY |
| DADDR7 | input | TCELL29:IMUX.IMUX39.DELAY |
| DCLK | input | TCELL29:IMUX.CLK0 |
| DEN | input | TCELL28:IMUX.IMUX16.DELAY |
| DFECLKDLYADJ0 | input | TCELL24:IMUX.IMUX35.DELAY |
| DFECLKDLYADJ1 | input | TCELL24:IMUX.IMUX19.DELAY |
| DFECLKDLYADJ2 | input | TCELL24:IMUX.IMUX18.DELAY |
| DFECLKDLYADJ3 | input | TCELL24:IMUX.IMUX33.DELAY |
| DFECLKDLYADJ4 | input | TCELL24:IMUX.IMUX17.DELAY |
| DFECLKDLYADJ5 | input | TCELL24:IMUX.IMUX16.DELAY |
| DFECLKDLYADJMON0 | output | TCELL26:OUT5.TMIN |
| DFECLKDLYADJMON1 | output | TCELL26:OUT1.TMIN |
| DFECLKDLYADJMON2 | output | TCELL26:OUT2.TMIN |
| DFECLKDLYADJMON3 | output | TCELL26:OUT6.TMIN |
| DFECLKDLYADJMON4 | output | TCELL26:OUT7.TMIN |
| DFECLKDLYADJMON5 | output | TCELL26:OUT3.TMIN |
| DFEDLYOVRD | input | TCELL24:IMUX.IMUX29.DELAY |
| DFEEYEDACMON0 | output | TCELL26:OUT13.TMIN |
| DFEEYEDACMON1 | output | TCELL26:OUT14.TMIN |
| DFEEYEDACMON2 | output | TCELL26:OUT10.TMIN |
| DFEEYEDACMON3 | output | TCELL26:OUT11.TMIN |
| DFEEYEDACMON4 | output | TCELL26:OUT15.TMIN |
| DFESENSCAL0 | output | TCELL26:OUT19.TMIN |
| DFESENSCAL1 | output | TCELL26:OUT18.TMIN |
| DFESENSCAL2 | output | TCELL26:OUT22.TMIN |
| DFETAP10 | input | TCELL24:IMUX.IMUX8.DELAY |
| DFETAP11 | input | TCELL24:IMUX.IMUX10.DELAY |
| DFETAP12 | input | TCELL24:IMUX.IMUX14.DELAY |
| DFETAP13 | input | TCELL24:IMUX.IMUX15.DELAY |
| DFETAP14 | input | TCELL24:IMUX.IMUX38.DELAY |
| DFETAP1MONITOR0 | output | TCELL28:OUT1.TMIN |
| DFETAP1MONITOR1 | output | TCELL28:OUT2.TMIN |
| DFETAP1MONITOR2 | output | TCELL28:OUT6.TMIN |
| DFETAP1MONITOR3 | output | TCELL28:OUT7.TMIN |
| DFETAP1MONITOR4 | output | TCELL28:OUT3.TMIN |
| DFETAP20 | input | TCELL24:IMUX.IMUX24.DELAY |
| DFETAP21 | input | TCELL24:IMUX.IMUX25.DELAY |
| DFETAP22 | input | TCELL24:IMUX.IMUX30.DELAY |
| DFETAP23 | input | TCELL24:IMUX.IMUX31.DELAY |
| DFETAP24 | input | TCELL24:IMUX.IMUX39.DELAY |
| DFETAP2MONITOR0 | output | TCELL27:OUT1.TMIN |
| DFETAP2MONITOR1 | output | TCELL27:OUT2.TMIN |
| DFETAP2MONITOR2 | output | TCELL27:OUT6.TMIN |
| DFETAP2MONITOR3 | output | TCELL27:OUT7.TMIN |
| DFETAP2MONITOR4 | output | TCELL27:OUT3.TMIN |
| DFETAP30 | input | TCELL26:IMUX.IMUX10.DELAY |
| DFETAP31 | input | TCELL26:IMUX.IMUX9.DELAY |
| DFETAP32 | input | TCELL26:IMUX.IMUX12.DELAY |
| DFETAP33 | input | TCELL26:IMUX.IMUX17.DELAY |
| DFETAP3MONITOR0 | output | TCELL28:OUT12.TMIN |
| DFETAP3MONITOR1 | output | TCELL28:OUT8.TMIN |
| DFETAP3MONITOR2 | output | TCELL28:OUT9.TMIN |
| DFETAP3MONITOR3 | output | TCELL28:OUT13.TMIN |
| DFETAP40 | input | TCELL26:IMUX.IMUX26.DELAY |
| DFETAP41 | input | TCELL26:IMUX.IMUX25.DELAY |
| DFETAP42 | input | TCELL26:IMUX.IMUX28.DELAY |
| DFETAP43 | input | TCELL26:IMUX.IMUX20.DELAY |
| DFETAP4MONITOR0 | output | TCELL27:OUT12.TMIN |
| DFETAP4MONITOR1 | output | TCELL27:OUT8.TMIN |
| DFETAP4MONITOR2 | output | TCELL27:OUT9.TMIN |
| DFETAP4MONITOR3 | output | TCELL27:OUT13.TMIN |
| DFETAPOVRD | input | TCELL24:IMUX.IMUX37.DELAY |
| DI0 | input | TCELL29:IMUX.IMUX8.DELAY |
| DI1 | input | TCELL29:IMUX.IMUX9.DELAY |
| DI10 | input | TCELL29:IMUX.IMUX18.DELAY |
| DI11 | input | TCELL29:IMUX.IMUX19.DELAY |
| DI12 | input | TCELL29:IMUX.IMUX20.DELAY |
| DI13 | input | TCELL29:IMUX.IMUX21.DELAY |
| DI14 | input | TCELL29:IMUX.IMUX22.DELAY |
| DI15 | input | TCELL29:IMUX.IMUX23.DELAY |
| DI2 | input | TCELL29:IMUX.IMUX10.DELAY |
| DI3 | input | TCELL29:IMUX.IMUX11.DELAY |
| DI4 | input | TCELL29:IMUX.IMUX12.DELAY |
| DI5 | input | TCELL29:IMUX.IMUX13.DELAY |
| DI6 | input | TCELL29:IMUX.IMUX14.DELAY |
| DI7 | input | TCELL29:IMUX.IMUX15.DELAY |
| DI8 | input | TCELL29:IMUX.IMUX16.DELAY |
| DI9 | input | TCELL29:IMUX.IMUX17.DELAY |
| DRDY | output | TCELL28:OUT0.TMIN |
| DRPDO0 | output | TCELL29:OUT3.TMIN |
| DRPDO1 | output | TCELL29:OUT7.TMIN |
| DRPDO10 | output | TCELL29:OUT10.TMIN |
| DRPDO11 | output | TCELL29:OUT14.TMIN |
| DRPDO12 | output | TCELL29:OUT13.TMIN |
| DRPDO13 | output | TCELL29:OUT9.TMIN |
| DRPDO14 | output | TCELL29:OUT8.TMIN |
| DRPDO15 | output | TCELL29:OUT12.TMIN |
| DRPDO2 | output | TCELL29:OUT6.TMIN |
| DRPDO3 | output | TCELL29:OUT2.TMIN |
| DRPDO4 | output | TCELL29:OUT1.TMIN |
| DRPDO5 | output | TCELL29:OUT5.TMIN |
| DRPDO6 | output | TCELL29:OUT4.TMIN |
| DRPDO7 | output | TCELL29:OUT0.TMIN |
| DRPDO8 | output | TCELL29:OUT15.TMIN |
| DRPDO9 | output | TCELL29:OUT11.TMIN |
| DWE | input | TCELL28:IMUX.IMUX8.DELAY |
| GATERXELECIDLE | input | TCELL26:IMUX.IMUX32.DELAY |
| GREFCLKRX | input | TCELL23:IMUX.CLK0 |
| GREFCLKTX | input | TCELL27:IMUX.CLK0 |
| GTXRXRESET | input | TCELL21:IMUX.CTRL0 |
| GTXTEST0 | input | TCELL22:IMUX.IMUX39.DELAY |
| GTXTEST1 | input | TCELL22:IMUX.IMUX38.DELAY |
| GTXTEST10 | input | TCELL22:IMUX.IMUX29.DELAY |
| GTXTEST11 | input | TCELL22:IMUX.IMUX28.DELAY |
| GTXTEST12 | input | TCELL22:IMUX.IMUX27.DELAY |
| GTXTEST2 | input | TCELL22:IMUX.IMUX37.DELAY |
| GTXTEST3 | input | TCELL22:IMUX.IMUX36.DELAY |
| GTXTEST4 | input | TCELL22:IMUX.IMUX35.DELAY |
| GTXTEST5 | input | TCELL22:IMUX.IMUX34.DELAY |
| GTXTEST6 | input | TCELL22:IMUX.IMUX33.DELAY |
| GTXTEST7 | input | TCELL22:IMUX.IMUX32.DELAY |
| GTXTEST8 | input | TCELL22:IMUX.IMUX31.DELAY |
| GTXTEST9 | input | TCELL22:IMUX.IMUX30.DELAY |
| GTXTXRESET | input | TCELL26:IMUX.CTRL1 |
| IGNORESIGDET | input | TCELL26:IMUX.IMUX37.DELAY |
| LOOPBACK0 | input | TCELL23:IMUX.IMUX24.DELAY |
| LOOPBACK1 | input | TCELL23:IMUX.IMUX11.DELAY |
| LOOPBACK2 | input | TCELL23:IMUX.IMUX27.DELAY |
| MGTREFCLKFAB0 | output | TCELL24:OUT0.TMIN |
| MGTREFCLKFAB1 | output | TCELL24:OUT12.TMIN |
| PHYSTATUS | output | TCELL24:OUT8.TMIN |
| PLLRXRESET | input | TCELL23:IMUX.CTRL0 |
| PLLTXRESET | input | TCELL25:IMUX.CTRL1 |
| PRBSCNTRESET | input | TCELL20:IMUX.CTRL1 |
| RXBUFRESET | input | TCELL22:IMUX.CTRL0 |
| RXBUFSTATUS0 | output | TCELL24:OUT6.TMIN |
| RXBUFSTATUS1 | output | TCELL24:OUT7.TMIN |
| RXBUFSTATUS2 | output | TCELL24:OUT3.TMIN |
| RXBUFWE | input | TCELL21:IMUX.IMUX24.DELAY |
| RXBYTEISALIGNED | output | TCELL22:OUT13.TMIN |
| RXBYTEREALIGN | output | TCELL22:OUT10.TMIN |
| RXCDRRESET | input | TCELL21:IMUX.CTRL1 |
| RXCHANBONDSEQ | output | TCELL25:OUT14.TMIN |
| RXCHANISALIGNED | output | TCELL23:OUT13.TMIN |
| RXCHANREALIGN | output | TCELL22:OUT14.TMIN |
| RXCHARISCOMMA0 | output | TCELL23:OUT14.TMIN |
| RXCHARISCOMMA1 | output | TCELL23:OUT2.TMIN |
| RXCHARISCOMMA2 | output | TCELL22:OUT8.TMIN |
| RXCHARISCOMMA3 | output | TCELL22:OUT18.TMIN |
| RXCHARISK0 | output | TCELL23:OUT16.TMIN |
| RXCHARISK1 | output | TCELL22:OUT5.TMIN |
| RXCHARISK2 | output | TCELL22:OUT15.TMIN |
| RXCHARISK3 | output | TCELL22:OUT3.TMIN |
| RXCHBONDI0 | input | TCELL23:IMUX.IMUX32.DELAY |
| RXCHBONDI1 | input | TCELL23:IMUX.IMUX33.DELAY |
| RXCHBONDI2 | input | TCELL23:IMUX.IMUX34.DELAY |
| RXCHBONDI3 | input | TCELL23:IMUX.IMUX35.DELAY |
| RXCHBONDLEVEL0 | input | TCELL22:IMUX.IMUX10.DELAY |
| RXCHBONDLEVEL1 | input | TCELL22:IMUX.IMUX26.DELAY |
| RXCHBONDLEVEL2 | input | TCELL22:IMUX.IMUX11.DELAY |
| RXCHBONDMASTER | input | TCELL22:IMUX.IMUX24.DELAY |
| RXCHBONDO0 | output | TCELL24:OUT17.TMIN |
| RXCHBONDO1 | output | TCELL24:OUT10.TMIN |
| RXCHBONDO2 | output | TCELL24:OUT11.TMIN |
| RXCHBONDO3 | output | TCELL24:OUT15.TMIN |
| RXCHBONDSLAVE | input | TCELL22:IMUX.IMUX8.DELAY |
| RXCLKCORCNT0 | output | TCELL25:OUT8.TMIN |
| RXCLKCORCNT1 | output | TCELL25:OUT9.TMIN |
| RXCLKCORCNT2 | output | TCELL25:OUT6.TMIN |
| RXCOMMADET | output | TCELL25:OUT12.TMIN |
| RXCOMMADETUSE | input | TCELL23:IMUX.IMUX36.DELAY |
| RXDATA0 | output | TCELL20:OUT4.TMIN |
| RXDATA1 | output | TCELL20:OUT7.TMIN |
| RXDATA10 | output | TCELL21:OUT6.TMIN |
| RXDATA11 | output | TCELL21:OUT2.TMIN |
| RXDATA12 | output | TCELL22:OUT7.TMIN |
| RXDATA13 | output | TCELL22:OUT6.TMIN |
| RXDATA14 | output | TCELL22:OUT2.TMIN |
| RXDATA15 | output | TCELL22:OUT1.TMIN |
| RXDATA16 | output | TCELL20:OUT15.TMIN |
| RXDATA17 | output | TCELL20:OUT3.TMIN |
| RXDATA18 | output | TCELL20:OUT0.TMIN |
| RXDATA19 | output | TCELL20:OUT22.TMIN |
| RXDATA2 | output | TCELL20:OUT6.TMIN |
| RXDATA20 | output | TCELL20:OUT18.TMIN |
| RXDATA21 | output | TCELL20:OUT17.TMIN |
| RXDATA22 | output | TCELL20:OUT16.TMIN |
| RXDATA23 | output | TCELL20:OUT20.TMIN |
| RXDATA24 | output | TCELL21:OUT0.TMIN |
| RXDATA25 | output | TCELL21:OUT22.TMIN |
| RXDATA26 | output | TCELL21:OUT18.TMIN |
| RXDATA27 | output | TCELL21:OUT9.TMIN |
| RXDATA28 | output | TCELL21:OUT16.TMIN |
| RXDATA29 | output | TCELL21:OUT11.TMIN |
| RXDATA3 | output | TCELL20:OUT2.TMIN |
| RXDATA30 | output | TCELL21:OUT15.TMIN |
| RXDATA31 | output | TCELL21:OUT3.TMIN |
| RXDATA4 | output | TCELL20:OUT1.TMIN |
| RXDATA5 | output | TCELL20:OUT5.TMIN |
| RXDATA6 | output | TCELL21:OUT1.TMIN |
| RXDATA7 | output | TCELL21:OUT5.TMIN |
| RXDATA8 | output | TCELL21:OUT4.TMIN |
| RXDATA9 | output | TCELL21:OUT7.TMIN |
| RXDATAVALID | output | TCELL22:OUT4.TMIN |
| RXDEC8B10BUSE | input | TCELL21:IMUX.IMUX39.DELAY |
| RXDISPERR0 | output | TCELL23:OUT4.TMIN |
| RXDISPERR1 | output | TCELL23:OUT8.TMIN |
| RXDISPERR2 | output | TCELL23:OUT0.TMIN |
| RXDISPERR3 | output | TCELL23:OUT22.TMIN |
| RXDLYALIGNDISABLE | input | TCELL25:IMUX.IMUX14.DELAY |
| RXDLYALIGNFORCEROTATEB | input | TCELL23:IMUX.IMUX25.DELAY |
| RXDLYALIGNMONENB | input | TCELL23:IMUX.IMUX28.DELAY |
| RXDLYALIGNMONITOR0 | output | TCELL25:OUT21.TMIN |
| RXDLYALIGNMONITOR1 | output | TCELL25:OUT15.TMIN |
| RXDLYALIGNMONITOR2 | output | TCELL25:OUT7.TMIN |
| RXDLYALIGNMONITOR3 | output | TCELL25:OUT20.TMIN |
| RXDLYALIGNMONITOR4 | output | TCELL25:OUT23.TMIN |
| RXDLYALIGNMONITOR5 | output | TCELL25:OUT19.TMIN |
| RXDLYALIGNMONITOR6 | output | TCELL25:OUT18.TMIN |
| RXDLYALIGNMONITOR7 | output | TCELL25:OUT0.TMIN |
| RXDLYALIGNOVERRIDE | input | TCELL25:IMUX.IMUX33.DELAY |
| RXDLYALIGNRESET | input | TCELL25:IMUX.IMUX29.DELAY |
| RXDLYALIGNSWPPRECURB | input | TCELL23:IMUX.IMUX29.DELAY |
| RXDLYALIGNTESTMODEENB | input | TCELL23:IMUX.IMUX12.DELAY |
| RXDLYALIGNUPDSW | input | TCELL25:IMUX.IMUX10.DELAY |
| RXELECIDLE | output | TCELL25:OUT3.TMIN |
| RXENCHANSYNC | input | TCELL21:IMUX.IMUX38.DELAY |
| RXENMCOMMAALIGN | input | TCELL21:IMUX.IMUX36.DELAY |
| RXENPCOMMAALIGN | input | TCELL21:IMUX.IMUX37.DELAY |
| RXENPMAPHASEALIGN | input | TCELL21:IMUX.IMUX35.DELAY |
| RXENPRBSTST0 | input | TCELL21:IMUX.IMUX33.DELAY |
| RXENPRBSTST1 | input | TCELL21:IMUX.IMUX34.DELAY |
| RXENPRBSTST2 | input | TCELL21:IMUX.IMUX18.DELAY |
| RXENSAMPLEALIGN | input | TCELL21:IMUX.IMUX32.DELAY |
| RXEQMIX0 | input | TCELL21:IMUX.IMUX14.DELAY |
| RXEQMIX1 | input | TCELL21:IMUX.IMUX15.DELAY |
| RXEQMIX2 | input | TCELL21:IMUX.IMUX30.DELAY |
| RXEQMIX3 | input | TCELL21:IMUX.IMUX22.DELAY |
| RXEQMIX4 | input | TCELL21:IMUX.IMUX29.DELAY |
| RXEQMIX5 | input | TCELL21:IMUX.IMUX21.DELAY |
| RXEQMIX6 | input | TCELL21:IMUX.IMUX28.DELAY |
| RXEQMIX7 | input | TCELL21:IMUX.IMUX20.DELAY |
| RXEQMIX8 | input | TCELL21:IMUX.IMUX27.DELAY |
| RXEQMIX9 | input | TCELL21:IMUX.IMUX19.DELAY |
| RXGEARBOXSLIP | input | TCELL21:IMUX.IMUX12.DELAY |
| RXHEADER0 | output | TCELL25:OUT10.TMIN |
| RXHEADER1 | output | TCELL25:OUT16.TMIN |
| RXHEADER2 | output | TCELL25:OUT17.TMIN |
| RXHEADERVALID | output | TCELL25:OUT11.TMIN |
| RXLOSSOFSYNC0 | output | TCELL22:OUT0.TMIN |
| RXLOSSOFSYNC1 | output | TCELL22:OUT22.TMIN |
| RXNOTINTABLE0 | output | TCELL23:OUT11.TMIN |
| RXNOTINTABLE1 | output | TCELL23:OUT7.TMIN |
| RXNOTINTABLE2 | output | TCELL23:OUT15.TMIN |
| RXNOTINTABLE3 | output | TCELL23:OUT3.TMIN |
| RXOVERSAMPLEERR | output | TCELL24:OUT22.TMIN |
| RXPLLLKDET | output | TCELL24:OUT5.TMIN |
| RXPLLLKDETEN | input | TCELL22:IMUX.IMUX20.DELAY |
| RXPLLPOWERDOWN | input | TCELL22:IMUX.IMUX21.DELAY |
| RXPLLREFSELDY0 | input | TCELL23:IMUX.IMUX37.DELAY |
| RXPLLREFSELDY1 | input | TCELL23:IMUX.IMUX22.DELAY |
| RXPLLREFSELDY2 | input | TCELL23:IMUX.IMUX39.DELAY |
| RXPMASETPHASE | input | TCELL21:IMUX.IMUX11.DELAY |
| RXPOLARITY | input | TCELL21:IMUX.IMUX26.DELAY |
| RXPOWERDOWN0 | input | TCELL24:IMUX.IMUX13.DELAY |
| RXPOWERDOWN1 | input | TCELL24:IMUX.IMUX21.DELAY |
| RXPRBSERR | output | TCELL25:OUT2.TMIN |
| RXRATE0 | input | TCELL26:IMUX.IMUX42.DELAY |
| RXRATE1 | input | TCELL26:IMUX.IMUX41.DELAY |
| RXRATEDONE | output | TCELL26:OUT20.TMIN |
| RXRECCLKPCS | output | TCELL25:OUT5.TMIN |
| RXRESET | input | TCELL22:IMUX.CTRL1 |
| RXRESETDONE | output | TCELL25:OUT22.TMIN |
| RXRUNDISP0 | output | TCELL23:OUT9.TMIN |
| RXRUNDISP1 | output | TCELL23:OUT5.TMIN |
| RXRUNDISP2 | output | TCELL23:OUT19.TMIN |
| RXRUNDISP3 | output | TCELL23:OUT1.TMIN |
| RXSLIDE | input | TCELL21:IMUX.IMUX9.DELAY |
| RXSTARTOFSEQ | output | TCELL25:OUT1.TMIN |
| RXSTATUS0 | output | TCELL24:OUT14.TMIN |
| RXSTATUS1 | output | TCELL24:OUT16.TMIN |
| RXSTATUS2 | output | TCELL24:OUT13.TMIN |
| RXUSRCLK | input | TCELL22:IMUX.CLK0 |
| RXUSRCLK2 | input | TCELL22:IMUX.CLK1 |
| RXVALID | output | TCELL25:OUT4.TMIN |
| SCANCLK | input | TCELL24:IMUX.CLK1 |
| SCANENB | input | TCELL20:IMUX.IMUX37.DELAY |
| SCANIN0 | input | TCELL28:IMUX.IMUX33.DELAY |
| SCANIN1 | input | TCELL28:IMUX.IMUX25.DELAY |
| SCANIN2 | input | TCELL20:IMUX.IMUX38.DELAY |
| SCANIN3 | input | TCELL20:IMUX.IMUX22.DELAY |
| SCANIN4 | input | TCELL28:IMUX.IMUX9.DELAY |
| SCANMODEB | input | TCELL20:IMUX.IMUX29.DELAY |
| SCANOUT0 | output | TCELL24:OUT18.TMIN |
| SCANOUT1 | output | TCELL24:OUT4.TMIN |
| SCANOUT2 | output | TCELL20:OUT23.TMIN |
| SCANOUT3 | output | TCELL20:OUT13.TMIN |
| SCANOUT4 | output | TCELL20:OUT8.TMIN |
| TSTCLK0 | input | TCELL23:IMUX.CLK1 |
| TSTCLK1 | input | TCELL25:IMUX.CLK1 |
| TSTIN0 | input | TCELL20:IMUX.IMUX30.DELAY |
| TSTIN1 | input | TCELL20:IMUX.IMUX14.DELAY |
| TSTIN10 | input | TCELL20:IMUX.IMUX31.DELAY |
| TSTIN11 | input | TCELL20:IMUX.IMUX21.DELAY |
| TSTIN12 | input | TCELL20:IMUX.IMUX13.DELAY |
| TSTIN13 | input | TCELL20:IMUX.IMUX28.DELAY |
| TSTIN14 | input | TCELL20:IMUX.IMUX32.DELAY |
| TSTIN15 | input | TCELL20:IMUX.IMUX16.DELAY |
| TSTIN16 | input | TCELL20:IMUX.IMUX40.DELAY |
| TSTIN17 | input | TCELL20:IMUX.IMUX0.DELAY |
| TSTIN18 | input | TCELL20:IMUX.IMUX1.DELAY |
| TSTIN19 | input | TCELL20:IMUX.IMUX41.DELAY |
| TSTIN2 | input | TCELL20:IMUX.IMUX27.DELAY |
| TSTIN3 | input | TCELL20:IMUX.IMUX11.DELAY |
| TSTIN4 | input | TCELL20:IMUX.IMUX26.DELAY |
| TSTIN5 | input | TCELL20:IMUX.IMUX10.DELAY |
| TSTIN6 | input | TCELL20:IMUX.IMUX25.DELAY |
| TSTIN7 | input | TCELL20:IMUX.IMUX9.DELAY |
| TSTIN8 | input | TCELL20:IMUX.IMUX24.DELAY |
| TSTIN9 | input | TCELL20:IMUX.IMUX8.DELAY |
| TSTOUT0 | output | TCELL21:OUT21.TMIN |
| TSTOUT1 | output | TCELL21:OUT17.TMIN |
| TSTOUT2 | output | TCELL21:OUT10.TMIN |
| TSTOUT3 | output | TCELL21:OUT20.TMIN |
| TSTOUT4 | output | TCELL21:OUT14.TMIN |
| TSTOUT5 | output | TCELL21:OUT23.TMIN |
| TSTOUT6 | output | TCELL21:OUT13.TMIN |
| TSTOUT7 | output | TCELL21:OUT19.TMIN |
| TSTOUT8 | output | TCELL21:OUT8.TMIN |
| TSTOUT9 | output | TCELL21:OUT12.TMIN |
| TSTPWRDN0 | input | TCELL20:IMUX.IMUX33.DELAY |
| TSTPWRDN1 | input | TCELL20:IMUX.IMUX18.DELAY |
| TSTPWRDN2 | input | TCELL20:IMUX.IMUX34.DELAY |
| TSTPWRDN3 | input | TCELL20:IMUX.IMUX19.DELAY |
| TSTPWRDN4 | input | TCELL20:IMUX.IMUX35.DELAY |
| TSTPWRDNOVRD | input | TCELL20:IMUX.IMUX17.DELAY |
| TXBUFDIFFCTRL0 | input | TCELL23:IMUX.IMUX0.DELAY |
| TXBUFDIFFCTRL1 | input | TCELL23:IMUX.IMUX16.DELAY |
| TXBUFDIFFCTRL2 | input | TCELL23:IMUX.IMUX18.DELAY |
| TXBUFSTATUS0 | output | TCELL27:OUT5.TMIN |
| TXBUFSTATUS1 | output | TCELL27:OUT17.TMIN |
| TXBYPASS8B10B0 | input | TCELL25:IMUX.IMUX11.DELAY |
| TXBYPASS8B10B1 | input | TCELL25:IMUX.IMUX27.DELAY |
| TXBYPASS8B10B2 | input | TCELL25:IMUX.IMUX35.DELAY |
| TXBYPASS8B10B3 | input | TCELL25:IMUX.IMUX19.DELAY |
| TXCHARDISPMODE0 | input | TCELL25:IMUX.IMUX34.DELAY |
| TXCHARDISPMODE1 | input | TCELL25:IMUX.IMUX28.DELAY |
| TXCHARDISPMODE2 | input | TCELL25:IMUX.IMUX37.DELAY |
| TXCHARDISPMODE3 | input | TCELL25:IMUX.IMUX21.DELAY |
| TXCHARDISPVAL0 | input | TCELL25:IMUX.IMUX44.DELAY |
| TXCHARDISPVAL1 | input | TCELL25:IMUX.IMUX30.DELAY |
| TXCHARDISPVAL2 | input | TCELL25:IMUX.IMUX38.DELAY |
| TXCHARDISPVAL3 | input | TCELL25:IMUX.IMUX22.DELAY |
| TXCHARISK0 | input | TCELL25:IMUX.IMUX26.DELAY |
| TXCHARISK1 | input | TCELL25:IMUX.IMUX36.DELAY |
| TXCHARISK2 | input | TCELL25:IMUX.IMUX39.DELAY |
| TXCHARISK3 | input | TCELL25:IMUX.IMUX23.DELAY |
| TXCOMINIT | input | TCELL27:IMUX.IMUX18.DELAY |
| TXCOMSAS | input | TCELL27:IMUX.IMUX19.DELAY |
| TXCOMWAKE | input | TCELL27:IMUX.IMUX10.DELAY |
| TXDATA0 | input | TCELL28:IMUX.IMUX38.DELAY |
| TXDATA1 | input | TCELL28:IMUX.IMUX36.DELAY |
| TXDATA10 | input | TCELL27:IMUX.IMUX13.DELAY |
| TXDATA11 | input | TCELL27:IMUX.IMUX40.DELAY |
| TXDATA12 | input | TCELL26:IMUX.IMUX3.DELAY |
| TXDATA13 | input | TCELL26:IMUX.IMUX30.DELAY |
| TXDATA14 | input | TCELL26:IMUX.IMUX5.DELAY |
| TXDATA15 | input | TCELL26:IMUX.IMUX13.DELAY |
| TXDATA16 | input | TCELL28:IMUX.IMUX31.DELAY |
| TXDATA17 | input | TCELL28:IMUX.IMUX30.DELAY |
| TXDATA18 | input | TCELL28:IMUX.IMUX29.DELAY |
| TXDATA19 | input | TCELL28:IMUX.IMUX27.DELAY |
| TXDATA2 | input | TCELL28:IMUX.IMUX28.DELAY |
| TXDATA20 | input | TCELL27:IMUX.IMUX27.DELAY |
| TXDATA21 | input | TCELL27:IMUX.IMUX28.DELAY |
| TXDATA22 | input | TCELL27:IMUX.IMUX25.DELAY |
| TXDATA23 | input | TCELL27:IMUX.IMUX24.DELAY |
| TXDATA24 | input | TCELL28:IMUX.IMUX39.DELAY |
| TXDATA25 | input | TCELL28:IMUX.IMUX19.DELAY |
| TXDATA26 | input | TCELL28:IMUX.IMUX37.DELAY |
| TXDATA27 | input | TCELL28:IMUX.IMUX35.DELAY |
| TXDATA28 | input | TCELL27:IMUX.IMUX35.DELAY |
| TXDATA29 | input | TCELL27:IMUX.IMUX36.DELAY |
| TXDATA3 | input | TCELL28:IMUX.IMUX32.DELAY |
| TXDATA30 | input | TCELL27:IMUX.IMUX33.DELAY |
| TXDATA31 | input | TCELL27:IMUX.IMUX32.DELAY |
| TXDATA4 | input | TCELL28:IMUX.IMUX26.DELAY |
| TXDATA5 | input | TCELL28:IMUX.IMUX34.DELAY |
| TXDATA6 | input | TCELL27:IMUX.IMUX34.DELAY |
| TXDATA7 | input | TCELL27:IMUX.IMUX26.DELAY |
| TXDATA8 | input | TCELL27:IMUX.IMUX15.DELAY |
| TXDATA9 | input | TCELL27:IMUX.IMUX21.DELAY |
| TXDEEMPH | input | TCELL23:IMUX.IMUX3.DELAY |
| TXDETECTRX | input | TCELL24:IMUX.IMUX9.DELAY |
| TXDIFFCTRL0 | input | TCELL23:IMUX.IMUX21.DELAY |
| TXDIFFCTRL1 | input | TCELL23:IMUX.IMUX38.DELAY |
| TXDIFFCTRL2 | input | TCELL23:IMUX.IMUX5.DELAY |
| TXDIFFCTRL3 | input | TCELL23:IMUX.IMUX30.DELAY |
| TXDLYALIGNDISABLE | input | TCELL25:IMUX.IMUX46.DELAY |
| TXDLYALIGNFORCEROTATEB | input | TCELL27:IMUX.IMUX9.DELAY |
| TXDLYALIGNMONENB | input | TCELL27:IMUX.IMUX11.DELAY |
| TXDLYALIGNMONITOR0 | output | TCELL27:OUT21.TMIN |
| TXDLYALIGNMONITOR1 | output | TCELL27:OUT16.TMIN |
| TXDLYALIGNMONITOR2 | output | TCELL27:OUT4.TMIN |
| TXDLYALIGNMONITOR3 | output | TCELL27:OUT20.TMIN |
| TXDLYALIGNMONITOR4 | output | TCELL27:OUT23.TMIN |
| TXDLYALIGNMONITOR5 | output | TCELL27:OUT19.TMIN |
| TXDLYALIGNMONITOR6 | output | TCELL27:OUT18.TMIN |
| TXDLYALIGNMONITOR7 | output | TCELL27:OUT0.TMIN |
| TXDLYALIGNOVERRIDE | input | TCELL25:IMUX.IMUX25.DELAY |
| TXDLYALIGNRESET | input | TCELL25:IMUX.IMUX13.DELAY |
| TXDLYALIGNTESTMODEENB | input | TCELL27:IMUX.IMUX30.DELAY |
| TXDLYALIGNUPDSW | input | TCELL25:IMUX.IMUX2.DELAY |
| TXELECIDLE | input | TCELL24:IMUX.IMUX32.DELAY |
| TXENC8B10BUSE | input | TCELL27:IMUX.IMUX22.DELAY |
| TXENPMAPHASEALIGN | input | TCELL28:IMUX.IMUX17.DELAY |
| TXENPRBSTST0 | input | TCELL26:IMUX.IMUX39.DELAY |
| TXENPRBSTST1 | input | TCELL26:IMUX.IMUX23.DELAY |
| TXENPRBSTST2 | input | TCELL26:IMUX.IMUX15.DELAY |
| TXGEARBOXREADY | output | TCELL26:OUT4.TMIN |
| TXHEADER0 | input | TCELL25:IMUX.IMUX8.DELAY |
| TXHEADER1 | input | TCELL25:IMUX.IMUX16.DELAY |
| TXHEADER2 | input | TCELL25:IMUX.IMUX32.DELAY |
| TXINHIBIT | input | TCELL25:IMUX.IMUX17.DELAY |
| TXKERR0 | output | TCELL27:OUT14.TMIN |
| TXKERR1 | output | TCELL27:OUT10.TMIN |
| TXKERR2 | output | TCELL27:OUT11.TMIN |
| TXKERR3 | output | TCELL27:OUT15.TMIN |
| TXMARGIN0 | input | TCELL24:IMUX.IMUX11.DELAY |
| TXMARGIN1 | input | TCELL24:IMUX.IMUX26.DELAY |
| TXMARGIN2 | input | TCELL25:IMUX.IMUX15.DELAY |
| TXOUTCLKPCS | output | TCELL26:OUT8.TMIN |
| TXPDOWNASYNCH | input | TCELL28:IMUX.IMUX15.DELAY |
| TXPLLLKDET | output | TCELL28:OUT5.TMIN |
| TXPLLLKDETEN | input | TCELL27:IMUX.IMUX12.DELAY |
| TXPLLPOWERDOWN | input | TCELL27:IMUX.IMUX29.DELAY |
| TXPLLREFSELDY0 | input | TCELL27:IMUX.IMUX37.DELAY |
| TXPLLREFSELDY1 | input | TCELL27:IMUX.IMUX38.DELAY |
| TXPLLREFSELDY2 | input | TCELL27:IMUX.IMUX39.DELAY |
| TXPMASETPHASE | input | TCELL25:IMUX.IMUX18.DELAY |
| TXPOLARITY | input | TCELL25:IMUX.IMUX9.DELAY |
| TXPOSTEMPHASIS0 | input | TCELL28:IMUX.IMUX10.DELAY |
| TXPOSTEMPHASIS1 | input | TCELL28:IMUX.IMUX18.DELAY |
| TXPOSTEMPHASIS2 | input | TCELL28:IMUX.IMUX12.DELAY |
| TXPOSTEMPHASIS3 | input | TCELL28:IMUX.IMUX20.DELAY |
| TXPOSTEMPHASIS4 | input | TCELL28:IMUX.IMUX22.DELAY |
| TXPOWERDOWN0 | input | TCELL24:IMUX.IMUX28.DELAY |
| TXPOWERDOWN1 | input | TCELL24:IMUX.IMUX36.DELAY |
| TXPRBSFORCEERR | input | TCELL28:IMUX.IMUX13.DELAY |
| TXPREEMPHASIS0 | input | TCELL23:IMUX.IMUX26.DELAY |
| TXPREEMPHASIS1 | input | TCELL23:IMUX.IMUX19.DELAY |
| TXPREEMPHASIS2 | input | TCELL23:IMUX.IMUX17.DELAY |
| TXPREEMPHASIS3 | input | TCELL23:IMUX.IMUX9.DELAY |
| TXRATE0 | input | TCELL26:IMUX.IMUX34.DELAY |
| TXRATE1 | input | TCELL26:IMUX.IMUX33.DELAY |
| TXRATEDONE | output | TCELL26:OUT23.TMIN |
| TXRESET | input | TCELL26:IMUX.CTRL0 |
| TXRESETDONE | output | TCELL27:OUT22.TMIN |
| TXRUNDISP0 | output | TCELL28:OUT14.TMIN |
| TXRUNDISP1 | output | TCELL28:OUT10.TMIN |
| TXRUNDISP2 | output | TCELL28:OUT11.TMIN |
| TXRUNDISP3 | output | TCELL28:OUT15.TMIN |
| TXSEQUENCE0 | input | TCELL26:IMUX.IMUX11.DELAY |
| TXSEQUENCE1 | input | TCELL26:IMUX.IMUX19.DELAY |
| TXSEQUENCE2 | input | TCELL26:IMUX.IMUX35.DELAY |
| TXSEQUENCE3 | input | TCELL26:IMUX.IMUX8.DELAY |
| TXSEQUENCE4 | input | TCELL26:IMUX.IMUX24.DELAY |
| TXSEQUENCE5 | input | TCELL26:IMUX.IMUX22.DELAY |
| TXSEQUENCE6 | input | TCELL26:IMUX.IMUX38.DELAY |
| TXSTARTSEQ | input | TCELL27:IMUX.IMUX14.DELAY |
| TXSWING | input | TCELL23:IMUX.IMUX13.DELAY |
| TXUSRCLK | input | TCELL26:IMUX.CLK0 |
| TXUSRCLK2 | input | TCELL26:IMUX.CLK1 |
| USRCODEERR | input | TCELL22:IMUX.IMUX14.DELAY |
Bel GTX3
| Pin | Direction | Wires |
|---|---|---|
| CLKTESTSIG0 | input | TCELL32:IMUX.IMUX19.DELAY |
| CLKTESTSIG1 | input | TCELL32:IMUX.IMUX18.DELAY |
| COMFINISH | output | TCELL38:OUT18.TMIN |
| COMINITDET | output | TCELL32:OUT20.TMIN |
| COMSASDET | output | TCELL32:OUT19.TMIN |
| COMWAKEDET | output | TCELL32:OUT23.TMIN |
| DADDR0 | input | TCELL39:IMUX.IMUX32.DELAY |
| DADDR1 | input | TCELL39:IMUX.IMUX33.DELAY |
| DADDR2 | input | TCELL39:IMUX.IMUX34.DELAY |
| DADDR3 | input | TCELL39:IMUX.IMUX35.DELAY |
| DADDR4 | input | TCELL39:IMUX.IMUX36.DELAY |
| DADDR5 | input | TCELL39:IMUX.IMUX37.DELAY |
| DADDR6 | input | TCELL39:IMUX.IMUX38.DELAY |
| DADDR7 | input | TCELL39:IMUX.IMUX39.DELAY |
| DCLK | input | TCELL39:IMUX.CLK0 |
| DEN | input | TCELL38:IMUX.IMUX16.DELAY |
| DFECLKDLYADJ0 | input | TCELL34:IMUX.IMUX35.DELAY |
| DFECLKDLYADJ1 | input | TCELL34:IMUX.IMUX19.DELAY |
| DFECLKDLYADJ2 | input | TCELL34:IMUX.IMUX18.DELAY |
| DFECLKDLYADJ3 | input | TCELL34:IMUX.IMUX33.DELAY |
| DFECLKDLYADJ4 | input | TCELL34:IMUX.IMUX17.DELAY |
| DFECLKDLYADJ5 | input | TCELL34:IMUX.IMUX16.DELAY |
| DFECLKDLYADJMON0 | output | TCELL36:OUT5.TMIN |
| DFECLKDLYADJMON1 | output | TCELL36:OUT1.TMIN |
| DFECLKDLYADJMON2 | output | TCELL36:OUT2.TMIN |
| DFECLKDLYADJMON3 | output | TCELL36:OUT6.TMIN |
| DFECLKDLYADJMON4 | output | TCELL36:OUT7.TMIN |
| DFECLKDLYADJMON5 | output | TCELL36:OUT3.TMIN |
| DFEDLYOVRD | input | TCELL34:IMUX.IMUX29.DELAY |
| DFEEYEDACMON0 | output | TCELL36:OUT13.TMIN |
| DFEEYEDACMON1 | output | TCELL36:OUT14.TMIN |
| DFEEYEDACMON2 | output | TCELL36:OUT10.TMIN |
| DFEEYEDACMON3 | output | TCELL36:OUT11.TMIN |
| DFEEYEDACMON4 | output | TCELL36:OUT15.TMIN |
| DFESENSCAL0 | output | TCELL36:OUT19.TMIN |
| DFESENSCAL1 | output | TCELL36:OUT18.TMIN |
| DFESENSCAL2 | output | TCELL36:OUT22.TMIN |
| DFETAP10 | input | TCELL34:IMUX.IMUX8.DELAY |
| DFETAP11 | input | TCELL34:IMUX.IMUX10.DELAY |
| DFETAP12 | input | TCELL34:IMUX.IMUX14.DELAY |
| DFETAP13 | input | TCELL34:IMUX.IMUX15.DELAY |
| DFETAP14 | input | TCELL34:IMUX.IMUX38.DELAY |
| DFETAP1MONITOR0 | output | TCELL38:OUT1.TMIN |
| DFETAP1MONITOR1 | output | TCELL38:OUT2.TMIN |
| DFETAP1MONITOR2 | output | TCELL38:OUT6.TMIN |
| DFETAP1MONITOR3 | output | TCELL38:OUT7.TMIN |
| DFETAP1MONITOR4 | output | TCELL38:OUT3.TMIN |
| DFETAP20 | input | TCELL34:IMUX.IMUX24.DELAY |
| DFETAP21 | input | TCELL34:IMUX.IMUX25.DELAY |
| DFETAP22 | input | TCELL34:IMUX.IMUX30.DELAY |
| DFETAP23 | input | TCELL34:IMUX.IMUX31.DELAY |
| DFETAP24 | input | TCELL34:IMUX.IMUX39.DELAY |
| DFETAP2MONITOR0 | output | TCELL37:OUT1.TMIN |
| DFETAP2MONITOR1 | output | TCELL37:OUT2.TMIN |
| DFETAP2MONITOR2 | output | TCELL37:OUT6.TMIN |
| DFETAP2MONITOR3 | output | TCELL37:OUT7.TMIN |
| DFETAP2MONITOR4 | output | TCELL37:OUT3.TMIN |
| DFETAP30 | input | TCELL36:IMUX.IMUX10.DELAY |
| DFETAP31 | input | TCELL36:IMUX.IMUX9.DELAY |
| DFETAP32 | input | TCELL36:IMUX.IMUX12.DELAY |
| DFETAP33 | input | TCELL36:IMUX.IMUX17.DELAY |
| DFETAP3MONITOR0 | output | TCELL38:OUT12.TMIN |
| DFETAP3MONITOR1 | output | TCELL38:OUT8.TMIN |
| DFETAP3MONITOR2 | output | TCELL38:OUT9.TMIN |
| DFETAP3MONITOR3 | output | TCELL38:OUT13.TMIN |
| DFETAP40 | input | TCELL36:IMUX.IMUX26.DELAY |
| DFETAP41 | input | TCELL36:IMUX.IMUX25.DELAY |
| DFETAP42 | input | TCELL36:IMUX.IMUX28.DELAY |
| DFETAP43 | input | TCELL36:IMUX.IMUX20.DELAY |
| DFETAP4MONITOR0 | output | TCELL37:OUT12.TMIN |
| DFETAP4MONITOR1 | output | TCELL37:OUT8.TMIN |
| DFETAP4MONITOR2 | output | TCELL37:OUT9.TMIN |
| DFETAP4MONITOR3 | output | TCELL37:OUT13.TMIN |
| DFETAPOVRD | input | TCELL34:IMUX.IMUX37.DELAY |
| DI0 | input | TCELL39:IMUX.IMUX8.DELAY |
| DI1 | input | TCELL39:IMUX.IMUX9.DELAY |
| DI10 | input | TCELL39:IMUX.IMUX18.DELAY |
| DI11 | input | TCELL39:IMUX.IMUX19.DELAY |
| DI12 | input | TCELL39:IMUX.IMUX20.DELAY |
| DI13 | input | TCELL39:IMUX.IMUX21.DELAY |
| DI14 | input | TCELL39:IMUX.IMUX22.DELAY |
| DI15 | input | TCELL39:IMUX.IMUX23.DELAY |
| DI2 | input | TCELL39:IMUX.IMUX10.DELAY |
| DI3 | input | TCELL39:IMUX.IMUX11.DELAY |
| DI4 | input | TCELL39:IMUX.IMUX12.DELAY |
| DI5 | input | TCELL39:IMUX.IMUX13.DELAY |
| DI6 | input | TCELL39:IMUX.IMUX14.DELAY |
| DI7 | input | TCELL39:IMUX.IMUX15.DELAY |
| DI8 | input | TCELL39:IMUX.IMUX16.DELAY |
| DI9 | input | TCELL39:IMUX.IMUX17.DELAY |
| DRDY | output | TCELL38:OUT0.TMIN |
| DRPDO0 | output | TCELL39:OUT3.TMIN |
| DRPDO1 | output | TCELL39:OUT7.TMIN |
| DRPDO10 | output | TCELL39:OUT10.TMIN |
| DRPDO11 | output | TCELL39:OUT14.TMIN |
| DRPDO12 | output | TCELL39:OUT13.TMIN |
| DRPDO13 | output | TCELL39:OUT9.TMIN |
| DRPDO14 | output | TCELL39:OUT8.TMIN |
| DRPDO15 | output | TCELL39:OUT12.TMIN |
| DRPDO2 | output | TCELL39:OUT6.TMIN |
| DRPDO3 | output | TCELL39:OUT2.TMIN |
| DRPDO4 | output | TCELL39:OUT1.TMIN |
| DRPDO5 | output | TCELL39:OUT5.TMIN |
| DRPDO6 | output | TCELL39:OUT4.TMIN |
| DRPDO7 | output | TCELL39:OUT0.TMIN |
| DRPDO8 | output | TCELL39:OUT15.TMIN |
| DRPDO9 | output | TCELL39:OUT11.TMIN |
| DWE | input | TCELL38:IMUX.IMUX8.DELAY |
| GATERXELECIDLE | input | TCELL36:IMUX.IMUX32.DELAY |
| GREFCLKRX | input | TCELL33:IMUX.CLK0 |
| GREFCLKTX | input | TCELL37:IMUX.CLK0 |
| GTXRXRESET | input | TCELL31:IMUX.CTRL0 |
| GTXTEST0 | input | TCELL32:IMUX.IMUX39.DELAY |
| GTXTEST1 | input | TCELL32:IMUX.IMUX38.DELAY |
| GTXTEST10 | input | TCELL32:IMUX.IMUX29.DELAY |
| GTXTEST11 | input | TCELL32:IMUX.IMUX28.DELAY |
| GTXTEST12 | input | TCELL32:IMUX.IMUX27.DELAY |
| GTXTEST2 | input | TCELL32:IMUX.IMUX37.DELAY |
| GTXTEST3 | input | TCELL32:IMUX.IMUX36.DELAY |
| GTXTEST4 | input | TCELL32:IMUX.IMUX35.DELAY |
| GTXTEST5 | input | TCELL32:IMUX.IMUX34.DELAY |
| GTXTEST6 | input | TCELL32:IMUX.IMUX33.DELAY |
| GTXTEST7 | input | TCELL32:IMUX.IMUX32.DELAY |
| GTXTEST8 | input | TCELL32:IMUX.IMUX31.DELAY |
| GTXTEST9 | input | TCELL32:IMUX.IMUX30.DELAY |
| GTXTXRESET | input | TCELL36:IMUX.CTRL1 |
| IGNORESIGDET | input | TCELL36:IMUX.IMUX37.DELAY |
| LOOPBACK0 | input | TCELL33:IMUX.IMUX24.DELAY |
| LOOPBACK1 | input | TCELL33:IMUX.IMUX11.DELAY |
| LOOPBACK2 | input | TCELL33:IMUX.IMUX27.DELAY |
| MGTREFCLKFAB0 | output | TCELL34:OUT0.TMIN |
| MGTREFCLKFAB1 | output | TCELL34:OUT12.TMIN |
| PHYSTATUS | output | TCELL34:OUT8.TMIN |
| PLLRXRESET | input | TCELL33:IMUX.CTRL0 |
| PLLTXRESET | input | TCELL35:IMUX.CTRL1 |
| PRBSCNTRESET | input | TCELL30:IMUX.CTRL1 |
| RXBUFRESET | input | TCELL32:IMUX.CTRL0 |
| RXBUFSTATUS0 | output | TCELL34:OUT6.TMIN |
| RXBUFSTATUS1 | output | TCELL34:OUT7.TMIN |
| RXBUFSTATUS2 | output | TCELL34:OUT3.TMIN |
| RXBUFWE | input | TCELL31:IMUX.IMUX24.DELAY |
| RXBYTEISALIGNED | output | TCELL32:OUT13.TMIN |
| RXBYTEREALIGN | output | TCELL32:OUT10.TMIN |
| RXCDRRESET | input | TCELL31:IMUX.CTRL1 |
| RXCHANBONDSEQ | output | TCELL35:OUT14.TMIN |
| RXCHANISALIGNED | output | TCELL33:OUT13.TMIN |
| RXCHANREALIGN | output | TCELL32:OUT14.TMIN |
| RXCHARISCOMMA0 | output | TCELL33:OUT14.TMIN |
| RXCHARISCOMMA1 | output | TCELL33:OUT2.TMIN |
| RXCHARISCOMMA2 | output | TCELL32:OUT8.TMIN |
| RXCHARISCOMMA3 | output | TCELL32:OUT18.TMIN |
| RXCHARISK0 | output | TCELL33:OUT16.TMIN |
| RXCHARISK1 | output | TCELL32:OUT5.TMIN |
| RXCHARISK2 | output | TCELL32:OUT15.TMIN |
| RXCHARISK3 | output | TCELL32:OUT3.TMIN |
| RXCHBONDI0 | input | TCELL33:IMUX.IMUX32.DELAY |
| RXCHBONDI1 | input | TCELL33:IMUX.IMUX33.DELAY |
| RXCHBONDI2 | input | TCELL33:IMUX.IMUX34.DELAY |
| RXCHBONDI3 | input | TCELL33:IMUX.IMUX35.DELAY |
| RXCHBONDLEVEL0 | input | TCELL32:IMUX.IMUX10.DELAY |
| RXCHBONDLEVEL1 | input | TCELL32:IMUX.IMUX26.DELAY |
| RXCHBONDLEVEL2 | input | TCELL32:IMUX.IMUX11.DELAY |
| RXCHBONDMASTER | input | TCELL32:IMUX.IMUX24.DELAY |
| RXCHBONDO0 | output | TCELL34:OUT17.TMIN |
| RXCHBONDO1 | output | TCELL34:OUT10.TMIN |
| RXCHBONDO2 | output | TCELL34:OUT11.TMIN |
| RXCHBONDO3 | output | TCELL34:OUT15.TMIN |
| RXCHBONDSLAVE | input | TCELL32:IMUX.IMUX8.DELAY |
| RXCLKCORCNT0 | output | TCELL35:OUT8.TMIN |
| RXCLKCORCNT1 | output | TCELL35:OUT9.TMIN |
| RXCLKCORCNT2 | output | TCELL35:OUT6.TMIN |
| RXCOMMADET | output | TCELL35:OUT12.TMIN |
| RXCOMMADETUSE | input | TCELL33:IMUX.IMUX36.DELAY |
| RXDATA0 | output | TCELL30:OUT4.TMIN |
| RXDATA1 | output | TCELL30:OUT7.TMIN |
| RXDATA10 | output | TCELL31:OUT6.TMIN |
| RXDATA11 | output | TCELL31:OUT2.TMIN |
| RXDATA12 | output | TCELL32:OUT7.TMIN |
| RXDATA13 | output | TCELL32:OUT6.TMIN |
| RXDATA14 | output | TCELL32:OUT2.TMIN |
| RXDATA15 | output | TCELL32:OUT1.TMIN |
| RXDATA16 | output | TCELL30:OUT15.TMIN |
| RXDATA17 | output | TCELL30:OUT3.TMIN |
| RXDATA18 | output | TCELL30:OUT0.TMIN |
| RXDATA19 | output | TCELL30:OUT22.TMIN |
| RXDATA2 | output | TCELL30:OUT6.TMIN |
| RXDATA20 | output | TCELL30:OUT18.TMIN |
| RXDATA21 | output | TCELL30:OUT17.TMIN |
| RXDATA22 | output | TCELL30:OUT16.TMIN |
| RXDATA23 | output | TCELL30:OUT20.TMIN |
| RXDATA24 | output | TCELL31:OUT0.TMIN |
| RXDATA25 | output | TCELL31:OUT22.TMIN |
| RXDATA26 | output | TCELL31:OUT18.TMIN |
| RXDATA27 | output | TCELL31:OUT9.TMIN |
| RXDATA28 | output | TCELL31:OUT16.TMIN |
| RXDATA29 | output | TCELL31:OUT11.TMIN |
| RXDATA3 | output | TCELL30:OUT2.TMIN |
| RXDATA30 | output | TCELL31:OUT15.TMIN |
| RXDATA31 | output | TCELL31:OUT3.TMIN |
| RXDATA4 | output | TCELL30:OUT1.TMIN |
| RXDATA5 | output | TCELL30:OUT5.TMIN |
| RXDATA6 | output | TCELL31:OUT1.TMIN |
| RXDATA7 | output | TCELL31:OUT5.TMIN |
| RXDATA8 | output | TCELL31:OUT4.TMIN |
| RXDATA9 | output | TCELL31:OUT7.TMIN |
| RXDATAVALID | output | TCELL32:OUT4.TMIN |
| RXDEC8B10BUSE | input | TCELL31:IMUX.IMUX39.DELAY |
| RXDISPERR0 | output | TCELL33:OUT4.TMIN |
| RXDISPERR1 | output | TCELL33:OUT8.TMIN |
| RXDISPERR2 | output | TCELL33:OUT0.TMIN |
| RXDISPERR3 | output | TCELL33:OUT22.TMIN |
| RXDLYALIGNDISABLE | input | TCELL35:IMUX.IMUX14.DELAY |
| RXDLYALIGNFORCEROTATEB | input | TCELL33:IMUX.IMUX25.DELAY |
| RXDLYALIGNMONENB | input | TCELL33:IMUX.IMUX28.DELAY |
| RXDLYALIGNMONITOR0 | output | TCELL35:OUT21.TMIN |
| RXDLYALIGNMONITOR1 | output | TCELL35:OUT15.TMIN |
| RXDLYALIGNMONITOR2 | output | TCELL35:OUT7.TMIN |
| RXDLYALIGNMONITOR3 | output | TCELL35:OUT20.TMIN |
| RXDLYALIGNMONITOR4 | output | TCELL35:OUT23.TMIN |
| RXDLYALIGNMONITOR5 | output | TCELL35:OUT19.TMIN |
| RXDLYALIGNMONITOR6 | output | TCELL35:OUT18.TMIN |
| RXDLYALIGNMONITOR7 | output | TCELL35:OUT0.TMIN |
| RXDLYALIGNOVERRIDE | input | TCELL35:IMUX.IMUX33.DELAY |
| RXDLYALIGNRESET | input | TCELL35:IMUX.IMUX29.DELAY |
| RXDLYALIGNSWPPRECURB | input | TCELL33:IMUX.IMUX29.DELAY |
| RXDLYALIGNTESTMODEENB | input | TCELL33:IMUX.IMUX12.DELAY |
| RXDLYALIGNUPDSW | input | TCELL35:IMUX.IMUX10.DELAY |
| RXELECIDLE | output | TCELL35:OUT3.TMIN |
| RXENCHANSYNC | input | TCELL31:IMUX.IMUX38.DELAY |
| RXENMCOMMAALIGN | input | TCELL31:IMUX.IMUX36.DELAY |
| RXENPCOMMAALIGN | input | TCELL31:IMUX.IMUX37.DELAY |
| RXENPMAPHASEALIGN | input | TCELL31:IMUX.IMUX35.DELAY |
| RXENPRBSTST0 | input | TCELL31:IMUX.IMUX33.DELAY |
| RXENPRBSTST1 | input | TCELL31:IMUX.IMUX34.DELAY |
| RXENPRBSTST2 | input | TCELL31:IMUX.IMUX18.DELAY |
| RXENSAMPLEALIGN | input | TCELL31:IMUX.IMUX32.DELAY |
| RXEQMIX0 | input | TCELL31:IMUX.IMUX14.DELAY |
| RXEQMIX1 | input | TCELL31:IMUX.IMUX15.DELAY |
| RXEQMIX2 | input | TCELL31:IMUX.IMUX30.DELAY |
| RXEQMIX3 | input | TCELL31:IMUX.IMUX22.DELAY |
| RXEQMIX4 | input | TCELL31:IMUX.IMUX29.DELAY |
| RXEQMIX5 | input | TCELL31:IMUX.IMUX21.DELAY |
| RXEQMIX6 | input | TCELL31:IMUX.IMUX28.DELAY |
| RXEQMIX7 | input | TCELL31:IMUX.IMUX20.DELAY |
| RXEQMIX8 | input | TCELL31:IMUX.IMUX27.DELAY |
| RXEQMIX9 | input | TCELL31:IMUX.IMUX19.DELAY |
| RXGEARBOXSLIP | input | TCELL31:IMUX.IMUX12.DELAY |
| RXHEADER0 | output | TCELL35:OUT10.TMIN |
| RXHEADER1 | output | TCELL35:OUT16.TMIN |
| RXHEADER2 | output | TCELL35:OUT17.TMIN |
| RXHEADERVALID | output | TCELL35:OUT11.TMIN |
| RXLOSSOFSYNC0 | output | TCELL32:OUT0.TMIN |
| RXLOSSOFSYNC1 | output | TCELL32:OUT22.TMIN |
| RXNOTINTABLE0 | output | TCELL33:OUT11.TMIN |
| RXNOTINTABLE1 | output | TCELL33:OUT7.TMIN |
| RXNOTINTABLE2 | output | TCELL33:OUT15.TMIN |
| RXNOTINTABLE3 | output | TCELL33:OUT3.TMIN |
| RXOVERSAMPLEERR | output | TCELL34:OUT22.TMIN |
| RXPLLLKDET | output | TCELL34:OUT5.TMIN |
| RXPLLLKDETEN | input | TCELL32:IMUX.IMUX20.DELAY |
| RXPLLPOWERDOWN | input | TCELL32:IMUX.IMUX21.DELAY |
| RXPLLREFSELDY0 | input | TCELL33:IMUX.IMUX37.DELAY |
| RXPLLREFSELDY1 | input | TCELL33:IMUX.IMUX22.DELAY |
| RXPLLREFSELDY2 | input | TCELL33:IMUX.IMUX39.DELAY |
| RXPMASETPHASE | input | TCELL31:IMUX.IMUX11.DELAY |
| RXPOLARITY | input | TCELL31:IMUX.IMUX26.DELAY |
| RXPOWERDOWN0 | input | TCELL34:IMUX.IMUX13.DELAY |
| RXPOWERDOWN1 | input | TCELL34:IMUX.IMUX21.DELAY |
| RXPRBSERR | output | TCELL35:OUT2.TMIN |
| RXRATE0 | input | TCELL36:IMUX.IMUX42.DELAY |
| RXRATE1 | input | TCELL36:IMUX.IMUX41.DELAY |
| RXRATEDONE | output | TCELL36:OUT20.TMIN |
| RXRECCLKPCS | output | TCELL35:OUT5.TMIN |
| RXRESET | input | TCELL32:IMUX.CTRL1 |
| RXRESETDONE | output | TCELL35:OUT22.TMIN |
| RXRUNDISP0 | output | TCELL33:OUT9.TMIN |
| RXRUNDISP1 | output | TCELL33:OUT5.TMIN |
| RXRUNDISP2 | output | TCELL33:OUT19.TMIN |
| RXRUNDISP3 | output | TCELL33:OUT1.TMIN |
| RXSLIDE | input | TCELL31:IMUX.IMUX9.DELAY |
| RXSTARTOFSEQ | output | TCELL35:OUT1.TMIN |
| RXSTATUS0 | output | TCELL34:OUT14.TMIN |
| RXSTATUS1 | output | TCELL34:OUT16.TMIN |
| RXSTATUS2 | output | TCELL34:OUT13.TMIN |
| RXUSRCLK | input | TCELL32:IMUX.CLK0 |
| RXUSRCLK2 | input | TCELL32:IMUX.CLK1 |
| RXVALID | output | TCELL35:OUT4.TMIN |
| SCANCLK | input | TCELL34:IMUX.CLK1 |
| SCANENB | input | TCELL30:IMUX.IMUX37.DELAY |
| SCANIN0 | input | TCELL38:IMUX.IMUX33.DELAY |
| SCANIN1 | input | TCELL38:IMUX.IMUX25.DELAY |
| SCANIN2 | input | TCELL30:IMUX.IMUX38.DELAY |
| SCANIN3 | input | TCELL30:IMUX.IMUX22.DELAY |
| SCANIN4 | input | TCELL38:IMUX.IMUX9.DELAY |
| SCANMODEB | input | TCELL30:IMUX.IMUX29.DELAY |
| SCANOUT0 | output | TCELL34:OUT18.TMIN |
| SCANOUT1 | output | TCELL34:OUT4.TMIN |
| SCANOUT2 | output | TCELL30:OUT23.TMIN |
| SCANOUT3 | output | TCELL30:OUT13.TMIN |
| SCANOUT4 | output | TCELL30:OUT8.TMIN |
| TSTCLK0 | input | TCELL33:IMUX.CLK1 |
| TSTCLK1 | input | TCELL35:IMUX.CLK1 |
| TSTIN0 | input | TCELL30:IMUX.IMUX30.DELAY |
| TSTIN1 | input | TCELL30:IMUX.IMUX14.DELAY |
| TSTIN10 | input | TCELL30:IMUX.IMUX31.DELAY |
| TSTIN11 | input | TCELL30:IMUX.IMUX21.DELAY |
| TSTIN12 | input | TCELL30:IMUX.IMUX13.DELAY |
| TSTIN13 | input | TCELL30:IMUX.IMUX28.DELAY |
| TSTIN14 | input | TCELL30:IMUX.IMUX32.DELAY |
| TSTIN15 | input | TCELL30:IMUX.IMUX16.DELAY |
| TSTIN16 | input | TCELL30:IMUX.IMUX40.DELAY |
| TSTIN17 | input | TCELL30:IMUX.IMUX0.DELAY |
| TSTIN18 | input | TCELL30:IMUX.IMUX1.DELAY |
| TSTIN19 | input | TCELL30:IMUX.IMUX41.DELAY |
| TSTIN2 | input | TCELL30:IMUX.IMUX27.DELAY |
| TSTIN3 | input | TCELL30:IMUX.IMUX11.DELAY |
| TSTIN4 | input | TCELL30:IMUX.IMUX26.DELAY |
| TSTIN5 | input | TCELL30:IMUX.IMUX10.DELAY |
| TSTIN6 | input | TCELL30:IMUX.IMUX25.DELAY |
| TSTIN7 | input | TCELL30:IMUX.IMUX9.DELAY |
| TSTIN8 | input | TCELL30:IMUX.IMUX24.DELAY |
| TSTIN9 | input | TCELL30:IMUX.IMUX8.DELAY |
| TSTOUT0 | output | TCELL31:OUT21.TMIN |
| TSTOUT1 | output | TCELL31:OUT17.TMIN |
| TSTOUT2 | output | TCELL31:OUT10.TMIN |
| TSTOUT3 | output | TCELL31:OUT20.TMIN |
| TSTOUT4 | output | TCELL31:OUT14.TMIN |
| TSTOUT5 | output | TCELL31:OUT23.TMIN |
| TSTOUT6 | output | TCELL31:OUT13.TMIN |
| TSTOUT7 | output | TCELL31:OUT19.TMIN |
| TSTOUT8 | output | TCELL31:OUT8.TMIN |
| TSTOUT9 | output | TCELL31:OUT12.TMIN |
| TSTPWRDN0 | input | TCELL30:IMUX.IMUX33.DELAY |
| TSTPWRDN1 | input | TCELL30:IMUX.IMUX18.DELAY |
| TSTPWRDN2 | input | TCELL30:IMUX.IMUX34.DELAY |
| TSTPWRDN3 | input | TCELL30:IMUX.IMUX19.DELAY |
| TSTPWRDN4 | input | TCELL30:IMUX.IMUX35.DELAY |
| TSTPWRDNOVRD | input | TCELL30:IMUX.IMUX17.DELAY |
| TXBUFDIFFCTRL0 | input | TCELL33:IMUX.IMUX0.DELAY |
| TXBUFDIFFCTRL1 | input | TCELL33:IMUX.IMUX16.DELAY |
| TXBUFDIFFCTRL2 | input | TCELL33:IMUX.IMUX18.DELAY |
| TXBUFSTATUS0 | output | TCELL37:OUT5.TMIN |
| TXBUFSTATUS1 | output | TCELL37:OUT17.TMIN |
| TXBYPASS8B10B0 | input | TCELL35:IMUX.IMUX11.DELAY |
| TXBYPASS8B10B1 | input | TCELL35:IMUX.IMUX27.DELAY |
| TXBYPASS8B10B2 | input | TCELL35:IMUX.IMUX35.DELAY |
| TXBYPASS8B10B3 | input | TCELL35:IMUX.IMUX19.DELAY |
| TXCHARDISPMODE0 | input | TCELL35:IMUX.IMUX34.DELAY |
| TXCHARDISPMODE1 | input | TCELL35:IMUX.IMUX28.DELAY |
| TXCHARDISPMODE2 | input | TCELL35:IMUX.IMUX37.DELAY |
| TXCHARDISPMODE3 | input | TCELL35:IMUX.IMUX21.DELAY |
| TXCHARDISPVAL0 | input | TCELL35:IMUX.IMUX44.DELAY |
| TXCHARDISPVAL1 | input | TCELL35:IMUX.IMUX30.DELAY |
| TXCHARDISPVAL2 | input | TCELL35:IMUX.IMUX38.DELAY |
| TXCHARDISPVAL3 | input | TCELL35:IMUX.IMUX22.DELAY |
| TXCHARISK0 | input | TCELL35:IMUX.IMUX26.DELAY |
| TXCHARISK1 | input | TCELL35:IMUX.IMUX36.DELAY |
| TXCHARISK2 | input | TCELL35:IMUX.IMUX39.DELAY |
| TXCHARISK3 | input | TCELL35:IMUX.IMUX23.DELAY |
| TXCOMINIT | input | TCELL37:IMUX.IMUX18.DELAY |
| TXCOMSAS | input | TCELL37:IMUX.IMUX19.DELAY |
| TXCOMWAKE | input | TCELL37:IMUX.IMUX10.DELAY |
| TXDATA0 | input | TCELL38:IMUX.IMUX38.DELAY |
| TXDATA1 | input | TCELL38:IMUX.IMUX36.DELAY |
| TXDATA10 | input | TCELL37:IMUX.IMUX13.DELAY |
| TXDATA11 | input | TCELL37:IMUX.IMUX40.DELAY |
| TXDATA12 | input | TCELL36:IMUX.IMUX3.DELAY |
| TXDATA13 | input | TCELL36:IMUX.IMUX30.DELAY |
| TXDATA14 | input | TCELL36:IMUX.IMUX5.DELAY |
| TXDATA15 | input | TCELL36:IMUX.IMUX13.DELAY |
| TXDATA16 | input | TCELL38:IMUX.IMUX31.DELAY |
| TXDATA17 | input | TCELL38:IMUX.IMUX30.DELAY |
| TXDATA18 | input | TCELL38:IMUX.IMUX29.DELAY |
| TXDATA19 | input | TCELL38:IMUX.IMUX27.DELAY |
| TXDATA2 | input | TCELL38:IMUX.IMUX28.DELAY |
| TXDATA20 | input | TCELL37:IMUX.IMUX27.DELAY |
| TXDATA21 | input | TCELL37:IMUX.IMUX28.DELAY |
| TXDATA22 | input | TCELL37:IMUX.IMUX25.DELAY |
| TXDATA23 | input | TCELL37:IMUX.IMUX24.DELAY |
| TXDATA24 | input | TCELL38:IMUX.IMUX39.DELAY |
| TXDATA25 | input | TCELL38:IMUX.IMUX19.DELAY |
| TXDATA26 | input | TCELL38:IMUX.IMUX37.DELAY |
| TXDATA27 | input | TCELL38:IMUX.IMUX35.DELAY |
| TXDATA28 | input | TCELL37:IMUX.IMUX35.DELAY |
| TXDATA29 | input | TCELL37:IMUX.IMUX36.DELAY |
| TXDATA3 | input | TCELL38:IMUX.IMUX32.DELAY |
| TXDATA30 | input | TCELL37:IMUX.IMUX33.DELAY |
| TXDATA31 | input | TCELL37:IMUX.IMUX32.DELAY |
| TXDATA4 | input | TCELL38:IMUX.IMUX26.DELAY |
| TXDATA5 | input | TCELL38:IMUX.IMUX34.DELAY |
| TXDATA6 | input | TCELL37:IMUX.IMUX34.DELAY |
| TXDATA7 | input | TCELL37:IMUX.IMUX26.DELAY |
| TXDATA8 | input | TCELL37:IMUX.IMUX15.DELAY |
| TXDATA9 | input | TCELL37:IMUX.IMUX21.DELAY |
| TXDEEMPH | input | TCELL33:IMUX.IMUX3.DELAY |
| TXDETECTRX | input | TCELL34:IMUX.IMUX9.DELAY |
| TXDIFFCTRL0 | input | TCELL33:IMUX.IMUX21.DELAY |
| TXDIFFCTRL1 | input | TCELL33:IMUX.IMUX38.DELAY |
| TXDIFFCTRL2 | input | TCELL33:IMUX.IMUX5.DELAY |
| TXDIFFCTRL3 | input | TCELL33:IMUX.IMUX30.DELAY |
| TXDLYALIGNDISABLE | input | TCELL35:IMUX.IMUX46.DELAY |
| TXDLYALIGNFORCEROTATEB | input | TCELL37:IMUX.IMUX9.DELAY |
| TXDLYALIGNMONENB | input | TCELL37:IMUX.IMUX11.DELAY |
| TXDLYALIGNMONITOR0 | output | TCELL37:OUT21.TMIN |
| TXDLYALIGNMONITOR1 | output | TCELL37:OUT16.TMIN |
| TXDLYALIGNMONITOR2 | output | TCELL37:OUT4.TMIN |
| TXDLYALIGNMONITOR3 | output | TCELL37:OUT20.TMIN |
| TXDLYALIGNMONITOR4 | output | TCELL37:OUT23.TMIN |
| TXDLYALIGNMONITOR5 | output | TCELL37:OUT19.TMIN |
| TXDLYALIGNMONITOR6 | output | TCELL37:OUT18.TMIN |
| TXDLYALIGNMONITOR7 | output | TCELL37:OUT0.TMIN |
| TXDLYALIGNOVERRIDE | input | TCELL35:IMUX.IMUX25.DELAY |
| TXDLYALIGNRESET | input | TCELL35:IMUX.IMUX13.DELAY |
| TXDLYALIGNTESTMODEENB | input | TCELL37:IMUX.IMUX30.DELAY |
| TXDLYALIGNUPDSW | input | TCELL35:IMUX.IMUX2.DELAY |
| TXELECIDLE | input | TCELL34:IMUX.IMUX32.DELAY |
| TXENC8B10BUSE | input | TCELL37:IMUX.IMUX22.DELAY |
| TXENPMAPHASEALIGN | input | TCELL38:IMUX.IMUX17.DELAY |
| TXENPRBSTST0 | input | TCELL36:IMUX.IMUX39.DELAY |
| TXENPRBSTST1 | input | TCELL36:IMUX.IMUX23.DELAY |
| TXENPRBSTST2 | input | TCELL36:IMUX.IMUX15.DELAY |
| TXGEARBOXREADY | output | TCELL36:OUT4.TMIN |
| TXHEADER0 | input | TCELL35:IMUX.IMUX8.DELAY |
| TXHEADER1 | input | TCELL35:IMUX.IMUX16.DELAY |
| TXHEADER2 | input | TCELL35:IMUX.IMUX32.DELAY |
| TXINHIBIT | input | TCELL35:IMUX.IMUX17.DELAY |
| TXKERR0 | output | TCELL37:OUT14.TMIN |
| TXKERR1 | output | TCELL37:OUT10.TMIN |
| TXKERR2 | output | TCELL37:OUT11.TMIN |
| TXKERR3 | output | TCELL37:OUT15.TMIN |
| TXMARGIN0 | input | TCELL34:IMUX.IMUX11.DELAY |
| TXMARGIN1 | input | TCELL34:IMUX.IMUX26.DELAY |
| TXMARGIN2 | input | TCELL35:IMUX.IMUX15.DELAY |
| TXOUTCLKPCS | output | TCELL36:OUT8.TMIN |
| TXPDOWNASYNCH | input | TCELL38:IMUX.IMUX15.DELAY |
| TXPLLLKDET | output | TCELL38:OUT5.TMIN |
| TXPLLLKDETEN | input | TCELL37:IMUX.IMUX12.DELAY |
| TXPLLPOWERDOWN | input | TCELL37:IMUX.IMUX29.DELAY |
| TXPLLREFSELDY0 | input | TCELL37:IMUX.IMUX37.DELAY |
| TXPLLREFSELDY1 | input | TCELL37:IMUX.IMUX38.DELAY |
| TXPLLREFSELDY2 | input | TCELL37:IMUX.IMUX39.DELAY |
| TXPMASETPHASE | input | TCELL35:IMUX.IMUX18.DELAY |
| TXPOLARITY | input | TCELL35:IMUX.IMUX9.DELAY |
| TXPOSTEMPHASIS0 | input | TCELL38:IMUX.IMUX10.DELAY |
| TXPOSTEMPHASIS1 | input | TCELL38:IMUX.IMUX18.DELAY |
| TXPOSTEMPHASIS2 | input | TCELL38:IMUX.IMUX12.DELAY |
| TXPOSTEMPHASIS3 | input | TCELL38:IMUX.IMUX20.DELAY |
| TXPOSTEMPHASIS4 | input | TCELL38:IMUX.IMUX22.DELAY |
| TXPOWERDOWN0 | input | TCELL34:IMUX.IMUX28.DELAY |
| TXPOWERDOWN1 | input | TCELL34:IMUX.IMUX36.DELAY |
| TXPRBSFORCEERR | input | TCELL38:IMUX.IMUX13.DELAY |
| TXPREEMPHASIS0 | input | TCELL33:IMUX.IMUX26.DELAY |
| TXPREEMPHASIS1 | input | TCELL33:IMUX.IMUX19.DELAY |
| TXPREEMPHASIS2 | input | TCELL33:IMUX.IMUX17.DELAY |
| TXPREEMPHASIS3 | input | TCELL33:IMUX.IMUX9.DELAY |
| TXRATE0 | input | TCELL36:IMUX.IMUX34.DELAY |
| TXRATE1 | input | TCELL36:IMUX.IMUX33.DELAY |
| TXRATEDONE | output | TCELL36:OUT23.TMIN |
| TXRESET | input | TCELL36:IMUX.CTRL0 |
| TXRESETDONE | output | TCELL37:OUT22.TMIN |
| TXRUNDISP0 | output | TCELL38:OUT14.TMIN |
| TXRUNDISP1 | output | TCELL38:OUT10.TMIN |
| TXRUNDISP2 | output | TCELL38:OUT11.TMIN |
| TXRUNDISP3 | output | TCELL38:OUT15.TMIN |
| TXSEQUENCE0 | input | TCELL36:IMUX.IMUX11.DELAY |
| TXSEQUENCE1 | input | TCELL36:IMUX.IMUX19.DELAY |
| TXSEQUENCE2 | input | TCELL36:IMUX.IMUX35.DELAY |
| TXSEQUENCE3 | input | TCELL36:IMUX.IMUX8.DELAY |
| TXSEQUENCE4 | input | TCELL36:IMUX.IMUX24.DELAY |
| TXSEQUENCE5 | input | TCELL36:IMUX.IMUX22.DELAY |
| TXSEQUENCE6 | input | TCELL36:IMUX.IMUX38.DELAY |
| TXSTARTSEQ | input | TCELL37:IMUX.IMUX14.DELAY |
| TXSWING | input | TCELL33:IMUX.IMUX13.DELAY |
| TXUSRCLK | input | TCELL36:IMUX.CLK0 |
| TXUSRCLK2 | input | TCELL36:IMUX.CLK1 |
| USRCODEERR | input | TCELL32:IMUX.IMUX14.DELAY |
Bel BUFDS0
| Pin | Direction | Wires |
|---|---|---|
| CEB | input | TCELL19:IMUX.IMUX31.DELAY |
| CLKTESTSIG_INT | input | TCELL12:IMUX.IMUX17.DELAY |
Bel BUFDS1
| Pin | Direction | Wires |
|---|---|---|
| CEB | input | TCELL19:IMUX.IMUX30.DELAY |
| CLKTESTSIG_INT | input | TCELL12:IMUX.IMUX16.DELAY |
Bel IPAD_CLKP0
| Pin | Direction | Wires |
|---|
Bel IPAD_CLKN0
| Pin | Direction | Wires |
|---|
Bel IPAD_CLKP1
| Pin | Direction | Wires |
|---|
Bel IPAD_CLKN1
| Pin | Direction | Wires |
|---|
Bel IPAD_RXP0
| Pin | Direction | Wires |
|---|
Bel IPAD_RXN0
| Pin | Direction | Wires |
|---|
Bel IPAD_RXP1
| Pin | Direction | Wires |
|---|
Bel IPAD_RXN1
| Pin | Direction | Wires |
|---|
Bel IPAD_RXP2
| Pin | Direction | Wires |
|---|
Bel IPAD_RXN2
| Pin | Direction | Wires |
|---|
Bel IPAD_RXP3
| Pin | Direction | Wires |
|---|
Bel IPAD_RXN3
| Pin | Direction | Wires |
|---|
Bel OPAD_TXP0
| Pin | Direction | Wires |
|---|
Bel OPAD_TXN0
| Pin | Direction | Wires |
|---|
Bel OPAD_TXP1
| Pin | Direction | Wires |
|---|
Bel OPAD_TXN1
| Pin | Direction | Wires |
|---|
Bel OPAD_TXP2
| Pin | Direction | Wires |
|---|
Bel OPAD_TXN2
| Pin | Direction | Wires |
|---|
Bel OPAD_TXP3
| Pin | Direction | Wires |
|---|
Bel OPAD_TXN3
| Pin | Direction | Wires |
|---|
Bel HCLK_GTX
| Pin | Direction | Wires |
|---|
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:IMUX.CTRL1 | GTX0.PRBSCNTRESET |
| TCELL0:IMUX.IMUX0.DELAY | GTX0.TSTIN17 |
| TCELL0:IMUX.IMUX1.DELAY | GTX0.TSTIN18 |
| TCELL0:IMUX.IMUX8.DELAY | GTX0.TSTIN9 |
| TCELL0:IMUX.IMUX9.DELAY | GTX0.TSTIN7 |
| TCELL0:IMUX.IMUX10.DELAY | GTX0.TSTIN5 |
| TCELL0:IMUX.IMUX11.DELAY | GTX0.TSTIN3 |
| TCELL0:IMUX.IMUX13.DELAY | GTX0.TSTIN12 |
| TCELL0:IMUX.IMUX14.DELAY | GTX0.TSTIN1 |
| TCELL0:IMUX.IMUX16.DELAY | GTX0.TSTIN15 |
| TCELL0:IMUX.IMUX17.DELAY | GTX0.TSTPWRDNOVRD |
| TCELL0:IMUX.IMUX18.DELAY | GTX0.TSTPWRDN1 |
| TCELL0:IMUX.IMUX19.DELAY | GTX0.TSTPWRDN3 |
| TCELL0:IMUX.IMUX21.DELAY | GTX0.TSTIN11 |
| TCELL0:IMUX.IMUX22.DELAY | GTX0.SCANIN3 |
| TCELL0:IMUX.IMUX24.DELAY | GTX0.TSTIN8 |
| TCELL0:IMUX.IMUX25.DELAY | GTX0.TSTIN6 |
| TCELL0:IMUX.IMUX26.DELAY | GTX0.TSTIN4 |
| TCELL0:IMUX.IMUX27.DELAY | GTX0.TSTIN2 |
| TCELL0:IMUX.IMUX28.DELAY | GTX0.TSTIN13 |
| TCELL0:IMUX.IMUX29.DELAY | GTX0.SCANMODEB |
| TCELL0:IMUX.IMUX30.DELAY | GTX0.TSTIN0 |
| TCELL0:IMUX.IMUX31.DELAY | GTX0.TSTIN10 |
| TCELL0:IMUX.IMUX32.DELAY | GTX0.TSTIN14 |
| TCELL0:IMUX.IMUX33.DELAY | GTX0.TSTPWRDN0 |
| TCELL0:IMUX.IMUX34.DELAY | GTX0.TSTPWRDN2 |
| TCELL0:IMUX.IMUX35.DELAY | GTX0.TSTPWRDN4 |
| TCELL0:IMUX.IMUX37.DELAY | GTX0.SCANENB |
| TCELL0:IMUX.IMUX38.DELAY | GTX0.SCANIN2 |
| TCELL0:IMUX.IMUX40.DELAY | GTX0.TSTIN16 |
| TCELL0:IMUX.IMUX41.DELAY | GTX0.TSTIN19 |
| TCELL0:OUT0.TMIN | GTX0.RXDATA18 |
| TCELL0:OUT1.TMIN | GTX0.RXDATA4 |
| TCELL0:OUT2.TMIN | GTX0.RXDATA3 |
| TCELL0:OUT3.TMIN | GTX0.RXDATA17 |
| TCELL0:OUT4.TMIN | GTX0.RXDATA0 |
| TCELL0:OUT5.TMIN | GTX0.RXDATA5 |
| TCELL0:OUT6.TMIN | GTX0.RXDATA2 |
| TCELL0:OUT7.TMIN | GTX0.RXDATA1 |
| TCELL0:OUT8.TMIN | GTX0.SCANOUT4 |
| TCELL0:OUT13.TMIN | GTX0.SCANOUT3 |
| TCELL0:OUT15.TMIN | GTX0.RXDATA16 |
| TCELL0:OUT16.TMIN | GTX0.RXDATA22 |
| TCELL0:OUT17.TMIN | GTX0.RXDATA21 |
| TCELL0:OUT18.TMIN | GTX0.RXDATA20 |
| TCELL0:OUT20.TMIN | GTX0.RXDATA23 |
| TCELL0:OUT22.TMIN | GTX0.RXDATA19 |
| TCELL0:OUT23.TMIN | GTX0.SCANOUT2 |
| TCELL1:IMUX.CTRL0 | GTX0.GTXRXRESET |
| TCELL1:IMUX.CTRL1 | GTX0.RXCDRRESET |
| TCELL1:IMUX.IMUX9.DELAY | GTX0.RXSLIDE |
| TCELL1:IMUX.IMUX11.DELAY | GTX0.RXPMASETPHASE |
| TCELL1:IMUX.IMUX12.DELAY | GTX0.RXGEARBOXSLIP |
| TCELL1:IMUX.IMUX14.DELAY | GTX0.RXEQMIX0 |
| TCELL1:IMUX.IMUX15.DELAY | GTX0.RXEQMIX1 |
| TCELL1:IMUX.IMUX18.DELAY | GTX0.RXENPRBSTST2 |
| TCELL1:IMUX.IMUX19.DELAY | GTX0.RXEQMIX9 |
| TCELL1:IMUX.IMUX20.DELAY | GTX0.RXEQMIX7 |
| TCELL1:IMUX.IMUX21.DELAY | GTX0.RXEQMIX5 |
| TCELL1:IMUX.IMUX22.DELAY | GTX0.RXEQMIX3 |
| TCELL1:IMUX.IMUX24.DELAY | GTX0.RXBUFWE |
| TCELL1:IMUX.IMUX26.DELAY | GTX0.RXPOLARITY |
| TCELL1:IMUX.IMUX27.DELAY | GTX0.RXEQMIX8 |
| TCELL1:IMUX.IMUX28.DELAY | GTX0.RXEQMIX6 |
| TCELL1:IMUX.IMUX29.DELAY | GTX0.RXEQMIX4 |
| TCELL1:IMUX.IMUX30.DELAY | GTX0.RXEQMIX2 |
| TCELL1:IMUX.IMUX32.DELAY | GTX0.RXENSAMPLEALIGN |
| TCELL1:IMUX.IMUX33.DELAY | GTX0.RXENPRBSTST0 |
| TCELL1:IMUX.IMUX34.DELAY | GTX0.RXENPRBSTST1 |
| TCELL1:IMUX.IMUX35.DELAY | GTX0.RXENPMAPHASEALIGN |
| TCELL1:IMUX.IMUX36.DELAY | GTX0.RXENMCOMMAALIGN |
| TCELL1:IMUX.IMUX37.DELAY | GTX0.RXENPCOMMAALIGN |
| TCELL1:IMUX.IMUX38.DELAY | GTX0.RXENCHANSYNC |
| TCELL1:IMUX.IMUX39.DELAY | GTX0.RXDEC8B10BUSE |
| TCELL1:OUT0.TMIN | GTX0.RXDATA24 |
| TCELL1:OUT1.TMIN | GTX0.RXDATA6 |
| TCELL1:OUT2.TMIN | GTX0.RXDATA11 |
| TCELL1:OUT3.TMIN | GTX0.RXDATA31 |
| TCELL1:OUT4.TMIN | GTX0.RXDATA8 |
| TCELL1:OUT5.TMIN | GTX0.RXDATA7 |
| TCELL1:OUT6.TMIN | GTX0.RXDATA10 |
| TCELL1:OUT7.TMIN | GTX0.RXDATA9 |
| TCELL1:OUT8.TMIN | GTX0.TSTOUT8 |
| TCELL1:OUT9.TMIN | GTX0.RXDATA27 |
| TCELL1:OUT10.TMIN | GTX0.TSTOUT2 |
| TCELL1:OUT11.TMIN | GTX0.RXDATA29 |
| TCELL1:OUT12.TMIN | GTX0.TSTOUT9 |
| TCELL1:OUT13.TMIN | GTX0.TSTOUT6 |
| TCELL1:OUT14.TMIN | GTX0.TSTOUT4 |
| TCELL1:OUT15.TMIN | GTX0.RXDATA30 |
| TCELL1:OUT16.TMIN | GTX0.RXDATA28 |
| TCELL1:OUT17.TMIN | GTX0.TSTOUT1 |
| TCELL1:OUT18.TMIN | GTX0.RXDATA26 |
| TCELL1:OUT19.TMIN | GTX0.TSTOUT7 |
| TCELL1:OUT20.TMIN | GTX0.TSTOUT3 |
| TCELL1:OUT21.TMIN | GTX0.TSTOUT0 |
| TCELL1:OUT22.TMIN | GTX0.RXDATA25 |
| TCELL1:OUT23.TMIN | GTX0.TSTOUT5 |
| TCELL2:IMUX.CLK0 | GTX0.RXUSRCLK |
| TCELL2:IMUX.CLK1 | GTX0.RXUSRCLK2 |
| TCELL2:IMUX.CTRL0 | GTX0.RXBUFRESET |
| TCELL2:IMUX.CTRL1 | GTX0.RXRESET |
| TCELL2:IMUX.IMUX8.DELAY | GTX0.RXCHBONDSLAVE |
| TCELL2:IMUX.IMUX10.DELAY | GTX0.RXCHBONDLEVEL0 |
| TCELL2:IMUX.IMUX11.DELAY | GTX0.RXCHBONDLEVEL2 |
| TCELL2:IMUX.IMUX14.DELAY | GTX0.USRCODEERR |
| TCELL2:IMUX.IMUX18.DELAY | GTX0.CLKTESTSIG1 |
| TCELL2:IMUX.IMUX19.DELAY | GTX0.CLKTESTSIG0 |
| TCELL2:IMUX.IMUX20.DELAY | GTX0.RXPLLLKDETEN |
| TCELL2:IMUX.IMUX21.DELAY | GTX0.RXPLLPOWERDOWN |
| TCELL2:IMUX.IMUX24.DELAY | GTX0.RXCHBONDMASTER |
| TCELL2:IMUX.IMUX26.DELAY | GTX0.RXCHBONDLEVEL1 |
| TCELL2:IMUX.IMUX27.DELAY | GTX0.GTXTEST12 |
| TCELL2:IMUX.IMUX28.DELAY | GTX0.GTXTEST11 |
| TCELL2:IMUX.IMUX29.DELAY | GTX0.GTXTEST10 |
| TCELL2:IMUX.IMUX30.DELAY | GTX0.GTXTEST9 |
| TCELL2:IMUX.IMUX31.DELAY | GTX0.GTXTEST8 |
| TCELL2:IMUX.IMUX32.DELAY | GTX0.GTXTEST7 |
| TCELL2:IMUX.IMUX33.DELAY | GTX0.GTXTEST6 |
| TCELL2:IMUX.IMUX34.DELAY | GTX0.GTXTEST5 |
| TCELL2:IMUX.IMUX35.DELAY | GTX0.GTXTEST4 |
| TCELL2:IMUX.IMUX36.DELAY | GTX0.GTXTEST3 |
| TCELL2:IMUX.IMUX37.DELAY | GTX0.GTXTEST2 |
| TCELL2:IMUX.IMUX38.DELAY | GTX0.GTXTEST1 |
| TCELL2:IMUX.IMUX39.DELAY | GTX0.GTXTEST0 |
| TCELL2:OUT0.TMIN | GTX0.RXLOSSOFSYNC0 |
| TCELL2:OUT1.TMIN | GTX0.RXDATA15 |
| TCELL2:OUT2.TMIN | GTX0.RXDATA14 |
| TCELL2:OUT3.TMIN | GTX0.RXCHARISK3 |
| TCELL2:OUT4.TMIN | GTX0.RXDATAVALID |
| TCELL2:OUT5.TMIN | GTX0.RXCHARISK1 |
| TCELL2:OUT6.TMIN | GTX0.RXDATA13 |
| TCELL2:OUT7.TMIN | GTX0.RXDATA12 |
| TCELL2:OUT8.TMIN | GTX0.RXCHARISCOMMA2 |
| TCELL2:OUT10.TMIN | GTX0.RXBYTEREALIGN |
| TCELL2:OUT13.TMIN | GTX0.RXBYTEISALIGNED |
| TCELL2:OUT14.TMIN | GTX0.RXCHANREALIGN |
| TCELL2:OUT15.TMIN | GTX0.RXCHARISK2 |
| TCELL2:OUT18.TMIN | GTX0.RXCHARISCOMMA3 |
| TCELL2:OUT19.TMIN | GTX0.COMSASDET |
| TCELL2:OUT20.TMIN | GTX0.COMINITDET |
| TCELL2:OUT22.TMIN | GTX0.RXLOSSOFSYNC1 |
| TCELL2:OUT23.TMIN | GTX0.COMWAKEDET |
| TCELL3:IMUX.CLK0 | GTX0.GREFCLKRX |
| TCELL3:IMUX.CLK1 | GTX0.TSTCLK0 |
| TCELL3:IMUX.CTRL0 | GTX0.PLLRXRESET |
| TCELL3:IMUX.IMUX0.DELAY | GTX0.TXBUFDIFFCTRL0 |
| TCELL3:IMUX.IMUX3.DELAY | GTX0.TXDEEMPH |
| TCELL3:IMUX.IMUX5.DELAY | GTX0.TXDIFFCTRL2 |
| TCELL3:IMUX.IMUX9.DELAY | GTX0.TXPREEMPHASIS3 |
| TCELL3:IMUX.IMUX11.DELAY | GTX0.LOOPBACK1 |
| TCELL3:IMUX.IMUX12.DELAY | GTX0.RXDLYALIGNTESTMODEENB |
| TCELL3:IMUX.IMUX13.DELAY | GTX0.TXSWING |
| TCELL3:IMUX.IMUX16.DELAY | GTX0.TXBUFDIFFCTRL1 |
| TCELL3:IMUX.IMUX17.DELAY | GTX0.TXPREEMPHASIS2 |
| TCELL3:IMUX.IMUX18.DELAY | GTX0.TXBUFDIFFCTRL2 |
| TCELL3:IMUX.IMUX19.DELAY | GTX0.TXPREEMPHASIS1 |
| TCELL3:IMUX.IMUX21.DELAY | GTX0.TXDIFFCTRL0 |
| TCELL3:IMUX.IMUX22.DELAY | GTX0.RXPLLREFSELDY1 |
| TCELL3:IMUX.IMUX24.DELAY | GTX0.LOOPBACK0 |
| TCELL3:IMUX.IMUX25.DELAY | GTX0.RXDLYALIGNFORCEROTATEB |
| TCELL3:IMUX.IMUX26.DELAY | GTX0.TXPREEMPHASIS0 |
| TCELL3:IMUX.IMUX27.DELAY | GTX0.LOOPBACK2 |
| TCELL3:IMUX.IMUX28.DELAY | GTX0.RXDLYALIGNMONENB |
| TCELL3:IMUX.IMUX29.DELAY | GTX0.RXDLYALIGNSWPPRECURB |
| TCELL3:IMUX.IMUX30.DELAY | GTX0.TXDIFFCTRL3 |
| TCELL3:IMUX.IMUX32.DELAY | GTX0.RXCHBONDI0 |
| TCELL3:IMUX.IMUX33.DELAY | GTX0.RXCHBONDI1 |
| TCELL3:IMUX.IMUX34.DELAY | GTX0.RXCHBONDI2 |
| TCELL3:IMUX.IMUX35.DELAY | GTX0.RXCHBONDI3 |
| TCELL3:IMUX.IMUX36.DELAY | GTX0.RXCOMMADETUSE |
| TCELL3:IMUX.IMUX37.DELAY | GTX0.RXPLLREFSELDY0 |
| TCELL3:IMUX.IMUX38.DELAY | GTX0.TXDIFFCTRL1 |
| TCELL3:IMUX.IMUX39.DELAY | GTX0.RXPLLREFSELDY2 |
| TCELL3:OUT0.TMIN | GTX0.RXDISPERR2 |
| TCELL3:OUT1.TMIN | GTX0.RXRUNDISP3 |
| TCELL3:OUT2.TMIN | GTX0.RXCHARISCOMMA1 |
| TCELL3:OUT3.TMIN | GTX0.RXNOTINTABLE3 |
| TCELL3:OUT4.TMIN | GTX0.RXDISPERR0 |
| TCELL3:OUT5.TMIN | GTX0.RXRUNDISP1 |
| TCELL3:OUT7.TMIN | GTX0.RXNOTINTABLE1 |
| TCELL3:OUT8.TMIN | GTX0.RXDISPERR1 |
| TCELL3:OUT9.TMIN | GTX0.RXRUNDISP0 |
| TCELL3:OUT11.TMIN | GTX0.RXNOTINTABLE0 |
| TCELL3:OUT13.TMIN | GTX0.RXCHANISALIGNED |
| TCELL3:OUT14.TMIN | GTX0.RXCHARISCOMMA0 |
| TCELL3:OUT15.TMIN | GTX0.RXNOTINTABLE2 |
| TCELL3:OUT16.TMIN | GTX0.RXCHARISK0 |
| TCELL3:OUT19.TMIN | GTX0.RXRUNDISP2 |
| TCELL3:OUT22.TMIN | GTX0.RXDISPERR3 |
| TCELL4:IMUX.CLK1 | GTX0.SCANCLK |
| TCELL4:IMUX.IMUX8.DELAY | GTX0.DFETAP10 |
| TCELL4:IMUX.IMUX9.DELAY | GTX0.TXDETECTRX |
| TCELL4:IMUX.IMUX10.DELAY | GTX0.DFETAP11 |
| TCELL4:IMUX.IMUX11.DELAY | GTX0.TXMARGIN0 |
| TCELL4:IMUX.IMUX13.DELAY | GTX0.RXPOWERDOWN0 |
| TCELL4:IMUX.IMUX14.DELAY | GTX0.DFETAP12 |
| TCELL4:IMUX.IMUX15.DELAY | GTX0.DFETAP13 |
| TCELL4:IMUX.IMUX16.DELAY | GTX0.DFECLKDLYADJ5 |
| TCELL4:IMUX.IMUX17.DELAY | GTX0.DFECLKDLYADJ4 |
| TCELL4:IMUX.IMUX18.DELAY | GTX0.DFECLKDLYADJ2 |
| TCELL4:IMUX.IMUX19.DELAY | GTX0.DFECLKDLYADJ1 |
| TCELL4:IMUX.IMUX21.DELAY | GTX0.RXPOWERDOWN1 |
| TCELL4:IMUX.IMUX24.DELAY | GTX0.DFETAP20 |
| TCELL4:IMUX.IMUX25.DELAY | GTX0.DFETAP21 |
| TCELL4:IMUX.IMUX26.DELAY | GTX0.TXMARGIN1 |
| TCELL4:IMUX.IMUX28.DELAY | GTX0.TXPOWERDOWN0 |
| TCELL4:IMUX.IMUX29.DELAY | GTX0.DFEDLYOVRD |
| TCELL4:IMUX.IMUX30.DELAY | GTX0.DFETAP22 |
| TCELL4:IMUX.IMUX31.DELAY | GTX0.DFETAP23 |
| TCELL4:IMUX.IMUX32.DELAY | GTX0.TXELECIDLE |
| TCELL4:IMUX.IMUX33.DELAY | GTX0.DFECLKDLYADJ3 |
| TCELL4:IMUX.IMUX35.DELAY | GTX0.DFECLKDLYADJ0 |
| TCELL4:IMUX.IMUX36.DELAY | GTX0.TXPOWERDOWN1 |
| TCELL4:IMUX.IMUX37.DELAY | GTX0.DFETAPOVRD |
| TCELL4:IMUX.IMUX38.DELAY | GTX0.DFETAP14 |
| TCELL4:IMUX.IMUX39.DELAY | GTX0.DFETAP24 |
| TCELL4:OUT0.TMIN | GTX0.MGTREFCLKFAB0 |
| TCELL4:OUT3.TMIN | GTX0.RXBUFSTATUS2 |
| TCELL4:OUT4.TMIN | GTX0.SCANOUT1 |
| TCELL4:OUT5.TMIN | GTX0.RXPLLLKDET |
| TCELL4:OUT6.TMIN | GTX0.RXBUFSTATUS0 |
| TCELL4:OUT7.TMIN | GTX0.RXBUFSTATUS1 |
| TCELL4:OUT8.TMIN | GTX0.PHYSTATUS |
| TCELL4:OUT10.TMIN | GTX0.RXCHBONDO1 |
| TCELL4:OUT11.TMIN | GTX0.RXCHBONDO2 |
| TCELL4:OUT12.TMIN | GTX0.MGTREFCLKFAB1 |
| TCELL4:OUT13.TMIN | GTX0.RXSTATUS2 |
| TCELL4:OUT14.TMIN | GTX0.RXSTATUS0 |
| TCELL4:OUT15.TMIN | GTX0.RXCHBONDO3 |
| TCELL4:OUT16.TMIN | GTX0.RXSTATUS1 |
| TCELL4:OUT17.TMIN | GTX0.RXCHBONDO0 |
| TCELL4:OUT18.TMIN | GTX0.SCANOUT0 |
| TCELL4:OUT22.TMIN | GTX0.RXOVERSAMPLEERR |
| TCELL5:IMUX.CLK1 | GTX0.TSTCLK1 |
| TCELL5:IMUX.CTRL1 | GTX0.PLLTXRESET |
| TCELL5:IMUX.IMUX2.DELAY | GTX0.TXDLYALIGNUPDSW |
| TCELL5:IMUX.IMUX8.DELAY | GTX0.TXHEADER0 |
| TCELL5:IMUX.IMUX9.DELAY | GTX0.TXPOLARITY |
| TCELL5:IMUX.IMUX10.DELAY | GTX0.RXDLYALIGNUPDSW |
| TCELL5:IMUX.IMUX11.DELAY | GTX0.TXBYPASS8B10B0 |
| TCELL5:IMUX.IMUX13.DELAY | GTX0.TXDLYALIGNRESET |
| TCELL5:IMUX.IMUX14.DELAY | GTX0.RXDLYALIGNDISABLE |
| TCELL5:IMUX.IMUX15.DELAY | GTX0.TXMARGIN2 |
| TCELL5:IMUX.IMUX16.DELAY | GTX0.TXHEADER1 |
| TCELL5:IMUX.IMUX17.DELAY | GTX0.TXINHIBIT |
| TCELL5:IMUX.IMUX18.DELAY | GTX0.TXPMASETPHASE |
| TCELL5:IMUX.IMUX19.DELAY | GTX0.TXBYPASS8B10B3 |
| TCELL5:IMUX.IMUX21.DELAY | GTX0.TXCHARDISPMODE3 |
| TCELL5:IMUX.IMUX22.DELAY | GTX0.TXCHARDISPVAL3 |
| TCELL5:IMUX.IMUX23.DELAY | GTX0.TXCHARISK3 |
| TCELL5:IMUX.IMUX25.DELAY | GTX0.TXDLYALIGNOVERRIDE |
| TCELL5:IMUX.IMUX26.DELAY | GTX0.TXCHARISK0 |
| TCELL5:IMUX.IMUX27.DELAY | GTX0.TXBYPASS8B10B1 |
| TCELL5:IMUX.IMUX28.DELAY | GTX0.TXCHARDISPMODE1 |
| TCELL5:IMUX.IMUX29.DELAY | GTX0.RXDLYALIGNRESET |
| TCELL5:IMUX.IMUX30.DELAY | GTX0.TXCHARDISPVAL1 |
| TCELL5:IMUX.IMUX32.DELAY | GTX0.TXHEADER2 |
| TCELL5:IMUX.IMUX33.DELAY | GTX0.RXDLYALIGNOVERRIDE |
| TCELL5:IMUX.IMUX34.DELAY | GTX0.TXCHARDISPMODE0 |
| TCELL5:IMUX.IMUX35.DELAY | GTX0.TXBYPASS8B10B2 |
| TCELL5:IMUX.IMUX36.DELAY | GTX0.TXCHARISK1 |
| TCELL5:IMUX.IMUX37.DELAY | GTX0.TXCHARDISPMODE2 |
| TCELL5:IMUX.IMUX38.DELAY | GTX0.TXCHARDISPVAL2 |
| TCELL5:IMUX.IMUX39.DELAY | GTX0.TXCHARISK2 |
| TCELL5:IMUX.IMUX44.DELAY | GTX0.TXCHARDISPVAL0 |
| TCELL5:IMUX.IMUX46.DELAY | GTX0.TXDLYALIGNDISABLE |
| TCELL5:OUT0.TMIN | GTX0.RXDLYALIGNMONITOR7 |
| TCELL5:OUT1.TMIN | GTX0.RXSTARTOFSEQ |
| TCELL5:OUT2.TMIN | GTX0.RXPRBSERR |
| TCELL5:OUT3.TMIN | GTX0.RXELECIDLE |
| TCELL5:OUT4.TMIN | GTX0.RXVALID |
| TCELL5:OUT5.TMIN | GTX0.RXRECCLKPCS |
| TCELL5:OUT6.TMIN | GTX0.RXCLKCORCNT2 |
| TCELL5:OUT7.TMIN | GTX0.RXDLYALIGNMONITOR2 |
| TCELL5:OUT8.TMIN | GTX0.RXCLKCORCNT0 |
| TCELL5:OUT9.TMIN | GTX0.RXCLKCORCNT1 |
| TCELL5:OUT10.TMIN | GTX0.RXHEADER0 |
| TCELL5:OUT11.TMIN | GTX0.RXHEADERVALID |
| TCELL5:OUT12.TMIN | GTX0.RXCOMMADET |
| TCELL5:OUT14.TMIN | GTX0.RXCHANBONDSEQ |
| TCELL5:OUT15.TMIN | GTX0.RXDLYALIGNMONITOR1 |
| TCELL5:OUT16.TMIN | GTX0.RXHEADER1 |
| TCELL5:OUT17.TMIN | GTX0.RXHEADER2 |
| TCELL5:OUT18.TMIN | GTX0.RXDLYALIGNMONITOR6 |
| TCELL5:OUT19.TMIN | GTX0.RXDLYALIGNMONITOR5 |
| TCELL5:OUT20.TMIN | GTX0.RXDLYALIGNMONITOR3 |
| TCELL5:OUT21.TMIN | GTX0.RXDLYALIGNMONITOR0 |
| TCELL5:OUT22.TMIN | GTX0.RXRESETDONE |
| TCELL5:OUT23.TMIN | GTX0.RXDLYALIGNMONITOR4 |
| TCELL6:IMUX.CLK0 | GTX0.TXUSRCLK |
| TCELL6:IMUX.CLK1 | GTX0.TXUSRCLK2 |
| TCELL6:IMUX.CTRL0 | GTX0.TXRESET |
| TCELL6:IMUX.CTRL1 | GTX0.GTXTXRESET |
| TCELL6:IMUX.IMUX3.DELAY | GTX0.TXDATA12 |
| TCELL6:IMUX.IMUX5.DELAY | GTX0.TXDATA14 |
| TCELL6:IMUX.IMUX8.DELAY | GTX0.TXSEQUENCE3 |
| TCELL6:IMUX.IMUX9.DELAY | GTX0.DFETAP31 |
| TCELL6:IMUX.IMUX10.DELAY | GTX0.DFETAP30 |
| TCELL6:IMUX.IMUX11.DELAY | GTX0.TXSEQUENCE0 |
| TCELL6:IMUX.IMUX12.DELAY | GTX0.DFETAP32 |
| TCELL6:IMUX.IMUX13.DELAY | GTX0.TXDATA15 |
| TCELL6:IMUX.IMUX15.DELAY | GTX0.TXENPRBSTST2 |
| TCELL6:IMUX.IMUX17.DELAY | GTX0.DFETAP33 |
| TCELL6:IMUX.IMUX19.DELAY | GTX0.TXSEQUENCE1 |
| TCELL6:IMUX.IMUX20.DELAY | GTX0.DFETAP43 |
| TCELL6:IMUX.IMUX22.DELAY | GTX0.TXSEQUENCE5 |
| TCELL6:IMUX.IMUX23.DELAY | GTX0.TXENPRBSTST1 |
| TCELL6:IMUX.IMUX24.DELAY | GTX0.TXSEQUENCE4 |
| TCELL6:IMUX.IMUX25.DELAY | GTX0.DFETAP41 |
| TCELL6:IMUX.IMUX26.DELAY | GTX0.DFETAP40 |
| TCELL6:IMUX.IMUX28.DELAY | GTX0.DFETAP42 |
| TCELL6:IMUX.IMUX30.DELAY | GTX0.TXDATA13 |
| TCELL6:IMUX.IMUX32.DELAY | GTX0.GATERXELECIDLE |
| TCELL6:IMUX.IMUX33.DELAY | GTX0.TXRATE1 |
| TCELL6:IMUX.IMUX34.DELAY | GTX0.TXRATE0 |
| TCELL6:IMUX.IMUX35.DELAY | GTX0.TXSEQUENCE2 |
| TCELL6:IMUX.IMUX37.DELAY | GTX0.IGNORESIGDET |
| TCELL6:IMUX.IMUX38.DELAY | GTX0.TXSEQUENCE6 |
| TCELL6:IMUX.IMUX39.DELAY | GTX0.TXENPRBSTST0 |
| TCELL6:IMUX.IMUX41.DELAY | GTX0.RXRATE1 |
| TCELL6:IMUX.IMUX42.DELAY | GTX0.RXRATE0 |
| TCELL6:OUT1.TMIN | GTX0.DFECLKDLYADJMON1 |
| TCELL6:OUT2.TMIN | GTX0.DFECLKDLYADJMON2 |
| TCELL6:OUT3.TMIN | GTX0.DFECLKDLYADJMON5 |
| TCELL6:OUT4.TMIN | GTX0.TXGEARBOXREADY |
| TCELL6:OUT5.TMIN | GTX0.DFECLKDLYADJMON0 |
| TCELL6:OUT6.TMIN | GTX0.DFECLKDLYADJMON3 |
| TCELL6:OUT7.TMIN | GTX0.DFECLKDLYADJMON4 |
| TCELL6:OUT8.TMIN | GTX0.TXOUTCLKPCS |
| TCELL6:OUT10.TMIN | GTX0.DFEEYEDACMON2 |
| TCELL6:OUT11.TMIN | GTX0.DFEEYEDACMON3 |
| TCELL6:OUT13.TMIN | GTX0.DFEEYEDACMON0 |
| TCELL6:OUT14.TMIN | GTX0.DFEEYEDACMON1 |
| TCELL6:OUT15.TMIN | GTX0.DFEEYEDACMON4 |
| TCELL6:OUT18.TMIN | GTX0.DFESENSCAL1 |
| TCELL6:OUT19.TMIN | GTX0.DFESENSCAL0 |
| TCELL6:OUT20.TMIN | GTX0.RXRATEDONE |
| TCELL6:OUT22.TMIN | GTX0.DFESENSCAL2 |
| TCELL6:OUT23.TMIN | GTX0.TXRATEDONE |
| TCELL7:IMUX.CLK0 | GTX0.GREFCLKTX |
| TCELL7:IMUX.IMUX9.DELAY | GTX0.TXDLYALIGNFORCEROTATEB |
| TCELL7:IMUX.IMUX10.DELAY | GTX0.TXCOMWAKE |
| TCELL7:IMUX.IMUX11.DELAY | GTX0.TXDLYALIGNMONENB |
| TCELL7:IMUX.IMUX12.DELAY | GTX0.TXPLLLKDETEN |
| TCELL7:IMUX.IMUX13.DELAY | GTX0.TXDATA10 |
| TCELL7:IMUX.IMUX14.DELAY | GTX0.TXSTARTSEQ |
| TCELL7:IMUX.IMUX15.DELAY | GTX0.TXDATA8 |
| TCELL7:IMUX.IMUX18.DELAY | GTX0.TXCOMINIT |
| TCELL7:IMUX.IMUX19.DELAY | GTX0.TXCOMSAS |
| TCELL7:IMUX.IMUX21.DELAY | GTX0.TXDATA9 |
| TCELL7:IMUX.IMUX22.DELAY | GTX0.TXENC8B10BUSE |
| TCELL7:IMUX.IMUX24.DELAY | GTX0.TXDATA23 |
| TCELL7:IMUX.IMUX25.DELAY | GTX0.TXDATA22 |
| TCELL7:IMUX.IMUX26.DELAY | GTX0.TXDATA7 |
| TCELL7:IMUX.IMUX27.DELAY | GTX0.TXDATA20 |
| TCELL7:IMUX.IMUX28.DELAY | GTX0.TXDATA21 |
| TCELL7:IMUX.IMUX29.DELAY | GTX0.TXPLLPOWERDOWN |
| TCELL7:IMUX.IMUX30.DELAY | GTX0.TXDLYALIGNTESTMODEENB |
| TCELL7:IMUX.IMUX32.DELAY | GTX0.TXDATA31 |
| TCELL7:IMUX.IMUX33.DELAY | GTX0.TXDATA30 |
| TCELL7:IMUX.IMUX34.DELAY | GTX0.TXDATA6 |
| TCELL7:IMUX.IMUX35.DELAY | GTX0.TXDATA28 |
| TCELL7:IMUX.IMUX36.DELAY | GTX0.TXDATA29 |
| TCELL7:IMUX.IMUX37.DELAY | GTX0.TXPLLREFSELDY0 |
| TCELL7:IMUX.IMUX38.DELAY | GTX0.TXPLLREFSELDY1 |
| TCELL7:IMUX.IMUX39.DELAY | GTX0.TXPLLREFSELDY2 |
| TCELL7:IMUX.IMUX40.DELAY | GTX0.TXDATA11 |
| TCELL7:OUT0.TMIN | GTX0.TXDLYALIGNMONITOR7 |
| TCELL7:OUT1.TMIN | GTX0.DFETAP2MONITOR0 |
| TCELL7:OUT2.TMIN | GTX0.DFETAP2MONITOR1 |
| TCELL7:OUT3.TMIN | GTX0.DFETAP2MONITOR4 |
| TCELL7:OUT4.TMIN | GTX0.TXDLYALIGNMONITOR2 |
| TCELL7:OUT5.TMIN | GTX0.TXBUFSTATUS0 |
| TCELL7:OUT6.TMIN | GTX0.DFETAP2MONITOR2 |
| TCELL7:OUT7.TMIN | GTX0.DFETAP2MONITOR3 |
| TCELL7:OUT8.TMIN | GTX0.DFETAP4MONITOR1 |
| TCELL7:OUT9.TMIN | GTX0.DFETAP4MONITOR2 |
| TCELL7:OUT10.TMIN | GTX0.TXKERR1 |
| TCELL7:OUT11.TMIN | GTX0.TXKERR2 |
| TCELL7:OUT12.TMIN | GTX0.DFETAP4MONITOR0 |
| TCELL7:OUT13.TMIN | GTX0.DFETAP4MONITOR3 |
| TCELL7:OUT14.TMIN | GTX0.TXKERR0 |
| TCELL7:OUT15.TMIN | GTX0.TXKERR3 |
| TCELL7:OUT16.TMIN | GTX0.TXDLYALIGNMONITOR1 |
| TCELL7:OUT17.TMIN | GTX0.TXBUFSTATUS1 |
| TCELL7:OUT18.TMIN | GTX0.TXDLYALIGNMONITOR6 |
| TCELL7:OUT19.TMIN | GTX0.TXDLYALIGNMONITOR5 |
| TCELL7:OUT20.TMIN | GTX0.TXDLYALIGNMONITOR3 |
| TCELL7:OUT21.TMIN | GTX0.TXDLYALIGNMONITOR0 |
| TCELL7:OUT22.TMIN | GTX0.TXRESETDONE |
| TCELL7:OUT23.TMIN | GTX0.TXDLYALIGNMONITOR4 |
| TCELL8:IMUX.IMUX8.DELAY | GTX0.DWE |
| TCELL8:IMUX.IMUX9.DELAY | GTX0.SCANIN4 |
| TCELL8:IMUX.IMUX10.DELAY | GTX0.TXPOSTEMPHASIS0 |
| TCELL8:IMUX.IMUX12.DELAY | GTX0.TXPOSTEMPHASIS2 |
| TCELL8:IMUX.IMUX13.DELAY | GTX0.TXPRBSFORCEERR |
| TCELL8:IMUX.IMUX15.DELAY | GTX0.TXPDOWNASYNCH |
| TCELL8:IMUX.IMUX16.DELAY | GTX0.DEN |
| TCELL8:IMUX.IMUX17.DELAY | GTX0.TXENPMAPHASEALIGN |
| TCELL8:IMUX.IMUX18.DELAY | GTX0.TXPOSTEMPHASIS1 |
| TCELL8:IMUX.IMUX19.DELAY | GTX0.TXDATA25 |
| TCELL8:IMUX.IMUX20.DELAY | GTX0.TXPOSTEMPHASIS3 |
| TCELL8:IMUX.IMUX22.DELAY | GTX0.TXPOSTEMPHASIS4 |
| TCELL8:IMUX.IMUX25.DELAY | GTX0.SCANIN1 |
| TCELL8:IMUX.IMUX26.DELAY | GTX0.TXDATA4 |
| TCELL8:IMUX.IMUX27.DELAY | GTX0.TXDATA19 |
| TCELL8:IMUX.IMUX28.DELAY | GTX0.TXDATA2 |
| TCELL8:IMUX.IMUX29.DELAY | GTX0.TXDATA18 |
| TCELL8:IMUX.IMUX30.DELAY | GTX0.TXDATA17 |
| TCELL8:IMUX.IMUX31.DELAY | GTX0.TXDATA16 |
| TCELL8:IMUX.IMUX32.DELAY | GTX0.TXDATA3 |
| TCELL8:IMUX.IMUX33.DELAY | GTX0.SCANIN0 |
| TCELL8:IMUX.IMUX34.DELAY | GTX0.TXDATA5 |
| TCELL8:IMUX.IMUX35.DELAY | GTX0.TXDATA27 |
| TCELL8:IMUX.IMUX36.DELAY | GTX0.TXDATA1 |
| TCELL8:IMUX.IMUX37.DELAY | GTX0.TXDATA26 |
| TCELL8:IMUX.IMUX38.DELAY | GTX0.TXDATA0 |
| TCELL8:IMUX.IMUX39.DELAY | GTX0.TXDATA24 |
| TCELL8:OUT0.TMIN | GTX0.DRDY |
| TCELL8:OUT1.TMIN | GTX0.DFETAP1MONITOR0 |
| TCELL8:OUT2.TMIN | GTX0.DFETAP1MONITOR1 |
| TCELL8:OUT3.TMIN | GTX0.DFETAP1MONITOR4 |
| TCELL8:OUT5.TMIN | GTX0.TXPLLLKDET |
| TCELL8:OUT6.TMIN | GTX0.DFETAP1MONITOR2 |
| TCELL8:OUT7.TMIN | GTX0.DFETAP1MONITOR3 |
| TCELL8:OUT8.TMIN | GTX0.DFETAP3MONITOR1 |
| TCELL8:OUT9.TMIN | GTX0.DFETAP3MONITOR2 |
| TCELL8:OUT10.TMIN | GTX0.TXRUNDISP1 |
| TCELL8:OUT11.TMIN | GTX0.TXRUNDISP2 |
| TCELL8:OUT12.TMIN | GTX0.DFETAP3MONITOR0 |
| TCELL8:OUT13.TMIN | GTX0.DFETAP3MONITOR3 |
| TCELL8:OUT14.TMIN | GTX0.TXRUNDISP0 |
| TCELL8:OUT15.TMIN | GTX0.TXRUNDISP3 |
| TCELL8:OUT18.TMIN | GTX0.COMFINISH |
| TCELL9:IMUX.CLK0 | GTX0.DCLK |
| TCELL9:IMUX.IMUX8.DELAY | GTX0.DI0 |
| TCELL9:IMUX.IMUX9.DELAY | GTX0.DI1 |
| TCELL9:IMUX.IMUX10.DELAY | GTX0.DI2 |
| TCELL9:IMUX.IMUX11.DELAY | GTX0.DI3 |
| TCELL9:IMUX.IMUX12.DELAY | GTX0.DI4 |
| TCELL9:IMUX.IMUX13.DELAY | GTX0.DI5 |
| TCELL9:IMUX.IMUX14.DELAY | GTX0.DI6 |
| TCELL9:IMUX.IMUX15.DELAY | GTX0.DI7 |
| TCELL9:IMUX.IMUX16.DELAY | GTX0.DI8 |
| TCELL9:IMUX.IMUX17.DELAY | GTX0.DI9 |
| TCELL9:IMUX.IMUX18.DELAY | GTX0.DI10 |
| TCELL9:IMUX.IMUX19.DELAY | GTX0.DI11 |
| TCELL9:IMUX.IMUX20.DELAY | GTX0.DI12 |
| TCELL9:IMUX.IMUX21.DELAY | GTX0.DI13 |
| TCELL9:IMUX.IMUX22.DELAY | GTX0.DI14 |
| TCELL9:IMUX.IMUX23.DELAY | GTX0.DI15 |
| TCELL9:IMUX.IMUX32.DELAY | GTX0.DADDR0 |
| TCELL9:IMUX.IMUX33.DELAY | GTX0.DADDR1 |
| TCELL9:IMUX.IMUX34.DELAY | GTX0.DADDR2 |
| TCELL9:IMUX.IMUX35.DELAY | GTX0.DADDR3 |
| TCELL9:IMUX.IMUX36.DELAY | GTX0.DADDR4 |
| TCELL9:IMUX.IMUX37.DELAY | GTX0.DADDR5 |
| TCELL9:IMUX.IMUX38.DELAY | GTX0.DADDR6 |
| TCELL9:IMUX.IMUX39.DELAY | GTX0.DADDR7 |
| TCELL9:OUT0.TMIN | GTX0.DRPDO7 |
| TCELL9:OUT1.TMIN | GTX0.DRPDO4 |
| TCELL9:OUT2.TMIN | GTX0.DRPDO3 |
| TCELL9:OUT3.TMIN | GTX0.DRPDO0 |
| TCELL9:OUT4.TMIN | GTX0.DRPDO6 |
| TCELL9:OUT5.TMIN | GTX0.DRPDO5 |
| TCELL9:OUT6.TMIN | GTX0.DRPDO2 |
| TCELL9:OUT7.TMIN | GTX0.DRPDO1 |
| TCELL9:OUT8.TMIN | GTX0.DRPDO14 |
| TCELL9:OUT9.TMIN | GTX0.DRPDO13 |
| TCELL9:OUT10.TMIN | GTX0.DRPDO10 |
| TCELL9:OUT11.TMIN | GTX0.DRPDO9 |
| TCELL9:OUT12.TMIN | GTX0.DRPDO15 |
| TCELL9:OUT13.TMIN | GTX0.DRPDO12 |
| TCELL9:OUT14.TMIN | GTX0.DRPDO11 |
| TCELL9:OUT15.TMIN | GTX0.DRPDO8 |
| TCELL10:IMUX.CTRL1 | GTX1.PRBSCNTRESET |
| TCELL10:IMUX.IMUX0.DELAY | GTX1.TSTIN17 |
| TCELL10:IMUX.IMUX1.DELAY | GTX1.TSTIN18 |
| TCELL10:IMUX.IMUX8.DELAY | GTX1.TSTIN9 |
| TCELL10:IMUX.IMUX9.DELAY | GTX1.TSTIN7 |
| TCELL10:IMUX.IMUX10.DELAY | GTX1.TSTIN5 |
| TCELL10:IMUX.IMUX11.DELAY | GTX1.TSTIN3 |
| TCELL10:IMUX.IMUX13.DELAY | GTX1.TSTIN12 |
| TCELL10:IMUX.IMUX14.DELAY | GTX1.TSTIN1 |
| TCELL10:IMUX.IMUX16.DELAY | GTX1.TSTIN15 |
| TCELL10:IMUX.IMUX17.DELAY | GTX1.TSTPWRDNOVRD |
| TCELL10:IMUX.IMUX18.DELAY | GTX1.TSTPWRDN1 |
| TCELL10:IMUX.IMUX19.DELAY | GTX1.TSTPWRDN3 |
| TCELL10:IMUX.IMUX21.DELAY | GTX1.TSTIN11 |
| TCELL10:IMUX.IMUX22.DELAY | GTX1.SCANIN3 |
| TCELL10:IMUX.IMUX24.DELAY | GTX1.TSTIN8 |
| TCELL10:IMUX.IMUX25.DELAY | GTX1.TSTIN6 |
| TCELL10:IMUX.IMUX26.DELAY | GTX1.TSTIN4 |
| TCELL10:IMUX.IMUX27.DELAY | GTX1.TSTIN2 |
| TCELL10:IMUX.IMUX28.DELAY | GTX1.TSTIN13 |
| TCELL10:IMUX.IMUX29.DELAY | GTX1.SCANMODEB |
| TCELL10:IMUX.IMUX30.DELAY | GTX1.TSTIN0 |
| TCELL10:IMUX.IMUX31.DELAY | GTX1.TSTIN10 |
| TCELL10:IMUX.IMUX32.DELAY | GTX1.TSTIN14 |
| TCELL10:IMUX.IMUX33.DELAY | GTX1.TSTPWRDN0 |
| TCELL10:IMUX.IMUX34.DELAY | GTX1.TSTPWRDN2 |
| TCELL10:IMUX.IMUX35.DELAY | GTX1.TSTPWRDN4 |
| TCELL10:IMUX.IMUX37.DELAY | GTX1.SCANENB |
| TCELL10:IMUX.IMUX38.DELAY | GTX1.SCANIN2 |
| TCELL10:IMUX.IMUX40.DELAY | GTX1.TSTIN16 |
| TCELL10:IMUX.IMUX41.DELAY | GTX1.TSTIN19 |
| TCELL10:OUT0.TMIN | GTX1.RXDATA18 |
| TCELL10:OUT1.TMIN | GTX1.RXDATA4 |
| TCELL10:OUT2.TMIN | GTX1.RXDATA3 |
| TCELL10:OUT3.TMIN | GTX1.RXDATA17 |
| TCELL10:OUT4.TMIN | GTX1.RXDATA0 |
| TCELL10:OUT5.TMIN | GTX1.RXDATA5 |
| TCELL10:OUT6.TMIN | GTX1.RXDATA2 |
| TCELL10:OUT7.TMIN | GTX1.RXDATA1 |
| TCELL10:OUT8.TMIN | GTX1.SCANOUT4 |
| TCELL10:OUT13.TMIN | GTX1.SCANOUT3 |
| TCELL10:OUT15.TMIN | GTX1.RXDATA16 |
| TCELL10:OUT16.TMIN | GTX1.RXDATA22 |
| TCELL10:OUT17.TMIN | GTX1.RXDATA21 |
| TCELL10:OUT18.TMIN | GTX1.RXDATA20 |
| TCELL10:OUT20.TMIN | GTX1.RXDATA23 |
| TCELL10:OUT22.TMIN | GTX1.RXDATA19 |
| TCELL10:OUT23.TMIN | GTX1.SCANOUT2 |
| TCELL11:IMUX.CTRL0 | GTX1.GTXRXRESET |
| TCELL11:IMUX.CTRL1 | GTX1.RXCDRRESET |
| TCELL11:IMUX.IMUX9.DELAY | GTX1.RXSLIDE |
| TCELL11:IMUX.IMUX11.DELAY | GTX1.RXPMASETPHASE |
| TCELL11:IMUX.IMUX12.DELAY | GTX1.RXGEARBOXSLIP |
| TCELL11:IMUX.IMUX14.DELAY | GTX1.RXEQMIX0 |
| TCELL11:IMUX.IMUX15.DELAY | GTX1.RXEQMIX1 |
| TCELL11:IMUX.IMUX18.DELAY | GTX1.RXENPRBSTST2 |
| TCELL11:IMUX.IMUX19.DELAY | GTX1.RXEQMIX9 |
| TCELL11:IMUX.IMUX20.DELAY | GTX1.RXEQMIX7 |
| TCELL11:IMUX.IMUX21.DELAY | GTX1.RXEQMIX5 |
| TCELL11:IMUX.IMUX22.DELAY | GTX1.RXEQMIX3 |
| TCELL11:IMUX.IMUX24.DELAY | GTX1.RXBUFWE |
| TCELL11:IMUX.IMUX26.DELAY | GTX1.RXPOLARITY |
| TCELL11:IMUX.IMUX27.DELAY | GTX1.RXEQMIX8 |
| TCELL11:IMUX.IMUX28.DELAY | GTX1.RXEQMIX6 |
| TCELL11:IMUX.IMUX29.DELAY | GTX1.RXEQMIX4 |
| TCELL11:IMUX.IMUX30.DELAY | GTX1.RXEQMIX2 |
| TCELL11:IMUX.IMUX32.DELAY | GTX1.RXENSAMPLEALIGN |
| TCELL11:IMUX.IMUX33.DELAY | GTX1.RXENPRBSTST0 |
| TCELL11:IMUX.IMUX34.DELAY | GTX1.RXENPRBSTST1 |
| TCELL11:IMUX.IMUX35.DELAY | GTX1.RXENPMAPHASEALIGN |
| TCELL11:IMUX.IMUX36.DELAY | GTX1.RXENMCOMMAALIGN |
| TCELL11:IMUX.IMUX37.DELAY | GTX1.RXENPCOMMAALIGN |
| TCELL11:IMUX.IMUX38.DELAY | GTX1.RXENCHANSYNC |
| TCELL11:IMUX.IMUX39.DELAY | GTX1.RXDEC8B10BUSE |
| TCELL11:OUT0.TMIN | GTX1.RXDATA24 |
| TCELL11:OUT1.TMIN | GTX1.RXDATA6 |
| TCELL11:OUT2.TMIN | GTX1.RXDATA11 |
| TCELL11:OUT3.TMIN | GTX1.RXDATA31 |
| TCELL11:OUT4.TMIN | GTX1.RXDATA8 |
| TCELL11:OUT5.TMIN | GTX1.RXDATA7 |
| TCELL11:OUT6.TMIN | GTX1.RXDATA10 |
| TCELL11:OUT7.TMIN | GTX1.RXDATA9 |
| TCELL11:OUT8.TMIN | GTX1.TSTOUT8 |
| TCELL11:OUT9.TMIN | GTX1.RXDATA27 |
| TCELL11:OUT10.TMIN | GTX1.TSTOUT2 |
| TCELL11:OUT11.TMIN | GTX1.RXDATA29 |
| TCELL11:OUT12.TMIN | GTX1.TSTOUT9 |
| TCELL11:OUT13.TMIN | GTX1.TSTOUT6 |
| TCELL11:OUT14.TMIN | GTX1.TSTOUT4 |
| TCELL11:OUT15.TMIN | GTX1.RXDATA30 |
| TCELL11:OUT16.TMIN | GTX1.RXDATA28 |
| TCELL11:OUT17.TMIN | GTX1.TSTOUT1 |
| TCELL11:OUT18.TMIN | GTX1.RXDATA26 |
| TCELL11:OUT19.TMIN | GTX1.TSTOUT7 |
| TCELL11:OUT20.TMIN | GTX1.TSTOUT3 |
| TCELL11:OUT21.TMIN | GTX1.TSTOUT0 |
| TCELL11:OUT22.TMIN | GTX1.RXDATA25 |
| TCELL11:OUT23.TMIN | GTX1.TSTOUT5 |
| TCELL12:IMUX.CLK0 | GTX1.RXUSRCLK |
| TCELL12:IMUX.CLK1 | GTX1.RXUSRCLK2 |
| TCELL12:IMUX.CTRL0 | GTX1.RXBUFRESET |
| TCELL12:IMUX.CTRL1 | GTX1.RXRESET |
| TCELL12:IMUX.IMUX8.DELAY | GTX1.RXCHBONDSLAVE |
| TCELL12:IMUX.IMUX10.DELAY | GTX1.RXCHBONDLEVEL0 |
| TCELL12:IMUX.IMUX11.DELAY | GTX1.RXCHBONDLEVEL2 |
| TCELL12:IMUX.IMUX14.DELAY | GTX1.USRCODEERR |
| TCELL12:IMUX.IMUX16.DELAY | BUFDS1.CLKTESTSIG_INT |
| TCELL12:IMUX.IMUX17.DELAY | BUFDS0.CLKTESTSIG_INT |
| TCELL12:IMUX.IMUX18.DELAY | GTX1.CLKTESTSIG1 |
| TCELL12:IMUX.IMUX19.DELAY | GTX1.CLKTESTSIG0 |
| TCELL12:IMUX.IMUX20.DELAY | GTX1.RXPLLLKDETEN |
| TCELL12:IMUX.IMUX21.DELAY | GTX1.RXPLLPOWERDOWN |
| TCELL12:IMUX.IMUX24.DELAY | GTX1.RXCHBONDMASTER |
| TCELL12:IMUX.IMUX26.DELAY | GTX1.RXCHBONDLEVEL1 |
| TCELL12:IMUX.IMUX27.DELAY | GTX1.GTXTEST12 |
| TCELL12:IMUX.IMUX28.DELAY | GTX1.GTXTEST11 |
| TCELL12:IMUX.IMUX29.DELAY | GTX1.GTXTEST10 |
| TCELL12:IMUX.IMUX30.DELAY | GTX1.GTXTEST9 |
| TCELL12:IMUX.IMUX31.DELAY | GTX1.GTXTEST8 |
| TCELL12:IMUX.IMUX32.DELAY | GTX1.GTXTEST7 |
| TCELL12:IMUX.IMUX33.DELAY | GTX1.GTXTEST6 |
| TCELL12:IMUX.IMUX34.DELAY | GTX1.GTXTEST5 |
| TCELL12:IMUX.IMUX35.DELAY | GTX1.GTXTEST4 |
| TCELL12:IMUX.IMUX36.DELAY | GTX1.GTXTEST3 |
| TCELL12:IMUX.IMUX37.DELAY | GTX1.GTXTEST2 |
| TCELL12:IMUX.IMUX38.DELAY | GTX1.GTXTEST1 |
| TCELL12:IMUX.IMUX39.DELAY | GTX1.GTXTEST0 |
| TCELL12:OUT0.TMIN | GTX1.RXLOSSOFSYNC0 |
| TCELL12:OUT1.TMIN | GTX1.RXDATA15 |
| TCELL12:OUT2.TMIN | GTX1.RXDATA14 |
| TCELL12:OUT3.TMIN | GTX1.RXCHARISK3 |
| TCELL12:OUT4.TMIN | GTX1.RXDATAVALID |
| TCELL12:OUT5.TMIN | GTX1.RXCHARISK1 |
| TCELL12:OUT6.TMIN | GTX1.RXDATA13 |
| TCELL12:OUT7.TMIN | GTX1.RXDATA12 |
| TCELL12:OUT8.TMIN | GTX1.RXCHARISCOMMA2 |
| TCELL12:OUT10.TMIN | GTX1.RXBYTEREALIGN |
| TCELL12:OUT13.TMIN | GTX1.RXBYTEISALIGNED |
| TCELL12:OUT14.TMIN | GTX1.RXCHANREALIGN |
| TCELL12:OUT15.TMIN | GTX1.RXCHARISK2 |
| TCELL12:OUT18.TMIN | GTX1.RXCHARISCOMMA3 |
| TCELL12:OUT19.TMIN | GTX1.COMSASDET |
| TCELL12:OUT20.TMIN | GTX1.COMINITDET |
| TCELL12:OUT22.TMIN | GTX1.RXLOSSOFSYNC1 |
| TCELL12:OUT23.TMIN | GTX1.COMWAKEDET |
| TCELL13:IMUX.CLK0 | GTX1.GREFCLKRX |
| TCELL13:IMUX.CLK1 | GTX1.TSTCLK0 |
| TCELL13:IMUX.CTRL0 | GTX1.PLLRXRESET |
| TCELL13:IMUX.IMUX0.DELAY | GTX1.TXBUFDIFFCTRL0 |
| TCELL13:IMUX.IMUX3.DELAY | GTX1.TXDEEMPH |
| TCELL13:IMUX.IMUX5.DELAY | GTX1.TXDIFFCTRL2 |
| TCELL13:IMUX.IMUX9.DELAY | GTX1.TXPREEMPHASIS3 |
| TCELL13:IMUX.IMUX11.DELAY | GTX1.LOOPBACK1 |
| TCELL13:IMUX.IMUX12.DELAY | GTX1.RXDLYALIGNTESTMODEENB |
| TCELL13:IMUX.IMUX13.DELAY | GTX1.TXSWING |
| TCELL13:IMUX.IMUX16.DELAY | GTX1.TXBUFDIFFCTRL1 |
| TCELL13:IMUX.IMUX17.DELAY | GTX1.TXPREEMPHASIS2 |
| TCELL13:IMUX.IMUX18.DELAY | GTX1.TXBUFDIFFCTRL2 |
| TCELL13:IMUX.IMUX19.DELAY | GTX1.TXPREEMPHASIS1 |
| TCELL13:IMUX.IMUX21.DELAY | GTX1.TXDIFFCTRL0 |
| TCELL13:IMUX.IMUX22.DELAY | GTX1.RXPLLREFSELDY1 |
| TCELL13:IMUX.IMUX24.DELAY | GTX1.LOOPBACK0 |
| TCELL13:IMUX.IMUX25.DELAY | GTX1.RXDLYALIGNFORCEROTATEB |
| TCELL13:IMUX.IMUX26.DELAY | GTX1.TXPREEMPHASIS0 |
| TCELL13:IMUX.IMUX27.DELAY | GTX1.LOOPBACK2 |
| TCELL13:IMUX.IMUX28.DELAY | GTX1.RXDLYALIGNMONENB |
| TCELL13:IMUX.IMUX29.DELAY | GTX1.RXDLYALIGNSWPPRECURB |
| TCELL13:IMUX.IMUX30.DELAY | GTX1.TXDIFFCTRL3 |
| TCELL13:IMUX.IMUX32.DELAY | GTX1.RXCHBONDI0 |
| TCELL13:IMUX.IMUX33.DELAY | GTX1.RXCHBONDI1 |
| TCELL13:IMUX.IMUX34.DELAY | GTX1.RXCHBONDI2 |
| TCELL13:IMUX.IMUX35.DELAY | GTX1.RXCHBONDI3 |
| TCELL13:IMUX.IMUX36.DELAY | GTX1.RXCOMMADETUSE |
| TCELL13:IMUX.IMUX37.DELAY | GTX1.RXPLLREFSELDY0 |
| TCELL13:IMUX.IMUX38.DELAY | GTX1.TXDIFFCTRL1 |
| TCELL13:IMUX.IMUX39.DELAY | GTX1.RXPLLREFSELDY2 |
| TCELL13:OUT0.TMIN | GTX1.RXDISPERR2 |
| TCELL13:OUT1.TMIN | GTX1.RXRUNDISP3 |
| TCELL13:OUT2.TMIN | GTX1.RXCHARISCOMMA1 |
| TCELL13:OUT3.TMIN | GTX1.RXNOTINTABLE3 |
| TCELL13:OUT4.TMIN | GTX1.RXDISPERR0 |
| TCELL13:OUT5.TMIN | GTX1.RXRUNDISP1 |
| TCELL13:OUT7.TMIN | GTX1.RXNOTINTABLE1 |
| TCELL13:OUT8.TMIN | GTX1.RXDISPERR1 |
| TCELL13:OUT9.TMIN | GTX1.RXRUNDISP0 |
| TCELL13:OUT11.TMIN | GTX1.RXNOTINTABLE0 |
| TCELL13:OUT13.TMIN | GTX1.RXCHANISALIGNED |
| TCELL13:OUT14.TMIN | GTX1.RXCHARISCOMMA0 |
| TCELL13:OUT15.TMIN | GTX1.RXNOTINTABLE2 |
| TCELL13:OUT16.TMIN | GTX1.RXCHARISK0 |
| TCELL13:OUT19.TMIN | GTX1.RXRUNDISP2 |
| TCELL13:OUT22.TMIN | GTX1.RXDISPERR3 |
| TCELL14:IMUX.CLK1 | GTX1.SCANCLK |
| TCELL14:IMUX.IMUX8.DELAY | GTX1.DFETAP10 |
| TCELL14:IMUX.IMUX9.DELAY | GTX1.TXDETECTRX |
| TCELL14:IMUX.IMUX10.DELAY | GTX1.DFETAP11 |
| TCELL14:IMUX.IMUX11.DELAY | GTX1.TXMARGIN0 |
| TCELL14:IMUX.IMUX13.DELAY | GTX1.RXPOWERDOWN0 |
| TCELL14:IMUX.IMUX14.DELAY | GTX1.DFETAP12 |
| TCELL14:IMUX.IMUX15.DELAY | GTX1.DFETAP13 |
| TCELL14:IMUX.IMUX16.DELAY | GTX1.DFECLKDLYADJ5 |
| TCELL14:IMUX.IMUX17.DELAY | GTX1.DFECLKDLYADJ4 |
| TCELL14:IMUX.IMUX18.DELAY | GTX1.DFECLKDLYADJ2 |
| TCELL14:IMUX.IMUX19.DELAY | GTX1.DFECLKDLYADJ1 |
| TCELL14:IMUX.IMUX21.DELAY | GTX1.RXPOWERDOWN1 |
| TCELL14:IMUX.IMUX24.DELAY | GTX1.DFETAP20 |
| TCELL14:IMUX.IMUX25.DELAY | GTX1.DFETAP21 |
| TCELL14:IMUX.IMUX26.DELAY | GTX1.TXMARGIN1 |
| TCELL14:IMUX.IMUX28.DELAY | GTX1.TXPOWERDOWN0 |
| TCELL14:IMUX.IMUX29.DELAY | GTX1.DFEDLYOVRD |
| TCELL14:IMUX.IMUX30.DELAY | GTX1.DFETAP22 |
| TCELL14:IMUX.IMUX31.DELAY | GTX1.DFETAP23 |
| TCELL14:IMUX.IMUX32.DELAY | GTX1.TXELECIDLE |
| TCELL14:IMUX.IMUX33.DELAY | GTX1.DFECLKDLYADJ3 |
| TCELL14:IMUX.IMUX35.DELAY | GTX1.DFECLKDLYADJ0 |
| TCELL14:IMUX.IMUX36.DELAY | GTX1.TXPOWERDOWN1 |
| TCELL14:IMUX.IMUX37.DELAY | GTX1.DFETAPOVRD |
| TCELL14:IMUX.IMUX38.DELAY | GTX1.DFETAP14 |
| TCELL14:IMUX.IMUX39.DELAY | GTX1.DFETAP24 |
| TCELL14:OUT0.TMIN | GTX1.MGTREFCLKFAB0 |
| TCELL14:OUT3.TMIN | GTX1.RXBUFSTATUS2 |
| TCELL14:OUT4.TMIN | GTX1.SCANOUT1 |
| TCELL14:OUT5.TMIN | GTX1.RXPLLLKDET |
| TCELL14:OUT6.TMIN | GTX1.RXBUFSTATUS0 |
| TCELL14:OUT7.TMIN | GTX1.RXBUFSTATUS1 |
| TCELL14:OUT8.TMIN | GTX1.PHYSTATUS |
| TCELL14:OUT10.TMIN | GTX1.RXCHBONDO1 |
| TCELL14:OUT11.TMIN | GTX1.RXCHBONDO2 |
| TCELL14:OUT12.TMIN | GTX1.MGTREFCLKFAB1 |
| TCELL14:OUT13.TMIN | GTX1.RXSTATUS2 |
| TCELL14:OUT14.TMIN | GTX1.RXSTATUS0 |
| TCELL14:OUT15.TMIN | GTX1.RXCHBONDO3 |
| TCELL14:OUT16.TMIN | GTX1.RXSTATUS1 |
| TCELL14:OUT17.TMIN | GTX1.RXCHBONDO0 |
| TCELL14:OUT18.TMIN | GTX1.SCANOUT0 |
| TCELL14:OUT22.TMIN | GTX1.RXOVERSAMPLEERR |
| TCELL15:IMUX.CLK1 | GTX1.TSTCLK1 |
| TCELL15:IMUX.CTRL1 | GTX1.PLLTXRESET |
| TCELL15:IMUX.IMUX2.DELAY | GTX1.TXDLYALIGNUPDSW |
| TCELL15:IMUX.IMUX8.DELAY | GTX1.TXHEADER0 |
| TCELL15:IMUX.IMUX9.DELAY | GTX1.TXPOLARITY |
| TCELL15:IMUX.IMUX10.DELAY | GTX1.RXDLYALIGNUPDSW |
| TCELL15:IMUX.IMUX11.DELAY | GTX1.TXBYPASS8B10B0 |
| TCELL15:IMUX.IMUX13.DELAY | GTX1.TXDLYALIGNRESET |
| TCELL15:IMUX.IMUX14.DELAY | GTX1.RXDLYALIGNDISABLE |
| TCELL15:IMUX.IMUX15.DELAY | GTX1.TXMARGIN2 |
| TCELL15:IMUX.IMUX16.DELAY | GTX1.TXHEADER1 |
| TCELL15:IMUX.IMUX17.DELAY | GTX1.TXINHIBIT |
| TCELL15:IMUX.IMUX18.DELAY | GTX1.TXPMASETPHASE |
| TCELL15:IMUX.IMUX19.DELAY | GTX1.TXBYPASS8B10B3 |
| TCELL15:IMUX.IMUX21.DELAY | GTX1.TXCHARDISPMODE3 |
| TCELL15:IMUX.IMUX22.DELAY | GTX1.TXCHARDISPVAL3 |
| TCELL15:IMUX.IMUX23.DELAY | GTX1.TXCHARISK3 |
| TCELL15:IMUX.IMUX25.DELAY | GTX1.TXDLYALIGNOVERRIDE |
| TCELL15:IMUX.IMUX26.DELAY | GTX1.TXCHARISK0 |
| TCELL15:IMUX.IMUX27.DELAY | GTX1.TXBYPASS8B10B1 |
| TCELL15:IMUX.IMUX28.DELAY | GTX1.TXCHARDISPMODE1 |
| TCELL15:IMUX.IMUX29.DELAY | GTX1.RXDLYALIGNRESET |
| TCELL15:IMUX.IMUX30.DELAY | GTX1.TXCHARDISPVAL1 |
| TCELL15:IMUX.IMUX32.DELAY | GTX1.TXHEADER2 |
| TCELL15:IMUX.IMUX33.DELAY | GTX1.RXDLYALIGNOVERRIDE |
| TCELL15:IMUX.IMUX34.DELAY | GTX1.TXCHARDISPMODE0 |
| TCELL15:IMUX.IMUX35.DELAY | GTX1.TXBYPASS8B10B2 |
| TCELL15:IMUX.IMUX36.DELAY | GTX1.TXCHARISK1 |
| TCELL15:IMUX.IMUX37.DELAY | GTX1.TXCHARDISPMODE2 |
| TCELL15:IMUX.IMUX38.DELAY | GTX1.TXCHARDISPVAL2 |
| TCELL15:IMUX.IMUX39.DELAY | GTX1.TXCHARISK2 |
| TCELL15:IMUX.IMUX44.DELAY | GTX1.TXCHARDISPVAL0 |
| TCELL15:IMUX.IMUX46.DELAY | GTX1.TXDLYALIGNDISABLE |
| TCELL15:OUT0.TMIN | GTX1.RXDLYALIGNMONITOR7 |
| TCELL15:OUT1.TMIN | GTX1.RXSTARTOFSEQ |
| TCELL15:OUT2.TMIN | GTX1.RXPRBSERR |
| TCELL15:OUT3.TMIN | GTX1.RXELECIDLE |
| TCELL15:OUT4.TMIN | GTX1.RXVALID |
| TCELL15:OUT5.TMIN | GTX1.RXRECCLKPCS |
| TCELL15:OUT6.TMIN | GTX1.RXCLKCORCNT2 |
| TCELL15:OUT7.TMIN | GTX1.RXDLYALIGNMONITOR2 |
| TCELL15:OUT8.TMIN | GTX1.RXCLKCORCNT0 |
| TCELL15:OUT9.TMIN | GTX1.RXCLKCORCNT1 |
| TCELL15:OUT10.TMIN | GTX1.RXHEADER0 |
| TCELL15:OUT11.TMIN | GTX1.RXHEADERVALID |
| TCELL15:OUT12.TMIN | GTX1.RXCOMMADET |
| TCELL15:OUT14.TMIN | GTX1.RXCHANBONDSEQ |
| TCELL15:OUT15.TMIN | GTX1.RXDLYALIGNMONITOR1 |
| TCELL15:OUT16.TMIN | GTX1.RXHEADER1 |
| TCELL15:OUT17.TMIN | GTX1.RXHEADER2 |
| TCELL15:OUT18.TMIN | GTX1.RXDLYALIGNMONITOR6 |
| TCELL15:OUT19.TMIN | GTX1.RXDLYALIGNMONITOR5 |
| TCELL15:OUT20.TMIN | GTX1.RXDLYALIGNMONITOR3 |
| TCELL15:OUT21.TMIN | GTX1.RXDLYALIGNMONITOR0 |
| TCELL15:OUT22.TMIN | GTX1.RXRESETDONE |
| TCELL15:OUT23.TMIN | GTX1.RXDLYALIGNMONITOR4 |
| TCELL16:IMUX.CLK0 | GTX1.TXUSRCLK |
| TCELL16:IMUX.CLK1 | GTX1.TXUSRCLK2 |
| TCELL16:IMUX.CTRL0 | GTX1.TXRESET |
| TCELL16:IMUX.CTRL1 | GTX1.GTXTXRESET |
| TCELL16:IMUX.IMUX3.DELAY | GTX1.TXDATA12 |
| TCELL16:IMUX.IMUX5.DELAY | GTX1.TXDATA14 |
| TCELL16:IMUX.IMUX8.DELAY | GTX1.TXSEQUENCE3 |
| TCELL16:IMUX.IMUX9.DELAY | GTX1.DFETAP31 |
| TCELL16:IMUX.IMUX10.DELAY | GTX1.DFETAP30 |
| TCELL16:IMUX.IMUX11.DELAY | GTX1.TXSEQUENCE0 |
| TCELL16:IMUX.IMUX12.DELAY | GTX1.DFETAP32 |
| TCELL16:IMUX.IMUX13.DELAY | GTX1.TXDATA15 |
| TCELL16:IMUX.IMUX15.DELAY | GTX1.TXENPRBSTST2 |
| TCELL16:IMUX.IMUX17.DELAY | GTX1.DFETAP33 |
| TCELL16:IMUX.IMUX19.DELAY | GTX1.TXSEQUENCE1 |
| TCELL16:IMUX.IMUX20.DELAY | GTX1.DFETAP43 |
| TCELL16:IMUX.IMUX22.DELAY | GTX1.TXSEQUENCE5 |
| TCELL16:IMUX.IMUX23.DELAY | GTX1.TXENPRBSTST1 |
| TCELL16:IMUX.IMUX24.DELAY | GTX1.TXSEQUENCE4 |
| TCELL16:IMUX.IMUX25.DELAY | GTX1.DFETAP41 |
| TCELL16:IMUX.IMUX26.DELAY | GTX1.DFETAP40 |
| TCELL16:IMUX.IMUX28.DELAY | GTX1.DFETAP42 |
| TCELL16:IMUX.IMUX30.DELAY | GTX1.TXDATA13 |
| TCELL16:IMUX.IMUX32.DELAY | GTX1.GATERXELECIDLE |
| TCELL16:IMUX.IMUX33.DELAY | GTX1.TXRATE1 |
| TCELL16:IMUX.IMUX34.DELAY | GTX1.TXRATE0 |
| TCELL16:IMUX.IMUX35.DELAY | GTX1.TXSEQUENCE2 |
| TCELL16:IMUX.IMUX37.DELAY | GTX1.IGNORESIGDET |
| TCELL16:IMUX.IMUX38.DELAY | GTX1.TXSEQUENCE6 |
| TCELL16:IMUX.IMUX39.DELAY | GTX1.TXENPRBSTST0 |
| TCELL16:IMUX.IMUX41.DELAY | GTX1.RXRATE1 |
| TCELL16:IMUX.IMUX42.DELAY | GTX1.RXRATE0 |
| TCELL16:OUT1.TMIN | GTX1.DFECLKDLYADJMON1 |
| TCELL16:OUT2.TMIN | GTX1.DFECLKDLYADJMON2 |
| TCELL16:OUT3.TMIN | GTX1.DFECLKDLYADJMON5 |
| TCELL16:OUT4.TMIN | GTX1.TXGEARBOXREADY |
| TCELL16:OUT5.TMIN | GTX1.DFECLKDLYADJMON0 |
| TCELL16:OUT6.TMIN | GTX1.DFECLKDLYADJMON3 |
| TCELL16:OUT7.TMIN | GTX1.DFECLKDLYADJMON4 |
| TCELL16:OUT8.TMIN | GTX1.TXOUTCLKPCS |
| TCELL16:OUT10.TMIN | GTX1.DFEEYEDACMON2 |
| TCELL16:OUT11.TMIN | GTX1.DFEEYEDACMON3 |
| TCELL16:OUT13.TMIN | GTX1.DFEEYEDACMON0 |
| TCELL16:OUT14.TMIN | GTX1.DFEEYEDACMON1 |
| TCELL16:OUT15.TMIN | GTX1.DFEEYEDACMON4 |
| TCELL16:OUT18.TMIN | GTX1.DFESENSCAL1 |
| TCELL16:OUT19.TMIN | GTX1.DFESENSCAL0 |
| TCELL16:OUT20.TMIN | GTX1.RXRATEDONE |
| TCELL16:OUT22.TMIN | GTX1.DFESENSCAL2 |
| TCELL16:OUT23.TMIN | GTX1.TXRATEDONE |
| TCELL17:IMUX.CLK0 | GTX1.GREFCLKTX |
| TCELL17:IMUX.IMUX9.DELAY | GTX1.TXDLYALIGNFORCEROTATEB |
| TCELL17:IMUX.IMUX10.DELAY | GTX1.TXCOMWAKE |
| TCELL17:IMUX.IMUX11.DELAY | GTX1.TXDLYALIGNMONENB |
| TCELL17:IMUX.IMUX12.DELAY | GTX1.TXPLLLKDETEN |
| TCELL17:IMUX.IMUX13.DELAY | GTX1.TXDATA10 |
| TCELL17:IMUX.IMUX14.DELAY | GTX1.TXSTARTSEQ |
| TCELL17:IMUX.IMUX15.DELAY | GTX1.TXDATA8 |
| TCELL17:IMUX.IMUX18.DELAY | GTX1.TXCOMINIT |
| TCELL17:IMUX.IMUX19.DELAY | GTX1.TXCOMSAS |
| TCELL17:IMUX.IMUX21.DELAY | GTX1.TXDATA9 |
| TCELL17:IMUX.IMUX22.DELAY | GTX1.TXENC8B10BUSE |
| TCELL17:IMUX.IMUX24.DELAY | GTX1.TXDATA23 |
| TCELL17:IMUX.IMUX25.DELAY | GTX1.TXDATA22 |
| TCELL17:IMUX.IMUX26.DELAY | GTX1.TXDATA7 |
| TCELL17:IMUX.IMUX27.DELAY | GTX1.TXDATA20 |
| TCELL17:IMUX.IMUX28.DELAY | GTX1.TXDATA21 |
| TCELL17:IMUX.IMUX29.DELAY | GTX1.TXPLLPOWERDOWN |
| TCELL17:IMUX.IMUX30.DELAY | GTX1.TXDLYALIGNTESTMODEENB |
| TCELL17:IMUX.IMUX32.DELAY | GTX1.TXDATA31 |
| TCELL17:IMUX.IMUX33.DELAY | GTX1.TXDATA30 |
| TCELL17:IMUX.IMUX34.DELAY | GTX1.TXDATA6 |
| TCELL17:IMUX.IMUX35.DELAY | GTX1.TXDATA28 |
| TCELL17:IMUX.IMUX36.DELAY | GTX1.TXDATA29 |
| TCELL17:IMUX.IMUX37.DELAY | GTX1.TXPLLREFSELDY0 |
| TCELL17:IMUX.IMUX38.DELAY | GTX1.TXPLLREFSELDY1 |
| TCELL17:IMUX.IMUX39.DELAY | GTX1.TXPLLREFSELDY2 |
| TCELL17:IMUX.IMUX40.DELAY | GTX1.TXDATA11 |
| TCELL17:OUT0.TMIN | GTX1.TXDLYALIGNMONITOR7 |
| TCELL17:OUT1.TMIN | GTX1.DFETAP2MONITOR0 |
| TCELL17:OUT2.TMIN | GTX1.DFETAP2MONITOR1 |
| TCELL17:OUT3.TMIN | GTX1.DFETAP2MONITOR4 |
| TCELL17:OUT4.TMIN | GTX1.TXDLYALIGNMONITOR2 |
| TCELL17:OUT5.TMIN | GTX1.TXBUFSTATUS0 |
| TCELL17:OUT6.TMIN | GTX1.DFETAP2MONITOR2 |
| TCELL17:OUT7.TMIN | GTX1.DFETAP2MONITOR3 |
| TCELL17:OUT8.TMIN | GTX1.DFETAP4MONITOR1 |
| TCELL17:OUT9.TMIN | GTX1.DFETAP4MONITOR2 |
| TCELL17:OUT10.TMIN | GTX1.TXKERR1 |
| TCELL17:OUT11.TMIN | GTX1.TXKERR2 |
| TCELL17:OUT12.TMIN | GTX1.DFETAP4MONITOR0 |
| TCELL17:OUT13.TMIN | GTX1.DFETAP4MONITOR3 |
| TCELL17:OUT14.TMIN | GTX1.TXKERR0 |
| TCELL17:OUT15.TMIN | GTX1.TXKERR3 |
| TCELL17:OUT16.TMIN | GTX1.TXDLYALIGNMONITOR1 |
| TCELL17:OUT17.TMIN | GTX1.TXBUFSTATUS1 |
| TCELL17:OUT18.TMIN | GTX1.TXDLYALIGNMONITOR6 |
| TCELL17:OUT19.TMIN | GTX1.TXDLYALIGNMONITOR5 |
| TCELL17:OUT20.TMIN | GTX1.TXDLYALIGNMONITOR3 |
| TCELL17:OUT21.TMIN | GTX1.TXDLYALIGNMONITOR0 |
| TCELL17:OUT22.TMIN | GTX1.TXRESETDONE |
| TCELL17:OUT23.TMIN | GTX1.TXDLYALIGNMONITOR4 |
| TCELL18:IMUX.IMUX8.DELAY | GTX1.DWE |
| TCELL18:IMUX.IMUX9.DELAY | GTX1.SCANIN4 |
| TCELL18:IMUX.IMUX10.DELAY | GTX1.TXPOSTEMPHASIS0 |
| TCELL18:IMUX.IMUX12.DELAY | GTX1.TXPOSTEMPHASIS2 |
| TCELL18:IMUX.IMUX13.DELAY | GTX1.TXPRBSFORCEERR |
| TCELL18:IMUX.IMUX15.DELAY | GTX1.TXPDOWNASYNCH |
| TCELL18:IMUX.IMUX16.DELAY | GTX1.DEN |
| TCELL18:IMUX.IMUX17.DELAY | GTX1.TXENPMAPHASEALIGN |
| TCELL18:IMUX.IMUX18.DELAY | GTX1.TXPOSTEMPHASIS1 |
| TCELL18:IMUX.IMUX19.DELAY | GTX1.TXDATA25 |
| TCELL18:IMUX.IMUX20.DELAY | GTX1.TXPOSTEMPHASIS3 |
| TCELL18:IMUX.IMUX22.DELAY | GTX1.TXPOSTEMPHASIS4 |
| TCELL18:IMUX.IMUX25.DELAY | GTX1.SCANIN1 |
| TCELL18:IMUX.IMUX26.DELAY | GTX1.TXDATA4 |
| TCELL18:IMUX.IMUX27.DELAY | GTX1.TXDATA19 |
| TCELL18:IMUX.IMUX28.DELAY | GTX1.TXDATA2 |
| TCELL18:IMUX.IMUX29.DELAY | GTX1.TXDATA18 |
| TCELL18:IMUX.IMUX30.DELAY | GTX1.TXDATA17 |
| TCELL18:IMUX.IMUX31.DELAY | GTX1.TXDATA16 |
| TCELL18:IMUX.IMUX32.DELAY | GTX1.TXDATA3 |
| TCELL18:IMUX.IMUX33.DELAY | GTX1.SCANIN0 |
| TCELL18:IMUX.IMUX34.DELAY | GTX1.TXDATA5 |
| TCELL18:IMUX.IMUX35.DELAY | GTX1.TXDATA27 |
| TCELL18:IMUX.IMUX36.DELAY | GTX1.TXDATA1 |
| TCELL18:IMUX.IMUX37.DELAY | GTX1.TXDATA26 |
| TCELL18:IMUX.IMUX38.DELAY | GTX1.TXDATA0 |
| TCELL18:IMUX.IMUX39.DELAY | GTX1.TXDATA24 |
| TCELL18:OUT0.TMIN | GTX1.DRDY |
| TCELL18:OUT1.TMIN | GTX1.DFETAP1MONITOR0 |
| TCELL18:OUT2.TMIN | GTX1.DFETAP1MONITOR1 |
| TCELL18:OUT3.TMIN | GTX1.DFETAP1MONITOR4 |
| TCELL18:OUT5.TMIN | GTX1.TXPLLLKDET |
| TCELL18:OUT6.TMIN | GTX1.DFETAP1MONITOR2 |
| TCELL18:OUT7.TMIN | GTX1.DFETAP1MONITOR3 |
| TCELL18:OUT8.TMIN | GTX1.DFETAP3MONITOR1 |
| TCELL18:OUT9.TMIN | GTX1.DFETAP3MONITOR2 |
| TCELL18:OUT10.TMIN | GTX1.TXRUNDISP1 |
| TCELL18:OUT11.TMIN | GTX1.TXRUNDISP2 |
| TCELL18:OUT12.TMIN | GTX1.DFETAP3MONITOR0 |
| TCELL18:OUT13.TMIN | GTX1.DFETAP3MONITOR3 |
| TCELL18:OUT14.TMIN | GTX1.TXRUNDISP0 |
| TCELL18:OUT15.TMIN | GTX1.TXRUNDISP3 |
| TCELL18:OUT18.TMIN | GTX1.COMFINISH |
| TCELL19:IMUX.CLK0 | GTX1.DCLK |
| TCELL19:IMUX.IMUX8.DELAY | GTX1.DI0 |
| TCELL19:IMUX.IMUX9.DELAY | GTX1.DI1 |
| TCELL19:IMUX.IMUX10.DELAY | GTX1.DI2 |
| TCELL19:IMUX.IMUX11.DELAY | GTX1.DI3 |
| TCELL19:IMUX.IMUX12.DELAY | GTX1.DI4 |
| TCELL19:IMUX.IMUX13.DELAY | GTX1.DI5 |
| TCELL19:IMUX.IMUX14.DELAY | GTX1.DI6 |
| TCELL19:IMUX.IMUX15.DELAY | GTX1.DI7 |
| TCELL19:IMUX.IMUX16.DELAY | GTX1.DI8 |
| TCELL19:IMUX.IMUX17.DELAY | GTX1.DI9 |
| TCELL19:IMUX.IMUX18.DELAY | GTX1.DI10 |
| TCELL19:IMUX.IMUX19.DELAY | GTX1.DI11 |
| TCELL19:IMUX.IMUX20.DELAY | GTX1.DI12 |
| TCELL19:IMUX.IMUX21.DELAY | GTX1.DI13 |
| TCELL19:IMUX.IMUX22.DELAY | GTX1.DI14 |
| TCELL19:IMUX.IMUX23.DELAY | GTX1.DI15 |
| TCELL19:IMUX.IMUX30.DELAY | BUFDS1.CEB |
| TCELL19:IMUX.IMUX31.DELAY | BUFDS0.CEB |
| TCELL19:IMUX.IMUX32.DELAY | GTX1.DADDR0 |
| TCELL19:IMUX.IMUX33.DELAY | GTX1.DADDR1 |
| TCELL19:IMUX.IMUX34.DELAY | GTX1.DADDR2 |
| TCELL19:IMUX.IMUX35.DELAY | GTX1.DADDR3 |
| TCELL19:IMUX.IMUX36.DELAY | GTX1.DADDR4 |
| TCELL19:IMUX.IMUX37.DELAY | GTX1.DADDR5 |
| TCELL19:IMUX.IMUX38.DELAY | GTX1.DADDR6 |
| TCELL19:IMUX.IMUX39.DELAY | GTX1.DADDR7 |
| TCELL19:OUT0.TMIN | GTX1.DRPDO7 |
| TCELL19:OUT1.TMIN | GTX1.DRPDO4 |
| TCELL19:OUT2.TMIN | GTX1.DRPDO3 |
| TCELL19:OUT3.TMIN | GTX1.DRPDO0 |
| TCELL19:OUT4.TMIN | GTX1.DRPDO6 |
| TCELL19:OUT5.TMIN | GTX1.DRPDO5 |
| TCELL19:OUT6.TMIN | GTX1.DRPDO2 |
| TCELL19:OUT7.TMIN | GTX1.DRPDO1 |
| TCELL19:OUT8.TMIN | GTX1.DRPDO14 |
| TCELL19:OUT9.TMIN | GTX1.DRPDO13 |
| TCELL19:OUT10.TMIN | GTX1.DRPDO10 |
| TCELL19:OUT11.TMIN | GTX1.DRPDO9 |
| TCELL19:OUT12.TMIN | GTX1.DRPDO15 |
| TCELL19:OUT13.TMIN | GTX1.DRPDO12 |
| TCELL19:OUT14.TMIN | GTX1.DRPDO11 |
| TCELL19:OUT15.TMIN | GTX1.DRPDO8 |
| TCELL20:IMUX.CTRL1 | GTX2.PRBSCNTRESET |
| TCELL20:IMUX.IMUX0.DELAY | GTX2.TSTIN17 |
| TCELL20:IMUX.IMUX1.DELAY | GTX2.TSTIN18 |
| TCELL20:IMUX.IMUX8.DELAY | GTX2.TSTIN9 |
| TCELL20:IMUX.IMUX9.DELAY | GTX2.TSTIN7 |
| TCELL20:IMUX.IMUX10.DELAY | GTX2.TSTIN5 |
| TCELL20:IMUX.IMUX11.DELAY | GTX2.TSTIN3 |
| TCELL20:IMUX.IMUX13.DELAY | GTX2.TSTIN12 |
| TCELL20:IMUX.IMUX14.DELAY | GTX2.TSTIN1 |
| TCELL20:IMUX.IMUX16.DELAY | GTX2.TSTIN15 |
| TCELL20:IMUX.IMUX17.DELAY | GTX2.TSTPWRDNOVRD |
| TCELL20:IMUX.IMUX18.DELAY | GTX2.TSTPWRDN1 |
| TCELL20:IMUX.IMUX19.DELAY | GTX2.TSTPWRDN3 |
| TCELL20:IMUX.IMUX21.DELAY | GTX2.TSTIN11 |
| TCELL20:IMUX.IMUX22.DELAY | GTX2.SCANIN3 |
| TCELL20:IMUX.IMUX24.DELAY | GTX2.TSTIN8 |
| TCELL20:IMUX.IMUX25.DELAY | GTX2.TSTIN6 |
| TCELL20:IMUX.IMUX26.DELAY | GTX2.TSTIN4 |
| TCELL20:IMUX.IMUX27.DELAY | GTX2.TSTIN2 |
| TCELL20:IMUX.IMUX28.DELAY | GTX2.TSTIN13 |
| TCELL20:IMUX.IMUX29.DELAY | GTX2.SCANMODEB |
| TCELL20:IMUX.IMUX30.DELAY | GTX2.TSTIN0 |
| TCELL20:IMUX.IMUX31.DELAY | GTX2.TSTIN10 |
| TCELL20:IMUX.IMUX32.DELAY | GTX2.TSTIN14 |
| TCELL20:IMUX.IMUX33.DELAY | GTX2.TSTPWRDN0 |
| TCELL20:IMUX.IMUX34.DELAY | GTX2.TSTPWRDN2 |
| TCELL20:IMUX.IMUX35.DELAY | GTX2.TSTPWRDN4 |
| TCELL20:IMUX.IMUX37.DELAY | GTX2.SCANENB |
| TCELL20:IMUX.IMUX38.DELAY | GTX2.SCANIN2 |
| TCELL20:IMUX.IMUX40.DELAY | GTX2.TSTIN16 |
| TCELL20:IMUX.IMUX41.DELAY | GTX2.TSTIN19 |
| TCELL20:OUT0.TMIN | GTX2.RXDATA18 |
| TCELL20:OUT1.TMIN | GTX2.RXDATA4 |
| TCELL20:OUT2.TMIN | GTX2.RXDATA3 |
| TCELL20:OUT3.TMIN | GTX2.RXDATA17 |
| TCELL20:OUT4.TMIN | GTX2.RXDATA0 |
| TCELL20:OUT5.TMIN | GTX2.RXDATA5 |
| TCELL20:OUT6.TMIN | GTX2.RXDATA2 |
| TCELL20:OUT7.TMIN | GTX2.RXDATA1 |
| TCELL20:OUT8.TMIN | GTX2.SCANOUT4 |
| TCELL20:OUT13.TMIN | GTX2.SCANOUT3 |
| TCELL20:OUT15.TMIN | GTX2.RXDATA16 |
| TCELL20:OUT16.TMIN | GTX2.RXDATA22 |
| TCELL20:OUT17.TMIN | GTX2.RXDATA21 |
| TCELL20:OUT18.TMIN | GTX2.RXDATA20 |
| TCELL20:OUT20.TMIN | GTX2.RXDATA23 |
| TCELL20:OUT22.TMIN | GTX2.RXDATA19 |
| TCELL20:OUT23.TMIN | GTX2.SCANOUT2 |
| TCELL21:IMUX.CTRL0 | GTX2.GTXRXRESET |
| TCELL21:IMUX.CTRL1 | GTX2.RXCDRRESET |
| TCELL21:IMUX.IMUX9.DELAY | GTX2.RXSLIDE |
| TCELL21:IMUX.IMUX11.DELAY | GTX2.RXPMASETPHASE |
| TCELL21:IMUX.IMUX12.DELAY | GTX2.RXGEARBOXSLIP |
| TCELL21:IMUX.IMUX14.DELAY | GTX2.RXEQMIX0 |
| TCELL21:IMUX.IMUX15.DELAY | GTX2.RXEQMIX1 |
| TCELL21:IMUX.IMUX18.DELAY | GTX2.RXENPRBSTST2 |
| TCELL21:IMUX.IMUX19.DELAY | GTX2.RXEQMIX9 |
| TCELL21:IMUX.IMUX20.DELAY | GTX2.RXEQMIX7 |
| TCELL21:IMUX.IMUX21.DELAY | GTX2.RXEQMIX5 |
| TCELL21:IMUX.IMUX22.DELAY | GTX2.RXEQMIX3 |
| TCELL21:IMUX.IMUX24.DELAY | GTX2.RXBUFWE |
| TCELL21:IMUX.IMUX26.DELAY | GTX2.RXPOLARITY |
| TCELL21:IMUX.IMUX27.DELAY | GTX2.RXEQMIX8 |
| TCELL21:IMUX.IMUX28.DELAY | GTX2.RXEQMIX6 |
| TCELL21:IMUX.IMUX29.DELAY | GTX2.RXEQMIX4 |
| TCELL21:IMUX.IMUX30.DELAY | GTX2.RXEQMIX2 |
| TCELL21:IMUX.IMUX32.DELAY | GTX2.RXENSAMPLEALIGN |
| TCELL21:IMUX.IMUX33.DELAY | GTX2.RXENPRBSTST0 |
| TCELL21:IMUX.IMUX34.DELAY | GTX2.RXENPRBSTST1 |
| TCELL21:IMUX.IMUX35.DELAY | GTX2.RXENPMAPHASEALIGN |
| TCELL21:IMUX.IMUX36.DELAY | GTX2.RXENMCOMMAALIGN |
| TCELL21:IMUX.IMUX37.DELAY | GTX2.RXENPCOMMAALIGN |
| TCELL21:IMUX.IMUX38.DELAY | GTX2.RXENCHANSYNC |
| TCELL21:IMUX.IMUX39.DELAY | GTX2.RXDEC8B10BUSE |
| TCELL21:OUT0.TMIN | GTX2.RXDATA24 |
| TCELL21:OUT1.TMIN | GTX2.RXDATA6 |
| TCELL21:OUT2.TMIN | GTX2.RXDATA11 |
| TCELL21:OUT3.TMIN | GTX2.RXDATA31 |
| TCELL21:OUT4.TMIN | GTX2.RXDATA8 |
| TCELL21:OUT5.TMIN | GTX2.RXDATA7 |
| TCELL21:OUT6.TMIN | GTX2.RXDATA10 |
| TCELL21:OUT7.TMIN | GTX2.RXDATA9 |
| TCELL21:OUT8.TMIN | GTX2.TSTOUT8 |
| TCELL21:OUT9.TMIN | GTX2.RXDATA27 |
| TCELL21:OUT10.TMIN | GTX2.TSTOUT2 |
| TCELL21:OUT11.TMIN | GTX2.RXDATA29 |
| TCELL21:OUT12.TMIN | GTX2.TSTOUT9 |
| TCELL21:OUT13.TMIN | GTX2.TSTOUT6 |
| TCELL21:OUT14.TMIN | GTX2.TSTOUT4 |
| TCELL21:OUT15.TMIN | GTX2.RXDATA30 |
| TCELL21:OUT16.TMIN | GTX2.RXDATA28 |
| TCELL21:OUT17.TMIN | GTX2.TSTOUT1 |
| TCELL21:OUT18.TMIN | GTX2.RXDATA26 |
| TCELL21:OUT19.TMIN | GTX2.TSTOUT7 |
| TCELL21:OUT20.TMIN | GTX2.TSTOUT3 |
| TCELL21:OUT21.TMIN | GTX2.TSTOUT0 |
| TCELL21:OUT22.TMIN | GTX2.RXDATA25 |
| TCELL21:OUT23.TMIN | GTX2.TSTOUT5 |
| TCELL22:IMUX.CLK0 | GTX2.RXUSRCLK |
| TCELL22:IMUX.CLK1 | GTX2.RXUSRCLK2 |
| TCELL22:IMUX.CTRL0 | GTX2.RXBUFRESET |
| TCELL22:IMUX.CTRL1 | GTX2.RXRESET |
| TCELL22:IMUX.IMUX8.DELAY | GTX2.RXCHBONDSLAVE |
| TCELL22:IMUX.IMUX10.DELAY | GTX2.RXCHBONDLEVEL0 |
| TCELL22:IMUX.IMUX11.DELAY | GTX2.RXCHBONDLEVEL2 |
| TCELL22:IMUX.IMUX14.DELAY | GTX2.USRCODEERR |
| TCELL22:IMUX.IMUX18.DELAY | GTX2.CLKTESTSIG1 |
| TCELL22:IMUX.IMUX19.DELAY | GTX2.CLKTESTSIG0 |
| TCELL22:IMUX.IMUX20.DELAY | GTX2.RXPLLLKDETEN |
| TCELL22:IMUX.IMUX21.DELAY | GTX2.RXPLLPOWERDOWN |
| TCELL22:IMUX.IMUX24.DELAY | GTX2.RXCHBONDMASTER |
| TCELL22:IMUX.IMUX26.DELAY | GTX2.RXCHBONDLEVEL1 |
| TCELL22:IMUX.IMUX27.DELAY | GTX2.GTXTEST12 |
| TCELL22:IMUX.IMUX28.DELAY | GTX2.GTXTEST11 |
| TCELL22:IMUX.IMUX29.DELAY | GTX2.GTXTEST10 |
| TCELL22:IMUX.IMUX30.DELAY | GTX2.GTXTEST9 |
| TCELL22:IMUX.IMUX31.DELAY | GTX2.GTXTEST8 |
| TCELL22:IMUX.IMUX32.DELAY | GTX2.GTXTEST7 |
| TCELL22:IMUX.IMUX33.DELAY | GTX2.GTXTEST6 |
| TCELL22:IMUX.IMUX34.DELAY | GTX2.GTXTEST5 |
| TCELL22:IMUX.IMUX35.DELAY | GTX2.GTXTEST4 |
| TCELL22:IMUX.IMUX36.DELAY | GTX2.GTXTEST3 |
| TCELL22:IMUX.IMUX37.DELAY | GTX2.GTXTEST2 |
| TCELL22:IMUX.IMUX38.DELAY | GTX2.GTXTEST1 |
| TCELL22:IMUX.IMUX39.DELAY | GTX2.GTXTEST0 |
| TCELL22:OUT0.TMIN | GTX2.RXLOSSOFSYNC0 |
| TCELL22:OUT1.TMIN | GTX2.RXDATA15 |
| TCELL22:OUT2.TMIN | GTX2.RXDATA14 |
| TCELL22:OUT3.TMIN | GTX2.RXCHARISK3 |
| TCELL22:OUT4.TMIN | GTX2.RXDATAVALID |
| TCELL22:OUT5.TMIN | GTX2.RXCHARISK1 |
| TCELL22:OUT6.TMIN | GTX2.RXDATA13 |
| TCELL22:OUT7.TMIN | GTX2.RXDATA12 |
| TCELL22:OUT8.TMIN | GTX2.RXCHARISCOMMA2 |
| TCELL22:OUT10.TMIN | GTX2.RXBYTEREALIGN |
| TCELL22:OUT13.TMIN | GTX2.RXBYTEISALIGNED |
| TCELL22:OUT14.TMIN | GTX2.RXCHANREALIGN |
| TCELL22:OUT15.TMIN | GTX2.RXCHARISK2 |
| TCELL22:OUT18.TMIN | GTX2.RXCHARISCOMMA3 |
| TCELL22:OUT19.TMIN | GTX2.COMSASDET |
| TCELL22:OUT20.TMIN | GTX2.COMINITDET |
| TCELL22:OUT22.TMIN | GTX2.RXLOSSOFSYNC1 |
| TCELL22:OUT23.TMIN | GTX2.COMWAKEDET |
| TCELL23:IMUX.CLK0 | GTX2.GREFCLKRX |
| TCELL23:IMUX.CLK1 | GTX2.TSTCLK0 |
| TCELL23:IMUX.CTRL0 | GTX2.PLLRXRESET |
| TCELL23:IMUX.IMUX0.DELAY | GTX2.TXBUFDIFFCTRL0 |
| TCELL23:IMUX.IMUX3.DELAY | GTX2.TXDEEMPH |
| TCELL23:IMUX.IMUX5.DELAY | GTX2.TXDIFFCTRL2 |
| TCELL23:IMUX.IMUX9.DELAY | GTX2.TXPREEMPHASIS3 |
| TCELL23:IMUX.IMUX11.DELAY | GTX2.LOOPBACK1 |
| TCELL23:IMUX.IMUX12.DELAY | GTX2.RXDLYALIGNTESTMODEENB |
| TCELL23:IMUX.IMUX13.DELAY | GTX2.TXSWING |
| TCELL23:IMUX.IMUX16.DELAY | GTX2.TXBUFDIFFCTRL1 |
| TCELL23:IMUX.IMUX17.DELAY | GTX2.TXPREEMPHASIS2 |
| TCELL23:IMUX.IMUX18.DELAY | GTX2.TXBUFDIFFCTRL2 |
| TCELL23:IMUX.IMUX19.DELAY | GTX2.TXPREEMPHASIS1 |
| TCELL23:IMUX.IMUX21.DELAY | GTX2.TXDIFFCTRL0 |
| TCELL23:IMUX.IMUX22.DELAY | GTX2.RXPLLREFSELDY1 |
| TCELL23:IMUX.IMUX24.DELAY | GTX2.LOOPBACK0 |
| TCELL23:IMUX.IMUX25.DELAY | GTX2.RXDLYALIGNFORCEROTATEB |
| TCELL23:IMUX.IMUX26.DELAY | GTX2.TXPREEMPHASIS0 |
| TCELL23:IMUX.IMUX27.DELAY | GTX2.LOOPBACK2 |
| TCELL23:IMUX.IMUX28.DELAY | GTX2.RXDLYALIGNMONENB |
| TCELL23:IMUX.IMUX29.DELAY | GTX2.RXDLYALIGNSWPPRECURB |
| TCELL23:IMUX.IMUX30.DELAY | GTX2.TXDIFFCTRL3 |
| TCELL23:IMUX.IMUX32.DELAY | GTX2.RXCHBONDI0 |
| TCELL23:IMUX.IMUX33.DELAY | GTX2.RXCHBONDI1 |
| TCELL23:IMUX.IMUX34.DELAY | GTX2.RXCHBONDI2 |
| TCELL23:IMUX.IMUX35.DELAY | GTX2.RXCHBONDI3 |
| TCELL23:IMUX.IMUX36.DELAY | GTX2.RXCOMMADETUSE |
| TCELL23:IMUX.IMUX37.DELAY | GTX2.RXPLLREFSELDY0 |
| TCELL23:IMUX.IMUX38.DELAY | GTX2.TXDIFFCTRL1 |
| TCELL23:IMUX.IMUX39.DELAY | GTX2.RXPLLREFSELDY2 |
| TCELL23:OUT0.TMIN | GTX2.RXDISPERR2 |
| TCELL23:OUT1.TMIN | GTX2.RXRUNDISP3 |
| TCELL23:OUT2.TMIN | GTX2.RXCHARISCOMMA1 |
| TCELL23:OUT3.TMIN | GTX2.RXNOTINTABLE3 |
| TCELL23:OUT4.TMIN | GTX2.RXDISPERR0 |
| TCELL23:OUT5.TMIN | GTX2.RXRUNDISP1 |
| TCELL23:OUT7.TMIN | GTX2.RXNOTINTABLE1 |
| TCELL23:OUT8.TMIN | GTX2.RXDISPERR1 |
| TCELL23:OUT9.TMIN | GTX2.RXRUNDISP0 |
| TCELL23:OUT11.TMIN | GTX2.RXNOTINTABLE0 |
| TCELL23:OUT13.TMIN | GTX2.RXCHANISALIGNED |
| TCELL23:OUT14.TMIN | GTX2.RXCHARISCOMMA0 |
| TCELL23:OUT15.TMIN | GTX2.RXNOTINTABLE2 |
| TCELL23:OUT16.TMIN | GTX2.RXCHARISK0 |
| TCELL23:OUT19.TMIN | GTX2.RXRUNDISP2 |
| TCELL23:OUT22.TMIN | GTX2.RXDISPERR3 |
| TCELL24:IMUX.CLK1 | GTX2.SCANCLK |
| TCELL24:IMUX.IMUX8.DELAY | GTX2.DFETAP10 |
| TCELL24:IMUX.IMUX9.DELAY | GTX2.TXDETECTRX |
| TCELL24:IMUX.IMUX10.DELAY | GTX2.DFETAP11 |
| TCELL24:IMUX.IMUX11.DELAY | GTX2.TXMARGIN0 |
| TCELL24:IMUX.IMUX13.DELAY | GTX2.RXPOWERDOWN0 |
| TCELL24:IMUX.IMUX14.DELAY | GTX2.DFETAP12 |
| TCELL24:IMUX.IMUX15.DELAY | GTX2.DFETAP13 |
| TCELL24:IMUX.IMUX16.DELAY | GTX2.DFECLKDLYADJ5 |
| TCELL24:IMUX.IMUX17.DELAY | GTX2.DFECLKDLYADJ4 |
| TCELL24:IMUX.IMUX18.DELAY | GTX2.DFECLKDLYADJ2 |
| TCELL24:IMUX.IMUX19.DELAY | GTX2.DFECLKDLYADJ1 |
| TCELL24:IMUX.IMUX21.DELAY | GTX2.RXPOWERDOWN1 |
| TCELL24:IMUX.IMUX24.DELAY | GTX2.DFETAP20 |
| TCELL24:IMUX.IMUX25.DELAY | GTX2.DFETAP21 |
| TCELL24:IMUX.IMUX26.DELAY | GTX2.TXMARGIN1 |
| TCELL24:IMUX.IMUX28.DELAY | GTX2.TXPOWERDOWN0 |
| TCELL24:IMUX.IMUX29.DELAY | GTX2.DFEDLYOVRD |
| TCELL24:IMUX.IMUX30.DELAY | GTX2.DFETAP22 |
| TCELL24:IMUX.IMUX31.DELAY | GTX2.DFETAP23 |
| TCELL24:IMUX.IMUX32.DELAY | GTX2.TXELECIDLE |
| TCELL24:IMUX.IMUX33.DELAY | GTX2.DFECLKDLYADJ3 |
| TCELL24:IMUX.IMUX35.DELAY | GTX2.DFECLKDLYADJ0 |
| TCELL24:IMUX.IMUX36.DELAY | GTX2.TXPOWERDOWN1 |
| TCELL24:IMUX.IMUX37.DELAY | GTX2.DFETAPOVRD |
| TCELL24:IMUX.IMUX38.DELAY | GTX2.DFETAP14 |
| TCELL24:IMUX.IMUX39.DELAY | GTX2.DFETAP24 |
| TCELL24:OUT0.TMIN | GTX2.MGTREFCLKFAB0 |
| TCELL24:OUT3.TMIN | GTX2.RXBUFSTATUS2 |
| TCELL24:OUT4.TMIN | GTX2.SCANOUT1 |
| TCELL24:OUT5.TMIN | GTX2.RXPLLLKDET |
| TCELL24:OUT6.TMIN | GTX2.RXBUFSTATUS0 |
| TCELL24:OUT7.TMIN | GTX2.RXBUFSTATUS1 |
| TCELL24:OUT8.TMIN | GTX2.PHYSTATUS |
| TCELL24:OUT10.TMIN | GTX2.RXCHBONDO1 |
| TCELL24:OUT11.TMIN | GTX2.RXCHBONDO2 |
| TCELL24:OUT12.TMIN | GTX2.MGTREFCLKFAB1 |
| TCELL24:OUT13.TMIN | GTX2.RXSTATUS2 |
| TCELL24:OUT14.TMIN | GTX2.RXSTATUS0 |
| TCELL24:OUT15.TMIN | GTX2.RXCHBONDO3 |
| TCELL24:OUT16.TMIN | GTX2.RXSTATUS1 |
| TCELL24:OUT17.TMIN | GTX2.RXCHBONDO0 |
| TCELL24:OUT18.TMIN | GTX2.SCANOUT0 |
| TCELL24:OUT22.TMIN | GTX2.RXOVERSAMPLEERR |
| TCELL25:IMUX.CLK1 | GTX2.TSTCLK1 |
| TCELL25:IMUX.CTRL1 | GTX2.PLLTXRESET |
| TCELL25:IMUX.IMUX2.DELAY | GTX2.TXDLYALIGNUPDSW |
| TCELL25:IMUX.IMUX8.DELAY | GTX2.TXHEADER0 |
| TCELL25:IMUX.IMUX9.DELAY | GTX2.TXPOLARITY |
| TCELL25:IMUX.IMUX10.DELAY | GTX2.RXDLYALIGNUPDSW |
| TCELL25:IMUX.IMUX11.DELAY | GTX2.TXBYPASS8B10B0 |
| TCELL25:IMUX.IMUX13.DELAY | GTX2.TXDLYALIGNRESET |
| TCELL25:IMUX.IMUX14.DELAY | GTX2.RXDLYALIGNDISABLE |
| TCELL25:IMUX.IMUX15.DELAY | GTX2.TXMARGIN2 |
| TCELL25:IMUX.IMUX16.DELAY | GTX2.TXHEADER1 |
| TCELL25:IMUX.IMUX17.DELAY | GTX2.TXINHIBIT |
| TCELL25:IMUX.IMUX18.DELAY | GTX2.TXPMASETPHASE |
| TCELL25:IMUX.IMUX19.DELAY | GTX2.TXBYPASS8B10B3 |
| TCELL25:IMUX.IMUX21.DELAY | GTX2.TXCHARDISPMODE3 |
| TCELL25:IMUX.IMUX22.DELAY | GTX2.TXCHARDISPVAL3 |
| TCELL25:IMUX.IMUX23.DELAY | GTX2.TXCHARISK3 |
| TCELL25:IMUX.IMUX25.DELAY | GTX2.TXDLYALIGNOVERRIDE |
| TCELL25:IMUX.IMUX26.DELAY | GTX2.TXCHARISK0 |
| TCELL25:IMUX.IMUX27.DELAY | GTX2.TXBYPASS8B10B1 |
| TCELL25:IMUX.IMUX28.DELAY | GTX2.TXCHARDISPMODE1 |
| TCELL25:IMUX.IMUX29.DELAY | GTX2.RXDLYALIGNRESET |
| TCELL25:IMUX.IMUX30.DELAY | GTX2.TXCHARDISPVAL1 |
| TCELL25:IMUX.IMUX32.DELAY | GTX2.TXHEADER2 |
| TCELL25:IMUX.IMUX33.DELAY | GTX2.RXDLYALIGNOVERRIDE |
| TCELL25:IMUX.IMUX34.DELAY | GTX2.TXCHARDISPMODE0 |
| TCELL25:IMUX.IMUX35.DELAY | GTX2.TXBYPASS8B10B2 |
| TCELL25:IMUX.IMUX36.DELAY | GTX2.TXCHARISK1 |
| TCELL25:IMUX.IMUX37.DELAY | GTX2.TXCHARDISPMODE2 |
| TCELL25:IMUX.IMUX38.DELAY | GTX2.TXCHARDISPVAL2 |
| TCELL25:IMUX.IMUX39.DELAY | GTX2.TXCHARISK2 |
| TCELL25:IMUX.IMUX44.DELAY | GTX2.TXCHARDISPVAL0 |
| TCELL25:IMUX.IMUX46.DELAY | GTX2.TXDLYALIGNDISABLE |
| TCELL25:OUT0.TMIN | GTX2.RXDLYALIGNMONITOR7 |
| TCELL25:OUT1.TMIN | GTX2.RXSTARTOFSEQ |
| TCELL25:OUT2.TMIN | GTX2.RXPRBSERR |
| TCELL25:OUT3.TMIN | GTX2.RXELECIDLE |
| TCELL25:OUT4.TMIN | GTX2.RXVALID |
| TCELL25:OUT5.TMIN | GTX2.RXRECCLKPCS |
| TCELL25:OUT6.TMIN | GTX2.RXCLKCORCNT2 |
| TCELL25:OUT7.TMIN | GTX2.RXDLYALIGNMONITOR2 |
| TCELL25:OUT8.TMIN | GTX2.RXCLKCORCNT0 |
| TCELL25:OUT9.TMIN | GTX2.RXCLKCORCNT1 |
| TCELL25:OUT10.TMIN | GTX2.RXHEADER0 |
| TCELL25:OUT11.TMIN | GTX2.RXHEADERVALID |
| TCELL25:OUT12.TMIN | GTX2.RXCOMMADET |
| TCELL25:OUT14.TMIN | GTX2.RXCHANBONDSEQ |
| TCELL25:OUT15.TMIN | GTX2.RXDLYALIGNMONITOR1 |
| TCELL25:OUT16.TMIN | GTX2.RXHEADER1 |
| TCELL25:OUT17.TMIN | GTX2.RXHEADER2 |
| TCELL25:OUT18.TMIN | GTX2.RXDLYALIGNMONITOR6 |
| TCELL25:OUT19.TMIN | GTX2.RXDLYALIGNMONITOR5 |
| TCELL25:OUT20.TMIN | GTX2.RXDLYALIGNMONITOR3 |
| TCELL25:OUT21.TMIN | GTX2.RXDLYALIGNMONITOR0 |
| TCELL25:OUT22.TMIN | GTX2.RXRESETDONE |
| TCELL25:OUT23.TMIN | GTX2.RXDLYALIGNMONITOR4 |
| TCELL26:IMUX.CLK0 | GTX2.TXUSRCLK |
| TCELL26:IMUX.CLK1 | GTX2.TXUSRCLK2 |
| TCELL26:IMUX.CTRL0 | GTX2.TXRESET |
| TCELL26:IMUX.CTRL1 | GTX2.GTXTXRESET |
| TCELL26:IMUX.IMUX3.DELAY | GTX2.TXDATA12 |
| TCELL26:IMUX.IMUX5.DELAY | GTX2.TXDATA14 |
| TCELL26:IMUX.IMUX8.DELAY | GTX2.TXSEQUENCE3 |
| TCELL26:IMUX.IMUX9.DELAY | GTX2.DFETAP31 |
| TCELL26:IMUX.IMUX10.DELAY | GTX2.DFETAP30 |
| TCELL26:IMUX.IMUX11.DELAY | GTX2.TXSEQUENCE0 |
| TCELL26:IMUX.IMUX12.DELAY | GTX2.DFETAP32 |
| TCELL26:IMUX.IMUX13.DELAY | GTX2.TXDATA15 |
| TCELL26:IMUX.IMUX15.DELAY | GTX2.TXENPRBSTST2 |
| TCELL26:IMUX.IMUX17.DELAY | GTX2.DFETAP33 |
| TCELL26:IMUX.IMUX19.DELAY | GTX2.TXSEQUENCE1 |
| TCELL26:IMUX.IMUX20.DELAY | GTX2.DFETAP43 |
| TCELL26:IMUX.IMUX22.DELAY | GTX2.TXSEQUENCE5 |
| TCELL26:IMUX.IMUX23.DELAY | GTX2.TXENPRBSTST1 |
| TCELL26:IMUX.IMUX24.DELAY | GTX2.TXSEQUENCE4 |
| TCELL26:IMUX.IMUX25.DELAY | GTX2.DFETAP41 |
| TCELL26:IMUX.IMUX26.DELAY | GTX2.DFETAP40 |
| TCELL26:IMUX.IMUX28.DELAY | GTX2.DFETAP42 |
| TCELL26:IMUX.IMUX30.DELAY | GTX2.TXDATA13 |
| TCELL26:IMUX.IMUX32.DELAY | GTX2.GATERXELECIDLE |
| TCELL26:IMUX.IMUX33.DELAY | GTX2.TXRATE1 |
| TCELL26:IMUX.IMUX34.DELAY | GTX2.TXRATE0 |
| TCELL26:IMUX.IMUX35.DELAY | GTX2.TXSEQUENCE2 |
| TCELL26:IMUX.IMUX37.DELAY | GTX2.IGNORESIGDET |
| TCELL26:IMUX.IMUX38.DELAY | GTX2.TXSEQUENCE6 |
| TCELL26:IMUX.IMUX39.DELAY | GTX2.TXENPRBSTST0 |
| TCELL26:IMUX.IMUX41.DELAY | GTX2.RXRATE1 |
| TCELL26:IMUX.IMUX42.DELAY | GTX2.RXRATE0 |
| TCELL26:OUT1.TMIN | GTX2.DFECLKDLYADJMON1 |
| TCELL26:OUT2.TMIN | GTX2.DFECLKDLYADJMON2 |
| TCELL26:OUT3.TMIN | GTX2.DFECLKDLYADJMON5 |
| TCELL26:OUT4.TMIN | GTX2.TXGEARBOXREADY |
| TCELL26:OUT5.TMIN | GTX2.DFECLKDLYADJMON0 |
| TCELL26:OUT6.TMIN | GTX2.DFECLKDLYADJMON3 |
| TCELL26:OUT7.TMIN | GTX2.DFECLKDLYADJMON4 |
| TCELL26:OUT8.TMIN | GTX2.TXOUTCLKPCS |
| TCELL26:OUT10.TMIN | GTX2.DFEEYEDACMON2 |
| TCELL26:OUT11.TMIN | GTX2.DFEEYEDACMON3 |
| TCELL26:OUT13.TMIN | GTX2.DFEEYEDACMON0 |
| TCELL26:OUT14.TMIN | GTX2.DFEEYEDACMON1 |
| TCELL26:OUT15.TMIN | GTX2.DFEEYEDACMON4 |
| TCELL26:OUT18.TMIN | GTX2.DFESENSCAL1 |
| TCELL26:OUT19.TMIN | GTX2.DFESENSCAL0 |
| TCELL26:OUT20.TMIN | GTX2.RXRATEDONE |
| TCELL26:OUT22.TMIN | GTX2.DFESENSCAL2 |
| TCELL26:OUT23.TMIN | GTX2.TXRATEDONE |
| TCELL27:IMUX.CLK0 | GTX2.GREFCLKTX |
| TCELL27:IMUX.IMUX9.DELAY | GTX2.TXDLYALIGNFORCEROTATEB |
| TCELL27:IMUX.IMUX10.DELAY | GTX2.TXCOMWAKE |
| TCELL27:IMUX.IMUX11.DELAY | GTX2.TXDLYALIGNMONENB |
| TCELL27:IMUX.IMUX12.DELAY | GTX2.TXPLLLKDETEN |
| TCELL27:IMUX.IMUX13.DELAY | GTX2.TXDATA10 |
| TCELL27:IMUX.IMUX14.DELAY | GTX2.TXSTARTSEQ |
| TCELL27:IMUX.IMUX15.DELAY | GTX2.TXDATA8 |
| TCELL27:IMUX.IMUX18.DELAY | GTX2.TXCOMINIT |
| TCELL27:IMUX.IMUX19.DELAY | GTX2.TXCOMSAS |
| TCELL27:IMUX.IMUX21.DELAY | GTX2.TXDATA9 |
| TCELL27:IMUX.IMUX22.DELAY | GTX2.TXENC8B10BUSE |
| TCELL27:IMUX.IMUX24.DELAY | GTX2.TXDATA23 |
| TCELL27:IMUX.IMUX25.DELAY | GTX2.TXDATA22 |
| TCELL27:IMUX.IMUX26.DELAY | GTX2.TXDATA7 |
| TCELL27:IMUX.IMUX27.DELAY | GTX2.TXDATA20 |
| TCELL27:IMUX.IMUX28.DELAY | GTX2.TXDATA21 |
| TCELL27:IMUX.IMUX29.DELAY | GTX2.TXPLLPOWERDOWN |
| TCELL27:IMUX.IMUX30.DELAY | GTX2.TXDLYALIGNTESTMODEENB |
| TCELL27:IMUX.IMUX32.DELAY | GTX2.TXDATA31 |
| TCELL27:IMUX.IMUX33.DELAY | GTX2.TXDATA30 |
| TCELL27:IMUX.IMUX34.DELAY | GTX2.TXDATA6 |
| TCELL27:IMUX.IMUX35.DELAY | GTX2.TXDATA28 |
| TCELL27:IMUX.IMUX36.DELAY | GTX2.TXDATA29 |
| TCELL27:IMUX.IMUX37.DELAY | GTX2.TXPLLREFSELDY0 |
| TCELL27:IMUX.IMUX38.DELAY | GTX2.TXPLLREFSELDY1 |
| TCELL27:IMUX.IMUX39.DELAY | GTX2.TXPLLREFSELDY2 |
| TCELL27:IMUX.IMUX40.DELAY | GTX2.TXDATA11 |
| TCELL27:OUT0.TMIN | GTX2.TXDLYALIGNMONITOR7 |
| TCELL27:OUT1.TMIN | GTX2.DFETAP2MONITOR0 |
| TCELL27:OUT2.TMIN | GTX2.DFETAP2MONITOR1 |
| TCELL27:OUT3.TMIN | GTX2.DFETAP2MONITOR4 |
| TCELL27:OUT4.TMIN | GTX2.TXDLYALIGNMONITOR2 |
| TCELL27:OUT5.TMIN | GTX2.TXBUFSTATUS0 |
| TCELL27:OUT6.TMIN | GTX2.DFETAP2MONITOR2 |
| TCELL27:OUT7.TMIN | GTX2.DFETAP2MONITOR3 |
| TCELL27:OUT8.TMIN | GTX2.DFETAP4MONITOR1 |
| TCELL27:OUT9.TMIN | GTX2.DFETAP4MONITOR2 |
| TCELL27:OUT10.TMIN | GTX2.TXKERR1 |
| TCELL27:OUT11.TMIN | GTX2.TXKERR2 |
| TCELL27:OUT12.TMIN | GTX2.DFETAP4MONITOR0 |
| TCELL27:OUT13.TMIN | GTX2.DFETAP4MONITOR3 |
| TCELL27:OUT14.TMIN | GTX2.TXKERR0 |
| TCELL27:OUT15.TMIN | GTX2.TXKERR3 |
| TCELL27:OUT16.TMIN | GTX2.TXDLYALIGNMONITOR1 |
| TCELL27:OUT17.TMIN | GTX2.TXBUFSTATUS1 |
| TCELL27:OUT18.TMIN | GTX2.TXDLYALIGNMONITOR6 |
| TCELL27:OUT19.TMIN | GTX2.TXDLYALIGNMONITOR5 |
| TCELL27:OUT20.TMIN | GTX2.TXDLYALIGNMONITOR3 |
| TCELL27:OUT21.TMIN | GTX2.TXDLYALIGNMONITOR0 |
| TCELL27:OUT22.TMIN | GTX2.TXRESETDONE |
| TCELL27:OUT23.TMIN | GTX2.TXDLYALIGNMONITOR4 |
| TCELL28:IMUX.IMUX8.DELAY | GTX2.DWE |
| TCELL28:IMUX.IMUX9.DELAY | GTX2.SCANIN4 |
| TCELL28:IMUX.IMUX10.DELAY | GTX2.TXPOSTEMPHASIS0 |
| TCELL28:IMUX.IMUX12.DELAY | GTX2.TXPOSTEMPHASIS2 |
| TCELL28:IMUX.IMUX13.DELAY | GTX2.TXPRBSFORCEERR |
| TCELL28:IMUX.IMUX15.DELAY | GTX2.TXPDOWNASYNCH |
| TCELL28:IMUX.IMUX16.DELAY | GTX2.DEN |
| TCELL28:IMUX.IMUX17.DELAY | GTX2.TXENPMAPHASEALIGN |
| TCELL28:IMUX.IMUX18.DELAY | GTX2.TXPOSTEMPHASIS1 |
| TCELL28:IMUX.IMUX19.DELAY | GTX2.TXDATA25 |
| TCELL28:IMUX.IMUX20.DELAY | GTX2.TXPOSTEMPHASIS3 |
| TCELL28:IMUX.IMUX22.DELAY | GTX2.TXPOSTEMPHASIS4 |
| TCELL28:IMUX.IMUX25.DELAY | GTX2.SCANIN1 |
| TCELL28:IMUX.IMUX26.DELAY | GTX2.TXDATA4 |
| TCELL28:IMUX.IMUX27.DELAY | GTX2.TXDATA19 |
| TCELL28:IMUX.IMUX28.DELAY | GTX2.TXDATA2 |
| TCELL28:IMUX.IMUX29.DELAY | GTX2.TXDATA18 |
| TCELL28:IMUX.IMUX30.DELAY | GTX2.TXDATA17 |
| TCELL28:IMUX.IMUX31.DELAY | GTX2.TXDATA16 |
| TCELL28:IMUX.IMUX32.DELAY | GTX2.TXDATA3 |
| TCELL28:IMUX.IMUX33.DELAY | GTX2.SCANIN0 |
| TCELL28:IMUX.IMUX34.DELAY | GTX2.TXDATA5 |
| TCELL28:IMUX.IMUX35.DELAY | GTX2.TXDATA27 |
| TCELL28:IMUX.IMUX36.DELAY | GTX2.TXDATA1 |
| TCELL28:IMUX.IMUX37.DELAY | GTX2.TXDATA26 |
| TCELL28:IMUX.IMUX38.DELAY | GTX2.TXDATA0 |
| TCELL28:IMUX.IMUX39.DELAY | GTX2.TXDATA24 |
| TCELL28:OUT0.TMIN | GTX2.DRDY |
| TCELL28:OUT1.TMIN | GTX2.DFETAP1MONITOR0 |
| TCELL28:OUT2.TMIN | GTX2.DFETAP1MONITOR1 |
| TCELL28:OUT3.TMIN | GTX2.DFETAP1MONITOR4 |
| TCELL28:OUT5.TMIN | GTX2.TXPLLLKDET |
| TCELL28:OUT6.TMIN | GTX2.DFETAP1MONITOR2 |
| TCELL28:OUT7.TMIN | GTX2.DFETAP1MONITOR3 |
| TCELL28:OUT8.TMIN | GTX2.DFETAP3MONITOR1 |
| TCELL28:OUT9.TMIN | GTX2.DFETAP3MONITOR2 |
| TCELL28:OUT10.TMIN | GTX2.TXRUNDISP1 |
| TCELL28:OUT11.TMIN | GTX2.TXRUNDISP2 |
| TCELL28:OUT12.TMIN | GTX2.DFETAP3MONITOR0 |
| TCELL28:OUT13.TMIN | GTX2.DFETAP3MONITOR3 |
| TCELL28:OUT14.TMIN | GTX2.TXRUNDISP0 |
| TCELL28:OUT15.TMIN | GTX2.TXRUNDISP3 |
| TCELL28:OUT18.TMIN | GTX2.COMFINISH |
| TCELL29:IMUX.CLK0 | GTX2.DCLK |
| TCELL29:IMUX.IMUX8.DELAY | GTX2.DI0 |
| TCELL29:IMUX.IMUX9.DELAY | GTX2.DI1 |
| TCELL29:IMUX.IMUX10.DELAY | GTX2.DI2 |
| TCELL29:IMUX.IMUX11.DELAY | GTX2.DI3 |
| TCELL29:IMUX.IMUX12.DELAY | GTX2.DI4 |
| TCELL29:IMUX.IMUX13.DELAY | GTX2.DI5 |
| TCELL29:IMUX.IMUX14.DELAY | GTX2.DI6 |
| TCELL29:IMUX.IMUX15.DELAY | GTX2.DI7 |
| TCELL29:IMUX.IMUX16.DELAY | GTX2.DI8 |
| TCELL29:IMUX.IMUX17.DELAY | GTX2.DI9 |
| TCELL29:IMUX.IMUX18.DELAY | GTX2.DI10 |
| TCELL29:IMUX.IMUX19.DELAY | GTX2.DI11 |
| TCELL29:IMUX.IMUX20.DELAY | GTX2.DI12 |
| TCELL29:IMUX.IMUX21.DELAY | GTX2.DI13 |
| TCELL29:IMUX.IMUX22.DELAY | GTX2.DI14 |
| TCELL29:IMUX.IMUX23.DELAY | GTX2.DI15 |
| TCELL29:IMUX.IMUX32.DELAY | GTX2.DADDR0 |
| TCELL29:IMUX.IMUX33.DELAY | GTX2.DADDR1 |
| TCELL29:IMUX.IMUX34.DELAY | GTX2.DADDR2 |
| TCELL29:IMUX.IMUX35.DELAY | GTX2.DADDR3 |
| TCELL29:IMUX.IMUX36.DELAY | GTX2.DADDR4 |
| TCELL29:IMUX.IMUX37.DELAY | GTX2.DADDR5 |
| TCELL29:IMUX.IMUX38.DELAY | GTX2.DADDR6 |
| TCELL29:IMUX.IMUX39.DELAY | GTX2.DADDR7 |
| TCELL29:OUT0.TMIN | GTX2.DRPDO7 |
| TCELL29:OUT1.TMIN | GTX2.DRPDO4 |
| TCELL29:OUT2.TMIN | GTX2.DRPDO3 |
| TCELL29:OUT3.TMIN | GTX2.DRPDO0 |
| TCELL29:OUT4.TMIN | GTX2.DRPDO6 |
| TCELL29:OUT5.TMIN | GTX2.DRPDO5 |
| TCELL29:OUT6.TMIN | GTX2.DRPDO2 |
| TCELL29:OUT7.TMIN | GTX2.DRPDO1 |
| TCELL29:OUT8.TMIN | GTX2.DRPDO14 |
| TCELL29:OUT9.TMIN | GTX2.DRPDO13 |
| TCELL29:OUT10.TMIN | GTX2.DRPDO10 |
| TCELL29:OUT11.TMIN | GTX2.DRPDO9 |
| TCELL29:OUT12.TMIN | GTX2.DRPDO15 |
| TCELL29:OUT13.TMIN | GTX2.DRPDO12 |
| TCELL29:OUT14.TMIN | GTX2.DRPDO11 |
| TCELL29:OUT15.TMIN | GTX2.DRPDO8 |
| TCELL30:IMUX.CTRL1 | GTX3.PRBSCNTRESET |
| TCELL30:IMUX.IMUX0.DELAY | GTX3.TSTIN17 |
| TCELL30:IMUX.IMUX1.DELAY | GTX3.TSTIN18 |
| TCELL30:IMUX.IMUX8.DELAY | GTX3.TSTIN9 |
| TCELL30:IMUX.IMUX9.DELAY | GTX3.TSTIN7 |
| TCELL30:IMUX.IMUX10.DELAY | GTX3.TSTIN5 |
| TCELL30:IMUX.IMUX11.DELAY | GTX3.TSTIN3 |
| TCELL30:IMUX.IMUX13.DELAY | GTX3.TSTIN12 |
| TCELL30:IMUX.IMUX14.DELAY | GTX3.TSTIN1 |
| TCELL30:IMUX.IMUX16.DELAY | GTX3.TSTIN15 |
| TCELL30:IMUX.IMUX17.DELAY | GTX3.TSTPWRDNOVRD |
| TCELL30:IMUX.IMUX18.DELAY | GTX3.TSTPWRDN1 |
| TCELL30:IMUX.IMUX19.DELAY | GTX3.TSTPWRDN3 |
| TCELL30:IMUX.IMUX21.DELAY | GTX3.TSTIN11 |
| TCELL30:IMUX.IMUX22.DELAY | GTX3.SCANIN3 |
| TCELL30:IMUX.IMUX24.DELAY | GTX3.TSTIN8 |
| TCELL30:IMUX.IMUX25.DELAY | GTX3.TSTIN6 |
| TCELL30:IMUX.IMUX26.DELAY | GTX3.TSTIN4 |
| TCELL30:IMUX.IMUX27.DELAY | GTX3.TSTIN2 |
| TCELL30:IMUX.IMUX28.DELAY | GTX3.TSTIN13 |
| TCELL30:IMUX.IMUX29.DELAY | GTX3.SCANMODEB |
| TCELL30:IMUX.IMUX30.DELAY | GTX3.TSTIN0 |
| TCELL30:IMUX.IMUX31.DELAY | GTX3.TSTIN10 |
| TCELL30:IMUX.IMUX32.DELAY | GTX3.TSTIN14 |
| TCELL30:IMUX.IMUX33.DELAY | GTX3.TSTPWRDN0 |
| TCELL30:IMUX.IMUX34.DELAY | GTX3.TSTPWRDN2 |
| TCELL30:IMUX.IMUX35.DELAY | GTX3.TSTPWRDN4 |
| TCELL30:IMUX.IMUX37.DELAY | GTX3.SCANENB |
| TCELL30:IMUX.IMUX38.DELAY | GTX3.SCANIN2 |
| TCELL30:IMUX.IMUX40.DELAY | GTX3.TSTIN16 |
| TCELL30:IMUX.IMUX41.DELAY | GTX3.TSTIN19 |
| TCELL30:OUT0.TMIN | GTX3.RXDATA18 |
| TCELL30:OUT1.TMIN | GTX3.RXDATA4 |
| TCELL30:OUT2.TMIN | GTX3.RXDATA3 |
| TCELL30:OUT3.TMIN | GTX3.RXDATA17 |
| TCELL30:OUT4.TMIN | GTX3.RXDATA0 |
| TCELL30:OUT5.TMIN | GTX3.RXDATA5 |
| TCELL30:OUT6.TMIN | GTX3.RXDATA2 |
| TCELL30:OUT7.TMIN | GTX3.RXDATA1 |
| TCELL30:OUT8.TMIN | GTX3.SCANOUT4 |
| TCELL30:OUT13.TMIN | GTX3.SCANOUT3 |
| TCELL30:OUT15.TMIN | GTX3.RXDATA16 |
| TCELL30:OUT16.TMIN | GTX3.RXDATA22 |
| TCELL30:OUT17.TMIN | GTX3.RXDATA21 |
| TCELL30:OUT18.TMIN | GTX3.RXDATA20 |
| TCELL30:OUT20.TMIN | GTX3.RXDATA23 |
| TCELL30:OUT22.TMIN | GTX3.RXDATA19 |
| TCELL30:OUT23.TMIN | GTX3.SCANOUT2 |
| TCELL31:IMUX.CTRL0 | GTX3.GTXRXRESET |
| TCELL31:IMUX.CTRL1 | GTX3.RXCDRRESET |
| TCELL31:IMUX.IMUX9.DELAY | GTX3.RXSLIDE |
| TCELL31:IMUX.IMUX11.DELAY | GTX3.RXPMASETPHASE |
| TCELL31:IMUX.IMUX12.DELAY | GTX3.RXGEARBOXSLIP |
| TCELL31:IMUX.IMUX14.DELAY | GTX3.RXEQMIX0 |
| TCELL31:IMUX.IMUX15.DELAY | GTX3.RXEQMIX1 |
| TCELL31:IMUX.IMUX18.DELAY | GTX3.RXENPRBSTST2 |
| TCELL31:IMUX.IMUX19.DELAY | GTX3.RXEQMIX9 |
| TCELL31:IMUX.IMUX20.DELAY | GTX3.RXEQMIX7 |
| TCELL31:IMUX.IMUX21.DELAY | GTX3.RXEQMIX5 |
| TCELL31:IMUX.IMUX22.DELAY | GTX3.RXEQMIX3 |
| TCELL31:IMUX.IMUX24.DELAY | GTX3.RXBUFWE |
| TCELL31:IMUX.IMUX26.DELAY | GTX3.RXPOLARITY |
| TCELL31:IMUX.IMUX27.DELAY | GTX3.RXEQMIX8 |
| TCELL31:IMUX.IMUX28.DELAY | GTX3.RXEQMIX6 |
| TCELL31:IMUX.IMUX29.DELAY | GTX3.RXEQMIX4 |
| TCELL31:IMUX.IMUX30.DELAY | GTX3.RXEQMIX2 |
| TCELL31:IMUX.IMUX32.DELAY | GTX3.RXENSAMPLEALIGN |
| TCELL31:IMUX.IMUX33.DELAY | GTX3.RXENPRBSTST0 |
| TCELL31:IMUX.IMUX34.DELAY | GTX3.RXENPRBSTST1 |
| TCELL31:IMUX.IMUX35.DELAY | GTX3.RXENPMAPHASEALIGN |
| TCELL31:IMUX.IMUX36.DELAY | GTX3.RXENMCOMMAALIGN |
| TCELL31:IMUX.IMUX37.DELAY | GTX3.RXENPCOMMAALIGN |
| TCELL31:IMUX.IMUX38.DELAY | GTX3.RXENCHANSYNC |
| TCELL31:IMUX.IMUX39.DELAY | GTX3.RXDEC8B10BUSE |
| TCELL31:OUT0.TMIN | GTX3.RXDATA24 |
| TCELL31:OUT1.TMIN | GTX3.RXDATA6 |
| TCELL31:OUT2.TMIN | GTX3.RXDATA11 |
| TCELL31:OUT3.TMIN | GTX3.RXDATA31 |
| TCELL31:OUT4.TMIN | GTX3.RXDATA8 |
| TCELL31:OUT5.TMIN | GTX3.RXDATA7 |
| TCELL31:OUT6.TMIN | GTX3.RXDATA10 |
| TCELL31:OUT7.TMIN | GTX3.RXDATA9 |
| TCELL31:OUT8.TMIN | GTX3.TSTOUT8 |
| TCELL31:OUT9.TMIN | GTX3.RXDATA27 |
| TCELL31:OUT10.TMIN | GTX3.TSTOUT2 |
| TCELL31:OUT11.TMIN | GTX3.RXDATA29 |
| TCELL31:OUT12.TMIN | GTX3.TSTOUT9 |
| TCELL31:OUT13.TMIN | GTX3.TSTOUT6 |
| TCELL31:OUT14.TMIN | GTX3.TSTOUT4 |
| TCELL31:OUT15.TMIN | GTX3.RXDATA30 |
| TCELL31:OUT16.TMIN | GTX3.RXDATA28 |
| TCELL31:OUT17.TMIN | GTX3.TSTOUT1 |
| TCELL31:OUT18.TMIN | GTX3.RXDATA26 |
| TCELL31:OUT19.TMIN | GTX3.TSTOUT7 |
| TCELL31:OUT20.TMIN | GTX3.TSTOUT3 |
| TCELL31:OUT21.TMIN | GTX3.TSTOUT0 |
| TCELL31:OUT22.TMIN | GTX3.RXDATA25 |
| TCELL31:OUT23.TMIN | GTX3.TSTOUT5 |
| TCELL32:IMUX.CLK0 | GTX3.RXUSRCLK |
| TCELL32:IMUX.CLK1 | GTX3.RXUSRCLK2 |
| TCELL32:IMUX.CTRL0 | GTX3.RXBUFRESET |
| TCELL32:IMUX.CTRL1 | GTX3.RXRESET |
| TCELL32:IMUX.IMUX8.DELAY | GTX3.RXCHBONDSLAVE |
| TCELL32:IMUX.IMUX10.DELAY | GTX3.RXCHBONDLEVEL0 |
| TCELL32:IMUX.IMUX11.DELAY | GTX3.RXCHBONDLEVEL2 |
| TCELL32:IMUX.IMUX14.DELAY | GTX3.USRCODEERR |
| TCELL32:IMUX.IMUX18.DELAY | GTX3.CLKTESTSIG1 |
| TCELL32:IMUX.IMUX19.DELAY | GTX3.CLKTESTSIG0 |
| TCELL32:IMUX.IMUX20.DELAY | GTX3.RXPLLLKDETEN |
| TCELL32:IMUX.IMUX21.DELAY | GTX3.RXPLLPOWERDOWN |
| TCELL32:IMUX.IMUX24.DELAY | GTX3.RXCHBONDMASTER |
| TCELL32:IMUX.IMUX26.DELAY | GTX3.RXCHBONDLEVEL1 |
| TCELL32:IMUX.IMUX27.DELAY | GTX3.GTXTEST12 |
| TCELL32:IMUX.IMUX28.DELAY | GTX3.GTXTEST11 |
| TCELL32:IMUX.IMUX29.DELAY | GTX3.GTXTEST10 |
| TCELL32:IMUX.IMUX30.DELAY | GTX3.GTXTEST9 |
| TCELL32:IMUX.IMUX31.DELAY | GTX3.GTXTEST8 |
| TCELL32:IMUX.IMUX32.DELAY | GTX3.GTXTEST7 |
| TCELL32:IMUX.IMUX33.DELAY | GTX3.GTXTEST6 |
| TCELL32:IMUX.IMUX34.DELAY | GTX3.GTXTEST5 |
| TCELL32:IMUX.IMUX35.DELAY | GTX3.GTXTEST4 |
| TCELL32:IMUX.IMUX36.DELAY | GTX3.GTXTEST3 |
| TCELL32:IMUX.IMUX37.DELAY | GTX3.GTXTEST2 |
| TCELL32:IMUX.IMUX38.DELAY | GTX3.GTXTEST1 |
| TCELL32:IMUX.IMUX39.DELAY | GTX3.GTXTEST0 |
| TCELL32:OUT0.TMIN | GTX3.RXLOSSOFSYNC0 |
| TCELL32:OUT1.TMIN | GTX3.RXDATA15 |
| TCELL32:OUT2.TMIN | GTX3.RXDATA14 |
| TCELL32:OUT3.TMIN | GTX3.RXCHARISK3 |
| TCELL32:OUT4.TMIN | GTX3.RXDATAVALID |
| TCELL32:OUT5.TMIN | GTX3.RXCHARISK1 |
| TCELL32:OUT6.TMIN | GTX3.RXDATA13 |
| TCELL32:OUT7.TMIN | GTX3.RXDATA12 |
| TCELL32:OUT8.TMIN | GTX3.RXCHARISCOMMA2 |
| TCELL32:OUT10.TMIN | GTX3.RXBYTEREALIGN |
| TCELL32:OUT13.TMIN | GTX3.RXBYTEISALIGNED |
| TCELL32:OUT14.TMIN | GTX3.RXCHANREALIGN |
| TCELL32:OUT15.TMIN | GTX3.RXCHARISK2 |
| TCELL32:OUT18.TMIN | GTX3.RXCHARISCOMMA3 |
| TCELL32:OUT19.TMIN | GTX3.COMSASDET |
| TCELL32:OUT20.TMIN | GTX3.COMINITDET |
| TCELL32:OUT22.TMIN | GTX3.RXLOSSOFSYNC1 |
| TCELL32:OUT23.TMIN | GTX3.COMWAKEDET |
| TCELL33:IMUX.CLK0 | GTX3.GREFCLKRX |
| TCELL33:IMUX.CLK1 | GTX3.TSTCLK0 |
| TCELL33:IMUX.CTRL0 | GTX3.PLLRXRESET |
| TCELL33:IMUX.IMUX0.DELAY | GTX3.TXBUFDIFFCTRL0 |
| TCELL33:IMUX.IMUX3.DELAY | GTX3.TXDEEMPH |
| TCELL33:IMUX.IMUX5.DELAY | GTX3.TXDIFFCTRL2 |
| TCELL33:IMUX.IMUX9.DELAY | GTX3.TXPREEMPHASIS3 |
| TCELL33:IMUX.IMUX11.DELAY | GTX3.LOOPBACK1 |
| TCELL33:IMUX.IMUX12.DELAY | GTX3.RXDLYALIGNTESTMODEENB |
| TCELL33:IMUX.IMUX13.DELAY | GTX3.TXSWING |
| TCELL33:IMUX.IMUX16.DELAY | GTX3.TXBUFDIFFCTRL1 |
| TCELL33:IMUX.IMUX17.DELAY | GTX3.TXPREEMPHASIS2 |
| TCELL33:IMUX.IMUX18.DELAY | GTX3.TXBUFDIFFCTRL2 |
| TCELL33:IMUX.IMUX19.DELAY | GTX3.TXPREEMPHASIS1 |
| TCELL33:IMUX.IMUX21.DELAY | GTX3.TXDIFFCTRL0 |
| TCELL33:IMUX.IMUX22.DELAY | GTX3.RXPLLREFSELDY1 |
| TCELL33:IMUX.IMUX24.DELAY | GTX3.LOOPBACK0 |
| TCELL33:IMUX.IMUX25.DELAY | GTX3.RXDLYALIGNFORCEROTATEB |
| TCELL33:IMUX.IMUX26.DELAY | GTX3.TXPREEMPHASIS0 |
| TCELL33:IMUX.IMUX27.DELAY | GTX3.LOOPBACK2 |
| TCELL33:IMUX.IMUX28.DELAY | GTX3.RXDLYALIGNMONENB |
| TCELL33:IMUX.IMUX29.DELAY | GTX3.RXDLYALIGNSWPPRECURB |
| TCELL33:IMUX.IMUX30.DELAY | GTX3.TXDIFFCTRL3 |
| TCELL33:IMUX.IMUX32.DELAY | GTX3.RXCHBONDI0 |
| TCELL33:IMUX.IMUX33.DELAY | GTX3.RXCHBONDI1 |
| TCELL33:IMUX.IMUX34.DELAY | GTX3.RXCHBONDI2 |
| TCELL33:IMUX.IMUX35.DELAY | GTX3.RXCHBONDI3 |
| TCELL33:IMUX.IMUX36.DELAY | GTX3.RXCOMMADETUSE |
| TCELL33:IMUX.IMUX37.DELAY | GTX3.RXPLLREFSELDY0 |
| TCELL33:IMUX.IMUX38.DELAY | GTX3.TXDIFFCTRL1 |
| TCELL33:IMUX.IMUX39.DELAY | GTX3.RXPLLREFSELDY2 |
| TCELL33:OUT0.TMIN | GTX3.RXDISPERR2 |
| TCELL33:OUT1.TMIN | GTX3.RXRUNDISP3 |
| TCELL33:OUT2.TMIN | GTX3.RXCHARISCOMMA1 |
| TCELL33:OUT3.TMIN | GTX3.RXNOTINTABLE3 |
| TCELL33:OUT4.TMIN | GTX3.RXDISPERR0 |
| TCELL33:OUT5.TMIN | GTX3.RXRUNDISP1 |
| TCELL33:OUT7.TMIN | GTX3.RXNOTINTABLE1 |
| TCELL33:OUT8.TMIN | GTX3.RXDISPERR1 |
| TCELL33:OUT9.TMIN | GTX3.RXRUNDISP0 |
| TCELL33:OUT11.TMIN | GTX3.RXNOTINTABLE0 |
| TCELL33:OUT13.TMIN | GTX3.RXCHANISALIGNED |
| TCELL33:OUT14.TMIN | GTX3.RXCHARISCOMMA0 |
| TCELL33:OUT15.TMIN | GTX3.RXNOTINTABLE2 |
| TCELL33:OUT16.TMIN | GTX3.RXCHARISK0 |
| TCELL33:OUT19.TMIN | GTX3.RXRUNDISP2 |
| TCELL33:OUT22.TMIN | GTX3.RXDISPERR3 |
| TCELL34:IMUX.CLK1 | GTX3.SCANCLK |
| TCELL34:IMUX.IMUX8.DELAY | GTX3.DFETAP10 |
| TCELL34:IMUX.IMUX9.DELAY | GTX3.TXDETECTRX |
| TCELL34:IMUX.IMUX10.DELAY | GTX3.DFETAP11 |
| TCELL34:IMUX.IMUX11.DELAY | GTX3.TXMARGIN0 |
| TCELL34:IMUX.IMUX13.DELAY | GTX3.RXPOWERDOWN0 |
| TCELL34:IMUX.IMUX14.DELAY | GTX3.DFETAP12 |
| TCELL34:IMUX.IMUX15.DELAY | GTX3.DFETAP13 |
| TCELL34:IMUX.IMUX16.DELAY | GTX3.DFECLKDLYADJ5 |
| TCELL34:IMUX.IMUX17.DELAY | GTX3.DFECLKDLYADJ4 |
| TCELL34:IMUX.IMUX18.DELAY | GTX3.DFECLKDLYADJ2 |
| TCELL34:IMUX.IMUX19.DELAY | GTX3.DFECLKDLYADJ1 |
| TCELL34:IMUX.IMUX21.DELAY | GTX3.RXPOWERDOWN1 |
| TCELL34:IMUX.IMUX24.DELAY | GTX3.DFETAP20 |
| TCELL34:IMUX.IMUX25.DELAY | GTX3.DFETAP21 |
| TCELL34:IMUX.IMUX26.DELAY | GTX3.TXMARGIN1 |
| TCELL34:IMUX.IMUX28.DELAY | GTX3.TXPOWERDOWN0 |
| TCELL34:IMUX.IMUX29.DELAY | GTX3.DFEDLYOVRD |
| TCELL34:IMUX.IMUX30.DELAY | GTX3.DFETAP22 |
| TCELL34:IMUX.IMUX31.DELAY | GTX3.DFETAP23 |
| TCELL34:IMUX.IMUX32.DELAY | GTX3.TXELECIDLE |
| TCELL34:IMUX.IMUX33.DELAY | GTX3.DFECLKDLYADJ3 |
| TCELL34:IMUX.IMUX35.DELAY | GTX3.DFECLKDLYADJ0 |
| TCELL34:IMUX.IMUX36.DELAY | GTX3.TXPOWERDOWN1 |
| TCELL34:IMUX.IMUX37.DELAY | GTX3.DFETAPOVRD |
| TCELL34:IMUX.IMUX38.DELAY | GTX3.DFETAP14 |
| TCELL34:IMUX.IMUX39.DELAY | GTX3.DFETAP24 |
| TCELL34:OUT0.TMIN | GTX3.MGTREFCLKFAB0 |
| TCELL34:OUT3.TMIN | GTX3.RXBUFSTATUS2 |
| TCELL34:OUT4.TMIN | GTX3.SCANOUT1 |
| TCELL34:OUT5.TMIN | GTX3.RXPLLLKDET |
| TCELL34:OUT6.TMIN | GTX3.RXBUFSTATUS0 |
| TCELL34:OUT7.TMIN | GTX3.RXBUFSTATUS1 |
| TCELL34:OUT8.TMIN | GTX3.PHYSTATUS |
| TCELL34:OUT10.TMIN | GTX3.RXCHBONDO1 |
| TCELL34:OUT11.TMIN | GTX3.RXCHBONDO2 |
| TCELL34:OUT12.TMIN | GTX3.MGTREFCLKFAB1 |
| TCELL34:OUT13.TMIN | GTX3.RXSTATUS2 |
| TCELL34:OUT14.TMIN | GTX3.RXSTATUS0 |
| TCELL34:OUT15.TMIN | GTX3.RXCHBONDO3 |
| TCELL34:OUT16.TMIN | GTX3.RXSTATUS1 |
| TCELL34:OUT17.TMIN | GTX3.RXCHBONDO0 |
| TCELL34:OUT18.TMIN | GTX3.SCANOUT0 |
| TCELL34:OUT22.TMIN | GTX3.RXOVERSAMPLEERR |
| TCELL35:IMUX.CLK1 | GTX3.TSTCLK1 |
| TCELL35:IMUX.CTRL1 | GTX3.PLLTXRESET |
| TCELL35:IMUX.IMUX2.DELAY | GTX3.TXDLYALIGNUPDSW |
| TCELL35:IMUX.IMUX8.DELAY | GTX3.TXHEADER0 |
| TCELL35:IMUX.IMUX9.DELAY | GTX3.TXPOLARITY |
| TCELL35:IMUX.IMUX10.DELAY | GTX3.RXDLYALIGNUPDSW |
| TCELL35:IMUX.IMUX11.DELAY | GTX3.TXBYPASS8B10B0 |
| TCELL35:IMUX.IMUX13.DELAY | GTX3.TXDLYALIGNRESET |
| TCELL35:IMUX.IMUX14.DELAY | GTX3.RXDLYALIGNDISABLE |
| TCELL35:IMUX.IMUX15.DELAY | GTX3.TXMARGIN2 |
| TCELL35:IMUX.IMUX16.DELAY | GTX3.TXHEADER1 |
| TCELL35:IMUX.IMUX17.DELAY | GTX3.TXINHIBIT |
| TCELL35:IMUX.IMUX18.DELAY | GTX3.TXPMASETPHASE |
| TCELL35:IMUX.IMUX19.DELAY | GTX3.TXBYPASS8B10B3 |
| TCELL35:IMUX.IMUX21.DELAY | GTX3.TXCHARDISPMODE3 |
| TCELL35:IMUX.IMUX22.DELAY | GTX3.TXCHARDISPVAL3 |
| TCELL35:IMUX.IMUX23.DELAY | GTX3.TXCHARISK3 |
| TCELL35:IMUX.IMUX25.DELAY | GTX3.TXDLYALIGNOVERRIDE |
| TCELL35:IMUX.IMUX26.DELAY | GTX3.TXCHARISK0 |
| TCELL35:IMUX.IMUX27.DELAY | GTX3.TXBYPASS8B10B1 |
| TCELL35:IMUX.IMUX28.DELAY | GTX3.TXCHARDISPMODE1 |
| TCELL35:IMUX.IMUX29.DELAY | GTX3.RXDLYALIGNRESET |
| TCELL35:IMUX.IMUX30.DELAY | GTX3.TXCHARDISPVAL1 |
| TCELL35:IMUX.IMUX32.DELAY | GTX3.TXHEADER2 |
| TCELL35:IMUX.IMUX33.DELAY | GTX3.RXDLYALIGNOVERRIDE |
| TCELL35:IMUX.IMUX34.DELAY | GTX3.TXCHARDISPMODE0 |
| TCELL35:IMUX.IMUX35.DELAY | GTX3.TXBYPASS8B10B2 |
| TCELL35:IMUX.IMUX36.DELAY | GTX3.TXCHARISK1 |
| TCELL35:IMUX.IMUX37.DELAY | GTX3.TXCHARDISPMODE2 |
| TCELL35:IMUX.IMUX38.DELAY | GTX3.TXCHARDISPVAL2 |
| TCELL35:IMUX.IMUX39.DELAY | GTX3.TXCHARISK2 |
| TCELL35:IMUX.IMUX44.DELAY | GTX3.TXCHARDISPVAL0 |
| TCELL35:IMUX.IMUX46.DELAY | GTX3.TXDLYALIGNDISABLE |
| TCELL35:OUT0.TMIN | GTX3.RXDLYALIGNMONITOR7 |
| TCELL35:OUT1.TMIN | GTX3.RXSTARTOFSEQ |
| TCELL35:OUT2.TMIN | GTX3.RXPRBSERR |
| TCELL35:OUT3.TMIN | GTX3.RXELECIDLE |
| TCELL35:OUT4.TMIN | GTX3.RXVALID |
| TCELL35:OUT5.TMIN | GTX3.RXRECCLKPCS |
| TCELL35:OUT6.TMIN | GTX3.RXCLKCORCNT2 |
| TCELL35:OUT7.TMIN | GTX3.RXDLYALIGNMONITOR2 |
| TCELL35:OUT8.TMIN | GTX3.RXCLKCORCNT0 |
| TCELL35:OUT9.TMIN | GTX3.RXCLKCORCNT1 |
| TCELL35:OUT10.TMIN | GTX3.RXHEADER0 |
| TCELL35:OUT11.TMIN | GTX3.RXHEADERVALID |
| TCELL35:OUT12.TMIN | GTX3.RXCOMMADET |
| TCELL35:OUT14.TMIN | GTX3.RXCHANBONDSEQ |
| TCELL35:OUT15.TMIN | GTX3.RXDLYALIGNMONITOR1 |
| TCELL35:OUT16.TMIN | GTX3.RXHEADER1 |
| TCELL35:OUT17.TMIN | GTX3.RXHEADER2 |
| TCELL35:OUT18.TMIN | GTX3.RXDLYALIGNMONITOR6 |
| TCELL35:OUT19.TMIN | GTX3.RXDLYALIGNMONITOR5 |
| TCELL35:OUT20.TMIN | GTX3.RXDLYALIGNMONITOR3 |
| TCELL35:OUT21.TMIN | GTX3.RXDLYALIGNMONITOR0 |
| TCELL35:OUT22.TMIN | GTX3.RXRESETDONE |
| TCELL35:OUT23.TMIN | GTX3.RXDLYALIGNMONITOR4 |
| TCELL36:IMUX.CLK0 | GTX3.TXUSRCLK |
| TCELL36:IMUX.CLK1 | GTX3.TXUSRCLK2 |
| TCELL36:IMUX.CTRL0 | GTX3.TXRESET |
| TCELL36:IMUX.CTRL1 | GTX3.GTXTXRESET |
| TCELL36:IMUX.IMUX3.DELAY | GTX3.TXDATA12 |
| TCELL36:IMUX.IMUX5.DELAY | GTX3.TXDATA14 |
| TCELL36:IMUX.IMUX8.DELAY | GTX3.TXSEQUENCE3 |
| TCELL36:IMUX.IMUX9.DELAY | GTX3.DFETAP31 |
| TCELL36:IMUX.IMUX10.DELAY | GTX3.DFETAP30 |
| TCELL36:IMUX.IMUX11.DELAY | GTX3.TXSEQUENCE0 |
| TCELL36:IMUX.IMUX12.DELAY | GTX3.DFETAP32 |
| TCELL36:IMUX.IMUX13.DELAY | GTX3.TXDATA15 |
| TCELL36:IMUX.IMUX15.DELAY | GTX3.TXENPRBSTST2 |
| TCELL36:IMUX.IMUX17.DELAY | GTX3.DFETAP33 |
| TCELL36:IMUX.IMUX19.DELAY | GTX3.TXSEQUENCE1 |
| TCELL36:IMUX.IMUX20.DELAY | GTX3.DFETAP43 |
| TCELL36:IMUX.IMUX22.DELAY | GTX3.TXSEQUENCE5 |
| TCELL36:IMUX.IMUX23.DELAY | GTX3.TXENPRBSTST1 |
| TCELL36:IMUX.IMUX24.DELAY | GTX3.TXSEQUENCE4 |
| TCELL36:IMUX.IMUX25.DELAY | GTX3.DFETAP41 |
| TCELL36:IMUX.IMUX26.DELAY | GTX3.DFETAP40 |
| TCELL36:IMUX.IMUX28.DELAY | GTX3.DFETAP42 |
| TCELL36:IMUX.IMUX30.DELAY | GTX3.TXDATA13 |
| TCELL36:IMUX.IMUX32.DELAY | GTX3.GATERXELECIDLE |
| TCELL36:IMUX.IMUX33.DELAY | GTX3.TXRATE1 |
| TCELL36:IMUX.IMUX34.DELAY | GTX3.TXRATE0 |
| TCELL36:IMUX.IMUX35.DELAY | GTX3.TXSEQUENCE2 |
| TCELL36:IMUX.IMUX37.DELAY | GTX3.IGNORESIGDET |
| TCELL36:IMUX.IMUX38.DELAY | GTX3.TXSEQUENCE6 |
| TCELL36:IMUX.IMUX39.DELAY | GTX3.TXENPRBSTST0 |
| TCELL36:IMUX.IMUX41.DELAY | GTX3.RXRATE1 |
| TCELL36:IMUX.IMUX42.DELAY | GTX3.RXRATE0 |
| TCELL36:OUT1.TMIN | GTX3.DFECLKDLYADJMON1 |
| TCELL36:OUT2.TMIN | GTX3.DFECLKDLYADJMON2 |
| TCELL36:OUT3.TMIN | GTX3.DFECLKDLYADJMON5 |
| TCELL36:OUT4.TMIN | GTX3.TXGEARBOXREADY |
| TCELL36:OUT5.TMIN | GTX3.DFECLKDLYADJMON0 |
| TCELL36:OUT6.TMIN | GTX3.DFECLKDLYADJMON3 |
| TCELL36:OUT7.TMIN | GTX3.DFECLKDLYADJMON4 |
| TCELL36:OUT8.TMIN | GTX3.TXOUTCLKPCS |
| TCELL36:OUT10.TMIN | GTX3.DFEEYEDACMON2 |
| TCELL36:OUT11.TMIN | GTX3.DFEEYEDACMON3 |
| TCELL36:OUT13.TMIN | GTX3.DFEEYEDACMON0 |
| TCELL36:OUT14.TMIN | GTX3.DFEEYEDACMON1 |
| TCELL36:OUT15.TMIN | GTX3.DFEEYEDACMON4 |
| TCELL36:OUT18.TMIN | GTX3.DFESENSCAL1 |
| TCELL36:OUT19.TMIN | GTX3.DFESENSCAL0 |
| TCELL36:OUT20.TMIN | GTX3.RXRATEDONE |
| TCELL36:OUT22.TMIN | GTX3.DFESENSCAL2 |
| TCELL36:OUT23.TMIN | GTX3.TXRATEDONE |
| TCELL37:IMUX.CLK0 | GTX3.GREFCLKTX |
| TCELL37:IMUX.IMUX9.DELAY | GTX3.TXDLYALIGNFORCEROTATEB |
| TCELL37:IMUX.IMUX10.DELAY | GTX3.TXCOMWAKE |
| TCELL37:IMUX.IMUX11.DELAY | GTX3.TXDLYALIGNMONENB |
| TCELL37:IMUX.IMUX12.DELAY | GTX3.TXPLLLKDETEN |
| TCELL37:IMUX.IMUX13.DELAY | GTX3.TXDATA10 |
| TCELL37:IMUX.IMUX14.DELAY | GTX3.TXSTARTSEQ |
| TCELL37:IMUX.IMUX15.DELAY | GTX3.TXDATA8 |
| TCELL37:IMUX.IMUX18.DELAY | GTX3.TXCOMINIT |
| TCELL37:IMUX.IMUX19.DELAY | GTX3.TXCOMSAS |
| TCELL37:IMUX.IMUX21.DELAY | GTX3.TXDATA9 |
| TCELL37:IMUX.IMUX22.DELAY | GTX3.TXENC8B10BUSE |
| TCELL37:IMUX.IMUX24.DELAY | GTX3.TXDATA23 |
| TCELL37:IMUX.IMUX25.DELAY | GTX3.TXDATA22 |
| TCELL37:IMUX.IMUX26.DELAY | GTX3.TXDATA7 |
| TCELL37:IMUX.IMUX27.DELAY | GTX3.TXDATA20 |
| TCELL37:IMUX.IMUX28.DELAY | GTX3.TXDATA21 |
| TCELL37:IMUX.IMUX29.DELAY | GTX3.TXPLLPOWERDOWN |
| TCELL37:IMUX.IMUX30.DELAY | GTX3.TXDLYALIGNTESTMODEENB |
| TCELL37:IMUX.IMUX32.DELAY | GTX3.TXDATA31 |
| TCELL37:IMUX.IMUX33.DELAY | GTX3.TXDATA30 |
| TCELL37:IMUX.IMUX34.DELAY | GTX3.TXDATA6 |
| TCELL37:IMUX.IMUX35.DELAY | GTX3.TXDATA28 |
| TCELL37:IMUX.IMUX36.DELAY | GTX3.TXDATA29 |
| TCELL37:IMUX.IMUX37.DELAY | GTX3.TXPLLREFSELDY0 |
| TCELL37:IMUX.IMUX38.DELAY | GTX3.TXPLLREFSELDY1 |
| TCELL37:IMUX.IMUX39.DELAY | GTX3.TXPLLREFSELDY2 |
| TCELL37:IMUX.IMUX40.DELAY | GTX3.TXDATA11 |
| TCELL37:OUT0.TMIN | GTX3.TXDLYALIGNMONITOR7 |
| TCELL37:OUT1.TMIN | GTX3.DFETAP2MONITOR0 |
| TCELL37:OUT2.TMIN | GTX3.DFETAP2MONITOR1 |
| TCELL37:OUT3.TMIN | GTX3.DFETAP2MONITOR4 |
| TCELL37:OUT4.TMIN | GTX3.TXDLYALIGNMONITOR2 |
| TCELL37:OUT5.TMIN | GTX3.TXBUFSTATUS0 |
| TCELL37:OUT6.TMIN | GTX3.DFETAP2MONITOR2 |
| TCELL37:OUT7.TMIN | GTX3.DFETAP2MONITOR3 |
| TCELL37:OUT8.TMIN | GTX3.DFETAP4MONITOR1 |
| TCELL37:OUT9.TMIN | GTX3.DFETAP4MONITOR2 |
| TCELL37:OUT10.TMIN | GTX3.TXKERR1 |
| TCELL37:OUT11.TMIN | GTX3.TXKERR2 |
| TCELL37:OUT12.TMIN | GTX3.DFETAP4MONITOR0 |
| TCELL37:OUT13.TMIN | GTX3.DFETAP4MONITOR3 |
| TCELL37:OUT14.TMIN | GTX3.TXKERR0 |
| TCELL37:OUT15.TMIN | GTX3.TXKERR3 |
| TCELL37:OUT16.TMIN | GTX3.TXDLYALIGNMONITOR1 |
| TCELL37:OUT17.TMIN | GTX3.TXBUFSTATUS1 |
| TCELL37:OUT18.TMIN | GTX3.TXDLYALIGNMONITOR6 |
| TCELL37:OUT19.TMIN | GTX3.TXDLYALIGNMONITOR5 |
| TCELL37:OUT20.TMIN | GTX3.TXDLYALIGNMONITOR3 |
| TCELL37:OUT21.TMIN | GTX3.TXDLYALIGNMONITOR0 |
| TCELL37:OUT22.TMIN | GTX3.TXRESETDONE |
| TCELL37:OUT23.TMIN | GTX3.TXDLYALIGNMONITOR4 |
| TCELL38:IMUX.IMUX8.DELAY | GTX3.DWE |
| TCELL38:IMUX.IMUX9.DELAY | GTX3.SCANIN4 |
| TCELL38:IMUX.IMUX10.DELAY | GTX3.TXPOSTEMPHASIS0 |
| TCELL38:IMUX.IMUX12.DELAY | GTX3.TXPOSTEMPHASIS2 |
| TCELL38:IMUX.IMUX13.DELAY | GTX3.TXPRBSFORCEERR |
| TCELL38:IMUX.IMUX15.DELAY | GTX3.TXPDOWNASYNCH |
| TCELL38:IMUX.IMUX16.DELAY | GTX3.DEN |
| TCELL38:IMUX.IMUX17.DELAY | GTX3.TXENPMAPHASEALIGN |
| TCELL38:IMUX.IMUX18.DELAY | GTX3.TXPOSTEMPHASIS1 |
| TCELL38:IMUX.IMUX19.DELAY | GTX3.TXDATA25 |
| TCELL38:IMUX.IMUX20.DELAY | GTX3.TXPOSTEMPHASIS3 |
| TCELL38:IMUX.IMUX22.DELAY | GTX3.TXPOSTEMPHASIS4 |
| TCELL38:IMUX.IMUX25.DELAY | GTX3.SCANIN1 |
| TCELL38:IMUX.IMUX26.DELAY | GTX3.TXDATA4 |
| TCELL38:IMUX.IMUX27.DELAY | GTX3.TXDATA19 |
| TCELL38:IMUX.IMUX28.DELAY | GTX3.TXDATA2 |
| TCELL38:IMUX.IMUX29.DELAY | GTX3.TXDATA18 |
| TCELL38:IMUX.IMUX30.DELAY | GTX3.TXDATA17 |
| TCELL38:IMUX.IMUX31.DELAY | GTX3.TXDATA16 |
| TCELL38:IMUX.IMUX32.DELAY | GTX3.TXDATA3 |
| TCELL38:IMUX.IMUX33.DELAY | GTX3.SCANIN0 |
| TCELL38:IMUX.IMUX34.DELAY | GTX3.TXDATA5 |
| TCELL38:IMUX.IMUX35.DELAY | GTX3.TXDATA27 |
| TCELL38:IMUX.IMUX36.DELAY | GTX3.TXDATA1 |
| TCELL38:IMUX.IMUX37.DELAY | GTX3.TXDATA26 |
| TCELL38:IMUX.IMUX38.DELAY | GTX3.TXDATA0 |
| TCELL38:IMUX.IMUX39.DELAY | GTX3.TXDATA24 |
| TCELL38:OUT0.TMIN | GTX3.DRDY |
| TCELL38:OUT1.TMIN | GTX3.DFETAP1MONITOR0 |
| TCELL38:OUT2.TMIN | GTX3.DFETAP1MONITOR1 |
| TCELL38:OUT3.TMIN | GTX3.DFETAP1MONITOR4 |
| TCELL38:OUT5.TMIN | GTX3.TXPLLLKDET |
| TCELL38:OUT6.TMIN | GTX3.DFETAP1MONITOR2 |
| TCELL38:OUT7.TMIN | GTX3.DFETAP1MONITOR3 |
| TCELL38:OUT8.TMIN | GTX3.DFETAP3MONITOR1 |
| TCELL38:OUT9.TMIN | GTX3.DFETAP3MONITOR2 |
| TCELL38:OUT10.TMIN | GTX3.TXRUNDISP1 |
| TCELL38:OUT11.TMIN | GTX3.TXRUNDISP2 |
| TCELL38:OUT12.TMIN | GTX3.DFETAP3MONITOR0 |
| TCELL38:OUT13.TMIN | GTX3.DFETAP3MONITOR3 |
| TCELL38:OUT14.TMIN | GTX3.TXRUNDISP0 |
| TCELL38:OUT15.TMIN | GTX3.TXRUNDISP3 |
| TCELL38:OUT18.TMIN | GTX3.COMFINISH |
| TCELL39:IMUX.CLK0 | GTX3.DCLK |
| TCELL39:IMUX.IMUX8.DELAY | GTX3.DI0 |
| TCELL39:IMUX.IMUX9.DELAY | GTX3.DI1 |
| TCELL39:IMUX.IMUX10.DELAY | GTX3.DI2 |
| TCELL39:IMUX.IMUX11.DELAY | GTX3.DI3 |
| TCELL39:IMUX.IMUX12.DELAY | GTX3.DI4 |
| TCELL39:IMUX.IMUX13.DELAY | GTX3.DI5 |
| TCELL39:IMUX.IMUX14.DELAY | GTX3.DI6 |
| TCELL39:IMUX.IMUX15.DELAY | GTX3.DI7 |
| TCELL39:IMUX.IMUX16.DELAY | GTX3.DI8 |
| TCELL39:IMUX.IMUX17.DELAY | GTX3.DI9 |
| TCELL39:IMUX.IMUX18.DELAY | GTX3.DI10 |
| TCELL39:IMUX.IMUX19.DELAY | GTX3.DI11 |
| TCELL39:IMUX.IMUX20.DELAY | GTX3.DI12 |
| TCELL39:IMUX.IMUX21.DELAY | GTX3.DI13 |
| TCELL39:IMUX.IMUX22.DELAY | GTX3.DI14 |
| TCELL39:IMUX.IMUX23.DELAY | GTX3.DI15 |
| TCELL39:IMUX.IMUX32.DELAY | GTX3.DADDR0 |
| TCELL39:IMUX.IMUX33.DELAY | GTX3.DADDR1 |
| TCELL39:IMUX.IMUX34.DELAY | GTX3.DADDR2 |
| TCELL39:IMUX.IMUX35.DELAY | GTX3.DADDR3 |
| TCELL39:IMUX.IMUX36.DELAY | GTX3.DADDR4 |
| TCELL39:IMUX.IMUX37.DELAY | GTX3.DADDR5 |
| TCELL39:IMUX.IMUX38.DELAY | GTX3.DADDR6 |
| TCELL39:IMUX.IMUX39.DELAY | GTX3.DADDR7 |
| TCELL39:OUT0.TMIN | GTX3.DRPDO7 |
| TCELL39:OUT1.TMIN | GTX3.DRPDO4 |
| TCELL39:OUT2.TMIN | GTX3.DRPDO3 |
| TCELL39:OUT3.TMIN | GTX3.DRPDO0 |
| TCELL39:OUT4.TMIN | GTX3.DRPDO6 |
| TCELL39:OUT5.TMIN | GTX3.DRPDO5 |
| TCELL39:OUT6.TMIN | GTX3.DRPDO2 |
| TCELL39:OUT7.TMIN | GTX3.DRPDO1 |
| TCELL39:OUT8.TMIN | GTX3.DRPDO14 |
| TCELL39:OUT9.TMIN | GTX3.DRPDO13 |
| TCELL39:OUT10.TMIN | GTX3.DRPDO10 |
| TCELL39:OUT11.TMIN | GTX3.DRPDO9 |
| TCELL39:OUT12.TMIN | GTX3.DRPDO15 |
| TCELL39:OUT13.TMIN | GTX3.DRPDO12 |
| TCELL39:OUT14.TMIN | GTX3.DRPDO11 |
| TCELL39:OUT15.TMIN | GTX3.DRPDO8 |
Bitstream
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP37[14] GTX0:PMA_TX_CFG[14] | GTX0:DRP37[15] GTX0:PMA_TX_CFG[15] |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP37[12] GTX0:PMA_TX_CFG[12] | GTX0:DRP37[13] GTX0:PMA_TX_CFG[13] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP37[10] GTX0:PMA_TX_CFG[10] | GTX0:DRP37[11] GTX0:PMA_TX_CFG[11] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP37[8] GTX0:PMA_TX_CFG[8] | GTX0:DRP37[9] GTX0:PMA_TX_CFG[9] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP37[6] GTX0:PMA_TX_CFG[6] | GTX0:DRP37[7] GTX0:PMA_TX_CFG[7] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP37[4] GTX0:PMA_TX_CFG[4] | GTX0:DRP37[5] GTX0:PMA_TX_CFG[5] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP37[2] GTX0:PMA_TX_CFG[2] | GTX0:DRP37[3] GTX0:PMA_TX_CFG[3] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP37[0] GTX0:PMA_TX_CFG[0] | GTX0:DRP37[1] GTX0:PMA_TX_CFG[1] |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP36[14] GTX0:PMA_CFG[74] | GTX0:DRP36[15] GTX0:PMA_CFG[75] |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP36[12] GTX0:PMA_CFG[72] | GTX0:DRP36[13] GTX0:PMA_CFG[73] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP36[10] GTX0:PMA_CFG[70] | GTX0:DRP36[11] GTX0:PMA_CFG[71] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP36[8] GTX0:PMA_CFG[68] | GTX0:DRP36[9] GTX0:PMA_CFG[69] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP36[6] GTX0:PMA_CFG[66] | GTX0:DRP36[7] GTX0:PMA_CFG[67] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP36[4] GTX0:PMA_CFG[64] | GTX0:DRP36[5] GTX0:PMA_CFG[65] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP36[2] GTX0:PMA_TX_CFG[18] | GTX0:DRP36[3] GTX0:PMA_TX_CFG[19] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP36[0] GTX0:PMA_TX_CFG[16] | GTX0:DRP36[1] GTX0:PMA_TX_CFG[17] |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP35[14] GTX0:PMA_CFG[62] | GTX0:DRP35[15] GTX0:PMA_CFG[63] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP35[12] GTX0:PMA_CFG[60] | GTX0:DRP35[13] GTX0:PMA_CFG[61] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP35[10] GTX0:PMA_CFG[58] | GTX0:DRP35[11] GTX0:PMA_CFG[59] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP35[8] GTX0:PMA_CFG[56] | GTX0:DRP35[9] GTX0:PMA_CFG[57] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP35[6] GTX0:PMA_CFG[54] | GTX0:DRP35[7] GTX0:PMA_CFG[55] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP35[4] GTX0:PMA_CFG[52] | GTX0:DRP35[5] GTX0:PMA_CFG[53] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP35[2] GTX0:PMA_CFG[50] | GTX0:DRP35[3] GTX0:PMA_CFG[51] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP35[0] GTX0:PMA_CFG[48] | GTX0:DRP35[1] GTX0:PMA_CFG[49] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP34[14] GTX0:PMA_CFG[46] | GTX0:DRP34[15] GTX0:PMA_CFG[47] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP34[12] GTX0:PMA_CFG[44] | GTX0:DRP34[13] GTX0:PMA_CFG[45] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP34[10] GTX0:PMA_CFG[42] | GTX0:DRP34[11] GTX0:PMA_CFG[43] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP34[8] GTX0:PMA_CFG[40] | GTX0:DRP34[9] GTX0:PMA_CFG[41] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP34[6] GTX0:PMA_CFG[38] | GTX0:DRP34[7] GTX0:PMA_CFG[39] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP34[4] GTX0:PMA_CFG[36] | GTX0:DRP34[5] GTX0:PMA_CFG[37] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP34[2] GTX0:PMA_CFG[34] | GTX0:DRP34[3] GTX0:PMA_CFG[35] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP34[0] GTX0:PMA_CFG[32] | GTX0:DRP34[1] GTX0:PMA_CFG[33] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP33[14] GTX0:PMA_CFG[30] | GTX0:DRP33[15] GTX0:PMA_CFG[31] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP33[12] GTX0:PMA_CFG[28] | GTX0:DRP33[13] GTX0:PMA_CFG[29] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP33[10] GTX0:PMA_CFG[26] | GTX0:DRP33[11] GTX0:PMA_CFG[27] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP33[8] GTX0:PMA_CFG[24] | GTX0:DRP33[9] GTX0:PMA_CFG[25] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP33[6] GTX0:PMA_CFG[22] | GTX0:DRP33[7] GTX0:PMA_CFG[23] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP33[4] GTX0:PMA_CFG[20] | GTX0:DRP33[5] GTX0:PMA_CFG[21] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP33[2] GTX0:PMA_CFG[18] | GTX0:DRP33[3] GTX0:PMA_CFG[19] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP33[0] GTX0:PMA_CFG[16] | GTX0:DRP33[1] GTX0:PMA_CFG[17] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP32[14] GTX0:PMA_CFG[14] | GTX0:DRP32[15] GTX0:PMA_CFG[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP32[12] GTX0:PMA_CFG[12] | GTX0:DRP32[13] GTX0:PMA_CFG[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP32[10] GTX0:PMA_CFG[10] | GTX0:DRP32[11] GTX0:PMA_CFG[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP32[8] GTX0:PMA_CFG[8] | GTX0:DRP32[9] GTX0:PMA_CFG[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP32[6] GTX0:PMA_CFG[6] | GTX0:DRP32[7] GTX0:PMA_CFG[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP32[4] GTX0:PMA_CFG[4] | GTX0:DRP32[5] GTX0:PMA_CFG[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP32[2] GTX0:PMA_CFG[2] | GTX0:DRP32[3] GTX0:PMA_CFG[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP32[0] GTX0:PMA_CFG[0] | GTX0:DRP32[1] GTX0:PMA_CFG[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP31[14] GTX0:TX_DATA_WIDTH[2] | GTX0:DRP31[15] GTX0:GEN_TXUSRCLK |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP31[12] GTX0:TX_DATA_WIDTH[0] | GTX0:DRP31[13] GTX0:TX_DATA_WIDTH[1] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP31[10] GTX0:PCOMMA_DETECT | GTX0:DRP31[11] GTX0:TX_BUFFER_USE |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP31[8] GTX0:PCOMMA_10B_VALUE[8] | GTX0:DRP31[9] GTX0:PCOMMA_10B_VALUE[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP31[6] GTX0:PCOMMA_10B_VALUE[6] | GTX0:DRP31[7] GTX0:PCOMMA_10B_VALUE[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP31[4] GTX0:PCOMMA_10B_VALUE[4] | GTX0:DRP31[5] GTX0:PCOMMA_10B_VALUE[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP31[2] GTX0:PCOMMA_10B_VALUE[2] | GTX0:DRP31[3] GTX0:PCOMMA_10B_VALUE[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP31[0] GTX0:PCOMMA_10B_VALUE[0] | GTX0:DRP31[1] GTX0:PCOMMA_10B_VALUE[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP30[14] ~GTX0:INV.TXUSRCLK | GTX0:DRP30[15] ~GTX0:INV.TXUSRCLK2 |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP30[12] GTX0:TX_IDLE_DEASSERT_DELAY[1] | GTX0:DRP30[13] GTX0:TX_IDLE_DEASSERT_DELAY[2] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP30[10] GTX0:MCOMMA_DETECT | GTX0:DRP30[11] GTX0:TX_IDLE_DEASSERT_DELAY[0] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP30[8] GTX0:MCOMMA_10B_VALUE[8] | GTX0:DRP30[9] GTX0:MCOMMA_10B_VALUE[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP30[6] GTX0:MCOMMA_10B_VALUE[6] | GTX0:DRP30[7] GTX0:MCOMMA_10B_VALUE[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP30[4] GTX0:MCOMMA_10B_VALUE[4] | GTX0:DRP30[5] GTX0:MCOMMA_10B_VALUE[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP30[2] GTX0:MCOMMA_10B_VALUE[2] | GTX0:DRP30[3] GTX0:MCOMMA_10B_VALUE[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP30[0] GTX0:MCOMMA_10B_VALUE[0] | GTX0:DRP30[1] GTX0:MCOMMA_10B_VALUE[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP47[14] | GTX0:DRP47[15] |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP47[12] | GTX0:DRP47[13] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP47[10] | GTX0:DRP47[11] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP47[8] GTX0:TXOUTCLK_DLY[8] | GTX0:DRP47[9] GTX0:TXOUTCLK_DLY[9] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP47[6] GTX0:TXOUTCLK_DLY[6] | GTX0:DRP47[7] GTX0:TXOUTCLK_DLY[7] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP47[4] GTX0:TXOUTCLK_DLY[4] | GTX0:DRP47[5] GTX0:TXOUTCLK_DLY[5] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP47[2] GTX0:TXOUTCLK_DLY[2] | GTX0:DRP47[3] GTX0:TXOUTCLK_DLY[3] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP47[0] GTX0:TXOUTCLK_DLY[0] | GTX0:DRP47[1] GTX0:TXOUTCLK_DLY[1] |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP46[14] | GTX0:DRP46[15] |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP46[12] | GTX0:DRP46[13] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP46[10] | GTX0:DRP46[11] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP46[8] GTX0:RXRECCLK_DLY[8] | GTX0:DRP46[9] GTX0:RXRECCLK_DLY[9] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP46[6] GTX0:RXRECCLK_DLY[6] | GTX0:DRP46[7] GTX0:RXRECCLK_DLY[7] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP46[4] GTX0:RXRECCLK_DLY[4] | GTX0:DRP46[5] GTX0:RXRECCLK_DLY[5] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP46[2] GTX0:RXRECCLK_DLY[2] | GTX0:DRP46[3] GTX0:RXRECCLK_DLY[3] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP46[0] GTX0:RXRECCLK_DLY[0] | GTX0:DRP46[1] GTX0:RXRECCLK_DLY[1] |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP45[14] | GTX0:DRP45[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP45[12] | GTX0:DRP45[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP45[10] GTX0:TX_USRCLK_CFG[4] | GTX0:DRP45[11] GTX0:TX_USRCLK_CFG[5] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP45[8] GTX0:TX_USRCLK_CFG[2] | GTX0:DRP45[9] GTX0:TX_USRCLK_CFG[3] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP45[6] GTX0:TX_USRCLK_CFG[0] | GTX0:DRP45[7] GTX0:TX_USRCLK_CFG[1] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP45[4] GTX0:TX_BYTECLK_CFG[4] | GTX0:DRP45[5] GTX0:TX_BYTECLK_CFG[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP45[2] GTX0:TX_BYTECLK_CFG[2] | GTX0:DRP45[3] GTX0:TX_BYTECLK_CFG[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP45[0] GTX0:TX_BYTECLK_CFG[0] | GTX0:DRP45[1] GTX0:TX_BYTECLK_CFG[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP44[14] | GTX0:DRP44[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP44[12] | GTX0:DRP44[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP44[10] | GTX0:DRP44[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP44[8] GTX0:POWER_SAVE[8] | GTX0:DRP44[9] GTX0:POWER_SAVE[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP44[6] GTX0:POWER_SAVE[6] | GTX0:DRP44[7] GTX0:POWER_SAVE[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP44[4] GTX0:POWER_SAVE[4] | GTX0:DRP44[5] GTX0:POWER_SAVE[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP44[2] GTX0:POWER_SAVE[2] | GTX0:DRP44[3] GTX0:POWER_SAVE[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP44[0] GTX0:POWER_SAVE[0] | GTX0:DRP44[1] GTX0:POWER_SAVE[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP43[14] ~GTX0:INV.GREFCLKTX | GTX0:DRP43[15] ~GTX0:INV.GREFCLKRX |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP43[12] | GTX0:DRP43[13] ~GTX0:INV.SCANCLK |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP43[10] ~GTX0:INV.TSTCLK0 | GTX0:DRP43[11] ~GTX0:INV.TSTCLK1 |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP43[8] | GTX0:DRP43[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP43[6] | GTX0:DRP43[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP43[4] GTX0:RXRECCLK_CTRL[1] | GTX0:DRP43[5] GTX0:RXRECCLK_CTRL[0] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP43[2] GTX0:TXOUTCLK_CTRL[0] | GTX0:DRP43[3] GTX0:RXRECCLK_CTRL[2] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP43[0] GTX0:TXOUTCLK_CTRL[2] | GTX0:DRP43[1] GTX0:TXOUTCLK_CTRL[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP42[14] GTX0:TST_ATTR[14] | GTX0:DRP42[15] GTX0:TST_ATTR[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP42[12] GTX0:TST_ATTR[12] | GTX0:DRP42[13] GTX0:TST_ATTR[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP42[10] GTX0:TST_ATTR[10] | GTX0:DRP42[11] GTX0:TST_ATTR[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP42[8] GTX0:TST_ATTR[8] | GTX0:DRP42[9] GTX0:TST_ATTR[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP42[6] GTX0:TST_ATTR[6] | GTX0:DRP42[7] GTX0:TST_ATTR[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP42[4] GTX0:TST_ATTR[4] | GTX0:DRP42[5] GTX0:TST_ATTR[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP42[2] GTX0:TST_ATTR[2] | GTX0:DRP42[3] GTX0:TST_ATTR[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP42[0] GTX0:TST_ATTR[0] | GTX0:DRP42[1] GTX0:TST_ATTR[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP41[14] GTX0:TST_ATTR[30] | GTX0:DRP41[15] GTX0:TST_ATTR[31] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP41[12] GTX0:TST_ATTR[28] | GTX0:DRP41[13] GTX0:TST_ATTR[29] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP41[10] GTX0:TST_ATTR[26] | GTX0:DRP41[11] GTX0:TST_ATTR[27] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP41[8] GTX0:TST_ATTR[24] | GTX0:DRP41[9] GTX0:TST_ATTR[25] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP41[6] GTX0:TST_ATTR[22] | GTX0:DRP41[7] GTX0:TST_ATTR[23] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP41[4] GTX0:TST_ATTR[20] | GTX0:DRP41[5] GTX0:TST_ATTR[21] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP41[2] GTX0:TST_ATTR[18] | GTX0:DRP41[3] GTX0:TST_ATTR[19] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP41[0] GTX0:TST_ATTR[16] | GTX0:DRP41[1] GTX0:TST_ATTR[17] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP40[14] | GTX0:DRP40[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP40[12] | GTX0:DRP40[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP40[10] | GTX0:DRP40[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:A_RXEQMIX[8] GTX0:DRP40[8] | GTX0:A_RXEQMIX[9] GTX0:DRP40[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:A_RXEQMIX[6] GTX0:DRP40[6] | GTX0:A_RXEQMIX[7] GTX0:DRP40[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:A_RXEQMIX[4] GTX0:DRP40[4] | GTX0:A_RXEQMIX[5] GTX0:DRP40[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:A_RXEQMIX[2] GTX0:DRP40[2] | GTX0:A_RXEQMIX[3] GTX0:DRP40[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:A_RXEQMIX[0] GTX0:DRP40[0] | GTX0:A_RXEQMIX[1] GTX0:DRP40[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4F[14] | GTX0:DRP4F[15] |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4F[12] | GTX0:DRP4F[13] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4F[10] | GTX0:DRP4F[11] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4F[8] | GTX0:DRP4F[9] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4F[6] | GTX0:DRP4F[7] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4F[4] | GTX0:DRP4F[5] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4F[2] | GTX0:DRP4F[3] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4F[0] | GTX0:DRP4F[1] |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4E[14] | GTX0:DRP4E[15] |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4E[12] | GTX0:DRP4E[13] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4E[10] | GTX0:DRP4E[11] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4E[8] | GTX0:DRP4E[9] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4E[6] | GTX0:DRP4E[7] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4E[4] | GTX0:DRP4E[5] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4E[2] | GTX0:DRP4E[3] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4E[0] | GTX0:DRP4E[1] |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4D[14] GTX0:RX_DLYALIGN_OVRDSETTING[6] | GTX0:DRP4D[15] GTX0:RX_DLYALIGN_OVRDSETTING[7] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4D[12] GTX0:RX_DLYALIGN_OVRDSETTING[4] | GTX0:DRP4D[13] GTX0:RX_DLYALIGN_OVRDSETTING[5] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4D[10] GTX0:RX_DLYALIGN_OVRDSETTING[2] | GTX0:DRP4D[11] GTX0:RX_DLYALIGN_OVRDSETTING[3] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4D[8] GTX0:RX_DLYALIGN_OVRDSETTING[0] | GTX0:DRP4D[9] GTX0:RX_DLYALIGN_OVRDSETTING[1] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4D[6] GTX0:RX_DLYALIGN_LPFINC[2] | GTX0:DRP4D[7] GTX0:RX_DLYALIGN_LPFINC[3] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4D[4] GTX0:RX_DLYALIGN_LPFINC[0] | GTX0:DRP4D[5] GTX0:RX_DLYALIGN_LPFINC[1] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4D[2] GTX0:RX_DLYALIGN_CTRINC[2] | GTX0:DRP4D[3] GTX0:RX_DLYALIGN_CTRINC[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4D[0] GTX0:RX_DLYALIGN_CTRINC[0] | GTX0:DRP4D[1] GTX0:RX_DLYALIGN_CTRINC[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4C[14] GTX0:TX_DLYALIGN_OVRDSETTING[6] | GTX0:DRP4C[15] GTX0:TX_DLYALIGN_OVRDSETTING[7] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4C[12] GTX0:TX_DLYALIGN_OVRDSETTING[4] | GTX0:DRP4C[13] GTX0:TX_DLYALIGN_OVRDSETTING[5] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4C[10] GTX0:TX_DLYALIGN_OVRDSETTING[2] | GTX0:DRP4C[11] GTX0:TX_DLYALIGN_OVRDSETTING[3] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4C[8] GTX0:TX_DLYALIGN_OVRDSETTING[0] | GTX0:DRP4C[9] GTX0:TX_DLYALIGN_OVRDSETTING[1] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4C[6] GTX0:TX_DLYALIGN_LPFINC[2] | GTX0:DRP4C[7] GTX0:TX_DLYALIGN_LPFINC[3] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4C[4] GTX0:TX_DLYALIGN_LPFINC[0] | GTX0:DRP4C[5] GTX0:TX_DLYALIGN_LPFINC[1] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4C[2] GTX0:TX_DLYALIGN_CTRINC[2] | GTX0:DRP4C[3] GTX0:TX_DLYALIGN_CTRINC[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4C[0] GTX0:TX_DLYALIGN_CTRINC[0] | GTX0:DRP4C[1] GTX0:TX_DLYALIGN_CTRINC[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4B[14] GTX0:RX_EN_REALIGN_RESET_BUF2 | GTX0:DRP4B[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4B[12] | GTX0:DRP4B[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4B[10] GTX0:RX_DLYALIGN_EDGESET[4] | GTX0:DRP4B[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4B[8] GTX0:RX_DLYALIGN_EDGESET[2] | GTX0:DRP4B[9] GTX0:RX_DLYALIGN_EDGESET[3] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4B[6] GTX0:RX_DLYALIGN_EDGESET[0] | GTX0:DRP4B[7] GTX0:RX_DLYALIGN_EDGESET[1] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4B[4] GTX0:TX_DLYALIGN_MONSEL[1] | GTX0:DRP4B[5] GTX0:TX_DLYALIGN_MONSEL[2] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4B[2] GTX0:RX_DLYALIGN_MONSEL[2] | GTX0:DRP4B[3] GTX0:TX_DLYALIGN_MONSEL[0] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4B[0] GTX0:RX_DLYALIGN_MONSEL[0] | GTX0:DRP4B[1] GTX0:RX_DLYALIGN_MONSEL[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4A[14] | GTX0:DRP4A[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4A[12] | GTX0:DRP4A[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4A[10] | GTX0:DRP4A[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4A[8] | GTX0:DRP4A[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4A[6] | GTX0:DRP4A[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4A[4] | GTX0:DRP4A[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4A[2] | GTX0:DRP4A[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP4A[0] | GTX0:DRP4A[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP49[14] | GTX0:DRP49[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP49[12] | GTX0:DRP49[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP49[10] | GTX0:DRP49[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP49[8] | GTX0:DRP49[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP49[6] | GTX0:DRP49[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP49[4] | GTX0:DRP49[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP49[2] | GTX0:DRP49[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP49[0] | GTX0:DRP49[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP48[14] | GTX0:DRP48[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP48[12] | GTX0:DRP48[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP48[10] | GTX0:DRP48[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP48[8] | GTX0:DRP48[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP48[6] | GTX0:DRP48[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP48[4] | GTX0:DRP48[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP48[2] | GTX0:DRP48[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX0:DRP48[0] | GTX0:DRP48[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP37[14] GTX1:PMA_TX_CFG[14] | GTX1:DRP37[15] GTX1:PMA_TX_CFG[15] |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP37[12] GTX1:PMA_TX_CFG[12] | GTX1:DRP37[13] GTX1:PMA_TX_CFG[13] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP37[10] GTX1:PMA_TX_CFG[10] | GTX1:DRP37[11] GTX1:PMA_TX_CFG[11] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP37[8] GTX1:PMA_TX_CFG[8] | GTX1:DRP37[9] GTX1:PMA_TX_CFG[9] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP37[6] GTX1:PMA_TX_CFG[6] | GTX1:DRP37[7] GTX1:PMA_TX_CFG[7] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP37[4] GTX1:PMA_TX_CFG[4] | GTX1:DRP37[5] GTX1:PMA_TX_CFG[5] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP37[2] GTX1:PMA_TX_CFG[2] | GTX1:DRP37[3] GTX1:PMA_TX_CFG[3] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP37[0] GTX1:PMA_TX_CFG[0] | GTX1:DRP37[1] GTX1:PMA_TX_CFG[1] |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP36[14] GTX1:PMA_CFG[74] | GTX1:DRP36[15] GTX1:PMA_CFG[75] |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP36[12] GTX1:PMA_CFG[72] | GTX1:DRP36[13] GTX1:PMA_CFG[73] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP36[10] GTX1:PMA_CFG[70] | GTX1:DRP36[11] GTX1:PMA_CFG[71] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP36[8] GTX1:PMA_CFG[68] | GTX1:DRP36[9] GTX1:PMA_CFG[69] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP36[6] GTX1:PMA_CFG[66] | GTX1:DRP36[7] GTX1:PMA_CFG[67] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP36[4] GTX1:PMA_CFG[64] | GTX1:DRP36[5] GTX1:PMA_CFG[65] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP36[2] GTX1:PMA_TX_CFG[18] | GTX1:DRP36[3] GTX1:PMA_TX_CFG[19] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP36[0] GTX1:PMA_TX_CFG[16] | GTX1:DRP36[1] GTX1:PMA_TX_CFG[17] |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP35[14] GTX1:PMA_CFG[62] | GTX1:DRP35[15] GTX1:PMA_CFG[63] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP35[12] GTX1:PMA_CFG[60] | GTX1:DRP35[13] GTX1:PMA_CFG[61] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP35[10] GTX1:PMA_CFG[58] | GTX1:DRP35[11] GTX1:PMA_CFG[59] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP35[8] GTX1:PMA_CFG[56] | GTX1:DRP35[9] GTX1:PMA_CFG[57] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP35[6] GTX1:PMA_CFG[54] | GTX1:DRP35[7] GTX1:PMA_CFG[55] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP35[4] GTX1:PMA_CFG[52] | GTX1:DRP35[5] GTX1:PMA_CFG[53] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP35[2] GTX1:PMA_CFG[50] | GTX1:DRP35[3] GTX1:PMA_CFG[51] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP35[0] GTX1:PMA_CFG[48] | GTX1:DRP35[1] GTX1:PMA_CFG[49] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP34[14] GTX1:PMA_CFG[46] | GTX1:DRP34[15] GTX1:PMA_CFG[47] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP34[12] GTX1:PMA_CFG[44] | GTX1:DRP34[13] GTX1:PMA_CFG[45] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP34[10] GTX1:PMA_CFG[42] | GTX1:DRP34[11] GTX1:PMA_CFG[43] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP34[8] GTX1:PMA_CFG[40] | GTX1:DRP34[9] GTX1:PMA_CFG[41] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP34[6] GTX1:PMA_CFG[38] | GTX1:DRP34[7] GTX1:PMA_CFG[39] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP34[4] GTX1:PMA_CFG[36] | GTX1:DRP34[5] GTX1:PMA_CFG[37] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP34[2] GTX1:PMA_CFG[34] | GTX1:DRP34[3] GTX1:PMA_CFG[35] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP34[0] GTX1:PMA_CFG[32] | GTX1:DRP34[1] GTX1:PMA_CFG[33] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP33[14] GTX1:PMA_CFG[30] | GTX1:DRP33[15] GTX1:PMA_CFG[31] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP33[12] GTX1:PMA_CFG[28] | GTX1:DRP33[13] GTX1:PMA_CFG[29] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP33[10] GTX1:PMA_CFG[26] | GTX1:DRP33[11] GTX1:PMA_CFG[27] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP33[8] GTX1:PMA_CFG[24] | GTX1:DRP33[9] GTX1:PMA_CFG[25] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP33[6] GTX1:PMA_CFG[22] | GTX1:DRP33[7] GTX1:PMA_CFG[23] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP33[4] GTX1:PMA_CFG[20] | GTX1:DRP33[5] GTX1:PMA_CFG[21] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP33[2] GTX1:PMA_CFG[18] | GTX1:DRP33[3] GTX1:PMA_CFG[19] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP33[0] GTX1:PMA_CFG[16] | GTX1:DRP33[1] GTX1:PMA_CFG[17] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP32[14] GTX1:PMA_CFG[14] | GTX1:DRP32[15] GTX1:PMA_CFG[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP32[12] GTX1:PMA_CFG[12] | GTX1:DRP32[13] GTX1:PMA_CFG[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP32[10] GTX1:PMA_CFG[10] | GTX1:DRP32[11] GTX1:PMA_CFG[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP32[8] GTX1:PMA_CFG[8] | GTX1:DRP32[9] GTX1:PMA_CFG[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP32[6] GTX1:PMA_CFG[6] | GTX1:DRP32[7] GTX1:PMA_CFG[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP32[4] GTX1:PMA_CFG[4] | GTX1:DRP32[5] GTX1:PMA_CFG[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP32[2] GTX1:PMA_CFG[2] | GTX1:DRP32[3] GTX1:PMA_CFG[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP32[0] GTX1:PMA_CFG[0] | GTX1:DRP32[1] GTX1:PMA_CFG[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP31[14] GTX1:TX_DATA_WIDTH[2] | GTX1:DRP31[15] GTX1:GEN_TXUSRCLK |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP31[12] GTX1:TX_DATA_WIDTH[0] | GTX1:DRP31[13] GTX1:TX_DATA_WIDTH[1] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP31[10] GTX1:PCOMMA_DETECT | GTX1:DRP31[11] GTX1:TX_BUFFER_USE |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP31[8] GTX1:PCOMMA_10B_VALUE[8] | GTX1:DRP31[9] GTX1:PCOMMA_10B_VALUE[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP31[6] GTX1:PCOMMA_10B_VALUE[6] | GTX1:DRP31[7] GTX1:PCOMMA_10B_VALUE[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP31[4] GTX1:PCOMMA_10B_VALUE[4] | GTX1:DRP31[5] GTX1:PCOMMA_10B_VALUE[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP31[2] GTX1:PCOMMA_10B_VALUE[2] | GTX1:DRP31[3] GTX1:PCOMMA_10B_VALUE[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP31[0] GTX1:PCOMMA_10B_VALUE[0] | GTX1:DRP31[1] GTX1:PCOMMA_10B_VALUE[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP30[14] ~GTX1:INV.TXUSRCLK | GTX1:DRP30[15] ~GTX1:INV.TXUSRCLK2 |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP30[12] GTX1:TX_IDLE_DEASSERT_DELAY[1] | GTX1:DRP30[13] GTX1:TX_IDLE_DEASSERT_DELAY[2] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP30[10] GTX1:MCOMMA_DETECT | GTX1:DRP30[11] GTX1:TX_IDLE_DEASSERT_DELAY[0] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP30[8] GTX1:MCOMMA_10B_VALUE[8] | GTX1:DRP30[9] GTX1:MCOMMA_10B_VALUE[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP30[6] GTX1:MCOMMA_10B_VALUE[6] | GTX1:DRP30[7] GTX1:MCOMMA_10B_VALUE[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP30[4] GTX1:MCOMMA_10B_VALUE[4] | GTX1:DRP30[5] GTX1:MCOMMA_10B_VALUE[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP30[2] GTX1:MCOMMA_10B_VALUE[2] | GTX1:DRP30[3] GTX1:MCOMMA_10B_VALUE[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP30[0] GTX1:MCOMMA_10B_VALUE[0] | GTX1:DRP30[1] GTX1:MCOMMA_10B_VALUE[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP47[14] | GTX1:DRP47[15] |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP47[12] | GTX1:DRP47[13] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP47[10] | GTX1:DRP47[11] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP47[8] GTX1:TXOUTCLK_DLY[8] | GTX1:DRP47[9] GTX1:TXOUTCLK_DLY[9] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP47[6] GTX1:TXOUTCLK_DLY[6] | GTX1:DRP47[7] GTX1:TXOUTCLK_DLY[7] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP47[4] GTX1:TXOUTCLK_DLY[4] | GTX1:DRP47[5] GTX1:TXOUTCLK_DLY[5] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP47[2] GTX1:TXOUTCLK_DLY[2] | GTX1:DRP47[3] GTX1:TXOUTCLK_DLY[3] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP47[0] GTX1:TXOUTCLK_DLY[0] | GTX1:DRP47[1] GTX1:TXOUTCLK_DLY[1] |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP46[14] | GTX1:DRP46[15] |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP46[12] | GTX1:DRP46[13] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP46[10] | GTX1:DRP46[11] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP46[8] GTX1:RXRECCLK_DLY[8] | GTX1:DRP46[9] GTX1:RXRECCLK_DLY[9] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP46[6] GTX1:RXRECCLK_DLY[6] | GTX1:DRP46[7] GTX1:RXRECCLK_DLY[7] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP46[4] GTX1:RXRECCLK_DLY[4] | GTX1:DRP46[5] GTX1:RXRECCLK_DLY[5] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP46[2] GTX1:RXRECCLK_DLY[2] | GTX1:DRP46[3] GTX1:RXRECCLK_DLY[3] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP46[0] GTX1:RXRECCLK_DLY[0] | GTX1:DRP46[1] GTX1:RXRECCLK_DLY[1] |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP45[14] | GTX1:DRP45[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP45[12] | GTX1:DRP45[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP45[10] GTX1:TX_USRCLK_CFG[4] | GTX1:DRP45[11] GTX1:TX_USRCLK_CFG[5] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP45[8] GTX1:TX_USRCLK_CFG[2] | GTX1:DRP45[9] GTX1:TX_USRCLK_CFG[3] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP45[6] GTX1:TX_USRCLK_CFG[0] | GTX1:DRP45[7] GTX1:TX_USRCLK_CFG[1] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP45[4] GTX1:TX_BYTECLK_CFG[4] | GTX1:DRP45[5] GTX1:TX_BYTECLK_CFG[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP45[2] GTX1:TX_BYTECLK_CFG[2] | GTX1:DRP45[3] GTX1:TX_BYTECLK_CFG[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP45[0] GTX1:TX_BYTECLK_CFG[0] | GTX1:DRP45[1] GTX1:TX_BYTECLK_CFG[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP44[14] | GTX1:DRP44[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP44[12] | GTX1:DRP44[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP44[10] | GTX1:DRP44[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP44[8] GTX1:POWER_SAVE[8] | GTX1:DRP44[9] GTX1:POWER_SAVE[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP44[6] GTX1:POWER_SAVE[6] | GTX1:DRP44[7] GTX1:POWER_SAVE[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP44[4] GTX1:POWER_SAVE[4] | GTX1:DRP44[5] GTX1:POWER_SAVE[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP44[2] GTX1:POWER_SAVE[2] | GTX1:DRP44[3] GTX1:POWER_SAVE[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP44[0] GTX1:POWER_SAVE[0] | GTX1:DRP44[1] GTX1:POWER_SAVE[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP43[14] ~GTX1:INV.GREFCLKTX | GTX1:DRP43[15] ~GTX1:INV.GREFCLKRX |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP43[12] | GTX1:DRP43[13] ~GTX1:INV.SCANCLK |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP43[10] ~GTX1:INV.TSTCLK0 | GTX1:DRP43[11] ~GTX1:INV.TSTCLK1 |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | BUFDS1:MUX.HCLK_OUT[1] GTX1:DRP43[8] | BUFDS1:MUX.HCLK_OUT[0] GTX1:DRP43[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | BUFDS0:MUX.HCLK_OUT[1] GTX1:DRP43[6] | BUFDS0:MUX.HCLK_OUT[0] GTX1:DRP43[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP43[4] GTX1:RXRECCLK_CTRL[1] | GTX1:DRP43[5] GTX1:RXRECCLK_CTRL[0] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP43[2] GTX1:TXOUTCLK_CTRL[0] | GTX1:DRP43[3] GTX1:RXRECCLK_CTRL[2] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP43[0] GTX1:TXOUTCLK_CTRL[2] | GTX1:DRP43[1] GTX1:TXOUTCLK_CTRL[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP42[14] GTX1:TST_ATTR[14] | GTX1:DRP42[15] GTX1:TST_ATTR[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP42[12] GTX1:TST_ATTR[12] | GTX1:DRP42[13] GTX1:TST_ATTR[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP42[10] GTX1:TST_ATTR[10] | GTX1:DRP42[11] GTX1:TST_ATTR[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP42[8] GTX1:TST_ATTR[8] | GTX1:DRP42[9] GTX1:TST_ATTR[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP42[6] GTX1:TST_ATTR[6] | GTX1:DRP42[7] GTX1:TST_ATTR[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP42[4] GTX1:TST_ATTR[4] | GTX1:DRP42[5] GTX1:TST_ATTR[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP42[2] GTX1:TST_ATTR[2] | GTX1:DRP42[3] GTX1:TST_ATTR[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP42[0] GTX1:TST_ATTR[0] | GTX1:DRP42[1] GTX1:TST_ATTR[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP41[14] GTX1:TST_ATTR[30] | GTX1:DRP41[15] GTX1:TST_ATTR[31] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP41[12] GTX1:TST_ATTR[28] | GTX1:DRP41[13] GTX1:TST_ATTR[29] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP41[10] GTX1:TST_ATTR[26] | GTX1:DRP41[11] GTX1:TST_ATTR[27] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP41[8] GTX1:TST_ATTR[24] | GTX1:DRP41[9] GTX1:TST_ATTR[25] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP41[6] GTX1:TST_ATTR[22] | GTX1:DRP41[7] GTX1:TST_ATTR[23] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP41[4] GTX1:TST_ATTR[20] | GTX1:DRP41[5] GTX1:TST_ATTR[21] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP41[2] GTX1:TST_ATTR[18] | GTX1:DRP41[3] GTX1:TST_ATTR[19] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP41[0] GTX1:TST_ATTR[16] | GTX1:DRP41[1] GTX1:TST_ATTR[17] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP40[14] | GTX1:DRP40[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP40[12] | GTX1:DRP40[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP40[10] | GTX1:DRP40[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:A_RXEQMIX[8] GTX1:DRP40[8] | GTX1:A_RXEQMIX[9] GTX1:DRP40[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:A_RXEQMIX[6] GTX1:DRP40[6] | GTX1:A_RXEQMIX[7] GTX1:DRP40[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:A_RXEQMIX[4] GTX1:DRP40[4] | GTX1:A_RXEQMIX[5] GTX1:DRP40[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:A_RXEQMIX[2] GTX1:DRP40[2] | GTX1:A_RXEQMIX[3] GTX1:DRP40[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:A_RXEQMIX[0] GTX1:DRP40[0] | GTX1:A_RXEQMIX[1] GTX1:DRP40[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4F[14] | GTX1:DRP4F[15] |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4F[12] | GTX1:DRP4F[13] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4F[10] | GTX1:DRP4F[11] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4F[8] | GTX1:DRP4F[9] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4F[6] | GTX1:DRP4F[7] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4F[4] | GTX1:DRP4F[5] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4F[2] | GTX1:DRP4F[3] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4F[0] | GTX1:DRP4F[1] |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4E[14] | GTX1:DRP4E[15] |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4E[12] | GTX1:DRP4E[13] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4E[10] | GTX1:DRP4E[11] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4E[8] | GTX1:DRP4E[9] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4E[6] | GTX1:DRP4E[7] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4E[4] | GTX1:DRP4E[5] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4E[2] | GTX1:DRP4E[3] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4E[0] | GTX1:DRP4E[1] |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4D[14] GTX1:RX_DLYALIGN_OVRDSETTING[6] | GTX1:DRP4D[15] GTX1:RX_DLYALIGN_OVRDSETTING[7] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4D[12] GTX1:RX_DLYALIGN_OVRDSETTING[4] | GTX1:DRP4D[13] GTX1:RX_DLYALIGN_OVRDSETTING[5] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4D[10] GTX1:RX_DLYALIGN_OVRDSETTING[2] | GTX1:DRP4D[11] GTX1:RX_DLYALIGN_OVRDSETTING[3] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4D[8] GTX1:RX_DLYALIGN_OVRDSETTING[0] | GTX1:DRP4D[9] GTX1:RX_DLYALIGN_OVRDSETTING[1] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4D[6] GTX1:RX_DLYALIGN_LPFINC[2] | GTX1:DRP4D[7] GTX1:RX_DLYALIGN_LPFINC[3] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4D[4] GTX1:RX_DLYALIGN_LPFINC[0] | GTX1:DRP4D[5] GTX1:RX_DLYALIGN_LPFINC[1] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4D[2] GTX1:RX_DLYALIGN_CTRINC[2] | GTX1:DRP4D[3] GTX1:RX_DLYALIGN_CTRINC[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4D[0] GTX1:RX_DLYALIGN_CTRINC[0] | GTX1:DRP4D[1] GTX1:RX_DLYALIGN_CTRINC[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4C[14] GTX1:TX_DLYALIGN_OVRDSETTING[6] | GTX1:DRP4C[15] GTX1:TX_DLYALIGN_OVRDSETTING[7] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4C[12] GTX1:TX_DLYALIGN_OVRDSETTING[4] | GTX1:DRP4C[13] GTX1:TX_DLYALIGN_OVRDSETTING[5] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4C[10] GTX1:TX_DLYALIGN_OVRDSETTING[2] | GTX1:DRP4C[11] GTX1:TX_DLYALIGN_OVRDSETTING[3] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4C[8] GTX1:TX_DLYALIGN_OVRDSETTING[0] | GTX1:DRP4C[9] GTX1:TX_DLYALIGN_OVRDSETTING[1] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4C[6] GTX1:TX_DLYALIGN_LPFINC[2] | GTX1:DRP4C[7] GTX1:TX_DLYALIGN_LPFINC[3] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4C[4] GTX1:TX_DLYALIGN_LPFINC[0] | GTX1:DRP4C[5] GTX1:TX_DLYALIGN_LPFINC[1] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4C[2] GTX1:TX_DLYALIGN_CTRINC[2] | GTX1:DRP4C[3] GTX1:TX_DLYALIGN_CTRINC[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4C[0] GTX1:TX_DLYALIGN_CTRINC[0] | GTX1:DRP4C[1] GTX1:TX_DLYALIGN_CTRINC[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4B[14] GTX1:RX_EN_REALIGN_RESET_BUF2 | GTX1:DRP4B[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4B[12] | GTX1:DRP4B[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4B[10] GTX1:RX_DLYALIGN_EDGESET[4] | GTX1:DRP4B[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4B[8] GTX1:RX_DLYALIGN_EDGESET[2] | GTX1:DRP4B[9] GTX1:RX_DLYALIGN_EDGESET[3] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4B[6] GTX1:RX_DLYALIGN_EDGESET[0] | GTX1:DRP4B[7] GTX1:RX_DLYALIGN_EDGESET[1] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4B[4] GTX1:TX_DLYALIGN_MONSEL[1] | GTX1:DRP4B[5] GTX1:TX_DLYALIGN_MONSEL[2] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4B[2] GTX1:RX_DLYALIGN_MONSEL[2] | GTX1:DRP4B[3] GTX1:TX_DLYALIGN_MONSEL[0] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4B[0] GTX1:RX_DLYALIGN_MONSEL[0] | GTX1:DRP4B[1] GTX1:RX_DLYALIGN_MONSEL[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4A[14] | GTX1:DRP4A[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4A[12] | GTX1:DRP4A[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4A[10] | GTX1:DRP4A[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4A[8] | GTX1:DRP4A[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4A[6] | GTX1:DRP4A[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4A[4] | GTX1:DRP4A[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4A[2] | GTX1:DRP4A[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP4A[0] | GTX1:DRP4A[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP49[14] | GTX1:DRP49[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP49[12] | GTX1:DRP49[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP49[10] | GTX1:DRP49[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | BUFDS1:REFCLKOUT_DLY[8] GTX1:DRP49[8] | BUFDS1:REFCLKOUT_DLY[9] GTX1:DRP49[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | BUFDS1:REFCLKOUT_DLY[6] GTX1:DRP49[6] | BUFDS1:REFCLKOUT_DLY[7] GTX1:DRP49[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | BUFDS1:REFCLKOUT_DLY[4] GTX1:DRP49[4] | BUFDS1:REFCLKOUT_DLY[5] GTX1:DRP49[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | BUFDS1:REFCLKOUT_DLY[2] GTX1:DRP49[2] | BUFDS1:REFCLKOUT_DLY[3] GTX1:DRP49[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | BUFDS1:REFCLKOUT_DLY[0] GTX1:DRP49[0] | BUFDS1:REFCLKOUT_DLY[1] GTX1:DRP49[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP48[14] | GTX1:DRP48[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP48[12] | GTX1:DRP48[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX1:DRP48[10] | GTX1:DRP48[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | BUFDS0:REFCLKOUT_DLY[8] GTX1:DRP48[8] | BUFDS0:REFCLKOUT_DLY[9] GTX1:DRP48[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | BUFDS0:REFCLKOUT_DLY[6] GTX1:DRP48[6] | BUFDS0:REFCLKOUT_DLY[7] GTX1:DRP48[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | BUFDS0:REFCLKOUT_DLY[4] GTX1:DRP48[4] | BUFDS0:REFCLKOUT_DLY[5] GTX1:DRP48[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | BUFDS0:REFCLKOUT_DLY[2] GTX1:DRP48[2] | BUFDS0:REFCLKOUT_DLY[3] GTX1:DRP48[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | BUFDS0:REFCLKOUT_DLY[0] GTX1:DRP48[0] | BUFDS0:REFCLKOUT_DLY[1] GTX1:DRP48[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP37[14] GTX2:PMA_TX_CFG[14] | GTX2:DRP37[15] GTX2:PMA_TX_CFG[15] |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP37[12] GTX2:PMA_TX_CFG[12] | GTX2:DRP37[13] GTX2:PMA_TX_CFG[13] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP37[10] GTX2:PMA_TX_CFG[10] | GTX2:DRP37[11] GTX2:PMA_TX_CFG[11] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP37[8] GTX2:PMA_TX_CFG[8] | GTX2:DRP37[9] GTX2:PMA_TX_CFG[9] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP37[6] GTX2:PMA_TX_CFG[6] | GTX2:DRP37[7] GTX2:PMA_TX_CFG[7] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP37[4] GTX2:PMA_TX_CFG[4] | GTX2:DRP37[5] GTX2:PMA_TX_CFG[5] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP37[2] GTX2:PMA_TX_CFG[2] | GTX2:DRP37[3] GTX2:PMA_TX_CFG[3] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP37[0] GTX2:PMA_TX_CFG[0] | GTX2:DRP37[1] GTX2:PMA_TX_CFG[1] |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP36[14] GTX2:PMA_CFG[74] | GTX2:DRP36[15] GTX2:PMA_CFG[75] |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP36[12] GTX2:PMA_CFG[72] | GTX2:DRP36[13] GTX2:PMA_CFG[73] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP36[10] GTX2:PMA_CFG[70] | GTX2:DRP36[11] GTX2:PMA_CFG[71] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP36[8] GTX2:PMA_CFG[68] | GTX2:DRP36[9] GTX2:PMA_CFG[69] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP36[6] GTX2:PMA_CFG[66] | GTX2:DRP36[7] GTX2:PMA_CFG[67] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP36[4] GTX2:PMA_CFG[64] | GTX2:DRP36[5] GTX2:PMA_CFG[65] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP36[2] GTX2:PMA_TX_CFG[18] | GTX2:DRP36[3] GTX2:PMA_TX_CFG[19] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP36[0] GTX2:PMA_TX_CFG[16] | GTX2:DRP36[1] GTX2:PMA_TX_CFG[17] |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP35[14] GTX2:PMA_CFG[62] | GTX2:DRP35[15] GTX2:PMA_CFG[63] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP35[12] GTX2:PMA_CFG[60] | GTX2:DRP35[13] GTX2:PMA_CFG[61] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP35[10] GTX2:PMA_CFG[58] | GTX2:DRP35[11] GTX2:PMA_CFG[59] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP35[8] GTX2:PMA_CFG[56] | GTX2:DRP35[9] GTX2:PMA_CFG[57] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP35[6] GTX2:PMA_CFG[54] | GTX2:DRP35[7] GTX2:PMA_CFG[55] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP35[4] GTX2:PMA_CFG[52] | GTX2:DRP35[5] GTX2:PMA_CFG[53] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP35[2] GTX2:PMA_CFG[50] | GTX2:DRP35[3] GTX2:PMA_CFG[51] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP35[0] GTX2:PMA_CFG[48] | GTX2:DRP35[1] GTX2:PMA_CFG[49] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP34[14] GTX2:PMA_CFG[46] | GTX2:DRP34[15] GTX2:PMA_CFG[47] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP34[12] GTX2:PMA_CFG[44] | GTX2:DRP34[13] GTX2:PMA_CFG[45] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP34[10] GTX2:PMA_CFG[42] | GTX2:DRP34[11] GTX2:PMA_CFG[43] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP34[8] GTX2:PMA_CFG[40] | GTX2:DRP34[9] GTX2:PMA_CFG[41] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP34[6] GTX2:PMA_CFG[38] | GTX2:DRP34[7] GTX2:PMA_CFG[39] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP34[4] GTX2:PMA_CFG[36] | GTX2:DRP34[5] GTX2:PMA_CFG[37] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP34[2] GTX2:PMA_CFG[34] | GTX2:DRP34[3] GTX2:PMA_CFG[35] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP34[0] GTX2:PMA_CFG[32] | GTX2:DRP34[1] GTX2:PMA_CFG[33] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP33[14] GTX2:PMA_CFG[30] | GTX2:DRP33[15] GTX2:PMA_CFG[31] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP33[12] GTX2:PMA_CFG[28] | GTX2:DRP33[13] GTX2:PMA_CFG[29] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP33[10] GTX2:PMA_CFG[26] | GTX2:DRP33[11] GTX2:PMA_CFG[27] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP33[8] GTX2:PMA_CFG[24] | GTX2:DRP33[9] GTX2:PMA_CFG[25] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP33[6] GTX2:PMA_CFG[22] | GTX2:DRP33[7] GTX2:PMA_CFG[23] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP33[4] GTX2:PMA_CFG[20] | GTX2:DRP33[5] GTX2:PMA_CFG[21] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP33[2] GTX2:PMA_CFG[18] | GTX2:DRP33[3] GTX2:PMA_CFG[19] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP33[0] GTX2:PMA_CFG[16] | GTX2:DRP33[1] GTX2:PMA_CFG[17] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP32[14] GTX2:PMA_CFG[14] | GTX2:DRP32[15] GTX2:PMA_CFG[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP32[12] GTX2:PMA_CFG[12] | GTX2:DRP32[13] GTX2:PMA_CFG[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP32[10] GTX2:PMA_CFG[10] | GTX2:DRP32[11] GTX2:PMA_CFG[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP32[8] GTX2:PMA_CFG[8] | GTX2:DRP32[9] GTX2:PMA_CFG[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP32[6] GTX2:PMA_CFG[6] | GTX2:DRP32[7] GTX2:PMA_CFG[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP32[4] GTX2:PMA_CFG[4] | GTX2:DRP32[5] GTX2:PMA_CFG[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP32[2] GTX2:PMA_CFG[2] | GTX2:DRP32[3] GTX2:PMA_CFG[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP32[0] GTX2:PMA_CFG[0] | GTX2:DRP32[1] GTX2:PMA_CFG[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP31[14] GTX2:TX_DATA_WIDTH[2] | GTX2:DRP31[15] GTX2:GEN_TXUSRCLK |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP31[12] GTX2:TX_DATA_WIDTH[0] | GTX2:DRP31[13] GTX2:TX_DATA_WIDTH[1] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP31[10] GTX2:PCOMMA_DETECT | GTX2:DRP31[11] GTX2:TX_BUFFER_USE |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP31[8] GTX2:PCOMMA_10B_VALUE[8] | GTX2:DRP31[9] GTX2:PCOMMA_10B_VALUE[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP31[6] GTX2:PCOMMA_10B_VALUE[6] | GTX2:DRP31[7] GTX2:PCOMMA_10B_VALUE[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP31[4] GTX2:PCOMMA_10B_VALUE[4] | GTX2:DRP31[5] GTX2:PCOMMA_10B_VALUE[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP31[2] GTX2:PCOMMA_10B_VALUE[2] | GTX2:DRP31[3] GTX2:PCOMMA_10B_VALUE[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP31[0] GTX2:PCOMMA_10B_VALUE[0] | GTX2:DRP31[1] GTX2:PCOMMA_10B_VALUE[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP30[14] ~GTX2:INV.TXUSRCLK | GTX2:DRP30[15] ~GTX2:INV.TXUSRCLK2 |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP30[12] GTX2:TX_IDLE_DEASSERT_DELAY[1] | GTX2:DRP30[13] GTX2:TX_IDLE_DEASSERT_DELAY[2] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP30[10] GTX2:MCOMMA_DETECT | GTX2:DRP30[11] GTX2:TX_IDLE_DEASSERT_DELAY[0] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP30[8] GTX2:MCOMMA_10B_VALUE[8] | GTX2:DRP30[9] GTX2:MCOMMA_10B_VALUE[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP30[6] GTX2:MCOMMA_10B_VALUE[6] | GTX2:DRP30[7] GTX2:MCOMMA_10B_VALUE[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP30[4] GTX2:MCOMMA_10B_VALUE[4] | GTX2:DRP30[5] GTX2:MCOMMA_10B_VALUE[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP30[2] GTX2:MCOMMA_10B_VALUE[2] | GTX2:DRP30[3] GTX2:MCOMMA_10B_VALUE[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP30[0] GTX2:MCOMMA_10B_VALUE[0] | GTX2:DRP30[1] GTX2:MCOMMA_10B_VALUE[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP47[14] | GTX2:DRP47[15] |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP47[12] | GTX2:DRP47[13] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP47[10] | GTX2:DRP47[11] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP47[8] GTX2:TXOUTCLK_DLY[8] | GTX2:DRP47[9] GTX2:TXOUTCLK_DLY[9] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP47[6] GTX2:TXOUTCLK_DLY[6] | GTX2:DRP47[7] GTX2:TXOUTCLK_DLY[7] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP47[4] GTX2:TXOUTCLK_DLY[4] | GTX2:DRP47[5] GTX2:TXOUTCLK_DLY[5] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP47[2] GTX2:TXOUTCLK_DLY[2] | GTX2:DRP47[3] GTX2:TXOUTCLK_DLY[3] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP47[0] GTX2:TXOUTCLK_DLY[0] | GTX2:DRP47[1] GTX2:TXOUTCLK_DLY[1] |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP46[14] | GTX2:DRP46[15] |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP46[12] | GTX2:DRP46[13] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP46[10] | GTX2:DRP46[11] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP46[8] GTX2:RXRECCLK_DLY[8] | GTX2:DRP46[9] GTX2:RXRECCLK_DLY[9] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP46[6] GTX2:RXRECCLK_DLY[6] | GTX2:DRP46[7] GTX2:RXRECCLK_DLY[7] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP46[4] GTX2:RXRECCLK_DLY[4] | GTX2:DRP46[5] GTX2:RXRECCLK_DLY[5] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP46[2] GTX2:RXRECCLK_DLY[2] | GTX2:DRP46[3] GTX2:RXRECCLK_DLY[3] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP46[0] GTX2:RXRECCLK_DLY[0] | GTX2:DRP46[1] GTX2:RXRECCLK_DLY[1] |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP45[14] | GTX2:DRP45[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP45[12] | GTX2:DRP45[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP45[10] GTX2:TX_USRCLK_CFG[4] | GTX2:DRP45[11] GTX2:TX_USRCLK_CFG[5] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP45[8] GTX2:TX_USRCLK_CFG[2] | GTX2:DRP45[9] GTX2:TX_USRCLK_CFG[3] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP45[6] GTX2:TX_USRCLK_CFG[0] | GTX2:DRP45[7] GTX2:TX_USRCLK_CFG[1] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP45[4] GTX2:TX_BYTECLK_CFG[4] | GTX2:DRP45[5] GTX2:TX_BYTECLK_CFG[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP45[2] GTX2:TX_BYTECLK_CFG[2] | GTX2:DRP45[3] GTX2:TX_BYTECLK_CFG[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP45[0] GTX2:TX_BYTECLK_CFG[0] | GTX2:DRP45[1] GTX2:TX_BYTECLK_CFG[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP44[14] | GTX2:DRP44[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP44[12] | GTX2:DRP44[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP44[10] | GTX2:DRP44[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP44[8] GTX2:POWER_SAVE[8] | GTX2:DRP44[9] GTX2:POWER_SAVE[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP44[6] GTX2:POWER_SAVE[6] | GTX2:DRP44[7] GTX2:POWER_SAVE[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP44[4] GTX2:POWER_SAVE[4] | GTX2:DRP44[5] GTX2:POWER_SAVE[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP44[2] GTX2:POWER_SAVE[2] | GTX2:DRP44[3] GTX2:POWER_SAVE[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP44[0] GTX2:POWER_SAVE[0] | GTX2:DRP44[1] GTX2:POWER_SAVE[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP43[14] ~GTX2:INV.GREFCLKTX | GTX2:DRP43[15] ~GTX2:INV.GREFCLKRX |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP43[12] | GTX2:DRP43[13] ~GTX2:INV.SCANCLK |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP43[10] ~GTX2:INV.TSTCLK0 | GTX2:DRP43[11] ~GTX2:INV.TSTCLK1 |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP43[8] | GTX2:DRP43[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP43[6] | GTX2:DRP43[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP43[4] GTX2:RXRECCLK_CTRL[1] | GTX2:DRP43[5] GTX2:RXRECCLK_CTRL[0] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP43[2] GTX2:TXOUTCLK_CTRL[0] | GTX2:DRP43[3] GTX2:RXRECCLK_CTRL[2] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP43[0] GTX2:TXOUTCLK_CTRL[2] | GTX2:DRP43[1] GTX2:TXOUTCLK_CTRL[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP42[14] GTX2:TST_ATTR[14] | GTX2:DRP42[15] GTX2:TST_ATTR[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP42[12] GTX2:TST_ATTR[12] | GTX2:DRP42[13] GTX2:TST_ATTR[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP42[10] GTX2:TST_ATTR[10] | GTX2:DRP42[11] GTX2:TST_ATTR[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP42[8] GTX2:TST_ATTR[8] | GTX2:DRP42[9] GTX2:TST_ATTR[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP42[6] GTX2:TST_ATTR[6] | GTX2:DRP42[7] GTX2:TST_ATTR[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP42[4] GTX2:TST_ATTR[4] | GTX2:DRP42[5] GTX2:TST_ATTR[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP42[2] GTX2:TST_ATTR[2] | GTX2:DRP42[3] GTX2:TST_ATTR[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP42[0] GTX2:TST_ATTR[0] | GTX2:DRP42[1] GTX2:TST_ATTR[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP41[14] GTX2:TST_ATTR[30] | GTX2:DRP41[15] GTX2:TST_ATTR[31] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP41[12] GTX2:TST_ATTR[28] | GTX2:DRP41[13] GTX2:TST_ATTR[29] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP41[10] GTX2:TST_ATTR[26] | GTX2:DRP41[11] GTX2:TST_ATTR[27] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP41[8] GTX2:TST_ATTR[24] | GTX2:DRP41[9] GTX2:TST_ATTR[25] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP41[6] GTX2:TST_ATTR[22] | GTX2:DRP41[7] GTX2:TST_ATTR[23] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP41[4] GTX2:TST_ATTR[20] | GTX2:DRP41[5] GTX2:TST_ATTR[21] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP41[2] GTX2:TST_ATTR[18] | GTX2:DRP41[3] GTX2:TST_ATTR[19] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP41[0] GTX2:TST_ATTR[16] | GTX2:DRP41[1] GTX2:TST_ATTR[17] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP40[14] | GTX2:DRP40[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP40[12] | GTX2:DRP40[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP40[10] | GTX2:DRP40[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:A_RXEQMIX[8] GTX2:DRP40[8] | GTX2:A_RXEQMIX[9] GTX2:DRP40[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:A_RXEQMIX[6] GTX2:DRP40[6] | GTX2:A_RXEQMIX[7] GTX2:DRP40[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:A_RXEQMIX[4] GTX2:DRP40[4] | GTX2:A_RXEQMIX[5] GTX2:DRP40[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:A_RXEQMIX[2] GTX2:DRP40[2] | GTX2:A_RXEQMIX[3] GTX2:DRP40[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:A_RXEQMIX[0] GTX2:DRP40[0] | GTX2:A_RXEQMIX[1] GTX2:DRP40[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4F[14] | GTX2:DRP4F[15] |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4F[12] | GTX2:DRP4F[13] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4F[10] | GTX2:DRP4F[11] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4F[8] | GTX2:DRP4F[9] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4F[6] | GTX2:DRP4F[7] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4F[4] | GTX2:DRP4F[5] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4F[2] | GTX2:DRP4F[3] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4F[0] | GTX2:DRP4F[1] |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4E[14] | GTX2:DRP4E[15] |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4E[12] | GTX2:DRP4E[13] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4E[10] | GTX2:DRP4E[11] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4E[8] | GTX2:DRP4E[9] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4E[6] | GTX2:DRP4E[7] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4E[4] | GTX2:DRP4E[5] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4E[2] | GTX2:DRP4E[3] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4E[0] | GTX2:DRP4E[1] |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4D[14] GTX2:RX_DLYALIGN_OVRDSETTING[6] | GTX2:DRP4D[15] GTX2:RX_DLYALIGN_OVRDSETTING[7] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4D[12] GTX2:RX_DLYALIGN_OVRDSETTING[4] | GTX2:DRP4D[13] GTX2:RX_DLYALIGN_OVRDSETTING[5] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4D[10] GTX2:RX_DLYALIGN_OVRDSETTING[2] | GTX2:DRP4D[11] GTX2:RX_DLYALIGN_OVRDSETTING[3] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4D[8] GTX2:RX_DLYALIGN_OVRDSETTING[0] | GTX2:DRP4D[9] GTX2:RX_DLYALIGN_OVRDSETTING[1] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4D[6] GTX2:RX_DLYALIGN_LPFINC[2] | GTX2:DRP4D[7] GTX2:RX_DLYALIGN_LPFINC[3] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4D[4] GTX2:RX_DLYALIGN_LPFINC[0] | GTX2:DRP4D[5] GTX2:RX_DLYALIGN_LPFINC[1] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4D[2] GTX2:RX_DLYALIGN_CTRINC[2] | GTX2:DRP4D[3] GTX2:RX_DLYALIGN_CTRINC[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4D[0] GTX2:RX_DLYALIGN_CTRINC[0] | GTX2:DRP4D[1] GTX2:RX_DLYALIGN_CTRINC[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4C[14] GTX2:TX_DLYALIGN_OVRDSETTING[6] | GTX2:DRP4C[15] GTX2:TX_DLYALIGN_OVRDSETTING[7] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4C[12] GTX2:TX_DLYALIGN_OVRDSETTING[4] | GTX2:DRP4C[13] GTX2:TX_DLYALIGN_OVRDSETTING[5] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4C[10] GTX2:TX_DLYALIGN_OVRDSETTING[2] | GTX2:DRP4C[11] GTX2:TX_DLYALIGN_OVRDSETTING[3] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4C[8] GTX2:TX_DLYALIGN_OVRDSETTING[0] | GTX2:DRP4C[9] GTX2:TX_DLYALIGN_OVRDSETTING[1] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4C[6] GTX2:TX_DLYALIGN_LPFINC[2] | GTX2:DRP4C[7] GTX2:TX_DLYALIGN_LPFINC[3] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4C[4] GTX2:TX_DLYALIGN_LPFINC[0] | GTX2:DRP4C[5] GTX2:TX_DLYALIGN_LPFINC[1] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4C[2] GTX2:TX_DLYALIGN_CTRINC[2] | GTX2:DRP4C[3] GTX2:TX_DLYALIGN_CTRINC[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4C[0] GTX2:TX_DLYALIGN_CTRINC[0] | GTX2:DRP4C[1] GTX2:TX_DLYALIGN_CTRINC[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4B[14] GTX2:RX_EN_REALIGN_RESET_BUF2 | GTX2:DRP4B[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4B[12] | GTX2:DRP4B[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4B[10] GTX2:RX_DLYALIGN_EDGESET[4] | GTX2:DRP4B[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4B[8] GTX2:RX_DLYALIGN_EDGESET[2] | GTX2:DRP4B[9] GTX2:RX_DLYALIGN_EDGESET[3] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4B[6] GTX2:RX_DLYALIGN_EDGESET[0] | GTX2:DRP4B[7] GTX2:RX_DLYALIGN_EDGESET[1] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4B[4] GTX2:TX_DLYALIGN_MONSEL[1] | GTX2:DRP4B[5] GTX2:TX_DLYALIGN_MONSEL[2] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4B[2] GTX2:RX_DLYALIGN_MONSEL[2] | GTX2:DRP4B[3] GTX2:TX_DLYALIGN_MONSEL[0] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4B[0] GTX2:RX_DLYALIGN_MONSEL[0] | GTX2:DRP4B[1] GTX2:RX_DLYALIGN_MONSEL[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4A[14] | GTX2:DRP4A[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4A[12] | GTX2:DRP4A[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4A[10] | GTX2:DRP4A[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4A[8] | GTX2:DRP4A[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4A[6] | GTX2:DRP4A[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4A[4] | GTX2:DRP4A[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4A[2] | GTX2:DRP4A[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP4A[0] | GTX2:DRP4A[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP49[14] | GTX2:DRP49[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP49[12] | GTX2:DRP49[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP49[10] | GTX2:DRP49[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP49[8] | GTX2:DRP49[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP49[6] | GTX2:DRP49[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP49[4] | GTX2:DRP49[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP49[2] | GTX2:DRP49[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP49[0] | GTX2:DRP49[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP48[14] | GTX2:DRP48[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP48[12] | GTX2:DRP48[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP48[10] | GTX2:DRP48[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP48[8] | GTX2:DRP48[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP48[6] | GTX2:DRP48[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP48[4] | GTX2:DRP48[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP48[2] | GTX2:DRP48[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX2:DRP48[0] | GTX2:DRP48[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP37[14] GTX3:PMA_TX_CFG[14] | GTX3:DRP37[15] GTX3:PMA_TX_CFG[15] |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP37[12] GTX3:PMA_TX_CFG[12] | GTX3:DRP37[13] GTX3:PMA_TX_CFG[13] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP37[10] GTX3:PMA_TX_CFG[10] | GTX3:DRP37[11] GTX3:PMA_TX_CFG[11] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP37[8] GTX3:PMA_TX_CFG[8] | GTX3:DRP37[9] GTX3:PMA_TX_CFG[9] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP37[6] GTX3:PMA_TX_CFG[6] | GTX3:DRP37[7] GTX3:PMA_TX_CFG[7] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP37[4] GTX3:PMA_TX_CFG[4] | GTX3:DRP37[5] GTX3:PMA_TX_CFG[5] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP37[2] GTX3:PMA_TX_CFG[2] | GTX3:DRP37[3] GTX3:PMA_TX_CFG[3] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP37[0] GTX3:PMA_TX_CFG[0] | GTX3:DRP37[1] GTX3:PMA_TX_CFG[1] |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP36[14] GTX3:PMA_CFG[74] | GTX3:DRP36[15] GTX3:PMA_CFG[75] |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP36[12] GTX3:PMA_CFG[72] | GTX3:DRP36[13] GTX3:PMA_CFG[73] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP36[10] GTX3:PMA_CFG[70] | GTX3:DRP36[11] GTX3:PMA_CFG[71] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP36[8] GTX3:PMA_CFG[68] | GTX3:DRP36[9] GTX3:PMA_CFG[69] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP36[6] GTX3:PMA_CFG[66] | GTX3:DRP36[7] GTX3:PMA_CFG[67] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP36[4] GTX3:PMA_CFG[64] | GTX3:DRP36[5] GTX3:PMA_CFG[65] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP36[2] GTX3:PMA_TX_CFG[18] | GTX3:DRP36[3] GTX3:PMA_TX_CFG[19] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP36[0] GTX3:PMA_TX_CFG[16] | GTX3:DRP36[1] GTX3:PMA_TX_CFG[17] |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP35[14] GTX3:PMA_CFG[62] | GTX3:DRP35[15] GTX3:PMA_CFG[63] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP35[12] GTX3:PMA_CFG[60] | GTX3:DRP35[13] GTX3:PMA_CFG[61] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP35[10] GTX3:PMA_CFG[58] | GTX3:DRP35[11] GTX3:PMA_CFG[59] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP35[8] GTX3:PMA_CFG[56] | GTX3:DRP35[9] GTX3:PMA_CFG[57] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP35[6] GTX3:PMA_CFG[54] | GTX3:DRP35[7] GTX3:PMA_CFG[55] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP35[4] GTX3:PMA_CFG[52] | GTX3:DRP35[5] GTX3:PMA_CFG[53] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP35[2] GTX3:PMA_CFG[50] | GTX3:DRP35[3] GTX3:PMA_CFG[51] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP35[0] GTX3:PMA_CFG[48] | GTX3:DRP35[1] GTX3:PMA_CFG[49] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP34[14] GTX3:PMA_CFG[46] | GTX3:DRP34[15] GTX3:PMA_CFG[47] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP34[12] GTX3:PMA_CFG[44] | GTX3:DRP34[13] GTX3:PMA_CFG[45] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP34[10] GTX3:PMA_CFG[42] | GTX3:DRP34[11] GTX3:PMA_CFG[43] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP34[8] GTX3:PMA_CFG[40] | GTX3:DRP34[9] GTX3:PMA_CFG[41] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP34[6] GTX3:PMA_CFG[38] | GTX3:DRP34[7] GTX3:PMA_CFG[39] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP34[4] GTX3:PMA_CFG[36] | GTX3:DRP34[5] GTX3:PMA_CFG[37] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP34[2] GTX3:PMA_CFG[34] | GTX3:DRP34[3] GTX3:PMA_CFG[35] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP34[0] GTX3:PMA_CFG[32] | GTX3:DRP34[1] GTX3:PMA_CFG[33] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP33[14] GTX3:PMA_CFG[30] | GTX3:DRP33[15] GTX3:PMA_CFG[31] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP33[12] GTX3:PMA_CFG[28] | GTX3:DRP33[13] GTX3:PMA_CFG[29] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP33[10] GTX3:PMA_CFG[26] | GTX3:DRP33[11] GTX3:PMA_CFG[27] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP33[8] GTX3:PMA_CFG[24] | GTX3:DRP33[9] GTX3:PMA_CFG[25] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP33[6] GTX3:PMA_CFG[22] | GTX3:DRP33[7] GTX3:PMA_CFG[23] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP33[4] GTX3:PMA_CFG[20] | GTX3:DRP33[5] GTX3:PMA_CFG[21] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP33[2] GTX3:PMA_CFG[18] | GTX3:DRP33[3] GTX3:PMA_CFG[19] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP33[0] GTX3:PMA_CFG[16] | GTX3:DRP33[1] GTX3:PMA_CFG[17] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP32[14] GTX3:PMA_CFG[14] | GTX3:DRP32[15] GTX3:PMA_CFG[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP32[12] GTX3:PMA_CFG[12] | GTX3:DRP32[13] GTX3:PMA_CFG[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP32[10] GTX3:PMA_CFG[10] | GTX3:DRP32[11] GTX3:PMA_CFG[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP32[8] GTX3:PMA_CFG[8] | GTX3:DRP32[9] GTX3:PMA_CFG[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP32[6] GTX3:PMA_CFG[6] | GTX3:DRP32[7] GTX3:PMA_CFG[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP32[4] GTX3:PMA_CFG[4] | GTX3:DRP32[5] GTX3:PMA_CFG[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP32[2] GTX3:PMA_CFG[2] | GTX3:DRP32[3] GTX3:PMA_CFG[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP32[0] GTX3:PMA_CFG[0] | GTX3:DRP32[1] GTX3:PMA_CFG[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP31[14] GTX3:TX_DATA_WIDTH[2] | GTX3:DRP31[15] GTX3:GEN_TXUSRCLK |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP31[12] GTX3:TX_DATA_WIDTH[0] | GTX3:DRP31[13] GTX3:TX_DATA_WIDTH[1] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP31[10] GTX3:PCOMMA_DETECT | GTX3:DRP31[11] GTX3:TX_BUFFER_USE |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP31[8] GTX3:PCOMMA_10B_VALUE[8] | GTX3:DRP31[9] GTX3:PCOMMA_10B_VALUE[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP31[6] GTX3:PCOMMA_10B_VALUE[6] | GTX3:DRP31[7] GTX3:PCOMMA_10B_VALUE[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP31[4] GTX3:PCOMMA_10B_VALUE[4] | GTX3:DRP31[5] GTX3:PCOMMA_10B_VALUE[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP31[2] GTX3:PCOMMA_10B_VALUE[2] | GTX3:DRP31[3] GTX3:PCOMMA_10B_VALUE[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP31[0] GTX3:PCOMMA_10B_VALUE[0] | GTX3:DRP31[1] GTX3:PCOMMA_10B_VALUE[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP30[14] ~GTX3:INV.TXUSRCLK | GTX3:DRP30[15] ~GTX3:INV.TXUSRCLK2 |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP30[12] GTX3:TX_IDLE_DEASSERT_DELAY[1] | GTX3:DRP30[13] GTX3:TX_IDLE_DEASSERT_DELAY[2] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP30[10] GTX3:MCOMMA_DETECT | GTX3:DRP30[11] GTX3:TX_IDLE_DEASSERT_DELAY[0] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP30[8] GTX3:MCOMMA_10B_VALUE[8] | GTX3:DRP30[9] GTX3:MCOMMA_10B_VALUE[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP30[6] GTX3:MCOMMA_10B_VALUE[6] | GTX3:DRP30[7] GTX3:MCOMMA_10B_VALUE[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP30[4] GTX3:MCOMMA_10B_VALUE[4] | GTX3:DRP30[5] GTX3:MCOMMA_10B_VALUE[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP30[2] GTX3:MCOMMA_10B_VALUE[2] | GTX3:DRP30[3] GTX3:MCOMMA_10B_VALUE[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP30[0] GTX3:MCOMMA_10B_VALUE[0] | GTX3:DRP30[1] GTX3:MCOMMA_10B_VALUE[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP47[14] | GTX3:DRP47[15] |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP47[12] | GTX3:DRP47[13] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP47[10] | GTX3:DRP47[11] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP47[8] GTX3:TXOUTCLK_DLY[8] | GTX3:DRP47[9] GTX3:TXOUTCLK_DLY[9] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP47[6] GTX3:TXOUTCLK_DLY[6] | GTX3:DRP47[7] GTX3:TXOUTCLK_DLY[7] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP47[4] GTX3:TXOUTCLK_DLY[4] | GTX3:DRP47[5] GTX3:TXOUTCLK_DLY[5] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP47[2] GTX3:TXOUTCLK_DLY[2] | GTX3:DRP47[3] GTX3:TXOUTCLK_DLY[3] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP47[0] GTX3:TXOUTCLK_DLY[0] | GTX3:DRP47[1] GTX3:TXOUTCLK_DLY[1] |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP46[14] | GTX3:DRP46[15] |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP46[12] | GTX3:DRP46[13] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP46[10] | GTX3:DRP46[11] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP46[8] GTX3:RXRECCLK_DLY[8] | GTX3:DRP46[9] GTX3:RXRECCLK_DLY[9] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP46[6] GTX3:RXRECCLK_DLY[6] | GTX3:DRP46[7] GTX3:RXRECCLK_DLY[7] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP46[4] GTX3:RXRECCLK_DLY[4] | GTX3:DRP46[5] GTX3:RXRECCLK_DLY[5] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP46[2] GTX3:RXRECCLK_DLY[2] | GTX3:DRP46[3] GTX3:RXRECCLK_DLY[3] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP46[0] GTX3:RXRECCLK_DLY[0] | GTX3:DRP46[1] GTX3:RXRECCLK_DLY[1] |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP45[14] | GTX3:DRP45[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP45[12] | GTX3:DRP45[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP45[10] GTX3:TX_USRCLK_CFG[4] | GTX3:DRP45[11] GTX3:TX_USRCLK_CFG[5] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP45[8] GTX3:TX_USRCLK_CFG[2] | GTX3:DRP45[9] GTX3:TX_USRCLK_CFG[3] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP45[6] GTX3:TX_USRCLK_CFG[0] | GTX3:DRP45[7] GTX3:TX_USRCLK_CFG[1] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP45[4] GTX3:TX_BYTECLK_CFG[4] | GTX3:DRP45[5] GTX3:TX_BYTECLK_CFG[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP45[2] GTX3:TX_BYTECLK_CFG[2] | GTX3:DRP45[3] GTX3:TX_BYTECLK_CFG[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP45[0] GTX3:TX_BYTECLK_CFG[0] | GTX3:DRP45[1] GTX3:TX_BYTECLK_CFG[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP44[14] | GTX3:DRP44[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP44[12] | GTX3:DRP44[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP44[10] | GTX3:DRP44[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP44[8] GTX3:POWER_SAVE[8] | GTX3:DRP44[9] GTX3:POWER_SAVE[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP44[6] GTX3:POWER_SAVE[6] | GTX3:DRP44[7] GTX3:POWER_SAVE[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP44[4] GTX3:POWER_SAVE[4] | GTX3:DRP44[5] GTX3:POWER_SAVE[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP44[2] GTX3:POWER_SAVE[2] | GTX3:DRP44[3] GTX3:POWER_SAVE[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP44[0] GTX3:POWER_SAVE[0] | GTX3:DRP44[1] GTX3:POWER_SAVE[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP43[14] ~GTX3:INV.GREFCLKTX | GTX3:DRP43[15] ~GTX3:INV.GREFCLKRX |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP43[12] | GTX3:DRP43[13] ~GTX3:INV.SCANCLK |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP43[10] ~GTX3:INV.TSTCLK0 | GTX3:DRP43[11] ~GTX3:INV.TSTCLK1 |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP43[8] | GTX3:DRP43[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP43[6] | GTX3:DRP43[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP43[4] GTX3:RXRECCLK_CTRL[1] | GTX3:DRP43[5] GTX3:RXRECCLK_CTRL[0] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP43[2] GTX3:TXOUTCLK_CTRL[0] | GTX3:DRP43[3] GTX3:RXRECCLK_CTRL[2] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP43[0] GTX3:TXOUTCLK_CTRL[2] | GTX3:DRP43[1] GTX3:TXOUTCLK_CTRL[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP42[14] GTX3:TST_ATTR[14] | GTX3:DRP42[15] GTX3:TST_ATTR[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP42[12] GTX3:TST_ATTR[12] | GTX3:DRP42[13] GTX3:TST_ATTR[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP42[10] GTX3:TST_ATTR[10] | GTX3:DRP42[11] GTX3:TST_ATTR[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP42[8] GTX3:TST_ATTR[8] | GTX3:DRP42[9] GTX3:TST_ATTR[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP42[6] GTX3:TST_ATTR[6] | GTX3:DRP42[7] GTX3:TST_ATTR[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP42[4] GTX3:TST_ATTR[4] | GTX3:DRP42[5] GTX3:TST_ATTR[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP42[2] GTX3:TST_ATTR[2] | GTX3:DRP42[3] GTX3:TST_ATTR[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP42[0] GTX3:TST_ATTR[0] | GTX3:DRP42[1] GTX3:TST_ATTR[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP41[14] GTX3:TST_ATTR[30] | GTX3:DRP41[15] GTX3:TST_ATTR[31] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP41[12] GTX3:TST_ATTR[28] | GTX3:DRP41[13] GTX3:TST_ATTR[29] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP41[10] GTX3:TST_ATTR[26] | GTX3:DRP41[11] GTX3:TST_ATTR[27] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP41[8] GTX3:TST_ATTR[24] | GTX3:DRP41[9] GTX3:TST_ATTR[25] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP41[6] GTX3:TST_ATTR[22] | GTX3:DRP41[7] GTX3:TST_ATTR[23] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP41[4] GTX3:TST_ATTR[20] | GTX3:DRP41[5] GTX3:TST_ATTR[21] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP41[2] GTX3:TST_ATTR[18] | GTX3:DRP41[3] GTX3:TST_ATTR[19] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP41[0] GTX3:TST_ATTR[16] | GTX3:DRP41[1] GTX3:TST_ATTR[17] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP40[14] | GTX3:DRP40[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP40[12] | GTX3:DRP40[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP40[10] | GTX3:DRP40[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:A_RXEQMIX[8] GTX3:DRP40[8] | GTX3:A_RXEQMIX[9] GTX3:DRP40[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:A_RXEQMIX[6] GTX3:DRP40[6] | GTX3:A_RXEQMIX[7] GTX3:DRP40[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:A_RXEQMIX[4] GTX3:DRP40[4] | GTX3:A_RXEQMIX[5] GTX3:DRP40[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:A_RXEQMIX[2] GTX3:DRP40[2] | GTX3:A_RXEQMIX[3] GTX3:DRP40[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:A_RXEQMIX[0] GTX3:DRP40[0] | GTX3:A_RXEQMIX[1] GTX3:DRP40[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4F[14] | GTX3:DRP4F[15] |
| 62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4F[12] | GTX3:DRP4F[13] |
| 61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4F[10] | GTX3:DRP4F[11] |
| 60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4F[8] | GTX3:DRP4F[9] |
| 59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4F[6] | GTX3:DRP4F[7] |
| 58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4F[4] | GTX3:DRP4F[5] |
| 57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4F[2] | GTX3:DRP4F[3] |
| 56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4F[0] | GTX3:DRP4F[1] |
| 55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4E[14] | GTX3:DRP4E[15] |
| 54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4E[12] | GTX3:DRP4E[13] |
| 53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4E[10] | GTX3:DRP4E[11] |
| 52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4E[8] | GTX3:DRP4E[9] |
| 51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4E[6] | GTX3:DRP4E[7] |
| 50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4E[4] | GTX3:DRP4E[5] |
| 49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4E[2] | GTX3:DRP4E[3] |
| 48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4E[0] | GTX3:DRP4E[1] |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4D[14] GTX3:RX_DLYALIGN_OVRDSETTING[6] | GTX3:DRP4D[15] GTX3:RX_DLYALIGN_OVRDSETTING[7] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4D[12] GTX3:RX_DLYALIGN_OVRDSETTING[4] | GTX3:DRP4D[13] GTX3:RX_DLYALIGN_OVRDSETTING[5] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4D[10] GTX3:RX_DLYALIGN_OVRDSETTING[2] | GTX3:DRP4D[11] GTX3:RX_DLYALIGN_OVRDSETTING[3] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4D[8] GTX3:RX_DLYALIGN_OVRDSETTING[0] | GTX3:DRP4D[9] GTX3:RX_DLYALIGN_OVRDSETTING[1] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4D[6] GTX3:RX_DLYALIGN_LPFINC[2] | GTX3:DRP4D[7] GTX3:RX_DLYALIGN_LPFINC[3] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4D[4] GTX3:RX_DLYALIGN_LPFINC[0] | GTX3:DRP4D[5] GTX3:RX_DLYALIGN_LPFINC[1] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4D[2] GTX3:RX_DLYALIGN_CTRINC[2] | GTX3:DRP4D[3] GTX3:RX_DLYALIGN_CTRINC[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4D[0] GTX3:RX_DLYALIGN_CTRINC[0] | GTX3:DRP4D[1] GTX3:RX_DLYALIGN_CTRINC[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4C[14] GTX3:TX_DLYALIGN_OVRDSETTING[6] | GTX3:DRP4C[15] GTX3:TX_DLYALIGN_OVRDSETTING[7] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4C[12] GTX3:TX_DLYALIGN_OVRDSETTING[4] | GTX3:DRP4C[13] GTX3:TX_DLYALIGN_OVRDSETTING[5] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4C[10] GTX3:TX_DLYALIGN_OVRDSETTING[2] | GTX3:DRP4C[11] GTX3:TX_DLYALIGN_OVRDSETTING[3] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4C[8] GTX3:TX_DLYALIGN_OVRDSETTING[0] | GTX3:DRP4C[9] GTX3:TX_DLYALIGN_OVRDSETTING[1] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4C[6] GTX3:TX_DLYALIGN_LPFINC[2] | GTX3:DRP4C[7] GTX3:TX_DLYALIGN_LPFINC[3] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4C[4] GTX3:TX_DLYALIGN_LPFINC[0] | GTX3:DRP4C[5] GTX3:TX_DLYALIGN_LPFINC[1] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4C[2] GTX3:TX_DLYALIGN_CTRINC[2] | GTX3:DRP4C[3] GTX3:TX_DLYALIGN_CTRINC[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4C[0] GTX3:TX_DLYALIGN_CTRINC[0] | GTX3:DRP4C[1] GTX3:TX_DLYALIGN_CTRINC[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4B[14] GTX3:RX_EN_REALIGN_RESET_BUF2 | GTX3:DRP4B[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4B[12] | GTX3:DRP4B[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4B[10] GTX3:RX_DLYALIGN_EDGESET[4] | GTX3:DRP4B[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4B[8] GTX3:RX_DLYALIGN_EDGESET[2] | GTX3:DRP4B[9] GTX3:RX_DLYALIGN_EDGESET[3] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4B[6] GTX3:RX_DLYALIGN_EDGESET[0] | GTX3:DRP4B[7] GTX3:RX_DLYALIGN_EDGESET[1] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4B[4] GTX3:TX_DLYALIGN_MONSEL[1] | GTX3:DRP4B[5] GTX3:TX_DLYALIGN_MONSEL[2] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4B[2] GTX3:RX_DLYALIGN_MONSEL[2] | GTX3:DRP4B[3] GTX3:TX_DLYALIGN_MONSEL[0] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4B[0] GTX3:RX_DLYALIGN_MONSEL[0] | GTX3:DRP4B[1] GTX3:RX_DLYALIGN_MONSEL[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4A[14] | GTX3:DRP4A[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4A[12] | GTX3:DRP4A[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4A[10] | GTX3:DRP4A[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4A[8] | GTX3:DRP4A[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4A[6] | GTX3:DRP4A[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4A[4] | GTX3:DRP4A[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4A[2] | GTX3:DRP4A[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP4A[0] | GTX3:DRP4A[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP49[14] | GTX3:DRP49[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP49[12] | GTX3:DRP49[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP49[10] | GTX3:DRP49[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP49[8] | GTX3:DRP49[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP49[6] | GTX3:DRP49[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP49[4] | GTX3:DRP49[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP49[2] | GTX3:DRP49[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP49[0] | GTX3:DRP49[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP48[14] | GTX3:DRP48[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP48[12] | GTX3:DRP48[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP48[10] | GTX3:DRP48[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP48[8] | GTX3:DRP48[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP48[6] | GTX3:DRP48[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP48[4] | GTX3:DRP48[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP48[2] | GTX3:DRP48[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | GTX3:DRP48[0] | GTX3:DRP48[1] |
| BUFDS0:CLKCM_CFG | 11.28.39 |
|---|---|
| BUFDS0:CLKRCV_TRST | 15.28.30 |
| BUFDS1:CLKCM_CFG | 11.29.39 |
| BUFDS1:CLKRCV_TRST | 15.29.30 |
| GTX0:AC_CAP_DIS | 2.28.58 |
| GTX0:A_DFEDLYOVRD | 5.28.31 |
| GTX0:A_DFETAPOVRD | 5.29.31 |
| GTX0:A_GTXRXRESET | 3.28.3 |
| GTX0:A_GTXTXRESET | 3.29.2 |
| GTX0:A_PLLCLKRXRESET | 3.28.38 |
| GTX0:A_PLLCLKTXRESET | 4.28.6 |
| GTX0:A_PLLRXRESET | 3.28.37 |
| GTX0:A_PLLTXRESET | 4.28.5 |
| GTX0:A_PRBSCNTRESET | 5.28.23 |
| GTX0:A_RXBUFRESET | 3.29.3 |
| GTX0:A_RXCDRFREQRESET | 3.29.5 |
| GTX0:A_RXCDRHOLD | 3.28.5 |
| GTX0:A_RXCDRPHASERESET | 3.28.6 |
| GTX0:A_RXCDRRESET | 3.28.2 |
| GTX0:A_RXDFERESET | 3.29.6 |
| GTX0:A_RXENPMAPHASEALIGN | 4.28.47 |
| GTX0:A_RXENSAMPLEALIGN | 5.28.15 |
| GTX0:A_RXPLLLKDETEN | 3.29.37 |
| GTX0:A_RXPLLPOWERDOWN | 3.28.39 |
| GTX0:A_RXPMASETPHASE | 4.29.46 |
| GTX0:A_RXPOLARITY | 4.28.45 |
| GTX0:A_RXRESET | 3.28.4 |
| GTX0:A_TXDEEMPH | 7.29.31 |
| GTX0:A_TXELECIDLE | 4.28.15 |
| GTX0:A_TXENPMAPHASEALIGN | 5.29.14 |
| GTX0:A_TXPLLLKDETEN | 4.29.5 |
| GTX0:A_TXPLLPOWERDOWN | 4.28.7 |
| GTX0:A_TXPMASETPHASE | 5.28.14 |
| GTX0:A_TXPOLARITY | 4.29.45 |
| GTX0:A_TXPRBSFORCEERR | 5.28.21 |
| GTX0:A_TXRESET | 3.29.4 |
| GTX0:A_TXSWING | 7.28.31 |
| GTX0:CHAN_BOND_KEEP_ALIGN | 1.28.15 |
| GTX0:CHAN_BOND_SEQ_2_USE | 1.28.23 |
| GTX0:CLK_CORRECT_USE | 1.28.47 |
| GTX0:CLK_COR_INSERT_IDLE_FLAG | 2.29.15 |
| GTX0:CLK_COR_KEEP_IDLE | 1.29.55 |
| GTX0:CLK_COR_PRECEDENCE | 1.29.47 |
| GTX0:CLK_COR_SEQ_2_USE | 2.28.15 |
| GTX0:COMMA_DOUBLE | 5.28.61 |
| GTX0:DEC_MCOMMA_DETECT | 2.29.37 |
| GTX0:DEC_PCOMMA_DETECT | 2.28.37 |
| GTX0:DEC_VALID_COMMA_ONLY | 2.29.39 |
| GTX0:DFE_DRP_EN | 5.29.39 |
| GTX0:GEN_RXUSRCLK | 2.29.63 |
| GTX0:GEN_TXUSRCLK | 6.29.15 |
| GTX0:GTX_CFG_PWRUP | 2.29.57 |
| GTX0:LOOPBACK_DRP_EN | 5.28.16 |
| GTX0:MASTER_DRP_EN | 3.29.7 |
| GTX0:MCOMMA_DETECT | 6.28.5 |
| GTX0:PCI_EXPRESS_MODE | 4.29.15 |
| GTX0:PCOMMA_DETECT | 6.28.13 |
| GTX0:PDELIDLE_DRP_EN | 4.29.6 |
| GTX0:PHASEALIGN_DRP_EN | 5.29.15 |
| GTX0:PLL_DRP_EN | 3.29.38 |
| GTX0:PMA_CAS_CLK_EN | 4.29.23 |
| GTX0:POLARITY_DRP_EN | 4.28.46 |
| GTX0:PRBS_DRP_EN | 5.29.23 |
| GTX0:RCV_TERM_GND | 5.29.51 |
| GTX0:RCV_TERM_VTTRX | 5.28.52 |
| GTX0:RESET_DRP_EN | 3.28.7 |
| GTX0:RXBUF_OVRD_THRESH | 1.28.38 |
| GTX0:RXGEARBOX_USE | 3.29.1 |
| GTX0:RXPLL_STARTUP_EN | 3.29.27 |
| GTX0:RXPRBSERR_LOOPBACK | 5.28.20 |
| GTX0:RX_BUFFER_USE | 0.28.39 |
| GTX0:RX_CDR_FORCE_ROTATE | 2.29.23 |
| GTX0:RX_DECODE_SEQ_MATCH | 2.29.38 |
| GTX0:RX_EN_IDLE_HOLD_CDR | 5.29.28 |
| GTX0:RX_EN_IDLE_HOLD_DFE | 5.29.29 |
| GTX0:RX_EN_IDLE_RESET_BUF | 1.28.29 |
| GTX0:RX_EN_IDLE_RESET_FR | 5.28.29 |
| GTX0:RX_EN_IDLE_RESET_PH | 1.29.23 |
| GTX0:RX_EN_MODE_RESET_BUF | 1.29.15 |
| GTX0:RX_EN_RATE_RESET_BUF | 1.29.7 |
| GTX0:RX_EN_REALIGN_RESET_BUF | 1.28.7 |
| GTX0:RX_EN_REALIGN_RESET_BUF2 | 9.28.31 |
| GTX0:RX_LOSS_OF_SYNC_FSM | 0.29.39 |
| GTX0:RX_OVERSAMPLE_MODE | 3.29.39 |
| GTX0:SHOW_REALIGN_COMMA | 2.28.23 |
| GTX0:TERMINATION_OVRD | 5.28.51 |
| GTX0:TXDRIVE_DRP_EN | 7.28.39 |
| GTX0:TXGEARBOX_USE | 5.29.63 |
| GTX0:TXOUTCLKPCS_SEL | 7.28.7 |
| GTX0:TXPLL_STARTUP_EN | 3.29.59 |
| GTX0:TX_BUFFER_USE | 6.29.13 |
| GTX0:TX_EN_RATE_RESET_BUF | 4.29.63 |
| GTX0:TX_OVERSAMPLE_MODE | 4.29.7 |
| GTX0:TX_PMADATA_OPT | 4.29.47 |
| GTX0:USR_CODE_ERR_CLR | 2.28.38 |
| GTX1:AC_CAP_DIS | 12.28.58 |
| GTX1:A_DFEDLYOVRD | 15.28.31 |
| GTX1:A_DFETAPOVRD | 15.29.31 |
| GTX1:A_GTXRXRESET | 13.28.3 |
| GTX1:A_GTXTXRESET | 13.29.2 |
| GTX1:A_PLLCLKRXRESET | 13.28.38 |
| GTX1:A_PLLCLKTXRESET | 14.28.6 |
| GTX1:A_PLLRXRESET | 13.28.37 |
| GTX1:A_PLLTXRESET | 14.28.5 |
| GTX1:A_PRBSCNTRESET | 15.28.23 |
| GTX1:A_RXBUFRESET | 13.29.3 |
| GTX1:A_RXCDRFREQRESET | 13.29.5 |
| GTX1:A_RXCDRHOLD | 13.28.5 |
| GTX1:A_RXCDRPHASERESET | 13.28.6 |
| GTX1:A_RXCDRRESET | 13.28.2 |
| GTX1:A_RXDFERESET | 13.29.6 |
| GTX1:A_RXENPMAPHASEALIGN | 14.28.47 |
| GTX1:A_RXENSAMPLEALIGN | 15.28.15 |
| GTX1:A_RXPLLLKDETEN | 13.29.37 |
| GTX1:A_RXPLLPOWERDOWN | 13.28.39 |
| GTX1:A_RXPMASETPHASE | 14.29.46 |
| GTX1:A_RXPOLARITY | 14.28.45 |
| GTX1:A_RXRESET | 13.28.4 |
| GTX1:A_TXDEEMPH | 17.29.31 |
| GTX1:A_TXELECIDLE | 14.28.15 |
| GTX1:A_TXENPMAPHASEALIGN | 15.29.14 |
| GTX1:A_TXPLLLKDETEN | 14.29.5 |
| GTX1:A_TXPLLPOWERDOWN | 14.28.7 |
| GTX1:A_TXPMASETPHASE | 15.28.14 |
| GTX1:A_TXPOLARITY | 14.29.45 |
| GTX1:A_TXPRBSFORCEERR | 15.28.21 |
| GTX1:A_TXRESET | 13.29.4 |
| GTX1:A_TXSWING | 17.28.31 |
| GTX1:CHAN_BOND_KEEP_ALIGN | 11.28.15 |
| GTX1:CHAN_BOND_SEQ_2_USE | 11.28.23 |
| GTX1:CLK_CORRECT_USE | 11.28.47 |
| GTX1:CLK_COR_INSERT_IDLE_FLAG | 12.29.15 |
| GTX1:CLK_COR_KEEP_IDLE | 11.29.55 |
| GTX1:CLK_COR_PRECEDENCE | 11.29.47 |
| GTX1:CLK_COR_SEQ_2_USE | 12.28.15 |
| GTX1:COMMA_DOUBLE | 15.28.61 |
| GTX1:DEC_MCOMMA_DETECT | 12.29.37 |
| GTX1:DEC_PCOMMA_DETECT | 12.28.37 |
| GTX1:DEC_VALID_COMMA_ONLY | 12.29.39 |
| GTX1:DFE_DRP_EN | 15.29.39 |
| GTX1:GEN_RXUSRCLK | 12.29.63 |
| GTX1:GEN_TXUSRCLK | 16.29.15 |
| GTX1:GTX_CFG_PWRUP | 12.29.57 |
| GTX1:LOOPBACK_DRP_EN | 15.28.16 |
| GTX1:MASTER_DRP_EN | 13.29.7 |
| GTX1:MCOMMA_DETECT | 16.28.5 |
| GTX1:PCI_EXPRESS_MODE | 14.29.15 |
| GTX1:PCOMMA_DETECT | 16.28.13 |
| GTX1:PDELIDLE_DRP_EN | 14.29.6 |
| GTX1:PHASEALIGN_DRP_EN | 15.29.15 |
| GTX1:PLL_DRP_EN | 13.29.38 |
| GTX1:PMA_CAS_CLK_EN | 14.29.23 |
| GTX1:POLARITY_DRP_EN | 14.28.46 |
| GTX1:PRBS_DRP_EN | 15.29.23 |
| GTX1:RCV_TERM_GND | 15.29.51 |
| GTX1:RCV_TERM_VTTRX | 15.28.52 |
| GTX1:RESET_DRP_EN | 13.28.7 |
| GTX1:RXBUF_OVRD_THRESH | 11.28.38 |
| GTX1:RXGEARBOX_USE | 13.29.1 |
| GTX1:RXPLL_STARTUP_EN | 13.29.27 |
| GTX1:RXPRBSERR_LOOPBACK | 15.28.20 |
| GTX1:RX_BUFFER_USE | 10.28.39 |
| GTX1:RX_CDR_FORCE_ROTATE | 12.29.23 |
| GTX1:RX_DECODE_SEQ_MATCH | 12.29.38 |
| GTX1:RX_EN_IDLE_HOLD_CDR | 15.29.28 |
| GTX1:RX_EN_IDLE_HOLD_DFE | 15.29.29 |
| GTX1:RX_EN_IDLE_RESET_BUF | 11.28.29 |
| GTX1:RX_EN_IDLE_RESET_FR | 15.28.29 |
| GTX1:RX_EN_IDLE_RESET_PH | 11.29.23 |
| GTX1:RX_EN_MODE_RESET_BUF | 11.29.15 |
| GTX1:RX_EN_RATE_RESET_BUF | 11.29.7 |
| GTX1:RX_EN_REALIGN_RESET_BUF | 11.28.7 |
| GTX1:RX_EN_REALIGN_RESET_BUF2 | 19.28.31 |
| GTX1:RX_LOSS_OF_SYNC_FSM | 10.29.39 |
| GTX1:RX_OVERSAMPLE_MODE | 13.29.39 |
| GTX1:SHOW_REALIGN_COMMA | 12.28.23 |
| GTX1:TERMINATION_OVRD | 15.28.51 |
| GTX1:TXDRIVE_DRP_EN | 17.28.39 |
| GTX1:TXGEARBOX_USE | 15.29.63 |
| GTX1:TXOUTCLKPCS_SEL | 17.28.7 |
| GTX1:TXPLL_STARTUP_EN | 13.29.59 |
| GTX1:TX_BUFFER_USE | 16.29.13 |
| GTX1:TX_EN_RATE_RESET_BUF | 14.29.63 |
| GTX1:TX_OVERSAMPLE_MODE | 14.29.7 |
| GTX1:TX_PMADATA_OPT | 14.29.47 |
| GTX1:USR_CODE_ERR_CLR | 12.28.38 |
| GTX2:AC_CAP_DIS | 22.28.58 |
| GTX2:A_DFEDLYOVRD | 25.28.31 |
| GTX2:A_DFETAPOVRD | 25.29.31 |
| GTX2:A_GTXRXRESET | 23.28.3 |
| GTX2:A_GTXTXRESET | 23.29.2 |
| GTX2:A_PLLCLKRXRESET | 23.28.38 |
| GTX2:A_PLLCLKTXRESET | 24.28.6 |
| GTX2:A_PLLRXRESET | 23.28.37 |
| GTX2:A_PLLTXRESET | 24.28.5 |
| GTX2:A_PRBSCNTRESET | 25.28.23 |
| GTX2:A_RXBUFRESET | 23.29.3 |
| GTX2:A_RXCDRFREQRESET | 23.29.5 |
| GTX2:A_RXCDRHOLD | 23.28.5 |
| GTX2:A_RXCDRPHASERESET | 23.28.6 |
| GTX2:A_RXCDRRESET | 23.28.2 |
| GTX2:A_RXDFERESET | 23.29.6 |
| GTX2:A_RXENPMAPHASEALIGN | 24.28.47 |
| GTX2:A_RXENSAMPLEALIGN | 25.28.15 |
| GTX2:A_RXPLLLKDETEN | 23.29.37 |
| GTX2:A_RXPLLPOWERDOWN | 23.28.39 |
| GTX2:A_RXPMASETPHASE | 24.29.46 |
| GTX2:A_RXPOLARITY | 24.28.45 |
| GTX2:A_RXRESET | 23.28.4 |
| GTX2:A_TXDEEMPH | 27.29.31 |
| GTX2:A_TXELECIDLE | 24.28.15 |
| GTX2:A_TXENPMAPHASEALIGN | 25.29.14 |
| GTX2:A_TXPLLLKDETEN | 24.29.5 |
| GTX2:A_TXPLLPOWERDOWN | 24.28.7 |
| GTX2:A_TXPMASETPHASE | 25.28.14 |
| GTX2:A_TXPOLARITY | 24.29.45 |
| GTX2:A_TXPRBSFORCEERR | 25.28.21 |
| GTX2:A_TXRESET | 23.29.4 |
| GTX2:A_TXSWING | 27.28.31 |
| GTX2:CHAN_BOND_KEEP_ALIGN | 21.28.15 |
| GTX2:CHAN_BOND_SEQ_2_USE | 21.28.23 |
| GTX2:CLK_CORRECT_USE | 21.28.47 |
| GTX2:CLK_COR_INSERT_IDLE_FLAG | 22.29.15 |
| GTX2:CLK_COR_KEEP_IDLE | 21.29.55 |
| GTX2:CLK_COR_PRECEDENCE | 21.29.47 |
| GTX2:CLK_COR_SEQ_2_USE | 22.28.15 |
| GTX2:COMMA_DOUBLE | 25.28.61 |
| GTX2:DEC_MCOMMA_DETECT | 22.29.37 |
| GTX2:DEC_PCOMMA_DETECT | 22.28.37 |
| GTX2:DEC_VALID_COMMA_ONLY | 22.29.39 |
| GTX2:DFE_DRP_EN | 25.29.39 |
| GTX2:GEN_RXUSRCLK | 22.29.63 |
| GTX2:GEN_TXUSRCLK | 26.29.15 |
| GTX2:GTX_CFG_PWRUP | 22.29.57 |
| GTX2:LOOPBACK_DRP_EN | 25.28.16 |
| GTX2:MASTER_DRP_EN | 23.29.7 |
| GTX2:MCOMMA_DETECT | 26.28.5 |
| GTX2:PCI_EXPRESS_MODE | 24.29.15 |
| GTX2:PCOMMA_DETECT | 26.28.13 |
| GTX2:PDELIDLE_DRP_EN | 24.29.6 |
| GTX2:PHASEALIGN_DRP_EN | 25.29.15 |
| GTX2:PLL_DRP_EN | 23.29.38 |
| GTX2:PMA_CAS_CLK_EN | 24.29.23 |
| GTX2:POLARITY_DRP_EN | 24.28.46 |
| GTX2:PRBS_DRP_EN | 25.29.23 |
| GTX2:RCV_TERM_GND | 25.29.51 |
| GTX2:RCV_TERM_VTTRX | 25.28.52 |
| GTX2:RESET_DRP_EN | 23.28.7 |
| GTX2:RXBUF_OVRD_THRESH | 21.28.38 |
| GTX2:RXGEARBOX_USE | 23.29.1 |
| GTX2:RXPLL_STARTUP_EN | 23.29.27 |
| GTX2:RXPRBSERR_LOOPBACK | 25.28.20 |
| GTX2:RX_BUFFER_USE | 20.28.39 |
| GTX2:RX_CDR_FORCE_ROTATE | 22.29.23 |
| GTX2:RX_DECODE_SEQ_MATCH | 22.29.38 |
| GTX2:RX_EN_IDLE_HOLD_CDR | 25.29.28 |
| GTX2:RX_EN_IDLE_HOLD_DFE | 25.29.29 |
| GTX2:RX_EN_IDLE_RESET_BUF | 21.28.29 |
| GTX2:RX_EN_IDLE_RESET_FR | 25.28.29 |
| GTX2:RX_EN_IDLE_RESET_PH | 21.29.23 |
| GTX2:RX_EN_MODE_RESET_BUF | 21.29.15 |
| GTX2:RX_EN_RATE_RESET_BUF | 21.29.7 |
| GTX2:RX_EN_REALIGN_RESET_BUF | 21.28.7 |
| GTX2:RX_EN_REALIGN_RESET_BUF2 | 29.28.31 |
| GTX2:RX_LOSS_OF_SYNC_FSM | 20.29.39 |
| GTX2:RX_OVERSAMPLE_MODE | 23.29.39 |
| GTX2:SHOW_REALIGN_COMMA | 22.28.23 |
| GTX2:TERMINATION_OVRD | 25.28.51 |
| GTX2:TXDRIVE_DRP_EN | 27.28.39 |
| GTX2:TXGEARBOX_USE | 25.29.63 |
| GTX2:TXOUTCLKPCS_SEL | 27.28.7 |
| GTX2:TXPLL_STARTUP_EN | 23.29.59 |
| GTX2:TX_BUFFER_USE | 26.29.13 |
| GTX2:TX_EN_RATE_RESET_BUF | 24.29.63 |
| GTX2:TX_OVERSAMPLE_MODE | 24.29.7 |
| GTX2:TX_PMADATA_OPT | 24.29.47 |
| GTX2:USR_CODE_ERR_CLR | 22.28.38 |
| GTX3:AC_CAP_DIS | 32.28.58 |
| GTX3:A_DFEDLYOVRD | 35.28.31 |
| GTX3:A_DFETAPOVRD | 35.29.31 |
| GTX3:A_GTXRXRESET | 33.28.3 |
| GTX3:A_GTXTXRESET | 33.29.2 |
| GTX3:A_PLLCLKRXRESET | 33.28.38 |
| GTX3:A_PLLCLKTXRESET | 34.28.6 |
| GTX3:A_PLLRXRESET | 33.28.37 |
| GTX3:A_PLLTXRESET | 34.28.5 |
| GTX3:A_PRBSCNTRESET | 35.28.23 |
| GTX3:A_RXBUFRESET | 33.29.3 |
| GTX3:A_RXCDRFREQRESET | 33.29.5 |
| GTX3:A_RXCDRHOLD | 33.28.5 |
| GTX3:A_RXCDRPHASERESET | 33.28.6 |
| GTX3:A_RXCDRRESET | 33.28.2 |
| GTX3:A_RXDFERESET | 33.29.6 |
| GTX3:A_RXENPMAPHASEALIGN | 34.28.47 |
| GTX3:A_RXENSAMPLEALIGN | 35.28.15 |
| GTX3:A_RXPLLLKDETEN | 33.29.37 |
| GTX3:A_RXPLLPOWERDOWN | 33.28.39 |
| GTX3:A_RXPMASETPHASE | 34.29.46 |
| GTX3:A_RXPOLARITY | 34.28.45 |
| GTX3:A_RXRESET | 33.28.4 |
| GTX3:A_TXDEEMPH | 37.29.31 |
| GTX3:A_TXELECIDLE | 34.28.15 |
| GTX3:A_TXENPMAPHASEALIGN | 35.29.14 |
| GTX3:A_TXPLLLKDETEN | 34.29.5 |
| GTX3:A_TXPLLPOWERDOWN | 34.28.7 |
| GTX3:A_TXPMASETPHASE | 35.28.14 |
| GTX3:A_TXPOLARITY | 34.29.45 |
| GTX3:A_TXPRBSFORCEERR | 35.28.21 |
| GTX3:A_TXRESET | 33.29.4 |
| GTX3:A_TXSWING | 37.28.31 |
| GTX3:CHAN_BOND_KEEP_ALIGN | 31.28.15 |
| GTX3:CHAN_BOND_SEQ_2_USE | 31.28.23 |
| GTX3:CLK_CORRECT_USE | 31.28.47 |
| GTX3:CLK_COR_INSERT_IDLE_FLAG | 32.29.15 |
| GTX3:CLK_COR_KEEP_IDLE | 31.29.55 |
| GTX3:CLK_COR_PRECEDENCE | 31.29.47 |
| GTX3:CLK_COR_SEQ_2_USE | 32.28.15 |
| GTX3:COMMA_DOUBLE | 35.28.61 |
| GTX3:DEC_MCOMMA_DETECT | 32.29.37 |
| GTX3:DEC_PCOMMA_DETECT | 32.28.37 |
| GTX3:DEC_VALID_COMMA_ONLY | 32.29.39 |
| GTX3:DFE_DRP_EN | 35.29.39 |
| GTX3:GEN_RXUSRCLK | 32.29.63 |
| GTX3:GEN_TXUSRCLK | 36.29.15 |
| GTX3:GTX_CFG_PWRUP | 32.29.57 |
| GTX3:LOOPBACK_DRP_EN | 35.28.16 |
| GTX3:MASTER_DRP_EN | 33.29.7 |
| GTX3:MCOMMA_DETECT | 36.28.5 |
| GTX3:PCI_EXPRESS_MODE | 34.29.15 |
| GTX3:PCOMMA_DETECT | 36.28.13 |
| GTX3:PDELIDLE_DRP_EN | 34.29.6 |
| GTX3:PHASEALIGN_DRP_EN | 35.29.15 |
| GTX3:PLL_DRP_EN | 33.29.38 |
| GTX3:PMA_CAS_CLK_EN | 34.29.23 |
| GTX3:POLARITY_DRP_EN | 34.28.46 |
| GTX3:PRBS_DRP_EN | 35.29.23 |
| GTX3:RCV_TERM_GND | 35.29.51 |
| GTX3:RCV_TERM_VTTRX | 35.28.52 |
| GTX3:RESET_DRP_EN | 33.28.7 |
| GTX3:RXBUF_OVRD_THRESH | 31.28.38 |
| GTX3:RXGEARBOX_USE | 33.29.1 |
| GTX3:RXPLL_STARTUP_EN | 33.29.27 |
| GTX3:RXPRBSERR_LOOPBACK | 35.28.20 |
| GTX3:RX_BUFFER_USE | 30.28.39 |
| GTX3:RX_CDR_FORCE_ROTATE | 32.29.23 |
| GTX3:RX_DECODE_SEQ_MATCH | 32.29.38 |
| GTX3:RX_EN_IDLE_HOLD_CDR | 35.29.28 |
| GTX3:RX_EN_IDLE_HOLD_DFE | 35.29.29 |
| GTX3:RX_EN_IDLE_RESET_BUF | 31.28.29 |
| GTX3:RX_EN_IDLE_RESET_FR | 35.28.29 |
| GTX3:RX_EN_IDLE_RESET_PH | 31.29.23 |
| GTX3:RX_EN_MODE_RESET_BUF | 31.29.15 |
| GTX3:RX_EN_RATE_RESET_BUF | 31.29.7 |
| GTX3:RX_EN_REALIGN_RESET_BUF | 31.28.7 |
| GTX3:RX_EN_REALIGN_RESET_BUF2 | 39.28.31 |
| GTX3:RX_LOSS_OF_SYNC_FSM | 30.29.39 |
| GTX3:RX_OVERSAMPLE_MODE | 33.29.39 |
| GTX3:SHOW_REALIGN_COMMA | 32.28.23 |
| GTX3:TERMINATION_OVRD | 35.28.51 |
| GTX3:TXDRIVE_DRP_EN | 37.28.39 |
| GTX3:TXGEARBOX_USE | 35.29.63 |
| GTX3:TXOUTCLKPCS_SEL | 37.28.7 |
| GTX3:TXPLL_STARTUP_EN | 33.29.59 |
| GTX3:TX_BUFFER_USE | 36.29.13 |
| GTX3:TX_EN_RATE_RESET_BUF | 34.29.63 |
| GTX3:TX_OVERSAMPLE_MODE | 34.29.7 |
| GTX3:TX_PMADATA_OPT | 34.29.47 |
| GTX3:USR_CODE_ERR_CLR | 32.28.38 |
| non-inverted | [0] |
| BUFDS0:MUX.HCLK_OUT | 18.28.27 | 18.29.27 |
|---|---|---|
| BUFDS1:MUX.HCLK_OUT | 18.28.28 | 18.29.28 |
| O | 0 | 0 |
| NONE | 0 | 1 |
| ODIV2 | 1 | 0 |
| CLKTESTSIG | 1 | 1 |
| BUFDS0:REFCLKOUT_DLY | 19.29.4 | 19.28.4 | 19.29.3 | 19.28.3 | 19.29.2 | 19.28.2 | 19.29.1 | 19.28.1 | 19.29.0 | 19.28.0 |
|---|---|---|---|---|---|---|---|---|---|---|
| BUFDS1:REFCLKOUT_DLY | 19.29.12 | 19.28.12 | 19.29.11 | 19.28.11 | 19.29.10 | 19.28.10 | 19.29.9 | 19.28.9 | 19.29.8 | 19.28.8 |
| GTX0:A_RXEQMIX | 8.29.4 | 8.28.4 | 8.29.3 | 8.28.3 | 8.29.2 | 8.28.2 | 8.29.1 | 8.28.1 | 8.29.0 | 8.28.0 |
| GTX0:CHAN_BOND_SEQ_1_1 | 0.29.36 | 0.28.36 | 0.29.35 | 0.28.35 | 0.29.34 | 0.28.34 | 0.29.33 | 0.28.33 | 0.29.32 | 0.28.32 |
| GTX0:CHAN_BOND_SEQ_1_2 | 0.29.44 | 0.28.44 | 0.29.43 | 0.28.43 | 0.29.42 | 0.28.42 | 0.29.41 | 0.28.41 | 0.29.40 | 0.28.40 |
| GTX0:CHAN_BOND_SEQ_1_3 | 0.29.52 | 0.28.52 | 0.29.51 | 0.28.51 | 0.29.50 | 0.28.50 | 0.29.49 | 0.28.49 | 0.29.48 | 0.28.48 |
| GTX0:CHAN_BOND_SEQ_1_4 | 0.29.60 | 0.28.60 | 0.29.59 | 0.28.59 | 0.29.58 | 0.28.58 | 0.29.57 | 0.28.57 | 0.29.56 | 0.28.56 |
| GTX0:CHAN_BOND_SEQ_2_1 | 1.29.4 | 1.28.4 | 1.29.3 | 1.28.3 | 1.29.2 | 1.28.2 | 1.29.1 | 1.28.1 | 1.29.0 | 1.28.0 |
| GTX0:CHAN_BOND_SEQ_2_2 | 1.29.12 | 1.28.12 | 1.29.11 | 1.28.11 | 1.29.10 | 1.28.10 | 1.29.9 | 1.28.9 | 1.29.8 | 1.28.8 |
| GTX0:CHAN_BOND_SEQ_2_3 | 1.29.20 | 1.28.20 | 1.29.19 | 1.28.19 | 1.29.18 | 1.28.18 | 1.29.17 | 1.28.17 | 1.29.16 | 1.28.16 |
| GTX0:CHAN_BOND_SEQ_2_4 | 1.29.28 | 1.28.28 | 1.29.27 | 1.28.27 | 1.29.26 | 1.28.26 | 1.29.25 | 1.28.25 | 1.29.24 | 1.28.24 |
| GTX0:CLK_COR_SEQ_1_1 | 1.29.44 | 1.28.44 | 1.29.43 | 1.28.43 | 1.29.42 | 1.28.42 | 1.29.41 | 1.28.41 | 1.29.40 | 1.28.40 |
| GTX0:CLK_COR_SEQ_1_2 | 1.29.52 | 1.28.52 | 1.29.51 | 1.28.51 | 1.29.50 | 1.28.50 | 1.29.49 | 1.28.49 | 1.29.48 | 1.28.48 |
| GTX0:CLK_COR_SEQ_1_3 | 1.29.60 | 1.28.60 | 1.29.59 | 1.28.59 | 1.29.58 | 1.28.58 | 1.29.57 | 1.28.57 | 1.29.56 | 1.28.56 |
| GTX0:CLK_COR_SEQ_1_4 | 2.29.4 | 2.28.4 | 2.29.3 | 2.28.3 | 2.29.2 | 2.28.2 | 2.29.1 | 2.28.1 | 2.29.0 | 2.28.0 |
| GTX0:CLK_COR_SEQ_2_1 | 2.29.12 | 2.28.12 | 2.29.11 | 2.28.11 | 2.29.10 | 2.28.10 | 2.29.9 | 2.28.9 | 2.29.8 | 2.28.8 |
| GTX0:CLK_COR_SEQ_2_2 | 2.29.20 | 2.28.20 | 2.29.19 | 2.28.19 | 2.29.18 | 2.28.18 | 2.29.17 | 2.28.17 | 2.29.16 | 2.28.16 |
| GTX0:CLK_COR_SEQ_2_3 | 2.29.28 | 2.28.28 | 2.29.27 | 2.28.27 | 2.29.26 | 2.28.26 | 2.29.25 | 2.28.25 | 2.29.24 | 2.28.24 |
| GTX0:CLK_COR_SEQ_2_4 | 2.29.36 | 2.28.36 | 2.29.35 | 2.28.35 | 2.29.34 | 2.28.34 | 2.29.33 | 2.28.33 | 2.29.32 | 2.28.32 |
| GTX0:COMMA_10B_ENABLE | 5.29.60 | 5.28.60 | 5.29.59 | 5.28.59 | 5.29.58 | 5.28.58 | 5.29.57 | 5.28.57 | 5.29.56 | 5.28.56 |
| GTX0:MCOMMA_10B_VALUE | 6.29.4 | 6.28.4 | 6.29.3 | 6.28.3 | 6.29.2 | 6.28.2 | 6.29.1 | 6.28.1 | 6.29.0 | 6.28.0 |
| GTX0:PCOMMA_10B_VALUE | 6.29.12 | 6.28.12 | 6.29.11 | 6.28.11 | 6.29.10 | 6.28.10 | 6.29.9 | 6.28.9 | 6.29.8 | 6.28.8 |
| GTX0:POWER_SAVE | 8.29.36 | 8.28.36 | 8.29.35 | 8.28.35 | 8.29.34 | 8.28.34 | 8.29.33 | 8.28.33 | 8.29.32 | 8.28.32 |
| GTX0:RXRECCLK_DLY | 8.29.52 | 8.28.52 | 8.29.51 | 8.28.51 | 8.29.50 | 8.28.50 | 8.29.49 | 8.28.49 | 8.29.48 | 8.28.48 |
| GTX0:TRANS_TIME_TO_P2 | 4.29.28 | 4.28.28 | 4.29.27 | 4.28.27 | 4.29.26 | 4.28.26 | 4.29.25 | 4.28.25 | 4.29.24 | 4.28.24 |
| GTX0:TXOUTCLK_DLY | 8.29.60 | 8.28.60 | 8.29.59 | 8.28.59 | 8.29.58 | 8.28.58 | 8.29.57 | 8.28.57 | 8.29.56 | 8.28.56 |
| GTX1:A_RXEQMIX | 18.29.4 | 18.28.4 | 18.29.3 | 18.28.3 | 18.29.2 | 18.28.2 | 18.29.1 | 18.28.1 | 18.29.0 | 18.28.0 |
| GTX1:CHAN_BOND_SEQ_1_1 | 10.29.36 | 10.28.36 | 10.29.35 | 10.28.35 | 10.29.34 | 10.28.34 | 10.29.33 | 10.28.33 | 10.29.32 | 10.28.32 |
| GTX1:CHAN_BOND_SEQ_1_2 | 10.29.44 | 10.28.44 | 10.29.43 | 10.28.43 | 10.29.42 | 10.28.42 | 10.29.41 | 10.28.41 | 10.29.40 | 10.28.40 |
| GTX1:CHAN_BOND_SEQ_1_3 | 10.29.52 | 10.28.52 | 10.29.51 | 10.28.51 | 10.29.50 | 10.28.50 | 10.29.49 | 10.28.49 | 10.29.48 | 10.28.48 |
| GTX1:CHAN_BOND_SEQ_1_4 | 10.29.60 | 10.28.60 | 10.29.59 | 10.28.59 | 10.29.58 | 10.28.58 | 10.29.57 | 10.28.57 | 10.29.56 | 10.28.56 |
| GTX1:CHAN_BOND_SEQ_2_1 | 11.29.4 | 11.28.4 | 11.29.3 | 11.28.3 | 11.29.2 | 11.28.2 | 11.29.1 | 11.28.1 | 11.29.0 | 11.28.0 |
| GTX1:CHAN_BOND_SEQ_2_2 | 11.29.12 | 11.28.12 | 11.29.11 | 11.28.11 | 11.29.10 | 11.28.10 | 11.29.9 | 11.28.9 | 11.29.8 | 11.28.8 |
| GTX1:CHAN_BOND_SEQ_2_3 | 11.29.20 | 11.28.20 | 11.29.19 | 11.28.19 | 11.29.18 | 11.28.18 | 11.29.17 | 11.28.17 | 11.29.16 | 11.28.16 |
| GTX1:CHAN_BOND_SEQ_2_4 | 11.29.28 | 11.28.28 | 11.29.27 | 11.28.27 | 11.29.26 | 11.28.26 | 11.29.25 | 11.28.25 | 11.29.24 | 11.28.24 |
| GTX1:CLK_COR_SEQ_1_1 | 11.29.44 | 11.28.44 | 11.29.43 | 11.28.43 | 11.29.42 | 11.28.42 | 11.29.41 | 11.28.41 | 11.29.40 | 11.28.40 |
| GTX1:CLK_COR_SEQ_1_2 | 11.29.52 | 11.28.52 | 11.29.51 | 11.28.51 | 11.29.50 | 11.28.50 | 11.29.49 | 11.28.49 | 11.29.48 | 11.28.48 |
| GTX1:CLK_COR_SEQ_1_3 | 11.29.60 | 11.28.60 | 11.29.59 | 11.28.59 | 11.29.58 | 11.28.58 | 11.29.57 | 11.28.57 | 11.29.56 | 11.28.56 |
| GTX1:CLK_COR_SEQ_1_4 | 12.29.4 | 12.28.4 | 12.29.3 | 12.28.3 | 12.29.2 | 12.28.2 | 12.29.1 | 12.28.1 | 12.29.0 | 12.28.0 |
| GTX1:CLK_COR_SEQ_2_1 | 12.29.12 | 12.28.12 | 12.29.11 | 12.28.11 | 12.29.10 | 12.28.10 | 12.29.9 | 12.28.9 | 12.29.8 | 12.28.8 |
| GTX1:CLK_COR_SEQ_2_2 | 12.29.20 | 12.28.20 | 12.29.19 | 12.28.19 | 12.29.18 | 12.28.18 | 12.29.17 | 12.28.17 | 12.29.16 | 12.28.16 |
| GTX1:CLK_COR_SEQ_2_3 | 12.29.28 | 12.28.28 | 12.29.27 | 12.28.27 | 12.29.26 | 12.28.26 | 12.29.25 | 12.28.25 | 12.29.24 | 12.28.24 |
| GTX1:CLK_COR_SEQ_2_4 | 12.29.36 | 12.28.36 | 12.29.35 | 12.28.35 | 12.29.34 | 12.28.34 | 12.29.33 | 12.28.33 | 12.29.32 | 12.28.32 |
| GTX1:COMMA_10B_ENABLE | 15.29.60 | 15.28.60 | 15.29.59 | 15.28.59 | 15.29.58 | 15.28.58 | 15.29.57 | 15.28.57 | 15.29.56 | 15.28.56 |
| GTX1:MCOMMA_10B_VALUE | 16.29.4 | 16.28.4 | 16.29.3 | 16.28.3 | 16.29.2 | 16.28.2 | 16.29.1 | 16.28.1 | 16.29.0 | 16.28.0 |
| GTX1:PCOMMA_10B_VALUE | 16.29.12 | 16.28.12 | 16.29.11 | 16.28.11 | 16.29.10 | 16.28.10 | 16.29.9 | 16.28.9 | 16.29.8 | 16.28.8 |
| GTX1:POWER_SAVE | 18.29.36 | 18.28.36 | 18.29.35 | 18.28.35 | 18.29.34 | 18.28.34 | 18.29.33 | 18.28.33 | 18.29.32 | 18.28.32 |
| GTX1:RXRECCLK_DLY | 18.29.52 | 18.28.52 | 18.29.51 | 18.28.51 | 18.29.50 | 18.28.50 | 18.29.49 | 18.28.49 | 18.29.48 | 18.28.48 |
| GTX1:TRANS_TIME_TO_P2 | 14.29.28 | 14.28.28 | 14.29.27 | 14.28.27 | 14.29.26 | 14.28.26 | 14.29.25 | 14.28.25 | 14.29.24 | 14.28.24 |
| GTX1:TXOUTCLK_DLY | 18.29.60 | 18.28.60 | 18.29.59 | 18.28.59 | 18.29.58 | 18.28.58 | 18.29.57 | 18.28.57 | 18.29.56 | 18.28.56 |
| GTX2:A_RXEQMIX | 28.29.4 | 28.28.4 | 28.29.3 | 28.28.3 | 28.29.2 | 28.28.2 | 28.29.1 | 28.28.1 | 28.29.0 | 28.28.0 |
| GTX2:CHAN_BOND_SEQ_1_1 | 20.29.36 | 20.28.36 | 20.29.35 | 20.28.35 | 20.29.34 | 20.28.34 | 20.29.33 | 20.28.33 | 20.29.32 | 20.28.32 |
| GTX2:CHAN_BOND_SEQ_1_2 | 20.29.44 | 20.28.44 | 20.29.43 | 20.28.43 | 20.29.42 | 20.28.42 | 20.29.41 | 20.28.41 | 20.29.40 | 20.28.40 |
| GTX2:CHAN_BOND_SEQ_1_3 | 20.29.52 | 20.28.52 | 20.29.51 | 20.28.51 | 20.29.50 | 20.28.50 | 20.29.49 | 20.28.49 | 20.29.48 | 20.28.48 |
| GTX2:CHAN_BOND_SEQ_1_4 | 20.29.60 | 20.28.60 | 20.29.59 | 20.28.59 | 20.29.58 | 20.28.58 | 20.29.57 | 20.28.57 | 20.29.56 | 20.28.56 |
| GTX2:CHAN_BOND_SEQ_2_1 | 21.29.4 | 21.28.4 | 21.29.3 | 21.28.3 | 21.29.2 | 21.28.2 | 21.29.1 | 21.28.1 | 21.29.0 | 21.28.0 |
| GTX2:CHAN_BOND_SEQ_2_2 | 21.29.12 | 21.28.12 | 21.29.11 | 21.28.11 | 21.29.10 | 21.28.10 | 21.29.9 | 21.28.9 | 21.29.8 | 21.28.8 |
| GTX2:CHAN_BOND_SEQ_2_3 | 21.29.20 | 21.28.20 | 21.29.19 | 21.28.19 | 21.29.18 | 21.28.18 | 21.29.17 | 21.28.17 | 21.29.16 | 21.28.16 |
| GTX2:CHAN_BOND_SEQ_2_4 | 21.29.28 | 21.28.28 | 21.29.27 | 21.28.27 | 21.29.26 | 21.28.26 | 21.29.25 | 21.28.25 | 21.29.24 | 21.28.24 |
| GTX2:CLK_COR_SEQ_1_1 | 21.29.44 | 21.28.44 | 21.29.43 | 21.28.43 | 21.29.42 | 21.28.42 | 21.29.41 | 21.28.41 | 21.29.40 | 21.28.40 |
| GTX2:CLK_COR_SEQ_1_2 | 21.29.52 | 21.28.52 | 21.29.51 | 21.28.51 | 21.29.50 | 21.28.50 | 21.29.49 | 21.28.49 | 21.29.48 | 21.28.48 |
| GTX2:CLK_COR_SEQ_1_3 | 21.29.60 | 21.28.60 | 21.29.59 | 21.28.59 | 21.29.58 | 21.28.58 | 21.29.57 | 21.28.57 | 21.29.56 | 21.28.56 |
| GTX2:CLK_COR_SEQ_1_4 | 22.29.4 | 22.28.4 | 22.29.3 | 22.28.3 | 22.29.2 | 22.28.2 | 22.29.1 | 22.28.1 | 22.29.0 | 22.28.0 |
| GTX2:CLK_COR_SEQ_2_1 | 22.29.12 | 22.28.12 | 22.29.11 | 22.28.11 | 22.29.10 | 22.28.10 | 22.29.9 | 22.28.9 | 22.29.8 | 22.28.8 |
| GTX2:CLK_COR_SEQ_2_2 | 22.29.20 | 22.28.20 | 22.29.19 | 22.28.19 | 22.29.18 | 22.28.18 | 22.29.17 | 22.28.17 | 22.29.16 | 22.28.16 |
| GTX2:CLK_COR_SEQ_2_3 | 22.29.28 | 22.28.28 | 22.29.27 | 22.28.27 | 22.29.26 | 22.28.26 | 22.29.25 | 22.28.25 | 22.29.24 | 22.28.24 |
| GTX2:CLK_COR_SEQ_2_4 | 22.29.36 | 22.28.36 | 22.29.35 | 22.28.35 | 22.29.34 | 22.28.34 | 22.29.33 | 22.28.33 | 22.29.32 | 22.28.32 |
| GTX2:COMMA_10B_ENABLE | 25.29.60 | 25.28.60 | 25.29.59 | 25.28.59 | 25.29.58 | 25.28.58 | 25.29.57 | 25.28.57 | 25.29.56 | 25.28.56 |
| GTX2:MCOMMA_10B_VALUE | 26.29.4 | 26.28.4 | 26.29.3 | 26.28.3 | 26.29.2 | 26.28.2 | 26.29.1 | 26.28.1 | 26.29.0 | 26.28.0 |
| GTX2:PCOMMA_10B_VALUE | 26.29.12 | 26.28.12 | 26.29.11 | 26.28.11 | 26.29.10 | 26.28.10 | 26.29.9 | 26.28.9 | 26.29.8 | 26.28.8 |
| GTX2:POWER_SAVE | 28.29.36 | 28.28.36 | 28.29.35 | 28.28.35 | 28.29.34 | 28.28.34 | 28.29.33 | 28.28.33 | 28.29.32 | 28.28.32 |
| GTX2:RXRECCLK_DLY | 28.29.52 | 28.28.52 | 28.29.51 | 28.28.51 | 28.29.50 | 28.28.50 | 28.29.49 | 28.28.49 | 28.29.48 | 28.28.48 |
| GTX2:TRANS_TIME_TO_P2 | 24.29.28 | 24.28.28 | 24.29.27 | 24.28.27 | 24.29.26 | 24.28.26 | 24.29.25 | 24.28.25 | 24.29.24 | 24.28.24 |
| GTX2:TXOUTCLK_DLY | 28.29.60 | 28.28.60 | 28.29.59 | 28.28.59 | 28.29.58 | 28.28.58 | 28.29.57 | 28.28.57 | 28.29.56 | 28.28.56 |
| GTX3:A_RXEQMIX | 38.29.4 | 38.28.4 | 38.29.3 | 38.28.3 | 38.29.2 | 38.28.2 | 38.29.1 | 38.28.1 | 38.29.0 | 38.28.0 |
| GTX3:CHAN_BOND_SEQ_1_1 | 30.29.36 | 30.28.36 | 30.29.35 | 30.28.35 | 30.29.34 | 30.28.34 | 30.29.33 | 30.28.33 | 30.29.32 | 30.28.32 |
| GTX3:CHAN_BOND_SEQ_1_2 | 30.29.44 | 30.28.44 | 30.29.43 | 30.28.43 | 30.29.42 | 30.28.42 | 30.29.41 | 30.28.41 | 30.29.40 | 30.28.40 |
| GTX3:CHAN_BOND_SEQ_1_3 | 30.29.52 | 30.28.52 | 30.29.51 | 30.28.51 | 30.29.50 | 30.28.50 | 30.29.49 | 30.28.49 | 30.29.48 | 30.28.48 |
| GTX3:CHAN_BOND_SEQ_1_4 | 30.29.60 | 30.28.60 | 30.29.59 | 30.28.59 | 30.29.58 | 30.28.58 | 30.29.57 | 30.28.57 | 30.29.56 | 30.28.56 |
| GTX3:CHAN_BOND_SEQ_2_1 | 31.29.4 | 31.28.4 | 31.29.3 | 31.28.3 | 31.29.2 | 31.28.2 | 31.29.1 | 31.28.1 | 31.29.0 | 31.28.0 |
| GTX3:CHAN_BOND_SEQ_2_2 | 31.29.12 | 31.28.12 | 31.29.11 | 31.28.11 | 31.29.10 | 31.28.10 | 31.29.9 | 31.28.9 | 31.29.8 | 31.28.8 |
| GTX3:CHAN_BOND_SEQ_2_3 | 31.29.20 | 31.28.20 | 31.29.19 | 31.28.19 | 31.29.18 | 31.28.18 | 31.29.17 | 31.28.17 | 31.29.16 | 31.28.16 |
| GTX3:CHAN_BOND_SEQ_2_4 | 31.29.28 | 31.28.28 | 31.29.27 | 31.28.27 | 31.29.26 | 31.28.26 | 31.29.25 | 31.28.25 | 31.29.24 | 31.28.24 |
| GTX3:CLK_COR_SEQ_1_1 | 31.29.44 | 31.28.44 | 31.29.43 | 31.28.43 | 31.29.42 | 31.28.42 | 31.29.41 | 31.28.41 | 31.29.40 | 31.28.40 |
| GTX3:CLK_COR_SEQ_1_2 | 31.29.52 | 31.28.52 | 31.29.51 | 31.28.51 | 31.29.50 | 31.28.50 | 31.29.49 | 31.28.49 | 31.29.48 | 31.28.48 |
| GTX3:CLK_COR_SEQ_1_3 | 31.29.60 | 31.28.60 | 31.29.59 | 31.28.59 | 31.29.58 | 31.28.58 | 31.29.57 | 31.28.57 | 31.29.56 | 31.28.56 |
| GTX3:CLK_COR_SEQ_1_4 | 32.29.4 | 32.28.4 | 32.29.3 | 32.28.3 | 32.29.2 | 32.28.2 | 32.29.1 | 32.28.1 | 32.29.0 | 32.28.0 |
| GTX3:CLK_COR_SEQ_2_1 | 32.29.12 | 32.28.12 | 32.29.11 | 32.28.11 | 32.29.10 | 32.28.10 | 32.29.9 | 32.28.9 | 32.29.8 | 32.28.8 |
| GTX3:CLK_COR_SEQ_2_2 | 32.29.20 | 32.28.20 | 32.29.19 | 32.28.19 | 32.29.18 | 32.28.18 | 32.29.17 | 32.28.17 | 32.29.16 | 32.28.16 |
| GTX3:CLK_COR_SEQ_2_3 | 32.29.28 | 32.28.28 | 32.29.27 | 32.28.27 | 32.29.26 | 32.28.26 | 32.29.25 | 32.28.25 | 32.29.24 | 32.28.24 |
| GTX3:CLK_COR_SEQ_2_4 | 32.29.36 | 32.28.36 | 32.29.35 | 32.28.35 | 32.29.34 | 32.28.34 | 32.29.33 | 32.28.33 | 32.29.32 | 32.28.32 |
| GTX3:COMMA_10B_ENABLE | 35.29.60 | 35.28.60 | 35.29.59 | 35.28.59 | 35.29.58 | 35.28.58 | 35.29.57 | 35.28.57 | 35.29.56 | 35.28.56 |
| GTX3:MCOMMA_10B_VALUE | 36.29.4 | 36.28.4 | 36.29.3 | 36.28.3 | 36.29.2 | 36.28.2 | 36.29.1 | 36.28.1 | 36.29.0 | 36.28.0 |
| GTX3:PCOMMA_10B_VALUE | 36.29.12 | 36.28.12 | 36.29.11 | 36.28.11 | 36.29.10 | 36.28.10 | 36.29.9 | 36.28.9 | 36.29.8 | 36.28.8 |
| GTX3:POWER_SAVE | 38.29.36 | 38.28.36 | 38.29.35 | 38.28.35 | 38.29.34 | 38.28.34 | 38.29.33 | 38.28.33 | 38.29.32 | 38.28.32 |
| GTX3:RXRECCLK_DLY | 38.29.52 | 38.28.52 | 38.29.51 | 38.28.51 | 38.29.50 | 38.28.50 | 38.29.49 | 38.28.49 | 38.29.48 | 38.28.48 |
| GTX3:TRANS_TIME_TO_P2 | 34.29.28 | 34.28.28 | 34.29.27 | 34.28.27 | 34.29.26 | 34.28.26 | 34.29.25 | 34.28.25 | 34.29.24 | 34.28.24 |
| GTX3:TXOUTCLK_DLY | 38.29.60 | 38.28.60 | 38.29.59 | 38.28.59 | 38.29.58 | 38.28.58 | 38.29.57 | 38.28.57 | 38.29.56 | 38.28.56 |
| non-inverted | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| GTX0:ALIGN_COMMA_WORD | 2.28.39 |
|---|---|
| GTX1:ALIGN_COMMA_WORD | 12.28.39 |
| GTX2:ALIGN_COMMA_WORD | 22.28.39 |
| GTX3:ALIGN_COMMA_WORD | 32.28.39 |
| 1 | 0 |
| 2 | 1 |
| GTX0:A_DFECLKDLYADJ | 5.28.39 | 5.29.38 | 5.28.38 | 5.29.37 | 5.28.37 | 5.29.36 |
|---|---|---|---|---|---|---|
| GTX0:CLK_COR_MAX_LAT | 2.29.7 | 2.28.7 | 2.29.6 | 2.28.6 | 2.29.5 | 2.28.5 |
| GTX0:CLK_COR_MIN_LAT | 1.29.63 | 1.28.63 | 1.29.62 | 1.28.62 | 1.29.61 | 1.28.61 |
| GTX0:RXBUF_OVFL_THRESH | 1.29.34 | 1.28.34 | 1.29.33 | 1.28.33 | 1.29.32 | 1.28.32 |
| GTX0:RXBUF_UDFL_THRESH | 1.29.37 | 1.28.37 | 1.29.36 | 1.28.36 | 1.29.35 | 1.28.35 |
| GTX0:SAS_MAX_COMSAS | 5.29.10 | 5.28.10 | 5.29.9 | 5.28.9 | 5.29.8 | 5.28.8 |
| GTX0:SAS_MIN_COMSAS | 5.29.13 | 5.28.13 | 5.29.12 | 5.28.12 | 5.29.11 | 5.28.11 |
| GTX0:SATA_MAX_BURST | 5.29.2 | 5.28.2 | 5.29.1 | 5.28.1 | 5.29.0 | 5.28.0 |
| GTX0:SATA_MAX_INIT | 4.29.58 | 4.28.58 | 4.29.57 | 4.28.57 | 4.29.56 | 4.28.56 |
| GTX0:SATA_MAX_WAKE | 4.29.50 | 4.28.50 | 4.29.49 | 4.28.49 | 4.29.48 | 4.28.48 |
| GTX0:SATA_MIN_BURST | 5.29.5 | 5.28.5 | 5.29.4 | 5.28.4 | 5.29.3 | 5.28.3 |
| GTX0:SATA_MIN_INIT | 4.29.61 | 4.28.61 | 4.29.60 | 4.28.60 | 4.29.59 | 4.28.59 |
| GTX0:SATA_MIN_WAKE | 4.29.53 | 4.28.53 | 4.29.52 | 4.28.52 | 4.29.51 | 4.28.51 |
| GTX0:TX_BYTECLK_CFG | 8.29.42 | 8.28.42 | 8.29.41 | 8.28.41 | 8.29.40 | 8.28.40 |
| GTX0:TX_USRCLK_CFG | 8.29.45 | 8.28.45 | 8.29.44 | 8.28.44 | 8.29.43 | 8.28.43 |
| GTX1:A_DFECLKDLYADJ | 15.28.39 | 15.29.38 | 15.28.38 | 15.29.37 | 15.28.37 | 15.29.36 |
| GTX1:CLK_COR_MAX_LAT | 12.29.7 | 12.28.7 | 12.29.6 | 12.28.6 | 12.29.5 | 12.28.5 |
| GTX1:CLK_COR_MIN_LAT | 11.29.63 | 11.28.63 | 11.29.62 | 11.28.62 | 11.29.61 | 11.28.61 |
| GTX1:RXBUF_OVFL_THRESH | 11.29.34 | 11.28.34 | 11.29.33 | 11.28.33 | 11.29.32 | 11.28.32 |
| GTX1:RXBUF_UDFL_THRESH | 11.29.37 | 11.28.37 | 11.29.36 | 11.28.36 | 11.29.35 | 11.28.35 |
| GTX1:SAS_MAX_COMSAS | 15.29.10 | 15.28.10 | 15.29.9 | 15.28.9 | 15.29.8 | 15.28.8 |
| GTX1:SAS_MIN_COMSAS | 15.29.13 | 15.28.13 | 15.29.12 | 15.28.12 | 15.29.11 | 15.28.11 |
| GTX1:SATA_MAX_BURST | 15.29.2 | 15.28.2 | 15.29.1 | 15.28.1 | 15.29.0 | 15.28.0 |
| GTX1:SATA_MAX_INIT | 14.29.58 | 14.28.58 | 14.29.57 | 14.28.57 | 14.29.56 | 14.28.56 |
| GTX1:SATA_MAX_WAKE | 14.29.50 | 14.28.50 | 14.29.49 | 14.28.49 | 14.29.48 | 14.28.48 |
| GTX1:SATA_MIN_BURST | 15.29.5 | 15.28.5 | 15.29.4 | 15.28.4 | 15.29.3 | 15.28.3 |
| GTX1:SATA_MIN_INIT | 14.29.61 | 14.28.61 | 14.29.60 | 14.28.60 | 14.29.59 | 14.28.59 |
| GTX1:SATA_MIN_WAKE | 14.29.53 | 14.28.53 | 14.29.52 | 14.28.52 | 14.29.51 | 14.28.51 |
| GTX1:TX_BYTECLK_CFG | 18.29.42 | 18.28.42 | 18.29.41 | 18.28.41 | 18.29.40 | 18.28.40 |
| GTX1:TX_USRCLK_CFG | 18.29.45 | 18.28.45 | 18.29.44 | 18.28.44 | 18.29.43 | 18.28.43 |
| GTX2:A_DFECLKDLYADJ | 25.28.39 | 25.29.38 | 25.28.38 | 25.29.37 | 25.28.37 | 25.29.36 |
| GTX2:CLK_COR_MAX_LAT | 22.29.7 | 22.28.7 | 22.29.6 | 22.28.6 | 22.29.5 | 22.28.5 |
| GTX2:CLK_COR_MIN_LAT | 21.29.63 | 21.28.63 | 21.29.62 | 21.28.62 | 21.29.61 | 21.28.61 |
| GTX2:RXBUF_OVFL_THRESH | 21.29.34 | 21.28.34 | 21.29.33 | 21.28.33 | 21.29.32 | 21.28.32 |
| GTX2:RXBUF_UDFL_THRESH | 21.29.37 | 21.28.37 | 21.29.36 | 21.28.36 | 21.29.35 | 21.28.35 |
| GTX2:SAS_MAX_COMSAS | 25.29.10 | 25.28.10 | 25.29.9 | 25.28.9 | 25.29.8 | 25.28.8 |
| GTX2:SAS_MIN_COMSAS | 25.29.13 | 25.28.13 | 25.29.12 | 25.28.12 | 25.29.11 | 25.28.11 |
| GTX2:SATA_MAX_BURST | 25.29.2 | 25.28.2 | 25.29.1 | 25.28.1 | 25.29.0 | 25.28.0 |
| GTX2:SATA_MAX_INIT | 24.29.58 | 24.28.58 | 24.29.57 | 24.28.57 | 24.29.56 | 24.28.56 |
| GTX2:SATA_MAX_WAKE | 24.29.50 | 24.28.50 | 24.29.49 | 24.28.49 | 24.29.48 | 24.28.48 |
| GTX2:SATA_MIN_BURST | 25.29.5 | 25.28.5 | 25.29.4 | 25.28.4 | 25.29.3 | 25.28.3 |
| GTX2:SATA_MIN_INIT | 24.29.61 | 24.28.61 | 24.29.60 | 24.28.60 | 24.29.59 | 24.28.59 |
| GTX2:SATA_MIN_WAKE | 24.29.53 | 24.28.53 | 24.29.52 | 24.28.52 | 24.29.51 | 24.28.51 |
| GTX2:TX_BYTECLK_CFG | 28.29.42 | 28.28.42 | 28.29.41 | 28.28.41 | 28.29.40 | 28.28.40 |
| GTX2:TX_USRCLK_CFG | 28.29.45 | 28.28.45 | 28.29.44 | 28.28.44 | 28.29.43 | 28.28.43 |
| GTX3:A_DFECLKDLYADJ | 35.28.39 | 35.29.38 | 35.28.38 | 35.29.37 | 35.28.37 | 35.29.36 |
| GTX3:CLK_COR_MAX_LAT | 32.29.7 | 32.28.7 | 32.29.6 | 32.28.6 | 32.29.5 | 32.28.5 |
| GTX3:CLK_COR_MIN_LAT | 31.29.63 | 31.28.63 | 31.29.62 | 31.28.62 | 31.29.61 | 31.28.61 |
| GTX3:RXBUF_OVFL_THRESH | 31.29.34 | 31.28.34 | 31.29.33 | 31.28.33 | 31.29.32 | 31.28.32 |
| GTX3:RXBUF_UDFL_THRESH | 31.29.37 | 31.28.37 | 31.29.36 | 31.28.36 | 31.29.35 | 31.28.35 |
| GTX3:SAS_MAX_COMSAS | 35.29.10 | 35.28.10 | 35.29.9 | 35.28.9 | 35.29.8 | 35.28.8 |
| GTX3:SAS_MIN_COMSAS | 35.29.13 | 35.28.13 | 35.29.12 | 35.28.12 | 35.29.11 | 35.28.11 |
| GTX3:SATA_MAX_BURST | 35.29.2 | 35.28.2 | 35.29.1 | 35.28.1 | 35.29.0 | 35.28.0 |
| GTX3:SATA_MAX_INIT | 34.29.58 | 34.28.58 | 34.29.57 | 34.28.57 | 34.29.56 | 34.28.56 |
| GTX3:SATA_MAX_WAKE | 34.29.50 | 34.28.50 | 34.29.49 | 34.28.49 | 34.29.48 | 34.28.48 |
| GTX3:SATA_MIN_BURST | 35.29.5 | 35.28.5 | 35.29.4 | 35.28.4 | 35.29.3 | 35.28.3 |
| GTX3:SATA_MIN_INIT | 34.29.61 | 34.28.61 | 34.29.60 | 34.28.60 | 34.29.59 | 34.28.59 |
| GTX3:SATA_MIN_WAKE | 34.29.53 | 34.28.53 | 34.29.52 | 34.28.52 | 34.29.51 | 34.28.51 |
| GTX3:TX_BYTECLK_CFG | 38.29.42 | 38.28.42 | 38.29.41 | 38.28.41 | 38.29.40 | 38.28.40 |
| GTX3:TX_USRCLK_CFG | 38.29.45 | 38.28.45 | 38.29.44 | 38.28.44 | 38.29.43 | 38.28.43 |
| non-inverted | [5] | [4] | [3] | [2] | [1] | [0] |
| GTX0:A_DFETAP1 | 5.28.26 | 5.29.25 | 5.28.25 | 5.29.24 | 5.28.24 |
|---|---|---|---|---|---|
| GTX0:A_DFETAP2 | 5.28.34 | 5.29.33 | 5.28.33 | 5.29.32 | 5.28.32 |
| GTX0:A_TXPOSTEMPHASIS | 7.29.47 | 7.28.47 | 7.29.46 | 7.28.46 | 7.29.45 |
| GTX0:CDR_PH_ADJ_TIME | 2.29.55 | 2.28.55 | 2.29.54 | 2.28.54 | 2.29.53 |
| GTX0:CHAN_BOND_SEQ_2_CFG | 2.29.61 | 1.29.22 | 1.28.22 | 1.29.21 | 1.28.21 |
| GTX0:CLK_COR_REPEAT_WAIT | 1.28.55 | 1.29.54 | 1.28.54 | 1.29.53 | 1.28.53 |
| GTX0:DFE_CAL_TIME | 5.29.55 | 5.28.55 | 5.29.54 | 5.28.54 | 5.29.53 |
| GTX0:RX_DLYALIGN_EDGESET | 9.28.29 | 9.29.28 | 9.28.28 | 9.29.27 | 9.28.27 |
| GTX0:TERMINATION_CTRL | 5.28.50 | 5.29.49 | 5.28.49 | 5.29.48 | 5.28.48 |
| GTX0:TX_DEEMPH_0 | 7.28.50 | 7.29.49 | 7.28.49 | 7.29.48 | 7.28.48 |
| GTX0:TX_DEEMPH_1 | 7.29.52 | 7.28.52 | 7.29.51 | 7.28.51 | 7.29.50 |
| GTX1:A_DFETAP1 | 15.28.26 | 15.29.25 | 15.28.25 | 15.29.24 | 15.28.24 |
| GTX1:A_DFETAP2 | 15.28.34 | 15.29.33 | 15.28.33 | 15.29.32 | 15.28.32 |
| GTX1:A_TXPOSTEMPHASIS | 17.29.47 | 17.28.47 | 17.29.46 | 17.28.46 | 17.29.45 |
| GTX1:CDR_PH_ADJ_TIME | 12.29.55 | 12.28.55 | 12.29.54 | 12.28.54 | 12.29.53 |
| GTX1:CHAN_BOND_SEQ_2_CFG | 12.29.61 | 11.29.22 | 11.28.22 | 11.29.21 | 11.28.21 |
| GTX1:CLK_COR_REPEAT_WAIT | 11.28.55 | 11.29.54 | 11.28.54 | 11.29.53 | 11.28.53 |
| GTX1:DFE_CAL_TIME | 15.29.55 | 15.28.55 | 15.29.54 | 15.28.54 | 15.29.53 |
| GTX1:RX_DLYALIGN_EDGESET | 19.28.29 | 19.29.28 | 19.28.28 | 19.29.27 | 19.28.27 |
| GTX1:TERMINATION_CTRL | 15.28.50 | 15.29.49 | 15.28.49 | 15.29.48 | 15.28.48 |
| GTX1:TX_DEEMPH_0 | 17.28.50 | 17.29.49 | 17.28.49 | 17.29.48 | 17.28.48 |
| GTX1:TX_DEEMPH_1 | 17.29.52 | 17.28.52 | 17.29.51 | 17.28.51 | 17.29.50 |
| GTX2:A_DFETAP1 | 25.28.26 | 25.29.25 | 25.28.25 | 25.29.24 | 25.28.24 |
| GTX2:A_DFETAP2 | 25.28.34 | 25.29.33 | 25.28.33 | 25.29.32 | 25.28.32 |
| GTX2:A_TXPOSTEMPHASIS | 27.29.47 | 27.28.47 | 27.29.46 | 27.28.46 | 27.29.45 |
| GTX2:CDR_PH_ADJ_TIME | 22.29.55 | 22.28.55 | 22.29.54 | 22.28.54 | 22.29.53 |
| GTX2:CHAN_BOND_SEQ_2_CFG | 22.29.61 | 21.29.22 | 21.28.22 | 21.29.21 | 21.28.21 |
| GTX2:CLK_COR_REPEAT_WAIT | 21.28.55 | 21.29.54 | 21.28.54 | 21.29.53 | 21.28.53 |
| GTX2:DFE_CAL_TIME | 25.29.55 | 25.28.55 | 25.29.54 | 25.28.54 | 25.29.53 |
| GTX2:RX_DLYALIGN_EDGESET | 29.28.29 | 29.29.28 | 29.28.28 | 29.29.27 | 29.28.27 |
| GTX2:TERMINATION_CTRL | 25.28.50 | 25.29.49 | 25.28.49 | 25.29.48 | 25.28.48 |
| GTX2:TX_DEEMPH_0 | 27.28.50 | 27.29.49 | 27.28.49 | 27.29.48 | 27.28.48 |
| GTX2:TX_DEEMPH_1 | 27.29.52 | 27.28.52 | 27.29.51 | 27.28.51 | 27.29.50 |
| GTX3:A_DFETAP1 | 35.28.26 | 35.29.25 | 35.28.25 | 35.29.24 | 35.28.24 |
| GTX3:A_DFETAP2 | 35.28.34 | 35.29.33 | 35.28.33 | 35.29.32 | 35.28.32 |
| GTX3:A_TXPOSTEMPHASIS | 37.29.47 | 37.28.47 | 37.29.46 | 37.28.46 | 37.29.45 |
| GTX3:CDR_PH_ADJ_TIME | 32.29.55 | 32.28.55 | 32.29.54 | 32.28.54 | 32.29.53 |
| GTX3:CHAN_BOND_SEQ_2_CFG | 32.29.61 | 31.29.22 | 31.28.22 | 31.29.21 | 31.28.21 |
| GTX3:CLK_COR_REPEAT_WAIT | 31.28.55 | 31.29.54 | 31.28.54 | 31.29.53 | 31.28.53 |
| GTX3:DFE_CAL_TIME | 35.29.55 | 35.28.55 | 35.29.54 | 35.28.54 | 35.29.53 |
| GTX3:RX_DLYALIGN_EDGESET | 39.28.29 | 39.29.28 | 39.28.28 | 39.29.27 | 39.28.27 |
| GTX3:TERMINATION_CTRL | 35.28.50 | 35.29.49 | 35.28.49 | 35.29.48 | 35.28.48 |
| GTX3:TX_DEEMPH_0 | 37.28.50 | 37.29.49 | 37.28.49 | 37.29.48 | 37.28.48 |
| GTX3:TX_DEEMPH_1 | 37.29.52 | 37.28.52 | 37.29.51 | 37.28.51 | 37.29.50 |
| non-inverted | [4] | [3] | [2] | [1] | [0] |
| GTX0:A_DFETAP3 | 5.28.28 | 5.29.27 | 5.28.27 | 5.29.26 |
|---|---|---|---|---|
| GTX0:A_DFETAP4 | 5.28.36 | 5.29.35 | 5.28.35 | 5.29.34 |
| GTX0:A_TXDIFFCTRL | 7.29.41 | 7.28.41 | 7.29.40 | 7.28.40 |
| GTX0:A_TXPREEMPHASIS | 7.28.45 | 7.29.44 | 7.28.44 | 7.29.43 |
| GTX0:CHAN_BOND_1_MAX_SKEW | 0.29.46 | 0.28.46 | 0.29.45 | 0.28.45 |
| GTX0:CHAN_BOND_2_MAX_SKEW | 1.29.14 | 1.28.14 | 1.29.13 | 1.28.13 |
| GTX0:CHAN_BOND_SEQ_1_ENABLE | 0.29.38 | 0.28.38 | 0.29.37 | 0.28.37 |
| GTX0:CHAN_BOND_SEQ_2_ENABLE | 1.29.6 | 1.28.6 | 1.29.5 | 1.28.5 |
| GTX0:CLK_COR_SEQ_1_ENABLE | 1.29.46 | 1.28.46 | 1.29.45 | 1.28.45 |
| GTX0:CLK_COR_SEQ_2_ENABLE | 2.29.14 | 2.28.14 | 2.29.13 | 2.28.13 |
| GTX0:COM_BURST_VAL | 4.29.39 | 4.28.39 | 4.29.38 | 4.28.38 |
| GTX0:RX_DLYALIGN_CTRINC | 9.29.41 | 9.28.41 | 9.29.40 | 9.28.40 |
| GTX0:RX_DLYALIGN_LPFINC | 9.29.43 | 9.28.43 | 9.29.42 | 9.28.42 |
| GTX0:RX_IDLE_HI_CNT | 1.29.31 | 1.28.31 | 1.29.30 | 1.28.30 |
| GTX0:RX_IDLE_LO_CNT | 0.29.63 | 0.28.63 | 0.29.62 | 0.28.62 |
| GTX0:RX_SLIDE_AUTO_WAIT | 2.29.31 | 2.28.31 | 2.29.30 | 2.28.30 |
| GTX0:TX_DLYALIGN_CTRINC | 9.29.33 | 9.28.33 | 9.29.32 | 9.28.32 |
| GTX0:TX_DLYALIGN_LPFINC | 9.29.35 | 9.28.35 | 9.29.34 | 9.28.34 |
| GTX1:A_DFETAP3 | 15.28.28 | 15.29.27 | 15.28.27 | 15.29.26 |
| GTX1:A_DFETAP4 | 15.28.36 | 15.29.35 | 15.28.35 | 15.29.34 |
| GTX1:A_TXDIFFCTRL | 17.29.41 | 17.28.41 | 17.29.40 | 17.28.40 |
| GTX1:A_TXPREEMPHASIS | 17.28.45 | 17.29.44 | 17.28.44 | 17.29.43 |
| GTX1:CHAN_BOND_1_MAX_SKEW | 10.29.46 | 10.28.46 | 10.29.45 | 10.28.45 |
| GTX1:CHAN_BOND_2_MAX_SKEW | 11.29.14 | 11.28.14 | 11.29.13 | 11.28.13 |
| GTX1:CHAN_BOND_SEQ_1_ENABLE | 10.29.38 | 10.28.38 | 10.29.37 | 10.28.37 |
| GTX1:CHAN_BOND_SEQ_2_ENABLE | 11.29.6 | 11.28.6 | 11.29.5 | 11.28.5 |
| GTX1:CLK_COR_SEQ_1_ENABLE | 11.29.46 | 11.28.46 | 11.29.45 | 11.28.45 |
| GTX1:CLK_COR_SEQ_2_ENABLE | 12.29.14 | 12.28.14 | 12.29.13 | 12.28.13 |
| GTX1:COM_BURST_VAL | 14.29.39 | 14.28.39 | 14.29.38 | 14.28.38 |
| GTX1:RX_DLYALIGN_CTRINC | 19.29.41 | 19.28.41 | 19.29.40 | 19.28.40 |
| GTX1:RX_DLYALIGN_LPFINC | 19.29.43 | 19.28.43 | 19.29.42 | 19.28.42 |
| GTX1:RX_IDLE_HI_CNT | 11.29.31 | 11.28.31 | 11.29.30 | 11.28.30 |
| GTX1:RX_IDLE_LO_CNT | 10.29.63 | 10.28.63 | 10.29.62 | 10.28.62 |
| GTX1:RX_SLIDE_AUTO_WAIT | 12.29.31 | 12.28.31 | 12.29.30 | 12.28.30 |
| GTX1:TX_DLYALIGN_CTRINC | 19.29.33 | 19.28.33 | 19.29.32 | 19.28.32 |
| GTX1:TX_DLYALIGN_LPFINC | 19.29.35 | 19.28.35 | 19.29.34 | 19.28.34 |
| GTX2:A_DFETAP3 | 25.28.28 | 25.29.27 | 25.28.27 | 25.29.26 |
| GTX2:A_DFETAP4 | 25.28.36 | 25.29.35 | 25.28.35 | 25.29.34 |
| GTX2:A_TXDIFFCTRL | 27.29.41 | 27.28.41 | 27.29.40 | 27.28.40 |
| GTX2:A_TXPREEMPHASIS | 27.28.45 | 27.29.44 | 27.28.44 | 27.29.43 |
| GTX2:CHAN_BOND_1_MAX_SKEW | 20.29.46 | 20.28.46 | 20.29.45 | 20.28.45 |
| GTX2:CHAN_BOND_2_MAX_SKEW | 21.29.14 | 21.28.14 | 21.29.13 | 21.28.13 |
| GTX2:CHAN_BOND_SEQ_1_ENABLE | 20.29.38 | 20.28.38 | 20.29.37 | 20.28.37 |
| GTX2:CHAN_BOND_SEQ_2_ENABLE | 21.29.6 | 21.28.6 | 21.29.5 | 21.28.5 |
| GTX2:CLK_COR_SEQ_1_ENABLE | 21.29.46 | 21.28.46 | 21.29.45 | 21.28.45 |
| GTX2:CLK_COR_SEQ_2_ENABLE | 22.29.14 | 22.28.14 | 22.29.13 | 22.28.13 |
| GTX2:COM_BURST_VAL | 24.29.39 | 24.28.39 | 24.29.38 | 24.28.38 |
| GTX2:RX_DLYALIGN_CTRINC | 29.29.41 | 29.28.41 | 29.29.40 | 29.28.40 |
| GTX2:RX_DLYALIGN_LPFINC | 29.29.43 | 29.28.43 | 29.29.42 | 29.28.42 |
| GTX2:RX_IDLE_HI_CNT | 21.29.31 | 21.28.31 | 21.29.30 | 21.28.30 |
| GTX2:RX_IDLE_LO_CNT | 20.29.63 | 20.28.63 | 20.29.62 | 20.28.62 |
| GTX2:RX_SLIDE_AUTO_WAIT | 22.29.31 | 22.28.31 | 22.29.30 | 22.28.30 |
| GTX2:TX_DLYALIGN_CTRINC | 29.29.33 | 29.28.33 | 29.29.32 | 29.28.32 |
| GTX2:TX_DLYALIGN_LPFINC | 29.29.35 | 29.28.35 | 29.29.34 | 29.28.34 |
| GTX3:A_DFETAP3 | 35.28.28 | 35.29.27 | 35.28.27 | 35.29.26 |
| GTX3:A_DFETAP4 | 35.28.36 | 35.29.35 | 35.28.35 | 35.29.34 |
| GTX3:A_TXDIFFCTRL | 37.29.41 | 37.28.41 | 37.29.40 | 37.28.40 |
| GTX3:A_TXPREEMPHASIS | 37.28.45 | 37.29.44 | 37.28.44 | 37.29.43 |
| GTX3:CHAN_BOND_1_MAX_SKEW | 30.29.46 | 30.28.46 | 30.29.45 | 30.28.45 |
| GTX3:CHAN_BOND_2_MAX_SKEW | 31.29.14 | 31.28.14 | 31.29.13 | 31.28.13 |
| GTX3:CHAN_BOND_SEQ_1_ENABLE | 30.29.38 | 30.28.38 | 30.29.37 | 30.28.37 |
| GTX3:CHAN_BOND_SEQ_2_ENABLE | 31.29.6 | 31.28.6 | 31.29.5 | 31.28.5 |
| GTX3:CLK_COR_SEQ_1_ENABLE | 31.29.46 | 31.28.46 | 31.29.45 | 31.28.45 |
| GTX3:CLK_COR_SEQ_2_ENABLE | 32.29.14 | 32.28.14 | 32.29.13 | 32.28.13 |
| GTX3:COM_BURST_VAL | 34.29.39 | 34.28.39 | 34.29.38 | 34.28.38 |
| GTX3:RX_DLYALIGN_CTRINC | 39.29.41 | 39.28.41 | 39.29.40 | 39.28.40 |
| GTX3:RX_DLYALIGN_LPFINC | 39.29.43 | 39.28.43 | 39.29.42 | 39.28.42 |
| GTX3:RX_IDLE_HI_CNT | 31.29.31 | 31.28.31 | 31.29.30 | 31.28.30 |
| GTX3:RX_IDLE_LO_CNT | 30.29.63 | 30.28.63 | 30.29.62 | 30.28.62 |
| GTX3:RX_SLIDE_AUTO_WAIT | 32.29.31 | 32.28.31 | 32.29.30 | 32.28.30 |
| GTX3:TX_DLYALIGN_CTRINC | 39.29.33 | 39.28.33 | 39.29.32 | 39.28.32 |
| GTX3:TX_DLYALIGN_LPFINC | 39.29.35 | 39.28.35 | 39.29.34 | 39.28.34 |
| non-inverted | [3] | [2] | [1] | [0] |
| GTX0:A_LOOPBACK | 5.29.17 | 5.28.17 | 5.29.16 |
|---|---|---|---|
| GTX0:A_RXENPRBSTST | 5.29.19 | 5.28.19 | 5.29.18 |
| GTX0:A_TXBUFDIFFCTRL | 7.28.43 | 7.29.42 | 7.28.42 |
| GTX0:A_TXENPRBSTST | 5.29.22 | 5.28.22 | 5.29.21 |
| GTX0:A_TXMARGIN | 7.29.55 | 7.28.55 | 7.29.54 |
| GTX0:GEARBOX_ENDEC | 3.28.1 | 3.29.0 | 3.28.0 |
| GTX0:OOBDETECT_THRESHOLD | 2.28.57 | 2.29.56 | 2.28.56 |
| GTX0:RXPLL_LKDET_CFG | 3.29.30 | 3.28.30 | 3.29.29 |
| GTX0:RX_DLYALIGN_MONSEL | 9.28.25 | 9.29.24 | 9.28.24 |
| GTX0:SATA_BURST_VAL | 5.28.7 | 5.29.6 | 5.28.6 |
| GTX0:SATA_IDLE_VAL | 4.28.63 | 4.29.62 | 4.28.62 |
| GTX0:TXPLL_LKDET_CFG | 3.29.62 | 3.28.62 | 3.29.61 |
| GTX0:TX_DLYALIGN_MONSEL | 9.29.26 | 9.28.26 | 9.29.25 |
| GTX0:TX_IDLE_ASSERT_DELAY | 5.29.62 | 5.28.62 | 5.29.61 |
| GTX0:TX_IDLE_DEASSERT_DELAY | 6.29.6 | 6.28.6 | 6.29.5 |
| GTX1:A_LOOPBACK | 15.29.17 | 15.28.17 | 15.29.16 |
| GTX1:A_RXENPRBSTST | 15.29.19 | 15.28.19 | 15.29.18 |
| GTX1:A_TXBUFDIFFCTRL | 17.28.43 | 17.29.42 | 17.28.42 |
| GTX1:A_TXENPRBSTST | 15.29.22 | 15.28.22 | 15.29.21 |
| GTX1:A_TXMARGIN | 17.29.55 | 17.28.55 | 17.29.54 |
| GTX1:GEARBOX_ENDEC | 13.28.1 | 13.29.0 | 13.28.0 |
| GTX1:OOBDETECT_THRESHOLD | 12.28.57 | 12.29.56 | 12.28.56 |
| GTX1:RXPLL_LKDET_CFG | 13.29.30 | 13.28.30 | 13.29.29 |
| GTX1:RX_DLYALIGN_MONSEL | 19.28.25 | 19.29.24 | 19.28.24 |
| GTX1:SATA_BURST_VAL | 15.28.7 | 15.29.6 | 15.28.6 |
| GTX1:SATA_IDLE_VAL | 14.28.63 | 14.29.62 | 14.28.62 |
| GTX1:TXPLL_LKDET_CFG | 13.29.62 | 13.28.62 | 13.29.61 |
| GTX1:TX_DLYALIGN_MONSEL | 19.29.26 | 19.28.26 | 19.29.25 |
| GTX1:TX_IDLE_ASSERT_DELAY | 15.29.62 | 15.28.62 | 15.29.61 |
| GTX1:TX_IDLE_DEASSERT_DELAY | 16.29.6 | 16.28.6 | 16.29.5 |
| GTX2:A_LOOPBACK | 25.29.17 | 25.28.17 | 25.29.16 |
| GTX2:A_RXENPRBSTST | 25.29.19 | 25.28.19 | 25.29.18 |
| GTX2:A_TXBUFDIFFCTRL | 27.28.43 | 27.29.42 | 27.28.42 |
| GTX2:A_TXENPRBSTST | 25.29.22 | 25.28.22 | 25.29.21 |
| GTX2:A_TXMARGIN | 27.29.55 | 27.28.55 | 27.29.54 |
| GTX2:GEARBOX_ENDEC | 23.28.1 | 23.29.0 | 23.28.0 |
| GTX2:OOBDETECT_THRESHOLD | 22.28.57 | 22.29.56 | 22.28.56 |
| GTX2:RXPLL_LKDET_CFG | 23.29.30 | 23.28.30 | 23.29.29 |
| GTX2:RX_DLYALIGN_MONSEL | 29.28.25 | 29.29.24 | 29.28.24 |
| GTX2:SATA_BURST_VAL | 25.28.7 | 25.29.6 | 25.28.6 |
| GTX2:SATA_IDLE_VAL | 24.28.63 | 24.29.62 | 24.28.62 |
| GTX2:TXPLL_LKDET_CFG | 23.29.62 | 23.28.62 | 23.29.61 |
| GTX2:TX_DLYALIGN_MONSEL | 29.29.26 | 29.28.26 | 29.29.25 |
| GTX2:TX_IDLE_ASSERT_DELAY | 25.29.62 | 25.28.62 | 25.29.61 |
| GTX2:TX_IDLE_DEASSERT_DELAY | 26.29.6 | 26.28.6 | 26.29.5 |
| GTX3:A_LOOPBACK | 35.29.17 | 35.28.17 | 35.29.16 |
| GTX3:A_RXENPRBSTST | 35.29.19 | 35.28.19 | 35.29.18 |
| GTX3:A_TXBUFDIFFCTRL | 37.28.43 | 37.29.42 | 37.28.42 |
| GTX3:A_TXENPRBSTST | 35.29.22 | 35.28.22 | 35.29.21 |
| GTX3:A_TXMARGIN | 37.29.55 | 37.28.55 | 37.29.54 |
| GTX3:GEARBOX_ENDEC | 33.28.1 | 33.29.0 | 33.28.0 |
| GTX3:OOBDETECT_THRESHOLD | 32.28.57 | 32.29.56 | 32.28.56 |
| GTX3:RXPLL_LKDET_CFG | 33.29.30 | 33.28.30 | 33.29.29 |
| GTX3:RX_DLYALIGN_MONSEL | 39.28.25 | 39.29.24 | 39.28.24 |
| GTX3:SATA_BURST_VAL | 35.28.7 | 35.29.6 | 35.28.6 |
| GTX3:SATA_IDLE_VAL | 34.28.63 | 34.29.62 | 34.28.62 |
| GTX3:TXPLL_LKDET_CFG | 33.29.62 | 33.28.62 | 33.29.61 |
| GTX3:TX_DLYALIGN_MONSEL | 39.29.26 | 39.28.26 | 39.29.25 |
| GTX3:TX_IDLE_ASSERT_DELAY | 35.29.62 | 35.28.62 | 35.29.61 |
| GTX3:TX_IDLE_DEASSERT_DELAY | 36.29.6 | 36.28.6 | 36.29.5 |
| non-inverted | [2] | [1] | [0] |
| GTX0:A_RXPOWERDOWN | 3.28.29 | 3.29.28 |
|---|---|---|
| GTX0:A_TXPOWERDOWN | 3.28.61 | 3.29.60 |
| GTX0:BGTEST_CFG | 4.29.55 | 4.28.55 |
| GTX0:CM_TRIM | 4.29.44 | 4.28.44 |
| GTX0:RX_EYE_SCANMODE | 5.28.53 | 5.29.52 |
| GTX0:TXPLL_SATA | 4.29.54 | 4.28.54 |
| GTX0:TX_TDCC_CFG | 7.29.15 | 7.28.15 |
| GTX1:A_RXPOWERDOWN | 13.28.29 | 13.29.28 |
| GTX1:A_TXPOWERDOWN | 13.28.61 | 13.29.60 |
| GTX1:BGTEST_CFG | 14.29.55 | 14.28.55 |
| GTX1:CM_TRIM | 14.29.44 | 14.28.44 |
| GTX1:RX_EYE_SCANMODE | 15.28.53 | 15.29.52 |
| GTX1:TXPLL_SATA | 14.29.54 | 14.28.54 |
| GTX1:TX_TDCC_CFG | 17.29.15 | 17.28.15 |
| GTX2:A_RXPOWERDOWN | 23.28.29 | 23.29.28 |
| GTX2:A_TXPOWERDOWN | 23.28.61 | 23.29.60 |
| GTX2:BGTEST_CFG | 24.29.55 | 24.28.55 |
| GTX2:CM_TRIM | 24.29.44 | 24.28.44 |
| GTX2:RX_EYE_SCANMODE | 25.28.53 | 25.29.52 |
| GTX2:TXPLL_SATA | 24.29.54 | 24.28.54 |
| GTX2:TX_TDCC_CFG | 27.29.15 | 27.28.15 |
| GTX3:A_RXPOWERDOWN | 33.28.29 | 33.29.28 |
| GTX3:A_TXPOWERDOWN | 33.28.61 | 33.29.60 |
| GTX3:BGTEST_CFG | 34.29.55 | 34.28.55 |
| GTX3:CM_TRIM | 34.29.44 | 34.28.44 |
| GTX3:RX_EYE_SCANMODE | 35.28.53 | 35.29.52 |
| GTX3:TXPLL_SATA | 34.29.54 | 34.28.54 |
| GTX3:TX_TDCC_CFG | 37.29.15 | 37.28.15 |
| non-inverted | [1] | [0] |
| GTX0:BIAS_CFG | 2.28.61 | 0.29.31 | 0.28.31 | 0.29.30 | 0.28.30 | 0.29.29 | 0.28.29 | 0.29.28 | 0.28.28 | 0.29.27 | 0.28.27 | 0.29.26 | 0.28.26 | 0.29.25 | 0.28.25 | 0.29.24 | 0.28.24 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GTX1:BIAS_CFG | 12.28.61 | 10.29.31 | 10.28.31 | 10.29.30 | 10.28.30 | 10.29.29 | 10.28.29 | 10.29.28 | 10.28.28 | 10.29.27 | 10.28.27 | 10.29.26 | 10.28.26 | 10.29.25 | 10.28.25 | 10.29.24 | 10.28.24 |
| GTX2:BIAS_CFG | 22.28.61 | 20.29.31 | 20.28.31 | 20.29.30 | 20.28.30 | 20.29.29 | 20.28.29 | 20.29.28 | 20.28.28 | 20.29.27 | 20.28.27 | 20.29.26 | 20.28.26 | 20.29.25 | 20.28.25 | 20.29.24 | 20.28.24 |
| GTX3:BIAS_CFG | 32.28.61 | 30.29.31 | 30.28.31 | 30.29.30 | 30.28.30 | 30.29.29 | 30.28.29 | 30.29.28 | 30.28.28 | 30.29.27 | 30.28.27 | 30.29.26 | 30.28.26 | 30.29.25 | 30.28.25 | 30.29.24 | 30.28.24 |
| non-inverted | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| GTX0:CHAN_BOND_SEQ_LEN | 0.29.61 | 0.28.61 |
|---|---|---|
| GTX0:CLK_COR_ADJ_LEN | 2.29.21 | 2.28.21 |
| GTX0:CLK_COR_DET_LEN | 2.29.29 | 2.28.29 |
| GTX1:CHAN_BOND_SEQ_LEN | 10.29.61 | 10.28.61 |
| GTX1:CLK_COR_ADJ_LEN | 12.29.21 | 12.28.21 |
| GTX1:CLK_COR_DET_LEN | 12.29.29 | 12.28.29 |
| GTX2:CHAN_BOND_SEQ_LEN | 20.29.61 | 20.28.61 |
| GTX2:CLK_COR_ADJ_LEN | 22.29.21 | 22.28.21 |
| GTX2:CLK_COR_DET_LEN | 22.29.29 | 22.28.29 |
| GTX3:CHAN_BOND_SEQ_LEN | 30.29.61 | 30.28.61 |
| GTX3:CLK_COR_ADJ_LEN | 32.29.21 | 32.28.21 |
| GTX3:CLK_COR_DET_LEN | 32.29.29 | 32.28.29 |
| 1 | 0 | 0 |
| 2 | 0 | 1 |
| 3 | 1 | 0 |
| 4 | 1 | 1 |
| GTX0:DFE_CFG | 5.29.43 | 5.28.43 | 5.29.42 | 5.28.42 | 5.29.41 | 5.28.41 | 5.29.40 | 5.28.40 |
|---|---|---|---|---|---|---|---|---|
| GTX0:RXPLL_CP_CFG | 3.29.23 | 3.28.23 | 3.29.22 | 3.28.22 | 3.29.21 | 3.28.21 | 3.29.20 | 3.28.20 |
| GTX0:RX_DLYALIGN_OVRDSETTING | 9.29.47 | 9.28.47 | 9.29.46 | 9.28.46 | 9.29.45 | 9.28.45 | 9.29.44 | 9.28.44 |
| GTX0:RX_EYE_OFFSET | 5.29.47 | 5.28.47 | 5.29.46 | 5.28.46 | 5.29.45 | 5.28.45 | 5.29.44 | 5.28.44 |
| GTX0:TRANS_TIME_NON_P2 | 4.29.43 | 4.28.43 | 4.29.42 | 4.28.42 | 4.29.41 | 4.28.41 | 4.29.40 | 4.28.40 |
| GTX0:TRANS_TIME_RATE | 7.29.59 | 7.28.59 | 7.29.58 | 7.28.58 | 7.29.57 | 7.28.57 | 7.29.56 | 7.28.56 |
| GTX0:TXPLL_CP_CFG | 3.29.55 | 3.28.55 | 3.29.54 | 3.28.54 | 3.29.53 | 3.28.53 | 3.29.52 | 3.28.52 |
| GTX0:TX_DLYALIGN_OVRDSETTING | 9.29.39 | 9.28.39 | 9.29.38 | 9.28.38 | 9.29.37 | 9.28.37 | 9.29.36 | 9.28.36 |
| GTX1:DFE_CFG | 15.29.43 | 15.28.43 | 15.29.42 | 15.28.42 | 15.29.41 | 15.28.41 | 15.29.40 | 15.28.40 |
| GTX1:RXPLL_CP_CFG | 13.29.23 | 13.28.23 | 13.29.22 | 13.28.22 | 13.29.21 | 13.28.21 | 13.29.20 | 13.28.20 |
| GTX1:RX_DLYALIGN_OVRDSETTING | 19.29.47 | 19.28.47 | 19.29.46 | 19.28.46 | 19.29.45 | 19.28.45 | 19.29.44 | 19.28.44 |
| GTX1:RX_EYE_OFFSET | 15.29.47 | 15.28.47 | 15.29.46 | 15.28.46 | 15.29.45 | 15.28.45 | 15.29.44 | 15.28.44 |
| GTX1:TRANS_TIME_NON_P2 | 14.29.43 | 14.28.43 | 14.29.42 | 14.28.42 | 14.29.41 | 14.28.41 | 14.29.40 | 14.28.40 |
| GTX1:TRANS_TIME_RATE | 17.29.59 | 17.28.59 | 17.29.58 | 17.28.58 | 17.29.57 | 17.28.57 | 17.29.56 | 17.28.56 |
| GTX1:TXPLL_CP_CFG | 13.29.55 | 13.28.55 | 13.29.54 | 13.28.54 | 13.29.53 | 13.28.53 | 13.29.52 | 13.28.52 |
| GTX1:TX_DLYALIGN_OVRDSETTING | 19.29.39 | 19.28.39 | 19.29.38 | 19.28.38 | 19.29.37 | 19.28.37 | 19.29.36 | 19.28.36 |
| GTX2:DFE_CFG | 25.29.43 | 25.28.43 | 25.29.42 | 25.28.42 | 25.29.41 | 25.28.41 | 25.29.40 | 25.28.40 |
| GTX2:RXPLL_CP_CFG | 23.29.23 | 23.28.23 | 23.29.22 | 23.28.22 | 23.29.21 | 23.28.21 | 23.29.20 | 23.28.20 |
| GTX2:RX_DLYALIGN_OVRDSETTING | 29.29.47 | 29.28.47 | 29.29.46 | 29.28.46 | 29.29.45 | 29.28.45 | 29.29.44 | 29.28.44 |
| GTX2:RX_EYE_OFFSET | 25.29.47 | 25.28.47 | 25.29.46 | 25.28.46 | 25.29.45 | 25.28.45 | 25.29.44 | 25.28.44 |
| GTX2:TRANS_TIME_NON_P2 | 24.29.43 | 24.28.43 | 24.29.42 | 24.28.42 | 24.29.41 | 24.28.41 | 24.29.40 | 24.28.40 |
| GTX2:TRANS_TIME_RATE | 27.29.59 | 27.28.59 | 27.29.58 | 27.28.58 | 27.29.57 | 27.28.57 | 27.29.56 | 27.28.56 |
| GTX2:TXPLL_CP_CFG | 23.29.55 | 23.28.55 | 23.29.54 | 23.28.54 | 23.29.53 | 23.28.53 | 23.29.52 | 23.28.52 |
| GTX2:TX_DLYALIGN_OVRDSETTING | 29.29.39 | 29.28.39 | 29.29.38 | 29.28.38 | 29.29.37 | 29.28.37 | 29.29.36 | 29.28.36 |
| GTX3:DFE_CFG | 35.29.43 | 35.28.43 | 35.29.42 | 35.28.42 | 35.29.41 | 35.28.41 | 35.29.40 | 35.28.40 |
| GTX3:RXPLL_CP_CFG | 33.29.23 | 33.28.23 | 33.29.22 | 33.28.22 | 33.29.21 | 33.28.21 | 33.29.20 | 33.28.20 |
| GTX3:RX_DLYALIGN_OVRDSETTING | 39.29.47 | 39.28.47 | 39.29.46 | 39.28.46 | 39.29.45 | 39.28.45 | 39.29.44 | 39.28.44 |
| GTX3:RX_EYE_OFFSET | 35.29.47 | 35.28.47 | 35.29.46 | 35.28.46 | 35.29.45 | 35.28.45 | 35.29.44 | 35.28.44 |
| GTX3:TRANS_TIME_NON_P2 | 34.29.43 | 34.28.43 | 34.29.42 | 34.28.42 | 34.29.41 | 34.28.41 | 34.29.40 | 34.28.40 |
| GTX3:TRANS_TIME_RATE | 37.29.59 | 37.28.59 | 37.29.58 | 37.28.58 | 37.29.57 | 37.28.57 | 37.29.56 | 37.28.56 |
| GTX3:TXPLL_CP_CFG | 33.29.55 | 33.28.55 | 33.29.54 | 33.28.54 | 33.29.53 | 33.28.53 | 33.29.52 | 33.28.52 |
| GTX3:TX_DLYALIGN_OVRDSETTING | 39.29.39 | 39.28.39 | 39.29.38 | 39.28.38 | 39.29.37 | 39.28.37 | 39.29.36 | 39.28.36 |
| non-inverted | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| GTX0:DRP00 | 0.29.7 | 0.28.7 | 0.29.6 | 0.28.6 | 0.29.5 | 0.28.5 | 0.29.4 | 0.28.4 | 0.29.3 | 0.28.3 | 0.29.2 | 0.28.2 | 0.29.1 | 0.28.1 | 0.29.0 | 0.28.0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GTX0:DRP01 | 0.29.15 | 0.28.15 | 0.29.14 | 0.28.14 | 0.29.13 | 0.28.13 | 0.29.12 | 0.28.12 | 0.29.11 | 0.28.11 | 0.29.10 | 0.28.10 | 0.29.9 | 0.28.9 | 0.29.8 | 0.28.8 |
| GTX0:DRP02 | 0.29.23 | 0.28.23 | 0.29.22 | 0.28.22 | 0.29.21 | 0.28.21 | 0.29.20 | 0.28.20 | 0.29.19 | 0.28.19 | 0.29.18 | 0.28.18 | 0.29.17 | 0.28.17 | 0.29.16 | 0.28.16 |
| GTX0:DRP03 | 0.29.31 | 0.28.31 | 0.29.30 | 0.28.30 | 0.29.29 | 0.28.29 | 0.29.28 | 0.28.28 | 0.29.27 | 0.28.27 | 0.29.26 | 0.28.26 | 0.29.25 | 0.28.25 | 0.29.24 | 0.28.24 |
| GTX0:DRP04 | 0.29.39 | 0.28.39 | 0.29.38 | 0.28.38 | 0.29.37 | 0.28.37 | 0.29.36 | 0.28.36 | 0.29.35 | 0.28.35 | 0.29.34 | 0.28.34 | 0.29.33 | 0.28.33 | 0.29.32 | 0.28.32 |
| GTX0:DRP05 | 0.29.47 | 0.28.47 | 0.29.46 | 0.28.46 | 0.29.45 | 0.28.45 | 0.29.44 | 0.28.44 | 0.29.43 | 0.28.43 | 0.29.42 | 0.28.42 | 0.29.41 | 0.28.41 | 0.29.40 | 0.28.40 |
| GTX0:DRP06 | 0.29.55 | 0.28.55 | 0.29.54 | 0.28.54 | 0.29.53 | 0.28.53 | 0.29.52 | 0.28.52 | 0.29.51 | 0.28.51 | 0.29.50 | 0.28.50 | 0.29.49 | 0.28.49 | 0.29.48 | 0.28.48 |
| GTX0:DRP07 | 0.29.63 | 0.28.63 | 0.29.62 | 0.28.62 | 0.29.61 | 0.28.61 | 0.29.60 | 0.28.60 | 0.29.59 | 0.28.59 | 0.29.58 | 0.28.58 | 0.29.57 | 0.28.57 | 0.29.56 | 0.28.56 |
| GTX0:DRP08 | 1.29.7 | 1.28.7 | 1.29.6 | 1.28.6 | 1.29.5 | 1.28.5 | 1.29.4 | 1.28.4 | 1.29.3 | 1.28.3 | 1.29.2 | 1.28.2 | 1.29.1 | 1.28.1 | 1.29.0 | 1.28.0 |
| GTX0:DRP09 | 1.29.15 | 1.28.15 | 1.29.14 | 1.28.14 | 1.29.13 | 1.28.13 | 1.29.12 | 1.28.12 | 1.29.11 | 1.28.11 | 1.29.10 | 1.28.10 | 1.29.9 | 1.28.9 | 1.29.8 | 1.28.8 |
| GTX0:DRP0A | 1.29.23 | 1.28.23 | 1.29.22 | 1.28.22 | 1.29.21 | 1.28.21 | 1.29.20 | 1.28.20 | 1.29.19 | 1.28.19 | 1.29.18 | 1.28.18 | 1.29.17 | 1.28.17 | 1.29.16 | 1.28.16 |
| GTX0:DRP0B | 1.29.31 | 1.28.31 | 1.29.30 | 1.28.30 | 1.29.29 | 1.28.29 | 1.29.28 | 1.28.28 | 1.29.27 | 1.28.27 | 1.29.26 | 1.28.26 | 1.29.25 | 1.28.25 | 1.29.24 | 1.28.24 |
| GTX0:DRP0C | 1.29.39 | 1.28.39 | 1.29.38 | 1.28.38 | 1.29.37 | 1.28.37 | 1.29.36 | 1.28.36 | 1.29.35 | 1.28.35 | 1.29.34 | 1.28.34 | 1.29.33 | 1.28.33 | 1.29.32 | 1.28.32 |
| GTX0:DRP0D | 1.29.47 | 1.28.47 | 1.29.46 | 1.28.46 | 1.29.45 | 1.28.45 | 1.29.44 | 1.28.44 | 1.29.43 | 1.28.43 | 1.29.42 | 1.28.42 | 1.29.41 | 1.28.41 | 1.29.40 | 1.28.40 |
| GTX0:DRP0E | 1.29.55 | 1.28.55 | 1.29.54 | 1.28.54 | 1.29.53 | 1.28.53 | 1.29.52 | 1.28.52 | 1.29.51 | 1.28.51 | 1.29.50 | 1.28.50 | 1.29.49 | 1.28.49 | 1.29.48 | 1.28.48 |
| GTX0:DRP0F | 1.29.63 | 1.28.63 | 1.29.62 | 1.28.62 | 1.29.61 | 1.28.61 | 1.29.60 | 1.28.60 | 1.29.59 | 1.28.59 | 1.29.58 | 1.28.58 | 1.29.57 | 1.28.57 | 1.29.56 | 1.28.56 |
| GTX0:DRP10 | 2.29.7 | 2.28.7 | 2.29.6 | 2.28.6 | 2.29.5 | 2.28.5 | 2.29.4 | 2.28.4 | 2.29.3 | 2.28.3 | 2.29.2 | 2.28.2 | 2.29.1 | 2.28.1 | 2.29.0 | 2.28.0 |
| GTX0:DRP11 | 2.29.15 | 2.28.15 | 2.29.14 | 2.28.14 | 2.29.13 | 2.28.13 | 2.29.12 | 2.28.12 | 2.29.11 | 2.28.11 | 2.29.10 | 2.28.10 | 2.29.9 | 2.28.9 | 2.29.8 | 2.28.8 |
| GTX0:DRP12 | 2.29.23 | 2.28.23 | 2.29.22 | 2.28.22 | 2.29.21 | 2.28.21 | 2.29.20 | 2.28.20 | 2.29.19 | 2.28.19 | 2.29.18 | 2.28.18 | 2.29.17 | 2.28.17 | 2.29.16 | 2.28.16 |
| GTX0:DRP13 | 2.29.31 | 2.28.31 | 2.29.30 | 2.28.30 | 2.29.29 | 2.28.29 | 2.29.28 | 2.28.28 | 2.29.27 | 2.28.27 | 2.29.26 | 2.28.26 | 2.29.25 | 2.28.25 | 2.29.24 | 2.28.24 |
| GTX0:DRP14 | 2.29.39 | 2.28.39 | 2.29.38 | 2.28.38 | 2.29.37 | 2.28.37 | 2.29.36 | 2.28.36 | 2.29.35 | 2.28.35 | 2.29.34 | 2.28.34 | 2.29.33 | 2.28.33 | 2.29.32 | 2.28.32 |
| GTX0:DRP15 | 2.29.47 | 2.28.47 | 2.29.46 | 2.28.46 | 2.29.45 | 2.28.45 | 2.29.44 | 2.28.44 | 2.29.43 | 2.28.43 | 2.29.42 | 2.28.42 | 2.29.41 | 2.28.41 | 2.29.40 | 2.28.40 |
| GTX0:DRP16 | 2.29.55 | 2.28.55 | 2.29.54 | 2.28.54 | 2.29.53 | 2.28.53 | 2.29.52 | 2.28.52 | 2.29.51 | 2.28.51 | 2.29.50 | 2.28.50 | 2.29.49 | 2.28.49 | 2.29.48 | 2.28.48 |
| GTX0:DRP17 | 2.29.63 | 2.28.63 | 2.29.62 | 2.28.62 | 2.29.61 | 2.28.61 | 2.29.60 | 2.28.60 | 2.29.59 | 2.28.59 | 2.29.58 | 2.28.58 | 2.29.57 | 2.28.57 | 2.29.56 | 2.28.56 |
| GTX0:DRP18 | 3.29.7 | 3.28.7 | 3.29.6 | 3.28.6 | 3.29.5 | 3.28.5 | 3.29.4 | 3.28.4 | 3.29.3 | 3.28.3 | 3.29.2 | 3.28.2 | 3.29.1 | 3.28.1 | 3.29.0 | 3.28.0 |
| GTX0:DRP19 | 3.29.15 | 3.28.15 | 3.29.14 | 3.28.14 | 3.29.13 | 3.28.13 | 3.29.12 | 3.28.12 | 3.29.11 | 3.28.11 | 3.29.10 | 3.28.10 | 3.29.9 | 3.28.9 | 3.29.8 | 3.28.8 |
| GTX0:DRP1A | 3.29.23 | 3.28.23 | 3.29.22 | 3.28.22 | 3.29.21 | 3.28.21 | 3.29.20 | 3.28.20 | 3.29.19 | 3.28.19 | 3.29.18 | 3.28.18 | 3.29.17 | 3.28.17 | 3.29.16 | 3.28.16 |
| GTX0:DRP1B | 3.29.31 | 3.28.31 | 3.29.30 | 3.28.30 | 3.29.29 | 3.28.29 | 3.29.28 | 3.28.28 | 3.29.27 | 3.28.27 | 3.29.26 | 3.28.26 | 3.29.25 | 3.28.25 | 3.29.24 | 3.28.24 |
| GTX0:DRP1C | 3.29.39 | 3.28.39 | 3.29.38 | 3.28.38 | 3.29.37 | 3.28.37 | 3.29.36 | 3.28.36 | 3.29.35 | 3.28.35 | 3.29.34 | 3.28.34 | 3.29.33 | 3.28.33 | 3.29.32 | 3.28.32 |
| GTX0:DRP1D | 3.29.47 | 3.28.47 | 3.29.46 | 3.28.46 | 3.29.45 | 3.28.45 | 3.29.44 | 3.28.44 | 3.29.43 | 3.28.43 | 3.29.42 | 3.28.42 | 3.29.41 | 3.28.41 | 3.29.40 | 3.28.40 |
| GTX0:DRP1E | 3.29.55 | 3.28.55 | 3.29.54 | 3.28.54 | 3.29.53 | 3.28.53 | 3.29.52 | 3.28.52 | 3.29.51 | 3.28.51 | 3.29.50 | 3.28.50 | 3.29.49 | 3.28.49 | 3.29.48 | 3.28.48 |
| GTX0:DRP1F | 3.29.63 | 3.28.63 | 3.29.62 | 3.28.62 | 3.29.61 | 3.28.61 | 3.29.60 | 3.28.60 | 3.29.59 | 3.28.59 | 3.29.58 | 3.28.58 | 3.29.57 | 3.28.57 | 3.29.56 | 3.28.56 |
| GTX0:DRP20 | 4.29.7 | 4.28.7 | 4.29.6 | 4.28.6 | 4.29.5 | 4.28.5 | 4.29.4 | 4.28.4 | 4.29.3 | 4.28.3 | 4.29.2 | 4.28.2 | 4.29.1 | 4.28.1 | 4.29.0 | 4.28.0 |
| GTX0:DRP21 | 4.29.15 | 4.28.15 | 4.29.14 | 4.28.14 | 4.29.13 | 4.28.13 | 4.29.12 | 4.28.12 | 4.29.11 | 4.28.11 | 4.29.10 | 4.28.10 | 4.29.9 | 4.28.9 | 4.29.8 | 4.28.8 |
| GTX0:DRP22 | 4.29.23 | 4.28.23 | 4.29.22 | 4.28.22 | 4.29.21 | 4.28.21 | 4.29.20 | 4.28.20 | 4.29.19 | 4.28.19 | 4.29.18 | 4.28.18 | 4.29.17 | 4.28.17 | 4.29.16 | 4.28.16 |
| GTX0:DRP23 | 4.29.31 | 4.28.31 | 4.29.30 | 4.28.30 | 4.29.29 | 4.28.29 | 4.29.28 | 4.28.28 | 4.29.27 | 4.28.27 | 4.29.26 | 4.28.26 | 4.29.25 | 4.28.25 | 4.29.24 | 4.28.24 |
| GTX0:DRP24 | 4.29.39 | 4.28.39 | 4.29.38 | 4.28.38 | 4.29.37 | 4.28.37 | 4.29.36 | 4.28.36 | 4.29.35 | 4.28.35 | 4.29.34 | 4.28.34 | 4.29.33 | 4.28.33 | 4.29.32 | 4.28.32 |
| GTX0:DRP25 | 4.29.47 | 4.28.47 | 4.29.46 | 4.28.46 | 4.29.45 | 4.28.45 | 4.29.44 | 4.28.44 | 4.29.43 | 4.28.43 | 4.29.42 | 4.28.42 | 4.29.41 | 4.28.41 | 4.29.40 | 4.28.40 |
| GTX0:DRP26 | 4.29.55 | 4.28.55 | 4.29.54 | 4.28.54 | 4.29.53 | 4.28.53 | 4.29.52 | 4.28.52 | 4.29.51 | 4.28.51 | 4.29.50 | 4.28.50 | 4.29.49 | 4.28.49 | 4.29.48 | 4.28.48 |
| GTX0:DRP27 | 4.29.63 | 4.28.63 | 4.29.62 | 4.28.62 | 4.29.61 | 4.28.61 | 4.29.60 | 4.28.60 | 4.29.59 | 4.28.59 | 4.29.58 | 4.28.58 | 4.29.57 | 4.28.57 | 4.29.56 | 4.28.56 |
| GTX0:DRP28 | 5.29.7 | 5.28.7 | 5.29.6 | 5.28.6 | 5.29.5 | 5.28.5 | 5.29.4 | 5.28.4 | 5.29.3 | 5.28.3 | 5.29.2 | 5.28.2 | 5.29.1 | 5.28.1 | 5.29.0 | 5.28.0 |
| GTX0:DRP29 | 5.29.15 | 5.28.15 | 5.29.14 | 5.28.14 | 5.29.13 | 5.28.13 | 5.29.12 | 5.28.12 | 5.29.11 | 5.28.11 | 5.29.10 | 5.28.10 | 5.29.9 | 5.28.9 | 5.29.8 | 5.28.8 |
| GTX0:DRP2A | 5.29.23 | 5.28.23 | 5.29.22 | 5.28.22 | 5.29.21 | 5.28.21 | 5.29.20 | 5.28.20 | 5.29.19 | 5.28.19 | 5.29.18 | 5.28.18 | 5.29.17 | 5.28.17 | 5.29.16 | 5.28.16 |
| GTX0:DRP2B | 5.29.31 | 5.28.31 | 5.29.30 | 5.28.30 | 5.29.29 | 5.28.29 | 5.29.28 | 5.28.28 | 5.29.27 | 5.28.27 | 5.29.26 | 5.28.26 | 5.29.25 | 5.28.25 | 5.29.24 | 5.28.24 |
| GTX0:DRP2C | 5.29.39 | 5.28.39 | 5.29.38 | 5.28.38 | 5.29.37 | 5.28.37 | 5.29.36 | 5.28.36 | 5.29.35 | 5.28.35 | 5.29.34 | 5.28.34 | 5.29.33 | 5.28.33 | 5.29.32 | 5.28.32 |
| GTX0:DRP2D | 5.29.47 | 5.28.47 | 5.29.46 | 5.28.46 | 5.29.45 | 5.28.45 | 5.29.44 | 5.28.44 | 5.29.43 | 5.28.43 | 5.29.42 | 5.28.42 | 5.29.41 | 5.28.41 | 5.29.40 | 5.28.40 |
| GTX0:DRP2E | 5.29.55 | 5.28.55 | 5.29.54 | 5.28.54 | 5.29.53 | 5.28.53 | 5.29.52 | 5.28.52 | 5.29.51 | 5.28.51 | 5.29.50 | 5.28.50 | 5.29.49 | 5.28.49 | 5.29.48 | 5.28.48 |
| GTX0:DRP2F | 5.29.63 | 5.28.63 | 5.29.62 | 5.28.62 | 5.29.61 | 5.28.61 | 5.29.60 | 5.28.60 | 5.29.59 | 5.28.59 | 5.29.58 | 5.28.58 | 5.29.57 | 5.28.57 | 5.29.56 | 5.28.56 |
| GTX0:DRP30 | 6.29.7 | 6.28.7 | 6.29.6 | 6.28.6 | 6.29.5 | 6.28.5 | 6.29.4 | 6.28.4 | 6.29.3 | 6.28.3 | 6.29.2 | 6.28.2 | 6.29.1 | 6.28.1 | 6.29.0 | 6.28.0 |
| GTX0:DRP31 | 6.29.15 | 6.28.15 | 6.29.14 | 6.28.14 | 6.29.13 | 6.28.13 | 6.29.12 | 6.28.12 | 6.29.11 | 6.28.11 | 6.29.10 | 6.28.10 | 6.29.9 | 6.28.9 | 6.29.8 | 6.28.8 |
| GTX0:DRP32 | 6.29.23 | 6.28.23 | 6.29.22 | 6.28.22 | 6.29.21 | 6.28.21 | 6.29.20 | 6.28.20 | 6.29.19 | 6.28.19 | 6.29.18 | 6.28.18 | 6.29.17 | 6.28.17 | 6.29.16 | 6.28.16 |
| GTX0:DRP33 | 6.29.31 | 6.28.31 | 6.29.30 | 6.28.30 | 6.29.29 | 6.28.29 | 6.29.28 | 6.28.28 | 6.29.27 | 6.28.27 | 6.29.26 | 6.28.26 | 6.29.25 | 6.28.25 | 6.29.24 | 6.28.24 |
| GTX0:DRP34 | 6.29.39 | 6.28.39 | 6.29.38 | 6.28.38 | 6.29.37 | 6.28.37 | 6.29.36 | 6.28.36 | 6.29.35 | 6.28.35 | 6.29.34 | 6.28.34 | 6.29.33 | 6.28.33 | 6.29.32 | 6.28.32 |
| GTX0:DRP35 | 6.29.47 | 6.28.47 | 6.29.46 | 6.28.46 | 6.29.45 | 6.28.45 | 6.29.44 | 6.28.44 | 6.29.43 | 6.28.43 | 6.29.42 | 6.28.42 | 6.29.41 | 6.28.41 | 6.29.40 | 6.28.40 |
| GTX0:DRP36 | 6.29.55 | 6.28.55 | 6.29.54 | 6.28.54 | 6.29.53 | 6.28.53 | 6.29.52 | 6.28.52 | 6.29.51 | 6.28.51 | 6.29.50 | 6.28.50 | 6.29.49 | 6.28.49 | 6.29.48 | 6.28.48 |
| GTX0:DRP37 | 6.29.63 | 6.28.63 | 6.29.62 | 6.28.62 | 6.29.61 | 6.28.61 | 6.29.60 | 6.28.60 | 6.29.59 | 6.28.59 | 6.29.58 | 6.28.58 | 6.29.57 | 6.28.57 | 6.29.56 | 6.28.56 |
| GTX0:DRP38 | 7.29.7 | 7.28.7 | 7.29.6 | 7.28.6 | 7.29.5 | 7.28.5 | 7.29.4 | 7.28.4 | 7.29.3 | 7.28.3 | 7.29.2 | 7.28.2 | 7.29.1 | 7.28.1 | 7.29.0 | 7.28.0 |
| GTX0:DRP39 | 7.29.15 | 7.28.15 | 7.29.14 | 7.28.14 | 7.29.13 | 7.28.13 | 7.29.12 | 7.28.12 | 7.29.11 | 7.28.11 | 7.29.10 | 7.28.10 | 7.29.9 | 7.28.9 | 7.29.8 | 7.28.8 |
| GTX0:DRP3A | 7.29.23 | 7.28.23 | 7.29.22 | 7.28.22 | 7.29.21 | 7.28.21 | 7.29.20 | 7.28.20 | 7.29.19 | 7.28.19 | 7.29.18 | 7.28.18 | 7.29.17 | 7.28.17 | 7.29.16 | 7.28.16 |
| GTX0:DRP3B | 7.29.31 | 7.28.31 | 7.29.30 | 7.28.30 | 7.29.29 | 7.28.29 | 7.29.28 | 7.28.28 | 7.29.27 | 7.28.27 | 7.29.26 | 7.28.26 | 7.29.25 | 7.28.25 | 7.29.24 | 7.28.24 |
| GTX0:DRP3C | 7.29.39 | 7.28.39 | 7.29.38 | 7.28.38 | 7.29.37 | 7.28.37 | 7.29.36 | 7.28.36 | 7.29.35 | 7.28.35 | 7.29.34 | 7.28.34 | 7.29.33 | 7.28.33 | 7.29.32 | 7.28.32 |
| GTX0:DRP3D | 7.29.47 | 7.28.47 | 7.29.46 | 7.28.46 | 7.29.45 | 7.28.45 | 7.29.44 | 7.28.44 | 7.29.43 | 7.28.43 | 7.29.42 | 7.28.42 | 7.29.41 | 7.28.41 | 7.29.40 | 7.28.40 |
| GTX0:DRP3E | 7.29.55 | 7.28.55 | 7.29.54 | 7.28.54 | 7.29.53 | 7.28.53 | 7.29.52 | 7.28.52 | 7.29.51 | 7.28.51 | 7.29.50 | 7.28.50 | 7.29.49 | 7.28.49 | 7.29.48 | 7.28.48 |
| GTX0:DRP3F | 7.29.63 | 7.28.63 | 7.29.62 | 7.28.62 | 7.29.61 | 7.28.61 | 7.29.60 | 7.28.60 | 7.29.59 | 7.28.59 | 7.29.58 | 7.28.58 | 7.29.57 | 7.28.57 | 7.29.56 | 7.28.56 |
| GTX0:DRP40 | 8.29.7 | 8.28.7 | 8.29.6 | 8.28.6 | 8.29.5 | 8.28.5 | 8.29.4 | 8.28.4 | 8.29.3 | 8.28.3 | 8.29.2 | 8.28.2 | 8.29.1 | 8.28.1 | 8.29.0 | 8.28.0 |
| GTX0:DRP41 | 8.29.15 | 8.28.15 | 8.29.14 | 8.28.14 | 8.29.13 | 8.28.13 | 8.29.12 | 8.28.12 | 8.29.11 | 8.28.11 | 8.29.10 | 8.28.10 | 8.29.9 | 8.28.9 | 8.29.8 | 8.28.8 |
| GTX0:DRP42 | 8.29.23 | 8.28.23 | 8.29.22 | 8.28.22 | 8.29.21 | 8.28.21 | 8.29.20 | 8.28.20 | 8.29.19 | 8.28.19 | 8.29.18 | 8.28.18 | 8.29.17 | 8.28.17 | 8.29.16 | 8.28.16 |
| GTX0:DRP43 | 8.29.31 | 8.28.31 | 8.29.30 | 8.28.30 | 8.29.29 | 8.28.29 | 8.29.28 | 8.28.28 | 8.29.27 | 8.28.27 | 8.29.26 | 8.28.26 | 8.29.25 | 8.28.25 | 8.29.24 | 8.28.24 |
| GTX0:DRP44 | 8.29.39 | 8.28.39 | 8.29.38 | 8.28.38 | 8.29.37 | 8.28.37 | 8.29.36 | 8.28.36 | 8.29.35 | 8.28.35 | 8.29.34 | 8.28.34 | 8.29.33 | 8.28.33 | 8.29.32 | 8.28.32 |
| GTX0:DRP45 | 8.29.47 | 8.28.47 | 8.29.46 | 8.28.46 | 8.29.45 | 8.28.45 | 8.29.44 | 8.28.44 | 8.29.43 | 8.28.43 | 8.29.42 | 8.28.42 | 8.29.41 | 8.28.41 | 8.29.40 | 8.28.40 |
| GTX0:DRP46 | 8.29.55 | 8.28.55 | 8.29.54 | 8.28.54 | 8.29.53 | 8.28.53 | 8.29.52 | 8.28.52 | 8.29.51 | 8.28.51 | 8.29.50 | 8.28.50 | 8.29.49 | 8.28.49 | 8.29.48 | 8.28.48 |
| GTX0:DRP47 | 8.29.63 | 8.28.63 | 8.29.62 | 8.28.62 | 8.29.61 | 8.28.61 | 8.29.60 | 8.28.60 | 8.29.59 | 8.28.59 | 8.29.58 | 8.28.58 | 8.29.57 | 8.28.57 | 8.29.56 | 8.28.56 |
| GTX0:DRP48 | 9.29.7 | 9.28.7 | 9.29.6 | 9.28.6 | 9.29.5 | 9.28.5 | 9.29.4 | 9.28.4 | 9.29.3 | 9.28.3 | 9.29.2 | 9.28.2 | 9.29.1 | 9.28.1 | 9.29.0 | 9.28.0 |
| GTX0:DRP49 | 9.29.15 | 9.28.15 | 9.29.14 | 9.28.14 | 9.29.13 | 9.28.13 | 9.29.12 | 9.28.12 | 9.29.11 | 9.28.11 | 9.29.10 | 9.28.10 | 9.29.9 | 9.28.9 | 9.29.8 | 9.28.8 |
| GTX0:DRP4A | 9.29.23 | 9.28.23 | 9.29.22 | 9.28.22 | 9.29.21 | 9.28.21 | 9.29.20 | 9.28.20 | 9.29.19 | 9.28.19 | 9.29.18 | 9.28.18 | 9.29.17 | 9.28.17 | 9.29.16 | 9.28.16 |
| GTX0:DRP4B | 9.29.31 | 9.28.31 | 9.29.30 | 9.28.30 | 9.29.29 | 9.28.29 | 9.29.28 | 9.28.28 | 9.29.27 | 9.28.27 | 9.29.26 | 9.28.26 | 9.29.25 | 9.28.25 | 9.29.24 | 9.28.24 |
| GTX0:DRP4C | 9.29.39 | 9.28.39 | 9.29.38 | 9.28.38 | 9.29.37 | 9.28.37 | 9.29.36 | 9.28.36 | 9.29.35 | 9.28.35 | 9.29.34 | 9.28.34 | 9.29.33 | 9.28.33 | 9.29.32 | 9.28.32 |
| GTX0:DRP4D | 9.29.47 | 9.28.47 | 9.29.46 | 9.28.46 | 9.29.45 | 9.28.45 | 9.29.44 | 9.28.44 | 9.29.43 | 9.28.43 | 9.29.42 | 9.28.42 | 9.29.41 | 9.28.41 | 9.29.40 | 9.28.40 |
| GTX0:DRP4E | 9.29.55 | 9.28.55 | 9.29.54 | 9.28.54 | 9.29.53 | 9.28.53 | 9.29.52 | 9.28.52 | 9.29.51 | 9.28.51 | 9.29.50 | 9.28.50 | 9.29.49 | 9.28.49 | 9.29.48 | 9.28.48 |
| GTX0:DRP4F | 9.29.63 | 9.28.63 | 9.29.62 | 9.28.62 | 9.29.61 | 9.28.61 | 9.29.60 | 9.28.60 | 9.29.59 | 9.28.59 | 9.29.58 | 9.28.58 | 9.29.57 | 9.28.57 | 9.29.56 | 9.28.56 |
| GTX0:RXUSRCLK_DLY | 0.29.23 | 0.28.23 | 0.29.22 | 0.28.22 | 0.29.21 | 0.28.21 | 0.29.20 | 0.28.20 | 0.29.19 | 0.28.19 | 0.29.18 | 0.28.18 | 0.29.17 | 0.28.17 | 0.29.16 | 0.28.16 |
| GTX1:DRP00 | 10.29.7 | 10.28.7 | 10.29.6 | 10.28.6 | 10.29.5 | 10.28.5 | 10.29.4 | 10.28.4 | 10.29.3 | 10.28.3 | 10.29.2 | 10.28.2 | 10.29.1 | 10.28.1 | 10.29.0 | 10.28.0 |
| GTX1:DRP01 | 10.29.15 | 10.28.15 | 10.29.14 | 10.28.14 | 10.29.13 | 10.28.13 | 10.29.12 | 10.28.12 | 10.29.11 | 10.28.11 | 10.29.10 | 10.28.10 | 10.29.9 | 10.28.9 | 10.29.8 | 10.28.8 |
| GTX1:DRP02 | 10.29.23 | 10.28.23 | 10.29.22 | 10.28.22 | 10.29.21 | 10.28.21 | 10.29.20 | 10.28.20 | 10.29.19 | 10.28.19 | 10.29.18 | 10.28.18 | 10.29.17 | 10.28.17 | 10.29.16 | 10.28.16 |
| GTX1:DRP03 | 10.29.31 | 10.28.31 | 10.29.30 | 10.28.30 | 10.29.29 | 10.28.29 | 10.29.28 | 10.28.28 | 10.29.27 | 10.28.27 | 10.29.26 | 10.28.26 | 10.29.25 | 10.28.25 | 10.29.24 | 10.28.24 |
| GTX1:DRP04 | 10.29.39 | 10.28.39 | 10.29.38 | 10.28.38 | 10.29.37 | 10.28.37 | 10.29.36 | 10.28.36 | 10.29.35 | 10.28.35 | 10.29.34 | 10.28.34 | 10.29.33 | 10.28.33 | 10.29.32 | 10.28.32 |
| GTX1:DRP05 | 10.29.47 | 10.28.47 | 10.29.46 | 10.28.46 | 10.29.45 | 10.28.45 | 10.29.44 | 10.28.44 | 10.29.43 | 10.28.43 | 10.29.42 | 10.28.42 | 10.29.41 | 10.28.41 | 10.29.40 | 10.28.40 |
| GTX1:DRP06 | 10.29.55 | 10.28.55 | 10.29.54 | 10.28.54 | 10.29.53 | 10.28.53 | 10.29.52 | 10.28.52 | 10.29.51 | 10.28.51 | 10.29.50 | 10.28.50 | 10.29.49 | 10.28.49 | 10.29.48 | 10.28.48 |
| GTX1:DRP07 | 10.29.63 | 10.28.63 | 10.29.62 | 10.28.62 | 10.29.61 | 10.28.61 | 10.29.60 | 10.28.60 | 10.29.59 | 10.28.59 | 10.29.58 | 10.28.58 | 10.29.57 | 10.28.57 | 10.29.56 | 10.28.56 |
| GTX1:DRP08 | 11.29.7 | 11.28.7 | 11.29.6 | 11.28.6 | 11.29.5 | 11.28.5 | 11.29.4 | 11.28.4 | 11.29.3 | 11.28.3 | 11.29.2 | 11.28.2 | 11.29.1 | 11.28.1 | 11.29.0 | 11.28.0 |
| GTX1:DRP09 | 11.29.15 | 11.28.15 | 11.29.14 | 11.28.14 | 11.29.13 | 11.28.13 | 11.29.12 | 11.28.12 | 11.29.11 | 11.28.11 | 11.29.10 | 11.28.10 | 11.29.9 | 11.28.9 | 11.29.8 | 11.28.8 |
| GTX1:DRP0A | 11.29.23 | 11.28.23 | 11.29.22 | 11.28.22 | 11.29.21 | 11.28.21 | 11.29.20 | 11.28.20 | 11.29.19 | 11.28.19 | 11.29.18 | 11.28.18 | 11.29.17 | 11.28.17 | 11.29.16 | 11.28.16 |
| GTX1:DRP0B | 11.29.31 | 11.28.31 | 11.29.30 | 11.28.30 | 11.29.29 | 11.28.29 | 11.29.28 | 11.28.28 | 11.29.27 | 11.28.27 | 11.29.26 | 11.28.26 | 11.29.25 | 11.28.25 | 11.29.24 | 11.28.24 |
| GTX1:DRP0C | 11.29.39 | 11.28.39 | 11.29.38 | 11.28.38 | 11.29.37 | 11.28.37 | 11.29.36 | 11.28.36 | 11.29.35 | 11.28.35 | 11.29.34 | 11.28.34 | 11.29.33 | 11.28.33 | 11.29.32 | 11.28.32 |
| GTX1:DRP0D | 11.29.47 | 11.28.47 | 11.29.46 | 11.28.46 | 11.29.45 | 11.28.45 | 11.29.44 | 11.28.44 | 11.29.43 | 11.28.43 | 11.29.42 | 11.28.42 | 11.29.41 | 11.28.41 | 11.29.40 | 11.28.40 |
| GTX1:DRP0E | 11.29.55 | 11.28.55 | 11.29.54 | 11.28.54 | 11.29.53 | 11.28.53 | 11.29.52 | 11.28.52 | 11.29.51 | 11.28.51 | 11.29.50 | 11.28.50 | 11.29.49 | 11.28.49 | 11.29.48 | 11.28.48 |
| GTX1:DRP0F | 11.29.63 | 11.28.63 | 11.29.62 | 11.28.62 | 11.29.61 | 11.28.61 | 11.29.60 | 11.28.60 | 11.29.59 | 11.28.59 | 11.29.58 | 11.28.58 | 11.29.57 | 11.28.57 | 11.29.56 | 11.28.56 |
| GTX1:DRP10 | 12.29.7 | 12.28.7 | 12.29.6 | 12.28.6 | 12.29.5 | 12.28.5 | 12.29.4 | 12.28.4 | 12.29.3 | 12.28.3 | 12.29.2 | 12.28.2 | 12.29.1 | 12.28.1 | 12.29.0 | 12.28.0 |
| GTX1:DRP11 | 12.29.15 | 12.28.15 | 12.29.14 | 12.28.14 | 12.29.13 | 12.28.13 | 12.29.12 | 12.28.12 | 12.29.11 | 12.28.11 | 12.29.10 | 12.28.10 | 12.29.9 | 12.28.9 | 12.29.8 | 12.28.8 |
| GTX1:DRP12 | 12.29.23 | 12.28.23 | 12.29.22 | 12.28.22 | 12.29.21 | 12.28.21 | 12.29.20 | 12.28.20 | 12.29.19 | 12.28.19 | 12.29.18 | 12.28.18 | 12.29.17 | 12.28.17 | 12.29.16 | 12.28.16 |
| GTX1:DRP13 | 12.29.31 | 12.28.31 | 12.29.30 | 12.28.30 | 12.29.29 | 12.28.29 | 12.29.28 | 12.28.28 | 12.29.27 | 12.28.27 | 12.29.26 | 12.28.26 | 12.29.25 | 12.28.25 | 12.29.24 | 12.28.24 |
| GTX1:DRP14 | 12.29.39 | 12.28.39 | 12.29.38 | 12.28.38 | 12.29.37 | 12.28.37 | 12.29.36 | 12.28.36 | 12.29.35 | 12.28.35 | 12.29.34 | 12.28.34 | 12.29.33 | 12.28.33 | 12.29.32 | 12.28.32 |
| GTX1:DRP15 | 12.29.47 | 12.28.47 | 12.29.46 | 12.28.46 | 12.29.45 | 12.28.45 | 12.29.44 | 12.28.44 | 12.29.43 | 12.28.43 | 12.29.42 | 12.28.42 | 12.29.41 | 12.28.41 | 12.29.40 | 12.28.40 |
| GTX1:DRP16 | 12.29.55 | 12.28.55 | 12.29.54 | 12.28.54 | 12.29.53 | 12.28.53 | 12.29.52 | 12.28.52 | 12.29.51 | 12.28.51 | 12.29.50 | 12.28.50 | 12.29.49 | 12.28.49 | 12.29.48 | 12.28.48 |
| GTX1:DRP17 | 12.29.63 | 12.28.63 | 12.29.62 | 12.28.62 | 12.29.61 | 12.28.61 | 12.29.60 | 12.28.60 | 12.29.59 | 12.28.59 | 12.29.58 | 12.28.58 | 12.29.57 | 12.28.57 | 12.29.56 | 12.28.56 |
| GTX1:DRP18 | 13.29.7 | 13.28.7 | 13.29.6 | 13.28.6 | 13.29.5 | 13.28.5 | 13.29.4 | 13.28.4 | 13.29.3 | 13.28.3 | 13.29.2 | 13.28.2 | 13.29.1 | 13.28.1 | 13.29.0 | 13.28.0 |
| GTX1:DRP19 | 13.29.15 | 13.28.15 | 13.29.14 | 13.28.14 | 13.29.13 | 13.28.13 | 13.29.12 | 13.28.12 | 13.29.11 | 13.28.11 | 13.29.10 | 13.28.10 | 13.29.9 | 13.28.9 | 13.29.8 | 13.28.8 |
| GTX1:DRP1A | 13.29.23 | 13.28.23 | 13.29.22 | 13.28.22 | 13.29.21 | 13.28.21 | 13.29.20 | 13.28.20 | 13.29.19 | 13.28.19 | 13.29.18 | 13.28.18 | 13.29.17 | 13.28.17 | 13.29.16 | 13.28.16 |
| GTX1:DRP1B | 13.29.31 | 13.28.31 | 13.29.30 | 13.28.30 | 13.29.29 | 13.28.29 | 13.29.28 | 13.28.28 | 13.29.27 | 13.28.27 | 13.29.26 | 13.28.26 | 13.29.25 | 13.28.25 | 13.29.24 | 13.28.24 |
| GTX1:DRP1C | 13.29.39 | 13.28.39 | 13.29.38 | 13.28.38 | 13.29.37 | 13.28.37 | 13.29.36 | 13.28.36 | 13.29.35 | 13.28.35 | 13.29.34 | 13.28.34 | 13.29.33 | 13.28.33 | 13.29.32 | 13.28.32 |
| GTX1:DRP1D | 13.29.47 | 13.28.47 | 13.29.46 | 13.28.46 | 13.29.45 | 13.28.45 | 13.29.44 | 13.28.44 | 13.29.43 | 13.28.43 | 13.29.42 | 13.28.42 | 13.29.41 | 13.28.41 | 13.29.40 | 13.28.40 |
| GTX1:DRP1E | 13.29.55 | 13.28.55 | 13.29.54 | 13.28.54 | 13.29.53 | 13.28.53 | 13.29.52 | 13.28.52 | 13.29.51 | 13.28.51 | 13.29.50 | 13.28.50 | 13.29.49 | 13.28.49 | 13.29.48 | 13.28.48 |
| GTX1:DRP1F | 13.29.63 | 13.28.63 | 13.29.62 | 13.28.62 | 13.29.61 | 13.28.61 | 13.29.60 | 13.28.60 | 13.29.59 | 13.28.59 | 13.29.58 | 13.28.58 | 13.29.57 | 13.28.57 | 13.29.56 | 13.28.56 |
| GTX1:DRP20 | 14.29.7 | 14.28.7 | 14.29.6 | 14.28.6 | 14.29.5 | 14.28.5 | 14.29.4 | 14.28.4 | 14.29.3 | 14.28.3 | 14.29.2 | 14.28.2 | 14.29.1 | 14.28.1 | 14.29.0 | 14.28.0 |
| GTX1:DRP21 | 14.29.15 | 14.28.15 | 14.29.14 | 14.28.14 | 14.29.13 | 14.28.13 | 14.29.12 | 14.28.12 | 14.29.11 | 14.28.11 | 14.29.10 | 14.28.10 | 14.29.9 | 14.28.9 | 14.29.8 | 14.28.8 |
| GTX1:DRP22 | 14.29.23 | 14.28.23 | 14.29.22 | 14.28.22 | 14.29.21 | 14.28.21 | 14.29.20 | 14.28.20 | 14.29.19 | 14.28.19 | 14.29.18 | 14.28.18 | 14.29.17 | 14.28.17 | 14.29.16 | 14.28.16 |
| GTX1:DRP23 | 14.29.31 | 14.28.31 | 14.29.30 | 14.28.30 | 14.29.29 | 14.28.29 | 14.29.28 | 14.28.28 | 14.29.27 | 14.28.27 | 14.29.26 | 14.28.26 | 14.29.25 | 14.28.25 | 14.29.24 | 14.28.24 |
| GTX1:DRP24 | 14.29.39 | 14.28.39 | 14.29.38 | 14.28.38 | 14.29.37 | 14.28.37 | 14.29.36 | 14.28.36 | 14.29.35 | 14.28.35 | 14.29.34 | 14.28.34 | 14.29.33 | 14.28.33 | 14.29.32 | 14.28.32 |
| GTX1:DRP25 | 14.29.47 | 14.28.47 | 14.29.46 | 14.28.46 | 14.29.45 | 14.28.45 | 14.29.44 | 14.28.44 | 14.29.43 | 14.28.43 | 14.29.42 | 14.28.42 | 14.29.41 | 14.28.41 | 14.29.40 | 14.28.40 |
| GTX1:DRP26 | 14.29.55 | 14.28.55 | 14.29.54 | 14.28.54 | 14.29.53 | 14.28.53 | 14.29.52 | 14.28.52 | 14.29.51 | 14.28.51 | 14.29.50 | 14.28.50 | 14.29.49 | 14.28.49 | 14.29.48 | 14.28.48 |
| GTX1:DRP27 | 14.29.63 | 14.28.63 | 14.29.62 | 14.28.62 | 14.29.61 | 14.28.61 | 14.29.60 | 14.28.60 | 14.29.59 | 14.28.59 | 14.29.58 | 14.28.58 | 14.29.57 | 14.28.57 | 14.29.56 | 14.28.56 |
| GTX1:DRP28 | 15.29.7 | 15.28.7 | 15.29.6 | 15.28.6 | 15.29.5 | 15.28.5 | 15.29.4 | 15.28.4 | 15.29.3 | 15.28.3 | 15.29.2 | 15.28.2 | 15.29.1 | 15.28.1 | 15.29.0 | 15.28.0 |
| GTX1:DRP29 | 15.29.15 | 15.28.15 | 15.29.14 | 15.28.14 | 15.29.13 | 15.28.13 | 15.29.12 | 15.28.12 | 15.29.11 | 15.28.11 | 15.29.10 | 15.28.10 | 15.29.9 | 15.28.9 | 15.29.8 | 15.28.8 |
| GTX1:DRP2A | 15.29.23 | 15.28.23 | 15.29.22 | 15.28.22 | 15.29.21 | 15.28.21 | 15.29.20 | 15.28.20 | 15.29.19 | 15.28.19 | 15.29.18 | 15.28.18 | 15.29.17 | 15.28.17 | 15.29.16 | 15.28.16 |
| GTX1:DRP2B | 15.29.31 | 15.28.31 | 15.29.30 | 15.28.30 | 15.29.29 | 15.28.29 | 15.29.28 | 15.28.28 | 15.29.27 | 15.28.27 | 15.29.26 | 15.28.26 | 15.29.25 | 15.28.25 | 15.29.24 | 15.28.24 |
| GTX1:DRP2C | 15.29.39 | 15.28.39 | 15.29.38 | 15.28.38 | 15.29.37 | 15.28.37 | 15.29.36 | 15.28.36 | 15.29.35 | 15.28.35 | 15.29.34 | 15.28.34 | 15.29.33 | 15.28.33 | 15.29.32 | 15.28.32 |
| GTX1:DRP2D | 15.29.47 | 15.28.47 | 15.29.46 | 15.28.46 | 15.29.45 | 15.28.45 | 15.29.44 | 15.28.44 | 15.29.43 | 15.28.43 | 15.29.42 | 15.28.42 | 15.29.41 | 15.28.41 | 15.29.40 | 15.28.40 |
| GTX1:DRP2E | 15.29.55 | 15.28.55 | 15.29.54 | 15.28.54 | 15.29.53 | 15.28.53 | 15.29.52 | 15.28.52 | 15.29.51 | 15.28.51 | 15.29.50 | 15.28.50 | 15.29.49 | 15.28.49 | 15.29.48 | 15.28.48 |
| GTX1:DRP2F | 15.29.63 | 15.28.63 | 15.29.62 | 15.28.62 | 15.29.61 | 15.28.61 | 15.29.60 | 15.28.60 | 15.29.59 | 15.28.59 | 15.29.58 | 15.28.58 | 15.29.57 | 15.28.57 | 15.29.56 | 15.28.56 |
| GTX1:DRP30 | 16.29.7 | 16.28.7 | 16.29.6 | 16.28.6 | 16.29.5 | 16.28.5 | 16.29.4 | 16.28.4 | 16.29.3 | 16.28.3 | 16.29.2 | 16.28.2 | 16.29.1 | 16.28.1 | 16.29.0 | 16.28.0 |
| GTX1:DRP31 | 16.29.15 | 16.28.15 | 16.29.14 | 16.28.14 | 16.29.13 | 16.28.13 | 16.29.12 | 16.28.12 | 16.29.11 | 16.28.11 | 16.29.10 | 16.28.10 | 16.29.9 | 16.28.9 | 16.29.8 | 16.28.8 |
| GTX1:DRP32 | 16.29.23 | 16.28.23 | 16.29.22 | 16.28.22 | 16.29.21 | 16.28.21 | 16.29.20 | 16.28.20 | 16.29.19 | 16.28.19 | 16.29.18 | 16.28.18 | 16.29.17 | 16.28.17 | 16.29.16 | 16.28.16 |
| GTX1:DRP33 | 16.29.31 | 16.28.31 | 16.29.30 | 16.28.30 | 16.29.29 | 16.28.29 | 16.29.28 | 16.28.28 | 16.29.27 | 16.28.27 | 16.29.26 | 16.28.26 | 16.29.25 | 16.28.25 | 16.29.24 | 16.28.24 |
| GTX1:DRP34 | 16.29.39 | 16.28.39 | 16.29.38 | 16.28.38 | 16.29.37 | 16.28.37 | 16.29.36 | 16.28.36 | 16.29.35 | 16.28.35 | 16.29.34 | 16.28.34 | 16.29.33 | 16.28.33 | 16.29.32 | 16.28.32 |
| GTX1:DRP35 | 16.29.47 | 16.28.47 | 16.29.46 | 16.28.46 | 16.29.45 | 16.28.45 | 16.29.44 | 16.28.44 | 16.29.43 | 16.28.43 | 16.29.42 | 16.28.42 | 16.29.41 | 16.28.41 | 16.29.40 | 16.28.40 |
| GTX1:DRP36 | 16.29.55 | 16.28.55 | 16.29.54 | 16.28.54 | 16.29.53 | 16.28.53 | 16.29.52 | 16.28.52 | 16.29.51 | 16.28.51 | 16.29.50 | 16.28.50 | 16.29.49 | 16.28.49 | 16.29.48 | 16.28.48 |
| GTX1:DRP37 | 16.29.63 | 16.28.63 | 16.29.62 | 16.28.62 | 16.29.61 | 16.28.61 | 16.29.60 | 16.28.60 | 16.29.59 | 16.28.59 | 16.29.58 | 16.28.58 | 16.29.57 | 16.28.57 | 16.29.56 | 16.28.56 |
| GTX1:DRP38 | 17.29.7 | 17.28.7 | 17.29.6 | 17.28.6 | 17.29.5 | 17.28.5 | 17.29.4 | 17.28.4 | 17.29.3 | 17.28.3 | 17.29.2 | 17.28.2 | 17.29.1 | 17.28.1 | 17.29.0 | 17.28.0 |
| GTX1:DRP39 | 17.29.15 | 17.28.15 | 17.29.14 | 17.28.14 | 17.29.13 | 17.28.13 | 17.29.12 | 17.28.12 | 17.29.11 | 17.28.11 | 17.29.10 | 17.28.10 | 17.29.9 | 17.28.9 | 17.29.8 | 17.28.8 |
| GTX1:DRP3A | 17.29.23 | 17.28.23 | 17.29.22 | 17.28.22 | 17.29.21 | 17.28.21 | 17.29.20 | 17.28.20 | 17.29.19 | 17.28.19 | 17.29.18 | 17.28.18 | 17.29.17 | 17.28.17 | 17.29.16 | 17.28.16 |
| GTX1:DRP3B | 17.29.31 | 17.28.31 | 17.29.30 | 17.28.30 | 17.29.29 | 17.28.29 | 17.29.28 | 17.28.28 | 17.29.27 | 17.28.27 | 17.29.26 | 17.28.26 | 17.29.25 | 17.28.25 | 17.29.24 | 17.28.24 |
| GTX1:DRP3C | 17.29.39 | 17.28.39 | 17.29.38 | 17.28.38 | 17.29.37 | 17.28.37 | 17.29.36 | 17.28.36 | 17.29.35 | 17.28.35 | 17.29.34 | 17.28.34 | 17.29.33 | 17.28.33 | 17.29.32 | 17.28.32 |
| GTX1:DRP3D | 17.29.47 | 17.28.47 | 17.29.46 | 17.28.46 | 17.29.45 | 17.28.45 | 17.29.44 | 17.28.44 | 17.29.43 | 17.28.43 | 17.29.42 | 17.28.42 | 17.29.41 | 17.28.41 | 17.29.40 | 17.28.40 |
| GTX1:DRP3E | 17.29.55 | 17.28.55 | 17.29.54 | 17.28.54 | 17.29.53 | 17.28.53 | 17.29.52 | 17.28.52 | 17.29.51 | 17.28.51 | 17.29.50 | 17.28.50 | 17.29.49 | 17.28.49 | 17.29.48 | 17.28.48 |
| GTX1:DRP3F | 17.29.63 | 17.28.63 | 17.29.62 | 17.28.62 | 17.29.61 | 17.28.61 | 17.29.60 | 17.28.60 | 17.29.59 | 17.28.59 | 17.29.58 | 17.28.58 | 17.29.57 | 17.28.57 | 17.29.56 | 17.28.56 |
| GTX1:DRP40 | 18.29.7 | 18.28.7 | 18.29.6 | 18.28.6 | 18.29.5 | 18.28.5 | 18.29.4 | 18.28.4 | 18.29.3 | 18.28.3 | 18.29.2 | 18.28.2 | 18.29.1 | 18.28.1 | 18.29.0 | 18.28.0 |
| GTX1:DRP41 | 18.29.15 | 18.28.15 | 18.29.14 | 18.28.14 | 18.29.13 | 18.28.13 | 18.29.12 | 18.28.12 | 18.29.11 | 18.28.11 | 18.29.10 | 18.28.10 | 18.29.9 | 18.28.9 | 18.29.8 | 18.28.8 |
| GTX1:DRP42 | 18.29.23 | 18.28.23 | 18.29.22 | 18.28.22 | 18.29.21 | 18.28.21 | 18.29.20 | 18.28.20 | 18.29.19 | 18.28.19 | 18.29.18 | 18.28.18 | 18.29.17 | 18.28.17 | 18.29.16 | 18.28.16 |
| GTX1:DRP43 | 18.29.31 | 18.28.31 | 18.29.30 | 18.28.30 | 18.29.29 | 18.28.29 | 18.29.28 | 18.28.28 | 18.29.27 | 18.28.27 | 18.29.26 | 18.28.26 | 18.29.25 | 18.28.25 | 18.29.24 | 18.28.24 |
| GTX1:DRP44 | 18.29.39 | 18.28.39 | 18.29.38 | 18.28.38 | 18.29.37 | 18.28.37 | 18.29.36 | 18.28.36 | 18.29.35 | 18.28.35 | 18.29.34 | 18.28.34 | 18.29.33 | 18.28.33 | 18.29.32 | 18.28.32 |
| GTX1:DRP45 | 18.29.47 | 18.28.47 | 18.29.46 | 18.28.46 | 18.29.45 | 18.28.45 | 18.29.44 | 18.28.44 | 18.29.43 | 18.28.43 | 18.29.42 | 18.28.42 | 18.29.41 | 18.28.41 | 18.29.40 | 18.28.40 |
| GTX1:DRP46 | 18.29.55 | 18.28.55 | 18.29.54 | 18.28.54 | 18.29.53 | 18.28.53 | 18.29.52 | 18.28.52 | 18.29.51 | 18.28.51 | 18.29.50 | 18.28.50 | 18.29.49 | 18.28.49 | 18.29.48 | 18.28.48 |
| GTX1:DRP47 | 18.29.63 | 18.28.63 | 18.29.62 | 18.28.62 | 18.29.61 | 18.28.61 | 18.29.60 | 18.28.60 | 18.29.59 | 18.28.59 | 18.29.58 | 18.28.58 | 18.29.57 | 18.28.57 | 18.29.56 | 18.28.56 |
| GTX1:DRP48 | 19.29.7 | 19.28.7 | 19.29.6 | 19.28.6 | 19.29.5 | 19.28.5 | 19.29.4 | 19.28.4 | 19.29.3 | 19.28.3 | 19.29.2 | 19.28.2 | 19.29.1 | 19.28.1 | 19.29.0 | 19.28.0 |
| GTX1:DRP49 | 19.29.15 | 19.28.15 | 19.29.14 | 19.28.14 | 19.29.13 | 19.28.13 | 19.29.12 | 19.28.12 | 19.29.11 | 19.28.11 | 19.29.10 | 19.28.10 | 19.29.9 | 19.28.9 | 19.29.8 | 19.28.8 |
| GTX1:DRP4A | 19.29.23 | 19.28.23 | 19.29.22 | 19.28.22 | 19.29.21 | 19.28.21 | 19.29.20 | 19.28.20 | 19.29.19 | 19.28.19 | 19.29.18 | 19.28.18 | 19.29.17 | 19.28.17 | 19.29.16 | 19.28.16 |
| GTX1:DRP4B | 19.29.31 | 19.28.31 | 19.29.30 | 19.28.30 | 19.29.29 | 19.28.29 | 19.29.28 | 19.28.28 | 19.29.27 | 19.28.27 | 19.29.26 | 19.28.26 | 19.29.25 | 19.28.25 | 19.29.24 | 19.28.24 |
| GTX1:DRP4C | 19.29.39 | 19.28.39 | 19.29.38 | 19.28.38 | 19.29.37 | 19.28.37 | 19.29.36 | 19.28.36 | 19.29.35 | 19.28.35 | 19.29.34 | 19.28.34 | 19.29.33 | 19.28.33 | 19.29.32 | 19.28.32 |
| GTX1:DRP4D | 19.29.47 | 19.28.47 | 19.29.46 | 19.28.46 | 19.29.45 | 19.28.45 | 19.29.44 | 19.28.44 | 19.29.43 | 19.28.43 | 19.29.42 | 19.28.42 | 19.29.41 | 19.28.41 | 19.29.40 | 19.28.40 |
| GTX1:DRP4E | 19.29.55 | 19.28.55 | 19.29.54 | 19.28.54 | 19.29.53 | 19.28.53 | 19.29.52 | 19.28.52 | 19.29.51 | 19.28.51 | 19.29.50 | 19.28.50 | 19.29.49 | 19.28.49 | 19.29.48 | 19.28.48 |
| GTX1:DRP4F | 19.29.63 | 19.28.63 | 19.29.62 | 19.28.62 | 19.29.61 | 19.28.61 | 19.29.60 | 19.28.60 | 19.29.59 | 19.28.59 | 19.29.58 | 19.28.58 | 19.29.57 | 19.28.57 | 19.29.56 | 19.28.56 |
| GTX1:RXUSRCLK_DLY | 10.29.23 | 10.28.23 | 10.29.22 | 10.28.22 | 10.29.21 | 10.28.21 | 10.29.20 | 10.28.20 | 10.29.19 | 10.28.19 | 10.29.18 | 10.28.18 | 10.29.17 | 10.28.17 | 10.29.16 | 10.28.16 |
| GTX2:DRP00 | 20.29.7 | 20.28.7 | 20.29.6 | 20.28.6 | 20.29.5 | 20.28.5 | 20.29.4 | 20.28.4 | 20.29.3 | 20.28.3 | 20.29.2 | 20.28.2 | 20.29.1 | 20.28.1 | 20.29.0 | 20.28.0 |
| GTX2:DRP01 | 20.29.15 | 20.28.15 | 20.29.14 | 20.28.14 | 20.29.13 | 20.28.13 | 20.29.12 | 20.28.12 | 20.29.11 | 20.28.11 | 20.29.10 | 20.28.10 | 20.29.9 | 20.28.9 | 20.29.8 | 20.28.8 |
| GTX2:DRP02 | 20.29.23 | 20.28.23 | 20.29.22 | 20.28.22 | 20.29.21 | 20.28.21 | 20.29.20 | 20.28.20 | 20.29.19 | 20.28.19 | 20.29.18 | 20.28.18 | 20.29.17 | 20.28.17 | 20.29.16 | 20.28.16 |
| GTX2:DRP03 | 20.29.31 | 20.28.31 | 20.29.30 | 20.28.30 | 20.29.29 | 20.28.29 | 20.29.28 | 20.28.28 | 20.29.27 | 20.28.27 | 20.29.26 | 20.28.26 | 20.29.25 | 20.28.25 | 20.29.24 | 20.28.24 |
| GTX2:DRP04 | 20.29.39 | 20.28.39 | 20.29.38 | 20.28.38 | 20.29.37 | 20.28.37 | 20.29.36 | 20.28.36 | 20.29.35 | 20.28.35 | 20.29.34 | 20.28.34 | 20.29.33 | 20.28.33 | 20.29.32 | 20.28.32 |
| GTX2:DRP05 | 20.29.47 | 20.28.47 | 20.29.46 | 20.28.46 | 20.29.45 | 20.28.45 | 20.29.44 | 20.28.44 | 20.29.43 | 20.28.43 | 20.29.42 | 20.28.42 | 20.29.41 | 20.28.41 | 20.29.40 | 20.28.40 |
| GTX2:DRP06 | 20.29.55 | 20.28.55 | 20.29.54 | 20.28.54 | 20.29.53 | 20.28.53 | 20.29.52 | 20.28.52 | 20.29.51 | 20.28.51 | 20.29.50 | 20.28.50 | 20.29.49 | 20.28.49 | 20.29.48 | 20.28.48 |
| GTX2:DRP07 | 20.29.63 | 20.28.63 | 20.29.62 | 20.28.62 | 20.29.61 | 20.28.61 | 20.29.60 | 20.28.60 | 20.29.59 | 20.28.59 | 20.29.58 | 20.28.58 | 20.29.57 | 20.28.57 | 20.29.56 | 20.28.56 |
| GTX2:DRP08 | 21.29.7 | 21.28.7 | 21.29.6 | 21.28.6 | 21.29.5 | 21.28.5 | 21.29.4 | 21.28.4 | 21.29.3 | 21.28.3 | 21.29.2 | 21.28.2 | 21.29.1 | 21.28.1 | 21.29.0 | 21.28.0 |
| GTX2:DRP09 | 21.29.15 | 21.28.15 | 21.29.14 | 21.28.14 | 21.29.13 | 21.28.13 | 21.29.12 | 21.28.12 | 21.29.11 | 21.28.11 | 21.29.10 | 21.28.10 | 21.29.9 | 21.28.9 | 21.29.8 | 21.28.8 |
| GTX2:DRP0A | 21.29.23 | 21.28.23 | 21.29.22 | 21.28.22 | 21.29.21 | 21.28.21 | 21.29.20 | 21.28.20 | 21.29.19 | 21.28.19 | 21.29.18 | 21.28.18 | 21.29.17 | 21.28.17 | 21.29.16 | 21.28.16 |
| GTX2:DRP0B | 21.29.31 | 21.28.31 | 21.29.30 | 21.28.30 | 21.29.29 | 21.28.29 | 21.29.28 | 21.28.28 | 21.29.27 | 21.28.27 | 21.29.26 | 21.28.26 | 21.29.25 | 21.28.25 | 21.29.24 | 21.28.24 |
| GTX2:DRP0C | 21.29.39 | 21.28.39 | 21.29.38 | 21.28.38 | 21.29.37 | 21.28.37 | 21.29.36 | 21.28.36 | 21.29.35 | 21.28.35 | 21.29.34 | 21.28.34 | 21.29.33 | 21.28.33 | 21.29.32 | 21.28.32 |
| GTX2:DRP0D | 21.29.47 | 21.28.47 | 21.29.46 | 21.28.46 | 21.29.45 | 21.28.45 | 21.29.44 | 21.28.44 | 21.29.43 | 21.28.43 | 21.29.42 | 21.28.42 | 21.29.41 | 21.28.41 | 21.29.40 | 21.28.40 |
| GTX2:DRP0E | 21.29.55 | 21.28.55 | 21.29.54 | 21.28.54 | 21.29.53 | 21.28.53 | 21.29.52 | 21.28.52 | 21.29.51 | 21.28.51 | 21.29.50 | 21.28.50 | 21.29.49 | 21.28.49 | 21.29.48 | 21.28.48 |
| GTX2:DRP0F | 21.29.63 | 21.28.63 | 21.29.62 | 21.28.62 | 21.29.61 | 21.28.61 | 21.29.60 | 21.28.60 | 21.29.59 | 21.28.59 | 21.29.58 | 21.28.58 | 21.29.57 | 21.28.57 | 21.29.56 | 21.28.56 |
| GTX2:DRP10 | 22.29.7 | 22.28.7 | 22.29.6 | 22.28.6 | 22.29.5 | 22.28.5 | 22.29.4 | 22.28.4 | 22.29.3 | 22.28.3 | 22.29.2 | 22.28.2 | 22.29.1 | 22.28.1 | 22.29.0 | 22.28.0 |
| GTX2:DRP11 | 22.29.15 | 22.28.15 | 22.29.14 | 22.28.14 | 22.29.13 | 22.28.13 | 22.29.12 | 22.28.12 | 22.29.11 | 22.28.11 | 22.29.10 | 22.28.10 | 22.29.9 | 22.28.9 | 22.29.8 | 22.28.8 |
| GTX2:DRP12 | 22.29.23 | 22.28.23 | 22.29.22 | 22.28.22 | 22.29.21 | 22.28.21 | 22.29.20 | 22.28.20 | 22.29.19 | 22.28.19 | 22.29.18 | 22.28.18 | 22.29.17 | 22.28.17 | 22.29.16 | 22.28.16 |
| GTX2:DRP13 | 22.29.31 | 22.28.31 | 22.29.30 | 22.28.30 | 22.29.29 | 22.28.29 | 22.29.28 | 22.28.28 | 22.29.27 | 22.28.27 | 22.29.26 | 22.28.26 | 22.29.25 | 22.28.25 | 22.29.24 | 22.28.24 |
| GTX2:DRP14 | 22.29.39 | 22.28.39 | 22.29.38 | 22.28.38 | 22.29.37 | 22.28.37 | 22.29.36 | 22.28.36 | 22.29.35 | 22.28.35 | 22.29.34 | 22.28.34 | 22.29.33 | 22.28.33 | 22.29.32 | 22.28.32 |
| GTX2:DRP15 | 22.29.47 | 22.28.47 | 22.29.46 | 22.28.46 | 22.29.45 | 22.28.45 | 22.29.44 | 22.28.44 | 22.29.43 | 22.28.43 | 22.29.42 | 22.28.42 | 22.29.41 | 22.28.41 | 22.29.40 | 22.28.40 |
| GTX2:DRP16 | 22.29.55 | 22.28.55 | 22.29.54 | 22.28.54 | 22.29.53 | 22.28.53 | 22.29.52 | 22.28.52 | 22.29.51 | 22.28.51 | 22.29.50 | 22.28.50 | 22.29.49 | 22.28.49 | 22.29.48 | 22.28.48 |
| GTX2:DRP17 | 22.29.63 | 22.28.63 | 22.29.62 | 22.28.62 | 22.29.61 | 22.28.61 | 22.29.60 | 22.28.60 | 22.29.59 | 22.28.59 | 22.29.58 | 22.28.58 | 22.29.57 | 22.28.57 | 22.29.56 | 22.28.56 |
| GTX2:DRP18 | 23.29.7 | 23.28.7 | 23.29.6 | 23.28.6 | 23.29.5 | 23.28.5 | 23.29.4 | 23.28.4 | 23.29.3 | 23.28.3 | 23.29.2 | 23.28.2 | 23.29.1 | 23.28.1 | 23.29.0 | 23.28.0 |
| GTX2:DRP19 | 23.29.15 | 23.28.15 | 23.29.14 | 23.28.14 | 23.29.13 | 23.28.13 | 23.29.12 | 23.28.12 | 23.29.11 | 23.28.11 | 23.29.10 | 23.28.10 | 23.29.9 | 23.28.9 | 23.29.8 | 23.28.8 |
| GTX2:DRP1A | 23.29.23 | 23.28.23 | 23.29.22 | 23.28.22 | 23.29.21 | 23.28.21 | 23.29.20 | 23.28.20 | 23.29.19 | 23.28.19 | 23.29.18 | 23.28.18 | 23.29.17 | 23.28.17 | 23.29.16 | 23.28.16 |
| GTX2:DRP1B | 23.29.31 | 23.28.31 | 23.29.30 | 23.28.30 | 23.29.29 | 23.28.29 | 23.29.28 | 23.28.28 | 23.29.27 | 23.28.27 | 23.29.26 | 23.28.26 | 23.29.25 | 23.28.25 | 23.29.24 | 23.28.24 |
| GTX2:DRP1C | 23.29.39 | 23.28.39 | 23.29.38 | 23.28.38 | 23.29.37 | 23.28.37 | 23.29.36 | 23.28.36 | 23.29.35 | 23.28.35 | 23.29.34 | 23.28.34 | 23.29.33 | 23.28.33 | 23.29.32 | 23.28.32 |
| GTX2:DRP1D | 23.29.47 | 23.28.47 | 23.29.46 | 23.28.46 | 23.29.45 | 23.28.45 | 23.29.44 | 23.28.44 | 23.29.43 | 23.28.43 | 23.29.42 | 23.28.42 | 23.29.41 | 23.28.41 | 23.29.40 | 23.28.40 |
| GTX2:DRP1E | 23.29.55 | 23.28.55 | 23.29.54 | 23.28.54 | 23.29.53 | 23.28.53 | 23.29.52 | 23.28.52 | 23.29.51 | 23.28.51 | 23.29.50 | 23.28.50 | 23.29.49 | 23.28.49 | 23.29.48 | 23.28.48 |
| GTX2:DRP1F | 23.29.63 | 23.28.63 | 23.29.62 | 23.28.62 | 23.29.61 | 23.28.61 | 23.29.60 | 23.28.60 | 23.29.59 | 23.28.59 | 23.29.58 | 23.28.58 | 23.29.57 | 23.28.57 | 23.29.56 | 23.28.56 |
| GTX2:DRP20 | 24.29.7 | 24.28.7 | 24.29.6 | 24.28.6 | 24.29.5 | 24.28.5 | 24.29.4 | 24.28.4 | 24.29.3 | 24.28.3 | 24.29.2 | 24.28.2 | 24.29.1 | 24.28.1 | 24.29.0 | 24.28.0 |
| GTX2:DRP21 | 24.29.15 | 24.28.15 | 24.29.14 | 24.28.14 | 24.29.13 | 24.28.13 | 24.29.12 | 24.28.12 | 24.29.11 | 24.28.11 | 24.29.10 | 24.28.10 | 24.29.9 | 24.28.9 | 24.29.8 | 24.28.8 |
| GTX2:DRP22 | 24.29.23 | 24.28.23 | 24.29.22 | 24.28.22 | 24.29.21 | 24.28.21 | 24.29.20 | 24.28.20 | 24.29.19 | 24.28.19 | 24.29.18 | 24.28.18 | 24.29.17 | 24.28.17 | 24.29.16 | 24.28.16 |
| GTX2:DRP23 | 24.29.31 | 24.28.31 | 24.29.30 | 24.28.30 | 24.29.29 | 24.28.29 | 24.29.28 | 24.28.28 | 24.29.27 | 24.28.27 | 24.29.26 | 24.28.26 | 24.29.25 | 24.28.25 | 24.29.24 | 24.28.24 |
| GTX2:DRP24 | 24.29.39 | 24.28.39 | 24.29.38 | 24.28.38 | 24.29.37 | 24.28.37 | 24.29.36 | 24.28.36 | 24.29.35 | 24.28.35 | 24.29.34 | 24.28.34 | 24.29.33 | 24.28.33 | 24.29.32 | 24.28.32 |
| GTX2:DRP25 | 24.29.47 | 24.28.47 | 24.29.46 | 24.28.46 | 24.29.45 | 24.28.45 | 24.29.44 | 24.28.44 | 24.29.43 | 24.28.43 | 24.29.42 | 24.28.42 | 24.29.41 | 24.28.41 | 24.29.40 | 24.28.40 |
| GTX2:DRP26 | 24.29.55 | 24.28.55 | 24.29.54 | 24.28.54 | 24.29.53 | 24.28.53 | 24.29.52 | 24.28.52 | 24.29.51 | 24.28.51 | 24.29.50 | 24.28.50 | 24.29.49 | 24.28.49 | 24.29.48 | 24.28.48 |
| GTX2:DRP27 | 24.29.63 | 24.28.63 | 24.29.62 | 24.28.62 | 24.29.61 | 24.28.61 | 24.29.60 | 24.28.60 | 24.29.59 | 24.28.59 | 24.29.58 | 24.28.58 | 24.29.57 | 24.28.57 | 24.29.56 | 24.28.56 |
| GTX2:DRP28 | 25.29.7 | 25.28.7 | 25.29.6 | 25.28.6 | 25.29.5 | 25.28.5 | 25.29.4 | 25.28.4 | 25.29.3 | 25.28.3 | 25.29.2 | 25.28.2 | 25.29.1 | 25.28.1 | 25.29.0 | 25.28.0 |
| GTX2:DRP29 | 25.29.15 | 25.28.15 | 25.29.14 | 25.28.14 | 25.29.13 | 25.28.13 | 25.29.12 | 25.28.12 | 25.29.11 | 25.28.11 | 25.29.10 | 25.28.10 | 25.29.9 | 25.28.9 | 25.29.8 | 25.28.8 |
| GTX2:DRP2A | 25.29.23 | 25.28.23 | 25.29.22 | 25.28.22 | 25.29.21 | 25.28.21 | 25.29.20 | 25.28.20 | 25.29.19 | 25.28.19 | 25.29.18 | 25.28.18 | 25.29.17 | 25.28.17 | 25.29.16 | 25.28.16 |
| GTX2:DRP2B | 25.29.31 | 25.28.31 | 25.29.30 | 25.28.30 | 25.29.29 | 25.28.29 | 25.29.28 | 25.28.28 | 25.29.27 | 25.28.27 | 25.29.26 | 25.28.26 | 25.29.25 | 25.28.25 | 25.29.24 | 25.28.24 |
| GTX2:DRP2C | 25.29.39 | 25.28.39 | 25.29.38 | 25.28.38 | 25.29.37 | 25.28.37 | 25.29.36 | 25.28.36 | 25.29.35 | 25.28.35 | 25.29.34 | 25.28.34 | 25.29.33 | 25.28.33 | 25.29.32 | 25.28.32 |
| GTX2:DRP2D | 25.29.47 | 25.28.47 | 25.29.46 | 25.28.46 | 25.29.45 | 25.28.45 | 25.29.44 | 25.28.44 | 25.29.43 | 25.28.43 | 25.29.42 | 25.28.42 | 25.29.41 | 25.28.41 | 25.29.40 | 25.28.40 |
| GTX2:DRP2E | 25.29.55 | 25.28.55 | 25.29.54 | 25.28.54 | 25.29.53 | 25.28.53 | 25.29.52 | 25.28.52 | 25.29.51 | 25.28.51 | 25.29.50 | 25.28.50 | 25.29.49 | 25.28.49 | 25.29.48 | 25.28.48 |
| GTX2:DRP2F | 25.29.63 | 25.28.63 | 25.29.62 | 25.28.62 | 25.29.61 | 25.28.61 | 25.29.60 | 25.28.60 | 25.29.59 | 25.28.59 | 25.29.58 | 25.28.58 | 25.29.57 | 25.28.57 | 25.29.56 | 25.28.56 |
| GTX2:DRP30 | 26.29.7 | 26.28.7 | 26.29.6 | 26.28.6 | 26.29.5 | 26.28.5 | 26.29.4 | 26.28.4 | 26.29.3 | 26.28.3 | 26.29.2 | 26.28.2 | 26.29.1 | 26.28.1 | 26.29.0 | 26.28.0 |
| GTX2:DRP31 | 26.29.15 | 26.28.15 | 26.29.14 | 26.28.14 | 26.29.13 | 26.28.13 | 26.29.12 | 26.28.12 | 26.29.11 | 26.28.11 | 26.29.10 | 26.28.10 | 26.29.9 | 26.28.9 | 26.29.8 | 26.28.8 |
| GTX2:DRP32 | 26.29.23 | 26.28.23 | 26.29.22 | 26.28.22 | 26.29.21 | 26.28.21 | 26.29.20 | 26.28.20 | 26.29.19 | 26.28.19 | 26.29.18 | 26.28.18 | 26.29.17 | 26.28.17 | 26.29.16 | 26.28.16 |
| GTX2:DRP33 | 26.29.31 | 26.28.31 | 26.29.30 | 26.28.30 | 26.29.29 | 26.28.29 | 26.29.28 | 26.28.28 | 26.29.27 | 26.28.27 | 26.29.26 | 26.28.26 | 26.29.25 | 26.28.25 | 26.29.24 | 26.28.24 |
| GTX2:DRP34 | 26.29.39 | 26.28.39 | 26.29.38 | 26.28.38 | 26.29.37 | 26.28.37 | 26.29.36 | 26.28.36 | 26.29.35 | 26.28.35 | 26.29.34 | 26.28.34 | 26.29.33 | 26.28.33 | 26.29.32 | 26.28.32 |
| GTX2:DRP35 | 26.29.47 | 26.28.47 | 26.29.46 | 26.28.46 | 26.29.45 | 26.28.45 | 26.29.44 | 26.28.44 | 26.29.43 | 26.28.43 | 26.29.42 | 26.28.42 | 26.29.41 | 26.28.41 | 26.29.40 | 26.28.40 |
| GTX2:DRP36 | 26.29.55 | 26.28.55 | 26.29.54 | 26.28.54 | 26.29.53 | 26.28.53 | 26.29.52 | 26.28.52 | 26.29.51 | 26.28.51 | 26.29.50 | 26.28.50 | 26.29.49 | 26.28.49 | 26.29.48 | 26.28.48 |
| GTX2:DRP37 | 26.29.63 | 26.28.63 | 26.29.62 | 26.28.62 | 26.29.61 | 26.28.61 | 26.29.60 | 26.28.60 | 26.29.59 | 26.28.59 | 26.29.58 | 26.28.58 | 26.29.57 | 26.28.57 | 26.29.56 | 26.28.56 |
| GTX2:DRP38 | 27.29.7 | 27.28.7 | 27.29.6 | 27.28.6 | 27.29.5 | 27.28.5 | 27.29.4 | 27.28.4 | 27.29.3 | 27.28.3 | 27.29.2 | 27.28.2 | 27.29.1 | 27.28.1 | 27.29.0 | 27.28.0 |
| GTX2:DRP39 | 27.29.15 | 27.28.15 | 27.29.14 | 27.28.14 | 27.29.13 | 27.28.13 | 27.29.12 | 27.28.12 | 27.29.11 | 27.28.11 | 27.29.10 | 27.28.10 | 27.29.9 | 27.28.9 | 27.29.8 | 27.28.8 |
| GTX2:DRP3A | 27.29.23 | 27.28.23 | 27.29.22 | 27.28.22 | 27.29.21 | 27.28.21 | 27.29.20 | 27.28.20 | 27.29.19 | 27.28.19 | 27.29.18 | 27.28.18 | 27.29.17 | 27.28.17 | 27.29.16 | 27.28.16 |
| GTX2:DRP3B | 27.29.31 | 27.28.31 | 27.29.30 | 27.28.30 | 27.29.29 | 27.28.29 | 27.29.28 | 27.28.28 | 27.29.27 | 27.28.27 | 27.29.26 | 27.28.26 | 27.29.25 | 27.28.25 | 27.29.24 | 27.28.24 |
| GTX2:DRP3C | 27.29.39 | 27.28.39 | 27.29.38 | 27.28.38 | 27.29.37 | 27.28.37 | 27.29.36 | 27.28.36 | 27.29.35 | 27.28.35 | 27.29.34 | 27.28.34 | 27.29.33 | 27.28.33 | 27.29.32 | 27.28.32 |
| GTX2:DRP3D | 27.29.47 | 27.28.47 | 27.29.46 | 27.28.46 | 27.29.45 | 27.28.45 | 27.29.44 | 27.28.44 | 27.29.43 | 27.28.43 | 27.29.42 | 27.28.42 | 27.29.41 | 27.28.41 | 27.29.40 | 27.28.40 |
| GTX2:DRP3E | 27.29.55 | 27.28.55 | 27.29.54 | 27.28.54 | 27.29.53 | 27.28.53 | 27.29.52 | 27.28.52 | 27.29.51 | 27.28.51 | 27.29.50 | 27.28.50 | 27.29.49 | 27.28.49 | 27.29.48 | 27.28.48 |
| GTX2:DRP3F | 27.29.63 | 27.28.63 | 27.29.62 | 27.28.62 | 27.29.61 | 27.28.61 | 27.29.60 | 27.28.60 | 27.29.59 | 27.28.59 | 27.29.58 | 27.28.58 | 27.29.57 | 27.28.57 | 27.29.56 | 27.28.56 |
| GTX2:DRP40 | 28.29.7 | 28.28.7 | 28.29.6 | 28.28.6 | 28.29.5 | 28.28.5 | 28.29.4 | 28.28.4 | 28.29.3 | 28.28.3 | 28.29.2 | 28.28.2 | 28.29.1 | 28.28.1 | 28.29.0 | 28.28.0 |
| GTX2:DRP41 | 28.29.15 | 28.28.15 | 28.29.14 | 28.28.14 | 28.29.13 | 28.28.13 | 28.29.12 | 28.28.12 | 28.29.11 | 28.28.11 | 28.29.10 | 28.28.10 | 28.29.9 | 28.28.9 | 28.29.8 | 28.28.8 |
| GTX2:DRP42 | 28.29.23 | 28.28.23 | 28.29.22 | 28.28.22 | 28.29.21 | 28.28.21 | 28.29.20 | 28.28.20 | 28.29.19 | 28.28.19 | 28.29.18 | 28.28.18 | 28.29.17 | 28.28.17 | 28.29.16 | 28.28.16 |
| GTX2:DRP43 | 28.29.31 | 28.28.31 | 28.29.30 | 28.28.30 | 28.29.29 | 28.28.29 | 28.29.28 | 28.28.28 | 28.29.27 | 28.28.27 | 28.29.26 | 28.28.26 | 28.29.25 | 28.28.25 | 28.29.24 | 28.28.24 |
| GTX2:DRP44 | 28.29.39 | 28.28.39 | 28.29.38 | 28.28.38 | 28.29.37 | 28.28.37 | 28.29.36 | 28.28.36 | 28.29.35 | 28.28.35 | 28.29.34 | 28.28.34 | 28.29.33 | 28.28.33 | 28.29.32 | 28.28.32 |
| GTX2:DRP45 | 28.29.47 | 28.28.47 | 28.29.46 | 28.28.46 | 28.29.45 | 28.28.45 | 28.29.44 | 28.28.44 | 28.29.43 | 28.28.43 | 28.29.42 | 28.28.42 | 28.29.41 | 28.28.41 | 28.29.40 | 28.28.40 |
| GTX2:DRP46 | 28.29.55 | 28.28.55 | 28.29.54 | 28.28.54 | 28.29.53 | 28.28.53 | 28.29.52 | 28.28.52 | 28.29.51 | 28.28.51 | 28.29.50 | 28.28.50 | 28.29.49 | 28.28.49 | 28.29.48 | 28.28.48 |
| GTX2:DRP47 | 28.29.63 | 28.28.63 | 28.29.62 | 28.28.62 | 28.29.61 | 28.28.61 | 28.29.60 | 28.28.60 | 28.29.59 | 28.28.59 | 28.29.58 | 28.28.58 | 28.29.57 | 28.28.57 | 28.29.56 | 28.28.56 |
| GTX2:DRP48 | 29.29.7 | 29.28.7 | 29.29.6 | 29.28.6 | 29.29.5 | 29.28.5 | 29.29.4 | 29.28.4 | 29.29.3 | 29.28.3 | 29.29.2 | 29.28.2 | 29.29.1 | 29.28.1 | 29.29.0 | 29.28.0 |
| GTX2:DRP49 | 29.29.15 | 29.28.15 | 29.29.14 | 29.28.14 | 29.29.13 | 29.28.13 | 29.29.12 | 29.28.12 | 29.29.11 | 29.28.11 | 29.29.10 | 29.28.10 | 29.29.9 | 29.28.9 | 29.29.8 | 29.28.8 |
| GTX2:DRP4A | 29.29.23 | 29.28.23 | 29.29.22 | 29.28.22 | 29.29.21 | 29.28.21 | 29.29.20 | 29.28.20 | 29.29.19 | 29.28.19 | 29.29.18 | 29.28.18 | 29.29.17 | 29.28.17 | 29.29.16 | 29.28.16 |
| GTX2:DRP4B | 29.29.31 | 29.28.31 | 29.29.30 | 29.28.30 | 29.29.29 | 29.28.29 | 29.29.28 | 29.28.28 | 29.29.27 | 29.28.27 | 29.29.26 | 29.28.26 | 29.29.25 | 29.28.25 | 29.29.24 | 29.28.24 |
| GTX2:DRP4C | 29.29.39 | 29.28.39 | 29.29.38 | 29.28.38 | 29.29.37 | 29.28.37 | 29.29.36 | 29.28.36 | 29.29.35 | 29.28.35 | 29.29.34 | 29.28.34 | 29.29.33 | 29.28.33 | 29.29.32 | 29.28.32 |
| GTX2:DRP4D | 29.29.47 | 29.28.47 | 29.29.46 | 29.28.46 | 29.29.45 | 29.28.45 | 29.29.44 | 29.28.44 | 29.29.43 | 29.28.43 | 29.29.42 | 29.28.42 | 29.29.41 | 29.28.41 | 29.29.40 | 29.28.40 |
| GTX2:DRP4E | 29.29.55 | 29.28.55 | 29.29.54 | 29.28.54 | 29.29.53 | 29.28.53 | 29.29.52 | 29.28.52 | 29.29.51 | 29.28.51 | 29.29.50 | 29.28.50 | 29.29.49 | 29.28.49 | 29.29.48 | 29.28.48 |
| GTX2:DRP4F | 29.29.63 | 29.28.63 | 29.29.62 | 29.28.62 | 29.29.61 | 29.28.61 | 29.29.60 | 29.28.60 | 29.29.59 | 29.28.59 | 29.29.58 | 29.28.58 | 29.29.57 | 29.28.57 | 29.29.56 | 29.28.56 |
| GTX2:RXUSRCLK_DLY | 20.29.23 | 20.28.23 | 20.29.22 | 20.28.22 | 20.29.21 | 20.28.21 | 20.29.20 | 20.28.20 | 20.29.19 | 20.28.19 | 20.29.18 | 20.28.18 | 20.29.17 | 20.28.17 | 20.29.16 | 20.28.16 |
| GTX3:DRP00 | 30.29.7 | 30.28.7 | 30.29.6 | 30.28.6 | 30.29.5 | 30.28.5 | 30.29.4 | 30.28.4 | 30.29.3 | 30.28.3 | 30.29.2 | 30.28.2 | 30.29.1 | 30.28.1 | 30.29.0 | 30.28.0 |
| GTX3:DRP01 | 30.29.15 | 30.28.15 | 30.29.14 | 30.28.14 | 30.29.13 | 30.28.13 | 30.29.12 | 30.28.12 | 30.29.11 | 30.28.11 | 30.29.10 | 30.28.10 | 30.29.9 | 30.28.9 | 30.29.8 | 30.28.8 |
| GTX3:DRP02 | 30.29.23 | 30.28.23 | 30.29.22 | 30.28.22 | 30.29.21 | 30.28.21 | 30.29.20 | 30.28.20 | 30.29.19 | 30.28.19 | 30.29.18 | 30.28.18 | 30.29.17 | 30.28.17 | 30.29.16 | 30.28.16 |
| GTX3:DRP03 | 30.29.31 | 30.28.31 | 30.29.30 | 30.28.30 | 30.29.29 | 30.28.29 | 30.29.28 | 30.28.28 | 30.29.27 | 30.28.27 | 30.29.26 | 30.28.26 | 30.29.25 | 30.28.25 | 30.29.24 | 30.28.24 |
| GTX3:DRP04 | 30.29.39 | 30.28.39 | 30.29.38 | 30.28.38 | 30.29.37 | 30.28.37 | 30.29.36 | 30.28.36 | 30.29.35 | 30.28.35 | 30.29.34 | 30.28.34 | 30.29.33 | 30.28.33 | 30.29.32 | 30.28.32 |
| GTX3:DRP05 | 30.29.47 | 30.28.47 | 30.29.46 | 30.28.46 | 30.29.45 | 30.28.45 | 30.29.44 | 30.28.44 | 30.29.43 | 30.28.43 | 30.29.42 | 30.28.42 | 30.29.41 | 30.28.41 | 30.29.40 | 30.28.40 |
| GTX3:DRP06 | 30.29.55 | 30.28.55 | 30.29.54 | 30.28.54 | 30.29.53 | 30.28.53 | 30.29.52 | 30.28.52 | 30.29.51 | 30.28.51 | 30.29.50 | 30.28.50 | 30.29.49 | 30.28.49 | 30.29.48 | 30.28.48 |
| GTX3:DRP07 | 30.29.63 | 30.28.63 | 30.29.62 | 30.28.62 | 30.29.61 | 30.28.61 | 30.29.60 | 30.28.60 | 30.29.59 | 30.28.59 | 30.29.58 | 30.28.58 | 30.29.57 | 30.28.57 | 30.29.56 | 30.28.56 |
| GTX3:DRP08 | 31.29.7 | 31.28.7 | 31.29.6 | 31.28.6 | 31.29.5 | 31.28.5 | 31.29.4 | 31.28.4 | 31.29.3 | 31.28.3 | 31.29.2 | 31.28.2 | 31.29.1 | 31.28.1 | 31.29.0 | 31.28.0 |
| GTX3:DRP09 | 31.29.15 | 31.28.15 | 31.29.14 | 31.28.14 | 31.29.13 | 31.28.13 | 31.29.12 | 31.28.12 | 31.29.11 | 31.28.11 | 31.29.10 | 31.28.10 | 31.29.9 | 31.28.9 | 31.29.8 | 31.28.8 |
| GTX3:DRP0A | 31.29.23 | 31.28.23 | 31.29.22 | 31.28.22 | 31.29.21 | 31.28.21 | 31.29.20 | 31.28.20 | 31.29.19 | 31.28.19 | 31.29.18 | 31.28.18 | 31.29.17 | 31.28.17 | 31.29.16 | 31.28.16 |
| GTX3:DRP0B | 31.29.31 | 31.28.31 | 31.29.30 | 31.28.30 | 31.29.29 | 31.28.29 | 31.29.28 | 31.28.28 | 31.29.27 | 31.28.27 | 31.29.26 | 31.28.26 | 31.29.25 | 31.28.25 | 31.29.24 | 31.28.24 |
| GTX3:DRP0C | 31.29.39 | 31.28.39 | 31.29.38 | 31.28.38 | 31.29.37 | 31.28.37 | 31.29.36 | 31.28.36 | 31.29.35 | 31.28.35 | 31.29.34 | 31.28.34 | 31.29.33 | 31.28.33 | 31.29.32 | 31.28.32 |
| GTX3:DRP0D | 31.29.47 | 31.28.47 | 31.29.46 | 31.28.46 | 31.29.45 | 31.28.45 | 31.29.44 | 31.28.44 | 31.29.43 | 31.28.43 | 31.29.42 | 31.28.42 | 31.29.41 | 31.28.41 | 31.29.40 | 31.28.40 |
| GTX3:DRP0E | 31.29.55 | 31.28.55 | 31.29.54 | 31.28.54 | 31.29.53 | 31.28.53 | 31.29.52 | 31.28.52 | 31.29.51 | 31.28.51 | 31.29.50 | 31.28.50 | 31.29.49 | 31.28.49 | 31.29.48 | 31.28.48 |
| GTX3:DRP0F | 31.29.63 | 31.28.63 | 31.29.62 | 31.28.62 | 31.29.61 | 31.28.61 | 31.29.60 | 31.28.60 | 31.29.59 | 31.28.59 | 31.29.58 | 31.28.58 | 31.29.57 | 31.28.57 | 31.29.56 | 31.28.56 |
| GTX3:DRP10 | 32.29.7 | 32.28.7 | 32.29.6 | 32.28.6 | 32.29.5 | 32.28.5 | 32.29.4 | 32.28.4 | 32.29.3 | 32.28.3 | 32.29.2 | 32.28.2 | 32.29.1 | 32.28.1 | 32.29.0 | 32.28.0 |
| GTX3:DRP11 | 32.29.15 | 32.28.15 | 32.29.14 | 32.28.14 | 32.29.13 | 32.28.13 | 32.29.12 | 32.28.12 | 32.29.11 | 32.28.11 | 32.29.10 | 32.28.10 | 32.29.9 | 32.28.9 | 32.29.8 | 32.28.8 |
| GTX3:DRP12 | 32.29.23 | 32.28.23 | 32.29.22 | 32.28.22 | 32.29.21 | 32.28.21 | 32.29.20 | 32.28.20 | 32.29.19 | 32.28.19 | 32.29.18 | 32.28.18 | 32.29.17 | 32.28.17 | 32.29.16 | 32.28.16 |
| GTX3:DRP13 | 32.29.31 | 32.28.31 | 32.29.30 | 32.28.30 | 32.29.29 | 32.28.29 | 32.29.28 | 32.28.28 | 32.29.27 | 32.28.27 | 32.29.26 | 32.28.26 | 32.29.25 | 32.28.25 | 32.29.24 | 32.28.24 |
| GTX3:DRP14 | 32.29.39 | 32.28.39 | 32.29.38 | 32.28.38 | 32.29.37 | 32.28.37 | 32.29.36 | 32.28.36 | 32.29.35 | 32.28.35 | 32.29.34 | 32.28.34 | 32.29.33 | 32.28.33 | 32.29.32 | 32.28.32 |
| GTX3:DRP15 | 32.29.47 | 32.28.47 | 32.29.46 | 32.28.46 | 32.29.45 | 32.28.45 | 32.29.44 | 32.28.44 | 32.29.43 | 32.28.43 | 32.29.42 | 32.28.42 | 32.29.41 | 32.28.41 | 32.29.40 | 32.28.40 |
| GTX3:DRP16 | 32.29.55 | 32.28.55 | 32.29.54 | 32.28.54 | 32.29.53 | 32.28.53 | 32.29.52 | 32.28.52 | 32.29.51 | 32.28.51 | 32.29.50 | 32.28.50 | 32.29.49 | 32.28.49 | 32.29.48 | 32.28.48 |
| GTX3:DRP17 | 32.29.63 | 32.28.63 | 32.29.62 | 32.28.62 | 32.29.61 | 32.28.61 | 32.29.60 | 32.28.60 | 32.29.59 | 32.28.59 | 32.29.58 | 32.28.58 | 32.29.57 | 32.28.57 | 32.29.56 | 32.28.56 |
| GTX3:DRP18 | 33.29.7 | 33.28.7 | 33.29.6 | 33.28.6 | 33.29.5 | 33.28.5 | 33.29.4 | 33.28.4 | 33.29.3 | 33.28.3 | 33.29.2 | 33.28.2 | 33.29.1 | 33.28.1 | 33.29.0 | 33.28.0 |
| GTX3:DRP19 | 33.29.15 | 33.28.15 | 33.29.14 | 33.28.14 | 33.29.13 | 33.28.13 | 33.29.12 | 33.28.12 | 33.29.11 | 33.28.11 | 33.29.10 | 33.28.10 | 33.29.9 | 33.28.9 | 33.29.8 | 33.28.8 |
| GTX3:DRP1A | 33.29.23 | 33.28.23 | 33.29.22 | 33.28.22 | 33.29.21 | 33.28.21 | 33.29.20 | 33.28.20 | 33.29.19 | 33.28.19 | 33.29.18 | 33.28.18 | 33.29.17 | 33.28.17 | 33.29.16 | 33.28.16 |
| GTX3:DRP1B | 33.29.31 | 33.28.31 | 33.29.30 | 33.28.30 | 33.29.29 | 33.28.29 | 33.29.28 | 33.28.28 | 33.29.27 | 33.28.27 | 33.29.26 | 33.28.26 | 33.29.25 | 33.28.25 | 33.29.24 | 33.28.24 |
| GTX3:DRP1C | 33.29.39 | 33.28.39 | 33.29.38 | 33.28.38 | 33.29.37 | 33.28.37 | 33.29.36 | 33.28.36 | 33.29.35 | 33.28.35 | 33.29.34 | 33.28.34 | 33.29.33 | 33.28.33 | 33.29.32 | 33.28.32 |
| GTX3:DRP1D | 33.29.47 | 33.28.47 | 33.29.46 | 33.28.46 | 33.29.45 | 33.28.45 | 33.29.44 | 33.28.44 | 33.29.43 | 33.28.43 | 33.29.42 | 33.28.42 | 33.29.41 | 33.28.41 | 33.29.40 | 33.28.40 |
| GTX3:DRP1E | 33.29.55 | 33.28.55 | 33.29.54 | 33.28.54 | 33.29.53 | 33.28.53 | 33.29.52 | 33.28.52 | 33.29.51 | 33.28.51 | 33.29.50 | 33.28.50 | 33.29.49 | 33.28.49 | 33.29.48 | 33.28.48 |
| GTX3:DRP1F | 33.29.63 | 33.28.63 | 33.29.62 | 33.28.62 | 33.29.61 | 33.28.61 | 33.29.60 | 33.28.60 | 33.29.59 | 33.28.59 | 33.29.58 | 33.28.58 | 33.29.57 | 33.28.57 | 33.29.56 | 33.28.56 |
| GTX3:DRP20 | 34.29.7 | 34.28.7 | 34.29.6 | 34.28.6 | 34.29.5 | 34.28.5 | 34.29.4 | 34.28.4 | 34.29.3 | 34.28.3 | 34.29.2 | 34.28.2 | 34.29.1 | 34.28.1 | 34.29.0 | 34.28.0 |
| GTX3:DRP21 | 34.29.15 | 34.28.15 | 34.29.14 | 34.28.14 | 34.29.13 | 34.28.13 | 34.29.12 | 34.28.12 | 34.29.11 | 34.28.11 | 34.29.10 | 34.28.10 | 34.29.9 | 34.28.9 | 34.29.8 | 34.28.8 |
| GTX3:DRP22 | 34.29.23 | 34.28.23 | 34.29.22 | 34.28.22 | 34.29.21 | 34.28.21 | 34.29.20 | 34.28.20 | 34.29.19 | 34.28.19 | 34.29.18 | 34.28.18 | 34.29.17 | 34.28.17 | 34.29.16 | 34.28.16 |
| GTX3:DRP23 | 34.29.31 | 34.28.31 | 34.29.30 | 34.28.30 | 34.29.29 | 34.28.29 | 34.29.28 | 34.28.28 | 34.29.27 | 34.28.27 | 34.29.26 | 34.28.26 | 34.29.25 | 34.28.25 | 34.29.24 | 34.28.24 |
| GTX3:DRP24 | 34.29.39 | 34.28.39 | 34.29.38 | 34.28.38 | 34.29.37 | 34.28.37 | 34.29.36 | 34.28.36 | 34.29.35 | 34.28.35 | 34.29.34 | 34.28.34 | 34.29.33 | 34.28.33 | 34.29.32 | 34.28.32 |
| GTX3:DRP25 | 34.29.47 | 34.28.47 | 34.29.46 | 34.28.46 | 34.29.45 | 34.28.45 | 34.29.44 | 34.28.44 | 34.29.43 | 34.28.43 | 34.29.42 | 34.28.42 | 34.29.41 | 34.28.41 | 34.29.40 | 34.28.40 |
| GTX3:DRP26 | 34.29.55 | 34.28.55 | 34.29.54 | 34.28.54 | 34.29.53 | 34.28.53 | 34.29.52 | 34.28.52 | 34.29.51 | 34.28.51 | 34.29.50 | 34.28.50 | 34.29.49 | 34.28.49 | 34.29.48 | 34.28.48 |
| GTX3:DRP27 | 34.29.63 | 34.28.63 | 34.29.62 | 34.28.62 | 34.29.61 | 34.28.61 | 34.29.60 | 34.28.60 | 34.29.59 | 34.28.59 | 34.29.58 | 34.28.58 | 34.29.57 | 34.28.57 | 34.29.56 | 34.28.56 |
| GTX3:DRP28 | 35.29.7 | 35.28.7 | 35.29.6 | 35.28.6 | 35.29.5 | 35.28.5 | 35.29.4 | 35.28.4 | 35.29.3 | 35.28.3 | 35.29.2 | 35.28.2 | 35.29.1 | 35.28.1 | 35.29.0 | 35.28.0 |
| GTX3:DRP29 | 35.29.15 | 35.28.15 | 35.29.14 | 35.28.14 | 35.29.13 | 35.28.13 | 35.29.12 | 35.28.12 | 35.29.11 | 35.28.11 | 35.29.10 | 35.28.10 | 35.29.9 | 35.28.9 | 35.29.8 | 35.28.8 |
| GTX3:DRP2A | 35.29.23 | 35.28.23 | 35.29.22 | 35.28.22 | 35.29.21 | 35.28.21 | 35.29.20 | 35.28.20 | 35.29.19 | 35.28.19 | 35.29.18 | 35.28.18 | 35.29.17 | 35.28.17 | 35.29.16 | 35.28.16 |
| GTX3:DRP2B | 35.29.31 | 35.28.31 | 35.29.30 | 35.28.30 | 35.29.29 | 35.28.29 | 35.29.28 | 35.28.28 | 35.29.27 | 35.28.27 | 35.29.26 | 35.28.26 | 35.29.25 | 35.28.25 | 35.29.24 | 35.28.24 |
| GTX3:DRP2C | 35.29.39 | 35.28.39 | 35.29.38 | 35.28.38 | 35.29.37 | 35.28.37 | 35.29.36 | 35.28.36 | 35.29.35 | 35.28.35 | 35.29.34 | 35.28.34 | 35.29.33 | 35.28.33 | 35.29.32 | 35.28.32 |
| GTX3:DRP2D | 35.29.47 | 35.28.47 | 35.29.46 | 35.28.46 | 35.29.45 | 35.28.45 | 35.29.44 | 35.28.44 | 35.29.43 | 35.28.43 | 35.29.42 | 35.28.42 | 35.29.41 | 35.28.41 | 35.29.40 | 35.28.40 |
| GTX3:DRP2E | 35.29.55 | 35.28.55 | 35.29.54 | 35.28.54 | 35.29.53 | 35.28.53 | 35.29.52 | 35.28.52 | 35.29.51 | 35.28.51 | 35.29.50 | 35.28.50 | 35.29.49 | 35.28.49 | 35.29.48 | 35.28.48 |
| GTX3:DRP2F | 35.29.63 | 35.28.63 | 35.29.62 | 35.28.62 | 35.29.61 | 35.28.61 | 35.29.60 | 35.28.60 | 35.29.59 | 35.28.59 | 35.29.58 | 35.28.58 | 35.29.57 | 35.28.57 | 35.29.56 | 35.28.56 |
| GTX3:DRP30 | 36.29.7 | 36.28.7 | 36.29.6 | 36.28.6 | 36.29.5 | 36.28.5 | 36.29.4 | 36.28.4 | 36.29.3 | 36.28.3 | 36.29.2 | 36.28.2 | 36.29.1 | 36.28.1 | 36.29.0 | 36.28.0 |
| GTX3:DRP31 | 36.29.15 | 36.28.15 | 36.29.14 | 36.28.14 | 36.29.13 | 36.28.13 | 36.29.12 | 36.28.12 | 36.29.11 | 36.28.11 | 36.29.10 | 36.28.10 | 36.29.9 | 36.28.9 | 36.29.8 | 36.28.8 |
| GTX3:DRP32 | 36.29.23 | 36.28.23 | 36.29.22 | 36.28.22 | 36.29.21 | 36.28.21 | 36.29.20 | 36.28.20 | 36.29.19 | 36.28.19 | 36.29.18 | 36.28.18 | 36.29.17 | 36.28.17 | 36.29.16 | 36.28.16 |
| GTX3:DRP33 | 36.29.31 | 36.28.31 | 36.29.30 | 36.28.30 | 36.29.29 | 36.28.29 | 36.29.28 | 36.28.28 | 36.29.27 | 36.28.27 | 36.29.26 | 36.28.26 | 36.29.25 | 36.28.25 | 36.29.24 | 36.28.24 |
| GTX3:DRP34 | 36.29.39 | 36.28.39 | 36.29.38 | 36.28.38 | 36.29.37 | 36.28.37 | 36.29.36 | 36.28.36 | 36.29.35 | 36.28.35 | 36.29.34 | 36.28.34 | 36.29.33 | 36.28.33 | 36.29.32 | 36.28.32 |
| GTX3:DRP35 | 36.29.47 | 36.28.47 | 36.29.46 | 36.28.46 | 36.29.45 | 36.28.45 | 36.29.44 | 36.28.44 | 36.29.43 | 36.28.43 | 36.29.42 | 36.28.42 | 36.29.41 | 36.28.41 | 36.29.40 | 36.28.40 |
| GTX3:DRP36 | 36.29.55 | 36.28.55 | 36.29.54 | 36.28.54 | 36.29.53 | 36.28.53 | 36.29.52 | 36.28.52 | 36.29.51 | 36.28.51 | 36.29.50 | 36.28.50 | 36.29.49 | 36.28.49 | 36.29.48 | 36.28.48 |
| GTX3:DRP37 | 36.29.63 | 36.28.63 | 36.29.62 | 36.28.62 | 36.29.61 | 36.28.61 | 36.29.60 | 36.28.60 | 36.29.59 | 36.28.59 | 36.29.58 | 36.28.58 | 36.29.57 | 36.28.57 | 36.29.56 | 36.28.56 |
| GTX3:DRP38 | 37.29.7 | 37.28.7 | 37.29.6 | 37.28.6 | 37.29.5 | 37.28.5 | 37.29.4 | 37.28.4 | 37.29.3 | 37.28.3 | 37.29.2 | 37.28.2 | 37.29.1 | 37.28.1 | 37.29.0 | 37.28.0 |
| GTX3:DRP39 | 37.29.15 | 37.28.15 | 37.29.14 | 37.28.14 | 37.29.13 | 37.28.13 | 37.29.12 | 37.28.12 | 37.29.11 | 37.28.11 | 37.29.10 | 37.28.10 | 37.29.9 | 37.28.9 | 37.29.8 | 37.28.8 |
| GTX3:DRP3A | 37.29.23 | 37.28.23 | 37.29.22 | 37.28.22 | 37.29.21 | 37.28.21 | 37.29.20 | 37.28.20 | 37.29.19 | 37.28.19 | 37.29.18 | 37.28.18 | 37.29.17 | 37.28.17 | 37.29.16 | 37.28.16 |
| GTX3:DRP3B | 37.29.31 | 37.28.31 | 37.29.30 | 37.28.30 | 37.29.29 | 37.28.29 | 37.29.28 | 37.28.28 | 37.29.27 | 37.28.27 | 37.29.26 | 37.28.26 | 37.29.25 | 37.28.25 | 37.29.24 | 37.28.24 |
| GTX3:DRP3C | 37.29.39 | 37.28.39 | 37.29.38 | 37.28.38 | 37.29.37 | 37.28.37 | 37.29.36 | 37.28.36 | 37.29.35 | 37.28.35 | 37.29.34 | 37.28.34 | 37.29.33 | 37.28.33 | 37.29.32 | 37.28.32 |
| GTX3:DRP3D | 37.29.47 | 37.28.47 | 37.29.46 | 37.28.46 | 37.29.45 | 37.28.45 | 37.29.44 | 37.28.44 | 37.29.43 | 37.28.43 | 37.29.42 | 37.28.42 | 37.29.41 | 37.28.41 | 37.29.40 | 37.28.40 |
| GTX3:DRP3E | 37.29.55 | 37.28.55 | 37.29.54 | 37.28.54 | 37.29.53 | 37.28.53 | 37.29.52 | 37.28.52 | 37.29.51 | 37.28.51 | 37.29.50 | 37.28.50 | 37.29.49 | 37.28.49 | 37.29.48 | 37.28.48 |
| GTX3:DRP3F | 37.29.63 | 37.28.63 | 37.29.62 | 37.28.62 | 37.29.61 | 37.28.61 | 37.29.60 | 37.28.60 | 37.29.59 | 37.28.59 | 37.29.58 | 37.28.58 | 37.29.57 | 37.28.57 | 37.29.56 | 37.28.56 |
| GTX3:DRP40 | 38.29.7 | 38.28.7 | 38.29.6 | 38.28.6 | 38.29.5 | 38.28.5 | 38.29.4 | 38.28.4 | 38.29.3 | 38.28.3 | 38.29.2 | 38.28.2 | 38.29.1 | 38.28.1 | 38.29.0 | 38.28.0 |
| GTX3:DRP41 | 38.29.15 | 38.28.15 | 38.29.14 | 38.28.14 | 38.29.13 | 38.28.13 | 38.29.12 | 38.28.12 | 38.29.11 | 38.28.11 | 38.29.10 | 38.28.10 | 38.29.9 | 38.28.9 | 38.29.8 | 38.28.8 |
| GTX3:DRP42 | 38.29.23 | 38.28.23 | 38.29.22 | 38.28.22 | 38.29.21 | 38.28.21 | 38.29.20 | 38.28.20 | 38.29.19 | 38.28.19 | 38.29.18 | 38.28.18 | 38.29.17 | 38.28.17 | 38.29.16 | 38.28.16 |
| GTX3:DRP43 | 38.29.31 | 38.28.31 | 38.29.30 | 38.28.30 | 38.29.29 | 38.28.29 | 38.29.28 | 38.28.28 | 38.29.27 | 38.28.27 | 38.29.26 | 38.28.26 | 38.29.25 | 38.28.25 | 38.29.24 | 38.28.24 |
| GTX3:DRP44 | 38.29.39 | 38.28.39 | 38.29.38 | 38.28.38 | 38.29.37 | 38.28.37 | 38.29.36 | 38.28.36 | 38.29.35 | 38.28.35 | 38.29.34 | 38.28.34 | 38.29.33 | 38.28.33 | 38.29.32 | 38.28.32 |
| GTX3:DRP45 | 38.29.47 | 38.28.47 | 38.29.46 | 38.28.46 | 38.29.45 | 38.28.45 | 38.29.44 | 38.28.44 | 38.29.43 | 38.28.43 | 38.29.42 | 38.28.42 | 38.29.41 | 38.28.41 | 38.29.40 | 38.28.40 |
| GTX3:DRP46 | 38.29.55 | 38.28.55 | 38.29.54 | 38.28.54 | 38.29.53 | 38.28.53 | 38.29.52 | 38.28.52 | 38.29.51 | 38.28.51 | 38.29.50 | 38.28.50 | 38.29.49 | 38.28.49 | 38.29.48 | 38.28.48 |
| GTX3:DRP47 | 38.29.63 | 38.28.63 | 38.29.62 | 38.28.62 | 38.29.61 | 38.28.61 | 38.29.60 | 38.28.60 | 38.29.59 | 38.28.59 | 38.29.58 | 38.28.58 | 38.29.57 | 38.28.57 | 38.29.56 | 38.28.56 |
| GTX3:DRP48 | 39.29.7 | 39.28.7 | 39.29.6 | 39.28.6 | 39.29.5 | 39.28.5 | 39.29.4 | 39.28.4 | 39.29.3 | 39.28.3 | 39.29.2 | 39.28.2 | 39.29.1 | 39.28.1 | 39.29.0 | 39.28.0 |
| GTX3:DRP49 | 39.29.15 | 39.28.15 | 39.29.14 | 39.28.14 | 39.29.13 | 39.28.13 | 39.29.12 | 39.28.12 | 39.29.11 | 39.28.11 | 39.29.10 | 39.28.10 | 39.29.9 | 39.28.9 | 39.29.8 | 39.28.8 |
| GTX3:DRP4A | 39.29.23 | 39.28.23 | 39.29.22 | 39.28.22 | 39.29.21 | 39.28.21 | 39.29.20 | 39.28.20 | 39.29.19 | 39.28.19 | 39.29.18 | 39.28.18 | 39.29.17 | 39.28.17 | 39.29.16 | 39.28.16 |
| GTX3:DRP4B | 39.29.31 | 39.28.31 | 39.29.30 | 39.28.30 | 39.29.29 | 39.28.29 | 39.29.28 | 39.28.28 | 39.29.27 | 39.28.27 | 39.29.26 | 39.28.26 | 39.29.25 | 39.28.25 | 39.29.24 | 39.28.24 |
| GTX3:DRP4C | 39.29.39 | 39.28.39 | 39.29.38 | 39.28.38 | 39.29.37 | 39.28.37 | 39.29.36 | 39.28.36 | 39.29.35 | 39.28.35 | 39.29.34 | 39.28.34 | 39.29.33 | 39.28.33 | 39.29.32 | 39.28.32 |
| GTX3:DRP4D | 39.29.47 | 39.28.47 | 39.29.46 | 39.28.46 | 39.29.45 | 39.28.45 | 39.29.44 | 39.28.44 | 39.29.43 | 39.28.43 | 39.29.42 | 39.28.42 | 39.29.41 | 39.28.41 | 39.29.40 | 39.28.40 |
| GTX3:DRP4E | 39.29.55 | 39.28.55 | 39.29.54 | 39.28.54 | 39.29.53 | 39.28.53 | 39.29.52 | 39.28.52 | 39.29.51 | 39.28.51 | 39.29.50 | 39.28.50 | 39.29.49 | 39.28.49 | 39.29.48 | 39.28.48 |
| GTX3:DRP4F | 39.29.63 | 39.28.63 | 39.29.62 | 39.28.62 | 39.29.61 | 39.28.61 | 39.29.60 | 39.28.60 | 39.29.59 | 39.28.59 | 39.29.58 | 39.28.58 | 39.29.57 | 39.28.57 | 39.29.56 | 39.28.56 |
| GTX3:RXUSRCLK_DLY | 30.29.23 | 30.28.23 | 30.29.22 | 30.28.22 | 30.29.21 | 30.28.21 | 30.29.20 | 30.28.20 | 30.29.19 | 30.28.19 | 30.29.18 | 30.28.18 | 30.29.17 | 30.28.17 | 30.29.16 | 30.28.16 |
| non-inverted | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| GTX0:INV.DCLK | 7.29.7 |
|---|---|
| GTX0:INV.GREFCLKRX | 8.29.31 |
| GTX0:INV.GREFCLKTX | 8.28.31 |
| GTX0:INV.RXUSRCLK | 0.28.47 |
| GTX0:INV.RXUSRCLK2 | 0.29.47 |
| GTX0:INV.SCANCLK | 8.29.30 |
| GTX0:INV.TSTCLK0 | 8.28.29 |
| GTX0:INV.TSTCLK1 | 8.29.29 |
| GTX0:INV.TXUSRCLK | 6.28.7 |
| GTX0:INV.TXUSRCLK2 | 6.29.7 |
| GTX0:TXDRIVE_LOOPBACK_HIZ | 7.28.23 |
| GTX0:TXDRIVE_LOOPBACK_PD | 7.29.23 |
| GTX1:INV.DCLK | 17.29.7 |
| GTX1:INV.GREFCLKRX | 18.29.31 |
| GTX1:INV.GREFCLKTX | 18.28.31 |
| GTX1:INV.RXUSRCLK | 10.28.47 |
| GTX1:INV.RXUSRCLK2 | 10.29.47 |
| GTX1:INV.SCANCLK | 18.29.30 |
| GTX1:INV.TSTCLK0 | 18.28.29 |
| GTX1:INV.TSTCLK1 | 18.29.29 |
| GTX1:INV.TXUSRCLK | 16.28.7 |
| GTX1:INV.TXUSRCLK2 | 16.29.7 |
| GTX1:TXDRIVE_LOOPBACK_HIZ | 17.28.23 |
| GTX1:TXDRIVE_LOOPBACK_PD | 17.29.23 |
| GTX2:INV.DCLK | 27.29.7 |
| GTX2:INV.GREFCLKRX | 28.29.31 |
| GTX2:INV.GREFCLKTX | 28.28.31 |
| GTX2:INV.RXUSRCLK | 20.28.47 |
| GTX2:INV.RXUSRCLK2 | 20.29.47 |
| GTX2:INV.SCANCLK | 28.29.30 |
| GTX2:INV.TSTCLK0 | 28.28.29 |
| GTX2:INV.TSTCLK1 | 28.29.29 |
| GTX2:INV.TXUSRCLK | 26.28.7 |
| GTX2:INV.TXUSRCLK2 | 26.29.7 |
| GTX2:TXDRIVE_LOOPBACK_HIZ | 27.28.23 |
| GTX2:TXDRIVE_LOOPBACK_PD | 27.29.23 |
| GTX3:INV.DCLK | 37.29.7 |
| GTX3:INV.GREFCLKRX | 38.29.31 |
| GTX3:INV.GREFCLKTX | 38.28.31 |
| GTX3:INV.RXUSRCLK | 30.28.47 |
| GTX3:INV.RXUSRCLK2 | 30.29.47 |
| GTX3:INV.SCANCLK | 38.29.30 |
| GTX3:INV.TSTCLK0 | 38.28.29 |
| GTX3:INV.TSTCLK1 | 38.29.29 |
| GTX3:INV.TXUSRCLK | 36.28.7 |
| GTX3:INV.TXUSRCLK2 | 36.29.7 |
| GTX3:TXDRIVE_LOOPBACK_HIZ | 37.28.23 |
| GTX3:TXDRIVE_LOOPBACK_PD | 37.29.23 |
| inverted | ~[0] |
| GTX0:PMA_CDR_SCAN | 2.28.53 | 2.29.52 | 2.28.52 | 2.29.51 | 2.28.51 | 2.29.50 | 2.28.50 | 2.29.49 | 2.28.49 | 2.29.48 | 2.28.48 | 2.29.47 | 2.28.47 | 2.29.46 | 2.28.46 | 2.29.45 | 2.28.45 | 2.29.44 | 2.28.44 | 2.29.43 | 2.28.43 | 2.29.42 | 2.28.42 | 2.29.41 | 2.28.41 | 2.29.40 | 2.28.40 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GTX1:PMA_CDR_SCAN | 12.28.53 | 12.29.52 | 12.28.52 | 12.29.51 | 12.28.51 | 12.29.50 | 12.28.50 | 12.29.49 | 12.28.49 | 12.29.48 | 12.28.48 | 12.29.47 | 12.28.47 | 12.29.46 | 12.28.46 | 12.29.45 | 12.28.45 | 12.29.44 | 12.28.44 | 12.29.43 | 12.28.43 | 12.29.42 | 12.28.42 | 12.29.41 | 12.28.41 | 12.29.40 | 12.28.40 |
| GTX2:PMA_CDR_SCAN | 22.28.53 | 22.29.52 | 22.28.52 | 22.29.51 | 22.28.51 | 22.29.50 | 22.28.50 | 22.29.49 | 22.28.49 | 22.29.48 | 22.28.48 | 22.29.47 | 22.28.47 | 22.29.46 | 22.28.46 | 22.29.45 | 22.28.45 | 22.29.44 | 22.28.44 | 22.29.43 | 22.28.43 | 22.29.42 | 22.28.42 | 22.29.41 | 22.28.41 | 22.29.40 | 22.28.40 |
| GTX3:PMA_CDR_SCAN | 32.28.53 | 32.29.52 | 32.28.52 | 32.29.51 | 32.28.51 | 32.29.50 | 32.28.50 | 32.29.49 | 32.28.49 | 32.29.48 | 32.28.48 | 32.29.47 | 32.28.47 | 32.29.46 | 32.28.46 | 32.29.45 | 32.28.45 | 32.29.44 | 32.28.44 | 32.29.43 | 32.28.43 | 32.29.42 | 32.28.42 | 32.29.41 | 32.28.41 | 32.29.40 | 32.28.40 |
| non-inverted | [26] | [25] | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| GTX0:PMA_CFG | 6.29.55 | 6.28.55 | 6.29.54 | 6.28.54 | 6.29.53 | 6.28.53 | 6.29.52 | 6.28.52 | 6.29.51 | 6.28.51 | 6.29.50 | 6.28.50 | 6.29.47 | 6.28.47 | 6.29.46 | 6.28.46 | 6.29.45 | 6.28.45 | 6.29.44 | 6.28.44 | 6.29.43 | 6.28.43 | 6.29.42 | 6.28.42 | 6.29.41 | 6.28.41 | 6.29.40 | 6.28.40 | 6.29.39 | 6.28.39 | 6.29.38 | 6.28.38 | 6.29.37 | 6.28.37 | 6.29.36 | 6.28.36 | 6.29.35 | 6.28.35 | 6.29.34 | 6.28.34 | 6.29.33 | 6.28.33 | 6.29.32 | 6.28.32 | 6.29.31 | 6.28.31 | 6.29.30 | 6.28.30 | 6.29.29 | 6.28.29 | 6.29.28 | 6.28.28 | 6.29.27 | 6.28.27 | 6.29.26 | 6.28.26 | 6.29.25 | 6.28.25 | 6.29.24 | 6.28.24 | 6.29.23 | 6.28.23 | 6.29.22 | 6.28.22 | 6.29.21 | 6.28.21 | 6.29.20 | 6.28.20 | 6.29.19 | 6.28.19 | 6.29.18 | 6.28.18 | 6.29.17 | 6.28.17 | 6.29.16 | 6.28.16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GTX1:PMA_CFG | 16.29.55 | 16.28.55 | 16.29.54 | 16.28.54 | 16.29.53 | 16.28.53 | 16.29.52 | 16.28.52 | 16.29.51 | 16.28.51 | 16.29.50 | 16.28.50 | 16.29.47 | 16.28.47 | 16.29.46 | 16.28.46 | 16.29.45 | 16.28.45 | 16.29.44 | 16.28.44 | 16.29.43 | 16.28.43 | 16.29.42 | 16.28.42 | 16.29.41 | 16.28.41 | 16.29.40 | 16.28.40 | 16.29.39 | 16.28.39 | 16.29.38 | 16.28.38 | 16.29.37 | 16.28.37 | 16.29.36 | 16.28.36 | 16.29.35 | 16.28.35 | 16.29.34 | 16.28.34 | 16.29.33 | 16.28.33 | 16.29.32 | 16.28.32 | 16.29.31 | 16.28.31 | 16.29.30 | 16.28.30 | 16.29.29 | 16.28.29 | 16.29.28 | 16.28.28 | 16.29.27 | 16.28.27 | 16.29.26 | 16.28.26 | 16.29.25 | 16.28.25 | 16.29.24 | 16.28.24 | 16.29.23 | 16.28.23 | 16.29.22 | 16.28.22 | 16.29.21 | 16.28.21 | 16.29.20 | 16.28.20 | 16.29.19 | 16.28.19 | 16.29.18 | 16.28.18 | 16.29.17 | 16.28.17 | 16.29.16 | 16.28.16 |
| GTX2:PMA_CFG | 26.29.55 | 26.28.55 | 26.29.54 | 26.28.54 | 26.29.53 | 26.28.53 | 26.29.52 | 26.28.52 | 26.29.51 | 26.28.51 | 26.29.50 | 26.28.50 | 26.29.47 | 26.28.47 | 26.29.46 | 26.28.46 | 26.29.45 | 26.28.45 | 26.29.44 | 26.28.44 | 26.29.43 | 26.28.43 | 26.29.42 | 26.28.42 | 26.29.41 | 26.28.41 | 26.29.40 | 26.28.40 | 26.29.39 | 26.28.39 | 26.29.38 | 26.28.38 | 26.29.37 | 26.28.37 | 26.29.36 | 26.28.36 | 26.29.35 | 26.28.35 | 26.29.34 | 26.28.34 | 26.29.33 | 26.28.33 | 26.29.32 | 26.28.32 | 26.29.31 | 26.28.31 | 26.29.30 | 26.28.30 | 26.29.29 | 26.28.29 | 26.29.28 | 26.28.28 | 26.29.27 | 26.28.27 | 26.29.26 | 26.28.26 | 26.29.25 | 26.28.25 | 26.29.24 | 26.28.24 | 26.29.23 | 26.28.23 | 26.29.22 | 26.28.22 | 26.29.21 | 26.28.21 | 26.29.20 | 26.28.20 | 26.29.19 | 26.28.19 | 26.29.18 | 26.28.18 | 26.29.17 | 26.28.17 | 26.29.16 | 26.28.16 |
| GTX3:PMA_CFG | 36.29.55 | 36.28.55 | 36.29.54 | 36.28.54 | 36.29.53 | 36.28.53 | 36.29.52 | 36.28.52 | 36.29.51 | 36.28.51 | 36.29.50 | 36.28.50 | 36.29.47 | 36.28.47 | 36.29.46 | 36.28.46 | 36.29.45 | 36.28.45 | 36.29.44 | 36.28.44 | 36.29.43 | 36.28.43 | 36.29.42 | 36.28.42 | 36.29.41 | 36.28.41 | 36.29.40 | 36.28.40 | 36.29.39 | 36.28.39 | 36.29.38 | 36.28.38 | 36.29.37 | 36.28.37 | 36.29.36 | 36.28.36 | 36.29.35 | 36.28.35 | 36.29.34 | 36.28.34 | 36.29.33 | 36.28.33 | 36.29.32 | 36.28.32 | 36.29.31 | 36.28.31 | 36.29.30 | 36.28.30 | 36.29.29 | 36.28.29 | 36.29.28 | 36.28.28 | 36.29.27 | 36.28.27 | 36.29.26 | 36.28.26 | 36.29.25 | 36.28.25 | 36.29.24 | 36.28.24 | 36.29.23 | 36.28.23 | 36.29.22 | 36.28.22 | 36.29.21 | 36.28.21 | 36.29.20 | 36.28.20 | 36.29.19 | 36.28.19 | 36.29.18 | 36.28.18 | 36.29.17 | 36.28.17 | 36.29.16 | 36.28.16 |
| non-inverted | [75] | [74] | [73] | [72] | [71] | [70] | [69] | [68] | [67] | [66] | [65] | [64] | [63] | [62] | [61] | [60] | [59] | [58] | [57] | [56] | [55] | [54] | [53] | [52] | [51] | [50] | [49] | [48] | [47] | [46] | [45] | [44] | [43] | [42] | [41] | [40] | [39] | [38] | [37] | [36] | [35] | [34] | [33] | [32] | [31] | [30] | [29] | [28] | [27] | [26] | [25] | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| GTX0:PMA_RXSYNC_CFG | 0.29.15 | 0.28.15 | 0.29.14 | 0.28.14 | 0.29.13 | 0.28.13 | 0.29.12 |
|---|---|---|---|---|---|---|---|
| GTX0:TX_MARGIN_FULL_0 | 7.29.6 | 7.28.6 | 7.29.5 | 7.28.5 | 7.29.4 | 7.28.4 | 7.29.3 |
| GTX0:TX_MARGIN_FULL_1 | 7.29.14 | 7.28.14 | 7.29.13 | 7.28.13 | 7.29.12 | 7.28.12 | 7.29.11 |
| GTX0:TX_MARGIN_FULL_2 | 7.29.22 | 7.28.22 | 7.29.21 | 7.28.21 | 7.29.20 | 7.28.20 | 7.29.19 |
| GTX0:TX_MARGIN_FULL_3 | 7.29.30 | 7.28.30 | 7.29.29 | 7.28.29 | 7.29.28 | 7.28.28 | 7.29.27 |
| GTX0:TX_MARGIN_FULL_4 | 7.29.38 | 7.28.38 | 7.29.37 | 7.28.37 | 7.29.36 | 7.28.36 | 7.29.35 |
| GTX0:TX_MARGIN_LOW_0 | 7.28.3 | 7.29.2 | 7.28.2 | 7.29.1 | 7.28.1 | 7.29.0 | 7.28.0 |
| GTX0:TX_MARGIN_LOW_1 | 7.28.11 | 7.29.10 | 7.28.10 | 7.29.9 | 7.28.9 | 7.29.8 | 7.28.8 |
| GTX0:TX_MARGIN_LOW_2 | 7.28.19 | 7.29.18 | 7.28.18 | 7.29.17 | 7.28.17 | 7.29.16 | 7.28.16 |
| GTX0:TX_MARGIN_LOW_3 | 7.28.27 | 7.29.26 | 7.28.26 | 7.29.25 | 7.28.25 | 7.29.24 | 7.28.24 |
| GTX0:TX_MARGIN_LOW_4 | 7.28.35 | 7.29.34 | 7.28.34 | 7.29.33 | 7.28.33 | 7.29.32 | 7.28.32 |
| GTX1:PMA_RXSYNC_CFG | 10.29.15 | 10.28.15 | 10.29.14 | 10.28.14 | 10.29.13 | 10.28.13 | 10.29.12 |
| GTX1:TX_MARGIN_FULL_0 | 17.29.6 | 17.28.6 | 17.29.5 | 17.28.5 | 17.29.4 | 17.28.4 | 17.29.3 |
| GTX1:TX_MARGIN_FULL_1 | 17.29.14 | 17.28.14 | 17.29.13 | 17.28.13 | 17.29.12 | 17.28.12 | 17.29.11 |
| GTX1:TX_MARGIN_FULL_2 | 17.29.22 | 17.28.22 | 17.29.21 | 17.28.21 | 17.29.20 | 17.28.20 | 17.29.19 |
| GTX1:TX_MARGIN_FULL_3 | 17.29.30 | 17.28.30 | 17.29.29 | 17.28.29 | 17.29.28 | 17.28.28 | 17.29.27 |
| GTX1:TX_MARGIN_FULL_4 | 17.29.38 | 17.28.38 | 17.29.37 | 17.28.37 | 17.29.36 | 17.28.36 | 17.29.35 |
| GTX1:TX_MARGIN_LOW_0 | 17.28.3 | 17.29.2 | 17.28.2 | 17.29.1 | 17.28.1 | 17.29.0 | 17.28.0 |
| GTX1:TX_MARGIN_LOW_1 | 17.28.11 | 17.29.10 | 17.28.10 | 17.29.9 | 17.28.9 | 17.29.8 | 17.28.8 |
| GTX1:TX_MARGIN_LOW_2 | 17.28.19 | 17.29.18 | 17.28.18 | 17.29.17 | 17.28.17 | 17.29.16 | 17.28.16 |
| GTX1:TX_MARGIN_LOW_3 | 17.28.27 | 17.29.26 | 17.28.26 | 17.29.25 | 17.28.25 | 17.29.24 | 17.28.24 |
| GTX1:TX_MARGIN_LOW_4 | 17.28.35 | 17.29.34 | 17.28.34 | 17.29.33 | 17.28.33 | 17.29.32 | 17.28.32 |
| GTX2:PMA_RXSYNC_CFG | 20.29.15 | 20.28.15 | 20.29.14 | 20.28.14 | 20.29.13 | 20.28.13 | 20.29.12 |
| GTX2:TX_MARGIN_FULL_0 | 27.29.6 | 27.28.6 | 27.29.5 | 27.28.5 | 27.29.4 | 27.28.4 | 27.29.3 |
| GTX2:TX_MARGIN_FULL_1 | 27.29.14 | 27.28.14 | 27.29.13 | 27.28.13 | 27.29.12 | 27.28.12 | 27.29.11 |
| GTX2:TX_MARGIN_FULL_2 | 27.29.22 | 27.28.22 | 27.29.21 | 27.28.21 | 27.29.20 | 27.28.20 | 27.29.19 |
| GTX2:TX_MARGIN_FULL_3 | 27.29.30 | 27.28.30 | 27.29.29 | 27.28.29 | 27.29.28 | 27.28.28 | 27.29.27 |
| GTX2:TX_MARGIN_FULL_4 | 27.29.38 | 27.28.38 | 27.29.37 | 27.28.37 | 27.29.36 | 27.28.36 | 27.29.35 |
| GTX2:TX_MARGIN_LOW_0 | 27.28.3 | 27.29.2 | 27.28.2 | 27.29.1 | 27.28.1 | 27.29.0 | 27.28.0 |
| GTX2:TX_MARGIN_LOW_1 | 27.28.11 | 27.29.10 | 27.28.10 | 27.29.9 | 27.28.9 | 27.29.8 | 27.28.8 |
| GTX2:TX_MARGIN_LOW_2 | 27.28.19 | 27.29.18 | 27.28.18 | 27.29.17 | 27.28.17 | 27.29.16 | 27.28.16 |
| GTX2:TX_MARGIN_LOW_3 | 27.28.27 | 27.29.26 | 27.28.26 | 27.29.25 | 27.28.25 | 27.29.24 | 27.28.24 |
| GTX2:TX_MARGIN_LOW_4 | 27.28.35 | 27.29.34 | 27.28.34 | 27.29.33 | 27.28.33 | 27.29.32 | 27.28.32 |
| GTX3:PMA_RXSYNC_CFG | 30.29.15 | 30.28.15 | 30.29.14 | 30.28.14 | 30.29.13 | 30.28.13 | 30.29.12 |
| GTX3:TX_MARGIN_FULL_0 | 37.29.6 | 37.28.6 | 37.29.5 | 37.28.5 | 37.29.4 | 37.28.4 | 37.29.3 |
| GTX3:TX_MARGIN_FULL_1 | 37.29.14 | 37.28.14 | 37.29.13 | 37.28.13 | 37.29.12 | 37.28.12 | 37.29.11 |
| GTX3:TX_MARGIN_FULL_2 | 37.29.22 | 37.28.22 | 37.29.21 | 37.28.21 | 37.29.20 | 37.28.20 | 37.29.19 |
| GTX3:TX_MARGIN_FULL_3 | 37.29.30 | 37.28.30 | 37.29.29 | 37.28.29 | 37.29.28 | 37.28.28 | 37.29.27 |
| GTX3:TX_MARGIN_FULL_4 | 37.29.38 | 37.28.38 | 37.29.37 | 37.28.37 | 37.29.36 | 37.28.36 | 37.29.35 |
| GTX3:TX_MARGIN_LOW_0 | 37.28.3 | 37.29.2 | 37.28.2 | 37.29.1 | 37.28.1 | 37.29.0 | 37.28.0 |
| GTX3:TX_MARGIN_LOW_1 | 37.28.11 | 37.29.10 | 37.28.10 | 37.29.9 | 37.28.9 | 37.29.8 | 37.28.8 |
| GTX3:TX_MARGIN_LOW_2 | 37.28.19 | 37.29.18 | 37.28.18 | 37.29.17 | 37.28.17 | 37.29.16 | 37.28.16 |
| GTX3:TX_MARGIN_LOW_3 | 37.28.27 | 37.29.26 | 37.28.26 | 37.29.25 | 37.28.25 | 37.29.24 | 37.28.24 |
| GTX3:TX_MARGIN_LOW_4 | 37.28.35 | 37.29.34 | 37.28.34 | 37.29.33 | 37.28.33 | 37.29.32 | 37.28.32 |
| non-inverted | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| GTX0:PMA_RX_CFG | 0.28.12 | 0.29.11 | 0.28.11 | 0.29.10 | 0.28.10 | 0.29.9 | 0.28.9 | 0.29.8 | 0.28.8 | 0.29.7 | 0.28.7 | 0.29.6 | 0.28.6 | 0.29.5 | 0.28.5 | 0.29.4 | 0.28.4 | 0.29.3 | 0.28.3 | 0.29.2 | 0.28.2 | 0.29.1 | 0.28.1 | 0.29.0 | 0.28.0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GTX1:PMA_RX_CFG | 10.28.12 | 10.29.11 | 10.28.11 | 10.29.10 | 10.28.10 | 10.29.9 | 10.28.9 | 10.29.8 | 10.28.8 | 10.29.7 | 10.28.7 | 10.29.6 | 10.28.6 | 10.29.5 | 10.28.5 | 10.29.4 | 10.28.4 | 10.29.3 | 10.28.3 | 10.29.2 | 10.28.2 | 10.29.1 | 10.28.1 | 10.29.0 | 10.28.0 |
| GTX2:PMA_RX_CFG | 20.28.12 | 20.29.11 | 20.28.11 | 20.29.10 | 20.28.10 | 20.29.9 | 20.28.9 | 20.29.8 | 20.28.8 | 20.29.7 | 20.28.7 | 20.29.6 | 20.28.6 | 20.29.5 | 20.28.5 | 20.29.4 | 20.28.4 | 20.29.3 | 20.28.3 | 20.29.2 | 20.28.2 | 20.29.1 | 20.28.1 | 20.29.0 | 20.28.0 |
| GTX3:PMA_RX_CFG | 30.28.12 | 30.29.11 | 30.28.11 | 30.29.10 | 30.28.10 | 30.29.9 | 30.28.9 | 30.29.8 | 30.28.8 | 30.29.7 | 30.28.7 | 30.29.6 | 30.28.6 | 30.29.5 | 30.28.5 | 30.29.4 | 30.28.4 | 30.29.3 | 30.28.3 | 30.29.2 | 30.28.2 | 30.29.1 | 30.28.1 | 30.29.0 | 30.28.0 |
| non-inverted | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| GTX0:PMA_TX_CFG | 6.29.49 | 6.28.49 | 6.29.48 | 6.28.48 | 6.29.63 | 6.28.63 | 6.29.62 | 6.28.62 | 6.29.61 | 6.28.61 | 6.29.60 | 6.28.60 | 6.29.59 | 6.28.59 | 6.29.58 | 6.28.58 | 6.29.57 | 6.28.57 | 6.29.56 | 6.28.56 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GTX1:PMA_TX_CFG | 16.29.49 | 16.28.49 | 16.29.48 | 16.28.48 | 16.29.63 | 16.28.63 | 16.29.62 | 16.28.62 | 16.29.61 | 16.28.61 | 16.29.60 | 16.28.60 | 16.29.59 | 16.28.59 | 16.29.58 | 16.28.58 | 16.29.57 | 16.28.57 | 16.29.56 | 16.28.56 |
| GTX2:PMA_TX_CFG | 26.29.49 | 26.28.49 | 26.29.48 | 26.28.48 | 26.29.63 | 26.28.63 | 26.29.62 | 26.28.62 | 26.29.61 | 26.28.61 | 26.29.60 | 26.28.60 | 26.29.59 | 26.28.59 | 26.29.58 | 26.28.58 | 26.29.57 | 26.28.57 | 26.29.56 | 26.28.56 |
| GTX3:PMA_TX_CFG | 36.29.49 | 36.28.49 | 36.29.48 | 36.28.48 | 36.29.63 | 36.28.63 | 36.29.62 | 36.28.62 | 36.29.61 | 36.28.61 | 36.29.60 | 36.28.60 | 36.29.59 | 36.28.59 | 36.29.58 | 36.28.58 | 36.29.57 | 36.28.57 | 36.29.56 | 36.28.56 |
| non-inverted | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| GTX0:RXPLLREFSEL_MODE | 3.28.35 |
|---|---|
| GTX0:TXPLLREFSEL_MODE | 4.28.3 |
| GTX1:RXPLLREFSEL_MODE | 13.28.35 |
| GTX1:TXPLLREFSEL_MODE | 14.28.3 |
| GTX2:RXPLLREFSEL_MODE | 23.28.35 |
| GTX2:TXPLLREFSEL_MODE | 24.28.3 |
| GTX3:RXPLLREFSEL_MODE | 33.28.35 |
| GTX3:TXPLLREFSEL_MODE | 34.28.3 |
| STATIC | 0 |
| DYNAMIC | 1 |
| GTX0:RXPLLREFSEL_STATIC | 3.29.36 | 3.28.36 | 3.29.35 |
|---|---|---|---|
| GTX0:TXPLLREFSEL_STATIC | 4.29.4 | 4.28.4 | 4.29.3 |
| GTX1:RXPLLREFSEL_STATIC | 13.29.36 | 13.28.36 | 13.29.35 |
| GTX1:TXPLLREFSEL_STATIC | 14.29.4 | 14.28.4 | 14.29.3 |
| GTX2:RXPLLREFSEL_STATIC | 23.29.36 | 23.28.36 | 23.29.35 |
| GTX2:TXPLLREFSEL_STATIC | 24.29.4 | 24.28.4 | 24.29.3 |
| GTX3:RXPLLREFSEL_STATIC | 33.29.36 | 33.28.36 | 33.29.35 |
| GTX3:TXPLLREFSEL_STATIC | 34.29.4 | 34.28.4 | 34.29.3 |
| MGTREFCLK0 | 0 | 0 | 0 |
| MGTREFCLK1 | 0 | 0 | 1 |
| NORTHREFCLK0 | 0 | 1 | 0 |
| NORTHREFCLK1 | 0 | 1 | 1 |
| SOUTHREFCLK0 | 1 | 0 | 0 |
| SOUTHREFCLK1 | 1 | 0 | 1 |
| CAS_CLK | 1 | 1 | 0 |
| TESTCLK | 1 | 1 | 1 |
| GTX0:RXPLLREFSEL_TESTCLK | 3.28.32 |
|---|---|
| GTX0:TXPLLREFSEL_TESTCLK | 4.28.0 |
| GTX1:RXPLLREFSEL_TESTCLK | 13.28.32 |
| GTX1:TXPLLREFSEL_TESTCLK | 14.28.0 |
| GTX2:RXPLLREFSEL_TESTCLK | 23.28.32 |
| GTX2:TXPLLREFSEL_TESTCLK | 24.28.0 |
| GTX3:RXPLLREFSEL_TESTCLK | 33.28.32 |
| GTX3:TXPLLREFSEL_TESTCLK | 34.28.0 |
| GREFCLK | 0 |
| PERFCLK | 1 |
| GTX0:RXPLL_COM_CFG | 3.29.19 | 3.28.19 | 3.29.18 | 3.28.18 | 3.29.17 | 3.28.17 | 3.29.16 | 3.28.16 | 3.29.15 | 3.28.15 | 3.29.14 | 3.28.14 | 3.29.13 | 3.28.13 | 3.29.12 | 3.28.12 | 3.29.11 | 3.28.11 | 3.29.10 | 3.28.10 | 3.29.9 | 3.28.9 | 3.29.8 | 3.28.8 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GTX0:TXPLL_COM_CFG | 3.29.51 | 3.28.51 | 3.29.50 | 3.28.50 | 3.29.49 | 3.28.49 | 3.29.48 | 3.28.48 | 3.29.47 | 3.28.47 | 3.29.46 | 3.28.46 | 3.29.45 | 3.28.45 | 3.29.44 | 3.28.44 | 3.29.43 | 3.28.43 | 3.29.42 | 3.28.42 | 3.29.41 | 3.28.41 | 3.29.40 | 3.28.40 |
| GTX1:RXPLL_COM_CFG | 13.29.19 | 13.28.19 | 13.29.18 | 13.28.18 | 13.29.17 | 13.28.17 | 13.29.16 | 13.28.16 | 13.29.15 | 13.28.15 | 13.29.14 | 13.28.14 | 13.29.13 | 13.28.13 | 13.29.12 | 13.28.12 | 13.29.11 | 13.28.11 | 13.29.10 | 13.28.10 | 13.29.9 | 13.28.9 | 13.29.8 | 13.28.8 |
| GTX1:TXPLL_COM_CFG | 13.29.51 | 13.28.51 | 13.29.50 | 13.28.50 | 13.29.49 | 13.28.49 | 13.29.48 | 13.28.48 | 13.29.47 | 13.28.47 | 13.29.46 | 13.28.46 | 13.29.45 | 13.28.45 | 13.29.44 | 13.28.44 | 13.29.43 | 13.28.43 | 13.29.42 | 13.28.42 | 13.29.41 | 13.28.41 | 13.29.40 | 13.28.40 |
| GTX2:RXPLL_COM_CFG | 23.29.19 | 23.28.19 | 23.29.18 | 23.28.18 | 23.29.17 | 23.28.17 | 23.29.16 | 23.28.16 | 23.29.15 | 23.28.15 | 23.29.14 | 23.28.14 | 23.29.13 | 23.28.13 | 23.29.12 | 23.28.12 | 23.29.11 | 23.28.11 | 23.29.10 | 23.28.10 | 23.29.9 | 23.28.9 | 23.29.8 | 23.28.8 |
| GTX2:TXPLL_COM_CFG | 23.29.51 | 23.28.51 | 23.29.50 | 23.28.50 | 23.29.49 | 23.28.49 | 23.29.48 | 23.28.48 | 23.29.47 | 23.28.47 | 23.29.46 | 23.28.46 | 23.29.45 | 23.28.45 | 23.29.44 | 23.28.44 | 23.29.43 | 23.28.43 | 23.29.42 | 23.28.42 | 23.29.41 | 23.28.41 | 23.29.40 | 23.28.40 |
| GTX3:RXPLL_COM_CFG | 33.29.19 | 33.28.19 | 33.29.18 | 33.28.18 | 33.29.17 | 33.28.17 | 33.29.16 | 33.28.16 | 33.29.15 | 33.28.15 | 33.29.14 | 33.28.14 | 33.29.13 | 33.28.13 | 33.29.12 | 33.28.12 | 33.29.11 | 33.28.11 | 33.29.10 | 33.28.10 | 33.29.9 | 33.28.9 | 33.29.8 | 33.28.8 |
| GTX3:TXPLL_COM_CFG | 33.29.51 | 33.28.51 | 33.29.50 | 33.28.50 | 33.29.49 | 33.28.49 | 33.29.48 | 33.28.48 | 33.29.47 | 33.28.47 | 33.29.46 | 33.28.46 | 33.29.45 | 33.28.45 | 33.29.44 | 33.28.44 | 33.29.43 | 33.28.43 | 33.29.42 | 33.28.42 | 33.29.41 | 33.28.41 | 33.29.40 | 33.28.40 |
| non-inverted | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| GTX0:RXPLL_DIVSEL45_FB | 3.28.27 |
|---|---|
| GTX0:TXPLL_DIVSEL45_FB | 3.28.59 |
| GTX1:RXPLL_DIVSEL45_FB | 13.28.27 |
| GTX1:TXPLL_DIVSEL45_FB | 13.28.59 |
| GTX2:RXPLL_DIVSEL45_FB | 23.28.27 |
| GTX2:TXPLL_DIVSEL45_FB | 23.28.59 |
| GTX3:RXPLL_DIVSEL45_FB | 33.28.27 |
| GTX3:TXPLL_DIVSEL45_FB | 33.28.59 |
| 4 | 0 |
| 5 | 1 |
| GTX0:RXPLL_DIVSEL_FB | 3.28.26 | 3.29.25 | 3.28.25 | 3.29.24 | 3.29.26 |
|---|---|---|---|---|---|
| GTX0:RXPLL_DIVSEL_REF | 3.28.34 | 3.29.33 | 3.28.33 | 3.29.32 | 3.29.34 |
| GTX0:TXPLL_DIVSEL_FB | 3.28.58 | 3.29.57 | 3.28.57 | 3.29.56 | 3.29.58 |
| GTX0:TXPLL_DIVSEL_REF | 4.28.2 | 4.29.1 | 4.28.1 | 4.29.0 | 4.29.2 |
| GTX1:RXPLL_DIVSEL_FB | 13.28.26 | 13.29.25 | 13.28.25 | 13.29.24 | 13.29.26 |
| GTX1:RXPLL_DIVSEL_REF | 13.28.34 | 13.29.33 | 13.28.33 | 13.29.32 | 13.29.34 |
| GTX1:TXPLL_DIVSEL_FB | 13.28.58 | 13.29.57 | 13.28.57 | 13.29.56 | 13.29.58 |
| GTX1:TXPLL_DIVSEL_REF | 14.28.2 | 14.29.1 | 14.28.1 | 14.29.0 | 14.29.2 |
| GTX2:RXPLL_DIVSEL_FB | 23.28.26 | 23.29.25 | 23.28.25 | 23.29.24 | 23.29.26 |
| GTX2:RXPLL_DIVSEL_REF | 23.28.34 | 23.29.33 | 23.28.33 | 23.29.32 | 23.29.34 |
| GTX2:TXPLL_DIVSEL_FB | 23.28.58 | 23.29.57 | 23.28.57 | 23.29.56 | 23.29.58 |
| GTX2:TXPLL_DIVSEL_REF | 24.28.2 | 24.29.1 | 24.28.1 | 24.29.0 | 24.29.2 |
| GTX3:RXPLL_DIVSEL_FB | 33.28.26 | 33.29.25 | 33.28.25 | 33.29.24 | 33.29.26 |
| GTX3:RXPLL_DIVSEL_REF | 33.28.34 | 33.29.33 | 33.28.33 | 33.29.32 | 33.29.34 |
| GTX3:TXPLL_DIVSEL_FB | 33.28.58 | 33.29.57 | 33.28.57 | 33.29.56 | 33.29.58 |
| GTX3:TXPLL_DIVSEL_REF | 34.28.2 | 34.29.1 | 34.28.1 | 34.29.0 | 34.29.2 |
| 2 | 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 1 |
| 3 | 0 | 0 | 0 | 1 | 0 |
| 4 | 0 | 0 | 1 | 0 | 0 |
| 5 | 0 | 0 | 1 | 1 | 0 |
| 6 | 0 | 1 | 0 | 1 | 0 |
| 8 | 0 | 1 | 1 | 0 | 0 |
| 10 | 0 | 1 | 1 | 1 | 0 |
| 12 | 1 | 1 | 0 | 1 | 0 |
| 16 | 1 | 1 | 1 | 0 | 0 |
| 20 | 1 | 1 | 1 | 1 | 0 |
| GTX0:RXPLL_DIVSEL_OUT | 3.29.31 | 3.28.31 |
|---|---|---|
| GTX0:TXPLL_DIVSEL_OUT | 3.29.63 | 3.28.63 |
| GTX1:RXPLL_DIVSEL_OUT | 13.29.31 | 13.28.31 |
| GTX1:TXPLL_DIVSEL_OUT | 13.29.63 | 13.28.63 |
| GTX2:RXPLL_DIVSEL_OUT | 23.29.31 | 23.28.31 |
| GTX2:TXPLL_DIVSEL_OUT | 23.29.63 | 23.28.63 |
| GTX3:RXPLL_DIVSEL_OUT | 33.29.31 | 33.28.31 |
| GTX3:TXPLL_DIVSEL_OUT | 33.29.63 | 33.28.63 |
| 1 | 0 | 0 |
| 2 | 0 | 1 |
| 4 | 1 | 0 |
| GTX0:RXRECCLK_CTRL | 8.29.25 | 8.28.26 | 8.29.26 |
|---|---|---|---|
| GTX1:RXRECCLK_CTRL | 18.29.25 | 18.28.26 | 18.29.26 |
| GTX2:RXRECCLK_CTRL | 28.29.25 | 28.28.26 | 28.29.26 |
| GTX3:RXRECCLK_CTRL | 38.29.25 | 38.28.26 | 38.29.26 |
| RXRECCLKPCS | 0 | 0 | 0 |
| RXPLLREFCLK_DIV2 | 0 | 0 | 1 |
| RXRECCLKPMA_DIV2 | 0 | 1 | 0 |
| OFF_HIGH | 0 | 1 | 1 |
| RXRECCLKPMA_DIV1 | 1 | 0 | 0 |
| OFF_LOW | 1 | 0 | 1 |
| RXPLLREFCLK_DIV1 | 1 | 1 | 0 |
| CLKTESTSIG1 | 1 | 1 | 1 |
| GTX0:RX_CLK25_DIVIDER | 2.29.60 | 2.28.60 | 2.29.59 | 2.28.59 | 2.29.58 |
|---|---|---|---|---|---|
| GTX0:TX_CLK25_DIVIDER | 4.28.31 | 4.29.30 | 4.28.30 | 4.29.29 | 4.28.29 |
| GTX1:RX_CLK25_DIVIDER | 12.29.60 | 12.28.60 | 12.29.59 | 12.28.59 | 12.29.58 |
| GTX1:TX_CLK25_DIVIDER | 14.28.31 | 14.29.30 | 14.28.30 | 14.29.29 | 14.28.29 |
| GTX2:RX_CLK25_DIVIDER | 22.29.60 | 22.28.60 | 22.29.59 | 22.28.59 | 22.29.58 |
| GTX2:TX_CLK25_DIVIDER | 24.28.31 | 24.29.30 | 24.28.30 | 24.29.29 | 24.28.29 |
| GTX3:RX_CLK25_DIVIDER | 32.29.60 | 32.28.60 | 32.29.59 | 32.28.59 | 32.29.58 |
| GTX3:TX_CLK25_DIVIDER | 34.28.31 | 34.29.30 | 34.28.30 | 34.29.29 | 34.28.29 |
| 1 | 0 | 0 | 0 | 0 | 0 |
| 2 | 0 | 0 | 0 | 0 | 1 |
| 3 | 0 | 0 | 0 | 1 | 0 |
| 4 | 0 | 0 | 0 | 1 | 1 |
| 5 | 0 | 0 | 1 | 0 | 0 |
| 6 | 0 | 0 | 1 | 0 | 1 |
| 7 | 0 | 0 | 1 | 1 | 0 |
| 8 | 0 | 0 | 1 | 1 | 1 |
| 9 | 0 | 1 | 0 | 0 | 0 |
| 10 | 0 | 1 | 0 | 0 | 1 |
| 11 | 0 | 1 | 0 | 1 | 0 |
| 12 | 0 | 1 | 0 | 1 | 1 |
| 13 | 0 | 1 | 1 | 0 | 0 |
| 14 | 0 | 1 | 1 | 0 | 1 |
| 15 | 0 | 1 | 1 | 1 | 0 |
| 16 | 0 | 1 | 1 | 1 | 1 |
| 17 | 1 | 0 | 0 | 0 | 0 |
| 18 | 1 | 0 | 0 | 0 | 1 |
| 19 | 1 | 0 | 0 | 1 | 0 |
| 20 | 1 | 0 | 0 | 1 | 1 |
| 21 | 1 | 0 | 1 | 0 | 0 |
| 22 | 1 | 0 | 1 | 0 | 1 |
| 23 | 1 | 0 | 1 | 1 | 0 |
| 24 | 1 | 0 | 1 | 1 | 1 |
| 25 | 1 | 1 | 0 | 0 | 0 |
| 26 | 1 | 1 | 0 | 0 | 1 |
| 27 | 1 | 1 | 0 | 1 | 0 |
| 28 | 1 | 1 | 0 | 1 | 1 |
| 29 | 1 | 1 | 1 | 0 | 0 |
| 30 | 1 | 1 | 1 | 0 | 1 |
| 31 | 1 | 1 | 1 | 1 | 0 |
| 32 | 1 | 1 | 1 | 1 | 1 |
| GTX0:RX_DATA_WIDTH | 2.28.63 | 2.29.62 | 2.28.62 |
|---|---|---|---|
| GTX0:TX_DATA_WIDTH | 6.28.15 | 6.29.14 | 6.28.14 |
| GTX1:RX_DATA_WIDTH | 12.28.63 | 12.29.62 | 12.28.62 |
| GTX1:TX_DATA_WIDTH | 16.28.15 | 16.29.14 | 16.28.14 |
| GTX2:RX_DATA_WIDTH | 22.28.63 | 22.29.62 | 22.28.62 |
| GTX2:TX_DATA_WIDTH | 26.28.15 | 26.29.14 | 26.28.14 |
| GTX3:RX_DATA_WIDTH | 32.28.63 | 32.29.62 | 32.28.62 |
| GTX3:TX_DATA_WIDTH | 36.28.15 | 36.29.14 | 36.28.14 |
| 8 | 0 | 0 | 0 |
| 10 | 0 | 0 | 1 |
| 16 | 0 | 1 | 0 |
| 20 | 0 | 1 | 1 |
| 32 | 1 | 0 | 0 |
| 40 | 1 | 0 | 1 |
| GTX0:RX_FIFO_ADDR_MODE | 1.29.38 |
|---|---|
| GTX1:RX_FIFO_ADDR_MODE | 11.29.38 |
| GTX2:RX_FIFO_ADDR_MODE | 21.29.38 |
| GTX3:RX_FIFO_ADDR_MODE | 31.29.38 |
| FULL | 0 |
| FAST | 1 |
| GTX0:RX_LOS_INVALID_INCR | 0.29.55 | 0.28.55 | 0.29.54 |
|---|---|---|---|
| GTX1:RX_LOS_INVALID_INCR | 10.29.55 | 10.28.55 | 10.29.54 |
| GTX2:RX_LOS_INVALID_INCR | 20.29.55 | 20.28.55 | 20.29.54 |
| GTX3:RX_LOS_INVALID_INCR | 30.29.55 | 30.28.55 | 30.29.54 |
| 1 | 0 | 0 | 0 |
| 2 | 0 | 0 | 1 |
| 4 | 0 | 1 | 0 |
| 8 | 0 | 1 | 1 |
| 16 | 1 | 0 | 0 |
| 32 | 1 | 0 | 1 |
| 64 | 1 | 1 | 0 |
| 128 | 1 | 1 | 1 |
| GTX0:RX_LOS_THRESHOLD | 0.28.54 | 0.29.53 | 0.28.53 |
|---|---|---|---|
| GTX1:RX_LOS_THRESHOLD | 10.28.54 | 10.29.53 | 10.28.53 |
| GTX2:RX_LOS_THRESHOLD | 20.28.54 | 20.29.53 | 20.28.53 |
| GTX3:RX_LOS_THRESHOLD | 30.28.54 | 30.29.53 | 30.28.53 |
| 4 | 0 | 0 | 0 |
| 8 | 0 | 0 | 1 |
| 16 | 0 | 1 | 0 |
| 32 | 0 | 1 | 1 |
| 64 | 1 | 0 | 0 |
| 128 | 1 | 0 | 1 |
| 256 | 1 | 1 | 0 |
| 512 | 1 | 1 | 1 |
| GTX0:RX_SLIDE_MODE | 2.29.22 | 2.28.22 |
|---|---|---|
| GTX1:RX_SLIDE_MODE | 12.29.22 | 12.28.22 |
| GTX2:RX_SLIDE_MODE | 22.29.22 | 22.28.22 |
| GTX3:RX_SLIDE_MODE | 32.29.22 | 32.28.22 |
| #OFF | 0 | 0 |
| AUTO | 0 | 1 |
| PCS | 1 | 0 |
| PMA | 1 | 1 |
| GTX0:RX_XCLK_SEL | 1.29.29 |
|---|---|
| GTX1:RX_XCLK_SEL | 11.29.29 |
| GTX2:RX_XCLK_SEL | 21.29.29 |
| GTX3:RX_XCLK_SEL | 31.29.29 |
| RXREC | 0 |
| RXUSR | 1 |
| GTX0:TRANS_TIME_FROM_P2 | 4.29.37 | 4.28.37 | 4.29.36 | 4.28.36 | 4.29.35 | 4.28.35 | 4.29.34 | 4.28.34 | 4.29.33 | 4.28.33 | 4.29.32 | 4.28.32 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GTX1:TRANS_TIME_FROM_P2 | 14.29.37 | 14.28.37 | 14.29.36 | 14.28.36 | 14.29.35 | 14.28.35 | 14.29.34 | 14.28.34 | 14.29.33 | 14.28.33 | 14.29.32 | 14.28.32 |
| GTX2:TRANS_TIME_FROM_P2 | 24.29.37 | 24.28.37 | 24.29.36 | 24.28.36 | 24.29.35 | 24.28.35 | 24.29.34 | 24.28.34 | 24.29.33 | 24.28.33 | 24.29.32 | 24.28.32 |
| GTX3:TRANS_TIME_FROM_P2 | 34.29.37 | 34.28.37 | 34.29.36 | 34.28.36 | 34.29.35 | 34.28.35 | 34.29.34 | 34.28.34 | 34.29.33 | 34.28.33 | 34.29.32 | 34.28.32 |
| non-inverted | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| GTX0:TST_ATTR | 8.29.15 | 8.28.15 | 8.29.14 | 8.28.14 | 8.29.13 | 8.28.13 | 8.29.12 | 8.28.12 | 8.29.11 | 8.28.11 | 8.29.10 | 8.28.10 | 8.29.9 | 8.28.9 | 8.29.8 | 8.28.8 | 8.29.23 | 8.28.23 | 8.29.22 | 8.28.22 | 8.29.21 | 8.28.21 | 8.29.20 | 8.28.20 | 8.29.19 | 8.28.19 | 8.29.18 | 8.28.18 | 8.29.17 | 8.28.17 | 8.29.16 | 8.28.16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GTX1:TST_ATTR | 18.29.15 | 18.28.15 | 18.29.14 | 18.28.14 | 18.29.13 | 18.28.13 | 18.29.12 | 18.28.12 | 18.29.11 | 18.28.11 | 18.29.10 | 18.28.10 | 18.29.9 | 18.28.9 | 18.29.8 | 18.28.8 | 18.29.23 | 18.28.23 | 18.29.22 | 18.28.22 | 18.29.21 | 18.28.21 | 18.29.20 | 18.28.20 | 18.29.19 | 18.28.19 | 18.29.18 | 18.28.18 | 18.29.17 | 18.28.17 | 18.29.16 | 18.28.16 |
| GTX2:TST_ATTR | 28.29.15 | 28.28.15 | 28.29.14 | 28.28.14 | 28.29.13 | 28.28.13 | 28.29.12 | 28.28.12 | 28.29.11 | 28.28.11 | 28.29.10 | 28.28.10 | 28.29.9 | 28.28.9 | 28.29.8 | 28.28.8 | 28.29.23 | 28.28.23 | 28.29.22 | 28.28.22 | 28.29.21 | 28.28.21 | 28.29.20 | 28.28.20 | 28.29.19 | 28.28.19 | 28.29.18 | 28.28.18 | 28.29.17 | 28.28.17 | 28.29.16 | 28.28.16 |
| GTX3:TST_ATTR | 38.29.15 | 38.28.15 | 38.29.14 | 38.28.14 | 38.29.13 | 38.28.13 | 38.29.12 | 38.28.12 | 38.29.11 | 38.28.11 | 38.29.10 | 38.28.10 | 38.29.9 | 38.28.9 | 38.29.8 | 38.28.8 | 38.29.23 | 38.28.23 | 38.29.22 | 38.28.22 | 38.29.21 | 38.28.21 | 38.29.20 | 38.28.20 | 38.29.19 | 38.28.19 | 38.29.18 | 38.28.18 | 38.29.17 | 38.28.17 | 38.29.16 | 38.28.16 |
| non-inverted | [31] | [30] | [29] | [28] | [27] | [26] | [25] | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| GTX0:TXOUTCLK_CTRL | 8.28.24 | 8.29.24 | 8.28.25 |
|---|---|---|---|
| GTX1:TXOUTCLK_CTRL | 18.28.24 | 18.29.24 | 18.28.25 |
| GTX2:TXOUTCLK_CTRL | 28.28.24 | 28.29.24 | 28.28.25 |
| GTX3:TXOUTCLK_CTRL | 38.28.24 | 38.29.24 | 38.28.25 |
| TXOUTCLKPCS | 0 | 0 | 0 |
| TXPLLREFCLK_DIV2 | 0 | 0 | 1 |
| TXOUTCLKPMA_DIV2 | 0 | 1 | 0 |
| OFF_HIGH | 0 | 1 | 1 |
| TXOUTCLKPMA_DIV1 | 1 | 0 | 0 |
| OFF_LOW | 1 | 0 | 1 |
| TXPLLREFCLK_DIV1 | 1 | 1 | 0 |
| CLKTESTSIG0 | 1 | 1 | 1 |
| GTX0:TX_CLK_SOURCE | 3.28.60 |
|---|---|
| GTX1:TX_CLK_SOURCE | 13.28.60 |
| GTX2:TX_CLK_SOURCE | 23.28.60 |
| GTX3:TX_CLK_SOURCE | 33.28.60 |
| TXPLL | 0 |
| RXPLL | 1 |
| GTX0:TX_DETECT_RX_CFG | 4.29.14 | 4.28.14 | 4.29.13 | 4.28.13 | 4.29.12 | 4.28.12 | 4.29.11 | 4.28.11 | 4.29.10 | 4.28.10 | 4.29.9 | 4.28.9 | 4.29.8 | 4.28.8 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GTX1:TX_DETECT_RX_CFG | 14.29.14 | 14.28.14 | 14.29.13 | 14.28.13 | 14.29.12 | 14.28.12 | 14.29.11 | 14.28.11 | 14.29.10 | 14.28.10 | 14.29.9 | 14.28.9 | 14.29.8 | 14.28.8 |
| GTX2:TX_DETECT_RX_CFG | 24.29.14 | 24.28.14 | 24.29.13 | 24.28.13 | 24.29.12 | 24.28.12 | 24.29.11 | 24.28.11 | 24.29.10 | 24.28.10 | 24.29.9 | 24.28.9 | 24.29.8 | 24.28.8 |
| GTX3:TX_DETECT_RX_CFG | 34.29.14 | 34.28.14 | 34.29.13 | 34.28.13 | 34.29.12 | 34.28.12 | 34.29.11 | 34.28.11 | 34.29.10 | 34.28.10 | 34.29.9 | 34.28.9 | 34.29.8 | 34.28.8 |
| non-inverted | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| GTX0:TX_DRIVE_MODE | 7.29.39 |
|---|---|
| GTX1:TX_DRIVE_MODE | 17.29.39 |
| GTX2:TX_DRIVE_MODE | 27.29.39 |
| GTX3:TX_DRIVE_MODE | 37.29.39 |
| DIRECT | 0 |
| PIPE | 1 |
| GTX0:TX_XCLK_SEL | 5.28.63 |
|---|---|
| GTX1:TX_XCLK_SEL | 15.28.63 |
| GTX2:TX_XCLK_SEL | 25.28.63 |
| GTX3:TX_XCLK_SEL | 35.28.63 |
| TXOUT | 0 |
| TXUSR | 1 |
| HCLK_GTX:MUX.NORTHREFCLKOUT0 | 34.29.16 | 34.28.16 |
|---|---|---|
| NONE | 0 | 0 |
| NORTHREFCLKIN0 | 0 | 1 |
| MGTREFCLKOUT0 | 1 | 0 |
| MGTREFCLKOUT1 | 1 | 1 |
| HCLK_GTX:MUX.NORTHREFCLKOUT1 | 34.28.18 | 34.29.17 |
|---|---|---|
| NONE | 0 | 0 |
| NORTHREFCLKIN1 | 0 | 1 |
| MGTREFCLKOUT0 | 1 | 0 |
| MGTREFCLKOUT1 | 1 | 1 |
| HCLK_GTX:MUX.PERFCLK | 14.29.22 | 14.28.22 | 14.28.23 |
|---|---|---|---|
| NONE | 0 | 0 | 0 |
| PERF0 | 0 | 0 | 1 |
| PERF1 | 0 | 1 | 1 |
| PERF2 | 1 | 0 | 1 |
| PERF3 | 1 | 1 | 1 |
| HCLK_GTX:MUX.SOUTHREFCLKOUT0 | 34.29.19 | 34.28.19 |
|---|---|---|
| NONE | 0 | 0 |
| SOUTHREFCLKIN0 | 0 | 1 |
| MGTREFCLKIN0 | 1 | 0 |
| MGTREFCLKIN1 | 1 | 1 |
| HCLK_GTX:MUX.SOUTHREFCLKOUT1 | 34.28.21 | 34.29.20 |
|---|---|---|
| NONE | 0 | 0 |
| SOUTHREFCLKIN1 | 0 | 1 |
| MGTREFCLKIN0 | 1 | 0 |
| MGTREFCLKIN1 | 1 | 1 |