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Global buffers

Tile CLK_BUFG_S

Cells: 4

Switchbox SPEC_INT

virtex7 CLK_BUFG_S switchbox SPEC_INT programmable buffers
DestinationSourceBit
CELL[0].OUT_BEL[0]CELL[0].IMUX_BUFG_O[1]MAIN[0][26][10]
CELL[0].OUT_BEL[1]CELL[0].IMUX_BUFG_O[3]MAIN[0][26][26]
CELL[0].OUT_BEL[2]CELL[0].IMUX_BUFG_O[5]MAIN[0][26][42]
CELL[0].OUT_BEL[3]CELL[0].IMUX_BUFG_O[7]MAIN[0][26][58]
CELL[0].OUT_BEL[4]CELL[0].IMUX_BUFG_O[0]MAIN[0][27][9]
CELL[0].OUT_BEL[5]CELL[0].IMUX_BUFG_O[2]MAIN[0][27][25]
CELL[0].OUT_BEL[6]CELL[0].IMUX_BUFG_O[4]MAIN[0][27][41]
CELL[0].OUT_BEL[7]CELL[0].IMUX_BUFG_O[6]MAIN[0][27][57]
CELL[0].GCLK[0]CELL[0].OUT_BUFG[0]MAIN[0][27][14]
CELL[0].GCLK[1]CELL[0].OUT_BUFG[1]MAIN[0][27][30]
CELL[0].GCLK[2]CELL[0].OUT_BUFG[2]MAIN[0][27][46]
CELL[0].GCLK[3]CELL[0].OUT_BUFG[3]MAIN[0][27][62]
CELL[0].GCLK[4]CELL[0].OUT_BUFG[4]MAIN[1][27][14]
CELL[0].GCLK[5]CELL[0].OUT_BUFG[5]MAIN[1][27][30]
CELL[0].GCLK[6]CELL[0].OUT_BUFG[6]MAIN[1][27][46]
CELL[0].GCLK[7]CELL[0].OUT_BUFG[7]MAIN[1][27][62]
CELL[0].GCLK[8]CELL[0].OUT_BUFG[8]MAIN[2][27][14]
CELL[0].GCLK[9]CELL[0].OUT_BUFG[9]MAIN[2][27][30]
CELL[0].GCLK[10]CELL[0].OUT_BUFG[10]MAIN[2][27][46]
CELL[0].GCLK[11]CELL[0].OUT_BUFG[11]MAIN[2][27][62]
CELL[0].GCLK[12]CELL[0].OUT_BUFG[12]MAIN[3][27][14]
CELL[0].GCLK[13]CELL[0].OUT_BUFG[13]MAIN[3][27][30]
CELL[0].GCLK[14]CELL[0].OUT_BUFG[14]MAIN[3][27][46]
CELL[0].GCLK[15]CELL[0].OUT_BUFG[15]MAIN[3][27][62]
CELL[0].OUT_BUFG_GFB[0]CELL[0].OUT_BUFG[0]MAIN[0][26][14]
CELL[0].OUT_BUFG_GFB[1]CELL[0].OUT_BUFG[1]MAIN[0][26][30]
CELL[0].OUT_BUFG_GFB[2]CELL[0].OUT_BUFG[2]MAIN[0][26][46]
CELL[0].OUT_BUFG_GFB[3]CELL[0].OUT_BUFG[3]MAIN[0][26][62]
CELL[0].OUT_BUFG_GFB[4]CELL[0].OUT_BUFG[4]MAIN[1][26][14]
CELL[0].OUT_BUFG_GFB[5]CELL[0].OUT_BUFG[5]MAIN[1][26][30]
CELL[0].OUT_BUFG_GFB[6]CELL[0].OUT_BUFG[6]MAIN[1][26][46]
CELL[0].OUT_BUFG_GFB[7]CELL[0].OUT_BUFG[7]MAIN[1][26][62]
CELL[0].OUT_BUFG_GFB[8]CELL[0].OUT_BUFG[8]MAIN[2][26][14]
CELL[0].OUT_BUFG_GFB[9]CELL[0].OUT_BUFG[9]MAIN[2][26][30]
CELL[0].OUT_BUFG_GFB[10]CELL[0].OUT_BUFG[10]MAIN[2][26][46]
CELL[0].OUT_BUFG_GFB[11]CELL[0].OUT_BUFG[11]MAIN[2][26][62]
CELL[0].OUT_BUFG_GFB[12]CELL[0].OUT_BUFG[12]MAIN[3][26][14]
CELL[0].OUT_BUFG_GFB[13]CELL[0].OUT_BUFG[13]MAIN[3][26][30]
CELL[0].OUT_BUFG_GFB[14]CELL[0].OUT_BUFG[14]MAIN[3][26][46]
CELL[0].OUT_BUFG_GFB[15]CELL[0].OUT_BUFG[15]MAIN[3][26][62]
CELL[1].OUT_BEL[0]CELL[0].IMUX_BUFG_O[9]MAIN[1][26][10]
CELL[1].OUT_BEL[1]CELL[0].IMUX_BUFG_O[11]MAIN[1][26][26]
CELL[1].OUT_BEL[2]CELL[0].IMUX_BUFG_O[13]MAIN[1][26][42]
CELL[1].OUT_BEL[3]CELL[0].IMUX_BUFG_O[15]MAIN[1][26][58]
CELL[1].OUT_BEL[4]CELL[0].IMUX_BUFG_O[8]MAIN[1][27][9]
CELL[1].OUT_BEL[5]CELL[0].IMUX_BUFG_O[10]MAIN[1][27][25]
CELL[1].OUT_BEL[6]CELL[0].IMUX_BUFG_O[12]MAIN[1][27][41]
CELL[1].OUT_BEL[7]CELL[0].IMUX_BUFG_O[14]MAIN[1][27][57]
CELL[2].OUT_BEL[0]CELL[0].IMUX_BUFG_O[17]MAIN[2][26][10]
CELL[2].OUT_BEL[1]CELL[0].IMUX_BUFG_O[19]MAIN[2][26][26]
CELL[2].OUT_BEL[2]CELL[0].IMUX_BUFG_O[21]MAIN[2][26][42]
CELL[2].OUT_BEL[3]CELL[0].IMUX_BUFG_O[23]MAIN[2][26][58]
CELL[2].OUT_BEL[4]CELL[0].IMUX_BUFG_O[16]MAIN[2][27][9]
CELL[2].OUT_BEL[5]CELL[0].IMUX_BUFG_O[18]MAIN[2][27][25]
CELL[2].OUT_BEL[6]CELL[0].IMUX_BUFG_O[20]MAIN[2][27][41]
CELL[2].OUT_BEL[7]CELL[0].IMUX_BUFG_O[22]MAIN[2][27][57]
CELL[3].OUT_BEL[0]CELL[0].IMUX_BUFG_O[25]MAIN[3][26][10]
CELL[3].OUT_BEL[1]CELL[0].IMUX_BUFG_O[27]MAIN[3][26][26]
CELL[3].OUT_BEL[2]CELL[0].IMUX_BUFG_O[29]MAIN[3][26][42]
CELL[3].OUT_BEL[3]CELL[0].IMUX_BUFG_O[31]MAIN[3][26][58]
CELL[3].OUT_BEL[4]CELL[0].IMUX_BUFG_O[24]MAIN[3][27][9]
CELL[3].OUT_BEL[5]CELL[0].IMUX_BUFG_O[26]MAIN[3][27][25]
CELL[3].OUT_BEL[6]CELL[0].IMUX_BUFG_O[28]MAIN[3][27][41]
CELL[3].OUT_BEL[7]CELL[0].IMUX_BUFG_O[30]MAIN[3][27][57]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[0]
BitsDestination
MAIN[0][26][8]MAIN[0][26][7]MAIN[0][27][6]CELL[0].IMUX_BUFG_O[0]
Source
000CELL[0].IMUX_IMUX[28]
001CELL[0].IMUX_IMUX[24]
010CELL[0].OUT_BUFG_GFB[15]
011CELL[0].OUT_BUFG_GFB[1]
100CELL[0].IMUX_BUFG_I[0]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[1]
BitsDestination
MAIN[0][26][4]MAIN[0][27][5]MAIN[0][26][5]CELL[0].IMUX_BUFG_O[1]
Source
000CELL[0].IMUX_IMUX[28]
001CELL[0].IMUX_IMUX[24]
010CELL[0].OUT_BUFG_GFB[15]
011CELL[0].OUT_BUFG_GFB[1]
100CELL[0].IMUX_BUFG_I[1]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[2]
BitsDestination
MAIN[0][26][24]MAIN[0][26][23]MAIN[0][27][22]CELL[0].IMUX_BUFG_O[2]
Source
000CELL[0].IMUX_IMUX[29]
001CELL[0].IMUX_IMUX[25]
010CELL[0].OUT_BUFG_GFB[0]
011CELL[0].OUT_BUFG_GFB[2]
100CELL[0].IMUX_BUFG_I[2]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[3]
BitsDestination
MAIN[0][26][20]MAIN[0][27][21]MAIN[0][26][21]CELL[0].IMUX_BUFG_O[3]
Source
000CELL[0].IMUX_IMUX[29]
001CELL[0].IMUX_IMUX[25]
010CELL[0].OUT_BUFG_GFB[0]
011CELL[0].OUT_BUFG_GFB[2]
100CELL[0].IMUX_BUFG_I[3]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[4]
BitsDestination
MAIN[0][26][40]MAIN[0][26][39]MAIN[0][27][38]CELL[0].IMUX_BUFG_O[4]
Source
000CELL[0].IMUX_IMUX[30]
001CELL[0].IMUX_IMUX[26]
010CELL[0].OUT_BUFG_GFB[1]
011CELL[0].OUT_BUFG_GFB[3]
100CELL[0].IMUX_BUFG_I[4]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[5]
BitsDestination
MAIN[0][26][36]MAIN[0][27][37]MAIN[0][26][37]CELL[0].IMUX_BUFG_O[5]
Source
000CELL[0].IMUX_IMUX[30]
001CELL[0].IMUX_IMUX[26]
010CELL[0].OUT_BUFG_GFB[1]
011CELL[0].OUT_BUFG_GFB[3]
100CELL[0].IMUX_BUFG_I[5]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[6]
BitsDestination
MAIN[0][26][56]MAIN[0][26][55]MAIN[0][27][54]CELL[0].IMUX_BUFG_O[6]
Source
000CELL[0].IMUX_IMUX[31]
001CELL[0].IMUX_IMUX[27]
010CELL[0].OUT_BUFG_GFB[2]
011CELL[0].OUT_BUFG_GFB[4]
100CELL[0].IMUX_BUFG_I[6]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[7]
BitsDestination
MAIN[0][26][52]MAIN[0][27][53]MAIN[0][26][53]CELL[0].IMUX_BUFG_O[7]
Source
000CELL[0].IMUX_IMUX[31]
001CELL[0].IMUX_IMUX[27]
010CELL[0].OUT_BUFG_GFB[2]
011CELL[0].OUT_BUFG_GFB[4]
100CELL[0].IMUX_BUFG_I[7]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[8]
BitsDestination
MAIN[1][26][8]MAIN[1][27][6]MAIN[1][26][7]CELL[0].IMUX_BUFG_O[8]
Source
000CELL[1].IMUX_IMUX[28]
001CELL[0].OUT_BUFG_GFB[3]
010CELL[1].IMUX_IMUX[24]
011CELL[0].OUT_BUFG_GFB[5]
100CELL[0].IMUX_BUFG_I[8]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[9]
BitsDestination
MAIN[1][26][4]MAIN[1][26][5]MAIN[1][27][5]CELL[0].IMUX_BUFG_O[9]
Source
000CELL[1].IMUX_IMUX[28]
001CELL[0].OUT_BUFG_GFB[3]
010CELL[1].IMUX_IMUX[24]
011CELL[0].OUT_BUFG_GFB[5]
100CELL[0].IMUX_BUFG_I[9]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[10]
BitsDestination
MAIN[1][26][24]MAIN[1][27][22]MAIN[1][26][23]CELL[0].IMUX_BUFG_O[10]
Source
000CELL[1].IMUX_IMUX[29]
001CELL[0].OUT_BUFG_GFB[4]
010CELL[1].IMUX_IMUX[25]
011CELL[0].OUT_BUFG_GFB[6]
100CELL[0].IMUX_BUFG_I[10]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[11]
BitsDestination
MAIN[1][26][20]MAIN[1][26][21]MAIN[1][27][21]CELL[0].IMUX_BUFG_O[11]
Source
000CELL[1].IMUX_IMUX[29]
001CELL[0].OUT_BUFG_GFB[4]
010CELL[1].IMUX_IMUX[25]
011CELL[0].OUT_BUFG_GFB[6]
100CELL[0].IMUX_BUFG_I[11]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[12]
BitsDestination
MAIN[1][26][40]MAIN[1][27][38]MAIN[1][26][39]CELL[0].IMUX_BUFG_O[12]
Source
000CELL[1].IMUX_IMUX[30]
001CELL[0].OUT_BUFG_GFB[5]
010CELL[1].IMUX_IMUX[26]
011CELL[0].OUT_BUFG_GFB[7]
100CELL[0].IMUX_BUFG_I[12]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[13]
BitsDestination
MAIN[1][26][36]MAIN[1][26][37]MAIN[1][27][37]CELL[0].IMUX_BUFG_O[13]
Source
000CELL[1].IMUX_IMUX[30]
001CELL[0].OUT_BUFG_GFB[5]
010CELL[1].IMUX_IMUX[26]
011CELL[0].OUT_BUFG_GFB[7]
100CELL[0].IMUX_BUFG_I[13]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[14]
BitsDestination
MAIN[1][26][56]MAIN[1][27][54]MAIN[1][26][55]CELL[0].IMUX_BUFG_O[14]
Source
000CELL[1].IMUX_IMUX[31]
001CELL[0].OUT_BUFG_GFB[6]
010CELL[1].IMUX_IMUX[27]
011CELL[0].OUT_BUFG_GFB[8]
100CELL[0].IMUX_BUFG_I[14]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[15]
BitsDestination
MAIN[1][26][52]MAIN[1][26][53]MAIN[1][27][53]CELL[0].IMUX_BUFG_O[15]
Source
000CELL[1].IMUX_IMUX[31]
001CELL[0].OUT_BUFG_GFB[6]
010CELL[1].IMUX_IMUX[27]
011CELL[0].OUT_BUFG_GFB[8]
100CELL[0].IMUX_BUFG_I[15]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[16]
BitsDestination
MAIN[2][26][8]MAIN[2][27][6]MAIN[2][26][7]CELL[0].IMUX_BUFG_O[16]
Source
000CELL[2].IMUX_IMUX[28]
001CELL[0].OUT_BUFG_GFB[7]
010CELL[2].IMUX_IMUX[24]
011CELL[0].OUT_BUFG_GFB[9]
100CELL[0].IMUX_BUFG_I[16]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[17]
BitsDestination
MAIN[2][26][4]MAIN[2][26][5]MAIN[2][27][5]CELL[0].IMUX_BUFG_O[17]
Source
000CELL[2].IMUX_IMUX[28]
001CELL[0].OUT_BUFG_GFB[7]
010CELL[2].IMUX_IMUX[24]
011CELL[0].OUT_BUFG_GFB[9]
100CELL[0].IMUX_BUFG_I[17]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[18]
BitsDestination
MAIN[2][26][24]MAIN[2][27][22]MAIN[2][26][23]CELL[0].IMUX_BUFG_O[18]
Source
000CELL[2].IMUX_IMUX[29]
001CELL[0].OUT_BUFG_GFB[8]
010CELL[2].IMUX_IMUX[25]
011CELL[0].OUT_BUFG_GFB[10]
100CELL[0].IMUX_BUFG_I[18]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[19]
BitsDestination
MAIN[2][26][20]MAIN[2][26][21]MAIN[2][27][21]CELL[0].IMUX_BUFG_O[19]
Source
000CELL[2].IMUX_IMUX[29]
001CELL[0].OUT_BUFG_GFB[8]
010CELL[2].IMUX_IMUX[25]
011CELL[0].OUT_BUFG_GFB[10]
100CELL[0].IMUX_BUFG_I[19]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[20]
BitsDestination
MAIN[2][26][40]MAIN[2][27][38]MAIN[2][26][39]CELL[0].IMUX_BUFG_O[20]
Source
000CELL[2].IMUX_IMUX[30]
001CELL[0].OUT_BUFG_GFB[9]
010CELL[2].IMUX_IMUX[26]
011CELL[0].OUT_BUFG_GFB[11]
100CELL[0].IMUX_BUFG_I[20]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[21]
BitsDestination
MAIN[2][26][36]MAIN[2][26][37]MAIN[2][27][37]CELL[0].IMUX_BUFG_O[21]
Source
000CELL[2].IMUX_IMUX[30]
001CELL[0].OUT_BUFG_GFB[9]
010CELL[2].IMUX_IMUX[26]
011CELL[0].OUT_BUFG_GFB[11]
100CELL[0].IMUX_BUFG_I[21]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[22]
BitsDestination
MAIN[2][26][56]MAIN[2][27][54]MAIN[2][26][55]CELL[0].IMUX_BUFG_O[22]
Source
000CELL[2].IMUX_IMUX[31]
001CELL[0].OUT_BUFG_GFB[10]
010CELL[2].IMUX_IMUX[27]
011CELL[0].OUT_BUFG_GFB[12]
100CELL[0].IMUX_BUFG_I[22]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[23]
BitsDestination
MAIN[2][26][52]MAIN[2][26][53]MAIN[2][27][53]CELL[0].IMUX_BUFG_O[23]
Source
000CELL[2].IMUX_IMUX[31]
001CELL[0].OUT_BUFG_GFB[10]
010CELL[2].IMUX_IMUX[27]
011CELL[0].OUT_BUFG_GFB[12]
100CELL[0].IMUX_BUFG_I[23]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[24]
BitsDestination
MAIN[3][26][8]MAIN[3][27][6]MAIN[3][26][7]CELL[0].IMUX_BUFG_O[24]
Source
000CELL[3].IMUX_IMUX[28]
001CELL[0].OUT_BUFG_GFB[11]
010CELL[3].IMUX_IMUX[24]
011CELL[0].OUT_BUFG_GFB[13]
100CELL[0].IMUX_BUFG_I[24]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[25]
BitsDestination
MAIN[3][26][4]MAIN[3][26][5]MAIN[3][27][5]CELL[0].IMUX_BUFG_O[25]
Source
000CELL[3].IMUX_IMUX[28]
001CELL[0].OUT_BUFG_GFB[11]
010CELL[3].IMUX_IMUX[24]
011CELL[0].OUT_BUFG_GFB[13]
100CELL[0].IMUX_BUFG_I[25]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[26]
BitsDestination
MAIN[3][26][24]MAIN[3][27][22]MAIN[3][26][23]CELL[0].IMUX_BUFG_O[26]
Source
000CELL[3].IMUX_IMUX[29]
001CELL[0].OUT_BUFG_GFB[12]
010CELL[3].IMUX_IMUX[25]
011CELL[0].OUT_BUFG_GFB[14]
100CELL[0].IMUX_BUFG_I[26]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[27]
BitsDestination
MAIN[3][26][20]MAIN[3][26][21]MAIN[3][27][21]CELL[0].IMUX_BUFG_O[27]
Source
000CELL[3].IMUX_IMUX[29]
001CELL[0].OUT_BUFG_GFB[12]
010CELL[3].IMUX_IMUX[25]
011CELL[0].OUT_BUFG_GFB[14]
100CELL[0].IMUX_BUFG_I[27]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[28]
BitsDestination
MAIN[3][26][40]MAIN[3][27][38]MAIN[3][26][39]CELL[0].IMUX_BUFG_O[28]
Source
000CELL[3].IMUX_IMUX[30]
001CELL[0].OUT_BUFG_GFB[13]
010CELL[3].IMUX_IMUX[26]
011CELL[0].OUT_BUFG_GFB[15]
100CELL[0].IMUX_BUFG_I[28]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[29]
BitsDestination
MAIN[3][26][36]MAIN[3][26][37]MAIN[3][27][37]CELL[0].IMUX_BUFG_O[29]
Source
000CELL[3].IMUX_IMUX[30]
001CELL[0].OUT_BUFG_GFB[13]
010CELL[3].IMUX_IMUX[26]
011CELL[0].OUT_BUFG_GFB[15]
100CELL[0].IMUX_BUFG_I[29]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[30]
BitsDestination
MAIN[3][26][56]MAIN[3][27][54]MAIN[3][26][55]CELL[0].IMUX_BUFG_O[30]
Source
000CELL[3].IMUX_IMUX[31]
001CELL[0].OUT_BUFG_GFB[14]
010CELL[3].IMUX_IMUX[27]
011CELL[0].OUT_BUFG_GFB[0]
100CELL[0].IMUX_BUFG_I[30]
virtex7 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[31]
BitsDestination
MAIN[3][26][52]MAIN[3][26][53]MAIN[3][27][53]CELL[0].IMUX_BUFG_O[31]
Source
000CELL[3].IMUX_IMUX[31]
001CELL[0].OUT_BUFG_GFB[14]
010CELL[3].IMUX_IMUX[27]
011CELL[0].OUT_BUFG_GFB[0]
100CELL[0].IMUX_BUFG_I[31]

Bels BUFGCTRL

virtex7 CLK_BUFG_S bel BUFGCTRL pins
PinDirectionBUFGCTRL[0]BUFGCTRL[1]BUFGCTRL[2]BUFGCTRL[3]BUFGCTRL[4]BUFGCTRL[5]BUFGCTRL[6]BUFGCTRL[7]BUFGCTRL[8]BUFGCTRL[9]BUFGCTRL[10]BUFGCTRL[11]BUFGCTRL[12]BUFGCTRL[13]BUFGCTRL[14]BUFGCTRL[15]
I0inCELL[0].IMUX_BUFG_O[0]CELL[0].IMUX_BUFG_O[2]CELL[0].IMUX_BUFG_O[4]CELL[0].IMUX_BUFG_O[6]CELL[0].IMUX_BUFG_O[8]CELL[0].IMUX_BUFG_O[10]CELL[0].IMUX_BUFG_O[12]CELL[0].IMUX_BUFG_O[14]CELL[0].IMUX_BUFG_O[16]CELL[0].IMUX_BUFG_O[18]CELL[0].IMUX_BUFG_O[20]CELL[0].IMUX_BUFG_O[22]CELL[0].IMUX_BUFG_O[24]CELL[0].IMUX_BUFG_O[26]CELL[0].IMUX_BUFG_O[28]CELL[0].IMUX_BUFG_O[30]
I1inCELL[0].IMUX_BUFG_O[1]CELL[0].IMUX_BUFG_O[3]CELL[0].IMUX_BUFG_O[5]CELL[0].IMUX_BUFG_O[7]CELL[0].IMUX_BUFG_O[9]CELL[0].IMUX_BUFG_O[11]CELL[0].IMUX_BUFG_O[13]CELL[0].IMUX_BUFG_O[15]CELL[0].IMUX_BUFG_O[17]CELL[0].IMUX_BUFG_O[19]CELL[0].IMUX_BUFG_O[21]CELL[0].IMUX_BUFG_O[23]CELL[0].IMUX_BUFG_O[25]CELL[0].IMUX_BUFG_O[27]CELL[0].IMUX_BUFG_O[29]CELL[0].IMUX_BUFG_O[31]
S0inCELL[0].IMUX_IMUX[4] invert by !MAIN[0][27][3]CELL[0].IMUX_IMUX[5] invert by !MAIN[0][27][19]CELL[0].IMUX_IMUX[6] invert by !MAIN[0][27][35]CELL[0].IMUX_IMUX[7] invert by !MAIN[0][27][51]CELL[1].IMUX_IMUX[4] invert by !MAIN[1][27][3]CELL[1].IMUX_IMUX[5] invert by !MAIN[1][27][19]CELL[1].IMUX_IMUX[6] invert by !MAIN[1][27][35]CELL[1].IMUX_IMUX[7] invert by !MAIN[1][27][51]CELL[2].IMUX_IMUX[4] invert by !MAIN[2][27][3]CELL[2].IMUX_IMUX[5] invert by !MAIN[2][27][19]CELL[2].IMUX_IMUX[6] invert by !MAIN[2][27][35]CELL[2].IMUX_IMUX[7] invert by !MAIN[2][27][51]CELL[3].IMUX_IMUX[4] invert by !MAIN[3][27][3]CELL[3].IMUX_IMUX[5] invert by !MAIN[3][27][19]CELL[3].IMUX_IMUX[6] invert by !MAIN[3][27][35]CELL[3].IMUX_IMUX[7] invert by !MAIN[3][27][51]
S1inCELL[0].IMUX_IMUX[0] invert by !MAIN[0][26][11]CELL[0].IMUX_IMUX[1] invert by !MAIN[0][26][27]CELL[0].IMUX_IMUX[2] invert by !MAIN[0][26][43]CELL[0].IMUX_IMUX[3] invert by !MAIN[0][26][59]CELL[1].IMUX_IMUX[0] invert by !MAIN[1][26][11]CELL[1].IMUX_IMUX[1] invert by !MAIN[1][26][27]CELL[1].IMUX_IMUX[2] invert by !MAIN[1][26][43]CELL[1].IMUX_IMUX[3] invert by !MAIN[1][26][59]CELL[2].IMUX_IMUX[0] invert by !MAIN[2][26][11]CELL[2].IMUX_IMUX[1] invert by !MAIN[2][26][27]CELL[2].IMUX_IMUX[2] invert by !MAIN[2][26][43]CELL[2].IMUX_IMUX[3] invert by !MAIN[2][26][59]CELL[3].IMUX_IMUX[0] invert by !MAIN[3][26][11]CELL[3].IMUX_IMUX[1] invert by !MAIN[3][26][27]CELL[3].IMUX_IMUX[2] invert by !MAIN[3][26][43]CELL[3].IMUX_IMUX[3] invert by !MAIN[3][26][59]
CE0inCELL[0].IMUX_IMUX[20] invert by !MAIN[0][27][2]CELL[0].IMUX_IMUX[21] invert by !MAIN[0][27][18]CELL[0].IMUX_IMUX[22] invert by !MAIN[0][27][34]CELL[0].IMUX_IMUX[23] invert by !MAIN[0][27][50]CELL[1].IMUX_IMUX[20] invert by !MAIN[1][27][2]CELL[1].IMUX_IMUX[21] invert by !MAIN[1][27][18]CELL[1].IMUX_IMUX[22] invert by !MAIN[1][27][34]CELL[1].IMUX_IMUX[23] invert by !MAIN[1][27][50]CELL[2].IMUX_IMUX[20] invert by !MAIN[2][27][2]CELL[2].IMUX_IMUX[21] invert by !MAIN[2][27][18]CELL[2].IMUX_IMUX[22] invert by !MAIN[2][27][34]CELL[2].IMUX_IMUX[23] invert by !MAIN[2][27][50]CELL[3].IMUX_IMUX[20] invert by !MAIN[3][27][2]CELL[3].IMUX_IMUX[21] invert by !MAIN[3][27][18]CELL[3].IMUX_IMUX[22] invert by !MAIN[3][27][34]CELL[3].IMUX_IMUX[23] invert by !MAIN[3][27][50]
CE1inCELL[0].IMUX_IMUX[16] invert by !MAIN[0][27][11]CELL[0].IMUX_IMUX[17] invert by !MAIN[0][27][27]CELL[0].IMUX_IMUX[18] invert by !MAIN[0][27][43]CELL[0].IMUX_IMUX[19] invert by !MAIN[0][27][59]CELL[1].IMUX_IMUX[16] invert by !MAIN[1][27][11]CELL[1].IMUX_IMUX[17] invert by !MAIN[1][27][27]CELL[1].IMUX_IMUX[18] invert by !MAIN[1][27][43]CELL[1].IMUX_IMUX[19] invert by !MAIN[1][27][59]CELL[2].IMUX_IMUX[16] invert by !MAIN[2][27][11]CELL[2].IMUX_IMUX[17] invert by !MAIN[2][27][27]CELL[2].IMUX_IMUX[18] invert by !MAIN[2][27][43]CELL[2].IMUX_IMUX[19] invert by !MAIN[2][27][59]CELL[3].IMUX_IMUX[16] invert by !MAIN[3][27][11]CELL[3].IMUX_IMUX[17] invert by !MAIN[3][27][27]CELL[3].IMUX_IMUX[18] invert by !MAIN[3][27][43]CELL[3].IMUX_IMUX[19] invert by !MAIN[3][27][59]
IGNORE0inCELL[0].IMUX_IMUX[12] invert by !MAIN[0][26][1]CELL[0].IMUX_IMUX[13] invert by !MAIN[0][26][17]CELL[0].IMUX_IMUX[14] invert by !MAIN[0][26][33]CELL[0].IMUX_IMUX[15] invert by !MAIN[0][26][49]CELL[1].IMUX_IMUX[12] invert by !MAIN[1][26][1]CELL[1].IMUX_IMUX[13] invert by !MAIN[1][26][17]CELL[1].IMUX_IMUX[14] invert by !MAIN[1][26][33]CELL[1].IMUX_IMUX[15] invert by !MAIN[1][26][49]CELL[2].IMUX_IMUX[12] invert by !MAIN[2][26][1]CELL[2].IMUX_IMUX[13] invert by !MAIN[2][26][17]CELL[2].IMUX_IMUX[14] invert by !MAIN[2][26][33]CELL[2].IMUX_IMUX[15] invert by !MAIN[2][26][49]CELL[3].IMUX_IMUX[12] invert by !MAIN[3][26][1]CELL[3].IMUX_IMUX[13] invert by !MAIN[3][26][17]CELL[3].IMUX_IMUX[14] invert by !MAIN[3][26][33]CELL[3].IMUX_IMUX[15] invert by !MAIN[3][26][49]
IGNORE1inCELL[0].IMUX_IMUX[8] invert by !MAIN[0][27][12]CELL[0].IMUX_IMUX[9] invert by !MAIN[0][27][28]CELL[0].IMUX_IMUX[10] invert by !MAIN[0][27][44]CELL[0].IMUX_IMUX[11] invert by !MAIN[0][27][60]CELL[1].IMUX_IMUX[8] invert by !MAIN[1][27][12]CELL[1].IMUX_IMUX[9] invert by !MAIN[1][27][28]CELL[1].IMUX_IMUX[10] invert by !MAIN[1][27][44]CELL[1].IMUX_IMUX[11] invert by !MAIN[1][27][60]CELL[2].IMUX_IMUX[8] invert by !MAIN[2][27][12]CELL[2].IMUX_IMUX[9] invert by !MAIN[2][27][28]CELL[2].IMUX_IMUX[10] invert by !MAIN[2][27][44]CELL[2].IMUX_IMUX[11] invert by !MAIN[2][27][60]CELL[3].IMUX_IMUX[8] invert by !MAIN[3][27][12]CELL[3].IMUX_IMUX[9] invert by !MAIN[3][27][28]CELL[3].IMUX_IMUX[10] invert by !MAIN[3][27][44]CELL[3].IMUX_IMUX[11] invert by !MAIN[3][27][60]
OoutCELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[15]
virtex7 CLK_BUFG_S bel BUFGCTRL attribute bits
AttributeBUFGCTRL[0]BUFGCTRL[1]BUFGCTRL[2]BUFGCTRL[3]BUFGCTRL[4]BUFGCTRL[5]BUFGCTRL[6]BUFGCTRL[7]BUFGCTRL[8]BUFGCTRL[9]BUFGCTRL[10]BUFGCTRL[11]BUFGCTRL[12]BUFGCTRL[13]BUFGCTRL[14]BUFGCTRL[15]
CREATE_EDGEMAIN[0][27][0]MAIN[0][27][16]MAIN[0][27][32]MAIN[0][27][48]MAIN[1][27][0]MAIN[1][27][16]MAIN[1][27][32]MAIN[1][27][48]MAIN[2][27][0]MAIN[2][27][16]MAIN[2][27][32]MAIN[2][27][48]MAIN[3][27][0]MAIN[3][27][16]MAIN[3][27][32]MAIN[3][27][48]
INIT_OUT bit 0MAIN[0][27][13]MAIN[0][27][29]MAIN[0][27][45]MAIN[0][27][61]MAIN[1][27][13]MAIN[1][27][29]MAIN[1][27][45]MAIN[1][27][61]MAIN[2][27][13]MAIN[2][27][29]MAIN[2][27][45]MAIN[2][27][61]MAIN[3][27][13]MAIN[3][27][29]MAIN[3][27][45]MAIN[3][27][61]
PRESELECT_I0!MAIN[0][26][2]!MAIN[0][26][18]!MAIN[0][26][34]!MAIN[0][26][50]!MAIN[1][26][2]!MAIN[1][26][18]!MAIN[1][26][34]!MAIN[1][26][50]!MAIN[2][26][2]!MAIN[2][26][18]!MAIN[2][26][34]!MAIN[2][26][50]!MAIN[3][26][2]!MAIN[3][26][18]!MAIN[3][26][34]!MAIN[3][26][50]
PRESELECT_I1MAIN[0][26][12]MAIN[0][26][28]MAIN[0][26][44]MAIN[0][26][60]MAIN[1][26][12]MAIN[1][26][28]MAIN[1][26][44]MAIN[1][26][60]MAIN[2][26][12]MAIN[2][26][28]MAIN[2][26][44]MAIN[2][26][60]MAIN[3][26][12]MAIN[3][26][28]MAIN[3][26][44]MAIN[3][26][60]
ENABLEMAIN[0][27][15]MAIN[0][27][31]MAIN[0][27][47]MAIN[0][27][63]MAIN[1][27][15]MAIN[1][27][31]MAIN[1][27][47]MAIN[1][27][63]MAIN[2][27][15]MAIN[2][27][31]MAIN[2][27][47]MAIN[2][27][63]MAIN[3][27][15]MAIN[3][27][31]MAIN[3][27][47]MAIN[3][27][63]

Bel wires

virtex7 CLK_BUFG_S bel wires
WirePins
CELL[0].IMUX_IMUX[0]BUFGCTRL[0].S1
CELL[0].IMUX_IMUX[1]BUFGCTRL[1].S1
CELL[0].IMUX_IMUX[2]BUFGCTRL[2].S1
CELL[0].IMUX_IMUX[3]BUFGCTRL[3].S1
CELL[0].IMUX_IMUX[4]BUFGCTRL[0].S0
CELL[0].IMUX_IMUX[5]BUFGCTRL[1].S0
CELL[0].IMUX_IMUX[6]BUFGCTRL[2].S0
CELL[0].IMUX_IMUX[7]BUFGCTRL[3].S0
CELL[0].IMUX_IMUX[8]BUFGCTRL[0].IGNORE1
CELL[0].IMUX_IMUX[9]BUFGCTRL[1].IGNORE1
CELL[0].IMUX_IMUX[10]BUFGCTRL[2].IGNORE1
CELL[0].IMUX_IMUX[11]BUFGCTRL[3].IGNORE1
CELL[0].IMUX_IMUX[12]BUFGCTRL[0].IGNORE0
CELL[0].IMUX_IMUX[13]BUFGCTRL[1].IGNORE0
CELL[0].IMUX_IMUX[14]BUFGCTRL[2].IGNORE0
CELL[0].IMUX_IMUX[15]BUFGCTRL[3].IGNORE0
CELL[0].IMUX_IMUX[16]BUFGCTRL[0].CE1
CELL[0].IMUX_IMUX[17]BUFGCTRL[1].CE1
CELL[0].IMUX_IMUX[18]BUFGCTRL[2].CE1
CELL[0].IMUX_IMUX[19]BUFGCTRL[3].CE1
CELL[0].IMUX_IMUX[20]BUFGCTRL[0].CE0
CELL[0].IMUX_IMUX[21]BUFGCTRL[1].CE0
CELL[0].IMUX_IMUX[22]BUFGCTRL[2].CE0
CELL[0].IMUX_IMUX[23]BUFGCTRL[3].CE0
CELL[0].OUT_BUFG[0]BUFGCTRL[0].O
CELL[0].OUT_BUFG[1]BUFGCTRL[1].O
CELL[0].OUT_BUFG[2]BUFGCTRL[2].O
CELL[0].OUT_BUFG[3]BUFGCTRL[3].O
CELL[0].OUT_BUFG[4]BUFGCTRL[4].O
CELL[0].OUT_BUFG[5]BUFGCTRL[5].O
CELL[0].OUT_BUFG[6]BUFGCTRL[6].O
CELL[0].OUT_BUFG[7]BUFGCTRL[7].O
CELL[0].OUT_BUFG[8]BUFGCTRL[8].O
CELL[0].OUT_BUFG[9]BUFGCTRL[9].O
CELL[0].OUT_BUFG[10]BUFGCTRL[10].O
CELL[0].OUT_BUFG[11]BUFGCTRL[11].O
CELL[0].OUT_BUFG[12]BUFGCTRL[12].O
CELL[0].OUT_BUFG[13]BUFGCTRL[13].O
CELL[0].OUT_BUFG[14]BUFGCTRL[14].O
CELL[0].OUT_BUFG[15]BUFGCTRL[15].O
CELL[0].IMUX_BUFG_O[0]BUFGCTRL[0].I0
CELL[0].IMUX_BUFG_O[1]BUFGCTRL[0].I1
CELL[0].IMUX_BUFG_O[2]BUFGCTRL[1].I0
CELL[0].IMUX_BUFG_O[3]BUFGCTRL[1].I1
CELL[0].IMUX_BUFG_O[4]BUFGCTRL[2].I0
CELL[0].IMUX_BUFG_O[5]BUFGCTRL[2].I1
CELL[0].IMUX_BUFG_O[6]BUFGCTRL[3].I0
CELL[0].IMUX_BUFG_O[7]BUFGCTRL[3].I1
CELL[0].IMUX_BUFG_O[8]BUFGCTRL[4].I0
CELL[0].IMUX_BUFG_O[9]BUFGCTRL[4].I1
CELL[0].IMUX_BUFG_O[10]BUFGCTRL[5].I0
CELL[0].IMUX_BUFG_O[11]BUFGCTRL[5].I1
CELL[0].IMUX_BUFG_O[12]BUFGCTRL[6].I0
CELL[0].IMUX_BUFG_O[13]BUFGCTRL[6].I1
CELL[0].IMUX_BUFG_O[14]BUFGCTRL[7].I0
CELL[0].IMUX_BUFG_O[15]BUFGCTRL[7].I1
CELL[0].IMUX_BUFG_O[16]BUFGCTRL[8].I0
CELL[0].IMUX_BUFG_O[17]BUFGCTRL[8].I1
CELL[0].IMUX_BUFG_O[18]BUFGCTRL[9].I0
CELL[0].IMUX_BUFG_O[19]BUFGCTRL[9].I1
CELL[0].IMUX_BUFG_O[20]BUFGCTRL[10].I0
CELL[0].IMUX_BUFG_O[21]BUFGCTRL[10].I1
CELL[0].IMUX_BUFG_O[22]BUFGCTRL[11].I0
CELL[0].IMUX_BUFG_O[23]BUFGCTRL[11].I1
CELL[0].IMUX_BUFG_O[24]BUFGCTRL[12].I0
CELL[0].IMUX_BUFG_O[25]BUFGCTRL[12].I1
CELL[0].IMUX_BUFG_O[26]BUFGCTRL[13].I0
CELL[0].IMUX_BUFG_O[27]BUFGCTRL[13].I1
CELL[0].IMUX_BUFG_O[28]BUFGCTRL[14].I0
CELL[0].IMUX_BUFG_O[29]BUFGCTRL[14].I1
CELL[0].IMUX_BUFG_O[30]BUFGCTRL[15].I0
CELL[0].IMUX_BUFG_O[31]BUFGCTRL[15].I1
CELL[1].IMUX_IMUX[0]BUFGCTRL[4].S1
CELL[1].IMUX_IMUX[1]BUFGCTRL[5].S1
CELL[1].IMUX_IMUX[2]BUFGCTRL[6].S1
CELL[1].IMUX_IMUX[3]BUFGCTRL[7].S1
CELL[1].IMUX_IMUX[4]BUFGCTRL[4].S0
CELL[1].IMUX_IMUX[5]BUFGCTRL[5].S0
CELL[1].IMUX_IMUX[6]BUFGCTRL[6].S0
CELL[1].IMUX_IMUX[7]BUFGCTRL[7].S0
CELL[1].IMUX_IMUX[8]BUFGCTRL[4].IGNORE1
CELL[1].IMUX_IMUX[9]BUFGCTRL[5].IGNORE1
CELL[1].IMUX_IMUX[10]BUFGCTRL[6].IGNORE1
CELL[1].IMUX_IMUX[11]BUFGCTRL[7].IGNORE1
CELL[1].IMUX_IMUX[12]BUFGCTRL[4].IGNORE0
CELL[1].IMUX_IMUX[13]BUFGCTRL[5].IGNORE0
CELL[1].IMUX_IMUX[14]BUFGCTRL[6].IGNORE0
CELL[1].IMUX_IMUX[15]BUFGCTRL[7].IGNORE0
CELL[1].IMUX_IMUX[16]BUFGCTRL[4].CE1
CELL[1].IMUX_IMUX[17]BUFGCTRL[5].CE1
CELL[1].IMUX_IMUX[18]BUFGCTRL[6].CE1
CELL[1].IMUX_IMUX[19]BUFGCTRL[7].CE1
CELL[1].IMUX_IMUX[20]BUFGCTRL[4].CE0
CELL[1].IMUX_IMUX[21]BUFGCTRL[5].CE0
CELL[1].IMUX_IMUX[22]BUFGCTRL[6].CE0
CELL[1].IMUX_IMUX[23]BUFGCTRL[7].CE0
CELL[2].IMUX_IMUX[0]BUFGCTRL[8].S1
CELL[2].IMUX_IMUX[1]BUFGCTRL[9].S1
CELL[2].IMUX_IMUX[2]BUFGCTRL[10].S1
CELL[2].IMUX_IMUX[3]BUFGCTRL[11].S1
CELL[2].IMUX_IMUX[4]BUFGCTRL[8].S0
CELL[2].IMUX_IMUX[5]BUFGCTRL[9].S0
CELL[2].IMUX_IMUX[6]BUFGCTRL[10].S0
CELL[2].IMUX_IMUX[7]BUFGCTRL[11].S0
CELL[2].IMUX_IMUX[8]BUFGCTRL[8].IGNORE1
CELL[2].IMUX_IMUX[9]BUFGCTRL[9].IGNORE1
CELL[2].IMUX_IMUX[10]BUFGCTRL[10].IGNORE1
CELL[2].IMUX_IMUX[11]BUFGCTRL[11].IGNORE1
CELL[2].IMUX_IMUX[12]BUFGCTRL[8].IGNORE0
CELL[2].IMUX_IMUX[13]BUFGCTRL[9].IGNORE0
CELL[2].IMUX_IMUX[14]BUFGCTRL[10].IGNORE0
CELL[2].IMUX_IMUX[15]BUFGCTRL[11].IGNORE0
CELL[2].IMUX_IMUX[16]BUFGCTRL[8].CE1
CELL[2].IMUX_IMUX[17]BUFGCTRL[9].CE1
CELL[2].IMUX_IMUX[18]BUFGCTRL[10].CE1
CELL[2].IMUX_IMUX[19]BUFGCTRL[11].CE1
CELL[2].IMUX_IMUX[20]BUFGCTRL[8].CE0
CELL[2].IMUX_IMUX[21]BUFGCTRL[9].CE0
CELL[2].IMUX_IMUX[22]BUFGCTRL[10].CE0
CELL[2].IMUX_IMUX[23]BUFGCTRL[11].CE0
CELL[3].IMUX_IMUX[0]BUFGCTRL[12].S1
CELL[3].IMUX_IMUX[1]BUFGCTRL[13].S1
CELL[3].IMUX_IMUX[2]BUFGCTRL[14].S1
CELL[3].IMUX_IMUX[3]BUFGCTRL[15].S1
CELL[3].IMUX_IMUX[4]BUFGCTRL[12].S0
CELL[3].IMUX_IMUX[5]BUFGCTRL[13].S0
CELL[3].IMUX_IMUX[6]BUFGCTRL[14].S0
CELL[3].IMUX_IMUX[7]BUFGCTRL[15].S0
CELL[3].IMUX_IMUX[8]BUFGCTRL[12].IGNORE1
CELL[3].IMUX_IMUX[9]BUFGCTRL[13].IGNORE1
CELL[3].IMUX_IMUX[10]BUFGCTRL[14].IGNORE1
CELL[3].IMUX_IMUX[11]BUFGCTRL[15].IGNORE1
CELL[3].IMUX_IMUX[12]BUFGCTRL[12].IGNORE0
CELL[3].IMUX_IMUX[13]BUFGCTRL[13].IGNORE0
CELL[3].IMUX_IMUX[14]BUFGCTRL[14].IGNORE0
CELL[3].IMUX_IMUX[15]BUFGCTRL[15].IGNORE0
CELL[3].IMUX_IMUX[16]BUFGCTRL[12].CE1
CELL[3].IMUX_IMUX[17]BUFGCTRL[13].CE1
CELL[3].IMUX_IMUX[18]BUFGCTRL[14].CE1
CELL[3].IMUX_IMUX[19]BUFGCTRL[15].CE1
CELL[3].IMUX_IMUX[20]BUFGCTRL[12].CE0
CELL[3].IMUX_IMUX[21]BUFGCTRL[13].CE0
CELL[3].IMUX_IMUX[22]BUFGCTRL[14].CE0
CELL[3].IMUX_IMUX[23]BUFGCTRL[15].CE0

Bitstream

virtex7 CLK_BUFG_S rect MAIN[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[3]: ENABLE - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[3] ← CELL[0].OUT_BUFG[3] SPEC_INT: buffer CELL[0].GCLK[3] ← CELL[0].OUT_BUFG[3] - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[3]: INIT_OUT bit 0 - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[3]: PRESELECT_I1 BUFGCTRL[3]: !invert IGNORE1 - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[3]: !invert S1 BUFGCTRL[3]: !invert CE1 - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BEL[3] ← CELL[0].IMUX_BUFG_O[7] - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BEL[7] ← CELL[0].IMUX_BUFG_O[6] - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 2 - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 1 - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 0 - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 1 - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 2 - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[3]: !invert S0 - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[3]: ! PRESELECT_I0 BUFGCTRL[3]: !invert CE0 - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[3]: !invert IGNORE0 - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[3]: CREATE_EDGE - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[2]: ENABLE - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[2] ← CELL[0].OUT_BUFG[2] SPEC_INT: buffer CELL[0].GCLK[2] ← CELL[0].OUT_BUFG[2] - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[2]: INIT_OUT bit 0 - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[2]: PRESELECT_I1 BUFGCTRL[2]: !invert IGNORE1 - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[2]: !invert S1 BUFGCTRL[2]: !invert CE1 - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BEL[2] ← CELL[0].IMUX_BUFG_O[5] - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BEL[6] ← CELL[0].IMUX_BUFG_O[4] - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 2 - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 1 - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 0 - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 1 - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 2 - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[2]: !invert S0 - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[2]: ! PRESELECT_I0 BUFGCTRL[2]: !invert CE0 - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[2]: !invert IGNORE0 - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[2]: CREATE_EDGE - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[1]: ENABLE - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[1] ← CELL[0].OUT_BUFG[1] SPEC_INT: buffer CELL[0].GCLK[1] ← CELL[0].OUT_BUFG[1] - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[1]: INIT_OUT bit 0 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[1]: PRESELECT_I1 BUFGCTRL[1]: !invert IGNORE1 - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[1]: !invert S1 BUFGCTRL[1]: !invert CE1 - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BEL[1] ← CELL[0].IMUX_BUFG_O[3] - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BEL[5] ← CELL[0].IMUX_BUFG_O[2] - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 2 - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 1 - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 0 - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 1 - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 2 - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[1]: !invert S0 - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[1]: ! PRESELECT_I0 BUFGCTRL[1]: !invert CE0 - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[1]: !invert IGNORE0 - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[1]: CREATE_EDGE - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[0]: ENABLE - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[0] ← CELL[0].OUT_BUFG[0] SPEC_INT: buffer CELL[0].GCLK[0] ← CELL[0].OUT_BUFG[0] - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[0]: INIT_OUT bit 0 - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[0]: PRESELECT_I1 BUFGCTRL[0]: !invert IGNORE1 - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[0]: !invert S1 BUFGCTRL[0]: !invert CE1 - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BEL[0] ← CELL[0].IMUX_BUFG_O[1] - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BEL[4] ← CELL[0].IMUX_BUFG_O[0] - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 2 - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 1 - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 0 - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 1 - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 2 - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[0]: !invert S0 - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[0]: ! PRESELECT_I0 BUFGCTRL[0]: !invert CE0 - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[0]: !invert IGNORE0 - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[0]: CREATE_EDGE - -
virtex7 CLK_BUFG_S rect MAIN[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[7]: ENABLE - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[7] ← CELL[0].OUT_BUFG[7] SPEC_INT: buffer CELL[0].GCLK[7] ← CELL[0].OUT_BUFG[7] - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[7]: INIT_OUT bit 0 - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[7]: PRESELECT_I1 BUFGCTRL[7]: !invert IGNORE1 - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[7]: !invert S1 BUFGCTRL[7]: !invert CE1 - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].OUT_BEL[3] ← CELL[0].IMUX_BUFG_O[15] - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].OUT_BEL[7] ← CELL[0].IMUX_BUFG_O[14] - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 2 - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 0 - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 1 - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 0 - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 2 - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[7]: !invert S0 - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[7]: ! PRESELECT_I0 BUFGCTRL[7]: !invert CE0 - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[7]: !invert IGNORE0 - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[7]: CREATE_EDGE - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[6]: ENABLE - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[6] ← CELL[0].OUT_BUFG[6] SPEC_INT: buffer CELL[0].GCLK[6] ← CELL[0].OUT_BUFG[6] - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[6]: INIT_OUT bit 0 - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[6]: PRESELECT_I1 BUFGCTRL[6]: !invert IGNORE1 - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[6]: !invert S1 BUFGCTRL[6]: !invert CE1 - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].OUT_BEL[2] ← CELL[0].IMUX_BUFG_O[13] - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].OUT_BEL[6] ← CELL[0].IMUX_BUFG_O[12] - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 2 - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 0 - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 1 - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 0 - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 2 - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[6]: !invert S0 - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[6]: ! PRESELECT_I0 BUFGCTRL[6]: !invert CE0 - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[6]: !invert IGNORE0 - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[6]: CREATE_EDGE - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[5]: ENABLE - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[5] ← CELL[0].OUT_BUFG[5] SPEC_INT: buffer CELL[0].GCLK[5] ← CELL[0].OUT_BUFG[5] - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[5]: INIT_OUT bit 0 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[5]: PRESELECT_I1 BUFGCTRL[5]: !invert IGNORE1 - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[5]: !invert S1 BUFGCTRL[5]: !invert CE1 - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].OUT_BEL[1] ← CELL[0].IMUX_BUFG_O[11] - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].OUT_BEL[5] ← CELL[0].IMUX_BUFG_O[10] - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 2 - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 0 - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 1 - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 0 - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 2 - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[5]: !invert S0 - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[5]: ! PRESELECT_I0 BUFGCTRL[5]: !invert CE0 - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[5]: !invert IGNORE0 - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[5]: CREATE_EDGE - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[4]: ENABLE - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[4] ← CELL[0].OUT_BUFG[4] SPEC_INT: buffer CELL[0].GCLK[4] ← CELL[0].OUT_BUFG[4] - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[4]: INIT_OUT bit 0 - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[4]: PRESELECT_I1 BUFGCTRL[4]: !invert IGNORE1 - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[4]: !invert S1 BUFGCTRL[4]: !invert CE1 - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].OUT_BEL[0] ← CELL[0].IMUX_BUFG_O[9] - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].OUT_BEL[4] ← CELL[0].IMUX_BUFG_O[8] - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 2 - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 0 - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 1 - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 0 - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 2 - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[4]: !invert S0 - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[4]: ! PRESELECT_I0 BUFGCTRL[4]: !invert CE0 - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[4]: !invert IGNORE0 - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[4]: CREATE_EDGE - -
virtex7 CLK_BUFG_S rect MAIN[2]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[11]: ENABLE - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[11] ← CELL[0].OUT_BUFG[11] SPEC_INT: buffer CELL[0].GCLK[11] ← CELL[0].OUT_BUFG[11] - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[11]: INIT_OUT bit 0 - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[11]: PRESELECT_I1 BUFGCTRL[11]: !invert IGNORE1 - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[11]: !invert S1 BUFGCTRL[11]: !invert CE1 - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[2].OUT_BEL[3] ← CELL[0].IMUX_BUFG_O[23] - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[2].OUT_BEL[7] ← CELL[0].IMUX_BUFG_O[22] - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 2 - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 0 - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 1 - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 0 - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 2 - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[11]: !invert S0 - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[11]: ! PRESELECT_I0 BUFGCTRL[11]: !invert CE0 - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[11]: !invert IGNORE0 - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[11]: CREATE_EDGE - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[10]: ENABLE - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[10] ← CELL[0].OUT_BUFG[10] SPEC_INT: buffer CELL[0].GCLK[10] ← CELL[0].OUT_BUFG[10] - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[10]: INIT_OUT bit 0 - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[10]: PRESELECT_I1 BUFGCTRL[10]: !invert IGNORE1 - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[10]: !invert S1 BUFGCTRL[10]: !invert CE1 - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[2].OUT_BEL[2] ← CELL[0].IMUX_BUFG_O[21] - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[2].OUT_BEL[6] ← CELL[0].IMUX_BUFG_O[20] - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 2 - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 0 - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 1 - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 0 - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 2 - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[10]: !invert S0 - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[10]: ! PRESELECT_I0 BUFGCTRL[10]: !invert CE0 - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[10]: !invert IGNORE0 - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[10]: CREATE_EDGE - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[9]: ENABLE - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[9] ← CELL[0].OUT_BUFG[9] SPEC_INT: buffer CELL[0].GCLK[9] ← CELL[0].OUT_BUFG[9] - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[9]: INIT_OUT bit 0 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[9]: PRESELECT_I1 BUFGCTRL[9]: !invert IGNORE1 - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[9]: !invert S1 BUFGCTRL[9]: !invert CE1 - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[2].OUT_BEL[1] ← CELL[0].IMUX_BUFG_O[19] - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[2].OUT_BEL[5] ← CELL[0].IMUX_BUFG_O[18] - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 2 - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 0 - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 1 - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 0 - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 2 - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[9]: !invert S0 - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[9]: ! PRESELECT_I0 BUFGCTRL[9]: !invert CE0 - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[9]: !invert IGNORE0 - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[9]: CREATE_EDGE - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[8]: ENABLE - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[8] ← CELL[0].OUT_BUFG[8] SPEC_INT: buffer CELL[0].GCLK[8] ← CELL[0].OUT_BUFG[8] - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[8]: INIT_OUT bit 0 - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[8]: PRESELECT_I1 BUFGCTRL[8]: !invert IGNORE1 - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[8]: !invert S1 BUFGCTRL[8]: !invert CE1 - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[2].OUT_BEL[0] ← CELL[0].IMUX_BUFG_O[17] - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[2].OUT_BEL[4] ← CELL[0].IMUX_BUFG_O[16] - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 2 - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 0 - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 1 - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 0 - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 2 - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[8]: !invert S0 - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[8]: ! PRESELECT_I0 BUFGCTRL[8]: !invert CE0 - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[8]: !invert IGNORE0 - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[8]: CREATE_EDGE - -
virtex7 CLK_BUFG_S rect MAIN[3]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[15]: ENABLE - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[15] ← CELL[0].OUT_BUFG[15] SPEC_INT: buffer CELL[0].GCLK[15] ← CELL[0].OUT_BUFG[15] - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[15]: INIT_OUT bit 0 - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[15]: PRESELECT_I1 BUFGCTRL[15]: !invert IGNORE1 - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[15]: !invert S1 BUFGCTRL[15]: !invert CE1 - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[3].OUT_BEL[3] ← CELL[0].IMUX_BUFG_O[31] - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[3].OUT_BEL[7] ← CELL[0].IMUX_BUFG_O[30] - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 2 - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 0 - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 1 - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 0 - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 2 - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[15]: !invert S0 - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[15]: ! PRESELECT_I0 BUFGCTRL[15]: !invert CE0 - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[15]: !invert IGNORE0 - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[15]: CREATE_EDGE - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[14]: ENABLE - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[14] ← CELL[0].OUT_BUFG[14] SPEC_INT: buffer CELL[0].GCLK[14] ← CELL[0].OUT_BUFG[14] - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[14]: INIT_OUT bit 0 - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[14]: PRESELECT_I1 BUFGCTRL[14]: !invert IGNORE1 - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[14]: !invert S1 BUFGCTRL[14]: !invert CE1 - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[3].OUT_BEL[2] ← CELL[0].IMUX_BUFG_O[29] - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[3].OUT_BEL[6] ← CELL[0].IMUX_BUFG_O[28] - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 2 - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 0 - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 1 - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 0 - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 2 - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[14]: !invert S0 - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[14]: ! PRESELECT_I0 BUFGCTRL[14]: !invert CE0 - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[14]: !invert IGNORE0 - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[14]: CREATE_EDGE - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[13]: ENABLE - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[13] ← CELL[0].OUT_BUFG[13] SPEC_INT: buffer CELL[0].GCLK[13] ← CELL[0].OUT_BUFG[13] - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[13]: INIT_OUT bit 0 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[13]: PRESELECT_I1 BUFGCTRL[13]: !invert IGNORE1 - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[13]: !invert S1 BUFGCTRL[13]: !invert CE1 - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[3].OUT_BEL[1] ← CELL[0].IMUX_BUFG_O[27] - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[3].OUT_BEL[5] ← CELL[0].IMUX_BUFG_O[26] - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 2 - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 0 - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 1 - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 0 - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 2 - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[13]: !invert S0 - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[13]: ! PRESELECT_I0 BUFGCTRL[13]: !invert CE0 - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[13]: !invert IGNORE0 - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[13]: CREATE_EDGE - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[12]: ENABLE - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[12] ← CELL[0].OUT_BUFG[12] SPEC_INT: buffer CELL[0].GCLK[12] ← CELL[0].OUT_BUFG[12] - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[12]: INIT_OUT bit 0 - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[12]: PRESELECT_I1 BUFGCTRL[12]: !invert IGNORE1 - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[12]: !invert S1 BUFGCTRL[12]: !invert CE1 - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[3].OUT_BEL[0] ← CELL[0].IMUX_BUFG_O[25] - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[3].OUT_BEL[4] ← CELL[0].IMUX_BUFG_O[24] - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 2 - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 0 - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 1 - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 0 - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 2 - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[12]: !invert S0 - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[12]: ! PRESELECT_I0 BUFGCTRL[12]: !invert CE0 - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[12]: !invert IGNORE0 - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[12]: CREATE_EDGE - -

Tile CLK_BUFG_N

Cells: 4

Switchbox SPEC_INT

virtex7 CLK_BUFG_N switchbox SPEC_INT programmable buffers
DestinationSourceBit
CELL[0].OUT_BEL[0]CELL[0].IMUX_BUFG_O[1]MAIN[0][26][10]
CELL[0].OUT_BEL[1]CELL[0].IMUX_BUFG_O[3]MAIN[0][26][26]
CELL[0].OUT_BEL[2]CELL[0].IMUX_BUFG_O[5]MAIN[0][26][42]
CELL[0].OUT_BEL[3]CELL[0].IMUX_BUFG_O[7]MAIN[0][26][58]
CELL[0].OUT_BEL[4]CELL[0].IMUX_BUFG_O[0]MAIN[0][27][9]
CELL[0].OUT_BEL[5]CELL[0].IMUX_BUFG_O[2]MAIN[0][27][25]
CELL[0].OUT_BEL[6]CELL[0].IMUX_BUFG_O[4]MAIN[0][27][41]
CELL[0].OUT_BEL[7]CELL[0].IMUX_BUFG_O[6]MAIN[0][27][57]
CELL[0].GCLK[16]CELL[0].OUT_BUFG[0]MAIN[0][27][14]
CELL[0].GCLK[17]CELL[0].OUT_BUFG[1]MAIN[0][27][30]
CELL[0].GCLK[18]CELL[0].OUT_BUFG[2]MAIN[0][27][46]
CELL[0].GCLK[19]CELL[0].OUT_BUFG[3]MAIN[0][27][62]
CELL[0].GCLK[20]CELL[0].OUT_BUFG[4]MAIN[1][27][14]
CELL[0].GCLK[21]CELL[0].OUT_BUFG[5]MAIN[1][27][30]
CELL[0].GCLK[22]CELL[0].OUT_BUFG[6]MAIN[1][27][46]
CELL[0].GCLK[23]CELL[0].OUT_BUFG[7]MAIN[1][27][62]
CELL[0].GCLK[24]CELL[0].OUT_BUFG[8]MAIN[2][27][14]
CELL[0].GCLK[25]CELL[0].OUT_BUFG[9]MAIN[2][27][30]
CELL[0].GCLK[26]CELL[0].OUT_BUFG[10]MAIN[2][27][46]
CELL[0].GCLK[27]CELL[0].OUT_BUFG[11]MAIN[2][27][62]
CELL[0].GCLK[28]CELL[0].OUT_BUFG[12]MAIN[3][27][14]
CELL[0].GCLK[29]CELL[0].OUT_BUFG[13]MAIN[3][27][30]
CELL[0].GCLK[30]CELL[0].OUT_BUFG[14]MAIN[3][27][46]
CELL[0].GCLK[31]CELL[0].OUT_BUFG[15]MAIN[3][27][62]
CELL[0].OUT_BUFG_GFB[0]CELL[0].OUT_BUFG[0]MAIN[0][26][14]
CELL[0].OUT_BUFG_GFB[1]CELL[0].OUT_BUFG[1]MAIN[0][26][30]
CELL[0].OUT_BUFG_GFB[2]CELL[0].OUT_BUFG[2]MAIN[0][26][46]
CELL[0].OUT_BUFG_GFB[3]CELL[0].OUT_BUFG[3]MAIN[0][26][62]
CELL[0].OUT_BUFG_GFB[4]CELL[0].OUT_BUFG[4]MAIN[1][26][14]
CELL[0].OUT_BUFG_GFB[5]CELL[0].OUT_BUFG[5]MAIN[1][26][30]
CELL[0].OUT_BUFG_GFB[6]CELL[0].OUT_BUFG[6]MAIN[1][26][46]
CELL[0].OUT_BUFG_GFB[7]CELL[0].OUT_BUFG[7]MAIN[1][26][62]
CELL[0].OUT_BUFG_GFB[8]CELL[0].OUT_BUFG[8]MAIN[2][26][14]
CELL[0].OUT_BUFG_GFB[9]CELL[0].OUT_BUFG[9]MAIN[2][26][30]
CELL[0].OUT_BUFG_GFB[10]CELL[0].OUT_BUFG[10]MAIN[2][26][46]
CELL[0].OUT_BUFG_GFB[11]CELL[0].OUT_BUFG[11]MAIN[2][26][62]
CELL[0].OUT_BUFG_GFB[12]CELL[0].OUT_BUFG[12]MAIN[3][26][14]
CELL[0].OUT_BUFG_GFB[13]CELL[0].OUT_BUFG[13]MAIN[3][26][30]
CELL[0].OUT_BUFG_GFB[14]CELL[0].OUT_BUFG[14]MAIN[3][26][46]
CELL[0].OUT_BUFG_GFB[15]CELL[0].OUT_BUFG[15]MAIN[3][26][62]
CELL[1].OUT_BEL[0]CELL[0].IMUX_BUFG_O[9]MAIN[1][26][10]
CELL[1].OUT_BEL[1]CELL[0].IMUX_BUFG_O[11]MAIN[1][26][26]
CELL[1].OUT_BEL[2]CELL[0].IMUX_BUFG_O[13]MAIN[1][26][42]
CELL[1].OUT_BEL[3]CELL[0].IMUX_BUFG_O[15]MAIN[1][26][58]
CELL[1].OUT_BEL[4]CELL[0].IMUX_BUFG_O[8]MAIN[1][27][9]
CELL[1].OUT_BEL[5]CELL[0].IMUX_BUFG_O[10]MAIN[1][27][25]
CELL[1].OUT_BEL[6]CELL[0].IMUX_BUFG_O[12]MAIN[1][27][41]
CELL[1].OUT_BEL[7]CELL[0].IMUX_BUFG_O[14]MAIN[1][27][57]
CELL[2].OUT_BEL[0]CELL[0].IMUX_BUFG_O[17]MAIN[2][26][10]
CELL[2].OUT_BEL[1]CELL[0].IMUX_BUFG_O[19]MAIN[2][26][26]
CELL[2].OUT_BEL[2]CELL[0].IMUX_BUFG_O[21]MAIN[2][26][42]
CELL[2].OUT_BEL[3]CELL[0].IMUX_BUFG_O[23]MAIN[2][26][58]
CELL[2].OUT_BEL[4]CELL[0].IMUX_BUFG_O[16]MAIN[2][27][9]
CELL[2].OUT_BEL[5]CELL[0].IMUX_BUFG_O[18]MAIN[2][27][25]
CELL[2].OUT_BEL[6]CELL[0].IMUX_BUFG_O[20]MAIN[2][27][41]
CELL[2].OUT_BEL[7]CELL[0].IMUX_BUFG_O[22]MAIN[2][27][57]
CELL[3].OUT_BEL[0]CELL[0].IMUX_BUFG_O[25]MAIN[3][26][10]
CELL[3].OUT_BEL[1]CELL[0].IMUX_BUFG_O[27]MAIN[3][26][26]
CELL[3].OUT_BEL[2]CELL[0].IMUX_BUFG_O[29]MAIN[3][26][42]
CELL[3].OUT_BEL[3]CELL[0].IMUX_BUFG_O[31]MAIN[3][26][58]
CELL[3].OUT_BEL[4]CELL[0].IMUX_BUFG_O[24]MAIN[3][27][9]
CELL[3].OUT_BEL[5]CELL[0].IMUX_BUFG_O[26]MAIN[3][27][25]
CELL[3].OUT_BEL[6]CELL[0].IMUX_BUFG_O[28]MAIN[3][27][41]
CELL[3].OUT_BEL[7]CELL[0].IMUX_BUFG_O[30]MAIN[3][27][57]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[0]
BitsDestination
MAIN[0][26][8]MAIN[0][26][7]MAIN[0][27][6]CELL[0].IMUX_BUFG_O[0]
Source
000CELL[0].IMUX_IMUX[28]
001CELL[0].IMUX_IMUX[24]
010CELL[0].OUT_BUFG_GFB[15]
011CELL[0].OUT_BUFG_GFB[1]
100CELL[0].IMUX_BUFG_I[0]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[1]
BitsDestination
MAIN[0][26][4]MAIN[0][27][5]MAIN[0][26][5]CELL[0].IMUX_BUFG_O[1]
Source
000CELL[0].IMUX_IMUX[28]
001CELL[0].IMUX_IMUX[24]
010CELL[0].OUT_BUFG_GFB[15]
011CELL[0].OUT_BUFG_GFB[1]
100CELL[0].IMUX_BUFG_I[1]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[2]
BitsDestination
MAIN[0][26][24]MAIN[0][26][23]MAIN[0][27][22]CELL[0].IMUX_BUFG_O[2]
Source
000CELL[0].IMUX_IMUX[29]
001CELL[0].IMUX_IMUX[25]
010CELL[0].OUT_BUFG_GFB[0]
011CELL[0].OUT_BUFG_GFB[2]
100CELL[0].IMUX_BUFG_I[2]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[3]
BitsDestination
MAIN[0][26][20]MAIN[0][27][21]MAIN[0][26][21]CELL[0].IMUX_BUFG_O[3]
Source
000CELL[0].IMUX_IMUX[29]
001CELL[0].IMUX_IMUX[25]
010CELL[0].OUT_BUFG_GFB[0]
011CELL[0].OUT_BUFG_GFB[2]
100CELL[0].IMUX_BUFG_I[3]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[4]
BitsDestination
MAIN[0][26][40]MAIN[0][26][39]MAIN[0][27][38]CELL[0].IMUX_BUFG_O[4]
Source
000CELL[0].IMUX_IMUX[30]
001CELL[0].IMUX_IMUX[26]
010CELL[0].OUT_BUFG_GFB[1]
011CELL[0].OUT_BUFG_GFB[3]
100CELL[0].IMUX_BUFG_I[4]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[5]
BitsDestination
MAIN[0][26][36]MAIN[0][27][37]MAIN[0][26][37]CELL[0].IMUX_BUFG_O[5]
Source
000CELL[0].IMUX_IMUX[30]
001CELL[0].IMUX_IMUX[26]
010CELL[0].OUT_BUFG_GFB[1]
011CELL[0].OUT_BUFG_GFB[3]
100CELL[0].IMUX_BUFG_I[5]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[6]
BitsDestination
MAIN[0][26][56]MAIN[0][26][55]MAIN[0][27][54]CELL[0].IMUX_BUFG_O[6]
Source
000CELL[0].IMUX_IMUX[31]
001CELL[0].IMUX_IMUX[27]
010CELL[0].OUT_BUFG_GFB[2]
011CELL[0].OUT_BUFG_GFB[4]
100CELL[0].IMUX_BUFG_I[6]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[7]
BitsDestination
MAIN[0][26][52]MAIN[0][27][53]MAIN[0][26][53]CELL[0].IMUX_BUFG_O[7]
Source
000CELL[0].IMUX_IMUX[31]
001CELL[0].IMUX_IMUX[27]
010CELL[0].OUT_BUFG_GFB[2]
011CELL[0].OUT_BUFG_GFB[4]
100CELL[0].IMUX_BUFG_I[7]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[8]
BitsDestination
MAIN[1][26][8]MAIN[1][27][6]MAIN[1][26][7]CELL[0].IMUX_BUFG_O[8]
Source
000CELL[1].IMUX_IMUX[28]
001CELL[0].OUT_BUFG_GFB[3]
010CELL[1].IMUX_IMUX[24]
011CELL[0].OUT_BUFG_GFB[5]
100CELL[0].IMUX_BUFG_I[8]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[9]
BitsDestination
MAIN[1][26][4]MAIN[1][26][5]MAIN[1][27][5]CELL[0].IMUX_BUFG_O[9]
Source
000CELL[1].IMUX_IMUX[28]
001CELL[0].OUT_BUFG_GFB[3]
010CELL[1].IMUX_IMUX[24]
011CELL[0].OUT_BUFG_GFB[5]
100CELL[0].IMUX_BUFG_I[9]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[10]
BitsDestination
MAIN[1][26][24]MAIN[1][27][22]MAIN[1][26][23]CELL[0].IMUX_BUFG_O[10]
Source
000CELL[1].IMUX_IMUX[29]
001CELL[0].OUT_BUFG_GFB[4]
010CELL[1].IMUX_IMUX[25]
011CELL[0].OUT_BUFG_GFB[6]
100CELL[0].IMUX_BUFG_I[10]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[11]
BitsDestination
MAIN[1][26][20]MAIN[1][26][21]MAIN[1][27][21]CELL[0].IMUX_BUFG_O[11]
Source
000CELL[1].IMUX_IMUX[29]
001CELL[0].OUT_BUFG_GFB[4]
010CELL[1].IMUX_IMUX[25]
011CELL[0].OUT_BUFG_GFB[6]
100CELL[0].IMUX_BUFG_I[11]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[12]
BitsDestination
MAIN[1][26][40]MAIN[1][27][38]MAIN[1][26][39]CELL[0].IMUX_BUFG_O[12]
Source
000CELL[1].IMUX_IMUX[30]
001CELL[0].OUT_BUFG_GFB[5]
010CELL[1].IMUX_IMUX[26]
011CELL[0].OUT_BUFG_GFB[7]
100CELL[0].IMUX_BUFG_I[12]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[13]
BitsDestination
MAIN[1][26][36]MAIN[1][26][37]MAIN[1][27][37]CELL[0].IMUX_BUFG_O[13]
Source
000CELL[1].IMUX_IMUX[30]
001CELL[0].OUT_BUFG_GFB[5]
010CELL[1].IMUX_IMUX[26]
011CELL[0].OUT_BUFG_GFB[7]
100CELL[0].IMUX_BUFG_I[13]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[14]
BitsDestination
MAIN[1][26][56]MAIN[1][27][54]MAIN[1][26][55]CELL[0].IMUX_BUFG_O[14]
Source
000CELL[1].IMUX_IMUX[31]
001CELL[0].OUT_BUFG_GFB[6]
010CELL[1].IMUX_IMUX[27]
011CELL[0].OUT_BUFG_GFB[8]
100CELL[0].IMUX_BUFG_I[14]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[15]
BitsDestination
MAIN[1][26][52]MAIN[1][26][53]MAIN[1][27][53]CELL[0].IMUX_BUFG_O[15]
Source
000CELL[1].IMUX_IMUX[31]
001CELL[0].OUT_BUFG_GFB[6]
010CELL[1].IMUX_IMUX[27]
011CELL[0].OUT_BUFG_GFB[8]
100CELL[0].IMUX_BUFG_I[15]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[16]
BitsDestination
MAIN[2][26][8]MAIN[2][27][6]MAIN[2][26][7]CELL[0].IMUX_BUFG_O[16]
Source
000CELL[2].IMUX_IMUX[28]
001CELL[0].OUT_BUFG_GFB[7]
010CELL[2].IMUX_IMUX[24]
011CELL[0].OUT_BUFG_GFB[9]
100CELL[0].IMUX_BUFG_I[16]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[17]
BitsDestination
MAIN[2][26][4]MAIN[2][26][5]MAIN[2][27][5]CELL[0].IMUX_BUFG_O[17]
Source
000CELL[2].IMUX_IMUX[28]
001CELL[0].OUT_BUFG_GFB[7]
010CELL[2].IMUX_IMUX[24]
011CELL[0].OUT_BUFG_GFB[9]
100CELL[0].IMUX_BUFG_I[17]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[18]
BitsDestination
MAIN[2][26][24]MAIN[2][27][22]MAIN[2][26][23]CELL[0].IMUX_BUFG_O[18]
Source
000CELL[2].IMUX_IMUX[29]
001CELL[0].OUT_BUFG_GFB[8]
010CELL[2].IMUX_IMUX[25]
011CELL[0].OUT_BUFG_GFB[10]
100CELL[0].IMUX_BUFG_I[18]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[19]
BitsDestination
MAIN[2][26][20]MAIN[2][26][21]MAIN[2][27][21]CELL[0].IMUX_BUFG_O[19]
Source
000CELL[2].IMUX_IMUX[29]
001CELL[0].OUT_BUFG_GFB[8]
010CELL[2].IMUX_IMUX[25]
011CELL[0].OUT_BUFG_GFB[10]
100CELL[0].IMUX_BUFG_I[19]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[20]
BitsDestination
MAIN[2][26][40]MAIN[2][27][38]MAIN[2][26][39]CELL[0].IMUX_BUFG_O[20]
Source
000CELL[2].IMUX_IMUX[30]
001CELL[0].OUT_BUFG_GFB[9]
010CELL[2].IMUX_IMUX[26]
011CELL[0].OUT_BUFG_GFB[11]
100CELL[0].IMUX_BUFG_I[20]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[21]
BitsDestination
MAIN[2][26][36]MAIN[2][26][37]MAIN[2][27][37]CELL[0].IMUX_BUFG_O[21]
Source
000CELL[2].IMUX_IMUX[30]
001CELL[0].OUT_BUFG_GFB[9]
010CELL[2].IMUX_IMUX[26]
011CELL[0].OUT_BUFG_GFB[11]
100CELL[0].IMUX_BUFG_I[21]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[22]
BitsDestination
MAIN[2][26][56]MAIN[2][27][54]MAIN[2][26][55]CELL[0].IMUX_BUFG_O[22]
Source
000CELL[2].IMUX_IMUX[31]
001CELL[0].OUT_BUFG_GFB[10]
010CELL[2].IMUX_IMUX[27]
011CELL[0].OUT_BUFG_GFB[12]
100CELL[0].IMUX_BUFG_I[22]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[23]
BitsDestination
MAIN[2][26][52]MAIN[2][26][53]MAIN[2][27][53]CELL[0].IMUX_BUFG_O[23]
Source
000CELL[2].IMUX_IMUX[31]
001CELL[0].OUT_BUFG_GFB[10]
010CELL[2].IMUX_IMUX[27]
011CELL[0].OUT_BUFG_GFB[12]
100CELL[0].IMUX_BUFG_I[23]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[24]
BitsDestination
MAIN[3][26][8]MAIN[3][27][6]MAIN[3][26][7]CELL[0].IMUX_BUFG_O[24]
Source
000CELL[3].IMUX_IMUX[28]
001CELL[0].OUT_BUFG_GFB[11]
010CELL[3].IMUX_IMUX[24]
011CELL[0].OUT_BUFG_GFB[13]
100CELL[0].IMUX_BUFG_I[24]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[25]
BitsDestination
MAIN[3][26][4]MAIN[3][26][5]MAIN[3][27][5]CELL[0].IMUX_BUFG_O[25]
Source
000CELL[3].IMUX_IMUX[28]
001CELL[0].OUT_BUFG_GFB[11]
010CELL[3].IMUX_IMUX[24]
011CELL[0].OUT_BUFG_GFB[13]
100CELL[0].IMUX_BUFG_I[25]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[26]
BitsDestination
MAIN[3][26][24]MAIN[3][27][22]MAIN[3][26][23]CELL[0].IMUX_BUFG_O[26]
Source
000CELL[3].IMUX_IMUX[29]
001CELL[0].OUT_BUFG_GFB[12]
010CELL[3].IMUX_IMUX[25]
011CELL[0].OUT_BUFG_GFB[14]
100CELL[0].IMUX_BUFG_I[26]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[27]
BitsDestination
MAIN[3][26][20]MAIN[3][26][21]MAIN[3][27][21]CELL[0].IMUX_BUFG_O[27]
Source
000CELL[3].IMUX_IMUX[29]
001CELL[0].OUT_BUFG_GFB[12]
010CELL[3].IMUX_IMUX[25]
011CELL[0].OUT_BUFG_GFB[14]
100CELL[0].IMUX_BUFG_I[27]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[28]
BitsDestination
MAIN[3][26][40]MAIN[3][27][38]MAIN[3][26][39]CELL[0].IMUX_BUFG_O[28]
Source
000CELL[3].IMUX_IMUX[30]
001CELL[0].OUT_BUFG_GFB[13]
010CELL[3].IMUX_IMUX[26]
011CELL[0].OUT_BUFG_GFB[15]
100CELL[0].IMUX_BUFG_I[28]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[29]
BitsDestination
MAIN[3][26][36]MAIN[3][26][37]MAIN[3][27][37]CELL[0].IMUX_BUFG_O[29]
Source
000CELL[3].IMUX_IMUX[30]
001CELL[0].OUT_BUFG_GFB[13]
010CELL[3].IMUX_IMUX[26]
011CELL[0].OUT_BUFG_GFB[15]
100CELL[0].IMUX_BUFG_I[29]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[30]
BitsDestination
MAIN[3][26][56]MAIN[3][27][54]MAIN[3][26][55]CELL[0].IMUX_BUFG_O[30]
Source
000CELL[3].IMUX_IMUX[31]
001CELL[0].OUT_BUFG_GFB[14]
010CELL[3].IMUX_IMUX[27]
011CELL[0].OUT_BUFG_GFB[0]
100CELL[0].IMUX_BUFG_I[30]
virtex7 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[31]
BitsDestination
MAIN[3][26][52]MAIN[3][26][53]MAIN[3][27][53]CELL[0].IMUX_BUFG_O[31]
Source
000CELL[3].IMUX_IMUX[31]
001CELL[0].OUT_BUFG_GFB[14]
010CELL[3].IMUX_IMUX[27]
011CELL[0].OUT_BUFG_GFB[0]
100CELL[0].IMUX_BUFG_I[31]

Bels BUFGCTRL

virtex7 CLK_BUFG_N bel BUFGCTRL pins
PinDirectionBUFGCTRL[0]BUFGCTRL[1]BUFGCTRL[2]BUFGCTRL[3]BUFGCTRL[4]BUFGCTRL[5]BUFGCTRL[6]BUFGCTRL[7]BUFGCTRL[8]BUFGCTRL[9]BUFGCTRL[10]BUFGCTRL[11]BUFGCTRL[12]BUFGCTRL[13]BUFGCTRL[14]BUFGCTRL[15]
I0inCELL[0].IMUX_BUFG_O[0]CELL[0].IMUX_BUFG_O[2]CELL[0].IMUX_BUFG_O[4]CELL[0].IMUX_BUFG_O[6]CELL[0].IMUX_BUFG_O[8]CELL[0].IMUX_BUFG_O[10]CELL[0].IMUX_BUFG_O[12]CELL[0].IMUX_BUFG_O[14]CELL[0].IMUX_BUFG_O[16]CELL[0].IMUX_BUFG_O[18]CELL[0].IMUX_BUFG_O[20]CELL[0].IMUX_BUFG_O[22]CELL[0].IMUX_BUFG_O[24]CELL[0].IMUX_BUFG_O[26]CELL[0].IMUX_BUFG_O[28]CELL[0].IMUX_BUFG_O[30]
I1inCELL[0].IMUX_BUFG_O[1]CELL[0].IMUX_BUFG_O[3]CELL[0].IMUX_BUFG_O[5]CELL[0].IMUX_BUFG_O[7]CELL[0].IMUX_BUFG_O[9]CELL[0].IMUX_BUFG_O[11]CELL[0].IMUX_BUFG_O[13]CELL[0].IMUX_BUFG_O[15]CELL[0].IMUX_BUFG_O[17]CELL[0].IMUX_BUFG_O[19]CELL[0].IMUX_BUFG_O[21]CELL[0].IMUX_BUFG_O[23]CELL[0].IMUX_BUFG_O[25]CELL[0].IMUX_BUFG_O[27]CELL[0].IMUX_BUFG_O[29]CELL[0].IMUX_BUFG_O[31]
S0inCELL[0].IMUX_IMUX[4] invert by !MAIN[0][27][3]CELL[0].IMUX_IMUX[5] invert by !MAIN[0][27][19]CELL[0].IMUX_IMUX[6] invert by !MAIN[0][27][35]CELL[0].IMUX_IMUX[7] invert by !MAIN[0][27][51]CELL[1].IMUX_IMUX[4] invert by !MAIN[1][27][3]CELL[1].IMUX_IMUX[5] invert by !MAIN[1][27][19]CELL[1].IMUX_IMUX[6] invert by !MAIN[1][27][35]CELL[1].IMUX_IMUX[7] invert by !MAIN[1][27][51]CELL[2].IMUX_IMUX[4] invert by !MAIN[2][27][3]CELL[2].IMUX_IMUX[5] invert by !MAIN[2][27][19]CELL[2].IMUX_IMUX[6] invert by !MAIN[2][27][35]CELL[2].IMUX_IMUX[7] invert by !MAIN[2][27][51]CELL[3].IMUX_IMUX[4] invert by !MAIN[3][27][3]CELL[3].IMUX_IMUX[5] invert by !MAIN[3][27][19]CELL[3].IMUX_IMUX[6] invert by !MAIN[3][27][35]CELL[3].IMUX_IMUX[7] invert by !MAIN[3][27][51]
S1inCELL[0].IMUX_IMUX[0] invert by !MAIN[0][26][11]CELL[0].IMUX_IMUX[1] invert by !MAIN[0][26][27]CELL[0].IMUX_IMUX[2] invert by !MAIN[0][26][43]CELL[0].IMUX_IMUX[3] invert by !MAIN[0][26][59]CELL[1].IMUX_IMUX[0] invert by !MAIN[1][26][11]CELL[1].IMUX_IMUX[1] invert by !MAIN[1][26][27]CELL[1].IMUX_IMUX[2] invert by !MAIN[1][26][43]CELL[1].IMUX_IMUX[3] invert by !MAIN[1][26][59]CELL[2].IMUX_IMUX[0] invert by !MAIN[2][26][11]CELL[2].IMUX_IMUX[1] invert by !MAIN[2][26][27]CELL[2].IMUX_IMUX[2] invert by !MAIN[2][26][43]CELL[2].IMUX_IMUX[3] invert by !MAIN[2][26][59]CELL[3].IMUX_IMUX[0] invert by !MAIN[3][26][11]CELL[3].IMUX_IMUX[1] invert by !MAIN[3][26][27]CELL[3].IMUX_IMUX[2] invert by !MAIN[3][26][43]CELL[3].IMUX_IMUX[3] invert by !MAIN[3][26][59]
CE0inCELL[0].IMUX_IMUX[20] invert by !MAIN[0][27][2]CELL[0].IMUX_IMUX[21] invert by !MAIN[0][27][18]CELL[0].IMUX_IMUX[22] invert by !MAIN[0][27][34]CELL[0].IMUX_IMUX[23] invert by !MAIN[0][27][50]CELL[1].IMUX_IMUX[20] invert by !MAIN[1][27][2]CELL[1].IMUX_IMUX[21] invert by !MAIN[1][27][18]CELL[1].IMUX_IMUX[22] invert by !MAIN[1][27][34]CELL[1].IMUX_IMUX[23] invert by !MAIN[1][27][50]CELL[2].IMUX_IMUX[20] invert by !MAIN[2][27][2]CELL[2].IMUX_IMUX[21] invert by !MAIN[2][27][18]CELL[2].IMUX_IMUX[22] invert by !MAIN[2][27][34]CELL[2].IMUX_IMUX[23] invert by !MAIN[2][27][50]CELL[3].IMUX_IMUX[20] invert by !MAIN[3][27][2]CELL[3].IMUX_IMUX[21] invert by !MAIN[3][27][18]CELL[3].IMUX_IMUX[22] invert by !MAIN[3][27][34]CELL[3].IMUX_IMUX[23] invert by !MAIN[3][27][50]
CE1inCELL[0].IMUX_IMUX[16] invert by !MAIN[0][27][11]CELL[0].IMUX_IMUX[17] invert by !MAIN[0][27][27]CELL[0].IMUX_IMUX[18] invert by !MAIN[0][27][43]CELL[0].IMUX_IMUX[19] invert by !MAIN[0][27][59]CELL[1].IMUX_IMUX[16] invert by !MAIN[1][27][11]CELL[1].IMUX_IMUX[17] invert by !MAIN[1][27][27]CELL[1].IMUX_IMUX[18] invert by !MAIN[1][27][43]CELL[1].IMUX_IMUX[19] invert by !MAIN[1][27][59]CELL[2].IMUX_IMUX[16] invert by !MAIN[2][27][11]CELL[2].IMUX_IMUX[17] invert by !MAIN[2][27][27]CELL[2].IMUX_IMUX[18] invert by !MAIN[2][27][43]CELL[2].IMUX_IMUX[19] invert by !MAIN[2][27][59]CELL[3].IMUX_IMUX[16] invert by !MAIN[3][27][11]CELL[3].IMUX_IMUX[17] invert by !MAIN[3][27][27]CELL[3].IMUX_IMUX[18] invert by !MAIN[3][27][43]CELL[3].IMUX_IMUX[19] invert by !MAIN[3][27][59]
IGNORE0inCELL[0].IMUX_IMUX[12] invert by !MAIN[0][26][1]CELL[0].IMUX_IMUX[13] invert by !MAIN[0][26][17]CELL[0].IMUX_IMUX[14] invert by !MAIN[0][26][33]CELL[0].IMUX_IMUX[15] invert by !MAIN[0][26][49]CELL[1].IMUX_IMUX[12] invert by !MAIN[1][26][1]CELL[1].IMUX_IMUX[13] invert by !MAIN[1][26][17]CELL[1].IMUX_IMUX[14] invert by !MAIN[1][26][33]CELL[1].IMUX_IMUX[15] invert by !MAIN[1][26][49]CELL[2].IMUX_IMUX[12] invert by !MAIN[2][26][1]CELL[2].IMUX_IMUX[13] invert by !MAIN[2][26][17]CELL[2].IMUX_IMUX[14] invert by !MAIN[2][26][33]CELL[2].IMUX_IMUX[15] invert by !MAIN[2][26][49]CELL[3].IMUX_IMUX[12] invert by !MAIN[3][26][1]CELL[3].IMUX_IMUX[13] invert by !MAIN[3][26][17]CELL[3].IMUX_IMUX[14] invert by !MAIN[3][26][33]CELL[3].IMUX_IMUX[15] invert by !MAIN[3][26][49]
IGNORE1inCELL[0].IMUX_IMUX[8] invert by !MAIN[0][27][12]CELL[0].IMUX_IMUX[9] invert by !MAIN[0][27][28]CELL[0].IMUX_IMUX[10] invert by !MAIN[0][27][44]CELL[0].IMUX_IMUX[11] invert by !MAIN[0][27][60]CELL[1].IMUX_IMUX[8] invert by !MAIN[1][27][12]CELL[1].IMUX_IMUX[9] invert by !MAIN[1][27][28]CELL[1].IMUX_IMUX[10] invert by !MAIN[1][27][44]CELL[1].IMUX_IMUX[11] invert by !MAIN[1][27][60]CELL[2].IMUX_IMUX[8] invert by !MAIN[2][27][12]CELL[2].IMUX_IMUX[9] invert by !MAIN[2][27][28]CELL[2].IMUX_IMUX[10] invert by !MAIN[2][27][44]CELL[2].IMUX_IMUX[11] invert by !MAIN[2][27][60]CELL[3].IMUX_IMUX[8] invert by !MAIN[3][27][12]CELL[3].IMUX_IMUX[9] invert by !MAIN[3][27][28]CELL[3].IMUX_IMUX[10] invert by !MAIN[3][27][44]CELL[3].IMUX_IMUX[11] invert by !MAIN[3][27][60]
OoutCELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[15]
virtex7 CLK_BUFG_N bel BUFGCTRL attribute bits
AttributeBUFGCTRL[0]BUFGCTRL[1]BUFGCTRL[2]BUFGCTRL[3]BUFGCTRL[4]BUFGCTRL[5]BUFGCTRL[6]BUFGCTRL[7]BUFGCTRL[8]BUFGCTRL[9]BUFGCTRL[10]BUFGCTRL[11]BUFGCTRL[12]BUFGCTRL[13]BUFGCTRL[14]BUFGCTRL[15]
CREATE_EDGEMAIN[0][27][0]MAIN[0][27][16]MAIN[0][27][32]MAIN[0][27][48]MAIN[1][27][0]MAIN[1][27][16]MAIN[1][27][32]MAIN[1][27][48]MAIN[2][27][0]MAIN[2][27][16]MAIN[2][27][32]MAIN[2][27][48]MAIN[3][27][0]MAIN[3][27][16]MAIN[3][27][32]MAIN[3][27][48]
INIT_OUT bit 0MAIN[0][27][13]MAIN[0][27][29]MAIN[0][27][45]MAIN[0][27][61]MAIN[1][27][13]MAIN[1][27][29]MAIN[1][27][45]MAIN[1][27][61]MAIN[2][27][13]MAIN[2][27][29]MAIN[2][27][45]MAIN[2][27][61]MAIN[3][27][13]MAIN[3][27][29]MAIN[3][27][45]MAIN[3][27][61]
PRESELECT_I0!MAIN[0][26][2]!MAIN[0][26][18]!MAIN[0][26][34]!MAIN[0][26][50]!MAIN[1][26][2]!MAIN[1][26][18]!MAIN[1][26][34]!MAIN[1][26][50]!MAIN[2][26][2]!MAIN[2][26][18]!MAIN[2][26][34]!MAIN[2][26][50]!MAIN[3][26][2]!MAIN[3][26][18]!MAIN[3][26][34]!MAIN[3][26][50]
PRESELECT_I1MAIN[0][26][12]MAIN[0][26][28]MAIN[0][26][44]MAIN[0][26][60]MAIN[1][26][12]MAIN[1][26][28]MAIN[1][26][44]MAIN[1][26][60]MAIN[2][26][12]MAIN[2][26][28]MAIN[2][26][44]MAIN[2][26][60]MAIN[3][26][12]MAIN[3][26][28]MAIN[3][26][44]MAIN[3][26][60]
ENABLEMAIN[0][27][15]MAIN[0][27][31]MAIN[0][27][47]MAIN[0][27][63]MAIN[1][27][15]MAIN[1][27][31]MAIN[1][27][47]MAIN[1][27][63]MAIN[2][27][15]MAIN[2][27][31]MAIN[2][27][47]MAIN[2][27][63]MAIN[3][27][15]MAIN[3][27][31]MAIN[3][27][47]MAIN[3][27][63]

Bel wires

virtex7 CLK_BUFG_N bel wires
WirePins
CELL[0].IMUX_IMUX[0]BUFGCTRL[0].S1
CELL[0].IMUX_IMUX[1]BUFGCTRL[1].S1
CELL[0].IMUX_IMUX[2]BUFGCTRL[2].S1
CELL[0].IMUX_IMUX[3]BUFGCTRL[3].S1
CELL[0].IMUX_IMUX[4]BUFGCTRL[0].S0
CELL[0].IMUX_IMUX[5]BUFGCTRL[1].S0
CELL[0].IMUX_IMUX[6]BUFGCTRL[2].S0
CELL[0].IMUX_IMUX[7]BUFGCTRL[3].S0
CELL[0].IMUX_IMUX[8]BUFGCTRL[0].IGNORE1
CELL[0].IMUX_IMUX[9]BUFGCTRL[1].IGNORE1
CELL[0].IMUX_IMUX[10]BUFGCTRL[2].IGNORE1
CELL[0].IMUX_IMUX[11]BUFGCTRL[3].IGNORE1
CELL[0].IMUX_IMUX[12]BUFGCTRL[0].IGNORE0
CELL[0].IMUX_IMUX[13]BUFGCTRL[1].IGNORE0
CELL[0].IMUX_IMUX[14]BUFGCTRL[2].IGNORE0
CELL[0].IMUX_IMUX[15]BUFGCTRL[3].IGNORE0
CELL[0].IMUX_IMUX[16]BUFGCTRL[0].CE1
CELL[0].IMUX_IMUX[17]BUFGCTRL[1].CE1
CELL[0].IMUX_IMUX[18]BUFGCTRL[2].CE1
CELL[0].IMUX_IMUX[19]BUFGCTRL[3].CE1
CELL[0].IMUX_IMUX[20]BUFGCTRL[0].CE0
CELL[0].IMUX_IMUX[21]BUFGCTRL[1].CE0
CELL[0].IMUX_IMUX[22]BUFGCTRL[2].CE0
CELL[0].IMUX_IMUX[23]BUFGCTRL[3].CE0
CELL[0].OUT_BUFG[0]BUFGCTRL[0].O
CELL[0].OUT_BUFG[1]BUFGCTRL[1].O
CELL[0].OUT_BUFG[2]BUFGCTRL[2].O
CELL[0].OUT_BUFG[3]BUFGCTRL[3].O
CELL[0].OUT_BUFG[4]BUFGCTRL[4].O
CELL[0].OUT_BUFG[5]BUFGCTRL[5].O
CELL[0].OUT_BUFG[6]BUFGCTRL[6].O
CELL[0].OUT_BUFG[7]BUFGCTRL[7].O
CELL[0].OUT_BUFG[8]BUFGCTRL[8].O
CELL[0].OUT_BUFG[9]BUFGCTRL[9].O
CELL[0].OUT_BUFG[10]BUFGCTRL[10].O
CELL[0].OUT_BUFG[11]BUFGCTRL[11].O
CELL[0].OUT_BUFG[12]BUFGCTRL[12].O
CELL[0].OUT_BUFG[13]BUFGCTRL[13].O
CELL[0].OUT_BUFG[14]BUFGCTRL[14].O
CELL[0].OUT_BUFG[15]BUFGCTRL[15].O
CELL[0].IMUX_BUFG_O[0]BUFGCTRL[0].I0
CELL[0].IMUX_BUFG_O[1]BUFGCTRL[0].I1
CELL[0].IMUX_BUFG_O[2]BUFGCTRL[1].I0
CELL[0].IMUX_BUFG_O[3]BUFGCTRL[1].I1
CELL[0].IMUX_BUFG_O[4]BUFGCTRL[2].I0
CELL[0].IMUX_BUFG_O[5]BUFGCTRL[2].I1
CELL[0].IMUX_BUFG_O[6]BUFGCTRL[3].I0
CELL[0].IMUX_BUFG_O[7]BUFGCTRL[3].I1
CELL[0].IMUX_BUFG_O[8]BUFGCTRL[4].I0
CELL[0].IMUX_BUFG_O[9]BUFGCTRL[4].I1
CELL[0].IMUX_BUFG_O[10]BUFGCTRL[5].I0
CELL[0].IMUX_BUFG_O[11]BUFGCTRL[5].I1
CELL[0].IMUX_BUFG_O[12]BUFGCTRL[6].I0
CELL[0].IMUX_BUFG_O[13]BUFGCTRL[6].I1
CELL[0].IMUX_BUFG_O[14]BUFGCTRL[7].I0
CELL[0].IMUX_BUFG_O[15]BUFGCTRL[7].I1
CELL[0].IMUX_BUFG_O[16]BUFGCTRL[8].I0
CELL[0].IMUX_BUFG_O[17]BUFGCTRL[8].I1
CELL[0].IMUX_BUFG_O[18]BUFGCTRL[9].I0
CELL[0].IMUX_BUFG_O[19]BUFGCTRL[9].I1
CELL[0].IMUX_BUFG_O[20]BUFGCTRL[10].I0
CELL[0].IMUX_BUFG_O[21]BUFGCTRL[10].I1
CELL[0].IMUX_BUFG_O[22]BUFGCTRL[11].I0
CELL[0].IMUX_BUFG_O[23]BUFGCTRL[11].I1
CELL[0].IMUX_BUFG_O[24]BUFGCTRL[12].I0
CELL[0].IMUX_BUFG_O[25]BUFGCTRL[12].I1
CELL[0].IMUX_BUFG_O[26]BUFGCTRL[13].I0
CELL[0].IMUX_BUFG_O[27]BUFGCTRL[13].I1
CELL[0].IMUX_BUFG_O[28]BUFGCTRL[14].I0
CELL[0].IMUX_BUFG_O[29]BUFGCTRL[14].I1
CELL[0].IMUX_BUFG_O[30]BUFGCTRL[15].I0
CELL[0].IMUX_BUFG_O[31]BUFGCTRL[15].I1
CELL[1].IMUX_IMUX[0]BUFGCTRL[4].S1
CELL[1].IMUX_IMUX[1]BUFGCTRL[5].S1
CELL[1].IMUX_IMUX[2]BUFGCTRL[6].S1
CELL[1].IMUX_IMUX[3]BUFGCTRL[7].S1
CELL[1].IMUX_IMUX[4]BUFGCTRL[4].S0
CELL[1].IMUX_IMUX[5]BUFGCTRL[5].S0
CELL[1].IMUX_IMUX[6]BUFGCTRL[6].S0
CELL[1].IMUX_IMUX[7]BUFGCTRL[7].S0
CELL[1].IMUX_IMUX[8]BUFGCTRL[4].IGNORE1
CELL[1].IMUX_IMUX[9]BUFGCTRL[5].IGNORE1
CELL[1].IMUX_IMUX[10]BUFGCTRL[6].IGNORE1
CELL[1].IMUX_IMUX[11]BUFGCTRL[7].IGNORE1
CELL[1].IMUX_IMUX[12]BUFGCTRL[4].IGNORE0
CELL[1].IMUX_IMUX[13]BUFGCTRL[5].IGNORE0
CELL[1].IMUX_IMUX[14]BUFGCTRL[6].IGNORE0
CELL[1].IMUX_IMUX[15]BUFGCTRL[7].IGNORE0
CELL[1].IMUX_IMUX[16]BUFGCTRL[4].CE1
CELL[1].IMUX_IMUX[17]BUFGCTRL[5].CE1
CELL[1].IMUX_IMUX[18]BUFGCTRL[6].CE1
CELL[1].IMUX_IMUX[19]BUFGCTRL[7].CE1
CELL[1].IMUX_IMUX[20]BUFGCTRL[4].CE0
CELL[1].IMUX_IMUX[21]BUFGCTRL[5].CE0
CELL[1].IMUX_IMUX[22]BUFGCTRL[6].CE0
CELL[1].IMUX_IMUX[23]BUFGCTRL[7].CE0
CELL[2].IMUX_IMUX[0]BUFGCTRL[8].S1
CELL[2].IMUX_IMUX[1]BUFGCTRL[9].S1
CELL[2].IMUX_IMUX[2]BUFGCTRL[10].S1
CELL[2].IMUX_IMUX[3]BUFGCTRL[11].S1
CELL[2].IMUX_IMUX[4]BUFGCTRL[8].S0
CELL[2].IMUX_IMUX[5]BUFGCTRL[9].S0
CELL[2].IMUX_IMUX[6]BUFGCTRL[10].S0
CELL[2].IMUX_IMUX[7]BUFGCTRL[11].S0
CELL[2].IMUX_IMUX[8]BUFGCTRL[8].IGNORE1
CELL[2].IMUX_IMUX[9]BUFGCTRL[9].IGNORE1
CELL[2].IMUX_IMUX[10]BUFGCTRL[10].IGNORE1
CELL[2].IMUX_IMUX[11]BUFGCTRL[11].IGNORE1
CELL[2].IMUX_IMUX[12]BUFGCTRL[8].IGNORE0
CELL[2].IMUX_IMUX[13]BUFGCTRL[9].IGNORE0
CELL[2].IMUX_IMUX[14]BUFGCTRL[10].IGNORE0
CELL[2].IMUX_IMUX[15]BUFGCTRL[11].IGNORE0
CELL[2].IMUX_IMUX[16]BUFGCTRL[8].CE1
CELL[2].IMUX_IMUX[17]BUFGCTRL[9].CE1
CELL[2].IMUX_IMUX[18]BUFGCTRL[10].CE1
CELL[2].IMUX_IMUX[19]BUFGCTRL[11].CE1
CELL[2].IMUX_IMUX[20]BUFGCTRL[8].CE0
CELL[2].IMUX_IMUX[21]BUFGCTRL[9].CE0
CELL[2].IMUX_IMUX[22]BUFGCTRL[10].CE0
CELL[2].IMUX_IMUX[23]BUFGCTRL[11].CE0
CELL[3].IMUX_IMUX[0]BUFGCTRL[12].S1
CELL[3].IMUX_IMUX[1]BUFGCTRL[13].S1
CELL[3].IMUX_IMUX[2]BUFGCTRL[14].S1
CELL[3].IMUX_IMUX[3]BUFGCTRL[15].S1
CELL[3].IMUX_IMUX[4]BUFGCTRL[12].S0
CELL[3].IMUX_IMUX[5]BUFGCTRL[13].S0
CELL[3].IMUX_IMUX[6]BUFGCTRL[14].S0
CELL[3].IMUX_IMUX[7]BUFGCTRL[15].S0
CELL[3].IMUX_IMUX[8]BUFGCTRL[12].IGNORE1
CELL[3].IMUX_IMUX[9]BUFGCTRL[13].IGNORE1
CELL[3].IMUX_IMUX[10]BUFGCTRL[14].IGNORE1
CELL[3].IMUX_IMUX[11]BUFGCTRL[15].IGNORE1
CELL[3].IMUX_IMUX[12]BUFGCTRL[12].IGNORE0
CELL[3].IMUX_IMUX[13]BUFGCTRL[13].IGNORE0
CELL[3].IMUX_IMUX[14]BUFGCTRL[14].IGNORE0
CELL[3].IMUX_IMUX[15]BUFGCTRL[15].IGNORE0
CELL[3].IMUX_IMUX[16]BUFGCTRL[12].CE1
CELL[3].IMUX_IMUX[17]BUFGCTRL[13].CE1
CELL[3].IMUX_IMUX[18]BUFGCTRL[14].CE1
CELL[3].IMUX_IMUX[19]BUFGCTRL[15].CE1
CELL[3].IMUX_IMUX[20]BUFGCTRL[12].CE0
CELL[3].IMUX_IMUX[21]BUFGCTRL[13].CE0
CELL[3].IMUX_IMUX[22]BUFGCTRL[14].CE0
CELL[3].IMUX_IMUX[23]BUFGCTRL[15].CE0

Bitstream

virtex7 CLK_BUFG_N rect MAIN[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[3]: ENABLE - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[3] ← CELL[0].OUT_BUFG[3] SPEC_INT: buffer CELL[0].GCLK[19] ← CELL[0].OUT_BUFG[3] - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[3]: INIT_OUT bit 0 - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[3]: PRESELECT_I1 BUFGCTRL[3]: !invert IGNORE1 - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[3]: !invert S1 BUFGCTRL[3]: !invert CE1 - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BEL[3] ← CELL[0].IMUX_BUFG_O[7] - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BEL[7] ← CELL[0].IMUX_BUFG_O[6] - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 2 - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 1 - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 0 - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 1 - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 2 - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[3]: !invert S0 - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[3]: ! PRESELECT_I0 BUFGCTRL[3]: !invert CE0 - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[3]: !invert IGNORE0 - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[3]: CREATE_EDGE - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[2]: ENABLE - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[2] ← CELL[0].OUT_BUFG[2] SPEC_INT: buffer CELL[0].GCLK[18] ← CELL[0].OUT_BUFG[2] - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[2]: INIT_OUT bit 0 - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[2]: PRESELECT_I1 BUFGCTRL[2]: !invert IGNORE1 - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[2]: !invert S1 BUFGCTRL[2]: !invert CE1 - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BEL[2] ← CELL[0].IMUX_BUFG_O[5] - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BEL[6] ← CELL[0].IMUX_BUFG_O[4] - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 2 - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 1 - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 0 - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 1 - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 2 - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[2]: !invert S0 - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[2]: ! PRESELECT_I0 BUFGCTRL[2]: !invert CE0 - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[2]: !invert IGNORE0 - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[2]: CREATE_EDGE - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[1]: ENABLE - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[1] ← CELL[0].OUT_BUFG[1] SPEC_INT: buffer CELL[0].GCLK[17] ← CELL[0].OUT_BUFG[1] - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[1]: INIT_OUT bit 0 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[1]: PRESELECT_I1 BUFGCTRL[1]: !invert IGNORE1 - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[1]: !invert S1 BUFGCTRL[1]: !invert CE1 - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BEL[1] ← CELL[0].IMUX_BUFG_O[3] - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BEL[5] ← CELL[0].IMUX_BUFG_O[2] - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 2 - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 1 - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 0 - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 1 - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 2 - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[1]: !invert S0 - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[1]: ! PRESELECT_I0 BUFGCTRL[1]: !invert CE0 - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[1]: !invert IGNORE0 - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[1]: CREATE_EDGE - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[0]: ENABLE - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[0] ← CELL[0].OUT_BUFG[0] SPEC_INT: buffer CELL[0].GCLK[16] ← CELL[0].OUT_BUFG[0] - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[0]: INIT_OUT bit 0 - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[0]: PRESELECT_I1 BUFGCTRL[0]: !invert IGNORE1 - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[0]: !invert S1 BUFGCTRL[0]: !invert CE1 - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BEL[0] ← CELL[0].IMUX_BUFG_O[1] - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BEL[4] ← CELL[0].IMUX_BUFG_O[0] - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 2 - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 1 - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 0 - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 1 - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 2 - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[0]: !invert S0 - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[0]: ! PRESELECT_I0 BUFGCTRL[0]: !invert CE0 - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[0]: !invert IGNORE0 - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[0]: CREATE_EDGE - -
virtex7 CLK_BUFG_N rect MAIN[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[7]: ENABLE - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[7] ← CELL[0].OUT_BUFG[7] SPEC_INT: buffer CELL[0].GCLK[23] ← CELL[0].OUT_BUFG[7] - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[7]: INIT_OUT bit 0 - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[7]: PRESELECT_I1 BUFGCTRL[7]: !invert IGNORE1 - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[7]: !invert S1 BUFGCTRL[7]: !invert CE1 - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].OUT_BEL[3] ← CELL[0].IMUX_BUFG_O[15] - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].OUT_BEL[7] ← CELL[0].IMUX_BUFG_O[14] - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 2 - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 0 - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 1 - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 0 - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 2 - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[7]: !invert S0 - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[7]: ! PRESELECT_I0 BUFGCTRL[7]: !invert CE0 - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[7]: !invert IGNORE0 - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[7]: CREATE_EDGE - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[6]: ENABLE - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[6] ← CELL[0].OUT_BUFG[6] SPEC_INT: buffer CELL[0].GCLK[22] ← CELL[0].OUT_BUFG[6] - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[6]: INIT_OUT bit 0 - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[6]: PRESELECT_I1 BUFGCTRL[6]: !invert IGNORE1 - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[6]: !invert S1 BUFGCTRL[6]: !invert CE1 - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].OUT_BEL[2] ← CELL[0].IMUX_BUFG_O[13] - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].OUT_BEL[6] ← CELL[0].IMUX_BUFG_O[12] - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 2 - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 0 - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 1 - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 0 - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 2 - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[6]: !invert S0 - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[6]: ! PRESELECT_I0 BUFGCTRL[6]: !invert CE0 - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[6]: !invert IGNORE0 - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[6]: CREATE_EDGE - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[5]: ENABLE - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[5] ← CELL[0].OUT_BUFG[5] SPEC_INT: buffer CELL[0].GCLK[21] ← CELL[0].OUT_BUFG[5] - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[5]: INIT_OUT bit 0 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[5]: PRESELECT_I1 BUFGCTRL[5]: !invert IGNORE1 - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[5]: !invert S1 BUFGCTRL[5]: !invert CE1 - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].OUT_BEL[1] ← CELL[0].IMUX_BUFG_O[11] - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].OUT_BEL[5] ← CELL[0].IMUX_BUFG_O[10] - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 2 - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 0 - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 1 - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 0 - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 2 - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[5]: !invert S0 - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[5]: ! PRESELECT_I0 BUFGCTRL[5]: !invert CE0 - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[5]: !invert IGNORE0 - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[5]: CREATE_EDGE - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[4]: ENABLE - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[4] ← CELL[0].OUT_BUFG[4] SPEC_INT: buffer CELL[0].GCLK[20] ← CELL[0].OUT_BUFG[4] - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[4]: INIT_OUT bit 0 - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[4]: PRESELECT_I1 BUFGCTRL[4]: !invert IGNORE1 - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[4]: !invert S1 BUFGCTRL[4]: !invert CE1 - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].OUT_BEL[0] ← CELL[0].IMUX_BUFG_O[9] - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].OUT_BEL[4] ← CELL[0].IMUX_BUFG_O[8] - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 2 - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 0 - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 1 - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 0 - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 2 - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[4]: !invert S0 - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[4]: ! PRESELECT_I0 BUFGCTRL[4]: !invert CE0 - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[4]: !invert IGNORE0 - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[4]: CREATE_EDGE - -
virtex7 CLK_BUFG_N rect MAIN[2]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[11]: ENABLE - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[11] ← CELL[0].OUT_BUFG[11] SPEC_INT: buffer CELL[0].GCLK[27] ← CELL[0].OUT_BUFG[11] - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[11]: INIT_OUT bit 0 - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[11]: PRESELECT_I1 BUFGCTRL[11]: !invert IGNORE1 - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[11]: !invert S1 BUFGCTRL[11]: !invert CE1 - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[2].OUT_BEL[3] ← CELL[0].IMUX_BUFG_O[23] - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[2].OUT_BEL[7] ← CELL[0].IMUX_BUFG_O[22] - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 2 - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 0 - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 1 - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 0 - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 2 - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[11]: !invert S0 - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[11]: ! PRESELECT_I0 BUFGCTRL[11]: !invert CE0 - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[11]: !invert IGNORE0 - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[11]: CREATE_EDGE - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[10]: ENABLE - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[10] ← CELL[0].OUT_BUFG[10] SPEC_INT: buffer CELL[0].GCLK[26] ← CELL[0].OUT_BUFG[10] - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[10]: INIT_OUT bit 0 - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[10]: PRESELECT_I1 BUFGCTRL[10]: !invert IGNORE1 - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[10]: !invert S1 BUFGCTRL[10]: !invert CE1 - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[2].OUT_BEL[2] ← CELL[0].IMUX_BUFG_O[21] - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[2].OUT_BEL[6] ← CELL[0].IMUX_BUFG_O[20] - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 2 - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 0 - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 1 - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 0 - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 2 - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[10]: !invert S0 - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[10]: ! PRESELECT_I0 BUFGCTRL[10]: !invert CE0 - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[10]: !invert IGNORE0 - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[10]: CREATE_EDGE - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[9]: ENABLE - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[9] ← CELL[0].OUT_BUFG[9] SPEC_INT: buffer CELL[0].GCLK[25] ← CELL[0].OUT_BUFG[9] - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[9]: INIT_OUT bit 0 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[9]: PRESELECT_I1 BUFGCTRL[9]: !invert IGNORE1 - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[9]: !invert S1 BUFGCTRL[9]: !invert CE1 - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[2].OUT_BEL[1] ← CELL[0].IMUX_BUFG_O[19] - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[2].OUT_BEL[5] ← CELL[0].IMUX_BUFG_O[18] - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 2 - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 0 - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 1 - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 0 - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 2 - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[9]: !invert S0 - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[9]: ! PRESELECT_I0 BUFGCTRL[9]: !invert CE0 - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[9]: !invert IGNORE0 - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[9]: CREATE_EDGE - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[8]: ENABLE - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[8] ← CELL[0].OUT_BUFG[8] SPEC_INT: buffer CELL[0].GCLK[24] ← CELL[0].OUT_BUFG[8] - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[8]: INIT_OUT bit 0 - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[8]: PRESELECT_I1 BUFGCTRL[8]: !invert IGNORE1 - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[8]: !invert S1 BUFGCTRL[8]: !invert CE1 - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[2].OUT_BEL[0] ← CELL[0].IMUX_BUFG_O[17] - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[2].OUT_BEL[4] ← CELL[0].IMUX_BUFG_O[16] - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 2 - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 0 - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 1 - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 0 - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 2 - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[8]: !invert S0 - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[8]: ! PRESELECT_I0 BUFGCTRL[8]: !invert CE0 - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[8]: !invert IGNORE0 - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[8]: CREATE_EDGE - -
virtex7 CLK_BUFG_N rect MAIN[3]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[15]: ENABLE - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[15] ← CELL[0].OUT_BUFG[15] SPEC_INT: buffer CELL[0].GCLK[31] ← CELL[0].OUT_BUFG[15] - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[15]: INIT_OUT bit 0 - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[15]: PRESELECT_I1 BUFGCTRL[15]: !invert IGNORE1 - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[15]: !invert S1 BUFGCTRL[15]: !invert CE1 - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[3].OUT_BEL[3] ← CELL[0].IMUX_BUFG_O[31] - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[3].OUT_BEL[7] ← CELL[0].IMUX_BUFG_O[30] - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 2 - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 0 - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 1 - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 0 - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 2 - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[15]: !invert S0 - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[15]: ! PRESELECT_I0 BUFGCTRL[15]: !invert CE0 - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[15]: !invert IGNORE0 - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[15]: CREATE_EDGE - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[14]: ENABLE - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[14] ← CELL[0].OUT_BUFG[14] SPEC_INT: buffer CELL[0].GCLK[30] ← CELL[0].OUT_BUFG[14] - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[14]: INIT_OUT bit 0 - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[14]: PRESELECT_I1 BUFGCTRL[14]: !invert IGNORE1 - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[14]: !invert S1 BUFGCTRL[14]: !invert CE1 - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[3].OUT_BEL[2] ← CELL[0].IMUX_BUFG_O[29] - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[3].OUT_BEL[6] ← CELL[0].IMUX_BUFG_O[28] - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 2 - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 0 - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 1 - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 0 - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 2 - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[14]: !invert S0 - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[14]: ! PRESELECT_I0 BUFGCTRL[14]: !invert CE0 - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[14]: !invert IGNORE0 - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[14]: CREATE_EDGE - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[13]: ENABLE - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[13] ← CELL[0].OUT_BUFG[13] SPEC_INT: buffer CELL[0].GCLK[29] ← CELL[0].OUT_BUFG[13] - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[13]: INIT_OUT bit 0 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[13]: PRESELECT_I1 BUFGCTRL[13]: !invert IGNORE1 - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[13]: !invert S1 BUFGCTRL[13]: !invert CE1 - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[3].OUT_BEL[1] ← CELL[0].IMUX_BUFG_O[27] - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[3].OUT_BEL[5] ← CELL[0].IMUX_BUFG_O[26] - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 2 - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 0 - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 1 - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 0 - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 2 - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[13]: !invert S0 - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[13]: ! PRESELECT_I0 BUFGCTRL[13]: !invert CE0 - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[13]: !invert IGNORE0 - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[13]: CREATE_EDGE - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[12]: ENABLE - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[12] ← CELL[0].OUT_BUFG[12] SPEC_INT: buffer CELL[0].GCLK[28] ← CELL[0].OUT_BUFG[12] - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[12]: INIT_OUT bit 0 - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[12]: PRESELECT_I1 BUFGCTRL[12]: !invert IGNORE1 - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[12]: !invert S1 BUFGCTRL[12]: !invert CE1 - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[3].OUT_BEL[0] ← CELL[0].IMUX_BUFG_O[25] - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[3].OUT_BEL[4] ← CELL[0].IMUX_BUFG_O[24] - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 2 - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 0 - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 1 - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 1 SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 0 - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 2 - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[12]: !invert S0 - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[12]: ! PRESELECT_I0 BUFGCTRL[12]: !invert CE0 - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[12]: !invert IGNORE0 - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFGCTRL[12]: CREATE_EDGE - -