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Clock row buffers

Tile CLK_HROW

Cells: 3

Switchbox SPEC_INT

virtex7 CLK_HROW switchbox SPEC_INT programmable buffers
DestinationSourceBit
CELL[1].GCLK_HROW[0]CELL[1].GCLK[0]HCLK[28][23]
CELL[1].GCLK_HROW[1]CELL[1].GCLK[1]HCLK[29][23]
CELL[1].GCLK_HROW[2]CELL[1].GCLK[2]HCLK[28][24]
CELL[1].GCLK_HROW[3]CELL[1].GCLK[3]HCLK[29][24]
CELL[1].GCLK_HROW[4]CELL[1].GCLK[4]HCLK[28][25]
CELL[1].GCLK_HROW[5]CELL[1].GCLK[5]HCLK[29][25]
CELL[1].GCLK_HROW[6]CELL[1].GCLK[6]HCLK[28][26]
CELL[1].GCLK_HROW[7]CELL[1].GCLK[7]HCLK[29][26]
CELL[1].GCLK_HROW[8]CELL[1].GCLK[8]HCLK[28][27]
CELL[1].GCLK_HROW[9]CELL[1].GCLK[9]HCLK[29][27]
CELL[1].GCLK_HROW[10]CELL[1].GCLK[10]HCLK[28][28]
CELL[1].GCLK_HROW[11]CELL[1].GCLK[11]HCLK[29][28]
CELL[1].GCLK_HROW[12]CELL[1].GCLK[12]HCLK[28][29]
CELL[1].GCLK_HROW[13]CELL[1].GCLK[13]HCLK[29][29]
CELL[1].GCLK_HROW[14]CELL[1].GCLK[14]HCLK[28][30]
CELL[1].GCLK_HROW[15]CELL[1].GCLK[15]HCLK[29][30]
CELL[1].GCLK_HROW[16]CELL[1].GCLK[16]HCLK[26][23]
CELL[1].GCLK_HROW[17]CELL[1].GCLK[17]HCLK[27][23]
CELL[1].GCLK_HROW[18]CELL[1].GCLK[18]HCLK[26][24]
CELL[1].GCLK_HROW[19]CELL[1].GCLK[19]HCLK[27][24]
CELL[1].GCLK_HROW[20]CELL[1].GCLK[20]HCLK[26][25]
CELL[1].GCLK_HROW[21]CELL[1].GCLK[21]HCLK[27][25]
CELL[1].GCLK_HROW[22]CELL[1].GCLK[22]HCLK[26][26]
CELL[1].GCLK_HROW[23]CELL[1].GCLK[23]HCLK[27][26]
CELL[1].GCLK_HROW[24]CELL[1].GCLK[24]HCLK[26][27]
CELL[1].GCLK_HROW[25]CELL[1].GCLK[25]HCLK[27][27]
CELL[1].GCLK_HROW[26]CELL[1].GCLK[26]HCLK[26][28]
CELL[1].GCLK_HROW[27]CELL[1].GCLK[27]HCLK[27][28]
CELL[1].GCLK_HROW[28]CELL[1].GCLK[28]HCLK[26][29]
CELL[1].GCLK_HROW[29]CELL[1].GCLK[29]HCLK[27][29]
CELL[1].GCLK_HROW[30]CELL[1].GCLK[30]HCLK[26][30]
CELL[1].GCLK_HROW[31]CELL[1].GCLK[31]HCLK[27][30]
CELL[1].HROW_I_HROW_W[0]CELL[1].HROW_I[0]HCLK[26][18]
CELL[1].HROW_I_HROW_W[1]CELL[1].HROW_I[1]HCLK[27][18]
CELL[1].HROW_I_HROW_W[2]CELL[1].HROW_I[2]HCLK[26][19]
CELL[1].HROW_I_HROW_W[3]CELL[1].HROW_I[3]HCLK[27][19]
CELL[1].HROW_I_HROW_W[4]CELL[1].HROW_I[4]HCLK[26][20]
CELL[1].HROW_I_HROW_W[5]CELL[1].HROW_I[5]HCLK[27][20]
CELL[1].HROW_I_HROW_W[6]CELL[1].HROW_I[6]HCLK[26][21]
CELL[1].HROW_I_HROW_W[7]CELL[1].HROW_I[7]HCLK[27][21]
CELL[1].HROW_I_HROW_W[8]CELL[1].HROW_I[8]HCLK[26][22]
CELL[1].HROW_I_HROW_W[9]CELL[1].HROW_I[9]HCLK[27][22]
CELL[1].HROW_I_HROW_W[10]CELL[1].HROW_I[10]MAIN[3][26][48]
CELL[1].HROW_I_HROW_W[11]CELL[1].HROW_I[11]MAIN[3][27][48]
CELL[1].HROW_I_HROW_W[12]CELL[1].HROW_I[12]MAIN[3][26][49]
CELL[1].HROW_I_HROW_W[13]CELL[1].HROW_I[13]MAIN[3][27][49]
CELL[1].HROW_I_HROW_E[0]CELL_E.HROW_I[0]HCLK[28][18]
CELL[1].HROW_I_HROW_E[1]CELL_E.HROW_I[1]HCLK[29][18]
CELL[1].HROW_I_HROW_E[2]CELL_E.HROW_I[2]HCLK[28][19]
CELL[1].HROW_I_HROW_E[3]CELL_E.HROW_I[3]HCLK[29][19]
CELL[1].HROW_I_HROW_E[4]CELL_E.HROW_I[4]HCLK[28][20]
CELL[1].HROW_I_HROW_E[5]CELL_E.HROW_I[5]HCLK[29][20]
CELL[1].HROW_I_HROW_E[6]CELL_E.HROW_I[6]HCLK[28][21]
CELL[1].HROW_I_HROW_E[7]CELL_E.HROW_I[7]HCLK[29][21]
CELL[1].HROW_I_HROW_E[8]CELL_E.HROW_I[8]HCLK[28][22]
CELL[1].HROW_I_HROW_E[9]CELL_E.HROW_I[9]HCLK[29][22]
CELL[1].HROW_I_HROW_E[10]CELL_E.HROW_I[10]MAIN[3][28][48]
CELL[1].HROW_I_HROW_E[11]CELL_E.HROW_I[11]MAIN[3][29][48]
CELL[1].HROW_I_HROW_E[12]CELL_E.HROW_I[12]MAIN[3][28][49]
CELL[1].HROW_I_HROW_E[13]CELL_E.HROW_I[13]MAIN[3][29][49]
CELL[1].RCLK_HROW_W[0]CELL[1].RCLK_ROW[0]HCLK[26][14]
CELL[1].RCLK_HROW_W[1]CELL[1].RCLK_ROW[1]HCLK[27][14]
CELL[1].RCLK_HROW_W[2]CELL[1].RCLK_ROW[2]HCLK[26][15]
CELL[1].RCLK_HROW_W[3]CELL[1].RCLK_ROW[3]HCLK[27][15]
CELL[1].RCLK_HROW_E[0]CELL_E.RCLK_ROW[0]HCLK[28][14]
CELL[1].RCLK_HROW_E[1]CELL_E.RCLK_ROW[1]HCLK[29][14]
CELL[1].RCLK_HROW_E[2]CELL_E.RCLK_ROW[2]HCLK[28][15]
CELL[1].RCLK_HROW_E[3]CELL_E.RCLK_ROW[3]HCLK[29][15]
CELL[1].CKINT_HROW[0]CELL[0].IMUX_CLK[0]HCLK[26][31]
CELL[1].CKINT_HROW[1]CELL[0].IMUX_CLK[1]HCLK[27][31]
CELL[1].CKINT_HROW[2]CELL[1].IMUX_CLK[0]HCLK[28][31]
CELL[1].CKINT_HROW[3]CELL[1].IMUX_CLK[1]HCLK[29][31]
CELL[1].GCLK_TEST_IN[0]CELL[1].GCLK_HROW[0]MAIN[0][27][20]
CELL[1].GCLK_TEST_IN[1]CELL[1].GCLK_HROW[1]MAIN[0][29][20]
CELL[1].GCLK_TEST_IN[2]CELL[1].GCLK_HROW[2]MAIN[0][27][36]
CELL[1].GCLK_TEST_IN[3]CELL[1].GCLK_HROW[3]MAIN[0][29][36]
CELL[1].GCLK_TEST_IN[4]CELL[1].GCLK_HROW[4]MAIN[0][27][52]
CELL[1].GCLK_TEST_IN[5]CELL[1].GCLK_HROW[5]MAIN[0][29][52]
CELL[1].GCLK_TEST_IN[6]CELL[1].GCLK_HROW[6]MAIN[1][27][4]
CELL[1].GCLK_TEST_IN[7]CELL[1].GCLK_HROW[7]MAIN[1][29][4]
CELL[1].GCLK_TEST_IN[8]CELL[1].GCLK_HROW[8]MAIN[1][27][20]
CELL[1].GCLK_TEST_IN[9]CELL[1].GCLK_HROW[9]MAIN[1][29][20]
CELL[1].GCLK_TEST_IN[10]CELL[1].GCLK_HROW[10]MAIN[1][27][36]
CELL[1].GCLK_TEST_IN[11]CELL[1].GCLK_HROW[11]MAIN[1][29][36]
CELL[1].GCLK_TEST_IN[12]CELL[1].GCLK_HROW[12]MAIN[1][27][52]
CELL[1].GCLK_TEST_IN[13]CELL[1].GCLK_HROW[13]MAIN[1][29][52]
CELL[1].GCLK_TEST_IN[14]CELL[1].GCLK_HROW[14]MAIN[2][27][4]
CELL[1].GCLK_TEST_IN[15]CELL[1].GCLK_HROW[15]MAIN[2][29][4]
CELL[1].GCLK_TEST_IN[16]CELL[1].GCLK_HROW[16]MAIN[5][27][52]
CELL[1].GCLK_TEST_IN[17]CELL[1].GCLK_HROW[17]MAIN[5][29][52]
CELL[1].GCLK_TEST_IN[18]CELL[1].GCLK_HROW[18]MAIN[6][27][4]
CELL[1].GCLK_TEST_IN[19]CELL[1].GCLK_HROW[19]MAIN[6][29][4]
CELL[1].GCLK_TEST_IN[20]CELL[1].GCLK_HROW[20]MAIN[6][27][20]
CELL[1].GCLK_TEST_IN[21]CELL[1].GCLK_HROW[21]MAIN[6][29][20]
CELL[1].GCLK_TEST_IN[22]CELL[1].GCLK_HROW[22]MAIN[6][27][36]
CELL[1].GCLK_TEST_IN[23]CELL[1].GCLK_HROW[23]MAIN[6][29][36]
CELL[1].GCLK_TEST_IN[24]CELL[1].GCLK_HROW[24]MAIN[6][27][52]
CELL[1].GCLK_TEST_IN[25]CELL[1].GCLK_HROW[25]MAIN[6][29][52]
CELL[1].GCLK_TEST_IN[26]CELL[1].GCLK_HROW[26]MAIN[7][27][4]
CELL[1].GCLK_TEST_IN[27]CELL[1].GCLK_HROW[27]MAIN[7][29][4]
CELL[1].GCLK_TEST_IN[28]CELL[1].GCLK_HROW[28]MAIN[7][27][20]
CELL[1].GCLK_TEST_IN[29]CELL[1].GCLK_HROW[29]MAIN[7][29][20]
CELL[1].GCLK_TEST_IN[30]CELL[1].GCLK_HROW[30]MAIN[7][27][36]
CELL[1].GCLK_TEST_IN[31]CELL[1].GCLK_HROW[31]MAIN[7][29][36]
virtex7 CLK_HROW switchbox SPEC_INT programmable inverters
DestinationSourceBit
CELL[1].GCLK_TEST[0]CELL[1].GCLK_TEST_IN[0]MAIN[0][26][21]
CELL[1].GCLK_TEST[1]CELL[1].GCLK_TEST_IN[1]MAIN[0][28][21]
CELL[1].GCLK_TEST[2]CELL[1].GCLK_TEST_IN[2]MAIN[0][26][37]
CELL[1].GCLK_TEST[3]CELL[1].GCLK_TEST_IN[3]MAIN[0][28][37]
CELL[1].GCLK_TEST[4]CELL[1].GCLK_TEST_IN[4]MAIN[0][26][53]
CELL[1].GCLK_TEST[5]CELL[1].GCLK_TEST_IN[5]MAIN[0][28][53]
CELL[1].GCLK_TEST[6]CELL[1].GCLK_TEST_IN[6]MAIN[1][26][5]
CELL[1].GCLK_TEST[7]CELL[1].GCLK_TEST_IN[7]MAIN[1][28][5]
CELL[1].GCLK_TEST[8]CELL[1].GCLK_TEST_IN[8]MAIN[1][26][21]
CELL[1].GCLK_TEST[9]CELL[1].GCLK_TEST_IN[9]MAIN[1][28][21]
CELL[1].GCLK_TEST[10]CELL[1].GCLK_TEST_IN[10]MAIN[1][26][37]
CELL[1].GCLK_TEST[11]CELL[1].GCLK_TEST_IN[11]MAIN[1][28][37]
CELL[1].GCLK_TEST[12]CELL[1].GCLK_TEST_IN[12]MAIN[1][26][53]
CELL[1].GCLK_TEST[13]CELL[1].GCLK_TEST_IN[13]MAIN[1][28][53]
CELL[1].GCLK_TEST[14]CELL[1].GCLK_TEST_IN[14]MAIN[2][26][5]
CELL[1].GCLK_TEST[15]CELL[1].GCLK_TEST_IN[15]MAIN[2][28][5]
CELL[1].GCLK_TEST[16]CELL[1].GCLK_TEST_IN[16]MAIN[5][26][53]
CELL[1].GCLK_TEST[17]CELL[1].GCLK_TEST_IN[17]MAIN[5][28][53]
CELL[1].GCLK_TEST[18]CELL[1].GCLK_TEST_IN[18]MAIN[6][26][5]
CELL[1].GCLK_TEST[19]CELL[1].GCLK_TEST_IN[19]MAIN[6][28][5]
CELL[1].GCLK_TEST[20]CELL[1].GCLK_TEST_IN[20]MAIN[6][26][21]
CELL[1].GCLK_TEST[21]CELL[1].GCLK_TEST_IN[21]MAIN[6][28][21]
CELL[1].GCLK_TEST[22]CELL[1].GCLK_TEST_IN[22]MAIN[6][26][37]
CELL[1].GCLK_TEST[23]CELL[1].GCLK_TEST_IN[23]MAIN[6][28][37]
CELL[1].GCLK_TEST[24]CELL[1].GCLK_TEST_IN[24]MAIN[6][26][53]
CELL[1].GCLK_TEST[25]CELL[1].GCLK_TEST_IN[25]MAIN[6][28][53]
CELL[1].GCLK_TEST[26]CELL[1].GCLK_TEST_IN[26]MAIN[7][26][5]
CELL[1].GCLK_TEST[27]CELL[1].GCLK_TEST_IN[27]MAIN[7][28][5]
CELL[1].GCLK_TEST[28]CELL[1].GCLK_TEST_IN[28]MAIN[7][26][21]
CELL[1].GCLK_TEST[29]CELL[1].GCLK_TEST_IN[29]MAIN[7][28][21]
CELL[1].GCLK_TEST[30]CELL[1].GCLK_TEST_IN[30]MAIN[7][26][37]
CELL[1].GCLK_TEST[31]CELL[1].GCLK_TEST_IN[31]MAIN[7][28][37]
CELL[1].BUFH_TEST_WCELL[1].BUFH_TEST_W_INMAIN[4][26][0]
CELL[1].BUFH_TEST_ECELL[1].BUFH_TEST_E_INMAIN[4][28][0]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[0]
BitsDestination
MAIN[0][27][31]MAIN[0][26][31]MAIN[0][27][30]MAIN[0][26][30]MAIN[0][27][29]MAIN[0][26][29]MAIN[0][27][28]MAIN[0][26][28]MAIN[0][26][26]MAIN[0][27][25]MAIN[0][26][25]MAIN[0][27][24]MAIN[0][26][24]MAIN[0][26][20]CELL[1].IMUX_BUFG_O[0]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[0]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[0]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[1]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[1]
BitsDestination
MAIN[0][29][31]MAIN[0][28][31]MAIN[0][29][30]MAIN[0][28][30]MAIN[0][29][29]MAIN[0][28][29]MAIN[0][29][28]MAIN[0][28][28]MAIN[0][28][26]MAIN[0][29][25]MAIN[0][28][25]MAIN[0][29][24]MAIN[0][28][24]MAIN[0][28][20]CELL[1].IMUX_BUFG_O[1]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[1]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[0]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[1]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[2]
BitsDestination
MAIN[0][27][47]MAIN[0][26][47]MAIN[0][27][46]MAIN[0][26][46]MAIN[0][27][45]MAIN[0][26][45]MAIN[0][27][44]MAIN[0][26][44]MAIN[0][26][42]MAIN[0][27][41]MAIN[0][26][41]MAIN[0][27][40]MAIN[0][26][40]MAIN[0][26][36]CELL[1].IMUX_BUFG_O[2]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[2]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[2]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[3]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[3]
BitsDestination
MAIN[0][29][47]MAIN[0][28][47]MAIN[0][29][46]MAIN[0][28][46]MAIN[0][29][45]MAIN[0][28][45]MAIN[0][29][44]MAIN[0][28][44]MAIN[0][28][42]MAIN[0][29][41]MAIN[0][28][41]MAIN[0][29][40]MAIN[0][28][40]MAIN[0][28][36]CELL[1].IMUX_BUFG_O[3]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[3]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[2]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[3]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[4]
BitsDestination
MAIN[0][27][63]MAIN[0][26][63]MAIN[0][27][62]MAIN[0][26][62]MAIN[0][27][61]MAIN[0][26][61]MAIN[0][27][60]MAIN[0][26][60]MAIN[0][26][58]MAIN[0][27][57]MAIN[0][26][57]MAIN[0][27][56]MAIN[0][26][56]MAIN[0][26][52]CELL[1].IMUX_BUFG_O[4]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[4]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[4]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[5]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[5]
BitsDestination
MAIN[0][29][63]MAIN[0][28][63]MAIN[0][29][62]MAIN[0][28][62]MAIN[0][29][61]MAIN[0][28][61]MAIN[0][29][60]MAIN[0][28][60]MAIN[0][28][58]MAIN[0][29][57]MAIN[0][28][57]MAIN[0][29][56]MAIN[0][28][56]MAIN[0][28][52]CELL[1].IMUX_BUFG_O[5]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[5]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[4]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[5]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[6]
BitsDestination
MAIN[1][27][15]MAIN[1][26][15]MAIN[1][27][14]MAIN[1][26][14]MAIN[1][27][13]MAIN[1][26][13]MAIN[1][27][12]MAIN[1][26][12]MAIN[1][26][10]MAIN[1][27][9]MAIN[1][26][9]MAIN[1][27][8]MAIN[1][26][8]MAIN[1][26][4]CELL[1].IMUX_BUFG_O[6]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[6]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[6]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[7]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[7]
BitsDestination
MAIN[1][29][15]MAIN[1][28][15]MAIN[1][29][14]MAIN[1][28][14]MAIN[1][29][13]MAIN[1][28][13]MAIN[1][29][12]MAIN[1][28][12]MAIN[1][28][10]MAIN[1][29][9]MAIN[1][28][9]MAIN[1][29][8]MAIN[1][28][8]MAIN[1][28][4]CELL[1].IMUX_BUFG_O[7]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[7]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[6]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[7]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[8]
BitsDestination
MAIN[1][27][31]MAIN[1][26][31]MAIN[1][27][30]MAIN[1][26][30]MAIN[1][27][29]MAIN[1][26][29]MAIN[1][27][28]MAIN[1][26][28]MAIN[1][26][26]MAIN[1][27][25]MAIN[1][26][25]MAIN[1][27][24]MAIN[1][26][24]MAIN[1][26][20]CELL[1].IMUX_BUFG_O[8]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[8]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[8]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[9]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[9]
BitsDestination
MAIN[1][29][31]MAIN[1][28][31]MAIN[1][29][30]MAIN[1][28][30]MAIN[1][29][29]MAIN[1][28][29]MAIN[1][29][28]MAIN[1][28][28]MAIN[1][28][26]MAIN[1][29][25]MAIN[1][28][25]MAIN[1][29][24]MAIN[1][28][24]MAIN[1][28][20]CELL[1].IMUX_BUFG_O[9]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[9]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[8]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[9]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[10]
BitsDestination
MAIN[1][27][47]MAIN[1][26][47]MAIN[1][27][46]MAIN[1][26][46]MAIN[1][27][45]MAIN[1][26][45]MAIN[1][27][44]MAIN[1][26][44]MAIN[1][26][42]MAIN[1][27][41]MAIN[1][26][41]MAIN[1][27][40]MAIN[1][26][40]MAIN[1][26][36]CELL[1].IMUX_BUFG_O[10]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[10]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[10]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[11]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[11]
BitsDestination
MAIN[1][29][47]MAIN[1][28][47]MAIN[1][29][46]MAIN[1][28][46]MAIN[1][29][45]MAIN[1][28][45]MAIN[1][29][44]MAIN[1][28][44]MAIN[1][28][42]MAIN[1][29][41]MAIN[1][28][41]MAIN[1][29][40]MAIN[1][28][40]MAIN[1][28][36]CELL[1].IMUX_BUFG_O[11]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[11]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[10]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[11]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[12]
BitsDestination
MAIN[1][27][63]MAIN[1][26][63]MAIN[1][27][62]MAIN[1][26][62]MAIN[1][27][61]MAIN[1][26][61]MAIN[1][27][60]MAIN[1][26][60]MAIN[1][26][58]MAIN[1][27][57]MAIN[1][26][57]MAIN[1][27][56]MAIN[1][26][56]MAIN[1][26][52]CELL[1].IMUX_BUFG_O[12]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[12]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[12]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[13]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[13]
BitsDestination
MAIN[1][29][63]MAIN[1][28][63]MAIN[1][29][62]MAIN[1][28][62]MAIN[1][29][61]MAIN[1][28][61]MAIN[1][29][60]MAIN[1][28][60]MAIN[1][28][58]MAIN[1][29][57]MAIN[1][28][57]MAIN[1][29][56]MAIN[1][28][56]MAIN[1][28][52]CELL[1].IMUX_BUFG_O[13]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[13]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[12]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[13]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[14]
BitsDestination
MAIN[2][27][15]MAIN[2][26][15]MAIN[2][27][14]MAIN[2][26][14]MAIN[2][27][13]MAIN[2][26][13]MAIN[2][27][12]MAIN[2][26][12]MAIN[2][26][10]MAIN[2][27][9]MAIN[2][26][9]MAIN[2][27][8]MAIN[2][26][8]MAIN[2][26][4]CELL[1].IMUX_BUFG_O[14]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[14]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[14]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[15]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[15]
BitsDestination
MAIN[2][29][15]MAIN[2][28][15]MAIN[2][29][14]MAIN[2][28][14]MAIN[2][29][13]MAIN[2][28][13]MAIN[2][29][12]MAIN[2][28][12]MAIN[2][28][10]MAIN[2][29][9]MAIN[2][28][9]MAIN[2][29][8]MAIN[2][28][8]MAIN[2][28][4]CELL[1].IMUX_BUFG_O[15]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[15]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[14]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[15]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[16]
BitsDestination
MAIN[5][27][63]MAIN[5][26][63]MAIN[5][27][62]MAIN[5][26][62]MAIN[5][27][61]MAIN[5][26][61]MAIN[5][27][60]MAIN[5][26][60]MAIN[5][26][58]MAIN[5][27][57]MAIN[5][26][57]MAIN[5][27][56]MAIN[5][26][56]MAIN[5][26][52]CELL[1].IMUX_BUFG_O[16]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[16]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[16]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[17]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[17]
BitsDestination
MAIN[5][29][63]MAIN[5][28][63]MAIN[5][29][62]MAIN[5][28][62]MAIN[5][29][61]MAIN[5][28][61]MAIN[5][29][60]MAIN[5][28][60]MAIN[5][28][58]MAIN[5][29][57]MAIN[5][28][57]MAIN[5][29][56]MAIN[5][28][56]MAIN[5][28][52]CELL[1].IMUX_BUFG_O[17]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[17]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[16]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[17]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[18]
BitsDestination
MAIN[6][27][15]MAIN[6][26][15]MAIN[6][27][14]MAIN[6][26][14]MAIN[6][27][13]MAIN[6][26][13]MAIN[6][27][12]MAIN[6][26][12]MAIN[6][26][10]MAIN[6][27][9]MAIN[6][26][9]MAIN[6][27][8]MAIN[6][26][8]MAIN[6][26][4]CELL[1].IMUX_BUFG_O[18]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[18]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[18]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[19]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[19]
BitsDestination
MAIN[6][29][15]MAIN[6][28][15]MAIN[6][29][14]MAIN[6][28][14]MAIN[6][29][13]MAIN[6][28][13]MAIN[6][29][12]MAIN[6][28][12]MAIN[6][28][10]MAIN[6][29][9]MAIN[6][28][9]MAIN[6][29][8]MAIN[6][28][8]MAIN[6][28][4]CELL[1].IMUX_BUFG_O[19]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[19]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[18]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[19]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[20]
BitsDestination
MAIN[6][27][31]MAIN[6][26][31]MAIN[6][27][30]MAIN[6][26][30]MAIN[6][27][29]MAIN[6][26][29]MAIN[6][27][28]MAIN[6][26][28]MAIN[6][26][26]MAIN[6][27][25]MAIN[6][26][25]MAIN[6][27][24]MAIN[6][26][24]MAIN[6][26][20]CELL[1].IMUX_BUFG_O[20]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[20]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[20]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[21]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[21]
BitsDestination
MAIN[6][29][31]MAIN[6][28][31]MAIN[6][29][30]MAIN[6][28][30]MAIN[6][29][29]MAIN[6][28][29]MAIN[6][29][28]MAIN[6][28][28]MAIN[6][28][26]MAIN[6][29][25]MAIN[6][28][25]MAIN[6][29][24]MAIN[6][28][24]MAIN[6][28][20]CELL[1].IMUX_BUFG_O[21]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[21]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[20]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[21]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[22]
BitsDestination
MAIN[6][27][47]MAIN[6][26][47]MAIN[6][27][46]MAIN[6][26][46]MAIN[6][27][45]MAIN[6][26][45]MAIN[6][27][44]MAIN[6][26][44]MAIN[6][26][42]MAIN[6][27][41]MAIN[6][26][41]MAIN[6][27][40]MAIN[6][26][40]MAIN[6][26][36]CELL[1].IMUX_BUFG_O[22]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[22]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[22]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[23]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[23]
BitsDestination
MAIN[6][29][47]MAIN[6][28][47]MAIN[6][29][46]MAIN[6][28][46]MAIN[6][29][45]MAIN[6][28][45]MAIN[6][29][44]MAIN[6][28][44]MAIN[6][28][42]MAIN[6][29][41]MAIN[6][28][41]MAIN[6][29][40]MAIN[6][28][40]MAIN[6][28][36]CELL[1].IMUX_BUFG_O[23]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[23]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[22]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[23]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[24]
BitsDestination
MAIN[6][27][63]MAIN[6][26][63]MAIN[6][27][62]MAIN[6][26][62]MAIN[6][27][61]MAIN[6][26][61]MAIN[6][27][60]MAIN[6][26][60]MAIN[6][26][58]MAIN[6][27][57]MAIN[6][26][57]MAIN[6][27][56]MAIN[6][26][56]MAIN[6][26][52]CELL[1].IMUX_BUFG_O[24]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[24]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[24]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[25]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[25]
BitsDestination
MAIN[6][29][63]MAIN[6][28][63]MAIN[6][29][62]MAIN[6][28][62]MAIN[6][29][61]MAIN[6][28][61]MAIN[6][29][60]MAIN[6][28][60]MAIN[6][28][58]MAIN[6][29][57]MAIN[6][28][57]MAIN[6][29][56]MAIN[6][28][56]MAIN[6][28][52]CELL[1].IMUX_BUFG_O[25]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[25]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[24]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[25]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[26]
BitsDestination
MAIN[7][27][15]MAIN[7][26][15]MAIN[7][27][14]MAIN[7][26][14]MAIN[7][27][13]MAIN[7][26][13]MAIN[7][27][12]MAIN[7][26][12]MAIN[7][26][10]MAIN[7][27][9]MAIN[7][26][9]MAIN[7][27][8]MAIN[7][26][8]MAIN[7][26][4]CELL[1].IMUX_BUFG_O[26]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[26]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[26]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[27]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[27]
BitsDestination
MAIN[7][29][15]MAIN[7][28][15]MAIN[7][29][14]MAIN[7][28][14]MAIN[7][29][13]MAIN[7][28][13]MAIN[7][29][12]MAIN[7][28][12]MAIN[7][28][10]MAIN[7][29][9]MAIN[7][28][9]MAIN[7][29][8]MAIN[7][28][8]MAIN[7][28][4]CELL[1].IMUX_BUFG_O[27]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[27]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[26]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[27]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[28]
BitsDestination
MAIN[7][27][31]MAIN[7][26][31]MAIN[7][27][30]MAIN[7][26][30]MAIN[7][27][29]MAIN[7][26][29]MAIN[7][27][28]MAIN[7][26][28]MAIN[7][26][26]MAIN[7][27][25]MAIN[7][26][25]MAIN[7][27][24]MAIN[7][26][24]MAIN[7][26][20]CELL[1].IMUX_BUFG_O[28]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[28]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[28]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[29]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[29]
BitsDestination
MAIN[7][29][31]MAIN[7][28][31]MAIN[7][29][30]MAIN[7][28][30]MAIN[7][29][29]MAIN[7][28][29]MAIN[7][29][28]MAIN[7][28][28]MAIN[7][28][26]MAIN[7][29][25]MAIN[7][28][25]MAIN[7][29][24]MAIN[7][28][24]MAIN[7][28][20]CELL[1].IMUX_BUFG_O[29]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[29]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[28]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[29]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[30]
BitsDestination
MAIN[7][27][47]MAIN[7][26][47]MAIN[7][27][46]MAIN[7][26][46]MAIN[7][27][45]MAIN[7][26][45]MAIN[7][27][44]MAIN[7][26][44]MAIN[7][26][42]MAIN[7][27][41]MAIN[7][26][41]MAIN[7][27][40]MAIN[7][26][40]MAIN[7][26][36]CELL[1].IMUX_BUFG_O[30]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[30]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[30]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[31]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFG_O[31]
BitsDestination
MAIN[7][29][47]MAIN[7][28][47]MAIN[7][29][46]MAIN[7][28][46]MAIN[7][29][45]MAIN[7][28][45]MAIN[7][29][44]MAIN[7][28][44]MAIN[7][28][42]MAIN[7][29][41]MAIN[7][28][41]MAIN[7][29][40]MAIN[7][28][40]MAIN[7][28][36]CELL[1].IMUX_BUFG_O[31]
Source
00000000000000off
00000000000001CELL[1].IMUX_BUFG_I[31]
00000001000010CELL[1].HROW_I_HROW_W[0]
00000001000100CELL[1].HROW_I_HROW_W[8]
00000001001000CELL[1].HROW_I_HROW_E[0]
00000001010000CELL[1].HROW_I_HROW_E[8]
00000001100000CELL[1].RCLK_HROW_W[0]
00000010000010CELL[1].HROW_I_HROW_W[1]
00000010000100CELL[1].HROW_I_HROW_W[9]
00000010001000CELL[1].HROW_I_HROW_E[1]
00000010010000CELL[1].HROW_I_HROW_E[9]
00000010100000CELL[1].RCLK_HROW_W[1]
00000100000010CELL[1].HROW_I_HROW_W[2]
00000100000100CELL[1].HROW_I_HROW_W[10]
00000100001000CELL[1].HROW_I_HROW_E[2]
00000100010000CELL[1].HROW_I_HROW_E[10]
00000100100000CELL[1].RCLK_HROW_W[2]
00001000000010CELL[1].HROW_I_HROW_W[3]
00001000000100CELL[1].HROW_I_HROW_W[11]
00001000001000CELL[1].HROW_I_HROW_E[3]
00001000010000CELL[1].HROW_I_HROW_E[11]
00001000100000CELL[1].RCLK_HROW_W[3]
00010000000010CELL[1].HROW_I_HROW_W[4]
00010000000100CELL[1].HROW_I_HROW_W[12]
00010000001000CELL[1].HROW_I_HROW_E[4]
00010000010000CELL[1].HROW_I_HROW_E[12]
00010000100000CELL[1].RCLK_HROW_E[0]
00100000000010CELL[1].HROW_I_HROW_W[5]
00100000000100CELL[1].HROW_I_HROW_W[13]
00100000001000CELL[1].HROW_I_HROW_E[5]
00100000010000CELL[1].HROW_I_HROW_E[13]
00100000100000CELL[1].RCLK_HROW_E[1]
01000000000010CELL[1].HROW_I_HROW_W[6]
01000000000100CELL[1].BUFH_TEST_W
01000000001000CELL[1].HROW_I_HROW_E[6]
01000000010000CELL[1].GCLK_TEST[30]
01000000100000CELL[1].RCLK_HROW_E[2]
10000000000010CELL[1].HROW_I_HROW_W[7]
10000000000100CELL[1].BUFH_TEST_E
10000000001000CELL[1].HROW_I_HROW_E[7]
10000000010000CELL[1].GCLK_TEST[31]
10000000100000CELL[1].RCLK_HROW_E[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes BUFH_TEST_W_IN
BitsDestination
MAIN[4][26][2]MAIN[4][27][1]MAIN[4][26][1]MAIN[4][27][0]HCLK[27][17]HCLK[26][17]HCLK[27][16]HCLK[26][16]CELL[1].BUFH_TEST_W_IN
Source
00000000off
00010001CELL[1].HROW_I_HROW_W[0]
00010010CELL[1].HROW_I_HROW_W[4]
00010100CELL[1].HROW_I_HROW_W[8]
00011000CELL[1].HROW_I_HROW_W[12]
00100001CELL[1].HROW_I_HROW_W[1]
00100010CELL[1].HROW_I_HROW_W[5]
00100100CELL[1].HROW_I_HROW_W[9]
00101000CELL[1].HROW_I_HROW_W[13]
01000001CELL[1].HROW_I_HROW_W[2]
01000010CELL[1].HROW_I_HROW_W[6]
01000100CELL[1].HROW_I_HROW_W[10]
10000001CELL[1].HROW_I_HROW_W[3]
10000010CELL[1].HROW_I_HROW_W[7]
10000100CELL[1].HROW_I_HROW_W[11]
virtex7 CLK_HROW switchbox SPEC_INT muxes BUFH_TEST_E_IN
BitsDestination
MAIN[4][28][2]MAIN[4][29][1]MAIN[4][28][1]MAIN[4][29][0]HCLK[29][17]HCLK[28][17]HCLK[29][16]HCLK[28][16]CELL[1].BUFH_TEST_E_IN
Source
00000000off
00010001CELL[1].HROW_I_HROW_E[0]
00010010CELL[1].HROW_I_HROW_E[4]
00010100CELL[1].HROW_I_HROW_E[8]
00011000CELL[1].HROW_I_HROW_E[12]
00100001CELL[1].HROW_I_HROW_E[1]
00100010CELL[1].HROW_I_HROW_E[5]
00100100CELL[1].HROW_I_HROW_E[9]
00101000CELL[1].HROW_I_HROW_E[13]
01000001CELL[1].HROW_I_HROW_E[2]
01000010CELL[1].HROW_I_HROW_E[6]
01000100CELL[1].HROW_I_HROW_E[10]
10000001CELL[1].HROW_I_HROW_E[3]
10000010CELL[1].HROW_I_HROW_E[7]
10000100CELL[1].HROW_I_HROW_E[11]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_W[0]
BitsDestination
MAIN[3][27][31]MAIN[3][26][31]MAIN[3][27][30]MAIN[3][26][30]MAIN[3][27][29]MAIN[3][26][29]MAIN[3][27][28]MAIN[3][26][28]MAIN[3][27][25]MAIN[3][26][25]MAIN[3][27][24]MAIN[3][26][24]MAIN[3][26][26]MAIN[3][27][26]MAIN[3][26][27]MAIN[3][27][27]CELL[1].IMUX_BUFHCE_W[0]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[2]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_W[1]
BitsDestination
MAIN[3][29][31]MAIN[3][28][31]MAIN[3][29][30]MAIN[3][28][30]MAIN[3][29][29]MAIN[3][28][29]MAIN[3][29][28]MAIN[3][28][28]MAIN[3][29][25]MAIN[3][28][25]MAIN[3][29][24]MAIN[3][28][24]MAIN[3][28][26]MAIN[3][29][26]MAIN[3][28][27]MAIN[3][29][27]CELL[1].IMUX_BUFHCE_W[1]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[2]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_W[2]
BitsDestination
MAIN[3][27][47]MAIN[3][26][47]MAIN[3][27][46]MAIN[3][26][46]MAIN[3][27][45]MAIN[3][26][45]MAIN[3][27][44]MAIN[3][26][44]MAIN[3][27][41]MAIN[3][26][41]MAIN[3][27][40]MAIN[3][26][40]MAIN[3][26][42]MAIN[3][27][42]MAIN[3][26][43]MAIN[3][27][43]CELL[1].IMUX_BUFHCE_W[2]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[2]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_W[3]
BitsDestination
MAIN[3][29][47]MAIN[3][28][47]MAIN[3][29][46]MAIN[3][28][46]MAIN[3][29][45]MAIN[3][28][45]MAIN[3][29][44]MAIN[3][28][44]MAIN[3][29][41]MAIN[3][28][41]MAIN[3][29][40]MAIN[3][28][40]MAIN[3][28][42]MAIN[3][29][42]MAIN[3][28][43]MAIN[3][29][43]CELL[1].IMUX_BUFHCE_W[3]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[2]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_W[4]
BitsDestination
MAIN[3][27][63]MAIN[3][26][63]MAIN[3][27][62]MAIN[3][26][62]MAIN[3][27][61]MAIN[3][26][61]MAIN[3][27][60]MAIN[3][26][60]MAIN[3][27][57]MAIN[3][26][57]MAIN[3][27][56]MAIN[3][26][56]MAIN[3][26][58]MAIN[3][27][58]MAIN[3][26][59]MAIN[3][27][59]CELL[1].IMUX_BUFHCE_W[4]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[2]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_W[5]
BitsDestination
MAIN[3][29][63]MAIN[3][28][63]MAIN[3][29][62]MAIN[3][28][62]MAIN[3][29][61]MAIN[3][28][61]MAIN[3][29][60]MAIN[3][28][60]MAIN[3][29][57]MAIN[3][28][57]MAIN[3][29][56]MAIN[3][28][56]MAIN[3][28][58]MAIN[3][29][58]MAIN[3][28][59]MAIN[3][29][59]CELL[1].IMUX_BUFHCE_W[5]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[2]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_W[6]
BitsDestination
MAIN[4][27][15]MAIN[4][26][15]MAIN[4][27][14]MAIN[4][26][14]MAIN[4][27][13]MAIN[4][26][13]MAIN[4][27][12]MAIN[4][26][12]MAIN[4][27][9]MAIN[4][26][9]MAIN[4][27][8]MAIN[4][26][8]MAIN[4][26][10]MAIN[4][27][10]MAIN[4][26][11]MAIN[4][27][11]CELL[1].IMUX_BUFHCE_W[6]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[0]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[1]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_W[7]
BitsDestination
MAIN[4][29][15]MAIN[4][28][15]MAIN[4][29][14]MAIN[4][28][14]MAIN[4][29][13]MAIN[4][28][13]MAIN[4][29][12]MAIN[4][28][12]MAIN[4][29][9]MAIN[4][28][9]MAIN[4][29][8]MAIN[4][28][8]MAIN[4][28][10]MAIN[4][29][10]MAIN[4][28][11]MAIN[4][29][11]CELL[1].IMUX_BUFHCE_W[7]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[0]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[1]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_W[8]
BitsDestination
MAIN[4][27][31]MAIN[4][26][31]MAIN[4][27][30]MAIN[4][26][30]MAIN[4][27][29]MAIN[4][26][29]MAIN[4][27][28]MAIN[4][26][28]MAIN[4][27][25]MAIN[4][26][25]MAIN[4][27][24]MAIN[4][26][24]MAIN[4][26][26]MAIN[4][27][26]MAIN[4][26][27]MAIN[4][27][27]CELL[1].IMUX_BUFHCE_W[8]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[0]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[1]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_W[9]
BitsDestination
MAIN[4][29][31]MAIN[4][28][31]MAIN[4][29][30]MAIN[4][28][30]MAIN[4][29][29]MAIN[4][28][29]MAIN[4][29][28]MAIN[4][28][28]MAIN[4][29][25]MAIN[4][28][25]MAIN[4][29][24]MAIN[4][28][24]MAIN[4][28][26]MAIN[4][29][26]MAIN[4][28][27]MAIN[4][29][27]CELL[1].IMUX_BUFHCE_W[9]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[0]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[1]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_W[10]
BitsDestination
MAIN[4][27][47]MAIN[4][26][47]MAIN[4][27][46]MAIN[4][26][46]MAIN[4][27][45]MAIN[4][26][45]MAIN[4][27][44]MAIN[4][26][44]MAIN[4][27][41]MAIN[4][26][41]MAIN[4][27][40]MAIN[4][26][40]MAIN[4][26][42]MAIN[4][27][42]MAIN[4][26][43]MAIN[4][27][43]CELL[1].IMUX_BUFHCE_W[10]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[0]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[1]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_W[11]
BitsDestination
MAIN[4][29][47]MAIN[4][28][47]MAIN[4][29][46]MAIN[4][28][46]MAIN[4][29][45]MAIN[4][28][45]MAIN[4][29][44]MAIN[4][28][44]MAIN[4][29][41]MAIN[4][28][41]MAIN[4][29][40]MAIN[4][28][40]MAIN[4][28][42]MAIN[4][29][42]MAIN[4][28][43]MAIN[4][29][43]CELL[1].IMUX_BUFHCE_W[11]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[0]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[1]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_E[0]
BitsDestination
MAIN[2][27][47]MAIN[2][26][47]MAIN[2][27][46]MAIN[2][26][46]MAIN[2][27][45]MAIN[2][26][45]MAIN[2][27][44]MAIN[2][26][44]MAIN[2][27][41]MAIN[2][26][41]MAIN[2][27][40]MAIN[2][26][40]MAIN[2][26][42]MAIN[2][27][42]MAIN[2][26][43]MAIN[2][27][43]CELL[1].IMUX_BUFHCE_E[0]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[0]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[1]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_E[1]
BitsDestination
MAIN[2][29][47]MAIN[2][28][47]MAIN[2][29][46]MAIN[2][28][46]MAIN[2][29][45]MAIN[2][28][45]MAIN[2][29][44]MAIN[2][28][44]MAIN[2][29][41]MAIN[2][28][41]MAIN[2][29][40]MAIN[2][28][40]MAIN[2][28][42]MAIN[2][29][42]MAIN[2][28][43]MAIN[2][29][43]CELL[1].IMUX_BUFHCE_E[1]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[0]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[1]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_E[2]
BitsDestination
MAIN[2][27][63]MAIN[2][26][63]MAIN[2][27][62]MAIN[2][26][62]MAIN[2][27][61]MAIN[2][26][61]MAIN[2][27][60]MAIN[2][26][60]MAIN[2][27][57]MAIN[2][26][57]MAIN[2][27][56]MAIN[2][26][56]MAIN[2][26][58]MAIN[2][27][58]MAIN[2][26][59]MAIN[2][27][59]CELL[1].IMUX_BUFHCE_E[2]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[0]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[1]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_E[3]
BitsDestination
MAIN[2][29][63]MAIN[2][28][63]MAIN[2][29][62]MAIN[2][28][62]MAIN[2][29][61]MAIN[2][28][61]MAIN[2][29][60]MAIN[2][28][60]MAIN[2][29][57]MAIN[2][28][57]MAIN[2][29][56]MAIN[2][28][56]MAIN[2][28][58]MAIN[2][29][58]MAIN[2][28][59]MAIN[2][29][59]CELL[1].IMUX_BUFHCE_E[3]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[0]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[1]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_E[4]
BitsDestination
MAIN[3][27][15]MAIN[3][26][15]MAIN[3][27][14]MAIN[3][26][14]MAIN[3][27][13]MAIN[3][26][13]MAIN[3][27][12]MAIN[3][26][12]MAIN[3][27][9]MAIN[3][26][9]MAIN[3][27][8]MAIN[3][26][8]MAIN[3][26][10]MAIN[3][27][10]MAIN[3][26][11]MAIN[3][27][11]CELL[1].IMUX_BUFHCE_E[4]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[0]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[1]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_E[5]
BitsDestination
MAIN[3][29][15]MAIN[3][28][15]MAIN[3][29][14]MAIN[3][28][14]MAIN[3][29][13]MAIN[3][28][13]MAIN[3][29][12]MAIN[3][28][12]MAIN[3][29][9]MAIN[3][28][9]MAIN[3][29][8]MAIN[3][28][8]MAIN[3][28][10]MAIN[3][29][10]MAIN[3][28][11]MAIN[3][29][11]CELL[1].IMUX_BUFHCE_E[5]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[0]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[1]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_E[6]
BitsDestination
MAIN[4][27][63]MAIN[4][26][63]MAIN[4][27][62]MAIN[4][26][62]MAIN[4][27][61]MAIN[4][26][61]MAIN[4][27][60]MAIN[4][26][60]MAIN[4][27][57]MAIN[4][26][57]MAIN[4][27][56]MAIN[4][26][56]MAIN[4][26][58]MAIN[4][27][58]MAIN[4][26][59]MAIN[4][27][59]CELL[1].IMUX_BUFHCE_E[6]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[2]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_E[7]
BitsDestination
MAIN[4][29][63]MAIN[4][28][63]MAIN[4][29][62]MAIN[4][28][62]MAIN[4][29][61]MAIN[4][28][61]MAIN[4][29][60]MAIN[4][28][60]MAIN[4][29][57]MAIN[4][28][57]MAIN[4][29][56]MAIN[4][28][56]MAIN[4][28][58]MAIN[4][29][58]MAIN[4][28][59]MAIN[4][29][59]CELL[1].IMUX_BUFHCE_E[7]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[2]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_E[8]
BitsDestination
MAIN[5][27][15]MAIN[5][26][15]MAIN[5][27][14]MAIN[5][26][14]MAIN[5][27][13]MAIN[5][26][13]MAIN[5][27][12]MAIN[5][26][12]MAIN[5][27][9]MAIN[5][26][9]MAIN[5][27][8]MAIN[5][26][8]MAIN[5][26][10]MAIN[5][27][10]MAIN[5][26][11]MAIN[5][27][11]CELL[1].IMUX_BUFHCE_E[8]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[2]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_E[9]
BitsDestination
MAIN[5][29][15]MAIN[5][28][15]MAIN[5][29][14]MAIN[5][28][14]MAIN[5][29][13]MAIN[5][28][13]MAIN[5][29][12]MAIN[5][28][12]MAIN[5][29][9]MAIN[5][28][9]MAIN[5][29][8]MAIN[5][28][8]MAIN[5][28][10]MAIN[5][29][10]MAIN[5][28][11]MAIN[5][29][11]CELL[1].IMUX_BUFHCE_E[9]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[2]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_E[10]
BitsDestination
MAIN[5][27][31]MAIN[5][26][31]MAIN[5][27][30]MAIN[5][26][30]MAIN[5][27][29]MAIN[5][26][29]MAIN[5][27][28]MAIN[5][26][28]MAIN[5][27][25]MAIN[5][26][25]MAIN[5][27][24]MAIN[5][26][24]MAIN[5][26][26]MAIN[5][27][26]MAIN[5][26][27]MAIN[5][27][27]CELL[1].IMUX_BUFHCE_E[10]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[2]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[3]
virtex7 CLK_HROW switchbox SPEC_INT muxes IMUX_BUFHCE_E[11]
BitsDestination
MAIN[5][29][31]MAIN[5][28][31]MAIN[5][29][30]MAIN[5][28][30]MAIN[5][29][29]MAIN[5][28][29]MAIN[5][29][28]MAIN[5][28][28]MAIN[5][29][25]MAIN[5][28][25]MAIN[5][29][24]MAIN[5][28][24]MAIN[5][28][26]MAIN[5][29][26]MAIN[5][28][27]MAIN[5][29][27]CELL[1].IMUX_BUFHCE_E[11]
Source
0000000000000000off
0000000100000001CELL[1].GCLK_HROW[0]
0000000100000010CELL[1].GCLK_HROW[8]
0000000100000100CELL[1].GCLK_HROW[16]
0000000100001000CELL[1].GCLK_HROW[24]
0000000100010000CELL[1].HROW_I_HROW_W[0]
0000000100100000CELL[1].HROW_I_HROW_W[8]
0000000101000000CELL[1].HROW_I_HROW_E[0]
0000000110000000CELL[1].HROW_I_HROW_E[8]
0000001000000001CELL[1].GCLK_HROW[1]
0000001000000010CELL[1].GCLK_HROW[9]
0000001000000100CELL[1].GCLK_HROW[17]
0000001000001000CELL[1].GCLK_HROW[25]
0000001000010000CELL[1].HROW_I_HROW_W[1]
0000001000100000CELL[1].HROW_I_HROW_W[9]
0000001001000000CELL[1].HROW_I_HROW_E[1]
0000001010000000CELL[1].HROW_I_HROW_E[9]
0000010000000001CELL[1].GCLK_HROW[2]
0000010000000010CELL[1].GCLK_HROW[10]
0000010000000100CELL[1].GCLK_HROW[18]
0000010000001000CELL[1].GCLK_HROW[26]
0000010000010000CELL[1].HROW_I_HROW_W[2]
0000010000100000CELL[1].HROW_I_HROW_W[10]
0000010001000000CELL[1].HROW_I_HROW_E[2]
0000010010000000CELL[1].HROW_I_HROW_E[10]
0000100000000001CELL[1].GCLK_HROW[3]
0000100000000010CELL[1].GCLK_HROW[11]
0000100000000100CELL[1].GCLK_HROW[19]
0000100000001000CELL[1].GCLK_HROW[27]
0000100000010000CELL[1].HROW_I_HROW_W[3]
0000100000100000CELL[1].HROW_I_HROW_W[11]
0000100001000000CELL[1].HROW_I_HROW_E[3]
0000100010000000CELL[1].HROW_I_HROW_E[11]
0001000000000001CELL[1].GCLK_HROW[4]
0001000000000010CELL[1].GCLK_HROW[12]
0001000000000100CELL[1].GCLK_HROW[20]
0001000000001000CELL[1].GCLK_HROW[28]
0001000000010000CELL[1].HROW_I_HROW_W[4]
0001000000100000CELL[1].HROW_I_HROW_W[12]
0001000001000000CELL[1].HROW_I_HROW_E[4]
0001000010000000CELL[1].HROW_I_HROW_E[12]
0010000000000001CELL[1].GCLK_HROW[5]
0010000000000010CELL[1].GCLK_HROW[13]
0010000000000100CELL[1].GCLK_HROW[21]
0010000000001000CELL[1].GCLK_HROW[29]
0010000000010000CELL[1].HROW_I_HROW_W[5]
0010000000100000CELL[1].HROW_I_HROW_W[13]
0010000001000000CELL[1].HROW_I_HROW_E[5]
0010000010000000CELL[1].HROW_I_HROW_E[13]
0100000000000001CELL[1].GCLK_HROW[6]
0100000000000010CELL[1].GCLK_HROW[14]
0100000000000100CELL[1].GCLK_HROW[22]
0100000000001000CELL[1].GCLK_HROW[30]
0100000000010000CELL[1].HROW_I_HROW_W[6]
0100000000100000CELL[1].BUFH_TEST_W
0100000001000000CELL[1].HROW_I_HROW_E[6]
0100000010000000CELL[1].CKINT_HROW[2]
1000000000000001CELL[1].GCLK_HROW[7]
1000000000000010CELL[1].GCLK_HROW[15]
1000000000000100CELL[1].GCLK_HROW[23]
1000000000001000CELL[1].GCLK_HROW[31]
1000000000010000CELL[1].HROW_I_HROW_W[7]
1000000000100000CELL[1].BUFH_TEST_E
1000000001000000CELL[1].HROW_I_HROW_E[7]
1000000010000000CELL[1].CKINT_HROW[3]

Bels BUFHCE

virtex7 CLK_HROW bel BUFHCE pins
PinDirectionBUFHCE_W[0]BUFHCE_W[1]BUFHCE_W[2]BUFHCE_W[3]BUFHCE_W[4]BUFHCE_W[5]BUFHCE_W[6]BUFHCE_W[7]BUFHCE_W[8]BUFHCE_W[9]BUFHCE_W[10]BUFHCE_W[11]BUFHCE_E[0]BUFHCE_E[1]BUFHCE_E[2]BUFHCE_E[3]BUFHCE_E[4]BUFHCE_E[5]BUFHCE_E[6]BUFHCE_E[7]BUFHCE_E[8]BUFHCE_E[9]BUFHCE_E[10]BUFHCE_E[11]
IinCELL[1].IMUX_BUFHCE_W[0]CELL[1].IMUX_BUFHCE_W[1]CELL[1].IMUX_BUFHCE_W[2]CELL[1].IMUX_BUFHCE_W[3]CELL[1].IMUX_BUFHCE_W[4]CELL[1].IMUX_BUFHCE_W[5]CELL[1].IMUX_BUFHCE_W[6]CELL[1].IMUX_BUFHCE_W[7]CELL[1].IMUX_BUFHCE_W[8]CELL[1].IMUX_BUFHCE_W[9]CELL[1].IMUX_BUFHCE_W[10]CELL[1].IMUX_BUFHCE_W[11]CELL[1].IMUX_BUFHCE_E[0]CELL[1].IMUX_BUFHCE_E[1]CELL[1].IMUX_BUFHCE_E[2]CELL[1].IMUX_BUFHCE_E[3]CELL[1].IMUX_BUFHCE_E[4]CELL[1].IMUX_BUFHCE_E[5]CELL[1].IMUX_BUFHCE_E[6]CELL[1].IMUX_BUFHCE_E[7]CELL[1].IMUX_BUFHCE_E[8]CELL[1].IMUX_BUFHCE_E[9]CELL[1].IMUX_BUFHCE_E[10]CELL[1].IMUX_BUFHCE_E[11]
CEinCELL[0].IMUX_IMUX[6] invert by !MAIN[3][27][19]CELL[0].IMUX_IMUX[7] invert by !MAIN[3][29][19]CELL[0].IMUX_IMUX[8] invert by !MAIN[3][27][35]CELL[0].IMUX_IMUX[9] invert by !MAIN[3][29][35]CELL[0].IMUX_IMUX[10] invert by !MAIN[3][27][51]CELL[0].IMUX_IMUX[11] invert by !MAIN[3][29][51]CELL[1].IMUX_IMUX[0] invert by !MAIN[4][27][3]CELL[1].IMUX_IMUX[1] invert by !MAIN[4][29][3]CELL[1].IMUX_IMUX[2] invert by !MAIN[4][27][19]CELL[1].IMUX_IMUX[3] invert by !MAIN[4][29][19]CELL[1].IMUX_IMUX[4] invert by !MAIN[4][27][35]CELL[1].IMUX_IMUX[5] invert by !MAIN[4][29][35]CELL[0].IMUX_IMUX[0] invert by !MAIN[2][27][35]CELL[0].IMUX_IMUX[1] invert by !MAIN[2][29][35]CELL[0].IMUX_IMUX[2] invert by !MAIN[2][27][51]CELL[0].IMUX_IMUX[3] invert by !MAIN[2][29][51]CELL[0].IMUX_IMUX[4] invert by !MAIN[3][27][3]CELL[0].IMUX_IMUX[5] invert by !MAIN[3][29][3]CELL[1].IMUX_IMUX[6] invert by !MAIN[4][27][51]CELL[1].IMUX_IMUX[7] invert by !MAIN[4][29][51]CELL[1].IMUX_IMUX[8] invert by !MAIN[5][27][3]CELL[1].IMUX_IMUX[9] invert by !MAIN[5][29][3]CELL[1].IMUX_IMUX[10] invert by !MAIN[5][27][19]CELL[1].IMUX_IMUX[11] invert by !MAIN[5][29][19]
OoutCELL[1].HCLK_ROW[0]CELL[1].HCLK_ROW[1]CELL[1].HCLK_ROW[2]CELL[1].HCLK_ROW[3]CELL[1].HCLK_ROW[4]CELL[1].HCLK_ROW[5]CELL[1].HCLK_ROW[6]CELL[1].HCLK_ROW[7]CELL[1].HCLK_ROW[8]CELL[1].HCLK_ROW[9]CELL[1].HCLK_ROW[10]CELL[1].HCLK_ROW[11]CELL_E.HCLK_ROW[0]CELL_E.HCLK_ROW[1]CELL_E.HCLK_ROW[2]CELL_E.HCLK_ROW[3]CELL_E.HCLK_ROW[4]CELL_E.HCLK_ROW[5]CELL_E.HCLK_ROW[6]CELL_E.HCLK_ROW[7]CELL_E.HCLK_ROW[8]CELL_E.HCLK_ROW[9]CELL_E.HCLK_ROW[10]CELL_E.HCLK_ROW[11]
virtex7 CLK_HROW bel BUFHCE attribute bits
AttributeBUFHCE_W[0]BUFHCE_W[1]BUFHCE_W[2]BUFHCE_W[3]BUFHCE_W[4]BUFHCE_W[5]BUFHCE_W[6]BUFHCE_W[7]BUFHCE_W[8]BUFHCE_W[9]BUFHCE_W[10]BUFHCE_W[11]BUFHCE_E[0]BUFHCE_E[1]BUFHCE_E[2]BUFHCE_E[3]BUFHCE_E[4]BUFHCE_E[5]BUFHCE_E[6]BUFHCE_E[7]BUFHCE_E[8]BUFHCE_E[9]BUFHCE_E[10]BUFHCE_E[11]
ENABLEMAIN[3][27][23]MAIN[3][29][23]MAIN[3][27][39]MAIN[3][29][39]MAIN[3][27][55]MAIN[3][29][55]MAIN[4][27][7]MAIN[4][29][7]MAIN[4][27][23]MAIN[4][29][23]MAIN[4][27][39]MAIN[4][29][39]MAIN[2][27][39]MAIN[2][29][39]MAIN[2][27][55]MAIN[2][29][55]MAIN[3][27][7]MAIN[3][29][7]MAIN[4][27][55]MAIN[4][29][55]MAIN[5][27][7]MAIN[5][29][7]MAIN[5][27][23]MAIN[5][29][23]
INIT_OUT bit 0MAIN[3][26][19]MAIN[3][28][19]MAIN[3][26][35]MAIN[3][28][35]MAIN[3][26][51]MAIN[3][28][51]MAIN[4][26][3]MAIN[4][28][3]MAIN[4][26][19]MAIN[4][28][19]MAIN[4][26][35]MAIN[4][28][35]MAIN[2][26][35]MAIN[2][28][35]MAIN[2][26][51]MAIN[2][28][51]MAIN[3][26][3]MAIN[3][28][3]MAIN[4][26][51]MAIN[4][28][51]MAIN[5][26][3]MAIN[5][28][3]MAIN[5][26][19]MAIN[5][28][19]
CE_TYPE[enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE][enum: BUFHCE_CE_TYPE]
virtex7 CLK_HROW enum BUFHCE_CE_TYPE
BUFHCE_W[0].CE_TYPEMAIN[3][27][22]
BUFHCE_W[1].CE_TYPEMAIN[3][29][22]
BUFHCE_W[2].CE_TYPEMAIN[3][27][38]
BUFHCE_W[3].CE_TYPEMAIN[3][29][38]
BUFHCE_W[4].CE_TYPEMAIN[3][27][54]
BUFHCE_W[5].CE_TYPEMAIN[3][29][54]
BUFHCE_W[6].CE_TYPEMAIN[4][27][6]
BUFHCE_W[7].CE_TYPEMAIN[4][29][6]
BUFHCE_W[8].CE_TYPEMAIN[4][27][22]
BUFHCE_W[9].CE_TYPEMAIN[4][29][22]
BUFHCE_W[10].CE_TYPEMAIN[4][27][38]
BUFHCE_W[11].CE_TYPEMAIN[4][29][38]
BUFHCE_E[0].CE_TYPEMAIN[2][27][38]
BUFHCE_E[1].CE_TYPEMAIN[2][29][38]
BUFHCE_E[2].CE_TYPEMAIN[2][27][54]
BUFHCE_E[3].CE_TYPEMAIN[2][29][54]
BUFHCE_E[4].CE_TYPEMAIN[3][27][6]
BUFHCE_E[5].CE_TYPEMAIN[3][29][6]
BUFHCE_E[6].CE_TYPEMAIN[4][27][54]
BUFHCE_E[7].CE_TYPEMAIN[4][29][54]
BUFHCE_E[8].CE_TYPEMAIN[5][27][6]
BUFHCE_E[9].CE_TYPEMAIN[5][29][6]
BUFHCE_E[10].CE_TYPEMAIN[5][27][22]
BUFHCE_E[11].CE_TYPEMAIN[5][29][22]
SYNC0
ASYNC1

Bel wires

virtex7 CLK_HROW bel wires
WirePins
CELL[0].IMUX_IMUX[0]BUFHCE_E[0].CE
CELL[0].IMUX_IMUX[1]BUFHCE_E[1].CE
CELL[0].IMUX_IMUX[2]BUFHCE_E[2].CE
CELL[0].IMUX_IMUX[3]BUFHCE_E[3].CE
CELL[0].IMUX_IMUX[4]BUFHCE_E[4].CE
CELL[0].IMUX_IMUX[5]BUFHCE_E[5].CE
CELL[0].IMUX_IMUX[6]BUFHCE_W[0].CE
CELL[0].IMUX_IMUX[7]BUFHCE_W[1].CE
CELL[0].IMUX_IMUX[8]BUFHCE_W[2].CE
CELL[0].IMUX_IMUX[9]BUFHCE_W[3].CE
CELL[0].IMUX_IMUX[10]BUFHCE_W[4].CE
CELL[0].IMUX_IMUX[11]BUFHCE_W[5].CE
CELL[1].IMUX_IMUX[0]BUFHCE_W[6].CE
CELL[1].IMUX_IMUX[1]BUFHCE_W[7].CE
CELL[1].IMUX_IMUX[2]BUFHCE_W[8].CE
CELL[1].IMUX_IMUX[3]BUFHCE_W[9].CE
CELL[1].IMUX_IMUX[4]BUFHCE_W[10].CE
CELL[1].IMUX_IMUX[5]BUFHCE_W[11].CE
CELL[1].IMUX_IMUX[6]BUFHCE_E[6].CE
CELL[1].IMUX_IMUX[7]BUFHCE_E[7].CE
CELL[1].IMUX_IMUX[8]BUFHCE_E[8].CE
CELL[1].IMUX_IMUX[9]BUFHCE_E[9].CE
CELL[1].IMUX_IMUX[10]BUFHCE_E[10].CE
CELL[1].IMUX_IMUX[11]BUFHCE_E[11].CE
CELL[1].IMUX_BUFHCE_W[0]BUFHCE_W[0].I
CELL[1].IMUX_BUFHCE_W[1]BUFHCE_W[1].I
CELL[1].IMUX_BUFHCE_W[2]BUFHCE_W[2].I
CELL[1].IMUX_BUFHCE_W[3]BUFHCE_W[3].I
CELL[1].IMUX_BUFHCE_W[4]BUFHCE_W[4].I
CELL[1].IMUX_BUFHCE_W[5]BUFHCE_W[5].I
CELL[1].IMUX_BUFHCE_W[6]BUFHCE_W[6].I
CELL[1].IMUX_BUFHCE_W[7]BUFHCE_W[7].I
CELL[1].IMUX_BUFHCE_W[8]BUFHCE_W[8].I
CELL[1].IMUX_BUFHCE_W[9]BUFHCE_W[9].I
CELL[1].IMUX_BUFHCE_W[10]BUFHCE_W[10].I
CELL[1].IMUX_BUFHCE_W[11]BUFHCE_W[11].I
CELL[1].IMUX_BUFHCE_E[0]BUFHCE_E[0].I
CELL[1].IMUX_BUFHCE_E[1]BUFHCE_E[1].I
CELL[1].IMUX_BUFHCE_E[2]BUFHCE_E[2].I
CELL[1].IMUX_BUFHCE_E[3]BUFHCE_E[3].I
CELL[1].IMUX_BUFHCE_E[4]BUFHCE_E[4].I
CELL[1].IMUX_BUFHCE_E[5]BUFHCE_E[5].I
CELL[1].IMUX_BUFHCE_E[6]BUFHCE_E[6].I
CELL[1].IMUX_BUFHCE_E[7]BUFHCE_E[7].I
CELL[1].IMUX_BUFHCE_E[8]BUFHCE_E[8].I
CELL[1].IMUX_BUFHCE_E[9]BUFHCE_E[9].I
CELL[1].IMUX_BUFHCE_E[10]BUFHCE_E[10].I
CELL[1].IMUX_BUFHCE_E[11]BUFHCE_E[11].I
CELL[1].HCLK_ROW[0]BUFHCE_W[0].O
CELL[1].HCLK_ROW[1]BUFHCE_W[1].O
CELL[1].HCLK_ROW[2]BUFHCE_W[2].O
CELL[1].HCLK_ROW[3]BUFHCE_W[3].O
CELL[1].HCLK_ROW[4]BUFHCE_W[4].O
CELL[1].HCLK_ROW[5]BUFHCE_W[5].O
CELL[1].HCLK_ROW[6]BUFHCE_W[6].O
CELL[1].HCLK_ROW[7]BUFHCE_W[7].O
CELL[1].HCLK_ROW[8]BUFHCE_W[8].O
CELL[1].HCLK_ROW[9]BUFHCE_W[9].O
CELL[1].HCLK_ROW[10]BUFHCE_W[10].O
CELL[1].HCLK_ROW[11]BUFHCE_W[11].O
CELL_E.HCLK_ROW[0]BUFHCE_E[0].O
CELL_E.HCLK_ROW[1]BUFHCE_E[1].O
CELL_E.HCLK_ROW[2]BUFHCE_E[2].O
CELL_E.HCLK_ROW[3]BUFHCE_E[3].O
CELL_E.HCLK_ROW[4]BUFHCE_E[4].O
CELL_E.HCLK_ROW[5]BUFHCE_E[5].O
CELL_E.HCLK_ROW[6]BUFHCE_E[6].O
CELL_E.HCLK_ROW[7]BUFHCE_E[7].O
CELL_E.HCLK_ROW[8]BUFHCE_E[8].O
CELL_E.HCLK_ROW[9]BUFHCE_E[9].O
CELL_E.HCLK_ROW[10]BUFHCE_E[10].O
CELL_E.HCLK_ROW[11]BUFHCE_E[11].O

Bitstream

virtex7 CLK_HROW rect MAIN[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 13
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 11
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 9
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 7
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 5 - SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 5 -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 4
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 2
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[1].GCLK_TEST[4] ← CELL[1].GCLK_TEST_IN[4] - SPEC_INT: invert CELL[1].GCLK_TEST[5] ← CELL[1].GCLK_TEST_IN[5] -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[4] ← CELL[1].GCLK_HROW[4] SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[5] ← CELL[1].GCLK_HROW[5]
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 13
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 11
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 9
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 7
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 5 - SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 5 -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 4
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 2
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[1].GCLK_TEST[2] ← CELL[1].GCLK_TEST_IN[2] - SPEC_INT: invert CELL[1].GCLK_TEST[3] ← CELL[1].GCLK_TEST_IN[3] -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[2] ← CELL[1].GCLK_HROW[2] SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[3] ← CELL[1].GCLK_HROW[3]
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 13
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 11
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 9
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 7
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 5 - SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 5 -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 4
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 2
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[1].GCLK_TEST[0] ← CELL[1].GCLK_TEST_IN[0] - SPEC_INT: invert CELL[1].GCLK_TEST[1] ← CELL[1].GCLK_TEST_IN[1] -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[0] ← CELL[1].GCLK_HROW[0] SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[1] ← CELL[1].GCLK_HROW[1]
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CLK_HROW rect MAIN[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 13
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 11
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 9
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 7
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 5 - SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 5 -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 4
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 2
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[1].GCLK_TEST[12] ← CELL[1].GCLK_TEST_IN[12] - SPEC_INT: invert CELL[1].GCLK_TEST[13] ← CELL[1].GCLK_TEST_IN[13] -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[12] ← CELL[1].GCLK_HROW[12] SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[13] ← CELL[1].GCLK_HROW[13]
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 13
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 11
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 9
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 7
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 5 - SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 5 -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 4
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 2
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[1].GCLK_TEST[10] ← CELL[1].GCLK_TEST_IN[10] - SPEC_INT: invert CELL[1].GCLK_TEST[11] ← CELL[1].GCLK_TEST_IN[11] -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[10] ← CELL[1].GCLK_HROW[10] SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[11] ← CELL[1].GCLK_HROW[11]
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 13
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 11
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 9
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 7
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 5 - SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 5 -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 4
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 2
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[1].GCLK_TEST[8] ← CELL[1].GCLK_TEST_IN[8] - SPEC_INT: invert CELL[1].GCLK_TEST[9] ← CELL[1].GCLK_TEST_IN[9] -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[8] ← CELL[1].GCLK_HROW[8] SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[9] ← CELL[1].GCLK_HROW[9]
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 13
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 11
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 9
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 7
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 5 - SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 5 -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 4
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 2
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[1].GCLK_TEST[6] ← CELL[1].GCLK_TEST_IN[6] - SPEC_INT: invert CELL[1].GCLK_TEST[7] ← CELL[1].GCLK_TEST_IN[7] -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[6] ← CELL[1].GCLK_HROW[6] SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[7] ← CELL[1].GCLK_HROW[7]
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CLK_HROW rect MAIN[2]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[2] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[2] bit 15 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[3] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[3] bit 15
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[2] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[2] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[3] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[3] bit 13
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[2] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[2] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[3] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[3] bit 11
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[2] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[2] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[3] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[3] bit 9
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[2] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[2] bit 0 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[3] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[3] bit 0
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[2] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[2] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[3] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[3] bit 2
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[2] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[2] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[3] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[3] bit 7
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[2] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[2] bit 5 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[3] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[3] bit 5
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[2]: ENABLE - BUFHCE_E[3]: ENABLE
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[2]: CE_TYPE bit 0 - BUFHCE_E[3]: CE_TYPE bit 0
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[2]: INIT_OUT bit 0 BUFHCE_E[2]: !invert CE BUFHCE_E[3]: INIT_OUT bit 0 BUFHCE_E[3]: !invert CE
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[0] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[0] bit 15 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[1] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[1] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[0] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[0] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[1] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[1] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[0] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[0] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[1] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[1] bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[0] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[0] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[1] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[1] bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[0] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[0] bit 0 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[1] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[1] bit 0
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[0] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[0] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[1] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[1] bit 2
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[0] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[0] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[1] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[1] bit 7
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[0] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[0] bit 5 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[1] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[1] bit 5
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[0]: ENABLE - BUFHCE_E[1]: ENABLE
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[0]: CE_TYPE bit 0 - BUFHCE_E[1]: CE_TYPE bit 0
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[0]: INIT_OUT bit 0 BUFHCE_E[0]: !invert CE BUFHCE_E[1]: INIT_OUT bit 0 BUFHCE_E[1]: !invert CE
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 13
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 11
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 9
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 7
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 5 - SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 5 -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 4
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 2
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[1].GCLK_TEST[14] ← CELL[1].GCLK_TEST_IN[14] - SPEC_INT: invert CELL[1].GCLK_TEST[15] ← CELL[1].GCLK_TEST_IN[15] -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[14] ← CELL[1].GCLK_HROW[14] SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[15] ← CELL[1].GCLK_HROW[15]
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CLK_HROW rect MAIN[3]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[4] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[4] bit 15 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[5] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[5] bit 15
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[4] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[4] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[5] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[5] bit 13
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[4] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[4] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[5] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[5] bit 11
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[4] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[4] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[5] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[5] bit 9
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[4] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[4] bit 0 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[5] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[5] bit 0
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[4] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[4] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[5] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[5] bit 2
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[4] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[4] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[5] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[5] bit 7
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[4] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[4] bit 5 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[5] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[5] bit 5
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[4]: ENABLE - BUFHCE_W[5]: ENABLE
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[4]: CE_TYPE bit 0 - BUFHCE_W[5]: CE_TYPE bit 0
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[4]: INIT_OUT bit 0 BUFHCE_W[4]: !invert CE BUFHCE_W[5]: INIT_OUT bit 0 BUFHCE_W[5]: !invert CE
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].HROW_I_HROW_W[12] ← CELL[1].HROW_I[12] SPEC_INT: buffer CELL[1].HROW_I_HROW_W[13] ← CELL[1].HROW_I[13] SPEC_INT: buffer CELL[1].HROW_I_HROW_E[12] ← CELL_E.HROW_I[12] SPEC_INT: buffer CELL[1].HROW_I_HROW_E[13] ← CELL_E.HROW_I[13]
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].HROW_I_HROW_W[10] ← CELL[1].HROW_I[10] SPEC_INT: buffer CELL[1].HROW_I_HROW_W[11] ← CELL[1].HROW_I[11] SPEC_INT: buffer CELL[1].HROW_I_HROW_E[10] ← CELL_E.HROW_I[10] SPEC_INT: buffer CELL[1].HROW_I_HROW_E[11] ← CELL_E.HROW_I[11]
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[2] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[2] bit 15 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[3] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[3] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[2] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[2] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[3] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[3] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[2] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[2] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[3] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[3] bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[2] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[2] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[3] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[3] bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[2] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[2] bit 0 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[3] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[3] bit 0
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[2] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[2] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[3] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[3] bit 2
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[2] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[2] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[3] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[3] bit 7
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[2] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[2] bit 5 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[3] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[3] bit 5
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[2]: ENABLE - BUFHCE_W[3]: ENABLE
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[2]: CE_TYPE bit 0 - BUFHCE_W[3]: CE_TYPE bit 0
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[2]: INIT_OUT bit 0 BUFHCE_W[2]: !invert CE BUFHCE_W[3]: INIT_OUT bit 0 BUFHCE_W[3]: !invert CE
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[0] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[0] bit 15 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[1] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[1] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[0] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[0] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[1] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[1] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[0] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[0] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[1] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[1] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[0] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[0] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[1] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[1] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[0] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[0] bit 0 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[1] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[1] bit 0
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[0] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[0] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[1] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[1] bit 2
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[0] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[0] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[1] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[1] bit 7
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[0] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[0] bit 5 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[1] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[1] bit 5
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[0]: ENABLE - BUFHCE_W[1]: ENABLE
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[0]: CE_TYPE bit 0 - BUFHCE_W[1]: CE_TYPE bit 0
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[0]: INIT_OUT bit 0 BUFHCE_W[0]: !invert CE BUFHCE_W[1]: INIT_OUT bit 0 BUFHCE_W[1]: !invert CE
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[4] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[4] bit 15 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[5] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[5] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[4] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[4] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[5] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[5] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[4] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[4] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[5] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[5] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[4] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[4] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[5] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[5] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[4] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[4] bit 0 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[5] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[5] bit 0
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[4] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[4] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[5] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[5] bit 2
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[4] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[4] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[5] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[5] bit 7
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[4] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[4] bit 5 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[5] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[5] bit 5
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[4]: ENABLE - BUFHCE_E[5]: ENABLE
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[4]: CE_TYPE bit 0 - BUFHCE_E[5]: CE_TYPE bit 0
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[4]: INIT_OUT bit 0 BUFHCE_E[4]: !invert CE BUFHCE_E[5]: INIT_OUT bit 0 BUFHCE_E[5]: !invert CE
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CLK_HROW rect MAIN[4]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[6] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[6] bit 15 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[7] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[7] bit 15
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[6] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[6] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[7] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[7] bit 13
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[6] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[6] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[7] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[7] bit 11
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[6] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[6] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[7] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[7] bit 9
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[6] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[6] bit 0 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[7] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[7] bit 0
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[6] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[6] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[7] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[7] bit 2
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[6] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[6] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[7] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[7] bit 7
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[6] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[6] bit 5 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[7] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[7] bit 5
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[6]: ENABLE - BUFHCE_E[7]: ENABLE
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[6]: CE_TYPE bit 0 - BUFHCE_E[7]: CE_TYPE bit 0
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[6]: INIT_OUT bit 0 BUFHCE_E[6]: !invert CE BUFHCE_E[7]: INIT_OUT bit 0 BUFHCE_E[7]: !invert CE
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[10] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[10] bit 15 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[11] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[11] bit 15
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[10] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[10] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[11] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[11] bit 13
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[10] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[10] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[11] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[11] bit 11
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[10] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[10] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[11] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[11] bit 9
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[10] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[10] bit 0 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[11] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[11] bit 0
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[10] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[10] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[11] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[11] bit 2
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[10] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[10] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[11] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[11] bit 7
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[10] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[10] bit 5 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[11] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[11] bit 5
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[10]: ENABLE - BUFHCE_W[11]: ENABLE
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[10]: CE_TYPE bit 0 - BUFHCE_W[11]: CE_TYPE bit 0
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[10]: INIT_OUT bit 0 BUFHCE_W[10]: !invert CE BUFHCE_W[11]: INIT_OUT bit 0 BUFHCE_W[11]: !invert CE
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[8] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[8] bit 15 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[9] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[9] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[8] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[8] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[9] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[9] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[8] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[8] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[9] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[9] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[8] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[8] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[9] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[9] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[8] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[8] bit 0 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[9] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[9] bit 0
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[8] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[8] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[9] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[9] bit 2
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[8] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[8] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[9] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[9] bit 7
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[8] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[8] bit 5 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[9] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[9] bit 5
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[8]: ENABLE - BUFHCE_W[9]: ENABLE
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[8]: CE_TYPE bit 0 - BUFHCE_W[9]: CE_TYPE bit 0
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[8]: INIT_OUT bit 0 BUFHCE_W[8]: !invert CE BUFHCE_W[9]: INIT_OUT bit 0 BUFHCE_W[9]: !invert CE
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[6] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[6] bit 15 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[7] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[7] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[6] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[6] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[7] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[7] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[6] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[6] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[7] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[7] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[6] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[6] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[7] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[7] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[6] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[6] bit 0 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[7] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[7] bit 0
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[6] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[6] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[7] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[7] bit 2
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[6] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[6] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[7] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[7] bit 7
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[6] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[6] bit 5 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[7] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_W[7] bit 5
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[6]: ENABLE - BUFHCE_W[7]: ENABLE
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[6]: CE_TYPE bit 0 - BUFHCE_W[7]: CE_TYPE bit 0
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[6]: INIT_OUT bit 0 BUFHCE_W[6]: !invert CE BUFHCE_W[7]: INIT_OUT bit 0 BUFHCE_W[7]: !invert CE
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].BUFH_TEST_W_IN bit 7 - SPEC_INT: mux CELL[1].BUFH_TEST_E_IN bit 7 -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].BUFH_TEST_W_IN bit 5 SPEC_INT: mux CELL[1].BUFH_TEST_W_IN bit 6 SPEC_INT: mux CELL[1].BUFH_TEST_E_IN bit 5 SPEC_INT: mux CELL[1].BUFH_TEST_E_IN bit 6
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[1].BUFH_TEST_W ← CELL[1].BUFH_TEST_W_IN SPEC_INT: mux CELL[1].BUFH_TEST_W_IN bit 4 SPEC_INT: invert CELL[1].BUFH_TEST_E ← CELL[1].BUFH_TEST_E_IN SPEC_INT: mux CELL[1].BUFH_TEST_E_IN bit 4
virtex7 CLK_HROW rect MAIN[5]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 13
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 11
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 9
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 7
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 5 - SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 5 -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 4
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 2
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[1].GCLK_TEST[16] ← CELL[1].GCLK_TEST_IN[16] - SPEC_INT: invert CELL[1].GCLK_TEST[17] ← CELL[1].GCLK_TEST_IN[17] -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[16] ← CELL[1].GCLK_HROW[16] SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[17] ← CELL[1].GCLK_HROW[17]
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[10] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[10] bit 15 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[11] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[11] bit 15
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[10] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[10] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[11] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[11] bit 13
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[10] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[10] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[11] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[11] bit 11
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[10] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[10] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[11] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[11] bit 9
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[10] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[10] bit 0 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[11] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[11] bit 0
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[10] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[10] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[11] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[11] bit 2
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[10] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[10] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[11] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[11] bit 7
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[10] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[10] bit 5 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[11] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[11] bit 5
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[10]: ENABLE - BUFHCE_E[11]: ENABLE
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[10]: CE_TYPE bit 0 - BUFHCE_E[11]: CE_TYPE bit 0
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[10]: INIT_OUT bit 0 BUFHCE_E[10]: !invert CE BUFHCE_E[11]: INIT_OUT bit 0 BUFHCE_E[11]: !invert CE
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[8] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[8] bit 15 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[9] bit 14 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[9] bit 15
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[8] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[8] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[9] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[9] bit 13
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[8] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[8] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[9] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[9] bit 11
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[8] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[8] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[9] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[9] bit 9
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[8] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[8] bit 0 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[9] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[9] bit 0
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[8] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[8] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[9] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[9] bit 2
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[8] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[8] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[9] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[9] bit 7
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[8] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[8] bit 5 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[9] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFHCE_E[9] bit 5
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[8]: ENABLE - BUFHCE_E[9]: ENABLE
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[8]: CE_TYPE bit 0 - BUFHCE_E[9]: CE_TYPE bit 0
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_E[8]: INIT_OUT bit 0 BUFHCE_E[8]: !invert CE BUFHCE_E[9]: INIT_OUT bit 0 BUFHCE_E[9]: !invert CE
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CLK_HROW rect MAIN[6]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 13
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 11
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 9
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 7
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 5 - SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 5 -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 4
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 2
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[1].GCLK_TEST[24] ← CELL[1].GCLK_TEST_IN[24] - SPEC_INT: invert CELL[1].GCLK_TEST[25] ← CELL[1].GCLK_TEST_IN[25] -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[24] ← CELL[1].GCLK_HROW[24] SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[25] ← CELL[1].GCLK_HROW[25]
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 13
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 11
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 9
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 7
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 5 - SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 5 -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 4
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 2
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[1].GCLK_TEST[22] ← CELL[1].GCLK_TEST_IN[22] - SPEC_INT: invert CELL[1].GCLK_TEST[23] ← CELL[1].GCLK_TEST_IN[23] -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[22] ← CELL[1].GCLK_HROW[22] SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[23] ← CELL[1].GCLK_HROW[23]
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 13
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 11
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 9
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 7
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 5 - SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 5 -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 4
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 2
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[1].GCLK_TEST[20] ← CELL[1].GCLK_TEST_IN[20] - SPEC_INT: invert CELL[1].GCLK_TEST[21] ← CELL[1].GCLK_TEST_IN[21] -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[20] ← CELL[1].GCLK_HROW[20] SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[21] ← CELL[1].GCLK_HROW[21]
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 13
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 11
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 9
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 7
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 5 - SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 5 -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 4
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 2
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[1].GCLK_TEST[18] ← CELL[1].GCLK_TEST_IN[18] - SPEC_INT: invert CELL[1].GCLK_TEST[19] ← CELL[1].GCLK_TEST_IN[19] -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[18] ← CELL[1].GCLK_HROW[18] SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[19] ← CELL[1].GCLK_HROW[19]
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CLK_HROW rect MAIN[7]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 13
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 11
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 9
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 7
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 5 - SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 5 -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 4
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 2
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[1].GCLK_TEST[30] ← CELL[1].GCLK_TEST_IN[30] - SPEC_INT: invert CELL[1].GCLK_TEST[31] ← CELL[1].GCLK_TEST_IN[31] -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[30] ← CELL[1].GCLK_HROW[30] SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[31] ← CELL[1].GCLK_HROW[31]
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 13
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 11
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 9
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 7
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 5 - SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 5 -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 4
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 2
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[1].GCLK_TEST[28] ← CELL[1].GCLK_TEST_IN[28] - SPEC_INT: invert CELL[1].GCLK_TEST[29] ← CELL[1].GCLK_TEST_IN[29] -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[28] ← CELL[1].GCLK_HROW[28] SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[29] ← CELL[1].GCLK_HROW[29]
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 13 SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 12 SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 13
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 11 SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 10 SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 11
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 9 SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 8 SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 9
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 7 SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 6 SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 7
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 5 - SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 5 -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 4 SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 3 SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 4
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 2 SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 1 SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 2
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[1].GCLK_TEST[26] ← CELL[1].GCLK_TEST_IN[26] - SPEC_INT: invert CELL[1].GCLK_TEST[27] ← CELL[1].GCLK_TEST_IN[27] -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[26] ← CELL[1].GCLK_HROW[26] SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 0 SPEC_INT: buffer CELL[1].GCLK_TEST_IN[27] ← CELL[1].GCLK_HROW[27]
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 CLK_HROW rect HCLK
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].CKINT_HROW[0] ← CELL[0].IMUX_CLK[0] SPEC_INT: buffer CELL[1].CKINT_HROW[1] ← CELL[0].IMUX_CLK[1] SPEC_INT: buffer CELL[1].CKINT_HROW[2] ← CELL[1].IMUX_CLK[0] SPEC_INT: buffer CELL[1].CKINT_HROW[3] ← CELL[1].IMUX_CLK[1]
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].GCLK_HROW[30] ← CELL[1].GCLK[30] SPEC_INT: buffer CELL[1].GCLK_HROW[31] ← CELL[1].GCLK[31] SPEC_INT: buffer CELL[1].GCLK_HROW[14] ← CELL[1].GCLK[14] SPEC_INT: buffer CELL[1].GCLK_HROW[15] ← CELL[1].GCLK[15]
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].GCLK_HROW[28] ← CELL[1].GCLK[28] SPEC_INT: buffer CELL[1].GCLK_HROW[29] ← CELL[1].GCLK[29] SPEC_INT: buffer CELL[1].GCLK_HROW[12] ← CELL[1].GCLK[12] SPEC_INT: buffer CELL[1].GCLK_HROW[13] ← CELL[1].GCLK[13]
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].GCLK_HROW[26] ← CELL[1].GCLK[26] SPEC_INT: buffer CELL[1].GCLK_HROW[27] ← CELL[1].GCLK[27] SPEC_INT: buffer CELL[1].GCLK_HROW[10] ← CELL[1].GCLK[10] SPEC_INT: buffer CELL[1].GCLK_HROW[11] ← CELL[1].GCLK[11]
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].GCLK_HROW[24] ← CELL[1].GCLK[24] SPEC_INT: buffer CELL[1].GCLK_HROW[25] ← CELL[1].GCLK[25] SPEC_INT: buffer CELL[1].GCLK_HROW[8] ← CELL[1].GCLK[8] SPEC_INT: buffer CELL[1].GCLK_HROW[9] ← CELL[1].GCLK[9]
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].GCLK_HROW[22] ← CELL[1].GCLK[22] SPEC_INT: buffer CELL[1].GCLK_HROW[23] ← CELL[1].GCLK[23] SPEC_INT: buffer CELL[1].GCLK_HROW[6] ← CELL[1].GCLK[6] SPEC_INT: buffer CELL[1].GCLK_HROW[7] ← CELL[1].GCLK[7]
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].GCLK_HROW[20] ← CELL[1].GCLK[20] SPEC_INT: buffer CELL[1].GCLK_HROW[21] ← CELL[1].GCLK[21] SPEC_INT: buffer CELL[1].GCLK_HROW[4] ← CELL[1].GCLK[4] SPEC_INT: buffer CELL[1].GCLK_HROW[5] ← CELL[1].GCLK[5]
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].GCLK_HROW[18] ← CELL[1].GCLK[18] SPEC_INT: buffer CELL[1].GCLK_HROW[19] ← CELL[1].GCLK[19] SPEC_INT: buffer CELL[1].GCLK_HROW[2] ← CELL[1].GCLK[2] SPEC_INT: buffer CELL[1].GCLK_HROW[3] ← CELL[1].GCLK[3]
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].GCLK_HROW[16] ← CELL[1].GCLK[16] SPEC_INT: buffer CELL[1].GCLK_HROW[17] ← CELL[1].GCLK[17] SPEC_INT: buffer CELL[1].GCLK_HROW[0] ← CELL[1].GCLK[0] SPEC_INT: buffer CELL[1].GCLK_HROW[1] ← CELL[1].GCLK[1]
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].HROW_I_HROW_W[8] ← CELL[1].HROW_I[8] SPEC_INT: buffer CELL[1].HROW_I_HROW_W[9] ← CELL[1].HROW_I[9] SPEC_INT: buffer CELL[1].HROW_I_HROW_E[8] ← CELL_E.HROW_I[8] SPEC_INT: buffer CELL[1].HROW_I_HROW_E[9] ← CELL_E.HROW_I[9]
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].HROW_I_HROW_W[6] ← CELL[1].HROW_I[6] SPEC_INT: buffer CELL[1].HROW_I_HROW_W[7] ← CELL[1].HROW_I[7] SPEC_INT: buffer CELL[1].HROW_I_HROW_E[6] ← CELL_E.HROW_I[6] SPEC_INT: buffer CELL[1].HROW_I_HROW_E[7] ← CELL_E.HROW_I[7]
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].HROW_I_HROW_W[4] ← CELL[1].HROW_I[4] SPEC_INT: buffer CELL[1].HROW_I_HROW_W[5] ← CELL[1].HROW_I[5] SPEC_INT: buffer CELL[1].HROW_I_HROW_E[4] ← CELL_E.HROW_I[4] SPEC_INT: buffer CELL[1].HROW_I_HROW_E[5] ← CELL_E.HROW_I[5]
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].HROW_I_HROW_W[2] ← CELL[1].HROW_I[2] SPEC_INT: buffer CELL[1].HROW_I_HROW_W[3] ← CELL[1].HROW_I[3] SPEC_INT: buffer CELL[1].HROW_I_HROW_E[2] ← CELL_E.HROW_I[2] SPEC_INT: buffer CELL[1].HROW_I_HROW_E[3] ← CELL_E.HROW_I[3]
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].HROW_I_HROW_W[0] ← CELL[1].HROW_I[0] SPEC_INT: buffer CELL[1].HROW_I_HROW_W[1] ← CELL[1].HROW_I[1] SPEC_INT: buffer CELL[1].HROW_I_HROW_E[0] ← CELL_E.HROW_I[0] SPEC_INT: buffer CELL[1].HROW_I_HROW_E[1] ← CELL_E.HROW_I[1]
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].BUFH_TEST_W_IN bit 2 SPEC_INT: mux CELL[1].BUFH_TEST_W_IN bit 3 SPEC_INT: mux CELL[1].BUFH_TEST_E_IN bit 2 SPEC_INT: mux CELL[1].BUFH_TEST_E_IN bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].BUFH_TEST_W_IN bit 0 SPEC_INT: mux CELL[1].BUFH_TEST_W_IN bit 1 SPEC_INT: mux CELL[1].BUFH_TEST_E_IN bit 0 SPEC_INT: mux CELL[1].BUFH_TEST_E_IN bit 1
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].RCLK_HROW_W[2] ← CELL[1].RCLK_ROW[2] SPEC_INT: buffer CELL[1].RCLK_HROW_W[3] ← CELL[1].RCLK_ROW[3] SPEC_INT: buffer CELL[1].RCLK_HROW_E[2] ← CELL_E.RCLK_ROW[2] SPEC_INT: buffer CELL[1].RCLK_HROW_E[3] ← CELL_E.RCLK_ROW[3]
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[1].RCLK_HROW_W[0] ← CELL[1].RCLK_ROW[0] SPEC_INT: buffer CELL[1].RCLK_HROW_W[1] ← CELL[1].RCLK_ROW[1] SPEC_INT: buffer CELL[1].RCLK_HROW_E[0] ← CELL_E.RCLK_ROW[0] SPEC_INT: buffer CELL[1].RCLK_HROW_E[1] ← CELL_E.RCLK_ROW[1]
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -