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Clock column buffers

Tile HCLK

Cells: 2

Switchbox HCLK

virtex7 HCLK switchbox HCLK programmable buffers
DestinationSourceBit
N.HCLK_BUF[0]N.HCLK_ROW[0]MAIN[1][0][14]
N.HCLK_BUF[1]N.HCLK_ROW[1]MAIN[1][1][19]
N.HCLK_BUF[2]N.HCLK_ROW[2]MAIN[1][0][22]
N.HCLK_BUF[3]N.HCLK_ROW[3]MAIN[1][1][22]
N.HCLK_BUF[4]N.HCLK_ROW[4]MAIN[1][0][23]
N.HCLK_BUF[5]N.HCLK_ROW[5]MAIN[1][1][23]
N.HCLK_BUF[6]N.HCLK_ROW[6]MAIN[1][0][31]
N.HCLK_BUF[7]N.HCLK_ROW[7]MAIN[1][1][31]
N.HCLK_BUF[8]N.HCLK_ROW[8]MAIN[0][0][14]
N.HCLK_BUF[9]N.HCLK_ROW[9]MAIN[0][1][19]
N.HCLK_BUF[10]N.HCLK_ROW[10]MAIN[0][0][22]
N.HCLK_BUF[11]N.HCLK_ROW[11]MAIN[0][1][22]
N.RCLK_BUF[0]N.RCLK_ROW[0]MAIN[0][0][23]
N.RCLK_BUF[1]N.RCLK_ROW[1]MAIN[0][1][23]
N.RCLK_BUF[2]N.RCLK_ROW[2]MAIN[0][0][31]
N.RCLK_BUF[3]N.RCLK_ROW[3]MAIN[0][1][31]
virtex7 HCLK switchbox HCLK muxes LCLK[0]
BitsDestination
MAIN[1][3][15]MAIN[1][4][15]MAIN[1][3][14]MAIN[1][4][14]MAIN[1][0][16]MAIN[1][1][15]MAIN[1][0][15]MAIN[1][1][14]S.LCLK[0]
MAIN[1][2][30]MAIN[1][5][30]MAIN[1][2][31]MAIN[1][5][31]MAIN[1][0][29]MAIN[1][1][29]MAIN[1][0][30]MAIN[1][1][30]N.LCLK[0]
Source
00000000off
00010001N.HCLK_BUF[0]
00010010N.HCLK_BUF[4]
00010100N.HCLK_BUF[8]
00011000N.RCLK_BUF[0]
00100001N.HCLK_BUF[1]
00100010N.HCLK_BUF[5]
00100100N.HCLK_BUF[9]
00101000N.RCLK_BUF[1]
01000001N.HCLK_BUF[2]
01000010N.HCLK_BUF[6]
01000100N.HCLK_BUF[10]
01001000N.RCLK_BUF[2]
10000001N.HCLK_BUF[3]
10000010N.HCLK_BUF[7]
10000100N.HCLK_BUF[11]
10001000N.RCLK_BUF[3]
virtex7 HCLK switchbox HCLK muxes LCLK[1]
BitsDestination
MAIN[1][5][15]MAIN[1][2][15]MAIN[1][5][14]MAIN[1][2][14]MAIN[1][2][16]MAIN[1][4][16]MAIN[1][5][16]MAIN[1][3][16]S.LCLK[1]
MAIN[1][4][30]MAIN[1][3][30]MAIN[1][4][31]MAIN[1][3][31]MAIN[1][3][29]MAIN[1][5][29]MAIN[1][4][29]MAIN[1][2][29]N.LCLK[1]
Source
00000000off
00010001N.HCLK_BUF[0]
00010010N.HCLK_BUF[4]
00010100N.HCLK_BUF[8]
00011000N.RCLK_BUF[0]
00100001N.HCLK_BUF[1]
00100010N.HCLK_BUF[5]
00100100N.HCLK_BUF[9]
00101000N.RCLK_BUF[1]
01000001N.HCLK_BUF[2]
01000010N.HCLK_BUF[6]
01000100N.HCLK_BUF[10]
01001000N.RCLK_BUF[2]
10000001N.HCLK_BUF[3]
10000010N.HCLK_BUF[7]
10000100N.HCLK_BUF[11]
10001000N.RCLK_BUF[3]
virtex7 HCLK switchbox HCLK muxes LCLK[2]
BitsDestination
MAIN[1][2][18]MAIN[1][5][18]MAIN[1][2][19]MAIN[1][5][19]MAIN[1][1][16]MAIN[1][0][17]MAIN[1][1][17]MAIN[1][0][18]S.LCLK[2]
MAIN[1][3][27]MAIN[1][4][27]MAIN[1][3][26]MAIN[1][4][26]MAIN[1][1][28]MAIN[1][0][28]MAIN[1][1][26]MAIN[1][0][26]N.LCLK[2]
Source
00000000off
00010001N.HCLK_BUF[0]
00010010N.HCLK_BUF[4]
00010100N.HCLK_BUF[8]
00011000N.RCLK_BUF[0]
00100001N.HCLK_BUF[1]
00100010N.HCLK_BUF[5]
00100100N.HCLK_BUF[9]
00101000N.RCLK_BUF[1]
01000001N.HCLK_BUF[2]
01000010N.HCLK_BUF[6]
01000100N.HCLK_BUF[10]
01001000N.RCLK_BUF[2]
10000001N.HCLK_BUF[3]
10000010N.HCLK_BUF[7]
10000100N.HCLK_BUF[11]
10001000N.RCLK_BUF[3]
virtex7 HCLK switchbox HCLK muxes LCLK[3]
BitsDestination
MAIN[1][4][18]MAIN[1][3][18]MAIN[1][4][19]MAIN[1][3][19]MAIN[1][3][17]MAIN[1][5][17]MAIN[1][4][17]MAIN[1][2][17]S.LCLK[3]
MAIN[1][5][27]MAIN[1][2][27]MAIN[1][5][26]MAIN[1][2][26]MAIN[1][2][28]MAIN[1][4][28]MAIN[1][5][28]MAIN[1][3][28]N.LCLK[3]
Source
00000000off
00010001N.HCLK_BUF[0]
00010010N.HCLK_BUF[4]
00010100N.HCLK_BUF[8]
00011000N.RCLK_BUF[0]
00100001N.HCLK_BUF[1]
00100010N.HCLK_BUF[5]
00100100N.HCLK_BUF[9]
00101000N.RCLK_BUF[1]
01000001N.HCLK_BUF[2]
01000010N.HCLK_BUF[6]
01000100N.HCLK_BUF[10]
01001000N.RCLK_BUF[2]
10000001N.HCLK_BUF[3]
10000010N.HCLK_BUF[7]
10000100N.HCLK_BUF[11]
10001000N.RCLK_BUF[3]
virtex7 HCLK switchbox HCLK muxes LCLK[4]
BitsDestination
MAIN[1][3][21]MAIN[1][4][21]MAIN[1][3][20]MAIN[1][4][20]MAIN[1][1][21]MAIN[1][0][21]MAIN[1][1][20]MAIN[1][0][20]S.LCLK[4]
MAIN[1][2][24]MAIN[1][5][24]MAIN[1][2][25]MAIN[1][5][25]MAIN[1][0][24]MAIN[1][1][24]MAIN[1][0][25]MAIN[1][1][25]N.LCLK[4]
Source
00000000off
00010001N.HCLK_BUF[0]
00010010N.HCLK_BUF[4]
00010100N.HCLK_BUF[8]
00011000N.RCLK_BUF[0]
00100001N.HCLK_BUF[1]
00100010N.HCLK_BUF[5]
00100100N.HCLK_BUF[9]
00101000N.RCLK_BUF[1]
01000001N.HCLK_BUF[2]
01000010N.HCLK_BUF[6]
01000100N.HCLK_BUF[10]
01001000N.RCLK_BUF[2]
10000001N.HCLK_BUF[3]
10000010N.HCLK_BUF[7]
10000100N.HCLK_BUF[11]
10001000N.RCLK_BUF[3]
virtex7 HCLK switchbox HCLK muxes LCLK[5]
BitsDestination
MAIN[1][5][21]MAIN[1][2][21]MAIN[1][5][20]MAIN[1][2][20]MAIN[1][2][22]MAIN[1][4][22]MAIN[1][5][22]MAIN[1][3][22]S.LCLK[5]
MAIN[1][4][24]MAIN[1][3][24]MAIN[1][4][25]MAIN[1][3][25]MAIN[1][3][23]MAIN[1][5][23]MAIN[1][4][23]MAIN[1][2][23]N.LCLK[5]
Source
00000000off
00010001N.HCLK_BUF[0]
00010010N.HCLK_BUF[4]
00010100N.HCLK_BUF[8]
00011000N.RCLK_BUF[0]
00100001N.HCLK_BUF[1]
00100010N.HCLK_BUF[5]
00100100N.HCLK_BUF[9]
00101000N.RCLK_BUF[1]
01000001N.HCLK_BUF[2]
01000010N.HCLK_BUF[6]
01000100N.HCLK_BUF[10]
01001000N.RCLK_BUF[2]
10000001N.HCLK_BUF[3]
10000010N.HCLK_BUF[7]
10000100N.HCLK_BUF[11]
10001000N.RCLK_BUF[3]
virtex7 HCLK switchbox HCLK muxes LCLK[6]
BitsDestination
MAIN[0][3][15]MAIN[0][4][15]MAIN[0][3][14]MAIN[0][4][14]MAIN[0][0][16]MAIN[0][1][15]MAIN[0][0][15]MAIN[0][1][14]S.LCLK[6]
MAIN[0][2][30]MAIN[0][5][30]MAIN[0][2][31]MAIN[0][5][31]MAIN[0][0][29]MAIN[0][1][29]MAIN[0][0][30]MAIN[0][1][30]N.LCLK[6]
Source
00000000off
00010001N.HCLK_BUF[0]
00010010N.HCLK_BUF[4]
00010100N.HCLK_BUF[8]
00011000N.RCLK_BUF[0]
00100001N.HCLK_BUF[1]
00100010N.HCLK_BUF[5]
00100100N.HCLK_BUF[9]
00101000N.RCLK_BUF[1]
01000001N.HCLK_BUF[2]
01000010N.HCLK_BUF[6]
01000100N.HCLK_BUF[10]
01001000N.RCLK_BUF[2]
10000001N.HCLK_BUF[3]
10000010N.HCLK_BUF[7]
10000100N.HCLK_BUF[11]
10001000N.RCLK_BUF[3]
virtex7 HCLK switchbox HCLK muxes LCLK[7]
BitsDestination
MAIN[0][5][15]MAIN[0][2][15]MAIN[0][5][14]MAIN[0][2][14]MAIN[0][2][16]MAIN[0][4][16]MAIN[0][5][16]MAIN[0][3][16]S.LCLK[7]
MAIN[0][4][30]MAIN[0][3][30]MAIN[0][4][31]MAIN[0][3][31]MAIN[0][3][29]MAIN[0][5][29]MAIN[0][4][29]MAIN[0][2][29]N.LCLK[7]
Source
00000000off
00010001N.HCLK_BUF[0]
00010010N.HCLK_BUF[4]
00010100N.HCLK_BUF[8]
00011000N.RCLK_BUF[0]
00100001N.HCLK_BUF[1]
00100010N.HCLK_BUF[5]
00100100N.HCLK_BUF[9]
00101000N.RCLK_BUF[1]
01000001N.HCLK_BUF[2]
01000010N.HCLK_BUF[6]
01000100N.HCLK_BUF[10]
01001000N.RCLK_BUF[2]
10000001N.HCLK_BUF[3]
10000010N.HCLK_BUF[7]
10000100N.HCLK_BUF[11]
10001000N.RCLK_BUF[3]
virtex7 HCLK switchbox HCLK muxes LCLK[8]
BitsDestination
MAIN[0][2][18]MAIN[0][5][18]MAIN[0][2][19]MAIN[0][5][19]MAIN[0][1][16]MAIN[0][0][17]MAIN[0][1][17]MAIN[0][0][18]S.LCLK[8]
MAIN[0][3][27]MAIN[0][4][27]MAIN[0][3][26]MAIN[0][4][26]MAIN[0][1][28]MAIN[0][0][28]MAIN[0][1][26]MAIN[0][0][26]N.LCLK[8]
Source
00000000off
00010001N.HCLK_BUF[0]
00010010N.HCLK_BUF[4]
00010100N.HCLK_BUF[8]
00011000N.RCLK_BUF[0]
00100001N.HCLK_BUF[1]
00100010N.HCLK_BUF[5]
00100100N.HCLK_BUF[9]
00101000N.RCLK_BUF[1]
01000001N.HCLK_BUF[2]
01000010N.HCLK_BUF[6]
01000100N.HCLK_BUF[10]
01001000N.RCLK_BUF[2]
10000001N.HCLK_BUF[3]
10000010N.HCLK_BUF[7]
10000100N.HCLK_BUF[11]
10001000N.RCLK_BUF[3]
virtex7 HCLK switchbox HCLK muxes LCLK[9]
BitsDestination
MAIN[0][4][18]MAIN[0][3][18]MAIN[0][4][19]MAIN[0][3][19]MAIN[0][3][17]MAIN[0][5][17]MAIN[0][4][17]MAIN[0][2][17]S.LCLK[9]
MAIN[0][5][27]MAIN[0][2][27]MAIN[0][5][26]MAIN[0][2][26]MAIN[0][2][28]MAIN[0][4][28]MAIN[0][5][28]MAIN[0][3][28]N.LCLK[9]
Source
00000000off
00010001N.HCLK_BUF[0]
00010010N.HCLK_BUF[4]
00010100N.HCLK_BUF[8]
00011000N.RCLK_BUF[0]
00100001N.HCLK_BUF[1]
00100010N.HCLK_BUF[5]
00100100N.HCLK_BUF[9]
00101000N.RCLK_BUF[1]
01000001N.HCLK_BUF[2]
01000010N.HCLK_BUF[6]
01000100N.HCLK_BUF[10]
01001000N.RCLK_BUF[2]
10000001N.HCLK_BUF[3]
10000010N.HCLK_BUF[7]
10000100N.HCLK_BUF[11]
10001000N.RCLK_BUF[3]
virtex7 HCLK switchbox HCLK muxes LCLK[10]
BitsDestination
MAIN[0][3][21]MAIN[0][4][21]MAIN[0][3][20]MAIN[0][4][20]MAIN[0][1][21]MAIN[0][0][21]MAIN[0][1][20]MAIN[0][0][20]S.LCLK[10]
MAIN[0][2][24]MAIN[0][5][24]MAIN[0][2][25]MAIN[0][5][25]MAIN[0][0][24]MAIN[0][1][24]MAIN[0][0][25]MAIN[0][1][25]N.LCLK[10]
Source
00000000off
00010001N.HCLK_BUF[0]
00010010N.HCLK_BUF[4]
00010100N.HCLK_BUF[8]
00011000N.RCLK_BUF[0]
00100001N.HCLK_BUF[1]
00100010N.HCLK_BUF[5]
00100100N.HCLK_BUF[9]
00101000N.RCLK_BUF[1]
01000001N.HCLK_BUF[2]
01000010N.HCLK_BUF[6]
01000100N.HCLK_BUF[10]
01001000N.RCLK_BUF[2]
10000001N.HCLK_BUF[3]
10000010N.HCLK_BUF[7]
10000100N.HCLK_BUF[11]
10001000N.RCLK_BUF[3]
virtex7 HCLK switchbox HCLK muxes LCLK[11]
BitsDestination
MAIN[0][5][21]MAIN[0][2][21]MAIN[0][5][20]MAIN[0][2][20]MAIN[0][2][22]MAIN[0][4][22]MAIN[0][5][22]MAIN[0][3][22]S.LCLK[11]
MAIN[0][4][24]MAIN[0][3][24]MAIN[0][4][25]MAIN[0][3][25]MAIN[0][3][23]MAIN[0][5][23]MAIN[0][4][23]MAIN[0][2][23]N.LCLK[11]
Source
00000000off
00010001N.HCLK_BUF[0]
00010010N.HCLK_BUF[4]
00010100N.HCLK_BUF[8]
00011000N.RCLK_BUF[0]
00100001N.HCLK_BUF[1]
00100010N.HCLK_BUF[5]
00100100N.HCLK_BUF[9]
00101000N.RCLK_BUF[1]
01000001N.HCLK_BUF[2]
01000010N.HCLK_BUF[6]
01000100N.HCLK_BUF[10]
01001000N.RCLK_BUF[2]
10000001N.HCLK_BUF[3]
10000010N.HCLK_BUF[7]
10000100N.HCLK_BUF[11]
10001000N.RCLK_BUF[3]

Bels HCLK_DRP

virtex7 HCLK bel HCLK_DRP pins
PinDirectionHCLK_DRP[0]HCLK_DRP[1]
virtex7 HCLK bel HCLK_DRP attribute bits
AttributeHCLK_DRP[0]HCLK_DRP[1]
DRP_MASK_SMAIN[0][24][13]MAIN[1][24][13]
DRP_MASK_NMAIN[0][25][13]MAIN[1][25][13]

Bitstream

virtex7 HCLK rect MAIN[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B31 HCLK: buffer N.RCLK_BUF[2] ← N.RCLK_ROW[2] HCLK: buffer N.RCLK_BUF[3] ← N.RCLK_ROW[3] HCLK: mux N.LCLK[6] bit 5 HCLK: mux N.LCLK[7] bit 4 HCLK: mux N.LCLK[7] bit 5 HCLK: mux N.LCLK[6] bit 4 - - - - - - - - - - - - - - - - - - - - - -
B30 HCLK: mux N.LCLK[6] bit 1 HCLK: mux N.LCLK[6] bit 0 HCLK: mux N.LCLK[6] bit 7 HCLK: mux N.LCLK[7] bit 6 HCLK: mux N.LCLK[7] bit 7 HCLK: mux N.LCLK[6] bit 6 - - - - - - - - - - - - - - - - - - - - - -
B29 HCLK: mux N.LCLK[6] bit 3 HCLK: mux N.LCLK[6] bit 2 HCLK: mux N.LCLK[7] bit 0 HCLK: mux N.LCLK[7] bit 3 HCLK: mux N.LCLK[7] bit 1 HCLK: mux N.LCLK[7] bit 2 - - - - - - - - - - - - - - - - - - - - - -
B28 HCLK: mux N.LCLK[8] bit 2 HCLK: mux N.LCLK[8] bit 3 HCLK: mux N.LCLK[9] bit 3 HCLK: mux N.LCLK[9] bit 0 HCLK: mux N.LCLK[9] bit 2 HCLK: mux N.LCLK[9] bit 1 - - - - - - - - - - - - - - - - - - - - - -
B27 - - HCLK: mux N.LCLK[9] bit 6 HCLK: mux N.LCLK[8] bit 7 HCLK: mux N.LCLK[8] bit 6 HCLK: mux N.LCLK[9] bit 7 - - - - - - - - - - - - - - - - - - - - - -
B26 HCLK: mux N.LCLK[8] bit 0 HCLK: mux N.LCLK[8] bit 1 HCLK: mux N.LCLK[9] bit 4 HCLK: mux N.LCLK[8] bit 5 HCLK: mux N.LCLK[8] bit 4 HCLK: mux N.LCLK[9] bit 5 - - - - - - - - - - - - - - - - - - - - - -
B25 HCLK: mux N.LCLK[10] bit 1 HCLK: mux N.LCLK[10] bit 0 HCLK: mux N.LCLK[10] bit 5 HCLK: mux N.LCLK[11] bit 4 HCLK: mux N.LCLK[11] bit 5 HCLK: mux N.LCLK[10] bit 4 - - - - - - - - - - - - - - - - - - - - - -
B24 HCLK: mux N.LCLK[10] bit 3 HCLK: mux N.LCLK[10] bit 2 HCLK: mux N.LCLK[10] bit 7 HCLK: mux N.LCLK[11] bit 6 HCLK: mux N.LCLK[11] bit 7 HCLK: mux N.LCLK[10] bit 6 - - - - - - - - - - - - - - - - - - - - - -
B23 HCLK: buffer N.RCLK_BUF[0] ← N.RCLK_ROW[0] HCLK: buffer N.RCLK_BUF[1] ← N.RCLK_ROW[1] HCLK: mux N.LCLK[11] bit 0 HCLK: mux N.LCLK[11] bit 3 HCLK: mux N.LCLK[11] bit 1 HCLK: mux N.LCLK[11] bit 2 - - - - - - - - - - - - - - - - - - - - - -
B22 HCLK: buffer N.HCLK_BUF[10] ← N.HCLK_ROW[10] HCLK: buffer N.HCLK_BUF[11] ← N.HCLK_ROW[11] HCLK: mux S.LCLK[11] bit 3 HCLK: mux S.LCLK[11] bit 0 HCLK: mux S.LCLK[11] bit 2 HCLK: mux S.LCLK[11] bit 1 - - - - - - - - - - - - - - - - - - - - - -
B21 HCLK: mux S.LCLK[10] bit 2 HCLK: mux S.LCLK[10] bit 3 HCLK: mux S.LCLK[11] bit 6 HCLK: mux S.LCLK[10] bit 7 HCLK: mux S.LCLK[10] bit 6 HCLK: mux S.LCLK[11] bit 7 - - - - - - - - - - - - - - - - - - - - - -
B20 HCLK: mux S.LCLK[10] bit 0 HCLK: mux S.LCLK[10] bit 1 HCLK: mux S.LCLK[11] bit 4 HCLK: mux S.LCLK[10] bit 5 HCLK: mux S.LCLK[10] bit 4 HCLK: mux S.LCLK[11] bit 5 - - - - - - - - - - - - - - - - - - - - - -
B19 - HCLK: buffer N.HCLK_BUF[9] ← N.HCLK_ROW[9] HCLK: mux S.LCLK[8] bit 5 HCLK: mux S.LCLK[9] bit 4 HCLK: mux S.LCLK[9] bit 5 HCLK: mux S.LCLK[8] bit 4 - - - - - - - - - - - - - - - - - - - - - -
B18 HCLK: mux S.LCLK[8] bit 0 - HCLK: mux S.LCLK[8] bit 7 HCLK: mux S.LCLK[9] bit 6 HCLK: mux S.LCLK[9] bit 7 HCLK: mux S.LCLK[8] bit 6 - - - - - - - - - - - - - - - - - - - - - -
B17 HCLK: mux S.LCLK[8] bit 2 HCLK: mux S.LCLK[8] bit 1 HCLK: mux S.LCLK[9] bit 0 HCLK: mux S.LCLK[9] bit 3 HCLK: mux S.LCLK[9] bit 1 HCLK: mux S.LCLK[9] bit 2 - - - - - - - - - - - - - - - - - - - - - -
B16 HCLK: mux S.LCLK[6] bit 3 HCLK: mux S.LCLK[8] bit 3 HCLK: mux S.LCLK[7] bit 3 HCLK: mux S.LCLK[7] bit 0 HCLK: mux S.LCLK[7] bit 2 HCLK: mux S.LCLK[7] bit 1 - - - - - - - - - - - - - - - - - - - - - -
B15 HCLK: mux S.LCLK[6] bit 1 HCLK: mux S.LCLK[6] bit 2 HCLK: mux S.LCLK[7] bit 6 HCLK: mux S.LCLK[6] bit 7 HCLK: mux S.LCLK[6] bit 6 HCLK: mux S.LCLK[7] bit 7 - - - - - - - - - - - - - - - - - - - - - -
B14 HCLK: buffer N.HCLK_BUF[8] ← N.HCLK_ROW[8] HCLK: mux S.LCLK[6] bit 0 HCLK: mux S.LCLK[7] bit 4 HCLK: mux S.LCLK[6] bit 5 HCLK: mux S.LCLK[6] bit 4 HCLK: mux S.LCLK[7] bit 5 - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - HCLK_DRP[0]: DRP_MASK_S HCLK_DRP[0]: DRP_MASK_N - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex7 HCLK rect MAIN[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B31 HCLK: buffer N.HCLK_BUF[6] ← N.HCLK_ROW[6] HCLK: buffer N.HCLK_BUF[7] ← N.HCLK_ROW[7] HCLK: mux N.LCLK[0] bit 5 HCLK: mux N.LCLK[1] bit 4 HCLK: mux N.LCLK[1] bit 5 HCLK: mux N.LCLK[0] bit 4 - - - - - - - - - - - - - - - - - - - - - -
B30 HCLK: mux N.LCLK[0] bit 1 HCLK: mux N.LCLK[0] bit 0 HCLK: mux N.LCLK[0] bit 7 HCLK: mux N.LCLK[1] bit 6 HCLK: mux N.LCLK[1] bit 7 HCLK: mux N.LCLK[0] bit 6 - - - - - - - - - - - - - - - - - - - - - -
B29 HCLK: mux N.LCLK[0] bit 3 HCLK: mux N.LCLK[0] bit 2 HCLK: mux N.LCLK[1] bit 0 HCLK: mux N.LCLK[1] bit 3 HCLK: mux N.LCLK[1] bit 1 HCLK: mux N.LCLK[1] bit 2 - - - - - - - - - - - - - - - - - - - - - -
B28 HCLK: mux N.LCLK[2] bit 2 HCLK: mux N.LCLK[2] bit 3 HCLK: mux N.LCLK[3] bit 3 HCLK: mux N.LCLK[3] bit 0 HCLK: mux N.LCLK[3] bit 2 HCLK: mux N.LCLK[3] bit 1 - - - - - - - - - - - - - - - - - - - - - -
B27 - - HCLK: mux N.LCLK[3] bit 6 HCLK: mux N.LCLK[2] bit 7 HCLK: mux N.LCLK[2] bit 6 HCLK: mux N.LCLK[3] bit 7 - - - - - - - - - - - - - - - - - - - - - -
B26 HCLK: mux N.LCLK[2] bit 0 HCLK: mux N.LCLK[2] bit 1 HCLK: mux N.LCLK[3] bit 4 HCLK: mux N.LCLK[2] bit 5 HCLK: mux N.LCLK[2] bit 4 HCLK: mux N.LCLK[3] bit 5 - - - - - - - - - - - - - - - - - - - - - -
B25 HCLK: mux N.LCLK[4] bit 1 HCLK: mux N.LCLK[4] bit 0 HCLK: mux N.LCLK[4] bit 5 HCLK: mux N.LCLK[5] bit 4 HCLK: mux N.LCLK[5] bit 5 HCLK: mux N.LCLK[4] bit 4 - - - - - - - - - - - - - - - - - - - - - -
B24 HCLK: mux N.LCLK[4] bit 3 HCLK: mux N.LCLK[4] bit 2 HCLK: mux N.LCLK[4] bit 7 HCLK: mux N.LCLK[5] bit 6 HCLK: mux N.LCLK[5] bit 7 HCLK: mux N.LCLK[4] bit 6 - - - - - - - - - - - - - - - - - - - - - -
B23 HCLK: buffer N.HCLK_BUF[4] ← N.HCLK_ROW[4] HCLK: buffer N.HCLK_BUF[5] ← N.HCLK_ROW[5] HCLK: mux N.LCLK[5] bit 0 HCLK: mux N.LCLK[5] bit 3 HCLK: mux N.LCLK[5] bit 1 HCLK: mux N.LCLK[5] bit 2 - - - - - - - - - - - - - - - - - - - - - -
B22 HCLK: buffer N.HCLK_BUF[2] ← N.HCLK_ROW[2] HCLK: buffer N.HCLK_BUF[3] ← N.HCLK_ROW[3] HCLK: mux S.LCLK[5] bit 3 HCLK: mux S.LCLK[5] bit 0 HCLK: mux S.LCLK[5] bit 2 HCLK: mux S.LCLK[5] bit 1 - - - - - - - - - - - - - - - - - - - - - -
B21 HCLK: mux S.LCLK[4] bit 2 HCLK: mux S.LCLK[4] bit 3 HCLK: mux S.LCLK[5] bit 6 HCLK: mux S.LCLK[4] bit 7 HCLK: mux S.LCLK[4] bit 6 HCLK: mux S.LCLK[5] bit 7 - - - - - - - - - - - - - - - - - - - - - -
B20 HCLK: mux S.LCLK[4] bit 0 HCLK: mux S.LCLK[4] bit 1 HCLK: mux S.LCLK[5] bit 4 HCLK: mux S.LCLK[4] bit 5 HCLK: mux S.LCLK[4] bit 4 HCLK: mux S.LCLK[5] bit 5 - - - - - - - - - - - - - - - - - - - - - -
B19 - HCLK: buffer N.HCLK_BUF[1] ← N.HCLK_ROW[1] HCLK: mux S.LCLK[2] bit 5 HCLK: mux S.LCLK[3] bit 4 HCLK: mux S.LCLK[3] bit 5 HCLK: mux S.LCLK[2] bit 4 - - - - - - - - - - - - - - - - - - - - - -
B18 HCLK: mux S.LCLK[2] bit 0 - HCLK: mux S.LCLK[2] bit 7 HCLK: mux S.LCLK[3] bit 6 HCLK: mux S.LCLK[3] bit 7 HCLK: mux S.LCLK[2] bit 6 - - - - - - - - - - - - - - - - - - - - - -
B17 HCLK: mux S.LCLK[2] bit 2 HCLK: mux S.LCLK[2] bit 1 HCLK: mux S.LCLK[3] bit 0 HCLK: mux S.LCLK[3] bit 3 HCLK: mux S.LCLK[3] bit 1 HCLK: mux S.LCLK[3] bit 2 - - - - - - - - - - - - - - - - - - - - - -
B16 HCLK: mux S.LCLK[0] bit 3 HCLK: mux S.LCLK[2] bit 3 HCLK: mux S.LCLK[1] bit 3 HCLK: mux S.LCLK[1] bit 0 HCLK: mux S.LCLK[1] bit 2 HCLK: mux S.LCLK[1] bit 1 - - - - - - - - - - - - - - - - - - - - - -
B15 HCLK: mux S.LCLK[0] bit 1 HCLK: mux S.LCLK[0] bit 2 HCLK: mux S.LCLK[1] bit 6 HCLK: mux S.LCLK[0] bit 7 HCLK: mux S.LCLK[0] bit 6 HCLK: mux S.LCLK[1] bit 7 - - - - - - - - - - - - - - - - - - - - - -
B14 HCLK: buffer N.HCLK_BUF[0] ← N.HCLK_ROW[0] HCLK: mux S.LCLK[0] bit 0 HCLK: mux S.LCLK[1] bit 4 HCLK: mux S.LCLK[0] bit 5 HCLK: mux S.LCLK[0] bit 4 HCLK: mux S.LCLK[1] bit 5 - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - HCLK_DRP[1]: DRP_MASK_S HCLK_DRP[1]: DRP_MASK_N - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - -