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Configuration registers

TODO: document

Tile GLOBAL

Cells: 0

Bels GLOBAL

virtex7 GLOBAL bel GLOBAL pins
PinDirectionGLOBAL
virtex7 GLOBAL bel GLOBAL attribute bits
AttributeGLOBAL
GWE_CYCLE[enum: STARTUP_CYCLE]
GTS_CYCLE[enum: STARTUP_CYCLE]
LOCK_CYCLE[enum: STARTUP_CYCLE]
MATCH_CYCLE[enum: STARTUP_CYCLE]
DONE_CYCLE[enum: STARTUP_CYCLE]
STARTUP_CLOCK[enum: STARTUP_CLOCK]
CONFIG_RATE_V7[enum: CONFIG_RATE_V7]
CAPTURE_ONESHOTCOR0[0][23]
DRIVE_DONECOR0[0][24]
DONE_PIPECOR0[0][25]
POWERDOWN_STATUSCOR0[0][27]
EXTMASTERCCLK_DIV[enum: EXTMASTERCCLK_DIV]
EXTMASTERCCLK_ENCOR0[0][26]
BPI_PAGE_SIZE[enum: BPI_PAGE_SIZE]
BPI_1ST_READ_CYCLE[enum: BPI_1ST_READ_CYCLE]
POST_CRC_ENCOR1[0][8]
POST_CRC_NO_PINCOR1[0][9]
POST_CRC_RECONFIGCOR1[0][6]
POST_CRC_KEEP!COR1[0][15]
POST_CRC_CORRECTCOR1[0][16]
POST_CRC_SEL bit 0COR1[0][7]
PERSIST_DEASSERT_AT_DESYNCHCOR1[0][17]
SYSMON_PARTIAL_RECONFIGCOR1[0][31]
POST_CRC_CLK[enum: POST_CRC_CLK]
POST_CRC_FREQ[enum: POST_CRC_FREQ]
CFG_IO_ACCESS_TDOCOR1[0][21]
TRIM_BITSTREAMCOR1[0][12]
TRIM_REG bit 0COR1[0][10]
TRIM_REG bit 1COR1[0][11]
GTS_USR_BCTL0[0][0]
EN_VTESTCTL1[0][1]
VGG_TESTCTL1[0][0]
PERSISTCTL0[0][3]
SECURITY[enum: SECURITY]
ENCRYPTCTL0[0][6]
GLUTMASK!CTL0[0][8]
ICAP_SELECT[enum: ICAP_SELECT]
CONFIG_FALLBACK!CTL0[0][10]
ENCRYPT_KEY_SELECT[enum: ENCRYPT_KEY_SELECT]
OVERTEMP_POWERDOWNCTL0[0][12]
SELECTMAP_ABORT!CTL0[0][9]
VGG_SEL bit 0CTL1[0][13]
VGG_SEL bit 1CTL1[0][14]
VGG_SEL bit 2CTL1[0][15]
VGG_SEL bit 3CTL1[0][16]
VGG_SEL bit 4CTL1[0][17]
INIT_SIGNALS_ERROR!CTL0[0][13]
SEC_ALLCTL0[0][29]
SEC_ERRORCTL0[0][11]
SEC_STATUSCTL0[0][14]
FARSRC[enum: FARSRC]
ICAP_ENCRYPTIONCTL1[0][20]
DIS_VGG_REGCTL1[0][2]
ENABLE_VGG_CLAMPCTL1[0][3]
VGG_NEG_GAIN_SEL bit 0CTL1[0][6]
VGG_NEG_GAIN_SEL bit 1CTL1[0][7]
VGG_NEG_GAIN_SEL bit 2CTL1[0][8]
VGG_NEG_GAIN_SEL bit 3CTL1[0][9]
VGG_NEG_GAIN_SEL bit 4CTL1[0][10]
VGG_POS_GAIN_SEL bit 0CTL1[0][4]
TIMER bit 0TIMER[0][0]
TIMER bit 1TIMER[0][1]
TIMER bit 2TIMER[0][2]
TIMER bit 3TIMER[0][3]
TIMER bit 4TIMER[0][4]
TIMER bit 5TIMER[0][5]
TIMER bit 6TIMER[0][6]
TIMER bit 7TIMER[0][7]
TIMER bit 8TIMER[0][8]
TIMER bit 9TIMER[0][9]
TIMER bit 10TIMER[0][10]
TIMER bit 11TIMER[0][11]
TIMER bit 12TIMER[0][12]
TIMER bit 13TIMER[0][13]
TIMER bit 14TIMER[0][14]
TIMER bit 15TIMER[0][15]
TIMER bit 16TIMER[0][16]
TIMER bit 17TIMER[0][17]
TIMER bit 18TIMER[0][18]
TIMER bit 19TIMER[0][19]
TIMER bit 20TIMER[0][20]
TIMER bit 21TIMER[0][21]
TIMER bit 22TIMER[0][22]
TIMER bit 23TIMER[0][23]
TIMER_CFGTIMER[0][30]
TIMER_USRTIMER[0][31]
V7_NEXT_CONFIG_ADDR bit 0WBSTAR[0][0]
V7_NEXT_CONFIG_ADDR bit 1WBSTAR[0][1]
V7_NEXT_CONFIG_ADDR bit 2WBSTAR[0][2]
V7_NEXT_CONFIG_ADDR bit 3WBSTAR[0][3]
V7_NEXT_CONFIG_ADDR bit 4WBSTAR[0][4]
V7_NEXT_CONFIG_ADDR bit 5WBSTAR[0][5]
V7_NEXT_CONFIG_ADDR bit 6WBSTAR[0][6]
V7_NEXT_CONFIG_ADDR bit 7WBSTAR[0][7]
V7_NEXT_CONFIG_ADDR bit 8WBSTAR[0][8]
V7_NEXT_CONFIG_ADDR bit 9WBSTAR[0][9]
V7_NEXT_CONFIG_ADDR bit 10WBSTAR[0][10]
V7_NEXT_CONFIG_ADDR bit 11WBSTAR[0][11]
V7_NEXT_CONFIG_ADDR bit 12WBSTAR[0][12]
V7_NEXT_CONFIG_ADDR bit 13WBSTAR[0][13]
V7_NEXT_CONFIG_ADDR bit 14WBSTAR[0][14]
V7_NEXT_CONFIG_ADDR bit 15WBSTAR[0][15]
V7_NEXT_CONFIG_ADDR bit 16WBSTAR[0][16]
V7_NEXT_CONFIG_ADDR bit 17WBSTAR[0][17]
V7_NEXT_CONFIG_ADDR bit 18WBSTAR[0][18]
V7_NEXT_CONFIG_ADDR bit 19WBSTAR[0][19]
V7_NEXT_CONFIG_ADDR bit 20WBSTAR[0][20]
V7_NEXT_CONFIG_ADDR bit 21WBSTAR[0][21]
V7_NEXT_CONFIG_ADDR bit 22WBSTAR[0][22]
V7_NEXT_CONFIG_ADDR bit 23WBSTAR[0][23]
V7_NEXT_CONFIG_ADDR bit 24WBSTAR[0][24]
V7_NEXT_CONFIG_ADDR bit 25WBSTAR[0][25]
V7_NEXT_CONFIG_ADDR bit 26WBSTAR[0][26]
V7_NEXT_CONFIG_ADDR bit 27WBSTAR[0][27]
V7_NEXT_CONFIG_ADDR bit 28WBSTAR[0][28]
REVISION_SELECT_TRISTATEWBSTAR[0][29]
REVISION_SELECT bit 0WBSTAR[0][30]
REVISION_SELECT bit 1WBSTAR[0][31]
SPI_BUSWIDTH[enum: SPI_BUSWIDTH]
SPI_OPCODE bit 0BSPI[0][0]
SPI_OPCODE bit 1BSPI[0][1]
SPI_OPCODE bit 2BSPI[0][2]
SPI_OPCODE bit 3BSPI[0][3]
SPI_OPCODE bit 4BSPI[0][4]
SPI_OPCODE bit 5BSPI[0][5]
SPI_OPCODE bit 6BSPI[0][6]
SPI_OPCODE bit 7BSPI[0][7]
BPI_SYNC_MODE[enum: BPI_SYNC_MODE]
TEST_REF_SEL bit 0TESTMODE[0][28]
TEST_REF_SEL bit 1TESTMODE[0][29]
TEST_REF_SEL bit 2TESTMODE[0][30]
TEST_VGG_SEL bit 0TESTMODE[0][8]
TEST_VGG_SEL bit 1TESTMODE[0][9]
TEST_VGG_SEL bit 2TESTMODE[0][10]
TEST_VGG_SEL bit 3TESTMODE[0][11]
TEST_NEG_SLOPE_VGG bit 0TESTMODE[0][12]
TEST_VGG_ENABLE bit 0TESTMODE[0][21]
MPD_SEL bit 0TRIM0[0][0]
MPD_SEL bit 1TRIM0[0][1]
MPD_SEL bit 2TRIM0[0][2]
TRIM_SPARE bit 0TRIM0[0][5]
TRIM_SPARE bit 1TRIM0[0][6]
MPD_DIS_OVERRIDE bit 0TRIM0[0][4]
MPD_OVERRIDE bit 0TRIM0[0][3]
VBG_FLAT_SEL bit 0TRIM1[0][14]
VBG_FLAT_SEL bit 1TRIM1[0][15]
VBG_FLAT_SEL bit 2TRIM1[0][16]
VBG_FLAT_SEL bit 3TRIM1[0][17]
VBG_FLAT_SEL bit 4TRIM1[0][18]
VBG_FLAT_SEL bit 5TRIM1[0][19]
VGGSEL bit 0TRIM1[0][20]
VGGSEL bit 1TRIM1[0][21]
VGGSEL bit 2TRIM1[0][22]
VGGSEL bit 3TRIM1[0][23]
VGGSEL bit 4TRIM1[0][24]
VGGSEL bit 5TRIM1[0][25]
VGGSEL2 bit 0TRIM1[0][26]
VGGSEL2 bit 1TRIM1[0][27]
VGGSEL2 bit 2TRIM1[0][28]
VGGSEL2 bit 3TRIM1[0][29]
VGGSEL2 bit 4TRIM1[0][30]
VGGSEL2 bit 5TRIM1[0][31]
VGG_TRIM_BOT bit 0TRIM2[0][12]
VGG_TRIM_BOT bit 1TRIM2[0][13]
VGG_TRIM_BOT bit 2TRIM2[0][14]
VGG_TRIM_BOT bit 3TRIM2[0][15]
VGG_TRIM_BOT bit 4TRIM2[0][16]
VGG_TRIM_BOT bit 5TRIM2[0][17]
VGG_TRIM_BOT bit 6TRIM2[0][18]
VGG_TRIM_BOT bit 7TRIM2[0][19]
VGG_TRIM_BOT bit 8TRIM2[0][20]
VGG_TRIM_BOT bit 9TRIM2[0][21]
VGG_TRIM_BOT bit 10TRIM2[0][22]
VGG_TRIM_BOT bit 11TRIM2[0][23]
VGG_TRIM_TOP bit 0TRIM2[0][0]
VGG_TRIM_TOP bit 1TRIM2[0][1]
VGG_TRIM_TOP bit 2TRIM2[0][2]
VGG_TRIM_TOP bit 3TRIM2[0][3]
VGG_TRIM_TOP bit 4TRIM2[0][4]
VGG_TRIM_TOP bit 5TRIM2[0][5]
VGG_TRIM_TOP bit 6TRIM2[0][6]
VGG_TRIM_TOP bit 7TRIM2[0][7]
VGG_TRIM_TOP bit 8TRIM2[0][8]
VGG_TRIM_TOP bit 9TRIM2[0][9]
VGG_TRIM_TOP bit 10TRIM2[0][10]
VGG_TRIM_TOP bit 11TRIM2[0][11]
virtex7 GLOBAL enum STARTUP_CYCLE
GLOBAL.GWE_CYCLECOR0[0][2]COR0[0][1]COR0[0][0]
GLOBAL.GTS_CYCLECOR0[0][5]COR0[0][4]COR0[0][3]
_1000
_2001
_3010
_4011
_5100
_6101
DONE110
KEEP111
virtex7 GLOBAL enum STARTUP_CYCLE
GLOBAL.LOCK_CYCLECOR0[0][8]COR0[0][7]COR0[0][6]
GLOBAL.MATCH_CYCLECOR0[0][11]COR0[0][10]COR0[0][9]
_0000
_1001
_2010
_3011
_4100
_5101
_6110
NOWAIT111
virtex7 GLOBAL enum STARTUP_CYCLE
GLOBAL.DONE_CYCLECOR0[0][14]COR0[0][13]COR0[0][12]
_1000
_2001
_3010
_4011
_5100
_6101
KEEP111
virtex7 GLOBAL enum STARTUP_CLOCK
GLOBAL.STARTUP_CLOCKCOR0[0][16]COR0[0][15]
CCLK00
USERCLK01
JTAGCLK10
virtex7 GLOBAL enum CONFIG_RATE_V7
GLOBAL.CONFIG_RATE_V7COR0[0][22]COR0[0][21]COR0[0][20]COR0[0][19]COR0[0][18]COR0[0][17]
_3000000
_6010000
_9000001
_12100000
_16010001
_22000100
_26010010
_33100001
_40001011
_50010101
_66011000
virtex7 GLOBAL enum EXTMASTERCCLK_DIV
GLOBAL.EXTMASTERCCLK_DIVCOR0[0][22]COR0[0][21]
_800
_401
_210
_111
virtex7 GLOBAL enum BPI_PAGE_SIZE
GLOBAL.BPI_PAGE_SIZECOR1[0][1]COR1[0][0]
_100
_401
_810
virtex7 GLOBAL enum BPI_1ST_READ_CYCLE
GLOBAL.BPI_1ST_READ_CYCLECOR1[0][3]COR1[0][2]
_100
_201
_310
_411
virtex7 GLOBAL enum POST_CRC_CLK
GLOBAL.POST_CRC_CLKCOR1[0][26]
CFG_CLK0
INTERNAL1
virtex7 GLOBAL enum POST_CRC_FREQ
GLOBAL.POST_CRC_FREQCOR1[0][29]COR1[0][28]COR1[0][27]
_50000
_25001
_13010
_6011
_3100
_2101
_1110
virtex7 GLOBAL enum SECURITY
GLOBAL.SECURITYCTL0[0][5]CTL0[0][4]
NONE00
LEVEL101
LEVEL210
virtex7 GLOBAL enum ICAP_SELECT
GLOBAL.ICAP_SELECTCTL0[0][30]
BOTTOM1
TOP0
virtex7 GLOBAL enum ENCRYPT_KEY_SELECT
GLOBAL.ENCRYPT_KEY_SELECTCTL0[0][31]
BBRAM0
EFUSE1
virtex7 GLOBAL enum FARSRC
GLOBAL.FARSRCCTL0[0][7]
FAR1
EFAR0
virtex7 GLOBAL enum SPI_BUSWIDTH
GLOBAL.SPI_BUSWIDTHBSPI[0][9]BSPI[0][8]
_100
_201
_410
virtex7 GLOBAL enum BPI_SYNC_MODE
GLOBAL.BPI_SYNC_MODEBSPI[0][27]BSPI[0][26]BSPI[0][25]BSPI[0][24]BSPI[0][23]BSPI[0][22]BSPI[0][21]BSPI[0][20]BSPI[0][19]BSPI[0][18]BSPI[0][17]BSPI[0][16]BSPI[0][15]BSPI[0][14]BSPI[0][13]BSPI[0][12]
NONE0000000000000000
TYPE11101100111001111
TYPE21010100111001111

Bitstream

virtex7 GLOBAL rect COR0
FrameBit
B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - - - - GLOBAL: POWERDOWN_STATUS GLOBAL: EXTMASTERCCLK_EN GLOBAL: DONE_PIPE GLOBAL: DRIVE_DONE GLOBAL: CAPTURE_ONESHOT GLOBAL: CONFIG_RATE_V7 bit 5 GLOBAL: EXTMASTERCCLK_DIV bit 1 GLOBAL: CONFIG_RATE_V7 bit 4 GLOBAL: EXTMASTERCCLK_DIV bit 0 GLOBAL: CONFIG_RATE_V7 bit 3 GLOBAL: CONFIG_RATE_V7 bit 2 GLOBAL: CONFIG_RATE_V7 bit 1 GLOBAL: CONFIG_RATE_V7 bit 0 GLOBAL: STARTUP_CLOCK bit 1 GLOBAL: STARTUP_CLOCK bit 0 GLOBAL: DONE_CYCLE bit 2 GLOBAL: DONE_CYCLE bit 1 GLOBAL: DONE_CYCLE bit 0 GLOBAL: MATCH_CYCLE bit 2 GLOBAL: MATCH_CYCLE bit 1 GLOBAL: MATCH_CYCLE bit 0 GLOBAL: LOCK_CYCLE bit 2 GLOBAL: LOCK_CYCLE bit 1 GLOBAL: LOCK_CYCLE bit 0 GLOBAL: GTS_CYCLE bit 2 GLOBAL: GTS_CYCLE bit 1 GLOBAL: GTS_CYCLE bit 0 GLOBAL: GWE_CYCLE bit 2 GLOBAL: GWE_CYCLE bit 1 GLOBAL: GWE_CYCLE bit 0
virtex7 GLOBAL rect COR1
FrameBit
B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 GLOBAL: SYSMON_PARTIAL_RECONFIG - GLOBAL: POST_CRC_FREQ bit 2 GLOBAL: POST_CRC_FREQ bit 1 GLOBAL: POST_CRC_FREQ bit 0 GLOBAL: POST_CRC_CLK bit 0 - - - - GLOBAL: CFG_IO_ACCESS_TDO - - - GLOBAL: PERSIST_DEASSERT_AT_DESYNCH GLOBAL: POST_CRC_CORRECT GLOBAL: ! POST_CRC_KEEP - - GLOBAL: TRIM_BITSTREAM GLOBAL: TRIM_REG bit 1 GLOBAL: TRIM_REG bit 0 GLOBAL: POST_CRC_NO_PIN GLOBAL: POST_CRC_EN GLOBAL: POST_CRC_SEL bit 0 GLOBAL: POST_CRC_RECONFIG - - GLOBAL: BPI_1ST_READ_CYCLE bit 1 GLOBAL: BPI_1ST_READ_CYCLE bit 0 GLOBAL: BPI_PAGE_SIZE bit 1 GLOBAL: BPI_PAGE_SIZE bit 0
virtex7 GLOBAL rect CTL0
FrameBit
B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 GLOBAL: ENCRYPT_KEY_SELECT bit 0 GLOBAL: ICAP_SELECT bit 0 GLOBAL: SEC_ALL - - - - - - - - - - - - - - GLOBAL: SEC_STATUS GLOBAL: ! INIT_SIGNALS_ERROR GLOBAL: OVERTEMP_POWERDOWN GLOBAL: SEC_ERROR GLOBAL: ! CONFIG_FALLBACK GLOBAL: ! SELECTMAP_ABORT GLOBAL: ! GLUTMASK GLOBAL: FARSRC bit 0 GLOBAL: ENCRYPT GLOBAL: SECURITY bit 1 GLOBAL: SECURITY bit 0 GLOBAL: PERSIST - - GLOBAL: GTS_USR_B
virtex7 GLOBAL rect CTL1
FrameBit
B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - - - - - - - - - - - GLOBAL: ICAP_ENCRYPTION - - GLOBAL: VGG_SEL bit 4 GLOBAL: VGG_SEL bit 3 GLOBAL: VGG_SEL bit 2 GLOBAL: VGG_SEL bit 1 GLOBAL: VGG_SEL bit 0 - - GLOBAL: VGG_NEG_GAIN_SEL bit 4 GLOBAL: VGG_NEG_GAIN_SEL bit 3 GLOBAL: VGG_NEG_GAIN_SEL bit 2 GLOBAL: VGG_NEG_GAIN_SEL bit 1 GLOBAL: VGG_NEG_GAIN_SEL bit 0 - GLOBAL: VGG_POS_GAIN_SEL bit 0 GLOBAL: ENABLE_VGG_CLAMP GLOBAL: DIS_VGG_REG GLOBAL: EN_VTEST GLOBAL: VGG_TEST
virtex7 GLOBAL rect TIMER
FrameBit
B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 GLOBAL: TIMER_USR GLOBAL: TIMER_CFG - - - - - - GLOBAL: TIMER bit 23 GLOBAL: TIMER bit 22 GLOBAL: TIMER bit 21 GLOBAL: TIMER bit 20 GLOBAL: TIMER bit 19 GLOBAL: TIMER bit 18 GLOBAL: TIMER bit 17 GLOBAL: TIMER bit 16 GLOBAL: TIMER bit 15 GLOBAL: TIMER bit 14 GLOBAL: TIMER bit 13 GLOBAL: TIMER bit 12 GLOBAL: TIMER bit 11 GLOBAL: TIMER bit 10 GLOBAL: TIMER bit 9 GLOBAL: TIMER bit 8 GLOBAL: TIMER bit 7 GLOBAL: TIMER bit 6 GLOBAL: TIMER bit 5 GLOBAL: TIMER bit 4 GLOBAL: TIMER bit 3 GLOBAL: TIMER bit 2 GLOBAL: TIMER bit 1 GLOBAL: TIMER bit 0
virtex7 GLOBAL rect WBSTAR
FrameBit
B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 GLOBAL: REVISION_SELECT bit 1 GLOBAL: REVISION_SELECT bit 0 GLOBAL: REVISION_SELECT_TRISTATE GLOBAL: V7_NEXT_CONFIG_ADDR bit 28 GLOBAL: V7_NEXT_CONFIG_ADDR bit 27 GLOBAL: V7_NEXT_CONFIG_ADDR bit 26 GLOBAL: V7_NEXT_CONFIG_ADDR bit 25 GLOBAL: V7_NEXT_CONFIG_ADDR bit 24 GLOBAL: V7_NEXT_CONFIG_ADDR bit 23 GLOBAL: V7_NEXT_CONFIG_ADDR bit 22 GLOBAL: V7_NEXT_CONFIG_ADDR bit 21 GLOBAL: V7_NEXT_CONFIG_ADDR bit 20 GLOBAL: V7_NEXT_CONFIG_ADDR bit 19 GLOBAL: V7_NEXT_CONFIG_ADDR bit 18 GLOBAL: V7_NEXT_CONFIG_ADDR bit 17 GLOBAL: V7_NEXT_CONFIG_ADDR bit 16 GLOBAL: V7_NEXT_CONFIG_ADDR bit 15 GLOBAL: V7_NEXT_CONFIG_ADDR bit 14 GLOBAL: V7_NEXT_CONFIG_ADDR bit 13 GLOBAL: V7_NEXT_CONFIG_ADDR bit 12 GLOBAL: V7_NEXT_CONFIG_ADDR bit 11 GLOBAL: V7_NEXT_CONFIG_ADDR bit 10 GLOBAL: V7_NEXT_CONFIG_ADDR bit 9 GLOBAL: V7_NEXT_CONFIG_ADDR bit 8 GLOBAL: V7_NEXT_CONFIG_ADDR bit 7 GLOBAL: V7_NEXT_CONFIG_ADDR bit 6 GLOBAL: V7_NEXT_CONFIG_ADDR bit 5 GLOBAL: V7_NEXT_CONFIG_ADDR bit 4 GLOBAL: V7_NEXT_CONFIG_ADDR bit 3 GLOBAL: V7_NEXT_CONFIG_ADDR bit 2 GLOBAL: V7_NEXT_CONFIG_ADDR bit 1 GLOBAL: V7_NEXT_CONFIG_ADDR bit 0
virtex7 GLOBAL rect TESTMODE
FrameBit
B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - GLOBAL: TEST_REF_SEL bit 2 GLOBAL: TEST_REF_SEL bit 1 GLOBAL: TEST_REF_SEL bit 0 - - - - - - GLOBAL: TEST_VGG_ENABLE bit 0 - - - - - - - - GLOBAL: TEST_NEG_SLOPE_VGG bit 0 GLOBAL: TEST_VGG_SEL bit 3 GLOBAL: TEST_VGG_SEL bit 2 GLOBAL: TEST_VGG_SEL bit 1 GLOBAL: TEST_VGG_SEL bit 0 - - - - - - - -
virtex7 GLOBAL rect TRIM0
FrameBit
B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - - - - - - - - - - - - - - - - - - - - - - - - - GLOBAL: TRIM_SPARE bit 1 GLOBAL: TRIM_SPARE bit 0 GLOBAL: MPD_DIS_OVERRIDE bit 0 GLOBAL: MPD_OVERRIDE bit 0 GLOBAL: MPD_SEL bit 2 GLOBAL: MPD_SEL bit 1 GLOBAL: MPD_SEL bit 0
virtex7 GLOBAL rect TRIM1
FrameBit
B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 GLOBAL: VGGSEL2 bit 5 GLOBAL: VGGSEL2 bit 4 GLOBAL: VGGSEL2 bit 3 GLOBAL: VGGSEL2 bit 2 GLOBAL: VGGSEL2 bit 1 GLOBAL: VGGSEL2 bit 0 GLOBAL: VGGSEL bit 5 GLOBAL: VGGSEL bit 4 GLOBAL: VGGSEL bit 3 GLOBAL: VGGSEL bit 2 GLOBAL: VGGSEL bit 1 GLOBAL: VGGSEL bit 0 GLOBAL: VBG_FLAT_SEL bit 5 GLOBAL: VBG_FLAT_SEL bit 4 GLOBAL: VBG_FLAT_SEL bit 3 GLOBAL: VBG_FLAT_SEL bit 2 GLOBAL: VBG_FLAT_SEL bit 1 GLOBAL: VBG_FLAT_SEL bit 0 - - - - - - - - - - - - - -
virtex7 GLOBAL rect TRIM2
FrameBit
B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - - - - - - - - GLOBAL: VGG_TRIM_BOT bit 11 GLOBAL: VGG_TRIM_BOT bit 10 GLOBAL: VGG_TRIM_BOT bit 9 GLOBAL: VGG_TRIM_BOT bit 8 GLOBAL: VGG_TRIM_BOT bit 7 GLOBAL: VGG_TRIM_BOT bit 6 GLOBAL: VGG_TRIM_BOT bit 5 GLOBAL: VGG_TRIM_BOT bit 4 GLOBAL: VGG_TRIM_BOT bit 3 GLOBAL: VGG_TRIM_BOT bit 2 GLOBAL: VGG_TRIM_BOT bit 1 GLOBAL: VGG_TRIM_BOT bit 0 GLOBAL: VGG_TRIM_TOP bit 11 GLOBAL: VGG_TRIM_TOP bit 10 GLOBAL: VGG_TRIM_TOP bit 9 GLOBAL: VGG_TRIM_TOP bit 8 GLOBAL: VGG_TRIM_TOP bit 7 GLOBAL: VGG_TRIM_TOP bit 6 GLOBAL: VGG_TRIM_TOP bit 5 GLOBAL: VGG_TRIM_TOP bit 4 GLOBAL: VGG_TRIM_TOP bit 3 GLOBAL: VGG_TRIM_TOP bit 2 GLOBAL: VGG_TRIM_TOP bit 1 GLOBAL: VGG_TRIM_TOP bit 0
virtex7 GLOBAL rect BSPI
FrameBit
B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - - - - GLOBAL: BPI_SYNC_MODE bit 15 GLOBAL: BPI_SYNC_MODE bit 14 GLOBAL: BPI_SYNC_MODE bit 13 GLOBAL: BPI_SYNC_MODE bit 12 GLOBAL: BPI_SYNC_MODE bit 11 GLOBAL: BPI_SYNC_MODE bit 10 GLOBAL: BPI_SYNC_MODE bit 9 GLOBAL: BPI_SYNC_MODE bit 8 GLOBAL: BPI_SYNC_MODE bit 7 GLOBAL: BPI_SYNC_MODE bit 6 GLOBAL: BPI_SYNC_MODE bit 5 GLOBAL: BPI_SYNC_MODE bit 4 GLOBAL: BPI_SYNC_MODE bit 3 GLOBAL: BPI_SYNC_MODE bit 2 GLOBAL: BPI_SYNC_MODE bit 1 GLOBAL: BPI_SYNC_MODE bit 0 - - GLOBAL: SPI_BUSWIDTH bit 1 GLOBAL: SPI_BUSWIDTH bit 0 GLOBAL: SPI_OPCODE bit 7 GLOBAL: SPI_OPCODE bit 6 GLOBAL: SPI_OPCODE bit 5 GLOBAL: SPI_OPCODE bit 4 GLOBAL: SPI_OPCODE bit 3 GLOBAL: SPI_OPCODE bit 2 GLOBAL: SPI_OPCODE bit 1 GLOBAL: SPI_OPCODE bit 0