Processing system
TODO: document
Tile PS
Cells: 100
Bel PS
| Pin | Direction | Wires |
|---|---|---|
| DDRARB0 | input | TCELL50:IMUX.IMUX2 |
| DDRARB1 | input | TCELL50:IMUX.IMUX3 |
| DDRARB2 | input | TCELL50:IMUX.IMUX4 |
| DDRARB3 | input | TCELL50:IMUX.IMUX5 |
| DEBUGDATA0 | output | TCELL0:OUT23.TMIN |
| DEBUGDATA1 | output | TCELL0:OUT22.TMIN |
| DEBUGDATA10 | output | TCELL2:OUT21.TMIN |
| DEBUGDATA100 | output | TCELL25:OUT23.TMIN |
| DEBUGDATA101 | output | TCELL25:OUT22.TMIN |
| DEBUGDATA102 | output | TCELL25:OUT21.TMIN |
| DEBUGDATA103 | output | TCELL25:OUT20.TMIN |
| DEBUGDATA104 | output | TCELL26:OUT23.TMIN |
| DEBUGDATA105 | output | TCELL26:OUT22.TMIN |
| DEBUGDATA106 | output | TCELL26:OUT21.TMIN |
| DEBUGDATA107 | output | TCELL26:OUT20.TMIN |
| DEBUGDATA108 | output | TCELL27:OUT23.TMIN |
| DEBUGDATA109 | output | TCELL27:OUT22.TMIN |
| DEBUGDATA11 | output | TCELL2:OUT20.TMIN |
| DEBUGDATA110 | output | TCELL27:OUT21.TMIN |
| DEBUGDATA111 | output | TCELL27:OUT20.TMIN |
| DEBUGDATA112 | output | TCELL28:OUT23.TMIN |
| DEBUGDATA113 | output | TCELL28:OUT22.TMIN |
| DEBUGDATA114 | output | TCELL28:OUT21.TMIN |
| DEBUGDATA115 | output | TCELL28:OUT20.TMIN |
| DEBUGDATA116 | output | TCELL29:OUT23.TMIN |
| DEBUGDATA117 | output | TCELL29:OUT22.TMIN |
| DEBUGDATA118 | output | TCELL29:OUT21.TMIN |
| DEBUGDATA119 | output | TCELL29:OUT20.TMIN |
| DEBUGDATA12 | output | TCELL3:OUT23.TMIN |
| DEBUGDATA120 | output | TCELL30:OUT23.TMIN |
| DEBUGDATA121 | output | TCELL30:OUT22.TMIN |
| DEBUGDATA122 | output | TCELL30:OUT21.TMIN |
| DEBUGDATA123 | output | TCELL30:OUT20.TMIN |
| DEBUGDATA124 | output | TCELL31:OUT23.TMIN |
| DEBUGDATA125 | output | TCELL31:OUT22.TMIN |
| DEBUGDATA126 | output | TCELL31:OUT21.TMIN |
| DEBUGDATA127 | output | TCELL31:OUT20.TMIN |
| DEBUGDATA128 | output | TCELL32:OUT23.TMIN |
| DEBUGDATA129 | output | TCELL32:OUT22.TMIN |
| DEBUGDATA13 | output | TCELL3:OUT22.TMIN |
| DEBUGDATA130 | output | TCELL32:OUT21.TMIN |
| DEBUGDATA131 | output | TCELL32:OUT20.TMIN |
| DEBUGDATA132 | output | TCELL33:OUT23.TMIN |
| DEBUGDATA133 | output | TCELL33:OUT22.TMIN |
| DEBUGDATA134 | output | TCELL33:OUT21.TMIN |
| DEBUGDATA135 | output | TCELL33:OUT20.TMIN |
| DEBUGDATA136 | output | TCELL34:OUT23.TMIN |
| DEBUGDATA137 | output | TCELL34:OUT22.TMIN |
| DEBUGDATA138 | output | TCELL34:OUT21.TMIN |
| DEBUGDATA139 | output | TCELL34:OUT20.TMIN |
| DEBUGDATA14 | output | TCELL3:OUT21.TMIN |
| DEBUGDATA140 | output | TCELL35:OUT23.TMIN |
| DEBUGDATA141 | output | TCELL35:OUT22.TMIN |
| DEBUGDATA142 | output | TCELL35:OUT21.TMIN |
| DEBUGDATA143 | output | TCELL35:OUT20.TMIN |
| DEBUGDATA144 | output | TCELL36:OUT23.TMIN |
| DEBUGDATA145 | output | TCELL36:OUT22.TMIN |
| DEBUGDATA146 | output | TCELL36:OUT21.TMIN |
| DEBUGDATA147 | output | TCELL36:OUT20.TMIN |
| DEBUGDATA148 | output | TCELL37:OUT23.TMIN |
| DEBUGDATA149 | output | TCELL37:OUT22.TMIN |
| DEBUGDATA15 | output | TCELL3:OUT20.TMIN |
| DEBUGDATA150 | output | TCELL37:OUT21.TMIN |
| DEBUGDATA151 | output | TCELL37:OUT20.TMIN |
| DEBUGDATA152 | output | TCELL38:OUT23.TMIN |
| DEBUGDATA153 | output | TCELL38:OUT22.TMIN |
| DEBUGDATA154 | output | TCELL38:OUT21.TMIN |
| DEBUGDATA155 | output | TCELL38:OUT20.TMIN |
| DEBUGDATA156 | output | TCELL39:OUT23.TMIN |
| DEBUGDATA157 | output | TCELL39:OUT22.TMIN |
| DEBUGDATA158 | output | TCELL39:OUT21.TMIN |
| DEBUGDATA159 | output | TCELL39:OUT20.TMIN |
| DEBUGDATA16 | output | TCELL4:OUT23.TMIN |
| DEBUGDATA160 | output | TCELL40:OUT23.TMIN |
| DEBUGDATA161 | output | TCELL40:OUT22.TMIN |
| DEBUGDATA162 | output | TCELL40:OUT21.TMIN |
| DEBUGDATA163 | output | TCELL40:OUT20.TMIN |
| DEBUGDATA164 | output | TCELL41:OUT23.TMIN |
| DEBUGDATA165 | output | TCELL41:OUT22.TMIN |
| DEBUGDATA166 | output | TCELL41:OUT21.TMIN |
| DEBUGDATA167 | output | TCELL41:OUT20.TMIN |
| DEBUGDATA168 | output | TCELL42:OUT23.TMIN |
| DEBUGDATA169 | output | TCELL42:OUT22.TMIN |
| DEBUGDATA17 | output | TCELL4:OUT22.TMIN |
| DEBUGDATA170 | output | TCELL42:OUT21.TMIN |
| DEBUGDATA171 | output | TCELL42:OUT20.TMIN |
| DEBUGDATA172 | output | TCELL43:OUT23.TMIN |
| DEBUGDATA173 | output | TCELL43:OUT22.TMIN |
| DEBUGDATA174 | output | TCELL43:OUT21.TMIN |
| DEBUGDATA175 | output | TCELL43:OUT20.TMIN |
| DEBUGDATA176 | output | TCELL44:OUT23.TMIN |
| DEBUGDATA177 | output | TCELL44:OUT22.TMIN |
| DEBUGDATA178 | output | TCELL44:OUT21.TMIN |
| DEBUGDATA179 | output | TCELL44:OUT20.TMIN |
| DEBUGDATA18 | output | TCELL4:OUT21.TMIN |
| DEBUGDATA180 | output | TCELL45:OUT23.TMIN |
| DEBUGDATA181 | output | TCELL45:OUT22.TMIN |
| DEBUGDATA182 | output | TCELL45:OUT21.TMIN |
| DEBUGDATA183 | output | TCELL45:OUT20.TMIN |
| DEBUGDATA184 | output | TCELL46:OUT23.TMIN |
| DEBUGDATA185 | output | TCELL46:OUT22.TMIN |
| DEBUGDATA186 | output | TCELL46:OUT21.TMIN |
| DEBUGDATA187 | output | TCELL46:OUT20.TMIN |
| DEBUGDATA188 | output | TCELL47:OUT23.TMIN |
| DEBUGDATA189 | output | TCELL47:OUT22.TMIN |
| DEBUGDATA19 | output | TCELL4:OUT20.TMIN |
| DEBUGDATA190 | output | TCELL48:OUT23.TMIN |
| DEBUGDATA191 | output | TCELL48:OUT22.TMIN |
| DEBUGDATA192 | output | TCELL49:OUT23.TMIN |
| DEBUGDATA193 | output | TCELL49:OUT22.TMIN |
| DEBUGDATA194 | output | TCELL50:OUT23.TMIN |
| DEBUGDATA195 | output | TCELL50:OUT22.TMIN |
| DEBUGDATA196 | output | TCELL51:OUT23.TMIN |
| DEBUGDATA197 | output | TCELL51:OUT22.TMIN |
| DEBUGDATA198 | output | TCELL52:OUT23.TMIN |
| DEBUGDATA199 | output | TCELL52:OUT22.TMIN |
| DEBUGDATA2 | output | TCELL0:OUT21.TMIN |
| DEBUGDATA20 | output | TCELL5:OUT23.TMIN |
| DEBUGDATA21 | output | TCELL5:OUT22.TMIN |
| DEBUGDATA22 | output | TCELL5:OUT21.TMIN |
| DEBUGDATA23 | output | TCELL5:OUT20.TMIN |
| DEBUGDATA24 | output | TCELL6:OUT23.TMIN |
| DEBUGDATA25 | output | TCELL6:OUT22.TMIN |
| DEBUGDATA26 | output | TCELL6:OUT21.TMIN |
| DEBUGDATA27 | output | TCELL6:OUT20.TMIN |
| DEBUGDATA28 | output | TCELL7:OUT23.TMIN |
| DEBUGDATA29 | output | TCELL7:OUT22.TMIN |
| DEBUGDATA3 | output | TCELL0:OUT20.TMIN |
| DEBUGDATA30 | output | TCELL7:OUT21.TMIN |
| DEBUGDATA31 | output | TCELL7:OUT20.TMIN |
| DEBUGDATA32 | output | TCELL8:OUT23.TMIN |
| DEBUGDATA33 | output | TCELL8:OUT22.TMIN |
| DEBUGDATA34 | output | TCELL8:OUT21.TMIN |
| DEBUGDATA35 | output | TCELL8:OUT20.TMIN |
| DEBUGDATA36 | output | TCELL9:OUT23.TMIN |
| DEBUGDATA37 | output | TCELL9:OUT22.TMIN |
| DEBUGDATA38 | output | TCELL9:OUT21.TMIN |
| DEBUGDATA39 | output | TCELL9:OUT20.TMIN |
| DEBUGDATA4 | output | TCELL1:OUT23.TMIN |
| DEBUGDATA40 | output | TCELL10:OUT23.TMIN |
| DEBUGDATA41 | output | TCELL10:OUT22.TMIN |
| DEBUGDATA42 | output | TCELL10:OUT21.TMIN |
| DEBUGDATA43 | output | TCELL10:OUT20.TMIN |
| DEBUGDATA44 | output | TCELL11:OUT23.TMIN |
| DEBUGDATA45 | output | TCELL11:OUT22.TMIN |
| DEBUGDATA46 | output | TCELL11:OUT21.TMIN |
| DEBUGDATA47 | output | TCELL11:OUT20.TMIN |
| DEBUGDATA48 | output | TCELL12:OUT23.TMIN |
| DEBUGDATA49 | output | TCELL12:OUT22.TMIN |
| DEBUGDATA5 | output | TCELL1:OUT22.TMIN |
| DEBUGDATA50 | output | TCELL12:OUT21.TMIN |
| DEBUGDATA51 | output | TCELL12:OUT20.TMIN |
| DEBUGDATA52 | output | TCELL13:OUT23.TMIN |
| DEBUGDATA53 | output | TCELL13:OUT22.TMIN |
| DEBUGDATA54 | output | TCELL13:OUT21.TMIN |
| DEBUGDATA55 | output | TCELL13:OUT20.TMIN |
| DEBUGDATA56 | output | TCELL14:OUT23.TMIN |
| DEBUGDATA57 | output | TCELL14:OUT22.TMIN |
| DEBUGDATA58 | output | TCELL14:OUT21.TMIN |
| DEBUGDATA59 | output | TCELL14:OUT20.TMIN |
| DEBUGDATA6 | output | TCELL1:OUT21.TMIN |
| DEBUGDATA60 | output | TCELL15:OUT23.TMIN |
| DEBUGDATA61 | output | TCELL15:OUT22.TMIN |
| DEBUGDATA62 | output | TCELL15:OUT21.TMIN |
| DEBUGDATA63 | output | TCELL15:OUT20.TMIN |
| DEBUGDATA64 | output | TCELL16:OUT23.TMIN |
| DEBUGDATA65 | output | TCELL16:OUT22.TMIN |
| DEBUGDATA66 | output | TCELL16:OUT21.TMIN |
| DEBUGDATA67 | output | TCELL16:OUT20.TMIN |
| DEBUGDATA68 | output | TCELL17:OUT23.TMIN |
| DEBUGDATA69 | output | TCELL17:OUT22.TMIN |
| DEBUGDATA7 | output | TCELL1:OUT20.TMIN |
| DEBUGDATA70 | output | TCELL17:OUT21.TMIN |
| DEBUGDATA71 | output | TCELL17:OUT20.TMIN |
| DEBUGDATA72 | output | TCELL18:OUT23.TMIN |
| DEBUGDATA73 | output | TCELL18:OUT22.TMIN |
| DEBUGDATA74 | output | TCELL18:OUT21.TMIN |
| DEBUGDATA75 | output | TCELL18:OUT20.TMIN |
| DEBUGDATA76 | output | TCELL19:OUT23.TMIN |
| DEBUGDATA77 | output | TCELL19:OUT22.TMIN |
| DEBUGDATA78 | output | TCELL19:OUT21.TMIN |
| DEBUGDATA79 | output | TCELL19:OUT20.TMIN |
| DEBUGDATA8 | output | TCELL2:OUT23.TMIN |
| DEBUGDATA80 | output | TCELL20:OUT23.TMIN |
| DEBUGDATA81 | output | TCELL20:OUT22.TMIN |
| DEBUGDATA82 | output | TCELL20:OUT21.TMIN |
| DEBUGDATA83 | output | TCELL20:OUT20.TMIN |
| DEBUGDATA84 | output | TCELL21:OUT23.TMIN |
| DEBUGDATA85 | output | TCELL21:OUT22.TMIN |
| DEBUGDATA86 | output | TCELL21:OUT21.TMIN |
| DEBUGDATA87 | output | TCELL21:OUT20.TMIN |
| DEBUGDATA88 | output | TCELL22:OUT23.TMIN |
| DEBUGDATA89 | output | TCELL22:OUT22.TMIN |
| DEBUGDATA9 | output | TCELL2:OUT22.TMIN |
| DEBUGDATA90 | output | TCELL22:OUT21.TMIN |
| DEBUGDATA91 | output | TCELL22:OUT20.TMIN |
| DEBUGDATA92 | output | TCELL23:OUT23.TMIN |
| DEBUGDATA93 | output | TCELL23:OUT22.TMIN |
| DEBUGDATA94 | output | TCELL23:OUT21.TMIN |
| DEBUGDATA95 | output | TCELL23:OUT20.TMIN |
| DEBUGDATA96 | output | TCELL24:OUT23.TMIN |
| DEBUGDATA97 | output | TCELL24:OUT22.TMIN |
| DEBUGDATA98 | output | TCELL24:OUT21.TMIN |
| DEBUGDATA99 | output | TCELL24:OUT20.TMIN |
| DEBUGSELECT0 | input | TCELL36:IMUX.IMUX47 |
| DEBUGSELECT1 | input | TCELL36:IMUX.IMUX46 |
| DEBUGSELECT10 | input | TCELL38:IMUX.IMUX45 |
| DEBUGSELECT11 | input | TCELL38:IMUX.IMUX44 |
| DEBUGSELECT12 | input | TCELL39:IMUX.IMUX47 |
| DEBUGSELECT13 | input | TCELL39:IMUX.IMUX46 |
| DEBUGSELECT14 | input | TCELL39:IMUX.IMUX45 |
| DEBUGSELECT15 | input | TCELL39:IMUX.IMUX44 |
| DEBUGSELECT2 | input | TCELL36:IMUX.IMUX45 |
| DEBUGSELECT3 | input | TCELL36:IMUX.IMUX44 |
| DEBUGSELECT4 | input | TCELL37:IMUX.IMUX47 |
| DEBUGSELECT5 | input | TCELL37:IMUX.IMUX46 |
| DEBUGSELECT6 | input | TCELL37:IMUX.IMUX45 |
| DEBUGSELECT7 | input | TCELL37:IMUX.IMUX44 |
| DEBUGSELECT8 | input | TCELL38:IMUX.IMUX47 |
| DEBUGSELECT9 | input | TCELL38:IMUX.IMUX46 |
| DMA0ACLK | input | TCELL36:IMUX.CLK0 |
| DMA0DAREADY | input | TCELL36:IMUX.IMUX0 |
| DMA0DATYPE0 | output | TCELL32:OUT0.TMIN |
| DMA0DATYPE1 | output | TCELL32:OUT1.TMIN |
| DMA0DAVALID | output | TCELL32:OUT2.TMIN |
| DMA0DRLAST | input | TCELL36:IMUX.IMUX1 |
| DMA0DRREADY | output | TCELL40:OUT0.TMIN |
| DMA0DRTYPE0 | input | TCELL40:IMUX.IMUX0 |
| DMA0DRTYPE1 | input | TCELL40:IMUX.IMUX1 |
| DMA0DRVALID | input | TCELL40:IMUX.IMUX2 |
| DMA0RSTN | output | TCELL36:OUT0.TMIN |
| DMA1ACLK | input | TCELL37:IMUX.CLK0 |
| DMA1DAREADY | input | TCELL37:IMUX.IMUX0 |
| DMA1DATYPE0 | output | TCELL33:OUT0.TMIN |
| DMA1DATYPE1 | output | TCELL33:OUT1.TMIN |
| DMA1DAVALID | output | TCELL33:OUT2.TMIN |
| DMA1DRLAST | input | TCELL37:IMUX.IMUX1 |
| DMA1DRREADY | output | TCELL41:OUT0.TMIN |
| DMA1DRTYPE0 | input | TCELL41:IMUX.IMUX0 |
| DMA1DRTYPE1 | input | TCELL41:IMUX.IMUX1 |
| DMA1DRVALID | input | TCELL41:IMUX.IMUX2 |
| DMA1RSTN | output | TCELL37:OUT0.TMIN |
| DMA2ACLK | input | TCELL38:IMUX.CLK0 |
| DMA2DAREADY | input | TCELL38:IMUX.IMUX0 |
| DMA2DATYPE0 | output | TCELL32:OUT3.TMIN |
| DMA2DATYPE1 | output | TCELL32:OUT4.TMIN |
| DMA2DAVALID | output | TCELL32:OUT5.TMIN |
| DMA2DRLAST | input | TCELL38:IMUX.IMUX1 |
| DMA2DRREADY | output | TCELL42:OUT0.TMIN |
| DMA2DRTYPE0 | input | TCELL42:IMUX.IMUX0 |
| DMA2DRTYPE1 | input | TCELL42:IMUX.IMUX1 |
| DMA2DRVALID | input | TCELL42:IMUX.IMUX2 |
| DMA2RSTN | output | TCELL38:OUT0.TMIN |
| DMA3ACLK | input | TCELL39:IMUX.CLK0 |
| DMA3DAREADY | input | TCELL39:IMUX.IMUX0 |
| DMA3DATYPE0 | output | TCELL33:OUT3.TMIN |
| DMA3DATYPE1 | output | TCELL33:OUT4.TMIN |
| DMA3DAVALID | output | TCELL33:OUT5.TMIN |
| DMA3DRLAST | input | TCELL39:IMUX.IMUX1 |
| DMA3DRREADY | output | TCELL43:OUT0.TMIN |
| DMA3DRTYPE0 | input | TCELL43:IMUX.IMUX0 |
| DMA3DRTYPE1 | input | TCELL43:IMUX.IMUX1 |
| DMA3DRVALID | input | TCELL43:IMUX.IMUX2 |
| DMA3RSTN | output | TCELL39:OUT0.TMIN |
| EMIOCAN0PHYRX | input | TCELL89:IMUX.IMUX6 |
| EMIOCAN0PHYTX | output | TCELL89:OUT8.TMIN |
| EMIOCAN1PHYRX | input | TCELL90:IMUX.IMUX5 |
| EMIOCAN1PHYTX | output | TCELL90:OUT7.TMIN |
| EMIOENET0EXTINTIN | input | TCELL66:IMUX.IMUX1 |
| EMIOENET0GMIICOL | input | TCELL68:IMUX.IMUX1 |
| EMIOENET0GMIICRS | input | TCELL68:IMUX.IMUX0 |
| EMIOENET0GMIIRXCLK | input | TCELL68:IMUX.CLK0 |
| EMIOENET0GMIIRXD0 | input | TCELL67:IMUX.IMUX0 |
| EMIOENET0GMIIRXD1 | input | TCELL67:IMUX.IMUX1 |
| EMIOENET0GMIIRXD2 | input | TCELL67:IMUX.IMUX2 |
| EMIOENET0GMIIRXD3 | input | TCELL67:IMUX.IMUX3 |
| EMIOENET0GMIIRXD4 | input | TCELL68:IMUX.IMUX2 |
| EMIOENET0GMIIRXD5 | input | TCELL68:IMUX.IMUX3 |
| EMIOENET0GMIIRXD6 | input | TCELL68:IMUX.IMUX4 |
| EMIOENET0GMIIRXD7 | input | TCELL68:IMUX.IMUX5 |
| EMIOENET0GMIIRXDV | input | TCELL68:IMUX.IMUX7 |
| EMIOENET0GMIIRXER | input | TCELL68:IMUX.IMUX6 |
| EMIOENET0GMIITXCLK | input | TCELL67:IMUX.CLK0 |
| EMIOENET0GMIITXD0 | output | TCELL67:OUT0.TMIN |
| EMIOENET0GMIITXD1 | output | TCELL67:OUT1.TMIN |
| EMIOENET0GMIITXD2 | output | TCELL67:OUT2.TMIN |
| EMIOENET0GMIITXD3 | output | TCELL67:OUT3.TMIN |
| EMIOENET0GMIITXD4 | output | TCELL68:OUT0.TMIN |
| EMIOENET0GMIITXD5 | output | TCELL68:OUT1.TMIN |
| EMIOENET0GMIITXD6 | output | TCELL68:OUT2.TMIN |
| EMIOENET0GMIITXD7 | output | TCELL68:OUT3.TMIN |
| EMIOENET0GMIITXEN | output | TCELL68:OUT4.TMIN |
| EMIOENET0GMIITXER | output | TCELL67:OUT4.TMIN |
| EMIOENET0MDIOI | input | TCELL66:IMUX.IMUX0 |
| EMIOENET0MDIOMDC | output | TCELL67:OUT5.TMIN |
| EMIOENET0MDIOO | output | TCELL66:OUT0.TMIN |
| EMIOENET0MDIOTN | output | TCELL66:OUT1.TMIN |
| EMIOENET0PTPDELAYREQRX | output | TCELL65:OUT4.TMIN |
| EMIOENET0PTPDELAYREQTX | output | TCELL66:OUT3.TMIN |
| EMIOENET0PTPPDELAYREQRX | output | TCELL65:OUT5.TMIN |
| EMIOENET0PTPPDELAYREQTX | output | TCELL65:OUT0.TMIN |
| EMIOENET0PTPPDELAYRESPRX | output | TCELL66:OUT4.TMIN |
| EMIOENET0PTPPDELAYRESPTX | output | TCELL65:OUT1.TMIN |
| EMIOENET0PTPSYNCFRAMERX | output | TCELL65:OUT3.TMIN |
| EMIOENET0PTPSYNCFRAMETX | output | TCELL66:OUT2.TMIN |
| EMIOENET0SOFRX | output | TCELL66:OUT5.TMIN |
| EMIOENET0SOFTX | output | TCELL65:OUT2.TMIN |
| EMIOENET1EXTINTIN | input | TCELL70:IMUX.IMUX1 |
| EMIOENET1GMIICOL | input | TCELL72:IMUX.IMUX1 |
| EMIOENET1GMIICRS | input | TCELL72:IMUX.IMUX0 |
| EMIOENET1GMIIRXCLK | input | TCELL72:IMUX.CLK0 |
| EMIOENET1GMIIRXD0 | input | TCELL71:IMUX.IMUX0 |
| EMIOENET1GMIIRXD1 | input | TCELL71:IMUX.IMUX1 |
| EMIOENET1GMIIRXD2 | input | TCELL71:IMUX.IMUX2 |
| EMIOENET1GMIIRXD3 | input | TCELL71:IMUX.IMUX3 |
| EMIOENET1GMIIRXD4 | input | TCELL72:IMUX.IMUX2 |
| EMIOENET1GMIIRXD5 | input | TCELL72:IMUX.IMUX3 |
| EMIOENET1GMIIRXD6 | input | TCELL72:IMUX.IMUX4 |
| EMIOENET1GMIIRXD7 | input | TCELL72:IMUX.IMUX5 |
| EMIOENET1GMIIRXDV | input | TCELL72:IMUX.IMUX7 |
| EMIOENET1GMIIRXER | input | TCELL72:IMUX.IMUX6 |
| EMIOENET1GMIITXCLK | input | TCELL71:IMUX.CLK0 |
| EMIOENET1GMIITXD0 | output | TCELL71:OUT0.TMIN |
| EMIOENET1GMIITXD1 | output | TCELL71:OUT1.TMIN |
| EMIOENET1GMIITXD2 | output | TCELL71:OUT2.TMIN |
| EMIOENET1GMIITXD3 | output | TCELL71:OUT3.TMIN |
| EMIOENET1GMIITXD4 | output | TCELL72:OUT0.TMIN |
| EMIOENET1GMIITXD5 | output | TCELL72:OUT1.TMIN |
| EMIOENET1GMIITXD6 | output | TCELL72:OUT2.TMIN |
| EMIOENET1GMIITXD7 | output | TCELL72:OUT3.TMIN |
| EMIOENET1GMIITXEN | output | TCELL72:OUT4.TMIN |
| EMIOENET1GMIITXER | output | TCELL71:OUT4.TMIN |
| EMIOENET1MDIOI | input | TCELL70:IMUX.IMUX0 |
| EMIOENET1MDIOMDC | output | TCELL71:OUT5.TMIN |
| EMIOENET1MDIOO | output | TCELL70:OUT0.TMIN |
| EMIOENET1MDIOTN | output | TCELL70:OUT1.TMIN |
| EMIOENET1PTPDELAYREQRX | output | TCELL69:OUT4.TMIN |
| EMIOENET1PTPDELAYREQTX | output | TCELL70:OUT3.TMIN |
| EMIOENET1PTPPDELAYREQRX | output | TCELL69:OUT5.TMIN |
| EMIOENET1PTPPDELAYREQTX | output | TCELL69:OUT0.TMIN |
| EMIOENET1PTPPDELAYRESPRX | output | TCELL70:OUT4.TMIN |
| EMIOENET1PTPPDELAYRESPTX | output | TCELL69:OUT1.TMIN |
| EMIOENET1PTPSYNCFRAMERX | output | TCELL69:OUT3.TMIN |
| EMIOENET1PTPSYNCFRAMETX | output | TCELL70:OUT2.TMIN |
| EMIOENET1SOFRX | output | TCELL70:OUT5.TMIN |
| EMIOENET1SOFTX | output | TCELL69:OUT2.TMIN |
| EMIOGPIOI0 | input | TCELL60:IMUX.IMUX0 |
| EMIOGPIOI1 | input | TCELL60:IMUX.IMUX1 |
| EMIOGPIOI10 | input | TCELL62:IMUX.IMUX2 |
| EMIOGPIOI11 | input | TCELL62:IMUX.IMUX3 |
| EMIOGPIOI12 | input | TCELL63:IMUX.IMUX0 |
| EMIOGPIOI13 | input | TCELL63:IMUX.IMUX1 |
| EMIOGPIOI14 | input | TCELL63:IMUX.IMUX2 |
| EMIOGPIOI15 | input | TCELL63:IMUX.IMUX3 |
| EMIOGPIOI16 | input | TCELL64:IMUX.IMUX0 |
| EMIOGPIOI17 | input | TCELL64:IMUX.IMUX1 |
| EMIOGPIOI18 | input | TCELL64:IMUX.IMUX2 |
| EMIOGPIOI19 | input | TCELL64:IMUX.IMUX3 |
| EMIOGPIOI2 | input | TCELL60:IMUX.IMUX2 |
| EMIOGPIOI20 | input | TCELL65:IMUX.IMUX0 |
| EMIOGPIOI21 | input | TCELL65:IMUX.IMUX1 |
| EMIOGPIOI22 | input | TCELL65:IMUX.IMUX2 |
| EMIOGPIOI23 | input | TCELL65:IMUX.IMUX3 |
| EMIOGPIOI24 | input | TCELL66:IMUX.IMUX2 |
| EMIOGPIOI25 | input | TCELL66:IMUX.IMUX3 |
| EMIOGPIOI26 | input | TCELL66:IMUX.IMUX4 |
| EMIOGPIOI27 | input | TCELL66:IMUX.IMUX5 |
| EMIOGPIOI28 | input | TCELL67:IMUX.IMUX4 |
| EMIOGPIOI29 | input | TCELL67:IMUX.IMUX5 |
| EMIOGPIOI3 | input | TCELL60:IMUX.IMUX3 |
| EMIOGPIOI30 | input | TCELL67:IMUX.IMUX6 |
| EMIOGPIOI31 | input | TCELL67:IMUX.IMUX7 |
| EMIOGPIOI32 | input | TCELL68:IMUX.IMUX8 |
| EMIOGPIOI33 | input | TCELL68:IMUX.IMUX9 |
| EMIOGPIOI34 | input | TCELL68:IMUX.IMUX10 |
| EMIOGPIOI35 | input | TCELL68:IMUX.IMUX11 |
| EMIOGPIOI36 | input | TCELL69:IMUX.IMUX0 |
| EMIOGPIOI37 | input | TCELL69:IMUX.IMUX1 |
| EMIOGPIOI38 | input | TCELL69:IMUX.IMUX2 |
| EMIOGPIOI39 | input | TCELL69:IMUX.IMUX3 |
| EMIOGPIOI4 | input | TCELL61:IMUX.IMUX0 |
| EMIOGPIOI40 | input | TCELL70:IMUX.IMUX2 |
| EMIOGPIOI41 | input | TCELL70:IMUX.IMUX3 |
| EMIOGPIOI42 | input | TCELL70:IMUX.IMUX4 |
| EMIOGPIOI43 | input | TCELL70:IMUX.IMUX5 |
| EMIOGPIOI44 | input | TCELL70:IMUX.IMUX6 |
| EMIOGPIOI45 | input | TCELL70:IMUX.IMUX7 |
| EMIOGPIOI46 | input | TCELL70:IMUX.IMUX8 |
| EMIOGPIOI47 | input | TCELL70:IMUX.IMUX9 |
| EMIOGPIOI48 | input | TCELL71:IMUX.IMUX4 |
| EMIOGPIOI49 | input | TCELL71:IMUX.IMUX5 |
| EMIOGPIOI5 | input | TCELL61:IMUX.IMUX1 |
| EMIOGPIOI50 | input | TCELL71:IMUX.IMUX6 |
| EMIOGPIOI51 | input | TCELL71:IMUX.IMUX7 |
| EMIOGPIOI52 | input | TCELL71:IMUX.IMUX8 |
| EMIOGPIOI53 | input | TCELL71:IMUX.IMUX9 |
| EMIOGPIOI54 | input | TCELL71:IMUX.IMUX10 |
| EMIOGPIOI55 | input | TCELL71:IMUX.IMUX11 |
| EMIOGPIOI56 | input | TCELL72:IMUX.IMUX8 |
| EMIOGPIOI57 | input | TCELL72:IMUX.IMUX9 |
| EMIOGPIOI58 | input | TCELL72:IMUX.IMUX10 |
| EMIOGPIOI59 | input | TCELL72:IMUX.IMUX11 |
| EMIOGPIOI6 | input | TCELL61:IMUX.IMUX2 |
| EMIOGPIOI60 | input | TCELL72:IMUX.IMUX12 |
| EMIOGPIOI61 | input | TCELL72:IMUX.IMUX13 |
| EMIOGPIOI62 | input | TCELL72:IMUX.IMUX14 |
| EMIOGPIOI63 | input | TCELL72:IMUX.IMUX15 |
| EMIOGPIOI7 | input | TCELL61:IMUX.IMUX3 |
| EMIOGPIOI8 | input | TCELL62:IMUX.IMUX0 |
| EMIOGPIOI9 | input | TCELL62:IMUX.IMUX1 |
| EMIOGPIOO0 | output | TCELL73:OUT0.TMIN |
| EMIOGPIOO1 | output | TCELL73:OUT1.TMIN |
| EMIOGPIOO10 | output | TCELL75:OUT2.TMIN |
| EMIOGPIOO11 | output | TCELL75:OUT3.TMIN |
| EMIOGPIOO12 | output | TCELL76:OUT0.TMIN |
| EMIOGPIOO13 | output | TCELL76:OUT1.TMIN |
| EMIOGPIOO14 | output | TCELL76:OUT2.TMIN |
| EMIOGPIOO15 | output | TCELL76:OUT3.TMIN |
| EMIOGPIOO16 | output | TCELL77:OUT0.TMIN |
| EMIOGPIOO17 | output | TCELL77:OUT1.TMIN |
| EMIOGPIOO18 | output | TCELL77:OUT2.TMIN |
| EMIOGPIOO19 | output | TCELL77:OUT3.TMIN |
| EMIOGPIOO2 | output | TCELL73:OUT2.TMIN |
| EMIOGPIOO20 | output | TCELL78:OUT0.TMIN |
| EMIOGPIOO21 | output | TCELL78:OUT1.TMIN |
| EMIOGPIOO22 | output | TCELL78:OUT2.TMIN |
| EMIOGPIOO23 | output | TCELL78:OUT3.TMIN |
| EMIOGPIOO24 | output | TCELL79:OUT0.TMIN |
| EMIOGPIOO25 | output | TCELL79:OUT1.TMIN |
| EMIOGPIOO26 | output | TCELL79:OUT2.TMIN |
| EMIOGPIOO27 | output | TCELL79:OUT3.TMIN |
| EMIOGPIOO28 | output | TCELL80:OUT0.TMIN |
| EMIOGPIOO29 | output | TCELL80:OUT1.TMIN |
| EMIOGPIOO3 | output | TCELL73:OUT3.TMIN |
| EMIOGPIOO30 | output | TCELL80:OUT2.TMIN |
| EMIOGPIOO31 | output | TCELL80:OUT3.TMIN |
| EMIOGPIOO32 | output | TCELL81:OUT0.TMIN |
| EMIOGPIOO33 | output | TCELL81:OUT1.TMIN |
| EMIOGPIOO34 | output | TCELL81:OUT2.TMIN |
| EMIOGPIOO35 | output | TCELL81:OUT3.TMIN |
| EMIOGPIOO36 | output | TCELL82:OUT0.TMIN |
| EMIOGPIOO37 | output | TCELL82:OUT1.TMIN |
| EMIOGPIOO38 | output | TCELL82:OUT2.TMIN |
| EMIOGPIOO39 | output | TCELL82:OUT3.TMIN |
| EMIOGPIOO4 | output | TCELL74:OUT0.TMIN |
| EMIOGPIOO40 | output | TCELL83:OUT0.TMIN |
| EMIOGPIOO41 | output | TCELL83:OUT1.TMIN |
| EMIOGPIOO42 | output | TCELL83:OUT2.TMIN |
| EMIOGPIOO43 | output | TCELL83:OUT3.TMIN |
| EMIOGPIOO44 | output | TCELL84:OUT0.TMIN |
| EMIOGPIOO45 | output | TCELL84:OUT1.TMIN |
| EMIOGPIOO46 | output | TCELL84:OUT2.TMIN |
| EMIOGPIOO47 | output | TCELL84:OUT3.TMIN |
| EMIOGPIOO48 | output | TCELL85:OUT0.TMIN |
| EMIOGPIOO49 | output | TCELL85:OUT1.TMIN |
| EMIOGPIOO5 | output | TCELL74:OUT1.TMIN |
| EMIOGPIOO50 | output | TCELL85:OUT2.TMIN |
| EMIOGPIOO51 | output | TCELL85:OUT3.TMIN |
| EMIOGPIOO52 | output | TCELL86:OUT0.TMIN |
| EMIOGPIOO53 | output | TCELL86:OUT1.TMIN |
| EMIOGPIOO54 | output | TCELL86:OUT2.TMIN |
| EMIOGPIOO55 | output | TCELL86:OUT3.TMIN |
| EMIOGPIOO56 | output | TCELL87:OUT0.TMIN |
| EMIOGPIOO57 | output | TCELL87:OUT1.TMIN |
| EMIOGPIOO58 | output | TCELL87:OUT2.TMIN |
| EMIOGPIOO59 | output | TCELL87:OUT3.TMIN |
| EMIOGPIOO6 | output | TCELL74:OUT2.TMIN |
| EMIOGPIOO60 | output | TCELL88:OUT0.TMIN |
| EMIOGPIOO61 | output | TCELL88:OUT1.TMIN |
| EMIOGPIOO62 | output | TCELL88:OUT2.TMIN |
| EMIOGPIOO63 | output | TCELL88:OUT3.TMIN |
| EMIOGPIOO7 | output | TCELL74:OUT3.TMIN |
| EMIOGPIOO8 | output | TCELL75:OUT0.TMIN |
| EMIOGPIOO9 | output | TCELL75:OUT1.TMIN |
| EMIOGPIOTN0 | output | TCELL73:OUT4.TMIN |
| EMIOGPIOTN1 | output | TCELL73:OUT5.TMIN |
| EMIOGPIOTN10 | output | TCELL75:OUT6.TMIN |
| EMIOGPIOTN11 | output | TCELL75:OUT7.TMIN |
| EMIOGPIOTN12 | output | TCELL76:OUT4.TMIN |
| EMIOGPIOTN13 | output | TCELL76:OUT5.TMIN |
| EMIOGPIOTN14 | output | TCELL76:OUT6.TMIN |
| EMIOGPIOTN15 | output | TCELL76:OUT7.TMIN |
| EMIOGPIOTN16 | output | TCELL77:OUT4.TMIN |
| EMIOGPIOTN17 | output | TCELL77:OUT5.TMIN |
| EMIOGPIOTN18 | output | TCELL77:OUT6.TMIN |
| EMIOGPIOTN19 | output | TCELL77:OUT7.TMIN |
| EMIOGPIOTN2 | output | TCELL73:OUT6.TMIN |
| EMIOGPIOTN20 | output | TCELL78:OUT4.TMIN |
| EMIOGPIOTN21 | output | TCELL78:OUT5.TMIN |
| EMIOGPIOTN22 | output | TCELL78:OUT6.TMIN |
| EMIOGPIOTN23 | output | TCELL78:OUT7.TMIN |
| EMIOGPIOTN24 | output | TCELL79:OUT4.TMIN |
| EMIOGPIOTN25 | output | TCELL79:OUT5.TMIN |
| EMIOGPIOTN26 | output | TCELL79:OUT6.TMIN |
| EMIOGPIOTN27 | output | TCELL79:OUT7.TMIN |
| EMIOGPIOTN28 | output | TCELL80:OUT4.TMIN |
| EMIOGPIOTN29 | output | TCELL80:OUT5.TMIN |
| EMIOGPIOTN3 | output | TCELL73:OUT7.TMIN |
| EMIOGPIOTN30 | output | TCELL80:OUT6.TMIN |
| EMIOGPIOTN31 | output | TCELL80:OUT7.TMIN |
| EMIOGPIOTN32 | output | TCELL81:OUT4.TMIN |
| EMIOGPIOTN33 | output | TCELL81:OUT5.TMIN |
| EMIOGPIOTN34 | output | TCELL81:OUT6.TMIN |
| EMIOGPIOTN35 | output | TCELL81:OUT7.TMIN |
| EMIOGPIOTN36 | output | TCELL82:OUT4.TMIN |
| EMIOGPIOTN37 | output | TCELL82:OUT5.TMIN |
| EMIOGPIOTN38 | output | TCELL82:OUT6.TMIN |
| EMIOGPIOTN39 | output | TCELL82:OUT7.TMIN |
| EMIOGPIOTN4 | output | TCELL74:OUT4.TMIN |
| EMIOGPIOTN40 | output | TCELL83:OUT4.TMIN |
| EMIOGPIOTN41 | output | TCELL83:OUT5.TMIN |
| EMIOGPIOTN42 | output | TCELL83:OUT6.TMIN |
| EMIOGPIOTN43 | output | TCELL83:OUT7.TMIN |
| EMIOGPIOTN44 | output | TCELL84:OUT4.TMIN |
| EMIOGPIOTN45 | output | TCELL84:OUT5.TMIN |
| EMIOGPIOTN46 | output | TCELL84:OUT6.TMIN |
| EMIOGPIOTN47 | output | TCELL84:OUT7.TMIN |
| EMIOGPIOTN48 | output | TCELL85:OUT4.TMIN |
| EMIOGPIOTN49 | output | TCELL85:OUT5.TMIN |
| EMIOGPIOTN5 | output | TCELL74:OUT5.TMIN |
| EMIOGPIOTN50 | output | TCELL85:OUT6.TMIN |
| EMIOGPIOTN51 | output | TCELL85:OUT7.TMIN |
| EMIOGPIOTN52 | output | TCELL86:OUT4.TMIN |
| EMIOGPIOTN53 | output | TCELL86:OUT5.TMIN |
| EMIOGPIOTN54 | output | TCELL86:OUT6.TMIN |
| EMIOGPIOTN55 | output | TCELL86:OUT7.TMIN |
| EMIOGPIOTN56 | output | TCELL87:OUT4.TMIN |
| EMIOGPIOTN57 | output | TCELL87:OUT5.TMIN |
| EMIOGPIOTN58 | output | TCELL87:OUT6.TMIN |
| EMIOGPIOTN59 | output | TCELL87:OUT7.TMIN |
| EMIOGPIOTN6 | output | TCELL74:OUT6.TMIN |
| EMIOGPIOTN60 | output | TCELL88:OUT4.TMIN |
| EMIOGPIOTN61 | output | TCELL88:OUT5.TMIN |
| EMIOGPIOTN62 | output | TCELL88:OUT6.TMIN |
| EMIOGPIOTN63 | output | TCELL88:OUT7.TMIN |
| EMIOGPIOTN7 | output | TCELL74:OUT7.TMIN |
| EMIOGPIOTN8 | output | TCELL75:OUT4.TMIN |
| EMIOGPIOTN9 | output | TCELL75:OUT5.TMIN |
| EMIOI2C0SCLI | input | TCELL89:IMUX.IMUX4 |
| EMIOI2C0SCLO | output | TCELL89:OUT4.TMIN |
| EMIOI2C0SCLTN | output | TCELL89:OUT5.TMIN |
| EMIOI2C0SDAI | input | TCELL89:IMUX.IMUX5 |
| EMIOI2C0SDAO | output | TCELL89:OUT6.TMIN |
| EMIOI2C0SDATN | output | TCELL89:OUT7.TMIN |
| EMIOI2C1SCLI | input | TCELL90:IMUX.IMUX3 |
| EMIOI2C1SCLO | output | TCELL90:OUT3.TMIN |
| EMIOI2C1SCLTN | output | TCELL90:OUT4.TMIN |
| EMIOI2C1SDAI | input | TCELL90:IMUX.IMUX4 |
| EMIOI2C1SDAO | output | TCELL90:OUT5.TMIN |
| EMIOI2C1SDATN | output | TCELL90:OUT6.TMIN |
| EMIOPJTAGTCK | input | TCELL98:IMUX.CLK0 |
| EMIOPJTAGTDI | input | TCELL96:IMUX.IMUX1 |
| EMIOPJTAGTDO | output | TCELL97:OUT9.TMIN |
| EMIOPJTAGTDTN | output | TCELL97:OUT8.TMIN |
| EMIOPJTAGTMS | input | TCELL96:IMUX.IMUX0 |
| EMIOSDIO0BUSPOW | output | TCELL92:OUT4.TMIN |
| EMIOSDIO0BUSVOLT0 | output | TCELL91:OUT4.TMIN |
| EMIOSDIO0BUSVOLT1 | output | TCELL93:OUT5.TMIN |
| EMIOSDIO0BUSVOLT2 | output | TCELL94:OUT9.TMIN |
| EMIOSDIO0CDN | input | TCELL94:IMUX.IMUX3 |
| EMIOSDIO0CLK | output | TCELL94:OUT4.TMIN |
| EMIOSDIO0CLKFB | input | TCELL92:IMUX.CLK0 |
| EMIOSDIO0CMDI | input | TCELL94:IMUX.IMUX2 |
| EMIOSDIO0CMDO | output | TCELL94:OUT5.TMIN |
| EMIOSDIO0CMDTN | output | TCELL94:OUT6.TMIN |
| EMIOSDIO0DATAI0 | input | TCELL93:IMUX.IMUX2 |
| EMIOSDIO0DATAI1 | input | TCELL93:IMUX.IMUX3 |
| EMIOSDIO0DATAI2 | input | TCELL93:IMUX.IMUX4 |
| EMIOSDIO0DATAI3 | input | TCELL93:IMUX.IMUX5 |
| EMIOSDIO0DATAO0 | output | TCELL91:OUT0.TMIN |
| EMIOSDIO0DATAO1 | output | TCELL91:OUT1.TMIN |
| EMIOSDIO0DATAO2 | output | TCELL91:OUT2.TMIN |
| EMIOSDIO0DATAO3 | output | TCELL91:OUT3.TMIN |
| EMIOSDIO0DATATN0 | output | TCELL93:OUT3.TMIN |
| EMIOSDIO0DATATN1 | output | TCELL93:OUT4.TMIN |
| EMIOSDIO0DATATN2 | output | TCELL94:OUT7.TMIN |
| EMIOSDIO0DATATN3 | output | TCELL94:OUT8.TMIN |
| EMIOSDIO0LED | output | TCELL92:OUT3.TMIN |
| EMIOSDIO0WP | input | TCELL94:IMUX.IMUX4 |
| EMIOSDIO1BUSPOW | output | TCELL96:OUT4.TMIN |
| EMIOSDIO1BUSVOLT0 | output | TCELL95:OUT4.TMIN |
| EMIOSDIO1BUSVOLT1 | output | TCELL97:OUT5.TMIN |
| EMIOSDIO1BUSVOLT2 | output | TCELL98:OUT9.TMIN |
| EMIOSDIO1CDN | input | TCELL98:IMUX.IMUX3 |
| EMIOSDIO1CLK | output | TCELL98:OUT4.TMIN |
| EMIOSDIO1CLKFB | input | TCELL96:IMUX.CLK0 |
| EMIOSDIO1CMDI | input | TCELL98:IMUX.IMUX2 |
| EMIOSDIO1CMDO | output | TCELL98:OUT5.TMIN |
| EMIOSDIO1CMDTN | output | TCELL98:OUT6.TMIN |
| EMIOSDIO1DATAI0 | input | TCELL97:IMUX.IMUX2 |
| EMIOSDIO1DATAI1 | input | TCELL97:IMUX.IMUX3 |
| EMIOSDIO1DATAI2 | input | TCELL97:IMUX.IMUX4 |
| EMIOSDIO1DATAI3 | input | TCELL97:IMUX.IMUX5 |
| EMIOSDIO1DATAO0 | output | TCELL95:OUT0.TMIN |
| EMIOSDIO1DATAO1 | output | TCELL95:OUT1.TMIN |
| EMIOSDIO1DATAO2 | output | TCELL95:OUT2.TMIN |
| EMIOSDIO1DATAO3 | output | TCELL95:OUT3.TMIN |
| EMIOSDIO1DATATN0 | output | TCELL97:OUT3.TMIN |
| EMIOSDIO1DATATN1 | output | TCELL97:OUT4.TMIN |
| EMIOSDIO1DATATN2 | output | TCELL98:OUT7.TMIN |
| EMIOSDIO1DATATN3 | output | TCELL98:OUT8.TMIN |
| EMIOSDIO1LED | output | TCELL96:OUT3.TMIN |
| EMIOSDIO1WP | input | TCELL98:IMUX.IMUX4 |
| EMIOSPI0MI | input | TCELL94:IMUX.IMUX1 |
| EMIOSPI0MO | output | TCELL94:OUT2.TMIN |
| EMIOSPI0MOTN | output | TCELL94:OUT3.TMIN |
| EMIOSPI0SCLKI | input | TCELL94:IMUX.IMUX0 |
| EMIOSPI0SCLKO | output | TCELL94:OUT0.TMIN |
| EMIOSPI0SCLKTN | output | TCELL94:OUT1.TMIN |
| EMIOSPI0SI | input | TCELL93:IMUX.IMUX0 |
| EMIOSPI0SO | output | TCELL93:OUT0.TMIN |
| EMIOSPI0SSIN | input | TCELL93:IMUX.IMUX1 |
| EMIOSPI0SSNTN | output | TCELL93:OUT2.TMIN |
| EMIOSPI0SSON0 | output | TCELL92:OUT0.TMIN |
| EMIOSPI0SSON1 | output | TCELL92:OUT1.TMIN |
| EMIOSPI0SSON2 | output | TCELL92:OUT2.TMIN |
| EMIOSPI0STN | output | TCELL93:OUT1.TMIN |
| EMIOSPI1MI | input | TCELL98:IMUX.IMUX1 |
| EMIOSPI1MO | output | TCELL98:OUT2.TMIN |
| EMIOSPI1MOTN | output | TCELL98:OUT3.TMIN |
| EMIOSPI1SCLKI | input | TCELL98:IMUX.IMUX0 |
| EMIOSPI1SCLKO | output | TCELL98:OUT0.TMIN |
| EMIOSPI1SCLKTN | output | TCELL98:OUT1.TMIN |
| EMIOSPI1SI | input | TCELL97:IMUX.IMUX0 |
| EMIOSPI1SO | output | TCELL97:OUT0.TMIN |
| EMIOSPI1SSIN | input | TCELL97:IMUX.IMUX1 |
| EMIOSPI1SSNTN | output | TCELL97:OUT2.TMIN |
| EMIOSPI1SSON0 | output | TCELL96:OUT0.TMIN |
| EMIOSPI1SSON1 | output | TCELL96:OUT1.TMIN |
| EMIOSPI1SSON2 | output | TCELL96:OUT2.TMIN |
| EMIOSPI1STN | output | TCELL97:OUT1.TMIN |
| EMIOSRAMINTIN | input | TCELL89:IMUX.IMUX12 |
| EMIOTRACECLK | input | TCELL89:IMUX.CLK0 |
| EMIOTRACECTL | output | TCELL90:OUT11.TMIN |
| EMIOTRACEDATA0 | output | TCELL89:OUT12.TMIN |
| EMIOTRACEDATA1 | output | TCELL89:OUT13.TMIN |
| EMIOTRACEDATA10 | output | TCELL91:OUT7.TMIN |
| EMIOTRACEDATA11 | output | TCELL91:OUT8.TMIN |
| EMIOTRACEDATA12 | output | TCELL92:OUT5.TMIN |
| EMIOTRACEDATA13 | output | TCELL92:OUT6.TMIN |
| EMIOTRACEDATA14 | output | TCELL92:OUT7.TMIN |
| EMIOTRACEDATA15 | output | TCELL92:OUT8.TMIN |
| EMIOTRACEDATA16 | output | TCELL93:OUT6.TMIN |
| EMIOTRACEDATA17 | output | TCELL93:OUT7.TMIN |
| EMIOTRACEDATA18 | output | TCELL93:OUT8.TMIN |
| EMIOTRACEDATA19 | output | TCELL93:OUT9.TMIN |
| EMIOTRACEDATA2 | output | TCELL89:OUT14.TMIN |
| EMIOTRACEDATA20 | output | TCELL94:OUT10.TMIN |
| EMIOTRACEDATA21 | output | TCELL94:OUT11.TMIN |
| EMIOTRACEDATA22 | output | TCELL95:OUT5.TMIN |
| EMIOTRACEDATA23 | output | TCELL95:OUT6.TMIN |
| EMIOTRACEDATA24 | output | TCELL95:OUT7.TMIN |
| EMIOTRACEDATA25 | output | TCELL95:OUT8.TMIN |
| EMIOTRACEDATA26 | output | TCELL96:OUT5.TMIN |
| EMIOTRACEDATA27 | output | TCELL96:OUT6.TMIN |
| EMIOTRACEDATA28 | output | TCELL96:OUT7.TMIN |
| EMIOTRACEDATA29 | output | TCELL96:OUT8.TMIN |
| EMIOTRACEDATA3 | output | TCELL89:OUT15.TMIN |
| EMIOTRACEDATA30 | output | TCELL97:OUT6.TMIN |
| EMIOTRACEDATA31 | output | TCELL97:OUT7.TMIN |
| EMIOTRACEDATA4 | output | TCELL90:OUT12.TMIN |
| EMIOTRACEDATA5 | output | TCELL90:OUT13.TMIN |
| EMIOTRACEDATA6 | output | TCELL90:OUT14.TMIN |
| EMIOTRACEDATA7 | output | TCELL90:OUT15.TMIN |
| EMIOTRACEDATA8 | output | TCELL91:OUT5.TMIN |
| EMIOTRACEDATA9 | output | TCELL91:OUT6.TMIN |
| EMIOTTC0CLKI0 | input | TCELL89:IMUX.IMUX0 |
| EMIOTTC0CLKI1 | input | TCELL89:IMUX.IMUX1 |
| EMIOTTC0CLKI2 | input | TCELL89:IMUX.IMUX2 |
| EMIOTTC0WAVEO0 | output | TCELL89:OUT0.TMIN |
| EMIOTTC0WAVEO1 | output | TCELL89:OUT1.TMIN |
| EMIOTTC0WAVEO2 | output | TCELL89:OUT2.TMIN |
| EMIOTTC1CLKI0 | input | TCELL90:IMUX.IMUX0 |
| EMIOTTC1CLKI1 | input | TCELL90:IMUX.IMUX1 |
| EMIOTTC1CLKI2 | input | TCELL90:IMUX.IMUX2 |
| EMIOTTC1WAVEO0 | output | TCELL90:OUT0.TMIN |
| EMIOTTC1WAVEO1 | output | TCELL90:OUT1.TMIN |
| EMIOTTC1WAVEO2 | output | TCELL90:OUT2.TMIN |
| EMIOUART0CTSN | input | TCELL90:IMUX.IMUX7 |
| EMIOUART0DCDN | input | TCELL90:IMUX.IMUX9 |
| EMIOUART0DSRN | input | TCELL90:IMUX.IMUX8 |
| EMIOUART0DTRN | output | TCELL90:OUT10.TMIN |
| EMIOUART0RIN | input | TCELL90:IMUX.IMUX10 |
| EMIOUART0RTSN | output | TCELL90:OUT9.TMIN |
| EMIOUART0RX | input | TCELL90:IMUX.IMUX6 |
| EMIOUART0TX | output | TCELL90:OUT8.TMIN |
| EMIOUART1CTSN | input | TCELL89:IMUX.IMUX8 |
| EMIOUART1DCDN | input | TCELL89:IMUX.IMUX10 |
| EMIOUART1DSRN | input | TCELL89:IMUX.IMUX9 |
| EMIOUART1DTRN | output | TCELL89:OUT11.TMIN |
| EMIOUART1RIN | input | TCELL89:IMUX.IMUX11 |
| EMIOUART1RTSN | output | TCELL89:OUT10.TMIN |
| EMIOUART1RX | input | TCELL89:IMUX.IMUX7 |
| EMIOUART1TX | output | TCELL89:OUT9.TMIN |
| EMIOUSB0PORTINDCTL0 | output | TCELL98:OUT10.TMIN |
| EMIOUSB0PORTINDCTL1 | output | TCELL98:OUT11.TMIN |
| EMIOUSB0VBUSPWRFAULT | input | TCELL98:IMUX.IMUX5 |
| EMIOUSB0VBUSPWRSELECT | output | TCELL98:OUT12.TMIN |
| EMIOUSB1PORTINDCTL0 | output | TCELL93:OUT10.TMIN |
| EMIOUSB1PORTINDCTL1 | output | TCELL95:OUT9.TMIN |
| EMIOUSB1VBUSPWRFAULT | input | TCELL94:IMUX.IMUX5 |
| EMIOUSB1VBUSPWRSELECT | output | TCELL94:OUT12.TMIN |
| EMIOWDTCLKI | input | TCELL89:IMUX.IMUX3 |
| EMIOWDTRSTO | output | TCELL89:OUT3.TMIN |
| EVENTEVENTI | input | TCELL64:IMUX.IMUX4 |
| EVENTEVENTO | output | TCELL64:OUT0.TMIN |
| EVENTSTANDBYWFE0 | output | TCELL64:OUT1.TMIN |
| EVENTSTANDBYWFE1 | output | TCELL64:OUT2.TMIN |
| EVENTSTANDBYWFI0 | output | TCELL63:OUT0.TMIN |
| EVENTSTANDBYWFI1 | output | TCELL63:OUT1.TMIN |
| FCLKCLK0_INT | output | TCELL39:OUT1.TMIN |
| FCLKCLK1_INT | output | TCELL39:OUT2.TMIN |
| FCLKCLK2_INT | output | TCELL61:OUT0.TMIN |
| FCLKCLK3_INT | output | TCELL61:OUT1.TMIN |
| FCLKCLKTRIGN0 | input | TCELL40:IMUX.IMUX3 |
| FCLKCLKTRIGN1 | input | TCELL40:IMUX.IMUX4 |
| FCLKCLKTRIGN2 | input | TCELL62:IMUX.IMUX4 |
| FCLKCLKTRIGN3 | input | TCELL62:IMUX.IMUX5 |
| FCLKRESETN0 | output | TCELL39:OUT3.TMIN |
| FCLKRESETN1 | output | TCELL39:OUT4.TMIN |
| FCLKRESETN2 | output | TCELL62:OUT0.TMIN |
| FCLKRESETN3 | output | TCELL62:OUT1.TMIN |
| FPGAIDLEN | input | TCELL64:IMUX.IMUX14 |
| FTMDTRACEINATID0 | input | TCELL60:IMUX.IMUX8 |
| FTMDTRACEINATID1 | input | TCELL60:IMUX.IMUX9 |
| FTMDTRACEINATID2 | input | TCELL60:IMUX.IMUX10 |
| FTMDTRACEINATID3 | input | TCELL60:IMUX.IMUX11 |
| FTMDTRACEINCLOCK | input | TCELL60:IMUX.CLK0 |
| FTMDTRACEINDATA0 | input | TCELL60:IMUX.IMUX4 |
| FTMDTRACEINDATA1 | input | TCELL60:IMUX.IMUX5 |
| FTMDTRACEINDATA10 | input | TCELL62:IMUX.IMUX8 |
| FTMDTRACEINDATA11 | input | TCELL62:IMUX.IMUX9 |
| FTMDTRACEINDATA12 | input | TCELL63:IMUX.IMUX4 |
| FTMDTRACEINDATA13 | input | TCELL63:IMUX.IMUX5 |
| FTMDTRACEINDATA14 | input | TCELL63:IMUX.IMUX6 |
| FTMDTRACEINDATA15 | input | TCELL63:IMUX.IMUX7 |
| FTMDTRACEINDATA16 | input | TCELL64:IMUX.IMUX5 |
| FTMDTRACEINDATA17 | input | TCELL64:IMUX.IMUX6 |
| FTMDTRACEINDATA18 | input | TCELL64:IMUX.IMUX7 |
| FTMDTRACEINDATA19 | input | TCELL64:IMUX.IMUX8 |
| FTMDTRACEINDATA2 | input | TCELL60:IMUX.IMUX6 |
| FTMDTRACEINDATA20 | input | TCELL65:IMUX.IMUX4 |
| FTMDTRACEINDATA21 | input | TCELL65:IMUX.IMUX5 |
| FTMDTRACEINDATA22 | input | TCELL65:IMUX.IMUX6 |
| FTMDTRACEINDATA23 | input | TCELL65:IMUX.IMUX7 |
| FTMDTRACEINDATA24 | input | TCELL69:IMUX.IMUX4 |
| FTMDTRACEINDATA25 | input | TCELL69:IMUX.IMUX5 |
| FTMDTRACEINDATA26 | input | TCELL69:IMUX.IMUX6 |
| FTMDTRACEINDATA27 | input | TCELL69:IMUX.IMUX7 |
| FTMDTRACEINDATA28 | input | TCELL70:IMUX.IMUX10 |
| FTMDTRACEINDATA29 | input | TCELL70:IMUX.IMUX11 |
| FTMDTRACEINDATA3 | input | TCELL60:IMUX.IMUX7 |
| FTMDTRACEINDATA30 | input | TCELL70:IMUX.IMUX12 |
| FTMDTRACEINDATA31 | input | TCELL70:IMUX.IMUX13 |
| FTMDTRACEINDATA4 | input | TCELL61:IMUX.IMUX4 |
| FTMDTRACEINDATA5 | input | TCELL61:IMUX.IMUX5 |
| FTMDTRACEINDATA6 | input | TCELL61:IMUX.IMUX6 |
| FTMDTRACEINDATA7 | input | TCELL61:IMUX.IMUX7 |
| FTMDTRACEINDATA8 | input | TCELL62:IMUX.IMUX6 |
| FTMDTRACEINDATA9 | input | TCELL62:IMUX.IMUX7 |
| FTMDTRACEINVALID | input | TCELL61:IMUX.IMUX8 |
| FTMTF2PDEBUG0 | input | TCELL60:IMUX.IMUX13 |
| FTMTF2PDEBUG1 | input | TCELL60:IMUX.IMUX14 |
| FTMTF2PDEBUG10 | input | TCELL62:IMUX.IMUX13 |
| FTMTF2PDEBUG11 | input | TCELL62:IMUX.IMUX14 |
| FTMTF2PDEBUG12 | input | TCELL63:IMUX.IMUX9 |
| FTMTF2PDEBUG13 | input | TCELL63:IMUX.IMUX10 |
| FTMTF2PDEBUG14 | input | TCELL63:IMUX.IMUX11 |
| FTMTF2PDEBUG15 | input | TCELL63:IMUX.IMUX12 |
| FTMTF2PDEBUG16 | input | TCELL64:IMUX.IMUX10 |
| FTMTF2PDEBUG17 | input | TCELL64:IMUX.IMUX11 |
| FTMTF2PDEBUG18 | input | TCELL64:IMUX.IMUX12 |
| FTMTF2PDEBUG19 | input | TCELL64:IMUX.IMUX13 |
| FTMTF2PDEBUG2 | input | TCELL60:IMUX.IMUX15 |
| FTMTF2PDEBUG20 | input | TCELL65:IMUX.IMUX9 |
| FTMTF2PDEBUG21 | input | TCELL65:IMUX.IMUX10 |
| FTMTF2PDEBUG22 | input | TCELL65:IMUX.IMUX11 |
| FTMTF2PDEBUG23 | input | TCELL65:IMUX.IMUX12 |
| FTMTF2PDEBUG24 | input | TCELL66:IMUX.IMUX7 |
| FTMTF2PDEBUG25 | input | TCELL66:IMUX.IMUX8 |
| FTMTF2PDEBUG26 | input | TCELL66:IMUX.IMUX9 |
| FTMTF2PDEBUG27 | input | TCELL66:IMUX.IMUX10 |
| FTMTF2PDEBUG28 | input | TCELL67:IMUX.IMUX9 |
| FTMTF2PDEBUG29 | input | TCELL67:IMUX.IMUX10 |
| FTMTF2PDEBUG3 | input | TCELL60:IMUX.IMUX16 |
| FTMTF2PDEBUG30 | input | TCELL67:IMUX.IMUX11 |
| FTMTF2PDEBUG31 | input | TCELL67:IMUX.IMUX12 |
| FTMTF2PDEBUG4 | input | TCELL61:IMUX.IMUX10 |
| FTMTF2PDEBUG5 | input | TCELL61:IMUX.IMUX11 |
| FTMTF2PDEBUG6 | input | TCELL61:IMUX.IMUX12 |
| FTMTF2PDEBUG7 | input | TCELL61:IMUX.IMUX13 |
| FTMTF2PDEBUG8 | input | TCELL62:IMUX.IMUX11 |
| FTMTF2PDEBUG9 | input | TCELL62:IMUX.IMUX12 |
| FTMTF2PTRIG0 | input | TCELL61:IMUX.IMUX9 |
| FTMTF2PTRIG1 | input | TCELL63:IMUX.IMUX8 |
| FTMTF2PTRIG2 | input | TCELL65:IMUX.IMUX8 |
| FTMTF2PTRIG3 | input | TCELL67:IMUX.IMUX8 |
| FTMTF2PTRIGACK0 | output | TCELL61:OUT2.TMIN |
| FTMTF2PTRIGACK1 | output | TCELL63:OUT2.TMIN |
| FTMTF2PTRIGACK2 | output | TCELL65:OUT7.TMIN |
| FTMTF2PTRIGACK3 | output | TCELL67:OUT10.TMIN |
| FTMTP2FDEBUG0 | output | TCELL60:OUT1.TMIN |
| FTMTP2FDEBUG1 | output | TCELL60:OUT2.TMIN |
| FTMTP2FDEBUG10 | output | TCELL62:OUT5.TMIN |
| FTMTP2FDEBUG11 | output | TCELL62:OUT6.TMIN |
| FTMTP2FDEBUG12 | output | TCELL63:OUT3.TMIN |
| FTMTP2FDEBUG13 | output | TCELL63:OUT4.TMIN |
| FTMTP2FDEBUG14 | output | TCELL63:OUT5.TMIN |
| FTMTP2FDEBUG15 | output | TCELL63:OUT6.TMIN |
| FTMTP2FDEBUG16 | output | TCELL64:OUT4.TMIN |
| FTMTP2FDEBUG17 | output | TCELL64:OUT5.TMIN |
| FTMTP2FDEBUG18 | output | TCELL64:OUT6.TMIN |
| FTMTP2FDEBUG19 | output | TCELL64:OUT7.TMIN |
| FTMTP2FDEBUG2 | output | TCELL60:OUT3.TMIN |
| FTMTP2FDEBUG20 | output | TCELL65:OUT8.TMIN |
| FTMTP2FDEBUG21 | output | TCELL65:OUT9.TMIN |
| FTMTP2FDEBUG22 | output | TCELL65:OUT10.TMIN |
| FTMTP2FDEBUG23 | output | TCELL65:OUT11.TMIN |
| FTMTP2FDEBUG24 | output | TCELL66:OUT11.TMIN |
| FTMTP2FDEBUG25 | output | TCELL66:OUT12.TMIN |
| FTMTP2FDEBUG26 | output | TCELL66:OUT13.TMIN |
| FTMTP2FDEBUG27 | output | TCELL66:OUT14.TMIN |
| FTMTP2FDEBUG28 | output | TCELL67:OUT11.TMIN |
| FTMTP2FDEBUG29 | output | TCELL67:OUT12.TMIN |
| FTMTP2FDEBUG3 | output | TCELL60:OUT4.TMIN |
| FTMTP2FDEBUG30 | output | TCELL67:OUT13.TMIN |
| FTMTP2FDEBUG31 | output | TCELL67:OUT14.TMIN |
| FTMTP2FDEBUG4 | output | TCELL61:OUT3.TMIN |
| FTMTP2FDEBUG5 | output | TCELL61:OUT4.TMIN |
| FTMTP2FDEBUG6 | output | TCELL61:OUT5.TMIN |
| FTMTP2FDEBUG7 | output | TCELL61:OUT6.TMIN |
| FTMTP2FDEBUG8 | output | TCELL62:OUT3.TMIN |
| FTMTP2FDEBUG9 | output | TCELL62:OUT4.TMIN |
| FTMTP2FTRIG0 | output | TCELL60:OUT0.TMIN |
| FTMTP2FTRIG1 | output | TCELL62:OUT2.TMIN |
| FTMTP2FTRIG2 | output | TCELL64:OUT3.TMIN |
| FTMTP2FTRIG3 | output | TCELL66:OUT10.TMIN |
| FTMTP2FTRIGACK0 | input | TCELL60:IMUX.IMUX12 |
| FTMTP2FTRIGACK1 | input | TCELL62:IMUX.IMUX10 |
| FTMTP2FTRIGACK2 | input | TCELL64:IMUX.IMUX9 |
| FTMTP2FTRIGACK3 | input | TCELL66:IMUX.IMUX6 |
| IRQF2P0 | input | TCELL45:IMUX.IMUX0 |
| IRQF2P1 | input | TCELL45:IMUX.IMUX1 |
| IRQF2P10 | input | TCELL50:IMUX.IMUX0 |
| IRQF2P11 | input | TCELL50:IMUX.IMUX1 |
| IRQF2P12 | input | TCELL51:IMUX.IMUX0 |
| IRQF2P13 | input | TCELL51:IMUX.IMUX1 |
| IRQF2P14 | input | TCELL52:IMUX.IMUX0 |
| IRQF2P15 | input | TCELL52:IMUX.IMUX1 |
| IRQF2P16 | input | TCELL53:IMUX.IMUX0 |
| IRQF2P17 | input | TCELL53:IMUX.IMUX1 |
| IRQF2P18 | input | TCELL54:IMUX.IMUX0 |
| IRQF2P19 | input | TCELL54:IMUX.IMUX1 |
| IRQF2P2 | input | TCELL46:IMUX.IMUX0 |
| IRQF2P3 | input | TCELL46:IMUX.IMUX1 |
| IRQF2P4 | input | TCELL47:IMUX.IMUX0 |
| IRQF2P5 | input | TCELL47:IMUX.IMUX1 |
| IRQF2P6 | input | TCELL48:IMUX.IMUX0 |
| IRQF2P7 | input | TCELL48:IMUX.IMUX1 |
| IRQF2P8 | input | TCELL49:IMUX.IMUX0 |
| IRQF2P9 | input | TCELL49:IMUX.IMUX1 |
| IRQP2F0 | output | TCELL65:OUT6.TMIN |
| IRQP2F1 | output | TCELL66:OUT6.TMIN |
| IRQP2F10 | output | TCELL68:OUT6.TMIN |
| IRQP2F11 | output | TCELL68:OUT7.TMIN |
| IRQP2F12 | output | TCELL68:OUT8.TMIN |
| IRQP2F13 | output | TCELL69:OUT6.TMIN |
| IRQP2F14 | output | TCELL69:OUT7.TMIN |
| IRQP2F15 | output | TCELL69:OUT8.TMIN |
| IRQP2F16 | output | TCELL69:OUT9.TMIN |
| IRQP2F17 | output | TCELL70:OUT6.TMIN |
| IRQP2F18 | output | TCELL70:OUT7.TMIN |
| IRQP2F19 | output | TCELL70:OUT8.TMIN |
| IRQP2F2 | output | TCELL66:OUT7.TMIN |
| IRQP2F20 | output | TCELL70:OUT9.TMIN |
| IRQP2F21 | output | TCELL71:OUT6.TMIN |
| IRQP2F22 | output | TCELL71:OUT7.TMIN |
| IRQP2F23 | output | TCELL71:OUT8.TMIN |
| IRQP2F24 | output | TCELL71:OUT9.TMIN |
| IRQP2F25 | output | TCELL72:OUT5.TMIN |
| IRQP2F26 | output | TCELL72:OUT6.TMIN |
| IRQP2F27 | output | TCELL72:OUT7.TMIN |
| IRQP2F28 | output | TCELL72:OUT8.TMIN |
| IRQP2F3 | output | TCELL66:OUT8.TMIN |
| IRQP2F4 | output | TCELL66:OUT9.TMIN |
| IRQP2F5 | output | TCELL67:OUT6.TMIN |
| IRQP2F6 | output | TCELL67:OUT7.TMIN |
| IRQP2F7 | output | TCELL67:OUT8.TMIN |
| IRQP2F8 | output | TCELL67:OUT9.TMIN |
| IRQP2F9 | output | TCELL68:OUT5.TMIN |
| MAXIGP0ACLK | input | TCELL45:IMUX.CLK0 |
| MAXIGP0ARADDR0 | output | TCELL40:OUT5.TMIN |
| MAXIGP0ARADDR1 | output | TCELL40:OUT6.TMIN |
| MAXIGP0ARADDR10 | output | TCELL42:OUT14.TMIN |
| MAXIGP0ARADDR11 | output | TCELL42:OUT15.TMIN |
| MAXIGP0ARADDR12 | output | TCELL43:OUT15.TMIN |
| MAXIGP0ARADDR13 | output | TCELL43:OUT16.TMIN |
| MAXIGP0ARADDR14 | output | TCELL43:OUT17.TMIN |
| MAXIGP0ARADDR15 | output | TCELL43:OUT18.TMIN |
| MAXIGP0ARADDR16 | output | TCELL44:OUT14.TMIN |
| MAXIGP0ARADDR17 | output | TCELL44:OUT15.TMIN |
| MAXIGP0ARADDR18 | output | TCELL44:OUT16.TMIN |
| MAXIGP0ARADDR19 | output | TCELL44:OUT17.TMIN |
| MAXIGP0ARADDR2 | output | TCELL40:OUT7.TMIN |
| MAXIGP0ARADDR20 | output | TCELL45:OUT14.TMIN |
| MAXIGP0ARADDR21 | output | TCELL45:OUT15.TMIN |
| MAXIGP0ARADDR22 | output | TCELL45:OUT16.TMIN |
| MAXIGP0ARADDR23 | output | TCELL45:OUT17.TMIN |
| MAXIGP0ARADDR24 | output | TCELL46:OUT11.TMIN |
| MAXIGP0ARADDR25 | output | TCELL46:OUT12.TMIN |
| MAXIGP0ARADDR26 | output | TCELL46:OUT13.TMIN |
| MAXIGP0ARADDR27 | output | TCELL46:OUT14.TMIN |
| MAXIGP0ARADDR28 | output | TCELL47:OUT17.TMIN |
| MAXIGP0ARADDR29 | output | TCELL47:OUT18.TMIN |
| MAXIGP0ARADDR3 | output | TCELL40:OUT8.TMIN |
| MAXIGP0ARADDR30 | output | TCELL48:OUT17.TMIN |
| MAXIGP0ARADDR31 | output | TCELL48:OUT18.TMIN |
| MAXIGP0ARADDR4 | output | TCELL41:OUT6.TMIN |
| MAXIGP0ARADDR5 | output | TCELL41:OUT7.TMIN |
| MAXIGP0ARADDR6 | output | TCELL41:OUT8.TMIN |
| MAXIGP0ARADDR7 | output | TCELL41:OUT9.TMIN |
| MAXIGP0ARADDR8 | output | TCELL42:OUT12.TMIN |
| MAXIGP0ARADDR9 | output | TCELL42:OUT13.TMIN |
| MAXIGP0ARBURST0 | output | TCELL40:OUT14.TMIN |
| MAXIGP0ARBURST1 | output | TCELL40:OUT15.TMIN |
| MAXIGP0ARCACHE0 | output | TCELL41:OUT11.TMIN |
| MAXIGP0ARCACHE1 | output | TCELL41:OUT12.TMIN |
| MAXIGP0ARCACHE2 | output | TCELL41:OUT13.TMIN |
| MAXIGP0ARCACHE3 | output | TCELL41:OUT14.TMIN |
| MAXIGP0ARESETN | output | TCELL44:OUT0.TMIN |
| MAXIGP0ARID0 | output | TCELL40:OUT1.TMIN |
| MAXIGP0ARID1 | output | TCELL40:OUT2.TMIN |
| MAXIGP0ARID10 | output | TCELL42:OUT11.TMIN |
| MAXIGP0ARID11 | output | TCELL43:OUT14.TMIN |
| MAXIGP0ARID2 | output | TCELL40:OUT3.TMIN |
| MAXIGP0ARID3 | output | TCELL40:OUT4.TMIN |
| MAXIGP0ARID4 | output | TCELL41:OUT3.TMIN |
| MAXIGP0ARID5 | output | TCELL41:OUT4.TMIN |
| MAXIGP0ARID6 | output | TCELL41:OUT5.TMIN |
| MAXIGP0ARID7 | output | TCELL42:OUT8.TMIN |
| MAXIGP0ARID8 | output | TCELL42:OUT9.TMIN |
| MAXIGP0ARID9 | output | TCELL42:OUT10.TMIN |
| MAXIGP0ARLEN0 | output | TCELL40:OUT9.TMIN |
| MAXIGP0ARLEN1 | output | TCELL40:OUT10.TMIN |
| MAXIGP0ARLEN2 | output | TCELL40:OUT11.TMIN |
| MAXIGP0ARLEN3 | output | TCELL41:OUT10.TMIN |
| MAXIGP0ARLOCK0 | output | TCELL40:OUT16.TMIN |
| MAXIGP0ARLOCK1 | output | TCELL40:OUT17.TMIN |
| MAXIGP0ARPROT0 | output | TCELL41:OUT15.TMIN |
| MAXIGP0ARPROT1 | output | TCELL42:OUT16.TMIN |
| MAXIGP0ARPROT2 | output | TCELL42:OUT17.TMIN |
| MAXIGP0ARQOS0 | output | TCELL40:OUT18.TMIN |
| MAXIGP0ARQOS1 | output | TCELL40:OUT19.TMIN |
| MAXIGP0ARQOS2 | output | TCELL41:OUT16.TMIN |
| MAXIGP0ARQOS3 | output | TCELL41:OUT17.TMIN |
| MAXIGP0ARREADY | input | TCELL45:IMUX.IMUX4 |
| MAXIGP0ARSIZE0 | output | TCELL40:OUT12.TMIN |
| MAXIGP0ARSIZE1 | output | TCELL40:OUT13.TMIN |
| MAXIGP0ARVALID | output | TCELL45:OUT18.TMIN |
| MAXIGP0AWADDR0 | output | TCELL41:OUT1.TMIN |
| MAXIGP0AWADDR1 | output | TCELL41:OUT2.TMIN |
| MAXIGP0AWADDR10 | output | TCELL44:OUT3.TMIN |
| MAXIGP0AWADDR11 | output | TCELL44:OUT4.TMIN |
| MAXIGP0AWADDR12 | output | TCELL45:OUT0.TMIN |
| MAXIGP0AWADDR13 | output | TCELL45:OUT1.TMIN |
| MAXIGP0AWADDR14 | output | TCELL45:OUT2.TMIN |
| MAXIGP0AWADDR15 | output | TCELL45:OUT3.TMIN |
| MAXIGP0AWADDR16 | output | TCELL46:OUT1.TMIN |
| MAXIGP0AWADDR17 | output | TCELL46:OUT2.TMIN |
| MAXIGP0AWADDR18 | output | TCELL46:OUT3.TMIN |
| MAXIGP0AWADDR19 | output | TCELL46:OUT4.TMIN |
| MAXIGP0AWADDR2 | output | TCELL42:OUT1.TMIN |
| MAXIGP0AWADDR20 | output | TCELL47:OUT4.TMIN |
| MAXIGP0AWADDR21 | output | TCELL47:OUT5.TMIN |
| MAXIGP0AWADDR22 | output | TCELL47:OUT6.TMIN |
| MAXIGP0AWADDR23 | output | TCELL47:OUT7.TMIN |
| MAXIGP0AWADDR24 | output | TCELL48:OUT3.TMIN |
| MAXIGP0AWADDR25 | output | TCELL48:OUT4.TMIN |
| MAXIGP0AWADDR26 | output | TCELL48:OUT5.TMIN |
| MAXIGP0AWADDR27 | output | TCELL48:OUT6.TMIN |
| MAXIGP0AWADDR28 | output | TCELL49:OUT4.TMIN |
| MAXIGP0AWADDR29 | output | TCELL49:OUT5.TMIN |
| MAXIGP0AWADDR3 | output | TCELL42:OUT2.TMIN |
| MAXIGP0AWADDR30 | output | TCELL49:OUT6.TMIN |
| MAXIGP0AWADDR31 | output | TCELL49:OUT7.TMIN |
| MAXIGP0AWADDR4 | output | TCELL43:OUT1.TMIN |
| MAXIGP0AWADDR5 | output | TCELL43:OUT2.TMIN |
| MAXIGP0AWADDR6 | output | TCELL43:OUT3.TMIN |
| MAXIGP0AWADDR7 | output | TCELL43:OUT4.TMIN |
| MAXIGP0AWADDR8 | output | TCELL44:OUT1.TMIN |
| MAXIGP0AWADDR9 | output | TCELL44:OUT2.TMIN |
| MAXIGP0AWBURST0 | output | TCELL49:OUT10.TMIN |
| MAXIGP0AWBURST1 | output | TCELL49:OUT11.TMIN |
| MAXIGP0AWCACHE0 | output | TCELL43:OUT8.TMIN |
| MAXIGP0AWCACHE1 | output | TCELL43:OUT9.TMIN |
| MAXIGP0AWCACHE2 | output | TCELL44:OUT5.TMIN |
| MAXIGP0AWCACHE3 | output | TCELL44:OUT6.TMIN |
| MAXIGP0AWID0 | output | TCELL46:OUT0.TMIN |
| MAXIGP0AWID1 | output | TCELL47:OUT0.TMIN |
| MAXIGP0AWID10 | output | TCELL49:OUT2.TMIN |
| MAXIGP0AWID11 | output | TCELL49:OUT3.TMIN |
| MAXIGP0AWID2 | output | TCELL47:OUT1.TMIN |
| MAXIGP0AWID3 | output | TCELL47:OUT2.TMIN |
| MAXIGP0AWID4 | output | TCELL47:OUT3.TMIN |
| MAXIGP0AWID5 | output | TCELL48:OUT0.TMIN |
| MAXIGP0AWID6 | output | TCELL48:OUT1.TMIN |
| MAXIGP0AWID7 | output | TCELL48:OUT2.TMIN |
| MAXIGP0AWID8 | output | TCELL49:OUT0.TMIN |
| MAXIGP0AWID9 | output | TCELL49:OUT1.TMIN |
| MAXIGP0AWLEN0 | output | TCELL42:OUT3.TMIN |
| MAXIGP0AWLEN1 | output | TCELL43:OUT5.TMIN |
| MAXIGP0AWLEN2 | output | TCELL43:OUT6.TMIN |
| MAXIGP0AWLEN3 | output | TCELL43:OUT7.TMIN |
| MAXIGP0AWLOCK0 | output | TCELL49:OUT12.TMIN |
| MAXIGP0AWLOCK1 | output | TCELL49:OUT13.TMIN |
| MAXIGP0AWPROT0 | output | TCELL44:OUT7.TMIN |
| MAXIGP0AWPROT1 | output | TCELL44:OUT8.TMIN |
| MAXIGP0AWPROT2 | output | TCELL45:OUT4.TMIN |
| MAXIGP0AWQOS0 | output | TCELL46:OUT15.TMIN |
| MAXIGP0AWQOS1 | output | TCELL46:OUT16.TMIN |
| MAXIGP0AWQOS2 | output | TCELL46:OUT17.TMIN |
| MAXIGP0AWQOS3 | output | TCELL46:OUT18.TMIN |
| MAXIGP0AWREADY | input | TCELL45:IMUX.IMUX2 |
| MAXIGP0AWSIZE0 | output | TCELL49:OUT8.TMIN |
| MAXIGP0AWSIZE1 | output | TCELL49:OUT9.TMIN |
| MAXIGP0AWVALID | output | TCELL45:OUT5.TMIN |
| MAXIGP0BID0 | input | TCELL47:IMUX.IMUX2 |
| MAXIGP0BID1 | input | TCELL47:IMUX.IMUX3 |
| MAXIGP0BID10 | input | TCELL49:IMUX.IMUX4 |
| MAXIGP0BID11 | input | TCELL49:IMUX.IMUX5 |
| MAXIGP0BID2 | input | TCELL47:IMUX.IMUX4 |
| MAXIGP0BID3 | input | TCELL47:IMUX.IMUX5 |
| MAXIGP0BID4 | input | TCELL48:IMUX.IMUX2 |
| MAXIGP0BID5 | input | TCELL48:IMUX.IMUX3 |
| MAXIGP0BID6 | input | TCELL48:IMUX.IMUX4 |
| MAXIGP0BID7 | input | TCELL48:IMUX.IMUX5 |
| MAXIGP0BID8 | input | TCELL49:IMUX.IMUX2 |
| MAXIGP0BID9 | input | TCELL49:IMUX.IMUX3 |
| MAXIGP0BREADY | output | TCELL45:OUT13.TMIN |
| MAXIGP0BRESP0 | input | TCELL48:IMUX.IMUX6 |
| MAXIGP0BRESP1 | input | TCELL49:IMUX.IMUX6 |
| MAXIGP0BVALID | input | TCELL46:IMUX.IMUX2 |
| MAXIGP0RDATA0 | input | TCELL40:IMUX.IMUX5 |
| MAXIGP0RDATA1 | input | TCELL40:IMUX.IMUX6 |
| MAXIGP0RDATA10 | input | TCELL42:IMUX.IMUX5 |
| MAXIGP0RDATA11 | input | TCELL42:IMUX.IMUX6 |
| MAXIGP0RDATA12 | input | TCELL43:IMUX.IMUX3 |
| MAXIGP0RDATA13 | input | TCELL43:IMUX.IMUX4 |
| MAXIGP0RDATA14 | input | TCELL43:IMUX.IMUX5 |
| MAXIGP0RDATA15 | input | TCELL43:IMUX.IMUX6 |
| MAXIGP0RDATA16 | input | TCELL44:IMUX.IMUX2 |
| MAXIGP0RDATA17 | input | TCELL44:IMUX.IMUX3 |
| MAXIGP0RDATA18 | input | TCELL44:IMUX.IMUX4 |
| MAXIGP0RDATA19 | input | TCELL44:IMUX.IMUX5 |
| MAXIGP0RDATA2 | input | TCELL40:IMUX.IMUX7 |
| MAXIGP0RDATA20 | input | TCELL45:IMUX.IMUX5 |
| MAXIGP0RDATA21 | input | TCELL45:IMUX.IMUX6 |
| MAXIGP0RDATA22 | input | TCELL45:IMUX.IMUX7 |
| MAXIGP0RDATA23 | input | TCELL45:IMUX.IMUX8 |
| MAXIGP0RDATA24 | input | TCELL46:IMUX.IMUX5 |
| MAXIGP0RDATA25 | input | TCELL46:IMUX.IMUX6 |
| MAXIGP0RDATA26 | input | TCELL46:IMUX.IMUX7 |
| MAXIGP0RDATA27 | input | TCELL46:IMUX.IMUX8 |
| MAXIGP0RDATA28 | input | TCELL47:IMUX.IMUX8 |
| MAXIGP0RDATA29 | input | TCELL47:IMUX.IMUX9 |
| MAXIGP0RDATA3 | input | TCELL40:IMUX.IMUX8 |
| MAXIGP0RDATA30 | input | TCELL47:IMUX.IMUX10 |
| MAXIGP0RDATA31 | input | TCELL47:IMUX.IMUX11 |
| MAXIGP0RDATA4 | input | TCELL41:IMUX.IMUX3 |
| MAXIGP0RDATA5 | input | TCELL41:IMUX.IMUX4 |
| MAXIGP0RDATA6 | input | TCELL41:IMUX.IMUX5 |
| MAXIGP0RDATA7 | input | TCELL41:IMUX.IMUX6 |
| MAXIGP0RDATA8 | input | TCELL42:IMUX.IMUX3 |
| MAXIGP0RDATA9 | input | TCELL42:IMUX.IMUX4 |
| MAXIGP0RID0 | input | TCELL44:IMUX.IMUX0 |
| MAXIGP0RID1 | input | TCELL44:IMUX.IMUX1 |
| MAXIGP0RID10 | input | TCELL49:IMUX.IMUX7 |
| MAXIGP0RID11 | input | TCELL49:IMUX.IMUX8 |
| MAXIGP0RID2 | input | TCELL46:IMUX.IMUX3 |
| MAXIGP0RID3 | input | TCELL46:IMUX.IMUX4 |
| MAXIGP0RID4 | input | TCELL47:IMUX.IMUX6 |
| MAXIGP0RID5 | input | TCELL47:IMUX.IMUX7 |
| MAXIGP0RID6 | input | TCELL48:IMUX.IMUX7 |
| MAXIGP0RID7 | input | TCELL48:IMUX.IMUX8 |
| MAXIGP0RID8 | input | TCELL48:IMUX.IMUX9 |
| MAXIGP0RID9 | input | TCELL48:IMUX.IMUX10 |
| MAXIGP0RLAST | input | TCELL43:IMUX.IMUX7 |
| MAXIGP0RREADY | output | TCELL44:OUT18.TMIN |
| MAXIGP0RRESP0 | input | TCELL44:IMUX.IMUX6 |
| MAXIGP0RRESP1 | input | TCELL44:IMUX.IMUX7 |
| MAXIGP0RVALID | input | TCELL44:IMUX.IMUX8 |
| MAXIGP0WDATA0 | output | TCELL42:OUT4.TMIN |
| MAXIGP0WDATA1 | output | TCELL42:OUT5.TMIN |
| MAXIGP0WDATA10 | output | TCELL44:OUT12.TMIN |
| MAXIGP0WDATA11 | output | TCELL44:OUT13.TMIN |
| MAXIGP0WDATA12 | output | TCELL45:OUT8.TMIN |
| MAXIGP0WDATA13 | output | TCELL45:OUT9.TMIN |
| MAXIGP0WDATA14 | output | TCELL45:OUT10.TMIN |
| MAXIGP0WDATA15 | output | TCELL45:OUT11.TMIN |
| MAXIGP0WDATA16 | output | TCELL46:OUT7.TMIN |
| MAXIGP0WDATA17 | output | TCELL46:OUT8.TMIN |
| MAXIGP0WDATA18 | output | TCELL46:OUT9.TMIN |
| MAXIGP0WDATA19 | output | TCELL46:OUT10.TMIN |
| MAXIGP0WDATA2 | output | TCELL42:OUT6.TMIN |
| MAXIGP0WDATA20 | output | TCELL47:OUT11.TMIN |
| MAXIGP0WDATA21 | output | TCELL47:OUT12.TMIN |
| MAXIGP0WDATA22 | output | TCELL47:OUT13.TMIN |
| MAXIGP0WDATA23 | output | TCELL47:OUT14.TMIN |
| MAXIGP0WDATA24 | output | TCELL48:OUT11.TMIN |
| MAXIGP0WDATA25 | output | TCELL48:OUT12.TMIN |
| MAXIGP0WDATA26 | output | TCELL48:OUT13.TMIN |
| MAXIGP0WDATA27 | output | TCELL48:OUT14.TMIN |
| MAXIGP0WDATA28 | output | TCELL49:OUT14.TMIN |
| MAXIGP0WDATA29 | output | TCELL49:OUT15.TMIN |
| MAXIGP0WDATA3 | output | TCELL42:OUT7.TMIN |
| MAXIGP0WDATA30 | output | TCELL49:OUT16.TMIN |
| MAXIGP0WDATA31 | output | TCELL49:OUT17.TMIN |
| MAXIGP0WDATA4 | output | TCELL43:OUT10.TMIN |
| MAXIGP0WDATA5 | output | TCELL43:OUT11.TMIN |
| MAXIGP0WDATA6 | output | TCELL43:OUT12.TMIN |
| MAXIGP0WDATA7 | output | TCELL43:OUT13.TMIN |
| MAXIGP0WDATA8 | output | TCELL44:OUT10.TMIN |
| MAXIGP0WDATA9 | output | TCELL44:OUT11.TMIN |
| MAXIGP0WID0 | output | TCELL44:OUT9.TMIN |
| MAXIGP0WID1 | output | TCELL45:OUT6.TMIN |
| MAXIGP0WID10 | output | TCELL48:OUT9.TMIN |
| MAXIGP0WID11 | output | TCELL48:OUT10.TMIN |
| MAXIGP0WID2 | output | TCELL45:OUT7.TMIN |
| MAXIGP0WID3 | output | TCELL46:OUT5.TMIN |
| MAXIGP0WID4 | output | TCELL46:OUT6.TMIN |
| MAXIGP0WID5 | output | TCELL47:OUT8.TMIN |
| MAXIGP0WID6 | output | TCELL47:OUT9.TMIN |
| MAXIGP0WID7 | output | TCELL47:OUT10.TMIN |
| MAXIGP0WID8 | output | TCELL48:OUT7.TMIN |
| MAXIGP0WID9 | output | TCELL48:OUT8.TMIN |
| MAXIGP0WLAST | output | TCELL49:OUT18.TMIN |
| MAXIGP0WREADY | input | TCELL45:IMUX.IMUX3 |
| MAXIGP0WSTRB0 | output | TCELL47:OUT15.TMIN |
| MAXIGP0WSTRB1 | output | TCELL47:OUT16.TMIN |
| MAXIGP0WSTRB2 | output | TCELL48:OUT15.TMIN |
| MAXIGP0WSTRB3 | output | TCELL48:OUT16.TMIN |
| MAXIGP0WVALID | output | TCELL45:OUT12.TMIN |
| MAXIGP1ACLK | input | TCELL55:IMUX.CLK0 |
| MAXIGP1ARADDR0 | output | TCELL50:OUT4.TMIN |
| MAXIGP1ARADDR1 | output | TCELL50:OUT5.TMIN |
| MAXIGP1ARADDR10 | output | TCELL52:OUT13.TMIN |
| MAXIGP1ARADDR11 | output | TCELL52:OUT14.TMIN |
| MAXIGP1ARADDR12 | output | TCELL53:OUT14.TMIN |
| MAXIGP1ARADDR13 | output | TCELL53:OUT15.TMIN |
| MAXIGP1ARADDR14 | output | TCELL53:OUT16.TMIN |
| MAXIGP1ARADDR15 | output | TCELL53:OUT17.TMIN |
| MAXIGP1ARADDR16 | output | TCELL54:OUT14.TMIN |
| MAXIGP1ARADDR17 | output | TCELL54:OUT15.TMIN |
| MAXIGP1ARADDR18 | output | TCELL54:OUT16.TMIN |
| MAXIGP1ARADDR19 | output | TCELL54:OUT17.TMIN |
| MAXIGP1ARADDR2 | output | TCELL50:OUT6.TMIN |
| MAXIGP1ARADDR20 | output | TCELL55:OUT14.TMIN |
| MAXIGP1ARADDR21 | output | TCELL55:OUT15.TMIN |
| MAXIGP1ARADDR22 | output | TCELL55:OUT16.TMIN |
| MAXIGP1ARADDR23 | output | TCELL55:OUT17.TMIN |
| MAXIGP1ARADDR24 | output | TCELL56:OUT11.TMIN |
| MAXIGP1ARADDR25 | output | TCELL56:OUT12.TMIN |
| MAXIGP1ARADDR26 | output | TCELL56:OUT13.TMIN |
| MAXIGP1ARADDR27 | output | TCELL56:OUT14.TMIN |
| MAXIGP1ARADDR28 | output | TCELL57:OUT17.TMIN |
| MAXIGP1ARADDR29 | output | TCELL57:OUT18.TMIN |
| MAXIGP1ARADDR3 | output | TCELL50:OUT7.TMIN |
| MAXIGP1ARADDR30 | output | TCELL58:OUT17.TMIN |
| MAXIGP1ARADDR31 | output | TCELL58:OUT18.TMIN |
| MAXIGP1ARADDR4 | output | TCELL51:OUT5.TMIN |
| MAXIGP1ARADDR5 | output | TCELL51:OUT6.TMIN |
| MAXIGP1ARADDR6 | output | TCELL51:OUT7.TMIN |
| MAXIGP1ARADDR7 | output | TCELL51:OUT8.TMIN |
| MAXIGP1ARADDR8 | output | TCELL52:OUT11.TMIN |
| MAXIGP1ARADDR9 | output | TCELL52:OUT12.TMIN |
| MAXIGP1ARBURST0 | output | TCELL50:OUT13.TMIN |
| MAXIGP1ARBURST1 | output | TCELL50:OUT14.TMIN |
| MAXIGP1ARCACHE0 | output | TCELL51:OUT10.TMIN |
| MAXIGP1ARCACHE1 | output | TCELL51:OUT11.TMIN |
| MAXIGP1ARCACHE2 | output | TCELL51:OUT12.TMIN |
| MAXIGP1ARCACHE3 | output | TCELL51:OUT13.TMIN |
| MAXIGP1ARESETN | output | TCELL54:OUT0.TMIN |
| MAXIGP1ARID0 | output | TCELL50:OUT0.TMIN |
| MAXIGP1ARID1 | output | TCELL50:OUT1.TMIN |
| MAXIGP1ARID10 | output | TCELL52:OUT10.TMIN |
| MAXIGP1ARID11 | output | TCELL53:OUT13.TMIN |
| MAXIGP1ARID2 | output | TCELL50:OUT2.TMIN |
| MAXIGP1ARID3 | output | TCELL50:OUT3.TMIN |
| MAXIGP1ARID4 | output | TCELL51:OUT2.TMIN |
| MAXIGP1ARID5 | output | TCELL51:OUT3.TMIN |
| MAXIGP1ARID6 | output | TCELL51:OUT4.TMIN |
| MAXIGP1ARID7 | output | TCELL52:OUT7.TMIN |
| MAXIGP1ARID8 | output | TCELL52:OUT8.TMIN |
| MAXIGP1ARID9 | output | TCELL52:OUT9.TMIN |
| MAXIGP1ARLEN0 | output | TCELL50:OUT8.TMIN |
| MAXIGP1ARLEN1 | output | TCELL50:OUT9.TMIN |
| MAXIGP1ARLEN2 | output | TCELL50:OUT10.TMIN |
| MAXIGP1ARLEN3 | output | TCELL51:OUT9.TMIN |
| MAXIGP1ARLOCK0 | output | TCELL50:OUT15.TMIN |
| MAXIGP1ARLOCK1 | output | TCELL50:OUT16.TMIN |
| MAXIGP1ARPROT0 | output | TCELL51:OUT14.TMIN |
| MAXIGP1ARPROT1 | output | TCELL52:OUT15.TMIN |
| MAXIGP1ARPROT2 | output | TCELL52:OUT16.TMIN |
| MAXIGP1ARQOS0 | output | TCELL50:OUT17.TMIN |
| MAXIGP1ARQOS1 | output | TCELL50:OUT18.TMIN |
| MAXIGP1ARQOS2 | output | TCELL51:OUT15.TMIN |
| MAXIGP1ARQOS3 | output | TCELL51:OUT16.TMIN |
| MAXIGP1ARREADY | input | TCELL55:IMUX.IMUX2 |
| MAXIGP1ARSIZE0 | output | TCELL50:OUT11.TMIN |
| MAXIGP1ARSIZE1 | output | TCELL50:OUT12.TMIN |
| MAXIGP1ARVALID | output | TCELL55:OUT18.TMIN |
| MAXIGP1AWADDR0 | output | TCELL51:OUT0.TMIN |
| MAXIGP1AWADDR1 | output | TCELL51:OUT1.TMIN |
| MAXIGP1AWADDR10 | output | TCELL54:OUT3.TMIN |
| MAXIGP1AWADDR11 | output | TCELL54:OUT4.TMIN |
| MAXIGP1AWADDR12 | output | TCELL55:OUT0.TMIN |
| MAXIGP1AWADDR13 | output | TCELL55:OUT1.TMIN |
| MAXIGP1AWADDR14 | output | TCELL55:OUT2.TMIN |
| MAXIGP1AWADDR15 | output | TCELL55:OUT3.TMIN |
| MAXIGP1AWADDR16 | output | TCELL56:OUT1.TMIN |
| MAXIGP1AWADDR17 | output | TCELL56:OUT2.TMIN |
| MAXIGP1AWADDR18 | output | TCELL56:OUT3.TMIN |
| MAXIGP1AWADDR19 | output | TCELL56:OUT4.TMIN |
| MAXIGP1AWADDR2 | output | TCELL52:OUT0.TMIN |
| MAXIGP1AWADDR20 | output | TCELL57:OUT4.TMIN |
| MAXIGP1AWADDR21 | output | TCELL57:OUT5.TMIN |
| MAXIGP1AWADDR22 | output | TCELL57:OUT6.TMIN |
| MAXIGP1AWADDR23 | output | TCELL57:OUT7.TMIN |
| MAXIGP1AWADDR24 | output | TCELL58:OUT3.TMIN |
| MAXIGP1AWADDR25 | output | TCELL58:OUT4.TMIN |
| MAXIGP1AWADDR26 | output | TCELL58:OUT5.TMIN |
| MAXIGP1AWADDR27 | output | TCELL58:OUT6.TMIN |
| MAXIGP1AWADDR28 | output | TCELL59:OUT4.TMIN |
| MAXIGP1AWADDR29 | output | TCELL59:OUT5.TMIN |
| MAXIGP1AWADDR3 | output | TCELL52:OUT1.TMIN |
| MAXIGP1AWADDR30 | output | TCELL59:OUT6.TMIN |
| MAXIGP1AWADDR31 | output | TCELL59:OUT7.TMIN |
| MAXIGP1AWADDR4 | output | TCELL53:OUT0.TMIN |
| MAXIGP1AWADDR5 | output | TCELL53:OUT1.TMIN |
| MAXIGP1AWADDR6 | output | TCELL53:OUT2.TMIN |
| MAXIGP1AWADDR7 | output | TCELL53:OUT3.TMIN |
| MAXIGP1AWADDR8 | output | TCELL54:OUT1.TMIN |
| MAXIGP1AWADDR9 | output | TCELL54:OUT2.TMIN |
| MAXIGP1AWBURST0 | output | TCELL59:OUT10.TMIN |
| MAXIGP1AWBURST1 | output | TCELL59:OUT11.TMIN |
| MAXIGP1AWCACHE0 | output | TCELL53:OUT7.TMIN |
| MAXIGP1AWCACHE1 | output | TCELL53:OUT8.TMIN |
| MAXIGP1AWCACHE2 | output | TCELL54:OUT5.TMIN |
| MAXIGP1AWCACHE3 | output | TCELL54:OUT6.TMIN |
| MAXIGP1AWID0 | output | TCELL56:OUT0.TMIN |
| MAXIGP1AWID1 | output | TCELL57:OUT0.TMIN |
| MAXIGP1AWID10 | output | TCELL59:OUT2.TMIN |
| MAXIGP1AWID11 | output | TCELL59:OUT3.TMIN |
| MAXIGP1AWID2 | output | TCELL57:OUT1.TMIN |
| MAXIGP1AWID3 | output | TCELL57:OUT2.TMIN |
| MAXIGP1AWID4 | output | TCELL57:OUT3.TMIN |
| MAXIGP1AWID5 | output | TCELL58:OUT0.TMIN |
| MAXIGP1AWID6 | output | TCELL58:OUT1.TMIN |
| MAXIGP1AWID7 | output | TCELL58:OUT2.TMIN |
| MAXIGP1AWID8 | output | TCELL59:OUT0.TMIN |
| MAXIGP1AWID9 | output | TCELL59:OUT1.TMIN |
| MAXIGP1AWLEN0 | output | TCELL52:OUT2.TMIN |
| MAXIGP1AWLEN1 | output | TCELL53:OUT4.TMIN |
| MAXIGP1AWLEN2 | output | TCELL53:OUT5.TMIN |
| MAXIGP1AWLEN3 | output | TCELL53:OUT6.TMIN |
| MAXIGP1AWLOCK0 | output | TCELL59:OUT12.TMIN |
| MAXIGP1AWLOCK1 | output | TCELL59:OUT13.TMIN |
| MAXIGP1AWPROT0 | output | TCELL54:OUT7.TMIN |
| MAXIGP1AWPROT1 | output | TCELL54:OUT8.TMIN |
| MAXIGP1AWPROT2 | output | TCELL55:OUT4.TMIN |
| MAXIGP1AWQOS0 | output | TCELL56:OUT15.TMIN |
| MAXIGP1AWQOS1 | output | TCELL56:OUT16.TMIN |
| MAXIGP1AWQOS2 | output | TCELL56:OUT17.TMIN |
| MAXIGP1AWQOS3 | output | TCELL56:OUT18.TMIN |
| MAXIGP1AWREADY | input | TCELL55:IMUX.IMUX0 |
| MAXIGP1AWSIZE0 | output | TCELL59:OUT8.TMIN |
| MAXIGP1AWSIZE1 | output | TCELL59:OUT9.TMIN |
| MAXIGP1AWVALID | output | TCELL55:OUT5.TMIN |
| MAXIGP1BID0 | input | TCELL57:IMUX.IMUX0 |
| MAXIGP1BID1 | input | TCELL57:IMUX.IMUX1 |
| MAXIGP1BID10 | input | TCELL59:IMUX.IMUX2 |
| MAXIGP1BID11 | input | TCELL59:IMUX.IMUX3 |
| MAXIGP1BID2 | input | TCELL57:IMUX.IMUX2 |
| MAXIGP1BID3 | input | TCELL57:IMUX.IMUX3 |
| MAXIGP1BID4 | input | TCELL58:IMUX.IMUX0 |
| MAXIGP1BID5 | input | TCELL58:IMUX.IMUX1 |
| MAXIGP1BID6 | input | TCELL58:IMUX.IMUX2 |
| MAXIGP1BID7 | input | TCELL58:IMUX.IMUX3 |
| MAXIGP1BID8 | input | TCELL59:IMUX.IMUX0 |
| MAXIGP1BID9 | input | TCELL59:IMUX.IMUX1 |
| MAXIGP1BREADY | output | TCELL55:OUT13.TMIN |
| MAXIGP1BRESP0 | input | TCELL58:IMUX.IMUX4 |
| MAXIGP1BRESP1 | input | TCELL59:IMUX.IMUX4 |
| MAXIGP1BVALID | input | TCELL56:IMUX.IMUX0 |
| MAXIGP1RDATA0 | input | TCELL50:IMUX.IMUX6 |
| MAXIGP1RDATA1 | input | TCELL50:IMUX.IMUX7 |
| MAXIGP1RDATA10 | input | TCELL52:IMUX.IMUX4 |
| MAXIGP1RDATA11 | input | TCELL52:IMUX.IMUX5 |
| MAXIGP1RDATA12 | input | TCELL53:IMUX.IMUX2 |
| MAXIGP1RDATA13 | input | TCELL53:IMUX.IMUX3 |
| MAXIGP1RDATA14 | input | TCELL53:IMUX.IMUX4 |
| MAXIGP1RDATA15 | input | TCELL53:IMUX.IMUX5 |
| MAXIGP1RDATA16 | input | TCELL54:IMUX.IMUX4 |
| MAXIGP1RDATA17 | input | TCELL54:IMUX.IMUX5 |
| MAXIGP1RDATA18 | input | TCELL54:IMUX.IMUX6 |
| MAXIGP1RDATA19 | input | TCELL54:IMUX.IMUX7 |
| MAXIGP1RDATA2 | input | TCELL50:IMUX.IMUX8 |
| MAXIGP1RDATA20 | input | TCELL55:IMUX.IMUX3 |
| MAXIGP1RDATA21 | input | TCELL55:IMUX.IMUX4 |
| MAXIGP1RDATA22 | input | TCELL55:IMUX.IMUX5 |
| MAXIGP1RDATA23 | input | TCELL55:IMUX.IMUX6 |
| MAXIGP1RDATA24 | input | TCELL56:IMUX.IMUX3 |
| MAXIGP1RDATA25 | input | TCELL56:IMUX.IMUX4 |
| MAXIGP1RDATA26 | input | TCELL56:IMUX.IMUX5 |
| MAXIGP1RDATA27 | input | TCELL56:IMUX.IMUX6 |
| MAXIGP1RDATA28 | input | TCELL57:IMUX.IMUX6 |
| MAXIGP1RDATA29 | input | TCELL57:IMUX.IMUX7 |
| MAXIGP1RDATA3 | input | TCELL50:IMUX.IMUX9 |
| MAXIGP1RDATA30 | input | TCELL57:IMUX.IMUX8 |
| MAXIGP1RDATA31 | input | TCELL57:IMUX.IMUX9 |
| MAXIGP1RDATA4 | input | TCELL51:IMUX.IMUX2 |
| MAXIGP1RDATA5 | input | TCELL51:IMUX.IMUX3 |
| MAXIGP1RDATA6 | input | TCELL51:IMUX.IMUX4 |
| MAXIGP1RDATA7 | input | TCELL51:IMUX.IMUX5 |
| MAXIGP1RDATA8 | input | TCELL52:IMUX.IMUX2 |
| MAXIGP1RDATA9 | input | TCELL52:IMUX.IMUX3 |
| MAXIGP1RID0 | input | TCELL54:IMUX.IMUX2 |
| MAXIGP1RID1 | input | TCELL54:IMUX.IMUX3 |
| MAXIGP1RID10 | input | TCELL59:IMUX.IMUX5 |
| MAXIGP1RID11 | input | TCELL59:IMUX.IMUX6 |
| MAXIGP1RID2 | input | TCELL56:IMUX.IMUX1 |
| MAXIGP1RID3 | input | TCELL56:IMUX.IMUX2 |
| MAXIGP1RID4 | input | TCELL57:IMUX.IMUX4 |
| MAXIGP1RID5 | input | TCELL57:IMUX.IMUX5 |
| MAXIGP1RID6 | input | TCELL58:IMUX.IMUX5 |
| MAXIGP1RID7 | input | TCELL58:IMUX.IMUX6 |
| MAXIGP1RID8 | input | TCELL58:IMUX.IMUX7 |
| MAXIGP1RID9 | input | TCELL58:IMUX.IMUX8 |
| MAXIGP1RLAST | input | TCELL53:IMUX.IMUX6 |
| MAXIGP1RREADY | output | TCELL54:OUT18.TMIN |
| MAXIGP1RRESP0 | input | TCELL54:IMUX.IMUX8 |
| MAXIGP1RRESP1 | input | TCELL54:IMUX.IMUX9 |
| MAXIGP1RVALID | input | TCELL54:IMUX.IMUX10 |
| MAXIGP1WDATA0 | output | TCELL52:OUT3.TMIN |
| MAXIGP1WDATA1 | output | TCELL52:OUT4.TMIN |
| MAXIGP1WDATA10 | output | TCELL54:OUT12.TMIN |
| MAXIGP1WDATA11 | output | TCELL54:OUT13.TMIN |
| MAXIGP1WDATA12 | output | TCELL55:OUT8.TMIN |
| MAXIGP1WDATA13 | output | TCELL55:OUT9.TMIN |
| MAXIGP1WDATA14 | output | TCELL55:OUT10.TMIN |
| MAXIGP1WDATA15 | output | TCELL55:OUT11.TMIN |
| MAXIGP1WDATA16 | output | TCELL56:OUT7.TMIN |
| MAXIGP1WDATA17 | output | TCELL56:OUT8.TMIN |
| MAXIGP1WDATA18 | output | TCELL56:OUT9.TMIN |
| MAXIGP1WDATA19 | output | TCELL56:OUT10.TMIN |
| MAXIGP1WDATA2 | output | TCELL52:OUT5.TMIN |
| MAXIGP1WDATA20 | output | TCELL57:OUT11.TMIN |
| MAXIGP1WDATA21 | output | TCELL57:OUT12.TMIN |
| MAXIGP1WDATA22 | output | TCELL57:OUT13.TMIN |
| MAXIGP1WDATA23 | output | TCELL57:OUT14.TMIN |
| MAXIGP1WDATA24 | output | TCELL58:OUT11.TMIN |
| MAXIGP1WDATA25 | output | TCELL58:OUT12.TMIN |
| MAXIGP1WDATA26 | output | TCELL58:OUT13.TMIN |
| MAXIGP1WDATA27 | output | TCELL58:OUT14.TMIN |
| MAXIGP1WDATA28 | output | TCELL59:OUT14.TMIN |
| MAXIGP1WDATA29 | output | TCELL59:OUT15.TMIN |
| MAXIGP1WDATA3 | output | TCELL52:OUT6.TMIN |
| MAXIGP1WDATA30 | output | TCELL59:OUT16.TMIN |
| MAXIGP1WDATA31 | output | TCELL59:OUT17.TMIN |
| MAXIGP1WDATA4 | output | TCELL53:OUT9.TMIN |
| MAXIGP1WDATA5 | output | TCELL53:OUT10.TMIN |
| MAXIGP1WDATA6 | output | TCELL53:OUT11.TMIN |
| MAXIGP1WDATA7 | output | TCELL53:OUT12.TMIN |
| MAXIGP1WDATA8 | output | TCELL54:OUT10.TMIN |
| MAXIGP1WDATA9 | output | TCELL54:OUT11.TMIN |
| MAXIGP1WID0 | output | TCELL54:OUT9.TMIN |
| MAXIGP1WID1 | output | TCELL55:OUT6.TMIN |
| MAXIGP1WID10 | output | TCELL58:OUT9.TMIN |
| MAXIGP1WID11 | output | TCELL58:OUT10.TMIN |
| MAXIGP1WID2 | output | TCELL55:OUT7.TMIN |
| MAXIGP1WID3 | output | TCELL56:OUT5.TMIN |
| MAXIGP1WID4 | output | TCELL56:OUT6.TMIN |
| MAXIGP1WID5 | output | TCELL57:OUT8.TMIN |
| MAXIGP1WID6 | output | TCELL57:OUT9.TMIN |
| MAXIGP1WID7 | output | TCELL57:OUT10.TMIN |
| MAXIGP1WID8 | output | TCELL58:OUT7.TMIN |
| MAXIGP1WID9 | output | TCELL58:OUT8.TMIN |
| MAXIGP1WLAST | output | TCELL59:OUT18.TMIN |
| MAXIGP1WREADY | input | TCELL55:IMUX.IMUX1 |
| MAXIGP1WSTRB0 | output | TCELL57:OUT15.TMIN |
| MAXIGP1WSTRB1 | output | TCELL57:OUT16.TMIN |
| MAXIGP1WSTRB2 | output | TCELL58:OUT15.TMIN |
| MAXIGP1WSTRB3 | output | TCELL58:OUT16.TMIN |
| MAXIGP1WVALID | output | TCELL55:OUT12.TMIN |
| SAXIACPACLK | input | TCELL35:IMUX.CLK0 |
| SAXIACPARADDR0 | input | TCELL32:IMUX.IMUX12 |
| SAXIACPARADDR1 | input | TCELL32:IMUX.IMUX13 |
| SAXIACPARADDR10 | input | TCELL34:IMUX.IMUX20 |
| SAXIACPARADDR11 | input | TCELL34:IMUX.IMUX21 |
| SAXIACPARADDR12 | input | TCELL35:IMUX.IMUX20 |
| SAXIACPARADDR13 | input | TCELL35:IMUX.IMUX21 |
| SAXIACPARADDR14 | input | TCELL35:IMUX.IMUX22 |
| SAXIACPARADDR15 | input | TCELL35:IMUX.IMUX23 |
| SAXIACPARADDR16 | input | TCELL36:IMUX.IMUX23 |
| SAXIACPARADDR17 | input | TCELL36:IMUX.IMUX24 |
| SAXIACPARADDR18 | input | TCELL36:IMUX.IMUX25 |
| SAXIACPARADDR19 | input | TCELL36:IMUX.IMUX26 |
| SAXIACPARADDR2 | input | TCELL32:IMUX.IMUX14 |
| SAXIACPARADDR20 | input | TCELL37:IMUX.IMUX23 |
| SAXIACPARADDR21 | input | TCELL37:IMUX.IMUX24 |
| SAXIACPARADDR22 | input | TCELL37:IMUX.IMUX25 |
| SAXIACPARADDR23 | input | TCELL37:IMUX.IMUX26 |
| SAXIACPARADDR24 | input | TCELL38:IMUX.IMUX22 |
| SAXIACPARADDR25 | input | TCELL38:IMUX.IMUX23 |
| SAXIACPARADDR26 | input | TCELL38:IMUX.IMUX24 |
| SAXIACPARADDR27 | input | TCELL38:IMUX.IMUX25 |
| SAXIACPARADDR28 | input | TCELL39:IMUX.IMUX17 |
| SAXIACPARADDR29 | input | TCELL39:IMUX.IMUX18 |
| SAXIACPARADDR3 | input | TCELL32:IMUX.IMUX15 |
| SAXIACPARADDR30 | input | TCELL39:IMUX.IMUX19 |
| SAXIACPARADDR31 | input | TCELL39:IMUX.IMUX20 |
| SAXIACPARADDR4 | input | TCELL33:IMUX.IMUX12 |
| SAXIACPARADDR5 | input | TCELL33:IMUX.IMUX13 |
| SAXIACPARADDR6 | input | TCELL33:IMUX.IMUX14 |
| SAXIACPARADDR7 | input | TCELL33:IMUX.IMUX15 |
| SAXIACPARADDR8 | input | TCELL34:IMUX.IMUX18 |
| SAXIACPARADDR9 | input | TCELL34:IMUX.IMUX19 |
| SAXIACPARBURST0 | input | TCELL32:IMUX.IMUX18 |
| SAXIACPARBURST1 | input | TCELL32:IMUX.IMUX19 |
| SAXIACPARCACHE0 | input | TCELL33:IMUX.IMUX20 |
| SAXIACPARCACHE1 | input | TCELL33:IMUX.IMUX21 |
| SAXIACPARCACHE2 | input | TCELL33:IMUX.IMUX22 |
| SAXIACPARCACHE3 | input | TCELL33:IMUX.IMUX23 |
| SAXIACPARESETN | output | TCELL35:OUT0.TMIN |
| SAXIACPARID0 | input | TCELL34:IMUX.IMUX16 |
| SAXIACPARID1 | input | TCELL34:IMUX.IMUX17 |
| SAXIACPARID2 | input | TCELL35:IMUX.IMUX19 |
| SAXIACPARLEN0 | input | TCELL32:IMUX.IMUX16 |
| SAXIACPARLEN1 | input | TCELL32:IMUX.IMUX17 |
| SAXIACPARLEN2 | input | TCELL33:IMUX.IMUX16 |
| SAXIACPARLEN3 | input | TCELL33:IMUX.IMUX17 |
| SAXIACPARLOCK0 | input | TCELL32:IMUX.IMUX20 |
| SAXIACPARLOCK1 | input | TCELL32:IMUX.IMUX21 |
| SAXIACPARPROT0 | input | TCELL33:IMUX.IMUX24 |
| SAXIACPARPROT1 | input | TCELL33:IMUX.IMUX25 |
| SAXIACPARPROT2 | input | TCELL35:IMUX.IMUX24 |
| SAXIACPARQOS0 | input | TCELL34:IMUX.IMUX22 |
| SAXIACPARQOS1 | input | TCELL34:IMUX.IMUX23 |
| SAXIACPARQOS2 | input | TCELL34:IMUX.IMUX24 |
| SAXIACPARQOS3 | input | TCELL34:IMUX.IMUX25 |
| SAXIACPARREADY | output | TCELL35:OUT2.TMIN |
| SAXIACPARSIZE0 | input | TCELL33:IMUX.IMUX18 |
| SAXIACPARSIZE1 | input | TCELL33:IMUX.IMUX19 |
| SAXIACPARUSER0 | input | TCELL32:IMUX.IMUX22 |
| SAXIACPARUSER1 | input | TCELL32:IMUX.IMUX23 |
| SAXIACPARUSER2 | input | TCELL32:IMUX.IMUX24 |
| SAXIACPARUSER3 | input | TCELL32:IMUX.IMUX25 |
| SAXIACPARUSER4 | input | TCELL33:IMUX.IMUX26 |
| SAXIACPARVALID | input | TCELL35:IMUX.IMUX25 |
| SAXIACPAWADDR0 | input | TCELL32:IMUX.IMUX0 |
| SAXIACPAWADDR1 | input | TCELL32:IMUX.IMUX1 |
| SAXIACPAWADDR10 | input | TCELL34:IMUX.IMUX2 |
| SAXIACPAWADDR11 | input | TCELL34:IMUX.IMUX3 |
| SAXIACPAWADDR12 | input | TCELL35:IMUX.IMUX0 |
| SAXIACPAWADDR13 | input | TCELL35:IMUX.IMUX1 |
| SAXIACPAWADDR14 | input | TCELL35:IMUX.IMUX2 |
| SAXIACPAWADDR15 | input | TCELL35:IMUX.IMUX3 |
| SAXIACPAWADDR16 | input | TCELL36:IMUX.IMUX2 |
| SAXIACPAWADDR17 | input | TCELL36:IMUX.IMUX3 |
| SAXIACPAWADDR18 | input | TCELL36:IMUX.IMUX4 |
| SAXIACPAWADDR19 | input | TCELL36:IMUX.IMUX5 |
| SAXIACPAWADDR2 | input | TCELL32:IMUX.IMUX2 |
| SAXIACPAWADDR20 | input | TCELL37:IMUX.IMUX2 |
| SAXIACPAWADDR21 | input | TCELL37:IMUX.IMUX3 |
| SAXIACPAWADDR22 | input | TCELL37:IMUX.IMUX4 |
| SAXIACPAWADDR23 | input | TCELL37:IMUX.IMUX5 |
| SAXIACPAWADDR24 | input | TCELL38:IMUX.IMUX2 |
| SAXIACPAWADDR25 | input | TCELL38:IMUX.IMUX3 |
| SAXIACPAWADDR26 | input | TCELL38:IMUX.IMUX4 |
| SAXIACPAWADDR27 | input | TCELL38:IMUX.IMUX5 |
| SAXIACPAWADDR28 | input | TCELL39:IMUX.IMUX5 |
| SAXIACPAWADDR29 | input | TCELL39:IMUX.IMUX6 |
| SAXIACPAWADDR3 | input | TCELL32:IMUX.IMUX3 |
| SAXIACPAWADDR30 | input | TCELL39:IMUX.IMUX7 |
| SAXIACPAWADDR31 | input | TCELL39:IMUX.IMUX8 |
| SAXIACPAWADDR4 | input | TCELL33:IMUX.IMUX0 |
| SAXIACPAWADDR5 | input | TCELL33:IMUX.IMUX1 |
| SAXIACPAWADDR6 | input | TCELL33:IMUX.IMUX2 |
| SAXIACPAWADDR7 | input | TCELL33:IMUX.IMUX3 |
| SAXIACPAWADDR8 | input | TCELL34:IMUX.IMUX0 |
| SAXIACPAWADDR9 | input | TCELL34:IMUX.IMUX1 |
| SAXIACPAWBURST0 | input | TCELL38:IMUX.IMUX12 |
| SAXIACPAWBURST1 | input | TCELL38:IMUX.IMUX13 |
| SAXIACPAWCACHE0 | input | TCELL37:IMUX.IMUX8 |
| SAXIACPAWCACHE1 | input | TCELL37:IMUX.IMUX9 |
| SAXIACPAWCACHE2 | input | TCELL37:IMUX.IMUX10 |
| SAXIACPAWCACHE3 | input | TCELL37:IMUX.IMUX11 |
| SAXIACPAWID0 | input | TCELL39:IMUX.IMUX2 |
| SAXIACPAWID1 | input | TCELL39:IMUX.IMUX3 |
| SAXIACPAWID2 | input | TCELL39:IMUX.IMUX4 |
| SAXIACPAWLEN0 | input | TCELL38:IMUX.IMUX6 |
| SAXIACPAWLEN1 | input | TCELL38:IMUX.IMUX7 |
| SAXIACPAWLEN2 | input | TCELL38:IMUX.IMUX8 |
| SAXIACPAWLEN3 | input | TCELL38:IMUX.IMUX9 |
| SAXIACPAWLOCK0 | input | TCELL37:IMUX.IMUX6 |
| SAXIACPAWLOCK1 | input | TCELL37:IMUX.IMUX7 |
| SAXIACPAWPROT0 | input | TCELL37:IMUX.IMUX12 |
| SAXIACPAWPROT1 | input | TCELL37:IMUX.IMUX13 |
| SAXIACPAWPROT2 | input | TCELL37:IMUX.IMUX14 |
| SAXIACPAWQOS0 | input | TCELL39:IMUX.IMUX21 |
| SAXIACPAWQOS1 | input | TCELL39:IMUX.IMUX22 |
| SAXIACPAWQOS2 | input | TCELL39:IMUX.IMUX23 |
| SAXIACPAWQOS3 | input | TCELL39:IMUX.IMUX24 |
| SAXIACPAWREADY | output | TCELL36:OUT1.TMIN |
| SAXIACPAWSIZE0 | input | TCELL38:IMUX.IMUX10 |
| SAXIACPAWSIZE1 | input | TCELL38:IMUX.IMUX11 |
| SAXIACPAWUSER0 | input | TCELL35:IMUX.IMUX4 |
| SAXIACPAWUSER1 | input | TCELL36:IMUX.IMUX7 |
| SAXIACPAWUSER2 | input | TCELL36:IMUX.IMUX8 |
| SAXIACPAWUSER3 | input | TCELL36:IMUX.IMUX9 |
| SAXIACPAWUSER4 | input | TCELL36:IMUX.IMUX10 |
| SAXIACPAWVALID | input | TCELL36:IMUX.IMUX6 |
| SAXIACPBID0 | output | TCELL34:OUT0.TMIN |
| SAXIACPBID1 | output | TCELL34:OUT1.TMIN |
| SAXIACPBID2 | output | TCELL34:OUT2.TMIN |
| SAXIACPBREADY | input | TCELL36:IMUX.IMUX22 |
| SAXIACPBRESP0 | output | TCELL37:OUT1.TMIN |
| SAXIACPBRESP1 | output | TCELL37:OUT2.TMIN |
| SAXIACPBVALID | output | TCELL36:OUT2.TMIN |
| SAXIACPRDATA0 | output | TCELL32:OUT6.TMIN |
| SAXIACPRDATA1 | output | TCELL32:OUT7.TMIN |
| SAXIACPRDATA10 | output | TCELL34:OUT7.TMIN |
| SAXIACPRDATA11 | output | TCELL34:OUT8.TMIN |
| SAXIACPRDATA12 | output | TCELL35:OUT4.TMIN |
| SAXIACPRDATA13 | output | TCELL35:OUT5.TMIN |
| SAXIACPRDATA14 | output | TCELL35:OUT6.TMIN |
| SAXIACPRDATA15 | output | TCELL35:OUT7.TMIN |
| SAXIACPRDATA16 | output | TCELL36:OUT3.TMIN |
| SAXIACPRDATA17 | output | TCELL36:OUT4.TMIN |
| SAXIACPRDATA18 | output | TCELL36:OUT5.TMIN |
| SAXIACPRDATA19 | output | TCELL36:OUT6.TMIN |
| SAXIACPRDATA2 | output | TCELL32:OUT8.TMIN |
| SAXIACPRDATA20 | output | TCELL37:OUT3.TMIN |
| SAXIACPRDATA21 | output | TCELL37:OUT4.TMIN |
| SAXIACPRDATA22 | output | TCELL37:OUT5.TMIN |
| SAXIACPRDATA23 | output | TCELL37:OUT6.TMIN |
| SAXIACPRDATA24 | output | TCELL38:OUT1.TMIN |
| SAXIACPRDATA25 | output | TCELL38:OUT2.TMIN |
| SAXIACPRDATA26 | output | TCELL38:OUT3.TMIN |
| SAXIACPRDATA27 | output | TCELL38:OUT4.TMIN |
| SAXIACPRDATA28 | output | TCELL39:OUT5.TMIN |
| SAXIACPRDATA29 | output | TCELL39:OUT6.TMIN |
| SAXIACPRDATA3 | output | TCELL32:OUT9.TMIN |
| SAXIACPRDATA30 | output | TCELL39:OUT7.TMIN |
| SAXIACPRDATA31 | output | TCELL39:OUT8.TMIN |
| SAXIACPRDATA32 | output | TCELL32:OUT10.TMIN |
| SAXIACPRDATA33 | output | TCELL32:OUT11.TMIN |
| SAXIACPRDATA34 | output | TCELL32:OUT12.TMIN |
| SAXIACPRDATA35 | output | TCELL32:OUT13.TMIN |
| SAXIACPRDATA36 | output | TCELL33:OUT10.TMIN |
| SAXIACPRDATA37 | output | TCELL33:OUT11.TMIN |
| SAXIACPRDATA38 | output | TCELL33:OUT12.TMIN |
| SAXIACPRDATA39 | output | TCELL33:OUT13.TMIN |
| SAXIACPRDATA4 | output | TCELL33:OUT6.TMIN |
| SAXIACPRDATA40 | output | TCELL34:OUT9.TMIN |
| SAXIACPRDATA41 | output | TCELL34:OUT10.TMIN |
| SAXIACPRDATA42 | output | TCELL34:OUT11.TMIN |
| SAXIACPRDATA43 | output | TCELL34:OUT12.TMIN |
| SAXIACPRDATA44 | output | TCELL35:OUT8.TMIN |
| SAXIACPRDATA45 | output | TCELL35:OUT9.TMIN |
| SAXIACPRDATA46 | output | TCELL35:OUT10.TMIN |
| SAXIACPRDATA47 | output | TCELL35:OUT11.TMIN |
| SAXIACPRDATA48 | output | TCELL36:OUT7.TMIN |
| SAXIACPRDATA49 | output | TCELL36:OUT8.TMIN |
| SAXIACPRDATA5 | output | TCELL33:OUT7.TMIN |
| SAXIACPRDATA50 | output | TCELL36:OUT9.TMIN |
| SAXIACPRDATA51 | output | TCELL36:OUT10.TMIN |
| SAXIACPRDATA52 | output | TCELL37:OUT7.TMIN |
| SAXIACPRDATA53 | output | TCELL37:OUT8.TMIN |
| SAXIACPRDATA54 | output | TCELL37:OUT9.TMIN |
| SAXIACPRDATA55 | output | TCELL37:OUT10.TMIN |
| SAXIACPRDATA56 | output | TCELL38:OUT5.TMIN |
| SAXIACPRDATA57 | output | TCELL38:OUT6.TMIN |
| SAXIACPRDATA58 | output | TCELL38:OUT7.TMIN |
| SAXIACPRDATA59 | output | TCELL38:OUT8.TMIN |
| SAXIACPRDATA6 | output | TCELL33:OUT8.TMIN |
| SAXIACPRDATA60 | output | TCELL39:OUT9.TMIN |
| SAXIACPRDATA61 | output | TCELL39:OUT10.TMIN |
| SAXIACPRDATA62 | output | TCELL39:OUT11.TMIN |
| SAXIACPRDATA63 | output | TCELL39:OUT12.TMIN |
| SAXIACPRDATA7 | output | TCELL33:OUT9.TMIN |
| SAXIACPRDATA8 | output | TCELL34:OUT5.TMIN |
| SAXIACPRDATA9 | output | TCELL34:OUT6.TMIN |
| SAXIACPRID0 | output | TCELL34:OUT3.TMIN |
| SAXIACPRID1 | output | TCELL34:OUT4.TMIN |
| SAXIACPRID2 | output | TCELL35:OUT3.TMIN |
| SAXIACPRLAST | output | TCELL38:OUT11.TMIN |
| SAXIACPRREADY | input | TCELL35:IMUX.IMUX26 |
| SAXIACPRRESP0 | output | TCELL38:OUT9.TMIN |
| SAXIACPRRESP1 | output | TCELL38:OUT10.TMIN |
| SAXIACPRVALID | output | TCELL35:OUT12.TMIN |
| SAXIACPWDATA0 | input | TCELL32:IMUX.IMUX4 |
| SAXIACPWDATA1 | input | TCELL32:IMUX.IMUX5 |
| SAXIACPWDATA10 | input | TCELL34:IMUX.IMUX6 |
| SAXIACPWDATA11 | input | TCELL34:IMUX.IMUX7 |
| SAXIACPWDATA12 | input | TCELL35:IMUX.IMUX5 |
| SAXIACPWDATA13 | input | TCELL35:IMUX.IMUX6 |
| SAXIACPWDATA14 | input | TCELL35:IMUX.IMUX7 |
| SAXIACPWDATA15 | input | TCELL35:IMUX.IMUX8 |
| SAXIACPWDATA16 | input | TCELL36:IMUX.IMUX14 |
| SAXIACPWDATA17 | input | TCELL36:IMUX.IMUX15 |
| SAXIACPWDATA18 | input | TCELL36:IMUX.IMUX16 |
| SAXIACPWDATA19 | input | TCELL36:IMUX.IMUX17 |
| SAXIACPWDATA2 | input | TCELL32:IMUX.IMUX6 |
| SAXIACPWDATA20 | input | TCELL37:IMUX.IMUX15 |
| SAXIACPWDATA21 | input | TCELL37:IMUX.IMUX16 |
| SAXIACPWDATA22 | input | TCELL37:IMUX.IMUX17 |
| SAXIACPWDATA23 | input | TCELL37:IMUX.IMUX18 |
| SAXIACPWDATA24 | input | TCELL38:IMUX.IMUX14 |
| SAXIACPWDATA25 | input | TCELL38:IMUX.IMUX15 |
| SAXIACPWDATA26 | input | TCELL38:IMUX.IMUX16 |
| SAXIACPWDATA27 | input | TCELL38:IMUX.IMUX17 |
| SAXIACPWDATA28 | input | TCELL39:IMUX.IMUX9 |
| SAXIACPWDATA29 | input | TCELL39:IMUX.IMUX10 |
| SAXIACPWDATA3 | input | TCELL32:IMUX.IMUX7 |
| SAXIACPWDATA30 | input | TCELL39:IMUX.IMUX11 |
| SAXIACPWDATA31 | input | TCELL39:IMUX.IMUX12 |
| SAXIACPWDATA32 | input | TCELL32:IMUX.IMUX8 |
| SAXIACPWDATA33 | input | TCELL32:IMUX.IMUX9 |
| SAXIACPWDATA34 | input | TCELL32:IMUX.IMUX10 |
| SAXIACPWDATA35 | input | TCELL32:IMUX.IMUX11 |
| SAXIACPWDATA36 | input | TCELL33:IMUX.IMUX8 |
| SAXIACPWDATA37 | input | TCELL33:IMUX.IMUX9 |
| SAXIACPWDATA38 | input | TCELL33:IMUX.IMUX10 |
| SAXIACPWDATA39 | input | TCELL33:IMUX.IMUX11 |
| SAXIACPWDATA4 | input | TCELL33:IMUX.IMUX4 |
| SAXIACPWDATA40 | input | TCELL34:IMUX.IMUX8 |
| SAXIACPWDATA41 | input | TCELL34:IMUX.IMUX9 |
| SAXIACPWDATA42 | input | TCELL34:IMUX.IMUX10 |
| SAXIACPWDATA43 | input | TCELL34:IMUX.IMUX11 |
| SAXIACPWDATA44 | input | TCELL35:IMUX.IMUX9 |
| SAXIACPWDATA45 | input | TCELL35:IMUX.IMUX10 |
| SAXIACPWDATA46 | input | TCELL35:IMUX.IMUX11 |
| SAXIACPWDATA47 | input | TCELL35:IMUX.IMUX12 |
| SAXIACPWDATA48 | input | TCELL36:IMUX.IMUX18 |
| SAXIACPWDATA49 | input | TCELL36:IMUX.IMUX19 |
| SAXIACPWDATA5 | input | TCELL33:IMUX.IMUX5 |
| SAXIACPWDATA50 | input | TCELL36:IMUX.IMUX20 |
| SAXIACPWDATA51 | input | TCELL36:IMUX.IMUX21 |
| SAXIACPWDATA52 | input | TCELL37:IMUX.IMUX19 |
| SAXIACPWDATA53 | input | TCELL37:IMUX.IMUX20 |
| SAXIACPWDATA54 | input | TCELL37:IMUX.IMUX21 |
| SAXIACPWDATA55 | input | TCELL37:IMUX.IMUX22 |
| SAXIACPWDATA56 | input | TCELL38:IMUX.IMUX18 |
| SAXIACPWDATA57 | input | TCELL38:IMUX.IMUX19 |
| SAXIACPWDATA58 | input | TCELL38:IMUX.IMUX20 |
| SAXIACPWDATA59 | input | TCELL38:IMUX.IMUX21 |
| SAXIACPWDATA6 | input | TCELL33:IMUX.IMUX6 |
| SAXIACPWDATA60 | input | TCELL39:IMUX.IMUX13 |
| SAXIACPWDATA61 | input | TCELL39:IMUX.IMUX14 |
| SAXIACPWDATA62 | input | TCELL39:IMUX.IMUX15 |
| SAXIACPWDATA63 | input | TCELL39:IMUX.IMUX16 |
| SAXIACPWDATA7 | input | TCELL33:IMUX.IMUX7 |
| SAXIACPWDATA8 | input | TCELL34:IMUX.IMUX4 |
| SAXIACPWDATA9 | input | TCELL34:IMUX.IMUX5 |
| SAXIACPWID0 | input | TCELL36:IMUX.IMUX11 |
| SAXIACPWID1 | input | TCELL36:IMUX.IMUX12 |
| SAXIACPWID2 | input | TCELL36:IMUX.IMUX13 |
| SAXIACPWLAST | input | TCELL35:IMUX.IMUX17 |
| SAXIACPWREADY | output | TCELL35:OUT1.TMIN |
| SAXIACPWSTRB0 | input | TCELL34:IMUX.IMUX12 |
| SAXIACPWSTRB1 | input | TCELL34:IMUX.IMUX13 |
| SAXIACPWSTRB2 | input | TCELL34:IMUX.IMUX14 |
| SAXIACPWSTRB3 | input | TCELL34:IMUX.IMUX15 |
| SAXIACPWSTRB4 | input | TCELL35:IMUX.IMUX13 |
| SAXIACPWSTRB5 | input | TCELL35:IMUX.IMUX14 |
| SAXIACPWSTRB6 | input | TCELL35:IMUX.IMUX15 |
| SAXIACPWSTRB7 | input | TCELL35:IMUX.IMUX16 |
| SAXIACPWVALID | input | TCELL35:IMUX.IMUX18 |
| SAXIGP0ACLK | input | TCELL77:IMUX.CLK0 |
| SAXIGP0ARADDR0 | input | TCELL73:IMUX.IMUX8 |
| SAXIGP0ARADDR1 | input | TCELL73:IMUX.IMUX9 |
| SAXIGP0ARADDR10 | input | TCELL75:IMUX.IMUX14 |
| SAXIGP0ARADDR11 | input | TCELL75:IMUX.IMUX15 |
| SAXIGP0ARADDR12 | input | TCELL76:IMUX.IMUX15 |
| SAXIGP0ARADDR13 | input | TCELL76:IMUX.IMUX16 |
| SAXIGP0ARADDR14 | input | TCELL76:IMUX.IMUX17 |
| SAXIGP0ARADDR15 | input | TCELL76:IMUX.IMUX18 |
| SAXIGP0ARADDR16 | input | TCELL77:IMUX.IMUX16 |
| SAXIGP0ARADDR17 | input | TCELL77:IMUX.IMUX17 |
| SAXIGP0ARADDR18 | input | TCELL77:IMUX.IMUX18 |
| SAXIGP0ARADDR19 | input | TCELL77:IMUX.IMUX19 |
| SAXIGP0ARADDR2 | input | TCELL73:IMUX.IMUX10 |
| SAXIGP0ARADDR20 | input | TCELL78:IMUX.IMUX15 |
| SAXIGP0ARADDR21 | input | TCELL78:IMUX.IMUX16 |
| SAXIGP0ARADDR22 | input | TCELL78:IMUX.IMUX17 |
| SAXIGP0ARADDR23 | input | TCELL78:IMUX.IMUX18 |
| SAXIGP0ARADDR24 | input | TCELL79:IMUX.IMUX16 |
| SAXIGP0ARADDR25 | input | TCELL79:IMUX.IMUX17 |
| SAXIGP0ARADDR26 | input | TCELL79:IMUX.IMUX18 |
| SAXIGP0ARADDR27 | input | TCELL79:IMUX.IMUX19 |
| SAXIGP0ARADDR28 | input | TCELL80:IMUX.IMUX16 |
| SAXIGP0ARADDR29 | input | TCELL80:IMUX.IMUX17 |
| SAXIGP0ARADDR3 | input | TCELL73:IMUX.IMUX11 |
| SAXIGP0ARADDR30 | input | TCELL80:IMUX.IMUX18 |
| SAXIGP0ARADDR31 | input | TCELL80:IMUX.IMUX19 |
| SAXIGP0ARADDR4 | input | TCELL74:IMUX.IMUX9 |
| SAXIGP0ARADDR5 | input | TCELL74:IMUX.IMUX10 |
| SAXIGP0ARADDR6 | input | TCELL74:IMUX.IMUX11 |
| SAXIGP0ARADDR7 | input | TCELL74:IMUX.IMUX12 |
| SAXIGP0ARADDR8 | input | TCELL75:IMUX.IMUX12 |
| SAXIGP0ARADDR9 | input | TCELL75:IMUX.IMUX13 |
| SAXIGP0ARBURST0 | input | TCELL74:IMUX.IMUX13 |
| SAXIGP0ARBURST1 | input | TCELL74:IMUX.IMUX14 |
| SAXIGP0ARCACHE0 | input | TCELL73:IMUX.IMUX12 |
| SAXIGP0ARCACHE1 | input | TCELL73:IMUX.IMUX13 |
| SAXIGP0ARCACHE2 | input | TCELL73:IMUX.IMUX14 |
| SAXIGP0ARCACHE3 | input | TCELL73:IMUX.IMUX15 |
| SAXIGP0ARESETN | output | TCELL77:OUT8.TMIN |
| SAXIGP0ARID0 | input | TCELL75:IMUX.IMUX8 |
| SAXIGP0ARID1 | input | TCELL75:IMUX.IMUX9 |
| SAXIGP0ARID2 | input | TCELL75:IMUX.IMUX10 |
| SAXIGP0ARID3 | input | TCELL75:IMUX.IMUX11 |
| SAXIGP0ARID4 | input | TCELL76:IMUX.IMUX13 |
| SAXIGP0ARID5 | input | TCELL76:IMUX.IMUX14 |
| SAXIGP0ARLEN0 | input | TCELL75:IMUX.IMUX16 |
| SAXIGP0ARLEN1 | input | TCELL75:IMUX.IMUX17 |
| SAXIGP0ARLEN2 | input | TCELL75:IMUX.IMUX18 |
| SAXIGP0ARLEN3 | input | TCELL75:IMUX.IMUX19 |
| SAXIGP0ARLOCK0 | input | TCELL74:IMUX.IMUX15 |
| SAXIGP0ARLOCK1 | input | TCELL74:IMUX.IMUX16 |
| SAXIGP0ARPROT0 | input | TCELL73:IMUX.IMUX16 |
| SAXIGP0ARPROT1 | input | TCELL73:IMUX.IMUX17 |
| SAXIGP0ARPROT2 | input | TCELL73:IMUX.IMUX18 |
| SAXIGP0ARQOS0 | input | TCELL74:IMUX.IMUX17 |
| SAXIGP0ARQOS1 | input | TCELL74:IMUX.IMUX18 |
| SAXIGP0ARQOS2 | input | TCELL74:IMUX.IMUX19 |
| SAXIGP0ARQOS3 | input | TCELL74:IMUX.IMUX20 |
| SAXIGP0ARREADY | output | TCELL76:OUT8.TMIN |
| SAXIGP0ARSIZE0 | input | TCELL75:IMUX.IMUX20 |
| SAXIGP0ARSIZE1 | input | TCELL75:IMUX.IMUX21 |
| SAXIGP0ARVALID | input | TCELL76:IMUX.IMUX19 |
| SAXIGP0AWADDR0 | input | TCELL73:IMUX.IMUX0 |
| SAXIGP0AWADDR1 | input | TCELL73:IMUX.IMUX1 |
| SAXIGP0AWADDR10 | input | TCELL75:IMUX.IMUX2 |
| SAXIGP0AWADDR11 | input | TCELL75:IMUX.IMUX3 |
| SAXIGP0AWADDR12 | input | TCELL76:IMUX.IMUX0 |
| SAXIGP0AWADDR13 | input | TCELL76:IMUX.IMUX1 |
| SAXIGP0AWADDR14 | input | TCELL76:IMUX.IMUX2 |
| SAXIGP0AWADDR15 | input | TCELL76:IMUX.IMUX3 |
| SAXIGP0AWADDR16 | input | TCELL77:IMUX.IMUX0 |
| SAXIGP0AWADDR17 | input | TCELL77:IMUX.IMUX1 |
| SAXIGP0AWADDR18 | input | TCELL77:IMUX.IMUX2 |
| SAXIGP0AWADDR19 | input | TCELL77:IMUX.IMUX3 |
| SAXIGP0AWADDR2 | input | TCELL73:IMUX.IMUX2 |
| SAXIGP0AWADDR20 | input | TCELL78:IMUX.IMUX0 |
| SAXIGP0AWADDR21 | input | TCELL78:IMUX.IMUX1 |
| SAXIGP0AWADDR22 | input | TCELL78:IMUX.IMUX2 |
| SAXIGP0AWADDR23 | input | TCELL78:IMUX.IMUX3 |
| SAXIGP0AWADDR24 | input | TCELL79:IMUX.IMUX2 |
| SAXIGP0AWADDR25 | input | TCELL79:IMUX.IMUX3 |
| SAXIGP0AWADDR26 | input | TCELL79:IMUX.IMUX4 |
| SAXIGP0AWADDR27 | input | TCELL79:IMUX.IMUX5 |
| SAXIGP0AWADDR28 | input | TCELL80:IMUX.IMUX4 |
| SAXIGP0AWADDR29 | input | TCELL80:IMUX.IMUX5 |
| SAXIGP0AWADDR3 | input | TCELL73:IMUX.IMUX3 |
| SAXIGP0AWADDR30 | input | TCELL80:IMUX.IMUX6 |
| SAXIGP0AWADDR31 | input | TCELL80:IMUX.IMUX7 |
| SAXIGP0AWADDR4 | input | TCELL74:IMUX.IMUX0 |
| SAXIGP0AWADDR5 | input | TCELL74:IMUX.IMUX1 |
| SAXIGP0AWADDR6 | input | TCELL74:IMUX.IMUX2 |
| SAXIGP0AWADDR7 | input | TCELL74:IMUX.IMUX3 |
| SAXIGP0AWADDR8 | input | TCELL75:IMUX.IMUX0 |
| SAXIGP0AWADDR9 | input | TCELL75:IMUX.IMUX1 |
| SAXIGP0AWBURST0 | input | TCELL78:IMUX.IMUX4 |
| SAXIGP0AWBURST1 | input | TCELL78:IMUX.IMUX5 |
| SAXIGP0AWCACHE0 | input | TCELL77:IMUX.IMUX4 |
| SAXIGP0AWCACHE1 | input | TCELL77:IMUX.IMUX5 |
| SAXIGP0AWCACHE2 | input | TCELL78:IMUX.IMUX8 |
| SAXIGP0AWCACHE3 | input | TCELL78:IMUX.IMUX9 |
| SAXIGP0AWID0 | input | TCELL79:IMUX.IMUX0 |
| SAXIGP0AWID1 | input | TCELL79:IMUX.IMUX1 |
| SAXIGP0AWID2 | input | TCELL80:IMUX.IMUX0 |
| SAXIGP0AWID3 | input | TCELL80:IMUX.IMUX1 |
| SAXIGP0AWID4 | input | TCELL80:IMUX.IMUX2 |
| SAXIGP0AWID5 | input | TCELL80:IMUX.IMUX3 |
| SAXIGP0AWLEN0 | input | TCELL80:IMUX.IMUX8 |
| SAXIGP0AWLEN1 | input | TCELL80:IMUX.IMUX9 |
| SAXIGP0AWLEN2 | input | TCELL80:IMUX.IMUX10 |
| SAXIGP0AWLEN3 | input | TCELL80:IMUX.IMUX11 |
| SAXIGP0AWLOCK0 | input | TCELL78:IMUX.IMUX6 |
| SAXIGP0AWLOCK1 | input | TCELL78:IMUX.IMUX7 |
| SAXIGP0AWPROT0 | input | TCELL76:IMUX.IMUX4 |
| SAXIGP0AWPROT1 | input | TCELL76:IMUX.IMUX5 |
| SAXIGP0AWPROT2 | input | TCELL76:IMUX.IMUX6 |
| SAXIGP0AWQOS0 | input | TCELL78:IMUX.IMUX19 |
| SAXIGP0AWQOS1 | input | TCELL78:IMUX.IMUX20 |
| SAXIGP0AWQOS2 | input | TCELL78:IMUX.IMUX21 |
| SAXIGP0AWQOS3 | input | TCELL78:IMUX.IMUX22 |
| SAXIGP0AWREADY | output | TCELL77:OUT9.TMIN |
| SAXIGP0AWSIZE0 | input | TCELL79:IMUX.IMUX6 |
| SAXIGP0AWSIZE1 | input | TCELL79:IMUX.IMUX7 |
| SAXIGP0AWVALID | input | TCELL77:IMUX.IMUX6 |
| SAXIGP0BID0 | output | TCELL79:OUT8.TMIN |
| SAXIGP0BID1 | output | TCELL79:OUT9.TMIN |
| SAXIGP0BID2 | output | TCELL80:OUT8.TMIN |
| SAXIGP0BID3 | output | TCELL80:OUT9.TMIN |
| SAXIGP0BID4 | output | TCELL80:OUT10.TMIN |
| SAXIGP0BID5 | output | TCELL80:OUT11.TMIN |
| SAXIGP0BREADY | input | TCELL78:IMUX.IMUX14 |
| SAXIGP0BRESP0 | output | TCELL79:OUT10.TMIN |
| SAXIGP0BRESP1 | output | TCELL79:OUT11.TMIN |
| SAXIGP0BVALID | output | TCELL78:OUT8.TMIN |
| SAXIGP0RDATA0 | output | TCELL73:OUT12.TMIN |
| SAXIGP0RDATA1 | output | TCELL73:OUT13.TMIN |
| SAXIGP0RDATA10 | output | TCELL75:OUT10.TMIN |
| SAXIGP0RDATA11 | output | TCELL75:OUT11.TMIN |
| SAXIGP0RDATA12 | output | TCELL76:OUT9.TMIN |
| SAXIGP0RDATA13 | output | TCELL76:OUT10.TMIN |
| SAXIGP0RDATA14 | output | TCELL76:OUT11.TMIN |
| SAXIGP0RDATA15 | output | TCELL76:OUT12.TMIN |
| SAXIGP0RDATA16 | output | TCELL77:OUT11.TMIN |
| SAXIGP0RDATA17 | output | TCELL77:OUT12.TMIN |
| SAXIGP0RDATA18 | output | TCELL77:OUT13.TMIN |
| SAXIGP0RDATA19 | output | TCELL77:OUT14.TMIN |
| SAXIGP0RDATA2 | output | TCELL73:OUT14.TMIN |
| SAXIGP0RDATA20 | output | TCELL78:OUT9.TMIN |
| SAXIGP0RDATA21 | output | TCELL78:OUT10.TMIN |
| SAXIGP0RDATA22 | output | TCELL78:OUT11.TMIN |
| SAXIGP0RDATA23 | output | TCELL78:OUT12.TMIN |
| SAXIGP0RDATA24 | output | TCELL79:OUT12.TMIN |
| SAXIGP0RDATA25 | output | TCELL79:OUT13.TMIN |
| SAXIGP0RDATA26 | output | TCELL79:OUT14.TMIN |
| SAXIGP0RDATA27 | output | TCELL79:OUT15.TMIN |
| SAXIGP0RDATA28 | output | TCELL80:OUT12.TMIN |
| SAXIGP0RDATA29 | output | TCELL80:OUT13.TMIN |
| SAXIGP0RDATA3 | output | TCELL73:OUT15.TMIN |
| SAXIGP0RDATA30 | output | TCELL80:OUT14.TMIN |
| SAXIGP0RDATA31 | output | TCELL80:OUT15.TMIN |
| SAXIGP0RDATA4 | output | TCELL74:OUT10.TMIN |
| SAXIGP0RDATA5 | output | TCELL74:OUT11.TMIN |
| SAXIGP0RDATA6 | output | TCELL74:OUT12.TMIN |
| SAXIGP0RDATA7 | output | TCELL74:OUT13.TMIN |
| SAXIGP0RDATA8 | output | TCELL75:OUT8.TMIN |
| SAXIGP0RDATA9 | output | TCELL75:OUT9.TMIN |
| SAXIGP0RID0 | output | TCELL73:OUT8.TMIN |
| SAXIGP0RID1 | output | TCELL73:OUT9.TMIN |
| SAXIGP0RID2 | output | TCELL73:OUT10.TMIN |
| SAXIGP0RID3 | output | TCELL73:OUT11.TMIN |
| SAXIGP0RID4 | output | TCELL74:OUT8.TMIN |
| SAXIGP0RID5 | output | TCELL74:OUT9.TMIN |
| SAXIGP0RLAST | output | TCELL74:OUT14.TMIN |
| SAXIGP0RREADY | input | TCELL76:IMUX.IMUX20 |
| SAXIGP0RRESP0 | output | TCELL75:OUT12.TMIN |
| SAXIGP0RRESP1 | output | TCELL75:OUT13.TMIN |
| SAXIGP0RVALID | output | TCELL76:OUT13.TMIN |
| SAXIGP0WDATA0 | input | TCELL73:IMUX.IMUX4 |
| SAXIGP0WDATA1 | input | TCELL73:IMUX.IMUX5 |
| SAXIGP0WDATA10 | input | TCELL75:IMUX.IMUX6 |
| SAXIGP0WDATA11 | input | TCELL75:IMUX.IMUX7 |
| SAXIGP0WDATA12 | input | TCELL76:IMUX.IMUX9 |
| SAXIGP0WDATA13 | input | TCELL76:IMUX.IMUX10 |
| SAXIGP0WDATA14 | input | TCELL76:IMUX.IMUX11 |
| SAXIGP0WDATA15 | input | TCELL76:IMUX.IMUX12 |
| SAXIGP0WDATA16 | input | TCELL77:IMUX.IMUX11 |
| SAXIGP0WDATA17 | input | TCELL77:IMUX.IMUX12 |
| SAXIGP0WDATA18 | input | TCELL77:IMUX.IMUX13 |
| SAXIGP0WDATA19 | input | TCELL77:IMUX.IMUX14 |
| SAXIGP0WDATA2 | input | TCELL73:IMUX.IMUX6 |
| SAXIGP0WDATA20 | input | TCELL78:IMUX.IMUX10 |
| SAXIGP0WDATA21 | input | TCELL78:IMUX.IMUX11 |
| SAXIGP0WDATA22 | input | TCELL78:IMUX.IMUX12 |
| SAXIGP0WDATA23 | input | TCELL78:IMUX.IMUX13 |
| SAXIGP0WDATA24 | input | TCELL79:IMUX.IMUX8 |
| SAXIGP0WDATA25 | input | TCELL79:IMUX.IMUX9 |
| SAXIGP0WDATA26 | input | TCELL79:IMUX.IMUX10 |
| SAXIGP0WDATA27 | input | TCELL79:IMUX.IMUX11 |
| SAXIGP0WDATA28 | input | TCELL80:IMUX.IMUX12 |
| SAXIGP0WDATA29 | input | TCELL80:IMUX.IMUX13 |
| SAXIGP0WDATA3 | input | TCELL73:IMUX.IMUX7 |
| SAXIGP0WDATA30 | input | TCELL80:IMUX.IMUX14 |
| SAXIGP0WDATA31 | input | TCELL80:IMUX.IMUX15 |
| SAXIGP0WDATA4 | input | TCELL74:IMUX.IMUX4 |
| SAXIGP0WDATA5 | input | TCELL74:IMUX.IMUX5 |
| SAXIGP0WDATA6 | input | TCELL74:IMUX.IMUX6 |
| SAXIGP0WDATA7 | input | TCELL74:IMUX.IMUX7 |
| SAXIGP0WDATA8 | input | TCELL75:IMUX.IMUX4 |
| SAXIGP0WDATA9 | input | TCELL75:IMUX.IMUX5 |
| SAXIGP0WID0 | input | TCELL76:IMUX.IMUX7 |
| SAXIGP0WID1 | input | TCELL76:IMUX.IMUX8 |
| SAXIGP0WID2 | input | TCELL77:IMUX.IMUX7 |
| SAXIGP0WID3 | input | TCELL77:IMUX.IMUX8 |
| SAXIGP0WID4 | input | TCELL77:IMUX.IMUX9 |
| SAXIGP0WID5 | input | TCELL77:IMUX.IMUX10 |
| SAXIGP0WLAST | input | TCELL74:IMUX.IMUX8 |
| SAXIGP0WREADY | output | TCELL77:OUT10.TMIN |
| SAXIGP0WSTRB0 | input | TCELL79:IMUX.IMUX12 |
| SAXIGP0WSTRB1 | input | TCELL79:IMUX.IMUX13 |
| SAXIGP0WSTRB2 | input | TCELL79:IMUX.IMUX14 |
| SAXIGP0WSTRB3 | input | TCELL79:IMUX.IMUX15 |
| SAXIGP0WVALID | input | TCELL77:IMUX.IMUX15 |
| SAXIGP1ACLK | input | TCELL85:IMUX.CLK0 |
| SAXIGP1ARADDR0 | input | TCELL81:IMUX.IMUX8 |
| SAXIGP1ARADDR1 | input | TCELL81:IMUX.IMUX9 |
| SAXIGP1ARADDR10 | input | TCELL83:IMUX.IMUX14 |
| SAXIGP1ARADDR11 | input | TCELL83:IMUX.IMUX15 |
| SAXIGP1ARADDR12 | input | TCELL84:IMUX.IMUX15 |
| SAXIGP1ARADDR13 | input | TCELL84:IMUX.IMUX16 |
| SAXIGP1ARADDR14 | input | TCELL84:IMUX.IMUX17 |
| SAXIGP1ARADDR15 | input | TCELL84:IMUX.IMUX18 |
| SAXIGP1ARADDR16 | input | TCELL85:IMUX.IMUX16 |
| SAXIGP1ARADDR17 | input | TCELL85:IMUX.IMUX17 |
| SAXIGP1ARADDR18 | input | TCELL85:IMUX.IMUX18 |
| SAXIGP1ARADDR19 | input | TCELL85:IMUX.IMUX19 |
| SAXIGP1ARADDR2 | input | TCELL81:IMUX.IMUX10 |
| SAXIGP1ARADDR20 | input | TCELL86:IMUX.IMUX15 |
| SAXIGP1ARADDR21 | input | TCELL86:IMUX.IMUX16 |
| SAXIGP1ARADDR22 | input | TCELL86:IMUX.IMUX17 |
| SAXIGP1ARADDR23 | input | TCELL86:IMUX.IMUX18 |
| SAXIGP1ARADDR24 | input | TCELL87:IMUX.IMUX16 |
| SAXIGP1ARADDR25 | input | TCELL87:IMUX.IMUX17 |
| SAXIGP1ARADDR26 | input | TCELL87:IMUX.IMUX18 |
| SAXIGP1ARADDR27 | input | TCELL87:IMUX.IMUX19 |
| SAXIGP1ARADDR28 | input | TCELL88:IMUX.IMUX16 |
| SAXIGP1ARADDR29 | input | TCELL88:IMUX.IMUX17 |
| SAXIGP1ARADDR3 | input | TCELL81:IMUX.IMUX11 |
| SAXIGP1ARADDR30 | input | TCELL88:IMUX.IMUX18 |
| SAXIGP1ARADDR31 | input | TCELL88:IMUX.IMUX19 |
| SAXIGP1ARADDR4 | input | TCELL82:IMUX.IMUX9 |
| SAXIGP1ARADDR5 | input | TCELL82:IMUX.IMUX10 |
| SAXIGP1ARADDR6 | input | TCELL82:IMUX.IMUX11 |
| SAXIGP1ARADDR7 | input | TCELL82:IMUX.IMUX12 |
| SAXIGP1ARADDR8 | input | TCELL83:IMUX.IMUX12 |
| SAXIGP1ARADDR9 | input | TCELL83:IMUX.IMUX13 |
| SAXIGP1ARBURST0 | input | TCELL82:IMUX.IMUX13 |
| SAXIGP1ARBURST1 | input | TCELL82:IMUX.IMUX14 |
| SAXIGP1ARCACHE0 | input | TCELL81:IMUX.IMUX12 |
| SAXIGP1ARCACHE1 | input | TCELL81:IMUX.IMUX13 |
| SAXIGP1ARCACHE2 | input | TCELL81:IMUX.IMUX14 |
| SAXIGP1ARCACHE3 | input | TCELL81:IMUX.IMUX15 |
| SAXIGP1ARESETN | output | TCELL85:OUT8.TMIN |
| SAXIGP1ARID0 | input | TCELL83:IMUX.IMUX8 |
| SAXIGP1ARID1 | input | TCELL83:IMUX.IMUX9 |
| SAXIGP1ARID2 | input | TCELL83:IMUX.IMUX10 |
| SAXIGP1ARID3 | input | TCELL83:IMUX.IMUX11 |
| SAXIGP1ARID4 | input | TCELL84:IMUX.IMUX13 |
| SAXIGP1ARID5 | input | TCELL84:IMUX.IMUX14 |
| SAXIGP1ARLEN0 | input | TCELL83:IMUX.IMUX16 |
| SAXIGP1ARLEN1 | input | TCELL83:IMUX.IMUX17 |
| SAXIGP1ARLEN2 | input | TCELL83:IMUX.IMUX18 |
| SAXIGP1ARLEN3 | input | TCELL83:IMUX.IMUX19 |
| SAXIGP1ARLOCK0 | input | TCELL82:IMUX.IMUX15 |
| SAXIGP1ARLOCK1 | input | TCELL82:IMUX.IMUX16 |
| SAXIGP1ARPROT0 | input | TCELL81:IMUX.IMUX16 |
| SAXIGP1ARPROT1 | input | TCELL81:IMUX.IMUX17 |
| SAXIGP1ARPROT2 | input | TCELL81:IMUX.IMUX18 |
| SAXIGP1ARQOS0 | input | TCELL82:IMUX.IMUX17 |
| SAXIGP1ARQOS1 | input | TCELL82:IMUX.IMUX18 |
| SAXIGP1ARQOS2 | input | TCELL82:IMUX.IMUX19 |
| SAXIGP1ARQOS3 | input | TCELL82:IMUX.IMUX20 |
| SAXIGP1ARREADY | output | TCELL84:OUT8.TMIN |
| SAXIGP1ARSIZE0 | input | TCELL83:IMUX.IMUX20 |
| SAXIGP1ARSIZE1 | input | TCELL83:IMUX.IMUX21 |
| SAXIGP1ARVALID | input | TCELL84:IMUX.IMUX19 |
| SAXIGP1AWADDR0 | input | TCELL81:IMUX.IMUX0 |
| SAXIGP1AWADDR1 | input | TCELL81:IMUX.IMUX1 |
| SAXIGP1AWADDR10 | input | TCELL83:IMUX.IMUX2 |
| SAXIGP1AWADDR11 | input | TCELL83:IMUX.IMUX3 |
| SAXIGP1AWADDR12 | input | TCELL84:IMUX.IMUX0 |
| SAXIGP1AWADDR13 | input | TCELL84:IMUX.IMUX1 |
| SAXIGP1AWADDR14 | input | TCELL84:IMUX.IMUX2 |
| SAXIGP1AWADDR15 | input | TCELL84:IMUX.IMUX3 |
| SAXIGP1AWADDR16 | input | TCELL85:IMUX.IMUX0 |
| SAXIGP1AWADDR17 | input | TCELL85:IMUX.IMUX1 |
| SAXIGP1AWADDR18 | input | TCELL85:IMUX.IMUX2 |
| SAXIGP1AWADDR19 | input | TCELL85:IMUX.IMUX3 |
| SAXIGP1AWADDR2 | input | TCELL81:IMUX.IMUX2 |
| SAXIGP1AWADDR20 | input | TCELL86:IMUX.IMUX0 |
| SAXIGP1AWADDR21 | input | TCELL86:IMUX.IMUX1 |
| SAXIGP1AWADDR22 | input | TCELL86:IMUX.IMUX2 |
| SAXIGP1AWADDR23 | input | TCELL86:IMUX.IMUX3 |
| SAXIGP1AWADDR24 | input | TCELL87:IMUX.IMUX2 |
| SAXIGP1AWADDR25 | input | TCELL87:IMUX.IMUX3 |
| SAXIGP1AWADDR26 | input | TCELL87:IMUX.IMUX4 |
| SAXIGP1AWADDR27 | input | TCELL87:IMUX.IMUX5 |
| SAXIGP1AWADDR28 | input | TCELL88:IMUX.IMUX4 |
| SAXIGP1AWADDR29 | input | TCELL88:IMUX.IMUX5 |
| SAXIGP1AWADDR3 | input | TCELL81:IMUX.IMUX3 |
| SAXIGP1AWADDR30 | input | TCELL88:IMUX.IMUX6 |
| SAXIGP1AWADDR31 | input | TCELL88:IMUX.IMUX7 |
| SAXIGP1AWADDR4 | input | TCELL82:IMUX.IMUX0 |
| SAXIGP1AWADDR5 | input | TCELL82:IMUX.IMUX1 |
| SAXIGP1AWADDR6 | input | TCELL82:IMUX.IMUX2 |
| SAXIGP1AWADDR7 | input | TCELL82:IMUX.IMUX3 |
| SAXIGP1AWADDR8 | input | TCELL83:IMUX.IMUX0 |
| SAXIGP1AWADDR9 | input | TCELL83:IMUX.IMUX1 |
| SAXIGP1AWBURST0 | input | TCELL86:IMUX.IMUX4 |
| SAXIGP1AWBURST1 | input | TCELL86:IMUX.IMUX5 |
| SAXIGP1AWCACHE0 | input | TCELL85:IMUX.IMUX4 |
| SAXIGP1AWCACHE1 | input | TCELL85:IMUX.IMUX5 |
| SAXIGP1AWCACHE2 | input | TCELL86:IMUX.IMUX8 |
| SAXIGP1AWCACHE3 | input | TCELL86:IMUX.IMUX9 |
| SAXIGP1AWID0 | input | TCELL87:IMUX.IMUX0 |
| SAXIGP1AWID1 | input | TCELL87:IMUX.IMUX1 |
| SAXIGP1AWID2 | input | TCELL88:IMUX.IMUX0 |
| SAXIGP1AWID3 | input | TCELL88:IMUX.IMUX1 |
| SAXIGP1AWID4 | input | TCELL88:IMUX.IMUX2 |
| SAXIGP1AWID5 | input | TCELL88:IMUX.IMUX3 |
| SAXIGP1AWLEN0 | input | TCELL88:IMUX.IMUX8 |
| SAXIGP1AWLEN1 | input | TCELL88:IMUX.IMUX9 |
| SAXIGP1AWLEN2 | input | TCELL88:IMUX.IMUX10 |
| SAXIGP1AWLEN3 | input | TCELL88:IMUX.IMUX11 |
| SAXIGP1AWLOCK0 | input | TCELL86:IMUX.IMUX6 |
| SAXIGP1AWLOCK1 | input | TCELL86:IMUX.IMUX7 |
| SAXIGP1AWPROT0 | input | TCELL84:IMUX.IMUX4 |
| SAXIGP1AWPROT1 | input | TCELL84:IMUX.IMUX5 |
| SAXIGP1AWPROT2 | input | TCELL84:IMUX.IMUX6 |
| SAXIGP1AWQOS0 | input | TCELL86:IMUX.IMUX19 |
| SAXIGP1AWQOS1 | input | TCELL86:IMUX.IMUX20 |
| SAXIGP1AWQOS2 | input | TCELL86:IMUX.IMUX21 |
| SAXIGP1AWQOS3 | input | TCELL86:IMUX.IMUX22 |
| SAXIGP1AWREADY | output | TCELL85:OUT9.TMIN |
| SAXIGP1AWSIZE0 | input | TCELL87:IMUX.IMUX6 |
| SAXIGP1AWSIZE1 | input | TCELL87:IMUX.IMUX7 |
| SAXIGP1AWVALID | input | TCELL85:IMUX.IMUX6 |
| SAXIGP1BID0 | output | TCELL87:OUT8.TMIN |
| SAXIGP1BID1 | output | TCELL87:OUT9.TMIN |
| SAXIGP1BID2 | output | TCELL88:OUT8.TMIN |
| SAXIGP1BID3 | output | TCELL88:OUT9.TMIN |
| SAXIGP1BID4 | output | TCELL88:OUT10.TMIN |
| SAXIGP1BID5 | output | TCELL88:OUT11.TMIN |
| SAXIGP1BREADY | input | TCELL86:IMUX.IMUX14 |
| SAXIGP1BRESP0 | output | TCELL87:OUT10.TMIN |
| SAXIGP1BRESP1 | output | TCELL87:OUT11.TMIN |
| SAXIGP1BVALID | output | TCELL86:OUT8.TMIN |
| SAXIGP1RDATA0 | output | TCELL81:OUT12.TMIN |
| SAXIGP1RDATA1 | output | TCELL81:OUT13.TMIN |
| SAXIGP1RDATA10 | output | TCELL83:OUT10.TMIN |
| SAXIGP1RDATA11 | output | TCELL83:OUT11.TMIN |
| SAXIGP1RDATA12 | output | TCELL84:OUT9.TMIN |
| SAXIGP1RDATA13 | output | TCELL84:OUT10.TMIN |
| SAXIGP1RDATA14 | output | TCELL84:OUT11.TMIN |
| SAXIGP1RDATA15 | output | TCELL84:OUT12.TMIN |
| SAXIGP1RDATA16 | output | TCELL85:OUT11.TMIN |
| SAXIGP1RDATA17 | output | TCELL85:OUT12.TMIN |
| SAXIGP1RDATA18 | output | TCELL85:OUT13.TMIN |
| SAXIGP1RDATA19 | output | TCELL85:OUT14.TMIN |
| SAXIGP1RDATA2 | output | TCELL81:OUT14.TMIN |
| SAXIGP1RDATA20 | output | TCELL86:OUT9.TMIN |
| SAXIGP1RDATA21 | output | TCELL86:OUT10.TMIN |
| SAXIGP1RDATA22 | output | TCELL86:OUT11.TMIN |
| SAXIGP1RDATA23 | output | TCELL86:OUT12.TMIN |
| SAXIGP1RDATA24 | output | TCELL87:OUT12.TMIN |
| SAXIGP1RDATA25 | output | TCELL87:OUT13.TMIN |
| SAXIGP1RDATA26 | output | TCELL87:OUT14.TMIN |
| SAXIGP1RDATA27 | output | TCELL87:OUT15.TMIN |
| SAXIGP1RDATA28 | output | TCELL88:OUT12.TMIN |
| SAXIGP1RDATA29 | output | TCELL88:OUT13.TMIN |
| SAXIGP1RDATA3 | output | TCELL81:OUT15.TMIN |
| SAXIGP1RDATA30 | output | TCELL88:OUT14.TMIN |
| SAXIGP1RDATA31 | output | TCELL88:OUT15.TMIN |
| SAXIGP1RDATA4 | output | TCELL82:OUT10.TMIN |
| SAXIGP1RDATA5 | output | TCELL82:OUT11.TMIN |
| SAXIGP1RDATA6 | output | TCELL82:OUT12.TMIN |
| SAXIGP1RDATA7 | output | TCELL82:OUT13.TMIN |
| SAXIGP1RDATA8 | output | TCELL83:OUT8.TMIN |
| SAXIGP1RDATA9 | output | TCELL83:OUT9.TMIN |
| SAXIGP1RID0 | output | TCELL81:OUT8.TMIN |
| SAXIGP1RID1 | output | TCELL81:OUT9.TMIN |
| SAXIGP1RID2 | output | TCELL81:OUT10.TMIN |
| SAXIGP1RID3 | output | TCELL81:OUT11.TMIN |
| SAXIGP1RID4 | output | TCELL82:OUT8.TMIN |
| SAXIGP1RID5 | output | TCELL82:OUT9.TMIN |
| SAXIGP1RLAST | output | TCELL82:OUT14.TMIN |
| SAXIGP1RREADY | input | TCELL84:IMUX.IMUX20 |
| SAXIGP1RRESP0 | output | TCELL83:OUT12.TMIN |
| SAXIGP1RRESP1 | output | TCELL83:OUT13.TMIN |
| SAXIGP1RVALID | output | TCELL84:OUT13.TMIN |
| SAXIGP1WDATA0 | input | TCELL81:IMUX.IMUX4 |
| SAXIGP1WDATA1 | input | TCELL81:IMUX.IMUX5 |
| SAXIGP1WDATA10 | input | TCELL83:IMUX.IMUX6 |
| SAXIGP1WDATA11 | input | TCELL83:IMUX.IMUX7 |
| SAXIGP1WDATA12 | input | TCELL84:IMUX.IMUX9 |
| SAXIGP1WDATA13 | input | TCELL84:IMUX.IMUX10 |
| SAXIGP1WDATA14 | input | TCELL84:IMUX.IMUX11 |
| SAXIGP1WDATA15 | input | TCELL84:IMUX.IMUX12 |
| SAXIGP1WDATA16 | input | TCELL85:IMUX.IMUX11 |
| SAXIGP1WDATA17 | input | TCELL85:IMUX.IMUX12 |
| SAXIGP1WDATA18 | input | TCELL85:IMUX.IMUX13 |
| SAXIGP1WDATA19 | input | TCELL85:IMUX.IMUX14 |
| SAXIGP1WDATA2 | input | TCELL81:IMUX.IMUX6 |
| SAXIGP1WDATA20 | input | TCELL86:IMUX.IMUX10 |
| SAXIGP1WDATA21 | input | TCELL86:IMUX.IMUX11 |
| SAXIGP1WDATA22 | input | TCELL86:IMUX.IMUX12 |
| SAXIGP1WDATA23 | input | TCELL86:IMUX.IMUX13 |
| SAXIGP1WDATA24 | input | TCELL87:IMUX.IMUX8 |
| SAXIGP1WDATA25 | input | TCELL87:IMUX.IMUX9 |
| SAXIGP1WDATA26 | input | TCELL87:IMUX.IMUX10 |
| SAXIGP1WDATA27 | input | TCELL87:IMUX.IMUX11 |
| SAXIGP1WDATA28 | input | TCELL88:IMUX.IMUX12 |
| SAXIGP1WDATA29 | input | TCELL88:IMUX.IMUX13 |
| SAXIGP1WDATA3 | input | TCELL81:IMUX.IMUX7 |
| SAXIGP1WDATA30 | input | TCELL88:IMUX.IMUX14 |
| SAXIGP1WDATA31 | input | TCELL88:IMUX.IMUX15 |
| SAXIGP1WDATA4 | input | TCELL82:IMUX.IMUX4 |
| SAXIGP1WDATA5 | input | TCELL82:IMUX.IMUX5 |
| SAXIGP1WDATA6 | input | TCELL82:IMUX.IMUX6 |
| SAXIGP1WDATA7 | input | TCELL82:IMUX.IMUX7 |
| SAXIGP1WDATA8 | input | TCELL83:IMUX.IMUX4 |
| SAXIGP1WDATA9 | input | TCELL83:IMUX.IMUX5 |
| SAXIGP1WID0 | input | TCELL84:IMUX.IMUX7 |
| SAXIGP1WID1 | input | TCELL84:IMUX.IMUX8 |
| SAXIGP1WID2 | input | TCELL85:IMUX.IMUX7 |
| SAXIGP1WID3 | input | TCELL85:IMUX.IMUX8 |
| SAXIGP1WID4 | input | TCELL85:IMUX.IMUX9 |
| SAXIGP1WID5 | input | TCELL85:IMUX.IMUX10 |
| SAXIGP1WLAST | input | TCELL82:IMUX.IMUX8 |
| SAXIGP1WREADY | output | TCELL85:OUT10.TMIN |
| SAXIGP1WSTRB0 | input | TCELL87:IMUX.IMUX12 |
| SAXIGP1WSTRB1 | input | TCELL87:IMUX.IMUX13 |
| SAXIGP1WSTRB2 | input | TCELL87:IMUX.IMUX14 |
| SAXIGP1WSTRB3 | input | TCELL87:IMUX.IMUX15 |
| SAXIGP1WVALID | input | TCELL85:IMUX.IMUX15 |
| SAXIHP0ACLK | input | TCELL4:IMUX.CLK0 |
| SAXIHP0ARADDR0 | input | TCELL0:IMUX.IMUX16 |
| SAXIHP0ARADDR1 | input | TCELL0:IMUX.IMUX17 |
| SAXIHP0ARADDR10 | input | TCELL2:IMUX.IMUX19 |
| SAXIHP0ARADDR11 | input | TCELL2:IMUX.IMUX20 |
| SAXIHP0ARADDR12 | input | TCELL3:IMUX.IMUX16 |
| SAXIHP0ARADDR13 | input | TCELL3:IMUX.IMUX17 |
| SAXIHP0ARADDR14 | input | TCELL3:IMUX.IMUX18 |
| SAXIHP0ARADDR15 | input | TCELL3:IMUX.IMUX19 |
| SAXIHP0ARADDR16 | input | TCELL4:IMUX.IMUX22 |
| SAXIHP0ARADDR17 | input | TCELL4:IMUX.IMUX23 |
| SAXIHP0ARADDR18 | input | TCELL4:IMUX.IMUX24 |
| SAXIHP0ARADDR19 | input | TCELL4:IMUX.IMUX25 |
| SAXIHP0ARADDR2 | input | TCELL0:IMUX.IMUX18 |
| SAXIHP0ARADDR20 | input | TCELL5:IMUX.IMUX21 |
| SAXIHP0ARADDR21 | input | TCELL5:IMUX.IMUX22 |
| SAXIHP0ARADDR22 | input | TCELL5:IMUX.IMUX23 |
| SAXIHP0ARADDR23 | input | TCELL5:IMUX.IMUX24 |
| SAXIHP0ARADDR24 | input | TCELL6:IMUX.IMUX19 |
| SAXIHP0ARADDR25 | input | TCELL6:IMUX.IMUX20 |
| SAXIHP0ARADDR26 | input | TCELL6:IMUX.IMUX21 |
| SAXIHP0ARADDR27 | input | TCELL6:IMUX.IMUX22 |
| SAXIHP0ARADDR28 | input | TCELL7:IMUX.IMUX18 |
| SAXIHP0ARADDR29 | input | TCELL7:IMUX.IMUX19 |
| SAXIHP0ARADDR3 | input | TCELL0:IMUX.IMUX19 |
| SAXIHP0ARADDR30 | input | TCELL7:IMUX.IMUX20 |
| SAXIHP0ARADDR31 | input | TCELL7:IMUX.IMUX21 |
| SAXIHP0ARADDR4 | input | TCELL1:IMUX.IMUX14 |
| SAXIHP0ARADDR5 | input | TCELL1:IMUX.IMUX15 |
| SAXIHP0ARADDR6 | input | TCELL1:IMUX.IMUX16 |
| SAXIHP0ARADDR7 | input | TCELL1:IMUX.IMUX17 |
| SAXIHP0ARADDR8 | input | TCELL2:IMUX.IMUX17 |
| SAXIHP0ARADDR9 | input | TCELL2:IMUX.IMUX18 |
| SAXIHP0ARBURST0 | input | TCELL0:IMUX.IMUX22 |
| SAXIHP0ARBURST1 | input | TCELL0:IMUX.IMUX23 |
| SAXIHP0ARCACHE0 | input | TCELL1:IMUX.IMUX19 |
| SAXIHP0ARCACHE1 | input | TCELL1:IMUX.IMUX20 |
| SAXIHP0ARCACHE2 | input | TCELL1:IMUX.IMUX21 |
| SAXIHP0ARCACHE3 | input | TCELL1:IMUX.IMUX22 |
| SAXIHP0ARESETN | output | TCELL7:OUT0.TMIN |
| SAXIHP0ARID0 | input | TCELL0:IMUX.IMUX12 |
| SAXIHP0ARID1 | input | TCELL0:IMUX.IMUX13 |
| SAXIHP0ARID2 | input | TCELL0:IMUX.IMUX14 |
| SAXIHP0ARID3 | input | TCELL0:IMUX.IMUX15 |
| SAXIHP0ARID4 | input | TCELL1:IMUX.IMUX12 |
| SAXIHP0ARID5 | input | TCELL1:IMUX.IMUX13 |
| SAXIHP0ARLEN0 | input | TCELL2:IMUX.IMUX21 |
| SAXIHP0ARLEN1 | input | TCELL2:IMUX.IMUX22 |
| SAXIHP0ARLEN2 | input | TCELL2:IMUX.IMUX23 |
| SAXIHP0ARLEN3 | input | TCELL2:IMUX.IMUX24 |
| SAXIHP0ARLOCK0 | input | TCELL0:IMUX.IMUX24 |
| SAXIHP0ARLOCK1 | input | TCELL1:IMUX.IMUX18 |
| SAXIHP0ARPROT0 | input | TCELL1:IMUX.IMUX23 |
| SAXIHP0ARPROT1 | input | TCELL1:IMUX.IMUX24 |
| SAXIHP0ARPROT2 | input | TCELL2:IMUX.IMUX25 |
| SAXIHP0ARQOS0 | input | TCELL3:IMUX.IMUX22 |
| SAXIHP0ARQOS1 | input | TCELL3:IMUX.IMUX23 |
| SAXIHP0ARQOS2 | input | TCELL3:IMUX.IMUX24 |
| SAXIHP0ARQOS3 | input | TCELL3:IMUX.IMUX25 |
| SAXIHP0ARREADY | output | TCELL3:OUT0.TMIN |
| SAXIHP0ARSIZE0 | input | TCELL0:IMUX.IMUX20 |
| SAXIHP0ARSIZE1 | input | TCELL0:IMUX.IMUX21 |
| SAXIHP0ARVALID | input | TCELL3:IMUX.IMUX20 |
| SAXIHP0AWADDR0 | input | TCELL0:IMUX.IMUX0 |
| SAXIHP0AWADDR1 | input | TCELL0:IMUX.IMUX1 |
| SAXIHP0AWADDR10 | input | TCELL2:IMUX.IMUX2 |
| SAXIHP0AWADDR11 | input | TCELL2:IMUX.IMUX3 |
| SAXIHP0AWADDR12 | input | TCELL3:IMUX.IMUX0 |
| SAXIHP0AWADDR13 | input | TCELL3:IMUX.IMUX1 |
| SAXIHP0AWADDR14 | input | TCELL3:IMUX.IMUX2 |
| SAXIHP0AWADDR15 | input | TCELL3:IMUX.IMUX3 |
| SAXIHP0AWADDR16 | input | TCELL4:IMUX.IMUX0 |
| SAXIHP0AWADDR17 | input | TCELL4:IMUX.IMUX1 |
| SAXIHP0AWADDR18 | input | TCELL4:IMUX.IMUX2 |
| SAXIHP0AWADDR19 | input | TCELL4:IMUX.IMUX3 |
| SAXIHP0AWADDR2 | input | TCELL0:IMUX.IMUX2 |
| SAXIHP0AWADDR20 | input | TCELL5:IMUX.IMUX0 |
| SAXIHP0AWADDR21 | input | TCELL5:IMUX.IMUX1 |
| SAXIHP0AWADDR22 | input | TCELL5:IMUX.IMUX2 |
| SAXIHP0AWADDR23 | input | TCELL5:IMUX.IMUX3 |
| SAXIHP0AWADDR24 | input | TCELL6:IMUX.IMUX4 |
| SAXIHP0AWADDR25 | input | TCELL6:IMUX.IMUX5 |
| SAXIHP0AWADDR26 | input | TCELL6:IMUX.IMUX6 |
| SAXIHP0AWADDR27 | input | TCELL6:IMUX.IMUX7 |
| SAXIHP0AWADDR28 | input | TCELL7:IMUX.IMUX2 |
| SAXIHP0AWADDR29 | input | TCELL7:IMUX.IMUX3 |
| SAXIHP0AWADDR3 | input | TCELL0:IMUX.IMUX3 |
| SAXIHP0AWADDR30 | input | TCELL7:IMUX.IMUX4 |
| SAXIHP0AWADDR31 | input | TCELL7:IMUX.IMUX5 |
| SAXIHP0AWADDR4 | input | TCELL1:IMUX.IMUX0 |
| SAXIHP0AWADDR5 | input | TCELL1:IMUX.IMUX1 |
| SAXIHP0AWADDR6 | input | TCELL1:IMUX.IMUX2 |
| SAXIHP0AWADDR7 | input | TCELL1:IMUX.IMUX3 |
| SAXIHP0AWADDR8 | input | TCELL2:IMUX.IMUX0 |
| SAXIHP0AWADDR9 | input | TCELL2:IMUX.IMUX1 |
| SAXIHP0AWBURST0 | input | TCELL5:IMUX.IMUX4 |
| SAXIHP0AWBURST1 | input | TCELL6:IMUX.IMUX10 |
| SAXIHP0AWCACHE0 | input | TCELL4:IMUX.IMUX4 |
| SAXIHP0AWCACHE1 | input | TCELL4:IMUX.IMUX5 |
| SAXIHP0AWCACHE2 | input | TCELL5:IMUX.IMUX7 |
| SAXIHP0AWCACHE3 | input | TCELL5:IMUX.IMUX8 |
| SAXIHP0AWID0 | input | TCELL6:IMUX.IMUX0 |
| SAXIHP0AWID1 | input | TCELL6:IMUX.IMUX1 |
| SAXIHP0AWID2 | input | TCELL6:IMUX.IMUX2 |
| SAXIHP0AWID3 | input | TCELL6:IMUX.IMUX3 |
| SAXIHP0AWID4 | input | TCELL7:IMUX.IMUX0 |
| SAXIHP0AWID5 | input | TCELL7:IMUX.IMUX1 |
| SAXIHP0AWLEN0 | input | TCELL7:IMUX.IMUX6 |
| SAXIHP0AWLEN1 | input | TCELL7:IMUX.IMUX7 |
| SAXIHP0AWLEN2 | input | TCELL7:IMUX.IMUX8 |
| SAXIHP0AWLEN3 | input | TCELL7:IMUX.IMUX9 |
| SAXIHP0AWLOCK0 | input | TCELL5:IMUX.IMUX5 |
| SAXIHP0AWLOCK1 | input | TCELL5:IMUX.IMUX6 |
| SAXIHP0AWPROT0 | input | TCELL4:IMUX.IMUX6 |
| SAXIHP0AWPROT1 | input | TCELL4:IMUX.IMUX7 |
| SAXIHP0AWPROT2 | input | TCELL4:IMUX.IMUX8 |
| SAXIHP0AWQOS0 | input | TCELL6:IMUX.IMUX23 |
| SAXIHP0AWQOS1 | input | TCELL6:IMUX.IMUX24 |
| SAXIHP0AWQOS2 | input | TCELL7:IMUX.IMUX23 |
| SAXIHP0AWQOS3 | input | TCELL7:IMUX.IMUX24 |
| SAXIHP0AWREADY | output | TCELL4:OUT0.TMIN |
| SAXIHP0AWSIZE0 | input | TCELL6:IMUX.IMUX8 |
| SAXIHP0AWSIZE1 | input | TCELL6:IMUX.IMUX9 |
| SAXIHP0AWVALID | input | TCELL4:IMUX.IMUX9 |
| SAXIHP0BID0 | output | TCELL4:OUT2.TMIN |
| SAXIHP0BID1 | output | TCELL4:OUT3.TMIN |
| SAXIHP0BID2 | output | TCELL5:OUT0.TMIN |
| SAXIHP0BID3 | output | TCELL5:OUT1.TMIN |
| SAXIHP0BID4 | output | TCELL5:OUT2.TMIN |
| SAXIHP0BID5 | output | TCELL5:OUT3.TMIN |
| SAXIHP0BREADY | input | TCELL4:IMUX.IMUX21 |
| SAXIHP0BRESP0 | output | TCELL2:OUT0.TMIN |
| SAXIHP0BRESP1 | output | TCELL2:OUT1.TMIN |
| SAXIHP0BVALID | output | TCELL4:OUT4.TMIN |
| SAXIHP0RACOUNT0 | output | TCELL0:OUT11.TMIN |
| SAXIHP0RACOUNT1 | output | TCELL0:OUT12.TMIN |
| SAXIHP0RACOUNT2 | output | TCELL0:OUT13.TMIN |
| SAXIHP0RCOUNT0 | output | TCELL1:OUT11.TMIN |
| SAXIHP0RCOUNT1 | output | TCELL1:OUT12.TMIN |
| SAXIHP0RCOUNT2 | output | TCELL1:OUT13.TMIN |
| SAXIHP0RCOUNT3 | output | TCELL1:OUT14.TMIN |
| SAXIHP0RCOUNT4 | output | TCELL2:OUT10.TMIN |
| SAXIHP0RCOUNT5 | output | TCELL2:OUT11.TMIN |
| SAXIHP0RCOUNT6 | output | TCELL2:OUT12.TMIN |
| SAXIHP0RCOUNT7 | output | TCELL2:OUT13.TMIN |
| SAXIHP0RDATA0 | output | TCELL0:OUT3.TMIN |
| SAXIHP0RDATA1 | output | TCELL0:OUT4.TMIN |
| SAXIHP0RDATA10 | output | TCELL2:OUT4.TMIN |
| SAXIHP0RDATA11 | output | TCELL2:OUT5.TMIN |
| SAXIHP0RDATA12 | output | TCELL3:OUT1.TMIN |
| SAXIHP0RDATA13 | output | TCELL3:OUT2.TMIN |
| SAXIHP0RDATA14 | output | TCELL3:OUT3.TMIN |
| SAXIHP0RDATA15 | output | TCELL3:OUT4.TMIN |
| SAXIHP0RDATA16 | output | TCELL4:OUT5.TMIN |
| SAXIHP0RDATA17 | output | TCELL4:OUT6.TMIN |
| SAXIHP0RDATA18 | output | TCELL4:OUT7.TMIN |
| SAXIHP0RDATA19 | output | TCELL4:OUT8.TMIN |
| SAXIHP0RDATA2 | output | TCELL0:OUT5.TMIN |
| SAXIHP0RDATA20 | output | TCELL5:OUT4.TMIN |
| SAXIHP0RDATA21 | output | TCELL5:OUT5.TMIN |
| SAXIHP0RDATA22 | output | TCELL5:OUT6.TMIN |
| SAXIHP0RDATA23 | output | TCELL5:OUT7.TMIN |
| SAXIHP0RDATA24 | output | TCELL6:OUT0.TMIN |
| SAXIHP0RDATA25 | output | TCELL6:OUT1.TMIN |
| SAXIHP0RDATA26 | output | TCELL6:OUT2.TMIN |
| SAXIHP0RDATA27 | output | TCELL6:OUT3.TMIN |
| SAXIHP0RDATA28 | output | TCELL7:OUT1.TMIN |
| SAXIHP0RDATA29 | output | TCELL7:OUT2.TMIN |
| SAXIHP0RDATA3 | output | TCELL0:OUT6.TMIN |
| SAXIHP0RDATA30 | output | TCELL7:OUT3.TMIN |
| SAXIHP0RDATA31 | output | TCELL7:OUT4.TMIN |
| SAXIHP0RDATA32 | output | TCELL0:OUT7.TMIN |
| SAXIHP0RDATA33 | output | TCELL0:OUT8.TMIN |
| SAXIHP0RDATA34 | output | TCELL0:OUT9.TMIN |
| SAXIHP0RDATA35 | output | TCELL0:OUT10.TMIN |
| SAXIHP0RDATA36 | output | TCELL1:OUT7.TMIN |
| SAXIHP0RDATA37 | output | TCELL1:OUT8.TMIN |
| SAXIHP0RDATA38 | output | TCELL1:OUT9.TMIN |
| SAXIHP0RDATA39 | output | TCELL1:OUT10.TMIN |
| SAXIHP0RDATA4 | output | TCELL1:OUT3.TMIN |
| SAXIHP0RDATA40 | output | TCELL2:OUT6.TMIN |
| SAXIHP0RDATA41 | output | TCELL2:OUT7.TMIN |
| SAXIHP0RDATA42 | output | TCELL2:OUT8.TMIN |
| SAXIHP0RDATA43 | output | TCELL2:OUT9.TMIN |
| SAXIHP0RDATA44 | output | TCELL3:OUT5.TMIN |
| SAXIHP0RDATA45 | output | TCELL3:OUT6.TMIN |
| SAXIHP0RDATA46 | output | TCELL3:OUT7.TMIN |
| SAXIHP0RDATA47 | output | TCELL3:OUT8.TMIN |
| SAXIHP0RDATA48 | output | TCELL4:OUT9.TMIN |
| SAXIHP0RDATA49 | output | TCELL4:OUT10.TMIN |
| SAXIHP0RDATA5 | output | TCELL1:OUT4.TMIN |
| SAXIHP0RDATA50 | output | TCELL4:OUT11.TMIN |
| SAXIHP0RDATA51 | output | TCELL4:OUT12.TMIN |
| SAXIHP0RDATA52 | output | TCELL5:OUT8.TMIN |
| SAXIHP0RDATA53 | output | TCELL5:OUT9.TMIN |
| SAXIHP0RDATA54 | output | TCELL5:OUT10.TMIN |
| SAXIHP0RDATA55 | output | TCELL5:OUT11.TMIN |
| SAXIHP0RDATA56 | output | TCELL6:OUT4.TMIN |
| SAXIHP0RDATA57 | output | TCELL6:OUT5.TMIN |
| SAXIHP0RDATA58 | output | TCELL6:OUT6.TMIN |
| SAXIHP0RDATA59 | output | TCELL6:OUT7.TMIN |
| SAXIHP0RDATA6 | output | TCELL1:OUT5.TMIN |
| SAXIHP0RDATA60 | output | TCELL7:OUT5.TMIN |
| SAXIHP0RDATA61 | output | TCELL7:OUT6.TMIN |
| SAXIHP0RDATA62 | output | TCELL7:OUT7.TMIN |
| SAXIHP0RDATA63 | output | TCELL7:OUT8.TMIN |
| SAXIHP0RDATA7 | output | TCELL1:OUT6.TMIN |
| SAXIHP0RDATA8 | output | TCELL2:OUT2.TMIN |
| SAXIHP0RDATA9 | output | TCELL2:OUT3.TMIN |
| SAXIHP0RDISSUECAP1EN | input | TCELL0:IMUX.IMUX25 |
| SAXIHP0RID0 | output | TCELL0:OUT0.TMIN |
| SAXIHP0RID1 | output | TCELL0:OUT1.TMIN |
| SAXIHP0RID2 | output | TCELL0:OUT2.TMIN |
| SAXIHP0RID3 | output | TCELL1:OUT0.TMIN |
| SAXIHP0RID4 | output | TCELL1:OUT1.TMIN |
| SAXIHP0RID5 | output | TCELL1:OUT2.TMIN |
| SAXIHP0RLAST | output | TCELL3:OUT11.TMIN |
| SAXIHP0RREADY | input | TCELL3:IMUX.IMUX21 |
| SAXIHP0RRESP0 | output | TCELL3:OUT9.TMIN |
| SAXIHP0RRESP1 | output | TCELL3:OUT10.TMIN |
| SAXIHP0RVALID | output | TCELL3:OUT12.TMIN |
| SAXIHP0WACOUNT0 | output | TCELL5:OUT12.TMIN |
| SAXIHP0WACOUNT1 | output | TCELL5:OUT13.TMIN |
| SAXIHP0WACOUNT2 | output | TCELL6:OUT12.TMIN |
| SAXIHP0WACOUNT3 | output | TCELL6:OUT13.TMIN |
| SAXIHP0WACOUNT4 | output | TCELL7:OUT13.TMIN |
| SAXIHP0WACOUNT5 | output | TCELL7:OUT14.TMIN |
| SAXIHP0WCOUNT0 | output | TCELL6:OUT8.TMIN |
| SAXIHP0WCOUNT1 | output | TCELL6:OUT9.TMIN |
| SAXIHP0WCOUNT2 | output | TCELL6:OUT10.TMIN |
| SAXIHP0WCOUNT3 | output | TCELL6:OUT11.TMIN |
| SAXIHP0WCOUNT4 | output | TCELL7:OUT9.TMIN |
| SAXIHP0WCOUNT5 | output | TCELL7:OUT10.TMIN |
| SAXIHP0WCOUNT6 | output | TCELL7:OUT11.TMIN |
| SAXIHP0WCOUNT7 | output | TCELL7:OUT12.TMIN |
| SAXIHP0WDATA0 | input | TCELL0:IMUX.IMUX4 |
| SAXIHP0WDATA1 | input | TCELL0:IMUX.IMUX5 |
| SAXIHP0WDATA10 | input | TCELL2:IMUX.IMUX6 |
| SAXIHP0WDATA11 | input | TCELL2:IMUX.IMUX7 |
| SAXIHP0WDATA12 | input | TCELL3:IMUX.IMUX4 |
| SAXIHP0WDATA13 | input | TCELL3:IMUX.IMUX5 |
| SAXIHP0WDATA14 | input | TCELL3:IMUX.IMUX6 |
| SAXIHP0WDATA15 | input | TCELL3:IMUX.IMUX7 |
| SAXIHP0WDATA16 | input | TCELL4:IMUX.IMUX12 |
| SAXIHP0WDATA17 | input | TCELL4:IMUX.IMUX13 |
| SAXIHP0WDATA18 | input | TCELL4:IMUX.IMUX14 |
| SAXIHP0WDATA19 | input | TCELL4:IMUX.IMUX15 |
| SAXIHP0WDATA2 | input | TCELL0:IMUX.IMUX6 |
| SAXIHP0WDATA20 | input | TCELL5:IMUX.IMUX13 |
| SAXIHP0WDATA21 | input | TCELL5:IMUX.IMUX14 |
| SAXIHP0WDATA22 | input | TCELL5:IMUX.IMUX15 |
| SAXIHP0WDATA23 | input | TCELL5:IMUX.IMUX16 |
| SAXIHP0WDATA24 | input | TCELL6:IMUX.IMUX11 |
| SAXIHP0WDATA25 | input | TCELL6:IMUX.IMUX12 |
| SAXIHP0WDATA26 | input | TCELL6:IMUX.IMUX13 |
| SAXIHP0WDATA27 | input | TCELL6:IMUX.IMUX14 |
| SAXIHP0WDATA28 | input | TCELL7:IMUX.IMUX10 |
| SAXIHP0WDATA29 | input | TCELL7:IMUX.IMUX11 |
| SAXIHP0WDATA3 | input | TCELL0:IMUX.IMUX7 |
| SAXIHP0WDATA30 | input | TCELL7:IMUX.IMUX12 |
| SAXIHP0WDATA31 | input | TCELL7:IMUX.IMUX13 |
| SAXIHP0WDATA32 | input | TCELL0:IMUX.IMUX8 |
| SAXIHP0WDATA33 | input | TCELL0:IMUX.IMUX9 |
| SAXIHP0WDATA34 | input | TCELL0:IMUX.IMUX10 |
| SAXIHP0WDATA35 | input | TCELL0:IMUX.IMUX11 |
| SAXIHP0WDATA36 | input | TCELL1:IMUX.IMUX8 |
| SAXIHP0WDATA37 | input | TCELL1:IMUX.IMUX9 |
| SAXIHP0WDATA38 | input | TCELL1:IMUX.IMUX10 |
| SAXIHP0WDATA39 | input | TCELL1:IMUX.IMUX11 |
| SAXIHP0WDATA4 | input | TCELL1:IMUX.IMUX4 |
| SAXIHP0WDATA40 | input | TCELL2:IMUX.IMUX8 |
| SAXIHP0WDATA41 | input | TCELL2:IMUX.IMUX9 |
| SAXIHP0WDATA42 | input | TCELL2:IMUX.IMUX10 |
| SAXIHP0WDATA43 | input | TCELL2:IMUX.IMUX11 |
| SAXIHP0WDATA44 | input | TCELL3:IMUX.IMUX8 |
| SAXIHP0WDATA45 | input | TCELL3:IMUX.IMUX9 |
| SAXIHP0WDATA46 | input | TCELL3:IMUX.IMUX10 |
| SAXIHP0WDATA47 | input | TCELL3:IMUX.IMUX11 |
| SAXIHP0WDATA48 | input | TCELL4:IMUX.IMUX16 |
| SAXIHP0WDATA49 | input | TCELL4:IMUX.IMUX17 |
| SAXIHP0WDATA5 | input | TCELL1:IMUX.IMUX5 |
| SAXIHP0WDATA50 | input | TCELL4:IMUX.IMUX18 |
| SAXIHP0WDATA51 | input | TCELL4:IMUX.IMUX19 |
| SAXIHP0WDATA52 | input | TCELL5:IMUX.IMUX17 |
| SAXIHP0WDATA53 | input | TCELL5:IMUX.IMUX18 |
| SAXIHP0WDATA54 | input | TCELL5:IMUX.IMUX19 |
| SAXIHP0WDATA55 | input | TCELL5:IMUX.IMUX20 |
| SAXIHP0WDATA56 | input | TCELL6:IMUX.IMUX15 |
| SAXIHP0WDATA57 | input | TCELL6:IMUX.IMUX16 |
| SAXIHP0WDATA58 | input | TCELL6:IMUX.IMUX17 |
| SAXIHP0WDATA59 | input | TCELL6:IMUX.IMUX18 |
| SAXIHP0WDATA6 | input | TCELL1:IMUX.IMUX6 |
| SAXIHP0WDATA60 | input | TCELL7:IMUX.IMUX14 |
| SAXIHP0WDATA61 | input | TCELL7:IMUX.IMUX15 |
| SAXIHP0WDATA62 | input | TCELL7:IMUX.IMUX16 |
| SAXIHP0WDATA63 | input | TCELL7:IMUX.IMUX17 |
| SAXIHP0WDATA7 | input | TCELL1:IMUX.IMUX7 |
| SAXIHP0WDATA8 | input | TCELL2:IMUX.IMUX4 |
| SAXIHP0WDATA9 | input | TCELL2:IMUX.IMUX5 |
| SAXIHP0WID0 | input | TCELL4:IMUX.IMUX10 |
| SAXIHP0WID1 | input | TCELL4:IMUX.IMUX11 |
| SAXIHP0WID2 | input | TCELL5:IMUX.IMUX9 |
| SAXIHP0WID3 | input | TCELL5:IMUX.IMUX10 |
| SAXIHP0WID4 | input | TCELL5:IMUX.IMUX11 |
| SAXIHP0WID5 | input | TCELL5:IMUX.IMUX12 |
| SAXIHP0WLAST | input | TCELL2:IMUX.IMUX16 |
| SAXIHP0WREADY | output | TCELL4:OUT1.TMIN |
| SAXIHP0WRISSUECAP1EN | input | TCELL7:IMUX.IMUX22 |
| SAXIHP0WSTRB0 | input | TCELL2:IMUX.IMUX12 |
| SAXIHP0WSTRB1 | input | TCELL2:IMUX.IMUX13 |
| SAXIHP0WSTRB2 | input | TCELL2:IMUX.IMUX14 |
| SAXIHP0WSTRB3 | input | TCELL2:IMUX.IMUX15 |
| SAXIHP0WSTRB4 | input | TCELL3:IMUX.IMUX12 |
| SAXIHP0WSTRB5 | input | TCELL3:IMUX.IMUX13 |
| SAXIHP0WSTRB6 | input | TCELL3:IMUX.IMUX14 |
| SAXIHP0WSTRB7 | input | TCELL3:IMUX.IMUX15 |
| SAXIHP0WVALID | input | TCELL4:IMUX.IMUX20 |
| SAXIHP1ACLK | input | TCELL12:IMUX.CLK0 |
| SAXIHP1ARADDR0 | input | TCELL8:IMUX.IMUX16 |
| SAXIHP1ARADDR1 | input | TCELL8:IMUX.IMUX17 |
| SAXIHP1ARADDR10 | input | TCELL10:IMUX.IMUX19 |
| SAXIHP1ARADDR11 | input | TCELL10:IMUX.IMUX20 |
| SAXIHP1ARADDR12 | input | TCELL11:IMUX.IMUX16 |
| SAXIHP1ARADDR13 | input | TCELL11:IMUX.IMUX17 |
| SAXIHP1ARADDR14 | input | TCELL11:IMUX.IMUX18 |
| SAXIHP1ARADDR15 | input | TCELL11:IMUX.IMUX19 |
| SAXIHP1ARADDR16 | input | TCELL12:IMUX.IMUX22 |
| SAXIHP1ARADDR17 | input | TCELL12:IMUX.IMUX23 |
| SAXIHP1ARADDR18 | input | TCELL12:IMUX.IMUX24 |
| SAXIHP1ARADDR19 | input | TCELL12:IMUX.IMUX25 |
| SAXIHP1ARADDR2 | input | TCELL8:IMUX.IMUX18 |
| SAXIHP1ARADDR20 | input | TCELL13:IMUX.IMUX21 |
| SAXIHP1ARADDR21 | input | TCELL13:IMUX.IMUX22 |
| SAXIHP1ARADDR22 | input | TCELL13:IMUX.IMUX23 |
| SAXIHP1ARADDR23 | input | TCELL13:IMUX.IMUX24 |
| SAXIHP1ARADDR24 | input | TCELL14:IMUX.IMUX19 |
| SAXIHP1ARADDR25 | input | TCELL14:IMUX.IMUX20 |
| SAXIHP1ARADDR26 | input | TCELL14:IMUX.IMUX21 |
| SAXIHP1ARADDR27 | input | TCELL14:IMUX.IMUX22 |
| SAXIHP1ARADDR28 | input | TCELL15:IMUX.IMUX18 |
| SAXIHP1ARADDR29 | input | TCELL15:IMUX.IMUX19 |
| SAXIHP1ARADDR3 | input | TCELL8:IMUX.IMUX19 |
| SAXIHP1ARADDR30 | input | TCELL15:IMUX.IMUX20 |
| SAXIHP1ARADDR31 | input | TCELL15:IMUX.IMUX21 |
| SAXIHP1ARADDR4 | input | TCELL9:IMUX.IMUX14 |
| SAXIHP1ARADDR5 | input | TCELL9:IMUX.IMUX15 |
| SAXIHP1ARADDR6 | input | TCELL9:IMUX.IMUX16 |
| SAXIHP1ARADDR7 | input | TCELL9:IMUX.IMUX17 |
| SAXIHP1ARADDR8 | input | TCELL10:IMUX.IMUX17 |
| SAXIHP1ARADDR9 | input | TCELL10:IMUX.IMUX18 |
| SAXIHP1ARBURST0 | input | TCELL8:IMUX.IMUX22 |
| SAXIHP1ARBURST1 | input | TCELL8:IMUX.IMUX23 |
| SAXIHP1ARCACHE0 | input | TCELL9:IMUX.IMUX19 |
| SAXIHP1ARCACHE1 | input | TCELL9:IMUX.IMUX20 |
| SAXIHP1ARCACHE2 | input | TCELL9:IMUX.IMUX21 |
| SAXIHP1ARCACHE3 | input | TCELL9:IMUX.IMUX22 |
| SAXIHP1ARESETN | output | TCELL15:OUT0.TMIN |
| SAXIHP1ARID0 | input | TCELL8:IMUX.IMUX12 |
| SAXIHP1ARID1 | input | TCELL8:IMUX.IMUX13 |
| SAXIHP1ARID2 | input | TCELL8:IMUX.IMUX14 |
| SAXIHP1ARID3 | input | TCELL8:IMUX.IMUX15 |
| SAXIHP1ARID4 | input | TCELL9:IMUX.IMUX12 |
| SAXIHP1ARID5 | input | TCELL9:IMUX.IMUX13 |
| SAXIHP1ARLEN0 | input | TCELL10:IMUX.IMUX21 |
| SAXIHP1ARLEN1 | input | TCELL10:IMUX.IMUX22 |
| SAXIHP1ARLEN2 | input | TCELL10:IMUX.IMUX23 |
| SAXIHP1ARLEN3 | input | TCELL10:IMUX.IMUX24 |
| SAXIHP1ARLOCK0 | input | TCELL8:IMUX.IMUX24 |
| SAXIHP1ARLOCK1 | input | TCELL9:IMUX.IMUX18 |
| SAXIHP1ARPROT0 | input | TCELL9:IMUX.IMUX23 |
| SAXIHP1ARPROT1 | input | TCELL9:IMUX.IMUX24 |
| SAXIHP1ARPROT2 | input | TCELL10:IMUX.IMUX25 |
| SAXIHP1ARQOS0 | input | TCELL11:IMUX.IMUX22 |
| SAXIHP1ARQOS1 | input | TCELL11:IMUX.IMUX23 |
| SAXIHP1ARQOS2 | input | TCELL11:IMUX.IMUX24 |
| SAXIHP1ARQOS3 | input | TCELL11:IMUX.IMUX25 |
| SAXIHP1ARREADY | output | TCELL11:OUT0.TMIN |
| SAXIHP1ARSIZE0 | input | TCELL8:IMUX.IMUX20 |
| SAXIHP1ARSIZE1 | input | TCELL8:IMUX.IMUX21 |
| SAXIHP1ARVALID | input | TCELL11:IMUX.IMUX20 |
| SAXIHP1AWADDR0 | input | TCELL8:IMUX.IMUX0 |
| SAXIHP1AWADDR1 | input | TCELL8:IMUX.IMUX1 |
| SAXIHP1AWADDR10 | input | TCELL10:IMUX.IMUX2 |
| SAXIHP1AWADDR11 | input | TCELL10:IMUX.IMUX3 |
| SAXIHP1AWADDR12 | input | TCELL11:IMUX.IMUX0 |
| SAXIHP1AWADDR13 | input | TCELL11:IMUX.IMUX1 |
| SAXIHP1AWADDR14 | input | TCELL11:IMUX.IMUX2 |
| SAXIHP1AWADDR15 | input | TCELL11:IMUX.IMUX3 |
| SAXIHP1AWADDR16 | input | TCELL12:IMUX.IMUX0 |
| SAXIHP1AWADDR17 | input | TCELL12:IMUX.IMUX1 |
| SAXIHP1AWADDR18 | input | TCELL12:IMUX.IMUX2 |
| SAXIHP1AWADDR19 | input | TCELL12:IMUX.IMUX3 |
| SAXIHP1AWADDR2 | input | TCELL8:IMUX.IMUX2 |
| SAXIHP1AWADDR20 | input | TCELL13:IMUX.IMUX0 |
| SAXIHP1AWADDR21 | input | TCELL13:IMUX.IMUX1 |
| SAXIHP1AWADDR22 | input | TCELL13:IMUX.IMUX2 |
| SAXIHP1AWADDR23 | input | TCELL13:IMUX.IMUX3 |
| SAXIHP1AWADDR24 | input | TCELL14:IMUX.IMUX4 |
| SAXIHP1AWADDR25 | input | TCELL14:IMUX.IMUX5 |
| SAXIHP1AWADDR26 | input | TCELL14:IMUX.IMUX6 |
| SAXIHP1AWADDR27 | input | TCELL14:IMUX.IMUX7 |
| SAXIHP1AWADDR28 | input | TCELL15:IMUX.IMUX2 |
| SAXIHP1AWADDR29 | input | TCELL15:IMUX.IMUX3 |
| SAXIHP1AWADDR3 | input | TCELL8:IMUX.IMUX3 |
| SAXIHP1AWADDR30 | input | TCELL15:IMUX.IMUX4 |
| SAXIHP1AWADDR31 | input | TCELL15:IMUX.IMUX5 |
| SAXIHP1AWADDR4 | input | TCELL9:IMUX.IMUX0 |
| SAXIHP1AWADDR5 | input | TCELL9:IMUX.IMUX1 |
| SAXIHP1AWADDR6 | input | TCELL9:IMUX.IMUX2 |
| SAXIHP1AWADDR7 | input | TCELL9:IMUX.IMUX3 |
| SAXIHP1AWADDR8 | input | TCELL10:IMUX.IMUX0 |
| SAXIHP1AWADDR9 | input | TCELL10:IMUX.IMUX1 |
| SAXIHP1AWBURST0 | input | TCELL13:IMUX.IMUX4 |
| SAXIHP1AWBURST1 | input | TCELL14:IMUX.IMUX10 |
| SAXIHP1AWCACHE0 | input | TCELL12:IMUX.IMUX4 |
| SAXIHP1AWCACHE1 | input | TCELL12:IMUX.IMUX5 |
| SAXIHP1AWCACHE2 | input | TCELL13:IMUX.IMUX7 |
| SAXIHP1AWCACHE3 | input | TCELL13:IMUX.IMUX8 |
| SAXIHP1AWID0 | input | TCELL14:IMUX.IMUX0 |
| SAXIHP1AWID1 | input | TCELL14:IMUX.IMUX1 |
| SAXIHP1AWID2 | input | TCELL14:IMUX.IMUX2 |
| SAXIHP1AWID3 | input | TCELL14:IMUX.IMUX3 |
| SAXIHP1AWID4 | input | TCELL15:IMUX.IMUX0 |
| SAXIHP1AWID5 | input | TCELL15:IMUX.IMUX1 |
| SAXIHP1AWLEN0 | input | TCELL15:IMUX.IMUX6 |
| SAXIHP1AWLEN1 | input | TCELL15:IMUX.IMUX7 |
| SAXIHP1AWLEN2 | input | TCELL15:IMUX.IMUX8 |
| SAXIHP1AWLEN3 | input | TCELL15:IMUX.IMUX9 |
| SAXIHP1AWLOCK0 | input | TCELL13:IMUX.IMUX5 |
| SAXIHP1AWLOCK1 | input | TCELL13:IMUX.IMUX6 |
| SAXIHP1AWPROT0 | input | TCELL12:IMUX.IMUX6 |
| SAXIHP1AWPROT1 | input | TCELL12:IMUX.IMUX7 |
| SAXIHP1AWPROT2 | input | TCELL12:IMUX.IMUX8 |
| SAXIHP1AWQOS0 | input | TCELL14:IMUX.IMUX23 |
| SAXIHP1AWQOS1 | input | TCELL14:IMUX.IMUX24 |
| SAXIHP1AWQOS2 | input | TCELL15:IMUX.IMUX23 |
| SAXIHP1AWQOS3 | input | TCELL15:IMUX.IMUX24 |
| SAXIHP1AWREADY | output | TCELL12:OUT0.TMIN |
| SAXIHP1AWSIZE0 | input | TCELL14:IMUX.IMUX8 |
| SAXIHP1AWSIZE1 | input | TCELL14:IMUX.IMUX9 |
| SAXIHP1AWVALID | input | TCELL12:IMUX.IMUX9 |
| SAXIHP1BID0 | output | TCELL12:OUT2.TMIN |
| SAXIHP1BID1 | output | TCELL12:OUT3.TMIN |
| SAXIHP1BID2 | output | TCELL13:OUT0.TMIN |
| SAXIHP1BID3 | output | TCELL13:OUT1.TMIN |
| SAXIHP1BID4 | output | TCELL13:OUT2.TMIN |
| SAXIHP1BID5 | output | TCELL13:OUT3.TMIN |
| SAXIHP1BREADY | input | TCELL12:IMUX.IMUX21 |
| SAXIHP1BRESP0 | output | TCELL10:OUT0.TMIN |
| SAXIHP1BRESP1 | output | TCELL10:OUT1.TMIN |
| SAXIHP1BVALID | output | TCELL12:OUT4.TMIN |
| SAXIHP1RACOUNT0 | output | TCELL8:OUT11.TMIN |
| SAXIHP1RACOUNT1 | output | TCELL8:OUT12.TMIN |
| SAXIHP1RACOUNT2 | output | TCELL8:OUT13.TMIN |
| SAXIHP1RCOUNT0 | output | TCELL9:OUT11.TMIN |
| SAXIHP1RCOUNT1 | output | TCELL9:OUT12.TMIN |
| SAXIHP1RCOUNT2 | output | TCELL9:OUT13.TMIN |
| SAXIHP1RCOUNT3 | output | TCELL9:OUT14.TMIN |
| SAXIHP1RCOUNT4 | output | TCELL10:OUT10.TMIN |
| SAXIHP1RCOUNT5 | output | TCELL10:OUT11.TMIN |
| SAXIHP1RCOUNT6 | output | TCELL10:OUT12.TMIN |
| SAXIHP1RCOUNT7 | output | TCELL10:OUT13.TMIN |
| SAXIHP1RDATA0 | output | TCELL8:OUT3.TMIN |
| SAXIHP1RDATA1 | output | TCELL8:OUT4.TMIN |
| SAXIHP1RDATA10 | output | TCELL10:OUT4.TMIN |
| SAXIHP1RDATA11 | output | TCELL10:OUT5.TMIN |
| SAXIHP1RDATA12 | output | TCELL11:OUT1.TMIN |
| SAXIHP1RDATA13 | output | TCELL11:OUT2.TMIN |
| SAXIHP1RDATA14 | output | TCELL11:OUT3.TMIN |
| SAXIHP1RDATA15 | output | TCELL11:OUT4.TMIN |
| SAXIHP1RDATA16 | output | TCELL12:OUT5.TMIN |
| SAXIHP1RDATA17 | output | TCELL12:OUT6.TMIN |
| SAXIHP1RDATA18 | output | TCELL12:OUT7.TMIN |
| SAXIHP1RDATA19 | output | TCELL12:OUT8.TMIN |
| SAXIHP1RDATA2 | output | TCELL8:OUT5.TMIN |
| SAXIHP1RDATA20 | output | TCELL13:OUT4.TMIN |
| SAXIHP1RDATA21 | output | TCELL13:OUT5.TMIN |
| SAXIHP1RDATA22 | output | TCELL13:OUT6.TMIN |
| SAXIHP1RDATA23 | output | TCELL13:OUT7.TMIN |
| SAXIHP1RDATA24 | output | TCELL14:OUT0.TMIN |
| SAXIHP1RDATA25 | output | TCELL14:OUT1.TMIN |
| SAXIHP1RDATA26 | output | TCELL14:OUT2.TMIN |
| SAXIHP1RDATA27 | output | TCELL14:OUT3.TMIN |
| SAXIHP1RDATA28 | output | TCELL15:OUT1.TMIN |
| SAXIHP1RDATA29 | output | TCELL15:OUT2.TMIN |
| SAXIHP1RDATA3 | output | TCELL8:OUT6.TMIN |
| SAXIHP1RDATA30 | output | TCELL15:OUT3.TMIN |
| SAXIHP1RDATA31 | output | TCELL15:OUT4.TMIN |
| SAXIHP1RDATA32 | output | TCELL8:OUT7.TMIN |
| SAXIHP1RDATA33 | output | TCELL8:OUT8.TMIN |
| SAXIHP1RDATA34 | output | TCELL8:OUT9.TMIN |
| SAXIHP1RDATA35 | output | TCELL8:OUT10.TMIN |
| SAXIHP1RDATA36 | output | TCELL9:OUT7.TMIN |
| SAXIHP1RDATA37 | output | TCELL9:OUT8.TMIN |
| SAXIHP1RDATA38 | output | TCELL9:OUT9.TMIN |
| SAXIHP1RDATA39 | output | TCELL9:OUT10.TMIN |
| SAXIHP1RDATA4 | output | TCELL9:OUT3.TMIN |
| SAXIHP1RDATA40 | output | TCELL10:OUT6.TMIN |
| SAXIHP1RDATA41 | output | TCELL10:OUT7.TMIN |
| SAXIHP1RDATA42 | output | TCELL10:OUT8.TMIN |
| SAXIHP1RDATA43 | output | TCELL10:OUT9.TMIN |
| SAXIHP1RDATA44 | output | TCELL11:OUT5.TMIN |
| SAXIHP1RDATA45 | output | TCELL11:OUT6.TMIN |
| SAXIHP1RDATA46 | output | TCELL11:OUT7.TMIN |
| SAXIHP1RDATA47 | output | TCELL11:OUT8.TMIN |
| SAXIHP1RDATA48 | output | TCELL12:OUT9.TMIN |
| SAXIHP1RDATA49 | output | TCELL12:OUT10.TMIN |
| SAXIHP1RDATA5 | output | TCELL9:OUT4.TMIN |
| SAXIHP1RDATA50 | output | TCELL12:OUT11.TMIN |
| SAXIHP1RDATA51 | output | TCELL12:OUT12.TMIN |
| SAXIHP1RDATA52 | output | TCELL13:OUT8.TMIN |
| SAXIHP1RDATA53 | output | TCELL13:OUT9.TMIN |
| SAXIHP1RDATA54 | output | TCELL13:OUT10.TMIN |
| SAXIHP1RDATA55 | output | TCELL13:OUT11.TMIN |
| SAXIHP1RDATA56 | output | TCELL14:OUT4.TMIN |
| SAXIHP1RDATA57 | output | TCELL14:OUT5.TMIN |
| SAXIHP1RDATA58 | output | TCELL14:OUT6.TMIN |
| SAXIHP1RDATA59 | output | TCELL14:OUT7.TMIN |
| SAXIHP1RDATA6 | output | TCELL9:OUT5.TMIN |
| SAXIHP1RDATA60 | output | TCELL15:OUT5.TMIN |
| SAXIHP1RDATA61 | output | TCELL15:OUT6.TMIN |
| SAXIHP1RDATA62 | output | TCELL15:OUT7.TMIN |
| SAXIHP1RDATA63 | output | TCELL15:OUT8.TMIN |
| SAXIHP1RDATA7 | output | TCELL9:OUT6.TMIN |
| SAXIHP1RDATA8 | output | TCELL10:OUT2.TMIN |
| SAXIHP1RDATA9 | output | TCELL10:OUT3.TMIN |
| SAXIHP1RDISSUECAP1EN | input | TCELL8:IMUX.IMUX25 |
| SAXIHP1RID0 | output | TCELL8:OUT0.TMIN |
| SAXIHP1RID1 | output | TCELL8:OUT1.TMIN |
| SAXIHP1RID2 | output | TCELL8:OUT2.TMIN |
| SAXIHP1RID3 | output | TCELL9:OUT0.TMIN |
| SAXIHP1RID4 | output | TCELL9:OUT1.TMIN |
| SAXIHP1RID5 | output | TCELL9:OUT2.TMIN |
| SAXIHP1RLAST | output | TCELL11:OUT11.TMIN |
| SAXIHP1RREADY | input | TCELL11:IMUX.IMUX21 |
| SAXIHP1RRESP0 | output | TCELL11:OUT9.TMIN |
| SAXIHP1RRESP1 | output | TCELL11:OUT10.TMIN |
| SAXIHP1RVALID | output | TCELL11:OUT12.TMIN |
| SAXIHP1WACOUNT0 | output | TCELL13:OUT12.TMIN |
| SAXIHP1WACOUNT1 | output | TCELL13:OUT13.TMIN |
| SAXIHP1WACOUNT2 | output | TCELL14:OUT12.TMIN |
| SAXIHP1WACOUNT3 | output | TCELL14:OUT13.TMIN |
| SAXIHP1WACOUNT4 | output | TCELL15:OUT13.TMIN |
| SAXIHP1WACOUNT5 | output | TCELL15:OUT14.TMIN |
| SAXIHP1WCOUNT0 | output | TCELL14:OUT8.TMIN |
| SAXIHP1WCOUNT1 | output | TCELL14:OUT9.TMIN |
| SAXIHP1WCOUNT2 | output | TCELL14:OUT10.TMIN |
| SAXIHP1WCOUNT3 | output | TCELL14:OUT11.TMIN |
| SAXIHP1WCOUNT4 | output | TCELL15:OUT9.TMIN |
| SAXIHP1WCOUNT5 | output | TCELL15:OUT10.TMIN |
| SAXIHP1WCOUNT6 | output | TCELL15:OUT11.TMIN |
| SAXIHP1WCOUNT7 | output | TCELL15:OUT12.TMIN |
| SAXIHP1WDATA0 | input | TCELL8:IMUX.IMUX4 |
| SAXIHP1WDATA1 | input | TCELL8:IMUX.IMUX5 |
| SAXIHP1WDATA10 | input | TCELL10:IMUX.IMUX6 |
| SAXIHP1WDATA11 | input | TCELL10:IMUX.IMUX7 |
| SAXIHP1WDATA12 | input | TCELL11:IMUX.IMUX4 |
| SAXIHP1WDATA13 | input | TCELL11:IMUX.IMUX5 |
| SAXIHP1WDATA14 | input | TCELL11:IMUX.IMUX6 |
| SAXIHP1WDATA15 | input | TCELL11:IMUX.IMUX7 |
| SAXIHP1WDATA16 | input | TCELL12:IMUX.IMUX12 |
| SAXIHP1WDATA17 | input | TCELL12:IMUX.IMUX13 |
| SAXIHP1WDATA18 | input | TCELL12:IMUX.IMUX14 |
| SAXIHP1WDATA19 | input | TCELL12:IMUX.IMUX15 |
| SAXIHP1WDATA2 | input | TCELL8:IMUX.IMUX6 |
| SAXIHP1WDATA20 | input | TCELL13:IMUX.IMUX13 |
| SAXIHP1WDATA21 | input | TCELL13:IMUX.IMUX14 |
| SAXIHP1WDATA22 | input | TCELL13:IMUX.IMUX15 |
| SAXIHP1WDATA23 | input | TCELL13:IMUX.IMUX16 |
| SAXIHP1WDATA24 | input | TCELL14:IMUX.IMUX11 |
| SAXIHP1WDATA25 | input | TCELL14:IMUX.IMUX12 |
| SAXIHP1WDATA26 | input | TCELL14:IMUX.IMUX13 |
| SAXIHP1WDATA27 | input | TCELL14:IMUX.IMUX14 |
| SAXIHP1WDATA28 | input | TCELL15:IMUX.IMUX10 |
| SAXIHP1WDATA29 | input | TCELL15:IMUX.IMUX11 |
| SAXIHP1WDATA3 | input | TCELL8:IMUX.IMUX7 |
| SAXIHP1WDATA30 | input | TCELL15:IMUX.IMUX12 |
| SAXIHP1WDATA31 | input | TCELL15:IMUX.IMUX13 |
| SAXIHP1WDATA32 | input | TCELL8:IMUX.IMUX8 |
| SAXIHP1WDATA33 | input | TCELL8:IMUX.IMUX9 |
| SAXIHP1WDATA34 | input | TCELL8:IMUX.IMUX10 |
| SAXIHP1WDATA35 | input | TCELL8:IMUX.IMUX11 |
| SAXIHP1WDATA36 | input | TCELL9:IMUX.IMUX8 |
| SAXIHP1WDATA37 | input | TCELL9:IMUX.IMUX9 |
| SAXIHP1WDATA38 | input | TCELL9:IMUX.IMUX10 |
| SAXIHP1WDATA39 | input | TCELL9:IMUX.IMUX11 |
| SAXIHP1WDATA4 | input | TCELL9:IMUX.IMUX4 |
| SAXIHP1WDATA40 | input | TCELL10:IMUX.IMUX8 |
| SAXIHP1WDATA41 | input | TCELL10:IMUX.IMUX9 |
| SAXIHP1WDATA42 | input | TCELL10:IMUX.IMUX10 |
| SAXIHP1WDATA43 | input | TCELL10:IMUX.IMUX11 |
| SAXIHP1WDATA44 | input | TCELL11:IMUX.IMUX8 |
| SAXIHP1WDATA45 | input | TCELL11:IMUX.IMUX9 |
| SAXIHP1WDATA46 | input | TCELL11:IMUX.IMUX10 |
| SAXIHP1WDATA47 | input | TCELL11:IMUX.IMUX11 |
| SAXIHP1WDATA48 | input | TCELL12:IMUX.IMUX16 |
| SAXIHP1WDATA49 | input | TCELL12:IMUX.IMUX17 |
| SAXIHP1WDATA5 | input | TCELL9:IMUX.IMUX5 |
| SAXIHP1WDATA50 | input | TCELL12:IMUX.IMUX18 |
| SAXIHP1WDATA51 | input | TCELL12:IMUX.IMUX19 |
| SAXIHP1WDATA52 | input | TCELL13:IMUX.IMUX17 |
| SAXIHP1WDATA53 | input | TCELL13:IMUX.IMUX18 |
| SAXIHP1WDATA54 | input | TCELL13:IMUX.IMUX19 |
| SAXIHP1WDATA55 | input | TCELL13:IMUX.IMUX20 |
| SAXIHP1WDATA56 | input | TCELL14:IMUX.IMUX15 |
| SAXIHP1WDATA57 | input | TCELL14:IMUX.IMUX16 |
| SAXIHP1WDATA58 | input | TCELL14:IMUX.IMUX17 |
| SAXIHP1WDATA59 | input | TCELL14:IMUX.IMUX18 |
| SAXIHP1WDATA6 | input | TCELL9:IMUX.IMUX6 |
| SAXIHP1WDATA60 | input | TCELL15:IMUX.IMUX14 |
| SAXIHP1WDATA61 | input | TCELL15:IMUX.IMUX15 |
| SAXIHP1WDATA62 | input | TCELL15:IMUX.IMUX16 |
| SAXIHP1WDATA63 | input | TCELL15:IMUX.IMUX17 |
| SAXIHP1WDATA7 | input | TCELL9:IMUX.IMUX7 |
| SAXIHP1WDATA8 | input | TCELL10:IMUX.IMUX4 |
| SAXIHP1WDATA9 | input | TCELL10:IMUX.IMUX5 |
| SAXIHP1WID0 | input | TCELL12:IMUX.IMUX10 |
| SAXIHP1WID1 | input | TCELL12:IMUX.IMUX11 |
| SAXIHP1WID2 | input | TCELL13:IMUX.IMUX9 |
| SAXIHP1WID3 | input | TCELL13:IMUX.IMUX10 |
| SAXIHP1WID4 | input | TCELL13:IMUX.IMUX11 |
| SAXIHP1WID5 | input | TCELL13:IMUX.IMUX12 |
| SAXIHP1WLAST | input | TCELL10:IMUX.IMUX16 |
| SAXIHP1WREADY | output | TCELL12:OUT1.TMIN |
| SAXIHP1WRISSUECAP1EN | input | TCELL15:IMUX.IMUX22 |
| SAXIHP1WSTRB0 | input | TCELL10:IMUX.IMUX12 |
| SAXIHP1WSTRB1 | input | TCELL10:IMUX.IMUX13 |
| SAXIHP1WSTRB2 | input | TCELL10:IMUX.IMUX14 |
| SAXIHP1WSTRB3 | input | TCELL10:IMUX.IMUX15 |
| SAXIHP1WSTRB4 | input | TCELL11:IMUX.IMUX12 |
| SAXIHP1WSTRB5 | input | TCELL11:IMUX.IMUX13 |
| SAXIHP1WSTRB6 | input | TCELL11:IMUX.IMUX14 |
| SAXIHP1WSTRB7 | input | TCELL11:IMUX.IMUX15 |
| SAXIHP1WVALID | input | TCELL12:IMUX.IMUX20 |
| SAXIHP2ACLK | input | TCELL20:IMUX.CLK0 |
| SAXIHP2ARADDR0 | input | TCELL16:IMUX.IMUX16 |
| SAXIHP2ARADDR1 | input | TCELL16:IMUX.IMUX17 |
| SAXIHP2ARADDR10 | input | TCELL18:IMUX.IMUX19 |
| SAXIHP2ARADDR11 | input | TCELL18:IMUX.IMUX20 |
| SAXIHP2ARADDR12 | input | TCELL19:IMUX.IMUX16 |
| SAXIHP2ARADDR13 | input | TCELL19:IMUX.IMUX17 |
| SAXIHP2ARADDR14 | input | TCELL19:IMUX.IMUX18 |
| SAXIHP2ARADDR15 | input | TCELL19:IMUX.IMUX19 |
| SAXIHP2ARADDR16 | input | TCELL20:IMUX.IMUX22 |
| SAXIHP2ARADDR17 | input | TCELL20:IMUX.IMUX23 |
| SAXIHP2ARADDR18 | input | TCELL20:IMUX.IMUX24 |
| SAXIHP2ARADDR19 | input | TCELL20:IMUX.IMUX25 |
| SAXIHP2ARADDR2 | input | TCELL16:IMUX.IMUX18 |
| SAXIHP2ARADDR20 | input | TCELL21:IMUX.IMUX21 |
| SAXIHP2ARADDR21 | input | TCELL21:IMUX.IMUX22 |
| SAXIHP2ARADDR22 | input | TCELL21:IMUX.IMUX23 |
| SAXIHP2ARADDR23 | input | TCELL21:IMUX.IMUX24 |
| SAXIHP2ARADDR24 | input | TCELL22:IMUX.IMUX19 |
| SAXIHP2ARADDR25 | input | TCELL22:IMUX.IMUX20 |
| SAXIHP2ARADDR26 | input | TCELL22:IMUX.IMUX21 |
| SAXIHP2ARADDR27 | input | TCELL22:IMUX.IMUX22 |
| SAXIHP2ARADDR28 | input | TCELL23:IMUX.IMUX18 |
| SAXIHP2ARADDR29 | input | TCELL23:IMUX.IMUX19 |
| SAXIHP2ARADDR3 | input | TCELL16:IMUX.IMUX19 |
| SAXIHP2ARADDR30 | input | TCELL23:IMUX.IMUX20 |
| SAXIHP2ARADDR31 | input | TCELL23:IMUX.IMUX21 |
| SAXIHP2ARADDR4 | input | TCELL17:IMUX.IMUX14 |
| SAXIHP2ARADDR5 | input | TCELL17:IMUX.IMUX15 |
| SAXIHP2ARADDR6 | input | TCELL17:IMUX.IMUX16 |
| SAXIHP2ARADDR7 | input | TCELL17:IMUX.IMUX17 |
| SAXIHP2ARADDR8 | input | TCELL18:IMUX.IMUX17 |
| SAXIHP2ARADDR9 | input | TCELL18:IMUX.IMUX18 |
| SAXIHP2ARBURST0 | input | TCELL16:IMUX.IMUX22 |
| SAXIHP2ARBURST1 | input | TCELL16:IMUX.IMUX23 |
| SAXIHP2ARCACHE0 | input | TCELL17:IMUX.IMUX19 |
| SAXIHP2ARCACHE1 | input | TCELL17:IMUX.IMUX20 |
| SAXIHP2ARCACHE2 | input | TCELL17:IMUX.IMUX21 |
| SAXIHP2ARCACHE3 | input | TCELL17:IMUX.IMUX22 |
| SAXIHP2ARESETN | output | TCELL23:OUT0.TMIN |
| SAXIHP2ARID0 | input | TCELL16:IMUX.IMUX12 |
| SAXIHP2ARID1 | input | TCELL16:IMUX.IMUX13 |
| SAXIHP2ARID2 | input | TCELL16:IMUX.IMUX14 |
| SAXIHP2ARID3 | input | TCELL16:IMUX.IMUX15 |
| SAXIHP2ARID4 | input | TCELL17:IMUX.IMUX12 |
| SAXIHP2ARID5 | input | TCELL17:IMUX.IMUX13 |
| SAXIHP2ARLEN0 | input | TCELL18:IMUX.IMUX21 |
| SAXIHP2ARLEN1 | input | TCELL18:IMUX.IMUX22 |
| SAXIHP2ARLEN2 | input | TCELL18:IMUX.IMUX23 |
| SAXIHP2ARLEN3 | input | TCELL18:IMUX.IMUX24 |
| SAXIHP2ARLOCK0 | input | TCELL16:IMUX.IMUX24 |
| SAXIHP2ARLOCK1 | input | TCELL17:IMUX.IMUX18 |
| SAXIHP2ARPROT0 | input | TCELL17:IMUX.IMUX23 |
| SAXIHP2ARPROT1 | input | TCELL17:IMUX.IMUX24 |
| SAXIHP2ARPROT2 | input | TCELL18:IMUX.IMUX25 |
| SAXIHP2ARQOS0 | input | TCELL19:IMUX.IMUX22 |
| SAXIHP2ARQOS1 | input | TCELL19:IMUX.IMUX23 |
| SAXIHP2ARQOS2 | input | TCELL19:IMUX.IMUX24 |
| SAXIHP2ARQOS3 | input | TCELL19:IMUX.IMUX25 |
| SAXIHP2ARREADY | output | TCELL19:OUT0.TMIN |
| SAXIHP2ARSIZE0 | input | TCELL16:IMUX.IMUX20 |
| SAXIHP2ARSIZE1 | input | TCELL16:IMUX.IMUX21 |
| SAXIHP2ARVALID | input | TCELL19:IMUX.IMUX20 |
| SAXIHP2AWADDR0 | input | TCELL16:IMUX.IMUX0 |
| SAXIHP2AWADDR1 | input | TCELL16:IMUX.IMUX1 |
| SAXIHP2AWADDR10 | input | TCELL18:IMUX.IMUX2 |
| SAXIHP2AWADDR11 | input | TCELL18:IMUX.IMUX3 |
| SAXIHP2AWADDR12 | input | TCELL19:IMUX.IMUX0 |
| SAXIHP2AWADDR13 | input | TCELL19:IMUX.IMUX1 |
| SAXIHP2AWADDR14 | input | TCELL19:IMUX.IMUX2 |
| SAXIHP2AWADDR15 | input | TCELL19:IMUX.IMUX3 |
| SAXIHP2AWADDR16 | input | TCELL20:IMUX.IMUX0 |
| SAXIHP2AWADDR17 | input | TCELL20:IMUX.IMUX1 |
| SAXIHP2AWADDR18 | input | TCELL20:IMUX.IMUX2 |
| SAXIHP2AWADDR19 | input | TCELL20:IMUX.IMUX3 |
| SAXIHP2AWADDR2 | input | TCELL16:IMUX.IMUX2 |
| SAXIHP2AWADDR20 | input | TCELL21:IMUX.IMUX0 |
| SAXIHP2AWADDR21 | input | TCELL21:IMUX.IMUX1 |
| SAXIHP2AWADDR22 | input | TCELL21:IMUX.IMUX2 |
| SAXIHP2AWADDR23 | input | TCELL21:IMUX.IMUX3 |
| SAXIHP2AWADDR24 | input | TCELL22:IMUX.IMUX4 |
| SAXIHP2AWADDR25 | input | TCELL22:IMUX.IMUX5 |
| SAXIHP2AWADDR26 | input | TCELL22:IMUX.IMUX6 |
| SAXIHP2AWADDR27 | input | TCELL22:IMUX.IMUX7 |
| SAXIHP2AWADDR28 | input | TCELL23:IMUX.IMUX2 |
| SAXIHP2AWADDR29 | input | TCELL23:IMUX.IMUX3 |
| SAXIHP2AWADDR3 | input | TCELL16:IMUX.IMUX3 |
| SAXIHP2AWADDR30 | input | TCELL23:IMUX.IMUX4 |
| SAXIHP2AWADDR31 | input | TCELL23:IMUX.IMUX5 |
| SAXIHP2AWADDR4 | input | TCELL17:IMUX.IMUX0 |
| SAXIHP2AWADDR5 | input | TCELL17:IMUX.IMUX1 |
| SAXIHP2AWADDR6 | input | TCELL17:IMUX.IMUX2 |
| SAXIHP2AWADDR7 | input | TCELL17:IMUX.IMUX3 |
| SAXIHP2AWADDR8 | input | TCELL18:IMUX.IMUX0 |
| SAXIHP2AWADDR9 | input | TCELL18:IMUX.IMUX1 |
| SAXIHP2AWBURST0 | input | TCELL21:IMUX.IMUX4 |
| SAXIHP2AWBURST1 | input | TCELL22:IMUX.IMUX10 |
| SAXIHP2AWCACHE0 | input | TCELL20:IMUX.IMUX4 |
| SAXIHP2AWCACHE1 | input | TCELL20:IMUX.IMUX5 |
| SAXIHP2AWCACHE2 | input | TCELL21:IMUX.IMUX7 |
| SAXIHP2AWCACHE3 | input | TCELL21:IMUX.IMUX8 |
| SAXIHP2AWID0 | input | TCELL22:IMUX.IMUX0 |
| SAXIHP2AWID1 | input | TCELL22:IMUX.IMUX1 |
| SAXIHP2AWID2 | input | TCELL22:IMUX.IMUX2 |
| SAXIHP2AWID3 | input | TCELL22:IMUX.IMUX3 |
| SAXIHP2AWID4 | input | TCELL23:IMUX.IMUX0 |
| SAXIHP2AWID5 | input | TCELL23:IMUX.IMUX1 |
| SAXIHP2AWLEN0 | input | TCELL23:IMUX.IMUX6 |
| SAXIHP2AWLEN1 | input | TCELL23:IMUX.IMUX7 |
| SAXIHP2AWLEN2 | input | TCELL23:IMUX.IMUX8 |
| SAXIHP2AWLEN3 | input | TCELL23:IMUX.IMUX9 |
| SAXIHP2AWLOCK0 | input | TCELL21:IMUX.IMUX5 |
| SAXIHP2AWLOCK1 | input | TCELL21:IMUX.IMUX6 |
| SAXIHP2AWPROT0 | input | TCELL20:IMUX.IMUX6 |
| SAXIHP2AWPROT1 | input | TCELL20:IMUX.IMUX7 |
| SAXIHP2AWPROT2 | input | TCELL20:IMUX.IMUX8 |
| SAXIHP2AWQOS0 | input | TCELL22:IMUX.IMUX23 |
| SAXIHP2AWQOS1 | input | TCELL22:IMUX.IMUX24 |
| SAXIHP2AWQOS2 | input | TCELL23:IMUX.IMUX23 |
| SAXIHP2AWQOS3 | input | TCELL23:IMUX.IMUX24 |
| SAXIHP2AWREADY | output | TCELL20:OUT0.TMIN |
| SAXIHP2AWSIZE0 | input | TCELL22:IMUX.IMUX8 |
| SAXIHP2AWSIZE1 | input | TCELL22:IMUX.IMUX9 |
| SAXIHP2AWVALID | input | TCELL20:IMUX.IMUX9 |
| SAXIHP2BID0 | output | TCELL20:OUT2.TMIN |
| SAXIHP2BID1 | output | TCELL20:OUT3.TMIN |
| SAXIHP2BID2 | output | TCELL21:OUT0.TMIN |
| SAXIHP2BID3 | output | TCELL21:OUT1.TMIN |
| SAXIHP2BID4 | output | TCELL21:OUT2.TMIN |
| SAXIHP2BID5 | output | TCELL21:OUT3.TMIN |
| SAXIHP2BREADY | input | TCELL20:IMUX.IMUX21 |
| SAXIHP2BRESP0 | output | TCELL18:OUT0.TMIN |
| SAXIHP2BRESP1 | output | TCELL18:OUT1.TMIN |
| SAXIHP2BVALID | output | TCELL20:OUT4.TMIN |
| SAXIHP2RACOUNT0 | output | TCELL16:OUT11.TMIN |
| SAXIHP2RACOUNT1 | output | TCELL16:OUT12.TMIN |
| SAXIHP2RACOUNT2 | output | TCELL16:OUT13.TMIN |
| SAXIHP2RCOUNT0 | output | TCELL17:OUT11.TMIN |
| SAXIHP2RCOUNT1 | output | TCELL17:OUT12.TMIN |
| SAXIHP2RCOUNT2 | output | TCELL17:OUT13.TMIN |
| SAXIHP2RCOUNT3 | output | TCELL17:OUT14.TMIN |
| SAXIHP2RCOUNT4 | output | TCELL18:OUT10.TMIN |
| SAXIHP2RCOUNT5 | output | TCELL18:OUT11.TMIN |
| SAXIHP2RCOUNT6 | output | TCELL18:OUT12.TMIN |
| SAXIHP2RCOUNT7 | output | TCELL18:OUT13.TMIN |
| SAXIHP2RDATA0 | output | TCELL16:OUT3.TMIN |
| SAXIHP2RDATA1 | output | TCELL16:OUT4.TMIN |
| SAXIHP2RDATA10 | output | TCELL18:OUT4.TMIN |
| SAXIHP2RDATA11 | output | TCELL18:OUT5.TMIN |
| SAXIHP2RDATA12 | output | TCELL19:OUT1.TMIN |
| SAXIHP2RDATA13 | output | TCELL19:OUT2.TMIN |
| SAXIHP2RDATA14 | output | TCELL19:OUT3.TMIN |
| SAXIHP2RDATA15 | output | TCELL19:OUT4.TMIN |
| SAXIHP2RDATA16 | output | TCELL20:OUT5.TMIN |
| SAXIHP2RDATA17 | output | TCELL20:OUT6.TMIN |
| SAXIHP2RDATA18 | output | TCELL20:OUT7.TMIN |
| SAXIHP2RDATA19 | output | TCELL20:OUT8.TMIN |
| SAXIHP2RDATA2 | output | TCELL16:OUT5.TMIN |
| SAXIHP2RDATA20 | output | TCELL21:OUT4.TMIN |
| SAXIHP2RDATA21 | output | TCELL21:OUT5.TMIN |
| SAXIHP2RDATA22 | output | TCELL21:OUT6.TMIN |
| SAXIHP2RDATA23 | output | TCELL21:OUT7.TMIN |
| SAXIHP2RDATA24 | output | TCELL22:OUT0.TMIN |
| SAXIHP2RDATA25 | output | TCELL22:OUT1.TMIN |
| SAXIHP2RDATA26 | output | TCELL22:OUT2.TMIN |
| SAXIHP2RDATA27 | output | TCELL22:OUT3.TMIN |
| SAXIHP2RDATA28 | output | TCELL23:OUT1.TMIN |
| SAXIHP2RDATA29 | output | TCELL23:OUT2.TMIN |
| SAXIHP2RDATA3 | output | TCELL16:OUT6.TMIN |
| SAXIHP2RDATA30 | output | TCELL23:OUT3.TMIN |
| SAXIHP2RDATA31 | output | TCELL23:OUT4.TMIN |
| SAXIHP2RDATA32 | output | TCELL16:OUT7.TMIN |
| SAXIHP2RDATA33 | output | TCELL16:OUT8.TMIN |
| SAXIHP2RDATA34 | output | TCELL16:OUT9.TMIN |
| SAXIHP2RDATA35 | output | TCELL16:OUT10.TMIN |
| SAXIHP2RDATA36 | output | TCELL17:OUT7.TMIN |
| SAXIHP2RDATA37 | output | TCELL17:OUT8.TMIN |
| SAXIHP2RDATA38 | output | TCELL17:OUT9.TMIN |
| SAXIHP2RDATA39 | output | TCELL17:OUT10.TMIN |
| SAXIHP2RDATA4 | output | TCELL17:OUT3.TMIN |
| SAXIHP2RDATA40 | output | TCELL18:OUT6.TMIN |
| SAXIHP2RDATA41 | output | TCELL18:OUT7.TMIN |
| SAXIHP2RDATA42 | output | TCELL18:OUT8.TMIN |
| SAXIHP2RDATA43 | output | TCELL18:OUT9.TMIN |
| SAXIHP2RDATA44 | output | TCELL19:OUT5.TMIN |
| SAXIHP2RDATA45 | output | TCELL19:OUT6.TMIN |
| SAXIHP2RDATA46 | output | TCELL19:OUT7.TMIN |
| SAXIHP2RDATA47 | output | TCELL19:OUT8.TMIN |
| SAXIHP2RDATA48 | output | TCELL20:OUT9.TMIN |
| SAXIHP2RDATA49 | output | TCELL20:OUT10.TMIN |
| SAXIHP2RDATA5 | output | TCELL17:OUT4.TMIN |
| SAXIHP2RDATA50 | output | TCELL20:OUT11.TMIN |
| SAXIHP2RDATA51 | output | TCELL20:OUT12.TMIN |
| SAXIHP2RDATA52 | output | TCELL21:OUT8.TMIN |
| SAXIHP2RDATA53 | output | TCELL21:OUT9.TMIN |
| SAXIHP2RDATA54 | output | TCELL21:OUT10.TMIN |
| SAXIHP2RDATA55 | output | TCELL21:OUT11.TMIN |
| SAXIHP2RDATA56 | output | TCELL22:OUT4.TMIN |
| SAXIHP2RDATA57 | output | TCELL22:OUT5.TMIN |
| SAXIHP2RDATA58 | output | TCELL22:OUT6.TMIN |
| SAXIHP2RDATA59 | output | TCELL22:OUT7.TMIN |
| SAXIHP2RDATA6 | output | TCELL17:OUT5.TMIN |
| SAXIHP2RDATA60 | output | TCELL23:OUT5.TMIN |
| SAXIHP2RDATA61 | output | TCELL23:OUT6.TMIN |
| SAXIHP2RDATA62 | output | TCELL23:OUT7.TMIN |
| SAXIHP2RDATA63 | output | TCELL23:OUT8.TMIN |
| SAXIHP2RDATA7 | output | TCELL17:OUT6.TMIN |
| SAXIHP2RDATA8 | output | TCELL18:OUT2.TMIN |
| SAXIHP2RDATA9 | output | TCELL18:OUT3.TMIN |
| SAXIHP2RDISSUECAP1EN | input | TCELL16:IMUX.IMUX25 |
| SAXIHP2RID0 | output | TCELL16:OUT0.TMIN |
| SAXIHP2RID1 | output | TCELL16:OUT1.TMIN |
| SAXIHP2RID2 | output | TCELL16:OUT2.TMIN |
| SAXIHP2RID3 | output | TCELL17:OUT0.TMIN |
| SAXIHP2RID4 | output | TCELL17:OUT1.TMIN |
| SAXIHP2RID5 | output | TCELL17:OUT2.TMIN |
| SAXIHP2RLAST | output | TCELL19:OUT11.TMIN |
| SAXIHP2RREADY | input | TCELL19:IMUX.IMUX21 |
| SAXIHP2RRESP0 | output | TCELL19:OUT9.TMIN |
| SAXIHP2RRESP1 | output | TCELL19:OUT10.TMIN |
| SAXIHP2RVALID | output | TCELL19:OUT12.TMIN |
| SAXIHP2WACOUNT0 | output | TCELL21:OUT12.TMIN |
| SAXIHP2WACOUNT1 | output | TCELL21:OUT13.TMIN |
| SAXIHP2WACOUNT2 | output | TCELL22:OUT12.TMIN |
| SAXIHP2WACOUNT3 | output | TCELL22:OUT13.TMIN |
| SAXIHP2WACOUNT4 | output | TCELL23:OUT13.TMIN |
| SAXIHP2WACOUNT5 | output | TCELL23:OUT14.TMIN |
| SAXIHP2WCOUNT0 | output | TCELL22:OUT8.TMIN |
| SAXIHP2WCOUNT1 | output | TCELL22:OUT9.TMIN |
| SAXIHP2WCOUNT2 | output | TCELL22:OUT10.TMIN |
| SAXIHP2WCOUNT3 | output | TCELL22:OUT11.TMIN |
| SAXIHP2WCOUNT4 | output | TCELL23:OUT9.TMIN |
| SAXIHP2WCOUNT5 | output | TCELL23:OUT10.TMIN |
| SAXIHP2WCOUNT6 | output | TCELL23:OUT11.TMIN |
| SAXIHP2WCOUNT7 | output | TCELL23:OUT12.TMIN |
| SAXIHP2WDATA0 | input | TCELL16:IMUX.IMUX4 |
| SAXIHP2WDATA1 | input | TCELL16:IMUX.IMUX5 |
| SAXIHP2WDATA10 | input | TCELL18:IMUX.IMUX6 |
| SAXIHP2WDATA11 | input | TCELL18:IMUX.IMUX7 |
| SAXIHP2WDATA12 | input | TCELL19:IMUX.IMUX4 |
| SAXIHP2WDATA13 | input | TCELL19:IMUX.IMUX5 |
| SAXIHP2WDATA14 | input | TCELL19:IMUX.IMUX6 |
| SAXIHP2WDATA15 | input | TCELL19:IMUX.IMUX7 |
| SAXIHP2WDATA16 | input | TCELL20:IMUX.IMUX12 |
| SAXIHP2WDATA17 | input | TCELL20:IMUX.IMUX13 |
| SAXIHP2WDATA18 | input | TCELL20:IMUX.IMUX14 |
| SAXIHP2WDATA19 | input | TCELL20:IMUX.IMUX15 |
| SAXIHP2WDATA2 | input | TCELL16:IMUX.IMUX6 |
| SAXIHP2WDATA20 | input | TCELL21:IMUX.IMUX13 |
| SAXIHP2WDATA21 | input | TCELL21:IMUX.IMUX14 |
| SAXIHP2WDATA22 | input | TCELL21:IMUX.IMUX15 |
| SAXIHP2WDATA23 | input | TCELL21:IMUX.IMUX16 |
| SAXIHP2WDATA24 | input | TCELL22:IMUX.IMUX11 |
| SAXIHP2WDATA25 | input | TCELL22:IMUX.IMUX12 |
| SAXIHP2WDATA26 | input | TCELL22:IMUX.IMUX13 |
| SAXIHP2WDATA27 | input | TCELL22:IMUX.IMUX14 |
| SAXIHP2WDATA28 | input | TCELL23:IMUX.IMUX10 |
| SAXIHP2WDATA29 | input | TCELL23:IMUX.IMUX11 |
| SAXIHP2WDATA3 | input | TCELL16:IMUX.IMUX7 |
| SAXIHP2WDATA30 | input | TCELL23:IMUX.IMUX12 |
| SAXIHP2WDATA31 | input | TCELL23:IMUX.IMUX13 |
| SAXIHP2WDATA32 | input | TCELL16:IMUX.IMUX8 |
| SAXIHP2WDATA33 | input | TCELL16:IMUX.IMUX9 |
| SAXIHP2WDATA34 | input | TCELL16:IMUX.IMUX10 |
| SAXIHP2WDATA35 | input | TCELL16:IMUX.IMUX11 |
| SAXIHP2WDATA36 | input | TCELL17:IMUX.IMUX8 |
| SAXIHP2WDATA37 | input | TCELL17:IMUX.IMUX9 |
| SAXIHP2WDATA38 | input | TCELL17:IMUX.IMUX10 |
| SAXIHP2WDATA39 | input | TCELL17:IMUX.IMUX11 |
| SAXIHP2WDATA4 | input | TCELL17:IMUX.IMUX4 |
| SAXIHP2WDATA40 | input | TCELL18:IMUX.IMUX8 |
| SAXIHP2WDATA41 | input | TCELL18:IMUX.IMUX9 |
| SAXIHP2WDATA42 | input | TCELL18:IMUX.IMUX10 |
| SAXIHP2WDATA43 | input | TCELL18:IMUX.IMUX11 |
| SAXIHP2WDATA44 | input | TCELL19:IMUX.IMUX8 |
| SAXIHP2WDATA45 | input | TCELL19:IMUX.IMUX9 |
| SAXIHP2WDATA46 | input | TCELL19:IMUX.IMUX10 |
| SAXIHP2WDATA47 | input | TCELL19:IMUX.IMUX11 |
| SAXIHP2WDATA48 | input | TCELL20:IMUX.IMUX16 |
| SAXIHP2WDATA49 | input | TCELL20:IMUX.IMUX17 |
| SAXIHP2WDATA5 | input | TCELL17:IMUX.IMUX5 |
| SAXIHP2WDATA50 | input | TCELL20:IMUX.IMUX18 |
| SAXIHP2WDATA51 | input | TCELL20:IMUX.IMUX19 |
| SAXIHP2WDATA52 | input | TCELL21:IMUX.IMUX17 |
| SAXIHP2WDATA53 | input | TCELL21:IMUX.IMUX18 |
| SAXIHP2WDATA54 | input | TCELL21:IMUX.IMUX19 |
| SAXIHP2WDATA55 | input | TCELL21:IMUX.IMUX20 |
| SAXIHP2WDATA56 | input | TCELL22:IMUX.IMUX15 |
| SAXIHP2WDATA57 | input | TCELL22:IMUX.IMUX16 |
| SAXIHP2WDATA58 | input | TCELL22:IMUX.IMUX17 |
| SAXIHP2WDATA59 | input | TCELL22:IMUX.IMUX18 |
| SAXIHP2WDATA6 | input | TCELL17:IMUX.IMUX6 |
| SAXIHP2WDATA60 | input | TCELL23:IMUX.IMUX14 |
| SAXIHP2WDATA61 | input | TCELL23:IMUX.IMUX15 |
| SAXIHP2WDATA62 | input | TCELL23:IMUX.IMUX16 |
| SAXIHP2WDATA63 | input | TCELL23:IMUX.IMUX17 |
| SAXIHP2WDATA7 | input | TCELL17:IMUX.IMUX7 |
| SAXIHP2WDATA8 | input | TCELL18:IMUX.IMUX4 |
| SAXIHP2WDATA9 | input | TCELL18:IMUX.IMUX5 |
| SAXIHP2WID0 | input | TCELL20:IMUX.IMUX10 |
| SAXIHP2WID1 | input | TCELL20:IMUX.IMUX11 |
| SAXIHP2WID2 | input | TCELL21:IMUX.IMUX9 |
| SAXIHP2WID3 | input | TCELL21:IMUX.IMUX10 |
| SAXIHP2WID4 | input | TCELL21:IMUX.IMUX11 |
| SAXIHP2WID5 | input | TCELL21:IMUX.IMUX12 |
| SAXIHP2WLAST | input | TCELL18:IMUX.IMUX16 |
| SAXIHP2WREADY | output | TCELL20:OUT1.TMIN |
| SAXIHP2WRISSUECAP1EN | input | TCELL23:IMUX.IMUX22 |
| SAXIHP2WSTRB0 | input | TCELL18:IMUX.IMUX12 |
| SAXIHP2WSTRB1 | input | TCELL18:IMUX.IMUX13 |
| SAXIHP2WSTRB2 | input | TCELL18:IMUX.IMUX14 |
| SAXIHP2WSTRB3 | input | TCELL18:IMUX.IMUX15 |
| SAXIHP2WSTRB4 | input | TCELL19:IMUX.IMUX12 |
| SAXIHP2WSTRB5 | input | TCELL19:IMUX.IMUX13 |
| SAXIHP2WSTRB6 | input | TCELL19:IMUX.IMUX14 |
| SAXIHP2WSTRB7 | input | TCELL19:IMUX.IMUX15 |
| SAXIHP2WVALID | input | TCELL20:IMUX.IMUX20 |
| SAXIHP3ACLK | input | TCELL28:IMUX.CLK0 |
| SAXIHP3ARADDR0 | input | TCELL24:IMUX.IMUX16 |
| SAXIHP3ARADDR1 | input | TCELL24:IMUX.IMUX17 |
| SAXIHP3ARADDR10 | input | TCELL26:IMUX.IMUX19 |
| SAXIHP3ARADDR11 | input | TCELL26:IMUX.IMUX20 |
| SAXIHP3ARADDR12 | input | TCELL27:IMUX.IMUX16 |
| SAXIHP3ARADDR13 | input | TCELL27:IMUX.IMUX17 |
| SAXIHP3ARADDR14 | input | TCELL27:IMUX.IMUX18 |
| SAXIHP3ARADDR15 | input | TCELL27:IMUX.IMUX19 |
| SAXIHP3ARADDR16 | input | TCELL28:IMUX.IMUX22 |
| SAXIHP3ARADDR17 | input | TCELL28:IMUX.IMUX23 |
| SAXIHP3ARADDR18 | input | TCELL28:IMUX.IMUX24 |
| SAXIHP3ARADDR19 | input | TCELL28:IMUX.IMUX25 |
| SAXIHP3ARADDR2 | input | TCELL24:IMUX.IMUX18 |
| SAXIHP3ARADDR20 | input | TCELL29:IMUX.IMUX21 |
| SAXIHP3ARADDR21 | input | TCELL29:IMUX.IMUX22 |
| SAXIHP3ARADDR22 | input | TCELL29:IMUX.IMUX23 |
| SAXIHP3ARADDR23 | input | TCELL29:IMUX.IMUX24 |
| SAXIHP3ARADDR24 | input | TCELL30:IMUX.IMUX19 |
| SAXIHP3ARADDR25 | input | TCELL30:IMUX.IMUX20 |
| SAXIHP3ARADDR26 | input | TCELL30:IMUX.IMUX21 |
| SAXIHP3ARADDR27 | input | TCELL30:IMUX.IMUX22 |
| SAXIHP3ARADDR28 | input | TCELL31:IMUX.IMUX18 |
| SAXIHP3ARADDR29 | input | TCELL31:IMUX.IMUX19 |
| SAXIHP3ARADDR3 | input | TCELL24:IMUX.IMUX19 |
| SAXIHP3ARADDR30 | input | TCELL31:IMUX.IMUX20 |
| SAXIHP3ARADDR31 | input | TCELL31:IMUX.IMUX21 |
| SAXIHP3ARADDR4 | input | TCELL25:IMUX.IMUX14 |
| SAXIHP3ARADDR5 | input | TCELL25:IMUX.IMUX15 |
| SAXIHP3ARADDR6 | input | TCELL25:IMUX.IMUX16 |
| SAXIHP3ARADDR7 | input | TCELL25:IMUX.IMUX17 |
| SAXIHP3ARADDR8 | input | TCELL26:IMUX.IMUX17 |
| SAXIHP3ARADDR9 | input | TCELL26:IMUX.IMUX18 |
| SAXIHP3ARBURST0 | input | TCELL24:IMUX.IMUX22 |
| SAXIHP3ARBURST1 | input | TCELL24:IMUX.IMUX23 |
| SAXIHP3ARCACHE0 | input | TCELL25:IMUX.IMUX19 |
| SAXIHP3ARCACHE1 | input | TCELL25:IMUX.IMUX20 |
| SAXIHP3ARCACHE2 | input | TCELL25:IMUX.IMUX21 |
| SAXIHP3ARCACHE3 | input | TCELL25:IMUX.IMUX22 |
| SAXIHP3ARESETN | output | TCELL31:OUT0.TMIN |
| SAXIHP3ARID0 | input | TCELL24:IMUX.IMUX12 |
| SAXIHP3ARID1 | input | TCELL24:IMUX.IMUX13 |
| SAXIHP3ARID2 | input | TCELL24:IMUX.IMUX14 |
| SAXIHP3ARID3 | input | TCELL24:IMUX.IMUX15 |
| SAXIHP3ARID4 | input | TCELL25:IMUX.IMUX12 |
| SAXIHP3ARID5 | input | TCELL25:IMUX.IMUX13 |
| SAXIHP3ARLEN0 | input | TCELL26:IMUX.IMUX21 |
| SAXIHP3ARLEN1 | input | TCELL26:IMUX.IMUX22 |
| SAXIHP3ARLEN2 | input | TCELL26:IMUX.IMUX23 |
| SAXIHP3ARLEN3 | input | TCELL26:IMUX.IMUX24 |
| SAXIHP3ARLOCK0 | input | TCELL24:IMUX.IMUX24 |
| SAXIHP3ARLOCK1 | input | TCELL25:IMUX.IMUX18 |
| SAXIHP3ARPROT0 | input | TCELL25:IMUX.IMUX23 |
| SAXIHP3ARPROT1 | input | TCELL25:IMUX.IMUX24 |
| SAXIHP3ARPROT2 | input | TCELL26:IMUX.IMUX25 |
| SAXIHP3ARQOS0 | input | TCELL27:IMUX.IMUX22 |
| SAXIHP3ARQOS1 | input | TCELL27:IMUX.IMUX23 |
| SAXIHP3ARQOS2 | input | TCELL27:IMUX.IMUX24 |
| SAXIHP3ARQOS3 | input | TCELL27:IMUX.IMUX25 |
| SAXIHP3ARREADY | output | TCELL27:OUT0.TMIN |
| SAXIHP3ARSIZE0 | input | TCELL24:IMUX.IMUX20 |
| SAXIHP3ARSIZE1 | input | TCELL24:IMUX.IMUX21 |
| SAXIHP3ARVALID | input | TCELL27:IMUX.IMUX20 |
| SAXIHP3AWADDR0 | input | TCELL24:IMUX.IMUX0 |
| SAXIHP3AWADDR1 | input | TCELL24:IMUX.IMUX1 |
| SAXIHP3AWADDR10 | input | TCELL26:IMUX.IMUX2 |
| SAXIHP3AWADDR11 | input | TCELL26:IMUX.IMUX3 |
| SAXIHP3AWADDR12 | input | TCELL27:IMUX.IMUX0 |
| SAXIHP3AWADDR13 | input | TCELL27:IMUX.IMUX1 |
| SAXIHP3AWADDR14 | input | TCELL27:IMUX.IMUX2 |
| SAXIHP3AWADDR15 | input | TCELL27:IMUX.IMUX3 |
| SAXIHP3AWADDR16 | input | TCELL28:IMUX.IMUX0 |
| SAXIHP3AWADDR17 | input | TCELL28:IMUX.IMUX1 |
| SAXIHP3AWADDR18 | input | TCELL28:IMUX.IMUX2 |
| SAXIHP3AWADDR19 | input | TCELL28:IMUX.IMUX3 |
| SAXIHP3AWADDR2 | input | TCELL24:IMUX.IMUX2 |
| SAXIHP3AWADDR20 | input | TCELL29:IMUX.IMUX0 |
| SAXIHP3AWADDR21 | input | TCELL29:IMUX.IMUX1 |
| SAXIHP3AWADDR22 | input | TCELL29:IMUX.IMUX2 |
| SAXIHP3AWADDR23 | input | TCELL29:IMUX.IMUX3 |
| SAXIHP3AWADDR24 | input | TCELL30:IMUX.IMUX4 |
| SAXIHP3AWADDR25 | input | TCELL30:IMUX.IMUX5 |
| SAXIHP3AWADDR26 | input | TCELL30:IMUX.IMUX6 |
| SAXIHP3AWADDR27 | input | TCELL30:IMUX.IMUX7 |
| SAXIHP3AWADDR28 | input | TCELL31:IMUX.IMUX2 |
| SAXIHP3AWADDR29 | input | TCELL31:IMUX.IMUX3 |
| SAXIHP3AWADDR3 | input | TCELL24:IMUX.IMUX3 |
| SAXIHP3AWADDR30 | input | TCELL31:IMUX.IMUX4 |
| SAXIHP3AWADDR31 | input | TCELL31:IMUX.IMUX5 |
| SAXIHP3AWADDR4 | input | TCELL25:IMUX.IMUX0 |
| SAXIHP3AWADDR5 | input | TCELL25:IMUX.IMUX1 |
| SAXIHP3AWADDR6 | input | TCELL25:IMUX.IMUX2 |
| SAXIHP3AWADDR7 | input | TCELL25:IMUX.IMUX3 |
| SAXIHP3AWADDR8 | input | TCELL26:IMUX.IMUX0 |
| SAXIHP3AWADDR9 | input | TCELL26:IMUX.IMUX1 |
| SAXIHP3AWBURST0 | input | TCELL29:IMUX.IMUX4 |
| SAXIHP3AWBURST1 | input | TCELL30:IMUX.IMUX10 |
| SAXIHP3AWCACHE0 | input | TCELL28:IMUX.IMUX4 |
| SAXIHP3AWCACHE1 | input | TCELL28:IMUX.IMUX5 |
| SAXIHP3AWCACHE2 | input | TCELL29:IMUX.IMUX7 |
| SAXIHP3AWCACHE3 | input | TCELL29:IMUX.IMUX8 |
| SAXIHP3AWID0 | input | TCELL30:IMUX.IMUX0 |
| SAXIHP3AWID1 | input | TCELL30:IMUX.IMUX1 |
| SAXIHP3AWID2 | input | TCELL30:IMUX.IMUX2 |
| SAXIHP3AWID3 | input | TCELL30:IMUX.IMUX3 |
| SAXIHP3AWID4 | input | TCELL31:IMUX.IMUX0 |
| SAXIHP3AWID5 | input | TCELL31:IMUX.IMUX1 |
| SAXIHP3AWLEN0 | input | TCELL31:IMUX.IMUX6 |
| SAXIHP3AWLEN1 | input | TCELL31:IMUX.IMUX7 |
| SAXIHP3AWLEN2 | input | TCELL31:IMUX.IMUX8 |
| SAXIHP3AWLEN3 | input | TCELL31:IMUX.IMUX9 |
| SAXIHP3AWLOCK0 | input | TCELL29:IMUX.IMUX5 |
| SAXIHP3AWLOCK1 | input | TCELL29:IMUX.IMUX6 |
| SAXIHP3AWPROT0 | input | TCELL28:IMUX.IMUX6 |
| SAXIHP3AWPROT1 | input | TCELL28:IMUX.IMUX7 |
| SAXIHP3AWPROT2 | input | TCELL28:IMUX.IMUX8 |
| SAXIHP3AWQOS0 | input | TCELL30:IMUX.IMUX23 |
| SAXIHP3AWQOS1 | input | TCELL30:IMUX.IMUX24 |
| SAXIHP3AWQOS2 | input | TCELL31:IMUX.IMUX23 |
| SAXIHP3AWQOS3 | input | TCELL31:IMUX.IMUX24 |
| SAXIHP3AWREADY | output | TCELL28:OUT0.TMIN |
| SAXIHP3AWSIZE0 | input | TCELL30:IMUX.IMUX8 |
| SAXIHP3AWSIZE1 | input | TCELL30:IMUX.IMUX9 |
| SAXIHP3AWVALID | input | TCELL28:IMUX.IMUX9 |
| SAXIHP3BID0 | output | TCELL28:OUT2.TMIN |
| SAXIHP3BID1 | output | TCELL28:OUT3.TMIN |
| SAXIHP3BID2 | output | TCELL29:OUT0.TMIN |
| SAXIHP3BID3 | output | TCELL29:OUT1.TMIN |
| SAXIHP3BID4 | output | TCELL29:OUT2.TMIN |
| SAXIHP3BID5 | output | TCELL29:OUT3.TMIN |
| SAXIHP3BREADY | input | TCELL28:IMUX.IMUX21 |
| SAXIHP3BRESP0 | output | TCELL26:OUT0.TMIN |
| SAXIHP3BRESP1 | output | TCELL26:OUT1.TMIN |
| SAXIHP3BVALID | output | TCELL28:OUT4.TMIN |
| SAXIHP3RACOUNT0 | output | TCELL24:OUT11.TMIN |
| SAXIHP3RACOUNT1 | output | TCELL24:OUT12.TMIN |
| SAXIHP3RACOUNT2 | output | TCELL24:OUT13.TMIN |
| SAXIHP3RCOUNT0 | output | TCELL25:OUT11.TMIN |
| SAXIHP3RCOUNT1 | output | TCELL25:OUT12.TMIN |
| SAXIHP3RCOUNT2 | output | TCELL25:OUT13.TMIN |
| SAXIHP3RCOUNT3 | output | TCELL25:OUT14.TMIN |
| SAXIHP3RCOUNT4 | output | TCELL26:OUT10.TMIN |
| SAXIHP3RCOUNT5 | output | TCELL26:OUT11.TMIN |
| SAXIHP3RCOUNT6 | output | TCELL26:OUT12.TMIN |
| SAXIHP3RCOUNT7 | output | TCELL26:OUT13.TMIN |
| SAXIHP3RDATA0 | output | TCELL24:OUT3.TMIN |
| SAXIHP3RDATA1 | output | TCELL24:OUT4.TMIN |
| SAXIHP3RDATA10 | output | TCELL26:OUT4.TMIN |
| SAXIHP3RDATA11 | output | TCELL26:OUT5.TMIN |
| SAXIHP3RDATA12 | output | TCELL27:OUT1.TMIN |
| SAXIHP3RDATA13 | output | TCELL27:OUT2.TMIN |
| SAXIHP3RDATA14 | output | TCELL27:OUT3.TMIN |
| SAXIHP3RDATA15 | output | TCELL27:OUT4.TMIN |
| SAXIHP3RDATA16 | output | TCELL28:OUT5.TMIN |
| SAXIHP3RDATA17 | output | TCELL28:OUT6.TMIN |
| SAXIHP3RDATA18 | output | TCELL28:OUT7.TMIN |
| SAXIHP3RDATA19 | output | TCELL28:OUT8.TMIN |
| SAXIHP3RDATA2 | output | TCELL24:OUT5.TMIN |
| SAXIHP3RDATA20 | output | TCELL29:OUT4.TMIN |
| SAXIHP3RDATA21 | output | TCELL29:OUT5.TMIN |
| SAXIHP3RDATA22 | output | TCELL29:OUT6.TMIN |
| SAXIHP3RDATA23 | output | TCELL29:OUT7.TMIN |
| SAXIHP3RDATA24 | output | TCELL30:OUT0.TMIN |
| SAXIHP3RDATA25 | output | TCELL30:OUT1.TMIN |
| SAXIHP3RDATA26 | output | TCELL30:OUT2.TMIN |
| SAXIHP3RDATA27 | output | TCELL30:OUT3.TMIN |
| SAXIHP3RDATA28 | output | TCELL31:OUT1.TMIN |
| SAXIHP3RDATA29 | output | TCELL31:OUT2.TMIN |
| SAXIHP3RDATA3 | output | TCELL24:OUT6.TMIN |
| SAXIHP3RDATA30 | output | TCELL31:OUT3.TMIN |
| SAXIHP3RDATA31 | output | TCELL31:OUT4.TMIN |
| SAXIHP3RDATA32 | output | TCELL24:OUT7.TMIN |
| SAXIHP3RDATA33 | output | TCELL24:OUT8.TMIN |
| SAXIHP3RDATA34 | output | TCELL24:OUT9.TMIN |
| SAXIHP3RDATA35 | output | TCELL24:OUT10.TMIN |
| SAXIHP3RDATA36 | output | TCELL25:OUT7.TMIN |
| SAXIHP3RDATA37 | output | TCELL25:OUT8.TMIN |
| SAXIHP3RDATA38 | output | TCELL25:OUT9.TMIN |
| SAXIHP3RDATA39 | output | TCELL25:OUT10.TMIN |
| SAXIHP3RDATA4 | output | TCELL25:OUT3.TMIN |
| SAXIHP3RDATA40 | output | TCELL26:OUT6.TMIN |
| SAXIHP3RDATA41 | output | TCELL26:OUT7.TMIN |
| SAXIHP3RDATA42 | output | TCELL26:OUT8.TMIN |
| SAXIHP3RDATA43 | output | TCELL26:OUT9.TMIN |
| SAXIHP3RDATA44 | output | TCELL27:OUT5.TMIN |
| SAXIHP3RDATA45 | output | TCELL27:OUT6.TMIN |
| SAXIHP3RDATA46 | output | TCELL27:OUT7.TMIN |
| SAXIHP3RDATA47 | output | TCELL27:OUT8.TMIN |
| SAXIHP3RDATA48 | output | TCELL28:OUT9.TMIN |
| SAXIHP3RDATA49 | output | TCELL28:OUT10.TMIN |
| SAXIHP3RDATA5 | output | TCELL25:OUT4.TMIN |
| SAXIHP3RDATA50 | output | TCELL28:OUT11.TMIN |
| SAXIHP3RDATA51 | output | TCELL28:OUT12.TMIN |
| SAXIHP3RDATA52 | output | TCELL29:OUT8.TMIN |
| SAXIHP3RDATA53 | output | TCELL29:OUT9.TMIN |
| SAXIHP3RDATA54 | output | TCELL29:OUT10.TMIN |
| SAXIHP3RDATA55 | output | TCELL29:OUT11.TMIN |
| SAXIHP3RDATA56 | output | TCELL30:OUT4.TMIN |
| SAXIHP3RDATA57 | output | TCELL30:OUT5.TMIN |
| SAXIHP3RDATA58 | output | TCELL30:OUT6.TMIN |
| SAXIHP3RDATA59 | output | TCELL30:OUT7.TMIN |
| SAXIHP3RDATA6 | output | TCELL25:OUT5.TMIN |
| SAXIHP3RDATA60 | output | TCELL31:OUT5.TMIN |
| SAXIHP3RDATA61 | output | TCELL31:OUT6.TMIN |
| SAXIHP3RDATA62 | output | TCELL31:OUT7.TMIN |
| SAXIHP3RDATA63 | output | TCELL31:OUT8.TMIN |
| SAXIHP3RDATA7 | output | TCELL25:OUT6.TMIN |
| SAXIHP3RDATA8 | output | TCELL26:OUT2.TMIN |
| SAXIHP3RDATA9 | output | TCELL26:OUT3.TMIN |
| SAXIHP3RDISSUECAP1EN | input | TCELL24:IMUX.IMUX25 |
| SAXIHP3RID0 | output | TCELL24:OUT0.TMIN |
| SAXIHP3RID1 | output | TCELL24:OUT1.TMIN |
| SAXIHP3RID2 | output | TCELL24:OUT2.TMIN |
| SAXIHP3RID3 | output | TCELL25:OUT0.TMIN |
| SAXIHP3RID4 | output | TCELL25:OUT1.TMIN |
| SAXIHP3RID5 | output | TCELL25:OUT2.TMIN |
| SAXIHP3RLAST | output | TCELL27:OUT11.TMIN |
| SAXIHP3RREADY | input | TCELL27:IMUX.IMUX21 |
| SAXIHP3RRESP0 | output | TCELL27:OUT9.TMIN |
| SAXIHP3RRESP1 | output | TCELL27:OUT10.TMIN |
| SAXIHP3RVALID | output | TCELL27:OUT12.TMIN |
| SAXIHP3WACOUNT0 | output | TCELL29:OUT12.TMIN |
| SAXIHP3WACOUNT1 | output | TCELL29:OUT13.TMIN |
| SAXIHP3WACOUNT2 | output | TCELL30:OUT12.TMIN |
| SAXIHP3WACOUNT3 | output | TCELL30:OUT13.TMIN |
| SAXIHP3WACOUNT4 | output | TCELL31:OUT13.TMIN |
| SAXIHP3WACOUNT5 | output | TCELL31:OUT14.TMIN |
| SAXIHP3WCOUNT0 | output | TCELL30:OUT8.TMIN |
| SAXIHP3WCOUNT1 | output | TCELL30:OUT9.TMIN |
| SAXIHP3WCOUNT2 | output | TCELL30:OUT10.TMIN |
| SAXIHP3WCOUNT3 | output | TCELL30:OUT11.TMIN |
| SAXIHP3WCOUNT4 | output | TCELL31:OUT9.TMIN |
| SAXIHP3WCOUNT5 | output | TCELL31:OUT10.TMIN |
| SAXIHP3WCOUNT6 | output | TCELL31:OUT11.TMIN |
| SAXIHP3WCOUNT7 | output | TCELL31:OUT12.TMIN |
| SAXIHP3WDATA0 | input | TCELL24:IMUX.IMUX4 |
| SAXIHP3WDATA1 | input | TCELL24:IMUX.IMUX5 |
| SAXIHP3WDATA10 | input | TCELL26:IMUX.IMUX6 |
| SAXIHP3WDATA11 | input | TCELL26:IMUX.IMUX7 |
| SAXIHP3WDATA12 | input | TCELL27:IMUX.IMUX4 |
| SAXIHP3WDATA13 | input | TCELL27:IMUX.IMUX5 |
| SAXIHP3WDATA14 | input | TCELL27:IMUX.IMUX6 |
| SAXIHP3WDATA15 | input | TCELL27:IMUX.IMUX7 |
| SAXIHP3WDATA16 | input | TCELL28:IMUX.IMUX12 |
| SAXIHP3WDATA17 | input | TCELL28:IMUX.IMUX13 |
| SAXIHP3WDATA18 | input | TCELL28:IMUX.IMUX14 |
| SAXIHP3WDATA19 | input | TCELL28:IMUX.IMUX15 |
| SAXIHP3WDATA2 | input | TCELL24:IMUX.IMUX6 |
| SAXIHP3WDATA20 | input | TCELL29:IMUX.IMUX13 |
| SAXIHP3WDATA21 | input | TCELL29:IMUX.IMUX14 |
| SAXIHP3WDATA22 | input | TCELL29:IMUX.IMUX15 |
| SAXIHP3WDATA23 | input | TCELL29:IMUX.IMUX16 |
| SAXIHP3WDATA24 | input | TCELL30:IMUX.IMUX11 |
| SAXIHP3WDATA25 | input | TCELL30:IMUX.IMUX12 |
| SAXIHP3WDATA26 | input | TCELL30:IMUX.IMUX13 |
| SAXIHP3WDATA27 | input | TCELL30:IMUX.IMUX14 |
| SAXIHP3WDATA28 | input | TCELL31:IMUX.IMUX10 |
| SAXIHP3WDATA29 | input | TCELL31:IMUX.IMUX11 |
| SAXIHP3WDATA3 | input | TCELL24:IMUX.IMUX7 |
| SAXIHP3WDATA30 | input | TCELL31:IMUX.IMUX12 |
| SAXIHP3WDATA31 | input | TCELL31:IMUX.IMUX13 |
| SAXIHP3WDATA32 | input | TCELL24:IMUX.IMUX8 |
| SAXIHP3WDATA33 | input | TCELL24:IMUX.IMUX9 |
| SAXIHP3WDATA34 | input | TCELL24:IMUX.IMUX10 |
| SAXIHP3WDATA35 | input | TCELL24:IMUX.IMUX11 |
| SAXIHP3WDATA36 | input | TCELL25:IMUX.IMUX8 |
| SAXIHP3WDATA37 | input | TCELL25:IMUX.IMUX9 |
| SAXIHP3WDATA38 | input | TCELL25:IMUX.IMUX10 |
| SAXIHP3WDATA39 | input | TCELL25:IMUX.IMUX11 |
| SAXIHP3WDATA4 | input | TCELL25:IMUX.IMUX4 |
| SAXIHP3WDATA40 | input | TCELL26:IMUX.IMUX8 |
| SAXIHP3WDATA41 | input | TCELL26:IMUX.IMUX9 |
| SAXIHP3WDATA42 | input | TCELL26:IMUX.IMUX10 |
| SAXIHP3WDATA43 | input | TCELL26:IMUX.IMUX11 |
| SAXIHP3WDATA44 | input | TCELL27:IMUX.IMUX8 |
| SAXIHP3WDATA45 | input | TCELL27:IMUX.IMUX9 |
| SAXIHP3WDATA46 | input | TCELL27:IMUX.IMUX10 |
| SAXIHP3WDATA47 | input | TCELL27:IMUX.IMUX11 |
| SAXIHP3WDATA48 | input | TCELL28:IMUX.IMUX16 |
| SAXIHP3WDATA49 | input | TCELL28:IMUX.IMUX17 |
| SAXIHP3WDATA5 | input | TCELL25:IMUX.IMUX5 |
| SAXIHP3WDATA50 | input | TCELL28:IMUX.IMUX18 |
| SAXIHP3WDATA51 | input | TCELL28:IMUX.IMUX19 |
| SAXIHP3WDATA52 | input | TCELL29:IMUX.IMUX17 |
| SAXIHP3WDATA53 | input | TCELL29:IMUX.IMUX18 |
| SAXIHP3WDATA54 | input | TCELL29:IMUX.IMUX19 |
| SAXIHP3WDATA55 | input | TCELL29:IMUX.IMUX20 |
| SAXIHP3WDATA56 | input | TCELL30:IMUX.IMUX15 |
| SAXIHP3WDATA57 | input | TCELL30:IMUX.IMUX16 |
| SAXIHP3WDATA58 | input | TCELL30:IMUX.IMUX17 |
| SAXIHP3WDATA59 | input | TCELL30:IMUX.IMUX18 |
| SAXIHP3WDATA6 | input | TCELL25:IMUX.IMUX6 |
| SAXIHP3WDATA60 | input | TCELL31:IMUX.IMUX14 |
| SAXIHP3WDATA61 | input | TCELL31:IMUX.IMUX15 |
| SAXIHP3WDATA62 | input | TCELL31:IMUX.IMUX16 |
| SAXIHP3WDATA63 | input | TCELL31:IMUX.IMUX17 |
| SAXIHP3WDATA7 | input | TCELL25:IMUX.IMUX7 |
| SAXIHP3WDATA8 | input | TCELL26:IMUX.IMUX4 |
| SAXIHP3WDATA9 | input | TCELL26:IMUX.IMUX5 |
| SAXIHP3WID0 | input | TCELL28:IMUX.IMUX10 |
| SAXIHP3WID1 | input | TCELL28:IMUX.IMUX11 |
| SAXIHP3WID2 | input | TCELL29:IMUX.IMUX9 |
| SAXIHP3WID3 | input | TCELL29:IMUX.IMUX10 |
| SAXIHP3WID4 | input | TCELL29:IMUX.IMUX11 |
| SAXIHP3WID5 | input | TCELL29:IMUX.IMUX12 |
| SAXIHP3WLAST | input | TCELL26:IMUX.IMUX16 |
| SAXIHP3WREADY | output | TCELL28:OUT1.TMIN |
| SAXIHP3WRISSUECAP1EN | input | TCELL31:IMUX.IMUX22 |
| SAXIHP3WSTRB0 | input | TCELL26:IMUX.IMUX12 |
| SAXIHP3WSTRB1 | input | TCELL26:IMUX.IMUX13 |
| SAXIHP3WSTRB2 | input | TCELL26:IMUX.IMUX14 |
| SAXIHP3WSTRB3 | input | TCELL26:IMUX.IMUX15 |
| SAXIHP3WSTRB4 | input | TCELL27:IMUX.IMUX12 |
| SAXIHP3WSTRB5 | input | TCELL27:IMUX.IMUX13 |
| SAXIHP3WSTRB6 | input | TCELL27:IMUX.IMUX14 |
| SAXIHP3WSTRB7 | input | TCELL27:IMUX.IMUX15 |
| SAXIHP3WVALID | input | TCELL28:IMUX.IMUX20 |
| TESTA9MBISTDATAIN | input | TCELL47:IMUX.IMUX46 |
| TESTA9MBISTDSHIFT | input | TCELL48:IMUX.IMUX47 |
| TESTA9MBISTENABLEN | input | TCELL49:IMUX.IMUX45 |
| TESTA9MBISTRESET | input | TCELL49:IMUX.IMUX46 |
| TESTA9MBISTRESULT0 | output | TCELL47:OUT21.TMIN |
| TESTA9MBISTRESULT1 | output | TCELL47:OUT20.TMIN |
| TESTA9MBISTRESULT2 | output | TCELL48:OUT21.TMIN |
| TESTA9MBISTRESULT3 | output | TCELL48:OUT20.TMIN |
| TESTA9MBISTRESULT4 | output | TCELL49:OUT21.TMIN |
| TESTA9MBISTRESULT5 | output | TCELL49:OUT20.TMIN |
| TESTA9MBISTRUN | input | TCELL48:IMUX.IMUX46 |
| TESTA9MBISTSHIFT | input | TCELL47:IMUX.IMUX47 |
| TESTAMUXENABLEB | input | TCELL97:IMUX.IMUX45 |
| TESTBGAMUXSEL0 | input | TCELL97:IMUX.IMUX47 |
| TESTBGAMUXSEL1 | input | TCELL97:IMUX.IMUX46 |
| TESTBGAMUXSEL2 | input | TCELL98:IMUX.IMUX46 |
| TESTBGAMUXSEL3 | input | TCELL98:IMUX.IMUX45 |
| TESTBGAMUXSEL4 | input | TCELL98:IMUX.IMUX44 |
| TESTBGPOWERDOWN | input | TCELL98:IMUX.IMUX47 |
| TESTBSCENN | input | TCELL49:IMUX.IMUX47 |
| TESTDFTRAMBYPN | input | TCELL53:IMUX.IMUX44 |
| TESTDIVCLKOUT0 | output | TCELL90:OUT23.TMIN |
| TESTDIVCLKOUT1 | output | TCELL90:OUT22.TMIN |
| TESTDIVCLKOUT10 | output | TCELL92:OUT21.TMIN |
| TESTDIVCLKOUT11 | output | TCELL92:OUT20.TMIN |
| TESTDIVCLKOUT12 | output | TCELL93:OUT23.TMIN |
| TESTDIVCLKOUT13 | output | TCELL93:OUT22.TMIN |
| TESTDIVCLKOUT14 | output | TCELL93:OUT21.TMIN |
| TESTDIVCLKOUT15 | output | TCELL93:OUT20.TMIN |
| TESTDIVCLKOUT16 | output | TCELL94:OUT23.TMIN |
| TESTDIVCLKOUT17 | output | TCELL94:OUT22.TMIN |
| TESTDIVCLKOUT18 | output | TCELL94:OUT21.TMIN |
| TESTDIVCLKOUT19 | output | TCELL94:OUT20.TMIN |
| TESTDIVCLKOUT2 | output | TCELL90:OUT21.TMIN |
| TESTDIVCLKOUT20 | output | TCELL95:OUT23.TMIN |
| TESTDIVCLKOUT3 | output | TCELL90:OUT20.TMIN |
| TESTDIVCLKOUT4 | output | TCELL91:OUT23.TMIN |
| TESTDIVCLKOUT5 | output | TCELL91:OUT22.TMIN |
| TESTDIVCLKOUT6 | output | TCELL91:OUT21.TMIN |
| TESTDIVCLKOUT7 | output | TCELL91:OUT20.TMIN |
| TESTDIVCLKOUT8 | output | TCELL92:OUT23.TMIN |
| TESTDIVCLKOUT9 | output | TCELL92:OUT22.TMIN |
| TESTDIVCLKOUTPREOPCGENABLEN | input | TCELL95:IMUX.IMUX47 |
| TESTDIVIDERRESETN | input | TCELL52:IMUX.IMUX44 |
| TESTDIVIDERUPDATETOG | input | TCELL90:IMUX.IMUX44 |
| TESTEDTBYPASS | input | TCELL59:IMUX.IMUX46 |
| TESTEDTCHANNELSIN0 | input | TCELL57:IMUX.IMUX46 |
| TESTEDTCHANNELSIN1 | input | TCELL58:IMUX.IMUX47 |
| TESTEDTCHANNELSIN2 | input | TCELL58:IMUX.IMUX46 |
| TESTEDTCHANNELSIN3 | input | TCELL58:IMUX.IMUX45 |
| TESTEDTCHANNELSIN4 | input | TCELL58:IMUX.IMUX44 |
| TESTEDTCHANNELSIN5 | input | TCELL59:IMUX.IMUX45 |
| TESTEDTCHANNELSIN6 | input | TCELL59:IMUX.IMUX44 |
| TESTEDTCHANNELSOUT0 | output | TCELL58:OUT23.TMIN |
| TESTEDTCHANNELSOUT1 | output | TCELL58:OUT22.TMIN |
| TESTEDTCHANNELSOUT2 | output | TCELL58:OUT21.TMIN |
| TESTEDTCHANNELSOUT3 | output | TCELL59:OUT23.TMIN |
| TESTEDTCHANNELSOUT4 | output | TCELL59:OUT22.TMIN |
| TESTEDTCHANNELSOUT5 | output | TCELL59:OUT21.TMIN |
| TESTEDTCHANNELSOUT6 | output | TCELL59:OUT20.TMIN |
| TESTEDTCLOCK | input | TCELL59:IMUX.CLK1 |
| TESTEDTUPDATE | input | TCELL59:IMUX.IMUX47 |
| TESTMBISTCOMPSTAT | output | TCELL53:OUT21.TMIN |
| TESTMBISTMODEN | input | TCELL55:IMUX.IMUX44 |
| TESTMBISTTAPTCK | input | TCELL57:IMUX.CLK1 |
| TESTMBISTTAPTDI | input | TCELL54:IMUX.IMUX45 |
| TESTMBISTTAPTDO | output | TCELL53:OUT23.TMIN |
| TESTMBISTTAPTDOENABLE | output | TCELL53:OUT22.TMIN |
| TESTMBISTTAPTMS | input | TCELL54:IMUX.IMUX44 |
| TESTMBISTTAPTRST | input | TCELL55:IMUX.IMUX45 |
| TESTPLLCONFIGREADY0 | output | TCELL89:OUT23.TMIN |
| TESTPLLCONFIGREADY1 | output | TCELL89:OUT22.TMIN |
| TESTPLLCONFIGREADY2 | output | TCELL89:OUT21.TMIN |
| TESTPLLCONFIGUPDATE0 | input | TCELL90:IMUX.IMUX47 |
| TESTPLLCONFIGUPDATE1 | input | TCELL90:IMUX.IMUX46 |
| TESTPLLCONFIGUPDATE2 | input | TCELL90:IMUX.IMUX45 |
| TESTPLLFBTESTN0 | input | TCELL94:IMUX.IMUX47 |
| TESTPLLFBTESTN1 | input | TCELL95:IMUX.IMUX46 |
| TESTPLLFBTESTN2 | input | TCELL95:IMUX.IMUX45 |
| TESTPLLFEEDBACKDIV0 | output | TCELL97:OUT23.TMIN |
| TESTPLLFEEDBACKDIV1 | output | TCELL97:OUT22.TMIN |
| TESTPLLFEEDBACKDIV2 | output | TCELL97:OUT21.TMIN |
| TESTPLLLOCK0 | output | TCELL96:OUT23.TMIN |
| TESTPLLLOCK1 | output | TCELL96:OUT22.TMIN |
| TESTPLLLOCK2 | output | TCELL96:OUT21.TMIN |
| TESTPLLPOWERDOWNN | input | TCELL96:IMUX.IMUX46 |
| TESTPLLREFCLKCPU | input | TCELL89:IMUX.CLK1 |
| TESTPLLREFCLKDDR | input | TCELL90:IMUX.CLK1 |
| TESTPLLREFCLKENN0 | input | TCELL91:IMUX.IMUX47 |
| TESTPLLREFCLKENN1 | input | TCELL91:IMUX.IMUX46 |
| TESTPLLREFCLKENN2 | input | TCELL91:IMUX.IMUX45 |
| TESTPLLREFCLKIOU | input | TCELL91:IMUX.CLK1 |
| TESTPLLRESET | input | TCELL96:IMUX.IMUX47 |
| TESTPSSCLOCKDR | input | TCELL51:IMUX.CLK1 |
| TESTPSSEXTEST | input | TCELL50:IMUX.IMUX47 |
| TESTPSSEXTESTSMPL | input | TCELL50:IMUX.IMUX46 |
| TESTPSSINTEST | input | TCELL50:IMUX.IMUX45 |
| TESTPSSRESETTAPB | input | TCELL51:IMUX.IMUX46 |
| TESTPSSSHIFTDR | input | TCELL51:IMUX.IMUX47 |
| TESTPSSTDI | input | TCELL51:IMUX.IMUX45 |
| TESTPSSTDO | output | TCELL51:OUT21.TMIN |
| TESTPSSUPDATEDR | input | TCELL51:IMUX.IMUX44 |
| TESTRESETMUXN | input | TCELL53:IMUX.IMUX45 |
| TESTSCANCLOCKCLOCKGEN | input | TCELL52:IMUX.IMUX46 |
| TESTSCANCLOCKOPCG0 | input | TCELL70:IMUX.CLK1 |
| TESTSCANCLOCKOPCG1 | input | TCELL71:IMUX.CLK1 |
| TESTSCANCLOCKOPCG10 | input | TCELL80:IMUX.CLK1 |
| TESTSCANCLOCKOPCG11 | input | TCELL81:IMUX.CLK1 |
| TESTSCANCLOCKOPCG12 | input | TCELL82:IMUX.CLK1 |
| TESTSCANCLOCKOPCG13 | input | TCELL83:IMUX.CLK1 |
| TESTSCANCLOCKOPCG14 | input | TCELL84:IMUX.CLK1 |
| TESTSCANCLOCKOPCG15 | input | TCELL85:IMUX.CLK1 |
| TESTSCANCLOCKOPCG16 | input | TCELL86:IMUX.CLK1 |
| TESTSCANCLOCKOPCG17 | input | TCELL87:IMUX.CLK1 |
| TESTSCANCLOCKOPCG18 | input | TCELL88:IMUX.CLK1 |
| TESTSCANCLOCKOPCG19 | input | TCELL92:IMUX.CLK1 |
| TESTSCANCLOCKOPCG2 | input | TCELL72:IMUX.CLK1 |
| TESTSCANCLOCKOPCG20 | input | TCELL93:IMUX.CLK1 |
| TESTSCANCLOCKOPCG21 | input | TCELL94:IMUX.CLK1 |
| TESTSCANCLOCKOPCG22 | input | TCELL95:IMUX.CLK1 |
| TESTSCANCLOCKOPCG23 | input | TCELL96:IMUX.CLK1 |
| TESTSCANCLOCKOPCG3 | input | TCELL73:IMUX.CLK1 |
| TESTSCANCLOCKOPCG4 | input | TCELL74:IMUX.CLK1 |
| TESTSCANCLOCKOPCG5 | input | TCELL75:IMUX.CLK1 |
| TESTSCANCLOCKOPCG6 | input | TCELL76:IMUX.CLK1 |
| TESTSCANCLOCKOPCG7 | input | TCELL77:IMUX.CLK1 |
| TESTSCANCLOCKOPCG8 | input | TCELL78:IMUX.CLK1 |
| TESTSCANCLOCKOPCG9 | input | TCELL79:IMUX.CLK1 |
| TESTSCANCLOCKPAD0 | input | TCELL65:IMUX.CLK1 |
| TESTSCANCLOCKPAD1 | input | TCELL66:IMUX.CLK1 |
| TESTSCANCLOCKPAD2 | input | TCELL67:IMUX.CLK1 |
| TESTSCANCLOCKPAD3 | input | TCELL68:IMUX.CLK1 |
| TESTSCANCLOCKPAD4 | input | TCELL69:IMUX.CLK1 |
| TESTSCANENABLEATSPEEDNONSCANFLOPSN | input | TCELL53:IMUX.IMUX46 |
| TESTSCANENABLEN | input | TCELL53:IMUX.IMUX47 |
| TESTSCANMODEATSPEEDN | input | TCELL54:IMUX.IMUX46 |
| TESTSCANMODEATSPEEDOPCGN0 | input | TCELL41:IMUX.IMUX47 |
| TESTSCANMODEATSPEEDOPCGN1 | input | TCELL41:IMUX.IMUX46 |
| TESTSCANMODEATSPEEDOPCGN10 | input | TCELL43:IMUX.IMUX45 |
| TESTSCANMODEATSPEEDOPCGN11 | input | TCELL43:IMUX.IMUX44 |
| TESTSCANMODEATSPEEDOPCGN12 | input | TCELL44:IMUX.IMUX47 |
| TESTSCANMODEATSPEEDOPCGN13 | input | TCELL44:IMUX.IMUX46 |
| TESTSCANMODEATSPEEDOPCGN14 | input | TCELL44:IMUX.IMUX45 |
| TESTSCANMODEATSPEEDOPCGN15 | input | TCELL44:IMUX.IMUX44 |
| TESTSCANMODEATSPEEDOPCGN16 | input | TCELL45:IMUX.IMUX47 |
| TESTSCANMODEATSPEEDOPCGN17 | input | TCELL45:IMUX.IMUX46 |
| TESTSCANMODEATSPEEDOPCGN18 | input | TCELL45:IMUX.IMUX45 |
| TESTSCANMODEATSPEEDOPCGN19 | input | TCELL45:IMUX.IMUX44 |
| TESTSCANMODEATSPEEDOPCGN2 | input | TCELL41:IMUX.IMUX45 |
| TESTSCANMODEATSPEEDOPCGN20 | input | TCELL46:IMUX.IMUX47 |
| TESTSCANMODEATSPEEDOPCGN21 | input | TCELL46:IMUX.IMUX46 |
| TESTSCANMODEATSPEEDOPCGN22 | input | TCELL46:IMUX.IMUX45 |
| TESTSCANMODEATSPEEDOPCGN23 | input | TCELL46:IMUX.IMUX44 |
| TESTSCANMODEATSPEEDOPCGN3 | input | TCELL41:IMUX.IMUX44 |
| TESTSCANMODEATSPEEDOPCGN4 | input | TCELL42:IMUX.IMUX47 |
| TESTSCANMODEATSPEEDOPCGN5 | input | TCELL42:IMUX.IMUX46 |
| TESTSCANMODEATSPEEDOPCGN6 | input | TCELL42:IMUX.IMUX45 |
| TESTSCANMODEATSPEEDOPCGN7 | input | TCELL42:IMUX.IMUX44 |
| TESTSCANMODEATSPEEDOPCGN8 | input | TCELL43:IMUX.IMUX47 |
| TESTSCANMODEATSPEEDOPCGN9 | input | TCELL43:IMUX.IMUX46 |
| TESTSCANMODEN | input | TCELL54:IMUX.IMUX47 |
| TESTSCANRESETN | input | TCELL52:IMUX.IMUX45 |
| TESTSLCRCONFIGCLOCK | input | TCELL58:IMUX.CLK1 |
| TESTSLCRCONFIGIN | input | TCELL57:IMUX.IMUX45 |
| TESTSLCRCONFIGOUT | output | TCELL58:OUT20.TMIN |
| TESTSLCRCONFIGRESETN | input | TCELL57:IMUX.IMUX44 |
| TESTSPAREIN0 | input | TCELL55:IMUX.IMUX47 |
| TESTSPAREIN1 | input | TCELL55:IMUX.IMUX46 |
| TESTSPAREIN2 | input | TCELL56:IMUX.IMUX47 |
| TESTSPAREIN3 | input | TCELL56:IMUX.IMUX46 |
| TESTSPAREIN4 | input | TCELL56:IMUX.IMUX45 |
| TESTSPAREIN5 | input | TCELL56:IMUX.IMUX44 |
| TESTSPAREIN6 | input | TCELL57:IMUX.IMUX47 |
| TESTSPAREOUT0 | output | TCELL56:OUT23.TMIN |
| TESTSPAREOUT1 | output | TCELL56:OUT22.TMIN |
| TESTSPAREOUT2 | output | TCELL56:OUT21.TMIN |
| TESTSPAREOUT3 | output | TCELL57:OUT23.TMIN |
| TESTSPAREOUT4 | output | TCELL57:OUT22.TMIN |
| TESTSPAREOUT5 | output | TCELL57:OUT21.TMIN |
| TESTSPAREOUT6 | output | TCELL57:OUT20.TMIN |
| TESTTRIGGEROPCGN | input | TCELL52:IMUX.IMUX47 |
Bel HCLK_PS_S
| Pin | Direction | Wires |
|---|
Bel HCLK_PS_N
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRWEB
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRVRN
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRVRP
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRA0
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRA1
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRA2
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRA3
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRA4
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRA5
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRA6
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRA7
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRA8
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRA9
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRA10
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRA11
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRA12
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRA14
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRA13
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRBA0
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRBA1
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRBA2
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRCASB
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRCKE
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRCKN
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRCKP
| Pin | Direction | Wires |
|---|
Bel IOPAD_PSCLK
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRCSB
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDM0
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDM1
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDM2
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDM3
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ0
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ1
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ2
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ3
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ4
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ5
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ6
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ7
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ8
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ9
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ10
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ11
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ12
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ13
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ14
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ15
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ16
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ17
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ18
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ19
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ20
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ21
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ22
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ23
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ24
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ25
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ26
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ27
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ28
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ29
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ30
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQ31
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQSN0
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQSN1
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQSN2
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQSN3
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQSP0
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQSP1
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQSP2
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDQSP3
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRDRSTB
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO0
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO1
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO2
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO3
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO4
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO5
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO6
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO7
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO8
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO9
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO10
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO11
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO12
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO13
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO14
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO15
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO16
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO17
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO18
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO19
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO20
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO21
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO22
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO23
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO24
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO25
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO26
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO27
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO28
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO29
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO30
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO31
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO32
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO33
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO34
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO35
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO36
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO37
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO38
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO39
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO40
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO41
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO42
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO43
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO44
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO45
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO46
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO47
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO48
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO49
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO50
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO51
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO52
| Pin | Direction | Wires |
|---|
Bel IOPAD_MIO53
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRODT
| Pin | Direction | Wires |
|---|
Bel IOPAD_PSPORB
| Pin | Direction | Wires |
|---|
Bel IOPAD_DDRRASB
| Pin | Direction | Wires |
|---|
Bel IOPAD_PSSRSTB
| Pin | Direction | Wires |
|---|
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:IMUX.IMUX0 | PS.SAXIHP0AWADDR0 |
| TCELL0:IMUX.IMUX1 | PS.SAXIHP0AWADDR1 |
| TCELL0:IMUX.IMUX2 | PS.SAXIHP0AWADDR2 |
| TCELL0:IMUX.IMUX3 | PS.SAXIHP0AWADDR3 |
| TCELL0:IMUX.IMUX4 | PS.SAXIHP0WDATA0 |
| TCELL0:IMUX.IMUX5 | PS.SAXIHP0WDATA1 |
| TCELL0:IMUX.IMUX6 | PS.SAXIHP0WDATA2 |
| TCELL0:IMUX.IMUX7 | PS.SAXIHP0WDATA3 |
| TCELL0:IMUX.IMUX8 | PS.SAXIHP0WDATA32 |
| TCELL0:IMUX.IMUX9 | PS.SAXIHP0WDATA33 |
| TCELL0:IMUX.IMUX10 | PS.SAXIHP0WDATA34 |
| TCELL0:IMUX.IMUX11 | PS.SAXIHP0WDATA35 |
| TCELL0:IMUX.IMUX12 | PS.SAXIHP0ARID0 |
| TCELL0:IMUX.IMUX13 | PS.SAXIHP0ARID1 |
| TCELL0:IMUX.IMUX14 | PS.SAXIHP0ARID2 |
| TCELL0:IMUX.IMUX15 | PS.SAXIHP0ARID3 |
| TCELL0:IMUX.IMUX16 | PS.SAXIHP0ARADDR0 |
| TCELL0:IMUX.IMUX17 | PS.SAXIHP0ARADDR1 |
| TCELL0:IMUX.IMUX18 | PS.SAXIHP0ARADDR2 |
| TCELL0:IMUX.IMUX19 | PS.SAXIHP0ARADDR3 |
| TCELL0:IMUX.IMUX20 | PS.SAXIHP0ARSIZE0 |
| TCELL0:IMUX.IMUX21 | PS.SAXIHP0ARSIZE1 |
| TCELL0:IMUX.IMUX22 | PS.SAXIHP0ARBURST0 |
| TCELL0:IMUX.IMUX23 | PS.SAXIHP0ARBURST1 |
| TCELL0:IMUX.IMUX24 | PS.SAXIHP0ARLOCK0 |
| TCELL0:IMUX.IMUX25 | PS.SAXIHP0RDISSUECAP1EN |
| TCELL0:OUT0.TMIN | PS.SAXIHP0RID0 |
| TCELL0:OUT1.TMIN | PS.SAXIHP0RID1 |
| TCELL0:OUT2.TMIN | PS.SAXIHP0RID2 |
| TCELL0:OUT3.TMIN | PS.SAXIHP0RDATA0 |
| TCELL0:OUT4.TMIN | PS.SAXIHP0RDATA1 |
| TCELL0:OUT5.TMIN | PS.SAXIHP0RDATA2 |
| TCELL0:OUT6.TMIN | PS.SAXIHP0RDATA3 |
| TCELL0:OUT7.TMIN | PS.SAXIHP0RDATA32 |
| TCELL0:OUT8.TMIN | PS.SAXIHP0RDATA33 |
| TCELL0:OUT9.TMIN | PS.SAXIHP0RDATA34 |
| TCELL0:OUT10.TMIN | PS.SAXIHP0RDATA35 |
| TCELL0:OUT11.TMIN | PS.SAXIHP0RACOUNT0 |
| TCELL0:OUT12.TMIN | PS.SAXIHP0RACOUNT1 |
| TCELL0:OUT13.TMIN | PS.SAXIHP0RACOUNT2 |
| TCELL0:OUT20.TMIN | PS.DEBUGDATA3 |
| TCELL0:OUT21.TMIN | PS.DEBUGDATA2 |
| TCELL0:OUT22.TMIN | PS.DEBUGDATA1 |
| TCELL0:OUT23.TMIN | PS.DEBUGDATA0 |
| TCELL1:IMUX.IMUX0 | PS.SAXIHP0AWADDR4 |
| TCELL1:IMUX.IMUX1 | PS.SAXIHP0AWADDR5 |
| TCELL1:IMUX.IMUX2 | PS.SAXIHP0AWADDR6 |
| TCELL1:IMUX.IMUX3 | PS.SAXIHP0AWADDR7 |
| TCELL1:IMUX.IMUX4 | PS.SAXIHP0WDATA4 |
| TCELL1:IMUX.IMUX5 | PS.SAXIHP0WDATA5 |
| TCELL1:IMUX.IMUX6 | PS.SAXIHP0WDATA6 |
| TCELL1:IMUX.IMUX7 | PS.SAXIHP0WDATA7 |
| TCELL1:IMUX.IMUX8 | PS.SAXIHP0WDATA36 |
| TCELL1:IMUX.IMUX9 | PS.SAXIHP0WDATA37 |
| TCELL1:IMUX.IMUX10 | PS.SAXIHP0WDATA38 |
| TCELL1:IMUX.IMUX11 | PS.SAXIHP0WDATA39 |
| TCELL1:IMUX.IMUX12 | PS.SAXIHP0ARID4 |
| TCELL1:IMUX.IMUX13 | PS.SAXIHP0ARID5 |
| TCELL1:IMUX.IMUX14 | PS.SAXIHP0ARADDR4 |
| TCELL1:IMUX.IMUX15 | PS.SAXIHP0ARADDR5 |
| TCELL1:IMUX.IMUX16 | PS.SAXIHP0ARADDR6 |
| TCELL1:IMUX.IMUX17 | PS.SAXIHP0ARADDR7 |
| TCELL1:IMUX.IMUX18 | PS.SAXIHP0ARLOCK1 |
| TCELL1:IMUX.IMUX19 | PS.SAXIHP0ARCACHE0 |
| TCELL1:IMUX.IMUX20 | PS.SAXIHP0ARCACHE1 |
| TCELL1:IMUX.IMUX21 | PS.SAXIHP0ARCACHE2 |
| TCELL1:IMUX.IMUX22 | PS.SAXIHP0ARCACHE3 |
| TCELL1:IMUX.IMUX23 | PS.SAXIHP0ARPROT0 |
| TCELL1:IMUX.IMUX24 | PS.SAXIHP0ARPROT1 |
| TCELL1:OUT0.TMIN | PS.SAXIHP0RID3 |
| TCELL1:OUT1.TMIN | PS.SAXIHP0RID4 |
| TCELL1:OUT2.TMIN | PS.SAXIHP0RID5 |
| TCELL1:OUT3.TMIN | PS.SAXIHP0RDATA4 |
| TCELL1:OUT4.TMIN | PS.SAXIHP0RDATA5 |
| TCELL1:OUT5.TMIN | PS.SAXIHP0RDATA6 |
| TCELL1:OUT6.TMIN | PS.SAXIHP0RDATA7 |
| TCELL1:OUT7.TMIN | PS.SAXIHP0RDATA36 |
| TCELL1:OUT8.TMIN | PS.SAXIHP0RDATA37 |
| TCELL1:OUT9.TMIN | PS.SAXIHP0RDATA38 |
| TCELL1:OUT10.TMIN | PS.SAXIHP0RDATA39 |
| TCELL1:OUT11.TMIN | PS.SAXIHP0RCOUNT0 |
| TCELL1:OUT12.TMIN | PS.SAXIHP0RCOUNT1 |
| TCELL1:OUT13.TMIN | PS.SAXIHP0RCOUNT2 |
| TCELL1:OUT14.TMIN | PS.SAXIHP0RCOUNT3 |
| TCELL1:OUT20.TMIN | PS.DEBUGDATA7 |
| TCELL1:OUT21.TMIN | PS.DEBUGDATA6 |
| TCELL1:OUT22.TMIN | PS.DEBUGDATA5 |
| TCELL1:OUT23.TMIN | PS.DEBUGDATA4 |
| TCELL2:IMUX.IMUX0 | PS.SAXIHP0AWADDR8 |
| TCELL2:IMUX.IMUX1 | PS.SAXIHP0AWADDR9 |
| TCELL2:IMUX.IMUX2 | PS.SAXIHP0AWADDR10 |
| TCELL2:IMUX.IMUX3 | PS.SAXIHP0AWADDR11 |
| TCELL2:IMUX.IMUX4 | PS.SAXIHP0WDATA8 |
| TCELL2:IMUX.IMUX5 | PS.SAXIHP0WDATA9 |
| TCELL2:IMUX.IMUX6 | PS.SAXIHP0WDATA10 |
| TCELL2:IMUX.IMUX7 | PS.SAXIHP0WDATA11 |
| TCELL2:IMUX.IMUX8 | PS.SAXIHP0WDATA40 |
| TCELL2:IMUX.IMUX9 | PS.SAXIHP0WDATA41 |
| TCELL2:IMUX.IMUX10 | PS.SAXIHP0WDATA42 |
| TCELL2:IMUX.IMUX11 | PS.SAXIHP0WDATA43 |
| TCELL2:IMUX.IMUX12 | PS.SAXIHP0WSTRB0 |
| TCELL2:IMUX.IMUX13 | PS.SAXIHP0WSTRB1 |
| TCELL2:IMUX.IMUX14 | PS.SAXIHP0WSTRB2 |
| TCELL2:IMUX.IMUX15 | PS.SAXIHP0WSTRB3 |
| TCELL2:IMUX.IMUX16 | PS.SAXIHP0WLAST |
| TCELL2:IMUX.IMUX17 | PS.SAXIHP0ARADDR8 |
| TCELL2:IMUX.IMUX18 | PS.SAXIHP0ARADDR9 |
| TCELL2:IMUX.IMUX19 | PS.SAXIHP0ARADDR10 |
| TCELL2:IMUX.IMUX20 | PS.SAXIHP0ARADDR11 |
| TCELL2:IMUX.IMUX21 | PS.SAXIHP0ARLEN0 |
| TCELL2:IMUX.IMUX22 | PS.SAXIHP0ARLEN1 |
| TCELL2:IMUX.IMUX23 | PS.SAXIHP0ARLEN2 |
| TCELL2:IMUX.IMUX24 | PS.SAXIHP0ARLEN3 |
| TCELL2:IMUX.IMUX25 | PS.SAXIHP0ARPROT2 |
| TCELL2:OUT0.TMIN | PS.SAXIHP0BRESP0 |
| TCELL2:OUT1.TMIN | PS.SAXIHP0BRESP1 |
| TCELL2:OUT2.TMIN | PS.SAXIHP0RDATA8 |
| TCELL2:OUT3.TMIN | PS.SAXIHP0RDATA9 |
| TCELL2:OUT4.TMIN | PS.SAXIHP0RDATA10 |
| TCELL2:OUT5.TMIN | PS.SAXIHP0RDATA11 |
| TCELL2:OUT6.TMIN | PS.SAXIHP0RDATA40 |
| TCELL2:OUT7.TMIN | PS.SAXIHP0RDATA41 |
| TCELL2:OUT8.TMIN | PS.SAXIHP0RDATA42 |
| TCELL2:OUT9.TMIN | PS.SAXIHP0RDATA43 |
| TCELL2:OUT10.TMIN | PS.SAXIHP0RCOUNT4 |
| TCELL2:OUT11.TMIN | PS.SAXIHP0RCOUNT5 |
| TCELL2:OUT12.TMIN | PS.SAXIHP0RCOUNT6 |
| TCELL2:OUT13.TMIN | PS.SAXIHP0RCOUNT7 |
| TCELL2:OUT20.TMIN | PS.DEBUGDATA11 |
| TCELL2:OUT21.TMIN | PS.DEBUGDATA10 |
| TCELL2:OUT22.TMIN | PS.DEBUGDATA9 |
| TCELL2:OUT23.TMIN | PS.DEBUGDATA8 |
| TCELL3:IMUX.IMUX0 | PS.SAXIHP0AWADDR12 |
| TCELL3:IMUX.IMUX1 | PS.SAXIHP0AWADDR13 |
| TCELL3:IMUX.IMUX2 | PS.SAXIHP0AWADDR14 |
| TCELL3:IMUX.IMUX3 | PS.SAXIHP0AWADDR15 |
| TCELL3:IMUX.IMUX4 | PS.SAXIHP0WDATA12 |
| TCELL3:IMUX.IMUX5 | PS.SAXIHP0WDATA13 |
| TCELL3:IMUX.IMUX6 | PS.SAXIHP0WDATA14 |
| TCELL3:IMUX.IMUX7 | PS.SAXIHP0WDATA15 |
| TCELL3:IMUX.IMUX8 | PS.SAXIHP0WDATA44 |
| TCELL3:IMUX.IMUX9 | PS.SAXIHP0WDATA45 |
| TCELL3:IMUX.IMUX10 | PS.SAXIHP0WDATA46 |
| TCELL3:IMUX.IMUX11 | PS.SAXIHP0WDATA47 |
| TCELL3:IMUX.IMUX12 | PS.SAXIHP0WSTRB4 |
| TCELL3:IMUX.IMUX13 | PS.SAXIHP0WSTRB5 |
| TCELL3:IMUX.IMUX14 | PS.SAXIHP0WSTRB6 |
| TCELL3:IMUX.IMUX15 | PS.SAXIHP0WSTRB7 |
| TCELL3:IMUX.IMUX16 | PS.SAXIHP0ARADDR12 |
| TCELL3:IMUX.IMUX17 | PS.SAXIHP0ARADDR13 |
| TCELL3:IMUX.IMUX18 | PS.SAXIHP0ARADDR14 |
| TCELL3:IMUX.IMUX19 | PS.SAXIHP0ARADDR15 |
| TCELL3:IMUX.IMUX20 | PS.SAXIHP0ARVALID |
| TCELL3:IMUX.IMUX21 | PS.SAXIHP0RREADY |
| TCELL3:IMUX.IMUX22 | PS.SAXIHP0ARQOS0 |
| TCELL3:IMUX.IMUX23 | PS.SAXIHP0ARQOS1 |
| TCELL3:IMUX.IMUX24 | PS.SAXIHP0ARQOS2 |
| TCELL3:IMUX.IMUX25 | PS.SAXIHP0ARQOS3 |
| TCELL3:OUT0.TMIN | PS.SAXIHP0ARREADY |
| TCELL3:OUT1.TMIN | PS.SAXIHP0RDATA12 |
| TCELL3:OUT2.TMIN | PS.SAXIHP0RDATA13 |
| TCELL3:OUT3.TMIN | PS.SAXIHP0RDATA14 |
| TCELL3:OUT4.TMIN | PS.SAXIHP0RDATA15 |
| TCELL3:OUT5.TMIN | PS.SAXIHP0RDATA44 |
| TCELL3:OUT6.TMIN | PS.SAXIHP0RDATA45 |
| TCELL3:OUT7.TMIN | PS.SAXIHP0RDATA46 |
| TCELL3:OUT8.TMIN | PS.SAXIHP0RDATA47 |
| TCELL3:OUT9.TMIN | PS.SAXIHP0RRESP0 |
| TCELL3:OUT10.TMIN | PS.SAXIHP0RRESP1 |
| TCELL3:OUT11.TMIN | PS.SAXIHP0RLAST |
| TCELL3:OUT12.TMIN | PS.SAXIHP0RVALID |
| TCELL3:OUT20.TMIN | PS.DEBUGDATA15 |
| TCELL3:OUT21.TMIN | PS.DEBUGDATA14 |
| TCELL3:OUT22.TMIN | PS.DEBUGDATA13 |
| TCELL3:OUT23.TMIN | PS.DEBUGDATA12 |
| TCELL4:IMUX.CLK0 | PS.SAXIHP0ACLK |
| TCELL4:IMUX.IMUX0 | PS.SAXIHP0AWADDR16 |
| TCELL4:IMUX.IMUX1 | PS.SAXIHP0AWADDR17 |
| TCELL4:IMUX.IMUX2 | PS.SAXIHP0AWADDR18 |
| TCELL4:IMUX.IMUX3 | PS.SAXIHP0AWADDR19 |
| TCELL4:IMUX.IMUX4 | PS.SAXIHP0AWCACHE0 |
| TCELL4:IMUX.IMUX5 | PS.SAXIHP0AWCACHE1 |
| TCELL4:IMUX.IMUX6 | PS.SAXIHP0AWPROT0 |
| TCELL4:IMUX.IMUX7 | PS.SAXIHP0AWPROT1 |
| TCELL4:IMUX.IMUX8 | PS.SAXIHP0AWPROT2 |
| TCELL4:IMUX.IMUX9 | PS.SAXIHP0AWVALID |
| TCELL4:IMUX.IMUX10 | PS.SAXIHP0WID0 |
| TCELL4:IMUX.IMUX11 | PS.SAXIHP0WID1 |
| TCELL4:IMUX.IMUX12 | PS.SAXIHP0WDATA16 |
| TCELL4:IMUX.IMUX13 | PS.SAXIHP0WDATA17 |
| TCELL4:IMUX.IMUX14 | PS.SAXIHP0WDATA18 |
| TCELL4:IMUX.IMUX15 | PS.SAXIHP0WDATA19 |
| TCELL4:IMUX.IMUX16 | PS.SAXIHP0WDATA48 |
| TCELL4:IMUX.IMUX17 | PS.SAXIHP0WDATA49 |
| TCELL4:IMUX.IMUX18 | PS.SAXIHP0WDATA50 |
| TCELL4:IMUX.IMUX19 | PS.SAXIHP0WDATA51 |
| TCELL4:IMUX.IMUX20 | PS.SAXIHP0WVALID |
| TCELL4:IMUX.IMUX21 | PS.SAXIHP0BREADY |
| TCELL4:IMUX.IMUX22 | PS.SAXIHP0ARADDR16 |
| TCELL4:IMUX.IMUX23 | PS.SAXIHP0ARADDR17 |
| TCELL4:IMUX.IMUX24 | PS.SAXIHP0ARADDR18 |
| TCELL4:IMUX.IMUX25 | PS.SAXIHP0ARADDR19 |
| TCELL4:OUT0.TMIN | PS.SAXIHP0AWREADY |
| TCELL4:OUT1.TMIN | PS.SAXIHP0WREADY |
| TCELL4:OUT2.TMIN | PS.SAXIHP0BID0 |
| TCELL4:OUT3.TMIN | PS.SAXIHP0BID1 |
| TCELL4:OUT4.TMIN | PS.SAXIHP0BVALID |
| TCELL4:OUT5.TMIN | PS.SAXIHP0RDATA16 |
| TCELL4:OUT6.TMIN | PS.SAXIHP0RDATA17 |
| TCELL4:OUT7.TMIN | PS.SAXIHP0RDATA18 |
| TCELL4:OUT8.TMIN | PS.SAXIHP0RDATA19 |
| TCELL4:OUT9.TMIN | PS.SAXIHP0RDATA48 |
| TCELL4:OUT10.TMIN | PS.SAXIHP0RDATA49 |
| TCELL4:OUT11.TMIN | PS.SAXIHP0RDATA50 |
| TCELL4:OUT12.TMIN | PS.SAXIHP0RDATA51 |
| TCELL4:OUT20.TMIN | PS.DEBUGDATA19 |
| TCELL4:OUT21.TMIN | PS.DEBUGDATA18 |
| TCELL4:OUT22.TMIN | PS.DEBUGDATA17 |
| TCELL4:OUT23.TMIN | PS.DEBUGDATA16 |
| TCELL5:IMUX.IMUX0 | PS.SAXIHP0AWADDR20 |
| TCELL5:IMUX.IMUX1 | PS.SAXIHP0AWADDR21 |
| TCELL5:IMUX.IMUX2 | PS.SAXIHP0AWADDR22 |
| TCELL5:IMUX.IMUX3 | PS.SAXIHP0AWADDR23 |
| TCELL5:IMUX.IMUX4 | PS.SAXIHP0AWBURST0 |
| TCELL5:IMUX.IMUX5 | PS.SAXIHP0AWLOCK0 |
| TCELL5:IMUX.IMUX6 | PS.SAXIHP0AWLOCK1 |
| TCELL5:IMUX.IMUX7 | PS.SAXIHP0AWCACHE2 |
| TCELL5:IMUX.IMUX8 | PS.SAXIHP0AWCACHE3 |
| TCELL5:IMUX.IMUX9 | PS.SAXIHP0WID2 |
| TCELL5:IMUX.IMUX10 | PS.SAXIHP0WID3 |
| TCELL5:IMUX.IMUX11 | PS.SAXIHP0WID4 |
| TCELL5:IMUX.IMUX12 | PS.SAXIHP0WID5 |
| TCELL5:IMUX.IMUX13 | PS.SAXIHP0WDATA20 |
| TCELL5:IMUX.IMUX14 | PS.SAXIHP0WDATA21 |
| TCELL5:IMUX.IMUX15 | PS.SAXIHP0WDATA22 |
| TCELL5:IMUX.IMUX16 | PS.SAXIHP0WDATA23 |
| TCELL5:IMUX.IMUX17 | PS.SAXIHP0WDATA52 |
| TCELL5:IMUX.IMUX18 | PS.SAXIHP0WDATA53 |
| TCELL5:IMUX.IMUX19 | PS.SAXIHP0WDATA54 |
| TCELL5:IMUX.IMUX20 | PS.SAXIHP0WDATA55 |
| TCELL5:IMUX.IMUX21 | PS.SAXIHP0ARADDR20 |
| TCELL5:IMUX.IMUX22 | PS.SAXIHP0ARADDR21 |
| TCELL5:IMUX.IMUX23 | PS.SAXIHP0ARADDR22 |
| TCELL5:IMUX.IMUX24 | PS.SAXIHP0ARADDR23 |
| TCELL5:OUT0.TMIN | PS.SAXIHP0BID2 |
| TCELL5:OUT1.TMIN | PS.SAXIHP0BID3 |
| TCELL5:OUT2.TMIN | PS.SAXIHP0BID4 |
| TCELL5:OUT3.TMIN | PS.SAXIHP0BID5 |
| TCELL5:OUT4.TMIN | PS.SAXIHP0RDATA20 |
| TCELL5:OUT5.TMIN | PS.SAXIHP0RDATA21 |
| TCELL5:OUT6.TMIN | PS.SAXIHP0RDATA22 |
| TCELL5:OUT7.TMIN | PS.SAXIHP0RDATA23 |
| TCELL5:OUT8.TMIN | PS.SAXIHP0RDATA52 |
| TCELL5:OUT9.TMIN | PS.SAXIHP0RDATA53 |
| TCELL5:OUT10.TMIN | PS.SAXIHP0RDATA54 |
| TCELL5:OUT11.TMIN | PS.SAXIHP0RDATA55 |
| TCELL5:OUT12.TMIN | PS.SAXIHP0WACOUNT0 |
| TCELL5:OUT13.TMIN | PS.SAXIHP0WACOUNT1 |
| TCELL5:OUT20.TMIN | PS.DEBUGDATA23 |
| TCELL5:OUT21.TMIN | PS.DEBUGDATA22 |
| TCELL5:OUT22.TMIN | PS.DEBUGDATA21 |
| TCELL5:OUT23.TMIN | PS.DEBUGDATA20 |
| TCELL6:IMUX.IMUX0 | PS.SAXIHP0AWID0 |
| TCELL6:IMUX.IMUX1 | PS.SAXIHP0AWID1 |
| TCELL6:IMUX.IMUX2 | PS.SAXIHP0AWID2 |
| TCELL6:IMUX.IMUX3 | PS.SAXIHP0AWID3 |
| TCELL6:IMUX.IMUX4 | PS.SAXIHP0AWADDR24 |
| TCELL6:IMUX.IMUX5 | PS.SAXIHP0AWADDR25 |
| TCELL6:IMUX.IMUX6 | PS.SAXIHP0AWADDR26 |
| TCELL6:IMUX.IMUX7 | PS.SAXIHP0AWADDR27 |
| TCELL6:IMUX.IMUX8 | PS.SAXIHP0AWSIZE0 |
| TCELL6:IMUX.IMUX9 | PS.SAXIHP0AWSIZE1 |
| TCELL6:IMUX.IMUX10 | PS.SAXIHP0AWBURST1 |
| TCELL6:IMUX.IMUX11 | PS.SAXIHP0WDATA24 |
| TCELL6:IMUX.IMUX12 | PS.SAXIHP0WDATA25 |
| TCELL6:IMUX.IMUX13 | PS.SAXIHP0WDATA26 |
| TCELL6:IMUX.IMUX14 | PS.SAXIHP0WDATA27 |
| TCELL6:IMUX.IMUX15 | PS.SAXIHP0WDATA56 |
| TCELL6:IMUX.IMUX16 | PS.SAXIHP0WDATA57 |
| TCELL6:IMUX.IMUX17 | PS.SAXIHP0WDATA58 |
| TCELL6:IMUX.IMUX18 | PS.SAXIHP0WDATA59 |
| TCELL6:IMUX.IMUX19 | PS.SAXIHP0ARADDR24 |
| TCELL6:IMUX.IMUX20 | PS.SAXIHP0ARADDR25 |
| TCELL6:IMUX.IMUX21 | PS.SAXIHP0ARADDR26 |
| TCELL6:IMUX.IMUX22 | PS.SAXIHP0ARADDR27 |
| TCELL6:IMUX.IMUX23 | PS.SAXIHP0AWQOS0 |
| TCELL6:IMUX.IMUX24 | PS.SAXIHP0AWQOS1 |
| TCELL6:OUT0.TMIN | PS.SAXIHP0RDATA24 |
| TCELL6:OUT1.TMIN | PS.SAXIHP0RDATA25 |
| TCELL6:OUT2.TMIN | PS.SAXIHP0RDATA26 |
| TCELL6:OUT3.TMIN | PS.SAXIHP0RDATA27 |
| TCELL6:OUT4.TMIN | PS.SAXIHP0RDATA56 |
| TCELL6:OUT5.TMIN | PS.SAXIHP0RDATA57 |
| TCELL6:OUT6.TMIN | PS.SAXIHP0RDATA58 |
| TCELL6:OUT7.TMIN | PS.SAXIHP0RDATA59 |
| TCELL6:OUT8.TMIN | PS.SAXIHP0WCOUNT0 |
| TCELL6:OUT9.TMIN | PS.SAXIHP0WCOUNT1 |
| TCELL6:OUT10.TMIN | PS.SAXIHP0WCOUNT2 |
| TCELL6:OUT11.TMIN | PS.SAXIHP0WCOUNT3 |
| TCELL6:OUT12.TMIN | PS.SAXIHP0WACOUNT2 |
| TCELL6:OUT13.TMIN | PS.SAXIHP0WACOUNT3 |
| TCELL6:OUT20.TMIN | PS.DEBUGDATA27 |
| TCELL6:OUT21.TMIN | PS.DEBUGDATA26 |
| TCELL6:OUT22.TMIN | PS.DEBUGDATA25 |
| TCELL6:OUT23.TMIN | PS.DEBUGDATA24 |
| TCELL7:IMUX.IMUX0 | PS.SAXIHP0AWID4 |
| TCELL7:IMUX.IMUX1 | PS.SAXIHP0AWID5 |
| TCELL7:IMUX.IMUX2 | PS.SAXIHP0AWADDR28 |
| TCELL7:IMUX.IMUX3 | PS.SAXIHP0AWADDR29 |
| TCELL7:IMUX.IMUX4 | PS.SAXIHP0AWADDR30 |
| TCELL7:IMUX.IMUX5 | PS.SAXIHP0AWADDR31 |
| TCELL7:IMUX.IMUX6 | PS.SAXIHP0AWLEN0 |
| TCELL7:IMUX.IMUX7 | PS.SAXIHP0AWLEN1 |
| TCELL7:IMUX.IMUX8 | PS.SAXIHP0AWLEN2 |
| TCELL7:IMUX.IMUX9 | PS.SAXIHP0AWLEN3 |
| TCELL7:IMUX.IMUX10 | PS.SAXIHP0WDATA28 |
| TCELL7:IMUX.IMUX11 | PS.SAXIHP0WDATA29 |
| TCELL7:IMUX.IMUX12 | PS.SAXIHP0WDATA30 |
| TCELL7:IMUX.IMUX13 | PS.SAXIHP0WDATA31 |
| TCELL7:IMUX.IMUX14 | PS.SAXIHP0WDATA60 |
| TCELL7:IMUX.IMUX15 | PS.SAXIHP0WDATA61 |
| TCELL7:IMUX.IMUX16 | PS.SAXIHP0WDATA62 |
| TCELL7:IMUX.IMUX17 | PS.SAXIHP0WDATA63 |
| TCELL7:IMUX.IMUX18 | PS.SAXIHP0ARADDR28 |
| TCELL7:IMUX.IMUX19 | PS.SAXIHP0ARADDR29 |
| TCELL7:IMUX.IMUX20 | PS.SAXIHP0ARADDR30 |
| TCELL7:IMUX.IMUX21 | PS.SAXIHP0ARADDR31 |
| TCELL7:IMUX.IMUX22 | PS.SAXIHP0WRISSUECAP1EN |
| TCELL7:IMUX.IMUX23 | PS.SAXIHP0AWQOS2 |
| TCELL7:IMUX.IMUX24 | PS.SAXIHP0AWQOS3 |
| TCELL7:OUT0.TMIN | PS.SAXIHP0ARESETN |
| TCELL7:OUT1.TMIN | PS.SAXIHP0RDATA28 |
| TCELL7:OUT2.TMIN | PS.SAXIHP0RDATA29 |
| TCELL7:OUT3.TMIN | PS.SAXIHP0RDATA30 |
| TCELL7:OUT4.TMIN | PS.SAXIHP0RDATA31 |
| TCELL7:OUT5.TMIN | PS.SAXIHP0RDATA60 |
| TCELL7:OUT6.TMIN | PS.SAXIHP0RDATA61 |
| TCELL7:OUT7.TMIN | PS.SAXIHP0RDATA62 |
| TCELL7:OUT8.TMIN | PS.SAXIHP0RDATA63 |
| TCELL7:OUT9.TMIN | PS.SAXIHP0WCOUNT4 |
| TCELL7:OUT10.TMIN | PS.SAXIHP0WCOUNT5 |
| TCELL7:OUT11.TMIN | PS.SAXIHP0WCOUNT6 |
| TCELL7:OUT12.TMIN | PS.SAXIHP0WCOUNT7 |
| TCELL7:OUT13.TMIN | PS.SAXIHP0WACOUNT4 |
| TCELL7:OUT14.TMIN | PS.SAXIHP0WACOUNT5 |
| TCELL7:OUT20.TMIN | PS.DEBUGDATA31 |
| TCELL7:OUT21.TMIN | PS.DEBUGDATA30 |
| TCELL7:OUT22.TMIN | PS.DEBUGDATA29 |
| TCELL7:OUT23.TMIN | PS.DEBUGDATA28 |
| TCELL8:IMUX.IMUX0 | PS.SAXIHP1AWADDR0 |
| TCELL8:IMUX.IMUX1 | PS.SAXIHP1AWADDR1 |
| TCELL8:IMUX.IMUX2 | PS.SAXIHP1AWADDR2 |
| TCELL8:IMUX.IMUX3 | PS.SAXIHP1AWADDR3 |
| TCELL8:IMUX.IMUX4 | PS.SAXIHP1WDATA0 |
| TCELL8:IMUX.IMUX5 | PS.SAXIHP1WDATA1 |
| TCELL8:IMUX.IMUX6 | PS.SAXIHP1WDATA2 |
| TCELL8:IMUX.IMUX7 | PS.SAXIHP1WDATA3 |
| TCELL8:IMUX.IMUX8 | PS.SAXIHP1WDATA32 |
| TCELL8:IMUX.IMUX9 | PS.SAXIHP1WDATA33 |
| TCELL8:IMUX.IMUX10 | PS.SAXIHP1WDATA34 |
| TCELL8:IMUX.IMUX11 | PS.SAXIHP1WDATA35 |
| TCELL8:IMUX.IMUX12 | PS.SAXIHP1ARID0 |
| TCELL8:IMUX.IMUX13 | PS.SAXIHP1ARID1 |
| TCELL8:IMUX.IMUX14 | PS.SAXIHP1ARID2 |
| TCELL8:IMUX.IMUX15 | PS.SAXIHP1ARID3 |
| TCELL8:IMUX.IMUX16 | PS.SAXIHP1ARADDR0 |
| TCELL8:IMUX.IMUX17 | PS.SAXIHP1ARADDR1 |
| TCELL8:IMUX.IMUX18 | PS.SAXIHP1ARADDR2 |
| TCELL8:IMUX.IMUX19 | PS.SAXIHP1ARADDR3 |
| TCELL8:IMUX.IMUX20 | PS.SAXIHP1ARSIZE0 |
| TCELL8:IMUX.IMUX21 | PS.SAXIHP1ARSIZE1 |
| TCELL8:IMUX.IMUX22 | PS.SAXIHP1ARBURST0 |
| TCELL8:IMUX.IMUX23 | PS.SAXIHP1ARBURST1 |
| TCELL8:IMUX.IMUX24 | PS.SAXIHP1ARLOCK0 |
| TCELL8:IMUX.IMUX25 | PS.SAXIHP1RDISSUECAP1EN |
| TCELL8:OUT0.TMIN | PS.SAXIHP1RID0 |
| TCELL8:OUT1.TMIN | PS.SAXIHP1RID1 |
| TCELL8:OUT2.TMIN | PS.SAXIHP1RID2 |
| TCELL8:OUT3.TMIN | PS.SAXIHP1RDATA0 |
| TCELL8:OUT4.TMIN | PS.SAXIHP1RDATA1 |
| TCELL8:OUT5.TMIN | PS.SAXIHP1RDATA2 |
| TCELL8:OUT6.TMIN | PS.SAXIHP1RDATA3 |
| TCELL8:OUT7.TMIN | PS.SAXIHP1RDATA32 |
| TCELL8:OUT8.TMIN | PS.SAXIHP1RDATA33 |
| TCELL8:OUT9.TMIN | PS.SAXIHP1RDATA34 |
| TCELL8:OUT10.TMIN | PS.SAXIHP1RDATA35 |
| TCELL8:OUT11.TMIN | PS.SAXIHP1RACOUNT0 |
| TCELL8:OUT12.TMIN | PS.SAXIHP1RACOUNT1 |
| TCELL8:OUT13.TMIN | PS.SAXIHP1RACOUNT2 |
| TCELL8:OUT20.TMIN | PS.DEBUGDATA35 |
| TCELL8:OUT21.TMIN | PS.DEBUGDATA34 |
| TCELL8:OUT22.TMIN | PS.DEBUGDATA33 |
| TCELL8:OUT23.TMIN | PS.DEBUGDATA32 |
| TCELL9:IMUX.IMUX0 | PS.SAXIHP1AWADDR4 |
| TCELL9:IMUX.IMUX1 | PS.SAXIHP1AWADDR5 |
| TCELL9:IMUX.IMUX2 | PS.SAXIHP1AWADDR6 |
| TCELL9:IMUX.IMUX3 | PS.SAXIHP1AWADDR7 |
| TCELL9:IMUX.IMUX4 | PS.SAXIHP1WDATA4 |
| TCELL9:IMUX.IMUX5 | PS.SAXIHP1WDATA5 |
| TCELL9:IMUX.IMUX6 | PS.SAXIHP1WDATA6 |
| TCELL9:IMUX.IMUX7 | PS.SAXIHP1WDATA7 |
| TCELL9:IMUX.IMUX8 | PS.SAXIHP1WDATA36 |
| TCELL9:IMUX.IMUX9 | PS.SAXIHP1WDATA37 |
| TCELL9:IMUX.IMUX10 | PS.SAXIHP1WDATA38 |
| TCELL9:IMUX.IMUX11 | PS.SAXIHP1WDATA39 |
| TCELL9:IMUX.IMUX12 | PS.SAXIHP1ARID4 |
| TCELL9:IMUX.IMUX13 | PS.SAXIHP1ARID5 |
| TCELL9:IMUX.IMUX14 | PS.SAXIHP1ARADDR4 |
| TCELL9:IMUX.IMUX15 | PS.SAXIHP1ARADDR5 |
| TCELL9:IMUX.IMUX16 | PS.SAXIHP1ARADDR6 |
| TCELL9:IMUX.IMUX17 | PS.SAXIHP1ARADDR7 |
| TCELL9:IMUX.IMUX18 | PS.SAXIHP1ARLOCK1 |
| TCELL9:IMUX.IMUX19 | PS.SAXIHP1ARCACHE0 |
| TCELL9:IMUX.IMUX20 | PS.SAXIHP1ARCACHE1 |
| TCELL9:IMUX.IMUX21 | PS.SAXIHP1ARCACHE2 |
| TCELL9:IMUX.IMUX22 | PS.SAXIHP1ARCACHE3 |
| TCELL9:IMUX.IMUX23 | PS.SAXIHP1ARPROT0 |
| TCELL9:IMUX.IMUX24 | PS.SAXIHP1ARPROT1 |
| TCELL9:OUT0.TMIN | PS.SAXIHP1RID3 |
| TCELL9:OUT1.TMIN | PS.SAXIHP1RID4 |
| TCELL9:OUT2.TMIN | PS.SAXIHP1RID5 |
| TCELL9:OUT3.TMIN | PS.SAXIHP1RDATA4 |
| TCELL9:OUT4.TMIN | PS.SAXIHP1RDATA5 |
| TCELL9:OUT5.TMIN | PS.SAXIHP1RDATA6 |
| TCELL9:OUT6.TMIN | PS.SAXIHP1RDATA7 |
| TCELL9:OUT7.TMIN | PS.SAXIHP1RDATA36 |
| TCELL9:OUT8.TMIN | PS.SAXIHP1RDATA37 |
| TCELL9:OUT9.TMIN | PS.SAXIHP1RDATA38 |
| TCELL9:OUT10.TMIN | PS.SAXIHP1RDATA39 |
| TCELL9:OUT11.TMIN | PS.SAXIHP1RCOUNT0 |
| TCELL9:OUT12.TMIN | PS.SAXIHP1RCOUNT1 |
| TCELL9:OUT13.TMIN | PS.SAXIHP1RCOUNT2 |
| TCELL9:OUT14.TMIN | PS.SAXIHP1RCOUNT3 |
| TCELL9:OUT20.TMIN | PS.DEBUGDATA39 |
| TCELL9:OUT21.TMIN | PS.DEBUGDATA38 |
| TCELL9:OUT22.TMIN | PS.DEBUGDATA37 |
| TCELL9:OUT23.TMIN | PS.DEBUGDATA36 |
| TCELL10:IMUX.IMUX0 | PS.SAXIHP1AWADDR8 |
| TCELL10:IMUX.IMUX1 | PS.SAXIHP1AWADDR9 |
| TCELL10:IMUX.IMUX2 | PS.SAXIHP1AWADDR10 |
| TCELL10:IMUX.IMUX3 | PS.SAXIHP1AWADDR11 |
| TCELL10:IMUX.IMUX4 | PS.SAXIHP1WDATA8 |
| TCELL10:IMUX.IMUX5 | PS.SAXIHP1WDATA9 |
| TCELL10:IMUX.IMUX6 | PS.SAXIHP1WDATA10 |
| TCELL10:IMUX.IMUX7 | PS.SAXIHP1WDATA11 |
| TCELL10:IMUX.IMUX8 | PS.SAXIHP1WDATA40 |
| TCELL10:IMUX.IMUX9 | PS.SAXIHP1WDATA41 |
| TCELL10:IMUX.IMUX10 | PS.SAXIHP1WDATA42 |
| TCELL10:IMUX.IMUX11 | PS.SAXIHP1WDATA43 |
| TCELL10:IMUX.IMUX12 | PS.SAXIHP1WSTRB0 |
| TCELL10:IMUX.IMUX13 | PS.SAXIHP1WSTRB1 |
| TCELL10:IMUX.IMUX14 | PS.SAXIHP1WSTRB2 |
| TCELL10:IMUX.IMUX15 | PS.SAXIHP1WSTRB3 |
| TCELL10:IMUX.IMUX16 | PS.SAXIHP1WLAST |
| TCELL10:IMUX.IMUX17 | PS.SAXIHP1ARADDR8 |
| TCELL10:IMUX.IMUX18 | PS.SAXIHP1ARADDR9 |
| TCELL10:IMUX.IMUX19 | PS.SAXIHP1ARADDR10 |
| TCELL10:IMUX.IMUX20 | PS.SAXIHP1ARADDR11 |
| TCELL10:IMUX.IMUX21 | PS.SAXIHP1ARLEN0 |
| TCELL10:IMUX.IMUX22 | PS.SAXIHP1ARLEN1 |
| TCELL10:IMUX.IMUX23 | PS.SAXIHP1ARLEN2 |
| TCELL10:IMUX.IMUX24 | PS.SAXIHP1ARLEN3 |
| TCELL10:IMUX.IMUX25 | PS.SAXIHP1ARPROT2 |
| TCELL10:OUT0.TMIN | PS.SAXIHP1BRESP0 |
| TCELL10:OUT1.TMIN | PS.SAXIHP1BRESP1 |
| TCELL10:OUT2.TMIN | PS.SAXIHP1RDATA8 |
| TCELL10:OUT3.TMIN | PS.SAXIHP1RDATA9 |
| TCELL10:OUT4.TMIN | PS.SAXIHP1RDATA10 |
| TCELL10:OUT5.TMIN | PS.SAXIHP1RDATA11 |
| TCELL10:OUT6.TMIN | PS.SAXIHP1RDATA40 |
| TCELL10:OUT7.TMIN | PS.SAXIHP1RDATA41 |
| TCELL10:OUT8.TMIN | PS.SAXIHP1RDATA42 |
| TCELL10:OUT9.TMIN | PS.SAXIHP1RDATA43 |
| TCELL10:OUT10.TMIN | PS.SAXIHP1RCOUNT4 |
| TCELL10:OUT11.TMIN | PS.SAXIHP1RCOUNT5 |
| TCELL10:OUT12.TMIN | PS.SAXIHP1RCOUNT6 |
| TCELL10:OUT13.TMIN | PS.SAXIHP1RCOUNT7 |
| TCELL10:OUT20.TMIN | PS.DEBUGDATA43 |
| TCELL10:OUT21.TMIN | PS.DEBUGDATA42 |
| TCELL10:OUT22.TMIN | PS.DEBUGDATA41 |
| TCELL10:OUT23.TMIN | PS.DEBUGDATA40 |
| TCELL11:IMUX.IMUX0 | PS.SAXIHP1AWADDR12 |
| TCELL11:IMUX.IMUX1 | PS.SAXIHP1AWADDR13 |
| TCELL11:IMUX.IMUX2 | PS.SAXIHP1AWADDR14 |
| TCELL11:IMUX.IMUX3 | PS.SAXIHP1AWADDR15 |
| TCELL11:IMUX.IMUX4 | PS.SAXIHP1WDATA12 |
| TCELL11:IMUX.IMUX5 | PS.SAXIHP1WDATA13 |
| TCELL11:IMUX.IMUX6 | PS.SAXIHP1WDATA14 |
| TCELL11:IMUX.IMUX7 | PS.SAXIHP1WDATA15 |
| TCELL11:IMUX.IMUX8 | PS.SAXIHP1WDATA44 |
| TCELL11:IMUX.IMUX9 | PS.SAXIHP1WDATA45 |
| TCELL11:IMUX.IMUX10 | PS.SAXIHP1WDATA46 |
| TCELL11:IMUX.IMUX11 | PS.SAXIHP1WDATA47 |
| TCELL11:IMUX.IMUX12 | PS.SAXIHP1WSTRB4 |
| TCELL11:IMUX.IMUX13 | PS.SAXIHP1WSTRB5 |
| TCELL11:IMUX.IMUX14 | PS.SAXIHP1WSTRB6 |
| TCELL11:IMUX.IMUX15 | PS.SAXIHP1WSTRB7 |
| TCELL11:IMUX.IMUX16 | PS.SAXIHP1ARADDR12 |
| TCELL11:IMUX.IMUX17 | PS.SAXIHP1ARADDR13 |
| TCELL11:IMUX.IMUX18 | PS.SAXIHP1ARADDR14 |
| TCELL11:IMUX.IMUX19 | PS.SAXIHP1ARADDR15 |
| TCELL11:IMUX.IMUX20 | PS.SAXIHP1ARVALID |
| TCELL11:IMUX.IMUX21 | PS.SAXIHP1RREADY |
| TCELL11:IMUX.IMUX22 | PS.SAXIHP1ARQOS0 |
| TCELL11:IMUX.IMUX23 | PS.SAXIHP1ARQOS1 |
| TCELL11:IMUX.IMUX24 | PS.SAXIHP1ARQOS2 |
| TCELL11:IMUX.IMUX25 | PS.SAXIHP1ARQOS3 |
| TCELL11:OUT0.TMIN | PS.SAXIHP1ARREADY |
| TCELL11:OUT1.TMIN | PS.SAXIHP1RDATA12 |
| TCELL11:OUT2.TMIN | PS.SAXIHP1RDATA13 |
| TCELL11:OUT3.TMIN | PS.SAXIHP1RDATA14 |
| TCELL11:OUT4.TMIN | PS.SAXIHP1RDATA15 |
| TCELL11:OUT5.TMIN | PS.SAXIHP1RDATA44 |
| TCELL11:OUT6.TMIN | PS.SAXIHP1RDATA45 |
| TCELL11:OUT7.TMIN | PS.SAXIHP1RDATA46 |
| TCELL11:OUT8.TMIN | PS.SAXIHP1RDATA47 |
| TCELL11:OUT9.TMIN | PS.SAXIHP1RRESP0 |
| TCELL11:OUT10.TMIN | PS.SAXIHP1RRESP1 |
| TCELL11:OUT11.TMIN | PS.SAXIHP1RLAST |
| TCELL11:OUT12.TMIN | PS.SAXIHP1RVALID |
| TCELL11:OUT20.TMIN | PS.DEBUGDATA47 |
| TCELL11:OUT21.TMIN | PS.DEBUGDATA46 |
| TCELL11:OUT22.TMIN | PS.DEBUGDATA45 |
| TCELL11:OUT23.TMIN | PS.DEBUGDATA44 |
| TCELL12:IMUX.CLK0 | PS.SAXIHP1ACLK |
| TCELL12:IMUX.IMUX0 | PS.SAXIHP1AWADDR16 |
| TCELL12:IMUX.IMUX1 | PS.SAXIHP1AWADDR17 |
| TCELL12:IMUX.IMUX2 | PS.SAXIHP1AWADDR18 |
| TCELL12:IMUX.IMUX3 | PS.SAXIHP1AWADDR19 |
| TCELL12:IMUX.IMUX4 | PS.SAXIHP1AWCACHE0 |
| TCELL12:IMUX.IMUX5 | PS.SAXIHP1AWCACHE1 |
| TCELL12:IMUX.IMUX6 | PS.SAXIHP1AWPROT0 |
| TCELL12:IMUX.IMUX7 | PS.SAXIHP1AWPROT1 |
| TCELL12:IMUX.IMUX8 | PS.SAXIHP1AWPROT2 |
| TCELL12:IMUX.IMUX9 | PS.SAXIHP1AWVALID |
| TCELL12:IMUX.IMUX10 | PS.SAXIHP1WID0 |
| TCELL12:IMUX.IMUX11 | PS.SAXIHP1WID1 |
| TCELL12:IMUX.IMUX12 | PS.SAXIHP1WDATA16 |
| TCELL12:IMUX.IMUX13 | PS.SAXIHP1WDATA17 |
| TCELL12:IMUX.IMUX14 | PS.SAXIHP1WDATA18 |
| TCELL12:IMUX.IMUX15 | PS.SAXIHP1WDATA19 |
| TCELL12:IMUX.IMUX16 | PS.SAXIHP1WDATA48 |
| TCELL12:IMUX.IMUX17 | PS.SAXIHP1WDATA49 |
| TCELL12:IMUX.IMUX18 | PS.SAXIHP1WDATA50 |
| TCELL12:IMUX.IMUX19 | PS.SAXIHP1WDATA51 |
| TCELL12:IMUX.IMUX20 | PS.SAXIHP1WVALID |
| TCELL12:IMUX.IMUX21 | PS.SAXIHP1BREADY |
| TCELL12:IMUX.IMUX22 | PS.SAXIHP1ARADDR16 |
| TCELL12:IMUX.IMUX23 | PS.SAXIHP1ARADDR17 |
| TCELL12:IMUX.IMUX24 | PS.SAXIHP1ARADDR18 |
| TCELL12:IMUX.IMUX25 | PS.SAXIHP1ARADDR19 |
| TCELL12:OUT0.TMIN | PS.SAXIHP1AWREADY |
| TCELL12:OUT1.TMIN | PS.SAXIHP1WREADY |
| TCELL12:OUT2.TMIN | PS.SAXIHP1BID0 |
| TCELL12:OUT3.TMIN | PS.SAXIHP1BID1 |
| TCELL12:OUT4.TMIN | PS.SAXIHP1BVALID |
| TCELL12:OUT5.TMIN | PS.SAXIHP1RDATA16 |
| TCELL12:OUT6.TMIN | PS.SAXIHP1RDATA17 |
| TCELL12:OUT7.TMIN | PS.SAXIHP1RDATA18 |
| TCELL12:OUT8.TMIN | PS.SAXIHP1RDATA19 |
| TCELL12:OUT9.TMIN | PS.SAXIHP1RDATA48 |
| TCELL12:OUT10.TMIN | PS.SAXIHP1RDATA49 |
| TCELL12:OUT11.TMIN | PS.SAXIHP1RDATA50 |
| TCELL12:OUT12.TMIN | PS.SAXIHP1RDATA51 |
| TCELL12:OUT20.TMIN | PS.DEBUGDATA51 |
| TCELL12:OUT21.TMIN | PS.DEBUGDATA50 |
| TCELL12:OUT22.TMIN | PS.DEBUGDATA49 |
| TCELL12:OUT23.TMIN | PS.DEBUGDATA48 |
| TCELL13:IMUX.IMUX0 | PS.SAXIHP1AWADDR20 |
| TCELL13:IMUX.IMUX1 | PS.SAXIHP1AWADDR21 |
| TCELL13:IMUX.IMUX2 | PS.SAXIHP1AWADDR22 |
| TCELL13:IMUX.IMUX3 | PS.SAXIHP1AWADDR23 |
| TCELL13:IMUX.IMUX4 | PS.SAXIHP1AWBURST0 |
| TCELL13:IMUX.IMUX5 | PS.SAXIHP1AWLOCK0 |
| TCELL13:IMUX.IMUX6 | PS.SAXIHP1AWLOCK1 |
| TCELL13:IMUX.IMUX7 | PS.SAXIHP1AWCACHE2 |
| TCELL13:IMUX.IMUX8 | PS.SAXIHP1AWCACHE3 |
| TCELL13:IMUX.IMUX9 | PS.SAXIHP1WID2 |
| TCELL13:IMUX.IMUX10 | PS.SAXIHP1WID3 |
| TCELL13:IMUX.IMUX11 | PS.SAXIHP1WID4 |
| TCELL13:IMUX.IMUX12 | PS.SAXIHP1WID5 |
| TCELL13:IMUX.IMUX13 | PS.SAXIHP1WDATA20 |
| TCELL13:IMUX.IMUX14 | PS.SAXIHP1WDATA21 |
| TCELL13:IMUX.IMUX15 | PS.SAXIHP1WDATA22 |
| TCELL13:IMUX.IMUX16 | PS.SAXIHP1WDATA23 |
| TCELL13:IMUX.IMUX17 | PS.SAXIHP1WDATA52 |
| TCELL13:IMUX.IMUX18 | PS.SAXIHP1WDATA53 |
| TCELL13:IMUX.IMUX19 | PS.SAXIHP1WDATA54 |
| TCELL13:IMUX.IMUX20 | PS.SAXIHP1WDATA55 |
| TCELL13:IMUX.IMUX21 | PS.SAXIHP1ARADDR20 |
| TCELL13:IMUX.IMUX22 | PS.SAXIHP1ARADDR21 |
| TCELL13:IMUX.IMUX23 | PS.SAXIHP1ARADDR22 |
| TCELL13:IMUX.IMUX24 | PS.SAXIHP1ARADDR23 |
| TCELL13:OUT0.TMIN | PS.SAXIHP1BID2 |
| TCELL13:OUT1.TMIN | PS.SAXIHP1BID3 |
| TCELL13:OUT2.TMIN | PS.SAXIHP1BID4 |
| TCELL13:OUT3.TMIN | PS.SAXIHP1BID5 |
| TCELL13:OUT4.TMIN | PS.SAXIHP1RDATA20 |
| TCELL13:OUT5.TMIN | PS.SAXIHP1RDATA21 |
| TCELL13:OUT6.TMIN | PS.SAXIHP1RDATA22 |
| TCELL13:OUT7.TMIN | PS.SAXIHP1RDATA23 |
| TCELL13:OUT8.TMIN | PS.SAXIHP1RDATA52 |
| TCELL13:OUT9.TMIN | PS.SAXIHP1RDATA53 |
| TCELL13:OUT10.TMIN | PS.SAXIHP1RDATA54 |
| TCELL13:OUT11.TMIN | PS.SAXIHP1RDATA55 |
| TCELL13:OUT12.TMIN | PS.SAXIHP1WACOUNT0 |
| TCELL13:OUT13.TMIN | PS.SAXIHP1WACOUNT1 |
| TCELL13:OUT20.TMIN | PS.DEBUGDATA55 |
| TCELL13:OUT21.TMIN | PS.DEBUGDATA54 |
| TCELL13:OUT22.TMIN | PS.DEBUGDATA53 |
| TCELL13:OUT23.TMIN | PS.DEBUGDATA52 |
| TCELL14:IMUX.IMUX0 | PS.SAXIHP1AWID0 |
| TCELL14:IMUX.IMUX1 | PS.SAXIHP1AWID1 |
| TCELL14:IMUX.IMUX2 | PS.SAXIHP1AWID2 |
| TCELL14:IMUX.IMUX3 | PS.SAXIHP1AWID3 |
| TCELL14:IMUX.IMUX4 | PS.SAXIHP1AWADDR24 |
| TCELL14:IMUX.IMUX5 | PS.SAXIHP1AWADDR25 |
| TCELL14:IMUX.IMUX6 | PS.SAXIHP1AWADDR26 |
| TCELL14:IMUX.IMUX7 | PS.SAXIHP1AWADDR27 |
| TCELL14:IMUX.IMUX8 | PS.SAXIHP1AWSIZE0 |
| TCELL14:IMUX.IMUX9 | PS.SAXIHP1AWSIZE1 |
| TCELL14:IMUX.IMUX10 | PS.SAXIHP1AWBURST1 |
| TCELL14:IMUX.IMUX11 | PS.SAXIHP1WDATA24 |
| TCELL14:IMUX.IMUX12 | PS.SAXIHP1WDATA25 |
| TCELL14:IMUX.IMUX13 | PS.SAXIHP1WDATA26 |
| TCELL14:IMUX.IMUX14 | PS.SAXIHP1WDATA27 |
| TCELL14:IMUX.IMUX15 | PS.SAXIHP1WDATA56 |
| TCELL14:IMUX.IMUX16 | PS.SAXIHP1WDATA57 |
| TCELL14:IMUX.IMUX17 | PS.SAXIHP1WDATA58 |
| TCELL14:IMUX.IMUX18 | PS.SAXIHP1WDATA59 |
| TCELL14:IMUX.IMUX19 | PS.SAXIHP1ARADDR24 |
| TCELL14:IMUX.IMUX20 | PS.SAXIHP1ARADDR25 |
| TCELL14:IMUX.IMUX21 | PS.SAXIHP1ARADDR26 |
| TCELL14:IMUX.IMUX22 | PS.SAXIHP1ARADDR27 |
| TCELL14:IMUX.IMUX23 | PS.SAXIHP1AWQOS0 |
| TCELL14:IMUX.IMUX24 | PS.SAXIHP1AWQOS1 |
| TCELL14:OUT0.TMIN | PS.SAXIHP1RDATA24 |
| TCELL14:OUT1.TMIN | PS.SAXIHP1RDATA25 |
| TCELL14:OUT2.TMIN | PS.SAXIHP1RDATA26 |
| TCELL14:OUT3.TMIN | PS.SAXIHP1RDATA27 |
| TCELL14:OUT4.TMIN | PS.SAXIHP1RDATA56 |
| TCELL14:OUT5.TMIN | PS.SAXIHP1RDATA57 |
| TCELL14:OUT6.TMIN | PS.SAXIHP1RDATA58 |
| TCELL14:OUT7.TMIN | PS.SAXIHP1RDATA59 |
| TCELL14:OUT8.TMIN | PS.SAXIHP1WCOUNT0 |
| TCELL14:OUT9.TMIN | PS.SAXIHP1WCOUNT1 |
| TCELL14:OUT10.TMIN | PS.SAXIHP1WCOUNT2 |
| TCELL14:OUT11.TMIN | PS.SAXIHP1WCOUNT3 |
| TCELL14:OUT12.TMIN | PS.SAXIHP1WACOUNT2 |
| TCELL14:OUT13.TMIN | PS.SAXIHP1WACOUNT3 |
| TCELL14:OUT20.TMIN | PS.DEBUGDATA59 |
| TCELL14:OUT21.TMIN | PS.DEBUGDATA58 |
| TCELL14:OUT22.TMIN | PS.DEBUGDATA57 |
| TCELL14:OUT23.TMIN | PS.DEBUGDATA56 |
| TCELL15:IMUX.IMUX0 | PS.SAXIHP1AWID4 |
| TCELL15:IMUX.IMUX1 | PS.SAXIHP1AWID5 |
| TCELL15:IMUX.IMUX2 | PS.SAXIHP1AWADDR28 |
| TCELL15:IMUX.IMUX3 | PS.SAXIHP1AWADDR29 |
| TCELL15:IMUX.IMUX4 | PS.SAXIHP1AWADDR30 |
| TCELL15:IMUX.IMUX5 | PS.SAXIHP1AWADDR31 |
| TCELL15:IMUX.IMUX6 | PS.SAXIHP1AWLEN0 |
| TCELL15:IMUX.IMUX7 | PS.SAXIHP1AWLEN1 |
| TCELL15:IMUX.IMUX8 | PS.SAXIHP1AWLEN2 |
| TCELL15:IMUX.IMUX9 | PS.SAXIHP1AWLEN3 |
| TCELL15:IMUX.IMUX10 | PS.SAXIHP1WDATA28 |
| TCELL15:IMUX.IMUX11 | PS.SAXIHP1WDATA29 |
| TCELL15:IMUX.IMUX12 | PS.SAXIHP1WDATA30 |
| TCELL15:IMUX.IMUX13 | PS.SAXIHP1WDATA31 |
| TCELL15:IMUX.IMUX14 | PS.SAXIHP1WDATA60 |
| TCELL15:IMUX.IMUX15 | PS.SAXIHP1WDATA61 |
| TCELL15:IMUX.IMUX16 | PS.SAXIHP1WDATA62 |
| TCELL15:IMUX.IMUX17 | PS.SAXIHP1WDATA63 |
| TCELL15:IMUX.IMUX18 | PS.SAXIHP1ARADDR28 |
| TCELL15:IMUX.IMUX19 | PS.SAXIHP1ARADDR29 |
| TCELL15:IMUX.IMUX20 | PS.SAXIHP1ARADDR30 |
| TCELL15:IMUX.IMUX21 | PS.SAXIHP1ARADDR31 |
| TCELL15:IMUX.IMUX22 | PS.SAXIHP1WRISSUECAP1EN |
| TCELL15:IMUX.IMUX23 | PS.SAXIHP1AWQOS2 |
| TCELL15:IMUX.IMUX24 | PS.SAXIHP1AWQOS3 |
| TCELL15:OUT0.TMIN | PS.SAXIHP1ARESETN |
| TCELL15:OUT1.TMIN | PS.SAXIHP1RDATA28 |
| TCELL15:OUT2.TMIN | PS.SAXIHP1RDATA29 |
| TCELL15:OUT3.TMIN | PS.SAXIHP1RDATA30 |
| TCELL15:OUT4.TMIN | PS.SAXIHP1RDATA31 |
| TCELL15:OUT5.TMIN | PS.SAXIHP1RDATA60 |
| TCELL15:OUT6.TMIN | PS.SAXIHP1RDATA61 |
| TCELL15:OUT7.TMIN | PS.SAXIHP1RDATA62 |
| TCELL15:OUT8.TMIN | PS.SAXIHP1RDATA63 |
| TCELL15:OUT9.TMIN | PS.SAXIHP1WCOUNT4 |
| TCELL15:OUT10.TMIN | PS.SAXIHP1WCOUNT5 |
| TCELL15:OUT11.TMIN | PS.SAXIHP1WCOUNT6 |
| TCELL15:OUT12.TMIN | PS.SAXIHP1WCOUNT7 |
| TCELL15:OUT13.TMIN | PS.SAXIHP1WACOUNT4 |
| TCELL15:OUT14.TMIN | PS.SAXIHP1WACOUNT5 |
| TCELL15:OUT20.TMIN | PS.DEBUGDATA63 |
| TCELL15:OUT21.TMIN | PS.DEBUGDATA62 |
| TCELL15:OUT22.TMIN | PS.DEBUGDATA61 |
| TCELL15:OUT23.TMIN | PS.DEBUGDATA60 |
| TCELL16:IMUX.IMUX0 | PS.SAXIHP2AWADDR0 |
| TCELL16:IMUX.IMUX1 | PS.SAXIHP2AWADDR1 |
| TCELL16:IMUX.IMUX2 | PS.SAXIHP2AWADDR2 |
| TCELL16:IMUX.IMUX3 | PS.SAXIHP2AWADDR3 |
| TCELL16:IMUX.IMUX4 | PS.SAXIHP2WDATA0 |
| TCELL16:IMUX.IMUX5 | PS.SAXIHP2WDATA1 |
| TCELL16:IMUX.IMUX6 | PS.SAXIHP2WDATA2 |
| TCELL16:IMUX.IMUX7 | PS.SAXIHP2WDATA3 |
| TCELL16:IMUX.IMUX8 | PS.SAXIHP2WDATA32 |
| TCELL16:IMUX.IMUX9 | PS.SAXIHP2WDATA33 |
| TCELL16:IMUX.IMUX10 | PS.SAXIHP2WDATA34 |
| TCELL16:IMUX.IMUX11 | PS.SAXIHP2WDATA35 |
| TCELL16:IMUX.IMUX12 | PS.SAXIHP2ARID0 |
| TCELL16:IMUX.IMUX13 | PS.SAXIHP2ARID1 |
| TCELL16:IMUX.IMUX14 | PS.SAXIHP2ARID2 |
| TCELL16:IMUX.IMUX15 | PS.SAXIHP2ARID3 |
| TCELL16:IMUX.IMUX16 | PS.SAXIHP2ARADDR0 |
| TCELL16:IMUX.IMUX17 | PS.SAXIHP2ARADDR1 |
| TCELL16:IMUX.IMUX18 | PS.SAXIHP2ARADDR2 |
| TCELL16:IMUX.IMUX19 | PS.SAXIHP2ARADDR3 |
| TCELL16:IMUX.IMUX20 | PS.SAXIHP2ARSIZE0 |
| TCELL16:IMUX.IMUX21 | PS.SAXIHP2ARSIZE1 |
| TCELL16:IMUX.IMUX22 | PS.SAXIHP2ARBURST0 |
| TCELL16:IMUX.IMUX23 | PS.SAXIHP2ARBURST1 |
| TCELL16:IMUX.IMUX24 | PS.SAXIHP2ARLOCK0 |
| TCELL16:IMUX.IMUX25 | PS.SAXIHP2RDISSUECAP1EN |
| TCELL16:OUT0.TMIN | PS.SAXIHP2RID0 |
| TCELL16:OUT1.TMIN | PS.SAXIHP2RID1 |
| TCELL16:OUT2.TMIN | PS.SAXIHP2RID2 |
| TCELL16:OUT3.TMIN | PS.SAXIHP2RDATA0 |
| TCELL16:OUT4.TMIN | PS.SAXIHP2RDATA1 |
| TCELL16:OUT5.TMIN | PS.SAXIHP2RDATA2 |
| TCELL16:OUT6.TMIN | PS.SAXIHP2RDATA3 |
| TCELL16:OUT7.TMIN | PS.SAXIHP2RDATA32 |
| TCELL16:OUT8.TMIN | PS.SAXIHP2RDATA33 |
| TCELL16:OUT9.TMIN | PS.SAXIHP2RDATA34 |
| TCELL16:OUT10.TMIN | PS.SAXIHP2RDATA35 |
| TCELL16:OUT11.TMIN | PS.SAXIHP2RACOUNT0 |
| TCELL16:OUT12.TMIN | PS.SAXIHP2RACOUNT1 |
| TCELL16:OUT13.TMIN | PS.SAXIHP2RACOUNT2 |
| TCELL16:OUT20.TMIN | PS.DEBUGDATA67 |
| TCELL16:OUT21.TMIN | PS.DEBUGDATA66 |
| TCELL16:OUT22.TMIN | PS.DEBUGDATA65 |
| TCELL16:OUT23.TMIN | PS.DEBUGDATA64 |
| TCELL17:IMUX.IMUX0 | PS.SAXIHP2AWADDR4 |
| TCELL17:IMUX.IMUX1 | PS.SAXIHP2AWADDR5 |
| TCELL17:IMUX.IMUX2 | PS.SAXIHP2AWADDR6 |
| TCELL17:IMUX.IMUX3 | PS.SAXIHP2AWADDR7 |
| TCELL17:IMUX.IMUX4 | PS.SAXIHP2WDATA4 |
| TCELL17:IMUX.IMUX5 | PS.SAXIHP2WDATA5 |
| TCELL17:IMUX.IMUX6 | PS.SAXIHP2WDATA6 |
| TCELL17:IMUX.IMUX7 | PS.SAXIHP2WDATA7 |
| TCELL17:IMUX.IMUX8 | PS.SAXIHP2WDATA36 |
| TCELL17:IMUX.IMUX9 | PS.SAXIHP2WDATA37 |
| TCELL17:IMUX.IMUX10 | PS.SAXIHP2WDATA38 |
| TCELL17:IMUX.IMUX11 | PS.SAXIHP2WDATA39 |
| TCELL17:IMUX.IMUX12 | PS.SAXIHP2ARID4 |
| TCELL17:IMUX.IMUX13 | PS.SAXIHP2ARID5 |
| TCELL17:IMUX.IMUX14 | PS.SAXIHP2ARADDR4 |
| TCELL17:IMUX.IMUX15 | PS.SAXIHP2ARADDR5 |
| TCELL17:IMUX.IMUX16 | PS.SAXIHP2ARADDR6 |
| TCELL17:IMUX.IMUX17 | PS.SAXIHP2ARADDR7 |
| TCELL17:IMUX.IMUX18 | PS.SAXIHP2ARLOCK1 |
| TCELL17:IMUX.IMUX19 | PS.SAXIHP2ARCACHE0 |
| TCELL17:IMUX.IMUX20 | PS.SAXIHP2ARCACHE1 |
| TCELL17:IMUX.IMUX21 | PS.SAXIHP2ARCACHE2 |
| TCELL17:IMUX.IMUX22 | PS.SAXIHP2ARCACHE3 |
| TCELL17:IMUX.IMUX23 | PS.SAXIHP2ARPROT0 |
| TCELL17:IMUX.IMUX24 | PS.SAXIHP2ARPROT1 |
| TCELL17:OUT0.TMIN | PS.SAXIHP2RID3 |
| TCELL17:OUT1.TMIN | PS.SAXIHP2RID4 |
| TCELL17:OUT2.TMIN | PS.SAXIHP2RID5 |
| TCELL17:OUT3.TMIN | PS.SAXIHP2RDATA4 |
| TCELL17:OUT4.TMIN | PS.SAXIHP2RDATA5 |
| TCELL17:OUT5.TMIN | PS.SAXIHP2RDATA6 |
| TCELL17:OUT6.TMIN | PS.SAXIHP2RDATA7 |
| TCELL17:OUT7.TMIN | PS.SAXIHP2RDATA36 |
| TCELL17:OUT8.TMIN | PS.SAXIHP2RDATA37 |
| TCELL17:OUT9.TMIN | PS.SAXIHP2RDATA38 |
| TCELL17:OUT10.TMIN | PS.SAXIHP2RDATA39 |
| TCELL17:OUT11.TMIN | PS.SAXIHP2RCOUNT0 |
| TCELL17:OUT12.TMIN | PS.SAXIHP2RCOUNT1 |
| TCELL17:OUT13.TMIN | PS.SAXIHP2RCOUNT2 |
| TCELL17:OUT14.TMIN | PS.SAXIHP2RCOUNT3 |
| TCELL17:OUT20.TMIN | PS.DEBUGDATA71 |
| TCELL17:OUT21.TMIN | PS.DEBUGDATA70 |
| TCELL17:OUT22.TMIN | PS.DEBUGDATA69 |
| TCELL17:OUT23.TMIN | PS.DEBUGDATA68 |
| TCELL18:IMUX.IMUX0 | PS.SAXIHP2AWADDR8 |
| TCELL18:IMUX.IMUX1 | PS.SAXIHP2AWADDR9 |
| TCELL18:IMUX.IMUX2 | PS.SAXIHP2AWADDR10 |
| TCELL18:IMUX.IMUX3 | PS.SAXIHP2AWADDR11 |
| TCELL18:IMUX.IMUX4 | PS.SAXIHP2WDATA8 |
| TCELL18:IMUX.IMUX5 | PS.SAXIHP2WDATA9 |
| TCELL18:IMUX.IMUX6 | PS.SAXIHP2WDATA10 |
| TCELL18:IMUX.IMUX7 | PS.SAXIHP2WDATA11 |
| TCELL18:IMUX.IMUX8 | PS.SAXIHP2WDATA40 |
| TCELL18:IMUX.IMUX9 | PS.SAXIHP2WDATA41 |
| TCELL18:IMUX.IMUX10 | PS.SAXIHP2WDATA42 |
| TCELL18:IMUX.IMUX11 | PS.SAXIHP2WDATA43 |
| TCELL18:IMUX.IMUX12 | PS.SAXIHP2WSTRB0 |
| TCELL18:IMUX.IMUX13 | PS.SAXIHP2WSTRB1 |
| TCELL18:IMUX.IMUX14 | PS.SAXIHP2WSTRB2 |
| TCELL18:IMUX.IMUX15 | PS.SAXIHP2WSTRB3 |
| TCELL18:IMUX.IMUX16 | PS.SAXIHP2WLAST |
| TCELL18:IMUX.IMUX17 | PS.SAXIHP2ARADDR8 |
| TCELL18:IMUX.IMUX18 | PS.SAXIHP2ARADDR9 |
| TCELL18:IMUX.IMUX19 | PS.SAXIHP2ARADDR10 |
| TCELL18:IMUX.IMUX20 | PS.SAXIHP2ARADDR11 |
| TCELL18:IMUX.IMUX21 | PS.SAXIHP2ARLEN0 |
| TCELL18:IMUX.IMUX22 | PS.SAXIHP2ARLEN1 |
| TCELL18:IMUX.IMUX23 | PS.SAXIHP2ARLEN2 |
| TCELL18:IMUX.IMUX24 | PS.SAXIHP2ARLEN3 |
| TCELL18:IMUX.IMUX25 | PS.SAXIHP2ARPROT2 |
| TCELL18:OUT0.TMIN | PS.SAXIHP2BRESP0 |
| TCELL18:OUT1.TMIN | PS.SAXIHP2BRESP1 |
| TCELL18:OUT2.TMIN | PS.SAXIHP2RDATA8 |
| TCELL18:OUT3.TMIN | PS.SAXIHP2RDATA9 |
| TCELL18:OUT4.TMIN | PS.SAXIHP2RDATA10 |
| TCELL18:OUT5.TMIN | PS.SAXIHP2RDATA11 |
| TCELL18:OUT6.TMIN | PS.SAXIHP2RDATA40 |
| TCELL18:OUT7.TMIN | PS.SAXIHP2RDATA41 |
| TCELL18:OUT8.TMIN | PS.SAXIHP2RDATA42 |
| TCELL18:OUT9.TMIN | PS.SAXIHP2RDATA43 |
| TCELL18:OUT10.TMIN | PS.SAXIHP2RCOUNT4 |
| TCELL18:OUT11.TMIN | PS.SAXIHP2RCOUNT5 |
| TCELL18:OUT12.TMIN | PS.SAXIHP2RCOUNT6 |
| TCELL18:OUT13.TMIN | PS.SAXIHP2RCOUNT7 |
| TCELL18:OUT20.TMIN | PS.DEBUGDATA75 |
| TCELL18:OUT21.TMIN | PS.DEBUGDATA74 |
| TCELL18:OUT22.TMIN | PS.DEBUGDATA73 |
| TCELL18:OUT23.TMIN | PS.DEBUGDATA72 |
| TCELL19:IMUX.IMUX0 | PS.SAXIHP2AWADDR12 |
| TCELL19:IMUX.IMUX1 | PS.SAXIHP2AWADDR13 |
| TCELL19:IMUX.IMUX2 | PS.SAXIHP2AWADDR14 |
| TCELL19:IMUX.IMUX3 | PS.SAXIHP2AWADDR15 |
| TCELL19:IMUX.IMUX4 | PS.SAXIHP2WDATA12 |
| TCELL19:IMUX.IMUX5 | PS.SAXIHP2WDATA13 |
| TCELL19:IMUX.IMUX6 | PS.SAXIHP2WDATA14 |
| TCELL19:IMUX.IMUX7 | PS.SAXIHP2WDATA15 |
| TCELL19:IMUX.IMUX8 | PS.SAXIHP2WDATA44 |
| TCELL19:IMUX.IMUX9 | PS.SAXIHP2WDATA45 |
| TCELL19:IMUX.IMUX10 | PS.SAXIHP2WDATA46 |
| TCELL19:IMUX.IMUX11 | PS.SAXIHP2WDATA47 |
| TCELL19:IMUX.IMUX12 | PS.SAXIHP2WSTRB4 |
| TCELL19:IMUX.IMUX13 | PS.SAXIHP2WSTRB5 |
| TCELL19:IMUX.IMUX14 | PS.SAXIHP2WSTRB6 |
| TCELL19:IMUX.IMUX15 | PS.SAXIHP2WSTRB7 |
| TCELL19:IMUX.IMUX16 | PS.SAXIHP2ARADDR12 |
| TCELL19:IMUX.IMUX17 | PS.SAXIHP2ARADDR13 |
| TCELL19:IMUX.IMUX18 | PS.SAXIHP2ARADDR14 |
| TCELL19:IMUX.IMUX19 | PS.SAXIHP2ARADDR15 |
| TCELL19:IMUX.IMUX20 | PS.SAXIHP2ARVALID |
| TCELL19:IMUX.IMUX21 | PS.SAXIHP2RREADY |
| TCELL19:IMUX.IMUX22 | PS.SAXIHP2ARQOS0 |
| TCELL19:IMUX.IMUX23 | PS.SAXIHP2ARQOS1 |
| TCELL19:IMUX.IMUX24 | PS.SAXIHP2ARQOS2 |
| TCELL19:IMUX.IMUX25 | PS.SAXIHP2ARQOS3 |
| TCELL19:OUT0.TMIN | PS.SAXIHP2ARREADY |
| TCELL19:OUT1.TMIN | PS.SAXIHP2RDATA12 |
| TCELL19:OUT2.TMIN | PS.SAXIHP2RDATA13 |
| TCELL19:OUT3.TMIN | PS.SAXIHP2RDATA14 |
| TCELL19:OUT4.TMIN | PS.SAXIHP2RDATA15 |
| TCELL19:OUT5.TMIN | PS.SAXIHP2RDATA44 |
| TCELL19:OUT6.TMIN | PS.SAXIHP2RDATA45 |
| TCELL19:OUT7.TMIN | PS.SAXIHP2RDATA46 |
| TCELL19:OUT8.TMIN | PS.SAXIHP2RDATA47 |
| TCELL19:OUT9.TMIN | PS.SAXIHP2RRESP0 |
| TCELL19:OUT10.TMIN | PS.SAXIHP2RRESP1 |
| TCELL19:OUT11.TMIN | PS.SAXIHP2RLAST |
| TCELL19:OUT12.TMIN | PS.SAXIHP2RVALID |
| TCELL19:OUT20.TMIN | PS.DEBUGDATA79 |
| TCELL19:OUT21.TMIN | PS.DEBUGDATA78 |
| TCELL19:OUT22.TMIN | PS.DEBUGDATA77 |
| TCELL19:OUT23.TMIN | PS.DEBUGDATA76 |
| TCELL20:IMUX.CLK0 | PS.SAXIHP2ACLK |
| TCELL20:IMUX.IMUX0 | PS.SAXIHP2AWADDR16 |
| TCELL20:IMUX.IMUX1 | PS.SAXIHP2AWADDR17 |
| TCELL20:IMUX.IMUX2 | PS.SAXIHP2AWADDR18 |
| TCELL20:IMUX.IMUX3 | PS.SAXIHP2AWADDR19 |
| TCELL20:IMUX.IMUX4 | PS.SAXIHP2AWCACHE0 |
| TCELL20:IMUX.IMUX5 | PS.SAXIHP2AWCACHE1 |
| TCELL20:IMUX.IMUX6 | PS.SAXIHP2AWPROT0 |
| TCELL20:IMUX.IMUX7 | PS.SAXIHP2AWPROT1 |
| TCELL20:IMUX.IMUX8 | PS.SAXIHP2AWPROT2 |
| TCELL20:IMUX.IMUX9 | PS.SAXIHP2AWVALID |
| TCELL20:IMUX.IMUX10 | PS.SAXIHP2WID0 |
| TCELL20:IMUX.IMUX11 | PS.SAXIHP2WID1 |
| TCELL20:IMUX.IMUX12 | PS.SAXIHP2WDATA16 |
| TCELL20:IMUX.IMUX13 | PS.SAXIHP2WDATA17 |
| TCELL20:IMUX.IMUX14 | PS.SAXIHP2WDATA18 |
| TCELL20:IMUX.IMUX15 | PS.SAXIHP2WDATA19 |
| TCELL20:IMUX.IMUX16 | PS.SAXIHP2WDATA48 |
| TCELL20:IMUX.IMUX17 | PS.SAXIHP2WDATA49 |
| TCELL20:IMUX.IMUX18 | PS.SAXIHP2WDATA50 |
| TCELL20:IMUX.IMUX19 | PS.SAXIHP2WDATA51 |
| TCELL20:IMUX.IMUX20 | PS.SAXIHP2WVALID |
| TCELL20:IMUX.IMUX21 | PS.SAXIHP2BREADY |
| TCELL20:IMUX.IMUX22 | PS.SAXIHP2ARADDR16 |
| TCELL20:IMUX.IMUX23 | PS.SAXIHP2ARADDR17 |
| TCELL20:IMUX.IMUX24 | PS.SAXIHP2ARADDR18 |
| TCELL20:IMUX.IMUX25 | PS.SAXIHP2ARADDR19 |
| TCELL20:OUT0.TMIN | PS.SAXIHP2AWREADY |
| TCELL20:OUT1.TMIN | PS.SAXIHP2WREADY |
| TCELL20:OUT2.TMIN | PS.SAXIHP2BID0 |
| TCELL20:OUT3.TMIN | PS.SAXIHP2BID1 |
| TCELL20:OUT4.TMIN | PS.SAXIHP2BVALID |
| TCELL20:OUT5.TMIN | PS.SAXIHP2RDATA16 |
| TCELL20:OUT6.TMIN | PS.SAXIHP2RDATA17 |
| TCELL20:OUT7.TMIN | PS.SAXIHP2RDATA18 |
| TCELL20:OUT8.TMIN | PS.SAXIHP2RDATA19 |
| TCELL20:OUT9.TMIN | PS.SAXIHP2RDATA48 |
| TCELL20:OUT10.TMIN | PS.SAXIHP2RDATA49 |
| TCELL20:OUT11.TMIN | PS.SAXIHP2RDATA50 |
| TCELL20:OUT12.TMIN | PS.SAXIHP2RDATA51 |
| TCELL20:OUT20.TMIN | PS.DEBUGDATA83 |
| TCELL20:OUT21.TMIN | PS.DEBUGDATA82 |
| TCELL20:OUT22.TMIN | PS.DEBUGDATA81 |
| TCELL20:OUT23.TMIN | PS.DEBUGDATA80 |
| TCELL21:IMUX.IMUX0 | PS.SAXIHP2AWADDR20 |
| TCELL21:IMUX.IMUX1 | PS.SAXIHP2AWADDR21 |
| TCELL21:IMUX.IMUX2 | PS.SAXIHP2AWADDR22 |
| TCELL21:IMUX.IMUX3 | PS.SAXIHP2AWADDR23 |
| TCELL21:IMUX.IMUX4 | PS.SAXIHP2AWBURST0 |
| TCELL21:IMUX.IMUX5 | PS.SAXIHP2AWLOCK0 |
| TCELL21:IMUX.IMUX6 | PS.SAXIHP2AWLOCK1 |
| TCELL21:IMUX.IMUX7 | PS.SAXIHP2AWCACHE2 |
| TCELL21:IMUX.IMUX8 | PS.SAXIHP2AWCACHE3 |
| TCELL21:IMUX.IMUX9 | PS.SAXIHP2WID2 |
| TCELL21:IMUX.IMUX10 | PS.SAXIHP2WID3 |
| TCELL21:IMUX.IMUX11 | PS.SAXIHP2WID4 |
| TCELL21:IMUX.IMUX12 | PS.SAXIHP2WID5 |
| TCELL21:IMUX.IMUX13 | PS.SAXIHP2WDATA20 |
| TCELL21:IMUX.IMUX14 | PS.SAXIHP2WDATA21 |
| TCELL21:IMUX.IMUX15 | PS.SAXIHP2WDATA22 |
| TCELL21:IMUX.IMUX16 | PS.SAXIHP2WDATA23 |
| TCELL21:IMUX.IMUX17 | PS.SAXIHP2WDATA52 |
| TCELL21:IMUX.IMUX18 | PS.SAXIHP2WDATA53 |
| TCELL21:IMUX.IMUX19 | PS.SAXIHP2WDATA54 |
| TCELL21:IMUX.IMUX20 | PS.SAXIHP2WDATA55 |
| TCELL21:IMUX.IMUX21 | PS.SAXIHP2ARADDR20 |
| TCELL21:IMUX.IMUX22 | PS.SAXIHP2ARADDR21 |
| TCELL21:IMUX.IMUX23 | PS.SAXIHP2ARADDR22 |
| TCELL21:IMUX.IMUX24 | PS.SAXIHP2ARADDR23 |
| TCELL21:OUT0.TMIN | PS.SAXIHP2BID2 |
| TCELL21:OUT1.TMIN | PS.SAXIHP2BID3 |
| TCELL21:OUT2.TMIN | PS.SAXIHP2BID4 |
| TCELL21:OUT3.TMIN | PS.SAXIHP2BID5 |
| TCELL21:OUT4.TMIN | PS.SAXIHP2RDATA20 |
| TCELL21:OUT5.TMIN | PS.SAXIHP2RDATA21 |
| TCELL21:OUT6.TMIN | PS.SAXIHP2RDATA22 |
| TCELL21:OUT7.TMIN | PS.SAXIHP2RDATA23 |
| TCELL21:OUT8.TMIN | PS.SAXIHP2RDATA52 |
| TCELL21:OUT9.TMIN | PS.SAXIHP2RDATA53 |
| TCELL21:OUT10.TMIN | PS.SAXIHP2RDATA54 |
| TCELL21:OUT11.TMIN | PS.SAXIHP2RDATA55 |
| TCELL21:OUT12.TMIN | PS.SAXIHP2WACOUNT0 |
| TCELL21:OUT13.TMIN | PS.SAXIHP2WACOUNT1 |
| TCELL21:OUT20.TMIN | PS.DEBUGDATA87 |
| TCELL21:OUT21.TMIN | PS.DEBUGDATA86 |
| TCELL21:OUT22.TMIN | PS.DEBUGDATA85 |
| TCELL21:OUT23.TMIN | PS.DEBUGDATA84 |
| TCELL22:IMUX.IMUX0 | PS.SAXIHP2AWID0 |
| TCELL22:IMUX.IMUX1 | PS.SAXIHP2AWID1 |
| TCELL22:IMUX.IMUX2 | PS.SAXIHP2AWID2 |
| TCELL22:IMUX.IMUX3 | PS.SAXIHP2AWID3 |
| TCELL22:IMUX.IMUX4 | PS.SAXIHP2AWADDR24 |
| TCELL22:IMUX.IMUX5 | PS.SAXIHP2AWADDR25 |
| TCELL22:IMUX.IMUX6 | PS.SAXIHP2AWADDR26 |
| TCELL22:IMUX.IMUX7 | PS.SAXIHP2AWADDR27 |
| TCELL22:IMUX.IMUX8 | PS.SAXIHP2AWSIZE0 |
| TCELL22:IMUX.IMUX9 | PS.SAXIHP2AWSIZE1 |
| TCELL22:IMUX.IMUX10 | PS.SAXIHP2AWBURST1 |
| TCELL22:IMUX.IMUX11 | PS.SAXIHP2WDATA24 |
| TCELL22:IMUX.IMUX12 | PS.SAXIHP2WDATA25 |
| TCELL22:IMUX.IMUX13 | PS.SAXIHP2WDATA26 |
| TCELL22:IMUX.IMUX14 | PS.SAXIHP2WDATA27 |
| TCELL22:IMUX.IMUX15 | PS.SAXIHP2WDATA56 |
| TCELL22:IMUX.IMUX16 | PS.SAXIHP2WDATA57 |
| TCELL22:IMUX.IMUX17 | PS.SAXIHP2WDATA58 |
| TCELL22:IMUX.IMUX18 | PS.SAXIHP2WDATA59 |
| TCELL22:IMUX.IMUX19 | PS.SAXIHP2ARADDR24 |
| TCELL22:IMUX.IMUX20 | PS.SAXIHP2ARADDR25 |
| TCELL22:IMUX.IMUX21 | PS.SAXIHP2ARADDR26 |
| TCELL22:IMUX.IMUX22 | PS.SAXIHP2ARADDR27 |
| TCELL22:IMUX.IMUX23 | PS.SAXIHP2AWQOS0 |
| TCELL22:IMUX.IMUX24 | PS.SAXIHP2AWQOS1 |
| TCELL22:OUT0.TMIN | PS.SAXIHP2RDATA24 |
| TCELL22:OUT1.TMIN | PS.SAXIHP2RDATA25 |
| TCELL22:OUT2.TMIN | PS.SAXIHP2RDATA26 |
| TCELL22:OUT3.TMIN | PS.SAXIHP2RDATA27 |
| TCELL22:OUT4.TMIN | PS.SAXIHP2RDATA56 |
| TCELL22:OUT5.TMIN | PS.SAXIHP2RDATA57 |
| TCELL22:OUT6.TMIN | PS.SAXIHP2RDATA58 |
| TCELL22:OUT7.TMIN | PS.SAXIHP2RDATA59 |
| TCELL22:OUT8.TMIN | PS.SAXIHP2WCOUNT0 |
| TCELL22:OUT9.TMIN | PS.SAXIHP2WCOUNT1 |
| TCELL22:OUT10.TMIN | PS.SAXIHP2WCOUNT2 |
| TCELL22:OUT11.TMIN | PS.SAXIHP2WCOUNT3 |
| TCELL22:OUT12.TMIN | PS.SAXIHP2WACOUNT2 |
| TCELL22:OUT13.TMIN | PS.SAXIHP2WACOUNT3 |
| TCELL22:OUT20.TMIN | PS.DEBUGDATA91 |
| TCELL22:OUT21.TMIN | PS.DEBUGDATA90 |
| TCELL22:OUT22.TMIN | PS.DEBUGDATA89 |
| TCELL22:OUT23.TMIN | PS.DEBUGDATA88 |
| TCELL23:IMUX.IMUX0 | PS.SAXIHP2AWID4 |
| TCELL23:IMUX.IMUX1 | PS.SAXIHP2AWID5 |
| TCELL23:IMUX.IMUX2 | PS.SAXIHP2AWADDR28 |
| TCELL23:IMUX.IMUX3 | PS.SAXIHP2AWADDR29 |
| TCELL23:IMUX.IMUX4 | PS.SAXIHP2AWADDR30 |
| TCELL23:IMUX.IMUX5 | PS.SAXIHP2AWADDR31 |
| TCELL23:IMUX.IMUX6 | PS.SAXIHP2AWLEN0 |
| TCELL23:IMUX.IMUX7 | PS.SAXIHP2AWLEN1 |
| TCELL23:IMUX.IMUX8 | PS.SAXIHP2AWLEN2 |
| TCELL23:IMUX.IMUX9 | PS.SAXIHP2AWLEN3 |
| TCELL23:IMUX.IMUX10 | PS.SAXIHP2WDATA28 |
| TCELL23:IMUX.IMUX11 | PS.SAXIHP2WDATA29 |
| TCELL23:IMUX.IMUX12 | PS.SAXIHP2WDATA30 |
| TCELL23:IMUX.IMUX13 | PS.SAXIHP2WDATA31 |
| TCELL23:IMUX.IMUX14 | PS.SAXIHP2WDATA60 |
| TCELL23:IMUX.IMUX15 | PS.SAXIHP2WDATA61 |
| TCELL23:IMUX.IMUX16 | PS.SAXIHP2WDATA62 |
| TCELL23:IMUX.IMUX17 | PS.SAXIHP2WDATA63 |
| TCELL23:IMUX.IMUX18 | PS.SAXIHP2ARADDR28 |
| TCELL23:IMUX.IMUX19 | PS.SAXIHP2ARADDR29 |
| TCELL23:IMUX.IMUX20 | PS.SAXIHP2ARADDR30 |
| TCELL23:IMUX.IMUX21 | PS.SAXIHP2ARADDR31 |
| TCELL23:IMUX.IMUX22 | PS.SAXIHP2WRISSUECAP1EN |
| TCELL23:IMUX.IMUX23 | PS.SAXIHP2AWQOS2 |
| TCELL23:IMUX.IMUX24 | PS.SAXIHP2AWQOS3 |
| TCELL23:OUT0.TMIN | PS.SAXIHP2ARESETN |
| TCELL23:OUT1.TMIN | PS.SAXIHP2RDATA28 |
| TCELL23:OUT2.TMIN | PS.SAXIHP2RDATA29 |
| TCELL23:OUT3.TMIN | PS.SAXIHP2RDATA30 |
| TCELL23:OUT4.TMIN | PS.SAXIHP2RDATA31 |
| TCELL23:OUT5.TMIN | PS.SAXIHP2RDATA60 |
| TCELL23:OUT6.TMIN | PS.SAXIHP2RDATA61 |
| TCELL23:OUT7.TMIN | PS.SAXIHP2RDATA62 |
| TCELL23:OUT8.TMIN | PS.SAXIHP2RDATA63 |
| TCELL23:OUT9.TMIN | PS.SAXIHP2WCOUNT4 |
| TCELL23:OUT10.TMIN | PS.SAXIHP2WCOUNT5 |
| TCELL23:OUT11.TMIN | PS.SAXIHP2WCOUNT6 |
| TCELL23:OUT12.TMIN | PS.SAXIHP2WCOUNT7 |
| TCELL23:OUT13.TMIN | PS.SAXIHP2WACOUNT4 |
| TCELL23:OUT14.TMIN | PS.SAXIHP2WACOUNT5 |
| TCELL23:OUT20.TMIN | PS.DEBUGDATA95 |
| TCELL23:OUT21.TMIN | PS.DEBUGDATA94 |
| TCELL23:OUT22.TMIN | PS.DEBUGDATA93 |
| TCELL23:OUT23.TMIN | PS.DEBUGDATA92 |
| TCELL24:IMUX.IMUX0 | PS.SAXIHP3AWADDR0 |
| TCELL24:IMUX.IMUX1 | PS.SAXIHP3AWADDR1 |
| TCELL24:IMUX.IMUX2 | PS.SAXIHP3AWADDR2 |
| TCELL24:IMUX.IMUX3 | PS.SAXIHP3AWADDR3 |
| TCELL24:IMUX.IMUX4 | PS.SAXIHP3WDATA0 |
| TCELL24:IMUX.IMUX5 | PS.SAXIHP3WDATA1 |
| TCELL24:IMUX.IMUX6 | PS.SAXIHP3WDATA2 |
| TCELL24:IMUX.IMUX7 | PS.SAXIHP3WDATA3 |
| TCELL24:IMUX.IMUX8 | PS.SAXIHP3WDATA32 |
| TCELL24:IMUX.IMUX9 | PS.SAXIHP3WDATA33 |
| TCELL24:IMUX.IMUX10 | PS.SAXIHP3WDATA34 |
| TCELL24:IMUX.IMUX11 | PS.SAXIHP3WDATA35 |
| TCELL24:IMUX.IMUX12 | PS.SAXIHP3ARID0 |
| TCELL24:IMUX.IMUX13 | PS.SAXIHP3ARID1 |
| TCELL24:IMUX.IMUX14 | PS.SAXIHP3ARID2 |
| TCELL24:IMUX.IMUX15 | PS.SAXIHP3ARID3 |
| TCELL24:IMUX.IMUX16 | PS.SAXIHP3ARADDR0 |
| TCELL24:IMUX.IMUX17 | PS.SAXIHP3ARADDR1 |
| TCELL24:IMUX.IMUX18 | PS.SAXIHP3ARADDR2 |
| TCELL24:IMUX.IMUX19 | PS.SAXIHP3ARADDR3 |
| TCELL24:IMUX.IMUX20 | PS.SAXIHP3ARSIZE0 |
| TCELL24:IMUX.IMUX21 | PS.SAXIHP3ARSIZE1 |
| TCELL24:IMUX.IMUX22 | PS.SAXIHP3ARBURST0 |
| TCELL24:IMUX.IMUX23 | PS.SAXIHP3ARBURST1 |
| TCELL24:IMUX.IMUX24 | PS.SAXIHP3ARLOCK0 |
| TCELL24:IMUX.IMUX25 | PS.SAXIHP3RDISSUECAP1EN |
| TCELL24:OUT0.TMIN | PS.SAXIHP3RID0 |
| TCELL24:OUT1.TMIN | PS.SAXIHP3RID1 |
| TCELL24:OUT2.TMIN | PS.SAXIHP3RID2 |
| TCELL24:OUT3.TMIN | PS.SAXIHP3RDATA0 |
| TCELL24:OUT4.TMIN | PS.SAXIHP3RDATA1 |
| TCELL24:OUT5.TMIN | PS.SAXIHP3RDATA2 |
| TCELL24:OUT6.TMIN | PS.SAXIHP3RDATA3 |
| TCELL24:OUT7.TMIN | PS.SAXIHP3RDATA32 |
| TCELL24:OUT8.TMIN | PS.SAXIHP3RDATA33 |
| TCELL24:OUT9.TMIN | PS.SAXIHP3RDATA34 |
| TCELL24:OUT10.TMIN | PS.SAXIHP3RDATA35 |
| TCELL24:OUT11.TMIN | PS.SAXIHP3RACOUNT0 |
| TCELL24:OUT12.TMIN | PS.SAXIHP3RACOUNT1 |
| TCELL24:OUT13.TMIN | PS.SAXIHP3RACOUNT2 |
| TCELL24:OUT20.TMIN | PS.DEBUGDATA99 |
| TCELL24:OUT21.TMIN | PS.DEBUGDATA98 |
| TCELL24:OUT22.TMIN | PS.DEBUGDATA97 |
| TCELL24:OUT23.TMIN | PS.DEBUGDATA96 |
| TCELL25:IMUX.IMUX0 | PS.SAXIHP3AWADDR4 |
| TCELL25:IMUX.IMUX1 | PS.SAXIHP3AWADDR5 |
| TCELL25:IMUX.IMUX2 | PS.SAXIHP3AWADDR6 |
| TCELL25:IMUX.IMUX3 | PS.SAXIHP3AWADDR7 |
| TCELL25:IMUX.IMUX4 | PS.SAXIHP3WDATA4 |
| TCELL25:IMUX.IMUX5 | PS.SAXIHP3WDATA5 |
| TCELL25:IMUX.IMUX6 | PS.SAXIHP3WDATA6 |
| TCELL25:IMUX.IMUX7 | PS.SAXIHP3WDATA7 |
| TCELL25:IMUX.IMUX8 | PS.SAXIHP3WDATA36 |
| TCELL25:IMUX.IMUX9 | PS.SAXIHP3WDATA37 |
| TCELL25:IMUX.IMUX10 | PS.SAXIHP3WDATA38 |
| TCELL25:IMUX.IMUX11 | PS.SAXIHP3WDATA39 |
| TCELL25:IMUX.IMUX12 | PS.SAXIHP3ARID4 |
| TCELL25:IMUX.IMUX13 | PS.SAXIHP3ARID5 |
| TCELL25:IMUX.IMUX14 | PS.SAXIHP3ARADDR4 |
| TCELL25:IMUX.IMUX15 | PS.SAXIHP3ARADDR5 |
| TCELL25:IMUX.IMUX16 | PS.SAXIHP3ARADDR6 |
| TCELL25:IMUX.IMUX17 | PS.SAXIHP3ARADDR7 |
| TCELL25:IMUX.IMUX18 | PS.SAXIHP3ARLOCK1 |
| TCELL25:IMUX.IMUX19 | PS.SAXIHP3ARCACHE0 |
| TCELL25:IMUX.IMUX20 | PS.SAXIHP3ARCACHE1 |
| TCELL25:IMUX.IMUX21 | PS.SAXIHP3ARCACHE2 |
| TCELL25:IMUX.IMUX22 | PS.SAXIHP3ARCACHE3 |
| TCELL25:IMUX.IMUX23 | PS.SAXIHP3ARPROT0 |
| TCELL25:IMUX.IMUX24 | PS.SAXIHP3ARPROT1 |
| TCELL25:OUT0.TMIN | PS.SAXIHP3RID3 |
| TCELL25:OUT1.TMIN | PS.SAXIHP3RID4 |
| TCELL25:OUT2.TMIN | PS.SAXIHP3RID5 |
| TCELL25:OUT3.TMIN | PS.SAXIHP3RDATA4 |
| TCELL25:OUT4.TMIN | PS.SAXIHP3RDATA5 |
| TCELL25:OUT5.TMIN | PS.SAXIHP3RDATA6 |
| TCELL25:OUT6.TMIN | PS.SAXIHP3RDATA7 |
| TCELL25:OUT7.TMIN | PS.SAXIHP3RDATA36 |
| TCELL25:OUT8.TMIN | PS.SAXIHP3RDATA37 |
| TCELL25:OUT9.TMIN | PS.SAXIHP3RDATA38 |
| TCELL25:OUT10.TMIN | PS.SAXIHP3RDATA39 |
| TCELL25:OUT11.TMIN | PS.SAXIHP3RCOUNT0 |
| TCELL25:OUT12.TMIN | PS.SAXIHP3RCOUNT1 |
| TCELL25:OUT13.TMIN | PS.SAXIHP3RCOUNT2 |
| TCELL25:OUT14.TMIN | PS.SAXIHP3RCOUNT3 |
| TCELL25:OUT20.TMIN | PS.DEBUGDATA103 |
| TCELL25:OUT21.TMIN | PS.DEBUGDATA102 |
| TCELL25:OUT22.TMIN | PS.DEBUGDATA101 |
| TCELL25:OUT23.TMIN | PS.DEBUGDATA100 |
| TCELL26:IMUX.IMUX0 | PS.SAXIHP3AWADDR8 |
| TCELL26:IMUX.IMUX1 | PS.SAXIHP3AWADDR9 |
| TCELL26:IMUX.IMUX2 | PS.SAXIHP3AWADDR10 |
| TCELL26:IMUX.IMUX3 | PS.SAXIHP3AWADDR11 |
| TCELL26:IMUX.IMUX4 | PS.SAXIHP3WDATA8 |
| TCELL26:IMUX.IMUX5 | PS.SAXIHP3WDATA9 |
| TCELL26:IMUX.IMUX6 | PS.SAXIHP3WDATA10 |
| TCELL26:IMUX.IMUX7 | PS.SAXIHP3WDATA11 |
| TCELL26:IMUX.IMUX8 | PS.SAXIHP3WDATA40 |
| TCELL26:IMUX.IMUX9 | PS.SAXIHP3WDATA41 |
| TCELL26:IMUX.IMUX10 | PS.SAXIHP3WDATA42 |
| TCELL26:IMUX.IMUX11 | PS.SAXIHP3WDATA43 |
| TCELL26:IMUX.IMUX12 | PS.SAXIHP3WSTRB0 |
| TCELL26:IMUX.IMUX13 | PS.SAXIHP3WSTRB1 |
| TCELL26:IMUX.IMUX14 | PS.SAXIHP3WSTRB2 |
| TCELL26:IMUX.IMUX15 | PS.SAXIHP3WSTRB3 |
| TCELL26:IMUX.IMUX16 | PS.SAXIHP3WLAST |
| TCELL26:IMUX.IMUX17 | PS.SAXIHP3ARADDR8 |
| TCELL26:IMUX.IMUX18 | PS.SAXIHP3ARADDR9 |
| TCELL26:IMUX.IMUX19 | PS.SAXIHP3ARADDR10 |
| TCELL26:IMUX.IMUX20 | PS.SAXIHP3ARADDR11 |
| TCELL26:IMUX.IMUX21 | PS.SAXIHP3ARLEN0 |
| TCELL26:IMUX.IMUX22 | PS.SAXIHP3ARLEN1 |
| TCELL26:IMUX.IMUX23 | PS.SAXIHP3ARLEN2 |
| TCELL26:IMUX.IMUX24 | PS.SAXIHP3ARLEN3 |
| TCELL26:IMUX.IMUX25 | PS.SAXIHP3ARPROT2 |
| TCELL26:OUT0.TMIN | PS.SAXIHP3BRESP0 |
| TCELL26:OUT1.TMIN | PS.SAXIHP3BRESP1 |
| TCELL26:OUT2.TMIN | PS.SAXIHP3RDATA8 |
| TCELL26:OUT3.TMIN | PS.SAXIHP3RDATA9 |
| TCELL26:OUT4.TMIN | PS.SAXIHP3RDATA10 |
| TCELL26:OUT5.TMIN | PS.SAXIHP3RDATA11 |
| TCELL26:OUT6.TMIN | PS.SAXIHP3RDATA40 |
| TCELL26:OUT7.TMIN | PS.SAXIHP3RDATA41 |
| TCELL26:OUT8.TMIN | PS.SAXIHP3RDATA42 |
| TCELL26:OUT9.TMIN | PS.SAXIHP3RDATA43 |
| TCELL26:OUT10.TMIN | PS.SAXIHP3RCOUNT4 |
| TCELL26:OUT11.TMIN | PS.SAXIHP3RCOUNT5 |
| TCELL26:OUT12.TMIN | PS.SAXIHP3RCOUNT6 |
| TCELL26:OUT13.TMIN | PS.SAXIHP3RCOUNT7 |
| TCELL26:OUT20.TMIN | PS.DEBUGDATA107 |
| TCELL26:OUT21.TMIN | PS.DEBUGDATA106 |
| TCELL26:OUT22.TMIN | PS.DEBUGDATA105 |
| TCELL26:OUT23.TMIN | PS.DEBUGDATA104 |
| TCELL27:IMUX.IMUX0 | PS.SAXIHP3AWADDR12 |
| TCELL27:IMUX.IMUX1 | PS.SAXIHP3AWADDR13 |
| TCELL27:IMUX.IMUX2 | PS.SAXIHP3AWADDR14 |
| TCELL27:IMUX.IMUX3 | PS.SAXIHP3AWADDR15 |
| TCELL27:IMUX.IMUX4 | PS.SAXIHP3WDATA12 |
| TCELL27:IMUX.IMUX5 | PS.SAXIHP3WDATA13 |
| TCELL27:IMUX.IMUX6 | PS.SAXIHP3WDATA14 |
| TCELL27:IMUX.IMUX7 | PS.SAXIHP3WDATA15 |
| TCELL27:IMUX.IMUX8 | PS.SAXIHP3WDATA44 |
| TCELL27:IMUX.IMUX9 | PS.SAXIHP3WDATA45 |
| TCELL27:IMUX.IMUX10 | PS.SAXIHP3WDATA46 |
| TCELL27:IMUX.IMUX11 | PS.SAXIHP3WDATA47 |
| TCELL27:IMUX.IMUX12 | PS.SAXIHP3WSTRB4 |
| TCELL27:IMUX.IMUX13 | PS.SAXIHP3WSTRB5 |
| TCELL27:IMUX.IMUX14 | PS.SAXIHP3WSTRB6 |
| TCELL27:IMUX.IMUX15 | PS.SAXIHP3WSTRB7 |
| TCELL27:IMUX.IMUX16 | PS.SAXIHP3ARADDR12 |
| TCELL27:IMUX.IMUX17 | PS.SAXIHP3ARADDR13 |
| TCELL27:IMUX.IMUX18 | PS.SAXIHP3ARADDR14 |
| TCELL27:IMUX.IMUX19 | PS.SAXIHP3ARADDR15 |
| TCELL27:IMUX.IMUX20 | PS.SAXIHP3ARVALID |
| TCELL27:IMUX.IMUX21 | PS.SAXIHP3RREADY |
| TCELL27:IMUX.IMUX22 | PS.SAXIHP3ARQOS0 |
| TCELL27:IMUX.IMUX23 | PS.SAXIHP3ARQOS1 |
| TCELL27:IMUX.IMUX24 | PS.SAXIHP3ARQOS2 |
| TCELL27:IMUX.IMUX25 | PS.SAXIHP3ARQOS3 |
| TCELL27:OUT0.TMIN | PS.SAXIHP3ARREADY |
| TCELL27:OUT1.TMIN | PS.SAXIHP3RDATA12 |
| TCELL27:OUT2.TMIN | PS.SAXIHP3RDATA13 |
| TCELL27:OUT3.TMIN | PS.SAXIHP3RDATA14 |
| TCELL27:OUT4.TMIN | PS.SAXIHP3RDATA15 |
| TCELL27:OUT5.TMIN | PS.SAXIHP3RDATA44 |
| TCELL27:OUT6.TMIN | PS.SAXIHP3RDATA45 |
| TCELL27:OUT7.TMIN | PS.SAXIHP3RDATA46 |
| TCELL27:OUT8.TMIN | PS.SAXIHP3RDATA47 |
| TCELL27:OUT9.TMIN | PS.SAXIHP3RRESP0 |
| TCELL27:OUT10.TMIN | PS.SAXIHP3RRESP1 |
| TCELL27:OUT11.TMIN | PS.SAXIHP3RLAST |
| TCELL27:OUT12.TMIN | PS.SAXIHP3RVALID |
| TCELL27:OUT20.TMIN | PS.DEBUGDATA111 |
| TCELL27:OUT21.TMIN | PS.DEBUGDATA110 |
| TCELL27:OUT22.TMIN | PS.DEBUGDATA109 |
| TCELL27:OUT23.TMIN | PS.DEBUGDATA108 |
| TCELL28:IMUX.CLK0 | PS.SAXIHP3ACLK |
| TCELL28:IMUX.IMUX0 | PS.SAXIHP3AWADDR16 |
| TCELL28:IMUX.IMUX1 | PS.SAXIHP3AWADDR17 |
| TCELL28:IMUX.IMUX2 | PS.SAXIHP3AWADDR18 |
| TCELL28:IMUX.IMUX3 | PS.SAXIHP3AWADDR19 |
| TCELL28:IMUX.IMUX4 | PS.SAXIHP3AWCACHE0 |
| TCELL28:IMUX.IMUX5 | PS.SAXIHP3AWCACHE1 |
| TCELL28:IMUX.IMUX6 | PS.SAXIHP3AWPROT0 |
| TCELL28:IMUX.IMUX7 | PS.SAXIHP3AWPROT1 |
| TCELL28:IMUX.IMUX8 | PS.SAXIHP3AWPROT2 |
| TCELL28:IMUX.IMUX9 | PS.SAXIHP3AWVALID |
| TCELL28:IMUX.IMUX10 | PS.SAXIHP3WID0 |
| TCELL28:IMUX.IMUX11 | PS.SAXIHP3WID1 |
| TCELL28:IMUX.IMUX12 | PS.SAXIHP3WDATA16 |
| TCELL28:IMUX.IMUX13 | PS.SAXIHP3WDATA17 |
| TCELL28:IMUX.IMUX14 | PS.SAXIHP3WDATA18 |
| TCELL28:IMUX.IMUX15 | PS.SAXIHP3WDATA19 |
| TCELL28:IMUX.IMUX16 | PS.SAXIHP3WDATA48 |
| TCELL28:IMUX.IMUX17 | PS.SAXIHP3WDATA49 |
| TCELL28:IMUX.IMUX18 | PS.SAXIHP3WDATA50 |
| TCELL28:IMUX.IMUX19 | PS.SAXIHP3WDATA51 |
| TCELL28:IMUX.IMUX20 | PS.SAXIHP3WVALID |
| TCELL28:IMUX.IMUX21 | PS.SAXIHP3BREADY |
| TCELL28:IMUX.IMUX22 | PS.SAXIHP3ARADDR16 |
| TCELL28:IMUX.IMUX23 | PS.SAXIHP3ARADDR17 |
| TCELL28:IMUX.IMUX24 | PS.SAXIHP3ARADDR18 |
| TCELL28:IMUX.IMUX25 | PS.SAXIHP3ARADDR19 |
| TCELL28:OUT0.TMIN | PS.SAXIHP3AWREADY |
| TCELL28:OUT1.TMIN | PS.SAXIHP3WREADY |
| TCELL28:OUT2.TMIN | PS.SAXIHP3BID0 |
| TCELL28:OUT3.TMIN | PS.SAXIHP3BID1 |
| TCELL28:OUT4.TMIN | PS.SAXIHP3BVALID |
| TCELL28:OUT5.TMIN | PS.SAXIHP3RDATA16 |
| TCELL28:OUT6.TMIN | PS.SAXIHP3RDATA17 |
| TCELL28:OUT7.TMIN | PS.SAXIHP3RDATA18 |
| TCELL28:OUT8.TMIN | PS.SAXIHP3RDATA19 |
| TCELL28:OUT9.TMIN | PS.SAXIHP3RDATA48 |
| TCELL28:OUT10.TMIN | PS.SAXIHP3RDATA49 |
| TCELL28:OUT11.TMIN | PS.SAXIHP3RDATA50 |
| TCELL28:OUT12.TMIN | PS.SAXIHP3RDATA51 |
| TCELL28:OUT20.TMIN | PS.DEBUGDATA115 |
| TCELL28:OUT21.TMIN | PS.DEBUGDATA114 |
| TCELL28:OUT22.TMIN | PS.DEBUGDATA113 |
| TCELL28:OUT23.TMIN | PS.DEBUGDATA112 |
| TCELL29:IMUX.IMUX0 | PS.SAXIHP3AWADDR20 |
| TCELL29:IMUX.IMUX1 | PS.SAXIHP3AWADDR21 |
| TCELL29:IMUX.IMUX2 | PS.SAXIHP3AWADDR22 |
| TCELL29:IMUX.IMUX3 | PS.SAXIHP3AWADDR23 |
| TCELL29:IMUX.IMUX4 | PS.SAXIHP3AWBURST0 |
| TCELL29:IMUX.IMUX5 | PS.SAXIHP3AWLOCK0 |
| TCELL29:IMUX.IMUX6 | PS.SAXIHP3AWLOCK1 |
| TCELL29:IMUX.IMUX7 | PS.SAXIHP3AWCACHE2 |
| TCELL29:IMUX.IMUX8 | PS.SAXIHP3AWCACHE3 |
| TCELL29:IMUX.IMUX9 | PS.SAXIHP3WID2 |
| TCELL29:IMUX.IMUX10 | PS.SAXIHP3WID3 |
| TCELL29:IMUX.IMUX11 | PS.SAXIHP3WID4 |
| TCELL29:IMUX.IMUX12 | PS.SAXIHP3WID5 |
| TCELL29:IMUX.IMUX13 | PS.SAXIHP3WDATA20 |
| TCELL29:IMUX.IMUX14 | PS.SAXIHP3WDATA21 |
| TCELL29:IMUX.IMUX15 | PS.SAXIHP3WDATA22 |
| TCELL29:IMUX.IMUX16 | PS.SAXIHP3WDATA23 |
| TCELL29:IMUX.IMUX17 | PS.SAXIHP3WDATA52 |
| TCELL29:IMUX.IMUX18 | PS.SAXIHP3WDATA53 |
| TCELL29:IMUX.IMUX19 | PS.SAXIHP3WDATA54 |
| TCELL29:IMUX.IMUX20 | PS.SAXIHP3WDATA55 |
| TCELL29:IMUX.IMUX21 | PS.SAXIHP3ARADDR20 |
| TCELL29:IMUX.IMUX22 | PS.SAXIHP3ARADDR21 |
| TCELL29:IMUX.IMUX23 | PS.SAXIHP3ARADDR22 |
| TCELL29:IMUX.IMUX24 | PS.SAXIHP3ARADDR23 |
| TCELL29:OUT0.TMIN | PS.SAXIHP3BID2 |
| TCELL29:OUT1.TMIN | PS.SAXIHP3BID3 |
| TCELL29:OUT2.TMIN | PS.SAXIHP3BID4 |
| TCELL29:OUT3.TMIN | PS.SAXIHP3BID5 |
| TCELL29:OUT4.TMIN | PS.SAXIHP3RDATA20 |
| TCELL29:OUT5.TMIN | PS.SAXIHP3RDATA21 |
| TCELL29:OUT6.TMIN | PS.SAXIHP3RDATA22 |
| TCELL29:OUT7.TMIN | PS.SAXIHP3RDATA23 |
| TCELL29:OUT8.TMIN | PS.SAXIHP3RDATA52 |
| TCELL29:OUT9.TMIN | PS.SAXIHP3RDATA53 |
| TCELL29:OUT10.TMIN | PS.SAXIHP3RDATA54 |
| TCELL29:OUT11.TMIN | PS.SAXIHP3RDATA55 |
| TCELL29:OUT12.TMIN | PS.SAXIHP3WACOUNT0 |
| TCELL29:OUT13.TMIN | PS.SAXIHP3WACOUNT1 |
| TCELL29:OUT20.TMIN | PS.DEBUGDATA119 |
| TCELL29:OUT21.TMIN | PS.DEBUGDATA118 |
| TCELL29:OUT22.TMIN | PS.DEBUGDATA117 |
| TCELL29:OUT23.TMIN | PS.DEBUGDATA116 |
| TCELL30:IMUX.IMUX0 | PS.SAXIHP3AWID0 |
| TCELL30:IMUX.IMUX1 | PS.SAXIHP3AWID1 |
| TCELL30:IMUX.IMUX2 | PS.SAXIHP3AWID2 |
| TCELL30:IMUX.IMUX3 | PS.SAXIHP3AWID3 |
| TCELL30:IMUX.IMUX4 | PS.SAXIHP3AWADDR24 |
| TCELL30:IMUX.IMUX5 | PS.SAXIHP3AWADDR25 |
| TCELL30:IMUX.IMUX6 | PS.SAXIHP3AWADDR26 |
| TCELL30:IMUX.IMUX7 | PS.SAXIHP3AWADDR27 |
| TCELL30:IMUX.IMUX8 | PS.SAXIHP3AWSIZE0 |
| TCELL30:IMUX.IMUX9 | PS.SAXIHP3AWSIZE1 |
| TCELL30:IMUX.IMUX10 | PS.SAXIHP3AWBURST1 |
| TCELL30:IMUX.IMUX11 | PS.SAXIHP3WDATA24 |
| TCELL30:IMUX.IMUX12 | PS.SAXIHP3WDATA25 |
| TCELL30:IMUX.IMUX13 | PS.SAXIHP3WDATA26 |
| TCELL30:IMUX.IMUX14 | PS.SAXIHP3WDATA27 |
| TCELL30:IMUX.IMUX15 | PS.SAXIHP3WDATA56 |
| TCELL30:IMUX.IMUX16 | PS.SAXIHP3WDATA57 |
| TCELL30:IMUX.IMUX17 | PS.SAXIHP3WDATA58 |
| TCELL30:IMUX.IMUX18 | PS.SAXIHP3WDATA59 |
| TCELL30:IMUX.IMUX19 | PS.SAXIHP3ARADDR24 |
| TCELL30:IMUX.IMUX20 | PS.SAXIHP3ARADDR25 |
| TCELL30:IMUX.IMUX21 | PS.SAXIHP3ARADDR26 |
| TCELL30:IMUX.IMUX22 | PS.SAXIHP3ARADDR27 |
| TCELL30:IMUX.IMUX23 | PS.SAXIHP3AWQOS0 |
| TCELL30:IMUX.IMUX24 | PS.SAXIHP3AWQOS1 |
| TCELL30:OUT0.TMIN | PS.SAXIHP3RDATA24 |
| TCELL30:OUT1.TMIN | PS.SAXIHP3RDATA25 |
| TCELL30:OUT2.TMIN | PS.SAXIHP3RDATA26 |
| TCELL30:OUT3.TMIN | PS.SAXIHP3RDATA27 |
| TCELL30:OUT4.TMIN | PS.SAXIHP3RDATA56 |
| TCELL30:OUT5.TMIN | PS.SAXIHP3RDATA57 |
| TCELL30:OUT6.TMIN | PS.SAXIHP3RDATA58 |
| TCELL30:OUT7.TMIN | PS.SAXIHP3RDATA59 |
| TCELL30:OUT8.TMIN | PS.SAXIHP3WCOUNT0 |
| TCELL30:OUT9.TMIN | PS.SAXIHP3WCOUNT1 |
| TCELL30:OUT10.TMIN | PS.SAXIHP3WCOUNT2 |
| TCELL30:OUT11.TMIN | PS.SAXIHP3WCOUNT3 |
| TCELL30:OUT12.TMIN | PS.SAXIHP3WACOUNT2 |
| TCELL30:OUT13.TMIN | PS.SAXIHP3WACOUNT3 |
| TCELL30:OUT20.TMIN | PS.DEBUGDATA123 |
| TCELL30:OUT21.TMIN | PS.DEBUGDATA122 |
| TCELL30:OUT22.TMIN | PS.DEBUGDATA121 |
| TCELL30:OUT23.TMIN | PS.DEBUGDATA120 |
| TCELL31:IMUX.IMUX0 | PS.SAXIHP3AWID4 |
| TCELL31:IMUX.IMUX1 | PS.SAXIHP3AWID5 |
| TCELL31:IMUX.IMUX2 | PS.SAXIHP3AWADDR28 |
| TCELL31:IMUX.IMUX3 | PS.SAXIHP3AWADDR29 |
| TCELL31:IMUX.IMUX4 | PS.SAXIHP3AWADDR30 |
| TCELL31:IMUX.IMUX5 | PS.SAXIHP3AWADDR31 |
| TCELL31:IMUX.IMUX6 | PS.SAXIHP3AWLEN0 |
| TCELL31:IMUX.IMUX7 | PS.SAXIHP3AWLEN1 |
| TCELL31:IMUX.IMUX8 | PS.SAXIHP3AWLEN2 |
| TCELL31:IMUX.IMUX9 | PS.SAXIHP3AWLEN3 |
| TCELL31:IMUX.IMUX10 | PS.SAXIHP3WDATA28 |
| TCELL31:IMUX.IMUX11 | PS.SAXIHP3WDATA29 |
| TCELL31:IMUX.IMUX12 | PS.SAXIHP3WDATA30 |
| TCELL31:IMUX.IMUX13 | PS.SAXIHP3WDATA31 |
| TCELL31:IMUX.IMUX14 | PS.SAXIHP3WDATA60 |
| TCELL31:IMUX.IMUX15 | PS.SAXIHP3WDATA61 |
| TCELL31:IMUX.IMUX16 | PS.SAXIHP3WDATA62 |
| TCELL31:IMUX.IMUX17 | PS.SAXIHP3WDATA63 |
| TCELL31:IMUX.IMUX18 | PS.SAXIHP3ARADDR28 |
| TCELL31:IMUX.IMUX19 | PS.SAXIHP3ARADDR29 |
| TCELL31:IMUX.IMUX20 | PS.SAXIHP3ARADDR30 |
| TCELL31:IMUX.IMUX21 | PS.SAXIHP3ARADDR31 |
| TCELL31:IMUX.IMUX22 | PS.SAXIHP3WRISSUECAP1EN |
| TCELL31:IMUX.IMUX23 | PS.SAXIHP3AWQOS2 |
| TCELL31:IMUX.IMUX24 | PS.SAXIHP3AWQOS3 |
| TCELL31:OUT0.TMIN | PS.SAXIHP3ARESETN |
| TCELL31:OUT1.TMIN | PS.SAXIHP3RDATA28 |
| TCELL31:OUT2.TMIN | PS.SAXIHP3RDATA29 |
| TCELL31:OUT3.TMIN | PS.SAXIHP3RDATA30 |
| TCELL31:OUT4.TMIN | PS.SAXIHP3RDATA31 |
| TCELL31:OUT5.TMIN | PS.SAXIHP3RDATA60 |
| TCELL31:OUT6.TMIN | PS.SAXIHP3RDATA61 |
| TCELL31:OUT7.TMIN | PS.SAXIHP3RDATA62 |
| TCELL31:OUT8.TMIN | PS.SAXIHP3RDATA63 |
| TCELL31:OUT9.TMIN | PS.SAXIHP3WCOUNT4 |
| TCELL31:OUT10.TMIN | PS.SAXIHP3WCOUNT5 |
| TCELL31:OUT11.TMIN | PS.SAXIHP3WCOUNT6 |
| TCELL31:OUT12.TMIN | PS.SAXIHP3WCOUNT7 |
| TCELL31:OUT13.TMIN | PS.SAXIHP3WACOUNT4 |
| TCELL31:OUT14.TMIN | PS.SAXIHP3WACOUNT5 |
| TCELL31:OUT20.TMIN | PS.DEBUGDATA127 |
| TCELL31:OUT21.TMIN | PS.DEBUGDATA126 |
| TCELL31:OUT22.TMIN | PS.DEBUGDATA125 |
| TCELL31:OUT23.TMIN | PS.DEBUGDATA124 |
| TCELL32:IMUX.IMUX0 | PS.SAXIACPAWADDR0 |
| TCELL32:IMUX.IMUX1 | PS.SAXIACPAWADDR1 |
| TCELL32:IMUX.IMUX2 | PS.SAXIACPAWADDR2 |
| TCELL32:IMUX.IMUX3 | PS.SAXIACPAWADDR3 |
| TCELL32:IMUX.IMUX4 | PS.SAXIACPWDATA0 |
| TCELL32:IMUX.IMUX5 | PS.SAXIACPWDATA1 |
| TCELL32:IMUX.IMUX6 | PS.SAXIACPWDATA2 |
| TCELL32:IMUX.IMUX7 | PS.SAXIACPWDATA3 |
| TCELL32:IMUX.IMUX8 | PS.SAXIACPWDATA32 |
| TCELL32:IMUX.IMUX9 | PS.SAXIACPWDATA33 |
| TCELL32:IMUX.IMUX10 | PS.SAXIACPWDATA34 |
| TCELL32:IMUX.IMUX11 | PS.SAXIACPWDATA35 |
| TCELL32:IMUX.IMUX12 | PS.SAXIACPARADDR0 |
| TCELL32:IMUX.IMUX13 | PS.SAXIACPARADDR1 |
| TCELL32:IMUX.IMUX14 | PS.SAXIACPARADDR2 |
| TCELL32:IMUX.IMUX15 | PS.SAXIACPARADDR3 |
| TCELL32:IMUX.IMUX16 | PS.SAXIACPARLEN0 |
| TCELL32:IMUX.IMUX17 | PS.SAXIACPARLEN1 |
| TCELL32:IMUX.IMUX18 | PS.SAXIACPARBURST0 |
| TCELL32:IMUX.IMUX19 | PS.SAXIACPARBURST1 |
| TCELL32:IMUX.IMUX20 | PS.SAXIACPARLOCK0 |
| TCELL32:IMUX.IMUX21 | PS.SAXIACPARLOCK1 |
| TCELL32:IMUX.IMUX22 | PS.SAXIACPARUSER0 |
| TCELL32:IMUX.IMUX23 | PS.SAXIACPARUSER1 |
| TCELL32:IMUX.IMUX24 | PS.SAXIACPARUSER2 |
| TCELL32:IMUX.IMUX25 | PS.SAXIACPARUSER3 |
| TCELL32:OUT0.TMIN | PS.DMA0DATYPE0 |
| TCELL32:OUT1.TMIN | PS.DMA0DATYPE1 |
| TCELL32:OUT2.TMIN | PS.DMA0DAVALID |
| TCELL32:OUT3.TMIN | PS.DMA2DATYPE0 |
| TCELL32:OUT4.TMIN | PS.DMA2DATYPE1 |
| TCELL32:OUT5.TMIN | PS.DMA2DAVALID |
| TCELL32:OUT6.TMIN | PS.SAXIACPRDATA0 |
| TCELL32:OUT7.TMIN | PS.SAXIACPRDATA1 |
| TCELL32:OUT8.TMIN | PS.SAXIACPRDATA2 |
| TCELL32:OUT9.TMIN | PS.SAXIACPRDATA3 |
| TCELL32:OUT10.TMIN | PS.SAXIACPRDATA32 |
| TCELL32:OUT11.TMIN | PS.SAXIACPRDATA33 |
| TCELL32:OUT12.TMIN | PS.SAXIACPRDATA34 |
| TCELL32:OUT13.TMIN | PS.SAXIACPRDATA35 |
| TCELL32:OUT20.TMIN | PS.DEBUGDATA131 |
| TCELL32:OUT21.TMIN | PS.DEBUGDATA130 |
| TCELL32:OUT22.TMIN | PS.DEBUGDATA129 |
| TCELL32:OUT23.TMIN | PS.DEBUGDATA128 |
| TCELL33:IMUX.IMUX0 | PS.SAXIACPAWADDR4 |
| TCELL33:IMUX.IMUX1 | PS.SAXIACPAWADDR5 |
| TCELL33:IMUX.IMUX2 | PS.SAXIACPAWADDR6 |
| TCELL33:IMUX.IMUX3 | PS.SAXIACPAWADDR7 |
| TCELL33:IMUX.IMUX4 | PS.SAXIACPWDATA4 |
| TCELL33:IMUX.IMUX5 | PS.SAXIACPWDATA5 |
| TCELL33:IMUX.IMUX6 | PS.SAXIACPWDATA6 |
| TCELL33:IMUX.IMUX7 | PS.SAXIACPWDATA7 |
| TCELL33:IMUX.IMUX8 | PS.SAXIACPWDATA36 |
| TCELL33:IMUX.IMUX9 | PS.SAXIACPWDATA37 |
| TCELL33:IMUX.IMUX10 | PS.SAXIACPWDATA38 |
| TCELL33:IMUX.IMUX11 | PS.SAXIACPWDATA39 |
| TCELL33:IMUX.IMUX12 | PS.SAXIACPARADDR4 |
| TCELL33:IMUX.IMUX13 | PS.SAXIACPARADDR5 |
| TCELL33:IMUX.IMUX14 | PS.SAXIACPARADDR6 |
| TCELL33:IMUX.IMUX15 | PS.SAXIACPARADDR7 |
| TCELL33:IMUX.IMUX16 | PS.SAXIACPARLEN2 |
| TCELL33:IMUX.IMUX17 | PS.SAXIACPARLEN3 |
| TCELL33:IMUX.IMUX18 | PS.SAXIACPARSIZE0 |
| TCELL33:IMUX.IMUX19 | PS.SAXIACPARSIZE1 |
| TCELL33:IMUX.IMUX20 | PS.SAXIACPARCACHE0 |
| TCELL33:IMUX.IMUX21 | PS.SAXIACPARCACHE1 |
| TCELL33:IMUX.IMUX22 | PS.SAXIACPARCACHE2 |
| TCELL33:IMUX.IMUX23 | PS.SAXIACPARCACHE3 |
| TCELL33:IMUX.IMUX24 | PS.SAXIACPARPROT0 |
| TCELL33:IMUX.IMUX25 | PS.SAXIACPARPROT1 |
| TCELL33:IMUX.IMUX26 | PS.SAXIACPARUSER4 |
| TCELL33:OUT0.TMIN | PS.DMA1DATYPE0 |
| TCELL33:OUT1.TMIN | PS.DMA1DATYPE1 |
| TCELL33:OUT2.TMIN | PS.DMA1DAVALID |
| TCELL33:OUT3.TMIN | PS.DMA3DATYPE0 |
| TCELL33:OUT4.TMIN | PS.DMA3DATYPE1 |
| TCELL33:OUT5.TMIN | PS.DMA3DAVALID |
| TCELL33:OUT6.TMIN | PS.SAXIACPRDATA4 |
| TCELL33:OUT7.TMIN | PS.SAXIACPRDATA5 |
| TCELL33:OUT8.TMIN | PS.SAXIACPRDATA6 |
| TCELL33:OUT9.TMIN | PS.SAXIACPRDATA7 |
| TCELL33:OUT10.TMIN | PS.SAXIACPRDATA36 |
| TCELL33:OUT11.TMIN | PS.SAXIACPRDATA37 |
| TCELL33:OUT12.TMIN | PS.SAXIACPRDATA38 |
| TCELL33:OUT13.TMIN | PS.SAXIACPRDATA39 |
| TCELL33:OUT20.TMIN | PS.DEBUGDATA135 |
| TCELL33:OUT21.TMIN | PS.DEBUGDATA134 |
| TCELL33:OUT22.TMIN | PS.DEBUGDATA133 |
| TCELL33:OUT23.TMIN | PS.DEBUGDATA132 |
| TCELL34:IMUX.IMUX0 | PS.SAXIACPAWADDR8 |
| TCELL34:IMUX.IMUX1 | PS.SAXIACPAWADDR9 |
| TCELL34:IMUX.IMUX2 | PS.SAXIACPAWADDR10 |
| TCELL34:IMUX.IMUX3 | PS.SAXIACPAWADDR11 |
| TCELL34:IMUX.IMUX4 | PS.SAXIACPWDATA8 |
| TCELL34:IMUX.IMUX5 | PS.SAXIACPWDATA9 |
| TCELL34:IMUX.IMUX6 | PS.SAXIACPWDATA10 |
| TCELL34:IMUX.IMUX7 | PS.SAXIACPWDATA11 |
| TCELL34:IMUX.IMUX8 | PS.SAXIACPWDATA40 |
| TCELL34:IMUX.IMUX9 | PS.SAXIACPWDATA41 |
| TCELL34:IMUX.IMUX10 | PS.SAXIACPWDATA42 |
| TCELL34:IMUX.IMUX11 | PS.SAXIACPWDATA43 |
| TCELL34:IMUX.IMUX12 | PS.SAXIACPWSTRB0 |
| TCELL34:IMUX.IMUX13 | PS.SAXIACPWSTRB1 |
| TCELL34:IMUX.IMUX14 | PS.SAXIACPWSTRB2 |
| TCELL34:IMUX.IMUX15 | PS.SAXIACPWSTRB3 |
| TCELL34:IMUX.IMUX16 | PS.SAXIACPARID0 |
| TCELL34:IMUX.IMUX17 | PS.SAXIACPARID1 |
| TCELL34:IMUX.IMUX18 | PS.SAXIACPARADDR8 |
| TCELL34:IMUX.IMUX19 | PS.SAXIACPARADDR9 |
| TCELL34:IMUX.IMUX20 | PS.SAXIACPARADDR10 |
| TCELL34:IMUX.IMUX21 | PS.SAXIACPARADDR11 |
| TCELL34:IMUX.IMUX22 | PS.SAXIACPARQOS0 |
| TCELL34:IMUX.IMUX23 | PS.SAXIACPARQOS1 |
| TCELL34:IMUX.IMUX24 | PS.SAXIACPARQOS2 |
| TCELL34:IMUX.IMUX25 | PS.SAXIACPARQOS3 |
| TCELL34:OUT0.TMIN | PS.SAXIACPBID0 |
| TCELL34:OUT1.TMIN | PS.SAXIACPBID1 |
| TCELL34:OUT2.TMIN | PS.SAXIACPBID2 |
| TCELL34:OUT3.TMIN | PS.SAXIACPRID0 |
| TCELL34:OUT4.TMIN | PS.SAXIACPRID1 |
| TCELL34:OUT5.TMIN | PS.SAXIACPRDATA8 |
| TCELL34:OUT6.TMIN | PS.SAXIACPRDATA9 |
| TCELL34:OUT7.TMIN | PS.SAXIACPRDATA10 |
| TCELL34:OUT8.TMIN | PS.SAXIACPRDATA11 |
| TCELL34:OUT9.TMIN | PS.SAXIACPRDATA40 |
| TCELL34:OUT10.TMIN | PS.SAXIACPRDATA41 |
| TCELL34:OUT11.TMIN | PS.SAXIACPRDATA42 |
| TCELL34:OUT12.TMIN | PS.SAXIACPRDATA43 |
| TCELL34:OUT20.TMIN | PS.DEBUGDATA139 |
| TCELL34:OUT21.TMIN | PS.DEBUGDATA138 |
| TCELL34:OUT22.TMIN | PS.DEBUGDATA137 |
| TCELL34:OUT23.TMIN | PS.DEBUGDATA136 |
| TCELL35:IMUX.CLK0 | PS.SAXIACPACLK |
| TCELL35:IMUX.IMUX0 | PS.SAXIACPAWADDR12 |
| TCELL35:IMUX.IMUX1 | PS.SAXIACPAWADDR13 |
| TCELL35:IMUX.IMUX2 | PS.SAXIACPAWADDR14 |
| TCELL35:IMUX.IMUX3 | PS.SAXIACPAWADDR15 |
| TCELL35:IMUX.IMUX4 | PS.SAXIACPAWUSER0 |
| TCELL35:IMUX.IMUX5 | PS.SAXIACPWDATA12 |
| TCELL35:IMUX.IMUX6 | PS.SAXIACPWDATA13 |
| TCELL35:IMUX.IMUX7 | PS.SAXIACPWDATA14 |
| TCELL35:IMUX.IMUX8 | PS.SAXIACPWDATA15 |
| TCELL35:IMUX.IMUX9 | PS.SAXIACPWDATA44 |
| TCELL35:IMUX.IMUX10 | PS.SAXIACPWDATA45 |
| TCELL35:IMUX.IMUX11 | PS.SAXIACPWDATA46 |
| TCELL35:IMUX.IMUX12 | PS.SAXIACPWDATA47 |
| TCELL35:IMUX.IMUX13 | PS.SAXIACPWSTRB4 |
| TCELL35:IMUX.IMUX14 | PS.SAXIACPWSTRB5 |
| TCELL35:IMUX.IMUX15 | PS.SAXIACPWSTRB6 |
| TCELL35:IMUX.IMUX16 | PS.SAXIACPWSTRB7 |
| TCELL35:IMUX.IMUX17 | PS.SAXIACPWLAST |
| TCELL35:IMUX.IMUX18 | PS.SAXIACPWVALID |
| TCELL35:IMUX.IMUX19 | PS.SAXIACPARID2 |
| TCELL35:IMUX.IMUX20 | PS.SAXIACPARADDR12 |
| TCELL35:IMUX.IMUX21 | PS.SAXIACPARADDR13 |
| TCELL35:IMUX.IMUX22 | PS.SAXIACPARADDR14 |
| TCELL35:IMUX.IMUX23 | PS.SAXIACPARADDR15 |
| TCELL35:IMUX.IMUX24 | PS.SAXIACPARPROT2 |
| TCELL35:IMUX.IMUX25 | PS.SAXIACPARVALID |
| TCELL35:IMUX.IMUX26 | PS.SAXIACPRREADY |
| TCELL35:OUT0.TMIN | PS.SAXIACPARESETN |
| TCELL35:OUT1.TMIN | PS.SAXIACPWREADY |
| TCELL35:OUT2.TMIN | PS.SAXIACPARREADY |
| TCELL35:OUT3.TMIN | PS.SAXIACPRID2 |
| TCELL35:OUT4.TMIN | PS.SAXIACPRDATA12 |
| TCELL35:OUT5.TMIN | PS.SAXIACPRDATA13 |
| TCELL35:OUT6.TMIN | PS.SAXIACPRDATA14 |
| TCELL35:OUT7.TMIN | PS.SAXIACPRDATA15 |
| TCELL35:OUT8.TMIN | PS.SAXIACPRDATA44 |
| TCELL35:OUT9.TMIN | PS.SAXIACPRDATA45 |
| TCELL35:OUT10.TMIN | PS.SAXIACPRDATA46 |
| TCELL35:OUT11.TMIN | PS.SAXIACPRDATA47 |
| TCELL35:OUT12.TMIN | PS.SAXIACPRVALID |
| TCELL35:OUT20.TMIN | PS.DEBUGDATA143 |
| TCELL35:OUT21.TMIN | PS.DEBUGDATA142 |
| TCELL35:OUT22.TMIN | PS.DEBUGDATA141 |
| TCELL35:OUT23.TMIN | PS.DEBUGDATA140 |
| TCELL36:IMUX.CLK0 | PS.DMA0ACLK |
| TCELL36:IMUX.IMUX0 | PS.DMA0DAREADY |
| TCELL36:IMUX.IMUX1 | PS.DMA0DRLAST |
| TCELL36:IMUX.IMUX2 | PS.SAXIACPAWADDR16 |
| TCELL36:IMUX.IMUX3 | PS.SAXIACPAWADDR17 |
| TCELL36:IMUX.IMUX4 | PS.SAXIACPAWADDR18 |
| TCELL36:IMUX.IMUX5 | PS.SAXIACPAWADDR19 |
| TCELL36:IMUX.IMUX6 | PS.SAXIACPAWVALID |
| TCELL36:IMUX.IMUX7 | PS.SAXIACPAWUSER1 |
| TCELL36:IMUX.IMUX8 | PS.SAXIACPAWUSER2 |
| TCELL36:IMUX.IMUX9 | PS.SAXIACPAWUSER3 |
| TCELL36:IMUX.IMUX10 | PS.SAXIACPAWUSER4 |
| TCELL36:IMUX.IMUX11 | PS.SAXIACPWID0 |
| TCELL36:IMUX.IMUX12 | PS.SAXIACPWID1 |
| TCELL36:IMUX.IMUX13 | PS.SAXIACPWID2 |
| TCELL36:IMUX.IMUX14 | PS.SAXIACPWDATA16 |
| TCELL36:IMUX.IMUX15 | PS.SAXIACPWDATA17 |
| TCELL36:IMUX.IMUX16 | PS.SAXIACPWDATA18 |
| TCELL36:IMUX.IMUX17 | PS.SAXIACPWDATA19 |
| TCELL36:IMUX.IMUX18 | PS.SAXIACPWDATA48 |
| TCELL36:IMUX.IMUX19 | PS.SAXIACPWDATA49 |
| TCELL36:IMUX.IMUX20 | PS.SAXIACPWDATA50 |
| TCELL36:IMUX.IMUX21 | PS.SAXIACPWDATA51 |
| TCELL36:IMUX.IMUX22 | PS.SAXIACPBREADY |
| TCELL36:IMUX.IMUX23 | PS.SAXIACPARADDR16 |
| TCELL36:IMUX.IMUX24 | PS.SAXIACPARADDR17 |
| TCELL36:IMUX.IMUX25 | PS.SAXIACPARADDR18 |
| TCELL36:IMUX.IMUX26 | PS.SAXIACPARADDR19 |
| TCELL36:IMUX.IMUX44 | PS.DEBUGSELECT3 |
| TCELL36:IMUX.IMUX45 | PS.DEBUGSELECT2 |
| TCELL36:IMUX.IMUX46 | PS.DEBUGSELECT1 |
| TCELL36:IMUX.IMUX47 | PS.DEBUGSELECT0 |
| TCELL36:OUT0.TMIN | PS.DMA0RSTN |
| TCELL36:OUT1.TMIN | PS.SAXIACPAWREADY |
| TCELL36:OUT2.TMIN | PS.SAXIACPBVALID |
| TCELL36:OUT3.TMIN | PS.SAXIACPRDATA16 |
| TCELL36:OUT4.TMIN | PS.SAXIACPRDATA17 |
| TCELL36:OUT5.TMIN | PS.SAXIACPRDATA18 |
| TCELL36:OUT6.TMIN | PS.SAXIACPRDATA19 |
| TCELL36:OUT7.TMIN | PS.SAXIACPRDATA48 |
| TCELL36:OUT8.TMIN | PS.SAXIACPRDATA49 |
| TCELL36:OUT9.TMIN | PS.SAXIACPRDATA50 |
| TCELL36:OUT10.TMIN | PS.SAXIACPRDATA51 |
| TCELL36:OUT20.TMIN | PS.DEBUGDATA147 |
| TCELL36:OUT21.TMIN | PS.DEBUGDATA146 |
| TCELL36:OUT22.TMIN | PS.DEBUGDATA145 |
| TCELL36:OUT23.TMIN | PS.DEBUGDATA144 |
| TCELL37:IMUX.CLK0 | PS.DMA1ACLK |
| TCELL37:IMUX.IMUX0 | PS.DMA1DAREADY |
| TCELL37:IMUX.IMUX1 | PS.DMA1DRLAST |
| TCELL37:IMUX.IMUX2 | PS.SAXIACPAWADDR20 |
| TCELL37:IMUX.IMUX3 | PS.SAXIACPAWADDR21 |
| TCELL37:IMUX.IMUX4 | PS.SAXIACPAWADDR22 |
| TCELL37:IMUX.IMUX5 | PS.SAXIACPAWADDR23 |
| TCELL37:IMUX.IMUX6 | PS.SAXIACPAWLOCK0 |
| TCELL37:IMUX.IMUX7 | PS.SAXIACPAWLOCK1 |
| TCELL37:IMUX.IMUX8 | PS.SAXIACPAWCACHE0 |
| TCELL37:IMUX.IMUX9 | PS.SAXIACPAWCACHE1 |
| TCELL37:IMUX.IMUX10 | PS.SAXIACPAWCACHE2 |
| TCELL37:IMUX.IMUX11 | PS.SAXIACPAWCACHE3 |
| TCELL37:IMUX.IMUX12 | PS.SAXIACPAWPROT0 |
| TCELL37:IMUX.IMUX13 | PS.SAXIACPAWPROT1 |
| TCELL37:IMUX.IMUX14 | PS.SAXIACPAWPROT2 |
| TCELL37:IMUX.IMUX15 | PS.SAXIACPWDATA20 |
| TCELL37:IMUX.IMUX16 | PS.SAXIACPWDATA21 |
| TCELL37:IMUX.IMUX17 | PS.SAXIACPWDATA22 |
| TCELL37:IMUX.IMUX18 | PS.SAXIACPWDATA23 |
| TCELL37:IMUX.IMUX19 | PS.SAXIACPWDATA52 |
| TCELL37:IMUX.IMUX20 | PS.SAXIACPWDATA53 |
| TCELL37:IMUX.IMUX21 | PS.SAXIACPWDATA54 |
| TCELL37:IMUX.IMUX22 | PS.SAXIACPWDATA55 |
| TCELL37:IMUX.IMUX23 | PS.SAXIACPARADDR20 |
| TCELL37:IMUX.IMUX24 | PS.SAXIACPARADDR21 |
| TCELL37:IMUX.IMUX25 | PS.SAXIACPARADDR22 |
| TCELL37:IMUX.IMUX26 | PS.SAXIACPARADDR23 |
| TCELL37:IMUX.IMUX44 | PS.DEBUGSELECT7 |
| TCELL37:IMUX.IMUX45 | PS.DEBUGSELECT6 |
| TCELL37:IMUX.IMUX46 | PS.DEBUGSELECT5 |
| TCELL37:IMUX.IMUX47 | PS.DEBUGSELECT4 |
| TCELL37:OUT0.TMIN | PS.DMA1RSTN |
| TCELL37:OUT1.TMIN | PS.SAXIACPBRESP0 |
| TCELL37:OUT2.TMIN | PS.SAXIACPBRESP1 |
| TCELL37:OUT3.TMIN | PS.SAXIACPRDATA20 |
| TCELL37:OUT4.TMIN | PS.SAXIACPRDATA21 |
| TCELL37:OUT5.TMIN | PS.SAXIACPRDATA22 |
| TCELL37:OUT6.TMIN | PS.SAXIACPRDATA23 |
| TCELL37:OUT7.TMIN | PS.SAXIACPRDATA52 |
| TCELL37:OUT8.TMIN | PS.SAXIACPRDATA53 |
| TCELL37:OUT9.TMIN | PS.SAXIACPRDATA54 |
| TCELL37:OUT10.TMIN | PS.SAXIACPRDATA55 |
| TCELL37:OUT20.TMIN | PS.DEBUGDATA151 |
| TCELL37:OUT21.TMIN | PS.DEBUGDATA150 |
| TCELL37:OUT22.TMIN | PS.DEBUGDATA149 |
| TCELL37:OUT23.TMIN | PS.DEBUGDATA148 |
| TCELL38:IMUX.CLK0 | PS.DMA2ACLK |
| TCELL38:IMUX.IMUX0 | PS.DMA2DAREADY |
| TCELL38:IMUX.IMUX1 | PS.DMA2DRLAST |
| TCELL38:IMUX.IMUX2 | PS.SAXIACPAWADDR24 |
| TCELL38:IMUX.IMUX3 | PS.SAXIACPAWADDR25 |
| TCELL38:IMUX.IMUX4 | PS.SAXIACPAWADDR26 |
| TCELL38:IMUX.IMUX5 | PS.SAXIACPAWADDR27 |
| TCELL38:IMUX.IMUX6 | PS.SAXIACPAWLEN0 |
| TCELL38:IMUX.IMUX7 | PS.SAXIACPAWLEN1 |
| TCELL38:IMUX.IMUX8 | PS.SAXIACPAWLEN2 |
| TCELL38:IMUX.IMUX9 | PS.SAXIACPAWLEN3 |
| TCELL38:IMUX.IMUX10 | PS.SAXIACPAWSIZE0 |
| TCELL38:IMUX.IMUX11 | PS.SAXIACPAWSIZE1 |
| TCELL38:IMUX.IMUX12 | PS.SAXIACPAWBURST0 |
| TCELL38:IMUX.IMUX13 | PS.SAXIACPAWBURST1 |
| TCELL38:IMUX.IMUX14 | PS.SAXIACPWDATA24 |
| TCELL38:IMUX.IMUX15 | PS.SAXIACPWDATA25 |
| TCELL38:IMUX.IMUX16 | PS.SAXIACPWDATA26 |
| TCELL38:IMUX.IMUX17 | PS.SAXIACPWDATA27 |
| TCELL38:IMUX.IMUX18 | PS.SAXIACPWDATA56 |
| TCELL38:IMUX.IMUX19 | PS.SAXIACPWDATA57 |
| TCELL38:IMUX.IMUX20 | PS.SAXIACPWDATA58 |
| TCELL38:IMUX.IMUX21 | PS.SAXIACPWDATA59 |
| TCELL38:IMUX.IMUX22 | PS.SAXIACPARADDR24 |
| TCELL38:IMUX.IMUX23 | PS.SAXIACPARADDR25 |
| TCELL38:IMUX.IMUX24 | PS.SAXIACPARADDR26 |
| TCELL38:IMUX.IMUX25 | PS.SAXIACPARADDR27 |
| TCELL38:IMUX.IMUX44 | PS.DEBUGSELECT11 |
| TCELL38:IMUX.IMUX45 | PS.DEBUGSELECT10 |
| TCELL38:IMUX.IMUX46 | PS.DEBUGSELECT9 |
| TCELL38:IMUX.IMUX47 | PS.DEBUGSELECT8 |
| TCELL38:OUT0.TMIN | PS.DMA2RSTN |
| TCELL38:OUT1.TMIN | PS.SAXIACPRDATA24 |
| TCELL38:OUT2.TMIN | PS.SAXIACPRDATA25 |
| TCELL38:OUT3.TMIN | PS.SAXIACPRDATA26 |
| TCELL38:OUT4.TMIN | PS.SAXIACPRDATA27 |
| TCELL38:OUT5.TMIN | PS.SAXIACPRDATA56 |
| TCELL38:OUT6.TMIN | PS.SAXIACPRDATA57 |
| TCELL38:OUT7.TMIN | PS.SAXIACPRDATA58 |
| TCELL38:OUT8.TMIN | PS.SAXIACPRDATA59 |
| TCELL38:OUT9.TMIN | PS.SAXIACPRRESP0 |
| TCELL38:OUT10.TMIN | PS.SAXIACPRRESP1 |
| TCELL38:OUT11.TMIN | PS.SAXIACPRLAST |
| TCELL38:OUT20.TMIN | PS.DEBUGDATA155 |
| TCELL38:OUT21.TMIN | PS.DEBUGDATA154 |
| TCELL38:OUT22.TMIN | PS.DEBUGDATA153 |
| TCELL38:OUT23.TMIN | PS.DEBUGDATA152 |
| TCELL39:IMUX.CLK0 | PS.DMA3ACLK |
| TCELL39:IMUX.IMUX0 | PS.DMA3DAREADY |
| TCELL39:IMUX.IMUX1 | PS.DMA3DRLAST |
| TCELL39:IMUX.IMUX2 | PS.SAXIACPAWID0 |
| TCELL39:IMUX.IMUX3 | PS.SAXIACPAWID1 |
| TCELL39:IMUX.IMUX4 | PS.SAXIACPAWID2 |
| TCELL39:IMUX.IMUX5 | PS.SAXIACPAWADDR28 |
| TCELL39:IMUX.IMUX6 | PS.SAXIACPAWADDR29 |
| TCELL39:IMUX.IMUX7 | PS.SAXIACPAWADDR30 |
| TCELL39:IMUX.IMUX8 | PS.SAXIACPAWADDR31 |
| TCELL39:IMUX.IMUX9 | PS.SAXIACPWDATA28 |
| TCELL39:IMUX.IMUX10 | PS.SAXIACPWDATA29 |
| TCELL39:IMUX.IMUX11 | PS.SAXIACPWDATA30 |
| TCELL39:IMUX.IMUX12 | PS.SAXIACPWDATA31 |
| TCELL39:IMUX.IMUX13 | PS.SAXIACPWDATA60 |
| TCELL39:IMUX.IMUX14 | PS.SAXIACPWDATA61 |
| TCELL39:IMUX.IMUX15 | PS.SAXIACPWDATA62 |
| TCELL39:IMUX.IMUX16 | PS.SAXIACPWDATA63 |
| TCELL39:IMUX.IMUX17 | PS.SAXIACPARADDR28 |
| TCELL39:IMUX.IMUX18 | PS.SAXIACPARADDR29 |
| TCELL39:IMUX.IMUX19 | PS.SAXIACPARADDR30 |
| TCELL39:IMUX.IMUX20 | PS.SAXIACPARADDR31 |
| TCELL39:IMUX.IMUX21 | PS.SAXIACPAWQOS0 |
| TCELL39:IMUX.IMUX22 | PS.SAXIACPAWQOS1 |
| TCELL39:IMUX.IMUX23 | PS.SAXIACPAWQOS2 |
| TCELL39:IMUX.IMUX24 | PS.SAXIACPAWQOS3 |
| TCELL39:IMUX.IMUX44 | PS.DEBUGSELECT15 |
| TCELL39:IMUX.IMUX45 | PS.DEBUGSELECT14 |
| TCELL39:IMUX.IMUX46 | PS.DEBUGSELECT13 |
| TCELL39:IMUX.IMUX47 | PS.DEBUGSELECT12 |
| TCELL39:OUT0.TMIN | PS.DMA3RSTN |
| TCELL39:OUT1.TMIN | PS.FCLKCLK0_INT |
| TCELL39:OUT2.TMIN | PS.FCLKCLK1_INT |
| TCELL39:OUT3.TMIN | PS.FCLKRESETN0 |
| TCELL39:OUT4.TMIN | PS.FCLKRESETN1 |
| TCELL39:OUT5.TMIN | PS.SAXIACPRDATA28 |
| TCELL39:OUT6.TMIN | PS.SAXIACPRDATA29 |
| TCELL39:OUT7.TMIN | PS.SAXIACPRDATA30 |
| TCELL39:OUT8.TMIN | PS.SAXIACPRDATA31 |
| TCELL39:OUT9.TMIN | PS.SAXIACPRDATA60 |
| TCELL39:OUT10.TMIN | PS.SAXIACPRDATA61 |
| TCELL39:OUT11.TMIN | PS.SAXIACPRDATA62 |
| TCELL39:OUT12.TMIN | PS.SAXIACPRDATA63 |
| TCELL39:OUT20.TMIN | PS.DEBUGDATA159 |
| TCELL39:OUT21.TMIN | PS.DEBUGDATA158 |
| TCELL39:OUT22.TMIN | PS.DEBUGDATA157 |
| TCELL39:OUT23.TMIN | PS.DEBUGDATA156 |
| TCELL40:IMUX.IMUX0 | PS.DMA0DRTYPE0 |
| TCELL40:IMUX.IMUX1 | PS.DMA0DRTYPE1 |
| TCELL40:IMUX.IMUX2 | PS.DMA0DRVALID |
| TCELL40:IMUX.IMUX3 | PS.FCLKCLKTRIGN0 |
| TCELL40:IMUX.IMUX4 | PS.FCLKCLKTRIGN1 |
| TCELL40:IMUX.IMUX5 | PS.MAXIGP0RDATA0 |
| TCELL40:IMUX.IMUX6 | PS.MAXIGP0RDATA1 |
| TCELL40:IMUX.IMUX7 | PS.MAXIGP0RDATA2 |
| TCELL40:IMUX.IMUX8 | PS.MAXIGP0RDATA3 |
| TCELL40:OUT0.TMIN | PS.DMA0DRREADY |
| TCELL40:OUT1.TMIN | PS.MAXIGP0ARID0 |
| TCELL40:OUT2.TMIN | PS.MAXIGP0ARID1 |
| TCELL40:OUT3.TMIN | PS.MAXIGP0ARID2 |
| TCELL40:OUT4.TMIN | PS.MAXIGP0ARID3 |
| TCELL40:OUT5.TMIN | PS.MAXIGP0ARADDR0 |
| TCELL40:OUT6.TMIN | PS.MAXIGP0ARADDR1 |
| TCELL40:OUT7.TMIN | PS.MAXIGP0ARADDR2 |
| TCELL40:OUT8.TMIN | PS.MAXIGP0ARADDR3 |
| TCELL40:OUT9.TMIN | PS.MAXIGP0ARLEN0 |
| TCELL40:OUT10.TMIN | PS.MAXIGP0ARLEN1 |
| TCELL40:OUT11.TMIN | PS.MAXIGP0ARLEN2 |
| TCELL40:OUT12.TMIN | PS.MAXIGP0ARSIZE0 |
| TCELL40:OUT13.TMIN | PS.MAXIGP0ARSIZE1 |
| TCELL40:OUT14.TMIN | PS.MAXIGP0ARBURST0 |
| TCELL40:OUT15.TMIN | PS.MAXIGP0ARBURST1 |
| TCELL40:OUT16.TMIN | PS.MAXIGP0ARLOCK0 |
| TCELL40:OUT17.TMIN | PS.MAXIGP0ARLOCK1 |
| TCELL40:OUT18.TMIN | PS.MAXIGP0ARQOS0 |
| TCELL40:OUT19.TMIN | PS.MAXIGP0ARQOS1 |
| TCELL40:OUT20.TMIN | PS.DEBUGDATA163 |
| TCELL40:OUT21.TMIN | PS.DEBUGDATA162 |
| TCELL40:OUT22.TMIN | PS.DEBUGDATA161 |
| TCELL40:OUT23.TMIN | PS.DEBUGDATA160 |
| TCELL41:IMUX.IMUX0 | PS.DMA1DRTYPE0 |
| TCELL41:IMUX.IMUX1 | PS.DMA1DRTYPE1 |
| TCELL41:IMUX.IMUX2 | PS.DMA1DRVALID |
| TCELL41:IMUX.IMUX3 | PS.MAXIGP0RDATA4 |
| TCELL41:IMUX.IMUX4 | PS.MAXIGP0RDATA5 |
| TCELL41:IMUX.IMUX5 | PS.MAXIGP0RDATA6 |
| TCELL41:IMUX.IMUX6 | PS.MAXIGP0RDATA7 |
| TCELL41:IMUX.IMUX44 | PS.TESTSCANMODEATSPEEDOPCGN3 |
| TCELL41:IMUX.IMUX45 | PS.TESTSCANMODEATSPEEDOPCGN2 |
| TCELL41:IMUX.IMUX46 | PS.TESTSCANMODEATSPEEDOPCGN1 |
| TCELL41:IMUX.IMUX47 | PS.TESTSCANMODEATSPEEDOPCGN0 |
| TCELL41:OUT0.TMIN | PS.DMA1DRREADY |
| TCELL41:OUT1.TMIN | PS.MAXIGP0AWADDR0 |
| TCELL41:OUT2.TMIN | PS.MAXIGP0AWADDR1 |
| TCELL41:OUT3.TMIN | PS.MAXIGP0ARID4 |
| TCELL41:OUT4.TMIN | PS.MAXIGP0ARID5 |
| TCELL41:OUT5.TMIN | PS.MAXIGP0ARID6 |
| TCELL41:OUT6.TMIN | PS.MAXIGP0ARADDR4 |
| TCELL41:OUT7.TMIN | PS.MAXIGP0ARADDR5 |
| TCELL41:OUT8.TMIN | PS.MAXIGP0ARADDR6 |
| TCELL41:OUT9.TMIN | PS.MAXIGP0ARADDR7 |
| TCELL41:OUT10.TMIN | PS.MAXIGP0ARLEN3 |
| TCELL41:OUT11.TMIN | PS.MAXIGP0ARCACHE0 |
| TCELL41:OUT12.TMIN | PS.MAXIGP0ARCACHE1 |
| TCELL41:OUT13.TMIN | PS.MAXIGP0ARCACHE2 |
| TCELL41:OUT14.TMIN | PS.MAXIGP0ARCACHE3 |
| TCELL41:OUT15.TMIN | PS.MAXIGP0ARPROT0 |
| TCELL41:OUT16.TMIN | PS.MAXIGP0ARQOS2 |
| TCELL41:OUT17.TMIN | PS.MAXIGP0ARQOS3 |
| TCELL41:OUT20.TMIN | PS.DEBUGDATA167 |
| TCELL41:OUT21.TMIN | PS.DEBUGDATA166 |
| TCELL41:OUT22.TMIN | PS.DEBUGDATA165 |
| TCELL41:OUT23.TMIN | PS.DEBUGDATA164 |
| TCELL42:IMUX.IMUX0 | PS.DMA2DRTYPE0 |
| TCELL42:IMUX.IMUX1 | PS.DMA2DRTYPE1 |
| TCELL42:IMUX.IMUX2 | PS.DMA2DRVALID |
| TCELL42:IMUX.IMUX3 | PS.MAXIGP0RDATA8 |
| TCELL42:IMUX.IMUX4 | PS.MAXIGP0RDATA9 |
| TCELL42:IMUX.IMUX5 | PS.MAXIGP0RDATA10 |
| TCELL42:IMUX.IMUX6 | PS.MAXIGP0RDATA11 |
| TCELL42:IMUX.IMUX44 | PS.TESTSCANMODEATSPEEDOPCGN7 |
| TCELL42:IMUX.IMUX45 | PS.TESTSCANMODEATSPEEDOPCGN6 |
| TCELL42:IMUX.IMUX46 | PS.TESTSCANMODEATSPEEDOPCGN5 |
| TCELL42:IMUX.IMUX47 | PS.TESTSCANMODEATSPEEDOPCGN4 |
| TCELL42:OUT0.TMIN | PS.DMA2DRREADY |
| TCELL42:OUT1.TMIN | PS.MAXIGP0AWADDR2 |
| TCELL42:OUT2.TMIN | PS.MAXIGP0AWADDR3 |
| TCELL42:OUT3.TMIN | PS.MAXIGP0AWLEN0 |
| TCELL42:OUT4.TMIN | PS.MAXIGP0WDATA0 |
| TCELL42:OUT5.TMIN | PS.MAXIGP0WDATA1 |
| TCELL42:OUT6.TMIN | PS.MAXIGP0WDATA2 |
| TCELL42:OUT7.TMIN | PS.MAXIGP0WDATA3 |
| TCELL42:OUT8.TMIN | PS.MAXIGP0ARID7 |
| TCELL42:OUT9.TMIN | PS.MAXIGP0ARID8 |
| TCELL42:OUT10.TMIN | PS.MAXIGP0ARID9 |
| TCELL42:OUT11.TMIN | PS.MAXIGP0ARID10 |
| TCELL42:OUT12.TMIN | PS.MAXIGP0ARADDR8 |
| TCELL42:OUT13.TMIN | PS.MAXIGP0ARADDR9 |
| TCELL42:OUT14.TMIN | PS.MAXIGP0ARADDR10 |
| TCELL42:OUT15.TMIN | PS.MAXIGP0ARADDR11 |
| TCELL42:OUT16.TMIN | PS.MAXIGP0ARPROT1 |
| TCELL42:OUT17.TMIN | PS.MAXIGP0ARPROT2 |
| TCELL42:OUT20.TMIN | PS.DEBUGDATA171 |
| TCELL42:OUT21.TMIN | PS.DEBUGDATA170 |
| TCELL42:OUT22.TMIN | PS.DEBUGDATA169 |
| TCELL42:OUT23.TMIN | PS.DEBUGDATA168 |
| TCELL43:IMUX.IMUX0 | PS.DMA3DRTYPE0 |
| TCELL43:IMUX.IMUX1 | PS.DMA3DRTYPE1 |
| TCELL43:IMUX.IMUX2 | PS.DMA3DRVALID |
| TCELL43:IMUX.IMUX3 | PS.MAXIGP0RDATA12 |
| TCELL43:IMUX.IMUX4 | PS.MAXIGP0RDATA13 |
| TCELL43:IMUX.IMUX5 | PS.MAXIGP0RDATA14 |
| TCELL43:IMUX.IMUX6 | PS.MAXIGP0RDATA15 |
| TCELL43:IMUX.IMUX7 | PS.MAXIGP0RLAST |
| TCELL43:IMUX.IMUX44 | PS.TESTSCANMODEATSPEEDOPCGN11 |
| TCELL43:IMUX.IMUX45 | PS.TESTSCANMODEATSPEEDOPCGN10 |
| TCELL43:IMUX.IMUX46 | PS.TESTSCANMODEATSPEEDOPCGN9 |
| TCELL43:IMUX.IMUX47 | PS.TESTSCANMODEATSPEEDOPCGN8 |
| TCELL43:OUT0.TMIN | PS.DMA3DRREADY |
| TCELL43:OUT1.TMIN | PS.MAXIGP0AWADDR4 |
| TCELL43:OUT2.TMIN | PS.MAXIGP0AWADDR5 |
| TCELL43:OUT3.TMIN | PS.MAXIGP0AWADDR6 |
| TCELL43:OUT4.TMIN | PS.MAXIGP0AWADDR7 |
| TCELL43:OUT5.TMIN | PS.MAXIGP0AWLEN1 |
| TCELL43:OUT6.TMIN | PS.MAXIGP0AWLEN2 |
| TCELL43:OUT7.TMIN | PS.MAXIGP0AWLEN3 |
| TCELL43:OUT8.TMIN | PS.MAXIGP0AWCACHE0 |
| TCELL43:OUT9.TMIN | PS.MAXIGP0AWCACHE1 |
| TCELL43:OUT10.TMIN | PS.MAXIGP0WDATA4 |
| TCELL43:OUT11.TMIN | PS.MAXIGP0WDATA5 |
| TCELL43:OUT12.TMIN | PS.MAXIGP0WDATA6 |
| TCELL43:OUT13.TMIN | PS.MAXIGP0WDATA7 |
| TCELL43:OUT14.TMIN | PS.MAXIGP0ARID11 |
| TCELL43:OUT15.TMIN | PS.MAXIGP0ARADDR12 |
| TCELL43:OUT16.TMIN | PS.MAXIGP0ARADDR13 |
| TCELL43:OUT17.TMIN | PS.MAXIGP0ARADDR14 |
| TCELL43:OUT18.TMIN | PS.MAXIGP0ARADDR15 |
| TCELL43:OUT20.TMIN | PS.DEBUGDATA175 |
| TCELL43:OUT21.TMIN | PS.DEBUGDATA174 |
| TCELL43:OUT22.TMIN | PS.DEBUGDATA173 |
| TCELL43:OUT23.TMIN | PS.DEBUGDATA172 |
| TCELL44:IMUX.IMUX0 | PS.MAXIGP0RID0 |
| TCELL44:IMUX.IMUX1 | PS.MAXIGP0RID1 |
| TCELL44:IMUX.IMUX2 | PS.MAXIGP0RDATA16 |
| TCELL44:IMUX.IMUX3 | PS.MAXIGP0RDATA17 |
| TCELL44:IMUX.IMUX4 | PS.MAXIGP0RDATA18 |
| TCELL44:IMUX.IMUX5 | PS.MAXIGP0RDATA19 |
| TCELL44:IMUX.IMUX6 | PS.MAXIGP0RRESP0 |
| TCELL44:IMUX.IMUX7 | PS.MAXIGP0RRESP1 |
| TCELL44:IMUX.IMUX8 | PS.MAXIGP0RVALID |
| TCELL44:IMUX.IMUX44 | PS.TESTSCANMODEATSPEEDOPCGN15 |
| TCELL44:IMUX.IMUX45 | PS.TESTSCANMODEATSPEEDOPCGN14 |
| TCELL44:IMUX.IMUX46 | PS.TESTSCANMODEATSPEEDOPCGN13 |
| TCELL44:IMUX.IMUX47 | PS.TESTSCANMODEATSPEEDOPCGN12 |
| TCELL44:OUT0.TMIN | PS.MAXIGP0ARESETN |
| TCELL44:OUT1.TMIN | PS.MAXIGP0AWADDR8 |
| TCELL44:OUT2.TMIN | PS.MAXIGP0AWADDR9 |
| TCELL44:OUT3.TMIN | PS.MAXIGP0AWADDR10 |
| TCELL44:OUT4.TMIN | PS.MAXIGP0AWADDR11 |
| TCELL44:OUT5.TMIN | PS.MAXIGP0AWCACHE2 |
| TCELL44:OUT6.TMIN | PS.MAXIGP0AWCACHE3 |
| TCELL44:OUT7.TMIN | PS.MAXIGP0AWPROT0 |
| TCELL44:OUT8.TMIN | PS.MAXIGP0AWPROT1 |
| TCELL44:OUT9.TMIN | PS.MAXIGP0WID0 |
| TCELL44:OUT10.TMIN | PS.MAXIGP0WDATA8 |
| TCELL44:OUT11.TMIN | PS.MAXIGP0WDATA9 |
| TCELL44:OUT12.TMIN | PS.MAXIGP0WDATA10 |
| TCELL44:OUT13.TMIN | PS.MAXIGP0WDATA11 |
| TCELL44:OUT14.TMIN | PS.MAXIGP0ARADDR16 |
| TCELL44:OUT15.TMIN | PS.MAXIGP0ARADDR17 |
| TCELL44:OUT16.TMIN | PS.MAXIGP0ARADDR18 |
| TCELL44:OUT17.TMIN | PS.MAXIGP0ARADDR19 |
| TCELL44:OUT18.TMIN | PS.MAXIGP0RREADY |
| TCELL44:OUT20.TMIN | PS.DEBUGDATA179 |
| TCELL44:OUT21.TMIN | PS.DEBUGDATA178 |
| TCELL44:OUT22.TMIN | PS.DEBUGDATA177 |
| TCELL44:OUT23.TMIN | PS.DEBUGDATA176 |
| TCELL45:IMUX.CLK0 | PS.MAXIGP0ACLK |
| TCELL45:IMUX.IMUX0 | PS.IRQF2P0 |
| TCELL45:IMUX.IMUX1 | PS.IRQF2P1 |
| TCELL45:IMUX.IMUX2 | PS.MAXIGP0AWREADY |
| TCELL45:IMUX.IMUX3 | PS.MAXIGP0WREADY |
| TCELL45:IMUX.IMUX4 | PS.MAXIGP0ARREADY |
| TCELL45:IMUX.IMUX5 | PS.MAXIGP0RDATA20 |
| TCELL45:IMUX.IMUX6 | PS.MAXIGP0RDATA21 |
| TCELL45:IMUX.IMUX7 | PS.MAXIGP0RDATA22 |
| TCELL45:IMUX.IMUX8 | PS.MAXIGP0RDATA23 |
| TCELL45:IMUX.IMUX44 | PS.TESTSCANMODEATSPEEDOPCGN19 |
| TCELL45:IMUX.IMUX45 | PS.TESTSCANMODEATSPEEDOPCGN18 |
| TCELL45:IMUX.IMUX46 | PS.TESTSCANMODEATSPEEDOPCGN17 |
| TCELL45:IMUX.IMUX47 | PS.TESTSCANMODEATSPEEDOPCGN16 |
| TCELL45:OUT0.TMIN | PS.MAXIGP0AWADDR12 |
| TCELL45:OUT1.TMIN | PS.MAXIGP0AWADDR13 |
| TCELL45:OUT2.TMIN | PS.MAXIGP0AWADDR14 |
| TCELL45:OUT3.TMIN | PS.MAXIGP0AWADDR15 |
| TCELL45:OUT4.TMIN | PS.MAXIGP0AWPROT2 |
| TCELL45:OUT5.TMIN | PS.MAXIGP0AWVALID |
| TCELL45:OUT6.TMIN | PS.MAXIGP0WID1 |
| TCELL45:OUT7.TMIN | PS.MAXIGP0WID2 |
| TCELL45:OUT8.TMIN | PS.MAXIGP0WDATA12 |
| TCELL45:OUT9.TMIN | PS.MAXIGP0WDATA13 |
| TCELL45:OUT10.TMIN | PS.MAXIGP0WDATA14 |
| TCELL45:OUT11.TMIN | PS.MAXIGP0WDATA15 |
| TCELL45:OUT12.TMIN | PS.MAXIGP0WVALID |
| TCELL45:OUT13.TMIN | PS.MAXIGP0BREADY |
| TCELL45:OUT14.TMIN | PS.MAXIGP0ARADDR20 |
| TCELL45:OUT15.TMIN | PS.MAXIGP0ARADDR21 |
| TCELL45:OUT16.TMIN | PS.MAXIGP0ARADDR22 |
| TCELL45:OUT17.TMIN | PS.MAXIGP0ARADDR23 |
| TCELL45:OUT18.TMIN | PS.MAXIGP0ARVALID |
| TCELL45:OUT20.TMIN | PS.DEBUGDATA183 |
| TCELL45:OUT21.TMIN | PS.DEBUGDATA182 |
| TCELL45:OUT22.TMIN | PS.DEBUGDATA181 |
| TCELL45:OUT23.TMIN | PS.DEBUGDATA180 |
| TCELL46:IMUX.IMUX0 | PS.IRQF2P2 |
| TCELL46:IMUX.IMUX1 | PS.IRQF2P3 |
| TCELL46:IMUX.IMUX2 | PS.MAXIGP0BVALID |
| TCELL46:IMUX.IMUX3 | PS.MAXIGP0RID2 |
| TCELL46:IMUX.IMUX4 | PS.MAXIGP0RID3 |
| TCELL46:IMUX.IMUX5 | PS.MAXIGP0RDATA24 |
| TCELL46:IMUX.IMUX6 | PS.MAXIGP0RDATA25 |
| TCELL46:IMUX.IMUX7 | PS.MAXIGP0RDATA26 |
| TCELL46:IMUX.IMUX8 | PS.MAXIGP0RDATA27 |
| TCELL46:IMUX.IMUX44 | PS.TESTSCANMODEATSPEEDOPCGN23 |
| TCELL46:IMUX.IMUX45 | PS.TESTSCANMODEATSPEEDOPCGN22 |
| TCELL46:IMUX.IMUX46 | PS.TESTSCANMODEATSPEEDOPCGN21 |
| TCELL46:IMUX.IMUX47 | PS.TESTSCANMODEATSPEEDOPCGN20 |
| TCELL46:OUT0.TMIN | PS.MAXIGP0AWID0 |
| TCELL46:OUT1.TMIN | PS.MAXIGP0AWADDR16 |
| TCELL46:OUT2.TMIN | PS.MAXIGP0AWADDR17 |
| TCELL46:OUT3.TMIN | PS.MAXIGP0AWADDR18 |
| TCELL46:OUT4.TMIN | PS.MAXIGP0AWADDR19 |
| TCELL46:OUT5.TMIN | PS.MAXIGP0WID3 |
| TCELL46:OUT6.TMIN | PS.MAXIGP0WID4 |
| TCELL46:OUT7.TMIN | PS.MAXIGP0WDATA16 |
| TCELL46:OUT8.TMIN | PS.MAXIGP0WDATA17 |
| TCELL46:OUT9.TMIN | PS.MAXIGP0WDATA18 |
| TCELL46:OUT10.TMIN | PS.MAXIGP0WDATA19 |
| TCELL46:OUT11.TMIN | PS.MAXIGP0ARADDR24 |
| TCELL46:OUT12.TMIN | PS.MAXIGP0ARADDR25 |
| TCELL46:OUT13.TMIN | PS.MAXIGP0ARADDR26 |
| TCELL46:OUT14.TMIN | PS.MAXIGP0ARADDR27 |
| TCELL46:OUT15.TMIN | PS.MAXIGP0AWQOS0 |
| TCELL46:OUT16.TMIN | PS.MAXIGP0AWQOS1 |
| TCELL46:OUT17.TMIN | PS.MAXIGP0AWQOS2 |
| TCELL46:OUT18.TMIN | PS.MAXIGP0AWQOS3 |
| TCELL46:OUT20.TMIN | PS.DEBUGDATA187 |
| TCELL46:OUT21.TMIN | PS.DEBUGDATA186 |
| TCELL46:OUT22.TMIN | PS.DEBUGDATA185 |
| TCELL46:OUT23.TMIN | PS.DEBUGDATA184 |
| TCELL47:IMUX.IMUX0 | PS.IRQF2P4 |
| TCELL47:IMUX.IMUX1 | PS.IRQF2P5 |
| TCELL47:IMUX.IMUX2 | PS.MAXIGP0BID0 |
| TCELL47:IMUX.IMUX3 | PS.MAXIGP0BID1 |
| TCELL47:IMUX.IMUX4 | PS.MAXIGP0BID2 |
| TCELL47:IMUX.IMUX5 | PS.MAXIGP0BID3 |
| TCELL47:IMUX.IMUX6 | PS.MAXIGP0RID4 |
| TCELL47:IMUX.IMUX7 | PS.MAXIGP0RID5 |
| TCELL47:IMUX.IMUX8 | PS.MAXIGP0RDATA28 |
| TCELL47:IMUX.IMUX9 | PS.MAXIGP0RDATA29 |
| TCELL47:IMUX.IMUX10 | PS.MAXIGP0RDATA30 |
| TCELL47:IMUX.IMUX11 | PS.MAXIGP0RDATA31 |
| TCELL47:IMUX.IMUX46 | PS.TESTA9MBISTDATAIN |
| TCELL47:IMUX.IMUX47 | PS.TESTA9MBISTSHIFT |
| TCELL47:OUT0.TMIN | PS.MAXIGP0AWID1 |
| TCELL47:OUT1.TMIN | PS.MAXIGP0AWID2 |
| TCELL47:OUT2.TMIN | PS.MAXIGP0AWID3 |
| TCELL47:OUT3.TMIN | PS.MAXIGP0AWID4 |
| TCELL47:OUT4.TMIN | PS.MAXIGP0AWADDR20 |
| TCELL47:OUT5.TMIN | PS.MAXIGP0AWADDR21 |
| TCELL47:OUT6.TMIN | PS.MAXIGP0AWADDR22 |
| TCELL47:OUT7.TMIN | PS.MAXIGP0AWADDR23 |
| TCELL47:OUT8.TMIN | PS.MAXIGP0WID5 |
| TCELL47:OUT9.TMIN | PS.MAXIGP0WID6 |
| TCELL47:OUT10.TMIN | PS.MAXIGP0WID7 |
| TCELL47:OUT11.TMIN | PS.MAXIGP0WDATA20 |
| TCELL47:OUT12.TMIN | PS.MAXIGP0WDATA21 |
| TCELL47:OUT13.TMIN | PS.MAXIGP0WDATA22 |
| TCELL47:OUT14.TMIN | PS.MAXIGP0WDATA23 |
| TCELL47:OUT15.TMIN | PS.MAXIGP0WSTRB0 |
| TCELL47:OUT16.TMIN | PS.MAXIGP0WSTRB1 |
| TCELL47:OUT17.TMIN | PS.MAXIGP0ARADDR28 |
| TCELL47:OUT18.TMIN | PS.MAXIGP0ARADDR29 |
| TCELL47:OUT20.TMIN | PS.TESTA9MBISTRESULT1 |
| TCELL47:OUT21.TMIN | PS.TESTA9MBISTRESULT0 |
| TCELL47:OUT22.TMIN | PS.DEBUGDATA189 |
| TCELL47:OUT23.TMIN | PS.DEBUGDATA188 |
| TCELL48:IMUX.IMUX0 | PS.IRQF2P6 |
| TCELL48:IMUX.IMUX1 | PS.IRQF2P7 |
| TCELL48:IMUX.IMUX2 | PS.MAXIGP0BID4 |
| TCELL48:IMUX.IMUX3 | PS.MAXIGP0BID5 |
| TCELL48:IMUX.IMUX4 | PS.MAXIGP0BID6 |
| TCELL48:IMUX.IMUX5 | PS.MAXIGP0BID7 |
| TCELL48:IMUX.IMUX6 | PS.MAXIGP0BRESP0 |
| TCELL48:IMUX.IMUX7 | PS.MAXIGP0RID6 |
| TCELL48:IMUX.IMUX8 | PS.MAXIGP0RID7 |
| TCELL48:IMUX.IMUX9 | PS.MAXIGP0RID8 |
| TCELL48:IMUX.IMUX10 | PS.MAXIGP0RID9 |
| TCELL48:IMUX.IMUX46 | PS.TESTA9MBISTRUN |
| TCELL48:IMUX.IMUX47 | PS.TESTA9MBISTDSHIFT |
| TCELL48:OUT0.TMIN | PS.MAXIGP0AWID5 |
| TCELL48:OUT1.TMIN | PS.MAXIGP0AWID6 |
| TCELL48:OUT2.TMIN | PS.MAXIGP0AWID7 |
| TCELL48:OUT3.TMIN | PS.MAXIGP0AWADDR24 |
| TCELL48:OUT4.TMIN | PS.MAXIGP0AWADDR25 |
| TCELL48:OUT5.TMIN | PS.MAXIGP0AWADDR26 |
| TCELL48:OUT6.TMIN | PS.MAXIGP0AWADDR27 |
| TCELL48:OUT7.TMIN | PS.MAXIGP0WID8 |
| TCELL48:OUT8.TMIN | PS.MAXIGP0WID9 |
| TCELL48:OUT9.TMIN | PS.MAXIGP0WID10 |
| TCELL48:OUT10.TMIN | PS.MAXIGP0WID11 |
| TCELL48:OUT11.TMIN | PS.MAXIGP0WDATA24 |
| TCELL48:OUT12.TMIN | PS.MAXIGP0WDATA25 |
| TCELL48:OUT13.TMIN | PS.MAXIGP0WDATA26 |
| TCELL48:OUT14.TMIN | PS.MAXIGP0WDATA27 |
| TCELL48:OUT15.TMIN | PS.MAXIGP0WSTRB2 |
| TCELL48:OUT16.TMIN | PS.MAXIGP0WSTRB3 |
| TCELL48:OUT17.TMIN | PS.MAXIGP0ARADDR30 |
| TCELL48:OUT18.TMIN | PS.MAXIGP0ARADDR31 |
| TCELL48:OUT20.TMIN | PS.TESTA9MBISTRESULT3 |
| TCELL48:OUT21.TMIN | PS.TESTA9MBISTRESULT2 |
| TCELL48:OUT22.TMIN | PS.DEBUGDATA191 |
| TCELL48:OUT23.TMIN | PS.DEBUGDATA190 |
| TCELL49:IMUX.IMUX0 | PS.IRQF2P8 |
| TCELL49:IMUX.IMUX1 | PS.IRQF2P9 |
| TCELL49:IMUX.IMUX2 | PS.MAXIGP0BID8 |
| TCELL49:IMUX.IMUX3 | PS.MAXIGP0BID9 |
| TCELL49:IMUX.IMUX4 | PS.MAXIGP0BID10 |
| TCELL49:IMUX.IMUX5 | PS.MAXIGP0BID11 |
| TCELL49:IMUX.IMUX6 | PS.MAXIGP0BRESP1 |
| TCELL49:IMUX.IMUX7 | PS.MAXIGP0RID10 |
| TCELL49:IMUX.IMUX8 | PS.MAXIGP0RID11 |
| TCELL49:IMUX.IMUX45 | PS.TESTA9MBISTENABLEN |
| TCELL49:IMUX.IMUX46 | PS.TESTA9MBISTRESET |
| TCELL49:IMUX.IMUX47 | PS.TESTBSCENN |
| TCELL49:OUT0.TMIN | PS.MAXIGP0AWID8 |
| TCELL49:OUT1.TMIN | PS.MAXIGP0AWID9 |
| TCELL49:OUT2.TMIN | PS.MAXIGP0AWID10 |
| TCELL49:OUT3.TMIN | PS.MAXIGP0AWID11 |
| TCELL49:OUT4.TMIN | PS.MAXIGP0AWADDR28 |
| TCELL49:OUT5.TMIN | PS.MAXIGP0AWADDR29 |
| TCELL49:OUT6.TMIN | PS.MAXIGP0AWADDR30 |
| TCELL49:OUT7.TMIN | PS.MAXIGP0AWADDR31 |
| TCELL49:OUT8.TMIN | PS.MAXIGP0AWSIZE0 |
| TCELL49:OUT9.TMIN | PS.MAXIGP0AWSIZE1 |
| TCELL49:OUT10.TMIN | PS.MAXIGP0AWBURST0 |
| TCELL49:OUT11.TMIN | PS.MAXIGP0AWBURST1 |
| TCELL49:OUT12.TMIN | PS.MAXIGP0AWLOCK0 |
| TCELL49:OUT13.TMIN | PS.MAXIGP0AWLOCK1 |
| TCELL49:OUT14.TMIN | PS.MAXIGP0WDATA28 |
| TCELL49:OUT15.TMIN | PS.MAXIGP0WDATA29 |
| TCELL49:OUT16.TMIN | PS.MAXIGP0WDATA30 |
| TCELL49:OUT17.TMIN | PS.MAXIGP0WDATA31 |
| TCELL49:OUT18.TMIN | PS.MAXIGP0WLAST |
| TCELL49:OUT20.TMIN | PS.TESTA9MBISTRESULT5 |
| TCELL49:OUT21.TMIN | PS.TESTA9MBISTRESULT4 |
| TCELL49:OUT22.TMIN | PS.DEBUGDATA193 |
| TCELL49:OUT23.TMIN | PS.DEBUGDATA192 |
| TCELL50:IMUX.IMUX0 | PS.IRQF2P10 |
| TCELL50:IMUX.IMUX1 | PS.IRQF2P11 |
| TCELL50:IMUX.IMUX2 | PS.DDRARB0 |
| TCELL50:IMUX.IMUX3 | PS.DDRARB1 |
| TCELL50:IMUX.IMUX4 | PS.DDRARB2 |
| TCELL50:IMUX.IMUX5 | PS.DDRARB3 |
| TCELL50:IMUX.IMUX6 | PS.MAXIGP1RDATA0 |
| TCELL50:IMUX.IMUX7 | PS.MAXIGP1RDATA1 |
| TCELL50:IMUX.IMUX8 | PS.MAXIGP1RDATA2 |
| TCELL50:IMUX.IMUX9 | PS.MAXIGP1RDATA3 |
| TCELL50:IMUX.IMUX45 | PS.TESTPSSINTEST |
| TCELL50:IMUX.IMUX46 | PS.TESTPSSEXTESTSMPL |
| TCELL50:IMUX.IMUX47 | PS.TESTPSSEXTEST |
| TCELL50:OUT0.TMIN | PS.MAXIGP1ARID0 |
| TCELL50:OUT1.TMIN | PS.MAXIGP1ARID1 |
| TCELL50:OUT2.TMIN | PS.MAXIGP1ARID2 |
| TCELL50:OUT3.TMIN | PS.MAXIGP1ARID3 |
| TCELL50:OUT4.TMIN | PS.MAXIGP1ARADDR0 |
| TCELL50:OUT5.TMIN | PS.MAXIGP1ARADDR1 |
| TCELL50:OUT6.TMIN | PS.MAXIGP1ARADDR2 |
| TCELL50:OUT7.TMIN | PS.MAXIGP1ARADDR3 |
| TCELL50:OUT8.TMIN | PS.MAXIGP1ARLEN0 |
| TCELL50:OUT9.TMIN | PS.MAXIGP1ARLEN1 |
| TCELL50:OUT10.TMIN | PS.MAXIGP1ARLEN2 |
| TCELL50:OUT11.TMIN | PS.MAXIGP1ARSIZE0 |
| TCELL50:OUT12.TMIN | PS.MAXIGP1ARSIZE1 |
| TCELL50:OUT13.TMIN | PS.MAXIGP1ARBURST0 |
| TCELL50:OUT14.TMIN | PS.MAXIGP1ARBURST1 |
| TCELL50:OUT15.TMIN | PS.MAXIGP1ARLOCK0 |
| TCELL50:OUT16.TMIN | PS.MAXIGP1ARLOCK1 |
| TCELL50:OUT17.TMIN | PS.MAXIGP1ARQOS0 |
| TCELL50:OUT18.TMIN | PS.MAXIGP1ARQOS1 |
| TCELL50:OUT22.TMIN | PS.DEBUGDATA195 |
| TCELL50:OUT23.TMIN | PS.DEBUGDATA194 |
| TCELL51:IMUX.CLK1 | PS.TESTPSSCLOCKDR |
| TCELL51:IMUX.IMUX0 | PS.IRQF2P12 |
| TCELL51:IMUX.IMUX1 | PS.IRQF2P13 |
| TCELL51:IMUX.IMUX2 | PS.MAXIGP1RDATA4 |
| TCELL51:IMUX.IMUX3 | PS.MAXIGP1RDATA5 |
| TCELL51:IMUX.IMUX4 | PS.MAXIGP1RDATA6 |
| TCELL51:IMUX.IMUX5 | PS.MAXIGP1RDATA7 |
| TCELL51:IMUX.IMUX44 | PS.TESTPSSUPDATEDR |
| TCELL51:IMUX.IMUX45 | PS.TESTPSSTDI |
| TCELL51:IMUX.IMUX46 | PS.TESTPSSRESETTAPB |
| TCELL51:IMUX.IMUX47 | PS.TESTPSSSHIFTDR |
| TCELL51:OUT0.TMIN | PS.MAXIGP1AWADDR0 |
| TCELL51:OUT1.TMIN | PS.MAXIGP1AWADDR1 |
| TCELL51:OUT2.TMIN | PS.MAXIGP1ARID4 |
| TCELL51:OUT3.TMIN | PS.MAXIGP1ARID5 |
| TCELL51:OUT4.TMIN | PS.MAXIGP1ARID6 |
| TCELL51:OUT5.TMIN | PS.MAXIGP1ARADDR4 |
| TCELL51:OUT6.TMIN | PS.MAXIGP1ARADDR5 |
| TCELL51:OUT7.TMIN | PS.MAXIGP1ARADDR6 |
| TCELL51:OUT8.TMIN | PS.MAXIGP1ARADDR7 |
| TCELL51:OUT9.TMIN | PS.MAXIGP1ARLEN3 |
| TCELL51:OUT10.TMIN | PS.MAXIGP1ARCACHE0 |
| TCELL51:OUT11.TMIN | PS.MAXIGP1ARCACHE1 |
| TCELL51:OUT12.TMIN | PS.MAXIGP1ARCACHE2 |
| TCELL51:OUT13.TMIN | PS.MAXIGP1ARCACHE3 |
| TCELL51:OUT14.TMIN | PS.MAXIGP1ARPROT0 |
| TCELL51:OUT15.TMIN | PS.MAXIGP1ARQOS2 |
| TCELL51:OUT16.TMIN | PS.MAXIGP1ARQOS3 |
| TCELL51:OUT21.TMIN | PS.TESTPSSTDO |
| TCELL51:OUT22.TMIN | PS.DEBUGDATA197 |
| TCELL51:OUT23.TMIN | PS.DEBUGDATA196 |
| TCELL52:IMUX.IMUX0 | PS.IRQF2P14 |
| TCELL52:IMUX.IMUX1 | PS.IRQF2P15 |
| TCELL52:IMUX.IMUX2 | PS.MAXIGP1RDATA8 |
| TCELL52:IMUX.IMUX3 | PS.MAXIGP1RDATA9 |
| TCELL52:IMUX.IMUX4 | PS.MAXIGP1RDATA10 |
| TCELL52:IMUX.IMUX5 | PS.MAXIGP1RDATA11 |
| TCELL52:IMUX.IMUX44 | PS.TESTDIVIDERRESETN |
| TCELL52:IMUX.IMUX45 | PS.TESTSCANRESETN |
| TCELL52:IMUX.IMUX46 | PS.TESTSCANCLOCKCLOCKGEN |
| TCELL52:IMUX.IMUX47 | PS.TESTTRIGGEROPCGN |
| TCELL52:OUT0.TMIN | PS.MAXIGP1AWADDR2 |
| TCELL52:OUT1.TMIN | PS.MAXIGP1AWADDR3 |
| TCELL52:OUT2.TMIN | PS.MAXIGP1AWLEN0 |
| TCELL52:OUT3.TMIN | PS.MAXIGP1WDATA0 |
| TCELL52:OUT4.TMIN | PS.MAXIGP1WDATA1 |
| TCELL52:OUT5.TMIN | PS.MAXIGP1WDATA2 |
| TCELL52:OUT6.TMIN | PS.MAXIGP1WDATA3 |
| TCELL52:OUT7.TMIN | PS.MAXIGP1ARID7 |
| TCELL52:OUT8.TMIN | PS.MAXIGP1ARID8 |
| TCELL52:OUT9.TMIN | PS.MAXIGP1ARID9 |
| TCELL52:OUT10.TMIN | PS.MAXIGP1ARID10 |
| TCELL52:OUT11.TMIN | PS.MAXIGP1ARADDR8 |
| TCELL52:OUT12.TMIN | PS.MAXIGP1ARADDR9 |
| TCELL52:OUT13.TMIN | PS.MAXIGP1ARADDR10 |
| TCELL52:OUT14.TMIN | PS.MAXIGP1ARADDR11 |
| TCELL52:OUT15.TMIN | PS.MAXIGP1ARPROT1 |
| TCELL52:OUT16.TMIN | PS.MAXIGP1ARPROT2 |
| TCELL52:OUT22.TMIN | PS.DEBUGDATA199 |
| TCELL52:OUT23.TMIN | PS.DEBUGDATA198 |
| TCELL53:IMUX.IMUX0 | PS.IRQF2P16 |
| TCELL53:IMUX.IMUX1 | PS.IRQF2P17 |
| TCELL53:IMUX.IMUX2 | PS.MAXIGP1RDATA12 |
| TCELL53:IMUX.IMUX3 | PS.MAXIGP1RDATA13 |
| TCELL53:IMUX.IMUX4 | PS.MAXIGP1RDATA14 |
| TCELL53:IMUX.IMUX5 | PS.MAXIGP1RDATA15 |
| TCELL53:IMUX.IMUX6 | PS.MAXIGP1RLAST |
| TCELL53:IMUX.IMUX44 | PS.TESTDFTRAMBYPN |
| TCELL53:IMUX.IMUX45 | PS.TESTRESETMUXN |
| TCELL53:IMUX.IMUX46 | PS.TESTSCANENABLEATSPEEDNONSCANFLOPSN |
| TCELL53:IMUX.IMUX47 | PS.TESTSCANENABLEN |
| TCELL53:OUT0.TMIN | PS.MAXIGP1AWADDR4 |
| TCELL53:OUT1.TMIN | PS.MAXIGP1AWADDR5 |
| TCELL53:OUT2.TMIN | PS.MAXIGP1AWADDR6 |
| TCELL53:OUT3.TMIN | PS.MAXIGP1AWADDR7 |
| TCELL53:OUT4.TMIN | PS.MAXIGP1AWLEN1 |
| TCELL53:OUT5.TMIN | PS.MAXIGP1AWLEN2 |
| TCELL53:OUT6.TMIN | PS.MAXIGP1AWLEN3 |
| TCELL53:OUT7.TMIN | PS.MAXIGP1AWCACHE0 |
| TCELL53:OUT8.TMIN | PS.MAXIGP1AWCACHE1 |
| TCELL53:OUT9.TMIN | PS.MAXIGP1WDATA4 |
| TCELL53:OUT10.TMIN | PS.MAXIGP1WDATA5 |
| TCELL53:OUT11.TMIN | PS.MAXIGP1WDATA6 |
| TCELL53:OUT12.TMIN | PS.MAXIGP1WDATA7 |
| TCELL53:OUT13.TMIN | PS.MAXIGP1ARID11 |
| TCELL53:OUT14.TMIN | PS.MAXIGP1ARADDR12 |
| TCELL53:OUT15.TMIN | PS.MAXIGP1ARADDR13 |
| TCELL53:OUT16.TMIN | PS.MAXIGP1ARADDR14 |
| TCELL53:OUT17.TMIN | PS.MAXIGP1ARADDR15 |
| TCELL53:OUT21.TMIN | PS.TESTMBISTCOMPSTAT |
| TCELL53:OUT22.TMIN | PS.TESTMBISTTAPTDOENABLE |
| TCELL53:OUT23.TMIN | PS.TESTMBISTTAPTDO |
| TCELL54:IMUX.IMUX0 | PS.IRQF2P18 |
| TCELL54:IMUX.IMUX1 | PS.IRQF2P19 |
| TCELL54:IMUX.IMUX2 | PS.MAXIGP1RID0 |
| TCELL54:IMUX.IMUX3 | PS.MAXIGP1RID1 |
| TCELL54:IMUX.IMUX4 | PS.MAXIGP1RDATA16 |
| TCELL54:IMUX.IMUX5 | PS.MAXIGP1RDATA17 |
| TCELL54:IMUX.IMUX6 | PS.MAXIGP1RDATA18 |
| TCELL54:IMUX.IMUX7 | PS.MAXIGP1RDATA19 |
| TCELL54:IMUX.IMUX8 | PS.MAXIGP1RRESP0 |
| TCELL54:IMUX.IMUX9 | PS.MAXIGP1RRESP1 |
| TCELL54:IMUX.IMUX10 | PS.MAXIGP1RVALID |
| TCELL54:IMUX.IMUX44 | PS.TESTMBISTTAPTMS |
| TCELL54:IMUX.IMUX45 | PS.TESTMBISTTAPTDI |
| TCELL54:IMUX.IMUX46 | PS.TESTSCANMODEATSPEEDN |
| TCELL54:IMUX.IMUX47 | PS.TESTSCANMODEN |
| TCELL54:OUT0.TMIN | PS.MAXIGP1ARESETN |
| TCELL54:OUT1.TMIN | PS.MAXIGP1AWADDR8 |
| TCELL54:OUT2.TMIN | PS.MAXIGP1AWADDR9 |
| TCELL54:OUT3.TMIN | PS.MAXIGP1AWADDR10 |
| TCELL54:OUT4.TMIN | PS.MAXIGP1AWADDR11 |
| TCELL54:OUT5.TMIN | PS.MAXIGP1AWCACHE2 |
| TCELL54:OUT6.TMIN | PS.MAXIGP1AWCACHE3 |
| TCELL54:OUT7.TMIN | PS.MAXIGP1AWPROT0 |
| TCELL54:OUT8.TMIN | PS.MAXIGP1AWPROT1 |
| TCELL54:OUT9.TMIN | PS.MAXIGP1WID0 |
| TCELL54:OUT10.TMIN | PS.MAXIGP1WDATA8 |
| TCELL54:OUT11.TMIN | PS.MAXIGP1WDATA9 |
| TCELL54:OUT12.TMIN | PS.MAXIGP1WDATA10 |
| TCELL54:OUT13.TMIN | PS.MAXIGP1WDATA11 |
| TCELL54:OUT14.TMIN | PS.MAXIGP1ARADDR16 |
| TCELL54:OUT15.TMIN | PS.MAXIGP1ARADDR17 |
| TCELL54:OUT16.TMIN | PS.MAXIGP1ARADDR18 |
| TCELL54:OUT17.TMIN | PS.MAXIGP1ARADDR19 |
| TCELL54:OUT18.TMIN | PS.MAXIGP1RREADY |
| TCELL55:IMUX.CLK0 | PS.MAXIGP1ACLK |
| TCELL55:IMUX.IMUX0 | PS.MAXIGP1AWREADY |
| TCELL55:IMUX.IMUX1 | PS.MAXIGP1WREADY |
| TCELL55:IMUX.IMUX2 | PS.MAXIGP1ARREADY |
| TCELL55:IMUX.IMUX3 | PS.MAXIGP1RDATA20 |
| TCELL55:IMUX.IMUX4 | PS.MAXIGP1RDATA21 |
| TCELL55:IMUX.IMUX5 | PS.MAXIGP1RDATA22 |
| TCELL55:IMUX.IMUX6 | PS.MAXIGP1RDATA23 |
| TCELL55:IMUX.IMUX44 | PS.TESTMBISTMODEN |
| TCELL55:IMUX.IMUX45 | PS.TESTMBISTTAPTRST |
| TCELL55:IMUX.IMUX46 | PS.TESTSPAREIN1 |
| TCELL55:IMUX.IMUX47 | PS.TESTSPAREIN0 |
| TCELL55:OUT0.TMIN | PS.MAXIGP1AWADDR12 |
| TCELL55:OUT1.TMIN | PS.MAXIGP1AWADDR13 |
| TCELL55:OUT2.TMIN | PS.MAXIGP1AWADDR14 |
| TCELL55:OUT3.TMIN | PS.MAXIGP1AWADDR15 |
| TCELL55:OUT4.TMIN | PS.MAXIGP1AWPROT2 |
| TCELL55:OUT5.TMIN | PS.MAXIGP1AWVALID |
| TCELL55:OUT6.TMIN | PS.MAXIGP1WID1 |
| TCELL55:OUT7.TMIN | PS.MAXIGP1WID2 |
| TCELL55:OUT8.TMIN | PS.MAXIGP1WDATA12 |
| TCELL55:OUT9.TMIN | PS.MAXIGP1WDATA13 |
| TCELL55:OUT10.TMIN | PS.MAXIGP1WDATA14 |
| TCELL55:OUT11.TMIN | PS.MAXIGP1WDATA15 |
| TCELL55:OUT12.TMIN | PS.MAXIGP1WVALID |
| TCELL55:OUT13.TMIN | PS.MAXIGP1BREADY |
| TCELL55:OUT14.TMIN | PS.MAXIGP1ARADDR20 |
| TCELL55:OUT15.TMIN | PS.MAXIGP1ARADDR21 |
| TCELL55:OUT16.TMIN | PS.MAXIGP1ARADDR22 |
| TCELL55:OUT17.TMIN | PS.MAXIGP1ARADDR23 |
| TCELL55:OUT18.TMIN | PS.MAXIGP1ARVALID |
| TCELL56:IMUX.IMUX0 | PS.MAXIGP1BVALID |
| TCELL56:IMUX.IMUX1 | PS.MAXIGP1RID2 |
| TCELL56:IMUX.IMUX2 | PS.MAXIGP1RID3 |
| TCELL56:IMUX.IMUX3 | PS.MAXIGP1RDATA24 |
| TCELL56:IMUX.IMUX4 | PS.MAXIGP1RDATA25 |
| TCELL56:IMUX.IMUX5 | PS.MAXIGP1RDATA26 |
| TCELL56:IMUX.IMUX6 | PS.MAXIGP1RDATA27 |
| TCELL56:IMUX.IMUX44 | PS.TESTSPAREIN5 |
| TCELL56:IMUX.IMUX45 | PS.TESTSPAREIN4 |
| TCELL56:IMUX.IMUX46 | PS.TESTSPAREIN3 |
| TCELL56:IMUX.IMUX47 | PS.TESTSPAREIN2 |
| TCELL56:OUT0.TMIN | PS.MAXIGP1AWID0 |
| TCELL56:OUT1.TMIN | PS.MAXIGP1AWADDR16 |
| TCELL56:OUT2.TMIN | PS.MAXIGP1AWADDR17 |
| TCELL56:OUT3.TMIN | PS.MAXIGP1AWADDR18 |
| TCELL56:OUT4.TMIN | PS.MAXIGP1AWADDR19 |
| TCELL56:OUT5.TMIN | PS.MAXIGP1WID3 |
| TCELL56:OUT6.TMIN | PS.MAXIGP1WID4 |
| TCELL56:OUT7.TMIN | PS.MAXIGP1WDATA16 |
| TCELL56:OUT8.TMIN | PS.MAXIGP1WDATA17 |
| TCELL56:OUT9.TMIN | PS.MAXIGP1WDATA18 |
| TCELL56:OUT10.TMIN | PS.MAXIGP1WDATA19 |
| TCELL56:OUT11.TMIN | PS.MAXIGP1ARADDR24 |
| TCELL56:OUT12.TMIN | PS.MAXIGP1ARADDR25 |
| TCELL56:OUT13.TMIN | PS.MAXIGP1ARADDR26 |
| TCELL56:OUT14.TMIN | PS.MAXIGP1ARADDR27 |
| TCELL56:OUT15.TMIN | PS.MAXIGP1AWQOS0 |
| TCELL56:OUT16.TMIN | PS.MAXIGP1AWQOS1 |
| TCELL56:OUT17.TMIN | PS.MAXIGP1AWQOS2 |
| TCELL56:OUT18.TMIN | PS.MAXIGP1AWQOS3 |
| TCELL56:OUT21.TMIN | PS.TESTSPAREOUT2 |
| TCELL56:OUT22.TMIN | PS.TESTSPAREOUT1 |
| TCELL56:OUT23.TMIN | PS.TESTSPAREOUT0 |
| TCELL57:IMUX.CLK1 | PS.TESTMBISTTAPTCK |
| TCELL57:IMUX.IMUX0 | PS.MAXIGP1BID0 |
| TCELL57:IMUX.IMUX1 | PS.MAXIGP1BID1 |
| TCELL57:IMUX.IMUX2 | PS.MAXIGP1BID2 |
| TCELL57:IMUX.IMUX3 | PS.MAXIGP1BID3 |
| TCELL57:IMUX.IMUX4 | PS.MAXIGP1RID4 |
| TCELL57:IMUX.IMUX5 | PS.MAXIGP1RID5 |
| TCELL57:IMUX.IMUX6 | PS.MAXIGP1RDATA28 |
| TCELL57:IMUX.IMUX7 | PS.MAXIGP1RDATA29 |
| TCELL57:IMUX.IMUX8 | PS.MAXIGP1RDATA30 |
| TCELL57:IMUX.IMUX9 | PS.MAXIGP1RDATA31 |
| TCELL57:IMUX.IMUX44 | PS.TESTSLCRCONFIGRESETN |
| TCELL57:IMUX.IMUX45 | PS.TESTSLCRCONFIGIN |
| TCELL57:IMUX.IMUX46 | PS.TESTEDTCHANNELSIN0 |
| TCELL57:IMUX.IMUX47 | PS.TESTSPAREIN6 |
| TCELL57:OUT0.TMIN | PS.MAXIGP1AWID1 |
| TCELL57:OUT1.TMIN | PS.MAXIGP1AWID2 |
| TCELL57:OUT2.TMIN | PS.MAXIGP1AWID3 |
| TCELL57:OUT3.TMIN | PS.MAXIGP1AWID4 |
| TCELL57:OUT4.TMIN | PS.MAXIGP1AWADDR20 |
| TCELL57:OUT5.TMIN | PS.MAXIGP1AWADDR21 |
| TCELL57:OUT6.TMIN | PS.MAXIGP1AWADDR22 |
| TCELL57:OUT7.TMIN | PS.MAXIGP1AWADDR23 |
| TCELL57:OUT8.TMIN | PS.MAXIGP1WID5 |
| TCELL57:OUT9.TMIN | PS.MAXIGP1WID6 |
| TCELL57:OUT10.TMIN | PS.MAXIGP1WID7 |
| TCELL57:OUT11.TMIN | PS.MAXIGP1WDATA20 |
| TCELL57:OUT12.TMIN | PS.MAXIGP1WDATA21 |
| TCELL57:OUT13.TMIN | PS.MAXIGP1WDATA22 |
| TCELL57:OUT14.TMIN | PS.MAXIGP1WDATA23 |
| TCELL57:OUT15.TMIN | PS.MAXIGP1WSTRB0 |
| TCELL57:OUT16.TMIN | PS.MAXIGP1WSTRB1 |
| TCELL57:OUT17.TMIN | PS.MAXIGP1ARADDR28 |
| TCELL57:OUT18.TMIN | PS.MAXIGP1ARADDR29 |
| TCELL57:OUT20.TMIN | PS.TESTSPAREOUT6 |
| TCELL57:OUT21.TMIN | PS.TESTSPAREOUT5 |
| TCELL57:OUT22.TMIN | PS.TESTSPAREOUT4 |
| TCELL57:OUT23.TMIN | PS.TESTSPAREOUT3 |
| TCELL58:IMUX.CLK1 | PS.TESTSLCRCONFIGCLOCK |
| TCELL58:IMUX.IMUX0 | PS.MAXIGP1BID4 |
| TCELL58:IMUX.IMUX1 | PS.MAXIGP1BID5 |
| TCELL58:IMUX.IMUX2 | PS.MAXIGP1BID6 |
| TCELL58:IMUX.IMUX3 | PS.MAXIGP1BID7 |
| TCELL58:IMUX.IMUX4 | PS.MAXIGP1BRESP0 |
| TCELL58:IMUX.IMUX5 | PS.MAXIGP1RID6 |
| TCELL58:IMUX.IMUX6 | PS.MAXIGP1RID7 |
| TCELL58:IMUX.IMUX7 | PS.MAXIGP1RID8 |
| TCELL58:IMUX.IMUX8 | PS.MAXIGP1RID9 |
| TCELL58:IMUX.IMUX44 | PS.TESTEDTCHANNELSIN4 |
| TCELL58:IMUX.IMUX45 | PS.TESTEDTCHANNELSIN3 |
| TCELL58:IMUX.IMUX46 | PS.TESTEDTCHANNELSIN2 |
| TCELL58:IMUX.IMUX47 | PS.TESTEDTCHANNELSIN1 |
| TCELL58:OUT0.TMIN | PS.MAXIGP1AWID5 |
| TCELL58:OUT1.TMIN | PS.MAXIGP1AWID6 |
| TCELL58:OUT2.TMIN | PS.MAXIGP1AWID7 |
| TCELL58:OUT3.TMIN | PS.MAXIGP1AWADDR24 |
| TCELL58:OUT4.TMIN | PS.MAXIGP1AWADDR25 |
| TCELL58:OUT5.TMIN | PS.MAXIGP1AWADDR26 |
| TCELL58:OUT6.TMIN | PS.MAXIGP1AWADDR27 |
| TCELL58:OUT7.TMIN | PS.MAXIGP1WID8 |
| TCELL58:OUT8.TMIN | PS.MAXIGP1WID9 |
| TCELL58:OUT9.TMIN | PS.MAXIGP1WID10 |
| TCELL58:OUT10.TMIN | PS.MAXIGP1WID11 |
| TCELL58:OUT11.TMIN | PS.MAXIGP1WDATA24 |
| TCELL58:OUT12.TMIN | PS.MAXIGP1WDATA25 |
| TCELL58:OUT13.TMIN | PS.MAXIGP1WDATA26 |
| TCELL58:OUT14.TMIN | PS.MAXIGP1WDATA27 |
| TCELL58:OUT15.TMIN | PS.MAXIGP1WSTRB2 |
| TCELL58:OUT16.TMIN | PS.MAXIGP1WSTRB3 |
| TCELL58:OUT17.TMIN | PS.MAXIGP1ARADDR30 |
| TCELL58:OUT18.TMIN | PS.MAXIGP1ARADDR31 |
| TCELL58:OUT20.TMIN | PS.TESTSLCRCONFIGOUT |
| TCELL58:OUT21.TMIN | PS.TESTEDTCHANNELSOUT2 |
| TCELL58:OUT22.TMIN | PS.TESTEDTCHANNELSOUT1 |
| TCELL58:OUT23.TMIN | PS.TESTEDTCHANNELSOUT0 |
| TCELL59:IMUX.CLK1 | PS.TESTEDTCLOCK |
| TCELL59:IMUX.IMUX0 | PS.MAXIGP1BID8 |
| TCELL59:IMUX.IMUX1 | PS.MAXIGP1BID9 |
| TCELL59:IMUX.IMUX2 | PS.MAXIGP1BID10 |
| TCELL59:IMUX.IMUX3 | PS.MAXIGP1BID11 |
| TCELL59:IMUX.IMUX4 | PS.MAXIGP1BRESP1 |
| TCELL59:IMUX.IMUX5 | PS.MAXIGP1RID10 |
| TCELL59:IMUX.IMUX6 | PS.MAXIGP1RID11 |
| TCELL59:IMUX.IMUX44 | PS.TESTEDTCHANNELSIN6 |
| TCELL59:IMUX.IMUX45 | PS.TESTEDTCHANNELSIN5 |
| TCELL59:IMUX.IMUX46 | PS.TESTEDTBYPASS |
| TCELL59:IMUX.IMUX47 | PS.TESTEDTUPDATE |
| TCELL59:OUT0.TMIN | PS.MAXIGP1AWID8 |
| TCELL59:OUT1.TMIN | PS.MAXIGP1AWID9 |
| TCELL59:OUT2.TMIN | PS.MAXIGP1AWID10 |
| TCELL59:OUT3.TMIN | PS.MAXIGP1AWID11 |
| TCELL59:OUT4.TMIN | PS.MAXIGP1AWADDR28 |
| TCELL59:OUT5.TMIN | PS.MAXIGP1AWADDR29 |
| TCELL59:OUT6.TMIN | PS.MAXIGP1AWADDR30 |
| TCELL59:OUT7.TMIN | PS.MAXIGP1AWADDR31 |
| TCELL59:OUT8.TMIN | PS.MAXIGP1AWSIZE0 |
| TCELL59:OUT9.TMIN | PS.MAXIGP1AWSIZE1 |
| TCELL59:OUT10.TMIN | PS.MAXIGP1AWBURST0 |
| TCELL59:OUT11.TMIN | PS.MAXIGP1AWBURST1 |
| TCELL59:OUT12.TMIN | PS.MAXIGP1AWLOCK0 |
| TCELL59:OUT13.TMIN | PS.MAXIGP1AWLOCK1 |
| TCELL59:OUT14.TMIN | PS.MAXIGP1WDATA28 |
| TCELL59:OUT15.TMIN | PS.MAXIGP1WDATA29 |
| TCELL59:OUT16.TMIN | PS.MAXIGP1WDATA30 |
| TCELL59:OUT17.TMIN | PS.MAXIGP1WDATA31 |
| TCELL59:OUT18.TMIN | PS.MAXIGP1WLAST |
| TCELL59:OUT20.TMIN | PS.TESTEDTCHANNELSOUT6 |
| TCELL59:OUT21.TMIN | PS.TESTEDTCHANNELSOUT5 |
| TCELL59:OUT22.TMIN | PS.TESTEDTCHANNELSOUT4 |
| TCELL59:OUT23.TMIN | PS.TESTEDTCHANNELSOUT3 |
| TCELL60:IMUX.CLK0 | PS.FTMDTRACEINCLOCK |
| TCELL60:IMUX.IMUX0 | PS.EMIOGPIOI0 |
| TCELL60:IMUX.IMUX1 | PS.EMIOGPIOI1 |
| TCELL60:IMUX.IMUX2 | PS.EMIOGPIOI2 |
| TCELL60:IMUX.IMUX3 | PS.EMIOGPIOI3 |
| TCELL60:IMUX.IMUX4 | PS.FTMDTRACEINDATA0 |
| TCELL60:IMUX.IMUX5 | PS.FTMDTRACEINDATA1 |
| TCELL60:IMUX.IMUX6 | PS.FTMDTRACEINDATA2 |
| TCELL60:IMUX.IMUX7 | PS.FTMDTRACEINDATA3 |
| TCELL60:IMUX.IMUX8 | PS.FTMDTRACEINATID0 |
| TCELL60:IMUX.IMUX9 | PS.FTMDTRACEINATID1 |
| TCELL60:IMUX.IMUX10 | PS.FTMDTRACEINATID2 |
| TCELL60:IMUX.IMUX11 | PS.FTMDTRACEINATID3 |
| TCELL60:IMUX.IMUX12 | PS.FTMTP2FTRIGACK0 |
| TCELL60:IMUX.IMUX13 | PS.FTMTF2PDEBUG0 |
| TCELL60:IMUX.IMUX14 | PS.FTMTF2PDEBUG1 |
| TCELL60:IMUX.IMUX15 | PS.FTMTF2PDEBUG2 |
| TCELL60:IMUX.IMUX16 | PS.FTMTF2PDEBUG3 |
| TCELL60:OUT0.TMIN | PS.FTMTP2FTRIG0 |
| TCELL60:OUT1.TMIN | PS.FTMTP2FDEBUG0 |
| TCELL60:OUT2.TMIN | PS.FTMTP2FDEBUG1 |
| TCELL60:OUT3.TMIN | PS.FTMTP2FDEBUG2 |
| TCELL60:OUT4.TMIN | PS.FTMTP2FDEBUG3 |
| TCELL61:IMUX.IMUX0 | PS.EMIOGPIOI4 |
| TCELL61:IMUX.IMUX1 | PS.EMIOGPIOI5 |
| TCELL61:IMUX.IMUX2 | PS.EMIOGPIOI6 |
| TCELL61:IMUX.IMUX3 | PS.EMIOGPIOI7 |
| TCELL61:IMUX.IMUX4 | PS.FTMDTRACEINDATA4 |
| TCELL61:IMUX.IMUX5 | PS.FTMDTRACEINDATA5 |
| TCELL61:IMUX.IMUX6 | PS.FTMDTRACEINDATA6 |
| TCELL61:IMUX.IMUX7 | PS.FTMDTRACEINDATA7 |
| TCELL61:IMUX.IMUX8 | PS.FTMDTRACEINVALID |
| TCELL61:IMUX.IMUX9 | PS.FTMTF2PTRIG0 |
| TCELL61:IMUX.IMUX10 | PS.FTMTF2PDEBUG4 |
| TCELL61:IMUX.IMUX11 | PS.FTMTF2PDEBUG5 |
| TCELL61:IMUX.IMUX12 | PS.FTMTF2PDEBUG6 |
| TCELL61:IMUX.IMUX13 | PS.FTMTF2PDEBUG7 |
| TCELL61:OUT0.TMIN | PS.FCLKCLK2_INT |
| TCELL61:OUT1.TMIN | PS.FCLKCLK3_INT |
| TCELL61:OUT2.TMIN | PS.FTMTF2PTRIGACK0 |
| TCELL61:OUT3.TMIN | PS.FTMTP2FDEBUG4 |
| TCELL61:OUT4.TMIN | PS.FTMTP2FDEBUG5 |
| TCELL61:OUT5.TMIN | PS.FTMTP2FDEBUG6 |
| TCELL61:OUT6.TMIN | PS.FTMTP2FDEBUG7 |
| TCELL62:IMUX.IMUX0 | PS.EMIOGPIOI8 |
| TCELL62:IMUX.IMUX1 | PS.EMIOGPIOI9 |
| TCELL62:IMUX.IMUX2 | PS.EMIOGPIOI10 |
| TCELL62:IMUX.IMUX3 | PS.EMIOGPIOI11 |
| TCELL62:IMUX.IMUX4 | PS.FCLKCLKTRIGN2 |
| TCELL62:IMUX.IMUX5 | PS.FCLKCLKTRIGN3 |
| TCELL62:IMUX.IMUX6 | PS.FTMDTRACEINDATA8 |
| TCELL62:IMUX.IMUX7 | PS.FTMDTRACEINDATA9 |
| TCELL62:IMUX.IMUX8 | PS.FTMDTRACEINDATA10 |
| TCELL62:IMUX.IMUX9 | PS.FTMDTRACEINDATA11 |
| TCELL62:IMUX.IMUX10 | PS.FTMTP2FTRIGACK1 |
| TCELL62:IMUX.IMUX11 | PS.FTMTF2PDEBUG8 |
| TCELL62:IMUX.IMUX12 | PS.FTMTF2PDEBUG9 |
| TCELL62:IMUX.IMUX13 | PS.FTMTF2PDEBUG10 |
| TCELL62:IMUX.IMUX14 | PS.FTMTF2PDEBUG11 |
| TCELL62:OUT0.TMIN | PS.FCLKRESETN2 |
| TCELL62:OUT1.TMIN | PS.FCLKRESETN3 |
| TCELL62:OUT2.TMIN | PS.FTMTP2FTRIG1 |
| TCELL62:OUT3.TMIN | PS.FTMTP2FDEBUG8 |
| TCELL62:OUT4.TMIN | PS.FTMTP2FDEBUG9 |
| TCELL62:OUT5.TMIN | PS.FTMTP2FDEBUG10 |
| TCELL62:OUT6.TMIN | PS.FTMTP2FDEBUG11 |
| TCELL63:IMUX.IMUX0 | PS.EMIOGPIOI12 |
| TCELL63:IMUX.IMUX1 | PS.EMIOGPIOI13 |
| TCELL63:IMUX.IMUX2 | PS.EMIOGPIOI14 |
| TCELL63:IMUX.IMUX3 | PS.EMIOGPIOI15 |
| TCELL63:IMUX.IMUX4 | PS.FTMDTRACEINDATA12 |
| TCELL63:IMUX.IMUX5 | PS.FTMDTRACEINDATA13 |
| TCELL63:IMUX.IMUX6 | PS.FTMDTRACEINDATA14 |
| TCELL63:IMUX.IMUX7 | PS.FTMDTRACEINDATA15 |
| TCELL63:IMUX.IMUX8 | PS.FTMTF2PTRIG1 |
| TCELL63:IMUX.IMUX9 | PS.FTMTF2PDEBUG12 |
| TCELL63:IMUX.IMUX10 | PS.FTMTF2PDEBUG13 |
| TCELL63:IMUX.IMUX11 | PS.FTMTF2PDEBUG14 |
| TCELL63:IMUX.IMUX12 | PS.FTMTF2PDEBUG15 |
| TCELL63:OUT0.TMIN | PS.EVENTSTANDBYWFI0 |
| TCELL63:OUT1.TMIN | PS.EVENTSTANDBYWFI1 |
| TCELL63:OUT2.TMIN | PS.FTMTF2PTRIGACK1 |
| TCELL63:OUT3.TMIN | PS.FTMTP2FDEBUG12 |
| TCELL63:OUT4.TMIN | PS.FTMTP2FDEBUG13 |
| TCELL63:OUT5.TMIN | PS.FTMTP2FDEBUG14 |
| TCELL63:OUT6.TMIN | PS.FTMTP2FDEBUG15 |
| TCELL64:IMUX.IMUX0 | PS.EMIOGPIOI16 |
| TCELL64:IMUX.IMUX1 | PS.EMIOGPIOI17 |
| TCELL64:IMUX.IMUX2 | PS.EMIOGPIOI18 |
| TCELL64:IMUX.IMUX3 | PS.EMIOGPIOI19 |
| TCELL64:IMUX.IMUX4 | PS.EVENTEVENTI |
| TCELL64:IMUX.IMUX5 | PS.FTMDTRACEINDATA16 |
| TCELL64:IMUX.IMUX6 | PS.FTMDTRACEINDATA17 |
| TCELL64:IMUX.IMUX7 | PS.FTMDTRACEINDATA18 |
| TCELL64:IMUX.IMUX8 | PS.FTMDTRACEINDATA19 |
| TCELL64:IMUX.IMUX9 | PS.FTMTP2FTRIGACK2 |
| TCELL64:IMUX.IMUX10 | PS.FTMTF2PDEBUG16 |
| TCELL64:IMUX.IMUX11 | PS.FTMTF2PDEBUG17 |
| TCELL64:IMUX.IMUX12 | PS.FTMTF2PDEBUG18 |
| TCELL64:IMUX.IMUX13 | PS.FTMTF2PDEBUG19 |
| TCELL64:IMUX.IMUX14 | PS.FPGAIDLEN |
| TCELL64:OUT0.TMIN | PS.EVENTEVENTO |
| TCELL64:OUT1.TMIN | PS.EVENTSTANDBYWFE0 |
| TCELL64:OUT2.TMIN | PS.EVENTSTANDBYWFE1 |
| TCELL64:OUT3.TMIN | PS.FTMTP2FTRIG2 |
| TCELL64:OUT4.TMIN | PS.FTMTP2FDEBUG16 |
| TCELL64:OUT5.TMIN | PS.FTMTP2FDEBUG17 |
| TCELL64:OUT6.TMIN | PS.FTMTP2FDEBUG18 |
| TCELL64:OUT7.TMIN | PS.FTMTP2FDEBUG19 |
| TCELL65:IMUX.CLK1 | PS.TESTSCANCLOCKPAD0 |
| TCELL65:IMUX.IMUX0 | PS.EMIOGPIOI20 |
| TCELL65:IMUX.IMUX1 | PS.EMIOGPIOI21 |
| TCELL65:IMUX.IMUX2 | PS.EMIOGPIOI22 |
| TCELL65:IMUX.IMUX3 | PS.EMIOGPIOI23 |
| TCELL65:IMUX.IMUX4 | PS.FTMDTRACEINDATA20 |
| TCELL65:IMUX.IMUX5 | PS.FTMDTRACEINDATA21 |
| TCELL65:IMUX.IMUX6 | PS.FTMDTRACEINDATA22 |
| TCELL65:IMUX.IMUX7 | PS.FTMDTRACEINDATA23 |
| TCELL65:IMUX.IMUX8 | PS.FTMTF2PTRIG2 |
| TCELL65:IMUX.IMUX9 | PS.FTMTF2PDEBUG20 |
| TCELL65:IMUX.IMUX10 | PS.FTMTF2PDEBUG21 |
| TCELL65:IMUX.IMUX11 | PS.FTMTF2PDEBUG22 |
| TCELL65:IMUX.IMUX12 | PS.FTMTF2PDEBUG23 |
| TCELL65:OUT0.TMIN | PS.EMIOENET0PTPPDELAYREQTX |
| TCELL65:OUT1.TMIN | PS.EMIOENET0PTPPDELAYRESPTX |
| TCELL65:OUT2.TMIN | PS.EMIOENET0SOFTX |
| TCELL65:OUT3.TMIN | PS.EMIOENET0PTPSYNCFRAMERX |
| TCELL65:OUT4.TMIN | PS.EMIOENET0PTPDELAYREQRX |
| TCELL65:OUT5.TMIN | PS.EMIOENET0PTPPDELAYREQRX |
| TCELL65:OUT6.TMIN | PS.IRQP2F0 |
| TCELL65:OUT7.TMIN | PS.FTMTF2PTRIGACK2 |
| TCELL65:OUT8.TMIN | PS.FTMTP2FDEBUG20 |
| TCELL65:OUT9.TMIN | PS.FTMTP2FDEBUG21 |
| TCELL65:OUT10.TMIN | PS.FTMTP2FDEBUG22 |
| TCELL65:OUT11.TMIN | PS.FTMTP2FDEBUG23 |
| TCELL66:IMUX.CLK1 | PS.TESTSCANCLOCKPAD1 |
| TCELL66:IMUX.IMUX0 | PS.EMIOENET0MDIOI |
| TCELL66:IMUX.IMUX1 | PS.EMIOENET0EXTINTIN |
| TCELL66:IMUX.IMUX2 | PS.EMIOGPIOI24 |
| TCELL66:IMUX.IMUX3 | PS.EMIOGPIOI25 |
| TCELL66:IMUX.IMUX4 | PS.EMIOGPIOI26 |
| TCELL66:IMUX.IMUX5 | PS.EMIOGPIOI27 |
| TCELL66:IMUX.IMUX6 | PS.FTMTP2FTRIGACK3 |
| TCELL66:IMUX.IMUX7 | PS.FTMTF2PDEBUG24 |
| TCELL66:IMUX.IMUX8 | PS.FTMTF2PDEBUG25 |
| TCELL66:IMUX.IMUX9 | PS.FTMTF2PDEBUG26 |
| TCELL66:IMUX.IMUX10 | PS.FTMTF2PDEBUG27 |
| TCELL66:OUT0.TMIN | PS.EMIOENET0MDIOO |
| TCELL66:OUT1.TMIN | PS.EMIOENET0MDIOTN |
| TCELL66:OUT2.TMIN | PS.EMIOENET0PTPSYNCFRAMETX |
| TCELL66:OUT3.TMIN | PS.EMIOENET0PTPDELAYREQTX |
| TCELL66:OUT4.TMIN | PS.EMIOENET0PTPPDELAYRESPRX |
| TCELL66:OUT5.TMIN | PS.EMIOENET0SOFRX |
| TCELL66:OUT6.TMIN | PS.IRQP2F1 |
| TCELL66:OUT7.TMIN | PS.IRQP2F2 |
| TCELL66:OUT8.TMIN | PS.IRQP2F3 |
| TCELL66:OUT9.TMIN | PS.IRQP2F4 |
| TCELL66:OUT10.TMIN | PS.FTMTP2FTRIG3 |
| TCELL66:OUT11.TMIN | PS.FTMTP2FDEBUG24 |
| TCELL66:OUT12.TMIN | PS.FTMTP2FDEBUG25 |
| TCELL66:OUT13.TMIN | PS.FTMTP2FDEBUG26 |
| TCELL66:OUT14.TMIN | PS.FTMTP2FDEBUG27 |
| TCELL67:IMUX.CLK0 | PS.EMIOENET0GMIITXCLK |
| TCELL67:IMUX.CLK1 | PS.TESTSCANCLOCKPAD2 |
| TCELL67:IMUX.IMUX0 | PS.EMIOENET0GMIIRXD0 |
| TCELL67:IMUX.IMUX1 | PS.EMIOENET0GMIIRXD1 |
| TCELL67:IMUX.IMUX2 | PS.EMIOENET0GMIIRXD2 |
| TCELL67:IMUX.IMUX3 | PS.EMIOENET0GMIIRXD3 |
| TCELL67:IMUX.IMUX4 | PS.EMIOGPIOI28 |
| TCELL67:IMUX.IMUX5 | PS.EMIOGPIOI29 |
| TCELL67:IMUX.IMUX6 | PS.EMIOGPIOI30 |
| TCELL67:IMUX.IMUX7 | PS.EMIOGPIOI31 |
| TCELL67:IMUX.IMUX8 | PS.FTMTF2PTRIG3 |
| TCELL67:IMUX.IMUX9 | PS.FTMTF2PDEBUG28 |
| TCELL67:IMUX.IMUX10 | PS.FTMTF2PDEBUG29 |
| TCELL67:IMUX.IMUX11 | PS.FTMTF2PDEBUG30 |
| TCELL67:IMUX.IMUX12 | PS.FTMTF2PDEBUG31 |
| TCELL67:OUT0.TMIN | PS.EMIOENET0GMIITXD0 |
| TCELL67:OUT1.TMIN | PS.EMIOENET0GMIITXD1 |
| TCELL67:OUT2.TMIN | PS.EMIOENET0GMIITXD2 |
| TCELL67:OUT3.TMIN | PS.EMIOENET0GMIITXD3 |
| TCELL67:OUT4.TMIN | PS.EMIOENET0GMIITXER |
| TCELL67:OUT5.TMIN | PS.EMIOENET0MDIOMDC |
| TCELL67:OUT6.TMIN | PS.IRQP2F5 |
| TCELL67:OUT7.TMIN | PS.IRQP2F6 |
| TCELL67:OUT8.TMIN | PS.IRQP2F7 |
| TCELL67:OUT9.TMIN | PS.IRQP2F8 |
| TCELL67:OUT10.TMIN | PS.FTMTF2PTRIGACK3 |
| TCELL67:OUT11.TMIN | PS.FTMTP2FDEBUG28 |
| TCELL67:OUT12.TMIN | PS.FTMTP2FDEBUG29 |
| TCELL67:OUT13.TMIN | PS.FTMTP2FDEBUG30 |
| TCELL67:OUT14.TMIN | PS.FTMTP2FDEBUG31 |
| TCELL68:IMUX.CLK0 | PS.EMIOENET0GMIIRXCLK |
| TCELL68:IMUX.CLK1 | PS.TESTSCANCLOCKPAD3 |
| TCELL68:IMUX.IMUX0 | PS.EMIOENET0GMIICRS |
| TCELL68:IMUX.IMUX1 | PS.EMIOENET0GMIICOL |
| TCELL68:IMUX.IMUX2 | PS.EMIOENET0GMIIRXD4 |
| TCELL68:IMUX.IMUX3 | PS.EMIOENET0GMIIRXD5 |
| TCELL68:IMUX.IMUX4 | PS.EMIOENET0GMIIRXD6 |
| TCELL68:IMUX.IMUX5 | PS.EMIOENET0GMIIRXD7 |
| TCELL68:IMUX.IMUX6 | PS.EMIOENET0GMIIRXER |
| TCELL68:IMUX.IMUX7 | PS.EMIOENET0GMIIRXDV |
| TCELL68:IMUX.IMUX8 | PS.EMIOGPIOI32 |
| TCELL68:IMUX.IMUX9 | PS.EMIOGPIOI33 |
| TCELL68:IMUX.IMUX10 | PS.EMIOGPIOI34 |
| TCELL68:IMUX.IMUX11 | PS.EMIOGPIOI35 |
| TCELL68:OUT0.TMIN | PS.EMIOENET0GMIITXD4 |
| TCELL68:OUT1.TMIN | PS.EMIOENET0GMIITXD5 |
| TCELL68:OUT2.TMIN | PS.EMIOENET0GMIITXD6 |
| TCELL68:OUT3.TMIN | PS.EMIOENET0GMIITXD7 |
| TCELL68:OUT4.TMIN | PS.EMIOENET0GMIITXEN |
| TCELL68:OUT5.TMIN | PS.IRQP2F9 |
| TCELL68:OUT6.TMIN | PS.IRQP2F10 |
| TCELL68:OUT7.TMIN | PS.IRQP2F11 |
| TCELL68:OUT8.TMIN | PS.IRQP2F12 |
| TCELL69:IMUX.CLK1 | PS.TESTSCANCLOCKPAD4 |
| TCELL69:IMUX.IMUX0 | PS.EMIOGPIOI36 |
| TCELL69:IMUX.IMUX1 | PS.EMIOGPIOI37 |
| TCELL69:IMUX.IMUX2 | PS.EMIOGPIOI38 |
| TCELL69:IMUX.IMUX3 | PS.EMIOGPIOI39 |
| TCELL69:IMUX.IMUX4 | PS.FTMDTRACEINDATA24 |
| TCELL69:IMUX.IMUX5 | PS.FTMDTRACEINDATA25 |
| TCELL69:IMUX.IMUX6 | PS.FTMDTRACEINDATA26 |
| TCELL69:IMUX.IMUX7 | PS.FTMDTRACEINDATA27 |
| TCELL69:OUT0.TMIN | PS.EMIOENET1PTPPDELAYREQTX |
| TCELL69:OUT1.TMIN | PS.EMIOENET1PTPPDELAYRESPTX |
| TCELL69:OUT2.TMIN | PS.EMIOENET1SOFTX |
| TCELL69:OUT3.TMIN | PS.EMIOENET1PTPSYNCFRAMERX |
| TCELL69:OUT4.TMIN | PS.EMIOENET1PTPDELAYREQRX |
| TCELL69:OUT5.TMIN | PS.EMIOENET1PTPPDELAYREQRX |
| TCELL69:OUT6.TMIN | PS.IRQP2F13 |
| TCELL69:OUT7.TMIN | PS.IRQP2F14 |
| TCELL69:OUT8.TMIN | PS.IRQP2F15 |
| TCELL69:OUT9.TMIN | PS.IRQP2F16 |
| TCELL70:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG0 |
| TCELL70:IMUX.IMUX0 | PS.EMIOENET1MDIOI |
| TCELL70:IMUX.IMUX1 | PS.EMIOENET1EXTINTIN |
| TCELL70:IMUX.IMUX2 | PS.EMIOGPIOI40 |
| TCELL70:IMUX.IMUX3 | PS.EMIOGPIOI41 |
| TCELL70:IMUX.IMUX4 | PS.EMIOGPIOI42 |
| TCELL70:IMUX.IMUX5 | PS.EMIOGPIOI43 |
| TCELL70:IMUX.IMUX6 | PS.EMIOGPIOI44 |
| TCELL70:IMUX.IMUX7 | PS.EMIOGPIOI45 |
| TCELL70:IMUX.IMUX8 | PS.EMIOGPIOI46 |
| TCELL70:IMUX.IMUX9 | PS.EMIOGPIOI47 |
| TCELL70:IMUX.IMUX10 | PS.FTMDTRACEINDATA28 |
| TCELL70:IMUX.IMUX11 | PS.FTMDTRACEINDATA29 |
| TCELL70:IMUX.IMUX12 | PS.FTMDTRACEINDATA30 |
| TCELL70:IMUX.IMUX13 | PS.FTMDTRACEINDATA31 |
| TCELL70:OUT0.TMIN | PS.EMIOENET1MDIOO |
| TCELL70:OUT1.TMIN | PS.EMIOENET1MDIOTN |
| TCELL70:OUT2.TMIN | PS.EMIOENET1PTPSYNCFRAMETX |
| TCELL70:OUT3.TMIN | PS.EMIOENET1PTPDELAYREQTX |
| TCELL70:OUT4.TMIN | PS.EMIOENET1PTPPDELAYRESPRX |
| TCELL70:OUT5.TMIN | PS.EMIOENET1SOFRX |
| TCELL70:OUT6.TMIN | PS.IRQP2F17 |
| TCELL70:OUT7.TMIN | PS.IRQP2F18 |
| TCELL70:OUT8.TMIN | PS.IRQP2F19 |
| TCELL70:OUT9.TMIN | PS.IRQP2F20 |
| TCELL71:IMUX.CLK0 | PS.EMIOENET1GMIITXCLK |
| TCELL71:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG1 |
| TCELL71:IMUX.IMUX0 | PS.EMIOENET1GMIIRXD0 |
| TCELL71:IMUX.IMUX1 | PS.EMIOENET1GMIIRXD1 |
| TCELL71:IMUX.IMUX2 | PS.EMIOENET1GMIIRXD2 |
| TCELL71:IMUX.IMUX3 | PS.EMIOENET1GMIIRXD3 |
| TCELL71:IMUX.IMUX4 | PS.EMIOGPIOI48 |
| TCELL71:IMUX.IMUX5 | PS.EMIOGPIOI49 |
| TCELL71:IMUX.IMUX6 | PS.EMIOGPIOI50 |
| TCELL71:IMUX.IMUX7 | PS.EMIOGPIOI51 |
| TCELL71:IMUX.IMUX8 | PS.EMIOGPIOI52 |
| TCELL71:IMUX.IMUX9 | PS.EMIOGPIOI53 |
| TCELL71:IMUX.IMUX10 | PS.EMIOGPIOI54 |
| TCELL71:IMUX.IMUX11 | PS.EMIOGPIOI55 |
| TCELL71:OUT0.TMIN | PS.EMIOENET1GMIITXD0 |
| TCELL71:OUT1.TMIN | PS.EMIOENET1GMIITXD1 |
| TCELL71:OUT2.TMIN | PS.EMIOENET1GMIITXD2 |
| TCELL71:OUT3.TMIN | PS.EMIOENET1GMIITXD3 |
| TCELL71:OUT4.TMIN | PS.EMIOENET1GMIITXER |
| TCELL71:OUT5.TMIN | PS.EMIOENET1MDIOMDC |
| TCELL71:OUT6.TMIN | PS.IRQP2F21 |
| TCELL71:OUT7.TMIN | PS.IRQP2F22 |
| TCELL71:OUT8.TMIN | PS.IRQP2F23 |
| TCELL71:OUT9.TMIN | PS.IRQP2F24 |
| TCELL72:IMUX.CLK0 | PS.EMIOENET1GMIIRXCLK |
| TCELL72:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG2 |
| TCELL72:IMUX.IMUX0 | PS.EMIOENET1GMIICRS |
| TCELL72:IMUX.IMUX1 | PS.EMIOENET1GMIICOL |
| TCELL72:IMUX.IMUX2 | PS.EMIOENET1GMIIRXD4 |
| TCELL72:IMUX.IMUX3 | PS.EMIOENET1GMIIRXD5 |
| TCELL72:IMUX.IMUX4 | PS.EMIOENET1GMIIRXD6 |
| TCELL72:IMUX.IMUX5 | PS.EMIOENET1GMIIRXD7 |
| TCELL72:IMUX.IMUX6 | PS.EMIOENET1GMIIRXER |
| TCELL72:IMUX.IMUX7 | PS.EMIOENET1GMIIRXDV |
| TCELL72:IMUX.IMUX8 | PS.EMIOGPIOI56 |
| TCELL72:IMUX.IMUX9 | PS.EMIOGPIOI57 |
| TCELL72:IMUX.IMUX10 | PS.EMIOGPIOI58 |
| TCELL72:IMUX.IMUX11 | PS.EMIOGPIOI59 |
| TCELL72:IMUX.IMUX12 | PS.EMIOGPIOI60 |
| TCELL72:IMUX.IMUX13 | PS.EMIOGPIOI61 |
| TCELL72:IMUX.IMUX14 | PS.EMIOGPIOI62 |
| TCELL72:IMUX.IMUX15 | PS.EMIOGPIOI63 |
| TCELL72:OUT0.TMIN | PS.EMIOENET1GMIITXD4 |
| TCELL72:OUT1.TMIN | PS.EMIOENET1GMIITXD5 |
| TCELL72:OUT2.TMIN | PS.EMIOENET1GMIITXD6 |
| TCELL72:OUT3.TMIN | PS.EMIOENET1GMIITXD7 |
| TCELL72:OUT4.TMIN | PS.EMIOENET1GMIITXEN |
| TCELL72:OUT5.TMIN | PS.IRQP2F25 |
| TCELL72:OUT6.TMIN | PS.IRQP2F26 |
| TCELL72:OUT7.TMIN | PS.IRQP2F27 |
| TCELL72:OUT8.TMIN | PS.IRQP2F28 |
| TCELL73:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG3 |
| TCELL73:IMUX.IMUX0 | PS.SAXIGP0AWADDR0 |
| TCELL73:IMUX.IMUX1 | PS.SAXIGP0AWADDR1 |
| TCELL73:IMUX.IMUX2 | PS.SAXIGP0AWADDR2 |
| TCELL73:IMUX.IMUX3 | PS.SAXIGP0AWADDR3 |
| TCELL73:IMUX.IMUX4 | PS.SAXIGP0WDATA0 |
| TCELL73:IMUX.IMUX5 | PS.SAXIGP0WDATA1 |
| TCELL73:IMUX.IMUX6 | PS.SAXIGP0WDATA2 |
| TCELL73:IMUX.IMUX7 | PS.SAXIGP0WDATA3 |
| TCELL73:IMUX.IMUX8 | PS.SAXIGP0ARADDR0 |
| TCELL73:IMUX.IMUX9 | PS.SAXIGP0ARADDR1 |
| TCELL73:IMUX.IMUX10 | PS.SAXIGP0ARADDR2 |
| TCELL73:IMUX.IMUX11 | PS.SAXIGP0ARADDR3 |
| TCELL73:IMUX.IMUX12 | PS.SAXIGP0ARCACHE0 |
| TCELL73:IMUX.IMUX13 | PS.SAXIGP0ARCACHE1 |
| TCELL73:IMUX.IMUX14 | PS.SAXIGP0ARCACHE2 |
| TCELL73:IMUX.IMUX15 | PS.SAXIGP0ARCACHE3 |
| TCELL73:IMUX.IMUX16 | PS.SAXIGP0ARPROT0 |
| TCELL73:IMUX.IMUX17 | PS.SAXIGP0ARPROT1 |
| TCELL73:IMUX.IMUX18 | PS.SAXIGP0ARPROT2 |
| TCELL73:OUT0.TMIN | PS.EMIOGPIOO0 |
| TCELL73:OUT1.TMIN | PS.EMIOGPIOO1 |
| TCELL73:OUT2.TMIN | PS.EMIOGPIOO2 |
| TCELL73:OUT3.TMIN | PS.EMIOGPIOO3 |
| TCELL73:OUT4.TMIN | PS.EMIOGPIOTN0 |
| TCELL73:OUT5.TMIN | PS.EMIOGPIOTN1 |
| TCELL73:OUT6.TMIN | PS.EMIOGPIOTN2 |
| TCELL73:OUT7.TMIN | PS.EMIOGPIOTN3 |
| TCELL73:OUT8.TMIN | PS.SAXIGP0RID0 |
| TCELL73:OUT9.TMIN | PS.SAXIGP0RID1 |
| TCELL73:OUT10.TMIN | PS.SAXIGP0RID2 |
| TCELL73:OUT11.TMIN | PS.SAXIGP0RID3 |
| TCELL73:OUT12.TMIN | PS.SAXIGP0RDATA0 |
| TCELL73:OUT13.TMIN | PS.SAXIGP0RDATA1 |
| TCELL73:OUT14.TMIN | PS.SAXIGP0RDATA2 |
| TCELL73:OUT15.TMIN | PS.SAXIGP0RDATA3 |
| TCELL74:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG4 |
| TCELL74:IMUX.IMUX0 | PS.SAXIGP0AWADDR4 |
| TCELL74:IMUX.IMUX1 | PS.SAXIGP0AWADDR5 |
| TCELL74:IMUX.IMUX2 | PS.SAXIGP0AWADDR6 |
| TCELL74:IMUX.IMUX3 | PS.SAXIGP0AWADDR7 |
| TCELL74:IMUX.IMUX4 | PS.SAXIGP0WDATA4 |
| TCELL74:IMUX.IMUX5 | PS.SAXIGP0WDATA5 |
| TCELL74:IMUX.IMUX6 | PS.SAXIGP0WDATA6 |
| TCELL74:IMUX.IMUX7 | PS.SAXIGP0WDATA7 |
| TCELL74:IMUX.IMUX8 | PS.SAXIGP0WLAST |
| TCELL74:IMUX.IMUX9 | PS.SAXIGP0ARADDR4 |
| TCELL74:IMUX.IMUX10 | PS.SAXIGP0ARADDR5 |
| TCELL74:IMUX.IMUX11 | PS.SAXIGP0ARADDR6 |
| TCELL74:IMUX.IMUX12 | PS.SAXIGP0ARADDR7 |
| TCELL74:IMUX.IMUX13 | PS.SAXIGP0ARBURST0 |
| TCELL74:IMUX.IMUX14 | PS.SAXIGP0ARBURST1 |
| TCELL74:IMUX.IMUX15 | PS.SAXIGP0ARLOCK0 |
| TCELL74:IMUX.IMUX16 | PS.SAXIGP0ARLOCK1 |
| TCELL74:IMUX.IMUX17 | PS.SAXIGP0ARQOS0 |
| TCELL74:IMUX.IMUX18 | PS.SAXIGP0ARQOS1 |
| TCELL74:IMUX.IMUX19 | PS.SAXIGP0ARQOS2 |
| TCELL74:IMUX.IMUX20 | PS.SAXIGP0ARQOS3 |
| TCELL74:OUT0.TMIN | PS.EMIOGPIOO4 |
| TCELL74:OUT1.TMIN | PS.EMIOGPIOO5 |
| TCELL74:OUT2.TMIN | PS.EMIOGPIOO6 |
| TCELL74:OUT3.TMIN | PS.EMIOGPIOO7 |
| TCELL74:OUT4.TMIN | PS.EMIOGPIOTN4 |
| TCELL74:OUT5.TMIN | PS.EMIOGPIOTN5 |
| TCELL74:OUT6.TMIN | PS.EMIOGPIOTN6 |
| TCELL74:OUT7.TMIN | PS.EMIOGPIOTN7 |
| TCELL74:OUT8.TMIN | PS.SAXIGP0RID4 |
| TCELL74:OUT9.TMIN | PS.SAXIGP0RID5 |
| TCELL74:OUT10.TMIN | PS.SAXIGP0RDATA4 |
| TCELL74:OUT11.TMIN | PS.SAXIGP0RDATA5 |
| TCELL74:OUT12.TMIN | PS.SAXIGP0RDATA6 |
| TCELL74:OUT13.TMIN | PS.SAXIGP0RDATA7 |
| TCELL74:OUT14.TMIN | PS.SAXIGP0RLAST |
| TCELL75:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG5 |
| TCELL75:IMUX.IMUX0 | PS.SAXIGP0AWADDR8 |
| TCELL75:IMUX.IMUX1 | PS.SAXIGP0AWADDR9 |
| TCELL75:IMUX.IMUX2 | PS.SAXIGP0AWADDR10 |
| TCELL75:IMUX.IMUX3 | PS.SAXIGP0AWADDR11 |
| TCELL75:IMUX.IMUX4 | PS.SAXIGP0WDATA8 |
| TCELL75:IMUX.IMUX5 | PS.SAXIGP0WDATA9 |
| TCELL75:IMUX.IMUX6 | PS.SAXIGP0WDATA10 |
| TCELL75:IMUX.IMUX7 | PS.SAXIGP0WDATA11 |
| TCELL75:IMUX.IMUX8 | PS.SAXIGP0ARID0 |
| TCELL75:IMUX.IMUX9 | PS.SAXIGP0ARID1 |
| TCELL75:IMUX.IMUX10 | PS.SAXIGP0ARID2 |
| TCELL75:IMUX.IMUX11 | PS.SAXIGP0ARID3 |
| TCELL75:IMUX.IMUX12 | PS.SAXIGP0ARADDR8 |
| TCELL75:IMUX.IMUX13 | PS.SAXIGP0ARADDR9 |
| TCELL75:IMUX.IMUX14 | PS.SAXIGP0ARADDR10 |
| TCELL75:IMUX.IMUX15 | PS.SAXIGP0ARADDR11 |
| TCELL75:IMUX.IMUX16 | PS.SAXIGP0ARLEN0 |
| TCELL75:IMUX.IMUX17 | PS.SAXIGP0ARLEN1 |
| TCELL75:IMUX.IMUX18 | PS.SAXIGP0ARLEN2 |
| TCELL75:IMUX.IMUX19 | PS.SAXIGP0ARLEN3 |
| TCELL75:IMUX.IMUX20 | PS.SAXIGP0ARSIZE0 |
| TCELL75:IMUX.IMUX21 | PS.SAXIGP0ARSIZE1 |
| TCELL75:OUT0.TMIN | PS.EMIOGPIOO8 |
| TCELL75:OUT1.TMIN | PS.EMIOGPIOO9 |
| TCELL75:OUT2.TMIN | PS.EMIOGPIOO10 |
| TCELL75:OUT3.TMIN | PS.EMIOGPIOO11 |
| TCELL75:OUT4.TMIN | PS.EMIOGPIOTN8 |
| TCELL75:OUT5.TMIN | PS.EMIOGPIOTN9 |
| TCELL75:OUT6.TMIN | PS.EMIOGPIOTN10 |
| TCELL75:OUT7.TMIN | PS.EMIOGPIOTN11 |
| TCELL75:OUT8.TMIN | PS.SAXIGP0RDATA8 |
| TCELL75:OUT9.TMIN | PS.SAXIGP0RDATA9 |
| TCELL75:OUT10.TMIN | PS.SAXIGP0RDATA10 |
| TCELL75:OUT11.TMIN | PS.SAXIGP0RDATA11 |
| TCELL75:OUT12.TMIN | PS.SAXIGP0RRESP0 |
| TCELL75:OUT13.TMIN | PS.SAXIGP0RRESP1 |
| TCELL76:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG6 |
| TCELL76:IMUX.IMUX0 | PS.SAXIGP0AWADDR12 |
| TCELL76:IMUX.IMUX1 | PS.SAXIGP0AWADDR13 |
| TCELL76:IMUX.IMUX2 | PS.SAXIGP0AWADDR14 |
| TCELL76:IMUX.IMUX3 | PS.SAXIGP0AWADDR15 |
| TCELL76:IMUX.IMUX4 | PS.SAXIGP0AWPROT0 |
| TCELL76:IMUX.IMUX5 | PS.SAXIGP0AWPROT1 |
| TCELL76:IMUX.IMUX6 | PS.SAXIGP0AWPROT2 |
| TCELL76:IMUX.IMUX7 | PS.SAXIGP0WID0 |
| TCELL76:IMUX.IMUX8 | PS.SAXIGP0WID1 |
| TCELL76:IMUX.IMUX9 | PS.SAXIGP0WDATA12 |
| TCELL76:IMUX.IMUX10 | PS.SAXIGP0WDATA13 |
| TCELL76:IMUX.IMUX11 | PS.SAXIGP0WDATA14 |
| TCELL76:IMUX.IMUX12 | PS.SAXIGP0WDATA15 |
| TCELL76:IMUX.IMUX13 | PS.SAXIGP0ARID4 |
| TCELL76:IMUX.IMUX14 | PS.SAXIGP0ARID5 |
| TCELL76:IMUX.IMUX15 | PS.SAXIGP0ARADDR12 |
| TCELL76:IMUX.IMUX16 | PS.SAXIGP0ARADDR13 |
| TCELL76:IMUX.IMUX17 | PS.SAXIGP0ARADDR14 |
| TCELL76:IMUX.IMUX18 | PS.SAXIGP0ARADDR15 |
| TCELL76:IMUX.IMUX19 | PS.SAXIGP0ARVALID |
| TCELL76:IMUX.IMUX20 | PS.SAXIGP0RREADY |
| TCELL76:OUT0.TMIN | PS.EMIOGPIOO12 |
| TCELL76:OUT1.TMIN | PS.EMIOGPIOO13 |
| TCELL76:OUT2.TMIN | PS.EMIOGPIOO14 |
| TCELL76:OUT3.TMIN | PS.EMIOGPIOO15 |
| TCELL76:OUT4.TMIN | PS.EMIOGPIOTN12 |
| TCELL76:OUT5.TMIN | PS.EMIOGPIOTN13 |
| TCELL76:OUT6.TMIN | PS.EMIOGPIOTN14 |
| TCELL76:OUT7.TMIN | PS.EMIOGPIOTN15 |
| TCELL76:OUT8.TMIN | PS.SAXIGP0ARREADY |
| TCELL76:OUT9.TMIN | PS.SAXIGP0RDATA12 |
| TCELL76:OUT10.TMIN | PS.SAXIGP0RDATA13 |
| TCELL76:OUT11.TMIN | PS.SAXIGP0RDATA14 |
| TCELL76:OUT12.TMIN | PS.SAXIGP0RDATA15 |
| TCELL76:OUT13.TMIN | PS.SAXIGP0RVALID |
| TCELL77:IMUX.CLK0 | PS.SAXIGP0ACLK |
| TCELL77:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG7 |
| TCELL77:IMUX.IMUX0 | PS.SAXIGP0AWADDR16 |
| TCELL77:IMUX.IMUX1 | PS.SAXIGP0AWADDR17 |
| TCELL77:IMUX.IMUX2 | PS.SAXIGP0AWADDR18 |
| TCELL77:IMUX.IMUX3 | PS.SAXIGP0AWADDR19 |
| TCELL77:IMUX.IMUX4 | PS.SAXIGP0AWCACHE0 |
| TCELL77:IMUX.IMUX5 | PS.SAXIGP0AWCACHE1 |
| TCELL77:IMUX.IMUX6 | PS.SAXIGP0AWVALID |
| TCELL77:IMUX.IMUX7 | PS.SAXIGP0WID2 |
| TCELL77:IMUX.IMUX8 | PS.SAXIGP0WID3 |
| TCELL77:IMUX.IMUX9 | PS.SAXIGP0WID4 |
| TCELL77:IMUX.IMUX10 | PS.SAXIGP0WID5 |
| TCELL77:IMUX.IMUX11 | PS.SAXIGP0WDATA16 |
| TCELL77:IMUX.IMUX12 | PS.SAXIGP0WDATA17 |
| TCELL77:IMUX.IMUX13 | PS.SAXIGP0WDATA18 |
| TCELL77:IMUX.IMUX14 | PS.SAXIGP0WDATA19 |
| TCELL77:IMUX.IMUX15 | PS.SAXIGP0WVALID |
| TCELL77:IMUX.IMUX16 | PS.SAXIGP0ARADDR16 |
| TCELL77:IMUX.IMUX17 | PS.SAXIGP0ARADDR17 |
| TCELL77:IMUX.IMUX18 | PS.SAXIGP0ARADDR18 |
| TCELL77:IMUX.IMUX19 | PS.SAXIGP0ARADDR19 |
| TCELL77:OUT0.TMIN | PS.EMIOGPIOO16 |
| TCELL77:OUT1.TMIN | PS.EMIOGPIOO17 |
| TCELL77:OUT2.TMIN | PS.EMIOGPIOO18 |
| TCELL77:OUT3.TMIN | PS.EMIOGPIOO19 |
| TCELL77:OUT4.TMIN | PS.EMIOGPIOTN16 |
| TCELL77:OUT5.TMIN | PS.EMIOGPIOTN17 |
| TCELL77:OUT6.TMIN | PS.EMIOGPIOTN18 |
| TCELL77:OUT7.TMIN | PS.EMIOGPIOTN19 |
| TCELL77:OUT8.TMIN | PS.SAXIGP0ARESETN |
| TCELL77:OUT9.TMIN | PS.SAXIGP0AWREADY |
| TCELL77:OUT10.TMIN | PS.SAXIGP0WREADY |
| TCELL77:OUT11.TMIN | PS.SAXIGP0RDATA16 |
| TCELL77:OUT12.TMIN | PS.SAXIGP0RDATA17 |
| TCELL77:OUT13.TMIN | PS.SAXIGP0RDATA18 |
| TCELL77:OUT14.TMIN | PS.SAXIGP0RDATA19 |
| TCELL78:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG8 |
| TCELL78:IMUX.IMUX0 | PS.SAXIGP0AWADDR20 |
| TCELL78:IMUX.IMUX1 | PS.SAXIGP0AWADDR21 |
| TCELL78:IMUX.IMUX2 | PS.SAXIGP0AWADDR22 |
| TCELL78:IMUX.IMUX3 | PS.SAXIGP0AWADDR23 |
| TCELL78:IMUX.IMUX4 | PS.SAXIGP0AWBURST0 |
| TCELL78:IMUX.IMUX5 | PS.SAXIGP0AWBURST1 |
| TCELL78:IMUX.IMUX6 | PS.SAXIGP0AWLOCK0 |
| TCELL78:IMUX.IMUX7 | PS.SAXIGP0AWLOCK1 |
| TCELL78:IMUX.IMUX8 | PS.SAXIGP0AWCACHE2 |
| TCELL78:IMUX.IMUX9 | PS.SAXIGP0AWCACHE3 |
| TCELL78:IMUX.IMUX10 | PS.SAXIGP0WDATA20 |
| TCELL78:IMUX.IMUX11 | PS.SAXIGP0WDATA21 |
| TCELL78:IMUX.IMUX12 | PS.SAXIGP0WDATA22 |
| TCELL78:IMUX.IMUX13 | PS.SAXIGP0WDATA23 |
| TCELL78:IMUX.IMUX14 | PS.SAXIGP0BREADY |
| TCELL78:IMUX.IMUX15 | PS.SAXIGP0ARADDR20 |
| TCELL78:IMUX.IMUX16 | PS.SAXIGP0ARADDR21 |
| TCELL78:IMUX.IMUX17 | PS.SAXIGP0ARADDR22 |
| TCELL78:IMUX.IMUX18 | PS.SAXIGP0ARADDR23 |
| TCELL78:IMUX.IMUX19 | PS.SAXIGP0AWQOS0 |
| TCELL78:IMUX.IMUX20 | PS.SAXIGP0AWQOS1 |
| TCELL78:IMUX.IMUX21 | PS.SAXIGP0AWQOS2 |
| TCELL78:IMUX.IMUX22 | PS.SAXIGP0AWQOS3 |
| TCELL78:OUT0.TMIN | PS.EMIOGPIOO20 |
| TCELL78:OUT1.TMIN | PS.EMIOGPIOO21 |
| TCELL78:OUT2.TMIN | PS.EMIOGPIOO22 |
| TCELL78:OUT3.TMIN | PS.EMIOGPIOO23 |
| TCELL78:OUT4.TMIN | PS.EMIOGPIOTN20 |
| TCELL78:OUT5.TMIN | PS.EMIOGPIOTN21 |
| TCELL78:OUT6.TMIN | PS.EMIOGPIOTN22 |
| TCELL78:OUT7.TMIN | PS.EMIOGPIOTN23 |
| TCELL78:OUT8.TMIN | PS.SAXIGP0BVALID |
| TCELL78:OUT9.TMIN | PS.SAXIGP0RDATA20 |
| TCELL78:OUT10.TMIN | PS.SAXIGP0RDATA21 |
| TCELL78:OUT11.TMIN | PS.SAXIGP0RDATA22 |
| TCELL78:OUT12.TMIN | PS.SAXIGP0RDATA23 |
| TCELL79:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG9 |
| TCELL79:IMUX.IMUX0 | PS.SAXIGP0AWID0 |
| TCELL79:IMUX.IMUX1 | PS.SAXIGP0AWID1 |
| TCELL79:IMUX.IMUX2 | PS.SAXIGP0AWADDR24 |
| TCELL79:IMUX.IMUX3 | PS.SAXIGP0AWADDR25 |
| TCELL79:IMUX.IMUX4 | PS.SAXIGP0AWADDR26 |
| TCELL79:IMUX.IMUX5 | PS.SAXIGP0AWADDR27 |
| TCELL79:IMUX.IMUX6 | PS.SAXIGP0AWSIZE0 |
| TCELL79:IMUX.IMUX7 | PS.SAXIGP0AWSIZE1 |
| TCELL79:IMUX.IMUX8 | PS.SAXIGP0WDATA24 |
| TCELL79:IMUX.IMUX9 | PS.SAXIGP0WDATA25 |
| TCELL79:IMUX.IMUX10 | PS.SAXIGP0WDATA26 |
| TCELL79:IMUX.IMUX11 | PS.SAXIGP0WDATA27 |
| TCELL79:IMUX.IMUX12 | PS.SAXIGP0WSTRB0 |
| TCELL79:IMUX.IMUX13 | PS.SAXIGP0WSTRB1 |
| TCELL79:IMUX.IMUX14 | PS.SAXIGP0WSTRB2 |
| TCELL79:IMUX.IMUX15 | PS.SAXIGP0WSTRB3 |
| TCELL79:IMUX.IMUX16 | PS.SAXIGP0ARADDR24 |
| TCELL79:IMUX.IMUX17 | PS.SAXIGP0ARADDR25 |
| TCELL79:IMUX.IMUX18 | PS.SAXIGP0ARADDR26 |
| TCELL79:IMUX.IMUX19 | PS.SAXIGP0ARADDR27 |
| TCELL79:OUT0.TMIN | PS.EMIOGPIOO24 |
| TCELL79:OUT1.TMIN | PS.EMIOGPIOO25 |
| TCELL79:OUT2.TMIN | PS.EMIOGPIOO26 |
| TCELL79:OUT3.TMIN | PS.EMIOGPIOO27 |
| TCELL79:OUT4.TMIN | PS.EMIOGPIOTN24 |
| TCELL79:OUT5.TMIN | PS.EMIOGPIOTN25 |
| TCELL79:OUT6.TMIN | PS.EMIOGPIOTN26 |
| TCELL79:OUT7.TMIN | PS.EMIOGPIOTN27 |
| TCELL79:OUT8.TMIN | PS.SAXIGP0BID0 |
| TCELL79:OUT9.TMIN | PS.SAXIGP0BID1 |
| TCELL79:OUT10.TMIN | PS.SAXIGP0BRESP0 |
| TCELL79:OUT11.TMIN | PS.SAXIGP0BRESP1 |
| TCELL79:OUT12.TMIN | PS.SAXIGP0RDATA24 |
| TCELL79:OUT13.TMIN | PS.SAXIGP0RDATA25 |
| TCELL79:OUT14.TMIN | PS.SAXIGP0RDATA26 |
| TCELL79:OUT15.TMIN | PS.SAXIGP0RDATA27 |
| TCELL80:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG10 |
| TCELL80:IMUX.IMUX0 | PS.SAXIGP0AWID2 |
| TCELL80:IMUX.IMUX1 | PS.SAXIGP0AWID3 |
| TCELL80:IMUX.IMUX2 | PS.SAXIGP0AWID4 |
| TCELL80:IMUX.IMUX3 | PS.SAXIGP0AWID5 |
| TCELL80:IMUX.IMUX4 | PS.SAXIGP0AWADDR28 |
| TCELL80:IMUX.IMUX5 | PS.SAXIGP0AWADDR29 |
| TCELL80:IMUX.IMUX6 | PS.SAXIGP0AWADDR30 |
| TCELL80:IMUX.IMUX7 | PS.SAXIGP0AWADDR31 |
| TCELL80:IMUX.IMUX8 | PS.SAXIGP0AWLEN0 |
| TCELL80:IMUX.IMUX9 | PS.SAXIGP0AWLEN1 |
| TCELL80:IMUX.IMUX10 | PS.SAXIGP0AWLEN2 |
| TCELL80:IMUX.IMUX11 | PS.SAXIGP0AWLEN3 |
| TCELL80:IMUX.IMUX12 | PS.SAXIGP0WDATA28 |
| TCELL80:IMUX.IMUX13 | PS.SAXIGP0WDATA29 |
| TCELL80:IMUX.IMUX14 | PS.SAXIGP0WDATA30 |
| TCELL80:IMUX.IMUX15 | PS.SAXIGP0WDATA31 |
| TCELL80:IMUX.IMUX16 | PS.SAXIGP0ARADDR28 |
| TCELL80:IMUX.IMUX17 | PS.SAXIGP0ARADDR29 |
| TCELL80:IMUX.IMUX18 | PS.SAXIGP0ARADDR30 |
| TCELL80:IMUX.IMUX19 | PS.SAXIGP0ARADDR31 |
| TCELL80:OUT0.TMIN | PS.EMIOGPIOO28 |
| TCELL80:OUT1.TMIN | PS.EMIOGPIOO29 |
| TCELL80:OUT2.TMIN | PS.EMIOGPIOO30 |
| TCELL80:OUT3.TMIN | PS.EMIOGPIOO31 |
| TCELL80:OUT4.TMIN | PS.EMIOGPIOTN28 |
| TCELL80:OUT5.TMIN | PS.EMIOGPIOTN29 |
| TCELL80:OUT6.TMIN | PS.EMIOGPIOTN30 |
| TCELL80:OUT7.TMIN | PS.EMIOGPIOTN31 |
| TCELL80:OUT8.TMIN | PS.SAXIGP0BID2 |
| TCELL80:OUT9.TMIN | PS.SAXIGP0BID3 |
| TCELL80:OUT10.TMIN | PS.SAXIGP0BID4 |
| TCELL80:OUT11.TMIN | PS.SAXIGP0BID5 |
| TCELL80:OUT12.TMIN | PS.SAXIGP0RDATA28 |
| TCELL80:OUT13.TMIN | PS.SAXIGP0RDATA29 |
| TCELL80:OUT14.TMIN | PS.SAXIGP0RDATA30 |
| TCELL80:OUT15.TMIN | PS.SAXIGP0RDATA31 |
| TCELL81:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG11 |
| TCELL81:IMUX.IMUX0 | PS.SAXIGP1AWADDR0 |
| TCELL81:IMUX.IMUX1 | PS.SAXIGP1AWADDR1 |
| TCELL81:IMUX.IMUX2 | PS.SAXIGP1AWADDR2 |
| TCELL81:IMUX.IMUX3 | PS.SAXIGP1AWADDR3 |
| TCELL81:IMUX.IMUX4 | PS.SAXIGP1WDATA0 |
| TCELL81:IMUX.IMUX5 | PS.SAXIGP1WDATA1 |
| TCELL81:IMUX.IMUX6 | PS.SAXIGP1WDATA2 |
| TCELL81:IMUX.IMUX7 | PS.SAXIGP1WDATA3 |
| TCELL81:IMUX.IMUX8 | PS.SAXIGP1ARADDR0 |
| TCELL81:IMUX.IMUX9 | PS.SAXIGP1ARADDR1 |
| TCELL81:IMUX.IMUX10 | PS.SAXIGP1ARADDR2 |
| TCELL81:IMUX.IMUX11 | PS.SAXIGP1ARADDR3 |
| TCELL81:IMUX.IMUX12 | PS.SAXIGP1ARCACHE0 |
| TCELL81:IMUX.IMUX13 | PS.SAXIGP1ARCACHE1 |
| TCELL81:IMUX.IMUX14 | PS.SAXIGP1ARCACHE2 |
| TCELL81:IMUX.IMUX15 | PS.SAXIGP1ARCACHE3 |
| TCELL81:IMUX.IMUX16 | PS.SAXIGP1ARPROT0 |
| TCELL81:IMUX.IMUX17 | PS.SAXIGP1ARPROT1 |
| TCELL81:IMUX.IMUX18 | PS.SAXIGP1ARPROT2 |
| TCELL81:OUT0.TMIN | PS.EMIOGPIOO32 |
| TCELL81:OUT1.TMIN | PS.EMIOGPIOO33 |
| TCELL81:OUT2.TMIN | PS.EMIOGPIOO34 |
| TCELL81:OUT3.TMIN | PS.EMIOGPIOO35 |
| TCELL81:OUT4.TMIN | PS.EMIOGPIOTN32 |
| TCELL81:OUT5.TMIN | PS.EMIOGPIOTN33 |
| TCELL81:OUT6.TMIN | PS.EMIOGPIOTN34 |
| TCELL81:OUT7.TMIN | PS.EMIOGPIOTN35 |
| TCELL81:OUT8.TMIN | PS.SAXIGP1RID0 |
| TCELL81:OUT9.TMIN | PS.SAXIGP1RID1 |
| TCELL81:OUT10.TMIN | PS.SAXIGP1RID2 |
| TCELL81:OUT11.TMIN | PS.SAXIGP1RID3 |
| TCELL81:OUT12.TMIN | PS.SAXIGP1RDATA0 |
| TCELL81:OUT13.TMIN | PS.SAXIGP1RDATA1 |
| TCELL81:OUT14.TMIN | PS.SAXIGP1RDATA2 |
| TCELL81:OUT15.TMIN | PS.SAXIGP1RDATA3 |
| TCELL82:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG12 |
| TCELL82:IMUX.IMUX0 | PS.SAXIGP1AWADDR4 |
| TCELL82:IMUX.IMUX1 | PS.SAXIGP1AWADDR5 |
| TCELL82:IMUX.IMUX2 | PS.SAXIGP1AWADDR6 |
| TCELL82:IMUX.IMUX3 | PS.SAXIGP1AWADDR7 |
| TCELL82:IMUX.IMUX4 | PS.SAXIGP1WDATA4 |
| TCELL82:IMUX.IMUX5 | PS.SAXIGP1WDATA5 |
| TCELL82:IMUX.IMUX6 | PS.SAXIGP1WDATA6 |
| TCELL82:IMUX.IMUX7 | PS.SAXIGP1WDATA7 |
| TCELL82:IMUX.IMUX8 | PS.SAXIGP1WLAST |
| TCELL82:IMUX.IMUX9 | PS.SAXIGP1ARADDR4 |
| TCELL82:IMUX.IMUX10 | PS.SAXIGP1ARADDR5 |
| TCELL82:IMUX.IMUX11 | PS.SAXIGP1ARADDR6 |
| TCELL82:IMUX.IMUX12 | PS.SAXIGP1ARADDR7 |
| TCELL82:IMUX.IMUX13 | PS.SAXIGP1ARBURST0 |
| TCELL82:IMUX.IMUX14 | PS.SAXIGP1ARBURST1 |
| TCELL82:IMUX.IMUX15 | PS.SAXIGP1ARLOCK0 |
| TCELL82:IMUX.IMUX16 | PS.SAXIGP1ARLOCK1 |
| TCELL82:IMUX.IMUX17 | PS.SAXIGP1ARQOS0 |
| TCELL82:IMUX.IMUX18 | PS.SAXIGP1ARQOS1 |
| TCELL82:IMUX.IMUX19 | PS.SAXIGP1ARQOS2 |
| TCELL82:IMUX.IMUX20 | PS.SAXIGP1ARQOS3 |
| TCELL82:OUT0.TMIN | PS.EMIOGPIOO36 |
| TCELL82:OUT1.TMIN | PS.EMIOGPIOO37 |
| TCELL82:OUT2.TMIN | PS.EMIOGPIOO38 |
| TCELL82:OUT3.TMIN | PS.EMIOGPIOO39 |
| TCELL82:OUT4.TMIN | PS.EMIOGPIOTN36 |
| TCELL82:OUT5.TMIN | PS.EMIOGPIOTN37 |
| TCELL82:OUT6.TMIN | PS.EMIOGPIOTN38 |
| TCELL82:OUT7.TMIN | PS.EMIOGPIOTN39 |
| TCELL82:OUT8.TMIN | PS.SAXIGP1RID4 |
| TCELL82:OUT9.TMIN | PS.SAXIGP1RID5 |
| TCELL82:OUT10.TMIN | PS.SAXIGP1RDATA4 |
| TCELL82:OUT11.TMIN | PS.SAXIGP1RDATA5 |
| TCELL82:OUT12.TMIN | PS.SAXIGP1RDATA6 |
| TCELL82:OUT13.TMIN | PS.SAXIGP1RDATA7 |
| TCELL82:OUT14.TMIN | PS.SAXIGP1RLAST |
| TCELL83:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG13 |
| TCELL83:IMUX.IMUX0 | PS.SAXIGP1AWADDR8 |
| TCELL83:IMUX.IMUX1 | PS.SAXIGP1AWADDR9 |
| TCELL83:IMUX.IMUX2 | PS.SAXIGP1AWADDR10 |
| TCELL83:IMUX.IMUX3 | PS.SAXIGP1AWADDR11 |
| TCELL83:IMUX.IMUX4 | PS.SAXIGP1WDATA8 |
| TCELL83:IMUX.IMUX5 | PS.SAXIGP1WDATA9 |
| TCELL83:IMUX.IMUX6 | PS.SAXIGP1WDATA10 |
| TCELL83:IMUX.IMUX7 | PS.SAXIGP1WDATA11 |
| TCELL83:IMUX.IMUX8 | PS.SAXIGP1ARID0 |
| TCELL83:IMUX.IMUX9 | PS.SAXIGP1ARID1 |
| TCELL83:IMUX.IMUX10 | PS.SAXIGP1ARID2 |
| TCELL83:IMUX.IMUX11 | PS.SAXIGP1ARID3 |
| TCELL83:IMUX.IMUX12 | PS.SAXIGP1ARADDR8 |
| TCELL83:IMUX.IMUX13 | PS.SAXIGP1ARADDR9 |
| TCELL83:IMUX.IMUX14 | PS.SAXIGP1ARADDR10 |
| TCELL83:IMUX.IMUX15 | PS.SAXIGP1ARADDR11 |
| TCELL83:IMUX.IMUX16 | PS.SAXIGP1ARLEN0 |
| TCELL83:IMUX.IMUX17 | PS.SAXIGP1ARLEN1 |
| TCELL83:IMUX.IMUX18 | PS.SAXIGP1ARLEN2 |
| TCELL83:IMUX.IMUX19 | PS.SAXIGP1ARLEN3 |
| TCELL83:IMUX.IMUX20 | PS.SAXIGP1ARSIZE0 |
| TCELL83:IMUX.IMUX21 | PS.SAXIGP1ARSIZE1 |
| TCELL83:OUT0.TMIN | PS.EMIOGPIOO40 |
| TCELL83:OUT1.TMIN | PS.EMIOGPIOO41 |
| TCELL83:OUT2.TMIN | PS.EMIOGPIOO42 |
| TCELL83:OUT3.TMIN | PS.EMIOGPIOO43 |
| TCELL83:OUT4.TMIN | PS.EMIOGPIOTN40 |
| TCELL83:OUT5.TMIN | PS.EMIOGPIOTN41 |
| TCELL83:OUT6.TMIN | PS.EMIOGPIOTN42 |
| TCELL83:OUT7.TMIN | PS.EMIOGPIOTN43 |
| TCELL83:OUT8.TMIN | PS.SAXIGP1RDATA8 |
| TCELL83:OUT9.TMIN | PS.SAXIGP1RDATA9 |
| TCELL83:OUT10.TMIN | PS.SAXIGP1RDATA10 |
| TCELL83:OUT11.TMIN | PS.SAXIGP1RDATA11 |
| TCELL83:OUT12.TMIN | PS.SAXIGP1RRESP0 |
| TCELL83:OUT13.TMIN | PS.SAXIGP1RRESP1 |
| TCELL84:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG14 |
| TCELL84:IMUX.IMUX0 | PS.SAXIGP1AWADDR12 |
| TCELL84:IMUX.IMUX1 | PS.SAXIGP1AWADDR13 |
| TCELL84:IMUX.IMUX2 | PS.SAXIGP1AWADDR14 |
| TCELL84:IMUX.IMUX3 | PS.SAXIGP1AWADDR15 |
| TCELL84:IMUX.IMUX4 | PS.SAXIGP1AWPROT0 |
| TCELL84:IMUX.IMUX5 | PS.SAXIGP1AWPROT1 |
| TCELL84:IMUX.IMUX6 | PS.SAXIGP1AWPROT2 |
| TCELL84:IMUX.IMUX7 | PS.SAXIGP1WID0 |
| TCELL84:IMUX.IMUX8 | PS.SAXIGP1WID1 |
| TCELL84:IMUX.IMUX9 | PS.SAXIGP1WDATA12 |
| TCELL84:IMUX.IMUX10 | PS.SAXIGP1WDATA13 |
| TCELL84:IMUX.IMUX11 | PS.SAXIGP1WDATA14 |
| TCELL84:IMUX.IMUX12 | PS.SAXIGP1WDATA15 |
| TCELL84:IMUX.IMUX13 | PS.SAXIGP1ARID4 |
| TCELL84:IMUX.IMUX14 | PS.SAXIGP1ARID5 |
| TCELL84:IMUX.IMUX15 | PS.SAXIGP1ARADDR12 |
| TCELL84:IMUX.IMUX16 | PS.SAXIGP1ARADDR13 |
| TCELL84:IMUX.IMUX17 | PS.SAXIGP1ARADDR14 |
| TCELL84:IMUX.IMUX18 | PS.SAXIGP1ARADDR15 |
| TCELL84:IMUX.IMUX19 | PS.SAXIGP1ARVALID |
| TCELL84:IMUX.IMUX20 | PS.SAXIGP1RREADY |
| TCELL84:OUT0.TMIN | PS.EMIOGPIOO44 |
| TCELL84:OUT1.TMIN | PS.EMIOGPIOO45 |
| TCELL84:OUT2.TMIN | PS.EMIOGPIOO46 |
| TCELL84:OUT3.TMIN | PS.EMIOGPIOO47 |
| TCELL84:OUT4.TMIN | PS.EMIOGPIOTN44 |
| TCELL84:OUT5.TMIN | PS.EMIOGPIOTN45 |
| TCELL84:OUT6.TMIN | PS.EMIOGPIOTN46 |
| TCELL84:OUT7.TMIN | PS.EMIOGPIOTN47 |
| TCELL84:OUT8.TMIN | PS.SAXIGP1ARREADY |
| TCELL84:OUT9.TMIN | PS.SAXIGP1RDATA12 |
| TCELL84:OUT10.TMIN | PS.SAXIGP1RDATA13 |
| TCELL84:OUT11.TMIN | PS.SAXIGP1RDATA14 |
| TCELL84:OUT12.TMIN | PS.SAXIGP1RDATA15 |
| TCELL84:OUT13.TMIN | PS.SAXIGP1RVALID |
| TCELL85:IMUX.CLK0 | PS.SAXIGP1ACLK |
| TCELL85:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG15 |
| TCELL85:IMUX.IMUX0 | PS.SAXIGP1AWADDR16 |
| TCELL85:IMUX.IMUX1 | PS.SAXIGP1AWADDR17 |
| TCELL85:IMUX.IMUX2 | PS.SAXIGP1AWADDR18 |
| TCELL85:IMUX.IMUX3 | PS.SAXIGP1AWADDR19 |
| TCELL85:IMUX.IMUX4 | PS.SAXIGP1AWCACHE0 |
| TCELL85:IMUX.IMUX5 | PS.SAXIGP1AWCACHE1 |
| TCELL85:IMUX.IMUX6 | PS.SAXIGP1AWVALID |
| TCELL85:IMUX.IMUX7 | PS.SAXIGP1WID2 |
| TCELL85:IMUX.IMUX8 | PS.SAXIGP1WID3 |
| TCELL85:IMUX.IMUX9 | PS.SAXIGP1WID4 |
| TCELL85:IMUX.IMUX10 | PS.SAXIGP1WID5 |
| TCELL85:IMUX.IMUX11 | PS.SAXIGP1WDATA16 |
| TCELL85:IMUX.IMUX12 | PS.SAXIGP1WDATA17 |
| TCELL85:IMUX.IMUX13 | PS.SAXIGP1WDATA18 |
| TCELL85:IMUX.IMUX14 | PS.SAXIGP1WDATA19 |
| TCELL85:IMUX.IMUX15 | PS.SAXIGP1WVALID |
| TCELL85:IMUX.IMUX16 | PS.SAXIGP1ARADDR16 |
| TCELL85:IMUX.IMUX17 | PS.SAXIGP1ARADDR17 |
| TCELL85:IMUX.IMUX18 | PS.SAXIGP1ARADDR18 |
| TCELL85:IMUX.IMUX19 | PS.SAXIGP1ARADDR19 |
| TCELL85:OUT0.TMIN | PS.EMIOGPIOO48 |
| TCELL85:OUT1.TMIN | PS.EMIOGPIOO49 |
| TCELL85:OUT2.TMIN | PS.EMIOGPIOO50 |
| TCELL85:OUT3.TMIN | PS.EMIOGPIOO51 |
| TCELL85:OUT4.TMIN | PS.EMIOGPIOTN48 |
| TCELL85:OUT5.TMIN | PS.EMIOGPIOTN49 |
| TCELL85:OUT6.TMIN | PS.EMIOGPIOTN50 |
| TCELL85:OUT7.TMIN | PS.EMIOGPIOTN51 |
| TCELL85:OUT8.TMIN | PS.SAXIGP1ARESETN |
| TCELL85:OUT9.TMIN | PS.SAXIGP1AWREADY |
| TCELL85:OUT10.TMIN | PS.SAXIGP1WREADY |
| TCELL85:OUT11.TMIN | PS.SAXIGP1RDATA16 |
| TCELL85:OUT12.TMIN | PS.SAXIGP1RDATA17 |
| TCELL85:OUT13.TMIN | PS.SAXIGP1RDATA18 |
| TCELL85:OUT14.TMIN | PS.SAXIGP1RDATA19 |
| TCELL86:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG16 |
| TCELL86:IMUX.IMUX0 | PS.SAXIGP1AWADDR20 |
| TCELL86:IMUX.IMUX1 | PS.SAXIGP1AWADDR21 |
| TCELL86:IMUX.IMUX2 | PS.SAXIGP1AWADDR22 |
| TCELL86:IMUX.IMUX3 | PS.SAXIGP1AWADDR23 |
| TCELL86:IMUX.IMUX4 | PS.SAXIGP1AWBURST0 |
| TCELL86:IMUX.IMUX5 | PS.SAXIGP1AWBURST1 |
| TCELL86:IMUX.IMUX6 | PS.SAXIGP1AWLOCK0 |
| TCELL86:IMUX.IMUX7 | PS.SAXIGP1AWLOCK1 |
| TCELL86:IMUX.IMUX8 | PS.SAXIGP1AWCACHE2 |
| TCELL86:IMUX.IMUX9 | PS.SAXIGP1AWCACHE3 |
| TCELL86:IMUX.IMUX10 | PS.SAXIGP1WDATA20 |
| TCELL86:IMUX.IMUX11 | PS.SAXIGP1WDATA21 |
| TCELL86:IMUX.IMUX12 | PS.SAXIGP1WDATA22 |
| TCELL86:IMUX.IMUX13 | PS.SAXIGP1WDATA23 |
| TCELL86:IMUX.IMUX14 | PS.SAXIGP1BREADY |
| TCELL86:IMUX.IMUX15 | PS.SAXIGP1ARADDR20 |
| TCELL86:IMUX.IMUX16 | PS.SAXIGP1ARADDR21 |
| TCELL86:IMUX.IMUX17 | PS.SAXIGP1ARADDR22 |
| TCELL86:IMUX.IMUX18 | PS.SAXIGP1ARADDR23 |
| TCELL86:IMUX.IMUX19 | PS.SAXIGP1AWQOS0 |
| TCELL86:IMUX.IMUX20 | PS.SAXIGP1AWQOS1 |
| TCELL86:IMUX.IMUX21 | PS.SAXIGP1AWQOS2 |
| TCELL86:IMUX.IMUX22 | PS.SAXIGP1AWQOS3 |
| TCELL86:OUT0.TMIN | PS.EMIOGPIOO52 |
| TCELL86:OUT1.TMIN | PS.EMIOGPIOO53 |
| TCELL86:OUT2.TMIN | PS.EMIOGPIOO54 |
| TCELL86:OUT3.TMIN | PS.EMIOGPIOO55 |
| TCELL86:OUT4.TMIN | PS.EMIOGPIOTN52 |
| TCELL86:OUT5.TMIN | PS.EMIOGPIOTN53 |
| TCELL86:OUT6.TMIN | PS.EMIOGPIOTN54 |
| TCELL86:OUT7.TMIN | PS.EMIOGPIOTN55 |
| TCELL86:OUT8.TMIN | PS.SAXIGP1BVALID |
| TCELL86:OUT9.TMIN | PS.SAXIGP1RDATA20 |
| TCELL86:OUT10.TMIN | PS.SAXIGP1RDATA21 |
| TCELL86:OUT11.TMIN | PS.SAXIGP1RDATA22 |
| TCELL86:OUT12.TMIN | PS.SAXIGP1RDATA23 |
| TCELL87:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG17 |
| TCELL87:IMUX.IMUX0 | PS.SAXIGP1AWID0 |
| TCELL87:IMUX.IMUX1 | PS.SAXIGP1AWID1 |
| TCELL87:IMUX.IMUX2 | PS.SAXIGP1AWADDR24 |
| TCELL87:IMUX.IMUX3 | PS.SAXIGP1AWADDR25 |
| TCELL87:IMUX.IMUX4 | PS.SAXIGP1AWADDR26 |
| TCELL87:IMUX.IMUX5 | PS.SAXIGP1AWADDR27 |
| TCELL87:IMUX.IMUX6 | PS.SAXIGP1AWSIZE0 |
| TCELL87:IMUX.IMUX7 | PS.SAXIGP1AWSIZE1 |
| TCELL87:IMUX.IMUX8 | PS.SAXIGP1WDATA24 |
| TCELL87:IMUX.IMUX9 | PS.SAXIGP1WDATA25 |
| TCELL87:IMUX.IMUX10 | PS.SAXIGP1WDATA26 |
| TCELL87:IMUX.IMUX11 | PS.SAXIGP1WDATA27 |
| TCELL87:IMUX.IMUX12 | PS.SAXIGP1WSTRB0 |
| TCELL87:IMUX.IMUX13 | PS.SAXIGP1WSTRB1 |
| TCELL87:IMUX.IMUX14 | PS.SAXIGP1WSTRB2 |
| TCELL87:IMUX.IMUX15 | PS.SAXIGP1WSTRB3 |
| TCELL87:IMUX.IMUX16 | PS.SAXIGP1ARADDR24 |
| TCELL87:IMUX.IMUX17 | PS.SAXIGP1ARADDR25 |
| TCELL87:IMUX.IMUX18 | PS.SAXIGP1ARADDR26 |
| TCELL87:IMUX.IMUX19 | PS.SAXIGP1ARADDR27 |
| TCELL87:OUT0.TMIN | PS.EMIOGPIOO56 |
| TCELL87:OUT1.TMIN | PS.EMIOGPIOO57 |
| TCELL87:OUT2.TMIN | PS.EMIOGPIOO58 |
| TCELL87:OUT3.TMIN | PS.EMIOGPIOO59 |
| TCELL87:OUT4.TMIN | PS.EMIOGPIOTN56 |
| TCELL87:OUT5.TMIN | PS.EMIOGPIOTN57 |
| TCELL87:OUT6.TMIN | PS.EMIOGPIOTN58 |
| TCELL87:OUT7.TMIN | PS.EMIOGPIOTN59 |
| TCELL87:OUT8.TMIN | PS.SAXIGP1BID0 |
| TCELL87:OUT9.TMIN | PS.SAXIGP1BID1 |
| TCELL87:OUT10.TMIN | PS.SAXIGP1BRESP0 |
| TCELL87:OUT11.TMIN | PS.SAXIGP1BRESP1 |
| TCELL87:OUT12.TMIN | PS.SAXIGP1RDATA24 |
| TCELL87:OUT13.TMIN | PS.SAXIGP1RDATA25 |
| TCELL87:OUT14.TMIN | PS.SAXIGP1RDATA26 |
| TCELL87:OUT15.TMIN | PS.SAXIGP1RDATA27 |
| TCELL88:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG18 |
| TCELL88:IMUX.IMUX0 | PS.SAXIGP1AWID2 |
| TCELL88:IMUX.IMUX1 | PS.SAXIGP1AWID3 |
| TCELL88:IMUX.IMUX2 | PS.SAXIGP1AWID4 |
| TCELL88:IMUX.IMUX3 | PS.SAXIGP1AWID5 |
| TCELL88:IMUX.IMUX4 | PS.SAXIGP1AWADDR28 |
| TCELL88:IMUX.IMUX5 | PS.SAXIGP1AWADDR29 |
| TCELL88:IMUX.IMUX6 | PS.SAXIGP1AWADDR30 |
| TCELL88:IMUX.IMUX7 | PS.SAXIGP1AWADDR31 |
| TCELL88:IMUX.IMUX8 | PS.SAXIGP1AWLEN0 |
| TCELL88:IMUX.IMUX9 | PS.SAXIGP1AWLEN1 |
| TCELL88:IMUX.IMUX10 | PS.SAXIGP1AWLEN2 |
| TCELL88:IMUX.IMUX11 | PS.SAXIGP1AWLEN3 |
| TCELL88:IMUX.IMUX12 | PS.SAXIGP1WDATA28 |
| TCELL88:IMUX.IMUX13 | PS.SAXIGP1WDATA29 |
| TCELL88:IMUX.IMUX14 | PS.SAXIGP1WDATA30 |
| TCELL88:IMUX.IMUX15 | PS.SAXIGP1WDATA31 |
| TCELL88:IMUX.IMUX16 | PS.SAXIGP1ARADDR28 |
| TCELL88:IMUX.IMUX17 | PS.SAXIGP1ARADDR29 |
| TCELL88:IMUX.IMUX18 | PS.SAXIGP1ARADDR30 |
| TCELL88:IMUX.IMUX19 | PS.SAXIGP1ARADDR31 |
| TCELL88:OUT0.TMIN | PS.EMIOGPIOO60 |
| TCELL88:OUT1.TMIN | PS.EMIOGPIOO61 |
| TCELL88:OUT2.TMIN | PS.EMIOGPIOO62 |
| TCELL88:OUT3.TMIN | PS.EMIOGPIOO63 |
| TCELL88:OUT4.TMIN | PS.EMIOGPIOTN60 |
| TCELL88:OUT5.TMIN | PS.EMIOGPIOTN61 |
| TCELL88:OUT6.TMIN | PS.EMIOGPIOTN62 |
| TCELL88:OUT7.TMIN | PS.EMIOGPIOTN63 |
| TCELL88:OUT8.TMIN | PS.SAXIGP1BID2 |
| TCELL88:OUT9.TMIN | PS.SAXIGP1BID3 |
| TCELL88:OUT10.TMIN | PS.SAXIGP1BID4 |
| TCELL88:OUT11.TMIN | PS.SAXIGP1BID5 |
| TCELL88:OUT12.TMIN | PS.SAXIGP1RDATA28 |
| TCELL88:OUT13.TMIN | PS.SAXIGP1RDATA29 |
| TCELL88:OUT14.TMIN | PS.SAXIGP1RDATA30 |
| TCELL88:OUT15.TMIN | PS.SAXIGP1RDATA31 |
| TCELL89:IMUX.CLK0 | PS.EMIOTRACECLK |
| TCELL89:IMUX.CLK1 | PS.TESTPLLREFCLKCPU |
| TCELL89:IMUX.IMUX0 | PS.EMIOTTC0CLKI0 |
| TCELL89:IMUX.IMUX1 | PS.EMIOTTC0CLKI1 |
| TCELL89:IMUX.IMUX2 | PS.EMIOTTC0CLKI2 |
| TCELL89:IMUX.IMUX3 | PS.EMIOWDTCLKI |
| TCELL89:IMUX.IMUX4 | PS.EMIOI2C0SCLI |
| TCELL89:IMUX.IMUX5 | PS.EMIOI2C0SDAI |
| TCELL89:IMUX.IMUX6 | PS.EMIOCAN0PHYRX |
| TCELL89:IMUX.IMUX7 | PS.EMIOUART1RX |
| TCELL89:IMUX.IMUX8 | PS.EMIOUART1CTSN |
| TCELL89:IMUX.IMUX9 | PS.EMIOUART1DSRN |
| TCELL89:IMUX.IMUX10 | PS.EMIOUART1DCDN |
| TCELL89:IMUX.IMUX11 | PS.EMIOUART1RIN |
| TCELL89:IMUX.IMUX12 | PS.EMIOSRAMINTIN |
| TCELL89:OUT0.TMIN | PS.EMIOTTC0WAVEO0 |
| TCELL89:OUT1.TMIN | PS.EMIOTTC0WAVEO1 |
| TCELL89:OUT2.TMIN | PS.EMIOTTC0WAVEO2 |
| TCELL89:OUT3.TMIN | PS.EMIOWDTRSTO |
| TCELL89:OUT4.TMIN | PS.EMIOI2C0SCLO |
| TCELL89:OUT5.TMIN | PS.EMIOI2C0SCLTN |
| TCELL89:OUT6.TMIN | PS.EMIOI2C0SDAO |
| TCELL89:OUT7.TMIN | PS.EMIOI2C0SDATN |
| TCELL89:OUT8.TMIN | PS.EMIOCAN0PHYTX |
| TCELL89:OUT9.TMIN | PS.EMIOUART1TX |
| TCELL89:OUT10.TMIN | PS.EMIOUART1RTSN |
| TCELL89:OUT11.TMIN | PS.EMIOUART1DTRN |
| TCELL89:OUT12.TMIN | PS.EMIOTRACEDATA0 |
| TCELL89:OUT13.TMIN | PS.EMIOTRACEDATA1 |
| TCELL89:OUT14.TMIN | PS.EMIOTRACEDATA2 |
| TCELL89:OUT15.TMIN | PS.EMIOTRACEDATA3 |
| TCELL89:OUT21.TMIN | PS.TESTPLLCONFIGREADY2 |
| TCELL89:OUT22.TMIN | PS.TESTPLLCONFIGREADY1 |
| TCELL89:OUT23.TMIN | PS.TESTPLLCONFIGREADY0 |
| TCELL90:IMUX.CLK1 | PS.TESTPLLREFCLKDDR |
| TCELL90:IMUX.IMUX0 | PS.EMIOTTC1CLKI0 |
| TCELL90:IMUX.IMUX1 | PS.EMIOTTC1CLKI1 |
| TCELL90:IMUX.IMUX2 | PS.EMIOTTC1CLKI2 |
| TCELL90:IMUX.IMUX3 | PS.EMIOI2C1SCLI |
| TCELL90:IMUX.IMUX4 | PS.EMIOI2C1SDAI |
| TCELL90:IMUX.IMUX5 | PS.EMIOCAN1PHYRX |
| TCELL90:IMUX.IMUX6 | PS.EMIOUART0RX |
| TCELL90:IMUX.IMUX7 | PS.EMIOUART0CTSN |
| TCELL90:IMUX.IMUX8 | PS.EMIOUART0DSRN |
| TCELL90:IMUX.IMUX9 | PS.EMIOUART0DCDN |
| TCELL90:IMUX.IMUX10 | PS.EMIOUART0RIN |
| TCELL90:IMUX.IMUX44 | PS.TESTDIVIDERUPDATETOG |
| TCELL90:IMUX.IMUX45 | PS.TESTPLLCONFIGUPDATE2 |
| TCELL90:IMUX.IMUX46 | PS.TESTPLLCONFIGUPDATE1 |
| TCELL90:IMUX.IMUX47 | PS.TESTPLLCONFIGUPDATE0 |
| TCELL90:OUT0.TMIN | PS.EMIOTTC1WAVEO0 |
| TCELL90:OUT1.TMIN | PS.EMIOTTC1WAVEO1 |
| TCELL90:OUT2.TMIN | PS.EMIOTTC1WAVEO2 |
| TCELL90:OUT3.TMIN | PS.EMIOI2C1SCLO |
| TCELL90:OUT4.TMIN | PS.EMIOI2C1SCLTN |
| TCELL90:OUT5.TMIN | PS.EMIOI2C1SDAO |
| TCELL90:OUT6.TMIN | PS.EMIOI2C1SDATN |
| TCELL90:OUT7.TMIN | PS.EMIOCAN1PHYTX |
| TCELL90:OUT8.TMIN | PS.EMIOUART0TX |
| TCELL90:OUT9.TMIN | PS.EMIOUART0RTSN |
| TCELL90:OUT10.TMIN | PS.EMIOUART0DTRN |
| TCELL90:OUT11.TMIN | PS.EMIOTRACECTL |
| TCELL90:OUT12.TMIN | PS.EMIOTRACEDATA4 |
| TCELL90:OUT13.TMIN | PS.EMIOTRACEDATA5 |
| TCELL90:OUT14.TMIN | PS.EMIOTRACEDATA6 |
| TCELL90:OUT15.TMIN | PS.EMIOTRACEDATA7 |
| TCELL90:OUT20.TMIN | PS.TESTDIVCLKOUT3 |
| TCELL90:OUT21.TMIN | PS.TESTDIVCLKOUT2 |
| TCELL90:OUT22.TMIN | PS.TESTDIVCLKOUT1 |
| TCELL90:OUT23.TMIN | PS.TESTDIVCLKOUT0 |
| TCELL91:IMUX.CLK1 | PS.TESTPLLREFCLKIOU |
| TCELL91:IMUX.IMUX45 | PS.TESTPLLREFCLKENN2 |
| TCELL91:IMUX.IMUX46 | PS.TESTPLLREFCLKENN1 |
| TCELL91:IMUX.IMUX47 | PS.TESTPLLREFCLKENN0 |
| TCELL91:OUT0.TMIN | PS.EMIOSDIO0DATAO0 |
| TCELL91:OUT1.TMIN | PS.EMIOSDIO0DATAO1 |
| TCELL91:OUT2.TMIN | PS.EMIOSDIO0DATAO2 |
| TCELL91:OUT3.TMIN | PS.EMIOSDIO0DATAO3 |
| TCELL91:OUT4.TMIN | PS.EMIOSDIO0BUSVOLT0 |
| TCELL91:OUT5.TMIN | PS.EMIOTRACEDATA8 |
| TCELL91:OUT6.TMIN | PS.EMIOTRACEDATA9 |
| TCELL91:OUT7.TMIN | PS.EMIOTRACEDATA10 |
| TCELL91:OUT8.TMIN | PS.EMIOTRACEDATA11 |
| TCELL91:OUT20.TMIN | PS.TESTDIVCLKOUT7 |
| TCELL91:OUT21.TMIN | PS.TESTDIVCLKOUT6 |
| TCELL91:OUT22.TMIN | PS.TESTDIVCLKOUT5 |
| TCELL91:OUT23.TMIN | PS.TESTDIVCLKOUT4 |
| TCELL92:IMUX.CLK0 | PS.EMIOSDIO0CLKFB |
| TCELL92:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG19 |
| TCELL92:OUT0.TMIN | PS.EMIOSPI0SSON0 |
| TCELL92:OUT1.TMIN | PS.EMIOSPI0SSON1 |
| TCELL92:OUT2.TMIN | PS.EMIOSPI0SSON2 |
| TCELL92:OUT3.TMIN | PS.EMIOSDIO0LED |
| TCELL92:OUT4.TMIN | PS.EMIOSDIO0BUSPOW |
| TCELL92:OUT5.TMIN | PS.EMIOTRACEDATA12 |
| TCELL92:OUT6.TMIN | PS.EMIOTRACEDATA13 |
| TCELL92:OUT7.TMIN | PS.EMIOTRACEDATA14 |
| TCELL92:OUT8.TMIN | PS.EMIOTRACEDATA15 |
| TCELL92:OUT20.TMIN | PS.TESTDIVCLKOUT11 |
| TCELL92:OUT21.TMIN | PS.TESTDIVCLKOUT10 |
| TCELL92:OUT22.TMIN | PS.TESTDIVCLKOUT9 |
| TCELL92:OUT23.TMIN | PS.TESTDIVCLKOUT8 |
| TCELL93:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG20 |
| TCELL93:IMUX.IMUX0 | PS.EMIOSPI0SI |
| TCELL93:IMUX.IMUX1 | PS.EMIOSPI0SSIN |
| TCELL93:IMUX.IMUX2 | PS.EMIOSDIO0DATAI0 |
| TCELL93:IMUX.IMUX3 | PS.EMIOSDIO0DATAI1 |
| TCELL93:IMUX.IMUX4 | PS.EMIOSDIO0DATAI2 |
| TCELL93:IMUX.IMUX5 | PS.EMIOSDIO0DATAI3 |
| TCELL93:OUT0.TMIN | PS.EMIOSPI0SO |
| TCELL93:OUT1.TMIN | PS.EMIOSPI0STN |
| TCELL93:OUT2.TMIN | PS.EMIOSPI0SSNTN |
| TCELL93:OUT3.TMIN | PS.EMIOSDIO0DATATN0 |
| TCELL93:OUT4.TMIN | PS.EMIOSDIO0DATATN1 |
| TCELL93:OUT5.TMIN | PS.EMIOSDIO0BUSVOLT1 |
| TCELL93:OUT6.TMIN | PS.EMIOTRACEDATA16 |
| TCELL93:OUT7.TMIN | PS.EMIOTRACEDATA17 |
| TCELL93:OUT8.TMIN | PS.EMIOTRACEDATA18 |
| TCELL93:OUT9.TMIN | PS.EMIOTRACEDATA19 |
| TCELL93:OUT10.TMIN | PS.EMIOUSB1PORTINDCTL0 |
| TCELL93:OUT20.TMIN | PS.TESTDIVCLKOUT15 |
| TCELL93:OUT21.TMIN | PS.TESTDIVCLKOUT14 |
| TCELL93:OUT22.TMIN | PS.TESTDIVCLKOUT13 |
| TCELL93:OUT23.TMIN | PS.TESTDIVCLKOUT12 |
| TCELL94:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG21 |
| TCELL94:IMUX.IMUX0 | PS.EMIOSPI0SCLKI |
| TCELL94:IMUX.IMUX1 | PS.EMIOSPI0MI |
| TCELL94:IMUX.IMUX2 | PS.EMIOSDIO0CMDI |
| TCELL94:IMUX.IMUX3 | PS.EMIOSDIO0CDN |
| TCELL94:IMUX.IMUX4 | PS.EMIOSDIO0WP |
| TCELL94:IMUX.IMUX5 | PS.EMIOUSB1VBUSPWRFAULT |
| TCELL94:IMUX.IMUX47 | PS.TESTPLLFBTESTN0 |
| TCELL94:OUT0.TMIN | PS.EMIOSPI0SCLKO |
| TCELL94:OUT1.TMIN | PS.EMIOSPI0SCLKTN |
| TCELL94:OUT2.TMIN | PS.EMIOSPI0MO |
| TCELL94:OUT3.TMIN | PS.EMIOSPI0MOTN |
| TCELL94:OUT4.TMIN | PS.EMIOSDIO0CLK |
| TCELL94:OUT5.TMIN | PS.EMIOSDIO0CMDO |
| TCELL94:OUT6.TMIN | PS.EMIOSDIO0CMDTN |
| TCELL94:OUT7.TMIN | PS.EMIOSDIO0DATATN2 |
| TCELL94:OUT8.TMIN | PS.EMIOSDIO0DATATN3 |
| TCELL94:OUT9.TMIN | PS.EMIOSDIO0BUSVOLT2 |
| TCELL94:OUT10.TMIN | PS.EMIOTRACEDATA20 |
| TCELL94:OUT11.TMIN | PS.EMIOTRACEDATA21 |
| TCELL94:OUT12.TMIN | PS.EMIOUSB1VBUSPWRSELECT |
| TCELL94:OUT20.TMIN | PS.TESTDIVCLKOUT19 |
| TCELL94:OUT21.TMIN | PS.TESTDIVCLKOUT18 |
| TCELL94:OUT22.TMIN | PS.TESTDIVCLKOUT17 |
| TCELL94:OUT23.TMIN | PS.TESTDIVCLKOUT16 |
| TCELL95:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG22 |
| TCELL95:IMUX.IMUX45 | PS.TESTPLLFBTESTN2 |
| TCELL95:IMUX.IMUX46 | PS.TESTPLLFBTESTN1 |
| TCELL95:IMUX.IMUX47 | PS.TESTDIVCLKOUTPREOPCGENABLEN |
| TCELL95:OUT0.TMIN | PS.EMIOSDIO1DATAO0 |
| TCELL95:OUT1.TMIN | PS.EMIOSDIO1DATAO1 |
| TCELL95:OUT2.TMIN | PS.EMIOSDIO1DATAO2 |
| TCELL95:OUT3.TMIN | PS.EMIOSDIO1DATAO3 |
| TCELL95:OUT4.TMIN | PS.EMIOSDIO1BUSVOLT0 |
| TCELL95:OUT5.TMIN | PS.EMIOTRACEDATA22 |
| TCELL95:OUT6.TMIN | PS.EMIOTRACEDATA23 |
| TCELL95:OUT7.TMIN | PS.EMIOTRACEDATA24 |
| TCELL95:OUT8.TMIN | PS.EMIOTRACEDATA25 |
| TCELL95:OUT9.TMIN | PS.EMIOUSB1PORTINDCTL1 |
| TCELL95:OUT23.TMIN | PS.TESTDIVCLKOUT20 |
| TCELL96:IMUX.CLK0 | PS.EMIOSDIO1CLKFB |
| TCELL96:IMUX.CLK1 | PS.TESTSCANCLOCKOPCG23 |
| TCELL96:IMUX.IMUX0 | PS.EMIOPJTAGTMS |
| TCELL96:IMUX.IMUX1 | PS.EMIOPJTAGTDI |
| TCELL96:IMUX.IMUX46 | PS.TESTPLLPOWERDOWNN |
| TCELL96:IMUX.IMUX47 | PS.TESTPLLRESET |
| TCELL96:OUT0.TMIN | PS.EMIOSPI1SSON0 |
| TCELL96:OUT1.TMIN | PS.EMIOSPI1SSON1 |
| TCELL96:OUT2.TMIN | PS.EMIOSPI1SSON2 |
| TCELL96:OUT3.TMIN | PS.EMIOSDIO1LED |
| TCELL96:OUT4.TMIN | PS.EMIOSDIO1BUSPOW |
| TCELL96:OUT5.TMIN | PS.EMIOTRACEDATA26 |
| TCELL96:OUT6.TMIN | PS.EMIOTRACEDATA27 |
| TCELL96:OUT7.TMIN | PS.EMIOTRACEDATA28 |
| TCELL96:OUT8.TMIN | PS.EMIOTRACEDATA29 |
| TCELL96:OUT21.TMIN | PS.TESTPLLLOCK2 |
| TCELL96:OUT22.TMIN | PS.TESTPLLLOCK1 |
| TCELL96:OUT23.TMIN | PS.TESTPLLLOCK0 |
| TCELL97:IMUX.IMUX0 | PS.EMIOSPI1SI |
| TCELL97:IMUX.IMUX1 | PS.EMIOSPI1SSIN |
| TCELL97:IMUX.IMUX2 | PS.EMIOSDIO1DATAI0 |
| TCELL97:IMUX.IMUX3 | PS.EMIOSDIO1DATAI1 |
| TCELL97:IMUX.IMUX4 | PS.EMIOSDIO1DATAI2 |
| TCELL97:IMUX.IMUX5 | PS.EMIOSDIO1DATAI3 |
| TCELL97:IMUX.IMUX45 | PS.TESTAMUXENABLEB |
| TCELL97:IMUX.IMUX46 | PS.TESTBGAMUXSEL1 |
| TCELL97:IMUX.IMUX47 | PS.TESTBGAMUXSEL0 |
| TCELL97:OUT0.TMIN | PS.EMIOSPI1SO |
| TCELL97:OUT1.TMIN | PS.EMIOSPI1STN |
| TCELL97:OUT2.TMIN | PS.EMIOSPI1SSNTN |
| TCELL97:OUT3.TMIN | PS.EMIOSDIO1DATATN0 |
| TCELL97:OUT4.TMIN | PS.EMIOSDIO1DATATN1 |
| TCELL97:OUT5.TMIN | PS.EMIOSDIO1BUSVOLT1 |
| TCELL97:OUT6.TMIN | PS.EMIOTRACEDATA30 |
| TCELL97:OUT7.TMIN | PS.EMIOTRACEDATA31 |
| TCELL97:OUT8.TMIN | PS.EMIOPJTAGTDTN |
| TCELL97:OUT9.TMIN | PS.EMIOPJTAGTDO |
| TCELL97:OUT21.TMIN | PS.TESTPLLFEEDBACKDIV2 |
| TCELL97:OUT22.TMIN | PS.TESTPLLFEEDBACKDIV1 |
| TCELL97:OUT23.TMIN | PS.TESTPLLFEEDBACKDIV0 |
| TCELL98:IMUX.CLK0 | PS.EMIOPJTAGTCK |
| TCELL98:IMUX.IMUX0 | PS.EMIOSPI1SCLKI |
| TCELL98:IMUX.IMUX1 | PS.EMIOSPI1MI |
| TCELL98:IMUX.IMUX2 | PS.EMIOSDIO1CMDI |
| TCELL98:IMUX.IMUX3 | PS.EMIOSDIO1CDN |
| TCELL98:IMUX.IMUX4 | PS.EMIOSDIO1WP |
| TCELL98:IMUX.IMUX5 | PS.EMIOUSB0VBUSPWRFAULT |
| TCELL98:IMUX.IMUX44 | PS.TESTBGAMUXSEL4 |
| TCELL98:IMUX.IMUX45 | PS.TESTBGAMUXSEL3 |
| TCELL98:IMUX.IMUX46 | PS.TESTBGAMUXSEL2 |
| TCELL98:IMUX.IMUX47 | PS.TESTBGPOWERDOWN |
| TCELL98:OUT0.TMIN | PS.EMIOSPI1SCLKO |
| TCELL98:OUT1.TMIN | PS.EMIOSPI1SCLKTN |
| TCELL98:OUT2.TMIN | PS.EMIOSPI1MO |
| TCELL98:OUT3.TMIN | PS.EMIOSPI1MOTN |
| TCELL98:OUT4.TMIN | PS.EMIOSDIO1CLK |
| TCELL98:OUT5.TMIN | PS.EMIOSDIO1CMDO |
| TCELL98:OUT6.TMIN | PS.EMIOSDIO1CMDTN |
| TCELL98:OUT7.TMIN | PS.EMIOSDIO1DATATN2 |
| TCELL98:OUT8.TMIN | PS.EMIOSDIO1DATATN3 |
| TCELL98:OUT9.TMIN | PS.EMIOSDIO1BUSVOLT2 |
| TCELL98:OUT10.TMIN | PS.EMIOUSB0PORTINDCTL0 |
| TCELL98:OUT11.TMIN | PS.EMIOUSB0PORTINDCTL1 |
| TCELL98:OUT12.TMIN | PS.EMIOUSB0VBUSPWRSELECT |