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Input/Output

I/O banks and special functions

Virtex 7 devices have a regular I/O bank structure. There are up to two I/O columns in the device: the left I/O column and the right I/O column. They contain one I/O bank per region (with the exception of regions that are covered up by the PS or GT holes).

There are two genders of I/O banks:

  • HP (high performance) banks, with 1.8V maximum voltage and DCI support
  • HR (high range) banks, with 3.3V maximum voltage and no DCI

In both cases, banks are 50 rows high. They have the following structure:

  • row 0: contains a IO_HP_BOT or IO_HR_BOT tile with a single unpaired IOB
  • rows 1-2, 3-4, 5-6, 7-8, …, 45-46, 47-48: contain IO_HP_PAIR or IO_HR_PAIR tiles, which are two rows high and contain two IOBs each, forming a differential pair; IOB0 is located in the bottom (odd) row and is the “complemented” pin of the pair, while IOB1 is in the top (even) row and is the “true” pin of the pair
  • row 49: contains another IO_HP_TOP or IO_HR_TOP tile
  • HCLK row: contains an HCLK_IO_HP or HCLK_IO_HR tile with common bank circuitry

The single IOB in row 0 is the VRP pin for DCI. The single IOB in row 49 is VRN pin.

The IOB1 pads in rows 24 and 26 are considered “multi-region clock capable”, and have dedicated routing to BUFIO and BUFR of this region and the two adjacent ones. The IOB1 pads in rows 22 and 28 are considered “single-region clock capable”, and can drive BUFIO and BUFR only within their own region.

The IOB0 pads in rows 11 and 37 can be used as VREF.

The IOB1 pads in rows 8, 20, 32, 44 can be used as DQS for byte groups. The byte groups are:

  • rows 1-12: byte group with DQS in row 8
  • rows 13-24: byte group with DQS in row 20
  • rows 25-36: byte group with DQS in row 32
  • rows 37-48: byte group with DQS in row 44

The banks are numbered as follows, where c is the region with the CFG tile (for multi-die packages, the CFG tile of the primary device):

  • the bank in left column region c + i is 14 + i
  • the bank in right column region c + i is 34 + i

In case of multi-die packages, this numbering continues across devices within the package.

In parallel or SPI configuration modes, some I/O pads in banks 14 and 15 are borrowed for configuration use:

  • bank 14 row 1: A[0]/D[16]
  • bank 14 row 2: A[1]/D[17]
  • bank 14 row 3: A[2]/D[18]
  • bank 14 row 4: A[3]/D[19]
  • bank 14 row 5: A[4]/D[20]
  • bank 14 row 6: A[5]/D[21]
  • bank 14 row 7: A[6]/D[22]
  • bank 14 row 9: A[7]/D[23]
  • bank 14 row 10: A[8]/D[24]
  • bank 14 row 11: A[9]/D[25]
  • bank 14 row 12: A[10]/D[26]
  • bank 14 row 13: A[11]/D[27]
  • bank 14 row 14: A[12]/D[28]
  • bank 14 row 15: A[13]/D[29]
  • bank 14 row 16: A[14]/D[30]
  • bank 14 row 17: A[15]/D[31]
  • bank 14 row 18: CSI_B
  • bank 14 row 19: DOUT/CSO_B
  • bank 14 row 20: RDWR_B
  • bank 14 row 29: D[15]
  • bank 14 row 30: D[14]
  • bank 14 row 31: D[13]
  • bank 14 row 33: D[12]
  • bank 14 row 34: D[11]
  • bank 14 row 36: D[10]
  • bank 14 row 36: D[9]
  • bank 14 row 37: D[8]
  • bank 14 row 38: FCS_B
  • bank 14 row 39: D[7]
  • bank 14 row 40: D[6]
  • bank 14 row 41: D[5]
  • bank 14 row 42: D[4]
  • bank 14 row 43: EM_CCLK
  • bank 14 row 44: PUDC_B
  • bank 14 row 45: D[3]
  • bank 14 row 46: D[2]
  • bank 14 row 47: D[1]/DIN
  • bank 14 row 48: D[0]/MOSI
  • bank 15 row 1: RS[0]
  • bank 15 row 2: RS[1]
  • bank 15 row 3: FWE_B
  • bank 15 row 4: FOE_B
  • bank 15 row 5: A[16]
  • bank 15 row 6: A[17]
  • bank 15 row 7: A[18]
  • bank 15 row 9: A[19]
  • bank 15 row 10: A[20]
  • bank 15 row 11: A[21]
  • bank 15 row 12: A[22]
  • bank 15 row 13: A[23]
  • bank 15 row 14: A[24]
  • bank 15 row 15: A[25]
  • bank 15 row 16: A[26]
  • bank 15 row 17: A[27]
  • bank 15 row 18: A[28]
  • bank 15 row 19: ADV_B

The devices with Processing System are not configured by normal means, so the above list is inapplicable. Furthermore, they do not have banks 14 and 15 at all — the place they would occupy is taken up by the PS itself. They do, however, have a special pin in bank 34 instead:

  • bank 34 row 44: PUDC_B

TODO: really, Wanda, how surprised would you be if it turned out that they are configurable by normal means by just substituting banks 34+35 and poking at the reserved mode pins that definitely aren’t M0/M1/M2?

The XADC, if present on the device, can use up to 16 IOB pairs as auxiliary analog differential inputs. The VPx input corresponds to IOB1 and VNx corresponds to IOB0 within the same tile. Depending on device banks present on the device, there are three different arrangements possible:

  • variant LR, used for devices that have both bank 15 and 35
  • variant L, used for devices without bank 35
  • variant R, used for devices without bank 15 (that is, devices with Processing System)

The IOBs for variant LR are:

  • VP0/VN0: bank 15 rows 47-48
  • VP1/VN1: bank 15 rows 43-44
  • VP2/VN2: bank 15 rows 35-36
  • VP3/VN3: bank 15 rows 31-32
  • VP4/VN4: bank 35 rows 47-48
  • VP5/VN5: bank 35 rows 43-44
  • VP6/VN6: bank 35 rows 35-31
  • VP7/VN7: bank 35 rows 31-32
  • VP8/VN8: bank 15 rows 45-46
  • VP9/VN9: bank 15 rows 39-40
  • VP10/VN10: bank 15 rows 33-34
  • VP11/VN11: bank 15 rows 29-30
  • VP12/VN12: bank 35 rows 45-46
  • VP13/VN13: bank 35 rows 39-40
  • VP14/VN14: bank 35 rows 33-34
  • VP15/VN15: bank 35 rows 29-30

The IOBs for variant L are:

  • VP0/VN0: bank 15 rows 47-48
  • VP1/VN1: bank 15 rows 43-44
  • VP2/VN2: bank 15 rows 39-40
  • VP3/VN3: bank 15 rows 33-34
  • VP4/VN4: bank 15 rows 29-30
  • VP5/VN5: bank 15 rows 25-26
  • VP6/VN6: unconnected
  • VP7/VN7: unconnected
  • VP8/VN8: bank 15 rows 45-46
  • VP9/VN9: bank 15 rows 41-42
  • VP10/VN10: bank 15 rows 35-36
  • VP11/VN11: bank 15 rows 31-32
  • VP12/VN12: bank 15 rows 27-28
  • VP13/VN13: unconnected
  • VP14/VN14: unconnected
  • VP15/VN15: unconnected

The IOBs for variant R are:

  • VP0/VN0: bank 35 rows 47-48
  • VP1/VN1: bank 35 rows 43-44
  • VP2/VN2: bank 35 rows 35-36
  • VP3/VN3: bank 35 rows 31-32
  • VP4/VN4: bank 35 rows 21-22
  • VP5/VN5: bank 35 rows 15-16
  • VP6/VN6: bank 35 rows 9-10
  • VP7/VN7: bank 35 rows 5-6
  • VP8/VN8: bank 35 rows 45-46
  • VP9/VN9: bank 35 rows 39-40
  • VP10/VN10: bank 35 rows 33-34
  • VP11/VN11: bank 35 rows 29-30
  • VP12/VN12: bank 35 rows 19-20
  • VP13/VN13: bank 35 rows 13-14
  • VP14/VN14: bank 35 rows 7-8
  • VP15/VN15: bank 35 rows 1-2

The devices also have dedicated configuration bank 0, which has no user I/O and is located in the CFG tile. It has the following pins:

  • CCLK
  • CFGBVS
  • DONE
  • INIT_B
  • M0, M1, M2
  • PROGRAM_B
  • TCK, TDI, TDO, TMS

Tile IO_HP_PAIR

Cells: 2

Switchbox SPEC_INT

virtex7 IO_HP_PAIR switchbox SPEC_INT permanent buffers
DestinationSource
CELL[0].IMUX_SPEC[0]CELL[0].IMUX_IOI_OCLKDIV[0]
CELL[0].IMUX_SPEC[2]CELL[0].IMUX_IOI_OCLK[0]
CELL[1].IMUX_SPEC[0]CELL[1].IMUX_IOI_OCLKDIV[0]
CELL[1].IMUX_SPEC[2]CELL[1].IMUX_IOI_OCLK[0]
virtex7 IO_HP_PAIR switchbox SPEC_INT muxes IMUX_IOI_ICLK[0]
BitsDestination
MAIN[0][28][51]MAIN[0][29][52]MAIN[0][29][46]MAIN[0][29][48]MAIN[0][28][53]MAIN[0][28][49]MAIN[0][28][47]MAIN[0][29][50]MAIN[0][29][62]MAIN[0][28][61]MAIN[0][29][60]CELL[0].IMUX_IOI_ICLK[0]-
MAIN[1][28][13]MAIN[1][29][12]MAIN[1][28][11]MAIN[1][29][16]MAIN[1][29][14]MAIN[1][28][17]MAIN[1][28][15]MAIN[1][29][10]MAIN[1][28][1]MAIN[1][29][2]MAIN[1][28][3]-CELL[1].IMUX_IOI_ICLK[0]
Source
00000000000offoff
00000000010CELL[0].PHASER_ICLKCELL[1].PHASER_ICLK
00000000100CELL[0].PHASER_OCLKCELL[1].PHASER_OCLK
00000011001CELL[0].IMUX_IMUX[20]CELL[0].LCLK_IO[0]
00000101001CELL[0].IMUX_IMUX[22]CELL[0].LCLK_IO[1]
00001001001-CELL[0].LCLK_IO[2]
00001010001CELL[0].LCLK_IO[3]-
00001100001CELL[0].LCLK_IO[2]-
00010001001CELL[0].IOCLK[2]CELL[0].LCLK_IO[3]
00011000001CELL[0].LCLK_IO[0]-
00100001001CELL[0].IOCLK[3]-
00100010001-CELL[0].LCLK_IO[4]
00100100001-CELL[0].LCLK_IO[5]
00101000001CELL[0].LCLK_IO[1]CELL[0].RCLK_IO[0]
00110000001-CELL[0].RCLK_IO[1]
01000010001CELL[0].RCLK_IO[1]CELL[0].RCLK_IO[2]
01000100001CELL[0].RCLK_IO[0]CELL[0].RCLK_IO[3]
01001000001-CELL[0].IOCLK[0]
01010000001CELL[0].LCLK_IO[4]CELL[0].IOCLK[1]
01100000001CELL[0].LCLK_IO[5]-
10000010001CELL[0].IOCLK[1]CELL[0].IOCLK[2]
10000100001CELL[0].IOCLK[0]CELL[0].IOCLK[3]
10001000001-CELL[1].IMUX_IMUX[22]
10010000001CELL[0].RCLK_IO[2]CELL[1].IMUX_IMUX[20]
10100000001CELL[0].RCLK_IO[3]-
virtex7 IO_HP_PAIR switchbox SPEC_INT muxes IMUX_IOI_ICLK[1]
BitsDestination
MAIN[0][31][51]MAIN[0][30][52]MAIN[0][30][46]MAIN[0][30][48]MAIN[0][31][53]MAIN[0][31][49]MAIN[0][31][47]MAIN[0][30][50]MAIN[0][30][62]MAIN[0][31][61]MAIN[0][30][60]CELL[0].IMUX_IOI_ICLK[1]-
MAIN[1][31][13]MAIN[1][30][12]MAIN[1][31][11]MAIN[1][30][16]MAIN[1][30][14]MAIN[1][31][17]MAIN[1][31][15]MAIN[1][30][10]MAIN[1][31][1]MAIN[1][30][2]MAIN[1][31][3]-CELL[1].IMUX_IOI_ICLK[1]
Source
00000000000offoff
00000000010CELL[0].PHASER_ICLKCELL[1].PHASER_ICLK
00000000100CELL[0].PHASER_OCLKCELL[1].PHASER_OCLK
00000011001CELL[0].IMUX_IMUX[20]CELL[0].LCLK_IO[0]
00000101001CELL[0].IMUX_IMUX[22]CELL[0].LCLK_IO[1]
00001001001-CELL[0].LCLK_IO[2]
00001010001CELL[0].LCLK_IO[3]-
00001100001CELL[0].LCLK_IO[2]-
00010001001CELL[0].IOCLK[2]CELL[0].LCLK_IO[3]
00011000001CELL[0].LCLK_IO[0]-
00100001001CELL[0].IOCLK[3]-
00100010001-CELL[0].LCLK_IO[4]
00100100001-CELL[0].LCLK_IO[5]
00101000001CELL[0].LCLK_IO[1]CELL[0].RCLK_IO[0]
00110000001-CELL[0].RCLK_IO[1]
01000010001CELL[0].RCLK_IO[1]CELL[0].RCLK_IO[2]
01000100001CELL[0].RCLK_IO[0]CELL[0].RCLK_IO[3]
01001000001-CELL[0].IOCLK[0]
01010000001CELL[0].LCLK_IO[4]CELL[0].IOCLK[1]
01100000001CELL[0].LCLK_IO[5]-
10000010001CELL[0].IOCLK[1]CELL[0].IOCLK[2]
10000100001CELL[0].IOCLK[0]CELL[0].IOCLK[3]
10001000001-CELL[1].IMUX_IMUX[22]
10010000001CELL[0].RCLK_IO[2]CELL[1].IMUX_IMUX[20]
10100000001CELL[0].RCLK_IO[3]-
virtex7 IO_HP_PAIR switchbox SPEC_INT muxes IMUX_IOI_ICLKDIVP
BitsDestination
MAIN[0][29][28]MAIN[0][28][29]CELL[0].IMUX_IOI_ICLKDIVP-
MAIN[1][28][35]MAIN[1][29][34]-CELL[1].IMUX_IOI_ICLKDIVP
Source
00offoff
01CELL[0].IMUX_CLK[0]CELL[1].IMUX_CLK[0]
10CELL[0].PHASER_ICLKDIVCELL[1].PHASER_ICLKDIV
virtex7 IO_HP_PAIR switchbox SPEC_INT muxes IMUX_IOI_OCLK[0]
BitsDestination
MAIN[0][28][35]MAIN[0][29][38]MAIN[0][28][31]MAIN[0][29][30]MAIN[0][29][32]MAIN[0][28][39]MAIN[0][29][34]MAIN[0][28][33]MAIN[0][28][43]MAIN[0][28][45]MAIN[0][29][44]CELL[0].IMUX_IOI_OCLK[0]-
MAIN[1][28][29]MAIN[1][29][28]MAIN[1][28][25]MAIN[1][29][32]MAIN[1][29][30]MAIN[1][28][33]MAIN[1][28][31]MAIN[1][29][24]MAIN[1][29][20]MAIN[1][29][18]MAIN[1][28][19]-CELL[1].IMUX_IOI_OCLK[0]
Source
00000000000offoff
00000000010CELL[0].PHASER_OCLKCELL[1].PHASER_OCLK
00000000100CELL[0].PHASER_OCLK90CELL[1].PHASER_OCLK90
00000011001CELL[0].IMUX_IMUX[31]CELL[0].LCLK_IO[0]
00000101001CELL[0].LCLK_IO[2]CELL[0].LCLK_IO[1]
00001001001-CELL[0].LCLK_IO[2]
00001010001CELL[0].IOCLK[2]-
00001100001CELL[0].LCLK_IO[0]-
00010001001-CELL[0].LCLK_IO[3]
00010010001CELL[0].IOCLK[3]-
00010100001CELL[0].LCLK_IO[1]-
00100010001-CELL[0].LCLK_IO[4]
00100100001CELL[0].LCLK_IO[3]CELL[0].LCLK_IO[5]
00101000001-CELL[0].RCLK_IO[0]
00110000001-CELL[0].RCLK_IO[1]
01000001001CELL[0].RCLK_IO[0]-
01000010001-CELL[0].RCLK_IO[2]
01000100001-CELL[0].RCLK_IO[3]
01001000001CELL[0].LCLK_IO[4]CELL[0].IOCLK[0]
01010000001CELL[0].LCLK_IO[5]CELL[0].IOCLK[1]
01100000001CELL[0].RCLK_IO[1]-
10000001001CELL[0].IOCLK[0]-
10000010001-CELL[0].IOCLK[2]
10000100001-CELL[0].IOCLK[3]
10001000001CELL[0].RCLK_IO[2]CELL[1].IMUX_IMUX[31]
10010000001CELL[0].RCLK_IO[3]-
10100000001CELL[0].IOCLK[1]-
virtex7 IO_HP_PAIR switchbox SPEC_INT muxes IMUX_IOI_OCLK[1]
BitsDestination
MAIN[0][31][35]MAIN[0][30][38]MAIN[0][31][31]MAIN[0][30][30]MAIN[0][30][32]MAIN[0][31][39]MAIN[0][30][34]MAIN[0][31][33]MAIN[0][31][43]MAIN[0][31][45]MAIN[0][30][44]CELL[0].IMUX_IOI_OCLK[1]-
MAIN[1][31][29]MAIN[1][30][28]MAIN[1][31][25]MAIN[1][30][32]MAIN[1][30][30]MAIN[1][31][33]MAIN[1][31][31]MAIN[1][30][24]MAIN[1][30][20]MAIN[1][30][18]MAIN[1][31][19]-CELL[1].IMUX_IOI_OCLK[1]
Source
00000000000offoff
00000000010CELL[0].PHASER_OCLKCELL[1].PHASER_OCLK
00000000100CELL[0].PHASER_OCLK90CELL[1].PHASER_OCLK90
00000011001CELL[0].IMUX_IMUX[31]CELL[0].LCLK_IO[0]
00000101001CELL[0].LCLK_IO[2]CELL[0].LCLK_IO[1]
00001001001-CELL[0].LCLK_IO[2]
00001010001CELL[0].IOCLK[2]-
00001100001CELL[0].LCLK_IO[0]-
00010001001-CELL[0].LCLK_IO[3]
00010010001CELL[0].IOCLK[3]-
00010100001CELL[0].LCLK_IO[1]-
00100010001-CELL[0].LCLK_IO[4]
00100100001CELL[0].LCLK_IO[3]CELL[0].LCLK_IO[5]
00101000001-CELL[0].RCLK_IO[0]
00110000001-CELL[0].RCLK_IO[1]
01000001001CELL[0].RCLK_IO[0]-
01000010001-CELL[0].RCLK_IO[2]
01000100001-CELL[0].RCLK_IO[3]
01001000001CELL[0].LCLK_IO[4]CELL[0].IOCLK[0]
01010000001CELL[0].LCLK_IO[5]CELL[0].IOCLK[1]
01100000001CELL[0].RCLK_IO[1]-
10000001001CELL[0].IOCLK[0]-
10000010001-CELL[0].IOCLK[2]
10000100001-CELL[0].IOCLK[3]
10001000001CELL[0].RCLK_IO[2]CELL[1].IMUX_IMUX[31]
10010000001CELL[0].RCLK_IO[3]-
10100000001CELL[0].IOCLK[1]-
virtex7 IO_HP_PAIR switchbox SPEC_INT muxes IMUX_IOI_OCLKDIV[0]
BitsDestination
MAIN[0][29][16]MAIN[0][28][17]CELL[0].IMUX_IOI_OCLKDIV[0]-
MAIN[1][28][47]MAIN[1][29][46]-CELL[1].IMUX_IOI_OCLKDIV[0]
Source
00offoff
01CELL[0].PHASER_OCLKDIVCELL[1].PHASER_OCLKDIV
10CELL[0].IMUX_IOI_OCLKDIVF[0]CELL[1].IMUX_IOI_OCLKDIVF[0]
virtex7 IO_HP_PAIR switchbox SPEC_INT muxes IMUX_IOI_OCLKDIV[1]
BitsDestination
MAIN[0][30][16]MAIN[0][31][17]CELL[0].IMUX_IOI_OCLKDIV[1]-
MAIN[1][31][47]MAIN[1][30][46]-CELL[1].IMUX_IOI_OCLKDIV[1]
Source
00offoff
01CELL[0].PHASER_OCLKDIVCELL[1].PHASER_OCLKDIV
10CELL[0].IMUX_IOI_OCLKDIVF[1]CELL[1].IMUX_IOI_OCLKDIVF[1]
virtex7 IO_HP_PAIR switchbox SPEC_INT muxes IMUX_IOI_OCLKDIVF[0]
BitsDestination
MAIN[0][29][8]MAIN[0][28][9]MAIN[0][29][6]MAIN[0][29][2]MAIN[0][28][1]MAIN[0][28][3]MAIN[0][29][4]CELL[0].IMUX_IOI_OCLKDIVF[0]-
MAIN[1][28][57]MAIN[1][28][55]MAIN[1][29][54]MAIN[1][28][61]MAIN[1][28][59]MAIN[1][29][62]MAIN[1][29][60]-CELL[1].IMUX_IOI_OCLKDIVF[0]
Source
0000000offoff
0010001CELL[0].IMUX_IMUX[8]CELL[0].LCLK_IO[0]
0010010CELL[0].RCLK_IO[2]CELL[0].LCLK_IO[1]
0010100CELL[0].RCLK_IO[3]CELL[0].LCLK_IO[2]
0011000-CELL[0].LCLK_IO[3]
0100001CELL[0].LCLK_IO[2]CELL[0].LCLK_IO[4]
0100010CELL[0].LCLK_IO[0]CELL[0].LCLK_IO[5]
0100100CELL[0].LCLK_IO[1]CELL[0].RCLK_IO[0]
0101000CELL[0].LCLK_IO[3]CELL[0].RCLK_IO[1]
1000001CELL[0].RCLK_IO[0]CELL[0].RCLK_IO[2]
1000010CELL[0].LCLK_IO[4]CELL[0].RCLK_IO[3]
1000100CELL[0].LCLK_IO[5]CELL[1].IMUX_IMUX[8]
1001000CELL[0].RCLK_IO[1]-
virtex7 IO_HP_PAIR switchbox SPEC_INT muxes IMUX_IOI_OCLKDIVF[1]
BitsDestination
MAIN[0][30][8]MAIN[0][31][9]MAIN[0][30][6]MAIN[0][30][2]MAIN[0][31][1]MAIN[0][31][3]MAIN[0][30][4]CELL[0].IMUX_IOI_OCLKDIVF[1]-
MAIN[1][31][57]MAIN[1][31][55]MAIN[1][30][54]MAIN[1][31][61]MAIN[1][31][59]MAIN[1][30][62]MAIN[1][30][60]-CELL[1].IMUX_IOI_OCLKDIVF[1]
Source
0000000offoff
0010001CELL[0].IMUX_IMUX[8]CELL[0].LCLK_IO[0]
0010010CELL[0].RCLK_IO[2]CELL[0].LCLK_IO[1]
0010100CELL[0].RCLK_IO[3]CELL[0].LCLK_IO[2]
0011000-CELL[0].LCLK_IO[3]
0100001CELL[0].LCLK_IO[2]CELL[0].LCLK_IO[4]
0100010CELL[0].LCLK_IO[0]CELL[0].LCLK_IO[5]
0100100CELL[0].LCLK_IO[1]CELL[0].RCLK_IO[0]
0101000CELL[0].LCLK_IO[3]CELL[0].RCLK_IO[1]
1000001CELL[0].RCLK_IO[0]CELL[0].RCLK_IO[2]
1000010CELL[0].LCLK_IO[4]CELL[0].RCLK_IO[3]
1000100CELL[0].LCLK_IO[5]CELL[1].IMUX_IMUX[8]
1001000CELL[0].RCLK_IO[1]-

Bels ILOGIC

virtex7 IO_HP_PAIR bel ILOGIC pins
PinDirectionILOGIC[0]ILOGIC[1]
CLKinCELL[0].IMUX_IOI_ICLK[0]CELL[1].IMUX_IOI_ICLK[0]
CLKBinCELL[0].IMUX_IOI_ICLK[1]CELL[1].IMUX_IOI_ICLK[1]
CLKDIVinCELL[0].IMUX_CLK[0]CELL[1].IMUX_CLK[0]
CLKDIVPinCELL[0].IMUX_IOI_ICLKDIVPCELL[1].IMUX_IOI_ICLKDIVP
SRinCELL[0].IMUX_CTRL[1]CELL[1].IMUX_CTRL[1]
CE1inCELL[0].IMUX_IMUX[5]CELL[1].IMUX_IMUX[5]
CE2inCELL[0].IMUX_IMUX[14]CELL[1].IMUX_IMUX[14]
BITSLIPinCELL[0].IMUX_IMUX[0]CELL[1].IMUX_IMUX[0]
DYNCLKSELinCELL[0].IMUX_IMUX[37]CELL[1].IMUX_IMUX[37]
DYNCLKDIVSELinCELL[0].IMUX_IMUX[4]CELL[1].IMUX_IMUX[4]
DYNCLKDIVPSELinCELL[0].IMUX_IMUX[10]CELL[1].IMUX_IMUX[10]
OoutCELL[0].OUT_BEL[18]CELL[1].OUT_BEL[18]
Q1outCELL[0].OUT_BEL[0]CELL[1].OUT_BEL[0]
Q2outCELL[0].OUT_BEL[23]CELL[1].OUT_BEL[23]
Q3outCELL[0].OUT_BEL[9]CELL[1].OUT_BEL[9]
Q4outCELL[0].OUT_BEL[10]CELL[1].OUT_BEL[10]
Q5outCELL[0].OUT_BEL[14]CELL[1].OUT_BEL[14]
Q6outCELL[0].OUT_BEL[3]CELL[1].OUT_BEL[3]
Q7outCELL[0].OUT_BEL[7]CELL[1].OUT_BEL[7]
Q8outCELL[0].OUT_BEL[8]CELL[1].OUT_BEL[8]
CLKPADout-CELL[1].OUT_CLKPAD
virtex7 IO_HP_PAIR bel ILOGIC attribute bits
AttributeILOGIC[0]ILOGIC[1]

Bels OLOGIC

virtex7 IO_HP_PAIR bel OLOGIC pins
PinDirectionOLOGIC[0]OLOGIC[1]
CLKinCELL[0].IMUX_IOI_OCLK[0]CELL[1].IMUX_IOI_OCLK[0]
CLKBinCELL[0].IMUX_IOI_OCLK[1]CELL[1].IMUX_IOI_OCLK[1]
CLKDIVinCELL[0].IMUX_IOI_OCLKDIV[0] invert by MAIN[0][31][42]CELL[1].IMUX_IOI_OCLKDIV[0] invert by MAIN[1][30][21]
CLKDIVBinCELL[0].IMUX_IOI_OCLKDIV[1]CELL[1].IMUX_IOI_OCLKDIV[1]
CLKDIVFinCELL[0].IMUX_IOI_OCLKDIVF[0] invert by MAIN[0][30][33]CELL[1].IMUX_IOI_OCLKDIVF[0] invert by MAIN[1][31][30]
CLKDIVFBinCELL[0].IMUX_IOI_OCLKDIVF[1]CELL[1].IMUX_IOI_OCLKDIVF[1]
SRinCELL[0].IMUX_CTRL[0]CELL[1].IMUX_CTRL[0]
OCEinCELL[0].IMUX_IMUX[29]CELL[1].IMUX_IMUX[29]
TCEinCELL[0].IMUX_IMUX[1]CELL[1].IMUX_IMUX[1]
D1inCELL[0].IMUX_IMUX[34] invert by MAIN[0][31][30]CELL[1].IMUX_IMUX[34] invert by MAIN[1][30][33]
D2inCELL[0].IMUX_IMUX[40] invert by MAIN[0][30][25]CELL[1].IMUX_IMUX[40] invert by MAIN[1][31][38]
D3inCELL[0].IMUX_IMUX[44] invert by MAIN[0][30][21]CELL[1].IMUX_IMUX[44] invert by MAIN[1][31][42]
D4inCELL[0].IMUX_IMUX[42] invert by MAIN[0][30][17]CELL[1].IMUX_IMUX[42] invert by MAIN[1][31][46]
D5inCELL[0].IMUX_IMUX[43] invert by MAIN[0][31][14]CELL[1].IMUX_IMUX[43] invert by MAIN[1][30][49]
D6inCELL[0].IMUX_IMUX[45] invert by MAIN[0][30][13]CELL[1].IMUX_IMUX[45] invert by MAIN[1][31][50]
D7inCELL[0].IMUX_IMUX[46] invert by MAIN[0][30][9]CELL[1].IMUX_IMUX[46] invert by MAIN[1][31][54]
D8inCELL[0].IMUX_IMUX[47] invert by MAIN[0][31][2]CELL[1].IMUX_IMUX[47] invert by MAIN[1][30][61]
T1inCELL[0].IMUX_IMUX[15] invert by !MAIN[0][31][60]CELL[1].IMUX_IMUX[15] invert by !MAIN[1][30][3]
T2inCELL[0].IMUX_IMUX[7] invert by !MAIN[0][31][56]CELL[1].IMUX_IMUX[7] invert by !MAIN[1][30][7]
T3inCELL[0].IMUX_IMUX[13] invert by !MAIN[0][30][51]CELL[1].IMUX_IMUX[13] invert by !MAIN[1][31][12]
T4inCELL[0].IMUX_IMUX[21] invert by !MAIN[0][31][48]CELL[1].IMUX_IMUX[21] invert by !MAIN[1][30][15]
TFBoutCELL[0].OUT_BEL[2]CELL[1].OUT_BEL[2]
IOCLKGLITCHoutCELL[0].OUT_BEL[5]CELL[1].OUT_BEL[5]
virtex7 IO_HP_PAIR bel OLOGIC attribute bits
AttributeOLOGIC[0]OLOGIC[1]
CLK1_INV!MAIN[0][30][37]!MAIN[1][31][26]
CLK2_INV!MAIN[0][30][35]!MAIN[1][31][28]
FFO_INIT bit 0!MAIN[0][32][30]!MAIN[1][33][33]
FFO_SRVAL bit 0!MAIN[0][32][32]!MAIN[1][33][31]
FFO_SRVAL bit 1!MAIN[0][32][20]!MAIN[1][33][43]
FFO_SRVAL bit 2!MAIN[0][33][19]!MAIN[1][32][44]
FFO_SR_SYNCMAIN[0][33][33]MAIN[1][32][30]
FFO_SR_ENABLEMAIN[0][33][15]MAIN[1][32][48]
V5_MUX_O[enum: OLOGIC_V5_MUX_O][enum: OLOGIC_V5_MUX_O]
FFT_INIT bit 0!MAIN[0][31][52]!MAIN[1][30][11]
FFT_SRVAL bit 0!MAIN[0][32][52]!MAIN[1][33][11]
FFT_SRVAL bit 1!MAIN[0][32][46]!MAIN[1][33][17]
FFT_SRVAL bit 2!MAIN[0][33][45]!MAIN[1][32][18]
FFT_SR_SYNCMAIN[0][33][55]MAIN[1][32][8]
FFT_SR_ENABLEMAIN[0][32][38]MAIN[1][33][25]
V5_MUX_T[enum: OLOGIC_V5_MUX_T][enum: OLOGIC_V5_MUX_T]
SERDESMAIN[0][32][54]MAIN[1][33][9]
SERDES_MODE[enum: IO_SERDES_MODE][enum: IO_SERDES_MODE]
DATA_WIDTH[enum: IO_DATA_WIDTH][enum: IO_DATA_WIDTH]
TRISTATE_WIDTH[enum: OLOGIC_TRISTATE_WIDTH][enum: OLOGIC_TRISTATE_WIDTH]
MISR_ENABLEMAIN[0][31][16]MAIN[1][30][47]
MISR_ENABLE_FDBKMAIN[0][31][10]MAIN[1][30][53]
MISR_RESETMAIN[0][31][8]MAIN[1][30][55]
MISR_CLK_SELECT[enum: OLOGIC_MISR_CLK_SELECT][enum: OLOGIC_MISR_CLK_SELECT]
CLOCK_RATIO[enum: OLOGIC_CLOCK_RATIO][enum: OLOGIC_CLOCK_RATIO]
SELFHEALMAIN[0][30][31]MAIN[1][31][32]
RANK3_USED!MAIN[0][30][41]!MAIN[1][31][22]
TBYTE_CTLMAIN[0][33][47]MAIN[1][32][16]
TBYTE_SRCMAIN[0][33][43]MAIN[1][32][20]
virtex7 IO_HP_PAIR enum OLOGIC_V5_MUX_O
OLOGIC[0].V5_MUX_OMAIN[0][33][17]MAIN[0][32][14]MAIN[0][32][36]MAIN[0][32][34]MAIN[0][32][16]
OLOGIC[1].V5_MUX_OMAIN[1][32][46]MAIN[1][33][49]MAIN[1][33][27]MAIN[1][33][29]MAIN[1][33][47]
NONE00000
D100001
SERDES_SDR00010
LATCH10010
FF01010
DDR00100
virtex7 IO_HP_PAIR enum OLOGIC_V5_MUX_T
OLOGIC[0].V5_MUX_TMAIN[0][32][60]MAIN[0][33][59]MAIN[0][33][57]MAIN[0][32][58]MAIN[0][33][61]
OLOGIC[1].V5_MUX_TMAIN[1][33][3]MAIN[1][32][4]MAIN[1][32][6]MAIN[1][33][5]MAIN[1][32][2]
NONE00000
T100001
SERDES_SDR00010
LATCH10010
FF01010
DDR00100
virtex7 IO_HP_PAIR enum IO_SERDES_MODE
OLOGIC[0].SERDES_MODEMAIN[0][32][44]
OLOGIC[1].SERDES_MODEMAIN[1][33][19]
MASTER0
SLAVE1
virtex7 IO_HP_PAIR enum IO_DATA_WIDTH
OLOGIC[0].DATA_WIDTHMAIN[0][31][26]MAIN[0][31][12]MAIN[0][30][11]MAIN[0][31][4]MAIN[0][30][7]MAIN[0][31][6]MAIN[0][30][3]MAIN[0][30][1]MAIN[0][31][0]
OLOGIC[1].DATA_WIDTHMAIN[1][30][37]MAIN[1][30][51]MAIN[1][31][52]MAIN[1][30][59]MAIN[1][31][56]MAIN[1][30][57]MAIN[1][31][60]MAIN[1][31][62]MAIN[1][30][63]
NONE000000000
_2000000001
_3000000010
_4000000100
_5000001000
_6000010000
_7000100000
_8001000000
_10010000000
_14100000000
virtex7 IO_HP_PAIR enum OLOGIC_TRISTATE_WIDTH
OLOGIC[0].TRISTATE_WIDTHMAIN[0][33][37]
OLOGIC[1].TRISTATE_WIDTHMAIN[1][32][26]
_10
_41
virtex7 IO_HP_PAIR enum OLOGIC_MISR_CLK_SELECT
OLOGIC[0].MISR_CLK_SELECTMAIN[0][30][5]MAIN[0][30][15]
OLOGIC[1].MISR_CLK_SELECTMAIN[1][31][58]MAIN[1][31][48]
NONE00
CLK101
CLK210
virtex7 IO_HP_PAIR enum OLOGIC_CLOCK_RATIO
OLOGIC[0].CLOCK_RATIOMAIN[0][30][27]MAIN[0][30][29]MAIN[0][31][32]MAIN[0][31][28]
OLOGIC[1].CLOCK_RATIOMAIN[1][31][36]MAIN[1][31][34]MAIN[1][30][31]MAIN[1][30][35]
NONE0000
_20001
_30010
_40011
_50101
_61101
_7_81100

Bels IDELAY

virtex7 IO_HP_PAIR bel IDELAY pins
PinDirectionIDELAY[0]IDELAY[1]
CinCELL[0].IMUX_CLK[1] invert by MAIN[0][35][39]CELL[1].IMUX_CLK[1] invert by MAIN[1][34][24]
CINVCTRLinCELL[0].IMUX_BYP_SITE[6]CELL[1].IMUX_BYP_SITE[6]
CEinCELL[0].IMUX_IMUX[32]CELL[1].IMUX_IMUX[32]
DATAINinCELL[0].IMUX_IMUX[25] invert by MAIN[0][34][46]CELL[1].IMUX_IMUX[25] invert by MAIN[1][35][17]
INCinCELL[0].IMUX_IMUX[26]CELL[1].IMUX_IMUX[26]
REGRSTinCELL[0].IMUX_IMUX[12]CELL[1].IMUX_IMUX[12]
LDinCELL[0].IMUX_IMUX[30]CELL[1].IMUX_IMUX[30]
LDPIPEENinCELL[0].IMUX_IMUX[33]CELL[1].IMUX_IMUX[33]
IFDLY[0]inCELL[0].IMUX_FAN_SITE[4]CELL[1].IMUX_FAN_SITE[4]
IFDLY[1]inCELL[0].IMUX_FAN_SITE[5]CELL[1].IMUX_FAN_SITE[5]
IFDLY[2]inCELL[0].IMUX_BYP_SITE[7]CELL[1].IMUX_BYP_SITE[7]
CNTVALUEIN[0]inCELL[0].IMUX_IMUX[41]CELL[1].IMUX_IMUX[41]
CNTVALUEIN[1]inCELL[0].IMUX_IMUX[36]CELL[1].IMUX_IMUX[36]
CNTVALUEIN[2]inCELL[0].IMUX_IMUX[35]CELL[1].IMUX_IMUX[35]
CNTVALUEIN[3]inCELL[0].IMUX_IMUX[38]CELL[1].IMUX_IMUX[38]
CNTVALUEIN[4]inCELL[0].IMUX_IMUX[39]CELL[1].IMUX_IMUX[39]
CNTVALUEOUT[0]outCELL[0].OUT_BEL[20]CELL[1].OUT_BEL[20]
CNTVALUEOUT[1]outCELL[0].OUT_BEL[1]CELL[1].OUT_BEL[1]
CNTVALUEOUT[2]outCELL[0].OUT_BEL[19]CELL[1].OUT_BEL[19]
CNTVALUEOUT[3]outCELL[0].OUT_BEL[15]CELL[1].OUT_BEL[15]
CNTVALUEOUT[4]outCELL[0].OUT_BEL[11]CELL[1].OUT_BEL[11]
virtex7 IO_HP_PAIR bel IDELAY attribute bits
AttributeIDELAY[0]IDELAY[1]
ENABLEMAIN[0][33][54]MAIN[1][32][9]
IDATAIN_INVMAIN[0][32][55]MAIN[1][33][8]
CINVCTRL_SELMAIN[0][34][38]MAIN[1][35][25]
FINEDELAYMAIN[0][28][58]MAIN[1][29][5]
DELAY_SRC[enum: IDELAY_DELAY_SRC][enum: IDELAY_DELAY_SRC]
DELAY_TYPE[enum: IODELAY_V7_DELAY_TYPE][enum: IODELAY_V7_DELAY_TYPE]
HIGH_PERFORMANCE_MODEMAIN[0][33][18]MAIN[1][32][45]
PIPE_SELMAIN[0][35][21]MAIN[1][34][42]
IDELAY_VALUE_CUR bit 0!MAIN[0][35][7]!MAIN[1][34][56]
IDELAY_VALUE_CUR bit 1!MAIN[0][35][13]!MAIN[1][34][50]
IDELAY_VALUE_CUR bit 2!MAIN[0][35][19]!MAIN[1][34][44]
IDELAY_VALUE_CUR bit 3!MAIN[0][35][27]!MAIN[1][34][36]
IDELAY_VALUE_CUR bit 4!MAIN[0][35][33]!MAIN[1][34][30]
IDELAY_VALUE_INIT bit 0MAIN[0][35][5]MAIN[1][34][58]
IDELAY_VALUE_INIT bit 1MAIN[0][35][11]MAIN[1][34][52]
IDELAY_VALUE_INIT bit 2MAIN[0][35][17]MAIN[1][34][46]
IDELAY_VALUE_INIT bit 3MAIN[0][35][25]MAIN[1][34][38]
IDELAY_VALUE_INIT bit 4MAIN[0][35][31]MAIN[1][34][32]
virtex7 IO_HP_PAIR enum IDELAY_DELAY_SRC
IDELAY[0].DELAY_SRCMAIN[0][35][57]MAIN[0][34][58]MAIN[0][34][56]MAIN[0][35][55]
IDELAY[1].DELAY_SRCMAIN[1][34][6]MAIN[1][35][5]MAIN[1][35][7]MAIN[1][34][8]
NONE0000
IDATAIN0001
OFB0010
DATAIN0100
DELAYCHAIN_OSC1000
virtex7 IO_HP_PAIR enum IODELAY_V7_DELAY_TYPE
IDELAY[0].DELAY_TYPEMAIN[0][34][14]MAIN[0][34][8]
IDELAY[1].DELAY_TYPEMAIN[1][35][49]MAIN[1][35][55]
FIXED00
VARIABLE01
VAR_LOAD11

Bels ODELAY

virtex7 IO_HP_PAIR bel ODELAY pins
PinDirectionODELAY[0]ODELAY[1]
CinCELL[0].IMUX_CLK[1] invert by MAIN[0][37][39]CELL[1].IMUX_CLK[1] invert by MAIN[1][36][24]
CINVCTRLinCELL[0].IMUX_BYP_SITE[2]CELL[1].IMUX_BYP_SITE[2]
CEinCELL[0].IMUX_IMUX[2]CELL[1].IMUX_IMUX[2]
INCinCELL[0].IMUX_IMUX[3]CELL[1].IMUX_IMUX[3]
REGRSTinCELL[0].IMUX_IMUX[11]CELL[1].IMUX_IMUX[11]
LDinCELL[0].IMUX_IMUX[28]CELL[1].IMUX_IMUX[28]
LDPIPEENinCELL[0].IMUX_IMUX[27]CELL[1].IMUX_IMUX[27]
OFDLY[0]inCELL[0].IMUX_BYP_SITE[0]CELL[1].IMUX_BYP_SITE[0]
OFDLY[1]inCELL[0].IMUX_BYP_SITE[1]CELL[1].IMUX_BYP_SITE[1]
OFDLY[2]inCELL[0].IMUX_BYP_SITE[5]CELL[1].IMUX_BYP_SITE[5]
CNTVALUEIN[0]inCELL[0].IMUX_IMUX[23]CELL[1].IMUX_IMUX[23]
CNTVALUEIN[1]inCELL[0].IMUX_IMUX[16]CELL[1].IMUX_IMUX[16]
CNTVALUEIN[2]inCELL[0].IMUX_IMUX[17]CELL[1].IMUX_IMUX[17]
CNTVALUEIN[3]inCELL[0].IMUX_IMUX[19]CELL[1].IMUX_IMUX[19]
CNTVALUEIN[4]inCELL[0].IMUX_IMUX[18]CELL[1].IMUX_IMUX[18]
CNTVALUEOUT[0]outCELL[0].OUT_BEL[12]CELL[1].OUT_BEL[12]
CNTVALUEOUT[1]outCELL[0].OUT_BEL[4]CELL[1].OUT_BEL[4]
CNTVALUEOUT[2]outCELL[0].OUT_BEL[6]CELL[1].OUT_BEL[6]
CNTVALUEOUT[3]outCELL[0].OUT_BEL[17]CELL[1].OUT_BEL[17]
CNTVALUEOUT[4]outCELL[0].OUT_BEL[21]CELL[1].OUT_BEL[21]
DATAOUToutCELL[0].IMUX_SPEC[1]CELL[1].IMUX_SPEC[1]
virtex7 IO_HP_PAIR bel ODELAY attribute bits
AttributeODELAY[0]ODELAY[1]
ENABLEMAIN[0][35][54]MAIN[1][34][9]
ODATAIN_INV!MAIN[0][34][55]!MAIN[1][35][8]
CINVCTRL_SELMAIN[0][36][38]MAIN[1][37][25]
FINEDELAYMAIN[0][36][22]MAIN[1][37][41]
DELAY_SRC[enum: ODELAY_DELAY_SRC][enum: ODELAY_DELAY_SRC]
DELAY_TYPE[enum: IODELAY_V7_DELAY_TYPE][enum: IODELAY_V7_DELAY_TYPE]
HIGH_PERFORMANCE_MODEMAIN[0][35][18]MAIN[1][34][45]
PIPE_SELMAIN[0][37][21]MAIN[1][36][42]
ODELAY_VALUE_CUR bit 0!MAIN[0][37][7]!MAIN[1][36][56]
ODELAY_VALUE_CUR bit 1!MAIN[0][37][13]!MAIN[1][36][50]
ODELAY_VALUE_CUR bit 2!MAIN[0][37][19]!MAIN[1][36][44]
ODELAY_VALUE_CUR bit 3!MAIN[0][37][27]!MAIN[1][36][36]
ODELAY_VALUE_CUR bit 4!MAIN[0][37][33]!MAIN[1][36][30]
ODELAY_VALUE_INIT bit 0MAIN[0][37][5]MAIN[1][36][58]
ODELAY_VALUE_INIT bit 1MAIN[0][37][11]MAIN[1][36][52]
ODELAY_VALUE_INIT bit 2MAIN[0][37][17]MAIN[1][36][46]
ODELAY_VALUE_INIT bit 3MAIN[0][37][25]MAIN[1][36][38]
ODELAY_VALUE_INIT bit 4MAIN[0][37][31]MAIN[1][36][32]
virtex7 IO_HP_PAIR enum ODELAY_DELAY_SRC
ODELAY[0].DELAY_SRCMAIN[0][37][57]MAIN[0][36][56]MAIN[0][37][55]
ODELAY[1].DELAY_SRCMAIN[1][36][6]MAIN[1][37][7]MAIN[1][36][8]
NONE000
ODATAIN001
CLKIN010
DELAYCHAIN_OSC100
virtex7 IO_HP_PAIR enum IODELAY_V7_DELAY_TYPE
ODELAY[0].DELAY_TYPEMAIN[0][36][14]MAIN[0][36][8]
ODELAY[1].DELAY_TYPEMAIN[1][37][49]MAIN[1][37][55]
FIXED00
VARIABLE01
VAR_LOAD11

Bels IOB

virtex7 IO_HP_PAIR bel IOB pins
PinDirectionIOB[0]IOB[1]
PD_INT_ENinCELL[0].IMUX_FAN_SITE[2]CELL[1].IMUX_FAN_SITE[2]
PU_INT_ENinCELL[0].IMUX_FAN_SITE[1]CELL[1].IMUX_FAN_SITE[1]
KEEPER_INT_ENinCELL[0].IMUX_FAN_SITE[3]CELL[1].IMUX_FAN_SITE[3]
DIFF_TERM_INT_ENinCELL[0].IMUX_FAN_SITE[0]-
IBUFDISABLEinCELL[0].IMUX_IMUX[9]CELL[1].IMUX_IMUX[9]
DCITERMDISABLEinCELL[0].IMUX_IMUX[6]CELL[1].IMUX_IMUX[6]
virtex7 IO_HP_PAIR bel IOB attribute bits
AttributeIOB[0]IOB[1]
PULL[enum: IOB_PULL][enum: IOB_PULL]
VREF_SYSMONMAIN[0][39][59]MAIN[1][38][4]
PULL_DYNAMICMAIN[0][38][6]MAIN[1][39][57]
DQS_BIAS_PMAIN[0][39][29]MAIN[1][38][34]
DQS_BIAS_NMAIN[0][38][36]MAIN[1][39][27]
IBUFDISABLE_ENMAIN[0][39][39]MAIN[1][38][24]
DCITERMDISABLE_ENMAIN[0][38][62]MAIN[1][39][1]
IBUF_MODE[enum: IOB_IBUF_MODE][enum: IOB_IBUF_MODE]
IBUF_VREF_HPMAIN[0][38][2]MAIN[1][39][61]
IBUF_DIFF_HPMAIN[0][39][3]MAIN[1][38][60]
INPUT_MISC bit 0MAIN[0][39][5]MAIN[1][38][58]
OUTPUT_ENABLE bit 0MAIN[0][38][32]MAIN[1][39][29]
OUTPUT_ENABLE bit 1MAIN[0][38][34]MAIN[1][39][31]
OUTPUT_DELAYMAIN[0][38][52]MAIN[1][39][11]
DCI_MODE[enum: IOB_DCI_MODE][enum: IOB_DCI_MODE]
DCI_TMAIN[0][39][63]MAIN[1][38][0]
DCIUPDATEMODE_ASREQUIRED!MAIN[0][38][56]!MAIN[1][39][7]
OUTPUT_PSEUDO_DIFFMAIN[0][39][43]-
OUTPUT_PSEUDO_DIFF_TMAIN[0][39][17]-
V5_LVDS bit 0MAIN[0][38][8]MAIN[1][39][55]
V5_LVDS bit 1MAIN[0][39][15]MAIN[1][38][48]
V5_LVDS bit 2MAIN[0][39][21]MAIN[1][38][42]
V5_LVDS bit 3MAIN[0][39][25]MAIN[1][38][38]
V5_LVDS bit 4MAIN[0][38][28]MAIN[1][39][35]
V5_LVDS bit 5MAIN[0][39][37]MAIN[1][38][26]
V5_LVDS bit 6MAIN[0][38][40]MAIN[1][39][23]
V5_LVDS bit 7MAIN[0][38][54]MAIN[1][39][9]
V5_LVDS bit 8MAIN[0][39][41]MAIN[1][38][22]
V6_PSLEW bit 0MAIN[0][38][50]MAIN[1][39][13]
V6_PSLEW bit 1MAIN[0][38][30]MAIN[1][39][33]
V6_PSLEW bit 2MAIN[0][38][26]MAIN[1][39][37]
V6_PSLEW bit 3MAIN[0][38][16]MAIN[1][39][47]
V6_PSLEW bit 4MAIN[0][39][13]MAIN[1][38][50]
V6_NSLEW bit 0MAIN[0][38][46]MAIN[1][39][17]
V6_NSLEW bit 1MAIN[0][39][45]MAIN[1][38][18]
V6_NSLEW bit 2MAIN[0][38][38]MAIN[1][39][25]
V6_NSLEW bit 3MAIN[0][38][22]MAIN[1][39][41]
V6_NSLEW bit 4MAIN[0][38][14]MAIN[1][39][49]
V7_PDRIVE bit 0MAIN[0][39][61]MAIN[1][38][2]
V7_PDRIVE bit 1MAIN[0][39][31]MAIN[1][38][32]
V7_PDRIVE bit 2!MAIN[0][38][48]!MAIN[1][39][15]
V7_PDRIVE bit 3!MAIN[0][39][49]!MAIN[1][38][14]
V7_PDRIVE bit 4MAIN[0][38][44]MAIN[1][39][19]
V7_PDRIVE bit 5!MAIN[0][39][33]!MAIN[1][38][30]
V7_PDRIVE bit 6MAIN[0][39][23]MAIN[1][38][40]
V7_NDRIVE bit 0MAIN[0][39][51]MAIN[1][38][12]
V7_NDRIVE bit 1MAIN[0][39][27]MAIN[1][38][36]
V7_NDRIVE bit 2MAIN[0][39][55]MAIN[1][38][8]
V7_NDRIVE bit 3!MAIN[0][39][47]!MAIN[1][38][16]
V7_NDRIVE bit 4MAIN[0][39][35]MAIN[1][38][28]
V7_NDRIVE bit 5!MAIN[0][38][24]!MAIN[1][39][39]
V7_NDRIVE bit 6MAIN[0][38][20]MAIN[1][39][43]
V7_OUTPUT_MISC bit 0MAIN[0][38][58]MAIN[1][39][5]
V7_OUTPUT_MISC bit 1MAIN[0][38][60]MAIN[1][39][3]
V7_OUTPUT_MISC bit 2MAIN[0][39][9]MAIN[1][38][54]
V7_OUTPUT_MISC bit 3MAIN[0][39][57]MAIN[1][38][6]
V7_OUTPUT_MISC bit 4MAIN[0][39][11]MAIN[1][38][52]
V7_OUTPUT_MISC bit 5MAIN[0][39][19]MAIN[1][38][44]
virtex7 IO_HP_PAIR enum IOB_PULL
IOB[0].PULLMAIN[0][38][4]MAIN[0][38][10]MAIN[0][38][12]
IOB[1].PULLMAIN[1][39][59]MAIN[1][39][53]MAIN[1][39][51]
NONE001
PULLUP011
PULLDOWN000
KEEPER101
virtex7 IO_HP_PAIR enum IOB_IBUF_MODE
IOB[0].IBUF_MODEMAIN[0][39][1]MAIN[0][38][0]
IOB[1].IBUF_MODEMAIN[1][38][62]MAIN[1][39][63]
NONE00
VREF01
DIFF10
CMOS11
virtex7 IO_HP_PAIR enum IOB_DCI_MODE
IOB[0].DCI_MODEMAIN[0][39][53]MAIN[0][38][42]
IOB[1].DCI_MODEMAIN[1][38][10]MAIN[1][39][21]
NONE00
OUTPUT01
OUTPUT_HALF10
TERM_SPLIT11

Bel wires

virtex7 IO_HP_PAIR bel wires
WirePins
CELL[0].IMUX_CLK[0]ILOGIC[0].CLKDIV
CELL[0].IMUX_CLK[1]IDELAY[0].C, ODELAY[0].C
CELL[0].IMUX_CTRL[0]OLOGIC[0].SR
CELL[0].IMUX_CTRL[1]ILOGIC[0].SR
CELL[0].IMUX_BYP_SITE[0]ODELAY[0].OFDLY[0]
CELL[0].IMUX_BYP_SITE[1]ODELAY[0].OFDLY[1]
CELL[0].IMUX_BYP_SITE[2]ODELAY[0].CINVCTRL
CELL[0].IMUX_BYP_SITE[5]ODELAY[0].OFDLY[2]
CELL[0].IMUX_BYP_SITE[6]IDELAY[0].CINVCTRL
CELL[0].IMUX_BYP_SITE[7]IDELAY[0].IFDLY[2]
CELL[0].IMUX_FAN_SITE[0]IOB[0].DIFF_TERM_INT_EN
CELL[0].IMUX_FAN_SITE[1]IOB[0].PU_INT_EN
CELL[0].IMUX_FAN_SITE[2]IOB[0].PD_INT_EN
CELL[0].IMUX_FAN_SITE[3]IOB[0].KEEPER_INT_EN
CELL[0].IMUX_FAN_SITE[4]IDELAY[0].IFDLY[0]
CELL[0].IMUX_FAN_SITE[5]IDELAY[0].IFDLY[1]
CELL[0].IMUX_IMUX[0]ILOGIC[0].BITSLIP
CELL[0].IMUX_IMUX[1]OLOGIC[0].TCE
CELL[0].IMUX_IMUX[2]ODELAY[0].CE
CELL[0].IMUX_IMUX[3]ODELAY[0].INC
CELL[0].IMUX_IMUX[4]ILOGIC[0].DYNCLKDIVSEL
CELL[0].IMUX_IMUX[5]ILOGIC[0].CE1
CELL[0].IMUX_IMUX[6]IOB[0].DCITERMDISABLE
CELL[0].IMUX_IMUX[7]OLOGIC[0].T2
CELL[0].IMUX_IMUX[9]IOB[0].IBUFDISABLE
CELL[0].IMUX_IMUX[10]ILOGIC[0].DYNCLKDIVPSEL
CELL[0].IMUX_IMUX[11]ODELAY[0].REGRST
CELL[0].IMUX_IMUX[12]IDELAY[0].REGRST
CELL[0].IMUX_IMUX[13]OLOGIC[0].T3
CELL[0].IMUX_IMUX[14]ILOGIC[0].CE2
CELL[0].IMUX_IMUX[15]OLOGIC[0].T1
CELL[0].IMUX_IMUX[16]ODELAY[0].CNTVALUEIN[1]
CELL[0].IMUX_IMUX[17]ODELAY[0].CNTVALUEIN[2]
CELL[0].IMUX_IMUX[18]ODELAY[0].CNTVALUEIN[4]
CELL[0].IMUX_IMUX[19]ODELAY[0].CNTVALUEIN[3]
CELL[0].IMUX_IMUX[21]OLOGIC[0].T4
CELL[0].IMUX_IMUX[23]ODELAY[0].CNTVALUEIN[0]
CELL[0].IMUX_IMUX[25]IDELAY[0].DATAIN
CELL[0].IMUX_IMUX[26]IDELAY[0].INC
CELL[0].IMUX_IMUX[27]ODELAY[0].LDPIPEEN
CELL[0].IMUX_IMUX[28]ODELAY[0].LD
CELL[0].IMUX_IMUX[29]OLOGIC[0].OCE
CELL[0].IMUX_IMUX[30]IDELAY[0].LD
CELL[0].IMUX_IMUX[32]IDELAY[0].CE
CELL[0].IMUX_IMUX[33]IDELAY[0].LDPIPEEN
CELL[0].IMUX_IMUX[34]OLOGIC[0].D1
CELL[0].IMUX_IMUX[35]IDELAY[0].CNTVALUEIN[2]
CELL[0].IMUX_IMUX[36]IDELAY[0].CNTVALUEIN[1]
CELL[0].IMUX_IMUX[37]ILOGIC[0].DYNCLKSEL
CELL[0].IMUX_IMUX[38]IDELAY[0].CNTVALUEIN[3]
CELL[0].IMUX_IMUX[39]IDELAY[0].CNTVALUEIN[4]
CELL[0].IMUX_IMUX[40]OLOGIC[0].D2
CELL[0].IMUX_IMUX[41]IDELAY[0].CNTVALUEIN[0]
CELL[0].IMUX_IMUX[42]OLOGIC[0].D4
CELL[0].IMUX_IMUX[43]OLOGIC[0].D5
CELL[0].IMUX_IMUX[44]OLOGIC[0].D3
CELL[0].IMUX_IMUX[45]OLOGIC[0].D6
CELL[0].IMUX_IMUX[46]OLOGIC[0].D7
CELL[0].IMUX_IMUX[47]OLOGIC[0].D8
CELL[0].OUT_BEL[0]ILOGIC[0].Q1
CELL[0].OUT_BEL[1]IDELAY[0].CNTVALUEOUT[1]
CELL[0].OUT_BEL[2]OLOGIC[0].TFB
CELL[0].OUT_BEL[3]ILOGIC[0].Q6
CELL[0].OUT_BEL[4]ODELAY[0].CNTVALUEOUT[1]
CELL[0].OUT_BEL[5]OLOGIC[0].IOCLKGLITCH
CELL[0].OUT_BEL[6]ODELAY[0].CNTVALUEOUT[2]
CELL[0].OUT_BEL[7]ILOGIC[0].Q7
CELL[0].OUT_BEL[8]ILOGIC[0].Q8
CELL[0].OUT_BEL[9]ILOGIC[0].Q3
CELL[0].OUT_BEL[10]ILOGIC[0].Q4
CELL[0].OUT_BEL[11]IDELAY[0].CNTVALUEOUT[4]
CELL[0].OUT_BEL[12]ODELAY[0].CNTVALUEOUT[0]
CELL[0].OUT_BEL[14]ILOGIC[0].Q5
CELL[0].OUT_BEL[15]IDELAY[0].CNTVALUEOUT[3]
CELL[0].OUT_BEL[17]ODELAY[0].CNTVALUEOUT[3]
CELL[0].OUT_BEL[18]ILOGIC[0].O
CELL[0].OUT_BEL[19]IDELAY[0].CNTVALUEOUT[2]
CELL[0].OUT_BEL[20]IDELAY[0].CNTVALUEOUT[0]
CELL[0].OUT_BEL[21]ODELAY[0].CNTVALUEOUT[4]
CELL[0].OUT_BEL[23]ILOGIC[0].Q2
CELL[0].IMUX_SPEC[1]ODELAY[0].DATAOUT
CELL[0].IMUX_IOI_ICLK[0]ILOGIC[0].CLK
CELL[0].IMUX_IOI_ICLK[1]ILOGIC[0].CLKB
CELL[0].IMUX_IOI_ICLKDIVPILOGIC[0].CLKDIVP
CELL[0].IMUX_IOI_OCLK[0]OLOGIC[0].CLK
CELL[0].IMUX_IOI_OCLK[1]OLOGIC[0].CLKB
CELL[0].IMUX_IOI_OCLKDIV[0]OLOGIC[0].CLKDIV
CELL[0].IMUX_IOI_OCLKDIV[1]OLOGIC[0].CLKDIVB
CELL[0].IMUX_IOI_OCLKDIVF[0]OLOGIC[0].CLKDIVF
CELL[0].IMUX_IOI_OCLKDIVF[1]OLOGIC[0].CLKDIVFB
CELL[1].IMUX_CLK[0]ILOGIC[1].CLKDIV
CELL[1].IMUX_CLK[1]IDELAY[1].C, ODELAY[1].C
CELL[1].IMUX_CTRL[0]OLOGIC[1].SR
CELL[1].IMUX_CTRL[1]ILOGIC[1].SR
CELL[1].IMUX_BYP_SITE[0]ODELAY[1].OFDLY[0]
CELL[1].IMUX_BYP_SITE[1]ODELAY[1].OFDLY[1]
CELL[1].IMUX_BYP_SITE[2]ODELAY[1].CINVCTRL
CELL[1].IMUX_BYP_SITE[5]ODELAY[1].OFDLY[2]
CELL[1].IMUX_BYP_SITE[6]IDELAY[1].CINVCTRL
CELL[1].IMUX_BYP_SITE[7]IDELAY[1].IFDLY[2]
CELL[1].IMUX_FAN_SITE[1]IOB[1].PU_INT_EN
CELL[1].IMUX_FAN_SITE[2]IOB[1].PD_INT_EN
CELL[1].IMUX_FAN_SITE[3]IOB[1].KEEPER_INT_EN
CELL[1].IMUX_FAN_SITE[4]IDELAY[1].IFDLY[0]
CELL[1].IMUX_FAN_SITE[5]IDELAY[1].IFDLY[1]
CELL[1].IMUX_IMUX[0]ILOGIC[1].BITSLIP
CELL[1].IMUX_IMUX[1]OLOGIC[1].TCE
CELL[1].IMUX_IMUX[2]ODELAY[1].CE
CELL[1].IMUX_IMUX[3]ODELAY[1].INC
CELL[1].IMUX_IMUX[4]ILOGIC[1].DYNCLKDIVSEL
CELL[1].IMUX_IMUX[5]ILOGIC[1].CE1
CELL[1].IMUX_IMUX[6]IOB[1].DCITERMDISABLE
CELL[1].IMUX_IMUX[7]OLOGIC[1].T2
CELL[1].IMUX_IMUX[9]IOB[1].IBUFDISABLE
CELL[1].IMUX_IMUX[10]ILOGIC[1].DYNCLKDIVPSEL
CELL[1].IMUX_IMUX[11]ODELAY[1].REGRST
CELL[1].IMUX_IMUX[12]IDELAY[1].REGRST
CELL[1].IMUX_IMUX[13]OLOGIC[1].T3
CELL[1].IMUX_IMUX[14]ILOGIC[1].CE2
CELL[1].IMUX_IMUX[15]OLOGIC[1].T1
CELL[1].IMUX_IMUX[16]ODELAY[1].CNTVALUEIN[1]
CELL[1].IMUX_IMUX[17]ODELAY[1].CNTVALUEIN[2]
CELL[1].IMUX_IMUX[18]ODELAY[1].CNTVALUEIN[4]
CELL[1].IMUX_IMUX[19]ODELAY[1].CNTVALUEIN[3]
CELL[1].IMUX_IMUX[21]OLOGIC[1].T4
CELL[1].IMUX_IMUX[23]ODELAY[1].CNTVALUEIN[0]
CELL[1].IMUX_IMUX[25]IDELAY[1].DATAIN
CELL[1].IMUX_IMUX[26]IDELAY[1].INC
CELL[1].IMUX_IMUX[27]ODELAY[1].LDPIPEEN
CELL[1].IMUX_IMUX[28]ODELAY[1].LD
CELL[1].IMUX_IMUX[29]OLOGIC[1].OCE
CELL[1].IMUX_IMUX[30]IDELAY[1].LD
CELL[1].IMUX_IMUX[32]IDELAY[1].CE
CELL[1].IMUX_IMUX[33]IDELAY[1].LDPIPEEN
CELL[1].IMUX_IMUX[34]OLOGIC[1].D1
CELL[1].IMUX_IMUX[35]IDELAY[1].CNTVALUEIN[2]
CELL[1].IMUX_IMUX[36]IDELAY[1].CNTVALUEIN[1]
CELL[1].IMUX_IMUX[37]ILOGIC[1].DYNCLKSEL
CELL[1].IMUX_IMUX[38]IDELAY[1].CNTVALUEIN[3]
CELL[1].IMUX_IMUX[39]IDELAY[1].CNTVALUEIN[4]
CELL[1].IMUX_IMUX[40]OLOGIC[1].D2
CELL[1].IMUX_IMUX[41]IDELAY[1].CNTVALUEIN[0]
CELL[1].IMUX_IMUX[42]OLOGIC[1].D4
CELL[1].IMUX_IMUX[43]OLOGIC[1].D5
CELL[1].IMUX_IMUX[44]OLOGIC[1].D3
CELL[1].IMUX_IMUX[45]OLOGIC[1].D6
CELL[1].IMUX_IMUX[46]OLOGIC[1].D7
CELL[1].IMUX_IMUX[47]OLOGIC[1].D8
CELL[1].OUT_BEL[0]ILOGIC[1].Q1
CELL[1].OUT_BEL[1]IDELAY[1].CNTVALUEOUT[1]
CELL[1].OUT_BEL[2]OLOGIC[1].TFB
CELL[1].OUT_BEL[3]ILOGIC[1].Q6
CELL[1].OUT_BEL[4]ODELAY[1].CNTVALUEOUT[1]
CELL[1].OUT_BEL[5]OLOGIC[1].IOCLKGLITCH
CELL[1].OUT_BEL[6]ODELAY[1].CNTVALUEOUT[2]
CELL[1].OUT_BEL[7]ILOGIC[1].Q7
CELL[1].OUT_BEL[8]ILOGIC[1].Q8
CELL[1].OUT_BEL[9]ILOGIC[1].Q3
CELL[1].OUT_BEL[10]ILOGIC[1].Q4
CELL[1].OUT_BEL[11]IDELAY[1].CNTVALUEOUT[4]
CELL[1].OUT_BEL[12]ODELAY[1].CNTVALUEOUT[0]
CELL[1].OUT_BEL[14]ILOGIC[1].Q5
CELL[1].OUT_BEL[15]IDELAY[1].CNTVALUEOUT[3]
CELL[1].OUT_BEL[17]ODELAY[1].CNTVALUEOUT[3]
CELL[1].OUT_BEL[18]ILOGIC[1].O
CELL[1].OUT_BEL[19]IDELAY[1].CNTVALUEOUT[2]
CELL[1].OUT_BEL[20]IDELAY[1].CNTVALUEOUT[0]
CELL[1].OUT_BEL[21]ODELAY[1].CNTVALUEOUT[4]
CELL[1].OUT_BEL[23]ILOGIC[1].Q2
CELL[1].IMUX_SPEC[1]ODELAY[1].DATAOUT
CELL[1].OUT_CLKPADILOGIC[1].CLKPAD
CELL[1].IMUX_IOI_ICLK[0]ILOGIC[1].CLK
CELL[1].IMUX_IOI_ICLK[1]ILOGIC[1].CLKB
CELL[1].IMUX_IOI_ICLKDIVPILOGIC[1].CLKDIVP
CELL[1].IMUX_IOI_OCLK[0]OLOGIC[1].CLK
CELL[1].IMUX_IOI_OCLK[1]OLOGIC[1].CLKB
CELL[1].IMUX_IOI_OCLKDIV[0]OLOGIC[1].CLKDIV
CELL[1].IMUX_IOI_OCLKDIV[1]OLOGIC[1].CLKDIVB
CELL[1].IMUX_IOI_OCLKDIVF[0]OLOGIC[1].CLKDIVF
CELL[1].IMUX_IOI_OCLKDIVF[1]OLOGIC[1].CLKDIVFB

Bitstream

virtex7 IO_HP_PAIR rect MAIN[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: DCI_T - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 2 SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 2 - - - - - - - IOB[0]: DCITERMDISABLE_EN - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 1 - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 1 - OLOGIC[0]: V5_MUX_T bit 0 - - - - - IOB[0]: V7_PDRIVE bit 0 - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 0 SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 0 OLOGIC[0]: !invert T1 OLOGIC[0]: V5_MUX_T bit 4 - - - - - IOB[0]: V7_OUTPUT_MISC bit 1 - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_T bit 3 - - - - - IOB[0]: VREF_SYSMON - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[0]: FINEDELAY - - - OLOGIC[0]: V5_MUX_T bit 1 - IDELAY[0]: DELAY_SRC bit 2 - - - IOB[0]: V7_OUTPUT_MISC bit 0 - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_T bit 2 - IDELAY[0]: DELAY_SRC bit 3 - ODELAY[0]: DELAY_SRC bit 2 - IOB[0]: V7_OUTPUT_MISC bit 3 - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: !invert T2 - - IDELAY[0]: DELAY_SRC bit 1 - ODELAY[0]: DELAY_SRC bit 1 - IOB[0]: ! DCIUPDATEMODE_ASREQUIRED - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[0]: IDATAIN_INV OLOGIC[0]: FFT_SR_SYNC ODELAY[0]: ! ODATAIN_INV IDELAY[0]: DELAY_SRC bit 0 - ODELAY[0]: DELAY_SRC bit 0 - IOB[0]: V7_NDRIVE bit 2 - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: SERDES IDELAY[0]: ENABLE - ODELAY[0]: ENABLE - - IOB[0]: V5_LVDS bit 7 - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 6 - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 6 - - - - - - - IOB[0]: DCI_MODE bit 1 - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 9 SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 9 OLOGIC[0]: ! FFT_INIT bit 0 OLOGIC[0]: ! FFT_SRVAL bit 0 - - - - - IOB[0]: OUTPUT_DELAY - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 10 - OLOGIC[0]: !invert T3 SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 10 - - - - - - - IOB[0]: V7_NDRIVE bit 0 - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 3 SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 3 - - - - - - - IOB[0]: V6_PSLEW bit 0 - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 5 - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 5 - - - - - - - IOB[0]: ! V7_PDRIVE bit 3 - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 7 SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 7 OLOGIC[0]: !invert T4 - - - - - - IOB[0]: ! V7_PDRIVE bit 2 - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 4 - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 4 - OLOGIC[0]: TBYTE_CTL - - - - - IOB[0]: ! V7_NDRIVE bit 3 - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 8 SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 8 - OLOGIC[0]: ! FFT_SRVAL bit 1 - IDELAY[0]: invert DATAIN - - - IOB[0]: V6_NSLEW bit 0 - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 1 - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 1 - OLOGIC[0]: ! FFT_SRVAL bit 2 - - - - - IOB[0]: V6_NSLEW bit 1 - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 0 SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 0 - OLOGIC[0]: SERDES_MODE bit 0 - - - - - IOB[0]: V7_PDRIVE bit 4 - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 2 - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 2 - OLOGIC[0]: TBYTE_SRC - - - - - IOB[0]: OUTPUT_PSEUDO_DIFF - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert CLKDIV - - - - - - IOB[0]: DCI_MODE bit 0 - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! RANK3_USED - - - - - - - - IOB[0]: V5_LVDS bit 8 - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: V5_LVDS bit 6 - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 5 - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 5 - - - IDELAY[0]: invert C - ODELAY[0]: invert C - IOB[0]: IBUFDISABLE_EN - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 9 SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 9 - OLOGIC[0]: FFT_SR_ENABLE - IDELAY[0]: CINVCTRL_SEL - ODELAY[0]: CINVCTRL_SEL - IOB[0]: V6_NSLEW bit 2 - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! CLK1_INV - - OLOGIC[0]: TRISTATE_WIDTH bit 0 - - - - - IOB[0]: V5_LVDS bit 5 - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_O bit 2 - - - - - IOB[0]: DQS_BIAS_N - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 10 - OLOGIC[0]: ! CLK2_INV SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 10 - - - - - - - IOB[0]: V7_NDRIVE bit 4 - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 4 SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 4 - OLOGIC[0]: V5_MUX_O bit 1 - - - - - IOB[0]: OUTPUT_ENABLE bit 1 - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 3 - OLOGIC[0]: invert CLKDIVF SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 3 - OLOGIC[0]: FFO_SR_SYNC - IDELAY[0]: ! IDELAY_VALUE_CUR bit 4 - ODELAY[0]: ! ODELAY_VALUE_CUR bit 4 - IOB[0]: ! V7_PDRIVE bit 5 - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 6 SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 6 OLOGIC[0]: CLOCK_RATIO bit 1 OLOGIC[0]: ! FFO_SRVAL bit 0 - - - - - IOB[0]: OUTPUT_ENABLE bit 0 - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 8 - OLOGIC[0]: SELFHEAL SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 8 - - - IDELAY[0]: IDELAY_VALUE_INIT bit 4 - ODELAY[0]: ODELAY_VALUE_INIT bit 4 - IOB[0]: V7_PDRIVE bit 1 - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 7 SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 7 OLOGIC[0]: invert D1 OLOGIC[0]: ! FFO_INIT bit 0 - - - - - IOB[0]: V6_PSLEW bit 1 - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLKDIVP bit 0 - OLOGIC[0]: CLOCK_RATIO bit 2 - - - - - - - - IOB[0]: DQS_BIAS_P - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLKDIVP bit 1 - OLOGIC[0]: CLOCK_RATIO bit 0 - - - - - - IOB[0]: V5_LVDS bit 4 - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: CLOCK_RATIO bit 3 - - - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 3 - ODELAY[0]: ! ODELAY_VALUE_CUR bit 3 - IOB[0]: V7_NDRIVE bit 1 - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 8 - - - - - - IOB[0]: V6_PSLEW bit 2 - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D2 - - - - IDELAY[0]: IDELAY_VALUE_INIT bit 3 - ODELAY[0]: ODELAY_VALUE_INIT bit 3 - IOB[0]: V5_LVDS bit 3 - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: ! V7_NDRIVE bit 5 - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: V7_PDRIVE bit 6 - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ODELAY[0]: FINEDELAY - IOB[0]: V6_NSLEW bit 3 - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D3 - - - - IDELAY[0]: PIPE_SEL - ODELAY[0]: PIPE_SEL - IOB[0]: V5_LVDS bit 2 - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFO_SRVAL bit 1 - - - - - IOB[0]: V7_NDRIVE bit 6 - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFO_SRVAL bit 2 - IDELAY[0]: ! IDELAY_VALUE_CUR bit 2 - ODELAY[0]: ! ODELAY_VALUE_CUR bit 2 - IOB[0]: V7_OUTPUT_MISC bit 5 - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[0]: HIGH_PERFORMANCE_MODE - ODELAY[0]: HIGH_PERFORMANCE_MODE - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[0] bit 0 - OLOGIC[0]: invert D4 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[1] bit 0 - OLOGIC[0]: V5_MUX_O bit 4 - IDELAY[0]: IDELAY_VALUE_INIT bit 2 - ODELAY[0]: ODELAY_VALUE_INIT bit 2 - IOB[0]: OUTPUT_PSEUDO_DIFF_T - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[0] bit 1 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[1] bit 1 OLOGIC[0]: MISR_ENABLE OLOGIC[0]: V5_MUX_O bit 0 - - - - - IOB[0]: V6_PSLEW bit 3 - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_CLK_SELECT bit 0 - - OLOGIC[0]: FFO_SR_ENABLE - - - - - IOB[0]: V5_LVDS bit 1 - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D5 OLOGIC[0]: V5_MUX_O bit 3 - IDELAY[0]: DELAY_TYPE bit 1 - ODELAY[0]: DELAY_TYPE bit 1 - IOB[0]: V6_NSLEW bit 4 - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D6 - - - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 1 - ODELAY[0]: ! ODELAY_VALUE_CUR bit 1 - IOB[0]: V6_PSLEW bit 4 - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 7 - - - - - - IOB[0]: PULL bit 0 - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 6 - - - - IDELAY[0]: IDELAY_VALUE_INIT bit 1 - ODELAY[0]: ODELAY_VALUE_INIT bit 1 - IOB[0]: V7_OUTPUT_MISC bit 4 - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_ENABLE_FDBK - - - - - - IOB[0]: PULL bit 1 - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[0] bit 5 - OLOGIC[0]: invert D7 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[1] bit 5 - - - - - - - IOB[0]: V7_OUTPUT_MISC bit 2 - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[0] bit 6 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[1] bit 6 OLOGIC[0]: MISR_RESET - - IDELAY[0]: DELAY_TYPE bit 0 - ODELAY[0]: DELAY_TYPE bit 0 - IOB[0]: V5_LVDS bit 0 - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 4 - - - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 0 - ODELAY[0]: ! ODELAY_VALUE_CUR bit 0 - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[0] bit 4 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[1] bit 4 OLOGIC[0]: DATA_WIDTH bit 3 - - - - - - IOB[0]: PULL_DYNAMIC - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_CLK_SELECT bit 1 - - - - IDELAY[0]: IDELAY_VALUE_INIT bit 0 - ODELAY[0]: ODELAY_VALUE_INIT bit 0 - IOB[0]: INPUT_MISC bit 0 - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[0] bit 0 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[1] bit 0 OLOGIC[0]: DATA_WIDTH bit 5 - - - - - - IOB[0]: PULL bit 2 - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[0] bit 1 - OLOGIC[0]: DATA_WIDTH bit 2 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[1] bit 1 - - - - - - - IOB[0]: IBUF_DIFF_HP - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[0] bit 3 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[1] bit 3 OLOGIC[0]: invert D8 - - - - - - IOB[0]: IBUF_VREF_HP - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[0] bit 2 - OLOGIC[0]: DATA_WIDTH bit 1 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[1] bit 2 - - - - - - - IOB[0]: IBUF_MODE bit 1 - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 0 - - - - - - IOB[0]: IBUF_MODE bit 0 - - -
virtex7 IO_HP_PAIR rect MAIN[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: DATA_WIDTH bit 0 - - - - - - - - IOB[1]: IBUF_MODE bit 0 - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[0] bit 1 SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[1] bit 1 OLOGIC[1]: DATA_WIDTH bit 1 - - - - - - IOB[1]: IBUF_MODE bit 1 - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[0] bit 3 - OLOGIC[1]: invert D8 SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[1] bit 3 - - - - - - - IOB[1]: IBUF_VREF_HP - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[0] bit 0 SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[1] bit 0 OLOGIC[1]: DATA_WIDTH bit 2 - - - - - - IOB[1]: IBUF_DIFF_HP - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[0] bit 2 - OLOGIC[1]: DATA_WIDTH bit 5 SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[1] bit 2 - - - - - - - IOB[1]: PULL bit 2 - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: MISR_CLK_SELECT bit 1 - - IDELAY[1]: IDELAY_VALUE_INIT bit 0 - ODELAY[1]: ODELAY_VALUE_INIT bit 0 - IOB[1]: INPUT_MISC bit 0 - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[0] bit 6 - OLOGIC[1]: DATA_WIDTH bit 3 SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[1] bit 6 - - - - - - - IOB[1]: PULL_DYNAMIC - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: DATA_WIDTH bit 4 - - IDELAY[1]: ! IDELAY_VALUE_CUR bit 0 - ODELAY[1]: ! ODELAY_VALUE_CUR bit 0 - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[0] bit 5 - OLOGIC[1]: MISR_RESET SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[1] bit 5 - - - IDELAY[1]: DELAY_TYPE bit 0 - ODELAY[1]: DELAY_TYPE bit 0 - IOB[1]: V5_LVDS bit 0 - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[0] bit 4 SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[1] bit 4 OLOGIC[1]: invert D7 - - - - - - IOB[1]: V7_OUTPUT_MISC bit 2 - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: MISR_ENABLE_FDBK - - - - - - - - IOB[1]: PULL bit 1 - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: DATA_WIDTH bit 6 - - IDELAY[1]: IDELAY_VALUE_INIT bit 1 - ODELAY[1]: ODELAY_VALUE_INIT bit 1 - IOB[1]: V7_OUTPUT_MISC bit 4 - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: DATA_WIDTH bit 7 - - - - - - - - IOB[1]: PULL bit 0 - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: invert D6 - - IDELAY[1]: ! IDELAY_VALUE_CUR bit 1 - ODELAY[1]: ! ODELAY_VALUE_CUR bit 1 - IOB[1]: V6_PSLEW bit 4 - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: invert D5 - - OLOGIC[1]: V5_MUX_O bit 3 - IDELAY[1]: DELAY_TYPE bit 1 - ODELAY[1]: DELAY_TYPE bit 1 - IOB[1]: V6_NSLEW bit 4 - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: MISR_CLK_SELECT bit 0 OLOGIC[1]: FFO_SR_ENABLE - - - - - IOB[1]: V5_LVDS bit 1 - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[0] bit 1 - OLOGIC[1]: MISR_ENABLE SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[1] bit 1 - OLOGIC[1]: V5_MUX_O bit 0 - - - - - IOB[1]: V6_PSLEW bit 3 - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[0] bit 0 SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[1] bit 0 OLOGIC[1]: invert D4 OLOGIC[1]: V5_MUX_O bit 4 - IDELAY[1]: IDELAY_VALUE_INIT bit 2 - ODELAY[1]: ODELAY_VALUE_INIT bit 2 - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[1]: HIGH_PERFORMANCE_MODE - ODELAY[1]: HIGH_PERFORMANCE_MODE - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: ! FFO_SRVAL bit 2 - IDELAY[1]: ! IDELAY_VALUE_CUR bit 2 - ODELAY[1]: ! ODELAY_VALUE_CUR bit 2 - IOB[1]: V7_OUTPUT_MISC bit 5 - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: ! FFO_SRVAL bit 1 - - - - - IOB[1]: V7_NDRIVE bit 6 - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: invert D3 - - IDELAY[1]: PIPE_SEL - ODELAY[1]: PIPE_SEL - IOB[1]: V5_LVDS bit 2 - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ODELAY[1]: FINEDELAY - IOB[1]: V6_NSLEW bit 3 - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[1]: V7_PDRIVE bit 6 - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[1]: ! V7_NDRIVE bit 5 - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: invert D2 - - IDELAY[1]: IDELAY_VALUE_INIT bit 3 - ODELAY[1]: ODELAY_VALUE_INIT bit 3 - IOB[1]: V5_LVDS bit 3 - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: DATA_WIDTH bit 8 - - - - - - - - IOB[1]: V6_PSLEW bit 2 - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: CLOCK_RATIO bit 3 - - IDELAY[1]: ! IDELAY_VALUE_CUR bit 3 - ODELAY[1]: ! ODELAY_VALUE_CUR bit 3 - IOB[1]: V7_NDRIVE bit 1 - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLKDIVP bit 1 - OLOGIC[1]: CLOCK_RATIO bit 0 - - - - - - - - IOB[1]: V5_LVDS bit 4 - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLKDIVP bit 0 - OLOGIC[1]: CLOCK_RATIO bit 2 - - - - - - IOB[1]: DQS_BIAS_P - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 5 - OLOGIC[1]: invert D1 SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 5 - OLOGIC[1]: ! FFO_INIT bit 0 - - - - - IOB[1]: V6_PSLEW bit 1 - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 7 SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 7 OLOGIC[1]: SELFHEAL - - IDELAY[1]: IDELAY_VALUE_INIT bit 4 - ODELAY[1]: ODELAY_VALUE_INIT bit 4 - IOB[1]: V7_PDRIVE bit 1 - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 4 - OLOGIC[1]: CLOCK_RATIO bit 1 SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 4 - OLOGIC[1]: ! FFO_SRVAL bit 0 - - - - - IOB[1]: OUTPUT_ENABLE bit 1 - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 6 SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 6 OLOGIC[1]: invert CLKDIVF OLOGIC[1]: FFO_SR_SYNC - IDELAY[1]: ! IDELAY_VALUE_CUR bit 4 - ODELAY[1]: ! ODELAY_VALUE_CUR bit 4 - IOB[1]: ! V7_PDRIVE bit 5 - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 10 - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 10 - OLOGIC[1]: V5_MUX_O bit 1 - - - - - IOB[1]: OUTPUT_ENABLE bit 0 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 9 SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 9 OLOGIC[1]: ! CLK2_INV - - - - - - IOB[1]: V7_NDRIVE bit 4 - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: V5_MUX_O bit 2 - - - - - IOB[1]: DQS_BIAS_N - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: ! CLK1_INV OLOGIC[1]: TRISTATE_WIDTH bit 0 - - - - - IOB[1]: V5_LVDS bit 5 - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 8 - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 8 - OLOGIC[1]: FFT_SR_ENABLE - IDELAY[1]: CINVCTRL_SEL - ODELAY[1]: CINVCTRL_SEL - IOB[1]: V6_NSLEW bit 2 - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 3 SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 3 - - - IDELAY[1]: invert C - ODELAY[1]: invert C - IOB[1]: IBUFDISABLE_EN - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[1]: V5_LVDS bit 6 - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: ! RANK3_USED - - - - - - IOB[1]: V5_LVDS bit 8 - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: invert CLKDIV - - - - - - - - IOB[1]: DCI_MODE bit 0 - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 2 SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 2 - OLOGIC[1]: TBYTE_SRC - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 0 - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 0 - OLOGIC[1]: SERDES_MODE bit 0 - - - - - IOB[1]: V7_PDRIVE bit 4 - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 1 SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 1 - OLOGIC[1]: ! FFT_SRVAL bit 2 - - - - - IOB[1]: V6_NSLEW bit 1 - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 5 - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 5 - OLOGIC[1]: ! FFT_SRVAL bit 1 - IDELAY[1]: invert DATAIN - - - IOB[1]: V6_NSLEW bit 0 - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 7 SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 7 - OLOGIC[1]: TBYTE_CTL - - - - - IOB[1]: ! V7_NDRIVE bit 3 - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 4 - OLOGIC[1]: !invert T4 SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 4 - - - - - - - IOB[1]: ! V7_PDRIVE bit 2 - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 6 SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 6 - - - - - - - IOB[1]: ! V7_PDRIVE bit 3 - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 10 - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 10 - - - - - - - IOB[1]: V6_PSLEW bit 0 - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 9 SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 9 OLOGIC[1]: !invert T3 - - - - - - IOB[1]: V7_NDRIVE bit 0 - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 8 - OLOGIC[1]: ! FFT_INIT bit 0 SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 8 - OLOGIC[1]: ! FFT_SRVAL bit 0 - - - - - IOB[1]: OUTPUT_DELAY - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 3 SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 3 - - - - - - - IOB[1]: DCI_MODE bit 1 - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[1]: ENABLE OLOGIC[1]: SERDES ODELAY[1]: ENABLE - - - - IOB[1]: V5_LVDS bit 7 - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFT_SR_SYNC IDELAY[1]: IDATAIN_INV IDELAY[1]: DELAY_SRC bit 0 ODELAY[1]: ! ODATAIN_INV ODELAY[1]: DELAY_SRC bit 0 - IOB[1]: V7_NDRIVE bit 2 - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: !invert T2 - - - - IDELAY[1]: DELAY_SRC bit 1 - ODELAY[1]: DELAY_SRC bit 1 - IOB[1]: ! DCIUPDATEMODE_ASREQUIRED - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: V5_MUX_T bit 2 - IDELAY[1]: DELAY_SRC bit 3 - ODELAY[1]: DELAY_SRC bit 2 - IOB[1]: V7_OUTPUT_MISC bit 3 - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[1]: FINEDELAY - - - OLOGIC[1]: V5_MUX_T bit 1 - IDELAY[1]: DELAY_SRC bit 2 - - - IOB[1]: V7_OUTPUT_MISC bit 0 - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: V5_MUX_T bit 3 - - - - - IOB[1]: VREF_SYSMON - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 0 - OLOGIC[1]: !invert T1 SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 0 - OLOGIC[1]: V5_MUX_T bit 4 - - - - - IOB[1]: V7_OUTPUT_MISC bit 1 - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 1 SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 1 - OLOGIC[1]: V5_MUX_T bit 0 - - - - - IOB[1]: V7_PDRIVE bit 0 - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 2 - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 2 - - - - - - - IOB[1]: DCITERMDISABLE_EN - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[1]: DCI_T - - -
### Bitstream
virtex7 IO_HP_PAIR rect R0
BitFrame
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B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.OCLK1
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:D_EMU1 -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:D_EMU2
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SRTYPE[0] -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IFF_SR_USED - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF_LATCH ~ILOGIC[0]:IFF1_SRVAL -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF1_INIT
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF2_SRVAL -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF2_INIT
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:NUM_CE[0] - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF3_SRVAL -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF3_INIT
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF4_SRVAL -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF4_INIT
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DDR_CLK_EDGE[0] - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DDR_CLK_EDGE[1] - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:RANK23_DLY - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[1] ILOGIC[0]:I_DELAY_ENABLE -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SERDES - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:I_TSBYPASS_ENABLE -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SERDES_MODE[0] - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:BITSLIP_ENABLE - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_RATE[0] - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[3] ~ILOGIC[0]:INV.D -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[2] - - ILOGIC[0]:TSBYPASS_MUX[0]
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[1] - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[0] - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[3] ILOGIC[0]:IFF_TSBYPASS_ENABLE -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.CLKDIVP - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[4] - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLKDIVP_INV_EN - - ILOGIC[0]:IFF_DELAY_ENABLE
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[2] - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLKDIV_INV_EN - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.CLKDIV - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[0] - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[1] -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.OCLK2
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[0] -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[2]
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLK_INV_EN -
virtex7 IO_HP_PAIR rect R1
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DYN_CLK_INV_EN
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:INV.CLK[0] -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:INV.CLK[2]
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INV.OCLK2 -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:INV.CLK[1]
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INTERFACE_TYPE[0] - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INV.CLKDIV - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DYN_CLKDIV_INV_EN - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INTERFACE_TYPE[2] - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DYN_CLKDIVP_INV_EN ILOGIC[1]:IFF_DELAY_ENABLE -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INTERFACE_TYPE[4] - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INV.CLKDIVP - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INTERFACE_TYPE[3] - - ILOGIC[1]:IFF_TSBYPASS_ENABLE
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DATA_WIDTH[0] - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DATA_WIDTH[1] - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DATA_WIDTH[2] ILOGIC[1]:TSBYPASS_MUX[0] -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DATA_WIDTH[3] - - ~ILOGIC[1]:INV.D
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DATA_RATE[0] - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:BITSLIP_ENABLE - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:SERDES_MODE[0] - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:I_TSBYPASS_ENABLE
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:SERDES - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INTERFACE_TYPE[1] - - ILOGIC[1]:I_DELAY_ENABLE
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:RANK23_DLY - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DDR_CLK_EDGE[1] - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DDR_CLK_EDGE[0] - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:IFF4_INIT -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:IFF4_SRVAL
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:IFF3_INIT -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:IFF3_SRVAL
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:NUM_CE[0] - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:IFF2_INIT -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:IFF2_SRVAL
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:IFF1_INIT -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:IFF_LATCH - - ~ILOGIC[1]:IFF1_SRVAL
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:IFF_SR_USED - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:SRTYPE[0]
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:D_EMU2 -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:D_EMU1
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INV.OCLK1 -
ILOGIC[0]:BITSLIP_ENABLE 0.F27.B20
ILOGIC[0]:DYN_CLKDIVP_INV_EN 0.F26.B11
ILOGIC[0]:DYN_CLKDIV_INV_EN 0.F26.B9
ILOGIC[0]:DYN_CLK_INV_EN 0.F28.B0
ILOGIC[0]:D_EMU1 0.F28.B62
ILOGIC[0]:D_EMU2 0.F29.B61
ILOGIC[0]:IFF_DELAY_ENABLE 0.F29.B11
ILOGIC[0]:IFF_SR_USED 0.F26.B57
ILOGIC[0]:IFF_TSBYPASS_ENABLE 0.F28.B14
ILOGIC[0]:INV.CLKDIV 0.F27.B8
ILOGIC[0]:INV.CLKDIVP 0.F26.B13
ILOGIC[0]:INV.OCLK1 0.F29.B63
ILOGIC[0]:INV.OCLK2 0.F29.B3
ILOGIC[0]:I_DELAY_ENABLE 0.F28.B26
ILOGIC[0]:I_TSBYPASS_ENABLE 0.F28.B24
ILOGIC[0]:RANK23_DLY 0.F26.B27
ILOGIC[0]:SERDES 0.F26.B25
ILOGIC[1]:BITSLIP_ENABLE 1.F26.B43
ILOGIC[1]:DYN_CLKDIVP_INV_EN 1.F27.B52
ILOGIC[1]:DYN_CLKDIV_INV_EN 1.F27.B54
ILOGIC[1]:DYN_CLK_INV_EN 1.F29.B63
ILOGIC[1]:D_EMU1 1.F29.B1
ILOGIC[1]:D_EMU2 1.F28.B2
ILOGIC[1]:IFF_DELAY_ENABLE 1.F28.B52
ILOGIC[1]:IFF_SR_USED 1.F27.B6
ILOGIC[1]:IFF_TSBYPASS_ENABLE 1.F29.B49
ILOGIC[1]:INV.CLKDIV 1.F26.B55
ILOGIC[1]:INV.CLKDIVP 1.F27.B50
ILOGIC[1]:INV.OCLK1 1.F28.B0
ILOGIC[1]:INV.OCLK2 1.F28.B60
ILOGIC[1]:I_DELAY_ENABLE 1.F29.B37
ILOGIC[1]:I_TSBYPASS_ENABLE 1.F29.B39
ILOGIC[1]:RANK23_DLY 1.F27.B36
ILOGIC[1]:SERDES 1.F27.B38
non-inverted [0]
ILOGIC[0]:DATA_RATE 0.F26.B19
ILOGIC[1]:DATA_RATE 1.F27.B44
DDR 0
SDR 1
ILOGIC[0]:DATA_WIDTH 0.F27.B18 0.F26.B17 0.F27.B16 0.F26.B15
ILOGIC[1]:DATA_WIDTH 1.F26.B45 1.F27.B46 1.F26.B47 1.F27.B48
NONE 0 0 0 0
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
10 1 0 1 0
14 1 1 1 0
ILOGIC[0]:DDR_CLK_EDGE 0.F27.B28 0.F26.B29
ILOGIC[1]:DDR_CLK_EDGE 1.F26.B35 1.F27.B34
SAME_EDGE_PIPELINED 0 0
OPPOSITE_EDGE 0 1
SAME_EDGE 1 0
ILOGIC[0]:IFF1_INIT 0.F29.B55
ILOGIC[0]:IFF1_SRVAL 0.F28.B56
ILOGIC[0]:IFF2_INIT 0.F29.B51
ILOGIC[0]:IFF2_SRVAL 0.F28.B52
ILOGIC[0]:IFF3_INIT 0.F29.B41
ILOGIC[0]:IFF3_SRVAL 0.F28.B42
ILOGIC[0]:IFF4_INIT 0.F29.B33
ILOGIC[0]:IFF4_SRVAL 0.F28.B34
ILOGIC[0]:IFF_LATCH 0.F27.B56
ILOGIC[0]:INV.D 0.F28.B18
ILOGIC[1]:IFF1_INIT 1.F28.B8
ILOGIC[1]:IFF1_SRVAL 1.F29.B7
ILOGIC[1]:IFF2_INIT 1.F28.B12
ILOGIC[1]:IFF2_SRVAL 1.F29.B11
ILOGIC[1]:IFF3_INIT 1.F28.B22
ILOGIC[1]:IFF3_SRVAL 1.F29.B21
ILOGIC[1]:IFF4_INIT 1.F28.B30
ILOGIC[1]:IFF4_SRVAL 1.F29.B29
ILOGIC[1]:IFF_LATCH 1.F26.B7
ILOGIC[1]:INV.D 1.F29.B45
inverted ~[0]
ILOGIC[0]:INTERFACE_TYPE 0.F27.B12 0.F27.B14 0.F27.B10 0.F27.B26 0.F27.B6
ILOGIC[1]:INTERFACE_TYPE 1.F26.B51 1.F26.B49 1.F26.B53 1.F26.B37 1.F26.B57
MEMORY 0 0 0 0 0
NETWORKING 0 0 0 0 1
MEMORY_DDR3 0 0 1 1 1
MEMORY_DDR3_V6 0 1 0 1 1
OVERSAMPLE 1 0 0 1 1
ILOGIC[0]:INV.CLK 0.F29.B1 0.F28.B4 0.F28.B2
ILOGIC[1]:INV.CLK 1.F29.B61 1.F29.B59 1.F28.B62
inverted ~[2] ~[1] ~[0]
ILOGIC[0]:NUM_CE 0.F26.B47
ILOGIC[1]:NUM_CE 1.F27.B16
1 0
2 1
ILOGIC[0]:SERDES_MODE 0.F26.B21
ILOGIC[1]:SERDES_MODE 1.F27.B42
MASTER 0
SLAVE 1
ILOGIC[0]:SRTYPE 0.F28.B60
ILOGIC[1]:SRTYPE 1.F29.B3
ASYNC 0
SYNC 1
ILOGIC[0]:TSBYPASS_MUX 0.F29.B17
ILOGIC[1]:TSBYPASS_MUX 1.F28.B46
T 0
GND 1

Tile IO_HP_S

Cells: 1

Switchbox SPEC_INT

virtex7 IO_HP_S switchbox SPEC_INT permanent buffers
DestinationSource
IMUX_SPEC[0]IMUX_IOI_OCLKDIV[0]
IMUX_SPEC[2]IMUX_IOI_OCLK[0]
virtex7 IO_HP_S switchbox SPEC_INT muxes IMUX_IOI_ICLK[0]
BitsDestination
MAIN[29][12]MAIN[28][11]MAIN[28][17]MAIN[28][15]MAIN[29][10]MAIN[29][14]MAIN[29][16]MAIN[28][13]MAIN[28][1]MAIN[29][2]MAIN[28][3]IMUX_IOI_ICLK[0]
Source
00000000000off
00000000010PHASER_ICLK
00000000100PHASER_OCLK
00000011001IMUX_IMUX[20]
00000101001IMUX_IMUX[22]
00001010001LCLK_IO[3]
00001100001LCLK_IO[2]
00010001001IOCLK[2]
00011000001LCLK_IO[0]
00100001001IOCLK[3]
00101000001LCLK_IO[1]
01000010001RCLK_IO[1]
01000100001RCLK_IO[0]
01010000001LCLK_IO[4]
01100000001LCLK_IO[5]
10000010001IOCLK[1]
10000100001IOCLK[0]
10010000001RCLK_IO[2]
10100000001RCLK_IO[3]
virtex7 IO_HP_S switchbox SPEC_INT muxes IMUX_IOI_ICLK[1]
BitsDestination
MAIN[30][12]MAIN[31][11]MAIN[31][17]MAIN[31][15]MAIN[30][10]MAIN[30][14]MAIN[30][16]MAIN[31][13]MAIN[31][1]MAIN[30][2]MAIN[31][3]IMUX_IOI_ICLK[1]
Source
00000000000off
00000000010PHASER_ICLK
00000000100PHASER_OCLK
00000011001IMUX_IMUX[20]
00000101001IMUX_IMUX[22]
00001010001LCLK_IO[3]
00001100001LCLK_IO[2]
00010001001IOCLK[2]
00011000001LCLK_IO[0]
00100001001IOCLK[3]
00101000001LCLK_IO[1]
01000010001RCLK_IO[1]
01000100001RCLK_IO[0]
01010000001LCLK_IO[4]
01100000001LCLK_IO[5]
10000010001IOCLK[1]
10000100001IOCLK[0]
10010000001RCLK_IO[2]
10100000001RCLK_IO[3]
virtex7 IO_HP_S switchbox SPEC_INT muxes IMUX_IOI_ICLKDIVP
BitsDestination
MAIN[28][35]MAIN[29][34]IMUX_IOI_ICLKDIVP
Source
00off
01IMUX_CLK[0]
10PHASER_ICLKDIV
virtex7 IO_HP_S switchbox SPEC_INT muxes IMUX_IOI_OCLK[0]
BitsDestination
MAIN[29][28]MAIN[28][25]MAIN[29][32]MAIN[28][33]MAIN[28][31]MAIN[29][24]MAIN[28][29]MAIN[29][30]MAIN[29][20]MAIN[29][18]MAIN[28][19]IMUX_IOI_OCLK[0]
Source
00000000000off
00000000010PHASER_OCLK
00000000100PHASER_OCLK90
00000011001IMUX_IMUX[31]
00000101001LCLK_IO[2]
00001010001IOCLK[2]
00001100001LCLK_IO[0]
00010010001IOCLK[3]
00010100001LCLK_IO[1]
00100100001LCLK_IO[3]
01000001001RCLK_IO[0]
01001000001LCLK_IO[4]
01010000001LCLK_IO[5]
01100000001RCLK_IO[1]
10000001001IOCLK[0]
10001000001RCLK_IO[2]
10010000001RCLK_IO[3]
10100000001IOCLK[1]
virtex7 IO_HP_S switchbox SPEC_INT muxes IMUX_IOI_OCLK[1]
BitsDestination
MAIN[30][28]MAIN[31][25]MAIN[30][32]MAIN[31][33]MAIN[31][31]MAIN[30][24]MAIN[31][29]MAIN[30][30]MAIN[30][20]MAIN[30][18]MAIN[31][19]IMUX_IOI_OCLK[1]
Source
00000000000off
00000000010PHASER_OCLK
00000000100PHASER_OCLK90
00000011001IMUX_IMUX[31]
00000101001LCLK_IO[2]
00001010001IOCLK[2]
00001100001LCLK_IO[0]
00010010001IOCLK[3]
00010100001LCLK_IO[1]
00100100001LCLK_IO[3]
01000001001RCLK_IO[0]
01001000001LCLK_IO[4]
01010000001LCLK_IO[5]
01100000001RCLK_IO[1]
10000001001IOCLK[0]
10001000001RCLK_IO[2]
10010000001RCLK_IO[3]
10100000001IOCLK[1]
virtex7 IO_HP_S switchbox SPEC_INT muxes IMUX_IOI_OCLKDIV[0]
BitsDestination
MAIN[28][47]MAIN[29][46]IMUX_IOI_OCLKDIV[0]
Source
00off
01PHASER_OCLKDIV
10IMUX_IOI_OCLKDIVF[0]
virtex7 IO_HP_S switchbox SPEC_INT muxes IMUX_IOI_OCLKDIV[1]
BitsDestination
MAIN[31][47]MAIN[30][46]IMUX_IOI_OCLKDIV[1]
Source
00off
01PHASER_OCLKDIV
10IMUX_IOI_OCLKDIVF[1]
virtex7 IO_HP_S switchbox SPEC_INT muxes IMUX_IOI_OCLKDIVF[0]
BitsDestination
MAIN[28][55]MAIN[29][54]MAIN[28][57]MAIN[28][61]MAIN[29][62]MAIN[29][60]MAIN[28][59]IMUX_IOI_OCLKDIVF[0]
Source
0000000off
0010001IMUX_IMUX[8]
0010010RCLK_IO[2]
0010100RCLK_IO[3]
0100001LCLK_IO[2]
0100010LCLK_IO[0]
0100100LCLK_IO[1]
0101000LCLK_IO[3]
1000001RCLK_IO[0]
1000010LCLK_IO[4]
1000100LCLK_IO[5]
1001000RCLK_IO[1]
virtex7 IO_HP_S switchbox SPEC_INT muxes IMUX_IOI_OCLKDIVF[1]
BitsDestination
MAIN[31][55]MAIN[30][54]MAIN[31][57]MAIN[31][61]MAIN[30][62]MAIN[30][60]MAIN[31][59]IMUX_IOI_OCLKDIVF[1]
Source
0000000off
0010001IMUX_IMUX[8]
0010010RCLK_IO[2]
0010100RCLK_IO[3]
0100001LCLK_IO[2]
0100010LCLK_IO[0]
0100100LCLK_IO[1]
0101000LCLK_IO[3]
1000001RCLK_IO[0]
1000010LCLK_IO[4]
1000100LCLK_IO[5]
1001000RCLK_IO[1]

Bels ILOGIC

virtex7 IO_HP_S bel ILOGIC pins
PinDirectionILOGIC[0]
CLKinIMUX_IOI_ICLK[0]
CLKBinIMUX_IOI_ICLK[1]
CLKDIVinIMUX_CLK[0]
CLKDIVPinIMUX_IOI_ICLKDIVP
SRinIMUX_CTRL[1]
CE1inIMUX_IMUX[5]
CE2inIMUX_IMUX[14]
BITSLIPinIMUX_IMUX[0]
DYNCLKSELinIMUX_IMUX[37]
DYNCLKDIVSELinIMUX_IMUX[4]
DYNCLKDIVPSELinIMUX_IMUX[10]
OoutOUT_BEL[18]
Q1outOUT_BEL[0]
Q2outOUT_BEL[23]
Q3outOUT_BEL[9]
Q4outOUT_BEL[10]
Q5outOUT_BEL[14]
Q6outOUT_BEL[3]
Q7outOUT_BEL[7]
Q8outOUT_BEL[8]
virtex7 IO_HP_S bel ILOGIC attribute bits
AttributeILOGIC[0]

Bels OLOGIC

virtex7 IO_HP_S bel OLOGIC pins
PinDirectionOLOGIC[0]
CLKinIMUX_IOI_OCLK[0]
CLKBinIMUX_IOI_OCLK[1]
CLKDIVinIMUX_IOI_OCLKDIV[0] invert by MAIN[30][21]
CLKDIVBinIMUX_IOI_OCLKDIV[1]
CLKDIVFinIMUX_IOI_OCLKDIVF[0] invert by MAIN[31][30]
CLKDIVFBinIMUX_IOI_OCLKDIVF[1]
SRinIMUX_CTRL[0]
OCEinIMUX_IMUX[29]
TCEinIMUX_IMUX[1]
D1inIMUX_IMUX[34] invert by MAIN[30][33]
D2inIMUX_IMUX[40] invert by MAIN[31][38]
D3inIMUX_IMUX[44] invert by MAIN[31][42]
D4inIMUX_IMUX[42] invert by MAIN[31][46]
D5inIMUX_IMUX[43] invert by MAIN[30][49]
D6inIMUX_IMUX[45] invert by MAIN[31][50]
D7inIMUX_IMUX[46] invert by MAIN[31][54]
D8inIMUX_IMUX[47] invert by MAIN[30][61]
T1inIMUX_IMUX[15] invert by !MAIN[30][3]
T2inIMUX_IMUX[7] invert by !MAIN[30][7]
T3inIMUX_IMUX[13] invert by !MAIN[31][12]
T4inIMUX_IMUX[21] invert by !MAIN[30][15]
TFBoutOUT_BEL[2]
IOCLKGLITCHoutOUT_BEL[5]
virtex7 IO_HP_S bel OLOGIC attribute bits
AttributeOLOGIC[0]
CLK1_INV!MAIN[31][26]
CLK2_INV!MAIN[31][28]
FFO_INIT bit 0!MAIN[33][33]
FFO_SRVAL bit 0!MAIN[33][31]
FFO_SRVAL bit 1!MAIN[33][43]
FFO_SRVAL bit 2!MAIN[32][44]
FFO_SR_SYNCMAIN[32][30]
FFO_SR_ENABLEMAIN[32][48]
V5_MUX_O[enum: OLOGIC_V5_MUX_O]
FFT_INIT bit 0!MAIN[30][11]
FFT_SRVAL bit 0!MAIN[33][11]
FFT_SRVAL bit 1!MAIN[33][17]
FFT_SRVAL bit 2!MAIN[32][18]
FFT_SR_SYNCMAIN[32][8]
FFT_SR_ENABLEMAIN[33][25]
V5_MUX_T[enum: OLOGIC_V5_MUX_T]
SERDESMAIN[33][9]
SERDES_MODE[enum: IO_SERDES_MODE]
DATA_WIDTH[enum: IO_DATA_WIDTH]
TRISTATE_WIDTH[enum: OLOGIC_TRISTATE_WIDTH]
MISR_ENABLEMAIN[30][47]
MISR_ENABLE_FDBKMAIN[30][53]
MISR_RESETMAIN[30][55]
MISR_CLK_SELECT[enum: OLOGIC_MISR_CLK_SELECT]
CLOCK_RATIO[enum: OLOGIC_CLOCK_RATIO]
SELFHEALMAIN[31][32]
RANK3_USED!MAIN[31][22]
TBYTE_CTLMAIN[32][16]
TBYTE_SRCMAIN[32][20]
virtex7 IO_HP_S enum OLOGIC_V5_MUX_O
OLOGIC[0].V5_MUX_OMAIN[32][46]MAIN[33][49]MAIN[33][27]MAIN[33][29]MAIN[33][47]
NONE00000
D100001
SERDES_SDR00010
LATCH10010
FF01010
DDR00100
virtex7 IO_HP_S enum OLOGIC_V5_MUX_T
OLOGIC[0].V5_MUX_TMAIN[33][3]MAIN[32][4]MAIN[32][6]MAIN[33][5]MAIN[32][2]
NONE00000
T100001
SERDES_SDR00010
LATCH10010
FF01010
DDR00100
virtex7 IO_HP_S enum IO_SERDES_MODE
OLOGIC[0].SERDES_MODEMAIN[33][19]
MASTER0
SLAVE1
virtex7 IO_HP_S enum IO_DATA_WIDTH
OLOGIC[0].DATA_WIDTHMAIN[30][37]MAIN[30][51]MAIN[31][52]MAIN[30][59]MAIN[31][56]MAIN[30][57]MAIN[31][60]MAIN[31][62]MAIN[30][63]
NONE000000000
_2000000001
_3000000010
_4000000100
_5000001000
_6000010000
_7000100000
_8001000000
_10010000000
_14100000000
virtex7 IO_HP_S enum OLOGIC_TRISTATE_WIDTH
OLOGIC[0].TRISTATE_WIDTHMAIN[32][26]
_10
_41
virtex7 IO_HP_S enum OLOGIC_MISR_CLK_SELECT
OLOGIC[0].MISR_CLK_SELECTMAIN[31][58]MAIN[31][48]
NONE00
CLK101
CLK210
virtex7 IO_HP_S enum OLOGIC_CLOCK_RATIO
OLOGIC[0].CLOCK_RATIOMAIN[31][36]MAIN[31][34]MAIN[30][31]MAIN[30][35]
NONE0000
_20001
_30010
_40011
_50101
_61101
_7_81100

Bels IDELAY

virtex7 IO_HP_S bel IDELAY pins
PinDirectionIDELAY[0]
CinIMUX_CLK[1] invert by MAIN[34][24]
CINVCTRLinIMUX_BYP_SITE[6]
CEinIMUX_IMUX[32]
DATAINinIMUX_IMUX[25] invert by MAIN[35][17]
INCinIMUX_IMUX[26]
REGRSTinIMUX_IMUX[12]
LDinIMUX_IMUX[30]
LDPIPEENinIMUX_IMUX[33]
IFDLY[0]inIMUX_FAN_SITE[4]
IFDLY[1]inIMUX_FAN_SITE[5]
IFDLY[2]inIMUX_BYP_SITE[7]
CNTVALUEIN[0]inIMUX_IMUX[41]
CNTVALUEIN[1]inIMUX_IMUX[36]
CNTVALUEIN[2]inIMUX_IMUX[35]
CNTVALUEIN[3]inIMUX_IMUX[38]
CNTVALUEIN[4]inIMUX_IMUX[39]
CNTVALUEOUT[0]outOUT_BEL[20]
CNTVALUEOUT[1]outOUT_BEL[1]
CNTVALUEOUT[2]outOUT_BEL[19]
CNTVALUEOUT[3]outOUT_BEL[15]
CNTVALUEOUT[4]outOUT_BEL[11]
virtex7 IO_HP_S bel IDELAY attribute bits
AttributeIDELAY[0]
ENABLEMAIN[32][9]
IDATAIN_INVMAIN[33][8]
CINVCTRL_SELMAIN[35][25]
FINEDELAYMAIN[29][5]
DELAY_SRC[enum: IDELAY_DELAY_SRC]
DELAY_TYPE[enum: IODELAY_V7_DELAY_TYPE]
HIGH_PERFORMANCE_MODEMAIN[32][45]
PIPE_SELMAIN[34][42]
IDELAY_VALUE_CUR bit 0!MAIN[34][56]
IDELAY_VALUE_CUR bit 1!MAIN[34][50]
IDELAY_VALUE_CUR bit 2!MAIN[34][44]
IDELAY_VALUE_CUR bit 3!MAIN[34][36]
IDELAY_VALUE_CUR bit 4!MAIN[34][30]
IDELAY_VALUE_INIT bit 0MAIN[34][58]
IDELAY_VALUE_INIT bit 1MAIN[34][52]
IDELAY_VALUE_INIT bit 2MAIN[34][46]
IDELAY_VALUE_INIT bit 3MAIN[34][38]
IDELAY_VALUE_INIT bit 4MAIN[34][32]
virtex7 IO_HP_S enum IDELAY_DELAY_SRC
IDELAY[0].DELAY_SRCMAIN[34][6]MAIN[35][5]MAIN[35][7]MAIN[34][8]
NONE0000
IDATAIN0001
OFB0010
DATAIN0100
DELAYCHAIN_OSC1000
virtex7 IO_HP_S enum IODELAY_V7_DELAY_TYPE
IDELAY[0].DELAY_TYPEMAIN[35][49]MAIN[35][55]
FIXED00
VARIABLE01
VAR_LOAD11

Bels ODELAY

virtex7 IO_HP_S bel ODELAY pins
PinDirectionODELAY[0]
CinIMUX_CLK[1] invert by MAIN[36][24]
CINVCTRLinIMUX_BYP_SITE[2]
CEinIMUX_IMUX[2]
INCinIMUX_IMUX[3]
REGRSTinIMUX_IMUX[11]
LDinIMUX_IMUX[28]
LDPIPEENinIMUX_IMUX[27]
OFDLY[0]inIMUX_BYP_SITE[0]
OFDLY[1]inIMUX_BYP_SITE[1]
OFDLY[2]inIMUX_BYP_SITE[5]
CNTVALUEIN[0]inIMUX_IMUX[23]
CNTVALUEIN[1]inIMUX_IMUX[16]
CNTVALUEIN[2]inIMUX_IMUX[17]
CNTVALUEIN[3]inIMUX_IMUX[19]
CNTVALUEIN[4]inIMUX_IMUX[18]
CNTVALUEOUT[0]outOUT_BEL[12]
CNTVALUEOUT[1]outOUT_BEL[4]
CNTVALUEOUT[2]outOUT_BEL[6]
CNTVALUEOUT[3]outOUT_BEL[17]
CNTVALUEOUT[4]outOUT_BEL[21]
DATAOUToutIMUX_SPEC[1]
virtex7 IO_HP_S bel ODELAY attribute bits
AttributeODELAY[0]
ENABLEMAIN[34][9]
ODATAIN_INV!MAIN[35][8]
CINVCTRL_SELMAIN[37][25]
FINEDELAYMAIN[37][41]
DELAY_SRC[enum: ODELAY_DELAY_SRC]
DELAY_TYPE[enum: IODELAY_V7_DELAY_TYPE]
HIGH_PERFORMANCE_MODEMAIN[34][45]
PIPE_SELMAIN[36][42]
ODELAY_VALUE_CUR bit 0!MAIN[36][56]
ODELAY_VALUE_CUR bit 1!MAIN[36][50]
ODELAY_VALUE_CUR bit 2!MAIN[36][44]
ODELAY_VALUE_CUR bit 3!MAIN[36][36]
ODELAY_VALUE_CUR bit 4!MAIN[36][30]
ODELAY_VALUE_INIT bit 0MAIN[36][58]
ODELAY_VALUE_INIT bit 1MAIN[36][52]
ODELAY_VALUE_INIT bit 2MAIN[36][46]
ODELAY_VALUE_INIT bit 3MAIN[36][38]
ODELAY_VALUE_INIT bit 4MAIN[36][32]
virtex7 IO_HP_S enum ODELAY_DELAY_SRC
ODELAY[0].DELAY_SRCMAIN[36][6]MAIN[37][7]MAIN[36][8]
NONE000
ODATAIN001
CLKIN010
DELAYCHAIN_OSC100
virtex7 IO_HP_S enum IODELAY_V7_DELAY_TYPE
ODELAY[0].DELAY_TYPEMAIN[37][49]MAIN[37][55]
FIXED00
VARIABLE01
VAR_LOAD11

Bels IOB

virtex7 IO_HP_S bel IOB pins
PinDirectionIOB[0]
PD_INT_ENinIMUX_FAN_SITE[2]
PU_INT_ENinIMUX_FAN_SITE[1]
KEEPER_INT_ENinIMUX_FAN_SITE[3]
IBUFDISABLEinIMUX_IMUX[9]
DCITERMDISABLEinIMUX_IMUX[6]
virtex7 IO_HP_S bel IOB attribute bits
AttributeIOB[0]
PULL[enum: IOB_PULL]
VRMAIN[39][45]
PULL_DYNAMICMAIN[39][57]
DQS_BIAS_PMAIN[38][34]
DQS_BIAS_NMAIN[39][27]
IBUFDISABLE_ENMAIN[38][24]
DCITERMDISABLE_ENMAIN[39][1]
IBUF_MODE[enum: IOB_IBUF_MODE]
IBUF_VREF_HPMAIN[39][61]
INPUT_MISC bit 0MAIN[38][58]
OUTPUT_ENABLE bit 0MAIN[39][29]
OUTPUT_ENABLE bit 1MAIN[39][31]
OUTPUT_DELAYMAIN[39][11]
DCI_MODE[enum: IOB_DCI_MODE]
DCI_TMAIN[38][0]
DCIUPDATEMODE_ASREQUIRED!MAIN[39][7]
V5_LVDS bit 0MAIN[39][55]
V5_LVDS bit 1MAIN[38][48]
V5_LVDS bit 2MAIN[38][42]
V5_LVDS bit 3MAIN[38][38]
V5_LVDS bit 4MAIN[39][35]
V5_LVDS bit 5MAIN[38][26]
V5_LVDS bit 6MAIN[39][23]
V5_LVDS bit 7MAIN[39][9]
V5_LVDS bit 8MAIN[38][22]
V6_PSLEW bit 0MAIN[39][13]
V6_PSLEW bit 1MAIN[39][33]
V6_PSLEW bit 2MAIN[39][37]
V6_PSLEW bit 3MAIN[39][47]
V6_PSLEW bit 4MAIN[38][50]
V6_NSLEW bit 0MAIN[39][17]
V6_NSLEW bit 1MAIN[38][18]
V6_NSLEW bit 2MAIN[39][25]
V6_NSLEW bit 3MAIN[39][41]
V6_NSLEW bit 4MAIN[39][49]
V7_PDRIVE bit 0MAIN[38][2]
V7_PDRIVE bit 1MAIN[38][32]
V7_PDRIVE bit 2!MAIN[39][15]
V7_PDRIVE bit 3!MAIN[38][14]
V7_PDRIVE bit 4MAIN[39][19]
V7_PDRIVE bit 5!MAIN[38][30]
V7_PDRIVE bit 6MAIN[38][40]
V7_NDRIVE bit 0MAIN[38][12]
V7_NDRIVE bit 1MAIN[38][36]
V7_NDRIVE bit 2MAIN[38][8]
V7_NDRIVE bit 3!MAIN[38][16]
V7_NDRIVE bit 4MAIN[38][28]
V7_NDRIVE bit 5!MAIN[39][39]
V7_NDRIVE bit 6MAIN[39][43]
V7_OUTPUT_MISC bit 0MAIN[39][5]
V7_OUTPUT_MISC bit 1MAIN[39][3]
V7_OUTPUT_MISC bit 2MAIN[38][54]
V7_OUTPUT_MISC bit 3MAIN[38][6]
V7_OUTPUT_MISC bit 4MAIN[38][52]
V7_OUTPUT_MISC bit 5MAIN[38][44]
virtex7 IO_HP_S enum IOB_PULL
IOB[0].PULLMAIN[39][59]MAIN[39][53]MAIN[39][51]
NONE001
PULLUP011
PULLDOWN000
KEEPER101
virtex7 IO_HP_S enum IOB_IBUF_MODE
IOB[0].IBUF_MODEMAIN[38][62]MAIN[39][63]
NONE00
VREF01
CMOS11
virtex7 IO_HP_S enum IOB_DCI_MODE
IOB[0].DCI_MODEMAIN[38][10]MAIN[39][21]
NONE00
OUTPUT01
OUTPUT_HALF10
TERM_SPLIT11

Bel wires

virtex7 IO_HP_S bel wires
WirePins
IMUX_CLK[0]ILOGIC[0].CLKDIV
IMUX_CLK[1]IDELAY[0].C, ODELAY[0].C
IMUX_CTRL[0]OLOGIC[0].SR
IMUX_CTRL[1]ILOGIC[0].SR
IMUX_BYP_SITE[0]ODELAY[0].OFDLY[0]
IMUX_BYP_SITE[1]ODELAY[0].OFDLY[1]
IMUX_BYP_SITE[2]ODELAY[0].CINVCTRL
IMUX_BYP_SITE[5]ODELAY[0].OFDLY[2]
IMUX_BYP_SITE[6]IDELAY[0].CINVCTRL
IMUX_BYP_SITE[7]IDELAY[0].IFDLY[2]
IMUX_FAN_SITE[1]IOB[0].PU_INT_EN
IMUX_FAN_SITE[2]IOB[0].PD_INT_EN
IMUX_FAN_SITE[3]IOB[0].KEEPER_INT_EN
IMUX_FAN_SITE[4]IDELAY[0].IFDLY[0]
IMUX_FAN_SITE[5]IDELAY[0].IFDLY[1]
IMUX_IMUX[0]ILOGIC[0].BITSLIP
IMUX_IMUX[1]OLOGIC[0].TCE
IMUX_IMUX[2]ODELAY[0].CE
IMUX_IMUX[3]ODELAY[0].INC
IMUX_IMUX[4]ILOGIC[0].DYNCLKDIVSEL
IMUX_IMUX[5]ILOGIC[0].CE1
IMUX_IMUX[6]IOB[0].DCITERMDISABLE
IMUX_IMUX[7]OLOGIC[0].T2
IMUX_IMUX[9]IOB[0].IBUFDISABLE
IMUX_IMUX[10]ILOGIC[0].DYNCLKDIVPSEL
IMUX_IMUX[11]ODELAY[0].REGRST
IMUX_IMUX[12]IDELAY[0].REGRST
IMUX_IMUX[13]OLOGIC[0].T3
IMUX_IMUX[14]ILOGIC[0].CE2
IMUX_IMUX[15]OLOGIC[0].T1
IMUX_IMUX[16]ODELAY[0].CNTVALUEIN[1]
IMUX_IMUX[17]ODELAY[0].CNTVALUEIN[2]
IMUX_IMUX[18]ODELAY[0].CNTVALUEIN[4]
IMUX_IMUX[19]ODELAY[0].CNTVALUEIN[3]
IMUX_IMUX[21]OLOGIC[0].T4
IMUX_IMUX[23]ODELAY[0].CNTVALUEIN[0]
IMUX_IMUX[25]IDELAY[0].DATAIN
IMUX_IMUX[26]IDELAY[0].INC
IMUX_IMUX[27]ODELAY[0].LDPIPEEN
IMUX_IMUX[28]ODELAY[0].LD
IMUX_IMUX[29]OLOGIC[0].OCE
IMUX_IMUX[30]IDELAY[0].LD
IMUX_IMUX[32]IDELAY[0].CE
IMUX_IMUX[33]IDELAY[0].LDPIPEEN
IMUX_IMUX[34]OLOGIC[0].D1
IMUX_IMUX[35]IDELAY[0].CNTVALUEIN[2]
IMUX_IMUX[36]IDELAY[0].CNTVALUEIN[1]
IMUX_IMUX[37]ILOGIC[0].DYNCLKSEL
IMUX_IMUX[38]IDELAY[0].CNTVALUEIN[3]
IMUX_IMUX[39]IDELAY[0].CNTVALUEIN[4]
IMUX_IMUX[40]OLOGIC[0].D2
IMUX_IMUX[41]IDELAY[0].CNTVALUEIN[0]
IMUX_IMUX[42]OLOGIC[0].D4
IMUX_IMUX[43]OLOGIC[0].D5
IMUX_IMUX[44]OLOGIC[0].D3
IMUX_IMUX[45]OLOGIC[0].D6
IMUX_IMUX[46]OLOGIC[0].D7
IMUX_IMUX[47]OLOGIC[0].D8
OUT_BEL[0]ILOGIC[0].Q1
OUT_BEL[1]IDELAY[0].CNTVALUEOUT[1]
OUT_BEL[2]OLOGIC[0].TFB
OUT_BEL[3]ILOGIC[0].Q6
OUT_BEL[4]ODELAY[0].CNTVALUEOUT[1]
OUT_BEL[5]OLOGIC[0].IOCLKGLITCH
OUT_BEL[6]ODELAY[0].CNTVALUEOUT[2]
OUT_BEL[7]ILOGIC[0].Q7
OUT_BEL[8]ILOGIC[0].Q8
OUT_BEL[9]ILOGIC[0].Q3
OUT_BEL[10]ILOGIC[0].Q4
OUT_BEL[11]IDELAY[0].CNTVALUEOUT[4]
OUT_BEL[12]ODELAY[0].CNTVALUEOUT[0]
OUT_BEL[14]ILOGIC[0].Q5
OUT_BEL[15]IDELAY[0].CNTVALUEOUT[3]
OUT_BEL[17]ODELAY[0].CNTVALUEOUT[3]
OUT_BEL[18]ILOGIC[0].O
OUT_BEL[19]IDELAY[0].CNTVALUEOUT[2]
OUT_BEL[20]IDELAY[0].CNTVALUEOUT[0]
OUT_BEL[21]ODELAY[0].CNTVALUEOUT[4]
OUT_BEL[23]ILOGIC[0].Q2
IMUX_SPEC[1]ODELAY[0].DATAOUT
IMUX_IOI_ICLK[0]ILOGIC[0].CLK
IMUX_IOI_ICLK[1]ILOGIC[0].CLKB
IMUX_IOI_ICLKDIVPILOGIC[0].CLKDIVP
IMUX_IOI_OCLK[0]OLOGIC[0].CLK
IMUX_IOI_OCLK[1]OLOGIC[0].CLKB
IMUX_IOI_OCLKDIV[0]OLOGIC[0].CLKDIV
IMUX_IOI_OCLKDIV[1]OLOGIC[0].CLKDIVB
IMUX_IOI_OCLKDIVF[0]OLOGIC[0].CLKDIVF
IMUX_IOI_OCLKDIVF[1]OLOGIC[0].CLKDIVFB

Bitstream

virtex7 IO_HP_S rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 0 - - - - - - - - IOB[0]: IBUF_MODE bit 0 - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 2 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 2 OLOGIC[0]: DATA_WIDTH bit 1 - - - - - - IOB[0]: IBUF_MODE bit 1 - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 3 - OLOGIC[0]: invert D8 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 3 - - - - - - - IOB[0]: IBUF_VREF_HP - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 1 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 1 OLOGIC[0]: DATA_WIDTH bit 2 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 0 - OLOGIC[0]: DATA_WIDTH bit 5 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 0 - - - - - - - IOB[0]: PULL bit 2 - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_CLK_SELECT bit 1 - - IDELAY[0]: IDELAY_VALUE_INIT bit 0 - ODELAY[0]: ODELAY_VALUE_INIT bit 0 - IOB[0]: INPUT_MISC bit 0 - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 4 - OLOGIC[0]: DATA_WIDTH bit 3 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 4 - - - - - - - IOB[0]: PULL_DYNAMIC - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 4 - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 0 - ODELAY[0]: ! ODELAY_VALUE_CUR bit 0 - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 6 - OLOGIC[0]: MISR_RESET SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 6 - - - IDELAY[0]: DELAY_TYPE bit 0 - ODELAY[0]: DELAY_TYPE bit 0 - IOB[0]: V5_LVDS bit 0 - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 5 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 5 OLOGIC[0]: invert D7 - - - - - - IOB[0]: V7_OUTPUT_MISC bit 2 - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_ENABLE_FDBK - - - - - - - - IOB[0]: PULL bit 1 - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 6 - - IDELAY[0]: IDELAY_VALUE_INIT bit 1 - ODELAY[0]: ODELAY_VALUE_INIT bit 1 - IOB[0]: V7_OUTPUT_MISC bit 4 - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 7 - - - - - - - - IOB[0]: PULL bit 0 - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D6 - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 1 - ODELAY[0]: ! ODELAY_VALUE_CUR bit 1 - IOB[0]: V6_PSLEW bit 4 - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D5 - - OLOGIC[0]: V5_MUX_O bit 3 - IDELAY[0]: DELAY_TYPE bit 1 - ODELAY[0]: DELAY_TYPE bit 1 - IOB[0]: V6_NSLEW bit 4 - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_CLK_SELECT bit 0 OLOGIC[0]: FFO_SR_ENABLE - - - - - IOB[0]: V5_LVDS bit 1 - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIV[0] bit 1 - OLOGIC[0]: MISR_ENABLE SPEC_INT: mux IMUX_IOI_OCLKDIV[1] bit 1 - OLOGIC[0]: V5_MUX_O bit 0 - - - - - IOB[0]: V6_PSLEW bit 3 - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIV[0] bit 0 SPEC_INT: mux IMUX_IOI_OCLKDIV[1] bit 0 OLOGIC[0]: invert D4 OLOGIC[0]: V5_MUX_O bit 4 - IDELAY[0]: IDELAY_VALUE_INIT bit 2 - ODELAY[0]: ODELAY_VALUE_INIT bit 2 - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[0]: HIGH_PERFORMANCE_MODE - ODELAY[0]: HIGH_PERFORMANCE_MODE - - - - IOB[0]: VR - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFO_SRVAL bit 2 - IDELAY[0]: ! IDELAY_VALUE_CUR bit 2 - ODELAY[0]: ! ODELAY_VALUE_CUR bit 2 - IOB[0]: V7_OUTPUT_MISC bit 5 - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFO_SRVAL bit 1 - - - - - IOB[0]: V7_NDRIVE bit 6 - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D3 - - IDELAY[0]: PIPE_SEL - ODELAY[0]: PIPE_SEL - IOB[0]: V5_LVDS bit 2 - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ODELAY[0]: FINEDELAY - IOB[0]: V6_NSLEW bit 3 - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: V7_PDRIVE bit 6 - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: ! V7_NDRIVE bit 5 - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D2 - - IDELAY[0]: IDELAY_VALUE_INIT bit 3 - ODELAY[0]: ODELAY_VALUE_INIT bit 3 - IOB[0]: V5_LVDS bit 3 - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 8 - - - - - - - - IOB[0]: V6_PSLEW bit 2 - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: CLOCK_RATIO bit 3 - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 3 - ODELAY[0]: ! ODELAY_VALUE_CUR bit 3 - IOB[0]: V7_NDRIVE bit 1 - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLKDIVP bit 1 - OLOGIC[0]: CLOCK_RATIO bit 0 - - - - - - - - IOB[0]: V5_LVDS bit 4 - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLKDIVP bit 0 - OLOGIC[0]: CLOCK_RATIO bit 2 - - - - - - IOB[0]: DQS_BIAS_P - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 7 - OLOGIC[0]: invert D1 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 7 - OLOGIC[0]: ! FFO_INIT bit 0 - - - - - IOB[0]: V6_PSLEW bit 1 - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 8 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 8 OLOGIC[0]: SELFHEAL - - IDELAY[0]: IDELAY_VALUE_INIT bit 4 - ODELAY[0]: ODELAY_VALUE_INIT bit 4 - IOB[0]: V7_PDRIVE bit 1 - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 6 - OLOGIC[0]: CLOCK_RATIO bit 1 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 6 - OLOGIC[0]: ! FFO_SRVAL bit 0 - - - - - IOB[0]: OUTPUT_ENABLE bit 1 - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 3 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 3 OLOGIC[0]: invert CLKDIVF OLOGIC[0]: FFO_SR_SYNC - IDELAY[0]: ! IDELAY_VALUE_CUR bit 4 - ODELAY[0]: ! ODELAY_VALUE_CUR bit 4 - IOB[0]: ! V7_PDRIVE bit 5 - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 4 - - SPEC_INT: mux IMUX_IOI_OCLK[1] bit 4 - OLOGIC[0]: V5_MUX_O bit 1 - - - - - IOB[0]: OUTPUT_ENABLE bit 0 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 10 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 10 OLOGIC[0]: ! CLK2_INV - - - - - - IOB[0]: V7_NDRIVE bit 4 - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_O bit 2 - - - - - IOB[0]: DQS_BIAS_N - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! CLK1_INV OLOGIC[0]: TRISTATE_WIDTH bit 0 - - - - - IOB[0]: V5_LVDS bit 5 - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 9 - - SPEC_INT: mux IMUX_IOI_OCLK[1] bit 9 - OLOGIC[0]: FFT_SR_ENABLE - IDELAY[0]: CINVCTRL_SEL - ODELAY[0]: CINVCTRL_SEL - IOB[0]: V6_NSLEW bit 2 - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 5 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 5 - - - IDELAY[0]: invert C - ODELAY[0]: invert C - IOB[0]: IBUFDISABLE_EN - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: V5_LVDS bit 6 - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! RANK3_USED - - - - - - IOB[0]: V5_LVDS bit 8 - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert CLKDIV - - - - - - - - IOB[0]: DCI_MODE bit 0 - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 2 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 2 - OLOGIC[0]: TBYTE_SRC - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 0 - - SPEC_INT: mux IMUX_IOI_OCLK[1] bit 0 - OLOGIC[0]: SERDES_MODE bit 0 - - - - - IOB[0]: V7_PDRIVE bit 4 - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 1 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 1 - OLOGIC[0]: ! FFT_SRVAL bit 2 - - - - - IOB[0]: V6_NSLEW bit 1 - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 8 - - SPEC_INT: mux IMUX_IOI_ICLK[1] bit 8 - OLOGIC[0]: ! FFT_SRVAL bit 1 - IDELAY[0]: invert DATAIN - - - IOB[0]: V6_NSLEW bit 0 - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 4 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 4 - OLOGIC[0]: TBYTE_CTL - - - - - IOB[0]: ! V7_NDRIVE bit 3 - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 7 - OLOGIC[0]: !invert T4 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 7 - - - - - - - IOB[0]: ! V7_PDRIVE bit 2 - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 5 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 5 - - - - - - - IOB[0]: ! V7_PDRIVE bit 3 - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 3 - - SPEC_INT: mux IMUX_IOI_ICLK[1] bit 3 - - - - - - - IOB[0]: V6_PSLEW bit 0 - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 10 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 10 OLOGIC[0]: !invert T3 - - - - - - IOB[0]: V7_NDRIVE bit 0 - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 9 - OLOGIC[0]: ! FFT_INIT bit 0 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 9 - OLOGIC[0]: ! FFT_SRVAL bit 0 - - - - - IOB[0]: OUTPUT_DELAY - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 6 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 6 - - - - - - - IOB[0]: DCI_MODE bit 1 - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[0]: ENABLE OLOGIC[0]: SERDES ODELAY[0]: ENABLE - - - - IOB[0]: V5_LVDS bit 7 - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFT_SR_SYNC IDELAY[0]: IDATAIN_INV IDELAY[0]: DELAY_SRC bit 0 ODELAY[0]: ! ODATAIN_INV ODELAY[0]: DELAY_SRC bit 0 - IOB[0]: V7_NDRIVE bit 2 - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: !invert T2 - - - - IDELAY[0]: DELAY_SRC bit 1 - ODELAY[0]: DELAY_SRC bit 1 - IOB[0]: ! DCIUPDATEMODE_ASREQUIRED - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_T bit 2 - IDELAY[0]: DELAY_SRC bit 3 - ODELAY[0]: DELAY_SRC bit 2 - IOB[0]: V7_OUTPUT_MISC bit 3 - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[0]: FINEDELAY - - - OLOGIC[0]: V5_MUX_T bit 1 - IDELAY[0]: DELAY_SRC bit 2 - - - IOB[0]: V7_OUTPUT_MISC bit 0 - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_T bit 3 - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 0 - OLOGIC[0]: !invert T1 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 0 - OLOGIC[0]: V5_MUX_T bit 4 - - - - - IOB[0]: V7_OUTPUT_MISC bit 1 - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 1 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 1 - OLOGIC[0]: V5_MUX_T bit 0 - - - - - IOB[0]: V7_PDRIVE bit 0 - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 2 - - SPEC_INT: mux IMUX_IOI_ICLK[1] bit 2 - - - - - - - IOB[0]: DCITERMDISABLE_EN - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: DCI_T - - -
### Bitstream
virtex7 IO_HP_S rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLK_INV_EN
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[0] -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[2]
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.OCLK2 -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[1]
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[0] - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.CLKDIV - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLKDIV_INV_EN - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[2] - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLKDIVP_INV_EN ILOGIC[0]:IFF_DELAY_ENABLE -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[4] - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.CLKDIVP - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[3] - - ILOGIC[0]:IFF_TSBYPASS_ENABLE
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[0] - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[1] - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[2] ILOGIC[0]:TSBYPASS_MUX[0] -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[3] - - ~ILOGIC[0]:INV.D
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_RATE[0] - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:BITSLIP_ENABLE - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SERDES_MODE[0] - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:I_TSBYPASS_ENABLE
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SERDES - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[1] - - ILOGIC[0]:I_DELAY_ENABLE
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:RANK23_DLY - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DDR_CLK_EDGE[1] - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DDR_CLK_EDGE[0] - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF4_INIT -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF4_SRVAL
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF3_INIT -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF3_SRVAL
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:NUM_CE[0] - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF2_INIT -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF2_SRVAL
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF1_INIT -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF_LATCH - - ~ILOGIC[0]:IFF1_SRVAL
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IFF_SR_USED - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SRTYPE[0]
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:D_EMU2 -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:D_EMU1
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.OCLK1 -
ILOGIC[0]:BITSLIP_ENABLE 0.F26.B43
ILOGIC[0]:DYN_CLKDIVP_INV_EN 0.F27.B52
ILOGIC[0]:DYN_CLKDIV_INV_EN 0.F27.B54
ILOGIC[0]:DYN_CLK_INV_EN 0.F29.B63
ILOGIC[0]:D_EMU1 0.F29.B1
ILOGIC[0]:D_EMU2 0.F28.B2
ILOGIC[0]:IFF_DELAY_ENABLE 0.F28.B52
ILOGIC[0]:IFF_SR_USED 0.F27.B6
ILOGIC[0]:IFF_TSBYPASS_ENABLE 0.F29.B49
ILOGIC[0]:INV.CLKDIV 0.F26.B55
ILOGIC[0]:INV.CLKDIVP 0.F27.B50
ILOGIC[0]:INV.OCLK1 0.F28.B0
ILOGIC[0]:INV.OCLK2 0.F28.B60
ILOGIC[0]:I_DELAY_ENABLE 0.F29.B37
ILOGIC[0]:I_TSBYPASS_ENABLE 0.F29.B39
ILOGIC[0]:RANK23_DLY 0.F27.B36
ILOGIC[0]:SERDES 0.F27.B38
non-inverted [0]
ILOGIC[0]:DATA_RATE 0.F27.B44
DDR 0
SDR 1
ILOGIC[0]:DATA_WIDTH 0.F26.B45 0.F27.B46 0.F26.B47 0.F27.B48
NONE 0 0 0 0
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
10 1 0 1 0
14 1 1 1 0
ILOGIC[0]:DDR_CLK_EDGE 0.F26.B35 0.F27.B34
SAME_EDGE_PIPELINED 0 0
OPPOSITE_EDGE 0 1
SAME_EDGE 1 0
ILOGIC[0]:IFF1_INIT 0.F28.B8
ILOGIC[0]:IFF1_SRVAL 0.F29.B7
ILOGIC[0]:IFF2_INIT 0.F28.B12
ILOGIC[0]:IFF2_SRVAL 0.F29.B11
ILOGIC[0]:IFF3_INIT 0.F28.B22
ILOGIC[0]:IFF3_SRVAL 0.F29.B21
ILOGIC[0]:IFF4_INIT 0.F28.B30
ILOGIC[0]:IFF4_SRVAL 0.F29.B29
ILOGIC[0]:IFF_LATCH 0.F26.B7
ILOGIC[0]:INV.D 0.F29.B45
inverted ~[0]
ILOGIC[0]:INTERFACE_TYPE 0.F26.B51 0.F26.B49 0.F26.B53 0.F26.B37 0.F26.B57
MEMORY 0 0 0 0 0
NETWORKING 0 0 0 0 1
MEMORY_DDR3 0 0 1 1 1
MEMORY_DDR3_V6 0 1 0 1 1
OVERSAMPLE 1 0 0 1 1
ILOGIC[0]:INV.CLK 0.F29.B61 0.F29.B59 0.F28.B62
inverted ~[2] ~[1] ~[0]
ILOGIC[0]:NUM_CE 0.F27.B16
1 0
2 1
ILOGIC[0]:SERDES_MODE 0.F27.B42
MASTER 0
SLAVE 1
ILOGIC[0]:SRTYPE 0.F29.B3
ASYNC 0
SYNC 1
ILOGIC[0]:TSBYPASS_MUX 0.F28.B46
T 0
GND 1

Tile IO_HP_N

Cells: 1

Switchbox SPEC_INT

virtex7 IO_HP_N switchbox SPEC_INT permanent buffers
DestinationSource
IMUX_SPEC[0]IMUX_IOI_OCLKDIV[0]
IMUX_SPEC[2]IMUX_IOI_OCLK[0]
virtex7 IO_HP_N switchbox SPEC_INT muxes IMUX_IOI_ICLK[0]
BitsDestination
MAIN[28][51]MAIN[29][52]MAIN[29][46]MAIN[29][48]MAIN[28][53]MAIN[28][49]MAIN[28][47]MAIN[29][50]MAIN[29][62]MAIN[28][61]MAIN[29][60]IMUX_IOI_ICLK[0]
Source
00000000000off
00000000010PHASER_ICLK
00000000100PHASER_OCLK
00000011001IMUX_IMUX[20]
00000101001IMUX_IMUX[22]
00001010001LCLK_IO[3]
00001100001LCLK_IO[2]
00010001001IOCLK[2]
00011000001LCLK_IO[0]
00100001001IOCLK[3]
00101000001LCLK_IO[1]
01000010001RCLK_IO[1]
01000100001RCLK_IO[0]
01010000001LCLK_IO[4]
01100000001LCLK_IO[5]
10000010001IOCLK[1]
10000100001IOCLK[0]
10010000001RCLK_IO[2]
10100000001RCLK_IO[3]
virtex7 IO_HP_N switchbox SPEC_INT muxes IMUX_IOI_ICLK[1]
BitsDestination
MAIN[31][51]MAIN[30][52]MAIN[30][46]MAIN[30][48]MAIN[31][53]MAIN[31][49]MAIN[31][47]MAIN[30][50]MAIN[30][62]MAIN[31][61]MAIN[30][60]IMUX_IOI_ICLK[1]
Source
00000000000off
00000000010PHASER_ICLK
00000000100PHASER_OCLK
00000011001IMUX_IMUX[20]
00000101001IMUX_IMUX[22]
00001010001LCLK_IO[3]
00001100001LCLK_IO[2]
00010001001IOCLK[2]
00011000001LCLK_IO[0]
00100001001IOCLK[3]
00101000001LCLK_IO[1]
01000010001RCLK_IO[1]
01000100001RCLK_IO[0]
01010000001LCLK_IO[4]
01100000001LCLK_IO[5]
10000010001IOCLK[1]
10000100001IOCLK[0]
10010000001RCLK_IO[2]
10100000001RCLK_IO[3]
virtex7 IO_HP_N switchbox SPEC_INT muxes IMUX_IOI_ICLKDIVP
BitsDestination
MAIN[29][28]MAIN[28][29]IMUX_IOI_ICLKDIVP
Source
00off
01IMUX_CLK[0]
10PHASER_ICLKDIV
virtex7 IO_HP_N switchbox SPEC_INT muxes IMUX_IOI_OCLK[0]
BitsDestination
MAIN[28][35]MAIN[29][38]MAIN[28][31]MAIN[29][30]MAIN[29][32]MAIN[28][39]MAIN[29][34]MAIN[28][33]MAIN[28][43]MAIN[28][45]MAIN[29][44]IMUX_IOI_OCLK[0]
Source
00000000000off
00000000010PHASER_OCLK
00000000100PHASER_OCLK90
00000011001IMUX_IMUX[31]
00000101001LCLK_IO[2]
00001010001IOCLK[2]
00001100001LCLK_IO[0]
00010010001IOCLK[3]
00010100001LCLK_IO[1]
00100100001LCLK_IO[3]
01000001001RCLK_IO[0]
01001000001LCLK_IO[4]
01010000001LCLK_IO[5]
01100000001RCLK_IO[1]
10000001001IOCLK[0]
10001000001RCLK_IO[2]
10010000001RCLK_IO[3]
10100000001IOCLK[1]
virtex7 IO_HP_N switchbox SPEC_INT muxes IMUX_IOI_OCLK[1]
BitsDestination
MAIN[31][35]MAIN[30][38]MAIN[31][31]MAIN[30][30]MAIN[30][32]MAIN[31][39]MAIN[30][34]MAIN[31][33]MAIN[31][43]MAIN[31][45]MAIN[30][44]IMUX_IOI_OCLK[1]
Source
00000000000off
00000000010PHASER_OCLK
00000000100PHASER_OCLK90
00000011001IMUX_IMUX[31]
00000101001LCLK_IO[2]
00001010001IOCLK[2]
00001100001LCLK_IO[0]
00010010001IOCLK[3]
00010100001LCLK_IO[1]
00100100001LCLK_IO[3]
01000001001RCLK_IO[0]
01001000001LCLK_IO[4]
01010000001LCLK_IO[5]
01100000001RCLK_IO[1]
10000001001IOCLK[0]
10001000001RCLK_IO[2]
10010000001RCLK_IO[3]
10100000001IOCLK[1]
virtex7 IO_HP_N switchbox SPEC_INT muxes IMUX_IOI_OCLKDIV[0]
BitsDestination
MAIN[29][16]MAIN[28][17]IMUX_IOI_OCLKDIV[0]
Source
00off
01PHASER_OCLKDIV
10IMUX_IOI_OCLKDIVF[0]
virtex7 IO_HP_N switchbox SPEC_INT muxes IMUX_IOI_OCLKDIV[1]
BitsDestination
MAIN[30][16]MAIN[31][17]IMUX_IOI_OCLKDIV[1]
Source
00off
01PHASER_OCLKDIV
10IMUX_IOI_OCLKDIVF[1]
virtex7 IO_HP_N switchbox SPEC_INT muxes IMUX_IOI_OCLKDIVF[0]
BitsDestination
MAIN[29][8]MAIN[28][9]MAIN[29][6]MAIN[29][2]MAIN[28][1]MAIN[28][3]MAIN[29][4]IMUX_IOI_OCLKDIVF[0]
Source
0000000off
0010001IMUX_IMUX[8]
0010010RCLK_IO[2]
0010100RCLK_IO[3]
0100001LCLK_IO[2]
0100010LCLK_IO[0]
0100100LCLK_IO[1]
0101000LCLK_IO[3]
1000001RCLK_IO[0]
1000010LCLK_IO[4]
1000100LCLK_IO[5]
1001000RCLK_IO[1]
virtex7 IO_HP_N switchbox SPEC_INT muxes IMUX_IOI_OCLKDIVF[1]
BitsDestination
MAIN[30][8]MAIN[31][9]MAIN[30][6]MAIN[30][2]MAIN[31][1]MAIN[31][3]MAIN[30][4]IMUX_IOI_OCLKDIVF[1]
Source
0000000off
0010001IMUX_IMUX[8]
0010010RCLK_IO[2]
0010100RCLK_IO[3]
0100001LCLK_IO[2]
0100010LCLK_IO[0]
0100100LCLK_IO[1]
0101000LCLK_IO[3]
1000001RCLK_IO[0]
1000010LCLK_IO[4]
1000100LCLK_IO[5]
1001000RCLK_IO[1]

Bels ILOGIC

virtex7 IO_HP_N bel ILOGIC pins
PinDirectionILOGIC[0]
CLKinIMUX_IOI_ICLK[0]
CLKBinIMUX_IOI_ICLK[1]
CLKDIVinIMUX_CLK[0]
CLKDIVPinIMUX_IOI_ICLKDIVP
SRinIMUX_CTRL[1]
CE1inIMUX_IMUX[5]
CE2inIMUX_IMUX[14]
BITSLIPinIMUX_IMUX[0]
DYNCLKSELinIMUX_IMUX[37]
DYNCLKDIVSELinIMUX_IMUX[4]
DYNCLKDIVPSELinIMUX_IMUX[10]
OoutOUT_BEL[18]
Q1outOUT_BEL[0]
Q2outOUT_BEL[23]
Q3outOUT_BEL[9]
Q4outOUT_BEL[10]
Q5outOUT_BEL[14]
Q6outOUT_BEL[3]
Q7outOUT_BEL[7]
Q8outOUT_BEL[8]
virtex7 IO_HP_N bel ILOGIC attribute bits
AttributeILOGIC[0]

Bels OLOGIC

virtex7 IO_HP_N bel OLOGIC pins
PinDirectionOLOGIC[0]
CLKinIMUX_IOI_OCLK[0]
CLKBinIMUX_IOI_OCLK[1]
CLKDIVinIMUX_IOI_OCLKDIV[0] invert by MAIN[31][42]
CLKDIVBinIMUX_IOI_OCLKDIV[1]
CLKDIVFinIMUX_IOI_OCLKDIVF[0] invert by MAIN[30][33]
CLKDIVFBinIMUX_IOI_OCLKDIVF[1]
SRinIMUX_CTRL[0]
OCEinIMUX_IMUX[29]
TCEinIMUX_IMUX[1]
D1inIMUX_IMUX[34] invert by MAIN[31][30]
D2inIMUX_IMUX[40] invert by MAIN[30][25]
D3inIMUX_IMUX[44] invert by MAIN[30][21]
D4inIMUX_IMUX[42] invert by MAIN[30][17]
D5inIMUX_IMUX[43] invert by MAIN[31][14]
D6inIMUX_IMUX[45] invert by MAIN[30][13]
D7inIMUX_IMUX[46] invert by MAIN[30][9]
D8inIMUX_IMUX[47] invert by MAIN[31][2]
T1inIMUX_IMUX[15] invert by !MAIN[31][60]
T2inIMUX_IMUX[7] invert by !MAIN[31][56]
T3inIMUX_IMUX[13] invert by !MAIN[30][51]
T4inIMUX_IMUX[21] invert by !MAIN[31][48]
TFBoutOUT_BEL[2]
IOCLKGLITCHoutOUT_BEL[5]
virtex7 IO_HP_N bel OLOGIC attribute bits
AttributeOLOGIC[0]
CLK1_INV!MAIN[30][37]
CLK2_INV!MAIN[30][35]
FFO_INIT bit 0!MAIN[32][30]
FFO_SRVAL bit 0!MAIN[32][32]
FFO_SRVAL bit 1!MAIN[32][20]
FFO_SRVAL bit 2!MAIN[33][19]
FFO_SR_SYNCMAIN[33][33]
FFO_SR_ENABLEMAIN[33][15]
V5_MUX_O[enum: OLOGIC_V5_MUX_O]
FFT_INIT bit 0!MAIN[31][52]
FFT_SRVAL bit 0!MAIN[32][52]
FFT_SRVAL bit 1!MAIN[32][46]
FFT_SRVAL bit 2!MAIN[33][45]
FFT_SR_SYNCMAIN[33][55]
FFT_SR_ENABLEMAIN[32][38]
V5_MUX_T[enum: OLOGIC_V5_MUX_T]
SERDESMAIN[32][54]
SERDES_MODE[enum: IO_SERDES_MODE]
DATA_WIDTH[enum: IO_DATA_WIDTH]
TRISTATE_WIDTH[enum: OLOGIC_TRISTATE_WIDTH]
MISR_ENABLEMAIN[31][16]
MISR_ENABLE_FDBKMAIN[31][10]
MISR_RESETMAIN[31][8]
MISR_CLK_SELECT[enum: OLOGIC_MISR_CLK_SELECT]
CLOCK_RATIO[enum: OLOGIC_CLOCK_RATIO]
SELFHEALMAIN[30][31]
RANK3_USED!MAIN[30][41]
TBYTE_CTLMAIN[33][47]
TBYTE_SRCMAIN[33][43]
virtex7 IO_HP_N enum OLOGIC_V5_MUX_O
OLOGIC[0].V5_MUX_OMAIN[33][17]MAIN[32][14]MAIN[32][36]MAIN[32][34]MAIN[32][16]
NONE00000
D100001
SERDES_SDR00010
LATCH10010
FF01010
DDR00100
virtex7 IO_HP_N enum OLOGIC_V5_MUX_T
OLOGIC[0].V5_MUX_TMAIN[32][60]MAIN[33][59]MAIN[33][57]MAIN[32][58]MAIN[33][61]
NONE00000
T100001
SERDES_SDR00010
LATCH10010
FF01010
DDR00100
virtex7 IO_HP_N enum IO_SERDES_MODE
OLOGIC[0].SERDES_MODEMAIN[32][44]
MASTER0
SLAVE1
virtex7 IO_HP_N enum IO_DATA_WIDTH
OLOGIC[0].DATA_WIDTHMAIN[31][26]MAIN[31][12]MAIN[30][11]MAIN[31][4]MAIN[30][7]MAIN[31][6]MAIN[30][3]MAIN[30][1]MAIN[31][0]
NONE000000000
_2000000001
_3000000010
_4000000100
_5000001000
_6000010000
_7000100000
_8001000000
_10010000000
_14100000000
virtex7 IO_HP_N enum OLOGIC_TRISTATE_WIDTH
OLOGIC[0].TRISTATE_WIDTHMAIN[33][37]
_10
_41
virtex7 IO_HP_N enum OLOGIC_MISR_CLK_SELECT
OLOGIC[0].MISR_CLK_SELECTMAIN[30][5]MAIN[30][15]
NONE00
CLK101
CLK210
virtex7 IO_HP_N enum OLOGIC_CLOCK_RATIO
OLOGIC[0].CLOCK_RATIOMAIN[30][27]MAIN[30][29]MAIN[31][32]MAIN[31][28]
NONE0000
_20001
_30010
_40011
_50101
_61101
_7_81100

Bels IDELAY

virtex7 IO_HP_N bel IDELAY pins
PinDirectionIDELAY[0]
CinIMUX_CLK[1] invert by MAIN[35][39]
CINVCTRLinIMUX_BYP_SITE[6]
CEinIMUX_IMUX[32]
DATAINinIMUX_IMUX[25] invert by MAIN[34][46]
INCinIMUX_IMUX[26]
REGRSTinIMUX_IMUX[12]
LDinIMUX_IMUX[30]
LDPIPEENinIMUX_IMUX[33]
IFDLY[0]inIMUX_FAN_SITE[4]
IFDLY[1]inIMUX_FAN_SITE[5]
IFDLY[2]inIMUX_BYP_SITE[7]
CNTVALUEIN[0]inIMUX_IMUX[41]
CNTVALUEIN[1]inIMUX_IMUX[36]
CNTVALUEIN[2]inIMUX_IMUX[35]
CNTVALUEIN[3]inIMUX_IMUX[38]
CNTVALUEIN[4]inIMUX_IMUX[39]
CNTVALUEOUT[0]outOUT_BEL[20]
CNTVALUEOUT[1]outOUT_BEL[1]
CNTVALUEOUT[2]outOUT_BEL[19]
CNTVALUEOUT[3]outOUT_BEL[15]
CNTVALUEOUT[4]outOUT_BEL[11]
virtex7 IO_HP_N bel IDELAY attribute bits
AttributeIDELAY[0]
ENABLEMAIN[33][54]
IDATAIN_INVMAIN[32][55]
CINVCTRL_SELMAIN[34][38]
FINEDELAYMAIN[28][58]
DELAY_SRC[enum: IDELAY_DELAY_SRC]
DELAY_TYPE[enum: IODELAY_V7_DELAY_TYPE]
HIGH_PERFORMANCE_MODEMAIN[33][18]
PIPE_SELMAIN[35][21]
IDELAY_VALUE_CUR bit 0!MAIN[35][7]
IDELAY_VALUE_CUR bit 1!MAIN[35][13]
IDELAY_VALUE_CUR bit 2!MAIN[35][19]
IDELAY_VALUE_CUR bit 3!MAIN[35][27]
IDELAY_VALUE_CUR bit 4!MAIN[35][33]
IDELAY_VALUE_INIT bit 0MAIN[35][5]
IDELAY_VALUE_INIT bit 1MAIN[35][11]
IDELAY_VALUE_INIT bit 2MAIN[35][17]
IDELAY_VALUE_INIT bit 3MAIN[35][25]
IDELAY_VALUE_INIT bit 4MAIN[35][31]
virtex7 IO_HP_N enum IDELAY_DELAY_SRC
IDELAY[0].DELAY_SRCMAIN[35][57]MAIN[34][58]MAIN[34][56]MAIN[35][55]
NONE0000
IDATAIN0001
OFB0010
DATAIN0100
DELAYCHAIN_OSC1000
virtex7 IO_HP_N enum IODELAY_V7_DELAY_TYPE
IDELAY[0].DELAY_TYPEMAIN[34][14]MAIN[34][8]
FIXED00
VARIABLE01
VAR_LOAD11

Bels ODELAY

virtex7 IO_HP_N bel ODELAY pins
PinDirectionODELAY[0]
CinIMUX_CLK[1] invert by MAIN[37][39]
CINVCTRLinIMUX_BYP_SITE[2]
CEinIMUX_IMUX[2]
INCinIMUX_IMUX[3]
REGRSTinIMUX_IMUX[11]
LDinIMUX_IMUX[28]
LDPIPEENinIMUX_IMUX[27]
OFDLY[0]inIMUX_BYP_SITE[0]
OFDLY[1]inIMUX_BYP_SITE[1]
OFDLY[2]inIMUX_BYP_SITE[5]
CNTVALUEIN[0]inIMUX_IMUX[23]
CNTVALUEIN[1]inIMUX_IMUX[16]
CNTVALUEIN[2]inIMUX_IMUX[17]
CNTVALUEIN[3]inIMUX_IMUX[19]
CNTVALUEIN[4]inIMUX_IMUX[18]
CNTVALUEOUT[0]outOUT_BEL[12]
CNTVALUEOUT[1]outOUT_BEL[4]
CNTVALUEOUT[2]outOUT_BEL[6]
CNTVALUEOUT[3]outOUT_BEL[17]
CNTVALUEOUT[4]outOUT_BEL[21]
DATAOUToutIMUX_SPEC[1]
virtex7 IO_HP_N bel ODELAY attribute bits
AttributeODELAY[0]
ENABLEMAIN[35][54]
ODATAIN_INV!MAIN[34][55]
CINVCTRL_SELMAIN[36][38]
FINEDELAYMAIN[36][22]
DELAY_SRC[enum: ODELAY_DELAY_SRC]
DELAY_TYPE[enum: IODELAY_V7_DELAY_TYPE]
HIGH_PERFORMANCE_MODEMAIN[35][18]
PIPE_SELMAIN[37][21]
ODELAY_VALUE_CUR bit 0!MAIN[37][7]
ODELAY_VALUE_CUR bit 1!MAIN[37][13]
ODELAY_VALUE_CUR bit 2!MAIN[37][19]
ODELAY_VALUE_CUR bit 3!MAIN[37][27]
ODELAY_VALUE_CUR bit 4!MAIN[37][33]
ODELAY_VALUE_INIT bit 0MAIN[37][5]
ODELAY_VALUE_INIT bit 1MAIN[37][11]
ODELAY_VALUE_INIT bit 2MAIN[37][17]
ODELAY_VALUE_INIT bit 3MAIN[37][25]
ODELAY_VALUE_INIT bit 4MAIN[37][31]
virtex7 IO_HP_N enum ODELAY_DELAY_SRC
ODELAY[0].DELAY_SRCMAIN[37][57]MAIN[36][56]MAIN[37][55]
NONE000
ODATAIN001
CLKIN010
DELAYCHAIN_OSC100
virtex7 IO_HP_N enum IODELAY_V7_DELAY_TYPE
ODELAY[0].DELAY_TYPEMAIN[36][14]MAIN[36][8]
FIXED00
VARIABLE01
VAR_LOAD11

Bels IOB

virtex7 IO_HP_N bel IOB pins
PinDirectionIOB[0]
PD_INT_ENinIMUX_FAN_SITE[2]
PU_INT_ENinIMUX_FAN_SITE[1]
KEEPER_INT_ENinIMUX_FAN_SITE[3]
IBUFDISABLEinIMUX_IMUX[9]
DCITERMDISABLEinIMUX_IMUX[6]
virtex7 IO_HP_N bel IOB attribute bits
AttributeIOB[0]
PULL[enum: IOB_PULL]
VRMAIN[38][18]
PULL_DYNAMICMAIN[38][6]
DQS_BIAS_PMAIN[39][29]
DQS_BIAS_NMAIN[38][36]
IBUFDISABLE_ENMAIN[39][39]
DCITERMDISABLE_ENMAIN[38][62]
IBUF_MODE[enum: IOB_IBUF_MODE]
IBUF_VREF_HPMAIN[38][2]
INPUT_MISC bit 0MAIN[39][5]
OUTPUT_ENABLE bit 0MAIN[38][32]
OUTPUT_ENABLE bit 1MAIN[38][34]
OUTPUT_DELAYMAIN[38][52]
DCI_MODE[enum: IOB_DCI_MODE]
DCI_TMAIN[39][63]
DCIUPDATEMODE_ASREQUIRED!MAIN[38][56]
V5_LVDS bit 0MAIN[38][8]
V5_LVDS bit 1MAIN[39][15]
V5_LVDS bit 2MAIN[39][21]
V5_LVDS bit 3MAIN[39][25]
V5_LVDS bit 4MAIN[38][28]
V5_LVDS bit 5MAIN[39][37]
V5_LVDS bit 6MAIN[38][40]
V5_LVDS bit 7MAIN[38][54]
V5_LVDS bit 8MAIN[39][41]
V6_PSLEW bit 0MAIN[38][50]
V6_PSLEW bit 1MAIN[38][30]
V6_PSLEW bit 2MAIN[38][26]
V6_PSLEW bit 3MAIN[38][16]
V6_PSLEW bit 4MAIN[39][13]
V6_NSLEW bit 0MAIN[38][46]
V6_NSLEW bit 1MAIN[39][45]
V6_NSLEW bit 2MAIN[38][38]
V6_NSLEW bit 3MAIN[38][22]
V6_NSLEW bit 4MAIN[38][14]
V7_PDRIVE bit 0MAIN[39][61]
V7_PDRIVE bit 1MAIN[39][31]
V7_PDRIVE bit 2!MAIN[38][48]
V7_PDRIVE bit 3!MAIN[39][49]
V7_PDRIVE bit 4MAIN[38][44]
V7_PDRIVE bit 5!MAIN[39][33]
V7_PDRIVE bit 6MAIN[39][23]
V7_NDRIVE bit 0MAIN[39][51]
V7_NDRIVE bit 1MAIN[39][27]
V7_NDRIVE bit 2MAIN[39][55]
V7_NDRIVE bit 3!MAIN[39][47]
V7_NDRIVE bit 4MAIN[39][35]
V7_NDRIVE bit 5!MAIN[38][24]
V7_NDRIVE bit 6MAIN[38][20]
V7_OUTPUT_MISC bit 0MAIN[38][58]
V7_OUTPUT_MISC bit 1MAIN[38][60]
V7_OUTPUT_MISC bit 2MAIN[39][9]
V7_OUTPUT_MISC bit 3MAIN[39][57]
V7_OUTPUT_MISC bit 4MAIN[39][11]
V7_OUTPUT_MISC bit 5MAIN[39][19]
virtex7 IO_HP_N enum IOB_PULL
IOB[0].PULLMAIN[38][4]MAIN[38][10]MAIN[38][12]
NONE001
PULLUP011
PULLDOWN000
KEEPER101
virtex7 IO_HP_N enum IOB_IBUF_MODE
IOB[0].IBUF_MODEMAIN[39][1]MAIN[38][0]
NONE00
VREF01
CMOS11
virtex7 IO_HP_N enum IOB_DCI_MODE
IOB[0].DCI_MODEMAIN[39][53]MAIN[38][42]
NONE00
OUTPUT01
OUTPUT_HALF10
TERM_SPLIT11

Bel wires

virtex7 IO_HP_N bel wires
WirePins
IMUX_CLK[0]ILOGIC[0].CLKDIV
IMUX_CLK[1]IDELAY[0].C, ODELAY[0].C
IMUX_CTRL[0]OLOGIC[0].SR
IMUX_CTRL[1]ILOGIC[0].SR
IMUX_BYP_SITE[0]ODELAY[0].OFDLY[0]
IMUX_BYP_SITE[1]ODELAY[0].OFDLY[1]
IMUX_BYP_SITE[2]ODELAY[0].CINVCTRL
IMUX_BYP_SITE[5]ODELAY[0].OFDLY[2]
IMUX_BYP_SITE[6]IDELAY[0].CINVCTRL
IMUX_BYP_SITE[7]IDELAY[0].IFDLY[2]
IMUX_FAN_SITE[1]IOB[0].PU_INT_EN
IMUX_FAN_SITE[2]IOB[0].PD_INT_EN
IMUX_FAN_SITE[3]IOB[0].KEEPER_INT_EN
IMUX_FAN_SITE[4]IDELAY[0].IFDLY[0]
IMUX_FAN_SITE[5]IDELAY[0].IFDLY[1]
IMUX_IMUX[0]ILOGIC[0].BITSLIP
IMUX_IMUX[1]OLOGIC[0].TCE
IMUX_IMUX[2]ODELAY[0].CE
IMUX_IMUX[3]ODELAY[0].INC
IMUX_IMUX[4]ILOGIC[0].DYNCLKDIVSEL
IMUX_IMUX[5]ILOGIC[0].CE1
IMUX_IMUX[6]IOB[0].DCITERMDISABLE
IMUX_IMUX[7]OLOGIC[0].T2
IMUX_IMUX[9]IOB[0].IBUFDISABLE
IMUX_IMUX[10]ILOGIC[0].DYNCLKDIVPSEL
IMUX_IMUX[11]ODELAY[0].REGRST
IMUX_IMUX[12]IDELAY[0].REGRST
IMUX_IMUX[13]OLOGIC[0].T3
IMUX_IMUX[14]ILOGIC[0].CE2
IMUX_IMUX[15]OLOGIC[0].T1
IMUX_IMUX[16]ODELAY[0].CNTVALUEIN[1]
IMUX_IMUX[17]ODELAY[0].CNTVALUEIN[2]
IMUX_IMUX[18]ODELAY[0].CNTVALUEIN[4]
IMUX_IMUX[19]ODELAY[0].CNTVALUEIN[3]
IMUX_IMUX[21]OLOGIC[0].T4
IMUX_IMUX[23]ODELAY[0].CNTVALUEIN[0]
IMUX_IMUX[25]IDELAY[0].DATAIN
IMUX_IMUX[26]IDELAY[0].INC
IMUX_IMUX[27]ODELAY[0].LDPIPEEN
IMUX_IMUX[28]ODELAY[0].LD
IMUX_IMUX[29]OLOGIC[0].OCE
IMUX_IMUX[30]IDELAY[0].LD
IMUX_IMUX[32]IDELAY[0].CE
IMUX_IMUX[33]IDELAY[0].LDPIPEEN
IMUX_IMUX[34]OLOGIC[0].D1
IMUX_IMUX[35]IDELAY[0].CNTVALUEIN[2]
IMUX_IMUX[36]IDELAY[0].CNTVALUEIN[1]
IMUX_IMUX[37]ILOGIC[0].DYNCLKSEL
IMUX_IMUX[38]IDELAY[0].CNTVALUEIN[3]
IMUX_IMUX[39]IDELAY[0].CNTVALUEIN[4]
IMUX_IMUX[40]OLOGIC[0].D2
IMUX_IMUX[41]IDELAY[0].CNTVALUEIN[0]
IMUX_IMUX[42]OLOGIC[0].D4
IMUX_IMUX[43]OLOGIC[0].D5
IMUX_IMUX[44]OLOGIC[0].D3
IMUX_IMUX[45]OLOGIC[0].D6
IMUX_IMUX[46]OLOGIC[0].D7
IMUX_IMUX[47]OLOGIC[0].D8
OUT_BEL[0]ILOGIC[0].Q1
OUT_BEL[1]IDELAY[0].CNTVALUEOUT[1]
OUT_BEL[2]OLOGIC[0].TFB
OUT_BEL[3]ILOGIC[0].Q6
OUT_BEL[4]ODELAY[0].CNTVALUEOUT[1]
OUT_BEL[5]OLOGIC[0].IOCLKGLITCH
OUT_BEL[6]ODELAY[0].CNTVALUEOUT[2]
OUT_BEL[7]ILOGIC[0].Q7
OUT_BEL[8]ILOGIC[0].Q8
OUT_BEL[9]ILOGIC[0].Q3
OUT_BEL[10]ILOGIC[0].Q4
OUT_BEL[11]IDELAY[0].CNTVALUEOUT[4]
OUT_BEL[12]ODELAY[0].CNTVALUEOUT[0]
OUT_BEL[14]ILOGIC[0].Q5
OUT_BEL[15]IDELAY[0].CNTVALUEOUT[3]
OUT_BEL[17]ODELAY[0].CNTVALUEOUT[3]
OUT_BEL[18]ILOGIC[0].O
OUT_BEL[19]IDELAY[0].CNTVALUEOUT[2]
OUT_BEL[20]IDELAY[0].CNTVALUEOUT[0]
OUT_BEL[21]ODELAY[0].CNTVALUEOUT[4]
OUT_BEL[23]ILOGIC[0].Q2
IMUX_SPEC[1]ODELAY[0].DATAOUT
IMUX_IOI_ICLK[0]ILOGIC[0].CLK
IMUX_IOI_ICLK[1]ILOGIC[0].CLKB
IMUX_IOI_ICLKDIVPILOGIC[0].CLKDIVP
IMUX_IOI_OCLK[0]OLOGIC[0].CLK
IMUX_IOI_OCLK[1]OLOGIC[0].CLKB
IMUX_IOI_OCLKDIV[0]OLOGIC[0].CLKDIV
IMUX_IOI_OCLKDIV[1]OLOGIC[0].CLKDIVB
IMUX_IOI_OCLKDIVF[0]OLOGIC[0].CLKDIVF
IMUX_IOI_OCLKDIVF[1]OLOGIC[0].CLKDIVFB

Bitstream

virtex7 IO_HP_N rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: DCI_T - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 2 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 2 - - - - - - - IOB[0]: DCITERMDISABLE_EN - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 1 - - SPEC_INT: mux IMUX_IOI_ICLK[1] bit 1 - OLOGIC[0]: V5_MUX_T bit 0 - - - - - IOB[0]: V7_PDRIVE bit 0 - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 0 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 0 OLOGIC[0]: !invert T1 OLOGIC[0]: V5_MUX_T bit 4 - - - - - IOB[0]: V7_OUTPUT_MISC bit 1 - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_T bit 3 - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[0]: FINEDELAY - - - OLOGIC[0]: V5_MUX_T bit 1 - IDELAY[0]: DELAY_SRC bit 2 - - - IOB[0]: V7_OUTPUT_MISC bit 0 - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_T bit 2 - IDELAY[0]: DELAY_SRC bit 3 - ODELAY[0]: DELAY_SRC bit 2 - IOB[0]: V7_OUTPUT_MISC bit 3 - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: !invert T2 - - IDELAY[0]: DELAY_SRC bit 1 - ODELAY[0]: DELAY_SRC bit 1 - IOB[0]: ! DCIUPDATEMODE_ASREQUIRED - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[0]: IDATAIN_INV OLOGIC[0]: FFT_SR_SYNC ODELAY[0]: ! ODATAIN_INV IDELAY[0]: DELAY_SRC bit 0 - ODELAY[0]: DELAY_SRC bit 0 - IOB[0]: V7_NDRIVE bit 2 - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: SERDES IDELAY[0]: ENABLE - ODELAY[0]: ENABLE - - IOB[0]: V5_LVDS bit 7 - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 6 - - SPEC_INT: mux IMUX_IOI_ICLK[1] bit 6 - - - - - - - IOB[0]: DCI_MODE bit 1 - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 9 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 9 OLOGIC[0]: ! FFT_INIT bit 0 OLOGIC[0]: ! FFT_SRVAL bit 0 - - - - - IOB[0]: OUTPUT_DELAY - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 10 - OLOGIC[0]: !invert T3 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 10 - - - - - - - IOB[0]: V7_NDRIVE bit 0 - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 3 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 3 - - - - - - - IOB[0]: V6_PSLEW bit 0 - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 5 - - SPEC_INT: mux IMUX_IOI_ICLK[1] bit 5 - - - - - - - IOB[0]: ! V7_PDRIVE bit 3 - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 7 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 7 OLOGIC[0]: !invert T4 - - - - - - IOB[0]: ! V7_PDRIVE bit 2 - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 4 - - SPEC_INT: mux IMUX_IOI_ICLK[1] bit 4 - OLOGIC[0]: TBYTE_CTL - - - - - IOB[0]: ! V7_NDRIVE bit 3 - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 8 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 8 - OLOGIC[0]: ! FFT_SRVAL bit 1 - IDELAY[0]: invert DATAIN - - - IOB[0]: V6_NSLEW bit 0 - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 1 - - SPEC_INT: mux IMUX_IOI_OCLK[1] bit 1 - OLOGIC[0]: ! FFT_SRVAL bit 2 - - - - - IOB[0]: V6_NSLEW bit 1 - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 0 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 0 - OLOGIC[0]: SERDES_MODE bit 0 - - - - - IOB[0]: V7_PDRIVE bit 4 - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 2 - - SPEC_INT: mux IMUX_IOI_OCLK[1] bit 2 - OLOGIC[0]: TBYTE_SRC - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert CLKDIV - - - - - - IOB[0]: DCI_MODE bit 0 - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! RANK3_USED - - - - - - - - IOB[0]: V5_LVDS bit 8 - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: V5_LVDS bit 6 - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 5 - - SPEC_INT: mux IMUX_IOI_OCLK[1] bit 5 - - - IDELAY[0]: invert C - ODELAY[0]: invert C - IOB[0]: IBUFDISABLE_EN - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 9 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 9 - OLOGIC[0]: FFT_SR_ENABLE - IDELAY[0]: CINVCTRL_SEL - ODELAY[0]: CINVCTRL_SEL - IOB[0]: V6_NSLEW bit 2 - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! CLK1_INV - - OLOGIC[0]: TRISTATE_WIDTH bit 0 - - - - - IOB[0]: V5_LVDS bit 5 - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_O bit 2 - - - - - IOB[0]: DQS_BIAS_N - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 10 - OLOGIC[0]: ! CLK2_INV SPEC_INT: mux IMUX_IOI_OCLK[1] bit 10 - - - - - - - IOB[0]: V7_NDRIVE bit 4 - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 4 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 4 - OLOGIC[0]: V5_MUX_O bit 1 - - - - - IOB[0]: OUTPUT_ENABLE bit 1 - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 3 - OLOGIC[0]: invert CLKDIVF SPEC_INT: mux IMUX_IOI_OCLK[1] bit 3 - OLOGIC[0]: FFO_SR_SYNC - IDELAY[0]: ! IDELAY_VALUE_CUR bit 4 - ODELAY[0]: ! ODELAY_VALUE_CUR bit 4 - IOB[0]: ! V7_PDRIVE bit 5 - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 6 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 6 OLOGIC[0]: CLOCK_RATIO bit 1 OLOGIC[0]: ! FFO_SRVAL bit 0 - - - - - IOB[0]: OUTPUT_ENABLE bit 0 - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 8 - OLOGIC[0]: SELFHEAL SPEC_INT: mux IMUX_IOI_OCLK[1] bit 8 - - - IDELAY[0]: IDELAY_VALUE_INIT bit 4 - ODELAY[0]: ODELAY_VALUE_INIT bit 4 - IOB[0]: V7_PDRIVE bit 1 - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 7 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 7 OLOGIC[0]: invert D1 OLOGIC[0]: ! FFO_INIT bit 0 - - - - - IOB[0]: V6_PSLEW bit 1 - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLKDIVP bit 0 - OLOGIC[0]: CLOCK_RATIO bit 2 - - - - - - - - IOB[0]: DQS_BIAS_P - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLKDIVP bit 1 - OLOGIC[0]: CLOCK_RATIO bit 0 - - - - - - IOB[0]: V5_LVDS bit 4 - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: CLOCK_RATIO bit 3 - - - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 3 - ODELAY[0]: ! ODELAY_VALUE_CUR bit 3 - IOB[0]: V7_NDRIVE bit 1 - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 8 - - - - - - IOB[0]: V6_PSLEW bit 2 - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D2 - - - - IDELAY[0]: IDELAY_VALUE_INIT bit 3 - ODELAY[0]: ODELAY_VALUE_INIT bit 3 - IOB[0]: V5_LVDS bit 3 - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: ! V7_NDRIVE bit 5 - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: V7_PDRIVE bit 6 - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ODELAY[0]: FINEDELAY - IOB[0]: V6_NSLEW bit 3 - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D3 - - - - IDELAY[0]: PIPE_SEL - ODELAY[0]: PIPE_SEL - IOB[0]: V5_LVDS bit 2 - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFO_SRVAL bit 1 - - - - - IOB[0]: V7_NDRIVE bit 6 - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFO_SRVAL bit 2 - IDELAY[0]: ! IDELAY_VALUE_CUR bit 2 - ODELAY[0]: ! ODELAY_VALUE_CUR bit 2 - IOB[0]: V7_OUTPUT_MISC bit 5 - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[0]: HIGH_PERFORMANCE_MODE - ODELAY[0]: HIGH_PERFORMANCE_MODE - - IOB[0]: VR - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIV[0] bit 0 - OLOGIC[0]: invert D4 SPEC_INT: mux IMUX_IOI_OCLKDIV[1] bit 0 - OLOGIC[0]: V5_MUX_O bit 4 - IDELAY[0]: IDELAY_VALUE_INIT bit 2 - ODELAY[0]: ODELAY_VALUE_INIT bit 2 - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIV[0] bit 1 SPEC_INT: mux IMUX_IOI_OCLKDIV[1] bit 1 OLOGIC[0]: MISR_ENABLE OLOGIC[0]: V5_MUX_O bit 0 - - - - - IOB[0]: V6_PSLEW bit 3 - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_CLK_SELECT bit 0 - - OLOGIC[0]: FFO_SR_ENABLE - - - - - IOB[0]: V5_LVDS bit 1 - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D5 OLOGIC[0]: V5_MUX_O bit 3 - IDELAY[0]: DELAY_TYPE bit 1 - ODELAY[0]: DELAY_TYPE bit 1 - IOB[0]: V6_NSLEW bit 4 - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D6 - - - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 1 - ODELAY[0]: ! ODELAY_VALUE_CUR bit 1 - IOB[0]: V6_PSLEW bit 4 - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 7 - - - - - - IOB[0]: PULL bit 0 - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 6 - - - - IDELAY[0]: IDELAY_VALUE_INIT bit 1 - ODELAY[0]: ODELAY_VALUE_INIT bit 1 - IOB[0]: V7_OUTPUT_MISC bit 4 - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_ENABLE_FDBK - - - - - - IOB[0]: PULL bit 1 - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 5 - OLOGIC[0]: invert D7 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 5 - - - - - - - IOB[0]: V7_OUTPUT_MISC bit 2 - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 6 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 6 OLOGIC[0]: MISR_RESET - - IDELAY[0]: DELAY_TYPE bit 0 - ODELAY[0]: DELAY_TYPE bit 0 - IOB[0]: V5_LVDS bit 0 - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 4 - - - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 0 - ODELAY[0]: ! ODELAY_VALUE_CUR bit 0 - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 4 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 4 OLOGIC[0]: DATA_WIDTH bit 3 - - - - - - IOB[0]: PULL_DYNAMIC - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_CLK_SELECT bit 1 - - - - IDELAY[0]: IDELAY_VALUE_INIT bit 0 - ODELAY[0]: ODELAY_VALUE_INIT bit 0 - IOB[0]: INPUT_MISC bit 0 - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 0 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 0 OLOGIC[0]: DATA_WIDTH bit 5 - - - - - - IOB[0]: PULL bit 2 - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 1 - OLOGIC[0]: DATA_WIDTH bit 2 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 1 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 3 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 3 OLOGIC[0]: invert D8 - - - - - - IOB[0]: IBUF_VREF_HP - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 2 - OLOGIC[0]: DATA_WIDTH bit 1 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 2 - - - - - - - IOB[0]: IBUF_MODE bit 1 - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 0 - - - - - - IOB[0]: IBUF_MODE bit 0 - - -
### Bitstream
virtex7 IO_HP_N rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.OCLK1
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:D_EMU1 -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:D_EMU2
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SRTYPE[0] -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IFF_SR_USED - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF_LATCH ~ILOGIC[0]:IFF1_SRVAL -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF1_INIT
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF2_SRVAL -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF2_INIT
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:NUM_CE[0] - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF3_SRVAL -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF3_INIT
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF4_SRVAL -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF4_INIT
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DDR_CLK_EDGE[0] - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DDR_CLK_EDGE[1] - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:RANK23_DLY - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[1] ILOGIC[0]:I_DELAY_ENABLE -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SERDES - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:I_TSBYPASS_ENABLE -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SERDES_MODE[0] - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:BITSLIP_ENABLE - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_RATE[0] - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[3] ~ILOGIC[0]:INV.D -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[2] - - ILOGIC[0]:TSBYPASS_MUX[0]
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[1] - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[0] - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[3] ILOGIC[0]:IFF_TSBYPASS_ENABLE -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.CLKDIVP - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[4] - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLKDIVP_INV_EN - - ILOGIC[0]:IFF_DELAY_ENABLE
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[2] - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLKDIV_INV_EN - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.CLKDIV - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[0] - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[1] -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.OCLK2
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[0] -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[2]
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLK_INV_EN -
ILOGIC[0]:BITSLIP_ENABLE 0.F27.B20
ILOGIC[0]:DYN_CLKDIVP_INV_EN 0.F26.B11
ILOGIC[0]:DYN_CLKDIV_INV_EN 0.F26.B9
ILOGIC[0]:DYN_CLK_INV_EN 0.F28.B0
ILOGIC[0]:D_EMU1 0.F28.B62
ILOGIC[0]:D_EMU2 0.F29.B61
ILOGIC[0]:IFF_DELAY_ENABLE 0.F29.B11
ILOGIC[0]:IFF_SR_USED 0.F26.B57
ILOGIC[0]:IFF_TSBYPASS_ENABLE 0.F28.B14
ILOGIC[0]:INV.CLKDIV 0.F27.B8
ILOGIC[0]:INV.CLKDIVP 0.F26.B13
ILOGIC[0]:INV.OCLK1 0.F29.B63
ILOGIC[0]:INV.OCLK2 0.F29.B3
ILOGIC[0]:I_DELAY_ENABLE 0.F28.B26
ILOGIC[0]:I_TSBYPASS_ENABLE 0.F28.B24
ILOGIC[0]:RANK23_DLY 0.F26.B27
ILOGIC[0]:SERDES 0.F26.B25
non-inverted [0]
ILOGIC[0]:DATA_RATE 0.F26.B19
DDR 0
SDR 1
ILOGIC[0]:DATA_WIDTH 0.F27.B18 0.F26.B17 0.F27.B16 0.F26.B15
NONE 0 0 0 0
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
10 1 0 1 0
14 1 1 1 0
ILOGIC[0]:DDR_CLK_EDGE 0.F27.B28 0.F26.B29
SAME_EDGE_PIPELINED 0 0
OPPOSITE_EDGE 0 1
SAME_EDGE 1 0
ILOGIC[0]:IFF1_INIT 0.F29.B55
ILOGIC[0]:IFF1_SRVAL 0.F28.B56
ILOGIC[0]:IFF2_INIT 0.F29.B51
ILOGIC[0]:IFF2_SRVAL 0.F28.B52
ILOGIC[0]:IFF3_INIT 0.F29.B41
ILOGIC[0]:IFF3_SRVAL 0.F28.B42
ILOGIC[0]:IFF4_INIT 0.F29.B33
ILOGIC[0]:IFF4_SRVAL 0.F28.B34
ILOGIC[0]:IFF_LATCH 0.F27.B56
ILOGIC[0]:INV.D 0.F28.B18
inverted ~[0]
ILOGIC[0]:INTERFACE_TYPE 0.F27.B12 0.F27.B14 0.F27.B10 0.F27.B26 0.F27.B6
MEMORY 0 0 0 0 0
NETWORKING 0 0 0 0 1
MEMORY_DDR3 0 0 1 1 1
MEMORY_DDR3_V6 0 1 0 1 1
OVERSAMPLE 1 0 0 1 1
ILOGIC[0]:INV.CLK 0.F29.B1 0.F28.B4 0.F28.B2
inverted ~[2] ~[1] ~[0]
ILOGIC[0]:NUM_CE 0.F26.B47
1 0
2 1
ILOGIC[0]:SERDES_MODE 0.F26.B21
MASTER 0
SLAVE 1
ILOGIC[0]:SRTYPE 0.F28.B60
ASYNC 0
SYNC 1
ILOGIC[0]:TSBYPASS_MUX 0.F29.B17
T 0
GND 1

Tile IO_HR_PAIR

Cells: 2

Switchbox SPEC_INT

virtex7 IO_HR_PAIR switchbox SPEC_INT permanent buffers
DestinationSource
CELL[0].IMUX_SPEC[0]CELL[0].IMUX_IOI_OCLKDIV[0]
CELL[0].IMUX_SPEC[2]CELL[0].IMUX_IOI_OCLK[0]
CELL[1].IMUX_SPEC[0]CELL[1].IMUX_IOI_OCLKDIV[0]
CELL[1].IMUX_SPEC[2]CELL[1].IMUX_IOI_OCLK[0]
virtex7 IO_HR_PAIR switchbox SPEC_INT muxes IMUX_IOI_ICLK[0]
BitsDestination
MAIN[0][28][51]MAIN[0][29][52]MAIN[0][29][46]MAIN[0][29][48]MAIN[0][28][53]MAIN[0][28][49]MAIN[0][28][47]MAIN[0][29][50]MAIN[0][29][62]MAIN[0][28][61]MAIN[0][29][60]CELL[0].IMUX_IOI_ICLK[0]-
MAIN[1][28][13]MAIN[1][29][12]MAIN[1][28][11]MAIN[1][29][16]MAIN[1][29][14]MAIN[1][28][17]MAIN[1][28][15]MAIN[1][29][10]MAIN[1][28][1]MAIN[1][29][2]MAIN[1][28][3]-CELL[1].IMUX_IOI_ICLK[0]
Source
00000000000offoff
00000000010CELL[0].PHASER_ICLKCELL[1].PHASER_ICLK
00000000100CELL[0].PHASER_OCLKCELL[1].PHASER_OCLK
00000011001CELL[0].IMUX_IMUX[20]CELL[0].LCLK_IO[0]
00000101001CELL[0].IMUX_IMUX[22]CELL[0].LCLK_IO[1]
00001001001-CELL[0].LCLK_IO[2]
00001010001CELL[0].LCLK_IO[3]-
00001100001CELL[0].LCLK_IO[2]-
00010001001CELL[0].IOCLK[2]CELL[0].LCLK_IO[3]
00011000001CELL[0].LCLK_IO[0]-
00100001001CELL[0].IOCLK[3]-
00100010001-CELL[0].LCLK_IO[4]
00100100001-CELL[0].LCLK_IO[5]
00101000001CELL[0].LCLK_IO[1]CELL[0].RCLK_IO[0]
00110000001-CELL[0].RCLK_IO[1]
01000010001CELL[0].RCLK_IO[1]CELL[0].RCLK_IO[2]
01000100001CELL[0].RCLK_IO[0]CELL[0].RCLK_IO[3]
01001000001-CELL[0].IOCLK[0]
01010000001CELL[0].LCLK_IO[4]CELL[0].IOCLK[1]
01100000001CELL[0].LCLK_IO[5]-
10000010001CELL[0].IOCLK[1]CELL[0].IOCLK[2]
10000100001CELL[0].IOCLK[0]CELL[0].IOCLK[3]
10001000001-CELL[1].IMUX_IMUX[22]
10010000001CELL[0].RCLK_IO[2]CELL[1].IMUX_IMUX[20]
10100000001CELL[0].RCLK_IO[3]-
virtex7 IO_HR_PAIR switchbox SPEC_INT muxes IMUX_IOI_ICLK[1]
BitsDestination
MAIN[0][31][51]MAIN[0][30][52]MAIN[0][30][46]MAIN[0][30][48]MAIN[0][31][53]MAIN[0][31][49]MAIN[0][31][47]MAIN[0][30][50]MAIN[0][30][62]MAIN[0][31][61]MAIN[0][30][60]CELL[0].IMUX_IOI_ICLK[1]-
MAIN[1][31][13]MAIN[1][30][12]MAIN[1][31][11]MAIN[1][30][16]MAIN[1][30][14]MAIN[1][31][17]MAIN[1][31][15]MAIN[1][30][10]MAIN[1][31][1]MAIN[1][30][2]MAIN[1][31][3]-CELL[1].IMUX_IOI_ICLK[1]
Source
00000000000offoff
00000000010CELL[0].PHASER_ICLKCELL[1].PHASER_ICLK
00000000100CELL[0].PHASER_OCLKCELL[1].PHASER_OCLK
00000011001CELL[0].IMUX_IMUX[20]CELL[0].LCLK_IO[0]
00000101001CELL[0].IMUX_IMUX[22]CELL[0].LCLK_IO[1]
00001001001-CELL[0].LCLK_IO[2]
00001010001CELL[0].LCLK_IO[3]-
00001100001CELL[0].LCLK_IO[2]-
00010001001CELL[0].IOCLK[2]CELL[0].LCLK_IO[3]
00011000001CELL[0].LCLK_IO[0]-
00100001001CELL[0].IOCLK[3]-
00100010001-CELL[0].LCLK_IO[4]
00100100001-CELL[0].LCLK_IO[5]
00101000001CELL[0].LCLK_IO[1]CELL[0].RCLK_IO[0]
00110000001-CELL[0].RCLK_IO[1]
01000010001CELL[0].RCLK_IO[1]CELL[0].RCLK_IO[2]
01000100001CELL[0].RCLK_IO[0]CELL[0].RCLK_IO[3]
01001000001-CELL[0].IOCLK[0]
01010000001CELL[0].LCLK_IO[4]CELL[0].IOCLK[1]
01100000001CELL[0].LCLK_IO[5]-
10000010001CELL[0].IOCLK[1]CELL[0].IOCLK[2]
10000100001CELL[0].IOCLK[0]CELL[0].IOCLK[3]
10001000001-CELL[1].IMUX_IMUX[22]
10010000001CELL[0].RCLK_IO[2]CELL[1].IMUX_IMUX[20]
10100000001CELL[0].RCLK_IO[3]-
virtex7 IO_HR_PAIR switchbox SPEC_INT muxes IMUX_IOI_ICLKDIVP
BitsDestination
MAIN[0][29][28]MAIN[0][28][29]CELL[0].IMUX_IOI_ICLKDIVP-
MAIN[1][28][35]MAIN[1][29][34]-CELL[1].IMUX_IOI_ICLKDIVP
Source
00offoff
01CELL[0].IMUX_CLK[0]CELL[1].IMUX_CLK[0]
10CELL[0].PHASER_ICLKDIVCELL[1].PHASER_ICLKDIV
virtex7 IO_HR_PAIR switchbox SPEC_INT muxes IMUX_IOI_OCLK[0]
BitsDestination
MAIN[0][28][35]MAIN[0][29][38]MAIN[0][28][31]MAIN[0][29][30]MAIN[0][29][32]MAIN[0][28][39]MAIN[0][29][34]MAIN[0][28][33]MAIN[0][28][43]MAIN[0][28][45]MAIN[0][29][44]CELL[0].IMUX_IOI_OCLK[0]-
MAIN[1][28][29]MAIN[1][29][28]MAIN[1][28][25]MAIN[1][29][32]MAIN[1][29][30]MAIN[1][28][33]MAIN[1][28][31]MAIN[1][29][24]MAIN[1][29][20]MAIN[1][29][18]MAIN[1][28][19]-CELL[1].IMUX_IOI_OCLK[0]
Source
00000000000offoff
00000000010CELL[0].PHASER_OCLKCELL[1].PHASER_OCLK
00000000100CELL[0].PHASER_OCLK90CELL[1].PHASER_OCLK90
00000011001CELL[0].IMUX_IMUX[31]CELL[0].LCLK_IO[0]
00000101001CELL[0].LCLK_IO[2]CELL[0].LCLK_IO[1]
00001001001-CELL[0].LCLK_IO[2]
00001010001CELL[0].IOCLK[2]-
00001100001CELL[0].LCLK_IO[0]-
00010001001-CELL[0].LCLK_IO[3]
00010010001CELL[0].IOCLK[3]-
00010100001CELL[0].LCLK_IO[1]-
00100010001-CELL[0].LCLK_IO[4]
00100100001CELL[0].LCLK_IO[3]CELL[0].LCLK_IO[5]
00101000001-CELL[0].RCLK_IO[0]
00110000001-CELL[0].RCLK_IO[1]
01000001001CELL[0].RCLK_IO[0]-
01000010001-CELL[0].RCLK_IO[2]
01000100001-CELL[0].RCLK_IO[3]
01001000001CELL[0].LCLK_IO[4]CELL[0].IOCLK[0]
01010000001CELL[0].LCLK_IO[5]CELL[0].IOCLK[1]
01100000001CELL[0].RCLK_IO[1]-
10000001001CELL[0].IOCLK[0]-
10000010001-CELL[0].IOCLK[2]
10000100001-CELL[0].IOCLK[3]
10001000001CELL[0].RCLK_IO[2]CELL[1].IMUX_IMUX[31]
10010000001CELL[0].RCLK_IO[3]-
10100000001CELL[0].IOCLK[1]-
virtex7 IO_HR_PAIR switchbox SPEC_INT muxes IMUX_IOI_OCLK[1]
BitsDestination
MAIN[0][31][35]MAIN[0][30][38]MAIN[0][31][31]MAIN[0][30][30]MAIN[0][30][32]MAIN[0][31][39]MAIN[0][30][34]MAIN[0][31][33]MAIN[0][31][43]MAIN[0][31][45]MAIN[0][30][44]CELL[0].IMUX_IOI_OCLK[1]-
MAIN[1][31][29]MAIN[1][30][28]MAIN[1][31][25]MAIN[1][30][32]MAIN[1][30][30]MAIN[1][31][33]MAIN[1][31][31]MAIN[1][30][24]MAIN[1][30][20]MAIN[1][30][18]MAIN[1][31][19]-CELL[1].IMUX_IOI_OCLK[1]
Source
00000000000offoff
00000000010CELL[0].PHASER_OCLKCELL[1].PHASER_OCLK
00000000100CELL[0].PHASER_OCLK90CELL[1].PHASER_OCLK90
00000011001CELL[0].IMUX_IMUX[31]CELL[0].LCLK_IO[0]
00000101001CELL[0].LCLK_IO[2]CELL[0].LCLK_IO[1]
00001001001-CELL[0].LCLK_IO[2]
00001010001CELL[0].IOCLK[2]-
00001100001CELL[0].LCLK_IO[0]-
00010001001-CELL[0].LCLK_IO[3]
00010010001CELL[0].IOCLK[3]-
00010100001CELL[0].LCLK_IO[1]-
00100010001-CELL[0].LCLK_IO[4]
00100100001CELL[0].LCLK_IO[3]CELL[0].LCLK_IO[5]
00101000001-CELL[0].RCLK_IO[0]
00110000001-CELL[0].RCLK_IO[1]
01000001001CELL[0].RCLK_IO[0]-
01000010001-CELL[0].RCLK_IO[2]
01000100001-CELL[0].RCLK_IO[3]
01001000001CELL[0].LCLK_IO[4]CELL[0].IOCLK[0]
01010000001CELL[0].LCLK_IO[5]CELL[0].IOCLK[1]
01100000001CELL[0].RCLK_IO[1]-
10000001001CELL[0].IOCLK[0]-
10000010001-CELL[0].IOCLK[2]
10000100001-CELL[0].IOCLK[3]
10001000001CELL[0].RCLK_IO[2]CELL[1].IMUX_IMUX[31]
10010000001CELL[0].RCLK_IO[3]-
10100000001CELL[0].IOCLK[1]-
virtex7 IO_HR_PAIR switchbox SPEC_INT muxes IMUX_IOI_OCLKDIV[0]
BitsDestination
MAIN[0][29][16]MAIN[0][28][17]CELL[0].IMUX_IOI_OCLKDIV[0]-
MAIN[1][28][47]MAIN[1][29][46]-CELL[1].IMUX_IOI_OCLKDIV[0]
Source
00offoff
01CELL[0].PHASER_OCLKDIVCELL[1].PHASER_OCLKDIV
10CELL[0].IMUX_IOI_OCLKDIVF[0]CELL[1].IMUX_IOI_OCLKDIVF[0]
virtex7 IO_HR_PAIR switchbox SPEC_INT muxes IMUX_IOI_OCLKDIV[1]
BitsDestination
MAIN[0][30][16]MAIN[0][31][17]CELL[0].IMUX_IOI_OCLKDIV[1]-
MAIN[1][31][47]MAIN[1][30][46]-CELL[1].IMUX_IOI_OCLKDIV[1]
Source
00offoff
01CELL[0].PHASER_OCLKDIVCELL[1].PHASER_OCLKDIV
10CELL[0].IMUX_IOI_OCLKDIVF[1]CELL[1].IMUX_IOI_OCLKDIVF[1]
virtex7 IO_HR_PAIR switchbox SPEC_INT muxes IMUX_IOI_OCLKDIVF[0]
BitsDestination
MAIN[0][29][8]MAIN[0][28][9]MAIN[0][29][6]MAIN[0][29][2]MAIN[0][28][1]MAIN[0][28][3]MAIN[0][29][4]CELL[0].IMUX_IOI_OCLKDIVF[0]-
MAIN[1][28][57]MAIN[1][28][55]MAIN[1][29][54]MAIN[1][28][61]MAIN[1][28][59]MAIN[1][29][62]MAIN[1][29][60]-CELL[1].IMUX_IOI_OCLKDIVF[0]
Source
0000000offoff
0010001CELL[0].IMUX_IMUX[8]CELL[0].LCLK_IO[0]
0010010CELL[0].RCLK_IO[2]CELL[0].LCLK_IO[1]
0010100CELL[0].RCLK_IO[3]CELL[0].LCLK_IO[2]
0011000-CELL[0].LCLK_IO[3]
0100001CELL[0].LCLK_IO[2]CELL[0].LCLK_IO[4]
0100010CELL[0].LCLK_IO[0]CELL[0].LCLK_IO[5]
0100100CELL[0].LCLK_IO[1]CELL[0].RCLK_IO[0]
0101000CELL[0].LCLK_IO[3]CELL[0].RCLK_IO[1]
1000001CELL[0].RCLK_IO[0]CELL[0].RCLK_IO[2]
1000010CELL[0].LCLK_IO[4]CELL[0].RCLK_IO[3]
1000100CELL[0].LCLK_IO[5]CELL[1].IMUX_IMUX[8]
1001000CELL[0].RCLK_IO[1]-
virtex7 IO_HR_PAIR switchbox SPEC_INT muxes IMUX_IOI_OCLKDIVF[1]
BitsDestination
MAIN[0][30][8]MAIN[0][31][9]MAIN[0][30][6]MAIN[0][30][2]MAIN[0][31][1]MAIN[0][31][3]MAIN[0][30][4]CELL[0].IMUX_IOI_OCLKDIVF[1]-
MAIN[1][31][57]MAIN[1][31][55]MAIN[1][30][54]MAIN[1][31][61]MAIN[1][31][59]MAIN[1][30][62]MAIN[1][30][60]-CELL[1].IMUX_IOI_OCLKDIVF[1]
Source
0000000offoff
0010001CELL[0].IMUX_IMUX[8]CELL[0].LCLK_IO[0]
0010010CELL[0].RCLK_IO[2]CELL[0].LCLK_IO[1]
0010100CELL[0].RCLK_IO[3]CELL[0].LCLK_IO[2]
0011000-CELL[0].LCLK_IO[3]
0100001CELL[0].LCLK_IO[2]CELL[0].LCLK_IO[4]
0100010CELL[0].LCLK_IO[0]CELL[0].LCLK_IO[5]
0100100CELL[0].LCLK_IO[1]CELL[0].RCLK_IO[0]
0101000CELL[0].LCLK_IO[3]CELL[0].RCLK_IO[1]
1000001CELL[0].RCLK_IO[0]CELL[0].RCLK_IO[2]
1000010CELL[0].LCLK_IO[4]CELL[0].RCLK_IO[3]
1000100CELL[0].LCLK_IO[5]CELL[1].IMUX_IMUX[8]
1001000CELL[0].RCLK_IO[1]-

Bels ILOGIC

virtex7 IO_HR_PAIR bel ILOGIC pins
PinDirectionILOGIC[0]ILOGIC[1]
CLKinCELL[0].IMUX_IOI_ICLK[0]CELL[1].IMUX_IOI_ICLK[0]
CLKBinCELL[0].IMUX_IOI_ICLK[1]CELL[1].IMUX_IOI_ICLK[1]
CLKDIVinCELL[0].IMUX_CLK[0]CELL[1].IMUX_CLK[0]
CLKDIVPinCELL[0].IMUX_IOI_ICLKDIVPCELL[1].IMUX_IOI_ICLKDIVP
SRinCELL[0].IMUX_CTRL[1]CELL[1].IMUX_CTRL[1]
CE1inCELL[0].IMUX_IMUX[5]CELL[1].IMUX_IMUX[5]
CE2inCELL[0].IMUX_IMUX[14]CELL[1].IMUX_IMUX[14]
BITSLIPinCELL[0].IMUX_IMUX[0]CELL[1].IMUX_IMUX[0]
DYNCLKSELinCELL[0].IMUX_IMUX[37]CELL[1].IMUX_IMUX[37]
DYNCLKDIVSELinCELL[0].IMUX_IMUX[4]CELL[1].IMUX_IMUX[4]
DYNCLKDIVPSELinCELL[0].IMUX_IMUX[10]CELL[1].IMUX_IMUX[10]
OoutCELL[0].OUT_BEL[18]CELL[1].OUT_BEL[18]
Q1outCELL[0].OUT_BEL[0]CELL[1].OUT_BEL[0]
Q2outCELL[0].OUT_BEL[23]CELL[1].OUT_BEL[23]
Q3outCELL[0].OUT_BEL[9]CELL[1].OUT_BEL[9]
Q4outCELL[0].OUT_BEL[10]CELL[1].OUT_BEL[10]
Q5outCELL[0].OUT_BEL[14]CELL[1].OUT_BEL[14]
Q6outCELL[0].OUT_BEL[3]CELL[1].OUT_BEL[3]
Q7outCELL[0].OUT_BEL[7]CELL[1].OUT_BEL[7]
Q8outCELL[0].OUT_BEL[8]CELL[1].OUT_BEL[8]
CLKPADout-CELL[1].OUT_CLKPAD
virtex7 IO_HR_PAIR bel ILOGIC attribute bits
AttributeILOGIC[0]ILOGIC[1]

Bels OLOGIC

virtex7 IO_HR_PAIR bel OLOGIC pins
PinDirectionOLOGIC[0]OLOGIC[1]
CLKinCELL[0].IMUX_IOI_OCLK[0]CELL[1].IMUX_IOI_OCLK[0]
CLKBinCELL[0].IMUX_IOI_OCLK[1]CELL[1].IMUX_IOI_OCLK[1]
CLKDIVinCELL[0].IMUX_IOI_OCLKDIV[0] invert by MAIN[0][31][42]CELL[1].IMUX_IOI_OCLKDIV[0] invert by MAIN[1][30][21]
CLKDIVBinCELL[0].IMUX_IOI_OCLKDIV[1]CELL[1].IMUX_IOI_OCLKDIV[1]
CLKDIVFinCELL[0].IMUX_IOI_OCLKDIVF[0] invert by MAIN[0][30][33]CELL[1].IMUX_IOI_OCLKDIVF[0] invert by MAIN[1][31][30]
CLKDIVFBinCELL[0].IMUX_IOI_OCLKDIVF[1]CELL[1].IMUX_IOI_OCLKDIVF[1]
SRinCELL[0].IMUX_CTRL[0]CELL[1].IMUX_CTRL[0]
OCEinCELL[0].IMUX_IMUX[29]CELL[1].IMUX_IMUX[29]
TCEinCELL[0].IMUX_IMUX[1]CELL[1].IMUX_IMUX[1]
D1inCELL[0].IMUX_IMUX[34] invert by MAIN[0][31][30]CELL[1].IMUX_IMUX[34] invert by MAIN[1][30][33]
D2inCELL[0].IMUX_IMUX[40] invert by MAIN[0][30][25]CELL[1].IMUX_IMUX[40] invert by MAIN[1][31][38]
D3inCELL[0].IMUX_IMUX[44] invert by MAIN[0][30][21]CELL[1].IMUX_IMUX[44] invert by MAIN[1][31][42]
D4inCELL[0].IMUX_IMUX[42] invert by MAIN[0][30][17]CELL[1].IMUX_IMUX[42] invert by MAIN[1][31][46]
D5inCELL[0].IMUX_IMUX[43] invert by MAIN[0][31][14]CELL[1].IMUX_IMUX[43] invert by MAIN[1][30][49]
D6inCELL[0].IMUX_IMUX[45] invert by MAIN[0][30][13]CELL[1].IMUX_IMUX[45] invert by MAIN[1][31][50]
D7inCELL[0].IMUX_IMUX[46] invert by MAIN[0][30][9]CELL[1].IMUX_IMUX[46] invert by MAIN[1][31][54]
D8inCELL[0].IMUX_IMUX[47] invert by MAIN[0][31][2]CELL[1].IMUX_IMUX[47] invert by MAIN[1][30][61]
T1inCELL[0].IMUX_IMUX[15] invert by !MAIN[0][31][60]CELL[1].IMUX_IMUX[15] invert by !MAIN[1][30][3]
T2inCELL[0].IMUX_IMUX[7] invert by !MAIN[0][31][56]CELL[1].IMUX_IMUX[7] invert by !MAIN[1][30][7]
T3inCELL[0].IMUX_IMUX[13] invert by !MAIN[0][30][51]CELL[1].IMUX_IMUX[13] invert by !MAIN[1][31][12]
T4inCELL[0].IMUX_IMUX[21] invert by !MAIN[0][31][48]CELL[1].IMUX_IMUX[21] invert by !MAIN[1][30][15]
TFBoutCELL[0].OUT_BEL[2]CELL[1].OUT_BEL[2]
IOCLKGLITCHoutCELL[0].OUT_BEL[5]CELL[1].OUT_BEL[5]
virtex7 IO_HR_PAIR bel OLOGIC attribute bits
AttributeOLOGIC[0]OLOGIC[1]
CLK1_INV!MAIN[0][30][37]!MAIN[1][31][26]
CLK2_INV!MAIN[0][30][35]!MAIN[1][31][28]
FFO_INIT bit 0!MAIN[0][32][30]!MAIN[1][33][33]
FFO_SRVAL bit 0!MAIN[0][32][32]!MAIN[1][33][31]
FFO_SRVAL bit 1!MAIN[0][32][20]!MAIN[1][33][43]
FFO_SRVAL bit 2!MAIN[0][33][19]!MAIN[1][32][44]
FFO_SR_SYNCMAIN[0][33][33]MAIN[1][32][30]
FFO_SR_ENABLEMAIN[0][33][15]MAIN[1][32][48]
V5_MUX_O[enum: OLOGIC_V5_MUX_O][enum: OLOGIC_V5_MUX_O]
FFT_INIT bit 0!MAIN[0][31][52]!MAIN[1][30][11]
FFT_SRVAL bit 0!MAIN[0][32][52]!MAIN[1][33][11]
FFT_SRVAL bit 1!MAIN[0][32][46]!MAIN[1][33][17]
FFT_SRVAL bit 2!MAIN[0][33][45]!MAIN[1][32][18]
FFT_SR_SYNCMAIN[0][33][55]MAIN[1][32][8]
FFT_SR_ENABLEMAIN[0][32][38]MAIN[1][33][25]
V5_MUX_T[enum: OLOGIC_V5_MUX_T][enum: OLOGIC_V5_MUX_T]
SERDESMAIN[0][32][54]MAIN[1][33][9]
SERDES_MODE[enum: IO_SERDES_MODE][enum: IO_SERDES_MODE]
DATA_WIDTH[enum: IO_DATA_WIDTH][enum: IO_DATA_WIDTH]
TRISTATE_WIDTH[enum: OLOGIC_TRISTATE_WIDTH][enum: OLOGIC_TRISTATE_WIDTH]
MISR_ENABLEMAIN[0][31][16]MAIN[1][30][47]
MISR_ENABLE_FDBKMAIN[0][31][10]MAIN[1][30][53]
MISR_RESETMAIN[0][31][8]MAIN[1][30][55]
MISR_CLK_SELECT[enum: OLOGIC_MISR_CLK_SELECT][enum: OLOGIC_MISR_CLK_SELECT]
CLOCK_RATIO[enum: OLOGIC_CLOCK_RATIO][enum: OLOGIC_CLOCK_RATIO]
SELFHEALMAIN[0][30][31]MAIN[1][31][32]
RANK3_USED!MAIN[0][30][41]!MAIN[1][31][22]
TBYTE_CTLMAIN[0][33][47]MAIN[1][32][16]
TBYTE_SRCMAIN[0][33][43]MAIN[1][32][20]
virtex7 IO_HR_PAIR enum OLOGIC_V5_MUX_O
OLOGIC[0].V5_MUX_OMAIN[0][33][17]MAIN[0][32][14]MAIN[0][32][36]MAIN[0][32][34]MAIN[0][32][16]
OLOGIC[1].V5_MUX_OMAIN[1][32][46]MAIN[1][33][49]MAIN[1][33][27]MAIN[1][33][29]MAIN[1][33][47]
NONE00000
D100001
SERDES_SDR00010
LATCH10010
FF01010
DDR00100
virtex7 IO_HR_PAIR enum OLOGIC_V5_MUX_T
OLOGIC[0].V5_MUX_TMAIN[0][32][60]MAIN[0][33][59]MAIN[0][33][57]MAIN[0][32][58]MAIN[0][33][61]
OLOGIC[1].V5_MUX_TMAIN[1][33][3]MAIN[1][32][4]MAIN[1][32][6]MAIN[1][33][5]MAIN[1][32][2]
NONE00000
T100001
SERDES_SDR00010
LATCH10010
FF01010
DDR00100
virtex7 IO_HR_PAIR enum IO_SERDES_MODE
OLOGIC[0].SERDES_MODEMAIN[0][32][44]
OLOGIC[1].SERDES_MODEMAIN[1][33][19]
MASTER0
SLAVE1
virtex7 IO_HR_PAIR enum IO_DATA_WIDTH
OLOGIC[0].DATA_WIDTHMAIN[0][31][26]MAIN[0][31][12]MAIN[0][30][11]MAIN[0][31][4]MAIN[0][30][7]MAIN[0][31][6]MAIN[0][30][3]MAIN[0][30][1]MAIN[0][31][0]
OLOGIC[1].DATA_WIDTHMAIN[1][30][37]MAIN[1][30][51]MAIN[1][31][52]MAIN[1][30][59]MAIN[1][31][56]MAIN[1][30][57]MAIN[1][31][60]MAIN[1][31][62]MAIN[1][30][63]
NONE000000000
_2000000001
_3000000010
_4000000100
_5000001000
_6000010000
_7000100000
_8001000000
_10010000000
_14100000000
virtex7 IO_HR_PAIR enum OLOGIC_TRISTATE_WIDTH
OLOGIC[0].TRISTATE_WIDTHMAIN[0][33][37]
OLOGIC[1].TRISTATE_WIDTHMAIN[1][32][26]
_10
_41
virtex7 IO_HR_PAIR enum OLOGIC_MISR_CLK_SELECT
OLOGIC[0].MISR_CLK_SELECTMAIN[0][30][5]MAIN[0][30][15]
OLOGIC[1].MISR_CLK_SELECTMAIN[1][31][58]MAIN[1][31][48]
NONE00
CLK101
CLK210
virtex7 IO_HR_PAIR enum OLOGIC_CLOCK_RATIO
OLOGIC[0].CLOCK_RATIOMAIN[0][30][27]MAIN[0][30][29]MAIN[0][31][32]MAIN[0][31][28]
OLOGIC[1].CLOCK_RATIOMAIN[1][31][36]MAIN[1][31][34]MAIN[1][30][31]MAIN[1][30][35]
NONE0000
_20001
_30010
_40011
_50101
_61101
_7_81100

Bels IDELAY

virtex7 IO_HR_PAIR bel IDELAY pins
PinDirectionIDELAY[0]IDELAY[1]
CinCELL[0].IMUX_CLK[1] invert by MAIN[0][35][39]CELL[1].IMUX_CLK[1] invert by MAIN[1][34][24]
CINVCTRLinCELL[0].IMUX_BYP_SITE[6]CELL[1].IMUX_BYP_SITE[6]
CEinCELL[0].IMUX_IMUX[32]CELL[1].IMUX_IMUX[32]
DATAINinCELL[0].IMUX_IMUX[25] invert by MAIN[0][34][46]CELL[1].IMUX_IMUX[25] invert by MAIN[1][35][17]
INCinCELL[0].IMUX_IMUX[26]CELL[1].IMUX_IMUX[26]
REGRSTinCELL[0].IMUX_IMUX[12]CELL[1].IMUX_IMUX[12]
LDinCELL[0].IMUX_IMUX[30]CELL[1].IMUX_IMUX[30]
LDPIPEENinCELL[0].IMUX_IMUX[33]CELL[1].IMUX_IMUX[33]
IFDLY[0]inCELL[0].IMUX_FAN_SITE[4]CELL[1].IMUX_FAN_SITE[4]
IFDLY[1]inCELL[0].IMUX_FAN_SITE[5]CELL[1].IMUX_FAN_SITE[5]
IFDLY[2]inCELL[0].IMUX_BYP_SITE[7]CELL[1].IMUX_BYP_SITE[7]
CNTVALUEIN[0]inCELL[0].IMUX_IMUX[41]CELL[1].IMUX_IMUX[41]
CNTVALUEIN[1]inCELL[0].IMUX_IMUX[36]CELL[1].IMUX_IMUX[36]
CNTVALUEIN[2]inCELL[0].IMUX_IMUX[35]CELL[1].IMUX_IMUX[35]
CNTVALUEIN[3]inCELL[0].IMUX_IMUX[38]CELL[1].IMUX_IMUX[38]
CNTVALUEIN[4]inCELL[0].IMUX_IMUX[39]CELL[1].IMUX_IMUX[39]
CNTVALUEOUT[0]outCELL[0].OUT_BEL[20]CELL[1].OUT_BEL[20]
CNTVALUEOUT[1]outCELL[0].OUT_BEL[1]CELL[1].OUT_BEL[1]
CNTVALUEOUT[2]outCELL[0].OUT_BEL[19]CELL[1].OUT_BEL[19]
CNTVALUEOUT[3]outCELL[0].OUT_BEL[15]CELL[1].OUT_BEL[15]
CNTVALUEOUT[4]outCELL[0].OUT_BEL[11]CELL[1].OUT_BEL[11]
virtex7 IO_HR_PAIR bel IDELAY attribute bits
AttributeIDELAY[0]IDELAY[1]
ENABLEMAIN[0][33][54]MAIN[1][32][9]
IDATAIN_INVMAIN[0][32][55]MAIN[1][33][8]
CINVCTRL_SELMAIN[0][34][38]MAIN[1][35][25]
DELAY_SRC[enum: IDELAY_DELAY_SRC][enum: IDELAY_DELAY_SRC]
DELAY_TYPE[enum: IODELAY_V7_DELAY_TYPE][enum: IODELAY_V7_DELAY_TYPE]
HIGH_PERFORMANCE_MODEMAIN[0][33][18]MAIN[1][32][45]
PIPE_SELMAIN[0][35][21]MAIN[1][34][42]
IDELAY_VALUE_CUR bit 0!MAIN[0][35][7]!MAIN[1][34][56]
IDELAY_VALUE_CUR bit 1!MAIN[0][35][13]!MAIN[1][34][50]
IDELAY_VALUE_CUR bit 2!MAIN[0][35][19]!MAIN[1][34][44]
IDELAY_VALUE_CUR bit 3!MAIN[0][35][27]!MAIN[1][34][36]
IDELAY_VALUE_CUR bit 4!MAIN[0][35][33]!MAIN[1][34][30]
IDELAY_VALUE_INIT bit 0MAIN[0][35][5]MAIN[1][34][58]
IDELAY_VALUE_INIT bit 1MAIN[0][35][11]MAIN[1][34][52]
IDELAY_VALUE_INIT bit 2MAIN[0][35][17]MAIN[1][34][46]
IDELAY_VALUE_INIT bit 3MAIN[0][35][25]MAIN[1][34][38]
IDELAY_VALUE_INIT bit 4MAIN[0][35][31]MAIN[1][34][32]
virtex7 IO_HR_PAIR enum IDELAY_DELAY_SRC
IDELAY[0].DELAY_SRCMAIN[0][35][57]MAIN[0][34][58]MAIN[0][34][56]MAIN[0][35][55]
IDELAY[1].DELAY_SRCMAIN[1][34][6]MAIN[1][35][5]MAIN[1][35][7]MAIN[1][34][8]
NONE0000
IDATAIN0001
OFB0010
DATAIN0100
DELAYCHAIN_OSC1000
virtex7 IO_HR_PAIR enum IODELAY_V7_DELAY_TYPE
IDELAY[0].DELAY_TYPEMAIN[0][34][14]MAIN[0][34][8]
IDELAY[1].DELAY_TYPEMAIN[1][35][49]MAIN[1][35][55]
FIXED00
VARIABLE01
VAR_LOAD11

Bels IOB

virtex7 IO_HR_PAIR bel IOB pins
PinDirectionIOB[0]IOB[1]
PD_INT_ENinCELL[0].IMUX_FAN_SITE[2]CELL[1].IMUX_FAN_SITE[2]
PU_INT_ENinCELL[0].IMUX_FAN_SITE[1]CELL[1].IMUX_FAN_SITE[1]
KEEPER_INT_ENinCELL[0].IMUX_FAN_SITE[3]CELL[1].IMUX_FAN_SITE[3]
DIFF_TERM_INT_ENinCELL[0].IMUX_FAN_SITE[0]-
IBUFDISABLEinCELL[0].IMUX_IMUX[9]CELL[1].IMUX_IMUX[9]
INTERMDISABLEinCELL[0].IMUX_IMUX[6]CELL[1].IMUX_IMUX[6]
virtex7 IO_HR_PAIR bel IOB attribute bits
AttributeIOB[0]IOB[1]
PULL[enum: IOB_PULL][enum: IOB_PULL]
VREF_SYSMONMAIN[0][39][39]MAIN[1][38][24]
PULL_DYNAMICMAIN[0][38][36]MAIN[1][39][27]
DQS_BIASMAIN[0][39][37]MAIN[1][38][26]
IBUFDISABLE_ENMAIN[0][39][45]MAIN[1][38][18]
INTERMDISABLE_ENMAIN[0][38][38]MAIN[1][39][25]
LOW_VOLTAGEMAIN[0][38][32]MAIN[1][39][31]
IBUF_MODE[enum: IOB_IBUF_MODE][enum: IOB_IBUF_MODE]
IBUF_VREF_HPMAIN[0][39][43]MAIN[1][38][20]
IBUF_DIFF_HPMAIN[0][38][44]MAIN[1][39][19]
INPUT_MISC bit 0MAIN[0][39][47]MAIN[1][38][16]
IN_TERM[enum: IOB_IN_TERM][enum: IOB_IN_TERM]
IBUF_PCIMAIN[0][38][46]MAIN[1][39][17]
OUTPUT_ENABLE bit 0MAIN[0][38][62]MAIN[1][39][1]
OUTPUT_ENABLE bit 1MAIN[0][39][63]MAIN[1][38][0]
OUTPUT_PSEUDO_DIFFMAIN[0][39][61]-
OUTPUT_PSEUDO_DIFF_TMAIN[0][39][59]-
LVDS_GROUP bit 0MAIN[0][38][24]MAIN[1][39][39]
HR_PDRIVE bit 0MAIN[0][38][0]MAIN[1][39][63]
HR_PDRIVE bit 1MAIN[0][39][1]MAIN[1][38][62]
HR_PDRIVE bit 2!MAIN[0][38][2]!MAIN[1][39][61]
HR_NDRIVE bit 0!MAIN[0][38][8]!MAIN[1][39][55]
HR_NDRIVE bit 1!MAIN[0][39][9]!MAIN[1][38][54]
HR_NDRIVE bit 2MAIN[0][38][10]MAIN[1][39][53]
HR_NDRIVE bit 3MAIN[0][39][11]MAIN[1][38][52]
HR_PSLEW bit 0MAIN[0][38][20]MAIN[1][39][43]
HR_PSLEW bit 1!MAIN[0][39][21]!MAIN[1][38][42]
HR_PSLEW bit 2MAIN[0][38][22]MAIN[1][39][41]
HR_NSLEW bit 0MAIN[0][38][16]MAIN[1][39][47]
HR_NSLEW bit 1!MAIN[0][39][17]!MAIN[1][38][46]
HR_NSLEW bit 2MAIN[0][38][18]MAIN[1][39][45]
HR_OUTPUT_MISC bit 0!MAIN[0][38][14]!MAIN[1][39][49]
HR_OUTPUT_MISC bit 1MAIN[0][39][15]MAIN[1][38][48]
HR_LVDS bit 0MAIN[0][39][53]MAIN[1][38][10]
HR_LVDS bit 1MAIN[0][38][52]MAIN[1][39][11]
HR_LVDS bit 2MAIN[0][39][51]MAIN[1][38][12]
HR_LVDS bit 3MAIN[0][38][50]MAIN[1][39][13]
HR_LVDS bit 4MAIN[0][39][49]MAIN[1][38][14]
HR_LVDS bit 5MAIN[0][38][48]MAIN[1][39][15]
HR_LVDS bit 6MAIN[0][39][31]MAIN[1][38][32]
HR_LVDS bit 7MAIN[0][38][30]MAIN[1][39][33]
HR_LVDS bit 8MAIN[0][39][29]MAIN[1][38][34]
HR_LVDS bit 9MAIN[0][38][28]MAIN[1][39][35]
HR_LVDS bit 10MAIN[0][39][27]MAIN[1][38][36]
HR_LVDS bit 11MAIN[0][38][26]MAIN[1][39][37]
HR_LVDS bit 12MAIN[0][39][25]MAIN[1][38][38]
virtex7 IO_HR_PAIR enum IOB_PULL
IOB[0].PULLMAIN[0][39][35]MAIN[0][38][34]MAIN[0][39][33]
IOB[1].PULLMAIN[1][38][28]MAIN[1][39][29]MAIN[1][38][30]
NONE001
PULLUP011
PULLDOWN000
KEEPER101
virtex7 IO_HR_PAIR enum IOB_IBUF_MODE
IOB[0].IBUF_MODEMAIN[0][38][42]MAIN[0][39][41]MAIN[0][38][40]
IOB[1].IBUF_MODEMAIN[1][39][21]MAIN[1][38][22]MAIN[1][39][23]
NONE000
VREF001
DIFF011
CMOS110
CMOS_HV111
TMDS010
virtex7 IO_HR_PAIR enum IOB_IN_TERM
IOB[0].IN_TERMMAIN[0][38][6]MAIN[0][39][5]MAIN[0][39][7]MAIN[0][38][4]
IOB[1].IN_TERMMAIN[1][39][57]MAIN[1][38][58]MAIN[1][39][59]MAIN[1][38][56]
NONE0000
UNTUNED_SPLIT_401111
UNTUNED_SPLIT_500111
UNTUNED_SPLIT_600011

Bel wires

virtex7 IO_HR_PAIR bel wires
WirePins
CELL[0].IMUX_CLK[0]ILOGIC[0].CLKDIV
CELL[0].IMUX_CLK[1]IDELAY[0].C
CELL[0].IMUX_CTRL[0]OLOGIC[0].SR
CELL[0].IMUX_CTRL[1]ILOGIC[0].SR
CELL[0].IMUX_BYP_SITE[6]IDELAY[0].CINVCTRL
CELL[0].IMUX_BYP_SITE[7]IDELAY[0].IFDLY[2]
CELL[0].IMUX_FAN_SITE[0]IOB[0].DIFF_TERM_INT_EN
CELL[0].IMUX_FAN_SITE[1]IOB[0].PU_INT_EN
CELL[0].IMUX_FAN_SITE[2]IOB[0].PD_INT_EN
CELL[0].IMUX_FAN_SITE[3]IOB[0].KEEPER_INT_EN
CELL[0].IMUX_FAN_SITE[4]IDELAY[0].IFDLY[0]
CELL[0].IMUX_FAN_SITE[5]IDELAY[0].IFDLY[1]
CELL[0].IMUX_IMUX[0]ILOGIC[0].BITSLIP
CELL[0].IMUX_IMUX[1]OLOGIC[0].TCE
CELL[0].IMUX_IMUX[4]ILOGIC[0].DYNCLKDIVSEL
CELL[0].IMUX_IMUX[5]ILOGIC[0].CE1
CELL[0].IMUX_IMUX[6]IOB[0].INTERMDISABLE
CELL[0].IMUX_IMUX[7]OLOGIC[0].T2
CELL[0].IMUX_IMUX[9]IOB[0].IBUFDISABLE
CELL[0].IMUX_IMUX[10]ILOGIC[0].DYNCLKDIVPSEL
CELL[0].IMUX_IMUX[12]IDELAY[0].REGRST
CELL[0].IMUX_IMUX[13]OLOGIC[0].T3
CELL[0].IMUX_IMUX[14]ILOGIC[0].CE2
CELL[0].IMUX_IMUX[15]OLOGIC[0].T1
CELL[0].IMUX_IMUX[21]OLOGIC[0].T4
CELL[0].IMUX_IMUX[25]IDELAY[0].DATAIN
CELL[0].IMUX_IMUX[26]IDELAY[0].INC
CELL[0].IMUX_IMUX[29]OLOGIC[0].OCE
CELL[0].IMUX_IMUX[30]IDELAY[0].LD
CELL[0].IMUX_IMUX[32]IDELAY[0].CE
CELL[0].IMUX_IMUX[33]IDELAY[0].LDPIPEEN
CELL[0].IMUX_IMUX[34]OLOGIC[0].D1
CELL[0].IMUX_IMUX[35]IDELAY[0].CNTVALUEIN[2]
CELL[0].IMUX_IMUX[36]IDELAY[0].CNTVALUEIN[1]
CELL[0].IMUX_IMUX[37]ILOGIC[0].DYNCLKSEL
CELL[0].IMUX_IMUX[38]IDELAY[0].CNTVALUEIN[3]
CELL[0].IMUX_IMUX[39]IDELAY[0].CNTVALUEIN[4]
CELL[0].IMUX_IMUX[40]OLOGIC[0].D2
CELL[0].IMUX_IMUX[41]IDELAY[0].CNTVALUEIN[0]
CELL[0].IMUX_IMUX[42]OLOGIC[0].D4
CELL[0].IMUX_IMUX[43]OLOGIC[0].D5
CELL[0].IMUX_IMUX[44]OLOGIC[0].D3
CELL[0].IMUX_IMUX[45]OLOGIC[0].D6
CELL[0].IMUX_IMUX[46]OLOGIC[0].D7
CELL[0].IMUX_IMUX[47]OLOGIC[0].D8
CELL[0].OUT_BEL[0]ILOGIC[0].Q1
CELL[0].OUT_BEL[1]IDELAY[0].CNTVALUEOUT[1]
CELL[0].OUT_BEL[2]OLOGIC[0].TFB
CELL[0].OUT_BEL[3]ILOGIC[0].Q6
CELL[0].OUT_BEL[5]OLOGIC[0].IOCLKGLITCH
CELL[0].OUT_BEL[7]ILOGIC[0].Q7
CELL[0].OUT_BEL[8]ILOGIC[0].Q8
CELL[0].OUT_BEL[9]ILOGIC[0].Q3
CELL[0].OUT_BEL[10]ILOGIC[0].Q4
CELL[0].OUT_BEL[11]IDELAY[0].CNTVALUEOUT[4]
CELL[0].OUT_BEL[14]ILOGIC[0].Q5
CELL[0].OUT_BEL[15]IDELAY[0].CNTVALUEOUT[3]
CELL[0].OUT_BEL[18]ILOGIC[0].O
CELL[0].OUT_BEL[19]IDELAY[0].CNTVALUEOUT[2]
CELL[0].OUT_BEL[20]IDELAY[0].CNTVALUEOUT[0]
CELL[0].OUT_BEL[23]ILOGIC[0].Q2
CELL[0].IMUX_IOI_ICLK[0]ILOGIC[0].CLK
CELL[0].IMUX_IOI_ICLK[1]ILOGIC[0].CLKB
CELL[0].IMUX_IOI_ICLKDIVPILOGIC[0].CLKDIVP
CELL[0].IMUX_IOI_OCLK[0]OLOGIC[0].CLK
CELL[0].IMUX_IOI_OCLK[1]OLOGIC[0].CLKB
CELL[0].IMUX_IOI_OCLKDIV[0]OLOGIC[0].CLKDIV
CELL[0].IMUX_IOI_OCLKDIV[1]OLOGIC[0].CLKDIVB
CELL[0].IMUX_IOI_OCLKDIVF[0]OLOGIC[0].CLKDIVF
CELL[0].IMUX_IOI_OCLKDIVF[1]OLOGIC[0].CLKDIVFB
CELL[1].IMUX_CLK[0]ILOGIC[1].CLKDIV
CELL[1].IMUX_CLK[1]IDELAY[1].C
CELL[1].IMUX_CTRL[0]OLOGIC[1].SR
CELL[1].IMUX_CTRL[1]ILOGIC[1].SR
CELL[1].IMUX_BYP_SITE[6]IDELAY[1].CINVCTRL
CELL[1].IMUX_BYP_SITE[7]IDELAY[1].IFDLY[2]
CELL[1].IMUX_FAN_SITE[1]IOB[1].PU_INT_EN
CELL[1].IMUX_FAN_SITE[2]IOB[1].PD_INT_EN
CELL[1].IMUX_FAN_SITE[3]IOB[1].KEEPER_INT_EN
CELL[1].IMUX_FAN_SITE[4]IDELAY[1].IFDLY[0]
CELL[1].IMUX_FAN_SITE[5]IDELAY[1].IFDLY[1]
CELL[1].IMUX_IMUX[0]ILOGIC[1].BITSLIP
CELL[1].IMUX_IMUX[1]OLOGIC[1].TCE
CELL[1].IMUX_IMUX[4]ILOGIC[1].DYNCLKDIVSEL
CELL[1].IMUX_IMUX[5]ILOGIC[1].CE1
CELL[1].IMUX_IMUX[6]IOB[1].INTERMDISABLE
CELL[1].IMUX_IMUX[7]OLOGIC[1].T2
CELL[1].IMUX_IMUX[9]IOB[1].IBUFDISABLE
CELL[1].IMUX_IMUX[10]ILOGIC[1].DYNCLKDIVPSEL
CELL[1].IMUX_IMUX[12]IDELAY[1].REGRST
CELL[1].IMUX_IMUX[13]OLOGIC[1].T3
CELL[1].IMUX_IMUX[14]ILOGIC[1].CE2
CELL[1].IMUX_IMUX[15]OLOGIC[1].T1
CELL[1].IMUX_IMUX[21]OLOGIC[1].T4
CELL[1].IMUX_IMUX[25]IDELAY[1].DATAIN
CELL[1].IMUX_IMUX[26]IDELAY[1].INC
CELL[1].IMUX_IMUX[29]OLOGIC[1].OCE
CELL[1].IMUX_IMUX[30]IDELAY[1].LD
CELL[1].IMUX_IMUX[32]IDELAY[1].CE
CELL[1].IMUX_IMUX[33]IDELAY[1].LDPIPEEN
CELL[1].IMUX_IMUX[34]OLOGIC[1].D1
CELL[1].IMUX_IMUX[35]IDELAY[1].CNTVALUEIN[2]
CELL[1].IMUX_IMUX[36]IDELAY[1].CNTVALUEIN[1]
CELL[1].IMUX_IMUX[37]ILOGIC[1].DYNCLKSEL
CELL[1].IMUX_IMUX[38]IDELAY[1].CNTVALUEIN[3]
CELL[1].IMUX_IMUX[39]IDELAY[1].CNTVALUEIN[4]
CELL[1].IMUX_IMUX[40]OLOGIC[1].D2
CELL[1].IMUX_IMUX[41]IDELAY[1].CNTVALUEIN[0]
CELL[1].IMUX_IMUX[42]OLOGIC[1].D4
CELL[1].IMUX_IMUX[43]OLOGIC[1].D5
CELL[1].IMUX_IMUX[44]OLOGIC[1].D3
CELL[1].IMUX_IMUX[45]OLOGIC[1].D6
CELL[1].IMUX_IMUX[46]OLOGIC[1].D7
CELL[1].IMUX_IMUX[47]OLOGIC[1].D8
CELL[1].OUT_BEL[0]ILOGIC[1].Q1
CELL[1].OUT_BEL[1]IDELAY[1].CNTVALUEOUT[1]
CELL[1].OUT_BEL[2]OLOGIC[1].TFB
CELL[1].OUT_BEL[3]ILOGIC[1].Q6
CELL[1].OUT_BEL[5]OLOGIC[1].IOCLKGLITCH
CELL[1].OUT_BEL[7]ILOGIC[1].Q7
CELL[1].OUT_BEL[8]ILOGIC[1].Q8
CELL[1].OUT_BEL[9]ILOGIC[1].Q3
CELL[1].OUT_BEL[10]ILOGIC[1].Q4
CELL[1].OUT_BEL[11]IDELAY[1].CNTVALUEOUT[4]
CELL[1].OUT_BEL[14]ILOGIC[1].Q5
CELL[1].OUT_BEL[15]IDELAY[1].CNTVALUEOUT[3]
CELL[1].OUT_BEL[18]ILOGIC[1].O
CELL[1].OUT_BEL[19]IDELAY[1].CNTVALUEOUT[2]
CELL[1].OUT_BEL[20]IDELAY[1].CNTVALUEOUT[0]
CELL[1].OUT_BEL[23]ILOGIC[1].Q2
CELL[1].OUT_CLKPADILOGIC[1].CLKPAD
CELL[1].IMUX_IOI_ICLK[0]ILOGIC[1].CLK
CELL[1].IMUX_IOI_ICLK[1]ILOGIC[1].CLKB
CELL[1].IMUX_IOI_ICLKDIVPILOGIC[1].CLKDIVP
CELL[1].IMUX_IOI_OCLK[0]OLOGIC[1].CLK
CELL[1].IMUX_IOI_OCLK[1]OLOGIC[1].CLKB
CELL[1].IMUX_IOI_OCLKDIV[0]OLOGIC[1].CLKDIV
CELL[1].IMUX_IOI_OCLKDIV[1]OLOGIC[1].CLKDIVB
CELL[1].IMUX_IOI_OCLKDIVF[0]OLOGIC[1].CLKDIVF
CELL[1].IMUX_IOI_OCLKDIVF[1]OLOGIC[1].CLKDIVFB

Bitstream

virtex7 IO_HR_PAIR rect MAIN[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: OUTPUT_ENABLE bit 1 - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 2 SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 2 - - - - - - - IOB[0]: OUTPUT_ENABLE bit 0 - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 1 - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 1 - OLOGIC[0]: V5_MUX_T bit 0 - - - - - IOB[0]: OUTPUT_PSEUDO_DIFF - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 0 SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 0 OLOGIC[0]: !invert T1 OLOGIC[0]: V5_MUX_T bit 4 - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_T bit 3 - - - - - IOB[0]: OUTPUT_PSEUDO_DIFF_T - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_T bit 1 - IDELAY[0]: DELAY_SRC bit 2 - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_T bit 2 - IDELAY[0]: DELAY_SRC bit 3 - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: !invert T2 - - IDELAY[0]: DELAY_SRC bit 1 - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[0]: IDATAIN_INV OLOGIC[0]: FFT_SR_SYNC - IDELAY[0]: DELAY_SRC bit 0 - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: SERDES IDELAY[0]: ENABLE - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 6 - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 6 - - - - - - - IOB[0]: HR_LVDS bit 0 - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 9 SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 9 OLOGIC[0]: ! FFT_INIT bit 0 OLOGIC[0]: ! FFT_SRVAL bit 0 - - - - - IOB[0]: HR_LVDS bit 1 - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 10 - OLOGIC[0]: !invert T3 SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 10 - - - - - - - IOB[0]: HR_LVDS bit 2 - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 3 SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 3 - - - - - - - IOB[0]: HR_LVDS bit 3 - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 5 - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 5 - - - - - - - IOB[0]: HR_LVDS bit 4 - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 7 SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 7 OLOGIC[0]: !invert T4 - - - - - - IOB[0]: HR_LVDS bit 5 - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 4 - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 4 - OLOGIC[0]: TBYTE_CTL - - - - - IOB[0]: INPUT_MISC bit 0 - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 8 SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 8 - OLOGIC[0]: ! FFT_SRVAL bit 1 - IDELAY[0]: invert DATAIN - - - IOB[0]: IBUF_PCI - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 1 - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 1 - OLOGIC[0]: ! FFT_SRVAL bit 2 - - - - - IOB[0]: IBUFDISABLE_EN - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 0 SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 0 - OLOGIC[0]: SERDES_MODE bit 0 - - - - - IOB[0]: IBUF_DIFF_HP - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 2 - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 2 - OLOGIC[0]: TBYTE_SRC - - - - - IOB[0]: IBUF_VREF_HP - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert CLKDIV - - - - - - IOB[0]: IBUF_MODE bit 2 - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! RANK3_USED - - - - - - - - IOB[0]: IBUF_MODE bit 1 - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: IBUF_MODE bit 0 - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 5 - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 5 - - - IDELAY[0]: invert C - - - IOB[0]: VREF_SYSMON - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 9 SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 9 - OLOGIC[0]: FFT_SR_ENABLE - IDELAY[0]: CINVCTRL_SEL - - - IOB[0]: INTERMDISABLE_EN - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! CLK1_INV - - OLOGIC[0]: TRISTATE_WIDTH bit 0 - - - - - IOB[0]: DQS_BIAS - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_O bit 2 - - - - - IOB[0]: PULL_DYNAMIC - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 10 - OLOGIC[0]: ! CLK2_INV SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 10 - - - - - - - IOB[0]: PULL bit 2 - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 4 SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 4 - OLOGIC[0]: V5_MUX_O bit 1 - - - - - IOB[0]: PULL bit 1 - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 3 - OLOGIC[0]: invert CLKDIVF SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 3 - OLOGIC[0]: FFO_SR_SYNC - IDELAY[0]: ! IDELAY_VALUE_CUR bit 4 - - - IOB[0]: PULL bit 0 - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 6 SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 6 OLOGIC[0]: CLOCK_RATIO bit 1 OLOGIC[0]: ! FFO_SRVAL bit 0 - - - - - IOB[0]: LOW_VOLTAGE - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 8 - OLOGIC[0]: SELFHEAL SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 8 - - - IDELAY[0]: IDELAY_VALUE_INIT bit 4 - - - IOB[0]: HR_LVDS bit 6 - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 7 SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 7 OLOGIC[0]: invert D1 OLOGIC[0]: ! FFO_INIT bit 0 - - - - - IOB[0]: HR_LVDS bit 7 - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLKDIVP bit 0 - OLOGIC[0]: CLOCK_RATIO bit 2 - - - - - - - - IOB[0]: HR_LVDS bit 8 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_ICLKDIVP bit 1 - OLOGIC[0]: CLOCK_RATIO bit 0 - - - - - - IOB[0]: HR_LVDS bit 9 - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: CLOCK_RATIO bit 3 - - - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 3 - - - IOB[0]: HR_LVDS bit 10 - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 8 - - - - - - IOB[0]: HR_LVDS bit 11 - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D2 - - - - IDELAY[0]: IDELAY_VALUE_INIT bit 3 - - - IOB[0]: HR_LVDS bit 12 - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: LVDS_GROUP bit 0 - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: HR_PSLEW bit 2 - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D3 - - - - IDELAY[0]: PIPE_SEL - - - IOB[0]: ! HR_PSLEW bit 1 - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFO_SRVAL bit 1 - - - - - IOB[0]: HR_PSLEW bit 0 - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFO_SRVAL bit 2 - IDELAY[0]: ! IDELAY_VALUE_CUR bit 2 - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[0]: HIGH_PERFORMANCE_MODE - - - - IOB[0]: HR_NSLEW bit 2 - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[0] bit 0 - OLOGIC[0]: invert D4 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[1] bit 0 - OLOGIC[0]: V5_MUX_O bit 4 - IDELAY[0]: IDELAY_VALUE_INIT bit 2 - - - IOB[0]: ! HR_NSLEW bit 1 - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[0] bit 1 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[1] bit 1 OLOGIC[0]: MISR_ENABLE OLOGIC[0]: V5_MUX_O bit 0 - - - - - IOB[0]: HR_NSLEW bit 0 - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_CLK_SELECT bit 0 - - OLOGIC[0]: FFO_SR_ENABLE - - - - - IOB[0]: HR_OUTPUT_MISC bit 1 - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D5 OLOGIC[0]: V5_MUX_O bit 3 - IDELAY[0]: DELAY_TYPE bit 1 - - - IOB[0]: ! HR_OUTPUT_MISC bit 0 - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D6 - - - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 1 - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 7 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 6 - - - - IDELAY[0]: IDELAY_VALUE_INIT bit 1 - - - IOB[0]: HR_NDRIVE bit 3 - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_ENABLE_FDBK - - - - - - IOB[0]: HR_NDRIVE bit 2 - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[0] bit 5 - OLOGIC[0]: invert D7 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[1] bit 5 - - - - - - - IOB[0]: ! HR_NDRIVE bit 1 - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[0] bit 6 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[1] bit 6 OLOGIC[0]: MISR_RESET - - IDELAY[0]: DELAY_TYPE bit 0 - - - IOB[0]: ! HR_NDRIVE bit 0 - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 4 - - - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 0 - - - IOB[0]: IN_TERM bit 1 - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[0] bit 4 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[1] bit 4 OLOGIC[0]: DATA_WIDTH bit 3 - - - - - - IOB[0]: IN_TERM bit 3 - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_CLK_SELECT bit 1 - - - - IDELAY[0]: IDELAY_VALUE_INIT bit 0 - - - IOB[0]: IN_TERM bit 2 - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[0] bit 0 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[1] bit 0 OLOGIC[0]: DATA_WIDTH bit 5 - - - - - - IOB[0]: IN_TERM bit 0 - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[0] bit 1 - OLOGIC[0]: DATA_WIDTH bit 2 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[1] bit 1 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[0] bit 3 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[1] bit 3 OLOGIC[0]: invert D8 - - - - - - IOB[0]: ! HR_PDRIVE bit 2 - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[0] bit 2 - OLOGIC[0]: DATA_WIDTH bit 1 SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIVF[1] bit 2 - - - - - - - IOB[0]: HR_PDRIVE bit 1 - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 0 - - - - - - IOB[0]: HR_PDRIVE bit 0 - - -
virtex7 IO_HR_PAIR rect MAIN[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: DATA_WIDTH bit 0 - - - - - - - - IOB[1]: HR_PDRIVE bit 0 - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[0] bit 1 SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[1] bit 1 OLOGIC[1]: DATA_WIDTH bit 1 - - - - - - IOB[1]: HR_PDRIVE bit 1 - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[0] bit 3 - OLOGIC[1]: invert D8 SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[1] bit 3 - - - - - - - IOB[1]: ! HR_PDRIVE bit 2 - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[0] bit 0 SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[1] bit 0 OLOGIC[1]: DATA_WIDTH bit 2 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[0] bit 2 - OLOGIC[1]: DATA_WIDTH bit 5 SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[1] bit 2 - - - - - - - IOB[1]: IN_TERM bit 1 - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: MISR_CLK_SELECT bit 1 - - IDELAY[1]: IDELAY_VALUE_INIT bit 0 - - - IOB[1]: IN_TERM bit 2 - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[0] bit 6 - OLOGIC[1]: DATA_WIDTH bit 3 SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[1] bit 6 - - - - - - - IOB[1]: IN_TERM bit 3 - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: DATA_WIDTH bit 4 - - IDELAY[1]: ! IDELAY_VALUE_CUR bit 0 - - - IOB[1]: IN_TERM bit 0 - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[0] bit 5 - OLOGIC[1]: MISR_RESET SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[1] bit 5 - - - IDELAY[1]: DELAY_TYPE bit 0 - - - IOB[1]: ! HR_NDRIVE bit 0 - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[0] bit 4 SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIVF[1] bit 4 OLOGIC[1]: invert D7 - - - - - - IOB[1]: ! HR_NDRIVE bit 1 - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: MISR_ENABLE_FDBK - - - - - - - - IOB[1]: HR_NDRIVE bit 2 - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: DATA_WIDTH bit 6 - - IDELAY[1]: IDELAY_VALUE_INIT bit 1 - - - IOB[1]: HR_NDRIVE bit 3 - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: DATA_WIDTH bit 7 - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: invert D6 - - IDELAY[1]: ! IDELAY_VALUE_CUR bit 1 - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: invert D5 - - OLOGIC[1]: V5_MUX_O bit 3 - IDELAY[1]: DELAY_TYPE bit 1 - - - IOB[1]: ! HR_OUTPUT_MISC bit 0 - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: MISR_CLK_SELECT bit 0 OLOGIC[1]: FFO_SR_ENABLE - - - - - IOB[1]: HR_OUTPUT_MISC bit 1 - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[0] bit 1 - OLOGIC[1]: MISR_ENABLE SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[1] bit 1 - OLOGIC[1]: V5_MUX_O bit 0 - - - - - IOB[1]: HR_NSLEW bit 0 - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[0] bit 0 SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[1] bit 0 OLOGIC[1]: invert D4 OLOGIC[1]: V5_MUX_O bit 4 - IDELAY[1]: IDELAY_VALUE_INIT bit 2 - - - IOB[1]: ! HR_NSLEW bit 1 - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[1]: HIGH_PERFORMANCE_MODE - - - - - - IOB[1]: HR_NSLEW bit 2 - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: ! FFO_SRVAL bit 2 - IDELAY[1]: ! IDELAY_VALUE_CUR bit 2 - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: ! FFO_SRVAL bit 1 - - - - - IOB[1]: HR_PSLEW bit 0 - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: invert D3 - - IDELAY[1]: PIPE_SEL - - - IOB[1]: ! HR_PSLEW bit 1 - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[1]: HR_PSLEW bit 2 - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[1]: LVDS_GROUP bit 0 - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: invert D2 - - IDELAY[1]: IDELAY_VALUE_INIT bit 3 - - - IOB[1]: HR_LVDS bit 12 - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: DATA_WIDTH bit 8 - - - - - - - - IOB[1]: HR_LVDS bit 11 - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: CLOCK_RATIO bit 3 - - IDELAY[1]: ! IDELAY_VALUE_CUR bit 3 - - - IOB[1]: HR_LVDS bit 10 - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLKDIVP bit 1 - OLOGIC[1]: CLOCK_RATIO bit 0 - - - - - - - - IOB[1]: HR_LVDS bit 9 - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLKDIVP bit 0 - OLOGIC[1]: CLOCK_RATIO bit 2 - - - - - - IOB[1]: HR_LVDS bit 8 - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 5 - OLOGIC[1]: invert D1 SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 5 - OLOGIC[1]: ! FFO_INIT bit 0 - - - - - IOB[1]: HR_LVDS bit 7 - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 7 SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 7 OLOGIC[1]: SELFHEAL - - IDELAY[1]: IDELAY_VALUE_INIT bit 4 - - - IOB[1]: HR_LVDS bit 6 - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 4 - OLOGIC[1]: CLOCK_RATIO bit 1 SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 4 - OLOGIC[1]: ! FFO_SRVAL bit 0 - - - - - IOB[1]: LOW_VOLTAGE - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 6 SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 6 OLOGIC[1]: invert CLKDIVF OLOGIC[1]: FFO_SR_SYNC - IDELAY[1]: ! IDELAY_VALUE_CUR bit 4 - - - IOB[1]: PULL bit 0 - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 10 - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 10 - OLOGIC[1]: V5_MUX_O bit 1 - - - - - IOB[1]: PULL bit 1 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 9 SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 9 OLOGIC[1]: ! CLK2_INV - - - - - - IOB[1]: PULL bit 2 - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: V5_MUX_O bit 2 - - - - - IOB[1]: PULL_DYNAMIC - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: ! CLK1_INV OLOGIC[1]: TRISTATE_WIDTH bit 0 - - - - - IOB[1]: DQS_BIAS - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 8 - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 8 - OLOGIC[1]: FFT_SR_ENABLE - IDELAY[1]: CINVCTRL_SEL - - - IOB[1]: INTERMDISABLE_EN - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 3 SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 3 - - - IDELAY[1]: invert C - - - IOB[1]: VREF_SYSMON - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[1]: IBUF_MODE bit 0 - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: ! RANK3_USED - - - - - - IOB[1]: IBUF_MODE bit 1 - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: invert CLKDIV - - - - - - - - IOB[1]: IBUF_MODE bit 2 - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 2 SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 2 - OLOGIC[1]: TBYTE_SRC - - - - - IOB[1]: IBUF_VREF_HP - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 0 - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 0 - OLOGIC[1]: SERDES_MODE bit 0 - - - - - IOB[1]: IBUF_DIFF_HP - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 1 SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 1 - OLOGIC[1]: ! FFT_SRVAL bit 2 - - - - - IOB[1]: IBUFDISABLE_EN - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 5 - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 5 - OLOGIC[1]: ! FFT_SRVAL bit 1 - IDELAY[1]: invert DATAIN - - - IOB[1]: IBUF_PCI - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 7 SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 7 - OLOGIC[1]: TBYTE_CTL - - - - - IOB[1]: INPUT_MISC bit 0 - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 4 - OLOGIC[1]: !invert T4 SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 4 - - - - - - - IOB[1]: HR_LVDS bit 5 - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 6 SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 6 - - - - - - - IOB[1]: HR_LVDS bit 4 - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 10 - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 10 - - - - - - - IOB[1]: HR_LVDS bit 3 - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 9 SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 9 OLOGIC[1]: !invert T3 - - - - - - IOB[1]: HR_LVDS bit 2 - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 8 - OLOGIC[1]: ! FFT_INIT bit 0 SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 8 - OLOGIC[1]: ! FFT_SRVAL bit 0 - - - - - IOB[1]: HR_LVDS bit 1 - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 3 SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 3 - - - - - - - IOB[1]: HR_LVDS bit 0 - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[1]: ENABLE OLOGIC[1]: SERDES - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFT_SR_SYNC IDELAY[1]: IDATAIN_INV IDELAY[1]: DELAY_SRC bit 0 - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: !invert T2 - - - - IDELAY[1]: DELAY_SRC bit 1 - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: V5_MUX_T bit 2 - IDELAY[1]: DELAY_SRC bit 3 - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: V5_MUX_T bit 1 - IDELAY[1]: DELAY_SRC bit 2 - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: V5_MUX_T bit 3 - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 0 - OLOGIC[1]: !invert T1 SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 0 - OLOGIC[1]: V5_MUX_T bit 4 - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 1 SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 1 - OLOGIC[1]: V5_MUX_T bit 0 - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 2 - - SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 2 - - - - - - - IOB[1]: OUTPUT_ENABLE bit 0 - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[1]: OUTPUT_ENABLE bit 1 - - -
### Bitstream
virtex7 IO_HR_PAIR rect R0
BitFrame
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B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.OCLK1
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:D_EMU1 -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:D_EMU2
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SRTYPE[0] -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IFF_SR_USED - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF_LATCH ~ILOGIC[0]:IFF1_SRVAL -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF1_INIT
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF2_SRVAL -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF2_INIT
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:NUM_CE[0] - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IDELAY_VALUE[4] -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IFFDELAY_VALUE[4]
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF3_SRVAL -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF3_INIT
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IDELAY_VALUE[3] -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IFFDELAY_VALUE[3]
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF4_SRVAL -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF4_INIT
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.ZHOLD_FABRIC
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:I_ZHOLD -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DDR_CLK_EDGE[0] - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DDR_CLK_EDGE[1] - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:RANK23_DLY - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[1] ILOGIC[0]:I_DELAY_ENABLE -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SERDES - - ILOGIC[0]:ZHOLD_ENABLE
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:I_TSBYPASS_ENABLE -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IDELAY_VALUE[2]
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IFFDELAY_VALUE[2] -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SERDES_MODE[0] - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:BITSLIP_ENABLE - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_RATE[0] - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[3] ~ILOGIC[0]:INV.D -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[2] - - ILOGIC[0]:TSBYPASS_MUX[0]
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[1] ILOGIC[0]:IDELAY_VALUE[1] -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[0] - - ILOGIC[0]:IFFDELAY_VALUE[1]
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[3] ILOGIC[0]:IFF_TSBYPASS_ENABLE -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.CLKDIVP - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[4] - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLKDIVP_INV_EN - - ILOGIC[0]:IFF_DELAY_ENABLE
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[2] ILOGIC[0]:IDELAY_VALUE[0] -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLKDIV_INV_EN - - ILOGIC[0]:IFFDELAY_VALUE[0]
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.CLKDIV ILOGIC[0]:IFF_ZHOLD -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.ZHOLD_IFF
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[0] - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[1] -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.OCLK2
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[0] -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[2]
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLK_INV_EN -
virtex7 IO_HR_PAIR rect R1
BitFrame
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B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DYN_CLK_INV_EN
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:INV.CLK[0] -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:INV.CLK[2]
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INV.OCLK2 -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:INV.CLK[1]
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INTERFACE_TYPE[0] - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INV.ZHOLD_IFF -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INV.CLKDIV - - ILOGIC[1]:IFF_ZHOLD
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DYN_CLKDIV_INV_EN ILOGIC[1]:IFFDELAY_VALUE[0] -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INTERFACE_TYPE[2] - - ILOGIC[1]:IDELAY_VALUE[0]
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DYN_CLKDIVP_INV_EN ILOGIC[1]:IFF_DELAY_ENABLE -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INTERFACE_TYPE[4] - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INV.CLKDIVP - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INTERFACE_TYPE[3] - - ILOGIC[1]:IFF_TSBYPASS_ENABLE
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DATA_WIDTH[0] ILOGIC[1]:IFFDELAY_VALUE[1] -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DATA_WIDTH[1] - - ILOGIC[1]:IDELAY_VALUE[1]
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DATA_WIDTH[2] ILOGIC[1]:TSBYPASS_MUX[0] -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DATA_WIDTH[3] - - ~ILOGIC[1]:INV.D
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DATA_RATE[0] - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:BITSLIP_ENABLE - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:SERDES_MODE[0] - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:IFFDELAY_VALUE[2]
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:IDELAY_VALUE[2] -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:I_TSBYPASS_ENABLE
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:SERDES ILOGIC[1]:ZHOLD_ENABLE -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INTERFACE_TYPE[1] - - ILOGIC[1]:I_DELAY_ENABLE
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:RANK23_DLY - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DDR_CLK_EDGE[1] - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:DDR_CLK_EDGE[0] - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:I_ZHOLD
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INV.ZHOLD_FABRIC -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:IFF4_INIT -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:IFF4_SRVAL
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:IFFDELAY_VALUE[3] -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:IDELAY_VALUE[3]
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:IFF3_INIT -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:IFF3_SRVAL
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:IFFDELAY_VALUE[4] -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:IDELAY_VALUE[4]
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:NUM_CE[0] - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:IFF2_INIT -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:IFF2_SRVAL
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:IFF1_INIT -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[1]:IFF_LATCH - - ~ILOGIC[1]:IFF1_SRVAL
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:IFF_SR_USED - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:SRTYPE[0]
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:D_EMU2 -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:D_EMU1
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]:INV.OCLK1 -
ILOGIC[0]:BITSLIP_ENABLE 0.F27.B20
ILOGIC[0]:DYN_CLKDIVP_INV_EN 0.F26.B11
ILOGIC[0]:DYN_CLKDIV_INV_EN 0.F26.B9
ILOGIC[0]:DYN_CLK_INV_EN 0.F28.B0
ILOGIC[0]:D_EMU1 0.F28.B62
ILOGIC[0]:D_EMU2 0.F29.B61
ILOGIC[0]:IFF_DELAY_ENABLE 0.F29.B11
ILOGIC[0]:IFF_SR_USED 0.F26.B57
ILOGIC[0]:IFF_TSBYPASS_ENABLE 0.F28.B14
ILOGIC[0]:IFF_ZHOLD 0.F28.B8
ILOGIC[0]:INV.CLKDIV 0.F27.B8
ILOGIC[0]:INV.CLKDIVP 0.F26.B13
ILOGIC[0]:INV.OCLK1 0.F29.B63
ILOGIC[0]:INV.OCLK2 0.F29.B3
ILOGIC[0]:INV.ZHOLD_FABRIC 0.F29.B31
ILOGIC[0]:INV.ZHOLD_IFF 0.F29.B7
ILOGIC[0]:I_DELAY_ENABLE 0.F28.B26
ILOGIC[0]:I_TSBYPASS_ENABLE 0.F28.B24
ILOGIC[0]:I_ZHOLD 0.F28.B30
ILOGIC[0]:RANK23_DLY 0.F26.B27
ILOGIC[0]:SERDES 0.F26.B25
ILOGIC[0]:ZHOLD_ENABLE 0.F29.B25
ILOGIC[1]:BITSLIP_ENABLE 1.F26.B43
ILOGIC[1]:DYN_CLKDIVP_INV_EN 1.F27.B52
ILOGIC[1]:DYN_CLKDIV_INV_EN 1.F27.B54
ILOGIC[1]:DYN_CLK_INV_EN 1.F29.B63
ILOGIC[1]:D_EMU1 1.F29.B1
ILOGIC[1]:D_EMU2 1.F28.B2
ILOGIC[1]:IFF_DELAY_ENABLE 1.F28.B52
ILOGIC[1]:IFF_SR_USED 1.F27.B6
ILOGIC[1]:IFF_TSBYPASS_ENABLE 1.F29.B49
ILOGIC[1]:IFF_ZHOLD 1.F29.B55
ILOGIC[1]:INV.CLKDIV 1.F26.B55
ILOGIC[1]:INV.CLKDIVP 1.F27.B50
ILOGIC[1]:INV.OCLK1 1.F28.B0
ILOGIC[1]:INV.OCLK2 1.F28.B60
ILOGIC[1]:INV.ZHOLD_FABRIC 1.F28.B32
ILOGIC[1]:INV.ZHOLD_IFF 1.F28.B56
ILOGIC[1]:I_DELAY_ENABLE 1.F29.B37
ILOGIC[1]:I_TSBYPASS_ENABLE 1.F29.B39
ILOGIC[1]:I_ZHOLD 1.F29.B33
ILOGIC[1]:RANK23_DLY 1.F27.B36
ILOGIC[1]:SERDES 1.F27.B38
ILOGIC[1]:ZHOLD_ENABLE 1.F28.B38
non-inverted [0]
ILOGIC[0]:DATA_RATE 0.F26.B19
ILOGIC[1]:DATA_RATE 1.F27.B44
DDR 0
SDR 1
ILOGIC[0]:DATA_WIDTH 0.F27.B18 0.F26.B17 0.F27.B16 0.F26.B15
ILOGIC[1]:DATA_WIDTH 1.F26.B45 1.F27.B46 1.F26.B47 1.F27.B48
NONE 0 0 0 0
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
10 1 0 1 0
14 1 1 1 0
ILOGIC[0]:DDR_CLK_EDGE 0.F27.B28 0.F26.B29
ILOGIC[1]:DDR_CLK_EDGE 1.F26.B35 1.F27.B34
SAME_EDGE_PIPELINED 0 0
OPPOSITE_EDGE 0 1
SAME_EDGE 1 0
ILOGIC[0]:IDELAY_VALUE 0.F28.B46 0.F28.B38 0.F29.B23 0.F28.B16 0.F28.B10
ILOGIC[0]:IFFDELAY_VALUE 0.F29.B45 0.F29.B37 0.F28.B22 0.F29.B15 0.F29.B9
ILOGIC[1]:IDELAY_VALUE 1.F29.B17 1.F29.B25 1.F28.B40 1.F29.B47 1.F29.B53
ILOGIC[1]:IFFDELAY_VALUE 1.F28.B18 1.F28.B26 1.F29.B41 1.F28.B48 1.F28.B54
non-inverted [4] [3] [2] [1] [0]
ILOGIC[0]:IFF1_INIT 0.F29.B55
ILOGIC[0]:IFF1_SRVAL 0.F28.B56
ILOGIC[0]:IFF2_INIT 0.F29.B51
ILOGIC[0]:IFF2_SRVAL 0.F28.B52
ILOGIC[0]:IFF3_INIT 0.F29.B41
ILOGIC[0]:IFF3_SRVAL 0.F28.B42
ILOGIC[0]:IFF4_INIT 0.F29.B33
ILOGIC[0]:IFF4_SRVAL 0.F28.B34
ILOGIC[0]:IFF_LATCH 0.F27.B56
ILOGIC[0]:INV.D 0.F28.B18
ILOGIC[1]:IFF1_INIT 1.F28.B8
ILOGIC[1]:IFF1_SRVAL 1.F29.B7
ILOGIC[1]:IFF2_INIT 1.F28.B12
ILOGIC[1]:IFF2_SRVAL 1.F29.B11
ILOGIC[1]:IFF3_INIT 1.F28.B22
ILOGIC[1]:IFF3_SRVAL 1.F29.B21
ILOGIC[1]:IFF4_INIT 1.F28.B30
ILOGIC[1]:IFF4_SRVAL 1.F29.B29
ILOGIC[1]:IFF_LATCH 1.F26.B7
ILOGIC[1]:INV.D 1.F29.B45
inverted ~[0]
ILOGIC[0]:INTERFACE_TYPE 0.F27.B12 0.F27.B14 0.F27.B10 0.F27.B26 0.F27.B6
ILOGIC[1]:INTERFACE_TYPE 1.F26.B51 1.F26.B49 1.F26.B53 1.F26.B37 1.F26.B57
MEMORY 0 0 0 0 0
NETWORKING 0 0 0 0 1
MEMORY_DDR3 0 0 1 1 1
MEMORY_DDR3_V6 0 1 0 1 1
OVERSAMPLE 1 0 0 1 1
ILOGIC[0]:INV.CLK 0.F29.B1 0.F28.B4 0.F28.B2
ILOGIC[1]:INV.CLK 1.F29.B61 1.F29.B59 1.F28.B62
inverted ~[2] ~[1] ~[0]
ILOGIC[0]:NUM_CE 0.F26.B47
ILOGIC[1]:NUM_CE 1.F27.B16
1 0
2 1
ILOGIC[0]:SERDES_MODE 0.F26.B21
ILOGIC[1]:SERDES_MODE 1.F27.B42
MASTER 0
SLAVE 1
ILOGIC[0]:SRTYPE 0.F28.B60
ILOGIC[1]:SRTYPE 1.F29.B3
ASYNC 0
SYNC 1
ILOGIC[0]:TSBYPASS_MUX 0.F29.B17
ILOGIC[1]:TSBYPASS_MUX 1.F28.B46
T 0
GND 1

Tile IO_HR_S

Cells: 1

Switchbox SPEC_INT

virtex7 IO_HR_S switchbox SPEC_INT permanent buffers
DestinationSource
IMUX_SPEC[0]IMUX_IOI_OCLKDIV[0]
IMUX_SPEC[2]IMUX_IOI_OCLK[0]
virtex7 IO_HR_S switchbox SPEC_INT muxes IMUX_IOI_ICLK[0]
BitsDestination
MAIN[29][12]MAIN[28][11]MAIN[28][17]MAIN[28][15]MAIN[29][10]MAIN[29][14]MAIN[29][16]MAIN[28][13]MAIN[28][1]MAIN[29][2]MAIN[28][3]IMUX_IOI_ICLK[0]
Source
00000000000off
00000000010PHASER_ICLK
00000000100PHASER_OCLK
00000011001IMUX_IMUX[20]
00000101001IMUX_IMUX[22]
00001010001LCLK_IO[3]
00001100001LCLK_IO[2]
00010001001IOCLK[2]
00011000001LCLK_IO[0]
00100001001IOCLK[3]
00101000001LCLK_IO[1]
01000010001RCLK_IO[1]
01000100001RCLK_IO[0]
01010000001LCLK_IO[4]
01100000001LCLK_IO[5]
10000010001IOCLK[1]
10000100001IOCLK[0]
10010000001RCLK_IO[2]
10100000001RCLK_IO[3]
virtex7 IO_HR_S switchbox SPEC_INT muxes IMUX_IOI_ICLK[1]
BitsDestination
MAIN[30][12]MAIN[31][11]MAIN[31][17]MAIN[31][15]MAIN[30][10]MAIN[30][14]MAIN[30][16]MAIN[31][13]MAIN[31][1]MAIN[30][2]MAIN[31][3]IMUX_IOI_ICLK[1]
Source
00000000000off
00000000010PHASER_ICLK
00000000100PHASER_OCLK
00000011001IMUX_IMUX[20]
00000101001IMUX_IMUX[22]
00001010001LCLK_IO[3]
00001100001LCLK_IO[2]
00010001001IOCLK[2]
00011000001LCLK_IO[0]
00100001001IOCLK[3]
00101000001LCLK_IO[1]
01000010001RCLK_IO[1]
01000100001RCLK_IO[0]
01010000001LCLK_IO[4]
01100000001LCLK_IO[5]
10000010001IOCLK[1]
10000100001IOCLK[0]
10010000001RCLK_IO[2]
10100000001RCLK_IO[3]
virtex7 IO_HR_S switchbox SPEC_INT muxes IMUX_IOI_ICLKDIVP
BitsDestination
MAIN[28][35]MAIN[29][34]IMUX_IOI_ICLKDIVP
Source
00off
01IMUX_CLK[0]
10PHASER_ICLKDIV
virtex7 IO_HR_S switchbox SPEC_INT muxes IMUX_IOI_OCLK[0]
BitsDestination
MAIN[29][28]MAIN[28][25]MAIN[29][32]MAIN[28][33]MAIN[28][31]MAIN[29][24]MAIN[28][29]MAIN[29][30]MAIN[29][20]MAIN[29][18]MAIN[28][19]IMUX_IOI_OCLK[0]
Source
00000000000off
00000000010PHASER_OCLK
00000000100PHASER_OCLK90
00000011001IMUX_IMUX[31]
00000101001LCLK_IO[2]
00001010001IOCLK[2]
00001100001LCLK_IO[0]
00010010001IOCLK[3]
00010100001LCLK_IO[1]
00100100001LCLK_IO[3]
01000001001RCLK_IO[0]
01001000001LCLK_IO[4]
01010000001LCLK_IO[5]
01100000001RCLK_IO[1]
10000001001IOCLK[0]
10001000001RCLK_IO[2]
10010000001RCLK_IO[3]
10100000001IOCLK[1]
virtex7 IO_HR_S switchbox SPEC_INT muxes IMUX_IOI_OCLK[1]
BitsDestination
MAIN[30][28]MAIN[31][25]MAIN[30][32]MAIN[31][33]MAIN[31][31]MAIN[30][24]MAIN[31][29]MAIN[30][30]MAIN[30][20]MAIN[30][18]MAIN[31][19]IMUX_IOI_OCLK[1]
Source
00000000000off
00000000010PHASER_OCLK
00000000100PHASER_OCLK90
00000011001IMUX_IMUX[31]
00000101001LCLK_IO[2]
00001010001IOCLK[2]
00001100001LCLK_IO[0]
00010010001IOCLK[3]
00010100001LCLK_IO[1]
00100100001LCLK_IO[3]
01000001001RCLK_IO[0]
01001000001LCLK_IO[4]
01010000001LCLK_IO[5]
01100000001RCLK_IO[1]
10000001001IOCLK[0]
10001000001RCLK_IO[2]
10010000001RCLK_IO[3]
10100000001IOCLK[1]
virtex7 IO_HR_S switchbox SPEC_INT muxes IMUX_IOI_OCLKDIV[0]
BitsDestination
MAIN[28][47]MAIN[29][46]IMUX_IOI_OCLKDIV[0]
Source
00off
01PHASER_OCLKDIV
10IMUX_IOI_OCLKDIVF[0]
virtex7 IO_HR_S switchbox SPEC_INT muxes IMUX_IOI_OCLKDIV[1]
BitsDestination
MAIN[31][47]MAIN[30][46]IMUX_IOI_OCLKDIV[1]
Source
00off
01PHASER_OCLKDIV
10IMUX_IOI_OCLKDIVF[1]
virtex7 IO_HR_S switchbox SPEC_INT muxes IMUX_IOI_OCLKDIVF[0]
BitsDestination
MAIN[28][55]MAIN[29][54]MAIN[28][57]MAIN[28][61]MAIN[29][62]MAIN[29][60]MAIN[28][59]IMUX_IOI_OCLKDIVF[0]
Source
0000000off
0010001IMUX_IMUX[8]
0010010RCLK_IO[2]
0010100RCLK_IO[3]
0100001LCLK_IO[2]
0100010LCLK_IO[0]
0100100LCLK_IO[1]
0101000LCLK_IO[3]
1000001RCLK_IO[0]
1000010LCLK_IO[4]
1000100LCLK_IO[5]
1001000RCLK_IO[1]
virtex7 IO_HR_S switchbox SPEC_INT muxes IMUX_IOI_OCLKDIVF[1]
BitsDestination
MAIN[31][55]MAIN[30][54]MAIN[31][57]MAIN[31][61]MAIN[30][62]MAIN[30][60]MAIN[31][59]IMUX_IOI_OCLKDIVF[1]
Source
0000000off
0010001IMUX_IMUX[8]
0010010RCLK_IO[2]
0010100RCLK_IO[3]
0100001LCLK_IO[2]
0100010LCLK_IO[0]
0100100LCLK_IO[1]
0101000LCLK_IO[3]
1000001RCLK_IO[0]
1000010LCLK_IO[4]
1000100LCLK_IO[5]
1001000RCLK_IO[1]

Bels ILOGIC

virtex7 IO_HR_S bel ILOGIC pins
PinDirectionILOGIC[0]
CLKinIMUX_IOI_ICLK[0]
CLKBinIMUX_IOI_ICLK[1]
CLKDIVinIMUX_CLK[0]
CLKDIVPinIMUX_IOI_ICLKDIVP
SRinIMUX_CTRL[1]
CE1inIMUX_IMUX[5]
CE2inIMUX_IMUX[14]
BITSLIPinIMUX_IMUX[0]
DYNCLKSELinIMUX_IMUX[37]
DYNCLKDIVSELinIMUX_IMUX[4]
DYNCLKDIVPSELinIMUX_IMUX[10]
OoutOUT_BEL[18]
Q1outOUT_BEL[0]
Q2outOUT_BEL[23]
Q3outOUT_BEL[9]
Q4outOUT_BEL[10]
Q5outOUT_BEL[14]
Q6outOUT_BEL[3]
Q7outOUT_BEL[7]
Q8outOUT_BEL[8]
virtex7 IO_HR_S bel ILOGIC attribute bits
AttributeILOGIC[0]

Bels OLOGIC

virtex7 IO_HR_S bel OLOGIC pins
PinDirectionOLOGIC[0]
CLKinIMUX_IOI_OCLK[0]
CLKBinIMUX_IOI_OCLK[1]
CLKDIVinIMUX_IOI_OCLKDIV[0] invert by MAIN[30][21]
CLKDIVBinIMUX_IOI_OCLKDIV[1]
CLKDIVFinIMUX_IOI_OCLKDIVF[0] invert by MAIN[31][30]
CLKDIVFBinIMUX_IOI_OCLKDIVF[1]
SRinIMUX_CTRL[0]
OCEinIMUX_IMUX[29]
TCEinIMUX_IMUX[1]
D1inIMUX_IMUX[34] invert by MAIN[30][33]
D2inIMUX_IMUX[40] invert by MAIN[31][38]
D3inIMUX_IMUX[44] invert by MAIN[31][42]
D4inIMUX_IMUX[42] invert by MAIN[31][46]
D5inIMUX_IMUX[43] invert by MAIN[30][49]
D6inIMUX_IMUX[45] invert by MAIN[31][50]
D7inIMUX_IMUX[46] invert by MAIN[31][54]
D8inIMUX_IMUX[47] invert by MAIN[30][61]
T1inIMUX_IMUX[15] invert by !MAIN[30][3]
T2inIMUX_IMUX[7] invert by !MAIN[30][7]
T3inIMUX_IMUX[13] invert by !MAIN[31][12]
T4inIMUX_IMUX[21] invert by !MAIN[30][15]
TFBoutOUT_BEL[2]
IOCLKGLITCHoutOUT_BEL[5]
virtex7 IO_HR_S bel OLOGIC attribute bits
AttributeOLOGIC[0]
CLK1_INV!MAIN[31][26]
CLK2_INV!MAIN[31][28]
FFO_INIT bit 0!MAIN[33][33]
FFO_SRVAL bit 0!MAIN[33][31]
FFO_SRVAL bit 1!MAIN[33][43]
FFO_SRVAL bit 2!MAIN[32][44]
FFO_SR_SYNCMAIN[32][30]
FFO_SR_ENABLEMAIN[32][48]
V5_MUX_O[enum: OLOGIC_V5_MUX_O]
FFT_INIT bit 0!MAIN[30][11]
FFT_SRVAL bit 0!MAIN[33][11]
FFT_SRVAL bit 1!MAIN[33][17]
FFT_SRVAL bit 2!MAIN[32][18]
FFT_SR_SYNCMAIN[32][8]
FFT_SR_ENABLEMAIN[33][25]
V5_MUX_T[enum: OLOGIC_V5_MUX_T]
SERDESMAIN[33][9]
SERDES_MODE[enum: IO_SERDES_MODE]
DATA_WIDTH[enum: IO_DATA_WIDTH]
TRISTATE_WIDTH[enum: OLOGIC_TRISTATE_WIDTH]
MISR_ENABLEMAIN[30][47]
MISR_ENABLE_FDBKMAIN[30][53]
MISR_RESETMAIN[30][55]
MISR_CLK_SELECT[enum: OLOGIC_MISR_CLK_SELECT]
CLOCK_RATIO[enum: OLOGIC_CLOCK_RATIO]
SELFHEALMAIN[31][32]
RANK3_USED!MAIN[31][22]
TBYTE_CTLMAIN[32][16]
TBYTE_SRCMAIN[32][20]
virtex7 IO_HR_S enum OLOGIC_V5_MUX_O
OLOGIC[0].V5_MUX_OMAIN[32][46]MAIN[33][49]MAIN[33][27]MAIN[33][29]MAIN[33][47]
NONE00000
D100001
SERDES_SDR00010
LATCH10010
FF01010
DDR00100
virtex7 IO_HR_S enum OLOGIC_V5_MUX_T
OLOGIC[0].V5_MUX_TMAIN[33][3]MAIN[32][4]MAIN[32][6]MAIN[33][5]MAIN[32][2]
NONE00000
T100001
SERDES_SDR00010
LATCH10010
FF01010
DDR00100
virtex7 IO_HR_S enum IO_SERDES_MODE
OLOGIC[0].SERDES_MODEMAIN[33][19]
MASTER0
SLAVE1
virtex7 IO_HR_S enum IO_DATA_WIDTH
OLOGIC[0].DATA_WIDTHMAIN[30][37]MAIN[30][51]MAIN[31][52]MAIN[30][59]MAIN[31][56]MAIN[30][57]MAIN[31][60]MAIN[31][62]MAIN[30][63]
NONE000000000
_2000000001
_3000000010
_4000000100
_5000001000
_6000010000
_7000100000
_8001000000
_10010000000
_14100000000
virtex7 IO_HR_S enum OLOGIC_TRISTATE_WIDTH
OLOGIC[0].TRISTATE_WIDTHMAIN[32][26]
_10
_41
virtex7 IO_HR_S enum OLOGIC_MISR_CLK_SELECT
OLOGIC[0].MISR_CLK_SELECTMAIN[31][58]MAIN[31][48]
NONE00
CLK101
CLK210
virtex7 IO_HR_S enum OLOGIC_CLOCK_RATIO
OLOGIC[0].CLOCK_RATIOMAIN[31][36]MAIN[31][34]MAIN[30][31]MAIN[30][35]
NONE0000
_20001
_30010
_40011
_50101
_61101
_7_81100

Bels IDELAY

virtex7 IO_HR_S bel IDELAY pins
PinDirectionIDELAY[0]
CinIMUX_CLK[1] invert by MAIN[34][24]
CINVCTRLinIMUX_BYP_SITE[6]
CEinIMUX_IMUX[32]
DATAINinIMUX_IMUX[25] invert by MAIN[35][17]
INCinIMUX_IMUX[26]
REGRSTinIMUX_IMUX[12]
LDinIMUX_IMUX[30]
LDPIPEENinIMUX_IMUX[33]
IFDLY[0]inIMUX_FAN_SITE[4]
IFDLY[1]inIMUX_FAN_SITE[5]
IFDLY[2]inIMUX_BYP_SITE[7]
CNTVALUEIN[0]inIMUX_IMUX[41]
CNTVALUEIN[1]inIMUX_IMUX[36]
CNTVALUEIN[2]inIMUX_IMUX[35]
CNTVALUEIN[3]inIMUX_IMUX[38]
CNTVALUEIN[4]inIMUX_IMUX[39]
CNTVALUEOUT[0]outOUT_BEL[20]
CNTVALUEOUT[1]outOUT_BEL[1]
CNTVALUEOUT[2]outOUT_BEL[19]
CNTVALUEOUT[3]outOUT_BEL[15]
CNTVALUEOUT[4]outOUT_BEL[11]
virtex7 IO_HR_S bel IDELAY attribute bits
AttributeIDELAY[0]
ENABLEMAIN[32][9]
IDATAIN_INVMAIN[33][8]
CINVCTRL_SELMAIN[35][25]
DELAY_SRC[enum: IDELAY_DELAY_SRC]
DELAY_TYPE[enum: IODELAY_V7_DELAY_TYPE]
HIGH_PERFORMANCE_MODEMAIN[32][45]
PIPE_SELMAIN[34][42]
IDELAY_VALUE_CUR bit 0!MAIN[34][56]
IDELAY_VALUE_CUR bit 1!MAIN[34][50]
IDELAY_VALUE_CUR bit 2!MAIN[34][44]
IDELAY_VALUE_CUR bit 3!MAIN[34][36]
IDELAY_VALUE_CUR bit 4!MAIN[34][30]
IDELAY_VALUE_INIT bit 0MAIN[34][58]
IDELAY_VALUE_INIT bit 1MAIN[34][52]
IDELAY_VALUE_INIT bit 2MAIN[34][46]
IDELAY_VALUE_INIT bit 3MAIN[34][38]
IDELAY_VALUE_INIT bit 4MAIN[34][32]
virtex7 IO_HR_S enum IDELAY_DELAY_SRC
IDELAY[0].DELAY_SRCMAIN[34][6]MAIN[35][5]MAIN[35][7]MAIN[34][8]
NONE0000
IDATAIN0001
OFB0010
DATAIN0100
DELAYCHAIN_OSC1000
virtex7 IO_HR_S enum IODELAY_V7_DELAY_TYPE
IDELAY[0].DELAY_TYPEMAIN[35][49]MAIN[35][55]
FIXED00
VARIABLE01
VAR_LOAD11

Bels IOB

virtex7 IO_HR_S bel IOB pins
PinDirectionIOB[0]
PD_INT_ENinIMUX_FAN_SITE[2]
PU_INT_ENinIMUX_FAN_SITE[1]
KEEPER_INT_ENinIMUX_FAN_SITE[3]
IBUFDISABLEinIMUX_IMUX[9]
INTERMDISABLEinIMUX_IMUX[6]
virtex7 IO_HR_S bel IOB attribute bits
AttributeIOB[0]
PULL[enum: IOB_PULL]
PULL_DYNAMICMAIN[39][27]
DQS_BIASMAIN[38][26]
IBUFDISABLE_ENMAIN[38][18]
INTERMDISABLE_ENMAIN[39][25]
LOW_VOLTAGEMAIN[39][31]
IBUF_MODE[enum: IOB_IBUF_MODE]
IBUF_VREF_HPMAIN[38][20]
INPUT_MISC bit 0MAIN[38][16]
IN_TERM[enum: IOB_IN_TERM]
IBUF_PCIMAIN[39][17]
OUTPUT_ENABLE bit 0MAIN[39][1]
OUTPUT_ENABLE bit 1MAIN[38][0]
HR_PDRIVE bit 0MAIN[39][63]
HR_PDRIVE bit 1MAIN[38][62]
HR_PDRIVE bit 2!MAIN[39][61]
HR_NDRIVE bit 0!MAIN[39][55]
HR_NDRIVE bit 1!MAIN[38][54]
HR_NDRIVE bit 2MAIN[39][53]
HR_NDRIVE bit 3MAIN[38][52]
HR_PSLEW bit 0MAIN[39][43]
HR_PSLEW bit 1!MAIN[38][42]
HR_PSLEW bit 2MAIN[39][41]
HR_NSLEW bit 0MAIN[39][47]
HR_NSLEW bit 1!MAIN[38][46]
HR_NSLEW bit 2MAIN[39][45]
HR_OUTPUT_MISC bit 0!MAIN[39][49]
HR_OUTPUT_MISC bit 1MAIN[38][48]
HR_LVDS bit 0MAIN[38][10]
HR_LVDS bit 1MAIN[39][11]
HR_LVDS bit 2MAIN[38][12]
HR_LVDS bit 3MAIN[39][13]
HR_LVDS bit 4MAIN[38][14]
HR_LVDS bit 5MAIN[39][15]
HR_LVDS bit 6MAIN[38][32]
HR_LVDS bit 7MAIN[39][33]
HR_LVDS bit 8MAIN[38][34]
HR_LVDS bit 9MAIN[39][35]
HR_LVDS bit 10MAIN[38][36]
HR_LVDS bit 11MAIN[39][37]
HR_LVDS bit 12MAIN[38][38]
virtex7 IO_HR_S enum IOB_PULL
IOB[0].PULLMAIN[38][28]MAIN[39][29]MAIN[38][30]
NONE001
PULLUP011
PULLDOWN000
KEEPER101
virtex7 IO_HR_S enum IOB_IBUF_MODE
IOB[0].IBUF_MODEMAIN[39][21]MAIN[38][22]MAIN[39][23]
NONE000
VREF001
CMOS110
CMOS_HV111
virtex7 IO_HR_S enum IOB_IN_TERM
IOB[0].IN_TERMMAIN[39][57]MAIN[38][58]MAIN[39][59]MAIN[38][56]
NONE0000
UNTUNED_SPLIT_401111
UNTUNED_SPLIT_500111
UNTUNED_SPLIT_600011

Bel wires

virtex7 IO_HR_S bel wires
WirePins
IMUX_CLK[0]ILOGIC[0].CLKDIV
IMUX_CLK[1]IDELAY[0].C
IMUX_CTRL[0]OLOGIC[0].SR
IMUX_CTRL[1]ILOGIC[0].SR
IMUX_BYP_SITE[6]IDELAY[0].CINVCTRL
IMUX_BYP_SITE[7]IDELAY[0].IFDLY[2]
IMUX_FAN_SITE[1]IOB[0].PU_INT_EN
IMUX_FAN_SITE[2]IOB[0].PD_INT_EN
IMUX_FAN_SITE[3]IOB[0].KEEPER_INT_EN
IMUX_FAN_SITE[4]IDELAY[0].IFDLY[0]
IMUX_FAN_SITE[5]IDELAY[0].IFDLY[1]
IMUX_IMUX[0]ILOGIC[0].BITSLIP
IMUX_IMUX[1]OLOGIC[0].TCE
IMUX_IMUX[4]ILOGIC[0].DYNCLKDIVSEL
IMUX_IMUX[5]ILOGIC[0].CE1
IMUX_IMUX[6]IOB[0].INTERMDISABLE
IMUX_IMUX[7]OLOGIC[0].T2
IMUX_IMUX[9]IOB[0].IBUFDISABLE
IMUX_IMUX[10]ILOGIC[0].DYNCLKDIVPSEL
IMUX_IMUX[12]IDELAY[0].REGRST
IMUX_IMUX[13]OLOGIC[0].T3
IMUX_IMUX[14]ILOGIC[0].CE2
IMUX_IMUX[15]OLOGIC[0].T1
IMUX_IMUX[21]OLOGIC[0].T4
IMUX_IMUX[25]IDELAY[0].DATAIN
IMUX_IMUX[26]IDELAY[0].INC
IMUX_IMUX[29]OLOGIC[0].OCE
IMUX_IMUX[30]IDELAY[0].LD
IMUX_IMUX[32]IDELAY[0].CE
IMUX_IMUX[33]IDELAY[0].LDPIPEEN
IMUX_IMUX[34]OLOGIC[0].D1
IMUX_IMUX[35]IDELAY[0].CNTVALUEIN[2]
IMUX_IMUX[36]IDELAY[0].CNTVALUEIN[1]
IMUX_IMUX[37]ILOGIC[0].DYNCLKSEL
IMUX_IMUX[38]IDELAY[0].CNTVALUEIN[3]
IMUX_IMUX[39]IDELAY[0].CNTVALUEIN[4]
IMUX_IMUX[40]OLOGIC[0].D2
IMUX_IMUX[41]IDELAY[0].CNTVALUEIN[0]
IMUX_IMUX[42]OLOGIC[0].D4
IMUX_IMUX[43]OLOGIC[0].D5
IMUX_IMUX[44]OLOGIC[0].D3
IMUX_IMUX[45]OLOGIC[0].D6
IMUX_IMUX[46]OLOGIC[0].D7
IMUX_IMUX[47]OLOGIC[0].D8
OUT_BEL[0]ILOGIC[0].Q1
OUT_BEL[1]IDELAY[0].CNTVALUEOUT[1]
OUT_BEL[2]OLOGIC[0].TFB
OUT_BEL[3]ILOGIC[0].Q6
OUT_BEL[5]OLOGIC[0].IOCLKGLITCH
OUT_BEL[7]ILOGIC[0].Q7
OUT_BEL[8]ILOGIC[0].Q8
OUT_BEL[9]ILOGIC[0].Q3
OUT_BEL[10]ILOGIC[0].Q4
OUT_BEL[11]IDELAY[0].CNTVALUEOUT[4]
OUT_BEL[14]ILOGIC[0].Q5
OUT_BEL[15]IDELAY[0].CNTVALUEOUT[3]
OUT_BEL[18]ILOGIC[0].O
OUT_BEL[19]IDELAY[0].CNTVALUEOUT[2]
OUT_BEL[20]IDELAY[0].CNTVALUEOUT[0]
OUT_BEL[23]ILOGIC[0].Q2
IMUX_IOI_ICLK[0]ILOGIC[0].CLK
IMUX_IOI_ICLK[1]ILOGIC[0].CLKB
IMUX_IOI_ICLKDIVPILOGIC[0].CLKDIVP
IMUX_IOI_OCLK[0]OLOGIC[0].CLK
IMUX_IOI_OCLK[1]OLOGIC[0].CLKB
IMUX_IOI_OCLKDIV[0]OLOGIC[0].CLKDIV
IMUX_IOI_OCLKDIV[1]OLOGIC[0].CLKDIVB
IMUX_IOI_OCLKDIVF[0]OLOGIC[0].CLKDIVF
IMUX_IOI_OCLKDIVF[1]OLOGIC[0].CLKDIVFB

Bitstream

virtex7 IO_HR_S rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 0 - - - - - - - - IOB[0]: HR_PDRIVE bit 0 - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 2 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 2 OLOGIC[0]: DATA_WIDTH bit 1 - - - - - - IOB[0]: HR_PDRIVE bit 1 - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 3 - OLOGIC[0]: invert D8 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 3 - - - - - - - IOB[0]: ! HR_PDRIVE bit 2 - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 1 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 1 OLOGIC[0]: DATA_WIDTH bit 2 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 0 - OLOGIC[0]: DATA_WIDTH bit 5 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 0 - - - - - - - IOB[0]: IN_TERM bit 1 - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_CLK_SELECT bit 1 - - IDELAY[0]: IDELAY_VALUE_INIT bit 0 - - - IOB[0]: IN_TERM bit 2 - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 4 - OLOGIC[0]: DATA_WIDTH bit 3 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 4 - - - - - - - IOB[0]: IN_TERM bit 3 - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 4 - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 0 - - - IOB[0]: IN_TERM bit 0 - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 6 - OLOGIC[0]: MISR_RESET SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 6 - - - IDELAY[0]: DELAY_TYPE bit 0 - - - IOB[0]: ! HR_NDRIVE bit 0 - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 5 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 5 OLOGIC[0]: invert D7 - - - - - - IOB[0]: ! HR_NDRIVE bit 1 - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_ENABLE_FDBK - - - - - - - - IOB[0]: HR_NDRIVE bit 2 - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 6 - - IDELAY[0]: IDELAY_VALUE_INIT bit 1 - - - IOB[0]: HR_NDRIVE bit 3 - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 7 - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D6 - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 1 - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D5 - - OLOGIC[0]: V5_MUX_O bit 3 - IDELAY[0]: DELAY_TYPE bit 1 - - - IOB[0]: ! HR_OUTPUT_MISC bit 0 - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_CLK_SELECT bit 0 OLOGIC[0]: FFO_SR_ENABLE - - - - - IOB[0]: HR_OUTPUT_MISC bit 1 - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIV[0] bit 1 - OLOGIC[0]: MISR_ENABLE SPEC_INT: mux IMUX_IOI_OCLKDIV[1] bit 1 - OLOGIC[0]: V5_MUX_O bit 0 - - - - - IOB[0]: HR_NSLEW bit 0 - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIV[0] bit 0 SPEC_INT: mux IMUX_IOI_OCLKDIV[1] bit 0 OLOGIC[0]: invert D4 OLOGIC[0]: V5_MUX_O bit 4 - IDELAY[0]: IDELAY_VALUE_INIT bit 2 - - - IOB[0]: ! HR_NSLEW bit 1 - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[0]: HIGH_PERFORMANCE_MODE - - - - - - IOB[0]: HR_NSLEW bit 2 - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFO_SRVAL bit 2 - IDELAY[0]: ! IDELAY_VALUE_CUR bit 2 - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFO_SRVAL bit 1 - - - - - IOB[0]: HR_PSLEW bit 0 - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D3 - - IDELAY[0]: PIPE_SEL - - - IOB[0]: ! HR_PSLEW bit 1 - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: HR_PSLEW bit 2 - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D2 - - IDELAY[0]: IDELAY_VALUE_INIT bit 3 - - - IOB[0]: HR_LVDS bit 12 - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 8 - - - - - - - - IOB[0]: HR_LVDS bit 11 - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: CLOCK_RATIO bit 3 - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 3 - - - IOB[0]: HR_LVDS bit 10 - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLKDIVP bit 1 - OLOGIC[0]: CLOCK_RATIO bit 0 - - - - - - - - IOB[0]: HR_LVDS bit 9 - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLKDIVP bit 0 - OLOGIC[0]: CLOCK_RATIO bit 2 - - - - - - IOB[0]: HR_LVDS bit 8 - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 7 - OLOGIC[0]: invert D1 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 7 - OLOGIC[0]: ! FFO_INIT bit 0 - - - - - IOB[0]: HR_LVDS bit 7 - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 8 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 8 OLOGIC[0]: SELFHEAL - - IDELAY[0]: IDELAY_VALUE_INIT bit 4 - - - IOB[0]: HR_LVDS bit 6 - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 6 - OLOGIC[0]: CLOCK_RATIO bit 1 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 6 - OLOGIC[0]: ! FFO_SRVAL bit 0 - - - - - IOB[0]: LOW_VOLTAGE - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 3 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 3 OLOGIC[0]: invert CLKDIVF OLOGIC[0]: FFO_SR_SYNC - IDELAY[0]: ! IDELAY_VALUE_CUR bit 4 - - - IOB[0]: PULL bit 0 - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 4 - - SPEC_INT: mux IMUX_IOI_OCLK[1] bit 4 - OLOGIC[0]: V5_MUX_O bit 1 - - - - - IOB[0]: PULL bit 1 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 10 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 10 OLOGIC[0]: ! CLK2_INV - - - - - - IOB[0]: PULL bit 2 - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_O bit 2 - - - - - IOB[0]: PULL_DYNAMIC - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! CLK1_INV OLOGIC[0]: TRISTATE_WIDTH bit 0 - - - - - IOB[0]: DQS_BIAS - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 9 - - SPEC_INT: mux IMUX_IOI_OCLK[1] bit 9 - OLOGIC[0]: FFT_SR_ENABLE - IDELAY[0]: CINVCTRL_SEL - - - IOB[0]: INTERMDISABLE_EN - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 5 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 5 - - - IDELAY[0]: invert C - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: IBUF_MODE bit 0 - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! RANK3_USED - - - - - - IOB[0]: IBUF_MODE bit 1 - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert CLKDIV - - - - - - - - IOB[0]: IBUF_MODE bit 2 - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 2 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 2 - OLOGIC[0]: TBYTE_SRC - - - - - IOB[0]: IBUF_VREF_HP - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 0 - - SPEC_INT: mux IMUX_IOI_OCLK[1] bit 0 - OLOGIC[0]: SERDES_MODE bit 0 - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 1 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 1 - OLOGIC[0]: ! FFT_SRVAL bit 2 - - - - - IOB[0]: IBUFDISABLE_EN - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 8 - - SPEC_INT: mux IMUX_IOI_ICLK[1] bit 8 - OLOGIC[0]: ! FFT_SRVAL bit 1 - IDELAY[0]: invert DATAIN - - - IOB[0]: IBUF_PCI - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 4 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 4 - OLOGIC[0]: TBYTE_CTL - - - - - IOB[0]: INPUT_MISC bit 0 - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 7 - OLOGIC[0]: !invert T4 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 7 - - - - - - - IOB[0]: HR_LVDS bit 5 - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 5 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 5 - - - - - - - IOB[0]: HR_LVDS bit 4 - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 3 - - SPEC_INT: mux IMUX_IOI_ICLK[1] bit 3 - - - - - - - IOB[0]: HR_LVDS bit 3 - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 10 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 10 OLOGIC[0]: !invert T3 - - - - - - IOB[0]: HR_LVDS bit 2 - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 9 - OLOGIC[0]: ! FFT_INIT bit 0 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 9 - OLOGIC[0]: ! FFT_SRVAL bit 0 - - - - - IOB[0]: HR_LVDS bit 1 - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 6 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 6 - - - - - - - IOB[0]: HR_LVDS bit 0 - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[0]: ENABLE OLOGIC[0]: SERDES - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFT_SR_SYNC IDELAY[0]: IDATAIN_INV IDELAY[0]: DELAY_SRC bit 0 - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: !invert T2 - - - - IDELAY[0]: DELAY_SRC bit 1 - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_T bit 2 - IDELAY[0]: DELAY_SRC bit 3 - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_T bit 1 - IDELAY[0]: DELAY_SRC bit 2 - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_T bit 3 - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 0 - OLOGIC[0]: !invert T1 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 0 - OLOGIC[0]: V5_MUX_T bit 4 - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 1 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 1 - OLOGIC[0]: V5_MUX_T bit 0 - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 2 - - SPEC_INT: mux IMUX_IOI_ICLK[1] bit 2 - - - - - - - IOB[0]: OUTPUT_ENABLE bit 0 - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: OUTPUT_ENABLE bit 1 - - -
### Bitstream
virtex7 IO_HR_S rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLK_INV_EN
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[0] -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[2]
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.OCLK2 -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[1]
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[0] - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.ZHOLD_IFF -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.CLKDIV - - ILOGIC[0]:IFF_ZHOLD
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLKDIV_INV_EN ILOGIC[0]:IFFDELAY_VALUE[0] -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[2] - - ILOGIC[0]:IDELAY_VALUE[0]
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLKDIVP_INV_EN ILOGIC[0]:IFF_DELAY_ENABLE -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[4] - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.CLKDIVP - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[3] - - ILOGIC[0]:IFF_TSBYPASS_ENABLE
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[0] ILOGIC[0]:IFFDELAY_VALUE[1] -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[1] - - ILOGIC[0]:IDELAY_VALUE[1]
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[2] ILOGIC[0]:TSBYPASS_MUX[0] -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[3] - - ~ILOGIC[0]:INV.D
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_RATE[0] - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:BITSLIP_ENABLE - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SERDES_MODE[0] - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IFFDELAY_VALUE[2]
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IDELAY_VALUE[2] -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:I_TSBYPASS_ENABLE
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SERDES ILOGIC[0]:ZHOLD_ENABLE -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[1] - - ILOGIC[0]:I_DELAY_ENABLE
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:RANK23_DLY - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DDR_CLK_EDGE[1] - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DDR_CLK_EDGE[0] - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:I_ZHOLD
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.ZHOLD_FABRIC -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF4_INIT -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF4_SRVAL
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IFFDELAY_VALUE[3] -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IDELAY_VALUE[3]
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF3_INIT -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF3_SRVAL
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IFFDELAY_VALUE[4] -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IDELAY_VALUE[4]
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:NUM_CE[0] - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF2_INIT -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF2_SRVAL
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF1_INIT -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF_LATCH - - ~ILOGIC[0]:IFF1_SRVAL
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IFF_SR_USED - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SRTYPE[0]
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:D_EMU2 -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:D_EMU1
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.OCLK1 -
ILOGIC[0]:BITSLIP_ENABLE 0.F26.B43
ILOGIC[0]:DYN_CLKDIVP_INV_EN 0.F27.B52
ILOGIC[0]:DYN_CLKDIV_INV_EN 0.F27.B54
ILOGIC[0]:DYN_CLK_INV_EN 0.F29.B63
ILOGIC[0]:D_EMU1 0.F29.B1
ILOGIC[0]:D_EMU2 0.F28.B2
ILOGIC[0]:IFF_DELAY_ENABLE 0.F28.B52
ILOGIC[0]:IFF_SR_USED 0.F27.B6
ILOGIC[0]:IFF_TSBYPASS_ENABLE 0.F29.B49
ILOGIC[0]:IFF_ZHOLD 0.F29.B55
ILOGIC[0]:INV.CLKDIV 0.F26.B55
ILOGIC[0]:INV.CLKDIVP 0.F27.B50
ILOGIC[0]:INV.OCLK1 0.F28.B0
ILOGIC[0]:INV.OCLK2 0.F28.B60
ILOGIC[0]:INV.ZHOLD_FABRIC 0.F28.B32
ILOGIC[0]:INV.ZHOLD_IFF 0.F28.B56
ILOGIC[0]:I_DELAY_ENABLE 0.F29.B37
ILOGIC[0]:I_TSBYPASS_ENABLE 0.F29.B39
ILOGIC[0]:I_ZHOLD 0.F29.B33
ILOGIC[0]:RANK23_DLY 0.F27.B36
ILOGIC[0]:SERDES 0.F27.B38
ILOGIC[0]:ZHOLD_ENABLE 0.F28.B38
non-inverted [0]
ILOGIC[0]:DATA_RATE 0.F27.B44
DDR 0
SDR 1
ILOGIC[0]:DATA_WIDTH 0.F26.B45 0.F27.B46 0.F26.B47 0.F27.B48
NONE 0 0 0 0
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
10 1 0 1 0
14 1 1 1 0
ILOGIC[0]:DDR_CLK_EDGE 0.F26.B35 0.F27.B34
SAME_EDGE_PIPELINED 0 0
OPPOSITE_EDGE 0 1
SAME_EDGE 1 0
ILOGIC[0]:IDELAY_VALUE 0.F29.B17 0.F29.B25 0.F28.B40 0.F29.B47 0.F29.B53
ILOGIC[0]:IFFDELAY_VALUE 0.F28.B18 0.F28.B26 0.F29.B41 0.F28.B48 0.F28.B54
non-inverted [4] [3] [2] [1] [0]
ILOGIC[0]:IFF1_INIT 0.F28.B8
ILOGIC[0]:IFF1_SRVAL 0.F29.B7
ILOGIC[0]:IFF2_INIT 0.F28.B12
ILOGIC[0]:IFF2_SRVAL 0.F29.B11
ILOGIC[0]:IFF3_INIT 0.F28.B22
ILOGIC[0]:IFF3_SRVAL 0.F29.B21
ILOGIC[0]:IFF4_INIT 0.F28.B30
ILOGIC[0]:IFF4_SRVAL 0.F29.B29
ILOGIC[0]:IFF_LATCH 0.F26.B7
ILOGIC[0]:INV.D 0.F29.B45
inverted ~[0]
ILOGIC[0]:INTERFACE_TYPE 0.F26.B51 0.F26.B49 0.F26.B53 0.F26.B37 0.F26.B57
MEMORY 0 0 0 0 0
NETWORKING 0 0 0 0 1
MEMORY_DDR3 0 0 1 1 1
MEMORY_DDR3_V6 0 1 0 1 1
OVERSAMPLE 1 0 0 1 1
ILOGIC[0]:INV.CLK 0.F29.B61 0.F29.B59 0.F28.B62
inverted ~[2] ~[1] ~[0]
ILOGIC[0]:NUM_CE 0.F27.B16
1 0
2 1
ILOGIC[0]:SERDES_MODE 0.F27.B42
MASTER 0
SLAVE 1
ILOGIC[0]:SRTYPE 0.F29.B3
ASYNC 0
SYNC 1
ILOGIC[0]:TSBYPASS_MUX 0.F28.B46
T 0
GND 1

Tile IO_HR_N

Cells: 1

Switchbox SPEC_INT

virtex7 IO_HR_N switchbox SPEC_INT permanent buffers
DestinationSource
IMUX_SPEC[0]IMUX_IOI_OCLKDIV[0]
IMUX_SPEC[2]IMUX_IOI_OCLK[0]
virtex7 IO_HR_N switchbox SPEC_INT muxes IMUX_IOI_ICLK[0]
BitsDestination
MAIN[28][51]MAIN[29][52]MAIN[29][46]MAIN[29][48]MAIN[28][53]MAIN[28][49]MAIN[28][47]MAIN[29][50]MAIN[29][62]MAIN[28][61]MAIN[29][60]IMUX_IOI_ICLK[0]
Source
00000000000off
00000000010PHASER_ICLK
00000000100PHASER_OCLK
00000011001IMUX_IMUX[20]
00000101001IMUX_IMUX[22]
00001010001LCLK_IO[3]
00001100001LCLK_IO[2]
00010001001IOCLK[2]
00011000001LCLK_IO[0]
00100001001IOCLK[3]
00101000001LCLK_IO[1]
01000010001RCLK_IO[1]
01000100001RCLK_IO[0]
01010000001LCLK_IO[4]
01100000001LCLK_IO[5]
10000010001IOCLK[1]
10000100001IOCLK[0]
10010000001RCLK_IO[2]
10100000001RCLK_IO[3]
virtex7 IO_HR_N switchbox SPEC_INT muxes IMUX_IOI_ICLK[1]
BitsDestination
MAIN[31][51]MAIN[30][52]MAIN[30][46]MAIN[30][48]MAIN[31][53]MAIN[31][49]MAIN[31][47]MAIN[30][50]MAIN[30][62]MAIN[31][61]MAIN[30][60]IMUX_IOI_ICLK[1]
Source
00000000000off
00000000010PHASER_ICLK
00000000100PHASER_OCLK
00000011001IMUX_IMUX[20]
00000101001IMUX_IMUX[22]
00001010001LCLK_IO[3]
00001100001LCLK_IO[2]
00010001001IOCLK[2]
00011000001LCLK_IO[0]
00100001001IOCLK[3]
00101000001LCLK_IO[1]
01000010001RCLK_IO[1]
01000100001RCLK_IO[0]
01010000001LCLK_IO[4]
01100000001LCLK_IO[5]
10000010001IOCLK[1]
10000100001IOCLK[0]
10010000001RCLK_IO[2]
10100000001RCLK_IO[3]
virtex7 IO_HR_N switchbox SPEC_INT muxes IMUX_IOI_ICLKDIVP
BitsDestination
MAIN[29][28]MAIN[28][29]IMUX_IOI_ICLKDIVP
Source
00off
01IMUX_CLK[0]
10PHASER_ICLKDIV
virtex7 IO_HR_N switchbox SPEC_INT muxes IMUX_IOI_OCLK[0]
BitsDestination
MAIN[28][35]MAIN[29][38]MAIN[28][31]MAIN[29][30]MAIN[29][32]MAIN[28][39]MAIN[29][34]MAIN[28][33]MAIN[28][43]MAIN[28][45]MAIN[29][44]IMUX_IOI_OCLK[0]
Source
00000000000off
00000000010PHASER_OCLK
00000000100PHASER_OCLK90
00000011001IMUX_IMUX[31]
00000101001LCLK_IO[2]
00001010001IOCLK[2]
00001100001LCLK_IO[0]
00010010001IOCLK[3]
00010100001LCLK_IO[1]
00100100001LCLK_IO[3]
01000001001RCLK_IO[0]
01001000001LCLK_IO[4]
01010000001LCLK_IO[5]
01100000001RCLK_IO[1]
10000001001IOCLK[0]
10001000001RCLK_IO[2]
10010000001RCLK_IO[3]
10100000001IOCLK[1]
virtex7 IO_HR_N switchbox SPEC_INT muxes IMUX_IOI_OCLK[1]
BitsDestination
MAIN[31][35]MAIN[30][38]MAIN[31][31]MAIN[30][30]MAIN[30][32]MAIN[31][39]MAIN[30][34]MAIN[31][33]MAIN[31][43]MAIN[31][45]MAIN[30][44]IMUX_IOI_OCLK[1]
Source
00000000000off
00000000010PHASER_OCLK
00000000100PHASER_OCLK90
00000011001IMUX_IMUX[31]
00000101001LCLK_IO[2]
00001010001IOCLK[2]
00001100001LCLK_IO[0]
00010010001IOCLK[3]
00010100001LCLK_IO[1]
00100100001LCLK_IO[3]
01000001001RCLK_IO[0]
01001000001LCLK_IO[4]
01010000001LCLK_IO[5]
01100000001RCLK_IO[1]
10000001001IOCLK[0]
10001000001RCLK_IO[2]
10010000001RCLK_IO[3]
10100000001IOCLK[1]
virtex7 IO_HR_N switchbox SPEC_INT muxes IMUX_IOI_OCLKDIV[0]
BitsDestination
MAIN[29][16]MAIN[28][17]IMUX_IOI_OCLKDIV[0]
Source
00off
01PHASER_OCLKDIV
10IMUX_IOI_OCLKDIVF[0]
virtex7 IO_HR_N switchbox SPEC_INT muxes IMUX_IOI_OCLKDIV[1]
BitsDestination
MAIN[30][16]MAIN[31][17]IMUX_IOI_OCLKDIV[1]
Source
00off
01PHASER_OCLKDIV
10IMUX_IOI_OCLKDIVF[1]
virtex7 IO_HR_N switchbox SPEC_INT muxes IMUX_IOI_OCLKDIVF[0]
BitsDestination
MAIN[29][8]MAIN[28][9]MAIN[29][6]MAIN[29][2]MAIN[28][1]MAIN[28][3]MAIN[29][4]IMUX_IOI_OCLKDIVF[0]
Source
0000000off
0010001IMUX_IMUX[8]
0010010RCLK_IO[2]
0010100RCLK_IO[3]
0100001LCLK_IO[2]
0100010LCLK_IO[0]
0100100LCLK_IO[1]
0101000LCLK_IO[3]
1000001RCLK_IO[0]
1000010LCLK_IO[4]
1000100LCLK_IO[5]
1001000RCLK_IO[1]
virtex7 IO_HR_N switchbox SPEC_INT muxes IMUX_IOI_OCLKDIVF[1]
BitsDestination
MAIN[30][8]MAIN[31][9]MAIN[30][6]MAIN[30][2]MAIN[31][1]MAIN[31][3]MAIN[30][4]IMUX_IOI_OCLKDIVF[1]
Source
0000000off
0010001IMUX_IMUX[8]
0010010RCLK_IO[2]
0010100RCLK_IO[3]
0100001LCLK_IO[2]
0100010LCLK_IO[0]
0100100LCLK_IO[1]
0101000LCLK_IO[3]
1000001RCLK_IO[0]
1000010LCLK_IO[4]
1000100LCLK_IO[5]
1001000RCLK_IO[1]

Bels ILOGIC

virtex7 IO_HR_N bel ILOGIC pins
PinDirectionILOGIC[0]
CLKinIMUX_IOI_ICLK[0]
CLKBinIMUX_IOI_ICLK[1]
CLKDIVinIMUX_CLK[0]
CLKDIVPinIMUX_IOI_ICLKDIVP
SRinIMUX_CTRL[1]
CE1inIMUX_IMUX[5]
CE2inIMUX_IMUX[14]
BITSLIPinIMUX_IMUX[0]
DYNCLKSELinIMUX_IMUX[37]
DYNCLKDIVSELinIMUX_IMUX[4]
DYNCLKDIVPSELinIMUX_IMUX[10]
OoutOUT_BEL[18]
Q1outOUT_BEL[0]
Q2outOUT_BEL[23]
Q3outOUT_BEL[9]
Q4outOUT_BEL[10]
Q5outOUT_BEL[14]
Q6outOUT_BEL[3]
Q7outOUT_BEL[7]
Q8outOUT_BEL[8]
virtex7 IO_HR_N bel ILOGIC attribute bits
AttributeILOGIC[0]

Bels OLOGIC

virtex7 IO_HR_N bel OLOGIC pins
PinDirectionOLOGIC[0]
CLKinIMUX_IOI_OCLK[0]
CLKBinIMUX_IOI_OCLK[1]
CLKDIVinIMUX_IOI_OCLKDIV[0] invert by MAIN[31][42]
CLKDIVBinIMUX_IOI_OCLKDIV[1]
CLKDIVFinIMUX_IOI_OCLKDIVF[0] invert by MAIN[30][33]
CLKDIVFBinIMUX_IOI_OCLKDIVF[1]
SRinIMUX_CTRL[0]
OCEinIMUX_IMUX[29]
TCEinIMUX_IMUX[1]
D1inIMUX_IMUX[34] invert by MAIN[31][30]
D2inIMUX_IMUX[40] invert by MAIN[30][25]
D3inIMUX_IMUX[44] invert by MAIN[30][21]
D4inIMUX_IMUX[42] invert by MAIN[30][17]
D5inIMUX_IMUX[43] invert by MAIN[31][14]
D6inIMUX_IMUX[45] invert by MAIN[30][13]
D7inIMUX_IMUX[46] invert by MAIN[30][9]
D8inIMUX_IMUX[47] invert by MAIN[31][2]
T1inIMUX_IMUX[15] invert by !MAIN[31][60]
T2inIMUX_IMUX[7] invert by !MAIN[31][56]
T3inIMUX_IMUX[13] invert by !MAIN[30][51]
T4inIMUX_IMUX[21] invert by !MAIN[31][48]
TFBoutOUT_BEL[2]
IOCLKGLITCHoutOUT_BEL[5]
virtex7 IO_HR_N bel OLOGIC attribute bits
AttributeOLOGIC[0]
CLK1_INV!MAIN[30][37]
CLK2_INV!MAIN[30][35]
FFO_INIT bit 0!MAIN[32][30]
FFO_SRVAL bit 0!MAIN[32][32]
FFO_SRVAL bit 1!MAIN[32][20]
FFO_SRVAL bit 2!MAIN[33][19]
FFO_SR_SYNCMAIN[33][33]
FFO_SR_ENABLEMAIN[33][15]
V5_MUX_O[enum: OLOGIC_V5_MUX_O]
FFT_INIT bit 0!MAIN[31][52]
FFT_SRVAL bit 0!MAIN[32][52]
FFT_SRVAL bit 1!MAIN[32][46]
FFT_SRVAL bit 2!MAIN[33][45]
FFT_SR_SYNCMAIN[33][55]
FFT_SR_ENABLEMAIN[32][38]
V5_MUX_T[enum: OLOGIC_V5_MUX_T]
SERDESMAIN[32][54]
SERDES_MODE[enum: IO_SERDES_MODE]
DATA_WIDTH[enum: IO_DATA_WIDTH]
TRISTATE_WIDTH[enum: OLOGIC_TRISTATE_WIDTH]
MISR_ENABLEMAIN[31][16]
MISR_ENABLE_FDBKMAIN[31][10]
MISR_RESETMAIN[31][8]
MISR_CLK_SELECT[enum: OLOGIC_MISR_CLK_SELECT]
CLOCK_RATIO[enum: OLOGIC_CLOCK_RATIO]
SELFHEALMAIN[30][31]
RANK3_USED!MAIN[30][41]
TBYTE_CTLMAIN[33][47]
TBYTE_SRCMAIN[33][43]
virtex7 IO_HR_N enum OLOGIC_V5_MUX_O
OLOGIC[0].V5_MUX_OMAIN[33][17]MAIN[32][14]MAIN[32][36]MAIN[32][34]MAIN[32][16]
NONE00000
D100001
SERDES_SDR00010
LATCH10010
FF01010
DDR00100
virtex7 IO_HR_N enum OLOGIC_V5_MUX_T
OLOGIC[0].V5_MUX_TMAIN[32][60]MAIN[33][59]MAIN[33][57]MAIN[32][58]MAIN[33][61]
NONE00000
T100001
SERDES_SDR00010
LATCH10010
FF01010
DDR00100
virtex7 IO_HR_N enum IO_SERDES_MODE
OLOGIC[0].SERDES_MODEMAIN[32][44]
MASTER0
SLAVE1
virtex7 IO_HR_N enum IO_DATA_WIDTH
OLOGIC[0].DATA_WIDTHMAIN[31][26]MAIN[31][12]MAIN[30][11]MAIN[31][4]MAIN[30][7]MAIN[31][6]MAIN[30][3]MAIN[30][1]MAIN[31][0]
NONE000000000
_2000000001
_3000000010
_4000000100
_5000001000
_6000010000
_7000100000
_8001000000
_10010000000
_14100000000
virtex7 IO_HR_N enum OLOGIC_TRISTATE_WIDTH
OLOGIC[0].TRISTATE_WIDTHMAIN[33][37]
_10
_41
virtex7 IO_HR_N enum OLOGIC_MISR_CLK_SELECT
OLOGIC[0].MISR_CLK_SELECTMAIN[30][5]MAIN[30][15]
NONE00
CLK101
CLK210
virtex7 IO_HR_N enum OLOGIC_CLOCK_RATIO
OLOGIC[0].CLOCK_RATIOMAIN[30][27]MAIN[30][29]MAIN[31][32]MAIN[31][28]
NONE0000
_20001
_30010
_40011
_50101
_61101
_7_81100

Bels IDELAY

virtex7 IO_HR_N bel IDELAY pins
PinDirectionIDELAY[0]
CinIMUX_CLK[1] invert by MAIN[35][39]
CINVCTRLinIMUX_BYP_SITE[6]
CEinIMUX_IMUX[32]
DATAINinIMUX_IMUX[25] invert by MAIN[34][46]
INCinIMUX_IMUX[26]
REGRSTinIMUX_IMUX[12]
LDinIMUX_IMUX[30]
LDPIPEENinIMUX_IMUX[33]
IFDLY[0]inIMUX_FAN_SITE[4]
IFDLY[1]inIMUX_FAN_SITE[5]
IFDLY[2]inIMUX_BYP_SITE[7]
CNTVALUEIN[0]inIMUX_IMUX[41]
CNTVALUEIN[1]inIMUX_IMUX[36]
CNTVALUEIN[2]inIMUX_IMUX[35]
CNTVALUEIN[3]inIMUX_IMUX[38]
CNTVALUEIN[4]inIMUX_IMUX[39]
CNTVALUEOUT[0]outOUT_BEL[20]
CNTVALUEOUT[1]outOUT_BEL[1]
CNTVALUEOUT[2]outOUT_BEL[19]
CNTVALUEOUT[3]outOUT_BEL[15]
CNTVALUEOUT[4]outOUT_BEL[11]
virtex7 IO_HR_N bel IDELAY attribute bits
AttributeIDELAY[0]
ENABLEMAIN[33][54]
IDATAIN_INVMAIN[32][55]
CINVCTRL_SELMAIN[34][38]
DELAY_SRC[enum: IDELAY_DELAY_SRC]
DELAY_TYPE[enum: IODELAY_V7_DELAY_TYPE]
HIGH_PERFORMANCE_MODEMAIN[33][18]
PIPE_SELMAIN[35][21]
IDELAY_VALUE_CUR bit 0!MAIN[35][7]
IDELAY_VALUE_CUR bit 1!MAIN[35][13]
IDELAY_VALUE_CUR bit 2!MAIN[35][19]
IDELAY_VALUE_CUR bit 3!MAIN[35][27]
IDELAY_VALUE_CUR bit 4!MAIN[35][33]
IDELAY_VALUE_INIT bit 0MAIN[35][5]
IDELAY_VALUE_INIT bit 1MAIN[35][11]
IDELAY_VALUE_INIT bit 2MAIN[35][17]
IDELAY_VALUE_INIT bit 3MAIN[35][25]
IDELAY_VALUE_INIT bit 4MAIN[35][31]
virtex7 IO_HR_N enum IDELAY_DELAY_SRC
IDELAY[0].DELAY_SRCMAIN[35][57]MAIN[34][58]MAIN[34][56]MAIN[35][55]
NONE0000
IDATAIN0001
OFB0010
DATAIN0100
DELAYCHAIN_OSC1000
virtex7 IO_HR_N enum IODELAY_V7_DELAY_TYPE
IDELAY[0].DELAY_TYPEMAIN[34][14]MAIN[34][8]
FIXED00
VARIABLE01
VAR_LOAD11

Bels IOB

virtex7 IO_HR_N bel IOB pins
PinDirectionIOB[0]
PD_INT_ENinIMUX_FAN_SITE[2]
PU_INT_ENinIMUX_FAN_SITE[1]
KEEPER_INT_ENinIMUX_FAN_SITE[3]
IBUFDISABLEinIMUX_IMUX[9]
INTERMDISABLEinIMUX_IMUX[6]
virtex7 IO_HR_N bel IOB attribute bits
AttributeIOB[0]
PULL[enum: IOB_PULL]
PULL_DYNAMICMAIN[38][36]
DQS_BIASMAIN[39][37]
IBUFDISABLE_ENMAIN[39][45]
INTERMDISABLE_ENMAIN[38][38]
LOW_VOLTAGEMAIN[38][32]
IBUF_MODE[enum: IOB_IBUF_MODE]
IBUF_VREF_HPMAIN[39][43]
INPUT_MISC bit 0MAIN[39][47]
IN_TERM[enum: IOB_IN_TERM]
IBUF_PCIMAIN[38][46]
OUTPUT_ENABLE bit 0MAIN[38][62]
OUTPUT_ENABLE bit 1MAIN[39][63]
HR_PDRIVE bit 0MAIN[38][0]
HR_PDRIVE bit 1MAIN[39][1]
HR_PDRIVE bit 2!MAIN[38][2]
HR_NDRIVE bit 0!MAIN[38][8]
HR_NDRIVE bit 1!MAIN[39][9]
HR_NDRIVE bit 2MAIN[38][10]
HR_NDRIVE bit 3MAIN[39][11]
HR_PSLEW bit 0MAIN[38][20]
HR_PSLEW bit 1!MAIN[39][21]
HR_PSLEW bit 2MAIN[38][22]
HR_NSLEW bit 0MAIN[38][16]
HR_NSLEW bit 1!MAIN[39][17]
HR_NSLEW bit 2MAIN[38][18]
HR_OUTPUT_MISC bit 0!MAIN[38][14]
HR_OUTPUT_MISC bit 1MAIN[39][15]
HR_LVDS bit 0MAIN[39][53]
HR_LVDS bit 1MAIN[38][52]
HR_LVDS bit 2MAIN[39][51]
HR_LVDS bit 3MAIN[38][50]
HR_LVDS bit 4MAIN[39][49]
HR_LVDS bit 5MAIN[38][48]
HR_LVDS bit 6MAIN[39][31]
HR_LVDS bit 7MAIN[38][30]
HR_LVDS bit 8MAIN[39][29]
HR_LVDS bit 9MAIN[38][28]
HR_LVDS bit 10MAIN[39][27]
HR_LVDS bit 11MAIN[38][26]
HR_LVDS bit 12MAIN[39][25]
virtex7 IO_HR_N enum IOB_PULL
IOB[0].PULLMAIN[39][35]MAIN[38][34]MAIN[39][33]
NONE001
PULLUP011
PULLDOWN000
KEEPER101
virtex7 IO_HR_N enum IOB_IBUF_MODE
IOB[0].IBUF_MODEMAIN[39][41]MAIN[38][42]MAIN[38][40]
NONE000
VREF001
CMOS110
CMOS_HV111
virtex7 IO_HR_N enum IOB_IN_TERM
IOB[0].IN_TERMMAIN[38][6]MAIN[39][5]MAIN[39][7]MAIN[38][4]
NONE0000
UNTUNED_SPLIT_401111
UNTUNED_SPLIT_500111
UNTUNED_SPLIT_600011

Bel wires

virtex7 IO_HR_N bel wires
WirePins
IMUX_CLK[0]ILOGIC[0].CLKDIV
IMUX_CLK[1]IDELAY[0].C
IMUX_CTRL[0]OLOGIC[0].SR
IMUX_CTRL[1]ILOGIC[0].SR
IMUX_BYP_SITE[6]IDELAY[0].CINVCTRL
IMUX_BYP_SITE[7]IDELAY[0].IFDLY[2]
IMUX_FAN_SITE[1]IOB[0].PU_INT_EN
IMUX_FAN_SITE[2]IOB[0].PD_INT_EN
IMUX_FAN_SITE[3]IOB[0].KEEPER_INT_EN
IMUX_FAN_SITE[4]IDELAY[0].IFDLY[0]
IMUX_FAN_SITE[5]IDELAY[0].IFDLY[1]
IMUX_IMUX[0]ILOGIC[0].BITSLIP
IMUX_IMUX[1]OLOGIC[0].TCE
IMUX_IMUX[4]ILOGIC[0].DYNCLKDIVSEL
IMUX_IMUX[5]ILOGIC[0].CE1
IMUX_IMUX[6]IOB[0].INTERMDISABLE
IMUX_IMUX[7]OLOGIC[0].T2
IMUX_IMUX[9]IOB[0].IBUFDISABLE
IMUX_IMUX[10]ILOGIC[0].DYNCLKDIVPSEL
IMUX_IMUX[12]IDELAY[0].REGRST
IMUX_IMUX[13]OLOGIC[0].T3
IMUX_IMUX[14]ILOGIC[0].CE2
IMUX_IMUX[15]OLOGIC[0].T1
IMUX_IMUX[21]OLOGIC[0].T4
IMUX_IMUX[25]IDELAY[0].DATAIN
IMUX_IMUX[26]IDELAY[0].INC
IMUX_IMUX[29]OLOGIC[0].OCE
IMUX_IMUX[30]IDELAY[0].LD
IMUX_IMUX[32]IDELAY[0].CE
IMUX_IMUX[33]IDELAY[0].LDPIPEEN
IMUX_IMUX[34]OLOGIC[0].D1
IMUX_IMUX[35]IDELAY[0].CNTVALUEIN[2]
IMUX_IMUX[36]IDELAY[0].CNTVALUEIN[1]
IMUX_IMUX[37]ILOGIC[0].DYNCLKSEL
IMUX_IMUX[38]IDELAY[0].CNTVALUEIN[3]
IMUX_IMUX[39]IDELAY[0].CNTVALUEIN[4]
IMUX_IMUX[40]OLOGIC[0].D2
IMUX_IMUX[41]IDELAY[0].CNTVALUEIN[0]
IMUX_IMUX[42]OLOGIC[0].D4
IMUX_IMUX[43]OLOGIC[0].D5
IMUX_IMUX[44]OLOGIC[0].D3
IMUX_IMUX[45]OLOGIC[0].D6
IMUX_IMUX[46]OLOGIC[0].D7
IMUX_IMUX[47]OLOGIC[0].D8
OUT_BEL[0]ILOGIC[0].Q1
OUT_BEL[1]IDELAY[0].CNTVALUEOUT[1]
OUT_BEL[2]OLOGIC[0].TFB
OUT_BEL[3]ILOGIC[0].Q6
OUT_BEL[5]OLOGIC[0].IOCLKGLITCH
OUT_BEL[7]ILOGIC[0].Q7
OUT_BEL[8]ILOGIC[0].Q8
OUT_BEL[9]ILOGIC[0].Q3
OUT_BEL[10]ILOGIC[0].Q4
OUT_BEL[11]IDELAY[0].CNTVALUEOUT[4]
OUT_BEL[14]ILOGIC[0].Q5
OUT_BEL[15]IDELAY[0].CNTVALUEOUT[3]
OUT_BEL[18]ILOGIC[0].O
OUT_BEL[19]IDELAY[0].CNTVALUEOUT[2]
OUT_BEL[20]IDELAY[0].CNTVALUEOUT[0]
OUT_BEL[23]ILOGIC[0].Q2
IMUX_IOI_ICLK[0]ILOGIC[0].CLK
IMUX_IOI_ICLK[1]ILOGIC[0].CLKB
IMUX_IOI_ICLKDIVPILOGIC[0].CLKDIVP
IMUX_IOI_OCLK[0]OLOGIC[0].CLK
IMUX_IOI_OCLK[1]OLOGIC[0].CLKB
IMUX_IOI_OCLKDIV[0]OLOGIC[0].CLKDIV
IMUX_IOI_OCLKDIV[1]OLOGIC[0].CLKDIVB
IMUX_IOI_OCLKDIVF[0]OLOGIC[0].CLKDIVF
IMUX_IOI_OCLKDIVF[1]OLOGIC[0].CLKDIVFB

Bitstream

virtex7 IO_HR_N rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: OUTPUT_ENABLE bit 1 - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 2 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 2 - - - - - - - IOB[0]: OUTPUT_ENABLE bit 0 - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 1 - - SPEC_INT: mux IMUX_IOI_ICLK[1] bit 1 - OLOGIC[0]: V5_MUX_T bit 0 - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 0 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 0 OLOGIC[0]: !invert T1 OLOGIC[0]: V5_MUX_T bit 4 - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_T bit 3 - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_T bit 1 - IDELAY[0]: DELAY_SRC bit 2 - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_T bit 2 - IDELAY[0]: DELAY_SRC bit 3 - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: !invert T2 - - IDELAY[0]: DELAY_SRC bit 1 - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[0]: IDATAIN_INV OLOGIC[0]: FFT_SR_SYNC - IDELAY[0]: DELAY_SRC bit 0 - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: SERDES IDELAY[0]: ENABLE - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 6 - - SPEC_INT: mux IMUX_IOI_ICLK[1] bit 6 - - - - - - - IOB[0]: HR_LVDS bit 0 - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 9 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 9 OLOGIC[0]: ! FFT_INIT bit 0 OLOGIC[0]: ! FFT_SRVAL bit 0 - - - - - IOB[0]: HR_LVDS bit 1 - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 10 - OLOGIC[0]: !invert T3 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 10 - - - - - - - IOB[0]: HR_LVDS bit 2 - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 3 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 3 - - - - - - - IOB[0]: HR_LVDS bit 3 - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 5 - - SPEC_INT: mux IMUX_IOI_ICLK[1] bit 5 - - - - - - - IOB[0]: HR_LVDS bit 4 - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 7 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 7 OLOGIC[0]: !invert T4 - - - - - - IOB[0]: HR_LVDS bit 5 - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 4 - - SPEC_INT: mux IMUX_IOI_ICLK[1] bit 4 - OLOGIC[0]: TBYTE_CTL - - - - - IOB[0]: INPUT_MISC bit 0 - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLK[0] bit 8 SPEC_INT: mux IMUX_IOI_ICLK[1] bit 8 - OLOGIC[0]: ! FFT_SRVAL bit 1 - IDELAY[0]: invert DATAIN - - - IOB[0]: IBUF_PCI - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 1 - - SPEC_INT: mux IMUX_IOI_OCLK[1] bit 1 - OLOGIC[0]: ! FFT_SRVAL bit 2 - - - - - IOB[0]: IBUFDISABLE_EN - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 0 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 0 - OLOGIC[0]: SERDES_MODE bit 0 - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 2 - - SPEC_INT: mux IMUX_IOI_OCLK[1] bit 2 - OLOGIC[0]: TBYTE_SRC - - - - - IOB[0]: IBUF_VREF_HP - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert CLKDIV - - - - - - IOB[0]: IBUF_MODE bit 1 - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! RANK3_USED - - - - - - - - IOB[0]: IBUF_MODE bit 2 - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: IBUF_MODE bit 0 - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 5 - - SPEC_INT: mux IMUX_IOI_OCLK[1] bit 5 - - - IDELAY[0]: invert C - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 9 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 9 - OLOGIC[0]: FFT_SR_ENABLE - IDELAY[0]: CINVCTRL_SEL - - - IOB[0]: INTERMDISABLE_EN - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! CLK1_INV - - OLOGIC[0]: TRISTATE_WIDTH bit 0 - - - - - IOB[0]: DQS_BIAS - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: V5_MUX_O bit 2 - - - - - IOB[0]: PULL_DYNAMIC - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 10 - OLOGIC[0]: ! CLK2_INV SPEC_INT: mux IMUX_IOI_OCLK[1] bit 10 - - - - - - - IOB[0]: PULL bit 2 - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 4 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 4 - OLOGIC[0]: V5_MUX_O bit 1 - - - - - IOB[0]: PULL bit 1 - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 3 - OLOGIC[0]: invert CLKDIVF SPEC_INT: mux IMUX_IOI_OCLK[1] bit 3 - OLOGIC[0]: FFO_SR_SYNC - IDELAY[0]: ! IDELAY_VALUE_CUR bit 4 - - - IOB[0]: PULL bit 0 - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 6 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 6 OLOGIC[0]: CLOCK_RATIO bit 1 OLOGIC[0]: ! FFO_SRVAL bit 0 - - - - - IOB[0]: LOW_VOLTAGE - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 8 - OLOGIC[0]: SELFHEAL SPEC_INT: mux IMUX_IOI_OCLK[1] bit 8 - - - IDELAY[0]: IDELAY_VALUE_INIT bit 4 - - - IOB[0]: HR_LVDS bit 6 - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLK[0] bit 7 SPEC_INT: mux IMUX_IOI_OCLK[1] bit 7 OLOGIC[0]: invert D1 OLOGIC[0]: ! FFO_INIT bit 0 - - - - - IOB[0]: HR_LVDS bit 7 - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLKDIVP bit 0 - OLOGIC[0]: CLOCK_RATIO bit 2 - - - - - - - - IOB[0]: HR_LVDS bit 8 - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_ICLKDIVP bit 1 - OLOGIC[0]: CLOCK_RATIO bit 0 - - - - - - IOB[0]: HR_LVDS bit 9 - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: CLOCK_RATIO bit 3 - - - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 3 - - - IOB[0]: HR_LVDS bit 10 - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 8 - - - - - - IOB[0]: HR_LVDS bit 11 - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D2 - - - - IDELAY[0]: IDELAY_VALUE_INIT bit 3 - - - IOB[0]: HR_LVDS bit 12 - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB[0]: HR_PSLEW bit 2 - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D3 - - - - IDELAY[0]: PIPE_SEL - - - IOB[0]: ! HR_PSLEW bit 1 - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFO_SRVAL bit 1 - - - - - IOB[0]: HR_PSLEW bit 0 - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFO_SRVAL bit 2 - IDELAY[0]: ! IDELAY_VALUE_CUR bit 2 - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY[0]: HIGH_PERFORMANCE_MODE - - - - IOB[0]: HR_NSLEW bit 2 - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIV[0] bit 0 - OLOGIC[0]: invert D4 SPEC_INT: mux IMUX_IOI_OCLKDIV[1] bit 0 - OLOGIC[0]: V5_MUX_O bit 4 - IDELAY[0]: IDELAY_VALUE_INIT bit 2 - - - IOB[0]: ! HR_NSLEW bit 1 - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIV[0] bit 1 SPEC_INT: mux IMUX_IOI_OCLKDIV[1] bit 1 OLOGIC[0]: MISR_ENABLE OLOGIC[0]: V5_MUX_O bit 0 - - - - - IOB[0]: HR_NSLEW bit 0 - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_CLK_SELECT bit 0 - - OLOGIC[0]: FFO_SR_ENABLE - - - - - IOB[0]: HR_OUTPUT_MISC bit 1 - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D5 OLOGIC[0]: V5_MUX_O bit 3 - IDELAY[0]: DELAY_TYPE bit 1 - - - IOB[0]: ! HR_OUTPUT_MISC bit 0 - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: invert D6 - - - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 1 - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 7 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 6 - - - - IDELAY[0]: IDELAY_VALUE_INIT bit 1 - - - IOB[0]: HR_NDRIVE bit 3 - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_ENABLE_FDBK - - - - - - IOB[0]: HR_NDRIVE bit 2 - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 5 - OLOGIC[0]: invert D7 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 5 - - - - - - - IOB[0]: ! HR_NDRIVE bit 1 - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 6 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 6 OLOGIC[0]: MISR_RESET - - IDELAY[0]: DELAY_TYPE bit 0 - - - IOB[0]: ! HR_NDRIVE bit 0 - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 4 - - - - IDELAY[0]: ! IDELAY_VALUE_CUR bit 0 - - - IOB[0]: IN_TERM bit 1 - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 4 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 4 OLOGIC[0]: DATA_WIDTH bit 3 - - - - - - IOB[0]: IN_TERM bit 3 - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_CLK_SELECT bit 1 - - - - IDELAY[0]: IDELAY_VALUE_INIT bit 0 - - - IOB[0]: IN_TERM bit 2 - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 0 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 0 OLOGIC[0]: DATA_WIDTH bit 5 - - - - - - IOB[0]: IN_TERM bit 0 - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 1 - OLOGIC[0]: DATA_WIDTH bit 2 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 1 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 3 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 3 OLOGIC[0]: invert D8 - - - - - - IOB[0]: ! HR_PDRIVE bit 2 - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_IOI_OCLKDIVF[0] bit 2 - OLOGIC[0]: DATA_WIDTH bit 1 SPEC_INT: mux IMUX_IOI_OCLKDIVF[1] bit 2 - - - - - - - IOB[0]: HR_PDRIVE bit 1 - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: DATA_WIDTH bit 0 - - - - - - IOB[0]: HR_PDRIVE bit 0 - - -
### Bitstream
virtex7 IO_HR_N rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.OCLK1
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:D_EMU1 -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:D_EMU2
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SRTYPE[0] -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IFF_SR_USED - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF_LATCH ~ILOGIC[0]:IFF1_SRVAL -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF1_INIT
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF2_SRVAL -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF2_INIT
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:NUM_CE[0] - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IDELAY_VALUE[4] -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IFFDELAY_VALUE[4]
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF3_SRVAL -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF3_INIT
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IDELAY_VALUE[3] -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IFFDELAY_VALUE[3]
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF4_SRVAL -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:IFF4_INIT
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.ZHOLD_FABRIC
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:I_ZHOLD -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DDR_CLK_EDGE[0] - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DDR_CLK_EDGE[1] - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:RANK23_DLY - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[1] ILOGIC[0]:I_DELAY_ENABLE -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SERDES - - ILOGIC[0]:ZHOLD_ENABLE
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:I_TSBYPASS_ENABLE -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IDELAY_VALUE[2]
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:IFFDELAY_VALUE[2] -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:SERDES_MODE[0] - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:BITSLIP_ENABLE - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_RATE[0] - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[3] ~ILOGIC[0]:INV.D -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[2] - - ILOGIC[0]:TSBYPASS_MUX[0]
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[1] ILOGIC[0]:IDELAY_VALUE[1] -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DATA_WIDTH[0] - - ILOGIC[0]:IFFDELAY_VALUE[1]
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[3] ILOGIC[0]:IFF_TSBYPASS_ENABLE -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.CLKDIVP - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[4] - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLKDIVP_INV_EN - - ILOGIC[0]:IFF_DELAY_ENABLE
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[2] ILOGIC[0]:IDELAY_VALUE[0] -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLKDIV_INV_EN - - ILOGIC[0]:IFFDELAY_VALUE[0]
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.CLKDIV ILOGIC[0]:IFF_ZHOLD -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.ZHOLD_IFF
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INTERFACE_TYPE[0] - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[1] -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:INV.OCLK2
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[0] -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC[0]:INV.CLK[2]
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]:DYN_CLK_INV_EN -
ILOGIC[0]:BITSLIP_ENABLE 0.F27.B20
ILOGIC[0]:DYN_CLKDIVP_INV_EN 0.F26.B11
ILOGIC[0]:DYN_CLKDIV_INV_EN 0.F26.B9
ILOGIC[0]:DYN_CLK_INV_EN 0.F28.B0
ILOGIC[0]:D_EMU1 0.F28.B62
ILOGIC[0]:D_EMU2 0.F29.B61
ILOGIC[0]:IFF_DELAY_ENABLE 0.F29.B11
ILOGIC[0]:IFF_SR_USED 0.F26.B57
ILOGIC[0]:IFF_TSBYPASS_ENABLE 0.F28.B14
ILOGIC[0]:IFF_ZHOLD 0.F28.B8
ILOGIC[0]:INV.CLKDIV 0.F27.B8
ILOGIC[0]:INV.CLKDIVP 0.F26.B13
ILOGIC[0]:INV.OCLK1 0.F29.B63
ILOGIC[0]:INV.OCLK2 0.F29.B3
ILOGIC[0]:INV.ZHOLD_FABRIC 0.F29.B31
ILOGIC[0]:INV.ZHOLD_IFF 0.F29.B7
ILOGIC[0]:I_DELAY_ENABLE 0.F28.B26
ILOGIC[0]:I_TSBYPASS_ENABLE 0.F28.B24
ILOGIC[0]:I_ZHOLD 0.F28.B30
ILOGIC[0]:RANK23_DLY 0.F26.B27
ILOGIC[0]:SERDES 0.F26.B25
ILOGIC[0]:ZHOLD_ENABLE 0.F29.B25
non-inverted [0]
ILOGIC[0]:DATA_RATE 0.F26.B19
DDR 0
SDR 1
ILOGIC[0]:DATA_WIDTH 0.F27.B18 0.F26.B17 0.F27.B16 0.F26.B15
NONE 0 0 0 0
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
10 1 0 1 0
14 1 1 1 0
ILOGIC[0]:DDR_CLK_EDGE 0.F27.B28 0.F26.B29
SAME_EDGE_PIPELINED 0 0
OPPOSITE_EDGE 0 1
SAME_EDGE 1 0
ILOGIC[0]:IDELAY_VALUE 0.F28.B46 0.F28.B38 0.F29.B23 0.F28.B16 0.F28.B10
ILOGIC[0]:IFFDELAY_VALUE 0.F29.B45 0.F29.B37 0.F28.B22 0.F29.B15 0.F29.B9
non-inverted [4] [3] [2] [1] [0]
ILOGIC[0]:IFF1_INIT 0.F29.B55
ILOGIC[0]:IFF1_SRVAL 0.F28.B56
ILOGIC[0]:IFF2_INIT 0.F29.B51
ILOGIC[0]:IFF2_SRVAL 0.F28.B52
ILOGIC[0]:IFF3_INIT 0.F29.B41
ILOGIC[0]:IFF3_SRVAL 0.F28.B42
ILOGIC[0]:IFF4_INIT 0.F29.B33
ILOGIC[0]:IFF4_SRVAL 0.F28.B34
ILOGIC[0]:IFF_LATCH 0.F27.B56
ILOGIC[0]:INV.D 0.F28.B18
inverted ~[0]
ILOGIC[0]:INTERFACE_TYPE 0.F27.B12 0.F27.B14 0.F27.B10 0.F27.B26 0.F27.B6
MEMORY 0 0 0 0 0
NETWORKING 0 0 0 0 1
MEMORY_DDR3 0 0 1 1 1
MEMORY_DDR3_V6 0 1 0 1 1
OVERSAMPLE 1 0 0 1 1
ILOGIC[0]:INV.CLK 0.F29.B1 0.F28.B4 0.F28.B2
inverted ~[2] ~[1] ~[0]
ILOGIC[0]:NUM_CE 0.F26.B47
1 0
2 1
ILOGIC[0]:SERDES_MODE 0.F26.B21
MASTER 0
SLAVE 1
ILOGIC[0]:SRTYPE 0.F28.B60
ASYNC 0
SYNC 1
ILOGIC[0]:TSBYPASS_MUX 0.F29.B17
T 0
GND 1

Tile HCLK_IO_HP

Cells: 8

Switchbox HCLK_IO_INT

virtex7 HCLK_IO_HP switchbox HCLK_IO_INT programmable buffers
DestinationSourceBit
CELL[4].HCLK_IO[0]CELL[4].HCLK_ROW[0]MAIN[28][15]
CELL[4].HCLK_IO[1]CELL[4].HCLK_ROW[1]MAIN[29][14]
CELL[4].HCLK_IO[2]CELL[4].HCLK_ROW[2]MAIN[29][16]
CELL[4].HCLK_IO[3]CELL[4].HCLK_ROW[3]MAIN[29][18]
CELL[4].HCLK_IO[4]CELL[4].HCLK_ROW[4]MAIN[29][23]
CELL[4].HCLK_IO[5]CELL[4].HCLK_ROW[5]MAIN[29][27]
CELL[4].HCLK_IO[6]CELL[4].HCLK_ROW[6]MAIN[29][30]
CELL[4].HCLK_IO[7]CELL[4].HCLK_ROW[7]MAIN[29][31]
CELL[4].HCLK_IO[8]CELL[4].HCLK_ROW[8]MAIN[28][14]
CELL[4].HCLK_IO[9]CELL[4].HCLK_ROW[9]MAIN[29][15]
CELL[4].HCLK_IO[10]CELL[4].HCLK_ROW[10]MAIN[29][17]
CELL[4].HCLK_IO[11]CELL[4].HCLK_ROW[11]MAIN[29][19]
CELL[4].RCLK_IO[0]CELL[4].RCLK_ROW[0]MAIN[32][29]
CELL[4].RCLK_IO[1]CELL[4].RCLK_ROW[1]MAIN[30][31]
CELL[4].RCLK_IO[2]CELL[4].RCLK_ROW[2]MAIN[31][19]
CELL[4].RCLK_IO[3]CELL[4].RCLK_ROW[3]MAIN[28][17]
CELL[4].PERF_IO[0]CELL[4].PERF[0]MAIN[36][28]
CELL[4].PERF_IO[1]CELL[4].PERF[1]MAIN[36][20]
CELL[4].PERF_IO[2]CELL[4].PERF[2]MAIN[36][14]
CELL[4].PERF_IO[3]CELL[4].PERF[3]MAIN[37][14]
virtex7 HCLK_IO_HP switchbox HCLK_IO_INT muxes LCLK_IO[0]
BitsDestination
MAIN[29][25]MAIN[28][18]MAIN[29][24]MAIN[27][27]MAIN[27][23]MAIN[27][19]MAIN[29][29]CELL[3].LCLK_IO[0]
MAIN[26][17]MAIN[26][18]MAIN[26][19]MAIN[29][26]MAIN[27][25]MAIN[27][21]MAIN[29][28]CELL[4].LCLK_IO[0]
Source
0000000off
0010001CELL[4].HCLK_IO[0]
0010010CELL[4].HCLK_IO[1]
0010100CELL[4].HCLK_IO[2]
0011000CELL[4].HCLK_IO[3]
0100001CELL[4].HCLK_IO[4]
0100010CELL[4].HCLK_IO[5]
0100100CELL[4].HCLK_IO[6]
0101000CELL[4].HCLK_IO[7]
1000001CELL[4].HCLK_IO[8]
1000010CELL[4].HCLK_IO[9]
1000100CELL[4].HCLK_IO[10]
1001000CELL[4].HCLK_IO[11]
virtex7 HCLK_IO_HP switchbox HCLK_IO_INT muxes LCLK_IO[1]
BitsDestination
MAIN[28][19]MAIN[31][29]MAIN[32][25]MAIN[27][28]MAIN[27][24]MAIN[27][20]MAIN[27][17]CELL[3].LCLK_IO[1]
MAIN[31][28]MAIN[31][31]MAIN[32][24]MAIN[27][29]MAIN[27][26]MAIN[27][22]MAIN[27][18]CELL[4].LCLK_IO[1]
Source
0000000off
0010001CELL[4].HCLK_IO[0]
0010010CELL[4].HCLK_IO[1]
0010100CELL[4].HCLK_IO[2]
0011000CELL[4].HCLK_IO[3]
0100001CELL[4].HCLK_IO[4]
0100010CELL[4].HCLK_IO[5]
0100100CELL[4].HCLK_IO[6]
0101000CELL[4].HCLK_IO[7]
1000001CELL[4].HCLK_IO[8]
1000010CELL[4].HCLK_IO[9]
1000100CELL[4].HCLK_IO[10]
1001000CELL[4].HCLK_IO[11]
virtex7 HCLK_IO_HP switchbox HCLK_IO_INT muxes LCLK_IO[2]
BitsDestination
MAIN[31][26]MAIN[31][24]MAIN[31][25]MAIN[30][24]MAIN[30][26]MAIN[30][28]MAIN[30][30]CELL[3].LCLK_IO[2]
MAIN[30][20]MAIN[30][21]MAIN[30][22]MAIN[30][23]MAIN[30][25]MAIN[30][27]MAIN[30][29]CELL[4].LCLK_IO[2]
Source
0000000off
0010001CELL[4].HCLK_IO[0]
0010010CELL[4].HCLK_IO[1]
0010100CELL[4].HCLK_IO[2]
0011000CELL[4].HCLK_IO[3]
0100001CELL[4].HCLK_IO[4]
0100010CELL[4].HCLK_IO[5]
0100100CELL[4].HCLK_IO[6]
0101000CELL[4].HCLK_IO[7]
1000001CELL[4].HCLK_IO[8]
1000010CELL[4].HCLK_IO[9]
1000100CELL[4].HCLK_IO[10]
1001000CELL[4].HCLK_IO[11]
virtex7 HCLK_IO_HP switchbox HCLK_IO_INT muxes LCLK_IO[3]
BitsDestination
MAIN[26][14]MAIN[27][15]MAIN[26][16]MAIN[29][21]MAIN[28][24]MAIN[28][28]MAIN[27][31]CELL[3].LCLK_IO[3]
MAIN[27][16]MAIN[27][14]MAIN[26][15]MAIN[29][22]MAIN[29][20]MAIN[28][26]MAIN[28][30]CELL[4].LCLK_IO[3]
Source
0000000off
0010001CELL[4].HCLK_IO[0]
0010010CELL[4].HCLK_IO[1]
0010100CELL[4].HCLK_IO[2]
0011000CELL[4].HCLK_IO[3]
0100001CELL[4].HCLK_IO[4]
0100010CELL[4].HCLK_IO[5]
0100100CELL[4].HCLK_IO[6]
0101000CELL[4].HCLK_IO[7]
1000001CELL[4].HCLK_IO[8]
1000010CELL[4].HCLK_IO[9]
1000100CELL[4].HCLK_IO[10]
1001000CELL[4].HCLK_IO[11]
virtex7 HCLK_IO_HP switchbox HCLK_IO_INT muxes LCLK_IO[4]
BitsDestination
MAIN[28][20]MAIN[31][30]MAIN[31][27]MAIN[28][22]MAIN[28][25]MAIN[28][29]MAIN[27][30]CELL[3].LCLK_IO[4]
MAIN[32][14]MAIN[32][15]MAIN[32][23]MAIN[28][21]MAIN[28][23]MAIN[28][27]MAIN[28][31]CELL[4].LCLK_IO[4]
Source
0000000off
0010001CELL[4].HCLK_IO[0]
0010010CELL[4].HCLK_IO[1]
0010100CELL[4].HCLK_IO[2]
0011000CELL[4].HCLK_IO[3]
0100001CELL[4].HCLK_IO[4]
0100010CELL[4].HCLK_IO[5]
0100100CELL[4].HCLK_IO[6]
0101000CELL[4].HCLK_IO[7]
1000001CELL[4].HCLK_IO[8]
1000010CELL[4].HCLK_IO[9]
1000100CELL[4].HCLK_IO[10]
1001000CELL[4].HCLK_IO[11]
virtex7 HCLK_IO_HP switchbox HCLK_IO_INT muxes LCLK_IO[5]
BitsDestination
MAIN[31][21]MAIN[31][22]MAIN[31][23]MAIN[30][15]MAIN[31][14]MAIN[31][16]MAIN[31][18]CELL[3].LCLK_IO[5]
MAIN[30][19]MAIN[30][18]MAIN[30][17]MAIN[30][16]MAIN[30][14]MAIN[31][15]MAIN[31][17]CELL[4].LCLK_IO[5]
Source
0000000off
0010001CELL[4].HCLK_IO[0]
0010010CELL[4].HCLK_IO[1]
0010100CELL[4].HCLK_IO[2]
0011000CELL[4].HCLK_IO[3]
0100001CELL[4].HCLK_IO[4]
0100010CELL[4].HCLK_IO[5]
0100100CELL[4].HCLK_IO[6]
0101000CELL[4].HCLK_IO[7]
1000001CELL[4].HCLK_IO[8]
1000010CELL[4].HCLK_IO[9]
1000100CELL[4].HCLK_IO[10]
1001000CELL[4].HCLK_IO[11]
virtex7 HCLK_IO_HP switchbox HCLK_IO_INT muxes IMUX_IDELAYCTRL_REFCLK
BitsDestination
MAIN[26][31]MAIN[26][30]MAIN[26][29]MAIN[26][28]MAIN[26][27]MAIN[26][26]MAIN[26][25]MAIN[26][24]MAIN[26][23]MAIN[26][22]MAIN[26][21]MAIN[26][20]CELL[4].IMUX_IDELAYCTRL_REFCLK
Source
000000000000off
000000000001CELL[3].LCLK_IO[0]
000000000010CELL[3].LCLK_IO[1]
000000000100CELL[3].LCLK_IO[2]
000000001000CELL[3].LCLK_IO[3]
000000010000CELL[3].LCLK_IO[4]
000000100000CELL[3].LCLK_IO[5]
000001000000CELL[4].LCLK_IO[0]
000010000000CELL[4].LCLK_IO[1]
000100000000CELL[4].LCLK_IO[2]
001000000000CELL[4].LCLK_IO[3]
010000000000CELL[4].LCLK_IO[4]
100000000000CELL[4].LCLK_IO[5]
virtex7 HCLK_IO_HP switchbox HCLK_IO_INT muxes IMUX_BUFIO[0]
BitsDestination
MAIN[36][29]CELL[4].IMUX_BUFIO[0]
Source
0CELL[5].OUT_CLKPAD
1CELL[4].PERF_IO[0]
virtex7 HCLK_IO_HP switchbox HCLK_IO_INT muxes IMUX_BUFIO[1]
BitsDestination
MAIN[37][21]CELL[4].IMUX_BUFIO[1]
Source
0CELL[7].OUT_CLKPAD
1CELL[4].PERF_IO[1]
virtex7 HCLK_IO_HP switchbox HCLK_IO_INT muxes IMUX_BUFIO[2]
BitsDestination
MAIN[36][17]CELL[4].IMUX_BUFIO[2]
Source
0CELL[1].OUT_CLKPAD
1CELL[4].PERF_IO[2]
virtex7 HCLK_IO_HP switchbox HCLK_IO_INT muxes IMUX_BUFIO[3]
BitsDestination
MAIN[37][17]CELL[4].IMUX_BUFIO[3]
Source
0CELL[3].OUT_CLKPAD
1CELL[4].PERF_IO[3]
virtex7 HCLK_IO_HP switchbox HCLK_IO_INT muxes IMUX_BUFR[0]
BitsDestination
MAIN[35][25]MAIN[34][31]MAIN[35][24]MAIN[35][23]MAIN[35][27]MAIN[35][26]MAIN[35][28]MAIN[35][29]CELL[4].IMUX_BUFR[0]
Source
00000000off
00000001CELL[3].IMUX_BYP_SITE[3]
00000010CELL[3].IMUX_BYP_SITE[4]
00000100CELL[4].IMUX_BYP_SITE[3]
00001000CELL[4].IMUX_BYP_SITE[4]
00010000CELL[4].IMUX_BUFIO[0]
00100000CELL[4].IMUX_BUFIO[1]
01000000CELL[4].IMUX_BUFIO[2]
10000000CELL[4].IMUX_BUFIO[3]
virtex7 HCLK_IO_HP switchbox HCLK_IO_INT muxes IMUX_BUFR[1]
BitsDestination
MAIN[34][24]MAIN[34][23]MAIN[36][27]MAIN[36][26]MAIN[34][26]MAIN[34][25]MAIN[34][30]MAIN[34][29]CELL[4].IMUX_BUFR[1]
Source
00000000off
00000001CELL[3].IMUX_BYP_SITE[3]
00000010CELL[3].IMUX_BYP_SITE[4]
00000100CELL[4].IMUX_BYP_SITE[3]
00001000CELL[4].IMUX_BYP_SITE[4]
00010000CELL[4].IMUX_BUFIO[0]
00100000CELL[4].IMUX_BUFIO[1]
01000000CELL[4].IMUX_BUFIO[2]
10000000CELL[4].IMUX_BUFIO[3]
virtex7 HCLK_IO_HP switchbox HCLK_IO_INT muxes IMUX_BUFR[2]
BitsDestination
MAIN[34][16]MAIN[34][15]MAIN[36][25]MAIN[36][24]MAIN[34][18]MAIN[34][17]MAIN[34][19]MAIN[34][20]CELL[4].IMUX_BUFR[2]
Source
00000000off
00000001CELL[3].IMUX_BYP_SITE[3]
00000010CELL[3].IMUX_BYP_SITE[4]
00000100CELL[4].IMUX_BYP_SITE[3]
00001000CELL[4].IMUX_BYP_SITE[4]
00010000CELL[4].IMUX_BUFIO[0]
00100000CELL[4].IMUX_BUFIO[1]
01000000CELL[4].IMUX_BUFIO[2]
10000000CELL[4].IMUX_BUFIO[3]
virtex7 HCLK_IO_HP switchbox HCLK_IO_INT muxes IMUX_BUFR[3]
BitsDestination
MAIN[35][19]MAIN[31][20]MAIN[35][21]MAIN[32][16]MAIN[35][17]MAIN[35][18]MAIN[35][16]MAIN[35][15]CELL[4].IMUX_BUFR[3]
Source
00000000off
00000001CELL[3].IMUX_BYP_SITE[3]
00000010CELL[3].IMUX_BYP_SITE[4]
00000100CELL[4].IMUX_BYP_SITE[3]
00001000CELL[4].IMUX_BYP_SITE[4]
00010000CELL[4].IMUX_BUFIO[0]
00100000CELL[4].IMUX_BUFIO[1]
01000000CELL[4].IMUX_BUFIO[2]
10000000CELL[4].IMUX_BUFIO[3]

Bels BUFR

virtex7 HCLK_IO_HP bel BUFR pins
PinDirectionBUFR[0]BUFR[1]BUFR[2]BUFR[3]
IinCELL[4].IMUX_BUFR[0]CELL[4].IMUX_BUFR[1]CELL[4].IMUX_BUFR[2]CELL[4].IMUX_BUFR[3]
CEinCELL[5].IMUX_BYP_SITE[3]CELL[5].IMUX_BYP_SITE[4]CELL[1].IMUX_BYP_SITE[4]CELL[1].IMUX_BYP_SITE[3]
CLRinCELL[6].IMUX_BYP_SITE[3]CELL[6].IMUX_BYP_SITE[4]CELL[2].IMUX_BYP_SITE[4]CELL[2].IMUX_BYP_SITE[3]
OoutCELL[4].RCLK_ROW[0]CELL[4].RCLK_ROW[1]CELL[4].RCLK_ROW[2]CELL[4].RCLK_ROW[3]
virtex7 HCLK_IO_HP bel BUFR attribute bits
AttributeBUFR[0]BUFR[1]BUFR[2]BUFR[3]
ENABLEMAIN[32][30]MAIN[32][26]MAIN[32][20]MAIN[32][19]
DIVIDE[enum: BUFR_DIVIDE][enum: BUFR_DIVIDE][enum: BUFR_DIVIDE][enum: BUFR_DIVIDE]
virtex7 HCLK_IO_HP enum BUFR_DIVIDE
BUFR[0].DIVIDEMAIN[33][28]MAIN[33][29]MAIN[33][30]MAIN[33][27]
BUFR[1].DIVIDEMAIN[33][24]MAIN[33][25]MAIN[33][26]MAIN[33][23]
BUFR[2].DIVIDEMAIN[33][19]MAIN[33][20]MAIN[33][21]MAIN[33][18]
BUFR[3].DIVIDEMAIN[33][15]MAIN[33][16]MAIN[33][17]MAIN[33][14]
BYPASS0000
_10001
_20011
_30101
_40111
_51001
_61011
_71101
_81111

Bels BUFIO

virtex7 HCLK_IO_HP bel BUFIO pins
PinDirectionBUFIO[0]BUFIO[1]BUFIO[2]BUFIO[3]
IinCELL[4].IMUX_BUFIO[0]CELL[4].IMUX_BUFIO[1]CELL[4].IMUX_BUFIO[2]CELL[4].IMUX_BUFIO[3]
OoutCELL[4].IOCLK[0]CELL[4].IOCLK[1]CELL[4].IOCLK[2]CELL[4].IOCLK[3]
virtex7 HCLK_IO_HP bel BUFIO attribute bits
AttributeBUFIO[0]BUFIO[1]BUFIO[2]BUFIO[3]
ENABLEMAIN[37][31]MAIN[37][22]MAIN[36][18]MAIN[37][18]
DELAY_ENABLEMAIN[36][31]MAIN[36][21]MAIN[36][16]MAIN[37][16]

Bels IDELAYCTRL

virtex7 HCLK_IO_HP bel IDELAYCTRL pins
PinDirectionIDELAYCTRL
REFCLKinCELL[4].IMUX_IDELAYCTRL_REFCLK
RSTinCELL[4].IMUX_IMUX[24]
RDYoutCELL[3].OUT_BEL[22]
DNPULSEOUToutCELL[4].OUT_BEL[13]
UPPULSEOUToutCELL[4].OUT_BEL[16]
OUTN1outCELL[3].OUT_BEL[13]
OUTN65outCELL[3].OUT_BEL[16]
virtex7 HCLK_IO_HP bel IDELAYCTRL attribute bits
AttributeIDELAYCTRL
DLL_ENABLEMAIN[37][29]
DELAY_ENABLEMAIN[37][28]
VCTL_SEL bit 0MAIN[37][23]
VCTL_SEL bit 1MAIN[37][25]
HIGH_PERFORMANCE_MODEMAIN[37][26]
BIAS_MODE bit 0MAIN[37][24]

Bels DCI

virtex7 HCLK_IO_HP bel DCI pins
PinDirectionDCI
TSTCLKinCELL[3].IMUX_FAN_SITE[7]
TSTRSTinCELL[6].IMUX_FAN_SITE[7]
TSTHLPinCELL[4].IMUX_FAN_SITE[7]
TSTHLNinCELL[5].IMUX_FAN_SITE[7]
INT_DCI_ENinCELL[3].IMUX_FAN_SITE[6]
DCIDONEoutCELL[4].OUT_BEL[22]
virtex7 HCLK_IO_HP bel DCI attribute bits
AttributeDCI
ENABLEMAIN[39][31]
QUIETMAIN[38][14]
TEST_ENABLE bit 0MAIN[38][15]
TEST_ENABLE bit 1MAIN[38][31]
CASCADE_FROM_ABOVEMAIN[38][21]
CASCADE_FROM_BELOWMAIN[38][22]
DYNAMIC_ENABLEMAIN[41][31]
NREF_OUTPUT bit 0MAIN[39][30]
NREF_OUTPUT bit 1MAIN[39][29]
NREF_OUTPUT_HALF bit 0MAIN[39][28]
NREF_OUTPUT_HALF bit 1MAIN[39][27]
NREF_OUTPUT_HALF bit 2MAIN[39][26]
NREF_TERM_SPLIT bit 0MAIN[39][25]
NREF_TERM_SPLIT bit 1MAIN[39][24]
NREF_TERM_SPLIT bit 2MAIN[39][23]
PREF_OUTPUT bit 0MAIN[40][18]
PREF_OUTPUT bit 1MAIN[40][17]
PREF_OUTPUT_HALF bit 0MAIN[40][16]
PREF_OUTPUT_HALF bit 1MAIN[40][15]
PREF_OUTPUT_HALF bit 2MAIN[40][14]

Bels BANK

virtex7 HCLK_IO_HP bel BANK pins
PinDirectionBANK
virtex7 HCLK_IO_HP bel BANK attribute bits
AttributeBANK
V7_LVDSBIAS bit 0MAIN[41][14]
V7_LVDSBIAS bit 1MAIN[41][15]
V7_LVDSBIAS bit 2MAIN[41][16]
V7_LVDSBIAS bit 3MAIN[41][17]
V7_LVDSBIAS bit 4MAIN[41][18]
V7_LVDSBIAS bit 5MAIN[41][19]
V7_LVDSBIAS bit 6MAIN[41][20]
V7_LVDSBIAS bit 7MAIN[41][21]
V7_LVDSBIAS bit 8MAIN[41][22]
V7_LVDSBIAS bit 9MAIN[41][23]
V7_LVDSBIAS bit 10MAIN[41][24]
V7_LVDSBIAS bit 11MAIN[41][25]
V7_LVDSBIAS bit 12MAIN[41][26]
V7_LVDSBIAS bit 13MAIN[41][27]
V7_LVDSBIAS bit 14MAIN[41][28]
V7_LVDSBIAS bit 15MAIN[41][29]
V7_LVDSBIAS bit 16MAIN[41][30]
V7_LVDSBIAS bit 17MAIN[40][31]
INTERNAL_VREF[enum: INTERNAL_VREF]
virtex7 HCLK_IO_HP enum INTERNAL_VREF
BANK.INTERNAL_VREFMAIN[40][23]MAIN[40][24]MAIN[40][25]MAIN[40][26]MAIN[40][28]MAIN[40][27]MAIN[40][19]
OFF0000000
_6000000011
_6750000101
_7500001001
_9000010001
_11000100001
_12501000001

Bel wires

virtex7 HCLK_IO_HP bel wires
WirePins
CELL[1].IMUX_BYP_SITE[3]BUFR[3].CE
CELL[1].IMUX_BYP_SITE[4]BUFR[2].CE
CELL[2].IMUX_BYP_SITE[3]BUFR[3].CLR
CELL[2].IMUX_BYP_SITE[4]BUFR[2].CLR
CELL[3].IMUX_FAN_SITE[6]DCI.INT_DCI_EN
CELL[3].IMUX_FAN_SITE[7]DCI.TSTCLK
CELL[3].OUT_BEL[13]IDELAYCTRL.OUTN1
CELL[3].OUT_BEL[16]IDELAYCTRL.OUTN65
CELL[3].OUT_BEL[22]IDELAYCTRL.RDY
CELL[4].IMUX_FAN_SITE[7]DCI.TSTHLP
CELL[4].IMUX_IMUX[24]IDELAYCTRL.RST
CELL[4].OUT_BEL[13]IDELAYCTRL.DNPULSEOUT
CELL[4].OUT_BEL[16]IDELAYCTRL.UPPULSEOUT
CELL[4].OUT_BEL[22]DCI.DCIDONE
CELL[4].RCLK_ROW[0]BUFR[0].O
CELL[4].RCLK_ROW[1]BUFR[1].O
CELL[4].RCLK_ROW[2]BUFR[2].O
CELL[4].RCLK_ROW[3]BUFR[3].O
CELL[4].IOCLK[0]BUFIO[0].O
CELL[4].IOCLK[1]BUFIO[1].O
CELL[4].IOCLK[2]BUFIO[2].O
CELL[4].IOCLK[3]BUFIO[3].O
CELL[4].IMUX_IDELAYCTRL_REFCLKIDELAYCTRL.REFCLK
CELL[4].IMUX_BUFIO[0]BUFIO[0].I
CELL[4].IMUX_BUFIO[1]BUFIO[1].I
CELL[4].IMUX_BUFIO[2]BUFIO[2].I
CELL[4].IMUX_BUFIO[3]BUFIO[3].I
CELL[4].IMUX_BUFR[0]BUFR[0].I
CELL[4].IMUX_BUFR[1]BUFR[1].I
CELL[4].IMUX_BUFR[2]BUFR[2].I
CELL[4].IMUX_BUFR[3]BUFR[3].I
CELL[5].IMUX_BYP_SITE[3]BUFR[0].CE
CELL[5].IMUX_BYP_SITE[4]BUFR[1].CE
CELL[5].IMUX_FAN_SITE[7]DCI.TSTHLN
CELL[6].IMUX_BYP_SITE[3]BUFR[0].CLR
CELL[6].IMUX_BYP_SITE[4]BUFR[1].CLR
CELL[6].IMUX_FAN_SITE[7]DCI.TSTRST

Bitstream

virtex7 HCLK_IO_HP rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 11 HCLK_IO_INT: mux CELL[3].LCLK_IO[3] bit 0 HCLK_IO_INT: mux CELL[4].LCLK_IO[4] bit 0 HCLK_IO_INT: buffer CELL[4].HCLK_IO[7] ← CELL[4].HCLK_ROW[7] HCLK_IO_INT: buffer CELL[4].RCLK_IO[1] ← CELL[4].RCLK_ROW[1] HCLK_IO_INT: mux CELL[4].LCLK_IO[1] bit 5 - - HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 6 - BUFIO[0]: DELAY_ENABLE BUFIO[0]: ENABLE DCI: TEST_ENABLE bit 1 DCI: ENABLE BANK: V7_LVDSBIAS bit 17 DCI: DYNAMIC_ENABLE
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 10 HCLK_IO_INT: mux CELL[3].LCLK_IO[4] bit 0 HCLK_IO_INT: mux CELL[4].LCLK_IO[3] bit 0 HCLK_IO_INT: buffer CELL[4].HCLK_IO[6] ← CELL[4].HCLK_ROW[6] HCLK_IO_INT: mux CELL[3].LCLK_IO[2] bit 0 HCLK_IO_INT: mux CELL[3].LCLK_IO[4] bit 5 BUFR[0]: ENABLE BUFR[0]: DIVIDE bit 1 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 1 - - - - DCI: NREF_OUTPUT bit 0 - BANK: V7_LVDSBIAS bit 16
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 9 HCLK_IO_INT: mux CELL[4].LCLK_IO[1] bit 3 HCLK_IO_INT: mux CELL[3].LCLK_IO[4] bit 1 HCLK_IO_INT: mux CELL[3].LCLK_IO[0] bit 0 HCLK_IO_INT: mux CELL[4].LCLK_IO[2] bit 0 HCLK_IO_INT: mux CELL[3].LCLK_IO[1] bit 5 HCLK_IO_INT: buffer CELL[4].RCLK_IO[0] ← CELL[4].RCLK_ROW[0] BUFR[0]: DIVIDE bit 2 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 0 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 0 HCLK_IO_INT: mux CELL[4].IMUX_BUFIO[0] bit 0 IDELAYCTRL: DLL_ENABLE - DCI: NREF_OUTPUT bit 1 - BANK: V7_LVDSBIAS bit 15
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 8 HCLK_IO_INT: mux CELL[3].LCLK_IO[1] bit 3 HCLK_IO_INT: mux CELL[3].LCLK_IO[3] bit 1 HCLK_IO_INT: mux CELL[4].LCLK_IO[0] bit 0 HCLK_IO_INT: mux CELL[3].LCLK_IO[2] bit 1 HCLK_IO_INT: mux CELL[4].LCLK_IO[1] bit 6 - BUFR[0]: DIVIDE bit 3 - HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 1 HCLK_IO_INT: buffer CELL[4].PERF_IO[0] ← CELL[4].PERF[0] IDELAYCTRL: DELAY_ENABLE - DCI: NREF_OUTPUT_HALF bit 0 BANK: INTERNAL_VREF bit 2 BANK: V7_LVDSBIAS bit 14
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 7 HCLK_IO_INT: mux CELL[3].LCLK_IO[0] bit 3 HCLK_IO_INT: mux CELL[4].LCLK_IO[4] bit 1 HCLK_IO_INT: buffer CELL[4].HCLK_IO[5] ← CELL[4].HCLK_ROW[5] HCLK_IO_INT: mux CELL[4].LCLK_IO[2] bit 1 HCLK_IO_INT: mux CELL[3].LCLK_IO[4] bit 4 - BUFR[0]: DIVIDE bit 0 - HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 3 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 5 - - DCI: NREF_OUTPUT_HALF bit 1 BANK: INTERNAL_VREF bit 1 BANK: V7_LVDSBIAS bit 13
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 6 HCLK_IO_INT: mux CELL[4].LCLK_IO[1] bit 2 HCLK_IO_INT: mux CELL[4].LCLK_IO[3] bit 1 HCLK_IO_INT: mux CELL[4].LCLK_IO[0] bit 3 HCLK_IO_INT: mux CELL[3].LCLK_IO[2] bit 2 HCLK_IO_INT: mux CELL[3].LCLK_IO[2] bit 6 BUFR[1]: ENABLE BUFR[1]: DIVIDE bit 1 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 3 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 2 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 4 IDELAYCTRL: HIGH_PERFORMANCE_MODE - DCI: NREF_OUTPUT_HALF bit 2 BANK: INTERNAL_VREF bit 3 BANK: V7_LVDSBIAS bit 12
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 5 HCLK_IO_INT: mux CELL[4].LCLK_IO[0] bit 2 HCLK_IO_INT: mux CELL[3].LCLK_IO[4] bit 2 HCLK_IO_INT: mux CELL[3].LCLK_IO[0] bit 6 HCLK_IO_INT: mux CELL[4].LCLK_IO[2] bit 2 HCLK_IO_INT: mux CELL[3].LCLK_IO[2] bit 4 HCLK_IO_INT: mux CELL[3].LCLK_IO[1] bit 4 BUFR[1]: DIVIDE bit 2 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 2 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 7 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[2] bit 5 IDELAYCTRL: VCTL_SEL bit 1 - DCI: NREF_TERM_SPLIT bit 0 BANK: INTERNAL_VREF bit 4 BANK: V7_LVDSBIAS bit 11
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 4 HCLK_IO_INT: mux CELL[3].LCLK_IO[1] bit 2 HCLK_IO_INT: mux CELL[3].LCLK_IO[3] bit 2 HCLK_IO_INT: mux CELL[3].LCLK_IO[0] bit 4 HCLK_IO_INT: mux CELL[3].LCLK_IO[2] bit 3 HCLK_IO_INT: mux CELL[3].LCLK_IO[2] bit 5 HCLK_IO_INT: mux CELL[4].LCLK_IO[1] bit 4 BUFR[1]: DIVIDE bit 3 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 7 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 5 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[2] bit 4 IDELAYCTRL: BIAS_MODE bit 0 - DCI: NREF_TERM_SPLIT bit 1 BANK: INTERNAL_VREF bit 5 BANK: V7_LVDSBIAS bit 10
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 3 HCLK_IO_INT: mux CELL[3].LCLK_IO[0] bit 2 HCLK_IO_INT: mux CELL[4].LCLK_IO[4] bit 2 HCLK_IO_INT: buffer CELL[4].HCLK_IO[4] ← CELL[4].HCLK_ROW[4] HCLK_IO_INT: mux CELL[4].LCLK_IO[2] bit 3 HCLK_IO_INT: mux CELL[3].LCLK_IO[5] bit 4 HCLK_IO_INT: mux CELL[4].LCLK_IO[4] bit 4 BUFR[1]: DIVIDE bit 0 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 6 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 4 - IDELAYCTRL: VCTL_SEL bit 0 - DCI: NREF_TERM_SPLIT bit 2 BANK: INTERNAL_VREF bit 6 BANK: V7_LVDSBIAS bit 9
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 2 HCLK_IO_INT: mux CELL[4].LCLK_IO[1] bit 1 HCLK_IO_INT: mux CELL[3].LCLK_IO[4] bit 3 HCLK_IO_INT: mux CELL[4].LCLK_IO[3] bit 3 HCLK_IO_INT: mux CELL[4].LCLK_IO[2] bit 4 HCLK_IO_INT: mux CELL[3].LCLK_IO[5] bit 5 - - - - - BUFIO[1]: ENABLE DCI: CASCADE_FROM_BELOW - - BANK: V7_LVDSBIAS bit 8
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 1 HCLK_IO_INT: mux CELL[4].LCLK_IO[0] bit 1 HCLK_IO_INT: mux CELL[4].LCLK_IO[4] bit 3 HCLK_IO_INT: mux CELL[3].LCLK_IO[3] bit 3 HCLK_IO_INT: mux CELL[4].LCLK_IO[2] bit 5 HCLK_IO_INT: mux CELL[3].LCLK_IO[5] bit 6 - BUFR[2]: DIVIDE bit 1 - HCLK_IO_INT: mux CELL[4].IMUX_BUFR[3] bit 5 BUFIO[1]: DELAY_ENABLE HCLK_IO_INT: mux CELL[4].IMUX_BUFIO[1] bit 0 DCI: CASCADE_FROM_ABOVE - - BANK: V7_LVDSBIAS bit 7
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 0 HCLK_IO_INT: mux CELL[3].LCLK_IO[1] bit 1 HCLK_IO_INT: mux CELL[3].LCLK_IO[4] bit 6 HCLK_IO_INT: mux CELL[4].LCLK_IO[3] bit 2 HCLK_IO_INT: mux CELL[4].LCLK_IO[2] bit 6 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[3] bit 6 BUFR[2]: ENABLE BUFR[2]: DIVIDE bit 2 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[2] bit 0 - HCLK_IO_INT: buffer CELL[4].PERF_IO[1] ← CELL[4].PERF[1] - - - - BANK: V7_LVDSBIAS bit 6
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].LCLK_IO[0] bit 4 HCLK_IO_INT: mux CELL[3].LCLK_IO[0] bit 1 HCLK_IO_INT: mux CELL[3].LCLK_IO[1] bit 6 HCLK_IO_INT: buffer CELL[4].HCLK_IO[11] ← CELL[4].HCLK_ROW[11] HCLK_IO_INT: mux CELL[4].LCLK_IO[5] bit 6 HCLK_IO_INT: buffer CELL[4].RCLK_IO[2] ← CELL[4].RCLK_ROW[2] BUFR[3]: ENABLE BUFR[2]: DIVIDE bit 3 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[2] bit 1 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[3] bit 7 - - - - BANK: INTERNAL_VREF bit 0 BANK: V7_LVDSBIAS bit 5
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].LCLK_IO[0] bit 5 HCLK_IO_INT: mux CELL[4].LCLK_IO[1] bit 0 HCLK_IO_INT: mux CELL[3].LCLK_IO[0] bit 5 HCLK_IO_INT: buffer CELL[4].HCLK_IO[3] ← CELL[4].HCLK_ROW[3] HCLK_IO_INT: mux CELL[4].LCLK_IO[5] bit 5 HCLK_IO_INT: mux CELL[3].LCLK_IO[5] bit 0 - BUFR[2]: DIVIDE bit 0 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[2] bit 3 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[3] bit 2 BUFIO[2]: ENABLE BUFIO[3]: ENABLE - - DCI: PREF_OUTPUT bit 0 BANK: V7_LVDSBIAS bit 4
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].LCLK_IO[0] bit 6 HCLK_IO_INT: mux CELL[3].LCLK_IO[1] bit 0 HCLK_IO_INT: buffer CELL[4].RCLK_IO[3] ← CELL[4].RCLK_ROW[3] HCLK_IO_INT: buffer CELL[4].HCLK_IO[10] ← CELL[4].HCLK_ROW[10] HCLK_IO_INT: mux CELL[4].LCLK_IO[5] bit 4 HCLK_IO_INT: mux CELL[4].LCLK_IO[5] bit 0 - BUFR[3]: DIVIDE bit 1 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[2] bit 2 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[3] bit 3 HCLK_IO_INT: mux CELL[4].IMUX_BUFIO[2] bit 0 HCLK_IO_INT: mux CELL[4].IMUX_BUFIO[3] bit 0 - - DCI: PREF_OUTPUT bit 1 BANK: V7_LVDSBIAS bit 3
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[3].LCLK_IO[3] bit 4 HCLK_IO_INT: mux CELL[4].LCLK_IO[3] bit 6 - HCLK_IO_INT: buffer CELL[4].HCLK_IO[2] ← CELL[4].HCLK_ROW[2] HCLK_IO_INT: mux CELL[4].LCLK_IO[5] bit 3 HCLK_IO_INT: mux CELL[3].LCLK_IO[5] bit 1 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[3] bit 4 BUFR[3]: DIVIDE bit 2 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[2] bit 7 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[3] bit 1 BUFIO[2]: DELAY_ENABLE BUFIO[3]: DELAY_ENABLE - - DCI: PREF_OUTPUT_HALF bit 0 BANK: V7_LVDSBIAS bit 2
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].LCLK_IO[3] bit 4 HCLK_IO_INT: mux CELL[3].LCLK_IO[3] bit 5 HCLK_IO_INT: buffer CELL[4].HCLK_IO[0] ← CELL[4].HCLK_ROW[0] HCLK_IO_INT: buffer CELL[4].HCLK_IO[9] ← CELL[4].HCLK_ROW[9] HCLK_IO_INT: mux CELL[3].LCLK_IO[5] bit 3 HCLK_IO_INT: mux CELL[4].LCLK_IO[5] bit 1 HCLK_IO_INT: mux CELL[4].LCLK_IO[4] bit 5 BUFR[3]: DIVIDE bit 3 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[2] bit 6 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[3] bit 0 - - DCI: TEST_ENABLE bit 0 - DCI: PREF_OUTPUT_HALF bit 1 BANK: V7_LVDSBIAS bit 1
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[3].LCLK_IO[3] bit 6 HCLK_IO_INT: mux CELL[4].LCLK_IO[3] bit 5 HCLK_IO_INT: buffer CELL[4].HCLK_IO[8] ← CELL[4].HCLK_ROW[8] HCLK_IO_INT: buffer CELL[4].HCLK_IO[1] ← CELL[4].HCLK_ROW[1] HCLK_IO_INT: mux CELL[4].LCLK_IO[5] bit 2 HCLK_IO_INT: mux CELL[3].LCLK_IO[5] bit 2 HCLK_IO_INT: mux CELL[4].LCLK_IO[4] bit 6 BUFR[3]: DIVIDE bit 0 - - HCLK_IO_INT: buffer CELL[4].PERF_IO[2] ← CELL[4].PERF[2] HCLK_IO_INT: buffer CELL[4].PERF_IO[3] ← CELL[4].PERF[3] DCI: QUIET - DCI: PREF_OUTPUT_HALF bit 2 BANK: V7_LVDSBIAS bit 0
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile HCLK_IO_HR

Cells: 8

Switchbox HCLK_IO_INT

virtex7 HCLK_IO_HR switchbox HCLK_IO_INT programmable buffers
DestinationSourceBit
CELL[4].HCLK_IO[0]CELL[4].HCLK_ROW[0]MAIN[28][15]
CELL[4].HCLK_IO[1]CELL[4].HCLK_ROW[1]MAIN[29][14]
CELL[4].HCLK_IO[2]CELL[4].HCLK_ROW[2]MAIN[29][16]
CELL[4].HCLK_IO[3]CELL[4].HCLK_ROW[3]MAIN[29][18]
CELL[4].HCLK_IO[4]CELL[4].HCLK_ROW[4]MAIN[29][23]
CELL[4].HCLK_IO[5]CELL[4].HCLK_ROW[5]MAIN[29][27]
CELL[4].HCLK_IO[6]CELL[4].HCLK_ROW[6]MAIN[29][30]
CELL[4].HCLK_IO[7]CELL[4].HCLK_ROW[7]MAIN[29][31]
CELL[4].HCLK_IO[8]CELL[4].HCLK_ROW[8]MAIN[28][14]
CELL[4].HCLK_IO[9]CELL[4].HCLK_ROW[9]MAIN[29][15]
CELL[4].HCLK_IO[10]CELL[4].HCLK_ROW[10]MAIN[29][17]
CELL[4].HCLK_IO[11]CELL[4].HCLK_ROW[11]MAIN[29][19]
CELL[4].RCLK_IO[0]CELL[4].RCLK_ROW[0]MAIN[32][29]
CELL[4].RCLK_IO[1]CELL[4].RCLK_ROW[1]MAIN[30][31]
CELL[4].RCLK_IO[2]CELL[4].RCLK_ROW[2]MAIN[31][19]
CELL[4].RCLK_IO[3]CELL[4].RCLK_ROW[3]MAIN[28][17]
CELL[4].PERF_IO[0]CELL[4].PERF[0]MAIN[36][28]
CELL[4].PERF_IO[1]CELL[4].PERF[1]MAIN[36][20]
CELL[4].PERF_IO[2]CELL[4].PERF[2]MAIN[36][14]
CELL[4].PERF_IO[3]CELL[4].PERF[3]MAIN[37][14]
virtex7 HCLK_IO_HR switchbox HCLK_IO_INT muxes LCLK_IO[0]
BitsDestination
MAIN[29][25]MAIN[28][18]MAIN[29][24]MAIN[27][27]MAIN[27][23]MAIN[27][19]MAIN[29][29]CELL[3].LCLK_IO[0]
MAIN[26][17]MAIN[26][18]MAIN[26][19]MAIN[29][26]MAIN[27][25]MAIN[27][21]MAIN[29][28]CELL[4].LCLK_IO[0]
Source
0000000off
0010001CELL[4].HCLK_IO[0]
0010010CELL[4].HCLK_IO[1]
0010100CELL[4].HCLK_IO[2]
0011000CELL[4].HCLK_IO[3]
0100001CELL[4].HCLK_IO[4]
0100010CELL[4].HCLK_IO[5]
0100100CELL[4].HCLK_IO[6]
0101000CELL[4].HCLK_IO[7]
1000001CELL[4].HCLK_IO[8]
1000010CELL[4].HCLK_IO[9]
1000100CELL[4].HCLK_IO[10]
1001000CELL[4].HCLK_IO[11]
virtex7 HCLK_IO_HR switchbox HCLK_IO_INT muxes LCLK_IO[1]
BitsDestination
MAIN[28][19]MAIN[31][29]MAIN[32][25]MAIN[27][28]MAIN[27][24]MAIN[27][20]MAIN[27][17]CELL[3].LCLK_IO[1]
MAIN[31][28]MAIN[31][31]MAIN[32][24]MAIN[27][29]MAIN[27][26]MAIN[27][22]MAIN[27][18]CELL[4].LCLK_IO[1]
Source
0000000off
0010001CELL[4].HCLK_IO[0]
0010010CELL[4].HCLK_IO[1]
0010100CELL[4].HCLK_IO[2]
0011000CELL[4].HCLK_IO[3]
0100001CELL[4].HCLK_IO[4]
0100010CELL[4].HCLK_IO[5]
0100100CELL[4].HCLK_IO[6]
0101000CELL[4].HCLK_IO[7]
1000001CELL[4].HCLK_IO[8]
1000010CELL[4].HCLK_IO[9]
1000100CELL[4].HCLK_IO[10]
1001000CELL[4].HCLK_IO[11]
virtex7 HCLK_IO_HR switchbox HCLK_IO_INT muxes LCLK_IO[2]
BitsDestination
MAIN[31][26]MAIN[31][24]MAIN[31][25]MAIN[30][24]MAIN[30][26]MAIN[30][28]MAIN[30][30]CELL[3].LCLK_IO[2]
MAIN[30][20]MAIN[30][21]MAIN[30][22]MAIN[30][23]MAIN[30][25]MAIN[30][27]MAIN[30][29]CELL[4].LCLK_IO[2]
Source
0000000off
0010001CELL[4].HCLK_IO[0]
0010010CELL[4].HCLK_IO[1]
0010100CELL[4].HCLK_IO[2]
0011000CELL[4].HCLK_IO[3]
0100001CELL[4].HCLK_IO[4]
0100010CELL[4].HCLK_IO[5]
0100100CELL[4].HCLK_IO[6]
0101000CELL[4].HCLK_IO[7]
1000001CELL[4].HCLK_IO[8]
1000010CELL[4].HCLK_IO[9]
1000100CELL[4].HCLK_IO[10]
1001000CELL[4].HCLK_IO[11]
virtex7 HCLK_IO_HR switchbox HCLK_IO_INT muxes LCLK_IO[3]
BitsDestination
MAIN[26][14]MAIN[27][15]MAIN[26][16]MAIN[29][21]MAIN[28][24]MAIN[28][28]MAIN[27][31]CELL[3].LCLK_IO[3]
MAIN[27][16]MAIN[27][14]MAIN[26][15]MAIN[29][22]MAIN[29][20]MAIN[28][26]MAIN[28][30]CELL[4].LCLK_IO[3]
Source
0000000off
0010001CELL[4].HCLK_IO[0]
0010010CELL[4].HCLK_IO[1]
0010100CELL[4].HCLK_IO[2]
0011000CELL[4].HCLK_IO[3]
0100001CELL[4].HCLK_IO[4]
0100010CELL[4].HCLK_IO[5]
0100100CELL[4].HCLK_IO[6]
0101000CELL[4].HCLK_IO[7]
1000001CELL[4].HCLK_IO[8]
1000010CELL[4].HCLK_IO[9]
1000100CELL[4].HCLK_IO[10]
1001000CELL[4].HCLK_IO[11]
virtex7 HCLK_IO_HR switchbox HCLK_IO_INT muxes LCLK_IO[4]
BitsDestination
MAIN[28][20]MAIN[31][30]MAIN[31][27]MAIN[28][22]MAIN[28][25]MAIN[28][29]MAIN[27][30]CELL[3].LCLK_IO[4]
MAIN[32][14]MAIN[32][15]MAIN[32][23]MAIN[28][21]MAIN[28][23]MAIN[28][27]MAIN[28][31]CELL[4].LCLK_IO[4]
Source
0000000off
0010001CELL[4].HCLK_IO[0]
0010010CELL[4].HCLK_IO[1]
0010100CELL[4].HCLK_IO[2]
0011000CELL[4].HCLK_IO[3]
0100001CELL[4].HCLK_IO[4]
0100010CELL[4].HCLK_IO[5]
0100100CELL[4].HCLK_IO[6]
0101000CELL[4].HCLK_IO[7]
1000001CELL[4].HCLK_IO[8]
1000010CELL[4].HCLK_IO[9]
1000100CELL[4].HCLK_IO[10]
1001000CELL[4].HCLK_IO[11]
virtex7 HCLK_IO_HR switchbox HCLK_IO_INT muxes LCLK_IO[5]
BitsDestination
MAIN[31][21]MAIN[31][22]MAIN[31][23]MAIN[30][15]MAIN[31][14]MAIN[31][16]MAIN[31][18]CELL[3].LCLK_IO[5]
MAIN[30][19]MAIN[30][18]MAIN[30][17]MAIN[30][16]MAIN[30][14]MAIN[31][15]MAIN[31][17]CELL[4].LCLK_IO[5]
Source
0000000off
0010001CELL[4].HCLK_IO[0]
0010010CELL[4].HCLK_IO[1]
0010100CELL[4].HCLK_IO[2]
0011000CELL[4].HCLK_IO[3]
0100001CELL[4].HCLK_IO[4]
0100010CELL[4].HCLK_IO[5]
0100100CELL[4].HCLK_IO[6]
0101000CELL[4].HCLK_IO[7]
1000001CELL[4].HCLK_IO[8]
1000010CELL[4].HCLK_IO[9]
1000100CELL[4].HCLK_IO[10]
1001000CELL[4].HCLK_IO[11]
virtex7 HCLK_IO_HR switchbox HCLK_IO_INT muxes IMUX_IDELAYCTRL_REFCLK
BitsDestination
MAIN[26][31]MAIN[26][30]MAIN[26][29]MAIN[26][28]MAIN[26][27]MAIN[26][26]MAIN[26][25]MAIN[26][24]MAIN[26][23]MAIN[26][22]MAIN[26][21]MAIN[26][20]CELL[4].IMUX_IDELAYCTRL_REFCLK
Source
000000000000off
000000000001CELL[3].LCLK_IO[0]
000000000010CELL[3].LCLK_IO[1]
000000000100CELL[3].LCLK_IO[2]
000000001000CELL[3].LCLK_IO[3]
000000010000CELL[3].LCLK_IO[4]
000000100000CELL[3].LCLK_IO[5]
000001000000CELL[4].LCLK_IO[0]
000010000000CELL[4].LCLK_IO[1]
000100000000CELL[4].LCLK_IO[2]
001000000000CELL[4].LCLK_IO[3]
010000000000CELL[4].LCLK_IO[4]
100000000000CELL[4].LCLK_IO[5]
virtex7 HCLK_IO_HR switchbox HCLK_IO_INT muxes IMUX_BUFIO[0]
BitsDestination
MAIN[36][29]CELL[4].IMUX_BUFIO[0]
Source
0CELL[5].OUT_CLKPAD
1CELL[4].PERF_IO[0]
virtex7 HCLK_IO_HR switchbox HCLK_IO_INT muxes IMUX_BUFIO[1]
BitsDestination
MAIN[37][21]CELL[4].IMUX_BUFIO[1]
Source
0CELL[7].OUT_CLKPAD
1CELL[4].PERF_IO[1]
virtex7 HCLK_IO_HR switchbox HCLK_IO_INT muxes IMUX_BUFIO[2]
BitsDestination
MAIN[36][17]CELL[4].IMUX_BUFIO[2]
Source
0CELL[1].OUT_CLKPAD
1CELL[4].PERF_IO[2]
virtex7 HCLK_IO_HR switchbox HCLK_IO_INT muxes IMUX_BUFIO[3]
BitsDestination
MAIN[37][17]CELL[4].IMUX_BUFIO[3]
Source
0CELL[3].OUT_CLKPAD
1CELL[4].PERF_IO[3]
virtex7 HCLK_IO_HR switchbox HCLK_IO_INT muxes IMUX_BUFR[0]
BitsDestination
MAIN[35][25]MAIN[34][31]MAIN[35][24]MAIN[35][23]MAIN[35][27]MAIN[35][26]MAIN[35][28]MAIN[35][29]CELL[4].IMUX_BUFR[0]
Source
00000000off
00000001CELL[3].IMUX_BYP_SITE[3]
00000010CELL[3].IMUX_BYP_SITE[4]
00000100CELL[4].IMUX_BYP_SITE[3]
00001000CELL[4].IMUX_BYP_SITE[4]
00010000CELL[4].IMUX_BUFIO[0]
00100000CELL[4].IMUX_BUFIO[1]
01000000CELL[4].IMUX_BUFIO[2]
10000000CELL[4].IMUX_BUFIO[3]
virtex7 HCLK_IO_HR switchbox HCLK_IO_INT muxes IMUX_BUFR[1]
BitsDestination
MAIN[34][24]MAIN[34][23]MAIN[36][27]MAIN[36][26]MAIN[34][26]MAIN[34][25]MAIN[34][30]MAIN[34][29]CELL[4].IMUX_BUFR[1]
Source
00000000off
00000001CELL[3].IMUX_BYP_SITE[3]
00000010CELL[3].IMUX_BYP_SITE[4]
00000100CELL[4].IMUX_BYP_SITE[3]
00001000CELL[4].IMUX_BYP_SITE[4]
00010000CELL[4].IMUX_BUFIO[0]
00100000CELL[4].IMUX_BUFIO[1]
01000000CELL[4].IMUX_BUFIO[2]
10000000CELL[4].IMUX_BUFIO[3]
virtex7 HCLK_IO_HR switchbox HCLK_IO_INT muxes IMUX_BUFR[2]
BitsDestination
MAIN[34][16]MAIN[34][15]MAIN[36][25]MAIN[36][24]MAIN[34][18]MAIN[34][17]MAIN[34][19]MAIN[34][20]CELL[4].IMUX_BUFR[2]
Source
00000000off
00000001CELL[3].IMUX_BYP_SITE[3]
00000010CELL[3].IMUX_BYP_SITE[4]
00000100CELL[4].IMUX_BYP_SITE[3]
00001000CELL[4].IMUX_BYP_SITE[4]
00010000CELL[4].IMUX_BUFIO[0]
00100000CELL[4].IMUX_BUFIO[1]
01000000CELL[4].IMUX_BUFIO[2]
10000000CELL[4].IMUX_BUFIO[3]
virtex7 HCLK_IO_HR switchbox HCLK_IO_INT muxes IMUX_BUFR[3]
BitsDestination
MAIN[35][19]MAIN[31][20]MAIN[35][21]MAIN[32][16]MAIN[35][17]MAIN[35][18]MAIN[35][16]MAIN[35][15]CELL[4].IMUX_BUFR[3]
Source
00000000off
00000001CELL[3].IMUX_BYP_SITE[3]
00000010CELL[3].IMUX_BYP_SITE[4]
00000100CELL[4].IMUX_BYP_SITE[3]
00001000CELL[4].IMUX_BYP_SITE[4]
00010000CELL[4].IMUX_BUFIO[0]
00100000CELL[4].IMUX_BUFIO[1]
01000000CELL[4].IMUX_BUFIO[2]
10000000CELL[4].IMUX_BUFIO[3]

Bels BUFR

virtex7 HCLK_IO_HR bel BUFR pins
PinDirectionBUFR[0]BUFR[1]BUFR[2]BUFR[3]
IinCELL[4].IMUX_BUFR[0]CELL[4].IMUX_BUFR[1]CELL[4].IMUX_BUFR[2]CELL[4].IMUX_BUFR[3]
CEinCELL[5].IMUX_BYP_SITE[3]CELL[5].IMUX_BYP_SITE[4]CELL[1].IMUX_BYP_SITE[4]CELL[1].IMUX_BYP_SITE[3]
CLRinCELL[6].IMUX_BYP_SITE[3]CELL[6].IMUX_BYP_SITE[4]CELL[2].IMUX_BYP_SITE[4]CELL[2].IMUX_BYP_SITE[3]
OoutCELL[4].RCLK_ROW[0]CELL[4].RCLK_ROW[1]CELL[4].RCLK_ROW[2]CELL[4].RCLK_ROW[3]
virtex7 HCLK_IO_HR bel BUFR attribute bits
AttributeBUFR[0]BUFR[1]BUFR[2]BUFR[3]
ENABLEMAIN[32][30]MAIN[32][26]MAIN[32][20]MAIN[32][19]
DIVIDE[enum: BUFR_DIVIDE][enum: BUFR_DIVIDE][enum: BUFR_DIVIDE][enum: BUFR_DIVIDE]
virtex7 HCLK_IO_HR enum BUFR_DIVIDE
BUFR[0].DIVIDEMAIN[33][28]MAIN[33][29]MAIN[33][30]MAIN[33][27]
BUFR[1].DIVIDEMAIN[33][24]MAIN[33][25]MAIN[33][26]MAIN[33][23]
BUFR[2].DIVIDEMAIN[33][19]MAIN[33][20]MAIN[33][21]MAIN[33][18]
BUFR[3].DIVIDEMAIN[33][15]MAIN[33][16]MAIN[33][17]MAIN[33][14]
BYPASS0000
_10001
_20011
_30101
_40111
_51001
_61011
_71101
_81111

Bels BUFIO

virtex7 HCLK_IO_HR bel BUFIO pins
PinDirectionBUFIO[0]BUFIO[1]BUFIO[2]BUFIO[3]
IinCELL[4].IMUX_BUFIO[0]CELL[4].IMUX_BUFIO[1]CELL[4].IMUX_BUFIO[2]CELL[4].IMUX_BUFIO[3]
OoutCELL[4].IOCLK[0]CELL[4].IOCLK[1]CELL[4].IOCLK[2]CELL[4].IOCLK[3]
virtex7 HCLK_IO_HR bel BUFIO attribute bits
AttributeBUFIO[0]BUFIO[1]BUFIO[2]BUFIO[3]
ENABLEMAIN[37][31]MAIN[37][22]MAIN[36][18]MAIN[37][18]
DELAY_ENABLEMAIN[36][31]MAIN[36][21]MAIN[36][16]MAIN[37][16]

Bels IDELAYCTRL

virtex7 HCLK_IO_HR bel IDELAYCTRL pins
PinDirectionIDELAYCTRL
REFCLKinCELL[4].IMUX_IDELAYCTRL_REFCLK
RSTinCELL[4].IMUX_IMUX[24]
RDYoutCELL[3].OUT_BEL[22]
DNPULSEOUToutCELL[4].OUT_BEL[13]
UPPULSEOUToutCELL[4].OUT_BEL[16]
OUTN1outCELL[3].OUT_BEL[13]
OUTN65outCELL[3].OUT_BEL[16]
virtex7 HCLK_IO_HR bel IDELAYCTRL attribute bits
AttributeIDELAYCTRL
DLL_ENABLEMAIN[37][29]
DELAY_ENABLEMAIN[37][28]
VCTL_SEL bit 0MAIN[37][23]
VCTL_SEL bit 1MAIN[37][25]
HIGH_PERFORMANCE_MODEMAIN[37][26]
BIAS_MODE bit 0MAIN[37][24]

Bels BANK

virtex7 HCLK_IO_HR bel BANK pins
PinDirectionBANK
virtex7 HCLK_IO_HR bel BANK attribute bits
AttributeBANK
INTERNAL_VREF[enum: INTERNAL_VREF]
HR_DRIVERBIAS bit 0MAIN[39][16]
HR_DRIVERBIAS bit 1MAIN[39][17]
HR_DRIVERBIAS bit 2MAIN[39][18]
HR_DRIVERBIAS bit 3MAIN[38][14]
HR_DRIVERBIAS bit 4MAIN[38][15]
HR_DRIVERBIAS bit 5MAIN[39][19]
HR_DRIVERBIAS bit 6MAIN[39][20]
HR_DRIVERBIAS bit 7MAIN[39][21]
HR_DRIVERBIAS bit 8MAIN[41][26]
HR_DRIVERBIAS bit 9MAIN[41][25]
HR_DRIVERBIAS bit 10MAIN[41][24]
HR_DRIVERBIAS bit 11MAIN[41][23]
HR_DRIVERBIAS bit 12MAIN[41][22]
HR_DRIVERBIAS bit 13MAIN[41][21]
HR_DRIVERBIAS bit 14MAIN[39][14]
HR_DRIVERBIAS bit 15MAIN[39][15]
HR_LVDS_COMMON bit 0MAIN[40][30]
HR_LVDS_COMMON bit 1MAIN[40][28]
HR_LVDS_COMMON bit 2MAIN[40][27]
HR_LVDS_COMMON bit 3MAIN[40][26]
HR_LVDS_COMMON bit 4MAIN[40][25]
HR_LVDS_COMMON bit 5MAIN[40][31]
HR_LVDS_COMMON bit 6MAIN[39][23]
HR_LVDS_COMMON bit 7MAIN[41][31]
HR_LVDS_COMMON bit 8MAIN[41][30]
HR_LVDS_GROUP[0] bit 0MAIN[38][23]
HR_LVDS_GROUP[0] bit 1MAIN[38][24]
HR_LVDS_GROUP[0] bit 2MAIN[38][25]
HR_LVDS_GROUP[0] bit 3MAIN[41][29]
HR_LVDS_GROUP[0] bit 4MAIN[41][28]
HR_LVDS_GROUP[0] bit 5MAIN[41][27]
HR_LVDS_GROUP[0] bit 6MAIN[41][14]
HR_LVDS_GROUP[0] bit 7MAIN[41][20]
HR_LVDS_GROUP[0] bit 8MAIN[41][19]
HR_LVDS_GROUP[0] bit 9MAIN[41][18]
HR_LVDS_GROUP[0] bit 10MAIN[41][17]
HR_LVDS_GROUP[0] bit 11MAIN[41][16]
HR_LVDS_GROUP[0] bit 12MAIN[41][15]
HR_LVDS_GROUP[0] bit 13MAIN[38][28]
HR_LVDS_GROUP[0] bit 14MAIN[38][27]
HR_LVDS_GROUP[0] bit 15MAIN[40][29]
HR_LVDS_GROUP[1] bit 0MAIN[38][18]
HR_LVDS_GROUP[1] bit 1MAIN[38][19]
HR_LVDS_GROUP[1] bit 2MAIN[38][20]
HR_LVDS_GROUP[1] bit 3MAIN[40][24]
HR_LVDS_GROUP[1] bit 4MAIN[40][23]
HR_LVDS_GROUP[1] bit 5MAIN[40][22]
HR_LVDS_GROUP[1] bit 6MAIN[40][21]
HR_LVDS_GROUP[1] bit 7MAIN[40][20]
HR_LVDS_GROUP[1] bit 8MAIN[40][19]
HR_LVDS_GROUP[1] bit 9MAIN[40][18]
HR_LVDS_GROUP[1] bit 10MAIN[40][17]
HR_LVDS_GROUP[1] bit 11MAIN[40][16]
HR_LVDS_GROUP[1] bit 12MAIN[40][15]
HR_LVDS_GROUP[1] bit 13MAIN[40][14]
HR_LVDS_GROUP[1] bit 14MAIN[39][31]
HR_LVDS_GROUP[1] bit 15MAIN[38][31]
HR_VCCOSENSE_FLAGMAIN[38][22]
HR_VCCOSENSE_MODE[enum: VCCOSENSE_MODE]
virtex7 HCLK_IO_HR enum INTERNAL_VREF
BANK.INTERNAL_VREFMAIN[38][30]MAIN[38][29]MAIN[39][29]MAIN[39][24]MAIN[39][22]MAIN[39][30]MAIN[38][26]
OFF0000000
_6000000011
_6750000101
_7500001001
_9000010001
_11000100001
_12501000001
virtex7 HCLK_IO_HR enum VCCOSENSE_MODE
BANK.HR_VCCOSENSE_MODEMAIN[39][27]MAIN[39][26]MAIN[39][25]MAIN[39][28]
ALWAYSACTIVE0000
FREEZE0001
OFF1110

Bel wires

virtex7 HCLK_IO_HR bel wires
WirePins
CELL[1].IMUX_BYP_SITE[3]BUFR[3].CE
CELL[1].IMUX_BYP_SITE[4]BUFR[2].CE
CELL[2].IMUX_BYP_SITE[3]BUFR[3].CLR
CELL[2].IMUX_BYP_SITE[4]BUFR[2].CLR
CELL[3].OUT_BEL[13]IDELAYCTRL.OUTN1
CELL[3].OUT_BEL[16]IDELAYCTRL.OUTN65
CELL[3].OUT_BEL[22]IDELAYCTRL.RDY
CELL[4].IMUX_IMUX[24]IDELAYCTRL.RST
CELL[4].OUT_BEL[13]IDELAYCTRL.DNPULSEOUT
CELL[4].OUT_BEL[16]IDELAYCTRL.UPPULSEOUT
CELL[4].RCLK_ROW[0]BUFR[0].O
CELL[4].RCLK_ROW[1]BUFR[1].O
CELL[4].RCLK_ROW[2]BUFR[2].O
CELL[4].RCLK_ROW[3]BUFR[3].O
CELL[4].IOCLK[0]BUFIO[0].O
CELL[4].IOCLK[1]BUFIO[1].O
CELL[4].IOCLK[2]BUFIO[2].O
CELL[4].IOCLK[3]BUFIO[3].O
CELL[4].IMUX_IDELAYCTRL_REFCLKIDELAYCTRL.REFCLK
CELL[4].IMUX_BUFIO[0]BUFIO[0].I
CELL[4].IMUX_BUFIO[1]BUFIO[1].I
CELL[4].IMUX_BUFIO[2]BUFIO[2].I
CELL[4].IMUX_BUFIO[3]BUFIO[3].I
CELL[4].IMUX_BUFR[0]BUFR[0].I
CELL[4].IMUX_BUFR[1]BUFR[1].I
CELL[4].IMUX_BUFR[2]BUFR[2].I
CELL[4].IMUX_BUFR[3]BUFR[3].I
CELL[5].IMUX_BYP_SITE[3]BUFR[0].CE
CELL[5].IMUX_BYP_SITE[4]BUFR[1].CE
CELL[6].IMUX_BYP_SITE[3]BUFR[0].CLR
CELL[6].IMUX_BYP_SITE[4]BUFR[1].CLR

Bitstream

virtex7 HCLK_IO_HR rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 11 HCLK_IO_INT: mux CELL[3].LCLK_IO[3] bit 0 HCLK_IO_INT: mux CELL[4].LCLK_IO[4] bit 0 HCLK_IO_INT: buffer CELL[4].HCLK_IO[7] ← CELL[4].HCLK_ROW[7] HCLK_IO_INT: buffer CELL[4].RCLK_IO[1] ← CELL[4].RCLK_ROW[1] HCLK_IO_INT: mux CELL[4].LCLK_IO[1] bit 5 - - HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 6 - BUFIO[0]: DELAY_ENABLE BUFIO[0]: ENABLE BANK: HR_LVDS_GROUP[1] bit 15 BANK: HR_LVDS_GROUP[1] bit 14 BANK: HR_LVDS_COMMON bit 5 BANK: HR_LVDS_COMMON bit 7
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 10 HCLK_IO_INT: mux CELL[3].LCLK_IO[4] bit 0 HCLK_IO_INT: mux CELL[4].LCLK_IO[3] bit 0 HCLK_IO_INT: buffer CELL[4].HCLK_IO[6] ← CELL[4].HCLK_ROW[6] HCLK_IO_INT: mux CELL[3].LCLK_IO[2] bit 0 HCLK_IO_INT: mux CELL[3].LCLK_IO[4] bit 5 BUFR[0]: ENABLE BUFR[0]: DIVIDE bit 1 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 1 - - - BANK: INTERNAL_VREF bit 6 BANK: INTERNAL_VREF bit 1 BANK: HR_LVDS_COMMON bit 0 BANK: HR_LVDS_COMMON bit 8
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 9 HCLK_IO_INT: mux CELL[4].LCLK_IO[1] bit 3 HCLK_IO_INT: mux CELL[3].LCLK_IO[4] bit 1 HCLK_IO_INT: mux CELL[3].LCLK_IO[0] bit 0 HCLK_IO_INT: mux CELL[4].LCLK_IO[2] bit 0 HCLK_IO_INT: mux CELL[3].LCLK_IO[1] bit 5 HCLK_IO_INT: buffer CELL[4].RCLK_IO[0] ← CELL[4].RCLK_ROW[0] BUFR[0]: DIVIDE bit 2 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 0 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 0 HCLK_IO_INT: mux CELL[4].IMUX_BUFIO[0] bit 0 IDELAYCTRL: DLL_ENABLE BANK: INTERNAL_VREF bit 5 BANK: INTERNAL_VREF bit 4 BANK: HR_LVDS_GROUP[0] bit 15 BANK: HR_LVDS_GROUP[0] bit 3
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 8 HCLK_IO_INT: mux CELL[3].LCLK_IO[1] bit 3 HCLK_IO_INT: mux CELL[3].LCLK_IO[3] bit 1 HCLK_IO_INT: mux CELL[4].LCLK_IO[0] bit 0 HCLK_IO_INT: mux CELL[3].LCLK_IO[2] bit 1 HCLK_IO_INT: mux CELL[4].LCLK_IO[1] bit 6 - BUFR[0]: DIVIDE bit 3 - HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 1 HCLK_IO_INT: buffer CELL[4].PERF_IO[0] ← CELL[4].PERF[0] IDELAYCTRL: DELAY_ENABLE BANK: HR_LVDS_GROUP[0] bit 13 BANK: HR_VCCOSENSE_MODE bit 0 BANK: HR_LVDS_COMMON bit 1 BANK: HR_LVDS_GROUP[0] bit 4
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 7 HCLK_IO_INT: mux CELL[3].LCLK_IO[0] bit 3 HCLK_IO_INT: mux CELL[4].LCLK_IO[4] bit 1 HCLK_IO_INT: buffer CELL[4].HCLK_IO[5] ← CELL[4].HCLK_ROW[5] HCLK_IO_INT: mux CELL[4].LCLK_IO[2] bit 1 HCLK_IO_INT: mux CELL[3].LCLK_IO[4] bit 4 - BUFR[0]: DIVIDE bit 0 - HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 3 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 5 - BANK: HR_LVDS_GROUP[0] bit 14 BANK: HR_VCCOSENSE_MODE bit 3 BANK: HR_LVDS_COMMON bit 2 BANK: HR_LVDS_GROUP[0] bit 5
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 6 HCLK_IO_INT: mux CELL[4].LCLK_IO[1] bit 2 HCLK_IO_INT: mux CELL[4].LCLK_IO[3] bit 1 HCLK_IO_INT: mux CELL[4].LCLK_IO[0] bit 3 HCLK_IO_INT: mux CELL[3].LCLK_IO[2] bit 2 HCLK_IO_INT: mux CELL[3].LCLK_IO[2] bit 6 BUFR[1]: ENABLE BUFR[1]: DIVIDE bit 1 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 3 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 2 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 4 IDELAYCTRL: HIGH_PERFORMANCE_MODE BANK: INTERNAL_VREF bit 0 BANK: HR_VCCOSENSE_MODE bit 2 BANK: HR_LVDS_COMMON bit 3 BANK: HR_DRIVERBIAS bit 8
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 5 HCLK_IO_INT: mux CELL[4].LCLK_IO[0] bit 2 HCLK_IO_INT: mux CELL[3].LCLK_IO[4] bit 2 HCLK_IO_INT: mux CELL[3].LCLK_IO[0] bit 6 HCLK_IO_INT: mux CELL[4].LCLK_IO[2] bit 2 HCLK_IO_INT: mux CELL[3].LCLK_IO[2] bit 4 HCLK_IO_INT: mux CELL[3].LCLK_IO[1] bit 4 BUFR[1]: DIVIDE bit 2 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 2 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 7 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[2] bit 5 IDELAYCTRL: VCTL_SEL bit 1 BANK: HR_LVDS_GROUP[0] bit 2 BANK: HR_VCCOSENSE_MODE bit 1 BANK: HR_LVDS_COMMON bit 4 BANK: HR_DRIVERBIAS bit 9
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 4 HCLK_IO_INT: mux CELL[3].LCLK_IO[1] bit 2 HCLK_IO_INT: mux CELL[3].LCLK_IO[3] bit 2 HCLK_IO_INT: mux CELL[3].LCLK_IO[0] bit 4 HCLK_IO_INT: mux CELL[3].LCLK_IO[2] bit 3 HCLK_IO_INT: mux CELL[3].LCLK_IO[2] bit 5 HCLK_IO_INT: mux CELL[4].LCLK_IO[1] bit 4 BUFR[1]: DIVIDE bit 3 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 7 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 5 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[2] bit 4 IDELAYCTRL: BIAS_MODE bit 0 BANK: HR_LVDS_GROUP[0] bit 1 BANK: INTERNAL_VREF bit 3 BANK: HR_LVDS_GROUP[1] bit 3 BANK: HR_DRIVERBIAS bit 10
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 3 HCLK_IO_INT: mux CELL[3].LCLK_IO[0] bit 2 HCLK_IO_INT: mux CELL[4].LCLK_IO[4] bit 2 HCLK_IO_INT: buffer CELL[4].HCLK_IO[4] ← CELL[4].HCLK_ROW[4] HCLK_IO_INT: mux CELL[4].LCLK_IO[2] bit 3 HCLK_IO_INT: mux CELL[3].LCLK_IO[5] bit 4 HCLK_IO_INT: mux CELL[4].LCLK_IO[4] bit 4 BUFR[1]: DIVIDE bit 0 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 6 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 4 - IDELAYCTRL: VCTL_SEL bit 0 BANK: HR_LVDS_GROUP[0] bit 0 BANK: HR_LVDS_COMMON bit 6 BANK: HR_LVDS_GROUP[1] bit 4 BANK: HR_DRIVERBIAS bit 11
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 2 HCLK_IO_INT: mux CELL[4].LCLK_IO[1] bit 1 HCLK_IO_INT: mux CELL[3].LCLK_IO[4] bit 3 HCLK_IO_INT: mux CELL[4].LCLK_IO[3] bit 3 HCLK_IO_INT: mux CELL[4].LCLK_IO[2] bit 4 HCLK_IO_INT: mux CELL[3].LCLK_IO[5] bit 5 - - - - - BUFIO[1]: ENABLE BANK: HR_VCCOSENSE_FLAG BANK: INTERNAL_VREF bit 2 BANK: HR_LVDS_GROUP[1] bit 5 BANK: HR_DRIVERBIAS bit 12
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 1 HCLK_IO_INT: mux CELL[4].LCLK_IO[0] bit 1 HCLK_IO_INT: mux CELL[4].LCLK_IO[4] bit 3 HCLK_IO_INT: mux CELL[3].LCLK_IO[3] bit 3 HCLK_IO_INT: mux CELL[4].LCLK_IO[2] bit 5 HCLK_IO_INT: mux CELL[3].LCLK_IO[5] bit 6 - BUFR[2]: DIVIDE bit 1 - HCLK_IO_INT: mux CELL[4].IMUX_BUFR[3] bit 5 BUFIO[1]: DELAY_ENABLE HCLK_IO_INT: mux CELL[4].IMUX_BUFIO[1] bit 0 - BANK: HR_DRIVERBIAS bit 7 BANK: HR_LVDS_GROUP[1] bit 6 BANK: HR_DRIVERBIAS bit 13
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 0 HCLK_IO_INT: mux CELL[3].LCLK_IO[1] bit 1 HCLK_IO_INT: mux CELL[3].LCLK_IO[4] bit 6 HCLK_IO_INT: mux CELL[4].LCLK_IO[3] bit 2 HCLK_IO_INT: mux CELL[4].LCLK_IO[2] bit 6 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[3] bit 6 BUFR[2]: ENABLE BUFR[2]: DIVIDE bit 2 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[2] bit 0 - HCLK_IO_INT: buffer CELL[4].PERF_IO[1] ← CELL[4].PERF[1] - BANK: HR_LVDS_GROUP[1] bit 2 BANK: HR_DRIVERBIAS bit 6 BANK: HR_LVDS_GROUP[1] bit 7 BANK: HR_LVDS_GROUP[0] bit 7
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].LCLK_IO[0] bit 4 HCLK_IO_INT: mux CELL[3].LCLK_IO[0] bit 1 HCLK_IO_INT: mux CELL[3].LCLK_IO[1] bit 6 HCLK_IO_INT: buffer CELL[4].HCLK_IO[11] ← CELL[4].HCLK_ROW[11] HCLK_IO_INT: mux CELL[4].LCLK_IO[5] bit 6 HCLK_IO_INT: buffer CELL[4].RCLK_IO[2] ← CELL[4].RCLK_ROW[2] BUFR[3]: ENABLE BUFR[2]: DIVIDE bit 3 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[2] bit 1 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[3] bit 7 - - BANK: HR_LVDS_GROUP[1] bit 1 BANK: HR_DRIVERBIAS bit 5 BANK: HR_LVDS_GROUP[1] bit 8 BANK: HR_LVDS_GROUP[0] bit 8
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].LCLK_IO[0] bit 5 HCLK_IO_INT: mux CELL[4].LCLK_IO[1] bit 0 HCLK_IO_INT: mux CELL[3].LCLK_IO[0] bit 5 HCLK_IO_INT: buffer CELL[4].HCLK_IO[3] ← CELL[4].HCLK_ROW[3] HCLK_IO_INT: mux CELL[4].LCLK_IO[5] bit 5 HCLK_IO_INT: mux CELL[3].LCLK_IO[5] bit 0 - BUFR[2]: DIVIDE bit 0 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[2] bit 3 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[3] bit 2 BUFIO[2]: ENABLE BUFIO[3]: ENABLE BANK: HR_LVDS_GROUP[1] bit 0 BANK: HR_DRIVERBIAS bit 2 BANK: HR_LVDS_GROUP[1] bit 9 BANK: HR_LVDS_GROUP[0] bit 9
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].LCLK_IO[0] bit 6 HCLK_IO_INT: mux CELL[3].LCLK_IO[1] bit 0 HCLK_IO_INT: buffer CELL[4].RCLK_IO[3] ← CELL[4].RCLK_ROW[3] HCLK_IO_INT: buffer CELL[4].HCLK_IO[10] ← CELL[4].HCLK_ROW[10] HCLK_IO_INT: mux CELL[4].LCLK_IO[5] bit 4 HCLK_IO_INT: mux CELL[4].LCLK_IO[5] bit 0 - BUFR[3]: DIVIDE bit 1 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[2] bit 2 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[3] bit 3 HCLK_IO_INT: mux CELL[4].IMUX_BUFIO[2] bit 0 HCLK_IO_INT: mux CELL[4].IMUX_BUFIO[3] bit 0 - BANK: HR_DRIVERBIAS bit 1 BANK: HR_LVDS_GROUP[1] bit 10 BANK: HR_LVDS_GROUP[0] bit 10
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[3].LCLK_IO[3] bit 4 HCLK_IO_INT: mux CELL[4].LCLK_IO[3] bit 6 - HCLK_IO_INT: buffer CELL[4].HCLK_IO[2] ← CELL[4].HCLK_ROW[2] HCLK_IO_INT: mux CELL[4].LCLK_IO[5] bit 3 HCLK_IO_INT: mux CELL[3].LCLK_IO[5] bit 1 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[3] bit 4 BUFR[3]: DIVIDE bit 2 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[2] bit 7 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[3] bit 1 BUFIO[2]: DELAY_ENABLE BUFIO[3]: DELAY_ENABLE - BANK: HR_DRIVERBIAS bit 0 BANK: HR_LVDS_GROUP[1] bit 11 BANK: HR_LVDS_GROUP[0] bit 11
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[4].LCLK_IO[3] bit 4 HCLK_IO_INT: mux CELL[3].LCLK_IO[3] bit 5 HCLK_IO_INT: buffer CELL[4].HCLK_IO[0] ← CELL[4].HCLK_ROW[0] HCLK_IO_INT: buffer CELL[4].HCLK_IO[9] ← CELL[4].HCLK_ROW[9] HCLK_IO_INT: mux CELL[3].LCLK_IO[5] bit 3 HCLK_IO_INT: mux CELL[4].LCLK_IO[5] bit 1 HCLK_IO_INT: mux CELL[4].LCLK_IO[4] bit 5 BUFR[3]: DIVIDE bit 3 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[2] bit 6 HCLK_IO_INT: mux CELL[4].IMUX_BUFR[3] bit 0 - - BANK: HR_DRIVERBIAS bit 4 BANK: HR_DRIVERBIAS bit 15 BANK: HR_LVDS_GROUP[1] bit 12 BANK: HR_LVDS_GROUP[0] bit 12
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IO_INT: mux CELL[3].LCLK_IO[3] bit 6 HCLK_IO_INT: mux CELL[4].LCLK_IO[3] bit 5 HCLK_IO_INT: buffer CELL[4].HCLK_IO[8] ← CELL[4].HCLK_ROW[8] HCLK_IO_INT: buffer CELL[4].HCLK_IO[1] ← CELL[4].HCLK_ROW[1] HCLK_IO_INT: mux CELL[4].LCLK_IO[5] bit 2 HCLK_IO_INT: mux CELL[3].LCLK_IO[5] bit 2 HCLK_IO_INT: mux CELL[4].LCLK_IO[4] bit 6 BUFR[3]: DIVIDE bit 0 - - HCLK_IO_INT: buffer CELL[4].PERF_IO[2] ← CELL[4].PERF[2] HCLK_IO_INT: buffer CELL[4].PERF_IO[3] ← CELL[4].PERF[3] BANK: HR_DRIVERBIAS bit 3 BANK: HR_DRIVERBIAS bit 14 BANK: HR_LVDS_GROUP[1] bit 13 BANK: HR_LVDS_GROUP[0] bit 6
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tables — HP IO

Table IOB_DATA

virtex7 table IOB_DATA
Row PDRIVE NDRIVE OUTPUT_MISC PSLEW_FAST NSLEW_FAST PSLEW_SLOW NSLEW_SLOW PREF_OUTPUT NREF_OUTPUT PREF_OUTPUT_HALF NREF_OUTPUT_HALF NREF_TERM_SPLIT
OFF 0b0000000 0b0000000 0b000000 0b00000 0b00000 - - 0b00 0b00 0b000 0b000 0b000
VREF - - - - - - - - - - - -
VR 0b0000000 0b0000000 - 0b11111 0b11111 - - - - - - -
LVCMOS12_2 0b0010010 0b0001100 - 0b11111 0b11000 0b00000 0b00000 - - - - -
LVCMOS12_4 0b0100010 0b0010100 - 0b11111 0b11111 0b00000 0b00000 - - - - -
LVCMOS12_6 0b0111000 0b0011100 - 0b11111 0b11111 0b00000 0b00000 - - - - -
LVCMOS12_8 0b1001100 0b0100100 - 0b11001 0b11111 0b00000 0b00000 - - - - -
LVCMOS15_2 0b0001100 0b0001000 - 0b11111 0b00001 0b00000 0b00000 - - - - -
LVCMOS15_4 0b0010110 0b0010000 - 0b11111 0b11111 0b00000 0b00000 - - - - -
LVCMOS15_6 0b0100000 0b0011000 - 0b11111 0b11111 0b00000 0b00000 - - - - -
LVCMOS15_8 0b0101100 0b0100000 - 0b01001 0b11111 0b00000 0b00000 - - - - -
LVCMOS15_12 0b1000010 0b0110000 - 0b01000 0b11111 0b00000 0b00000 - - - - -
LVCMOS15_16 0b1011010 0b1000000 - 0b00110 0b11111 0b00000 0b00000 - - - - -
LVCMOS18_2 0b0001000 0b0001000 - 0b10001 0b11111 0b00000 0b00000 - - - - -
LVCMOS18_4 0b0001110 0b0001100 - 0b11111 0b11111 0b00000 0b00000 - - - - -
LVCMOS18_6 0b0011110 0b0010100 - 0b00111 0b11111 0b00000 0b00000 - - - - -
LVCMOS18_8 0b0011100 0b0011000 - 0b00110 0b11111 0b00000 0b00000 - - - - -
LVCMOS18_12 0b0101100 0b0101000 - 0b01111 0b11111 0b00000 0b00000 - - - - -
LVCMOS18_16 0b0111010 0b0110100 - 0b00110 0b11111 0b00000 0b00000 - - - - -
LVCMOS25_2 - - - - - - - - - - - -
LVCMOS25_4 - - - - - - - - - - - -
LVCMOS25_6 - - - - - - - - - - - -
LVCMOS25_8 - - - - - - - - - - - -
LVCMOS25_12 - - - - - - - - - - - -
LVCMOS25_16 - - - - - - - - - - - -
LVCMOS25_24 - - - - - - - - - - - -
LVCMOS33_2 - - - - - - - - - - - -
LVCMOS33_4 - - - - - - - - - - - -
LVCMOS33_6 - - - - - - - - - - - -
LVCMOS33_8 - - - - - - - - - - - -
LVCMOS33_12 - - - - - - - - - - - -
LVCMOS33_16 - - - - - - - - - - - -
LVCMOS33_24 - - - - - - - - - - - -
LVTTL_2 - - - - - - - - - - - -
LVTTL_4 - - - - - - - - - - - -
LVTTL_6 - - - - - - - - - - - -
LVTTL_8 - - - - - - - - - - - -
LVTTL_12 - - - - - - - - - - - -
LVTTL_16 - - - - - - - - - - - -
LVTTL_24 - - - - - - - - - - - -
PCI33_3 - - - - - - - - - - - -
PCI66_3 - - - - - - - - - - - -
PCIX - - - - - - - - - - - -
LVDCI_15 - - - 0b00111 0b11111 - - 0b01 0b10 - - -
LVDCI_18 - - - 0b00110 0b11111 - - 0b01 0b10 - - -
LVDCI_25 - - - - - - - - - - - -
LVDCI_33 - - - - - - - - - - - -
LVDCI_DV2_15 - - - 0b01111 0b11000 - - - - 0b011 0b100 -
LVDCI_DV2_18 - - - 0b01100 0b11000 - - - - 0b101 0b100 -
LVDCI_DV2_25 - - - - - - - - - - - -
HSLVDCI_15 - - - 0b00111 0b11111 - - 0b00 0b00 - - -
HSLVDCI_18 - - - 0b00110 0b11111 - - 0b00 0b00 - - -
HSLVDCI_25 - - - - - - - - - - - -
HSLVDCI_33 - - - - - - - - - - - -
HSUL_12_DCI - - - 0b00111 0b11111 0b00001 0b00010 0b01 0b10 - - -
GTL - - - - - - - - - - - -
GTLP - - - - - - - - - - - -
SSTL12 0b1011000 0b0101000 - 0b11010 0b11111 0b00011 0b00011 - - - - -
SSTL135 0b1000100 0b0101000 - 0b11110 0b11111 0b00011 0b00011 - - - - -
SSTL15 0b0110000 0b0100100 - 0b11111 0b11010 0b00011 0b00111 - - - - -
SSTL18_I 0b0011100 0b0011000 - 0b00101 0b11011 0b00001 0b00011 - - - - -
SSTL18_II 0b1010110 0b1001000 - 0b00011 0b11111 0b00000 0b00000 - - - - -
SSTL2_I - - - - - - - - - - - -
SSTL2_II - - - - - - - - - - - -
HSUL_12 0b1000000 0b0100000 - 0b00111 0b11111 0b00001 0b00010 - - - - -
HSTL_I_12 0b1010100 0b0100100 - 0b11011 0b11111 0b00001 0b00001 - - - - -
HSTL_I 0b0101000 0b0011100 - 0b11100 0b11111 0b00010 0b00001 - - - - -
HSTL_II 0b1010110 0b0111000 - 0b01000 0b11111 0b00001 0b00001 - - - - -
HSTL_III - - - - - - - - - - - -
HSTL_IV - - - - - - - - - - - -
HSTL_I_18 0b0100000 0b0011100 - 0b00111 0b11111 0b00001 0b00011 - - - - -
HSTL_II_18 0b1000000 0b0111000 - 0b00100 0b11111 0b00001 0b00010 - - - - -
HSTL_III_18 - - - - - - - - - - - -
HSTL_IV_18 - - - - - - - - - - - -
GTL_DCI - - - - - - - - - - - -
GTLP_DCI - - - - - - - - - - - -
SSTL12_DCI 0b1011000 0b0101000 - 0b11010 0b11111 0b00011 0b00011 - - - - 0b001
SSTL12_T_DCI 0b1011000 0b0101000 - 0b11010 0b11111 0b00011 0b00011 - - - - 0b001
SSTL135_DCI 0b1000100 0b0101000 - 0b11110 0b11111 0b00011 0b00011 - - - - 0b001
SSTL135_T_DCI 0b1000100 0b0101000 - 0b11110 0b11111 0b00011 0b00011 - - - - 0b001
SSTL15_DCI 0b0110000 0b0100100 - 0b11111 0b11010 0b00011 0b00111 - - - - 0b001
SSTL15_T_DCI 0b0110000 0b0100100 - 0b11111 0b11010 0b00011 0b00111 - - - - 0b001
SSTL18_I_DCI 0b0010100 0b0010100 - 0b00101 0b11111 0b00011 0b00111 - - - - 0b001
SSTL18_II_DCI 0b0101100 0b0100000 - 0b00111 0b11100 0b00011 0b00101 - - - - 0b001
SSTL18_II_T_DCI 0b0010100 0b0010100 - 0b00101 0b11111 0b00011 0b00111 - - - - 0b001
SSTL2_I_DCI - - - - - - - - - - - -
SSTL2_II_DCI - - - - - - - - - - - -
SSTL2_II_T_DCI - - - - - - - - - - - -
HSTL_I_DCI 0b0101000 0b0011100 - 0b11100 0b11111 0b00010 0b00001 - - - - 0b001
HSTL_II_DCI 0b1010010 0b0111000 - 0b01000 0b11111 0b00001 0b00001 - - - - 0b001
HSTL_II_T_DCI 0b0101000 0b0011100 - 0b11100 0b11111 0b00010 0b00001 - - - - 0b001
HSTL_III_DCI - - - - - - - - - - - -
HSTL_IV_DCI - - - - - - - - - - - -
HSTL_I_DCI_18 0b0100000 0b0011100 - 0b00111 0b11111 0b00001 0b00011 - - - - 0b001
HSTL_II_DCI_18 0b1000000 0b0111000 - 0b00100 0b11111 0b00001 0b00010 - - - - 0b001
HSTL_II_T_DCI_18 0b0100000 0b0011100 - 0b00111 0b11111 0b00001 0b00011 - - - - 0b001
HSTL_III_DCI_18 - - - - - - - - - - - -
HSTL_IV_DCI_18 - - - - - - - - - - - -
BLVDS_25 - - - - - - - - - - - -
LVPECL_25 - - - - - - - - - - - -
LVDS_25_DCI - - - - - - - - - - - -
LVDSEXT_25_DCI - - - - - - - - - - - -

Table LVDS_DATA

virtex7 table LVDS_DATA
Row OUTPUT_T OUTPUT_C TERM_T TERM_C DYN_TERM_T DYN_TERM_C LVDSBIAS
OFF 0b000000000 0b000000000 - - - - 0b000000000000000000
LVDS 0b110000000 0b001110111 0b000000000 0b101110111 0b000000001 0b101110111 0b110000000000000010

Tables — HR IO

Table IOB_DATA_HR

virtex7 table IOB_DATA_HR
Row PDRIVE NDRIVE PSLEW_SLOW NSLEW_SLOW PSLEW_FAST NSLEW_FAST OUTPUT_MISC
OFF 0b000 0b0000 - - 0b010 0b010 0b00
LVTTL_4 0b001 0b0001 0b100 0b100 0b010 0b010 0b01
LVTTL_8 0b010 0b0010 0b100 0b100 0b010 0b010 0b01
LVTTL_12 0b010 0b0010 0b100 0b100 0b010 0b010 0b01
LVTTL_16 0b011 0b0011 0b100 0b100 0b010 0b010 0b01
LVTTL_24 0b110 0b0110 0b100 0b100 0b010 0b010 0b01
LVCMOS33_4 0b001 0b0001 0b100 0b100 0b010 0b010 0b01
LVCMOS33_8 0b010 0b0010 0b100 0b100 0b010 0b010 0b01
LVCMOS33_12 0b011 0b0011 0b100 0b100 0b010 0b010 0b01
LVCMOS33_16 0b101 0b0101 0b100 0b100 0b010 0b010 0b01
LVCMOS25_4 0b001 0b0001 0b100 0b100 0b010 0b010 0b10
LVCMOS25_8 0b100 0b0010 0b100 0b100 0b010 0b010 0b10
LVCMOS25_12 0b100 0b0011 0b100 0b100 0b010 0b010 0b10
LVCMOS25_16 0b110 0b0101 0b100 0b100 0b010 0b010 0b10
LVCMOS18_4 0b001 0b0001 0b100 0b100 0b010 0b010 0b10
LVCMOS18_8 0b010 0b0010 0b100 0b100 0b010 0b010 0b10
LVCMOS18_12 0b010 0b0010 0b100 0b100 0b010 0b010 0b10
LVCMOS18_16 0b011 0b0011 0b100 0b100 0b010 0b010 0b10
LVCMOS18_24 0b110 0b0110 0b100 0b100 0b010 0b010 0b10
LVCMOS15_4 0b001 0b0001 0b100 0b100 0b010 0b010 0b10
LVCMOS15_8 0b011 0b0010 0b100 0b100 0b010 0b010 0b10
LVCMOS15_12 0b101 0b0011 0b100 0b100 0b010 0b010 0b10
LVCMOS15_16 0b111 0b0101 0b100 0b100 0b010 0b010 0b10
LVCMOS12_4 0b010 0b0001 0b100 0b100 0b010 0b010 0b10
LVCMOS12_8 0b100 0b0010 0b100 0b100 0b010 0b010 0b10
LVCMOS12_12 0b111 0b0011 0b100 0b100 0b010 0b010 0b10
PCI33_3 0b111 0b1111 - - 0b001 0b001 0b11
MOBILE_DDR 0b010 0b0010 0b100 0b100 0b010 0b010 0b10
SSTL135 0b111 0b0100 0b100 0b100 0b111 0b101 0b10
SSTL135_R 0b100 0b0010 0b100 0b100 0b111 0b101 0b10
SSTL15 0b111 0b0101 0b100 0b100 0b111 0b101 0b10
SSTL15_R 0b011 0b0010 0b100 0b100 0b111 0b101 0b10
SSTL18_I 0b010 0b0010 0b100 0b100 0b111 0b111 0b10
SSTL18_II 0b110 0b0101 0b100 0b100 0b111 0b111 0b10
HSTL_I 0b011 0b0010 0b100 0b100 0b111 0b011 0b10
HSTL_II 0b110 0b0100 0b100 0b100 0b111 0b011 0b10
HSTL_I_18 0b011 0b0011 0b100 0b100 0b111 0b011 0b10
HSTL_II_18 0b111 0b0110 0b100 0b100 0b111 0b111 0b10
HSUL_12 0b111 0b0011 0b100 0b100 0b111 0b101 0b10
BLVDS_25 0b110 0b0101 - - 0b010 0b010 0b10

Table LVDS_DATA_HR

virtex7 table LVDS_DATA_HR
Row OUTPUT_T OUTPUT_C TERM_T TERM_C LVDSBIAS_COMMON LVDSBIAS_GROUP
OFF 0b0000000000000 0b0000000000000 - - 0b000000000 0b0000000000000000
LVDS_25 0b1010110000111 0b0000000000000 0b0010010000000 0b0000000000000 0b011010101 0b1101111001111111
MINI_LVDS_25 0b1010110000000 0b0000000000000 0b0010010000000 0b0000000000000 0b011010101 0b1101111001111111
RSDS_25 0b1010010000000 0b0000000000000 0b0010010000000 0b0000000000000 0b011010101 0b1101111001111111
PPDS_25 0b1010010000000 0b0000000000000 0b0010010000000 0b0000000000000 0b011010101 0b1001111000110111
TMDS_33 0b0100000000000 0b0000000000000 - - 0b011010101 0b1110100100000000

Table DRIVERBIAS

virtex7 table DRIVERBIAS
Row DRIVERBIAS
OFF 0b0000000000000000
_3V3 0b0000000000000000
_2V5 0b0000000000000000
_1V8 0b1100000000010001
_1V5 0b1100000000010001
_1V35 0b1100000000010001
_1V2 0b1100000000010001