Input/Output

I/O banks and special functions

Virtex 7 devices have a regular I/O bank structure. There are up to two I/O columns in the device: the left I/O column and the right I/O column. They contain one I/O bank per region (with the exception of regions that are covered up by the PS or GT holes).

There are two genders of I/O banks:

  • HP (high performance) banks, with 1.8V maximum voltage and DCI support
  • HR (high range) banks, with 3.3V maximum voltage and no DCI

In both cases, banks are 50 rows high. They have the following structure:

  • row 0: contains a IO_HP_BOT or IO_HR_BOT tile with a single unpaired IOB
  • rows 1-2, 3-4, 5-6, 7-8, ..., 45-46, 47-48: contain IO_HP_PAIR or IO_HR_PAIR tiles, which are two rows high and contain two IOBs each, forming a differential pair; IOB0 is located in the bottom (odd) row and is the "complemented" pin of the pair, while IOB1 is in the top (even) row and is the "true" pin of the pair
  • row 49: contains another IO_HP_TOP or IO_HR_TOP tile
  • HCLK row: contains an HCLK_IO_HP or HCLK_IO_HR tile with common bank circuitry

The single IOB in row 0 is the VRP pin for DCI. The single IOB in row 49 is VRN pin.

The IOB1 pads in rows 24 and 26 are considered "multi-region clock capable", and have dedicated routing to BUFIO and BUFR of this region and the two adjacent ones. The IOB1 pads in rows 22 and 28 are considered "single-region clock capable", and can drive BUFIO and BUFR only within their own region.

The IOB0 pads in rows 11 and 37 can be used as VREF.

The IOB1 pads in rows 8, 20, 32, 44 can be used as DQS for byte groups. The byte groups are:

  • rows 1-12: byte group with DQS in row 8
  • rows 13-24: byte group with DQS in row 20
  • rows 25-36: byte group with DQS in row 32
  • rows 37-48: byte group with DQS in row 44

The banks are numbered as follows, where c is the region with the CFG tile (for multi-die packages, the CFG tile of the primary device):

  • the bank in left column region c + i is 14 + i
  • the bank in right column region c + i is 34 + i

In case of multi-die packages, this numbering continues across devices within the package.

In parallel or SPI configuration modes, some I/O pads in banks 14 and 15 are borrowed for configuration use:

  • bank 14 row 1: A[0]/D[16]
  • bank 14 row 2: A[1]/D[17]
  • bank 14 row 3: A[2]/D[18]
  • bank 14 row 4: A[3]/D[19]
  • bank 14 row 5: A[4]/D[20]
  • bank 14 row 6: A[5]/D[21]
  • bank 14 row 7: A[6]/D[22]
  • bank 14 row 9: A[7]/D[23]
  • bank 14 row 10: A[8]/D[24]
  • bank 14 row 11: A[9]/D[25]
  • bank 14 row 12: A[10]/D[26]
  • bank 14 row 13: A[11]/D[27]
  • bank 14 row 14: A[12]/D[28]
  • bank 14 row 15: A[13]/D[29]
  • bank 14 row 16: A[14]/D[30]
  • bank 14 row 17: A[15]/D[31]
  • bank 14 row 18: CSI_B
  • bank 14 row 19: DOUT/CSO_B
  • bank 14 row 20: RDWR_B
  • bank 14 row 29: D[15]
  • bank 14 row 30: D[14]
  • bank 14 row 31: D[13]
  • bank 14 row 33: D[12]
  • bank 14 row 34: D[11]
  • bank 14 row 36: D[10]
  • bank 14 row 36: D[9]
  • bank 14 row 37: D[8]
  • bank 14 row 38: FCS_B
  • bank 14 row 39: D[7]
  • bank 14 row 40: D[6]
  • bank 14 row 41: D[5]
  • bank 14 row 42: D[4]
  • bank 14 row 43: EM_CCLK
  • bank 14 row 44: PUDC_B
  • bank 14 row 45: D[3]
  • bank 14 row 46: D[2]
  • bank 14 row 47: D[1]/DIN
  • bank 14 row 48: D[0]/MOSI
  • bank 15 row 1: RS[0]
  • bank 15 row 2: RS[1]
  • bank 15 row 3: FWE_B
  • bank 15 row 4: FOE_B
  • bank 15 row 5: A[16]
  • bank 15 row 6: A[17]
  • bank 15 row 7: A[18]
  • bank 15 row 9: A[19]
  • bank 15 row 10: A[20]
  • bank 15 row 11: A[21]
  • bank 15 row 12: A[22]
  • bank 15 row 13: A[23]
  • bank 15 row 14: A[24]
  • bank 15 row 15: A[25]
  • bank 15 row 16: A[26]
  • bank 15 row 17: A[27]
  • bank 15 row 18: A[28]
  • bank 15 row 19: ADV_B

The devices with Processing System are not configured by normal means, so the above list is inapplicable. Furthermore, they do not have banks 14 and 15 at all — the place they would occupy is taken up by the PS itself. They do, however, have a special pin in bank 34 instead:

  • bank 34 row 44: PUDC_B

TODO: really, Wanda, how surprised would you be if it turned out that they are configurable by normal means by just substituting banks 34+35 and poking at the reserved mode pins that definitely aren't M0/M1/M2?

The XADC, if present on the device, can use up to 16 IOB pairs as auxiliary analog differential inputs. The VPx input corresponds to IOB1 and VNx corresponds to IOB0 within the same tile. Depending on device banks present on the device, there are three different arrangements possible:

  • variant LR, used for devices that have both bank 15 and 35
  • variant L, used for devices without bank 35
  • variant R, used for devices without bank 15 (that is, devices with Processing System)

The IOBs for variant LR are:

  • VP0/VN0: bank 15 rows 47-48
  • VP1/VN1: bank 15 rows 43-44
  • VP2/VN2: bank 15 rows 35-36
  • VP3/VN3: bank 15 rows 31-32
  • VP4/VN4: bank 35 rows 47-48
  • VP5/VN5: bank 35 rows 43-44
  • VP6/VN6: bank 35 rows 35-31
  • VP7/VN7: bank 35 rows 31-32
  • VP8/VN8: bank 15 rows 45-46
  • VP9/VN9: bank 15 rows 39-40
  • VP10/VN10: bank 15 rows 33-34
  • VP11/VN11: bank 15 rows 29-30
  • VP12/VN12: bank 35 rows 45-46
  • VP13/VN13: bank 35 rows 39-40
  • VP14/VN14: bank 35 rows 33-34
  • VP15/VN15: bank 35 rows 29-30

The IOBs for variant L are:

  • VP0/VN0: bank 15 rows 47-48
  • VP1/VN1: bank 15 rows 43-44
  • VP2/VN2: bank 15 rows 39-40
  • VP3/VN3: bank 15 rows 33-34
  • VP4/VN4: bank 15 rows 29-30
  • VP5/VN5: bank 15 rows 25-26
  • VP6/VN6: unconnected
  • VP7/VN7: unconnected
  • VP8/VN8: bank 15 rows 45-46
  • VP9/VN9: bank 15 rows 41-42
  • VP10/VN10: bank 15 rows 35-36
  • VP11/VN11: bank 15 rows 31-32
  • VP12/VN12: bank 15 rows 27-28
  • VP13/VN13: unconnected
  • VP14/VN14: unconnected
  • VP15/VN15: unconnected

The IOBs for variant R are:

  • VP0/VN0: bank 35 rows 47-48
  • VP1/VN1: bank 35 rows 43-44
  • VP2/VN2: bank 35 rows 35-36
  • VP3/VN3: bank 35 rows 31-32
  • VP4/VN4: bank 35 rows 21-22
  • VP5/VN5: bank 35 rows 15-16
  • VP6/VN6: bank 35 rows 9-10
  • VP7/VN7: bank 35 rows 5-6
  • VP8/VN8: bank 35 rows 45-46
  • VP9/VN9: bank 35 rows 39-40
  • VP10/VN10: bank 35 rows 33-34
  • VP11/VN11: bank 35 rows 29-30
  • VP12/VN12: bank 35 rows 19-20
  • VP13/VN13: bank 35 rows 13-14
  • VP14/VN14: bank 35 rows 7-8
  • VP15/VN15: bank 35 rows 1-2

The devices also have dedicated configuration bank 0, which has no user I/O and is located in the CFG tile. It has the following pins:

  • CCLK
  • CFGBVS
  • DONE
  • INIT_B
  • M0, M1, M2
  • PROGRAM_B
  • TCK, TDI, TDO, TMS

Bitstream — IO_HP_PAIR

virtex7 IO_HP_PAIR bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.OCLK1 - - - - - - - - - IOB0:DCI_T
62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:D_EMU1 ILOGIC0:MUX.CLK[1] ILOGIC0:MUX.CLKB[1] - - - - - - - IOB0:DCITERMDISABLE_SEL[0] -
61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[0] ILOGIC0:D_EMU2 - ILOGIC0:MUX.CLKB[0] - OLOGIC0:TMUX[0] - - - - - IOB0:PDRIVE[0]
60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:SRTYPE[0] ILOGIC0:MUX.CLK[2] ILOGIC0:MUX.CLKB[2] ~OLOGIC0:INV.T1 OLOGIC0:TMUX[4] - - - - - IOB0:OUTPUT_MISC[1] -
59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TMUX[3] - - - - - IOB0:VREF_SYSMON
58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY0:FINEDELAY[0] - - - OLOGIC0:TMUX[1] - IDELAY0:DELAY_SRC[1] - - - IOB0:OUTPUT_MISC[0] -
57 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_SR_USED - - - - - - OLOGIC0:TMUX[2] - IDELAY0:DELAY_SRC[3] - ODELAY0:DELAY_SRC[2] - IOB0:OUTPUT_MISC[3]
56 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF_LATCH ~ILOGIC0:IFF1_SRVAL - - ~OLOGIC0:INV.T2 - - IDELAY0:DELAY_SRC[2] - ODELAY0:DELAY_SRC[1] - IOB0:DCIUPDATEMODE_QUIET -
55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF1_INIT - - IDELAY0:INV.IDATAIN OLOGIC0:TFF_SR_SYNC ~ODELAY0:INV.ODATAIN IDELAY0:DELAY_SRC[0] - ODELAY0:DELAY_SRC[0] - IOB0:NDRIVE[2]
54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:SERDES IDELAY0:ENABLE - ODELAY0:ENABLE - - IOB0:LVDS[7] -
53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[3] - - ILOGIC0:MUX.CLKB[3] - - - - - - - IOB0:DCI_MODE[1]
52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF2_SRVAL ILOGIC0:MUX.CLK[8] ILOGIC0:MUX.CLKB[8] ~OLOGIC0:TFF_INIT ~OLOGIC0:TFF_SRVAL[1] - - - - - IOB0:OUTPUT_DELAY -
51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[9] ~ILOGIC0:IFF2_INIT ~OLOGIC0:INV.T3 ILOGIC0:MUX.CLKB[9] - - - - - - - IOB0:NDRIVE[0]
50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[10] ILOGIC0:MUX.CLKB[10] - - - - - - - IOB0:PSLEW[0] -
49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[6] - - ILOGIC0:MUX.CLKB[6] - - - - - - - ~IOB0:PDRIVE[3]
48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[4] ILOGIC0:MUX.CLKB[4] ~OLOGIC0:INV.T4 - - - - - - ~IOB0:PDRIVE[2] -
47 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:NUM_CE[0] - ILOGIC0:MUX.CLK[7] - - ILOGIC0:MUX.CLKB[7] - OLOGIC0:TBYTE_CTL - - - - - ~IOB0:NDRIVE[3]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[5] ILOGIC0:MUX.CLKB[5] - ~OLOGIC0:TFF_SRVAL[0] - IDELAY0:INV.DATAIN - - - IOB0:NSLEW[0] -
45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[1] - - OLOGIC0:MUX.CLKB[1] - ~OLOGIC0:TFF_SRVAL[2] - - - - - IOB0:NSLEW[1]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[0] OLOGIC0:MUX.CLKB[0] - OLOGIC0:SERDES_MODE[0] - - - - - IOB0:PDRIVE[4] -
43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[2] - - OLOGIC0:MUX.CLKB[2] - OLOGIC0:TBYTE_SRC - - - - - IOB0:OMUX[0]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF3_SRVAL - - OLOGIC0:INV.CLKDIV - - - - - - IOB0:DCI_MODE[0] -
41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF3_INIT ~OLOGIC0:RANK3_USED - - - - - - - - IOB0:LVDS[8]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB0:LVDS[6] -
39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[3] - - OLOGIC0:MUX.CLKB[3] - - - IDELAY0:INV.C - ODELAY0:INV.C - IOB0:IBUFDISABLE_SEL[0]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[8] OLOGIC0:MUX.CLKB[8] - OLOGIC0:TFF_SR_USED - IDELAY0:CINVCTRL_SEL - ODELAY0:CINVCTRL_SEL - IOB0:NSLEW[2] -
37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~OLOGIC0:INV.CLK1 - - OLOGIC0:TRISTATE_WIDTH[0] - - - - - IOB0:LVDS[5]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:OMUX[2] - - - - - IOB0:DQS_BIAS_N -
35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[9] - ~OLOGIC0:INV.CLK2 OLOGIC0:MUX.CLKB[9] - - - - - - - IOB0:NDRIVE[4]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF4_SRVAL OLOGIC0:MUX.CLK[10] OLOGIC0:MUX.CLKB[10] - OLOGIC0:OMUX[1] - - - - - IOB0:OUTPUT_ENABLE[1] -
33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[6] ~ILOGIC0:IFF4_INIT OLOGIC0:INV.CLKDIVF OLOGIC0:MUX.CLKB[6] - OLOGIC0:OFF_SR_SYNC - ~IDELAY0:IDELAY_VALUE_CUR[4] - ~ODELAY0:ODELAY_VALUE_CUR[4] - ~IOB0:PDRIVE[5]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[4] OLOGIC0:MUX.CLKB[4] OLOGIC0:CLK_RATIO[1] ~OLOGIC0:OFF_SRVAL[1] - - - - - IOB0:OUTPUT_ENABLE[0] -
31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[7] - OLOGIC0:SELFHEAL OLOGIC0:MUX.CLKB[7] - - - IDELAY0:IDELAY_VALUE_INIT[4] - ODELAY0:ODELAY_VALUE_INIT[4] - IOB0:PDRIVE[1]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[5] OLOGIC0:MUX.CLKB[5] OLOGIC0:INV.D1 ~OLOGIC0:OFF_INIT - - - - - IOB0:PSLEW[1] -
29 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DDR_CLK_EDGE[0] - ILOGIC0:MUX.CLKDIVP[0] - OLOGIC0:CLK_RATIO[2] - - - - - - - - IOB0:DQS_BIAS_P
28 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DDR_CLK_EDGE[1] - ILOGIC0:MUX.CLKDIVP[1] - OLOGIC0:CLK_RATIO[0] - - - - - - IOB0:LVDS[4] -
27 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:RANK23_DLY - - - OLOGIC0:CLK_RATIO[3] - - - - ~IDELAY0:IDELAY_VALUE_CUR[3] - ~ODELAY0:ODELAY_VALUE_CUR[3] - IOB0:NDRIVE[1]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[1] ILOGIC0:I_DELAY_ENABLE - - OLOGIC0:DATA_WIDTH[8] - - - - - - IOB0:PSLEW[2] -
25 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:SERDES - - - OLOGIC0:INV.D2 - - - - IDELAY0:IDELAY_VALUE_INIT[3] - ODELAY0:ODELAY_VALUE_INIT[3] - IOB0:LVDS[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:I_TSBYPASS_ENABLE - - - - - - - - - ~IOB0:NDRIVE[5] -
23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB0:PDRIVE[6]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ODELAY0:FINEDELAY[0] - IOB0:NSLEW[3] -
21 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:SERDES_MODE[0] - - - OLOGIC0:INV.D3 - - - - IDELAY0:PIPE_SEL - ODELAY0:PIPE_SEL - IOB0:LVDS[2]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:BITSLIP_ENABLE - - - - ~OLOGIC0:OFF_SRVAL[0] - - - - - IOB0:NDRIVE[6] -
19 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_RATE[0] - - - - - - ~OLOGIC0:OFF_SRVAL[2] - ~IDELAY0:IDELAY_VALUE_CUR[2] - ~ODELAY0:ODELAY_VALUE_CUR[2] - IOB0:OUTPUT_MISC[5]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[3] ~ILOGIC0:INV.D - - - - IDELAY0:HIGH_PERFORMANCE_MODE - ODELAY0:HIGH_PERFORMANCE_MODE - - - -
17 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[2] - OLOGIC0:MUX.CLKDIV[1] ILOGIC0:TSBYPASS_MUX[0] OLOGIC0:INV.D4 OLOGIC0:MUX.CLKDIVB[1] - OLOGIC0:OMUX[4] - IDELAY0:IDELAY_VALUE_INIT[2] - ODELAY0:ODELAY_VALUE_INIT[2] - IOB0:TMUX[0]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[1] - OLOGIC0:MUX.CLKDIV[0] OLOGIC0:MUX.CLKDIVB[0] OLOGIC0:MISR_ENABLE OLOGIC0:OMUX[0] - - - - - IOB0:PSLEW[3] -
15 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[0] - - - OLOGIC0:MISR_CLK_SELECT[0] - - OLOGIC0:OFF_SR_USED - - - - - IOB0:LVDS[1]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[3] ILOGIC0:IFF_TSBYPASS_ENABLE - - OLOGIC0:INV.D5 OLOGIC0:OMUX[3] - IDELAY0:IDELAY_TYPE[1] - ODELAY0:ODELAY_TYPE[1] - IOB0:NSLEW[4] -
13 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.CLKDIVP - - - OLOGIC0:INV.D6 - - - - ~IDELAY0:IDELAY_VALUE_CUR[1] - ~ODELAY0:ODELAY_VALUE_CUR[1] - IOB0:PSLEW[4]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[4] - - - OLOGIC0:DATA_WIDTH[7] - - - - - - IOB0:PULL[0] -
11 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLKDIVP_INV_EN - - ILOGIC0:IFF_DELAY_ENABLE OLOGIC0:DATA_WIDTH[6] - - - - IDELAY0:IDELAY_VALUE_INIT[1] - ODELAY0:ODELAY_VALUE_INIT[1] - IOB0:OUTPUT_MISC[4]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[2] - - - OLOGIC0:MISR_ENABLE_FDBK - - - - - - IOB0:PULL[1] -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLKDIV_INV_EN - OLOGIC0:MUX.CLKDIVF[4] - OLOGIC0:INV.D7 OLOGIC0:MUX.CLKDIVFB[4] - - - - - - - IOB0:OUTPUT_MISC[2]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.CLKDIV - OLOGIC0:MUX.CLKDIVF[5] OLOGIC0:MUX.CLKDIVFB[5] OLOGIC0:MISR_RESET - - IDELAY0:IDELAY_TYPE[0] - ODELAY0:ODELAY_TYPE[0] - IOB0:LVDS[0] -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:DATA_WIDTH[4] - - - - ~IDELAY0:IDELAY_VALUE_CUR[0] - ~ODELAY0:ODELAY_VALUE_CUR[0] - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[0] - OLOGIC0:MUX.CLKDIVF[6] OLOGIC0:MUX.CLKDIVFB[6] OLOGIC0:DATA_WIDTH[3] - - - - - - IOB0:PULL_DYNAMIC -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MISR_CLK_SELECT[1] - - - - IDELAY0:IDELAY_VALUE_INIT[0] - ODELAY0:ODELAY_VALUE_INIT[0] - IOB0:INPUT_MISC
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INV.CLK[1] OLOGIC0:MUX.CLKDIVF[2] OLOGIC0:MUX.CLKDIVFB[2] OLOGIC0:DATA_WIDTH[5] - - - - - - IOB0:PULL[2] -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLKDIVF[0] ILOGIC0:INV.OCLK2 OLOGIC0:DATA_WIDTH[2] OLOGIC0:MUX.CLKDIVFB[0] - - - - - - - IOB0:IBUF_MODE[3]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INV.CLK[0] OLOGIC0:MUX.CLKDIVF[3] OLOGIC0:MUX.CLKDIVFB[3] OLOGIC0:INV.D8 - - - - - - IOB0:IBUF_MODE[2] -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLKDIVF[1] ~ILOGIC0:INV.CLK[2] OLOGIC0:DATA_WIDTH[1] OLOGIC0:MUX.CLKDIVFB[1] - - - - - - - IOB0:IBUF_MODE[1]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLK_INV_EN - - OLOGIC0:DATA_WIDTH[0] - - - - - - IOB0:IBUF_MODE[0] -
virtex7 IO_HP_PAIR bittile 1
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DYN_CLK_INV_EN OLOGIC1:DATA_WIDTH[0] - - - - - - - - IOB1:IBUF_MODE[0]
62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INV.CLK[0] OLOGIC1:MUX.CLKDIVF[1] OLOGIC1:MUX.CLKDIVFB[1] OLOGIC1:DATA_WIDTH[1] - - - - - - IOB1:IBUF_MODE[1] -
61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLKDIVF[3] ~ILOGIC1:INV.CLK[2] OLOGIC1:INV.D8 OLOGIC1:MUX.CLKDIVFB[3] - - - - - - - IOB1:IBUF_MODE[2]
60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INV.OCLK2 OLOGIC1:MUX.CLKDIVF[0] OLOGIC1:MUX.CLKDIVFB[0] OLOGIC1:DATA_WIDTH[2] - - - - - - IOB1:IBUF_MODE[3] -
59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLKDIVF[2] ~ILOGIC1:INV.CLK[1] OLOGIC1:DATA_WIDTH[5] OLOGIC1:MUX.CLKDIVFB[2] - - - - - - - IOB1:PULL[2]
58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MISR_CLK_SELECT[1] - - IDELAY1:IDELAY_VALUE_INIT[0] - ODELAY1:ODELAY_VALUE_INIT[0] - IOB1:INPUT_MISC -
57 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INTERFACE_TYPE[0] - OLOGIC1:MUX.CLKDIVF[6] - OLOGIC1:DATA_WIDTH[3] OLOGIC1:MUX.CLKDIVFB[6] - - - - - - - IOB1:PULL_DYNAMIC
56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:DATA_WIDTH[4] - - ~IDELAY1:IDELAY_VALUE_CUR[0] - ~ODELAY1:ODELAY_VALUE_CUR[0] - - -
55 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INV.CLKDIV - OLOGIC1:MUX.CLKDIVF[5] - OLOGIC1:MISR_RESET OLOGIC1:MUX.CLKDIVFB[5] - - - IDELAY1:IDELAY_TYPE[0] - ODELAY1:ODELAY_TYPE[0] - IOB1:LVDS[0]
54 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DYN_CLKDIV_INV_EN - OLOGIC1:MUX.CLKDIVF[4] OLOGIC1:MUX.CLKDIVFB[4] OLOGIC1:INV.D7 - - - - - - IOB1:OUTPUT_MISC[2] -
53 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INTERFACE_TYPE[2] - - - OLOGIC1:MISR_ENABLE_FDBK - - - - - - - - IOB1:PULL[1]
52 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DYN_CLKDIVP_INV_EN ILOGIC1:IFF_DELAY_ENABLE - - OLOGIC1:DATA_WIDTH[6] - - IDELAY1:IDELAY_VALUE_INIT[1] - ODELAY1:ODELAY_VALUE_INIT[1] - IOB1:OUTPUT_MISC[4] -
51 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INTERFACE_TYPE[4] - - - OLOGIC1:DATA_WIDTH[7] - - - - - - - - IOB1:PULL[0]
50 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INV.CLKDIVP - - - OLOGIC1:INV.D6 - - ~IDELAY1:IDELAY_VALUE_CUR[1] - ~ODELAY1:ODELAY_VALUE_CUR[1] - IOB1:PSLEW[4] -
49 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INTERFACE_TYPE[3] - - ILOGIC1:IFF_TSBYPASS_ENABLE OLOGIC1:INV.D5 - - OLOGIC1:OMUX[3] - IDELAY1:IDELAY_TYPE[1] - ODELAY1:ODELAY_TYPE[1] - IOB1:NSLEW[4]
48 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DATA_WIDTH[0] - - - OLOGIC1:MISR_CLK_SELECT[0] OLOGIC1:OFF_SR_USED - - - - - IOB1:LVDS[1] -
47 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DATA_WIDTH[1] - OLOGIC1:MUX.CLKDIV[0] - OLOGIC1:MISR_ENABLE OLOGIC1:MUX.CLKDIVB[0] - OLOGIC1:OMUX[0] - - - - - IOB1:PSLEW[3]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DATA_WIDTH[2] ILOGIC1:TSBYPASS_MUX[0] OLOGIC1:MUX.CLKDIV[1] OLOGIC1:MUX.CLKDIVB[1] OLOGIC1:INV.D4 OLOGIC1:OMUX[4] - IDELAY1:IDELAY_VALUE_INIT[2] - ODELAY1:ODELAY_VALUE_INIT[2] - - -
45 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DATA_WIDTH[3] - - ~ILOGIC1:INV.D - - IDELAY1:HIGH_PERFORMANCE_MODE - ODELAY1:HIGH_PERFORMANCE_MODE - - - - -
44 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DATA_RATE[0] - - - - ~OLOGIC1:OFF_SRVAL[0] - ~IDELAY1:IDELAY_VALUE_CUR[2] - ~ODELAY1:ODELAY_VALUE_CUR[2] - IOB1:OUTPUT_MISC[5] -
43 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:BITSLIP_ENABLE - - - - - - ~OLOGIC1:OFF_SRVAL[2] - - - - - IOB1:NDRIVE[6]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:SERDES_MODE[0] - - - OLOGIC1:INV.D3 - - IDELAY1:PIPE_SEL - ODELAY1:PIPE_SEL - IOB1:LVDS[2] -
41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ODELAY1:FINEDELAY[0] - IOB1:NSLEW[3]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB1:PDRIVE[6] -
39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:I_TSBYPASS_ENABLE - - - - - - - - - ~IOB1:NDRIVE[5]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:SERDES - - - OLOGIC1:INV.D2 - - IDELAY1:IDELAY_VALUE_INIT[3] - ODELAY1:ODELAY_VALUE_INIT[3] - IOB1:LVDS[3] -
37 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INTERFACE_TYPE[1] - - ILOGIC1:I_DELAY_ENABLE OLOGIC1:DATA_WIDTH[8] - - - - - - - - IOB1:PSLEW[2]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:RANK23_DLY - - - OLOGIC1:CLK_RATIO[3] - - ~IDELAY1:IDELAY_VALUE_CUR[3] - ~ODELAY1:ODELAY_VALUE_CUR[3] - IOB1:NDRIVE[1] -
35 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DDR_CLK_EDGE[1] - ILOGIC1:MUX.CLKDIVP[1] - OLOGIC1:CLK_RATIO[0] - - - - - - - - IOB1:LVDS[4]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DDR_CLK_EDGE[0] - ILOGIC1:MUX.CLKDIVP[0] - OLOGIC1:CLK_RATIO[2] - - - - - - IOB1:DQS_BIAS_P -
33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[5] - OLOGIC1:INV.D1 OLOGIC1:MUX.CLKB[5] - ~OLOGIC1:OFF_INIT - - - - - IOB1:PSLEW[1]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[7] OLOGIC1:MUX.CLKB[7] OLOGIC1:SELFHEAL - - IDELAY1:IDELAY_VALUE_INIT[4] - ODELAY1:ODELAY_VALUE_INIT[4] - IOB1:PDRIVE[1] -
31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[4] - OLOGIC1:CLK_RATIO[1] OLOGIC1:MUX.CLKB[4] - ~OLOGIC1:OFF_SRVAL[1] - - - - - IOB1:OUTPUT_ENABLE[1]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF4_INIT OLOGIC1:MUX.CLK[6] OLOGIC1:MUX.CLKB[6] OLOGIC1:INV.CLKDIVF OLOGIC1:OFF_SR_SYNC - ~IDELAY1:IDELAY_VALUE_CUR[4] - ~ODELAY1:ODELAY_VALUE_CUR[4] - ~IOB1:PDRIVE[5] -
29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[10] ~ILOGIC1:IFF4_SRVAL - OLOGIC1:MUX.CLKB[10] - OLOGIC1:OMUX[1] - - - - - IOB1:OUTPUT_ENABLE[0]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[9] OLOGIC1:MUX.CLKB[9] ~OLOGIC1:INV.CLK2 - - - - - - IOB1:NDRIVE[4] -
27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:OMUX[2] - - - - - IOB1:DQS_BIAS_N
26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~OLOGIC1:INV.CLK1 OLOGIC1:TRISTATE_WIDTH[0] - - - - - IOB1:LVDS[5] -
25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[8] - - OLOGIC1:MUX.CLKB[8] - OLOGIC1:TFF_SR_USED - IDELAY1:CINVCTRL_SEL - ODELAY1:CINVCTRL_SEL - IOB1:NSLEW[2]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[3] OLOGIC1:MUX.CLKB[3] - - - IDELAY1:INV.C - ODELAY1:INV.C - IOB1:IBUFDISABLE_SEL[0] -
23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB1:LVDS[6]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF3_INIT - - ~OLOGIC1:RANK3_USED - - - - - - IOB1:LVDS[8] -
21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF3_SRVAL OLOGIC1:INV.CLKDIV - - - - - - - - IOB1:DCI_MODE[0]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[2] OLOGIC1:MUX.CLKB[2] - OLOGIC1:TBYTE_SRC - - - - - - -
19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[0] - - OLOGIC1:MUX.CLKB[0] - OLOGIC1:SERDES_MODE[0] - - - - - IOB1:PDRIVE[4]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[1] OLOGIC1:MUX.CLKB[1] - ~OLOGIC1:TFF_SRVAL[0] - - - - - IOB1:NSLEW[1] -
17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.CLK[5] - - ILOGIC1:MUX.CLKB[5] - ~OLOGIC1:TFF_SRVAL[2] - IDELAY1:INV.DATAIN - - - IOB1:NSLEW[0]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:NUM_CE[0] - ILOGIC1:MUX.CLK[7] ILOGIC1:MUX.CLKB[7] - OLOGIC1:TBYTE_CTL - - - - - ~IOB1:NDRIVE[3] -
15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.CLK[4] - ~OLOGIC1:INV.T4 ILOGIC1:MUX.CLKB[4] - - - - - - - ~IOB1:PDRIVE[2]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.CLK[6] ILOGIC1:MUX.CLKB[6] - - - - - - - ~IOB1:PDRIVE[3] -
13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.CLK[10] - - ILOGIC1:MUX.CLKB[10] - - - - - - - IOB1:PSLEW[0]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF2_INIT ILOGIC1:MUX.CLK[9] ILOGIC1:MUX.CLKB[9] ~OLOGIC1:INV.T3 - - - - - - IOB1:NDRIVE[0] -
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.CLK[8] ~ILOGIC1:IFF2_SRVAL ~OLOGIC1:TFF_INIT ILOGIC1:MUX.CLKB[8] - ~OLOGIC1:TFF_SRVAL[1] - - - - - IOB1:OUTPUT_DELAY
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.CLK[3] ILOGIC1:MUX.CLKB[3] - - - - - - - IOB1:DCI_MODE[1] -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY1:ENABLE OLOGIC1:SERDES ODELAY1:ENABLE - - - - IOB1:LVDS[7]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF1_INIT - - - OLOGIC1:TFF_SR_SYNC IDELAY1:INV.IDATAIN IDELAY1:DELAY_SRC[0] ~ODELAY1:INV.ODATAIN ODELAY1:DELAY_SRC[0] - IOB1:NDRIVE[2] -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF_LATCH - - ~ILOGIC1:IFF1_SRVAL ~OLOGIC1:INV.T2 - - - - IDELAY1:DELAY_SRC[2] - ODELAY1:DELAY_SRC[1] - IOB1:DCIUPDATEMODE_QUIET
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IFF_SR_USED - - - - OLOGIC1:TMUX[2] - IDELAY1:DELAY_SRC[3] - ODELAY1:DELAY_SRC[2] - IOB1:OUTPUT_MISC[3] -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY1:FINEDELAY[0] - - - OLOGIC1:TMUX[1] - IDELAY1:DELAY_SRC[1] - - - IOB1:OUTPUT_MISC[0]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:TMUX[3] - - - - - IOB1:VREF_SYSMON -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.CLK[2] ILOGIC1:SRTYPE[0] ~OLOGIC1:INV.T1 ILOGIC1:MUX.CLKB[2] - OLOGIC1:TMUX[4] - - - - - IOB1:OUTPUT_MISC[1]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:D_EMU2 ILOGIC1:MUX.CLK[0] ILOGIC1:MUX.CLKB[0] - OLOGIC1:TMUX[0] - - - - - IOB1:PDRIVE[0] -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.CLK[1] ILOGIC1:D_EMU1 - ILOGIC1:MUX.CLKB[1] - - - - - - - IOB1:DCITERMDISABLE_SEL[0]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INV.OCLK1 - - - - - - - - - IOB1:DCI_T -
IDELAY0:CINVCTRL_SEL 0.34.38
IDELAY0:ENABLE 0.33.54
IDELAY0:HIGH_PERFORMANCE_MODE 0.33.18
IDELAY0:INV.C 0.35.39
IDELAY0:INV.DATAIN 0.34.46
IDELAY0:INV.IDATAIN 0.32.55
IDELAY0:PIPE_SEL 0.35.21
IDELAY1:CINVCTRL_SEL 1.35.25
IDELAY1:ENABLE 1.32.9
IDELAY1:HIGH_PERFORMANCE_MODE 1.32.45
IDELAY1:INV.C 1.34.24
IDELAY1:INV.DATAIN 1.35.17
IDELAY1:INV.IDATAIN 1.33.8
IDELAY1:PIPE_SEL 1.34.42
ILOGIC0:BITSLIP_ENABLE 0.27.20
ILOGIC0:DYN_CLKDIVP_INV_EN 0.26.11
ILOGIC0:DYN_CLKDIV_INV_EN 0.26.9
ILOGIC0:DYN_CLK_INV_EN 0.28.0
ILOGIC0:D_EMU1 0.28.62
ILOGIC0:D_EMU2 0.29.61
ILOGIC0:IFF_DELAY_ENABLE 0.29.11
ILOGIC0:IFF_SR_USED 0.26.57
ILOGIC0:IFF_TSBYPASS_ENABLE 0.28.14
ILOGIC0:INV.CLKDIV 0.27.8
ILOGIC0:INV.CLKDIVP 0.26.13
ILOGIC0:INV.OCLK1 0.29.63
ILOGIC0:INV.OCLK2 0.29.3
ILOGIC0:I_DELAY_ENABLE 0.28.26
ILOGIC0:I_TSBYPASS_ENABLE 0.28.24
ILOGIC0:RANK23_DLY 0.26.27
ILOGIC0:SERDES 0.26.25
ILOGIC1:BITSLIP_ENABLE 1.26.43
ILOGIC1:DYN_CLKDIVP_INV_EN 1.27.52
ILOGIC1:DYN_CLKDIV_INV_EN 1.27.54
ILOGIC1:DYN_CLK_INV_EN 1.29.63
ILOGIC1:D_EMU1 1.29.1
ILOGIC1:D_EMU2 1.28.2
ILOGIC1:IFF_DELAY_ENABLE 1.28.52
ILOGIC1:IFF_SR_USED 1.27.6
ILOGIC1:IFF_TSBYPASS_ENABLE 1.29.49
ILOGIC1:INV.CLKDIV 1.26.55
ILOGIC1:INV.CLKDIVP 1.27.50
ILOGIC1:INV.OCLK1 1.28.0
ILOGIC1:INV.OCLK2 1.28.60
ILOGIC1:I_DELAY_ENABLE 1.29.37
ILOGIC1:I_TSBYPASS_ENABLE 1.29.39
ILOGIC1:RANK23_DLY 1.27.36
ILOGIC1:SERDES 1.27.38
IOB0:DCIUPDATEMODE_QUIET 0.38.56
IOB0:DCI_T 0.39.63
IOB0:DQS_BIAS_N 0.38.36
IOB0:DQS_BIAS_P 0.39.29
IOB0:INPUT_MISC 0.39.5
IOB0:OUTPUT_DELAY 0.38.52
IOB0:PULL_DYNAMIC 0.38.6
IOB0:VREF_SYSMON 0.39.59
IOB1:DCIUPDATEMODE_QUIET 1.39.7
IOB1:DCI_T 1.38.0
IOB1:DQS_BIAS_N 1.39.27
IOB1:DQS_BIAS_P 1.38.34
IOB1:INPUT_MISC 1.38.58
IOB1:OUTPUT_DELAY 1.39.11
IOB1:PULL_DYNAMIC 1.39.57
IOB1:VREF_SYSMON 1.38.4
ODELAY0:CINVCTRL_SEL 0.36.38
ODELAY0:ENABLE 0.35.54
ODELAY0:HIGH_PERFORMANCE_MODE 0.35.18
ODELAY0:INV.C 0.37.39
ODELAY0:PIPE_SEL 0.37.21
ODELAY1:CINVCTRL_SEL 1.37.25
ODELAY1:ENABLE 1.34.9
ODELAY1:HIGH_PERFORMANCE_MODE 1.34.45
ODELAY1:INV.C 1.36.24
ODELAY1:PIPE_SEL 1.36.42
OLOGIC0:INV.CLKDIV 0.31.42
OLOGIC0:INV.CLKDIVF 0.30.33
OLOGIC0:INV.D1 0.31.30
OLOGIC0:INV.D2 0.30.25
OLOGIC0:INV.D3 0.30.21
OLOGIC0:INV.D4 0.30.17
OLOGIC0:INV.D5 0.31.14
OLOGIC0:INV.D6 0.30.13
OLOGIC0:INV.D7 0.30.9
OLOGIC0:INV.D8 0.31.2
OLOGIC0:MISR_ENABLE 0.31.16
OLOGIC0:MISR_ENABLE_FDBK 0.31.10
OLOGIC0:MISR_RESET 0.31.8
OLOGIC0:OFF_SR_SYNC 0.33.33
OLOGIC0:OFF_SR_USED 0.33.15
OLOGIC0:SELFHEAL 0.30.31
OLOGIC0:SERDES 0.32.54
OLOGIC0:TBYTE_CTL 0.33.47
OLOGIC0:TBYTE_SRC 0.33.43
OLOGIC0:TFF_SR_SYNC 0.33.55
OLOGIC0:TFF_SR_USED 0.32.38
OLOGIC1:INV.CLKDIV 1.30.21
OLOGIC1:INV.CLKDIVF 1.31.30
OLOGIC1:INV.D1 1.30.33
OLOGIC1:INV.D2 1.31.38
OLOGIC1:INV.D3 1.31.42
OLOGIC1:INV.D4 1.31.46
OLOGIC1:INV.D5 1.30.49
OLOGIC1:INV.D6 1.31.50
OLOGIC1:INV.D7 1.31.54
OLOGIC1:INV.D8 1.30.61
OLOGIC1:MISR_ENABLE 1.30.47
OLOGIC1:MISR_ENABLE_FDBK 1.30.53
OLOGIC1:MISR_RESET 1.30.55
OLOGIC1:OFF_SR_SYNC 1.32.30
OLOGIC1:OFF_SR_USED 1.32.48
OLOGIC1:SELFHEAL 1.31.32
OLOGIC1:SERDES 1.33.9
OLOGIC1:TBYTE_CTL 1.32.16
OLOGIC1:TBYTE_SRC 1.32.20
OLOGIC1:TFF_SR_SYNC 1.32.8
OLOGIC1:TFF_SR_USED 1.33.25
non-inverted [0]
IDELAY0:DELAY_SRC 0.35.57 0.34.56 0.34.58 0.35.55
IDELAY1:DELAY_SRC 1.34.6 1.35.7 1.35.5 1.34.8
NONE 0 0 0 0
IDATAIN 0 0 0 1
DATAIN 0 0 1 0
OFB 0 1 0 0
DELAYCHAIN_OSC 1 0 0 0
IDELAY0:FINEDELAY 0.28.58
IDELAY1:FINEDELAY 1.29.5
ODELAY0:FINEDELAY 0.36.22
ODELAY1:FINEDELAY 1.37.41
BYPASS 0
ADD_DLY 1
IDELAY0:IDELAY_TYPE 0.34.14 0.34.8
IDELAY1:IDELAY_TYPE 1.35.49 1.35.55
ODELAY0:ODELAY_TYPE 0.36.14 0.36.8
ODELAY1:ODELAY_TYPE 1.37.49 1.37.55
FIXED 0 0
VARIABLE 0 1
VAR_LOAD 1 1
IDELAY0:IDELAY_VALUE_CUR 0.35.33 0.35.27 0.35.19 0.35.13 0.35.7
IDELAY1:IDELAY_VALUE_CUR 1.34.30 1.34.36 1.34.44 1.34.50 1.34.56
ODELAY0:ODELAY_VALUE_CUR 0.37.33 0.37.27 0.37.19 0.37.13 0.37.7
ODELAY1:ODELAY_VALUE_CUR 1.36.30 1.36.36 1.36.44 1.36.50 1.36.56
inverted ~[4] ~[3] ~[2] ~[1] ~[0]
IDELAY0:IDELAY_VALUE_INIT 0.35.31 0.35.25 0.35.17 0.35.11 0.35.5
IDELAY1:IDELAY_VALUE_INIT 1.34.32 1.34.38 1.34.46 1.34.52 1.34.58
IOB0:NSLEW 0.38.14 0.38.22 0.38.38 0.39.45 0.38.46
IOB0:PSLEW 0.39.13 0.38.16 0.38.26 0.38.30 0.38.50
IOB1:NSLEW 1.39.49 1.39.41 1.39.25 1.38.18 1.39.17
IOB1:PSLEW 1.38.50 1.39.47 1.39.37 1.39.33 1.39.13
ODELAY0:ODELAY_VALUE_INIT 0.37.31 0.37.25 0.37.17 0.37.11 0.37.5
ODELAY1:ODELAY_VALUE_INIT 1.36.32 1.36.38 1.36.46 1.36.52 1.36.58
non-inverted [4] [3] [2] [1] [0]
ILOGIC0:DATA_RATE 0.26.19
ILOGIC1:DATA_RATE 1.27.44
DDR 0
SDR 1
ILOGIC0:DATA_WIDTH 0.27.18 0.26.17 0.27.16 0.26.15
ILOGIC1:DATA_WIDTH 1.26.45 1.27.46 1.26.47 1.27.48
NONE 0 0 0 0
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
10 1 0 1 0
14 1 1 1 0
ILOGIC0:DDR_CLK_EDGE 0.27.28 0.26.29
ILOGIC1:DDR_CLK_EDGE 1.26.35 1.27.34
SAME_EDGE_PIPELINED 0 0
OPPOSITE_EDGE 0 1
SAME_EDGE 1 0
ILOGIC0:IFF1_INIT 0.29.55
ILOGIC0:IFF1_SRVAL 0.28.56
ILOGIC0:IFF2_INIT 0.29.51
ILOGIC0:IFF2_SRVAL 0.28.52
ILOGIC0:IFF3_INIT 0.29.41
ILOGIC0:IFF3_SRVAL 0.28.42
ILOGIC0:IFF4_INIT 0.29.33
ILOGIC0:IFF4_SRVAL 0.28.34
ILOGIC0:IFF_LATCH 0.27.56
ILOGIC0:INV.D 0.28.18
ILOGIC1:IFF1_INIT 1.28.8
ILOGIC1:IFF1_SRVAL 1.29.7
ILOGIC1:IFF2_INIT 1.28.12
ILOGIC1:IFF2_SRVAL 1.29.11
ILOGIC1:IFF3_INIT 1.28.22
ILOGIC1:IFF3_SRVAL 1.29.21
ILOGIC1:IFF4_INIT 1.28.30
ILOGIC1:IFF4_SRVAL 1.29.29
ILOGIC1:IFF_LATCH 1.26.7
ILOGIC1:INV.D 1.29.45
ODELAY0:INV.ODATAIN 0.34.55
ODELAY1:INV.ODATAIN 1.35.8
OLOGIC0:INV.CLK1 0.30.37
OLOGIC0:INV.CLK2 0.30.35
OLOGIC0:INV.T1 0.31.60
OLOGIC0:INV.T2 0.31.56
OLOGIC0:INV.T3 0.30.51
OLOGIC0:INV.T4 0.31.48
OLOGIC0:OFF_INIT 0.32.30
OLOGIC0:RANK3_USED 0.30.41
OLOGIC0:TFF_INIT 0.31.52
OLOGIC1:INV.CLK1 1.31.26
OLOGIC1:INV.CLK2 1.31.28
OLOGIC1:INV.T1 1.30.3
OLOGIC1:INV.T2 1.30.7
OLOGIC1:INV.T3 1.31.12
OLOGIC1:INV.T4 1.30.15
OLOGIC1:OFF_INIT 1.33.33
OLOGIC1:RANK3_USED 1.31.22
OLOGIC1:TFF_INIT 1.30.11
inverted ~[0]
ILOGIC0:INTERFACE_TYPE 0.27.12 0.27.14 0.27.10 0.27.26 0.27.6
ILOGIC1:INTERFACE_TYPE 1.26.51 1.26.49 1.26.53 1.26.37 1.26.57
MEMORY 0 0 0 0 0
NETWORKING 0 0 0 0 1
MEMORY_DDR3 0 0 1 1 1
MEMORY_DDR3_V6 0 1 0 1 1
OVERSAMPLE 1 0 0 1 1
ILOGIC0:INV.CLK 0.29.1 0.28.4 0.28.2
ILOGIC1:INV.CLK 1.29.61 1.29.59 1.28.62
OLOGIC0:OFF_SRVAL 0.33.19 0.32.32 0.32.20
OLOGIC0:TFF_SRVAL 0.33.45 0.32.52 0.32.46
OLOGIC1:OFF_SRVAL 1.33.43 1.33.31 1.32.44
OLOGIC1:TFF_SRVAL 1.33.17 1.33.11 1.32.18
inverted ~[2] ~[1] ~[0]
ILOGIC0:MUX.CLK 0.29.50 0.28.51 0.29.52 0.28.47 0.28.49 0.29.46 0.29.48 0.28.53 0.29.60 0.29.62 0.28.61
ILOGIC0:MUX.CLKB 0.30.50 0.31.51 0.30.52 0.31.47 0.31.49 0.30.46 0.30.48 0.31.53 0.30.60 0.30.62 0.31.61
ILOGIC1:MUX.CLK 1.28.13 1.29.12 1.28.11 1.29.16 1.29.14 1.28.17 1.28.15 1.29.10 1.28.3 1.28.1 1.29.2
ILOGIC1:MUX.CLKB 1.31.13 1.30.12 1.31.11 1.30.16 1.30.14 1.31.17 1.31.15 1.30.10 1.31.3 1.31.1 1.30.2
NONE 0 0 0 0 0 0 0 0 0 0 0
PHASER_ICLK 0 0 0 0 0 0 0 0 0 0 1
PHASER_OCLK 0 0 0 0 0 0 0 0 0 1 0
HCLK0 0 0 0 0 0 0 1 1 1 0 0
HCLK1 0 0 0 0 0 1 0 1 1 0 0
HCLK2 0 0 0 0 1 0 0 1 1 0 0
HCLK3 0 0 0 1 0 0 0 1 1 0 0
HCLK4 0 0 1 0 0 0 1 0 1 0 0
HCLK5 0 0 1 0 0 1 0 0 1 0 0
RCLK0 0 0 1 0 1 0 0 0 1 0 0
RCLK1 0 0 1 1 0 0 0 0 1 0 0
RCLK2 0 1 0 0 0 0 1 0 1 0 0
RCLK3 0 1 0 0 0 1 0 0 1 0 0
IOCLK0 0 1 0 0 1 0 0 0 1 0 0
IOCLK1 0 1 0 1 0 0 0 0 1 0 0
IOCLK2 1 0 0 0 0 0 1 0 1 0 0
IOCLK3 1 0 0 0 0 1 0 0 1 0 0
CKINT1 1 0 0 0 1 0 0 0 1 0 0
CKINT0 1 0 0 1 0 0 0 0 1 0 0
ILOGIC0:MUX.CLKDIVP 0.29.28 0.28.29
ILOGIC1:MUX.CLKDIVP 1.28.35 1.29.34
NONE 0 0
CLKDIV 0 1
PHASER 1 0
ILOGIC0:NUM_CE 0.26.47
ILOGIC1:NUM_CE 1.27.16
1 0
2 1
ILOGIC0:SERDES_MODE 0.26.21
ILOGIC1:SERDES_MODE 1.27.42
OLOGIC0:SERDES_MODE 0.32.44
OLOGIC1:SERDES_MODE 1.33.19
MASTER 0
SLAVE 1
ILOGIC0:SRTYPE 0.28.60
ILOGIC1:SRTYPE 1.29.3
ASYNC 0
SYNC 1
ILOGIC0:TSBYPASS_MUX 0.29.17
ILOGIC1:TSBYPASS_MUX 1.28.46
T 0
GND 1
IOB0:DCITERMDISABLE_SEL 0.38.62
IOB0:IBUFDISABLE_SEL 0.39.39
IOB1:DCITERMDISABLE_SEL 1.39.1
IOB1:IBUFDISABLE_SEL 1.38.24
GND 0
I 1
IOB0:DCI_MODE 0.39.53 0.38.42
IOB1:DCI_MODE 1.38.10 1.39.21
NONE 0 0
OUTPUT 0 1
OUTPUT_HALF 1 0
TERM_SPLIT 1 1
IOB0:IBUF_MODE 0.39.3 0.38.2 0.39.1 0.38.0
IOB1:IBUF_MODE 1.38.60 1.39.61 1.38.62 1.39.63
OFF 0 0 0 0
VREF_LP 0 0 0 1
DIFF_LP 0 0 1 0
CMOS 0 0 1 1
VREF_HP 0 1 0 1
DIFF_HP 1 0 1 0
IOB0:LVDS 0.39.41 0.38.54 0.38.40 0.39.37 0.38.28 0.39.25 0.39.21 0.39.15 0.38.8
IOB1:LVDS 1.38.22 1.39.9 1.39.23 1.38.26 1.39.35 1.38.38 1.38.42 1.38.48 1.39.55
non-inverted [8] [7] [6] [5] [4] [3] [2] [1] [0]
IOB0:NDRIVE 0.38.20 0.38.24 0.39.35 0.39.47 0.39.55 0.39.27 0.39.51
IOB1:NDRIVE 1.39.43 1.39.39 1.38.28 1.38.16 1.38.8 1.38.36 1.38.12
mixed inversion [6] ~[5] [4] ~[3] [2] [1] [0]
IOB0:OMUX 0.39.43
O 0
OTHER_O_INV 1
IOB0:OUTPUT_ENABLE 0.38.34 0.38.32
IOB1:OUTPUT_ENABLE 1.39.31 1.39.29
non-inverted [1] [0]
IOB0:OUTPUT_MISC 0.39.19 0.39.11 0.39.57 0.39.9 0.38.60 0.38.58
IOB1:OUTPUT_MISC 1.38.44 1.38.52 1.38.6 1.38.54 1.39.3 1.39.5
non-inverted [5] [4] [3] [2] [1] [0]
IOB0:PDRIVE 0.39.23 0.39.33 0.38.44 0.39.49 0.38.48 0.39.31 0.39.61
IOB1:PDRIVE 1.38.40 1.38.30 1.39.19 1.38.14 1.39.15 1.38.32 1.38.2
mixed inversion [6] ~[5] [4] ~[3] ~[2] [1] [0]
IOB0:PULL 0.38.4 0.38.10 0.38.12
IOB1:PULL 1.39.59 1.39.53 1.39.51
PULLDOWN 0 0 0
NONE 0 0 1
PULLUP 0 1 1
KEEPER 1 0 1
IOB0:TMUX 0.39.17
T 0
OTHER_T 1
ODELAY0:DELAY_SRC 0.37.57 0.36.56 0.37.55
ODELAY1:DELAY_SRC 1.36.6 1.37.7 1.36.8
NONE 0 0 0
ODATAIN 0 0 1
CLKIN 0 1 0
DELAYCHAIN_OSC 1 0 0
OLOGIC0:CLK_RATIO 0.30.27 0.30.29 0.31.32 0.31.28
OLOGIC1:CLK_RATIO 1.31.36 1.31.34 1.30.31 1.30.35
NONE 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 1
7_8 1 1 0 0
6 1 1 0 1
OLOGIC0:DATA_WIDTH 0.31.26 0.31.12 0.30.11 0.31.4 0.30.7 0.31.6 0.30.3 0.30.1 0.31.0
OLOGIC1:DATA_WIDTH 1.30.37 1.30.51 1.31.52 1.30.59 1.31.56 1.30.57 1.31.60 1.31.62 1.30.63
NONE 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 1
3 0 0 0 0 0 0 0 1 0
4 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 1 0 0 0
6 0 0 0 0 1 0 0 0 0
7 0 0 0 1 0 0 0 0 0
8 0 0 1 0 0 0 0 0 0
10 0 1 0 0 0 0 0 0 0
14 1 0 0 0 0 0 0 0 0
OLOGIC0:MISR_CLK_SELECT 0.30.5 0.30.15
OLOGIC1:MISR_CLK_SELECT 1.31.58 1.31.48
NONE 0 0
CLK1 0 1
CLK2 1 0
OLOGIC0:MUX.CLK 0.29.34 0.28.35 0.29.38 0.28.31 0.28.33 0.29.30 0.29.32 0.28.39 0.28.43 0.28.45 0.29.44
OLOGIC0:MUX.CLKB 0.30.34 0.31.35 0.30.38 0.31.31 0.31.33 0.30.30 0.30.32 0.31.39 0.31.43 0.31.45 0.30.44
OLOGIC1:MUX.CLK 1.28.29 1.29.28 1.28.25 1.29.32 1.29.30 1.28.33 1.28.31 1.29.24 1.29.20 1.29.18 1.28.19
OLOGIC1:MUX.CLKB 1.31.29 1.30.28 1.31.25 1.30.32 1.30.30 1.31.33 1.31.31 1.30.24 1.30.20 1.30.18 1.31.19
NONE 0 0 0 0 0 0 0 0 0 0 0
PHASER_OCLK 0 0 0 0 0 0 0 0 0 1 0
PHASER_OCLK90 0 0 0 0 0 0 0 0 1 0 0
HCLK0 0 0 0 0 0 0 1 1 0 0 1
HCLK1 0 0 0 0 0 1 0 1 0 0 1
HCLK2 0 0 0 0 1 0 0 1 0 0 1
HCLK3 0 0 0 1 0 0 0 1 0 0 1
HCLK4 0 0 1 0 0 0 1 0 0 0 1
HCLK5 0 0 1 0 0 1 0 0 0 0 1
RCLK0 0 0 1 0 1 0 0 0 0 0 1
RCLK1 0 0 1 1 0 0 0 0 0 0 1
RCLK2 0 1 0 0 0 0 1 0 0 0 1
RCLK3 0 1 0 0 0 1 0 0 0 0 1
IOCLK0 0 1 0 0 1 0 0 0 0 0 1
IOCLK1 0 1 0 1 0 0 0 0 0 0 1
IOCLK2 1 0 0 0 0 0 1 0 0 0 1
IOCLK3 1 0 0 0 0 1 0 0 0 0 1
CKINT 1 0 0 0 1 0 0 0 0 0 1
OLOGIC0:MUX.CLKDIV 0.28.17 0.29.16
OLOGIC1:MUX.CLKDIV 1.29.46 1.28.47
NONE 0 0
CLKDIVF 0 1
PHASER_OCLKDIV 1 0
OLOGIC0:MUX.CLKDIVB 0.31.17 0.30.16
OLOGIC1:MUX.CLKDIVB 1.30.46 1.31.47
NONE 0 0
CLKDIVFB 0 1
PHASER_OCLKDIV 1 0
OLOGIC0:MUX.CLKDIVF 0.29.6 0.29.8 0.28.9 0.29.2 0.29.4 0.28.1 0.28.3
OLOGIC0:MUX.CLKDIVFB 0.30.6 0.30.8 0.31.9 0.30.2 0.30.4 0.31.1 0.31.3
OLOGIC1:MUX.CLKDIVF 1.28.57 1.28.55 1.29.54 1.28.61 1.28.59 1.29.62 1.29.60
OLOGIC1:MUX.CLKDIVFB 1.31.57 1.31.55 1.30.54 1.31.61 1.31.59 1.30.62 1.30.60
NONE 0 0 0 0 0 0 0
HCLK0 0 0 1 0 0 0 1
HCLK1 0 0 1 0 0 1 0
HCLK2 0 0 1 0 1 0 0
HCLK3 0 0 1 1 0 0 0
HCLK4 0 1 0 0 0 0 1
HCLK5 0 1 0 0 0 1 0
RCLK0 0 1 0 0 1 0 0
RCLK1 0 1 0 1 0 0 0
RCLK2 1 0 0 0 0 0 1
RCLK3 1 0 0 0 0 1 0
CKINT 1 0 0 0 1 0 0
OLOGIC0:OMUX 0.33.17 0.32.14 0.32.36 0.32.34 0.32.16
OLOGIC1:OMUX 1.32.46 1.33.49 1.33.27 1.33.29 1.33.47
NONE 0 0 0 0 0
D1 0 0 0 0 1
SERDES_SDR 0 0 0 1 0
DDR 0 0 1 0 0
FF 0 1 0 1 0
LATCH 1 0 0 1 0
OLOGIC0:TMUX 0.32.60 0.33.59 0.33.57 0.32.58 0.33.61
OLOGIC1:TMUX 1.33.3 1.32.4 1.32.6 1.33.5 1.32.2
NONE 0 0 0 0 0
T1 0 0 0 0 1
SERDES_SDR 0 0 0 1 0
DDR 0 0 1 0 0
FF 0 1 0 1 0
LATCH 1 0 0 1 0
OLOGIC0:TRISTATE_WIDTH 0.33.37
OLOGIC1:TRISTATE_WIDTH 1.32.26
1 0
4 1

Bitstream — IO_HP_BOT

virtex7 IO_HP_BOT bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLK_INV_EN OLOGIC0:DATA_WIDTH[0] - - - - - - - - IOB0:IBUF_MODE[0]
62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INV.CLK[0] OLOGIC0:MUX.CLKDIVF[1] OLOGIC0:MUX.CLKDIVFB[1] OLOGIC0:DATA_WIDTH[1] - - - - - - IOB0:IBUF_MODE[1] -
61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLKDIVF[3] ~ILOGIC0:INV.CLK[2] OLOGIC0:INV.D8 OLOGIC0:MUX.CLKDIVFB[3] - - - - - - - IOB0:IBUF_MODE[2]
60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.OCLK2 OLOGIC0:MUX.CLKDIVF[0] OLOGIC0:MUX.CLKDIVFB[0] OLOGIC0:DATA_WIDTH[2] - - - - - - - -
59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLKDIVF[2] ~ILOGIC0:INV.CLK[1] OLOGIC0:DATA_WIDTH[5] OLOGIC0:MUX.CLKDIVFB[2] - - - - - - - IOB0:PULL[2]
58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MISR_CLK_SELECT[1] - - IDELAY0:IDELAY_VALUE_INIT[0] - ODELAY0:ODELAY_VALUE_INIT[0] - IOB0:INPUT_MISC -
57 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[0] - OLOGIC0:MUX.CLKDIVF[6] - OLOGIC0:DATA_WIDTH[3] OLOGIC0:MUX.CLKDIVFB[6] - - - - - - - IOB0:PULL_DYNAMIC
56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:DATA_WIDTH[4] - - ~IDELAY0:IDELAY_VALUE_CUR[0] - ~ODELAY0:ODELAY_VALUE_CUR[0] - - -
55 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.CLKDIV - OLOGIC0:MUX.CLKDIVF[5] - OLOGIC0:MISR_RESET OLOGIC0:MUX.CLKDIVFB[5] - - - IDELAY0:IDELAY_TYPE[0] - ODELAY0:ODELAY_TYPE[0] - IOB0:LVDS[0]
54 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLKDIV_INV_EN - OLOGIC0:MUX.CLKDIVF[4] OLOGIC0:MUX.CLKDIVFB[4] OLOGIC0:INV.D7 - - - - - - IOB0:OUTPUT_MISC[2] -
53 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[2] - - - OLOGIC0:MISR_ENABLE_FDBK - - - - - - - - IOB0:PULL[1]
52 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLKDIVP_INV_EN ILOGIC0:IFF_DELAY_ENABLE - - OLOGIC0:DATA_WIDTH[6] - - IDELAY0:IDELAY_VALUE_INIT[1] - ODELAY0:ODELAY_VALUE_INIT[1] - IOB0:OUTPUT_MISC[4] -
51 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[4] - - - OLOGIC0:DATA_WIDTH[7] - - - - - - - - IOB0:PULL[0]
50 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.CLKDIVP - - - OLOGIC0:INV.D6 - - ~IDELAY0:IDELAY_VALUE_CUR[1] - ~ODELAY0:ODELAY_VALUE_CUR[1] - IOB0:PSLEW[4] -
49 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[3] - - ILOGIC0:IFF_TSBYPASS_ENABLE OLOGIC0:INV.D5 - - OLOGIC0:OMUX[3] - IDELAY0:IDELAY_TYPE[1] - ODELAY0:ODELAY_TYPE[1] - IOB0:NSLEW[4]
48 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[0] - - - OLOGIC0:MISR_CLK_SELECT[0] OLOGIC0:OFF_SR_USED - - - - - IOB0:LVDS[1] -
47 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[1] - OLOGIC0:MUX.CLKDIV[0] - OLOGIC0:MISR_ENABLE OLOGIC0:MUX.CLKDIVB[0] - OLOGIC0:OMUX[0] - - - - - IOB0:PSLEW[3]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[2] ILOGIC0:TSBYPASS_MUX[0] OLOGIC0:MUX.CLKDIV[1] OLOGIC0:MUX.CLKDIVB[1] OLOGIC0:INV.D4 OLOGIC0:OMUX[4] - IDELAY0:IDELAY_VALUE_INIT[2] - ODELAY0:ODELAY_VALUE_INIT[2] - - -
45 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[3] - - ~ILOGIC0:INV.D - - IDELAY0:HIGH_PERFORMANCE_MODE - ODELAY0:HIGH_PERFORMANCE_MODE - - - - IOB0:VR
44 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_RATE[0] - - - - ~OLOGIC0:OFF_SRVAL[0] - ~IDELAY0:IDELAY_VALUE_CUR[2] - ~ODELAY0:ODELAY_VALUE_CUR[2] - IOB0:OUTPUT_MISC[5] -
43 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:BITSLIP_ENABLE - - - - - - ~OLOGIC0:OFF_SRVAL[2] - - - - - IOB0:NDRIVE[6]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:SERDES_MODE[0] - - - OLOGIC0:INV.D3 - - IDELAY0:PIPE_SEL - ODELAY0:PIPE_SEL - IOB0:LVDS[2] -
41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ODELAY0:FINEDELAY[0] - IOB0:NSLEW[3]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB0:PDRIVE[6] -
39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:I_TSBYPASS_ENABLE - - - - - - - - - ~IOB0:NDRIVE[5]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:SERDES - - - OLOGIC0:INV.D2 - - IDELAY0:IDELAY_VALUE_INIT[3] - ODELAY0:ODELAY_VALUE_INIT[3] - IOB0:LVDS[3] -
37 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[1] - - ILOGIC0:I_DELAY_ENABLE OLOGIC0:DATA_WIDTH[8] - - - - - - - - IOB0:PSLEW[2]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:RANK23_DLY - - - OLOGIC0:CLK_RATIO[3] - - ~IDELAY0:IDELAY_VALUE_CUR[3] - ~ODELAY0:ODELAY_VALUE_CUR[3] - IOB0:NDRIVE[1] -
35 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DDR_CLK_EDGE[1] - ILOGIC0:MUX.CLKDIVP[1] - OLOGIC0:CLK_RATIO[0] - - - - - - - - IOB0:LVDS[4]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DDR_CLK_EDGE[0] - ILOGIC0:MUX.CLKDIVP[0] - OLOGIC0:CLK_RATIO[2] - - - - - - IOB0:DQS_BIAS_P -
33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[5] - OLOGIC0:INV.D1 OLOGIC0:MUX.CLKB[5] - ~OLOGIC0:OFF_INIT - - - - - IOB0:PSLEW[1]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[7] OLOGIC0:MUX.CLKB[7] OLOGIC0:SELFHEAL - - IDELAY0:IDELAY_VALUE_INIT[4] - ODELAY0:ODELAY_VALUE_INIT[4] - IOB0:PDRIVE[1] -
31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[4] - OLOGIC0:CLK_RATIO[1] OLOGIC0:MUX.CLKB[4] - ~OLOGIC0:OFF_SRVAL[1] - - - - - IOB0:OUTPUT_ENABLE[1]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF4_INIT OLOGIC0:MUX.CLK[6] OLOGIC0:MUX.CLKB[6] OLOGIC0:INV.CLKDIVF OLOGIC0:OFF_SR_SYNC - ~IDELAY0:IDELAY_VALUE_CUR[4] - ~ODELAY0:ODELAY_VALUE_CUR[4] - ~IOB0:PDRIVE[5] -
29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[10] ~ILOGIC0:IFF4_SRVAL - OLOGIC0:MUX.CLKB[10] - OLOGIC0:OMUX[1] - - - - - IOB0:OUTPUT_ENABLE[0]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[9] OLOGIC0:MUX.CLKB[9] ~OLOGIC0:INV.CLK2 - - - - - - IOB0:NDRIVE[4] -
27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:OMUX[2] - - - - - IOB0:DQS_BIAS_N
26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~OLOGIC0:INV.CLK1 OLOGIC0:TRISTATE_WIDTH[0] - - - - - IOB0:LVDS[5] -
25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[8] - - OLOGIC0:MUX.CLKB[8] - OLOGIC0:TFF_SR_USED - IDELAY0:CINVCTRL_SEL - ODELAY0:CINVCTRL_SEL - IOB0:NSLEW[2]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[3] OLOGIC0:MUX.CLKB[3] - - - IDELAY0:INV.C - ODELAY0:INV.C - IOB0:IBUFDISABLE_SEL[0] -
23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB0:LVDS[6]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF3_INIT - - ~OLOGIC0:RANK3_USED - - - - - - IOB0:LVDS[8] -
21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF3_SRVAL OLOGIC0:INV.CLKDIV - - - - - - - - IOB0:DCI_MODE[0]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[2] OLOGIC0:MUX.CLKB[2] - OLOGIC0:TBYTE_SRC - - - - - - -
19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[0] - - OLOGIC0:MUX.CLKB[0] - OLOGIC0:SERDES_MODE[0] - - - - - IOB0:PDRIVE[4]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[1] OLOGIC0:MUX.CLKB[1] - ~OLOGIC0:TFF_SRVAL[0] - - - - - IOB0:NSLEW[1] -
17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[5] - - ILOGIC0:MUX.CLKB[5] - ~OLOGIC0:TFF_SRVAL[2] - IDELAY0:INV.DATAIN - - - IOB0:NSLEW[0]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:NUM_CE[0] - ILOGIC0:MUX.CLK[7] ILOGIC0:MUX.CLKB[7] - OLOGIC0:TBYTE_CTL - - - - - ~IOB0:NDRIVE[3] -
15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[4] - ~OLOGIC0:INV.T4 ILOGIC0:MUX.CLKB[4] - - - - - - - ~IOB0:PDRIVE[2]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[6] ILOGIC0:MUX.CLKB[6] - - - - - - - ~IOB0:PDRIVE[3] -
13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[10] - - ILOGIC0:MUX.CLKB[10] - - - - - - - IOB0:PSLEW[0]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF2_INIT ILOGIC0:MUX.CLK[9] ILOGIC0:MUX.CLKB[9] ~OLOGIC0:INV.T3 - - - - - - IOB0:NDRIVE[0] -
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[8] ~ILOGIC0:IFF2_SRVAL ~OLOGIC0:TFF_INIT ILOGIC0:MUX.CLKB[8] - ~OLOGIC0:TFF_SRVAL[1] - - - - - IOB0:OUTPUT_DELAY
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[3] ILOGIC0:MUX.CLKB[3] - - - - - - - IOB0:DCI_MODE[1] -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY0:ENABLE OLOGIC0:SERDES ODELAY0:ENABLE - - - - IOB0:LVDS[7]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF1_INIT - - - OLOGIC0:TFF_SR_SYNC IDELAY0:INV.IDATAIN IDELAY0:DELAY_SRC[0] ~ODELAY0:INV.ODATAIN ODELAY0:DELAY_SRC[0] - IOB0:NDRIVE[2] -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF_LATCH - - ~ILOGIC0:IFF1_SRVAL ~OLOGIC0:INV.T2 - - - - IDELAY0:DELAY_SRC[2] - ODELAY0:DELAY_SRC[1] - IOB0:DCIUPDATEMODE_QUIET
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_SR_USED - - - - OLOGIC0:TMUX[2] - IDELAY0:DELAY_SRC[3] - ODELAY0:DELAY_SRC[2] - IOB0:OUTPUT_MISC[3] -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY0:FINEDELAY[0] - - - OLOGIC0:TMUX[1] - IDELAY0:DELAY_SRC[1] - - - IOB0:OUTPUT_MISC[0]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TMUX[3] - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[2] ILOGIC0:SRTYPE[0] ~OLOGIC0:INV.T1 ILOGIC0:MUX.CLKB[2] - OLOGIC0:TMUX[4] - - - - - IOB0:OUTPUT_MISC[1]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:D_EMU2 ILOGIC0:MUX.CLK[0] ILOGIC0:MUX.CLKB[0] - OLOGIC0:TMUX[0] - - - - - IOB0:PDRIVE[0] -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[1] ILOGIC0:D_EMU1 - ILOGIC0:MUX.CLKB[1] - - - - - - - IOB0:DCITERMDISABLE_SEL[0]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.OCLK1 - - - - - - - - - IOB0:DCI_T -
IDELAY0:CINVCTRL_SEL 0.35.25
IDELAY0:ENABLE 0.32.9
IDELAY0:HIGH_PERFORMANCE_MODE 0.32.45
IDELAY0:INV.C 0.34.24
IDELAY0:INV.DATAIN 0.35.17
IDELAY0:INV.IDATAIN 0.33.8
IDELAY0:PIPE_SEL 0.34.42
ILOGIC0:BITSLIP_ENABLE 0.26.43
ILOGIC0:DYN_CLKDIVP_INV_EN 0.27.52
ILOGIC0:DYN_CLKDIV_INV_EN 0.27.54
ILOGIC0:DYN_CLK_INV_EN 0.29.63
ILOGIC0:D_EMU1 0.29.1
ILOGIC0:D_EMU2 0.28.2
ILOGIC0:IFF_DELAY_ENABLE 0.28.52
ILOGIC0:IFF_SR_USED 0.27.6
ILOGIC0:IFF_TSBYPASS_ENABLE 0.29.49
ILOGIC0:INV.CLKDIV 0.26.55
ILOGIC0:INV.CLKDIVP 0.27.50
ILOGIC0:INV.OCLK1 0.28.0
ILOGIC0:INV.OCLK2 0.28.60
ILOGIC0:I_DELAY_ENABLE 0.29.37
ILOGIC0:I_TSBYPASS_ENABLE 0.29.39
ILOGIC0:RANK23_DLY 0.27.36
ILOGIC0:SERDES 0.27.38
IOB0:DCIUPDATEMODE_QUIET 0.39.7
IOB0:DCI_T 0.38.0
IOB0:DQS_BIAS_N 0.39.27
IOB0:DQS_BIAS_P 0.38.34
IOB0:INPUT_MISC 0.38.58
IOB0:OUTPUT_DELAY 0.39.11
IOB0:PULL_DYNAMIC 0.39.57
IOB0:VR 0.39.45
ODELAY0:CINVCTRL_SEL 0.37.25
ODELAY0:ENABLE 0.34.9
ODELAY0:HIGH_PERFORMANCE_MODE 0.34.45
ODELAY0:INV.C 0.36.24
ODELAY0:PIPE_SEL 0.36.42
OLOGIC0:INV.CLKDIV 0.30.21
OLOGIC0:INV.CLKDIVF 0.31.30
OLOGIC0:INV.D1 0.30.33
OLOGIC0:INV.D2 0.31.38
OLOGIC0:INV.D3 0.31.42
OLOGIC0:INV.D4 0.31.46
OLOGIC0:INV.D5 0.30.49
OLOGIC0:INV.D6 0.31.50
OLOGIC0:INV.D7 0.31.54
OLOGIC0:INV.D8 0.30.61
OLOGIC0:MISR_ENABLE 0.30.47
OLOGIC0:MISR_ENABLE_FDBK 0.30.53
OLOGIC0:MISR_RESET 0.30.55
OLOGIC0:OFF_SR_SYNC 0.32.30
OLOGIC0:OFF_SR_USED 0.32.48
OLOGIC0:SELFHEAL 0.31.32
OLOGIC0:SERDES 0.33.9
OLOGIC0:TBYTE_CTL 0.32.16
OLOGIC0:TBYTE_SRC 0.32.20
OLOGIC0:TFF_SR_SYNC 0.32.8
OLOGIC0:TFF_SR_USED 0.33.25
non-inverted [0]
IDELAY0:DELAY_SRC 0.34.6 0.35.7 0.35.5 0.34.8
NONE 0 0 0 0
IDATAIN 0 0 0 1
DATAIN 0 0 1 0
OFB 0 1 0 0
DELAYCHAIN_OSC 1 0 0 0
IDELAY0:FINEDELAY 0.29.5
ODELAY0:FINEDELAY 0.37.41
BYPASS 0
ADD_DLY 1
IDELAY0:IDELAY_TYPE 0.35.49 0.35.55
ODELAY0:ODELAY_TYPE 0.37.49 0.37.55
FIXED 0 0
VARIABLE 0 1
VAR_LOAD 1 1
IDELAY0:IDELAY_VALUE_CUR 0.34.30 0.34.36 0.34.44 0.34.50 0.34.56
ODELAY0:ODELAY_VALUE_CUR 0.36.30 0.36.36 0.36.44 0.36.50 0.36.56
inverted ~[4] ~[3] ~[2] ~[1] ~[0]
IDELAY0:IDELAY_VALUE_INIT 0.34.32 0.34.38 0.34.46 0.34.52 0.34.58
IOB0:NSLEW 0.39.49 0.39.41 0.39.25 0.38.18 0.39.17
IOB0:PSLEW 0.38.50 0.39.47 0.39.37 0.39.33 0.39.13
ODELAY0:ODELAY_VALUE_INIT 0.36.32 0.36.38 0.36.46 0.36.52 0.36.58
non-inverted [4] [3] [2] [1] [0]
ILOGIC0:DATA_RATE 0.27.44
DDR 0
SDR 1
ILOGIC0:DATA_WIDTH 0.26.45 0.27.46 0.26.47 0.27.48
NONE 0 0 0 0
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
10 1 0 1 0
14 1 1 1 0
ILOGIC0:DDR_CLK_EDGE 0.26.35 0.27.34
SAME_EDGE_PIPELINED 0 0
OPPOSITE_EDGE 0 1
SAME_EDGE 1 0
ILOGIC0:IFF1_INIT 0.28.8
ILOGIC0:IFF1_SRVAL 0.29.7
ILOGIC0:IFF2_INIT 0.28.12
ILOGIC0:IFF2_SRVAL 0.29.11
ILOGIC0:IFF3_INIT 0.28.22
ILOGIC0:IFF3_SRVAL 0.29.21
ILOGIC0:IFF4_INIT 0.28.30
ILOGIC0:IFF4_SRVAL 0.29.29
ILOGIC0:IFF_LATCH 0.26.7
ILOGIC0:INV.D 0.29.45
ODELAY0:INV.ODATAIN 0.35.8
OLOGIC0:INV.CLK1 0.31.26
OLOGIC0:INV.CLK2 0.31.28
OLOGIC0:INV.T1 0.30.3
OLOGIC0:INV.T2 0.30.7
OLOGIC0:INV.T3 0.31.12
OLOGIC0:INV.T4 0.30.15
OLOGIC0:OFF_INIT 0.33.33
OLOGIC0:RANK3_USED 0.31.22
OLOGIC0:TFF_INIT 0.30.11
inverted ~[0]
ILOGIC0:INTERFACE_TYPE 0.26.51 0.26.49 0.26.53 0.26.37 0.26.57
MEMORY 0 0 0 0 0
NETWORKING 0 0 0 0 1
MEMORY_DDR3 0 0 1 1 1
MEMORY_DDR3_V6 0 1 0 1 1
OVERSAMPLE 1 0 0 1 1
ILOGIC0:INV.CLK 0.29.61 0.29.59 0.28.62
OLOGIC0:OFF_SRVAL 0.33.43 0.33.31 0.32.44
OLOGIC0:TFF_SRVAL 0.33.17 0.33.11 0.32.18
inverted ~[2] ~[1] ~[0]
ILOGIC0:MUX.CLK 0.28.13 0.29.12 0.28.11 0.29.16 0.29.14 0.28.17 0.28.15 0.29.10 0.28.3 0.28.1 0.29.2
ILOGIC0:MUX.CLKB 0.31.13 0.30.12 0.31.11 0.30.16 0.30.14 0.31.17 0.31.15 0.30.10 0.31.3 0.31.1 0.30.2
NONE 0 0 0 0 0 0 0 0 0 0 0
PHASER_ICLK 0 0 0 0 0 0 0 0 0 0 1
PHASER_OCLK 0 0 0 0 0 0 0 0 0 1 0
HCLK0 0 0 0 0 0 0 1 1 1 0 0
HCLK1 0 0 0 0 0 1 0 1 1 0 0
HCLK2 0 0 0 0 1 0 0 1 1 0 0
HCLK3 0 0 0 1 0 0 0 1 1 0 0
HCLK4 0 0 1 0 0 0 1 0 1 0 0
HCLK5 0 0 1 0 0 1 0 0 1 0 0
RCLK0 0 0 1 0 1 0 0 0 1 0 0
RCLK1 0 0 1 1 0 0 0 0 1 0 0
RCLK2 0 1 0 0 0 0 1 0 1 0 0
RCLK3 0 1 0 0 0 1 0 0 1 0 0
IOCLK0 0 1 0 0 1 0 0 0 1 0 0
IOCLK1 0 1 0 1 0 0 0 0 1 0 0
IOCLK2 1 0 0 0 0 0 1 0 1 0 0
IOCLK3 1 0 0 0 0 1 0 0 1 0 0
CKINT1 1 0 0 0 1 0 0 0 1 0 0
CKINT0 1 0 0 1 0 0 0 0 1 0 0
ILOGIC0:MUX.CLKDIVP 0.28.35 0.29.34
NONE 0 0
CLKDIV 0 1
PHASER 1 0
ILOGIC0:NUM_CE 0.27.16
1 0
2 1
ILOGIC0:SERDES_MODE 0.27.42
OLOGIC0:SERDES_MODE 0.33.19
MASTER 0
SLAVE 1
ILOGIC0:SRTYPE 0.29.3
ASYNC 0
SYNC 1
ILOGIC0:TSBYPASS_MUX 0.28.46
T 0
GND 1
IOB0:DCITERMDISABLE_SEL 0.39.1
IOB0:IBUFDISABLE_SEL 0.38.24
GND 0
I 1
IOB0:DCI_MODE 0.38.10 0.39.21
NONE 0 0
OUTPUT 0 1
OUTPUT_HALF 1 0
TERM_SPLIT 1 1
IOB0:IBUF_MODE 0.39.61 0.38.62 0.39.63
OFF 0 0 0
VREF_LP 0 0 1
CMOS 0 1 1
VREF_HP 1 0 1
IOB0:LVDS 0.38.22 0.39.9 0.39.23 0.38.26 0.39.35 0.38.38 0.38.42 0.38.48 0.39.55
non-inverted [8] [7] [6] [5] [4] [3] [2] [1] [0]
IOB0:NDRIVE 0.39.43 0.39.39 0.38.28 0.38.16 0.38.8 0.38.36 0.38.12
mixed inversion [6] ~[5] [4] ~[3] [2] [1] [0]
IOB0:OUTPUT_ENABLE 0.39.31 0.39.29
non-inverted [1] [0]
IOB0:OUTPUT_MISC 0.38.44 0.38.52 0.38.6 0.38.54 0.39.3 0.39.5
non-inverted [5] [4] [3] [2] [1] [0]
IOB0:PDRIVE 0.38.40 0.38.30 0.39.19 0.38.14 0.39.15 0.38.32 0.38.2
mixed inversion [6] ~[5] [4] ~[3] ~[2] [1] [0]
IOB0:PULL 0.39.59 0.39.53 0.39.51
PULLDOWN 0 0 0
NONE 0 0 1
PULLUP 0 1 1
KEEPER 1 0 1
ODELAY0:DELAY_SRC 0.36.6 0.37.7 0.36.8
NONE 0 0 0
ODATAIN 0 0 1
CLKIN 0 1 0
DELAYCHAIN_OSC 1 0 0
OLOGIC0:CLK_RATIO 0.31.36 0.31.34 0.30.31 0.30.35
NONE 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 1
7_8 1 1 0 0
6 1 1 0 1
OLOGIC0:DATA_WIDTH 0.30.37 0.30.51 0.31.52 0.30.59 0.31.56 0.30.57 0.31.60 0.31.62 0.30.63
NONE 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 1
3 0 0 0 0 0 0 0 1 0
4 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 1 0 0 0
6 0 0 0 0 1 0 0 0 0
7 0 0 0 1 0 0 0 0 0
8 0 0 1 0 0 0 0 0 0
10 0 1 0 0 0 0 0 0 0
14 1 0 0 0 0 0 0 0 0
OLOGIC0:MISR_CLK_SELECT 0.31.58 0.31.48
NONE 0 0
CLK1 0 1
CLK2 1 0
OLOGIC0:MUX.CLK 0.28.29 0.29.28 0.28.25 0.29.32 0.29.30 0.28.33 0.28.31 0.29.24 0.29.20 0.29.18 0.28.19
OLOGIC0:MUX.CLKB 0.31.29 0.30.28 0.31.25 0.30.32 0.30.30 0.31.33 0.31.31 0.30.24 0.30.20 0.30.18 0.31.19
NONE 0 0 0 0 0 0 0 0 0 0 0
PHASER_OCLK 0 0 0 0 0 0 0 0 0 1 0
PHASER_OCLK90 0 0 0 0 0 0 0 0 1 0 0
HCLK0 0 0 0 0 0 0 1 1 0 0 1
HCLK1 0 0 0 0 0 1 0 1 0 0 1
HCLK2 0 0 0 0 1 0 0 1 0 0 1
HCLK3 0 0 0 1 0 0 0 1 0 0 1
HCLK4 0 0 1 0 0 0 1 0 0 0 1
HCLK5 0 0 1 0 0 1 0 0 0 0 1
RCLK0 0 0 1 0 1 0 0 0 0 0 1
RCLK1 0 0 1 1 0 0 0 0 0 0 1
RCLK2 0 1 0 0 0 0 1 0 0 0 1
RCLK3 0 1 0 0 0 1 0 0 0 0 1
IOCLK0 0 1 0 0 1 0 0 0 0 0 1
IOCLK1 0 1 0 1 0 0 0 0 0 0 1
IOCLK2 1 0 0 0 0 0 1 0 0 0 1
IOCLK3 1 0 0 0 0 1 0 0 0 0 1
CKINT 1 0 0 0 1 0 0 0 0 0 1
OLOGIC0:MUX.CLKDIV 0.29.46 0.28.47
NONE 0 0
CLKDIVF 0 1
PHASER_OCLKDIV 1 0
OLOGIC0:MUX.CLKDIVB 0.30.46 0.31.47
NONE 0 0
CLKDIVFB 0 1
PHASER_OCLKDIV 1 0
OLOGIC0:MUX.CLKDIVF 0.28.57 0.28.55 0.29.54 0.28.61 0.28.59 0.29.62 0.29.60
OLOGIC0:MUX.CLKDIVFB 0.31.57 0.31.55 0.30.54 0.31.61 0.31.59 0.30.62 0.30.60
NONE 0 0 0 0 0 0 0
HCLK0 0 0 1 0 0 0 1
HCLK1 0 0 1 0 0 1 0
HCLK2 0 0 1 0 1 0 0
HCLK3 0 0 1 1 0 0 0
HCLK4 0 1 0 0 0 0 1
HCLK5 0 1 0 0 0 1 0
RCLK0 0 1 0 0 1 0 0
RCLK1 0 1 0 1 0 0 0
RCLK2 1 0 0 0 0 0 1
RCLK3 1 0 0 0 0 1 0
CKINT 1 0 0 0 1 0 0
OLOGIC0:OMUX 0.32.46 0.33.49 0.33.27 0.33.29 0.33.47
NONE 0 0 0 0 0
D1 0 0 0 0 1
SERDES_SDR 0 0 0 1 0
DDR 0 0 1 0 0
FF 0 1 0 1 0
LATCH 1 0 0 1 0
OLOGIC0:TMUX 0.33.3 0.32.4 0.32.6 0.33.5 0.32.2
NONE 0 0 0 0 0
T1 0 0 0 0 1
SERDES_SDR 0 0 0 1 0
DDR 0 0 1 0 0
FF 0 1 0 1 0
LATCH 1 0 0 1 0
OLOGIC0:TRISTATE_WIDTH 0.32.26
1 0
4 1

Bitstream — IO_HP_TOP

virtex7 IO_HP_TOP bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.OCLK1 - - - - - - - - - IOB0:DCI_T
62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:D_EMU1 ILOGIC0:MUX.CLK[1] ILOGIC0:MUX.CLKB[1] - - - - - - - IOB0:DCITERMDISABLE_SEL[0] -
61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[0] ILOGIC0:D_EMU2 - ILOGIC0:MUX.CLKB[0] - OLOGIC0:TMUX[0] - - - - - IOB0:PDRIVE[0]
60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:SRTYPE[0] ILOGIC0:MUX.CLK[2] ILOGIC0:MUX.CLKB[2] ~OLOGIC0:INV.T1 OLOGIC0:TMUX[4] - - - - - IOB0:OUTPUT_MISC[1] -
59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TMUX[3] - - - - - -
58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY0:FINEDELAY[0] - - - OLOGIC0:TMUX[1] - IDELAY0:DELAY_SRC[1] - - - IOB0:OUTPUT_MISC[0] -
57 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_SR_USED - - - - - - OLOGIC0:TMUX[2] - IDELAY0:DELAY_SRC[3] - ODELAY0:DELAY_SRC[2] - IOB0:OUTPUT_MISC[3]
56 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF_LATCH ~ILOGIC0:IFF1_SRVAL - - ~OLOGIC0:INV.T2 - - IDELAY0:DELAY_SRC[2] - ODELAY0:DELAY_SRC[1] - IOB0:DCIUPDATEMODE_QUIET -
55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF1_INIT - - IDELAY0:INV.IDATAIN OLOGIC0:TFF_SR_SYNC ~ODELAY0:INV.ODATAIN IDELAY0:DELAY_SRC[0] - ODELAY0:DELAY_SRC[0] - IOB0:NDRIVE[2]
54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:SERDES IDELAY0:ENABLE - ODELAY0:ENABLE - - IOB0:LVDS[7] -
53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[3] - - ILOGIC0:MUX.CLKB[3] - - - - - - - IOB0:DCI_MODE[1]
52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF2_SRVAL ILOGIC0:MUX.CLK[8] ILOGIC0:MUX.CLKB[8] ~OLOGIC0:TFF_INIT ~OLOGIC0:TFF_SRVAL[1] - - - - - IOB0:OUTPUT_DELAY -
51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[9] ~ILOGIC0:IFF2_INIT ~OLOGIC0:INV.T3 ILOGIC0:MUX.CLKB[9] - - - - - - - IOB0:NDRIVE[0]
50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[10] ILOGIC0:MUX.CLKB[10] - - - - - - - IOB0:PSLEW[0] -
49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[6] - - ILOGIC0:MUX.CLKB[6] - - - - - - - ~IOB0:PDRIVE[3]
48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[4] ILOGIC0:MUX.CLKB[4] ~OLOGIC0:INV.T4 - - - - - - ~IOB0:PDRIVE[2] -
47 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:NUM_CE[0] - ILOGIC0:MUX.CLK[7] - - ILOGIC0:MUX.CLKB[7] - OLOGIC0:TBYTE_CTL - - - - - ~IOB0:NDRIVE[3]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[5] ILOGIC0:MUX.CLKB[5] - ~OLOGIC0:TFF_SRVAL[0] - IDELAY0:INV.DATAIN - - - IOB0:NSLEW[0] -
45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[1] - - OLOGIC0:MUX.CLKB[1] - ~OLOGIC0:TFF_SRVAL[2] - - - - - IOB0:NSLEW[1]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[0] OLOGIC0:MUX.CLKB[0] - OLOGIC0:SERDES_MODE[0] - - - - - IOB0:PDRIVE[4] -
43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[2] - - OLOGIC0:MUX.CLKB[2] - OLOGIC0:TBYTE_SRC - - - - - -
42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF3_SRVAL - - OLOGIC0:INV.CLKDIV - - - - - - IOB0:DCI_MODE[0] -
41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF3_INIT ~OLOGIC0:RANK3_USED - - - - - - - - IOB0:LVDS[8]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB0:LVDS[6] -
39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[3] - - OLOGIC0:MUX.CLKB[3] - - - IDELAY0:INV.C - ODELAY0:INV.C - IOB0:IBUFDISABLE_SEL[0]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[8] OLOGIC0:MUX.CLKB[8] - OLOGIC0:TFF_SR_USED - IDELAY0:CINVCTRL_SEL - ODELAY0:CINVCTRL_SEL - IOB0:NSLEW[2] -
37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~OLOGIC0:INV.CLK1 - - OLOGIC0:TRISTATE_WIDTH[0] - - - - - IOB0:LVDS[5]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:OMUX[2] - - - - - IOB0:DQS_BIAS_N -
35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[9] - ~OLOGIC0:INV.CLK2 OLOGIC0:MUX.CLKB[9] - - - - - - - IOB0:NDRIVE[4]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF4_SRVAL OLOGIC0:MUX.CLK[10] OLOGIC0:MUX.CLKB[10] - OLOGIC0:OMUX[1] - - - - - IOB0:OUTPUT_ENABLE[1] -
33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[6] ~ILOGIC0:IFF4_INIT OLOGIC0:INV.CLKDIVF OLOGIC0:MUX.CLKB[6] - OLOGIC0:OFF_SR_SYNC - ~IDELAY0:IDELAY_VALUE_CUR[4] - ~ODELAY0:ODELAY_VALUE_CUR[4] - ~IOB0:PDRIVE[5]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[4] OLOGIC0:MUX.CLKB[4] OLOGIC0:CLK_RATIO[1] ~OLOGIC0:OFF_SRVAL[1] - - - - - IOB0:OUTPUT_ENABLE[0] -
31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[7] - OLOGIC0:SELFHEAL OLOGIC0:MUX.CLKB[7] - - - IDELAY0:IDELAY_VALUE_INIT[4] - ODELAY0:ODELAY_VALUE_INIT[4] - IOB0:PDRIVE[1]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[5] OLOGIC0:MUX.CLKB[5] OLOGIC0:INV.D1 ~OLOGIC0:OFF_INIT - - - - - IOB0:PSLEW[1] -
29 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DDR_CLK_EDGE[0] - ILOGIC0:MUX.CLKDIVP[0] - OLOGIC0:CLK_RATIO[2] - - - - - - - - IOB0:DQS_BIAS_P
28 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DDR_CLK_EDGE[1] - ILOGIC0:MUX.CLKDIVP[1] - OLOGIC0:CLK_RATIO[0] - - - - - - IOB0:LVDS[4] -
27 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:RANK23_DLY - - - OLOGIC0:CLK_RATIO[3] - - - - ~IDELAY0:IDELAY_VALUE_CUR[3] - ~ODELAY0:ODELAY_VALUE_CUR[3] - IOB0:NDRIVE[1]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[1] ILOGIC0:I_DELAY_ENABLE - - OLOGIC0:DATA_WIDTH[8] - - - - - - IOB0:PSLEW[2] -
25 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:SERDES - - - OLOGIC0:INV.D2 - - - - IDELAY0:IDELAY_VALUE_INIT[3] - ODELAY0:ODELAY_VALUE_INIT[3] - IOB0:LVDS[3]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:I_TSBYPASS_ENABLE - - - - - - - - - ~IOB0:NDRIVE[5] -
23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB0:PDRIVE[6]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ODELAY0:FINEDELAY[0] - IOB0:NSLEW[3] -
21 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:SERDES_MODE[0] - - - OLOGIC0:INV.D3 - - - - IDELAY0:PIPE_SEL - ODELAY0:PIPE_SEL - IOB0:LVDS[2]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:BITSLIP_ENABLE - - - - ~OLOGIC0:OFF_SRVAL[0] - - - - - IOB0:NDRIVE[6] -
19 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_RATE[0] - - - - - - ~OLOGIC0:OFF_SRVAL[2] - ~IDELAY0:IDELAY_VALUE_CUR[2] - ~ODELAY0:ODELAY_VALUE_CUR[2] - IOB0:OUTPUT_MISC[5]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[3] ~ILOGIC0:INV.D - - - - IDELAY0:HIGH_PERFORMANCE_MODE - ODELAY0:HIGH_PERFORMANCE_MODE - - IOB0:VR -
17 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[2] - OLOGIC0:MUX.CLKDIV[1] ILOGIC0:TSBYPASS_MUX[0] OLOGIC0:INV.D4 OLOGIC0:MUX.CLKDIVB[1] - OLOGIC0:OMUX[4] - IDELAY0:IDELAY_VALUE_INIT[2] - ODELAY0:ODELAY_VALUE_INIT[2] - -
16 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[1] - OLOGIC0:MUX.CLKDIV[0] OLOGIC0:MUX.CLKDIVB[0] OLOGIC0:MISR_ENABLE OLOGIC0:OMUX[0] - - - - - IOB0:PSLEW[3] -
15 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[0] - - - OLOGIC0:MISR_CLK_SELECT[0] - - OLOGIC0:OFF_SR_USED - - - - - IOB0:LVDS[1]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[3] ILOGIC0:IFF_TSBYPASS_ENABLE - - OLOGIC0:INV.D5 OLOGIC0:OMUX[3] - IDELAY0:IDELAY_TYPE[1] - ODELAY0:ODELAY_TYPE[1] - IOB0:NSLEW[4] -
13 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.CLKDIVP - - - OLOGIC0:INV.D6 - - - - ~IDELAY0:IDELAY_VALUE_CUR[1] - ~ODELAY0:ODELAY_VALUE_CUR[1] - IOB0:PSLEW[4]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[4] - - - OLOGIC0:DATA_WIDTH[7] - - - - - - IOB0:PULL[0] -
11 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLKDIVP_INV_EN - - ILOGIC0:IFF_DELAY_ENABLE OLOGIC0:DATA_WIDTH[6] - - - - IDELAY0:IDELAY_VALUE_INIT[1] - ODELAY0:ODELAY_VALUE_INIT[1] - IOB0:OUTPUT_MISC[4]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[2] - - - OLOGIC0:MISR_ENABLE_FDBK - - - - - - IOB0:PULL[1] -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLKDIV_INV_EN - OLOGIC0:MUX.CLKDIVF[4] - OLOGIC0:INV.D7 OLOGIC0:MUX.CLKDIVFB[4] - - - - - - - IOB0:OUTPUT_MISC[2]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.CLKDIV - OLOGIC0:MUX.CLKDIVF[5] OLOGIC0:MUX.CLKDIVFB[5] OLOGIC0:MISR_RESET - - IDELAY0:IDELAY_TYPE[0] - ODELAY0:ODELAY_TYPE[0] - IOB0:LVDS[0] -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:DATA_WIDTH[4] - - - - ~IDELAY0:IDELAY_VALUE_CUR[0] - ~ODELAY0:ODELAY_VALUE_CUR[0] - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[0] - OLOGIC0:MUX.CLKDIVF[6] OLOGIC0:MUX.CLKDIVFB[6] OLOGIC0:DATA_WIDTH[3] - - - - - - IOB0:PULL_DYNAMIC -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MISR_CLK_SELECT[1] - - - - IDELAY0:IDELAY_VALUE_INIT[0] - ODELAY0:ODELAY_VALUE_INIT[0] - IOB0:INPUT_MISC
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INV.CLK[1] OLOGIC0:MUX.CLKDIVF[2] OLOGIC0:MUX.CLKDIVFB[2] OLOGIC0:DATA_WIDTH[5] - - - - - - IOB0:PULL[2] -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLKDIVF[0] ILOGIC0:INV.OCLK2 OLOGIC0:DATA_WIDTH[2] OLOGIC0:MUX.CLKDIVFB[0] - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INV.CLK[0] OLOGIC0:MUX.CLKDIVF[3] OLOGIC0:MUX.CLKDIVFB[3] OLOGIC0:INV.D8 - - - - - - IOB0:IBUF_MODE[2] -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLKDIVF[1] ~ILOGIC0:INV.CLK[2] OLOGIC0:DATA_WIDTH[1] OLOGIC0:MUX.CLKDIVFB[1] - - - - - - - IOB0:IBUF_MODE[1]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLK_INV_EN - - OLOGIC0:DATA_WIDTH[0] - - - - - - IOB0:IBUF_MODE[0] -
IDELAY0:CINVCTRL_SEL 0.34.38
IDELAY0:ENABLE 0.33.54
IDELAY0:HIGH_PERFORMANCE_MODE 0.33.18
IDELAY0:INV.C 0.35.39
IDELAY0:INV.DATAIN 0.34.46
IDELAY0:INV.IDATAIN 0.32.55
IDELAY0:PIPE_SEL 0.35.21
ILOGIC0:BITSLIP_ENABLE 0.27.20
ILOGIC0:DYN_CLKDIVP_INV_EN 0.26.11
ILOGIC0:DYN_CLKDIV_INV_EN 0.26.9
ILOGIC0:DYN_CLK_INV_EN 0.28.0
ILOGIC0:D_EMU1 0.28.62
ILOGIC0:D_EMU2 0.29.61
ILOGIC0:IFF_DELAY_ENABLE 0.29.11
ILOGIC0:IFF_SR_USED 0.26.57
ILOGIC0:IFF_TSBYPASS_ENABLE 0.28.14
ILOGIC0:INV.CLKDIV 0.27.8
ILOGIC0:INV.CLKDIVP 0.26.13
ILOGIC0:INV.OCLK1 0.29.63
ILOGIC0:INV.OCLK2 0.29.3
ILOGIC0:I_DELAY_ENABLE 0.28.26
ILOGIC0:I_TSBYPASS_ENABLE 0.28.24
ILOGIC0:RANK23_DLY 0.26.27
ILOGIC0:SERDES 0.26.25
IOB0:DCIUPDATEMODE_QUIET 0.38.56
IOB0:DCI_T 0.39.63
IOB0:DQS_BIAS_N 0.38.36
IOB0:DQS_BIAS_P 0.39.29
IOB0:INPUT_MISC 0.39.5
IOB0:OUTPUT_DELAY 0.38.52
IOB0:PULL_DYNAMIC 0.38.6
IOB0:VR 0.38.18
ODELAY0:CINVCTRL_SEL 0.36.38
ODELAY0:ENABLE 0.35.54
ODELAY0:HIGH_PERFORMANCE_MODE 0.35.18
ODELAY0:INV.C 0.37.39
ODELAY0:PIPE_SEL 0.37.21
OLOGIC0:INV.CLKDIV 0.31.42
OLOGIC0:INV.CLKDIVF 0.30.33
OLOGIC0:INV.D1 0.31.30
OLOGIC0:INV.D2 0.30.25
OLOGIC0:INV.D3 0.30.21
OLOGIC0:INV.D4 0.30.17
OLOGIC0:INV.D5 0.31.14
OLOGIC0:INV.D6 0.30.13
OLOGIC0:INV.D7 0.30.9
OLOGIC0:INV.D8 0.31.2
OLOGIC0:MISR_ENABLE 0.31.16
OLOGIC0:MISR_ENABLE_FDBK 0.31.10
OLOGIC0:MISR_RESET 0.31.8
OLOGIC0:OFF_SR_SYNC 0.33.33
OLOGIC0:OFF_SR_USED 0.33.15
OLOGIC0:SELFHEAL 0.30.31
OLOGIC0:SERDES 0.32.54
OLOGIC0:TBYTE_CTL 0.33.47
OLOGIC0:TBYTE_SRC 0.33.43
OLOGIC0:TFF_SR_SYNC 0.33.55
OLOGIC0:TFF_SR_USED 0.32.38
non-inverted [0]
IDELAY0:DELAY_SRC 0.35.57 0.34.56 0.34.58 0.35.55
NONE 0 0 0 0
IDATAIN 0 0 0 1
DATAIN 0 0 1 0
OFB 0 1 0 0
DELAYCHAIN_OSC 1 0 0 0
IDELAY0:FINEDELAY 0.28.58
ODELAY0:FINEDELAY 0.36.22
BYPASS 0
ADD_DLY 1
IDELAY0:IDELAY_TYPE 0.34.14 0.34.8
ODELAY0:ODELAY_TYPE 0.36.14 0.36.8
FIXED 0 0
VARIABLE 0 1
VAR_LOAD 1 1
IDELAY0:IDELAY_VALUE_CUR 0.35.33 0.35.27 0.35.19 0.35.13 0.35.7
ODELAY0:ODELAY_VALUE_CUR 0.37.33 0.37.27 0.37.19 0.37.13 0.37.7
inverted ~[4] ~[3] ~[2] ~[1] ~[0]
IDELAY0:IDELAY_VALUE_INIT 0.35.31 0.35.25 0.35.17 0.35.11 0.35.5
IOB0:NSLEW 0.38.14 0.38.22 0.38.38 0.39.45 0.38.46
IOB0:PSLEW 0.39.13 0.38.16 0.38.26 0.38.30 0.38.50
ODELAY0:ODELAY_VALUE_INIT 0.37.31 0.37.25 0.37.17 0.37.11 0.37.5
non-inverted [4] [3] [2] [1] [0]
ILOGIC0:DATA_RATE 0.26.19
DDR 0
SDR 1
ILOGIC0:DATA_WIDTH 0.27.18 0.26.17 0.27.16 0.26.15
NONE 0 0 0 0
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
10 1 0 1 0
14 1 1 1 0
ILOGIC0:DDR_CLK_EDGE 0.27.28 0.26.29
SAME_EDGE_PIPELINED 0 0
OPPOSITE_EDGE 0 1
SAME_EDGE 1 0
ILOGIC0:IFF1_INIT 0.29.55
ILOGIC0:IFF1_SRVAL 0.28.56
ILOGIC0:IFF2_INIT 0.29.51
ILOGIC0:IFF2_SRVAL 0.28.52
ILOGIC0:IFF3_INIT 0.29.41
ILOGIC0:IFF3_SRVAL 0.28.42
ILOGIC0:IFF4_INIT 0.29.33
ILOGIC0:IFF4_SRVAL 0.28.34
ILOGIC0:IFF_LATCH 0.27.56
ILOGIC0:INV.D 0.28.18
ODELAY0:INV.ODATAIN 0.34.55
OLOGIC0:INV.CLK1 0.30.37
OLOGIC0:INV.CLK2 0.30.35
OLOGIC0:INV.T1 0.31.60
OLOGIC0:INV.T2 0.31.56
OLOGIC0:INV.T3 0.30.51
OLOGIC0:INV.T4 0.31.48
OLOGIC0:OFF_INIT 0.32.30
OLOGIC0:RANK3_USED 0.30.41
OLOGIC0:TFF_INIT 0.31.52
inverted ~[0]
ILOGIC0:INTERFACE_TYPE 0.27.12 0.27.14 0.27.10 0.27.26 0.27.6
MEMORY 0 0 0 0 0
NETWORKING 0 0 0 0 1
MEMORY_DDR3 0 0 1 1 1
MEMORY_DDR3_V6 0 1 0 1 1
OVERSAMPLE 1 0 0 1 1
ILOGIC0:INV.CLK 0.29.1 0.28.4 0.28.2
OLOGIC0:OFF_SRVAL 0.33.19 0.32.32 0.32.20
OLOGIC0:TFF_SRVAL 0.33.45 0.32.52 0.32.46
inverted ~[2] ~[1] ~[0]
ILOGIC0:MUX.CLK 0.29.50 0.28.51 0.29.52 0.28.47 0.28.49 0.29.46 0.29.48 0.28.53 0.29.60 0.29.62 0.28.61
ILOGIC0:MUX.CLKB 0.30.50 0.31.51 0.30.52 0.31.47 0.31.49 0.30.46 0.30.48 0.31.53 0.30.60 0.30.62 0.31.61
NONE 0 0 0 0 0 0 0 0 0 0 0
PHASER_ICLK 0 0 0 0 0 0 0 0 0 0 1
PHASER_OCLK 0 0 0 0 0 0 0 0 0 1 0
HCLK0 0 0 0 0 0 0 1 1 1 0 0
HCLK1 0 0 0 0 0 1 0 1 1 0 0
HCLK2 0 0 0 0 1 0 0 1 1 0 0
HCLK3 0 0 0 1 0 0 0 1 1 0 0
HCLK4 0 0 1 0 0 0 1 0 1 0 0
HCLK5 0 0 1 0 0 1 0 0 1 0 0
RCLK0 0 0 1 0 1 0 0 0 1 0 0
RCLK1 0 0 1 1 0 0 0 0 1 0 0
RCLK2 0 1 0 0 0 0 1 0 1 0 0
RCLK3 0 1 0 0 0 1 0 0 1 0 0
IOCLK0 0 1 0 0 1 0 0 0 1 0 0
IOCLK1 0 1 0 1 0 0 0 0 1 0 0
IOCLK2 1 0 0 0 0 0 1 0 1 0 0
IOCLK3 1 0 0 0 0 1 0 0 1 0 0
CKINT1 1 0 0 0 1 0 0 0 1 0 0
CKINT0 1 0 0 1 0 0 0 0 1 0 0
ILOGIC0:MUX.CLKDIVP 0.29.28 0.28.29
NONE 0 0
CLKDIV 0 1
PHASER 1 0
ILOGIC0:NUM_CE 0.26.47
1 0
2 1
ILOGIC0:SERDES_MODE 0.26.21
OLOGIC0:SERDES_MODE 0.32.44
MASTER 0
SLAVE 1
ILOGIC0:SRTYPE 0.28.60
ASYNC 0
SYNC 1
ILOGIC0:TSBYPASS_MUX 0.29.17
T 0
GND 1
IOB0:DCITERMDISABLE_SEL 0.38.62
IOB0:IBUFDISABLE_SEL 0.39.39
GND 0
I 1
IOB0:DCI_MODE 0.39.53 0.38.42
NONE 0 0
OUTPUT 0 1
OUTPUT_HALF 1 0
TERM_SPLIT 1 1
IOB0:IBUF_MODE 0.38.2 0.39.1 0.38.0
OFF 0 0 0
VREF_LP 0 0 1
CMOS 0 1 1
VREF_HP 1 0 1
IOB0:LVDS 0.39.41 0.38.54 0.38.40 0.39.37 0.38.28 0.39.25 0.39.21 0.39.15 0.38.8
non-inverted [8] [7] [6] [5] [4] [3] [2] [1] [0]
IOB0:NDRIVE 0.38.20 0.38.24 0.39.35 0.39.47 0.39.55 0.39.27 0.39.51
mixed inversion [6] ~[5] [4] ~[3] [2] [1] [0]
IOB0:OUTPUT_ENABLE 0.38.34 0.38.32
non-inverted [1] [0]
IOB0:OUTPUT_MISC 0.39.19 0.39.11 0.39.57 0.39.9 0.38.60 0.38.58
non-inverted [5] [4] [3] [2] [1] [0]
IOB0:PDRIVE 0.39.23 0.39.33 0.38.44 0.39.49 0.38.48 0.39.31 0.39.61
mixed inversion [6] ~[5] [4] ~[3] ~[2] [1] [0]
IOB0:PULL 0.38.4 0.38.10 0.38.12
PULLDOWN 0 0 0
NONE 0 0 1
PULLUP 0 1 1
KEEPER 1 0 1
ODELAY0:DELAY_SRC 0.37.57 0.36.56 0.37.55
NONE 0 0 0
ODATAIN 0 0 1
CLKIN 0 1 0
DELAYCHAIN_OSC 1 0 0
OLOGIC0:CLK_RATIO 0.30.27 0.30.29 0.31.32 0.31.28
NONE 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 1
7_8 1 1 0 0
6 1 1 0 1
OLOGIC0:DATA_WIDTH 0.31.26 0.31.12 0.30.11 0.31.4 0.30.7 0.31.6 0.30.3 0.30.1 0.31.0
NONE 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 1
3 0 0 0 0 0 0 0 1 0
4 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 1 0 0 0
6 0 0 0 0 1 0 0 0 0
7 0 0 0 1 0 0 0 0 0
8 0 0 1 0 0 0 0 0 0
10 0 1 0 0 0 0 0 0 0
14 1 0 0 0 0 0 0 0 0
OLOGIC0:MISR_CLK_SELECT 0.30.5 0.30.15
NONE 0 0
CLK1 0 1
CLK2 1 0
OLOGIC0:MUX.CLK 0.29.34 0.28.35 0.29.38 0.28.31 0.28.33 0.29.30 0.29.32 0.28.39 0.28.43 0.28.45 0.29.44
OLOGIC0:MUX.CLKB 0.30.34 0.31.35 0.30.38 0.31.31 0.31.33 0.30.30 0.30.32 0.31.39 0.31.43 0.31.45 0.30.44
NONE 0 0 0 0 0 0 0 0 0 0 0
PHASER_OCLK 0 0 0 0 0 0 0 0 0 1 0
PHASER_OCLK90 0 0 0 0 0 0 0 0 1 0 0
HCLK0 0 0 0 0 0 0 1 1 0 0 1
HCLK1 0 0 0 0 0 1 0 1 0 0 1
HCLK2 0 0 0 0 1 0 0 1 0 0 1
HCLK3 0 0 0 1 0 0 0 1 0 0 1
HCLK4 0 0 1 0 0 0 1 0 0 0 1
HCLK5 0 0 1 0 0 1 0 0 0 0 1
RCLK0 0 0 1 0 1 0 0 0 0 0 1
RCLK1 0 0 1 1 0 0 0 0 0 0 1
RCLK2 0 1 0 0 0 0 1 0 0 0 1
RCLK3 0 1 0 0 0 1 0 0 0 0 1
IOCLK0 0 1 0 0 1 0 0 0 0 0 1
IOCLK1 0 1 0 1 0 0 0 0 0 0 1
IOCLK2 1 0 0 0 0 0 1 0 0 0 1
IOCLK3 1 0 0 0 0 1 0 0 0 0 1
CKINT 1 0 0 0 1 0 0 0 0 0 1
OLOGIC0:MUX.CLKDIV 0.28.17 0.29.16
NONE 0 0
CLKDIVF 0 1
PHASER_OCLKDIV 1 0
OLOGIC0:MUX.CLKDIVB 0.31.17 0.30.16
NONE 0 0
CLKDIVFB 0 1
PHASER_OCLKDIV 1 0
OLOGIC0:MUX.CLKDIVF 0.29.6 0.29.8 0.28.9 0.29.2 0.29.4 0.28.1 0.28.3
OLOGIC0:MUX.CLKDIVFB 0.30.6 0.30.8 0.31.9 0.30.2 0.30.4 0.31.1 0.31.3
NONE 0 0 0 0 0 0 0
HCLK0 0 0 1 0 0 0 1
HCLK1 0 0 1 0 0 1 0
HCLK2 0 0 1 0 1 0 0
HCLK3 0 0 1 1 0 0 0
HCLK4 0 1 0 0 0 0 1
HCLK5 0 1 0 0 0 1 0
RCLK0 0 1 0 0 1 0 0
RCLK1 0 1 0 1 0 0 0
RCLK2 1 0 0 0 0 0 1
RCLK3 1 0 0 0 0 1 0
CKINT 1 0 0 0 1 0 0
OLOGIC0:OMUX 0.33.17 0.32.14 0.32.36 0.32.34 0.32.16
NONE 0 0 0 0 0
D1 0 0 0 0 1
SERDES_SDR 0 0 0 1 0
DDR 0 0 1 0 0
FF 0 1 0 1 0
LATCH 1 0 0 1 0
OLOGIC0:TMUX 0.32.60 0.33.59 0.33.57 0.32.58 0.33.61
NONE 0 0 0 0 0
T1 0 0 0 0 1
SERDES_SDR 0 0 0 1 0
DDR 0 0 1 0 0
FF 0 1 0 1 0
LATCH 1 0 0 1 0
OLOGIC0:TRISTATE_WIDTH 0.33.37
1 0
4 1

Bitstream — IO_HR_PAIR

virtex7 IO_HR_PAIR bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.OCLK1 - - - - - - - - - IOB0:OUTPUT_ENABLE[1]
62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:D_EMU1 ILOGIC0:MUX.CLK[1] ILOGIC0:MUX.CLKB[1] - - - - - - - IOB0:OUTPUT_ENABLE[0] -
61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[0] ILOGIC0:D_EMU2 - ILOGIC0:MUX.CLKB[0] - OLOGIC0:TMUX[0] - - - - - IOB0:OMUX[1]
60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:SRTYPE[0] ILOGIC0:MUX.CLK[2] ILOGIC0:MUX.CLKB[2] ~OLOGIC0:INV.T1 OLOGIC0:TMUX[4] - - - - - IOB0:OUTPUT_MISC_B -
59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TMUX[3] - - - - - IOB0:OMUX[0]
58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TMUX[1] - IDELAY0:DELAY_SRC[1] - - - - -
57 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_SR_USED - - - - - - OLOGIC0:TMUX[2] - IDELAY0:DELAY_SRC[3] - - - -
56 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF_LATCH ~ILOGIC0:IFF1_SRVAL - - ~OLOGIC0:INV.T2 - - IDELAY0:DELAY_SRC[2] - - - - -
55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF1_INIT - - IDELAY0:INV.IDATAIN OLOGIC0:TFF_SR_SYNC - IDELAY0:DELAY_SRC[0] - - - -
54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:SERDES IDELAY0:ENABLE - - - - - -
53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[3] - - ILOGIC0:MUX.CLKB[3] - - - - - - - IOB0:LVDS[0]
52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF2_SRVAL ILOGIC0:MUX.CLK[8] ILOGIC0:MUX.CLKB[8] ~OLOGIC0:TFF_INIT ~OLOGIC0:TFF_SRVAL[1] - - - - - IOB0:LVDS[1] -
51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[9] ~ILOGIC0:IFF2_INIT ~OLOGIC0:INV.T3 ILOGIC0:MUX.CLKB[9] - - - - - - - IOB0:LVDS[2]
50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[10] ILOGIC0:MUX.CLKB[10] - - - - - - - IOB0:LVDS[3] -
49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[6] - - ILOGIC0:MUX.CLKB[6] - - - - - - - IOB0:LVDS[4]
48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[4] ILOGIC0:MUX.CLKB[4] ~OLOGIC0:INV.T4 - - - - - - IOB0:LVDS[5] -
47 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:NUM_CE[0] - ILOGIC0:MUX.CLK[7] - - ILOGIC0:MUX.CLKB[7] - OLOGIC0:TBYTE_CTL - - - - - IOB0:INPUT_MISC
46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IDELAY_VALUE[4] ILOGIC0:MUX.CLK[5] ILOGIC0:MUX.CLKB[5] - ~OLOGIC0:TFF_SRVAL[0] - IDELAY0:INV.DATAIN - - - IOB0:IBUF_MODE[3] -
45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[1] ILOGIC0:IFFDELAY_VALUE[4] - OLOGIC0:MUX.CLKB[1] - ~OLOGIC0:TFF_SRVAL[2] - - - - - IOB0:IBUFDISABLE_SEL[0]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[0] OLOGIC0:MUX.CLKB[0] - OLOGIC0:SERDES_MODE[0] - - - - - IOB0:IBUF_MODE[5] -
43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[2] - - OLOGIC0:MUX.CLKB[2] - OLOGIC0:TBYTE_SRC - - - - - IOB0:IBUF_MODE[4]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF3_SRVAL - - OLOGIC0:INV.CLKDIV - - - - - - IOB0:IBUF_MODE[2] -
41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF3_INIT ~OLOGIC0:RANK3_USED - - - - - - - - IOB0:IBUF_MODE[1]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB0:IBUF_MODE[0] -
39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[3] - - OLOGIC0:MUX.CLKB[3] - - - IDELAY0:INV.C - - - IOB0:VREF_SYSMON
38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IDELAY_VALUE[3] OLOGIC0:MUX.CLK[8] OLOGIC0:MUX.CLKB[8] - OLOGIC0:TFF_SR_USED - IDELAY0:CINVCTRL_SEL - - - IOB0:INTERMDISABLE_SEL[0] -
37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFFDELAY_VALUE[3] ~OLOGIC0:INV.CLK1 - - OLOGIC0:TRISTATE_WIDTH[0] - - - - - IOB0:DQS_BIAS
36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:OMUX[2] - - - - - IOB0:PULL_DYNAMIC -
35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[9] - ~OLOGIC0:INV.CLK2 OLOGIC0:MUX.CLKB[9] - - - - - - - IOB0:PULL[2]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF4_SRVAL OLOGIC0:MUX.CLK[10] OLOGIC0:MUX.CLKB[10] - OLOGIC0:OMUX[1] - - - - - IOB0:PULL[1] -
33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[6] ~ILOGIC0:IFF4_INIT OLOGIC0:INV.CLKDIVF OLOGIC0:MUX.CLKB[6] - OLOGIC0:OFF_SR_SYNC - ~IDELAY0:IDELAY_VALUE_CUR[4] - - - IOB0:PULL[0]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[4] OLOGIC0:MUX.CLKB[4] OLOGIC0:CLK_RATIO[1] ~OLOGIC0:OFF_SRVAL[1] - - - - - IOB0:LOW_VOLTAGE -
31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[7] ILOGIC0:INV.ZHOLD_FABRIC OLOGIC0:SELFHEAL OLOGIC0:MUX.CLKB[7] - - - IDELAY0:IDELAY_VALUE_INIT[4] - - - IOB0:LVDS[6]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:I_ZHOLD OLOGIC0:MUX.CLK[5] OLOGIC0:MUX.CLKB[5] OLOGIC0:INV.D1 ~OLOGIC0:OFF_INIT - - - - - IOB0:LVDS[7] -
29 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DDR_CLK_EDGE[0] - ILOGIC0:MUX.CLKDIVP[0] - OLOGIC0:CLK_RATIO[2] - - - - - - - - IOB0:LVDS[8]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DDR_CLK_EDGE[1] - ILOGIC0:MUX.CLKDIVP[1] - OLOGIC0:CLK_RATIO[0] - - - - - - IOB0:LVDS[9] -
27 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:RANK23_DLY - - - OLOGIC0:CLK_RATIO[3] - - - - ~IDELAY0:IDELAY_VALUE_CUR[3] - - - IOB0:LVDS[10]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[1] ILOGIC0:I_DELAY_ENABLE - - OLOGIC0:DATA_WIDTH[8] - - - - - - IOB0:LVDS[11] -
25 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:SERDES - - ILOGIC0:ZHOLD_ENABLE OLOGIC0:INV.D2 - - - - IDELAY0:IDELAY_VALUE_INIT[3] - - - IOB0:LVDS[12]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:I_TSBYPASS_ENABLE - - - - - - - - - IOB0:LVDS_GROUP -
23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IDELAY_VALUE[2] - - - - - - - - - IOB0:SLEW[9]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFFDELAY_VALUE[2] - - - - - - - - - IOB0:SLEW[8] -
21 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:SERDES_MODE[0] - - - OLOGIC0:INV.D3 - - - - IDELAY0:PIPE_SEL - - - IOB0:SLEW[7]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:BITSLIP_ENABLE - - - - ~OLOGIC0:OFF_SRVAL[0] - - - - - IOB0:SLEW[6] -
19 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_RATE[0] - - - - - - ~OLOGIC0:OFF_SRVAL[2] - ~IDELAY0:IDELAY_VALUE_CUR[2] - - - IOB0:SLEW[5]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[3] ~ILOGIC0:INV.D - - - - IDELAY0:HIGH_PERFORMANCE_MODE - - - - IOB0:SLEW[4] -
17 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[2] - OLOGIC0:MUX.CLKDIV[1] ILOGIC0:TSBYPASS_MUX[0] OLOGIC0:INV.D4 OLOGIC0:MUX.CLKDIVB[1] - OLOGIC0:OMUX[4] - IDELAY0:IDELAY_VALUE_INIT[2] - - - IOB0:SLEW[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[1] ILOGIC0:IDELAY_VALUE[1] OLOGIC0:MUX.CLKDIV[0] OLOGIC0:MUX.CLKDIVB[0] OLOGIC0:MISR_ENABLE OLOGIC0:OMUX[0] - - - - - IOB0:SLEW[2] -
15 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[0] - - ILOGIC0:IFFDELAY_VALUE[1] OLOGIC0:MISR_CLK_SELECT[0] - - OLOGIC0:OFF_SR_USED - - - - - IOB0:SLEW[1]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[3] ILOGIC0:IFF_TSBYPASS_ENABLE - - OLOGIC0:INV.D5 OLOGIC0:OMUX[3] - IDELAY0:IDELAY_TYPE[1] - - - ~IOB0:SLEW[0] -
13 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.CLKDIVP - - - OLOGIC0:INV.D6 - - - - ~IDELAY0:IDELAY_VALUE_CUR[1] - - - IOB0:OUTPUT_MISC[2]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[4] - - - OLOGIC0:DATA_WIDTH[7] - - - - - - IOB0:OUTPUT_MISC[1] -
11 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLKDIVP_INV_EN - - ILOGIC0:IFF_DELAY_ENABLE OLOGIC0:DATA_WIDTH[6] - - - - IDELAY0:IDELAY_VALUE_INIT[1] - - - IOB0:OUTPUT_MISC[0]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[2] ILOGIC0:IDELAY_VALUE[0] - - OLOGIC0:MISR_ENABLE_FDBK - - - - - - IOB0:DRIVE[6] -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLKDIV_INV_EN - OLOGIC0:MUX.CLKDIVF[4] ILOGIC0:IFFDELAY_VALUE[0] OLOGIC0:INV.D7 OLOGIC0:MUX.CLKDIVFB[4] - - - - - - - ~IOB0:DRIVE[5]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.CLKDIV ILOGIC0:IFF_ZHOLD OLOGIC0:MUX.CLKDIVF[5] OLOGIC0:MUX.CLKDIVFB[5] OLOGIC0:MISR_RESET - - IDELAY0:IDELAY_TYPE[0] - - - ~IOB0:DRIVE[4] -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.ZHOLD_IFF OLOGIC0:DATA_WIDTH[4] - - - - ~IDELAY0:IDELAY_VALUE_CUR[0] - - - IOB0:IN_TERM[1]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[0] - OLOGIC0:MUX.CLKDIVF[6] OLOGIC0:MUX.CLKDIVFB[6] OLOGIC0:DATA_WIDTH[3] - - - - - - IOB0:IN_TERM[3] -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MISR_CLK_SELECT[1] - - - - IDELAY0:IDELAY_VALUE_INIT[0] - - - IOB0:IN_TERM[2]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INV.CLK[1] OLOGIC0:MUX.CLKDIVF[2] OLOGIC0:MUX.CLKDIVFB[2] OLOGIC0:DATA_WIDTH[5] - - - - - - IOB0:IN_TERM[0] -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLKDIVF[0] ILOGIC0:INV.OCLK2 OLOGIC0:DATA_WIDTH[2] OLOGIC0:MUX.CLKDIVFB[0] - - - - - - - IOB0:DRIVE[3]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INV.CLK[0] OLOGIC0:MUX.CLKDIVF[3] OLOGIC0:MUX.CLKDIVFB[3] OLOGIC0:INV.D8 - - - - - - ~IOB0:DRIVE[2] -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLKDIVF[1] ~ILOGIC0:INV.CLK[2] OLOGIC0:DATA_WIDTH[1] OLOGIC0:MUX.CLKDIVFB[1] - - - - - - - IOB0:DRIVE[1]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLK_INV_EN - - OLOGIC0:DATA_WIDTH[0] - - - - - - IOB0:DRIVE[0] -
virtex7 IO_HR_PAIR bittile 1
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DYN_CLK_INV_EN OLOGIC1:DATA_WIDTH[0] - - - - - - - - IOB1:DRIVE[0]
62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INV.CLK[0] OLOGIC1:MUX.CLKDIVF[1] OLOGIC1:MUX.CLKDIVFB[1] OLOGIC1:DATA_WIDTH[1] - - - - - - IOB1:DRIVE[1] -
61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLKDIVF[3] ~ILOGIC1:INV.CLK[2] OLOGIC1:INV.D8 OLOGIC1:MUX.CLKDIVFB[3] - - - - - - - ~IOB1:DRIVE[2]
60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INV.OCLK2 OLOGIC1:MUX.CLKDIVF[0] OLOGIC1:MUX.CLKDIVFB[0] OLOGIC1:DATA_WIDTH[2] - - - - - - IOB1:DRIVE[3] -
59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLKDIVF[2] ~ILOGIC1:INV.CLK[1] OLOGIC1:DATA_WIDTH[5] OLOGIC1:MUX.CLKDIVFB[2] - - - - - - - IOB1:IN_TERM[1]
58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MISR_CLK_SELECT[1] - - IDELAY1:IDELAY_VALUE_INIT[0] - - - IOB1:IN_TERM[2] -
57 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INTERFACE_TYPE[0] - OLOGIC1:MUX.CLKDIVF[6] - OLOGIC1:DATA_WIDTH[3] OLOGIC1:MUX.CLKDIVFB[6] - - - - - - - IOB1:IN_TERM[3]
56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INV.ZHOLD_IFF - - OLOGIC1:DATA_WIDTH[4] - - ~IDELAY1:IDELAY_VALUE_CUR[0] - - - IOB1:IN_TERM[0] -
55 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INV.CLKDIV - OLOGIC1:MUX.CLKDIVF[5] ILOGIC1:IFF_ZHOLD OLOGIC1:MISR_RESET OLOGIC1:MUX.CLKDIVFB[5] - - - IDELAY1:IDELAY_TYPE[0] - - - ~IOB1:DRIVE[4]
54 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DYN_CLKDIV_INV_EN ILOGIC1:IFFDELAY_VALUE[0] OLOGIC1:MUX.CLKDIVF[4] OLOGIC1:MUX.CLKDIVFB[4] OLOGIC1:INV.D7 - - - - - - ~IOB1:DRIVE[5] -
53 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INTERFACE_TYPE[2] - - ILOGIC1:IDELAY_VALUE[0] OLOGIC1:MISR_ENABLE_FDBK - - - - - - - - IOB1:DRIVE[6]
52 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DYN_CLKDIVP_INV_EN ILOGIC1:IFF_DELAY_ENABLE - - OLOGIC1:DATA_WIDTH[6] - - IDELAY1:IDELAY_VALUE_INIT[1] - - - IOB1:OUTPUT_MISC[0] -
51 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INTERFACE_TYPE[4] - - - OLOGIC1:DATA_WIDTH[7] - - - - - - - - IOB1:OUTPUT_MISC[1]
50 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INV.CLKDIVP - - - OLOGIC1:INV.D6 - - ~IDELAY1:IDELAY_VALUE_CUR[1] - - - IOB1:OUTPUT_MISC[2] -
49 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INTERFACE_TYPE[3] - - ILOGIC1:IFF_TSBYPASS_ENABLE OLOGIC1:INV.D5 - - OLOGIC1:OMUX[3] - IDELAY1:IDELAY_TYPE[1] - - - ~IOB1:SLEW[0]
48 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DATA_WIDTH[0] ILOGIC1:IFFDELAY_VALUE[1] - - OLOGIC1:MISR_CLK_SELECT[0] OLOGIC1:OFF_SR_USED - - - - - IOB1:SLEW[1] -
47 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DATA_WIDTH[1] - OLOGIC1:MUX.CLKDIV[0] ILOGIC1:IDELAY_VALUE[1] OLOGIC1:MISR_ENABLE OLOGIC1:MUX.CLKDIVB[0] - OLOGIC1:OMUX[0] - - - - - IOB1:SLEW[2]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DATA_WIDTH[2] ILOGIC1:TSBYPASS_MUX[0] OLOGIC1:MUX.CLKDIV[1] OLOGIC1:MUX.CLKDIVB[1] OLOGIC1:INV.D4 OLOGIC1:OMUX[4] - IDELAY1:IDELAY_VALUE_INIT[2] - - - IOB1:SLEW[3] -
45 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DATA_WIDTH[3] - - ~ILOGIC1:INV.D - - IDELAY1:HIGH_PERFORMANCE_MODE - - - - - - IOB1:SLEW[4]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DATA_RATE[0] - - - - ~OLOGIC1:OFF_SRVAL[0] - ~IDELAY1:IDELAY_VALUE_CUR[2] - - - IOB1:SLEW[5] -
43 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:BITSLIP_ENABLE - - - - - - ~OLOGIC1:OFF_SRVAL[2] - - - - - IOB1:SLEW[6]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:SERDES_MODE[0] - - - OLOGIC1:INV.D3 - - IDELAY1:PIPE_SEL - - - IOB1:SLEW[7] -
41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IFFDELAY_VALUE[2] - - - - - - - - - IOB1:SLEW[8]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IDELAY_VALUE[2] - - - - - - - - - IOB1:SLEW[9] -
39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:I_TSBYPASS_ENABLE - - - - - - - - - IOB1:LVDS_GROUP
38 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:SERDES ILOGIC1:ZHOLD_ENABLE - - OLOGIC1:INV.D2 - - IDELAY1:IDELAY_VALUE_INIT[3] - - - IOB1:LVDS[12] -
37 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INTERFACE_TYPE[1] - - ILOGIC1:I_DELAY_ENABLE OLOGIC1:DATA_WIDTH[8] - - - - - - - - IOB1:LVDS[11]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:RANK23_DLY - - - OLOGIC1:CLK_RATIO[3] - - ~IDELAY1:IDELAY_VALUE_CUR[3] - - - IOB1:LVDS[10] -
35 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DDR_CLK_EDGE[1] - ILOGIC1:MUX.CLKDIVP[1] - OLOGIC1:CLK_RATIO[0] - - - - - - - - IOB1:LVDS[9]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DDR_CLK_EDGE[0] - ILOGIC1:MUX.CLKDIVP[0] - OLOGIC1:CLK_RATIO[2] - - - - - - IOB1:LVDS[8] -
33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[5] ILOGIC1:I_ZHOLD OLOGIC1:INV.D1 OLOGIC1:MUX.CLKB[5] - ~OLOGIC1:OFF_INIT - - - - - IOB1:LVDS[7]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INV.ZHOLD_FABRIC OLOGIC1:MUX.CLK[7] OLOGIC1:MUX.CLKB[7] OLOGIC1:SELFHEAL - - IDELAY1:IDELAY_VALUE_INIT[4] - - - IOB1:LVDS[6] -
31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[4] - OLOGIC1:CLK_RATIO[1] OLOGIC1:MUX.CLKB[4] - ~OLOGIC1:OFF_SRVAL[1] - - - - - IOB1:LOW_VOLTAGE
30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF4_INIT OLOGIC1:MUX.CLK[6] OLOGIC1:MUX.CLKB[6] OLOGIC1:INV.CLKDIVF OLOGIC1:OFF_SR_SYNC - ~IDELAY1:IDELAY_VALUE_CUR[4] - - - IOB1:PULL[0] -
29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[10] ~ILOGIC1:IFF4_SRVAL - OLOGIC1:MUX.CLKB[10] - OLOGIC1:OMUX[1] - - - - - IOB1:PULL[1]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[9] OLOGIC1:MUX.CLKB[9] ~OLOGIC1:INV.CLK2 - - - - - - IOB1:PULL[2] -
27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:OMUX[2] - - - - - IOB1:PULL_DYNAMIC
26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IFFDELAY_VALUE[3] - - ~OLOGIC1:INV.CLK1 OLOGIC1:TRISTATE_WIDTH[0] - - - - - IOB1:DQS_BIAS -
25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[8] ILOGIC1:IDELAY_VALUE[3] - OLOGIC1:MUX.CLKB[8] - OLOGIC1:TFF_SR_USED - IDELAY1:CINVCTRL_SEL - - - IOB1:INTERMDISABLE_SEL[0]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[3] OLOGIC1:MUX.CLKB[3] - - - IDELAY1:INV.C - - - IOB1:VREF_SYSMON -
23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB1:IBUF_MODE[0]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF3_INIT - - ~OLOGIC1:RANK3_USED - - - - - - IOB1:IBUF_MODE[1] -
21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF3_SRVAL OLOGIC1:INV.CLKDIV - - - - - - - - IOB1:IBUF_MODE[2]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[2] OLOGIC1:MUX.CLKB[2] - OLOGIC1:TBYTE_SRC - - - - - IOB1:IBUF_MODE[4] -
19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.CLK[0] - - OLOGIC1:MUX.CLKB[0] - OLOGIC1:SERDES_MODE[0] - - - - - IOB1:IBUF_MODE[5]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IFFDELAY_VALUE[4] OLOGIC1:MUX.CLK[1] OLOGIC1:MUX.CLKB[1] - ~OLOGIC1:TFF_SRVAL[0] - - - - - IOB1:IBUFDISABLE_SEL[0] -
17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.CLK[5] ILOGIC1:IDELAY_VALUE[4] - ILOGIC1:MUX.CLKB[5] - ~OLOGIC1:TFF_SRVAL[2] - IDELAY1:INV.DATAIN - - - IOB1:IBUF_MODE[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:NUM_CE[0] - ILOGIC1:MUX.CLK[7] ILOGIC1:MUX.CLKB[7] - OLOGIC1:TBYTE_CTL - - - - - IOB1:INPUT_MISC -
15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.CLK[4] - ~OLOGIC1:INV.T4 ILOGIC1:MUX.CLKB[4] - - - - - - - IOB1:LVDS[5]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.CLK[6] ILOGIC1:MUX.CLKB[6] - - - - - - - IOB1:LVDS[4] -
13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.CLK[10] - - ILOGIC1:MUX.CLKB[10] - - - - - - - IOB1:LVDS[3]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF2_INIT ILOGIC1:MUX.CLK[9] ILOGIC1:MUX.CLKB[9] ~OLOGIC1:INV.T3 - - - - - - IOB1:LVDS[2] -
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.CLK[8] ~ILOGIC1:IFF2_SRVAL ~OLOGIC1:TFF_INIT ILOGIC1:MUX.CLKB[8] - ~OLOGIC1:TFF_SRVAL[1] - - - - - IOB1:LVDS[1]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.CLK[3] ILOGIC1:MUX.CLKB[3] - - - - - - - IOB1:LVDS[0] -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY1:ENABLE OLOGIC1:SERDES - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF1_INIT - - - OLOGIC1:TFF_SR_SYNC IDELAY1:INV.IDATAIN IDELAY1:DELAY_SRC[0] - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF_LATCH - - ~ILOGIC1:IFF1_SRVAL ~OLOGIC1:INV.T2 - - - - IDELAY1:DELAY_SRC[2] - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IFF_SR_USED - - - - OLOGIC1:TMUX[2] - IDELAY1:DELAY_SRC[3] - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:TMUX[1] - IDELAY1:DELAY_SRC[1] - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:TMUX[3] - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.CLK[2] ILOGIC1:SRTYPE[0] ~OLOGIC1:INV.T1 ILOGIC1:MUX.CLKB[2] - OLOGIC1:TMUX[4] - - - - - IOB1:OUTPUT_MISC_B
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:D_EMU2 ILOGIC1:MUX.CLK[0] ILOGIC1:MUX.CLKB[0] - OLOGIC1:TMUX[0] - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.CLK[1] ILOGIC1:D_EMU1 - ILOGIC1:MUX.CLKB[1] - - - - - - - IOB1:OUTPUT_ENABLE[0]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INV.OCLK1 - - - - - - - - - IOB1:OUTPUT_ENABLE[1] -
IDELAY0:CINVCTRL_SEL 0.34.38
IDELAY0:ENABLE 0.33.54
IDELAY0:HIGH_PERFORMANCE_MODE 0.33.18
IDELAY0:INV.C 0.35.39
IDELAY0:INV.DATAIN 0.34.46
IDELAY0:INV.IDATAIN 0.32.55
IDELAY0:PIPE_SEL 0.35.21
IDELAY1:CINVCTRL_SEL 1.35.25
IDELAY1:ENABLE 1.32.9
IDELAY1:HIGH_PERFORMANCE_MODE 1.32.45
IDELAY1:INV.C 1.34.24
IDELAY1:INV.DATAIN 1.35.17
IDELAY1:INV.IDATAIN 1.33.8
IDELAY1:PIPE_SEL 1.34.42
ILOGIC0:BITSLIP_ENABLE 0.27.20
ILOGIC0:DYN_CLKDIVP_INV_EN 0.26.11
ILOGIC0:DYN_CLKDIV_INV_EN 0.26.9
ILOGIC0:DYN_CLK_INV_EN 0.28.0
ILOGIC0:D_EMU1 0.28.62
ILOGIC0:D_EMU2 0.29.61
ILOGIC0:IFF_DELAY_ENABLE 0.29.11
ILOGIC0:IFF_SR_USED 0.26.57
ILOGIC0:IFF_TSBYPASS_ENABLE 0.28.14
ILOGIC0:IFF_ZHOLD 0.28.8
ILOGIC0:INV.CLKDIV 0.27.8
ILOGIC0:INV.CLKDIVP 0.26.13
ILOGIC0:INV.OCLK1 0.29.63
ILOGIC0:INV.OCLK2 0.29.3
ILOGIC0:INV.ZHOLD_FABRIC 0.29.31
ILOGIC0:INV.ZHOLD_IFF 0.29.7
ILOGIC0:I_DELAY_ENABLE 0.28.26
ILOGIC0:I_TSBYPASS_ENABLE 0.28.24
ILOGIC0:I_ZHOLD 0.28.30
ILOGIC0:RANK23_DLY 0.26.27
ILOGIC0:SERDES 0.26.25
ILOGIC0:ZHOLD_ENABLE 0.29.25
ILOGIC1:BITSLIP_ENABLE 1.26.43
ILOGIC1:DYN_CLKDIVP_INV_EN 1.27.52
ILOGIC1:DYN_CLKDIV_INV_EN 1.27.54
ILOGIC1:DYN_CLK_INV_EN 1.29.63
ILOGIC1:D_EMU1 1.29.1
ILOGIC1:D_EMU2 1.28.2
ILOGIC1:IFF_DELAY_ENABLE 1.28.52
ILOGIC1:IFF_SR_USED 1.27.6
ILOGIC1:IFF_TSBYPASS_ENABLE 1.29.49
ILOGIC1:IFF_ZHOLD 1.29.55
ILOGIC1:INV.CLKDIV 1.26.55
ILOGIC1:INV.CLKDIVP 1.27.50
ILOGIC1:INV.OCLK1 1.28.0
ILOGIC1:INV.OCLK2 1.28.60
ILOGIC1:INV.ZHOLD_FABRIC 1.28.32
ILOGIC1:INV.ZHOLD_IFF 1.28.56
ILOGIC1:I_DELAY_ENABLE 1.29.37
ILOGIC1:I_TSBYPASS_ENABLE 1.29.39
ILOGIC1:I_ZHOLD 1.29.33
ILOGIC1:RANK23_DLY 1.27.36
ILOGIC1:SERDES 1.27.38
ILOGIC1:ZHOLD_ENABLE 1.28.38
IOB0:DQS_BIAS 0.39.37
IOB0:INPUT_MISC 0.39.47
IOB0:LOW_VOLTAGE 0.38.32
IOB0:LVDS_GROUP 0.38.24
IOB0:OUTPUT_MISC_B 0.38.60
IOB0:PULL_DYNAMIC 0.38.36
IOB0:VREF_SYSMON 0.39.39
IOB1:DQS_BIAS 1.38.26
IOB1:INPUT_MISC 1.38.16
IOB1:LOW_VOLTAGE 1.39.31
IOB1:LVDS_GROUP 1.39.39
IOB1:OUTPUT_MISC_B 1.39.3
IOB1:PULL_DYNAMIC 1.39.27
IOB1:VREF_SYSMON 1.38.24
OLOGIC0:INV.CLKDIV 0.31.42
OLOGIC0:INV.CLKDIVF 0.30.33
OLOGIC0:INV.D1 0.31.30
OLOGIC0:INV.D2 0.30.25
OLOGIC0:INV.D3 0.30.21
OLOGIC0:INV.D4 0.30.17
OLOGIC0:INV.D5 0.31.14
OLOGIC0:INV.D6 0.30.13
OLOGIC0:INV.D7 0.30.9
OLOGIC0:INV.D8 0.31.2
OLOGIC0:MISR_ENABLE 0.31.16
OLOGIC0:MISR_ENABLE_FDBK 0.31.10
OLOGIC0:MISR_RESET 0.31.8
OLOGIC0:OFF_SR_SYNC 0.33.33
OLOGIC0:OFF_SR_USED 0.33.15
OLOGIC0:SELFHEAL 0.30.31
OLOGIC0:SERDES 0.32.54
OLOGIC0:TBYTE_CTL 0.33.47
OLOGIC0:TBYTE_SRC 0.33.43
OLOGIC0:TFF_SR_SYNC 0.33.55
OLOGIC0:TFF_SR_USED 0.32.38
OLOGIC1:INV.CLKDIV 1.30.21
OLOGIC1:INV.CLKDIVF 1.31.30
OLOGIC1:INV.D1 1.30.33
OLOGIC1:INV.D2 1.31.38
OLOGIC1:INV.D3 1.31.42
OLOGIC1:INV.D4 1.31.46
OLOGIC1:INV.D5 1.30.49
OLOGIC1:INV.D6 1.31.50
OLOGIC1:INV.D7 1.31.54
OLOGIC1:INV.D8 1.30.61
OLOGIC1:MISR_ENABLE 1.30.47
OLOGIC1:MISR_ENABLE_FDBK 1.30.53
OLOGIC1:MISR_RESET 1.30.55
OLOGIC1:OFF_SR_SYNC 1.32.30
OLOGIC1:OFF_SR_USED 1.32.48
OLOGIC1:SELFHEAL 1.31.32
OLOGIC1:SERDES 1.33.9
OLOGIC1:TBYTE_CTL 1.32.16
OLOGIC1:TBYTE_SRC 1.32.20
OLOGIC1:TFF_SR_SYNC 1.32.8
OLOGIC1:TFF_SR_USED 1.33.25
non-inverted [0]
IDELAY0:DELAY_SRC 0.35.57 0.34.56 0.34.58 0.35.55
IDELAY1:DELAY_SRC 1.34.6 1.35.7 1.35.5 1.34.8
NONE 0 0 0 0
IDATAIN 0 0 0 1
DATAIN 0 0 1 0
OFB 0 1 0 0
DELAYCHAIN_OSC 1 0 0 0
IDELAY0:IDELAY_TYPE 0.34.14 0.34.8
IDELAY1:IDELAY_TYPE 1.35.49 1.35.55
FIXED 0 0
VARIABLE 0 1
VAR_LOAD 1 1
IDELAY0:IDELAY_VALUE_CUR 0.35.33 0.35.27 0.35.19 0.35.13 0.35.7
IDELAY1:IDELAY_VALUE_CUR 1.34.30 1.34.36 1.34.44 1.34.50 1.34.56
inverted ~[4] ~[3] ~[2] ~[1] ~[0]
IDELAY0:IDELAY_VALUE_INIT 0.35.31 0.35.25 0.35.17 0.35.11 0.35.5
IDELAY1:IDELAY_VALUE_INIT 1.34.32 1.34.38 1.34.46 1.34.52 1.34.58
ILOGIC0:IDELAY_VALUE 0.28.46 0.28.38 0.29.23 0.28.16 0.28.10
ILOGIC0:IFFDELAY_VALUE 0.29.45 0.29.37 0.28.22 0.29.15 0.29.9
ILOGIC1:IDELAY_VALUE 1.29.17 1.29.25 1.28.40 1.29.47 1.29.53
ILOGIC1:IFFDELAY_VALUE 1.28.18 1.28.26 1.29.41 1.28.48 1.28.54
non-inverted [4] [3] [2] [1] [0]
ILOGIC0:DATA_RATE 0.26.19
ILOGIC1:DATA_RATE 1.27.44
DDR 0
SDR 1
ILOGIC0:DATA_WIDTH 0.27.18 0.26.17 0.27.16 0.26.15
ILOGIC1:DATA_WIDTH 1.26.45 1.27.46 1.26.47 1.27.48
NONE 0 0 0 0
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
10 1 0 1 0
14 1 1 1 0
ILOGIC0:DDR_CLK_EDGE 0.27.28 0.26.29
ILOGIC1:DDR_CLK_EDGE 1.26.35 1.27.34
SAME_EDGE_PIPELINED 0 0
OPPOSITE_EDGE 0 1
SAME_EDGE 1 0
ILOGIC0:IFF1_INIT 0.29.55
ILOGIC0:IFF1_SRVAL 0.28.56
ILOGIC0:IFF2_INIT 0.29.51
ILOGIC0:IFF2_SRVAL 0.28.52
ILOGIC0:IFF3_INIT 0.29.41
ILOGIC0:IFF3_SRVAL 0.28.42
ILOGIC0:IFF4_INIT 0.29.33
ILOGIC0:IFF4_SRVAL 0.28.34
ILOGIC0:IFF_LATCH 0.27.56
ILOGIC0:INV.D 0.28.18
ILOGIC1:IFF1_INIT 1.28.8
ILOGIC1:IFF1_SRVAL 1.29.7
ILOGIC1:IFF2_INIT 1.28.12
ILOGIC1:IFF2_SRVAL 1.29.11
ILOGIC1:IFF3_INIT 1.28.22
ILOGIC1:IFF3_SRVAL 1.29.21
ILOGIC1:IFF4_INIT 1.28.30
ILOGIC1:IFF4_SRVAL 1.29.29
ILOGIC1:IFF_LATCH 1.26.7
ILOGIC1:INV.D 1.29.45
OLOGIC0:INV.CLK1 0.30.37
OLOGIC0:INV.CLK2 0.30.35
OLOGIC0:INV.T1 0.31.60
OLOGIC0:INV.T2 0.31.56
OLOGIC0:INV.T3 0.30.51
OLOGIC0:INV.T4 0.31.48
OLOGIC0:OFF_INIT 0.32.30
OLOGIC0:RANK3_USED 0.30.41
OLOGIC0:TFF_INIT 0.31.52
OLOGIC1:INV.CLK1 1.31.26
OLOGIC1:INV.CLK2 1.31.28
OLOGIC1:INV.T1 1.30.3
OLOGIC1:INV.T2 1.30.7
OLOGIC1:INV.T3 1.31.12
OLOGIC1:INV.T4 1.30.15
OLOGIC1:OFF_INIT 1.33.33
OLOGIC1:RANK3_USED 1.31.22
OLOGIC1:TFF_INIT 1.30.11
inverted ~[0]
ILOGIC0:INTERFACE_TYPE 0.27.12 0.27.14 0.27.10 0.27.26 0.27.6
ILOGIC1:INTERFACE_TYPE 1.26.51 1.26.49 1.26.53 1.26.37 1.26.57
MEMORY 0 0 0 0 0
NETWORKING 0 0 0 0 1
MEMORY_DDR3 0 0 1 1 1
MEMORY_DDR3_V6 0 1 0 1 1
OVERSAMPLE 1 0 0 1 1
ILOGIC0:INV.CLK 0.29.1 0.28.4 0.28.2
ILOGIC1:INV.CLK 1.29.61 1.29.59 1.28.62
OLOGIC0:OFF_SRVAL 0.33.19 0.32.32 0.32.20
OLOGIC0:TFF_SRVAL 0.33.45 0.32.52 0.32.46
OLOGIC1:OFF_SRVAL 1.33.43 1.33.31 1.32.44
OLOGIC1:TFF_SRVAL 1.33.17 1.33.11 1.32.18
inverted ~[2] ~[1] ~[0]
ILOGIC0:MUX.CLK 0.29.50 0.28.51 0.29.52 0.28.47 0.28.49 0.29.46 0.29.48 0.28.53 0.29.60 0.29.62 0.28.61
ILOGIC0:MUX.CLKB 0.30.50 0.31.51 0.30.52 0.31.47 0.31.49 0.30.46 0.30.48 0.31.53 0.30.60 0.30.62 0.31.61
ILOGIC1:MUX.CLK 1.28.13 1.29.12 1.28.11 1.29.16 1.29.14 1.28.17 1.28.15 1.29.10 1.28.3 1.28.1 1.29.2
ILOGIC1:MUX.CLKB 1.31.13 1.30.12 1.31.11 1.30.16 1.30.14 1.31.17 1.31.15 1.30.10 1.31.3 1.31.1 1.30.2
NONE 0 0 0 0 0 0 0 0 0 0 0
PHASER_ICLK 0 0 0 0 0 0 0 0 0 0 1
PHASER_OCLK 0 0 0 0 0 0 0 0 0 1 0
HCLK0 0 0 0 0 0 0 1 1 1 0 0
HCLK1 0 0 0 0 0 1 0 1 1 0 0
HCLK2 0 0 0 0 1 0 0 1 1 0 0
HCLK3 0 0 0 1 0 0 0 1 1 0 0
HCLK4 0 0 1 0 0 0 1 0 1 0 0
HCLK5 0 0 1 0 0 1 0 0 1 0 0
RCLK0 0 0 1 0 1 0 0 0 1 0 0
RCLK1 0 0 1 1 0 0 0 0 1 0 0
RCLK2 0 1 0 0 0 0 1 0 1 0 0
RCLK3 0 1 0 0 0 1 0 0 1 0 0
IOCLK0 0 1 0 0 1 0 0 0 1 0 0
IOCLK1 0 1 0 1 0 0 0 0 1 0 0
IOCLK2 1 0 0 0 0 0 1 0 1 0 0
IOCLK3 1 0 0 0 0 1 0 0 1 0 0
CKINT1 1 0 0 0 1 0 0 0 1 0 0
CKINT0 1 0 0 1 0 0 0 0 1 0 0
ILOGIC0:MUX.CLKDIVP 0.29.28 0.28.29
ILOGIC1:MUX.CLKDIVP 1.28.35 1.29.34
NONE 0 0
CLKDIV 0 1
PHASER 1 0
ILOGIC0:NUM_CE 0.26.47
ILOGIC1:NUM_CE 1.27.16
1 0
2 1
ILOGIC0:SERDES_MODE 0.26.21
ILOGIC1:SERDES_MODE 1.27.42
OLOGIC0:SERDES_MODE 0.32.44
OLOGIC1:SERDES_MODE 1.33.19
MASTER 0
SLAVE 1
ILOGIC0:SRTYPE 0.28.60
ILOGIC1:SRTYPE 1.29.3
ASYNC 0
SYNC 1
ILOGIC0:TSBYPASS_MUX 0.29.17
ILOGIC1:TSBYPASS_MUX 1.28.46
T 0
GND 1
IOB0:DRIVE 0.38.10 0.39.9 0.38.8 0.39.3 0.38.2 0.39.1 0.38.0
IOB1:DRIVE 1.39.53 1.38.54 1.39.55 1.38.60 1.39.61 1.38.62 1.39.63
mixed inversion [6] ~[5] ~[4] [3] ~[2] [1] [0]
IOB0:IBUFDISABLE_SEL 0.39.45
IOB0:INTERMDISABLE_SEL 0.38.38
IOB1:IBUFDISABLE_SEL 1.38.18
IOB1:INTERMDISABLE_SEL 1.39.25
GND 0
I 1
IOB0:IBUF_MODE 0.38.44 0.39.43 0.38.46 0.38.42 0.39.41 0.38.40
IOB1:IBUF_MODE 1.39.19 1.38.20 1.39.17 1.39.21 1.38.22 1.39.23
OFF 0 0 0 0 0 0
VREF_LP 0 0 0 0 0 1
TMDS_LP 0 0 0 0 1 0
DIFF_LP 0 0 0 0 1 1
CMOS_LV 0 0 0 1 1 0
CMOS_HV 0 0 0 1 1 1
PCI 0 0 1 1 1 1
VREF_HP 0 1 0 0 0 1
TMDS_HP 1 0 0 0 1 0
DIFF_HP 1 0 0 0 1 1
IOB0:IN_TERM 0.38.6 0.39.5 0.39.7 0.38.4
IOB1:IN_TERM 1.39.57 1.38.58 1.39.59 1.38.56
NONE 0 0 0 0
UNTUNED_SPLIT_60 0 0 1 1
UNTUNED_SPLIT_50 0 1 1 1
UNTUNED_SPLIT_40 1 1 1 1
IOB0:LVDS 0.39.25 0.38.26 0.39.27 0.38.28 0.39.29 0.38.30 0.39.31 0.38.48 0.39.49 0.38.50 0.39.51 0.38.52 0.39.53
IOB1:LVDS 1.38.38 1.39.37 1.38.36 1.39.35 1.38.34 1.39.33 1.38.32 1.39.15 1.38.14 1.39.13 1.38.12 1.39.11 1.38.10
non-inverted [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
IOB0:OMUX 0.39.61 0.39.59
O 0 0
OTHER_O_INV 1 1
IOB0:OUTPUT_ENABLE 0.39.63 0.38.62
IOB1:OUTPUT_ENABLE 1.38.0 1.39.1
non-inverted [1] [0]
IOB0:OUTPUT_MISC 0.39.13 0.38.12 0.39.11
IOB1:OUTPUT_MISC 1.38.50 1.39.51 1.38.52
non-inverted [2] [1] [0]
IOB0:PULL 0.39.35 0.38.34 0.39.33
IOB1:PULL 1.38.28 1.39.29 1.38.30
PULLDOWN 0 0 0
NONE 0 0 1
PULLUP 0 1 1
KEEPER 1 0 1
IOB0:SLEW 0.39.23 0.38.22 0.39.21 0.38.20 0.39.19 0.38.18 0.39.17 0.38.16 0.39.15 0.38.14
IOB1:SLEW 1.38.40 1.39.41 1.38.42 1.39.43 1.38.44 1.39.45 1.38.46 1.39.47 1.38.48 1.39.49
mixed inversion [9] [8] [7] [6] [5] [4] [3] [2] [1] ~[0]
OLOGIC0:CLK_RATIO 0.30.27 0.30.29 0.31.32 0.31.28
OLOGIC1:CLK_RATIO 1.31.36 1.31.34 1.30.31 1.30.35
NONE 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 1
7_8 1 1 0 0
6 1 1 0 1
OLOGIC0:DATA_WIDTH 0.31.26 0.31.12 0.30.11 0.31.4 0.30.7 0.31.6 0.30.3 0.30.1 0.31.0
OLOGIC1:DATA_WIDTH 1.30.37 1.30.51 1.31.52 1.30.59 1.31.56 1.30.57 1.31.60 1.31.62 1.30.63
NONE 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 1
3 0 0 0 0 0 0 0 1 0
4 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 1 0 0 0
6 0 0 0 0 1 0 0 0 0
7 0 0 0 1 0 0 0 0 0
8 0 0 1 0 0 0 0 0 0
10 0 1 0 0 0 0 0 0 0
14 1 0 0 0 0 0 0 0 0
OLOGIC0:MISR_CLK_SELECT 0.30.5 0.30.15
OLOGIC1:MISR_CLK_SELECT 1.31.58 1.31.48
NONE 0 0
CLK1 0 1
CLK2 1 0
OLOGIC0:MUX.CLK 0.29.34 0.28.35 0.29.38 0.28.31 0.28.33 0.29.30 0.29.32 0.28.39 0.28.43 0.28.45 0.29.44
OLOGIC0:MUX.CLKB 0.30.34 0.31.35 0.30.38 0.31.31 0.31.33 0.30.30 0.30.32 0.31.39 0.31.43 0.31.45 0.30.44
OLOGIC1:MUX.CLK 1.28.29 1.29.28 1.28.25 1.29.32 1.29.30 1.28.33 1.28.31 1.29.24 1.29.20 1.29.18 1.28.19
OLOGIC1:MUX.CLKB 1.31.29 1.30.28 1.31.25 1.30.32 1.30.30 1.31.33 1.31.31 1.30.24 1.30.20 1.30.18 1.31.19
NONE 0 0 0 0 0 0 0 0 0 0 0
PHASER_OCLK 0 0 0 0 0 0 0 0 0 1 0
PHASER_OCLK90 0 0 0 0 0 0 0 0 1 0 0
HCLK0 0 0 0 0 0 0 1 1 0 0 1
HCLK1 0 0 0 0 0 1 0 1 0 0 1
HCLK2 0 0 0 0 1 0 0 1 0 0 1
HCLK3 0 0 0 1 0 0 0 1 0 0 1
HCLK4 0 0 1 0 0 0 1 0 0 0 1
HCLK5 0 0 1 0 0 1 0 0 0 0 1
RCLK0 0 0 1 0 1 0 0 0 0 0 1
RCLK1 0 0 1 1 0 0 0 0 0 0 1
RCLK2 0 1 0 0 0 0 1 0 0 0 1
RCLK3 0 1 0 0 0 1 0 0 0 0 1
IOCLK0 0 1 0 0 1 0 0 0 0 0 1
IOCLK1 0 1 0 1 0 0 0 0 0 0 1
IOCLK2 1 0 0 0 0 0 1 0 0 0 1
IOCLK3 1 0 0 0 0 1 0 0 0 0 1
CKINT 1 0 0 0 1 0 0 0 0 0 1
OLOGIC0:MUX.CLKDIV 0.28.17 0.29.16
OLOGIC1:MUX.CLKDIV 1.29.46 1.28.47
NONE 0 0
CLKDIVF 0 1
PHASER_OCLKDIV 1 0
OLOGIC0:MUX.CLKDIVB 0.31.17 0.30.16
OLOGIC1:MUX.CLKDIVB 1.30.46 1.31.47
NONE 0 0
CLKDIVFB 0 1
PHASER_OCLKDIV 1 0
OLOGIC0:MUX.CLKDIVF 0.29.6 0.29.8 0.28.9 0.29.2 0.29.4 0.28.1 0.28.3
OLOGIC0:MUX.CLKDIVFB 0.30.6 0.30.8 0.31.9 0.30.2 0.30.4 0.31.1 0.31.3
OLOGIC1:MUX.CLKDIVF 1.28.57 1.28.55 1.29.54 1.28.61 1.28.59 1.29.62 1.29.60
OLOGIC1:MUX.CLKDIVFB 1.31.57 1.31.55 1.30.54 1.31.61 1.31.59 1.30.62 1.30.60
NONE 0 0 0 0 0 0 0
HCLK0 0 0 1 0 0 0 1
HCLK1 0 0 1 0 0 1 0
HCLK2 0 0 1 0 1 0 0
HCLK3 0 0 1 1 0 0 0
HCLK4 0 1 0 0 0 0 1
HCLK5 0 1 0 0 0 1 0
RCLK0 0 1 0 0 1 0 0
RCLK1 0 1 0 1 0 0 0
RCLK2 1 0 0 0 0 0 1
RCLK3 1 0 0 0 0 1 0
CKINT 1 0 0 0 1 0 0
OLOGIC0:OMUX 0.33.17 0.32.14 0.32.36 0.32.34 0.32.16
OLOGIC1:OMUX 1.32.46 1.33.49 1.33.27 1.33.29 1.33.47
NONE 0 0 0 0 0
D1 0 0 0 0 1
SERDES_SDR 0 0 0 1 0
DDR 0 0 1 0 0
FF 0 1 0 1 0
LATCH 1 0 0 1 0
OLOGIC0:TMUX 0.32.60 0.33.59 0.33.57 0.32.58 0.33.61
OLOGIC1:TMUX 1.33.3 1.32.4 1.32.6 1.33.5 1.32.2
NONE 0 0 0 0 0
T1 0 0 0 0 1
SERDES_SDR 0 0 0 1 0
DDR 0 0 1 0 0
FF 0 1 0 1 0
LATCH 1 0 0 1 0
OLOGIC0:TRISTATE_WIDTH 0.33.37
OLOGIC1:TRISTATE_WIDTH 1.32.26
1 0
4 1

Bitstream — IO_HR_BOT

virtex7 IO_HR_BOT bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLK_INV_EN OLOGIC0:DATA_WIDTH[0] - - - - - - - - IOB0:DRIVE[0]
62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INV.CLK[0] OLOGIC0:MUX.CLKDIVF[1] OLOGIC0:MUX.CLKDIVFB[1] OLOGIC0:DATA_WIDTH[1] - - - - - - IOB0:DRIVE[1] -
61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLKDIVF[3] ~ILOGIC0:INV.CLK[2] OLOGIC0:INV.D8 OLOGIC0:MUX.CLKDIVFB[3] - - - - - - - ~IOB0:DRIVE[2]
60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.OCLK2 OLOGIC0:MUX.CLKDIVF[0] OLOGIC0:MUX.CLKDIVFB[0] OLOGIC0:DATA_WIDTH[2] - - - - - - IOB0:DRIVE[3] -
59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLKDIVF[2] ~ILOGIC0:INV.CLK[1] OLOGIC0:DATA_WIDTH[5] OLOGIC0:MUX.CLKDIVFB[2] - - - - - - - IOB0:IN_TERM[1]
58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MISR_CLK_SELECT[1] - - IDELAY0:IDELAY_VALUE_INIT[0] - - - IOB0:IN_TERM[2] -
57 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[0] - OLOGIC0:MUX.CLKDIVF[6] - OLOGIC0:DATA_WIDTH[3] OLOGIC0:MUX.CLKDIVFB[6] - - - - - - - IOB0:IN_TERM[3]
56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.ZHOLD_IFF - - OLOGIC0:DATA_WIDTH[4] - - ~IDELAY0:IDELAY_VALUE_CUR[0] - - - IOB0:IN_TERM[0] -
55 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.CLKDIV - OLOGIC0:MUX.CLKDIVF[5] ILOGIC0:IFF_ZHOLD OLOGIC0:MISR_RESET OLOGIC0:MUX.CLKDIVFB[5] - - - IDELAY0:IDELAY_TYPE[0] - - - ~IOB0:DRIVE[4]
54 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLKDIV_INV_EN ILOGIC0:IFFDELAY_VALUE[0] OLOGIC0:MUX.CLKDIVF[4] OLOGIC0:MUX.CLKDIVFB[4] OLOGIC0:INV.D7 - - - - - - ~IOB0:DRIVE[5] -
53 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[2] - - ILOGIC0:IDELAY_VALUE[0] OLOGIC0:MISR_ENABLE_FDBK - - - - - - - - IOB0:DRIVE[6]
52 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLKDIVP_INV_EN ILOGIC0:IFF_DELAY_ENABLE - - OLOGIC0:DATA_WIDTH[6] - - IDELAY0:IDELAY_VALUE_INIT[1] - - - IOB0:OUTPUT_MISC[0] -
51 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[4] - - - OLOGIC0:DATA_WIDTH[7] - - - - - - - - IOB0:OUTPUT_MISC[1]
50 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.CLKDIVP - - - OLOGIC0:INV.D6 - - ~IDELAY0:IDELAY_VALUE_CUR[1] - - - IOB0:OUTPUT_MISC[2] -
49 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[3] - - ILOGIC0:IFF_TSBYPASS_ENABLE OLOGIC0:INV.D5 - - OLOGIC0:OMUX[3] - IDELAY0:IDELAY_TYPE[1] - - - ~IOB0:SLEW[0]
48 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[0] ILOGIC0:IFFDELAY_VALUE[1] - - OLOGIC0:MISR_CLK_SELECT[0] OLOGIC0:OFF_SR_USED - - - - - IOB0:SLEW[1] -
47 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[1] - OLOGIC0:MUX.CLKDIV[0] ILOGIC0:IDELAY_VALUE[1] OLOGIC0:MISR_ENABLE OLOGIC0:MUX.CLKDIVB[0] - OLOGIC0:OMUX[0] - - - - - IOB0:SLEW[2]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[2] ILOGIC0:TSBYPASS_MUX[0] OLOGIC0:MUX.CLKDIV[1] OLOGIC0:MUX.CLKDIVB[1] OLOGIC0:INV.D4 OLOGIC0:OMUX[4] - IDELAY0:IDELAY_VALUE_INIT[2] - - - IOB0:SLEW[3] -
45 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[3] - - ~ILOGIC0:INV.D - - IDELAY0:HIGH_PERFORMANCE_MODE - - - - - - IOB0:SLEW[4]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_RATE[0] - - - - ~OLOGIC0:OFF_SRVAL[0] - ~IDELAY0:IDELAY_VALUE_CUR[2] - - - IOB0:SLEW[5] -
43 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:BITSLIP_ENABLE - - - - - - ~OLOGIC0:OFF_SRVAL[2] - - - - - IOB0:SLEW[6]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:SERDES_MODE[0] - - - OLOGIC0:INV.D3 - - IDELAY0:PIPE_SEL - - - IOB0:SLEW[7] -
41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFFDELAY_VALUE[2] - - - - - - - - - IOB0:SLEW[8]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IDELAY_VALUE[2] - - - - - - - - - IOB0:SLEW[9] -
39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:I_TSBYPASS_ENABLE - - - - - - - - - -
38 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:SERDES ILOGIC0:ZHOLD_ENABLE - - OLOGIC0:INV.D2 - - IDELAY0:IDELAY_VALUE_INIT[3] - - - IOB0:LVDS[12] -
37 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[1] - - ILOGIC0:I_DELAY_ENABLE OLOGIC0:DATA_WIDTH[8] - - - - - - - - IOB0:LVDS[11]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:RANK23_DLY - - - OLOGIC0:CLK_RATIO[3] - - ~IDELAY0:IDELAY_VALUE_CUR[3] - - - IOB0:LVDS[10] -
35 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DDR_CLK_EDGE[1] - ILOGIC0:MUX.CLKDIVP[1] - OLOGIC0:CLK_RATIO[0] - - - - - - - - IOB0:LVDS[9]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DDR_CLK_EDGE[0] - ILOGIC0:MUX.CLKDIVP[0] - OLOGIC0:CLK_RATIO[2] - - - - - - IOB0:LVDS[8] -
33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[5] ILOGIC0:I_ZHOLD OLOGIC0:INV.D1 OLOGIC0:MUX.CLKB[5] - ~OLOGIC0:OFF_INIT - - - - - IOB0:LVDS[7]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.ZHOLD_FABRIC OLOGIC0:MUX.CLK[7] OLOGIC0:MUX.CLKB[7] OLOGIC0:SELFHEAL - - IDELAY0:IDELAY_VALUE_INIT[4] - - - IOB0:LVDS[6] -
31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[4] - OLOGIC0:CLK_RATIO[1] OLOGIC0:MUX.CLKB[4] - ~OLOGIC0:OFF_SRVAL[1] - - - - - IOB0:LOW_VOLTAGE
30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF4_INIT OLOGIC0:MUX.CLK[6] OLOGIC0:MUX.CLKB[6] OLOGIC0:INV.CLKDIVF OLOGIC0:OFF_SR_SYNC - ~IDELAY0:IDELAY_VALUE_CUR[4] - - - IOB0:PULL[0] -
29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[10] ~ILOGIC0:IFF4_SRVAL - OLOGIC0:MUX.CLKB[10] - OLOGIC0:OMUX[1] - - - - - IOB0:PULL[1]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[9] OLOGIC0:MUX.CLKB[9] ~OLOGIC0:INV.CLK2 - - - - - - IOB0:PULL[2] -
27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:OMUX[2] - - - - - IOB0:PULL_DYNAMIC
26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFFDELAY_VALUE[3] - - ~OLOGIC0:INV.CLK1 OLOGIC0:TRISTATE_WIDTH[0] - - - - - IOB0:DQS_BIAS -
25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[8] ILOGIC0:IDELAY_VALUE[3] - OLOGIC0:MUX.CLKB[8] - OLOGIC0:TFF_SR_USED - IDELAY0:CINVCTRL_SEL - - - IOB0:INTERMDISABLE_SEL[0]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[3] OLOGIC0:MUX.CLKB[3] - - - IDELAY0:INV.C - - - - -
23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB0:IBUF_MODE[0]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF3_INIT - - ~OLOGIC0:RANK3_USED - - - - - - IOB0:IBUF_MODE[1] -
21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF3_SRVAL OLOGIC0:INV.CLKDIV - - - - - - - - IOB0:IBUF_MODE[2]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[2] OLOGIC0:MUX.CLKB[2] - OLOGIC0:TBYTE_SRC - - - - - IOB0:IBUF_MODE[4] -
19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[0] - - OLOGIC0:MUX.CLKB[0] - OLOGIC0:SERDES_MODE[0] - - - - - -
18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFFDELAY_VALUE[4] OLOGIC0:MUX.CLK[1] OLOGIC0:MUX.CLKB[1] - ~OLOGIC0:TFF_SRVAL[0] - - - - - IOB0:IBUFDISABLE_SEL[0] -
17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[5] ILOGIC0:IDELAY_VALUE[4] - ILOGIC0:MUX.CLKB[5] - ~OLOGIC0:TFF_SRVAL[2] - IDELAY0:INV.DATAIN - - - IOB0:IBUF_MODE[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:NUM_CE[0] - ILOGIC0:MUX.CLK[7] ILOGIC0:MUX.CLKB[7] - OLOGIC0:TBYTE_CTL - - - - - IOB0:INPUT_MISC -
15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[4] - ~OLOGIC0:INV.T4 ILOGIC0:MUX.CLKB[4] - - - - - - - IOB0:LVDS[5]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[6] ILOGIC0:MUX.CLKB[6] - - - - - - - IOB0:LVDS[4] -
13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[10] - - ILOGIC0:MUX.CLKB[10] - - - - - - - IOB0:LVDS[3]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF2_INIT ILOGIC0:MUX.CLK[9] ILOGIC0:MUX.CLKB[9] ~OLOGIC0:INV.T3 - - - - - - IOB0:LVDS[2] -
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[8] ~ILOGIC0:IFF2_SRVAL ~OLOGIC0:TFF_INIT ILOGIC0:MUX.CLKB[8] - ~OLOGIC0:TFF_SRVAL[1] - - - - - IOB0:LVDS[1]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[3] ILOGIC0:MUX.CLKB[3] - - - - - - - IOB0:LVDS[0] -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAY0:ENABLE OLOGIC0:SERDES - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF1_INIT - - - OLOGIC0:TFF_SR_SYNC IDELAY0:INV.IDATAIN IDELAY0:DELAY_SRC[0] - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF_LATCH - - ~ILOGIC0:IFF1_SRVAL ~OLOGIC0:INV.T2 - - - - IDELAY0:DELAY_SRC[2] - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_SR_USED - - - - OLOGIC0:TMUX[2] - IDELAY0:DELAY_SRC[3] - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TMUX[1] - IDELAY0:DELAY_SRC[1] - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TMUX[3] - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[2] ILOGIC0:SRTYPE[0] ~OLOGIC0:INV.T1 ILOGIC0:MUX.CLKB[2] - OLOGIC0:TMUX[4] - - - - - IOB0:OUTPUT_MISC_B
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:D_EMU2 ILOGIC0:MUX.CLK[0] ILOGIC0:MUX.CLKB[0] - OLOGIC0:TMUX[0] - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[1] ILOGIC0:D_EMU1 - ILOGIC0:MUX.CLKB[1] - - - - - - - IOB0:OUTPUT_ENABLE[0]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.OCLK1 - - - - - - - - - IOB0:OUTPUT_ENABLE[1] -
IDELAY0:CINVCTRL_SEL 0.35.25
IDELAY0:ENABLE 0.32.9
IDELAY0:HIGH_PERFORMANCE_MODE 0.32.45
IDELAY0:INV.C 0.34.24
IDELAY0:INV.DATAIN 0.35.17
IDELAY0:INV.IDATAIN 0.33.8
IDELAY0:PIPE_SEL 0.34.42
ILOGIC0:BITSLIP_ENABLE 0.26.43
ILOGIC0:DYN_CLKDIVP_INV_EN 0.27.52
ILOGIC0:DYN_CLKDIV_INV_EN 0.27.54
ILOGIC0:DYN_CLK_INV_EN 0.29.63
ILOGIC0:D_EMU1 0.29.1
ILOGIC0:D_EMU2 0.28.2
ILOGIC0:IFF_DELAY_ENABLE 0.28.52
ILOGIC0:IFF_SR_USED 0.27.6
ILOGIC0:IFF_TSBYPASS_ENABLE 0.29.49
ILOGIC0:IFF_ZHOLD 0.29.55
ILOGIC0:INV.CLKDIV 0.26.55
ILOGIC0:INV.CLKDIVP 0.27.50
ILOGIC0:INV.OCLK1 0.28.0
ILOGIC0:INV.OCLK2 0.28.60
ILOGIC0:INV.ZHOLD_FABRIC 0.28.32
ILOGIC0:INV.ZHOLD_IFF 0.28.56
ILOGIC0:I_DELAY_ENABLE 0.29.37
ILOGIC0:I_TSBYPASS_ENABLE 0.29.39
ILOGIC0:I_ZHOLD 0.29.33
ILOGIC0:RANK23_DLY 0.27.36
ILOGIC0:SERDES 0.27.38
ILOGIC0:ZHOLD_ENABLE 0.28.38
IOB0:DQS_BIAS 0.38.26
IOB0:INPUT_MISC 0.38.16
IOB0:LOW_VOLTAGE 0.39.31
IOB0:OUTPUT_MISC_B 0.39.3
IOB0:PULL_DYNAMIC 0.39.27
OLOGIC0:INV.CLKDIV 0.30.21
OLOGIC0:INV.CLKDIVF 0.31.30
OLOGIC0:INV.D1 0.30.33
OLOGIC0:INV.D2 0.31.38
OLOGIC0:INV.D3 0.31.42
OLOGIC0:INV.D4 0.31.46
OLOGIC0:INV.D5 0.30.49
OLOGIC0:INV.D6 0.31.50
OLOGIC0:INV.D7 0.31.54
OLOGIC0:INV.D8 0.30.61
OLOGIC0:MISR_ENABLE 0.30.47
OLOGIC0:MISR_ENABLE_FDBK 0.30.53
OLOGIC0:MISR_RESET 0.30.55
OLOGIC0:OFF_SR_SYNC 0.32.30
OLOGIC0:OFF_SR_USED 0.32.48
OLOGIC0:SELFHEAL 0.31.32
OLOGIC0:SERDES 0.33.9
OLOGIC0:TBYTE_CTL 0.32.16
OLOGIC0:TBYTE_SRC 0.32.20
OLOGIC0:TFF_SR_SYNC 0.32.8
OLOGIC0:TFF_SR_USED 0.33.25
non-inverted [0]
IDELAY0:DELAY_SRC 0.34.6 0.35.7 0.35.5 0.34.8
NONE 0 0 0 0
IDATAIN 0 0 0 1
DATAIN 0 0 1 0
OFB 0 1 0 0
DELAYCHAIN_OSC 1 0 0 0
IDELAY0:IDELAY_TYPE 0.35.49 0.35.55
FIXED 0 0
VARIABLE 0 1
VAR_LOAD 1 1
IDELAY0:IDELAY_VALUE_CUR 0.34.30 0.34.36 0.34.44 0.34.50 0.34.56
inverted ~[4] ~[3] ~[2] ~[1] ~[0]
IDELAY0:IDELAY_VALUE_INIT 0.34.32 0.34.38 0.34.46 0.34.52 0.34.58
ILOGIC0:IDELAY_VALUE 0.29.17 0.29.25 0.28.40 0.29.47 0.29.53
ILOGIC0:IFFDELAY_VALUE 0.28.18 0.28.26 0.29.41 0.28.48 0.28.54
non-inverted [4] [3] [2] [1] [0]
ILOGIC0:DATA_RATE 0.27.44
DDR 0
SDR 1
ILOGIC0:DATA_WIDTH 0.26.45 0.27.46 0.26.47 0.27.48
NONE 0 0 0 0
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
10 1 0 1 0
14 1 1 1 0
ILOGIC0:DDR_CLK_EDGE 0.26.35 0.27.34
SAME_EDGE_PIPELINED 0 0
OPPOSITE_EDGE 0 1
SAME_EDGE 1 0
ILOGIC0:IFF1_INIT 0.28.8
ILOGIC0:IFF1_SRVAL 0.29.7
ILOGIC0:IFF2_INIT 0.28.12
ILOGIC0:IFF2_SRVAL 0.29.11
ILOGIC0:IFF3_INIT 0.28.22
ILOGIC0:IFF3_SRVAL 0.29.21
ILOGIC0:IFF4_INIT 0.28.30
ILOGIC0:IFF4_SRVAL 0.29.29
ILOGIC0:IFF_LATCH 0.26.7
ILOGIC0:INV.D 0.29.45
OLOGIC0:INV.CLK1 0.31.26
OLOGIC0:INV.CLK2 0.31.28
OLOGIC0:INV.T1 0.30.3
OLOGIC0:INV.T2 0.30.7
OLOGIC0:INV.T3 0.31.12
OLOGIC0:INV.T4 0.30.15
OLOGIC0:OFF_INIT 0.33.33
OLOGIC0:RANK3_USED 0.31.22
OLOGIC0:TFF_INIT 0.30.11
inverted ~[0]
ILOGIC0:INTERFACE_TYPE 0.26.51 0.26.49 0.26.53 0.26.37 0.26.57
MEMORY 0 0 0 0 0
NETWORKING 0 0 0 0 1
MEMORY_DDR3 0 0 1 1 1
MEMORY_DDR3_V6 0 1 0 1 1
OVERSAMPLE 1 0 0 1 1
ILOGIC0:INV.CLK 0.29.61 0.29.59 0.28.62
OLOGIC0:OFF_SRVAL 0.33.43 0.33.31 0.32.44
OLOGIC0:TFF_SRVAL 0.33.17 0.33.11 0.32.18
inverted ~[2] ~[1] ~[0]
ILOGIC0:MUX.CLK 0.28.13 0.29.12 0.28.11 0.29.16 0.29.14 0.28.17 0.28.15 0.29.10 0.28.3 0.28.1 0.29.2
ILOGIC0:MUX.CLKB 0.31.13 0.30.12 0.31.11 0.30.16 0.30.14 0.31.17 0.31.15 0.30.10 0.31.3 0.31.1 0.30.2
NONE 0 0 0 0 0 0 0 0 0 0 0
PHASER_ICLK 0 0 0 0 0 0 0 0 0 0 1
PHASER_OCLK 0 0 0 0 0 0 0 0 0 1 0
HCLK0 0 0 0 0 0 0 1 1 1 0 0
HCLK1 0 0 0 0 0 1 0 1 1 0 0
HCLK2 0 0 0 0 1 0 0 1 1 0 0
HCLK3 0 0 0 1 0 0 0 1 1 0 0
HCLK4 0 0 1 0 0 0 1 0 1 0 0
HCLK5 0 0 1 0 0 1 0 0 1 0 0
RCLK0 0 0 1 0 1 0 0 0 1 0 0
RCLK1 0 0 1 1 0 0 0 0 1 0 0
RCLK2 0 1 0 0 0 0 1 0 1 0 0
RCLK3 0 1 0 0 0 1 0 0 1 0 0
IOCLK0 0 1 0 0 1 0 0 0 1 0 0
IOCLK1 0 1 0 1 0 0 0 0 1 0 0
IOCLK2 1 0 0 0 0 0 1 0 1 0 0
IOCLK3 1 0 0 0 0 1 0 0 1 0 0
CKINT1 1 0 0 0 1 0 0 0 1 0 0
CKINT0 1 0 0 1 0 0 0 0 1 0 0
ILOGIC0:MUX.CLKDIVP 0.28.35 0.29.34
NONE 0 0
CLKDIV 0 1
PHASER 1 0
ILOGIC0:NUM_CE 0.27.16
1 0
2 1
ILOGIC0:SERDES_MODE 0.27.42
OLOGIC0:SERDES_MODE 0.33.19
MASTER 0
SLAVE 1
ILOGIC0:SRTYPE 0.29.3
ASYNC 0
SYNC 1
ILOGIC0:TSBYPASS_MUX 0.28.46
T 0
GND 1
IOB0:DRIVE 0.39.53 0.38.54 0.39.55 0.38.60 0.39.61 0.38.62 0.39.63
mixed inversion [6] ~[5] ~[4] [3] ~[2] [1] [0]
IOB0:IBUFDISABLE_SEL 0.38.18
IOB0:INTERMDISABLE_SEL 0.39.25
GND 0
I 1
IOB0:IBUF_MODE 0.38.20 0.39.17 0.39.21 0.38.22 0.39.23
OFF 0 0 0 0 0
VREF_LP 0 0 0 0 1
CMOS_LV 0 0 1 1 0
CMOS_HV 0 0 1 1 1
PCI 0 1 1 1 1
VREF_HP 1 0 0 0 1
IOB0:IN_TERM 0.39.57 0.38.58 0.39.59 0.38.56
NONE 0 0 0 0
UNTUNED_SPLIT_60 0 0 1 1
UNTUNED_SPLIT_50 0 1 1 1
UNTUNED_SPLIT_40 1 1 1 1
IOB0:LVDS 0.38.38 0.39.37 0.38.36 0.39.35 0.38.34 0.39.33 0.38.32 0.39.15 0.38.14 0.39.13 0.38.12 0.39.11 0.38.10
non-inverted [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
IOB0:OUTPUT_ENABLE 0.38.0 0.39.1
non-inverted [1] [0]
IOB0:OUTPUT_MISC 0.38.50 0.39.51 0.38.52
non-inverted [2] [1] [0]
IOB0:PULL 0.38.28 0.39.29 0.38.30
PULLDOWN 0 0 0
NONE 0 0 1
PULLUP 0 1 1
KEEPER 1 0 1
IOB0:SLEW 0.38.40 0.39.41 0.38.42 0.39.43 0.38.44 0.39.45 0.38.46 0.39.47 0.38.48 0.39.49
mixed inversion [9] [8] [7] [6] [5] [4] [3] [2] [1] ~[0]
OLOGIC0:CLK_RATIO 0.31.36 0.31.34 0.30.31 0.30.35
NONE 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 1
7_8 1 1 0 0
6 1 1 0 1
OLOGIC0:DATA_WIDTH 0.30.37 0.30.51 0.31.52 0.30.59 0.31.56 0.30.57 0.31.60 0.31.62 0.30.63
NONE 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 1
3 0 0 0 0 0 0 0 1 0
4 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 1 0 0 0
6 0 0 0 0 1 0 0 0 0
7 0 0 0 1 0 0 0 0 0
8 0 0 1 0 0 0 0 0 0
10 0 1 0 0 0 0 0 0 0
14 1 0 0 0 0 0 0 0 0
OLOGIC0:MISR_CLK_SELECT 0.31.58 0.31.48
NONE 0 0
CLK1 0 1
CLK2 1 0
OLOGIC0:MUX.CLK 0.28.29 0.29.28 0.28.25 0.29.32 0.29.30 0.28.33 0.28.31 0.29.24 0.29.20 0.29.18 0.28.19
OLOGIC0:MUX.CLKB 0.31.29 0.30.28 0.31.25 0.30.32 0.30.30 0.31.33 0.31.31 0.30.24 0.30.20 0.30.18 0.31.19
NONE 0 0 0 0 0 0 0 0 0 0 0
PHASER_OCLK 0 0 0 0 0 0 0 0 0 1 0
PHASER_OCLK90 0 0 0 0 0 0 0 0 1 0 0
HCLK0 0 0 0 0 0 0 1 1 0 0 1
HCLK1 0 0 0 0 0 1 0 1 0 0 1
HCLK2 0 0 0 0 1 0 0 1 0 0 1
HCLK3 0 0 0 1 0 0 0 1 0 0 1
HCLK4 0 0 1 0 0 0 1 0 0 0 1
HCLK5 0 0 1 0 0 1 0 0 0 0 1
RCLK0 0 0 1 0 1 0 0 0 0 0 1
RCLK1 0 0 1 1 0 0 0 0 0 0 1
RCLK2 0 1 0 0 0 0 1 0 0 0 1
RCLK3 0 1 0 0 0 1 0 0 0 0 1
IOCLK0 0 1 0 0 1 0 0 0 0 0 1
IOCLK1 0 1 0 1 0 0 0 0 0 0 1
IOCLK2 1 0 0 0 0 0 1 0 0 0 1
IOCLK3 1 0 0 0 0 1 0 0 0 0 1
CKINT 1 0 0 0 1 0 0 0 0 0 1
OLOGIC0:MUX.CLKDIV 0.29.46 0.28.47
NONE 0 0
CLKDIVF 0 1
PHASER_OCLKDIV 1 0
OLOGIC0:MUX.CLKDIVB 0.30.46 0.31.47
NONE 0 0
CLKDIVFB 0 1
PHASER_OCLKDIV 1 0
OLOGIC0:MUX.CLKDIVF 0.28.57 0.28.55 0.29.54 0.28.61 0.28.59 0.29.62 0.29.60
OLOGIC0:MUX.CLKDIVFB 0.31.57 0.31.55 0.30.54 0.31.61 0.31.59 0.30.62 0.30.60
NONE 0 0 0 0 0 0 0
HCLK0 0 0 1 0 0 0 1
HCLK1 0 0 1 0 0 1 0
HCLK2 0 0 1 0 1 0 0
HCLK3 0 0 1 1 0 0 0
HCLK4 0 1 0 0 0 0 1
HCLK5 0 1 0 0 0 1 0
RCLK0 0 1 0 0 1 0 0
RCLK1 0 1 0 1 0 0 0
RCLK2 1 0 0 0 0 0 1
RCLK3 1 0 0 0 0 1 0
CKINT 1 0 0 0 1 0 0
OLOGIC0:OMUX 0.32.46 0.33.49 0.33.27 0.33.29 0.33.47
NONE 0 0 0 0 0
D1 0 0 0 0 1
SERDES_SDR 0 0 0 1 0
DDR 0 0 1 0 0
FF 0 1 0 1 0
LATCH 1 0 0 1 0
OLOGIC0:TMUX 0.33.3 0.32.4 0.32.6 0.33.5 0.32.2
NONE 0 0 0 0 0
T1 0 0 0 0 1
SERDES_SDR 0 0 0 1 0
DDR 0 0 1 0 0
FF 0 1 0 1 0
LATCH 1 0 0 1 0
OLOGIC0:TRISTATE_WIDTH 0.32.26
1 0
4 1

Bitstream — IO_HR_TOP

virtex7 IO_HR_TOP bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.OCLK1 - - - - - - - - - IOB0:OUTPUT_ENABLE[1]
62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:D_EMU1 ILOGIC0:MUX.CLK[1] ILOGIC0:MUX.CLKB[1] - - - - - - - IOB0:OUTPUT_ENABLE[0] -
61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[0] ILOGIC0:D_EMU2 - ILOGIC0:MUX.CLKB[0] - OLOGIC0:TMUX[0] - - - - - -
60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:SRTYPE[0] ILOGIC0:MUX.CLK[2] ILOGIC0:MUX.CLKB[2] ~OLOGIC0:INV.T1 OLOGIC0:TMUX[4] - - - - - IOB0:OUTPUT_MISC_B -
59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TMUX[3] - - - - - -
58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TMUX[1] - IDELAY0:DELAY_SRC[1] - - - - -
57 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_SR_USED - - - - - - OLOGIC0:TMUX[2] - IDELAY0:DELAY_SRC[3] - - - -
56 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF_LATCH ~ILOGIC0:IFF1_SRVAL - - ~OLOGIC0:INV.T2 - - IDELAY0:DELAY_SRC[2] - - - - -
55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF1_INIT - - IDELAY0:INV.IDATAIN OLOGIC0:TFF_SR_SYNC - IDELAY0:DELAY_SRC[0] - - - -
54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:SERDES IDELAY0:ENABLE - - - - - -
53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[3] - - ILOGIC0:MUX.CLKB[3] - - - - - - - IOB0:LVDS[0]
52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF2_SRVAL ILOGIC0:MUX.CLK[8] ILOGIC0:MUX.CLKB[8] ~OLOGIC0:TFF_INIT ~OLOGIC0:TFF_SRVAL[1] - - - - - IOB0:LVDS[1] -
51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[9] ~ILOGIC0:IFF2_INIT ~OLOGIC0:INV.T3 ILOGIC0:MUX.CLKB[9] - - - - - - - IOB0:LVDS[2]
50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[10] ILOGIC0:MUX.CLKB[10] - - - - - - - IOB0:LVDS[3] -
49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[6] - - ILOGIC0:MUX.CLKB[6] - - - - - - - IOB0:LVDS[4]
48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.CLK[4] ILOGIC0:MUX.CLKB[4] ~OLOGIC0:INV.T4 - - - - - - IOB0:LVDS[5] -
47 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:NUM_CE[0] - ILOGIC0:MUX.CLK[7] - - ILOGIC0:MUX.CLKB[7] - OLOGIC0:TBYTE_CTL - - - - - IOB0:INPUT_MISC
46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IDELAY_VALUE[4] ILOGIC0:MUX.CLK[5] ILOGIC0:MUX.CLKB[5] - ~OLOGIC0:TFF_SRVAL[0] - IDELAY0:INV.DATAIN - - - IOB0:IBUF_MODE[3] -
45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[1] ILOGIC0:IFFDELAY_VALUE[4] - OLOGIC0:MUX.CLKB[1] - ~OLOGIC0:TFF_SRVAL[2] - - - - - IOB0:IBUFDISABLE_SEL[0]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[0] OLOGIC0:MUX.CLKB[0] - OLOGIC0:SERDES_MODE[0] - - - - - - -
43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[2] - - OLOGIC0:MUX.CLKB[2] - OLOGIC0:TBYTE_SRC - - - - - IOB0:IBUF_MODE[4]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF3_SRVAL - - OLOGIC0:INV.CLKDIV - - - - - - IOB0:IBUF_MODE[1] -
41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF3_INIT ~OLOGIC0:RANK3_USED - - - - - - - - IOB0:IBUF_MODE[2]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IOB0:IBUF_MODE[0] -
39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[3] - - OLOGIC0:MUX.CLKB[3] - - - IDELAY0:INV.C - - - -
38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IDELAY_VALUE[3] OLOGIC0:MUX.CLK[8] OLOGIC0:MUX.CLKB[8] - OLOGIC0:TFF_SR_USED - IDELAY0:CINVCTRL_SEL - - - IOB0:INTERMDISABLE_SEL[0] -
37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFFDELAY_VALUE[3] ~OLOGIC0:INV.CLK1 - - OLOGIC0:TRISTATE_WIDTH[0] - - - - - IOB0:DQS_BIAS
36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:OMUX[2] - - - - - IOB0:PULL_DYNAMIC -
35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[9] - ~OLOGIC0:INV.CLK2 OLOGIC0:MUX.CLKB[9] - - - - - - - IOB0:PULL[2]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF4_SRVAL OLOGIC0:MUX.CLK[10] OLOGIC0:MUX.CLKB[10] - OLOGIC0:OMUX[1] - - - - - IOB0:PULL[1] -
33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[6] ~ILOGIC0:IFF4_INIT OLOGIC0:INV.CLKDIVF OLOGIC0:MUX.CLKB[6] - OLOGIC0:OFF_SR_SYNC - ~IDELAY0:IDELAY_VALUE_CUR[4] - - - IOB0:PULL[0]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[4] OLOGIC0:MUX.CLKB[4] OLOGIC0:CLK_RATIO[1] ~OLOGIC0:OFF_SRVAL[1] - - - - - IOB0:LOW_VOLTAGE -
31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLK[7] ILOGIC0:INV.ZHOLD_FABRIC OLOGIC0:SELFHEAL OLOGIC0:MUX.CLKB[7] - - - IDELAY0:IDELAY_VALUE_INIT[4] - - - IOB0:LVDS[6]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:I_ZHOLD OLOGIC0:MUX.CLK[5] OLOGIC0:MUX.CLKB[5] OLOGIC0:INV.D1 ~OLOGIC0:OFF_INIT - - - - - IOB0:LVDS[7] -
29 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DDR_CLK_EDGE[0] - ILOGIC0:MUX.CLKDIVP[0] - OLOGIC0:CLK_RATIO[2] - - - - - - - - IOB0:LVDS[8]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DDR_CLK_EDGE[1] - ILOGIC0:MUX.CLKDIVP[1] - OLOGIC0:CLK_RATIO[0] - - - - - - IOB0:LVDS[9] -
27 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:RANK23_DLY - - - OLOGIC0:CLK_RATIO[3] - - - - ~IDELAY0:IDELAY_VALUE_CUR[3] - - - IOB0:LVDS[10]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[1] ILOGIC0:I_DELAY_ENABLE - - OLOGIC0:DATA_WIDTH[8] - - - - - - IOB0:LVDS[11] -
25 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:SERDES - - ILOGIC0:ZHOLD_ENABLE OLOGIC0:INV.D2 - - - - IDELAY0:IDELAY_VALUE_INIT[3] - - - IOB0:LVDS[12]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:I_TSBYPASS_ENABLE - - - - - - - - - - -
23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IDELAY_VALUE[2] - - - - - - - - - IOB0:SLEW[9]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFFDELAY_VALUE[2] - - - - - - - - - IOB0:SLEW[8] -
21 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:SERDES_MODE[0] - - - OLOGIC0:INV.D3 - - - - IDELAY0:PIPE_SEL - - - IOB0:SLEW[7]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:BITSLIP_ENABLE - - - - ~OLOGIC0:OFF_SRVAL[0] - - - - - IOB0:SLEW[6] -
19 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_RATE[0] - - - - - - ~OLOGIC0:OFF_SRVAL[2] - ~IDELAY0:IDELAY_VALUE_CUR[2] - - - IOB0:SLEW[5]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[3] ~ILOGIC0:INV.D - - - - IDELAY0:HIGH_PERFORMANCE_MODE - - - - IOB0:SLEW[4] -
17 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[2] - OLOGIC0:MUX.CLKDIV[1] ILOGIC0:TSBYPASS_MUX[0] OLOGIC0:INV.D4 OLOGIC0:MUX.CLKDIVB[1] - OLOGIC0:OMUX[4] - IDELAY0:IDELAY_VALUE_INIT[2] - - - IOB0:SLEW[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[1] ILOGIC0:IDELAY_VALUE[1] OLOGIC0:MUX.CLKDIV[0] OLOGIC0:MUX.CLKDIVB[0] OLOGIC0:MISR_ENABLE OLOGIC0:OMUX[0] - - - - - IOB0:SLEW[2] -
15 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[0] - - ILOGIC0:IFFDELAY_VALUE[1] OLOGIC0:MISR_CLK_SELECT[0] - - OLOGIC0:OFF_SR_USED - - - - - IOB0:SLEW[1]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[3] ILOGIC0:IFF_TSBYPASS_ENABLE - - OLOGIC0:INV.D5 OLOGIC0:OMUX[3] - IDELAY0:IDELAY_TYPE[1] - - - ~IOB0:SLEW[0] -
13 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.CLKDIVP - - - OLOGIC0:INV.D6 - - - - ~IDELAY0:IDELAY_VALUE_CUR[1] - - - IOB0:OUTPUT_MISC[2]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[4] - - - OLOGIC0:DATA_WIDTH[7] - - - - - - IOB0:OUTPUT_MISC[1] -
11 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLKDIVP_INV_EN - - ILOGIC0:IFF_DELAY_ENABLE OLOGIC0:DATA_WIDTH[6] - - - - IDELAY0:IDELAY_VALUE_INIT[1] - - - IOB0:OUTPUT_MISC[0]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[2] ILOGIC0:IDELAY_VALUE[0] - - OLOGIC0:MISR_ENABLE_FDBK - - - - - - IOB0:DRIVE[6] -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLKDIV_INV_EN - OLOGIC0:MUX.CLKDIVF[4] ILOGIC0:IFFDELAY_VALUE[0] OLOGIC0:INV.D7 OLOGIC0:MUX.CLKDIVFB[4] - - - - - - - ~IOB0:DRIVE[5]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.CLKDIV ILOGIC0:IFF_ZHOLD OLOGIC0:MUX.CLKDIVF[5] OLOGIC0:MUX.CLKDIVFB[5] OLOGIC0:MISR_RESET - - IDELAY0:IDELAY_TYPE[0] - - - ~IOB0:DRIVE[4] -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.ZHOLD_IFF OLOGIC0:DATA_WIDTH[4] - - - - ~IDELAY0:IDELAY_VALUE_CUR[0] - - - IOB0:IN_TERM[1]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[0] - OLOGIC0:MUX.CLKDIVF[6] OLOGIC0:MUX.CLKDIVFB[6] OLOGIC0:DATA_WIDTH[3] - - - - - - IOB0:IN_TERM[3] -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MISR_CLK_SELECT[1] - - - - IDELAY0:IDELAY_VALUE_INIT[0] - - - IOB0:IN_TERM[2]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INV.CLK[1] OLOGIC0:MUX.CLKDIVF[2] OLOGIC0:MUX.CLKDIVFB[2] OLOGIC0:DATA_WIDTH[5] - - - - - - IOB0:IN_TERM[0] -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLKDIVF[0] ILOGIC0:INV.OCLK2 OLOGIC0:DATA_WIDTH[2] OLOGIC0:MUX.CLKDIVFB[0] - - - - - - - IOB0:DRIVE[3]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INV.CLK[0] OLOGIC0:MUX.CLKDIVF[3] OLOGIC0:MUX.CLKDIVFB[3] OLOGIC0:INV.D8 - - - - - - ~IOB0:DRIVE[2] -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.CLKDIVF[1] ~ILOGIC0:INV.CLK[2] OLOGIC0:DATA_WIDTH[1] OLOGIC0:MUX.CLKDIVFB[1] - - - - - - - IOB0:DRIVE[1]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_CLK_INV_EN - - OLOGIC0:DATA_WIDTH[0] - - - - - - IOB0:DRIVE[0] -
IDELAY0:CINVCTRL_SEL 0.34.38
IDELAY0:ENABLE 0.33.54
IDELAY0:HIGH_PERFORMANCE_MODE 0.33.18
IDELAY0:INV.C 0.35.39
IDELAY0:INV.DATAIN 0.34.46
IDELAY0:INV.IDATAIN 0.32.55
IDELAY0:PIPE_SEL 0.35.21
ILOGIC0:BITSLIP_ENABLE 0.27.20
ILOGIC0:DYN_CLKDIVP_INV_EN 0.26.11
ILOGIC0:DYN_CLKDIV_INV_EN 0.26.9
ILOGIC0:DYN_CLK_INV_EN 0.28.0
ILOGIC0:D_EMU1 0.28.62
ILOGIC0:D_EMU2 0.29.61
ILOGIC0:IFF_DELAY_ENABLE 0.29.11
ILOGIC0:IFF_SR_USED 0.26.57
ILOGIC0:IFF_TSBYPASS_ENABLE 0.28.14
ILOGIC0:IFF_ZHOLD 0.28.8
ILOGIC0:INV.CLKDIV 0.27.8
ILOGIC0:INV.CLKDIVP 0.26.13
ILOGIC0:INV.OCLK1 0.29.63
ILOGIC0:INV.OCLK2 0.29.3
ILOGIC0:INV.ZHOLD_FABRIC 0.29.31
ILOGIC0:INV.ZHOLD_IFF 0.29.7
ILOGIC0:I_DELAY_ENABLE 0.28.26
ILOGIC0:I_TSBYPASS_ENABLE 0.28.24
ILOGIC0:I_ZHOLD 0.28.30
ILOGIC0:RANK23_DLY 0.26.27
ILOGIC0:SERDES 0.26.25
ILOGIC0:ZHOLD_ENABLE 0.29.25
IOB0:DQS_BIAS 0.39.37
IOB0:INPUT_MISC 0.39.47
IOB0:LOW_VOLTAGE 0.38.32
IOB0:OUTPUT_MISC_B 0.38.60
IOB0:PULL_DYNAMIC 0.38.36
OLOGIC0:INV.CLKDIV 0.31.42
OLOGIC0:INV.CLKDIVF 0.30.33
OLOGIC0:INV.D1 0.31.30
OLOGIC0:INV.D2 0.30.25
OLOGIC0:INV.D3 0.30.21
OLOGIC0:INV.D4 0.30.17
OLOGIC0:INV.D5 0.31.14
OLOGIC0:INV.D6 0.30.13
OLOGIC0:INV.D7 0.30.9
OLOGIC0:INV.D8 0.31.2
OLOGIC0:MISR_ENABLE 0.31.16
OLOGIC0:MISR_ENABLE_FDBK 0.31.10
OLOGIC0:MISR_RESET 0.31.8
OLOGIC0:OFF_SR_SYNC 0.33.33
OLOGIC0:OFF_SR_USED 0.33.15
OLOGIC0:SELFHEAL 0.30.31
OLOGIC0:SERDES 0.32.54
OLOGIC0:TBYTE_CTL 0.33.47
OLOGIC0:TBYTE_SRC 0.33.43
OLOGIC0:TFF_SR_SYNC 0.33.55
OLOGIC0:TFF_SR_USED 0.32.38
non-inverted [0]
IDELAY0:DELAY_SRC 0.35.57 0.34.56 0.34.58 0.35.55
NONE 0 0 0 0
IDATAIN 0 0 0 1
DATAIN 0 0 1 0
OFB 0 1 0 0
DELAYCHAIN_OSC 1 0 0 0
IDELAY0:IDELAY_TYPE 0.34.14 0.34.8
FIXED 0 0
VARIABLE 0 1
VAR_LOAD 1 1
IDELAY0:IDELAY_VALUE_CUR 0.35.33 0.35.27 0.35.19 0.35.13 0.35.7
inverted ~[4] ~[3] ~[2] ~[1] ~[0]
IDELAY0:IDELAY_VALUE_INIT 0.35.31 0.35.25 0.35.17 0.35.11 0.35.5
ILOGIC0:IDELAY_VALUE 0.28.46 0.28.38 0.29.23 0.28.16 0.28.10
ILOGIC0:IFFDELAY_VALUE 0.29.45 0.29.37 0.28.22 0.29.15 0.29.9
non-inverted [4] [3] [2] [1] [0]
ILOGIC0:DATA_RATE 0.26.19
DDR 0
SDR 1
ILOGIC0:DATA_WIDTH 0.27.18 0.26.17 0.27.16 0.26.15
NONE 0 0 0 0
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
10 1 0 1 0
14 1 1 1 0
ILOGIC0:DDR_CLK_EDGE 0.27.28 0.26.29
SAME_EDGE_PIPELINED 0 0
OPPOSITE_EDGE 0 1
SAME_EDGE 1 0
ILOGIC0:IFF1_INIT 0.29.55
ILOGIC0:IFF1_SRVAL 0.28.56
ILOGIC0:IFF2_INIT 0.29.51
ILOGIC0:IFF2_SRVAL 0.28.52
ILOGIC0:IFF3_INIT 0.29.41
ILOGIC0:IFF3_SRVAL 0.28.42
ILOGIC0:IFF4_INIT 0.29.33
ILOGIC0:IFF4_SRVAL 0.28.34
ILOGIC0:IFF_LATCH 0.27.56
ILOGIC0:INV.D 0.28.18
OLOGIC0:INV.CLK1 0.30.37
OLOGIC0:INV.CLK2 0.30.35
OLOGIC0:INV.T1 0.31.60
OLOGIC0:INV.T2 0.31.56
OLOGIC0:INV.T3 0.30.51
OLOGIC0:INV.T4 0.31.48
OLOGIC0:OFF_INIT 0.32.30
OLOGIC0:RANK3_USED 0.30.41
OLOGIC0:TFF_INIT 0.31.52
inverted ~[0]
ILOGIC0:INTERFACE_TYPE 0.27.12 0.27.14 0.27.10 0.27.26 0.27.6
MEMORY 0 0 0 0 0
NETWORKING 0 0 0 0 1
MEMORY_DDR3 0 0 1 1 1
MEMORY_DDR3_V6 0 1 0 1 1
OVERSAMPLE 1 0 0 1 1
ILOGIC0:INV.CLK 0.29.1 0.28.4 0.28.2
OLOGIC0:OFF_SRVAL 0.33.19 0.32.32 0.32.20
OLOGIC0:TFF_SRVAL 0.33.45 0.32.52 0.32.46
inverted ~[2] ~[1] ~[0]
ILOGIC0:MUX.CLK 0.29.50 0.28.51 0.29.52 0.28.47 0.28.49 0.29.46 0.29.48 0.28.53 0.29.60 0.29.62 0.28.61
ILOGIC0:MUX.CLKB 0.30.50 0.31.51 0.30.52 0.31.47 0.31.49 0.30.46 0.30.48 0.31.53 0.30.60 0.30.62 0.31.61
NONE 0 0 0 0 0 0 0 0 0 0 0
PHASER_ICLK 0 0 0 0 0 0 0 0 0 0 1
PHASER_OCLK 0 0 0 0 0 0 0 0 0 1 0
HCLK0 0 0 0 0 0 0 1 1 1 0 0
HCLK1 0 0 0 0 0 1 0 1 1 0 0
HCLK2 0 0 0 0 1 0 0 1 1 0 0
HCLK3 0 0 0 1 0 0 0 1 1 0 0
HCLK4 0 0 1 0 0 0 1 0 1 0 0
HCLK5 0 0 1 0 0 1 0 0 1 0 0
RCLK0 0 0 1 0 1 0 0 0 1 0 0
RCLK1 0 0 1 1 0 0 0 0 1 0 0
RCLK2 0 1 0 0 0 0 1 0 1 0 0
RCLK3 0 1 0 0 0 1 0 0 1 0 0
IOCLK0 0 1 0 0 1 0 0 0 1 0 0
IOCLK1 0 1 0 1 0 0 0 0 1 0 0
IOCLK2 1 0 0 0 0 0 1 0 1 0 0
IOCLK3 1 0 0 0 0 1 0 0 1 0 0
CKINT1 1 0 0 0 1 0 0 0 1 0 0
CKINT0 1 0 0 1 0 0 0 0 1 0 0
ILOGIC0:MUX.CLKDIVP 0.29.28 0.28.29
NONE 0 0
CLKDIV 0 1
PHASER 1 0
ILOGIC0:NUM_CE 0.26.47
1 0
2 1
ILOGIC0:SERDES_MODE 0.26.21
OLOGIC0:SERDES_MODE 0.32.44
MASTER 0
SLAVE 1
ILOGIC0:SRTYPE 0.28.60
ASYNC 0
SYNC 1
ILOGIC0:TSBYPASS_MUX 0.29.17
T 0
GND 1
IOB0:DRIVE 0.38.10 0.39.9 0.38.8 0.39.3 0.38.2 0.39.1 0.38.0
mixed inversion [6] ~[5] ~[4] [3] ~[2] [1] [0]
IOB0:IBUFDISABLE_SEL 0.39.45
IOB0:INTERMDISABLE_SEL 0.38.38
GND 0
I 1
IOB0:IBUF_MODE 0.39.43 0.38.46 0.39.41 0.38.42 0.38.40
OFF 0 0 0 0 0
VREF_LP 0 0 0 0 1
CMOS_LV 0 0 1 1 0
CMOS_HV 0 0 1 1 1
PCI 0 1 1 1 1
VREF_HP 1 0 0 0 1
IOB0:IN_TERM 0.38.6 0.39.5 0.39.7 0.38.4
NONE 0 0 0 0
UNTUNED_SPLIT_60 0 0 1 1
UNTUNED_SPLIT_50 0 1 1 1
UNTUNED_SPLIT_40 1 1 1 1
IOB0:LVDS 0.39.25 0.38.26 0.39.27 0.38.28 0.39.29 0.38.30 0.39.31 0.38.48 0.39.49 0.38.50 0.39.51 0.38.52 0.39.53
non-inverted [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
IOB0:OUTPUT_ENABLE 0.39.63 0.38.62
non-inverted [1] [0]
IOB0:OUTPUT_MISC 0.39.13 0.38.12 0.39.11
non-inverted [2] [1] [0]
IOB0:PULL 0.39.35 0.38.34 0.39.33
PULLDOWN 0 0 0
NONE 0 0 1
PULLUP 0 1 1
KEEPER 1 0 1
IOB0:SLEW 0.39.23 0.38.22 0.39.21 0.38.20 0.39.19 0.38.18 0.39.17 0.38.16 0.39.15 0.38.14
mixed inversion [9] [8] [7] [6] [5] [4] [3] [2] [1] ~[0]
OLOGIC0:CLK_RATIO 0.30.27 0.30.29 0.31.32 0.31.28
NONE 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 1
7_8 1 1 0 0
6 1 1 0 1
OLOGIC0:DATA_WIDTH 0.31.26 0.31.12 0.30.11 0.31.4 0.30.7 0.31.6 0.30.3 0.30.1 0.31.0
NONE 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 1
3 0 0 0 0 0 0 0 1 0
4 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 1 0 0 0
6 0 0 0 0 1 0 0 0 0
7 0 0 0 1 0 0 0 0 0
8 0 0 1 0 0 0 0 0 0
10 0 1 0 0 0 0 0 0 0
14 1 0 0 0 0 0 0 0 0
OLOGIC0:MISR_CLK_SELECT 0.30.5 0.30.15
NONE 0 0
CLK1 0 1
CLK2 1 0
OLOGIC0:MUX.CLK 0.29.34 0.28.35 0.29.38 0.28.31 0.28.33 0.29.30 0.29.32 0.28.39 0.28.43 0.28.45 0.29.44
OLOGIC0:MUX.CLKB 0.30.34 0.31.35 0.30.38 0.31.31 0.31.33 0.30.30 0.30.32 0.31.39 0.31.43 0.31.45 0.30.44
NONE 0 0 0 0 0 0 0 0 0 0 0
PHASER_OCLK 0 0 0 0 0 0 0 0 0 1 0
PHASER_OCLK90 0 0 0 0 0 0 0 0 1 0 0
HCLK0 0 0 0 0 0 0 1 1 0 0 1
HCLK1 0 0 0 0 0 1 0 1 0 0 1
HCLK2 0 0 0 0 1 0 0 1 0 0 1
HCLK3 0 0 0 1 0 0 0 1 0 0 1
HCLK4 0 0 1 0 0 0 1 0 0 0 1
HCLK5 0 0 1 0 0 1 0 0 0 0 1
RCLK0 0 0 1 0 1 0 0 0 0 0 1
RCLK1 0 0 1 1 0 0 0 0 0 0 1
RCLK2 0 1 0 0 0 0 1 0 0 0 1
RCLK3 0 1 0 0 0 1 0 0 0 0 1
IOCLK0 0 1 0 0 1 0 0 0 0 0 1
IOCLK1 0 1 0 1 0 0 0 0 0 0 1
IOCLK2 1 0 0 0 0 0 1 0 0 0 1
IOCLK3 1 0 0 0 0 1 0 0 0 0 1
CKINT 1 0 0 0 1 0 0 0 0 0 1
OLOGIC0:MUX.CLKDIV 0.28.17 0.29.16
NONE 0 0
CLKDIVF 0 1
PHASER_OCLKDIV 1 0
OLOGIC0:MUX.CLKDIVB 0.31.17 0.30.16
NONE 0 0
CLKDIVFB 0 1
PHASER_OCLKDIV 1 0
OLOGIC0:MUX.CLKDIVF 0.29.6 0.29.8 0.28.9 0.29.2 0.29.4 0.28.1 0.28.3
OLOGIC0:MUX.CLKDIVFB 0.30.6 0.30.8 0.31.9 0.30.2 0.30.4 0.31.1 0.31.3
NONE 0 0 0 0 0 0 0
HCLK0 0 0 1 0 0 0 1
HCLK1 0 0 1 0 0 1 0
HCLK2 0 0 1 0 1 0 0
HCLK3 0 0 1 1 0 0 0
HCLK4 0 1 0 0 0 0 1
HCLK5 0 1 0 0 0 1 0
RCLK0 0 1 0 0 1 0 0
RCLK1 0 1 0 1 0 0 0
RCLK2 1 0 0 0 0 0 1
RCLK3 1 0 0 0 0 1 0
CKINT 1 0 0 0 1 0 0
OLOGIC0:OMUX 0.33.17 0.32.14 0.32.36 0.32.34 0.32.16
NONE 0 0 0 0 0
D1 0 0 0 0 1
SERDES_SDR 0 0 0 1 0
DDR 0 0 1 0 0
FF 0 1 0 1 0
LATCH 1 0 0 1 0
OLOGIC0:TMUX 0.32.60 0.33.59 0.33.57 0.32.58 0.33.61
NONE 0 0 0 0 0
T1 0 0 0 0 1
SERDES_SDR 0 0 0 1 0
DDR 0 0 1 0 0
FF 0 1 0 1 0
LATCH 1 0 0 1 0
OLOGIC0:TRISTATE_WIDTH 0.33.37
1 0
4 1

Bitstream — HCLK_IOI_HP

virtex7 HCLK_IOI_HP bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
31 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[11] HCLK_IOI:MUX.HCLK_IO_D3[0] HCLK_IOI:MUX.HCLK_IO_U4[0] HCLK_IOI:ENABLE.HCLK7 HCLK_IOI:BUF.RCLK1 HCLK_IOI:MUX.HCLK_IO_U1[5] - - BUFR0:MUX.I[2] - ~BUFIO0:DELAY_BYPASS BUFIO0:ENABLE DCI:TEST_ENABLE[1] DCI:ENABLE LVDS:LVDSBIAS[17] DCI:DYNAMIC_ENABLE
30 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[10] HCLK_IOI:MUX.HCLK_IO_D4[0] HCLK_IOI:MUX.HCLK_IO_U3[0] HCLK_IOI:ENABLE.HCLK6 HCLK_IOI:MUX.HCLK_IO_D2[0] HCLK_IOI:MUX.HCLK_IO_D4[5] BUFR0:ENABLE BUFR0:BUFR_DIVIDE[1] BUFR1:MUX.I[6] - - - - DCI:NREF_OUTPUT[0] - LVDS:LVDSBIAS[16]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[9] HCLK_IOI:MUX.HCLK_IO_U1[3] HCLK_IOI:MUX.HCLK_IO_D4[1] HCLK_IOI:MUX.HCLK_IO_D0[0] HCLK_IOI:MUX.HCLK_IO_U2[0] HCLK_IOI:MUX.HCLK_IO_D1[5] HCLK_IOI:BUF.RCLK0 BUFR0:BUFR_DIVIDE[2] BUFR1:MUX.I[7] BUFR0:MUX.I[7] BUFIO0:MUX.I[0] IDELAYCTRL:MODE[1] - DCI:NREF_OUTPUT[1] - LVDS:LVDSBIAS[15]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[8] HCLK_IOI:MUX.HCLK_IO_D1[3] HCLK_IOI:MUX.HCLK_IO_D3[1] HCLK_IOI:MUX.HCLK_IO_U0[0] HCLK_IOI:MUX.HCLK_IO_D2[1] HCLK_IOI:MUX.HCLK_IO_U1[6] - BUFR0:BUFR_DIVIDE[3] - BUFR0:MUX.I[6] HCLK_IOI:ENABLE.PERF0 IDELAYCTRL:MODE[0] - DCI:NREF_OUTPUT_HALF[0] INTERNAL_VREF:VREF[2] LVDS:LVDSBIAS[14]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[7] HCLK_IOI:MUX.HCLK_IO_D0[3] HCLK_IOI:MUX.HCLK_IO_U4[1] HCLK_IOI:ENABLE.HCLK5 HCLK_IOI:MUX.HCLK_IO_U2[1] HCLK_IOI:MUX.HCLK_IO_D4[4] - BUFR0:BUFR_DIVIDE[0] - BUFR0:MUX.I[5] BUFR1:MUX.I[1] - - DCI:NREF_OUTPUT_HALF[1] INTERNAL_VREF:VREF[1] LVDS:LVDSBIAS[13]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[6] HCLK_IOI:MUX.HCLK_IO_U1[2] HCLK_IOI:MUX.HCLK_IO_U3[1] HCLK_IOI:MUX.HCLK_IO_U0[3] HCLK_IOI:MUX.HCLK_IO_D2[2] HCLK_IOI:MUX.HCLK_IO_D2[6] BUFR1:ENABLE BUFR1:BUFR_DIVIDE[1] BUFR1:MUX.I[5] BUFR0:MUX.I[4] BUFR1:MUX.I[0] IDELAYCTRL:HIGH_PERFORMANCE_MODE - DCI:NREF_OUTPUT_HALF[2] INTERNAL_VREF:VREF[3] LVDS:LVDSBIAS[12]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[5] HCLK_IOI:MUX.HCLK_IO_U0[2] HCLK_IOI:MUX.HCLK_IO_D4[2] HCLK_IOI:MUX.HCLK_IO_D0[6] HCLK_IOI:MUX.HCLK_IO_U2[2] HCLK_IOI:MUX.HCLK_IO_D2[4] HCLK_IOI:MUX.HCLK_IO_D1[4] BUFR1:BUFR_DIVIDE[2] BUFR1:MUX.I[4] BUFR0:MUX.I[3] BUFR2:MUX.I[1] - - DCI:NREF_TERM_SPLIT[0] INTERNAL_VREF:VREF[4] LVDS:LVDSBIAS[11]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[4] HCLK_IOI:MUX.HCLK_IO_D1[2] HCLK_IOI:MUX.HCLK_IO_D3[2] HCLK_IOI:MUX.HCLK_IO_D0[4] HCLK_IOI:MUX.HCLK_IO_D2[3] HCLK_IOI:MUX.HCLK_IO_D2[5] HCLK_IOI:MUX.HCLK_IO_U1[4] BUFR1:BUFR_DIVIDE[3] BUFR1:MUX.I[3] BUFR0:MUX.I[1] BUFR2:MUX.I[0] IDELAYCTRL:MODE[2] - DCI:NREF_TERM_SPLIT[1] INTERNAL_VREF:VREF[5] LVDS:LVDSBIAS[10]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[3] HCLK_IOI:MUX.HCLK_IO_D0[2] HCLK_IOI:MUX.HCLK_IO_U4[2] HCLK_IOI:ENABLE.HCLK4 HCLK_IOI:MUX.HCLK_IO_U2[3] HCLK_IOI:MUX.HCLK_IO_D5[4] HCLK_IOI:MUX.HCLK_IO_U4[4] BUFR1:BUFR_DIVIDE[0] BUFR1:MUX.I[2] BUFR0:MUX.I[0] - - - DCI:NREF_TERM_SPLIT[2] INTERNAL_VREF:VREF[6] LVDS:LVDSBIAS[9]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[2] HCLK_IOI:MUX.HCLK_IO_U1[1] HCLK_IOI:MUX.HCLK_IO_D4[3] HCLK_IOI:MUX.HCLK_IO_U3[3] HCLK_IOI:MUX.HCLK_IO_U2[4] HCLK_IOI:MUX.HCLK_IO_D5[5] - - - - - BUFIO1:ENABLE DCI:CASCADE_FROM_BELOW - - LVDS:LVDSBIAS[8]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[1] HCLK_IOI:MUX.HCLK_IO_U0[1] HCLK_IOI:MUX.HCLK_IO_U4[3] HCLK_IOI:MUX.HCLK_IO_D3[3] HCLK_IOI:MUX.HCLK_IO_U2[5] HCLK_IOI:MUX.HCLK_IO_D5[6] - BUFR2:BUFR_DIVIDE[1] - BUFR3:MUX.I[1] ~BUFIO1:DELAY_BYPASS BUFIO1:MUX.I[0] DCI:CASCADE_FROM_ABOVE - - LVDS:LVDSBIAS[7]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[0] HCLK_IOI:MUX.HCLK_IO_D1[1] HCLK_IOI:MUX.HCLK_IO_D4[6] HCLK_IOI:MUX.HCLK_IO_U3[2] HCLK_IOI:MUX.HCLK_IO_U2[6] BUFR3:MUX.I[2] BUFR2:ENABLE BUFR2:BUFR_DIVIDE[2] BUFR2:MUX.I[7] - HCLK_IOI:ENABLE.PERF1 - - - - LVDS:LVDSBIAS[6]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:MUX.HCLK_IO_U0[4] HCLK_IOI:MUX.HCLK_IO_D0[1] HCLK_IOI:MUX.HCLK_IO_D1[6] HCLK_IOI:ENABLE.HCLK11 HCLK_IOI:MUX.HCLK_IO_U5[6] HCLK_IOI:BUF.RCLK2 BUFR3:ENABLE BUFR2:BUFR_DIVIDE[3] BUFR2:MUX.I[6] BUFR3:MUX.I[3] - - - - INTERNAL_VREF:VREF[0] LVDS:LVDSBIAS[5]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:MUX.HCLK_IO_U0[5] HCLK_IOI:MUX.HCLK_IO_U1[0] HCLK_IOI:MUX.HCLK_IO_D0[5] HCLK_IOI:ENABLE.HCLK3 HCLK_IOI:MUX.HCLK_IO_U5[5] HCLK_IOI:MUX.HCLK_IO_D5[0] - BUFR2:BUFR_DIVIDE[0] BUFR2:MUX.I[5] BUFR3:MUX.I[4] BUFIO2:ENABLE BUFIO3:ENABLE - - DCI:PREF_OUTPUT[0] LVDS:LVDSBIAS[4]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:MUX.HCLK_IO_U0[6] HCLK_IOI:MUX.HCLK_IO_D1[0] HCLK_IOI:BUF.RCLK3 HCLK_IOI:ENABLE.HCLK10 HCLK_IOI:MUX.HCLK_IO_U5[4] HCLK_IOI:MUX.HCLK_IO_U5[0] - BUFR3:BUFR_DIVIDE[1] BUFR2:MUX.I[4] BUFR3:MUX.I[5] BUFIO2:MUX.I[0] BUFIO3:MUX.I[0] - - DCI:PREF_OUTPUT[1] LVDS:LVDSBIAS[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:MUX.HCLK_IO_D3[4] HCLK_IOI:MUX.HCLK_IO_U3[6] - HCLK_IOI:ENABLE.HCLK2 HCLK_IOI:MUX.HCLK_IO_U5[3] HCLK_IOI:MUX.HCLK_IO_D5[1] BUFR3:MUX.I[0] BUFR3:BUFR_DIVIDE[2] BUFR2:MUX.I[3] BUFR3:MUX.I[6] ~BUFIO2:DELAY_BYPASS ~BUFIO3:DELAY_BYPASS - - DCI:PREF_OUTPUT_HALF[0] LVDS:LVDSBIAS[2]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:MUX.HCLK_IO_U3[4] HCLK_IOI:MUX.HCLK_IO_D3[5] HCLK_IOI:ENABLE.HCLK0 HCLK_IOI:ENABLE.HCLK9 HCLK_IOI:MUX.HCLK_IO_D5[3] HCLK_IOI:MUX.HCLK_IO_U5[1] HCLK_IOI:MUX.HCLK_IO_U4[5] BUFR3:BUFR_DIVIDE[3] BUFR2:MUX.I[2] BUFR3:MUX.I[7] - - DCI:TEST_ENABLE[0] - DCI:PREF_OUTPUT_HALF[1] LVDS:LVDSBIAS[1]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:MUX.HCLK_IO_D3[6] HCLK_IOI:MUX.HCLK_IO_U3[5] HCLK_IOI:ENABLE.HCLK8 HCLK_IOI:ENABLE.HCLK1 HCLK_IOI:MUX.HCLK_IO_U5[2] HCLK_IOI:MUX.HCLK_IO_D5[2] HCLK_IOI:MUX.HCLK_IO_U4[6] BUFR3:BUFR_DIVIDE[0] - - HCLK_IOI:ENABLE.PERF2 HCLK_IOI:ENABLE.PERF3 DCI:QUIET - DCI:PREF_OUTPUT_HALF[2] LVDS:LVDSBIAS[0]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFIO0:DELAY_BYPASS 0.36.31
BUFIO1:DELAY_BYPASS 0.36.21
BUFIO2:DELAY_BYPASS 0.36.16
BUFIO3:DELAY_BYPASS 0.37.16
inverted ~[0]
BUFIO0:ENABLE 0.37.31
BUFIO1:ENABLE 0.37.22
BUFIO2:ENABLE 0.36.18
BUFIO3:ENABLE 0.37.18
BUFR0:ENABLE 0.32.30
BUFR1:ENABLE 0.32.26
BUFR2:ENABLE 0.32.20
BUFR3:ENABLE 0.32.19
DCI:CASCADE_FROM_ABOVE 0.38.21
DCI:CASCADE_FROM_BELOW 0.38.22
DCI:DYNAMIC_ENABLE 0.41.31
DCI:ENABLE 0.39.31
DCI:QUIET 0.38.14
HCLK_IOI:BUF.RCLK0 0.32.29
HCLK_IOI:BUF.RCLK1 0.30.31
HCLK_IOI:BUF.RCLK2 0.31.19
HCLK_IOI:BUF.RCLK3 0.28.17
HCLK_IOI:ENABLE.HCLK0 0.28.15
HCLK_IOI:ENABLE.HCLK1 0.29.14
HCLK_IOI:ENABLE.HCLK10 0.29.17
HCLK_IOI:ENABLE.HCLK11 0.29.19
HCLK_IOI:ENABLE.HCLK2 0.29.16
HCLK_IOI:ENABLE.HCLK3 0.29.18
HCLK_IOI:ENABLE.HCLK4 0.29.23
HCLK_IOI:ENABLE.HCLK5 0.29.27
HCLK_IOI:ENABLE.HCLK6 0.29.30
HCLK_IOI:ENABLE.HCLK7 0.29.31
HCLK_IOI:ENABLE.HCLK8 0.28.14
HCLK_IOI:ENABLE.HCLK9 0.29.15
HCLK_IOI:ENABLE.PERF0 0.36.28
HCLK_IOI:ENABLE.PERF1 0.36.20
HCLK_IOI:ENABLE.PERF2 0.36.14
HCLK_IOI:ENABLE.PERF3 0.37.14
IDELAYCTRL:HIGH_PERFORMANCE_MODE 0.37.26
non-inverted [0]
BUFIO0:MUX.I 0.36.29
BUFIO1:MUX.I 0.37.21
BUFIO2:MUX.I 0.36.17
BUFIO3:MUX.I 0.37.17
CCIO 0
PERF 1
BUFR0:BUFR_DIVIDE 0.33.28 0.33.29 0.33.30 0.33.27
BUFR1:BUFR_DIVIDE 0.33.24 0.33.25 0.33.26 0.33.23
BUFR2:BUFR_DIVIDE 0.33.19 0.33.20 0.33.21 0.33.18
BUFR3:BUFR_DIVIDE 0.33.15 0.33.16 0.33.17 0.33.14
BYPASS 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 1 0 1
4 0 1 1 1
5 1 0 0 1
6 1 0 1 1
7 1 1 0 1
8 1 1 1 1
BUFR0:MUX.I 0.35.29 0.35.28 0.35.27 0.35.26 0.35.25 0.34.31 0.35.24 0.35.23
BUFR1:MUX.I 0.34.29 0.34.30 0.34.26 0.34.25 0.34.24 0.34.23 0.36.27 0.36.26
BUFR2:MUX.I 0.34.20 0.34.19 0.34.18 0.34.17 0.34.16 0.34.15 0.36.25 0.36.24
BUFR3:MUX.I 0.35.15 0.35.16 0.35.17 0.35.18 0.35.19 0.31.20 0.35.21 0.32.16
NONE 0 0 0 0 0 0 0 0
BUFIO0_I 0 0 0 0 0 0 0 1
BUFIO1_I 0 0 0 0 0 0 1 0
BUFIO2_I 0 0 0 0 0 1 0 0
BUFIO3_I 0 0 0 0 1 0 0 0
CKINT0 0 0 0 1 0 0 0 0
CKINT1 0 0 1 0 0 0 0 0
CKINT2 0 1 0 0 0 0 0 0
CKINT3 1 0 0 0 0 0 0 0
DCI:NREF_OUTPUT 0.39.29 0.39.30
DCI:PREF_OUTPUT 0.40.17 0.40.18
DCI:TEST_ENABLE 0.38.31 0.38.15
non-inverted [1] [0]
DCI:NREF_OUTPUT_HALF 0.39.26 0.39.27 0.39.28
DCI:NREF_TERM_SPLIT 0.39.23 0.39.24 0.39.25
DCI:PREF_OUTPUT_HALF 0.40.14 0.40.15 0.40.16
non-inverted [2] [1] [0]
HCLK_IOI:MUX.HCLK_IO_D0 0.29.25 0.28.18 0.29.24 0.27.27 0.27.23 0.27.19 0.29.29
HCLK_IOI:MUX.HCLK_IO_D1 0.28.19 0.31.29 0.32.25 0.27.28 0.27.24 0.27.20 0.27.17
HCLK_IOI:MUX.HCLK_IO_D2 0.31.26 0.31.24 0.31.25 0.30.24 0.30.26 0.30.28 0.30.30
HCLK_IOI:MUX.HCLK_IO_D3 0.26.14 0.27.15 0.26.16 0.29.21 0.28.24 0.28.28 0.27.31
HCLK_IOI:MUX.HCLK_IO_D4 0.28.20 0.31.30 0.31.27 0.28.22 0.28.25 0.28.29 0.27.30
HCLK_IOI:MUX.HCLK_IO_D5 0.31.21 0.31.22 0.31.23 0.30.15 0.31.14 0.31.16 0.31.18
HCLK_IOI:MUX.HCLK_IO_U0 0.26.17 0.26.18 0.26.19 0.29.26 0.27.25 0.27.21 0.29.28
HCLK_IOI:MUX.HCLK_IO_U1 0.31.28 0.31.31 0.32.24 0.27.29 0.27.26 0.27.22 0.27.18
HCLK_IOI:MUX.HCLK_IO_U2 0.30.20 0.30.21 0.30.22 0.30.23 0.30.25 0.30.27 0.30.29
HCLK_IOI:MUX.HCLK_IO_U3 0.27.16 0.27.14 0.26.15 0.29.22 0.29.20 0.28.26 0.28.30
HCLK_IOI:MUX.HCLK_IO_U4 0.32.14 0.32.15 0.32.23 0.28.21 0.28.23 0.28.27 0.28.31
HCLK_IOI:MUX.HCLK_IO_U5 0.30.19 0.30.18 0.30.17 0.30.16 0.30.14 0.31.15 0.31.17
NONE 0 0 0 0 0 0 0
HCLK0 0 0 1 0 0 0 1
HCLK1 0 0 1 0 0 1 0
HCLK2 0 0 1 0 1 0 0
HCLK3 0 0 1 1 0 0 0
HCLK4 0 1 0 0 0 0 1
HCLK5 0 1 0 0 0 1 0
HCLK6 0 1 0 0 1 0 0
HCLK7 0 1 0 1 0 0 0
HCLK8 1 0 0 0 0 0 1
HCLK9 1 0 0 0 0 1 0
HCLK10 1 0 0 0 1 0 0
HCLK11 1 0 0 1 0 0 0
IDELAYCTRL:MODE 0.37.24 0.37.29 0.37.28
NONE 0 0 0
DEFAULT 0 0 1
FULL_0 0 1 1
FULL_1 1 1 1
IDELAYCTRL:MUX.REFCLK 0.26.31 0.26.30 0.26.29 0.26.28 0.26.27 0.26.26 0.26.25 0.26.24 0.26.23 0.26.22 0.26.21 0.26.20
NONE 0 0 0 0 0 0 0 0 0 0 0 0
HCLK_IO_D0 0 0 0 0 0 0 0 0 0 0 0 1
HCLK_IO_D1 0 0 0 0 0 0 0 0 0 0 1 0
HCLK_IO_D2 0 0 0 0 0 0 0 0 0 1 0 0
HCLK_IO_D3 0 0 0 0 0 0 0 0 1 0 0 0
HCLK_IO_D4 0 0 0 0 0 0 0 1 0 0 0 0
HCLK_IO_D5 0 0 0 0 0 0 1 0 0 0 0 0
HCLK_IO_U0 0 0 0 0 0 1 0 0 0 0 0 0
HCLK_IO_U1 0 0 0 0 1 0 0 0 0 0 0 0
HCLK_IO_U2 0 0 0 1 0 0 0 0 0 0 0 0
HCLK_IO_U3 0 0 1 0 0 0 0 0 0 0 0 0
HCLK_IO_U4 0 1 0 0 0 0 0 0 0 0 0 0
HCLK_IO_U5 1 0 0 0 0 0 0 0 0 0 0 0
INTERNAL_VREF:VREF 0.40.23 0.40.24 0.40.25 0.40.26 0.40.28 0.40.27 0.40.19
OFF 0 0 0 0 0 0 0
600 0 0 0 0 0 1 1
675 0 0 0 0 1 0 1
750 0 0 0 1 0 0 1
900 0 0 1 0 0 0 1
1100 0 1 0 0 0 0 1
1250 1 0 0 0 0 0 1
LVDS:LVDSBIAS 0.40.31 0.41.30 0.41.29 0.41.28 0.41.27 0.41.26 0.41.25 0.41.24 0.41.23 0.41.22 0.41.21 0.41.20 0.41.19 0.41.18 0.41.17 0.41.16 0.41.15 0.41.14
non-inverted [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

Bitstream — HCLK_IOI_HR

virtex7 HCLK_IOI_HR bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
31 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[11] HCLK_IOI:MUX.HCLK_IO_D3[0] HCLK_IOI:MUX.HCLK_IO_U4[0] HCLK_IOI:ENABLE.HCLK7 HCLK_IOI:BUF.RCLK1 HCLK_IOI:MUX.HCLK_IO_U1[5] - - BUFR0:MUX.I[2] - ~BUFIO0:DELAY_BYPASS BUFIO0:ENABLE LVDS:GROUP1[15] LVDS:GROUP1[14] LVDS:COMMON[5] LVDS:COMMON[7]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[10] HCLK_IOI:MUX.HCLK_IO_D4[0] HCLK_IOI:MUX.HCLK_IO_U3[0] HCLK_IOI:ENABLE.HCLK6 HCLK_IOI:MUX.HCLK_IO_D2[0] HCLK_IOI:MUX.HCLK_IO_D4[5] BUFR0:ENABLE BUFR0:BUFR_DIVIDE[1] BUFR1:MUX.I[6] - - - INTERNAL_VREF:VREF[6] INTERNAL_VREF:VREF[1] LVDS:COMMON[0] LVDS:COMMON[8]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[9] HCLK_IOI:MUX.HCLK_IO_U1[3] HCLK_IOI:MUX.HCLK_IO_D4[1] HCLK_IOI:MUX.HCLK_IO_D0[0] HCLK_IOI:MUX.HCLK_IO_U2[0] HCLK_IOI:MUX.HCLK_IO_D1[5] HCLK_IOI:BUF.RCLK0 BUFR0:BUFR_DIVIDE[2] BUFR1:MUX.I[7] BUFR0:MUX.I[7] BUFIO0:MUX.I[0] IDELAYCTRL:MODE[1] INTERNAL_VREF:VREF[5] INTERNAL_VREF:VREF[4] LVDS:GROUP0[15] LVDS:GROUP0[3]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[8] HCLK_IOI:MUX.HCLK_IO_D1[3] HCLK_IOI:MUX.HCLK_IO_D3[1] HCLK_IOI:MUX.HCLK_IO_U0[0] HCLK_IOI:MUX.HCLK_IO_D2[1] HCLK_IOI:MUX.HCLK_IO_U1[6] - BUFR0:BUFR_DIVIDE[3] - BUFR0:MUX.I[6] HCLK_IOI:ENABLE.PERF0 IDELAYCTRL:MODE[0] LVDS:GROUP0[13] VCCOSENSE:MODE[3] LVDS:COMMON[1] LVDS:GROUP0[4]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[7] HCLK_IOI:MUX.HCLK_IO_D0[3] HCLK_IOI:MUX.HCLK_IO_U4[1] HCLK_IOI:ENABLE.HCLK5 HCLK_IOI:MUX.HCLK_IO_U2[1] HCLK_IOI:MUX.HCLK_IO_D4[4] - BUFR0:BUFR_DIVIDE[0] - BUFR0:MUX.I[5] BUFR1:MUX.I[1] - LVDS:GROUP0[14] VCCOSENSE:MODE[2] LVDS:COMMON[2] LVDS:GROUP0[5]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[6] HCLK_IOI:MUX.HCLK_IO_U1[2] HCLK_IOI:MUX.HCLK_IO_U3[1] HCLK_IOI:MUX.HCLK_IO_U0[3] HCLK_IOI:MUX.HCLK_IO_D2[2] HCLK_IOI:MUX.HCLK_IO_D2[6] BUFR1:ENABLE BUFR1:BUFR_DIVIDE[1] BUFR1:MUX.I[5] BUFR0:MUX.I[4] BUFR1:MUX.I[0] IDELAYCTRL:HIGH_PERFORMANCE_MODE INTERNAL_VREF:VREF[0] VCCOSENSE:MODE[1] LVDS:COMMON[3] DRIVERBIAS:DRIVERBIAS[8]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[5] HCLK_IOI:MUX.HCLK_IO_U0[2] HCLK_IOI:MUX.HCLK_IO_D4[2] HCLK_IOI:MUX.HCLK_IO_D0[6] HCLK_IOI:MUX.HCLK_IO_U2[2] HCLK_IOI:MUX.HCLK_IO_D2[4] HCLK_IOI:MUX.HCLK_IO_D1[4] BUFR1:BUFR_DIVIDE[2] BUFR1:MUX.I[4] BUFR0:MUX.I[3] BUFR2:MUX.I[1] - LVDS:GROUP0[2] VCCOSENSE:MODE[0] LVDS:COMMON[4] DRIVERBIAS:DRIVERBIAS[9]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[4] HCLK_IOI:MUX.HCLK_IO_D1[2] HCLK_IOI:MUX.HCLK_IO_D3[2] HCLK_IOI:MUX.HCLK_IO_D0[4] HCLK_IOI:MUX.HCLK_IO_D2[3] HCLK_IOI:MUX.HCLK_IO_D2[5] HCLK_IOI:MUX.HCLK_IO_U1[4] BUFR1:BUFR_DIVIDE[3] BUFR1:MUX.I[3] BUFR0:MUX.I[1] BUFR2:MUX.I[0] IDELAYCTRL:MODE[2] LVDS:GROUP0[1] INTERNAL_VREF:VREF[3] LVDS:GROUP1[3] DRIVERBIAS:DRIVERBIAS[10]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[3] HCLK_IOI:MUX.HCLK_IO_D0[2] HCLK_IOI:MUX.HCLK_IO_U4[2] HCLK_IOI:ENABLE.HCLK4 HCLK_IOI:MUX.HCLK_IO_U2[3] HCLK_IOI:MUX.HCLK_IO_D5[4] HCLK_IOI:MUX.HCLK_IO_U4[4] BUFR1:BUFR_DIVIDE[0] BUFR1:MUX.I[2] BUFR0:MUX.I[0] - - LVDS:GROUP0[0] LVDS:COMMON[6] LVDS:GROUP1[4] DRIVERBIAS:DRIVERBIAS[11]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[2] HCLK_IOI:MUX.HCLK_IO_U1[1] HCLK_IOI:MUX.HCLK_IO_D4[3] HCLK_IOI:MUX.HCLK_IO_U3[3] HCLK_IOI:MUX.HCLK_IO_U2[4] HCLK_IOI:MUX.HCLK_IO_D5[5] - - - - - BUFIO1:ENABLE VCCOSENSE:FLAG INTERNAL_VREF:VREF[2] LVDS:GROUP1[5] DRIVERBIAS:DRIVERBIAS[12]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[1] HCLK_IOI:MUX.HCLK_IO_U0[1] HCLK_IOI:MUX.HCLK_IO_U4[3] HCLK_IOI:MUX.HCLK_IO_D3[3] HCLK_IOI:MUX.HCLK_IO_U2[5] HCLK_IOI:MUX.HCLK_IO_D5[6] - BUFR2:BUFR_DIVIDE[1] - BUFR3:MUX.I[1] ~BUFIO1:DELAY_BYPASS BUFIO1:MUX.I[0] - DRIVERBIAS:DRIVERBIAS[7] LVDS:GROUP1[6] DRIVERBIAS:DRIVERBIAS[13]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[0] HCLK_IOI:MUX.HCLK_IO_D1[1] HCLK_IOI:MUX.HCLK_IO_D4[6] HCLK_IOI:MUX.HCLK_IO_U3[2] HCLK_IOI:MUX.HCLK_IO_U2[6] BUFR3:MUX.I[2] BUFR2:ENABLE BUFR2:BUFR_DIVIDE[2] BUFR2:MUX.I[7] - HCLK_IOI:ENABLE.PERF1 - LVDS:GROUP1[2] DRIVERBIAS:DRIVERBIAS[6] LVDS:GROUP1[7] LVDS:GROUP0[7]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:MUX.HCLK_IO_U0[4] HCLK_IOI:MUX.HCLK_IO_D0[1] HCLK_IOI:MUX.HCLK_IO_D1[6] HCLK_IOI:ENABLE.HCLK11 HCLK_IOI:MUX.HCLK_IO_U5[6] HCLK_IOI:BUF.RCLK2 BUFR3:ENABLE BUFR2:BUFR_DIVIDE[3] BUFR2:MUX.I[6] BUFR3:MUX.I[3] - - LVDS:GROUP1[1] DRIVERBIAS:DRIVERBIAS[5] LVDS:GROUP1[8] LVDS:GROUP0[8]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:MUX.HCLK_IO_U0[5] HCLK_IOI:MUX.HCLK_IO_U1[0] HCLK_IOI:MUX.HCLK_IO_D0[5] HCLK_IOI:ENABLE.HCLK3 HCLK_IOI:MUX.HCLK_IO_U5[5] HCLK_IOI:MUX.HCLK_IO_D5[0] - BUFR2:BUFR_DIVIDE[0] BUFR2:MUX.I[5] BUFR3:MUX.I[4] BUFIO2:ENABLE BUFIO3:ENABLE LVDS:GROUP1[0] DRIVERBIAS:DRIVERBIAS[2] LVDS:GROUP1[9] LVDS:GROUP0[9]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:MUX.HCLK_IO_U0[6] HCLK_IOI:MUX.HCLK_IO_D1[0] HCLK_IOI:BUF.RCLK3 HCLK_IOI:ENABLE.HCLK10 HCLK_IOI:MUX.HCLK_IO_U5[4] HCLK_IOI:MUX.HCLK_IO_U5[0] - BUFR3:BUFR_DIVIDE[1] BUFR2:MUX.I[4] BUFR3:MUX.I[5] BUFIO2:MUX.I[0] BUFIO3:MUX.I[0] - DRIVERBIAS:DRIVERBIAS[1] LVDS:GROUP1[10] LVDS:GROUP0[10]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:MUX.HCLK_IO_D3[4] HCLK_IOI:MUX.HCLK_IO_U3[6] - HCLK_IOI:ENABLE.HCLK2 HCLK_IOI:MUX.HCLK_IO_U5[3] HCLK_IOI:MUX.HCLK_IO_D5[1] BUFR3:MUX.I[0] BUFR3:BUFR_DIVIDE[2] BUFR2:MUX.I[3] BUFR3:MUX.I[6] ~BUFIO2:DELAY_BYPASS ~BUFIO3:DELAY_BYPASS - DRIVERBIAS:DRIVERBIAS[0] LVDS:GROUP1[11] LVDS:GROUP0[11]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:MUX.HCLK_IO_U3[4] HCLK_IOI:MUX.HCLK_IO_D3[5] HCLK_IOI:ENABLE.HCLK0 HCLK_IOI:ENABLE.HCLK9 HCLK_IOI:MUX.HCLK_IO_D5[3] HCLK_IOI:MUX.HCLK_IO_U5[1] HCLK_IOI:MUX.HCLK_IO_U4[5] BUFR3:BUFR_DIVIDE[3] BUFR2:MUX.I[2] BUFR3:MUX.I[7] - - DRIVERBIAS:DRIVERBIAS[4] DRIVERBIAS:DRIVERBIAS[15] LVDS:GROUP1[12] LVDS:GROUP0[12]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:MUX.HCLK_IO_D3[6] HCLK_IOI:MUX.HCLK_IO_U3[5] HCLK_IOI:ENABLE.HCLK8 HCLK_IOI:ENABLE.HCLK1 HCLK_IOI:MUX.HCLK_IO_U5[2] HCLK_IOI:MUX.HCLK_IO_D5[2] HCLK_IOI:MUX.HCLK_IO_U4[6] BUFR3:BUFR_DIVIDE[0] - - HCLK_IOI:ENABLE.PERF2 HCLK_IOI:ENABLE.PERF3 DRIVERBIAS:DRIVERBIAS[3] DRIVERBIAS:DRIVERBIAS[14] LVDS:GROUP1[13] LVDS:GROUP0[6]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFIO0:DELAY_BYPASS 0.36.31
BUFIO1:DELAY_BYPASS 0.36.21
BUFIO2:DELAY_BYPASS 0.36.16
BUFIO3:DELAY_BYPASS 0.37.16
inverted ~[0]
BUFIO0:ENABLE 0.37.31
BUFIO1:ENABLE 0.37.22
BUFIO2:ENABLE 0.36.18
BUFIO3:ENABLE 0.37.18
BUFR0:ENABLE 0.32.30
BUFR1:ENABLE 0.32.26
BUFR2:ENABLE 0.32.20
BUFR3:ENABLE 0.32.19
HCLK_IOI:BUF.RCLK0 0.32.29
HCLK_IOI:BUF.RCLK1 0.30.31
HCLK_IOI:BUF.RCLK2 0.31.19
HCLK_IOI:BUF.RCLK3 0.28.17
HCLK_IOI:ENABLE.HCLK0 0.28.15
HCLK_IOI:ENABLE.HCLK1 0.29.14
HCLK_IOI:ENABLE.HCLK10 0.29.17
HCLK_IOI:ENABLE.HCLK11 0.29.19
HCLK_IOI:ENABLE.HCLK2 0.29.16
HCLK_IOI:ENABLE.HCLK3 0.29.18
HCLK_IOI:ENABLE.HCLK4 0.29.23
HCLK_IOI:ENABLE.HCLK5 0.29.27
HCLK_IOI:ENABLE.HCLK6 0.29.30
HCLK_IOI:ENABLE.HCLK7 0.29.31
HCLK_IOI:ENABLE.HCLK8 0.28.14
HCLK_IOI:ENABLE.HCLK9 0.29.15
HCLK_IOI:ENABLE.PERF0 0.36.28
HCLK_IOI:ENABLE.PERF1 0.36.20
HCLK_IOI:ENABLE.PERF2 0.36.14
HCLK_IOI:ENABLE.PERF3 0.37.14
IDELAYCTRL:HIGH_PERFORMANCE_MODE 0.37.26
VCCOSENSE:FLAG 0.38.22
non-inverted [0]
BUFIO0:MUX.I 0.36.29
BUFIO1:MUX.I 0.37.21
BUFIO2:MUX.I 0.36.17
BUFIO3:MUX.I 0.37.17
CCIO 0
PERF 1
BUFR0:BUFR_DIVIDE 0.33.28 0.33.29 0.33.30 0.33.27
BUFR1:BUFR_DIVIDE 0.33.24 0.33.25 0.33.26 0.33.23
BUFR2:BUFR_DIVIDE 0.33.19 0.33.20 0.33.21 0.33.18
BUFR3:BUFR_DIVIDE 0.33.15 0.33.16 0.33.17 0.33.14
BYPASS 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 1 0 1
4 0 1 1 1
5 1 0 0 1
6 1 0 1 1
7 1 1 0 1
8 1 1 1 1
BUFR0:MUX.I 0.35.29 0.35.28 0.35.27 0.35.26 0.35.25 0.34.31 0.35.24 0.35.23
BUFR1:MUX.I 0.34.29 0.34.30 0.34.26 0.34.25 0.34.24 0.34.23 0.36.27 0.36.26
BUFR2:MUX.I 0.34.20 0.34.19 0.34.18 0.34.17 0.34.16 0.34.15 0.36.25 0.36.24
BUFR3:MUX.I 0.35.15 0.35.16 0.35.17 0.35.18 0.35.19 0.31.20 0.35.21 0.32.16
NONE 0 0 0 0 0 0 0 0
BUFIO0_I 0 0 0 0 0 0 0 1
BUFIO1_I 0 0 0 0 0 0 1 0
BUFIO2_I 0 0 0 0 0 1 0 0
BUFIO3_I 0 0 0 0 1 0 0 0
CKINT0 0 0 0 1 0 0 0 0
CKINT1 0 0 1 0 0 0 0 0
CKINT2 0 1 0 0 0 0 0 0
CKINT3 1 0 0 0 0 0 0 0
DRIVERBIAS:DRIVERBIAS 0.39.15 0.39.14 0.41.21 0.41.22 0.41.23 0.41.24 0.41.25 0.41.26 0.39.21 0.39.20 0.39.19 0.38.15 0.38.14 0.39.18 0.39.17 0.39.16
LVDS:GROUP0 0.40.29 0.38.27 0.38.28 0.41.15 0.41.16 0.41.17 0.41.18 0.41.19 0.41.20 0.41.14 0.41.27 0.41.28 0.41.29 0.38.25 0.38.24 0.38.23
LVDS:GROUP1 0.38.31 0.39.31 0.40.14 0.40.15 0.40.16 0.40.17 0.40.18 0.40.19 0.40.20 0.40.21 0.40.22 0.40.23 0.40.24 0.38.20 0.38.19 0.38.18
non-inverted [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
HCLK_IOI:MUX.HCLK_IO_D0 0.29.25 0.28.18 0.29.24 0.27.27 0.27.23 0.27.19 0.29.29
HCLK_IOI:MUX.HCLK_IO_D1 0.28.19 0.31.29 0.32.25 0.27.28 0.27.24 0.27.20 0.27.17
HCLK_IOI:MUX.HCLK_IO_D2 0.31.26 0.31.24 0.31.25 0.30.24 0.30.26 0.30.28 0.30.30
HCLK_IOI:MUX.HCLK_IO_D3 0.26.14 0.27.15 0.26.16 0.29.21 0.28.24 0.28.28 0.27.31
HCLK_IOI:MUX.HCLK_IO_D4 0.28.20 0.31.30 0.31.27 0.28.22 0.28.25 0.28.29 0.27.30
HCLK_IOI:MUX.HCLK_IO_D5 0.31.21 0.31.22 0.31.23 0.30.15 0.31.14 0.31.16 0.31.18
HCLK_IOI:MUX.HCLK_IO_U0 0.26.17 0.26.18 0.26.19 0.29.26 0.27.25 0.27.21 0.29.28
HCLK_IOI:MUX.HCLK_IO_U1 0.31.28 0.31.31 0.32.24 0.27.29 0.27.26 0.27.22 0.27.18
HCLK_IOI:MUX.HCLK_IO_U2 0.30.20 0.30.21 0.30.22 0.30.23 0.30.25 0.30.27 0.30.29
HCLK_IOI:MUX.HCLK_IO_U3 0.27.16 0.27.14 0.26.15 0.29.22 0.29.20 0.28.26 0.28.30
HCLK_IOI:MUX.HCLK_IO_U4 0.32.14 0.32.15 0.32.23 0.28.21 0.28.23 0.28.27 0.28.31
HCLK_IOI:MUX.HCLK_IO_U5 0.30.19 0.30.18 0.30.17 0.30.16 0.30.14 0.31.15 0.31.17
NONE 0 0 0 0 0 0 0
HCLK0 0 0 1 0 0 0 1
HCLK1 0 0 1 0 0 1 0
HCLK2 0 0 1 0 1 0 0
HCLK3 0 0 1 1 0 0 0
HCLK4 0 1 0 0 0 0 1
HCLK5 0 1 0 0 0 1 0
HCLK6 0 1 0 0 1 0 0
HCLK7 0 1 0 1 0 0 0
HCLK8 1 0 0 0 0 0 1
HCLK9 1 0 0 0 0 1 0
HCLK10 1 0 0 0 1 0 0
HCLK11 1 0 0 1 0 0 0
IDELAYCTRL:MODE 0.37.24 0.37.29 0.37.28
NONE 0 0 0
DEFAULT 0 0 1
FULL_0 0 1 1
FULL_1 1 1 1
IDELAYCTRL:MUX.REFCLK 0.26.31 0.26.30 0.26.29 0.26.28 0.26.27 0.26.26 0.26.25 0.26.24 0.26.23 0.26.22 0.26.21 0.26.20
NONE 0 0 0 0 0 0 0 0 0 0 0 0
HCLK_IO_D0 0 0 0 0 0 0 0 0 0 0 0 1
HCLK_IO_D1 0 0 0 0 0 0 0 0 0 0 1 0
HCLK_IO_D2 0 0 0 0 0 0 0 0 0 1 0 0
HCLK_IO_D3 0 0 0 0 0 0 0 0 1 0 0 0
HCLK_IO_D4 0 0 0 0 0 0 0 1 0 0 0 0
HCLK_IO_D5 0 0 0 0 0 0 1 0 0 0 0 0
HCLK_IO_U0 0 0 0 0 0 1 0 0 0 0 0 0
HCLK_IO_U1 0 0 0 0 1 0 0 0 0 0 0 0
HCLK_IO_U2 0 0 0 1 0 0 0 0 0 0 0 0
HCLK_IO_U3 0 0 1 0 0 0 0 0 0 0 0 0
HCLK_IO_U4 0 1 0 0 0 0 0 0 0 0 0 0
HCLK_IO_U5 1 0 0 0 0 0 0 0 0 0 0 0
INTERNAL_VREF:VREF 0.38.30 0.38.29 0.39.29 0.39.24 0.39.22 0.39.30 0.38.26
OFF 0 0 0 0 0 0 0
600 0 0 0 0 0 1 1
675 0 0 0 0 1 0 1
750 0 0 0 1 0 0 1
900 0 0 1 0 0 0 1
1100 0 1 0 0 0 0 1
1250 1 0 0 0 0 0 1
LVDS:COMMON 0.41.30 0.41.31 0.39.23 0.40.31 0.40.25 0.40.26 0.40.27 0.40.28 0.40.30
non-inverted [8] [7] [6] [5] [4] [3] [2] [1] [0]
VCCOSENSE:MODE 0.39.28 0.39.27 0.39.26 0.39.25
ALWAYSACTIVE 0 0 0 0
OFF 0 1 1 1
FREEZE 1 0 0 0

Tables — HP IO

Name HP_IOSTD:PDRIVE HP_IOSTD:NDRIVE
[6] [5] [4] [3] [2] [1] [0] [6] [5] [4] [3] [2] [1] [0]
HSTL_I 0 1 0 1 0 0 0 0 0 1 1 1 0 0
HSTL_II 1 0 1 0 1 1 0 0 1 1 1 0 0 0
HSTL_II_18 1 0 0 0 0 0 0 0 1 1 1 0 0 0
HSTL_II_DCI 1 0 1 0 0 1 0 0 1 1 1 0 0 0
HSTL_II_DCI_18 1 0 0 0 0 0 0 0 1 1 1 0 0 0
HSTL_II_T_DCI 0 1 0 1 0 0 0 0 0 1 1 1 0 0
HSTL_II_T_DCI_18 0 1 0 0 0 0 0 0 0 1 1 1 0 0
HSTL_I_12 1 0 1 0 1 0 0 0 1 0 0 1 0 0
HSTL_I_18 0 1 0 0 0 0 0 0 0 1 1 1 0 0
HSTL_I_DCI 0 1 0 1 0 0 0 0 0 1 1 1 0 0
HSTL_I_DCI_18 0 1 0 0 0 0 0 0 0 1 1 1 0 0
HSUL_12 1 0 0 0 0 0 0 0 1 0 0 0 0 0
LVCMOS12.2 0 0 1 0 0 1 0 0 0 0 1 1 0 0
LVCMOS12.4 0 1 0 0 0 1 0 0 0 1 0 1 0 0
LVCMOS12.6 0 1 1 1 0 0 0 0 0 1 1 1 0 0
LVCMOS12.8 1 0 0 1 1 0 0 0 1 0 0 1 0 0
LVCMOS15.12 1 0 0 0 0 1 0 0 1 1 0 0 0 0
LVCMOS15.16 1 0 1 1 0 1 0 1 0 0 0 0 0 0
LVCMOS15.2 0 0 0 1 1 0 0 0 0 0 1 0 0 0
LVCMOS15.4 0 0 1 0 1 1 0 0 0 1 0 0 0 0
LVCMOS15.6 0 1 0 0 0 0 0 0 0 1 1 0 0 0
LVCMOS15.8 0 1 0 1 1 0 0 0 1 0 0 0 0 0
LVCMOS18.12 0 1 0 1 1 0 0 0 1 0 1 0 0 0
LVCMOS18.16 0 1 1 1 0 1 0 0 1 1 0 1 0 0
LVCMOS18.2 0 0 0 1 0 0 0 0 0 0 1 0 0 0
LVCMOS18.4 0 0 0 1 1 1 0 0 0 0 1 1 0 0
LVCMOS18.6 0 0 1 1 1 1 0 0 0 1 0 1 0 0
LVCMOS18.8 0 0 1 1 1 0 0 0 0 1 1 0 0 0
OFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SSTL12 1 0 1 1 0 0 0 0 1 0 1 0 0 0
SSTL12_DCI 1 0 1 1 0 0 0 0 1 0 1 0 0 0
SSTL12_T_DCI 1 0 1 1 0 0 0 0 1 0 1 0 0 0
SSTL135 1 0 0 0 1 0 0 0 1 0 1 0 0 0
SSTL135_DCI 1 0 0 0 1 0 0 0 1 0 1 0 0 0
SSTL135_T_DCI 1 0 0 0 1 0 0 0 1 0 1 0 0 0
SSTL15 0 1 1 0 0 0 0 0 1 0 0 1 0 0
SSTL15_DCI 0 1 1 0 0 0 0 0 1 0 0 1 0 0
SSTL15_T_DCI 0 1 1 0 0 0 0 0 1 0 0 1 0 0
SSTL18_I 0 0 1 1 1 0 0 0 0 1 1 0 0 0
SSTL18_II 1 0 1 0 1 1 0 1 0 0 1 0 0 0
SSTL18_II_DCI 0 1 0 1 1 0 0 0 1 0 0 0 0 0
SSTL18_II_T_DCI 0 0 1 0 1 0 0 0 0 1 0 1 0 0
SSTL18_I_DCI 0 0 1 0 1 0 0 0 0 1 0 1 0 0
Name HP_IOSTD:PSLEW HP_IOSTD:NSLEW
[4] [3] [2] [1] [0] [4] [3] [2] [1] [0]
HSLVDCI_15 0 0 1 1 1 1 1 1 1 1
HSLVDCI_18 0 0 1 1 0 1 1 1 1 1
HSTL_I.FAST 1 1 1 0 0 1 1 1 1 1
HSTL_I.SLOW 0 0 0 1 0 0 0 0 0 1
HSTL_II.FAST 0 1 0 0 0 1 1 1 1 1
HSTL_II.SLOW 0 0 0 0 1 0 0 0 0 1
HSTL_II_18.FAST 0 0 1 0 0 1 1 1 1 1
HSTL_II_18.SLOW 0 0 0 0 1 0 0 0 1 0
HSTL_II_DCI.FAST 0 1 0 0 0 1 1 1 1 1
HSTL_II_DCI.SLOW 0 0 0 0 1 0 0 0 0 1
HSTL_II_DCI_18.FAST 0 0 1 0 0 1 1 1 1 1
HSTL_II_DCI_18.SLOW 0 0 0 0 1 0 0 0 1 0
HSTL_II_T_DCI.FAST 1 1 1 0 0 1 1 1 1 1
HSTL_II_T_DCI.SLOW 0 0 0 1 0 0 0 0 0 1
HSTL_II_T_DCI_18.FAST 0 0 1 1 1 1 1 1 1 1
HSTL_II_T_DCI_18.SLOW 0 0 0 0 1 0 0 0 1 1
HSTL_I_12.FAST 1 1 0 1 1 1 1 1 1 1
HSTL_I_12.SLOW 0 0 0 0 1 0 0 0 0 1
HSTL_I_18.FAST 0 0 1 1 1 1 1 1 1 1
HSTL_I_18.SLOW 0 0 0 0 1 0 0 0 1 1
HSTL_I_DCI.FAST 1 1 1 0 0 1 1 1 1 1
HSTL_I_DCI.SLOW 0 0 0 1 0 0 0 0 0 1
HSTL_I_DCI_18.FAST 0 0 1 1 1 1 1 1 1 1
HSTL_I_DCI_18.SLOW 0 0 0 0 1 0 0 0 1 1
HSUL_12.FAST 0 0 1 1 1 1 1 1 1 1
HSUL_12.SLOW 0 0 0 0 1 0 0 0 1 0
HSUL_12_DCI.FAST 0 0 1 1 1 1 1 1 1 1
HSUL_12_DCI.SLOW 0 0 0 0 1 0 0 0 1 0
LVCMOS12.2.FAST 1 1 1 1 1 1 1 0 0 0
LVCMOS12.2.SLOW 0 0 0 0 0 0 0 0 0 0
LVCMOS12.4.FAST 1 1 1 1 1 1 1 1 1 1
LVCMOS12.4.SLOW 0 0 0 0 0 0 0 0 0 0
LVCMOS12.6.FAST 1 1 1 1 1 1 1 1 1 1
LVCMOS12.6.SLOW 0 0 0 0 0 0 0 0 0 0
LVCMOS12.8.FAST 1 1 0 0 1 1 1 1 1 1
LVCMOS12.8.SLOW 0 0 0 0 0 0 0 0 0 0
LVCMOS15.12.FAST 0 1 0 0 0 1 1 1 1 1
LVCMOS15.12.SLOW 0 0 0 0 0 0 0 0 0 0
LVCMOS15.16.FAST 0 0 1 1 0 1 1 1 1 1
LVCMOS15.16.SLOW 0 0 0 0 0 0 0 0 0 0
LVCMOS15.2.FAST 1 1 1 1 1 0 0 0 0 1
LVCMOS15.2.SLOW 0 0 0 0 0 0 0 0 0 0
LVCMOS15.4.FAST 1 1 1 1 1 1 1 1 1 1
LVCMOS15.4.SLOW 0 0 0 0 0 0 0 0 0 0
LVCMOS15.6.FAST 1 1 1 1 1 1 1 1 1 1
LVCMOS15.6.SLOW 0 0 0 0 0 0 0 0 0 0
LVCMOS15.8.FAST 0 1 0 0 1 1 1 1 1 1
LVCMOS15.8.SLOW 0 0 0 0 0 0 0 0 0 0
LVCMOS18.12.FAST 0 1 1 1 1 1 1 1 1 1
LVCMOS18.12.SLOW 0 0 0 0 0 0 0 0 0 0
LVCMOS18.16.FAST 0 0 1 1 0 1 1 1 1 1
LVCMOS18.16.SLOW 0 0 0 0 0 0 0 0 0 0
LVCMOS18.2.FAST 1 0 0 0 1 1 1 1 1 1
LVCMOS18.2.SLOW 0 0 0 0 0 0 0 0 0 0
LVCMOS18.4.FAST 1 1 1 1 1 1 1 1 1 1
LVCMOS18.4.SLOW 0 0 0 0 0 0 0 0 0 0
LVCMOS18.6.FAST 0 0 1 1 1 1 1 1 1 1
LVCMOS18.6.SLOW 0 0 0 0 0 0 0 0 0 0
LVCMOS18.8.FAST 0 0 1 1 0 1 1 1 1 1
LVCMOS18.8.SLOW 0 0 0 0 0 0 0 0 0 0
LVDCI_15 0 0 1 1 1 1 1 1 1 1
LVDCI_18 0 0 1 1 0 1 1 1 1 1
LVDCI_DV2_15 0 1 1 1 1 1 1 0 0 0
LVDCI_DV2_18 0 1 1 0 0 1 1 0 0 0
OFF 0 0 0 0 0 0 0 0 0 0
SSTL12.FAST 1 1 0 1 0 1 1 1 1 1
SSTL12.SLOW 0 0 0 1 1 0 0 0 1 1
SSTL12_DCI.FAST 1 1 0 1 0 1 1 1 1 1
SSTL12_DCI.SLOW 0 0 0 1 1 0 0 0 1 1
SSTL12_T_DCI.FAST 1 1 0 1 0 1 1 1 1 1
SSTL12_T_DCI.SLOW 0 0 0 1 1 0 0 0 1 1
SSTL135.FAST 1 1 1 1 0 1 1 1 1 1
SSTL135.SLOW 0 0 0 1 1 0 0 0 1 1
SSTL135_DCI.FAST 1 1 1 1 0 1 1 1 1 1
SSTL135_DCI.SLOW 0 0 0 1 1 0 0 0 1 1
SSTL135_T_DCI.FAST 1 1 1 1 0 1 1 1 1 1
SSTL135_T_DCI.SLOW 0 0 0 1 1 0 0 0 1 1
SSTL15.FAST 1 1 1 1 1 1 1 0 1 0
SSTL15.SLOW 0 0 0 1 1 0 0 1 1 1
SSTL15_DCI.FAST 1 1 1 1 1 1 1 0 1 0
SSTL15_DCI.SLOW 0 0 0 1 1 0 0 1 1 1
SSTL15_T_DCI.FAST 1 1 1 1 1 1 1 0 1 0
SSTL15_T_DCI.SLOW 0 0 0 1 1 0 0 1 1 1
SSTL18_I.FAST 0 0 1 0 1 1 1 0 1 1
SSTL18_I.SLOW 0 0 0 0 1 0 0 0 1 1
SSTL18_II.FAST 0 0 0 1 1 1 1 1 1 1
SSTL18_II.SLOW 0 0 0 0 0 0 0 0 0 0
SSTL18_II_DCI.FAST 0 0 1 1 1 1 1 1 0 0
SSTL18_II_DCI.SLOW 0 0 0 1 1 0 0 1 0 1
SSTL18_II_T_DCI.FAST 0 0 1 0 1 1 1 1 1 1
SSTL18_II_T_DCI.SLOW 0 0 0 1 1 0 0 1 1 1
SSTL18_I_DCI.FAST 0 0 1 0 1 1 1 1 1 1
SSTL18_I_DCI.SLOW 0 0 0 1 1 0 0 1 1 1
VR 1 1 1 1 1 1 1 1 1 1
Name HP_IOSTD:LVDS_T HP_IOSTD:LVDS_C
[8] [7] [6] [5] [4] [3] [2] [1] [0] [8] [7] [6] [5] [4] [3] [2] [1] [0]
OFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OUTPUT_LVDS 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1
TERM_DYNAMIC_LVDS 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 1 1 1
TERM_LVDS 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 1
Name HP_IOSTD:LVDSBIAS
[17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
LVDS 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
OFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Name HP_IOSTD:DCI:PREF_OUTPUT HP_IOSTD:DCI:NREF_OUTPUT
[1] [0] [1] [0]
HSLVDCI_15 0 0 0 0
HSLVDCI_18 0 0 0 0
HSUL_12_DCI 0 1 1 0
LVDCI_15 0 1 1 0
LVDCI_18 0 1 1 0
OFF 0 0 0 0
Name HP_IOSTD:DCI:PREF_OUTPUT_HALF HP_IOSTD:DCI:NREF_OUTPUT_HALF
[2] [1] [0] [2] [1] [0]
LVDCI_DV2_15 0 1 1 1 0 0
LVDCI_DV2_18 1 0 1 1 0 0
OFF 0 0 0 0 0 0
Name HP_IOSTD:DCI:NREF_TERM_SPLIT
[2] [1] [0]
HSTL_II_DCI 0 0 1
HSTL_II_DCI_18 0 0 1
HSTL_II_T_DCI 0 0 1
HSTL_II_T_DCI_18 0 0 1
HSTL_I_DCI 0 0 1
HSTL_I_DCI_18 0 0 1
OFF 0 0 0
SSTL12_DCI 0 0 1
SSTL12_T_DCI 0 0 1
SSTL135_DCI 0 0 1
SSTL135_T_DCI 0 0 1
SSTL15_DCI 0 0 1
SSTL15_T_DCI 0 0 1
SSTL18_II_DCI 0 0 1
SSTL18_II_T_DCI 0 0 1
SSTL18_I_DCI 0 0 1

Tables — HR IO

Name HR_IOSTD:DRIVE
[6] [5] [4] [3] [2] [1] [0]
BLVDS_25 1 0 1 0 1 1 0
HSTL_I 0 1 0 0 0 1 1
HSTL_II 1 0 0 0 1 1 0
HSTL_II_18 1 1 0 0 1 1 1
HSTL_I_18 0 1 1 0 0 1 1
HSUL_12 0 1 1 0 1 1 1
LVCMOS12.12 0 1 1 0 1 1 1
LVCMOS12.4 0 0 1 0 0 1 0
LVCMOS12.8 0 1 0 0 1 0 0
LVCMOS15.12 0 1 1 0 1 0 1
LVCMOS15.16 1 0 1 0 1 1 1
LVCMOS15.4 0 0 1 0 0 0 1
LVCMOS15.8 0 1 0 0 0 1 1
LVCMOS18.12 0 1 0 0 0 1 0
LVCMOS18.16 0 1 1 0 0 1 1
LVCMOS18.24 1 1 0 0 1 1 0
LVCMOS18.4 0 0 1 0 0 0 1
LVCMOS18.8 0 1 0 0 0 1 0
LVCMOS25.12 0 1 1 0 1 0 0
LVCMOS25.16 1 0 1 0 1 1 0
LVCMOS25.4 0 0 1 0 0 0 1
LVCMOS25.8 0 1 0 0 1 0 0
LVCMOS33.12 0 1 1 0 0 1 1
LVCMOS33.16 1 0 1 0 1 0 1
LVCMOS33.4 0 0 1 0 0 0 1
LVCMOS33.8 0 1 0 0 0 1 0
LVTTL.12 0 1 0 0 0 1 0
LVTTL.16 0 1 1 0 0 1 1
LVTTL.24 1 1 0 0 1 1 0
LVTTL.4 0 0 1 0 0 0 1
LVTTL.8 0 1 0 0 0 1 0
MOBILE_DDR 0 1 0 0 0 1 0
OFF 0 0 0 0 0 0 0
PCI33_3 1 1 1 0 1 1 1
SSTL135 1 0 0 0 1 1 1
SSTL135_R 0 1 0 0 1 0 0
SSTL15 1 0 1 0 1 1 1
SSTL15_R 0 1 0 0 0 1 1
SSTL18_I 0 1 0 0 0 1 0
SSTL18_II 1 0 1 0 1 1 0
Name HR_IOSTD:SLEW
[9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
BLVDS_25 0 0 0 0 0 0 0 0 1 0
HSTL_I.FAST 0 1 0 1 0 0 0 1 1 0
HSTL_I.SLOW 0 1 1 0 0 1 1 0 1 0
HSTL_II.FAST 0 1 0 1 0 0 0 1 1 0
HSTL_II.SLOW 0 1 1 0 0 1 1 0 1 0
HSTL_II_18.FAST 0 1 0 1 0 1 0 1 1 0
HSTL_II_18.SLOW 0 1 1 0 0 1 1 0 1 0
HSTL_I_18.FAST 0 1 0 1 0 0 0 1 1 0
HSTL_I_18.SLOW 0 1 1 0 0 1 1 0 1 0
HSUL_12.FAST 0 1 0 1 0 1 1 1 1 0
HSUL_12.SLOW 0 1 1 0 0 1 1 0 1 0
LVCMOS12.12.FAST 0 0 0 0 0 0 0 0 1 0
LVCMOS12.12.SLOW 0 1 1 0 0 1 1 0 1 0
LVCMOS12.4.FAST 0 0 0 0 0 0 0 0 1 0
LVCMOS12.4.SLOW 0 1 1 0 0 1 1 0 1 0
LVCMOS12.8.FAST 0 0 0 0 0 0 0 0 1 0
LVCMOS12.8.SLOW 0 1 1 0 0 1 1 0 1 0
LVCMOS15.12.FAST 0 0 0 0 0 0 0 0 1 0
LVCMOS15.12.SLOW 0 1 1 0 0 1 1 0 1 0
LVCMOS15.16.FAST 0 0 0 0 0 0 0 0 1 0
LVCMOS15.16.SLOW 0 1 1 0 0 1 1 0 1 0
LVCMOS15.4.FAST 0 0 0 0 0 0 0 0 1 0
LVCMOS15.4.SLOW 0 1 1 0 0 1 1 0 1 0
LVCMOS15.8.FAST 0 0 0 0 0 0 0 0 1 0
LVCMOS15.8.SLOW 0 1 1 0 0 1 1 0 1 0
LVCMOS18.12.FAST 0 0 0 0 0 0 0 0 1 0
LVCMOS18.12.SLOW 0 1 1 0 0 1 1 0 1 0
LVCMOS18.16.FAST 0 0 0 0 0 0 0 0 1 0
LVCMOS18.16.SLOW 0 1 1 0 0 1 1 0 1 0
LVCMOS18.24.FAST 0 0 0 0 0 0 0 0 1 0
LVCMOS18.24.SLOW 0 1 1 0 0 1 1 0 1 0
LVCMOS18.4.FAST 0 0 0 0 0 0 0 0 1 0
LVCMOS18.4.SLOW 0 1 1 0 0 1 1 0 1 0
LVCMOS18.8.FAST 0 0 0 0 0 0 0 0 1 0
LVCMOS18.8.SLOW 0 1 1 0 0 1 1 0 1 0
LVCMOS25.12.FAST 0 0 0 0 0 0 0 0 1 0
LVCMOS25.12.SLOW 0 1 1 0 0 1 1 0 1 0
LVCMOS25.16.FAST 0 0 0 0 0 0 0 0 1 0
LVCMOS25.16.SLOW 0 1 1 0 0 1 1 0 1 0
LVCMOS25.4.FAST 0 0 0 0 0 0 0 0 1 0
LVCMOS25.4.SLOW 0 1 1 0 0 1 1 0 1 0
LVCMOS25.8.FAST 0 0 0 0 0 0 0 0 1 0
LVCMOS25.8.SLOW 0 1 1 0 0 1 1 0 1 0
LVCMOS33.12.FAST 0 0 0 0 0 0 0 0 0 1
LVCMOS33.12.SLOW 0 1 1 0 0 1 1 0 0 1
LVCMOS33.16.FAST 0 0 0 0 0 0 0 0 0 1
LVCMOS33.16.SLOW 0 1 1 0 0 1 1 0 0 1
LVCMOS33.4.FAST 0 0 0 0 0 0 0 0 0 1
LVCMOS33.4.SLOW 0 1 1 0 0 1 1 0 0 1
LVCMOS33.8.FAST 0 0 0 0 0 0 0 0 0 1
LVCMOS33.8.SLOW 0 1 1 0 0 1 1 0 0 1
LVTTL.12.FAST 0 0 0 0 0 0 0 0 0 1
LVTTL.12.SLOW 0 1 1 0 0 1 1 0 0 1
LVTTL.16.FAST 0 0 0 0 0 0 0 0 0 1
LVTTL.16.SLOW 0 1 1 0 0 1 1 0 0 1
LVTTL.24.FAST 0 0 0 0 0 0 0 0 0 1
LVTTL.24.SLOW 0 1 1 0 0 1 1 0 0 1
LVTTL.4.FAST 0 0 0 0 0 0 0 0 0 1
LVTTL.4.SLOW 0 1 1 0 0 1 1 0 0 1
LVTTL.8.FAST 0 0 0 0 0 0 0 0 0 1
LVTTL.8.SLOW 0 1 1 0 0 1 1 0 0 1
MOBILE_DDR.FAST 0 0 0 0 0 0 0 0 1 0
MOBILE_DDR.SLOW 0 1 1 0 0 1 1 0 1 0
OFF 0 0 0 0 0 0 0 0 0 0
PCI33_3 0 0 1 1 0 0 1 1 1 1
SSTL135.FAST 0 1 0 1 0 1 1 1 1 0
SSTL135.SLOW 0 1 1 0 0 1 1 0 1 0
SSTL135_R.FAST 0 1 0 1 0 1 1 1 1 0
SSTL135_R.SLOW 0 1 1 0 0 1 1 0 1 0
SSTL15.FAST 0 1 0 1 0 1 1 1 1 0
SSTL15.SLOW 0 1 1 0 0 1 1 0 1 0
SSTL15_R.FAST 0 1 0 1 0 1 1 1 1 0
SSTL15_R.SLOW 0 1 1 0 0 1 1 0 1 0
SSTL18_I.FAST 0 1 0 1 0 1 0 1 1 0
SSTL18_I.SLOW 0 1 1 0 0 1 1 0 1 0
SSTL18_II.FAST 0 1 0 1 0 1 0 1 1 0
SSTL18_II.SLOW 0 1 1 0 0 1 1 0 1 0
Name HR_IOSTD:OUTPUT_MISC
[2] [1] [0]
BLVDS_25 0 0 0
HSTL_I 0 0 0
HSTL_II 0 0 0
HSTL_II_18 0 0 0
HSTL_I_18 0 0 0
HSUL_12 0 0 0
LVCMOS12 0 0 0
LVCMOS15 0 0 0
LVCMOS18 0 0 0
LVCMOS25 0 0 0
LVCMOS33 0 0 0
LVTTL 0 0 0
MOBILE_DDR 0 0 0
OFF 0 0 0
PCI33_3 0 0 1
SSTL135 0 0 0
SSTL135_R 0 0 0
SSTL15 0 0 0
SSTL15_R 0 0 0
SSTL18_I 0 0 0
SSTL18_II 0 0 0
Name HR_IOSTD:LVDS_T HR_IOSTD:LVDS_C
[12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
OFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OUTPUT_LVDS_25 1 0 1 0 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
OUTPUT_MINI_LVDS_25 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OUTPUT_PPDS_25 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OUTPUT_RSDS_25 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OUTPUT_TMDS_33 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TERM_LVDS_25 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TERM_MINI_LVDS_25 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TERM_PPDS_25 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TERM_RSDS_25 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Name HR_IOSTD:DRIVERBIAS
[15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
1200 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1
1350 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1
1500 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1
1800 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1
2500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3300 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Name HR_IOSTD:LVDSBIAS:COMMON HR_IOSTD:LVDSBIAS:GROUP
[8] [7] [6] [5] [4] [3] [2] [1] [0] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
LVDS_25 0 1 1 0 1 0 1 0 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 1 1
MINI_LVDS_25 0 1 1 0 1 0 1 0 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 1 1
OFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PPDS_25 0 1 1 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 1 0 1 1 1
RSDS_25 0 1 1 0 1 0 1 0 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 1 1
TMDS_33 0 1 1 0 1 0 1 0 1 1 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0