PCI Express Gen3 cores
Tile PCIE3
Cells: 100
Bel PCIE3
| Pin | Direction | Wires |
|---|---|---|
| CFGCONFIGSPACEENABLE | input | CELL62.IMUX.IMUX21.DELAY |
| CFGCURRENTSPEED0 | output | CELL39.OUT9.TMIN |
| CFGCURRENTSPEED1 | output | CELL39.OUT10.TMIN |
| CFGCURRENTSPEED2 | output | CELL39.OUT11.TMIN |
| CFGDEVID0 | input | CELL89.IMUX.IMUX13.DELAY |
| CFGDEVID1 | input | CELL89.IMUX.IMUX14.DELAY |
| CFGDEVID10 | input | CELL93.IMUX.IMUX15.DELAY |
| CFGDEVID11 | input | CELL96.IMUX.IMUX12.DELAY |
| CFGDEVID12 | input | CELL97.IMUX.IMUX12.DELAY |
| CFGDEVID13 | input | CELL97.IMUX.IMUX13.DELAY |
| CFGDEVID14 | input | CELL97.IMUX.IMUX14.DELAY |
| CFGDEVID15 | input | CELL97.IMUX.IMUX15.DELAY |
| CFGDEVID2 | input | CELL89.IMUX.IMUX15.DELAY |
| CFGDEVID3 | input | CELL92.IMUX.IMUX12.DELAY |
| CFGDEVID4 | input | CELL92.IMUX.IMUX13.DELAY |
| CFGDEVID5 | input | CELL92.IMUX.IMUX14.DELAY |
| CFGDEVID6 | input | CELL92.IMUX.IMUX15.DELAY |
| CFGDEVID7 | input | CELL93.IMUX.IMUX12.DELAY |
| CFGDEVID8 | input | CELL93.IMUX.IMUX13.DELAY |
| CFGDEVID9 | input | CELL93.IMUX.IMUX14.DELAY |
| CFGDPASUBSTATECHANGE0 | output | CELL12.OUT19.TMIN |
| CFGDPASUBSTATECHANGE1 | output | CELL13.OUT16.TMIN |
| CFGDSBUSNUMBER0 | input | CELL73.IMUX.IMUX22.DELAY |
| CFGDSBUSNUMBER1 | input | CELL73.IMUX.IMUX23.DELAY |
| CFGDSBUSNUMBER2 | input | CELL74.IMUX.IMUX20.DELAY |
| CFGDSBUSNUMBER3 | input | CELL74.IMUX.IMUX21.DELAY |
| CFGDSBUSNUMBER4 | input | CELL74.IMUX.IMUX22.DELAY |
| CFGDSBUSNUMBER5 | input | CELL74.IMUX.IMUX23.DELAY |
| CFGDSBUSNUMBER6 | input | CELL75.IMUX.IMUX20.DELAY |
| CFGDSBUSNUMBER7 | input | CELL75.IMUX.IMUX21.DELAY |
| CFGDSDEVICENUMBER0 | input | CELL75.IMUX.IMUX22.DELAY |
| CFGDSDEVICENUMBER1 | input | CELL75.IMUX.IMUX23.DELAY |
| CFGDSDEVICENUMBER2 | input | CELL76.IMUX.IMUX20.DELAY |
| CFGDSDEVICENUMBER3 | input | CELL76.IMUX.IMUX21.DELAY |
| CFGDSDEVICENUMBER4 | input | CELL76.IMUX.IMUX22.DELAY |
| CFGDSFUNCTIONNUMBER0 | input | CELL76.IMUX.IMUX23.DELAY |
| CFGDSFUNCTIONNUMBER1 | input | CELL77.IMUX.IMUX20.DELAY |
| CFGDSFUNCTIONNUMBER2 | input | CELL77.IMUX.IMUX21.DELAY |
| CFGDSN0 | input | CELL64.IMUX.IMUX16.DELAY |
| CFGDSN1 | input | CELL64.IMUX.IMUX17.DELAY |
| CFGDSN10 | input | CELL68.IMUX.IMUX15.DELAY |
| CFGDSN11 | input | CELL71.IMUX.IMUX12.DELAY |
| CFGDSN12 | input | CELL71.IMUX.IMUX13.DELAY |
| CFGDSN13 | input | CELL71.IMUX.IMUX14.DELAY |
| CFGDSN14 | input | CELL72.IMUX.IMUX12.DELAY |
| CFGDSN15 | input | CELL72.IMUX.IMUX13.DELAY |
| CFGDSN16 | input | CELL72.IMUX.IMUX14.DELAY |
| CFGDSN17 | input | CELL72.IMUX.IMUX15.DELAY |
| CFGDSN18 | input | CELL73.IMUX.IMUX12.DELAY |
| CFGDSN19 | input | CELL73.IMUX.IMUX13.DELAY |
| CFGDSN2 | input | CELL64.IMUX.IMUX18.DELAY |
| CFGDSN20 | input | CELL73.IMUX.IMUX14.DELAY |
| CFGDSN21 | input | CELL73.IMUX.IMUX15.DELAY |
| CFGDSN22 | input | CELL74.IMUX.IMUX12.DELAY |
| CFGDSN23 | input | CELL74.IMUX.IMUX13.DELAY |
| CFGDSN24 | input | CELL74.IMUX.IMUX14.DELAY |
| CFGDSN25 | input | CELL74.IMUX.IMUX15.DELAY |
| CFGDSN26 | input | CELL75.IMUX.IMUX12.DELAY |
| CFGDSN27 | input | CELL75.IMUX.IMUX13.DELAY |
| CFGDSN28 | input | CELL75.IMUX.IMUX14.DELAY |
| CFGDSN29 | input | CELL75.IMUX.IMUX15.DELAY |
| CFGDSN3 | input | CELL64.IMUX.IMUX19.DELAY |
| CFGDSN30 | input | CELL76.IMUX.IMUX12.DELAY |
| CFGDSN31 | input | CELL76.IMUX.IMUX13.DELAY |
| CFGDSN32 | input | CELL76.IMUX.IMUX14.DELAY |
| CFGDSN33 | input | CELL76.IMUX.IMUX15.DELAY |
| CFGDSN34 | input | CELL77.IMUX.IMUX12.DELAY |
| CFGDSN35 | input | CELL77.IMUX.IMUX13.DELAY |
| CFGDSN36 | input | CELL77.IMUX.IMUX14.DELAY |
| CFGDSN37 | input | CELL77.IMUX.IMUX15.DELAY |
| CFGDSN38 | input | CELL78.IMUX.IMUX12.DELAY |
| CFGDSN39 | input | CELL78.IMUX.IMUX13.DELAY |
| CFGDSN4 | input | CELL67.IMUX.IMUX13.DELAY |
| CFGDSN40 | input | CELL78.IMUX.IMUX14.DELAY |
| CFGDSN41 | input | CELL78.IMUX.IMUX15.DELAY |
| CFGDSN42 | input | CELL81.IMUX.IMUX12.DELAY |
| CFGDSN43 | input | CELL81.IMUX.IMUX13.DELAY |
| CFGDSN44 | input | CELL81.IMUX.IMUX14.DELAY |
| CFGDSN45 | input | CELL81.IMUX.IMUX15.DELAY |
| CFGDSN46 | input | CELL82.IMUX.IMUX12.DELAY |
| CFGDSN47 | input | CELL82.IMUX.IMUX13.DELAY |
| CFGDSN48 | input | CELL82.IMUX.IMUX14.DELAY |
| CFGDSN49 | input | CELL82.IMUX.IMUX15.DELAY |
| CFGDSN5 | input | CELL67.IMUX.IMUX14.DELAY |
| CFGDSN50 | input | CELL85.IMUX.IMUX12.DELAY |
| CFGDSN51 | input | CELL86.IMUX.IMUX12.DELAY |
| CFGDSN52 | input | CELL86.IMUX.IMUX13.DELAY |
| CFGDSN53 | input | CELL86.IMUX.IMUX14.DELAY |
| CFGDSN54 | input | CELL86.IMUX.IMUX15.DELAY |
| CFGDSN55 | input | CELL87.IMUX.IMUX12.DELAY |
| CFGDSN56 | input | CELL87.IMUX.IMUX13.DELAY |
| CFGDSN57 | input | CELL87.IMUX.IMUX14.DELAY |
| CFGDSN58 | input | CELL87.IMUX.IMUX15.DELAY |
| CFGDSN59 | input | CELL88.IMUX.IMUX12.DELAY |
| CFGDSN6 | input | CELL67.IMUX.IMUX15.DELAY |
| CFGDSN60 | input | CELL88.IMUX.IMUX13.DELAY |
| CFGDSN61 | input | CELL88.IMUX.IMUX14.DELAY |
| CFGDSN62 | input | CELL88.IMUX.IMUX15.DELAY |
| CFGDSN63 | input | CELL89.IMUX.IMUX12.DELAY |
| CFGDSN7 | input | CELL68.IMUX.IMUX12.DELAY |
| CFGDSN8 | input | CELL68.IMUX.IMUX13.DELAY |
| CFGDSN9 | input | CELL68.IMUX.IMUX14.DELAY |
| CFGDSPORTNUMBER0 | input | CELL72.IMUX.IMUX18.DELAY |
| CFGDSPORTNUMBER1 | input | CELL72.IMUX.IMUX19.DELAY |
| CFGDSPORTNUMBER2 | input | CELL63.IMUX.IMUX20.DELAY |
| CFGDSPORTNUMBER3 | input | CELL63.IMUX.IMUX21.DELAY |
| CFGDSPORTNUMBER4 | input | CELL63.IMUX.IMUX22.DELAY |
| CFGDSPORTNUMBER5 | input | CELL63.IMUX.IMUX23.DELAY |
| CFGDSPORTNUMBER6 | input | CELL73.IMUX.IMUX20.DELAY |
| CFGDSPORTNUMBER7 | input | CELL73.IMUX.IMUX21.DELAY |
| CFGERRCORIN | input | CELL77.IMUX.IMUX23.DELAY |
| CFGERRCOROUT | output | CELL10.OUT18.TMIN |
| CFGERRFATALOUT | output | CELL10.OUT20.TMIN |
| CFGERRNONFATALOUT | output | CELL10.OUT19.TMIN |
| CFGERRUNCORIN | input | CELL87.IMUX.IMUX20.DELAY |
| CFGEXTFUNCTIONNUMBER0 | output | CELL73.OUT23.TMIN |
| CFGEXTFUNCTIONNUMBER1 | output | CELL74.OUT20.TMIN |
| CFGEXTFUNCTIONNUMBER2 | output | CELL74.OUT21.TMIN |
| CFGEXTFUNCTIONNUMBER3 | output | CELL74.OUT22.TMIN |
| CFGEXTFUNCTIONNUMBER4 | output | CELL74.OUT23.TMIN |
| CFGEXTFUNCTIONNUMBER5 | output | CELL75.OUT20.TMIN |
| CFGEXTFUNCTIONNUMBER6 | output | CELL75.OUT21.TMIN |
| CFGEXTFUNCTIONNUMBER7 | output | CELL75.OUT22.TMIN |
| CFGEXTREADDATA0 | input | CELL50.IMUX.IMUX28.DELAY |
| CFGEXTREADDATA1 | input | CELL50.IMUX.IMUX29.DELAY |
| CFGEXTREADDATA10 | input | CELL53.IMUX.IMUX20.DELAY |
| CFGEXTREADDATA11 | input | CELL53.IMUX.IMUX21.DELAY |
| CFGEXTREADDATA12 | input | CELL53.IMUX.IMUX22.DELAY |
| CFGEXTREADDATA13 | input | CELL53.IMUX.IMUX23.DELAY |
| CFGEXTREADDATA14 | input | CELL54.IMUX.IMUX12.DELAY |
| CFGEXTREADDATA15 | input | CELL54.IMUX.IMUX13.DELAY |
| CFGEXTREADDATA16 | input | CELL54.IMUX.IMUX14.DELAY |
| CFGEXTREADDATA17 | input | CELL54.IMUX.IMUX15.DELAY |
| CFGEXTREADDATA18 | input | CELL55.IMUX.IMUX12.DELAY |
| CFGEXTREADDATA19 | input | CELL55.IMUX.IMUX13.DELAY |
| CFGEXTREADDATA2 | input | CELL51.IMUX.IMUX26.DELAY |
| CFGEXTREADDATA20 | input | CELL55.IMUX.IMUX14.DELAY |
| CFGEXTREADDATA21 | input | CELL55.IMUX.IMUX15.DELAY |
| CFGEXTREADDATA22 | input | CELL56.IMUX.IMUX16.DELAY |
| CFGEXTREADDATA23 | input | CELL56.IMUX.IMUX17.DELAY |
| CFGEXTREADDATA24 | input | CELL56.IMUX.IMUX18.DELAY |
| CFGEXTREADDATA25 | input | CELL56.IMUX.IMUX19.DELAY |
| CFGEXTREADDATA26 | input | CELL57.IMUX.IMUX16.DELAY |
| CFGEXTREADDATA27 | input | CELL57.IMUX.IMUX17.DELAY |
| CFGEXTREADDATA28 | input | CELL57.IMUX.IMUX18.DELAY |
| CFGEXTREADDATA29 | input | CELL57.IMUX.IMUX19.DELAY |
| CFGEXTREADDATA3 | input | CELL51.IMUX.IMUX27.DELAY |
| CFGEXTREADDATA30 | input | CELL58.IMUX.IMUX11.DELAY |
| CFGEXTREADDATA31 | input | CELL58.IMUX.IMUX12.DELAY |
| CFGEXTREADDATA4 | input | CELL51.IMUX.IMUX28.DELAY |
| CFGEXTREADDATA5 | input | CELL51.IMUX.IMUX29.DELAY |
| CFGEXTREADDATA6 | input | CELL52.IMUX.IMUX24.DELAY |
| CFGEXTREADDATA7 | input | CELL52.IMUX.IMUX25.DELAY |
| CFGEXTREADDATA8 | input | CELL52.IMUX.IMUX26.DELAY |
| CFGEXTREADDATA9 | input | CELL52.IMUX.IMUX27.DELAY |
| CFGEXTREADDATAVALID | input | CELL58.IMUX.IMUX13.DELAY |
| CFGEXTREADRECEIVED | output | CELL70.OUT23.TMIN |
| CFGEXTREGISTERNUMBER0 | output | CELL71.OUT21.TMIN |
| CFGEXTREGISTERNUMBER1 | output | CELL71.OUT22.TMIN |
| CFGEXTREGISTERNUMBER2 | output | CELL71.OUT23.TMIN |
| CFGEXTREGISTERNUMBER3 | output | CELL72.OUT20.TMIN |
| CFGEXTREGISTERNUMBER4 | output | CELL72.OUT21.TMIN |
| CFGEXTREGISTERNUMBER5 | output | CELL72.OUT22.TMIN |
| CFGEXTREGISTERNUMBER6 | output | CELL72.OUT23.TMIN |
| CFGEXTREGISTERNUMBER7 | output | CELL73.OUT20.TMIN |
| CFGEXTREGISTERNUMBER8 | output | CELL73.OUT21.TMIN |
| CFGEXTREGISTERNUMBER9 | output | CELL73.OUT22.TMIN |
| CFGEXTWRITEBYTEENABLE0 | output | CELL89.OUT19.TMIN |
| CFGEXTWRITEBYTEENABLE1 | output | CELL90.OUT17.TMIN |
| CFGEXTWRITEBYTEENABLE2 | output | CELL90.OUT18.TMIN |
| CFGEXTWRITEBYTEENABLE3 | output | CELL90.OUT19.TMIN |
| CFGEXTWRITEDATA0 | output | CELL75.OUT23.TMIN |
| CFGEXTWRITEDATA1 | output | CELL79.OUT18.TMIN |
| CFGEXTWRITEDATA10 | output | CELL83.OUT23.TMIN |
| CFGEXTWRITEDATA11 | output | CELL84.OUT17.TMIN |
| CFGEXTWRITEDATA12 | output | CELL84.OUT18.TMIN |
| CFGEXTWRITEDATA13 | output | CELL84.OUT19.TMIN |
| CFGEXTWRITEDATA14 | output | CELL84.OUT20.TMIN |
| CFGEXTWRITEDATA15 | output | CELL85.OUT16.TMIN |
| CFGEXTWRITEDATA16 | output | CELL85.OUT17.TMIN |
| CFGEXTWRITEDATA17 | output | CELL85.OUT18.TMIN |
| CFGEXTWRITEDATA18 | output | CELL85.OUT19.TMIN |
| CFGEXTWRITEDATA19 | output | CELL86.OUT18.TMIN |
| CFGEXTWRITEDATA2 | output | CELL79.OUT19.TMIN |
| CFGEXTWRITEDATA20 | output | CELL86.OUT20.TMIN |
| CFGEXTWRITEDATA21 | output | CELL86.OUT21.TMIN |
| CFGEXTWRITEDATA22 | output | CELL87.OUT17.TMIN |
| CFGEXTWRITEDATA23 | output | CELL87.OUT18.TMIN |
| CFGEXTWRITEDATA24 | output | CELL87.OUT19.TMIN |
| CFGEXTWRITEDATA25 | output | CELL88.OUT16.TMIN |
| CFGEXTWRITEDATA26 | output | CELL88.OUT17.TMIN |
| CFGEXTWRITEDATA27 | output | CELL88.OUT18.TMIN |
| CFGEXTWRITEDATA28 | output | CELL88.OUT19.TMIN |
| CFGEXTWRITEDATA29 | output | CELL89.OUT16.TMIN |
| CFGEXTWRITEDATA3 | output | CELL80.OUT18.TMIN |
| CFGEXTWRITEDATA30 | output | CELL89.OUT17.TMIN |
| CFGEXTWRITEDATA31 | output | CELL89.OUT18.TMIN |
| CFGEXTWRITEDATA4 | output | CELL80.OUT19.TMIN |
| CFGEXTWRITEDATA5 | output | CELL81.OUT22.TMIN |
| CFGEXTWRITEDATA6 | output | CELL81.OUT23.TMIN |
| CFGEXTWRITEDATA7 | output | CELL82.OUT22.TMIN |
| CFGEXTWRITEDATA8 | output | CELL82.OUT23.TMIN |
| CFGEXTWRITEDATA9 | output | CELL83.OUT22.TMIN |
| CFGEXTWRITERECEIVED | output | CELL71.OUT20.TMIN |
| CFGFCCPLD0 | output | CELL71.OUT19.TMIN |
| CFGFCCPLD1 | output | CELL72.OUT16.TMIN |
| CFGFCCPLD10 | output | CELL74.OUT17.TMIN |
| CFGFCCPLD11 | output | CELL74.OUT18.TMIN |
| CFGFCCPLD2 | output | CELL72.OUT17.TMIN |
| CFGFCCPLD3 | output | CELL72.OUT18.TMIN |
| CFGFCCPLD4 | output | CELL72.OUT19.TMIN |
| CFGFCCPLD5 | output | CELL73.OUT16.TMIN |
| CFGFCCPLD6 | output | CELL73.OUT17.TMIN |
| CFGFCCPLD7 | output | CELL73.OUT18.TMIN |
| CFGFCCPLD8 | output | CELL73.OUT19.TMIN |
| CFGFCCPLD9 | output | CELL74.OUT16.TMIN |
| CFGFCCPLH0 | output | CELL69.OUT22.TMIN |
| CFGFCCPLH1 | output | CELL69.OUT23.TMIN |
| CFGFCCPLH2 | output | CELL70.OUT20.TMIN |
| CFGFCCPLH3 | output | CELL70.OUT21.TMIN |
| CFGFCCPLH4 | output | CELL70.OUT22.TMIN |
| CFGFCCPLH5 | output | CELL71.OUT16.TMIN |
| CFGFCCPLH6 | output | CELL71.OUT17.TMIN |
| CFGFCCPLH7 | output | CELL71.OUT18.TMIN |
| CFGFCNPD0 | output | CELL63.OUT22.TMIN |
| CFGFCNPD1 | output | CELL63.OUT23.TMIN |
| CFGFCNPD10 | output | CELL68.OUT22.TMIN |
| CFGFCNPD11 | output | CELL68.OUT23.TMIN |
| CFGFCNPD2 | output | CELL64.OUT22.TMIN |
| CFGFCNPD3 | output | CELL64.OUT23.TMIN |
| CFGFCNPD4 | output | CELL65.OUT18.TMIN |
| CFGFCNPD5 | output | CELL65.OUT19.TMIN |
| CFGFCNPD6 | output | CELL66.OUT18.TMIN |
| CFGFCNPD7 | output | CELL66.OUT19.TMIN |
| CFGFCNPD8 | output | CELL67.OUT22.TMIN |
| CFGFCNPD9 | output | CELL67.OUT23.TMIN |
| CFGFCNPH0 | output | CELL60.OUT20.TMIN |
| CFGFCNPH1 | output | CELL60.OUT21.TMIN |
| CFGFCNPH2 | output | CELL60.OUT22.TMIN |
| CFGFCNPH3 | output | CELL60.OUT23.TMIN |
| CFGFCNPH4 | output | CELL61.OUT22.TMIN |
| CFGFCNPH5 | output | CELL61.OUT23.TMIN |
| CFGFCNPH6 | output | CELL62.OUT22.TMIN |
| CFGFCNPH7 | output | CELL62.OUT23.TMIN |
| CFGFCPD0 | output | CELL54.OUT18.TMIN |
| CFGFCPD1 | output | CELL54.OUT19.TMIN |
| CFGFCPD10 | output | CELL59.OUT22.TMIN |
| CFGFCPD11 | output | CELL59.OUT23.TMIN |
| CFGFCPD2 | output | CELL55.OUT18.TMIN |
| CFGFCPD3 | output | CELL55.OUT19.TMIN |
| CFGFCPD4 | output | CELL56.OUT22.TMIN |
| CFGFCPD5 | output | CELL56.OUT23.TMIN |
| CFGFCPD6 | output | CELL57.OUT22.TMIN |
| CFGFCPD7 | output | CELL57.OUT23.TMIN |
| CFGFCPD8 | output | CELL58.OUT22.TMIN |
| CFGFCPD9 | output | CELL58.OUT23.TMIN |
| CFGFCPH0 | output | CELL50.OUT22.TMIN |
| CFGFCPH1 | output | CELL50.OUT23.TMIN |
| CFGFCPH2 | output | CELL51.OUT22.TMIN |
| CFGFCPH3 | output | CELL51.OUT23.TMIN |
| CFGFCPH4 | output | CELL52.OUT22.TMIN |
| CFGFCPH5 | output | CELL52.OUT23.TMIN |
| CFGFCPH6 | output | CELL53.OUT22.TMIN |
| CFGFCPH7 | output | CELL53.OUT23.TMIN |
| CFGFCSEL0 | input | CELL50.IMUX.IMUX24.DELAY |
| CFGFCSEL1 | input | CELL50.IMUX.IMUX25.DELAY |
| CFGFCSEL2 | input | CELL50.IMUX.IMUX26.DELAY |
| CFGFLRDONE0 | input | CELL87.IMUX.IMUX21.DELAY |
| CFGFLRDONE1 | input | CELL87.IMUX.IMUX22.DELAY |
| CFGFLRINPROCESS0 | output | CELL84.OUT13.TMIN |
| CFGFLRINPROCESS1 | output | CELL84.OUT14.TMIN |
| CFGFUNCTIONPOWERSTATE0 | output | CELL20.OUT19.TMIN |
| CFGFUNCTIONPOWERSTATE1 | output | CELL20.OUT20.TMIN |
| CFGFUNCTIONPOWERSTATE2 | output | CELL20.OUT21.TMIN |
| CFGFUNCTIONPOWERSTATE3 | output | CELL19.OUT20.TMIN |
| CFGFUNCTIONPOWERSTATE4 | output | CELL19.OUT21.TMIN |
| CFGFUNCTIONPOWERSTATE5 | output | CELL15.OUT19.TMIN |
| CFGFUNCTIONSTATUS0 | output | CELL39.OUT14.TMIN |
| CFGFUNCTIONSTATUS1 | output | CELL39.OUT15.TMIN |
| CFGFUNCTIONSTATUS2 | output | CELL38.OUT12.TMIN |
| CFGFUNCTIONSTATUS3 | output | CELL38.OUT13.TMIN |
| CFGFUNCTIONSTATUS4 | output | CELL38.OUT14.TMIN |
| CFGFUNCTIONSTATUS5 | output | CELL38.OUT15.TMIN |
| CFGFUNCTIONSTATUS6 | output | CELL37.OUT12.TMIN |
| CFGFUNCTIONSTATUS7 | output | CELL37.OUT13.TMIN |
| CFGHOTRESETIN | input | CELL62.IMUX.IMUX20.DELAY |
| CFGHOTRESETOUT | output | CELL78.OUT23.TMIN |
| CFGINPUTUPDATEDONE | output | CELL83.OUT19.TMIN |
| CFGINPUTUPDATEREQUEST | input | CELL62.IMUX.IMUX22.DELAY |
| CFGINTERRUPTAOUTPUT | output | CELL0.OUT22.TMIN |
| CFGINTERRUPTBOUTPUT | output | CELL2.OUT19.TMIN |
| CFGINTERRUPTCOUTPUT | output | CELL2.OUT21.TMIN |
| CFGINTERRUPTDOUTPUT | output | CELL4.OUT22.TMIN |
| CFGINTERRUPTINT0 | input | CELL1.IMUX.IMUX20.DELAY |
| CFGINTERRUPTINT1 | input | CELL1.IMUX.IMUX21.DELAY |
| CFGINTERRUPTINT2 | input | CELL1.IMUX.IMUX22.DELAY |
| CFGINTERRUPTINT3 | input | CELL1.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIATTR0 | input | CELL38.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIATTR1 | input | CELL38.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIATTR2 | input | CELL37.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSIDATA0 | output | CELL14.OUT21.TMIN |
| CFGINTERRUPTMSIDATA1 | output | CELL14.OUT22.TMIN |
| CFGINTERRUPTMSIDATA10 | output | CELL35.OUT23.TMIN |
| CFGINTERRUPTMSIDATA11 | output | CELL36.OUT19.TMIN |
| CFGINTERRUPTMSIDATA12 | output | CELL37.OUT16.TMIN |
| CFGINTERRUPTMSIDATA13 | output | CELL37.OUT17.TMIN |
| CFGINTERRUPTMSIDATA14 | output | CELL37.OUT18.TMIN |
| CFGINTERRUPTMSIDATA15 | output | CELL37.OUT19.TMIN |
| CFGINTERRUPTMSIDATA16 | output | CELL38.OUT16.TMIN |
| CFGINTERRUPTMSIDATA17 | output | CELL38.OUT17.TMIN |
| CFGINTERRUPTMSIDATA18 | output | CELL38.OUT18.TMIN |
| CFGINTERRUPTMSIDATA19 | output | CELL38.OUT19.TMIN |
| CFGINTERRUPTMSIDATA2 | output | CELL14.OUT23.TMIN |
| CFGINTERRUPTMSIDATA20 | output | CELL39.OUT16.TMIN |
| CFGINTERRUPTMSIDATA21 | output | CELL39.OUT17.TMIN |
| CFGINTERRUPTMSIDATA22 | output | CELL39.OUT18.TMIN |
| CFGINTERRUPTMSIDATA23 | output | CELL39.OUT19.TMIN |
| CFGINTERRUPTMSIDATA24 | output | CELL40.OUT15.TMIN |
| CFGINTERRUPTMSIDATA25 | output | CELL41.OUT21.TMIN |
| CFGINTERRUPTMSIDATA26 | output | CELL42.OUT21.TMIN |
| CFGINTERRUPTMSIDATA27 | output | CELL43.OUT20.TMIN |
| CFGINTERRUPTMSIDATA28 | output | CELL44.OUT16.TMIN |
| CFGINTERRUPTMSIDATA29 | output | CELL45.OUT17.TMIN |
| CFGINTERRUPTMSIDATA3 | output | CELL15.OUT22.TMIN |
| CFGINTERRUPTMSIDATA30 | output | CELL46.OUT16.TMIN |
| CFGINTERRUPTMSIDATA31 | output | CELL47.OUT21.TMIN |
| CFGINTERRUPTMSIDATA4 | output | CELL19.OUT22.TMIN |
| CFGINTERRUPTMSIDATA5 | output | CELL20.OUT22.TMIN |
| CFGINTERRUPTMSIDATA6 | output | CELL34.OUT22.TMIN |
| CFGINTERRUPTMSIDATA7 | output | CELL35.OUT20.TMIN |
| CFGINTERRUPTMSIDATA8 | output | CELL35.OUT21.TMIN |
| CFGINTERRUPTMSIDATA9 | output | CELL35.OUT22.TMIN |
| CFGINTERRUPTMSIENABLE0 | output | CELL4.OUT23.TMIN |
| CFGINTERRUPTMSIENABLE1 | output | CELL5.OUT15.TMIN |
| CFGINTERRUPTMSIFAIL | output | CELL12.OUT21.TMIN |
| CFGINTERRUPTMSIFUNCTIONNUMBER0 | input | CELL32.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSIFUNCTIONNUMBER1 | input | CELL32.IMUX.IMUX18.DELAY |
| CFGINTERRUPTMSIFUNCTIONNUMBER2 | input | CELL32.IMUX.IMUX19.DELAY |
| CFGINTERRUPTMSIINT0 | input | CELL2.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIINT1 | input | CELL3.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIINT10 | input | CELL5.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIINT11 | input | CELL5.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIINT12 | input | CELL5.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIINT13 | input | CELL6.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIINT14 | input | CELL6.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIINT15 | input | CELL6.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIINT16 | input | CELL6.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIINT17 | input | CELL7.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIINT18 | input | CELL7.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIINT19 | input | CELL7.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIINT2 | input | CELL3.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIINT20 | input | CELL7.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIINT21 | input | CELL8.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIINT22 | input | CELL8.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIINT23 | input | CELL8.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIINT24 | input | CELL8.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIINT25 | input | CELL9.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIINT26 | input | CELL9.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIINT27 | input | CELL9.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIINT28 | input | CELL9.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIINT29 | input | CELL10.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIINT3 | input | CELL3.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIINT30 | input | CELL10.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIINT31 | input | CELL10.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIINT4 | input | CELL3.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIINT5 | input | CELL4.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIINT6 | input | CELL4.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIINT7 | input | CELL4.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIINT8 | input | CELL4.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIINT9 | input | CELL5.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIMASKUPDATE | output | CELL14.OUT20.TMIN |
| CFGINTERRUPTMSIMMENABLE0 | output | CELL12.OUT22.TMIN |
| CFGINTERRUPTMSIMMENABLE1 | output | CELL12.OUT23.TMIN |
| CFGINTERRUPTMSIMMENABLE2 | output | CELL13.OUT20.TMIN |
| CFGINTERRUPTMSIMMENABLE3 | output | CELL13.OUT21.TMIN |
| CFGINTERRUPTMSIMMENABLE4 | output | CELL13.OUT22.TMIN |
| CFGINTERRUPTMSIMMENABLE5 | output | CELL13.OUT23.TMIN |
| CFGINTERRUPTMSIPENDINGSTATUS0 | input | CELL10.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS1 | input | CELL11.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS10 | input | CELL13.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS11 | input | CELL13.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS12 | input | CELL13.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS13 | input | CELL14.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS14 | input | CELL14.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS15 | input | CELL14.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS16 | input | CELL14.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS17 | input | CELL15.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS18 | input | CELL15.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS19 | input | CELL15.IMUX.IMUX18.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS2 | input | CELL11.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS20 | input | CELL15.IMUX.IMUX19.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS21 | input | CELL16.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS22 | input | CELL16.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS23 | input | CELL16.IMUX.IMUX18.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS24 | input | CELL16.IMUX.IMUX19.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS25 | input | CELL17.IMUX.IMUX12.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS26 | input | CELL17.IMUX.IMUX13.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS27 | input | CELL17.IMUX.IMUX14.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS28 | input | CELL17.IMUX.IMUX15.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS29 | input | CELL18.IMUX.IMUX12.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS3 | input | CELL11.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS30 | input | CELL18.IMUX.IMUX13.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS31 | input | CELL18.IMUX.IMUX14.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS32 | input | CELL18.IMUX.IMUX15.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS33 | input | CELL19.IMUX.IMUX12.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS34 | input | CELL19.IMUX.IMUX13.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS35 | input | CELL19.IMUX.IMUX14.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS36 | input | CELL19.IMUX.IMUX15.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS37 | input | CELL20.IMUX.IMUX12.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS38 | input | CELL20.IMUX.IMUX13.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS39 | input | CELL20.IMUX.IMUX14.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS4 | input | CELL11.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS40 | input | CELL20.IMUX.IMUX15.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS41 | input | CELL21.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS42 | input | CELL21.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS43 | input | CELL21.IMUX.IMUX18.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS44 | input | CELL21.IMUX.IMUX19.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS45 | input | CELL22.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS46 | input | CELL22.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS47 | input | CELL22.IMUX.IMUX18.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS48 | input | CELL22.IMUX.IMUX19.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS49 | input | CELL23.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS5 | input | CELL12.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS50 | input | CELL23.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS51 | input | CELL23.IMUX.IMUX18.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS52 | input | CELL23.IMUX.IMUX19.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS53 | input | CELL24.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS54 | input | CELL24.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS55 | input | CELL24.IMUX.IMUX18.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS56 | input | CELL24.IMUX.IMUX19.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS57 | input | CELL25.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS58 | input | CELL25.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS59 | input | CELL25.IMUX.IMUX18.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS6 | input | CELL12.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS60 | input | CELL25.IMUX.IMUX19.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS61 | input | CELL26.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS62 | input | CELL26.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS63 | input | CELL26.IMUX.IMUX18.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS7 | input | CELL12.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS8 | input | CELL12.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIPENDINGSTATUS9 | input | CELL13.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSISELECT0 | input | CELL26.IMUX.IMUX19.DELAY |
| CFGINTERRUPTMSISELECT1 | input | CELL27.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSISELECT2 | input | CELL27.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSISELECT3 | input | CELL27.IMUX.IMUX18.DELAY |
| CFGINTERRUPTMSISENT | output | CELL12.OUT20.TMIN |
| CFGINTERRUPTMSITPHPRESENT | input | CELL37.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSITPHSTTAG0 | input | CELL35.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSITPHSTTAG1 | input | CELL35.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSITPHSTTAG2 | input | CELL35.IMUX.IMUX18.DELAY |
| CFGINTERRUPTMSITPHSTTAG3 | input | CELL35.IMUX.IMUX19.DELAY |
| CFGINTERRUPTMSITPHSTTAG4 | input | CELL34.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSITPHSTTAG5 | input | CELL34.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSITPHSTTAG6 | input | CELL33.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSITPHSTTAG7 | input | CELL33.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSITPHSTTAG8 | input | CELL32.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSITPHTYPE0 | input | CELL36.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSITPHTYPE1 | input | CELL36.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIVFENABLE0 | output | CELL7.OUT19.TMIN |
| CFGINTERRUPTMSIVFENABLE1 | output | CELL9.OUT22.TMIN |
| CFGINTERRUPTMSIVFENABLE2 | output | CELL11.OUT20.TMIN |
| CFGINTERRUPTMSIVFENABLE3 | output | CELL11.OUT21.TMIN |
| CFGINTERRUPTMSIVFENABLE4 | output | CELL11.OUT22.TMIN |
| CFGINTERRUPTMSIVFENABLE5 | output | CELL11.OUT23.TMIN |
| CFGINTERRUPTMSIXADDRESS0 | input | CELL27.IMUX.IMUX19.DELAY |
| CFGINTERRUPTMSIXADDRESS1 | input | CELL28.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSIXADDRESS10 | input | CELL32.IMUX.IMUX13.DELAY |
| CFGINTERRUPTMSIXADDRESS11 | input | CELL32.IMUX.IMUX14.DELAY |
| CFGINTERRUPTMSIXADDRESS12 | input | CELL32.IMUX.IMUX15.DELAY |
| CFGINTERRUPTMSIXADDRESS13 | input | CELL33.IMUX.IMUX12.DELAY |
| CFGINTERRUPTMSIXADDRESS14 | input | CELL33.IMUX.IMUX13.DELAY |
| CFGINTERRUPTMSIXADDRESS15 | input | CELL33.IMUX.IMUX14.DELAY |
| CFGINTERRUPTMSIXADDRESS16 | input | CELL33.IMUX.IMUX15.DELAY |
| CFGINTERRUPTMSIXADDRESS17 | input | CELL34.IMUX.IMUX12.DELAY |
| CFGINTERRUPTMSIXADDRESS18 | input | CELL34.IMUX.IMUX13.DELAY |
| CFGINTERRUPTMSIXADDRESS19 | input | CELL34.IMUX.IMUX14.DELAY |
| CFGINTERRUPTMSIXADDRESS2 | input | CELL28.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSIXADDRESS20 | input | CELL34.IMUX.IMUX15.DELAY |
| CFGINTERRUPTMSIXADDRESS21 | input | CELL36.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSIXADDRESS22 | input | CELL36.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSIXADDRESS23 | input | CELL36.IMUX.IMUX18.DELAY |
| CFGINTERRUPTMSIXADDRESS24 | input | CELL36.IMUX.IMUX19.DELAY |
| CFGINTERRUPTMSIXADDRESS25 | input | CELL37.IMUX.IMUX12.DELAY |
| CFGINTERRUPTMSIXADDRESS26 | input | CELL37.IMUX.IMUX13.DELAY |
| CFGINTERRUPTMSIXADDRESS27 | input | CELL37.IMUX.IMUX14.DELAY |
| CFGINTERRUPTMSIXADDRESS28 | input | CELL37.IMUX.IMUX15.DELAY |
| CFGINTERRUPTMSIXADDRESS29 | input | CELL38.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSIXADDRESS3 | input | CELL29.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSIXADDRESS30 | input | CELL38.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSIXADDRESS31 | input | CELL38.IMUX.IMUX18.DELAY |
| CFGINTERRUPTMSIXADDRESS32 | input | CELL38.IMUX.IMUX19.DELAY |
| CFGINTERRUPTMSIXADDRESS33 | input | CELL39.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIXADDRESS34 | input | CELL39.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIXADDRESS35 | input | CELL39.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIXADDRESS36 | input | CELL39.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIXADDRESS37 | input | CELL40.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIXADDRESS38 | input | CELL40.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIXADDRESS39 | input | CELL40.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIXADDRESS4 | input | CELL29.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSIXADDRESS40 | input | CELL40.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIXADDRESS41 | input | CELL41.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIXADDRESS42 | input | CELL41.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIXADDRESS43 | input | CELL41.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIXADDRESS44 | input | CELL41.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIXADDRESS45 | input | CELL42.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIXADDRESS46 | input | CELL42.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIXADDRESS47 | input | CELL42.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIXADDRESS48 | input | CELL42.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIXADDRESS49 | input | CELL43.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIXADDRESS5 | input | CELL30.IMUX.IMUX16.DELAY |
| CFGINTERRUPTMSIXADDRESS50 | input | CELL43.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIXADDRESS51 | input | CELL43.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIXADDRESS52 | input | CELL43.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIXADDRESS53 | input | CELL44.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIXADDRESS54 | input | CELL44.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIXADDRESS55 | input | CELL44.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIXADDRESS56 | input | CELL44.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIXADDRESS57 | input | CELL45.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIXADDRESS58 | input | CELL45.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIXADDRESS59 | input | CELL45.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIXADDRESS6 | input | CELL30.IMUX.IMUX17.DELAY |
| CFGINTERRUPTMSIXADDRESS60 | input | CELL45.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIXADDRESS61 | input | CELL46.IMUX.IMUX20.DELAY |
| CFGINTERRUPTMSIXADDRESS62 | input | CELL46.IMUX.IMUX21.DELAY |
| CFGINTERRUPTMSIXADDRESS63 | input | CELL46.IMUX.IMUX22.DELAY |
| CFGINTERRUPTMSIXADDRESS7 | input | CELL31.IMUX.IMUX14.DELAY |
| CFGINTERRUPTMSIXADDRESS8 | input | CELL31.IMUX.IMUX15.DELAY |
| CFGINTERRUPTMSIXADDRESS9 | input | CELL32.IMUX.IMUX12.DELAY |
| CFGINTERRUPTMSIXDATA0 | input | CELL46.IMUX.IMUX23.DELAY |
| CFGINTERRUPTMSIXDATA1 | input | CELL47.IMUX.IMUX24.DELAY |
| CFGINTERRUPTMSIXDATA10 | input | CELL49.IMUX.IMUX13.DELAY |
| CFGINTERRUPTMSIXDATA11 | input | CELL49.IMUX.IMUX14.DELAY |
| CFGINTERRUPTMSIXDATA12 | input | CELL49.IMUX.IMUX15.DELAY |
| CFGINTERRUPTMSIXDATA13 | input | CELL48.IMUX.IMUX28.DELAY |
| CFGINTERRUPTMSIXDATA14 | input | CELL48.IMUX.IMUX29.DELAY |
| CFGINTERRUPTMSIXDATA15 | input | CELL47.IMUX.IMUX28.DELAY |
| CFGINTERRUPTMSIXDATA16 | input | CELL47.IMUX.IMUX29.DELAY |
| CFGINTERRUPTMSIXDATA17 | input | CELL46.IMUX.IMUX24.DELAY |
| CFGINTERRUPTMSIXDATA18 | input | CELL46.IMUX.IMUX25.DELAY |
| CFGINTERRUPTMSIXDATA19 | input | CELL45.IMUX.IMUX24.DELAY |
| CFGINTERRUPTMSIXDATA2 | input | CELL47.IMUX.IMUX25.DELAY |
| CFGINTERRUPTMSIXDATA20 | input | CELL45.IMUX.IMUX25.DELAY |
| CFGINTERRUPTMSIXDATA21 | input | CELL44.IMUX.IMUX24.DELAY |
| CFGINTERRUPTMSIXDATA22 | input | CELL44.IMUX.IMUX25.DELAY |
| CFGINTERRUPTMSIXDATA23 | input | CELL43.IMUX.IMUX24.DELAY |
| CFGINTERRUPTMSIXDATA24 | input | CELL43.IMUX.IMUX25.DELAY |
| CFGINTERRUPTMSIXDATA25 | input | CELL42.IMUX.IMUX24.DELAY |
| CFGINTERRUPTMSIXDATA26 | input | CELL42.IMUX.IMUX25.DELAY |
| CFGINTERRUPTMSIXDATA27 | input | CELL41.IMUX.IMUX24.DELAY |
| CFGINTERRUPTMSIXDATA28 | input | CELL41.IMUX.IMUX25.DELAY |
| CFGINTERRUPTMSIXDATA29 | input | CELL40.IMUX.IMUX24.DELAY |
| CFGINTERRUPTMSIXDATA3 | input | CELL47.IMUX.IMUX26.DELAY |
| CFGINTERRUPTMSIXDATA30 | input | CELL40.IMUX.IMUX25.DELAY |
| CFGINTERRUPTMSIXDATA31 | input | CELL39.IMUX.IMUX24.DELAY |
| CFGINTERRUPTMSIXDATA4 | input | CELL47.IMUX.IMUX27.DELAY |
| CFGINTERRUPTMSIXDATA5 | input | CELL48.IMUX.IMUX24.DELAY |
| CFGINTERRUPTMSIXDATA6 | input | CELL48.IMUX.IMUX25.DELAY |
| CFGINTERRUPTMSIXDATA7 | input | CELL48.IMUX.IMUX26.DELAY |
| CFGINTERRUPTMSIXDATA8 | input | CELL48.IMUX.IMUX27.DELAY |
| CFGINTERRUPTMSIXDATA9 | input | CELL49.IMUX.IMUX12.DELAY |
| CFGINTERRUPTMSIXENABLE0 | output | CELL47.OUT23.TMIN |
| CFGINTERRUPTMSIXENABLE1 | output | CELL48.OUT20.TMIN |
| CFGINTERRUPTMSIXFAIL | output | CELL38.OUT22.TMIN |
| CFGINTERRUPTMSIXINT | input | CELL39.IMUX.IMUX25.DELAY |
| CFGINTERRUPTMSIXMASK0 | output | CELL48.OUT23.TMIN |
| CFGINTERRUPTMSIXMASK1 | output | CELL49.OUT22.TMIN |
| CFGINTERRUPTMSIXSENT | output | CELL38.OUT21.TMIN |
| CFGINTERRUPTMSIXVFENABLE0 | output | CELL49.OUT23.TMIN |
| CFGINTERRUPTMSIXVFENABLE1 | output | CELL46.OUT20.TMIN |
| CFGINTERRUPTMSIXVFENABLE2 | output | CELL45.OUT22.TMIN |
| CFGINTERRUPTMSIXVFENABLE3 | output | CELL44.OUT19.TMIN |
| CFGINTERRUPTMSIXVFENABLE4 | output | CELL42.OUT23.TMIN |
| CFGINTERRUPTMSIXVFENABLE5 | output | CELL41.OUT23.TMIN |
| CFGINTERRUPTMSIXVFMASK0 | output | CELL40.OUT22.TMIN |
| CFGINTERRUPTMSIXVFMASK1 | output | CELL39.OUT20.TMIN |
| CFGINTERRUPTMSIXVFMASK2 | output | CELL39.OUT21.TMIN |
| CFGINTERRUPTMSIXVFMASK3 | output | CELL39.OUT22.TMIN |
| CFGINTERRUPTMSIXVFMASK4 | output | CELL39.OUT23.TMIN |
| CFGINTERRUPTMSIXVFMASK5 | output | CELL38.OUT20.TMIN |
| CFGINTERRUPTPENDING0 | input | CELL2.IMUX.IMUX20.DELAY |
| CFGINTERRUPTPENDING1 | input | CELL2.IMUX.IMUX21.DELAY |
| CFGINTERRUPTSENT | output | CELL0.OUT15.TMIN |
| CFGLINKPOWERSTATE0 | output | CELL10.OUT16.TMIN |
| CFGLINKPOWERSTATE1 | output | CELL10.OUT17.TMIN |
| CFGLINKTRAININGENABLE | input | CELL98.IMUX.IMUX22.DELAY |
| CFGLOCALERROR | output | CELL10.OUT21.TMIN |
| CFGLTRENABLE | output | CELL10.OUT22.TMIN |
| CFGLTSSMSTATE0 | output | CELL10.OUT23.TMIN |
| CFGLTSSMSTATE1 | output | CELL11.OUT16.TMIN |
| CFGLTSSMSTATE2 | output | CELL11.OUT17.TMIN |
| CFGLTSSMSTATE3 | output | CELL11.OUT18.TMIN |
| CFGLTSSMSTATE4 | output | CELL11.OUT19.TMIN |
| CFGLTSSMSTATE5 | output | CELL12.OUT16.TMIN |
| CFGMAXPAYLOAD0 | output | CELL42.OUT20.TMIN |
| CFGMAXPAYLOAD1 | output | CELL47.OUT20.TMIN |
| CFGMAXPAYLOAD2 | output | CELL49.OUT20.TMIN |
| CFGMAXREADREQ0 | output | CELL49.OUT21.TMIN |
| CFGMAXREADREQ1 | output | CELL39.OUT12.TMIN |
| CFGMAXREADREQ2 | output | CELL39.OUT13.TMIN |
| CFGMCUPDATEDONE | output | CELL83.OUT21.TMIN |
| CFGMCUPDATEREQUEST | input | CELL63.IMUX.IMUX19.DELAY |
| CFGMGMTADDR0 | input | CELL7.IMUX.IMUX18.DELAY |
| CFGMGMTADDR1 | input | CELL7.IMUX.IMUX19.DELAY |
| CFGMGMTADDR10 | input | CELL10.IMUX.IMUX16.DELAY |
| CFGMGMTADDR11 | input | CELL10.IMUX.IMUX17.DELAY |
| CFGMGMTADDR12 | input | CELL10.IMUX.IMUX18.DELAY |
| CFGMGMTADDR13 | input | CELL10.IMUX.IMUX19.DELAY |
| CFGMGMTADDR14 | input | CELL11.IMUX.IMUX16.DELAY |
| CFGMGMTADDR15 | input | CELL11.IMUX.IMUX17.DELAY |
| CFGMGMTADDR16 | input | CELL11.IMUX.IMUX18.DELAY |
| CFGMGMTADDR17 | input | CELL11.IMUX.IMUX19.DELAY |
| CFGMGMTADDR18 | input | CELL12.IMUX.IMUX16.DELAY |
| CFGMGMTADDR2 | input | CELL8.IMUX.IMUX16.DELAY |
| CFGMGMTADDR3 | input | CELL8.IMUX.IMUX17.DELAY |
| CFGMGMTADDR4 | input | CELL8.IMUX.IMUX18.DELAY |
| CFGMGMTADDR5 | input | CELL8.IMUX.IMUX19.DELAY |
| CFGMGMTADDR6 | input | CELL9.IMUX.IMUX16.DELAY |
| CFGMGMTADDR7 | input | CELL9.IMUX.IMUX17.DELAY |
| CFGMGMTADDR8 | input | CELL9.IMUX.IMUX18.DELAY |
| CFGMGMTADDR9 | input | CELL9.IMUX.IMUX19.DELAY |
| CFGMGMTBYTEENABLE0 | input | CELL21.IMUX.IMUX12.DELAY |
| CFGMGMTBYTEENABLE1 | input | CELL21.IMUX.IMUX13.DELAY |
| CFGMGMTBYTEENABLE2 | input | CELL21.IMUX.IMUX14.DELAY |
| CFGMGMTBYTEENABLE3 | input | CELL21.IMUX.IMUX15.DELAY |
| CFGMGMTREAD | input | CELL22.IMUX.IMUX12.DELAY |
| CFGMGMTREADDATA0 | output | CELL19.OUT16.TMIN |
| CFGMGMTREADDATA1 | output | CELL19.OUT17.TMIN |
| CFGMGMTREADDATA10 | output | CELL22.OUT17.TMIN |
| CFGMGMTREADDATA11 | output | CELL24.OUT20.TMIN |
| CFGMGMTREADDATA12 | output | CELL24.OUT21.TMIN |
| CFGMGMTREADDATA13 | output | CELL25.OUT19.TMIN |
| CFGMGMTREADDATA14 | output | CELL25.OUT20.TMIN |
| CFGMGMTREADDATA15 | output | CELL25.OUT21.TMIN |
| CFGMGMTREADDATA16 | output | CELL29.OUT20.TMIN |
| CFGMGMTREADDATA17 | output | CELL29.OUT21.TMIN |
| CFGMGMTREADDATA18 | output | CELL30.OUT19.TMIN |
| CFGMGMTREADDATA19 | output | CELL30.OUT20.TMIN |
| CFGMGMTREADDATA2 | output | CELL19.OUT18.TMIN |
| CFGMGMTREADDATA20 | output | CELL30.OUT21.TMIN |
| CFGMGMTREADDATA21 | output | CELL34.OUT18.TMIN |
| CFGMGMTREADDATA22 | output | CELL34.OUT19.TMIN |
| CFGMGMTREADDATA23 | output | CELL35.OUT8.TMIN |
| CFGMGMTREADDATA24 | output | CELL35.OUT9.TMIN |
| CFGMGMTREADDATA25 | output | CELL35.OUT10.TMIN |
| CFGMGMTREADDATA26 | output | CELL35.OUT11.TMIN |
| CFGMGMTREADDATA27 | output | CELL36.OUT8.TMIN |
| CFGMGMTREADDATA28 | output | CELL36.OUT9.TMIN |
| CFGMGMTREADDATA29 | output | CELL36.OUT10.TMIN |
| CFGMGMTREADDATA3 | output | CELL19.OUT19.TMIN |
| CFGMGMTREADDATA30 | output | CELL36.OUT11.TMIN |
| CFGMGMTREADDATA31 | output | CELL37.OUT8.TMIN |
| CFGMGMTREADDATA4 | output | CELL20.OUT15.TMIN |
| CFGMGMTREADDATA5 | output | CELL20.OUT16.TMIN |
| CFGMGMTREADDATA6 | output | CELL20.OUT17.TMIN |
| CFGMGMTREADDATA7 | output | CELL20.OUT18.TMIN |
| CFGMGMTREADDATA8 | output | CELL22.OUT14.TMIN |
| CFGMGMTREADDATA9 | output | CELL22.OUT16.TMIN |
| CFGMGMTREADWRITEDONE | output | CELL37.OUT9.TMIN |
| CFGMGMTTYPE1CFGREGACCESS | input | CELL22.IMUX.IMUX13.DELAY |
| CFGMGMTWRITE | input | CELL12.IMUX.IMUX17.DELAY |
| CFGMGMTWRITEDATA0 | input | CELL12.IMUX.IMUX18.DELAY |
| CFGMGMTWRITEDATA1 | input | CELL12.IMUX.IMUX19.DELAY |
| CFGMGMTWRITEDATA10 | input | CELL15.IMUX.IMUX14.DELAY |
| CFGMGMTWRITEDATA11 | input | CELL15.IMUX.IMUX15.DELAY |
| CFGMGMTWRITEDATA12 | input | CELL16.IMUX.IMUX12.DELAY |
| CFGMGMTWRITEDATA13 | input | CELL16.IMUX.IMUX13.DELAY |
| CFGMGMTWRITEDATA14 | input | CELL16.IMUX.IMUX14.DELAY |
| CFGMGMTWRITEDATA15 | input | CELL16.IMUX.IMUX15.DELAY |
| CFGMGMTWRITEDATA16 | input | CELL17.IMUX.IMUX8.DELAY |
| CFGMGMTWRITEDATA17 | input | CELL17.IMUX.IMUX9.DELAY |
| CFGMGMTWRITEDATA18 | input | CELL17.IMUX.IMUX10.DELAY |
| CFGMGMTWRITEDATA19 | input | CELL17.IMUX.IMUX11.DELAY |
| CFGMGMTWRITEDATA2 | input | CELL13.IMUX.IMUX16.DELAY |
| CFGMGMTWRITEDATA20 | input | CELL18.IMUX.IMUX8.DELAY |
| CFGMGMTWRITEDATA21 | input | CELL18.IMUX.IMUX9.DELAY |
| CFGMGMTWRITEDATA22 | input | CELL18.IMUX.IMUX10.DELAY |
| CFGMGMTWRITEDATA23 | input | CELL18.IMUX.IMUX11.DELAY |
| CFGMGMTWRITEDATA24 | input | CELL19.IMUX.IMUX8.DELAY |
| CFGMGMTWRITEDATA25 | input | CELL19.IMUX.IMUX9.DELAY |
| CFGMGMTWRITEDATA26 | input | CELL19.IMUX.IMUX10.DELAY |
| CFGMGMTWRITEDATA27 | input | CELL19.IMUX.IMUX11.DELAY |
| CFGMGMTWRITEDATA28 | input | CELL20.IMUX.IMUX8.DELAY |
| CFGMGMTWRITEDATA29 | input | CELL20.IMUX.IMUX9.DELAY |
| CFGMGMTWRITEDATA3 | input | CELL13.IMUX.IMUX17.DELAY |
| CFGMGMTWRITEDATA30 | input | CELL20.IMUX.IMUX10.DELAY |
| CFGMGMTWRITEDATA31 | input | CELL20.IMUX.IMUX11.DELAY |
| CFGMGMTWRITEDATA4 | input | CELL13.IMUX.IMUX18.DELAY |
| CFGMGMTWRITEDATA5 | input | CELL13.IMUX.IMUX19.DELAY |
| CFGMGMTWRITEDATA6 | input | CELL14.IMUX.IMUX16.DELAY |
| CFGMGMTWRITEDATA7 | input | CELL14.IMUX.IMUX17.DELAY |
| CFGMGMTWRITEDATA8 | input | CELL14.IMUX.IMUX18.DELAY |
| CFGMGMTWRITEDATA9 | input | CELL14.IMUX.IMUX19.DELAY |
| CFGMSGRECEIVED | output | CELL30.OUT23.TMIN |
| CFGMSGRECEIVEDDATA0 | output | CELL31.OUT13.TMIN |
| CFGMSGRECEIVEDDATA1 | output | CELL31.OUT15.TMIN |
| CFGMSGRECEIVEDDATA2 | output | CELL32.OUT21.TMIN |
| CFGMSGRECEIVEDDATA3 | output | CELL32.OUT23.TMIN |
| CFGMSGRECEIVEDDATA4 | output | CELL33.OUT17.TMIN |
| CFGMSGRECEIVEDDATA5 | output | CELL33.OUT21.TMIN |
| CFGMSGRECEIVEDDATA6 | output | CELL34.OUT23.TMIN |
| CFGMSGRECEIVEDDATA7 | output | CELL35.OUT16.TMIN |
| CFGMSGRECEIVEDTYPE0 | output | CELL35.OUT17.TMIN |
| CFGMSGRECEIVEDTYPE1 | output | CELL35.OUT18.TMIN |
| CFGMSGRECEIVEDTYPE2 | output | CELL35.OUT19.TMIN |
| CFGMSGRECEIVEDTYPE3 | output | CELL36.OUT16.TMIN |
| CFGMSGRECEIVEDTYPE4 | output | CELL36.OUT17.TMIN |
| CFGMSGTRANSMIT | input | CELL22.IMUX.IMUX14.DELAY |
| CFGMSGTRANSMITDATA0 | input | CELL23.IMUX.IMUX14.DELAY |
| CFGMSGTRANSMITDATA1 | input | CELL23.IMUX.IMUX15.DELAY |
| CFGMSGTRANSMITDATA10 | input | CELL26.IMUX.IMUX12.DELAY |
| CFGMSGTRANSMITDATA11 | input | CELL26.IMUX.IMUX13.DELAY |
| CFGMSGTRANSMITDATA12 | input | CELL26.IMUX.IMUX14.DELAY |
| CFGMSGTRANSMITDATA13 | input | CELL26.IMUX.IMUX15.DELAY |
| CFGMSGTRANSMITDATA14 | input | CELL27.IMUX.IMUX12.DELAY |
| CFGMSGTRANSMITDATA15 | input | CELL27.IMUX.IMUX13.DELAY |
| CFGMSGTRANSMITDATA16 | input | CELL27.IMUX.IMUX14.DELAY |
| CFGMSGTRANSMITDATA17 | input | CELL27.IMUX.IMUX15.DELAY |
| CFGMSGTRANSMITDATA18 | input | CELL28.IMUX.IMUX12.DELAY |
| CFGMSGTRANSMITDATA19 | input | CELL28.IMUX.IMUX13.DELAY |
| CFGMSGTRANSMITDATA2 | input | CELL24.IMUX.IMUX12.DELAY |
| CFGMSGTRANSMITDATA20 | input | CELL28.IMUX.IMUX14.DELAY |
| CFGMSGTRANSMITDATA21 | input | CELL28.IMUX.IMUX15.DELAY |
| CFGMSGTRANSMITDATA22 | input | CELL29.IMUX.IMUX12.DELAY |
| CFGMSGTRANSMITDATA23 | input | CELL29.IMUX.IMUX13.DELAY |
| CFGMSGTRANSMITDATA24 | input | CELL29.IMUX.IMUX14.DELAY |
| CFGMSGTRANSMITDATA25 | input | CELL29.IMUX.IMUX15.DELAY |
| CFGMSGTRANSMITDATA26 | input | CELL30.IMUX.IMUX12.DELAY |
| CFGMSGTRANSMITDATA27 | input | CELL30.IMUX.IMUX13.DELAY |
| CFGMSGTRANSMITDATA28 | input | CELL30.IMUX.IMUX14.DELAY |
| CFGMSGTRANSMITDATA29 | input | CELL30.IMUX.IMUX15.DELAY |
| CFGMSGTRANSMITDATA3 | input | CELL24.IMUX.IMUX13.DELAY |
| CFGMSGTRANSMITDATA30 | input | CELL31.IMUX.IMUX12.DELAY |
| CFGMSGTRANSMITDATA31 | input | CELL31.IMUX.IMUX13.DELAY |
| CFGMSGTRANSMITDATA4 | input | CELL24.IMUX.IMUX14.DELAY |
| CFGMSGTRANSMITDATA5 | input | CELL24.IMUX.IMUX15.DELAY |
| CFGMSGTRANSMITDATA6 | input | CELL25.IMUX.IMUX12.DELAY |
| CFGMSGTRANSMITDATA7 | input | CELL25.IMUX.IMUX13.DELAY |
| CFGMSGTRANSMITDATA8 | input | CELL25.IMUX.IMUX14.DELAY |
| CFGMSGTRANSMITDATA9 | input | CELL25.IMUX.IMUX15.DELAY |
| CFGMSGTRANSMITDONE | output | CELL36.OUT18.TMIN |
| CFGMSGTRANSMITTYPE0 | input | CELL22.IMUX.IMUX15.DELAY |
| CFGMSGTRANSMITTYPE1 | input | CELL23.IMUX.IMUX12.DELAY |
| CFGMSGTRANSMITTYPE2 | input | CELL23.IMUX.IMUX13.DELAY |
| CFGNEGOTIATEDWIDTH0 | output | CELL38.OUT9.TMIN |
| CFGNEGOTIATEDWIDTH1 | output | CELL38.OUT10.TMIN |
| CFGNEGOTIATEDWIDTH2 | output | CELL38.OUT11.TMIN |
| CFGNEGOTIATEDWIDTH3 | output | CELL39.OUT8.TMIN |
| CFGOBFFENABLE0 | output | CELL13.OUT17.TMIN |
| CFGOBFFENABLE1 | output | CELL13.OUT18.TMIN |
| CFGPERFUNCSTATUSCONTROL0 | input | CELL50.IMUX.IMUX27.DELAY |
| CFGPERFUNCSTATUSCONTROL1 | input | CELL51.IMUX.IMUX24.DELAY |
| CFGPERFUNCSTATUSCONTROL2 | input | CELL51.IMUX.IMUX25.DELAY |
| CFGPERFUNCSTATUSDATA0 | output | CELL74.OUT19.TMIN |
| CFGPERFUNCSTATUSDATA1 | output | CELL75.OUT16.TMIN |
| CFGPERFUNCSTATUSDATA10 | output | CELL77.OUT21.TMIN |
| CFGPERFUNCSTATUSDATA11 | output | CELL77.OUT22.TMIN |
| CFGPERFUNCSTATUSDATA12 | output | CELL77.OUT23.TMIN |
| CFGPERFUNCSTATUSDATA13 | output | CELL78.OUT20.TMIN |
| CFGPERFUNCSTATUSDATA14 | output | CELL78.OUT21.TMIN |
| CFGPERFUNCSTATUSDATA15 | output | CELL78.OUT22.TMIN |
| CFGPERFUNCSTATUSDATA2 | output | CELL75.OUT17.TMIN |
| CFGPERFUNCSTATUSDATA3 | output | CELL75.OUT18.TMIN |
| CFGPERFUNCSTATUSDATA4 | output | CELL75.OUT19.TMIN |
| CFGPERFUNCSTATUSDATA5 | output | CELL76.OUT20.TMIN |
| CFGPERFUNCSTATUSDATA6 | output | CELL76.OUT21.TMIN |
| CFGPERFUNCSTATUSDATA7 | output | CELL76.OUT22.TMIN |
| CFGPERFUNCSTATUSDATA8 | output | CELL76.OUT23.TMIN |
| CFGPERFUNCSTATUSDATA9 | output | CELL77.OUT20.TMIN |
| CFGPERFUNCTIONNUMBER0 | input | CELL62.IMUX.IMUX23.DELAY |
| CFGPERFUNCTIONNUMBER1 | input | CELL63.IMUX.IMUX16.DELAY |
| CFGPERFUNCTIONNUMBER2 | input | CELL63.IMUX.IMUX17.DELAY |
| CFGPERFUNCTIONOUTPUTREQUEST | input | CELL63.IMUX.IMUX18.DELAY |
| CFGPERFUNCTIONUPDATEDONE | output | CELL83.OUT20.TMIN |
| CFGPHYLINKDOWN | output | CELL37.OUT10.TMIN |
| CFGPHYLINKSTATUS0 | output | CELL37.OUT11.TMIN |
| CFGPHYLINKSTATUS1 | output | CELL38.OUT8.TMIN |
| CFGPLSTATUSCHANGE | output | CELL13.OUT19.TMIN |
| CFGPOWERSTATECHANGEACK | input | CELL77.IMUX.IMUX22.DELAY |
| CFGPOWERSTATECHANGEINTERRUPT | output | CELL84.OUT12.TMIN |
| CFGRCBSTATUS0 | output | CELL12.OUT17.TMIN |
| CFGRCBSTATUS1 | output | CELL12.OUT18.TMIN |
| CFGREQPMTRANSITIONL23READY | input | CELL98.IMUX.IMUX21.DELAY |
| CFGREVID0 | input | CELL89.IMUX.IMUX16.DELAY |
| CFGREVID1 | input | CELL89.IMUX.IMUX17.DELAY |
| CFGREVID2 | input | CELL89.IMUX.IMUX18.DELAY |
| CFGREVID3 | input | CELL89.IMUX.IMUX19.DELAY |
| CFGREVID4 | input | CELL88.IMUX.IMUX16.DELAY |
| CFGREVID5 | input | CELL88.IMUX.IMUX17.DELAY |
| CFGREVID6 | input | CELL88.IMUX.IMUX18.DELAY |
| CFGREVID7 | input | CELL88.IMUX.IMUX19.DELAY |
| CFGSUBSYSID0 | input | CELL87.IMUX.IMUX16.DELAY |
| CFGSUBSYSID1 | input | CELL87.IMUX.IMUX17.DELAY |
| CFGSUBSYSID10 | input | CELL78.IMUX.IMUX19.DELAY |
| CFGSUBSYSID11 | input | CELL77.IMUX.IMUX16.DELAY |
| CFGSUBSYSID12 | input | CELL77.IMUX.IMUX17.DELAY |
| CFGSUBSYSID13 | input | CELL77.IMUX.IMUX18.DELAY |
| CFGSUBSYSID14 | input | CELL77.IMUX.IMUX19.DELAY |
| CFGSUBSYSID15 | input | CELL76.IMUX.IMUX16.DELAY |
| CFGSUBSYSID2 | input | CELL87.IMUX.IMUX18.DELAY |
| CFGSUBSYSID3 | input | CELL87.IMUX.IMUX19.DELAY |
| CFGSUBSYSID4 | input | CELL86.IMUX.IMUX17.DELAY |
| CFGSUBSYSID5 | input | CELL86.IMUX.IMUX18.DELAY |
| CFGSUBSYSID6 | input | CELL86.IMUX.IMUX19.DELAY |
| CFGSUBSYSID7 | input | CELL78.IMUX.IMUX16.DELAY |
| CFGSUBSYSID8 | input | CELL78.IMUX.IMUX17.DELAY |
| CFGSUBSYSID9 | input | CELL78.IMUX.IMUX18.DELAY |
| CFGSUBSYSVENDID0 | input | CELL76.IMUX.IMUX17.DELAY |
| CFGSUBSYSVENDID1 | input | CELL76.IMUX.IMUX18.DELAY |
| CFGSUBSYSVENDID10 | input | CELL74.IMUX.IMUX19.DELAY |
| CFGSUBSYSVENDID11 | input | CELL73.IMUX.IMUX16.DELAY |
| CFGSUBSYSVENDID12 | input | CELL73.IMUX.IMUX17.DELAY |
| CFGSUBSYSVENDID13 | input | CELL73.IMUX.IMUX18.DELAY |
| CFGSUBSYSVENDID14 | input | CELL73.IMUX.IMUX19.DELAY |
| CFGSUBSYSVENDID15 | input | CELL72.IMUX.IMUX17.DELAY |
| CFGSUBSYSVENDID2 | input | CELL76.IMUX.IMUX19.DELAY |
| CFGSUBSYSVENDID3 | input | CELL75.IMUX.IMUX16.DELAY |
| CFGSUBSYSVENDID4 | input | CELL75.IMUX.IMUX17.DELAY |
| CFGSUBSYSVENDID5 | input | CELL75.IMUX.IMUX18.DELAY |
| CFGSUBSYSVENDID6 | input | CELL75.IMUX.IMUX19.DELAY |
| CFGSUBSYSVENDID7 | input | CELL74.IMUX.IMUX16.DELAY |
| CFGSUBSYSVENDID8 | input | CELL74.IMUX.IMUX17.DELAY |
| CFGSUBSYSVENDID9 | input | CELL74.IMUX.IMUX18.DELAY |
| CFGTPHFUNCTIONNUM0 | output | CELL92.OUT22.TMIN |
| CFGTPHFUNCTIONNUM1 | output | CELL92.OUT23.TMIN |
| CFGTPHFUNCTIONNUM2 | output | CELL93.OUT22.TMIN |
| CFGTPHREQUESTERENABLE0 | output | CELL14.OUT16.TMIN |
| CFGTPHREQUESTERENABLE1 | output | CELL14.OUT17.TMIN |
| CFGTPHSTMODE0 | output | CELL14.OUT18.TMIN |
| CFGTPHSTMODE1 | output | CELL14.OUT19.TMIN |
| CFGTPHSTMODE2 | output | CELL15.OUT23.TMIN |
| CFGTPHSTMODE3 | output | CELL16.OUT13.TMIN |
| CFGTPHSTMODE4 | output | CELL16.OUT15.TMIN |
| CFGTPHSTMODE5 | output | CELL17.OUT21.TMIN |
| CFGTPHSTTADDRESS0 | output | CELL91.OUT17.TMIN |
| CFGTPHSTTADDRESS1 | output | CELL91.OUT18.TMIN |
| CFGTPHSTTADDRESS2 | output | CELL91.OUT19.TMIN |
| CFGTPHSTTADDRESS3 | output | CELL92.OUT20.TMIN |
| CFGTPHSTTADDRESS4 | output | CELL92.OUT21.TMIN |
| CFGTPHSTTREADDATA0 | input | CELL58.IMUX.IMUX14.DELAY |
| CFGTPHSTTREADDATA1 | input | CELL59.IMUX.IMUX9.DELAY |
| CFGTPHSTTREADDATA10 | input | CELL61.IMUX.IMUX21.DELAY |
| CFGTPHSTTREADDATA11 | input | CELL61.IMUX.IMUX22.DELAY |
| CFGTPHSTTREADDATA12 | input | CELL61.IMUX.IMUX23.DELAY |
| CFGTPHSTTREADDATA13 | input | CELL62.IMUX.IMUX24.DELAY |
| CFGTPHSTTREADDATA14 | input | CELL62.IMUX.IMUX25.DELAY |
| CFGTPHSTTREADDATA15 | input | CELL62.IMUX.IMUX26.DELAY |
| CFGTPHSTTREADDATA16 | input | CELL62.IMUX.IMUX27.DELAY |
| CFGTPHSTTREADDATA17 | input | CELL63.IMUX.IMUX24.DELAY |
| CFGTPHSTTREADDATA18 | input | CELL63.IMUX.IMUX25.DELAY |
| CFGTPHSTTREADDATA19 | input | CELL63.IMUX.IMUX26.DELAY |
| CFGTPHSTTREADDATA2 | input | CELL59.IMUX.IMUX10.DELAY |
| CFGTPHSTTREADDATA20 | input | CELL63.IMUX.IMUX27.DELAY |
| CFGTPHSTTREADDATA21 | input | CELL64.IMUX.IMUX20.DELAY |
| CFGTPHSTTREADDATA22 | input | CELL64.IMUX.IMUX21.DELAY |
| CFGTPHSTTREADDATA23 | input | CELL64.IMUX.IMUX22.DELAY |
| CFGTPHSTTREADDATA24 | input | CELL64.IMUX.IMUX23.DELAY |
| CFGTPHSTTREADDATA25 | input | CELL65.IMUX.IMUX12.DELAY |
| CFGTPHSTTREADDATA26 | input | CELL65.IMUX.IMUX13.DELAY |
| CFGTPHSTTREADDATA27 | input | CELL65.IMUX.IMUX14.DELAY |
| CFGTPHSTTREADDATA28 | input | CELL65.IMUX.IMUX15.DELAY |
| CFGTPHSTTREADDATA29 | input | CELL66.IMUX.IMUX12.DELAY |
| CFGTPHSTTREADDATA3 | input | CELL59.IMUX.IMUX11.DELAY |
| CFGTPHSTTREADDATA30 | input | CELL66.IMUX.IMUX13.DELAY |
| CFGTPHSTTREADDATA31 | input | CELL66.IMUX.IMUX14.DELAY |
| CFGTPHSTTREADDATA4 | input | CELL59.IMUX.IMUX12.DELAY |
| CFGTPHSTTREADDATA5 | input | CELL60.IMUX.IMUX13.DELAY |
| CFGTPHSTTREADDATA6 | input | CELL60.IMUX.IMUX14.DELAY |
| CFGTPHSTTREADDATA7 | input | CELL60.IMUX.IMUX15.DELAY |
| CFGTPHSTTREADDATA8 | input | CELL60.IMUX.IMUX17.DELAY |
| CFGTPHSTTREADDATA9 | input | CELL61.IMUX.IMUX20.DELAY |
| CFGTPHSTTREADDATAVALID | input | CELL66.IMUX.IMUX15.DELAY |
| CFGTPHSTTREADENABLE | output | CELL87.OUT23.TMIN |
| CFGTPHSTTWRITEBYTEVALID0 | output | CELL86.OUT23.TMIN |
| CFGTPHSTTWRITEBYTEVALID1 | output | CELL87.OUT20.TMIN |
| CFGTPHSTTWRITEBYTEVALID2 | output | CELL87.OUT21.TMIN |
| CFGTPHSTTWRITEBYTEVALID3 | output | CELL87.OUT22.TMIN |
| CFGTPHSTTWRITEDATA0 | output | CELL93.OUT23.TMIN |
| CFGTPHSTTWRITEDATA1 | output | CELL94.OUT12.TMIN |
| CFGTPHSTTWRITEDATA10 | output | CELL96.OUT9.TMIN |
| CFGTPHSTTWRITEDATA11 | output | CELL96.OUT10.TMIN |
| CFGTPHSTTWRITEDATA12 | output | CELL96.OUT11.TMIN |
| CFGTPHSTTWRITEDATA13 | output | CELL97.OUT8.TMIN |
| CFGTPHSTTWRITEDATA14 | output | CELL97.OUT9.TMIN |
| CFGTPHSTTWRITEDATA15 | output | CELL97.OUT10.TMIN |
| CFGTPHSTTWRITEDATA16 | output | CELL97.OUT11.TMIN |
| CFGTPHSTTWRITEDATA17 | output | CELL98.OUT8.TMIN |
| CFGTPHSTTWRITEDATA18 | output | CELL98.OUT9.TMIN |
| CFGTPHSTTWRITEDATA19 | output | CELL98.OUT10.TMIN |
| CFGTPHSTTWRITEDATA2 | output | CELL94.OUT14.TMIN |
| CFGTPHSTTWRITEDATA20 | output | CELL98.OUT11.TMIN |
| CFGTPHSTTWRITEDATA21 | output | CELL99.OUT8.TMIN |
| CFGTPHSTTWRITEDATA22 | output | CELL99.OUT9.TMIN |
| CFGTPHSTTWRITEDATA23 | output | CELL99.OUT10.TMIN |
| CFGTPHSTTWRITEDATA24 | output | CELL99.OUT11.TMIN |
| CFGTPHSTTWRITEDATA25 | output | CELL84.OUT21.TMIN |
| CFGTPHSTTWRITEDATA26 | output | CELL84.OUT22.TMIN |
| CFGTPHSTTWRITEDATA27 | output | CELL84.OUT23.TMIN |
| CFGTPHSTTWRITEDATA28 | output | CELL85.OUT20.TMIN |
| CFGTPHSTTWRITEDATA29 | output | CELL85.OUT21.TMIN |
| CFGTPHSTTWRITEDATA3 | output | CELL94.OUT16.TMIN |
| CFGTPHSTTWRITEDATA30 | output | CELL85.OUT22.TMIN |
| CFGTPHSTTWRITEDATA31 | output | CELL85.OUT23.TMIN |
| CFGTPHSTTWRITEDATA4 | output | CELL94.OUT17.TMIN |
| CFGTPHSTTWRITEDATA5 | output | CELL95.OUT8.TMIN |
| CFGTPHSTTWRITEDATA6 | output | CELL95.OUT9.TMIN |
| CFGTPHSTTWRITEDATA7 | output | CELL95.OUT10.TMIN |
| CFGTPHSTTWRITEDATA8 | output | CELL95.OUT11.TMIN |
| CFGTPHSTTWRITEDATA9 | output | CELL96.OUT8.TMIN |
| CFGTPHSTTWRITEENABLE | output | CELL86.OUT22.TMIN |
| CFGVENDID0 | input | CELL98.IMUX.IMUX12.DELAY |
| CFGVENDID1 | input | CELL98.IMUX.IMUX13.DELAY |
| CFGVENDID10 | input | CELL98.IMUX.IMUX17.DELAY |
| CFGVENDID11 | input | CELL98.IMUX.IMUX18.DELAY |
| CFGVENDID12 | input | CELL98.IMUX.IMUX19.DELAY |
| CFGVENDID13 | input | CELL97.IMUX.IMUX17.DELAY |
| CFGVENDID14 | input | CELL97.IMUX.IMUX18.DELAY |
| CFGVENDID15 | input | CELL97.IMUX.IMUX19.DELAY |
| CFGVENDID2 | input | CELL98.IMUX.IMUX14.DELAY |
| CFGVENDID3 | input | CELL98.IMUX.IMUX15.DELAY |
| CFGVENDID4 | input | CELL99.IMUX.IMUX15.DELAY |
| CFGVENDID5 | input | CELL99.IMUX.IMUX16.DELAY |
| CFGVENDID6 | input | CELL99.IMUX.IMUX17.DELAY |
| CFGVENDID7 | input | CELL99.IMUX.IMUX18.DELAY |
| CFGVENDID8 | input | CELL99.IMUX.IMUX19.DELAY |
| CFGVENDID9 | input | CELL98.IMUX.IMUX16.DELAY |
| CFGVFFLRDONE0 | input | CELL87.IMUX.IMUX23.DELAY |
| CFGVFFLRDONE1 | input | CELL88.IMUX.IMUX20.DELAY |
| CFGVFFLRDONE2 | input | CELL88.IMUX.IMUX21.DELAY |
| CFGVFFLRDONE3 | input | CELL88.IMUX.IMUX22.DELAY |
| CFGVFFLRDONE4 | input | CELL88.IMUX.IMUX23.DELAY |
| CFGVFFLRDONE5 | input | CELL98.IMUX.IMUX20.DELAY |
| CFGVFFLRINPROCESS0 | output | CELL84.OUT16.TMIN |
| CFGVFFLRINPROCESS1 | output | CELL85.OUT12.TMIN |
| CFGVFFLRINPROCESS2 | output | CELL85.OUT13.TMIN |
| CFGVFFLRINPROCESS3 | output | CELL85.OUT14.TMIN |
| CFGVFFLRINPROCESS4 | output | CELL85.OUT15.TMIN |
| CFGVFFLRINPROCESS5 | output | CELL86.OUT17.TMIN |
| CFGVFPOWERSTATE0 | output | CELL15.OUT20.TMIN |
| CFGVFPOWERSTATE1 | output | CELL15.OUT21.TMIN |
| CFGVFPOWERSTATE10 | output | CELL12.OUT12.TMIN |
| CFGVFPOWERSTATE11 | output | CELL12.OUT13.TMIN |
| CFGVFPOWERSTATE12 | output | CELL12.OUT14.TMIN |
| CFGVFPOWERSTATE13 | output | CELL12.OUT15.TMIN |
| CFGVFPOWERSTATE14 | output | CELL11.OUT12.TMIN |
| CFGVFPOWERSTATE15 | output | CELL11.OUT13.TMIN |
| CFGVFPOWERSTATE16 | output | CELL11.OUT14.TMIN |
| CFGVFPOWERSTATE17 | output | CELL11.OUT15.TMIN |
| CFGVFPOWERSTATE2 | output | CELL14.OUT12.TMIN |
| CFGVFPOWERSTATE3 | output | CELL14.OUT13.TMIN |
| CFGVFPOWERSTATE4 | output | CELL14.OUT14.TMIN |
| CFGVFPOWERSTATE5 | output | CELL14.OUT15.TMIN |
| CFGVFPOWERSTATE6 | output | CELL13.OUT12.TMIN |
| CFGVFPOWERSTATE7 | output | CELL13.OUT13.TMIN |
| CFGVFPOWERSTATE8 | output | CELL13.OUT14.TMIN |
| CFGVFPOWERSTATE9 | output | CELL13.OUT15.TMIN |
| CFGVFSTATUS0 | output | CELL37.OUT14.TMIN |
| CFGVFSTATUS1 | output | CELL37.OUT15.TMIN |
| CFGVFSTATUS10 | output | CELL34.OUT20.TMIN |
| CFGVFSTATUS11 | output | CELL34.OUT21.TMIN |
| CFGVFSTATUS2 | output | CELL36.OUT12.TMIN |
| CFGVFSTATUS3 | output | CELL36.OUT13.TMIN |
| CFGVFSTATUS4 | output | CELL36.OUT14.TMIN |
| CFGVFSTATUS5 | output | CELL36.OUT15.TMIN |
| CFGVFSTATUS6 | output | CELL35.OUT12.TMIN |
| CFGVFSTATUS7 | output | CELL35.OUT13.TMIN |
| CFGVFSTATUS8 | output | CELL35.OUT14.TMIN |
| CFGVFSTATUS9 | output | CELL35.OUT15.TMIN |
| CFGVFTPHREQUESTERENABLE0 | output | CELL17.OUT23.TMIN |
| CFGVFTPHREQUESTERENABLE1 | output | CELL18.OUT17.TMIN |
| CFGVFTPHREQUESTERENABLE2 | output | CELL18.OUT21.TMIN |
| CFGVFTPHREQUESTERENABLE3 | output | CELL19.OUT23.TMIN |
| CFGVFTPHREQUESTERENABLE4 | output | CELL20.OUT23.TMIN |
| CFGVFTPHREQUESTERENABLE5 | output | CELL21.OUT13.TMIN |
| CFGVFTPHSTMODE0 | output | CELL21.OUT15.TMIN |
| CFGVFTPHSTMODE1 | output | CELL22.OUT21.TMIN |
| CFGVFTPHSTMODE10 | output | CELL26.OUT15.TMIN |
| CFGVFTPHSTMODE11 | output | CELL27.OUT21.TMIN |
| CFGVFTPHSTMODE12 | output | CELL27.OUT23.TMIN |
| CFGVFTPHSTMODE13 | output | CELL28.OUT17.TMIN |
| CFGVFTPHSTMODE14 | output | CELL28.OUT21.TMIN |
| CFGVFTPHSTMODE15 | output | CELL29.OUT22.TMIN |
| CFGVFTPHSTMODE16 | output | CELL29.OUT23.TMIN |
| CFGVFTPHSTMODE17 | output | CELL30.OUT22.TMIN |
| CFGVFTPHSTMODE2 | output | CELL22.OUT23.TMIN |
| CFGVFTPHSTMODE3 | output | CELL23.OUT17.TMIN |
| CFGVFTPHSTMODE4 | output | CELL23.OUT21.TMIN |
| CFGVFTPHSTMODE5 | output | CELL24.OUT22.TMIN |
| CFGVFTPHSTMODE6 | output | CELL24.OUT23.TMIN |
| CFGVFTPHSTMODE7 | output | CELL25.OUT22.TMIN |
| CFGVFTPHSTMODE8 | output | CELL25.OUT23.TMIN |
| CFGVFTPHSTMODE9 | output | CELL26.OUT13.TMIN |
| CORECLK | input | CELL25.IMUX.CLK1 |
| CORECLKMICOMPLETIONRAML | input | CELL18.IMUX.CLK0 |
| CORECLKMICOMPLETIONRAMU | input | CELL30.IMUX.CLK0 |
| CORECLKMIREPLAYRAM | input | CELL45.IMUX.CLK0 |
| CORECLKMIREQUESTRAM | input | CELL5.IMUX.CLK0 |
| DBGDATAOUT0 | output | CELL88.OUT20.TMIN |
| DBGDATAOUT1 | output | CELL88.OUT21.TMIN |
| DBGDATAOUT10 | output | CELL94.OUT20.TMIN |
| DBGDATAOUT11 | output | CELL94.OUT21.TMIN |
| DBGDATAOUT12 | output | CELL95.OUT12.TMIN |
| DBGDATAOUT13 | output | CELL95.OUT13.TMIN |
| DBGDATAOUT14 | output | CELL95.OUT14.TMIN |
| DBGDATAOUT15 | output | CELL95.OUT15.TMIN |
| DBGDATAOUT2 | output | CELL88.OUT22.TMIN |
| DBGDATAOUT3 | output | CELL88.OUT23.TMIN |
| DBGDATAOUT4 | output | CELL89.OUT20.TMIN |
| DBGDATAOUT5 | output | CELL89.OUT21.TMIN |
| DBGDATAOUT6 | output | CELL89.OUT22.TMIN |
| DBGDATAOUT7 | output | CELL89.OUT23.TMIN |
| DBGDATAOUT8 | output | CELL94.OUT18.TMIN |
| DBGDATAOUT9 | output | CELL94.OUT19.TMIN |
| DRPADDR0 | input | CELL67.IMUX.IMUX18.DELAY |
| DRPADDR1 | input | CELL67.IMUX.IMUX19.DELAY |
| DRPADDR10 | input | CELL70.IMUX.IMUX9.DELAY |
| DRPADDR2 | input | CELL68.IMUX.IMUX16.DELAY |
| DRPADDR3 | input | CELL68.IMUX.IMUX17.DELAY |
| DRPADDR4 | input | CELL68.IMUX.IMUX18.DELAY |
| DRPADDR5 | input | CELL68.IMUX.IMUX19.DELAY |
| DRPADDR6 | input | CELL69.IMUX.IMUX11.DELAY |
| DRPADDR7 | input | CELL69.IMUX.IMUX12.DELAY |
| DRPADDR8 | input | CELL69.IMUX.IMUX13.DELAY |
| DRPADDR9 | input | CELL69.IMUX.IMUX14.DELAY |
| DRPCLK | input | CELL74.IMUX.CLK1 |
| DRPDI0 | input | CELL70.IMUX.IMUX10.DELAY |
| DRPDI1 | input | CELL70.IMUX.IMUX11.DELAY |
| DRPDI10 | input | CELL72.IMUX.IMUX23.DELAY |
| DRPDI11 | input | CELL73.IMUX.IMUX24.DELAY |
| DRPDI12 | input | CELL73.IMUX.IMUX25.DELAY |
| DRPDI13 | input | CELL73.IMUX.IMUX26.DELAY |
| DRPDI14 | input | CELL73.IMUX.IMUX27.DELAY |
| DRPDI15 | input | CELL74.IMUX.IMUX24.DELAY |
| DRPDI2 | input | CELL70.IMUX.IMUX12.DELAY |
| DRPDI3 | input | CELL71.IMUX.IMUX15.DELAY |
| DRPDI4 | input | CELL71.IMUX.IMUX17.DELAY |
| DRPDI5 | input | CELL71.IMUX.IMUX18.DELAY |
| DRPDI6 | input | CELL71.IMUX.IMUX19.DELAY |
| DRPDI7 | input | CELL72.IMUX.IMUX20.DELAY |
| DRPDI8 | input | CELL72.IMUX.IMUX21.DELAY |
| DRPDI9 | input | CELL72.IMUX.IMUX22.DELAY |
| DRPDO0 | output | CELL96.OUT13.TMIN |
| DRPDO1 | output | CELL96.OUT14.TMIN |
| DRPDO10 | output | CELL98.OUT15.TMIN |
| DRPDO11 | output | CELL99.OUT12.TMIN |
| DRPDO12 | output | CELL99.OUT13.TMIN |
| DRPDO13 | output | CELL99.OUT14.TMIN |
| DRPDO14 | output | CELL99.OUT15.TMIN |
| DRPDO15 | output | CELL94.OUT22.TMIN |
| DRPDO2 | output | CELL96.OUT15.TMIN |
| DRPDO3 | output | CELL97.OUT12.TMIN |
| DRPDO4 | output | CELL97.OUT13.TMIN |
| DRPDO5 | output | CELL97.OUT14.TMIN |
| DRPDO6 | output | CELL97.OUT15.TMIN |
| DRPDO7 | output | CELL98.OUT12.TMIN |
| DRPDO8 | output | CELL98.OUT13.TMIN |
| DRPDO9 | output | CELL98.OUT14.TMIN |
| DRPEN | input | CELL67.IMUX.IMUX16.DELAY |
| DRPRDY | output | CELL96.OUT12.TMIN |
| DRPWE | input | CELL67.IMUX.IMUX17.DELAY |
| MAXISCQTDATA0 | output | CELL96.OUT7.TMIN |
| MAXISCQTDATA1 | output | CELL95.OUT4.TMIN |
| MAXISCQTDATA10 | output | CELL93.OUT19.TMIN |
| MAXISCQTDATA100 | output | CELL71.OUT7.TMIN |
| MAXISCQTDATA101 | output | CELL70.OUT4.TMIN |
| MAXISCQTDATA102 | output | CELL70.OUT5.TMIN |
| MAXISCQTDATA103 | output | CELL70.OUT7.TMIN |
| MAXISCQTDATA104 | output | CELL70.OUT8.TMIN |
| MAXISCQTDATA105 | output | CELL69.OUT5.TMIN |
| MAXISCQTDATA106 | output | CELL69.OUT6.TMIN |
| MAXISCQTDATA107 | output | CELL69.OUT7.TMIN |
| MAXISCQTDATA108 | output | CELL69.OUT10.TMIN |
| MAXISCQTDATA109 | output | CELL68.OUT18.TMIN |
| MAXISCQTDATA11 | output | CELL93.OUT20.TMIN |
| MAXISCQTDATA110 | output | CELL68.OUT19.TMIN |
| MAXISCQTDATA111 | output | CELL68.OUT20.TMIN |
| MAXISCQTDATA112 | output | CELL68.OUT21.TMIN |
| MAXISCQTDATA113 | output | CELL67.OUT14.TMIN |
| MAXISCQTDATA114 | output | CELL67.OUT17.TMIN |
| MAXISCQTDATA115 | output | CELL67.OUT18.TMIN |
| MAXISCQTDATA116 | output | CELL67.OUT19.TMIN |
| MAXISCQTDATA117 | output | CELL66.OUT8.TMIN |
| MAXISCQTDATA118 | output | CELL66.OUT10.TMIN |
| MAXISCQTDATA119 | output | CELL66.OUT12.TMIN |
| MAXISCQTDATA12 | output | CELL93.OUT21.TMIN |
| MAXISCQTDATA120 | output | CELL66.OUT14.TMIN |
| MAXISCQTDATA121 | output | CELL65.OUT8.TMIN |
| MAXISCQTDATA122 | output | CELL65.OUT10.TMIN |
| MAXISCQTDATA123 | output | CELL65.OUT12.TMIN |
| MAXISCQTDATA124 | output | CELL65.OUT14.TMIN |
| MAXISCQTDATA125 | output | CELL64.OUT8.TMIN |
| MAXISCQTDATA126 | output | CELL64.OUT10.TMIN |
| MAXISCQTDATA127 | output | CELL64.OUT12.TMIN |
| MAXISCQTDATA128 | output | CELL64.OUT14.TMIN |
| MAXISCQTDATA129 | output | CELL63.OUT8.TMIN |
| MAXISCQTDATA13 | output | CELL92.OUT14.TMIN |
| MAXISCQTDATA130 | output | CELL63.OUT10.TMIN |
| MAXISCQTDATA131 | output | CELL63.OUT12.TMIN |
| MAXISCQTDATA132 | output | CELL63.OUT14.TMIN |
| MAXISCQTDATA133 | output | CELL62.OUT8.TMIN |
| MAXISCQTDATA134 | output | CELL62.OUT10.TMIN |
| MAXISCQTDATA135 | output | CELL62.OUT12.TMIN |
| MAXISCQTDATA136 | output | CELL62.OUT14.TMIN |
| MAXISCQTDATA137 | output | CELL61.OUT8.TMIN |
| MAXISCQTDATA138 | output | CELL61.OUT9.TMIN |
| MAXISCQTDATA139 | output | CELL61.OUT10.TMIN |
| MAXISCQTDATA14 | output | CELL92.OUT17.TMIN |
| MAXISCQTDATA140 | output | CELL61.OUT11.TMIN |
| MAXISCQTDATA141 | output | CELL60.OUT4.TMIN |
| MAXISCQTDATA142 | output | CELL60.OUT5.TMIN |
| MAXISCQTDATA143 | output | CELL60.OUT6.TMIN |
| MAXISCQTDATA144 | output | CELL60.OUT7.TMIN |
| MAXISCQTDATA145 | output | CELL59.OUT4.TMIN |
| MAXISCQTDATA146 | output | CELL59.OUT5.TMIN |
| MAXISCQTDATA147 | output | CELL59.OUT6.TMIN |
| MAXISCQTDATA148 | output | CELL59.OUT7.TMIN |
| MAXISCQTDATA149 | output | CELL58.OUT5.TMIN |
| MAXISCQTDATA15 | output | CELL92.OUT18.TMIN |
| MAXISCQTDATA150 | output | CELL58.OUT6.TMIN |
| MAXISCQTDATA151 | output | CELL58.OUT7.TMIN |
| MAXISCQTDATA152 | output | CELL58.OUT10.TMIN |
| MAXISCQTDATA153 | output | CELL57.OUT18.TMIN |
| MAXISCQTDATA154 | output | CELL57.OUT19.TMIN |
| MAXISCQTDATA155 | output | CELL57.OUT20.TMIN |
| MAXISCQTDATA156 | output | CELL57.OUT21.TMIN |
| MAXISCQTDATA157 | output | CELL56.OUT14.TMIN |
| MAXISCQTDATA158 | output | CELL56.OUT17.TMIN |
| MAXISCQTDATA159 | output | CELL56.OUT18.TMIN |
| MAXISCQTDATA16 | output | CELL92.OUT19.TMIN |
| MAXISCQTDATA160 | output | CELL56.OUT19.TMIN |
| MAXISCQTDATA161 | output | CELL55.OUT8.TMIN |
| MAXISCQTDATA162 | output | CELL55.OUT10.TMIN |
| MAXISCQTDATA163 | output | CELL55.OUT12.TMIN |
| MAXISCQTDATA164 | output | CELL55.OUT14.TMIN |
| MAXISCQTDATA165 | output | CELL54.OUT8.TMIN |
| MAXISCQTDATA166 | output | CELL54.OUT10.TMIN |
| MAXISCQTDATA167 | output | CELL54.OUT12.TMIN |
| MAXISCQTDATA168 | output | CELL54.OUT14.TMIN |
| MAXISCQTDATA169 | output | CELL53.OUT8.TMIN |
| MAXISCQTDATA17 | output | CELL91.OUT8.TMIN |
| MAXISCQTDATA170 | output | CELL53.OUT10.TMIN |
| MAXISCQTDATA171 | output | CELL53.OUT12.TMIN |
| MAXISCQTDATA172 | output | CELL53.OUT14.TMIN |
| MAXISCQTDATA173 | output | CELL52.OUT8.TMIN |
| MAXISCQTDATA174 | output | CELL52.OUT10.TMIN |
| MAXISCQTDATA175 | output | CELL52.OUT12.TMIN |
| MAXISCQTDATA176 | output | CELL52.OUT14.TMIN |
| MAXISCQTDATA177 | output | CELL51.OUT8.TMIN |
| MAXISCQTDATA178 | output | CELL51.OUT10.TMIN |
| MAXISCQTDATA179 | output | CELL51.OUT12.TMIN |
| MAXISCQTDATA18 | output | CELL91.OUT10.TMIN |
| MAXISCQTDATA180 | output | CELL51.OUT14.TMIN |
| MAXISCQTDATA181 | output | CELL51.OUT16.TMIN |
| MAXISCQTDATA182 | output | CELL51.OUT17.TMIN |
| MAXISCQTDATA183 | output | CELL51.OUT18.TMIN |
| MAXISCQTDATA184 | output | CELL51.OUT19.TMIN |
| MAXISCQTDATA185 | output | CELL52.OUT16.TMIN |
| MAXISCQTDATA186 | output | CELL52.OUT17.TMIN |
| MAXISCQTDATA187 | output | CELL52.OUT18.TMIN |
| MAXISCQTDATA188 | output | CELL52.OUT19.TMIN |
| MAXISCQTDATA189 | output | CELL53.OUT16.TMIN |
| MAXISCQTDATA19 | output | CELL91.OUT12.TMIN |
| MAXISCQTDATA190 | output | CELL53.OUT17.TMIN |
| MAXISCQTDATA191 | output | CELL53.OUT18.TMIN |
| MAXISCQTDATA192 | output | CELL53.OUT19.TMIN |
| MAXISCQTDATA193 | output | CELL54.OUT17.TMIN |
| MAXISCQTDATA194 | output | CELL55.OUT17.TMIN |
| MAXISCQTDATA195 | output | CELL56.OUT20.TMIN |
| MAXISCQTDATA196 | output | CELL56.OUT21.TMIN |
| MAXISCQTDATA197 | output | CELL58.OUT12.TMIN |
| MAXISCQTDATA198 | output | CELL58.OUT14.TMIN |
| MAXISCQTDATA199 | output | CELL58.OUT16.TMIN |
| MAXISCQTDATA2 | output | CELL95.OUT5.TMIN |
| MAXISCQTDATA20 | output | CELL91.OUT14.TMIN |
| MAXISCQTDATA200 | output | CELL58.OUT17.TMIN |
| MAXISCQTDATA201 | output | CELL59.OUT8.TMIN |
| MAXISCQTDATA202 | output | CELL59.OUT9.TMIN |
| MAXISCQTDATA203 | output | CELL59.OUT10.TMIN |
| MAXISCQTDATA204 | output | CELL59.OUT11.TMIN |
| MAXISCQTDATA205 | output | CELL60.OUT8.TMIN |
| MAXISCQTDATA206 | output | CELL60.OUT9.TMIN |
| MAXISCQTDATA207 | output | CELL60.OUT10.TMIN |
| MAXISCQTDATA208 | output | CELL60.OUT11.TMIN |
| MAXISCQTDATA209 | output | CELL61.OUT12.TMIN |
| MAXISCQTDATA21 | output | CELL90.OUT8.TMIN |
| MAXISCQTDATA210 | output | CELL61.OUT13.TMIN |
| MAXISCQTDATA211 | output | CELL61.OUT14.TMIN |
| MAXISCQTDATA212 | output | CELL61.OUT15.TMIN |
| MAXISCQTDATA213 | output | CELL62.OUT16.TMIN |
| MAXISCQTDATA214 | output | CELL62.OUT17.TMIN |
| MAXISCQTDATA215 | output | CELL62.OUT18.TMIN |
| MAXISCQTDATA216 | output | CELL62.OUT19.TMIN |
| MAXISCQTDATA217 | output | CELL63.OUT16.TMIN |
| MAXISCQTDATA218 | output | CELL63.OUT17.TMIN |
| MAXISCQTDATA219 | output | CELL63.OUT18.TMIN |
| MAXISCQTDATA22 | output | CELL90.OUT10.TMIN |
| MAXISCQTDATA220 | output | CELL63.OUT19.TMIN |
| MAXISCQTDATA221 | output | CELL64.OUT16.TMIN |
| MAXISCQTDATA222 | output | CELL64.OUT17.TMIN |
| MAXISCQTDATA223 | output | CELL64.OUT18.TMIN |
| MAXISCQTDATA224 | output | CELL64.OUT19.TMIN |
| MAXISCQTDATA225 | output | CELL65.OUT17.TMIN |
| MAXISCQTDATA226 | output | CELL66.OUT17.TMIN |
| MAXISCQTDATA227 | output | CELL67.OUT20.TMIN |
| MAXISCQTDATA228 | output | CELL67.OUT21.TMIN |
| MAXISCQTDATA229 | output | CELL69.OUT12.TMIN |
| MAXISCQTDATA23 | output | CELL90.OUT12.TMIN |
| MAXISCQTDATA230 | output | CELL69.OUT14.TMIN |
| MAXISCQTDATA231 | output | CELL69.OUT16.TMIN |
| MAXISCQTDATA232 | output | CELL69.OUT17.TMIN |
| MAXISCQTDATA233 | output | CELL70.OUT9.TMIN |
| MAXISCQTDATA234 | output | CELL70.OUT10.TMIN |
| MAXISCQTDATA235 | output | CELL70.OUT11.TMIN |
| MAXISCQTDATA236 | output | CELL70.OUT12.TMIN |
| MAXISCQTDATA237 | output | CELL71.OUT8.TMIN |
| MAXISCQTDATA238 | output | CELL71.OUT9.TMIN |
| MAXISCQTDATA239 | output | CELL71.OUT10.TMIN |
| MAXISCQTDATA24 | output | CELL90.OUT14.TMIN |
| MAXISCQTDATA240 | output | CELL71.OUT11.TMIN |
| MAXISCQTDATA241 | output | CELL72.OUT8.TMIN |
| MAXISCQTDATA242 | output | CELL72.OUT9.TMIN |
| MAXISCQTDATA243 | output | CELL72.OUT10.TMIN |
| MAXISCQTDATA244 | output | CELL72.OUT11.TMIN |
| MAXISCQTDATA245 | output | CELL73.OUT8.TMIN |
| MAXISCQTDATA246 | output | CELL73.OUT9.TMIN |
| MAXISCQTDATA247 | output | CELL73.OUT10.TMIN |
| MAXISCQTDATA248 | output | CELL73.OUT11.TMIN |
| MAXISCQTDATA249 | output | CELL74.OUT8.TMIN |
| MAXISCQTDATA25 | output | CELL89.OUT8.TMIN |
| MAXISCQTDATA250 | output | CELL74.OUT9.TMIN |
| MAXISCQTDATA251 | output | CELL74.OUT10.TMIN |
| MAXISCQTDATA252 | output | CELL74.OUT11.TMIN |
| MAXISCQTDATA253 | output | CELL75.OUT12.TMIN |
| MAXISCQTDATA254 | output | CELL75.OUT13.TMIN |
| MAXISCQTDATA255 | output | CELL75.OUT14.TMIN |
| MAXISCQTDATA26 | output | CELL89.OUT10.TMIN |
| MAXISCQTDATA27 | output | CELL89.OUT12.TMIN |
| MAXISCQTDATA28 | output | CELL89.OUT14.TMIN |
| MAXISCQTDATA29 | output | CELL88.OUT8.TMIN |
| MAXISCQTDATA3 | output | CELL95.OUT6.TMIN |
| MAXISCQTDATA30 | output | CELL88.OUT10.TMIN |
| MAXISCQTDATA31 | output | CELL88.OUT12.TMIN |
| MAXISCQTDATA32 | output | CELL88.OUT14.TMIN |
| MAXISCQTDATA33 | output | CELL87.OUT8.TMIN |
| MAXISCQTDATA34 | output | CELL87.OUT10.TMIN |
| MAXISCQTDATA35 | output | CELL87.OUT12.TMIN |
| MAXISCQTDATA36 | output | CELL87.OUT14.TMIN |
| MAXISCQTDATA37 | output | CELL86.OUT8.TMIN |
| MAXISCQTDATA38 | output | CELL86.OUT10.TMIN |
| MAXISCQTDATA39 | output | CELL86.OUT11.TMIN |
| MAXISCQTDATA4 | output | CELL95.OUT7.TMIN |
| MAXISCQTDATA40 | output | CELL86.OUT12.TMIN |
| MAXISCQTDATA41 | output | CELL85.OUT4.TMIN |
| MAXISCQTDATA42 | output | CELL85.OUT5.TMIN |
| MAXISCQTDATA43 | output | CELL85.OUT6.TMIN |
| MAXISCQTDATA44 | output | CELL85.OUT7.TMIN |
| MAXISCQTDATA45 | output | CELL84.OUT4.TMIN |
| MAXISCQTDATA46 | output | CELL84.OUT5.TMIN |
| MAXISCQTDATA47 | output | CELL84.OUT6.TMIN |
| MAXISCQTDATA48 | output | CELL84.OUT7.TMIN |
| MAXISCQTDATA49 | output | CELL83.OUT6.TMIN |
| MAXISCQTDATA5 | output | CELL94.OUT5.TMIN |
| MAXISCQTDATA50 | output | CELL83.OUT7.TMIN |
| MAXISCQTDATA51 | output | CELL83.OUT10.TMIN |
| MAXISCQTDATA52 | output | CELL83.OUT12.TMIN |
| MAXISCQTDATA53 | output | CELL82.OUT18.TMIN |
| MAXISCQTDATA54 | output | CELL82.OUT19.TMIN |
| MAXISCQTDATA55 | output | CELL82.OUT20.TMIN |
| MAXISCQTDATA56 | output | CELL82.OUT21.TMIN |
| MAXISCQTDATA57 | output | CELL81.OUT14.TMIN |
| MAXISCQTDATA58 | output | CELL81.OUT17.TMIN |
| MAXISCQTDATA59 | output | CELL81.OUT18.TMIN |
| MAXISCQTDATA6 | output | CELL94.OUT6.TMIN |
| MAXISCQTDATA60 | output | CELL81.OUT19.TMIN |
| MAXISCQTDATA61 | output | CELL80.OUT8.TMIN |
| MAXISCQTDATA62 | output | CELL80.OUT10.TMIN |
| MAXISCQTDATA63 | output | CELL80.OUT12.TMIN |
| MAXISCQTDATA64 | output | CELL80.OUT14.TMIN |
| MAXISCQTDATA65 | output | CELL79.OUT8.TMIN |
| MAXISCQTDATA66 | output | CELL79.OUT10.TMIN |
| MAXISCQTDATA67 | output | CELL79.OUT12.TMIN |
| MAXISCQTDATA68 | output | CELL79.OUT14.TMIN |
| MAXISCQTDATA69 | output | CELL78.OUT8.TMIN |
| MAXISCQTDATA7 | output | CELL94.OUT7.TMIN |
| MAXISCQTDATA70 | output | CELL78.OUT10.TMIN |
| MAXISCQTDATA71 | output | CELL78.OUT12.TMIN |
| MAXISCQTDATA72 | output | CELL78.OUT14.TMIN |
| MAXISCQTDATA73 | output | CELL77.OUT8.TMIN |
| MAXISCQTDATA74 | output | CELL77.OUT10.TMIN |
| MAXISCQTDATA75 | output | CELL77.OUT12.TMIN |
| MAXISCQTDATA76 | output | CELL77.OUT14.TMIN |
| MAXISCQTDATA77 | output | CELL76.OUT8.TMIN |
| MAXISCQTDATA78 | output | CELL76.OUT10.TMIN |
| MAXISCQTDATA79 | output | CELL76.OUT12.TMIN |
| MAXISCQTDATA8 | output | CELL94.OUT10.TMIN |
| MAXISCQTDATA80 | output | CELL76.OUT14.TMIN |
| MAXISCQTDATA81 | output | CELL75.OUT8.TMIN |
| MAXISCQTDATA82 | output | CELL75.OUT9.TMIN |
| MAXISCQTDATA83 | output | CELL75.OUT10.TMIN |
| MAXISCQTDATA84 | output | CELL75.OUT11.TMIN |
| MAXISCQTDATA85 | output | CELL74.OUT4.TMIN |
| MAXISCQTDATA86 | output | CELL74.OUT5.TMIN |
| MAXISCQTDATA87 | output | CELL74.OUT6.TMIN |
| MAXISCQTDATA88 | output | CELL74.OUT7.TMIN |
| MAXISCQTDATA89 | output | CELL73.OUT4.TMIN |
| MAXISCQTDATA9 | output | CELL93.OUT18.TMIN |
| MAXISCQTDATA90 | output | CELL73.OUT5.TMIN |
| MAXISCQTDATA91 | output | CELL73.OUT6.TMIN |
| MAXISCQTDATA92 | output | CELL73.OUT7.TMIN |
| MAXISCQTDATA93 | output | CELL72.OUT4.TMIN |
| MAXISCQTDATA94 | output | CELL72.OUT5.TMIN |
| MAXISCQTDATA95 | output | CELL72.OUT6.TMIN |
| MAXISCQTDATA96 | output | CELL72.OUT7.TMIN |
| MAXISCQTDATA97 | output | CELL71.OUT4.TMIN |
| MAXISCQTDATA98 | output | CELL71.OUT5.TMIN |
| MAXISCQTDATA99 | output | CELL71.OUT6.TMIN |
| MAXISCQTKEEP0 | output | CELL59.OUT16.TMIN |
| MAXISCQTKEEP1 | output | CELL59.OUT17.TMIN |
| MAXISCQTKEEP2 | output | CELL59.OUT18.TMIN |
| MAXISCQTKEEP3 | output | CELL59.OUT19.TMIN |
| MAXISCQTKEEP4 | output | CELL60.OUT16.TMIN |
| MAXISCQTKEEP5 | output | CELL60.OUT17.TMIN |
| MAXISCQTKEEP6 | output | CELL60.OUT18.TMIN |
| MAXISCQTKEEP7 | output | CELL60.OUT19.TMIN |
| MAXISCQTLAST | output | CELL87.OUT16.TMIN |
| MAXISCQTREADY0 | input | CELL51.IMUX.IMUX21.DELAY |
| MAXISCQTREADY1 | input | CELL51.IMUX.IMUX22.DELAY |
| MAXISCQTREADY10 | input | CELL61.IMUX.IMUX17.DELAY |
| MAXISCQTREADY11 | input | CELL61.IMUX.IMUX18.DELAY |
| MAXISCQTREADY12 | input | CELL61.IMUX.IMUX19.DELAY |
| MAXISCQTREADY13 | input | CELL62.IMUX.IMUX16.DELAY |
| MAXISCQTREADY14 | input | CELL62.IMUX.IMUX17.DELAY |
| MAXISCQTREADY15 | input | CELL62.IMUX.IMUX18.DELAY |
| MAXISCQTREADY16 | input | CELL62.IMUX.IMUX19.DELAY |
| MAXISCQTREADY17 | input | CELL64.IMUX.IMUX12.DELAY |
| MAXISCQTREADY18 | input | CELL64.IMUX.IMUX13.DELAY |
| MAXISCQTREADY19 | input | CELL64.IMUX.IMUX14.DELAY |
| MAXISCQTREADY2 | input | CELL51.IMUX.IMUX23.DELAY |
| MAXISCQTREADY20 | input | CELL64.IMUX.IMUX15.DELAY |
| MAXISCQTREADY21 | input | CELL67.IMUX.IMUX12.DELAY |
| MAXISCQTREADY3 | input | CELL52.IMUX.IMUX20.DELAY |
| MAXISCQTREADY4 | input | CELL52.IMUX.IMUX21.DELAY |
| MAXISCQTREADY5 | input | CELL52.IMUX.IMUX22.DELAY |
| MAXISCQTREADY6 | input | CELL52.IMUX.IMUX23.DELAY |
| MAXISCQTREADY7 | input | CELL53.IMUX.IMUX17.DELAY |
| MAXISCQTREADY8 | input | CELL53.IMUX.IMUX18.DELAY |
| MAXISCQTREADY9 | input | CELL53.IMUX.IMUX19.DELAY |
| MAXISCQTUSER0 | output | CELL51.OUT20.TMIN |
| MAXISCQTUSER1 | output | CELL51.OUT21.TMIN |
| MAXISCQTUSER10 | output | CELL59.OUT12.TMIN |
| MAXISCQTUSER11 | output | CELL59.OUT13.TMIN |
| MAXISCQTUSER12 | output | CELL59.OUT14.TMIN |
| MAXISCQTUSER13 | output | CELL59.OUT15.TMIN |
| MAXISCQTUSER14 | output | CELL60.OUT12.TMIN |
| MAXISCQTUSER15 | output | CELL60.OUT13.TMIN |
| MAXISCQTUSER16 | output | CELL60.OUT14.TMIN |
| MAXISCQTUSER17 | output | CELL60.OUT15.TMIN |
| MAXISCQTUSER18 | output | CELL61.OUT16.TMIN |
| MAXISCQTUSER19 | output | CELL61.OUT17.TMIN |
| MAXISCQTUSER2 | output | CELL52.OUT20.TMIN |
| MAXISCQTUSER20 | output | CELL61.OUT18.TMIN |
| MAXISCQTUSER21 | output | CELL61.OUT19.TMIN |
| MAXISCQTUSER22 | output | CELL62.OUT20.TMIN |
| MAXISCQTUSER23 | output | CELL62.OUT21.TMIN |
| MAXISCQTUSER24 | output | CELL63.OUT20.TMIN |
| MAXISCQTUSER25 | output | CELL63.OUT21.TMIN |
| MAXISCQTUSER26 | output | CELL64.OUT20.TMIN |
| MAXISCQTUSER27 | output | CELL64.OUT21.TMIN |
| MAXISCQTUSER28 | output | CELL69.OUT18.TMIN |
| MAXISCQTUSER29 | output | CELL69.OUT19.TMIN |
| MAXISCQTUSER3 | output | CELL52.OUT21.TMIN |
| MAXISCQTUSER30 | output | CELL69.OUT20.TMIN |
| MAXISCQTUSER31 | output | CELL69.OUT21.TMIN |
| MAXISCQTUSER32 | output | CELL70.OUT13.TMIN |
| MAXISCQTUSER33 | output | CELL70.OUT14.TMIN |
| MAXISCQTUSER34 | output | CELL70.OUT15.TMIN |
| MAXISCQTUSER35 | output | CELL70.OUT17.TMIN |
| MAXISCQTUSER36 | output | CELL71.OUT12.TMIN |
| MAXISCQTUSER37 | output | CELL71.OUT13.TMIN |
| MAXISCQTUSER38 | output | CELL71.OUT14.TMIN |
| MAXISCQTUSER39 | output | CELL71.OUT15.TMIN |
| MAXISCQTUSER4 | output | CELL53.OUT20.TMIN |
| MAXISCQTUSER40 | output | CELL72.OUT12.TMIN |
| MAXISCQTUSER41 | output | CELL72.OUT13.TMIN |
| MAXISCQTUSER42 | output | CELL72.OUT14.TMIN |
| MAXISCQTUSER43 | output | CELL72.OUT15.TMIN |
| MAXISCQTUSER44 | output | CELL73.OUT12.TMIN |
| MAXISCQTUSER45 | output | CELL73.OUT13.TMIN |
| MAXISCQTUSER46 | output | CELL73.OUT14.TMIN |
| MAXISCQTUSER47 | output | CELL73.OUT15.TMIN |
| MAXISCQTUSER48 | output | CELL74.OUT12.TMIN |
| MAXISCQTUSER49 | output | CELL74.OUT13.TMIN |
| MAXISCQTUSER5 | output | CELL53.OUT21.TMIN |
| MAXISCQTUSER50 | output | CELL74.OUT14.TMIN |
| MAXISCQTUSER51 | output | CELL74.OUT15.TMIN |
| MAXISCQTUSER52 | output | CELL75.OUT15.TMIN |
| MAXISCQTUSER53 | output | CELL76.OUT16.TMIN |
| MAXISCQTUSER54 | output | CELL76.OUT17.TMIN |
| MAXISCQTUSER55 | output | CELL76.OUT18.TMIN |
| MAXISCQTUSER56 | output | CELL76.OUT19.TMIN |
| MAXISCQTUSER57 | output | CELL77.OUT16.TMIN |
| MAXISCQTUSER58 | output | CELL77.OUT17.TMIN |
| MAXISCQTUSER59 | output | CELL77.OUT18.TMIN |
| MAXISCQTUSER6 | output | CELL58.OUT18.TMIN |
| MAXISCQTUSER60 | output | CELL77.OUT19.TMIN |
| MAXISCQTUSER61 | output | CELL78.OUT16.TMIN |
| MAXISCQTUSER62 | output | CELL78.OUT17.TMIN |
| MAXISCQTUSER63 | output | CELL78.OUT18.TMIN |
| MAXISCQTUSER64 | output | CELL78.OUT19.TMIN |
| MAXISCQTUSER65 | output | CELL79.OUT17.TMIN |
| MAXISCQTUSER66 | output | CELL80.OUT17.TMIN |
| MAXISCQTUSER67 | output | CELL81.OUT20.TMIN |
| MAXISCQTUSER68 | output | CELL81.OUT21.TMIN |
| MAXISCQTUSER69 | output | CELL83.OUT14.TMIN |
| MAXISCQTUSER7 | output | CELL58.OUT19.TMIN |
| MAXISCQTUSER70 | output | CELL83.OUT16.TMIN |
| MAXISCQTUSER71 | output | CELL83.OUT17.TMIN |
| MAXISCQTUSER72 | output | CELL83.OUT18.TMIN |
| MAXISCQTUSER73 | output | CELL84.OUT8.TMIN |
| MAXISCQTUSER74 | output | CELL84.OUT9.TMIN |
| MAXISCQTUSER75 | output | CELL84.OUT10.TMIN |
| MAXISCQTUSER76 | output | CELL84.OUT11.TMIN |
| MAXISCQTUSER77 | output | CELL85.OUT8.TMIN |
| MAXISCQTUSER78 | output | CELL85.OUT9.TMIN |
| MAXISCQTUSER79 | output | CELL85.OUT10.TMIN |
| MAXISCQTUSER8 | output | CELL58.OUT20.TMIN |
| MAXISCQTUSER80 | output | CELL85.OUT11.TMIN |
| MAXISCQTUSER81 | output | CELL86.OUT13.TMIN |
| MAXISCQTUSER82 | output | CELL86.OUT14.TMIN |
| MAXISCQTUSER83 | output | CELL86.OUT15.TMIN |
| MAXISCQTUSER84 | output | CELL86.OUT16.TMIN |
| MAXISCQTUSER9 | output | CELL58.OUT21.TMIN |
| MAXISCQTVALID | output | CELL59.OUT20.TMIN |
| MAXISRCTDATA0 | output | CELL0.OUT0.TMIN |
| MAXISRCTDATA1 | output | CELL0.OUT8.TMIN |
| MAXISRCTDATA10 | output | CELL4.OUT18.TMIN |
| MAXISRCTDATA100 | output | CELL29.OUT0.TMIN |
| MAXISRCTDATA101 | output | CELL29.OUT1.TMIN |
| MAXISRCTDATA102 | output | CELL29.OUT2.TMIN |
| MAXISRCTDATA103 | output | CELL29.OUT3.TMIN |
| MAXISRCTDATA104 | output | CELL30.OUT0.TMIN |
| MAXISRCTDATA105 | output | CELL30.OUT8.TMIN |
| MAXISRCTDATA106 | output | CELL30.OUT9.TMIN |
| MAXISRCTDATA107 | output | CELL30.OUT10.TMIN |
| MAXISRCTDATA108 | output | CELL31.OUT1.TMIN |
| MAXISRCTDATA109 | output | CELL31.OUT4.TMIN |
| MAXISRCTDATA11 | output | CELL4.OUT19.TMIN |
| MAXISRCTDATA110 | output | CELL31.OUT5.TMIN |
| MAXISRCTDATA111 | output | CELL31.OUT8.TMIN |
| MAXISRCTDATA112 | output | CELL32.OUT3.TMIN |
| MAXISRCTDATA113 | output | CELL32.OUT5.TMIN |
| MAXISRCTDATA114 | output | CELL32.OUT8.TMIN |
| MAXISRCTDATA115 | output | CELL32.OUT9.TMIN |
| MAXISRCTDATA116 | output | CELL33.OUT5.TMIN |
| MAXISRCTDATA117 | output | CELL33.OUT7.TMIN |
| MAXISRCTDATA118 | output | CELL33.OUT9.TMIN |
| MAXISRCTDATA119 | output | CELL33.OUT11.TMIN |
| MAXISRCTDATA12 | output | CELL5.OUT0.TMIN |
| MAXISRCTDATA120 | output | CELL34.OUT0.TMIN |
| MAXISRCTDATA121 | output | CELL34.OUT1.TMIN |
| MAXISRCTDATA122 | output | CELL34.OUT2.TMIN |
| MAXISRCTDATA123 | output | CELL34.OUT3.TMIN |
| MAXISRCTDATA124 | output | CELL35.OUT0.TMIN |
| MAXISRCTDATA125 | output | CELL35.OUT1.TMIN |
| MAXISRCTDATA126 | output | CELL35.OUT2.TMIN |
| MAXISRCTDATA127 | output | CELL35.OUT3.TMIN |
| MAXISRCTDATA128 | output | CELL36.OUT0.TMIN |
| MAXISRCTDATA129 | output | CELL36.OUT1.TMIN |
| MAXISRCTDATA13 | output | CELL5.OUT8.TMIN |
| MAXISRCTDATA130 | output | CELL36.OUT2.TMIN |
| MAXISRCTDATA131 | output | CELL36.OUT3.TMIN |
| MAXISRCTDATA132 | output | CELL37.OUT0.TMIN |
| MAXISRCTDATA133 | output | CELL37.OUT1.TMIN |
| MAXISRCTDATA134 | output | CELL37.OUT2.TMIN |
| MAXISRCTDATA135 | output | CELL37.OUT3.TMIN |
| MAXISRCTDATA136 | output | CELL38.OUT0.TMIN |
| MAXISRCTDATA137 | output | CELL38.OUT1.TMIN |
| MAXISRCTDATA138 | output | CELL38.OUT2.TMIN |
| MAXISRCTDATA139 | output | CELL38.OUT3.TMIN |
| MAXISRCTDATA14 | output | CELL5.OUT9.TMIN |
| MAXISRCTDATA140 | output | CELL39.OUT0.TMIN |
| MAXISRCTDATA141 | output | CELL39.OUT1.TMIN |
| MAXISRCTDATA142 | output | CELL39.OUT2.TMIN |
| MAXISRCTDATA143 | output | CELL39.OUT3.TMIN |
| MAXISRCTDATA144 | output | CELL40.OUT0.TMIN |
| MAXISRCTDATA145 | output | CELL40.OUT8.TMIN |
| MAXISRCTDATA146 | output | CELL40.OUT9.TMIN |
| MAXISRCTDATA147 | output | CELL40.OUT10.TMIN |
| MAXISRCTDATA148 | output | CELL41.OUT6.TMIN |
| MAXISRCTDATA149 | output | CELL41.OUT11.TMIN |
| MAXISRCTDATA15 | output | CELL5.OUT10.TMIN |
| MAXISRCTDATA150 | output | CELL41.OUT14.TMIN |
| MAXISRCTDATA151 | output | CELL41.OUT15.TMIN |
| MAXISRCTDATA152 | output | CELL42.OUT2.TMIN |
| MAXISRCTDATA153 | output | CELL42.OUT4.TMIN |
| MAXISRCTDATA154 | output | CELL42.OUT5.TMIN |
| MAXISRCTDATA155 | output | CELL42.OUT10.TMIN |
| MAXISRCTDATA156 | output | CELL43.OUT0.TMIN |
| MAXISRCTDATA157 | output | CELL43.OUT4.TMIN |
| MAXISRCTDATA158 | output | CELL43.OUT5.TMIN |
| MAXISRCTDATA159 | output | CELL43.OUT7.TMIN |
| MAXISRCTDATA16 | output | CELL7.OUT0.TMIN |
| MAXISRCTDATA160 | output | CELL44.OUT5.TMIN |
| MAXISRCTDATA161 | output | CELL44.OUT9.TMIN |
| MAXISRCTDATA162 | output | CELL44.OUT12.TMIN |
| MAXISRCTDATA163 | output | CELL45.OUT0.TMIN |
| MAXISRCTDATA164 | output | CELL45.OUT1.TMIN |
| MAXISRCTDATA165 | output | CELL45.OUT6.TMIN |
| MAXISRCTDATA166 | output | CELL45.OUT7.TMIN |
| MAXISRCTDATA167 | output | CELL46.OUT2.TMIN |
| MAXISRCTDATA168 | output | CELL46.OUT9.TMIN |
| MAXISRCTDATA169 | output | CELL47.OUT2.TMIN |
| MAXISRCTDATA17 | output | CELL7.OUT1.TMIN |
| MAXISRCTDATA170 | output | CELL47.OUT4.TMIN |
| MAXISRCTDATA171 | output | CELL47.OUT5.TMIN |
| MAXISRCTDATA172 | output | CELL47.OUT7.TMIN |
| MAXISRCTDATA173 | output | CELL48.OUT0.TMIN |
| MAXISRCTDATA174 | output | CELL48.OUT2.TMIN |
| MAXISRCTDATA175 | output | CELL48.OUT4.TMIN |
| MAXISRCTDATA176 | output | CELL48.OUT7.TMIN |
| MAXISRCTDATA177 | output | CELL49.OUT16.TMIN |
| MAXISRCTDATA178 | output | CELL49.OUT17.TMIN |
| MAXISRCTDATA179 | output | CELL49.OUT18.TMIN |
| MAXISRCTDATA18 | output | CELL7.OUT6.TMIN |
| MAXISRCTDATA180 | output | CELL49.OUT19.TMIN |
| MAXISRCTDATA181 | output | CELL48.OUT10.TMIN |
| MAXISRCTDATA182 | output | CELL48.OUT11.TMIN |
| MAXISRCTDATA183 | output | CELL48.OUT12.TMIN |
| MAXISRCTDATA184 | output | CELL48.OUT18.TMIN |
| MAXISRCTDATA185 | output | CELL47.OUT10.TMIN |
| MAXISRCTDATA186 | output | CELL47.OUT11.TMIN |
| MAXISRCTDATA187 | output | CELL47.OUT16.TMIN |
| MAXISRCTDATA188 | output | CELL47.OUT17.TMIN |
| MAXISRCTDATA189 | output | CELL45.OUT12.TMIN |
| MAXISRCTDATA19 | output | CELL7.OUT7.TMIN |
| MAXISRCTDATA190 | output | CELL43.OUT10.TMIN |
| MAXISRCTDATA191 | output | CELL43.OUT11.TMIN |
| MAXISRCTDATA192 | output | CELL43.OUT12.TMIN |
| MAXISRCTDATA193 | output | CELL43.OUT17.TMIN |
| MAXISRCTDATA194 | output | CELL42.OUT11.TMIN |
| MAXISRCTDATA195 | output | CELL42.OUT12.TMIN |
| MAXISRCTDATA196 | output | CELL42.OUT16.TMIN |
| MAXISRCTDATA197 | output | CELL42.OUT17.TMIN |
| MAXISRCTDATA198 | output | CELL41.OUT20.TMIN |
| MAXISRCTDATA199 | output | CELL40.OUT11.TMIN |
| MAXISRCTDATA2 | output | CELL0.OUT9.TMIN |
| MAXISRCTDATA20 | output | CELL9.OUT16.TMIN |
| MAXISRCTDATA200 | output | CELL40.OUT12.TMIN |
| MAXISRCTDATA201 | output | CELL40.OUT13.TMIN |
| MAXISRCTDATA202 | output | CELL40.OUT14.TMIN |
| MAXISRCTDATA203 | output | CELL39.OUT4.TMIN |
| MAXISRCTDATA204 | output | CELL39.OUT5.TMIN |
| MAXISRCTDATA205 | output | CELL39.OUT6.TMIN |
| MAXISRCTDATA206 | output | CELL39.OUT7.TMIN |
| MAXISRCTDATA207 | output | CELL38.OUT4.TMIN |
| MAXISRCTDATA208 | output | CELL38.OUT5.TMIN |
| MAXISRCTDATA209 | output | CELL38.OUT6.TMIN |
| MAXISRCTDATA21 | output | CELL9.OUT17.TMIN |
| MAXISRCTDATA210 | output | CELL38.OUT7.TMIN |
| MAXISRCTDATA211 | output | CELL37.OUT4.TMIN |
| MAXISRCTDATA212 | output | CELL37.OUT5.TMIN |
| MAXISRCTDATA213 | output | CELL37.OUT6.TMIN |
| MAXISRCTDATA214 | output | CELL37.OUT7.TMIN |
| MAXISRCTDATA215 | output | CELL36.OUT4.TMIN |
| MAXISRCTDATA216 | output | CELL36.OUT5.TMIN |
| MAXISRCTDATA217 | output | CELL36.OUT6.TMIN |
| MAXISRCTDATA218 | output | CELL36.OUT7.TMIN |
| MAXISRCTDATA219 | output | CELL35.OUT4.TMIN |
| MAXISRCTDATA22 | output | CELL9.OUT18.TMIN |
| MAXISRCTDATA220 | output | CELL35.OUT5.TMIN |
| MAXISRCTDATA221 | output | CELL35.OUT6.TMIN |
| MAXISRCTDATA222 | output | CELL35.OUT7.TMIN |
| MAXISRCTDATA223 | output | CELL34.OUT4.TMIN |
| MAXISRCTDATA224 | output | CELL34.OUT5.TMIN |
| MAXISRCTDATA225 | output | CELL34.OUT6.TMIN |
| MAXISRCTDATA226 | output | CELL34.OUT7.TMIN |
| MAXISRCTDATA227 | output | CELL33.OUT15.TMIN |
| MAXISRCTDATA228 | output | CELL32.OUT10.TMIN |
| MAXISRCTDATA229 | output | CELL32.OUT11.TMIN |
| MAXISRCTDATA23 | output | CELL9.OUT19.TMIN |
| MAXISRCTDATA230 | output | CELL32.OUT12.TMIN |
| MAXISRCTDATA231 | output | CELL32.OUT13.TMIN |
| MAXISRCTDATA232 | output | CELL31.OUT9.TMIN |
| MAXISRCTDATA233 | output | CELL30.OUT11.TMIN |
| MAXISRCTDATA234 | output | CELL30.OUT12.TMIN |
| MAXISRCTDATA235 | output | CELL30.OUT13.TMIN |
| MAXISRCTDATA236 | output | CELL30.OUT14.TMIN |
| MAXISRCTDATA237 | output | CELL29.OUT4.TMIN |
| MAXISRCTDATA238 | output | CELL29.OUT5.TMIN |
| MAXISRCTDATA239 | output | CELL29.OUT6.TMIN |
| MAXISRCTDATA24 | output | CELL10.OUT0.TMIN |
| MAXISRCTDATA240 | output | CELL29.OUT7.TMIN |
| MAXISRCTDATA241 | output | CELL28.OUT15.TMIN |
| MAXISRCTDATA242 | output | CELL27.OUT10.TMIN |
| MAXISRCTDATA243 | output | CELL27.OUT11.TMIN |
| MAXISRCTDATA244 | output | CELL27.OUT12.TMIN |
| MAXISRCTDATA245 | output | CELL27.OUT13.TMIN |
| MAXISRCTDATA246 | output | CELL26.OUT9.TMIN |
| MAXISRCTDATA247 | output | CELL25.OUT11.TMIN |
| MAXISRCTDATA248 | output | CELL25.OUT12.TMIN |
| MAXISRCTDATA249 | output | CELL25.OUT13.TMIN |
| MAXISRCTDATA25 | output | CELL10.OUT1.TMIN |
| MAXISRCTDATA250 | output | CELL25.OUT14.TMIN |
| MAXISRCTDATA251 | output | CELL24.OUT4.TMIN |
| MAXISRCTDATA252 | output | CELL24.OUT5.TMIN |
| MAXISRCTDATA253 | output | CELL24.OUT6.TMIN |
| MAXISRCTDATA254 | output | CELL24.OUT7.TMIN |
| MAXISRCTDATA255 | output | CELL23.OUT15.TMIN |
| MAXISRCTDATA26 | output | CELL10.OUT2.TMIN |
| MAXISRCTDATA27 | output | CELL10.OUT3.TMIN |
| MAXISRCTDATA28 | output | CELL11.OUT0.TMIN |
| MAXISRCTDATA29 | output | CELL11.OUT1.TMIN |
| MAXISRCTDATA3 | output | CELL0.OUT10.TMIN |
| MAXISRCTDATA30 | output | CELL11.OUT2.TMIN |
| MAXISRCTDATA31 | output | CELL11.OUT3.TMIN |
| MAXISRCTDATA32 | output | CELL12.OUT0.TMIN |
| MAXISRCTDATA33 | output | CELL12.OUT1.TMIN |
| MAXISRCTDATA34 | output | CELL12.OUT2.TMIN |
| MAXISRCTDATA35 | output | CELL12.OUT3.TMIN |
| MAXISRCTDATA36 | output | CELL13.OUT0.TMIN |
| MAXISRCTDATA37 | output | CELL13.OUT1.TMIN |
| MAXISRCTDATA38 | output | CELL13.OUT2.TMIN |
| MAXISRCTDATA39 | output | CELL13.OUT3.TMIN |
| MAXISRCTDATA4 | output | CELL2.OUT6.TMIN |
| MAXISRCTDATA40 | output | CELL14.OUT0.TMIN |
| MAXISRCTDATA41 | output | CELL14.OUT1.TMIN |
| MAXISRCTDATA42 | output | CELL14.OUT2.TMIN |
| MAXISRCTDATA43 | output | CELL14.OUT3.TMIN |
| MAXISRCTDATA44 | output | CELL15.OUT0.TMIN |
| MAXISRCTDATA45 | output | CELL15.OUT8.TMIN |
| MAXISRCTDATA46 | output | CELL15.OUT9.TMIN |
| MAXISRCTDATA47 | output | CELL15.OUT10.TMIN |
| MAXISRCTDATA48 | output | CELL16.OUT1.TMIN |
| MAXISRCTDATA49 | output | CELL16.OUT4.TMIN |
| MAXISRCTDATA5 | output | CELL2.OUT7.TMIN |
| MAXISRCTDATA50 | output | CELL16.OUT5.TMIN |
| MAXISRCTDATA51 | output | CELL16.OUT8.TMIN |
| MAXISRCTDATA52 | output | CELL17.OUT3.TMIN |
| MAXISRCTDATA53 | output | CELL17.OUT5.TMIN |
| MAXISRCTDATA54 | output | CELL17.OUT8.TMIN |
| MAXISRCTDATA55 | output | CELL17.OUT9.TMIN |
| MAXISRCTDATA56 | output | CELL18.OUT5.TMIN |
| MAXISRCTDATA57 | output | CELL18.OUT7.TMIN |
| MAXISRCTDATA58 | output | CELL18.OUT9.TMIN |
| MAXISRCTDATA59 | output | CELL18.OUT11.TMIN |
| MAXISRCTDATA6 | output | CELL2.OUT12.TMIN |
| MAXISRCTDATA60 | output | CELL19.OUT0.TMIN |
| MAXISRCTDATA61 | output | CELL19.OUT1.TMIN |
| MAXISRCTDATA62 | output | CELL19.OUT2.TMIN |
| MAXISRCTDATA63 | output | CELL19.OUT3.TMIN |
| MAXISRCTDATA64 | output | CELL20.OUT0.TMIN |
| MAXISRCTDATA65 | output | CELL20.OUT8.TMIN |
| MAXISRCTDATA66 | output | CELL20.OUT9.TMIN |
| MAXISRCTDATA67 | output | CELL20.OUT10.TMIN |
| MAXISRCTDATA68 | output | CELL21.OUT1.TMIN |
| MAXISRCTDATA69 | output | CELL21.OUT4.TMIN |
| MAXISRCTDATA7 | output | CELL2.OUT16.TMIN |
| MAXISRCTDATA70 | output | CELL21.OUT5.TMIN |
| MAXISRCTDATA71 | output | CELL21.OUT8.TMIN |
| MAXISRCTDATA72 | output | CELL22.OUT3.TMIN |
| MAXISRCTDATA73 | output | CELL22.OUT5.TMIN |
| MAXISRCTDATA74 | output | CELL22.OUT8.TMIN |
| MAXISRCTDATA75 | output | CELL22.OUT9.TMIN |
| MAXISRCTDATA76 | output | CELL23.OUT5.TMIN |
| MAXISRCTDATA77 | output | CELL23.OUT7.TMIN |
| MAXISRCTDATA78 | output | CELL23.OUT9.TMIN |
| MAXISRCTDATA79 | output | CELL23.OUT11.TMIN |
| MAXISRCTDATA8 | output | CELL4.OUT16.TMIN |
| MAXISRCTDATA80 | output | CELL24.OUT0.TMIN |
| MAXISRCTDATA81 | output | CELL24.OUT1.TMIN |
| MAXISRCTDATA82 | output | CELL24.OUT2.TMIN |
| MAXISRCTDATA83 | output | CELL24.OUT3.TMIN |
| MAXISRCTDATA84 | output | CELL25.OUT0.TMIN |
| MAXISRCTDATA85 | output | CELL25.OUT8.TMIN |
| MAXISRCTDATA86 | output | CELL25.OUT9.TMIN |
| MAXISRCTDATA87 | output | CELL25.OUT10.TMIN |
| MAXISRCTDATA88 | output | CELL26.OUT1.TMIN |
| MAXISRCTDATA89 | output | CELL26.OUT4.TMIN |
| MAXISRCTDATA9 | output | CELL4.OUT17.TMIN |
| MAXISRCTDATA90 | output | CELL26.OUT5.TMIN |
| MAXISRCTDATA91 | output | CELL26.OUT8.TMIN |
| MAXISRCTDATA92 | output | CELL27.OUT3.TMIN |
| MAXISRCTDATA93 | output | CELL27.OUT5.TMIN |
| MAXISRCTDATA94 | output | CELL27.OUT8.TMIN |
| MAXISRCTDATA95 | output | CELL27.OUT9.TMIN |
| MAXISRCTDATA96 | output | CELL28.OUT5.TMIN |
| MAXISRCTDATA97 | output | CELL28.OUT7.TMIN |
| MAXISRCTDATA98 | output | CELL28.OUT9.TMIN |
| MAXISRCTDATA99 | output | CELL28.OUT11.TMIN |
| MAXISRCTKEEP0 | output | CELL10.OUT8.TMIN |
| MAXISRCTKEEP1 | output | CELL10.OUT9.TMIN |
| MAXISRCTKEEP2 | output | CELL10.OUT10.TMIN |
| MAXISRCTKEEP3 | output | CELL10.OUT11.TMIN |
| MAXISRCTKEEP4 | output | CELL11.OUT8.TMIN |
| MAXISRCTKEEP5 | output | CELL11.OUT9.TMIN |
| MAXISRCTKEEP6 | output | CELL11.OUT10.TMIN |
| MAXISRCTKEEP7 | output | CELL11.OUT11.TMIN |
| MAXISRCTLAST | output | CELL0.OUT11.TMIN |
| MAXISRCTREADY0 | input | CELL2.IMUX.IMUX16.DELAY |
| MAXISRCTREADY1 | input | CELL2.IMUX.IMUX17.DELAY |
| MAXISRCTREADY10 | input | CELL4.IMUX.IMUX18.DELAY |
| MAXISRCTREADY11 | input | CELL4.IMUX.IMUX19.DELAY |
| MAXISRCTREADY12 | input | CELL5.IMUX.IMUX16.DELAY |
| MAXISRCTREADY13 | input | CELL5.IMUX.IMUX17.DELAY |
| MAXISRCTREADY14 | input | CELL5.IMUX.IMUX18.DELAY |
| MAXISRCTREADY15 | input | CELL5.IMUX.IMUX19.DELAY |
| MAXISRCTREADY16 | input | CELL6.IMUX.IMUX16.DELAY |
| MAXISRCTREADY17 | input | CELL6.IMUX.IMUX17.DELAY |
| MAXISRCTREADY18 | input | CELL6.IMUX.IMUX18.DELAY |
| MAXISRCTREADY19 | input | CELL6.IMUX.IMUX19.DELAY |
| MAXISRCTREADY2 | input | CELL2.IMUX.IMUX18.DELAY |
| MAXISRCTREADY20 | input | CELL7.IMUX.IMUX16.DELAY |
| MAXISRCTREADY21 | input | CELL7.IMUX.IMUX17.DELAY |
| MAXISRCTREADY3 | input | CELL2.IMUX.IMUX19.DELAY |
| MAXISRCTREADY4 | input | CELL3.IMUX.IMUX16.DELAY |
| MAXISRCTREADY5 | input | CELL3.IMUX.IMUX17.DELAY |
| MAXISRCTREADY6 | input | CELL3.IMUX.IMUX18.DELAY |
| MAXISRCTREADY7 | input | CELL3.IMUX.IMUX19.DELAY |
| MAXISRCTREADY8 | input | CELL4.IMUX.IMUX16.DELAY |
| MAXISRCTREADY9 | input | CELL4.IMUX.IMUX17.DELAY |
| MAXISRCTUSER0 | output | CELL5.OUT11.TMIN |
| MAXISRCTUSER1 | output | CELL5.OUT12.TMIN |
| MAXISRCTUSER10 | output | CELL10.OUT6.TMIN |
| MAXISRCTUSER11 | output | CELL10.OUT7.TMIN |
| MAXISRCTUSER12 | output | CELL11.OUT4.TMIN |
| MAXISRCTUSER13 | output | CELL11.OUT5.TMIN |
| MAXISRCTUSER14 | output | CELL11.OUT6.TMIN |
| MAXISRCTUSER15 | output | CELL11.OUT7.TMIN |
| MAXISRCTUSER16 | output | CELL12.OUT4.TMIN |
| MAXISRCTUSER17 | output | CELL12.OUT5.TMIN |
| MAXISRCTUSER18 | output | CELL12.OUT6.TMIN |
| MAXISRCTUSER19 | output | CELL12.OUT7.TMIN |
| MAXISRCTUSER2 | output | CELL5.OUT13.TMIN |
| MAXISRCTUSER20 | output | CELL13.OUT4.TMIN |
| MAXISRCTUSER21 | output | CELL13.OUT5.TMIN |
| MAXISRCTUSER22 | output | CELL13.OUT6.TMIN |
| MAXISRCTUSER23 | output | CELL13.OUT7.TMIN |
| MAXISRCTUSER24 | output | CELL14.OUT4.TMIN |
| MAXISRCTUSER25 | output | CELL14.OUT5.TMIN |
| MAXISRCTUSER26 | output | CELL14.OUT6.TMIN |
| MAXISRCTUSER27 | output | CELL14.OUT7.TMIN |
| MAXISRCTUSER28 | output | CELL15.OUT11.TMIN |
| MAXISRCTUSER29 | output | CELL15.OUT12.TMIN |
| MAXISRCTUSER3 | output | CELL5.OUT14.TMIN |
| MAXISRCTUSER30 | output | CELL15.OUT13.TMIN |
| MAXISRCTUSER31 | output | CELL15.OUT14.TMIN |
| MAXISRCTUSER32 | output | CELL16.OUT9.TMIN |
| MAXISRCTUSER33 | output | CELL17.OUT10.TMIN |
| MAXISRCTUSER34 | output | CELL17.OUT11.TMIN |
| MAXISRCTUSER35 | output | CELL17.OUT12.TMIN |
| MAXISRCTUSER36 | output | CELL17.OUT13.TMIN |
| MAXISRCTUSER37 | output | CELL18.OUT15.TMIN |
| MAXISRCTUSER38 | output | CELL19.OUT4.TMIN |
| MAXISRCTUSER39 | output | CELL19.OUT5.TMIN |
| MAXISRCTUSER4 | output | CELL7.OUT16.TMIN |
| MAXISRCTUSER40 | output | CELL19.OUT6.TMIN |
| MAXISRCTUSER41 | output | CELL19.OUT7.TMIN |
| MAXISRCTUSER42 | output | CELL20.OUT11.TMIN |
| MAXISRCTUSER43 | output | CELL20.OUT12.TMIN |
| MAXISRCTUSER44 | output | CELL20.OUT13.TMIN |
| MAXISRCTUSER45 | output | CELL20.OUT14.TMIN |
| MAXISRCTUSER46 | output | CELL21.OUT9.TMIN |
| MAXISRCTUSER47 | output | CELL22.OUT10.TMIN |
| MAXISRCTUSER48 | output | CELL22.OUT11.TMIN |
| MAXISRCTUSER49 | output | CELL22.OUT12.TMIN |
| MAXISRCTUSER5 | output | CELL7.OUT17.TMIN |
| MAXISRCTUSER50 | output | CELL22.OUT13.TMIN |
| MAXISRCTUSER51 | output | CELL24.OUT16.TMIN |
| MAXISRCTUSER52 | output | CELL24.OUT17.TMIN |
| MAXISRCTUSER53 | output | CELL24.OUT18.TMIN |
| MAXISRCTUSER54 | output | CELL24.OUT19.TMIN |
| MAXISRCTUSER55 | output | CELL25.OUT15.TMIN |
| MAXISRCTUSER56 | output | CELL25.OUT16.TMIN |
| MAXISRCTUSER57 | output | CELL25.OUT17.TMIN |
| MAXISRCTUSER58 | output | CELL25.OUT18.TMIN |
| MAXISRCTUSER59 | output | CELL27.OUT14.TMIN |
| MAXISRCTUSER6 | output | CELL9.OUT20.TMIN |
| MAXISRCTUSER60 | output | CELL27.OUT16.TMIN |
| MAXISRCTUSER61 | output | CELL27.OUT17.TMIN |
| MAXISRCTUSER62 | output | CELL29.OUT16.TMIN |
| MAXISRCTUSER63 | output | CELL29.OUT17.TMIN |
| MAXISRCTUSER64 | output | CELL29.OUT18.TMIN |
| MAXISRCTUSER65 | output | CELL29.OUT19.TMIN |
| MAXISRCTUSER66 | output | CELL30.OUT15.TMIN |
| MAXISRCTUSER67 | output | CELL30.OUT16.TMIN |
| MAXISRCTUSER68 | output | CELL30.OUT17.TMIN |
| MAXISRCTUSER69 | output | CELL30.OUT18.TMIN |
| MAXISRCTUSER7 | output | CELL9.OUT21.TMIN |
| MAXISRCTUSER70 | output | CELL32.OUT14.TMIN |
| MAXISRCTUSER71 | output | CELL32.OUT16.TMIN |
| MAXISRCTUSER72 | output | CELL32.OUT17.TMIN |
| MAXISRCTUSER73 | output | CELL34.OUT16.TMIN |
| MAXISRCTUSER74 | output | CELL34.OUT17.TMIN |
| MAXISRCTUSER8 | output | CELL10.OUT4.TMIN |
| MAXISRCTUSER9 | output | CELL10.OUT5.TMIN |
| MAXISRCTVALID | output | CELL10.OUT12.TMIN |
| MGMTRESETN | input | CELL15.IMUX.IMUX21.DELAY |
| MGMTSTICKYRESETN | input | CELL15.IMUX.IMUX22.DELAY |
| MICOMPLETIONRAMREADADDRESSAL0 | output | CELL16.OUT14.TMIN |
| MICOMPLETIONRAMREADADDRESSAL1 | output | CELL18.OUT14.TMIN |
| MICOMPLETIONRAMREADADDRESSAL2 | output | CELL18.OUT12.TMIN |
| MICOMPLETIONRAMREADADDRESSAL3 | output | CELL18.OUT8.TMIN |
| MICOMPLETIONRAMREADADDRESSAL4 | output | CELL16.OUT10.TMIN |
| MICOMPLETIONRAMREADADDRESSAL5 | output | CELL16.OUT3.TMIN |
| MICOMPLETIONRAMREADADDRESSAL6 | output | CELL17.OUT2.TMIN |
| MICOMPLETIONRAMREADADDRESSAL7 | output | CELL16.OUT11.TMIN |
| MICOMPLETIONRAMREADADDRESSAL8 | output | CELL18.OUT10.TMIN |
| MICOMPLETIONRAMREADADDRESSAL9 | output | CELL18.OUT13.TMIN |
| MICOMPLETIONRAMREADADDRESSAU0 | output | CELL26.OUT14.TMIN |
| MICOMPLETIONRAMREADADDRESSAU1 | output | CELL28.OUT14.TMIN |
| MICOMPLETIONRAMREADADDRESSAU2 | output | CELL28.OUT12.TMIN |
| MICOMPLETIONRAMREADADDRESSAU3 | output | CELL28.OUT8.TMIN |
| MICOMPLETIONRAMREADADDRESSAU4 | output | CELL26.OUT10.TMIN |
| MICOMPLETIONRAMREADADDRESSAU5 | output | CELL28.OUT13.TMIN |
| MICOMPLETIONRAMREADADDRESSAU6 | output | CELL27.OUT2.TMIN |
| MICOMPLETIONRAMREADADDRESSAU7 | output | CELL26.OUT11.TMIN |
| MICOMPLETIONRAMREADADDRESSAU8 | output | CELL28.OUT10.TMIN |
| MICOMPLETIONRAMREADADDRESSAU9 | output | CELL26.OUT3.TMIN |
| MICOMPLETIONRAMREADADDRESSBL0 | output | CELL23.OUT12.TMIN |
| MICOMPLETIONRAMREADADDRESSBL1 | output | CELL23.OUT14.TMIN |
| MICOMPLETIONRAMREADADDRESSBL2 | output | CELL21.OUT10.TMIN |
| MICOMPLETIONRAMREADADDRESSBL3 | output | CELL23.OUT8.TMIN |
| MICOMPLETIONRAMREADADDRESSBL4 | output | CELL21.OUT14.TMIN |
| MICOMPLETIONRAMREADADDRESSBL5 | output | CELL23.OUT13.TMIN |
| MICOMPLETIONRAMREADADDRESSBL6 | output | CELL22.OUT2.TMIN |
| MICOMPLETIONRAMREADADDRESSBL7 | output | CELL21.OUT11.TMIN |
| MICOMPLETIONRAMREADADDRESSBL8 | output | CELL23.OUT10.TMIN |
| MICOMPLETIONRAMREADADDRESSBL9 | output | CELL21.OUT3.TMIN |
| MICOMPLETIONRAMREADADDRESSBU0 | output | CELL31.OUT10.TMIN |
| MICOMPLETIONRAMREADADDRESSBU1 | output | CELL33.OUT14.TMIN |
| MICOMPLETIONRAMREADADDRESSBU2 | output | CELL33.OUT12.TMIN |
| MICOMPLETIONRAMREADADDRESSBU3 | output | CELL33.OUT8.TMIN |
| MICOMPLETIONRAMREADADDRESSBU4 | output | CELL31.OUT14.TMIN |
| MICOMPLETIONRAMREADADDRESSBU5 | output | CELL33.OUT13.TMIN |
| MICOMPLETIONRAMREADADDRESSBU6 | output | CELL32.OUT2.TMIN |
| MICOMPLETIONRAMREADADDRESSBU7 | output | CELL31.OUT11.TMIN |
| MICOMPLETIONRAMREADADDRESSBU8 | output | CELL33.OUT10.TMIN |
| MICOMPLETIONRAMREADADDRESSBU9 | output | CELL31.OUT3.TMIN |
| MICOMPLETIONRAMREADDATA0 | input | CELL18.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA1 | input | CELL18.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA10 | input | CELL20.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA100 | input | CELL32.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA101 | input | CELL32.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA102 | input | CELL32.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA103 | input | CELL32.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA104 | input | CELL32.IMUX.IMUX4.DELAY |
| MICOMPLETIONRAMREADDATA105 | input | CELL32.IMUX.IMUX5.DELAY |
| MICOMPLETIONRAMREADDATA106 | input | CELL32.IMUX.IMUX6.DELAY |
| MICOMPLETIONRAMREADDATA107 | input | CELL32.IMUX.IMUX7.DELAY |
| MICOMPLETIONRAMREADDATA108 | input | CELL33.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA109 | input | CELL33.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA11 | input | CELL20.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA110 | input | CELL33.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA111 | input | CELL33.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA112 | input | CELL33.IMUX.IMUX4.DELAY |
| MICOMPLETIONRAMREADDATA113 | input | CELL33.IMUX.IMUX5.DELAY |
| MICOMPLETIONRAMREADDATA114 | input | CELL33.IMUX.IMUX6.DELAY |
| MICOMPLETIONRAMREADDATA115 | input | CELL33.IMUX.IMUX7.DELAY |
| MICOMPLETIONRAMREADDATA116 | input | CELL34.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA117 | input | CELL34.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA118 | input | CELL34.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA119 | input | CELL34.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA12 | input | CELL21.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA120 | input | CELL34.IMUX.IMUX4.DELAY |
| MICOMPLETIONRAMREADDATA121 | input | CELL34.IMUX.IMUX5.DELAY |
| MICOMPLETIONRAMREADDATA122 | input | CELL34.IMUX.IMUX6.DELAY |
| MICOMPLETIONRAMREADDATA123 | input | CELL34.IMUX.IMUX7.DELAY |
| MICOMPLETIONRAMREADDATA124 | input | CELL35.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA125 | input | CELL35.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA126 | input | CELL35.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA127 | input | CELL35.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA128 | input | CELL35.IMUX.IMUX4.DELAY |
| MICOMPLETIONRAMREADDATA129 | input | CELL35.IMUX.IMUX5.DELAY |
| MICOMPLETIONRAMREADDATA13 | input | CELL21.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA130 | input | CELL35.IMUX.IMUX6.DELAY |
| MICOMPLETIONRAMREADDATA131 | input | CELL35.IMUX.IMUX7.DELAY |
| MICOMPLETIONRAMREADDATA132 | input | CELL36.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA133 | input | CELL36.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA134 | input | CELL36.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA135 | input | CELL36.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA136 | input | CELL36.IMUX.IMUX4.DELAY |
| MICOMPLETIONRAMREADDATA137 | input | CELL36.IMUX.IMUX5.DELAY |
| MICOMPLETIONRAMREADDATA138 | input | CELL36.IMUX.IMUX6.DELAY |
| MICOMPLETIONRAMREADDATA139 | input | CELL36.IMUX.IMUX7.DELAY |
| MICOMPLETIONRAMREADDATA14 | input | CELL21.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA140 | input | CELL37.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA141 | input | CELL37.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA142 | input | CELL37.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA143 | input | CELL37.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA15 | input | CELL21.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA16 | input | CELL21.IMUX.IMUX4.DELAY |
| MICOMPLETIONRAMREADDATA17 | input | CELL21.IMUX.IMUX5.DELAY |
| MICOMPLETIONRAMREADDATA18 | input | CELL21.IMUX.IMUX6.DELAY |
| MICOMPLETIONRAMREADDATA19 | input | CELL21.IMUX.IMUX7.DELAY |
| MICOMPLETIONRAMREADDATA2 | input | CELL18.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA20 | input | CELL22.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA21 | input | CELL22.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA22 | input | CELL22.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA23 | input | CELL22.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA24 | input | CELL22.IMUX.IMUX4.DELAY |
| MICOMPLETIONRAMREADDATA25 | input | CELL22.IMUX.IMUX5.DELAY |
| MICOMPLETIONRAMREADDATA26 | input | CELL22.IMUX.IMUX6.DELAY |
| MICOMPLETIONRAMREADDATA27 | input | CELL22.IMUX.IMUX7.DELAY |
| MICOMPLETIONRAMREADDATA28 | input | CELL23.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA29 | input | CELL23.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA3 | input | CELL18.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA30 | input | CELL23.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA31 | input | CELL23.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA32 | input | CELL23.IMUX.IMUX4.DELAY |
| MICOMPLETIONRAMREADDATA33 | input | CELL23.IMUX.IMUX5.DELAY |
| MICOMPLETIONRAMREADDATA34 | input | CELL23.IMUX.IMUX6.DELAY |
| MICOMPLETIONRAMREADDATA35 | input | CELL23.IMUX.IMUX7.DELAY |
| MICOMPLETIONRAMREADDATA36 | input | CELL24.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA37 | input | CELL24.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA38 | input | CELL24.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA39 | input | CELL24.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA4 | input | CELL19.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA40 | input | CELL24.IMUX.IMUX4.DELAY |
| MICOMPLETIONRAMREADDATA41 | input | CELL24.IMUX.IMUX5.DELAY |
| MICOMPLETIONRAMREADDATA42 | input | CELL24.IMUX.IMUX6.DELAY |
| MICOMPLETIONRAMREADDATA43 | input | CELL24.IMUX.IMUX7.DELAY |
| MICOMPLETIONRAMREADDATA44 | input | CELL25.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA45 | input | CELL25.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA46 | input | CELL25.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA47 | input | CELL25.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA48 | input | CELL25.IMUX.IMUX4.DELAY |
| MICOMPLETIONRAMREADDATA49 | input | CELL25.IMUX.IMUX5.DELAY |
| MICOMPLETIONRAMREADDATA5 | input | CELL19.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA50 | input | CELL25.IMUX.IMUX6.DELAY |
| MICOMPLETIONRAMREADDATA51 | input | CELL25.IMUX.IMUX7.DELAY |
| MICOMPLETIONRAMREADDATA52 | input | CELL26.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA53 | input | CELL26.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA54 | input | CELL26.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA55 | input | CELL26.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA56 | input | CELL26.IMUX.IMUX4.DELAY |
| MICOMPLETIONRAMREADDATA57 | input | CELL26.IMUX.IMUX5.DELAY |
| MICOMPLETIONRAMREADDATA58 | input | CELL26.IMUX.IMUX6.DELAY |
| MICOMPLETIONRAMREADDATA59 | input | CELL26.IMUX.IMUX7.DELAY |
| MICOMPLETIONRAMREADDATA6 | input | CELL19.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA60 | input | CELL27.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA61 | input | CELL27.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA62 | input | CELL27.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA63 | input | CELL27.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA64 | input | CELL27.IMUX.IMUX4.DELAY |
| MICOMPLETIONRAMREADDATA65 | input | CELL27.IMUX.IMUX5.DELAY |
| MICOMPLETIONRAMREADDATA66 | input | CELL27.IMUX.IMUX6.DELAY |
| MICOMPLETIONRAMREADDATA67 | input | CELL27.IMUX.IMUX7.DELAY |
| MICOMPLETIONRAMREADDATA68 | input | CELL28.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA69 | input | CELL28.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA7 | input | CELL19.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA70 | input | CELL28.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA71 | input | CELL28.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA72 | input | CELL28.IMUX.IMUX4.DELAY |
| MICOMPLETIONRAMREADDATA73 | input | CELL28.IMUX.IMUX5.DELAY |
| MICOMPLETIONRAMREADDATA74 | input | CELL28.IMUX.IMUX6.DELAY |
| MICOMPLETIONRAMREADDATA75 | input | CELL28.IMUX.IMUX7.DELAY |
| MICOMPLETIONRAMREADDATA76 | input | CELL29.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA77 | input | CELL29.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA78 | input | CELL29.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA79 | input | CELL29.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA8 | input | CELL20.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA80 | input | CELL29.IMUX.IMUX4.DELAY |
| MICOMPLETIONRAMREADDATA81 | input | CELL29.IMUX.IMUX5.DELAY |
| MICOMPLETIONRAMREADDATA82 | input | CELL29.IMUX.IMUX6.DELAY |
| MICOMPLETIONRAMREADDATA83 | input | CELL29.IMUX.IMUX7.DELAY |
| MICOMPLETIONRAMREADDATA84 | input | CELL30.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA85 | input | CELL30.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA86 | input | CELL30.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA87 | input | CELL30.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA88 | input | CELL30.IMUX.IMUX4.DELAY |
| MICOMPLETIONRAMREADDATA89 | input | CELL30.IMUX.IMUX5.DELAY |
| MICOMPLETIONRAMREADDATA9 | input | CELL20.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA90 | input | CELL30.IMUX.IMUX6.DELAY |
| MICOMPLETIONRAMREADDATA91 | input | CELL30.IMUX.IMUX7.DELAY |
| MICOMPLETIONRAMREADDATA92 | input | CELL31.IMUX.IMUX0.DELAY |
| MICOMPLETIONRAMREADDATA93 | input | CELL31.IMUX.IMUX1.DELAY |
| MICOMPLETIONRAMREADDATA94 | input | CELL31.IMUX.IMUX2.DELAY |
| MICOMPLETIONRAMREADDATA95 | input | CELL31.IMUX.IMUX3.DELAY |
| MICOMPLETIONRAMREADDATA96 | input | CELL31.IMUX.IMUX4.DELAY |
| MICOMPLETIONRAMREADDATA97 | input | CELL31.IMUX.IMUX5.DELAY |
| MICOMPLETIONRAMREADDATA98 | input | CELL31.IMUX.IMUX6.DELAY |
| MICOMPLETIONRAMREADDATA99 | input | CELL31.IMUX.IMUX7.DELAY |
| MICOMPLETIONRAMREADENABLEL0 | output | CELL17.OUT0.TMIN |
| MICOMPLETIONRAMREADENABLEL1 | output | CELL17.OUT4.TMIN |
| MICOMPLETIONRAMREADENABLEL2 | output | CELL22.OUT0.TMIN |
| MICOMPLETIONRAMREADENABLEL3 | output | CELL22.OUT4.TMIN |
| MICOMPLETIONRAMREADENABLEU0 | output | CELL27.OUT0.TMIN |
| MICOMPLETIONRAMREADENABLEU1 | output | CELL27.OUT4.TMIN |
| MICOMPLETIONRAMREADENABLEU2 | output | CELL32.OUT0.TMIN |
| MICOMPLETIONRAMREADENABLEU3 | output | CELL32.OUT4.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAL0 | output | CELL16.OUT6.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAL1 | output | CELL18.OUT2.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAL2 | output | CELL18.OUT0.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAL3 | output | CELL18.OUT4.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAL4 | output | CELL16.OUT2.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAL5 | output | CELL16.OUT7.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAL6 | output | CELL17.OUT20.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAL7 | output | CELL18.OUT1.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAL8 | output | CELL18.OUT6.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAL9 | output | CELL16.OUT21.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAU0 | output | CELL26.OUT6.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAU1 | output | CELL28.OUT2.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAU2 | output | CELL28.OUT0.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAU3 | output | CELL28.OUT4.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAU4 | output | CELL26.OUT2.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAU5 | output | CELL28.OUT1.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAU6 | output | CELL27.OUT20.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAU7 | output | CELL26.OUT7.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAU8 | output | CELL28.OUT6.TMIN |
| MICOMPLETIONRAMWRITEADDRESSAU9 | output | CELL26.OUT21.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBL0 | output | CELL21.OUT6.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBL1 | output | CELL23.OUT0.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBL2 | output | CELL23.OUT2.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBL3 | output | CELL23.OUT4.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBL4 | output | CELL21.OUT2.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBL5 | output | CELL23.OUT1.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBL6 | output | CELL22.OUT20.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBL7 | output | CELL21.OUT7.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBL8 | output | CELL23.OUT6.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBL9 | output | CELL21.OUT21.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBU0 | output | CELL31.OUT6.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBU1 | output | CELL33.OUT2.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBU2 | output | CELL33.OUT0.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBU3 | output | CELL33.OUT4.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBU4 | output | CELL31.OUT2.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBU5 | output | CELL33.OUT1.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBU6 | output | CELL32.OUT20.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBU7 | output | CELL31.OUT7.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBU8 | output | CELL33.OUT6.TMIN |
| MICOMPLETIONRAMWRITEADDRESSBU9 | output | CELL31.OUT21.TMIN |
| MICOMPLETIONRAMWRITEDATAL0 | output | CELL16.OUT0.TMIN |
| MICOMPLETIONRAMWRITEDATAL1 | output | CELL15.OUT5.TMIN |
| MICOMPLETIONRAMWRITEDATAL10 | output | CELL16.OUT20.TMIN |
| MICOMPLETIONRAMWRITEDATAL11 | output | CELL15.OUT3.TMIN |
| MICOMPLETIONRAMWRITEDATAL12 | output | CELL16.OUT19.TMIN |
| MICOMPLETIONRAMWRITEDATAL13 | output | CELL15.OUT6.TMIN |
| MICOMPLETIONRAMWRITEDATAL14 | output | CELL16.OUT17.TMIN |
| MICOMPLETIONRAMWRITEDATAL15 | output | CELL17.OUT18.TMIN |
| MICOMPLETIONRAMWRITEDATAL16 | output | CELL17.OUT1.TMIN |
| MICOMPLETIONRAMWRITEDATAL17 | output | CELL16.OUT22.TMIN |
| MICOMPLETIONRAMWRITEDATAL18 | output | CELL16.OUT12.TMIN |
| MICOMPLETIONRAMWRITEDATAL19 | output | CELL18.OUT22.TMIN |
| MICOMPLETIONRAMWRITEDATAL2 | output | CELL15.OUT2.TMIN |
| MICOMPLETIONRAMWRITEDATAL20 | output | CELL18.OUT19.TMIN |
| MICOMPLETIONRAMWRITEDATAL21 | output | CELL18.OUT20.TMIN |
| MICOMPLETIONRAMWRITEDATAL22 | output | CELL19.OUT12.TMIN |
| MICOMPLETIONRAMWRITEDATAL23 | output | CELL19.OUT9.TMIN |
| MICOMPLETIONRAMWRITEDATAL24 | output | CELL19.OUT14.TMIN |
| MICOMPLETIONRAMWRITEDATAL25 | output | CELL19.OUT11.TMIN |
| MICOMPLETIONRAMWRITEDATAL26 | output | CELL17.OUT15.TMIN |
| MICOMPLETIONRAMWRITEDATAL27 | output | CELL18.OUT18.TMIN |
| MICOMPLETIONRAMWRITEDATAL28 | output | CELL18.OUT23.TMIN |
| MICOMPLETIONRAMWRITEDATAL29 | output | CELL18.OUT16.TMIN |
| MICOMPLETIONRAMWRITEDATAL3 | output | CELL15.OUT7.TMIN |
| MICOMPLETIONRAMWRITEDATAL30 | output | CELL19.OUT8.TMIN |
| MICOMPLETIONRAMWRITEDATAL31 | output | CELL19.OUT13.TMIN |
| MICOMPLETIONRAMWRITEDATAL32 | output | CELL19.OUT10.TMIN |
| MICOMPLETIONRAMWRITEDATAL33 | output | CELL19.OUT15.TMIN |
| MICOMPLETIONRAMWRITEDATAL34 | output | CELL17.OUT19.TMIN |
| MICOMPLETIONRAMWRITEDATAL35 | output | CELL18.OUT3.TMIN |
| MICOMPLETIONRAMWRITEDATAL36 | output | CELL21.OUT0.TMIN |
| MICOMPLETIONRAMWRITEDATAL37 | output | CELL20.OUT5.TMIN |
| MICOMPLETIONRAMWRITEDATAL38 | output | CELL20.OUT2.TMIN |
| MICOMPLETIONRAMWRITEDATAL39 | output | CELL20.OUT7.TMIN |
| MICOMPLETIONRAMWRITEDATAL4 | output | CELL16.OUT18.TMIN |
| MICOMPLETIONRAMWRITEDATAL40 | output | CELL21.OUT18.TMIN |
| MICOMPLETIONRAMWRITEDATAL41 | output | CELL21.OUT23.TMIN |
| MICOMPLETIONRAMWRITEDATAL42 | output | CELL21.OUT16.TMIN |
| MICOMPLETIONRAMWRITEDATAL43 | output | CELL20.OUT4.TMIN |
| MICOMPLETIONRAMWRITEDATAL44 | output | CELL22.OUT22.TMIN |
| MICOMPLETIONRAMWRITEDATAL45 | output | CELL20.OUT1.TMIN |
| MICOMPLETIONRAMWRITEDATAL46 | output | CELL20.OUT6.TMIN |
| MICOMPLETIONRAMWRITEDATAL47 | output | CELL20.OUT3.TMIN |
| MICOMPLETIONRAMWRITEDATAL48 | output | CELL21.OUT19.TMIN |
| MICOMPLETIONRAMWRITEDATAL49 | output | CELL21.OUT20.TMIN |
| MICOMPLETIONRAMWRITEDATAL5 | output | CELL15.OUT4.TMIN |
| MICOMPLETIONRAMWRITEDATAL50 | output | CELL21.OUT17.TMIN |
| MICOMPLETIONRAMWRITEDATAL51 | output | CELL22.OUT18.TMIN |
| MICOMPLETIONRAMWRITEDATAL52 | output | CELL22.OUT1.TMIN |
| MICOMPLETIONRAMWRITEDATAL53 | output | CELL21.OUT22.TMIN |
| MICOMPLETIONRAMWRITEDATAL54 | output | CELL21.OUT12.TMIN |
| MICOMPLETIONRAMWRITEDATAL55 | output | CELL23.OUT22.TMIN |
| MICOMPLETIONRAMWRITEDATAL56 | output | CELL23.OUT19.TMIN |
| MICOMPLETIONRAMWRITEDATAL57 | output | CELL23.OUT20.TMIN |
| MICOMPLETIONRAMWRITEDATAL58 | output | CELL24.OUT12.TMIN |
| MICOMPLETIONRAMWRITEDATAL59 | output | CELL24.OUT9.TMIN |
| MICOMPLETIONRAMWRITEDATAL6 | output | CELL16.OUT16.TMIN |
| MICOMPLETIONRAMWRITEDATAL60 | output | CELL24.OUT14.TMIN |
| MICOMPLETIONRAMWRITEDATAL61 | output | CELL24.OUT11.TMIN |
| MICOMPLETIONRAMWRITEDATAL62 | output | CELL22.OUT15.TMIN |
| MICOMPLETIONRAMWRITEDATAL63 | output | CELL23.OUT18.TMIN |
| MICOMPLETIONRAMWRITEDATAL64 | output | CELL23.OUT23.TMIN |
| MICOMPLETIONRAMWRITEDATAL65 | output | CELL23.OUT16.TMIN |
| MICOMPLETIONRAMWRITEDATAL66 | output | CELL24.OUT8.TMIN |
| MICOMPLETIONRAMWRITEDATAL67 | output | CELL24.OUT13.TMIN |
| MICOMPLETIONRAMWRITEDATAL68 | output | CELL24.OUT10.TMIN |
| MICOMPLETIONRAMWRITEDATAL69 | output | CELL24.OUT15.TMIN |
| MICOMPLETIONRAMWRITEDATAL7 | output | CELL17.OUT22.TMIN |
| MICOMPLETIONRAMWRITEDATAL70 | output | CELL22.OUT19.TMIN |
| MICOMPLETIONRAMWRITEDATAL71 | output | CELL23.OUT3.TMIN |
| MICOMPLETIONRAMWRITEDATAL8 | output | CELL16.OUT23.TMIN |
| MICOMPLETIONRAMWRITEDATAL9 | output | CELL15.OUT1.TMIN |
| MICOMPLETIONRAMWRITEDATAU0 | output | CELL26.OUT0.TMIN |
| MICOMPLETIONRAMWRITEDATAU1 | output | CELL25.OUT5.TMIN |
| MICOMPLETIONRAMWRITEDATAU10 | output | CELL25.OUT6.TMIN |
| MICOMPLETIONRAMWRITEDATAU11 | output | CELL25.OUT3.TMIN |
| MICOMPLETIONRAMWRITEDATAU12 | output | CELL26.OUT19.TMIN |
| MICOMPLETIONRAMWRITEDATAU13 | output | CELL26.OUT20.TMIN |
| MICOMPLETIONRAMWRITEDATAU14 | output | CELL26.OUT17.TMIN |
| MICOMPLETIONRAMWRITEDATAU15 | output | CELL27.OUT18.TMIN |
| MICOMPLETIONRAMWRITEDATAU16 | output | CELL27.OUT1.TMIN |
| MICOMPLETIONRAMWRITEDATAU17 | output | CELL26.OUT22.TMIN |
| MICOMPLETIONRAMWRITEDATAU18 | output | CELL26.OUT12.TMIN |
| MICOMPLETIONRAMWRITEDATAU19 | output | CELL28.OUT22.TMIN |
| MICOMPLETIONRAMWRITEDATAU2 | output | CELL25.OUT2.TMIN |
| MICOMPLETIONRAMWRITEDATAU20 | output | CELL28.OUT19.TMIN |
| MICOMPLETIONRAMWRITEDATAU21 | output | CELL28.OUT20.TMIN |
| MICOMPLETIONRAMWRITEDATAU22 | output | CELL29.OUT12.TMIN |
| MICOMPLETIONRAMWRITEDATAU23 | output | CELL29.OUT9.TMIN |
| MICOMPLETIONRAMWRITEDATAU24 | output | CELL29.OUT14.TMIN |
| MICOMPLETIONRAMWRITEDATAU25 | output | CELL29.OUT11.TMIN |
| MICOMPLETIONRAMWRITEDATAU26 | output | CELL27.OUT15.TMIN |
| MICOMPLETIONRAMWRITEDATAU27 | output | CELL28.OUT18.TMIN |
| MICOMPLETIONRAMWRITEDATAU28 | output | CELL28.OUT23.TMIN |
| MICOMPLETIONRAMWRITEDATAU29 | output | CELL28.OUT16.TMIN |
| MICOMPLETIONRAMWRITEDATAU3 | output | CELL25.OUT7.TMIN |
| MICOMPLETIONRAMWRITEDATAU30 | output | CELL29.OUT8.TMIN |
| MICOMPLETIONRAMWRITEDATAU31 | output | CELL29.OUT13.TMIN |
| MICOMPLETIONRAMWRITEDATAU32 | output | CELL29.OUT10.TMIN |
| MICOMPLETIONRAMWRITEDATAU33 | output | CELL29.OUT15.TMIN |
| MICOMPLETIONRAMWRITEDATAU34 | output | CELL27.OUT19.TMIN |
| MICOMPLETIONRAMWRITEDATAU35 | output | CELL28.OUT3.TMIN |
| MICOMPLETIONRAMWRITEDATAU36 | output | CELL31.OUT0.TMIN |
| MICOMPLETIONRAMWRITEDATAU37 | output | CELL30.OUT5.TMIN |
| MICOMPLETIONRAMWRITEDATAU38 | output | CELL30.OUT2.TMIN |
| MICOMPLETIONRAMWRITEDATAU39 | output | CELL30.OUT7.TMIN |
| MICOMPLETIONRAMWRITEDATAU4 | output | CELL26.OUT18.TMIN |
| MICOMPLETIONRAMWRITEDATAU40 | output | CELL31.OUT18.TMIN |
| MICOMPLETIONRAMWRITEDATAU41 | output | CELL31.OUT23.TMIN |
| MICOMPLETIONRAMWRITEDATAU42 | output | CELL31.OUT16.TMIN |
| MICOMPLETIONRAMWRITEDATAU43 | output | CELL32.OUT22.TMIN |
| MICOMPLETIONRAMWRITEDATAU44 | output | CELL30.OUT4.TMIN |
| MICOMPLETIONRAMWRITEDATAU45 | output | CELL30.OUT1.TMIN |
| MICOMPLETIONRAMWRITEDATAU46 | output | CELL30.OUT6.TMIN |
| MICOMPLETIONRAMWRITEDATAU47 | output | CELL30.OUT3.TMIN |
| MICOMPLETIONRAMWRITEDATAU48 | output | CELL31.OUT19.TMIN |
| MICOMPLETIONRAMWRITEDATAU49 | output | CELL31.OUT20.TMIN |
| MICOMPLETIONRAMWRITEDATAU5 | output | CELL26.OUT23.TMIN |
| MICOMPLETIONRAMWRITEDATAU50 | output | CELL31.OUT17.TMIN |
| MICOMPLETIONRAMWRITEDATAU51 | output | CELL32.OUT18.TMIN |
| MICOMPLETIONRAMWRITEDATAU52 | output | CELL32.OUT1.TMIN |
| MICOMPLETIONRAMWRITEDATAU53 | output | CELL31.OUT22.TMIN |
| MICOMPLETIONRAMWRITEDATAU54 | output | CELL31.OUT12.TMIN |
| MICOMPLETIONRAMWRITEDATAU55 | output | CELL33.OUT22.TMIN |
| MICOMPLETIONRAMWRITEDATAU56 | output | CELL33.OUT19.TMIN |
| MICOMPLETIONRAMWRITEDATAU57 | output | CELL33.OUT20.TMIN |
| MICOMPLETIONRAMWRITEDATAU58 | output | CELL34.OUT12.TMIN |
| MICOMPLETIONRAMWRITEDATAU59 | output | CELL34.OUT9.TMIN |
| MICOMPLETIONRAMWRITEDATAU6 | output | CELL26.OUT16.TMIN |
| MICOMPLETIONRAMWRITEDATAU60 | output | CELL34.OUT14.TMIN |
| MICOMPLETIONRAMWRITEDATAU61 | output | CELL34.OUT11.TMIN |
| MICOMPLETIONRAMWRITEDATAU62 | output | CELL32.OUT15.TMIN |
| MICOMPLETIONRAMWRITEDATAU63 | output | CELL33.OUT18.TMIN |
| MICOMPLETIONRAMWRITEDATAU64 | output | CELL33.OUT23.TMIN |
| MICOMPLETIONRAMWRITEDATAU65 | output | CELL33.OUT16.TMIN |
| MICOMPLETIONRAMWRITEDATAU66 | output | CELL34.OUT8.TMIN |
| MICOMPLETIONRAMWRITEDATAU67 | output | CELL34.OUT13.TMIN |
| MICOMPLETIONRAMWRITEDATAU68 | output | CELL34.OUT10.TMIN |
| MICOMPLETIONRAMWRITEDATAU69 | output | CELL34.OUT15.TMIN |
| MICOMPLETIONRAMWRITEDATAU7 | output | CELL27.OUT22.TMIN |
| MICOMPLETIONRAMWRITEDATAU70 | output | CELL32.OUT19.TMIN |
| MICOMPLETIONRAMWRITEDATAU71 | output | CELL33.OUT3.TMIN |
| MICOMPLETIONRAMWRITEDATAU8 | output | CELL25.OUT4.TMIN |
| MICOMPLETIONRAMWRITEDATAU9 | output | CELL25.OUT1.TMIN |
| MICOMPLETIONRAMWRITEENABLEL0 | output | CELL17.OUT6.TMIN |
| MICOMPLETIONRAMWRITEENABLEL1 | output | CELL17.OUT7.TMIN |
| MICOMPLETIONRAMWRITEENABLEL2 | output | CELL22.OUT6.TMIN |
| MICOMPLETIONRAMWRITEENABLEL3 | output | CELL22.OUT7.TMIN |
| MICOMPLETIONRAMWRITEENABLEU0 | output | CELL27.OUT6.TMIN |
| MICOMPLETIONRAMWRITEENABLEU1 | output | CELL27.OUT7.TMIN |
| MICOMPLETIONRAMWRITEENABLEU2 | output | CELL32.OUT6.TMIN |
| MICOMPLETIONRAMWRITEENABLEU3 | output | CELL32.OUT7.TMIN |
| MIREPLAYRAMADDRESS0 | output | CELL46.OUT13.TMIN |
| MIREPLAYRAMADDRESS1 | output | CELL44.OUT23.TMIN |
| MIREPLAYRAMADDRESS2 | output | CELL44.OUT6.TMIN |
| MIREPLAYRAMADDRESS3 | output | CELL45.OUT15.TMIN |
| MIREPLAYRAMADDRESS4 | output | CELL46.OUT1.TMIN |
| MIREPLAYRAMADDRESS5 | output | CELL45.OUT8.TMIN |
| MIREPLAYRAMADDRESS6 | output | CELL45.OUT11.TMIN |
| MIREPLAYRAMADDRESS7 | output | CELL44.OUT8.TMIN |
| MIREPLAYRAMADDRESS8 | output | CELL46.OUT7.TMIN |
| MIREPLAYRAMREADDATA0 | input | CELL38.IMUX.IMUX0.DELAY |
| MIREPLAYRAMREADDATA1 | input | CELL38.IMUX.IMUX1.DELAY |
| MIREPLAYRAMREADDATA10 | input | CELL39.IMUX.IMUX2.DELAY |
| MIREPLAYRAMREADDATA100 | input | CELL46.IMUX.IMUX8.DELAY |
| MIREPLAYRAMREADDATA101 | input | CELL46.IMUX.IMUX9.DELAY |
| MIREPLAYRAMREADDATA102 | input | CELL46.IMUX.IMUX10.DELAY |
| MIREPLAYRAMREADDATA103 | input | CELL46.IMUX.IMUX11.DELAY |
| MIREPLAYRAMREADDATA104 | input | CELL47.IMUX.IMUX0.DELAY |
| MIREPLAYRAMREADDATA105 | input | CELL47.IMUX.IMUX1.DELAY |
| MIREPLAYRAMREADDATA106 | input | CELL47.IMUX.IMUX2.DELAY |
| MIREPLAYRAMREADDATA107 | input | CELL47.IMUX.IMUX3.DELAY |
| MIREPLAYRAMREADDATA108 | input | CELL47.IMUX.IMUX4.DELAY |
| MIREPLAYRAMREADDATA109 | input | CELL47.IMUX.IMUX5.DELAY |
| MIREPLAYRAMREADDATA11 | input | CELL39.IMUX.IMUX3.DELAY |
| MIREPLAYRAMREADDATA110 | input | CELL47.IMUX.IMUX6.DELAY |
| MIREPLAYRAMREADDATA111 | input | CELL47.IMUX.IMUX7.DELAY |
| MIREPLAYRAMREADDATA112 | input | CELL47.IMUX.IMUX8.DELAY |
| MIREPLAYRAMREADDATA113 | input | CELL47.IMUX.IMUX9.DELAY |
| MIREPLAYRAMREADDATA114 | input | CELL47.IMUX.IMUX10.DELAY |
| MIREPLAYRAMREADDATA115 | input | CELL47.IMUX.IMUX11.DELAY |
| MIREPLAYRAMREADDATA116 | input | CELL47.IMUX.IMUX12.DELAY |
| MIREPLAYRAMREADDATA117 | input | CELL47.IMUX.IMUX13.DELAY |
| MIREPLAYRAMREADDATA118 | input | CELL47.IMUX.IMUX14.DELAY |
| MIREPLAYRAMREADDATA119 | input | CELL47.IMUX.IMUX15.DELAY |
| MIREPLAYRAMREADDATA12 | input | CELL39.IMUX.IMUX4.DELAY |
| MIREPLAYRAMREADDATA120 | input | CELL48.IMUX.IMUX0.DELAY |
| MIREPLAYRAMREADDATA121 | input | CELL48.IMUX.IMUX1.DELAY |
| MIREPLAYRAMREADDATA122 | input | CELL48.IMUX.IMUX2.DELAY |
| MIREPLAYRAMREADDATA123 | input | CELL48.IMUX.IMUX3.DELAY |
| MIREPLAYRAMREADDATA124 | input | CELL48.IMUX.IMUX4.DELAY |
| MIREPLAYRAMREADDATA125 | input | CELL48.IMUX.IMUX5.DELAY |
| MIREPLAYRAMREADDATA126 | input | CELL48.IMUX.IMUX6.DELAY |
| MIREPLAYRAMREADDATA127 | input | CELL48.IMUX.IMUX7.DELAY |
| MIREPLAYRAMREADDATA128 | input | CELL48.IMUX.IMUX8.DELAY |
| MIREPLAYRAMREADDATA129 | input | CELL48.IMUX.IMUX9.DELAY |
| MIREPLAYRAMREADDATA13 | input | CELL39.IMUX.IMUX5.DELAY |
| MIREPLAYRAMREADDATA130 | input | CELL48.IMUX.IMUX10.DELAY |
| MIREPLAYRAMREADDATA131 | input | CELL48.IMUX.IMUX11.DELAY |
| MIREPLAYRAMREADDATA132 | input | CELL48.IMUX.IMUX12.DELAY |
| MIREPLAYRAMREADDATA133 | input | CELL48.IMUX.IMUX13.DELAY |
| MIREPLAYRAMREADDATA134 | input | CELL48.IMUX.IMUX14.DELAY |
| MIREPLAYRAMREADDATA135 | input | CELL48.IMUX.IMUX15.DELAY |
| MIREPLAYRAMREADDATA136 | input | CELL49.IMUX.IMUX0.DELAY |
| MIREPLAYRAMREADDATA137 | input | CELL49.IMUX.IMUX1.DELAY |
| MIREPLAYRAMREADDATA138 | input | CELL49.IMUX.IMUX2.DELAY |
| MIREPLAYRAMREADDATA139 | input | CELL49.IMUX.IMUX3.DELAY |
| MIREPLAYRAMREADDATA14 | input | CELL39.IMUX.IMUX6.DELAY |
| MIREPLAYRAMREADDATA140 | input | CELL49.IMUX.IMUX4.DELAY |
| MIREPLAYRAMREADDATA141 | input | CELL49.IMUX.IMUX5.DELAY |
| MIREPLAYRAMREADDATA142 | input | CELL49.IMUX.IMUX6.DELAY |
| MIREPLAYRAMREADDATA143 | input | CELL49.IMUX.IMUX7.DELAY |
| MIREPLAYRAMREADDATA15 | input | CELL39.IMUX.IMUX7.DELAY |
| MIREPLAYRAMREADDATA16 | input | CELL39.IMUX.IMUX8.DELAY |
| MIREPLAYRAMREADDATA17 | input | CELL39.IMUX.IMUX9.DELAY |
| MIREPLAYRAMREADDATA18 | input | CELL39.IMUX.IMUX10.DELAY |
| MIREPLAYRAMREADDATA19 | input | CELL39.IMUX.IMUX11.DELAY |
| MIREPLAYRAMREADDATA2 | input | CELL38.IMUX.IMUX2.DELAY |
| MIREPLAYRAMREADDATA20 | input | CELL40.IMUX.IMUX0.DELAY |
| MIREPLAYRAMREADDATA21 | input | CELL40.IMUX.IMUX1.DELAY |
| MIREPLAYRAMREADDATA22 | input | CELL40.IMUX.IMUX2.DELAY |
| MIREPLAYRAMREADDATA23 | input | CELL40.IMUX.IMUX3.DELAY |
| MIREPLAYRAMREADDATA24 | input | CELL40.IMUX.IMUX4.DELAY |
| MIREPLAYRAMREADDATA25 | input | CELL40.IMUX.IMUX5.DELAY |
| MIREPLAYRAMREADDATA26 | input | CELL40.IMUX.IMUX6.DELAY |
| MIREPLAYRAMREADDATA27 | input | CELL40.IMUX.IMUX7.DELAY |
| MIREPLAYRAMREADDATA28 | input | CELL40.IMUX.IMUX8.DELAY |
| MIREPLAYRAMREADDATA29 | input | CELL40.IMUX.IMUX9.DELAY |
| MIREPLAYRAMREADDATA3 | input | CELL38.IMUX.IMUX3.DELAY |
| MIREPLAYRAMREADDATA30 | input | CELL40.IMUX.IMUX10.DELAY |
| MIREPLAYRAMREADDATA31 | input | CELL40.IMUX.IMUX11.DELAY |
| MIREPLAYRAMREADDATA32 | input | CELL41.IMUX.IMUX0.DELAY |
| MIREPLAYRAMREADDATA33 | input | CELL41.IMUX.IMUX1.DELAY |
| MIREPLAYRAMREADDATA34 | input | CELL41.IMUX.IMUX2.DELAY |
| MIREPLAYRAMREADDATA35 | input | CELL41.IMUX.IMUX3.DELAY |
| MIREPLAYRAMREADDATA36 | input | CELL41.IMUX.IMUX4.DELAY |
| MIREPLAYRAMREADDATA37 | input | CELL41.IMUX.IMUX5.DELAY |
| MIREPLAYRAMREADDATA38 | input | CELL41.IMUX.IMUX6.DELAY |
| MIREPLAYRAMREADDATA39 | input | CELL41.IMUX.IMUX7.DELAY |
| MIREPLAYRAMREADDATA4 | input | CELL38.IMUX.IMUX4.DELAY |
| MIREPLAYRAMREADDATA40 | input | CELL41.IMUX.IMUX8.DELAY |
| MIREPLAYRAMREADDATA41 | input | CELL41.IMUX.IMUX9.DELAY |
| MIREPLAYRAMREADDATA42 | input | CELL41.IMUX.IMUX10.DELAY |
| MIREPLAYRAMREADDATA43 | input | CELL41.IMUX.IMUX11.DELAY |
| MIREPLAYRAMREADDATA44 | input | CELL42.IMUX.IMUX0.DELAY |
| MIREPLAYRAMREADDATA45 | input | CELL42.IMUX.IMUX1.DELAY |
| MIREPLAYRAMREADDATA46 | input | CELL42.IMUX.IMUX2.DELAY |
| MIREPLAYRAMREADDATA47 | input | CELL42.IMUX.IMUX3.DELAY |
| MIREPLAYRAMREADDATA48 | input | CELL42.IMUX.IMUX4.DELAY |
| MIREPLAYRAMREADDATA49 | input | CELL42.IMUX.IMUX5.DELAY |
| MIREPLAYRAMREADDATA5 | input | CELL38.IMUX.IMUX5.DELAY |
| MIREPLAYRAMREADDATA50 | input | CELL42.IMUX.IMUX6.DELAY |
| MIREPLAYRAMREADDATA51 | input | CELL42.IMUX.IMUX7.DELAY |
| MIREPLAYRAMREADDATA52 | input | CELL42.IMUX.IMUX8.DELAY |
| MIREPLAYRAMREADDATA53 | input | CELL42.IMUX.IMUX9.DELAY |
| MIREPLAYRAMREADDATA54 | input | CELL42.IMUX.IMUX10.DELAY |
| MIREPLAYRAMREADDATA55 | input | CELL42.IMUX.IMUX11.DELAY |
| MIREPLAYRAMREADDATA56 | input | CELL43.IMUX.IMUX0.DELAY |
| MIREPLAYRAMREADDATA57 | input | CELL43.IMUX.IMUX1.DELAY |
| MIREPLAYRAMREADDATA58 | input | CELL43.IMUX.IMUX2.DELAY |
| MIREPLAYRAMREADDATA59 | input | CELL43.IMUX.IMUX3.DELAY |
| MIREPLAYRAMREADDATA6 | input | CELL38.IMUX.IMUX6.DELAY |
| MIREPLAYRAMREADDATA60 | input | CELL43.IMUX.IMUX4.DELAY |
| MIREPLAYRAMREADDATA61 | input | CELL43.IMUX.IMUX5.DELAY |
| MIREPLAYRAMREADDATA62 | input | CELL43.IMUX.IMUX6.DELAY |
| MIREPLAYRAMREADDATA63 | input | CELL43.IMUX.IMUX7.DELAY |
| MIREPLAYRAMREADDATA64 | input | CELL43.IMUX.IMUX8.DELAY |
| MIREPLAYRAMREADDATA65 | input | CELL43.IMUX.IMUX9.DELAY |
| MIREPLAYRAMREADDATA66 | input | CELL43.IMUX.IMUX10.DELAY |
| MIREPLAYRAMREADDATA67 | input | CELL43.IMUX.IMUX11.DELAY |
| MIREPLAYRAMREADDATA68 | input | CELL44.IMUX.IMUX0.DELAY |
| MIREPLAYRAMREADDATA69 | input | CELL44.IMUX.IMUX1.DELAY |
| MIREPLAYRAMREADDATA7 | input | CELL38.IMUX.IMUX7.DELAY |
| MIREPLAYRAMREADDATA70 | input | CELL44.IMUX.IMUX2.DELAY |
| MIREPLAYRAMREADDATA71 | input | CELL44.IMUX.IMUX3.DELAY |
| MIREPLAYRAMREADDATA72 | input | CELL44.IMUX.IMUX4.DELAY |
| MIREPLAYRAMREADDATA73 | input | CELL44.IMUX.IMUX5.DELAY |
| MIREPLAYRAMREADDATA74 | input | CELL44.IMUX.IMUX6.DELAY |
| MIREPLAYRAMREADDATA75 | input | CELL44.IMUX.IMUX7.DELAY |
| MIREPLAYRAMREADDATA76 | input | CELL44.IMUX.IMUX8.DELAY |
| MIREPLAYRAMREADDATA77 | input | CELL44.IMUX.IMUX9.DELAY |
| MIREPLAYRAMREADDATA78 | input | CELL44.IMUX.IMUX10.DELAY |
| MIREPLAYRAMREADDATA79 | input | CELL44.IMUX.IMUX11.DELAY |
| MIREPLAYRAMREADDATA8 | input | CELL39.IMUX.IMUX0.DELAY |
| MIREPLAYRAMREADDATA80 | input | CELL45.IMUX.IMUX0.DELAY |
| MIREPLAYRAMREADDATA81 | input | CELL45.IMUX.IMUX1.DELAY |
| MIREPLAYRAMREADDATA82 | input | CELL45.IMUX.IMUX2.DELAY |
| MIREPLAYRAMREADDATA83 | input | CELL45.IMUX.IMUX3.DELAY |
| MIREPLAYRAMREADDATA84 | input | CELL45.IMUX.IMUX4.DELAY |
| MIREPLAYRAMREADDATA85 | input | CELL45.IMUX.IMUX5.DELAY |
| MIREPLAYRAMREADDATA86 | input | CELL45.IMUX.IMUX6.DELAY |
| MIREPLAYRAMREADDATA87 | input | CELL45.IMUX.IMUX7.DELAY |
| MIREPLAYRAMREADDATA88 | input | CELL45.IMUX.IMUX8.DELAY |
| MIREPLAYRAMREADDATA89 | input | CELL45.IMUX.IMUX9.DELAY |
| MIREPLAYRAMREADDATA9 | input | CELL39.IMUX.IMUX1.DELAY |
| MIREPLAYRAMREADDATA90 | input | CELL45.IMUX.IMUX10.DELAY |
| MIREPLAYRAMREADDATA91 | input | CELL45.IMUX.IMUX11.DELAY |
| MIREPLAYRAMREADDATA92 | input | CELL46.IMUX.IMUX0.DELAY |
| MIREPLAYRAMREADDATA93 | input | CELL46.IMUX.IMUX1.DELAY |
| MIREPLAYRAMREADDATA94 | input | CELL46.IMUX.IMUX2.DELAY |
| MIREPLAYRAMREADDATA95 | input | CELL46.IMUX.IMUX3.DELAY |
| MIREPLAYRAMREADDATA96 | input | CELL46.IMUX.IMUX4.DELAY |
| MIREPLAYRAMREADDATA97 | input | CELL46.IMUX.IMUX5.DELAY |
| MIREPLAYRAMREADDATA98 | input | CELL46.IMUX.IMUX6.DELAY |
| MIREPLAYRAMREADDATA99 | input | CELL46.IMUX.IMUX7.DELAY |
| MIREPLAYRAMREADENABLE0 | output | CELL42.OUT0.TMIN |
| MIREPLAYRAMREADENABLE1 | output | CELL47.OUT0.TMIN |
| MIREPLAYRAMWRITEDATA0 | output | CELL41.OUT9.TMIN |
| MIREPLAYRAMWRITEDATA1 | output | CELL40.OUT2.TMIN |
| MIREPLAYRAMWRITEDATA10 | output | CELL42.OUT22.TMIN |
| MIREPLAYRAMWRITEDATA100 | output | CELL45.OUT2.TMIN |
| MIREPLAYRAMWRITEDATA101 | output | CELL46.OUT6.TMIN |
| MIREPLAYRAMWRITEDATA102 | output | CELL47.OUT8.TMIN |
| MIREPLAYRAMWRITEDATA103 | output | CELL46.OUT18.TMIN |
| MIREPLAYRAMWRITEDATA104 | output | CELL45.OUT13.TMIN |
| MIREPLAYRAMWRITEDATA105 | output | CELL46.OUT17.TMIN |
| MIREPLAYRAMWRITEDATA106 | output | CELL49.OUT9.TMIN |
| MIREPLAYRAMWRITEDATA107 | output | CELL48.OUT1.TMIN |
| MIREPLAYRAMWRITEDATA108 | output | CELL47.OUT14.TMIN |
| MIREPLAYRAMWRITEDATA109 | output | CELL45.OUT18.TMIN |
| MIREPLAYRAMWRITEDATA11 | output | CELL40.OUT3.TMIN |
| MIREPLAYRAMWRITEDATA110 | output | CELL49.OUT5.TMIN |
| MIREPLAYRAMWRITEDATA111 | output | CELL49.OUT13.TMIN |
| MIREPLAYRAMWRITEDATA112 | output | CELL46.OUT3.TMIN |
| MIREPLAYRAMWRITEDATA113 | output | CELL47.OUT15.TMIN |
| MIREPLAYRAMWRITEDATA114 | output | CELL46.OUT12.TMIN |
| MIREPLAYRAMWRITEDATA115 | output | CELL47.OUT9.TMIN |
| MIREPLAYRAMWRITEDATA116 | output | CELL49.OUT10.TMIN |
| MIREPLAYRAMWRITEDATA117 | output | CELL49.OUT11.TMIN |
| MIREPLAYRAMWRITEDATA118 | output | CELL48.OUT9.TMIN |
| MIREPLAYRAMWRITEDATA119 | output | CELL48.OUT22.TMIN |
| MIREPLAYRAMWRITEDATA12 | output | CELL40.OUT6.TMIN |
| MIREPLAYRAMWRITEDATA120 | output | CELL49.OUT2.TMIN |
| MIREPLAYRAMWRITEDATA121 | output | CELL48.OUT17.TMIN |
| MIREPLAYRAMWRITEDATA122 | output | CELL49.OUT7.TMIN |
| MIREPLAYRAMWRITEDATA123 | output | CELL49.OUT8.TMIN |
| MIREPLAYRAMWRITEDATA124 | output | CELL48.OUT6.TMIN |
| MIREPLAYRAMWRITEDATA125 | output | CELL48.OUT8.TMIN |
| MIREPLAYRAMWRITEDATA126 | output | CELL47.OUT19.TMIN |
| MIREPLAYRAMWRITEDATA127 | output | CELL48.OUT15.TMIN |
| MIREPLAYRAMWRITEDATA128 | output | CELL48.OUT13.TMIN |
| MIREPLAYRAMWRITEDATA129 | output | CELL49.OUT15.TMIN |
| MIREPLAYRAMWRITEDATA13 | output | CELL40.OUT1.TMIN |
| MIREPLAYRAMWRITEDATA130 | output | CELL48.OUT14.TMIN |
| MIREPLAYRAMWRITEDATA131 | output | CELL49.OUT0.TMIN |
| MIREPLAYRAMWRITEDATA132 | output | CELL48.OUT3.TMIN |
| MIREPLAYRAMWRITEDATA133 | output | CELL47.OUT1.TMIN |
| MIREPLAYRAMWRITEDATA134 | output | CELL49.OUT14.TMIN |
| MIREPLAYRAMWRITEDATA135 | output | CELL47.OUT3.TMIN |
| MIREPLAYRAMWRITEDATA136 | output | CELL49.OUT4.TMIN |
| MIREPLAYRAMWRITEDATA137 | output | CELL46.OUT22.TMIN |
| MIREPLAYRAMWRITEDATA138 | output | CELL49.OUT1.TMIN |
| MIREPLAYRAMWRITEDATA139 | output | CELL48.OUT5.TMIN |
| MIREPLAYRAMWRITEDATA14 | output | CELL42.OUT7.TMIN |
| MIREPLAYRAMWRITEDATA140 | output | CELL49.OUT6.TMIN |
| MIREPLAYRAMWRITEDATA141 | output | CELL48.OUT21.TMIN |
| MIREPLAYRAMWRITEDATA142 | output | CELL48.OUT16.TMIN |
| MIREPLAYRAMWRITEDATA143 | output | CELL49.OUT3.TMIN |
| MIREPLAYRAMWRITEDATA15 | output | CELL41.OUT1.TMIN |
| MIREPLAYRAMWRITEDATA16 | output | CELL44.OUT2.TMIN |
| MIREPLAYRAMWRITEDATA17 | output | CELL41.OUT13.TMIN |
| MIREPLAYRAMWRITEDATA18 | output | CELL41.OUT2.TMIN |
| MIREPLAYRAMWRITEDATA19 | output | CELL42.OUT18.TMIN |
| MIREPLAYRAMWRITEDATA2 | output | CELL41.OUT19.TMIN |
| MIREPLAYRAMWRITEDATA20 | output | CELL40.OUT23.TMIN |
| MIREPLAYRAMWRITEDATA21 | output | CELL41.OUT4.TMIN |
| MIREPLAYRAMWRITEDATA22 | output | CELL41.OUT5.TMIN |
| MIREPLAYRAMWRITEDATA23 | output | CELL44.OUT17.TMIN |
| MIREPLAYRAMWRITEDATA24 | output | CELL41.OUT7.TMIN |
| MIREPLAYRAMWRITEDATA25 | output | CELL44.OUT0.TMIN |
| MIREPLAYRAMWRITEDATA26 | output | CELL40.OUT18.TMIN |
| MIREPLAYRAMWRITEDATA27 | output | CELL42.OUT14.TMIN |
| MIREPLAYRAMWRITEDATA28 | output | CELL43.OUT1.TMIN |
| MIREPLAYRAMWRITEDATA29 | output | CELL41.OUT3.TMIN |
| MIREPLAYRAMWRITEDATA3 | output | CELL40.OUT4.TMIN |
| MIREPLAYRAMWRITEDATA30 | output | CELL40.OUT17.TMIN |
| MIREPLAYRAMWRITEDATA31 | output | CELL40.OUT21.TMIN |
| MIREPLAYRAMWRITEDATA32 | output | CELL40.OUT19.TMIN |
| MIREPLAYRAMWRITEDATA33 | output | CELL40.OUT16.TMIN |
| MIREPLAYRAMWRITEDATA34 | output | CELL44.OUT11.TMIN |
| MIREPLAYRAMWRITEDATA35 | output | CELL42.OUT9.TMIN |
| MIREPLAYRAMWRITEDATA36 | output | CELL41.OUT10.TMIN |
| MIREPLAYRAMWRITEDATA37 | output | CELL41.OUT18.TMIN |
| MIREPLAYRAMWRITEDATA38 | output | CELL40.OUT20.TMIN |
| MIREPLAYRAMWRITEDATA39 | output | CELL43.OUT14.TMIN |
| MIREPLAYRAMWRITEDATA4 | output | CELL41.OUT0.TMIN |
| MIREPLAYRAMWRITEDATA40 | output | CELL43.OUT19.TMIN |
| MIREPLAYRAMWRITEDATA41 | output | CELL42.OUT15.TMIN |
| MIREPLAYRAMWRITEDATA42 | output | CELL42.OUT19.TMIN |
| MIREPLAYRAMWRITEDATA43 | output | CELL42.OUT8.TMIN |
| MIREPLAYRAMWRITEDATA44 | output | CELL43.OUT22.TMIN |
| MIREPLAYRAMWRITEDATA45 | output | CELL44.OUT7.TMIN |
| MIREPLAYRAMWRITEDATA46 | output | CELL44.OUT18.TMIN |
| MIREPLAYRAMWRITEDATA47 | output | CELL41.OUT12.TMIN |
| MIREPLAYRAMWRITEDATA48 | output | CELL44.OUT3.TMIN |
| MIREPLAYRAMWRITEDATA49 | output | CELL44.OUT20.TMIN |
| MIREPLAYRAMWRITEDATA5 | output | CELL41.OUT8.TMIN |
| MIREPLAYRAMWRITEDATA50 | output | CELL43.OUT2.TMIN |
| MIREPLAYRAMWRITEDATA51 | output | CELL43.OUT13.TMIN |
| MIREPLAYRAMWRITEDATA52 | output | CELL43.OUT15.TMIN |
| MIREPLAYRAMWRITEDATA53 | output | CELL41.OUT22.TMIN |
| MIREPLAYRAMWRITEDATA54 | output | CELL44.OUT13.TMIN |
| MIREPLAYRAMWRITEDATA55 | output | CELL43.OUT8.TMIN |
| MIREPLAYRAMWRITEDATA56 | output | CELL42.OUT1.TMIN |
| MIREPLAYRAMWRITEDATA57 | output | CELL44.OUT15.TMIN |
| MIREPLAYRAMWRITEDATA58 | output | CELL43.OUT6.TMIN |
| MIREPLAYRAMWRITEDATA59 | output | CELL44.OUT1.TMIN |
| MIREPLAYRAMWRITEDATA6 | output | CELL40.OUT5.TMIN |
| MIREPLAYRAMWRITEDATA60 | output | CELL43.OUT3.TMIN |
| MIREPLAYRAMWRITEDATA61 | output | CELL42.OUT13.TMIN |
| MIREPLAYRAMWRITEDATA62 | output | CELL44.OUT4.TMIN |
| MIREPLAYRAMWRITEDATA63 | output | CELL43.OUT9.TMIN |
| MIREPLAYRAMWRITEDATA64 | output | CELL44.OUT22.TMIN |
| MIREPLAYRAMWRITEDATA65 | output | CELL43.OUT18.TMIN |
| MIREPLAYRAMWRITEDATA66 | output | CELL44.OUT10.TMIN |
| MIREPLAYRAMWRITEDATA67 | output | CELL42.OUT3.TMIN |
| MIREPLAYRAMWRITEDATA68 | output | CELL44.OUT14.TMIN |
| MIREPLAYRAMWRITEDATA69 | output | CELL47.OUT18.TMIN |
| MIREPLAYRAMWRITEDATA7 | output | CELL41.OUT17.TMIN |
| MIREPLAYRAMWRITEDATA70 | output | CELL46.OUT5.TMIN |
| MIREPLAYRAMWRITEDATA71 | output | CELL44.OUT21.TMIN |
| MIREPLAYRAMWRITEDATA72 | output | CELL45.OUT9.TMIN |
| MIREPLAYRAMWRITEDATA73 | output | CELL46.OUT10.TMIN |
| MIREPLAYRAMWRITEDATA74 | output | CELL45.OUT23.TMIN |
| MIREPLAYRAMWRITEDATA75 | output | CELL46.OUT0.TMIN |
| MIREPLAYRAMWRITEDATA76 | output | CELL45.OUT4.TMIN |
| MIREPLAYRAMWRITEDATA77 | output | CELL43.OUT23.TMIN |
| MIREPLAYRAMWRITEDATA78 | output | CELL45.OUT20.TMIN |
| MIREPLAYRAMWRITEDATA79 | output | CELL46.OUT15.TMIN |
| MIREPLAYRAMWRITEDATA8 | output | CELL41.OUT16.TMIN |
| MIREPLAYRAMWRITEDATA80 | output | CELL45.OUT10.TMIN |
| MIREPLAYRAMWRITEDATA81 | output | CELL46.OUT19.TMIN |
| MIREPLAYRAMWRITEDATA82 | output | CELL47.OUT22.TMIN |
| MIREPLAYRAMWRITEDATA83 | output | CELL46.OUT21.TMIN |
| MIREPLAYRAMWRITEDATA84 | output | CELL43.OUT16.TMIN |
| MIREPLAYRAMWRITEDATA85 | output | CELL45.OUT16.TMIN |
| MIREPLAYRAMWRITEDATA86 | output | CELL47.OUT13.TMIN |
| MIREPLAYRAMWRITEDATA87 | output | CELL45.OUT5.TMIN |
| MIREPLAYRAMWRITEDATA88 | output | CELL46.OUT11.TMIN |
| MIREPLAYRAMWRITEDATA89 | output | CELL45.OUT14.TMIN |
| MIREPLAYRAMWRITEDATA9 | output | CELL40.OUT7.TMIN |
| MIREPLAYRAMWRITEDATA90 | output | CELL46.OUT8.TMIN |
| MIREPLAYRAMWRITEDATA91 | output | CELL45.OUT3.TMIN |
| MIREPLAYRAMWRITEDATA92 | output | CELL46.OUT23.TMIN |
| MIREPLAYRAMWRITEDATA93 | output | CELL46.OUT4.TMIN |
| MIREPLAYRAMWRITEDATA94 | output | CELL47.OUT12.TMIN |
| MIREPLAYRAMWRITEDATA95 | output | CELL48.OUT19.TMIN |
| MIREPLAYRAMWRITEDATA96 | output | CELL45.OUT19.TMIN |
| MIREPLAYRAMWRITEDATA97 | output | CELL45.OUT21.TMIN |
| MIREPLAYRAMWRITEDATA98 | output | CELL46.OUT14.TMIN |
| MIREPLAYRAMWRITEDATA99 | output | CELL49.OUT12.TMIN |
| MIREPLAYRAMWRITEENABLE0 | output | CELL42.OUT6.TMIN |
| MIREPLAYRAMWRITEENABLE1 | output | CELL47.OUT6.TMIN |
| MIREQUESTRAMREADADDRESSA0 | output | CELL3.OUT4.TMIN |
| MIREQUESTRAMREADADDRESSA1 | output | CELL8.OUT15.TMIN |
| MIREQUESTRAMREADADDRESSA2 | output | CELL2.OUT2.TMIN |
| MIREQUESTRAMREADADDRESSA3 | output | CELL1.OUT14.TMIN |
| MIREQUESTRAMREADADDRESSA4 | output | CELL3.OUT12.TMIN |
| MIREQUESTRAMREADADDRESSA5 | output | CELL3.OUT6.TMIN |
| MIREQUESTRAMREADADDRESSA6 | output | CELL1.OUT3.TMIN |
| MIREQUESTRAMREADADDRESSA7 | output | CELL1.OUT11.TMIN |
| MIREQUESTRAMREADADDRESSA8 | output | CELL3.OUT1.TMIN |
| MIREQUESTRAMREADADDRESSB0 | output | CELL8.OUT4.TMIN |
| MIREQUESTRAMREADADDRESSB1 | output | CELL6.OUT3.TMIN |
| MIREQUESTRAMREADADDRESSB2 | output | CELL6.OUT14.TMIN |
| MIREQUESTRAMREADADDRESSB3 | output | CELL8.OUT1.TMIN |
| MIREQUESTRAMREADADDRESSB4 | output | CELL3.OUT17.TMIN |
| MIREQUESTRAMREADADDRESSB5 | output | CELL7.OUT2.TMIN |
| MIREQUESTRAMREADADDRESSB6 | output | CELL6.OUT11.TMIN |
| MIREQUESTRAMREADADDRESSB7 | output | CELL2.OUT0.TMIN |
| MIREQUESTRAMREADADDRESSB8 | output | CELL8.OUT6.TMIN |
| MIREQUESTRAMREADDATA0 | input | CELL0.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA1 | input | CELL0.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA10 | input | CELL0.IMUX.IMUX10.DELAY |
| MIREQUESTRAMREADDATA100 | input | CELL12.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA101 | input | CELL12.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA102 | input | CELL12.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA103 | input | CELL12.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA104 | input | CELL12.IMUX.IMUX4.DELAY |
| MIREQUESTRAMREADDATA105 | input | CELL12.IMUX.IMUX5.DELAY |
| MIREQUESTRAMREADDATA106 | input | CELL12.IMUX.IMUX6.DELAY |
| MIREQUESTRAMREADDATA107 | input | CELL12.IMUX.IMUX7.DELAY |
| MIREQUESTRAMREADDATA108 | input | CELL13.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA109 | input | CELL13.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA11 | input | CELL1.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA110 | input | CELL13.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA111 | input | CELL13.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA112 | input | CELL13.IMUX.IMUX4.DELAY |
| MIREQUESTRAMREADDATA113 | input | CELL13.IMUX.IMUX5.DELAY |
| MIREQUESTRAMREADDATA114 | input | CELL13.IMUX.IMUX6.DELAY |
| MIREQUESTRAMREADDATA115 | input | CELL13.IMUX.IMUX7.DELAY |
| MIREQUESTRAMREADDATA116 | input | CELL14.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA117 | input | CELL14.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA118 | input | CELL14.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA119 | input | CELL14.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA12 | input | CELL1.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA120 | input | CELL14.IMUX.IMUX4.DELAY |
| MIREQUESTRAMREADDATA121 | input | CELL14.IMUX.IMUX5.DELAY |
| MIREQUESTRAMREADDATA122 | input | CELL14.IMUX.IMUX6.DELAY |
| MIREQUESTRAMREADDATA123 | input | CELL14.IMUX.IMUX7.DELAY |
| MIREQUESTRAMREADDATA124 | input | CELL15.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA125 | input | CELL15.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA126 | input | CELL15.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA127 | input | CELL15.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA128 | input | CELL15.IMUX.IMUX4.DELAY |
| MIREQUESTRAMREADDATA129 | input | CELL15.IMUX.IMUX5.DELAY |
| MIREQUESTRAMREADDATA13 | input | CELL1.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA130 | input | CELL15.IMUX.IMUX6.DELAY |
| MIREQUESTRAMREADDATA131 | input | CELL15.IMUX.IMUX7.DELAY |
| MIREQUESTRAMREADDATA132 | input | CELL16.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA133 | input | CELL16.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA134 | input | CELL16.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA135 | input | CELL16.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA136 | input | CELL16.IMUX.IMUX4.DELAY |
| MIREQUESTRAMREADDATA137 | input | CELL16.IMUX.IMUX5.DELAY |
| MIREQUESTRAMREADDATA138 | input | CELL16.IMUX.IMUX6.DELAY |
| MIREQUESTRAMREADDATA139 | input | CELL16.IMUX.IMUX7.DELAY |
| MIREQUESTRAMREADDATA14 | input | CELL1.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA140 | input | CELL17.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA141 | input | CELL17.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA142 | input | CELL17.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA143 | input | CELL17.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA15 | input | CELL1.IMUX.IMUX4.DELAY |
| MIREQUESTRAMREADDATA16 | input | CELL1.IMUX.IMUX5.DELAY |
| MIREQUESTRAMREADDATA17 | input | CELL1.IMUX.IMUX6.DELAY |
| MIREQUESTRAMREADDATA18 | input | CELL1.IMUX.IMUX7.DELAY |
| MIREQUESTRAMREADDATA19 | input | CELL2.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA2 | input | CELL0.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA20 | input | CELL2.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA21 | input | CELL2.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA22 | input | CELL2.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA23 | input | CELL2.IMUX.IMUX4.DELAY |
| MIREQUESTRAMREADDATA24 | input | CELL2.IMUX.IMUX5.DELAY |
| MIREQUESTRAMREADDATA25 | input | CELL2.IMUX.IMUX6.DELAY |
| MIREQUESTRAMREADDATA26 | input | CELL2.IMUX.IMUX7.DELAY |
| MIREQUESTRAMREADDATA27 | input | CELL2.IMUX.IMUX47.DELAY |
| MIREQUESTRAMREADDATA28 | input | CELL3.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA29 | input | CELL3.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA3 | input | CELL0.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA30 | input | CELL3.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA31 | input | CELL3.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA32 | input | CELL3.IMUX.IMUX4.DELAY |
| MIREQUESTRAMREADDATA33 | input | CELL3.IMUX.IMUX5.DELAY |
| MIREQUESTRAMREADDATA34 | input | CELL3.IMUX.IMUX6.DELAY |
| MIREQUESTRAMREADDATA35 | input | CELL3.IMUX.IMUX7.DELAY |
| MIREQUESTRAMREADDATA36 | input | CELL4.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA37 | input | CELL4.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA38 | input | CELL4.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA39 | input | CELL4.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA4 | input | CELL0.IMUX.IMUX4.DELAY |
| MIREQUESTRAMREADDATA40 | input | CELL4.IMUX.IMUX4.DELAY |
| MIREQUESTRAMREADDATA41 | input | CELL4.IMUX.IMUX5.DELAY |
| MIREQUESTRAMREADDATA42 | input | CELL4.IMUX.IMUX6.DELAY |
| MIREQUESTRAMREADDATA43 | input | CELL4.IMUX.IMUX7.DELAY |
| MIREQUESTRAMREADDATA44 | input | CELL5.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA45 | input | CELL5.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA46 | input | CELL5.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA47 | input | CELL5.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA48 | input | CELL5.IMUX.IMUX4.DELAY |
| MIREQUESTRAMREADDATA49 | input | CELL5.IMUX.IMUX5.DELAY |
| MIREQUESTRAMREADDATA5 | input | CELL0.IMUX.IMUX5.DELAY |
| MIREQUESTRAMREADDATA50 | input | CELL5.IMUX.IMUX6.DELAY |
| MIREQUESTRAMREADDATA51 | input | CELL5.IMUX.IMUX7.DELAY |
| MIREQUESTRAMREADDATA52 | input | CELL6.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA53 | input | CELL6.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA54 | input | CELL6.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA55 | input | CELL6.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA56 | input | CELL6.IMUX.IMUX4.DELAY |
| MIREQUESTRAMREADDATA57 | input | CELL6.IMUX.IMUX5.DELAY |
| MIREQUESTRAMREADDATA58 | input | CELL6.IMUX.IMUX6.DELAY |
| MIREQUESTRAMREADDATA59 | input | CELL6.IMUX.IMUX7.DELAY |
| MIREQUESTRAMREADDATA6 | input | CELL0.IMUX.IMUX6.DELAY |
| MIREQUESTRAMREADDATA60 | input | CELL7.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA61 | input | CELL7.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA62 | input | CELL7.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA63 | input | CELL7.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA64 | input | CELL7.IMUX.IMUX4.DELAY |
| MIREQUESTRAMREADDATA65 | input | CELL7.IMUX.IMUX5.DELAY |
| MIREQUESTRAMREADDATA66 | input | CELL7.IMUX.IMUX6.DELAY |
| MIREQUESTRAMREADDATA67 | input | CELL7.IMUX.IMUX7.DELAY |
| MIREQUESTRAMREADDATA68 | input | CELL8.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA69 | input | CELL8.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA7 | input | CELL0.IMUX.IMUX7.DELAY |
| MIREQUESTRAMREADDATA70 | input | CELL8.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA71 | input | CELL8.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA72 | input | CELL8.IMUX.IMUX4.DELAY |
| MIREQUESTRAMREADDATA73 | input | CELL8.IMUX.IMUX5.DELAY |
| MIREQUESTRAMREADDATA74 | input | CELL8.IMUX.IMUX6.DELAY |
| MIREQUESTRAMREADDATA75 | input | CELL8.IMUX.IMUX7.DELAY |
| MIREQUESTRAMREADDATA76 | input | CELL9.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA77 | input | CELL9.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA78 | input | CELL9.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA79 | input | CELL9.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA8 | input | CELL0.IMUX.IMUX8.DELAY |
| MIREQUESTRAMREADDATA80 | input | CELL9.IMUX.IMUX4.DELAY |
| MIREQUESTRAMREADDATA81 | input | CELL9.IMUX.IMUX5.DELAY |
| MIREQUESTRAMREADDATA82 | input | CELL9.IMUX.IMUX6.DELAY |
| MIREQUESTRAMREADDATA83 | input | CELL9.IMUX.IMUX7.DELAY |
| MIREQUESTRAMREADDATA84 | input | CELL10.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA85 | input | CELL10.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA86 | input | CELL10.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA87 | input | CELL10.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA88 | input | CELL10.IMUX.IMUX4.DELAY |
| MIREQUESTRAMREADDATA89 | input | CELL10.IMUX.IMUX5.DELAY |
| MIREQUESTRAMREADDATA9 | input | CELL0.IMUX.IMUX9.DELAY |
| MIREQUESTRAMREADDATA90 | input | CELL10.IMUX.IMUX6.DELAY |
| MIREQUESTRAMREADDATA91 | input | CELL10.IMUX.IMUX7.DELAY |
| MIREQUESTRAMREADDATA92 | input | CELL11.IMUX.IMUX0.DELAY |
| MIREQUESTRAMREADDATA93 | input | CELL11.IMUX.IMUX1.DELAY |
| MIREQUESTRAMREADDATA94 | input | CELL11.IMUX.IMUX2.DELAY |
| MIREQUESTRAMREADDATA95 | input | CELL11.IMUX.IMUX3.DELAY |
| MIREQUESTRAMREADDATA96 | input | CELL11.IMUX.IMUX4.DELAY |
| MIREQUESTRAMREADDATA97 | input | CELL11.IMUX.IMUX5.DELAY |
| MIREQUESTRAMREADDATA98 | input | CELL11.IMUX.IMUX6.DELAY |
| MIREQUESTRAMREADDATA99 | input | CELL11.IMUX.IMUX7.DELAY |
| MIREQUESTRAMREADENABLE0 | output | CELL2.OUT1.TMIN |
| MIREQUESTRAMREADENABLE1 | output | CELL2.OUT4.TMIN |
| MIREQUESTRAMREADENABLE2 | output | CELL7.OUT4.TMIN |
| MIREQUESTRAMREADENABLE3 | output | CELL7.OUT12.TMIN |
| MIREQUESTRAMWRITEADDRESSA0 | output | CELL2.OUT20.TMIN |
| MIREQUESTRAMWRITEADDRESSA1 | output | CELL3.OUT18.TMIN |
| MIREQUESTRAMWRITEADDRESSA2 | output | CELL3.OUT16.TMIN |
| MIREQUESTRAMWRITEADDRESSA3 | output | CELL3.OUT0.TMIN |
| MIREQUESTRAMWRITEADDRESSA4 | output | CELL3.OUT23.TMIN |
| MIREQUESTRAMWRITEADDRESSA5 | output | CELL1.OUT7.TMIN |
| MIREQUESTRAMWRITEADDRESSA6 | output | CELL1.OUT2.TMIN |
| MIREQUESTRAMWRITEADDRESSA7 | output | CELL3.OUT15.TMIN |
| MIREQUESTRAMWRITEADDRESSA8 | output | CELL1.OUT21.TMIN |
| MIREQUESTRAMWRITEADDRESSB0 | output | CELL8.OUT18.TMIN |
| MIREQUESTRAMWRITEADDRESSB1 | output | CELL6.OUT21.TMIN |
| MIREQUESTRAMWRITEADDRESSB2 | output | CELL6.OUT2.TMIN |
| MIREQUESTRAMWRITEADDRESSB3 | output | CELL7.OUT20.TMIN |
| MIREQUESTRAMWRITEADDRESSB4 | output | CELL8.OUT23.TMIN |
| MIREQUESTRAMWRITEADDRESSB5 | output | CELL6.OUT7.TMIN |
| MIREQUESTRAMWRITEADDRESSB6 | output | CELL8.OUT12.TMIN |
| MIREQUESTRAMWRITEADDRESSB7 | output | CELL8.OUT16.TMIN |
| MIREQUESTRAMWRITEADDRESSB8 | output | CELL8.OUT0.TMIN |
| MIREQUESTRAMWRITEDATA0 | output | CELL1.OUT9.TMIN |
| MIREQUESTRAMWRITEDATA1 | output | CELL0.OUT5.TMIN |
| MIREQUESTRAMWRITEDATA10 | output | CELL1.OUT19.TMIN |
| MIREQUESTRAMWRITEDATA100 | output | CELL5.OUT23.TMIN |
| MIREQUESTRAMWRITEDATA101 | output | CELL7.OUT14.TMIN |
| MIREQUESTRAMWRITEDATA102 | output | CELL6.OUT16.TMIN |
| MIREQUESTRAMWRITEDATA103 | output | CELL5.OUT2.TMIN |
| MIREQUESTRAMWRITEDATA104 | output | CELL7.OUT15.TMIN |
| MIREQUESTRAMWRITEDATA105 | output | CELL6.OUT15.TMIN |
| MIREQUESTRAMWRITEDATA106 | output | CELL6.OUT18.TMIN |
| MIREQUESTRAMWRITEDATA107 | output | CELL8.OUT22.TMIN |
| MIREQUESTRAMWRITEDATA108 | output | CELL6.OUT10.TMIN |
| MIREQUESTRAMWRITEDATA109 | output | CELL5.OUT21.TMIN |
| MIREQUESTRAMWRITEDATA11 | output | CELL1.OUT20.TMIN |
| MIREQUESTRAMWRITEDATA110 | output | CELL9.OUT12.TMIN |
| MIREQUESTRAMWRITEDATA111 | output | CELL8.OUT20.TMIN |
| MIREQUESTRAMWRITEDATA112 | output | CELL5.OUT19.TMIN |
| MIREQUESTRAMWRITEDATA113 | output | CELL8.OUT13.TMIN |
| MIREQUESTRAMWRITEDATA114 | output | CELL9.OUT14.TMIN |
| MIREQUESTRAMWRITEDATA115 | output | CELL9.OUT11.TMIN |
| MIREQUESTRAMWRITEDATA116 | output | CELL7.OUT9.TMIN |
| MIREQUESTRAMWRITEDATA117 | output | CELL8.OUT10.TMIN |
| MIREQUESTRAMWRITEDATA118 | output | CELL9.OUT8.TMIN |
| MIREQUESTRAMWRITEDATA119 | output | CELL9.OUT10.TMIN |
| MIREQUESTRAMWRITEDATA12 | output | CELL1.OUT4.TMIN |
| MIREQUESTRAMWRITEDATA120 | output | CELL8.OUT11.TMIN |
| MIREQUESTRAMWRITEDATA121 | output | CELL7.OUT5.TMIN |
| MIREQUESTRAMWRITEDATA122 | output | CELL8.OUT14.TMIN |
| MIREQUESTRAMWRITEDATA123 | output | CELL9.OUT9.TMIN |
| MIREQUESTRAMWRITEDATA124 | output | CELL8.OUT8.TMIN |
| MIREQUESTRAMWRITEDATA125 | output | CELL8.OUT9.TMIN |
| MIREQUESTRAMWRITEDATA126 | output | CELL6.OUT22.TMIN |
| MIREQUESTRAMWRITEDATA127 | output | CELL9.OUT2.TMIN |
| MIREQUESTRAMWRITEDATA128 | output | CELL9.OUT13.TMIN |
| MIREQUESTRAMWRITEDATA129 | output | CELL9.OUT3.TMIN |
| MIREQUESTRAMWRITEDATA13 | output | CELL2.OUT22.TMIN |
| MIREQUESTRAMWRITEDATA130 | output | CELL9.OUT0.TMIN |
| MIREQUESTRAMWRITEDATA131 | output | CELL9.OUT5.TMIN |
| MIREQUESTRAMWRITEDATA132 | output | CELL9.OUT7.TMIN |
| MIREQUESTRAMWRITEDATA133 | output | CELL7.OUT23.TMIN |
| MIREQUESTRAMWRITEDATA134 | output | CELL9.OUT1.TMIN |
| MIREQUESTRAMWRITEDATA135 | output | CELL8.OUT3.TMIN |
| MIREQUESTRAMWRITEDATA136 | output | CELL8.OUT2.TMIN |
| MIREQUESTRAMWRITEDATA137 | output | CELL8.OUT5.TMIN |
| MIREQUESTRAMWRITEDATA138 | output | CELL9.OUT15.TMIN |
| MIREQUESTRAMWRITEDATA139 | output | CELL7.OUT3.TMIN |
| MIREQUESTRAMWRITEDATA14 | output | CELL1.OUT8.TMIN |
| MIREQUESTRAMWRITEDATA140 | output | CELL8.OUT7.TMIN |
| MIREQUESTRAMWRITEDATA141 | output | CELL9.OUT6.TMIN |
| MIREQUESTRAMWRITEDATA142 | output | CELL9.OUT4.TMIN |
| MIREQUESTRAMWRITEDATA143 | output | CELL8.OUT21.TMIN |
| MIREQUESTRAMWRITEDATA15 | output | CELL0.OUT1.TMIN |
| MIREQUESTRAMWRITEDATA16 | output | CELL0.OUT17.TMIN |
| MIREQUESTRAMWRITEDATA17 | output | CELL2.OUT13.TMIN |
| MIREQUESTRAMWRITEDATA18 | output | CELL1.OUT15.TMIN |
| MIREQUESTRAMWRITEDATA19 | output | CELL0.OUT19.TMIN |
| MIREQUESTRAMWRITEDATA2 | output | CELL0.OUT3.TMIN |
| MIREQUESTRAMWRITEDATA20 | output | CELL4.OUT11.TMIN |
| MIREQUESTRAMWRITEDATA21 | output | CELL0.OUT4.TMIN |
| MIREQUESTRAMWRITEDATA22 | output | CELL1.OUT5.TMIN |
| MIREQUESTRAMWRITEDATA23 | output | CELL2.OUT8.TMIN |
| MIREQUESTRAMWRITEDATA24 | output | CELL2.OUT18.TMIN |
| MIREQUESTRAMWRITEDATA25 | output | CELL0.OUT18.TMIN |
| MIREQUESTRAMWRITEDATA26 | output | CELL0.OUT20.TMIN |
| MIREQUESTRAMWRITEDATA27 | output | CELL1.OUT16.TMIN |
| MIREQUESTRAMWRITEDATA28 | output | CELL1.OUT23.TMIN |
| MIREQUESTRAMWRITEDATA29 | output | CELL0.OUT16.TMIN |
| MIREQUESTRAMWRITEDATA3 | output | CELL0.OUT7.TMIN |
| MIREQUESTRAMWRITEDATA30 | output | CELL0.OUT23.TMIN |
| MIREQUESTRAMWRITEDATA31 | output | CELL2.OUT9.TMIN |
| MIREQUESTRAMWRITEDATA32 | output | CELL2.OUT14.TMIN |
| MIREQUESTRAMWRITEDATA33 | output | CELL3.OUT19.TMIN |
| MIREQUESTRAMWRITEDATA34 | output | CELL0.OUT21.TMIN |
| MIREQUESTRAMWRITEDATA35 | output | CELL1.OUT18.TMIN |
| MIREQUESTRAMWRITEDATA36 | output | CELL1.OUT12.TMIN |
| MIREQUESTRAMWRITEDATA37 | output | CELL1.OUT10.TMIN |
| MIREQUESTRAMWRITEDATA38 | output | CELL2.OUT5.TMIN |
| MIREQUESTRAMWRITEDATA39 | output | CELL3.OUT13.TMIN |
| MIREQUESTRAMWRITEDATA4 | output | CELL1.OUT0.TMIN |
| MIREQUESTRAMWRITEDATA40 | output | CELL3.OUT11.TMIN |
| MIREQUESTRAMWRITEDATA41 | output | CELL3.OUT9.TMIN |
| MIREQUESTRAMWRITEDATA42 | output | CELL3.OUT22.TMIN |
| MIREQUESTRAMWRITEDATA43 | output | CELL3.OUT5.TMIN |
| MIREQUESTRAMWRITEDATA44 | output | CELL3.OUT20.TMIN |
| MIREQUESTRAMWRITEDATA45 | output | CELL4.OUT9.TMIN |
| MIREQUESTRAMWRITEDATA46 | output | CELL1.OUT22.TMIN |
| MIREQUESTRAMWRITEDATA47 | output | CELL4.OUT15.TMIN |
| MIREQUESTRAMWRITEDATA48 | output | CELL4.OUT8.TMIN |
| MIREQUESTRAMWRITEDATA49 | output | CELL4.OUT12.TMIN |
| MIREQUESTRAMWRITEDATA5 | output | CELL1.OUT1.TMIN |
| MIREQUESTRAMWRITEDATA50 | output | CELL4.OUT5.TMIN |
| MIREQUESTRAMWRITEDATA51 | output | CELL4.OUT14.TMIN |
| MIREQUESTRAMWRITEDATA52 | output | CELL3.OUT7.TMIN |
| MIREQUESTRAMWRITEDATA53 | output | CELL4.OUT13.TMIN |
| MIREQUESTRAMWRITEDATA54 | output | CELL1.OUT13.TMIN |
| MIREQUESTRAMWRITEDATA55 | output | CELL6.OUT8.TMIN |
| MIREQUESTRAMWRITEDATA56 | output | CELL4.OUT0.TMIN |
| MIREQUESTRAMWRITEDATA57 | output | CELL5.OUT6.TMIN |
| MIREQUESTRAMWRITEDATA58 | output | CELL3.OUT14.TMIN |
| MIREQUESTRAMWRITEDATA59 | output | CELL3.OUT3.TMIN |
| MIREQUESTRAMWRITEDATA6 | output | CELL1.OUT6.TMIN |
| MIREQUESTRAMWRITEDATA60 | output | CELL3.OUT2.TMIN |
| MIREQUESTRAMWRITEDATA61 | output | CELL3.OUT10.TMIN |
| MIREQUESTRAMWRITEDATA62 | output | CELL2.OUT3.TMIN |
| MIREQUESTRAMWRITEDATA63 | output | CELL2.OUT15.TMIN |
| MIREQUESTRAMWRITEDATA64 | output | CELL5.OUT5.TMIN |
| MIREQUESTRAMWRITEDATA65 | output | CELL4.OUT4.TMIN |
| MIREQUESTRAMWRITEDATA66 | output | CELL4.OUT10.TMIN |
| MIREQUESTRAMWRITEDATA67 | output | CELL3.OUT21.TMIN |
| MIREQUESTRAMWRITEDATA68 | output | CELL2.OUT23.TMIN |
| MIREQUESTRAMWRITEDATA69 | output | CELL4.OUT2.TMIN |
| MIREQUESTRAMWRITEDATA7 | output | CELL0.OUT6.TMIN |
| MIREQUESTRAMWRITEDATA70 | output | CELL4.OUT1.TMIN |
| MIREQUESTRAMWRITEDATA71 | output | CELL5.OUT20.TMIN |
| MIREQUESTRAMWRITEDATA72 | output | CELL4.OUT7.TMIN |
| MIREQUESTRAMWRITEDATA73 | output | CELL6.OUT0.TMIN |
| MIREQUESTRAMWRITEDATA74 | output | CELL6.OUT17.TMIN |
| MIREQUESTRAMWRITEDATA75 | output | CELL6.OUT9.TMIN |
| MIREQUESTRAMWRITEDATA76 | output | CELL4.OUT3.TMIN |
| MIREQUESTRAMWRITEDATA77 | output | CELL6.OUT23.TMIN |
| MIREQUESTRAMWRITEDATA78 | output | CELL5.OUT7.TMIN |
| MIREQUESTRAMWRITEDATA79 | output | CELL7.OUT8.TMIN |
| MIREQUESTRAMWRITEDATA8 | output | CELL0.OUT2.TMIN |
| MIREQUESTRAMWRITEDATA80 | output | CELL3.OUT8.TMIN |
| MIREQUESTRAMWRITEDATA81 | output | CELL7.OUT22.TMIN |
| MIREQUESTRAMWRITEDATA82 | output | CELL5.OUT3.TMIN |
| MIREQUESTRAMWRITEDATA83 | output | CELL5.OUT1.TMIN |
| MIREQUESTRAMWRITEDATA84 | output | CELL7.OUT18.TMIN |
| MIREQUESTRAMWRITEDATA85 | output | CELL4.OUT6.TMIN |
| MIREQUESTRAMWRITEDATA86 | output | CELL5.OUT18.TMIN |
| MIREQUESTRAMWRITEDATA87 | output | CELL8.OUT19.TMIN |
| MIREQUESTRAMWRITEDATA88 | output | CELL5.OUT4.TMIN |
| MIREQUESTRAMWRITEDATA89 | output | CELL6.OUT6.TMIN |
| MIREQUESTRAMWRITEDATA9 | output | CELL1.OUT17.TMIN |
| MIREQUESTRAMWRITEDATA90 | output | CELL5.OUT17.TMIN |
| MIREQUESTRAMWRITEDATA91 | output | CELL6.OUT1.TMIN |
| MIREQUESTRAMWRITEDATA92 | output | CELL6.OUT13.TMIN |
| MIREQUESTRAMWRITEDATA93 | output | CELL5.OUT16.TMIN |
| MIREQUESTRAMWRITEDATA94 | output | CELL6.OUT19.TMIN |
| MIREQUESTRAMWRITEDATA95 | output | CELL7.OUT13.TMIN |
| MIREQUESTRAMWRITEDATA96 | output | CELL6.OUT4.TMIN |
| MIREQUESTRAMWRITEDATA97 | output | CELL6.OUT5.TMIN |
| MIREQUESTRAMWRITEDATA98 | output | CELL6.OUT12.TMIN |
| MIREQUESTRAMWRITEDATA99 | output | CELL6.OUT20.TMIN |
| MIREQUESTRAMWRITEENABLE0 | output | CELL2.OUT10.TMIN |
| MIREQUESTRAMWRITEENABLE1 | output | CELL2.OUT11.TMIN |
| MIREQUESTRAMWRITEENABLE2 | output | CELL7.OUT10.TMIN |
| MIREQUESTRAMWRITEENABLE3 | output | CELL7.OUT11.TMIN |
| PCIECQNPREQ | input | CELL0.IMUX.IMUX16.DELAY |
| PCIECQNPREQCOUNT0 | output | CELL0.OUT12.TMIN |
| PCIECQNPREQCOUNT1 | output | CELL0.OUT13.TMIN |
| PCIECQNPREQCOUNT2 | output | CELL0.OUT14.TMIN |
| PCIECQNPREQCOUNT3 | output | CELL2.OUT17.TMIN |
| PCIECQNPREQCOUNT4 | output | CELL4.OUT20.TMIN |
| PCIECQNPREQCOUNT5 | output | CELL4.OUT21.TMIN |
| PCIERQSEQNUM0 | output | CELL12.OUT9.TMIN |
| PCIERQSEQNUM1 | output | CELL12.OUT10.TMIN |
| PCIERQSEQNUM2 | output | CELL12.OUT11.TMIN |
| PCIERQSEQNUM3 | output | CELL13.OUT8.TMIN |
| PCIERQSEQNUMVLD | output | CELL13.OUT9.TMIN |
| PCIERQTAG0 | output | CELL13.OUT10.TMIN |
| PCIERQTAG1 | output | CELL13.OUT11.TMIN |
| PCIERQTAG2 | output | CELL14.OUT8.TMIN |
| PCIERQTAG3 | output | CELL14.OUT9.TMIN |
| PCIERQTAG4 | output | CELL14.OUT10.TMIN |
| PCIERQTAG5 | output | CELL14.OUT11.TMIN |
| PCIERQTAGAV0 | output | CELL17.OUT16.TMIN |
| PCIERQTAGAV1 | output | CELL17.OUT17.TMIN |
| PCIERQTAGVLD | output | CELL15.OUT15.TMIN |
| PCIETFCNPDAV0 | output | CELL15.OUT18.TMIN |
| PCIETFCNPDAV1 | output | CELL17.OUT14.TMIN |
| PCIETFCNPHAV0 | output | CELL15.OUT16.TMIN |
| PCIETFCNPHAV1 | output | CELL15.OUT17.TMIN |
| PIPECLK | input | CELL75.IMUX.CLK0 |
| PIPEEQFS0 | input | CELL74.IMUX.IMUX4.DELAY |
| PIPEEQFS1 | input | CELL74.IMUX.IMUX5.DELAY |
| PIPEEQFS2 | input | CELL74.IMUX.IMUX6.DELAY |
| PIPEEQFS3 | input | CELL74.IMUX.IMUX7.DELAY |
| PIPEEQFS4 | input | CELL73.IMUX.IMUX4.DELAY |
| PIPEEQFS5 | input | CELL73.IMUX.IMUX5.DELAY |
| PIPEEQLF0 | input | CELL73.IMUX.IMUX6.DELAY |
| PIPEEQLF1 | input | CELL73.IMUX.IMUX7.DELAY |
| PIPEEQLF2 | input | CELL72.IMUX.IMUX4.DELAY |
| PIPEEQLF3 | input | CELL72.IMUX.IMUX5.DELAY |
| PIPEEQLF4 | input | CELL72.IMUX.IMUX6.DELAY |
| PIPEEQLF5 | input | CELL72.IMUX.IMUX7.DELAY |
| PIPERESETN | input | CELL15.IMUX.IMUX23.DELAY |
| PIPERX0CHARISK0 | input | CELL97.IMUX.IMUX16.DELAY |
| PIPERX0CHARISK1 | input | CELL95.IMUX.IMUX16.DELAY |
| PIPERX0DATA0 | input | CELL97.IMUX.IMUX37.DELAY |
| PIPERX0DATA1 | input | CELL97.IMUX.IMUX36.DELAY |
| PIPERX0DATA10 | input | CELL95.IMUX.IMUX33.DELAY |
| PIPERX0DATA11 | input | CELL95.IMUX.IMUX32.DELAY |
| PIPERX0DATA12 | input | CELL94.IMUX.IMUX39.DELAY |
| PIPERX0DATA13 | input | CELL94.IMUX.IMUX38.DELAY |
| PIPERX0DATA14 | input | CELL94.IMUX.IMUX35.DELAY |
| PIPERX0DATA15 | input | CELL94.IMUX.IMUX34.DELAY |
| PIPERX0DATA16 | input | CELL93.IMUX.IMUX37.DELAY |
| PIPERX0DATA17 | input | CELL93.IMUX.IMUX36.DELAY |
| PIPERX0DATA18 | input | CELL93.IMUX.IMUX33.DELAY |
| PIPERX0DATA19 | input | CELL93.IMUX.IMUX32.DELAY |
| PIPERX0DATA2 | input | CELL97.IMUX.IMUX33.DELAY |
| PIPERX0DATA20 | input | CELL92.IMUX.IMUX39.DELAY |
| PIPERX0DATA21 | input | CELL92.IMUX.IMUX38.DELAY |
| PIPERX0DATA22 | input | CELL92.IMUX.IMUX35.DELAY |
| PIPERX0DATA23 | input | CELL92.IMUX.IMUX34.DELAY |
| PIPERX0DATA24 | input | CELL91.IMUX.IMUX37.DELAY |
| PIPERX0DATA25 | input | CELL91.IMUX.IMUX36.DELAY |
| PIPERX0DATA26 | input | CELL91.IMUX.IMUX33.DELAY |
| PIPERX0DATA27 | input | CELL91.IMUX.IMUX32.DELAY |
| PIPERX0DATA28 | input | CELL90.IMUX.IMUX39.DELAY |
| PIPERX0DATA29 | input | CELL90.IMUX.IMUX38.DELAY |
| PIPERX0DATA3 | input | CELL97.IMUX.IMUX32.DELAY |
| PIPERX0DATA30 | input | CELL90.IMUX.IMUX35.DELAY |
| PIPERX0DATA31 | input | CELL90.IMUX.IMUX34.DELAY |
| PIPERX0DATA4 | input | CELL96.IMUX.IMUX39.DELAY |
| PIPERX0DATA5 | input | CELL96.IMUX.IMUX38.DELAY |
| PIPERX0DATA6 | input | CELL96.IMUX.IMUX35.DELAY |
| PIPERX0DATA7 | input | CELL96.IMUX.IMUX34.DELAY |
| PIPERX0DATA8 | input | CELL95.IMUX.IMUX37.DELAY |
| PIPERX0DATA9 | input | CELL95.IMUX.IMUX36.DELAY |
| PIPERX0DATAVALID | input | CELL91.IMUX.IMUX23.DELAY |
| PIPERX0ELECIDLE | input | CELL95.IMUX.IMUX41.DELAY |
| PIPERX0EQCONTROL0 | output | CELL50.OUT1.TMIN |
| PIPERX0EQCONTROL1 | output | CELL50.OUT3.TMIN |
| PIPERX0EQDONE | input | CELL85.IMUX.IMUX0.DELAY |
| PIPERX0EQLPADAPTDONE | input | CELL83.IMUX.IMUX0.DELAY |
| PIPERX0EQLPLFFS0 | output | CELL64.OUT5.TMIN |
| PIPERX0EQLPLFFS1 | output | CELL64.OUT7.TMIN |
| PIPERX0EQLPLFFS2 | output | CELL65.OUT1.TMIN |
| PIPERX0EQLPLFFS3 | output | CELL65.OUT3.TMIN |
| PIPERX0EQLPLFFS4 | output | CELL65.OUT5.TMIN |
| PIPERX0EQLPLFFS5 | output | CELL65.OUT7.TMIN |
| PIPERX0EQLPLFFSSEL | input | CELL50.IMUX.IMUX0.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET0 | input | CELL50.IMUX.IMUX8.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET1 | input | CELL50.IMUX.IMUX9.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET10 | input | CELL50.IMUX.IMUX18.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET11 | input | CELL50.IMUX.IMUX19.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET12 | input | CELL50.IMUX.IMUX20.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET13 | input | CELL50.IMUX.IMUX21.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET14 | input | CELL50.IMUX.IMUX22.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET15 | input | CELL50.IMUX.IMUX23.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET16 | input | CELL51.IMUX.IMUX0.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET17 | input | CELL51.IMUX.IMUX1.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET2 | input | CELL50.IMUX.IMUX10.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET3 | input | CELL50.IMUX.IMUX11.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET4 | input | CELL50.IMUX.IMUX12.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET5 | input | CELL50.IMUX.IMUX13.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET6 | input | CELL50.IMUX.IMUX14.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET7 | input | CELL50.IMUX.IMUX15.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET8 | input | CELL50.IMUX.IMUX16.DELAY |
| PIPERX0EQLPNEWTXCOEFFORPRESET9 | input | CELL50.IMUX.IMUX17.DELAY |
| PIPERX0EQLPTXPRESET0 | output | CELL56.OUT10.TMIN |
| PIPERX0EQLPTXPRESET1 | output | CELL56.OUT12.TMIN |
| PIPERX0EQLPTXPRESET2 | output | CELL57.OUT10.TMIN |
| PIPERX0EQLPTXPRESET3 | output | CELL57.OUT12.TMIN |
| PIPERX0EQPRESET0 | output | CELL50.OUT20.TMIN |
| PIPERX0EQPRESET1 | output | CELL50.OUT21.TMIN |
| PIPERX0EQPRESET2 | output | CELL51.OUT1.TMIN |
| PIPERX0PHYSTATUS | input | CELL96.IMUX.IMUX45.DELAY |
| PIPERX0POLARITY | output | CELL94.OUT1.TMIN |
| PIPERX0STARTBLOCK | input | CELL91.IMUX.IMUX22.DELAY |
| PIPERX0STATUS0 | input | CELL95.IMUX.IMUX44.DELAY |
| PIPERX0STATUS1 | input | CELL95.IMUX.IMUX43.DELAY |
| PIPERX0STATUS2 | input | CELL95.IMUX.IMUX42.DELAY |
| PIPERX0SYNCHEADER0 | input | CELL91.IMUX.IMUX21.DELAY |
| PIPERX0SYNCHEADER1 | input | CELL91.IMUX.IMUX20.DELAY |
| PIPERX0VALID | input | CELL96.IMUX.IMUX40.DELAY |
| PIPERX1CHARISK0 | input | CELL96.IMUX.IMUX16.DELAY |
| PIPERX1CHARISK1 | input | CELL94.IMUX.IMUX16.DELAY |
| PIPERX1DATA0 | input | CELL96.IMUX.IMUX37.DELAY |
| PIPERX1DATA1 | input | CELL96.IMUX.IMUX36.DELAY |
| PIPERX1DATA10 | input | CELL94.IMUX.IMUX33.DELAY |
| PIPERX1DATA11 | input | CELL94.IMUX.IMUX32.DELAY |
| PIPERX1DATA12 | input | CELL93.IMUX.IMUX39.DELAY |
| PIPERX1DATA13 | input | CELL93.IMUX.IMUX38.DELAY |
| PIPERX1DATA14 | input | CELL93.IMUX.IMUX35.DELAY |
| PIPERX1DATA15 | input | CELL93.IMUX.IMUX34.DELAY |
| PIPERX1DATA16 | input | CELL92.IMUX.IMUX37.DELAY |
| PIPERX1DATA17 | input | CELL92.IMUX.IMUX36.DELAY |
| PIPERX1DATA18 | input | CELL92.IMUX.IMUX33.DELAY |
| PIPERX1DATA19 | input | CELL92.IMUX.IMUX32.DELAY |
| PIPERX1DATA2 | input | CELL96.IMUX.IMUX33.DELAY |
| PIPERX1DATA20 | input | CELL91.IMUX.IMUX39.DELAY |
| PIPERX1DATA21 | input | CELL91.IMUX.IMUX38.DELAY |
| PIPERX1DATA22 | input | CELL91.IMUX.IMUX35.DELAY |
| PIPERX1DATA23 | input | CELL91.IMUX.IMUX34.DELAY |
| PIPERX1DATA24 | input | CELL90.IMUX.IMUX37.DELAY |
| PIPERX1DATA25 | input | CELL90.IMUX.IMUX36.DELAY |
| PIPERX1DATA26 | input | CELL90.IMUX.IMUX33.DELAY |
| PIPERX1DATA27 | input | CELL90.IMUX.IMUX32.DELAY |
| PIPERX1DATA28 | input | CELL89.IMUX.IMUX39.DELAY |
| PIPERX1DATA29 | input | CELL89.IMUX.IMUX38.DELAY |
| PIPERX1DATA3 | input | CELL96.IMUX.IMUX32.DELAY |
| PIPERX1DATA30 | input | CELL89.IMUX.IMUX35.DELAY |
| PIPERX1DATA31 | input | CELL89.IMUX.IMUX34.DELAY |
| PIPERX1DATA4 | input | CELL95.IMUX.IMUX39.DELAY |
| PIPERX1DATA5 | input | CELL95.IMUX.IMUX38.DELAY |
| PIPERX1DATA6 | input | CELL95.IMUX.IMUX35.DELAY |
| PIPERX1DATA7 | input | CELL95.IMUX.IMUX34.DELAY |
| PIPERX1DATA8 | input | CELL94.IMUX.IMUX37.DELAY |
| PIPERX1DATA9 | input | CELL94.IMUX.IMUX36.DELAY |
| PIPERX1DATAVALID | input | CELL90.IMUX.IMUX23.DELAY |
| PIPERX1ELECIDLE | input | CELL94.IMUX.IMUX41.DELAY |
| PIPERX1EQCONTROL0 | output | CELL50.OUT5.TMIN |
| PIPERX1EQCONTROL1 | output | CELL50.OUT7.TMIN |
| PIPERX1EQDONE | input | CELL85.IMUX.IMUX1.DELAY |
| PIPERX1EQLPADAPTDONE | input | CELL83.IMUX.IMUX1.DELAY |
| PIPERX1EQLPLFFS0 | output | CELL66.OUT1.TMIN |
| PIPERX1EQLPLFFS1 | output | CELL66.OUT3.TMIN |
| PIPERX1EQLPLFFS2 | output | CELL66.OUT5.TMIN |
| PIPERX1EQLPLFFS3 | output | CELL66.OUT7.TMIN |
| PIPERX1EQLPLFFS4 | output | CELL67.OUT1.TMIN |
| PIPERX1EQLPLFFS5 | output | CELL67.OUT8.TMIN |
| PIPERX1EQLPLFFSSEL | input | CELL50.IMUX.IMUX1.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET0 | input | CELL51.IMUX.IMUX2.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET1 | input | CELL51.IMUX.IMUX3.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET10 | input | CELL54.IMUX.IMUX0.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET11 | input | CELL54.IMUX.IMUX1.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET12 | input | CELL54.IMUX.IMUX2.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET13 | input | CELL54.IMUX.IMUX3.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET14 | input | CELL55.IMUX.IMUX0.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET15 | input | CELL55.IMUX.IMUX1.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET16 | input | CELL55.IMUX.IMUX2.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET17 | input | CELL55.IMUX.IMUX3.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET2 | input | CELL52.IMUX.IMUX0.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET3 | input | CELL52.IMUX.IMUX1.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET4 | input | CELL52.IMUX.IMUX2.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET5 | input | CELL52.IMUX.IMUX3.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET6 | input | CELL53.IMUX.IMUX0.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET7 | input | CELL53.IMUX.IMUX1.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET8 | input | CELL53.IMUX.IMUX2.DELAY |
| PIPERX1EQLPNEWTXCOEFFORPRESET9 | input | CELL53.IMUX.IMUX3.DELAY |
| PIPERX1EQLPTXPRESET0 | output | CELL57.OUT14.TMIN |
| PIPERX1EQLPTXPRESET1 | output | CELL57.OUT17.TMIN |
| PIPERX1EQLPTXPRESET2 | output | CELL58.OUT0.TMIN |
| PIPERX1EQLPTXPRESET3 | output | CELL58.OUT2.TMIN |
| PIPERX1EQPRESET0 | output | CELL51.OUT3.TMIN |
| PIPERX1EQPRESET1 | output | CELL51.OUT5.TMIN |
| PIPERX1EQPRESET2 | output | CELL51.OUT7.TMIN |
| PIPERX1PHYSTATUS | input | CELL95.IMUX.IMUX45.DELAY |
| PIPERX1POLARITY | output | CELL93.OUT1.TMIN |
| PIPERX1STARTBLOCK | input | CELL90.IMUX.IMUX22.DELAY |
| PIPERX1STATUS0 | input | CELL94.IMUX.IMUX44.DELAY |
| PIPERX1STATUS1 | input | CELL94.IMUX.IMUX43.DELAY |
| PIPERX1STATUS2 | input | CELL94.IMUX.IMUX42.DELAY |
| PIPERX1SYNCHEADER0 | input | CELL90.IMUX.IMUX21.DELAY |
| PIPERX1SYNCHEADER1 | input | CELL90.IMUX.IMUX20.DELAY |
| PIPERX1VALID | input | CELL95.IMUX.IMUX40.DELAY |
| PIPERX2CHARISK0 | input | CELL86.IMUX.IMUX16.DELAY |
| PIPERX2CHARISK1 | input | CELL84.IMUX.IMUX16.DELAY |
| PIPERX2DATA0 | input | CELL86.IMUX.IMUX37.DELAY |
| PIPERX2DATA1 | input | CELL86.IMUX.IMUX36.DELAY |
| PIPERX2DATA10 | input | CELL84.IMUX.IMUX33.DELAY |
| PIPERX2DATA11 | input | CELL84.IMUX.IMUX32.DELAY |
| PIPERX2DATA12 | input | CELL83.IMUX.IMUX39.DELAY |
| PIPERX2DATA13 | input | CELL83.IMUX.IMUX38.DELAY |
| PIPERX2DATA14 | input | CELL83.IMUX.IMUX35.DELAY |
| PIPERX2DATA15 | input | CELL83.IMUX.IMUX34.DELAY |
| PIPERX2DATA16 | input | CELL82.IMUX.IMUX37.DELAY |
| PIPERX2DATA17 | input | CELL82.IMUX.IMUX36.DELAY |
| PIPERX2DATA18 | input | CELL82.IMUX.IMUX33.DELAY |
| PIPERX2DATA19 | input | CELL82.IMUX.IMUX32.DELAY |
| PIPERX2DATA2 | input | CELL86.IMUX.IMUX33.DELAY |
| PIPERX2DATA20 | input | CELL81.IMUX.IMUX39.DELAY |
| PIPERX2DATA21 | input | CELL81.IMUX.IMUX38.DELAY |
| PIPERX2DATA22 | input | CELL81.IMUX.IMUX35.DELAY |
| PIPERX2DATA23 | input | CELL81.IMUX.IMUX34.DELAY |
| PIPERX2DATA24 | input | CELL80.IMUX.IMUX37.DELAY |
| PIPERX2DATA25 | input | CELL80.IMUX.IMUX36.DELAY |
| PIPERX2DATA26 | input | CELL80.IMUX.IMUX33.DELAY |
| PIPERX2DATA27 | input | CELL80.IMUX.IMUX32.DELAY |
| PIPERX2DATA28 | input | CELL79.IMUX.IMUX39.DELAY |
| PIPERX2DATA29 | input | CELL79.IMUX.IMUX38.DELAY |
| PIPERX2DATA3 | input | CELL86.IMUX.IMUX32.DELAY |
| PIPERX2DATA30 | input | CELL79.IMUX.IMUX35.DELAY |
| PIPERX2DATA31 | input | CELL79.IMUX.IMUX34.DELAY |
| PIPERX2DATA4 | input | CELL85.IMUX.IMUX39.DELAY |
| PIPERX2DATA5 | input | CELL85.IMUX.IMUX38.DELAY |
| PIPERX2DATA6 | input | CELL85.IMUX.IMUX35.DELAY |
| PIPERX2DATA7 | input | CELL85.IMUX.IMUX34.DELAY |
| PIPERX2DATA8 | input | CELL84.IMUX.IMUX37.DELAY |
| PIPERX2DATA9 | input | CELL84.IMUX.IMUX36.DELAY |
| PIPERX2DATAVALID | input | CELL80.IMUX.IMUX23.DELAY |
| PIPERX2ELECIDLE | input | CELL84.IMUX.IMUX41.DELAY |
| PIPERX2EQCONTROL0 | output | CELL50.OUT8.TMIN |
| PIPERX2EQCONTROL1 | output | CELL50.OUT9.TMIN |
| PIPERX2EQDONE | input | CELL85.IMUX.IMUX2.DELAY |
| PIPERX2EQLPADAPTDONE | input | CELL83.IMUX.IMUX2.DELAY |
| PIPERX2EQLPLFFS0 | output | CELL67.OUT10.TMIN |
| PIPERX2EQLPLFFS1 | output | CELL67.OUT12.TMIN |
| PIPERX2EQLPLFFS2 | output | CELL68.OUT10.TMIN |
| PIPERX2EQLPLFFS3 | output | CELL68.OUT12.TMIN |
| PIPERX2EQLPLFFS4 | output | CELL68.OUT14.TMIN |
| PIPERX2EQLPLFFS5 | output | CELL68.OUT17.TMIN |
| PIPERX2EQLPLFFSSEL | input | CELL50.IMUX.IMUX2.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET0 | input | CELL56.IMUX.IMUX0.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET1 | input | CELL56.IMUX.IMUX1.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET10 | input | CELL58.IMUX.IMUX2.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET11 | input | CELL58.IMUX.IMUX3.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET12 | input | CELL59.IMUX.IMUX0.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET13 | input | CELL59.IMUX.IMUX1.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET14 | input | CELL59.IMUX.IMUX2.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET15 | input | CELL59.IMUX.IMUX3.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET16 | input | CELL60.IMUX.IMUX0.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET17 | input | CELL60.IMUX.IMUX1.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET2 | input | CELL56.IMUX.IMUX2.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET3 | input | CELL56.IMUX.IMUX3.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET4 | input | CELL57.IMUX.IMUX0.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET5 | input | CELL57.IMUX.IMUX1.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET6 | input | CELL57.IMUX.IMUX2.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET7 | input | CELL57.IMUX.IMUX3.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET8 | input | CELL58.IMUX.IMUX0.DELAY |
| PIPERX2EQLPNEWTXCOEFFORPRESET9 | input | CELL58.IMUX.IMUX1.DELAY |
| PIPERX2EQLPTXPRESET0 | output | CELL58.OUT3.TMIN |
| PIPERX2EQLPTXPRESET1 | output | CELL58.OUT4.TMIN |
| PIPERX2EQLPTXPRESET2 | output | CELL59.OUT0.TMIN |
| PIPERX2EQLPTXPRESET3 | output | CELL59.OUT1.TMIN |
| PIPERX2EQPRESET0 | output | CELL52.OUT1.TMIN |
| PIPERX2EQPRESET1 | output | CELL52.OUT3.TMIN |
| PIPERX2EQPRESET2 | output | CELL52.OUT5.TMIN |
| PIPERX2PHYSTATUS | input | CELL85.IMUX.IMUX45.DELAY |
| PIPERX2POLARITY | output | CELL83.OUT1.TMIN |
| PIPERX2STARTBLOCK | input | CELL80.IMUX.IMUX22.DELAY |
| PIPERX2STATUS0 | input | CELL84.IMUX.IMUX44.DELAY |
| PIPERX2STATUS1 | input | CELL84.IMUX.IMUX43.DELAY |
| PIPERX2STATUS2 | input | CELL84.IMUX.IMUX42.DELAY |
| PIPERX2SYNCHEADER0 | input | CELL80.IMUX.IMUX21.DELAY |
| PIPERX2SYNCHEADER1 | input | CELL80.IMUX.IMUX20.DELAY |
| PIPERX2VALID | input | CELL85.IMUX.IMUX40.DELAY |
| PIPERX3CHARISK0 | input | CELL85.IMUX.IMUX16.DELAY |
| PIPERX3CHARISK1 | input | CELL83.IMUX.IMUX16.DELAY |
| PIPERX3DATA0 | input | CELL85.IMUX.IMUX37.DELAY |
| PIPERX3DATA1 | input | CELL85.IMUX.IMUX36.DELAY |
| PIPERX3DATA10 | input | CELL83.IMUX.IMUX33.DELAY |
| PIPERX3DATA11 | input | CELL83.IMUX.IMUX32.DELAY |
| PIPERX3DATA12 | input | CELL82.IMUX.IMUX39.DELAY |
| PIPERX3DATA13 | input | CELL82.IMUX.IMUX38.DELAY |
| PIPERX3DATA14 | input | CELL82.IMUX.IMUX35.DELAY |
| PIPERX3DATA15 | input | CELL82.IMUX.IMUX34.DELAY |
| PIPERX3DATA16 | input | CELL81.IMUX.IMUX37.DELAY |
| PIPERX3DATA17 | input | CELL81.IMUX.IMUX36.DELAY |
| PIPERX3DATA18 | input | CELL81.IMUX.IMUX33.DELAY |
| PIPERX3DATA19 | input | CELL81.IMUX.IMUX32.DELAY |
| PIPERX3DATA2 | input | CELL85.IMUX.IMUX33.DELAY |
| PIPERX3DATA20 | input | CELL80.IMUX.IMUX39.DELAY |
| PIPERX3DATA21 | input | CELL80.IMUX.IMUX38.DELAY |
| PIPERX3DATA22 | input | CELL80.IMUX.IMUX35.DELAY |
| PIPERX3DATA23 | input | CELL80.IMUX.IMUX34.DELAY |
| PIPERX3DATA24 | input | CELL79.IMUX.IMUX37.DELAY |
| PIPERX3DATA25 | input | CELL79.IMUX.IMUX36.DELAY |
| PIPERX3DATA26 | input | CELL79.IMUX.IMUX33.DELAY |
| PIPERX3DATA27 | input | CELL79.IMUX.IMUX32.DELAY |
| PIPERX3DATA28 | input | CELL78.IMUX.IMUX39.DELAY |
| PIPERX3DATA29 | input | CELL78.IMUX.IMUX38.DELAY |
| PIPERX3DATA3 | input | CELL85.IMUX.IMUX32.DELAY |
| PIPERX3DATA30 | input | CELL78.IMUX.IMUX35.DELAY |
| PIPERX3DATA31 | input | CELL78.IMUX.IMUX34.DELAY |
| PIPERX3DATA4 | input | CELL84.IMUX.IMUX39.DELAY |
| PIPERX3DATA5 | input | CELL84.IMUX.IMUX38.DELAY |
| PIPERX3DATA6 | input | CELL84.IMUX.IMUX35.DELAY |
| PIPERX3DATA7 | input | CELL84.IMUX.IMUX34.DELAY |
| PIPERX3DATA8 | input | CELL83.IMUX.IMUX37.DELAY |
| PIPERX3DATA9 | input | CELL83.IMUX.IMUX36.DELAY |
| PIPERX3DATAVALID | input | CELL79.IMUX.IMUX23.DELAY |
| PIPERX3ELECIDLE | input | CELL83.IMUX.IMUX41.DELAY |
| PIPERX3EQCONTROL0 | output | CELL50.OUT10.TMIN |
| PIPERX3EQCONTROL1 | output | CELL50.OUT11.TMIN |
| PIPERX3EQDONE | input | CELL85.IMUX.IMUX3.DELAY |
| PIPERX3EQLPADAPTDONE | input | CELL83.IMUX.IMUX3.DELAY |
| PIPERX3EQLPLFFS0 | output | CELL69.OUT0.TMIN |
| PIPERX3EQLPLFFS1 | output | CELL69.OUT2.TMIN |
| PIPERX3EQLPLFFS2 | output | CELL69.OUT3.TMIN |
| PIPERX3EQLPLFFS3 | output | CELL69.OUT4.TMIN |
| PIPERX3EQLPLFFS4 | output | CELL70.OUT0.TMIN |
| PIPERX3EQLPLFFS5 | output | CELL70.OUT1.TMIN |
| PIPERX3EQLPLFFSSEL | input | CELL50.IMUX.IMUX3.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET0 | input | CELL60.IMUX.IMUX2.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET1 | input | CELL60.IMUX.IMUX3.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET10 | input | CELL63.IMUX.IMUX0.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET11 | input | CELL63.IMUX.IMUX1.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET12 | input | CELL63.IMUX.IMUX2.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET13 | input | CELL63.IMUX.IMUX3.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET14 | input | CELL64.IMUX.IMUX0.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET15 | input | CELL64.IMUX.IMUX1.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET16 | input | CELL64.IMUX.IMUX2.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET17 | input | CELL64.IMUX.IMUX3.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET2 | input | CELL61.IMUX.IMUX0.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET3 | input | CELL61.IMUX.IMUX1.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET4 | input | CELL61.IMUX.IMUX2.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET5 | input | CELL61.IMUX.IMUX3.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET6 | input | CELL62.IMUX.IMUX0.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET7 | input | CELL62.IMUX.IMUX1.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET8 | input | CELL62.IMUX.IMUX2.DELAY |
| PIPERX3EQLPNEWTXCOEFFORPRESET9 | input | CELL62.IMUX.IMUX3.DELAY |
| PIPERX3EQLPTXPRESET0 | output | CELL59.OUT2.TMIN |
| PIPERX3EQLPTXPRESET1 | output | CELL59.OUT3.TMIN |
| PIPERX3EQLPTXPRESET2 | output | CELL60.OUT0.TMIN |
| PIPERX3EQLPTXPRESET3 | output | CELL60.OUT1.TMIN |
| PIPERX3EQPRESET0 | output | CELL52.OUT7.TMIN |
| PIPERX3EQPRESET1 | output | CELL53.OUT1.TMIN |
| PIPERX3EQPRESET2 | output | CELL53.OUT3.TMIN |
| PIPERX3PHYSTATUS | input | CELL84.IMUX.IMUX45.DELAY |
| PIPERX3POLARITY | output | CELL82.OUT1.TMIN |
| PIPERX3STARTBLOCK | input | CELL79.IMUX.IMUX22.DELAY |
| PIPERX3STATUS0 | input | CELL83.IMUX.IMUX44.DELAY |
| PIPERX3STATUS1 | input | CELL83.IMUX.IMUX43.DELAY |
| PIPERX3STATUS2 | input | CELL83.IMUX.IMUX42.DELAY |
| PIPERX3SYNCHEADER0 | input | CELL79.IMUX.IMUX21.DELAY |
| PIPERX3SYNCHEADER1 | input | CELL79.IMUX.IMUX20.DELAY |
| PIPERX3VALID | input | CELL84.IMUX.IMUX40.DELAY |
| PIPERX4CHARISK0 | input | CELL72.IMUX.IMUX16.DELAY |
| PIPERX4CHARISK1 | input | CELL70.IMUX.IMUX16.DELAY |
| PIPERX4DATA0 | input | CELL72.IMUX.IMUX37.DELAY |
| PIPERX4DATA1 | input | CELL72.IMUX.IMUX36.DELAY |
| PIPERX4DATA10 | input | CELL70.IMUX.IMUX33.DELAY |
| PIPERX4DATA11 | input | CELL70.IMUX.IMUX32.DELAY |
| PIPERX4DATA12 | input | CELL69.IMUX.IMUX39.DELAY |
| PIPERX4DATA13 | input | CELL69.IMUX.IMUX38.DELAY |
| PIPERX4DATA14 | input | CELL69.IMUX.IMUX35.DELAY |
| PIPERX4DATA15 | input | CELL69.IMUX.IMUX34.DELAY |
| PIPERX4DATA16 | input | CELL68.IMUX.IMUX37.DELAY |
| PIPERX4DATA17 | input | CELL68.IMUX.IMUX36.DELAY |
| PIPERX4DATA18 | input | CELL68.IMUX.IMUX33.DELAY |
| PIPERX4DATA19 | input | CELL68.IMUX.IMUX32.DELAY |
| PIPERX4DATA2 | input | CELL72.IMUX.IMUX33.DELAY |
| PIPERX4DATA20 | input | CELL67.IMUX.IMUX39.DELAY |
| PIPERX4DATA21 | input | CELL67.IMUX.IMUX38.DELAY |
| PIPERX4DATA22 | input | CELL67.IMUX.IMUX35.DELAY |
| PIPERX4DATA23 | input | CELL67.IMUX.IMUX34.DELAY |
| PIPERX4DATA24 | input | CELL66.IMUX.IMUX37.DELAY |
| PIPERX4DATA25 | input | CELL66.IMUX.IMUX36.DELAY |
| PIPERX4DATA26 | input | CELL66.IMUX.IMUX33.DELAY |
| PIPERX4DATA27 | input | CELL66.IMUX.IMUX32.DELAY |
| PIPERX4DATA28 | input | CELL65.IMUX.IMUX39.DELAY |
| PIPERX4DATA29 | input | CELL65.IMUX.IMUX38.DELAY |
| PIPERX4DATA3 | input | CELL72.IMUX.IMUX32.DELAY |
| PIPERX4DATA30 | input | CELL65.IMUX.IMUX35.DELAY |
| PIPERX4DATA31 | input | CELL65.IMUX.IMUX34.DELAY |
| PIPERX4DATA4 | input | CELL71.IMUX.IMUX39.DELAY |
| PIPERX4DATA5 | input | CELL71.IMUX.IMUX38.DELAY |
| PIPERX4DATA6 | input | CELL71.IMUX.IMUX35.DELAY |
| PIPERX4DATA7 | input | CELL71.IMUX.IMUX34.DELAY |
| PIPERX4DATA8 | input | CELL70.IMUX.IMUX37.DELAY |
| PIPERX4DATA9 | input | CELL70.IMUX.IMUX36.DELAY |
| PIPERX4DATAVALID | input | CELL66.IMUX.IMUX23.DELAY |
| PIPERX4ELECIDLE | input | CELL70.IMUX.IMUX41.DELAY |
| PIPERX4EQCONTROL0 | output | CELL50.OUT12.TMIN |
| PIPERX4EQCONTROL1 | output | CELL50.OUT13.TMIN |
| PIPERX4EQDONE | input | CELL86.IMUX.IMUX0.DELAY |
| PIPERX4EQLPADAPTDONE | input | CELL84.IMUX.IMUX0.DELAY |
| PIPERX4EQLPLFFS0 | output | CELL70.OUT2.TMIN |
| PIPERX4EQLPLFFS1 | output | CELL70.OUT3.TMIN |
| PIPERX4EQLPLFFS2 | output | CELL71.OUT0.TMIN |
| PIPERX4EQLPLFFS3 | output | CELL71.OUT1.TMIN |
| PIPERX4EQLPLFFS4 | output | CELL71.OUT2.TMIN |
| PIPERX4EQLPLFFS5 | output | CELL71.OUT3.TMIN |
| PIPERX4EQLPLFFSSEL | input | CELL50.IMUX.IMUX4.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET0 | input | CELL65.IMUX.IMUX0.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET1 | input | CELL65.IMUX.IMUX1.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET10 | input | CELL67.IMUX.IMUX2.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET11 | input | CELL67.IMUX.IMUX3.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET12 | input | CELL68.IMUX.IMUX0.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET13 | input | CELL68.IMUX.IMUX1.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET14 | input | CELL68.IMUX.IMUX2.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET15 | input | CELL68.IMUX.IMUX3.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET16 | input | CELL69.IMUX.IMUX0.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET17 | input | CELL69.IMUX.IMUX1.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET2 | input | CELL65.IMUX.IMUX2.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET3 | input | CELL65.IMUX.IMUX3.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET4 | input | CELL66.IMUX.IMUX0.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET5 | input | CELL66.IMUX.IMUX1.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET6 | input | CELL66.IMUX.IMUX2.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET7 | input | CELL66.IMUX.IMUX3.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET8 | input | CELL67.IMUX.IMUX0.DELAY |
| PIPERX4EQLPNEWTXCOEFFORPRESET9 | input | CELL67.IMUX.IMUX1.DELAY |
| PIPERX4EQLPTXPRESET0 | output | CELL60.OUT2.TMIN |
| PIPERX4EQLPTXPRESET1 | output | CELL60.OUT3.TMIN |
| PIPERX4EQLPTXPRESET2 | output | CELL61.OUT1.TMIN |
| PIPERX4EQLPTXPRESET3 | output | CELL61.OUT3.TMIN |
| PIPERX4EQPRESET0 | output | CELL53.OUT5.TMIN |
| PIPERX4EQPRESET1 | output | CELL53.OUT7.TMIN |
| PIPERX4EQPRESET2 | output | CELL54.OUT1.TMIN |
| PIPERX4PHYSTATUS | input | CELL71.IMUX.IMUX45.DELAY |
| PIPERX4POLARITY | output | CELL69.OUT1.TMIN |
| PIPERX4STARTBLOCK | input | CELL66.IMUX.IMUX22.DELAY |
| PIPERX4STATUS0 | input | CELL70.IMUX.IMUX44.DELAY |
| PIPERX4STATUS1 | input | CELL70.IMUX.IMUX43.DELAY |
| PIPERX4STATUS2 | input | CELL70.IMUX.IMUX42.DELAY |
| PIPERX4SYNCHEADER0 | input | CELL66.IMUX.IMUX21.DELAY |
| PIPERX4SYNCHEADER1 | input | CELL66.IMUX.IMUX20.DELAY |
| PIPERX4VALID | input | CELL71.IMUX.IMUX40.DELAY |
| PIPERX5CHARISK0 | input | CELL71.IMUX.IMUX16.DELAY |
| PIPERX5CHARISK1 | input | CELL69.IMUX.IMUX16.DELAY |
| PIPERX5DATA0 | input | CELL71.IMUX.IMUX37.DELAY |
| PIPERX5DATA1 | input | CELL71.IMUX.IMUX36.DELAY |
| PIPERX5DATA10 | input | CELL69.IMUX.IMUX33.DELAY |
| PIPERX5DATA11 | input | CELL69.IMUX.IMUX32.DELAY |
| PIPERX5DATA12 | input | CELL68.IMUX.IMUX39.DELAY |
| PIPERX5DATA13 | input | CELL68.IMUX.IMUX38.DELAY |
| PIPERX5DATA14 | input | CELL68.IMUX.IMUX35.DELAY |
| PIPERX5DATA15 | input | CELL68.IMUX.IMUX34.DELAY |
| PIPERX5DATA16 | input | CELL67.IMUX.IMUX37.DELAY |
| PIPERX5DATA17 | input | CELL67.IMUX.IMUX36.DELAY |
| PIPERX5DATA18 | input | CELL67.IMUX.IMUX33.DELAY |
| PIPERX5DATA19 | input | CELL67.IMUX.IMUX32.DELAY |
| PIPERX5DATA2 | input | CELL71.IMUX.IMUX33.DELAY |
| PIPERX5DATA20 | input | CELL66.IMUX.IMUX39.DELAY |
| PIPERX5DATA21 | input | CELL66.IMUX.IMUX38.DELAY |
| PIPERX5DATA22 | input | CELL66.IMUX.IMUX35.DELAY |
| PIPERX5DATA23 | input | CELL66.IMUX.IMUX34.DELAY |
| PIPERX5DATA24 | input | CELL65.IMUX.IMUX37.DELAY |
| PIPERX5DATA25 | input | CELL65.IMUX.IMUX36.DELAY |
| PIPERX5DATA26 | input | CELL65.IMUX.IMUX33.DELAY |
| PIPERX5DATA27 | input | CELL65.IMUX.IMUX32.DELAY |
| PIPERX5DATA28 | input | CELL64.IMUX.IMUX39.DELAY |
| PIPERX5DATA29 | input | CELL64.IMUX.IMUX38.DELAY |
| PIPERX5DATA3 | input | CELL71.IMUX.IMUX32.DELAY |
| PIPERX5DATA30 | input | CELL64.IMUX.IMUX35.DELAY |
| PIPERX5DATA31 | input | CELL64.IMUX.IMUX34.DELAY |
| PIPERX5DATA4 | input | CELL70.IMUX.IMUX39.DELAY |
| PIPERX5DATA5 | input | CELL70.IMUX.IMUX38.DELAY |
| PIPERX5DATA6 | input | CELL70.IMUX.IMUX35.DELAY |
| PIPERX5DATA7 | input | CELL70.IMUX.IMUX34.DELAY |
| PIPERX5DATA8 | input | CELL69.IMUX.IMUX37.DELAY |
| PIPERX5DATA9 | input | CELL69.IMUX.IMUX36.DELAY |
| PIPERX5DATAVALID | input | CELL65.IMUX.IMUX23.DELAY |
| PIPERX5ELECIDLE | input | CELL69.IMUX.IMUX41.DELAY |
| PIPERX5EQCONTROL0 | output | CELL50.OUT14.TMIN |
| PIPERX5EQCONTROL1 | output | CELL50.OUT15.TMIN |
| PIPERX5EQDONE | input | CELL86.IMUX.IMUX1.DELAY |
| PIPERX5EQLPADAPTDONE | input | CELL84.IMUX.IMUX1.DELAY |
| PIPERX5EQLPLFFS0 | output | CELL72.OUT0.TMIN |
| PIPERX5EQLPLFFS1 | output | CELL72.OUT1.TMIN |
| PIPERX5EQLPLFFS2 | output | CELL72.OUT2.TMIN |
| PIPERX5EQLPLFFS3 | output | CELL72.OUT3.TMIN |
| PIPERX5EQLPLFFS4 | output | CELL73.OUT0.TMIN |
| PIPERX5EQLPLFFS5 | output | CELL73.OUT1.TMIN |
| PIPERX5EQLPLFFSSEL | input | CELL50.IMUX.IMUX5.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET0 | input | CELL69.IMUX.IMUX2.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET1 | input | CELL69.IMUX.IMUX3.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET10 | input | CELL72.IMUX.IMUX0.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET11 | input | CELL72.IMUX.IMUX1.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET12 | input | CELL72.IMUX.IMUX2.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET13 | input | CELL72.IMUX.IMUX3.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET14 | input | CELL73.IMUX.IMUX0.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET15 | input | CELL73.IMUX.IMUX1.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET16 | input | CELL73.IMUX.IMUX2.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET17 | input | CELL73.IMUX.IMUX3.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET2 | input | CELL70.IMUX.IMUX0.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET3 | input | CELL70.IMUX.IMUX1.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET4 | input | CELL70.IMUX.IMUX2.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET5 | input | CELL70.IMUX.IMUX3.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET6 | input | CELL71.IMUX.IMUX0.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET7 | input | CELL71.IMUX.IMUX1.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET8 | input | CELL71.IMUX.IMUX2.DELAY |
| PIPERX5EQLPNEWTXCOEFFORPRESET9 | input | CELL71.IMUX.IMUX3.DELAY |
| PIPERX5EQLPTXPRESET0 | output | CELL61.OUT5.TMIN |
| PIPERX5EQLPTXPRESET1 | output | CELL61.OUT7.TMIN |
| PIPERX5EQLPTXPRESET2 | output | CELL62.OUT1.TMIN |
| PIPERX5EQLPTXPRESET3 | output | CELL62.OUT3.TMIN |
| PIPERX5EQPRESET0 | output | CELL54.OUT3.TMIN |
| PIPERX5EQPRESET1 | output | CELL54.OUT5.TMIN |
| PIPERX5EQPRESET2 | output | CELL54.OUT7.TMIN |
| PIPERX5PHYSTATUS | input | CELL70.IMUX.IMUX45.DELAY |
| PIPERX5POLARITY | output | CELL68.OUT1.TMIN |
| PIPERX5STARTBLOCK | input | CELL65.IMUX.IMUX22.DELAY |
| PIPERX5STATUS0 | input | CELL69.IMUX.IMUX44.DELAY |
| PIPERX5STATUS1 | input | CELL69.IMUX.IMUX43.DELAY |
| PIPERX5STATUS2 | input | CELL69.IMUX.IMUX42.DELAY |
| PIPERX5SYNCHEADER0 | input | CELL65.IMUX.IMUX21.DELAY |
| PIPERX5SYNCHEADER1 | input | CELL65.IMUX.IMUX20.DELAY |
| PIPERX5VALID | input | CELL70.IMUX.IMUX40.DELAY |
| PIPERX6CHARISK0 | input | CELL61.IMUX.IMUX16.DELAY |
| PIPERX6CHARISK1 | input | CELL59.IMUX.IMUX16.DELAY |
| PIPERX6DATA0 | input | CELL61.IMUX.IMUX37.DELAY |
| PIPERX6DATA1 | input | CELL61.IMUX.IMUX36.DELAY |
| PIPERX6DATA10 | input | CELL59.IMUX.IMUX33.DELAY |
| PIPERX6DATA11 | input | CELL59.IMUX.IMUX32.DELAY |
| PIPERX6DATA12 | input | CELL58.IMUX.IMUX39.DELAY |
| PIPERX6DATA13 | input | CELL58.IMUX.IMUX38.DELAY |
| PIPERX6DATA14 | input | CELL58.IMUX.IMUX35.DELAY |
| PIPERX6DATA15 | input | CELL58.IMUX.IMUX34.DELAY |
| PIPERX6DATA16 | input | CELL57.IMUX.IMUX37.DELAY |
| PIPERX6DATA17 | input | CELL57.IMUX.IMUX36.DELAY |
| PIPERX6DATA18 | input | CELL57.IMUX.IMUX33.DELAY |
| PIPERX6DATA19 | input | CELL57.IMUX.IMUX32.DELAY |
| PIPERX6DATA2 | input | CELL61.IMUX.IMUX33.DELAY |
| PIPERX6DATA20 | input | CELL56.IMUX.IMUX39.DELAY |
| PIPERX6DATA21 | input | CELL56.IMUX.IMUX38.DELAY |
| PIPERX6DATA22 | input | CELL56.IMUX.IMUX35.DELAY |
| PIPERX6DATA23 | input | CELL56.IMUX.IMUX34.DELAY |
| PIPERX6DATA24 | input | CELL55.IMUX.IMUX37.DELAY |
| PIPERX6DATA25 | input | CELL55.IMUX.IMUX36.DELAY |
| PIPERX6DATA26 | input | CELL55.IMUX.IMUX33.DELAY |
| PIPERX6DATA27 | input | CELL55.IMUX.IMUX32.DELAY |
| PIPERX6DATA28 | input | CELL54.IMUX.IMUX39.DELAY |
| PIPERX6DATA29 | input | CELL54.IMUX.IMUX38.DELAY |
| PIPERX6DATA3 | input | CELL61.IMUX.IMUX32.DELAY |
| PIPERX6DATA30 | input | CELL54.IMUX.IMUX35.DELAY |
| PIPERX6DATA31 | input | CELL54.IMUX.IMUX34.DELAY |
| PIPERX6DATA4 | input | CELL60.IMUX.IMUX39.DELAY |
| PIPERX6DATA5 | input | CELL60.IMUX.IMUX38.DELAY |
| PIPERX6DATA6 | input | CELL60.IMUX.IMUX35.DELAY |
| PIPERX6DATA7 | input | CELL60.IMUX.IMUX34.DELAY |
| PIPERX6DATA8 | input | CELL59.IMUX.IMUX37.DELAY |
| PIPERX6DATA9 | input | CELL59.IMUX.IMUX36.DELAY |
| PIPERX6DATAVALID | input | CELL55.IMUX.IMUX23.DELAY |
| PIPERX6ELECIDLE | input | CELL59.IMUX.IMUX41.DELAY |
| PIPERX6EQCONTROL0 | output | CELL50.OUT16.TMIN |
| PIPERX6EQCONTROL1 | output | CELL50.OUT17.TMIN |
| PIPERX6EQDONE | input | CELL86.IMUX.IMUX2.DELAY |
| PIPERX6EQLPADAPTDONE | input | CELL84.IMUX.IMUX2.DELAY |
| PIPERX6EQLPLFFS0 | output | CELL73.OUT2.TMIN |
| PIPERX6EQLPLFFS1 | output | CELL73.OUT3.TMIN |
| PIPERX6EQLPLFFS2 | output | CELL74.OUT0.TMIN |
| PIPERX6EQLPLFFS3 | output | CELL74.OUT1.TMIN |
| PIPERX6EQLPLFFS4 | output | CELL74.OUT2.TMIN |
| PIPERX6EQLPLFFS5 | output | CELL74.OUT3.TMIN |
| PIPERX6EQLPLFFSSEL | input | CELL50.IMUX.IMUX6.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET0 | input | CELL74.IMUX.IMUX0.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET1 | input | CELL74.IMUX.IMUX1.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET10 | input | CELL76.IMUX.IMUX2.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET11 | input | CELL76.IMUX.IMUX3.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET12 | input | CELL77.IMUX.IMUX0.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET13 | input | CELL77.IMUX.IMUX1.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET14 | input | CELL77.IMUX.IMUX2.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET15 | input | CELL77.IMUX.IMUX3.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET16 | input | CELL78.IMUX.IMUX0.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET17 | input | CELL78.IMUX.IMUX1.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET2 | input | CELL74.IMUX.IMUX2.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET3 | input | CELL74.IMUX.IMUX3.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET4 | input | CELL75.IMUX.IMUX0.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET5 | input | CELL75.IMUX.IMUX1.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET6 | input | CELL75.IMUX.IMUX2.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET7 | input | CELL75.IMUX.IMUX3.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET8 | input | CELL76.IMUX.IMUX0.DELAY |
| PIPERX6EQLPNEWTXCOEFFORPRESET9 | input | CELL76.IMUX.IMUX1.DELAY |
| PIPERX6EQLPTXPRESET0 | output | CELL62.OUT5.TMIN |
| PIPERX6EQLPTXPRESET1 | output | CELL62.OUT7.TMIN |
| PIPERX6EQLPTXPRESET2 | output | CELL63.OUT1.TMIN |
| PIPERX6EQLPTXPRESET3 | output | CELL63.OUT3.TMIN |
| PIPERX6EQPRESET0 | output | CELL55.OUT1.TMIN |
| PIPERX6EQPRESET1 | output | CELL55.OUT3.TMIN |
| PIPERX6EQPRESET2 | output | CELL55.OUT5.TMIN |
| PIPERX6PHYSTATUS | input | CELL60.IMUX.IMUX45.DELAY |
| PIPERX6POLARITY | output | CELL58.OUT1.TMIN |
| PIPERX6STARTBLOCK | input | CELL55.IMUX.IMUX22.DELAY |
| PIPERX6STATUS0 | input | CELL59.IMUX.IMUX44.DELAY |
| PIPERX6STATUS1 | input | CELL59.IMUX.IMUX43.DELAY |
| PIPERX6STATUS2 | input | CELL59.IMUX.IMUX42.DELAY |
| PIPERX6SYNCHEADER0 | input | CELL55.IMUX.IMUX21.DELAY |
| PIPERX6SYNCHEADER1 | input | CELL55.IMUX.IMUX20.DELAY |
| PIPERX6VALID | input | CELL60.IMUX.IMUX40.DELAY |
| PIPERX7CHARISK0 | input | CELL60.IMUX.IMUX16.DELAY |
| PIPERX7CHARISK1 | input | CELL58.IMUX.IMUX16.DELAY |
| PIPERX7DATA0 | input | CELL60.IMUX.IMUX37.DELAY |
| PIPERX7DATA1 | input | CELL60.IMUX.IMUX36.DELAY |
| PIPERX7DATA10 | input | CELL58.IMUX.IMUX33.DELAY |
| PIPERX7DATA11 | input | CELL58.IMUX.IMUX32.DELAY |
| PIPERX7DATA12 | input | CELL57.IMUX.IMUX39.DELAY |
| PIPERX7DATA13 | input | CELL57.IMUX.IMUX38.DELAY |
| PIPERX7DATA14 | input | CELL57.IMUX.IMUX35.DELAY |
| PIPERX7DATA15 | input | CELL57.IMUX.IMUX34.DELAY |
| PIPERX7DATA16 | input | CELL56.IMUX.IMUX37.DELAY |
| PIPERX7DATA17 | input | CELL56.IMUX.IMUX36.DELAY |
| PIPERX7DATA18 | input | CELL56.IMUX.IMUX33.DELAY |
| PIPERX7DATA19 | input | CELL56.IMUX.IMUX32.DELAY |
| PIPERX7DATA2 | input | CELL60.IMUX.IMUX33.DELAY |
| PIPERX7DATA20 | input | CELL55.IMUX.IMUX39.DELAY |
| PIPERX7DATA21 | input | CELL55.IMUX.IMUX38.DELAY |
| PIPERX7DATA22 | input | CELL55.IMUX.IMUX35.DELAY |
| PIPERX7DATA23 | input | CELL55.IMUX.IMUX34.DELAY |
| PIPERX7DATA24 | input | CELL54.IMUX.IMUX37.DELAY |
| PIPERX7DATA25 | input | CELL54.IMUX.IMUX36.DELAY |
| PIPERX7DATA26 | input | CELL54.IMUX.IMUX33.DELAY |
| PIPERX7DATA27 | input | CELL54.IMUX.IMUX32.DELAY |
| PIPERX7DATA28 | input | CELL53.IMUX.IMUX39.DELAY |
| PIPERX7DATA29 | input | CELL53.IMUX.IMUX38.DELAY |
| PIPERX7DATA3 | input | CELL60.IMUX.IMUX32.DELAY |
| PIPERX7DATA30 | input | CELL53.IMUX.IMUX35.DELAY |
| PIPERX7DATA31 | input | CELL53.IMUX.IMUX34.DELAY |
| PIPERX7DATA4 | input | CELL59.IMUX.IMUX39.DELAY |
| PIPERX7DATA5 | input | CELL59.IMUX.IMUX38.DELAY |
| PIPERX7DATA6 | input | CELL59.IMUX.IMUX35.DELAY |
| PIPERX7DATA7 | input | CELL59.IMUX.IMUX34.DELAY |
| PIPERX7DATA8 | input | CELL58.IMUX.IMUX37.DELAY |
| PIPERX7DATA9 | input | CELL58.IMUX.IMUX36.DELAY |
| PIPERX7DATAVALID | input | CELL54.IMUX.IMUX23.DELAY |
| PIPERX7ELECIDLE | input | CELL58.IMUX.IMUX41.DELAY |
| PIPERX7EQCONTROL0 | output | CELL50.OUT18.TMIN |
| PIPERX7EQCONTROL1 | output | CELL50.OUT19.TMIN |
| PIPERX7EQDONE | input | CELL86.IMUX.IMUX3.DELAY |
| PIPERX7EQLPADAPTDONE | input | CELL84.IMUX.IMUX3.DELAY |
| PIPERX7EQLPLFFS0 | output | CELL75.OUT1.TMIN |
| PIPERX7EQLPLFFS1 | output | CELL75.OUT3.TMIN |
| PIPERX7EQLPLFFS2 | output | CELL75.OUT5.TMIN |
| PIPERX7EQLPLFFS3 | output | CELL75.OUT7.TMIN |
| PIPERX7EQLPLFFS4 | output | CELL76.OUT1.TMIN |
| PIPERX7EQLPLFFS5 | output | CELL76.OUT3.TMIN |
| PIPERX7EQLPLFFSSEL | input | CELL50.IMUX.IMUX7.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET0 | input | CELL78.IMUX.IMUX2.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET1 | input | CELL78.IMUX.IMUX3.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET10 | input | CELL81.IMUX.IMUX0.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET11 | input | CELL81.IMUX.IMUX1.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET12 | input | CELL81.IMUX.IMUX2.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET13 | input | CELL81.IMUX.IMUX3.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET14 | input | CELL82.IMUX.IMUX0.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET15 | input | CELL82.IMUX.IMUX1.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET16 | input | CELL82.IMUX.IMUX2.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET17 | input | CELL82.IMUX.IMUX3.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET2 | input | CELL79.IMUX.IMUX0.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET3 | input | CELL79.IMUX.IMUX1.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET4 | input | CELL79.IMUX.IMUX2.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET5 | input | CELL79.IMUX.IMUX3.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET6 | input | CELL80.IMUX.IMUX0.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET7 | input | CELL80.IMUX.IMUX1.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET8 | input | CELL80.IMUX.IMUX2.DELAY |
| PIPERX7EQLPNEWTXCOEFFORPRESET9 | input | CELL80.IMUX.IMUX3.DELAY |
| PIPERX7EQLPTXPRESET0 | output | CELL63.OUT5.TMIN |
| PIPERX7EQLPTXPRESET1 | output | CELL63.OUT7.TMIN |
| PIPERX7EQLPTXPRESET2 | output | CELL64.OUT1.TMIN |
| PIPERX7EQLPTXPRESET3 | output | CELL64.OUT3.TMIN |
| PIPERX7EQPRESET0 | output | CELL55.OUT7.TMIN |
| PIPERX7EQPRESET1 | output | CELL56.OUT1.TMIN |
| PIPERX7EQPRESET2 | output | CELL56.OUT8.TMIN |
| PIPERX7PHYSTATUS | input | CELL59.IMUX.IMUX45.DELAY |
| PIPERX7POLARITY | output | CELL57.OUT1.TMIN |
| PIPERX7STARTBLOCK | input | CELL54.IMUX.IMUX22.DELAY |
| PIPERX7STATUS0 | input | CELL58.IMUX.IMUX44.DELAY |
| PIPERX7STATUS1 | input | CELL58.IMUX.IMUX43.DELAY |
| PIPERX7STATUS2 | input | CELL58.IMUX.IMUX42.DELAY |
| PIPERX7SYNCHEADER0 | input | CELL54.IMUX.IMUX21.DELAY |
| PIPERX7SYNCHEADER1 | input | CELL54.IMUX.IMUX20.DELAY |
| PIPERX7VALID | input | CELL59.IMUX.IMUX40.DELAY |
| PIPETX0CHARISK0 | output | CELL93.OUT16.TMIN |
| PIPETX0CHARISK1 | output | CELL91.OUT16.TMIN |
| PIPETX0COMPLIANCE | output | CELL94.OUT8.TMIN |
| PIPETX0DATA0 | output | CELL94.OUT9.TMIN |
| PIPETX0DATA1 | output | CELL94.OUT13.TMIN |
| PIPETX0DATA10 | output | CELL92.OUT11.TMIN |
| PIPETX0DATA11 | output | CELL92.OUT15.TMIN |
| PIPETX0DATA12 | output | CELL91.OUT0.TMIN |
| PIPETX0DATA13 | output | CELL91.OUT4.TMIN |
| PIPETX0DATA14 | output | CELL91.OUT2.TMIN |
| PIPETX0DATA15 | output | CELL91.OUT6.TMIN |
| PIPETX0DATA16 | output | CELL90.OUT9.TMIN |
| PIPETX0DATA17 | output | CELL90.OUT13.TMIN |
| PIPETX0DATA18 | output | CELL90.OUT11.TMIN |
| PIPETX0DATA19 | output | CELL90.OUT15.TMIN |
| PIPETX0DATA2 | output | CELL94.OUT11.TMIN |
| PIPETX0DATA20 | output | CELL89.OUT0.TMIN |
| PIPETX0DATA21 | output | CELL89.OUT4.TMIN |
| PIPETX0DATA22 | output | CELL89.OUT2.TMIN |
| PIPETX0DATA23 | output | CELL89.OUT6.TMIN |
| PIPETX0DATA24 | output | CELL88.OUT9.TMIN |
| PIPETX0DATA25 | output | CELL88.OUT13.TMIN |
| PIPETX0DATA26 | output | CELL88.OUT11.TMIN |
| PIPETX0DATA27 | output | CELL88.OUT15.TMIN |
| PIPETX0DATA28 | output | CELL87.OUT0.TMIN |
| PIPETX0DATA29 | output | CELL87.OUT4.TMIN |
| PIPETX0DATA3 | output | CELL94.OUT15.TMIN |
| PIPETX0DATA30 | output | CELL87.OUT2.TMIN |
| PIPETX0DATA31 | output | CELL87.OUT6.TMIN |
| PIPETX0DATA4 | output | CELL93.OUT0.TMIN |
| PIPETX0DATA5 | output | CELL93.OUT4.TMIN |
| PIPETX0DATA6 | output | CELL93.OUT2.TMIN |
| PIPETX0DATA7 | output | CELL93.OUT6.TMIN |
| PIPETX0DATA8 | output | CELL92.OUT9.TMIN |
| PIPETX0DATA9 | output | CELL92.OUT13.TMIN |
| PIPETX0DATAVALID | output | CELL91.OUT23.TMIN |
| PIPETX0ELECIDLE | output | CELL93.OUT3.TMIN |
| PIPETX0EQCOEFF0 | input | CELL87.IMUX.IMUX0.DELAY |
| PIPETX0EQCOEFF1 | input | CELL87.IMUX.IMUX1.DELAY |
| PIPETX0EQCOEFF10 | input | CELL89.IMUX.IMUX2.DELAY |
| PIPETX0EQCOEFF11 | input | CELL89.IMUX.IMUX3.DELAY |
| PIPETX0EQCOEFF12 | input | CELL90.IMUX.IMUX0.DELAY |
| PIPETX0EQCOEFF13 | input | CELL90.IMUX.IMUX1.DELAY |
| PIPETX0EQCOEFF14 | input | CELL90.IMUX.IMUX2.DELAY |
| PIPETX0EQCOEFF15 | input | CELL90.IMUX.IMUX3.DELAY |
| PIPETX0EQCOEFF16 | input | CELL91.IMUX.IMUX0.DELAY |
| PIPETX0EQCOEFF17 | input | CELL91.IMUX.IMUX1.DELAY |
| PIPETX0EQCOEFF2 | input | CELL87.IMUX.IMUX2.DELAY |
| PIPETX0EQCOEFF3 | input | CELL87.IMUX.IMUX3.DELAY |
| PIPETX0EQCOEFF4 | input | CELL88.IMUX.IMUX0.DELAY |
| PIPETX0EQCOEFF5 | input | CELL88.IMUX.IMUX1.DELAY |
| PIPETX0EQCOEFF6 | input | CELL88.IMUX.IMUX2.DELAY |
| PIPETX0EQCOEFF7 | input | CELL88.IMUX.IMUX3.DELAY |
| PIPETX0EQCOEFF8 | input | CELL89.IMUX.IMUX0.DELAY |
| PIPETX0EQCOEFF9 | input | CELL89.IMUX.IMUX1.DELAY |
| PIPETX0EQCONTROL0 | output | CELL76.OUT5.TMIN |
| PIPETX0EQCONTROL1 | output | CELL76.OUT7.TMIN |
| PIPETX0EQDEEMPH0 | output | CELL88.OUT5.TMIN |
| PIPETX0EQDEEMPH1 | output | CELL88.OUT7.TMIN |
| PIPETX0EQDEEMPH2 | output | CELL89.OUT1.TMIN |
| PIPETX0EQDEEMPH3 | output | CELL89.OUT3.TMIN |
| PIPETX0EQDEEMPH4 | output | CELL89.OUT5.TMIN |
| PIPETX0EQDEEMPH5 | output | CELL89.OUT7.TMIN |
| PIPETX0EQDONE | input | CELL76.IMUX.IMUX4.DELAY |
| PIPETX0EQPRESET0 | output | CELL80.OUT5.TMIN |
| PIPETX0EQPRESET1 | output | CELL80.OUT7.TMIN |
| PIPETX0EQPRESET2 | output | CELL81.OUT1.TMIN |
| PIPETX0EQPRESET3 | output | CELL81.OUT8.TMIN |
| PIPETX0POWERDOWN0 | output | CELL93.OUT5.TMIN |
| PIPETX0POWERDOWN1 | output | CELL93.OUT7.TMIN |
| PIPETX0STARTBLOCK | output | CELL91.OUT22.TMIN |
| PIPETX0SYNCHEADER0 | output | CELL91.OUT21.TMIN |
| PIPETX0SYNCHEADER1 | output | CELL91.OUT20.TMIN |
| PIPETX1CHARISK0 | output | CELL92.OUT16.TMIN |
| PIPETX1CHARISK1 | output | CELL90.OUT16.TMIN |
| PIPETX1COMPLIANCE | output | CELL93.OUT8.TMIN |
| PIPETX1DATA0 | output | CELL93.OUT9.TMIN |
| PIPETX1DATA1 | output | CELL93.OUT13.TMIN |
| PIPETX1DATA10 | output | CELL91.OUT11.TMIN |
| PIPETX1DATA11 | output | CELL91.OUT15.TMIN |
| PIPETX1DATA12 | output | CELL90.OUT0.TMIN |
| PIPETX1DATA13 | output | CELL90.OUT4.TMIN |
| PIPETX1DATA14 | output | CELL90.OUT2.TMIN |
| PIPETX1DATA15 | output | CELL90.OUT6.TMIN |
| PIPETX1DATA16 | output | CELL89.OUT9.TMIN |
| PIPETX1DATA17 | output | CELL89.OUT13.TMIN |
| PIPETX1DATA18 | output | CELL89.OUT11.TMIN |
| PIPETX1DATA19 | output | CELL89.OUT15.TMIN |
| PIPETX1DATA2 | output | CELL93.OUT11.TMIN |
| PIPETX1DATA20 | output | CELL88.OUT0.TMIN |
| PIPETX1DATA21 | output | CELL88.OUT4.TMIN |
| PIPETX1DATA22 | output | CELL88.OUT2.TMIN |
| PIPETX1DATA23 | output | CELL88.OUT6.TMIN |
| PIPETX1DATA24 | output | CELL87.OUT9.TMIN |
| PIPETX1DATA25 | output | CELL87.OUT13.TMIN |
| PIPETX1DATA26 | output | CELL87.OUT11.TMIN |
| PIPETX1DATA27 | output | CELL87.OUT15.TMIN |
| PIPETX1DATA28 | output | CELL86.OUT0.TMIN |
| PIPETX1DATA29 | output | CELL86.OUT4.TMIN |
| PIPETX1DATA3 | output | CELL93.OUT15.TMIN |
| PIPETX1DATA30 | output | CELL86.OUT2.TMIN |
| PIPETX1DATA31 | output | CELL86.OUT6.TMIN |
| PIPETX1DATA4 | output | CELL92.OUT0.TMIN |
| PIPETX1DATA5 | output | CELL92.OUT4.TMIN |
| PIPETX1DATA6 | output | CELL92.OUT2.TMIN |
| PIPETX1DATA7 | output | CELL92.OUT6.TMIN |
| PIPETX1DATA8 | output | CELL91.OUT9.TMIN |
| PIPETX1DATA9 | output | CELL91.OUT13.TMIN |
| PIPETX1DATAVALID | output | CELL90.OUT23.TMIN |
| PIPETX1ELECIDLE | output | CELL92.OUT3.TMIN |
| PIPETX1EQCOEFF0 | input | CELL91.IMUX.IMUX2.DELAY |
| PIPETX1EQCOEFF1 | input | CELL91.IMUX.IMUX3.DELAY |
| PIPETX1EQCOEFF10 | input | CELL94.IMUX.IMUX0.DELAY |
| PIPETX1EQCOEFF11 | input | CELL94.IMUX.IMUX1.DELAY |
| PIPETX1EQCOEFF12 | input | CELL94.IMUX.IMUX2.DELAY |
| PIPETX1EQCOEFF13 | input | CELL94.IMUX.IMUX3.DELAY |
| PIPETX1EQCOEFF14 | input | CELL95.IMUX.IMUX0.DELAY |
| PIPETX1EQCOEFF15 | input | CELL95.IMUX.IMUX1.DELAY |
| PIPETX1EQCOEFF16 | input | CELL95.IMUX.IMUX2.DELAY |
| PIPETX1EQCOEFF17 | input | CELL95.IMUX.IMUX3.DELAY |
| PIPETX1EQCOEFF2 | input | CELL92.IMUX.IMUX0.DELAY |
| PIPETX1EQCOEFF3 | input | CELL92.IMUX.IMUX1.DELAY |
| PIPETX1EQCOEFF4 | input | CELL92.IMUX.IMUX2.DELAY |
| PIPETX1EQCOEFF5 | input | CELL92.IMUX.IMUX3.DELAY |
| PIPETX1EQCOEFF6 | input | CELL93.IMUX.IMUX0.DELAY |
| PIPETX1EQCOEFF7 | input | CELL93.IMUX.IMUX1.DELAY |
| PIPETX1EQCOEFF8 | input | CELL93.IMUX.IMUX2.DELAY |
| PIPETX1EQCOEFF9 | input | CELL93.IMUX.IMUX3.DELAY |
| PIPETX1EQCONTROL0 | output | CELL77.OUT1.TMIN |
| PIPETX1EQCONTROL1 | output | CELL77.OUT3.TMIN |
| PIPETX1EQDEEMPH0 | output | CELL90.OUT1.TMIN |
| PIPETX1EQDEEMPH1 | output | CELL90.OUT3.TMIN |
| PIPETX1EQDEEMPH2 | output | CELL90.OUT5.TMIN |
| PIPETX1EQDEEMPH3 | output | CELL90.OUT7.TMIN |
| PIPETX1EQDEEMPH4 | output | CELL91.OUT1.TMIN |
| PIPETX1EQDEEMPH5 | output | CELL91.OUT3.TMIN |
| PIPETX1EQDONE | input | CELL76.IMUX.IMUX5.DELAY |
| PIPETX1EQPRESET0 | output | CELL81.OUT10.TMIN |
| PIPETX1EQPRESET1 | output | CELL81.OUT12.TMIN |
| PIPETX1EQPRESET2 | output | CELL82.OUT10.TMIN |
| PIPETX1EQPRESET3 | output | CELL82.OUT12.TMIN |
| PIPETX1POWERDOWN0 | output | CELL92.OUT5.TMIN |
| PIPETX1POWERDOWN1 | output | CELL92.OUT7.TMIN |
| PIPETX1STARTBLOCK | output | CELL90.OUT22.TMIN |
| PIPETX1SYNCHEADER0 | output | CELL90.OUT21.TMIN |
| PIPETX1SYNCHEADER1 | output | CELL90.OUT20.TMIN |
| PIPETX2CHARISK0 | output | CELL82.OUT16.TMIN |
| PIPETX2CHARISK1 | output | CELL80.OUT16.TMIN |
| PIPETX2COMPLIANCE | output | CELL83.OUT8.TMIN |
| PIPETX2DATA0 | output | CELL83.OUT9.TMIN |
| PIPETX2DATA1 | output | CELL83.OUT13.TMIN |
| PIPETX2DATA10 | output | CELL81.OUT11.TMIN |
| PIPETX2DATA11 | output | CELL81.OUT15.TMIN |
| PIPETX2DATA12 | output | CELL80.OUT0.TMIN |
| PIPETX2DATA13 | output | CELL80.OUT4.TMIN |
| PIPETX2DATA14 | output | CELL80.OUT2.TMIN |
| PIPETX2DATA15 | output | CELL80.OUT6.TMIN |
| PIPETX2DATA16 | output | CELL79.OUT9.TMIN |
| PIPETX2DATA17 | output | CELL79.OUT13.TMIN |
| PIPETX2DATA18 | output | CELL79.OUT11.TMIN |
| PIPETX2DATA19 | output | CELL79.OUT15.TMIN |
| PIPETX2DATA2 | output | CELL83.OUT11.TMIN |
| PIPETX2DATA20 | output | CELL78.OUT0.TMIN |
| PIPETX2DATA21 | output | CELL78.OUT4.TMIN |
| PIPETX2DATA22 | output | CELL78.OUT2.TMIN |
| PIPETX2DATA23 | output | CELL78.OUT6.TMIN |
| PIPETX2DATA24 | output | CELL77.OUT9.TMIN |
| PIPETX2DATA25 | output | CELL77.OUT13.TMIN |
| PIPETX2DATA26 | output | CELL77.OUT11.TMIN |
| PIPETX2DATA27 | output | CELL77.OUT15.TMIN |
| PIPETX2DATA28 | output | CELL76.OUT0.TMIN |
| PIPETX2DATA29 | output | CELL76.OUT4.TMIN |
| PIPETX2DATA3 | output | CELL83.OUT15.TMIN |
| PIPETX2DATA30 | output | CELL76.OUT2.TMIN |
| PIPETX2DATA31 | output | CELL76.OUT6.TMIN |
| PIPETX2DATA4 | output | CELL82.OUT0.TMIN |
| PIPETX2DATA5 | output | CELL82.OUT4.TMIN |
| PIPETX2DATA6 | output | CELL82.OUT2.TMIN |
| PIPETX2DATA7 | output | CELL82.OUT6.TMIN |
| PIPETX2DATA8 | output | CELL81.OUT9.TMIN |
| PIPETX2DATA9 | output | CELL81.OUT13.TMIN |
| PIPETX2DATAVALID | output | CELL80.OUT23.TMIN |
| PIPETX2ELECIDLE | output | CELL82.OUT3.TMIN |
| PIPETX2EQCOEFF0 | input | CELL96.IMUX.IMUX0.DELAY |
| PIPETX2EQCOEFF1 | input | CELL96.IMUX.IMUX1.DELAY |
| PIPETX2EQCOEFF10 | input | CELL98.IMUX.IMUX2.DELAY |
| PIPETX2EQCOEFF11 | input | CELL98.IMUX.IMUX3.DELAY |
| PIPETX2EQCOEFF12 | input | CELL99.IMUX.IMUX0.DELAY |
| PIPETX2EQCOEFF13 | input | CELL99.IMUX.IMUX1.DELAY |
| PIPETX2EQCOEFF14 | input | CELL99.IMUX.IMUX2.DELAY |
| PIPETX2EQCOEFF15 | input | CELL99.IMUX.IMUX3.DELAY |
| PIPETX2EQCOEFF16 | input | CELL99.IMUX.IMUX4.DELAY |
| PIPETX2EQCOEFF17 | input | CELL99.IMUX.IMUX5.DELAY |
| PIPETX2EQCOEFF2 | input | CELL96.IMUX.IMUX2.DELAY |
| PIPETX2EQCOEFF3 | input | CELL96.IMUX.IMUX3.DELAY |
| PIPETX2EQCOEFF4 | input | CELL97.IMUX.IMUX0.DELAY |
| PIPETX2EQCOEFF5 | input | CELL97.IMUX.IMUX1.DELAY |
| PIPETX2EQCOEFF6 | input | CELL97.IMUX.IMUX2.DELAY |
| PIPETX2EQCOEFF7 | input | CELL97.IMUX.IMUX3.DELAY |
| PIPETX2EQCOEFF8 | input | CELL98.IMUX.IMUX0.DELAY |
| PIPETX2EQCOEFF9 | input | CELL98.IMUX.IMUX1.DELAY |
| PIPETX2EQCONTROL0 | output | CELL77.OUT5.TMIN |
| PIPETX2EQCONTROL1 | output | CELL77.OUT7.TMIN |
| PIPETX2EQDEEMPH0 | output | CELL91.OUT5.TMIN |
| PIPETX2EQDEEMPH1 | output | CELL91.OUT7.TMIN |
| PIPETX2EQDEEMPH2 | output | CELL92.OUT1.TMIN |
| PIPETX2EQDEEMPH3 | output | CELL92.OUT8.TMIN |
| PIPETX2EQDEEMPH4 | output | CELL92.OUT10.TMIN |
| PIPETX2EQDEEMPH5 | output | CELL92.OUT12.TMIN |
| PIPETX2EQDONE | input | CELL76.IMUX.IMUX6.DELAY |
| PIPETX2EQPRESET0 | output | CELL82.OUT14.TMIN |
| PIPETX2EQPRESET1 | output | CELL82.OUT17.TMIN |
| PIPETX2EQPRESET2 | output | CELL83.OUT2.TMIN |
| PIPETX2EQPRESET3 | output | CELL83.OUT3.TMIN |
| PIPETX2POWERDOWN0 | output | CELL82.OUT5.TMIN |
| PIPETX2POWERDOWN1 | output | CELL82.OUT7.TMIN |
| PIPETX2STARTBLOCK | output | CELL80.OUT22.TMIN |
| PIPETX2SYNCHEADER0 | output | CELL80.OUT21.TMIN |
| PIPETX2SYNCHEADER1 | output | CELL80.OUT20.TMIN |
| PIPETX3CHARISK0 | output | CELL81.OUT16.TMIN |
| PIPETX3CHARISK1 | output | CELL79.OUT16.TMIN |
| PIPETX3COMPLIANCE | output | CELL82.OUT8.TMIN |
| PIPETX3DATA0 | output | CELL82.OUT9.TMIN |
| PIPETX3DATA1 | output | CELL82.OUT13.TMIN |
| PIPETX3DATA10 | output | CELL80.OUT11.TMIN |
| PIPETX3DATA11 | output | CELL80.OUT15.TMIN |
| PIPETX3DATA12 | output | CELL79.OUT0.TMIN |
| PIPETX3DATA13 | output | CELL79.OUT4.TMIN |
| PIPETX3DATA14 | output | CELL79.OUT2.TMIN |
| PIPETX3DATA15 | output | CELL79.OUT6.TMIN |
| PIPETX3DATA16 | output | CELL78.OUT9.TMIN |
| PIPETX3DATA17 | output | CELL78.OUT13.TMIN |
| PIPETX3DATA18 | output | CELL78.OUT11.TMIN |
| PIPETX3DATA19 | output | CELL78.OUT15.TMIN |
| PIPETX3DATA2 | output | CELL82.OUT11.TMIN |
| PIPETX3DATA20 | output | CELL77.OUT0.TMIN |
| PIPETX3DATA21 | output | CELL77.OUT4.TMIN |
| PIPETX3DATA22 | output | CELL77.OUT2.TMIN |
| PIPETX3DATA23 | output | CELL77.OUT6.TMIN |
| PIPETX3DATA24 | output | CELL76.OUT9.TMIN |
| PIPETX3DATA25 | output | CELL76.OUT13.TMIN |
| PIPETX3DATA26 | output | CELL76.OUT11.TMIN |
| PIPETX3DATA27 | output | CELL76.OUT15.TMIN |
| PIPETX3DATA28 | output | CELL75.OUT0.TMIN |
| PIPETX3DATA29 | output | CELL75.OUT4.TMIN |
| PIPETX3DATA3 | output | CELL82.OUT15.TMIN |
| PIPETX3DATA30 | output | CELL75.OUT2.TMIN |
| PIPETX3DATA31 | output | CELL75.OUT6.TMIN |
| PIPETX3DATA4 | output | CELL81.OUT0.TMIN |
| PIPETX3DATA5 | output | CELL81.OUT4.TMIN |
| PIPETX3DATA6 | output | CELL81.OUT2.TMIN |
| PIPETX3DATA7 | output | CELL81.OUT6.TMIN |
| PIPETX3DATA8 | output | CELL80.OUT9.TMIN |
| PIPETX3DATA9 | output | CELL80.OUT13.TMIN |
| PIPETX3DATAVALID | output | CELL79.OUT23.TMIN |
| PIPETX3ELECIDLE | output | CELL81.OUT3.TMIN |
| PIPETX3EQCOEFF0 | input | CELL99.IMUX.IMUX6.DELAY |
| PIPETX3EQCOEFF1 | input | CELL99.IMUX.IMUX7.DELAY |
| PIPETX3EQCOEFF10 | input | CELL96.IMUX.IMUX4.DELAY |
| PIPETX3EQCOEFF11 | input | CELL96.IMUX.IMUX5.DELAY |
| PIPETX3EQCOEFF12 | input | CELL96.IMUX.IMUX6.DELAY |
| PIPETX3EQCOEFF13 | input | CELL96.IMUX.IMUX7.DELAY |
| PIPETX3EQCOEFF14 | input | CELL95.IMUX.IMUX4.DELAY |
| PIPETX3EQCOEFF15 | input | CELL95.IMUX.IMUX5.DELAY |
| PIPETX3EQCOEFF16 | input | CELL95.IMUX.IMUX6.DELAY |
| PIPETX3EQCOEFF17 | input | CELL95.IMUX.IMUX7.DELAY |
| PIPETX3EQCOEFF2 | input | CELL98.IMUX.IMUX4.DELAY |
| PIPETX3EQCOEFF3 | input | CELL98.IMUX.IMUX5.DELAY |
| PIPETX3EQCOEFF4 | input | CELL98.IMUX.IMUX6.DELAY |
| PIPETX3EQCOEFF5 | input | CELL98.IMUX.IMUX7.DELAY |
| PIPETX3EQCOEFF6 | input | CELL97.IMUX.IMUX4.DELAY |
| PIPETX3EQCOEFF7 | input | CELL97.IMUX.IMUX5.DELAY |
| PIPETX3EQCOEFF8 | input | CELL97.IMUX.IMUX6.DELAY |
| PIPETX3EQCOEFF9 | input | CELL97.IMUX.IMUX7.DELAY |
| PIPETX3EQCONTROL0 | output | CELL78.OUT1.TMIN |
| PIPETX3EQCONTROL1 | output | CELL78.OUT3.TMIN |
| PIPETX3EQDEEMPH0 | output | CELL93.OUT10.TMIN |
| PIPETX3EQDEEMPH1 | output | CELL93.OUT12.TMIN |
| PIPETX3EQDEEMPH2 | output | CELL93.OUT14.TMIN |
| PIPETX3EQDEEMPH3 | output | CELL93.OUT17.TMIN |
| PIPETX3EQDEEMPH4 | output | CELL94.OUT0.TMIN |
| PIPETX3EQDEEMPH5 | output | CELL94.OUT2.TMIN |
| PIPETX3EQDONE | input | CELL76.IMUX.IMUX7.DELAY |
| PIPETX3EQPRESET0 | output | CELL83.OUT4.TMIN |
| PIPETX3EQPRESET1 | output | CELL83.OUT5.TMIN |
| PIPETX3EQPRESET2 | output | CELL84.OUT0.TMIN |
| PIPETX3EQPRESET3 | output | CELL84.OUT1.TMIN |
| PIPETX3POWERDOWN0 | output | CELL81.OUT5.TMIN |
| PIPETX3POWERDOWN1 | output | CELL81.OUT7.TMIN |
| PIPETX3STARTBLOCK | output | CELL79.OUT22.TMIN |
| PIPETX3SYNCHEADER0 | output | CELL79.OUT21.TMIN |
| PIPETX3SYNCHEADER1 | output | CELL79.OUT20.TMIN |
| PIPETX4CHARISK0 | output | CELL68.OUT16.TMIN |
| PIPETX4CHARISK1 | output | CELL66.OUT16.TMIN |
| PIPETX4COMPLIANCE | output | CELL69.OUT8.TMIN |
| PIPETX4DATA0 | output | CELL69.OUT9.TMIN |
| PIPETX4DATA1 | output | CELL69.OUT13.TMIN |
| PIPETX4DATA10 | output | CELL67.OUT11.TMIN |
| PIPETX4DATA11 | output | CELL67.OUT15.TMIN |
| PIPETX4DATA12 | output | CELL66.OUT0.TMIN |
| PIPETX4DATA13 | output | CELL66.OUT4.TMIN |
| PIPETX4DATA14 | output | CELL66.OUT2.TMIN |
| PIPETX4DATA15 | output | CELL66.OUT6.TMIN |
| PIPETX4DATA16 | output | CELL65.OUT9.TMIN |
| PIPETX4DATA17 | output | CELL65.OUT13.TMIN |
| PIPETX4DATA18 | output | CELL65.OUT11.TMIN |
| PIPETX4DATA19 | output | CELL65.OUT15.TMIN |
| PIPETX4DATA2 | output | CELL69.OUT11.TMIN |
| PIPETX4DATA20 | output | CELL64.OUT0.TMIN |
| PIPETX4DATA21 | output | CELL64.OUT4.TMIN |
| PIPETX4DATA22 | output | CELL64.OUT2.TMIN |
| PIPETX4DATA23 | output | CELL64.OUT6.TMIN |
| PIPETX4DATA24 | output | CELL63.OUT9.TMIN |
| PIPETX4DATA25 | output | CELL63.OUT13.TMIN |
| PIPETX4DATA26 | output | CELL63.OUT11.TMIN |
| PIPETX4DATA27 | output | CELL63.OUT15.TMIN |
| PIPETX4DATA28 | output | CELL62.OUT0.TMIN |
| PIPETX4DATA29 | output | CELL62.OUT4.TMIN |
| PIPETX4DATA3 | output | CELL69.OUT15.TMIN |
| PIPETX4DATA30 | output | CELL62.OUT2.TMIN |
| PIPETX4DATA31 | output | CELL62.OUT6.TMIN |
| PIPETX4DATA4 | output | CELL68.OUT0.TMIN |
| PIPETX4DATA5 | output | CELL68.OUT4.TMIN |
| PIPETX4DATA6 | output | CELL68.OUT2.TMIN |
| PIPETX4DATA7 | output | CELL68.OUT6.TMIN |
| PIPETX4DATA8 | output | CELL67.OUT9.TMIN |
| PIPETX4DATA9 | output | CELL67.OUT13.TMIN |
| PIPETX4DATAVALID | output | CELL66.OUT23.TMIN |
| PIPETX4ELECIDLE | output | CELL68.OUT3.TMIN |
| PIPETX4EQCOEFF0 | input | CELL94.IMUX.IMUX4.DELAY |
| PIPETX4EQCOEFF1 | input | CELL94.IMUX.IMUX5.DELAY |
| PIPETX4EQCOEFF10 | input | CELL92.IMUX.IMUX6.DELAY |
| PIPETX4EQCOEFF11 | input | CELL92.IMUX.IMUX7.DELAY |
| PIPETX4EQCOEFF12 | input | CELL91.IMUX.IMUX4.DELAY |
| PIPETX4EQCOEFF13 | input | CELL91.IMUX.IMUX5.DELAY |
| PIPETX4EQCOEFF14 | input | CELL91.IMUX.IMUX6.DELAY |
| PIPETX4EQCOEFF15 | input | CELL91.IMUX.IMUX7.DELAY |
| PIPETX4EQCOEFF16 | input | CELL90.IMUX.IMUX4.DELAY |
| PIPETX4EQCOEFF17 | input | CELL90.IMUX.IMUX5.DELAY |
| PIPETX4EQCOEFF2 | input | CELL94.IMUX.IMUX6.DELAY |
| PIPETX4EQCOEFF3 | input | CELL94.IMUX.IMUX7.DELAY |
| PIPETX4EQCOEFF4 | input | CELL93.IMUX.IMUX4.DELAY |
| PIPETX4EQCOEFF5 | input | CELL93.IMUX.IMUX5.DELAY |
| PIPETX4EQCOEFF6 | input | CELL93.IMUX.IMUX6.DELAY |
| PIPETX4EQCOEFF7 | input | CELL93.IMUX.IMUX7.DELAY |
| PIPETX4EQCOEFF8 | input | CELL92.IMUX.IMUX4.DELAY |
| PIPETX4EQCOEFF9 | input | CELL92.IMUX.IMUX5.DELAY |
| PIPETX4EQCONTROL0 | output | CELL78.OUT5.TMIN |
| PIPETX4EQCONTROL1 | output | CELL78.OUT7.TMIN |
| PIPETX4EQDEEMPH0 | output | CELL94.OUT3.TMIN |
| PIPETX4EQDEEMPH1 | output | CELL94.OUT4.TMIN |
| PIPETX4EQDEEMPH2 | output | CELL95.OUT0.TMIN |
| PIPETX4EQDEEMPH3 | output | CELL95.OUT1.TMIN |
| PIPETX4EQDEEMPH4 | output | CELL95.OUT2.TMIN |
| PIPETX4EQDEEMPH5 | output | CELL95.OUT3.TMIN |
| PIPETX4EQDONE | input | CELL75.IMUX.IMUX4.DELAY |
| PIPETX4EQPRESET0 | output | CELL84.OUT2.TMIN |
| PIPETX4EQPRESET1 | output | CELL84.OUT3.TMIN |
| PIPETX4EQPRESET2 | output | CELL85.OUT0.TMIN |
| PIPETX4EQPRESET3 | output | CELL85.OUT1.TMIN |
| PIPETX4POWERDOWN0 | output | CELL68.OUT5.TMIN |
| PIPETX4POWERDOWN1 | output | CELL68.OUT7.TMIN |
| PIPETX4STARTBLOCK | output | CELL66.OUT22.TMIN |
| PIPETX4SYNCHEADER0 | output | CELL66.OUT21.TMIN |
| PIPETX4SYNCHEADER1 | output | CELL66.OUT20.TMIN |
| PIPETX5CHARISK0 | output | CELL67.OUT16.TMIN |
| PIPETX5CHARISK1 | output | CELL65.OUT16.TMIN |
| PIPETX5COMPLIANCE | output | CELL68.OUT8.TMIN |
| PIPETX5DATA0 | output | CELL68.OUT9.TMIN |
| PIPETX5DATA1 | output | CELL68.OUT13.TMIN |
| PIPETX5DATA10 | output | CELL66.OUT11.TMIN |
| PIPETX5DATA11 | output | CELL66.OUT15.TMIN |
| PIPETX5DATA12 | output | CELL65.OUT0.TMIN |
| PIPETX5DATA13 | output | CELL65.OUT4.TMIN |
| PIPETX5DATA14 | output | CELL65.OUT2.TMIN |
| PIPETX5DATA15 | output | CELL65.OUT6.TMIN |
| PIPETX5DATA16 | output | CELL64.OUT9.TMIN |
| PIPETX5DATA17 | output | CELL64.OUT13.TMIN |
| PIPETX5DATA18 | output | CELL64.OUT11.TMIN |
| PIPETX5DATA19 | output | CELL64.OUT15.TMIN |
| PIPETX5DATA2 | output | CELL68.OUT11.TMIN |
| PIPETX5DATA20 | output | CELL63.OUT0.TMIN |
| PIPETX5DATA21 | output | CELL63.OUT4.TMIN |
| PIPETX5DATA22 | output | CELL63.OUT2.TMIN |
| PIPETX5DATA23 | output | CELL63.OUT6.TMIN |
| PIPETX5DATA24 | output | CELL62.OUT9.TMIN |
| PIPETX5DATA25 | output | CELL62.OUT13.TMIN |
| PIPETX5DATA26 | output | CELL62.OUT11.TMIN |
| PIPETX5DATA27 | output | CELL62.OUT15.TMIN |
| PIPETX5DATA28 | output | CELL61.OUT0.TMIN |
| PIPETX5DATA29 | output | CELL61.OUT4.TMIN |
| PIPETX5DATA3 | output | CELL68.OUT15.TMIN |
| PIPETX5DATA30 | output | CELL61.OUT2.TMIN |
| PIPETX5DATA31 | output | CELL61.OUT6.TMIN |
| PIPETX5DATA4 | output | CELL67.OUT0.TMIN |
| PIPETX5DATA5 | output | CELL67.OUT4.TMIN |
| PIPETX5DATA6 | output | CELL67.OUT2.TMIN |
| PIPETX5DATA7 | output | CELL67.OUT6.TMIN |
| PIPETX5DATA8 | output | CELL66.OUT9.TMIN |
| PIPETX5DATA9 | output | CELL66.OUT13.TMIN |
| PIPETX5DATAVALID | output | CELL65.OUT23.TMIN |
| PIPETX5ELECIDLE | output | CELL67.OUT3.TMIN |
| PIPETX5EQCOEFF0 | input | CELL90.IMUX.IMUX6.DELAY |
| PIPETX5EQCOEFF1 | input | CELL90.IMUX.IMUX7.DELAY |
| PIPETX5EQCOEFF10 | input | CELL87.IMUX.IMUX4.DELAY |
| PIPETX5EQCOEFF11 | input | CELL87.IMUX.IMUX5.DELAY |
| PIPETX5EQCOEFF12 | input | CELL87.IMUX.IMUX6.DELAY |
| PIPETX5EQCOEFF13 | input | CELL87.IMUX.IMUX7.DELAY |
| PIPETX5EQCOEFF14 | input | CELL86.IMUX.IMUX4.DELAY |
| PIPETX5EQCOEFF15 | input | CELL86.IMUX.IMUX5.DELAY |
| PIPETX5EQCOEFF16 | input | CELL86.IMUX.IMUX6.DELAY |
| PIPETX5EQCOEFF17 | input | CELL86.IMUX.IMUX7.DELAY |
| PIPETX5EQCOEFF2 | input | CELL89.IMUX.IMUX4.DELAY |
| PIPETX5EQCOEFF3 | input | CELL89.IMUX.IMUX5.DELAY |
| PIPETX5EQCOEFF4 | input | CELL89.IMUX.IMUX6.DELAY |
| PIPETX5EQCOEFF5 | input | CELL89.IMUX.IMUX7.DELAY |
| PIPETX5EQCOEFF6 | input | CELL88.IMUX.IMUX4.DELAY |
| PIPETX5EQCOEFF7 | input | CELL88.IMUX.IMUX5.DELAY |
| PIPETX5EQCOEFF8 | input | CELL88.IMUX.IMUX6.DELAY |
| PIPETX5EQCOEFF9 | input | CELL88.IMUX.IMUX7.DELAY |
| PIPETX5EQCONTROL0 | output | CELL79.OUT1.TMIN |
| PIPETX5EQCONTROL1 | output | CELL79.OUT3.TMIN |
| PIPETX5EQDEEMPH0 | output | CELL96.OUT0.TMIN |
| PIPETX5EQDEEMPH1 | output | CELL96.OUT1.TMIN |
| PIPETX5EQDEEMPH2 | output | CELL96.OUT2.TMIN |
| PIPETX5EQDEEMPH3 | output | CELL96.OUT3.TMIN |
| PIPETX5EQDEEMPH4 | output | CELL97.OUT0.TMIN |
| PIPETX5EQDEEMPH5 | output | CELL97.OUT1.TMIN |
| PIPETX5EQDONE | input | CELL75.IMUX.IMUX5.DELAY |
| PIPETX5EQPRESET0 | output | CELL85.OUT2.TMIN |
| PIPETX5EQPRESET1 | output | CELL85.OUT3.TMIN |
| PIPETX5EQPRESET2 | output | CELL86.OUT1.TMIN |
| PIPETX5EQPRESET3 | output | CELL86.OUT3.TMIN |
| PIPETX5POWERDOWN0 | output | CELL67.OUT5.TMIN |
| PIPETX5POWERDOWN1 | output | CELL67.OUT7.TMIN |
| PIPETX5STARTBLOCK | output | CELL65.OUT22.TMIN |
| PIPETX5SYNCHEADER0 | output | CELL65.OUT21.TMIN |
| PIPETX5SYNCHEADER1 | output | CELL65.OUT20.TMIN |
| PIPETX6CHARISK0 | output | CELL57.OUT16.TMIN |
| PIPETX6CHARISK1 | output | CELL55.OUT16.TMIN |
| PIPETX6COMPLIANCE | output | CELL58.OUT8.TMIN |
| PIPETX6DATA0 | output | CELL58.OUT9.TMIN |
| PIPETX6DATA1 | output | CELL58.OUT13.TMIN |
| PIPETX6DATA10 | output | CELL56.OUT11.TMIN |
| PIPETX6DATA11 | output | CELL56.OUT15.TMIN |
| PIPETX6DATA12 | output | CELL55.OUT0.TMIN |
| PIPETX6DATA13 | output | CELL55.OUT4.TMIN |
| PIPETX6DATA14 | output | CELL55.OUT2.TMIN |
| PIPETX6DATA15 | output | CELL55.OUT6.TMIN |
| PIPETX6DATA16 | output | CELL54.OUT9.TMIN |
| PIPETX6DATA17 | output | CELL54.OUT13.TMIN |
| PIPETX6DATA18 | output | CELL54.OUT11.TMIN |
| PIPETX6DATA19 | output | CELL54.OUT15.TMIN |
| PIPETX6DATA2 | output | CELL58.OUT11.TMIN |
| PIPETX6DATA20 | output | CELL53.OUT0.TMIN |
| PIPETX6DATA21 | output | CELL53.OUT4.TMIN |
| PIPETX6DATA22 | output | CELL53.OUT2.TMIN |
| PIPETX6DATA23 | output | CELL53.OUT6.TMIN |
| PIPETX6DATA24 | output | CELL52.OUT9.TMIN |
| PIPETX6DATA25 | output | CELL52.OUT13.TMIN |
| PIPETX6DATA26 | output | CELL52.OUT11.TMIN |
| PIPETX6DATA27 | output | CELL52.OUT15.TMIN |
| PIPETX6DATA28 | output | CELL51.OUT0.TMIN |
| PIPETX6DATA29 | output | CELL51.OUT4.TMIN |
| PIPETX6DATA3 | output | CELL58.OUT15.TMIN |
| PIPETX6DATA30 | output | CELL51.OUT2.TMIN |
| PIPETX6DATA31 | output | CELL51.OUT6.TMIN |
| PIPETX6DATA4 | output | CELL57.OUT0.TMIN |
| PIPETX6DATA5 | output | CELL57.OUT4.TMIN |
| PIPETX6DATA6 | output | CELL57.OUT2.TMIN |
| PIPETX6DATA7 | output | CELL57.OUT6.TMIN |
| PIPETX6DATA8 | output | CELL56.OUT9.TMIN |
| PIPETX6DATA9 | output | CELL56.OUT13.TMIN |
| PIPETX6DATAVALID | output | CELL55.OUT23.TMIN |
| PIPETX6ELECIDLE | output | CELL57.OUT3.TMIN |
| PIPETX6EQCOEFF0 | input | CELL85.IMUX.IMUX4.DELAY |
| PIPETX6EQCOEFF1 | input | CELL85.IMUX.IMUX5.DELAY |
| PIPETX6EQCOEFF10 | input | CELL83.IMUX.IMUX6.DELAY |
| PIPETX6EQCOEFF11 | input | CELL83.IMUX.IMUX7.DELAY |
| PIPETX6EQCOEFF12 | input | CELL82.IMUX.IMUX4.DELAY |
| PIPETX6EQCOEFF13 | input | CELL82.IMUX.IMUX5.DELAY |
| PIPETX6EQCOEFF14 | input | CELL82.IMUX.IMUX6.DELAY |
| PIPETX6EQCOEFF15 | input | CELL82.IMUX.IMUX7.DELAY |
| PIPETX6EQCOEFF16 | input | CELL81.IMUX.IMUX4.DELAY |
| PIPETX6EQCOEFF17 | input | CELL81.IMUX.IMUX5.DELAY |
| PIPETX6EQCOEFF2 | input | CELL85.IMUX.IMUX6.DELAY |
| PIPETX6EQCOEFF3 | input | CELL85.IMUX.IMUX7.DELAY |
| PIPETX6EQCOEFF4 | input | CELL84.IMUX.IMUX4.DELAY |
| PIPETX6EQCOEFF5 | input | CELL84.IMUX.IMUX5.DELAY |
| PIPETX6EQCOEFF6 | input | CELL84.IMUX.IMUX6.DELAY |
| PIPETX6EQCOEFF7 | input | CELL84.IMUX.IMUX7.DELAY |
| PIPETX6EQCOEFF8 | input | CELL83.IMUX.IMUX4.DELAY |
| PIPETX6EQCOEFF9 | input | CELL83.IMUX.IMUX5.DELAY |
| PIPETX6EQCONTROL0 | output | CELL79.OUT5.TMIN |
| PIPETX6EQCONTROL1 | output | CELL79.OUT7.TMIN |
| PIPETX6EQDEEMPH0 | output | CELL97.OUT2.TMIN |
| PIPETX6EQDEEMPH1 | output | CELL97.OUT3.TMIN |
| PIPETX6EQDEEMPH2 | output | CELL98.OUT0.TMIN |
| PIPETX6EQDEEMPH3 | output | CELL98.OUT1.TMIN |
| PIPETX6EQDEEMPH4 | output | CELL98.OUT2.TMIN |
| PIPETX6EQDEEMPH5 | output | CELL98.OUT3.TMIN |
| PIPETX6EQDONE | input | CELL75.IMUX.IMUX6.DELAY |
| PIPETX6EQPRESET0 | output | CELL86.OUT5.TMIN |
| PIPETX6EQPRESET1 | output | CELL86.OUT7.TMIN |
| PIPETX6EQPRESET2 | output | CELL87.OUT1.TMIN |
| PIPETX6EQPRESET3 | output | CELL87.OUT3.TMIN |
| PIPETX6POWERDOWN0 | output | CELL57.OUT5.TMIN |
| PIPETX6POWERDOWN1 | output | CELL57.OUT7.TMIN |
| PIPETX6STARTBLOCK | output | CELL55.OUT22.TMIN |
| PIPETX6SYNCHEADER0 | output | CELL55.OUT21.TMIN |
| PIPETX6SYNCHEADER1 | output | CELL55.OUT20.TMIN |
| PIPETX7CHARISK0 | output | CELL56.OUT16.TMIN |
| PIPETX7CHARISK1 | output | CELL54.OUT16.TMIN |
| PIPETX7COMPLIANCE | output | CELL57.OUT8.TMIN |
| PIPETX7DATA0 | output | CELL57.OUT9.TMIN |
| PIPETX7DATA1 | output | CELL57.OUT13.TMIN |
| PIPETX7DATA10 | output | CELL55.OUT11.TMIN |
| PIPETX7DATA11 | output | CELL55.OUT15.TMIN |
| PIPETX7DATA12 | output | CELL54.OUT0.TMIN |
| PIPETX7DATA13 | output | CELL54.OUT4.TMIN |
| PIPETX7DATA14 | output | CELL54.OUT2.TMIN |
| PIPETX7DATA15 | output | CELL54.OUT6.TMIN |
| PIPETX7DATA16 | output | CELL53.OUT9.TMIN |
| PIPETX7DATA17 | output | CELL53.OUT13.TMIN |
| PIPETX7DATA18 | output | CELL53.OUT11.TMIN |
| PIPETX7DATA19 | output | CELL53.OUT15.TMIN |
| PIPETX7DATA2 | output | CELL57.OUT11.TMIN |
| PIPETX7DATA20 | output | CELL52.OUT0.TMIN |
| PIPETX7DATA21 | output | CELL52.OUT4.TMIN |
| PIPETX7DATA22 | output | CELL52.OUT2.TMIN |
| PIPETX7DATA23 | output | CELL52.OUT6.TMIN |
| PIPETX7DATA24 | output | CELL51.OUT9.TMIN |
| PIPETX7DATA25 | output | CELL51.OUT13.TMIN |
| PIPETX7DATA26 | output | CELL51.OUT11.TMIN |
| PIPETX7DATA27 | output | CELL51.OUT15.TMIN |
| PIPETX7DATA28 | output | CELL50.OUT0.TMIN |
| PIPETX7DATA29 | output | CELL50.OUT4.TMIN |
| PIPETX7DATA3 | output | CELL57.OUT15.TMIN |
| PIPETX7DATA30 | output | CELL50.OUT2.TMIN |
| PIPETX7DATA31 | output | CELL50.OUT6.TMIN |
| PIPETX7DATA4 | output | CELL56.OUT0.TMIN |
| PIPETX7DATA5 | output | CELL56.OUT4.TMIN |
| PIPETX7DATA6 | output | CELL56.OUT2.TMIN |
| PIPETX7DATA7 | output | CELL56.OUT6.TMIN |
| PIPETX7DATA8 | output | CELL55.OUT9.TMIN |
| PIPETX7DATA9 | output | CELL55.OUT13.TMIN |
| PIPETX7DATAVALID | output | CELL54.OUT23.TMIN |
| PIPETX7ELECIDLE | output | CELL56.OUT3.TMIN |
| PIPETX7EQCOEFF0 | input | CELL81.IMUX.IMUX6.DELAY |
| PIPETX7EQCOEFF1 | input | CELL81.IMUX.IMUX7.DELAY |
| PIPETX7EQCOEFF10 | input | CELL78.IMUX.IMUX4.DELAY |
| PIPETX7EQCOEFF11 | input | CELL78.IMUX.IMUX5.DELAY |
| PIPETX7EQCOEFF12 | input | CELL78.IMUX.IMUX6.DELAY |
| PIPETX7EQCOEFF13 | input | CELL78.IMUX.IMUX7.DELAY |
| PIPETX7EQCOEFF14 | input | CELL77.IMUX.IMUX4.DELAY |
| PIPETX7EQCOEFF15 | input | CELL77.IMUX.IMUX5.DELAY |
| PIPETX7EQCOEFF16 | input | CELL77.IMUX.IMUX6.DELAY |
| PIPETX7EQCOEFF17 | input | CELL77.IMUX.IMUX7.DELAY |
| PIPETX7EQCOEFF2 | input | CELL80.IMUX.IMUX4.DELAY |
| PIPETX7EQCOEFF3 | input | CELL80.IMUX.IMUX5.DELAY |
| PIPETX7EQCOEFF4 | input | CELL80.IMUX.IMUX6.DELAY |
| PIPETX7EQCOEFF5 | input | CELL80.IMUX.IMUX7.DELAY |
| PIPETX7EQCOEFF6 | input | CELL79.IMUX.IMUX4.DELAY |
| PIPETX7EQCOEFF7 | input | CELL79.IMUX.IMUX5.DELAY |
| PIPETX7EQCOEFF8 | input | CELL79.IMUX.IMUX6.DELAY |
| PIPETX7EQCOEFF9 | input | CELL79.IMUX.IMUX7.DELAY |
| PIPETX7EQCONTROL0 | output | CELL80.OUT1.TMIN |
| PIPETX7EQCONTROL1 | output | CELL80.OUT3.TMIN |
| PIPETX7EQDEEMPH0 | output | CELL99.OUT0.TMIN |
| PIPETX7EQDEEMPH1 | output | CELL99.OUT1.TMIN |
| PIPETX7EQDEEMPH2 | output | CELL99.OUT2.TMIN |
| PIPETX7EQDEEMPH3 | output | CELL99.OUT3.TMIN |
| PIPETX7EQDEEMPH4 | output | CELL99.OUT4.TMIN |
| PIPETX7EQDEEMPH5 | output | CELL99.OUT5.TMIN |
| PIPETX7EQDONE | input | CELL75.IMUX.IMUX7.DELAY |
| PIPETX7EQPRESET0 | output | CELL87.OUT5.TMIN |
| PIPETX7EQPRESET1 | output | CELL87.OUT7.TMIN |
| PIPETX7EQPRESET2 | output | CELL88.OUT1.TMIN |
| PIPETX7EQPRESET3 | output | CELL88.OUT3.TMIN |
| PIPETX7POWERDOWN0 | output | CELL56.OUT5.TMIN |
| PIPETX7POWERDOWN1 | output | CELL56.OUT7.TMIN |
| PIPETX7STARTBLOCK | output | CELL54.OUT22.TMIN |
| PIPETX7SYNCHEADER0 | output | CELL54.OUT21.TMIN |
| PIPETX7SYNCHEADER1 | output | CELL54.OUT20.TMIN |
| PIPETXDEEMPH | output | CELL83.OUT0.TMIN |
| PIPETXMARGIN0 | output | CELL70.OUT18.TMIN |
| PIPETXMARGIN1 | output | CELL70.OUT16.TMIN |
| PIPETXMARGIN2 | output | CELL70.OUT6.TMIN |
| PIPETXRATE0 | output | CELL86.OUT19.TMIN |
| PIPETXRATE1 | output | CELL99.OUT6.TMIN |
| PIPETXRCVRDET | output | CELL84.OUT15.TMIN |
| PIPETXRESET | output | CELL86.OUT9.TMIN |
| PIPETXSWING | output | CELL99.OUT7.TMIN |
| PLDISABLESCRAMBLER | input | CELL71.IMUX.IMUX5.DELAY |
| PLEQINPROGRESS | output | CELL98.OUT4.TMIN |
| PLEQPHASE0 | output | CELL98.OUT5.TMIN |
| PLEQPHASE1 | output | CELL98.OUT6.TMIN |
| PLEQRESETEIEOSCOUNT | input | CELL71.IMUX.IMUX4.DELAY |
| PLGEN3PCSDISABLE | input | CELL71.IMUX.IMUX6.DELAY |
| PLGEN3PCSRXSLIDE0 | output | CELL98.OUT7.TMIN |
| PLGEN3PCSRXSLIDE1 | output | CELL97.OUT4.TMIN |
| PLGEN3PCSRXSLIDE2 | output | CELL97.OUT5.TMIN |
| PLGEN3PCSRXSLIDE3 | output | CELL97.OUT6.TMIN |
| PLGEN3PCSRXSLIDE4 | output | CELL97.OUT7.TMIN |
| PLGEN3PCSRXSLIDE5 | output | CELL96.OUT4.TMIN |
| PLGEN3PCSRXSLIDE6 | output | CELL96.OUT5.TMIN |
| PLGEN3PCSRXSLIDE7 | output | CELL96.OUT6.TMIN |
| PLGEN3PCSRXSYNCDONE0 | input | CELL71.IMUX.IMUX7.DELAY |
| PLGEN3PCSRXSYNCDONE1 | input | CELL70.IMUX.IMUX4.DELAY |
| PLGEN3PCSRXSYNCDONE2 | input | CELL70.IMUX.IMUX5.DELAY |
| PLGEN3PCSRXSYNCDONE3 | input | CELL70.IMUX.IMUX6.DELAY |
| PLGEN3PCSRXSYNCDONE4 | input | CELL70.IMUX.IMUX7.DELAY |
| PLGEN3PCSRXSYNCDONE5 | input | CELL69.IMUX.IMUX4.DELAY |
| PLGEN3PCSRXSYNCDONE6 | input | CELL69.IMUX.IMUX5.DELAY |
| PLGEN3PCSRXSYNCDONE7 | input | CELL69.IMUX.IMUX6.DELAY |
| RECCLK | input | CELL75.IMUX.CLK1 |
| RESETN | input | CELL15.IMUX.IMUX20.DELAY |
| SAXISCCTDATA0 | input | CELL69.IMUX.IMUX7.DELAY |
| SAXISCCTDATA1 | input | CELL68.IMUX.IMUX4.DELAY |
| SAXISCCTDATA10 | input | CELL66.IMUX.IMUX5.DELAY |
| SAXISCCTDATA100 | input | CELL57.IMUX.IMUX11.DELAY |
| SAXISCCTDATA101 | input | CELL58.IMUX.IMUX8.DELAY |
| SAXISCCTDATA102 | input | CELL58.IMUX.IMUX9.DELAY |
| SAXISCCTDATA103 | input | CELL58.IMUX.IMUX10.DELAY |
| SAXISCCTDATA104 | input | CELL59.IMUX.IMUX8.DELAY |
| SAXISCCTDATA105 | input | CELL60.IMUX.IMUX8.DELAY |
| SAXISCCTDATA106 | input | CELL60.IMUX.IMUX9.DELAY |
| SAXISCCTDATA107 | input | CELL60.IMUX.IMUX10.DELAY |
| SAXISCCTDATA108 | input | CELL60.IMUX.IMUX11.DELAY |
| SAXISCCTDATA109 | input | CELL61.IMUX.IMUX8.DELAY |
| SAXISCCTDATA11 | input | CELL66.IMUX.IMUX6.DELAY |
| SAXISCCTDATA110 | input | CELL61.IMUX.IMUX9.DELAY |
| SAXISCCTDATA111 | input | CELL61.IMUX.IMUX10.DELAY |
| SAXISCCTDATA112 | input | CELL61.IMUX.IMUX11.DELAY |
| SAXISCCTDATA113 | input | CELL62.IMUX.IMUX8.DELAY |
| SAXISCCTDATA114 | input | CELL62.IMUX.IMUX9.DELAY |
| SAXISCCTDATA115 | input | CELL62.IMUX.IMUX10.DELAY |
| SAXISCCTDATA116 | input | CELL62.IMUX.IMUX11.DELAY |
| SAXISCCTDATA117 | input | CELL63.IMUX.IMUX8.DELAY |
| SAXISCCTDATA118 | input | CELL63.IMUX.IMUX9.DELAY |
| SAXISCCTDATA119 | input | CELL63.IMUX.IMUX10.DELAY |
| SAXISCCTDATA12 | input | CELL66.IMUX.IMUX7.DELAY |
| SAXISCCTDATA120 | input | CELL63.IMUX.IMUX11.DELAY |
| SAXISCCTDATA121 | input | CELL64.IMUX.IMUX8.DELAY |
| SAXISCCTDATA122 | input | CELL64.IMUX.IMUX9.DELAY |
| SAXISCCTDATA123 | input | CELL64.IMUX.IMUX10.DELAY |
| SAXISCCTDATA124 | input | CELL64.IMUX.IMUX11.DELAY |
| SAXISCCTDATA125 | input | CELL65.IMUX.IMUX8.DELAY |
| SAXISCCTDATA126 | input | CELL65.IMUX.IMUX9.DELAY |
| SAXISCCTDATA127 | input | CELL65.IMUX.IMUX10.DELAY |
| SAXISCCTDATA128 | input | CELL65.IMUX.IMUX11.DELAY |
| SAXISCCTDATA129 | input | CELL66.IMUX.IMUX8.DELAY |
| SAXISCCTDATA13 | input | CELL65.IMUX.IMUX4.DELAY |
| SAXISCCTDATA130 | input | CELL66.IMUX.IMUX9.DELAY |
| SAXISCCTDATA131 | input | CELL66.IMUX.IMUX10.DELAY |
| SAXISCCTDATA132 | input | CELL66.IMUX.IMUX11.DELAY |
| SAXISCCTDATA133 | input | CELL67.IMUX.IMUX8.DELAY |
| SAXISCCTDATA134 | input | CELL67.IMUX.IMUX9.DELAY |
| SAXISCCTDATA135 | input | CELL67.IMUX.IMUX10.DELAY |
| SAXISCCTDATA136 | input | CELL67.IMUX.IMUX11.DELAY |
| SAXISCCTDATA137 | input | CELL68.IMUX.IMUX8.DELAY |
| SAXISCCTDATA138 | input | CELL68.IMUX.IMUX9.DELAY |
| SAXISCCTDATA139 | input | CELL68.IMUX.IMUX10.DELAY |
| SAXISCCTDATA14 | input | CELL65.IMUX.IMUX5.DELAY |
| SAXISCCTDATA140 | input | CELL68.IMUX.IMUX11.DELAY |
| SAXISCCTDATA141 | input | CELL69.IMUX.IMUX8.DELAY |
| SAXISCCTDATA142 | input | CELL69.IMUX.IMUX9.DELAY |
| SAXISCCTDATA143 | input | CELL69.IMUX.IMUX10.DELAY |
| SAXISCCTDATA144 | input | CELL70.IMUX.IMUX8.DELAY |
| SAXISCCTDATA145 | input | CELL71.IMUX.IMUX8.DELAY |
| SAXISCCTDATA146 | input | CELL71.IMUX.IMUX9.DELAY |
| SAXISCCTDATA147 | input | CELL71.IMUX.IMUX10.DELAY |
| SAXISCCTDATA148 | input | CELL71.IMUX.IMUX11.DELAY |
| SAXISCCTDATA149 | input | CELL72.IMUX.IMUX8.DELAY |
| SAXISCCTDATA15 | input | CELL65.IMUX.IMUX6.DELAY |
| SAXISCCTDATA150 | input | CELL72.IMUX.IMUX9.DELAY |
| SAXISCCTDATA151 | input | CELL72.IMUX.IMUX10.DELAY |
| SAXISCCTDATA152 | input | CELL72.IMUX.IMUX11.DELAY |
| SAXISCCTDATA153 | input | CELL73.IMUX.IMUX8.DELAY |
| SAXISCCTDATA154 | input | CELL73.IMUX.IMUX9.DELAY |
| SAXISCCTDATA155 | input | CELL73.IMUX.IMUX10.DELAY |
| SAXISCCTDATA156 | input | CELL73.IMUX.IMUX11.DELAY |
| SAXISCCTDATA157 | input | CELL74.IMUX.IMUX8.DELAY |
| SAXISCCTDATA158 | input | CELL74.IMUX.IMUX9.DELAY |
| SAXISCCTDATA159 | input | CELL74.IMUX.IMUX10.DELAY |
| SAXISCCTDATA16 | input | CELL65.IMUX.IMUX7.DELAY |
| SAXISCCTDATA160 | input | CELL74.IMUX.IMUX11.DELAY |
| SAXISCCTDATA161 | input | CELL75.IMUX.IMUX8.DELAY |
| SAXISCCTDATA162 | input | CELL75.IMUX.IMUX9.DELAY |
| SAXISCCTDATA163 | input | CELL75.IMUX.IMUX10.DELAY |
| SAXISCCTDATA164 | input | CELL75.IMUX.IMUX11.DELAY |
| SAXISCCTDATA165 | input | CELL76.IMUX.IMUX8.DELAY |
| SAXISCCTDATA166 | input | CELL76.IMUX.IMUX9.DELAY |
| SAXISCCTDATA167 | input | CELL76.IMUX.IMUX10.DELAY |
| SAXISCCTDATA168 | input | CELL76.IMUX.IMUX11.DELAY |
| SAXISCCTDATA169 | input | CELL77.IMUX.IMUX8.DELAY |
| SAXISCCTDATA17 | input | CELL64.IMUX.IMUX4.DELAY |
| SAXISCCTDATA170 | input | CELL77.IMUX.IMUX9.DELAY |
| SAXISCCTDATA171 | input | CELL77.IMUX.IMUX10.DELAY |
| SAXISCCTDATA172 | input | CELL77.IMUX.IMUX11.DELAY |
| SAXISCCTDATA173 | input | CELL78.IMUX.IMUX8.DELAY |
| SAXISCCTDATA174 | input | CELL78.IMUX.IMUX9.DELAY |
| SAXISCCTDATA175 | input | CELL78.IMUX.IMUX10.DELAY |
| SAXISCCTDATA176 | input | CELL78.IMUX.IMUX11.DELAY |
| SAXISCCTDATA177 | input | CELL79.IMUX.IMUX8.DELAY |
| SAXISCCTDATA178 | input | CELL79.IMUX.IMUX9.DELAY |
| SAXISCCTDATA179 | input | CELL79.IMUX.IMUX10.DELAY |
| SAXISCCTDATA18 | input | CELL64.IMUX.IMUX5.DELAY |
| SAXISCCTDATA180 | input | CELL79.IMUX.IMUX11.DELAY |
| SAXISCCTDATA181 | input | CELL80.IMUX.IMUX8.DELAY |
| SAXISCCTDATA182 | input | CELL80.IMUX.IMUX9.DELAY |
| SAXISCCTDATA183 | input | CELL80.IMUX.IMUX10.DELAY |
| SAXISCCTDATA184 | input | CELL80.IMUX.IMUX11.DELAY |
| SAXISCCTDATA185 | input | CELL81.IMUX.IMUX8.DELAY |
| SAXISCCTDATA186 | input | CELL81.IMUX.IMUX9.DELAY |
| SAXISCCTDATA187 | input | CELL81.IMUX.IMUX10.DELAY |
| SAXISCCTDATA188 | input | CELL81.IMUX.IMUX11.DELAY |
| SAXISCCTDATA189 | input | CELL82.IMUX.IMUX8.DELAY |
| SAXISCCTDATA19 | input | CELL64.IMUX.IMUX6.DELAY |
| SAXISCCTDATA190 | input | CELL82.IMUX.IMUX9.DELAY |
| SAXISCCTDATA191 | input | CELL82.IMUX.IMUX10.DELAY |
| SAXISCCTDATA192 | input | CELL82.IMUX.IMUX11.DELAY |
| SAXISCCTDATA193 | input | CELL83.IMUX.IMUX8.DELAY |
| SAXISCCTDATA194 | input | CELL83.IMUX.IMUX9.DELAY |
| SAXISCCTDATA195 | input | CELL83.IMUX.IMUX10.DELAY |
| SAXISCCTDATA196 | input | CELL84.IMUX.IMUX8.DELAY |
| SAXISCCTDATA197 | input | CELL85.IMUX.IMUX8.DELAY |
| SAXISCCTDATA198 | input | CELL85.IMUX.IMUX9.DELAY |
| SAXISCCTDATA199 | input | CELL85.IMUX.IMUX10.DELAY |
| SAXISCCTDATA2 | input | CELL68.IMUX.IMUX5.DELAY |
| SAXISCCTDATA20 | input | CELL64.IMUX.IMUX7.DELAY |
| SAXISCCTDATA200 | input | CELL85.IMUX.IMUX11.DELAY |
| SAXISCCTDATA201 | input | CELL86.IMUX.IMUX8.DELAY |
| SAXISCCTDATA202 | input | CELL86.IMUX.IMUX9.DELAY |
| SAXISCCTDATA203 | input | CELL86.IMUX.IMUX10.DELAY |
| SAXISCCTDATA204 | input | CELL86.IMUX.IMUX11.DELAY |
| SAXISCCTDATA205 | input | CELL87.IMUX.IMUX8.DELAY |
| SAXISCCTDATA206 | input | CELL87.IMUX.IMUX9.DELAY |
| SAXISCCTDATA207 | input | CELL87.IMUX.IMUX10.DELAY |
| SAXISCCTDATA208 | input | CELL87.IMUX.IMUX11.DELAY |
| SAXISCCTDATA209 | input | CELL88.IMUX.IMUX8.DELAY |
| SAXISCCTDATA21 | input | CELL63.IMUX.IMUX4.DELAY |
| SAXISCCTDATA210 | input | CELL88.IMUX.IMUX9.DELAY |
| SAXISCCTDATA211 | input | CELL88.IMUX.IMUX10.DELAY |
| SAXISCCTDATA212 | input | CELL88.IMUX.IMUX11.DELAY |
| SAXISCCTDATA213 | input | CELL89.IMUX.IMUX8.DELAY |
| SAXISCCTDATA214 | input | CELL89.IMUX.IMUX9.DELAY |
| SAXISCCTDATA215 | input | CELL89.IMUX.IMUX10.DELAY |
| SAXISCCTDATA216 | input | CELL89.IMUX.IMUX11.DELAY |
| SAXISCCTDATA217 | input | CELL90.IMUX.IMUX8.DELAY |
| SAXISCCTDATA218 | input | CELL90.IMUX.IMUX9.DELAY |
| SAXISCCTDATA219 | input | CELL90.IMUX.IMUX10.DELAY |
| SAXISCCTDATA22 | input | CELL63.IMUX.IMUX5.DELAY |
| SAXISCCTDATA220 | input | CELL90.IMUX.IMUX11.DELAY |
| SAXISCCTDATA221 | input | CELL91.IMUX.IMUX8.DELAY |
| SAXISCCTDATA222 | input | CELL91.IMUX.IMUX9.DELAY |
| SAXISCCTDATA223 | input | CELL91.IMUX.IMUX10.DELAY |
| SAXISCCTDATA224 | input | CELL91.IMUX.IMUX11.DELAY |
| SAXISCCTDATA225 | input | CELL92.IMUX.IMUX8.DELAY |
| SAXISCCTDATA226 | input | CELL92.IMUX.IMUX9.DELAY |
| SAXISCCTDATA227 | input | CELL92.IMUX.IMUX10.DELAY |
| SAXISCCTDATA228 | input | CELL92.IMUX.IMUX11.DELAY |
| SAXISCCTDATA229 | input | CELL93.IMUX.IMUX8.DELAY |
| SAXISCCTDATA23 | input | CELL63.IMUX.IMUX6.DELAY |
| SAXISCCTDATA230 | input | CELL93.IMUX.IMUX9.DELAY |
| SAXISCCTDATA231 | input | CELL93.IMUX.IMUX10.DELAY |
| SAXISCCTDATA232 | input | CELL93.IMUX.IMUX11.DELAY |
| SAXISCCTDATA233 | input | CELL94.IMUX.IMUX8.DELAY |
| SAXISCCTDATA234 | input | CELL94.IMUX.IMUX9.DELAY |
| SAXISCCTDATA235 | input | CELL94.IMUX.IMUX10.DELAY |
| SAXISCCTDATA236 | input | CELL95.IMUX.IMUX8.DELAY |
| SAXISCCTDATA237 | input | CELL96.IMUX.IMUX8.DELAY |
| SAXISCCTDATA238 | input | CELL96.IMUX.IMUX9.DELAY |
| SAXISCCTDATA239 | input | CELL96.IMUX.IMUX10.DELAY |
| SAXISCCTDATA24 | input | CELL63.IMUX.IMUX7.DELAY |
| SAXISCCTDATA240 | input | CELL96.IMUX.IMUX11.DELAY |
| SAXISCCTDATA241 | input | CELL97.IMUX.IMUX8.DELAY |
| SAXISCCTDATA242 | input | CELL97.IMUX.IMUX9.DELAY |
| SAXISCCTDATA243 | input | CELL97.IMUX.IMUX10.DELAY |
| SAXISCCTDATA244 | input | CELL97.IMUX.IMUX11.DELAY |
| SAXISCCTDATA245 | input | CELL98.IMUX.IMUX8.DELAY |
| SAXISCCTDATA246 | input | CELL98.IMUX.IMUX9.DELAY |
| SAXISCCTDATA247 | input | CELL98.IMUX.IMUX10.DELAY |
| SAXISCCTDATA248 | input | CELL98.IMUX.IMUX11.DELAY |
| SAXISCCTDATA249 | input | CELL99.IMUX.IMUX8.DELAY |
| SAXISCCTDATA25 | input | CELL62.IMUX.IMUX4.DELAY |
| SAXISCCTDATA250 | input | CELL99.IMUX.IMUX9.DELAY |
| SAXISCCTDATA251 | input | CELL99.IMUX.IMUX10.DELAY |
| SAXISCCTDATA252 | input | CELL99.IMUX.IMUX11.DELAY |
| SAXISCCTDATA253 | input | CELL99.IMUX.IMUX12.DELAY |
| SAXISCCTDATA254 | input | CELL99.IMUX.IMUX13.DELAY |
| SAXISCCTDATA255 | input | CELL99.IMUX.IMUX14.DELAY |
| SAXISCCTDATA26 | input | CELL62.IMUX.IMUX5.DELAY |
| SAXISCCTDATA27 | input | CELL62.IMUX.IMUX6.DELAY |
| SAXISCCTDATA28 | input | CELL62.IMUX.IMUX7.DELAY |
| SAXISCCTDATA29 | input | CELL61.IMUX.IMUX4.DELAY |
| SAXISCCTDATA3 | input | CELL68.IMUX.IMUX6.DELAY |
| SAXISCCTDATA30 | input | CELL61.IMUX.IMUX5.DELAY |
| SAXISCCTDATA31 | input | CELL61.IMUX.IMUX6.DELAY |
| SAXISCCTDATA32 | input | CELL61.IMUX.IMUX7.DELAY |
| SAXISCCTDATA33 | input | CELL60.IMUX.IMUX4.DELAY |
| SAXISCCTDATA34 | input | CELL60.IMUX.IMUX5.DELAY |
| SAXISCCTDATA35 | input | CELL60.IMUX.IMUX6.DELAY |
| SAXISCCTDATA36 | input | CELL60.IMUX.IMUX7.DELAY |
| SAXISCCTDATA37 | input | CELL59.IMUX.IMUX4.DELAY |
| SAXISCCTDATA38 | input | CELL59.IMUX.IMUX5.DELAY |
| SAXISCCTDATA39 | input | CELL59.IMUX.IMUX6.DELAY |
| SAXISCCTDATA4 | input | CELL68.IMUX.IMUX7.DELAY |
| SAXISCCTDATA40 | input | CELL59.IMUX.IMUX7.DELAY |
| SAXISCCTDATA41 | input | CELL58.IMUX.IMUX4.DELAY |
| SAXISCCTDATA42 | input | CELL58.IMUX.IMUX5.DELAY |
| SAXISCCTDATA43 | input | CELL58.IMUX.IMUX6.DELAY |
| SAXISCCTDATA44 | input | CELL58.IMUX.IMUX7.DELAY |
| SAXISCCTDATA45 | input | CELL57.IMUX.IMUX4.DELAY |
| SAXISCCTDATA46 | input | CELL57.IMUX.IMUX5.DELAY |
| SAXISCCTDATA47 | input | CELL57.IMUX.IMUX6.DELAY |
| SAXISCCTDATA48 | input | CELL57.IMUX.IMUX7.DELAY |
| SAXISCCTDATA49 | input | CELL56.IMUX.IMUX4.DELAY |
| SAXISCCTDATA5 | input | CELL67.IMUX.IMUX4.DELAY |
| SAXISCCTDATA50 | input | CELL56.IMUX.IMUX5.DELAY |
| SAXISCCTDATA51 | input | CELL56.IMUX.IMUX6.DELAY |
| SAXISCCTDATA52 | input | CELL56.IMUX.IMUX7.DELAY |
| SAXISCCTDATA53 | input | CELL55.IMUX.IMUX4.DELAY |
| SAXISCCTDATA54 | input | CELL55.IMUX.IMUX5.DELAY |
| SAXISCCTDATA55 | input | CELL55.IMUX.IMUX6.DELAY |
| SAXISCCTDATA56 | input | CELL55.IMUX.IMUX7.DELAY |
| SAXISCCTDATA57 | input | CELL54.IMUX.IMUX4.DELAY |
| SAXISCCTDATA58 | input | CELL54.IMUX.IMUX5.DELAY |
| SAXISCCTDATA59 | input | CELL54.IMUX.IMUX6.DELAY |
| SAXISCCTDATA6 | input | CELL67.IMUX.IMUX5.DELAY |
| SAXISCCTDATA60 | input | CELL54.IMUX.IMUX7.DELAY |
| SAXISCCTDATA61 | input | CELL53.IMUX.IMUX4.DELAY |
| SAXISCCTDATA62 | input | CELL53.IMUX.IMUX5.DELAY |
| SAXISCCTDATA63 | input | CELL53.IMUX.IMUX6.DELAY |
| SAXISCCTDATA64 | input | CELL53.IMUX.IMUX7.DELAY |
| SAXISCCTDATA65 | input | CELL52.IMUX.IMUX4.DELAY |
| SAXISCCTDATA66 | input | CELL52.IMUX.IMUX5.DELAY |
| SAXISCCTDATA67 | input | CELL52.IMUX.IMUX6.DELAY |
| SAXISCCTDATA68 | input | CELL52.IMUX.IMUX7.DELAY |
| SAXISCCTDATA69 | input | CELL51.IMUX.IMUX4.DELAY |
| SAXISCCTDATA7 | input | CELL67.IMUX.IMUX6.DELAY |
| SAXISCCTDATA70 | input | CELL51.IMUX.IMUX5.DELAY |
| SAXISCCTDATA71 | input | CELL51.IMUX.IMUX6.DELAY |
| SAXISCCTDATA72 | input | CELL51.IMUX.IMUX7.DELAY |
| SAXISCCTDATA73 | input | CELL51.IMUX.IMUX8.DELAY |
| SAXISCCTDATA74 | input | CELL51.IMUX.IMUX9.DELAY |
| SAXISCCTDATA75 | input | CELL51.IMUX.IMUX10.DELAY |
| SAXISCCTDATA76 | input | CELL51.IMUX.IMUX11.DELAY |
| SAXISCCTDATA77 | input | CELL52.IMUX.IMUX8.DELAY |
| SAXISCCTDATA78 | input | CELL52.IMUX.IMUX9.DELAY |
| SAXISCCTDATA79 | input | CELL52.IMUX.IMUX10.DELAY |
| SAXISCCTDATA8 | input | CELL67.IMUX.IMUX7.DELAY |
| SAXISCCTDATA80 | input | CELL52.IMUX.IMUX11.DELAY |
| SAXISCCTDATA81 | input | CELL53.IMUX.IMUX8.DELAY |
| SAXISCCTDATA82 | input | CELL53.IMUX.IMUX9.DELAY |
| SAXISCCTDATA83 | input | CELL53.IMUX.IMUX10.DELAY |
| SAXISCCTDATA84 | input | CELL53.IMUX.IMUX11.DELAY |
| SAXISCCTDATA85 | input | CELL54.IMUX.IMUX8.DELAY |
| SAXISCCTDATA86 | input | CELL54.IMUX.IMUX9.DELAY |
| SAXISCCTDATA87 | input | CELL54.IMUX.IMUX10.DELAY |
| SAXISCCTDATA88 | input | CELL54.IMUX.IMUX11.DELAY |
| SAXISCCTDATA89 | input | CELL55.IMUX.IMUX8.DELAY |
| SAXISCCTDATA9 | input | CELL66.IMUX.IMUX4.DELAY |
| SAXISCCTDATA90 | input | CELL55.IMUX.IMUX9.DELAY |
| SAXISCCTDATA91 | input | CELL55.IMUX.IMUX10.DELAY |
| SAXISCCTDATA92 | input | CELL55.IMUX.IMUX11.DELAY |
| SAXISCCTDATA93 | input | CELL56.IMUX.IMUX8.DELAY |
| SAXISCCTDATA94 | input | CELL56.IMUX.IMUX9.DELAY |
| SAXISCCTDATA95 | input | CELL56.IMUX.IMUX10.DELAY |
| SAXISCCTDATA96 | input | CELL56.IMUX.IMUX11.DELAY |
| SAXISCCTDATA97 | input | CELL57.IMUX.IMUX8.DELAY |
| SAXISCCTDATA98 | input | CELL57.IMUX.IMUX9.DELAY |
| SAXISCCTDATA99 | input | CELL57.IMUX.IMUX10.DELAY |
| SAXISCCTKEEP0 | input | CELL51.IMUX.IMUX17.DELAY |
| SAXISCCTKEEP1 | input | CELL51.IMUX.IMUX18.DELAY |
| SAXISCCTKEEP2 | input | CELL51.IMUX.IMUX19.DELAY |
| SAXISCCTKEEP3 | input | CELL52.IMUX.IMUX16.DELAY |
| SAXISCCTKEEP4 | input | CELL52.IMUX.IMUX17.DELAY |
| SAXISCCTKEEP5 | input | CELL52.IMUX.IMUX18.DELAY |
| SAXISCCTKEEP6 | input | CELL52.IMUX.IMUX19.DELAY |
| SAXISCCTKEEP7 | input | CELL53.IMUX.IMUX16.DELAY |
| SAXISCCTLAST | input | CELL51.IMUX.IMUX16.DELAY |
| SAXISCCTREADY0 | output | CELL59.OUT21.TMIN |
| SAXISCCTREADY1 | output | CELL61.OUT20.TMIN |
| SAXISCCTREADY2 | output | CELL61.OUT21.TMIN |
| SAXISCCTREADY3 | output | CELL70.OUT19.TMIN |
| SAXISCCTUSER0 | input | CELL51.IMUX.IMUX12.DELAY |
| SAXISCCTUSER1 | input | CELL51.IMUX.IMUX13.DELAY |
| SAXISCCTUSER10 | input | CELL53.IMUX.IMUX14.DELAY |
| SAXISCCTUSER11 | input | CELL53.IMUX.IMUX15.DELAY |
| SAXISCCTUSER12 | input | CELL56.IMUX.IMUX12.DELAY |
| SAXISCCTUSER13 | input | CELL56.IMUX.IMUX13.DELAY |
| SAXISCCTUSER14 | input | CELL56.IMUX.IMUX14.DELAY |
| SAXISCCTUSER15 | input | CELL56.IMUX.IMUX15.DELAY |
| SAXISCCTUSER16 | input | CELL57.IMUX.IMUX12.DELAY |
| SAXISCCTUSER17 | input | CELL57.IMUX.IMUX13.DELAY |
| SAXISCCTUSER18 | input | CELL57.IMUX.IMUX14.DELAY |
| SAXISCCTUSER19 | input | CELL57.IMUX.IMUX15.DELAY |
| SAXISCCTUSER2 | input | CELL51.IMUX.IMUX14.DELAY |
| SAXISCCTUSER20 | input | CELL60.IMUX.IMUX12.DELAY |
| SAXISCCTUSER21 | input | CELL61.IMUX.IMUX12.DELAY |
| SAXISCCTUSER22 | input | CELL61.IMUX.IMUX13.DELAY |
| SAXISCCTUSER23 | input | CELL61.IMUX.IMUX14.DELAY |
| SAXISCCTUSER24 | input | CELL61.IMUX.IMUX15.DELAY |
| SAXISCCTUSER25 | input | CELL62.IMUX.IMUX12.DELAY |
| SAXISCCTUSER26 | input | CELL62.IMUX.IMUX13.DELAY |
| SAXISCCTUSER27 | input | CELL62.IMUX.IMUX14.DELAY |
| SAXISCCTUSER28 | input | CELL62.IMUX.IMUX15.DELAY |
| SAXISCCTUSER29 | input | CELL63.IMUX.IMUX12.DELAY |
| SAXISCCTUSER3 | input | CELL51.IMUX.IMUX15.DELAY |
| SAXISCCTUSER30 | input | CELL63.IMUX.IMUX13.DELAY |
| SAXISCCTUSER31 | input | CELL63.IMUX.IMUX14.DELAY |
| SAXISCCTUSER32 | input | CELL63.IMUX.IMUX15.DELAY |
| SAXISCCTUSER4 | input | CELL52.IMUX.IMUX12.DELAY |
| SAXISCCTUSER5 | input | CELL52.IMUX.IMUX13.DELAY |
| SAXISCCTUSER6 | input | CELL52.IMUX.IMUX14.DELAY |
| SAXISCCTUSER7 | input | CELL52.IMUX.IMUX15.DELAY |
| SAXISCCTUSER8 | input | CELL53.IMUX.IMUX12.DELAY |
| SAXISCCTUSER9 | input | CELL53.IMUX.IMUX13.DELAY |
| SAXISCCTVALID | input | CELL51.IMUX.IMUX20.DELAY |
| SAXISRQTDATA0 | input | CELL0.IMUX.IMUX11.DELAY |
| SAXISRQTDATA1 | input | CELL0.IMUX.IMUX12.DELAY |
| SAXISRQTDATA10 | input | CELL2.IMUX.IMUX10.DELAY |
| SAXISRQTDATA100 | input | CELL25.IMUX.IMUX8.DELAY |
| SAXISRQTDATA101 | input | CELL25.IMUX.IMUX9.DELAY |
| SAXISRQTDATA102 | input | CELL25.IMUX.IMUX10.DELAY |
| SAXISRQTDATA103 | input | CELL25.IMUX.IMUX11.DELAY |
| SAXISRQTDATA104 | input | CELL26.IMUX.IMUX8.DELAY |
| SAXISRQTDATA105 | input | CELL26.IMUX.IMUX9.DELAY |
| SAXISRQTDATA106 | input | CELL26.IMUX.IMUX10.DELAY |
| SAXISRQTDATA107 | input | CELL26.IMUX.IMUX11.DELAY |
| SAXISRQTDATA108 | input | CELL27.IMUX.IMUX8.DELAY |
| SAXISRQTDATA109 | input | CELL27.IMUX.IMUX9.DELAY |
| SAXISRQTDATA11 | input | CELL2.IMUX.IMUX11.DELAY |
| SAXISRQTDATA110 | input | CELL27.IMUX.IMUX10.DELAY |
| SAXISRQTDATA111 | input | CELL27.IMUX.IMUX11.DELAY |
| SAXISRQTDATA112 | input | CELL28.IMUX.IMUX8.DELAY |
| SAXISRQTDATA113 | input | CELL28.IMUX.IMUX9.DELAY |
| SAXISRQTDATA114 | input | CELL28.IMUX.IMUX10.DELAY |
| SAXISRQTDATA115 | input | CELL28.IMUX.IMUX11.DELAY |
| SAXISRQTDATA116 | input | CELL29.IMUX.IMUX8.DELAY |
| SAXISRQTDATA117 | input | CELL29.IMUX.IMUX9.DELAY |
| SAXISRQTDATA118 | input | CELL29.IMUX.IMUX10.DELAY |
| SAXISRQTDATA119 | input | CELL29.IMUX.IMUX11.DELAY |
| SAXISRQTDATA12 | input | CELL3.IMUX.IMUX8.DELAY |
| SAXISRQTDATA120 | input | CELL30.IMUX.IMUX8.DELAY |
| SAXISRQTDATA121 | input | CELL30.IMUX.IMUX9.DELAY |
| SAXISRQTDATA122 | input | CELL30.IMUX.IMUX10.DELAY |
| SAXISRQTDATA123 | input | CELL30.IMUX.IMUX11.DELAY |
| SAXISRQTDATA124 | input | CELL31.IMUX.IMUX8.DELAY |
| SAXISRQTDATA125 | input | CELL31.IMUX.IMUX9.DELAY |
| SAXISRQTDATA126 | input | CELL31.IMUX.IMUX10.DELAY |
| SAXISRQTDATA127 | input | CELL31.IMUX.IMUX11.DELAY |
| SAXISRQTDATA128 | input | CELL32.IMUX.IMUX8.DELAY |
| SAXISRQTDATA129 | input | CELL32.IMUX.IMUX9.DELAY |
| SAXISRQTDATA13 | input | CELL3.IMUX.IMUX9.DELAY |
| SAXISRQTDATA130 | input | CELL32.IMUX.IMUX10.DELAY |
| SAXISRQTDATA131 | input | CELL32.IMUX.IMUX11.DELAY |
| SAXISRQTDATA132 | input | CELL33.IMUX.IMUX8.DELAY |
| SAXISRQTDATA133 | input | CELL33.IMUX.IMUX9.DELAY |
| SAXISRQTDATA134 | input | CELL33.IMUX.IMUX10.DELAY |
| SAXISRQTDATA135 | input | CELL33.IMUX.IMUX11.DELAY |
| SAXISRQTDATA136 | input | CELL34.IMUX.IMUX8.DELAY |
| SAXISRQTDATA137 | input | CELL34.IMUX.IMUX9.DELAY |
| SAXISRQTDATA138 | input | CELL34.IMUX.IMUX10.DELAY |
| SAXISRQTDATA139 | input | CELL34.IMUX.IMUX11.DELAY |
| SAXISRQTDATA14 | input | CELL3.IMUX.IMUX10.DELAY |
| SAXISRQTDATA140 | input | CELL35.IMUX.IMUX8.DELAY |
| SAXISRQTDATA141 | input | CELL35.IMUX.IMUX9.DELAY |
| SAXISRQTDATA142 | input | CELL35.IMUX.IMUX10.DELAY |
| SAXISRQTDATA143 | input | CELL35.IMUX.IMUX11.DELAY |
| SAXISRQTDATA144 | input | CELL36.IMUX.IMUX8.DELAY |
| SAXISRQTDATA145 | input | CELL36.IMUX.IMUX9.DELAY |
| SAXISRQTDATA146 | input | CELL36.IMUX.IMUX10.DELAY |
| SAXISRQTDATA147 | input | CELL36.IMUX.IMUX11.DELAY |
| SAXISRQTDATA148 | input | CELL37.IMUX.IMUX4.DELAY |
| SAXISRQTDATA149 | input | CELL37.IMUX.IMUX5.DELAY |
| SAXISRQTDATA15 | input | CELL3.IMUX.IMUX11.DELAY |
| SAXISRQTDATA150 | input | CELL37.IMUX.IMUX6.DELAY |
| SAXISRQTDATA151 | input | CELL37.IMUX.IMUX7.DELAY |
| SAXISRQTDATA152 | input | CELL38.IMUX.IMUX8.DELAY |
| SAXISRQTDATA153 | input | CELL38.IMUX.IMUX9.DELAY |
| SAXISRQTDATA154 | input | CELL38.IMUX.IMUX10.DELAY |
| SAXISRQTDATA155 | input | CELL38.IMUX.IMUX11.DELAY |
| SAXISRQTDATA156 | input | CELL39.IMUX.IMUX12.DELAY |
| SAXISRQTDATA157 | input | CELL39.IMUX.IMUX13.DELAY |
| SAXISRQTDATA158 | input | CELL39.IMUX.IMUX14.DELAY |
| SAXISRQTDATA159 | input | CELL39.IMUX.IMUX15.DELAY |
| SAXISRQTDATA16 | input | CELL4.IMUX.IMUX8.DELAY |
| SAXISRQTDATA160 | input | CELL40.IMUX.IMUX12.DELAY |
| SAXISRQTDATA161 | input | CELL40.IMUX.IMUX13.DELAY |
| SAXISRQTDATA162 | input | CELL40.IMUX.IMUX14.DELAY |
| SAXISRQTDATA163 | input | CELL40.IMUX.IMUX15.DELAY |
| SAXISRQTDATA164 | input | CELL41.IMUX.IMUX12.DELAY |
| SAXISRQTDATA165 | input | CELL41.IMUX.IMUX13.DELAY |
| SAXISRQTDATA166 | input | CELL41.IMUX.IMUX14.DELAY |
| SAXISRQTDATA167 | input | CELL41.IMUX.IMUX15.DELAY |
| SAXISRQTDATA168 | input | CELL42.IMUX.IMUX12.DELAY |
| SAXISRQTDATA169 | input | CELL42.IMUX.IMUX13.DELAY |
| SAXISRQTDATA17 | input | CELL4.IMUX.IMUX9.DELAY |
| SAXISRQTDATA170 | input | CELL42.IMUX.IMUX14.DELAY |
| SAXISRQTDATA171 | input | CELL42.IMUX.IMUX15.DELAY |
| SAXISRQTDATA172 | input | CELL43.IMUX.IMUX12.DELAY |
| SAXISRQTDATA173 | input | CELL43.IMUX.IMUX13.DELAY |
| SAXISRQTDATA174 | input | CELL43.IMUX.IMUX14.DELAY |
| SAXISRQTDATA175 | input | CELL43.IMUX.IMUX15.DELAY |
| SAXISRQTDATA176 | input | CELL44.IMUX.IMUX12.DELAY |
| SAXISRQTDATA177 | input | CELL44.IMUX.IMUX13.DELAY |
| SAXISRQTDATA178 | input | CELL44.IMUX.IMUX14.DELAY |
| SAXISRQTDATA179 | input | CELL44.IMUX.IMUX15.DELAY |
| SAXISRQTDATA18 | input | CELL4.IMUX.IMUX10.DELAY |
| SAXISRQTDATA180 | input | CELL45.IMUX.IMUX12.DELAY |
| SAXISRQTDATA181 | input | CELL45.IMUX.IMUX13.DELAY |
| SAXISRQTDATA182 | input | CELL45.IMUX.IMUX14.DELAY |
| SAXISRQTDATA183 | input | CELL45.IMUX.IMUX15.DELAY |
| SAXISRQTDATA184 | input | CELL46.IMUX.IMUX12.DELAY |
| SAXISRQTDATA185 | input | CELL46.IMUX.IMUX13.DELAY |
| SAXISRQTDATA186 | input | CELL46.IMUX.IMUX14.DELAY |
| SAXISRQTDATA187 | input | CELL46.IMUX.IMUX15.DELAY |
| SAXISRQTDATA188 | input | CELL47.IMUX.IMUX16.DELAY |
| SAXISRQTDATA189 | input | CELL47.IMUX.IMUX17.DELAY |
| SAXISRQTDATA19 | input | CELL4.IMUX.IMUX11.DELAY |
| SAXISRQTDATA190 | input | CELL47.IMUX.IMUX18.DELAY |
| SAXISRQTDATA191 | input | CELL47.IMUX.IMUX19.DELAY |
| SAXISRQTDATA192 | input | CELL48.IMUX.IMUX16.DELAY |
| SAXISRQTDATA193 | input | CELL48.IMUX.IMUX17.DELAY |
| SAXISRQTDATA194 | input | CELL48.IMUX.IMUX18.DELAY |
| SAXISRQTDATA195 | input | CELL48.IMUX.IMUX19.DELAY |
| SAXISRQTDATA196 | input | CELL49.IMUX.IMUX8.DELAY |
| SAXISRQTDATA197 | input | CELL49.IMUX.IMUX9.DELAY |
| SAXISRQTDATA198 | input | CELL49.IMUX.IMUX10.DELAY |
| SAXISRQTDATA199 | input | CELL49.IMUX.IMUX11.DELAY |
| SAXISRQTDATA2 | input | CELL0.IMUX.IMUX13.DELAY |
| SAXISRQTDATA20 | input | CELL5.IMUX.IMUX8.DELAY |
| SAXISRQTDATA200 | input | CELL48.IMUX.IMUX20.DELAY |
| SAXISRQTDATA201 | input | CELL48.IMUX.IMUX21.DELAY |
| SAXISRQTDATA202 | input | CELL48.IMUX.IMUX22.DELAY |
| SAXISRQTDATA203 | input | CELL48.IMUX.IMUX23.DELAY |
| SAXISRQTDATA204 | input | CELL47.IMUX.IMUX20.DELAY |
| SAXISRQTDATA205 | input | CELL47.IMUX.IMUX21.DELAY |
| SAXISRQTDATA206 | input | CELL47.IMUX.IMUX22.DELAY |
| SAXISRQTDATA207 | input | CELL47.IMUX.IMUX23.DELAY |
| SAXISRQTDATA208 | input | CELL46.IMUX.IMUX16.DELAY |
| SAXISRQTDATA209 | input | CELL46.IMUX.IMUX17.DELAY |
| SAXISRQTDATA21 | input | CELL5.IMUX.IMUX9.DELAY |
| SAXISRQTDATA210 | input | CELL46.IMUX.IMUX18.DELAY |
| SAXISRQTDATA211 | input | CELL46.IMUX.IMUX19.DELAY |
| SAXISRQTDATA212 | input | CELL45.IMUX.IMUX16.DELAY |
| SAXISRQTDATA213 | input | CELL45.IMUX.IMUX17.DELAY |
| SAXISRQTDATA214 | input | CELL45.IMUX.IMUX18.DELAY |
| SAXISRQTDATA215 | input | CELL45.IMUX.IMUX19.DELAY |
| SAXISRQTDATA216 | input | CELL44.IMUX.IMUX16.DELAY |
| SAXISRQTDATA217 | input | CELL44.IMUX.IMUX17.DELAY |
| SAXISRQTDATA218 | input | CELL44.IMUX.IMUX18.DELAY |
| SAXISRQTDATA219 | input | CELL44.IMUX.IMUX19.DELAY |
| SAXISRQTDATA22 | input | CELL5.IMUX.IMUX10.DELAY |
| SAXISRQTDATA220 | input | CELL43.IMUX.IMUX16.DELAY |
| SAXISRQTDATA221 | input | CELL43.IMUX.IMUX17.DELAY |
| SAXISRQTDATA222 | input | CELL43.IMUX.IMUX18.DELAY |
| SAXISRQTDATA223 | input | CELL43.IMUX.IMUX19.DELAY |
| SAXISRQTDATA224 | input | CELL42.IMUX.IMUX16.DELAY |
| SAXISRQTDATA225 | input | CELL42.IMUX.IMUX17.DELAY |
| SAXISRQTDATA226 | input | CELL42.IMUX.IMUX18.DELAY |
| SAXISRQTDATA227 | input | CELL42.IMUX.IMUX19.DELAY |
| SAXISRQTDATA228 | input | CELL41.IMUX.IMUX16.DELAY |
| SAXISRQTDATA229 | input | CELL41.IMUX.IMUX17.DELAY |
| SAXISRQTDATA23 | input | CELL5.IMUX.IMUX11.DELAY |
| SAXISRQTDATA230 | input | CELL41.IMUX.IMUX18.DELAY |
| SAXISRQTDATA231 | input | CELL41.IMUX.IMUX19.DELAY |
| SAXISRQTDATA232 | input | CELL40.IMUX.IMUX16.DELAY |
| SAXISRQTDATA233 | input | CELL40.IMUX.IMUX17.DELAY |
| SAXISRQTDATA234 | input | CELL40.IMUX.IMUX18.DELAY |
| SAXISRQTDATA235 | input | CELL40.IMUX.IMUX19.DELAY |
| SAXISRQTDATA236 | input | CELL39.IMUX.IMUX16.DELAY |
| SAXISRQTDATA237 | input | CELL39.IMUX.IMUX17.DELAY |
| SAXISRQTDATA238 | input | CELL39.IMUX.IMUX18.DELAY |
| SAXISRQTDATA239 | input | CELL39.IMUX.IMUX19.DELAY |
| SAXISRQTDATA24 | input | CELL6.IMUX.IMUX8.DELAY |
| SAXISRQTDATA240 | input | CELL38.IMUX.IMUX12.DELAY |
| SAXISRQTDATA241 | input | CELL38.IMUX.IMUX13.DELAY |
| SAXISRQTDATA242 | input | CELL38.IMUX.IMUX14.DELAY |
| SAXISRQTDATA243 | input | CELL38.IMUX.IMUX15.DELAY |
| SAXISRQTDATA244 | input | CELL37.IMUX.IMUX8.DELAY |
| SAXISRQTDATA245 | input | CELL37.IMUX.IMUX9.DELAY |
| SAXISRQTDATA246 | input | CELL37.IMUX.IMUX10.DELAY |
| SAXISRQTDATA247 | input | CELL37.IMUX.IMUX11.DELAY |
| SAXISRQTDATA248 | input | CELL36.IMUX.IMUX12.DELAY |
| SAXISRQTDATA249 | input | CELL36.IMUX.IMUX13.DELAY |
| SAXISRQTDATA25 | input | CELL6.IMUX.IMUX9.DELAY |
| SAXISRQTDATA250 | input | CELL36.IMUX.IMUX14.DELAY |
| SAXISRQTDATA251 | input | CELL36.IMUX.IMUX15.DELAY |
| SAXISRQTDATA252 | input | CELL35.IMUX.IMUX12.DELAY |
| SAXISRQTDATA253 | input | CELL35.IMUX.IMUX13.DELAY |
| SAXISRQTDATA254 | input | CELL35.IMUX.IMUX14.DELAY |
| SAXISRQTDATA255 | input | CELL35.IMUX.IMUX15.DELAY |
| SAXISRQTDATA26 | input | CELL6.IMUX.IMUX10.DELAY |
| SAXISRQTDATA27 | input | CELL6.IMUX.IMUX11.DELAY |
| SAXISRQTDATA28 | input | CELL7.IMUX.IMUX8.DELAY |
| SAXISRQTDATA29 | input | CELL7.IMUX.IMUX9.DELAY |
| SAXISRQTDATA3 | input | CELL0.IMUX.IMUX14.DELAY |
| SAXISRQTDATA30 | input | CELL7.IMUX.IMUX10.DELAY |
| SAXISRQTDATA31 | input | CELL7.IMUX.IMUX11.DELAY |
| SAXISRQTDATA32 | input | CELL8.IMUX.IMUX8.DELAY |
| SAXISRQTDATA33 | input | CELL8.IMUX.IMUX9.DELAY |
| SAXISRQTDATA34 | input | CELL8.IMUX.IMUX10.DELAY |
| SAXISRQTDATA35 | input | CELL8.IMUX.IMUX11.DELAY |
| SAXISRQTDATA36 | input | CELL9.IMUX.IMUX8.DELAY |
| SAXISRQTDATA37 | input | CELL9.IMUX.IMUX9.DELAY |
| SAXISRQTDATA38 | input | CELL9.IMUX.IMUX10.DELAY |
| SAXISRQTDATA39 | input | CELL9.IMUX.IMUX11.DELAY |
| SAXISRQTDATA4 | input | CELL1.IMUX.IMUX8.DELAY |
| SAXISRQTDATA40 | input | CELL10.IMUX.IMUX8.DELAY |
| SAXISRQTDATA41 | input | CELL10.IMUX.IMUX9.DELAY |
| SAXISRQTDATA42 | input | CELL10.IMUX.IMUX10.DELAY |
| SAXISRQTDATA43 | input | CELL10.IMUX.IMUX11.DELAY |
| SAXISRQTDATA44 | input | CELL11.IMUX.IMUX8.DELAY |
| SAXISRQTDATA45 | input | CELL11.IMUX.IMUX9.DELAY |
| SAXISRQTDATA46 | input | CELL11.IMUX.IMUX10.DELAY |
| SAXISRQTDATA47 | input | CELL11.IMUX.IMUX11.DELAY |
| SAXISRQTDATA48 | input | CELL12.IMUX.IMUX8.DELAY |
| SAXISRQTDATA49 | input | CELL12.IMUX.IMUX9.DELAY |
| SAXISRQTDATA5 | input | CELL1.IMUX.IMUX9.DELAY |
| SAXISRQTDATA50 | input | CELL12.IMUX.IMUX10.DELAY |
| SAXISRQTDATA51 | input | CELL12.IMUX.IMUX11.DELAY |
| SAXISRQTDATA52 | input | CELL13.IMUX.IMUX8.DELAY |
| SAXISRQTDATA53 | input | CELL13.IMUX.IMUX9.DELAY |
| SAXISRQTDATA54 | input | CELL13.IMUX.IMUX10.DELAY |
| SAXISRQTDATA55 | input | CELL13.IMUX.IMUX11.DELAY |
| SAXISRQTDATA56 | input | CELL14.IMUX.IMUX8.DELAY |
| SAXISRQTDATA57 | input | CELL14.IMUX.IMUX9.DELAY |
| SAXISRQTDATA58 | input | CELL14.IMUX.IMUX10.DELAY |
| SAXISRQTDATA59 | input | CELL14.IMUX.IMUX11.DELAY |
| SAXISRQTDATA6 | input | CELL1.IMUX.IMUX10.DELAY |
| SAXISRQTDATA60 | input | CELL15.IMUX.IMUX8.DELAY |
| SAXISRQTDATA61 | input | CELL15.IMUX.IMUX9.DELAY |
| SAXISRQTDATA62 | input | CELL15.IMUX.IMUX10.DELAY |
| SAXISRQTDATA63 | input | CELL15.IMUX.IMUX11.DELAY |
| SAXISRQTDATA64 | input | CELL16.IMUX.IMUX8.DELAY |
| SAXISRQTDATA65 | input | CELL16.IMUX.IMUX9.DELAY |
| SAXISRQTDATA66 | input | CELL16.IMUX.IMUX10.DELAY |
| SAXISRQTDATA67 | input | CELL16.IMUX.IMUX11.DELAY |
| SAXISRQTDATA68 | input | CELL17.IMUX.IMUX4.DELAY |
| SAXISRQTDATA69 | input | CELL17.IMUX.IMUX5.DELAY |
| SAXISRQTDATA7 | input | CELL1.IMUX.IMUX11.DELAY |
| SAXISRQTDATA70 | input | CELL17.IMUX.IMUX6.DELAY |
| SAXISRQTDATA71 | input | CELL17.IMUX.IMUX7.DELAY |
| SAXISRQTDATA72 | input | CELL18.IMUX.IMUX4.DELAY |
| SAXISRQTDATA73 | input | CELL18.IMUX.IMUX5.DELAY |
| SAXISRQTDATA74 | input | CELL18.IMUX.IMUX6.DELAY |
| SAXISRQTDATA75 | input | CELL18.IMUX.IMUX7.DELAY |
| SAXISRQTDATA76 | input | CELL19.IMUX.IMUX4.DELAY |
| SAXISRQTDATA77 | input | CELL19.IMUX.IMUX5.DELAY |
| SAXISRQTDATA78 | input | CELL19.IMUX.IMUX6.DELAY |
| SAXISRQTDATA79 | input | CELL19.IMUX.IMUX7.DELAY |
| SAXISRQTDATA8 | input | CELL2.IMUX.IMUX8.DELAY |
| SAXISRQTDATA80 | input | CELL20.IMUX.IMUX4.DELAY |
| SAXISRQTDATA81 | input | CELL20.IMUX.IMUX5.DELAY |
| SAXISRQTDATA82 | input | CELL20.IMUX.IMUX6.DELAY |
| SAXISRQTDATA83 | input | CELL20.IMUX.IMUX7.DELAY |
| SAXISRQTDATA84 | input | CELL21.IMUX.IMUX8.DELAY |
| SAXISRQTDATA85 | input | CELL21.IMUX.IMUX9.DELAY |
| SAXISRQTDATA86 | input | CELL21.IMUX.IMUX10.DELAY |
| SAXISRQTDATA87 | input | CELL21.IMUX.IMUX11.DELAY |
| SAXISRQTDATA88 | input | CELL22.IMUX.IMUX8.DELAY |
| SAXISRQTDATA89 | input | CELL22.IMUX.IMUX9.DELAY |
| SAXISRQTDATA9 | input | CELL2.IMUX.IMUX9.DELAY |
| SAXISRQTDATA90 | input | CELL22.IMUX.IMUX10.DELAY |
| SAXISRQTDATA91 | input | CELL22.IMUX.IMUX11.DELAY |
| SAXISRQTDATA92 | input | CELL23.IMUX.IMUX8.DELAY |
| SAXISRQTDATA93 | input | CELL23.IMUX.IMUX9.DELAY |
| SAXISRQTDATA94 | input | CELL23.IMUX.IMUX10.DELAY |
| SAXISRQTDATA95 | input | CELL23.IMUX.IMUX11.DELAY |
| SAXISRQTDATA96 | input | CELL24.IMUX.IMUX8.DELAY |
| SAXISRQTDATA97 | input | CELL24.IMUX.IMUX9.DELAY |
| SAXISRQTDATA98 | input | CELL24.IMUX.IMUX10.DELAY |
| SAXISRQTDATA99 | input | CELL24.IMUX.IMUX11.DELAY |
| SAXISRQTKEEP0 | input | CELL0.IMUX.IMUX19.DELAY |
| SAXISRQTKEEP1 | input | CELL0.IMUX.IMUX20.DELAY |
| SAXISRQTKEEP2 | input | CELL0.IMUX.IMUX21.DELAY |
| SAXISRQTKEEP3 | input | CELL0.IMUX.IMUX22.DELAY |
| SAXISRQTKEEP4 | input | CELL1.IMUX.IMUX16.DELAY |
| SAXISRQTKEEP5 | input | CELL1.IMUX.IMUX17.DELAY |
| SAXISRQTKEEP6 | input | CELL1.IMUX.IMUX18.DELAY |
| SAXISRQTKEEP7 | input | CELL1.IMUX.IMUX19.DELAY |
| SAXISRQTLAST | input | CELL0.IMUX.IMUX15.DELAY |
| SAXISRQTREADY0 | output | CELL10.OUT13.TMIN |
| SAXISRQTREADY1 | output | CELL10.OUT14.TMIN |
| SAXISRQTREADY2 | output | CELL10.OUT15.TMIN |
| SAXISRQTREADY3 | output | CELL12.OUT8.TMIN |
| SAXISRQTUSER0 | input | CELL0.IMUX.IMUX17.DELAY |
| SAXISRQTUSER1 | input | CELL0.IMUX.IMUX18.DELAY |
| SAXISRQTUSER10 | input | CELL3.IMUX.IMUX12.DELAY |
| SAXISRQTUSER11 | input | CELL3.IMUX.IMUX13.DELAY |
| SAXISRQTUSER12 | input | CELL3.IMUX.IMUX14.DELAY |
| SAXISRQTUSER13 | input | CELL3.IMUX.IMUX15.DELAY |
| SAXISRQTUSER14 | input | CELL4.IMUX.IMUX12.DELAY |
| SAXISRQTUSER15 | input | CELL4.IMUX.IMUX13.DELAY |
| SAXISRQTUSER16 | input | CELL4.IMUX.IMUX14.DELAY |
| SAXISRQTUSER17 | input | CELL4.IMUX.IMUX15.DELAY |
| SAXISRQTUSER18 | input | CELL5.IMUX.IMUX12.DELAY |
| SAXISRQTUSER19 | input | CELL5.IMUX.IMUX13.DELAY |
| SAXISRQTUSER2 | input | CELL1.IMUX.IMUX12.DELAY |
| SAXISRQTUSER20 | input | CELL5.IMUX.IMUX14.DELAY |
| SAXISRQTUSER21 | input | CELL5.IMUX.IMUX15.DELAY |
| SAXISRQTUSER22 | input | CELL6.IMUX.IMUX12.DELAY |
| SAXISRQTUSER23 | input | CELL6.IMUX.IMUX13.DELAY |
| SAXISRQTUSER24 | input | CELL6.IMUX.IMUX14.DELAY |
| SAXISRQTUSER25 | input | CELL6.IMUX.IMUX15.DELAY |
| SAXISRQTUSER26 | input | CELL7.IMUX.IMUX12.DELAY |
| SAXISRQTUSER27 | input | CELL7.IMUX.IMUX13.DELAY |
| SAXISRQTUSER28 | input | CELL7.IMUX.IMUX14.DELAY |
| SAXISRQTUSER29 | input | CELL7.IMUX.IMUX15.DELAY |
| SAXISRQTUSER3 | input | CELL1.IMUX.IMUX13.DELAY |
| SAXISRQTUSER30 | input | CELL8.IMUX.IMUX12.DELAY |
| SAXISRQTUSER31 | input | CELL8.IMUX.IMUX13.DELAY |
| SAXISRQTUSER32 | input | CELL8.IMUX.IMUX14.DELAY |
| SAXISRQTUSER33 | input | CELL8.IMUX.IMUX15.DELAY |
| SAXISRQTUSER34 | input | CELL9.IMUX.IMUX12.DELAY |
| SAXISRQTUSER35 | input | CELL9.IMUX.IMUX13.DELAY |
| SAXISRQTUSER36 | input | CELL9.IMUX.IMUX14.DELAY |
| SAXISRQTUSER37 | input | CELL9.IMUX.IMUX15.DELAY |
| SAXISRQTUSER38 | input | CELL10.IMUX.IMUX12.DELAY |
| SAXISRQTUSER39 | input | CELL10.IMUX.IMUX13.DELAY |
| SAXISRQTUSER4 | input | CELL1.IMUX.IMUX14.DELAY |
| SAXISRQTUSER40 | input | CELL10.IMUX.IMUX14.DELAY |
| SAXISRQTUSER41 | input | CELL10.IMUX.IMUX15.DELAY |
| SAXISRQTUSER42 | input | CELL11.IMUX.IMUX12.DELAY |
| SAXISRQTUSER43 | input | CELL11.IMUX.IMUX13.DELAY |
| SAXISRQTUSER44 | input | CELL11.IMUX.IMUX14.DELAY |
| SAXISRQTUSER45 | input | CELL11.IMUX.IMUX15.DELAY |
| SAXISRQTUSER46 | input | CELL12.IMUX.IMUX12.DELAY |
| SAXISRQTUSER47 | input | CELL12.IMUX.IMUX13.DELAY |
| SAXISRQTUSER48 | input | CELL12.IMUX.IMUX14.DELAY |
| SAXISRQTUSER49 | input | CELL12.IMUX.IMUX15.DELAY |
| SAXISRQTUSER5 | input | CELL1.IMUX.IMUX15.DELAY |
| SAXISRQTUSER50 | input | CELL13.IMUX.IMUX12.DELAY |
| SAXISRQTUSER51 | input | CELL13.IMUX.IMUX13.DELAY |
| SAXISRQTUSER52 | input | CELL13.IMUX.IMUX14.DELAY |
| SAXISRQTUSER53 | input | CELL13.IMUX.IMUX15.DELAY |
| SAXISRQTUSER54 | input | CELL14.IMUX.IMUX12.DELAY |
| SAXISRQTUSER55 | input | CELL14.IMUX.IMUX13.DELAY |
| SAXISRQTUSER56 | input | CELL14.IMUX.IMUX14.DELAY |
| SAXISRQTUSER57 | input | CELL14.IMUX.IMUX15.DELAY |
| SAXISRQTUSER58 | input | CELL15.IMUX.IMUX12.DELAY |
| SAXISRQTUSER59 | input | CELL15.IMUX.IMUX13.DELAY |
| SAXISRQTUSER6 | input | CELL2.IMUX.IMUX12.DELAY |
| SAXISRQTUSER7 | input | CELL2.IMUX.IMUX13.DELAY |
| SAXISRQTUSER8 | input | CELL2.IMUX.IMUX14.DELAY |
| SAXISRQTUSER9 | input | CELL2.IMUX.IMUX15.DELAY |
| SAXISRQTVALID | input | CELL0.IMUX.IMUX23.DELAY |
| SCANENABLEN | input | CELL74.IMUX.IMUX26.DELAY |
| SCANIN0 | input | CELL74.IMUX.IMUX27.DELAY |
| SCANIN1 | input | CELL75.IMUX.IMUX24.DELAY |
| SCANIN10 | input | CELL77.IMUX.IMUX25.DELAY |
| SCANIN11 | input | CELL77.IMUX.IMUX26.DELAY |
| SCANIN12 | input | CELL77.IMUX.IMUX27.DELAY |
| SCANIN13 | input | CELL78.IMUX.IMUX20.DELAY |
| SCANIN14 | input | CELL78.IMUX.IMUX21.DELAY |
| SCANIN15 | input | CELL78.IMUX.IMUX22.DELAY |
| SCANIN16 | input | CELL78.IMUX.IMUX23.DELAY |
| SCANIN17 | input | CELL79.IMUX.IMUX12.DELAY |
| SCANIN18 | input | CELL79.IMUX.IMUX13.DELAY |
| SCANIN19 | input | CELL79.IMUX.IMUX14.DELAY |
| SCANIN2 | input | CELL75.IMUX.IMUX25.DELAY |
| SCANIN20 | input | CELL79.IMUX.IMUX15.DELAY |
| SCANIN21 | input | CELL80.IMUX.IMUX12.DELAY |
| SCANIN22 | input | CELL80.IMUX.IMUX13.DELAY |
| SCANIN23 | input | CELL80.IMUX.IMUX14.DELAY |
| SCANIN24 | input | CELL80.IMUX.IMUX15.DELAY |
| SCANIN3 | input | CELL75.IMUX.IMUX26.DELAY |
| SCANIN4 | input | CELL75.IMUX.IMUX27.DELAY |
| SCANIN5 | input | CELL76.IMUX.IMUX24.DELAY |
| SCANIN6 | input | CELL76.IMUX.IMUX25.DELAY |
| SCANIN7 | input | CELL76.IMUX.IMUX26.DELAY |
| SCANIN8 | input | CELL76.IMUX.IMUX27.DELAY |
| SCANIN9 | input | CELL77.IMUX.IMUX24.DELAY |
| SCANMODEN | input | CELL74.IMUX.IMUX25.DELAY |
| SCANOUT0 | output | CELL94.OUT23.TMIN |
| SCANOUT1 | output | CELL95.OUT16.TMIN |
| SCANOUT10 | output | CELL97.OUT17.TMIN |
| SCANOUT11 | output | CELL97.OUT18.TMIN |
| SCANOUT12 | output | CELL97.OUT19.TMIN |
| SCANOUT13 | output | CELL98.OUT16.TMIN |
| SCANOUT14 | output | CELL98.OUT17.TMIN |
| SCANOUT15 | output | CELL98.OUT18.TMIN |
| SCANOUT16 | output | CELL98.OUT19.TMIN |
| SCANOUT17 | output | CELL99.OUT16.TMIN |
| SCANOUT18 | output | CELL99.OUT17.TMIN |
| SCANOUT19 | output | CELL99.OUT18.TMIN |
| SCANOUT2 | output | CELL95.OUT17.TMIN |
| SCANOUT20 | output | CELL99.OUT19.TMIN |
| SCANOUT21 | output | CELL95.OUT20.TMIN |
| SCANOUT22 | output | CELL95.OUT21.TMIN |
| SCANOUT23 | output | CELL95.OUT22.TMIN |
| SCANOUT24 | output | CELL95.OUT23.TMIN |
| SCANOUT3 | output | CELL95.OUT18.TMIN |
| SCANOUT4 | output | CELL95.OUT19.TMIN |
| SCANOUT5 | output | CELL96.OUT16.TMIN |
| SCANOUT6 | output | CELL96.OUT17.TMIN |
| SCANOUT7 | output | CELL96.OUT18.TMIN |
| SCANOUT8 | output | CELL96.OUT19.TMIN |
| SCANOUT9 | output | CELL97.OUT16.TMIN |
| USERCLK | input | CELL25.IMUX.CLK0 |
| XILUNCONNOUT0 | output | CELL96.OUT20.TMIN |
| XILUNCONNOUT1 | output | CELL96.OUT21.TMIN |
| XILUNCONNOUT10 | output | CELL98.OUT22.TMIN |
| XILUNCONNOUT11 | output | CELL98.OUT23.TMIN |
| XILUNCONNOUT12 | output | CELL99.OUT20.TMIN |
| XILUNCONNOUT13 | output | CELL99.OUT21.TMIN |
| XILUNCONNOUT14 | output | CELL99.OUT22.TMIN |
| XILUNCONNOUT15 | output | CELL99.OUT23.TMIN |
| XILUNCONNOUT16 | output | CELL43.OUT21.TMIN |
| XILUNCONNOUT17 | output | CELL38.OUT23.TMIN |
| XILUNCONNOUT18 | output | CELL37.OUT20.TMIN |
| XILUNCONNOUT19 | output | CELL37.OUT21.TMIN |
| XILUNCONNOUT2 | output | CELL96.OUT22.TMIN |
| XILUNCONNOUT20 | output | CELL37.OUT22.TMIN |
| XILUNCONNOUT21 | output | CELL37.OUT23.TMIN |
| XILUNCONNOUT22 | output | CELL36.OUT20.TMIN |
| XILUNCONNOUT23 | output | CELL36.OUT21.TMIN |
| XILUNCONNOUT24 | output | CELL36.OUT22.TMIN |
| XILUNCONNOUT25 | output | CELL36.OUT23.TMIN |
| XILUNCONNOUT26 | output | CELL9.OUT23.TMIN |
| XILUNCONNOUT27 | output | CELL8.OUT17.TMIN |
| XILUNCONNOUT28 | output | CELL7.OUT21.TMIN |
| XILUNCONNOUT29 | output | CELL5.OUT22.TMIN |
| XILUNCONNOUT3 | output | CELL96.OUT23.TMIN |
| XILUNCONNOUT4 | output | CELL97.OUT20.TMIN |
| XILUNCONNOUT5 | output | CELL97.OUT21.TMIN |
| XILUNCONNOUT6 | output | CELL97.OUT22.TMIN |
| XILUNCONNOUT7 | output | CELL97.OUT23.TMIN |
| XILUNCONNOUT8 | output | CELL98.OUT20.TMIN |
| XILUNCONNOUT9 | output | CELL98.OUT21.TMIN |
Bel wires
| Wire | Pins |
|---|---|
| CELL0.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA0 |
| CELL0.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA1 |
| CELL0.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA2 |
| CELL0.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA3 |
| CELL0.IMUX.IMUX4.DELAY | PCIE3.MIREQUESTRAMREADDATA4 |
| CELL0.IMUX.IMUX5.DELAY | PCIE3.MIREQUESTRAMREADDATA5 |
| CELL0.IMUX.IMUX6.DELAY | PCIE3.MIREQUESTRAMREADDATA6 |
| CELL0.IMUX.IMUX7.DELAY | PCIE3.MIREQUESTRAMREADDATA7 |
| CELL0.IMUX.IMUX8.DELAY | PCIE3.MIREQUESTRAMREADDATA8 |
| CELL0.IMUX.IMUX9.DELAY | PCIE3.MIREQUESTRAMREADDATA9 |
| CELL0.IMUX.IMUX10.DELAY | PCIE3.MIREQUESTRAMREADDATA10 |
| CELL0.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA0 |
| CELL0.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTDATA1 |
| CELL0.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTDATA2 |
| CELL0.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTDATA3 |
| CELL0.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTLAST |
| CELL0.IMUX.IMUX16.DELAY | PCIE3.PCIECQNPREQ |
| CELL0.IMUX.IMUX17.DELAY | PCIE3.SAXISRQTUSER0 |
| CELL0.IMUX.IMUX18.DELAY | PCIE3.SAXISRQTUSER1 |
| CELL0.IMUX.IMUX19.DELAY | PCIE3.SAXISRQTKEEP0 |
| CELL0.IMUX.IMUX20.DELAY | PCIE3.SAXISRQTKEEP1 |
| CELL0.IMUX.IMUX21.DELAY | PCIE3.SAXISRQTKEEP2 |
| CELL0.IMUX.IMUX22.DELAY | PCIE3.SAXISRQTKEEP3 |
| CELL0.IMUX.IMUX23.DELAY | PCIE3.SAXISRQTVALID |
| CELL0.OUT0.TMIN | PCIE3.MAXISRCTDATA0 |
| CELL0.OUT1.TMIN | PCIE3.MIREQUESTRAMWRITEDATA15 |
| CELL0.OUT2.TMIN | PCIE3.MIREQUESTRAMWRITEDATA8 |
| CELL0.OUT3.TMIN | PCIE3.MIREQUESTRAMWRITEDATA2 |
| CELL0.OUT4.TMIN | PCIE3.MIREQUESTRAMWRITEDATA21 |
| CELL0.OUT5.TMIN | PCIE3.MIREQUESTRAMWRITEDATA1 |
| CELL0.OUT6.TMIN | PCIE3.MIREQUESTRAMWRITEDATA7 |
| CELL0.OUT7.TMIN | PCIE3.MIREQUESTRAMWRITEDATA3 |
| CELL0.OUT8.TMIN | PCIE3.MAXISRCTDATA1 |
| CELL0.OUT9.TMIN | PCIE3.MAXISRCTDATA2 |
| CELL0.OUT10.TMIN | PCIE3.MAXISRCTDATA3 |
| CELL0.OUT11.TMIN | PCIE3.MAXISRCTLAST |
| CELL0.OUT12.TMIN | PCIE3.PCIECQNPREQCOUNT0 |
| CELL0.OUT13.TMIN | PCIE3.PCIECQNPREQCOUNT1 |
| CELL0.OUT14.TMIN | PCIE3.PCIECQNPREQCOUNT2 |
| CELL0.OUT15.TMIN | PCIE3.CFGINTERRUPTSENT |
| CELL0.OUT16.TMIN | PCIE3.MIREQUESTRAMWRITEDATA29 |
| CELL0.OUT17.TMIN | PCIE3.MIREQUESTRAMWRITEDATA16 |
| CELL0.OUT18.TMIN | PCIE3.MIREQUESTRAMWRITEDATA25 |
| CELL0.OUT19.TMIN | PCIE3.MIREQUESTRAMWRITEDATA19 |
| CELL0.OUT20.TMIN | PCIE3.MIREQUESTRAMWRITEDATA26 |
| CELL0.OUT21.TMIN | PCIE3.MIREQUESTRAMWRITEDATA34 |
| CELL0.OUT22.TMIN | PCIE3.CFGINTERRUPTAOUTPUT |
| CELL0.OUT23.TMIN | PCIE3.MIREQUESTRAMWRITEDATA30 |
| CELL1.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA11 |
| CELL1.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA12 |
| CELL1.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA13 |
| CELL1.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA14 |
| CELL1.IMUX.IMUX4.DELAY | PCIE3.MIREQUESTRAMREADDATA15 |
| CELL1.IMUX.IMUX5.DELAY | PCIE3.MIREQUESTRAMREADDATA16 |
| CELL1.IMUX.IMUX6.DELAY | PCIE3.MIREQUESTRAMREADDATA17 |
| CELL1.IMUX.IMUX7.DELAY | PCIE3.MIREQUESTRAMREADDATA18 |
| CELL1.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA4 |
| CELL1.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA5 |
| CELL1.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA6 |
| CELL1.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA7 |
| CELL1.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTUSER2 |
| CELL1.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTUSER3 |
| CELL1.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTUSER4 |
| CELL1.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTUSER5 |
| CELL1.IMUX.IMUX16.DELAY | PCIE3.SAXISRQTKEEP4 |
| CELL1.IMUX.IMUX17.DELAY | PCIE3.SAXISRQTKEEP5 |
| CELL1.IMUX.IMUX18.DELAY | PCIE3.SAXISRQTKEEP6 |
| CELL1.IMUX.IMUX19.DELAY | PCIE3.SAXISRQTKEEP7 |
| CELL1.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTINT0 |
| CELL1.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTINT1 |
| CELL1.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTINT2 |
| CELL1.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTINT3 |
| CELL1.OUT0.TMIN | PCIE3.MIREQUESTRAMWRITEDATA4 |
| CELL1.OUT1.TMIN | PCIE3.MIREQUESTRAMWRITEDATA5 |
| CELL1.OUT2.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSA6 |
| CELL1.OUT3.TMIN | PCIE3.MIREQUESTRAMREADADDRESSA6 |
| CELL1.OUT4.TMIN | PCIE3.MIREQUESTRAMWRITEDATA12 |
| CELL1.OUT5.TMIN | PCIE3.MIREQUESTRAMWRITEDATA22 |
| CELL1.OUT6.TMIN | PCIE3.MIREQUESTRAMWRITEDATA6 |
| CELL1.OUT7.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSA5 |
| CELL1.OUT8.TMIN | PCIE3.MIREQUESTRAMWRITEDATA14 |
| CELL1.OUT9.TMIN | PCIE3.MIREQUESTRAMWRITEDATA0 |
| CELL1.OUT10.TMIN | PCIE3.MIREQUESTRAMWRITEDATA37 |
| CELL1.OUT11.TMIN | PCIE3.MIREQUESTRAMREADADDRESSA7 |
| CELL1.OUT12.TMIN | PCIE3.MIREQUESTRAMWRITEDATA36 |
| CELL1.OUT13.TMIN | PCIE3.MIREQUESTRAMWRITEDATA54 |
| CELL1.OUT14.TMIN | PCIE3.MIREQUESTRAMREADADDRESSA3 |
| CELL1.OUT15.TMIN | PCIE3.MIREQUESTRAMWRITEDATA18 |
| CELL1.OUT16.TMIN | PCIE3.MIREQUESTRAMWRITEDATA27 |
| CELL1.OUT17.TMIN | PCIE3.MIREQUESTRAMWRITEDATA9 |
| CELL1.OUT18.TMIN | PCIE3.MIREQUESTRAMWRITEDATA35 |
| CELL1.OUT19.TMIN | PCIE3.MIREQUESTRAMWRITEDATA10 |
| CELL1.OUT20.TMIN | PCIE3.MIREQUESTRAMWRITEDATA11 |
| CELL1.OUT21.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSA8 |
| CELL1.OUT22.TMIN | PCIE3.MIREQUESTRAMWRITEDATA46 |
| CELL1.OUT23.TMIN | PCIE3.MIREQUESTRAMWRITEDATA28 |
| CELL2.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA19 |
| CELL2.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA20 |
| CELL2.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA21 |
| CELL2.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA22 |
| CELL2.IMUX.IMUX4.DELAY | PCIE3.MIREQUESTRAMREADDATA23 |
| CELL2.IMUX.IMUX5.DELAY | PCIE3.MIREQUESTRAMREADDATA24 |
| CELL2.IMUX.IMUX6.DELAY | PCIE3.MIREQUESTRAMREADDATA25 |
| CELL2.IMUX.IMUX7.DELAY | PCIE3.MIREQUESTRAMREADDATA26 |
| CELL2.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA8 |
| CELL2.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA9 |
| CELL2.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA10 |
| CELL2.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA11 |
| CELL2.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTUSER6 |
| CELL2.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTUSER7 |
| CELL2.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTUSER8 |
| CELL2.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTUSER9 |
| CELL2.IMUX.IMUX16.DELAY | PCIE3.MAXISRCTREADY0 |
| CELL2.IMUX.IMUX17.DELAY | PCIE3.MAXISRCTREADY1 |
| CELL2.IMUX.IMUX18.DELAY | PCIE3.MAXISRCTREADY2 |
| CELL2.IMUX.IMUX19.DELAY | PCIE3.MAXISRCTREADY3 |
| CELL2.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTPENDING0 |
| CELL2.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTPENDING1 |
| CELL2.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIINT0 |
| CELL2.IMUX.IMUX47.DELAY | PCIE3.MIREQUESTRAMREADDATA27 |
| CELL2.OUT0.TMIN | PCIE3.MIREQUESTRAMREADADDRESSB7 |
| CELL2.OUT1.TMIN | PCIE3.MIREQUESTRAMREADENABLE0 |
| CELL2.OUT2.TMIN | PCIE3.MIREQUESTRAMREADADDRESSA2 |
| CELL2.OUT3.TMIN | PCIE3.MIREQUESTRAMWRITEDATA62 |
| CELL2.OUT4.TMIN | PCIE3.MIREQUESTRAMREADENABLE1 |
| CELL2.OUT5.TMIN | PCIE3.MIREQUESTRAMWRITEDATA38 |
| CELL2.OUT6.TMIN | PCIE3.MAXISRCTDATA4 |
| CELL2.OUT7.TMIN | PCIE3.MAXISRCTDATA5 |
| CELL2.OUT8.TMIN | PCIE3.MIREQUESTRAMWRITEDATA23 |
| CELL2.OUT9.TMIN | PCIE3.MIREQUESTRAMWRITEDATA31 |
| CELL2.OUT10.TMIN | PCIE3.MIREQUESTRAMWRITEENABLE0 |
| CELL2.OUT11.TMIN | PCIE3.MIREQUESTRAMWRITEENABLE1 |
| CELL2.OUT12.TMIN | PCIE3.MAXISRCTDATA6 |
| CELL2.OUT13.TMIN | PCIE3.MIREQUESTRAMWRITEDATA17 |
| CELL2.OUT14.TMIN | PCIE3.MIREQUESTRAMWRITEDATA32 |
| CELL2.OUT15.TMIN | PCIE3.MIREQUESTRAMWRITEDATA63 |
| CELL2.OUT16.TMIN | PCIE3.MAXISRCTDATA7 |
| CELL2.OUT17.TMIN | PCIE3.PCIECQNPREQCOUNT3 |
| CELL2.OUT18.TMIN | PCIE3.MIREQUESTRAMWRITEDATA24 |
| CELL2.OUT19.TMIN | PCIE3.CFGINTERRUPTBOUTPUT |
| CELL2.OUT20.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSA0 |
| CELL2.OUT21.TMIN | PCIE3.CFGINTERRUPTCOUTPUT |
| CELL2.OUT22.TMIN | PCIE3.MIREQUESTRAMWRITEDATA13 |
| CELL2.OUT23.TMIN | PCIE3.MIREQUESTRAMWRITEDATA68 |
| CELL3.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA28 |
| CELL3.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA29 |
| CELL3.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA30 |
| CELL3.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA31 |
| CELL3.IMUX.IMUX4.DELAY | PCIE3.MIREQUESTRAMREADDATA32 |
| CELL3.IMUX.IMUX5.DELAY | PCIE3.MIREQUESTRAMREADDATA33 |
| CELL3.IMUX.IMUX6.DELAY | PCIE3.MIREQUESTRAMREADDATA34 |
| CELL3.IMUX.IMUX7.DELAY | PCIE3.MIREQUESTRAMREADDATA35 |
| CELL3.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA12 |
| CELL3.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA13 |
| CELL3.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA14 |
| CELL3.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA15 |
| CELL3.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTUSER10 |
| CELL3.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTUSER11 |
| CELL3.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTUSER12 |
| CELL3.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTUSER13 |
| CELL3.IMUX.IMUX16.DELAY | PCIE3.MAXISRCTREADY4 |
| CELL3.IMUX.IMUX17.DELAY | PCIE3.MAXISRCTREADY5 |
| CELL3.IMUX.IMUX18.DELAY | PCIE3.MAXISRCTREADY6 |
| CELL3.IMUX.IMUX19.DELAY | PCIE3.MAXISRCTREADY7 |
| CELL3.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIINT1 |
| CELL3.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIINT2 |
| CELL3.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIINT3 |
| CELL3.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIINT4 |
| CELL3.OUT0.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSA3 |
| CELL3.OUT1.TMIN | PCIE3.MIREQUESTRAMREADADDRESSA8 |
| CELL3.OUT2.TMIN | PCIE3.MIREQUESTRAMWRITEDATA60 |
| CELL3.OUT3.TMIN | PCIE3.MIREQUESTRAMWRITEDATA59 |
| CELL3.OUT4.TMIN | PCIE3.MIREQUESTRAMREADADDRESSA0 |
| CELL3.OUT5.TMIN | PCIE3.MIREQUESTRAMWRITEDATA43 |
| CELL3.OUT6.TMIN | PCIE3.MIREQUESTRAMREADADDRESSA5 |
| CELL3.OUT7.TMIN | PCIE3.MIREQUESTRAMWRITEDATA52 |
| CELL3.OUT8.TMIN | PCIE3.MIREQUESTRAMWRITEDATA80 |
| CELL3.OUT9.TMIN | PCIE3.MIREQUESTRAMWRITEDATA41 |
| CELL3.OUT10.TMIN | PCIE3.MIREQUESTRAMWRITEDATA61 |
| CELL3.OUT11.TMIN | PCIE3.MIREQUESTRAMWRITEDATA40 |
| CELL3.OUT12.TMIN | PCIE3.MIREQUESTRAMREADADDRESSA4 |
| CELL3.OUT13.TMIN | PCIE3.MIREQUESTRAMWRITEDATA39 |
| CELL3.OUT14.TMIN | PCIE3.MIREQUESTRAMWRITEDATA58 |
| CELL3.OUT15.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSA7 |
| CELL3.OUT16.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSA2 |
| CELL3.OUT17.TMIN | PCIE3.MIREQUESTRAMREADADDRESSB4 |
| CELL3.OUT18.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSA1 |
| CELL3.OUT19.TMIN | PCIE3.MIREQUESTRAMWRITEDATA33 |
| CELL3.OUT20.TMIN | PCIE3.MIREQUESTRAMWRITEDATA44 |
| CELL3.OUT21.TMIN | PCIE3.MIREQUESTRAMWRITEDATA67 |
| CELL3.OUT22.TMIN | PCIE3.MIREQUESTRAMWRITEDATA42 |
| CELL3.OUT23.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSA4 |
| CELL4.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA36 |
| CELL4.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA37 |
| CELL4.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA38 |
| CELL4.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA39 |
| CELL4.IMUX.IMUX4.DELAY | PCIE3.MIREQUESTRAMREADDATA40 |
| CELL4.IMUX.IMUX5.DELAY | PCIE3.MIREQUESTRAMREADDATA41 |
| CELL4.IMUX.IMUX6.DELAY | PCIE3.MIREQUESTRAMREADDATA42 |
| CELL4.IMUX.IMUX7.DELAY | PCIE3.MIREQUESTRAMREADDATA43 |
| CELL4.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA16 |
| CELL4.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA17 |
| CELL4.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA18 |
| CELL4.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA19 |
| CELL4.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTUSER14 |
| CELL4.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTUSER15 |
| CELL4.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTUSER16 |
| CELL4.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTUSER17 |
| CELL4.IMUX.IMUX16.DELAY | PCIE3.MAXISRCTREADY8 |
| CELL4.IMUX.IMUX17.DELAY | PCIE3.MAXISRCTREADY9 |
| CELL4.IMUX.IMUX18.DELAY | PCIE3.MAXISRCTREADY10 |
| CELL4.IMUX.IMUX19.DELAY | PCIE3.MAXISRCTREADY11 |
| CELL4.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIINT5 |
| CELL4.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIINT6 |
| CELL4.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIINT7 |
| CELL4.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIINT8 |
| CELL4.OUT0.TMIN | PCIE3.MIREQUESTRAMWRITEDATA56 |
| CELL4.OUT1.TMIN | PCIE3.MIREQUESTRAMWRITEDATA70 |
| CELL4.OUT2.TMIN | PCIE3.MIREQUESTRAMWRITEDATA69 |
| CELL4.OUT3.TMIN | PCIE3.MIREQUESTRAMWRITEDATA76 |
| CELL4.OUT4.TMIN | PCIE3.MIREQUESTRAMWRITEDATA65 |
| CELL4.OUT5.TMIN | PCIE3.MIREQUESTRAMWRITEDATA50 |
| CELL4.OUT6.TMIN | PCIE3.MIREQUESTRAMWRITEDATA85 |
| CELL4.OUT7.TMIN | PCIE3.MIREQUESTRAMWRITEDATA72 |
| CELL4.OUT8.TMIN | PCIE3.MIREQUESTRAMWRITEDATA48 |
| CELL4.OUT9.TMIN | PCIE3.MIREQUESTRAMWRITEDATA45 |
| CELL4.OUT10.TMIN | PCIE3.MIREQUESTRAMWRITEDATA66 |
| CELL4.OUT11.TMIN | PCIE3.MIREQUESTRAMWRITEDATA20 |
| CELL4.OUT12.TMIN | PCIE3.MIREQUESTRAMWRITEDATA49 |
| CELL4.OUT13.TMIN | PCIE3.MIREQUESTRAMWRITEDATA53 |
| CELL4.OUT14.TMIN | PCIE3.MIREQUESTRAMWRITEDATA51 |
| CELL4.OUT15.TMIN | PCIE3.MIREQUESTRAMWRITEDATA47 |
| CELL4.OUT16.TMIN | PCIE3.MAXISRCTDATA8 |
| CELL4.OUT17.TMIN | PCIE3.MAXISRCTDATA9 |
| CELL4.OUT18.TMIN | PCIE3.MAXISRCTDATA10 |
| CELL4.OUT19.TMIN | PCIE3.MAXISRCTDATA11 |
| CELL4.OUT20.TMIN | PCIE3.PCIECQNPREQCOUNT4 |
| CELL4.OUT21.TMIN | PCIE3.PCIECQNPREQCOUNT5 |
| CELL4.OUT22.TMIN | PCIE3.CFGINTERRUPTDOUTPUT |
| CELL4.OUT23.TMIN | PCIE3.CFGINTERRUPTMSIENABLE0 |
| CELL5.IMUX.CLK0 | PCIE3.CORECLKMIREQUESTRAM |
| CELL5.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA44 |
| CELL5.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA45 |
| CELL5.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA46 |
| CELL5.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA47 |
| CELL5.IMUX.IMUX4.DELAY | PCIE3.MIREQUESTRAMREADDATA48 |
| CELL5.IMUX.IMUX5.DELAY | PCIE3.MIREQUESTRAMREADDATA49 |
| CELL5.IMUX.IMUX6.DELAY | PCIE3.MIREQUESTRAMREADDATA50 |
| CELL5.IMUX.IMUX7.DELAY | PCIE3.MIREQUESTRAMREADDATA51 |
| CELL5.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA20 |
| CELL5.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA21 |
| CELL5.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA22 |
| CELL5.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA23 |
| CELL5.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTUSER18 |
| CELL5.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTUSER19 |
| CELL5.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTUSER20 |
| CELL5.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTUSER21 |
| CELL5.IMUX.IMUX16.DELAY | PCIE3.MAXISRCTREADY12 |
| CELL5.IMUX.IMUX17.DELAY | PCIE3.MAXISRCTREADY13 |
| CELL5.IMUX.IMUX18.DELAY | PCIE3.MAXISRCTREADY14 |
| CELL5.IMUX.IMUX19.DELAY | PCIE3.MAXISRCTREADY15 |
| CELL5.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIINT9 |
| CELL5.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIINT10 |
| CELL5.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIINT11 |
| CELL5.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIINT12 |
| CELL5.OUT0.TMIN | PCIE3.MAXISRCTDATA12 |
| CELL5.OUT1.TMIN | PCIE3.MIREQUESTRAMWRITEDATA83 |
| CELL5.OUT2.TMIN | PCIE3.MIREQUESTRAMWRITEDATA103 |
| CELL5.OUT3.TMIN | PCIE3.MIREQUESTRAMWRITEDATA82 |
| CELL5.OUT4.TMIN | PCIE3.MIREQUESTRAMWRITEDATA88 |
| CELL5.OUT5.TMIN | PCIE3.MIREQUESTRAMWRITEDATA64 |
| CELL5.OUT6.TMIN | PCIE3.MIREQUESTRAMWRITEDATA57 |
| CELL5.OUT7.TMIN | PCIE3.MIREQUESTRAMWRITEDATA78 |
| CELL5.OUT8.TMIN | PCIE3.MAXISRCTDATA13 |
| CELL5.OUT9.TMIN | PCIE3.MAXISRCTDATA14 |
| CELL5.OUT10.TMIN | PCIE3.MAXISRCTDATA15 |
| CELL5.OUT11.TMIN | PCIE3.MAXISRCTUSER0 |
| CELL5.OUT12.TMIN | PCIE3.MAXISRCTUSER1 |
| CELL5.OUT13.TMIN | PCIE3.MAXISRCTUSER2 |
| CELL5.OUT14.TMIN | PCIE3.MAXISRCTUSER3 |
| CELL5.OUT15.TMIN | PCIE3.CFGINTERRUPTMSIENABLE1 |
| CELL5.OUT16.TMIN | PCIE3.MIREQUESTRAMWRITEDATA93 |
| CELL5.OUT17.TMIN | PCIE3.MIREQUESTRAMWRITEDATA90 |
| CELL5.OUT18.TMIN | PCIE3.MIREQUESTRAMWRITEDATA86 |
| CELL5.OUT19.TMIN | PCIE3.MIREQUESTRAMWRITEDATA112 |
| CELL5.OUT20.TMIN | PCIE3.MIREQUESTRAMWRITEDATA71 |
| CELL5.OUT21.TMIN | PCIE3.MIREQUESTRAMWRITEDATA109 |
| CELL5.OUT22.TMIN | PCIE3.XILUNCONNOUT29 |
| CELL5.OUT23.TMIN | PCIE3.MIREQUESTRAMWRITEDATA100 |
| CELL6.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA52 |
| CELL6.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA53 |
| CELL6.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA54 |
| CELL6.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA55 |
| CELL6.IMUX.IMUX4.DELAY | PCIE3.MIREQUESTRAMREADDATA56 |
| CELL6.IMUX.IMUX5.DELAY | PCIE3.MIREQUESTRAMREADDATA57 |
| CELL6.IMUX.IMUX6.DELAY | PCIE3.MIREQUESTRAMREADDATA58 |
| CELL6.IMUX.IMUX7.DELAY | PCIE3.MIREQUESTRAMREADDATA59 |
| CELL6.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA24 |
| CELL6.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA25 |
| CELL6.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA26 |
| CELL6.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA27 |
| CELL6.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTUSER22 |
| CELL6.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTUSER23 |
| CELL6.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTUSER24 |
| CELL6.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTUSER25 |
| CELL6.IMUX.IMUX16.DELAY | PCIE3.MAXISRCTREADY16 |
| CELL6.IMUX.IMUX17.DELAY | PCIE3.MAXISRCTREADY17 |
| CELL6.IMUX.IMUX18.DELAY | PCIE3.MAXISRCTREADY18 |
| CELL6.IMUX.IMUX19.DELAY | PCIE3.MAXISRCTREADY19 |
| CELL6.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIINT13 |
| CELL6.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIINT14 |
| CELL6.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIINT15 |
| CELL6.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIINT16 |
| CELL6.OUT0.TMIN | PCIE3.MIREQUESTRAMWRITEDATA73 |
| CELL6.OUT1.TMIN | PCIE3.MIREQUESTRAMWRITEDATA91 |
| CELL6.OUT2.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSB2 |
| CELL6.OUT3.TMIN | PCIE3.MIREQUESTRAMREADADDRESSB1 |
| CELL6.OUT4.TMIN | PCIE3.MIREQUESTRAMWRITEDATA96 |
| CELL6.OUT5.TMIN | PCIE3.MIREQUESTRAMWRITEDATA97 |
| CELL6.OUT6.TMIN | PCIE3.MIREQUESTRAMWRITEDATA89 |
| CELL6.OUT7.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSB5 |
| CELL6.OUT8.TMIN | PCIE3.MIREQUESTRAMWRITEDATA55 |
| CELL6.OUT9.TMIN | PCIE3.MIREQUESTRAMWRITEDATA75 |
| CELL6.OUT10.TMIN | PCIE3.MIREQUESTRAMWRITEDATA108 |
| CELL6.OUT11.TMIN | PCIE3.MIREQUESTRAMREADADDRESSB6 |
| CELL6.OUT12.TMIN | PCIE3.MIREQUESTRAMWRITEDATA98 |
| CELL6.OUT13.TMIN | PCIE3.MIREQUESTRAMWRITEDATA92 |
| CELL6.OUT14.TMIN | PCIE3.MIREQUESTRAMREADADDRESSB2 |
| CELL6.OUT15.TMIN | PCIE3.MIREQUESTRAMWRITEDATA105 |
| CELL6.OUT16.TMIN | PCIE3.MIREQUESTRAMWRITEDATA102 |
| CELL6.OUT17.TMIN | PCIE3.MIREQUESTRAMWRITEDATA74 |
| CELL6.OUT18.TMIN | PCIE3.MIREQUESTRAMWRITEDATA106 |
| CELL6.OUT19.TMIN | PCIE3.MIREQUESTRAMWRITEDATA94 |
| CELL6.OUT20.TMIN | PCIE3.MIREQUESTRAMWRITEDATA99 |
| CELL6.OUT21.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSB1 |
| CELL6.OUT22.TMIN | PCIE3.MIREQUESTRAMWRITEDATA126 |
| CELL6.OUT23.TMIN | PCIE3.MIREQUESTRAMWRITEDATA77 |
| CELL7.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA60 |
| CELL7.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA61 |
| CELL7.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA62 |
| CELL7.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA63 |
| CELL7.IMUX.IMUX4.DELAY | PCIE3.MIREQUESTRAMREADDATA64 |
| CELL7.IMUX.IMUX5.DELAY | PCIE3.MIREQUESTRAMREADDATA65 |
| CELL7.IMUX.IMUX6.DELAY | PCIE3.MIREQUESTRAMREADDATA66 |
| CELL7.IMUX.IMUX7.DELAY | PCIE3.MIREQUESTRAMREADDATA67 |
| CELL7.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA28 |
| CELL7.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA29 |
| CELL7.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA30 |
| CELL7.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA31 |
| CELL7.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTUSER26 |
| CELL7.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTUSER27 |
| CELL7.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTUSER28 |
| CELL7.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTUSER29 |
| CELL7.IMUX.IMUX16.DELAY | PCIE3.MAXISRCTREADY20 |
| CELL7.IMUX.IMUX17.DELAY | PCIE3.MAXISRCTREADY21 |
| CELL7.IMUX.IMUX18.DELAY | PCIE3.CFGMGMTADDR0 |
| CELL7.IMUX.IMUX19.DELAY | PCIE3.CFGMGMTADDR1 |
| CELL7.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIINT17 |
| CELL7.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIINT18 |
| CELL7.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIINT19 |
| CELL7.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIINT20 |
| CELL7.OUT0.TMIN | PCIE3.MAXISRCTDATA16 |
| CELL7.OUT1.TMIN | PCIE3.MAXISRCTDATA17 |
| CELL7.OUT2.TMIN | PCIE3.MIREQUESTRAMREADADDRESSB5 |
| CELL7.OUT3.TMIN | PCIE3.MIREQUESTRAMWRITEDATA139 |
| CELL7.OUT4.TMIN | PCIE3.MIREQUESTRAMREADENABLE2 |
| CELL7.OUT5.TMIN | PCIE3.MIREQUESTRAMWRITEDATA121 |
| CELL7.OUT6.TMIN | PCIE3.MAXISRCTDATA18 |
| CELL7.OUT7.TMIN | PCIE3.MAXISRCTDATA19 |
| CELL7.OUT8.TMIN | PCIE3.MIREQUESTRAMWRITEDATA79 |
| CELL7.OUT9.TMIN | PCIE3.MIREQUESTRAMWRITEDATA116 |
| CELL7.OUT10.TMIN | PCIE3.MIREQUESTRAMWRITEENABLE2 |
| CELL7.OUT11.TMIN | PCIE3.MIREQUESTRAMWRITEENABLE3 |
| CELL7.OUT12.TMIN | PCIE3.MIREQUESTRAMREADENABLE3 |
| CELL7.OUT13.TMIN | PCIE3.MIREQUESTRAMWRITEDATA95 |
| CELL7.OUT14.TMIN | PCIE3.MIREQUESTRAMWRITEDATA101 |
| CELL7.OUT15.TMIN | PCIE3.MIREQUESTRAMWRITEDATA104 |
| CELL7.OUT16.TMIN | PCIE3.MAXISRCTUSER4 |
| CELL7.OUT17.TMIN | PCIE3.MAXISRCTUSER5 |
| CELL7.OUT18.TMIN | PCIE3.MIREQUESTRAMWRITEDATA84 |
| CELL7.OUT19.TMIN | PCIE3.CFGINTERRUPTMSIVFENABLE0 |
| CELL7.OUT20.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSB3 |
| CELL7.OUT21.TMIN | PCIE3.XILUNCONNOUT28 |
| CELL7.OUT22.TMIN | PCIE3.MIREQUESTRAMWRITEDATA81 |
| CELL7.OUT23.TMIN | PCIE3.MIREQUESTRAMWRITEDATA133 |
| CELL8.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA68 |
| CELL8.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA69 |
| CELL8.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA70 |
| CELL8.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA71 |
| CELL8.IMUX.IMUX4.DELAY | PCIE3.MIREQUESTRAMREADDATA72 |
| CELL8.IMUX.IMUX5.DELAY | PCIE3.MIREQUESTRAMREADDATA73 |
| CELL8.IMUX.IMUX6.DELAY | PCIE3.MIREQUESTRAMREADDATA74 |
| CELL8.IMUX.IMUX7.DELAY | PCIE3.MIREQUESTRAMREADDATA75 |
| CELL8.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA32 |
| CELL8.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA33 |
| CELL8.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA34 |
| CELL8.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA35 |
| CELL8.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTUSER30 |
| CELL8.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTUSER31 |
| CELL8.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTUSER32 |
| CELL8.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTUSER33 |
| CELL8.IMUX.IMUX16.DELAY | PCIE3.CFGMGMTADDR2 |
| CELL8.IMUX.IMUX17.DELAY | PCIE3.CFGMGMTADDR3 |
| CELL8.IMUX.IMUX18.DELAY | PCIE3.CFGMGMTADDR4 |
| CELL8.IMUX.IMUX19.DELAY | PCIE3.CFGMGMTADDR5 |
| CELL8.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIINT21 |
| CELL8.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIINT22 |
| CELL8.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIINT23 |
| CELL8.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIINT24 |
| CELL8.OUT0.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSB8 |
| CELL8.OUT1.TMIN | PCIE3.MIREQUESTRAMREADADDRESSB3 |
| CELL8.OUT2.TMIN | PCIE3.MIREQUESTRAMWRITEDATA136 |
| CELL8.OUT3.TMIN | PCIE3.MIREQUESTRAMWRITEDATA135 |
| CELL8.OUT4.TMIN | PCIE3.MIREQUESTRAMREADADDRESSB0 |
| CELL8.OUT5.TMIN | PCIE3.MIREQUESTRAMWRITEDATA137 |
| CELL8.OUT6.TMIN | PCIE3.MIREQUESTRAMREADADDRESSB8 |
| CELL8.OUT7.TMIN | PCIE3.MIREQUESTRAMWRITEDATA140 |
| CELL8.OUT8.TMIN | PCIE3.MIREQUESTRAMWRITEDATA124 |
| CELL8.OUT9.TMIN | PCIE3.MIREQUESTRAMWRITEDATA125 |
| CELL8.OUT10.TMIN | PCIE3.MIREQUESTRAMWRITEDATA117 |
| CELL8.OUT11.TMIN | PCIE3.MIREQUESTRAMWRITEDATA120 |
| CELL8.OUT12.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSB6 |
| CELL8.OUT13.TMIN | PCIE3.MIREQUESTRAMWRITEDATA113 |
| CELL8.OUT14.TMIN | PCIE3.MIREQUESTRAMWRITEDATA122 |
| CELL8.OUT15.TMIN | PCIE3.MIREQUESTRAMREADADDRESSA1 |
| CELL8.OUT16.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSB7 |
| CELL8.OUT17.TMIN | PCIE3.XILUNCONNOUT27 |
| CELL8.OUT18.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSB0 |
| CELL8.OUT19.TMIN | PCIE3.MIREQUESTRAMWRITEDATA87 |
| CELL8.OUT20.TMIN | PCIE3.MIREQUESTRAMWRITEDATA111 |
| CELL8.OUT21.TMIN | PCIE3.MIREQUESTRAMWRITEDATA143 |
| CELL8.OUT22.TMIN | PCIE3.MIREQUESTRAMWRITEDATA107 |
| CELL8.OUT23.TMIN | PCIE3.MIREQUESTRAMWRITEADDRESSB4 |
| CELL9.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA76 |
| CELL9.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA77 |
| CELL9.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA78 |
| CELL9.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA79 |
| CELL9.IMUX.IMUX4.DELAY | PCIE3.MIREQUESTRAMREADDATA80 |
| CELL9.IMUX.IMUX5.DELAY | PCIE3.MIREQUESTRAMREADDATA81 |
| CELL9.IMUX.IMUX6.DELAY | PCIE3.MIREQUESTRAMREADDATA82 |
| CELL9.IMUX.IMUX7.DELAY | PCIE3.MIREQUESTRAMREADDATA83 |
| CELL9.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA36 |
| CELL9.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA37 |
| CELL9.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA38 |
| CELL9.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA39 |
| CELL9.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTUSER34 |
| CELL9.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTUSER35 |
| CELL9.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTUSER36 |
| CELL9.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTUSER37 |
| CELL9.IMUX.IMUX16.DELAY | PCIE3.CFGMGMTADDR6 |
| CELL9.IMUX.IMUX17.DELAY | PCIE3.CFGMGMTADDR7 |
| CELL9.IMUX.IMUX18.DELAY | PCIE3.CFGMGMTADDR8 |
| CELL9.IMUX.IMUX19.DELAY | PCIE3.CFGMGMTADDR9 |
| CELL9.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIINT25 |
| CELL9.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIINT26 |
| CELL9.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIINT27 |
| CELL9.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIINT28 |
| CELL9.OUT0.TMIN | PCIE3.MIREQUESTRAMWRITEDATA130 |
| CELL9.OUT1.TMIN | PCIE3.MIREQUESTRAMWRITEDATA134 |
| CELL9.OUT2.TMIN | PCIE3.MIREQUESTRAMWRITEDATA127 |
| CELL9.OUT3.TMIN | PCIE3.MIREQUESTRAMWRITEDATA129 |
| CELL9.OUT4.TMIN | PCIE3.MIREQUESTRAMWRITEDATA142 |
| CELL9.OUT5.TMIN | PCIE3.MIREQUESTRAMWRITEDATA131 |
| CELL9.OUT6.TMIN | PCIE3.MIREQUESTRAMWRITEDATA141 |
| CELL9.OUT7.TMIN | PCIE3.MIREQUESTRAMWRITEDATA132 |
| CELL9.OUT8.TMIN | PCIE3.MIREQUESTRAMWRITEDATA118 |
| CELL9.OUT9.TMIN | PCIE3.MIREQUESTRAMWRITEDATA123 |
| CELL9.OUT10.TMIN | PCIE3.MIREQUESTRAMWRITEDATA119 |
| CELL9.OUT11.TMIN | PCIE3.MIREQUESTRAMWRITEDATA115 |
| CELL9.OUT12.TMIN | PCIE3.MIREQUESTRAMWRITEDATA110 |
| CELL9.OUT13.TMIN | PCIE3.MIREQUESTRAMWRITEDATA128 |
| CELL9.OUT14.TMIN | PCIE3.MIREQUESTRAMWRITEDATA114 |
| CELL9.OUT15.TMIN | PCIE3.MIREQUESTRAMWRITEDATA138 |
| CELL9.OUT16.TMIN | PCIE3.MAXISRCTDATA20 |
| CELL9.OUT17.TMIN | PCIE3.MAXISRCTDATA21 |
| CELL9.OUT18.TMIN | PCIE3.MAXISRCTDATA22 |
| CELL9.OUT19.TMIN | PCIE3.MAXISRCTDATA23 |
| CELL9.OUT20.TMIN | PCIE3.MAXISRCTUSER6 |
| CELL9.OUT21.TMIN | PCIE3.MAXISRCTUSER7 |
| CELL9.OUT22.TMIN | PCIE3.CFGINTERRUPTMSIVFENABLE1 |
| CELL9.OUT23.TMIN | PCIE3.XILUNCONNOUT26 |
| CELL10.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA84 |
| CELL10.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA85 |
| CELL10.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA86 |
| CELL10.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA87 |
| CELL10.IMUX.IMUX4.DELAY | PCIE3.MIREQUESTRAMREADDATA88 |
| CELL10.IMUX.IMUX5.DELAY | PCIE3.MIREQUESTRAMREADDATA89 |
| CELL10.IMUX.IMUX6.DELAY | PCIE3.MIREQUESTRAMREADDATA90 |
| CELL10.IMUX.IMUX7.DELAY | PCIE3.MIREQUESTRAMREADDATA91 |
| CELL10.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA40 |
| CELL10.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA41 |
| CELL10.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA42 |
| CELL10.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA43 |
| CELL10.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTUSER38 |
| CELL10.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTUSER39 |
| CELL10.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTUSER40 |
| CELL10.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTUSER41 |
| CELL10.IMUX.IMUX16.DELAY | PCIE3.CFGMGMTADDR10 |
| CELL10.IMUX.IMUX17.DELAY | PCIE3.CFGMGMTADDR11 |
| CELL10.IMUX.IMUX18.DELAY | PCIE3.CFGMGMTADDR12 |
| CELL10.IMUX.IMUX19.DELAY | PCIE3.CFGMGMTADDR13 |
| CELL10.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIINT29 |
| CELL10.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIINT30 |
| CELL10.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIINT31 |
| CELL10.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS0 |
| CELL10.OUT0.TMIN | PCIE3.MAXISRCTDATA24 |
| CELL10.OUT1.TMIN | PCIE3.MAXISRCTDATA25 |
| CELL10.OUT2.TMIN | PCIE3.MAXISRCTDATA26 |
| CELL10.OUT3.TMIN | PCIE3.MAXISRCTDATA27 |
| CELL10.OUT4.TMIN | PCIE3.MAXISRCTUSER8 |
| CELL10.OUT5.TMIN | PCIE3.MAXISRCTUSER9 |
| CELL10.OUT6.TMIN | PCIE3.MAXISRCTUSER10 |
| CELL10.OUT7.TMIN | PCIE3.MAXISRCTUSER11 |
| CELL10.OUT8.TMIN | PCIE3.MAXISRCTKEEP0 |
| CELL10.OUT9.TMIN | PCIE3.MAXISRCTKEEP1 |
| CELL10.OUT10.TMIN | PCIE3.MAXISRCTKEEP2 |
| CELL10.OUT11.TMIN | PCIE3.MAXISRCTKEEP3 |
| CELL10.OUT12.TMIN | PCIE3.MAXISRCTVALID |
| CELL10.OUT13.TMIN | PCIE3.SAXISRQTREADY0 |
| CELL10.OUT14.TMIN | PCIE3.SAXISRQTREADY1 |
| CELL10.OUT15.TMIN | PCIE3.SAXISRQTREADY2 |
| CELL10.OUT16.TMIN | PCIE3.CFGLINKPOWERSTATE0 |
| CELL10.OUT17.TMIN | PCIE3.CFGLINKPOWERSTATE1 |
| CELL10.OUT18.TMIN | PCIE3.CFGERRCOROUT |
| CELL10.OUT19.TMIN | PCIE3.CFGERRNONFATALOUT |
| CELL10.OUT20.TMIN | PCIE3.CFGERRFATALOUT |
| CELL10.OUT21.TMIN | PCIE3.CFGLOCALERROR |
| CELL10.OUT22.TMIN | PCIE3.CFGLTRENABLE |
| CELL10.OUT23.TMIN | PCIE3.CFGLTSSMSTATE0 |
| CELL11.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA92 |
| CELL11.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA93 |
| CELL11.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA94 |
| CELL11.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA95 |
| CELL11.IMUX.IMUX4.DELAY | PCIE3.MIREQUESTRAMREADDATA96 |
| CELL11.IMUX.IMUX5.DELAY | PCIE3.MIREQUESTRAMREADDATA97 |
| CELL11.IMUX.IMUX6.DELAY | PCIE3.MIREQUESTRAMREADDATA98 |
| CELL11.IMUX.IMUX7.DELAY | PCIE3.MIREQUESTRAMREADDATA99 |
| CELL11.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA44 |
| CELL11.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA45 |
| CELL11.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA46 |
| CELL11.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA47 |
| CELL11.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTUSER42 |
| CELL11.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTUSER43 |
| CELL11.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTUSER44 |
| CELL11.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTUSER45 |
| CELL11.IMUX.IMUX16.DELAY | PCIE3.CFGMGMTADDR14 |
| CELL11.IMUX.IMUX17.DELAY | PCIE3.CFGMGMTADDR15 |
| CELL11.IMUX.IMUX18.DELAY | PCIE3.CFGMGMTADDR16 |
| CELL11.IMUX.IMUX19.DELAY | PCIE3.CFGMGMTADDR17 |
| CELL11.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS1 |
| CELL11.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS2 |
| CELL11.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS3 |
| CELL11.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS4 |
| CELL11.OUT0.TMIN | PCIE3.MAXISRCTDATA28 |
| CELL11.OUT1.TMIN | PCIE3.MAXISRCTDATA29 |
| CELL11.OUT2.TMIN | PCIE3.MAXISRCTDATA30 |
| CELL11.OUT3.TMIN | PCIE3.MAXISRCTDATA31 |
| CELL11.OUT4.TMIN | PCIE3.MAXISRCTUSER12 |
| CELL11.OUT5.TMIN | PCIE3.MAXISRCTUSER13 |
| CELL11.OUT6.TMIN | PCIE3.MAXISRCTUSER14 |
| CELL11.OUT7.TMIN | PCIE3.MAXISRCTUSER15 |
| CELL11.OUT8.TMIN | PCIE3.MAXISRCTKEEP4 |
| CELL11.OUT9.TMIN | PCIE3.MAXISRCTKEEP5 |
| CELL11.OUT10.TMIN | PCIE3.MAXISRCTKEEP6 |
| CELL11.OUT11.TMIN | PCIE3.MAXISRCTKEEP7 |
| CELL11.OUT12.TMIN | PCIE3.CFGVFPOWERSTATE14 |
| CELL11.OUT13.TMIN | PCIE3.CFGVFPOWERSTATE15 |
| CELL11.OUT14.TMIN | PCIE3.CFGVFPOWERSTATE16 |
| CELL11.OUT15.TMIN | PCIE3.CFGVFPOWERSTATE17 |
| CELL11.OUT16.TMIN | PCIE3.CFGLTSSMSTATE1 |
| CELL11.OUT17.TMIN | PCIE3.CFGLTSSMSTATE2 |
| CELL11.OUT18.TMIN | PCIE3.CFGLTSSMSTATE3 |
| CELL11.OUT19.TMIN | PCIE3.CFGLTSSMSTATE4 |
| CELL11.OUT20.TMIN | PCIE3.CFGINTERRUPTMSIVFENABLE2 |
| CELL11.OUT21.TMIN | PCIE3.CFGINTERRUPTMSIVFENABLE3 |
| CELL11.OUT22.TMIN | PCIE3.CFGINTERRUPTMSIVFENABLE4 |
| CELL11.OUT23.TMIN | PCIE3.CFGINTERRUPTMSIVFENABLE5 |
| CELL12.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA100 |
| CELL12.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA101 |
| CELL12.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA102 |
| CELL12.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA103 |
| CELL12.IMUX.IMUX4.DELAY | PCIE3.MIREQUESTRAMREADDATA104 |
| CELL12.IMUX.IMUX5.DELAY | PCIE3.MIREQUESTRAMREADDATA105 |
| CELL12.IMUX.IMUX6.DELAY | PCIE3.MIREQUESTRAMREADDATA106 |
| CELL12.IMUX.IMUX7.DELAY | PCIE3.MIREQUESTRAMREADDATA107 |
| CELL12.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA48 |
| CELL12.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA49 |
| CELL12.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA50 |
| CELL12.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA51 |
| CELL12.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTUSER46 |
| CELL12.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTUSER47 |
| CELL12.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTUSER48 |
| CELL12.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTUSER49 |
| CELL12.IMUX.IMUX16.DELAY | PCIE3.CFGMGMTADDR18 |
| CELL12.IMUX.IMUX17.DELAY | PCIE3.CFGMGMTWRITE |
| CELL12.IMUX.IMUX18.DELAY | PCIE3.CFGMGMTWRITEDATA0 |
| CELL12.IMUX.IMUX19.DELAY | PCIE3.CFGMGMTWRITEDATA1 |
| CELL12.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS5 |
| CELL12.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS6 |
| CELL12.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS7 |
| CELL12.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS8 |
| CELL12.OUT0.TMIN | PCIE3.MAXISRCTDATA32 |
| CELL12.OUT1.TMIN | PCIE3.MAXISRCTDATA33 |
| CELL12.OUT2.TMIN | PCIE3.MAXISRCTDATA34 |
| CELL12.OUT3.TMIN | PCIE3.MAXISRCTDATA35 |
| CELL12.OUT4.TMIN | PCIE3.MAXISRCTUSER16 |
| CELL12.OUT5.TMIN | PCIE3.MAXISRCTUSER17 |
| CELL12.OUT6.TMIN | PCIE3.MAXISRCTUSER18 |
| CELL12.OUT7.TMIN | PCIE3.MAXISRCTUSER19 |
| CELL12.OUT8.TMIN | PCIE3.SAXISRQTREADY3 |
| CELL12.OUT9.TMIN | PCIE3.PCIERQSEQNUM0 |
| CELL12.OUT10.TMIN | PCIE3.PCIERQSEQNUM1 |
| CELL12.OUT11.TMIN | PCIE3.PCIERQSEQNUM2 |
| CELL12.OUT12.TMIN | PCIE3.CFGVFPOWERSTATE10 |
| CELL12.OUT13.TMIN | PCIE3.CFGVFPOWERSTATE11 |
| CELL12.OUT14.TMIN | PCIE3.CFGVFPOWERSTATE12 |
| CELL12.OUT15.TMIN | PCIE3.CFGVFPOWERSTATE13 |
| CELL12.OUT16.TMIN | PCIE3.CFGLTSSMSTATE5 |
| CELL12.OUT17.TMIN | PCIE3.CFGRCBSTATUS0 |
| CELL12.OUT18.TMIN | PCIE3.CFGRCBSTATUS1 |
| CELL12.OUT19.TMIN | PCIE3.CFGDPASUBSTATECHANGE0 |
| CELL12.OUT20.TMIN | PCIE3.CFGINTERRUPTMSISENT |
| CELL12.OUT21.TMIN | PCIE3.CFGINTERRUPTMSIFAIL |
| CELL12.OUT22.TMIN | PCIE3.CFGINTERRUPTMSIMMENABLE0 |
| CELL12.OUT23.TMIN | PCIE3.CFGINTERRUPTMSIMMENABLE1 |
| CELL13.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA108 |
| CELL13.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA109 |
| CELL13.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA110 |
| CELL13.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA111 |
| CELL13.IMUX.IMUX4.DELAY | PCIE3.MIREQUESTRAMREADDATA112 |
| CELL13.IMUX.IMUX5.DELAY | PCIE3.MIREQUESTRAMREADDATA113 |
| CELL13.IMUX.IMUX6.DELAY | PCIE3.MIREQUESTRAMREADDATA114 |
| CELL13.IMUX.IMUX7.DELAY | PCIE3.MIREQUESTRAMREADDATA115 |
| CELL13.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA52 |
| CELL13.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA53 |
| CELL13.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA54 |
| CELL13.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA55 |
| CELL13.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTUSER50 |
| CELL13.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTUSER51 |
| CELL13.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTUSER52 |
| CELL13.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTUSER53 |
| CELL13.IMUX.IMUX16.DELAY | PCIE3.CFGMGMTWRITEDATA2 |
| CELL13.IMUX.IMUX17.DELAY | PCIE3.CFGMGMTWRITEDATA3 |
| CELL13.IMUX.IMUX18.DELAY | PCIE3.CFGMGMTWRITEDATA4 |
| CELL13.IMUX.IMUX19.DELAY | PCIE3.CFGMGMTWRITEDATA5 |
| CELL13.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS9 |
| CELL13.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS10 |
| CELL13.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS11 |
| CELL13.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS12 |
| CELL13.OUT0.TMIN | PCIE3.MAXISRCTDATA36 |
| CELL13.OUT1.TMIN | PCIE3.MAXISRCTDATA37 |
| CELL13.OUT2.TMIN | PCIE3.MAXISRCTDATA38 |
| CELL13.OUT3.TMIN | PCIE3.MAXISRCTDATA39 |
| CELL13.OUT4.TMIN | PCIE3.MAXISRCTUSER20 |
| CELL13.OUT5.TMIN | PCIE3.MAXISRCTUSER21 |
| CELL13.OUT6.TMIN | PCIE3.MAXISRCTUSER22 |
| CELL13.OUT7.TMIN | PCIE3.MAXISRCTUSER23 |
| CELL13.OUT8.TMIN | PCIE3.PCIERQSEQNUM3 |
| CELL13.OUT9.TMIN | PCIE3.PCIERQSEQNUMVLD |
| CELL13.OUT10.TMIN | PCIE3.PCIERQTAG0 |
| CELL13.OUT11.TMIN | PCIE3.PCIERQTAG1 |
| CELL13.OUT12.TMIN | PCIE3.CFGVFPOWERSTATE6 |
| CELL13.OUT13.TMIN | PCIE3.CFGVFPOWERSTATE7 |
| CELL13.OUT14.TMIN | PCIE3.CFGVFPOWERSTATE8 |
| CELL13.OUT15.TMIN | PCIE3.CFGVFPOWERSTATE9 |
| CELL13.OUT16.TMIN | PCIE3.CFGDPASUBSTATECHANGE1 |
| CELL13.OUT17.TMIN | PCIE3.CFGOBFFENABLE0 |
| CELL13.OUT18.TMIN | PCIE3.CFGOBFFENABLE1 |
| CELL13.OUT19.TMIN | PCIE3.CFGPLSTATUSCHANGE |
| CELL13.OUT20.TMIN | PCIE3.CFGINTERRUPTMSIMMENABLE2 |
| CELL13.OUT21.TMIN | PCIE3.CFGINTERRUPTMSIMMENABLE3 |
| CELL13.OUT22.TMIN | PCIE3.CFGINTERRUPTMSIMMENABLE4 |
| CELL13.OUT23.TMIN | PCIE3.CFGINTERRUPTMSIMMENABLE5 |
| CELL14.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA116 |
| CELL14.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA117 |
| CELL14.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA118 |
| CELL14.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA119 |
| CELL14.IMUX.IMUX4.DELAY | PCIE3.MIREQUESTRAMREADDATA120 |
| CELL14.IMUX.IMUX5.DELAY | PCIE3.MIREQUESTRAMREADDATA121 |
| CELL14.IMUX.IMUX6.DELAY | PCIE3.MIREQUESTRAMREADDATA122 |
| CELL14.IMUX.IMUX7.DELAY | PCIE3.MIREQUESTRAMREADDATA123 |
| CELL14.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA56 |
| CELL14.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA57 |
| CELL14.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA58 |
| CELL14.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA59 |
| CELL14.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTUSER54 |
| CELL14.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTUSER55 |
| CELL14.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTUSER56 |
| CELL14.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTUSER57 |
| CELL14.IMUX.IMUX16.DELAY | PCIE3.CFGMGMTWRITEDATA6 |
| CELL14.IMUX.IMUX17.DELAY | PCIE3.CFGMGMTWRITEDATA7 |
| CELL14.IMUX.IMUX18.DELAY | PCIE3.CFGMGMTWRITEDATA8 |
| CELL14.IMUX.IMUX19.DELAY | PCIE3.CFGMGMTWRITEDATA9 |
| CELL14.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS13 |
| CELL14.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS14 |
| CELL14.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS15 |
| CELL14.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS16 |
| CELL14.OUT0.TMIN | PCIE3.MAXISRCTDATA40 |
| CELL14.OUT1.TMIN | PCIE3.MAXISRCTDATA41 |
| CELL14.OUT2.TMIN | PCIE3.MAXISRCTDATA42 |
| CELL14.OUT3.TMIN | PCIE3.MAXISRCTDATA43 |
| CELL14.OUT4.TMIN | PCIE3.MAXISRCTUSER24 |
| CELL14.OUT5.TMIN | PCIE3.MAXISRCTUSER25 |
| CELL14.OUT6.TMIN | PCIE3.MAXISRCTUSER26 |
| CELL14.OUT7.TMIN | PCIE3.MAXISRCTUSER27 |
| CELL14.OUT8.TMIN | PCIE3.PCIERQTAG2 |
| CELL14.OUT9.TMIN | PCIE3.PCIERQTAG3 |
| CELL14.OUT10.TMIN | PCIE3.PCIERQTAG4 |
| CELL14.OUT11.TMIN | PCIE3.PCIERQTAG5 |
| CELL14.OUT12.TMIN | PCIE3.CFGVFPOWERSTATE2 |
| CELL14.OUT13.TMIN | PCIE3.CFGVFPOWERSTATE3 |
| CELL14.OUT14.TMIN | PCIE3.CFGVFPOWERSTATE4 |
| CELL14.OUT15.TMIN | PCIE3.CFGVFPOWERSTATE5 |
| CELL14.OUT16.TMIN | PCIE3.CFGTPHREQUESTERENABLE0 |
| CELL14.OUT17.TMIN | PCIE3.CFGTPHREQUESTERENABLE1 |
| CELL14.OUT18.TMIN | PCIE3.CFGTPHSTMODE0 |
| CELL14.OUT19.TMIN | PCIE3.CFGTPHSTMODE1 |
| CELL14.OUT20.TMIN | PCIE3.CFGINTERRUPTMSIMASKUPDATE |
| CELL14.OUT21.TMIN | PCIE3.CFGINTERRUPTMSIDATA0 |
| CELL14.OUT22.TMIN | PCIE3.CFGINTERRUPTMSIDATA1 |
| CELL14.OUT23.TMIN | PCIE3.CFGINTERRUPTMSIDATA2 |
| CELL15.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA124 |
| CELL15.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA125 |
| CELL15.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA126 |
| CELL15.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA127 |
| CELL15.IMUX.IMUX4.DELAY | PCIE3.MIREQUESTRAMREADDATA128 |
| CELL15.IMUX.IMUX5.DELAY | PCIE3.MIREQUESTRAMREADDATA129 |
| CELL15.IMUX.IMUX6.DELAY | PCIE3.MIREQUESTRAMREADDATA130 |
| CELL15.IMUX.IMUX7.DELAY | PCIE3.MIREQUESTRAMREADDATA131 |
| CELL15.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA60 |
| CELL15.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA61 |
| CELL15.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA62 |
| CELL15.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA63 |
| CELL15.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTUSER58 |
| CELL15.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTUSER59 |
| CELL15.IMUX.IMUX14.DELAY | PCIE3.CFGMGMTWRITEDATA10 |
| CELL15.IMUX.IMUX15.DELAY | PCIE3.CFGMGMTWRITEDATA11 |
| CELL15.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS17 |
| CELL15.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS18 |
| CELL15.IMUX.IMUX18.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS19 |
| CELL15.IMUX.IMUX19.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS20 |
| CELL15.IMUX.IMUX20.DELAY | PCIE3.RESETN |
| CELL15.IMUX.IMUX21.DELAY | PCIE3.MGMTRESETN |
| CELL15.IMUX.IMUX22.DELAY | PCIE3.MGMTSTICKYRESETN |
| CELL15.IMUX.IMUX23.DELAY | PCIE3.PIPERESETN |
| CELL15.OUT0.TMIN | PCIE3.MAXISRCTDATA44 |
| CELL15.OUT1.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL9 |
| CELL15.OUT2.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL2 |
| CELL15.OUT3.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL11 |
| CELL15.OUT4.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL5 |
| CELL15.OUT5.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL1 |
| CELL15.OUT6.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL13 |
| CELL15.OUT7.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL3 |
| CELL15.OUT8.TMIN | PCIE3.MAXISRCTDATA45 |
| CELL15.OUT9.TMIN | PCIE3.MAXISRCTDATA46 |
| CELL15.OUT10.TMIN | PCIE3.MAXISRCTDATA47 |
| CELL15.OUT11.TMIN | PCIE3.MAXISRCTUSER28 |
| CELL15.OUT12.TMIN | PCIE3.MAXISRCTUSER29 |
| CELL15.OUT13.TMIN | PCIE3.MAXISRCTUSER30 |
| CELL15.OUT14.TMIN | PCIE3.MAXISRCTUSER31 |
| CELL15.OUT15.TMIN | PCIE3.PCIERQTAGVLD |
| CELL15.OUT16.TMIN | PCIE3.PCIETFCNPHAV0 |
| CELL15.OUT17.TMIN | PCIE3.PCIETFCNPHAV1 |
| CELL15.OUT18.TMIN | PCIE3.PCIETFCNPDAV0 |
| CELL15.OUT19.TMIN | PCIE3.CFGFUNCTIONPOWERSTATE5 |
| CELL15.OUT20.TMIN | PCIE3.CFGVFPOWERSTATE0 |
| CELL15.OUT21.TMIN | PCIE3.CFGVFPOWERSTATE1 |
| CELL15.OUT22.TMIN | PCIE3.CFGINTERRUPTMSIDATA3 |
| CELL15.OUT23.TMIN | PCIE3.CFGTPHSTMODE2 |
| CELL16.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA132 |
| CELL16.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA133 |
| CELL16.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA134 |
| CELL16.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA135 |
| CELL16.IMUX.IMUX4.DELAY | PCIE3.MIREQUESTRAMREADDATA136 |
| CELL16.IMUX.IMUX5.DELAY | PCIE3.MIREQUESTRAMREADDATA137 |
| CELL16.IMUX.IMUX6.DELAY | PCIE3.MIREQUESTRAMREADDATA138 |
| CELL16.IMUX.IMUX7.DELAY | PCIE3.MIREQUESTRAMREADDATA139 |
| CELL16.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA64 |
| CELL16.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA65 |
| CELL16.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA66 |
| CELL16.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA67 |
| CELL16.IMUX.IMUX12.DELAY | PCIE3.CFGMGMTWRITEDATA12 |
| CELL16.IMUX.IMUX13.DELAY | PCIE3.CFGMGMTWRITEDATA13 |
| CELL16.IMUX.IMUX14.DELAY | PCIE3.CFGMGMTWRITEDATA14 |
| CELL16.IMUX.IMUX15.DELAY | PCIE3.CFGMGMTWRITEDATA15 |
| CELL16.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS21 |
| CELL16.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS22 |
| CELL16.IMUX.IMUX18.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS23 |
| CELL16.IMUX.IMUX19.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS24 |
| CELL16.OUT0.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL0 |
| CELL16.OUT1.TMIN | PCIE3.MAXISRCTDATA48 |
| CELL16.OUT2.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAL4 |
| CELL16.OUT3.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAL5 |
| CELL16.OUT4.TMIN | PCIE3.MAXISRCTDATA49 |
| CELL16.OUT5.TMIN | PCIE3.MAXISRCTDATA50 |
| CELL16.OUT6.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAL0 |
| CELL16.OUT7.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAL5 |
| CELL16.OUT8.TMIN | PCIE3.MAXISRCTDATA51 |
| CELL16.OUT9.TMIN | PCIE3.MAXISRCTUSER32 |
| CELL16.OUT10.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAL4 |
| CELL16.OUT11.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAL7 |
| CELL16.OUT12.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL18 |
| CELL16.OUT13.TMIN | PCIE3.CFGTPHSTMODE3 |
| CELL16.OUT14.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAL0 |
| CELL16.OUT15.TMIN | PCIE3.CFGTPHSTMODE4 |
| CELL16.OUT16.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL6 |
| CELL16.OUT17.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL14 |
| CELL16.OUT18.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL4 |
| CELL16.OUT19.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL12 |
| CELL16.OUT20.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL10 |
| CELL16.OUT21.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAL9 |
| CELL16.OUT22.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL17 |
| CELL16.OUT23.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL8 |
| CELL17.IMUX.IMUX0.DELAY | PCIE3.MIREQUESTRAMREADDATA140 |
| CELL17.IMUX.IMUX1.DELAY | PCIE3.MIREQUESTRAMREADDATA141 |
| CELL17.IMUX.IMUX2.DELAY | PCIE3.MIREQUESTRAMREADDATA142 |
| CELL17.IMUX.IMUX3.DELAY | PCIE3.MIREQUESTRAMREADDATA143 |
| CELL17.IMUX.IMUX4.DELAY | PCIE3.SAXISRQTDATA68 |
| CELL17.IMUX.IMUX5.DELAY | PCIE3.SAXISRQTDATA69 |
| CELL17.IMUX.IMUX6.DELAY | PCIE3.SAXISRQTDATA70 |
| CELL17.IMUX.IMUX7.DELAY | PCIE3.SAXISRQTDATA71 |
| CELL17.IMUX.IMUX8.DELAY | PCIE3.CFGMGMTWRITEDATA16 |
| CELL17.IMUX.IMUX9.DELAY | PCIE3.CFGMGMTWRITEDATA17 |
| CELL17.IMUX.IMUX10.DELAY | PCIE3.CFGMGMTWRITEDATA18 |
| CELL17.IMUX.IMUX11.DELAY | PCIE3.CFGMGMTWRITEDATA19 |
| CELL17.IMUX.IMUX12.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS25 |
| CELL17.IMUX.IMUX13.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS26 |
| CELL17.IMUX.IMUX14.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS27 |
| CELL17.IMUX.IMUX15.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS28 |
| CELL17.OUT0.TMIN | PCIE3.MICOMPLETIONRAMREADENABLEL0 |
| CELL17.OUT1.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL16 |
| CELL17.OUT2.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAL6 |
| CELL17.OUT3.TMIN | PCIE3.MAXISRCTDATA52 |
| CELL17.OUT4.TMIN | PCIE3.MICOMPLETIONRAMREADENABLEL1 |
| CELL17.OUT5.TMIN | PCIE3.MAXISRCTDATA53 |
| CELL17.OUT6.TMIN | PCIE3.MICOMPLETIONRAMWRITEENABLEL0 |
| CELL17.OUT7.TMIN | PCIE3.MICOMPLETIONRAMWRITEENABLEL1 |
| CELL17.OUT8.TMIN | PCIE3.MAXISRCTDATA54 |
| CELL17.OUT9.TMIN | PCIE3.MAXISRCTDATA55 |
| CELL17.OUT10.TMIN | PCIE3.MAXISRCTUSER33 |
| CELL17.OUT11.TMIN | PCIE3.MAXISRCTUSER34 |
| CELL17.OUT12.TMIN | PCIE3.MAXISRCTUSER35 |
| CELL17.OUT13.TMIN | PCIE3.MAXISRCTUSER36 |
| CELL17.OUT14.TMIN | PCIE3.PCIETFCNPDAV1 |
| CELL17.OUT15.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL26 |
| CELL17.OUT16.TMIN | PCIE3.PCIERQTAGAV0 |
| CELL17.OUT17.TMIN | PCIE3.PCIERQTAGAV1 |
| CELL17.OUT18.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL15 |
| CELL17.OUT19.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL34 |
| CELL17.OUT20.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAL6 |
| CELL17.OUT21.TMIN | PCIE3.CFGTPHSTMODE5 |
| CELL17.OUT22.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL7 |
| CELL17.OUT23.TMIN | PCIE3.CFGVFTPHREQUESTERENABLE0 |
| CELL18.IMUX.CLK0 | PCIE3.CORECLKMICOMPLETIONRAML |
| CELL18.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA0 |
| CELL18.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA1 |
| CELL18.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA2 |
| CELL18.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA3 |
| CELL18.IMUX.IMUX4.DELAY | PCIE3.SAXISRQTDATA72 |
| CELL18.IMUX.IMUX5.DELAY | PCIE3.SAXISRQTDATA73 |
| CELL18.IMUX.IMUX6.DELAY | PCIE3.SAXISRQTDATA74 |
| CELL18.IMUX.IMUX7.DELAY | PCIE3.SAXISRQTDATA75 |
| CELL18.IMUX.IMUX8.DELAY | PCIE3.CFGMGMTWRITEDATA20 |
| CELL18.IMUX.IMUX9.DELAY | PCIE3.CFGMGMTWRITEDATA21 |
| CELL18.IMUX.IMUX10.DELAY | PCIE3.CFGMGMTWRITEDATA22 |
| CELL18.IMUX.IMUX11.DELAY | PCIE3.CFGMGMTWRITEDATA23 |
| CELL18.IMUX.IMUX12.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS29 |
| CELL18.IMUX.IMUX13.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS30 |
| CELL18.IMUX.IMUX14.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS31 |
| CELL18.IMUX.IMUX15.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS32 |
| CELL18.OUT0.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAL2 |
| CELL18.OUT1.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAL7 |
| CELL18.OUT2.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAL1 |
| CELL18.OUT3.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL35 |
| CELL18.OUT4.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAL3 |
| CELL18.OUT5.TMIN | PCIE3.MAXISRCTDATA56 |
| CELL18.OUT6.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAL8 |
| CELL18.OUT7.TMIN | PCIE3.MAXISRCTDATA57 |
| CELL18.OUT8.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAL3 |
| CELL18.OUT9.TMIN | PCIE3.MAXISRCTDATA58 |
| CELL18.OUT10.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAL8 |
| CELL18.OUT11.TMIN | PCIE3.MAXISRCTDATA59 |
| CELL18.OUT12.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAL2 |
| CELL18.OUT13.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAL9 |
| CELL18.OUT14.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAL1 |
| CELL18.OUT15.TMIN | PCIE3.MAXISRCTUSER37 |
| CELL18.OUT16.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL29 |
| CELL18.OUT17.TMIN | PCIE3.CFGVFTPHREQUESTERENABLE1 |
| CELL18.OUT18.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL27 |
| CELL18.OUT19.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL20 |
| CELL18.OUT20.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL21 |
| CELL18.OUT21.TMIN | PCIE3.CFGVFTPHREQUESTERENABLE2 |
| CELL18.OUT22.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL19 |
| CELL18.OUT23.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL28 |
| CELL19.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA4 |
| CELL19.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA5 |
| CELL19.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA6 |
| CELL19.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA7 |
| CELL19.IMUX.IMUX4.DELAY | PCIE3.SAXISRQTDATA76 |
| CELL19.IMUX.IMUX5.DELAY | PCIE3.SAXISRQTDATA77 |
| CELL19.IMUX.IMUX6.DELAY | PCIE3.SAXISRQTDATA78 |
| CELL19.IMUX.IMUX7.DELAY | PCIE3.SAXISRQTDATA79 |
| CELL19.IMUX.IMUX8.DELAY | PCIE3.CFGMGMTWRITEDATA24 |
| CELL19.IMUX.IMUX9.DELAY | PCIE3.CFGMGMTWRITEDATA25 |
| CELL19.IMUX.IMUX10.DELAY | PCIE3.CFGMGMTWRITEDATA26 |
| CELL19.IMUX.IMUX11.DELAY | PCIE3.CFGMGMTWRITEDATA27 |
| CELL19.IMUX.IMUX12.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS33 |
| CELL19.IMUX.IMUX13.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS34 |
| CELL19.IMUX.IMUX14.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS35 |
| CELL19.IMUX.IMUX15.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS36 |
| CELL19.OUT0.TMIN | PCIE3.MAXISRCTDATA60 |
| CELL19.OUT1.TMIN | PCIE3.MAXISRCTDATA61 |
| CELL19.OUT2.TMIN | PCIE3.MAXISRCTDATA62 |
| CELL19.OUT3.TMIN | PCIE3.MAXISRCTDATA63 |
| CELL19.OUT4.TMIN | PCIE3.MAXISRCTUSER38 |
| CELL19.OUT5.TMIN | PCIE3.MAXISRCTUSER39 |
| CELL19.OUT6.TMIN | PCIE3.MAXISRCTUSER40 |
| CELL19.OUT7.TMIN | PCIE3.MAXISRCTUSER41 |
| CELL19.OUT8.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL30 |
| CELL19.OUT9.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL23 |
| CELL19.OUT10.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL32 |
| CELL19.OUT11.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL25 |
| CELL19.OUT12.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL22 |
| CELL19.OUT13.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL31 |
| CELL19.OUT14.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL24 |
| CELL19.OUT15.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL33 |
| CELL19.OUT16.TMIN | PCIE3.CFGMGMTREADDATA0 |
| CELL19.OUT17.TMIN | PCIE3.CFGMGMTREADDATA1 |
| CELL19.OUT18.TMIN | PCIE3.CFGMGMTREADDATA2 |
| CELL19.OUT19.TMIN | PCIE3.CFGMGMTREADDATA3 |
| CELL19.OUT20.TMIN | PCIE3.CFGFUNCTIONPOWERSTATE3 |
| CELL19.OUT21.TMIN | PCIE3.CFGFUNCTIONPOWERSTATE4 |
| CELL19.OUT22.TMIN | PCIE3.CFGINTERRUPTMSIDATA4 |
| CELL19.OUT23.TMIN | PCIE3.CFGVFTPHREQUESTERENABLE3 |
| CELL20.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA8 |
| CELL20.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA9 |
| CELL20.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA10 |
| CELL20.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA11 |
| CELL20.IMUX.IMUX4.DELAY | PCIE3.SAXISRQTDATA80 |
| CELL20.IMUX.IMUX5.DELAY | PCIE3.SAXISRQTDATA81 |
| CELL20.IMUX.IMUX6.DELAY | PCIE3.SAXISRQTDATA82 |
| CELL20.IMUX.IMUX7.DELAY | PCIE3.SAXISRQTDATA83 |
| CELL20.IMUX.IMUX8.DELAY | PCIE3.CFGMGMTWRITEDATA28 |
| CELL20.IMUX.IMUX9.DELAY | PCIE3.CFGMGMTWRITEDATA29 |
| CELL20.IMUX.IMUX10.DELAY | PCIE3.CFGMGMTWRITEDATA30 |
| CELL20.IMUX.IMUX11.DELAY | PCIE3.CFGMGMTWRITEDATA31 |
| CELL20.IMUX.IMUX12.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS37 |
| CELL20.IMUX.IMUX13.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS38 |
| CELL20.IMUX.IMUX14.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS39 |
| CELL20.IMUX.IMUX15.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS40 |
| CELL20.OUT0.TMIN | PCIE3.MAXISRCTDATA64 |
| CELL20.OUT1.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL45 |
| CELL20.OUT2.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL38 |
| CELL20.OUT3.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL47 |
| CELL20.OUT4.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL43 |
| CELL20.OUT5.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL37 |
| CELL20.OUT6.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL46 |
| CELL20.OUT7.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL39 |
| CELL20.OUT8.TMIN | PCIE3.MAXISRCTDATA65 |
| CELL20.OUT9.TMIN | PCIE3.MAXISRCTDATA66 |
| CELL20.OUT10.TMIN | PCIE3.MAXISRCTDATA67 |
| CELL20.OUT11.TMIN | PCIE3.MAXISRCTUSER42 |
| CELL20.OUT12.TMIN | PCIE3.MAXISRCTUSER43 |
| CELL20.OUT13.TMIN | PCIE3.MAXISRCTUSER44 |
| CELL20.OUT14.TMIN | PCIE3.MAXISRCTUSER45 |
| CELL20.OUT15.TMIN | PCIE3.CFGMGMTREADDATA4 |
| CELL20.OUT16.TMIN | PCIE3.CFGMGMTREADDATA5 |
| CELL20.OUT17.TMIN | PCIE3.CFGMGMTREADDATA6 |
| CELL20.OUT18.TMIN | PCIE3.CFGMGMTREADDATA7 |
| CELL20.OUT19.TMIN | PCIE3.CFGFUNCTIONPOWERSTATE0 |
| CELL20.OUT20.TMIN | PCIE3.CFGFUNCTIONPOWERSTATE1 |
| CELL20.OUT21.TMIN | PCIE3.CFGFUNCTIONPOWERSTATE2 |
| CELL20.OUT22.TMIN | PCIE3.CFGINTERRUPTMSIDATA5 |
| CELL20.OUT23.TMIN | PCIE3.CFGVFTPHREQUESTERENABLE4 |
| CELL21.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA12 |
| CELL21.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA13 |
| CELL21.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA14 |
| CELL21.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA15 |
| CELL21.IMUX.IMUX4.DELAY | PCIE3.MICOMPLETIONRAMREADDATA16 |
| CELL21.IMUX.IMUX5.DELAY | PCIE3.MICOMPLETIONRAMREADDATA17 |
| CELL21.IMUX.IMUX6.DELAY | PCIE3.MICOMPLETIONRAMREADDATA18 |
| CELL21.IMUX.IMUX7.DELAY | PCIE3.MICOMPLETIONRAMREADDATA19 |
| CELL21.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA84 |
| CELL21.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA85 |
| CELL21.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA86 |
| CELL21.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA87 |
| CELL21.IMUX.IMUX12.DELAY | PCIE3.CFGMGMTBYTEENABLE0 |
| CELL21.IMUX.IMUX13.DELAY | PCIE3.CFGMGMTBYTEENABLE1 |
| CELL21.IMUX.IMUX14.DELAY | PCIE3.CFGMGMTBYTEENABLE2 |
| CELL21.IMUX.IMUX15.DELAY | PCIE3.CFGMGMTBYTEENABLE3 |
| CELL21.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS41 |
| CELL21.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS42 |
| CELL21.IMUX.IMUX18.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS43 |
| CELL21.IMUX.IMUX19.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS44 |
| CELL21.OUT0.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL36 |
| CELL21.OUT1.TMIN | PCIE3.MAXISRCTDATA68 |
| CELL21.OUT2.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBL4 |
| CELL21.OUT3.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBL9 |
| CELL21.OUT4.TMIN | PCIE3.MAXISRCTDATA69 |
| CELL21.OUT5.TMIN | PCIE3.MAXISRCTDATA70 |
| CELL21.OUT6.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBL0 |
| CELL21.OUT7.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBL7 |
| CELL21.OUT8.TMIN | PCIE3.MAXISRCTDATA71 |
| CELL21.OUT9.TMIN | PCIE3.MAXISRCTUSER46 |
| CELL21.OUT10.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBL2 |
| CELL21.OUT11.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBL7 |
| CELL21.OUT12.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL54 |
| CELL21.OUT13.TMIN | PCIE3.CFGVFTPHREQUESTERENABLE5 |
| CELL21.OUT14.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBL4 |
| CELL21.OUT15.TMIN | PCIE3.CFGVFTPHSTMODE0 |
| CELL21.OUT16.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL42 |
| CELL21.OUT17.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL50 |
| CELL21.OUT18.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL40 |
| CELL21.OUT19.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL48 |
| CELL21.OUT20.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL49 |
| CELL21.OUT21.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBL9 |
| CELL21.OUT22.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL53 |
| CELL21.OUT23.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL41 |
| CELL22.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA20 |
| CELL22.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA21 |
| CELL22.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA22 |
| CELL22.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA23 |
| CELL22.IMUX.IMUX4.DELAY | PCIE3.MICOMPLETIONRAMREADDATA24 |
| CELL22.IMUX.IMUX5.DELAY | PCIE3.MICOMPLETIONRAMREADDATA25 |
| CELL22.IMUX.IMUX6.DELAY | PCIE3.MICOMPLETIONRAMREADDATA26 |
| CELL22.IMUX.IMUX7.DELAY | PCIE3.MICOMPLETIONRAMREADDATA27 |
| CELL22.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA88 |
| CELL22.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA89 |
| CELL22.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA90 |
| CELL22.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA91 |
| CELL22.IMUX.IMUX12.DELAY | PCIE3.CFGMGMTREAD |
| CELL22.IMUX.IMUX13.DELAY | PCIE3.CFGMGMTTYPE1CFGREGACCESS |
| CELL22.IMUX.IMUX14.DELAY | PCIE3.CFGMSGTRANSMIT |
| CELL22.IMUX.IMUX15.DELAY | PCIE3.CFGMSGTRANSMITTYPE0 |
| CELL22.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS45 |
| CELL22.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS46 |
| CELL22.IMUX.IMUX18.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS47 |
| CELL22.IMUX.IMUX19.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS48 |
| CELL22.OUT0.TMIN | PCIE3.MICOMPLETIONRAMREADENABLEL2 |
| CELL22.OUT1.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL52 |
| CELL22.OUT2.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBL6 |
| CELL22.OUT3.TMIN | PCIE3.MAXISRCTDATA72 |
| CELL22.OUT4.TMIN | PCIE3.MICOMPLETIONRAMREADENABLEL3 |
| CELL22.OUT5.TMIN | PCIE3.MAXISRCTDATA73 |
| CELL22.OUT6.TMIN | PCIE3.MICOMPLETIONRAMWRITEENABLEL2 |
| CELL22.OUT7.TMIN | PCIE3.MICOMPLETIONRAMWRITEENABLEL3 |
| CELL22.OUT8.TMIN | PCIE3.MAXISRCTDATA74 |
| CELL22.OUT9.TMIN | PCIE3.MAXISRCTDATA75 |
| CELL22.OUT10.TMIN | PCIE3.MAXISRCTUSER47 |
| CELL22.OUT11.TMIN | PCIE3.MAXISRCTUSER48 |
| CELL22.OUT12.TMIN | PCIE3.MAXISRCTUSER49 |
| CELL22.OUT13.TMIN | PCIE3.MAXISRCTUSER50 |
| CELL22.OUT14.TMIN | PCIE3.CFGMGMTREADDATA8 |
| CELL22.OUT15.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL62 |
| CELL22.OUT16.TMIN | PCIE3.CFGMGMTREADDATA9 |
| CELL22.OUT17.TMIN | PCIE3.CFGMGMTREADDATA10 |
| CELL22.OUT18.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL51 |
| CELL22.OUT19.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL70 |
| CELL22.OUT20.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBL6 |
| CELL22.OUT21.TMIN | PCIE3.CFGVFTPHSTMODE1 |
| CELL22.OUT22.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL44 |
| CELL22.OUT23.TMIN | PCIE3.CFGVFTPHSTMODE2 |
| CELL23.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA28 |
| CELL23.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA29 |
| CELL23.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA30 |
| CELL23.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA31 |
| CELL23.IMUX.IMUX4.DELAY | PCIE3.MICOMPLETIONRAMREADDATA32 |
| CELL23.IMUX.IMUX5.DELAY | PCIE3.MICOMPLETIONRAMREADDATA33 |
| CELL23.IMUX.IMUX6.DELAY | PCIE3.MICOMPLETIONRAMREADDATA34 |
| CELL23.IMUX.IMUX7.DELAY | PCIE3.MICOMPLETIONRAMREADDATA35 |
| CELL23.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA92 |
| CELL23.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA93 |
| CELL23.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA94 |
| CELL23.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA95 |
| CELL23.IMUX.IMUX12.DELAY | PCIE3.CFGMSGTRANSMITTYPE1 |
| CELL23.IMUX.IMUX13.DELAY | PCIE3.CFGMSGTRANSMITTYPE2 |
| CELL23.IMUX.IMUX14.DELAY | PCIE3.CFGMSGTRANSMITDATA0 |
| CELL23.IMUX.IMUX15.DELAY | PCIE3.CFGMSGTRANSMITDATA1 |
| CELL23.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS49 |
| CELL23.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS50 |
| CELL23.IMUX.IMUX18.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS51 |
| CELL23.IMUX.IMUX19.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS52 |
| CELL23.OUT0.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBL1 |
| CELL23.OUT1.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBL5 |
| CELL23.OUT2.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBL2 |
| CELL23.OUT3.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL71 |
| CELL23.OUT4.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBL3 |
| CELL23.OUT5.TMIN | PCIE3.MAXISRCTDATA76 |
| CELL23.OUT6.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBL8 |
| CELL23.OUT7.TMIN | PCIE3.MAXISRCTDATA77 |
| CELL23.OUT8.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBL3 |
| CELL23.OUT9.TMIN | PCIE3.MAXISRCTDATA78 |
| CELL23.OUT10.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBL8 |
| CELL23.OUT11.TMIN | PCIE3.MAXISRCTDATA79 |
| CELL23.OUT12.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBL0 |
| CELL23.OUT13.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBL5 |
| CELL23.OUT14.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBL1 |
| CELL23.OUT15.TMIN | PCIE3.MAXISRCTDATA255 |
| CELL23.OUT16.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL65 |
| CELL23.OUT17.TMIN | PCIE3.CFGVFTPHSTMODE3 |
| CELL23.OUT18.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL63 |
| CELL23.OUT19.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL56 |
| CELL23.OUT20.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL57 |
| CELL23.OUT21.TMIN | PCIE3.CFGVFTPHSTMODE4 |
| CELL23.OUT22.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL55 |
| CELL23.OUT23.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL64 |
| CELL24.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA36 |
| CELL24.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA37 |
| CELL24.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA38 |
| CELL24.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA39 |
| CELL24.IMUX.IMUX4.DELAY | PCIE3.MICOMPLETIONRAMREADDATA40 |
| CELL24.IMUX.IMUX5.DELAY | PCIE3.MICOMPLETIONRAMREADDATA41 |
| CELL24.IMUX.IMUX6.DELAY | PCIE3.MICOMPLETIONRAMREADDATA42 |
| CELL24.IMUX.IMUX7.DELAY | PCIE3.MICOMPLETIONRAMREADDATA43 |
| CELL24.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA96 |
| CELL24.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA97 |
| CELL24.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA98 |
| CELL24.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA99 |
| CELL24.IMUX.IMUX12.DELAY | PCIE3.CFGMSGTRANSMITDATA2 |
| CELL24.IMUX.IMUX13.DELAY | PCIE3.CFGMSGTRANSMITDATA3 |
| CELL24.IMUX.IMUX14.DELAY | PCIE3.CFGMSGTRANSMITDATA4 |
| CELL24.IMUX.IMUX15.DELAY | PCIE3.CFGMSGTRANSMITDATA5 |
| CELL24.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS53 |
| CELL24.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS54 |
| CELL24.IMUX.IMUX18.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS55 |
| CELL24.IMUX.IMUX19.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS56 |
| CELL24.OUT0.TMIN | PCIE3.MAXISRCTDATA80 |
| CELL24.OUT1.TMIN | PCIE3.MAXISRCTDATA81 |
| CELL24.OUT2.TMIN | PCIE3.MAXISRCTDATA82 |
| CELL24.OUT3.TMIN | PCIE3.MAXISRCTDATA83 |
| CELL24.OUT4.TMIN | PCIE3.MAXISRCTDATA251 |
| CELL24.OUT5.TMIN | PCIE3.MAXISRCTDATA252 |
| CELL24.OUT6.TMIN | PCIE3.MAXISRCTDATA253 |
| CELL24.OUT7.TMIN | PCIE3.MAXISRCTDATA254 |
| CELL24.OUT8.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL66 |
| CELL24.OUT9.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL59 |
| CELL24.OUT10.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL68 |
| CELL24.OUT11.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL61 |
| CELL24.OUT12.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL58 |
| CELL24.OUT13.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL67 |
| CELL24.OUT14.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL60 |
| CELL24.OUT15.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAL69 |
| CELL24.OUT16.TMIN | PCIE3.MAXISRCTUSER51 |
| CELL24.OUT17.TMIN | PCIE3.MAXISRCTUSER52 |
| CELL24.OUT18.TMIN | PCIE3.MAXISRCTUSER53 |
| CELL24.OUT19.TMIN | PCIE3.MAXISRCTUSER54 |
| CELL24.OUT20.TMIN | PCIE3.CFGMGMTREADDATA11 |
| CELL24.OUT21.TMIN | PCIE3.CFGMGMTREADDATA12 |
| CELL24.OUT22.TMIN | PCIE3.CFGVFTPHSTMODE5 |
| CELL24.OUT23.TMIN | PCIE3.CFGVFTPHSTMODE6 |
| CELL25.IMUX.CLK0 | PCIE3.USERCLK |
| CELL25.IMUX.CLK1 | PCIE3.CORECLK |
| CELL25.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA44 |
| CELL25.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA45 |
| CELL25.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA46 |
| CELL25.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA47 |
| CELL25.IMUX.IMUX4.DELAY | PCIE3.MICOMPLETIONRAMREADDATA48 |
| CELL25.IMUX.IMUX5.DELAY | PCIE3.MICOMPLETIONRAMREADDATA49 |
| CELL25.IMUX.IMUX6.DELAY | PCIE3.MICOMPLETIONRAMREADDATA50 |
| CELL25.IMUX.IMUX7.DELAY | PCIE3.MICOMPLETIONRAMREADDATA51 |
| CELL25.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA100 |
| CELL25.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA101 |
| CELL25.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA102 |
| CELL25.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA103 |
| CELL25.IMUX.IMUX12.DELAY | PCIE3.CFGMSGTRANSMITDATA6 |
| CELL25.IMUX.IMUX13.DELAY | PCIE3.CFGMSGTRANSMITDATA7 |
| CELL25.IMUX.IMUX14.DELAY | PCIE3.CFGMSGTRANSMITDATA8 |
| CELL25.IMUX.IMUX15.DELAY | PCIE3.CFGMSGTRANSMITDATA9 |
| CELL25.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS57 |
| CELL25.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS58 |
| CELL25.IMUX.IMUX18.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS59 |
| CELL25.IMUX.IMUX19.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS60 |
| CELL25.OUT0.TMIN | PCIE3.MAXISRCTDATA84 |
| CELL25.OUT1.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU9 |
| CELL25.OUT2.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU2 |
| CELL25.OUT3.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU11 |
| CELL25.OUT4.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU8 |
| CELL25.OUT5.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU1 |
| CELL25.OUT6.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU10 |
| CELL25.OUT7.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU3 |
| CELL25.OUT8.TMIN | PCIE3.MAXISRCTDATA85 |
| CELL25.OUT9.TMIN | PCIE3.MAXISRCTDATA86 |
| CELL25.OUT10.TMIN | PCIE3.MAXISRCTDATA87 |
| CELL25.OUT11.TMIN | PCIE3.MAXISRCTDATA247 |
| CELL25.OUT12.TMIN | PCIE3.MAXISRCTDATA248 |
| CELL25.OUT13.TMIN | PCIE3.MAXISRCTDATA249 |
| CELL25.OUT14.TMIN | PCIE3.MAXISRCTDATA250 |
| CELL25.OUT15.TMIN | PCIE3.MAXISRCTUSER55 |
| CELL25.OUT16.TMIN | PCIE3.MAXISRCTUSER56 |
| CELL25.OUT17.TMIN | PCIE3.MAXISRCTUSER57 |
| CELL25.OUT18.TMIN | PCIE3.MAXISRCTUSER58 |
| CELL25.OUT19.TMIN | PCIE3.CFGMGMTREADDATA13 |
| CELL25.OUT20.TMIN | PCIE3.CFGMGMTREADDATA14 |
| CELL25.OUT21.TMIN | PCIE3.CFGMGMTREADDATA15 |
| CELL25.OUT22.TMIN | PCIE3.CFGVFTPHSTMODE7 |
| CELL25.OUT23.TMIN | PCIE3.CFGVFTPHSTMODE8 |
| CELL26.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA52 |
| CELL26.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA53 |
| CELL26.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA54 |
| CELL26.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA55 |
| CELL26.IMUX.IMUX4.DELAY | PCIE3.MICOMPLETIONRAMREADDATA56 |
| CELL26.IMUX.IMUX5.DELAY | PCIE3.MICOMPLETIONRAMREADDATA57 |
| CELL26.IMUX.IMUX6.DELAY | PCIE3.MICOMPLETIONRAMREADDATA58 |
| CELL26.IMUX.IMUX7.DELAY | PCIE3.MICOMPLETIONRAMREADDATA59 |
| CELL26.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA104 |
| CELL26.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA105 |
| CELL26.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA106 |
| CELL26.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA107 |
| CELL26.IMUX.IMUX12.DELAY | PCIE3.CFGMSGTRANSMITDATA10 |
| CELL26.IMUX.IMUX13.DELAY | PCIE3.CFGMSGTRANSMITDATA11 |
| CELL26.IMUX.IMUX14.DELAY | PCIE3.CFGMSGTRANSMITDATA12 |
| CELL26.IMUX.IMUX15.DELAY | PCIE3.CFGMSGTRANSMITDATA13 |
| CELL26.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS61 |
| CELL26.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS62 |
| CELL26.IMUX.IMUX18.DELAY | PCIE3.CFGINTERRUPTMSIPENDINGSTATUS63 |
| CELL26.IMUX.IMUX19.DELAY | PCIE3.CFGINTERRUPTMSISELECT0 |
| CELL26.OUT0.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU0 |
| CELL26.OUT1.TMIN | PCIE3.MAXISRCTDATA88 |
| CELL26.OUT2.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAU4 |
| CELL26.OUT3.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAU9 |
| CELL26.OUT4.TMIN | PCIE3.MAXISRCTDATA89 |
| CELL26.OUT5.TMIN | PCIE3.MAXISRCTDATA90 |
| CELL26.OUT6.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAU0 |
| CELL26.OUT7.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAU7 |
| CELL26.OUT8.TMIN | PCIE3.MAXISRCTDATA91 |
| CELL26.OUT9.TMIN | PCIE3.MAXISRCTDATA246 |
| CELL26.OUT10.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAU4 |
| CELL26.OUT11.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAU7 |
| CELL26.OUT12.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU18 |
| CELL26.OUT13.TMIN | PCIE3.CFGVFTPHSTMODE9 |
| CELL26.OUT14.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAU0 |
| CELL26.OUT15.TMIN | PCIE3.CFGVFTPHSTMODE10 |
| CELL26.OUT16.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU6 |
| CELL26.OUT17.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU14 |
| CELL26.OUT18.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU4 |
| CELL26.OUT19.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU12 |
| CELL26.OUT20.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU13 |
| CELL26.OUT21.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAU9 |
| CELL26.OUT22.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU17 |
| CELL26.OUT23.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU5 |
| CELL27.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA60 |
| CELL27.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA61 |
| CELL27.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA62 |
| CELL27.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA63 |
| CELL27.IMUX.IMUX4.DELAY | PCIE3.MICOMPLETIONRAMREADDATA64 |
| CELL27.IMUX.IMUX5.DELAY | PCIE3.MICOMPLETIONRAMREADDATA65 |
| CELL27.IMUX.IMUX6.DELAY | PCIE3.MICOMPLETIONRAMREADDATA66 |
| CELL27.IMUX.IMUX7.DELAY | PCIE3.MICOMPLETIONRAMREADDATA67 |
| CELL27.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA108 |
| CELL27.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA109 |
| CELL27.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA110 |
| CELL27.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA111 |
| CELL27.IMUX.IMUX12.DELAY | PCIE3.CFGMSGTRANSMITDATA14 |
| CELL27.IMUX.IMUX13.DELAY | PCIE3.CFGMSGTRANSMITDATA15 |
| CELL27.IMUX.IMUX14.DELAY | PCIE3.CFGMSGTRANSMITDATA16 |
| CELL27.IMUX.IMUX15.DELAY | PCIE3.CFGMSGTRANSMITDATA17 |
| CELL27.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSISELECT1 |
| CELL27.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSISELECT2 |
| CELL27.IMUX.IMUX18.DELAY | PCIE3.CFGINTERRUPTMSISELECT3 |
| CELL27.IMUX.IMUX19.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS0 |
| CELL27.OUT0.TMIN | PCIE3.MICOMPLETIONRAMREADENABLEU0 |
| CELL27.OUT1.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU16 |
| CELL27.OUT2.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAU6 |
| CELL27.OUT3.TMIN | PCIE3.MAXISRCTDATA92 |
| CELL27.OUT4.TMIN | PCIE3.MICOMPLETIONRAMREADENABLEU1 |
| CELL27.OUT5.TMIN | PCIE3.MAXISRCTDATA93 |
| CELL27.OUT6.TMIN | PCIE3.MICOMPLETIONRAMWRITEENABLEU0 |
| CELL27.OUT7.TMIN | PCIE3.MICOMPLETIONRAMWRITEENABLEU1 |
| CELL27.OUT8.TMIN | PCIE3.MAXISRCTDATA94 |
| CELL27.OUT9.TMIN | PCIE3.MAXISRCTDATA95 |
| CELL27.OUT10.TMIN | PCIE3.MAXISRCTDATA242 |
| CELL27.OUT11.TMIN | PCIE3.MAXISRCTDATA243 |
| CELL27.OUT12.TMIN | PCIE3.MAXISRCTDATA244 |
| CELL27.OUT13.TMIN | PCIE3.MAXISRCTDATA245 |
| CELL27.OUT14.TMIN | PCIE3.MAXISRCTUSER59 |
| CELL27.OUT15.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU26 |
| CELL27.OUT16.TMIN | PCIE3.MAXISRCTUSER60 |
| CELL27.OUT17.TMIN | PCIE3.MAXISRCTUSER61 |
| CELL27.OUT18.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU15 |
| CELL27.OUT19.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU34 |
| CELL27.OUT20.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAU6 |
| CELL27.OUT21.TMIN | PCIE3.CFGVFTPHSTMODE11 |
| CELL27.OUT22.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU7 |
| CELL27.OUT23.TMIN | PCIE3.CFGVFTPHSTMODE12 |
| CELL28.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA68 |
| CELL28.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA69 |
| CELL28.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA70 |
| CELL28.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA71 |
| CELL28.IMUX.IMUX4.DELAY | PCIE3.MICOMPLETIONRAMREADDATA72 |
| CELL28.IMUX.IMUX5.DELAY | PCIE3.MICOMPLETIONRAMREADDATA73 |
| CELL28.IMUX.IMUX6.DELAY | PCIE3.MICOMPLETIONRAMREADDATA74 |
| CELL28.IMUX.IMUX7.DELAY | PCIE3.MICOMPLETIONRAMREADDATA75 |
| CELL28.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA112 |
| CELL28.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA113 |
| CELL28.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA114 |
| CELL28.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA115 |
| CELL28.IMUX.IMUX12.DELAY | PCIE3.CFGMSGTRANSMITDATA18 |
| CELL28.IMUX.IMUX13.DELAY | PCIE3.CFGMSGTRANSMITDATA19 |
| CELL28.IMUX.IMUX14.DELAY | PCIE3.CFGMSGTRANSMITDATA20 |
| CELL28.IMUX.IMUX15.DELAY | PCIE3.CFGMSGTRANSMITDATA21 |
| CELL28.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS1 |
| CELL28.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS2 |
| CELL28.OUT0.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAU2 |
| CELL28.OUT1.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAU5 |
| CELL28.OUT2.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAU1 |
| CELL28.OUT3.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU35 |
| CELL28.OUT4.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAU3 |
| CELL28.OUT5.TMIN | PCIE3.MAXISRCTDATA96 |
| CELL28.OUT6.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSAU8 |
| CELL28.OUT7.TMIN | PCIE3.MAXISRCTDATA97 |
| CELL28.OUT8.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAU3 |
| CELL28.OUT9.TMIN | PCIE3.MAXISRCTDATA98 |
| CELL28.OUT10.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAU8 |
| CELL28.OUT11.TMIN | PCIE3.MAXISRCTDATA99 |
| CELL28.OUT12.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAU2 |
| CELL28.OUT13.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAU5 |
| CELL28.OUT14.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSAU1 |
| CELL28.OUT15.TMIN | PCIE3.MAXISRCTDATA241 |
| CELL28.OUT16.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU29 |
| CELL28.OUT17.TMIN | PCIE3.CFGVFTPHSTMODE13 |
| CELL28.OUT18.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU27 |
| CELL28.OUT19.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU20 |
| CELL28.OUT20.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU21 |
| CELL28.OUT21.TMIN | PCIE3.CFGVFTPHSTMODE14 |
| CELL28.OUT22.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU19 |
| CELL28.OUT23.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU28 |
| CELL29.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA76 |
| CELL29.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA77 |
| CELL29.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA78 |
| CELL29.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA79 |
| CELL29.IMUX.IMUX4.DELAY | PCIE3.MICOMPLETIONRAMREADDATA80 |
| CELL29.IMUX.IMUX5.DELAY | PCIE3.MICOMPLETIONRAMREADDATA81 |
| CELL29.IMUX.IMUX6.DELAY | PCIE3.MICOMPLETIONRAMREADDATA82 |
| CELL29.IMUX.IMUX7.DELAY | PCIE3.MICOMPLETIONRAMREADDATA83 |
| CELL29.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA116 |
| CELL29.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA117 |
| CELL29.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA118 |
| CELL29.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA119 |
| CELL29.IMUX.IMUX12.DELAY | PCIE3.CFGMSGTRANSMITDATA22 |
| CELL29.IMUX.IMUX13.DELAY | PCIE3.CFGMSGTRANSMITDATA23 |
| CELL29.IMUX.IMUX14.DELAY | PCIE3.CFGMSGTRANSMITDATA24 |
| CELL29.IMUX.IMUX15.DELAY | PCIE3.CFGMSGTRANSMITDATA25 |
| CELL29.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS3 |
| CELL29.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS4 |
| CELL29.OUT0.TMIN | PCIE3.MAXISRCTDATA100 |
| CELL29.OUT1.TMIN | PCIE3.MAXISRCTDATA101 |
| CELL29.OUT2.TMIN | PCIE3.MAXISRCTDATA102 |
| CELL29.OUT3.TMIN | PCIE3.MAXISRCTDATA103 |
| CELL29.OUT4.TMIN | PCIE3.MAXISRCTDATA237 |
| CELL29.OUT5.TMIN | PCIE3.MAXISRCTDATA238 |
| CELL29.OUT6.TMIN | PCIE3.MAXISRCTDATA239 |
| CELL29.OUT7.TMIN | PCIE3.MAXISRCTDATA240 |
| CELL29.OUT8.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU30 |
| CELL29.OUT9.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU23 |
| CELL29.OUT10.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU32 |
| CELL29.OUT11.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU25 |
| CELL29.OUT12.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU22 |
| CELL29.OUT13.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU31 |
| CELL29.OUT14.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU24 |
| CELL29.OUT15.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU33 |
| CELL29.OUT16.TMIN | PCIE3.MAXISRCTUSER62 |
| CELL29.OUT17.TMIN | PCIE3.MAXISRCTUSER63 |
| CELL29.OUT18.TMIN | PCIE3.MAXISRCTUSER64 |
| CELL29.OUT19.TMIN | PCIE3.MAXISRCTUSER65 |
| CELL29.OUT20.TMIN | PCIE3.CFGMGMTREADDATA16 |
| CELL29.OUT21.TMIN | PCIE3.CFGMGMTREADDATA17 |
| CELL29.OUT22.TMIN | PCIE3.CFGVFTPHSTMODE15 |
| CELL29.OUT23.TMIN | PCIE3.CFGVFTPHSTMODE16 |
| CELL30.IMUX.CLK0 | PCIE3.CORECLKMICOMPLETIONRAMU |
| CELL30.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA84 |
| CELL30.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA85 |
| CELL30.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA86 |
| CELL30.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA87 |
| CELL30.IMUX.IMUX4.DELAY | PCIE3.MICOMPLETIONRAMREADDATA88 |
| CELL30.IMUX.IMUX5.DELAY | PCIE3.MICOMPLETIONRAMREADDATA89 |
| CELL30.IMUX.IMUX6.DELAY | PCIE3.MICOMPLETIONRAMREADDATA90 |
| CELL30.IMUX.IMUX7.DELAY | PCIE3.MICOMPLETIONRAMREADDATA91 |
| CELL30.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA120 |
| CELL30.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA121 |
| CELL30.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA122 |
| CELL30.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA123 |
| CELL30.IMUX.IMUX12.DELAY | PCIE3.CFGMSGTRANSMITDATA26 |
| CELL30.IMUX.IMUX13.DELAY | PCIE3.CFGMSGTRANSMITDATA27 |
| CELL30.IMUX.IMUX14.DELAY | PCIE3.CFGMSGTRANSMITDATA28 |
| CELL30.IMUX.IMUX15.DELAY | PCIE3.CFGMSGTRANSMITDATA29 |
| CELL30.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS5 |
| CELL30.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS6 |
| CELL30.OUT0.TMIN | PCIE3.MAXISRCTDATA104 |
| CELL30.OUT1.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU45 |
| CELL30.OUT2.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU38 |
| CELL30.OUT3.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU47 |
| CELL30.OUT4.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU44 |
| CELL30.OUT5.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU37 |
| CELL30.OUT6.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU46 |
| CELL30.OUT7.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU39 |
| CELL30.OUT8.TMIN | PCIE3.MAXISRCTDATA105 |
| CELL30.OUT9.TMIN | PCIE3.MAXISRCTDATA106 |
| CELL30.OUT10.TMIN | PCIE3.MAXISRCTDATA107 |
| CELL30.OUT11.TMIN | PCIE3.MAXISRCTDATA233 |
| CELL30.OUT12.TMIN | PCIE3.MAXISRCTDATA234 |
| CELL30.OUT13.TMIN | PCIE3.MAXISRCTDATA235 |
| CELL30.OUT14.TMIN | PCIE3.MAXISRCTDATA236 |
| CELL30.OUT15.TMIN | PCIE3.MAXISRCTUSER66 |
| CELL30.OUT16.TMIN | PCIE3.MAXISRCTUSER67 |
| CELL30.OUT17.TMIN | PCIE3.MAXISRCTUSER68 |
| CELL30.OUT18.TMIN | PCIE3.MAXISRCTUSER69 |
| CELL30.OUT19.TMIN | PCIE3.CFGMGMTREADDATA18 |
| CELL30.OUT20.TMIN | PCIE3.CFGMGMTREADDATA19 |
| CELL30.OUT21.TMIN | PCIE3.CFGMGMTREADDATA20 |
| CELL30.OUT22.TMIN | PCIE3.CFGVFTPHSTMODE17 |
| CELL30.OUT23.TMIN | PCIE3.CFGMSGRECEIVED |
| CELL31.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA92 |
| CELL31.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA93 |
| CELL31.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA94 |
| CELL31.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA95 |
| CELL31.IMUX.IMUX4.DELAY | PCIE3.MICOMPLETIONRAMREADDATA96 |
| CELL31.IMUX.IMUX5.DELAY | PCIE3.MICOMPLETIONRAMREADDATA97 |
| CELL31.IMUX.IMUX6.DELAY | PCIE3.MICOMPLETIONRAMREADDATA98 |
| CELL31.IMUX.IMUX7.DELAY | PCIE3.MICOMPLETIONRAMREADDATA99 |
| CELL31.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA124 |
| CELL31.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA125 |
| CELL31.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA126 |
| CELL31.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA127 |
| CELL31.IMUX.IMUX12.DELAY | PCIE3.CFGMSGTRANSMITDATA30 |
| CELL31.IMUX.IMUX13.DELAY | PCIE3.CFGMSGTRANSMITDATA31 |
| CELL31.IMUX.IMUX14.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS7 |
| CELL31.IMUX.IMUX15.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS8 |
| CELL31.OUT0.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU36 |
| CELL31.OUT1.TMIN | PCIE3.MAXISRCTDATA108 |
| CELL31.OUT2.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBU4 |
| CELL31.OUT3.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBU9 |
| CELL31.OUT4.TMIN | PCIE3.MAXISRCTDATA109 |
| CELL31.OUT5.TMIN | PCIE3.MAXISRCTDATA110 |
| CELL31.OUT6.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBU0 |
| CELL31.OUT7.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBU7 |
| CELL31.OUT8.TMIN | PCIE3.MAXISRCTDATA111 |
| CELL31.OUT9.TMIN | PCIE3.MAXISRCTDATA232 |
| CELL31.OUT10.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBU0 |
| CELL31.OUT11.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBU7 |
| CELL31.OUT12.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU54 |
| CELL31.OUT13.TMIN | PCIE3.CFGMSGRECEIVEDDATA0 |
| CELL31.OUT14.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBU4 |
| CELL31.OUT15.TMIN | PCIE3.CFGMSGRECEIVEDDATA1 |
| CELL31.OUT16.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU42 |
| CELL31.OUT17.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU50 |
| CELL31.OUT18.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU40 |
| CELL31.OUT19.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU48 |
| CELL31.OUT20.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU49 |
| CELL31.OUT21.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBU9 |
| CELL31.OUT22.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU53 |
| CELL31.OUT23.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU41 |
| CELL32.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA100 |
| CELL32.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA101 |
| CELL32.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA102 |
| CELL32.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA103 |
| CELL32.IMUX.IMUX4.DELAY | PCIE3.MICOMPLETIONRAMREADDATA104 |
| CELL32.IMUX.IMUX5.DELAY | PCIE3.MICOMPLETIONRAMREADDATA105 |
| CELL32.IMUX.IMUX6.DELAY | PCIE3.MICOMPLETIONRAMREADDATA106 |
| CELL32.IMUX.IMUX7.DELAY | PCIE3.MICOMPLETIONRAMREADDATA107 |
| CELL32.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA128 |
| CELL32.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA129 |
| CELL32.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA130 |
| CELL32.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA131 |
| CELL32.IMUX.IMUX12.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS9 |
| CELL32.IMUX.IMUX13.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS10 |
| CELL32.IMUX.IMUX14.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS11 |
| CELL32.IMUX.IMUX15.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS12 |
| CELL32.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSITPHSTTAG8 |
| CELL32.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSIFUNCTIONNUMBER0 |
| CELL32.IMUX.IMUX18.DELAY | PCIE3.CFGINTERRUPTMSIFUNCTIONNUMBER1 |
| CELL32.IMUX.IMUX19.DELAY | PCIE3.CFGINTERRUPTMSIFUNCTIONNUMBER2 |
| CELL32.OUT0.TMIN | PCIE3.MICOMPLETIONRAMREADENABLEU2 |
| CELL32.OUT1.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU52 |
| CELL32.OUT2.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBU6 |
| CELL32.OUT3.TMIN | PCIE3.MAXISRCTDATA112 |
| CELL32.OUT4.TMIN | PCIE3.MICOMPLETIONRAMREADENABLEU3 |
| CELL32.OUT5.TMIN | PCIE3.MAXISRCTDATA113 |
| CELL32.OUT6.TMIN | PCIE3.MICOMPLETIONRAMWRITEENABLEU2 |
| CELL32.OUT7.TMIN | PCIE3.MICOMPLETIONRAMWRITEENABLEU3 |
| CELL32.OUT8.TMIN | PCIE3.MAXISRCTDATA114 |
| CELL32.OUT9.TMIN | PCIE3.MAXISRCTDATA115 |
| CELL32.OUT10.TMIN | PCIE3.MAXISRCTDATA228 |
| CELL32.OUT11.TMIN | PCIE3.MAXISRCTDATA229 |
| CELL32.OUT12.TMIN | PCIE3.MAXISRCTDATA230 |
| CELL32.OUT13.TMIN | PCIE3.MAXISRCTDATA231 |
| CELL32.OUT14.TMIN | PCIE3.MAXISRCTUSER70 |
| CELL32.OUT15.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU62 |
| CELL32.OUT16.TMIN | PCIE3.MAXISRCTUSER71 |
| CELL32.OUT17.TMIN | PCIE3.MAXISRCTUSER72 |
| CELL32.OUT18.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU51 |
| CELL32.OUT19.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU70 |
| CELL32.OUT20.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBU6 |
| CELL32.OUT21.TMIN | PCIE3.CFGMSGRECEIVEDDATA2 |
| CELL32.OUT22.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU43 |
| CELL32.OUT23.TMIN | PCIE3.CFGMSGRECEIVEDDATA3 |
| CELL33.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA108 |
| CELL33.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA109 |
| CELL33.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA110 |
| CELL33.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA111 |
| CELL33.IMUX.IMUX4.DELAY | PCIE3.MICOMPLETIONRAMREADDATA112 |
| CELL33.IMUX.IMUX5.DELAY | PCIE3.MICOMPLETIONRAMREADDATA113 |
| CELL33.IMUX.IMUX6.DELAY | PCIE3.MICOMPLETIONRAMREADDATA114 |
| CELL33.IMUX.IMUX7.DELAY | PCIE3.MICOMPLETIONRAMREADDATA115 |
| CELL33.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA132 |
| CELL33.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA133 |
| CELL33.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA134 |
| CELL33.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA135 |
| CELL33.IMUX.IMUX12.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS13 |
| CELL33.IMUX.IMUX13.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS14 |
| CELL33.IMUX.IMUX14.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS15 |
| CELL33.IMUX.IMUX15.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS16 |
| CELL33.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSITPHSTTAG6 |
| CELL33.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSITPHSTTAG7 |
| CELL33.OUT0.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBU2 |
| CELL33.OUT1.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBU5 |
| CELL33.OUT2.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBU1 |
| CELL33.OUT3.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU71 |
| CELL33.OUT4.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBU3 |
| CELL33.OUT5.TMIN | PCIE3.MAXISRCTDATA116 |
| CELL33.OUT6.TMIN | PCIE3.MICOMPLETIONRAMWRITEADDRESSBU8 |
| CELL33.OUT7.TMIN | PCIE3.MAXISRCTDATA117 |
| CELL33.OUT8.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBU3 |
| CELL33.OUT9.TMIN | PCIE3.MAXISRCTDATA118 |
| CELL33.OUT10.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBU8 |
| CELL33.OUT11.TMIN | PCIE3.MAXISRCTDATA119 |
| CELL33.OUT12.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBU2 |
| CELL33.OUT13.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBU5 |
| CELL33.OUT14.TMIN | PCIE3.MICOMPLETIONRAMREADADDRESSBU1 |
| CELL33.OUT15.TMIN | PCIE3.MAXISRCTDATA227 |
| CELL33.OUT16.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU65 |
| CELL33.OUT17.TMIN | PCIE3.CFGMSGRECEIVEDDATA4 |
| CELL33.OUT18.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU63 |
| CELL33.OUT19.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU56 |
| CELL33.OUT20.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU57 |
| CELL33.OUT21.TMIN | PCIE3.CFGMSGRECEIVEDDATA5 |
| CELL33.OUT22.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU55 |
| CELL33.OUT23.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU64 |
| CELL34.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA116 |
| CELL34.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA117 |
| CELL34.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA118 |
| CELL34.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA119 |
| CELL34.IMUX.IMUX4.DELAY | PCIE3.MICOMPLETIONRAMREADDATA120 |
| CELL34.IMUX.IMUX5.DELAY | PCIE3.MICOMPLETIONRAMREADDATA121 |
| CELL34.IMUX.IMUX6.DELAY | PCIE3.MICOMPLETIONRAMREADDATA122 |
| CELL34.IMUX.IMUX7.DELAY | PCIE3.MICOMPLETIONRAMREADDATA123 |
| CELL34.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA136 |
| CELL34.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA137 |
| CELL34.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA138 |
| CELL34.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA139 |
| CELL34.IMUX.IMUX12.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS17 |
| CELL34.IMUX.IMUX13.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS18 |
| CELL34.IMUX.IMUX14.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS19 |
| CELL34.IMUX.IMUX15.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS20 |
| CELL34.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSITPHSTTAG4 |
| CELL34.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSITPHSTTAG5 |
| CELL34.OUT0.TMIN | PCIE3.MAXISRCTDATA120 |
| CELL34.OUT1.TMIN | PCIE3.MAXISRCTDATA121 |
| CELL34.OUT2.TMIN | PCIE3.MAXISRCTDATA122 |
| CELL34.OUT3.TMIN | PCIE3.MAXISRCTDATA123 |
| CELL34.OUT4.TMIN | PCIE3.MAXISRCTDATA223 |
| CELL34.OUT5.TMIN | PCIE3.MAXISRCTDATA224 |
| CELL34.OUT6.TMIN | PCIE3.MAXISRCTDATA225 |
| CELL34.OUT7.TMIN | PCIE3.MAXISRCTDATA226 |
| CELL34.OUT8.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU66 |
| CELL34.OUT9.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU59 |
| CELL34.OUT10.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU68 |
| CELL34.OUT11.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU61 |
| CELL34.OUT12.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU58 |
| CELL34.OUT13.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU67 |
| CELL34.OUT14.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU60 |
| CELL34.OUT15.TMIN | PCIE3.MICOMPLETIONRAMWRITEDATAU69 |
| CELL34.OUT16.TMIN | PCIE3.MAXISRCTUSER73 |
| CELL34.OUT17.TMIN | PCIE3.MAXISRCTUSER74 |
| CELL34.OUT18.TMIN | PCIE3.CFGMGMTREADDATA21 |
| CELL34.OUT19.TMIN | PCIE3.CFGMGMTREADDATA22 |
| CELL34.OUT20.TMIN | PCIE3.CFGVFSTATUS10 |
| CELL34.OUT21.TMIN | PCIE3.CFGVFSTATUS11 |
| CELL34.OUT22.TMIN | PCIE3.CFGINTERRUPTMSIDATA6 |
| CELL34.OUT23.TMIN | PCIE3.CFGMSGRECEIVEDDATA6 |
| CELL35.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA124 |
| CELL35.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA125 |
| CELL35.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA126 |
| CELL35.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA127 |
| CELL35.IMUX.IMUX4.DELAY | PCIE3.MICOMPLETIONRAMREADDATA128 |
| CELL35.IMUX.IMUX5.DELAY | PCIE3.MICOMPLETIONRAMREADDATA129 |
| CELL35.IMUX.IMUX6.DELAY | PCIE3.MICOMPLETIONRAMREADDATA130 |
| CELL35.IMUX.IMUX7.DELAY | PCIE3.MICOMPLETIONRAMREADDATA131 |
| CELL35.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA140 |
| CELL35.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA141 |
| CELL35.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA142 |
| CELL35.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA143 |
| CELL35.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTDATA252 |
| CELL35.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTDATA253 |
| CELL35.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTDATA254 |
| CELL35.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTDATA255 |
| CELL35.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSITPHSTTAG0 |
| CELL35.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSITPHSTTAG1 |
| CELL35.IMUX.IMUX18.DELAY | PCIE3.CFGINTERRUPTMSITPHSTTAG2 |
| CELL35.IMUX.IMUX19.DELAY | PCIE3.CFGINTERRUPTMSITPHSTTAG3 |
| CELL35.OUT0.TMIN | PCIE3.MAXISRCTDATA124 |
| CELL35.OUT1.TMIN | PCIE3.MAXISRCTDATA125 |
| CELL35.OUT2.TMIN | PCIE3.MAXISRCTDATA126 |
| CELL35.OUT3.TMIN | PCIE3.MAXISRCTDATA127 |
| CELL35.OUT4.TMIN | PCIE3.MAXISRCTDATA219 |
| CELL35.OUT5.TMIN | PCIE3.MAXISRCTDATA220 |
| CELL35.OUT6.TMIN | PCIE3.MAXISRCTDATA221 |
| CELL35.OUT7.TMIN | PCIE3.MAXISRCTDATA222 |
| CELL35.OUT8.TMIN | PCIE3.CFGMGMTREADDATA23 |
| CELL35.OUT9.TMIN | PCIE3.CFGMGMTREADDATA24 |
| CELL35.OUT10.TMIN | PCIE3.CFGMGMTREADDATA25 |
| CELL35.OUT11.TMIN | PCIE3.CFGMGMTREADDATA26 |
| CELL35.OUT12.TMIN | PCIE3.CFGVFSTATUS6 |
| CELL35.OUT13.TMIN | PCIE3.CFGVFSTATUS7 |
| CELL35.OUT14.TMIN | PCIE3.CFGVFSTATUS8 |
| CELL35.OUT15.TMIN | PCIE3.CFGVFSTATUS9 |
| CELL35.OUT16.TMIN | PCIE3.CFGMSGRECEIVEDDATA7 |
| CELL35.OUT17.TMIN | PCIE3.CFGMSGRECEIVEDTYPE0 |
| CELL35.OUT18.TMIN | PCIE3.CFGMSGRECEIVEDTYPE1 |
| CELL35.OUT19.TMIN | PCIE3.CFGMSGRECEIVEDTYPE2 |
| CELL35.OUT20.TMIN | PCIE3.CFGINTERRUPTMSIDATA7 |
| CELL35.OUT21.TMIN | PCIE3.CFGINTERRUPTMSIDATA8 |
| CELL35.OUT22.TMIN | PCIE3.CFGINTERRUPTMSIDATA9 |
| CELL35.OUT23.TMIN | PCIE3.CFGINTERRUPTMSIDATA10 |
| CELL36.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA132 |
| CELL36.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA133 |
| CELL36.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA134 |
| CELL36.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA135 |
| CELL36.IMUX.IMUX4.DELAY | PCIE3.MICOMPLETIONRAMREADDATA136 |
| CELL36.IMUX.IMUX5.DELAY | PCIE3.MICOMPLETIONRAMREADDATA137 |
| CELL36.IMUX.IMUX6.DELAY | PCIE3.MICOMPLETIONRAMREADDATA138 |
| CELL36.IMUX.IMUX7.DELAY | PCIE3.MICOMPLETIONRAMREADDATA139 |
| CELL36.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA144 |
| CELL36.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA145 |
| CELL36.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA146 |
| CELL36.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA147 |
| CELL36.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTDATA248 |
| CELL36.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTDATA249 |
| CELL36.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTDATA250 |
| CELL36.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTDATA251 |
| CELL36.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS21 |
| CELL36.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS22 |
| CELL36.IMUX.IMUX18.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS23 |
| CELL36.IMUX.IMUX19.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS24 |
| CELL36.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSITPHTYPE0 |
| CELL36.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSITPHTYPE1 |
| CELL36.OUT0.TMIN | PCIE3.MAXISRCTDATA128 |
| CELL36.OUT1.TMIN | PCIE3.MAXISRCTDATA129 |
| CELL36.OUT2.TMIN | PCIE3.MAXISRCTDATA130 |
| CELL36.OUT3.TMIN | PCIE3.MAXISRCTDATA131 |
| CELL36.OUT4.TMIN | PCIE3.MAXISRCTDATA215 |
| CELL36.OUT5.TMIN | PCIE3.MAXISRCTDATA216 |
| CELL36.OUT6.TMIN | PCIE3.MAXISRCTDATA217 |
| CELL36.OUT7.TMIN | PCIE3.MAXISRCTDATA218 |
| CELL36.OUT8.TMIN | PCIE3.CFGMGMTREADDATA27 |
| CELL36.OUT9.TMIN | PCIE3.CFGMGMTREADDATA28 |
| CELL36.OUT10.TMIN | PCIE3.CFGMGMTREADDATA29 |
| CELL36.OUT11.TMIN | PCIE3.CFGMGMTREADDATA30 |
| CELL36.OUT12.TMIN | PCIE3.CFGVFSTATUS2 |
| CELL36.OUT13.TMIN | PCIE3.CFGVFSTATUS3 |
| CELL36.OUT14.TMIN | PCIE3.CFGVFSTATUS4 |
| CELL36.OUT15.TMIN | PCIE3.CFGVFSTATUS5 |
| CELL36.OUT16.TMIN | PCIE3.CFGMSGRECEIVEDTYPE3 |
| CELL36.OUT17.TMIN | PCIE3.CFGMSGRECEIVEDTYPE4 |
| CELL36.OUT18.TMIN | PCIE3.CFGMSGTRANSMITDONE |
| CELL36.OUT19.TMIN | PCIE3.CFGINTERRUPTMSIDATA11 |
| CELL36.OUT20.TMIN | PCIE3.XILUNCONNOUT22 |
| CELL36.OUT21.TMIN | PCIE3.XILUNCONNOUT23 |
| CELL36.OUT22.TMIN | PCIE3.XILUNCONNOUT24 |
| CELL36.OUT23.TMIN | PCIE3.XILUNCONNOUT25 |
| CELL37.IMUX.IMUX0.DELAY | PCIE3.MICOMPLETIONRAMREADDATA140 |
| CELL37.IMUX.IMUX1.DELAY | PCIE3.MICOMPLETIONRAMREADDATA141 |
| CELL37.IMUX.IMUX2.DELAY | PCIE3.MICOMPLETIONRAMREADDATA142 |
| CELL37.IMUX.IMUX3.DELAY | PCIE3.MICOMPLETIONRAMREADDATA143 |
| CELL37.IMUX.IMUX4.DELAY | PCIE3.SAXISRQTDATA148 |
| CELL37.IMUX.IMUX5.DELAY | PCIE3.SAXISRQTDATA149 |
| CELL37.IMUX.IMUX6.DELAY | PCIE3.SAXISRQTDATA150 |
| CELL37.IMUX.IMUX7.DELAY | PCIE3.SAXISRQTDATA151 |
| CELL37.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA244 |
| CELL37.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA245 |
| CELL37.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA246 |
| CELL37.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA247 |
| CELL37.IMUX.IMUX12.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS25 |
| CELL37.IMUX.IMUX13.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS26 |
| CELL37.IMUX.IMUX14.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS27 |
| CELL37.IMUX.IMUX15.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS28 |
| CELL37.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSIATTR2 |
| CELL37.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSITPHPRESENT |
| CELL37.OUT0.TMIN | PCIE3.MAXISRCTDATA132 |
| CELL37.OUT1.TMIN | PCIE3.MAXISRCTDATA133 |
| CELL37.OUT2.TMIN | PCIE3.MAXISRCTDATA134 |
| CELL37.OUT3.TMIN | PCIE3.MAXISRCTDATA135 |
| CELL37.OUT4.TMIN | PCIE3.MAXISRCTDATA211 |
| CELL37.OUT5.TMIN | PCIE3.MAXISRCTDATA212 |
| CELL37.OUT6.TMIN | PCIE3.MAXISRCTDATA213 |
| CELL37.OUT7.TMIN | PCIE3.MAXISRCTDATA214 |
| CELL37.OUT8.TMIN | PCIE3.CFGMGMTREADDATA31 |
| CELL37.OUT9.TMIN | PCIE3.CFGMGMTREADWRITEDONE |
| CELL37.OUT10.TMIN | PCIE3.CFGPHYLINKDOWN |
| CELL37.OUT11.TMIN | PCIE3.CFGPHYLINKSTATUS0 |
| CELL37.OUT12.TMIN | PCIE3.CFGFUNCTIONSTATUS6 |
| CELL37.OUT13.TMIN | PCIE3.CFGFUNCTIONSTATUS7 |
| CELL37.OUT14.TMIN | PCIE3.CFGVFSTATUS0 |
| CELL37.OUT15.TMIN | PCIE3.CFGVFSTATUS1 |
| CELL37.OUT16.TMIN | PCIE3.CFGINTERRUPTMSIDATA12 |
| CELL37.OUT17.TMIN | PCIE3.CFGINTERRUPTMSIDATA13 |
| CELL37.OUT18.TMIN | PCIE3.CFGINTERRUPTMSIDATA14 |
| CELL37.OUT19.TMIN | PCIE3.CFGINTERRUPTMSIDATA15 |
| CELL37.OUT20.TMIN | PCIE3.XILUNCONNOUT18 |
| CELL37.OUT21.TMIN | PCIE3.XILUNCONNOUT19 |
| CELL37.OUT22.TMIN | PCIE3.XILUNCONNOUT20 |
| CELL37.OUT23.TMIN | PCIE3.XILUNCONNOUT21 |
| CELL38.IMUX.IMUX0.DELAY | PCIE3.MIREPLAYRAMREADDATA0 |
| CELL38.IMUX.IMUX1.DELAY | PCIE3.MIREPLAYRAMREADDATA1 |
| CELL38.IMUX.IMUX2.DELAY | PCIE3.MIREPLAYRAMREADDATA2 |
| CELL38.IMUX.IMUX3.DELAY | PCIE3.MIREPLAYRAMREADDATA3 |
| CELL38.IMUX.IMUX4.DELAY | PCIE3.MIREPLAYRAMREADDATA4 |
| CELL38.IMUX.IMUX5.DELAY | PCIE3.MIREPLAYRAMREADDATA5 |
| CELL38.IMUX.IMUX6.DELAY | PCIE3.MIREPLAYRAMREADDATA6 |
| CELL38.IMUX.IMUX7.DELAY | PCIE3.MIREPLAYRAMREADDATA7 |
| CELL38.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA152 |
| CELL38.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA153 |
| CELL38.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA154 |
| CELL38.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA155 |
| CELL38.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTDATA240 |
| CELL38.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTDATA241 |
| CELL38.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTDATA242 |
| CELL38.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTDATA243 |
| CELL38.IMUX.IMUX16.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS29 |
| CELL38.IMUX.IMUX17.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS30 |
| CELL38.IMUX.IMUX18.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS31 |
| CELL38.IMUX.IMUX19.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS32 |
| CELL38.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIATTR0 |
| CELL38.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIATTR1 |
| CELL38.OUT0.TMIN | PCIE3.MAXISRCTDATA136 |
| CELL38.OUT1.TMIN | PCIE3.MAXISRCTDATA137 |
| CELL38.OUT2.TMIN | PCIE3.MAXISRCTDATA138 |
| CELL38.OUT3.TMIN | PCIE3.MAXISRCTDATA139 |
| CELL38.OUT4.TMIN | PCIE3.MAXISRCTDATA207 |
| CELL38.OUT5.TMIN | PCIE3.MAXISRCTDATA208 |
| CELL38.OUT6.TMIN | PCIE3.MAXISRCTDATA209 |
| CELL38.OUT7.TMIN | PCIE3.MAXISRCTDATA210 |
| CELL38.OUT8.TMIN | PCIE3.CFGPHYLINKSTATUS1 |
| CELL38.OUT9.TMIN | PCIE3.CFGNEGOTIATEDWIDTH0 |
| CELL38.OUT10.TMIN | PCIE3.CFGNEGOTIATEDWIDTH1 |
| CELL38.OUT11.TMIN | PCIE3.CFGNEGOTIATEDWIDTH2 |
| CELL38.OUT12.TMIN | PCIE3.CFGFUNCTIONSTATUS2 |
| CELL38.OUT13.TMIN | PCIE3.CFGFUNCTIONSTATUS3 |
| CELL38.OUT14.TMIN | PCIE3.CFGFUNCTIONSTATUS4 |
| CELL38.OUT15.TMIN | PCIE3.CFGFUNCTIONSTATUS5 |
| CELL38.OUT16.TMIN | PCIE3.CFGINTERRUPTMSIDATA16 |
| CELL38.OUT17.TMIN | PCIE3.CFGINTERRUPTMSIDATA17 |
| CELL38.OUT18.TMIN | PCIE3.CFGINTERRUPTMSIDATA18 |
| CELL38.OUT19.TMIN | PCIE3.CFGINTERRUPTMSIDATA19 |
| CELL38.OUT20.TMIN | PCIE3.CFGINTERRUPTMSIXVFMASK5 |
| CELL38.OUT21.TMIN | PCIE3.CFGINTERRUPTMSIXSENT |
| CELL38.OUT22.TMIN | PCIE3.CFGINTERRUPTMSIXFAIL |
| CELL38.OUT23.TMIN | PCIE3.XILUNCONNOUT17 |
| CELL39.IMUX.IMUX0.DELAY | PCIE3.MIREPLAYRAMREADDATA8 |
| CELL39.IMUX.IMUX1.DELAY | PCIE3.MIREPLAYRAMREADDATA9 |
| CELL39.IMUX.IMUX2.DELAY | PCIE3.MIREPLAYRAMREADDATA10 |
| CELL39.IMUX.IMUX3.DELAY | PCIE3.MIREPLAYRAMREADDATA11 |
| CELL39.IMUX.IMUX4.DELAY | PCIE3.MIREPLAYRAMREADDATA12 |
| CELL39.IMUX.IMUX5.DELAY | PCIE3.MIREPLAYRAMREADDATA13 |
| CELL39.IMUX.IMUX6.DELAY | PCIE3.MIREPLAYRAMREADDATA14 |
| CELL39.IMUX.IMUX7.DELAY | PCIE3.MIREPLAYRAMREADDATA15 |
| CELL39.IMUX.IMUX8.DELAY | PCIE3.MIREPLAYRAMREADDATA16 |
| CELL39.IMUX.IMUX9.DELAY | PCIE3.MIREPLAYRAMREADDATA17 |
| CELL39.IMUX.IMUX10.DELAY | PCIE3.MIREPLAYRAMREADDATA18 |
| CELL39.IMUX.IMUX11.DELAY | PCIE3.MIREPLAYRAMREADDATA19 |
| CELL39.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTDATA156 |
| CELL39.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTDATA157 |
| CELL39.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTDATA158 |
| CELL39.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTDATA159 |
| CELL39.IMUX.IMUX16.DELAY | PCIE3.SAXISRQTDATA236 |
| CELL39.IMUX.IMUX17.DELAY | PCIE3.SAXISRQTDATA237 |
| CELL39.IMUX.IMUX18.DELAY | PCIE3.SAXISRQTDATA238 |
| CELL39.IMUX.IMUX19.DELAY | PCIE3.SAXISRQTDATA239 |
| CELL39.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS33 |
| CELL39.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS34 |
| CELL39.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS35 |
| CELL39.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS36 |
| CELL39.IMUX.IMUX24.DELAY | PCIE3.CFGINTERRUPTMSIXDATA31 |
| CELL39.IMUX.IMUX25.DELAY | PCIE3.CFGINTERRUPTMSIXINT |
| CELL39.OUT0.TMIN | PCIE3.MAXISRCTDATA140 |
| CELL39.OUT1.TMIN | PCIE3.MAXISRCTDATA141 |
| CELL39.OUT2.TMIN | PCIE3.MAXISRCTDATA142 |
| CELL39.OUT3.TMIN | PCIE3.MAXISRCTDATA143 |
| CELL39.OUT4.TMIN | PCIE3.MAXISRCTDATA203 |
| CELL39.OUT5.TMIN | PCIE3.MAXISRCTDATA204 |
| CELL39.OUT6.TMIN | PCIE3.MAXISRCTDATA205 |
| CELL39.OUT7.TMIN | PCIE3.MAXISRCTDATA206 |
| CELL39.OUT8.TMIN | PCIE3.CFGNEGOTIATEDWIDTH3 |
| CELL39.OUT9.TMIN | PCIE3.CFGCURRENTSPEED0 |
| CELL39.OUT10.TMIN | PCIE3.CFGCURRENTSPEED1 |
| CELL39.OUT11.TMIN | PCIE3.CFGCURRENTSPEED2 |
| CELL39.OUT12.TMIN | PCIE3.CFGMAXREADREQ1 |
| CELL39.OUT13.TMIN | PCIE3.CFGMAXREADREQ2 |
| CELL39.OUT14.TMIN | PCIE3.CFGFUNCTIONSTATUS0 |
| CELL39.OUT15.TMIN | PCIE3.CFGFUNCTIONSTATUS1 |
| CELL39.OUT16.TMIN | PCIE3.CFGINTERRUPTMSIDATA20 |
| CELL39.OUT17.TMIN | PCIE3.CFGINTERRUPTMSIDATA21 |
| CELL39.OUT18.TMIN | PCIE3.CFGINTERRUPTMSIDATA22 |
| CELL39.OUT19.TMIN | PCIE3.CFGINTERRUPTMSIDATA23 |
| CELL39.OUT20.TMIN | PCIE3.CFGINTERRUPTMSIXVFMASK1 |
| CELL39.OUT21.TMIN | PCIE3.CFGINTERRUPTMSIXVFMASK2 |
| CELL39.OUT22.TMIN | PCIE3.CFGINTERRUPTMSIXVFMASK3 |
| CELL39.OUT23.TMIN | PCIE3.CFGINTERRUPTMSIXVFMASK4 |
| CELL40.IMUX.IMUX0.DELAY | PCIE3.MIREPLAYRAMREADDATA20 |
| CELL40.IMUX.IMUX1.DELAY | PCIE3.MIREPLAYRAMREADDATA21 |
| CELL40.IMUX.IMUX2.DELAY | PCIE3.MIREPLAYRAMREADDATA22 |
| CELL40.IMUX.IMUX3.DELAY | PCIE3.MIREPLAYRAMREADDATA23 |
| CELL40.IMUX.IMUX4.DELAY | PCIE3.MIREPLAYRAMREADDATA24 |
| CELL40.IMUX.IMUX5.DELAY | PCIE3.MIREPLAYRAMREADDATA25 |
| CELL40.IMUX.IMUX6.DELAY | PCIE3.MIREPLAYRAMREADDATA26 |
| CELL40.IMUX.IMUX7.DELAY | PCIE3.MIREPLAYRAMREADDATA27 |
| CELL40.IMUX.IMUX8.DELAY | PCIE3.MIREPLAYRAMREADDATA28 |
| CELL40.IMUX.IMUX9.DELAY | PCIE3.MIREPLAYRAMREADDATA29 |
| CELL40.IMUX.IMUX10.DELAY | PCIE3.MIREPLAYRAMREADDATA30 |
| CELL40.IMUX.IMUX11.DELAY | PCIE3.MIREPLAYRAMREADDATA31 |
| CELL40.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTDATA160 |
| CELL40.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTDATA161 |
| CELL40.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTDATA162 |
| CELL40.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTDATA163 |
| CELL40.IMUX.IMUX16.DELAY | PCIE3.SAXISRQTDATA232 |
| CELL40.IMUX.IMUX17.DELAY | PCIE3.SAXISRQTDATA233 |
| CELL40.IMUX.IMUX18.DELAY | PCIE3.SAXISRQTDATA234 |
| CELL40.IMUX.IMUX19.DELAY | PCIE3.SAXISRQTDATA235 |
| CELL40.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS37 |
| CELL40.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS38 |
| CELL40.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS39 |
| CELL40.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS40 |
| CELL40.IMUX.IMUX24.DELAY | PCIE3.CFGINTERRUPTMSIXDATA29 |
| CELL40.IMUX.IMUX25.DELAY | PCIE3.CFGINTERRUPTMSIXDATA30 |
| CELL40.OUT0.TMIN | PCIE3.MAXISRCTDATA144 |
| CELL40.OUT1.TMIN | PCIE3.MIREPLAYRAMWRITEDATA13 |
| CELL40.OUT2.TMIN | PCIE3.MIREPLAYRAMWRITEDATA1 |
| CELL40.OUT3.TMIN | PCIE3.MIREPLAYRAMWRITEDATA11 |
| CELL40.OUT4.TMIN | PCIE3.MIREPLAYRAMWRITEDATA3 |
| CELL40.OUT5.TMIN | PCIE3.MIREPLAYRAMWRITEDATA6 |
| CELL40.OUT6.TMIN | PCIE3.MIREPLAYRAMWRITEDATA12 |
| CELL40.OUT7.TMIN | PCIE3.MIREPLAYRAMWRITEDATA9 |
| CELL40.OUT8.TMIN | PCIE3.MAXISRCTDATA145 |
| CELL40.OUT9.TMIN | PCIE3.MAXISRCTDATA146 |
| CELL40.OUT10.TMIN | PCIE3.MAXISRCTDATA147 |
| CELL40.OUT11.TMIN | PCIE3.MAXISRCTDATA199 |
| CELL40.OUT12.TMIN | PCIE3.MAXISRCTDATA200 |
| CELL40.OUT13.TMIN | PCIE3.MAXISRCTDATA201 |
| CELL40.OUT14.TMIN | PCIE3.MAXISRCTDATA202 |
| CELL40.OUT15.TMIN | PCIE3.CFGINTERRUPTMSIDATA24 |
| CELL40.OUT16.TMIN | PCIE3.MIREPLAYRAMWRITEDATA33 |
| CELL40.OUT17.TMIN | PCIE3.MIREPLAYRAMWRITEDATA30 |
| CELL40.OUT18.TMIN | PCIE3.MIREPLAYRAMWRITEDATA26 |
| CELL40.OUT19.TMIN | PCIE3.MIREPLAYRAMWRITEDATA32 |
| CELL40.OUT20.TMIN | PCIE3.MIREPLAYRAMWRITEDATA38 |
| CELL40.OUT21.TMIN | PCIE3.MIREPLAYRAMWRITEDATA31 |
| CELL40.OUT22.TMIN | PCIE3.CFGINTERRUPTMSIXVFMASK0 |
| CELL40.OUT23.TMIN | PCIE3.MIREPLAYRAMWRITEDATA20 |
| CELL41.IMUX.IMUX0.DELAY | PCIE3.MIREPLAYRAMREADDATA32 |
| CELL41.IMUX.IMUX1.DELAY | PCIE3.MIREPLAYRAMREADDATA33 |
| CELL41.IMUX.IMUX2.DELAY | PCIE3.MIREPLAYRAMREADDATA34 |
| CELL41.IMUX.IMUX3.DELAY | PCIE3.MIREPLAYRAMREADDATA35 |
| CELL41.IMUX.IMUX4.DELAY | PCIE3.MIREPLAYRAMREADDATA36 |
| CELL41.IMUX.IMUX5.DELAY | PCIE3.MIREPLAYRAMREADDATA37 |
| CELL41.IMUX.IMUX6.DELAY | PCIE3.MIREPLAYRAMREADDATA38 |
| CELL41.IMUX.IMUX7.DELAY | PCIE3.MIREPLAYRAMREADDATA39 |
| CELL41.IMUX.IMUX8.DELAY | PCIE3.MIREPLAYRAMREADDATA40 |
| CELL41.IMUX.IMUX9.DELAY | PCIE3.MIREPLAYRAMREADDATA41 |
| CELL41.IMUX.IMUX10.DELAY | PCIE3.MIREPLAYRAMREADDATA42 |
| CELL41.IMUX.IMUX11.DELAY | PCIE3.MIREPLAYRAMREADDATA43 |
| CELL41.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTDATA164 |
| CELL41.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTDATA165 |
| CELL41.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTDATA166 |
| CELL41.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTDATA167 |
| CELL41.IMUX.IMUX16.DELAY | PCIE3.SAXISRQTDATA228 |
| CELL41.IMUX.IMUX17.DELAY | PCIE3.SAXISRQTDATA229 |
| CELL41.IMUX.IMUX18.DELAY | PCIE3.SAXISRQTDATA230 |
| CELL41.IMUX.IMUX19.DELAY | PCIE3.SAXISRQTDATA231 |
| CELL41.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS41 |
| CELL41.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS42 |
| CELL41.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS43 |
| CELL41.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS44 |
| CELL41.IMUX.IMUX24.DELAY | PCIE3.CFGINTERRUPTMSIXDATA27 |
| CELL41.IMUX.IMUX25.DELAY | PCIE3.CFGINTERRUPTMSIXDATA28 |
| CELL41.OUT0.TMIN | PCIE3.MIREPLAYRAMWRITEDATA4 |
| CELL41.OUT1.TMIN | PCIE3.MIREPLAYRAMWRITEDATA15 |
| CELL41.OUT2.TMIN | PCIE3.MIREPLAYRAMWRITEDATA18 |
| CELL41.OUT3.TMIN | PCIE3.MIREPLAYRAMWRITEDATA29 |
| CELL41.OUT4.TMIN | PCIE3.MIREPLAYRAMWRITEDATA21 |
| CELL41.OUT5.TMIN | PCIE3.MIREPLAYRAMWRITEDATA22 |
| CELL41.OUT6.TMIN | PCIE3.MAXISRCTDATA148 |
| CELL41.OUT7.TMIN | PCIE3.MIREPLAYRAMWRITEDATA24 |
| CELL41.OUT8.TMIN | PCIE3.MIREPLAYRAMWRITEDATA5 |
| CELL41.OUT9.TMIN | PCIE3.MIREPLAYRAMWRITEDATA0 |
| CELL41.OUT10.TMIN | PCIE3.MIREPLAYRAMWRITEDATA36 |
| CELL41.OUT11.TMIN | PCIE3.MAXISRCTDATA149 |
| CELL41.OUT12.TMIN | PCIE3.MIREPLAYRAMWRITEDATA47 |
| CELL41.OUT13.TMIN | PCIE3.MIREPLAYRAMWRITEDATA17 |
| CELL41.OUT14.TMIN | PCIE3.MAXISRCTDATA150 |
| CELL41.OUT15.TMIN | PCIE3.MAXISRCTDATA151 |
| CELL41.OUT16.TMIN | PCIE3.MIREPLAYRAMWRITEDATA8 |
| CELL41.OUT17.TMIN | PCIE3.MIREPLAYRAMWRITEDATA7 |
| CELL41.OUT18.TMIN | PCIE3.MIREPLAYRAMWRITEDATA37 |
| CELL41.OUT19.TMIN | PCIE3.MIREPLAYRAMWRITEDATA2 |
| CELL41.OUT20.TMIN | PCIE3.MAXISRCTDATA198 |
| CELL41.OUT21.TMIN | PCIE3.CFGINTERRUPTMSIDATA25 |
| CELL41.OUT22.TMIN | PCIE3.MIREPLAYRAMWRITEDATA53 |
| CELL41.OUT23.TMIN | PCIE3.CFGINTERRUPTMSIXVFENABLE5 |
| CELL42.IMUX.IMUX0.DELAY | PCIE3.MIREPLAYRAMREADDATA44 |
| CELL42.IMUX.IMUX1.DELAY | PCIE3.MIREPLAYRAMREADDATA45 |
| CELL42.IMUX.IMUX2.DELAY | PCIE3.MIREPLAYRAMREADDATA46 |
| CELL42.IMUX.IMUX3.DELAY | PCIE3.MIREPLAYRAMREADDATA47 |
| CELL42.IMUX.IMUX4.DELAY | PCIE3.MIREPLAYRAMREADDATA48 |
| CELL42.IMUX.IMUX5.DELAY | PCIE3.MIREPLAYRAMREADDATA49 |
| CELL42.IMUX.IMUX6.DELAY | PCIE3.MIREPLAYRAMREADDATA50 |
| CELL42.IMUX.IMUX7.DELAY | PCIE3.MIREPLAYRAMREADDATA51 |
| CELL42.IMUX.IMUX8.DELAY | PCIE3.MIREPLAYRAMREADDATA52 |
| CELL42.IMUX.IMUX9.DELAY | PCIE3.MIREPLAYRAMREADDATA53 |
| CELL42.IMUX.IMUX10.DELAY | PCIE3.MIREPLAYRAMREADDATA54 |
| CELL42.IMUX.IMUX11.DELAY | PCIE3.MIREPLAYRAMREADDATA55 |
| CELL42.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTDATA168 |
| CELL42.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTDATA169 |
| CELL42.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTDATA170 |
| CELL42.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTDATA171 |
| CELL42.IMUX.IMUX16.DELAY | PCIE3.SAXISRQTDATA224 |
| CELL42.IMUX.IMUX17.DELAY | PCIE3.SAXISRQTDATA225 |
| CELL42.IMUX.IMUX18.DELAY | PCIE3.SAXISRQTDATA226 |
| CELL42.IMUX.IMUX19.DELAY | PCIE3.SAXISRQTDATA227 |
| CELL42.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS45 |
| CELL42.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS46 |
| CELL42.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS47 |
| CELL42.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS48 |
| CELL42.IMUX.IMUX24.DELAY | PCIE3.CFGINTERRUPTMSIXDATA25 |
| CELL42.IMUX.IMUX25.DELAY | PCIE3.CFGINTERRUPTMSIXDATA26 |
| CELL42.OUT0.TMIN | PCIE3.MIREPLAYRAMREADENABLE0 |
| CELL42.OUT1.TMIN | PCIE3.MIREPLAYRAMWRITEDATA56 |
| CELL42.OUT2.TMIN | PCIE3.MAXISRCTDATA152 |
| CELL42.OUT3.TMIN | PCIE3.MIREPLAYRAMWRITEDATA67 |
| CELL42.OUT4.TMIN | PCIE3.MAXISRCTDATA153 |
| CELL42.OUT5.TMIN | PCIE3.MAXISRCTDATA154 |
| CELL42.OUT6.TMIN | PCIE3.MIREPLAYRAMWRITEENABLE0 |
| CELL42.OUT7.TMIN | PCIE3.MIREPLAYRAMWRITEDATA14 |
| CELL42.OUT8.TMIN | PCIE3.MIREPLAYRAMWRITEDATA43 |
| CELL42.OUT9.TMIN | PCIE3.MIREPLAYRAMWRITEDATA35 |
| CELL42.OUT10.TMIN | PCIE3.MAXISRCTDATA155 |
| CELL42.OUT11.TMIN | PCIE3.MAXISRCTDATA194 |
| CELL42.OUT12.TMIN | PCIE3.MAXISRCTDATA195 |
| CELL42.OUT13.TMIN | PCIE3.MIREPLAYRAMWRITEDATA61 |
| CELL42.OUT14.TMIN | PCIE3.MIREPLAYRAMWRITEDATA27 |
| CELL42.OUT15.TMIN | PCIE3.MIREPLAYRAMWRITEDATA41 |
| CELL42.OUT16.TMIN | PCIE3.MAXISRCTDATA196 |
| CELL42.OUT17.TMIN | PCIE3.MAXISRCTDATA197 |
| CELL42.OUT18.TMIN | PCIE3.MIREPLAYRAMWRITEDATA19 |
| CELL42.OUT19.TMIN | PCIE3.MIREPLAYRAMWRITEDATA42 |
| CELL42.OUT20.TMIN | PCIE3.CFGMAXPAYLOAD0 |
| CELL42.OUT21.TMIN | PCIE3.CFGINTERRUPTMSIDATA26 |
| CELL42.OUT22.TMIN | PCIE3.MIREPLAYRAMWRITEDATA10 |
| CELL42.OUT23.TMIN | PCIE3.CFGINTERRUPTMSIXVFENABLE4 |
| CELL43.IMUX.IMUX0.DELAY | PCIE3.MIREPLAYRAMREADDATA56 |
| CELL43.IMUX.IMUX1.DELAY | PCIE3.MIREPLAYRAMREADDATA57 |
| CELL43.IMUX.IMUX2.DELAY | PCIE3.MIREPLAYRAMREADDATA58 |
| CELL43.IMUX.IMUX3.DELAY | PCIE3.MIREPLAYRAMREADDATA59 |
| CELL43.IMUX.IMUX4.DELAY | PCIE3.MIREPLAYRAMREADDATA60 |
| CELL43.IMUX.IMUX5.DELAY | PCIE3.MIREPLAYRAMREADDATA61 |
| CELL43.IMUX.IMUX6.DELAY | PCIE3.MIREPLAYRAMREADDATA62 |
| CELL43.IMUX.IMUX7.DELAY | PCIE3.MIREPLAYRAMREADDATA63 |
| CELL43.IMUX.IMUX8.DELAY | PCIE3.MIREPLAYRAMREADDATA64 |
| CELL43.IMUX.IMUX9.DELAY | PCIE3.MIREPLAYRAMREADDATA65 |
| CELL43.IMUX.IMUX10.DELAY | PCIE3.MIREPLAYRAMREADDATA66 |
| CELL43.IMUX.IMUX11.DELAY | PCIE3.MIREPLAYRAMREADDATA67 |
| CELL43.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTDATA172 |
| CELL43.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTDATA173 |
| CELL43.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTDATA174 |
| CELL43.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTDATA175 |
| CELL43.IMUX.IMUX16.DELAY | PCIE3.SAXISRQTDATA220 |
| CELL43.IMUX.IMUX17.DELAY | PCIE3.SAXISRQTDATA221 |
| CELL43.IMUX.IMUX18.DELAY | PCIE3.SAXISRQTDATA222 |
| CELL43.IMUX.IMUX19.DELAY | PCIE3.SAXISRQTDATA223 |
| CELL43.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS49 |
| CELL43.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS50 |
| CELL43.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS51 |
| CELL43.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS52 |
| CELL43.IMUX.IMUX24.DELAY | PCIE3.CFGINTERRUPTMSIXDATA23 |
| CELL43.IMUX.IMUX25.DELAY | PCIE3.CFGINTERRUPTMSIXDATA24 |
| CELL43.OUT0.TMIN | PCIE3.MAXISRCTDATA156 |
| CELL43.OUT1.TMIN | PCIE3.MIREPLAYRAMWRITEDATA28 |
| CELL43.OUT2.TMIN | PCIE3.MIREPLAYRAMWRITEDATA50 |
| CELL43.OUT3.TMIN | PCIE3.MIREPLAYRAMWRITEDATA60 |
| CELL43.OUT4.TMIN | PCIE3.MAXISRCTDATA157 |
| CELL43.OUT5.TMIN | PCIE3.MAXISRCTDATA158 |
| CELL43.OUT6.TMIN | PCIE3.MIREPLAYRAMWRITEDATA58 |
| CELL43.OUT7.TMIN | PCIE3.MAXISRCTDATA159 |
| CELL43.OUT8.TMIN | PCIE3.MIREPLAYRAMWRITEDATA55 |
| CELL43.OUT9.TMIN | PCIE3.MIREPLAYRAMWRITEDATA63 |
| CELL43.OUT10.TMIN | PCIE3.MAXISRCTDATA190 |
| CELL43.OUT11.TMIN | PCIE3.MAXISRCTDATA191 |
| CELL43.OUT12.TMIN | PCIE3.MAXISRCTDATA192 |
| CELL43.OUT13.TMIN | PCIE3.MIREPLAYRAMWRITEDATA51 |
| CELL43.OUT14.TMIN | PCIE3.MIREPLAYRAMWRITEDATA39 |
| CELL43.OUT15.TMIN | PCIE3.MIREPLAYRAMWRITEDATA52 |
| CELL43.OUT16.TMIN | PCIE3.MIREPLAYRAMWRITEDATA84 |
| CELL43.OUT17.TMIN | PCIE3.MAXISRCTDATA193 |
| CELL43.OUT18.TMIN | PCIE3.MIREPLAYRAMWRITEDATA65 |
| CELL43.OUT19.TMIN | PCIE3.MIREPLAYRAMWRITEDATA40 |
| CELL43.OUT20.TMIN | PCIE3.CFGINTERRUPTMSIDATA27 |
| CELL43.OUT21.TMIN | PCIE3.XILUNCONNOUT16 |
| CELL43.OUT22.TMIN | PCIE3.MIREPLAYRAMWRITEDATA44 |
| CELL43.OUT23.TMIN | PCIE3.MIREPLAYRAMWRITEDATA77 |
| CELL44.IMUX.IMUX0.DELAY | PCIE3.MIREPLAYRAMREADDATA68 |
| CELL44.IMUX.IMUX1.DELAY | PCIE3.MIREPLAYRAMREADDATA69 |
| CELL44.IMUX.IMUX2.DELAY | PCIE3.MIREPLAYRAMREADDATA70 |
| CELL44.IMUX.IMUX3.DELAY | PCIE3.MIREPLAYRAMREADDATA71 |
| CELL44.IMUX.IMUX4.DELAY | PCIE3.MIREPLAYRAMREADDATA72 |
| CELL44.IMUX.IMUX5.DELAY | PCIE3.MIREPLAYRAMREADDATA73 |
| CELL44.IMUX.IMUX6.DELAY | PCIE3.MIREPLAYRAMREADDATA74 |
| CELL44.IMUX.IMUX7.DELAY | PCIE3.MIREPLAYRAMREADDATA75 |
| CELL44.IMUX.IMUX8.DELAY | PCIE3.MIREPLAYRAMREADDATA76 |
| CELL44.IMUX.IMUX9.DELAY | PCIE3.MIREPLAYRAMREADDATA77 |
| CELL44.IMUX.IMUX10.DELAY | PCIE3.MIREPLAYRAMREADDATA78 |
| CELL44.IMUX.IMUX11.DELAY | PCIE3.MIREPLAYRAMREADDATA79 |
| CELL44.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTDATA176 |
| CELL44.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTDATA177 |
| CELL44.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTDATA178 |
| CELL44.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTDATA179 |
| CELL44.IMUX.IMUX16.DELAY | PCIE3.SAXISRQTDATA216 |
| CELL44.IMUX.IMUX17.DELAY | PCIE3.SAXISRQTDATA217 |
| CELL44.IMUX.IMUX18.DELAY | PCIE3.SAXISRQTDATA218 |
| CELL44.IMUX.IMUX19.DELAY | PCIE3.SAXISRQTDATA219 |
| CELL44.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS53 |
| CELL44.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS54 |
| CELL44.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS55 |
| CELL44.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS56 |
| CELL44.IMUX.IMUX24.DELAY | PCIE3.CFGINTERRUPTMSIXDATA21 |
| CELL44.IMUX.IMUX25.DELAY | PCIE3.CFGINTERRUPTMSIXDATA22 |
| CELL44.OUT0.TMIN | PCIE3.MIREPLAYRAMWRITEDATA25 |
| CELL44.OUT1.TMIN | PCIE3.MIREPLAYRAMWRITEDATA59 |
| CELL44.OUT2.TMIN | PCIE3.MIREPLAYRAMWRITEDATA16 |
| CELL44.OUT3.TMIN | PCIE3.MIREPLAYRAMWRITEDATA48 |
| CELL44.OUT4.TMIN | PCIE3.MIREPLAYRAMWRITEDATA62 |
| CELL44.OUT5.TMIN | PCIE3.MAXISRCTDATA160 |
| CELL44.OUT6.TMIN | PCIE3.MIREPLAYRAMADDRESS2 |
| CELL44.OUT7.TMIN | PCIE3.MIREPLAYRAMWRITEDATA45 |
| CELL44.OUT8.TMIN | PCIE3.MIREPLAYRAMADDRESS7 |
| CELL44.OUT9.TMIN | PCIE3.MAXISRCTDATA161 |
| CELL44.OUT10.TMIN | PCIE3.MIREPLAYRAMWRITEDATA66 |
| CELL44.OUT11.TMIN | PCIE3.MIREPLAYRAMWRITEDATA34 |
| CELL44.OUT12.TMIN | PCIE3.MAXISRCTDATA162 |
| CELL44.OUT13.TMIN | PCIE3.MIREPLAYRAMWRITEDATA54 |
| CELL44.OUT14.TMIN | PCIE3.MIREPLAYRAMWRITEDATA68 |
| CELL44.OUT15.TMIN | PCIE3.MIREPLAYRAMWRITEDATA57 |
| CELL44.OUT16.TMIN | PCIE3.CFGINTERRUPTMSIDATA28 |
| CELL44.OUT17.TMIN | PCIE3.MIREPLAYRAMWRITEDATA23 |
| CELL44.OUT18.TMIN | PCIE3.MIREPLAYRAMWRITEDATA46 |
| CELL44.OUT19.TMIN | PCIE3.CFGINTERRUPTMSIXVFENABLE3 |
| CELL44.OUT20.TMIN | PCIE3.MIREPLAYRAMWRITEDATA49 |
| CELL44.OUT21.TMIN | PCIE3.MIREPLAYRAMWRITEDATA71 |
| CELL44.OUT22.TMIN | PCIE3.MIREPLAYRAMWRITEDATA64 |
| CELL44.OUT23.TMIN | PCIE3.MIREPLAYRAMADDRESS1 |
| CELL45.IMUX.CLK0 | PCIE3.CORECLKMIREPLAYRAM |
| CELL45.IMUX.IMUX0.DELAY | PCIE3.MIREPLAYRAMREADDATA80 |
| CELL45.IMUX.IMUX1.DELAY | PCIE3.MIREPLAYRAMREADDATA81 |
| CELL45.IMUX.IMUX2.DELAY | PCIE3.MIREPLAYRAMREADDATA82 |
| CELL45.IMUX.IMUX3.DELAY | PCIE3.MIREPLAYRAMREADDATA83 |
| CELL45.IMUX.IMUX4.DELAY | PCIE3.MIREPLAYRAMREADDATA84 |
| CELL45.IMUX.IMUX5.DELAY | PCIE3.MIREPLAYRAMREADDATA85 |
| CELL45.IMUX.IMUX6.DELAY | PCIE3.MIREPLAYRAMREADDATA86 |
| CELL45.IMUX.IMUX7.DELAY | PCIE3.MIREPLAYRAMREADDATA87 |
| CELL45.IMUX.IMUX8.DELAY | PCIE3.MIREPLAYRAMREADDATA88 |
| CELL45.IMUX.IMUX9.DELAY | PCIE3.MIREPLAYRAMREADDATA89 |
| CELL45.IMUX.IMUX10.DELAY | PCIE3.MIREPLAYRAMREADDATA90 |
| CELL45.IMUX.IMUX11.DELAY | PCIE3.MIREPLAYRAMREADDATA91 |
| CELL45.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTDATA180 |
| CELL45.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTDATA181 |
| CELL45.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTDATA182 |
| CELL45.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTDATA183 |
| CELL45.IMUX.IMUX16.DELAY | PCIE3.SAXISRQTDATA212 |
| CELL45.IMUX.IMUX17.DELAY | PCIE3.SAXISRQTDATA213 |
| CELL45.IMUX.IMUX18.DELAY | PCIE3.SAXISRQTDATA214 |
| CELL45.IMUX.IMUX19.DELAY | PCIE3.SAXISRQTDATA215 |
| CELL45.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS57 |
| CELL45.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS58 |
| CELL45.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS59 |
| CELL45.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS60 |
| CELL45.IMUX.IMUX24.DELAY | PCIE3.CFGINTERRUPTMSIXDATA19 |
| CELL45.IMUX.IMUX25.DELAY | PCIE3.CFGINTERRUPTMSIXDATA20 |
| CELL45.OUT0.TMIN | PCIE3.MAXISRCTDATA163 |
| CELL45.OUT1.TMIN | PCIE3.MAXISRCTDATA164 |
| CELL45.OUT2.TMIN | PCIE3.MIREPLAYRAMWRITEDATA100 |
| CELL45.OUT3.TMIN | PCIE3.MIREPLAYRAMWRITEDATA91 |
| CELL45.OUT4.TMIN | PCIE3.MIREPLAYRAMWRITEDATA76 |
| CELL45.OUT5.TMIN | PCIE3.MIREPLAYRAMWRITEDATA87 |
| CELL45.OUT6.TMIN | PCIE3.MAXISRCTDATA165 |
| CELL45.OUT7.TMIN | PCIE3.MAXISRCTDATA166 |
| CELL45.OUT8.TMIN | PCIE3.MIREPLAYRAMADDRESS5 |
| CELL45.OUT9.TMIN | PCIE3.MIREPLAYRAMWRITEDATA72 |
| CELL45.OUT10.TMIN | PCIE3.MIREPLAYRAMWRITEDATA80 |
| CELL45.OUT11.TMIN | PCIE3.MIREPLAYRAMADDRESS6 |
| CELL45.OUT12.TMIN | PCIE3.MAXISRCTDATA189 |
| CELL45.OUT13.TMIN | PCIE3.MIREPLAYRAMWRITEDATA104 |
| CELL45.OUT14.TMIN | PCIE3.MIREPLAYRAMWRITEDATA89 |
| CELL45.OUT15.TMIN | PCIE3.MIREPLAYRAMADDRESS3 |
| CELL45.OUT16.TMIN | PCIE3.MIREPLAYRAMWRITEDATA85 |
| CELL45.OUT17.TMIN | PCIE3.CFGINTERRUPTMSIDATA29 |
| CELL45.OUT18.TMIN | PCIE3.MIREPLAYRAMWRITEDATA109 |
| CELL45.OUT19.TMIN | PCIE3.MIREPLAYRAMWRITEDATA96 |
| CELL45.OUT20.TMIN | PCIE3.MIREPLAYRAMWRITEDATA78 |
| CELL45.OUT21.TMIN | PCIE3.MIREPLAYRAMWRITEDATA97 |
| CELL45.OUT22.TMIN | PCIE3.CFGINTERRUPTMSIXVFENABLE2 |
| CELL45.OUT23.TMIN | PCIE3.MIREPLAYRAMWRITEDATA74 |
| CELL46.IMUX.IMUX0.DELAY | PCIE3.MIREPLAYRAMREADDATA92 |
| CELL46.IMUX.IMUX1.DELAY | PCIE3.MIREPLAYRAMREADDATA93 |
| CELL46.IMUX.IMUX2.DELAY | PCIE3.MIREPLAYRAMREADDATA94 |
| CELL46.IMUX.IMUX3.DELAY | PCIE3.MIREPLAYRAMREADDATA95 |
| CELL46.IMUX.IMUX4.DELAY | PCIE3.MIREPLAYRAMREADDATA96 |
| CELL46.IMUX.IMUX5.DELAY | PCIE3.MIREPLAYRAMREADDATA97 |
| CELL46.IMUX.IMUX6.DELAY | PCIE3.MIREPLAYRAMREADDATA98 |
| CELL46.IMUX.IMUX7.DELAY | PCIE3.MIREPLAYRAMREADDATA99 |
| CELL46.IMUX.IMUX8.DELAY | PCIE3.MIREPLAYRAMREADDATA100 |
| CELL46.IMUX.IMUX9.DELAY | PCIE3.MIREPLAYRAMREADDATA101 |
| CELL46.IMUX.IMUX10.DELAY | PCIE3.MIREPLAYRAMREADDATA102 |
| CELL46.IMUX.IMUX11.DELAY | PCIE3.MIREPLAYRAMREADDATA103 |
| CELL46.IMUX.IMUX12.DELAY | PCIE3.SAXISRQTDATA184 |
| CELL46.IMUX.IMUX13.DELAY | PCIE3.SAXISRQTDATA185 |
| CELL46.IMUX.IMUX14.DELAY | PCIE3.SAXISRQTDATA186 |
| CELL46.IMUX.IMUX15.DELAY | PCIE3.SAXISRQTDATA187 |
| CELL46.IMUX.IMUX16.DELAY | PCIE3.SAXISRQTDATA208 |
| CELL46.IMUX.IMUX17.DELAY | PCIE3.SAXISRQTDATA209 |
| CELL46.IMUX.IMUX18.DELAY | PCIE3.SAXISRQTDATA210 |
| CELL46.IMUX.IMUX19.DELAY | PCIE3.SAXISRQTDATA211 |
| CELL46.IMUX.IMUX20.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS61 |
| CELL46.IMUX.IMUX21.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS62 |
| CELL46.IMUX.IMUX22.DELAY | PCIE3.CFGINTERRUPTMSIXADDRESS63 |
| CELL46.IMUX.IMUX23.DELAY | PCIE3.CFGINTERRUPTMSIXDATA0 |
| CELL46.IMUX.IMUX24.DELAY | PCIE3.CFGINTERRUPTMSIXDATA17 |
| CELL46.IMUX.IMUX25.DELAY | PCIE3.CFGINTERRUPTMSIXDATA18 |
| CELL46.OUT0.TMIN | PCIE3.MIREPLAYRAMWRITEDATA75 |
| CELL46.OUT1.TMIN | PCIE3.MIREPLAYRAMADDRESS4 |
| CELL46.OUT2.TMIN | PCIE3.MAXISRCTDATA167 |
| CELL46.OUT3.TMIN | PCIE3.MIREPLAYRAMWRITEDATA112 |
| CELL46.OUT4.TMIN | PCIE3.MIREPLAYRAMWRITEDATA93 |
| CELL46.OUT5.TMIN | PCIE3.MIREPLAYRAMWRITEDATA70 |
| CELL46.OUT6.TMIN | PCIE3.MIREPLAYRAMWRITEDATA101 |
| CELL46.OUT7.TMIN | PCIE3.MIREPLAYRAMADDRESS8 |
| CELL46.OUT8.TMIN | PCIE3.MIREPLAYRAMWRITEDATA90 |
| CELL46.OUT9.TMIN | PCIE3.MAXISRCTDATA168 |
| CELL46.OUT10.TMIN | PCIE3.MIREPLAYRAMWRITEDATA73 |
| CELL46.OUT11.TMIN | PCIE3.MIREPLAYRAMWRITEDATA88 |
| CELL46.OUT12.TMIN | PCIE3.MIREPLAYRAMWRITEDATA114 |
| CELL46.OUT13.TMIN | PCIE3.MIREPLAYRAMADDRESS0 |
| CELL46.OUT14.TMIN | PCIE3.MIREPLAYRAMWRITEDATA98 |
| CELL46.OUT15.TMIN | PCIE3.MIREPLAYRAMWRITEDATA79 |
| CELL46.OUT16.TMIN | PCIE3.CFGINTERRUPTMSIDATA30 |
| CELL46.OUT17.TMIN | PCIE3.MIREPLAYRAMWRITEDATA105 |
| CELL46.OUT18.TMIN | PCIE3.MIREPLAYRAMWRITEDATA103 |
| CELL46.OUT19.TMIN | PCIE3.MIREPLAYRAMWRITEDATA81 |
| CELL46.OUT20.TMIN | PCIE3.CFGINTERRUPTMSIXVFENABLE1 |
| CELL46.OUT21.TMIN | PCIE3.MIREPLAYRAMWRITEDATA83 |
| CELL46.OUT22.TMIN | PCIE3.MIREPLAYRAMWRITEDATA137 |
| CELL46.OUT23.TMIN | PCIE3.MIREPLAYRAMWRITEDATA92 |
| CELL47.IMUX.IMUX0.DELAY | PCIE3.MIREPLAYRAMREADDATA104 |
| CELL47.IMUX.IMUX1.DELAY | PCIE3.MIREPLAYRAMREADDATA105 |
| CELL47.IMUX.IMUX2.DELAY | PCIE3.MIREPLAYRAMREADDATA106 |
| CELL47.IMUX.IMUX3.DELAY | PCIE3.MIREPLAYRAMREADDATA107 |
| CELL47.IMUX.IMUX4.DELAY | PCIE3.MIREPLAYRAMREADDATA108 |
| CELL47.IMUX.IMUX5.DELAY | PCIE3.MIREPLAYRAMREADDATA109 |
| CELL47.IMUX.IMUX6.DELAY | PCIE3.MIREPLAYRAMREADDATA110 |
| CELL47.IMUX.IMUX7.DELAY | PCIE3.MIREPLAYRAMREADDATA111 |
| CELL47.IMUX.IMUX8.DELAY | PCIE3.MIREPLAYRAMREADDATA112 |
| CELL47.IMUX.IMUX9.DELAY | PCIE3.MIREPLAYRAMREADDATA113 |
| CELL47.IMUX.IMUX10.DELAY | PCIE3.MIREPLAYRAMREADDATA114 |
| CELL47.IMUX.IMUX11.DELAY | PCIE3.MIREPLAYRAMREADDATA115 |
| CELL47.IMUX.IMUX12.DELAY | PCIE3.MIREPLAYRAMREADDATA116 |
| CELL47.IMUX.IMUX13.DELAY | PCIE3.MIREPLAYRAMREADDATA117 |
| CELL47.IMUX.IMUX14.DELAY | PCIE3.MIREPLAYRAMREADDATA118 |
| CELL47.IMUX.IMUX15.DELAY | PCIE3.MIREPLAYRAMREADDATA119 |
| CELL47.IMUX.IMUX16.DELAY | PCIE3.SAXISRQTDATA188 |
| CELL47.IMUX.IMUX17.DELAY | PCIE3.SAXISRQTDATA189 |
| CELL47.IMUX.IMUX18.DELAY | PCIE3.SAXISRQTDATA190 |
| CELL47.IMUX.IMUX19.DELAY | PCIE3.SAXISRQTDATA191 |
| CELL47.IMUX.IMUX20.DELAY | PCIE3.SAXISRQTDATA204 |
| CELL47.IMUX.IMUX21.DELAY | PCIE3.SAXISRQTDATA205 |
| CELL47.IMUX.IMUX22.DELAY | PCIE3.SAXISRQTDATA206 |
| CELL47.IMUX.IMUX23.DELAY | PCIE3.SAXISRQTDATA207 |
| CELL47.IMUX.IMUX24.DELAY | PCIE3.CFGINTERRUPTMSIXDATA1 |
| CELL47.IMUX.IMUX25.DELAY | PCIE3.CFGINTERRUPTMSIXDATA2 |
| CELL47.IMUX.IMUX26.DELAY | PCIE3.CFGINTERRUPTMSIXDATA3 |
| CELL47.IMUX.IMUX27.DELAY | PCIE3.CFGINTERRUPTMSIXDATA4 |
| CELL47.IMUX.IMUX28.DELAY | PCIE3.CFGINTERRUPTMSIXDATA15 |
| CELL47.IMUX.IMUX29.DELAY | PCIE3.CFGINTERRUPTMSIXDATA16 |
| CELL47.OUT0.TMIN | PCIE3.MIREPLAYRAMREADENABLE1 |
| CELL47.OUT1.TMIN | PCIE3.MIREPLAYRAMWRITEDATA133 |
| CELL47.OUT2.TMIN | PCIE3.MAXISRCTDATA169 |
| CELL47.OUT3.TMIN | PCIE3.MIREPLAYRAMWRITEDATA135 |
| CELL47.OUT4.TMIN | PCIE3.MAXISRCTDATA170 |
| CELL47.OUT5.TMIN | PCIE3.MAXISRCTDATA171 |
| CELL47.OUT6.TMIN | PCIE3.MIREPLAYRAMWRITEENABLE1 |
| CELL47.OUT7.TMIN | PCIE3.MAXISRCTDATA172 |
| CELL47.OUT8.TMIN | PCIE3.MIREPLAYRAMWRITEDATA102 |
| CELL47.OUT9.TMIN | PCIE3.MIREPLAYRAMWRITEDATA115 |
| CELL47.OUT10.TMIN | PCIE3.MAXISRCTDATA185 |
| CELL47.OUT11.TMIN | PCIE3.MAXISRCTDATA186 |
| CELL47.OUT12.TMIN | PCIE3.MIREPLAYRAMWRITEDATA94 |
| CELL47.OUT13.TMIN | PCIE3.MIREPLAYRAMWRITEDATA86 |
| CELL47.OUT14.TMIN | PCIE3.MIREPLAYRAMWRITEDATA108 |
| CELL47.OUT15.TMIN | PCIE3.MIREPLAYRAMWRITEDATA113 |
| CELL47.OUT16.TMIN | PCIE3.MAXISRCTDATA187 |
| CELL47.OUT17.TMIN | PCIE3.MAXISRCTDATA188 |
| CELL47.OUT18.TMIN | PCIE3.MIREPLAYRAMWRITEDATA69 |
| CELL47.OUT19.TMIN | PCIE3.MIREPLAYRAMWRITEDATA126 |
| CELL47.OUT20.TMIN | PCIE3.CFGMAXPAYLOAD1 |
| CELL47.OUT21.TMIN | PCIE3.CFGINTERRUPTMSIDATA31 |
| CELL47.OUT22.TMIN | PCIE3.MIREPLAYRAMWRITEDATA82 |
| CELL47.OUT23.TMIN | PCIE3.CFGINTERRUPTMSIXENABLE0 |
| CELL48.IMUX.IMUX0.DELAY | PCIE3.MIREPLAYRAMREADDATA120 |
| CELL48.IMUX.IMUX1.DELAY | PCIE3.MIREPLAYRAMREADDATA121 |
| CELL48.IMUX.IMUX2.DELAY | PCIE3.MIREPLAYRAMREADDATA122 |
| CELL48.IMUX.IMUX3.DELAY | PCIE3.MIREPLAYRAMREADDATA123 |
| CELL48.IMUX.IMUX4.DELAY | PCIE3.MIREPLAYRAMREADDATA124 |
| CELL48.IMUX.IMUX5.DELAY | PCIE3.MIREPLAYRAMREADDATA125 |
| CELL48.IMUX.IMUX6.DELAY | PCIE3.MIREPLAYRAMREADDATA126 |
| CELL48.IMUX.IMUX7.DELAY | PCIE3.MIREPLAYRAMREADDATA127 |
| CELL48.IMUX.IMUX8.DELAY | PCIE3.MIREPLAYRAMREADDATA128 |
| CELL48.IMUX.IMUX9.DELAY | PCIE3.MIREPLAYRAMREADDATA129 |
| CELL48.IMUX.IMUX10.DELAY | PCIE3.MIREPLAYRAMREADDATA130 |
| CELL48.IMUX.IMUX11.DELAY | PCIE3.MIREPLAYRAMREADDATA131 |
| CELL48.IMUX.IMUX12.DELAY | PCIE3.MIREPLAYRAMREADDATA132 |
| CELL48.IMUX.IMUX13.DELAY | PCIE3.MIREPLAYRAMREADDATA133 |
| CELL48.IMUX.IMUX14.DELAY | PCIE3.MIREPLAYRAMREADDATA134 |
| CELL48.IMUX.IMUX15.DELAY | PCIE3.MIREPLAYRAMREADDATA135 |
| CELL48.IMUX.IMUX16.DELAY | PCIE3.SAXISRQTDATA192 |
| CELL48.IMUX.IMUX17.DELAY | PCIE3.SAXISRQTDATA193 |
| CELL48.IMUX.IMUX18.DELAY | PCIE3.SAXISRQTDATA194 |
| CELL48.IMUX.IMUX19.DELAY | PCIE3.SAXISRQTDATA195 |
| CELL48.IMUX.IMUX20.DELAY | PCIE3.SAXISRQTDATA200 |
| CELL48.IMUX.IMUX21.DELAY | PCIE3.SAXISRQTDATA201 |
| CELL48.IMUX.IMUX22.DELAY | PCIE3.SAXISRQTDATA202 |
| CELL48.IMUX.IMUX23.DELAY | PCIE3.SAXISRQTDATA203 |
| CELL48.IMUX.IMUX24.DELAY | PCIE3.CFGINTERRUPTMSIXDATA5 |
| CELL48.IMUX.IMUX25.DELAY | PCIE3.CFGINTERRUPTMSIXDATA6 |
| CELL48.IMUX.IMUX26.DELAY | PCIE3.CFGINTERRUPTMSIXDATA7 |
| CELL48.IMUX.IMUX27.DELAY | PCIE3.CFGINTERRUPTMSIXDATA8 |
| CELL48.IMUX.IMUX28.DELAY | PCIE3.CFGINTERRUPTMSIXDATA13 |
| CELL48.IMUX.IMUX29.DELAY | PCIE3.CFGINTERRUPTMSIXDATA14 |
| CELL48.OUT0.TMIN | PCIE3.MAXISRCTDATA173 |
| CELL48.OUT1.TMIN | PCIE3.MIREPLAYRAMWRITEDATA107 |
| CELL48.OUT2.TMIN | PCIE3.MAXISRCTDATA174 |
| CELL48.OUT3.TMIN | PCIE3.MIREPLAYRAMWRITEDATA132 |
| CELL48.OUT4.TMIN | PCIE3.MAXISRCTDATA175 |
| CELL48.OUT5.TMIN | PCIE3.MIREPLAYRAMWRITEDATA139 |
| CELL48.OUT6.TMIN | PCIE3.MIREPLAYRAMWRITEDATA124 |
| CELL48.OUT7.TMIN | PCIE3.MAXISRCTDATA176 |
| CELL48.OUT8.TMIN | PCIE3.MIREPLAYRAMWRITEDATA125 |
| CELL48.OUT9.TMIN | PCIE3.MIREPLAYRAMWRITEDATA118 |
| CELL48.OUT10.TMIN | PCIE3.MAXISRCTDATA181 |
| CELL48.OUT11.TMIN | PCIE3.MAXISRCTDATA182 |
| CELL48.OUT12.TMIN | PCIE3.MAXISRCTDATA183 |
| CELL48.OUT13.TMIN | PCIE3.MIREPLAYRAMWRITEDATA128 |
| CELL48.OUT14.TMIN | PCIE3.MIREPLAYRAMWRITEDATA130 |
| CELL48.OUT15.TMIN | PCIE3.MIREPLAYRAMWRITEDATA127 |
| CELL48.OUT16.TMIN | PCIE3.MIREPLAYRAMWRITEDATA142 |
| CELL48.OUT17.TMIN | PCIE3.MIREPLAYRAMWRITEDATA121 |
| CELL48.OUT18.TMIN | PCIE3.MAXISRCTDATA184 |
| CELL48.OUT19.TMIN | PCIE3.MIREPLAYRAMWRITEDATA95 |
| CELL48.OUT20.TMIN | PCIE3.CFGINTERRUPTMSIXENABLE1 |
| CELL48.OUT21.TMIN | PCIE3.MIREPLAYRAMWRITEDATA141 |
| CELL48.OUT22.TMIN | PCIE3.MIREPLAYRAMWRITEDATA119 |
| CELL48.OUT23.TMIN | PCIE3.CFGINTERRUPTMSIXMASK0 |
| CELL49.IMUX.IMUX0.DELAY | PCIE3.MIREPLAYRAMREADDATA136 |
| CELL49.IMUX.IMUX1.DELAY | PCIE3.MIREPLAYRAMREADDATA137 |
| CELL49.IMUX.IMUX2.DELAY | PCIE3.MIREPLAYRAMREADDATA138 |
| CELL49.IMUX.IMUX3.DELAY | PCIE3.MIREPLAYRAMREADDATA139 |
| CELL49.IMUX.IMUX4.DELAY | PCIE3.MIREPLAYRAMREADDATA140 |
| CELL49.IMUX.IMUX5.DELAY | PCIE3.MIREPLAYRAMREADDATA141 |
| CELL49.IMUX.IMUX6.DELAY | PCIE3.MIREPLAYRAMREADDATA142 |
| CELL49.IMUX.IMUX7.DELAY | PCIE3.MIREPLAYRAMREADDATA143 |
| CELL49.IMUX.IMUX8.DELAY | PCIE3.SAXISRQTDATA196 |
| CELL49.IMUX.IMUX9.DELAY | PCIE3.SAXISRQTDATA197 |
| CELL49.IMUX.IMUX10.DELAY | PCIE3.SAXISRQTDATA198 |
| CELL49.IMUX.IMUX11.DELAY | PCIE3.SAXISRQTDATA199 |
| CELL49.IMUX.IMUX12.DELAY | PCIE3.CFGINTERRUPTMSIXDATA9 |
| CELL49.IMUX.IMUX13.DELAY | PCIE3.CFGINTERRUPTMSIXDATA10 |
| CELL49.IMUX.IMUX14.DELAY | PCIE3.CFGINTERRUPTMSIXDATA11 |
| CELL49.IMUX.IMUX15.DELAY | PCIE3.CFGINTERRUPTMSIXDATA12 |
| CELL49.OUT0.TMIN | PCIE3.MIREPLAYRAMWRITEDATA131 |
| CELL49.OUT1.TMIN | PCIE3.MIREPLAYRAMWRITEDATA138 |
| CELL49.OUT2.TMIN | PCIE3.MIREPLAYRAMWRITEDATA120 |
| CELL49.OUT3.TMIN | PCIE3.MIREPLAYRAMWRITEDATA143 |
| CELL49.OUT4.TMIN | PCIE3.MIREPLAYRAMWRITEDATA136 |
| CELL49.OUT5.TMIN | PCIE3.MIREPLAYRAMWRITEDATA110 |
| CELL49.OUT6.TMIN | PCIE3.MIREPLAYRAMWRITEDATA140 |
| CELL49.OUT7.TMIN | PCIE3.MIREPLAYRAMWRITEDATA122 |
| CELL49.OUT8.TMIN | PCIE3.MIREPLAYRAMWRITEDATA123 |
| CELL49.OUT9.TMIN | PCIE3.MIREPLAYRAMWRITEDATA106 |
| CELL49.OUT10.TMIN | PCIE3.MIREPLAYRAMWRITEDATA116 |
| CELL49.OUT11.TMIN | PCIE3.MIREPLAYRAMWRITEDATA117 |
| CELL49.OUT12.TMIN | PCIE3.MIREPLAYRAMWRITEDATA99 |
| CELL49.OUT13.TMIN | PCIE3.MIREPLAYRAMWRITEDATA111 |
| CELL49.OUT14.TMIN | PCIE3.MIREPLAYRAMWRITEDATA134 |
| CELL49.OUT15.TMIN | PCIE3.MIREPLAYRAMWRITEDATA129 |
| CELL49.OUT16.TMIN | PCIE3.MAXISRCTDATA177 |
| CELL49.OUT17.TMIN | PCIE3.MAXISRCTDATA178 |
| CELL49.OUT18.TMIN | PCIE3.MAXISRCTDATA179 |
| CELL49.OUT19.TMIN | PCIE3.MAXISRCTDATA180 |
| CELL49.OUT20.TMIN | PCIE3.CFGMAXPAYLOAD2 |
| CELL49.OUT21.TMIN | PCIE3.CFGMAXREADREQ0 |
| CELL49.OUT22.TMIN | PCIE3.CFGINTERRUPTMSIXMASK1 |
| CELL49.OUT23.TMIN | PCIE3.CFGINTERRUPTMSIXVFENABLE0 |
| CELL50.IMUX.IMUX0.DELAY | PCIE3.PIPERX0EQLPLFFSSEL |
| CELL50.IMUX.IMUX1.DELAY | PCIE3.PIPERX1EQLPLFFSSEL |
| CELL50.IMUX.IMUX2.DELAY | PCIE3.PIPERX2EQLPLFFSSEL |
| CELL50.IMUX.IMUX3.DELAY | PCIE3.PIPERX3EQLPLFFSSEL |
| CELL50.IMUX.IMUX4.DELAY | PCIE3.PIPERX4EQLPLFFSSEL |
| CELL50.IMUX.IMUX5.DELAY | PCIE3.PIPERX5EQLPLFFSSEL |
| CELL50.IMUX.IMUX6.DELAY | PCIE3.PIPERX6EQLPLFFSSEL |
| CELL50.IMUX.IMUX7.DELAY | PCIE3.PIPERX7EQLPLFFSSEL |
| CELL50.IMUX.IMUX8.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET0 |
| CELL50.IMUX.IMUX9.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET1 |
| CELL50.IMUX.IMUX10.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET2 |
| CELL50.IMUX.IMUX11.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET3 |
| CELL50.IMUX.IMUX12.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET4 |
| CELL50.IMUX.IMUX13.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET5 |
| CELL50.IMUX.IMUX14.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET6 |
| CELL50.IMUX.IMUX15.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET7 |
| CELL50.IMUX.IMUX16.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET8 |
| CELL50.IMUX.IMUX17.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET9 |
| CELL50.IMUX.IMUX18.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET10 |
| CELL50.IMUX.IMUX19.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET11 |
| CELL50.IMUX.IMUX20.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET12 |
| CELL50.IMUX.IMUX21.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET13 |
| CELL50.IMUX.IMUX22.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET14 |
| CELL50.IMUX.IMUX23.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET15 |
| CELL50.IMUX.IMUX24.DELAY | PCIE3.CFGFCSEL0 |
| CELL50.IMUX.IMUX25.DELAY | PCIE3.CFGFCSEL1 |
| CELL50.IMUX.IMUX26.DELAY | PCIE3.CFGFCSEL2 |
| CELL50.IMUX.IMUX27.DELAY | PCIE3.CFGPERFUNCSTATUSCONTROL0 |
| CELL50.IMUX.IMUX28.DELAY | PCIE3.CFGEXTREADDATA0 |
| CELL50.IMUX.IMUX29.DELAY | PCIE3.CFGEXTREADDATA1 |
| CELL50.OUT0.TMIN | PCIE3.PIPETX7DATA28 |
| CELL50.OUT1.TMIN | PCIE3.PIPERX0EQCONTROL0 |
| CELL50.OUT2.TMIN | PCIE3.PIPETX7DATA30 |
| CELL50.OUT3.TMIN | PCIE3.PIPERX0EQCONTROL1 |
| CELL50.OUT4.TMIN | PCIE3.PIPETX7DATA29 |
| CELL50.OUT5.TMIN | PCIE3.PIPERX1EQCONTROL0 |
| CELL50.OUT6.TMIN | PCIE3.PIPETX7DATA31 |
| CELL50.OUT7.TMIN | PCIE3.PIPERX1EQCONTROL1 |
| CELL50.OUT8.TMIN | PCIE3.PIPERX2EQCONTROL0 |
| CELL50.OUT9.TMIN | PCIE3.PIPERX2EQCONTROL1 |
| CELL50.OUT10.TMIN | PCIE3.PIPERX3EQCONTROL0 |
| CELL50.OUT11.TMIN | PCIE3.PIPERX3EQCONTROL1 |
| CELL50.OUT12.TMIN | PCIE3.PIPERX4EQCONTROL0 |
| CELL50.OUT13.TMIN | PCIE3.PIPERX4EQCONTROL1 |
| CELL50.OUT14.TMIN | PCIE3.PIPERX5EQCONTROL0 |
| CELL50.OUT15.TMIN | PCIE3.PIPERX5EQCONTROL1 |
| CELL50.OUT16.TMIN | PCIE3.PIPERX6EQCONTROL0 |
| CELL50.OUT17.TMIN | PCIE3.PIPERX6EQCONTROL1 |
| CELL50.OUT18.TMIN | PCIE3.PIPERX7EQCONTROL0 |
| CELL50.OUT19.TMIN | PCIE3.PIPERX7EQCONTROL1 |
| CELL50.OUT20.TMIN | PCIE3.PIPERX0EQPRESET0 |
| CELL50.OUT21.TMIN | PCIE3.PIPERX0EQPRESET1 |
| CELL50.OUT22.TMIN | PCIE3.CFGFCPH0 |
| CELL50.OUT23.TMIN | PCIE3.CFGFCPH1 |
| CELL51.IMUX.IMUX0.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET16 |
| CELL51.IMUX.IMUX1.DELAY | PCIE3.PIPERX0EQLPNEWTXCOEFFORPRESET17 |
| CELL51.IMUX.IMUX2.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET0 |
| CELL51.IMUX.IMUX3.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET1 |
| CELL51.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA69 |
| CELL51.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA70 |
| CELL51.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA71 |
| CELL51.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA72 |
| CELL51.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA73 |
| CELL51.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA74 |
| CELL51.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA75 |
| CELL51.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA76 |
| CELL51.IMUX.IMUX12.DELAY | PCIE3.SAXISCCTUSER0 |
| CELL51.IMUX.IMUX13.DELAY | PCIE3.SAXISCCTUSER1 |
| CELL51.IMUX.IMUX14.DELAY | PCIE3.SAXISCCTUSER2 |
| CELL51.IMUX.IMUX15.DELAY | PCIE3.SAXISCCTUSER3 |
| CELL51.IMUX.IMUX16.DELAY | PCIE3.SAXISCCTLAST |
| CELL51.IMUX.IMUX17.DELAY | PCIE3.SAXISCCTKEEP0 |
| CELL51.IMUX.IMUX18.DELAY | PCIE3.SAXISCCTKEEP1 |
| CELL51.IMUX.IMUX19.DELAY | PCIE3.SAXISCCTKEEP2 |
| CELL51.IMUX.IMUX20.DELAY | PCIE3.SAXISCCTVALID |
| CELL51.IMUX.IMUX21.DELAY | PCIE3.MAXISCQTREADY0 |
| CELL51.IMUX.IMUX22.DELAY | PCIE3.MAXISCQTREADY1 |
| CELL51.IMUX.IMUX23.DELAY | PCIE3.MAXISCQTREADY2 |
| CELL51.IMUX.IMUX24.DELAY | PCIE3.CFGPERFUNCSTATUSCONTROL1 |
| CELL51.IMUX.IMUX25.DELAY | PCIE3.CFGPERFUNCSTATUSCONTROL2 |
| CELL51.IMUX.IMUX26.DELAY | PCIE3.CFGEXTREADDATA2 |
| CELL51.IMUX.IMUX27.DELAY | PCIE3.CFGEXTREADDATA3 |
| CELL51.IMUX.IMUX28.DELAY | PCIE3.CFGEXTREADDATA4 |
| CELL51.IMUX.IMUX29.DELAY | PCIE3.CFGEXTREADDATA5 |
| CELL51.OUT0.TMIN | PCIE3.PIPETX6DATA28 |
| CELL51.OUT1.TMIN | PCIE3.PIPERX0EQPRESET2 |
| CELL51.OUT2.TMIN | PCIE3.PIPETX6DATA30 |
| CELL51.OUT3.TMIN | PCIE3.PIPERX1EQPRESET0 |
| CELL51.OUT4.TMIN | PCIE3.PIPETX6DATA29 |
| CELL51.OUT5.TMIN | PCIE3.PIPERX1EQPRESET1 |
| CELL51.OUT6.TMIN | PCIE3.PIPETX6DATA31 |
| CELL51.OUT7.TMIN | PCIE3.PIPERX1EQPRESET2 |
| CELL51.OUT8.TMIN | PCIE3.MAXISCQTDATA177 |
| CELL51.OUT9.TMIN | PCIE3.PIPETX7DATA24 |
| CELL51.OUT10.TMIN | PCIE3.MAXISCQTDATA178 |
| CELL51.OUT11.TMIN | PCIE3.PIPETX7DATA26 |
| CELL51.OUT12.TMIN | PCIE3.MAXISCQTDATA179 |
| CELL51.OUT13.TMIN | PCIE3.PIPETX7DATA25 |
| CELL51.OUT14.TMIN | PCIE3.MAXISCQTDATA180 |
| CELL51.OUT15.TMIN | PCIE3.PIPETX7DATA27 |
| CELL51.OUT16.TMIN | PCIE3.MAXISCQTDATA181 |
| CELL51.OUT17.TMIN | PCIE3.MAXISCQTDATA182 |
| CELL51.OUT18.TMIN | PCIE3.MAXISCQTDATA183 |
| CELL51.OUT19.TMIN | PCIE3.MAXISCQTDATA184 |
| CELL51.OUT20.TMIN | PCIE3.MAXISCQTUSER0 |
| CELL51.OUT21.TMIN | PCIE3.MAXISCQTUSER1 |
| CELL51.OUT22.TMIN | PCIE3.CFGFCPH2 |
| CELL51.OUT23.TMIN | PCIE3.CFGFCPH3 |
| CELL52.IMUX.IMUX0.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET2 |
| CELL52.IMUX.IMUX1.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET3 |
| CELL52.IMUX.IMUX2.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET4 |
| CELL52.IMUX.IMUX3.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET5 |
| CELL52.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA65 |
| CELL52.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA66 |
| CELL52.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA67 |
| CELL52.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA68 |
| CELL52.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA77 |
| CELL52.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA78 |
| CELL52.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA79 |
| CELL52.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA80 |
| CELL52.IMUX.IMUX12.DELAY | PCIE3.SAXISCCTUSER4 |
| CELL52.IMUX.IMUX13.DELAY | PCIE3.SAXISCCTUSER5 |
| CELL52.IMUX.IMUX14.DELAY | PCIE3.SAXISCCTUSER6 |
| CELL52.IMUX.IMUX15.DELAY | PCIE3.SAXISCCTUSER7 |
| CELL52.IMUX.IMUX16.DELAY | PCIE3.SAXISCCTKEEP3 |
| CELL52.IMUX.IMUX17.DELAY | PCIE3.SAXISCCTKEEP4 |
| CELL52.IMUX.IMUX18.DELAY | PCIE3.SAXISCCTKEEP5 |
| CELL52.IMUX.IMUX19.DELAY | PCIE3.SAXISCCTKEEP6 |
| CELL52.IMUX.IMUX20.DELAY | PCIE3.MAXISCQTREADY3 |
| CELL52.IMUX.IMUX21.DELAY | PCIE3.MAXISCQTREADY4 |
| CELL52.IMUX.IMUX22.DELAY | PCIE3.MAXISCQTREADY5 |
| CELL52.IMUX.IMUX23.DELAY | PCIE3.MAXISCQTREADY6 |
| CELL52.IMUX.IMUX24.DELAY | PCIE3.CFGEXTREADDATA6 |
| CELL52.IMUX.IMUX25.DELAY | PCIE3.CFGEXTREADDATA7 |
| CELL52.IMUX.IMUX26.DELAY | PCIE3.CFGEXTREADDATA8 |
| CELL52.IMUX.IMUX27.DELAY | PCIE3.CFGEXTREADDATA9 |
| CELL52.OUT0.TMIN | PCIE3.PIPETX7DATA20 |
| CELL52.OUT1.TMIN | PCIE3.PIPERX2EQPRESET0 |
| CELL52.OUT2.TMIN | PCIE3.PIPETX7DATA22 |
| CELL52.OUT3.TMIN | PCIE3.PIPERX2EQPRESET1 |
| CELL52.OUT4.TMIN | PCIE3.PIPETX7DATA21 |
| CELL52.OUT5.TMIN | PCIE3.PIPERX2EQPRESET2 |
| CELL52.OUT6.TMIN | PCIE3.PIPETX7DATA23 |
| CELL52.OUT7.TMIN | PCIE3.PIPERX3EQPRESET0 |
| CELL52.OUT8.TMIN | PCIE3.MAXISCQTDATA173 |
| CELL52.OUT9.TMIN | PCIE3.PIPETX6DATA24 |
| CELL52.OUT10.TMIN | PCIE3.MAXISCQTDATA174 |
| CELL52.OUT11.TMIN | PCIE3.PIPETX6DATA26 |
| CELL52.OUT12.TMIN | PCIE3.MAXISCQTDATA175 |
| CELL52.OUT13.TMIN | PCIE3.PIPETX6DATA25 |
| CELL52.OUT14.TMIN | PCIE3.MAXISCQTDATA176 |
| CELL52.OUT15.TMIN | PCIE3.PIPETX6DATA27 |
| CELL52.OUT16.TMIN | PCIE3.MAXISCQTDATA185 |
| CELL52.OUT17.TMIN | PCIE3.MAXISCQTDATA186 |
| CELL52.OUT18.TMIN | PCIE3.MAXISCQTDATA187 |
| CELL52.OUT19.TMIN | PCIE3.MAXISCQTDATA188 |
| CELL52.OUT20.TMIN | PCIE3.MAXISCQTUSER2 |
| CELL52.OUT21.TMIN | PCIE3.MAXISCQTUSER3 |
| CELL52.OUT22.TMIN | PCIE3.CFGFCPH4 |
| CELL52.OUT23.TMIN | PCIE3.CFGFCPH5 |
| CELL53.IMUX.IMUX0.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET6 |
| CELL53.IMUX.IMUX1.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET7 |
| CELL53.IMUX.IMUX2.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET8 |
| CELL53.IMUX.IMUX3.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET9 |
| CELL53.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA61 |
| CELL53.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA62 |
| CELL53.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA63 |
| CELL53.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA64 |
| CELL53.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA81 |
| CELL53.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA82 |
| CELL53.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA83 |
| CELL53.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA84 |
| CELL53.IMUX.IMUX12.DELAY | PCIE3.SAXISCCTUSER8 |
| CELL53.IMUX.IMUX13.DELAY | PCIE3.SAXISCCTUSER9 |
| CELL53.IMUX.IMUX14.DELAY | PCIE3.SAXISCCTUSER10 |
| CELL53.IMUX.IMUX15.DELAY | PCIE3.SAXISCCTUSER11 |
| CELL53.IMUX.IMUX16.DELAY | PCIE3.SAXISCCTKEEP7 |
| CELL53.IMUX.IMUX17.DELAY | PCIE3.MAXISCQTREADY7 |
| CELL53.IMUX.IMUX18.DELAY | PCIE3.MAXISCQTREADY8 |
| CELL53.IMUX.IMUX19.DELAY | PCIE3.MAXISCQTREADY9 |
| CELL53.IMUX.IMUX20.DELAY | PCIE3.CFGEXTREADDATA10 |
| CELL53.IMUX.IMUX21.DELAY | PCIE3.CFGEXTREADDATA11 |
| CELL53.IMUX.IMUX22.DELAY | PCIE3.CFGEXTREADDATA12 |
| CELL53.IMUX.IMUX23.DELAY | PCIE3.CFGEXTREADDATA13 |
| CELL53.IMUX.IMUX34.DELAY | PCIE3.PIPERX7DATA31 |
| CELL53.IMUX.IMUX35.DELAY | PCIE3.PIPERX7DATA30 |
| CELL53.IMUX.IMUX38.DELAY | PCIE3.PIPERX7DATA29 |
| CELL53.IMUX.IMUX39.DELAY | PCIE3.PIPERX7DATA28 |
| CELL53.OUT0.TMIN | PCIE3.PIPETX6DATA20 |
| CELL53.OUT1.TMIN | PCIE3.PIPERX3EQPRESET1 |
| CELL53.OUT2.TMIN | PCIE3.PIPETX6DATA22 |
| CELL53.OUT3.TMIN | PCIE3.PIPERX3EQPRESET2 |
| CELL53.OUT4.TMIN | PCIE3.PIPETX6DATA21 |
| CELL53.OUT5.TMIN | PCIE3.PIPERX4EQPRESET0 |
| CELL53.OUT6.TMIN | PCIE3.PIPETX6DATA23 |
| CELL53.OUT7.TMIN | PCIE3.PIPERX4EQPRESET1 |
| CELL53.OUT8.TMIN | PCIE3.MAXISCQTDATA169 |
| CELL53.OUT9.TMIN | PCIE3.PIPETX7DATA16 |
| CELL53.OUT10.TMIN | PCIE3.MAXISCQTDATA170 |
| CELL53.OUT11.TMIN | PCIE3.PIPETX7DATA18 |
| CELL53.OUT12.TMIN | PCIE3.MAXISCQTDATA171 |
| CELL53.OUT13.TMIN | PCIE3.PIPETX7DATA17 |
| CELL53.OUT14.TMIN | PCIE3.MAXISCQTDATA172 |
| CELL53.OUT15.TMIN | PCIE3.PIPETX7DATA19 |
| CELL53.OUT16.TMIN | PCIE3.MAXISCQTDATA189 |
| CELL53.OUT17.TMIN | PCIE3.MAXISCQTDATA190 |
| CELL53.OUT18.TMIN | PCIE3.MAXISCQTDATA191 |
| CELL53.OUT19.TMIN | PCIE3.MAXISCQTDATA192 |
| CELL53.OUT20.TMIN | PCIE3.MAXISCQTUSER4 |
| CELL53.OUT21.TMIN | PCIE3.MAXISCQTUSER5 |
| CELL53.OUT22.TMIN | PCIE3.CFGFCPH6 |
| CELL53.OUT23.TMIN | PCIE3.CFGFCPH7 |
| CELL54.IMUX.IMUX0.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET10 |
| CELL54.IMUX.IMUX1.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET11 |
| CELL54.IMUX.IMUX2.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET12 |
| CELL54.IMUX.IMUX3.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET13 |
| CELL54.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA57 |
| CELL54.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA58 |
| CELL54.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA59 |
| CELL54.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA60 |
| CELL54.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA85 |
| CELL54.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA86 |
| CELL54.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA87 |
| CELL54.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA88 |
| CELL54.IMUX.IMUX12.DELAY | PCIE3.CFGEXTREADDATA14 |
| CELL54.IMUX.IMUX13.DELAY | PCIE3.CFGEXTREADDATA15 |
| CELL54.IMUX.IMUX14.DELAY | PCIE3.CFGEXTREADDATA16 |
| CELL54.IMUX.IMUX15.DELAY | PCIE3.CFGEXTREADDATA17 |
| CELL54.IMUX.IMUX20.DELAY | PCIE3.PIPERX7SYNCHEADER1 |
| CELL54.IMUX.IMUX21.DELAY | PCIE3.PIPERX7SYNCHEADER0 |
| CELL54.IMUX.IMUX22.DELAY | PCIE3.PIPERX7STARTBLOCK |
| CELL54.IMUX.IMUX23.DELAY | PCIE3.PIPERX7DATAVALID |
| CELL54.IMUX.IMUX32.DELAY | PCIE3.PIPERX7DATA27 |
| CELL54.IMUX.IMUX33.DELAY | PCIE3.PIPERX7DATA26 |
| CELL54.IMUX.IMUX34.DELAY | PCIE3.PIPERX6DATA31 |
| CELL54.IMUX.IMUX35.DELAY | PCIE3.PIPERX6DATA30 |
| CELL54.IMUX.IMUX36.DELAY | PCIE3.PIPERX7DATA25 |
| CELL54.IMUX.IMUX37.DELAY | PCIE3.PIPERX7DATA24 |
| CELL54.IMUX.IMUX38.DELAY | PCIE3.PIPERX6DATA29 |
| CELL54.IMUX.IMUX39.DELAY | PCIE3.PIPERX6DATA28 |
| CELL54.OUT0.TMIN | PCIE3.PIPETX7DATA12 |
| CELL54.OUT1.TMIN | PCIE3.PIPERX4EQPRESET2 |
| CELL54.OUT2.TMIN | PCIE3.PIPETX7DATA14 |
| CELL54.OUT3.TMIN | PCIE3.PIPERX5EQPRESET0 |
| CELL54.OUT4.TMIN | PCIE3.PIPETX7DATA13 |
| CELL54.OUT5.TMIN | PCIE3.PIPERX5EQPRESET1 |
| CELL54.OUT6.TMIN | PCIE3.PIPETX7DATA15 |
| CELL54.OUT7.TMIN | PCIE3.PIPERX5EQPRESET2 |
| CELL54.OUT8.TMIN | PCIE3.MAXISCQTDATA165 |
| CELL54.OUT9.TMIN | PCIE3.PIPETX6DATA16 |
| CELL54.OUT10.TMIN | PCIE3.MAXISCQTDATA166 |
| CELL54.OUT11.TMIN | PCIE3.PIPETX6DATA18 |
| CELL54.OUT12.TMIN | PCIE3.MAXISCQTDATA167 |
| CELL54.OUT13.TMIN | PCIE3.PIPETX6DATA17 |
| CELL54.OUT14.TMIN | PCIE3.MAXISCQTDATA168 |
| CELL54.OUT15.TMIN | PCIE3.PIPETX6DATA19 |
| CELL54.OUT16.TMIN | PCIE3.PIPETX7CHARISK1 |
| CELL54.OUT17.TMIN | PCIE3.MAXISCQTDATA193 |
| CELL54.OUT18.TMIN | PCIE3.CFGFCPD0 |
| CELL54.OUT19.TMIN | PCIE3.CFGFCPD1 |
| CELL54.OUT20.TMIN | PCIE3.PIPETX7SYNCHEADER1 |
| CELL54.OUT21.TMIN | PCIE3.PIPETX7SYNCHEADER0 |
| CELL54.OUT22.TMIN | PCIE3.PIPETX7STARTBLOCK |
| CELL54.OUT23.TMIN | PCIE3.PIPETX7DATAVALID |
| CELL55.IMUX.IMUX0.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET14 |
| CELL55.IMUX.IMUX1.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET15 |
| CELL55.IMUX.IMUX2.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET16 |
| CELL55.IMUX.IMUX3.DELAY | PCIE3.PIPERX1EQLPNEWTXCOEFFORPRESET17 |
| CELL55.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA53 |
| CELL55.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA54 |
| CELL55.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA55 |
| CELL55.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA56 |
| CELL55.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA89 |
| CELL55.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA90 |
| CELL55.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA91 |
| CELL55.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA92 |
| CELL55.IMUX.IMUX12.DELAY | PCIE3.CFGEXTREADDATA18 |
| CELL55.IMUX.IMUX13.DELAY | PCIE3.CFGEXTREADDATA19 |
| CELL55.IMUX.IMUX14.DELAY | PCIE3.CFGEXTREADDATA20 |
| CELL55.IMUX.IMUX15.DELAY | PCIE3.CFGEXTREADDATA21 |
| CELL55.IMUX.IMUX20.DELAY | PCIE3.PIPERX6SYNCHEADER1 |
| CELL55.IMUX.IMUX21.DELAY | PCIE3.PIPERX6SYNCHEADER0 |
| CELL55.IMUX.IMUX22.DELAY | PCIE3.PIPERX6STARTBLOCK |
| CELL55.IMUX.IMUX23.DELAY | PCIE3.PIPERX6DATAVALID |
| CELL55.IMUX.IMUX32.DELAY | PCIE3.PIPERX6DATA27 |
| CELL55.IMUX.IMUX33.DELAY | PCIE3.PIPERX6DATA26 |
| CELL55.IMUX.IMUX34.DELAY | PCIE3.PIPERX7DATA23 |
| CELL55.IMUX.IMUX35.DELAY | PCIE3.PIPERX7DATA22 |
| CELL55.IMUX.IMUX36.DELAY | PCIE3.PIPERX6DATA25 |
| CELL55.IMUX.IMUX37.DELAY | PCIE3.PIPERX6DATA24 |
| CELL55.IMUX.IMUX38.DELAY | PCIE3.PIPERX7DATA21 |
| CELL55.IMUX.IMUX39.DELAY | PCIE3.PIPERX7DATA20 |
| CELL55.OUT0.TMIN | PCIE3.PIPETX6DATA12 |
| CELL55.OUT1.TMIN | PCIE3.PIPERX6EQPRESET0 |
| CELL55.OUT2.TMIN | PCIE3.PIPETX6DATA14 |
| CELL55.OUT3.TMIN | PCIE3.PIPERX6EQPRESET1 |
| CELL55.OUT4.TMIN | PCIE3.PIPETX6DATA13 |
| CELL55.OUT5.TMIN | PCIE3.PIPERX6EQPRESET2 |
| CELL55.OUT6.TMIN | PCIE3.PIPETX6DATA15 |
| CELL55.OUT7.TMIN | PCIE3.PIPERX7EQPRESET0 |
| CELL55.OUT8.TMIN | PCIE3.MAXISCQTDATA161 |
| CELL55.OUT9.TMIN | PCIE3.PIPETX7DATA8 |
| CELL55.OUT10.TMIN | PCIE3.MAXISCQTDATA162 |
| CELL55.OUT11.TMIN | PCIE3.PIPETX7DATA10 |
| CELL55.OUT12.TMIN | PCIE3.MAXISCQTDATA163 |
| CELL55.OUT13.TMIN | PCIE3.PIPETX7DATA9 |
| CELL55.OUT14.TMIN | PCIE3.MAXISCQTDATA164 |
| CELL55.OUT15.TMIN | PCIE3.PIPETX7DATA11 |
| CELL55.OUT16.TMIN | PCIE3.PIPETX6CHARISK1 |
| CELL55.OUT17.TMIN | PCIE3.MAXISCQTDATA194 |
| CELL55.OUT18.TMIN | PCIE3.CFGFCPD2 |
| CELL55.OUT19.TMIN | PCIE3.CFGFCPD3 |
| CELL55.OUT20.TMIN | PCIE3.PIPETX6SYNCHEADER1 |
| CELL55.OUT21.TMIN | PCIE3.PIPETX6SYNCHEADER0 |
| CELL55.OUT22.TMIN | PCIE3.PIPETX6STARTBLOCK |
| CELL55.OUT23.TMIN | PCIE3.PIPETX6DATAVALID |
| CELL56.IMUX.IMUX0.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET0 |
| CELL56.IMUX.IMUX1.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET1 |
| CELL56.IMUX.IMUX2.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET2 |
| CELL56.IMUX.IMUX3.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET3 |
| CELL56.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA49 |
| CELL56.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA50 |
| CELL56.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA51 |
| CELL56.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA52 |
| CELL56.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA93 |
| CELL56.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA94 |
| CELL56.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA95 |
| CELL56.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA96 |
| CELL56.IMUX.IMUX12.DELAY | PCIE3.SAXISCCTUSER12 |
| CELL56.IMUX.IMUX13.DELAY | PCIE3.SAXISCCTUSER13 |
| CELL56.IMUX.IMUX14.DELAY | PCIE3.SAXISCCTUSER14 |
| CELL56.IMUX.IMUX15.DELAY | PCIE3.SAXISCCTUSER15 |
| CELL56.IMUX.IMUX16.DELAY | PCIE3.CFGEXTREADDATA22 |
| CELL56.IMUX.IMUX17.DELAY | PCIE3.CFGEXTREADDATA23 |
| CELL56.IMUX.IMUX18.DELAY | PCIE3.CFGEXTREADDATA24 |
| CELL56.IMUX.IMUX19.DELAY | PCIE3.CFGEXTREADDATA25 |
| CELL56.IMUX.IMUX32.DELAY | PCIE3.PIPERX7DATA19 |
| CELL56.IMUX.IMUX33.DELAY | PCIE3.PIPERX7DATA18 |
| CELL56.IMUX.IMUX34.DELAY | PCIE3.PIPERX6DATA23 |
| CELL56.IMUX.IMUX35.DELAY | PCIE3.PIPERX6DATA22 |
| CELL56.IMUX.IMUX36.DELAY | PCIE3.PIPERX7DATA17 |
| CELL56.IMUX.IMUX37.DELAY | PCIE3.PIPERX7DATA16 |
| CELL56.IMUX.IMUX38.DELAY | PCIE3.PIPERX6DATA21 |
| CELL56.IMUX.IMUX39.DELAY | PCIE3.PIPERX6DATA20 |
| CELL56.OUT0.TMIN | PCIE3.PIPETX7DATA4 |
| CELL56.OUT1.TMIN | PCIE3.PIPERX7EQPRESET1 |
| CELL56.OUT2.TMIN | PCIE3.PIPETX7DATA6 |
| CELL56.OUT3.TMIN | PCIE3.PIPETX7ELECIDLE |
| CELL56.OUT4.TMIN | PCIE3.PIPETX7DATA5 |
| CELL56.OUT5.TMIN | PCIE3.PIPETX7POWERDOWN0 |
| CELL56.OUT6.TMIN | PCIE3.PIPETX7DATA7 |
| CELL56.OUT7.TMIN | PCIE3.PIPETX7POWERDOWN1 |
| CELL56.OUT8.TMIN | PCIE3.PIPERX7EQPRESET2 |
| CELL56.OUT9.TMIN | PCIE3.PIPETX6DATA8 |
| CELL56.OUT10.TMIN | PCIE3.PIPERX0EQLPTXPRESET0 |
| CELL56.OUT11.TMIN | PCIE3.PIPETX6DATA10 |
| CELL56.OUT12.TMIN | PCIE3.PIPERX0EQLPTXPRESET1 |
| CELL56.OUT13.TMIN | PCIE3.PIPETX6DATA9 |
| CELL56.OUT14.TMIN | PCIE3.MAXISCQTDATA157 |
| CELL56.OUT15.TMIN | PCIE3.PIPETX6DATA11 |
| CELL56.OUT16.TMIN | PCIE3.PIPETX7CHARISK0 |
| CELL56.OUT17.TMIN | PCIE3.MAXISCQTDATA158 |
| CELL56.OUT18.TMIN | PCIE3.MAXISCQTDATA159 |
| CELL56.OUT19.TMIN | PCIE3.MAXISCQTDATA160 |
| CELL56.OUT20.TMIN | PCIE3.MAXISCQTDATA195 |
| CELL56.OUT21.TMIN | PCIE3.MAXISCQTDATA196 |
| CELL56.OUT22.TMIN | PCIE3.CFGFCPD4 |
| CELL56.OUT23.TMIN | PCIE3.CFGFCPD5 |
| CELL57.IMUX.IMUX0.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET4 |
| CELL57.IMUX.IMUX1.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET5 |
| CELL57.IMUX.IMUX2.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET6 |
| CELL57.IMUX.IMUX3.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET7 |
| CELL57.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA45 |
| CELL57.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA46 |
| CELL57.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA47 |
| CELL57.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA48 |
| CELL57.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA97 |
| CELL57.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA98 |
| CELL57.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA99 |
| CELL57.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA100 |
| CELL57.IMUX.IMUX12.DELAY | PCIE3.SAXISCCTUSER16 |
| CELL57.IMUX.IMUX13.DELAY | PCIE3.SAXISCCTUSER17 |
| CELL57.IMUX.IMUX14.DELAY | PCIE3.SAXISCCTUSER18 |
| CELL57.IMUX.IMUX15.DELAY | PCIE3.SAXISCCTUSER19 |
| CELL57.IMUX.IMUX16.DELAY | PCIE3.CFGEXTREADDATA26 |
| CELL57.IMUX.IMUX17.DELAY | PCIE3.CFGEXTREADDATA27 |
| CELL57.IMUX.IMUX18.DELAY | PCIE3.CFGEXTREADDATA28 |
| CELL57.IMUX.IMUX19.DELAY | PCIE3.CFGEXTREADDATA29 |
| CELL57.IMUX.IMUX32.DELAY | PCIE3.PIPERX6DATA19 |
| CELL57.IMUX.IMUX33.DELAY | PCIE3.PIPERX6DATA18 |
| CELL57.IMUX.IMUX34.DELAY | PCIE3.PIPERX7DATA15 |
| CELL57.IMUX.IMUX35.DELAY | PCIE3.PIPERX7DATA14 |
| CELL57.IMUX.IMUX36.DELAY | PCIE3.PIPERX6DATA17 |
| CELL57.IMUX.IMUX37.DELAY | PCIE3.PIPERX6DATA16 |
| CELL57.IMUX.IMUX38.DELAY | PCIE3.PIPERX7DATA13 |
| CELL57.IMUX.IMUX39.DELAY | PCIE3.PIPERX7DATA12 |
| CELL57.OUT0.TMIN | PCIE3.PIPETX6DATA4 |
| CELL57.OUT1.TMIN | PCIE3.PIPERX7POLARITY |
| CELL57.OUT2.TMIN | PCIE3.PIPETX6DATA6 |
| CELL57.OUT3.TMIN | PCIE3.PIPETX6ELECIDLE |
| CELL57.OUT4.TMIN | PCIE3.PIPETX6DATA5 |
| CELL57.OUT5.TMIN | PCIE3.PIPETX6POWERDOWN0 |
| CELL57.OUT6.TMIN | PCIE3.PIPETX6DATA7 |
| CELL57.OUT7.TMIN | PCIE3.PIPETX6POWERDOWN1 |
| CELL57.OUT8.TMIN | PCIE3.PIPETX7COMPLIANCE |
| CELL57.OUT9.TMIN | PCIE3.PIPETX7DATA0 |
| CELL57.OUT10.TMIN | PCIE3.PIPERX0EQLPTXPRESET2 |
| CELL57.OUT11.TMIN | PCIE3.PIPETX7DATA2 |
| CELL57.OUT12.TMIN | PCIE3.PIPERX0EQLPTXPRESET3 |
| CELL57.OUT13.TMIN | PCIE3.PIPETX7DATA1 |
| CELL57.OUT14.TMIN | PCIE3.PIPERX1EQLPTXPRESET0 |
| CELL57.OUT15.TMIN | PCIE3.PIPETX7DATA3 |
| CELL57.OUT16.TMIN | PCIE3.PIPETX6CHARISK0 |
| CELL57.OUT17.TMIN | PCIE3.PIPERX1EQLPTXPRESET1 |
| CELL57.OUT18.TMIN | PCIE3.MAXISCQTDATA153 |
| CELL57.OUT19.TMIN | PCIE3.MAXISCQTDATA154 |
| CELL57.OUT20.TMIN | PCIE3.MAXISCQTDATA155 |
| CELL57.OUT21.TMIN | PCIE3.MAXISCQTDATA156 |
| CELL57.OUT22.TMIN | PCIE3.CFGFCPD6 |
| CELL57.OUT23.TMIN | PCIE3.CFGFCPD7 |
| CELL58.IMUX.IMUX0.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET8 |
| CELL58.IMUX.IMUX1.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET9 |
| CELL58.IMUX.IMUX2.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET10 |
| CELL58.IMUX.IMUX3.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET11 |
| CELL58.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA41 |
| CELL58.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA42 |
| CELL58.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA43 |
| CELL58.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA44 |
| CELL58.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA101 |
| CELL58.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA102 |
| CELL58.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA103 |
| CELL58.IMUX.IMUX11.DELAY | PCIE3.CFGEXTREADDATA30 |
| CELL58.IMUX.IMUX12.DELAY | PCIE3.CFGEXTREADDATA31 |
| CELL58.IMUX.IMUX13.DELAY | PCIE3.CFGEXTREADDATAVALID |
| CELL58.IMUX.IMUX14.DELAY | PCIE3.CFGTPHSTTREADDATA0 |
| CELL58.IMUX.IMUX16.DELAY | PCIE3.PIPERX7CHARISK1 |
| CELL58.IMUX.IMUX32.DELAY | PCIE3.PIPERX7DATA11 |
| CELL58.IMUX.IMUX33.DELAY | PCIE3.PIPERX7DATA10 |
| CELL58.IMUX.IMUX34.DELAY | PCIE3.PIPERX6DATA15 |
| CELL58.IMUX.IMUX35.DELAY | PCIE3.PIPERX6DATA14 |
| CELL58.IMUX.IMUX36.DELAY | PCIE3.PIPERX7DATA9 |
| CELL58.IMUX.IMUX37.DELAY | PCIE3.PIPERX7DATA8 |
| CELL58.IMUX.IMUX38.DELAY | PCIE3.PIPERX6DATA13 |
| CELL58.IMUX.IMUX39.DELAY | PCIE3.PIPERX6DATA12 |
| CELL58.IMUX.IMUX41.DELAY | PCIE3.PIPERX7ELECIDLE |
| CELL58.IMUX.IMUX42.DELAY | PCIE3.PIPERX7STATUS2 |
| CELL58.IMUX.IMUX43.DELAY | PCIE3.PIPERX7STATUS1 |
| CELL58.IMUX.IMUX44.DELAY | PCIE3.PIPERX7STATUS0 |
| CELL58.OUT0.TMIN | PCIE3.PIPERX1EQLPTXPRESET2 |
| CELL58.OUT1.TMIN | PCIE3.PIPERX6POLARITY |
| CELL58.OUT2.TMIN | PCIE3.PIPERX1EQLPTXPRESET3 |
| CELL58.OUT3.TMIN | PCIE3.PIPERX2EQLPTXPRESET0 |
| CELL58.OUT4.TMIN | PCIE3.PIPERX2EQLPTXPRESET1 |
| CELL58.OUT5.TMIN | PCIE3.MAXISCQTDATA149 |
| CELL58.OUT6.TMIN | PCIE3.MAXISCQTDATA150 |
| CELL58.OUT7.TMIN | PCIE3.MAXISCQTDATA151 |
| CELL58.OUT8.TMIN | PCIE3.PIPETX6COMPLIANCE |
| CELL58.OUT9.TMIN | PCIE3.PIPETX6DATA0 |
| CELL58.OUT10.TMIN | PCIE3.MAXISCQTDATA152 |
| CELL58.OUT11.TMIN | PCIE3.PIPETX6DATA2 |
| CELL58.OUT12.TMIN | PCIE3.MAXISCQTDATA197 |
| CELL58.OUT13.TMIN | PCIE3.PIPETX6DATA1 |
| CELL58.OUT14.TMIN | PCIE3.MAXISCQTDATA198 |
| CELL58.OUT15.TMIN | PCIE3.PIPETX6DATA3 |
| CELL58.OUT16.TMIN | PCIE3.MAXISCQTDATA199 |
| CELL58.OUT17.TMIN | PCIE3.MAXISCQTDATA200 |
| CELL58.OUT18.TMIN | PCIE3.MAXISCQTUSER6 |
| CELL58.OUT19.TMIN | PCIE3.MAXISCQTUSER7 |
| CELL58.OUT20.TMIN | PCIE3.MAXISCQTUSER8 |
| CELL58.OUT21.TMIN | PCIE3.MAXISCQTUSER9 |
| CELL58.OUT22.TMIN | PCIE3.CFGFCPD8 |
| CELL58.OUT23.TMIN | PCIE3.CFGFCPD9 |
| CELL59.IMUX.IMUX0.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET12 |
| CELL59.IMUX.IMUX1.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET13 |
| CELL59.IMUX.IMUX2.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET14 |
| CELL59.IMUX.IMUX3.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET15 |
| CELL59.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA37 |
| CELL59.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA38 |
| CELL59.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA39 |
| CELL59.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA40 |
| CELL59.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA104 |
| CELL59.IMUX.IMUX9.DELAY | PCIE3.CFGTPHSTTREADDATA1 |
| CELL59.IMUX.IMUX10.DELAY | PCIE3.CFGTPHSTTREADDATA2 |
| CELL59.IMUX.IMUX11.DELAY | PCIE3.CFGTPHSTTREADDATA3 |
| CELL59.IMUX.IMUX12.DELAY | PCIE3.CFGTPHSTTREADDATA4 |
| CELL59.IMUX.IMUX16.DELAY | PCIE3.PIPERX6CHARISK1 |
| CELL59.IMUX.IMUX32.DELAY | PCIE3.PIPERX6DATA11 |
| CELL59.IMUX.IMUX33.DELAY | PCIE3.PIPERX6DATA10 |
| CELL59.IMUX.IMUX34.DELAY | PCIE3.PIPERX7DATA7 |
| CELL59.IMUX.IMUX35.DELAY | PCIE3.PIPERX7DATA6 |
| CELL59.IMUX.IMUX36.DELAY | PCIE3.PIPERX6DATA9 |
| CELL59.IMUX.IMUX37.DELAY | PCIE3.PIPERX6DATA8 |
| CELL59.IMUX.IMUX38.DELAY | PCIE3.PIPERX7DATA5 |
| CELL59.IMUX.IMUX39.DELAY | PCIE3.PIPERX7DATA4 |
| CELL59.IMUX.IMUX40.DELAY | PCIE3.PIPERX7VALID |
| CELL59.IMUX.IMUX41.DELAY | PCIE3.PIPERX6ELECIDLE |
| CELL59.IMUX.IMUX42.DELAY | PCIE3.PIPERX6STATUS2 |
| CELL59.IMUX.IMUX43.DELAY | PCIE3.PIPERX6STATUS1 |
| CELL59.IMUX.IMUX44.DELAY | PCIE3.PIPERX6STATUS0 |
| CELL59.IMUX.IMUX45.DELAY | PCIE3.PIPERX7PHYSTATUS |
| CELL59.OUT0.TMIN | PCIE3.PIPERX2EQLPTXPRESET2 |
| CELL59.OUT1.TMIN | PCIE3.PIPERX2EQLPTXPRESET3 |
| CELL59.OUT2.TMIN | PCIE3.PIPERX3EQLPTXPRESET0 |
| CELL59.OUT3.TMIN | PCIE3.PIPERX3EQLPTXPRESET1 |
| CELL59.OUT4.TMIN | PCIE3.MAXISCQTDATA145 |
| CELL59.OUT5.TMIN | PCIE3.MAXISCQTDATA146 |
| CELL59.OUT6.TMIN | PCIE3.MAXISCQTDATA147 |
| CELL59.OUT7.TMIN | PCIE3.MAXISCQTDATA148 |
| CELL59.OUT8.TMIN | PCIE3.MAXISCQTDATA201 |
| CELL59.OUT9.TMIN | PCIE3.MAXISCQTDATA202 |
| CELL59.OUT10.TMIN | PCIE3.MAXISCQTDATA203 |
| CELL59.OUT11.TMIN | PCIE3.MAXISCQTDATA204 |
| CELL59.OUT12.TMIN | PCIE3.MAXISCQTUSER10 |
| CELL59.OUT13.TMIN | PCIE3.MAXISCQTUSER11 |
| CELL59.OUT14.TMIN | PCIE3.MAXISCQTUSER12 |
| CELL59.OUT15.TMIN | PCIE3.MAXISCQTUSER13 |
| CELL59.OUT16.TMIN | PCIE3.MAXISCQTKEEP0 |
| CELL59.OUT17.TMIN | PCIE3.MAXISCQTKEEP1 |
| CELL59.OUT18.TMIN | PCIE3.MAXISCQTKEEP2 |
| CELL59.OUT19.TMIN | PCIE3.MAXISCQTKEEP3 |
| CELL59.OUT20.TMIN | PCIE3.MAXISCQTVALID |
| CELL59.OUT21.TMIN | PCIE3.SAXISCCTREADY0 |
| CELL59.OUT22.TMIN | PCIE3.CFGFCPD10 |
| CELL59.OUT23.TMIN | PCIE3.CFGFCPD11 |
| CELL60.IMUX.IMUX0.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET16 |
| CELL60.IMUX.IMUX1.DELAY | PCIE3.PIPERX2EQLPNEWTXCOEFFORPRESET17 |
| CELL60.IMUX.IMUX2.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET0 |
| CELL60.IMUX.IMUX3.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET1 |
| CELL60.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA33 |
| CELL60.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA34 |
| CELL60.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA35 |
| CELL60.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA36 |
| CELL60.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA105 |
| CELL60.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA106 |
| CELL60.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA107 |
| CELL60.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA108 |
| CELL60.IMUX.IMUX12.DELAY | PCIE3.SAXISCCTUSER20 |
| CELL60.IMUX.IMUX13.DELAY | PCIE3.CFGTPHSTTREADDATA5 |
| CELL60.IMUX.IMUX14.DELAY | PCIE3.CFGTPHSTTREADDATA6 |
| CELL60.IMUX.IMUX15.DELAY | PCIE3.CFGTPHSTTREADDATA7 |
| CELL60.IMUX.IMUX16.DELAY | PCIE3.PIPERX7CHARISK0 |
| CELL60.IMUX.IMUX17.DELAY | PCIE3.CFGTPHSTTREADDATA8 |
| CELL60.IMUX.IMUX32.DELAY | PCIE3.PIPERX7DATA3 |
| CELL60.IMUX.IMUX33.DELAY | PCIE3.PIPERX7DATA2 |
| CELL60.IMUX.IMUX34.DELAY | PCIE3.PIPERX6DATA7 |
| CELL60.IMUX.IMUX35.DELAY | PCIE3.PIPERX6DATA6 |
| CELL60.IMUX.IMUX36.DELAY | PCIE3.PIPERX7DATA1 |
| CELL60.IMUX.IMUX37.DELAY | PCIE3.PIPERX7DATA0 |
| CELL60.IMUX.IMUX38.DELAY | PCIE3.PIPERX6DATA5 |
| CELL60.IMUX.IMUX39.DELAY | PCIE3.PIPERX6DATA4 |
| CELL60.IMUX.IMUX40.DELAY | PCIE3.PIPERX6VALID |
| CELL60.IMUX.IMUX45.DELAY | PCIE3.PIPERX6PHYSTATUS |
| CELL60.OUT0.TMIN | PCIE3.PIPERX3EQLPTXPRESET2 |
| CELL60.OUT1.TMIN | PCIE3.PIPERX3EQLPTXPRESET3 |
| CELL60.OUT2.TMIN | PCIE3.PIPERX4EQLPTXPRESET0 |
| CELL60.OUT3.TMIN | PCIE3.PIPERX4EQLPTXPRESET1 |
| CELL60.OUT4.TMIN | PCIE3.MAXISCQTDATA141 |
| CELL60.OUT5.TMIN | PCIE3.MAXISCQTDATA142 |
| CELL60.OUT6.TMIN | PCIE3.MAXISCQTDATA143 |
| CELL60.OUT7.TMIN | PCIE3.MAXISCQTDATA144 |
| CELL60.OUT8.TMIN | PCIE3.MAXISCQTDATA205 |
| CELL60.OUT9.TMIN | PCIE3.MAXISCQTDATA206 |
| CELL60.OUT10.TMIN | PCIE3.MAXISCQTDATA207 |
| CELL60.OUT11.TMIN | PCIE3.MAXISCQTDATA208 |
| CELL60.OUT12.TMIN | PCIE3.MAXISCQTUSER14 |
| CELL60.OUT13.TMIN | PCIE3.MAXISCQTUSER15 |
| CELL60.OUT14.TMIN | PCIE3.MAXISCQTUSER16 |
| CELL60.OUT15.TMIN | PCIE3.MAXISCQTUSER17 |
| CELL60.OUT16.TMIN | PCIE3.MAXISCQTKEEP4 |
| CELL60.OUT17.TMIN | PCIE3.MAXISCQTKEEP5 |
| CELL60.OUT18.TMIN | PCIE3.MAXISCQTKEEP6 |
| CELL60.OUT19.TMIN | PCIE3.MAXISCQTKEEP7 |
| CELL60.OUT20.TMIN | PCIE3.CFGFCNPH0 |
| CELL60.OUT21.TMIN | PCIE3.CFGFCNPH1 |
| CELL60.OUT22.TMIN | PCIE3.CFGFCNPH2 |
| CELL60.OUT23.TMIN | PCIE3.CFGFCNPH3 |
| CELL61.IMUX.IMUX0.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET2 |
| CELL61.IMUX.IMUX1.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET3 |
| CELL61.IMUX.IMUX2.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET4 |
| CELL61.IMUX.IMUX3.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET5 |
| CELL61.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA29 |
| CELL61.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA30 |
| CELL61.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA31 |
| CELL61.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA32 |
| CELL61.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA109 |
| CELL61.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA110 |
| CELL61.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA111 |
| CELL61.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA112 |
| CELL61.IMUX.IMUX12.DELAY | PCIE3.SAXISCCTUSER21 |
| CELL61.IMUX.IMUX13.DELAY | PCIE3.SAXISCCTUSER22 |
| CELL61.IMUX.IMUX14.DELAY | PCIE3.SAXISCCTUSER23 |
| CELL61.IMUX.IMUX15.DELAY | PCIE3.SAXISCCTUSER24 |
| CELL61.IMUX.IMUX16.DELAY | PCIE3.PIPERX6CHARISK0 |
| CELL61.IMUX.IMUX17.DELAY | PCIE3.MAXISCQTREADY10 |
| CELL61.IMUX.IMUX18.DELAY | PCIE3.MAXISCQTREADY11 |
| CELL61.IMUX.IMUX19.DELAY | PCIE3.MAXISCQTREADY12 |
| CELL61.IMUX.IMUX20.DELAY | PCIE3.CFGTPHSTTREADDATA9 |
| CELL61.IMUX.IMUX21.DELAY | PCIE3.CFGTPHSTTREADDATA10 |
| CELL61.IMUX.IMUX22.DELAY | PCIE3.CFGTPHSTTREADDATA11 |
| CELL61.IMUX.IMUX23.DELAY | PCIE3.CFGTPHSTTREADDATA12 |
| CELL61.IMUX.IMUX32.DELAY | PCIE3.PIPERX6DATA3 |
| CELL61.IMUX.IMUX33.DELAY | PCIE3.PIPERX6DATA2 |
| CELL61.IMUX.IMUX36.DELAY | PCIE3.PIPERX6DATA1 |
| CELL61.IMUX.IMUX37.DELAY | PCIE3.PIPERX6DATA0 |
| CELL61.OUT0.TMIN | PCIE3.PIPETX5DATA28 |
| CELL61.OUT1.TMIN | PCIE3.PIPERX4EQLPTXPRESET2 |
| CELL61.OUT2.TMIN | PCIE3.PIPETX5DATA30 |
| CELL61.OUT3.TMIN | PCIE3.PIPERX4EQLPTXPRESET3 |
| CELL61.OUT4.TMIN | PCIE3.PIPETX5DATA29 |
| CELL61.OUT5.TMIN | PCIE3.PIPERX5EQLPTXPRESET0 |
| CELL61.OUT6.TMIN | PCIE3.PIPETX5DATA31 |
| CELL61.OUT7.TMIN | PCIE3.PIPERX5EQLPTXPRESET1 |
| CELL61.OUT8.TMIN | PCIE3.MAXISCQTDATA137 |
| CELL61.OUT9.TMIN | PCIE3.MAXISCQTDATA138 |
| CELL61.OUT10.TMIN | PCIE3.MAXISCQTDATA139 |
| CELL61.OUT11.TMIN | PCIE3.MAXISCQTDATA140 |
| CELL61.OUT12.TMIN | PCIE3.MAXISCQTDATA209 |
| CELL61.OUT13.TMIN | PCIE3.MAXISCQTDATA210 |
| CELL61.OUT14.TMIN | PCIE3.MAXISCQTDATA211 |
| CELL61.OUT15.TMIN | PCIE3.MAXISCQTDATA212 |
| CELL61.OUT16.TMIN | PCIE3.MAXISCQTUSER18 |
| CELL61.OUT17.TMIN | PCIE3.MAXISCQTUSER19 |
| CELL61.OUT18.TMIN | PCIE3.MAXISCQTUSER20 |
| CELL61.OUT19.TMIN | PCIE3.MAXISCQTUSER21 |
| CELL61.OUT20.TMIN | PCIE3.SAXISCCTREADY1 |
| CELL61.OUT21.TMIN | PCIE3.SAXISCCTREADY2 |
| CELL61.OUT22.TMIN | PCIE3.CFGFCNPH4 |
| CELL61.OUT23.TMIN | PCIE3.CFGFCNPH5 |
| CELL62.IMUX.IMUX0.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET6 |
| CELL62.IMUX.IMUX1.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET7 |
| CELL62.IMUX.IMUX2.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET8 |
| CELL62.IMUX.IMUX3.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET9 |
| CELL62.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA25 |
| CELL62.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA26 |
| CELL62.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA27 |
| CELL62.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA28 |
| CELL62.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA113 |
| CELL62.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA114 |
| CELL62.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA115 |
| CELL62.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA116 |
| CELL62.IMUX.IMUX12.DELAY | PCIE3.SAXISCCTUSER25 |
| CELL62.IMUX.IMUX13.DELAY | PCIE3.SAXISCCTUSER26 |
| CELL62.IMUX.IMUX14.DELAY | PCIE3.SAXISCCTUSER27 |
| CELL62.IMUX.IMUX15.DELAY | PCIE3.SAXISCCTUSER28 |
| CELL62.IMUX.IMUX16.DELAY | PCIE3.MAXISCQTREADY13 |
| CELL62.IMUX.IMUX17.DELAY | PCIE3.MAXISCQTREADY14 |
| CELL62.IMUX.IMUX18.DELAY | PCIE3.MAXISCQTREADY15 |
| CELL62.IMUX.IMUX19.DELAY | PCIE3.MAXISCQTREADY16 |
| CELL62.IMUX.IMUX20.DELAY | PCIE3.CFGHOTRESETIN |
| CELL62.IMUX.IMUX21.DELAY | PCIE3.CFGCONFIGSPACEENABLE |
| CELL62.IMUX.IMUX22.DELAY | PCIE3.CFGINPUTUPDATEREQUEST |
| CELL62.IMUX.IMUX23.DELAY | PCIE3.CFGPERFUNCTIONNUMBER0 |
| CELL62.IMUX.IMUX24.DELAY | PCIE3.CFGTPHSTTREADDATA13 |
| CELL62.IMUX.IMUX25.DELAY | PCIE3.CFGTPHSTTREADDATA14 |
| CELL62.IMUX.IMUX26.DELAY | PCIE3.CFGTPHSTTREADDATA15 |
| CELL62.IMUX.IMUX27.DELAY | PCIE3.CFGTPHSTTREADDATA16 |
| CELL62.OUT0.TMIN | PCIE3.PIPETX4DATA28 |
| CELL62.OUT1.TMIN | PCIE3.PIPERX5EQLPTXPRESET2 |
| CELL62.OUT2.TMIN | PCIE3.PIPETX4DATA30 |
| CELL62.OUT3.TMIN | PCIE3.PIPERX5EQLPTXPRESET3 |
| CELL62.OUT4.TMIN | PCIE3.PIPETX4DATA29 |
| CELL62.OUT5.TMIN | PCIE3.PIPERX6EQLPTXPRESET0 |
| CELL62.OUT6.TMIN | PCIE3.PIPETX4DATA31 |
| CELL62.OUT7.TMIN | PCIE3.PIPERX6EQLPTXPRESET1 |
| CELL62.OUT8.TMIN | PCIE3.MAXISCQTDATA133 |
| CELL62.OUT9.TMIN | PCIE3.PIPETX5DATA24 |
| CELL62.OUT10.TMIN | PCIE3.MAXISCQTDATA134 |
| CELL62.OUT11.TMIN | PCIE3.PIPETX5DATA26 |
| CELL62.OUT12.TMIN | PCIE3.MAXISCQTDATA135 |
| CELL62.OUT13.TMIN | PCIE3.PIPETX5DATA25 |
| CELL62.OUT14.TMIN | PCIE3.MAXISCQTDATA136 |
| CELL62.OUT15.TMIN | PCIE3.PIPETX5DATA27 |
| CELL62.OUT16.TMIN | PCIE3.MAXISCQTDATA213 |
| CELL62.OUT17.TMIN | PCIE3.MAXISCQTDATA214 |
| CELL62.OUT18.TMIN | PCIE3.MAXISCQTDATA215 |
| CELL62.OUT19.TMIN | PCIE3.MAXISCQTDATA216 |
| CELL62.OUT20.TMIN | PCIE3.MAXISCQTUSER22 |
| CELL62.OUT21.TMIN | PCIE3.MAXISCQTUSER23 |
| CELL62.OUT22.TMIN | PCIE3.CFGFCNPH6 |
| CELL62.OUT23.TMIN | PCIE3.CFGFCNPH7 |
| CELL63.IMUX.IMUX0.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET10 |
| CELL63.IMUX.IMUX1.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET11 |
| CELL63.IMUX.IMUX2.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET12 |
| CELL63.IMUX.IMUX3.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET13 |
| CELL63.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA21 |
| CELL63.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA22 |
| CELL63.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA23 |
| CELL63.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA24 |
| CELL63.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA117 |
| CELL63.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA118 |
| CELL63.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA119 |
| CELL63.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA120 |
| CELL63.IMUX.IMUX12.DELAY | PCIE3.SAXISCCTUSER29 |
| CELL63.IMUX.IMUX13.DELAY | PCIE3.SAXISCCTUSER30 |
| CELL63.IMUX.IMUX14.DELAY | PCIE3.SAXISCCTUSER31 |
| CELL63.IMUX.IMUX15.DELAY | PCIE3.SAXISCCTUSER32 |
| CELL63.IMUX.IMUX16.DELAY | PCIE3.CFGPERFUNCTIONNUMBER1 |
| CELL63.IMUX.IMUX17.DELAY | PCIE3.CFGPERFUNCTIONNUMBER2 |
| CELL63.IMUX.IMUX18.DELAY | PCIE3.CFGPERFUNCTIONOUTPUTREQUEST |
| CELL63.IMUX.IMUX19.DELAY | PCIE3.CFGMCUPDATEREQUEST |
| CELL63.IMUX.IMUX20.DELAY | PCIE3.CFGDSPORTNUMBER2 |
| CELL63.IMUX.IMUX21.DELAY | PCIE3.CFGDSPORTNUMBER3 |
| CELL63.IMUX.IMUX22.DELAY | PCIE3.CFGDSPORTNUMBER4 |
| CELL63.IMUX.IMUX23.DELAY | PCIE3.CFGDSPORTNUMBER5 |
| CELL63.IMUX.IMUX24.DELAY | PCIE3.CFGTPHSTTREADDATA17 |
| CELL63.IMUX.IMUX25.DELAY | PCIE3.CFGTPHSTTREADDATA18 |
| CELL63.IMUX.IMUX26.DELAY | PCIE3.CFGTPHSTTREADDATA19 |
| CELL63.IMUX.IMUX27.DELAY | PCIE3.CFGTPHSTTREADDATA20 |
| CELL63.OUT0.TMIN | PCIE3.PIPETX5DATA20 |
| CELL63.OUT1.TMIN | PCIE3.PIPERX6EQLPTXPRESET2 |
| CELL63.OUT2.TMIN | PCIE3.PIPETX5DATA22 |
| CELL63.OUT3.TMIN | PCIE3.PIPERX6EQLPTXPRESET3 |
| CELL63.OUT4.TMIN | PCIE3.PIPETX5DATA21 |
| CELL63.OUT5.TMIN | PCIE3.PIPERX7EQLPTXPRESET0 |
| CELL63.OUT6.TMIN | PCIE3.PIPETX5DATA23 |
| CELL63.OUT7.TMIN | PCIE3.PIPERX7EQLPTXPRESET1 |
| CELL63.OUT8.TMIN | PCIE3.MAXISCQTDATA129 |
| CELL63.OUT9.TMIN | PCIE3.PIPETX4DATA24 |
| CELL63.OUT10.TMIN | PCIE3.MAXISCQTDATA130 |
| CELL63.OUT11.TMIN | PCIE3.PIPETX4DATA26 |
| CELL63.OUT12.TMIN | PCIE3.MAXISCQTDATA131 |
| CELL63.OUT13.TMIN | PCIE3.PIPETX4DATA25 |
| CELL63.OUT14.TMIN | PCIE3.MAXISCQTDATA132 |
| CELL63.OUT15.TMIN | PCIE3.PIPETX4DATA27 |
| CELL63.OUT16.TMIN | PCIE3.MAXISCQTDATA217 |
| CELL63.OUT17.TMIN | PCIE3.MAXISCQTDATA218 |
| CELL63.OUT18.TMIN | PCIE3.MAXISCQTDATA219 |
| CELL63.OUT19.TMIN | PCIE3.MAXISCQTDATA220 |
| CELL63.OUT20.TMIN | PCIE3.MAXISCQTUSER24 |
| CELL63.OUT21.TMIN | PCIE3.MAXISCQTUSER25 |
| CELL63.OUT22.TMIN | PCIE3.CFGFCNPD0 |
| CELL63.OUT23.TMIN | PCIE3.CFGFCNPD1 |
| CELL64.IMUX.IMUX0.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET14 |
| CELL64.IMUX.IMUX1.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET15 |
| CELL64.IMUX.IMUX2.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET16 |
| CELL64.IMUX.IMUX3.DELAY | PCIE3.PIPERX3EQLPNEWTXCOEFFORPRESET17 |
| CELL64.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA17 |
| CELL64.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA18 |
| CELL64.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA19 |
| CELL64.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA20 |
| CELL64.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA121 |
| CELL64.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA122 |
| CELL64.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA123 |
| CELL64.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA124 |
| CELL64.IMUX.IMUX12.DELAY | PCIE3.MAXISCQTREADY17 |
| CELL64.IMUX.IMUX13.DELAY | PCIE3.MAXISCQTREADY18 |
| CELL64.IMUX.IMUX14.DELAY | PCIE3.MAXISCQTREADY19 |
| CELL64.IMUX.IMUX15.DELAY | PCIE3.MAXISCQTREADY20 |
| CELL64.IMUX.IMUX16.DELAY | PCIE3.CFGDSN0 |
| CELL64.IMUX.IMUX17.DELAY | PCIE3.CFGDSN1 |
| CELL64.IMUX.IMUX18.DELAY | PCIE3.CFGDSN2 |
| CELL64.IMUX.IMUX19.DELAY | PCIE3.CFGDSN3 |
| CELL64.IMUX.IMUX20.DELAY | PCIE3.CFGTPHSTTREADDATA21 |
| CELL64.IMUX.IMUX21.DELAY | PCIE3.CFGTPHSTTREADDATA22 |
| CELL64.IMUX.IMUX22.DELAY | PCIE3.CFGTPHSTTREADDATA23 |
| CELL64.IMUX.IMUX23.DELAY | PCIE3.CFGTPHSTTREADDATA24 |
| CELL64.IMUX.IMUX34.DELAY | PCIE3.PIPERX5DATA31 |
| CELL64.IMUX.IMUX35.DELAY | PCIE3.PIPERX5DATA30 |
| CELL64.IMUX.IMUX38.DELAY | PCIE3.PIPERX5DATA29 |
| CELL64.IMUX.IMUX39.DELAY | PCIE3.PIPERX5DATA28 |
| CELL64.OUT0.TMIN | PCIE3.PIPETX4DATA20 |
| CELL64.OUT1.TMIN | PCIE3.PIPERX7EQLPTXPRESET2 |
| CELL64.OUT2.TMIN | PCIE3.PIPETX4DATA22 |
| CELL64.OUT3.TMIN | PCIE3.PIPERX7EQLPTXPRESET3 |
| CELL64.OUT4.TMIN | PCIE3.PIPETX4DATA21 |
| CELL64.OUT5.TMIN | PCIE3.PIPERX0EQLPLFFS0 |
| CELL64.OUT6.TMIN | PCIE3.PIPETX4DATA23 |
| CELL64.OUT7.TMIN | PCIE3.PIPERX0EQLPLFFS1 |
| CELL64.OUT8.TMIN | PCIE3.MAXISCQTDATA125 |
| CELL64.OUT9.TMIN | PCIE3.PIPETX5DATA16 |
| CELL64.OUT10.TMIN | PCIE3.MAXISCQTDATA126 |
| CELL64.OUT11.TMIN | PCIE3.PIPETX5DATA18 |
| CELL64.OUT12.TMIN | PCIE3.MAXISCQTDATA127 |
| CELL64.OUT13.TMIN | PCIE3.PIPETX5DATA17 |
| CELL64.OUT14.TMIN | PCIE3.MAXISCQTDATA128 |
| CELL64.OUT15.TMIN | PCIE3.PIPETX5DATA19 |
| CELL64.OUT16.TMIN | PCIE3.MAXISCQTDATA221 |
| CELL64.OUT17.TMIN | PCIE3.MAXISCQTDATA222 |
| CELL64.OUT18.TMIN | PCIE3.MAXISCQTDATA223 |
| CELL64.OUT19.TMIN | PCIE3.MAXISCQTDATA224 |
| CELL64.OUT20.TMIN | PCIE3.MAXISCQTUSER26 |
| CELL64.OUT21.TMIN | PCIE3.MAXISCQTUSER27 |
| CELL64.OUT22.TMIN | PCIE3.CFGFCNPD2 |
| CELL64.OUT23.TMIN | PCIE3.CFGFCNPD3 |
| CELL65.IMUX.IMUX0.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET0 |
| CELL65.IMUX.IMUX1.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET1 |
| CELL65.IMUX.IMUX2.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET2 |
| CELL65.IMUX.IMUX3.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET3 |
| CELL65.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA13 |
| CELL65.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA14 |
| CELL65.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA15 |
| CELL65.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA16 |
| CELL65.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA125 |
| CELL65.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA126 |
| CELL65.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA127 |
| CELL65.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA128 |
| CELL65.IMUX.IMUX12.DELAY | PCIE3.CFGTPHSTTREADDATA25 |
| CELL65.IMUX.IMUX13.DELAY | PCIE3.CFGTPHSTTREADDATA26 |
| CELL65.IMUX.IMUX14.DELAY | PCIE3.CFGTPHSTTREADDATA27 |
| CELL65.IMUX.IMUX15.DELAY | PCIE3.CFGTPHSTTREADDATA28 |
| CELL65.IMUX.IMUX20.DELAY | PCIE3.PIPERX5SYNCHEADER1 |
| CELL65.IMUX.IMUX21.DELAY | PCIE3.PIPERX5SYNCHEADER0 |
| CELL65.IMUX.IMUX22.DELAY | PCIE3.PIPERX5STARTBLOCK |
| CELL65.IMUX.IMUX23.DELAY | PCIE3.PIPERX5DATAVALID |
| CELL65.IMUX.IMUX32.DELAY | PCIE3.PIPERX5DATA27 |
| CELL65.IMUX.IMUX33.DELAY | PCIE3.PIPERX5DATA26 |
| CELL65.IMUX.IMUX34.DELAY | PCIE3.PIPERX4DATA31 |
| CELL65.IMUX.IMUX35.DELAY | PCIE3.PIPERX4DATA30 |
| CELL65.IMUX.IMUX36.DELAY | PCIE3.PIPERX5DATA25 |
| CELL65.IMUX.IMUX37.DELAY | PCIE3.PIPERX5DATA24 |
| CELL65.IMUX.IMUX38.DELAY | PCIE3.PIPERX4DATA29 |
| CELL65.IMUX.IMUX39.DELAY | PCIE3.PIPERX4DATA28 |
| CELL65.OUT0.TMIN | PCIE3.PIPETX5DATA12 |
| CELL65.OUT1.TMIN | PCIE3.PIPERX0EQLPLFFS2 |
| CELL65.OUT2.TMIN | PCIE3.PIPETX5DATA14 |
| CELL65.OUT3.TMIN | PCIE3.PIPERX0EQLPLFFS3 |
| CELL65.OUT4.TMIN | PCIE3.PIPETX5DATA13 |
| CELL65.OUT5.TMIN | PCIE3.PIPERX0EQLPLFFS4 |
| CELL65.OUT6.TMIN | PCIE3.PIPETX5DATA15 |
| CELL65.OUT7.TMIN | PCIE3.PIPERX0EQLPLFFS5 |
| CELL65.OUT8.TMIN | PCIE3.MAXISCQTDATA121 |
| CELL65.OUT9.TMIN | PCIE3.PIPETX4DATA16 |
| CELL65.OUT10.TMIN | PCIE3.MAXISCQTDATA122 |
| CELL65.OUT11.TMIN | PCIE3.PIPETX4DATA18 |
| CELL65.OUT12.TMIN | PCIE3.MAXISCQTDATA123 |
| CELL65.OUT13.TMIN | PCIE3.PIPETX4DATA17 |
| CELL65.OUT14.TMIN | PCIE3.MAXISCQTDATA124 |
| CELL65.OUT15.TMIN | PCIE3.PIPETX4DATA19 |
| CELL65.OUT16.TMIN | PCIE3.PIPETX5CHARISK1 |
| CELL65.OUT17.TMIN | PCIE3.MAXISCQTDATA225 |
| CELL65.OUT18.TMIN | PCIE3.CFGFCNPD4 |
| CELL65.OUT19.TMIN | PCIE3.CFGFCNPD5 |
| CELL65.OUT20.TMIN | PCIE3.PIPETX5SYNCHEADER1 |
| CELL65.OUT21.TMIN | PCIE3.PIPETX5SYNCHEADER0 |
| CELL65.OUT22.TMIN | PCIE3.PIPETX5STARTBLOCK |
| CELL65.OUT23.TMIN | PCIE3.PIPETX5DATAVALID |
| CELL66.IMUX.IMUX0.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET4 |
| CELL66.IMUX.IMUX1.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET5 |
| CELL66.IMUX.IMUX2.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET6 |
| CELL66.IMUX.IMUX3.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET7 |
| CELL66.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA9 |
| CELL66.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA10 |
| CELL66.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA11 |
| CELL66.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA12 |
| CELL66.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA129 |
| CELL66.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA130 |
| CELL66.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA131 |
| CELL66.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA132 |
| CELL66.IMUX.IMUX12.DELAY | PCIE3.CFGTPHSTTREADDATA29 |
| CELL66.IMUX.IMUX13.DELAY | PCIE3.CFGTPHSTTREADDATA30 |
| CELL66.IMUX.IMUX14.DELAY | PCIE3.CFGTPHSTTREADDATA31 |
| CELL66.IMUX.IMUX15.DELAY | PCIE3.CFGTPHSTTREADDATAVALID |
| CELL66.IMUX.IMUX20.DELAY | PCIE3.PIPERX4SYNCHEADER1 |
| CELL66.IMUX.IMUX21.DELAY | PCIE3.PIPERX4SYNCHEADER0 |
| CELL66.IMUX.IMUX22.DELAY | PCIE3.PIPERX4STARTBLOCK |
| CELL66.IMUX.IMUX23.DELAY | PCIE3.PIPERX4DATAVALID |
| CELL66.IMUX.IMUX32.DELAY | PCIE3.PIPERX4DATA27 |
| CELL66.IMUX.IMUX33.DELAY | PCIE3.PIPERX4DATA26 |
| CELL66.IMUX.IMUX34.DELAY | PCIE3.PIPERX5DATA23 |
| CELL66.IMUX.IMUX35.DELAY | PCIE3.PIPERX5DATA22 |
| CELL66.IMUX.IMUX36.DELAY | PCIE3.PIPERX4DATA25 |
| CELL66.IMUX.IMUX37.DELAY | PCIE3.PIPERX4DATA24 |
| CELL66.IMUX.IMUX38.DELAY | PCIE3.PIPERX5DATA21 |
| CELL66.IMUX.IMUX39.DELAY | PCIE3.PIPERX5DATA20 |
| CELL66.OUT0.TMIN | PCIE3.PIPETX4DATA12 |
| CELL66.OUT1.TMIN | PCIE3.PIPERX1EQLPLFFS0 |
| CELL66.OUT2.TMIN | PCIE3.PIPETX4DATA14 |
| CELL66.OUT3.TMIN | PCIE3.PIPERX1EQLPLFFS1 |
| CELL66.OUT4.TMIN | PCIE3.PIPETX4DATA13 |
| CELL66.OUT5.TMIN | PCIE3.PIPERX1EQLPLFFS2 |
| CELL66.OUT6.TMIN | PCIE3.PIPETX4DATA15 |
| CELL66.OUT7.TMIN | PCIE3.PIPERX1EQLPLFFS3 |
| CELL66.OUT8.TMIN | PCIE3.MAXISCQTDATA117 |
| CELL66.OUT9.TMIN | PCIE3.PIPETX5DATA8 |
| CELL66.OUT10.TMIN | PCIE3.MAXISCQTDATA118 |
| CELL66.OUT11.TMIN | PCIE3.PIPETX5DATA10 |
| CELL66.OUT12.TMIN | PCIE3.MAXISCQTDATA119 |
| CELL66.OUT13.TMIN | PCIE3.PIPETX5DATA9 |
| CELL66.OUT14.TMIN | PCIE3.MAXISCQTDATA120 |
| CELL66.OUT15.TMIN | PCIE3.PIPETX5DATA11 |
| CELL66.OUT16.TMIN | PCIE3.PIPETX4CHARISK1 |
| CELL66.OUT17.TMIN | PCIE3.MAXISCQTDATA226 |
| CELL66.OUT18.TMIN | PCIE3.CFGFCNPD6 |
| CELL66.OUT19.TMIN | PCIE3.CFGFCNPD7 |
| CELL66.OUT20.TMIN | PCIE3.PIPETX4SYNCHEADER1 |
| CELL66.OUT21.TMIN | PCIE3.PIPETX4SYNCHEADER0 |
| CELL66.OUT22.TMIN | PCIE3.PIPETX4STARTBLOCK |
| CELL66.OUT23.TMIN | PCIE3.PIPETX4DATAVALID |
| CELL67.IMUX.IMUX0.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET8 |
| CELL67.IMUX.IMUX1.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET9 |
| CELL67.IMUX.IMUX2.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET10 |
| CELL67.IMUX.IMUX3.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET11 |
| CELL67.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA5 |
| CELL67.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA6 |
| CELL67.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA7 |
| CELL67.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA8 |
| CELL67.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA133 |
| CELL67.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA134 |
| CELL67.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA135 |
| CELL67.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA136 |
| CELL67.IMUX.IMUX12.DELAY | PCIE3.MAXISCQTREADY21 |
| CELL67.IMUX.IMUX13.DELAY | PCIE3.CFGDSN4 |
| CELL67.IMUX.IMUX14.DELAY | PCIE3.CFGDSN5 |
| CELL67.IMUX.IMUX15.DELAY | PCIE3.CFGDSN6 |
| CELL67.IMUX.IMUX16.DELAY | PCIE3.DRPEN |
| CELL67.IMUX.IMUX17.DELAY | PCIE3.DRPWE |
| CELL67.IMUX.IMUX18.DELAY | PCIE3.DRPADDR0 |
| CELL67.IMUX.IMUX19.DELAY | PCIE3.DRPADDR1 |
| CELL67.IMUX.IMUX32.DELAY | PCIE3.PIPERX5DATA19 |
| CELL67.IMUX.IMUX33.DELAY | PCIE3.PIPERX5DATA18 |
| CELL67.IMUX.IMUX34.DELAY | PCIE3.PIPERX4DATA23 |
| CELL67.IMUX.IMUX35.DELAY | PCIE3.PIPERX4DATA22 |
| CELL67.IMUX.IMUX36.DELAY | PCIE3.PIPERX5DATA17 |
| CELL67.IMUX.IMUX37.DELAY | PCIE3.PIPERX5DATA16 |
| CELL67.IMUX.IMUX38.DELAY | PCIE3.PIPERX4DATA21 |
| CELL67.IMUX.IMUX39.DELAY | PCIE3.PIPERX4DATA20 |
| CELL67.OUT0.TMIN | PCIE3.PIPETX5DATA4 |
| CELL67.OUT1.TMIN | PCIE3.PIPERX1EQLPLFFS4 |
| CELL67.OUT2.TMIN | PCIE3.PIPETX5DATA6 |
| CELL67.OUT3.TMIN | PCIE3.PIPETX5ELECIDLE |
| CELL67.OUT4.TMIN | PCIE3.PIPETX5DATA5 |
| CELL67.OUT5.TMIN | PCIE3.PIPETX5POWERDOWN0 |
| CELL67.OUT6.TMIN | PCIE3.PIPETX5DATA7 |
| CELL67.OUT7.TMIN | PCIE3.PIPETX5POWERDOWN1 |
| CELL67.OUT8.TMIN | PCIE3.PIPERX1EQLPLFFS5 |
| CELL67.OUT9.TMIN | PCIE3.PIPETX4DATA8 |
| CELL67.OUT10.TMIN | PCIE3.PIPERX2EQLPLFFS0 |
| CELL67.OUT11.TMIN | PCIE3.PIPETX4DATA10 |
| CELL67.OUT12.TMIN | PCIE3.PIPERX2EQLPLFFS1 |
| CELL67.OUT13.TMIN | PCIE3.PIPETX4DATA9 |
| CELL67.OUT14.TMIN | PCIE3.MAXISCQTDATA113 |
| CELL67.OUT15.TMIN | PCIE3.PIPETX4DATA11 |
| CELL67.OUT16.TMIN | PCIE3.PIPETX5CHARISK0 |
| CELL67.OUT17.TMIN | PCIE3.MAXISCQTDATA114 |
| CELL67.OUT18.TMIN | PCIE3.MAXISCQTDATA115 |
| CELL67.OUT19.TMIN | PCIE3.MAXISCQTDATA116 |
| CELL67.OUT20.TMIN | PCIE3.MAXISCQTDATA227 |
| CELL67.OUT21.TMIN | PCIE3.MAXISCQTDATA228 |
| CELL67.OUT22.TMIN | PCIE3.CFGFCNPD8 |
| CELL67.OUT23.TMIN | PCIE3.CFGFCNPD9 |
| CELL68.IMUX.IMUX0.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET12 |
| CELL68.IMUX.IMUX1.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET13 |
| CELL68.IMUX.IMUX2.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET14 |
| CELL68.IMUX.IMUX3.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET15 |
| CELL68.IMUX.IMUX4.DELAY | PCIE3.SAXISCCTDATA1 |
| CELL68.IMUX.IMUX5.DELAY | PCIE3.SAXISCCTDATA2 |
| CELL68.IMUX.IMUX6.DELAY | PCIE3.SAXISCCTDATA3 |
| CELL68.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA4 |
| CELL68.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA137 |
| CELL68.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA138 |
| CELL68.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA139 |
| CELL68.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA140 |
| CELL68.IMUX.IMUX12.DELAY | PCIE3.CFGDSN7 |
| CELL68.IMUX.IMUX13.DELAY | PCIE3.CFGDSN8 |
| CELL68.IMUX.IMUX14.DELAY | PCIE3.CFGDSN9 |
| CELL68.IMUX.IMUX15.DELAY | PCIE3.CFGDSN10 |
| CELL68.IMUX.IMUX16.DELAY | PCIE3.DRPADDR2 |
| CELL68.IMUX.IMUX17.DELAY | PCIE3.DRPADDR3 |
| CELL68.IMUX.IMUX18.DELAY | PCIE3.DRPADDR4 |
| CELL68.IMUX.IMUX19.DELAY | PCIE3.DRPADDR5 |
| CELL68.IMUX.IMUX32.DELAY | PCIE3.PIPERX4DATA19 |
| CELL68.IMUX.IMUX33.DELAY | PCIE3.PIPERX4DATA18 |
| CELL68.IMUX.IMUX34.DELAY | PCIE3.PIPERX5DATA15 |
| CELL68.IMUX.IMUX35.DELAY | PCIE3.PIPERX5DATA14 |
| CELL68.IMUX.IMUX36.DELAY | PCIE3.PIPERX4DATA17 |
| CELL68.IMUX.IMUX37.DELAY | PCIE3.PIPERX4DATA16 |
| CELL68.IMUX.IMUX38.DELAY | PCIE3.PIPERX5DATA13 |
| CELL68.IMUX.IMUX39.DELAY | PCIE3.PIPERX5DATA12 |
| CELL68.OUT0.TMIN | PCIE3.PIPETX4DATA4 |
| CELL68.OUT1.TMIN | PCIE3.PIPERX5POLARITY |
| CELL68.OUT2.TMIN | PCIE3.PIPETX4DATA6 |
| CELL68.OUT3.TMIN | PCIE3.PIPETX4ELECIDLE |
| CELL68.OUT4.TMIN | PCIE3.PIPETX4DATA5 |
| CELL68.OUT5.TMIN | PCIE3.PIPETX4POWERDOWN0 |
| CELL68.OUT6.TMIN | PCIE3.PIPETX4DATA7 |
| CELL68.OUT7.TMIN | PCIE3.PIPETX4POWERDOWN1 |
| CELL68.OUT8.TMIN | PCIE3.PIPETX5COMPLIANCE |
| CELL68.OUT9.TMIN | PCIE3.PIPETX5DATA0 |
| CELL68.OUT10.TMIN | PCIE3.PIPERX2EQLPLFFS2 |
| CELL68.OUT11.TMIN | PCIE3.PIPETX5DATA2 |
| CELL68.OUT12.TMIN | PCIE3.PIPERX2EQLPLFFS3 |
| CELL68.OUT13.TMIN | PCIE3.PIPETX5DATA1 |
| CELL68.OUT14.TMIN | PCIE3.PIPERX2EQLPLFFS4 |
| CELL68.OUT15.TMIN | PCIE3.PIPETX5DATA3 |
| CELL68.OUT16.TMIN | PCIE3.PIPETX4CHARISK0 |
| CELL68.OUT17.TMIN | PCIE3.PIPERX2EQLPLFFS5 |
| CELL68.OUT18.TMIN | PCIE3.MAXISCQTDATA109 |
| CELL68.OUT19.TMIN | PCIE3.MAXISCQTDATA110 |
| CELL68.OUT20.TMIN | PCIE3.MAXISCQTDATA111 |
| CELL68.OUT21.TMIN | PCIE3.MAXISCQTDATA112 |
| CELL68.OUT22.TMIN | PCIE3.CFGFCNPD10 |
| CELL68.OUT23.TMIN | PCIE3.CFGFCNPD11 |
| CELL69.IMUX.IMUX0.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET16 |
| CELL69.IMUX.IMUX1.DELAY | PCIE3.PIPERX4EQLPNEWTXCOEFFORPRESET17 |
| CELL69.IMUX.IMUX2.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET0 |
| CELL69.IMUX.IMUX3.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET1 |
| CELL69.IMUX.IMUX4.DELAY | PCIE3.PLGEN3PCSRXSYNCDONE5 |
| CELL69.IMUX.IMUX5.DELAY | PCIE3.PLGEN3PCSRXSYNCDONE6 |
| CELL69.IMUX.IMUX6.DELAY | PCIE3.PLGEN3PCSRXSYNCDONE7 |
| CELL69.IMUX.IMUX7.DELAY | PCIE3.SAXISCCTDATA0 |
| CELL69.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA141 |
| CELL69.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA142 |
| CELL69.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA143 |
| CELL69.IMUX.IMUX11.DELAY | PCIE3.DRPADDR6 |
| CELL69.IMUX.IMUX12.DELAY | PCIE3.DRPADDR7 |
| CELL69.IMUX.IMUX13.DELAY | PCIE3.DRPADDR8 |
| CELL69.IMUX.IMUX14.DELAY | PCIE3.DRPADDR9 |
| CELL69.IMUX.IMUX16.DELAY | PCIE3.PIPERX5CHARISK1 |
| CELL69.IMUX.IMUX32.DELAY | PCIE3.PIPERX5DATA11 |
| CELL69.IMUX.IMUX33.DELAY | PCIE3.PIPERX5DATA10 |
| CELL69.IMUX.IMUX34.DELAY | PCIE3.PIPERX4DATA15 |
| CELL69.IMUX.IMUX35.DELAY | PCIE3.PIPERX4DATA14 |
| CELL69.IMUX.IMUX36.DELAY | PCIE3.PIPERX5DATA9 |
| CELL69.IMUX.IMUX37.DELAY | PCIE3.PIPERX5DATA8 |
| CELL69.IMUX.IMUX38.DELAY | PCIE3.PIPERX4DATA13 |
| CELL69.IMUX.IMUX39.DELAY | PCIE3.PIPERX4DATA12 |
| CELL69.IMUX.IMUX41.DELAY | PCIE3.PIPERX5ELECIDLE |
| CELL69.IMUX.IMUX42.DELAY | PCIE3.PIPERX5STATUS2 |
| CELL69.IMUX.IMUX43.DELAY | PCIE3.PIPERX5STATUS1 |
| CELL69.IMUX.IMUX44.DELAY | PCIE3.PIPERX5STATUS0 |
| CELL69.OUT0.TMIN | PCIE3.PIPERX3EQLPLFFS0 |
| CELL69.OUT1.TMIN | PCIE3.PIPERX4POLARITY |
| CELL69.OUT2.TMIN | PCIE3.PIPERX3EQLPLFFS1 |
| CELL69.OUT3.TMIN | PCIE3.PIPERX3EQLPLFFS2 |
| CELL69.OUT4.TMIN | PCIE3.PIPERX3EQLPLFFS3 |
| CELL69.OUT5.TMIN | PCIE3.MAXISCQTDATA105 |
| CELL69.OUT6.TMIN | PCIE3.MAXISCQTDATA106 |
| CELL69.OUT7.TMIN | PCIE3.MAXISCQTDATA107 |
| CELL69.OUT8.TMIN | PCIE3.PIPETX4COMPLIANCE |
| CELL69.OUT9.TMIN | PCIE3.PIPETX4DATA0 |
| CELL69.OUT10.TMIN | PCIE3.MAXISCQTDATA108 |
| CELL69.OUT11.TMIN | PCIE3.PIPETX4DATA2 |
| CELL69.OUT12.TMIN | PCIE3.MAXISCQTDATA229 |
| CELL69.OUT13.TMIN | PCIE3.PIPETX4DATA1 |
| CELL69.OUT14.TMIN | PCIE3.MAXISCQTDATA230 |
| CELL69.OUT15.TMIN | PCIE3.PIPETX4DATA3 |
| CELL69.OUT16.TMIN | PCIE3.MAXISCQTDATA231 |
| CELL69.OUT17.TMIN | PCIE3.MAXISCQTDATA232 |
| CELL69.OUT18.TMIN | PCIE3.MAXISCQTUSER28 |
| CELL69.OUT19.TMIN | PCIE3.MAXISCQTUSER29 |
| CELL69.OUT20.TMIN | PCIE3.MAXISCQTUSER30 |
| CELL69.OUT21.TMIN | PCIE3.MAXISCQTUSER31 |
| CELL69.OUT22.TMIN | PCIE3.CFGFCCPLH0 |
| CELL69.OUT23.TMIN | PCIE3.CFGFCCPLH1 |
| CELL70.IMUX.IMUX0.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET2 |
| CELL70.IMUX.IMUX1.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET3 |
| CELL70.IMUX.IMUX2.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET4 |
| CELL70.IMUX.IMUX3.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET5 |
| CELL70.IMUX.IMUX4.DELAY | PCIE3.PLGEN3PCSRXSYNCDONE1 |
| CELL70.IMUX.IMUX5.DELAY | PCIE3.PLGEN3PCSRXSYNCDONE2 |
| CELL70.IMUX.IMUX6.DELAY | PCIE3.PLGEN3PCSRXSYNCDONE3 |
| CELL70.IMUX.IMUX7.DELAY | PCIE3.PLGEN3PCSRXSYNCDONE4 |
| CELL70.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA144 |
| CELL70.IMUX.IMUX9.DELAY | PCIE3.DRPADDR10 |
| CELL70.IMUX.IMUX10.DELAY | PCIE3.DRPDI0 |
| CELL70.IMUX.IMUX11.DELAY | PCIE3.DRPDI1 |
| CELL70.IMUX.IMUX12.DELAY | PCIE3.DRPDI2 |
| CELL70.IMUX.IMUX16.DELAY | PCIE3.PIPERX4CHARISK1 |
| CELL70.IMUX.IMUX32.DELAY | PCIE3.PIPERX4DATA11 |
| CELL70.IMUX.IMUX33.DELAY | PCIE3.PIPERX4DATA10 |
| CELL70.IMUX.IMUX34.DELAY | PCIE3.PIPERX5DATA7 |
| CELL70.IMUX.IMUX35.DELAY | PCIE3.PIPERX5DATA6 |
| CELL70.IMUX.IMUX36.DELAY | PCIE3.PIPERX4DATA9 |
| CELL70.IMUX.IMUX37.DELAY | PCIE3.PIPERX4DATA8 |
| CELL70.IMUX.IMUX38.DELAY | PCIE3.PIPERX5DATA5 |
| CELL70.IMUX.IMUX39.DELAY | PCIE3.PIPERX5DATA4 |
| CELL70.IMUX.IMUX40.DELAY | PCIE3.PIPERX5VALID |
| CELL70.IMUX.IMUX41.DELAY | PCIE3.PIPERX4ELECIDLE |
| CELL70.IMUX.IMUX42.DELAY | PCIE3.PIPERX4STATUS2 |
| CELL70.IMUX.IMUX43.DELAY | PCIE3.PIPERX4STATUS1 |
| CELL70.IMUX.IMUX44.DELAY | PCIE3.PIPERX4STATUS0 |
| CELL70.IMUX.IMUX45.DELAY | PCIE3.PIPERX5PHYSTATUS |
| CELL70.OUT0.TMIN | PCIE3.PIPERX3EQLPLFFS4 |
| CELL70.OUT1.TMIN | PCIE3.PIPERX3EQLPLFFS5 |
| CELL70.OUT2.TMIN | PCIE3.PIPERX4EQLPLFFS0 |
| CELL70.OUT3.TMIN | PCIE3.PIPERX4EQLPLFFS1 |
| CELL70.OUT4.TMIN | PCIE3.MAXISCQTDATA101 |
| CELL70.OUT5.TMIN | PCIE3.MAXISCQTDATA102 |
| CELL70.OUT6.TMIN | PCIE3.PIPETXMARGIN2 |
| CELL70.OUT7.TMIN | PCIE3.MAXISCQTDATA103 |
| CELL70.OUT8.TMIN | PCIE3.MAXISCQTDATA104 |
| CELL70.OUT9.TMIN | PCIE3.MAXISCQTDATA233 |
| CELL70.OUT10.TMIN | PCIE3.MAXISCQTDATA234 |
| CELL70.OUT11.TMIN | PCIE3.MAXISCQTDATA235 |
| CELL70.OUT12.TMIN | PCIE3.MAXISCQTDATA236 |
| CELL70.OUT13.TMIN | PCIE3.MAXISCQTUSER32 |
| CELL70.OUT14.TMIN | PCIE3.MAXISCQTUSER33 |
| CELL70.OUT15.TMIN | PCIE3.MAXISCQTUSER34 |
| CELL70.OUT16.TMIN | PCIE3.PIPETXMARGIN1 |
| CELL70.OUT17.TMIN | PCIE3.MAXISCQTUSER35 |
| CELL70.OUT18.TMIN | PCIE3.PIPETXMARGIN0 |
| CELL70.OUT19.TMIN | PCIE3.SAXISCCTREADY3 |
| CELL70.OUT20.TMIN | PCIE3.CFGFCCPLH2 |
| CELL70.OUT21.TMIN | PCIE3.CFGFCCPLH3 |
| CELL70.OUT22.TMIN | PCIE3.CFGFCCPLH4 |
| CELL70.OUT23.TMIN | PCIE3.CFGEXTREADRECEIVED |
| CELL71.IMUX.IMUX0.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET6 |
| CELL71.IMUX.IMUX1.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET7 |
| CELL71.IMUX.IMUX2.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET8 |
| CELL71.IMUX.IMUX3.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET9 |
| CELL71.IMUX.IMUX4.DELAY | PCIE3.PLEQRESETEIEOSCOUNT |
| CELL71.IMUX.IMUX5.DELAY | PCIE3.PLDISABLESCRAMBLER |
| CELL71.IMUX.IMUX6.DELAY | PCIE3.PLGEN3PCSDISABLE |
| CELL71.IMUX.IMUX7.DELAY | PCIE3.PLGEN3PCSRXSYNCDONE0 |
| CELL71.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA145 |
| CELL71.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA146 |
| CELL71.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA147 |
| CELL71.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA148 |
| CELL71.IMUX.IMUX12.DELAY | PCIE3.CFGDSN11 |
| CELL71.IMUX.IMUX13.DELAY | PCIE3.CFGDSN12 |
| CELL71.IMUX.IMUX14.DELAY | PCIE3.CFGDSN13 |
| CELL71.IMUX.IMUX15.DELAY | PCIE3.DRPDI3 |
| CELL71.IMUX.IMUX16.DELAY | PCIE3.PIPERX5CHARISK0 |
| CELL71.IMUX.IMUX17.DELAY | PCIE3.DRPDI4 |
| CELL71.IMUX.IMUX18.DELAY | PCIE3.DRPDI5 |
| CELL71.IMUX.IMUX19.DELAY | PCIE3.DRPDI6 |
| CELL71.IMUX.IMUX32.DELAY | PCIE3.PIPERX5DATA3 |
| CELL71.IMUX.IMUX33.DELAY | PCIE3.PIPERX5DATA2 |
| CELL71.IMUX.IMUX34.DELAY | PCIE3.PIPERX4DATA7 |
| CELL71.IMUX.IMUX35.DELAY | PCIE3.PIPERX4DATA6 |
| CELL71.IMUX.IMUX36.DELAY | PCIE3.PIPERX5DATA1 |
| CELL71.IMUX.IMUX37.DELAY | PCIE3.PIPERX5DATA0 |
| CELL71.IMUX.IMUX38.DELAY | PCIE3.PIPERX4DATA5 |
| CELL71.IMUX.IMUX39.DELAY | PCIE3.PIPERX4DATA4 |
| CELL71.IMUX.IMUX40.DELAY | PCIE3.PIPERX4VALID |
| CELL71.IMUX.IMUX45.DELAY | PCIE3.PIPERX4PHYSTATUS |
| CELL71.OUT0.TMIN | PCIE3.PIPERX4EQLPLFFS2 |
| CELL71.OUT1.TMIN | PCIE3.PIPERX4EQLPLFFS3 |
| CELL71.OUT2.TMIN | PCIE3.PIPERX4EQLPLFFS4 |
| CELL71.OUT3.TMIN | PCIE3.PIPERX4EQLPLFFS5 |
| CELL71.OUT4.TMIN | PCIE3.MAXISCQTDATA97 |
| CELL71.OUT5.TMIN | PCIE3.MAXISCQTDATA98 |
| CELL71.OUT6.TMIN | PCIE3.MAXISCQTDATA99 |
| CELL71.OUT7.TMIN | PCIE3.MAXISCQTDATA100 |
| CELL71.OUT8.TMIN | PCIE3.MAXISCQTDATA237 |
| CELL71.OUT9.TMIN | PCIE3.MAXISCQTDATA238 |
| CELL71.OUT10.TMIN | PCIE3.MAXISCQTDATA239 |
| CELL71.OUT11.TMIN | PCIE3.MAXISCQTDATA240 |
| CELL71.OUT12.TMIN | PCIE3.MAXISCQTUSER36 |
| CELL71.OUT13.TMIN | PCIE3.MAXISCQTUSER37 |
| CELL71.OUT14.TMIN | PCIE3.MAXISCQTUSER38 |
| CELL71.OUT15.TMIN | PCIE3.MAXISCQTUSER39 |
| CELL71.OUT16.TMIN | PCIE3.CFGFCCPLH5 |
| CELL71.OUT17.TMIN | PCIE3.CFGFCCPLH6 |
| CELL71.OUT18.TMIN | PCIE3.CFGFCCPLH7 |
| CELL71.OUT19.TMIN | PCIE3.CFGFCCPLD0 |
| CELL71.OUT20.TMIN | PCIE3.CFGEXTWRITERECEIVED |
| CELL71.OUT21.TMIN | PCIE3.CFGEXTREGISTERNUMBER0 |
| CELL71.OUT22.TMIN | PCIE3.CFGEXTREGISTERNUMBER1 |
| CELL71.OUT23.TMIN | PCIE3.CFGEXTREGISTERNUMBER2 |
| CELL72.IMUX.IMUX0.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET10 |
| CELL72.IMUX.IMUX1.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET11 |
| CELL72.IMUX.IMUX2.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET12 |
| CELL72.IMUX.IMUX3.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET13 |
| CELL72.IMUX.IMUX4.DELAY | PCIE3.PIPEEQLF2 |
| CELL72.IMUX.IMUX5.DELAY | PCIE3.PIPEEQLF3 |
| CELL72.IMUX.IMUX6.DELAY | PCIE3.PIPEEQLF4 |
| CELL72.IMUX.IMUX7.DELAY | PCIE3.PIPEEQLF5 |
| CELL72.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA149 |
| CELL72.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA150 |
| CELL72.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA151 |
| CELL72.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA152 |
| CELL72.IMUX.IMUX12.DELAY | PCIE3.CFGDSN14 |
| CELL72.IMUX.IMUX13.DELAY | PCIE3.CFGDSN15 |
| CELL72.IMUX.IMUX14.DELAY | PCIE3.CFGDSN16 |
| CELL72.IMUX.IMUX15.DELAY | PCIE3.CFGDSN17 |
| CELL72.IMUX.IMUX16.DELAY | PCIE3.PIPERX4CHARISK0 |
| CELL72.IMUX.IMUX17.DELAY | PCIE3.CFGSUBSYSVENDID15 |
| CELL72.IMUX.IMUX18.DELAY | PCIE3.CFGDSPORTNUMBER0 |
| CELL72.IMUX.IMUX19.DELAY | PCIE3.CFGDSPORTNUMBER1 |
| CELL72.IMUX.IMUX20.DELAY | PCIE3.DRPDI7 |
| CELL72.IMUX.IMUX21.DELAY | PCIE3.DRPDI8 |
| CELL72.IMUX.IMUX22.DELAY | PCIE3.DRPDI9 |
| CELL72.IMUX.IMUX23.DELAY | PCIE3.DRPDI10 |
| CELL72.IMUX.IMUX32.DELAY | PCIE3.PIPERX4DATA3 |
| CELL72.IMUX.IMUX33.DELAY | PCIE3.PIPERX4DATA2 |
| CELL72.IMUX.IMUX36.DELAY | PCIE3.PIPERX4DATA1 |
| CELL72.IMUX.IMUX37.DELAY | PCIE3.PIPERX4DATA0 |
| CELL72.OUT0.TMIN | PCIE3.PIPERX5EQLPLFFS0 |
| CELL72.OUT1.TMIN | PCIE3.PIPERX5EQLPLFFS1 |
| CELL72.OUT2.TMIN | PCIE3.PIPERX5EQLPLFFS2 |
| CELL72.OUT3.TMIN | PCIE3.PIPERX5EQLPLFFS3 |
| CELL72.OUT4.TMIN | PCIE3.MAXISCQTDATA93 |
| CELL72.OUT5.TMIN | PCIE3.MAXISCQTDATA94 |
| CELL72.OUT6.TMIN | PCIE3.MAXISCQTDATA95 |
| CELL72.OUT7.TMIN | PCIE3.MAXISCQTDATA96 |
| CELL72.OUT8.TMIN | PCIE3.MAXISCQTDATA241 |
| CELL72.OUT9.TMIN | PCIE3.MAXISCQTDATA242 |
| CELL72.OUT10.TMIN | PCIE3.MAXISCQTDATA243 |
| CELL72.OUT11.TMIN | PCIE3.MAXISCQTDATA244 |
| CELL72.OUT12.TMIN | PCIE3.MAXISCQTUSER40 |
| CELL72.OUT13.TMIN | PCIE3.MAXISCQTUSER41 |
| CELL72.OUT14.TMIN | PCIE3.MAXISCQTUSER42 |
| CELL72.OUT15.TMIN | PCIE3.MAXISCQTUSER43 |
| CELL72.OUT16.TMIN | PCIE3.CFGFCCPLD1 |
| CELL72.OUT17.TMIN | PCIE3.CFGFCCPLD2 |
| CELL72.OUT18.TMIN | PCIE3.CFGFCCPLD3 |
| CELL72.OUT19.TMIN | PCIE3.CFGFCCPLD4 |
| CELL72.OUT20.TMIN | PCIE3.CFGEXTREGISTERNUMBER3 |
| CELL72.OUT21.TMIN | PCIE3.CFGEXTREGISTERNUMBER4 |
| CELL72.OUT22.TMIN | PCIE3.CFGEXTREGISTERNUMBER5 |
| CELL72.OUT23.TMIN | PCIE3.CFGEXTREGISTERNUMBER6 |
| CELL73.IMUX.IMUX0.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET14 |
| CELL73.IMUX.IMUX1.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET15 |
| CELL73.IMUX.IMUX2.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET16 |
| CELL73.IMUX.IMUX3.DELAY | PCIE3.PIPERX5EQLPNEWTXCOEFFORPRESET17 |
| CELL73.IMUX.IMUX4.DELAY | PCIE3.PIPEEQFS4 |
| CELL73.IMUX.IMUX5.DELAY | PCIE3.PIPEEQFS5 |
| CELL73.IMUX.IMUX6.DELAY | PCIE3.PIPEEQLF0 |
| CELL73.IMUX.IMUX7.DELAY | PCIE3.PIPEEQLF1 |
| CELL73.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA153 |
| CELL73.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA154 |
| CELL73.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA155 |
| CELL73.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA156 |
| CELL73.IMUX.IMUX12.DELAY | PCIE3.CFGDSN18 |
| CELL73.IMUX.IMUX13.DELAY | PCIE3.CFGDSN19 |
| CELL73.IMUX.IMUX14.DELAY | PCIE3.CFGDSN20 |
| CELL73.IMUX.IMUX15.DELAY | PCIE3.CFGDSN21 |
| CELL73.IMUX.IMUX16.DELAY | PCIE3.CFGSUBSYSVENDID11 |
| CELL73.IMUX.IMUX17.DELAY | PCIE3.CFGSUBSYSVENDID12 |
| CELL73.IMUX.IMUX18.DELAY | PCIE3.CFGSUBSYSVENDID13 |
| CELL73.IMUX.IMUX19.DELAY | PCIE3.CFGSUBSYSVENDID14 |
| CELL73.IMUX.IMUX20.DELAY | PCIE3.CFGDSPORTNUMBER6 |
| CELL73.IMUX.IMUX21.DELAY | PCIE3.CFGDSPORTNUMBER7 |
| CELL73.IMUX.IMUX22.DELAY | PCIE3.CFGDSBUSNUMBER0 |
| CELL73.IMUX.IMUX23.DELAY | PCIE3.CFGDSBUSNUMBER1 |
| CELL73.IMUX.IMUX24.DELAY | PCIE3.DRPDI11 |
| CELL73.IMUX.IMUX25.DELAY | PCIE3.DRPDI12 |
| CELL73.IMUX.IMUX26.DELAY | PCIE3.DRPDI13 |
| CELL73.IMUX.IMUX27.DELAY | PCIE3.DRPDI14 |
| CELL73.OUT0.TMIN | PCIE3.PIPERX5EQLPLFFS4 |
| CELL73.OUT1.TMIN | PCIE3.PIPERX5EQLPLFFS5 |
| CELL73.OUT2.TMIN | PCIE3.PIPERX6EQLPLFFS0 |
| CELL73.OUT3.TMIN | PCIE3.PIPERX6EQLPLFFS1 |
| CELL73.OUT4.TMIN | PCIE3.MAXISCQTDATA89 |
| CELL73.OUT5.TMIN | PCIE3.MAXISCQTDATA90 |
| CELL73.OUT6.TMIN | PCIE3.MAXISCQTDATA91 |
| CELL73.OUT7.TMIN | PCIE3.MAXISCQTDATA92 |
| CELL73.OUT8.TMIN | PCIE3.MAXISCQTDATA245 |
| CELL73.OUT9.TMIN | PCIE3.MAXISCQTDATA246 |
| CELL73.OUT10.TMIN | PCIE3.MAXISCQTDATA247 |
| CELL73.OUT11.TMIN | PCIE3.MAXISCQTDATA248 |
| CELL73.OUT12.TMIN | PCIE3.MAXISCQTUSER44 |
| CELL73.OUT13.TMIN | PCIE3.MAXISCQTUSER45 |
| CELL73.OUT14.TMIN | PCIE3.MAXISCQTUSER46 |
| CELL73.OUT15.TMIN | PCIE3.MAXISCQTUSER47 |
| CELL73.OUT16.TMIN | PCIE3.CFGFCCPLD5 |
| CELL73.OUT17.TMIN | PCIE3.CFGFCCPLD6 |
| CELL73.OUT18.TMIN | PCIE3.CFGFCCPLD7 |
| CELL73.OUT19.TMIN | PCIE3.CFGFCCPLD8 |
| CELL73.OUT20.TMIN | PCIE3.CFGEXTREGISTERNUMBER7 |
| CELL73.OUT21.TMIN | PCIE3.CFGEXTREGISTERNUMBER8 |
| CELL73.OUT22.TMIN | PCIE3.CFGEXTREGISTERNUMBER9 |
| CELL73.OUT23.TMIN | PCIE3.CFGEXTFUNCTIONNUMBER0 |
| CELL74.IMUX.CLK1 | PCIE3.DRPCLK |
| CELL74.IMUX.IMUX0.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET0 |
| CELL74.IMUX.IMUX1.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET1 |
| CELL74.IMUX.IMUX2.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET2 |
| CELL74.IMUX.IMUX3.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET3 |
| CELL74.IMUX.IMUX4.DELAY | PCIE3.PIPEEQFS0 |
| CELL74.IMUX.IMUX5.DELAY | PCIE3.PIPEEQFS1 |
| CELL74.IMUX.IMUX6.DELAY | PCIE3.PIPEEQFS2 |
| CELL74.IMUX.IMUX7.DELAY | PCIE3.PIPEEQFS3 |
| CELL74.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA157 |
| CELL74.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA158 |
| CELL74.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA159 |
| CELL74.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA160 |
| CELL74.IMUX.IMUX12.DELAY | PCIE3.CFGDSN22 |
| CELL74.IMUX.IMUX13.DELAY | PCIE3.CFGDSN23 |
| CELL74.IMUX.IMUX14.DELAY | PCIE3.CFGDSN24 |
| CELL74.IMUX.IMUX15.DELAY | PCIE3.CFGDSN25 |
| CELL74.IMUX.IMUX16.DELAY | PCIE3.CFGSUBSYSVENDID7 |
| CELL74.IMUX.IMUX17.DELAY | PCIE3.CFGSUBSYSVENDID8 |
| CELL74.IMUX.IMUX18.DELAY | PCIE3.CFGSUBSYSVENDID9 |
| CELL74.IMUX.IMUX19.DELAY | PCIE3.CFGSUBSYSVENDID10 |
| CELL74.IMUX.IMUX20.DELAY | PCIE3.CFGDSBUSNUMBER2 |
| CELL74.IMUX.IMUX21.DELAY | PCIE3.CFGDSBUSNUMBER3 |
| CELL74.IMUX.IMUX22.DELAY | PCIE3.CFGDSBUSNUMBER4 |
| CELL74.IMUX.IMUX23.DELAY | PCIE3.CFGDSBUSNUMBER5 |
| CELL74.IMUX.IMUX24.DELAY | PCIE3.DRPDI15 |
| CELL74.IMUX.IMUX25.DELAY | PCIE3.SCANMODEN |
| CELL74.IMUX.IMUX26.DELAY | PCIE3.SCANENABLEN |
| CELL74.IMUX.IMUX27.DELAY | PCIE3.SCANIN0 |
| CELL74.OUT0.TMIN | PCIE3.PIPERX6EQLPLFFS2 |
| CELL74.OUT1.TMIN | PCIE3.PIPERX6EQLPLFFS3 |
| CELL74.OUT2.TMIN | PCIE3.PIPERX6EQLPLFFS4 |
| CELL74.OUT3.TMIN | PCIE3.PIPERX6EQLPLFFS5 |
| CELL74.OUT4.TMIN | PCIE3.MAXISCQTDATA85 |
| CELL74.OUT5.TMIN | PCIE3.MAXISCQTDATA86 |
| CELL74.OUT6.TMIN | PCIE3.MAXISCQTDATA87 |
| CELL74.OUT7.TMIN | PCIE3.MAXISCQTDATA88 |
| CELL74.OUT8.TMIN | PCIE3.MAXISCQTDATA249 |
| CELL74.OUT9.TMIN | PCIE3.MAXISCQTDATA250 |
| CELL74.OUT10.TMIN | PCIE3.MAXISCQTDATA251 |
| CELL74.OUT11.TMIN | PCIE3.MAXISCQTDATA252 |
| CELL74.OUT12.TMIN | PCIE3.MAXISCQTUSER48 |
| CELL74.OUT13.TMIN | PCIE3.MAXISCQTUSER49 |
| CELL74.OUT14.TMIN | PCIE3.MAXISCQTUSER50 |
| CELL74.OUT15.TMIN | PCIE3.MAXISCQTUSER51 |
| CELL74.OUT16.TMIN | PCIE3.CFGFCCPLD9 |
| CELL74.OUT17.TMIN | PCIE3.CFGFCCPLD10 |
| CELL74.OUT18.TMIN | PCIE3.CFGFCCPLD11 |
| CELL74.OUT19.TMIN | PCIE3.CFGPERFUNCSTATUSDATA0 |
| CELL74.OUT20.TMIN | PCIE3.CFGEXTFUNCTIONNUMBER1 |
| CELL74.OUT21.TMIN | PCIE3.CFGEXTFUNCTIONNUMBER2 |
| CELL74.OUT22.TMIN | PCIE3.CFGEXTFUNCTIONNUMBER3 |
| CELL74.OUT23.TMIN | PCIE3.CFGEXTFUNCTIONNUMBER4 |
| CELL75.IMUX.CLK0 | PCIE3.PIPECLK |
| CELL75.IMUX.CLK1 | PCIE3.RECCLK |
| CELL75.IMUX.IMUX0.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET4 |
| CELL75.IMUX.IMUX1.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET5 |
| CELL75.IMUX.IMUX2.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET6 |
| CELL75.IMUX.IMUX3.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET7 |
| CELL75.IMUX.IMUX4.DELAY | PCIE3.PIPETX4EQDONE |
| CELL75.IMUX.IMUX5.DELAY | PCIE3.PIPETX5EQDONE |
| CELL75.IMUX.IMUX6.DELAY | PCIE3.PIPETX6EQDONE |
| CELL75.IMUX.IMUX7.DELAY | PCIE3.PIPETX7EQDONE |
| CELL75.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA161 |
| CELL75.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA162 |
| CELL75.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA163 |
| CELL75.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA164 |
| CELL75.IMUX.IMUX12.DELAY | PCIE3.CFGDSN26 |
| CELL75.IMUX.IMUX13.DELAY | PCIE3.CFGDSN27 |
| CELL75.IMUX.IMUX14.DELAY | PCIE3.CFGDSN28 |
| CELL75.IMUX.IMUX15.DELAY | PCIE3.CFGDSN29 |
| CELL75.IMUX.IMUX16.DELAY | PCIE3.CFGSUBSYSVENDID3 |
| CELL75.IMUX.IMUX17.DELAY | PCIE3.CFGSUBSYSVENDID4 |
| CELL75.IMUX.IMUX18.DELAY | PCIE3.CFGSUBSYSVENDID5 |
| CELL75.IMUX.IMUX19.DELAY | PCIE3.CFGSUBSYSVENDID6 |
| CELL75.IMUX.IMUX20.DELAY | PCIE3.CFGDSBUSNUMBER6 |
| CELL75.IMUX.IMUX21.DELAY | PCIE3.CFGDSBUSNUMBER7 |
| CELL75.IMUX.IMUX22.DELAY | PCIE3.CFGDSDEVICENUMBER0 |
| CELL75.IMUX.IMUX23.DELAY | PCIE3.CFGDSDEVICENUMBER1 |
| CELL75.IMUX.IMUX24.DELAY | PCIE3.SCANIN1 |
| CELL75.IMUX.IMUX25.DELAY | PCIE3.SCANIN2 |
| CELL75.IMUX.IMUX26.DELAY | PCIE3.SCANIN3 |
| CELL75.IMUX.IMUX27.DELAY | PCIE3.SCANIN4 |
| CELL75.OUT0.TMIN | PCIE3.PIPETX3DATA28 |
| CELL75.OUT1.TMIN | PCIE3.PIPERX7EQLPLFFS0 |
| CELL75.OUT2.TMIN | PCIE3.PIPETX3DATA30 |
| CELL75.OUT3.TMIN | PCIE3.PIPERX7EQLPLFFS1 |
| CELL75.OUT4.TMIN | PCIE3.PIPETX3DATA29 |
| CELL75.OUT5.TMIN | PCIE3.PIPERX7EQLPLFFS2 |
| CELL75.OUT6.TMIN | PCIE3.PIPETX3DATA31 |
| CELL75.OUT7.TMIN | PCIE3.PIPERX7EQLPLFFS3 |
| CELL75.OUT8.TMIN | PCIE3.MAXISCQTDATA81 |
| CELL75.OUT9.TMIN | PCIE3.MAXISCQTDATA82 |
| CELL75.OUT10.TMIN | PCIE3.MAXISCQTDATA83 |
| CELL75.OUT11.TMIN | PCIE3.MAXISCQTDATA84 |
| CELL75.OUT12.TMIN | PCIE3.MAXISCQTDATA253 |
| CELL75.OUT13.TMIN | PCIE3.MAXISCQTDATA254 |
| CELL75.OUT14.TMIN | PCIE3.MAXISCQTDATA255 |
| CELL75.OUT15.TMIN | PCIE3.MAXISCQTUSER52 |
| CELL75.OUT16.TMIN | PCIE3.CFGPERFUNCSTATUSDATA1 |
| CELL75.OUT17.TMIN | PCIE3.CFGPERFUNCSTATUSDATA2 |
| CELL75.OUT18.TMIN | PCIE3.CFGPERFUNCSTATUSDATA3 |
| CELL75.OUT19.TMIN | PCIE3.CFGPERFUNCSTATUSDATA4 |
| CELL75.OUT20.TMIN | PCIE3.CFGEXTFUNCTIONNUMBER5 |
| CELL75.OUT21.TMIN | PCIE3.CFGEXTFUNCTIONNUMBER6 |
| CELL75.OUT22.TMIN | PCIE3.CFGEXTFUNCTIONNUMBER7 |
| CELL75.OUT23.TMIN | PCIE3.CFGEXTWRITEDATA0 |
| CELL76.IMUX.IMUX0.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET8 |
| CELL76.IMUX.IMUX1.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET9 |
| CELL76.IMUX.IMUX2.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET10 |
| CELL76.IMUX.IMUX3.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET11 |
| CELL76.IMUX.IMUX4.DELAY | PCIE3.PIPETX0EQDONE |
| CELL76.IMUX.IMUX5.DELAY | PCIE3.PIPETX1EQDONE |
| CELL76.IMUX.IMUX6.DELAY | PCIE3.PIPETX2EQDONE |
| CELL76.IMUX.IMUX7.DELAY | PCIE3.PIPETX3EQDONE |
| CELL76.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA165 |
| CELL76.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA166 |
| CELL76.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA167 |
| CELL76.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA168 |
| CELL76.IMUX.IMUX12.DELAY | PCIE3.CFGDSN30 |
| CELL76.IMUX.IMUX13.DELAY | PCIE3.CFGDSN31 |
| CELL76.IMUX.IMUX14.DELAY | PCIE3.CFGDSN32 |
| CELL76.IMUX.IMUX15.DELAY | PCIE3.CFGDSN33 |
| CELL76.IMUX.IMUX16.DELAY | PCIE3.CFGSUBSYSID15 |
| CELL76.IMUX.IMUX17.DELAY | PCIE3.CFGSUBSYSVENDID0 |
| CELL76.IMUX.IMUX18.DELAY | PCIE3.CFGSUBSYSVENDID1 |
| CELL76.IMUX.IMUX19.DELAY | PCIE3.CFGSUBSYSVENDID2 |
| CELL76.IMUX.IMUX20.DELAY | PCIE3.CFGDSDEVICENUMBER2 |
| CELL76.IMUX.IMUX21.DELAY | PCIE3.CFGDSDEVICENUMBER3 |
| CELL76.IMUX.IMUX22.DELAY | PCIE3.CFGDSDEVICENUMBER4 |
| CELL76.IMUX.IMUX23.DELAY | PCIE3.CFGDSFUNCTIONNUMBER0 |
| CELL76.IMUX.IMUX24.DELAY | PCIE3.SCANIN5 |
| CELL76.IMUX.IMUX25.DELAY | PCIE3.SCANIN6 |
| CELL76.IMUX.IMUX26.DELAY | PCIE3.SCANIN7 |
| CELL76.IMUX.IMUX27.DELAY | PCIE3.SCANIN8 |
| CELL76.OUT0.TMIN | PCIE3.PIPETX2DATA28 |
| CELL76.OUT1.TMIN | PCIE3.PIPERX7EQLPLFFS4 |
| CELL76.OUT2.TMIN | PCIE3.PIPETX2DATA30 |
| CELL76.OUT3.TMIN | PCIE3.PIPERX7EQLPLFFS5 |
| CELL76.OUT4.TMIN | PCIE3.PIPETX2DATA29 |
| CELL76.OUT5.TMIN | PCIE3.PIPETX0EQCONTROL0 |
| CELL76.OUT6.TMIN | PCIE3.PIPETX2DATA31 |
| CELL76.OUT7.TMIN | PCIE3.PIPETX0EQCONTROL1 |
| CELL76.OUT8.TMIN | PCIE3.MAXISCQTDATA77 |
| CELL76.OUT9.TMIN | PCIE3.PIPETX3DATA24 |
| CELL76.OUT10.TMIN | PCIE3.MAXISCQTDATA78 |
| CELL76.OUT11.TMIN | PCIE3.PIPETX3DATA26 |
| CELL76.OUT12.TMIN | PCIE3.MAXISCQTDATA79 |
| CELL76.OUT13.TMIN | PCIE3.PIPETX3DATA25 |
| CELL76.OUT14.TMIN | PCIE3.MAXISCQTDATA80 |
| CELL76.OUT15.TMIN | PCIE3.PIPETX3DATA27 |
| CELL76.OUT16.TMIN | PCIE3.MAXISCQTUSER53 |
| CELL76.OUT17.TMIN | PCIE3.MAXISCQTUSER54 |
| CELL76.OUT18.TMIN | PCIE3.MAXISCQTUSER55 |
| CELL76.OUT19.TMIN | PCIE3.MAXISCQTUSER56 |
| CELL76.OUT20.TMIN | PCIE3.CFGPERFUNCSTATUSDATA5 |
| CELL76.OUT21.TMIN | PCIE3.CFGPERFUNCSTATUSDATA6 |
| CELL76.OUT22.TMIN | PCIE3.CFGPERFUNCSTATUSDATA7 |
| CELL76.OUT23.TMIN | PCIE3.CFGPERFUNCSTATUSDATA8 |
| CELL77.IMUX.IMUX0.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET12 |
| CELL77.IMUX.IMUX1.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET13 |
| CELL77.IMUX.IMUX2.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET14 |
| CELL77.IMUX.IMUX3.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET15 |
| CELL77.IMUX.IMUX4.DELAY | PCIE3.PIPETX7EQCOEFF14 |
| CELL77.IMUX.IMUX5.DELAY | PCIE3.PIPETX7EQCOEFF15 |
| CELL77.IMUX.IMUX6.DELAY | PCIE3.PIPETX7EQCOEFF16 |
| CELL77.IMUX.IMUX7.DELAY | PCIE3.PIPETX7EQCOEFF17 |
| CELL77.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA169 |
| CELL77.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA170 |
| CELL77.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA171 |
| CELL77.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA172 |
| CELL77.IMUX.IMUX12.DELAY | PCIE3.CFGDSN34 |
| CELL77.IMUX.IMUX13.DELAY | PCIE3.CFGDSN35 |
| CELL77.IMUX.IMUX14.DELAY | PCIE3.CFGDSN36 |
| CELL77.IMUX.IMUX15.DELAY | PCIE3.CFGDSN37 |
| CELL77.IMUX.IMUX16.DELAY | PCIE3.CFGSUBSYSID11 |
| CELL77.IMUX.IMUX17.DELAY | PCIE3.CFGSUBSYSID12 |
| CELL77.IMUX.IMUX18.DELAY | PCIE3.CFGSUBSYSID13 |
| CELL77.IMUX.IMUX19.DELAY | PCIE3.CFGSUBSYSID14 |
| CELL77.IMUX.IMUX20.DELAY | PCIE3.CFGDSFUNCTIONNUMBER1 |
| CELL77.IMUX.IMUX21.DELAY | PCIE3.CFGDSFUNCTIONNUMBER2 |
| CELL77.IMUX.IMUX22.DELAY | PCIE3.CFGPOWERSTATECHANGEACK |
| CELL77.IMUX.IMUX23.DELAY | PCIE3.CFGERRCORIN |
| CELL77.IMUX.IMUX24.DELAY | PCIE3.SCANIN9 |
| CELL77.IMUX.IMUX25.DELAY | PCIE3.SCANIN10 |
| CELL77.IMUX.IMUX26.DELAY | PCIE3.SCANIN11 |
| CELL77.IMUX.IMUX27.DELAY | PCIE3.SCANIN12 |
| CELL77.OUT0.TMIN | PCIE3.PIPETX3DATA20 |
| CELL77.OUT1.TMIN | PCIE3.PIPETX1EQCONTROL0 |
| CELL77.OUT2.TMIN | PCIE3.PIPETX3DATA22 |
| CELL77.OUT3.TMIN | PCIE3.PIPETX1EQCONTROL1 |
| CELL77.OUT4.TMIN | PCIE3.PIPETX3DATA21 |
| CELL77.OUT5.TMIN | PCIE3.PIPETX2EQCONTROL0 |
| CELL77.OUT6.TMIN | PCIE3.PIPETX3DATA23 |
| CELL77.OUT7.TMIN | PCIE3.PIPETX2EQCONTROL1 |
| CELL77.OUT8.TMIN | PCIE3.MAXISCQTDATA73 |
| CELL77.OUT9.TMIN | PCIE3.PIPETX2DATA24 |
| CELL77.OUT10.TMIN | PCIE3.MAXISCQTDATA74 |
| CELL77.OUT11.TMIN | PCIE3.PIPETX2DATA26 |
| CELL77.OUT12.TMIN | PCIE3.MAXISCQTDATA75 |
| CELL77.OUT13.TMIN | PCIE3.PIPETX2DATA25 |
| CELL77.OUT14.TMIN | PCIE3.MAXISCQTDATA76 |
| CELL77.OUT15.TMIN | PCIE3.PIPETX2DATA27 |
| CELL77.OUT16.TMIN | PCIE3.MAXISCQTUSER57 |
| CELL77.OUT17.TMIN | PCIE3.MAXISCQTUSER58 |
| CELL77.OUT18.TMIN | PCIE3.MAXISCQTUSER59 |
| CELL77.OUT19.TMIN | PCIE3.MAXISCQTUSER60 |
| CELL77.OUT20.TMIN | PCIE3.CFGPERFUNCSTATUSDATA9 |
| CELL77.OUT21.TMIN | PCIE3.CFGPERFUNCSTATUSDATA10 |
| CELL77.OUT22.TMIN | PCIE3.CFGPERFUNCSTATUSDATA11 |
| CELL77.OUT23.TMIN | PCIE3.CFGPERFUNCSTATUSDATA12 |
| CELL78.IMUX.IMUX0.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET16 |
| CELL78.IMUX.IMUX1.DELAY | PCIE3.PIPERX6EQLPNEWTXCOEFFORPRESET17 |
| CELL78.IMUX.IMUX2.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET0 |
| CELL78.IMUX.IMUX3.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET1 |
| CELL78.IMUX.IMUX4.DELAY | PCIE3.PIPETX7EQCOEFF10 |
| CELL78.IMUX.IMUX5.DELAY | PCIE3.PIPETX7EQCOEFF11 |
| CELL78.IMUX.IMUX6.DELAY | PCIE3.PIPETX7EQCOEFF12 |
| CELL78.IMUX.IMUX7.DELAY | PCIE3.PIPETX7EQCOEFF13 |
| CELL78.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA173 |
| CELL78.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA174 |
| CELL78.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA175 |
| CELL78.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA176 |
| CELL78.IMUX.IMUX12.DELAY | PCIE3.CFGDSN38 |
| CELL78.IMUX.IMUX13.DELAY | PCIE3.CFGDSN39 |
| CELL78.IMUX.IMUX14.DELAY | PCIE3.CFGDSN40 |
| CELL78.IMUX.IMUX15.DELAY | PCIE3.CFGDSN41 |
| CELL78.IMUX.IMUX16.DELAY | PCIE3.CFGSUBSYSID7 |
| CELL78.IMUX.IMUX17.DELAY | PCIE3.CFGSUBSYSID8 |
| CELL78.IMUX.IMUX18.DELAY | PCIE3.CFGSUBSYSID9 |
| CELL78.IMUX.IMUX19.DELAY | PCIE3.CFGSUBSYSID10 |
| CELL78.IMUX.IMUX20.DELAY | PCIE3.SCANIN13 |
| CELL78.IMUX.IMUX21.DELAY | PCIE3.SCANIN14 |
| CELL78.IMUX.IMUX22.DELAY | PCIE3.SCANIN15 |
| CELL78.IMUX.IMUX23.DELAY | PCIE3.SCANIN16 |
| CELL78.IMUX.IMUX34.DELAY | PCIE3.PIPERX3DATA31 |
| CELL78.IMUX.IMUX35.DELAY | PCIE3.PIPERX3DATA30 |
| CELL78.IMUX.IMUX38.DELAY | PCIE3.PIPERX3DATA29 |
| CELL78.IMUX.IMUX39.DELAY | PCIE3.PIPERX3DATA28 |
| CELL78.OUT0.TMIN | PCIE3.PIPETX2DATA20 |
| CELL78.OUT1.TMIN | PCIE3.PIPETX3EQCONTROL0 |
| CELL78.OUT2.TMIN | PCIE3.PIPETX2DATA22 |
| CELL78.OUT3.TMIN | PCIE3.PIPETX3EQCONTROL1 |
| CELL78.OUT4.TMIN | PCIE3.PIPETX2DATA21 |
| CELL78.OUT5.TMIN | PCIE3.PIPETX4EQCONTROL0 |
| CELL78.OUT6.TMIN | PCIE3.PIPETX2DATA23 |
| CELL78.OUT7.TMIN | PCIE3.PIPETX4EQCONTROL1 |
| CELL78.OUT8.TMIN | PCIE3.MAXISCQTDATA69 |
| CELL78.OUT9.TMIN | PCIE3.PIPETX3DATA16 |
| CELL78.OUT10.TMIN | PCIE3.MAXISCQTDATA70 |
| CELL78.OUT11.TMIN | PCIE3.PIPETX3DATA18 |
| CELL78.OUT12.TMIN | PCIE3.MAXISCQTDATA71 |
| CELL78.OUT13.TMIN | PCIE3.PIPETX3DATA17 |
| CELL78.OUT14.TMIN | PCIE3.MAXISCQTDATA72 |
| CELL78.OUT15.TMIN | PCIE3.PIPETX3DATA19 |
| CELL78.OUT16.TMIN | PCIE3.MAXISCQTUSER61 |
| CELL78.OUT17.TMIN | PCIE3.MAXISCQTUSER62 |
| CELL78.OUT18.TMIN | PCIE3.MAXISCQTUSER63 |
| CELL78.OUT19.TMIN | PCIE3.MAXISCQTUSER64 |
| CELL78.OUT20.TMIN | PCIE3.CFGPERFUNCSTATUSDATA13 |
| CELL78.OUT21.TMIN | PCIE3.CFGPERFUNCSTATUSDATA14 |
| CELL78.OUT22.TMIN | PCIE3.CFGPERFUNCSTATUSDATA15 |
| CELL78.OUT23.TMIN | PCIE3.CFGHOTRESETOUT |
| CELL79.IMUX.IMUX0.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET2 |
| CELL79.IMUX.IMUX1.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET3 |
| CELL79.IMUX.IMUX2.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET4 |
| CELL79.IMUX.IMUX3.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET5 |
| CELL79.IMUX.IMUX4.DELAY | PCIE3.PIPETX7EQCOEFF6 |
| CELL79.IMUX.IMUX5.DELAY | PCIE3.PIPETX7EQCOEFF7 |
| CELL79.IMUX.IMUX6.DELAY | PCIE3.PIPETX7EQCOEFF8 |
| CELL79.IMUX.IMUX7.DELAY | PCIE3.PIPETX7EQCOEFF9 |
| CELL79.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA177 |
| CELL79.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA178 |
| CELL79.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA179 |
| CELL79.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA180 |
| CELL79.IMUX.IMUX12.DELAY | PCIE3.SCANIN17 |
| CELL79.IMUX.IMUX13.DELAY | PCIE3.SCANIN18 |
| CELL79.IMUX.IMUX14.DELAY | PCIE3.SCANIN19 |
| CELL79.IMUX.IMUX15.DELAY | PCIE3.SCANIN20 |
| CELL79.IMUX.IMUX20.DELAY | PCIE3.PIPERX3SYNCHEADER1 |
| CELL79.IMUX.IMUX21.DELAY | PCIE3.PIPERX3SYNCHEADER0 |
| CELL79.IMUX.IMUX22.DELAY | PCIE3.PIPERX3STARTBLOCK |
| CELL79.IMUX.IMUX23.DELAY | PCIE3.PIPERX3DATAVALID |
| CELL79.IMUX.IMUX32.DELAY | PCIE3.PIPERX3DATA27 |
| CELL79.IMUX.IMUX33.DELAY | PCIE3.PIPERX3DATA26 |
| CELL79.IMUX.IMUX34.DELAY | PCIE3.PIPERX2DATA31 |
| CELL79.IMUX.IMUX35.DELAY | PCIE3.PIPERX2DATA30 |
| CELL79.IMUX.IMUX36.DELAY | PCIE3.PIPERX3DATA25 |
| CELL79.IMUX.IMUX37.DELAY | PCIE3.PIPERX3DATA24 |
| CELL79.IMUX.IMUX38.DELAY | PCIE3.PIPERX2DATA29 |
| CELL79.IMUX.IMUX39.DELAY | PCIE3.PIPERX2DATA28 |
| CELL79.OUT0.TMIN | PCIE3.PIPETX3DATA12 |
| CELL79.OUT1.TMIN | PCIE3.PIPETX5EQCONTROL0 |
| CELL79.OUT2.TMIN | PCIE3.PIPETX3DATA14 |
| CELL79.OUT3.TMIN | PCIE3.PIPETX5EQCONTROL1 |
| CELL79.OUT4.TMIN | PCIE3.PIPETX3DATA13 |
| CELL79.OUT5.TMIN | PCIE3.PIPETX6EQCONTROL0 |
| CELL79.OUT6.TMIN | PCIE3.PIPETX3DATA15 |
| CELL79.OUT7.TMIN | PCIE3.PIPETX6EQCONTROL1 |
| CELL79.OUT8.TMIN | PCIE3.MAXISCQTDATA65 |
| CELL79.OUT9.TMIN | PCIE3.PIPETX2DATA16 |
| CELL79.OUT10.TMIN | PCIE3.MAXISCQTDATA66 |
| CELL79.OUT11.TMIN | PCIE3.PIPETX2DATA18 |
| CELL79.OUT12.TMIN | PCIE3.MAXISCQTDATA67 |
| CELL79.OUT13.TMIN | PCIE3.PIPETX2DATA17 |
| CELL79.OUT14.TMIN | PCIE3.MAXISCQTDATA68 |
| CELL79.OUT15.TMIN | PCIE3.PIPETX2DATA19 |
| CELL79.OUT16.TMIN | PCIE3.PIPETX3CHARISK1 |
| CELL79.OUT17.TMIN | PCIE3.MAXISCQTUSER65 |
| CELL79.OUT18.TMIN | PCIE3.CFGEXTWRITEDATA1 |
| CELL79.OUT19.TMIN | PCIE3.CFGEXTWRITEDATA2 |
| CELL79.OUT20.TMIN | PCIE3.PIPETX3SYNCHEADER1 |
| CELL79.OUT21.TMIN | PCIE3.PIPETX3SYNCHEADER0 |
| CELL79.OUT22.TMIN | PCIE3.PIPETX3STARTBLOCK |
| CELL79.OUT23.TMIN | PCIE3.PIPETX3DATAVALID |
| CELL80.IMUX.IMUX0.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET6 |
| CELL80.IMUX.IMUX1.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET7 |
| CELL80.IMUX.IMUX2.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET8 |
| CELL80.IMUX.IMUX3.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET9 |
| CELL80.IMUX.IMUX4.DELAY | PCIE3.PIPETX7EQCOEFF2 |
| CELL80.IMUX.IMUX5.DELAY | PCIE3.PIPETX7EQCOEFF3 |
| CELL80.IMUX.IMUX6.DELAY | PCIE3.PIPETX7EQCOEFF4 |
| CELL80.IMUX.IMUX7.DELAY | PCIE3.PIPETX7EQCOEFF5 |
| CELL80.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA181 |
| CELL80.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA182 |
| CELL80.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA183 |
| CELL80.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA184 |
| CELL80.IMUX.IMUX12.DELAY | PCIE3.SCANIN21 |
| CELL80.IMUX.IMUX13.DELAY | PCIE3.SCANIN22 |
| CELL80.IMUX.IMUX14.DELAY | PCIE3.SCANIN23 |
| CELL80.IMUX.IMUX15.DELAY | PCIE3.SCANIN24 |
| CELL80.IMUX.IMUX20.DELAY | PCIE3.PIPERX2SYNCHEADER1 |
| CELL80.IMUX.IMUX21.DELAY | PCIE3.PIPERX2SYNCHEADER0 |
| CELL80.IMUX.IMUX22.DELAY | PCIE3.PIPERX2STARTBLOCK |
| CELL80.IMUX.IMUX23.DELAY | PCIE3.PIPERX2DATAVALID |
| CELL80.IMUX.IMUX32.DELAY | PCIE3.PIPERX2DATA27 |
| CELL80.IMUX.IMUX33.DELAY | PCIE3.PIPERX2DATA26 |
| CELL80.IMUX.IMUX34.DELAY | PCIE3.PIPERX3DATA23 |
| CELL80.IMUX.IMUX35.DELAY | PCIE3.PIPERX3DATA22 |
| CELL80.IMUX.IMUX36.DELAY | PCIE3.PIPERX2DATA25 |
| CELL80.IMUX.IMUX37.DELAY | PCIE3.PIPERX2DATA24 |
| CELL80.IMUX.IMUX38.DELAY | PCIE3.PIPERX3DATA21 |
| CELL80.IMUX.IMUX39.DELAY | PCIE3.PIPERX3DATA20 |
| CELL80.OUT0.TMIN | PCIE3.PIPETX2DATA12 |
| CELL80.OUT1.TMIN | PCIE3.PIPETX7EQCONTROL0 |
| CELL80.OUT2.TMIN | PCIE3.PIPETX2DATA14 |
| CELL80.OUT3.TMIN | PCIE3.PIPETX7EQCONTROL1 |
| CELL80.OUT4.TMIN | PCIE3.PIPETX2DATA13 |
| CELL80.OUT5.TMIN | PCIE3.PIPETX0EQPRESET0 |
| CELL80.OUT6.TMIN | PCIE3.PIPETX2DATA15 |
| CELL80.OUT7.TMIN | PCIE3.PIPETX0EQPRESET1 |
| CELL80.OUT8.TMIN | PCIE3.MAXISCQTDATA61 |
| CELL80.OUT9.TMIN | PCIE3.PIPETX3DATA8 |
| CELL80.OUT10.TMIN | PCIE3.MAXISCQTDATA62 |
| CELL80.OUT11.TMIN | PCIE3.PIPETX3DATA10 |
| CELL80.OUT12.TMIN | PCIE3.MAXISCQTDATA63 |
| CELL80.OUT13.TMIN | PCIE3.PIPETX3DATA9 |
| CELL80.OUT14.TMIN | PCIE3.MAXISCQTDATA64 |
| CELL80.OUT15.TMIN | PCIE3.PIPETX3DATA11 |
| CELL80.OUT16.TMIN | PCIE3.PIPETX2CHARISK1 |
| CELL80.OUT17.TMIN | PCIE3.MAXISCQTUSER66 |
| CELL80.OUT18.TMIN | PCIE3.CFGEXTWRITEDATA3 |
| CELL80.OUT19.TMIN | PCIE3.CFGEXTWRITEDATA4 |
| CELL80.OUT20.TMIN | PCIE3.PIPETX2SYNCHEADER1 |
| CELL80.OUT21.TMIN | PCIE3.PIPETX2SYNCHEADER0 |
| CELL80.OUT22.TMIN | PCIE3.PIPETX2STARTBLOCK |
| CELL80.OUT23.TMIN | PCIE3.PIPETX2DATAVALID |
| CELL81.IMUX.IMUX0.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET10 |
| CELL81.IMUX.IMUX1.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET11 |
| CELL81.IMUX.IMUX2.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET12 |
| CELL81.IMUX.IMUX3.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET13 |
| CELL81.IMUX.IMUX4.DELAY | PCIE3.PIPETX6EQCOEFF16 |
| CELL81.IMUX.IMUX5.DELAY | PCIE3.PIPETX6EQCOEFF17 |
| CELL81.IMUX.IMUX6.DELAY | PCIE3.PIPETX7EQCOEFF0 |
| CELL81.IMUX.IMUX7.DELAY | PCIE3.PIPETX7EQCOEFF1 |
| CELL81.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA185 |
| CELL81.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA186 |
| CELL81.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA187 |
| CELL81.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA188 |
| CELL81.IMUX.IMUX12.DELAY | PCIE3.CFGDSN42 |
| CELL81.IMUX.IMUX13.DELAY | PCIE3.CFGDSN43 |
| CELL81.IMUX.IMUX14.DELAY | PCIE3.CFGDSN44 |
| CELL81.IMUX.IMUX15.DELAY | PCIE3.CFGDSN45 |
| CELL81.IMUX.IMUX32.DELAY | PCIE3.PIPERX3DATA19 |
| CELL81.IMUX.IMUX33.DELAY | PCIE3.PIPERX3DATA18 |
| CELL81.IMUX.IMUX34.DELAY | PCIE3.PIPERX2DATA23 |
| CELL81.IMUX.IMUX35.DELAY | PCIE3.PIPERX2DATA22 |
| CELL81.IMUX.IMUX36.DELAY | PCIE3.PIPERX3DATA17 |
| CELL81.IMUX.IMUX37.DELAY | PCIE3.PIPERX3DATA16 |
| CELL81.IMUX.IMUX38.DELAY | PCIE3.PIPERX2DATA21 |
| CELL81.IMUX.IMUX39.DELAY | PCIE3.PIPERX2DATA20 |
| CELL81.OUT0.TMIN | PCIE3.PIPETX3DATA4 |
| CELL81.OUT1.TMIN | PCIE3.PIPETX0EQPRESET2 |
| CELL81.OUT2.TMIN | PCIE3.PIPETX3DATA6 |
| CELL81.OUT3.TMIN | PCIE3.PIPETX3ELECIDLE |
| CELL81.OUT4.TMIN | PCIE3.PIPETX3DATA5 |
| CELL81.OUT5.TMIN | PCIE3.PIPETX3POWERDOWN0 |
| CELL81.OUT6.TMIN | PCIE3.PIPETX3DATA7 |
| CELL81.OUT7.TMIN | PCIE3.PIPETX3POWERDOWN1 |
| CELL81.OUT8.TMIN | PCIE3.PIPETX0EQPRESET3 |
| CELL81.OUT9.TMIN | PCIE3.PIPETX2DATA8 |
| CELL81.OUT10.TMIN | PCIE3.PIPETX1EQPRESET0 |
| CELL81.OUT11.TMIN | PCIE3.PIPETX2DATA10 |
| CELL81.OUT12.TMIN | PCIE3.PIPETX1EQPRESET1 |
| CELL81.OUT13.TMIN | PCIE3.PIPETX2DATA9 |
| CELL81.OUT14.TMIN | PCIE3.MAXISCQTDATA57 |
| CELL81.OUT15.TMIN | PCIE3.PIPETX2DATA11 |
| CELL81.OUT16.TMIN | PCIE3.PIPETX3CHARISK0 |
| CELL81.OUT17.TMIN | PCIE3.MAXISCQTDATA58 |
| CELL81.OUT18.TMIN | PCIE3.MAXISCQTDATA59 |
| CELL81.OUT19.TMIN | PCIE3.MAXISCQTDATA60 |
| CELL81.OUT20.TMIN | PCIE3.MAXISCQTUSER67 |
| CELL81.OUT21.TMIN | PCIE3.MAXISCQTUSER68 |
| CELL81.OUT22.TMIN | PCIE3.CFGEXTWRITEDATA5 |
| CELL81.OUT23.TMIN | PCIE3.CFGEXTWRITEDATA6 |
| CELL82.IMUX.IMUX0.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET14 |
| CELL82.IMUX.IMUX1.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET15 |
| CELL82.IMUX.IMUX2.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET16 |
| CELL82.IMUX.IMUX3.DELAY | PCIE3.PIPERX7EQLPNEWTXCOEFFORPRESET17 |
| CELL82.IMUX.IMUX4.DELAY | PCIE3.PIPETX6EQCOEFF12 |
| CELL82.IMUX.IMUX5.DELAY | PCIE3.PIPETX6EQCOEFF13 |
| CELL82.IMUX.IMUX6.DELAY | PCIE3.PIPETX6EQCOEFF14 |
| CELL82.IMUX.IMUX7.DELAY | PCIE3.PIPETX6EQCOEFF15 |
| CELL82.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA189 |
| CELL82.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA190 |
| CELL82.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA191 |
| CELL82.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA192 |
| CELL82.IMUX.IMUX12.DELAY | PCIE3.CFGDSN46 |
| CELL82.IMUX.IMUX13.DELAY | PCIE3.CFGDSN47 |
| CELL82.IMUX.IMUX14.DELAY | PCIE3.CFGDSN48 |
| CELL82.IMUX.IMUX15.DELAY | PCIE3.CFGDSN49 |
| CELL82.IMUX.IMUX32.DELAY | PCIE3.PIPERX2DATA19 |
| CELL82.IMUX.IMUX33.DELAY | PCIE3.PIPERX2DATA18 |
| CELL82.IMUX.IMUX34.DELAY | PCIE3.PIPERX3DATA15 |
| CELL82.IMUX.IMUX35.DELAY | PCIE3.PIPERX3DATA14 |
| CELL82.IMUX.IMUX36.DELAY | PCIE3.PIPERX2DATA17 |
| CELL82.IMUX.IMUX37.DELAY | PCIE3.PIPERX2DATA16 |
| CELL82.IMUX.IMUX38.DELAY | PCIE3.PIPERX3DATA13 |
| CELL82.IMUX.IMUX39.DELAY | PCIE3.PIPERX3DATA12 |
| CELL82.OUT0.TMIN | PCIE3.PIPETX2DATA4 |
| CELL82.OUT1.TMIN | PCIE3.PIPERX3POLARITY |
| CELL82.OUT2.TMIN | PCIE3.PIPETX2DATA6 |
| CELL82.OUT3.TMIN | PCIE3.PIPETX2ELECIDLE |
| CELL82.OUT4.TMIN | PCIE3.PIPETX2DATA5 |
| CELL82.OUT5.TMIN | PCIE3.PIPETX2POWERDOWN0 |
| CELL82.OUT6.TMIN | PCIE3.PIPETX2DATA7 |
| CELL82.OUT7.TMIN | PCIE3.PIPETX2POWERDOWN1 |
| CELL82.OUT8.TMIN | PCIE3.PIPETX3COMPLIANCE |
| CELL82.OUT9.TMIN | PCIE3.PIPETX3DATA0 |
| CELL82.OUT10.TMIN | PCIE3.PIPETX1EQPRESET2 |
| CELL82.OUT11.TMIN | PCIE3.PIPETX3DATA2 |
| CELL82.OUT12.TMIN | PCIE3.PIPETX1EQPRESET3 |
| CELL82.OUT13.TMIN | PCIE3.PIPETX3DATA1 |
| CELL82.OUT14.TMIN | PCIE3.PIPETX2EQPRESET0 |
| CELL82.OUT15.TMIN | PCIE3.PIPETX3DATA3 |
| CELL82.OUT16.TMIN | PCIE3.PIPETX2CHARISK0 |
| CELL82.OUT17.TMIN | PCIE3.PIPETX2EQPRESET1 |
| CELL82.OUT18.TMIN | PCIE3.MAXISCQTDATA53 |
| CELL82.OUT19.TMIN | PCIE3.MAXISCQTDATA54 |
| CELL82.OUT20.TMIN | PCIE3.MAXISCQTDATA55 |
| CELL82.OUT21.TMIN | PCIE3.MAXISCQTDATA56 |
| CELL82.OUT22.TMIN | PCIE3.CFGEXTWRITEDATA7 |
| CELL82.OUT23.TMIN | PCIE3.CFGEXTWRITEDATA8 |
| CELL83.IMUX.IMUX0.DELAY | PCIE3.PIPERX0EQLPADAPTDONE |
| CELL83.IMUX.IMUX1.DELAY | PCIE3.PIPERX1EQLPADAPTDONE |
| CELL83.IMUX.IMUX2.DELAY | PCIE3.PIPERX2EQLPADAPTDONE |
| CELL83.IMUX.IMUX3.DELAY | PCIE3.PIPERX3EQLPADAPTDONE |
| CELL83.IMUX.IMUX4.DELAY | PCIE3.PIPETX6EQCOEFF8 |
| CELL83.IMUX.IMUX5.DELAY | PCIE3.PIPETX6EQCOEFF9 |
| CELL83.IMUX.IMUX6.DELAY | PCIE3.PIPETX6EQCOEFF10 |
| CELL83.IMUX.IMUX7.DELAY | PCIE3.PIPETX6EQCOEFF11 |
| CELL83.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA193 |
| CELL83.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA194 |
| CELL83.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA195 |
| CELL83.IMUX.IMUX16.DELAY | PCIE3.PIPERX3CHARISK1 |
| CELL83.IMUX.IMUX32.DELAY | PCIE3.PIPERX3DATA11 |
| CELL83.IMUX.IMUX33.DELAY | PCIE3.PIPERX3DATA10 |
| CELL83.IMUX.IMUX34.DELAY | PCIE3.PIPERX2DATA15 |
| CELL83.IMUX.IMUX35.DELAY | PCIE3.PIPERX2DATA14 |
| CELL83.IMUX.IMUX36.DELAY | PCIE3.PIPERX3DATA9 |
| CELL83.IMUX.IMUX37.DELAY | PCIE3.PIPERX3DATA8 |
| CELL83.IMUX.IMUX38.DELAY | PCIE3.PIPERX2DATA13 |
| CELL83.IMUX.IMUX39.DELAY | PCIE3.PIPERX2DATA12 |
| CELL83.IMUX.IMUX41.DELAY | PCIE3.PIPERX3ELECIDLE |
| CELL83.IMUX.IMUX42.DELAY | PCIE3.PIPERX3STATUS2 |
| CELL83.IMUX.IMUX43.DELAY | PCIE3.PIPERX3STATUS1 |
| CELL83.IMUX.IMUX44.DELAY | PCIE3.PIPERX3STATUS0 |
| CELL83.OUT0.TMIN | PCIE3.PIPETXDEEMPH |
| CELL83.OUT1.TMIN | PCIE3.PIPERX2POLARITY |
| CELL83.OUT2.TMIN | PCIE3.PIPETX2EQPRESET2 |
| CELL83.OUT3.TMIN | PCIE3.PIPETX2EQPRESET3 |
| CELL83.OUT4.TMIN | PCIE3.PIPETX3EQPRESET0 |
| CELL83.OUT5.TMIN | PCIE3.PIPETX3EQPRESET1 |
| CELL83.OUT6.TMIN | PCIE3.MAXISCQTDATA49 |
| CELL83.OUT7.TMIN | PCIE3.MAXISCQTDATA50 |
| CELL83.OUT8.TMIN | PCIE3.PIPETX2COMPLIANCE |
| CELL83.OUT9.TMIN | PCIE3.PIPETX2DATA0 |
| CELL83.OUT10.TMIN | PCIE3.MAXISCQTDATA51 |
| CELL83.OUT11.TMIN | PCIE3.PIPETX2DATA2 |
| CELL83.OUT12.TMIN | PCIE3.MAXISCQTDATA52 |
| CELL83.OUT13.TMIN | PCIE3.PIPETX2DATA1 |
| CELL83.OUT14.TMIN | PCIE3.MAXISCQTUSER69 |
| CELL83.OUT15.TMIN | PCIE3.PIPETX2DATA3 |
| CELL83.OUT16.TMIN | PCIE3.MAXISCQTUSER70 |
| CELL83.OUT17.TMIN | PCIE3.MAXISCQTUSER71 |
| CELL83.OUT18.TMIN | PCIE3.MAXISCQTUSER72 |
| CELL83.OUT19.TMIN | PCIE3.CFGINPUTUPDATEDONE |
| CELL83.OUT20.TMIN | PCIE3.CFGPERFUNCTIONUPDATEDONE |
| CELL83.OUT21.TMIN | PCIE3.CFGMCUPDATEDONE |
| CELL83.OUT22.TMIN | PCIE3.CFGEXTWRITEDATA9 |
| CELL83.OUT23.TMIN | PCIE3.CFGEXTWRITEDATA10 |
| CELL84.IMUX.IMUX0.DELAY | PCIE3.PIPERX4EQLPADAPTDONE |
| CELL84.IMUX.IMUX1.DELAY | PCIE3.PIPERX5EQLPADAPTDONE |
| CELL84.IMUX.IMUX2.DELAY | PCIE3.PIPERX6EQLPADAPTDONE |
| CELL84.IMUX.IMUX3.DELAY | PCIE3.PIPERX7EQLPADAPTDONE |
| CELL84.IMUX.IMUX4.DELAY | PCIE3.PIPETX6EQCOEFF4 |
| CELL84.IMUX.IMUX5.DELAY | PCIE3.PIPETX6EQCOEFF5 |
| CELL84.IMUX.IMUX6.DELAY | PCIE3.PIPETX6EQCOEFF6 |
| CELL84.IMUX.IMUX7.DELAY | PCIE3.PIPETX6EQCOEFF7 |
| CELL84.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA196 |
| CELL84.IMUX.IMUX16.DELAY | PCIE3.PIPERX2CHARISK1 |
| CELL84.IMUX.IMUX32.DELAY | PCIE3.PIPERX2DATA11 |
| CELL84.IMUX.IMUX33.DELAY | PCIE3.PIPERX2DATA10 |
| CELL84.IMUX.IMUX34.DELAY | PCIE3.PIPERX3DATA7 |
| CELL84.IMUX.IMUX35.DELAY | PCIE3.PIPERX3DATA6 |
| CELL84.IMUX.IMUX36.DELAY | PCIE3.PIPERX2DATA9 |
| CELL84.IMUX.IMUX37.DELAY | PCIE3.PIPERX2DATA8 |
| CELL84.IMUX.IMUX38.DELAY | PCIE3.PIPERX3DATA5 |
| CELL84.IMUX.IMUX39.DELAY | PCIE3.PIPERX3DATA4 |
| CELL84.IMUX.IMUX40.DELAY | PCIE3.PIPERX3VALID |
| CELL84.IMUX.IMUX41.DELAY | PCIE3.PIPERX2ELECIDLE |
| CELL84.IMUX.IMUX42.DELAY | PCIE3.PIPERX2STATUS2 |
| CELL84.IMUX.IMUX43.DELAY | PCIE3.PIPERX2STATUS1 |
| CELL84.IMUX.IMUX44.DELAY | PCIE3.PIPERX2STATUS0 |
| CELL84.IMUX.IMUX45.DELAY | PCIE3.PIPERX3PHYSTATUS |
| CELL84.OUT0.TMIN | PCIE3.PIPETX3EQPRESET2 |
| CELL84.OUT1.TMIN | PCIE3.PIPETX3EQPRESET3 |
| CELL84.OUT2.TMIN | PCIE3.PIPETX4EQPRESET0 |
| CELL84.OUT3.TMIN | PCIE3.PIPETX4EQPRESET1 |
| CELL84.OUT4.TMIN | PCIE3.MAXISCQTDATA45 |
| CELL84.OUT5.TMIN | PCIE3.MAXISCQTDATA46 |
| CELL84.OUT6.TMIN | PCIE3.MAXISCQTDATA47 |
| CELL84.OUT7.TMIN | PCIE3.MAXISCQTDATA48 |
| CELL84.OUT8.TMIN | PCIE3.MAXISCQTUSER73 |
| CELL84.OUT9.TMIN | PCIE3.MAXISCQTUSER74 |
| CELL84.OUT10.TMIN | PCIE3.MAXISCQTUSER75 |
| CELL84.OUT11.TMIN | PCIE3.MAXISCQTUSER76 |
| CELL84.OUT12.TMIN | PCIE3.CFGPOWERSTATECHANGEINTERRUPT |
| CELL84.OUT13.TMIN | PCIE3.CFGFLRINPROCESS0 |
| CELL84.OUT14.TMIN | PCIE3.CFGFLRINPROCESS1 |
| CELL84.OUT15.TMIN | PCIE3.PIPETXRCVRDET |
| CELL84.OUT16.TMIN | PCIE3.CFGVFFLRINPROCESS0 |
| CELL84.OUT17.TMIN | PCIE3.CFGEXTWRITEDATA11 |
| CELL84.OUT18.TMIN | PCIE3.CFGEXTWRITEDATA12 |
| CELL84.OUT19.TMIN | PCIE3.CFGEXTWRITEDATA13 |
| CELL84.OUT20.TMIN | PCIE3.CFGEXTWRITEDATA14 |
| CELL84.OUT21.TMIN | PCIE3.CFGTPHSTTWRITEDATA25 |
| CELL84.OUT22.TMIN | PCIE3.CFGTPHSTTWRITEDATA26 |
| CELL84.OUT23.TMIN | PCIE3.CFGTPHSTTWRITEDATA27 |
| CELL85.IMUX.IMUX0.DELAY | PCIE3.PIPERX0EQDONE |
| CELL85.IMUX.IMUX1.DELAY | PCIE3.PIPERX1EQDONE |
| CELL85.IMUX.IMUX2.DELAY | PCIE3.PIPERX2EQDONE |
| CELL85.IMUX.IMUX3.DELAY | PCIE3.PIPERX3EQDONE |
| CELL85.IMUX.IMUX4.DELAY | PCIE3.PIPETX6EQCOEFF0 |
| CELL85.IMUX.IMUX5.DELAY | PCIE3.PIPETX6EQCOEFF1 |
| CELL85.IMUX.IMUX6.DELAY | PCIE3.PIPETX6EQCOEFF2 |
| CELL85.IMUX.IMUX7.DELAY | PCIE3.PIPETX6EQCOEFF3 |
| CELL85.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA197 |
| CELL85.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA198 |
| CELL85.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA199 |
| CELL85.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA200 |
| CELL85.IMUX.IMUX12.DELAY | PCIE3.CFGDSN50 |
| CELL85.IMUX.IMUX16.DELAY | PCIE3.PIPERX3CHARISK0 |
| CELL85.IMUX.IMUX32.DELAY | PCIE3.PIPERX3DATA3 |
| CELL85.IMUX.IMUX33.DELAY | PCIE3.PIPERX3DATA2 |
| CELL85.IMUX.IMUX34.DELAY | PCIE3.PIPERX2DATA7 |
| CELL85.IMUX.IMUX35.DELAY | PCIE3.PIPERX2DATA6 |
| CELL85.IMUX.IMUX36.DELAY | PCIE3.PIPERX3DATA1 |
| CELL85.IMUX.IMUX37.DELAY | PCIE3.PIPERX3DATA0 |
| CELL85.IMUX.IMUX38.DELAY | PCIE3.PIPERX2DATA5 |
| CELL85.IMUX.IMUX39.DELAY | PCIE3.PIPERX2DATA4 |
| CELL85.IMUX.IMUX40.DELAY | PCIE3.PIPERX2VALID |
| CELL85.IMUX.IMUX45.DELAY | PCIE3.PIPERX2PHYSTATUS |
| CELL85.OUT0.TMIN | PCIE3.PIPETX4EQPRESET2 |
| CELL85.OUT1.TMIN | PCIE3.PIPETX4EQPRESET3 |
| CELL85.OUT2.TMIN | PCIE3.PIPETX5EQPRESET0 |
| CELL85.OUT3.TMIN | PCIE3.PIPETX5EQPRESET1 |
| CELL85.OUT4.TMIN | PCIE3.MAXISCQTDATA41 |
| CELL85.OUT5.TMIN | PCIE3.MAXISCQTDATA42 |
| CELL85.OUT6.TMIN | PCIE3.MAXISCQTDATA43 |
| CELL85.OUT7.TMIN | PCIE3.MAXISCQTDATA44 |
| CELL85.OUT8.TMIN | PCIE3.MAXISCQTUSER77 |
| CELL85.OUT9.TMIN | PCIE3.MAXISCQTUSER78 |
| CELL85.OUT10.TMIN | PCIE3.MAXISCQTUSER79 |
| CELL85.OUT11.TMIN | PCIE3.MAXISCQTUSER80 |
| CELL85.OUT12.TMIN | PCIE3.CFGVFFLRINPROCESS1 |
| CELL85.OUT13.TMIN | PCIE3.CFGVFFLRINPROCESS2 |
| CELL85.OUT14.TMIN | PCIE3.CFGVFFLRINPROCESS3 |
| CELL85.OUT15.TMIN | PCIE3.CFGVFFLRINPROCESS4 |
| CELL85.OUT16.TMIN | PCIE3.CFGEXTWRITEDATA15 |
| CELL85.OUT17.TMIN | PCIE3.CFGEXTWRITEDATA16 |
| CELL85.OUT18.TMIN | PCIE3.CFGEXTWRITEDATA17 |
| CELL85.OUT19.TMIN | PCIE3.CFGEXTWRITEDATA18 |
| CELL85.OUT20.TMIN | PCIE3.CFGTPHSTTWRITEDATA28 |
| CELL85.OUT21.TMIN | PCIE3.CFGTPHSTTWRITEDATA29 |
| CELL85.OUT22.TMIN | PCIE3.CFGTPHSTTWRITEDATA30 |
| CELL85.OUT23.TMIN | PCIE3.CFGTPHSTTWRITEDATA31 |
| CELL86.IMUX.IMUX0.DELAY | PCIE3.PIPERX4EQDONE |
| CELL86.IMUX.IMUX1.DELAY | PCIE3.PIPERX5EQDONE |
| CELL86.IMUX.IMUX2.DELAY | PCIE3.PIPERX6EQDONE |
| CELL86.IMUX.IMUX3.DELAY | PCIE3.PIPERX7EQDONE |
| CELL86.IMUX.IMUX4.DELAY | PCIE3.PIPETX5EQCOEFF14 |
| CELL86.IMUX.IMUX5.DELAY | PCIE3.PIPETX5EQCOEFF15 |
| CELL86.IMUX.IMUX6.DELAY | PCIE3.PIPETX5EQCOEFF16 |
| CELL86.IMUX.IMUX7.DELAY | PCIE3.PIPETX5EQCOEFF17 |
| CELL86.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA201 |
| CELL86.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA202 |
| CELL86.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA203 |
| CELL86.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA204 |
| CELL86.IMUX.IMUX12.DELAY | PCIE3.CFGDSN51 |
| CELL86.IMUX.IMUX13.DELAY | PCIE3.CFGDSN52 |
| CELL86.IMUX.IMUX14.DELAY | PCIE3.CFGDSN53 |
| CELL86.IMUX.IMUX15.DELAY | PCIE3.CFGDSN54 |
| CELL86.IMUX.IMUX16.DELAY | PCIE3.PIPERX2CHARISK0 |
| CELL86.IMUX.IMUX17.DELAY | PCIE3.CFGSUBSYSID4 |
| CELL86.IMUX.IMUX18.DELAY | PCIE3.CFGSUBSYSID5 |
| CELL86.IMUX.IMUX19.DELAY | PCIE3.CFGSUBSYSID6 |
| CELL86.IMUX.IMUX32.DELAY | PCIE3.PIPERX2DATA3 |
| CELL86.IMUX.IMUX33.DELAY | PCIE3.PIPERX2DATA2 |
| CELL86.IMUX.IMUX36.DELAY | PCIE3.PIPERX2DATA1 |
| CELL86.IMUX.IMUX37.DELAY | PCIE3.PIPERX2DATA0 |
| CELL86.OUT0.TMIN | PCIE3.PIPETX1DATA28 |
| CELL86.OUT1.TMIN | PCIE3.PIPETX5EQPRESET2 |
| CELL86.OUT2.TMIN | PCIE3.PIPETX1DATA30 |
| CELL86.OUT3.TMIN | PCIE3.PIPETX5EQPRESET3 |
| CELL86.OUT4.TMIN | PCIE3.PIPETX1DATA29 |
| CELL86.OUT5.TMIN | PCIE3.PIPETX6EQPRESET0 |
| CELL86.OUT6.TMIN | PCIE3.PIPETX1DATA31 |
| CELL86.OUT7.TMIN | PCIE3.PIPETX6EQPRESET1 |
| CELL86.OUT8.TMIN | PCIE3.MAXISCQTDATA37 |
| CELL86.OUT9.TMIN | PCIE3.PIPETXRESET |
| CELL86.OUT10.TMIN | PCIE3.MAXISCQTDATA38 |
| CELL86.OUT11.TMIN | PCIE3.MAXISCQTDATA39 |
| CELL86.OUT12.TMIN | PCIE3.MAXISCQTDATA40 |
| CELL86.OUT13.TMIN | PCIE3.MAXISCQTUSER81 |
| CELL86.OUT14.TMIN | PCIE3.MAXISCQTUSER82 |
| CELL86.OUT15.TMIN | PCIE3.MAXISCQTUSER83 |
| CELL86.OUT16.TMIN | PCIE3.MAXISCQTUSER84 |
| CELL86.OUT17.TMIN | PCIE3.CFGVFFLRINPROCESS5 |
| CELL86.OUT18.TMIN | PCIE3.CFGEXTWRITEDATA19 |
| CELL86.OUT19.TMIN | PCIE3.PIPETXRATE0 |
| CELL86.OUT20.TMIN | PCIE3.CFGEXTWRITEDATA20 |
| CELL86.OUT21.TMIN | PCIE3.CFGEXTWRITEDATA21 |
| CELL86.OUT22.TMIN | PCIE3.CFGTPHSTTWRITEENABLE |
| CELL86.OUT23.TMIN | PCIE3.CFGTPHSTTWRITEBYTEVALID0 |
| CELL87.IMUX.IMUX0.DELAY | PCIE3.PIPETX0EQCOEFF0 |
| CELL87.IMUX.IMUX1.DELAY | PCIE3.PIPETX0EQCOEFF1 |
| CELL87.IMUX.IMUX2.DELAY | PCIE3.PIPETX0EQCOEFF2 |
| CELL87.IMUX.IMUX3.DELAY | PCIE3.PIPETX0EQCOEFF3 |
| CELL87.IMUX.IMUX4.DELAY | PCIE3.PIPETX5EQCOEFF10 |
| CELL87.IMUX.IMUX5.DELAY | PCIE3.PIPETX5EQCOEFF11 |
| CELL87.IMUX.IMUX6.DELAY | PCIE3.PIPETX5EQCOEFF12 |
| CELL87.IMUX.IMUX7.DELAY | PCIE3.PIPETX5EQCOEFF13 |
| CELL87.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA205 |
| CELL87.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA206 |
| CELL87.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA207 |
| CELL87.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA208 |
| CELL87.IMUX.IMUX12.DELAY | PCIE3.CFGDSN55 |
| CELL87.IMUX.IMUX13.DELAY | PCIE3.CFGDSN56 |
| CELL87.IMUX.IMUX14.DELAY | PCIE3.CFGDSN57 |
| CELL87.IMUX.IMUX15.DELAY | PCIE3.CFGDSN58 |
| CELL87.IMUX.IMUX16.DELAY | PCIE3.CFGSUBSYSID0 |
| CELL87.IMUX.IMUX17.DELAY | PCIE3.CFGSUBSYSID1 |
| CELL87.IMUX.IMUX18.DELAY | PCIE3.CFGSUBSYSID2 |
| CELL87.IMUX.IMUX19.DELAY | PCIE3.CFGSUBSYSID3 |
| CELL87.IMUX.IMUX20.DELAY | PCIE3.CFGERRUNCORIN |
| CELL87.IMUX.IMUX21.DELAY | PCIE3.CFGFLRDONE0 |
| CELL87.IMUX.IMUX22.DELAY | PCIE3.CFGFLRDONE1 |
| CELL87.IMUX.IMUX23.DELAY | PCIE3.CFGVFFLRDONE0 |
| CELL87.OUT0.TMIN | PCIE3.PIPETX0DATA28 |
| CELL87.OUT1.TMIN | PCIE3.PIPETX6EQPRESET2 |
| CELL87.OUT2.TMIN | PCIE3.PIPETX0DATA30 |
| CELL87.OUT3.TMIN | PCIE3.PIPETX6EQPRESET3 |
| CELL87.OUT4.TMIN | PCIE3.PIPETX0DATA29 |
| CELL87.OUT5.TMIN | PCIE3.PIPETX7EQPRESET0 |
| CELL87.OUT6.TMIN | PCIE3.PIPETX0DATA31 |
| CELL87.OUT7.TMIN | PCIE3.PIPETX7EQPRESET1 |
| CELL87.OUT8.TMIN | PCIE3.MAXISCQTDATA33 |
| CELL87.OUT9.TMIN | PCIE3.PIPETX1DATA24 |
| CELL87.OUT10.TMIN | PCIE3.MAXISCQTDATA34 |
| CELL87.OUT11.TMIN | PCIE3.PIPETX1DATA26 |
| CELL87.OUT12.TMIN | PCIE3.MAXISCQTDATA35 |
| CELL87.OUT13.TMIN | PCIE3.PIPETX1DATA25 |
| CELL87.OUT14.TMIN | PCIE3.MAXISCQTDATA36 |
| CELL87.OUT15.TMIN | PCIE3.PIPETX1DATA27 |
| CELL87.OUT16.TMIN | PCIE3.MAXISCQTLAST |
| CELL87.OUT17.TMIN | PCIE3.CFGEXTWRITEDATA22 |
| CELL87.OUT18.TMIN | PCIE3.CFGEXTWRITEDATA23 |
| CELL87.OUT19.TMIN | PCIE3.CFGEXTWRITEDATA24 |
| CELL87.OUT20.TMIN | PCIE3.CFGTPHSTTWRITEBYTEVALID1 |
| CELL87.OUT21.TMIN | PCIE3.CFGTPHSTTWRITEBYTEVALID2 |
| CELL87.OUT22.TMIN | PCIE3.CFGTPHSTTWRITEBYTEVALID3 |
| CELL87.OUT23.TMIN | PCIE3.CFGTPHSTTREADENABLE |
| CELL88.IMUX.IMUX0.DELAY | PCIE3.PIPETX0EQCOEFF4 |
| CELL88.IMUX.IMUX1.DELAY | PCIE3.PIPETX0EQCOEFF5 |
| CELL88.IMUX.IMUX2.DELAY | PCIE3.PIPETX0EQCOEFF6 |
| CELL88.IMUX.IMUX3.DELAY | PCIE3.PIPETX0EQCOEFF7 |
| CELL88.IMUX.IMUX4.DELAY | PCIE3.PIPETX5EQCOEFF6 |
| CELL88.IMUX.IMUX5.DELAY | PCIE3.PIPETX5EQCOEFF7 |
| CELL88.IMUX.IMUX6.DELAY | PCIE3.PIPETX5EQCOEFF8 |
| CELL88.IMUX.IMUX7.DELAY | PCIE3.PIPETX5EQCOEFF9 |
| CELL88.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA209 |
| CELL88.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA210 |
| CELL88.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA211 |
| CELL88.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA212 |
| CELL88.IMUX.IMUX12.DELAY | PCIE3.CFGDSN59 |
| CELL88.IMUX.IMUX13.DELAY | PCIE3.CFGDSN60 |
| CELL88.IMUX.IMUX14.DELAY | PCIE3.CFGDSN61 |
| CELL88.IMUX.IMUX15.DELAY | PCIE3.CFGDSN62 |
| CELL88.IMUX.IMUX16.DELAY | PCIE3.CFGREVID4 |
| CELL88.IMUX.IMUX17.DELAY | PCIE3.CFGREVID5 |
| CELL88.IMUX.IMUX18.DELAY | PCIE3.CFGREVID6 |
| CELL88.IMUX.IMUX19.DELAY | PCIE3.CFGREVID7 |
| CELL88.IMUX.IMUX20.DELAY | PCIE3.CFGVFFLRDONE1 |
| CELL88.IMUX.IMUX21.DELAY | PCIE3.CFGVFFLRDONE2 |
| CELL88.IMUX.IMUX22.DELAY | PCIE3.CFGVFFLRDONE3 |
| CELL88.IMUX.IMUX23.DELAY | PCIE3.CFGVFFLRDONE4 |
| CELL88.OUT0.TMIN | PCIE3.PIPETX1DATA20 |
| CELL88.OUT1.TMIN | PCIE3.PIPETX7EQPRESET2 |
| CELL88.OUT2.TMIN | PCIE3.PIPETX1DATA22 |
| CELL88.OUT3.TMIN | PCIE3.PIPETX7EQPRESET3 |
| CELL88.OUT4.TMIN | PCIE3.PIPETX1DATA21 |
| CELL88.OUT5.TMIN | PCIE3.PIPETX0EQDEEMPH0 |
| CELL88.OUT6.TMIN | PCIE3.PIPETX1DATA23 |
| CELL88.OUT7.TMIN | PCIE3.PIPETX0EQDEEMPH1 |
| CELL88.OUT8.TMIN | PCIE3.MAXISCQTDATA29 |
| CELL88.OUT9.TMIN | PCIE3.PIPETX0DATA24 |
| CELL88.OUT10.TMIN | PCIE3.MAXISCQTDATA30 |
| CELL88.OUT11.TMIN | PCIE3.PIPETX0DATA26 |
| CELL88.OUT12.TMIN | PCIE3.MAXISCQTDATA31 |
| CELL88.OUT13.TMIN | PCIE3.PIPETX0DATA25 |
| CELL88.OUT14.TMIN | PCIE3.MAXISCQTDATA32 |
| CELL88.OUT15.TMIN | PCIE3.PIPETX0DATA27 |
| CELL88.OUT16.TMIN | PCIE3.CFGEXTWRITEDATA25 |
| CELL88.OUT17.TMIN | PCIE3.CFGEXTWRITEDATA26 |
| CELL88.OUT18.TMIN | PCIE3.CFGEXTWRITEDATA27 |
| CELL88.OUT19.TMIN | PCIE3.CFGEXTWRITEDATA28 |
| CELL88.OUT20.TMIN | PCIE3.DBGDATAOUT0 |
| CELL88.OUT21.TMIN | PCIE3.DBGDATAOUT1 |
| CELL88.OUT22.TMIN | PCIE3.DBGDATAOUT2 |
| CELL88.OUT23.TMIN | PCIE3.DBGDATAOUT3 |
| CELL89.IMUX.IMUX0.DELAY | PCIE3.PIPETX0EQCOEFF8 |
| CELL89.IMUX.IMUX1.DELAY | PCIE3.PIPETX0EQCOEFF9 |
| CELL89.IMUX.IMUX2.DELAY | PCIE3.PIPETX0EQCOEFF10 |
| CELL89.IMUX.IMUX3.DELAY | PCIE3.PIPETX0EQCOEFF11 |
| CELL89.IMUX.IMUX4.DELAY | PCIE3.PIPETX5EQCOEFF2 |
| CELL89.IMUX.IMUX5.DELAY | PCIE3.PIPETX5EQCOEFF3 |
| CELL89.IMUX.IMUX6.DELAY | PCIE3.PIPETX5EQCOEFF4 |
| CELL89.IMUX.IMUX7.DELAY | PCIE3.PIPETX5EQCOEFF5 |
| CELL89.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA213 |
| CELL89.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA214 |
| CELL89.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA215 |
| CELL89.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA216 |
| CELL89.IMUX.IMUX12.DELAY | PCIE3.CFGDSN63 |
| CELL89.IMUX.IMUX13.DELAY | PCIE3.CFGDEVID0 |
| CELL89.IMUX.IMUX14.DELAY | PCIE3.CFGDEVID1 |
| CELL89.IMUX.IMUX15.DELAY | PCIE3.CFGDEVID2 |
| CELL89.IMUX.IMUX16.DELAY | PCIE3.CFGREVID0 |
| CELL89.IMUX.IMUX17.DELAY | PCIE3.CFGREVID1 |
| CELL89.IMUX.IMUX18.DELAY | PCIE3.CFGREVID2 |
| CELL89.IMUX.IMUX19.DELAY | PCIE3.CFGREVID3 |
| CELL89.IMUX.IMUX34.DELAY | PCIE3.PIPERX1DATA31 |
| CELL89.IMUX.IMUX35.DELAY | PCIE3.PIPERX1DATA30 |
| CELL89.IMUX.IMUX38.DELAY | PCIE3.PIPERX1DATA29 |
| CELL89.IMUX.IMUX39.DELAY | PCIE3.PIPERX1DATA28 |
| CELL89.OUT0.TMIN | PCIE3.PIPETX0DATA20 |
| CELL89.OUT1.TMIN | PCIE3.PIPETX0EQDEEMPH2 |
| CELL89.OUT2.TMIN | PCIE3.PIPETX0DATA22 |
| CELL89.OUT3.TMIN | PCIE3.PIPETX0EQDEEMPH3 |
| CELL89.OUT4.TMIN | PCIE3.PIPETX0DATA21 |
| CELL89.OUT5.TMIN | PCIE3.PIPETX0EQDEEMPH4 |
| CELL89.OUT6.TMIN | PCIE3.PIPETX0DATA23 |
| CELL89.OUT7.TMIN | PCIE3.PIPETX0EQDEEMPH5 |
| CELL89.OUT8.TMIN | PCIE3.MAXISCQTDATA25 |
| CELL89.OUT9.TMIN | PCIE3.PIPETX1DATA16 |
| CELL89.OUT10.TMIN | PCIE3.MAXISCQTDATA26 |
| CELL89.OUT11.TMIN | PCIE3.PIPETX1DATA18 |
| CELL89.OUT12.TMIN | PCIE3.MAXISCQTDATA27 |
| CELL89.OUT13.TMIN | PCIE3.PIPETX1DATA17 |
| CELL89.OUT14.TMIN | PCIE3.MAXISCQTDATA28 |
| CELL89.OUT15.TMIN | PCIE3.PIPETX1DATA19 |
| CELL89.OUT16.TMIN | PCIE3.CFGEXTWRITEDATA29 |
| CELL89.OUT17.TMIN | PCIE3.CFGEXTWRITEDATA30 |
| CELL89.OUT18.TMIN | PCIE3.CFGEXTWRITEDATA31 |
| CELL89.OUT19.TMIN | PCIE3.CFGEXTWRITEBYTEENABLE0 |
| CELL89.OUT20.TMIN | PCIE3.DBGDATAOUT4 |
| CELL89.OUT21.TMIN | PCIE3.DBGDATAOUT5 |
| CELL89.OUT22.TMIN | PCIE3.DBGDATAOUT6 |
| CELL89.OUT23.TMIN | PCIE3.DBGDATAOUT7 |
| CELL90.IMUX.IMUX0.DELAY | PCIE3.PIPETX0EQCOEFF12 |
| CELL90.IMUX.IMUX1.DELAY | PCIE3.PIPETX0EQCOEFF13 |
| CELL90.IMUX.IMUX2.DELAY | PCIE3.PIPETX0EQCOEFF14 |
| CELL90.IMUX.IMUX3.DELAY | PCIE3.PIPETX0EQCOEFF15 |
| CELL90.IMUX.IMUX4.DELAY | PCIE3.PIPETX4EQCOEFF16 |
| CELL90.IMUX.IMUX5.DELAY | PCIE3.PIPETX4EQCOEFF17 |
| CELL90.IMUX.IMUX6.DELAY | PCIE3.PIPETX5EQCOEFF0 |
| CELL90.IMUX.IMUX7.DELAY | PCIE3.PIPETX5EQCOEFF1 |
| CELL90.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA217 |
| CELL90.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA218 |
| CELL90.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA219 |
| CELL90.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA220 |
| CELL90.IMUX.IMUX20.DELAY | PCIE3.PIPERX1SYNCHEADER1 |
| CELL90.IMUX.IMUX21.DELAY | PCIE3.PIPERX1SYNCHEADER0 |
| CELL90.IMUX.IMUX22.DELAY | PCIE3.PIPERX1STARTBLOCK |
| CELL90.IMUX.IMUX23.DELAY | PCIE3.PIPERX1DATAVALID |
| CELL90.IMUX.IMUX32.DELAY | PCIE3.PIPERX1DATA27 |
| CELL90.IMUX.IMUX33.DELAY | PCIE3.PIPERX1DATA26 |
| CELL90.IMUX.IMUX34.DELAY | PCIE3.PIPERX0DATA31 |
| CELL90.IMUX.IMUX35.DELAY | PCIE3.PIPERX0DATA30 |
| CELL90.IMUX.IMUX36.DELAY | PCIE3.PIPERX1DATA25 |
| CELL90.IMUX.IMUX37.DELAY | PCIE3.PIPERX1DATA24 |
| CELL90.IMUX.IMUX38.DELAY | PCIE3.PIPERX0DATA29 |
| CELL90.IMUX.IMUX39.DELAY | PCIE3.PIPERX0DATA28 |
| CELL90.OUT0.TMIN | PCIE3.PIPETX1DATA12 |
| CELL90.OUT1.TMIN | PCIE3.PIPETX1EQDEEMPH0 |
| CELL90.OUT2.TMIN | PCIE3.PIPETX1DATA14 |
| CELL90.OUT3.TMIN | PCIE3.PIPETX1EQDEEMPH1 |
| CELL90.OUT4.TMIN | PCIE3.PIPETX1DATA13 |
| CELL90.OUT5.TMIN | PCIE3.PIPETX1EQDEEMPH2 |
| CELL90.OUT6.TMIN | PCIE3.PIPETX1DATA15 |
| CELL90.OUT7.TMIN | PCIE3.PIPETX1EQDEEMPH3 |
| CELL90.OUT8.TMIN | PCIE3.MAXISCQTDATA21 |
| CELL90.OUT9.TMIN | PCIE3.PIPETX0DATA16 |
| CELL90.OUT10.TMIN | PCIE3.MAXISCQTDATA22 |
| CELL90.OUT11.TMIN | PCIE3.PIPETX0DATA18 |
| CELL90.OUT12.TMIN | PCIE3.MAXISCQTDATA23 |
| CELL90.OUT13.TMIN | PCIE3.PIPETX0DATA17 |
| CELL90.OUT14.TMIN | PCIE3.MAXISCQTDATA24 |
| CELL90.OUT15.TMIN | PCIE3.PIPETX0DATA19 |
| CELL90.OUT16.TMIN | PCIE3.PIPETX1CHARISK1 |
| CELL90.OUT17.TMIN | PCIE3.CFGEXTWRITEBYTEENABLE1 |
| CELL90.OUT18.TMIN | PCIE3.CFGEXTWRITEBYTEENABLE2 |
| CELL90.OUT19.TMIN | PCIE3.CFGEXTWRITEBYTEENABLE3 |
| CELL90.OUT20.TMIN | PCIE3.PIPETX1SYNCHEADER1 |
| CELL90.OUT21.TMIN | PCIE3.PIPETX1SYNCHEADER0 |
| CELL90.OUT22.TMIN | PCIE3.PIPETX1STARTBLOCK |
| CELL90.OUT23.TMIN | PCIE3.PIPETX1DATAVALID |
| CELL91.IMUX.IMUX0.DELAY | PCIE3.PIPETX0EQCOEFF16 |
| CELL91.IMUX.IMUX1.DELAY | PCIE3.PIPETX0EQCOEFF17 |
| CELL91.IMUX.IMUX2.DELAY | PCIE3.PIPETX1EQCOEFF0 |
| CELL91.IMUX.IMUX3.DELAY | PCIE3.PIPETX1EQCOEFF1 |
| CELL91.IMUX.IMUX4.DELAY | PCIE3.PIPETX4EQCOEFF12 |
| CELL91.IMUX.IMUX5.DELAY | PCIE3.PIPETX4EQCOEFF13 |
| CELL91.IMUX.IMUX6.DELAY | PCIE3.PIPETX4EQCOEFF14 |
| CELL91.IMUX.IMUX7.DELAY | PCIE3.PIPETX4EQCOEFF15 |
| CELL91.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA221 |
| CELL91.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA222 |
| CELL91.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA223 |
| CELL91.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA224 |
| CELL91.IMUX.IMUX20.DELAY | PCIE3.PIPERX0SYNCHEADER1 |
| CELL91.IMUX.IMUX21.DELAY | PCIE3.PIPERX0SYNCHEADER0 |
| CELL91.IMUX.IMUX22.DELAY | PCIE3.PIPERX0STARTBLOCK |
| CELL91.IMUX.IMUX23.DELAY | PCIE3.PIPERX0DATAVALID |
| CELL91.IMUX.IMUX32.DELAY | PCIE3.PIPERX0DATA27 |
| CELL91.IMUX.IMUX33.DELAY | PCIE3.PIPERX0DATA26 |
| CELL91.IMUX.IMUX34.DELAY | PCIE3.PIPERX1DATA23 |
| CELL91.IMUX.IMUX35.DELAY | PCIE3.PIPERX1DATA22 |
| CELL91.IMUX.IMUX36.DELAY | PCIE3.PIPERX0DATA25 |
| CELL91.IMUX.IMUX37.DELAY | PCIE3.PIPERX0DATA24 |
| CELL91.IMUX.IMUX38.DELAY | PCIE3.PIPERX1DATA21 |
| CELL91.IMUX.IMUX39.DELAY | PCIE3.PIPERX1DATA20 |
| CELL91.OUT0.TMIN | PCIE3.PIPETX0DATA12 |
| CELL91.OUT1.TMIN | PCIE3.PIPETX1EQDEEMPH4 |
| CELL91.OUT2.TMIN | PCIE3.PIPETX0DATA14 |
| CELL91.OUT3.TMIN | PCIE3.PIPETX1EQDEEMPH5 |
| CELL91.OUT4.TMIN | PCIE3.PIPETX0DATA13 |
| CELL91.OUT5.TMIN | PCIE3.PIPETX2EQDEEMPH0 |
| CELL91.OUT6.TMIN | PCIE3.PIPETX0DATA15 |
| CELL91.OUT7.TMIN | PCIE3.PIPETX2EQDEEMPH1 |
| CELL91.OUT8.TMIN | PCIE3.MAXISCQTDATA17 |
| CELL91.OUT9.TMIN | PCIE3.PIPETX1DATA8 |
| CELL91.OUT10.TMIN | PCIE3.MAXISCQTDATA18 |
| CELL91.OUT11.TMIN | PCIE3.PIPETX1DATA10 |
| CELL91.OUT12.TMIN | PCIE3.MAXISCQTDATA19 |
| CELL91.OUT13.TMIN | PCIE3.PIPETX1DATA9 |
| CELL91.OUT14.TMIN | PCIE3.MAXISCQTDATA20 |
| CELL91.OUT15.TMIN | PCIE3.PIPETX1DATA11 |
| CELL91.OUT16.TMIN | PCIE3.PIPETX0CHARISK1 |
| CELL91.OUT17.TMIN | PCIE3.CFGTPHSTTADDRESS0 |
| CELL91.OUT18.TMIN | PCIE3.CFGTPHSTTADDRESS1 |
| CELL91.OUT19.TMIN | PCIE3.CFGTPHSTTADDRESS2 |
| CELL91.OUT20.TMIN | PCIE3.PIPETX0SYNCHEADER1 |
| CELL91.OUT21.TMIN | PCIE3.PIPETX0SYNCHEADER0 |
| CELL91.OUT22.TMIN | PCIE3.PIPETX0STARTBLOCK |
| CELL91.OUT23.TMIN | PCIE3.PIPETX0DATAVALID |
| CELL92.IMUX.IMUX0.DELAY | PCIE3.PIPETX1EQCOEFF2 |
| CELL92.IMUX.IMUX1.DELAY | PCIE3.PIPETX1EQCOEFF3 |
| CELL92.IMUX.IMUX2.DELAY | PCIE3.PIPETX1EQCOEFF4 |
| CELL92.IMUX.IMUX3.DELAY | PCIE3.PIPETX1EQCOEFF5 |
| CELL92.IMUX.IMUX4.DELAY | PCIE3.PIPETX4EQCOEFF8 |
| CELL92.IMUX.IMUX5.DELAY | PCIE3.PIPETX4EQCOEFF9 |
| CELL92.IMUX.IMUX6.DELAY | PCIE3.PIPETX4EQCOEFF10 |
| CELL92.IMUX.IMUX7.DELAY | PCIE3.PIPETX4EQCOEFF11 |
| CELL92.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA225 |
| CELL92.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA226 |
| CELL92.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA227 |
| CELL92.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA228 |
| CELL92.IMUX.IMUX12.DELAY | PCIE3.CFGDEVID3 |
| CELL92.IMUX.IMUX13.DELAY | PCIE3.CFGDEVID4 |
| CELL92.IMUX.IMUX14.DELAY | PCIE3.CFGDEVID5 |
| CELL92.IMUX.IMUX15.DELAY | PCIE3.CFGDEVID6 |
| CELL92.IMUX.IMUX32.DELAY | PCIE3.PIPERX1DATA19 |
| CELL92.IMUX.IMUX33.DELAY | PCIE3.PIPERX1DATA18 |
| CELL92.IMUX.IMUX34.DELAY | PCIE3.PIPERX0DATA23 |
| CELL92.IMUX.IMUX35.DELAY | PCIE3.PIPERX0DATA22 |
| CELL92.IMUX.IMUX36.DELAY | PCIE3.PIPERX1DATA17 |
| CELL92.IMUX.IMUX37.DELAY | PCIE3.PIPERX1DATA16 |
| CELL92.IMUX.IMUX38.DELAY | PCIE3.PIPERX0DATA21 |
| CELL92.IMUX.IMUX39.DELAY | PCIE3.PIPERX0DATA20 |
| CELL92.OUT0.TMIN | PCIE3.PIPETX1DATA4 |
| CELL92.OUT1.TMIN | PCIE3.PIPETX2EQDEEMPH2 |
| CELL92.OUT2.TMIN | PCIE3.PIPETX1DATA6 |
| CELL92.OUT3.TMIN | PCIE3.PIPETX1ELECIDLE |
| CELL92.OUT4.TMIN | PCIE3.PIPETX1DATA5 |
| CELL92.OUT5.TMIN | PCIE3.PIPETX1POWERDOWN0 |
| CELL92.OUT6.TMIN | PCIE3.PIPETX1DATA7 |
| CELL92.OUT7.TMIN | PCIE3.PIPETX1POWERDOWN1 |
| CELL92.OUT8.TMIN | PCIE3.PIPETX2EQDEEMPH3 |
| CELL92.OUT9.TMIN | PCIE3.PIPETX0DATA8 |
| CELL92.OUT10.TMIN | PCIE3.PIPETX2EQDEEMPH4 |
| CELL92.OUT11.TMIN | PCIE3.PIPETX0DATA10 |
| CELL92.OUT12.TMIN | PCIE3.PIPETX2EQDEEMPH5 |
| CELL92.OUT13.TMIN | PCIE3.PIPETX0DATA9 |
| CELL92.OUT14.TMIN | PCIE3.MAXISCQTDATA13 |
| CELL92.OUT15.TMIN | PCIE3.PIPETX0DATA11 |
| CELL92.OUT16.TMIN | PCIE3.PIPETX1CHARISK0 |
| CELL92.OUT17.TMIN | PCIE3.MAXISCQTDATA14 |
| CELL92.OUT18.TMIN | PCIE3.MAXISCQTDATA15 |
| CELL92.OUT19.TMIN | PCIE3.MAXISCQTDATA16 |
| CELL92.OUT20.TMIN | PCIE3.CFGTPHSTTADDRESS3 |
| CELL92.OUT21.TMIN | PCIE3.CFGTPHSTTADDRESS4 |
| CELL92.OUT22.TMIN | PCIE3.CFGTPHFUNCTIONNUM0 |
| CELL92.OUT23.TMIN | PCIE3.CFGTPHFUNCTIONNUM1 |
| CELL93.IMUX.IMUX0.DELAY | PCIE3.PIPETX1EQCOEFF6 |
| CELL93.IMUX.IMUX1.DELAY | PCIE3.PIPETX1EQCOEFF7 |
| CELL93.IMUX.IMUX2.DELAY | PCIE3.PIPETX1EQCOEFF8 |
| CELL93.IMUX.IMUX3.DELAY | PCIE3.PIPETX1EQCOEFF9 |
| CELL93.IMUX.IMUX4.DELAY | PCIE3.PIPETX4EQCOEFF4 |
| CELL93.IMUX.IMUX5.DELAY | PCIE3.PIPETX4EQCOEFF5 |
| CELL93.IMUX.IMUX6.DELAY | PCIE3.PIPETX4EQCOEFF6 |
| CELL93.IMUX.IMUX7.DELAY | PCIE3.PIPETX4EQCOEFF7 |
| CELL93.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA229 |
| CELL93.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA230 |
| CELL93.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA231 |
| CELL93.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA232 |
| CELL93.IMUX.IMUX12.DELAY | PCIE3.CFGDEVID7 |
| CELL93.IMUX.IMUX13.DELAY | PCIE3.CFGDEVID8 |
| CELL93.IMUX.IMUX14.DELAY | PCIE3.CFGDEVID9 |
| CELL93.IMUX.IMUX15.DELAY | PCIE3.CFGDEVID10 |
| CELL93.IMUX.IMUX32.DELAY | PCIE3.PIPERX0DATA19 |
| CELL93.IMUX.IMUX33.DELAY | PCIE3.PIPERX0DATA18 |
| CELL93.IMUX.IMUX34.DELAY | PCIE3.PIPERX1DATA15 |
| CELL93.IMUX.IMUX35.DELAY | PCIE3.PIPERX1DATA14 |
| CELL93.IMUX.IMUX36.DELAY | PCIE3.PIPERX0DATA17 |
| CELL93.IMUX.IMUX37.DELAY | PCIE3.PIPERX0DATA16 |
| CELL93.IMUX.IMUX38.DELAY | PCIE3.PIPERX1DATA13 |
| CELL93.IMUX.IMUX39.DELAY | PCIE3.PIPERX1DATA12 |
| CELL93.OUT0.TMIN | PCIE3.PIPETX0DATA4 |
| CELL93.OUT1.TMIN | PCIE3.PIPERX1POLARITY |
| CELL93.OUT2.TMIN | PCIE3.PIPETX0DATA6 |
| CELL93.OUT3.TMIN | PCIE3.PIPETX0ELECIDLE |
| CELL93.OUT4.TMIN | PCIE3.PIPETX0DATA5 |
| CELL93.OUT5.TMIN | PCIE3.PIPETX0POWERDOWN0 |
| CELL93.OUT6.TMIN | PCIE3.PIPETX0DATA7 |
| CELL93.OUT7.TMIN | PCIE3.PIPETX0POWERDOWN1 |
| CELL93.OUT8.TMIN | PCIE3.PIPETX1COMPLIANCE |
| CELL93.OUT9.TMIN | PCIE3.PIPETX1DATA0 |
| CELL93.OUT10.TMIN | PCIE3.PIPETX3EQDEEMPH0 |
| CELL93.OUT11.TMIN | PCIE3.PIPETX1DATA2 |
| CELL93.OUT12.TMIN | PCIE3.PIPETX3EQDEEMPH1 |
| CELL93.OUT13.TMIN | PCIE3.PIPETX1DATA1 |
| CELL93.OUT14.TMIN | PCIE3.PIPETX3EQDEEMPH2 |
| CELL93.OUT15.TMIN | PCIE3.PIPETX1DATA3 |
| CELL93.OUT16.TMIN | PCIE3.PIPETX0CHARISK0 |
| CELL93.OUT17.TMIN | PCIE3.PIPETX3EQDEEMPH3 |
| CELL93.OUT18.TMIN | PCIE3.MAXISCQTDATA9 |
| CELL93.OUT19.TMIN | PCIE3.MAXISCQTDATA10 |
| CELL93.OUT20.TMIN | PCIE3.MAXISCQTDATA11 |
| CELL93.OUT21.TMIN | PCIE3.MAXISCQTDATA12 |
| CELL93.OUT22.TMIN | PCIE3.CFGTPHFUNCTIONNUM2 |
| CELL93.OUT23.TMIN | PCIE3.CFGTPHSTTWRITEDATA0 |
| CELL94.IMUX.IMUX0.DELAY | PCIE3.PIPETX1EQCOEFF10 |
| CELL94.IMUX.IMUX1.DELAY | PCIE3.PIPETX1EQCOEFF11 |
| CELL94.IMUX.IMUX2.DELAY | PCIE3.PIPETX1EQCOEFF12 |
| CELL94.IMUX.IMUX3.DELAY | PCIE3.PIPETX1EQCOEFF13 |
| CELL94.IMUX.IMUX4.DELAY | PCIE3.PIPETX4EQCOEFF0 |
| CELL94.IMUX.IMUX5.DELAY | PCIE3.PIPETX4EQCOEFF1 |
| CELL94.IMUX.IMUX6.DELAY | PCIE3.PIPETX4EQCOEFF2 |
| CELL94.IMUX.IMUX7.DELAY | PCIE3.PIPETX4EQCOEFF3 |
| CELL94.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA233 |
| CELL94.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA234 |
| CELL94.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA235 |
| CELL94.IMUX.IMUX16.DELAY | PCIE3.PIPERX1CHARISK1 |
| CELL94.IMUX.IMUX32.DELAY | PCIE3.PIPERX1DATA11 |
| CELL94.IMUX.IMUX33.DELAY | PCIE3.PIPERX1DATA10 |
| CELL94.IMUX.IMUX34.DELAY | PCIE3.PIPERX0DATA15 |
| CELL94.IMUX.IMUX35.DELAY | PCIE3.PIPERX0DATA14 |
| CELL94.IMUX.IMUX36.DELAY | PCIE3.PIPERX1DATA9 |
| CELL94.IMUX.IMUX37.DELAY | PCIE3.PIPERX1DATA8 |
| CELL94.IMUX.IMUX38.DELAY | PCIE3.PIPERX0DATA13 |
| CELL94.IMUX.IMUX39.DELAY | PCIE3.PIPERX0DATA12 |
| CELL94.IMUX.IMUX41.DELAY | PCIE3.PIPERX1ELECIDLE |
| CELL94.IMUX.IMUX42.DELAY | PCIE3.PIPERX1STATUS2 |
| CELL94.IMUX.IMUX43.DELAY | PCIE3.PIPERX1STATUS1 |
| CELL94.IMUX.IMUX44.DELAY | PCIE3.PIPERX1STATUS0 |
| CELL94.OUT0.TMIN | PCIE3.PIPETX3EQDEEMPH4 |
| CELL94.OUT1.TMIN | PCIE3.PIPERX0POLARITY |
| CELL94.OUT2.TMIN | PCIE3.PIPETX3EQDEEMPH5 |
| CELL94.OUT3.TMIN | PCIE3.PIPETX4EQDEEMPH0 |
| CELL94.OUT4.TMIN | PCIE3.PIPETX4EQDEEMPH1 |
| CELL94.OUT5.TMIN | PCIE3.MAXISCQTDATA5 |
| CELL94.OUT6.TMIN | PCIE3.MAXISCQTDATA6 |
| CELL94.OUT7.TMIN | PCIE3.MAXISCQTDATA7 |
| CELL94.OUT8.TMIN | PCIE3.PIPETX0COMPLIANCE |
| CELL94.OUT9.TMIN | PCIE3.PIPETX0DATA0 |
| CELL94.OUT10.TMIN | PCIE3.MAXISCQTDATA8 |
| CELL94.OUT11.TMIN | PCIE3.PIPETX0DATA2 |
| CELL94.OUT12.TMIN | PCIE3.CFGTPHSTTWRITEDATA1 |
| CELL94.OUT13.TMIN | PCIE3.PIPETX0DATA1 |
| CELL94.OUT14.TMIN | PCIE3.CFGTPHSTTWRITEDATA2 |
| CELL94.OUT15.TMIN | PCIE3.PIPETX0DATA3 |
| CELL94.OUT16.TMIN | PCIE3.CFGTPHSTTWRITEDATA3 |
| CELL94.OUT17.TMIN | PCIE3.CFGTPHSTTWRITEDATA4 |
| CELL94.OUT18.TMIN | PCIE3.DBGDATAOUT8 |
| CELL94.OUT19.TMIN | PCIE3.DBGDATAOUT9 |
| CELL94.OUT20.TMIN | PCIE3.DBGDATAOUT10 |
| CELL94.OUT21.TMIN | PCIE3.DBGDATAOUT11 |
| CELL94.OUT22.TMIN | PCIE3.DRPDO15 |
| CELL94.OUT23.TMIN | PCIE3.SCANOUT0 |
| CELL95.IMUX.IMUX0.DELAY | PCIE3.PIPETX1EQCOEFF14 |
| CELL95.IMUX.IMUX1.DELAY | PCIE3.PIPETX1EQCOEFF15 |
| CELL95.IMUX.IMUX2.DELAY | PCIE3.PIPETX1EQCOEFF16 |
| CELL95.IMUX.IMUX3.DELAY | PCIE3.PIPETX1EQCOEFF17 |
| CELL95.IMUX.IMUX4.DELAY | PCIE3.PIPETX3EQCOEFF14 |
| CELL95.IMUX.IMUX5.DELAY | PCIE3.PIPETX3EQCOEFF15 |
| CELL95.IMUX.IMUX6.DELAY | PCIE3.PIPETX3EQCOEFF16 |
| CELL95.IMUX.IMUX7.DELAY | PCIE3.PIPETX3EQCOEFF17 |
| CELL95.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA236 |
| CELL95.IMUX.IMUX16.DELAY | PCIE3.PIPERX0CHARISK1 |
| CELL95.IMUX.IMUX32.DELAY | PCIE3.PIPERX0DATA11 |
| CELL95.IMUX.IMUX33.DELAY | PCIE3.PIPERX0DATA10 |
| CELL95.IMUX.IMUX34.DELAY | PCIE3.PIPERX1DATA7 |
| CELL95.IMUX.IMUX35.DELAY | PCIE3.PIPERX1DATA6 |
| CELL95.IMUX.IMUX36.DELAY | PCIE3.PIPERX0DATA9 |
| CELL95.IMUX.IMUX37.DELAY | PCIE3.PIPERX0DATA8 |
| CELL95.IMUX.IMUX38.DELAY | PCIE3.PIPERX1DATA5 |
| CELL95.IMUX.IMUX39.DELAY | PCIE3.PIPERX1DATA4 |
| CELL95.IMUX.IMUX40.DELAY | PCIE3.PIPERX1VALID |
| CELL95.IMUX.IMUX41.DELAY | PCIE3.PIPERX0ELECIDLE |
| CELL95.IMUX.IMUX42.DELAY | PCIE3.PIPERX0STATUS2 |
| CELL95.IMUX.IMUX43.DELAY | PCIE3.PIPERX0STATUS1 |
| CELL95.IMUX.IMUX44.DELAY | PCIE3.PIPERX0STATUS0 |
| CELL95.IMUX.IMUX45.DELAY | PCIE3.PIPERX1PHYSTATUS |
| CELL95.OUT0.TMIN | PCIE3.PIPETX4EQDEEMPH2 |
| CELL95.OUT1.TMIN | PCIE3.PIPETX4EQDEEMPH3 |
| CELL95.OUT2.TMIN | PCIE3.PIPETX4EQDEEMPH4 |
| CELL95.OUT3.TMIN | PCIE3.PIPETX4EQDEEMPH5 |
| CELL95.OUT4.TMIN | PCIE3.MAXISCQTDATA1 |
| CELL95.OUT5.TMIN | PCIE3.MAXISCQTDATA2 |
| CELL95.OUT6.TMIN | PCIE3.MAXISCQTDATA3 |
| CELL95.OUT7.TMIN | PCIE3.MAXISCQTDATA4 |
| CELL95.OUT8.TMIN | PCIE3.CFGTPHSTTWRITEDATA5 |
| CELL95.OUT9.TMIN | PCIE3.CFGTPHSTTWRITEDATA6 |
| CELL95.OUT10.TMIN | PCIE3.CFGTPHSTTWRITEDATA7 |
| CELL95.OUT11.TMIN | PCIE3.CFGTPHSTTWRITEDATA8 |
| CELL95.OUT12.TMIN | PCIE3.DBGDATAOUT12 |
| CELL95.OUT13.TMIN | PCIE3.DBGDATAOUT13 |
| CELL95.OUT14.TMIN | PCIE3.DBGDATAOUT14 |
| CELL95.OUT15.TMIN | PCIE3.DBGDATAOUT15 |
| CELL95.OUT16.TMIN | PCIE3.SCANOUT1 |
| CELL95.OUT17.TMIN | PCIE3.SCANOUT2 |
| CELL95.OUT18.TMIN | PCIE3.SCANOUT3 |
| CELL95.OUT19.TMIN | PCIE3.SCANOUT4 |
| CELL95.OUT20.TMIN | PCIE3.SCANOUT21 |
| CELL95.OUT21.TMIN | PCIE3.SCANOUT22 |
| CELL95.OUT22.TMIN | PCIE3.SCANOUT23 |
| CELL95.OUT23.TMIN | PCIE3.SCANOUT24 |
| CELL96.IMUX.IMUX0.DELAY | PCIE3.PIPETX2EQCOEFF0 |
| CELL96.IMUX.IMUX1.DELAY | PCIE3.PIPETX2EQCOEFF1 |
| CELL96.IMUX.IMUX2.DELAY | PCIE3.PIPETX2EQCOEFF2 |
| CELL96.IMUX.IMUX3.DELAY | PCIE3.PIPETX2EQCOEFF3 |
| CELL96.IMUX.IMUX4.DELAY | PCIE3.PIPETX3EQCOEFF10 |
| CELL96.IMUX.IMUX5.DELAY | PCIE3.PIPETX3EQCOEFF11 |
| CELL96.IMUX.IMUX6.DELAY | PCIE3.PIPETX3EQCOEFF12 |
| CELL96.IMUX.IMUX7.DELAY | PCIE3.PIPETX3EQCOEFF13 |
| CELL96.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA237 |
| CELL96.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA238 |
| CELL96.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA239 |
| CELL96.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA240 |
| CELL96.IMUX.IMUX12.DELAY | PCIE3.CFGDEVID11 |
| CELL96.IMUX.IMUX16.DELAY | PCIE3.PIPERX1CHARISK0 |
| CELL96.IMUX.IMUX32.DELAY | PCIE3.PIPERX1DATA3 |
| CELL96.IMUX.IMUX33.DELAY | PCIE3.PIPERX1DATA2 |
| CELL96.IMUX.IMUX34.DELAY | PCIE3.PIPERX0DATA7 |
| CELL96.IMUX.IMUX35.DELAY | PCIE3.PIPERX0DATA6 |
| CELL96.IMUX.IMUX36.DELAY | PCIE3.PIPERX1DATA1 |
| CELL96.IMUX.IMUX37.DELAY | PCIE3.PIPERX1DATA0 |
| CELL96.IMUX.IMUX38.DELAY | PCIE3.PIPERX0DATA5 |
| CELL96.IMUX.IMUX39.DELAY | PCIE3.PIPERX0DATA4 |
| CELL96.IMUX.IMUX40.DELAY | PCIE3.PIPERX0VALID |
| CELL96.IMUX.IMUX45.DELAY | PCIE3.PIPERX0PHYSTATUS |
| CELL96.OUT0.TMIN | PCIE3.PIPETX5EQDEEMPH0 |
| CELL96.OUT1.TMIN | PCIE3.PIPETX5EQDEEMPH1 |
| CELL96.OUT2.TMIN | PCIE3.PIPETX5EQDEEMPH2 |
| CELL96.OUT3.TMIN | PCIE3.PIPETX5EQDEEMPH3 |
| CELL96.OUT4.TMIN | PCIE3.PLGEN3PCSRXSLIDE5 |
| CELL96.OUT5.TMIN | PCIE3.PLGEN3PCSRXSLIDE6 |
| CELL96.OUT6.TMIN | PCIE3.PLGEN3PCSRXSLIDE7 |
| CELL96.OUT7.TMIN | PCIE3.MAXISCQTDATA0 |
| CELL96.OUT8.TMIN | PCIE3.CFGTPHSTTWRITEDATA9 |
| CELL96.OUT9.TMIN | PCIE3.CFGTPHSTTWRITEDATA10 |
| CELL96.OUT10.TMIN | PCIE3.CFGTPHSTTWRITEDATA11 |
| CELL96.OUT11.TMIN | PCIE3.CFGTPHSTTWRITEDATA12 |
| CELL96.OUT12.TMIN | PCIE3.DRPRDY |
| CELL96.OUT13.TMIN | PCIE3.DRPDO0 |
| CELL96.OUT14.TMIN | PCIE3.DRPDO1 |
| CELL96.OUT15.TMIN | PCIE3.DRPDO2 |
| CELL96.OUT16.TMIN | PCIE3.SCANOUT5 |
| CELL96.OUT17.TMIN | PCIE3.SCANOUT6 |
| CELL96.OUT18.TMIN | PCIE3.SCANOUT7 |
| CELL96.OUT19.TMIN | PCIE3.SCANOUT8 |
| CELL96.OUT20.TMIN | PCIE3.XILUNCONNOUT0 |
| CELL96.OUT21.TMIN | PCIE3.XILUNCONNOUT1 |
| CELL96.OUT22.TMIN | PCIE3.XILUNCONNOUT2 |
| CELL96.OUT23.TMIN | PCIE3.XILUNCONNOUT3 |
| CELL97.IMUX.IMUX0.DELAY | PCIE3.PIPETX2EQCOEFF4 |
| CELL97.IMUX.IMUX1.DELAY | PCIE3.PIPETX2EQCOEFF5 |
| CELL97.IMUX.IMUX2.DELAY | PCIE3.PIPETX2EQCOEFF6 |
| CELL97.IMUX.IMUX3.DELAY | PCIE3.PIPETX2EQCOEFF7 |
| CELL97.IMUX.IMUX4.DELAY | PCIE3.PIPETX3EQCOEFF6 |
| CELL97.IMUX.IMUX5.DELAY | PCIE3.PIPETX3EQCOEFF7 |
| CELL97.IMUX.IMUX6.DELAY | PCIE3.PIPETX3EQCOEFF8 |
| CELL97.IMUX.IMUX7.DELAY | PCIE3.PIPETX3EQCOEFF9 |
| CELL97.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA241 |
| CELL97.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA242 |
| CELL97.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA243 |
| CELL97.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA244 |
| CELL97.IMUX.IMUX12.DELAY | PCIE3.CFGDEVID12 |
| CELL97.IMUX.IMUX13.DELAY | PCIE3.CFGDEVID13 |
| CELL97.IMUX.IMUX14.DELAY | PCIE3.CFGDEVID14 |
| CELL97.IMUX.IMUX15.DELAY | PCIE3.CFGDEVID15 |
| CELL97.IMUX.IMUX16.DELAY | PCIE3.PIPERX0CHARISK0 |
| CELL97.IMUX.IMUX17.DELAY | PCIE3.CFGVENDID13 |
| CELL97.IMUX.IMUX18.DELAY | PCIE3.CFGVENDID14 |
| CELL97.IMUX.IMUX19.DELAY | PCIE3.CFGVENDID15 |
| CELL97.IMUX.IMUX32.DELAY | PCIE3.PIPERX0DATA3 |
| CELL97.IMUX.IMUX33.DELAY | PCIE3.PIPERX0DATA2 |
| CELL97.IMUX.IMUX36.DELAY | PCIE3.PIPERX0DATA1 |
| CELL97.IMUX.IMUX37.DELAY | PCIE3.PIPERX0DATA0 |
| CELL97.OUT0.TMIN | PCIE3.PIPETX5EQDEEMPH4 |
| CELL97.OUT1.TMIN | PCIE3.PIPETX5EQDEEMPH5 |
| CELL97.OUT2.TMIN | PCIE3.PIPETX6EQDEEMPH0 |
| CELL97.OUT3.TMIN | PCIE3.PIPETX6EQDEEMPH1 |
| CELL97.OUT4.TMIN | PCIE3.PLGEN3PCSRXSLIDE1 |
| CELL97.OUT5.TMIN | PCIE3.PLGEN3PCSRXSLIDE2 |
| CELL97.OUT6.TMIN | PCIE3.PLGEN3PCSRXSLIDE3 |
| CELL97.OUT7.TMIN | PCIE3.PLGEN3PCSRXSLIDE4 |
| CELL97.OUT8.TMIN | PCIE3.CFGTPHSTTWRITEDATA13 |
| CELL97.OUT9.TMIN | PCIE3.CFGTPHSTTWRITEDATA14 |
| CELL97.OUT10.TMIN | PCIE3.CFGTPHSTTWRITEDATA15 |
| CELL97.OUT11.TMIN | PCIE3.CFGTPHSTTWRITEDATA16 |
| CELL97.OUT12.TMIN | PCIE3.DRPDO3 |
| CELL97.OUT13.TMIN | PCIE3.DRPDO4 |
| CELL97.OUT14.TMIN | PCIE3.DRPDO5 |
| CELL97.OUT15.TMIN | PCIE3.DRPDO6 |
| CELL97.OUT16.TMIN | PCIE3.SCANOUT9 |
| CELL97.OUT17.TMIN | PCIE3.SCANOUT10 |
| CELL97.OUT18.TMIN | PCIE3.SCANOUT11 |
| CELL97.OUT19.TMIN | PCIE3.SCANOUT12 |
| CELL97.OUT20.TMIN | PCIE3.XILUNCONNOUT4 |
| CELL97.OUT21.TMIN | PCIE3.XILUNCONNOUT5 |
| CELL97.OUT22.TMIN | PCIE3.XILUNCONNOUT6 |
| CELL97.OUT23.TMIN | PCIE3.XILUNCONNOUT7 |
| CELL98.IMUX.IMUX0.DELAY | PCIE3.PIPETX2EQCOEFF8 |
| CELL98.IMUX.IMUX1.DELAY | PCIE3.PIPETX2EQCOEFF9 |
| CELL98.IMUX.IMUX2.DELAY | PCIE3.PIPETX2EQCOEFF10 |
| CELL98.IMUX.IMUX3.DELAY | PCIE3.PIPETX2EQCOEFF11 |
| CELL98.IMUX.IMUX4.DELAY | PCIE3.PIPETX3EQCOEFF2 |
| CELL98.IMUX.IMUX5.DELAY | PCIE3.PIPETX3EQCOEFF3 |
| CELL98.IMUX.IMUX6.DELAY | PCIE3.PIPETX3EQCOEFF4 |
| CELL98.IMUX.IMUX7.DELAY | PCIE3.PIPETX3EQCOEFF5 |
| CELL98.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA245 |
| CELL98.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA246 |
| CELL98.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA247 |
| CELL98.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA248 |
| CELL98.IMUX.IMUX12.DELAY | PCIE3.CFGVENDID0 |
| CELL98.IMUX.IMUX13.DELAY | PCIE3.CFGVENDID1 |
| CELL98.IMUX.IMUX14.DELAY | PCIE3.CFGVENDID2 |
| CELL98.IMUX.IMUX15.DELAY | PCIE3.CFGVENDID3 |
| CELL98.IMUX.IMUX16.DELAY | PCIE3.CFGVENDID9 |
| CELL98.IMUX.IMUX17.DELAY | PCIE3.CFGVENDID10 |
| CELL98.IMUX.IMUX18.DELAY | PCIE3.CFGVENDID11 |
| CELL98.IMUX.IMUX19.DELAY | PCIE3.CFGVENDID12 |
| CELL98.IMUX.IMUX20.DELAY | PCIE3.CFGVFFLRDONE5 |
| CELL98.IMUX.IMUX21.DELAY | PCIE3.CFGREQPMTRANSITIONL23READY |
| CELL98.IMUX.IMUX22.DELAY | PCIE3.CFGLINKTRAININGENABLE |
| CELL98.OUT0.TMIN | PCIE3.PIPETX6EQDEEMPH2 |
| CELL98.OUT1.TMIN | PCIE3.PIPETX6EQDEEMPH3 |
| CELL98.OUT2.TMIN | PCIE3.PIPETX6EQDEEMPH4 |
| CELL98.OUT3.TMIN | PCIE3.PIPETX6EQDEEMPH5 |
| CELL98.OUT4.TMIN | PCIE3.PLEQINPROGRESS |
| CELL98.OUT5.TMIN | PCIE3.PLEQPHASE0 |
| CELL98.OUT6.TMIN | PCIE3.PLEQPHASE1 |
| CELL98.OUT7.TMIN | PCIE3.PLGEN3PCSRXSLIDE0 |
| CELL98.OUT8.TMIN | PCIE3.CFGTPHSTTWRITEDATA17 |
| CELL98.OUT9.TMIN | PCIE3.CFGTPHSTTWRITEDATA18 |
| CELL98.OUT10.TMIN | PCIE3.CFGTPHSTTWRITEDATA19 |
| CELL98.OUT11.TMIN | PCIE3.CFGTPHSTTWRITEDATA20 |
| CELL98.OUT12.TMIN | PCIE3.DRPDO7 |
| CELL98.OUT13.TMIN | PCIE3.DRPDO8 |
| CELL98.OUT14.TMIN | PCIE3.DRPDO9 |
| CELL98.OUT15.TMIN | PCIE3.DRPDO10 |
| CELL98.OUT16.TMIN | PCIE3.SCANOUT13 |
| CELL98.OUT17.TMIN | PCIE3.SCANOUT14 |
| CELL98.OUT18.TMIN | PCIE3.SCANOUT15 |
| CELL98.OUT19.TMIN | PCIE3.SCANOUT16 |
| CELL98.OUT20.TMIN | PCIE3.XILUNCONNOUT8 |
| CELL98.OUT21.TMIN | PCIE3.XILUNCONNOUT9 |
| CELL98.OUT22.TMIN | PCIE3.XILUNCONNOUT10 |
| CELL98.OUT23.TMIN | PCIE3.XILUNCONNOUT11 |
| CELL99.IMUX.IMUX0.DELAY | PCIE3.PIPETX2EQCOEFF12 |
| CELL99.IMUX.IMUX1.DELAY | PCIE3.PIPETX2EQCOEFF13 |
| CELL99.IMUX.IMUX2.DELAY | PCIE3.PIPETX2EQCOEFF14 |
| CELL99.IMUX.IMUX3.DELAY | PCIE3.PIPETX2EQCOEFF15 |
| CELL99.IMUX.IMUX4.DELAY | PCIE3.PIPETX2EQCOEFF16 |
| CELL99.IMUX.IMUX5.DELAY | PCIE3.PIPETX2EQCOEFF17 |
| CELL99.IMUX.IMUX6.DELAY | PCIE3.PIPETX3EQCOEFF0 |
| CELL99.IMUX.IMUX7.DELAY | PCIE3.PIPETX3EQCOEFF1 |
| CELL99.IMUX.IMUX8.DELAY | PCIE3.SAXISCCTDATA249 |
| CELL99.IMUX.IMUX9.DELAY | PCIE3.SAXISCCTDATA250 |
| CELL99.IMUX.IMUX10.DELAY | PCIE3.SAXISCCTDATA251 |
| CELL99.IMUX.IMUX11.DELAY | PCIE3.SAXISCCTDATA252 |
| CELL99.IMUX.IMUX12.DELAY | PCIE3.SAXISCCTDATA253 |
| CELL99.IMUX.IMUX13.DELAY | PCIE3.SAXISCCTDATA254 |
| CELL99.IMUX.IMUX14.DELAY | PCIE3.SAXISCCTDATA255 |
| CELL99.IMUX.IMUX15.DELAY | PCIE3.CFGVENDID4 |
| CELL99.IMUX.IMUX16.DELAY | PCIE3.CFGVENDID5 |
| CELL99.IMUX.IMUX17.DELAY | PCIE3.CFGVENDID6 |
| CELL99.IMUX.IMUX18.DELAY | PCIE3.CFGVENDID7 |
| CELL99.IMUX.IMUX19.DELAY | PCIE3.CFGVENDID8 |
| CELL99.OUT0.TMIN | PCIE3.PIPETX7EQDEEMPH0 |
| CELL99.OUT1.TMIN | PCIE3.PIPETX7EQDEEMPH1 |
| CELL99.OUT2.TMIN | PCIE3.PIPETX7EQDEEMPH2 |
| CELL99.OUT3.TMIN | PCIE3.PIPETX7EQDEEMPH3 |
| CELL99.OUT4.TMIN | PCIE3.PIPETX7EQDEEMPH4 |
| CELL99.OUT5.TMIN | PCIE3.PIPETX7EQDEEMPH5 |
| CELL99.OUT6.TMIN | PCIE3.PIPETXRATE1 |
| CELL99.OUT7.TMIN | PCIE3.PIPETXSWING |
| CELL99.OUT8.TMIN | PCIE3.CFGTPHSTTWRITEDATA21 |
| CELL99.OUT9.TMIN | PCIE3.CFGTPHSTTWRITEDATA22 |
| CELL99.OUT10.TMIN | PCIE3.CFGTPHSTTWRITEDATA23 |
| CELL99.OUT11.TMIN | PCIE3.CFGTPHSTTWRITEDATA24 |
| CELL99.OUT12.TMIN | PCIE3.DRPDO11 |
| CELL99.OUT13.TMIN | PCIE3.DRPDO12 |
| CELL99.OUT14.TMIN | PCIE3.DRPDO13 |
| CELL99.OUT15.TMIN | PCIE3.DRPDO14 |
| CELL99.OUT16.TMIN | PCIE3.SCANOUT17 |
| CELL99.OUT17.TMIN | PCIE3.SCANOUT18 |
| CELL99.OUT18.TMIN | PCIE3.SCANOUT19 |
| CELL99.OUT19.TMIN | PCIE3.SCANOUT20 |
| CELL99.OUT20.TMIN | PCIE3.XILUNCONNOUT12 |
| CELL99.OUT21.TMIN | PCIE3.XILUNCONNOUT13 |
| CELL99.OUT22.TMIN | PCIE3.XILUNCONNOUT14 |
| CELL99.OUT23.TMIN | PCIE3.XILUNCONNOUT15 |
Bitstream
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_L1_REENTRY_DELAY[30] | PCIE3:PM_L1_REENTRY_DELAY[31] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_L1_REENTRY_DELAY[28] | PCIE3:PM_L1_REENTRY_DELAY[29] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_L1_REENTRY_DELAY[26] | PCIE3:PM_L1_REENTRY_DELAY[27] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_L1_REENTRY_DELAY[24] | PCIE3:PM_L1_REENTRY_DELAY[25] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_L1_REENTRY_DELAY[22] | PCIE3:PM_L1_REENTRY_DELAY[23] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_L1_REENTRY_DELAY[20] | PCIE3:PM_L1_REENTRY_DELAY[21] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_L1_REENTRY_DELAY[18] | PCIE3:PM_L1_REENTRY_DELAY[19] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_L1_REENTRY_DELAY[16] | PCIE3:PM_L1_REENTRY_DELAY[17] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_L1_REENTRY_DELAY[14] | PCIE3:PM_L1_REENTRY_DELAY[15] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_L1_REENTRY_DELAY[12] | PCIE3:PM_L1_REENTRY_DELAY[13] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_L1_REENTRY_DELAY[10] | PCIE3:PM_L1_REENTRY_DELAY[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_L1_REENTRY_DELAY[8] | PCIE3:PM_L1_REENTRY_DELAY[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_L1_REENTRY_DELAY[6] | PCIE3:PM_L1_REENTRY_DELAY[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_L1_REENTRY_DELAY[4] | PCIE3:PM_L1_REENTRY_DELAY[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_L1_REENTRY_DELAY[2] | PCIE3:PM_L1_REENTRY_DELAY[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_L1_REENTRY_DELAY[0] | PCIE3:PM_L1_REENTRY_DELAY[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML0S_TIMEOUT[14] | PCIE3:PM_ASPML0S_TIMEOUT[15] |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML0S_TIMEOUT[12] | PCIE3:PM_ASPML0S_TIMEOUT[13] |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML0S_TIMEOUT[10] | PCIE3:PM_ASPML0S_TIMEOUT[11] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML0S_TIMEOUT[8] | PCIE3:PM_ASPML0S_TIMEOUT[9] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML0S_TIMEOUT[6] | PCIE3:PM_ASPML0S_TIMEOUT[7] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML0S_TIMEOUT[4] | PCIE3:PM_ASPML0S_TIMEOUT[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML0S_TIMEOUT[2] | PCIE3:PM_ASPML0S_TIMEOUT[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML0S_TIMEOUT[0] | PCIE3:PM_ASPML0S_TIMEOUT[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:AXISTEN_IF_ENABLE_CLIENT_TAG | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:AXISTEN_IF_RQ_PARITY_CHK | PCIE3:AXISTEN_IF_CC_PARITY_CHK |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[16] | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[17] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[14] | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[15] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[12] | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[13] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[10] | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[11] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[8] | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[9] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[6] | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[4] | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[2] | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[0] | PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:AXISTEN_IF_ENABLE_RX_MSG_INTFC | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:AXISTEN_IF_RC_ALIGNMENT_MODE | PCIE3:AXISTEN_IF_RC_STRADDLE |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:AXISTEN_IF_CC_ALIGNMENT_MODE | PCIE3:AXISTEN_IF_RQ_ALIGNMENT_MODE |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:AXISTEN_IF_WIDTH[1] | PCIE3:AXISTEN_IF_CQ_ALIGNMENT_MODE |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:CRM_USER_CLK_FREQ[1] | PCIE3:AXISTEN_IF_WIDTH[0] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:CRM_CORE_CLK_FREQ_500 | PCIE3:CRM_USER_CLK_FREQ[0] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LINK_CAP_MAX_LINK_SPEED[1] | PCIE3:PL_LINK_CAP_MAX_LINK_SPEED[2] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LINK_CAP_MAX_LINK_WIDTH[3] | PCIE3:PL_LINK_CAP_MAX_LINK_SPEED[0] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LINK_CAP_MAX_LINK_WIDTH[1] | PCIE3:PL_LINK_CAP_MAX_LINK_WIDTH[2] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LINK_CAP_MAX_LINK_WIDTH[0] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_TURNOFF_ACK_DELAY[14] | PCIE3:PM_PME_TURNOFF_ACK_DELAY[15] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_TURNOFF_ACK_DELAY[12] | PCIE3:PM_PME_TURNOFF_ACK_DELAY[13] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_TURNOFF_ACK_DELAY[10] | PCIE3:PM_PME_TURNOFF_ACK_DELAY[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_TURNOFF_ACK_DELAY[8] | PCIE3:PM_PME_TURNOFF_ACK_DELAY[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_TURNOFF_ACK_DELAY[6] | PCIE3:PM_PME_TURNOFF_ACK_DELAY[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_TURNOFF_ACK_DELAY[4] | PCIE3:PM_PME_TURNOFF_ACK_DELAY[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_TURNOFF_ACK_DELAY[2] | PCIE3:PM_PME_TURNOFF_ACK_DELAY[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_TURNOFF_ACK_DELAY[0] | PCIE3:PM_PME_TURNOFF_ACK_DELAY[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[18] | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[19] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[16] | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[17] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[14] | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[15] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[12] | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[13] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[10] | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[8] | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[6] | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[4] | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[2] | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[0] | PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML1_ENTRY_DELAY[18] | PCIE3:PM_ASPML1_ENTRY_DELAY[19] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML1_ENTRY_DELAY[16] | PCIE3:PM_ASPML1_ENTRY_DELAY[17] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML1_ENTRY_DELAY[14] | PCIE3:PM_ASPML1_ENTRY_DELAY[15] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML1_ENTRY_DELAY[12] | PCIE3:PM_ASPML1_ENTRY_DELAY[13] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML1_ENTRY_DELAY[10] | PCIE3:PM_ASPML1_ENTRY_DELAY[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML1_ENTRY_DELAY[8] | PCIE3:PM_ASPML1_ENTRY_DELAY[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML1_ENTRY_DELAY[6] | PCIE3:PM_ASPML1_ENTRY_DELAY[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML1_ENTRY_DELAY[4] | PCIE3:PM_ASPML1_ENTRY_DELAY[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML1_ENTRY_DELAY[2] | PCIE3:PM_ASPML1_ENTRY_DELAY[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PM_ASPML1_ENTRY_DELAY[0] | PCIE3:PM_ASPML1_ENTRY_DELAY[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE1_EQ_CONTROL[14] | PCIE3:PL_LANE1_EQ_CONTROL[15] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE1_EQ_CONTROL[12] | PCIE3:PL_LANE1_EQ_CONTROL[13] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE1_EQ_CONTROL[10] | PCIE3:PL_LANE1_EQ_CONTROL[11] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE1_EQ_CONTROL[8] | PCIE3:PL_LANE1_EQ_CONTROL[9] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE1_EQ_CONTROL[6] | PCIE3:PL_LANE1_EQ_CONTROL[7] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE1_EQ_CONTROL[4] | PCIE3:PL_LANE1_EQ_CONTROL[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE1_EQ_CONTROL[2] | PCIE3:PL_LANE1_EQ_CONTROL[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE1_EQ_CONTROL[0] | PCIE3:PL_LANE1_EQ_CONTROL[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE0_EQ_CONTROL[14] | PCIE3:PL_LANE0_EQ_CONTROL[15] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE0_EQ_CONTROL[12] | PCIE3:PL_LANE0_EQ_CONTROL[13] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE0_EQ_CONTROL[10] | PCIE3:PL_LANE0_EQ_CONTROL[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE0_EQ_CONTROL[8] | PCIE3:PL_LANE0_EQ_CONTROL[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE0_EQ_CONTROL[6] | PCIE3:PL_LANE0_EQ_CONTROL[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE0_EQ_CONTROL[4] | PCIE3:PL_LANE0_EQ_CONTROL[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE0_EQ_CONTROL[2] | PCIE3:PL_LANE0_EQ_CONTROL[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE0_EQ_CONTROL[0] | PCIE3:PL_LANE0_EQ_CONTROL[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_GEN3[6] | PCIE3:PL_N_FTS_GEN3[7] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_GEN3[4] | PCIE3:PL_N_FTS_GEN3[5] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_GEN3[2] | PCIE3:PL_N_FTS_GEN3[3] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_GEN3[0] | PCIE3:PL_N_FTS_GEN3[1] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_COMCLK_GEN3[6] | PCIE3:PL_N_FTS_COMCLK_GEN3[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_COMCLK_GEN3[4] | PCIE3:PL_N_FTS_COMCLK_GEN3[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_COMCLK_GEN3[2] | PCIE3:PL_N_FTS_COMCLK_GEN3[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_COMCLK_GEN3[0] | PCIE3:PL_N_FTS_COMCLK_GEN3[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_GEN2[6] | PCIE3:PL_N_FTS_GEN2[7] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_GEN2[4] | PCIE3:PL_N_FTS_GEN2[5] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_GEN2[2] | PCIE3:PL_N_FTS_GEN2[3] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_GEN2[0] | PCIE3:PL_N_FTS_GEN2[1] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_COMCLK_GEN2[6] | PCIE3:PL_N_FTS_COMCLK_GEN2[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_COMCLK_GEN2[4] | PCIE3:PL_N_FTS_COMCLK_GEN2[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_COMCLK_GEN2[2] | PCIE3:PL_N_FTS_COMCLK_GEN2[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_COMCLK_GEN2[0] | PCIE3:PL_N_FTS_COMCLK_GEN2[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_GEN1[6] | PCIE3:PL_N_FTS_GEN1[7] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_GEN1[4] | PCIE3:PL_N_FTS_GEN1[5] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_GEN1[2] | PCIE3:PL_N_FTS_GEN1[3] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_GEN1[0] | PCIE3:PL_N_FTS_GEN1[1] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_COMCLK_GEN1[6] | PCIE3:PL_N_FTS_COMCLK_GEN1[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_COMCLK_GEN1[4] | PCIE3:PL_N_FTS_COMCLK_GEN1[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_COMCLK_GEN1[2] | PCIE3:PL_N_FTS_COMCLK_GEN1[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_N_FTS_COMCLK_GEN1[0] | PCIE3:PL_N_FTS_COMCLK_GEN1[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE7_EQ_CONTROL[14] | PCIE3:PL_LANE7_EQ_CONTROL[15] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE7_EQ_CONTROL[12] | PCIE3:PL_LANE7_EQ_CONTROL[13] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE7_EQ_CONTROL[10] | PCIE3:PL_LANE7_EQ_CONTROL[11] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE7_EQ_CONTROL[8] | PCIE3:PL_LANE7_EQ_CONTROL[9] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE7_EQ_CONTROL[6] | PCIE3:PL_LANE7_EQ_CONTROL[7] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE7_EQ_CONTROL[4] | PCIE3:PL_LANE7_EQ_CONTROL[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE7_EQ_CONTROL[2] | PCIE3:PL_LANE7_EQ_CONTROL[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE7_EQ_CONTROL[0] | PCIE3:PL_LANE7_EQ_CONTROL[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE6_EQ_CONTROL[14] | PCIE3:PL_LANE6_EQ_CONTROL[15] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE6_EQ_CONTROL[12] | PCIE3:PL_LANE6_EQ_CONTROL[13] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE6_EQ_CONTROL[10] | PCIE3:PL_LANE6_EQ_CONTROL[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE6_EQ_CONTROL[8] | PCIE3:PL_LANE6_EQ_CONTROL[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE6_EQ_CONTROL[6] | PCIE3:PL_LANE6_EQ_CONTROL[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE6_EQ_CONTROL[4] | PCIE3:PL_LANE6_EQ_CONTROL[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE6_EQ_CONTROL[2] | PCIE3:PL_LANE6_EQ_CONTROL[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE6_EQ_CONTROL[0] | PCIE3:PL_LANE6_EQ_CONTROL[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE5_EQ_CONTROL[14] | PCIE3:PL_LANE5_EQ_CONTROL[15] |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE5_EQ_CONTROL[12] | PCIE3:PL_LANE5_EQ_CONTROL[13] |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE5_EQ_CONTROL[10] | PCIE3:PL_LANE5_EQ_CONTROL[11] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE5_EQ_CONTROL[8] | PCIE3:PL_LANE5_EQ_CONTROL[9] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE5_EQ_CONTROL[6] | PCIE3:PL_LANE5_EQ_CONTROL[7] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE5_EQ_CONTROL[4] | PCIE3:PL_LANE5_EQ_CONTROL[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE5_EQ_CONTROL[2] | PCIE3:PL_LANE5_EQ_CONTROL[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE5_EQ_CONTROL[0] | PCIE3:PL_LANE5_EQ_CONTROL[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE4_EQ_CONTROL[14] | PCIE3:PL_LANE4_EQ_CONTROL[15] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE4_EQ_CONTROL[12] | PCIE3:PL_LANE4_EQ_CONTROL[13] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE4_EQ_CONTROL[10] | PCIE3:PL_LANE4_EQ_CONTROL[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE4_EQ_CONTROL[8] | PCIE3:PL_LANE4_EQ_CONTROL[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE4_EQ_CONTROL[6] | PCIE3:PL_LANE4_EQ_CONTROL[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE4_EQ_CONTROL[4] | PCIE3:PL_LANE4_EQ_CONTROL[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE4_EQ_CONTROL[2] | PCIE3:PL_LANE4_EQ_CONTROL[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE4_EQ_CONTROL[0] | PCIE3:PL_LANE4_EQ_CONTROL[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE3_EQ_CONTROL[14] | PCIE3:PL_LANE3_EQ_CONTROL[15] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE3_EQ_CONTROL[12] | PCIE3:PL_LANE3_EQ_CONTROL[13] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE3_EQ_CONTROL[10] | PCIE3:PL_LANE3_EQ_CONTROL[11] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE3_EQ_CONTROL[8] | PCIE3:PL_LANE3_EQ_CONTROL[9] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE3_EQ_CONTROL[6] | PCIE3:PL_LANE3_EQ_CONTROL[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE3_EQ_CONTROL[4] | PCIE3:PL_LANE3_EQ_CONTROL[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE3_EQ_CONTROL[2] | PCIE3:PL_LANE3_EQ_CONTROL[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE3_EQ_CONTROL[0] | PCIE3:PL_LANE3_EQ_CONTROL[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE2_EQ_CONTROL[14] | PCIE3:PL_LANE2_EQ_CONTROL[15] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE2_EQ_CONTROL[12] | PCIE3:PL_LANE2_EQ_CONTROL[13] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE2_EQ_CONTROL[10] | PCIE3:PL_LANE2_EQ_CONTROL[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE2_EQ_CONTROL[8] | PCIE3:PL_LANE2_EQ_CONTROL[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE2_EQ_CONTROL[6] | PCIE3:PL_LANE2_EQ_CONTROL[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE2_EQ_CONTROL[4] | PCIE3:PL_LANE2_EQ_CONTROL[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE2_EQ_CONTROL[2] | PCIE3:PL_LANE2_EQ_CONTROL[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_LANE2_EQ_CONTROL[0] | PCIE3:PL_LANE2_EQ_CONTROL[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_P_FC_UPDATE_TIMER[14] | PCIE3:LL_P_FC_UPDATE_TIMER[15] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_P_FC_UPDATE_TIMER[12] | PCIE3:LL_P_FC_UPDATE_TIMER[13] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_P_FC_UPDATE_TIMER[10] | PCIE3:LL_P_FC_UPDATE_TIMER[11] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_P_FC_UPDATE_TIMER[8] | PCIE3:LL_P_FC_UPDATE_TIMER[9] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_P_FC_UPDATE_TIMER[6] | PCIE3:LL_P_FC_UPDATE_TIMER[7] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_P_FC_UPDATE_TIMER[4] | PCIE3:LL_P_FC_UPDATE_TIMER[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_P_FC_UPDATE_TIMER[2] | PCIE3:LL_P_FC_UPDATE_TIMER[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_P_FC_UPDATE_TIMER[0] | PCIE3:LL_P_FC_UPDATE_TIMER[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_P_FC_UPDATE_TIMER_OVERRIDE | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_CPL_FC_UPDATE_TIMER[14] | PCIE3:LL_CPL_FC_UPDATE_TIMER[15] |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_CPL_FC_UPDATE_TIMER[12] | PCIE3:LL_CPL_FC_UPDATE_TIMER[13] |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_CPL_FC_UPDATE_TIMER[10] | PCIE3:LL_CPL_FC_UPDATE_TIMER[11] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_CPL_FC_UPDATE_TIMER[8] | PCIE3:LL_CPL_FC_UPDATE_TIMER[9] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_CPL_FC_UPDATE_TIMER[6] | PCIE3:LL_CPL_FC_UPDATE_TIMER[7] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_CPL_FC_UPDATE_TIMER[4] | PCIE3:LL_CPL_FC_UPDATE_TIMER[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_CPL_FC_UPDATE_TIMER[2] | PCIE3:LL_CPL_FC_UPDATE_TIMER[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_CPL_FC_UPDATE_TIMER[0] | PCIE3:LL_CPL_FC_UPDATE_TIMER[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_REPLAY_TIMEOUT_FUNC[1] | PCIE3:LL_CPL_FC_UPDATE_TIMER_OVERRIDE |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_REPLAY_TIMEOUT[8] | PCIE3:LL_REPLAY_TIMEOUT_FUNC[0] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_REPLAY_TIMEOUT[6] | PCIE3:LL_REPLAY_TIMEOUT[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_REPLAY_TIMEOUT[4] | PCIE3:LL_REPLAY_TIMEOUT[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_REPLAY_TIMEOUT[2] | PCIE3:LL_REPLAY_TIMEOUT[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_REPLAY_TIMEOUT[0] | PCIE3:LL_REPLAY_TIMEOUT[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_ACK_TIMEOUT_FUNC[1] | PCIE3:LL_REPLAY_TIMEOUT_EN |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_ACK_TIMEOUT[8] | PCIE3:LL_ACK_TIMEOUT_FUNC[0] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_ACK_TIMEOUT[6] | PCIE3:LL_ACK_TIMEOUT[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_ACK_TIMEOUT[4] | PCIE3:LL_ACK_TIMEOUT[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_ACK_TIMEOUT[2] | PCIE3:LL_ACK_TIMEOUT[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_ACK_TIMEOUT[0] | PCIE3:LL_ACK_TIMEOUT[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_ACK_TIMEOUT_EN | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_EQ_ADAPT_REJECT_RETRY_COUNT[0] | PCIE3:PL_EQ_ADAPT_REJECT_RETRY_COUNT[1] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_EQ_ADAPT_ITER_COUNT[3] | PCIE3:PL_EQ_ADAPT_ITER_COUNT[4] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_EQ_ADAPT_ITER_COUNT[1] | PCIE3:PL_EQ_ADAPT_ITER_COUNT[2] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PL_EQ_ADAPT_ITER_COUNT[0] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CH[6] | PCIE3:TL_CREDITS_CH[7] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CH[4] | PCIE3:TL_CREDITS_CH[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CH[2] | PCIE3:TL_CREDITS_CH[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CH[0] | PCIE3:TL_CREDITS_CH[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CD[11] | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CD[9] | PCIE3:TL_CREDITS_CD[10] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CD[7] | PCIE3:TL_CREDITS_CD[8] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CD[5] | PCIE3:TL_CREDITS_CD[6] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CD[3] | PCIE3:TL_CREDITS_CD[4] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CD[1] | PCIE3:TL_CREDITS_CD[2] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_CD[0] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER[14] | PCIE3:LL_FC_UPDATE_TIMER[15] |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER[12] | PCIE3:LL_FC_UPDATE_TIMER[13] |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER[10] | PCIE3:LL_FC_UPDATE_TIMER[11] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER[8] | PCIE3:LL_FC_UPDATE_TIMER[9] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER[6] | PCIE3:LL_FC_UPDATE_TIMER[7] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER[4] | PCIE3:LL_FC_UPDATE_TIMER[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER[2] | PCIE3:LL_FC_UPDATE_TIMER[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER[0] | PCIE3:LL_FC_UPDATE_TIMER[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_FC_UPDATE_TIMER_OVERRIDE | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER[14] | PCIE3:LL_NP_FC_UPDATE_TIMER[15] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER[12] | PCIE3:LL_NP_FC_UPDATE_TIMER[13] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER[10] | PCIE3:LL_NP_FC_UPDATE_TIMER[11] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER[8] | PCIE3:LL_NP_FC_UPDATE_TIMER[9] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER[6] | PCIE3:LL_NP_FC_UPDATE_TIMER[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER[4] | PCIE3:LL_NP_FC_UPDATE_TIMER[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER[2] | PCIE3:LL_NP_FC_UPDATE_TIMER[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER[0] | PCIE3:LL_NP_FC_UPDATE_TIMER[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LL_NP_FC_UPDATE_TIMER_OVERRIDE | - |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG0[22] | PCIE3:TL_COMPL_TIMEOUT_REG0[23] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG0[20] | PCIE3:TL_COMPL_TIMEOUT_REG0[21] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG0[18] | PCIE3:TL_COMPL_TIMEOUT_REG0[19] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG0[16] | PCIE3:TL_COMPL_TIMEOUT_REG0[17] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG0[14] | PCIE3:TL_COMPL_TIMEOUT_REG0[15] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG0[12] | PCIE3:TL_COMPL_TIMEOUT_REG0[13] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG0[10] | PCIE3:TL_COMPL_TIMEOUT_REG0[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG0[8] | PCIE3:TL_COMPL_TIMEOUT_REG0[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG0[6] | PCIE3:TL_COMPL_TIMEOUT_REG0[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG0[4] | PCIE3:TL_COMPL_TIMEOUT_REG0[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG0[2] | PCIE3:TL_COMPL_TIMEOUT_REG0[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG0[0] | PCIE3:TL_COMPL_TIMEOUT_REG0[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_PH[6] | PCIE3:TL_CREDITS_PH[7] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_PH[4] | PCIE3:TL_CREDITS_PH[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_PH[2] | PCIE3:TL_CREDITS_PH[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_PH[0] | PCIE3:TL_CREDITS_PH[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_PD[10] | PCIE3:TL_CREDITS_PD[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_PD[8] | PCIE3:TL_CREDITS_PD[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_PD[6] | PCIE3:TL_CREDITS_PD[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_PD[4] | PCIE3:TL_CREDITS_PD[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_PD[2] | PCIE3:TL_CREDITS_PD[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_PD[0] | PCIE3:TL_CREDITS_PD[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_NPH[6] | PCIE3:TL_CREDITS_NPH[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_NPH[4] | PCIE3:TL_CREDITS_NPH[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_NPH[2] | PCIE3:TL_CREDITS_NPH[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_NPH[0] | PCIE3:TL_CREDITS_NPH[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_NPD[10] | PCIE3:TL_CREDITS_NPD[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_NPD[8] | PCIE3:TL_CREDITS_NPD[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_NPD[6] | PCIE3:TL_CREDITS_NPD[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_NPD[4] | PCIE3:TL_CREDITS_NPD[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_NPD[2] | PCIE3:TL_CREDITS_NPD[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_CREDITS_NPD[0] | PCIE3:TL_CREDITS_NPD[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_CLASS_CODE[14] | PCIE3:PF0_CLASS_CODE[15] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_CLASS_CODE[12] | PCIE3:PF0_CLASS_CODE[13] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_CLASS_CODE[10] | PCIE3:PF0_CLASS_CODE[11] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_CLASS_CODE[8] | PCIE3:PF0_CLASS_CODE[9] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_CLASS_CODE[6] | PCIE3:PF0_CLASS_CODE[7] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_CLASS_CODE[4] | PCIE3:PF0_CLASS_CODE[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_CLASS_CODE[2] | PCIE3:PF0_CLASS_CODE[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_CLASS_CODE[0] | PCIE3:PF0_CLASS_CODE[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_REVISION_ID[6] | PCIE3:PF1_REVISION_ID[7] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_REVISION_ID[4] | PCIE3:PF1_REVISION_ID[5] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_REVISION_ID[2] | PCIE3:PF1_REVISION_ID[3] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_REVISION_ID[0] | PCIE3:PF1_REVISION_ID[1] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_REVISION_ID[6] | PCIE3:PF0_REVISION_ID[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_REVISION_ID[4] | PCIE3:PF0_REVISION_ID[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_REVISION_ID[2] | PCIE3:PF0_REVISION_ID[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_REVISION_ID[0] | PCIE3:PF0_REVISION_ID[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_DEVICE_ID[14] | PCIE3:PF1_DEVICE_ID[15] |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_DEVICE_ID[12] | PCIE3:PF1_DEVICE_ID[13] |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_DEVICE_ID[10] | PCIE3:PF1_DEVICE_ID[11] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_DEVICE_ID[8] | PCIE3:PF1_DEVICE_ID[9] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_DEVICE_ID[6] | PCIE3:PF1_DEVICE_ID[7] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_DEVICE_ID[4] | PCIE3:PF1_DEVICE_ID[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_DEVICE_ID[2] | PCIE3:PF1_DEVICE_ID[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_DEVICE_ID[0] | PCIE3:PF1_DEVICE_ID[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DEVICE_ID[14] | PCIE3:PF0_DEVICE_ID[15] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DEVICE_ID[12] | PCIE3:PF0_DEVICE_ID[13] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DEVICE_ID[10] | PCIE3:PF0_DEVICE_ID[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DEVICE_ID[8] | PCIE3:PF0_DEVICE_ID[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DEVICE_ID[6] | PCIE3:PF0_DEVICE_ID[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DEVICE_ID[4] | PCIE3:PF0_DEVICE_ID[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DEVICE_ID[2] | PCIE3:PF0_DEVICE_ID[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DEVICE_ID[0] | PCIE3:PF0_DEVICE_ID[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG1[26] | PCIE3:TL_COMPL_TIMEOUT_REG1[27] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG1[24] | PCIE3:TL_COMPL_TIMEOUT_REG1[25] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG1[22] | PCIE3:TL_COMPL_TIMEOUT_REG1[23] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG1[20] | PCIE3:TL_COMPL_TIMEOUT_REG1[21] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG1[18] | PCIE3:TL_COMPL_TIMEOUT_REG1[19] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG1[16] | PCIE3:TL_COMPL_TIMEOUT_REG1[17] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG1[14] | PCIE3:TL_COMPL_TIMEOUT_REG1[15] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG1[12] | PCIE3:TL_COMPL_TIMEOUT_REG1[13] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG1[10] | PCIE3:TL_COMPL_TIMEOUT_REG1[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG1[8] | PCIE3:TL_COMPL_TIMEOUT_REG1[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG1[6] | PCIE3:TL_COMPL_TIMEOUT_REG1[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG1[4] | PCIE3:TL_COMPL_TIMEOUT_REG1[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG1[2] | PCIE3:TL_COMPL_TIMEOUT_REG1[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:TL_COMPL_TIMEOUT_REG1[0] | PCIE3:TL_COMPL_TIMEOUT_REG1[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_INTERRUPT_LINE[6] | PCIE3:PF0_INTERRUPT_LINE[7] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_INTERRUPT_LINE[4] | PCIE3:PF0_INTERRUPT_LINE[5] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_INTERRUPT_LINE[2] | PCIE3:PF0_INTERRUPT_LINE[3] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_INTERRUPT_LINE[0] | PCIE3:PF0_INTERRUPT_LINE[1] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_INTERRUPT_PIN[1] | PCIE3:PF1_INTERRUPT_PIN[2] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_INTERRUPT_PIN[2] | PCIE3:PF1_INTERRUPT_PIN[0] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_INTERRUPT_PIN[0] | PCIE3:PF0_INTERRUPT_PIN[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SUBSYSTEM_ID[14] | PCIE3:PF1_SUBSYSTEM_ID[15] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SUBSYSTEM_ID[12] | PCIE3:PF1_SUBSYSTEM_ID[13] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SUBSYSTEM_ID[10] | PCIE3:PF1_SUBSYSTEM_ID[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SUBSYSTEM_ID[8] | PCIE3:PF1_SUBSYSTEM_ID[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SUBSYSTEM_ID[6] | PCIE3:PF1_SUBSYSTEM_ID[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SUBSYSTEM_ID[4] | PCIE3:PF1_SUBSYSTEM_ID[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SUBSYSTEM_ID[2] | PCIE3:PF1_SUBSYSTEM_ID[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SUBSYSTEM_ID[0] | PCIE3:PF1_SUBSYSTEM_ID[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SUBSYSTEM_ID[14] | PCIE3:PF0_SUBSYSTEM_ID[15] |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SUBSYSTEM_ID[12] | PCIE3:PF0_SUBSYSTEM_ID[13] |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SUBSYSTEM_ID[10] | PCIE3:PF0_SUBSYSTEM_ID[11] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SUBSYSTEM_ID[8] | PCIE3:PF0_SUBSYSTEM_ID[9] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SUBSYSTEM_ID[6] | PCIE3:PF0_SUBSYSTEM_ID[7] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SUBSYSTEM_ID[4] | PCIE3:PF0_SUBSYSTEM_ID[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SUBSYSTEM_ID[2] | PCIE3:PF0_SUBSYSTEM_ID[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SUBSYSTEM_ID[0] | PCIE3:PF0_SUBSYSTEM_ID[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_CLASS_CODE[22] | PCIE3:PF1_CLASS_CODE[23] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_CLASS_CODE[20] | PCIE3:PF1_CLASS_CODE[21] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_CLASS_CODE[18] | PCIE3:PF1_CLASS_CODE[19] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_CLASS_CODE[16] | PCIE3:PF1_CLASS_CODE[17] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_CLASS_CODE[14] | PCIE3:PF1_CLASS_CODE[15] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_CLASS_CODE[12] | PCIE3:PF1_CLASS_CODE[13] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_CLASS_CODE[10] | PCIE3:PF1_CLASS_CODE[11] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_CLASS_CODE[8] | PCIE3:PF1_CLASS_CODE[9] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_CLASS_CODE[6] | PCIE3:PF1_CLASS_CODE[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_CLASS_CODE[4] | PCIE3:PF1_CLASS_CODE[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_CLASS_CODE[2] | PCIE3:PF1_CLASS_CODE[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_CLASS_CODE[0] | PCIE3:PF1_CLASS_CODE[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_CLASS_CODE[22] | PCIE3:PF0_CLASS_CODE[23] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_CLASS_CODE[20] | PCIE3:PF0_CLASS_CODE[21] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_CLASS_CODE[18] | PCIE3:PF0_CLASS_CODE[19] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_CLASS_CODE[16] | PCIE3:PF0_CLASS_CODE[17] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR2_APERTURE_SIZE[3] | PCIE3:PF1_BAR2_APERTURE_SIZE[4] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR2_APERTURE_SIZE[1] | PCIE3:PF1_BAR2_APERTURE_SIZE[2] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR2_APERTURE_SIZE[4] | PCIE3:PF1_BAR2_APERTURE_SIZE[0] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR2_APERTURE_SIZE[2] | PCIE3:PF0_BAR2_APERTURE_SIZE[3] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR2_APERTURE_SIZE[0] | PCIE3:PF0_BAR2_APERTURE_SIZE[1] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR2_CONTROL[1] | PCIE3:PF1_BAR2_CONTROL[2] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR2_CONTROL[2] | PCIE3:PF1_BAR2_CONTROL[0] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR2_CONTROL[0] | PCIE3:PF0_BAR2_CONTROL[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR1_APERTURE_SIZE[3] | PCIE3:PF1_BAR1_APERTURE_SIZE[4] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR1_APERTURE_SIZE[1] | PCIE3:PF1_BAR1_APERTURE_SIZE[2] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR1_APERTURE_SIZE[4] | PCIE3:PF1_BAR1_APERTURE_SIZE[0] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR1_APERTURE_SIZE[2] | PCIE3:PF0_BAR1_APERTURE_SIZE[3] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR1_APERTURE_SIZE[0] | PCIE3:PF0_BAR1_APERTURE_SIZE[1] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR1_CONTROL[1] | PCIE3:PF1_BAR1_CONTROL[2] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR1_CONTROL[2] | PCIE3:PF1_BAR1_CONTROL[0] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR1_CONTROL[0] | PCIE3:PF0_BAR1_CONTROL[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR0_APERTURE_SIZE[3] | PCIE3:PF1_BAR0_APERTURE_SIZE[4] |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR0_APERTURE_SIZE[1] | PCIE3:PF1_BAR0_APERTURE_SIZE[2] |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR0_APERTURE_SIZE[4] | PCIE3:PF1_BAR0_APERTURE_SIZE[0] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR0_APERTURE_SIZE[2] | PCIE3:PF0_BAR0_APERTURE_SIZE[3] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR0_APERTURE_SIZE[0] | PCIE3:PF0_BAR0_APERTURE_SIZE[1] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR0_CONTROL[1] | PCIE3:PF1_BAR0_CONTROL[2] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR0_CONTROL[2] | PCIE3:PF1_BAR0_CONTROL[0] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR0_CONTROL[0] | PCIE3:PF0_BAR0_CONTROL[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_CAPABILITY_POINTER[6] | PCIE3:VF0_CAPABILITY_POINTER[7] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_CAPABILITY_POINTER[4] | PCIE3:VF0_CAPABILITY_POINTER[5] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_CAPABILITY_POINTER[2] | PCIE3:VF0_CAPABILITY_POINTER[3] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_CAPABILITY_POINTER[0] | PCIE3:VF0_CAPABILITY_POINTER[1] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_CAPABILITY_POINTER[6] | PCIE3:PF1_CAPABILITY_POINTER[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_CAPABILITY_POINTER[4] | PCIE3:PF1_CAPABILITY_POINTER[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_CAPABILITY_POINTER[2] | PCIE3:PF1_CAPABILITY_POINTER[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_CAPABILITY_POINTER[0] | PCIE3:PF1_CAPABILITY_POINTER[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_CAPABILITY_POINTER[6] | PCIE3:PF0_CAPABILITY_POINTER[7] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_CAPABILITY_POINTER[4] | PCIE3:PF0_CAPABILITY_POINTER[5] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_CAPABILITY_POINTER[2] | PCIE3:PF0_CAPABILITY_POINTER[3] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_CAPABILITY_POINTER[0] | PCIE3:PF0_CAPABILITY_POINTER[1] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BIST_REGISTER[6] | PCIE3:PF1_BIST_REGISTER[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BIST_REGISTER[4] | PCIE3:PF1_BIST_REGISTER[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BIST_REGISTER[2] | PCIE3:PF1_BIST_REGISTER[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BIST_REGISTER[0] | PCIE3:PF1_BIST_REGISTER[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BIST_REGISTER[6] | PCIE3:PF0_BIST_REGISTER[7] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BIST_REGISTER[4] | PCIE3:PF0_BIST_REGISTER[5] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BIST_REGISTER[2] | PCIE3:PF0_BIST_REGISTER[3] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BIST_REGISTER[0] | PCIE3:PF0_BIST_REGISTER[1] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_INTERRUPT_LINE[6] | PCIE3:PF1_INTERRUPT_LINE[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_INTERRUPT_LINE[4] | PCIE3:PF1_INTERRUPT_LINE[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_INTERRUPT_LINE[2] | PCIE3:PF1_INTERRUPT_LINE[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_INTERRUPT_LINE[0] | PCIE3:PF1_INTERRUPT_LINE[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DEV_CAP_ENDPOINT_L1_LATENCY[1] | PCIE3:PF0_DEV_CAP_ENDPOINT_L1_LATENCY[2] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DEV_CAP_ENDPOINT_L0S_LATENCY[2] | PCIE3:PF0_DEV_CAP_ENDPOINT_L1_LATENCY[0] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DEV_CAP_ENDPOINT_L0S_LATENCY[0] | PCIE3:PF0_DEV_CAP_ENDPOINT_L0S_LATENCY[1] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_DEV_CAP_MAX_PAYLOAD_SIZE[2] | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_DEV_CAP_MAX_PAYLOAD_SIZE[0] | PCIE3:PF1_DEV_CAP_MAX_PAYLOAD_SIZE[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DEV_CAP_MAX_PAYLOAD_SIZE[2] | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DEV_CAP_MAX_PAYLOAD_SIZE[0] | PCIE3:PF0_DEV_CAP_MAX_PAYLOAD_SIZE[1] |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_EXPANSION_ROM_APERTURE_SIZE[3] | PCIE3:PF1_EXPANSION_ROM_APERTURE_SIZE[4] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_EXPANSION_ROM_APERTURE_SIZE[1] | PCIE3:PF1_EXPANSION_ROM_APERTURE_SIZE[2] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_EXPANSION_ROM_APERTURE_SIZE[4] | PCIE3:PF1_EXPANSION_ROM_APERTURE_SIZE[0] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_EXPANSION_ROM_APERTURE_SIZE[2] | PCIE3:PF0_EXPANSION_ROM_APERTURE_SIZE[3] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_EXPANSION_ROM_APERTURE_SIZE[0] | PCIE3:PF0_EXPANSION_ROM_APERTURE_SIZE[1] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR5_APERTURE_SIZE[3] | PCIE3:PF1_BAR5_APERTURE_SIZE[4] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR5_APERTURE_SIZE[1] | PCIE3:PF1_BAR5_APERTURE_SIZE[2] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR5_APERTURE_SIZE[4] | PCIE3:PF1_BAR5_APERTURE_SIZE[0] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR5_APERTURE_SIZE[2] | PCIE3:PF0_BAR5_APERTURE_SIZE[3] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR5_APERTURE_SIZE[0] | PCIE3:PF0_BAR5_APERTURE_SIZE[1] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR5_CONTROL[1] | PCIE3:PF1_BAR5_CONTROL[2] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR5_CONTROL[2] | PCIE3:PF1_BAR5_CONTROL[0] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR5_CONTROL[0] | PCIE3:PF0_BAR5_CONTROL[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR4_APERTURE_SIZE[3] | PCIE3:PF1_BAR4_APERTURE_SIZE[4] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR4_APERTURE_SIZE[1] | PCIE3:PF1_BAR4_APERTURE_SIZE[2] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR4_APERTURE_SIZE[4] | PCIE3:PF1_BAR4_APERTURE_SIZE[0] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR4_APERTURE_SIZE[2] | PCIE3:PF0_BAR4_APERTURE_SIZE[3] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR4_APERTURE_SIZE[0] | PCIE3:PF0_BAR4_APERTURE_SIZE[1] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR4_CONTROL[1] | PCIE3:PF1_BAR4_CONTROL[2] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR4_CONTROL[2] | PCIE3:PF1_BAR4_CONTROL[0] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR4_CONTROL[0] | PCIE3:PF0_BAR4_CONTROL[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR3_APERTURE_SIZE[3] | PCIE3:PF1_BAR3_APERTURE_SIZE[4] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR3_APERTURE_SIZE[1] | PCIE3:PF1_BAR3_APERTURE_SIZE[2] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR3_APERTURE_SIZE[4] | PCIE3:PF1_BAR3_APERTURE_SIZE[0] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR3_APERTURE_SIZE[2] | PCIE3:PF0_BAR3_APERTURE_SIZE[3] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR3_APERTURE_SIZE[0] | PCIE3:PF0_BAR3_APERTURE_SIZE[1] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_BAR3_CONTROL[1] | PCIE3:PF1_BAR3_CONTROL[2] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR3_CONTROL[2] | PCIE3:PF1_BAR3_CONTROL[0] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_BAR3_CONTROL[0] | PCIE3:PF0_BAR3_CONTROL[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_NEXTPTR[6] | PCIE3:PF1_MSIX_CAP_NEXTPTR[7] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_NEXTPTR[4] | PCIE3:PF1_MSIX_CAP_NEXTPTR[5] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_NEXTPTR[2] | PCIE3:PF1_MSIX_CAP_NEXTPTR[3] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_NEXTPTR[0] | PCIE3:PF1_MSIX_CAP_NEXTPTR[1] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_NEXTPTR[6] | PCIE3:PF0_MSIX_CAP_NEXTPTR[7] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_NEXTPTR[4] | PCIE3:PF0_MSIX_CAP_NEXTPTR[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_NEXTPTR[2] | PCIE3:PF0_MSIX_CAP_NEXTPTR[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_NEXTPTR[0] | PCIE3:PF0_MSIX_CAP_NEXTPTR[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSI_CAP_NEXTPTR[6] | PCIE3:PF1_MSI_CAP_NEXTPTR[7] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSI_CAP_NEXTPTR[4] | PCIE3:PF1_MSI_CAP_NEXTPTR[5] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSI_CAP_NEXTPTR[2] | PCIE3:PF1_MSI_CAP_NEXTPTR[3] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSI_CAP_NEXTPTR[0] | PCIE3:PF1_MSI_CAP_NEXTPTR[1] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSI_CAP_NEXTPTR[6] | PCIE3:PF0_MSI_CAP_NEXTPTR[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSI_CAP_NEXTPTR[4] | PCIE3:PF0_MSI_CAP_NEXTPTR[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSI_CAP_NEXTPTR[2] | PCIE3:PF0_MSI_CAP_NEXTPTR[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSI_CAP_NEXTPTR[0] | PCIE3:PF0_MSI_CAP_NEXTPTR[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DEV_CAP2_OBFF_SUPPORT[0] | PCIE3:PF0_DEV_CAP2_OBFF_SUPPORT[1] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[28] | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[26] | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[27] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[24] | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[25] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[22] | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[23] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[20] | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[21] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[18] | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[19] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[16] | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[17] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[14] | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[15] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[12] | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[13] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[10] | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[8] | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[6] | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[4] | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[2] | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[0] | PCIE3:PF1_MSIX_CAP_PBA_OFFSET[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[28] | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[26] | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[27] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[24] | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[25] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[22] | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[23] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[20] | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[21] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[18] | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[19] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[16] | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[17] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[14] | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[15] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[12] | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[13] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[10] | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[8] | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[6] | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[4] | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[2] | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[0] | PCIE3:PF0_MSIX_CAP_PBA_OFFSET[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[28] | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[26] | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[27] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[24] | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[25] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[22] | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[23] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[20] | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[21] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[18] | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[19] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[16] | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[17] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[14] | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[15] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[12] | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[13] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[10] | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[8] | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[6] | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[4] | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[2] | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[0] | PCIE3:VF2_MSIX_CAP_PBA_OFFSET[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[28] | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[26] | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[27] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[24] | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[25] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[22] | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[23] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[20] | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[21] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[18] | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[19] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[16] | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[17] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[14] | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[15] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[12] | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[13] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[10] | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[8] | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[6] | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[4] | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[2] | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[0] | PCIE3:VF1_MSIX_CAP_PBA_OFFSET[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[28] | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[26] | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[27] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[24] | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[25] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[22] | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[23] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[20] | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[21] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[18] | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[19] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[16] | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[17] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[14] | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[15] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[12] | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[13] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[10] | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[8] | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[6] | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[4] | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[2] | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[0] | PCIE3:VF0_MSIX_CAP_PBA_OFFSET[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[28] | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[26] | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[27] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[24] | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[25] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[22] | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[23] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[20] | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[21] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[18] | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[19] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[16] | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[17] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[14] | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[15] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[12] | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[13] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[10] | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[8] | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[6] | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[4] | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[2] | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[0] | PCIE3:VF5_MSIX_CAP_PBA_OFFSET[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[28] | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[26] | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[27] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[24] | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[25] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[22] | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[23] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[20] | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[21] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[18] | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[19] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[16] | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[17] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[14] | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[15] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[12] | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[13] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[10] | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[8] | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[6] | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[4] | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[2] | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[0] | PCIE3:VF4_MSIX_CAP_PBA_OFFSET[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[28] | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[26] | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[27] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[24] | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[25] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[22] | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[23] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[20] | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[21] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[18] | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[19] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[16] | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[17] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[14] | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[15] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[12] | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[13] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[10] | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[8] | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[6] | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[4] | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[2] | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[0] | PCIE3:VF3_MSIX_CAP_PBA_OFFSET[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[28] | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[26] | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[27] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[24] | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[25] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[22] | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[23] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[20] | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[21] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[18] | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[19] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[16] | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[17] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[14] | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[15] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[12] | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[13] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[10] | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[8] | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[6] | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[4] | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[2] | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[0] | PCIE3:PF1_MSIX_CAP_TABLE_OFFSET[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[28] | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[26] | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[27] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[24] | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[25] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[22] | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[23] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[20] | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[21] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[18] | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[19] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[16] | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[17] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[14] | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[15] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[12] | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[13] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[10] | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[8] | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[6] | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[4] | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[2] | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[0] | PCIE3:PF0_MSIX_CAP_TABLE_OFFSET[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[28] | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[26] | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[27] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[24] | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[25] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[22] | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[23] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[20] | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[21] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[18] | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[19] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[16] | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[17] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[14] | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[15] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[12] | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[13] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[10] | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[8] | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[6] | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[4] | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[2] | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[0] | PCIE3:VF2_MSIX_CAP_TABLE_OFFSET[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[28] | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[26] | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[27] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[24] | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[25] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[22] | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[23] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[20] | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[21] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[18] | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[19] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[16] | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[17] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[14] | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[15] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[12] | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[13] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[10] | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[8] | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[6] | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[4] | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[2] | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[0] | PCIE3:VF1_MSIX_CAP_TABLE_OFFSET[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[28] | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[26] | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[27] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[24] | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[25] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[22] | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[23] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[20] | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[21] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[18] | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[19] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[16] | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[17] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[14] | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[15] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[12] | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[13] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[10] | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[8] | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[6] | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[4] | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[2] | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[0] | PCIE3:VF0_MSIX_CAP_TABLE_OFFSET[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[28] | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[26] | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[27] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[24] | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[25] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[22] | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[23] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[20] | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[21] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[18] | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[19] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[16] | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[17] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[14] | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[15] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[12] | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[13] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[10] | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[8] | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[6] | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[4] | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[2] | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[0] | PCIE3:VF5_MSIX_CAP_TABLE_OFFSET[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[28] | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[26] | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[27] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[24] | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[25] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[22] | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[23] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[20] | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[21] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[18] | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[19] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[16] | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[17] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[14] | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[15] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[12] | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[13] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[10] | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[8] | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[6] | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[4] | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[2] | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[0] | PCIE3:VF4_MSIX_CAP_TABLE_OFFSET[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[28] | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[26] | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[27] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[24] | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[25] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[22] | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[23] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[20] | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[21] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[18] | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[19] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[16] | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[17] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[14] | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[15] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[12] | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[13] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[10] | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[8] | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[6] | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[4] | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[2] | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[0] | PCIE3:VF3_MSIX_CAP_TABLE_OFFSET[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_SIZE[10] | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_SIZE[8] | PCIE3:VF3_MSIX_CAP_TABLE_SIZE[9] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_SIZE[6] | PCIE3:VF3_MSIX_CAP_TABLE_SIZE[7] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_SIZE[4] | PCIE3:VF3_MSIX_CAP_TABLE_SIZE[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_SIZE[2] | PCIE3:VF3_MSIX_CAP_TABLE_SIZE[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_MSIX_CAP_TABLE_SIZE[0] | PCIE3:VF3_MSIX_CAP_TABLE_SIZE[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_SIZE[10] | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_SIZE[8] | PCIE3:VF2_MSIX_CAP_TABLE_SIZE[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_SIZE[6] | PCIE3:VF2_MSIX_CAP_TABLE_SIZE[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_SIZE[4] | PCIE3:VF2_MSIX_CAP_TABLE_SIZE[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_SIZE[2] | PCIE3:VF2_MSIX_CAP_TABLE_SIZE[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_MSIX_CAP_TABLE_SIZE[0] | PCIE3:VF2_MSIX_CAP_TABLE_SIZE[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_SIZE[10] | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_SIZE[8] | PCIE3:VF1_MSIX_CAP_TABLE_SIZE[9] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_SIZE[6] | PCIE3:VF1_MSIX_CAP_TABLE_SIZE[7] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_SIZE[4] | PCIE3:VF1_MSIX_CAP_TABLE_SIZE[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_SIZE[2] | PCIE3:VF1_MSIX_CAP_TABLE_SIZE[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_MSIX_CAP_TABLE_SIZE[0] | PCIE3:VF1_MSIX_CAP_TABLE_SIZE[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_SIZE[10] | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_SIZE[8] | PCIE3:VF0_MSIX_CAP_TABLE_SIZE[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_SIZE[6] | PCIE3:VF0_MSIX_CAP_TABLE_SIZE[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_SIZE[4] | PCIE3:VF0_MSIX_CAP_TABLE_SIZE[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_SIZE[2] | PCIE3:VF0_MSIX_CAP_TABLE_SIZE[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_MSIX_CAP_TABLE_SIZE[0] | PCIE3:VF0_MSIX_CAP_TABLE_SIZE[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_SIZE[10] | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_SIZE[8] | PCIE3:PF1_MSIX_CAP_TABLE_SIZE[9] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_SIZE[6] | PCIE3:PF1_MSIX_CAP_TABLE_SIZE[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_SIZE[4] | PCIE3:PF1_MSIX_CAP_TABLE_SIZE[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_SIZE[2] | PCIE3:PF1_MSIX_CAP_TABLE_SIZE[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_MSIX_CAP_TABLE_SIZE[0] | PCIE3:PF1_MSIX_CAP_TABLE_SIZE[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_SIZE[10] | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_SIZE[8] | PCIE3:PF0_MSIX_CAP_TABLE_SIZE[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_SIZE[6] | PCIE3:PF0_MSIX_CAP_TABLE_SIZE[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_SIZE[4] | PCIE3:PF0_MSIX_CAP_TABLE_SIZE[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_SIZE[2] | PCIE3:PF0_MSIX_CAP_TABLE_SIZE[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_MSIX_CAP_TABLE_SIZE[0] | PCIE3:PF0_MSIX_CAP_TABLE_SIZE[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_PM_CAP_ID[6] | PCIE3:VF5_PM_CAP_ID[7] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_PM_CAP_ID[4] | PCIE3:VF5_PM_CAP_ID[5] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_PM_CAP_ID[2] | PCIE3:VF5_PM_CAP_ID[3] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_PM_CAP_ID[0] | PCIE3:VF5_PM_CAP_ID[1] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_PM_CAP_ID[6] | PCIE3:VF4_PM_CAP_ID[7] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_PM_CAP_ID[4] | PCIE3:VF4_PM_CAP_ID[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_PM_CAP_ID[2] | PCIE3:VF4_PM_CAP_ID[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_PM_CAP_ID[0] | PCIE3:VF4_PM_CAP_ID[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_PM_CAP_ID[6] | PCIE3:VF3_PM_CAP_ID[7] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_PM_CAP_ID[4] | PCIE3:VF3_PM_CAP_ID[5] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_PM_CAP_ID[2] | PCIE3:VF3_PM_CAP_ID[3] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_PM_CAP_ID[0] | PCIE3:VF3_PM_CAP_ID[1] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_PM_CAP_ID[6] | PCIE3:VF2_PM_CAP_ID[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_PM_CAP_ID[4] | PCIE3:VF2_PM_CAP_ID[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_PM_CAP_ID[2] | PCIE3:VF2_PM_CAP_ID[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_PM_CAP_ID[0] | PCIE3:VF2_PM_CAP_ID[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_PM_CAP_ID[6] | PCIE3:VF1_PM_CAP_ID[7] |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_PM_CAP_ID[4] | PCIE3:VF1_PM_CAP_ID[5] |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_PM_CAP_ID[2] | PCIE3:VF1_PM_CAP_ID[3] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_PM_CAP_ID[0] | PCIE3:VF1_PM_CAP_ID[1] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_PM_CAP_ID[6] | PCIE3:VF0_PM_CAP_ID[7] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_PM_CAP_ID[4] | PCIE3:VF0_PM_CAP_ID[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_PM_CAP_ID[2] | PCIE3:VF0_PM_CAP_ID[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_PM_CAP_ID[0] | PCIE3:VF0_PM_CAP_ID[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_PM_CAP_ID[6] | PCIE3:PF1_PM_CAP_ID[7] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_PM_CAP_ID[4] | PCIE3:PF1_PM_CAP_ID[5] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_PM_CAP_ID[2] | PCIE3:PF1_PM_CAP_ID[3] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_PM_CAP_ID[0] | PCIE3:PF1_PM_CAP_ID[1] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PM_CAP_ID[6] | PCIE3:PF0_PM_CAP_ID[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PM_CAP_ID[4] | PCIE3:PF0_PM_CAP_ID[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PM_CAP_ID[2] | PCIE3:PF0_PM_CAP_ID[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PM_CAP_ID[0] | PCIE3:PF0_PM_CAP_ID[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_SIZE[10] | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_SIZE[8] | PCIE3:VF5_MSIX_CAP_TABLE_SIZE[9] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_SIZE[6] | PCIE3:VF5_MSIX_CAP_TABLE_SIZE[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_SIZE[4] | PCIE3:VF5_MSIX_CAP_TABLE_SIZE[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_SIZE[2] | PCIE3:VF5_MSIX_CAP_TABLE_SIZE[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_MSIX_CAP_TABLE_SIZE[0] | PCIE3:VF5_MSIX_CAP_TABLE_SIZE[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_SIZE[10] | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_SIZE[8] | PCIE3:VF4_MSIX_CAP_TABLE_SIZE[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_SIZE[6] | PCIE3:VF4_MSIX_CAP_TABLE_SIZE[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_SIZE[4] | PCIE3:VF4_MSIX_CAP_TABLE_SIZE[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_SIZE[2] | PCIE3:VF4_MSIX_CAP_TABLE_SIZE[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_MSIX_CAP_TABLE_SIZE[0] | PCIE3:VF4_MSIX_CAP_TABLE_SIZE[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_PM_CAP_VER_ID[1] | PCIE3:VF5_PM_CAP_VER_ID[2] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_PM_CAP_VER_ID[2] | PCIE3:VF5_PM_CAP_VER_ID[0] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_PM_CAP_VER_ID[0] | PCIE3:VF4_PM_CAP_VER_ID[1] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_PM_CAP_VER_ID[1] | PCIE3:VF3_PM_CAP_VER_ID[2] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_PM_CAP_VER_ID[2] | PCIE3:VF3_PM_CAP_VER_ID[0] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_PM_CAP_VER_ID[0] | PCIE3:VF2_PM_CAP_VER_ID[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_PM_CAP_VER_ID[1] | PCIE3:VF1_PM_CAP_VER_ID[2] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_PM_CAP_VER_ID[2] | PCIE3:VF1_PM_CAP_VER_ID[0] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_PM_CAP_VER_ID[0] | PCIE3:VF0_PM_CAP_VER_ID[1] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_PM_CAP_VER_ID[1] | PCIE3:PF1_PM_CAP_VER_ID[2] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PM_CAP_VER_ID[2] | PCIE3:PF1_PM_CAP_VER_ID[0] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PM_CAP_VER_ID[0] | PCIE3:PF0_PM_CAP_VER_ID[1] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_PM_CAP_NEXTPTR[6] | PCIE3:VF5_PM_CAP_NEXTPTR[7] |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_PM_CAP_NEXTPTR[4] | PCIE3:VF5_PM_CAP_NEXTPTR[5] |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_PM_CAP_NEXTPTR[2] | PCIE3:VF5_PM_CAP_NEXTPTR[3] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_PM_CAP_NEXTPTR[0] | PCIE3:VF5_PM_CAP_NEXTPTR[1] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_PM_CAP_NEXTPTR[6] | PCIE3:VF4_PM_CAP_NEXTPTR[7] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_PM_CAP_NEXTPTR[4] | PCIE3:VF4_PM_CAP_NEXTPTR[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_PM_CAP_NEXTPTR[2] | PCIE3:VF4_PM_CAP_NEXTPTR[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_PM_CAP_NEXTPTR[0] | PCIE3:VF4_PM_CAP_NEXTPTR[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_PM_CAP_NEXTPTR[6] | PCIE3:VF3_PM_CAP_NEXTPTR[7] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_PM_CAP_NEXTPTR[4] | PCIE3:VF3_PM_CAP_NEXTPTR[5] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_PM_CAP_NEXTPTR[2] | PCIE3:VF3_PM_CAP_NEXTPTR[3] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_PM_CAP_NEXTPTR[0] | PCIE3:VF3_PM_CAP_NEXTPTR[1] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_PM_CAP_NEXTPTR[6] | PCIE3:VF2_PM_CAP_NEXTPTR[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_PM_CAP_NEXTPTR[4] | PCIE3:VF2_PM_CAP_NEXTPTR[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_PM_CAP_NEXTPTR[2] | PCIE3:VF2_PM_CAP_NEXTPTR[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_PM_CAP_NEXTPTR[0] | PCIE3:VF2_PM_CAP_NEXTPTR[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_PM_CAP_NEXTPTR[6] | PCIE3:VF1_PM_CAP_NEXTPTR[7] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_PM_CAP_NEXTPTR[4] | PCIE3:VF1_PM_CAP_NEXTPTR[5] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_PM_CAP_NEXTPTR[2] | PCIE3:VF1_PM_CAP_NEXTPTR[3] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_PM_CAP_NEXTPTR[0] | PCIE3:VF1_PM_CAP_NEXTPTR[1] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_PM_CAP_NEXTPTR[6] | PCIE3:VF0_PM_CAP_NEXTPTR[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_PM_CAP_NEXTPTR[4] | PCIE3:VF0_PM_CAP_NEXTPTR[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_PM_CAP_NEXTPTR[2] | PCIE3:VF0_PM_CAP_NEXTPTR[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_PM_CAP_NEXTPTR[0] | PCIE3:VF0_PM_CAP_NEXTPTR[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_PM_CAP_NEXTPTR[6] | PCIE3:PF1_PM_CAP_NEXTPTR[7] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_PM_CAP_NEXTPTR[4] | PCIE3:PF1_PM_CAP_NEXTPTR[5] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_PM_CAP_NEXTPTR[2] | PCIE3:PF1_PM_CAP_NEXTPTR[3] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_PM_CAP_NEXTPTR[0] | PCIE3:PF1_PM_CAP_NEXTPTR[1] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PM_CAP_NEXTPTR[6] | PCIE3:PF0_PM_CAP_NEXTPTR[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PM_CAP_NEXTPTR[4] | PCIE3:PF0_PM_CAP_NEXTPTR[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PM_CAP_NEXTPTR[2] | PCIE3:PF0_PM_CAP_NEXTPTR[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PM_CAP_NEXTPTR[0] | PCIE3:PF0_PM_CAP_NEXTPTR[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE0[18] | PCIE3:PF0_RBAR_CAP_SIZE0[19] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE0[16] | PCIE3:PF0_RBAR_CAP_SIZE0[17] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE0[14] | PCIE3:PF0_RBAR_CAP_SIZE0[15] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE0[12] | PCIE3:PF0_RBAR_CAP_SIZE0[13] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE0[10] | PCIE3:PF0_RBAR_CAP_SIZE0[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE0[8] | PCIE3:PF0_RBAR_CAP_SIZE0[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE0[6] | PCIE3:PF0_RBAR_CAP_SIZE0[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE0[4] | PCIE3:PF0_RBAR_CAP_SIZE0[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE0[2] | PCIE3:PF0_RBAR_CAP_SIZE0[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE0[0] | PCIE3:PF0_RBAR_CAP_SIZE0[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_INDEX0[2] | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_INDEX0[0] | PCIE3:PF1_RBAR_CAP_INDEX0[1] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_INDEX0[1] | PCIE3:PF0_RBAR_CAP_INDEX0[2] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_NUM[2] | PCIE3:PF0_RBAR_CAP_INDEX0[0] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_NUM[0] | PCIE3:PF1_RBAR_NUM[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_NUM[2] | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_NUM[0] | PCIE3:PF0_RBAR_NUM[1] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_NEXTPTR[10] | PCIE3:PF1_RBAR_CAP_NEXTPTR[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_NEXTPTR[8] | PCIE3:PF1_RBAR_CAP_NEXTPTR[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_NEXTPTR[6] | PCIE3:PF1_RBAR_CAP_NEXTPTR[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_NEXTPTR[4] | PCIE3:PF1_RBAR_CAP_NEXTPTR[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_NEXTPTR[2] | PCIE3:PF1_RBAR_CAP_NEXTPTR[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_NEXTPTR[0] | PCIE3:PF1_RBAR_CAP_NEXTPTR[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_NEXTPTR[10] | PCIE3:PF0_RBAR_CAP_NEXTPTR[11] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_NEXTPTR[8] | PCIE3:PF0_RBAR_CAP_NEXTPTR[9] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_NEXTPTR[6] | PCIE3:PF0_RBAR_CAP_NEXTPTR[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_NEXTPTR[4] | PCIE3:PF0_RBAR_CAP_NEXTPTR[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_NEXTPTR[2] | PCIE3:PF0_RBAR_CAP_NEXTPTR[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_NEXTPTR[0] | PCIE3:PF0_RBAR_CAP_NEXTPTR[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_VER[2] | PCIE3:PF1_RBAR_CAP_VER[3] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_VER[0] | PCIE3:PF1_RBAR_CAP_VER[1] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_VER[2] | PCIE3:PF0_RBAR_CAP_VER[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_VER[0] | PCIE3:PF0_RBAR_CAP_VER[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_INDEX2[1] | PCIE3:PF1_RBAR_CAP_INDEX2[2] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_INDEX2[2] | PCIE3:PF1_RBAR_CAP_INDEX2[0] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_INDEX2[0] | PCIE3:PF0_RBAR_CAP_INDEX2[1] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE1[18] | PCIE3:PF1_RBAR_CAP_SIZE1[19] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE1[16] | PCIE3:PF1_RBAR_CAP_SIZE1[17] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE1[14] | PCIE3:PF1_RBAR_CAP_SIZE1[15] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE1[12] | PCIE3:PF1_RBAR_CAP_SIZE1[13] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE1[10] | PCIE3:PF1_RBAR_CAP_SIZE1[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE1[8] | PCIE3:PF1_RBAR_CAP_SIZE1[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE1[6] | PCIE3:PF1_RBAR_CAP_SIZE1[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE1[4] | PCIE3:PF1_RBAR_CAP_SIZE1[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE1[2] | PCIE3:PF1_RBAR_CAP_SIZE1[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE1[0] | PCIE3:PF1_RBAR_CAP_SIZE1[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE1[18] | PCIE3:PF0_RBAR_CAP_SIZE1[19] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE1[16] | PCIE3:PF0_RBAR_CAP_SIZE1[17] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE1[14] | PCIE3:PF0_RBAR_CAP_SIZE1[15] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE1[12] | PCIE3:PF0_RBAR_CAP_SIZE1[13] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE1[10] | PCIE3:PF0_RBAR_CAP_SIZE1[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE1[8] | PCIE3:PF0_RBAR_CAP_SIZE1[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE1[6] | PCIE3:PF0_RBAR_CAP_SIZE1[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE1[4] | PCIE3:PF0_RBAR_CAP_SIZE1[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE1[2] | PCIE3:PF0_RBAR_CAP_SIZE1[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE1[0] | PCIE3:PF0_RBAR_CAP_SIZE1[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_INDEX1[1] | PCIE3:PF1_RBAR_CAP_INDEX1[2] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_INDEX1[2] | PCIE3:PF1_RBAR_CAP_INDEX1[0] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_INDEX1[0] | PCIE3:PF0_RBAR_CAP_INDEX1[1] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE0[18] | PCIE3:PF1_RBAR_CAP_SIZE0[19] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE0[16] | PCIE3:PF1_RBAR_CAP_SIZE0[17] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE0[14] | PCIE3:PF1_RBAR_CAP_SIZE0[15] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE0[12] | PCIE3:PF1_RBAR_CAP_SIZE0[13] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE0[10] | PCIE3:PF1_RBAR_CAP_SIZE0[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE0[8] | PCIE3:PF1_RBAR_CAP_SIZE0[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE0[6] | PCIE3:PF1_RBAR_CAP_SIZE0[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE0[4] | PCIE3:PF1_RBAR_CAP_SIZE0[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE0[2] | PCIE3:PF1_RBAR_CAP_SIZE0[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE0[0] | PCIE3:PF1_RBAR_CAP_SIZE0[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_VC_CAP_VER[2] | PCIE3:PF0_VC_CAP_VER[3] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_VC_CAP_VER[0] | PCIE3:PF0_VC_CAP_VER[1] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_DSN_CAP_NEXTPTR[10] | PCIE3:PF1_DSN_CAP_NEXTPTR[11] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_DSN_CAP_NEXTPTR[8] | PCIE3:PF1_DSN_CAP_NEXTPTR[9] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_DSN_CAP_NEXTPTR[6] | PCIE3:PF1_DSN_CAP_NEXTPTR[7] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_DSN_CAP_NEXTPTR[4] | PCIE3:PF1_DSN_CAP_NEXTPTR[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_DSN_CAP_NEXTPTR[2] | PCIE3:PF1_DSN_CAP_NEXTPTR[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_DSN_CAP_NEXTPTR[0] | PCIE3:PF1_DSN_CAP_NEXTPTR[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DSN_CAP_NEXTPTR[10] | PCIE3:PF0_DSN_CAP_NEXTPTR[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DSN_CAP_NEXTPTR[8] | PCIE3:PF0_DSN_CAP_NEXTPTR[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DSN_CAP_NEXTPTR[6] | PCIE3:PF0_DSN_CAP_NEXTPTR[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DSN_CAP_NEXTPTR[4] | PCIE3:PF0_DSN_CAP_NEXTPTR[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DSN_CAP_NEXTPTR[2] | PCIE3:PF0_DSN_CAP_NEXTPTR[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_DSN_CAP_NEXTPTR[0] | PCIE3:PF0_DSN_CAP_NEXTPTR[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:DNSTREAM_LINK_NUM[6] | PCIE3:DNSTREAM_LINK_NUM[7] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:DNSTREAM_LINK_NUM[4] | PCIE3:DNSTREAM_LINK_NUM[5] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:DNSTREAM_LINK_NUM[2] | PCIE3:DNSTREAM_LINK_NUM[3] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:DNSTREAM_LINK_NUM[0] | PCIE3:DNSTREAM_LINK_NUM[1] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE2[18] | PCIE3:PF1_RBAR_CAP_SIZE2[19] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE2[16] | PCIE3:PF1_RBAR_CAP_SIZE2[17] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE2[14] | PCIE3:PF1_RBAR_CAP_SIZE2[15] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE2[12] | PCIE3:PF1_RBAR_CAP_SIZE2[13] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE2[10] | PCIE3:PF1_RBAR_CAP_SIZE2[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE2[8] | PCIE3:PF1_RBAR_CAP_SIZE2[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE2[6] | PCIE3:PF1_RBAR_CAP_SIZE2[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE2[4] | PCIE3:PF1_RBAR_CAP_SIZE2[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE2[2] | PCIE3:PF1_RBAR_CAP_SIZE2[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_RBAR_CAP_SIZE2[0] | PCIE3:PF1_RBAR_CAP_SIZE2[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE2[18] | PCIE3:PF0_RBAR_CAP_SIZE2[19] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE2[16] | PCIE3:PF0_RBAR_CAP_SIZE2[17] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE2[14] | PCIE3:PF0_RBAR_CAP_SIZE2[15] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE2[12] | PCIE3:PF0_RBAR_CAP_SIZE2[13] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE2[10] | PCIE3:PF0_RBAR_CAP_SIZE2[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE2[8] | PCIE3:PF0_RBAR_CAP_SIZE2[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE2[6] | PCIE3:PF0_RBAR_CAP_SIZE2[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE2[4] | PCIE3:PF0_RBAR_CAP_SIZE2[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE2[2] | PCIE3:PF0_RBAR_CAP_SIZE2[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_RBAR_CAP_SIZE2[0] | PCIE3:PF0_RBAR_CAP_SIZE2[1] |
| Bit | Frame |
|---|
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_ARI_CAP_NEXTPTR[10] | PCIE3:VF0_ARI_CAP_NEXTPTR[11] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_ARI_CAP_NEXTPTR[8] | PCIE3:VF0_ARI_CAP_NEXTPTR[9] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_ARI_CAP_NEXTPTR[6] | PCIE3:VF0_ARI_CAP_NEXTPTR[7] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_ARI_CAP_NEXTPTR[4] | PCIE3:VF0_ARI_CAP_NEXTPTR[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_ARI_CAP_NEXTPTR[2] | PCIE3:VF0_ARI_CAP_NEXTPTR[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_ARI_CAP_NEXTPTR[0] | PCIE3:VF0_ARI_CAP_NEXTPTR[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_ARI_CAP_NEXTPTR[10] | PCIE3:PF1_ARI_CAP_NEXTPTR[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_ARI_CAP_NEXTPTR[8] | PCIE3:PF1_ARI_CAP_NEXTPTR[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_ARI_CAP_NEXTPTR[6] | PCIE3:PF1_ARI_CAP_NEXTPTR[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_ARI_CAP_NEXTPTR[4] | PCIE3:PF1_ARI_CAP_NEXTPTR[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_ARI_CAP_NEXTPTR[2] | PCIE3:PF1_ARI_CAP_NEXTPTR[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_ARI_CAP_NEXTPTR[0] | PCIE3:PF1_ARI_CAP_NEXTPTR[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_ARI_CAP_NEXTPTR[11] | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_ARI_CAP_NEXTPTR[9] | PCIE3:PF0_ARI_CAP_NEXTPTR[10] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_ARI_CAP_NEXTPTR[7] | PCIE3:PF0_ARI_CAP_NEXTPTR[8] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_ARI_CAP_NEXTPTR[5] | PCIE3:PF0_ARI_CAP_NEXTPTR[6] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_ARI_CAP_NEXTPTR[3] | PCIE3:PF0_ARI_CAP_NEXTPTR[4] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_ARI_CAP_NEXTPTR[1] | PCIE3:PF0_ARI_CAP_NEXTPTR[2] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:ARI_CAP_ENABLE | PCIE3:PF0_ARI_CAP_NEXTPTR[0] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_AER_CAP_ECRC_GEN_CAPABLE | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_AER_CAP_ECRC_CHECK_CAPABLE | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_AER_CAP_NEXTPTR[10] | PCIE3:PF1_AER_CAP_NEXTPTR[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_AER_CAP_NEXTPTR[8] | PCIE3:PF1_AER_CAP_NEXTPTR[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_AER_CAP_NEXTPTR[6] | PCIE3:PF1_AER_CAP_NEXTPTR[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_AER_CAP_NEXTPTR[4] | PCIE3:PF1_AER_CAP_NEXTPTR[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_AER_CAP_NEXTPTR[2] | PCIE3:PF1_AER_CAP_NEXTPTR[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_AER_CAP_NEXTPTR[0] | PCIE3:PF1_AER_CAP_NEXTPTR[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_AER_CAP_NEXTPTR[10] | PCIE3:PF0_AER_CAP_NEXTPTR[11] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_AER_CAP_NEXTPTR[8] | PCIE3:PF0_AER_CAP_NEXTPTR[9] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_AER_CAP_NEXTPTR[6] | PCIE3:PF0_AER_CAP_NEXTPTR[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_AER_CAP_NEXTPTR[4] | PCIE3:PF0_AER_CAP_NEXTPTR[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_AER_CAP_NEXTPTR[2] | PCIE3:PF0_AER_CAP_NEXTPTR[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_AER_CAP_NEXTPTR[0] | PCIE3:PF0_AER_CAP_NEXTPTR[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_VC_CAP_NEXTPTR[10] | PCIE3:PF0_VC_CAP_NEXTPTR[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_VC_CAP_NEXTPTR[8] | PCIE3:PF0_VC_CAP_NEXTPTR[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_VC_CAP_NEXTPTR[6] | PCIE3:PF0_VC_CAP_NEXTPTR[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_VC_CAP_NEXTPTR[4] | PCIE3:PF0_VC_CAP_NEXTPTR[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_VC_CAP_NEXTPTR[2] | PCIE3:PF0_VC_CAP_NEXTPTR[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_VC_CAP_NEXTPTR[0] | PCIE3:PF0_VC_CAP_NEXTPTR[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_ARI_CAP_NEXT_FUNC[6] | PCIE3:PF1_ARI_CAP_NEXT_FUNC[7] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_ARI_CAP_NEXT_FUNC[4] | PCIE3:PF1_ARI_CAP_NEXT_FUNC[5] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_ARI_CAP_NEXT_FUNC[2] | PCIE3:PF1_ARI_CAP_NEXT_FUNC[3] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_ARI_CAP_NEXT_FUNC[0] | PCIE3:PF1_ARI_CAP_NEXT_FUNC[1] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_ARI_CAP_NEXT_FUNC[6] | PCIE3:PF0_ARI_CAP_NEXT_FUNC[7] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_ARI_CAP_NEXT_FUNC[4] | PCIE3:PF0_ARI_CAP_NEXT_FUNC[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_ARI_CAP_NEXT_FUNC[2] | PCIE3:PF0_ARI_CAP_NEXT_FUNC[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_ARI_CAP_NEXT_FUNC[0] | PCIE3:PF0_ARI_CAP_NEXT_FUNC[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_ARI_CAP_VER[2] | PCIE3:PF0_ARI_CAP_VER[3] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_ARI_CAP_VER[0] | PCIE3:PF0_ARI_CAP_VER[1] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_ARI_CAP_NEXTPTR[10] | PCIE3:VF5_ARI_CAP_NEXTPTR[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_ARI_CAP_NEXTPTR[8] | PCIE3:VF5_ARI_CAP_NEXTPTR[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_ARI_CAP_NEXTPTR[6] | PCIE3:VF5_ARI_CAP_NEXTPTR[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_ARI_CAP_NEXTPTR[4] | PCIE3:VF5_ARI_CAP_NEXTPTR[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_ARI_CAP_NEXTPTR[2] | PCIE3:VF5_ARI_CAP_NEXTPTR[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_ARI_CAP_NEXTPTR[0] | PCIE3:VF5_ARI_CAP_NEXTPTR[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_ARI_CAP_NEXTPTR[10] | PCIE3:VF4_ARI_CAP_NEXTPTR[11] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_ARI_CAP_NEXTPTR[8] | PCIE3:VF4_ARI_CAP_NEXTPTR[9] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_ARI_CAP_NEXTPTR[6] | PCIE3:VF4_ARI_CAP_NEXTPTR[7] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_ARI_CAP_NEXTPTR[4] | PCIE3:VF4_ARI_CAP_NEXTPTR[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_ARI_CAP_NEXTPTR[2] | PCIE3:VF4_ARI_CAP_NEXTPTR[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_ARI_CAP_NEXTPTR[0] | PCIE3:VF4_ARI_CAP_NEXTPTR[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_ARI_CAP_NEXTPTR[10] | PCIE3:VF3_ARI_CAP_NEXTPTR[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_ARI_CAP_NEXTPTR[8] | PCIE3:VF3_ARI_CAP_NEXTPTR[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_ARI_CAP_NEXTPTR[6] | PCIE3:VF3_ARI_CAP_NEXTPTR[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_ARI_CAP_NEXTPTR[4] | PCIE3:VF3_ARI_CAP_NEXTPTR[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_ARI_CAP_NEXTPTR[2] | PCIE3:VF3_ARI_CAP_NEXTPTR[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_ARI_CAP_NEXTPTR[0] | PCIE3:VF3_ARI_CAP_NEXTPTR[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_ARI_CAP_NEXTPTR[10] | PCIE3:VF2_ARI_CAP_NEXTPTR[11] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_ARI_CAP_NEXTPTR[8] | PCIE3:VF2_ARI_CAP_NEXTPTR[9] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_ARI_CAP_NEXTPTR[6] | PCIE3:VF2_ARI_CAP_NEXTPTR[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_ARI_CAP_NEXTPTR[4] | PCIE3:VF2_ARI_CAP_NEXTPTR[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_ARI_CAP_NEXTPTR[2] | PCIE3:VF2_ARI_CAP_NEXTPTR[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_ARI_CAP_NEXTPTR[0] | PCIE3:VF2_ARI_CAP_NEXTPTR[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_ARI_CAP_NEXTPTR[10] | PCIE3:VF1_ARI_CAP_NEXTPTR[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_ARI_CAP_NEXTPTR[8] | PCIE3:VF1_ARI_CAP_NEXTPTR[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_ARI_CAP_NEXTPTR[6] | PCIE3:VF1_ARI_CAP_NEXTPTR[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_ARI_CAP_NEXTPTR[4] | PCIE3:VF1_ARI_CAP_NEXTPTR[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_ARI_CAP_NEXTPTR[2] | PCIE3:VF1_ARI_CAP_NEXTPTR[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_ARI_CAP_NEXTPTR[0] | PCIE3:VF1_ARI_CAP_NEXTPTR[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:LTR_TX_MESSAGE_ON_LTR_ENABLE | PCIE3:LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[8] | PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[9] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[6] | PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[7] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[4] | PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[2] | PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[0] | PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[8] | PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[6] | PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[4] | PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[2] | PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[0] | PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_VER[2] | PCIE3:PF0_LTR_CAP_VER[3] |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_VER[0] | PCIE3:PF0_LTR_CAP_VER[1] |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_NEXTPTR[10] | PCIE3:PF0_LTR_CAP_NEXTPTR[11] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_NEXTPTR[8] | PCIE3:PF0_LTR_CAP_NEXTPTR[9] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_NEXTPTR[6] | PCIE3:PF0_LTR_CAP_NEXTPTR[7] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_NEXTPTR[4] | PCIE3:PF0_LTR_CAP_NEXTPTR[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_NEXTPTR[2] | PCIE3:PF0_LTR_CAP_NEXTPTR[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_LTR_CAP_NEXTPTR[0] | PCIE3:PF0_LTR_CAP_NEXTPTR[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_PB_CAP_VER[2] | PCIE3:PF1_PB_CAP_VER[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_PB_CAP_VER[0] | PCIE3:PF1_PB_CAP_VER[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PB_CAP_VER[2] | PCIE3:PF0_PB_CAP_VER[3] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PB_CAP_VER[0] | PCIE3:PF0_PB_CAP_VER[1] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_PB_CAP_NEXTPTR[10] | PCIE3:PF1_PB_CAP_NEXTPTR[11] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_PB_CAP_NEXTPTR[8] | PCIE3:PF1_PB_CAP_NEXTPTR[9] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_PB_CAP_NEXTPTR[6] | PCIE3:PF1_PB_CAP_NEXTPTR[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_PB_CAP_NEXTPTR[4] | PCIE3:PF1_PB_CAP_NEXTPTR[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_PB_CAP_NEXTPTR[2] | PCIE3:PF1_PB_CAP_NEXTPTR[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_PB_CAP_NEXTPTR[0] | PCIE3:PF1_PB_CAP_NEXTPTR[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PB_CAP_NEXTPTR[10] | PCIE3:PF0_PB_CAP_NEXTPTR[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PB_CAP_NEXTPTR[8] | PCIE3:PF0_PB_CAP_NEXTPTR[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PB_CAP_NEXTPTR[6] | PCIE3:PF0_PB_CAP_NEXTPTR[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PB_CAP_NEXTPTR[4] | PCIE3:PF0_PB_CAP_NEXTPTR[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PB_CAP_NEXTPTR[2] | PCIE3:PF0_PB_CAP_NEXTPTR[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_PB_CAP_NEXTPTR[0] | PCIE3:PF0_PB_CAP_NEXTPTR[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_TOTAL_VF[14] | PCIE3:PF0_SRIOV_CAP_TOTAL_VF[15] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_TOTAL_VF[12] | PCIE3:PF0_SRIOV_CAP_TOTAL_VF[13] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_TOTAL_VF[10] | PCIE3:PF0_SRIOV_CAP_TOTAL_VF[11] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_TOTAL_VF[8] | PCIE3:PF0_SRIOV_CAP_TOTAL_VF[9] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_TOTAL_VF[6] | PCIE3:PF0_SRIOV_CAP_TOTAL_VF[7] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_TOTAL_VF[4] | PCIE3:PF0_SRIOV_CAP_TOTAL_VF[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_TOTAL_VF[2] | PCIE3:PF0_SRIOV_CAP_TOTAL_VF[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_TOTAL_VF[0] | PCIE3:PF0_SRIOV_CAP_TOTAL_VF[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SRIOV_CAP_INITIAL_VF[14] | PCIE3:PF1_SRIOV_CAP_INITIAL_VF[15] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SRIOV_CAP_INITIAL_VF[12] | PCIE3:PF1_SRIOV_CAP_INITIAL_VF[13] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SRIOV_CAP_INITIAL_VF[10] | PCIE3:PF1_SRIOV_CAP_INITIAL_VF[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SRIOV_CAP_INITIAL_VF[8] | PCIE3:PF1_SRIOV_CAP_INITIAL_VF[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SRIOV_CAP_INITIAL_VF[6] | PCIE3:PF1_SRIOV_CAP_INITIAL_VF[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SRIOV_CAP_INITIAL_VF[4] | PCIE3:PF1_SRIOV_CAP_INITIAL_VF[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SRIOV_CAP_INITIAL_VF[2] | PCIE3:PF1_SRIOV_CAP_INITIAL_VF[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SRIOV_CAP_INITIAL_VF[0] | PCIE3:PF1_SRIOV_CAP_INITIAL_VF[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_INITIAL_VF[14] | PCIE3:PF0_SRIOV_CAP_INITIAL_VF[15] |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_INITIAL_VF[12] | PCIE3:PF0_SRIOV_CAP_INITIAL_VF[13] |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_INITIAL_VF[10] | PCIE3:PF0_SRIOV_CAP_INITIAL_VF[11] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_INITIAL_VF[8] | PCIE3:PF0_SRIOV_CAP_INITIAL_VF[9] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_INITIAL_VF[6] | PCIE3:PF0_SRIOV_CAP_INITIAL_VF[7] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_INITIAL_VF[4] | PCIE3:PF0_SRIOV_CAP_INITIAL_VF[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_INITIAL_VF[2] | PCIE3:PF0_SRIOV_CAP_INITIAL_VF[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_INITIAL_VF[0] | PCIE3:PF0_SRIOV_CAP_INITIAL_VF[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SRIOV_CAP_VER[2] | PCIE3:PF1_SRIOV_CAP_VER[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SRIOV_CAP_VER[0] | PCIE3:PF1_SRIOV_CAP_VER[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_VER[2] | PCIE3:PF0_SRIOV_CAP_VER[3] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_VER[0] | PCIE3:PF0_SRIOV_CAP_VER[1] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SRIOV_CAP_NEXTPTR[10] | PCIE3:PF1_SRIOV_CAP_NEXTPTR[11] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SRIOV_CAP_NEXTPTR[8] | PCIE3:PF1_SRIOV_CAP_NEXTPTR[9] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SRIOV_CAP_NEXTPTR[6] | PCIE3:PF1_SRIOV_CAP_NEXTPTR[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SRIOV_CAP_NEXTPTR[4] | PCIE3:PF1_SRIOV_CAP_NEXTPTR[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SRIOV_CAP_NEXTPTR[2] | PCIE3:PF1_SRIOV_CAP_NEXTPTR[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_SRIOV_CAP_NEXTPTR[0] | PCIE3:PF1_SRIOV_CAP_NEXTPTR[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_NEXTPTR[11] | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_NEXTPTR[9] | PCIE3:PF0_SRIOV_CAP_NEXTPTR[10] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_NEXTPTR[7] | PCIE3:PF0_SRIOV_CAP_NEXTPTR[8] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_NEXTPTR[5] | PCIE3:PF0_SRIOV_CAP_NEXTPTR[6] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_NEXTPTR[3] | PCIE3:PF0_SRIOV_CAP_NEXTPTR[4] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_NEXTPTR[1] | PCIE3:PF0_SRIOV_CAP_NEXTPTR[2] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_SRIOV_CAP_NEXTPTR[0] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_TPHR_CAP_NEXTPTR[10] | PCIE3:VF4_TPHR_CAP_NEXTPTR[11] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_TPHR_CAP_NEXTPTR[8] | PCIE3:VF4_TPHR_CAP_NEXTPTR[9] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_TPHR_CAP_NEXTPTR[6] | PCIE3:VF4_TPHR_CAP_NEXTPTR[7] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_TPHR_CAP_NEXTPTR[4] | PCIE3:VF4_TPHR_CAP_NEXTPTR[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_TPHR_CAP_NEXTPTR[2] | PCIE3:VF4_TPHR_CAP_NEXTPTR[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_TPHR_CAP_NEXTPTR[0] | PCIE3:VF4_TPHR_CAP_NEXTPTR[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_TPHR_CAP_NEXTPTR[10] | PCIE3:VF3_TPHR_CAP_NEXTPTR[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_TPHR_CAP_NEXTPTR[8] | PCIE3:VF3_TPHR_CAP_NEXTPTR[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_TPHR_CAP_NEXTPTR[6] | PCIE3:VF3_TPHR_CAP_NEXTPTR[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_TPHR_CAP_NEXTPTR[4] | PCIE3:VF3_TPHR_CAP_NEXTPTR[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_TPHR_CAP_NEXTPTR[2] | PCIE3:VF3_TPHR_CAP_NEXTPTR[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_TPHR_CAP_NEXTPTR[0] | PCIE3:VF3_TPHR_CAP_NEXTPTR[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_TPHR_CAP_NEXTPTR[10] | PCIE3:VF2_TPHR_CAP_NEXTPTR[11] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_TPHR_CAP_NEXTPTR[8] | PCIE3:VF2_TPHR_CAP_NEXTPTR[9] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_TPHR_CAP_NEXTPTR[6] | PCIE3:VF2_TPHR_CAP_NEXTPTR[7] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_TPHR_CAP_NEXTPTR[4] | PCIE3:VF2_TPHR_CAP_NEXTPTR[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_TPHR_CAP_NEXTPTR[2] | PCIE3:VF2_TPHR_CAP_NEXTPTR[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_TPHR_CAP_NEXTPTR[0] | PCIE3:VF2_TPHR_CAP_NEXTPTR[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_TPHR_CAP_NEXTPTR[10] | PCIE3:VF1_TPHR_CAP_NEXTPTR[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_TPHR_CAP_NEXTPTR[8] | PCIE3:VF1_TPHR_CAP_NEXTPTR[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_TPHR_CAP_NEXTPTR[6] | PCIE3:VF1_TPHR_CAP_NEXTPTR[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_TPHR_CAP_NEXTPTR[4] | PCIE3:VF1_TPHR_CAP_NEXTPTR[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_TPHR_CAP_NEXTPTR[2] | PCIE3:VF1_TPHR_CAP_NEXTPTR[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_TPHR_CAP_NEXTPTR[0] | PCIE3:VF1_TPHR_CAP_NEXTPTR[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_TPHR_CAP_NEXTPTR[10] | PCIE3:VF0_TPHR_CAP_NEXTPTR[11] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_TPHR_CAP_NEXTPTR[8] | PCIE3:VF0_TPHR_CAP_NEXTPTR[9] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_TPHR_CAP_NEXTPTR[6] | PCIE3:VF0_TPHR_CAP_NEXTPTR[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_TPHR_CAP_NEXTPTR[4] | PCIE3:VF0_TPHR_CAP_NEXTPTR[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_TPHR_CAP_NEXTPTR[2] | PCIE3:VF0_TPHR_CAP_NEXTPTR[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_TPHR_CAP_NEXTPTR[0] | PCIE3:VF0_TPHR_CAP_NEXTPTR[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_TPHR_CAP_NEXTPTR[10] | PCIE3:PF1_TPHR_CAP_NEXTPTR[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_TPHR_CAP_NEXTPTR[8] | PCIE3:PF1_TPHR_CAP_NEXTPTR[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_TPHR_CAP_NEXTPTR[6] | PCIE3:PF1_TPHR_CAP_NEXTPTR[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_TPHR_CAP_NEXTPTR[4] | PCIE3:PF1_TPHR_CAP_NEXTPTR[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_TPHR_CAP_NEXTPTR[2] | PCIE3:PF1_TPHR_CAP_NEXTPTR[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_TPHR_CAP_NEXTPTR[0] | PCIE3:PF1_TPHR_CAP_NEXTPTR[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[10] | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[8] | PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[9] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[6] | PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[7] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[4] | PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[2] | PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[0] | PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_TPHR_CAP_ST_TABLE_LOC[0] | PCIE3:VF5_TPHR_CAP_ST_TABLE_LOC[1] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_TPHR_CAP_ST_TABLE_LOC[0] | PCIE3:VF4_TPHR_CAP_ST_TABLE_LOC[1] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_TPHR_CAP_ST_TABLE_LOC[0] | PCIE3:VF3_TPHR_CAP_ST_TABLE_LOC[1] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_TPHR_CAP_ST_TABLE_LOC[0] | PCIE3:VF2_TPHR_CAP_ST_TABLE_LOC[1] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_TPHR_CAP_ST_TABLE_LOC[0] | PCIE3:VF1_TPHR_CAP_ST_TABLE_LOC[1] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_TPHR_CAP_ST_TABLE_LOC[0] | PCIE3:VF0_TPHR_CAP_ST_TABLE_LOC[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_TPHR_CAP_ST_TABLE_LOC[0] | PCIE3:PF1_TPHR_CAP_ST_TABLE_LOC[1] |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_TPHR_CAP_ST_TABLE_LOC[0] | PCIE3:PF0_TPHR_CAP_ST_TABLE_LOC[1] |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_TPHR_CAP_VER[2] | PCIE3:VF5_TPHR_CAP_VER[3] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_TPHR_CAP_VER[0] | PCIE3:VF5_TPHR_CAP_VER[1] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_TPHR_CAP_VER[2] | PCIE3:VF4_TPHR_CAP_VER[3] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_TPHR_CAP_VER[0] | PCIE3:VF4_TPHR_CAP_VER[1] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_TPHR_CAP_VER[2] | PCIE3:VF3_TPHR_CAP_VER[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_TPHR_CAP_VER[0] | PCIE3:VF3_TPHR_CAP_VER[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_TPHR_CAP_VER[2] | PCIE3:VF2_TPHR_CAP_VER[3] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_TPHR_CAP_VER[0] | PCIE3:VF2_TPHR_CAP_VER[1] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_TPHR_CAP_VER[2] | PCIE3:VF1_TPHR_CAP_VER[3] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_TPHR_CAP_VER[0] | PCIE3:VF1_TPHR_CAP_VER[1] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_TPHR_CAP_VER[2] | PCIE3:VF0_TPHR_CAP_VER[3] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_TPHR_CAP_VER[0] | PCIE3:VF0_TPHR_CAP_VER[1] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_TPHR_CAP_VER[2] | PCIE3:PF1_TPHR_CAP_VER[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_TPHR_CAP_VER[0] | PCIE3:PF1_TPHR_CAP_VER[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_TPHR_CAP_VER[2] | PCIE3:PF0_TPHR_CAP_VER[3] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_TPHR_CAP_VER[0] | PCIE3:PF0_TPHR_CAP_VER[1] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_TPHR_CAP_NEXTPTR[10] | PCIE3:VF5_TPHR_CAP_NEXTPTR[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_TPHR_CAP_NEXTPTR[8] | PCIE3:VF5_TPHR_CAP_NEXTPTR[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_TPHR_CAP_NEXTPTR[6] | PCIE3:VF5_TPHR_CAP_NEXTPTR[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_TPHR_CAP_NEXTPTR[4] | PCIE3:VF5_TPHR_CAP_NEXTPTR[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_TPHR_CAP_NEXTPTR[2] | PCIE3:VF5_TPHR_CAP_NEXTPTR[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_TPHR_CAP_NEXTPTR[0] | PCIE3:VF5_TPHR_CAP_NEXTPTR[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[10] | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[8] | PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[9] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[6] | PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[7] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[4] | PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[2] | PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[0] | PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[10] | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[8] | PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[6] | PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[4] | PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[2] | PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[0] | PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[10] | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[8] | PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[9] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[6] | PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[7] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[4] | PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[2] | PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[0] | PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[10] | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[8] | PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[6] | PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[4] | PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[2] | PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[0] | PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[10] | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[8] | PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[9] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[6] | PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[4] | PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[2] | PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[0] | PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[10] | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[8] | PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[6] | PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[4] | PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[2] | PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[0] | PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_BYTE3[6] | PCIE3:SPARE_BYTE3[7] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_BYTE3[4] | PCIE3:SPARE_BYTE3[5] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_BYTE3[2] | PCIE3:SPARE_BYTE3[3] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_BYTE3[0] | PCIE3:SPARE_BYTE3[1] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_BYTE2[6] | PCIE3:SPARE_BYTE2[7] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_BYTE2[4] | PCIE3:SPARE_BYTE2[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_BYTE2[2] | PCIE3:SPARE_BYTE2[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_BYTE2[0] | PCIE3:SPARE_BYTE2[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_BYTE1[6] | PCIE3:SPARE_BYTE1[7] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_BYTE1[4] | PCIE3:SPARE_BYTE1[5] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_BYTE1[2] | PCIE3:SPARE_BYTE1[3] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_BYTE1[0] | PCIE3:SPARE_BYTE1[1] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_BYTE0[6] | PCIE3:SPARE_BYTE0[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_BYTE0[4] | PCIE3:SPARE_BYTE0[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_BYTE0[2] | PCIE3:SPARE_BYTE0[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_BYTE0[0] | PCIE3:SPARE_BYTE0[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:GEN3_PCS_RX_ELECIDLE_INTERNAL | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:GEN3_PCS_AUTO_REALIGN[0] | PCIE3:GEN3_PCS_AUTO_REALIGN[1] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_TPHR_CAP_ST_MODE_SEL[1] | PCIE3:VF5_TPHR_CAP_ST_MODE_SEL[2] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_TPHR_CAP_ST_MODE_SEL[2] | PCIE3:VF5_TPHR_CAP_ST_MODE_SEL[0] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF4_TPHR_CAP_ST_MODE_SEL[0] | PCIE3:VF4_TPHR_CAP_ST_MODE_SEL[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_TPHR_CAP_ST_MODE_SEL[2] | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF3_TPHR_CAP_ST_MODE_SEL[0] | PCIE3:VF3_TPHR_CAP_ST_MODE_SEL[1] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF2_TPHR_CAP_ST_MODE_SEL[1] | PCIE3:VF2_TPHR_CAP_ST_MODE_SEL[2] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_TPHR_CAP_ST_MODE_SEL[2] | PCIE3:VF2_TPHR_CAP_ST_MODE_SEL[0] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF1_TPHR_CAP_ST_MODE_SEL[0] | PCIE3:VF1_TPHR_CAP_ST_MODE_SEL[1] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF0_TPHR_CAP_ST_MODE_SEL[1] | PCIE3:VF0_TPHR_CAP_ST_MODE_SEL[2] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_TPHR_CAP_ST_MODE_SEL[2] | PCIE3:VF0_TPHR_CAP_ST_MODE_SEL[0] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF1_TPHR_CAP_ST_MODE_SEL[0] | PCIE3:PF1_TPHR_CAP_ST_MODE_SEL[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:PF0_TPHR_CAP_ST_MODE_SEL[1] | PCIE3:PF0_TPHR_CAP_ST_MODE_SEL[2] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[10] | PCIE3:PF0_TPHR_CAP_ST_MODE_SEL[0] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[8] | PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[6] | PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[4] | PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[2] | PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[0] | PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD2[30] | PCIE3:SPARE_WORD2[31] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD2[28] | PCIE3:SPARE_WORD2[29] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD2[26] | PCIE3:SPARE_WORD2[27] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD2[24] | PCIE3:SPARE_WORD2[25] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD2[22] | PCIE3:SPARE_WORD2[23] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD2[20] | PCIE3:SPARE_WORD2[21] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD2[18] | PCIE3:SPARE_WORD2[19] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD2[16] | PCIE3:SPARE_WORD2[17] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD2[14] | PCIE3:SPARE_WORD2[15] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD2[12] | PCIE3:SPARE_WORD2[13] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD2[10] | PCIE3:SPARE_WORD2[11] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD2[8] | PCIE3:SPARE_WORD2[9] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD2[6] | PCIE3:SPARE_WORD2[7] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD2[4] | PCIE3:SPARE_WORD2[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD2[2] | PCIE3:SPARE_WORD2[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD2[0] | PCIE3:SPARE_WORD2[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD1[30] | PCIE3:SPARE_WORD1[31] |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD1[28] | PCIE3:SPARE_WORD1[29] |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD1[26] | PCIE3:SPARE_WORD1[27] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD1[24] | PCIE3:SPARE_WORD1[25] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD1[22] | PCIE3:SPARE_WORD1[23] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD1[20] | PCIE3:SPARE_WORD1[21] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD1[18] | PCIE3:SPARE_WORD1[19] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD1[16] | PCIE3:SPARE_WORD1[17] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD1[14] | PCIE3:SPARE_WORD1[15] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD1[12] | PCIE3:SPARE_WORD1[13] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD1[10] | PCIE3:SPARE_WORD1[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD1[8] | PCIE3:SPARE_WORD1[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD1[6] | PCIE3:SPARE_WORD1[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD1[4] | PCIE3:SPARE_WORD1[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD1[2] | PCIE3:SPARE_WORD1[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD1[0] | PCIE3:SPARE_WORD1[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD0[30] | PCIE3:SPARE_WORD0[31] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD0[28] | PCIE3:SPARE_WORD0[29] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD0[26] | PCIE3:SPARE_WORD0[27] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD0[24] | PCIE3:SPARE_WORD0[25] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD0[22] | PCIE3:SPARE_WORD0[23] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD0[20] | PCIE3:SPARE_WORD0[21] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD0[18] | PCIE3:SPARE_WORD0[19] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD0[16] | PCIE3:SPARE_WORD0[17] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD0[14] | PCIE3:SPARE_WORD0[15] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD0[12] | PCIE3:SPARE_WORD0[13] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD0[10] | PCIE3:SPARE_WORD0[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD0[8] | PCIE3:SPARE_WORD0[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD0[6] | PCIE3:SPARE_WORD0[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD0[4] | PCIE3:SPARE_WORD0[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD0[2] | PCIE3:SPARE_WORD0[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD0[0] | PCIE3:SPARE_WORD0[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD3[30] | PCIE3:SPARE_WORD3[31] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD3[28] | PCIE3:SPARE_WORD3[29] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD3[26] | PCIE3:SPARE_WORD3[27] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD3[24] | PCIE3:SPARE_WORD3[25] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD3[22] | PCIE3:SPARE_WORD3[23] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD3[20] | PCIE3:SPARE_WORD3[21] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD3[18] | PCIE3:SPARE_WORD3[19] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD3[16] | PCIE3:SPARE_WORD3[17] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD3[14] | PCIE3:SPARE_WORD3[15] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD3[12] | PCIE3:SPARE_WORD3[13] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD3[10] | PCIE3:SPARE_WORD3[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD3[8] | PCIE3:SPARE_WORD3[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD3[6] | PCIE3:SPARE_WORD3[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD3[4] | PCIE3:SPARE_WORD3[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD3[2] | PCIE3:SPARE_WORD3[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE3:SPARE_WORD3[0] | PCIE3:SPARE_WORD3[1] |
| PCIE3:ARI_CAP_ENABLE | 25.F28.B24 |
|---|---|
| PCIE3:AXISTEN_IF_CC_ALIGNMENT_MODE | 0.F28.B3 |
| PCIE3:AXISTEN_IF_CC_PARITY_CHK | 0.F29.B17 |
| PCIE3:AXISTEN_IF_CQ_ALIGNMENT_MODE | 0.F29.B2 |
| PCIE3:AXISTEN_IF_ENABLE_CLIENT_TAG | 0.F28.B18 |
| PCIE3:AXISTEN_IF_ENABLE_RX_MSG_INTFC | 0.F28.B5 |
| PCIE3:AXISTEN_IF_RC_ALIGNMENT_MODE | 0.F28.B4 |
| PCIE3:AXISTEN_IF_RC_STRADDLE | 0.F29.B4 |
| PCIE3:AXISTEN_IF_RQ_ALIGNMENT_MODE | 0.F29.B3 |
| PCIE3:AXISTEN_IF_RQ_PARITY_CHK | 0.F28.B17 |
| PCIE3:CRM_CORE_CLK_FREQ_500 | 0.F28.B0 |
| PCIE3:GEN3_PCS_RX_ELECIDLE_INTERNAL | 37.F28.B24 |
| PCIE3:LL_ACK_TIMEOUT_EN | 4.F28.B6 |
| PCIE3:LL_CPL_FC_UPDATE_TIMER_OVERRIDE | 4.F29.B21 |
| PCIE3:LL_FC_UPDATE_TIMER_OVERRIDE | 5.F28.B16 |
| PCIE3:LL_NP_FC_UPDATE_TIMER_OVERRIDE | 5.F28.B0 |
| PCIE3:LL_P_FC_UPDATE_TIMER_OVERRIDE | 4.F28.B32 |
| PCIE3:LL_REPLAY_TIMEOUT_EN | 4.F29.B13 |
| PCIE3:LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE | 27.F29.B45 |
| PCIE3:LTR_TX_MESSAGE_ON_LTR_ENABLE | 27.F28.B45 |
| PCIE3:PF0_AER_CAP_ECRC_CHECK_CAPABLE | 25.F28.B22 |
| PCIE3:PF0_AER_CAP_ECRC_GEN_CAPABLE | 25.F28.B23 |
| non-inverted | [0] |
| PCIE3:AXISTEN_IF_ENABLE_MSG_ROUTE | 0.F29.B16 | 0.F28.B16 | 0.F29.B15 | 0.F28.B15 | 0.F29.B14 | 0.F28.B14 | 0.F29.B13 | 0.F28.B13 | 0.F29.B12 | 0.F28.B12 | 0.F29.B11 | 0.F28.B11 | 0.F29.B10 | 0.F28.B10 | 0.F29.B9 | 0.F28.B9 | 0.F29.B8 | 0.F28.B8 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| non-inverted | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE3:AXISTEN_IF_WIDTH | 0.F28.B2 | 0.F29.B1 |
|---|---|---|
| PCIE3:CRM_USER_CLK_FREQ | 0.F28.B1 | 0.F29.B0 |
| PCIE3:GEN3_PCS_AUTO_REALIGN | 37.F29.B23 | 37.F28.B23 |
| PCIE3:LL_ACK_TIMEOUT_FUNC | 4.F28.B13 | 4.F29.B12 |
| PCIE3:LL_REPLAY_TIMEOUT_FUNC | 4.F28.B21 | 4.F29.B20 |
| PCIE3:PF0_DEV_CAP2_OBFF_SUPPORT | 11.F29.B14 | 11.F28.B14 |
| PCIE3:PF0_TPHR_CAP_ST_TABLE_LOC | 35.F29.B30 | 35.F28.B30 |
| PCIE3:PF1_TPHR_CAP_ST_TABLE_LOC | 35.F29.B31 | 35.F28.B31 |
| PCIE3:PL_EQ_ADAPT_REJECT_RETRY_COUNT | 4.F29.B3 | 4.F28.B3 |
| PCIE3:VF0_TPHR_CAP_ST_TABLE_LOC | 35.F29.B32 | 35.F28.B32 |
| PCIE3:VF1_TPHR_CAP_ST_TABLE_LOC | 35.F29.B33 | 35.F28.B33 |
| PCIE3:VF2_TPHR_CAP_ST_TABLE_LOC | 35.F29.B34 | 35.F28.B34 |
| PCIE3:VF3_TPHR_CAP_ST_TABLE_LOC | 35.F29.B35 | 35.F28.B35 |
| PCIE3:VF4_TPHR_CAP_ST_TABLE_LOC | 35.F29.B36 | 35.F28.B36 |
| PCIE3:VF5_TPHR_CAP_ST_TABLE_LOC | 35.F29.B37 | 35.F28.B37 |
| non-inverted | [1] | [0] |
| PCIE3:DNSTREAM_LINK_NUM | 23.F29.B29 | 23.F28.B29 | 23.F29.B28 | 23.F28.B28 | 23.F29.B27 | 23.F28.B27 | 23.F29.B26 | 23.F28.B26 |
|---|---|---|---|---|---|---|---|---|
| PCIE3:PF0_ARI_CAP_NEXT_FUNC | 26.F29.B43 | 26.F28.B43 | 26.F29.B42 | 26.F28.B42 | 26.F29.B41 | 26.F28.B41 | 26.F29.B40 | 26.F28.B40 |
| PCIE3:PF0_BIST_REGISTER | 9.F29.B7 | 9.F28.B7 | 9.F29.B6 | 9.F28.B6 | 9.F29.B5 | 9.F28.B5 | 9.F29.B4 | 9.F28.B4 |
| PCIE3:PF0_CAPABILITY_POINTER | 9.F29.B15 | 9.F28.B15 | 9.F29.B14 | 9.F28.B14 | 9.F29.B13 | 9.F28.B13 | 9.F29.B12 | 9.F28.B12 |
| PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 | 28.F29.B35 | 28.F28.B35 | 28.F29.B34 | 28.F28.B34 | 28.F29.B33 | 28.F28.B33 | 28.F29.B32 | 28.F28.B32 |
| PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 | 28.F29.B43 | 28.F28.B43 | 28.F29.B42 | 28.F28.B42 | 28.F29.B41 | 28.F28.B41 | 28.F29.B40 | 28.F28.B40 |
| PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 | 29.F29.B3 | 29.F28.B3 | 29.F29.B2 | 29.F28.B2 | 29.F29.B1 | 29.F28.B1 | 29.F29.B0 | 29.F28.B0 |
| PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 | 29.F29.B11 | 29.F28.B11 | 29.F29.B10 | 29.F28.B10 | 29.F29.B9 | 29.F28.B9 | 29.F29.B8 | 29.F28.B8 |
| PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 | 29.F29.B19 | 29.F28.B19 | 29.F29.B18 | 29.F28.B18 | 29.F29.B17 | 29.F28.B17 | 29.F29.B16 | 29.F28.B16 |
| PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 | 29.F29.B27 | 29.F28.B27 | 29.F29.B26 | 29.F28.B26 | 29.F29.B25 | 29.F28.B25 | 29.F29.B24 | 29.F28.B24 |
| PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 | 29.F29.B35 | 29.F28.B35 | 29.F29.B34 | 29.F28.B34 | 29.F29.B33 | 29.F28.B33 | 29.F29.B32 | 29.F28.B32 |
| PCIE3:PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 | 29.F29.B43 | 29.F28.B43 | 29.F29.B42 | 29.F28.B42 | 29.F29.B41 | 29.F28.B41 | 29.F29.B40 | 29.F28.B40 |
| PCIE3:PF0_INTERRUPT_LINE | 8.F29.B46 | 8.F28.B46 | 8.F29.B45 | 8.F28.B45 | 8.F29.B44 | 8.F28.B44 | 8.F29.B43 | 8.F28.B43 |
| PCIE3:PF0_MSIX_CAP_NEXTPTR | 11.F29.B43 | 11.F28.B43 | 11.F29.B42 | 11.F28.B42 | 11.F29.B41 | 11.F28.B41 | 11.F29.B40 | 11.F28.B40 |
| PCIE3:PF0_MSI_CAP_NEXTPTR | 11.F29.B19 | 11.F28.B19 | 11.F29.B18 | 11.F28.B18 | 11.F29.B17 | 11.F28.B17 | 11.F29.B16 | 11.F28.B16 |
| PCIE3:PF0_PM_CAP_ID | 19.F29.B19 | 19.F28.B19 | 19.F29.B18 | 19.F28.B18 | 19.F29.B17 | 19.F28.B17 | 19.F29.B16 | 19.F28.B16 |
| PCIE3:PF0_PM_CAP_NEXTPTR | 20.F29.B3 | 20.F28.B3 | 20.F29.B2 | 20.F28.B2 | 20.F29.B1 | 20.F28.B1 | 20.F29.B0 | 20.F28.B0 |
| PCIE3:PF0_REVISION_ID | 7.F29.B35 | 7.F28.B35 | 7.F29.B34 | 7.F28.B34 | 7.F29.B33 | 7.F28.B33 | 7.F29.B32 | 7.F28.B32 |
| PCIE3:PF1_ARI_CAP_NEXT_FUNC | 26.F29.B47 | 26.F28.B47 | 26.F29.B46 | 26.F28.B46 | 26.F29.B45 | 26.F28.B45 | 26.F29.B44 | 26.F28.B44 |
| PCIE3:PF1_BIST_REGISTER | 9.F29.B11 | 9.F28.B11 | 9.F29.B10 | 9.F28.B10 | 9.F29.B9 | 9.F28.B9 | 9.F29.B8 | 9.F28.B8 |
| PCIE3:PF1_CAPABILITY_POINTER | 9.F29.B19 | 9.F28.B19 | 9.F29.B18 | 9.F28.B18 | 9.F29.B17 | 9.F28.B17 | 9.F29.B16 | 9.F28.B16 |
| PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 | 28.F29.B39 | 28.F28.B39 | 28.F29.B38 | 28.F28.B38 | 28.F29.B37 | 28.F28.B37 | 28.F29.B36 | 28.F28.B36 |
| PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 | 28.F29.B47 | 28.F28.B47 | 28.F29.B46 | 28.F28.B46 | 28.F29.B45 | 28.F28.B45 | 28.F29.B44 | 28.F28.B44 |
| PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 | 29.F29.B7 | 29.F28.B7 | 29.F29.B6 | 29.F28.B6 | 29.F29.B5 | 29.F28.B5 | 29.F29.B4 | 29.F28.B4 |
| PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 | 29.F29.B15 | 29.F28.B15 | 29.F29.B14 | 29.F28.B14 | 29.F29.B13 | 29.F28.B13 | 29.F29.B12 | 29.F28.B12 |
| PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 | 29.F29.B23 | 29.F28.B23 | 29.F29.B22 | 29.F28.B22 | 29.F29.B21 | 29.F28.B21 | 29.F29.B20 | 29.F28.B20 |
| PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 | 29.F29.B31 | 29.F28.B31 | 29.F29.B30 | 29.F28.B30 | 29.F29.B29 | 29.F28.B29 | 29.F29.B28 | 29.F28.B28 |
| PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 | 29.F29.B39 | 29.F28.B39 | 29.F29.B38 | 29.F28.B38 | 29.F29.B37 | 29.F28.B37 | 29.F29.B36 | 29.F28.B36 |
| PCIE3:PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 | 29.F29.B47 | 29.F28.B47 | 29.F29.B46 | 29.F28.B46 | 29.F29.B45 | 29.F28.B45 | 29.F29.B44 | 29.F28.B44 |
| PCIE3:PF1_INTERRUPT_LINE | 9.F29.B3 | 9.F28.B3 | 9.F29.B2 | 9.F28.B2 | 9.F29.B1 | 9.F28.B1 | 9.F29.B0 | 9.F28.B0 |
| PCIE3:PF1_MSIX_CAP_NEXTPTR | 11.F29.B47 | 11.F28.B47 | 11.F29.B46 | 11.F28.B46 | 11.F29.B45 | 11.F28.B45 | 11.F29.B44 | 11.F28.B44 |
| PCIE3:PF1_MSI_CAP_NEXTPTR | 11.F29.B23 | 11.F28.B23 | 11.F29.B22 | 11.F28.B22 | 11.F29.B21 | 11.F28.B21 | 11.F29.B20 | 11.F28.B20 |
| PCIE3:PF1_PM_CAP_ID | 19.F29.B23 | 19.F28.B23 | 19.F29.B22 | 19.F28.B22 | 19.F29.B21 | 19.F28.B21 | 19.F29.B20 | 19.F28.B20 |
| PCIE3:PF1_PM_CAP_NEXTPTR | 20.F29.B7 | 20.F28.B7 | 20.F29.B6 | 20.F28.B6 | 20.F29.B5 | 20.F28.B5 | 20.F29.B4 | 20.F28.B4 |
| PCIE3:PF1_REVISION_ID | 7.F29.B39 | 7.F28.B39 | 7.F29.B38 | 7.F28.B38 | 7.F29.B37 | 7.F28.B37 | 7.F29.B36 | 7.F28.B36 |
| PCIE3:PL_N_FTS_COMCLK_GEN1 | 2.F29.B3 | 2.F28.B3 | 2.F29.B2 | 2.F28.B2 | 2.F29.B1 | 2.F28.B1 | 2.F29.B0 | 2.F28.B0 |
| PCIE3:PL_N_FTS_COMCLK_GEN2 | 2.F29.B11 | 2.F28.B11 | 2.F29.B10 | 2.F28.B10 | 2.F29.B9 | 2.F28.B9 | 2.F29.B8 | 2.F28.B8 |
| PCIE3:PL_N_FTS_COMCLK_GEN3 | 2.F29.B19 | 2.F28.B19 | 2.F29.B18 | 2.F28.B18 | 2.F29.B17 | 2.F28.B17 | 2.F29.B16 | 2.F28.B16 |
| PCIE3:PL_N_FTS_GEN1 | 2.F29.B7 | 2.F28.B7 | 2.F29.B6 | 2.F28.B6 | 2.F29.B5 | 2.F28.B5 | 2.F29.B4 | 2.F28.B4 |
| PCIE3:PL_N_FTS_GEN2 | 2.F29.B15 | 2.F28.B15 | 2.F29.B14 | 2.F28.B14 | 2.F29.B13 | 2.F28.B13 | 2.F29.B12 | 2.F28.B12 |
| PCIE3:PL_N_FTS_GEN3 | 2.F29.B23 | 2.F28.B23 | 2.F29.B22 | 2.F28.B22 | 2.F29.B21 | 2.F28.B21 | 2.F29.B20 | 2.F28.B20 |
| PCIE3:SPARE_BYTE0 | 37.F29.B35 | 37.F28.B35 | 37.F29.B34 | 37.F28.B34 | 37.F29.B33 | 37.F28.B33 | 37.F29.B32 | 37.F28.B32 |
| PCIE3:SPARE_BYTE1 | 37.F29.B39 | 37.F28.B39 | 37.F29.B38 | 37.F28.B38 | 37.F29.B37 | 37.F28.B37 | 37.F29.B36 | 37.F28.B36 |
| PCIE3:SPARE_BYTE2 | 37.F29.B43 | 37.F28.B43 | 37.F29.B42 | 37.F28.B42 | 37.F29.B41 | 37.F28.B41 | 37.F29.B40 | 37.F28.B40 |
| PCIE3:SPARE_BYTE3 | 37.F29.B47 | 37.F28.B47 | 37.F29.B46 | 37.F28.B46 | 37.F29.B45 | 37.F28.B45 | 37.F29.B44 | 37.F28.B44 |
| PCIE3:TL_CREDITS_CH | 5.F29.B43 | 5.F28.B43 | 5.F29.B42 | 5.F28.B42 | 5.F29.B41 | 5.F28.B41 | 5.F29.B40 | 5.F28.B40 |
| PCIE3:TL_CREDITS_NPH | 6.F29.B11 | 6.F28.B11 | 6.F29.B10 | 6.F28.B10 | 6.F29.B9 | 6.F28.B9 | 6.F29.B8 | 6.F28.B8 |
| PCIE3:TL_CREDITS_PH | 6.F29.B27 | 6.F28.B27 | 6.F29.B26 | 6.F28.B26 | 6.F29.B25 | 6.F28.B25 | 6.F29.B24 | 6.F28.B24 |
| PCIE3:VF0_CAPABILITY_POINTER | 9.F29.B23 | 9.F28.B23 | 9.F29.B22 | 9.F28.B22 | 9.F29.B21 | 9.F28.B21 | 9.F29.B20 | 9.F28.B20 |
| PCIE3:VF0_PM_CAP_ID | 19.F29.B27 | 19.F28.B27 | 19.F29.B26 | 19.F28.B26 | 19.F29.B25 | 19.F28.B25 | 19.F29.B24 | 19.F28.B24 |
| PCIE3:VF0_PM_CAP_NEXTPTR | 20.F29.B11 | 20.F28.B11 | 20.F29.B10 | 20.F28.B10 | 20.F29.B9 | 20.F28.B9 | 20.F29.B8 | 20.F28.B8 |
| PCIE3:VF1_PM_CAP_ID | 19.F29.B31 | 19.F28.B31 | 19.F29.B30 | 19.F28.B30 | 19.F29.B29 | 19.F28.B29 | 19.F29.B28 | 19.F28.B28 |
| PCIE3:VF1_PM_CAP_NEXTPTR | 20.F29.B15 | 20.F28.B15 | 20.F29.B14 | 20.F28.B14 | 20.F29.B13 | 20.F28.B13 | 20.F29.B12 | 20.F28.B12 |
| PCIE3:VF2_PM_CAP_ID | 19.F29.B35 | 19.F28.B35 | 19.F29.B34 | 19.F28.B34 | 19.F29.B33 | 19.F28.B33 | 19.F29.B32 | 19.F28.B32 |
| PCIE3:VF2_PM_CAP_NEXTPTR | 20.F29.B19 | 20.F28.B19 | 20.F29.B18 | 20.F28.B18 | 20.F29.B17 | 20.F28.B17 | 20.F29.B16 | 20.F28.B16 |
| PCIE3:VF3_PM_CAP_ID | 19.F29.B39 | 19.F28.B39 | 19.F29.B38 | 19.F28.B38 | 19.F29.B37 | 19.F28.B37 | 19.F29.B36 | 19.F28.B36 |
| PCIE3:VF3_PM_CAP_NEXTPTR | 20.F29.B23 | 20.F28.B23 | 20.F29.B22 | 20.F28.B22 | 20.F29.B21 | 20.F28.B21 | 20.F29.B20 | 20.F28.B20 |
| PCIE3:VF4_PM_CAP_ID | 19.F29.B43 | 19.F28.B43 | 19.F29.B42 | 19.F28.B42 | 19.F29.B41 | 19.F28.B41 | 19.F29.B40 | 19.F28.B40 |
| PCIE3:VF4_PM_CAP_NEXTPTR | 20.F29.B27 | 20.F28.B27 | 20.F29.B26 | 20.F28.B26 | 20.F29.B25 | 20.F28.B25 | 20.F29.B24 | 20.F28.B24 |
| PCIE3:VF5_PM_CAP_ID | 19.F29.B47 | 19.F28.B47 | 19.F29.B46 | 19.F28.B46 | 19.F29.B45 | 19.F28.B45 | 19.F29.B44 | 19.F28.B44 |
| PCIE3:VF5_PM_CAP_NEXTPTR | 20.F29.B31 | 20.F28.B31 | 20.F29.B30 | 20.F28.B30 | 20.F29.B29 | 20.F28.B29 | 20.F29.B28 | 20.F28.B28 |
| non-inverted | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE3:LL_ACK_TIMEOUT | 4.F28.B12 | 4.F29.B11 | 4.F28.B11 | 4.F29.B10 | 4.F28.B10 | 4.F29.B9 | 4.F28.B9 | 4.F29.B8 | 4.F28.B8 |
|---|---|---|---|---|---|---|---|---|---|
| PCIE3:LL_REPLAY_TIMEOUT | 4.F28.B20 | 4.F29.B19 | 4.F28.B19 | 4.F29.B18 | 4.F28.B18 | 4.F29.B17 | 4.F28.B17 | 4.F29.B16 | 4.F28.B16 |
| non-inverted | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE3:LL_CPL_FC_UPDATE_TIMER | 4.F29.B31 | 4.F28.B31 | 4.F29.B30 | 4.F28.B30 | 4.F29.B29 | 4.F28.B29 | 4.F29.B28 | 4.F28.B28 | 4.F29.B27 | 4.F28.B27 | 4.F29.B26 | 4.F28.B26 | 4.F29.B25 | 4.F28.B25 | 4.F29.B24 | 4.F28.B24 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE3:LL_FC_UPDATE_TIMER | 5.F29.B31 | 5.F28.B31 | 5.F29.B30 | 5.F28.B30 | 5.F29.B29 | 5.F28.B29 | 5.F29.B28 | 5.F28.B28 | 5.F29.B27 | 5.F28.B27 | 5.F29.B26 | 5.F28.B26 | 5.F29.B25 | 5.F28.B25 | 5.F29.B24 | 5.F28.B24 |
| PCIE3:LL_NP_FC_UPDATE_TIMER | 5.F29.B15 | 5.F28.B15 | 5.F29.B14 | 5.F28.B14 | 5.F29.B13 | 5.F28.B13 | 5.F29.B12 | 5.F28.B12 | 5.F29.B11 | 5.F28.B11 | 5.F29.B10 | 5.F28.B10 | 5.F29.B9 | 5.F28.B9 | 5.F29.B8 | 5.F28.B8 |
| PCIE3:LL_P_FC_UPDATE_TIMER | 4.F29.B47 | 4.F28.B47 | 4.F29.B46 | 4.F28.B46 | 4.F29.B45 | 4.F28.B45 | 4.F29.B44 | 4.F28.B44 | 4.F29.B43 | 4.F28.B43 | 4.F29.B42 | 4.F28.B42 | 4.F29.B41 | 4.F28.B41 | 4.F29.B40 | 4.F28.B40 |
| PCIE3:PF0_DEVICE_ID | 7.F29.B23 | 7.F28.B23 | 7.F29.B22 | 7.F28.B22 | 7.F29.B21 | 7.F28.B21 | 7.F29.B20 | 7.F28.B20 | 7.F29.B19 | 7.F28.B19 | 7.F29.B18 | 7.F28.B18 | 7.F29.B17 | 7.F28.B17 | 7.F29.B16 | 7.F28.B16 |
| PCIE3:PF0_SRIOV_CAP_INITIAL_VF | 30.F29.B31 | 30.F28.B31 | 30.F29.B30 | 30.F28.B30 | 30.F29.B29 | 30.F28.B29 | 30.F29.B28 | 30.F28.B28 | 30.F29.B27 | 30.F28.B27 | 30.F29.B26 | 30.F28.B26 | 30.F29.B25 | 30.F28.B25 | 30.F29.B24 | 30.F28.B24 |
| PCIE3:PF0_SRIOV_CAP_TOTAL_VF | 30.F29.B47 | 30.F28.B47 | 30.F29.B46 | 30.F28.B46 | 30.F29.B45 | 30.F28.B45 | 30.F29.B44 | 30.F28.B44 | 30.F29.B43 | 30.F28.B43 | 30.F29.B42 | 30.F28.B42 | 30.F29.B41 | 30.F28.B41 | 30.F29.B40 | 30.F28.B40 |
| PCIE3:PF0_SRIOV_FIRST_VF_OFFSET | 31.F29.B31 | 31.F28.B31 | 31.F29.B30 | 31.F28.B30 | 31.F29.B29 | 31.F28.B29 | 31.F29.B28 | 31.F28.B28 | 31.F29.B27 | 31.F28.B27 | 31.F29.B26 | 31.F28.B26 | 31.F29.B25 | 31.F28.B25 | 31.F29.B24 | 31.F28.B24 |
| PCIE3:PF0_SRIOV_FUNC_DEP_LINK | 31.F29.B15 | 31.F28.B15 | 31.F29.B14 | 31.F28.B14 | 31.F29.B13 | 31.F28.B13 | 31.F29.B12 | 31.F28.B12 | 31.F29.B11 | 31.F28.B11 | 31.F29.B10 | 31.F28.B10 | 31.F29.B9 | 31.F28.B9 | 31.F29.B8 | 31.F28.B8 |
| PCIE3:PF0_SRIOV_VF_DEVICE_ID | 31.F29.B47 | 31.F28.B47 | 31.F29.B46 | 31.F28.B46 | 31.F29.B45 | 31.F28.B45 | 31.F29.B44 | 31.F28.B44 | 31.F29.B43 | 31.F28.B43 | 31.F29.B42 | 31.F28.B42 | 31.F29.B41 | 31.F28.B41 | 31.F29.B40 | 31.F28.B40 |
| PCIE3:PF0_SUBSYSTEM_ID | 8.F29.B31 | 8.F28.B31 | 8.F29.B30 | 8.F28.B30 | 8.F29.B29 | 8.F28.B29 | 8.F29.B28 | 8.F28.B28 | 8.F29.B27 | 8.F28.B27 | 8.F29.B26 | 8.F28.B26 | 8.F29.B25 | 8.F28.B25 | 8.F29.B24 | 8.F28.B24 |
| PCIE3:PF1_DEVICE_ID | 7.F29.B31 | 7.F28.B31 | 7.F29.B30 | 7.F28.B30 | 7.F29.B29 | 7.F28.B29 | 7.F29.B28 | 7.F28.B28 | 7.F29.B27 | 7.F28.B27 | 7.F29.B26 | 7.F28.B26 | 7.F29.B25 | 7.F28.B25 | 7.F29.B24 | 7.F28.B24 |
| PCIE3:PF1_SRIOV_CAP_INITIAL_VF | 30.F29.B39 | 30.F28.B39 | 30.F29.B38 | 30.F28.B38 | 30.F29.B37 | 30.F28.B37 | 30.F29.B36 | 30.F28.B36 | 30.F29.B35 | 30.F28.B35 | 30.F29.B34 | 30.F28.B34 | 30.F29.B33 | 30.F28.B33 | 30.F29.B32 | 30.F28.B32 |
| PCIE3:PF1_SRIOV_CAP_TOTAL_VF | 31.F29.B7 | 31.F28.B7 | 31.F29.B6 | 31.F28.B6 | 31.F29.B5 | 31.F28.B5 | 31.F29.B4 | 31.F28.B4 | 31.F29.B3 | 31.F28.B3 | 31.F29.B2 | 31.F28.B2 | 31.F29.B1 | 31.F28.B1 | 31.F29.B0 | 31.F28.B0 |
| PCIE3:PF1_SRIOV_FIRST_VF_OFFSET | 31.F29.B39 | 31.F28.B39 | 31.F29.B38 | 31.F28.B38 | 31.F29.B37 | 31.F28.B37 | 31.F29.B36 | 31.F28.B36 | 31.F29.B35 | 31.F28.B35 | 31.F29.B34 | 31.F28.B34 | 31.F29.B33 | 31.F28.B33 | 31.F29.B32 | 31.F28.B32 |
| PCIE3:PF1_SRIOV_FUNC_DEP_LINK | 31.F29.B23 | 31.F28.B23 | 31.F29.B22 | 31.F28.B22 | 31.F29.B21 | 31.F28.B21 | 31.F29.B20 | 31.F28.B20 | 31.F29.B19 | 31.F28.B19 | 31.F29.B18 | 31.F28.B18 | 31.F29.B17 | 31.F28.B17 | 31.F29.B16 | 31.F28.B16 |
| PCIE3:PF1_SRIOV_VF_DEVICE_ID | 32.F29.B7 | 32.F28.B7 | 32.F29.B6 | 32.F28.B6 | 32.F29.B5 | 32.F28.B5 | 32.F29.B4 | 32.F28.B4 | 32.F29.B3 | 32.F28.B3 | 32.F29.B2 | 32.F28.B2 | 32.F29.B1 | 32.F28.B1 | 32.F29.B0 | 32.F28.B0 |
| PCIE3:PF1_SUBSYSTEM_ID | 8.F29.B39 | 8.F28.B39 | 8.F29.B38 | 8.F28.B38 | 8.F29.B37 | 8.F28.B37 | 8.F29.B36 | 8.F28.B36 | 8.F29.B35 | 8.F28.B35 | 8.F29.B34 | 8.F28.B34 | 8.F29.B33 | 8.F28.B33 | 8.F29.B32 | 8.F28.B32 |
| PCIE3:PL_LANE0_EQ_CONTROL | 2.F29.B39 | 2.F28.B39 | 2.F29.B38 | 2.F28.B38 | 2.F29.B37 | 2.F28.B37 | 2.F29.B36 | 2.F28.B36 | 2.F29.B35 | 2.F28.B35 | 2.F29.B34 | 2.F28.B34 | 2.F29.B33 | 2.F28.B33 | 2.F29.B32 | 2.F28.B32 |
| PCIE3:PL_LANE1_EQ_CONTROL | 2.F29.B47 | 2.F28.B47 | 2.F29.B46 | 2.F28.B46 | 2.F29.B45 | 2.F28.B45 | 2.F29.B44 | 2.F28.B44 | 2.F29.B43 | 2.F28.B43 | 2.F29.B42 | 2.F28.B42 | 2.F29.B41 | 2.F28.B41 | 2.F29.B40 | 2.F28.B40 |
| PCIE3:PL_LANE2_EQ_CONTROL | 3.F29.B7 | 3.F28.B7 | 3.F29.B6 | 3.F28.B6 | 3.F29.B5 | 3.F28.B5 | 3.F29.B4 | 3.F28.B4 | 3.F29.B3 | 3.F28.B3 | 3.F29.B2 | 3.F28.B2 | 3.F29.B1 | 3.F28.B1 | 3.F29.B0 | 3.F28.B0 |
| PCIE3:PL_LANE3_EQ_CONTROL | 3.F29.B15 | 3.F28.B15 | 3.F29.B14 | 3.F28.B14 | 3.F29.B13 | 3.F28.B13 | 3.F29.B12 | 3.F28.B12 | 3.F29.B11 | 3.F28.B11 | 3.F29.B10 | 3.F28.B10 | 3.F29.B9 | 3.F28.B9 | 3.F29.B8 | 3.F28.B8 |
| PCIE3:PL_LANE4_EQ_CONTROL | 3.F29.B23 | 3.F28.B23 | 3.F29.B22 | 3.F28.B22 | 3.F29.B21 | 3.F28.B21 | 3.F29.B20 | 3.F28.B20 | 3.F29.B19 | 3.F28.B19 | 3.F29.B18 | 3.F28.B18 | 3.F29.B17 | 3.F28.B17 | 3.F29.B16 | 3.F28.B16 |
| PCIE3:PL_LANE5_EQ_CONTROL | 3.F29.B31 | 3.F28.B31 | 3.F29.B30 | 3.F28.B30 | 3.F29.B29 | 3.F28.B29 | 3.F29.B28 | 3.F28.B28 | 3.F29.B27 | 3.F28.B27 | 3.F29.B26 | 3.F28.B26 | 3.F29.B25 | 3.F28.B25 | 3.F29.B24 | 3.F28.B24 |
| PCIE3:PL_LANE6_EQ_CONTROL | 3.F29.B39 | 3.F28.B39 | 3.F29.B38 | 3.F28.B38 | 3.F29.B37 | 3.F28.B37 | 3.F29.B36 | 3.F28.B36 | 3.F29.B35 | 3.F28.B35 | 3.F29.B34 | 3.F28.B34 | 3.F29.B33 | 3.F28.B33 | 3.F29.B32 | 3.F28.B32 |
| PCIE3:PL_LANE7_EQ_CONTROL | 3.F29.B47 | 3.F28.B47 | 3.F29.B46 | 3.F28.B46 | 3.F29.B45 | 3.F28.B45 | 3.F29.B44 | 3.F28.B44 | 3.F29.B43 | 3.F28.B43 | 3.F29.B42 | 3.F28.B42 | 3.F29.B41 | 3.F28.B41 | 3.F29.B40 | 3.F28.B40 |
| PCIE3:PM_ASPML0S_TIMEOUT | 0.F29.B31 | 0.F28.B31 | 0.F29.B30 | 0.F28.B30 | 0.F29.B29 | 0.F28.B29 | 0.F29.B28 | 0.F28.B28 | 0.F29.B27 | 0.F28.B27 | 0.F29.B26 | 0.F28.B26 | 0.F29.B25 | 0.F28.B25 | 0.F29.B24 | 0.F28.B24 |
| PCIE3:PM_PME_TURNOFF_ACK_DELAY | 1.F29.B39 | 1.F28.B39 | 1.F29.B38 | 1.F28.B38 | 1.F29.B37 | 1.F28.B37 | 1.F29.B36 | 1.F28.B36 | 1.F29.B35 | 1.F28.B35 | 1.F29.B34 | 1.F28.B34 | 1.F29.B33 | 1.F28.B33 | 1.F29.B32 | 1.F28.B32 |
| non-inverted | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE3:LTR_TX_MESSAGE_MINIMUM_INTERVAL | 28.F29.B4 | 28.F28.B4 | 28.F29.B3 | 28.F28.B3 | 28.F29.B2 | 28.F28.B2 | 28.F29.B1 | 28.F28.B1 | 28.F29.B0 | 28.F28.B0 |
|---|---|---|---|---|---|---|---|---|---|---|
| PCIE3:PF0_LTR_CAP_MAX_NOSNOOP_LAT | 27.F29.B44 | 27.F28.B44 | 27.F29.B43 | 27.F28.B43 | 27.F29.B42 | 27.F28.B42 | 27.F29.B41 | 27.F28.B41 | 27.F29.B40 | 27.F28.B40 |
| PCIE3:PF0_LTR_CAP_MAX_SNOOP_LAT | 27.F29.B36 | 27.F28.B36 | 27.F29.B35 | 27.F28.B35 | 27.F29.B34 | 27.F28.B34 | 27.F29.B33 | 27.F28.B33 | 27.F29.B32 | 27.F28.B32 |
| non-inverted | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE3:PF0_AER_CAP_NEXTPTR | 25.F29.B13 | 25.F28.B13 | 25.F29.B12 | 25.F28.B12 | 25.F29.B11 | 25.F28.B11 | 25.F29.B10 | 25.F28.B10 | 25.F29.B9 | 25.F28.B9 | 25.F29.B8 | 25.F28.B8 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE3:PF0_ARI_CAP_NEXTPTR | 25.F28.B30 | 25.F29.B29 | 25.F28.B29 | 25.F29.B28 | 25.F28.B28 | 25.F29.B27 | 25.F28.B27 | 25.F29.B26 | 25.F28.B26 | 25.F29.B25 | 25.F28.B25 | 25.F29.B24 |
| PCIE3:PF0_DPA_CAP_NEXTPTR | 28.F29.B13 | 28.F28.B13 | 28.F29.B12 | 28.F28.B12 | 28.F29.B11 | 28.F28.B11 | 28.F29.B10 | 28.F28.B10 | 28.F29.B9 | 28.F28.B9 | 28.F29.B8 | 28.F28.B8 |
| PCIE3:PF0_DSN_CAP_NEXTPTR | 23.F29.B37 | 23.F28.B37 | 23.F29.B36 | 23.F28.B36 | 23.F29.B35 | 23.F28.B35 | 23.F29.B34 | 23.F28.B34 | 23.F29.B33 | 23.F28.B33 | 23.F29.B32 | 23.F28.B32 |
| PCIE3:PF0_LTR_CAP_NEXTPTR | 27.F29.B29 | 27.F28.B29 | 27.F29.B28 | 27.F28.B28 | 27.F29.B27 | 27.F28.B27 | 27.F29.B26 | 27.F28.B26 | 27.F29.B25 | 27.F28.B25 | 27.F29.B24 | 27.F28.B24 |
| PCIE3:PF0_PB_CAP_NEXTPTR | 27.F29.B5 | 27.F28.B5 | 27.F29.B4 | 27.F28.B4 | 27.F29.B3 | 27.F28.B3 | 27.F29.B2 | 27.F28.B2 | 27.F29.B1 | 27.F28.B1 | 27.F29.B0 | 27.F28.B0 |
| PCIE3:PF0_RBAR_CAP_NEXTPTR | 21.F29.B13 | 21.F28.B13 | 21.F29.B12 | 21.F28.B12 | 21.F29.B11 | 21.F28.B11 | 21.F29.B10 | 21.F28.B10 | 21.F29.B9 | 21.F28.B9 | 21.F29.B8 | 21.F28.B8 |
| PCIE3:PF0_SRIOV_CAP_NEXTPTR | 30.F28.B6 | 30.F29.B5 | 30.F28.B5 | 30.F29.B4 | 30.F28.B4 | 30.F29.B3 | 30.F28.B3 | 30.F29.B2 | 30.F28.B2 | 30.F29.B1 | 30.F28.B1 | 30.F29.B0 |
| PCIE3:PF0_TPHR_CAP_NEXTPTR | 33.F29.B45 | 33.F28.B45 | 33.F29.B44 | 33.F28.B44 | 33.F29.B43 | 33.F28.B43 | 33.F29.B42 | 33.F28.B42 | 33.F29.B41 | 33.F28.B41 | 33.F29.B40 | 33.F28.B40 |
| PCIE3:PF0_VC_CAP_NEXTPTR | 25.F29.B5 | 25.F28.B5 | 25.F29.B4 | 25.F28.B4 | 25.F29.B3 | 25.F28.B3 | 25.F29.B2 | 25.F28.B2 | 25.F29.B1 | 25.F28.B1 | 25.F29.B0 | 25.F28.B0 |
| PCIE3:PF1_AER_CAP_NEXTPTR | 25.F29.B21 | 25.F28.B21 | 25.F29.B20 | 25.F28.B20 | 25.F29.B19 | 25.F28.B19 | 25.F29.B18 | 25.F28.B18 | 25.F29.B17 | 25.F28.B17 | 25.F29.B16 | 25.F28.B16 |
| PCIE3:PF1_ARI_CAP_NEXTPTR | 25.F29.B37 | 25.F28.B37 | 25.F29.B36 | 25.F28.B36 | 25.F29.B35 | 25.F28.B35 | 25.F29.B34 | 25.F28.B34 | 25.F29.B33 | 25.F28.B33 | 25.F29.B32 | 25.F28.B32 |
| PCIE3:PF1_DPA_CAP_NEXTPTR | 28.F29.B21 | 28.F28.B21 | 28.F29.B20 | 28.F28.B20 | 28.F29.B19 | 28.F28.B19 | 28.F29.B18 | 28.F28.B18 | 28.F29.B17 | 28.F28.B17 | 28.F29.B16 | 28.F28.B16 |
| PCIE3:PF1_DSN_CAP_NEXTPTR | 23.F29.B45 | 23.F28.B45 | 23.F29.B44 | 23.F28.B44 | 23.F29.B43 | 23.F28.B43 | 23.F29.B42 | 23.F28.B42 | 23.F29.B41 | 23.F28.B41 | 23.F29.B40 | 23.F28.B40 |
| PCIE3:PF1_PB_CAP_NEXTPTR | 27.F29.B13 | 27.F28.B13 | 27.F29.B12 | 27.F28.B12 | 27.F29.B11 | 27.F28.B11 | 27.F29.B10 | 27.F28.B10 | 27.F29.B9 | 27.F28.B9 | 27.F29.B8 | 27.F28.B8 |
| PCIE3:PF1_RBAR_CAP_NEXTPTR | 21.F29.B21 | 21.F28.B21 | 21.F29.B20 | 21.F28.B20 | 21.F29.B19 | 21.F28.B19 | 21.F29.B18 | 21.F28.B18 | 21.F29.B17 | 21.F28.B17 | 21.F29.B16 | 21.F28.B16 |
| PCIE3:PF1_SRIOV_CAP_NEXTPTR | 30.F29.B13 | 30.F28.B13 | 30.F29.B12 | 30.F28.B12 | 30.F29.B11 | 30.F28.B11 | 30.F29.B10 | 30.F28.B10 | 30.F29.B9 | 30.F28.B9 | 30.F29.B8 | 30.F28.B8 |
| PCIE3:PF1_TPHR_CAP_NEXTPTR | 34.F29.B5 | 34.F28.B5 | 34.F29.B4 | 34.F28.B4 | 34.F29.B3 | 34.F28.B3 | 34.F29.B2 | 34.F28.B2 | 34.F29.B1 | 34.F28.B1 | 34.F29.B0 | 34.F28.B0 |
| PCIE3:TL_CREDITS_CD | 5.F28.B38 | 5.F29.B37 | 5.F28.B37 | 5.F29.B36 | 5.F28.B36 | 5.F29.B35 | 5.F28.B35 | 5.F29.B34 | 5.F28.B34 | 5.F29.B33 | 5.F28.B33 | 5.F29.B32 |
| PCIE3:TL_CREDITS_NPD | 6.F29.B5 | 6.F28.B5 | 6.F29.B4 | 6.F28.B4 | 6.F29.B3 | 6.F28.B3 | 6.F29.B2 | 6.F28.B2 | 6.F29.B1 | 6.F28.B1 | 6.F29.B0 | 6.F28.B0 |
| PCIE3:TL_CREDITS_PD | 6.F29.B21 | 6.F28.B21 | 6.F29.B20 | 6.F28.B20 | 6.F29.B19 | 6.F28.B19 | 6.F29.B18 | 6.F28.B18 | 6.F29.B17 | 6.F28.B17 | 6.F29.B16 | 6.F28.B16 |
| PCIE3:VF0_ARI_CAP_NEXTPTR | 25.F29.B45 | 25.F28.B45 | 25.F29.B44 | 25.F28.B44 | 25.F29.B43 | 25.F28.B43 | 25.F29.B42 | 25.F28.B42 | 25.F29.B41 | 25.F28.B41 | 25.F29.B40 | 25.F28.B40 |
| PCIE3:VF0_TPHR_CAP_NEXTPTR | 34.F29.B13 | 34.F28.B13 | 34.F29.B12 | 34.F28.B12 | 34.F29.B11 | 34.F28.B11 | 34.F29.B10 | 34.F28.B10 | 34.F29.B9 | 34.F28.B9 | 34.F29.B8 | 34.F28.B8 |
| PCIE3:VF1_ARI_CAP_NEXTPTR | 26.F29.B5 | 26.F28.B5 | 26.F29.B4 | 26.F28.B4 | 26.F29.B3 | 26.F28.B3 | 26.F29.B2 | 26.F28.B2 | 26.F29.B1 | 26.F28.B1 | 26.F29.B0 | 26.F28.B0 |
| PCIE3:VF1_TPHR_CAP_NEXTPTR | 34.F29.B21 | 34.F28.B21 | 34.F29.B20 | 34.F28.B20 | 34.F29.B19 | 34.F28.B19 | 34.F29.B18 | 34.F28.B18 | 34.F29.B17 | 34.F28.B17 | 34.F29.B16 | 34.F28.B16 |
| PCIE3:VF2_ARI_CAP_NEXTPTR | 26.F29.B13 | 26.F28.B13 | 26.F29.B12 | 26.F28.B12 | 26.F29.B11 | 26.F28.B11 | 26.F29.B10 | 26.F28.B10 | 26.F29.B9 | 26.F28.B9 | 26.F29.B8 | 26.F28.B8 |
| PCIE3:VF2_TPHR_CAP_NEXTPTR | 34.F29.B29 | 34.F28.B29 | 34.F29.B28 | 34.F28.B28 | 34.F29.B27 | 34.F28.B27 | 34.F29.B26 | 34.F28.B26 | 34.F29.B25 | 34.F28.B25 | 34.F29.B24 | 34.F28.B24 |
| PCIE3:VF3_ARI_CAP_NEXTPTR | 26.F29.B21 | 26.F28.B21 | 26.F29.B20 | 26.F28.B20 | 26.F29.B19 | 26.F28.B19 | 26.F29.B18 | 26.F28.B18 | 26.F29.B17 | 26.F28.B17 | 26.F29.B16 | 26.F28.B16 |
| PCIE3:VF3_TPHR_CAP_NEXTPTR | 34.F29.B37 | 34.F28.B37 | 34.F29.B36 | 34.F28.B36 | 34.F29.B35 | 34.F28.B35 | 34.F29.B34 | 34.F28.B34 | 34.F29.B33 | 34.F28.B33 | 34.F29.B32 | 34.F28.B32 |
| PCIE3:VF4_ARI_CAP_NEXTPTR | 26.F29.B29 | 26.F28.B29 | 26.F29.B28 | 26.F28.B28 | 26.F29.B27 | 26.F28.B27 | 26.F29.B26 | 26.F28.B26 | 26.F29.B25 | 26.F28.B25 | 26.F29.B24 | 26.F28.B24 |
| PCIE3:VF4_TPHR_CAP_NEXTPTR | 34.F29.B45 | 34.F28.B45 | 34.F29.B44 | 34.F28.B44 | 34.F29.B43 | 34.F28.B43 | 34.F29.B42 | 34.F28.B42 | 34.F29.B41 | 34.F28.B41 | 34.F29.B40 | 34.F28.B40 |
| PCIE3:VF5_ARI_CAP_NEXTPTR | 26.F29.B37 | 26.F28.B37 | 26.F29.B36 | 26.F28.B36 | 26.F29.B35 | 26.F28.B35 | 26.F29.B34 | 26.F28.B34 | 26.F29.B33 | 26.F28.B33 | 26.F29.B32 | 26.F28.B32 |
| PCIE3:VF5_TPHR_CAP_NEXTPTR | 35.F29.B5 | 35.F28.B5 | 35.F29.B4 | 35.F28.B4 | 35.F29.B3 | 35.F28.B3 | 35.F29.B2 | 35.F28.B2 | 35.F29.B1 | 35.F28.B1 | 35.F29.B0 | 35.F28.B0 |
| non-inverted | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE3:PF0_ARI_CAP_VER | 26.F29.B39 | 26.F28.B39 | 26.F29.B38 | 26.F28.B38 |
|---|---|---|---|---|
| PCIE3:PF0_DPA_CAP_VER | 28.F29.B23 | 28.F28.B23 | 28.F29.B22 | 28.F28.B22 |
| PCIE3:PF0_LTR_CAP_VER | 27.F29.B31 | 27.F28.B31 | 27.F29.B30 | 27.F28.B30 |
| PCIE3:PF0_PB_CAP_VER | 27.F29.B15 | 27.F28.B15 | 27.F29.B14 | 27.F28.B14 |
| PCIE3:PF0_RBAR_CAP_VER | 21.F29.B1 | 21.F28.B1 | 21.F29.B0 | 21.F28.B0 |
| PCIE3:PF0_SRIOV_CAP_VER | 30.F29.B15 | 30.F28.B15 | 30.F29.B14 | 30.F28.B14 |
| PCIE3:PF0_TPHR_CAP_VER | 35.F29.B7 | 35.F28.B7 | 35.F29.B6 | 35.F28.B6 |
| PCIE3:PF0_VC_CAP_VER | 23.F29.B47 | 23.F28.B47 | 23.F29.B46 | 23.F28.B46 |
| PCIE3:PF1_DPA_CAP_VER | 28.F29.B25 | 28.F28.B25 | 28.F29.B24 | 28.F28.B24 |
| PCIE3:PF1_PB_CAP_VER | 27.F29.B17 | 27.F28.B17 | 27.F29.B16 | 27.F28.B16 |
| PCIE3:PF1_RBAR_CAP_VER | 21.F29.B3 | 21.F28.B3 | 21.F29.B2 | 21.F28.B2 |
| PCIE3:PF1_SRIOV_CAP_VER | 30.F29.B17 | 30.F28.B17 | 30.F29.B16 | 30.F28.B16 |
| PCIE3:PF1_TPHR_CAP_VER | 35.F29.B9 | 35.F28.B9 | 35.F29.B8 | 35.F28.B8 |
| PCIE3:PL_LINK_CAP_MAX_LINK_WIDTH | 1.F28.B42 | 1.F29.B41 | 1.F28.B41 | 1.F29.B40 |
| PCIE3:VF0_TPHR_CAP_VER | 35.F29.B11 | 35.F28.B11 | 35.F29.B10 | 35.F28.B10 |
| PCIE3:VF1_TPHR_CAP_VER | 35.F29.B13 | 35.F28.B13 | 35.F29.B12 | 35.F28.B12 |
| PCIE3:VF2_TPHR_CAP_VER | 35.F29.B15 | 35.F28.B15 | 35.F29.B14 | 35.F28.B14 |
| PCIE3:VF3_TPHR_CAP_VER | 35.F29.B17 | 35.F28.B17 | 35.F29.B16 | 35.F28.B16 |
| PCIE3:VF4_TPHR_CAP_VER | 35.F29.B19 | 35.F28.B19 | 35.F29.B18 | 35.F28.B18 |
| PCIE3:VF5_TPHR_CAP_VER | 35.F29.B21 | 35.F28.B21 | 35.F29.B20 | 35.F28.B20 |
| non-inverted | [3] | [2] | [1] | [0] |
| PCIE3:PF0_BAR0_APERTURE_SIZE | 9.F28.B29 | 9.F29.B28 | 9.F28.B28 | 9.F29.B27 | 9.F28.B27 |
|---|---|---|---|---|---|
| PCIE3:PF0_BAR1_APERTURE_SIZE | 9.F28.B37 | 9.F29.B36 | 9.F28.B36 | 9.F29.B35 | 9.F28.B35 |
| PCIE3:PF0_BAR2_APERTURE_SIZE | 9.F28.B45 | 9.F29.B44 | 9.F28.B44 | 9.F29.B43 | 9.F28.B43 |
| PCIE3:PF0_BAR3_APERTURE_SIZE | 10.F28.B5 | 10.F29.B4 | 10.F28.B4 | 10.F29.B3 | 10.F28.B3 |
| PCIE3:PF0_BAR4_APERTURE_SIZE | 10.F28.B13 | 10.F29.B12 | 10.F28.B12 | 10.F29.B11 | 10.F28.B11 |
| PCIE3:PF0_BAR5_APERTURE_SIZE | 10.F28.B21 | 10.F29.B20 | 10.F28.B20 | 10.F29.B19 | 10.F28.B19 |
| PCIE3:PF0_DPA_CAP_SUB_STATE_CONTROL | 28.F28.B29 | 28.F29.B28 | 28.F28.B28 | 28.F29.B27 | 28.F28.B27 |
| PCIE3:PF0_EXPANSION_ROM_APERTURE_SIZE | 10.F28.B27 | 10.F29.B26 | 10.F28.B26 | 10.F29.B25 | 10.F28.B25 |
| PCIE3:PF0_SRIOV_BAR0_APERTURE_SIZE | 32.F28.B45 | 32.F29.B44 | 32.F28.B44 | 32.F29.B43 | 32.F28.B43 |
| PCIE3:PF0_SRIOV_BAR1_APERTURE_SIZE | 33.F28.B5 | 33.F29.B4 | 33.F28.B4 | 33.F29.B3 | 33.F28.B3 |
| PCIE3:PF0_SRIOV_BAR2_APERTURE_SIZE | 33.F28.B13 | 33.F29.B12 | 33.F28.B12 | 33.F29.B11 | 33.F28.B11 |
| PCIE3:PF0_SRIOV_BAR3_APERTURE_SIZE | 33.F28.B21 | 33.F29.B20 | 33.F28.B20 | 33.F29.B19 | 33.F28.B19 |
| PCIE3:PF0_SRIOV_BAR4_APERTURE_SIZE | 33.F28.B29 | 33.F29.B28 | 33.F28.B28 | 33.F29.B27 | 33.F28.B27 |
| PCIE3:PF0_SRIOV_BAR5_APERTURE_SIZE | 33.F28.B37 | 33.F29.B36 | 33.F28.B36 | 33.F29.B35 | 33.F28.B35 |
| PCIE3:PF1_BAR0_APERTURE_SIZE | 9.F29.B31 | 9.F28.B31 | 9.F29.B30 | 9.F28.B30 | 9.F29.B29 |
| PCIE3:PF1_BAR1_APERTURE_SIZE | 9.F29.B39 | 9.F28.B39 | 9.F29.B38 | 9.F28.B38 | 9.F29.B37 |
| PCIE3:PF1_BAR2_APERTURE_SIZE | 9.F29.B47 | 9.F28.B47 | 9.F29.B46 | 9.F28.B46 | 9.F29.B45 |
| PCIE3:PF1_BAR3_APERTURE_SIZE | 10.F29.B7 | 10.F28.B7 | 10.F29.B6 | 10.F28.B6 | 10.F29.B5 |
| PCIE3:PF1_BAR4_APERTURE_SIZE | 10.F29.B15 | 10.F28.B15 | 10.F29.B14 | 10.F28.B14 | 10.F29.B13 |
| PCIE3:PF1_BAR5_APERTURE_SIZE | 10.F29.B23 | 10.F28.B23 | 10.F29.B22 | 10.F28.B22 | 10.F29.B21 |
| PCIE3:PF1_DPA_CAP_SUB_STATE_CONTROL | 28.F29.B31 | 28.F28.B31 | 28.F29.B30 | 28.F28.B30 | 28.F29.B29 |
| PCIE3:PF1_EXPANSION_ROM_APERTURE_SIZE | 10.F29.B29 | 10.F28.B29 | 10.F29.B28 | 10.F28.B28 | 10.F29.B27 |
| PCIE3:PF1_SRIOV_BAR0_APERTURE_SIZE | 32.F29.B47 | 32.F28.B47 | 32.F29.B46 | 32.F28.B46 | 32.F29.B45 |
| PCIE3:PF1_SRIOV_BAR1_APERTURE_SIZE | 33.F29.B7 | 33.F28.B7 | 33.F29.B6 | 33.F28.B6 | 33.F29.B5 |
| PCIE3:PF1_SRIOV_BAR2_APERTURE_SIZE | 33.F29.B15 | 33.F28.B15 | 33.F29.B14 | 33.F28.B14 | 33.F29.B13 |
| PCIE3:PF1_SRIOV_BAR3_APERTURE_SIZE | 33.F29.B23 | 33.F28.B23 | 33.F29.B22 | 33.F28.B22 | 33.F29.B21 |
| PCIE3:PF1_SRIOV_BAR4_APERTURE_SIZE | 33.F29.B31 | 33.F28.B31 | 33.F29.B30 | 33.F28.B30 | 33.F29.B29 |
| PCIE3:PF1_SRIOV_BAR5_APERTURE_SIZE | 33.F29.B39 | 33.F28.B39 | 33.F29.B38 | 33.F28.B38 | 33.F29.B37 |
| PCIE3:PL_EQ_ADAPT_ITER_COUNT | 4.F29.B2 | 4.F28.B2 | 4.F29.B1 | 4.F28.B1 | 4.F29.B0 |
| non-inverted | [4] | [3] | [2] | [1] | [0] |
| PCIE3:PF0_BAR0_CONTROL | 9.F28.B25 | 9.F29.B24 | 9.F28.B24 |
|---|---|---|---|
| PCIE3:PF0_BAR1_CONTROL | 9.F28.B33 | 9.F29.B32 | 9.F28.B32 |
| PCIE3:PF0_BAR2_CONTROL | 9.F28.B41 | 9.F29.B40 | 9.F28.B40 |
| PCIE3:PF0_BAR3_CONTROL | 10.F28.B1 | 10.F29.B0 | 10.F28.B0 |
| PCIE3:PF0_BAR4_CONTROL | 10.F28.B9 | 10.F29.B8 | 10.F28.B8 |
| PCIE3:PF0_BAR5_CONTROL | 10.F28.B17 | 10.F29.B16 | 10.F28.B16 |
| PCIE3:PF0_DEV_CAP_ENDPOINT_L0S_LATENCY | 10.F28.B35 | 10.F29.B34 | 10.F28.B34 |
| PCIE3:PF0_DEV_CAP_ENDPOINT_L1_LATENCY | 10.F29.B36 | 10.F28.B36 | 10.F29.B35 |
| PCIE3:PF0_DEV_CAP_MAX_PAYLOAD_SIZE | 10.F28.B31 | 10.F29.B30 | 10.F28.B30 |
| PCIE3:PF0_INTERRUPT_PIN | 8.F28.B41 | 8.F29.B40 | 8.F28.B40 |
| PCIE3:PF0_PM_CAP_VER_ID | 20.F28.B35 | 20.F29.B34 | 20.F28.B34 |
| PCIE3:PF0_RBAR_CAP_INDEX0 | 21.F29.B26 | 21.F28.B26 | 21.F29.B25 |
| PCIE3:PF0_RBAR_CAP_INDEX1 | 22.F28.B11 | 22.F29.B10 | 22.F28.B10 |
| PCIE3:PF0_RBAR_CAP_INDEX2 | 22.F28.B43 | 22.F29.B42 | 22.F28.B42 |
| PCIE3:PF0_RBAR_NUM | 21.F28.B23 | 21.F29.B22 | 21.F28.B22 |
| PCIE3:PF0_SRIOV_BAR0_CONTROL | 32.F28.B41 | 32.F29.B40 | 32.F28.B40 |
| PCIE3:PF0_SRIOV_BAR1_CONTROL | 33.F28.B1 | 33.F29.B0 | 33.F28.B0 |
| PCIE3:PF0_SRIOV_BAR2_CONTROL | 33.F28.B9 | 33.F29.B8 | 33.F28.B8 |
| PCIE3:PF0_SRIOV_BAR3_CONTROL | 33.F28.B17 | 33.F29.B16 | 33.F28.B16 |
| PCIE3:PF0_SRIOV_BAR4_CONTROL | 33.F28.B25 | 33.F29.B24 | 33.F28.B24 |
| PCIE3:PF0_SRIOV_BAR5_CONTROL | 33.F28.B33 | 33.F29.B32 | 33.F28.B32 |
| PCIE3:PF0_TPHR_CAP_ST_MODE_SEL | 37.F29.B6 | 37.F28.B6 | 37.F29.B5 |
| PCIE3:PF1_BAR0_CONTROL | 9.F29.B26 | 9.F28.B26 | 9.F29.B25 |
| PCIE3:PF1_BAR1_CONTROL | 9.F29.B34 | 9.F28.B34 | 9.F29.B33 |
| PCIE3:PF1_BAR2_CONTROL | 9.F29.B42 | 9.F28.B42 | 9.F29.B41 |
| PCIE3:PF1_BAR3_CONTROL | 10.F29.B2 | 10.F28.B2 | 10.F29.B1 |
| PCIE3:PF1_BAR4_CONTROL | 10.F29.B10 | 10.F28.B10 | 10.F29.B9 |
| PCIE3:PF1_BAR5_CONTROL | 10.F29.B18 | 10.F28.B18 | 10.F29.B17 |
| PCIE3:PF1_DEV_CAP_MAX_PAYLOAD_SIZE | 10.F28.B33 | 10.F29.B32 | 10.F28.B32 |
| PCIE3:PF1_INTERRUPT_PIN | 8.F29.B42 | 8.F28.B42 | 8.F29.B41 |
| PCIE3:PF1_PM_CAP_VER_ID | 20.F29.B36 | 20.F28.B36 | 20.F29.B35 |
| PCIE3:PF1_RBAR_CAP_INDEX0 | 21.F28.B28 | 21.F29.B27 | 21.F28.B27 |
| PCIE3:PF1_RBAR_CAP_INDEX1 | 22.F29.B12 | 22.F28.B12 | 22.F29.B11 |
| PCIE3:PF1_RBAR_CAP_INDEX2 | 22.F29.B44 | 22.F28.B44 | 22.F29.B43 |
| PCIE3:PF1_RBAR_NUM | 21.F28.B25 | 21.F29.B24 | 21.F28.B24 |
| PCIE3:PF1_SRIOV_BAR0_CONTROL | 32.F29.B42 | 32.F28.B42 | 32.F29.B41 |
| PCIE3:PF1_SRIOV_BAR1_CONTROL | 33.F29.B2 | 33.F28.B2 | 33.F29.B1 |
| PCIE3:PF1_SRIOV_BAR2_CONTROL | 33.F29.B10 | 33.F28.B10 | 33.F29.B9 |
| PCIE3:PF1_SRIOV_BAR3_CONTROL | 33.F29.B18 | 33.F28.B18 | 33.F29.B17 |
| PCIE3:PF1_SRIOV_BAR4_CONTROL | 33.F29.B26 | 33.F28.B26 | 33.F29.B25 |
| PCIE3:PF1_SRIOV_BAR5_CONTROL | 33.F29.B34 | 33.F28.B34 | 33.F29.B33 |
| PCIE3:PF1_TPHR_CAP_ST_MODE_SEL | 37.F28.B9 | 37.F29.B8 | 37.F28.B8 |
| PCIE3:PL_LINK_CAP_MAX_LINK_SPEED | 1.F29.B43 | 1.F28.B43 | 1.F29.B42 |
| PCIE3:VF0_PM_CAP_VER_ID | 20.F28.B38 | 20.F29.B37 | 20.F28.B37 |
| PCIE3:VF0_TPHR_CAP_ST_MODE_SEL | 37.F29.B10 | 37.F28.B10 | 37.F29.B9 |
| PCIE3:VF1_PM_CAP_VER_ID | 20.F29.B39 | 20.F28.B39 | 20.F29.B38 |
| PCIE3:VF1_TPHR_CAP_ST_MODE_SEL | 37.F28.B12 | 37.F29.B11 | 37.F28.B11 |
| PCIE3:VF2_PM_CAP_VER_ID | 20.F28.B41 | 20.F29.B40 | 20.F28.B40 |
| PCIE3:VF2_TPHR_CAP_ST_MODE_SEL | 37.F29.B13 | 37.F28.B13 | 37.F29.B12 |
| PCIE3:VF3_PM_CAP_VER_ID | 20.F29.B42 | 20.F28.B42 | 20.F29.B41 |
| PCIE3:VF3_TPHR_CAP_ST_MODE_SEL | 37.F28.B15 | 37.F29.B14 | 37.F28.B14 |
| PCIE3:VF4_PM_CAP_VER_ID | 20.F28.B44 | 20.F29.B43 | 20.F28.B43 |
| PCIE3:VF4_TPHR_CAP_ST_MODE_SEL | 37.F28.B17 | 37.F29.B16 | 37.F28.B16 |
| PCIE3:VF5_PM_CAP_VER_ID | 20.F29.B45 | 20.F28.B45 | 20.F29.B44 |
| PCIE3:VF5_TPHR_CAP_ST_MODE_SEL | 37.F29.B18 | 37.F28.B18 | 37.F29.B17 |
| non-inverted | [2] | [1] | [0] |
| PCIE3:PF0_CLASS_CODE | 8.F29.B3 | 8.F28.B3 | 8.F29.B2 | 8.F28.B2 | 8.F29.B1 | 8.F28.B1 | 8.F29.B0 | 8.F28.B0 | 7.F29.B47 | 7.F28.B47 | 7.F29.B46 | 7.F28.B46 | 7.F29.B45 | 7.F28.B45 | 7.F29.B44 | 7.F28.B44 | 7.F29.B43 | 7.F28.B43 | 7.F29.B42 | 7.F28.B42 | 7.F29.B41 | 7.F28.B41 | 7.F29.B40 | 7.F28.B40 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE3:PF1_CLASS_CODE | 8.F29.B19 | 8.F28.B19 | 8.F29.B18 | 8.F28.B18 | 8.F29.B17 | 8.F28.B17 | 8.F29.B16 | 8.F28.B16 | 8.F29.B15 | 8.F28.B15 | 8.F29.B14 | 8.F28.B14 | 8.F29.B13 | 8.F28.B13 | 8.F29.B12 | 8.F28.B12 | 8.F29.B11 | 8.F28.B11 | 8.F29.B10 | 8.F28.B10 | 8.F29.B9 | 8.F28.B9 | 8.F29.B8 | 8.F28.B8 |
| PCIE3:TL_COMPL_TIMEOUT_REG0 | 6.F29.B43 | 6.F28.B43 | 6.F29.B42 | 6.F28.B42 | 6.F29.B41 | 6.F28.B41 | 6.F29.B40 | 6.F28.B40 | 6.F29.B39 | 6.F28.B39 | 6.F29.B38 | 6.F28.B38 | 6.F29.B37 | 6.F28.B37 | 6.F29.B36 | 6.F28.B36 | 6.F29.B35 | 6.F28.B35 | 6.F29.B34 | 6.F28.B34 | 6.F29.B33 | 6.F28.B33 | 6.F29.B32 | 6.F28.B32 |
| non-inverted | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE3:PF0_MSIX_CAP_PBA_OFFSET | 12.F28.B30 | 12.F29.B29 | 12.F28.B29 | 12.F29.B28 | 12.F28.B28 | 12.F29.B27 | 12.F28.B27 | 12.F29.B26 | 12.F28.B26 | 12.F29.B25 | 12.F28.B25 | 12.F29.B24 | 12.F28.B24 | 12.F29.B23 | 12.F28.B23 | 12.F29.B22 | 12.F28.B22 | 12.F29.B21 | 12.F28.B21 | 12.F29.B20 | 12.F28.B20 | 12.F29.B19 | 12.F28.B19 | 12.F29.B18 | 12.F28.B18 | 12.F29.B17 | 12.F28.B17 | 12.F29.B16 | 12.F28.B16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE3:PF0_MSIX_CAP_TABLE_OFFSET | 15.F28.B30 | 15.F29.B29 | 15.F28.B29 | 15.F29.B28 | 15.F28.B28 | 15.F29.B27 | 15.F28.B27 | 15.F29.B26 | 15.F28.B26 | 15.F29.B25 | 15.F28.B25 | 15.F29.B24 | 15.F28.B24 | 15.F29.B23 | 15.F28.B23 | 15.F29.B22 | 15.F28.B22 | 15.F29.B21 | 15.F28.B21 | 15.F29.B20 | 15.F28.B20 | 15.F29.B19 | 15.F28.B19 | 15.F29.B18 | 15.F28.B18 | 15.F29.B17 | 15.F28.B17 | 15.F29.B16 | 15.F28.B16 |
| PCIE3:PF1_MSIX_CAP_PBA_OFFSET | 12.F28.B46 | 12.F29.B45 | 12.F28.B45 | 12.F29.B44 | 12.F28.B44 | 12.F29.B43 | 12.F28.B43 | 12.F29.B42 | 12.F28.B42 | 12.F29.B41 | 12.F28.B41 | 12.F29.B40 | 12.F28.B40 | 12.F29.B39 | 12.F28.B39 | 12.F29.B38 | 12.F28.B38 | 12.F29.B37 | 12.F28.B37 | 12.F29.B36 | 12.F28.B36 | 12.F29.B35 | 12.F28.B35 | 12.F29.B34 | 12.F28.B34 | 12.F29.B33 | 12.F28.B33 | 12.F29.B32 | 12.F28.B32 |
| PCIE3:PF1_MSIX_CAP_TABLE_OFFSET | 15.F28.B46 | 15.F29.B45 | 15.F28.B45 | 15.F29.B44 | 15.F28.B44 | 15.F29.B43 | 15.F28.B43 | 15.F29.B42 | 15.F28.B42 | 15.F29.B41 | 15.F28.B41 | 15.F29.B40 | 15.F28.B40 | 15.F29.B39 | 15.F28.B39 | 15.F29.B38 | 15.F28.B38 | 15.F29.B37 | 15.F28.B37 | 15.F29.B36 | 15.F28.B36 | 15.F29.B35 | 15.F28.B35 | 15.F29.B34 | 15.F28.B34 | 15.F29.B33 | 15.F28.B33 | 15.F29.B32 | 15.F28.B32 |
| PCIE3:VF0_MSIX_CAP_PBA_OFFSET | 13.F28.B14 | 13.F29.B13 | 13.F28.B13 | 13.F29.B12 | 13.F28.B12 | 13.F29.B11 | 13.F28.B11 | 13.F29.B10 | 13.F28.B10 | 13.F29.B9 | 13.F28.B9 | 13.F29.B8 | 13.F28.B8 | 13.F29.B7 | 13.F28.B7 | 13.F29.B6 | 13.F28.B6 | 13.F29.B5 | 13.F28.B5 | 13.F29.B4 | 13.F28.B4 | 13.F29.B3 | 13.F28.B3 | 13.F29.B2 | 13.F28.B2 | 13.F29.B1 | 13.F28.B1 | 13.F29.B0 | 13.F28.B0 |
| PCIE3:VF0_MSIX_CAP_TABLE_OFFSET | 16.F28.B14 | 16.F29.B13 | 16.F28.B13 | 16.F29.B12 | 16.F28.B12 | 16.F29.B11 | 16.F28.B11 | 16.F29.B10 | 16.F28.B10 | 16.F29.B9 | 16.F28.B9 | 16.F29.B8 | 16.F28.B8 | 16.F29.B7 | 16.F28.B7 | 16.F29.B6 | 16.F28.B6 | 16.F29.B5 | 16.F28.B5 | 16.F29.B4 | 16.F28.B4 | 16.F29.B3 | 16.F28.B3 | 16.F29.B2 | 16.F28.B2 | 16.F29.B1 | 16.F28.B1 | 16.F29.B0 | 16.F28.B0 |
| PCIE3:VF1_MSIX_CAP_PBA_OFFSET | 13.F28.B30 | 13.F29.B29 | 13.F28.B29 | 13.F29.B28 | 13.F28.B28 | 13.F29.B27 | 13.F28.B27 | 13.F29.B26 | 13.F28.B26 | 13.F29.B25 | 13.F28.B25 | 13.F29.B24 | 13.F28.B24 | 13.F29.B23 | 13.F28.B23 | 13.F29.B22 | 13.F28.B22 | 13.F29.B21 | 13.F28.B21 | 13.F29.B20 | 13.F28.B20 | 13.F29.B19 | 13.F28.B19 | 13.F29.B18 | 13.F28.B18 | 13.F29.B17 | 13.F28.B17 | 13.F29.B16 | 13.F28.B16 |
| PCIE3:VF1_MSIX_CAP_TABLE_OFFSET | 16.F28.B30 | 16.F29.B29 | 16.F28.B29 | 16.F29.B28 | 16.F28.B28 | 16.F29.B27 | 16.F28.B27 | 16.F29.B26 | 16.F28.B26 | 16.F29.B25 | 16.F28.B25 | 16.F29.B24 | 16.F28.B24 | 16.F29.B23 | 16.F28.B23 | 16.F29.B22 | 16.F28.B22 | 16.F29.B21 | 16.F28.B21 | 16.F29.B20 | 16.F28.B20 | 16.F29.B19 | 16.F28.B19 | 16.F29.B18 | 16.F28.B18 | 16.F29.B17 | 16.F28.B17 | 16.F29.B16 | 16.F28.B16 |
| PCIE3:VF2_MSIX_CAP_PBA_OFFSET | 13.F28.B46 | 13.F29.B45 | 13.F28.B45 | 13.F29.B44 | 13.F28.B44 | 13.F29.B43 | 13.F28.B43 | 13.F29.B42 | 13.F28.B42 | 13.F29.B41 | 13.F28.B41 | 13.F29.B40 | 13.F28.B40 | 13.F29.B39 | 13.F28.B39 | 13.F29.B38 | 13.F28.B38 | 13.F29.B37 | 13.F28.B37 | 13.F29.B36 | 13.F28.B36 | 13.F29.B35 | 13.F28.B35 | 13.F29.B34 | 13.F28.B34 | 13.F29.B33 | 13.F28.B33 | 13.F29.B32 | 13.F28.B32 |
| PCIE3:VF2_MSIX_CAP_TABLE_OFFSET | 16.F28.B46 | 16.F29.B45 | 16.F28.B45 | 16.F29.B44 | 16.F28.B44 | 16.F29.B43 | 16.F28.B43 | 16.F29.B42 | 16.F28.B42 | 16.F29.B41 | 16.F28.B41 | 16.F29.B40 | 16.F28.B40 | 16.F29.B39 | 16.F28.B39 | 16.F29.B38 | 16.F28.B38 | 16.F29.B37 | 16.F28.B37 | 16.F29.B36 | 16.F28.B36 | 16.F29.B35 | 16.F28.B35 | 16.F29.B34 | 16.F28.B34 | 16.F29.B33 | 16.F28.B33 | 16.F29.B32 | 16.F28.B32 |
| PCIE3:VF3_MSIX_CAP_PBA_OFFSET | 14.F28.B14 | 14.F29.B13 | 14.F28.B13 | 14.F29.B12 | 14.F28.B12 | 14.F29.B11 | 14.F28.B11 | 14.F29.B10 | 14.F28.B10 | 14.F29.B9 | 14.F28.B9 | 14.F29.B8 | 14.F28.B8 | 14.F29.B7 | 14.F28.B7 | 14.F29.B6 | 14.F28.B6 | 14.F29.B5 | 14.F28.B5 | 14.F29.B4 | 14.F28.B4 | 14.F29.B3 | 14.F28.B3 | 14.F29.B2 | 14.F28.B2 | 14.F29.B1 | 14.F28.B1 | 14.F29.B0 | 14.F28.B0 |
| PCIE3:VF3_MSIX_CAP_TABLE_OFFSET | 17.F28.B14 | 17.F29.B13 | 17.F28.B13 | 17.F29.B12 | 17.F28.B12 | 17.F29.B11 | 17.F28.B11 | 17.F29.B10 | 17.F28.B10 | 17.F29.B9 | 17.F28.B9 | 17.F29.B8 | 17.F28.B8 | 17.F29.B7 | 17.F28.B7 | 17.F29.B6 | 17.F28.B6 | 17.F29.B5 | 17.F28.B5 | 17.F29.B4 | 17.F28.B4 | 17.F29.B3 | 17.F28.B3 | 17.F29.B2 | 17.F28.B2 | 17.F29.B1 | 17.F28.B1 | 17.F29.B0 | 17.F28.B0 |
| PCIE3:VF4_MSIX_CAP_PBA_OFFSET | 14.F28.B30 | 14.F29.B29 | 14.F28.B29 | 14.F29.B28 | 14.F28.B28 | 14.F29.B27 | 14.F28.B27 | 14.F29.B26 | 14.F28.B26 | 14.F29.B25 | 14.F28.B25 | 14.F29.B24 | 14.F28.B24 | 14.F29.B23 | 14.F28.B23 | 14.F29.B22 | 14.F28.B22 | 14.F29.B21 | 14.F28.B21 | 14.F29.B20 | 14.F28.B20 | 14.F29.B19 | 14.F28.B19 | 14.F29.B18 | 14.F28.B18 | 14.F29.B17 | 14.F28.B17 | 14.F29.B16 | 14.F28.B16 |
| PCIE3:VF4_MSIX_CAP_TABLE_OFFSET | 17.F28.B30 | 17.F29.B29 | 17.F28.B29 | 17.F29.B28 | 17.F28.B28 | 17.F29.B27 | 17.F28.B27 | 17.F29.B26 | 17.F28.B26 | 17.F29.B25 | 17.F28.B25 | 17.F29.B24 | 17.F28.B24 | 17.F29.B23 | 17.F28.B23 | 17.F29.B22 | 17.F28.B22 | 17.F29.B21 | 17.F28.B21 | 17.F29.B20 | 17.F28.B20 | 17.F29.B19 | 17.F28.B19 | 17.F29.B18 | 17.F28.B18 | 17.F29.B17 | 17.F28.B17 | 17.F29.B16 | 17.F28.B16 |
| PCIE3:VF5_MSIX_CAP_PBA_OFFSET | 14.F28.B46 | 14.F29.B45 | 14.F28.B45 | 14.F29.B44 | 14.F28.B44 | 14.F29.B43 | 14.F28.B43 | 14.F29.B42 | 14.F28.B42 | 14.F29.B41 | 14.F28.B41 | 14.F29.B40 | 14.F28.B40 | 14.F29.B39 | 14.F28.B39 | 14.F29.B38 | 14.F28.B38 | 14.F29.B37 | 14.F28.B37 | 14.F29.B36 | 14.F28.B36 | 14.F29.B35 | 14.F28.B35 | 14.F29.B34 | 14.F28.B34 | 14.F29.B33 | 14.F28.B33 | 14.F29.B32 | 14.F28.B32 |
| PCIE3:VF5_MSIX_CAP_TABLE_OFFSET | 17.F28.B46 | 17.F29.B45 | 17.F28.B45 | 17.F29.B44 | 17.F28.B44 | 17.F29.B43 | 17.F28.B43 | 17.F29.B42 | 17.F28.B42 | 17.F29.B41 | 17.F28.B41 | 17.F29.B40 | 17.F28.B40 | 17.F29.B39 | 17.F28.B39 | 17.F29.B38 | 17.F28.B38 | 17.F29.B37 | 17.F28.B37 | 17.F29.B36 | 17.F28.B36 | 17.F29.B35 | 17.F28.B35 | 17.F29.B34 | 17.F28.B34 | 17.F29.B33 | 17.F28.B33 | 17.F29.B32 | 17.F28.B32 |
| non-inverted | [28] | [27] | [26] | [25] | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE3:PF0_MSIX_CAP_TABLE_SIZE | 18.F28.B5 | 18.F29.B4 | 18.F28.B4 | 18.F29.B3 | 18.F28.B3 | 18.F29.B2 | 18.F28.B2 | 18.F29.B1 | 18.F28.B1 | 18.F29.B0 | 18.F28.B0 |
|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE3:PF0_TPHR_CAP_ST_TABLE_SIZE | 35.F28.B45 | 35.F29.B44 | 35.F28.B44 | 35.F29.B43 | 35.F28.B43 | 35.F29.B42 | 35.F28.B42 | 35.F29.B41 | 35.F28.B41 | 35.F29.B40 | 35.F28.B40 |
| PCIE3:PF1_MSIX_CAP_TABLE_SIZE | 18.F28.B13 | 18.F29.B12 | 18.F28.B12 | 18.F29.B11 | 18.F28.B11 | 18.F29.B10 | 18.F28.B10 | 18.F29.B9 | 18.F28.B9 | 18.F29.B8 | 18.F28.B8 |
| PCIE3:PF1_TPHR_CAP_ST_TABLE_SIZE | 36.F28.B5 | 36.F29.B4 | 36.F28.B4 | 36.F29.B3 | 36.F28.B3 | 36.F29.B2 | 36.F28.B2 | 36.F29.B1 | 36.F28.B1 | 36.F29.B0 | 36.F28.B0 |
| PCIE3:VF0_MSIX_CAP_TABLE_SIZE | 18.F28.B21 | 18.F29.B20 | 18.F28.B20 | 18.F29.B19 | 18.F28.B19 | 18.F29.B18 | 18.F28.B18 | 18.F29.B17 | 18.F28.B17 | 18.F29.B16 | 18.F28.B16 |
| PCIE3:VF0_TPHR_CAP_ST_TABLE_SIZE | 36.F28.B13 | 36.F29.B12 | 36.F28.B12 | 36.F29.B11 | 36.F28.B11 | 36.F29.B10 | 36.F28.B10 | 36.F29.B9 | 36.F28.B9 | 36.F29.B8 | 36.F28.B8 |
| PCIE3:VF1_MSIX_CAP_TABLE_SIZE | 18.F28.B29 | 18.F29.B28 | 18.F28.B28 | 18.F29.B27 | 18.F28.B27 | 18.F29.B26 | 18.F28.B26 | 18.F29.B25 | 18.F28.B25 | 18.F29.B24 | 18.F28.B24 |
| PCIE3:VF1_TPHR_CAP_ST_TABLE_SIZE | 36.F28.B21 | 36.F29.B20 | 36.F28.B20 | 36.F29.B19 | 36.F28.B19 | 36.F29.B18 | 36.F28.B18 | 36.F29.B17 | 36.F28.B17 | 36.F29.B16 | 36.F28.B16 |
| PCIE3:VF2_MSIX_CAP_TABLE_SIZE | 18.F28.B37 | 18.F29.B36 | 18.F28.B36 | 18.F29.B35 | 18.F28.B35 | 18.F29.B34 | 18.F28.B34 | 18.F29.B33 | 18.F28.B33 | 18.F29.B32 | 18.F28.B32 |
| PCIE3:VF2_TPHR_CAP_ST_TABLE_SIZE | 36.F28.B29 | 36.F29.B28 | 36.F28.B28 | 36.F29.B27 | 36.F28.B27 | 36.F29.B26 | 36.F28.B26 | 36.F29.B25 | 36.F28.B25 | 36.F29.B24 | 36.F28.B24 |
| PCIE3:VF3_MSIX_CAP_TABLE_SIZE | 18.F28.B45 | 18.F29.B44 | 18.F28.B44 | 18.F29.B43 | 18.F28.B43 | 18.F29.B42 | 18.F28.B42 | 18.F29.B41 | 18.F28.B41 | 18.F29.B40 | 18.F28.B40 |
| PCIE3:VF3_TPHR_CAP_ST_TABLE_SIZE | 36.F28.B37 | 36.F29.B36 | 36.F28.B36 | 36.F29.B35 | 36.F28.B35 | 36.F29.B34 | 36.F28.B34 | 36.F29.B33 | 36.F28.B33 | 36.F29.B32 | 36.F28.B32 |
| PCIE3:VF4_MSIX_CAP_TABLE_SIZE | 19.F28.B5 | 19.F29.B4 | 19.F28.B4 | 19.F29.B3 | 19.F28.B3 | 19.F29.B2 | 19.F28.B2 | 19.F29.B1 | 19.F28.B1 | 19.F29.B0 | 19.F28.B0 |
| PCIE3:VF4_TPHR_CAP_ST_TABLE_SIZE | 36.F28.B45 | 36.F29.B44 | 36.F28.B44 | 36.F29.B43 | 36.F28.B43 | 36.F29.B42 | 36.F28.B42 | 36.F29.B41 | 36.F28.B41 | 36.F29.B40 | 36.F28.B40 |
| PCIE3:VF5_MSIX_CAP_TABLE_SIZE | 19.F28.B13 | 19.F29.B12 | 19.F28.B12 | 19.F29.B11 | 19.F28.B11 | 19.F29.B10 | 19.F28.B10 | 19.F29.B9 | 19.F28.B9 | 19.F29.B8 | 19.F28.B8 |
| PCIE3:VF5_TPHR_CAP_ST_TABLE_SIZE | 37.F28.B5 | 37.F29.B4 | 37.F28.B4 | 37.F29.B3 | 37.F28.B3 | 37.F29.B2 | 37.F28.B2 | 37.F29.B1 | 37.F28.B1 | 37.F29.B0 | 37.F28.B0 |
| non-inverted | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE3:PF0_RBAR_CAP_SIZE0 | 21.F29.B41 | 21.F28.B41 | 21.F29.B40 | 21.F28.B40 | 21.F29.B39 | 21.F28.B39 | 21.F29.B38 | 21.F28.B38 | 21.F29.B37 | 21.F28.B37 | 21.F29.B36 | 21.F28.B36 | 21.F29.B35 | 21.F28.B35 | 21.F29.B34 | 21.F28.B34 | 21.F29.B33 | 21.F28.B33 | 21.F29.B32 | 21.F28.B32 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE3:PF0_RBAR_CAP_SIZE1 | 22.F29.B25 | 22.F28.B25 | 22.F29.B24 | 22.F28.B24 | 22.F29.B23 | 22.F28.B23 | 22.F29.B22 | 22.F28.B22 | 22.F29.B21 | 22.F28.B21 | 22.F29.B20 | 22.F28.B20 | 22.F29.B19 | 22.F28.B19 | 22.F29.B18 | 22.F28.B18 | 22.F29.B17 | 22.F28.B17 | 22.F29.B16 | 22.F28.B16 |
| PCIE3:PF0_RBAR_CAP_SIZE2 | 23.F29.B9 | 23.F28.B9 | 23.F29.B8 | 23.F28.B8 | 23.F29.B7 | 23.F28.B7 | 23.F29.B6 | 23.F28.B6 | 23.F29.B5 | 23.F28.B5 | 23.F29.B4 | 23.F28.B4 | 23.F29.B3 | 23.F28.B3 | 23.F29.B2 | 23.F28.B2 | 23.F29.B1 | 23.F28.B1 | 23.F29.B0 | 23.F28.B0 |
| PCIE3:PF1_RBAR_CAP_SIZE0 | 22.F29.B9 | 22.F28.B9 | 22.F29.B8 | 22.F28.B8 | 22.F29.B7 | 22.F28.B7 | 22.F29.B6 | 22.F28.B6 | 22.F29.B5 | 22.F28.B5 | 22.F29.B4 | 22.F28.B4 | 22.F29.B3 | 22.F28.B3 | 22.F29.B2 | 22.F28.B2 | 22.F29.B1 | 22.F28.B1 | 22.F29.B0 | 22.F28.B0 |
| PCIE3:PF1_RBAR_CAP_SIZE1 | 22.F29.B41 | 22.F28.B41 | 22.F29.B40 | 22.F28.B40 | 22.F29.B39 | 22.F28.B39 | 22.F29.B38 | 22.F28.B38 | 22.F29.B37 | 22.F28.B37 | 22.F29.B36 | 22.F28.B36 | 22.F29.B35 | 22.F28.B35 | 22.F29.B34 | 22.F28.B34 | 22.F29.B33 | 22.F28.B33 | 22.F29.B32 | 22.F28.B32 |
| PCIE3:PF1_RBAR_CAP_SIZE2 | 23.F29.B25 | 23.F28.B25 | 23.F29.B24 | 23.F28.B24 | 23.F29.B23 | 23.F28.B23 | 23.F29.B22 | 23.F28.B22 | 23.F29.B21 | 23.F28.B21 | 23.F29.B20 | 23.F28.B20 | 23.F29.B19 | 23.F28.B19 | 23.F29.B18 | 23.F28.B18 | 23.F29.B17 | 23.F28.B17 | 23.F29.B16 | 23.F28.B16 |
| PCIE3:PM_ASPML1_ENTRY_DELAY | 1.F29.B9 | 1.F28.B9 | 1.F29.B8 | 1.F28.B8 | 1.F29.B7 | 1.F28.B7 | 1.F29.B6 | 1.F28.B6 | 1.F29.B5 | 1.F28.B5 | 1.F29.B4 | 1.F28.B4 | 1.F29.B3 | 1.F28.B3 | 1.F29.B2 | 1.F28.B2 | 1.F29.B1 | 1.F28.B1 | 1.F29.B0 | 1.F28.B0 |
| PCIE3:PM_PME_SERVICE_TIMEOUT_DELAY | 1.F29.B25 | 1.F28.B25 | 1.F29.B24 | 1.F28.B24 | 1.F29.B23 | 1.F28.B23 | 1.F29.B22 | 1.F28.B22 | 1.F29.B21 | 1.F28.B21 | 1.F29.B20 | 1.F28.B20 | 1.F29.B19 | 1.F28.B19 | 1.F29.B18 | 1.F28.B18 | 1.F29.B17 | 1.F28.B17 | 1.F29.B16 | 1.F28.B16 |
| non-inverted | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE3:PF0_SRIOV_SUPPORTED_PAGE_SIZE | 32.F29.B23 | 32.F28.B23 | 32.F29.B22 | 32.F28.B22 | 32.F29.B21 | 32.F28.B21 | 32.F29.B20 | 32.F28.B20 | 32.F29.B19 | 32.F28.B19 | 32.F29.B18 | 32.F28.B18 | 32.F29.B17 | 32.F28.B17 | 32.F29.B16 | 32.F28.B16 | 32.F29.B15 | 32.F28.B15 | 32.F29.B14 | 32.F28.B14 | 32.F29.B13 | 32.F28.B13 | 32.F29.B12 | 32.F28.B12 | 32.F29.B11 | 32.F28.B11 | 32.F29.B10 | 32.F28.B10 | 32.F29.B9 | 32.F28.B9 | 32.F29.B8 | 32.F28.B8 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE3:PF1_SRIOV_SUPPORTED_PAGE_SIZE | 32.F29.B39 | 32.F28.B39 | 32.F29.B38 | 32.F28.B38 | 32.F29.B37 | 32.F28.B37 | 32.F29.B36 | 32.F28.B36 | 32.F29.B35 | 32.F28.B35 | 32.F29.B34 | 32.F28.B34 | 32.F29.B33 | 32.F28.B33 | 32.F29.B32 | 32.F28.B32 | 32.F29.B31 | 32.F28.B31 | 32.F29.B30 | 32.F28.B30 | 32.F29.B29 | 32.F28.B29 | 32.F29.B28 | 32.F28.B28 | 32.F29.B27 | 32.F28.B27 | 32.F29.B26 | 32.F28.B26 | 32.F29.B25 | 32.F28.B25 | 32.F29.B24 | 32.F28.B24 |
| PCIE3:PM_L1_REENTRY_DELAY | 0.F29.B47 | 0.F28.B47 | 0.F29.B46 | 0.F28.B46 | 0.F29.B45 | 0.F28.B45 | 0.F29.B44 | 0.F28.B44 | 0.F29.B43 | 0.F28.B43 | 0.F29.B42 | 0.F28.B42 | 0.F29.B41 | 0.F28.B41 | 0.F29.B40 | 0.F28.B40 | 0.F29.B39 | 0.F28.B39 | 0.F29.B38 | 0.F28.B38 | 0.F29.B37 | 0.F28.B37 | 0.F29.B36 | 0.F28.B36 | 0.F29.B35 | 0.F28.B35 | 0.F29.B34 | 0.F28.B34 | 0.F29.B33 | 0.F28.B33 | 0.F29.B32 | 0.F28.B32 |
| PCIE3:SPARE_WORD0 | 38.F29.B15 | 38.F28.B15 | 38.F29.B14 | 38.F28.B14 | 38.F29.B13 | 38.F28.B13 | 38.F29.B12 | 38.F28.B12 | 38.F29.B11 | 38.F28.B11 | 38.F29.B10 | 38.F28.B10 | 38.F29.B9 | 38.F28.B9 | 38.F29.B8 | 38.F28.B8 | 38.F29.B7 | 38.F28.B7 | 38.F29.B6 | 38.F28.B6 | 38.F29.B5 | 38.F28.B5 | 38.F29.B4 | 38.F28.B4 | 38.F29.B3 | 38.F28.B3 | 38.F29.B2 | 38.F28.B2 | 38.F29.B1 | 38.F28.B1 | 38.F29.B0 | 38.F28.B0 |
| PCIE3:SPARE_WORD1 | 38.F29.B31 | 38.F28.B31 | 38.F29.B30 | 38.F28.B30 | 38.F29.B29 | 38.F28.B29 | 38.F29.B28 | 38.F28.B28 | 38.F29.B27 | 38.F28.B27 | 38.F29.B26 | 38.F28.B26 | 38.F29.B25 | 38.F28.B25 | 38.F29.B24 | 38.F28.B24 | 38.F29.B23 | 38.F28.B23 | 38.F29.B22 | 38.F28.B22 | 38.F29.B21 | 38.F28.B21 | 38.F29.B20 | 38.F28.B20 | 38.F29.B19 | 38.F28.B19 | 38.F29.B18 | 38.F28.B18 | 38.F29.B17 | 38.F28.B17 | 38.F29.B16 | 38.F28.B16 |
| PCIE3:SPARE_WORD2 | 38.F29.B47 | 38.F28.B47 | 38.F29.B46 | 38.F28.B46 | 38.F29.B45 | 38.F28.B45 | 38.F29.B44 | 38.F28.B44 | 38.F29.B43 | 38.F28.B43 | 38.F29.B42 | 38.F28.B42 | 38.F29.B41 | 38.F28.B41 | 38.F29.B40 | 38.F28.B40 | 38.F29.B39 | 38.F28.B39 | 38.F29.B38 | 38.F28.B38 | 38.F29.B37 | 38.F28.B37 | 38.F29.B36 | 38.F28.B36 | 38.F29.B35 | 38.F28.B35 | 38.F29.B34 | 38.F28.B34 | 38.F29.B33 | 38.F28.B33 | 38.F29.B32 | 38.F28.B32 |
| PCIE3:SPARE_WORD3 | 39.F29.B15 | 39.F28.B15 | 39.F29.B14 | 39.F28.B14 | 39.F29.B13 | 39.F28.B13 | 39.F29.B12 | 39.F28.B12 | 39.F29.B11 | 39.F28.B11 | 39.F29.B10 | 39.F28.B10 | 39.F29.B9 | 39.F28.B9 | 39.F29.B8 | 39.F28.B8 | 39.F29.B7 | 39.F28.B7 | 39.F29.B6 | 39.F28.B6 | 39.F29.B5 | 39.F28.B5 | 39.F29.B4 | 39.F28.B4 | 39.F29.B3 | 39.F28.B3 | 39.F29.B2 | 39.F28.B2 | 39.F29.B1 | 39.F28.B1 | 39.F29.B0 | 39.F28.B0 |
| non-inverted | [31] | [30] | [29] | [28] | [27] | [26] | [25] | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE3:TL_COMPL_TIMEOUT_REG1 | 7.F29.B13 | 7.F28.B13 | 7.F29.B12 | 7.F28.B12 | 7.F29.B11 | 7.F28.B11 | 7.F29.B10 | 7.F28.B10 | 7.F29.B9 | 7.F28.B9 | 7.F29.B8 | 7.F28.B8 | 7.F29.B7 | 7.F28.B7 | 7.F29.B6 | 7.F28.B6 | 7.F29.B5 | 7.F28.B5 | 7.F29.B4 | 7.F28.B4 | 7.F29.B3 | 7.F28.B3 | 7.F29.B2 | 7.F28.B2 | 7.F29.B1 | 7.F28.B1 | 7.F29.B0 | 7.F28.B0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| non-inverted | [27] | [26] | [25] | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |