PCI Express Gen2 cores
Tile PCIE
Cells: 50
Bel PCIE
| Pin | Direction | Wires |
|---|---|---|
| CFGAERECRCCHECKEN | output | TCELL44:OUT17.TMIN |
| CFGAERECRCGENEN | output | TCELL44:OUT18.TMIN |
| CFGAERINTERRUPTMSGNUM0 | input | TCELL39:IMUX.IMUX12.DELAY |
| CFGAERINTERRUPTMSGNUM1 | input | TCELL39:IMUX.IMUX13.DELAY |
| CFGAERINTERRUPTMSGNUM2 | input | TCELL39:IMUX.IMUX14.DELAY |
| CFGAERINTERRUPTMSGNUM3 | input | TCELL39:IMUX.IMUX15.DELAY |
| CFGAERINTERRUPTMSGNUM4 | input | TCELL41:IMUX.IMUX12.DELAY |
| CFGAERROOTERRCORRERRRECEIVED | output | TCELL45:OUT21.TMIN |
| CFGAERROOTERRCORRERRREPORTINGEN | output | TCELL44:OUT19.TMIN |
| CFGAERROOTERRFATALERRRECEIVED | output | TCELL46:OUT16.TMIN |
| CFGAERROOTERRFATALERRREPORTINGEN | output | TCELL45:OUT20.TMIN |
| CFGAERROOTERRNONFATALERRRECEIVED | output | TCELL45:OUT22.TMIN |
| CFGAERROOTERRNONFATALERRREPORTINGEN | output | TCELL45:OUT19.TMIN |
| CFGBRIDGESERREN | output | TCELL33:OUT17.TMIN |
| CFGCOMMANDBUSMASTERENABLE | output | TCELL24:OUT20.TMIN |
| CFGCOMMANDINTERRUPTDISABLE | output | TCELL24:OUT21.TMIN |
| CFGCOMMANDIOENABLE | output | TCELL49:OUT11.TMIN |
| CFGCOMMANDMEMENABLE | output | TCELL24:OUT17.TMIN |
| CFGCOMMANDSERREN | output | TCELL33:OUT16.TMIN |
| CFGDEVCONTROL2ARIFORWARDEN | output | TCELL48:OUT15.TMIN |
| CFGDEVCONTROL2ATOMICEGRESSBLOCK | output | TCELL49:OUT13.TMIN |
| CFGDEVCONTROL2ATOMICREQUESTEREN | output | TCELL49:OUT12.TMIN |
| CFGDEVCONTROL2CPLTIMEOUTDIS | output | TCELL48:OUT14.TMIN |
| CFGDEVCONTROL2CPLTIMEOUTVAL0 | output | TCELL47:OUT14.TMIN |
| CFGDEVCONTROL2CPLTIMEOUTVAL1 | output | TCELL47:OUT15.TMIN |
| CFGDEVCONTROL2CPLTIMEOUTVAL2 | output | TCELL48:OUT12.TMIN |
| CFGDEVCONTROL2CPLTIMEOUTVAL3 | output | TCELL48:OUT13.TMIN |
| CFGDEVCONTROL2IDOCPLEN | output | TCELL49:OUT15.TMIN |
| CFGDEVCONTROL2IDOREQEN | output | TCELL49:OUT14.TMIN |
| CFGDEVCONTROL2LTREN | output | TCELL24:OUT23.TMIN |
| CFGDEVCONTROL2TLPPREFIXBLOCK | output | TCELL40:OUT21.TMIN |
| CFGDEVCONTROLAUXPOWEREN | output | TCELL40:OUT19.TMIN |
| CFGDEVCONTROLCORRERRREPORTINGEN | output | TCELL37:OUT20.TMIN |
| CFGDEVCONTROLENABLERO | output | TCELL39:OUT18.TMIN |
| CFGDEVCONTROLEXTTAGEN | output | TCELL40:OUT17.TMIN |
| CFGDEVCONTROLFATALERRREPORTINGEN | output | TCELL38:OUT20.TMIN |
| CFGDEVCONTROLMAXPAYLOAD0 | output | TCELL39:OUT19.TMIN |
| CFGDEVCONTROLMAXPAYLOAD1 | output | TCELL39:OUT20.TMIN |
| CFGDEVCONTROLMAXPAYLOAD2 | output | TCELL39:OUT21.TMIN |
| CFGDEVCONTROLMAXREADREQ0 | output | TCELL41:OUT16.TMIN |
| CFGDEVCONTROLMAXREADREQ1 | output | TCELL41:OUT17.TMIN |
| CFGDEVCONTROLMAXREADREQ2 | output | TCELL41:OUT18.TMIN |
| CFGDEVCONTROLNONFATALREPORTINGEN | output | TCELL37:OUT21.TMIN |
| CFGDEVCONTROLNOSNOOPEN | output | TCELL40:OUT20.TMIN |
| CFGDEVCONTROLPHANTOMEN | output | TCELL40:OUT18.TMIN |
| CFGDEVCONTROLURERRREPORTINGEN | output | TCELL38:OUT21.TMIN |
| CFGDEVID0 | input | TCELL46:IMUX.IMUX11.DELAY |
| CFGDEVID1 | input | TCELL47:IMUX.IMUX8.DELAY |
| CFGDEVID10 | input | TCELL49:IMUX.IMUX9.DELAY |
| CFGDEVID11 | input | TCELL49:IMUX.IMUX10.DELAY |
| CFGDEVID12 | input | TCELL49:IMUX.IMUX11.DELAY |
| CFGDEVID13 | input | TCELL24:IMUX.IMUX21.DELAY |
| CFGDEVID14 | input | TCELL24:IMUX.IMUX22.DELAY |
| CFGDEVID15 | input | TCELL24:IMUX.IMUX23.DELAY |
| CFGDEVID2 | input | TCELL47:IMUX.IMUX9.DELAY |
| CFGDEVID3 | input | TCELL47:IMUX.IMUX10.DELAY |
| CFGDEVID4 | input | TCELL47:IMUX.IMUX11.DELAY |
| CFGDEVID5 | input | TCELL48:IMUX.IMUX8.DELAY |
| CFGDEVID6 | input | TCELL48:IMUX.IMUX9.DELAY |
| CFGDEVID7 | input | TCELL48:IMUX.IMUX10.DELAY |
| CFGDEVID8 | input | TCELL48:IMUX.IMUX11.DELAY |
| CFGDEVID9 | input | TCELL49:IMUX.IMUX8.DELAY |
| CFGDEVSTATUSCORRERRDETECTED | output | TCELL34:OUT16.TMIN |
| CFGDEVSTATUSFATALERRDETECTED | output | TCELL35:OUT16.TMIN |
| CFGDEVSTATUSNONFATALERRDETECTED | output | TCELL34:OUT17.TMIN |
| CFGDEVSTATUSURDETECTED | output | TCELL35:OUT17.TMIN |
| CFGDSBUSNUMBER0 | input | TCELL12:IMUX.IMUX14.DELAY |
| CFGDSBUSNUMBER1 | input | TCELL12:IMUX.IMUX15.DELAY |
| CFGDSBUSNUMBER2 | input | TCELL12:IMUX.IMUX16.DELAY |
| CFGDSBUSNUMBER3 | input | TCELL11:IMUX.IMUX13.DELAY |
| CFGDSBUSNUMBER4 | input | TCELL11:IMUX.IMUX14.DELAY |
| CFGDSBUSNUMBER5 | input | TCELL11:IMUX.IMUX15.DELAY |
| CFGDSBUSNUMBER6 | input | TCELL11:IMUX.IMUX16.DELAY |
| CFGDSBUSNUMBER7 | input | TCELL10:IMUX.IMUX13.DELAY |
| CFGDSDEVICENUMBER0 | input | TCELL10:IMUX.IMUX14.DELAY |
| CFGDSDEVICENUMBER1 | input | TCELL10:IMUX.IMUX15.DELAY |
| CFGDSDEVICENUMBER2 | input | TCELL10:IMUX.IMUX17.DELAY |
| CFGDSDEVICENUMBER3 | input | TCELL2:IMUX.IMUX20.DELAY |
| CFGDSDEVICENUMBER4 | input | TCELL1:IMUX.IMUX16.DELAY |
| CFGDSFUNCTIONNUMBER0 | input | TCELL1:IMUX.IMUX17.DELAY |
| CFGDSFUNCTIONNUMBER1 | input | TCELL1:IMUX.IMUX18.DELAY |
| CFGDSFUNCTIONNUMBER2 | input | TCELL1:IMUX.IMUX19.DELAY |
| CFGDSN0 | input | TCELL30:IMUX.IMUX11.DELAY |
| CFGDSN1 | input | TCELL31:IMUX.IMUX8.DELAY |
| CFGDSN10 | input | TCELL33:IMUX.IMUX9.DELAY |
| CFGDSN11 | input | TCELL33:IMUX.IMUX10.DELAY |
| CFGDSN12 | input | TCELL33:IMUX.IMUX11.DELAY |
| CFGDSN13 | input | TCELL34:IMUX.IMUX8.DELAY |
| CFGDSN14 | input | TCELL34:IMUX.IMUX9.DELAY |
| CFGDSN15 | input | TCELL34:IMUX.IMUX10.DELAY |
| CFGDSN16 | input | TCELL34:IMUX.IMUX11.DELAY |
| CFGDSN17 | input | TCELL35:IMUX.IMUX8.DELAY |
| CFGDSN18 | input | TCELL35:IMUX.IMUX9.DELAY |
| CFGDSN19 | input | TCELL35:IMUX.IMUX10.DELAY |
| CFGDSN2 | input | TCELL31:IMUX.IMUX9.DELAY |
| CFGDSN20 | input | TCELL35:IMUX.IMUX11.DELAY |
| CFGDSN21 | input | TCELL36:IMUX.IMUX8.DELAY |
| CFGDSN22 | input | TCELL36:IMUX.IMUX9.DELAY |
| CFGDSN23 | input | TCELL36:IMUX.IMUX10.DELAY |
| CFGDSN24 | input | TCELL36:IMUX.IMUX11.DELAY |
| CFGDSN25 | input | TCELL37:IMUX.IMUX8.DELAY |
| CFGDSN26 | input | TCELL37:IMUX.IMUX9.DELAY |
| CFGDSN27 | input | TCELL37:IMUX.IMUX10.DELAY |
| CFGDSN28 | input | TCELL37:IMUX.IMUX11.DELAY |
| CFGDSN29 | input | TCELL38:IMUX.IMUX8.DELAY |
| CFGDSN3 | input | TCELL31:IMUX.IMUX10.DELAY |
| CFGDSN30 | input | TCELL38:IMUX.IMUX9.DELAY |
| CFGDSN31 | input | TCELL38:IMUX.IMUX10.DELAY |
| CFGDSN32 | input | TCELL38:IMUX.IMUX11.DELAY |
| CFGDSN33 | input | TCELL39:IMUX.IMUX8.DELAY |
| CFGDSN34 | input | TCELL39:IMUX.IMUX9.DELAY |
| CFGDSN35 | input | TCELL39:IMUX.IMUX10.DELAY |
| CFGDSN36 | input | TCELL39:IMUX.IMUX11.DELAY |
| CFGDSN37 | input | TCELL40:IMUX.IMUX8.DELAY |
| CFGDSN38 | input | TCELL40:IMUX.IMUX9.DELAY |
| CFGDSN39 | input | TCELL40:IMUX.IMUX10.DELAY |
| CFGDSN4 | input | TCELL31:IMUX.IMUX11.DELAY |
| CFGDSN40 | input | TCELL40:IMUX.IMUX11.DELAY |
| CFGDSN41 | input | TCELL41:IMUX.IMUX8.DELAY |
| CFGDSN42 | input | TCELL41:IMUX.IMUX9.DELAY |
| CFGDSN43 | input | TCELL41:IMUX.IMUX10.DELAY |
| CFGDSN44 | input | TCELL41:IMUX.IMUX11.DELAY |
| CFGDSN45 | input | TCELL42:IMUX.IMUX8.DELAY |
| CFGDSN46 | input | TCELL42:IMUX.IMUX9.DELAY |
| CFGDSN47 | input | TCELL42:IMUX.IMUX10.DELAY |
| CFGDSN48 | input | TCELL42:IMUX.IMUX11.DELAY |
| CFGDSN49 | input | TCELL43:IMUX.IMUX8.DELAY |
| CFGDSN5 | input | TCELL32:IMUX.IMUX8.DELAY |
| CFGDSN50 | input | TCELL43:IMUX.IMUX9.DELAY |
| CFGDSN51 | input | TCELL43:IMUX.IMUX10.DELAY |
| CFGDSN52 | input | TCELL43:IMUX.IMUX11.DELAY |
| CFGDSN53 | input | TCELL44:IMUX.IMUX8.DELAY |
| CFGDSN54 | input | TCELL44:IMUX.IMUX9.DELAY |
| CFGDSN55 | input | TCELL44:IMUX.IMUX10.DELAY |
| CFGDSN56 | input | TCELL44:IMUX.IMUX11.DELAY |
| CFGDSN57 | input | TCELL45:IMUX.IMUX8.DELAY |
| CFGDSN58 | input | TCELL45:IMUX.IMUX9.DELAY |
| CFGDSN59 | input | TCELL45:IMUX.IMUX10.DELAY |
| CFGDSN6 | input | TCELL32:IMUX.IMUX9.DELAY |
| CFGDSN60 | input | TCELL45:IMUX.IMUX11.DELAY |
| CFGDSN61 | input | TCELL46:IMUX.IMUX8.DELAY |
| CFGDSN62 | input | TCELL46:IMUX.IMUX9.DELAY |
| CFGDSN63 | input | TCELL46:IMUX.IMUX10.DELAY |
| CFGDSN7 | input | TCELL32:IMUX.IMUX10.DELAY |
| CFGDSN8 | input | TCELL32:IMUX.IMUX11.DELAY |
| CFGDSN9 | input | TCELL33:IMUX.IMUX8.DELAY |
| CFGERRACSN | input | TCELL16:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG0 | input | TCELL22:IMUX.IMUX19.DELAY |
| CFGERRAERHEADERLOG1 | input | TCELL22:IMUX.IMUX20.DELAY |
| CFGERRAERHEADERLOG10 | input | TCELL23:IMUX.IMUX24.DELAY |
| CFGERRAERHEADERLOG100 | input | TCELL31:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG101 | input | TCELL31:IMUX.IMUX7.DELAY |
| CFGERRAERHEADERLOG102 | input | TCELL32:IMUX.IMUX4.DELAY |
| CFGERRAERHEADERLOG103 | input | TCELL32:IMUX.IMUX5.DELAY |
| CFGERRAERHEADERLOG104 | input | TCELL32:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG105 | input | TCELL32:IMUX.IMUX7.DELAY |
| CFGERRAERHEADERLOG106 | input | TCELL33:IMUX.IMUX4.DELAY |
| CFGERRAERHEADERLOG107 | input | TCELL33:IMUX.IMUX5.DELAY |
| CFGERRAERHEADERLOG108 | input | TCELL33:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG109 | input | TCELL33:IMUX.IMUX7.DELAY |
| CFGERRAERHEADERLOG11 | input | TCELL22:IMUX.IMUX21.DELAY |
| CFGERRAERHEADERLOG110 | input | TCELL34:IMUX.IMUX4.DELAY |
| CFGERRAERHEADERLOG111 | input | TCELL34:IMUX.IMUX5.DELAY |
| CFGERRAERHEADERLOG112 | input | TCELL34:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG113 | input | TCELL34:IMUX.IMUX7.DELAY |
| CFGERRAERHEADERLOG114 | input | TCELL35:IMUX.IMUX4.DELAY |
| CFGERRAERHEADERLOG115 | input | TCELL35:IMUX.IMUX5.DELAY |
| CFGERRAERHEADERLOG116 | input | TCELL35:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG117 | input | TCELL35:IMUX.IMUX7.DELAY |
| CFGERRAERHEADERLOG118 | input | TCELL36:IMUX.IMUX4.DELAY |
| CFGERRAERHEADERLOG119 | input | TCELL36:IMUX.IMUX5.DELAY |
| CFGERRAERHEADERLOG12 | input | TCELL16:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG120 | input | TCELL36:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG121 | input | TCELL36:IMUX.IMUX7.DELAY |
| CFGERRAERHEADERLOG122 | input | TCELL37:IMUX.IMUX4.DELAY |
| CFGERRAERHEADERLOG123 | input | TCELL37:IMUX.IMUX5.DELAY |
| CFGERRAERHEADERLOG124 | input | TCELL37:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG125 | input | TCELL37:IMUX.IMUX7.DELAY |
| CFGERRAERHEADERLOG126 | input | TCELL38:IMUX.IMUX4.DELAY |
| CFGERRAERHEADERLOG127 | input | TCELL38:IMUX.IMUX5.DELAY |
| CFGERRAERHEADERLOG13 | input | TCELL16:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG14 | input | TCELL14:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG15 | input | TCELL14:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG16 | input | TCELL14:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG17 | input | TCELL14:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG18 | input | TCELL13:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG19 | input | TCELL13:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG2 | input | TCELL23:IMUX.IMUX20.DELAY |
| CFGERRAERHEADERLOG20 | input | TCELL13:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG21 | input | TCELL13:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG22 | input | TCELL12:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG23 | input | TCELL12:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG24 | input | TCELL12:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG25 | input | TCELL12:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG26 | input | TCELL11:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG27 | input | TCELL11:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG28 | input | TCELL11:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG29 | input | TCELL11:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG3 | input | TCELL23:IMUX.IMUX21.DELAY |
| CFGERRAERHEADERLOG30 | input | TCELL10:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG31 | input | TCELL10:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG32 | input | TCELL10:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG33 | input | TCELL10:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG34 | input | TCELL9:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG35 | input | TCELL9:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG36 | input | TCELL9:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG37 | input | TCELL9:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG38 | input | TCELL8:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG39 | input | TCELL8:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG4 | input | TCELL23:IMUX.IMUX22.DELAY |
| CFGERRAERHEADERLOG40 | input | TCELL8:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG41 | input | TCELL8:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG42 | input | TCELL7:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG43 | input | TCELL7:IMUX.IMUX15.DELAY |
| CFGERRAERHEADERLOG44 | input | TCELL7:IMUX.IMUX16.DELAY |
| CFGERRAERHEADERLOG45 | input | TCELL7:IMUX.IMUX17.DELAY |
| CFGERRAERHEADERLOG46 | input | TCELL6:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG47 | input | TCELL6:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG48 | input | TCELL6:IMUX.IMUX15.DELAY |
| CFGERRAERHEADERLOG49 | input | TCELL6:IMUX.IMUX17.DELAY |
| CFGERRAERHEADERLOG5 | input | TCELL23:IMUX.IMUX23.DELAY |
| CFGERRAERHEADERLOG50 | input | TCELL5:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG51 | input | TCELL5:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG52 | input | TCELL5:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG53 | input | TCELL5:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG54 | input | TCELL4:IMUX.IMUX8.DELAY |
| CFGERRAERHEADERLOG55 | input | TCELL4:IMUX.IMUX9.DELAY |
| CFGERRAERHEADERLOG56 | input | TCELL4:IMUX.IMUX10.DELAY |
| CFGERRAERHEADERLOG57 | input | TCELL4:IMUX.IMUX11.DELAY |
| CFGERRAERHEADERLOG58 | input | TCELL3:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG59 | input | TCELL3:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG6 | input | TCELL24:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG60 | input | TCELL3:IMUX.IMUX15.DELAY |
| CFGERRAERHEADERLOG61 | input | TCELL3:IMUX.IMUX16.DELAY |
| CFGERRAERHEADERLOG62 | input | TCELL2:IMUX.IMUX16.DELAY |
| CFGERRAERHEADERLOG63 | input | TCELL2:IMUX.IMUX17.DELAY |
| CFGERRAERHEADERLOG64 | input | TCELL2:IMUX.IMUX18.DELAY |
| CFGERRAERHEADERLOG65 | input | TCELL2:IMUX.IMUX19.DELAY |
| CFGERRAERHEADERLOG66 | input | TCELL1:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG67 | input | TCELL1:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG68 | input | TCELL1:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG69 | input | TCELL1:IMUX.IMUX15.DELAY |
| CFGERRAERHEADERLOG7 | input | TCELL24:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG70 | input | TCELL0:IMUX.IMUX12.DELAY |
| CFGERRAERHEADERLOG71 | input | TCELL0:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG72 | input | TCELL0:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG73 | input | TCELL0:IMUX.IMUX15.DELAY |
| CFGERRAERHEADERLOG74 | input | TCELL25:IMUX.IMUX13.DELAY |
| CFGERRAERHEADERLOG75 | input | TCELL25:IMUX.IMUX14.DELAY |
| CFGERRAERHEADERLOG76 | input | TCELL25:IMUX.IMUX15.DELAY |
| CFGERRAERHEADERLOG77 | input | TCELL25:IMUX.IMUX16.DELAY |
| CFGERRAERHEADERLOG78 | input | TCELL26:IMUX.IMUX4.DELAY |
| CFGERRAERHEADERLOG79 | input | TCELL26:IMUX.IMUX5.DELAY |
| CFGERRAERHEADERLOG8 | input | TCELL24:IMUX.IMUX15.DELAY |
| CFGERRAERHEADERLOG80 | input | TCELL26:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG81 | input | TCELL26:IMUX.IMUX7.DELAY |
| CFGERRAERHEADERLOG82 | input | TCELL27:IMUX.IMUX4.DELAY |
| CFGERRAERHEADERLOG83 | input | TCELL27:IMUX.IMUX5.DELAY |
| CFGERRAERHEADERLOG84 | input | TCELL27:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG85 | input | TCELL27:IMUX.IMUX7.DELAY |
| CFGERRAERHEADERLOG86 | input | TCELL28:IMUX.IMUX4.DELAY |
| CFGERRAERHEADERLOG87 | input | TCELL28:IMUX.IMUX5.DELAY |
| CFGERRAERHEADERLOG88 | input | TCELL28:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG89 | input | TCELL28:IMUX.IMUX7.DELAY |
| CFGERRAERHEADERLOG9 | input | TCELL24:IMUX.IMUX16.DELAY |
| CFGERRAERHEADERLOG90 | input | TCELL29:IMUX.IMUX4.DELAY |
| CFGERRAERHEADERLOG91 | input | TCELL29:IMUX.IMUX5.DELAY |
| CFGERRAERHEADERLOG92 | input | TCELL29:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG93 | input | TCELL29:IMUX.IMUX7.DELAY |
| CFGERRAERHEADERLOG94 | input | TCELL30:IMUX.IMUX4.DELAY |
| CFGERRAERHEADERLOG95 | input | TCELL30:IMUX.IMUX5.DELAY |
| CFGERRAERHEADERLOG96 | input | TCELL30:IMUX.IMUX6.DELAY |
| CFGERRAERHEADERLOG97 | input | TCELL30:IMUX.IMUX7.DELAY |
| CFGERRAERHEADERLOG98 | input | TCELL31:IMUX.IMUX4.DELAY |
| CFGERRAERHEADERLOG99 | input | TCELL31:IMUX.IMUX5.DELAY |
| CFGERRAERHEADERLOGSETN | output | TCELL12:OUT17.TMIN |
| CFGERRATOMICEGRESSBLOCKEDN | input | TCELL17:IMUX.IMUX13.DELAY |
| CFGERRCORN | input | TCELL15:IMUX.IMUX9.DELAY |
| CFGERRCPLABORTN | input | TCELL16:IMUX.IMUX9.DELAY |
| CFGERRCPLRDYN | output | TCELL10:OUT14.TMIN |
| CFGERRCPLTIMEOUTN | input | TCELL15:IMUX.IMUX12.DELAY |
| CFGERRCPLUNEXPECTN | input | TCELL16:IMUX.IMUX10.DELAY |
| CFGERRECRCN | input | TCELL15:IMUX.IMUX11.DELAY |
| CFGERRINTERNALCORN | input | TCELL17:IMUX.IMUX17.DELAY |
| CFGERRINTERNALUNCORN | input | TCELL17:IMUX.IMUX15.DELAY |
| CFGERRLOCKEDN | input | TCELL22:IMUX.IMUX17.DELAY |
| CFGERRMALFORMEDN | input | TCELL14:IMUX.IMUX8.DELAY |
| CFGERRMCBLOCKEDN | input | TCELL17:IMUX.IMUX14.DELAY |
| CFGERRNORECOVERYN | input | TCELL22:IMUX.IMUX18.DELAY |
| CFGERRPOISONEDN | input | TCELL16:IMUX.IMUX11.DELAY |
| CFGERRPOSTEDN | input | TCELL18:IMUX.IMUX17.DELAY |
| CFGERRTLPCPLHEADER0 | input | TCELL38:IMUX.IMUX6.DELAY |
| CFGERRTLPCPLHEADER1 | input | TCELL38:IMUX.IMUX7.DELAY |
| CFGERRTLPCPLHEADER10 | input | TCELL41:IMUX.IMUX4.DELAY |
| CFGERRTLPCPLHEADER11 | input | TCELL41:IMUX.IMUX5.DELAY |
| CFGERRTLPCPLHEADER12 | input | TCELL41:IMUX.IMUX6.DELAY |
| CFGERRTLPCPLHEADER13 | input | TCELL41:IMUX.IMUX7.DELAY |
| CFGERRTLPCPLHEADER14 | input | TCELL42:IMUX.IMUX4.DELAY |
| CFGERRTLPCPLHEADER15 | input | TCELL42:IMUX.IMUX5.DELAY |
| CFGERRTLPCPLHEADER16 | input | TCELL42:IMUX.IMUX6.DELAY |
| CFGERRTLPCPLHEADER17 | input | TCELL42:IMUX.IMUX7.DELAY |
| CFGERRTLPCPLHEADER18 | input | TCELL43:IMUX.IMUX4.DELAY |
| CFGERRTLPCPLHEADER19 | input | TCELL43:IMUX.IMUX5.DELAY |
| CFGERRTLPCPLHEADER2 | input | TCELL39:IMUX.IMUX4.DELAY |
| CFGERRTLPCPLHEADER20 | input | TCELL43:IMUX.IMUX6.DELAY |
| CFGERRTLPCPLHEADER21 | input | TCELL43:IMUX.IMUX7.DELAY |
| CFGERRTLPCPLHEADER22 | input | TCELL44:IMUX.IMUX4.DELAY |
| CFGERRTLPCPLHEADER23 | input | TCELL44:IMUX.IMUX5.DELAY |
| CFGERRTLPCPLHEADER24 | input | TCELL44:IMUX.IMUX6.DELAY |
| CFGERRTLPCPLHEADER25 | input | TCELL44:IMUX.IMUX7.DELAY |
| CFGERRTLPCPLHEADER26 | input | TCELL45:IMUX.IMUX4.DELAY |
| CFGERRTLPCPLHEADER27 | input | TCELL45:IMUX.IMUX5.DELAY |
| CFGERRTLPCPLHEADER28 | input | TCELL45:IMUX.IMUX6.DELAY |
| CFGERRTLPCPLHEADER29 | input | TCELL45:IMUX.IMUX7.DELAY |
| CFGERRTLPCPLHEADER3 | input | TCELL39:IMUX.IMUX5.DELAY |
| CFGERRTLPCPLHEADER30 | input | TCELL46:IMUX.IMUX4.DELAY |
| CFGERRTLPCPLHEADER31 | input | TCELL46:IMUX.IMUX5.DELAY |
| CFGERRTLPCPLHEADER32 | input | TCELL46:IMUX.IMUX6.DELAY |
| CFGERRTLPCPLHEADER33 | input | TCELL46:IMUX.IMUX7.DELAY |
| CFGERRTLPCPLHEADER34 | input | TCELL47:IMUX.IMUX4.DELAY |
| CFGERRTLPCPLHEADER35 | input | TCELL47:IMUX.IMUX5.DELAY |
| CFGERRTLPCPLHEADER36 | input | TCELL47:IMUX.IMUX6.DELAY |
| CFGERRTLPCPLHEADER37 | input | TCELL47:IMUX.IMUX7.DELAY |
| CFGERRTLPCPLHEADER38 | input | TCELL48:IMUX.IMUX4.DELAY |
| CFGERRTLPCPLHEADER39 | input | TCELL48:IMUX.IMUX5.DELAY |
| CFGERRTLPCPLHEADER4 | input | TCELL39:IMUX.IMUX6.DELAY |
| CFGERRTLPCPLHEADER40 | input | TCELL48:IMUX.IMUX6.DELAY |
| CFGERRTLPCPLHEADER41 | input | TCELL48:IMUX.IMUX7.DELAY |
| CFGERRTLPCPLHEADER42 | input | TCELL49:IMUX.IMUX4.DELAY |
| CFGERRTLPCPLHEADER43 | input | TCELL49:IMUX.IMUX5.DELAY |
| CFGERRTLPCPLHEADER44 | input | TCELL49:IMUX.IMUX6.DELAY |
| CFGERRTLPCPLHEADER45 | input | TCELL49:IMUX.IMUX7.DELAY |
| CFGERRTLPCPLHEADER46 | input | TCELL24:IMUX.IMUX17.DELAY |
| CFGERRTLPCPLHEADER47 | input | TCELL24:IMUX.IMUX18.DELAY |
| CFGERRTLPCPLHEADER5 | input | TCELL39:IMUX.IMUX7.DELAY |
| CFGERRTLPCPLHEADER6 | input | TCELL40:IMUX.IMUX4.DELAY |
| CFGERRTLPCPLHEADER7 | input | TCELL40:IMUX.IMUX5.DELAY |
| CFGERRTLPCPLHEADER8 | input | TCELL40:IMUX.IMUX6.DELAY |
| CFGERRTLPCPLHEADER9 | input | TCELL40:IMUX.IMUX7.DELAY |
| CFGERRURN | input | TCELL15:IMUX.IMUX10.DELAY |
| CFGFORCECOMMONCLOCKOFF | input | TCELL30:IMUX.IMUX9.DELAY |
| CFGFORCEEXTENDEDSYNCON | input | TCELL30:IMUX.IMUX10.DELAY |
| CFGFORCEMPS0 | input | TCELL29:IMUX.IMUX10.DELAY |
| CFGFORCEMPS1 | input | TCELL29:IMUX.IMUX11.DELAY |
| CFGFORCEMPS2 | input | TCELL30:IMUX.IMUX8.DELAY |
| CFGINTERRUPTASSERTN | input | TCELL13:IMUX.IMUX16.DELAY |
| CFGINTERRUPTDI0 | input | TCELL24:IMUX.IMUX20.DELAY |
| CFGINTERRUPTDI1 | input | TCELL14:IMUX.IMUX13.DELAY |
| CFGINTERRUPTDI2 | input | TCELL14:IMUX.IMUX14.DELAY |
| CFGINTERRUPTDI3 | input | TCELL14:IMUX.IMUX15.DELAY |
| CFGINTERRUPTDI4 | input | TCELL14:IMUX.IMUX16.DELAY |
| CFGINTERRUPTDI5 | input | TCELL13:IMUX.IMUX13.DELAY |
| CFGINTERRUPTDI6 | input | TCELL13:IMUX.IMUX14.DELAY |
| CFGINTERRUPTDI7 | input | TCELL13:IMUX.IMUX15.DELAY |
| CFGINTERRUPTDO0 | output | TCELL30:OUT17.TMIN |
| CFGINTERRUPTDO1 | output | TCELL33:OUT12.TMIN |
| CFGINTERRUPTDO2 | output | TCELL33:OUT13.TMIN |
| CFGINTERRUPTDO3 | output | TCELL33:OUT14.TMIN |
| CFGINTERRUPTDO4 | output | TCELL33:OUT15.TMIN |
| CFGINTERRUPTDO5 | output | TCELL34:OUT12.TMIN |
| CFGINTERRUPTDO6 | output | TCELL34:OUT13.TMIN |
| CFGINTERRUPTDO7 | output | TCELL34:OUT14.TMIN |
| CFGINTERRUPTMMENABLE0 | output | TCELL10:OUT16.TMIN |
| CFGINTERRUPTMMENABLE1 | output | TCELL10:OUT17.TMIN |
| CFGINTERRUPTMMENABLE2 | output | TCELL26:OUT16.TMIN |
| CFGINTERRUPTMSIENABLE | output | TCELL26:OUT17.TMIN |
| CFGINTERRUPTMSIXENABLE | output | TCELL29:OUT17.TMIN |
| CFGINTERRUPTMSIXFM | output | TCELL30:OUT16.TMIN |
| CFGINTERRUPTN | input | TCELL24:IMUX.IMUX19.DELAY |
| CFGINTERRUPTRDYN | output | TCELL10:OUT15.TMIN |
| CFGINTERRUPTSTATN | input | TCELL12:IMUX.IMUX13.DELAY |
| CFGLINKCONTROLASPMCONTROL0 | output | TCELL44:OUT15.TMIN |
| CFGLINKCONTROLASPMCONTROL1 | output | TCELL45:OUT13.TMIN |
| CFGLINKCONTROLAUTOBANDWIDTHINTEN | output | TCELL47:OUT13.TMIN |
| CFGLINKCONTROLBANDWIDTHINTEN | output | TCELL47:OUT12.TMIN |
| CFGLINKCONTROLCLOCKPMEN | output | TCELL46:OUT14.TMIN |
| CFGLINKCONTROLCOMMONCLOCK | output | TCELL46:OUT12.TMIN |
| CFGLINKCONTROLEXTENDEDSYNC | output | TCELL46:OUT13.TMIN |
| CFGLINKCONTROLHWAUTOWIDTHDIS | output | TCELL46:OUT15.TMIN |
| CFGLINKCONTROLLINKDISABLE | output | TCELL45:OUT15.TMIN |
| CFGLINKCONTROLRCB | output | TCELL45:OUT14.TMIN |
| CFGLINKCONTROLRETRAINLINK | output | TCELL45:OUT17.TMIN |
| CFGLINKSTATUSAUTOBANDWIDTHSTATUS | output | TCELL44:OUT14.TMIN |
| CFGLINKSTATUSBANDWIDTHSTATUS | output | TCELL44:OUT13.TMIN |
| CFGLINKSTATUSCURRENTSPEED0 | output | TCELL41:OUT19.TMIN |
| CFGLINKSTATUSCURRENTSPEED1 | output | TCELL42:OUT20.TMIN |
| CFGLINKSTATUSDLLACTIVE | output | TCELL44:OUT12.TMIN |
| CFGLINKSTATUSLINKTRAINING | output | TCELL43:OUT21.TMIN |
| CFGLINKSTATUSNEGOTIATEDWIDTH0 | output | TCELL42:OUT21.TMIN |
| CFGLINKSTATUSNEGOTIATEDWIDTH1 | output | TCELL43:OUT18.TMIN |
| CFGLINKSTATUSNEGOTIATEDWIDTH2 | output | TCELL43:OUT19.TMIN |
| CFGLINKSTATUSNEGOTIATEDWIDTH3 | output | TCELL43:OUT20.TMIN |
| CFGMGMTBYTEENN0 | input | TCELL10:IMUX.IMUX6.DELAY |
| CFGMGMTBYTEENN1 | input | TCELL10:IMUX.IMUX7.DELAY |
| CFGMGMTBYTEENN2 | input | TCELL10:IMUX.IMUX8.DELAY |
| CFGMGMTBYTEENN3 | input | TCELL11:IMUX.IMUX5.DELAY |
| CFGMGMTDI0 | input | TCELL2:IMUX.IMUX13.DELAY |
| CFGMGMTDI1 | input | TCELL2:IMUX.IMUX14.DELAY |
| CFGMGMTDI10 | input | TCELL4:IMUX.IMUX7.DELAY |
| CFGMGMTDI11 | input | TCELL5:IMUX.IMUX7.DELAY |
| CFGMGMTDI12 | input | TCELL5:IMUX.IMUX8.DELAY |
| CFGMGMTDI13 | input | TCELL5:IMUX.IMUX9.DELAY |
| CFGMGMTDI14 | input | TCELL5:IMUX.IMUX10.DELAY |
| CFGMGMTDI15 | input | TCELL6:IMUX.IMUX9.DELAY |
| CFGMGMTDI16 | input | TCELL6:IMUX.IMUX10.DELAY |
| CFGMGMTDI17 | input | TCELL6:IMUX.IMUX11.DELAY |
| CFGMGMTDI18 | input | TCELL6:IMUX.IMUX12.DELAY |
| CFGMGMTDI19 | input | TCELL7:IMUX.IMUX10.DELAY |
| CFGMGMTDI2 | input | TCELL2:IMUX.IMUX15.DELAY |
| CFGMGMTDI20 | input | TCELL7:IMUX.IMUX11.DELAY |
| CFGMGMTDI21 | input | TCELL7:IMUX.IMUX12.DELAY |
| CFGMGMTDI22 | input | TCELL7:IMUX.IMUX13.DELAY |
| CFGMGMTDI23 | input | TCELL8:IMUX.IMUX5.DELAY |
| CFGMGMTDI24 | input | TCELL8:IMUX.IMUX6.DELAY |
| CFGMGMTDI25 | input | TCELL8:IMUX.IMUX7.DELAY |
| CFGMGMTDI26 | input | TCELL8:IMUX.IMUX8.DELAY |
| CFGMGMTDI27 | input | TCELL9:IMUX.IMUX7.DELAY |
| CFGMGMTDI28 | input | TCELL9:IMUX.IMUX8.DELAY |
| CFGMGMTDI29 | input | TCELL9:IMUX.IMUX9.DELAY |
| CFGMGMTDI3 | input | TCELL3:IMUX.IMUX9.DELAY |
| CFGMGMTDI30 | input | TCELL9:IMUX.IMUX10.DELAY |
| CFGMGMTDI31 | input | TCELL10:IMUX.IMUX5.DELAY |
| CFGMGMTDI4 | input | TCELL3:IMUX.IMUX10.DELAY |
| CFGMGMTDI5 | input | TCELL3:IMUX.IMUX11.DELAY |
| CFGMGMTDI6 | input | TCELL3:IMUX.IMUX12.DELAY |
| CFGMGMTDI7 | input | TCELL4:IMUX.IMUX4.DELAY |
| CFGMGMTDI8 | input | TCELL4:IMUX.IMUX5.DELAY |
| CFGMGMTDI9 | input | TCELL4:IMUX.IMUX6.DELAY |
| CFGMGMTDO0 | output | TCELL10:OUT11.TMIN |
| CFGMGMTDO1 | output | TCELL10:OUT12.TMIN |
| CFGMGMTDO10 | output | TCELL13:OUT15.TMIN |
| CFGMGMTDO11 | output | TCELL13:OUT17.TMIN |
| CFGMGMTDO12 | output | TCELL14:OUT12.TMIN |
| CFGMGMTDO13 | output | TCELL14:OUT14.TMIN |
| CFGMGMTDO14 | output | TCELL14:OUT16.TMIN |
| CFGMGMTDO15 | output | TCELL14:OUT17.TMIN |
| CFGMGMTDO16 | output | TCELL21:OUT21.TMIN |
| CFGMGMTDO17 | output | TCELL22:OUT16.TMIN |
| CFGMGMTDO18 | output | TCELL22:OUT17.TMIN |
| CFGMGMTDO19 | output | TCELL22:OUT19.TMIN |
| CFGMGMTDO2 | output | TCELL10:OUT13.TMIN |
| CFGMGMTDO20 | output | TCELL23:OUT11.TMIN |
| CFGMGMTDO21 | output | TCELL23:OUT12.TMIN |
| CFGMGMTDO22 | output | TCELL23:OUT13.TMIN |
| CFGMGMTDO23 | output | TCELL23:OUT15.TMIN |
| CFGMGMTDO24 | output | TCELL24:OUT13.TMIN |
| CFGMGMTDO25 | output | TCELL24:OUT14.TMIN |
| CFGMGMTDO26 | output | TCELL24:OUT15.TMIN |
| CFGMGMTDO27 | output | TCELL24:OUT16.TMIN |
| CFGMGMTDO28 | output | TCELL23:OUT16.TMIN |
| CFGMGMTDO29 | output | TCELL23:OUT17.TMIN |
| CFGMGMTDO3 | output | TCELL11:OUT13.TMIN |
| CFGMGMTDO30 | output | TCELL23:OUT18.TMIN |
| CFGMGMTDO31 | output | TCELL14:OUT18.TMIN |
| CFGMGMTDO4 | output | TCELL11:OUT14.TMIN |
| CFGMGMTDO5 | output | TCELL11:OUT15.TMIN |
| CFGMGMTDO6 | output | TCELL12:OUT8.TMIN |
| CFGMGMTDO7 | output | TCELL12:OUT10.TMIN |
| CFGMGMTDO8 | output | TCELL12:OUT12.TMIN |
| CFGMGMTDO9 | output | TCELL12:OUT14.TMIN |
| CFGMGMTDWADDR0 | input | TCELL11:IMUX.IMUX6.DELAY |
| CFGMGMTDWADDR1 | input | TCELL11:IMUX.IMUX7.DELAY |
| CFGMGMTDWADDR2 | input | TCELL11:IMUX.IMUX8.DELAY |
| CFGMGMTDWADDR3 | input | TCELL12:IMUX.IMUX5.DELAY |
| CFGMGMTDWADDR4 | input | TCELL12:IMUX.IMUX6.DELAY |
| CFGMGMTDWADDR5 | input | TCELL12:IMUX.IMUX7.DELAY |
| CFGMGMTDWADDR6 | input | TCELL12:IMUX.IMUX8.DELAY |
| CFGMGMTDWADDR7 | input | TCELL13:IMUX.IMUX5.DELAY |
| CFGMGMTDWADDR8 | input | TCELL13:IMUX.IMUX6.DELAY |
| CFGMGMTDWADDR9 | input | TCELL13:IMUX.IMUX7.DELAY |
| CFGMGMTRDENN | input | TCELL14:IMUX.IMUX7.DELAY |
| CFGMGMTRDWRDONEN | output | TCELL12:OUT16.TMIN |
| CFGMGMTWRENN | input | TCELL14:IMUX.IMUX6.DELAY |
| CFGMGMTWRREADONLYN | input | TCELL14:IMUX.IMUX5.DELAY |
| CFGMGMTWRRW1CASRWN | input | TCELL13:IMUX.IMUX8.DELAY |
| CFGMSGDATA0 | output | TCELL35:OUT12.TMIN |
| CFGMSGDATA1 | output | TCELL35:OUT13.TMIN |
| CFGMSGDATA10 | output | TCELL39:OUT12.TMIN |
| CFGMSGDATA11 | output | TCELL39:OUT14.TMIN |
| CFGMSGDATA12 | output | TCELL39:OUT16.TMIN |
| CFGMSGDATA13 | output | TCELL39:OUT17.TMIN |
| CFGMSGDATA14 | output | TCELL40:OUT12.TMIN |
| CFGMSGDATA15 | output | TCELL40:OUT13.TMIN |
| CFGMSGDATA2 | output | TCELL35:OUT14.TMIN |
| CFGMSGDATA3 | output | TCELL35:OUT15.TMIN |
| CFGMSGDATA4 | output | TCELL36:OUT17.TMIN |
| CFGMSGDATA5 | output | TCELL36:OUT18.TMIN |
| CFGMSGDATA6 | output | TCELL37:OUT16.TMIN |
| CFGMSGDATA7 | output | TCELL37:OUT17.TMIN |
| CFGMSGDATA8 | output | TCELL37:OUT18.TMIN |
| CFGMSGDATA9 | output | TCELL37:OUT19.TMIN |
| CFGMSGRECEIVED | output | TCELL34:OUT15.TMIN |
| CFGMSGRECEIVEDASSERTINTA | output | TCELL41:OUT10.TMIN |
| CFGMSGRECEIVEDASSERTINTB | output | TCELL41:OUT14.TMIN |
| CFGMSGRECEIVEDASSERTINTC | output | TCELL42:OUT17.TMIN |
| CFGMSGRECEIVEDASSERTINTD | output | TCELL42:OUT19.TMIN |
| CFGMSGRECEIVEDDEASSERTINTA | output | TCELL41:OUT12.TMIN |
| CFGMSGRECEIVEDDEASSERTINTB | output | TCELL42:OUT15.TMIN |
| CFGMSGRECEIVEDDEASSERTINTC | output | TCELL42:OUT18.TMIN |
| CFGMSGRECEIVEDDEASSERTINTD | output | TCELL43:OUT12.TMIN |
| CFGMSGRECEIVEDERRCOR | output | TCELL40:OUT14.TMIN |
| CFGMSGRECEIVEDERRFATAL | output | TCELL41:OUT8.TMIN |
| CFGMSGRECEIVEDERRNONFATAL | output | TCELL40:OUT15.TMIN |
| CFGMSGRECEIVEDPMASNAK | output | TCELL44:OUT10.TMIN |
| CFGMSGRECEIVEDPMETO | output | TCELL43:OUT17.TMIN |
| CFGMSGRECEIVEDPMETOACK | output | TCELL43:OUT16.TMIN |
| CFGMSGRECEIVEDPMPME | output | TCELL43:OUT14.TMIN |
| CFGMSGRECEIVEDSETSLOTPOWERLIMIT | output | TCELL44:OUT8.TMIN |
| CFGMSGRECEIVEDUNLOCK | output | TCELL44:OUT9.TMIN |
| CFGPCIECAPINTERRUPTMSGNUM0 | input | TCELL28:IMUX.IMUX8.DELAY |
| CFGPCIECAPINTERRUPTMSGNUM1 | input | TCELL28:IMUX.IMUX9.DELAY |
| CFGPCIECAPINTERRUPTMSGNUM2 | input | TCELL28:IMUX.IMUX10.DELAY |
| CFGPCIECAPINTERRUPTMSGNUM3 | input | TCELL28:IMUX.IMUX11.DELAY |
| CFGPCIECAPINTERRUPTMSGNUM4 | input | TCELL29:IMUX.IMUX8.DELAY |
| CFGPCIELINKSTATE0 | output | TCELL44:OUT11.TMIN |
| CFGPCIELINKSTATE1 | output | TCELL45:OUT9.TMIN |
| CFGPCIELINKSTATE2 | output | TCELL45:OUT10.TMIN |
| CFGPMCSRPMEEN | output | TCELL47:OUT8.TMIN |
| CFGPMCSRPMESTATUS | output | TCELL47:OUT9.TMIN |
| CFGPMCSRPOWERSTATE0 | output | TCELL46:OUT10.TMIN |
| CFGPMCSRPOWERSTATE1 | output | TCELL46:OUT11.TMIN |
| CFGPMFORCESTATE0 | input | TCELL26:IMUX.IMUX11.DELAY |
| CFGPMFORCESTATE1 | input | TCELL27:IMUX.IMUX8.DELAY |
| CFGPMFORCESTATEENN | input | TCELL26:IMUX.IMUX10.DELAY |
| CFGPMHALTASPML0SN | input | TCELL26:IMUX.IMUX8.DELAY |
| CFGPMHALTASPML1N | input | TCELL26:IMUX.IMUX9.DELAY |
| CFGPMRCVASREQL1N | output | TCELL45:OUT11.TMIN |
| CFGPMRCVENTERL1N | output | TCELL45:OUT12.TMIN |
| CFGPMRCVENTERL23N | output | TCELL46:OUT8.TMIN |
| CFGPMRCVREQACKN | output | TCELL46:OUT9.TMIN |
| CFGPMSENDPMETON | input | TCELL27:IMUX.IMUX11.DELAY |
| CFGPMTURNOFFOKN | input | TCELL27:IMUX.IMUX10.DELAY |
| CFGPMWAKEN | input | TCELL27:IMUX.IMUX9.DELAY |
| CFGPORTNUMBER0 | input | TCELL0:IMUX.IMUX16.DELAY |
| CFGPORTNUMBER1 | input | TCELL0:IMUX.IMUX17.DELAY |
| CFGPORTNUMBER2 | input | TCELL0:IMUX.IMUX18.DELAY |
| CFGPORTNUMBER3 | input | TCELL0:IMUX.IMUX19.DELAY |
| CFGPORTNUMBER4 | input | TCELL25:IMUX.IMUX17.DELAY |
| CFGPORTNUMBER5 | input | TCELL25:IMUX.IMUX18.DELAY |
| CFGPORTNUMBER6 | input | TCELL25:IMUX.IMUX19.DELAY |
| CFGPORTNUMBER7 | input | TCELL25:IMUX.IMUX20.DELAY |
| CFGREVID0 | input | TCELL26:IMUX.IMUX12.DELAY |
| CFGREVID1 | input | TCELL26:IMUX.IMUX13.DELAY |
| CFGREVID2 | input | TCELL26:IMUX.IMUX14.DELAY |
| CFGREVID3 | input | TCELL26:IMUX.IMUX15.DELAY |
| CFGREVID4 | input | TCELL27:IMUX.IMUX12.DELAY |
| CFGREVID5 | input | TCELL27:IMUX.IMUX13.DELAY |
| CFGREVID6 | input | TCELL27:IMUX.IMUX14.DELAY |
| CFGREVID7 | input | TCELL27:IMUX.IMUX15.DELAY |
| CFGROOTCONTROLPMEINTEN | output | TCELL44:OUT16.TMIN |
| CFGROOTCONTROLSYSERRCORRERREN | output | TCELL41:OUT20.TMIN |
| CFGROOTCONTROLSYSERRFATALERREN | output | TCELL43:OUT22.TMIN |
| CFGROOTCONTROLSYSERRNONFATALERREN | output | TCELL41:OUT21.TMIN |
| CFGSLOTCONTROLELECTROMECHILCTLPULSE | output | TCELL40:OUT22.TMIN |
| CFGSUBSYSID0 | input | TCELL28:IMUX.IMUX12.DELAY |
| CFGSUBSYSID1 | input | TCELL28:IMUX.IMUX13.DELAY |
| CFGSUBSYSID10 | input | TCELL32:IMUX.IMUX12.DELAY |
| CFGSUBSYSID11 | input | TCELL32:IMUX.IMUX13.DELAY |
| CFGSUBSYSID12 | input | TCELL32:IMUX.IMUX14.DELAY |
| CFGSUBSYSID13 | input | TCELL32:IMUX.IMUX15.DELAY |
| CFGSUBSYSID14 | input | TCELL34:IMUX.IMUX12.DELAY |
| CFGSUBSYSID15 | input | TCELL34:IMUX.IMUX13.DELAY |
| CFGSUBSYSID2 | input | TCELL28:IMUX.IMUX14.DELAY |
| CFGSUBSYSID3 | input | TCELL28:IMUX.IMUX15.DELAY |
| CFGSUBSYSID4 | input | TCELL30:IMUX.IMUX12.DELAY |
| CFGSUBSYSID5 | input | TCELL30:IMUX.IMUX13.DELAY |
| CFGSUBSYSID6 | input | TCELL31:IMUX.IMUX12.DELAY |
| CFGSUBSYSID7 | input | TCELL31:IMUX.IMUX13.DELAY |
| CFGSUBSYSID8 | input | TCELL31:IMUX.IMUX14.DELAY |
| CFGSUBSYSID9 | input | TCELL31:IMUX.IMUX15.DELAY |
| CFGSUBSYSVENDID0 | input | TCELL35:IMUX.IMUX12.DELAY |
| CFGSUBSYSVENDID1 | input | TCELL35:IMUX.IMUX13.DELAY |
| CFGSUBSYSVENDID10 | input | TCELL37:IMUX.IMUX14.DELAY |
| CFGSUBSYSVENDID11 | input | TCELL37:IMUX.IMUX15.DELAY |
| CFGSUBSYSVENDID12 | input | TCELL38:IMUX.IMUX12.DELAY |
| CFGSUBSYSVENDID13 | input | TCELL38:IMUX.IMUX13.DELAY |
| CFGSUBSYSVENDID14 | input | TCELL38:IMUX.IMUX14.DELAY |
| CFGSUBSYSVENDID15 | input | TCELL38:IMUX.IMUX15.DELAY |
| CFGSUBSYSVENDID2 | input | TCELL35:IMUX.IMUX14.DELAY |
| CFGSUBSYSVENDID3 | input | TCELL35:IMUX.IMUX15.DELAY |
| CFGSUBSYSVENDID4 | input | TCELL36:IMUX.IMUX12.DELAY |
| CFGSUBSYSVENDID5 | input | TCELL36:IMUX.IMUX13.DELAY |
| CFGSUBSYSVENDID6 | input | TCELL36:IMUX.IMUX14.DELAY |
| CFGSUBSYSVENDID7 | input | TCELL36:IMUX.IMUX15.DELAY |
| CFGSUBSYSVENDID8 | input | TCELL37:IMUX.IMUX12.DELAY |
| CFGSUBSYSVENDID9 | input | TCELL37:IMUX.IMUX13.DELAY |
| CFGTRANSACTION | output | TCELL47:OUT10.TMIN |
| CFGTRANSACTIONADDR0 | output | TCELL48:OUT8.TMIN |
| CFGTRANSACTIONADDR1 | output | TCELL48:OUT9.TMIN |
| CFGTRANSACTIONADDR2 | output | TCELL48:OUT10.TMIN |
| CFGTRANSACTIONADDR3 | output | TCELL48:OUT11.TMIN |
| CFGTRANSACTIONADDR4 | output | TCELL49:OUT8.TMIN |
| CFGTRANSACTIONADDR5 | output | TCELL49:OUT9.TMIN |
| CFGTRANSACTIONADDR6 | output | TCELL49:OUT10.TMIN |
| CFGTRANSACTIONTYPE | output | TCELL47:OUT11.TMIN |
| CFGTRNPENDINGN | input | TCELL29:IMUX.IMUX9.DELAY |
| CFGVCTCVCMAP0 | output | TCELL46:OUT17.TMIN |
| CFGVCTCVCMAP1 | output | TCELL46:OUT18.TMIN |
| CFGVCTCVCMAP2 | output | TCELL46:OUT19.TMIN |
| CFGVCTCVCMAP3 | output | TCELL47:OUT16.TMIN |
| CFGVCTCVCMAP4 | output | TCELL47:OUT17.TMIN |
| CFGVCTCVCMAP5 | output | TCELL47:OUT18.TMIN |
| CFGVCTCVCMAP6 | output | TCELL47:OUT19.TMIN |
| CFGVENDID0 | input | TCELL24:IMUX.IMUX24.DELAY |
| CFGVENDID1 | input | TCELL14:IMUX.IMUX17.DELAY |
| CFGVENDID10 | input | TCELL11:IMUX.IMUX17.DELAY |
| CFGVENDID11 | input | TCELL11:IMUX.IMUX18.DELAY |
| CFGVENDID12 | input | TCELL11:IMUX.IMUX19.DELAY |
| CFGVENDID13 | input | TCELL11:IMUX.IMUX20.DELAY |
| CFGVENDID14 | input | TCELL1:IMUX.IMUX20.DELAY |
| CFGVENDID15 | input | TCELL0:IMUX.IMUX20.DELAY |
| CFGVENDID2 | input | TCELL13:IMUX.IMUX17.DELAY |
| CFGVENDID3 | input | TCELL13:IMUX.IMUX18.DELAY |
| CFGVENDID4 | input | TCELL13:IMUX.IMUX19.DELAY |
| CFGVENDID5 | input | TCELL13:IMUX.IMUX20.DELAY |
| CFGVENDID6 | input | TCELL12:IMUX.IMUX17.DELAY |
| CFGVENDID7 | input | TCELL12:IMUX.IMUX18.DELAY |
| CFGVENDID8 | input | TCELL12:IMUX.IMUX19.DELAY |
| CFGVENDID9 | input | TCELL12:IMUX.IMUX20.DELAY |
| CMRSTN | input | TCELL0:IMUX.CTRL1 |
| CMSTICKYRSTN | input | TCELL1:IMUX.CTRL0 |
| DBGMODE0 | input | TCELL24:IMUX.IMUX25.DELAY |
| DBGMODE1 | input | TCELL13:IMUX.IMUX21.DELAY |
| DBGSCLRA | output | TCELL35:OUT19.TMIN |
| DBGSCLRB | output | TCELL35:OUT20.TMIN |
| DBGSCLRC | output | TCELL35:OUT21.TMIN |
| DBGSCLRD | output | TCELL36:OUT19.TMIN |
| DBGSCLRE | output | TCELL36:OUT20.TMIN |
| DBGSCLRF | output | TCELL36:OUT21.TMIN |
| DBGSCLRG | output | TCELL36:OUT22.TMIN |
| DBGSCLRH | output | TCELL37:OUT22.TMIN |
| DBGSCLRI | output | TCELL37:OUT23.TMIN |
| DBGSCLRJ | output | TCELL38:OUT22.TMIN |
| DBGSCLRK | output | TCELL38:OUT23.TMIN |
| DBGSUBMODE | input | TCELL12:IMUX.IMUX21.DELAY |
| DBGVECA0 | output | TCELL47:OUT21.TMIN |
| DBGVECA1 | output | TCELL47:OUT22.TMIN |
| DBGVECA10 | output | TCELL49:OUT23.TMIN |
| DBGVECA11 | output | TCELL24:OUT22.TMIN |
| DBGVECA12 | output | TCELL23:OUT20.TMIN |
| DBGVECA13 | output | TCELL23:OUT21.TMIN |
| DBGVECA14 | output | TCELL22:OUT20.TMIN |
| DBGVECA15 | output | TCELL22:OUT23.TMIN |
| DBGVECA16 | output | TCELL21:OUT22.TMIN |
| DBGVECA17 | output | TCELL21:OUT23.TMIN |
| DBGVECA18 | output | TCELL20:OUT14.TMIN |
| DBGVECA19 | output | TCELL20:OUT19.TMIN |
| DBGVECA2 | output | TCELL47:OUT23.TMIN |
| DBGVECA20 | output | TCELL20:OUT20.TMIN |
| DBGVECA21 | output | TCELL20:OUT21.TMIN |
| DBGVECA22 | output | TCELL19:OUT21.TMIN |
| DBGVECA23 | output | TCELL19:OUT22.TMIN |
| DBGVECA24 | output | TCELL19:OUT23.TMIN |
| DBGVECA25 | output | TCELL18:OUT7.TMIN |
| DBGVECA26 | output | TCELL18:OUT8.TMIN |
| DBGVECA27 | output | TCELL18:OUT20.TMIN |
| DBGVECA28 | output | TCELL18:OUT21.TMIN |
| DBGVECA29 | output | TCELL17:OUT20.TMIN |
| DBGVECA3 | output | TCELL48:OUT20.TMIN |
| DBGVECA30 | output | TCELL17:OUT21.TMIN |
| DBGVECA31 | output | TCELL17:OUT22.TMIN |
| DBGVECA32 | output | TCELL16:OUT2.TMIN |
| DBGVECA33 | output | TCELL16:OUT22.TMIN |
| DBGVECA34 | output | TCELL15:OUT10.TMIN |
| DBGVECA35 | output | TCELL15:OUT11.TMIN |
| DBGVECA36 | output | TCELL15:OUT19.TMIN |
| DBGVECA37 | output | TCELL15:OUT20.TMIN |
| DBGVECA38 | output | TCELL14:OUT19.TMIN |
| DBGVECA39 | output | TCELL14:OUT20.TMIN |
| DBGVECA4 | output | TCELL48:OUT21.TMIN |
| DBGVECA40 | output | TCELL14:OUT21.TMIN |
| DBGVECA41 | output | TCELL14:OUT22.TMIN |
| DBGVECA42 | output | TCELL13:OUT18.TMIN |
| DBGVECA43 | output | TCELL13:OUT19.TMIN |
| DBGVECA44 | output | TCELL13:OUT20.TMIN |
| DBGVECA45 | output | TCELL13:OUT21.TMIN |
| DBGVECA46 | output | TCELL12:OUT18.TMIN |
| DBGVECA47 | output | TCELL12:OUT19.TMIN |
| DBGVECA48 | output | TCELL12:OUT20.TMIN |
| DBGVECA49 | output | TCELL12:OUT21.TMIN |
| DBGVECA5 | output | TCELL48:OUT22.TMIN |
| DBGVECA50 | output | TCELL11:OUT17.TMIN |
| DBGVECA51 | output | TCELL11:OUT18.TMIN |
| DBGVECA52 | output | TCELL11:OUT20.TMIN |
| DBGVECA53 | output | TCELL11:OUT21.TMIN |
| DBGVECA54 | output | TCELL10:OUT18.TMIN |
| DBGVECA55 | output | TCELL10:OUT19.TMIN |
| DBGVECA56 | output | TCELL10:OUT20.TMIN |
| DBGVECA57 | output | TCELL10:OUT21.TMIN |
| DBGVECA58 | output | TCELL9:OUT14.TMIN |
| DBGVECA59 | output | TCELL9:OUT19.TMIN |
| DBGVECA6 | output | TCELL48:OUT23.TMIN |
| DBGVECA60 | output | TCELL9:OUT20.TMIN |
| DBGVECA61 | output | TCELL9:OUT21.TMIN |
| DBGVECA62 | output | TCELL8:OUT14.TMIN |
| DBGVECA63 | output | TCELL8:OUT15.TMIN |
| DBGVECA7 | output | TCELL49:OUT20.TMIN |
| DBGVECA8 | output | TCELL49:OUT21.TMIN |
| DBGVECA9 | output | TCELL49:OUT22.TMIN |
| DBGVECB0 | output | TCELL8:OUT16.TMIN |
| DBGVECB1 | output | TCELL8:OUT17.TMIN |
| DBGVECB10 | output | TCELL20:OUT22.TMIN |
| DBGVECB11 | output | TCELL8:OUT18.TMIN |
| DBGVECB12 | output | TCELL7:OUT10.TMIN |
| DBGVECB13 | output | TCELL7:OUT14.TMIN |
| DBGVECB14 | output | TCELL7:OUT17.TMIN |
| DBGVECB15 | output | TCELL7:OUT18.TMIN |
| DBGVECB16 | output | TCELL6:OUT9.TMIN |
| DBGVECB17 | output | TCELL6:OUT13.TMIN |
| DBGVECB18 | output | TCELL5:OUT6.TMIN |
| DBGVECB19 | output | TCELL5:OUT7.TMIN |
| DBGVECB2 | output | TCELL9:OUT22.TMIN |
| DBGVECB20 | output | TCELL5:OUT16.TMIN |
| DBGVECB21 | output | TCELL5:OUT18.TMIN |
| DBGVECB22 | output | TCELL4:OUT7.TMIN |
| DBGVECB23 | output | TCELL4:OUT8.TMIN |
| DBGVECB24 | output | TCELL4:OUT12.TMIN |
| DBGVECB25 | output | TCELL4:OUT19.TMIN |
| DBGVECB26 | output | TCELL3:OUT7.TMIN |
| DBGVECB27 | output | TCELL3:OUT8.TMIN |
| DBGVECB28 | output | TCELL3:OUT16.TMIN |
| DBGVECB29 | output | TCELL3:OUT20.TMIN |
| DBGVECB3 | output | TCELL10:OUT22.TMIN |
| DBGVECB30 | output | TCELL2:OUT12.TMIN |
| DBGVECB31 | output | TCELL2:OUT13.TMIN |
| DBGVECB32 | output | TCELL2:OUT15.TMIN |
| DBGVECB33 | output | TCELL2:OUT22.TMIN |
| DBGVECB34 | output | TCELL1:OUT22.TMIN |
| DBGVECB35 | output | TCELL0:OUT22.TMIN |
| DBGVECB36 | output | TCELL25:OUT20.TMIN |
| DBGVECB37 | output | TCELL25:OUT21.TMIN |
| DBGVECB38 | output | TCELL25:OUT22.TMIN |
| DBGVECB39 | output | TCELL26:OUT18.TMIN |
| DBGVECB4 | output | TCELL11:OUT22.TMIN |
| DBGVECB40 | output | TCELL26:OUT19.TMIN |
| DBGVECB41 | output | TCELL26:OUT20.TMIN |
| DBGVECB42 | output | TCELL26:OUT21.TMIN |
| DBGVECB43 | output | TCELL27:OUT18.TMIN |
| DBGVECB44 | output | TCELL27:OUT19.TMIN |
| DBGVECB45 | output | TCELL27:OUT20.TMIN |
| DBGVECB46 | output | TCELL27:OUT21.TMIN |
| DBGVECB47 | output | TCELL28:OUT18.TMIN |
| DBGVECB48 | output | TCELL28:OUT19.TMIN |
| DBGVECB49 | output | TCELL28:OUT20.TMIN |
| DBGVECB5 | output | TCELL12:OUT22.TMIN |
| DBGVECB50 | output | TCELL28:OUT21.TMIN |
| DBGVECB51 | output | TCELL29:OUT18.TMIN |
| DBGVECB52 | output | TCELL29:OUT19.TMIN |
| DBGVECB53 | output | TCELL29:OUT20.TMIN |
| DBGVECB54 | output | TCELL29:OUT21.TMIN |
| DBGVECB55 | output | TCELL30:OUT18.TMIN |
| DBGVECB56 | output | TCELL30:OUT19.TMIN |
| DBGVECB57 | output | TCELL30:OUT20.TMIN |
| DBGVECB58 | output | TCELL30:OUT21.TMIN |
| DBGVECB59 | output | TCELL31:OUT18.TMIN |
| DBGVECB6 | output | TCELL13:OUT22.TMIN |
| DBGVECB60 | output | TCELL31:OUT19.TMIN |
| DBGVECB61 | output | TCELL31:OUT20.TMIN |
| DBGVECB62 | output | TCELL31:OUT21.TMIN |
| DBGVECB63 | output | TCELL32:OUT18.TMIN |
| DBGVECB7 | output | TCELL14:OUT23.TMIN |
| DBGVECB8 | output | TCELL15:OUT22.TMIN |
| DBGVECB9 | output | TCELL18:OUT22.TMIN |
| DBGVECC0 | output | TCELL32:OUT19.TMIN |
| DBGVECC1 | output | TCELL32:OUT20.TMIN |
| DBGVECC10 | output | TCELL34:OUT21.TMIN |
| DBGVECC11 | output | TCELL35:OUT18.TMIN |
| DBGVECC2 | output | TCELL32:OUT21.TMIN |
| DBGVECC3 | output | TCELL33:OUT18.TMIN |
| DBGVECC4 | output | TCELL33:OUT19.TMIN |
| DBGVECC5 | output | TCELL33:OUT20.TMIN |
| DBGVECC6 | output | TCELL33:OUT21.TMIN |
| DBGVECC7 | output | TCELL34:OUT18.TMIN |
| DBGVECC8 | output | TCELL34:OUT19.TMIN |
| DBGVECC9 | output | TCELL34:OUT20.TMIN |
| DLRSTN | input | TCELL2:IMUX.CTRL1 |
| DRPADDR0 | input | TCELL42:IMUX.IMUX13.DELAY |
| DRPADDR1 | input | TCELL42:IMUX.IMUX14.DELAY |
| DRPADDR2 | input | TCELL42:IMUX.IMUX15.DELAY |
| DRPADDR3 | input | TCELL43:IMUX.IMUX12.DELAY |
| DRPADDR4 | input | TCELL43:IMUX.IMUX13.DELAY |
| DRPADDR5 | input | TCELL43:IMUX.IMUX14.DELAY |
| DRPADDR6 | input | TCELL43:IMUX.IMUX15.DELAY |
| DRPADDR7 | input | TCELL45:IMUX.IMUX12.DELAY |
| DRPADDR8 | input | TCELL45:IMUX.IMUX13.DELAY |
| DRPCLK | input | TCELL11:IMUX.CLK1 |
| DRPDI0 | input | TCELL46:IMUX.IMUX12.DELAY |
| DRPDI1 | input | TCELL46:IMUX.IMUX13.DELAY |
| DRPDI10 | input | TCELL48:IMUX.IMUX14.DELAY |
| DRPDI11 | input | TCELL48:IMUX.IMUX15.DELAY |
| DRPDI12 | input | TCELL49:IMUX.IMUX12.DELAY |
| DRPDI13 | input | TCELL49:IMUX.IMUX13.DELAY |
| DRPDI14 | input | TCELL49:IMUX.IMUX14.DELAY |
| DRPDI15 | input | TCELL49:IMUX.IMUX15.DELAY |
| DRPDI2 | input | TCELL46:IMUX.IMUX14.DELAY |
| DRPDI3 | input | TCELL46:IMUX.IMUX15.DELAY |
| DRPDI4 | input | TCELL47:IMUX.IMUX12.DELAY |
| DRPDI5 | input | TCELL47:IMUX.IMUX13.DELAY |
| DRPDI6 | input | TCELL47:IMUX.IMUX14.DELAY |
| DRPDI7 | input | TCELL47:IMUX.IMUX15.DELAY |
| DRPDI8 | input | TCELL48:IMUX.IMUX12.DELAY |
| DRPDI9 | input | TCELL48:IMUX.IMUX13.DELAY |
| DRPDO0 | output | TCELL48:OUT17.TMIN |
| DRPDO1 | output | TCELL48:OUT18.TMIN |
| DRPDO10 | output | TCELL44:OUT23.TMIN |
| DRPDO11 | output | TCELL46:OUT20.TMIN |
| DRPDO12 | output | TCELL46:OUT21.TMIN |
| DRPDO13 | output | TCELL46:OUT22.TMIN |
| DRPDO14 | output | TCELL46:OUT23.TMIN |
| DRPDO15 | output | TCELL47:OUT20.TMIN |
| DRPDO2 | output | TCELL48:OUT19.TMIN |
| DRPDO3 | output | TCELL49:OUT16.TMIN |
| DRPDO4 | output | TCELL49:OUT17.TMIN |
| DRPDO5 | output | TCELL49:OUT18.TMIN |
| DRPDO6 | output | TCELL49:OUT19.TMIN |
| DRPDO7 | output | TCELL44:OUT20.TMIN |
| DRPDO8 | output | TCELL44:OUT21.TMIN |
| DRPDO9 | output | TCELL44:OUT22.TMIN |
| DRPEN | input | TCELL41:IMUX.IMUX13.DELAY |
| DRPRDY | output | TCELL48:OUT16.TMIN |
| DRPWE | input | TCELL42:IMUX.IMUX12.DELAY |
| EDTBYPASS | input | TCELL21:IMUX.IMUX17.DELAY |
| EDTCHANNELSIN1 | input | TCELL18:IMUX.IMUX16.DELAY |
| EDTCHANNELSIN2 | input | TCELL17:IMUX.IMUX12.DELAY |
| EDTCHANNELSIN3 | input | TCELL16:IMUX.IMUX8.DELAY |
| EDTCHANNELSIN4 | input | TCELL15:IMUX.IMUX8.DELAY |
| EDTCHANNELSIN5 | input | TCELL14:IMUX.IMUX4.DELAY |
| EDTCHANNELSIN6 | input | TCELL13:IMUX.IMUX4.DELAY |
| EDTCHANNELSIN7 | input | TCELL12:IMUX.IMUX4.DELAY |
| EDTCHANNELSIN8 | input | TCELL11:IMUX.IMUX4.DELAY |
| EDTCHANNELSOUT1 | output | TCELL0:OUT15.TMIN |
| EDTCHANNELSOUT2 | output | TCELL0:OUT19.TMIN |
| EDTCHANNELSOUT3 | output | TCELL0:OUT20.TMIN |
| EDTCHANNELSOUT4 | output | TCELL0:OUT21.TMIN |
| EDTCHANNELSOUT5 | output | TCELL1:OUT17.TMIN |
| EDTCHANNELSOUT6 | output | TCELL1:OUT18.TMIN |
| EDTCHANNELSOUT7 | output | TCELL1:OUT20.TMIN |
| EDTCHANNELSOUT8 | output | TCELL1:OUT21.TMIN |
| EDTCLK | input | TCELL10:IMUX.CLK0 |
| EDTCONFIGURATION | input | TCELL20:IMUX.IMUX14.DELAY |
| EDTSINGLEBYPASSCHAIN | input | TCELL19:IMUX.IMUX12.DELAY |
| EDTUPDATE | input | TCELL22:IMUX.IMUX16.DELAY |
| FUNCLVLRSTN | input | TCELL1:IMUX.CTRL1 |
| LL2BADDLLPERR | output | TCELL13:OUT14.TMIN |
| LL2BADTLPERR | output | TCELL13:OUT13.TMIN |
| LL2LINKSTATUS0 | output | TCELL17:OUT15.TMIN |
| LL2LINKSTATUS1 | output | TCELL17:OUT19.TMIN |
| LL2LINKSTATUS2 | output | TCELL16:OUT3.TMIN |
| LL2LINKSTATUS3 | output | TCELL16:OUT4.TMIN |
| LL2LINKSTATUS4 | output | TCELL16:OUT20.TMIN |
| LL2PROTOCOLERR | output | TCELL13:OUT12.TMIN |
| LL2RECEIVERERR | output | TCELL13:OUT11.TMIN |
| LL2REPLAYROERR | output | TCELL12:OUT4.TMIN |
| LL2REPLAYTOERR | output | TCELL12:OUT5.TMIN |
| LL2SENDASREQL1 | input | TCELL49:IMUX.IMUX1.DELAY |
| LL2SENDENTERL1 | input | TCELL48:IMUX.IMUX3.DELAY |
| LL2SENDENTERL23 | input | TCELL49:IMUX.IMUX0.DELAY |
| LL2SENDPMACK | input | TCELL49:IMUX.IMUX2.DELAY |
| LL2SUSPENDNOW | input | TCELL23:IMUX.IMUX16.DELAY |
| LL2SUSPENDOK | output | TCELL17:OUT12.TMIN |
| LL2TFCINIT1SEQ | output | TCELL21:OUT16.TMIN |
| LL2TFCINIT2SEQ | output | TCELL21:OUT20.TMIN |
| LL2TLPRCV | input | TCELL48:IMUX.IMUX2.DELAY |
| LL2TXIDLE | output | TCELL17:OUT13.TMIN |
| LNKCLKEN | output | TCELL10:OUT10.TMIN |
| MIMRXRADDR0 | output | TCELL22:OUT13.TMIN |
| MIMRXRADDR1 | output | TCELL21:OUT11.TMIN |
| MIMRXRADDR10 | output | TCELL20:OUT3.TMIN |
| MIMRXRADDR11 | output | TCELL20:OUT10.TMIN |
| MIMRXRADDR12 | output | TCELL15:OUT21.TMIN |
| MIMRXRADDR2 | output | TCELL22:OUT12.TMIN |
| MIMRXRADDR3 | output | TCELL18:OUT16.TMIN |
| MIMRXRADDR4 | output | TCELL22:OUT5.TMIN |
| MIMRXRADDR5 | output | TCELL19:OUT8.TMIN |
| MIMRXRADDR6 | output | TCELL19:OUT9.TMIN |
| MIMRXRADDR7 | output | TCELL19:OUT15.TMIN |
| MIMRXRADDR8 | output | TCELL20:OUT17.TMIN |
| MIMRXRADDR9 | output | TCELL20:OUT8.TMIN |
| MIMRXRDATA0 | input | TCELL15:IMUX.IMUX0.DELAY |
| MIMRXRDATA1 | input | TCELL15:IMUX.IMUX1.DELAY |
| MIMRXRDATA10 | input | TCELL17:IMUX.IMUX2.DELAY |
| MIMRXRDATA11 | input | TCELL17:IMUX.IMUX3.DELAY |
| MIMRXRDATA12 | input | TCELL18:IMUX.IMUX0.DELAY |
| MIMRXRDATA13 | input | TCELL18:IMUX.IMUX1.DELAY |
| MIMRXRDATA14 | input | TCELL18:IMUX.IMUX2.DELAY |
| MIMRXRDATA15 | input | TCELL18:IMUX.IMUX3.DELAY |
| MIMRXRDATA16 | input | TCELL19:IMUX.IMUX0.DELAY |
| MIMRXRDATA17 | input | TCELL19:IMUX.IMUX1.DELAY |
| MIMRXRDATA18 | input | TCELL19:IMUX.IMUX2.DELAY |
| MIMRXRDATA19 | input | TCELL19:IMUX.IMUX3.DELAY |
| MIMRXRDATA2 | input | TCELL15:IMUX.IMUX2.DELAY |
| MIMRXRDATA20 | input | TCELL20:IMUX.IMUX0.DELAY |
| MIMRXRDATA21 | input | TCELL20:IMUX.IMUX1.DELAY |
| MIMRXRDATA22 | input | TCELL20:IMUX.IMUX2.DELAY |
| MIMRXRDATA23 | input | TCELL20:IMUX.IMUX3.DELAY |
| MIMRXRDATA24 | input | TCELL21:IMUX.IMUX0.DELAY |
| MIMRXRDATA25 | input | TCELL21:IMUX.IMUX1.DELAY |
| MIMRXRDATA26 | input | TCELL21:IMUX.IMUX2.DELAY |
| MIMRXRDATA27 | input | TCELL21:IMUX.IMUX3.DELAY |
| MIMRXRDATA28 | input | TCELL22:IMUX.IMUX0.DELAY |
| MIMRXRDATA29 | input | TCELL22:IMUX.IMUX1.DELAY |
| MIMRXRDATA3 | input | TCELL15:IMUX.IMUX3.DELAY |
| MIMRXRDATA30 | input | TCELL22:IMUX.IMUX2.DELAY |
| MIMRXRDATA31 | input | TCELL22:IMUX.IMUX3.DELAY |
| MIMRXRDATA32 | input | TCELL23:IMUX.IMUX0.DELAY |
| MIMRXRDATA33 | input | TCELL23:IMUX.IMUX1.DELAY |
| MIMRXRDATA34 | input | TCELL23:IMUX.IMUX2.DELAY |
| MIMRXRDATA35 | input | TCELL23:IMUX.IMUX3.DELAY |
| MIMRXRDATA36 | input | TCELL24:IMUX.IMUX0.DELAY |
| MIMRXRDATA37 | input | TCELL24:IMUX.IMUX1.DELAY |
| MIMRXRDATA38 | input | TCELL24:IMUX.IMUX2.DELAY |
| MIMRXRDATA39 | input | TCELL24:IMUX.IMUX3.DELAY |
| MIMRXRDATA4 | input | TCELL16:IMUX.IMUX0.DELAY |
| MIMRXRDATA40 | input | TCELL23:IMUX.IMUX4.DELAY |
| MIMRXRDATA41 | input | TCELL23:IMUX.IMUX5.DELAY |
| MIMRXRDATA42 | input | TCELL23:IMUX.IMUX6.DELAY |
| MIMRXRDATA43 | input | TCELL23:IMUX.IMUX7.DELAY |
| MIMRXRDATA44 | input | TCELL22:IMUX.IMUX4.DELAY |
| MIMRXRDATA45 | input | TCELL22:IMUX.IMUX5.DELAY |
| MIMRXRDATA46 | input | TCELL22:IMUX.IMUX6.DELAY |
| MIMRXRDATA47 | input | TCELL22:IMUX.IMUX7.DELAY |
| MIMRXRDATA48 | input | TCELL21:IMUX.IMUX4.DELAY |
| MIMRXRDATA49 | input | TCELL21:IMUX.IMUX5.DELAY |
| MIMRXRDATA5 | input | TCELL16:IMUX.IMUX1.DELAY |
| MIMRXRDATA50 | input | TCELL21:IMUX.IMUX6.DELAY |
| MIMRXRDATA51 | input | TCELL21:IMUX.IMUX7.DELAY |
| MIMRXRDATA52 | input | TCELL20:IMUX.IMUX4.DELAY |
| MIMRXRDATA53 | input | TCELL20:IMUX.IMUX5.DELAY |
| MIMRXRDATA54 | input | TCELL20:IMUX.IMUX6.DELAY |
| MIMRXRDATA55 | input | TCELL20:IMUX.IMUX7.DELAY |
| MIMRXRDATA56 | input | TCELL19:IMUX.IMUX4.DELAY |
| MIMRXRDATA57 | input | TCELL19:IMUX.IMUX5.DELAY |
| MIMRXRDATA58 | input | TCELL19:IMUX.IMUX6.DELAY |
| MIMRXRDATA59 | input | TCELL19:IMUX.IMUX7.DELAY |
| MIMRXRDATA6 | input | TCELL16:IMUX.IMUX2.DELAY |
| MIMRXRDATA60 | input | TCELL18:IMUX.IMUX4.DELAY |
| MIMRXRDATA61 | input | TCELL18:IMUX.IMUX5.DELAY |
| MIMRXRDATA62 | input | TCELL18:IMUX.IMUX6.DELAY |
| MIMRXRDATA63 | input | TCELL18:IMUX.IMUX7.DELAY |
| MIMRXRDATA64 | input | TCELL17:IMUX.IMUX4.DELAY |
| MIMRXRDATA65 | input | TCELL17:IMUX.IMUX5.DELAY |
| MIMRXRDATA66 | input | TCELL17:IMUX.IMUX6.DELAY |
| MIMRXRDATA67 | input | TCELL17:IMUX.IMUX7.DELAY |
| MIMRXRDATA7 | input | TCELL16:IMUX.IMUX3.DELAY |
| MIMRXRDATA8 | input | TCELL17:IMUX.IMUX0.DELAY |
| MIMRXRDATA9 | input | TCELL17:IMUX.IMUX1.DELAY |
| MIMRXREN | output | TCELL21:OUT12.TMIN |
| MIMRXWADDR0 | output | TCELL19:OUT14.TMIN |
| MIMRXWADDR1 | output | TCELL21:OUT15.TMIN |
| MIMRXWADDR10 | output | TCELL16:OUT12.TMIN |
| MIMRXWADDR11 | output | TCELL16:OUT14.TMIN |
| MIMRXWADDR12 | output | TCELL20:OUT1.TMIN |
| MIMRXWADDR2 | output | TCELL22:OUT0.TMIN |
| MIMRXWADDR3 | output | TCELL16:OUT7.TMIN |
| MIMRXWADDR4 | output | TCELL19:OUT16.TMIN |
| MIMRXWADDR5 | output | TCELL21:OUT9.TMIN |
| MIMRXWADDR6 | output | TCELL17:OUT17.TMIN |
| MIMRXWADDR7 | output | TCELL19:OUT11.TMIN |
| MIMRXWADDR8 | output | TCELL16:OUT8.TMIN |
| MIMRXWADDR9 | output | TCELL19:OUT17.TMIN |
| MIMRXWDATA0 | output | TCELL20:OUT11.TMIN |
| MIMRXWDATA1 | output | TCELL20:OUT13.TMIN |
| MIMRXWDATA10 | output | TCELL21:OUT19.TMIN |
| MIMRXWDATA11 | output | TCELL24:OUT18.TMIN |
| MIMRXWDATA12 | output | TCELL21:OUT2.TMIN |
| MIMRXWDATA13 | output | TCELL24:OUT9.TMIN |
| MIMRXWDATA14 | output | TCELL18:OUT4.TMIN |
| MIMRXWDATA15 | output | TCELL24:OUT10.TMIN |
| MIMRXWDATA16 | output | TCELL19:OUT0.TMIN |
| MIMRXWDATA17 | output | TCELL22:OUT9.TMIN |
| MIMRXWDATA18 | output | TCELL19:OUT2.TMIN |
| MIMRXWDATA19 | output | TCELL23:OUT8.TMIN |
| MIMRXWDATA2 | output | TCELL20:OUT18.TMIN |
| MIMRXWDATA20 | output | TCELL20:OUT0.TMIN |
| MIMRXWDATA21 | output | TCELL23:OUT19.TMIN |
| MIMRXWDATA22 | output | TCELL20:OUT15.TMIN |
| MIMRXWDATA23 | output | TCELL23:OUT14.TMIN |
| MIMRXWDATA24 | output | TCELL21:OUT0.TMIN |
| MIMRXWDATA25 | output | TCELL23:OUT10.TMIN |
| MIMRXWDATA26 | output | TCELL21:OUT13.TMIN |
| MIMRXWDATA27 | output | TCELL24:OUT19.TMIN |
| MIMRXWDATA28 | output | TCELL22:OUT14.TMIN |
| MIMRXWDATA29 | output | TCELL24:OUT8.TMIN |
| MIMRXWDATA3 | output | TCELL22:OUT15.TMIN |
| MIMRXWDATA30 | output | TCELL22:OUT18.TMIN |
| MIMRXWDATA31 | output | TCELL22:OUT21.TMIN |
| MIMRXWDATA32 | output | TCELL22:OUT1.TMIN |
| MIMRXWDATA33 | output | TCELL22:OUT22.TMIN |
| MIMRXWDATA34 | output | TCELL21:OUT17.TMIN |
| MIMRXWDATA35 | output | TCELL24:OUT11.TMIN |
| MIMRXWDATA36 | output | TCELL15:OUT17.TMIN |
| MIMRXWDATA37 | output | TCELL15:OUT9.TMIN |
| MIMRXWDATA38 | output | TCELL15:OUT12.TMIN |
| MIMRXWDATA39 | output | TCELL17:OUT23.TMIN |
| MIMRXWDATA4 | output | TCELL20:OUT9.TMIN |
| MIMRXWDATA40 | output | TCELL15:OUT13.TMIN |
| MIMRXWDATA41 | output | TCELL18:OUT18.TMIN |
| MIMRXWDATA42 | output | TCELL15:OUT14.TMIN |
| MIMRXWDATA43 | output | TCELL18:OUT19.TMIN |
| MIMRXWDATA44 | output | TCELL16:OUT18.TMIN |
| MIMRXWDATA45 | output | TCELL18:OUT17.TMIN |
| MIMRXWDATA46 | output | TCELL16:OUT23.TMIN |
| MIMRXWDATA47 | output | TCELL19:OUT18.TMIN |
| MIMRXWDATA48 | output | TCELL16:OUT16.TMIN |
| MIMRXWDATA49 | output | TCELL21:OUT5.TMIN |
| MIMRXWDATA5 | output | TCELL23:OUT22.TMIN |
| MIMRXWDATA50 | output | TCELL16:OUT17.TMIN |
| MIMRXWDATA51 | output | TCELL21:OUT7.TMIN |
| MIMRXWDATA52 | output | TCELL15:OUT18.TMIN |
| MIMRXWDATA53 | output | TCELL17:OUT11.TMIN |
| MIMRXWDATA54 | output | TCELL16:OUT5.TMIN |
| MIMRXWDATA55 | output | TCELL18:OUT12.TMIN |
| MIMRXWDATA56 | output | TCELL16:OUT6.TMIN |
| MIMRXWDATA57 | output | TCELL19:OUT5.TMIN |
| MIMRXWDATA58 | output | TCELL15:OUT15.TMIN |
| MIMRXWDATA59 | output | TCELL18:OUT14.TMIN |
| MIMRXWDATA6 | output | TCELL20:OUT16.TMIN |
| MIMRXWDATA60 | output | TCELL18:OUT6.TMIN |
| MIMRXWDATA61 | output | TCELL19:OUT12.TMIN |
| MIMRXWDATA62 | output | TCELL16:OUT19.TMIN |
| MIMRXWDATA63 | output | TCELL18:OUT10.TMIN |
| MIMRXWDATA64 | output | TCELL16:OUT10.TMIN |
| MIMRXWDATA65 | output | TCELL19:OUT10.TMIN |
| MIMRXWDATA66 | output | TCELL17:OUT18.TMIN |
| MIMRXWDATA67 | output | TCELL17:OUT14.TMIN |
| MIMRXWDATA7 | output | TCELL23:OUT23.TMIN |
| MIMRXWDATA8 | output | TCELL21:OUT8.TMIN |
| MIMRXWDATA9 | output | TCELL23:OUT3.TMIN |
| MIMRXWEN | output | TCELL21:OUT18.TMIN |
| MIMTXRADDR0 | output | TCELL4:OUT20.TMIN |
| MIMTXRADDR1 | output | TCELL6:OUT11.TMIN |
| MIMTXRADDR10 | output | TCELL9:OUT8.TMIN |
| MIMTXRADDR11 | output | TCELL5:OUT8.TMIN |
| MIMTXRADDR12 | output | TCELL7:OUT8.TMIN |
| MIMTXRADDR2 | output | TCELL7:OUT22.TMIN |
| MIMTXRADDR3 | output | TCELL2:OUT10.TMIN |
| MIMTXRADDR4 | output | TCELL4:OUT14.TMIN |
| MIMTXRADDR5 | output | TCELL6:OUT19.TMIN |
| MIMTXRADDR6 | output | TCELL2:OUT17.TMIN |
| MIMTXRADDR7 | output | TCELL4:OUT17.TMIN |
| MIMTXRADDR8 | output | TCELL3:OUT22.TMIN |
| MIMTXRADDR9 | output | TCELL4:OUT3.TMIN |
| MIMTXRDATA0 | input | TCELL0:IMUX.IMUX0.DELAY |
| MIMTXRDATA1 | input | TCELL0:IMUX.IMUX1.DELAY |
| MIMTXRDATA10 | input | TCELL2:IMUX.IMUX2.DELAY |
| MIMTXRDATA11 | input | TCELL2:IMUX.IMUX3.DELAY |
| MIMTXRDATA12 | input | TCELL3:IMUX.IMUX0.DELAY |
| MIMTXRDATA13 | input | TCELL3:IMUX.IMUX1.DELAY |
| MIMTXRDATA14 | input | TCELL3:IMUX.IMUX2.DELAY |
| MIMTXRDATA15 | input | TCELL3:IMUX.IMUX3.DELAY |
| MIMTXRDATA16 | input | TCELL4:IMUX.IMUX0.DELAY |
| MIMTXRDATA17 | input | TCELL4:IMUX.IMUX1.DELAY |
| MIMTXRDATA18 | input | TCELL4:IMUX.IMUX2.DELAY |
| MIMTXRDATA19 | input | TCELL4:IMUX.IMUX3.DELAY |
| MIMTXRDATA2 | input | TCELL0:IMUX.IMUX2.DELAY |
| MIMTXRDATA20 | input | TCELL5:IMUX.IMUX0.DELAY |
| MIMTXRDATA21 | input | TCELL5:IMUX.IMUX1.DELAY |
| MIMTXRDATA22 | input | TCELL5:IMUX.IMUX2.DELAY |
| MIMTXRDATA23 | input | TCELL5:IMUX.IMUX3.DELAY |
| MIMTXRDATA24 | input | TCELL6:IMUX.IMUX0.DELAY |
| MIMTXRDATA25 | input | TCELL6:IMUX.IMUX1.DELAY |
| MIMTXRDATA26 | input | TCELL6:IMUX.IMUX2.DELAY |
| MIMTXRDATA27 | input | TCELL6:IMUX.IMUX3.DELAY |
| MIMTXRDATA28 | input | TCELL7:IMUX.IMUX0.DELAY |
| MIMTXRDATA29 | input | TCELL7:IMUX.IMUX1.DELAY |
| MIMTXRDATA3 | input | TCELL0:IMUX.IMUX3.DELAY |
| MIMTXRDATA30 | input | TCELL7:IMUX.IMUX2.DELAY |
| MIMTXRDATA31 | input | TCELL7:IMUX.IMUX3.DELAY |
| MIMTXRDATA32 | input | TCELL8:IMUX.IMUX0.DELAY |
| MIMTXRDATA33 | input | TCELL8:IMUX.IMUX1.DELAY |
| MIMTXRDATA34 | input | TCELL8:IMUX.IMUX2.DELAY |
| MIMTXRDATA35 | input | TCELL8:IMUX.IMUX3.DELAY |
| MIMTXRDATA36 | input | TCELL9:IMUX.IMUX0.DELAY |
| MIMTXRDATA37 | input | TCELL9:IMUX.IMUX1.DELAY |
| MIMTXRDATA38 | input | TCELL9:IMUX.IMUX2.DELAY |
| MIMTXRDATA39 | input | TCELL9:IMUX.IMUX3.DELAY |
| MIMTXRDATA4 | input | TCELL1:IMUX.IMUX0.DELAY |
| MIMTXRDATA40 | input | TCELL7:IMUX.IMUX4.DELAY |
| MIMTXRDATA41 | input | TCELL7:IMUX.IMUX5.DELAY |
| MIMTXRDATA42 | input | TCELL7:IMUX.IMUX6.DELAY |
| MIMTXRDATA43 | input | TCELL7:IMUX.IMUX7.DELAY |
| MIMTXRDATA44 | input | TCELL6:IMUX.IMUX4.DELAY |
| MIMTXRDATA45 | input | TCELL6:IMUX.IMUX5.DELAY |
| MIMTXRDATA46 | input | TCELL6:IMUX.IMUX6.DELAY |
| MIMTXRDATA47 | input | TCELL6:IMUX.IMUX7.DELAY |
| MIMTXRDATA48 | input | TCELL5:IMUX.IMUX4.DELAY |
| MIMTXRDATA49 | input | TCELL5:IMUX.IMUX5.DELAY |
| MIMTXRDATA5 | input | TCELL1:IMUX.IMUX1.DELAY |
| MIMTXRDATA50 | input | TCELL3:IMUX.IMUX4.DELAY |
| MIMTXRDATA51 | input | TCELL3:IMUX.IMUX5.DELAY |
| MIMTXRDATA52 | input | TCELL3:IMUX.IMUX6.DELAY |
| MIMTXRDATA53 | input | TCELL3:IMUX.IMUX7.DELAY |
| MIMTXRDATA54 | input | TCELL2:IMUX.IMUX4.DELAY |
| MIMTXRDATA55 | input | TCELL2:IMUX.IMUX5.DELAY |
| MIMTXRDATA56 | input | TCELL2:IMUX.IMUX6.DELAY |
| MIMTXRDATA57 | input | TCELL2:IMUX.IMUX7.DELAY |
| MIMTXRDATA58 | input | TCELL1:IMUX.IMUX4.DELAY |
| MIMTXRDATA59 | input | TCELL1:IMUX.IMUX5.DELAY |
| MIMTXRDATA6 | input | TCELL1:IMUX.IMUX2.DELAY |
| MIMTXRDATA60 | input | TCELL1:IMUX.IMUX6.DELAY |
| MIMTXRDATA61 | input | TCELL1:IMUX.IMUX7.DELAY |
| MIMTXRDATA62 | input | TCELL0:IMUX.IMUX4.DELAY |
| MIMTXRDATA63 | input | TCELL0:IMUX.IMUX5.DELAY |
| MIMTXRDATA64 | input | TCELL0:IMUX.IMUX6.DELAY |
| MIMTXRDATA65 | input | TCELL0:IMUX.IMUX7.DELAY |
| MIMTXRDATA66 | input | TCELL9:IMUX.IMUX4.DELAY |
| MIMTXRDATA67 | input | TCELL9:IMUX.IMUX5.DELAY |
| MIMTXRDATA68 | input | TCELL7:IMUX.IMUX8.DELAY |
| MIMTXRDATA7 | input | TCELL1:IMUX.IMUX3.DELAY |
| MIMTXRDATA8 | input | TCELL2:IMUX.IMUX0.DELAY |
| MIMTXRDATA9 | input | TCELL2:IMUX.IMUX1.DELAY |
| MIMTXREN | output | TCELL6:OUT8.TMIN |
| MIMTXWADDR0 | output | TCELL7:OUT23.TMIN |
| MIMTXWADDR1 | output | TCELL1:OUT6.TMIN |
| MIMTXWADDR10 | output | TCELL8:OUT23.TMIN |
| MIMTXWADDR11 | output | TCELL3:OUT2.TMIN |
| MIMTXWADDR12 | output | TCELL1:OUT10.TMIN |
| MIMTXWADDR2 | output | TCELL7:OUT12.TMIN |
| MIMTXWADDR3 | output | TCELL5:OUT23.TMIN |
| MIMTXWADDR4 | output | TCELL4:OUT10.TMIN |
| MIMTXWADDR5 | output | TCELL3:OUT14.TMIN |
| MIMTXWADDR6 | output | TCELL2:OUT11.TMIN |
| MIMTXWADDR7 | output | TCELL4:OUT15.TMIN |
| MIMTXWADDR8 | output | TCELL3:OUT12.TMIN |
| MIMTXWADDR9 | output | TCELL4:OUT21.TMIN |
| MIMTXWDATA0 | output | TCELL5:OUT17.TMIN |
| MIMTXWDATA1 | output | TCELL5:OUT19.TMIN |
| MIMTXWDATA10 | output | TCELL6:OUT23.TMIN |
| MIMTXWDATA11 | output | TCELL9:OUT18.TMIN |
| MIMTXWDATA12 | output | TCELL6:OUT10.TMIN |
| MIMTXWDATA13 | output | TCELL9:OUT5.TMIN |
| MIMTXWDATA14 | output | TCELL6:OUT21.TMIN |
| MIMTXWDATA15 | output | TCELL9:OUT16.TMIN |
| MIMTXWDATA16 | output | TCELL4:OUT1.TMIN |
| MIMTXWDATA17 | output | TCELL7:OUT5.TMIN |
| MIMTXWDATA18 | output | TCELL5:OUT1.TMIN |
| MIMTXWDATA19 | output | TCELL8:OUT4.TMIN |
| MIMTXWDATA2 | output | TCELL5:OUT12.TMIN |
| MIMTXWDATA20 | output | TCELL5:OUT0.TMIN |
| MIMTXWDATA21 | output | TCELL8:OUT5.TMIN |
| MIMTXWDATA22 | output | TCELL6:OUT17.TMIN |
| MIMTXWDATA23 | output | TCELL8:OUT20.TMIN |
| MIMTXWDATA24 | output | TCELL6:OUT18.TMIN |
| MIMTXWDATA25 | output | TCELL8:OUT10.TMIN |
| MIMTXWDATA26 | output | TCELL6:OUT5.TMIN |
| MIMTXWDATA27 | output | TCELL9:OUT13.TMIN |
| MIMTXWDATA28 | output | TCELL7:OUT16.TMIN |
| MIMTXWDATA29 | output | TCELL10:OUT2.TMIN |
| MIMTXWDATA3 | output | TCELL7:OUT7.TMIN |
| MIMTXWDATA30 | output | TCELL6:OUT20.TMIN |
| MIMTXWDATA31 | output | TCELL9:OUT7.TMIN |
| MIMTXWDATA32 | output | TCELL7:OUT19.TMIN |
| MIMTXWDATA33 | output | TCELL7:OUT4.TMIN |
| MIMTXWDATA34 | output | TCELL6:OUT15.TMIN |
| MIMTXWDATA35 | output | TCELL9:OUT17.TMIN |
| MIMTXWDATA36 | output | TCELL0:OUT11.TMIN |
| MIMTXWDATA37 | output | TCELL0:OUT9.TMIN |
| MIMTXWDATA38 | output | TCELL0:OUT18.TMIN |
| MIMTXWDATA39 | output | TCELL2:OUT21.TMIN |
| MIMTXWDATA4 | output | TCELL5:OUT5.TMIN |
| MIMTXWDATA40 | output | TCELL0:OUT1.TMIN |
| MIMTXWDATA41 | output | TCELL3:OUT18.TMIN |
| MIMTXWDATA42 | output | TCELL0:OUT14.TMIN |
| MIMTXWDATA43 | output | TCELL3:OUT19.TMIN |
| MIMTXWDATA44 | output | TCELL1:OUT8.TMIN |
| MIMTXWDATA45 | output | TCELL3:OUT17.TMIN |
| MIMTXWDATA46 | output | TCELL1:OUT19.TMIN |
| MIMTXWDATA47 | output | TCELL4:OUT18.TMIN |
| MIMTXWDATA48 | output | TCELL1:OUT14.TMIN |
| MIMTXWDATA49 | output | TCELL4:OUT13.TMIN |
| MIMTXWDATA5 | output | TCELL9:OUT4.TMIN |
| MIMTXWDATA50 | output | TCELL1:OUT7.TMIN |
| MIMTXWDATA51 | output | TCELL5:OUT14.TMIN |
| MIMTXWDATA52 | output | TCELL0:OUT12.TMIN |
| MIMTXWDATA53 | output | TCELL2:OUT19.TMIN |
| MIMTXWDATA54 | output | TCELL0:OUT13.TMIN |
| MIMTXWDATA55 | output | TCELL2:OUT20.TMIN |
| MIMTXWDATA56 | output | TCELL0:OUT10.TMIN |
| MIMTXWDATA57 | output | TCELL4:OUT9.TMIN |
| MIMTXWDATA58 | output | TCELL0:OUT17.TMIN |
| MIMTXWDATA59 | output | TCELL4:OUT11.TMIN |
| MIMTXWDATA6 | output | TCELL5:OUT20.TMIN |
| MIMTXWDATA60 | output | TCELL1:OUT12.TMIN |
| MIMTXWDATA61 | output | TCELL3:OUT6.TMIN |
| MIMTXWDATA62 | output | TCELL1:OUT5.TMIN |
| MIMTXWDATA63 | output | TCELL3:OUT10.TMIN |
| MIMTXWDATA64 | output | TCELL1:OUT16.TMIN |
| MIMTXWDATA65 | output | TCELL5:OUT10.TMIN |
| MIMTXWDATA66 | output | TCELL2:OUT18.TMIN |
| MIMTXWDATA67 | output | TCELL2:OUT14.TMIN |
| MIMTXWDATA68 | output | TCELL2:OUT5.TMIN |
| MIMTXWDATA7 | output | TCELL8:OUT19.TMIN |
| MIMTXWDATA8 | output | TCELL6:OUT22.TMIN |
| MIMTXWDATA9 | output | TCELL8:OUT21.TMIN |
| MIMTXWEN | output | TCELL6:OUT12.TMIN |
| PIPECLK | input | TCELL11:IMUX.CLK0 |
| PIPERX0CHANISALIGNED | input | TCELL45:IMUX.IMUX33.DELAY |
| PIPERX0CHARISK0 | input | TCELL46:IMUX.IMUX16.DELAY |
| PIPERX0CHARISK1 | input | TCELL44:IMUX.IMUX16.DELAY |
| PIPERX0DATA0 | input | TCELL46:IMUX.IMUX37.DELAY |
| PIPERX0DATA1 | input | TCELL46:IMUX.IMUX36.DELAY |
| PIPERX0DATA10 | input | TCELL44:IMUX.IMUX33.DELAY |
| PIPERX0DATA11 | input | TCELL44:IMUX.IMUX32.DELAY |
| PIPERX0DATA12 | input | TCELL43:IMUX.IMUX39.DELAY |
| PIPERX0DATA13 | input | TCELL43:IMUX.IMUX38.DELAY |
| PIPERX0DATA14 | input | TCELL43:IMUX.IMUX35.DELAY |
| PIPERX0DATA15 | input | TCELL43:IMUX.IMUX34.DELAY |
| PIPERX0DATA2 | input | TCELL46:IMUX.IMUX33.DELAY |
| PIPERX0DATA3 | input | TCELL46:IMUX.IMUX32.DELAY |
| PIPERX0DATA4 | input | TCELL45:IMUX.IMUX39.DELAY |
| PIPERX0DATA5 | input | TCELL45:IMUX.IMUX38.DELAY |
| PIPERX0DATA6 | input | TCELL45:IMUX.IMUX35.DELAY |
| PIPERX0DATA7 | input | TCELL45:IMUX.IMUX34.DELAY |
| PIPERX0DATA8 | input | TCELL44:IMUX.IMUX37.DELAY |
| PIPERX0DATA9 | input | TCELL44:IMUX.IMUX36.DELAY |
| PIPERX0ELECIDLE | input | TCELL44:IMUX.IMUX34.DELAY |
| PIPERX0PHYSTATUS | input | TCELL45:IMUX.IMUX37.DELAY |
| PIPERX0POLARITY | output | TCELL43:OUT1.TMIN |
| PIPERX0STATUS0 | input | TCELL44:IMUX.IMUX39.DELAY |
| PIPERX0STATUS1 | input | TCELL44:IMUX.IMUX38.DELAY |
| PIPERX0STATUS2 | input | TCELL44:IMUX.IMUX35.DELAY |
| PIPERX0VALID | input | TCELL45:IMUX.IMUX36.DELAY |
| PIPERX1CHANISALIGNED | input | TCELL34:IMUX.IMUX33.DELAY |
| PIPERX1CHARISK0 | input | TCELL35:IMUX.IMUX16.DELAY |
| PIPERX1CHARISK1 | input | TCELL33:IMUX.IMUX16.DELAY |
| PIPERX1DATA0 | input | TCELL35:IMUX.IMUX37.DELAY |
| PIPERX1DATA1 | input | TCELL35:IMUX.IMUX36.DELAY |
| PIPERX1DATA10 | input | TCELL33:IMUX.IMUX33.DELAY |
| PIPERX1DATA11 | input | TCELL33:IMUX.IMUX32.DELAY |
| PIPERX1DATA12 | input | TCELL32:IMUX.IMUX39.DELAY |
| PIPERX1DATA13 | input | TCELL32:IMUX.IMUX38.DELAY |
| PIPERX1DATA14 | input | TCELL32:IMUX.IMUX35.DELAY |
| PIPERX1DATA15 | input | TCELL32:IMUX.IMUX34.DELAY |
| PIPERX1DATA2 | input | TCELL35:IMUX.IMUX33.DELAY |
| PIPERX1DATA3 | input | TCELL35:IMUX.IMUX32.DELAY |
| PIPERX1DATA4 | input | TCELL34:IMUX.IMUX39.DELAY |
| PIPERX1DATA5 | input | TCELL34:IMUX.IMUX38.DELAY |
| PIPERX1DATA6 | input | TCELL34:IMUX.IMUX35.DELAY |
| PIPERX1DATA7 | input | TCELL34:IMUX.IMUX34.DELAY |
| PIPERX1DATA8 | input | TCELL33:IMUX.IMUX37.DELAY |
| PIPERX1DATA9 | input | TCELL33:IMUX.IMUX36.DELAY |
| PIPERX1ELECIDLE | input | TCELL33:IMUX.IMUX34.DELAY |
| PIPERX1PHYSTATUS | input | TCELL34:IMUX.IMUX37.DELAY |
| PIPERX1POLARITY | output | TCELL32:OUT1.TMIN |
| PIPERX1STATUS0 | input | TCELL33:IMUX.IMUX39.DELAY |
| PIPERX1STATUS1 | input | TCELL33:IMUX.IMUX38.DELAY |
| PIPERX1STATUS2 | input | TCELL33:IMUX.IMUX35.DELAY |
| PIPERX1VALID | input | TCELL34:IMUX.IMUX36.DELAY |
| PIPERX2CHANISALIGNED | input | TCELL41:IMUX.IMUX33.DELAY |
| PIPERX2CHARISK0 | input | TCELL42:IMUX.IMUX16.DELAY |
| PIPERX2CHARISK1 | input | TCELL40:IMUX.IMUX16.DELAY |
| PIPERX2DATA0 | input | TCELL42:IMUX.IMUX37.DELAY |
| PIPERX2DATA1 | input | TCELL42:IMUX.IMUX36.DELAY |
| PIPERX2DATA10 | input | TCELL40:IMUX.IMUX33.DELAY |
| PIPERX2DATA11 | input | TCELL40:IMUX.IMUX32.DELAY |
| PIPERX2DATA12 | input | TCELL39:IMUX.IMUX39.DELAY |
| PIPERX2DATA13 | input | TCELL39:IMUX.IMUX38.DELAY |
| PIPERX2DATA14 | input | TCELL39:IMUX.IMUX35.DELAY |
| PIPERX2DATA15 | input | TCELL39:IMUX.IMUX34.DELAY |
| PIPERX2DATA2 | input | TCELL42:IMUX.IMUX33.DELAY |
| PIPERX2DATA3 | input | TCELL42:IMUX.IMUX32.DELAY |
| PIPERX2DATA4 | input | TCELL41:IMUX.IMUX39.DELAY |
| PIPERX2DATA5 | input | TCELL41:IMUX.IMUX38.DELAY |
| PIPERX2DATA6 | input | TCELL41:IMUX.IMUX35.DELAY |
| PIPERX2DATA7 | input | TCELL41:IMUX.IMUX34.DELAY |
| PIPERX2DATA8 | input | TCELL40:IMUX.IMUX37.DELAY |
| PIPERX2DATA9 | input | TCELL40:IMUX.IMUX36.DELAY |
| PIPERX2ELECIDLE | input | TCELL40:IMUX.IMUX34.DELAY |
| PIPERX2PHYSTATUS | input | TCELL41:IMUX.IMUX37.DELAY |
| PIPERX2POLARITY | output | TCELL39:OUT1.TMIN |
| PIPERX2STATUS0 | input | TCELL40:IMUX.IMUX39.DELAY |
| PIPERX2STATUS1 | input | TCELL40:IMUX.IMUX38.DELAY |
| PIPERX2STATUS2 | input | TCELL40:IMUX.IMUX35.DELAY |
| PIPERX2VALID | input | TCELL41:IMUX.IMUX36.DELAY |
| PIPERX3CHANISALIGNED | input | TCELL30:IMUX.IMUX33.DELAY |
| PIPERX3CHARISK0 | input | TCELL31:IMUX.IMUX16.DELAY |
| PIPERX3CHARISK1 | input | TCELL29:IMUX.IMUX16.DELAY |
| PIPERX3DATA0 | input | TCELL31:IMUX.IMUX37.DELAY |
| PIPERX3DATA1 | input | TCELL31:IMUX.IMUX36.DELAY |
| PIPERX3DATA10 | input | TCELL29:IMUX.IMUX33.DELAY |
| PIPERX3DATA11 | input | TCELL29:IMUX.IMUX32.DELAY |
| PIPERX3DATA12 | input | TCELL28:IMUX.IMUX39.DELAY |
| PIPERX3DATA13 | input | TCELL28:IMUX.IMUX38.DELAY |
| PIPERX3DATA14 | input | TCELL28:IMUX.IMUX35.DELAY |
| PIPERX3DATA15 | input | TCELL28:IMUX.IMUX34.DELAY |
| PIPERX3DATA2 | input | TCELL31:IMUX.IMUX33.DELAY |
| PIPERX3DATA3 | input | TCELL31:IMUX.IMUX32.DELAY |
| PIPERX3DATA4 | input | TCELL30:IMUX.IMUX39.DELAY |
| PIPERX3DATA5 | input | TCELL30:IMUX.IMUX38.DELAY |
| PIPERX3DATA6 | input | TCELL30:IMUX.IMUX35.DELAY |
| PIPERX3DATA7 | input | TCELL30:IMUX.IMUX34.DELAY |
| PIPERX3DATA8 | input | TCELL29:IMUX.IMUX37.DELAY |
| PIPERX3DATA9 | input | TCELL29:IMUX.IMUX36.DELAY |
| PIPERX3ELECIDLE | input | TCELL29:IMUX.IMUX34.DELAY |
| PIPERX3PHYSTATUS | input | TCELL30:IMUX.IMUX37.DELAY |
| PIPERX3POLARITY | output | TCELL28:OUT1.TMIN |
| PIPERX3STATUS0 | input | TCELL29:IMUX.IMUX39.DELAY |
| PIPERX3STATUS1 | input | TCELL29:IMUX.IMUX38.DELAY |
| PIPERX3STATUS2 | input | TCELL29:IMUX.IMUX35.DELAY |
| PIPERX3VALID | input | TCELL30:IMUX.IMUX36.DELAY |
| PIPERX4CHANISALIGNED | input | TCELL20:IMUX.IMUX33.DELAY |
| PIPERX4CHARISK0 | input | TCELL21:IMUX.IMUX16.DELAY |
| PIPERX4CHARISK1 | input | TCELL19:IMUX.IMUX16.DELAY |
| PIPERX4DATA0 | input | TCELL21:IMUX.IMUX37.DELAY |
| PIPERX4DATA1 | input | TCELL21:IMUX.IMUX36.DELAY |
| PIPERX4DATA10 | input | TCELL19:IMUX.IMUX33.DELAY |
| PIPERX4DATA11 | input | TCELL19:IMUX.IMUX32.DELAY |
| PIPERX4DATA12 | input | TCELL18:IMUX.IMUX39.DELAY |
| PIPERX4DATA13 | input | TCELL18:IMUX.IMUX38.DELAY |
| PIPERX4DATA14 | input | TCELL18:IMUX.IMUX35.DELAY |
| PIPERX4DATA15 | input | TCELL18:IMUX.IMUX34.DELAY |
| PIPERX4DATA2 | input | TCELL21:IMUX.IMUX33.DELAY |
| PIPERX4DATA3 | input | TCELL21:IMUX.IMUX32.DELAY |
| PIPERX4DATA4 | input | TCELL20:IMUX.IMUX39.DELAY |
| PIPERX4DATA5 | input | TCELL20:IMUX.IMUX38.DELAY |
| PIPERX4DATA6 | input | TCELL20:IMUX.IMUX35.DELAY |
| PIPERX4DATA7 | input | TCELL20:IMUX.IMUX34.DELAY |
| PIPERX4DATA8 | input | TCELL19:IMUX.IMUX37.DELAY |
| PIPERX4DATA9 | input | TCELL19:IMUX.IMUX36.DELAY |
| PIPERX4ELECIDLE | input | TCELL19:IMUX.IMUX34.DELAY |
| PIPERX4PHYSTATUS | input | TCELL20:IMUX.IMUX37.DELAY |
| PIPERX4POLARITY | output | TCELL18:OUT1.TMIN |
| PIPERX4STATUS0 | input | TCELL19:IMUX.IMUX39.DELAY |
| PIPERX4STATUS1 | input | TCELL19:IMUX.IMUX38.DELAY |
| PIPERX4STATUS2 | input | TCELL19:IMUX.IMUX35.DELAY |
| PIPERX4VALID | input | TCELL20:IMUX.IMUX36.DELAY |
| PIPERX5CHANISALIGNED | input | TCELL9:IMUX.IMUX33.DELAY |
| PIPERX5CHARISK0 | input | TCELL10:IMUX.IMUX16.DELAY |
| PIPERX5CHARISK1 | input | TCELL8:IMUX.IMUX16.DELAY |
| PIPERX5DATA0 | input | TCELL10:IMUX.IMUX37.DELAY |
| PIPERX5DATA1 | input | TCELL10:IMUX.IMUX36.DELAY |
| PIPERX5DATA10 | input | TCELL8:IMUX.IMUX33.DELAY |
| PIPERX5DATA11 | input | TCELL8:IMUX.IMUX32.DELAY |
| PIPERX5DATA12 | input | TCELL7:IMUX.IMUX39.DELAY |
| PIPERX5DATA13 | input | TCELL7:IMUX.IMUX38.DELAY |
| PIPERX5DATA14 | input | TCELL7:IMUX.IMUX35.DELAY |
| PIPERX5DATA15 | input | TCELL7:IMUX.IMUX34.DELAY |
| PIPERX5DATA2 | input | TCELL10:IMUX.IMUX33.DELAY |
| PIPERX5DATA3 | input | TCELL10:IMUX.IMUX32.DELAY |
| PIPERX5DATA4 | input | TCELL9:IMUX.IMUX39.DELAY |
| PIPERX5DATA5 | input | TCELL9:IMUX.IMUX38.DELAY |
| PIPERX5DATA6 | input | TCELL9:IMUX.IMUX35.DELAY |
| PIPERX5DATA7 | input | TCELL9:IMUX.IMUX34.DELAY |
| PIPERX5DATA8 | input | TCELL8:IMUX.IMUX37.DELAY |
| PIPERX5DATA9 | input | TCELL8:IMUX.IMUX36.DELAY |
| PIPERX5ELECIDLE | input | TCELL8:IMUX.IMUX34.DELAY |
| PIPERX5PHYSTATUS | input | TCELL9:IMUX.IMUX37.DELAY |
| PIPERX5POLARITY | output | TCELL7:OUT1.TMIN |
| PIPERX5STATUS0 | input | TCELL8:IMUX.IMUX39.DELAY |
| PIPERX5STATUS1 | input | TCELL8:IMUX.IMUX38.DELAY |
| PIPERX5STATUS2 | input | TCELL8:IMUX.IMUX35.DELAY |
| PIPERX5VALID | input | TCELL9:IMUX.IMUX36.DELAY |
| PIPERX6CHANISALIGNED | input | TCELL16:IMUX.IMUX33.DELAY |
| PIPERX6CHARISK0 | input | TCELL17:IMUX.IMUX16.DELAY |
| PIPERX6CHARISK1 | input | TCELL15:IMUX.IMUX16.DELAY |
| PIPERX6DATA0 | input | TCELL17:IMUX.IMUX37.DELAY |
| PIPERX6DATA1 | input | TCELL17:IMUX.IMUX36.DELAY |
| PIPERX6DATA10 | input | TCELL15:IMUX.IMUX33.DELAY |
| PIPERX6DATA11 | input | TCELL15:IMUX.IMUX32.DELAY |
| PIPERX6DATA12 | input | TCELL14:IMUX.IMUX39.DELAY |
| PIPERX6DATA13 | input | TCELL14:IMUX.IMUX38.DELAY |
| PIPERX6DATA14 | input | TCELL14:IMUX.IMUX35.DELAY |
| PIPERX6DATA15 | input | TCELL14:IMUX.IMUX34.DELAY |
| PIPERX6DATA2 | input | TCELL17:IMUX.IMUX33.DELAY |
| PIPERX6DATA3 | input | TCELL17:IMUX.IMUX32.DELAY |
| PIPERX6DATA4 | input | TCELL16:IMUX.IMUX39.DELAY |
| PIPERX6DATA5 | input | TCELL16:IMUX.IMUX38.DELAY |
| PIPERX6DATA6 | input | TCELL16:IMUX.IMUX35.DELAY |
| PIPERX6DATA7 | input | TCELL16:IMUX.IMUX34.DELAY |
| PIPERX6DATA8 | input | TCELL15:IMUX.IMUX37.DELAY |
| PIPERX6DATA9 | input | TCELL15:IMUX.IMUX36.DELAY |
| PIPERX6ELECIDLE | input | TCELL15:IMUX.IMUX34.DELAY |
| PIPERX6PHYSTATUS | input | TCELL16:IMUX.IMUX37.DELAY |
| PIPERX6POLARITY | output | TCELL14:OUT1.TMIN |
| PIPERX6STATUS0 | input | TCELL15:IMUX.IMUX39.DELAY |
| PIPERX6STATUS1 | input | TCELL15:IMUX.IMUX38.DELAY |
| PIPERX6STATUS2 | input | TCELL15:IMUX.IMUX35.DELAY |
| PIPERX6VALID | input | TCELL16:IMUX.IMUX36.DELAY |
| PIPERX7CHANISALIGNED | input | TCELL5:IMUX.IMUX33.DELAY |
| PIPERX7CHARISK0 | input | TCELL6:IMUX.IMUX16.DELAY |
| PIPERX7CHARISK1 | input | TCELL4:IMUX.IMUX16.DELAY |
| PIPERX7DATA0 | input | TCELL6:IMUX.IMUX37.DELAY |
| PIPERX7DATA1 | input | TCELL6:IMUX.IMUX36.DELAY |
| PIPERX7DATA10 | input | TCELL4:IMUX.IMUX33.DELAY |
| PIPERX7DATA11 | input | TCELL4:IMUX.IMUX32.DELAY |
| PIPERX7DATA12 | input | TCELL3:IMUX.IMUX39.DELAY |
| PIPERX7DATA13 | input | TCELL3:IMUX.IMUX38.DELAY |
| PIPERX7DATA14 | input | TCELL3:IMUX.IMUX35.DELAY |
| PIPERX7DATA15 | input | TCELL3:IMUX.IMUX34.DELAY |
| PIPERX7DATA2 | input | TCELL6:IMUX.IMUX33.DELAY |
| PIPERX7DATA3 | input | TCELL6:IMUX.IMUX32.DELAY |
| PIPERX7DATA4 | input | TCELL5:IMUX.IMUX39.DELAY |
| PIPERX7DATA5 | input | TCELL5:IMUX.IMUX38.DELAY |
| PIPERX7DATA6 | input | TCELL5:IMUX.IMUX35.DELAY |
| PIPERX7DATA7 | input | TCELL5:IMUX.IMUX34.DELAY |
| PIPERX7DATA8 | input | TCELL4:IMUX.IMUX37.DELAY |
| PIPERX7DATA9 | input | TCELL4:IMUX.IMUX36.DELAY |
| PIPERX7ELECIDLE | input | TCELL4:IMUX.IMUX34.DELAY |
| PIPERX7PHYSTATUS | input | TCELL5:IMUX.IMUX37.DELAY |
| PIPERX7POLARITY | output | TCELL3:OUT1.TMIN |
| PIPERX7STATUS0 | input | TCELL4:IMUX.IMUX39.DELAY |
| PIPERX7STATUS1 | input | TCELL4:IMUX.IMUX38.DELAY |
| PIPERX7STATUS2 | input | TCELL4:IMUX.IMUX35.DELAY |
| PIPERX7VALID | input | TCELL5:IMUX.IMUX36.DELAY |
| PIPETX0CHARISK0 | output | TCELL42:OUT16.TMIN |
| PIPETX0CHARISK1 | output | TCELL40:OUT16.TMIN |
| PIPETX0COMPLIANCE | output | TCELL43:OUT3.TMIN |
| PIPETX0DATA0 | output | TCELL43:OUT9.TMIN |
| PIPETX0DATA1 | output | TCELL43:OUT13.TMIN |
| PIPETX0DATA10 | output | TCELL41:OUT11.TMIN |
| PIPETX0DATA11 | output | TCELL41:OUT15.TMIN |
| PIPETX0DATA12 | output | TCELL40:OUT0.TMIN |
| PIPETX0DATA13 | output | TCELL40:OUT4.TMIN |
| PIPETX0DATA14 | output | TCELL40:OUT2.TMIN |
| PIPETX0DATA15 | output | TCELL40:OUT6.TMIN |
| PIPETX0DATA2 | output | TCELL43:OUT11.TMIN |
| PIPETX0DATA3 | output | TCELL43:OUT15.TMIN |
| PIPETX0DATA4 | output | TCELL42:OUT0.TMIN |
| PIPETX0DATA5 | output | TCELL42:OUT4.TMIN |
| PIPETX0DATA6 | output | TCELL42:OUT2.TMIN |
| PIPETX0DATA7 | output | TCELL42:OUT6.TMIN |
| PIPETX0DATA8 | output | TCELL41:OUT9.TMIN |
| PIPETX0DATA9 | output | TCELL41:OUT13.TMIN |
| PIPETX0ELECIDLE | output | TCELL42:OUT3.TMIN |
| PIPETX0POWERDOWN0 | output | TCELL42:OUT1.TMIN |
| PIPETX0POWERDOWN1 | output | TCELL42:OUT7.TMIN |
| PIPETX1CHARISK0 | output | TCELL31:OUT16.TMIN |
| PIPETX1CHARISK1 | output | TCELL29:OUT16.TMIN |
| PIPETX1COMPLIANCE | output | TCELL32:OUT3.TMIN |
| PIPETX1DATA0 | output | TCELL32:OUT9.TMIN |
| PIPETX1DATA1 | output | TCELL32:OUT13.TMIN |
| PIPETX1DATA10 | output | TCELL30:OUT11.TMIN |
| PIPETX1DATA11 | output | TCELL30:OUT15.TMIN |
| PIPETX1DATA12 | output | TCELL29:OUT0.TMIN |
| PIPETX1DATA13 | output | TCELL29:OUT4.TMIN |
| PIPETX1DATA14 | output | TCELL29:OUT2.TMIN |
| PIPETX1DATA15 | output | TCELL29:OUT6.TMIN |
| PIPETX1DATA2 | output | TCELL32:OUT11.TMIN |
| PIPETX1DATA3 | output | TCELL32:OUT15.TMIN |
| PIPETX1DATA4 | output | TCELL31:OUT0.TMIN |
| PIPETX1DATA5 | output | TCELL31:OUT4.TMIN |
| PIPETX1DATA6 | output | TCELL31:OUT2.TMIN |
| PIPETX1DATA7 | output | TCELL31:OUT6.TMIN |
| PIPETX1DATA8 | output | TCELL30:OUT9.TMIN |
| PIPETX1DATA9 | output | TCELL30:OUT13.TMIN |
| PIPETX1ELECIDLE | output | TCELL31:OUT3.TMIN |
| PIPETX1POWERDOWN0 | output | TCELL31:OUT1.TMIN |
| PIPETX1POWERDOWN1 | output | TCELL31:OUT7.TMIN |
| PIPETX2CHARISK0 | output | TCELL38:OUT16.TMIN |
| PIPETX2CHARISK1 | output | TCELL36:OUT16.TMIN |
| PIPETX2COMPLIANCE | output | TCELL39:OUT3.TMIN |
| PIPETX2DATA0 | output | TCELL39:OUT9.TMIN |
| PIPETX2DATA1 | output | TCELL39:OUT13.TMIN |
| PIPETX2DATA10 | output | TCELL37:OUT11.TMIN |
| PIPETX2DATA11 | output | TCELL37:OUT15.TMIN |
| PIPETX2DATA12 | output | TCELL36:OUT0.TMIN |
| PIPETX2DATA13 | output | TCELL36:OUT4.TMIN |
| PIPETX2DATA14 | output | TCELL36:OUT2.TMIN |
| PIPETX2DATA15 | output | TCELL36:OUT6.TMIN |
| PIPETX2DATA2 | output | TCELL39:OUT11.TMIN |
| PIPETX2DATA3 | output | TCELL39:OUT15.TMIN |
| PIPETX2DATA4 | output | TCELL38:OUT0.TMIN |
| PIPETX2DATA5 | output | TCELL38:OUT4.TMIN |
| PIPETX2DATA6 | output | TCELL38:OUT2.TMIN |
| PIPETX2DATA7 | output | TCELL38:OUT6.TMIN |
| PIPETX2DATA8 | output | TCELL37:OUT9.TMIN |
| PIPETX2DATA9 | output | TCELL37:OUT13.TMIN |
| PIPETX2ELECIDLE | output | TCELL38:OUT3.TMIN |
| PIPETX2POWERDOWN0 | output | TCELL38:OUT1.TMIN |
| PIPETX2POWERDOWN1 | output | TCELL38:OUT7.TMIN |
| PIPETX3CHARISK0 | output | TCELL27:OUT16.TMIN |
| PIPETX3CHARISK1 | output | TCELL25:OUT16.TMIN |
| PIPETX3COMPLIANCE | output | TCELL28:OUT3.TMIN |
| PIPETX3DATA0 | output | TCELL28:OUT9.TMIN |
| PIPETX3DATA1 | output | TCELL28:OUT13.TMIN |
| PIPETX3DATA10 | output | TCELL26:OUT11.TMIN |
| PIPETX3DATA11 | output | TCELL26:OUT15.TMIN |
| PIPETX3DATA12 | output | TCELL25:OUT0.TMIN |
| PIPETX3DATA13 | output | TCELL25:OUT4.TMIN |
| PIPETX3DATA14 | output | TCELL25:OUT2.TMIN |
| PIPETX3DATA15 | output | TCELL25:OUT6.TMIN |
| PIPETX3DATA2 | output | TCELL28:OUT11.TMIN |
| PIPETX3DATA3 | output | TCELL28:OUT15.TMIN |
| PIPETX3DATA4 | output | TCELL27:OUT0.TMIN |
| PIPETX3DATA5 | output | TCELL27:OUT4.TMIN |
| PIPETX3DATA6 | output | TCELL27:OUT2.TMIN |
| PIPETX3DATA7 | output | TCELL27:OUT6.TMIN |
| PIPETX3DATA8 | output | TCELL26:OUT9.TMIN |
| PIPETX3DATA9 | output | TCELL26:OUT13.TMIN |
| PIPETX3ELECIDLE | output | TCELL27:OUT3.TMIN |
| PIPETX3POWERDOWN0 | output | TCELL27:OUT1.TMIN |
| PIPETX3POWERDOWN1 | output | TCELL27:OUT7.TMIN |
| PIPETX4CHARISK0 | output | TCELL17:OUT16.TMIN |
| PIPETX4CHARISK1 | output | TCELL15:OUT16.TMIN |
| PIPETX4COMPLIANCE | output | TCELL18:OUT3.TMIN |
| PIPETX4DATA0 | output | TCELL18:OUT9.TMIN |
| PIPETX4DATA1 | output | TCELL18:OUT13.TMIN |
| PIPETX4DATA10 | output | TCELL16:OUT11.TMIN |
| PIPETX4DATA11 | output | TCELL16:OUT15.TMIN |
| PIPETX4DATA12 | output | TCELL15:OUT0.TMIN |
| PIPETX4DATA13 | output | TCELL15:OUT4.TMIN |
| PIPETX4DATA14 | output | TCELL15:OUT2.TMIN |
| PIPETX4DATA15 | output | TCELL15:OUT6.TMIN |
| PIPETX4DATA2 | output | TCELL18:OUT11.TMIN |
| PIPETX4DATA3 | output | TCELL18:OUT15.TMIN |
| PIPETX4DATA4 | output | TCELL17:OUT0.TMIN |
| PIPETX4DATA5 | output | TCELL17:OUT4.TMIN |
| PIPETX4DATA6 | output | TCELL17:OUT2.TMIN |
| PIPETX4DATA7 | output | TCELL17:OUT6.TMIN |
| PIPETX4DATA8 | output | TCELL16:OUT9.TMIN |
| PIPETX4DATA9 | output | TCELL16:OUT13.TMIN |
| PIPETX4ELECIDLE | output | TCELL17:OUT3.TMIN |
| PIPETX4POWERDOWN0 | output | TCELL17:OUT1.TMIN |
| PIPETX4POWERDOWN1 | output | TCELL17:OUT7.TMIN |
| PIPETX5CHARISK0 | output | TCELL6:OUT16.TMIN |
| PIPETX5CHARISK1 | output | TCELL4:OUT16.TMIN |
| PIPETX5COMPLIANCE | output | TCELL7:OUT3.TMIN |
| PIPETX5DATA0 | output | TCELL7:OUT9.TMIN |
| PIPETX5DATA1 | output | TCELL7:OUT13.TMIN |
| PIPETX5DATA10 | output | TCELL5:OUT11.TMIN |
| PIPETX5DATA11 | output | TCELL5:OUT15.TMIN |
| PIPETX5DATA12 | output | TCELL4:OUT0.TMIN |
| PIPETX5DATA13 | output | TCELL4:OUT4.TMIN |
| PIPETX5DATA14 | output | TCELL4:OUT2.TMIN |
| PIPETX5DATA15 | output | TCELL4:OUT6.TMIN |
| PIPETX5DATA2 | output | TCELL7:OUT11.TMIN |
| PIPETX5DATA3 | output | TCELL7:OUT15.TMIN |
| PIPETX5DATA4 | output | TCELL6:OUT0.TMIN |
| PIPETX5DATA5 | output | TCELL6:OUT4.TMIN |
| PIPETX5DATA6 | output | TCELL6:OUT2.TMIN |
| PIPETX5DATA7 | output | TCELL6:OUT6.TMIN |
| PIPETX5DATA8 | output | TCELL5:OUT9.TMIN |
| PIPETX5DATA9 | output | TCELL5:OUT13.TMIN |
| PIPETX5ELECIDLE | output | TCELL6:OUT3.TMIN |
| PIPETX5POWERDOWN0 | output | TCELL6:OUT1.TMIN |
| PIPETX5POWERDOWN1 | output | TCELL6:OUT7.TMIN |
| PIPETX6CHARISK0 | output | TCELL13:OUT16.TMIN |
| PIPETX6CHARISK1 | output | TCELL11:OUT16.TMIN |
| PIPETX6COMPLIANCE | output | TCELL14:OUT3.TMIN |
| PIPETX6DATA0 | output | TCELL14:OUT9.TMIN |
| PIPETX6DATA1 | output | TCELL14:OUT13.TMIN |
| PIPETX6DATA10 | output | TCELL12:OUT11.TMIN |
| PIPETX6DATA11 | output | TCELL12:OUT15.TMIN |
| PIPETX6DATA12 | output | TCELL11:OUT0.TMIN |
| PIPETX6DATA13 | output | TCELL11:OUT4.TMIN |
| PIPETX6DATA14 | output | TCELL11:OUT2.TMIN |
| PIPETX6DATA15 | output | TCELL11:OUT6.TMIN |
| PIPETX6DATA2 | output | TCELL14:OUT11.TMIN |
| PIPETX6DATA3 | output | TCELL14:OUT15.TMIN |
| PIPETX6DATA4 | output | TCELL13:OUT0.TMIN |
| PIPETX6DATA5 | output | TCELL13:OUT4.TMIN |
| PIPETX6DATA6 | output | TCELL13:OUT2.TMIN |
| PIPETX6DATA7 | output | TCELL13:OUT6.TMIN |
| PIPETX6DATA8 | output | TCELL12:OUT9.TMIN |
| PIPETX6DATA9 | output | TCELL12:OUT13.TMIN |
| PIPETX6ELECIDLE | output | TCELL13:OUT3.TMIN |
| PIPETX6POWERDOWN0 | output | TCELL13:OUT1.TMIN |
| PIPETX6POWERDOWN1 | output | TCELL13:OUT7.TMIN |
| PIPETX7CHARISK0 | output | TCELL2:OUT16.TMIN |
| PIPETX7CHARISK1 | output | TCELL0:OUT16.TMIN |
| PIPETX7COMPLIANCE | output | TCELL3:OUT3.TMIN |
| PIPETX7DATA0 | output | TCELL3:OUT9.TMIN |
| PIPETX7DATA1 | output | TCELL3:OUT13.TMIN |
| PIPETX7DATA10 | output | TCELL1:OUT11.TMIN |
| PIPETX7DATA11 | output | TCELL1:OUT15.TMIN |
| PIPETX7DATA12 | output | TCELL0:OUT0.TMIN |
| PIPETX7DATA13 | output | TCELL0:OUT4.TMIN |
| PIPETX7DATA14 | output | TCELL0:OUT2.TMIN |
| PIPETX7DATA15 | output | TCELL0:OUT6.TMIN |
| PIPETX7DATA2 | output | TCELL3:OUT11.TMIN |
| PIPETX7DATA3 | output | TCELL3:OUT15.TMIN |
| PIPETX7DATA4 | output | TCELL2:OUT0.TMIN |
| PIPETX7DATA5 | output | TCELL2:OUT4.TMIN |
| PIPETX7DATA6 | output | TCELL2:OUT2.TMIN |
| PIPETX7DATA7 | output | TCELL2:OUT6.TMIN |
| PIPETX7DATA8 | output | TCELL1:OUT9.TMIN |
| PIPETX7DATA9 | output | TCELL1:OUT13.TMIN |
| PIPETX7ELECIDLE | output | TCELL2:OUT3.TMIN |
| PIPETX7POWERDOWN0 | output | TCELL2:OUT1.TMIN |
| PIPETX7POWERDOWN1 | output | TCELL2:OUT7.TMIN |
| PIPETXDEEMPH | output | TCELL8:OUT0.TMIN |
| PIPETXMARGIN0 | output | TCELL45:OUT18.TMIN |
| PIPETXMARGIN1 | output | TCELL45:OUT16.TMIN |
| PIPETXMARGIN2 | output | TCELL45:OUT6.TMIN |
| PIPETXRATE | output | TCELL11:OUT19.TMIN |
| PIPETXRCVRDET | output | TCELL9:OUT15.TMIN |
| PIPETXRESET | output | TCELL11:OUT9.TMIN |
| PL2DIRECTEDLSTATE0 | input | TCELL49:IMUX.IMUX3.DELAY |
| PL2DIRECTEDLSTATE1 | input | TCELL24:IMUX.IMUX8.DELAY |
| PL2DIRECTEDLSTATE2 | input | TCELL24:IMUX.IMUX9.DELAY |
| PL2DIRECTEDLSTATE3 | input | TCELL24:IMUX.IMUX10.DELAY |
| PL2DIRECTEDLSTATE4 | input | TCELL24:IMUX.IMUX11.DELAY |
| PL2L0REQ | output | TCELL19:OUT20.TMIN |
| PL2LINKUP | output | TCELL14:OUT8.TMIN |
| PL2RECEIVERERR | output | TCELL14:OUT10.TMIN |
| PL2RECOVERY | output | TCELL20:OUT12.TMIN |
| PL2RXELECIDLE | output | TCELL19:OUT7.TMIN |
| PL2RXPMSTATE0 | output | TCELL19:OUT13.TMIN |
| PL2RXPMSTATE1 | output | TCELL19:OUT19.TMIN |
| PL2SUSPENDOK | output | TCELL20:OUT7.TMIN |
| PLDBGMODE0 | input | TCELL11:IMUX.IMUX21.DELAY |
| PLDBGMODE1 | input | TCELL26:IMUX.IMUX16.DELAY |
| PLDBGMODE2 | input | TCELL26:IMUX.IMUX17.DELAY |
| PLDBGVEC0 | output | TCELL39:OUT22.TMIN |
| PLDBGVEC1 | output | TCELL39:OUT23.TMIN |
| PLDBGVEC10 | output | TCELL5:OUT21.TMIN |
| PLDBGVEC11 | output | TCELL4:OUT22.TMIN |
| PLDBGVEC2 | output | TCELL40:OUT23.TMIN |
| PLDBGVEC3 | output | TCELL41:OUT22.TMIN |
| PLDBGVEC4 | output | TCELL41:OUT23.TMIN |
| PLDBGVEC5 | output | TCELL42:OUT22.TMIN |
| PLDBGVEC6 | output | TCELL42:OUT23.TMIN |
| PLDBGVEC7 | output | TCELL43:OUT23.TMIN |
| PLDBGVEC8 | output | TCELL45:OUT23.TMIN |
| PLDBGVEC9 | output | TCELL7:OUT20.TMIN |
| PLDIRECTEDCHANGEDONE | output | TCELL28:OUT0.TMIN |
| PLDIRECTEDLINKAUTON | input | TCELL25:IMUX.IMUX5.DELAY |
| PLDIRECTEDLINKCHANGE0 | input | TCELL25:IMUX.IMUX0.DELAY |
| PLDIRECTEDLINKCHANGE1 | input | TCELL25:IMUX.IMUX1.DELAY |
| PLDIRECTEDLINKSPEED | input | TCELL25:IMUX.IMUX4.DELAY |
| PLDIRECTEDLINKWIDTH0 | input | TCELL25:IMUX.IMUX2.DELAY |
| PLDIRECTEDLINKWIDTH1 | input | TCELL25:IMUX.IMUX3.DELAY |
| PLDIRECTEDLTSSMNEW0 | input | TCELL25:IMUX.IMUX9.DELAY |
| PLDIRECTEDLTSSMNEW1 | input | TCELL25:IMUX.IMUX10.DELAY |
| PLDIRECTEDLTSSMNEW2 | input | TCELL25:IMUX.IMUX11.DELAY |
| PLDIRECTEDLTSSMNEW3 | input | TCELL25:IMUX.IMUX12.DELAY |
| PLDIRECTEDLTSSMNEW4 | input | TCELL26:IMUX.IMUX0.DELAY |
| PLDIRECTEDLTSSMNEW5 | input | TCELL26:IMUX.IMUX1.DELAY |
| PLDIRECTEDLTSSMNEWVLD | input | TCELL25:IMUX.IMUX8.DELAY |
| PLDIRECTEDLTSSMSTALL | input | TCELL26:IMUX.IMUX2.DELAY |
| PLDOWNSTREAMDEEMPHSOURCE | input | TCELL25:IMUX.IMUX7.DELAY |
| PLINITIALLINKWIDTH0 | output | TCELL27:OUT8.TMIN |
| PLINITIALLINKWIDTH1 | output | TCELL27:OUT9.TMIN |
| PLINITIALLINKWIDTH2 | output | TCELL27:OUT10.TMIN |
| PLLANEREVERSALMODE0 | output | TCELL25:OUT13.TMIN |
| PLLANEREVERSALMODE1 | output | TCELL25:OUT14.TMIN |
| PLLINKGEN2CAP | output | TCELL26:OUT3.TMIN |
| PLLINKPARTNERGEN2SUPPORTED | output | TCELL27:OUT5.TMIN |
| PLLINKUPCFGCAP | output | TCELL26:OUT2.TMIN |
| PLLTSSMSTATE0 | output | TCELL25:OUT7.TMIN |
| PLLTSSMSTATE1 | output | TCELL25:OUT8.TMIN |
| PLLTSSMSTATE2 | output | TCELL25:OUT9.TMIN |
| PLLTSSMSTATE3 | output | TCELL25:OUT10.TMIN |
| PLLTSSMSTATE4 | output | TCELL25:OUT11.TMIN |
| PLLTSSMSTATE5 | output | TCELL25:OUT12.TMIN |
| PLPHYLNKUPN | output | TCELL25:OUT15.TMIN |
| PLRECEIVEDHOTRST | output | TCELL8:OUT13.TMIN |
| PLRSTN | input | TCELL3:IMUX.CTRL0 |
| PLRXPMSTATE0 | output | TCELL26:OUT0.TMIN |
| PLRXPMSTATE1 | output | TCELL26:OUT1.TMIN |
| PLSELLNKRATE | output | TCELL25:OUT1.TMIN |
| PLSELLNKWIDTH0 | output | TCELL25:OUT3.TMIN |
| PLSELLNKWIDTH1 | output | TCELL25:OUT5.TMIN |
| PLTRANSMITHOTRST | input | TCELL2:IMUX.IMUX12.DELAY |
| PLTXPMSTATE0 | output | TCELL25:OUT17.TMIN |
| PLTXPMSTATE1 | output | TCELL25:OUT18.TMIN |
| PLTXPMSTATE2 | output | TCELL25:OUT19.TMIN |
| PLUPSTREAMPREFERDEEMPH | input | TCELL25:IMUX.IMUX6.DELAY |
| PMVDIVIDE0 | input | TCELL6:IMUX.IMUX8.DELAY |
| PMVDIVIDE1 | input | TCELL5:IMUX.IMUX6.DELAY |
| PMVENABLEN | input | TCELL10:IMUX.IMUX4.DELAY |
| PMVOUT | output | TCELL2:OUT9.TMIN |
| PMVSELECT0 | input | TCELL9:IMUX.IMUX6.DELAY |
| PMVSELECT1 | input | TCELL8:IMUX.IMUX4.DELAY |
| PMVSELECT2 | input | TCELL7:IMUX.IMUX9.DELAY |
| RECEIVEDFUNCLVLRSTN | output | TCELL9:OUT12.TMIN |
| SCANENABLEN | input | TCELL24:IMUX.IMUX12.DELAY |
| SCANMODEN | input | TCELL23:IMUX.IMUX19.DELAY |
| SYSRSTN | input | TCELL0:IMUX.CTRL0 |
| TL2ASPMSUSPENDCREDITCHECK | input | TCELL23:IMUX.IMUX18.DELAY |
| TL2ASPMSUSPENDCREDITCHECKOK | output | TCELL14:OUT7.TMIN |
| TL2ASPMSUSPENDREQ | output | TCELL14:OUT6.TMIN |
| TL2ERRFCPE | output | TCELL38:OUT19.TMIN |
| TL2ERRHDR0 | output | TCELL12:OUT6.TMIN |
| TL2ERRHDR1 | output | TCELL12:OUT7.TMIN |
| TL2ERRHDR10 | output | TCELL9:OUT6.TMIN |
| TL2ERRHDR11 | output | TCELL9:OUT9.TMIN |
| TL2ERRHDR12 | output | TCELL9:OUT10.TMIN |
| TL2ERRHDR13 | output | TCELL9:OUT11.TMIN |
| TL2ERRHDR14 | output | TCELL8:OUT7.TMIN |
| TL2ERRHDR15 | output | TCELL8:OUT8.TMIN |
| TL2ERRHDR16 | output | TCELL8:OUT9.TMIN |
| TL2ERRHDR17 | output | TCELL8:OUT11.TMIN |
| TL2ERRHDR18 | output | TCELL1:OUT4.TMIN |
| TL2ERRHDR19 | output | TCELL26:OUT8.TMIN |
| TL2ERRHDR2 | output | TCELL11:OUT8.TMIN |
| TL2ERRHDR20 | output | TCELL26:OUT10.TMIN |
| TL2ERRHDR21 | output | TCELL26:OUT12.TMIN |
| TL2ERRHDR22 | output | TCELL26:OUT14.TMIN |
| TL2ERRHDR23 | output | TCELL27:OUT15.TMIN |
| TL2ERRHDR24 | output | TCELL27:OUT17.TMIN |
| TL2ERRHDR25 | output | TCELL28:OUT12.TMIN |
| TL2ERRHDR26 | output | TCELL28:OUT14.TMIN |
| TL2ERRHDR27 | output | TCELL28:OUT16.TMIN |
| TL2ERRHDR28 | output | TCELL28:OUT17.TMIN |
| TL2ERRHDR29 | output | TCELL29:OUT12.TMIN |
| TL2ERRHDR3 | output | TCELL11:OUT10.TMIN |
| TL2ERRHDR30 | output | TCELL29:OUT13.TMIN |
| TL2ERRHDR31 | output | TCELL29:OUT14.TMIN |
| TL2ERRHDR32 | output | TCELL29:OUT15.TMIN |
| TL2ERRHDR33 | output | TCELL30:OUT8.TMIN |
| TL2ERRHDR34 | output | TCELL30:OUT10.TMIN |
| TL2ERRHDR35 | output | TCELL30:OUT12.TMIN |
| TL2ERRHDR36 | output | TCELL30:OUT14.TMIN |
| TL2ERRHDR37 | output | TCELL31:OUT15.TMIN |
| TL2ERRHDR38 | output | TCELL31:OUT17.TMIN |
| TL2ERRHDR39 | output | TCELL32:OUT12.TMIN |
| TL2ERRHDR4 | output | TCELL11:OUT11.TMIN |
| TL2ERRHDR40 | output | TCELL32:OUT14.TMIN |
| TL2ERRHDR41 | output | TCELL32:OUT16.TMIN |
| TL2ERRHDR42 | output | TCELL32:OUT17.TMIN |
| TL2ERRHDR43 | output | TCELL33:OUT8.TMIN |
| TL2ERRHDR44 | output | TCELL33:OUT9.TMIN |
| TL2ERRHDR45 | output | TCELL33:OUT10.TMIN |
| TL2ERRHDR46 | output | TCELL33:OUT11.TMIN |
| TL2ERRHDR47 | output | TCELL34:OUT8.TMIN |
| TL2ERRHDR48 | output | TCELL34:OUT9.TMIN |
| TL2ERRHDR49 | output | TCELL34:OUT10.TMIN |
| TL2ERRHDR5 | output | TCELL11:OUT12.TMIN |
| TL2ERRHDR50 | output | TCELL34:OUT11.TMIN |
| TL2ERRHDR51 | output | TCELL35:OUT8.TMIN |
| TL2ERRHDR52 | output | TCELL35:OUT9.TMIN |
| TL2ERRHDR53 | output | TCELL35:OUT10.TMIN |
| TL2ERRHDR54 | output | TCELL35:OUT11.TMIN |
| TL2ERRHDR55 | output | TCELL36:OUT12.TMIN |
| TL2ERRHDR56 | output | TCELL36:OUT13.TMIN |
| TL2ERRHDR57 | output | TCELL36:OUT14.TMIN |
| TL2ERRHDR58 | output | TCELL36:OUT15.TMIN |
| TL2ERRHDR59 | output | TCELL37:OUT8.TMIN |
| TL2ERRHDR6 | output | TCELL10:OUT6.TMIN |
| TL2ERRHDR60 | output | TCELL37:OUT10.TMIN |
| TL2ERRHDR61 | output | TCELL37:OUT12.TMIN |
| TL2ERRHDR62 | output | TCELL37:OUT14.TMIN |
| TL2ERRHDR63 | output | TCELL38:OUT15.TMIN |
| TL2ERRHDR7 | output | TCELL10:OUT7.TMIN |
| TL2ERRHDR8 | output | TCELL10:OUT8.TMIN |
| TL2ERRHDR9 | output | TCELL10:OUT9.TMIN |
| TL2ERRMALFORMED | output | TCELL38:OUT17.TMIN |
| TL2ERRRXOVERFLOW | output | TCELL38:OUT18.TMIN |
| TL2PPMSUSPENDOK | output | TCELL16:OUT21.TMIN |
| TL2PPMSUSPENDREQ | input | TCELL23:IMUX.IMUX17.DELAY |
| TLRSTN | input | TCELL2:IMUX.CTRL0 |
| TRNFCCPLD0 | output | TCELL33:OUT7.TMIN |
| TRNFCCPLD1 | output | TCELL34:OUT4.TMIN |
| TRNFCCPLD10 | output | TCELL36:OUT9.TMIN |
| TRNFCCPLD11 | output | TCELL36:OUT10.TMIN |
| TRNFCCPLD2 | output | TCELL34:OUT5.TMIN |
| TRNFCCPLD3 | output | TCELL34:OUT6.TMIN |
| TRNFCCPLD4 | output | TCELL34:OUT7.TMIN |
| TRNFCCPLD5 | output | TCELL35:OUT4.TMIN |
| TRNFCCPLD6 | output | TCELL35:OUT5.TMIN |
| TRNFCCPLD7 | output | TCELL35:OUT6.TMIN |
| TRNFCCPLD8 | output | TCELL35:OUT7.TMIN |
| TRNFCCPLD9 | output | TCELL36:OUT8.TMIN |
| TRNFCCPLH0 | output | TCELL31:OUT14.TMIN |
| TRNFCCPLH1 | output | TCELL32:OUT6.TMIN |
| TRNFCCPLH2 | output | TCELL32:OUT7.TMIN |
| TRNFCCPLH3 | output | TCELL32:OUT8.TMIN |
| TRNFCCPLH4 | output | TCELL32:OUT10.TMIN |
| TRNFCCPLH5 | output | TCELL33:OUT4.TMIN |
| TRNFCCPLH6 | output | TCELL33:OUT5.TMIN |
| TRNFCCPLH7 | output | TCELL33:OUT6.TMIN |
| TRNFCNPD0 | output | TCELL28:OUT10.TMIN |
| TRNFCNPD1 | output | TCELL29:OUT8.TMIN |
| TRNFCNPD10 | output | TCELL31:OUT12.TMIN |
| TRNFCNPD11 | output | TCELL31:OUT13.TMIN |
| TRNFCNPD2 | output | TCELL29:OUT9.TMIN |
| TRNFCNPD3 | output | TCELL29:OUT10.TMIN |
| TRNFCNPD4 | output | TCELL29:OUT11.TMIN |
| TRNFCNPD5 | output | TCELL30:OUT4.TMIN |
| TRNFCNPD6 | output | TCELL30:OUT5.TMIN |
| TRNFCNPD7 | output | TCELL30:OUT6.TMIN |
| TRNFCNPD8 | output | TCELL30:OUT7.TMIN |
| TRNFCNPD9 | output | TCELL31:OUT11.TMIN |
| TRNFCNPH0 | output | TCELL26:OUT7.TMIN |
| TRNFCNPH1 | output | TCELL27:OUT11.TMIN |
| TRNFCNPH2 | output | TCELL27:OUT12.TMIN |
| TRNFCNPH3 | output | TCELL27:OUT13.TMIN |
| TRNFCNPH4 | output | TCELL27:OUT14.TMIN |
| TRNFCNPH5 | output | TCELL28:OUT6.TMIN |
| TRNFCNPH6 | output | TCELL28:OUT7.TMIN |
| TRNFCNPH7 | output | TCELL28:OUT8.TMIN |
| TRNFCPD0 | output | TCELL3:OUT5.TMIN |
| TRNFCPD1 | output | TCELL2:OUT8.TMIN |
| TRNFCPD10 | output | TCELL26:OUT5.TMIN |
| TRNFCPD11 | output | TCELL26:OUT6.TMIN |
| TRNFCPD2 | output | TCELL1:OUT0.TMIN |
| TRNFCPD3 | output | TCELL1:OUT1.TMIN |
| TRNFCPD4 | output | TCELL1:OUT2.TMIN |
| TRNFCPD5 | output | TCELL1:OUT3.TMIN |
| TRNFCPD6 | output | TCELL0:OUT5.TMIN |
| TRNFCPD7 | output | TCELL0:OUT7.TMIN |
| TRNFCPD8 | output | TCELL0:OUT8.TMIN |
| TRNFCPD9 | output | TCELL26:OUT4.TMIN |
| TRNFCPH0 | output | TCELL7:OUT2.TMIN |
| TRNFCPH1 | output | TCELL7:OUT6.TMIN |
| TRNFCPH2 | output | TCELL5:OUT2.TMIN |
| TRNFCPH3 | output | TCELL5:OUT3.TMIN |
| TRNFCPH4 | output | TCELL5:OUT4.TMIN |
| TRNFCPH5 | output | TCELL4:OUT5.TMIN |
| TRNFCPH6 | output | TCELL3:OUT0.TMIN |
| TRNFCPH7 | output | TCELL3:OUT4.TMIN |
| TRNFCSEL0 | input | TCELL39:IMUX.IMUX2.DELAY |
| TRNFCSEL1 | input | TCELL39:IMUX.IMUX3.DELAY |
| TRNFCSEL2 | input | TCELL40:IMUX.IMUX0.DELAY |
| TRNLNKUP | output | TCELL7:OUT0.TMIN |
| TRNRBARHIT0 | output | TCELL9:OUT0.TMIN |
| TRNRBARHIT1 | output | TCELL9:OUT1.TMIN |
| TRNRBARHIT2 | output | TCELL9:OUT2.TMIN |
| TRNRBARHIT3 | output | TCELL9:OUT3.TMIN |
| TRNRBARHIT4 | output | TCELL8:OUT1.TMIN |
| TRNRBARHIT5 | output | TCELL8:OUT2.TMIN |
| TRNRBARHIT6 | output | TCELL8:OUT3.TMIN |
| TRNRBARHIT7 | output | TCELL8:OUT6.TMIN |
| TRNRD0 | output | TCELL30:OUT1.TMIN |
| TRNRD1 | output | TCELL30:OUT2.TMIN |
| TRNRD10 | output | TCELL32:OUT5.TMIN |
| TRNRD100 | output | TCELL19:OUT3.TMIN |
| TRNRD101 | output | TCELL19:OUT4.TMIN |
| TRNRD102 | output | TCELL19:OUT6.TMIN |
| TRNRD103 | output | TCELL18:OUT0.TMIN |
| TRNRD104 | output | TCELL18:OUT2.TMIN |
| TRNRD105 | output | TCELL18:OUT5.TMIN |
| TRNRD106 | output | TCELL17:OUT5.TMIN |
| TRNRD107 | output | TCELL17:OUT8.TMIN |
| TRNRD108 | output | TCELL17:OUT9.TMIN |
| TRNRD109 | output | TCELL17:OUT10.TMIN |
| TRNRD11 | output | TCELL33:OUT0.TMIN |
| TRNRD110 | output | TCELL16:OUT0.TMIN |
| TRNRD111 | output | TCELL16:OUT1.TMIN |
| TRNRD112 | output | TCELL15:OUT3.TMIN |
| TRNRD113 | output | TCELL15:OUT5.TMIN |
| TRNRD114 | output | TCELL15:OUT7.TMIN |
| TRNRD115 | output | TCELL15:OUT8.TMIN |
| TRNRD116 | output | TCELL14:OUT0.TMIN |
| TRNRD117 | output | TCELL14:OUT2.TMIN |
| TRNRD118 | output | TCELL14:OUT4.TMIN |
| TRNRD119 | output | TCELL14:OUT5.TMIN |
| TRNRD12 | output | TCELL33:OUT1.TMIN |
| TRNRD120 | output | TCELL13:OUT5.TMIN |
| TRNRD121 | output | TCELL13:OUT8.TMIN |
| TRNRD122 | output | TCELL13:OUT9.TMIN |
| TRNRD123 | output | TCELL13:OUT10.TMIN |
| TRNRD124 | output | TCELL12:OUT0.TMIN |
| TRNRD125 | output | TCELL12:OUT1.TMIN |
| TRNRD126 | output | TCELL12:OUT2.TMIN |
| TRNRD127 | output | TCELL12:OUT3.TMIN |
| TRNRD13 | output | TCELL33:OUT2.TMIN |
| TRNRD14 | output | TCELL33:OUT3.TMIN |
| TRNRD15 | output | TCELL34:OUT0.TMIN |
| TRNRD16 | output | TCELL34:OUT1.TMIN |
| TRNRD17 | output | TCELL34:OUT2.TMIN |
| TRNRD18 | output | TCELL34:OUT3.TMIN |
| TRNRD19 | output | TCELL35:OUT0.TMIN |
| TRNRD2 | output | TCELL30:OUT3.TMIN |
| TRNRD20 | output | TCELL35:OUT1.TMIN |
| TRNRD21 | output | TCELL35:OUT2.TMIN |
| TRNRD22 | output | TCELL35:OUT3.TMIN |
| TRNRD23 | output | TCELL36:OUT1.TMIN |
| TRNRD24 | output | TCELL36:OUT3.TMIN |
| TRNRD25 | output | TCELL36:OUT5.TMIN |
| TRNRD26 | output | TCELL36:OUT7.TMIN |
| TRNRD27 | output | TCELL37:OUT0.TMIN |
| TRNRD28 | output | TCELL37:OUT1.TMIN |
| TRNRD29 | output | TCELL37:OUT2.TMIN |
| TRNRD3 | output | TCELL31:OUT5.TMIN |
| TRNRD30 | output | TCELL37:OUT3.TMIN |
| TRNRD31 | output | TCELL38:OUT5.TMIN |
| TRNRD32 | output | TCELL38:OUT8.TMIN |
| TRNRD33 | output | TCELL38:OUT9.TMIN |
| TRNRD34 | output | TCELL38:OUT10.TMIN |
| TRNRD35 | output | TCELL39:OUT0.TMIN |
| TRNRD36 | output | TCELL39:OUT2.TMIN |
| TRNRD37 | output | TCELL39:OUT4.TMIN |
| TRNRD38 | output | TCELL39:OUT5.TMIN |
| TRNRD39 | output | TCELL40:OUT1.TMIN |
| TRNRD4 | output | TCELL31:OUT8.TMIN |
| TRNRD40 | output | TCELL40:OUT3.TMIN |
| TRNRD41 | output | TCELL40:OUT5.TMIN |
| TRNRD42 | output | TCELL40:OUT7.TMIN |
| TRNRD43 | output | TCELL41:OUT0.TMIN |
| TRNRD44 | output | TCELL41:OUT1.TMIN |
| TRNRD45 | output | TCELL41:OUT2.TMIN |
| TRNRD46 | output | TCELL41:OUT3.TMIN |
| TRNRD47 | output | TCELL42:OUT5.TMIN |
| TRNRD48 | output | TCELL42:OUT8.TMIN |
| TRNRD49 | output | TCELL42:OUT9.TMIN |
| TRNRD5 | output | TCELL31:OUT9.TMIN |
| TRNRD50 | output | TCELL42:OUT10.TMIN |
| TRNRD51 | output | TCELL43:OUT0.TMIN |
| TRNRD52 | output | TCELL43:OUT2.TMIN |
| TRNRD53 | output | TCELL43:OUT4.TMIN |
| TRNRD54 | output | TCELL43:OUT5.TMIN |
| TRNRD55 | output | TCELL44:OUT0.TMIN |
| TRNRD56 | output | TCELL44:OUT1.TMIN |
| TRNRD57 | output | TCELL44:OUT2.TMIN |
| TRNRD58 | output | TCELL44:OUT3.TMIN |
| TRNRD59 | output | TCELL45:OUT0.TMIN |
| TRNRD6 | output | TCELL31:OUT10.TMIN |
| TRNRD60 | output | TCELL45:OUT1.TMIN |
| TRNRD61 | output | TCELL45:OUT2.TMIN |
| TRNRD62 | output | TCELL45:OUT3.TMIN |
| TRNRD63 | output | TCELL46:OUT0.TMIN |
| TRNRD64 | output | TCELL46:OUT1.TMIN |
| TRNRD65 | output | TCELL46:OUT2.TMIN |
| TRNRD66 | output | TCELL46:OUT3.TMIN |
| TRNRD67 | output | TCELL47:OUT0.TMIN |
| TRNRD68 | output | TCELL47:OUT1.TMIN |
| TRNRD69 | output | TCELL47:OUT2.TMIN |
| TRNRD7 | output | TCELL32:OUT0.TMIN |
| TRNRD70 | output | TCELL47:OUT3.TMIN |
| TRNRD71 | output | TCELL48:OUT0.TMIN |
| TRNRD72 | output | TCELL48:OUT1.TMIN |
| TRNRD73 | output | TCELL48:OUT2.TMIN |
| TRNRD74 | output | TCELL48:OUT3.TMIN |
| TRNRD75 | output | TCELL49:OUT0.TMIN |
| TRNRD76 | output | TCELL49:OUT1.TMIN |
| TRNRD77 | output | TCELL49:OUT2.TMIN |
| TRNRD78 | output | TCELL49:OUT3.TMIN |
| TRNRD79 | output | TCELL24:OUT0.TMIN |
| TRNRD8 | output | TCELL32:OUT2.TMIN |
| TRNRD80 | output | TCELL24:OUT2.TMIN |
| TRNRD81 | output | TCELL24:OUT3.TMIN |
| TRNRD82 | output | TCELL24:OUT4.TMIN |
| TRNRD83 | output | TCELL23:OUT0.TMIN |
| TRNRD84 | output | TCELL23:OUT1.TMIN |
| TRNRD85 | output | TCELL23:OUT2.TMIN |
| TRNRD86 | output | TCELL23:OUT4.TMIN |
| TRNRD87 | output | TCELL22:OUT2.TMIN |
| TRNRD88 | output | TCELL22:OUT3.TMIN |
| TRNRD89 | output | TCELL22:OUT4.TMIN |
| TRNRD9 | output | TCELL32:OUT4.TMIN |
| TRNRD90 | output | TCELL22:OUT6.TMIN |
| TRNRD91 | output | TCELL21:OUT1.TMIN |
| TRNRD92 | output | TCELL21:OUT3.TMIN |
| TRNRD93 | output | TCELL21:OUT4.TMIN |
| TRNRD94 | output | TCELL21:OUT6.TMIN |
| TRNRD95 | output | TCELL20:OUT2.TMIN |
| TRNRD96 | output | TCELL20:OUT4.TMIN |
| TRNRD97 | output | TCELL20:OUT5.TMIN |
| TRNRD98 | output | TCELL20:OUT6.TMIN |
| TRNRD99 | output | TCELL19:OUT1.TMIN |
| TRNRDLLPDATA0 | output | TCELL37:OUT4.TMIN |
| TRNRDLLPDATA1 | output | TCELL37:OUT5.TMIN |
| TRNRDLLPDATA10 | output | TCELL39:OUT8.TMIN |
| TRNRDLLPDATA11 | output | TCELL39:OUT10.TMIN |
| TRNRDLLPDATA12 | output | TCELL40:OUT8.TMIN |
| TRNRDLLPDATA13 | output | TCELL40:OUT9.TMIN |
| TRNRDLLPDATA14 | output | TCELL40:OUT10.TMIN |
| TRNRDLLPDATA15 | output | TCELL40:OUT11.TMIN |
| TRNRDLLPDATA16 | output | TCELL41:OUT4.TMIN |
| TRNRDLLPDATA17 | output | TCELL41:OUT5.TMIN |
| TRNRDLLPDATA18 | output | TCELL41:OUT6.TMIN |
| TRNRDLLPDATA19 | output | TCELL41:OUT7.TMIN |
| TRNRDLLPDATA2 | output | TCELL37:OUT6.TMIN |
| TRNRDLLPDATA20 | output | TCELL42:OUT11.TMIN |
| TRNRDLLPDATA21 | output | TCELL42:OUT12.TMIN |
| TRNRDLLPDATA22 | output | TCELL42:OUT13.TMIN |
| TRNRDLLPDATA23 | output | TCELL42:OUT14.TMIN |
| TRNRDLLPDATA24 | output | TCELL43:OUT6.TMIN |
| TRNRDLLPDATA25 | output | TCELL43:OUT7.TMIN |
| TRNRDLLPDATA26 | output | TCELL43:OUT8.TMIN |
| TRNRDLLPDATA27 | output | TCELL43:OUT10.TMIN |
| TRNRDLLPDATA28 | output | TCELL44:OUT4.TMIN |
| TRNRDLLPDATA29 | output | TCELL44:OUT5.TMIN |
| TRNRDLLPDATA3 | output | TCELL37:OUT7.TMIN |
| TRNRDLLPDATA30 | output | TCELL44:OUT6.TMIN |
| TRNRDLLPDATA31 | output | TCELL44:OUT7.TMIN |
| TRNRDLLPDATA32 | output | TCELL45:OUT4.TMIN |
| TRNRDLLPDATA33 | output | TCELL45:OUT5.TMIN |
| TRNRDLLPDATA34 | output | TCELL45:OUT7.TMIN |
| TRNRDLLPDATA35 | output | TCELL45:OUT8.TMIN |
| TRNRDLLPDATA36 | output | TCELL46:OUT4.TMIN |
| TRNRDLLPDATA37 | output | TCELL46:OUT5.TMIN |
| TRNRDLLPDATA38 | output | TCELL46:OUT6.TMIN |
| TRNRDLLPDATA39 | output | TCELL46:OUT7.TMIN |
| TRNRDLLPDATA4 | output | TCELL38:OUT11.TMIN |
| TRNRDLLPDATA40 | output | TCELL47:OUT4.TMIN |
| TRNRDLLPDATA41 | output | TCELL47:OUT5.TMIN |
| TRNRDLLPDATA42 | output | TCELL47:OUT6.TMIN |
| TRNRDLLPDATA43 | output | TCELL47:OUT7.TMIN |
| TRNRDLLPDATA44 | output | TCELL48:OUT4.TMIN |
| TRNRDLLPDATA45 | output | TCELL48:OUT5.TMIN |
| TRNRDLLPDATA46 | output | TCELL48:OUT6.TMIN |
| TRNRDLLPDATA47 | output | TCELL48:OUT7.TMIN |
| TRNRDLLPDATA48 | output | TCELL49:OUT4.TMIN |
| TRNRDLLPDATA49 | output | TCELL49:OUT5.TMIN |
| TRNRDLLPDATA5 | output | TCELL38:OUT12.TMIN |
| TRNRDLLPDATA50 | output | TCELL49:OUT6.TMIN |
| TRNRDLLPDATA51 | output | TCELL49:OUT7.TMIN |
| TRNRDLLPDATA52 | output | TCELL24:OUT5.TMIN |
| TRNRDLLPDATA53 | output | TCELL24:OUT6.TMIN |
| TRNRDLLPDATA54 | output | TCELL24:OUT7.TMIN |
| TRNRDLLPDATA55 | output | TCELL24:OUT12.TMIN |
| TRNRDLLPDATA56 | output | TCELL23:OUT5.TMIN |
| TRNRDLLPDATA57 | output | TCELL23:OUT6.TMIN |
| TRNRDLLPDATA58 | output | TCELL23:OUT7.TMIN |
| TRNRDLLPDATA59 | output | TCELL23:OUT9.TMIN |
| TRNRDLLPDATA6 | output | TCELL38:OUT13.TMIN |
| TRNRDLLPDATA60 | output | TCELL22:OUT7.TMIN |
| TRNRDLLPDATA61 | output | TCELL22:OUT8.TMIN |
| TRNRDLLPDATA62 | output | TCELL22:OUT10.TMIN |
| TRNRDLLPDATA63 | output | TCELL22:OUT11.TMIN |
| TRNRDLLPDATA7 | output | TCELL38:OUT14.TMIN |
| TRNRDLLPDATA8 | output | TCELL39:OUT6.TMIN |
| TRNRDLLPDATA9 | output | TCELL39:OUT7.TMIN |
| TRNRDLLPSRCRDY0 | output | TCELL21:OUT10.TMIN |
| TRNRDLLPSRCRDY1 | output | TCELL21:OUT14.TMIN |
| TRNRDSTRDY | input | TCELL38:IMUX.IMUX2.DELAY |
| TRNRECRCERR | output | TCELL10:OUT4.TMIN |
| TRNREOF | output | TCELL11:OUT7.TMIN |
| TRNRERRFWD | output | TCELL10:OUT5.TMIN |
| TRNRFCPRET | input | TCELL39:IMUX.IMUX0.DELAY |
| TRNRNPOK | input | TCELL39:IMUX.IMUX1.DELAY |
| TRNRNPREQ | input | TCELL38:IMUX.IMUX3.DELAY |
| TRNRREM0 | output | TCELL11:OUT1.TMIN |
| TRNRREM1 | output | TCELL11:OUT3.TMIN |
| TRNRSOF | output | TCELL11:OUT5.TMIN |
| TRNRSRCDSC | output | TCELL10:OUT3.TMIN |
| TRNRSRCRDY | output | TCELL10:OUT0.TMIN |
| TRNTBUFAV0 | output | TCELL28:OUT4.TMIN |
| TRNTBUFAV1 | output | TCELL28:OUT5.TMIN |
| TRNTBUFAV2 | output | TCELL29:OUT1.TMIN |
| TRNTBUFAV3 | output | TCELL29:OUT3.TMIN |
| TRNTBUFAV4 | output | TCELL29:OUT5.TMIN |
| TRNTBUFAV5 | output | TCELL29:OUT7.TMIN |
| TRNTCFGGNT | input | TCELL38:IMUX.IMUX1.DELAY |
| TRNTCFGREQ | output | TCELL30:OUT0.TMIN |
| TRNTD0 | input | TCELL18:IMUX.IMUX8.DELAY |
| TRNTD1 | input | TCELL18:IMUX.IMUX9.DELAY |
| TRNTD10 | input | TCELL20:IMUX.IMUX10.DELAY |
| TRNTD100 | input | TCELL29:IMUX.IMUX0.DELAY |
| TRNTD101 | input | TCELL29:IMUX.IMUX1.DELAY |
| TRNTD102 | input | TCELL29:IMUX.IMUX2.DELAY |
| TRNTD103 | input | TCELL29:IMUX.IMUX3.DELAY |
| TRNTD104 | input | TCELL30:IMUX.IMUX0.DELAY |
| TRNTD105 | input | TCELL30:IMUX.IMUX1.DELAY |
| TRNTD106 | input | TCELL30:IMUX.IMUX2.DELAY |
| TRNTD107 | input | TCELL30:IMUX.IMUX3.DELAY |
| TRNTD108 | input | TCELL31:IMUX.IMUX0.DELAY |
| TRNTD109 | input | TCELL31:IMUX.IMUX1.DELAY |
| TRNTD11 | input | TCELL20:IMUX.IMUX11.DELAY |
| TRNTD110 | input | TCELL31:IMUX.IMUX2.DELAY |
| TRNTD111 | input | TCELL31:IMUX.IMUX3.DELAY |
| TRNTD112 | input | TCELL32:IMUX.IMUX0.DELAY |
| TRNTD113 | input | TCELL32:IMUX.IMUX1.DELAY |
| TRNTD114 | input | TCELL32:IMUX.IMUX2.DELAY |
| TRNTD115 | input | TCELL32:IMUX.IMUX3.DELAY |
| TRNTD116 | input | TCELL33:IMUX.IMUX0.DELAY |
| TRNTD117 | input | TCELL33:IMUX.IMUX1.DELAY |
| TRNTD118 | input | TCELL33:IMUX.IMUX2.DELAY |
| TRNTD119 | input | TCELL33:IMUX.IMUX3.DELAY |
| TRNTD12 | input | TCELL21:IMUX.IMUX8.DELAY |
| TRNTD120 | input | TCELL34:IMUX.IMUX0.DELAY |
| TRNTD121 | input | TCELL34:IMUX.IMUX1.DELAY |
| TRNTD122 | input | TCELL34:IMUX.IMUX2.DELAY |
| TRNTD123 | input | TCELL34:IMUX.IMUX3.DELAY |
| TRNTD124 | input | TCELL35:IMUX.IMUX0.DELAY |
| TRNTD125 | input | TCELL35:IMUX.IMUX1.DELAY |
| TRNTD126 | input | TCELL35:IMUX.IMUX2.DELAY |
| TRNTD127 | input | TCELL35:IMUX.IMUX3.DELAY |
| TRNTD13 | input | TCELL21:IMUX.IMUX9.DELAY |
| TRNTD14 | input | TCELL21:IMUX.IMUX10.DELAY |
| TRNTD15 | input | TCELL21:IMUX.IMUX11.DELAY |
| TRNTD16 | input | TCELL22:IMUX.IMUX8.DELAY |
| TRNTD17 | input | TCELL22:IMUX.IMUX9.DELAY |
| TRNTD18 | input | TCELL22:IMUX.IMUX10.DELAY |
| TRNTD19 | input | TCELL22:IMUX.IMUX11.DELAY |
| TRNTD2 | input | TCELL18:IMUX.IMUX10.DELAY |
| TRNTD20 | input | TCELL23:IMUX.IMUX8.DELAY |
| TRNTD21 | input | TCELL23:IMUX.IMUX9.DELAY |
| TRNTD22 | input | TCELL23:IMUX.IMUX10.DELAY |
| TRNTD23 | input | TCELL23:IMUX.IMUX11.DELAY |
| TRNTD24 | input | TCELL24:IMUX.IMUX4.DELAY |
| TRNTD25 | input | TCELL24:IMUX.IMUX5.DELAY |
| TRNTD26 | input | TCELL24:IMUX.IMUX6.DELAY |
| TRNTD27 | input | TCELL24:IMUX.IMUX7.DELAY |
| TRNTD28 | input | TCELL23:IMUX.IMUX12.DELAY |
| TRNTD29 | input | TCELL23:IMUX.IMUX13.DELAY |
| TRNTD3 | input | TCELL18:IMUX.IMUX11.DELAY |
| TRNTD30 | input | TCELL23:IMUX.IMUX14.DELAY |
| TRNTD31 | input | TCELL23:IMUX.IMUX15.DELAY |
| TRNTD32 | input | TCELL22:IMUX.IMUX12.DELAY |
| TRNTD33 | input | TCELL22:IMUX.IMUX13.DELAY |
| TRNTD34 | input | TCELL22:IMUX.IMUX14.DELAY |
| TRNTD35 | input | TCELL22:IMUX.IMUX15.DELAY |
| TRNTD36 | input | TCELL21:IMUX.IMUX12.DELAY |
| TRNTD37 | input | TCELL21:IMUX.IMUX13.DELAY |
| TRNTD38 | input | TCELL21:IMUX.IMUX14.DELAY |
| TRNTD39 | input | TCELL21:IMUX.IMUX15.DELAY |
| TRNTD4 | input | TCELL19:IMUX.IMUX8.DELAY |
| TRNTD40 | input | TCELL20:IMUX.IMUX12.DELAY |
| TRNTD41 | input | TCELL20:IMUX.IMUX13.DELAY |
| TRNTD42 | input | TCELL18:IMUX.IMUX12.DELAY |
| TRNTD43 | input | TCELL18:IMUX.IMUX13.DELAY |
| TRNTD44 | input | TCELL18:IMUX.IMUX14.DELAY |
| TRNTD45 | input | TCELL18:IMUX.IMUX15.DELAY |
| TRNTD46 | input | TCELL17:IMUX.IMUX8.DELAY |
| TRNTD47 | input | TCELL17:IMUX.IMUX9.DELAY |
| TRNTD48 | input | TCELL17:IMUX.IMUX10.DELAY |
| TRNTD49 | input | TCELL17:IMUX.IMUX11.DELAY |
| TRNTD5 | input | TCELL19:IMUX.IMUX9.DELAY |
| TRNTD50 | input | TCELL16:IMUX.IMUX4.DELAY |
| TRNTD51 | input | TCELL16:IMUX.IMUX5.DELAY |
| TRNTD52 | input | TCELL16:IMUX.IMUX6.DELAY |
| TRNTD53 | input | TCELL16:IMUX.IMUX7.DELAY |
| TRNTD54 | input | TCELL15:IMUX.IMUX4.DELAY |
| TRNTD55 | input | TCELL15:IMUX.IMUX5.DELAY |
| TRNTD56 | input | TCELL15:IMUX.IMUX6.DELAY |
| TRNTD57 | input | TCELL15:IMUX.IMUX7.DELAY |
| TRNTD58 | input | TCELL14:IMUX.IMUX0.DELAY |
| TRNTD59 | input | TCELL14:IMUX.IMUX1.DELAY |
| TRNTD6 | input | TCELL19:IMUX.IMUX10.DELAY |
| TRNTD60 | input | TCELL14:IMUX.IMUX2.DELAY |
| TRNTD61 | input | TCELL14:IMUX.IMUX3.DELAY |
| TRNTD62 | input | TCELL13:IMUX.IMUX0.DELAY |
| TRNTD63 | input | TCELL13:IMUX.IMUX1.DELAY |
| TRNTD64 | input | TCELL13:IMUX.IMUX2.DELAY |
| TRNTD65 | input | TCELL13:IMUX.IMUX3.DELAY |
| TRNTD66 | input | TCELL12:IMUX.IMUX0.DELAY |
| TRNTD67 | input | TCELL12:IMUX.IMUX1.DELAY |
| TRNTD68 | input | TCELL12:IMUX.IMUX2.DELAY |
| TRNTD69 | input | TCELL12:IMUX.IMUX3.DELAY |
| TRNTD7 | input | TCELL19:IMUX.IMUX11.DELAY |
| TRNTD70 | input | TCELL11:IMUX.IMUX0.DELAY |
| TRNTD71 | input | TCELL11:IMUX.IMUX1.DELAY |
| TRNTD72 | input | TCELL11:IMUX.IMUX2.DELAY |
| TRNTD73 | input | TCELL11:IMUX.IMUX3.DELAY |
| TRNTD74 | input | TCELL10:IMUX.IMUX0.DELAY |
| TRNTD75 | input | TCELL10:IMUX.IMUX1.DELAY |
| TRNTD76 | input | TCELL10:IMUX.IMUX2.DELAY |
| TRNTD77 | input | TCELL10:IMUX.IMUX3.DELAY |
| TRNTD78 | input | TCELL3:IMUX.IMUX8.DELAY |
| TRNTD79 | input | TCELL2:IMUX.IMUX8.DELAY |
| TRNTD8 | input | TCELL20:IMUX.IMUX8.DELAY |
| TRNTD80 | input | TCELL2:IMUX.IMUX9.DELAY |
| TRNTD81 | input | TCELL2:IMUX.IMUX10.DELAY |
| TRNTD82 | input | TCELL2:IMUX.IMUX11.DELAY |
| TRNTD83 | input | TCELL1:IMUX.IMUX8.DELAY |
| TRNTD84 | input | TCELL1:IMUX.IMUX9.DELAY |
| TRNTD85 | input | TCELL1:IMUX.IMUX10.DELAY |
| TRNTD86 | input | TCELL1:IMUX.IMUX11.DELAY |
| TRNTD87 | input | TCELL0:IMUX.IMUX8.DELAY |
| TRNTD88 | input | TCELL0:IMUX.IMUX9.DELAY |
| TRNTD89 | input | TCELL0:IMUX.IMUX10.DELAY |
| TRNTD9 | input | TCELL20:IMUX.IMUX9.DELAY |
| TRNTD90 | input | TCELL0:IMUX.IMUX11.DELAY |
| TRNTD91 | input | TCELL26:IMUX.IMUX3.DELAY |
| TRNTD92 | input | TCELL27:IMUX.IMUX0.DELAY |
| TRNTD93 | input | TCELL27:IMUX.IMUX1.DELAY |
| TRNTD94 | input | TCELL27:IMUX.IMUX2.DELAY |
| TRNTD95 | input | TCELL27:IMUX.IMUX3.DELAY |
| TRNTD96 | input | TCELL28:IMUX.IMUX0.DELAY |
| TRNTD97 | input | TCELL28:IMUX.IMUX1.DELAY |
| TRNTD98 | input | TCELL28:IMUX.IMUX2.DELAY |
| TRNTD99 | input | TCELL28:IMUX.IMUX3.DELAY |
| TRNTDLLPDATA0 | input | TCELL40:IMUX.IMUX1.DELAY |
| TRNTDLLPDATA1 | input | TCELL40:IMUX.IMUX2.DELAY |
| TRNTDLLPDATA10 | input | TCELL42:IMUX.IMUX3.DELAY |
| TRNTDLLPDATA11 | input | TCELL43:IMUX.IMUX0.DELAY |
| TRNTDLLPDATA12 | input | TCELL43:IMUX.IMUX1.DELAY |
| TRNTDLLPDATA13 | input | TCELL43:IMUX.IMUX2.DELAY |
| TRNTDLLPDATA14 | input | TCELL43:IMUX.IMUX3.DELAY |
| TRNTDLLPDATA15 | input | TCELL44:IMUX.IMUX0.DELAY |
| TRNTDLLPDATA16 | input | TCELL44:IMUX.IMUX1.DELAY |
| TRNTDLLPDATA17 | input | TCELL44:IMUX.IMUX2.DELAY |
| TRNTDLLPDATA18 | input | TCELL44:IMUX.IMUX3.DELAY |
| TRNTDLLPDATA19 | input | TCELL45:IMUX.IMUX0.DELAY |
| TRNTDLLPDATA2 | input | TCELL40:IMUX.IMUX3.DELAY |
| TRNTDLLPDATA20 | input | TCELL45:IMUX.IMUX1.DELAY |
| TRNTDLLPDATA21 | input | TCELL45:IMUX.IMUX2.DELAY |
| TRNTDLLPDATA22 | input | TCELL45:IMUX.IMUX3.DELAY |
| TRNTDLLPDATA23 | input | TCELL46:IMUX.IMUX0.DELAY |
| TRNTDLLPDATA24 | input | TCELL46:IMUX.IMUX1.DELAY |
| TRNTDLLPDATA25 | input | TCELL46:IMUX.IMUX2.DELAY |
| TRNTDLLPDATA26 | input | TCELL46:IMUX.IMUX3.DELAY |
| TRNTDLLPDATA27 | input | TCELL47:IMUX.IMUX0.DELAY |
| TRNTDLLPDATA28 | input | TCELL47:IMUX.IMUX1.DELAY |
| TRNTDLLPDATA29 | input | TCELL47:IMUX.IMUX2.DELAY |
| TRNTDLLPDATA3 | input | TCELL41:IMUX.IMUX0.DELAY |
| TRNTDLLPDATA30 | input | TCELL47:IMUX.IMUX3.DELAY |
| TRNTDLLPDATA31 | input | TCELL48:IMUX.IMUX0.DELAY |
| TRNTDLLPDATA4 | input | TCELL41:IMUX.IMUX1.DELAY |
| TRNTDLLPDATA5 | input | TCELL41:IMUX.IMUX2.DELAY |
| TRNTDLLPDATA6 | input | TCELL41:IMUX.IMUX3.DELAY |
| TRNTDLLPDATA7 | input | TCELL42:IMUX.IMUX0.DELAY |
| TRNTDLLPDATA8 | input | TCELL42:IMUX.IMUX1.DELAY |
| TRNTDLLPDATA9 | input | TCELL42:IMUX.IMUX2.DELAY |
| TRNTDLLPDSTRDY | output | TCELL36:OUT11.TMIN |
| TRNTDLLPSRCRDY | input | TCELL48:IMUX.IMUX1.DELAY |
| TRNTDSTRDY0 | output | TCELL10:OUT1.TMIN |
| TRNTDSTRDY1 | output | TCELL15:OUT1.TMIN |
| TRNTDSTRDY2 | output | TCELL0:OUT3.TMIN |
| TRNTDSTRDY3 | output | TCELL24:OUT1.TMIN |
| TRNTECRCGEN | input | TCELL37:IMUX.IMUX3.DELAY |
| TRNTEOF | input | TCELL36:IMUX.IMUX3.DELAY |
| TRNTERRDROP | output | TCELL28:OUT2.TMIN |
| TRNTERRFWD | input | TCELL37:IMUX.IMUX2.DELAY |
| TRNTREM0 | input | TCELL36:IMUX.IMUX0.DELAY |
| TRNTREM1 | input | TCELL36:IMUX.IMUX1.DELAY |
| TRNTSOF | input | TCELL36:IMUX.IMUX2.DELAY |
| TRNTSRCDSC | input | TCELL37:IMUX.IMUX1.DELAY |
| TRNTSRCRDY | input | TCELL37:IMUX.IMUX0.DELAY |
| TRNTSTR | input | TCELL38:IMUX.IMUX0.DELAY |
| USERCLK | input | TCELL12:IMUX.CLK0 |
| USERCLK2 | input | TCELL12:IMUX.CLK1 |
| USERCLKPREBUF | input | TCELL0:IMUX.CLK0 |
| USERCLKPREBUFEN | input | TCELL0:IMUX.CLK1 |
| USERRSTN | output | TCELL8:OUT12.TMIN |
| XILUNCONNOUT0 | output | TCELL4:OUT23.TMIN |
| XILUNCONNOUT1 | output | TCELL3:OUT21.TMIN |
| XILUNCONNOUT10 | output | TCELL27:OUT23.TMIN |
| XILUNCONNOUT11 | output | TCELL28:OUT22.TMIN |
| XILUNCONNOUT12 | output | TCELL28:OUT23.TMIN |
| XILUNCONNOUT13 | output | TCELL29:OUT22.TMIN |
| XILUNCONNOUT14 | output | TCELL29:OUT23.TMIN |
| XILUNCONNOUT15 | output | TCELL30:OUT22.TMIN |
| XILUNCONNOUT16 | output | TCELL30:OUT23.TMIN |
| XILUNCONNOUT17 | output | TCELL31:OUT22.TMIN |
| XILUNCONNOUT18 | output | TCELL31:OUT23.TMIN |
| XILUNCONNOUT19 | output | TCELL32:OUT22.TMIN |
| XILUNCONNOUT2 | output | TCELL3:OUT23.TMIN |
| XILUNCONNOUT20 | output | TCELL32:OUT23.TMIN |
| XILUNCONNOUT21 | output | TCELL33:OUT22.TMIN |
| XILUNCONNOUT22 | output | TCELL33:OUT23.TMIN |
| XILUNCONNOUT23 | output | TCELL34:OUT22.TMIN |
| XILUNCONNOUT24 | output | TCELL34:OUT23.TMIN |
| XILUNCONNOUT25 | output | TCELL35:OUT22.TMIN |
| XILUNCONNOUT26 | output | TCELL35:OUT23.TMIN |
| XILUNCONNOUT27 | output | TCELL36:OUT23.TMIN |
| XILUNCONNOUT28 | output | TCELL20:OUT23.TMIN |
| XILUNCONNOUT29 | output | TCELL18:OUT23.TMIN |
| XILUNCONNOUT3 | output | TCELL2:OUT23.TMIN |
| XILUNCONNOUT30 | output | TCELL15:OUT23.TMIN |
| XILUNCONNOUT31 | output | TCELL13:OUT23.TMIN |
| XILUNCONNOUT32 | output | TCELL12:OUT23.TMIN |
| XILUNCONNOUT33 | output | TCELL11:OUT23.TMIN |
| XILUNCONNOUT34 | output | TCELL10:OUT23.TMIN |
| XILUNCONNOUT35 | output | TCELL9:OUT23.TMIN |
| XILUNCONNOUT36 | output | TCELL8:OUT22.TMIN |
| XILUNCONNOUT37 | output | TCELL6:OUT14.TMIN |
| XILUNCONNOUT38 | output | TCELL7:OUT21.TMIN |
| XILUNCONNOUT39 | output | TCELL5:OUT22.TMIN |
| XILUNCONNOUT4 | output | TCELL1:OUT23.TMIN |
| XILUNCONNOUT5 | output | TCELL0:OUT23.TMIN |
| XILUNCONNOUT6 | output | TCELL25:OUT23.TMIN |
| XILUNCONNOUT7 | output | TCELL26:OUT22.TMIN |
| XILUNCONNOUT8 | output | TCELL26:OUT23.TMIN |
| XILUNCONNOUT9 | output | TCELL27:OUT22.TMIN |
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:IMUX.CLK0 | PCIE.USERCLKPREBUF |
| TCELL0:IMUX.CLK1 | PCIE.USERCLKPREBUFEN |
| TCELL0:IMUX.CTRL0 | PCIE.SYSRSTN |
| TCELL0:IMUX.CTRL1 | PCIE.CMRSTN |
| TCELL0:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA0 |
| TCELL0:IMUX.IMUX1.DELAY | PCIE.MIMTXRDATA1 |
| TCELL0:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA2 |
| TCELL0:IMUX.IMUX3.DELAY | PCIE.MIMTXRDATA3 |
| TCELL0:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA62 |
| TCELL0:IMUX.IMUX5.DELAY | PCIE.MIMTXRDATA63 |
| TCELL0:IMUX.IMUX6.DELAY | PCIE.MIMTXRDATA64 |
| TCELL0:IMUX.IMUX7.DELAY | PCIE.MIMTXRDATA65 |
| TCELL0:IMUX.IMUX8.DELAY | PCIE.TRNTD87 |
| TCELL0:IMUX.IMUX9.DELAY | PCIE.TRNTD88 |
| TCELL0:IMUX.IMUX10.DELAY | PCIE.TRNTD89 |
| TCELL0:IMUX.IMUX11.DELAY | PCIE.TRNTD90 |
| TCELL0:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG70 |
| TCELL0:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG71 |
| TCELL0:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG72 |
| TCELL0:IMUX.IMUX15.DELAY | PCIE.CFGERRAERHEADERLOG73 |
| TCELL0:IMUX.IMUX16.DELAY | PCIE.CFGPORTNUMBER0 |
| TCELL0:IMUX.IMUX17.DELAY | PCIE.CFGPORTNUMBER1 |
| TCELL0:IMUX.IMUX18.DELAY | PCIE.CFGPORTNUMBER2 |
| TCELL0:IMUX.IMUX19.DELAY | PCIE.CFGPORTNUMBER3 |
| TCELL0:IMUX.IMUX20.DELAY | PCIE.CFGVENDID15 |
| TCELL0:OUT0.TMIN | PCIE.PIPETX7DATA12 |
| TCELL0:OUT1.TMIN | PCIE.MIMTXWDATA40 |
| TCELL0:OUT2.TMIN | PCIE.PIPETX7DATA14 |
| TCELL0:OUT3.TMIN | PCIE.TRNTDSTRDY2 |
| TCELL0:OUT4.TMIN | PCIE.PIPETX7DATA13 |
| TCELL0:OUT5.TMIN | PCIE.TRNFCPD6 |
| TCELL0:OUT6.TMIN | PCIE.PIPETX7DATA15 |
| TCELL0:OUT7.TMIN | PCIE.TRNFCPD7 |
| TCELL0:OUT8.TMIN | PCIE.TRNFCPD8 |
| TCELL0:OUT9.TMIN | PCIE.MIMTXWDATA37 |
| TCELL0:OUT10.TMIN | PCIE.MIMTXWDATA56 |
| TCELL0:OUT11.TMIN | PCIE.MIMTXWDATA36 |
| TCELL0:OUT12.TMIN | PCIE.MIMTXWDATA52 |
| TCELL0:OUT13.TMIN | PCIE.MIMTXWDATA54 |
| TCELL0:OUT14.TMIN | PCIE.MIMTXWDATA42 |
| TCELL0:OUT15.TMIN | PCIE.EDTCHANNELSOUT1 |
| TCELL0:OUT16.TMIN | PCIE.PIPETX7CHARISK1 |
| TCELL0:OUT17.TMIN | PCIE.MIMTXWDATA58 |
| TCELL0:OUT18.TMIN | PCIE.MIMTXWDATA38 |
| TCELL0:OUT19.TMIN | PCIE.EDTCHANNELSOUT2 |
| TCELL0:OUT20.TMIN | PCIE.EDTCHANNELSOUT3 |
| TCELL0:OUT21.TMIN | PCIE.EDTCHANNELSOUT4 |
| TCELL0:OUT22.TMIN | PCIE.DBGVECB35 |
| TCELL0:OUT23.TMIN | PCIE.XILUNCONNOUT5 |
| TCELL1:IMUX.CTRL0 | PCIE.CMSTICKYRSTN |
| TCELL1:IMUX.CTRL1 | PCIE.FUNCLVLRSTN |
| TCELL1:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA4 |
| TCELL1:IMUX.IMUX1.DELAY | PCIE.MIMTXRDATA5 |
| TCELL1:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA6 |
| TCELL1:IMUX.IMUX3.DELAY | PCIE.MIMTXRDATA7 |
| TCELL1:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA58 |
| TCELL1:IMUX.IMUX5.DELAY | PCIE.MIMTXRDATA59 |
| TCELL1:IMUX.IMUX6.DELAY | PCIE.MIMTXRDATA60 |
| TCELL1:IMUX.IMUX7.DELAY | PCIE.MIMTXRDATA61 |
| TCELL1:IMUX.IMUX8.DELAY | PCIE.TRNTD83 |
| TCELL1:IMUX.IMUX9.DELAY | PCIE.TRNTD84 |
| TCELL1:IMUX.IMUX10.DELAY | PCIE.TRNTD85 |
| TCELL1:IMUX.IMUX11.DELAY | PCIE.TRNTD86 |
| TCELL1:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG66 |
| TCELL1:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG67 |
| TCELL1:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG68 |
| TCELL1:IMUX.IMUX15.DELAY | PCIE.CFGERRAERHEADERLOG69 |
| TCELL1:IMUX.IMUX16.DELAY | PCIE.CFGDSDEVICENUMBER4 |
| TCELL1:IMUX.IMUX17.DELAY | PCIE.CFGDSFUNCTIONNUMBER0 |
| TCELL1:IMUX.IMUX18.DELAY | PCIE.CFGDSFUNCTIONNUMBER1 |
| TCELL1:IMUX.IMUX19.DELAY | PCIE.CFGDSFUNCTIONNUMBER2 |
| TCELL1:IMUX.IMUX20.DELAY | PCIE.CFGVENDID14 |
| TCELL1:OUT0.TMIN | PCIE.TRNFCPD2 |
| TCELL1:OUT1.TMIN | PCIE.TRNFCPD3 |
| TCELL1:OUT2.TMIN | PCIE.TRNFCPD4 |
| TCELL1:OUT3.TMIN | PCIE.TRNFCPD5 |
| TCELL1:OUT4.TMIN | PCIE.TL2ERRHDR18 |
| TCELL1:OUT5.TMIN | PCIE.MIMTXWDATA62 |
| TCELL1:OUT6.TMIN | PCIE.MIMTXWADDR1 |
| TCELL1:OUT7.TMIN | PCIE.MIMTXWDATA50 |
| TCELL1:OUT8.TMIN | PCIE.MIMTXWDATA44 |
| TCELL1:OUT9.TMIN | PCIE.PIPETX7DATA8 |
| TCELL1:OUT10.TMIN | PCIE.MIMTXWADDR12 |
| TCELL1:OUT11.TMIN | PCIE.PIPETX7DATA10 |
| TCELL1:OUT12.TMIN | PCIE.MIMTXWDATA60 |
| TCELL1:OUT13.TMIN | PCIE.PIPETX7DATA9 |
| TCELL1:OUT14.TMIN | PCIE.MIMTXWDATA48 |
| TCELL1:OUT15.TMIN | PCIE.PIPETX7DATA11 |
| TCELL1:OUT16.TMIN | PCIE.MIMTXWDATA64 |
| TCELL1:OUT17.TMIN | PCIE.EDTCHANNELSOUT5 |
| TCELL1:OUT18.TMIN | PCIE.EDTCHANNELSOUT6 |
| TCELL1:OUT19.TMIN | PCIE.MIMTXWDATA46 |
| TCELL1:OUT20.TMIN | PCIE.EDTCHANNELSOUT7 |
| TCELL1:OUT21.TMIN | PCIE.EDTCHANNELSOUT8 |
| TCELL1:OUT22.TMIN | PCIE.DBGVECB34 |
| TCELL1:OUT23.TMIN | PCIE.XILUNCONNOUT4 |
| TCELL2:IMUX.CTRL0 | PCIE.TLRSTN |
| TCELL2:IMUX.CTRL1 | PCIE.DLRSTN |
| TCELL2:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA8 |
| TCELL2:IMUX.IMUX1.DELAY | PCIE.MIMTXRDATA9 |
| TCELL2:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA10 |
| TCELL2:IMUX.IMUX3.DELAY | PCIE.MIMTXRDATA11 |
| TCELL2:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA54 |
| TCELL2:IMUX.IMUX5.DELAY | PCIE.MIMTXRDATA55 |
| TCELL2:IMUX.IMUX6.DELAY | PCIE.MIMTXRDATA56 |
| TCELL2:IMUX.IMUX7.DELAY | PCIE.MIMTXRDATA57 |
| TCELL2:IMUX.IMUX8.DELAY | PCIE.TRNTD79 |
| TCELL2:IMUX.IMUX9.DELAY | PCIE.TRNTD80 |
| TCELL2:IMUX.IMUX10.DELAY | PCIE.TRNTD81 |
| TCELL2:IMUX.IMUX11.DELAY | PCIE.TRNTD82 |
| TCELL2:IMUX.IMUX12.DELAY | PCIE.PLTRANSMITHOTRST |
| TCELL2:IMUX.IMUX13.DELAY | PCIE.CFGMGMTDI0 |
| TCELL2:IMUX.IMUX14.DELAY | PCIE.CFGMGMTDI1 |
| TCELL2:IMUX.IMUX15.DELAY | PCIE.CFGMGMTDI2 |
| TCELL2:IMUX.IMUX16.DELAY | PCIE.CFGERRAERHEADERLOG62 |
| TCELL2:IMUX.IMUX17.DELAY | PCIE.CFGERRAERHEADERLOG63 |
| TCELL2:IMUX.IMUX18.DELAY | PCIE.CFGERRAERHEADERLOG64 |
| TCELL2:IMUX.IMUX19.DELAY | PCIE.CFGERRAERHEADERLOG65 |
| TCELL2:IMUX.IMUX20.DELAY | PCIE.CFGDSDEVICENUMBER3 |
| TCELL2:OUT0.TMIN | PCIE.PIPETX7DATA4 |
| TCELL2:OUT1.TMIN | PCIE.PIPETX7POWERDOWN0 |
| TCELL2:OUT2.TMIN | PCIE.PIPETX7DATA6 |
| TCELL2:OUT3.TMIN | PCIE.PIPETX7ELECIDLE |
| TCELL2:OUT4.TMIN | PCIE.PIPETX7DATA5 |
| TCELL2:OUT5.TMIN | PCIE.MIMTXWDATA68 |
| TCELL2:OUT6.TMIN | PCIE.PIPETX7DATA7 |
| TCELL2:OUT7.TMIN | PCIE.PIPETX7POWERDOWN1 |
| TCELL2:OUT8.TMIN | PCIE.TRNFCPD1 |
| TCELL2:OUT9.TMIN | PCIE.PMVOUT |
| TCELL2:OUT10.TMIN | PCIE.MIMTXRADDR3 |
| TCELL2:OUT11.TMIN | PCIE.MIMTXWADDR6 |
| TCELL2:OUT12.TMIN | PCIE.DBGVECB30 |
| TCELL2:OUT13.TMIN | PCIE.DBGVECB31 |
| TCELL2:OUT14.TMIN | PCIE.MIMTXWDATA67 |
| TCELL2:OUT15.TMIN | PCIE.DBGVECB32 |
| TCELL2:OUT16.TMIN | PCIE.PIPETX7CHARISK0 |
| TCELL2:OUT17.TMIN | PCIE.MIMTXRADDR6 |
| TCELL2:OUT18.TMIN | PCIE.MIMTXWDATA66 |
| TCELL2:OUT19.TMIN | PCIE.MIMTXWDATA53 |
| TCELL2:OUT20.TMIN | PCIE.MIMTXWDATA55 |
| TCELL2:OUT21.TMIN | PCIE.MIMTXWDATA39 |
| TCELL2:OUT22.TMIN | PCIE.DBGVECB33 |
| TCELL2:OUT23.TMIN | PCIE.XILUNCONNOUT3 |
| TCELL3:IMUX.CTRL0 | PCIE.PLRSTN |
| TCELL3:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA12 |
| TCELL3:IMUX.IMUX1.DELAY | PCIE.MIMTXRDATA13 |
| TCELL3:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA14 |
| TCELL3:IMUX.IMUX3.DELAY | PCIE.MIMTXRDATA15 |
| TCELL3:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA50 |
| TCELL3:IMUX.IMUX5.DELAY | PCIE.MIMTXRDATA51 |
| TCELL3:IMUX.IMUX6.DELAY | PCIE.MIMTXRDATA52 |
| TCELL3:IMUX.IMUX7.DELAY | PCIE.MIMTXRDATA53 |
| TCELL3:IMUX.IMUX8.DELAY | PCIE.TRNTD78 |
| TCELL3:IMUX.IMUX9.DELAY | PCIE.CFGMGMTDI3 |
| TCELL3:IMUX.IMUX10.DELAY | PCIE.CFGMGMTDI4 |
| TCELL3:IMUX.IMUX11.DELAY | PCIE.CFGMGMTDI5 |
| TCELL3:IMUX.IMUX12.DELAY | PCIE.CFGMGMTDI6 |
| TCELL3:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG58 |
| TCELL3:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG59 |
| TCELL3:IMUX.IMUX15.DELAY | PCIE.CFGERRAERHEADERLOG60 |
| TCELL3:IMUX.IMUX16.DELAY | PCIE.CFGERRAERHEADERLOG61 |
| TCELL3:IMUX.IMUX34.DELAY | PCIE.PIPERX7DATA15 |
| TCELL3:IMUX.IMUX35.DELAY | PCIE.PIPERX7DATA14 |
| TCELL3:IMUX.IMUX38.DELAY | PCIE.PIPERX7DATA13 |
| TCELL3:IMUX.IMUX39.DELAY | PCIE.PIPERX7DATA12 |
| TCELL3:OUT0.TMIN | PCIE.TRNFCPH6 |
| TCELL3:OUT1.TMIN | PCIE.PIPERX7POLARITY |
| TCELL3:OUT2.TMIN | PCIE.MIMTXWADDR11 |
| TCELL3:OUT3.TMIN | PCIE.PIPETX7COMPLIANCE |
| TCELL3:OUT4.TMIN | PCIE.TRNFCPH7 |
| TCELL3:OUT5.TMIN | PCIE.TRNFCPD0 |
| TCELL3:OUT6.TMIN | PCIE.MIMTXWDATA61 |
| TCELL3:OUT7.TMIN | PCIE.DBGVECB26 |
| TCELL3:OUT8.TMIN | PCIE.DBGVECB27 |
| TCELL3:OUT9.TMIN | PCIE.PIPETX7DATA0 |
| TCELL3:OUT10.TMIN | PCIE.MIMTXWDATA63 |
| TCELL3:OUT11.TMIN | PCIE.PIPETX7DATA2 |
| TCELL3:OUT12.TMIN | PCIE.MIMTXWADDR8 |
| TCELL3:OUT13.TMIN | PCIE.PIPETX7DATA1 |
| TCELL3:OUT14.TMIN | PCIE.MIMTXWADDR5 |
| TCELL3:OUT15.TMIN | PCIE.PIPETX7DATA3 |
| TCELL3:OUT16.TMIN | PCIE.DBGVECB28 |
| TCELL3:OUT17.TMIN | PCIE.MIMTXWDATA45 |
| TCELL3:OUT18.TMIN | PCIE.MIMTXWDATA41 |
| TCELL3:OUT19.TMIN | PCIE.MIMTXWDATA43 |
| TCELL3:OUT20.TMIN | PCIE.DBGVECB29 |
| TCELL3:OUT21.TMIN | PCIE.XILUNCONNOUT1 |
| TCELL3:OUT22.TMIN | PCIE.MIMTXRADDR8 |
| TCELL3:OUT23.TMIN | PCIE.XILUNCONNOUT2 |
| TCELL4:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA16 |
| TCELL4:IMUX.IMUX1.DELAY | PCIE.MIMTXRDATA17 |
| TCELL4:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA18 |
| TCELL4:IMUX.IMUX3.DELAY | PCIE.MIMTXRDATA19 |
| TCELL4:IMUX.IMUX4.DELAY | PCIE.CFGMGMTDI7 |
| TCELL4:IMUX.IMUX5.DELAY | PCIE.CFGMGMTDI8 |
| TCELL4:IMUX.IMUX6.DELAY | PCIE.CFGMGMTDI9 |
| TCELL4:IMUX.IMUX7.DELAY | PCIE.CFGMGMTDI10 |
| TCELL4:IMUX.IMUX8.DELAY | PCIE.CFGERRAERHEADERLOG54 |
| TCELL4:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG55 |
| TCELL4:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG56 |
| TCELL4:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG57 |
| TCELL4:IMUX.IMUX16.DELAY | PCIE.PIPERX7CHARISK1 |
| TCELL4:IMUX.IMUX32.DELAY | PCIE.PIPERX7DATA11 |
| TCELL4:IMUX.IMUX33.DELAY | PCIE.PIPERX7DATA10 |
| TCELL4:IMUX.IMUX34.DELAY | PCIE.PIPERX7ELECIDLE |
| TCELL4:IMUX.IMUX35.DELAY | PCIE.PIPERX7STATUS2 |
| TCELL4:IMUX.IMUX36.DELAY | PCIE.PIPERX7DATA9 |
| TCELL4:IMUX.IMUX37.DELAY | PCIE.PIPERX7DATA8 |
| TCELL4:IMUX.IMUX38.DELAY | PCIE.PIPERX7STATUS1 |
| TCELL4:IMUX.IMUX39.DELAY | PCIE.PIPERX7STATUS0 |
| TCELL4:OUT0.TMIN | PCIE.PIPETX5DATA12 |
| TCELL4:OUT1.TMIN | PCIE.MIMTXWDATA16 |
| TCELL4:OUT2.TMIN | PCIE.PIPETX5DATA14 |
| TCELL4:OUT3.TMIN | PCIE.MIMTXRADDR9 |
| TCELL4:OUT4.TMIN | PCIE.PIPETX5DATA13 |
| TCELL4:OUT5.TMIN | PCIE.TRNFCPH5 |
| TCELL4:OUT6.TMIN | PCIE.PIPETX5DATA15 |
| TCELL4:OUT7.TMIN | PCIE.DBGVECB22 |
| TCELL4:OUT8.TMIN | PCIE.DBGVECB23 |
| TCELL4:OUT9.TMIN | PCIE.MIMTXWDATA57 |
| TCELL4:OUT10.TMIN | PCIE.MIMTXWADDR4 |
| TCELL4:OUT11.TMIN | PCIE.MIMTXWDATA59 |
| TCELL4:OUT12.TMIN | PCIE.DBGVECB24 |
| TCELL4:OUT13.TMIN | PCIE.MIMTXWDATA49 |
| TCELL4:OUT14.TMIN | PCIE.MIMTXRADDR4 |
| TCELL4:OUT15.TMIN | PCIE.MIMTXWADDR7 |
| TCELL4:OUT16.TMIN | PCIE.PIPETX5CHARISK1 |
| TCELL4:OUT17.TMIN | PCIE.MIMTXRADDR7 |
| TCELL4:OUT18.TMIN | PCIE.MIMTXWDATA47 |
| TCELL4:OUT19.TMIN | PCIE.DBGVECB25 |
| TCELL4:OUT20.TMIN | PCIE.MIMTXRADDR0 |
| TCELL4:OUT21.TMIN | PCIE.MIMTXWADDR9 |
| TCELL4:OUT22.TMIN | PCIE.PLDBGVEC11 |
| TCELL4:OUT23.TMIN | PCIE.XILUNCONNOUT0 |
| TCELL5:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA20 |
| TCELL5:IMUX.IMUX1.DELAY | PCIE.MIMTXRDATA21 |
| TCELL5:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA22 |
| TCELL5:IMUX.IMUX3.DELAY | PCIE.MIMTXRDATA23 |
| TCELL5:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA48 |
| TCELL5:IMUX.IMUX5.DELAY | PCIE.MIMTXRDATA49 |
| TCELL5:IMUX.IMUX6.DELAY | PCIE.PMVDIVIDE1 |
| TCELL5:IMUX.IMUX7.DELAY | PCIE.CFGMGMTDI11 |
| TCELL5:IMUX.IMUX8.DELAY | PCIE.CFGMGMTDI12 |
| TCELL5:IMUX.IMUX9.DELAY | PCIE.CFGMGMTDI13 |
| TCELL5:IMUX.IMUX10.DELAY | PCIE.CFGMGMTDI14 |
| TCELL5:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG50 |
| TCELL5:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG51 |
| TCELL5:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG52 |
| TCELL5:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG53 |
| TCELL5:IMUX.IMUX33.DELAY | PCIE.PIPERX7CHANISALIGNED |
| TCELL5:IMUX.IMUX34.DELAY | PCIE.PIPERX7DATA7 |
| TCELL5:IMUX.IMUX35.DELAY | PCIE.PIPERX7DATA6 |
| TCELL5:IMUX.IMUX36.DELAY | PCIE.PIPERX7VALID |
| TCELL5:IMUX.IMUX37.DELAY | PCIE.PIPERX7PHYSTATUS |
| TCELL5:IMUX.IMUX38.DELAY | PCIE.PIPERX7DATA5 |
| TCELL5:IMUX.IMUX39.DELAY | PCIE.PIPERX7DATA4 |
| TCELL5:OUT0.TMIN | PCIE.MIMTXWDATA20 |
| TCELL5:OUT1.TMIN | PCIE.MIMTXWDATA18 |
| TCELL5:OUT2.TMIN | PCIE.TRNFCPH2 |
| TCELL5:OUT3.TMIN | PCIE.TRNFCPH3 |
| TCELL5:OUT4.TMIN | PCIE.TRNFCPH4 |
| TCELL5:OUT5.TMIN | PCIE.MIMTXWDATA4 |
| TCELL5:OUT6.TMIN | PCIE.DBGVECB18 |
| TCELL5:OUT7.TMIN | PCIE.DBGVECB19 |
| TCELL5:OUT8.TMIN | PCIE.MIMTXRADDR11 |
| TCELL5:OUT9.TMIN | PCIE.PIPETX5DATA8 |
| TCELL5:OUT10.TMIN | PCIE.MIMTXWDATA65 |
| TCELL5:OUT11.TMIN | PCIE.PIPETX5DATA10 |
| TCELL5:OUT12.TMIN | PCIE.MIMTXWDATA2 |
| TCELL5:OUT13.TMIN | PCIE.PIPETX5DATA9 |
| TCELL5:OUT14.TMIN | PCIE.MIMTXWDATA51 |
| TCELL5:OUT15.TMIN | PCIE.PIPETX5DATA11 |
| TCELL5:OUT16.TMIN | PCIE.DBGVECB20 |
| TCELL5:OUT17.TMIN | PCIE.MIMTXWDATA0 |
| TCELL5:OUT18.TMIN | PCIE.DBGVECB21 |
| TCELL5:OUT19.TMIN | PCIE.MIMTXWDATA1 |
| TCELL5:OUT20.TMIN | PCIE.MIMTXWDATA6 |
| TCELL5:OUT21.TMIN | PCIE.PLDBGVEC10 |
| TCELL5:OUT22.TMIN | PCIE.XILUNCONNOUT39 |
| TCELL5:OUT23.TMIN | PCIE.MIMTXWADDR3 |
| TCELL6:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA24 |
| TCELL6:IMUX.IMUX1.DELAY | PCIE.MIMTXRDATA25 |
| TCELL6:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA26 |
| TCELL6:IMUX.IMUX3.DELAY | PCIE.MIMTXRDATA27 |
| TCELL6:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA44 |
| TCELL6:IMUX.IMUX5.DELAY | PCIE.MIMTXRDATA45 |
| TCELL6:IMUX.IMUX6.DELAY | PCIE.MIMTXRDATA46 |
| TCELL6:IMUX.IMUX7.DELAY | PCIE.MIMTXRDATA47 |
| TCELL6:IMUX.IMUX8.DELAY | PCIE.PMVDIVIDE0 |
| TCELL6:IMUX.IMUX9.DELAY | PCIE.CFGMGMTDI15 |
| TCELL6:IMUX.IMUX10.DELAY | PCIE.CFGMGMTDI16 |
| TCELL6:IMUX.IMUX11.DELAY | PCIE.CFGMGMTDI17 |
| TCELL6:IMUX.IMUX12.DELAY | PCIE.CFGMGMTDI18 |
| TCELL6:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG46 |
| TCELL6:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG47 |
| TCELL6:IMUX.IMUX15.DELAY | PCIE.CFGERRAERHEADERLOG48 |
| TCELL6:IMUX.IMUX16.DELAY | PCIE.PIPERX7CHARISK0 |
| TCELL6:IMUX.IMUX17.DELAY | PCIE.CFGERRAERHEADERLOG49 |
| TCELL6:IMUX.IMUX32.DELAY | PCIE.PIPERX7DATA3 |
| TCELL6:IMUX.IMUX33.DELAY | PCIE.PIPERX7DATA2 |
| TCELL6:IMUX.IMUX36.DELAY | PCIE.PIPERX7DATA1 |
| TCELL6:IMUX.IMUX37.DELAY | PCIE.PIPERX7DATA0 |
| TCELL6:OUT0.TMIN | PCIE.PIPETX5DATA4 |
| TCELL6:OUT1.TMIN | PCIE.PIPETX5POWERDOWN0 |
| TCELL6:OUT2.TMIN | PCIE.PIPETX5DATA6 |
| TCELL6:OUT3.TMIN | PCIE.PIPETX5ELECIDLE |
| TCELL6:OUT4.TMIN | PCIE.PIPETX5DATA5 |
| TCELL6:OUT5.TMIN | PCIE.MIMTXWDATA26 |
| TCELL6:OUT6.TMIN | PCIE.PIPETX5DATA7 |
| TCELL6:OUT7.TMIN | PCIE.PIPETX5POWERDOWN1 |
| TCELL6:OUT8.TMIN | PCIE.MIMTXREN |
| TCELL6:OUT9.TMIN | PCIE.DBGVECB16 |
| TCELL6:OUT10.TMIN | PCIE.MIMTXWDATA12 |
| TCELL6:OUT11.TMIN | PCIE.MIMTXRADDR1 |
| TCELL6:OUT12.TMIN | PCIE.MIMTXWEN |
| TCELL6:OUT13.TMIN | PCIE.DBGVECB17 |
| TCELL6:OUT14.TMIN | PCIE.XILUNCONNOUT37 |
| TCELL6:OUT15.TMIN | PCIE.MIMTXWDATA34 |
| TCELL6:OUT16.TMIN | PCIE.PIPETX5CHARISK0 |
| TCELL6:OUT17.TMIN | PCIE.MIMTXWDATA22 |
| TCELL6:OUT18.TMIN | PCIE.MIMTXWDATA24 |
| TCELL6:OUT19.TMIN | PCIE.MIMTXRADDR5 |
| TCELL6:OUT20.TMIN | PCIE.MIMTXWDATA30 |
| TCELL6:OUT21.TMIN | PCIE.MIMTXWDATA14 |
| TCELL6:OUT22.TMIN | PCIE.MIMTXWDATA8 |
| TCELL6:OUT23.TMIN | PCIE.MIMTXWDATA10 |
| TCELL7:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA28 |
| TCELL7:IMUX.IMUX1.DELAY | PCIE.MIMTXRDATA29 |
| TCELL7:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA30 |
| TCELL7:IMUX.IMUX3.DELAY | PCIE.MIMTXRDATA31 |
| TCELL7:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA40 |
| TCELL7:IMUX.IMUX5.DELAY | PCIE.MIMTXRDATA41 |
| TCELL7:IMUX.IMUX6.DELAY | PCIE.MIMTXRDATA42 |
| TCELL7:IMUX.IMUX7.DELAY | PCIE.MIMTXRDATA43 |
| TCELL7:IMUX.IMUX8.DELAY | PCIE.MIMTXRDATA68 |
| TCELL7:IMUX.IMUX9.DELAY | PCIE.PMVSELECT2 |
| TCELL7:IMUX.IMUX10.DELAY | PCIE.CFGMGMTDI19 |
| TCELL7:IMUX.IMUX11.DELAY | PCIE.CFGMGMTDI20 |
| TCELL7:IMUX.IMUX12.DELAY | PCIE.CFGMGMTDI21 |
| TCELL7:IMUX.IMUX13.DELAY | PCIE.CFGMGMTDI22 |
| TCELL7:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG42 |
| TCELL7:IMUX.IMUX15.DELAY | PCIE.CFGERRAERHEADERLOG43 |
| TCELL7:IMUX.IMUX16.DELAY | PCIE.CFGERRAERHEADERLOG44 |
| TCELL7:IMUX.IMUX17.DELAY | PCIE.CFGERRAERHEADERLOG45 |
| TCELL7:IMUX.IMUX34.DELAY | PCIE.PIPERX5DATA15 |
| TCELL7:IMUX.IMUX35.DELAY | PCIE.PIPERX5DATA14 |
| TCELL7:IMUX.IMUX38.DELAY | PCIE.PIPERX5DATA13 |
| TCELL7:IMUX.IMUX39.DELAY | PCIE.PIPERX5DATA12 |
| TCELL7:OUT0.TMIN | PCIE.TRNLNKUP |
| TCELL7:OUT1.TMIN | PCIE.PIPERX5POLARITY |
| TCELL7:OUT2.TMIN | PCIE.TRNFCPH0 |
| TCELL7:OUT3.TMIN | PCIE.PIPETX5COMPLIANCE |
| TCELL7:OUT4.TMIN | PCIE.MIMTXWDATA33 |
| TCELL7:OUT5.TMIN | PCIE.MIMTXWDATA17 |
| TCELL7:OUT6.TMIN | PCIE.TRNFCPH1 |
| TCELL7:OUT7.TMIN | PCIE.MIMTXWDATA3 |
| TCELL7:OUT8.TMIN | PCIE.MIMTXRADDR12 |
| TCELL7:OUT9.TMIN | PCIE.PIPETX5DATA0 |
| TCELL7:OUT10.TMIN | PCIE.DBGVECB12 |
| TCELL7:OUT11.TMIN | PCIE.PIPETX5DATA2 |
| TCELL7:OUT12.TMIN | PCIE.MIMTXWADDR2 |
| TCELL7:OUT13.TMIN | PCIE.PIPETX5DATA1 |
| TCELL7:OUT14.TMIN | PCIE.DBGVECB13 |
| TCELL7:OUT15.TMIN | PCIE.PIPETX5DATA3 |
| TCELL7:OUT16.TMIN | PCIE.MIMTXWDATA28 |
| TCELL7:OUT17.TMIN | PCIE.DBGVECB14 |
| TCELL7:OUT18.TMIN | PCIE.DBGVECB15 |
| TCELL7:OUT19.TMIN | PCIE.MIMTXWDATA32 |
| TCELL7:OUT20.TMIN | PCIE.PLDBGVEC9 |
| TCELL7:OUT21.TMIN | PCIE.XILUNCONNOUT38 |
| TCELL7:OUT22.TMIN | PCIE.MIMTXRADDR2 |
| TCELL7:OUT23.TMIN | PCIE.MIMTXWADDR0 |
| TCELL8:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA32 |
| TCELL8:IMUX.IMUX1.DELAY | PCIE.MIMTXRDATA33 |
| TCELL8:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA34 |
| TCELL8:IMUX.IMUX3.DELAY | PCIE.MIMTXRDATA35 |
| TCELL8:IMUX.IMUX4.DELAY | PCIE.PMVSELECT1 |
| TCELL8:IMUX.IMUX5.DELAY | PCIE.CFGMGMTDI23 |
| TCELL8:IMUX.IMUX6.DELAY | PCIE.CFGMGMTDI24 |
| TCELL8:IMUX.IMUX7.DELAY | PCIE.CFGMGMTDI25 |
| TCELL8:IMUX.IMUX8.DELAY | PCIE.CFGMGMTDI26 |
| TCELL8:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG38 |
| TCELL8:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG39 |
| TCELL8:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG40 |
| TCELL8:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG41 |
| TCELL8:IMUX.IMUX16.DELAY | PCIE.PIPERX5CHARISK1 |
| TCELL8:IMUX.IMUX32.DELAY | PCIE.PIPERX5DATA11 |
| TCELL8:IMUX.IMUX33.DELAY | PCIE.PIPERX5DATA10 |
| TCELL8:IMUX.IMUX34.DELAY | PCIE.PIPERX5ELECIDLE |
| TCELL8:IMUX.IMUX35.DELAY | PCIE.PIPERX5STATUS2 |
| TCELL8:IMUX.IMUX36.DELAY | PCIE.PIPERX5DATA9 |
| TCELL8:IMUX.IMUX37.DELAY | PCIE.PIPERX5DATA8 |
| TCELL8:IMUX.IMUX38.DELAY | PCIE.PIPERX5STATUS1 |
| TCELL8:IMUX.IMUX39.DELAY | PCIE.PIPERX5STATUS0 |
| TCELL8:OUT0.TMIN | PCIE.PIPETXDEEMPH |
| TCELL8:OUT1.TMIN | PCIE.TRNRBARHIT4 |
| TCELL8:OUT2.TMIN | PCIE.TRNRBARHIT5 |
| TCELL8:OUT3.TMIN | PCIE.TRNRBARHIT6 |
| TCELL8:OUT4.TMIN | PCIE.MIMTXWDATA19 |
| TCELL8:OUT5.TMIN | PCIE.MIMTXWDATA21 |
| TCELL8:OUT6.TMIN | PCIE.TRNRBARHIT7 |
| TCELL8:OUT7.TMIN | PCIE.TL2ERRHDR14 |
| TCELL8:OUT8.TMIN | PCIE.TL2ERRHDR15 |
| TCELL8:OUT9.TMIN | PCIE.TL2ERRHDR16 |
| TCELL8:OUT10.TMIN | PCIE.MIMTXWDATA25 |
| TCELL8:OUT11.TMIN | PCIE.TL2ERRHDR17 |
| TCELL8:OUT12.TMIN | PCIE.USERRSTN |
| TCELL8:OUT13.TMIN | PCIE.PLRECEIVEDHOTRST |
| TCELL8:OUT14.TMIN | PCIE.DBGVECA62 |
| TCELL8:OUT15.TMIN | PCIE.DBGVECA63 |
| TCELL8:OUT16.TMIN | PCIE.DBGVECB0 |
| TCELL8:OUT17.TMIN | PCIE.DBGVECB1 |
| TCELL8:OUT18.TMIN | PCIE.DBGVECB11 |
| TCELL8:OUT19.TMIN | PCIE.MIMTXWDATA7 |
| TCELL8:OUT20.TMIN | PCIE.MIMTXWDATA23 |
| TCELL8:OUT21.TMIN | PCIE.MIMTXWDATA9 |
| TCELL8:OUT22.TMIN | PCIE.XILUNCONNOUT36 |
| TCELL8:OUT23.TMIN | PCIE.MIMTXWADDR10 |
| TCELL9:IMUX.IMUX0.DELAY | PCIE.MIMTXRDATA36 |
| TCELL9:IMUX.IMUX1.DELAY | PCIE.MIMTXRDATA37 |
| TCELL9:IMUX.IMUX2.DELAY | PCIE.MIMTXRDATA38 |
| TCELL9:IMUX.IMUX3.DELAY | PCIE.MIMTXRDATA39 |
| TCELL9:IMUX.IMUX4.DELAY | PCIE.MIMTXRDATA66 |
| TCELL9:IMUX.IMUX5.DELAY | PCIE.MIMTXRDATA67 |
| TCELL9:IMUX.IMUX6.DELAY | PCIE.PMVSELECT0 |
| TCELL9:IMUX.IMUX7.DELAY | PCIE.CFGMGMTDI27 |
| TCELL9:IMUX.IMUX8.DELAY | PCIE.CFGMGMTDI28 |
| TCELL9:IMUX.IMUX9.DELAY | PCIE.CFGMGMTDI29 |
| TCELL9:IMUX.IMUX10.DELAY | PCIE.CFGMGMTDI30 |
| TCELL9:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG34 |
| TCELL9:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG35 |
| TCELL9:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG36 |
| TCELL9:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG37 |
| TCELL9:IMUX.IMUX33.DELAY | PCIE.PIPERX5CHANISALIGNED |
| TCELL9:IMUX.IMUX34.DELAY | PCIE.PIPERX5DATA7 |
| TCELL9:IMUX.IMUX35.DELAY | PCIE.PIPERX5DATA6 |
| TCELL9:IMUX.IMUX36.DELAY | PCIE.PIPERX5VALID |
| TCELL9:IMUX.IMUX37.DELAY | PCIE.PIPERX5PHYSTATUS |
| TCELL9:IMUX.IMUX38.DELAY | PCIE.PIPERX5DATA5 |
| TCELL9:IMUX.IMUX39.DELAY | PCIE.PIPERX5DATA4 |
| TCELL9:OUT0.TMIN | PCIE.TRNRBARHIT0 |
| TCELL9:OUT1.TMIN | PCIE.TRNRBARHIT1 |
| TCELL9:OUT2.TMIN | PCIE.TRNRBARHIT2 |
| TCELL9:OUT3.TMIN | PCIE.TRNRBARHIT3 |
| TCELL9:OUT4.TMIN | PCIE.MIMTXWDATA5 |
| TCELL9:OUT5.TMIN | PCIE.MIMTXWDATA13 |
| TCELL9:OUT6.TMIN | PCIE.TL2ERRHDR10 |
| TCELL9:OUT7.TMIN | PCIE.MIMTXWDATA31 |
| TCELL9:OUT8.TMIN | PCIE.MIMTXRADDR10 |
| TCELL9:OUT9.TMIN | PCIE.TL2ERRHDR11 |
| TCELL9:OUT10.TMIN | PCIE.TL2ERRHDR12 |
| TCELL9:OUT11.TMIN | PCIE.TL2ERRHDR13 |
| TCELL9:OUT12.TMIN | PCIE.RECEIVEDFUNCLVLRSTN |
| TCELL9:OUT13.TMIN | PCIE.MIMTXWDATA27 |
| TCELL9:OUT14.TMIN | PCIE.DBGVECA58 |
| TCELL9:OUT15.TMIN | PCIE.PIPETXRCVRDET |
| TCELL9:OUT16.TMIN | PCIE.MIMTXWDATA15 |
| TCELL9:OUT17.TMIN | PCIE.MIMTXWDATA35 |
| TCELL9:OUT18.TMIN | PCIE.MIMTXWDATA11 |
| TCELL9:OUT19.TMIN | PCIE.DBGVECA59 |
| TCELL9:OUT20.TMIN | PCIE.DBGVECA60 |
| TCELL9:OUT21.TMIN | PCIE.DBGVECA61 |
| TCELL9:OUT22.TMIN | PCIE.DBGVECB2 |
| TCELL9:OUT23.TMIN | PCIE.XILUNCONNOUT35 |
| TCELL10:IMUX.CLK0 | PCIE.EDTCLK |
| TCELL10:IMUX.IMUX0.DELAY | PCIE.TRNTD74 |
| TCELL10:IMUX.IMUX1.DELAY | PCIE.TRNTD75 |
| TCELL10:IMUX.IMUX2.DELAY | PCIE.TRNTD76 |
| TCELL10:IMUX.IMUX3.DELAY | PCIE.TRNTD77 |
| TCELL10:IMUX.IMUX4.DELAY | PCIE.PMVENABLEN |
| TCELL10:IMUX.IMUX5.DELAY | PCIE.CFGMGMTDI31 |
| TCELL10:IMUX.IMUX6.DELAY | PCIE.CFGMGMTBYTEENN0 |
| TCELL10:IMUX.IMUX7.DELAY | PCIE.CFGMGMTBYTEENN1 |
| TCELL10:IMUX.IMUX8.DELAY | PCIE.CFGMGMTBYTEENN2 |
| TCELL10:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG30 |
| TCELL10:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG31 |
| TCELL10:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG32 |
| TCELL10:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG33 |
| TCELL10:IMUX.IMUX13.DELAY | PCIE.CFGDSBUSNUMBER7 |
| TCELL10:IMUX.IMUX14.DELAY | PCIE.CFGDSDEVICENUMBER0 |
| TCELL10:IMUX.IMUX15.DELAY | PCIE.CFGDSDEVICENUMBER1 |
| TCELL10:IMUX.IMUX16.DELAY | PCIE.PIPERX5CHARISK0 |
| TCELL10:IMUX.IMUX17.DELAY | PCIE.CFGDSDEVICENUMBER2 |
| TCELL10:IMUX.IMUX32.DELAY | PCIE.PIPERX5DATA3 |
| TCELL10:IMUX.IMUX33.DELAY | PCIE.PIPERX5DATA2 |
| TCELL10:IMUX.IMUX36.DELAY | PCIE.PIPERX5DATA1 |
| TCELL10:IMUX.IMUX37.DELAY | PCIE.PIPERX5DATA0 |
| TCELL10:OUT0.TMIN | PCIE.TRNRSRCRDY |
| TCELL10:OUT1.TMIN | PCIE.TRNTDSTRDY0 |
| TCELL10:OUT2.TMIN | PCIE.MIMTXWDATA29 |
| TCELL10:OUT3.TMIN | PCIE.TRNRSRCDSC |
| TCELL10:OUT4.TMIN | PCIE.TRNRECRCERR |
| TCELL10:OUT5.TMIN | PCIE.TRNRERRFWD |
| TCELL10:OUT6.TMIN | PCIE.TL2ERRHDR6 |
| TCELL10:OUT7.TMIN | PCIE.TL2ERRHDR7 |
| TCELL10:OUT8.TMIN | PCIE.TL2ERRHDR8 |
| TCELL10:OUT9.TMIN | PCIE.TL2ERRHDR9 |
| TCELL10:OUT10.TMIN | PCIE.LNKCLKEN |
| TCELL10:OUT11.TMIN | PCIE.CFGMGMTDO0 |
| TCELL10:OUT12.TMIN | PCIE.CFGMGMTDO1 |
| TCELL10:OUT13.TMIN | PCIE.CFGMGMTDO2 |
| TCELL10:OUT14.TMIN | PCIE.CFGERRCPLRDYN |
| TCELL10:OUT15.TMIN | PCIE.CFGINTERRUPTRDYN |
| TCELL10:OUT16.TMIN | PCIE.CFGINTERRUPTMMENABLE0 |
| TCELL10:OUT17.TMIN | PCIE.CFGINTERRUPTMMENABLE1 |
| TCELL10:OUT18.TMIN | PCIE.DBGVECA54 |
| TCELL10:OUT19.TMIN | PCIE.DBGVECA55 |
| TCELL10:OUT20.TMIN | PCIE.DBGVECA56 |
| TCELL10:OUT21.TMIN | PCIE.DBGVECA57 |
| TCELL10:OUT22.TMIN | PCIE.DBGVECB3 |
| TCELL10:OUT23.TMIN | PCIE.XILUNCONNOUT34 |
| TCELL11:IMUX.CLK0 | PCIE.PIPECLK |
| TCELL11:IMUX.CLK1 | PCIE.DRPCLK |
| TCELL11:IMUX.IMUX0.DELAY | PCIE.TRNTD70 |
| TCELL11:IMUX.IMUX1.DELAY | PCIE.TRNTD71 |
| TCELL11:IMUX.IMUX2.DELAY | PCIE.TRNTD72 |
| TCELL11:IMUX.IMUX3.DELAY | PCIE.TRNTD73 |
| TCELL11:IMUX.IMUX4.DELAY | PCIE.EDTCHANNELSIN8 |
| TCELL11:IMUX.IMUX5.DELAY | PCIE.CFGMGMTBYTEENN3 |
| TCELL11:IMUX.IMUX6.DELAY | PCIE.CFGMGMTDWADDR0 |
| TCELL11:IMUX.IMUX7.DELAY | PCIE.CFGMGMTDWADDR1 |
| TCELL11:IMUX.IMUX8.DELAY | PCIE.CFGMGMTDWADDR2 |
| TCELL11:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG26 |
| TCELL11:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG27 |
| TCELL11:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG28 |
| TCELL11:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG29 |
| TCELL11:IMUX.IMUX13.DELAY | PCIE.CFGDSBUSNUMBER3 |
| TCELL11:IMUX.IMUX14.DELAY | PCIE.CFGDSBUSNUMBER4 |
| TCELL11:IMUX.IMUX15.DELAY | PCIE.CFGDSBUSNUMBER5 |
| TCELL11:IMUX.IMUX16.DELAY | PCIE.CFGDSBUSNUMBER6 |
| TCELL11:IMUX.IMUX17.DELAY | PCIE.CFGVENDID10 |
| TCELL11:IMUX.IMUX18.DELAY | PCIE.CFGVENDID11 |
| TCELL11:IMUX.IMUX19.DELAY | PCIE.CFGVENDID12 |
| TCELL11:IMUX.IMUX20.DELAY | PCIE.CFGVENDID13 |
| TCELL11:IMUX.IMUX21.DELAY | PCIE.PLDBGMODE0 |
| TCELL11:OUT0.TMIN | PCIE.PIPETX6DATA12 |
| TCELL11:OUT1.TMIN | PCIE.TRNRREM0 |
| TCELL11:OUT2.TMIN | PCIE.PIPETX6DATA14 |
| TCELL11:OUT3.TMIN | PCIE.TRNRREM1 |
| TCELL11:OUT4.TMIN | PCIE.PIPETX6DATA13 |
| TCELL11:OUT5.TMIN | PCIE.TRNRSOF |
| TCELL11:OUT6.TMIN | PCIE.PIPETX6DATA15 |
| TCELL11:OUT7.TMIN | PCIE.TRNREOF |
| TCELL11:OUT8.TMIN | PCIE.TL2ERRHDR2 |
| TCELL11:OUT9.TMIN | PCIE.PIPETXRESET |
| TCELL11:OUT10.TMIN | PCIE.TL2ERRHDR3 |
| TCELL11:OUT11.TMIN | PCIE.TL2ERRHDR4 |
| TCELL11:OUT12.TMIN | PCIE.TL2ERRHDR5 |
| TCELL11:OUT13.TMIN | PCIE.CFGMGMTDO3 |
| TCELL11:OUT14.TMIN | PCIE.CFGMGMTDO4 |
| TCELL11:OUT15.TMIN | PCIE.CFGMGMTDO5 |
| TCELL11:OUT16.TMIN | PCIE.PIPETX6CHARISK1 |
| TCELL11:OUT17.TMIN | PCIE.DBGVECA50 |
| TCELL11:OUT18.TMIN | PCIE.DBGVECA51 |
| TCELL11:OUT19.TMIN | PCIE.PIPETXRATE |
| TCELL11:OUT20.TMIN | PCIE.DBGVECA52 |
| TCELL11:OUT21.TMIN | PCIE.DBGVECA53 |
| TCELL11:OUT22.TMIN | PCIE.DBGVECB4 |
| TCELL11:OUT23.TMIN | PCIE.XILUNCONNOUT33 |
| TCELL12:IMUX.CLK0 | PCIE.USERCLK |
| TCELL12:IMUX.CLK1 | PCIE.USERCLK2 |
| TCELL12:IMUX.IMUX0.DELAY | PCIE.TRNTD66 |
| TCELL12:IMUX.IMUX1.DELAY | PCIE.TRNTD67 |
| TCELL12:IMUX.IMUX2.DELAY | PCIE.TRNTD68 |
| TCELL12:IMUX.IMUX3.DELAY | PCIE.TRNTD69 |
| TCELL12:IMUX.IMUX4.DELAY | PCIE.EDTCHANNELSIN7 |
| TCELL12:IMUX.IMUX5.DELAY | PCIE.CFGMGMTDWADDR3 |
| TCELL12:IMUX.IMUX6.DELAY | PCIE.CFGMGMTDWADDR4 |
| TCELL12:IMUX.IMUX7.DELAY | PCIE.CFGMGMTDWADDR5 |
| TCELL12:IMUX.IMUX8.DELAY | PCIE.CFGMGMTDWADDR6 |
| TCELL12:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG22 |
| TCELL12:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG23 |
| TCELL12:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG24 |
| TCELL12:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG25 |
| TCELL12:IMUX.IMUX13.DELAY | PCIE.CFGINTERRUPTSTATN |
| TCELL12:IMUX.IMUX14.DELAY | PCIE.CFGDSBUSNUMBER0 |
| TCELL12:IMUX.IMUX15.DELAY | PCIE.CFGDSBUSNUMBER1 |
| TCELL12:IMUX.IMUX16.DELAY | PCIE.CFGDSBUSNUMBER2 |
| TCELL12:IMUX.IMUX17.DELAY | PCIE.CFGVENDID6 |
| TCELL12:IMUX.IMUX18.DELAY | PCIE.CFGVENDID7 |
| TCELL12:IMUX.IMUX19.DELAY | PCIE.CFGVENDID8 |
| TCELL12:IMUX.IMUX20.DELAY | PCIE.CFGVENDID9 |
| TCELL12:IMUX.IMUX21.DELAY | PCIE.DBGSUBMODE |
| TCELL12:OUT0.TMIN | PCIE.TRNRD124 |
| TCELL12:OUT1.TMIN | PCIE.TRNRD125 |
| TCELL12:OUT2.TMIN | PCIE.TRNRD126 |
| TCELL12:OUT3.TMIN | PCIE.TRNRD127 |
| TCELL12:OUT4.TMIN | PCIE.LL2REPLAYROERR |
| TCELL12:OUT5.TMIN | PCIE.LL2REPLAYTOERR |
| TCELL12:OUT6.TMIN | PCIE.TL2ERRHDR0 |
| TCELL12:OUT7.TMIN | PCIE.TL2ERRHDR1 |
| TCELL12:OUT8.TMIN | PCIE.CFGMGMTDO6 |
| TCELL12:OUT9.TMIN | PCIE.PIPETX6DATA8 |
| TCELL12:OUT10.TMIN | PCIE.CFGMGMTDO7 |
| TCELL12:OUT11.TMIN | PCIE.PIPETX6DATA10 |
| TCELL12:OUT12.TMIN | PCIE.CFGMGMTDO8 |
| TCELL12:OUT13.TMIN | PCIE.PIPETX6DATA9 |
| TCELL12:OUT14.TMIN | PCIE.CFGMGMTDO9 |
| TCELL12:OUT15.TMIN | PCIE.PIPETX6DATA11 |
| TCELL12:OUT16.TMIN | PCIE.CFGMGMTRDWRDONEN |
| TCELL12:OUT17.TMIN | PCIE.CFGERRAERHEADERLOGSETN |
| TCELL12:OUT18.TMIN | PCIE.DBGVECA46 |
| TCELL12:OUT19.TMIN | PCIE.DBGVECA47 |
| TCELL12:OUT20.TMIN | PCIE.DBGVECA48 |
| TCELL12:OUT21.TMIN | PCIE.DBGVECA49 |
| TCELL12:OUT22.TMIN | PCIE.DBGVECB5 |
| TCELL12:OUT23.TMIN | PCIE.XILUNCONNOUT32 |
| TCELL13:IMUX.IMUX0.DELAY | PCIE.TRNTD62 |
| TCELL13:IMUX.IMUX1.DELAY | PCIE.TRNTD63 |
| TCELL13:IMUX.IMUX2.DELAY | PCIE.TRNTD64 |
| TCELL13:IMUX.IMUX3.DELAY | PCIE.TRNTD65 |
| TCELL13:IMUX.IMUX4.DELAY | PCIE.EDTCHANNELSIN6 |
| TCELL13:IMUX.IMUX5.DELAY | PCIE.CFGMGMTDWADDR7 |
| TCELL13:IMUX.IMUX6.DELAY | PCIE.CFGMGMTDWADDR8 |
| TCELL13:IMUX.IMUX7.DELAY | PCIE.CFGMGMTDWADDR9 |
| TCELL13:IMUX.IMUX8.DELAY | PCIE.CFGMGMTWRRW1CASRWN |
| TCELL13:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG18 |
| TCELL13:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG19 |
| TCELL13:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG20 |
| TCELL13:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG21 |
| TCELL13:IMUX.IMUX13.DELAY | PCIE.CFGINTERRUPTDI5 |
| TCELL13:IMUX.IMUX14.DELAY | PCIE.CFGINTERRUPTDI6 |
| TCELL13:IMUX.IMUX15.DELAY | PCIE.CFGINTERRUPTDI7 |
| TCELL13:IMUX.IMUX16.DELAY | PCIE.CFGINTERRUPTASSERTN |
| TCELL13:IMUX.IMUX17.DELAY | PCIE.CFGVENDID2 |
| TCELL13:IMUX.IMUX18.DELAY | PCIE.CFGVENDID3 |
| TCELL13:IMUX.IMUX19.DELAY | PCIE.CFGVENDID4 |
| TCELL13:IMUX.IMUX20.DELAY | PCIE.CFGVENDID5 |
| TCELL13:IMUX.IMUX21.DELAY | PCIE.DBGMODE1 |
| TCELL13:OUT0.TMIN | PCIE.PIPETX6DATA4 |
| TCELL13:OUT1.TMIN | PCIE.PIPETX6POWERDOWN0 |
| TCELL13:OUT2.TMIN | PCIE.PIPETX6DATA6 |
| TCELL13:OUT3.TMIN | PCIE.PIPETX6ELECIDLE |
| TCELL13:OUT4.TMIN | PCIE.PIPETX6DATA5 |
| TCELL13:OUT5.TMIN | PCIE.TRNRD120 |
| TCELL13:OUT6.TMIN | PCIE.PIPETX6DATA7 |
| TCELL13:OUT7.TMIN | PCIE.PIPETX6POWERDOWN1 |
| TCELL13:OUT8.TMIN | PCIE.TRNRD121 |
| TCELL13:OUT9.TMIN | PCIE.TRNRD122 |
| TCELL13:OUT10.TMIN | PCIE.TRNRD123 |
| TCELL13:OUT11.TMIN | PCIE.LL2RECEIVERERR |
| TCELL13:OUT12.TMIN | PCIE.LL2PROTOCOLERR |
| TCELL13:OUT13.TMIN | PCIE.LL2BADTLPERR |
| TCELL13:OUT14.TMIN | PCIE.LL2BADDLLPERR |
| TCELL13:OUT15.TMIN | PCIE.CFGMGMTDO10 |
| TCELL13:OUT16.TMIN | PCIE.PIPETX6CHARISK0 |
| TCELL13:OUT17.TMIN | PCIE.CFGMGMTDO11 |
| TCELL13:OUT18.TMIN | PCIE.DBGVECA42 |
| TCELL13:OUT19.TMIN | PCIE.DBGVECA43 |
| TCELL13:OUT20.TMIN | PCIE.DBGVECA44 |
| TCELL13:OUT21.TMIN | PCIE.DBGVECA45 |
| TCELL13:OUT22.TMIN | PCIE.DBGVECB6 |
| TCELL13:OUT23.TMIN | PCIE.XILUNCONNOUT31 |
| TCELL14:IMUX.IMUX0.DELAY | PCIE.TRNTD58 |
| TCELL14:IMUX.IMUX1.DELAY | PCIE.TRNTD59 |
| TCELL14:IMUX.IMUX2.DELAY | PCIE.TRNTD60 |
| TCELL14:IMUX.IMUX3.DELAY | PCIE.TRNTD61 |
| TCELL14:IMUX.IMUX4.DELAY | PCIE.EDTCHANNELSIN5 |
| TCELL14:IMUX.IMUX5.DELAY | PCIE.CFGMGMTWRREADONLYN |
| TCELL14:IMUX.IMUX6.DELAY | PCIE.CFGMGMTWRENN |
| TCELL14:IMUX.IMUX7.DELAY | PCIE.CFGMGMTRDENN |
| TCELL14:IMUX.IMUX8.DELAY | PCIE.CFGERRMALFORMEDN |
| TCELL14:IMUX.IMUX9.DELAY | PCIE.CFGERRAERHEADERLOG14 |
| TCELL14:IMUX.IMUX10.DELAY | PCIE.CFGERRAERHEADERLOG15 |
| TCELL14:IMUX.IMUX11.DELAY | PCIE.CFGERRAERHEADERLOG16 |
| TCELL14:IMUX.IMUX12.DELAY | PCIE.CFGERRAERHEADERLOG17 |
| TCELL14:IMUX.IMUX13.DELAY | PCIE.CFGINTERRUPTDI1 |
| TCELL14:IMUX.IMUX14.DELAY | PCIE.CFGINTERRUPTDI2 |
| TCELL14:IMUX.IMUX15.DELAY | PCIE.CFGINTERRUPTDI3 |
| TCELL14:IMUX.IMUX16.DELAY | PCIE.CFGINTERRUPTDI4 |
| TCELL14:IMUX.IMUX17.DELAY | PCIE.CFGVENDID1 |
| TCELL14:IMUX.IMUX34.DELAY | PCIE.PIPERX6DATA15 |
| TCELL14:IMUX.IMUX35.DELAY | PCIE.PIPERX6DATA14 |
| TCELL14:IMUX.IMUX38.DELAY | PCIE.PIPERX6DATA13 |
| TCELL14:IMUX.IMUX39.DELAY | PCIE.PIPERX6DATA12 |
| TCELL14:OUT0.TMIN | PCIE.TRNRD116 |
| TCELL14:OUT1.TMIN | PCIE.PIPERX6POLARITY |
| TCELL14:OUT2.TMIN | PCIE.TRNRD117 |
| TCELL14:OUT3.TMIN | PCIE.PIPETX6COMPLIANCE |
| TCELL14:OUT4.TMIN | PCIE.TRNRD118 |
| TCELL14:OUT5.TMIN | PCIE.TRNRD119 |
| TCELL14:OUT6.TMIN | PCIE.TL2ASPMSUSPENDREQ |
| TCELL14:OUT7.TMIN | PCIE.TL2ASPMSUSPENDCREDITCHECKOK |
| TCELL14:OUT8.TMIN | PCIE.PL2LINKUP |
| TCELL14:OUT9.TMIN | PCIE.PIPETX6DATA0 |
| TCELL14:OUT10.TMIN | PCIE.PL2RECEIVERERR |
| TCELL14:OUT11.TMIN | PCIE.PIPETX6DATA2 |
| TCELL14:OUT12.TMIN | PCIE.CFGMGMTDO12 |
| TCELL14:OUT13.TMIN | PCIE.PIPETX6DATA1 |
| TCELL14:OUT14.TMIN | PCIE.CFGMGMTDO13 |
| TCELL14:OUT15.TMIN | PCIE.PIPETX6DATA3 |
| TCELL14:OUT16.TMIN | PCIE.CFGMGMTDO14 |
| TCELL14:OUT17.TMIN | PCIE.CFGMGMTDO15 |
| TCELL14:OUT18.TMIN | PCIE.CFGMGMTDO31 |
| TCELL14:OUT19.TMIN | PCIE.DBGVECA38 |
| TCELL14:OUT20.TMIN | PCIE.DBGVECA39 |
| TCELL14:OUT21.TMIN | PCIE.DBGVECA40 |
| TCELL14:OUT22.TMIN | PCIE.DBGVECA41 |
| TCELL14:OUT23.TMIN | PCIE.DBGVECB7 |
| TCELL15:IMUX.IMUX0.DELAY | PCIE.MIMRXRDATA0 |
| TCELL15:IMUX.IMUX1.DELAY | PCIE.MIMRXRDATA1 |
| TCELL15:IMUX.IMUX2.DELAY | PCIE.MIMRXRDATA2 |
| TCELL15:IMUX.IMUX3.DELAY | PCIE.MIMRXRDATA3 |
| TCELL15:IMUX.IMUX4.DELAY | PCIE.TRNTD54 |
| TCELL15:IMUX.IMUX5.DELAY | PCIE.TRNTD55 |
| TCELL15:IMUX.IMUX6.DELAY | PCIE.TRNTD56 |
| TCELL15:IMUX.IMUX7.DELAY | PCIE.TRNTD57 |
| TCELL15:IMUX.IMUX8.DELAY | PCIE.EDTCHANNELSIN4 |
| TCELL15:IMUX.IMUX9.DELAY | PCIE.CFGERRCORN |
| TCELL15:IMUX.IMUX10.DELAY | PCIE.CFGERRURN |
| TCELL15:IMUX.IMUX11.DELAY | PCIE.CFGERRECRCN |
| TCELL15:IMUX.IMUX12.DELAY | PCIE.CFGERRCPLTIMEOUTN |
| TCELL15:IMUX.IMUX16.DELAY | PCIE.PIPERX6CHARISK1 |
| TCELL15:IMUX.IMUX32.DELAY | PCIE.PIPERX6DATA11 |
| TCELL15:IMUX.IMUX33.DELAY | PCIE.PIPERX6DATA10 |
| TCELL15:IMUX.IMUX34.DELAY | PCIE.PIPERX6ELECIDLE |
| TCELL15:IMUX.IMUX35.DELAY | PCIE.PIPERX6STATUS2 |
| TCELL15:IMUX.IMUX36.DELAY | PCIE.PIPERX6DATA9 |
| TCELL15:IMUX.IMUX37.DELAY | PCIE.PIPERX6DATA8 |
| TCELL15:IMUX.IMUX38.DELAY | PCIE.PIPERX6STATUS1 |
| TCELL15:IMUX.IMUX39.DELAY | PCIE.PIPERX6STATUS0 |
| TCELL15:OUT0.TMIN | PCIE.PIPETX4DATA12 |
| TCELL15:OUT1.TMIN | PCIE.TRNTDSTRDY1 |
| TCELL15:OUT2.TMIN | PCIE.PIPETX4DATA14 |
| TCELL15:OUT3.TMIN | PCIE.TRNRD112 |
| TCELL15:OUT4.TMIN | PCIE.PIPETX4DATA13 |
| TCELL15:OUT5.TMIN | PCIE.TRNRD113 |
| TCELL15:OUT6.TMIN | PCIE.PIPETX4DATA15 |
| TCELL15:OUT7.TMIN | PCIE.TRNRD114 |
| TCELL15:OUT8.TMIN | PCIE.TRNRD115 |
| TCELL15:OUT9.TMIN | PCIE.MIMRXWDATA37 |
| TCELL15:OUT10.TMIN | PCIE.DBGVECA34 |
| TCELL15:OUT11.TMIN | PCIE.DBGVECA35 |
| TCELL15:OUT12.TMIN | PCIE.MIMRXWDATA38 |
| TCELL15:OUT13.TMIN | PCIE.MIMRXWDATA40 |
| TCELL15:OUT14.TMIN | PCIE.MIMRXWDATA42 |
| TCELL15:OUT15.TMIN | PCIE.MIMRXWDATA58 |
| TCELL15:OUT16.TMIN | PCIE.PIPETX4CHARISK1 |
| TCELL15:OUT17.TMIN | PCIE.MIMRXWDATA36 |
| TCELL15:OUT18.TMIN | PCIE.MIMRXWDATA52 |
| TCELL15:OUT19.TMIN | PCIE.DBGVECA36 |
| TCELL15:OUT20.TMIN | PCIE.DBGVECA37 |
| TCELL15:OUT21.TMIN | PCIE.MIMRXRADDR12 |
| TCELL15:OUT22.TMIN | PCIE.DBGVECB8 |
| TCELL15:OUT23.TMIN | PCIE.XILUNCONNOUT30 |
| TCELL16:IMUX.IMUX0.DELAY | PCIE.MIMRXRDATA4 |
| TCELL16:IMUX.IMUX1.DELAY | PCIE.MIMRXRDATA5 |
| TCELL16:IMUX.IMUX2.DELAY | PCIE.MIMRXRDATA6 |
| TCELL16:IMUX.IMUX3.DELAY | PCIE.MIMRXRDATA7 |
| TCELL16:IMUX.IMUX4.DELAY | PCIE.TRNTD50 |
| TCELL16:IMUX.IMUX5.DELAY | PCIE.TRNTD51 |
| TCELL16:IMUX.IMUX6.DELAY | PCIE.TRNTD52 |
| TCELL16:IMUX.IMUX7.DELAY | PCIE.TRNTD53 |
| TCELL16:IMUX.IMUX8.DELAY | PCIE.EDTCHANNELSIN3 |
| TCELL16:IMUX.IMUX9.DELAY | PCIE.CFGERRCPLABORTN |
| TCELL16:IMUX.IMUX10.DELAY | PCIE.CFGERRCPLUNEXPECTN |
| TCELL16:IMUX.IMUX11.DELAY | PCIE.CFGERRPOISONEDN |
| TCELL16:IMUX.IMUX12.DELAY | PCIE.CFGERRACSN |
| TCELL16:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG12 |
| TCELL16:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG13 |
| TCELL16:IMUX.IMUX33.DELAY | PCIE.PIPERX6CHANISALIGNED |
| TCELL16:IMUX.IMUX34.DELAY | PCIE.PIPERX6DATA7 |
| TCELL16:IMUX.IMUX35.DELAY | PCIE.PIPERX6DATA6 |
| TCELL16:IMUX.IMUX36.DELAY | PCIE.PIPERX6VALID |
| TCELL16:IMUX.IMUX37.DELAY | PCIE.PIPERX6PHYSTATUS |
| TCELL16:IMUX.IMUX38.DELAY | PCIE.PIPERX6DATA5 |
| TCELL16:IMUX.IMUX39.DELAY | PCIE.PIPERX6DATA4 |
| TCELL16:OUT0.TMIN | PCIE.TRNRD110 |
| TCELL16:OUT1.TMIN | PCIE.TRNRD111 |
| TCELL16:OUT2.TMIN | PCIE.DBGVECA32 |
| TCELL16:OUT3.TMIN | PCIE.LL2LINKSTATUS2 |
| TCELL16:OUT4.TMIN | PCIE.LL2LINKSTATUS3 |
| TCELL16:OUT5.TMIN | PCIE.MIMRXWDATA54 |
| TCELL16:OUT6.TMIN | PCIE.MIMRXWDATA56 |
| TCELL16:OUT7.TMIN | PCIE.MIMRXWADDR3 |
| TCELL16:OUT8.TMIN | PCIE.MIMRXWADDR8 |
| TCELL16:OUT9.TMIN | PCIE.PIPETX4DATA8 |
| TCELL16:OUT10.TMIN | PCIE.MIMRXWDATA64 |
| TCELL16:OUT11.TMIN | PCIE.PIPETX4DATA10 |
| TCELL16:OUT12.TMIN | PCIE.MIMRXWADDR10 |
| TCELL16:OUT13.TMIN | PCIE.PIPETX4DATA9 |
| TCELL16:OUT14.TMIN | PCIE.MIMRXWADDR11 |
| TCELL16:OUT15.TMIN | PCIE.PIPETX4DATA11 |
| TCELL16:OUT16.TMIN | PCIE.MIMRXWDATA48 |
| TCELL16:OUT17.TMIN | PCIE.MIMRXWDATA50 |
| TCELL16:OUT18.TMIN | PCIE.MIMRXWDATA44 |
| TCELL16:OUT19.TMIN | PCIE.MIMRXWDATA62 |
| TCELL16:OUT20.TMIN | PCIE.LL2LINKSTATUS4 |
| TCELL16:OUT21.TMIN | PCIE.TL2PPMSUSPENDOK |
| TCELL16:OUT22.TMIN | PCIE.DBGVECA33 |
| TCELL16:OUT23.TMIN | PCIE.MIMRXWDATA46 |
| TCELL17:IMUX.IMUX0.DELAY | PCIE.MIMRXRDATA8 |
| TCELL17:IMUX.IMUX1.DELAY | PCIE.MIMRXRDATA9 |
| TCELL17:IMUX.IMUX2.DELAY | PCIE.MIMRXRDATA10 |
| TCELL17:IMUX.IMUX3.DELAY | PCIE.MIMRXRDATA11 |
| TCELL17:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA64 |
| TCELL17:IMUX.IMUX5.DELAY | PCIE.MIMRXRDATA65 |
| TCELL17:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA66 |
| TCELL17:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA67 |
| TCELL17:IMUX.IMUX8.DELAY | PCIE.TRNTD46 |
| TCELL17:IMUX.IMUX9.DELAY | PCIE.TRNTD47 |
| TCELL17:IMUX.IMUX10.DELAY | PCIE.TRNTD48 |
| TCELL17:IMUX.IMUX11.DELAY | PCIE.TRNTD49 |
| TCELL17:IMUX.IMUX12.DELAY | PCIE.EDTCHANNELSIN2 |
| TCELL17:IMUX.IMUX13.DELAY | PCIE.CFGERRATOMICEGRESSBLOCKEDN |
| TCELL17:IMUX.IMUX14.DELAY | PCIE.CFGERRMCBLOCKEDN |
| TCELL17:IMUX.IMUX15.DELAY | PCIE.CFGERRINTERNALUNCORN |
| TCELL17:IMUX.IMUX16.DELAY | PCIE.PIPERX6CHARISK0 |
| TCELL17:IMUX.IMUX17.DELAY | PCIE.CFGERRINTERNALCORN |
| TCELL17:IMUX.IMUX32.DELAY | PCIE.PIPERX6DATA3 |
| TCELL17:IMUX.IMUX33.DELAY | PCIE.PIPERX6DATA2 |
| TCELL17:IMUX.IMUX36.DELAY | PCIE.PIPERX6DATA1 |
| TCELL17:IMUX.IMUX37.DELAY | PCIE.PIPERX6DATA0 |
| TCELL17:OUT0.TMIN | PCIE.PIPETX4DATA4 |
| TCELL17:OUT1.TMIN | PCIE.PIPETX4POWERDOWN0 |
| TCELL17:OUT2.TMIN | PCIE.PIPETX4DATA6 |
| TCELL17:OUT3.TMIN | PCIE.PIPETX4ELECIDLE |
| TCELL17:OUT4.TMIN | PCIE.PIPETX4DATA5 |
| TCELL17:OUT5.TMIN | PCIE.TRNRD106 |
| TCELL17:OUT6.TMIN | PCIE.PIPETX4DATA7 |
| TCELL17:OUT7.TMIN | PCIE.PIPETX4POWERDOWN1 |
| TCELL17:OUT8.TMIN | PCIE.TRNRD107 |
| TCELL17:OUT9.TMIN | PCIE.TRNRD108 |
| TCELL17:OUT10.TMIN | PCIE.TRNRD109 |
| TCELL17:OUT11.TMIN | PCIE.MIMRXWDATA53 |
| TCELL17:OUT12.TMIN | PCIE.LL2SUSPENDOK |
| TCELL17:OUT13.TMIN | PCIE.LL2TXIDLE |
| TCELL17:OUT14.TMIN | PCIE.MIMRXWDATA67 |
| TCELL17:OUT15.TMIN | PCIE.LL2LINKSTATUS0 |
| TCELL17:OUT16.TMIN | PCIE.PIPETX4CHARISK0 |
| TCELL17:OUT17.TMIN | PCIE.MIMRXWADDR6 |
| TCELL17:OUT18.TMIN | PCIE.MIMRXWDATA66 |
| TCELL17:OUT19.TMIN | PCIE.LL2LINKSTATUS1 |
| TCELL17:OUT20.TMIN | PCIE.DBGVECA29 |
| TCELL17:OUT21.TMIN | PCIE.DBGVECA30 |
| TCELL17:OUT22.TMIN | PCIE.DBGVECA31 |
| TCELL17:OUT23.TMIN | PCIE.MIMRXWDATA39 |
| TCELL18:IMUX.IMUX0.DELAY | PCIE.MIMRXRDATA12 |
| TCELL18:IMUX.IMUX1.DELAY | PCIE.MIMRXRDATA13 |
| TCELL18:IMUX.IMUX2.DELAY | PCIE.MIMRXRDATA14 |
| TCELL18:IMUX.IMUX3.DELAY | PCIE.MIMRXRDATA15 |
| TCELL18:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA60 |
| TCELL18:IMUX.IMUX5.DELAY | PCIE.MIMRXRDATA61 |
| TCELL18:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA62 |
| TCELL18:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA63 |
| TCELL18:IMUX.IMUX8.DELAY | PCIE.TRNTD0 |
| TCELL18:IMUX.IMUX9.DELAY | PCIE.TRNTD1 |
| TCELL18:IMUX.IMUX10.DELAY | PCIE.TRNTD2 |
| TCELL18:IMUX.IMUX11.DELAY | PCIE.TRNTD3 |
| TCELL18:IMUX.IMUX12.DELAY | PCIE.TRNTD42 |
| TCELL18:IMUX.IMUX13.DELAY | PCIE.TRNTD43 |
| TCELL18:IMUX.IMUX14.DELAY | PCIE.TRNTD44 |
| TCELL18:IMUX.IMUX15.DELAY | PCIE.TRNTD45 |
| TCELL18:IMUX.IMUX16.DELAY | PCIE.EDTCHANNELSIN1 |
| TCELL18:IMUX.IMUX17.DELAY | PCIE.CFGERRPOSTEDN |
| TCELL18:IMUX.IMUX34.DELAY | PCIE.PIPERX4DATA15 |
| TCELL18:IMUX.IMUX35.DELAY | PCIE.PIPERX4DATA14 |
| TCELL18:IMUX.IMUX38.DELAY | PCIE.PIPERX4DATA13 |
| TCELL18:IMUX.IMUX39.DELAY | PCIE.PIPERX4DATA12 |
| TCELL18:OUT0.TMIN | PCIE.TRNRD103 |
| TCELL18:OUT1.TMIN | PCIE.PIPERX4POLARITY |
| TCELL18:OUT2.TMIN | PCIE.TRNRD104 |
| TCELL18:OUT3.TMIN | PCIE.PIPETX4COMPLIANCE |
| TCELL18:OUT4.TMIN | PCIE.MIMRXWDATA14 |
| TCELL18:OUT5.TMIN | PCIE.TRNRD105 |
| TCELL18:OUT6.TMIN | PCIE.MIMRXWDATA60 |
| TCELL18:OUT7.TMIN | PCIE.DBGVECA25 |
| TCELL18:OUT8.TMIN | PCIE.DBGVECA26 |
| TCELL18:OUT9.TMIN | PCIE.PIPETX4DATA0 |
| TCELL18:OUT10.TMIN | PCIE.MIMRXWDATA63 |
| TCELL18:OUT11.TMIN | PCIE.PIPETX4DATA2 |
| TCELL18:OUT12.TMIN | PCIE.MIMRXWDATA55 |
| TCELL18:OUT13.TMIN | PCIE.PIPETX4DATA1 |
| TCELL18:OUT14.TMIN | PCIE.MIMRXWDATA59 |
| TCELL18:OUT15.TMIN | PCIE.PIPETX4DATA3 |
| TCELL18:OUT16.TMIN | PCIE.MIMRXRADDR3 |
| TCELL18:OUT17.TMIN | PCIE.MIMRXWDATA45 |
| TCELL18:OUT18.TMIN | PCIE.MIMRXWDATA41 |
| TCELL18:OUT19.TMIN | PCIE.MIMRXWDATA43 |
| TCELL18:OUT20.TMIN | PCIE.DBGVECA27 |
| TCELL18:OUT21.TMIN | PCIE.DBGVECA28 |
| TCELL18:OUT22.TMIN | PCIE.DBGVECB9 |
| TCELL18:OUT23.TMIN | PCIE.XILUNCONNOUT29 |
| TCELL19:IMUX.IMUX0.DELAY | PCIE.MIMRXRDATA16 |
| TCELL19:IMUX.IMUX1.DELAY | PCIE.MIMRXRDATA17 |
| TCELL19:IMUX.IMUX2.DELAY | PCIE.MIMRXRDATA18 |
| TCELL19:IMUX.IMUX3.DELAY | PCIE.MIMRXRDATA19 |
| TCELL19:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA56 |
| TCELL19:IMUX.IMUX5.DELAY | PCIE.MIMRXRDATA57 |
| TCELL19:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA58 |
| TCELL19:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA59 |
| TCELL19:IMUX.IMUX8.DELAY | PCIE.TRNTD4 |
| TCELL19:IMUX.IMUX9.DELAY | PCIE.TRNTD5 |
| TCELL19:IMUX.IMUX10.DELAY | PCIE.TRNTD6 |
| TCELL19:IMUX.IMUX11.DELAY | PCIE.TRNTD7 |
| TCELL19:IMUX.IMUX12.DELAY | PCIE.EDTSINGLEBYPASSCHAIN |
| TCELL19:IMUX.IMUX16.DELAY | PCIE.PIPERX4CHARISK1 |
| TCELL19:IMUX.IMUX32.DELAY | PCIE.PIPERX4DATA11 |
| TCELL19:IMUX.IMUX33.DELAY | PCIE.PIPERX4DATA10 |
| TCELL19:IMUX.IMUX34.DELAY | PCIE.PIPERX4ELECIDLE |
| TCELL19:IMUX.IMUX35.DELAY | PCIE.PIPERX4STATUS2 |
| TCELL19:IMUX.IMUX36.DELAY | PCIE.PIPERX4DATA9 |
| TCELL19:IMUX.IMUX37.DELAY | PCIE.PIPERX4DATA8 |
| TCELL19:IMUX.IMUX38.DELAY | PCIE.PIPERX4STATUS1 |
| TCELL19:IMUX.IMUX39.DELAY | PCIE.PIPERX4STATUS0 |
| TCELL19:OUT0.TMIN | PCIE.MIMRXWDATA16 |
| TCELL19:OUT1.TMIN | PCIE.TRNRD99 |
| TCELL19:OUT2.TMIN | PCIE.MIMRXWDATA18 |
| TCELL19:OUT3.TMIN | PCIE.TRNRD100 |
| TCELL19:OUT4.TMIN | PCIE.TRNRD101 |
| TCELL19:OUT5.TMIN | PCIE.MIMRXWDATA57 |
| TCELL19:OUT6.TMIN | PCIE.TRNRD102 |
| TCELL19:OUT7.TMIN | PCIE.PL2RXELECIDLE |
| TCELL19:OUT8.TMIN | PCIE.MIMRXRADDR5 |
| TCELL19:OUT9.TMIN | PCIE.MIMRXRADDR6 |
| TCELL19:OUT10.TMIN | PCIE.MIMRXWDATA65 |
| TCELL19:OUT11.TMIN | PCIE.MIMRXWADDR7 |
| TCELL19:OUT12.TMIN | PCIE.MIMRXWDATA61 |
| TCELL19:OUT13.TMIN | PCIE.PL2RXPMSTATE0 |
| TCELL19:OUT14.TMIN | PCIE.MIMRXWADDR0 |
| TCELL19:OUT15.TMIN | PCIE.MIMRXRADDR7 |
| TCELL19:OUT16.TMIN | PCIE.MIMRXWADDR4 |
| TCELL19:OUT17.TMIN | PCIE.MIMRXWADDR9 |
| TCELL19:OUT18.TMIN | PCIE.MIMRXWDATA47 |
| TCELL19:OUT19.TMIN | PCIE.PL2RXPMSTATE1 |
| TCELL19:OUT20.TMIN | PCIE.PL2L0REQ |
| TCELL19:OUT21.TMIN | PCIE.DBGVECA22 |
| TCELL19:OUT22.TMIN | PCIE.DBGVECA23 |
| TCELL19:OUT23.TMIN | PCIE.DBGVECA24 |
| TCELL20:IMUX.IMUX0.DELAY | PCIE.MIMRXRDATA20 |
| TCELL20:IMUX.IMUX1.DELAY | PCIE.MIMRXRDATA21 |
| TCELL20:IMUX.IMUX2.DELAY | PCIE.MIMRXRDATA22 |
| TCELL20:IMUX.IMUX3.DELAY | PCIE.MIMRXRDATA23 |
| TCELL20:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA52 |
| TCELL20:IMUX.IMUX5.DELAY | PCIE.MIMRXRDATA53 |
| TCELL20:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA54 |
| TCELL20:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA55 |
| TCELL20:IMUX.IMUX8.DELAY | PCIE.TRNTD8 |
| TCELL20:IMUX.IMUX9.DELAY | PCIE.TRNTD9 |
| TCELL20:IMUX.IMUX10.DELAY | PCIE.TRNTD10 |
| TCELL20:IMUX.IMUX11.DELAY | PCIE.TRNTD11 |
| TCELL20:IMUX.IMUX12.DELAY | PCIE.TRNTD40 |
| TCELL20:IMUX.IMUX13.DELAY | PCIE.TRNTD41 |
| TCELL20:IMUX.IMUX14.DELAY | PCIE.EDTCONFIGURATION |
| TCELL20:IMUX.IMUX33.DELAY | PCIE.PIPERX4CHANISALIGNED |
| TCELL20:IMUX.IMUX34.DELAY | PCIE.PIPERX4DATA7 |
| TCELL20:IMUX.IMUX35.DELAY | PCIE.PIPERX4DATA6 |
| TCELL20:IMUX.IMUX36.DELAY | PCIE.PIPERX4VALID |
| TCELL20:IMUX.IMUX37.DELAY | PCIE.PIPERX4PHYSTATUS |
| TCELL20:IMUX.IMUX38.DELAY | PCIE.PIPERX4DATA5 |
| TCELL20:IMUX.IMUX39.DELAY | PCIE.PIPERX4DATA4 |
| TCELL20:OUT0.TMIN | PCIE.MIMRXWDATA20 |
| TCELL20:OUT1.TMIN | PCIE.MIMRXWADDR12 |
| TCELL20:OUT2.TMIN | PCIE.TRNRD95 |
| TCELL20:OUT3.TMIN | PCIE.MIMRXRADDR10 |
| TCELL20:OUT4.TMIN | PCIE.TRNRD96 |
| TCELL20:OUT5.TMIN | PCIE.TRNRD97 |
| TCELL20:OUT6.TMIN | PCIE.TRNRD98 |
| TCELL20:OUT7.TMIN | PCIE.PL2SUSPENDOK |
| TCELL20:OUT8.TMIN | PCIE.MIMRXRADDR9 |
| TCELL20:OUT9.TMIN | PCIE.MIMRXWDATA4 |
| TCELL20:OUT10.TMIN | PCIE.MIMRXRADDR11 |
| TCELL20:OUT11.TMIN | PCIE.MIMRXWDATA0 |
| TCELL20:OUT12.TMIN | PCIE.PL2RECOVERY |
| TCELL20:OUT13.TMIN | PCIE.MIMRXWDATA1 |
| TCELL20:OUT14.TMIN | PCIE.DBGVECA18 |
| TCELL20:OUT15.TMIN | PCIE.MIMRXWDATA22 |
| TCELL20:OUT16.TMIN | PCIE.MIMRXWDATA6 |
| TCELL20:OUT17.TMIN | PCIE.MIMRXRADDR8 |
| TCELL20:OUT18.TMIN | PCIE.MIMRXWDATA2 |
| TCELL20:OUT19.TMIN | PCIE.DBGVECA19 |
| TCELL20:OUT20.TMIN | PCIE.DBGVECA20 |
| TCELL20:OUT21.TMIN | PCIE.DBGVECA21 |
| TCELL20:OUT22.TMIN | PCIE.DBGVECB10 |
| TCELL20:OUT23.TMIN | PCIE.XILUNCONNOUT28 |
| TCELL21:IMUX.IMUX0.DELAY | PCIE.MIMRXRDATA24 |
| TCELL21:IMUX.IMUX1.DELAY | PCIE.MIMRXRDATA25 |
| TCELL21:IMUX.IMUX2.DELAY | PCIE.MIMRXRDATA26 |
| TCELL21:IMUX.IMUX3.DELAY | PCIE.MIMRXRDATA27 |
| TCELL21:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA48 |
| TCELL21:IMUX.IMUX5.DELAY | PCIE.MIMRXRDATA49 |
| TCELL21:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA50 |
| TCELL21:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA51 |
| TCELL21:IMUX.IMUX8.DELAY | PCIE.TRNTD12 |
| TCELL21:IMUX.IMUX9.DELAY | PCIE.TRNTD13 |
| TCELL21:IMUX.IMUX10.DELAY | PCIE.TRNTD14 |
| TCELL21:IMUX.IMUX11.DELAY | PCIE.TRNTD15 |
| TCELL21:IMUX.IMUX12.DELAY | PCIE.TRNTD36 |
| TCELL21:IMUX.IMUX13.DELAY | PCIE.TRNTD37 |
| TCELL21:IMUX.IMUX14.DELAY | PCIE.TRNTD38 |
| TCELL21:IMUX.IMUX15.DELAY | PCIE.TRNTD39 |
| TCELL21:IMUX.IMUX16.DELAY | PCIE.PIPERX4CHARISK0 |
| TCELL21:IMUX.IMUX17.DELAY | PCIE.EDTBYPASS |
| TCELL21:IMUX.IMUX32.DELAY | PCIE.PIPERX4DATA3 |
| TCELL21:IMUX.IMUX33.DELAY | PCIE.PIPERX4DATA2 |
| TCELL21:IMUX.IMUX36.DELAY | PCIE.PIPERX4DATA1 |
| TCELL21:IMUX.IMUX37.DELAY | PCIE.PIPERX4DATA0 |
| TCELL21:OUT0.TMIN | PCIE.MIMRXWDATA24 |
| TCELL21:OUT1.TMIN | PCIE.TRNRD91 |
| TCELL21:OUT2.TMIN | PCIE.MIMRXWDATA12 |
| TCELL21:OUT3.TMIN | PCIE.TRNRD92 |
| TCELL21:OUT4.TMIN | PCIE.TRNRD93 |
| TCELL21:OUT5.TMIN | PCIE.MIMRXWDATA49 |
| TCELL21:OUT6.TMIN | PCIE.TRNRD94 |
| TCELL21:OUT7.TMIN | PCIE.MIMRXWDATA51 |
| TCELL21:OUT8.TMIN | PCIE.MIMRXWDATA8 |
| TCELL21:OUT9.TMIN | PCIE.MIMRXWADDR5 |
| TCELL21:OUT10.TMIN | PCIE.TRNRDLLPSRCRDY0 |
| TCELL21:OUT11.TMIN | PCIE.MIMRXRADDR1 |
| TCELL21:OUT12.TMIN | PCIE.MIMRXREN |
| TCELL21:OUT13.TMIN | PCIE.MIMRXWDATA26 |
| TCELL21:OUT14.TMIN | PCIE.TRNRDLLPSRCRDY1 |
| TCELL21:OUT15.TMIN | PCIE.MIMRXWADDR1 |
| TCELL21:OUT16.TMIN | PCIE.LL2TFCINIT1SEQ |
| TCELL21:OUT17.TMIN | PCIE.MIMRXWDATA34 |
| TCELL21:OUT18.TMIN | PCIE.MIMRXWEN |
| TCELL21:OUT19.TMIN | PCIE.MIMRXWDATA10 |
| TCELL21:OUT20.TMIN | PCIE.LL2TFCINIT2SEQ |
| TCELL21:OUT21.TMIN | PCIE.CFGMGMTDO16 |
| TCELL21:OUT22.TMIN | PCIE.DBGVECA16 |
| TCELL21:OUT23.TMIN | PCIE.DBGVECA17 |
| TCELL22:IMUX.IMUX0.DELAY | PCIE.MIMRXRDATA28 |
| TCELL22:IMUX.IMUX1.DELAY | PCIE.MIMRXRDATA29 |
| TCELL22:IMUX.IMUX2.DELAY | PCIE.MIMRXRDATA30 |
| TCELL22:IMUX.IMUX3.DELAY | PCIE.MIMRXRDATA31 |
| TCELL22:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA44 |
| TCELL22:IMUX.IMUX5.DELAY | PCIE.MIMRXRDATA45 |
| TCELL22:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA46 |
| TCELL22:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA47 |
| TCELL22:IMUX.IMUX8.DELAY | PCIE.TRNTD16 |
| TCELL22:IMUX.IMUX9.DELAY | PCIE.TRNTD17 |
| TCELL22:IMUX.IMUX10.DELAY | PCIE.TRNTD18 |
| TCELL22:IMUX.IMUX11.DELAY | PCIE.TRNTD19 |
| TCELL22:IMUX.IMUX12.DELAY | PCIE.TRNTD32 |
| TCELL22:IMUX.IMUX13.DELAY | PCIE.TRNTD33 |
| TCELL22:IMUX.IMUX14.DELAY | PCIE.TRNTD34 |
| TCELL22:IMUX.IMUX15.DELAY | PCIE.TRNTD35 |
| TCELL22:IMUX.IMUX16.DELAY | PCIE.EDTUPDATE |
| TCELL22:IMUX.IMUX17.DELAY | PCIE.CFGERRLOCKEDN |
| TCELL22:IMUX.IMUX18.DELAY | PCIE.CFGERRNORECOVERYN |
| TCELL22:IMUX.IMUX19.DELAY | PCIE.CFGERRAERHEADERLOG0 |
| TCELL22:IMUX.IMUX20.DELAY | PCIE.CFGERRAERHEADERLOG1 |
| TCELL22:IMUX.IMUX21.DELAY | PCIE.CFGERRAERHEADERLOG11 |
| TCELL22:OUT0.TMIN | PCIE.MIMRXWADDR2 |
| TCELL22:OUT1.TMIN | PCIE.MIMRXWDATA32 |
| TCELL22:OUT2.TMIN | PCIE.TRNRD87 |
| TCELL22:OUT3.TMIN | PCIE.TRNRD88 |
| TCELL22:OUT4.TMIN | PCIE.TRNRD89 |
| TCELL22:OUT5.TMIN | PCIE.MIMRXRADDR4 |
| TCELL22:OUT6.TMIN | PCIE.TRNRD90 |
| TCELL22:OUT7.TMIN | PCIE.TRNRDLLPDATA60 |
| TCELL22:OUT8.TMIN | PCIE.TRNRDLLPDATA61 |
| TCELL22:OUT9.TMIN | PCIE.MIMRXWDATA17 |
| TCELL22:OUT10.TMIN | PCIE.TRNRDLLPDATA62 |
| TCELL22:OUT11.TMIN | PCIE.TRNRDLLPDATA63 |
| TCELL22:OUT12.TMIN | PCIE.MIMRXRADDR2 |
| TCELL22:OUT13.TMIN | PCIE.MIMRXRADDR0 |
| TCELL22:OUT14.TMIN | PCIE.MIMRXWDATA28 |
| TCELL22:OUT15.TMIN | PCIE.MIMRXWDATA3 |
| TCELL22:OUT16.TMIN | PCIE.CFGMGMTDO17 |
| TCELL22:OUT17.TMIN | PCIE.CFGMGMTDO18 |
| TCELL22:OUT18.TMIN | PCIE.MIMRXWDATA30 |
| TCELL22:OUT19.TMIN | PCIE.CFGMGMTDO19 |
| TCELL22:OUT20.TMIN | PCIE.DBGVECA14 |
| TCELL22:OUT21.TMIN | PCIE.MIMRXWDATA31 |
| TCELL22:OUT22.TMIN | PCIE.MIMRXWDATA33 |
| TCELL22:OUT23.TMIN | PCIE.DBGVECA15 |
| TCELL23:IMUX.IMUX0.DELAY | PCIE.MIMRXRDATA32 |
| TCELL23:IMUX.IMUX1.DELAY | PCIE.MIMRXRDATA33 |
| TCELL23:IMUX.IMUX2.DELAY | PCIE.MIMRXRDATA34 |
| TCELL23:IMUX.IMUX3.DELAY | PCIE.MIMRXRDATA35 |
| TCELL23:IMUX.IMUX4.DELAY | PCIE.MIMRXRDATA40 |
| TCELL23:IMUX.IMUX5.DELAY | PCIE.MIMRXRDATA41 |
| TCELL23:IMUX.IMUX6.DELAY | PCIE.MIMRXRDATA42 |
| TCELL23:IMUX.IMUX7.DELAY | PCIE.MIMRXRDATA43 |
| TCELL23:IMUX.IMUX8.DELAY | PCIE.TRNTD20 |
| TCELL23:IMUX.IMUX9.DELAY | PCIE.TRNTD21 |
| TCELL23:IMUX.IMUX10.DELAY | PCIE.TRNTD22 |
| TCELL23:IMUX.IMUX11.DELAY | PCIE.TRNTD23 |
| TCELL23:IMUX.IMUX12.DELAY | PCIE.TRNTD28 |
| TCELL23:IMUX.IMUX13.DELAY | PCIE.TRNTD29 |
| TCELL23:IMUX.IMUX14.DELAY | PCIE.TRNTD30 |
| TCELL23:IMUX.IMUX15.DELAY | PCIE.TRNTD31 |
| TCELL23:IMUX.IMUX16.DELAY | PCIE.LL2SUSPENDNOW |
| TCELL23:IMUX.IMUX17.DELAY | PCIE.TL2PPMSUSPENDREQ |
| TCELL23:IMUX.IMUX18.DELAY | PCIE.TL2ASPMSUSPENDCREDITCHECK |
| TCELL23:IMUX.IMUX19.DELAY | PCIE.SCANMODEN |
| TCELL23:IMUX.IMUX20.DELAY | PCIE.CFGERRAERHEADERLOG2 |
| TCELL23:IMUX.IMUX21.DELAY | PCIE.CFGERRAERHEADERLOG3 |
| TCELL23:IMUX.IMUX22.DELAY | PCIE.CFGERRAERHEADERLOG4 |
| TCELL23:IMUX.IMUX23.DELAY | PCIE.CFGERRAERHEADERLOG5 |
| TCELL23:IMUX.IMUX24.DELAY | PCIE.CFGERRAERHEADERLOG10 |
| TCELL23:OUT0.TMIN | PCIE.TRNRD83 |
| TCELL23:OUT1.TMIN | PCIE.TRNRD84 |
| TCELL23:OUT2.TMIN | PCIE.TRNRD85 |
| TCELL23:OUT3.TMIN | PCIE.MIMRXWDATA9 |
| TCELL23:OUT4.TMIN | PCIE.TRNRD86 |
| TCELL23:OUT5.TMIN | PCIE.TRNRDLLPDATA56 |
| TCELL23:OUT6.TMIN | PCIE.TRNRDLLPDATA57 |
| TCELL23:OUT7.TMIN | PCIE.TRNRDLLPDATA58 |
| TCELL23:OUT8.TMIN | PCIE.MIMRXWDATA19 |
| TCELL23:OUT9.TMIN | PCIE.TRNRDLLPDATA59 |
| TCELL23:OUT10.TMIN | PCIE.MIMRXWDATA25 |
| TCELL23:OUT11.TMIN | PCIE.CFGMGMTDO20 |
| TCELL23:OUT12.TMIN | PCIE.CFGMGMTDO21 |
| TCELL23:OUT13.TMIN | PCIE.CFGMGMTDO22 |
| TCELL23:OUT14.TMIN | PCIE.MIMRXWDATA23 |
| TCELL23:OUT15.TMIN | PCIE.CFGMGMTDO23 |
| TCELL23:OUT16.TMIN | PCIE.CFGMGMTDO28 |
| TCELL23:OUT17.TMIN | PCIE.CFGMGMTDO29 |
| TCELL23:OUT18.TMIN | PCIE.CFGMGMTDO30 |
| TCELL23:OUT19.TMIN | PCIE.MIMRXWDATA21 |
| TCELL23:OUT20.TMIN | PCIE.DBGVECA12 |
| TCELL23:OUT21.TMIN | PCIE.DBGVECA13 |
| TCELL23:OUT22.TMIN | PCIE.MIMRXWDATA5 |
| TCELL23:OUT23.TMIN | PCIE.MIMRXWDATA7 |
| TCELL24:IMUX.IMUX0.DELAY | PCIE.MIMRXRDATA36 |
| TCELL24:IMUX.IMUX1.DELAY | PCIE.MIMRXRDATA37 |
| TCELL24:IMUX.IMUX2.DELAY | PCIE.MIMRXRDATA38 |
| TCELL24:IMUX.IMUX3.DELAY | PCIE.MIMRXRDATA39 |
| TCELL24:IMUX.IMUX4.DELAY | PCIE.TRNTD24 |
| TCELL24:IMUX.IMUX5.DELAY | PCIE.TRNTD25 |
| TCELL24:IMUX.IMUX6.DELAY | PCIE.TRNTD26 |
| TCELL24:IMUX.IMUX7.DELAY | PCIE.TRNTD27 |
| TCELL24:IMUX.IMUX8.DELAY | PCIE.PL2DIRECTEDLSTATE1 |
| TCELL24:IMUX.IMUX9.DELAY | PCIE.PL2DIRECTEDLSTATE2 |
| TCELL24:IMUX.IMUX10.DELAY | PCIE.PL2DIRECTEDLSTATE3 |
| TCELL24:IMUX.IMUX11.DELAY | PCIE.PL2DIRECTEDLSTATE4 |
| TCELL24:IMUX.IMUX12.DELAY | PCIE.SCANENABLEN |
| TCELL24:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG6 |
| TCELL24:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG7 |
| TCELL24:IMUX.IMUX15.DELAY | PCIE.CFGERRAERHEADERLOG8 |
| TCELL24:IMUX.IMUX16.DELAY | PCIE.CFGERRAERHEADERLOG9 |
| TCELL24:IMUX.IMUX17.DELAY | PCIE.CFGERRTLPCPLHEADER46 |
| TCELL24:IMUX.IMUX18.DELAY | PCIE.CFGERRTLPCPLHEADER47 |
| TCELL24:IMUX.IMUX19.DELAY | PCIE.CFGINTERRUPTN |
| TCELL24:IMUX.IMUX20.DELAY | PCIE.CFGINTERRUPTDI0 |
| TCELL24:IMUX.IMUX21.DELAY | PCIE.CFGDEVID13 |
| TCELL24:IMUX.IMUX22.DELAY | PCIE.CFGDEVID14 |
| TCELL24:IMUX.IMUX23.DELAY | PCIE.CFGDEVID15 |
| TCELL24:IMUX.IMUX24.DELAY | PCIE.CFGVENDID0 |
| TCELL24:IMUX.IMUX25.DELAY | PCIE.DBGMODE0 |
| TCELL24:OUT0.TMIN | PCIE.TRNRD79 |
| TCELL24:OUT1.TMIN | PCIE.TRNTDSTRDY3 |
| TCELL24:OUT2.TMIN | PCIE.TRNRD80 |
| TCELL24:OUT3.TMIN | PCIE.TRNRD81 |
| TCELL24:OUT4.TMIN | PCIE.TRNRD82 |
| TCELL24:OUT5.TMIN | PCIE.TRNRDLLPDATA52 |
| TCELL24:OUT6.TMIN | PCIE.TRNRDLLPDATA53 |
| TCELL24:OUT7.TMIN | PCIE.TRNRDLLPDATA54 |
| TCELL24:OUT8.TMIN | PCIE.MIMRXWDATA29 |
| TCELL24:OUT9.TMIN | PCIE.MIMRXWDATA13 |
| TCELL24:OUT10.TMIN | PCIE.MIMRXWDATA15 |
| TCELL24:OUT11.TMIN | PCIE.MIMRXWDATA35 |
| TCELL24:OUT12.TMIN | PCIE.TRNRDLLPDATA55 |
| TCELL24:OUT13.TMIN | PCIE.CFGMGMTDO24 |
| TCELL24:OUT14.TMIN | PCIE.CFGMGMTDO25 |
| TCELL24:OUT15.TMIN | PCIE.CFGMGMTDO26 |
| TCELL24:OUT16.TMIN | PCIE.CFGMGMTDO27 |
| TCELL24:OUT17.TMIN | PCIE.CFGCOMMANDMEMENABLE |
| TCELL24:OUT18.TMIN | PCIE.MIMRXWDATA11 |
| TCELL24:OUT19.TMIN | PCIE.MIMRXWDATA27 |
| TCELL24:OUT20.TMIN | PCIE.CFGCOMMANDBUSMASTERENABLE |
| TCELL24:OUT21.TMIN | PCIE.CFGCOMMANDINTERRUPTDISABLE |
| TCELL24:OUT22.TMIN | PCIE.DBGVECA11 |
| TCELL24:OUT23.TMIN | PCIE.CFGDEVCONTROL2LTREN |
| TCELL25:IMUX.IMUX0.DELAY | PCIE.PLDIRECTEDLINKCHANGE0 |
| TCELL25:IMUX.IMUX1.DELAY | PCIE.PLDIRECTEDLINKCHANGE1 |
| TCELL25:IMUX.IMUX2.DELAY | PCIE.PLDIRECTEDLINKWIDTH0 |
| TCELL25:IMUX.IMUX3.DELAY | PCIE.PLDIRECTEDLINKWIDTH1 |
| TCELL25:IMUX.IMUX4.DELAY | PCIE.PLDIRECTEDLINKSPEED |
| TCELL25:IMUX.IMUX5.DELAY | PCIE.PLDIRECTEDLINKAUTON |
| TCELL25:IMUX.IMUX6.DELAY | PCIE.PLUPSTREAMPREFERDEEMPH |
| TCELL25:IMUX.IMUX7.DELAY | PCIE.PLDOWNSTREAMDEEMPHSOURCE |
| TCELL25:IMUX.IMUX8.DELAY | PCIE.PLDIRECTEDLTSSMNEWVLD |
| TCELL25:IMUX.IMUX9.DELAY | PCIE.PLDIRECTEDLTSSMNEW0 |
| TCELL25:IMUX.IMUX10.DELAY | PCIE.PLDIRECTEDLTSSMNEW1 |
| TCELL25:IMUX.IMUX11.DELAY | PCIE.PLDIRECTEDLTSSMNEW2 |
| TCELL25:IMUX.IMUX12.DELAY | PCIE.PLDIRECTEDLTSSMNEW3 |
| TCELL25:IMUX.IMUX13.DELAY | PCIE.CFGERRAERHEADERLOG74 |
| TCELL25:IMUX.IMUX14.DELAY | PCIE.CFGERRAERHEADERLOG75 |
| TCELL25:IMUX.IMUX15.DELAY | PCIE.CFGERRAERHEADERLOG76 |
| TCELL25:IMUX.IMUX16.DELAY | PCIE.CFGERRAERHEADERLOG77 |
| TCELL25:IMUX.IMUX17.DELAY | PCIE.CFGPORTNUMBER4 |
| TCELL25:IMUX.IMUX18.DELAY | PCIE.CFGPORTNUMBER5 |
| TCELL25:IMUX.IMUX19.DELAY | PCIE.CFGPORTNUMBER6 |
| TCELL25:IMUX.IMUX20.DELAY | PCIE.CFGPORTNUMBER7 |
| TCELL25:OUT0.TMIN | PCIE.PIPETX3DATA12 |
| TCELL25:OUT1.TMIN | PCIE.PLSELLNKRATE |
| TCELL25:OUT2.TMIN | PCIE.PIPETX3DATA14 |
| TCELL25:OUT3.TMIN | PCIE.PLSELLNKWIDTH0 |
| TCELL25:OUT4.TMIN | PCIE.PIPETX3DATA13 |
| TCELL25:OUT5.TMIN | PCIE.PLSELLNKWIDTH1 |
| TCELL25:OUT6.TMIN | PCIE.PIPETX3DATA15 |
| TCELL25:OUT7.TMIN | PCIE.PLLTSSMSTATE0 |
| TCELL25:OUT8.TMIN | PCIE.PLLTSSMSTATE1 |
| TCELL25:OUT9.TMIN | PCIE.PLLTSSMSTATE2 |
| TCELL25:OUT10.TMIN | PCIE.PLLTSSMSTATE3 |
| TCELL25:OUT11.TMIN | PCIE.PLLTSSMSTATE4 |
| TCELL25:OUT12.TMIN | PCIE.PLLTSSMSTATE5 |
| TCELL25:OUT13.TMIN | PCIE.PLLANEREVERSALMODE0 |
| TCELL25:OUT14.TMIN | PCIE.PLLANEREVERSALMODE1 |
| TCELL25:OUT15.TMIN | PCIE.PLPHYLNKUPN |
| TCELL25:OUT16.TMIN | PCIE.PIPETX3CHARISK1 |
| TCELL25:OUT17.TMIN | PCIE.PLTXPMSTATE0 |
| TCELL25:OUT18.TMIN | PCIE.PLTXPMSTATE1 |
| TCELL25:OUT19.TMIN | PCIE.PLTXPMSTATE2 |
| TCELL25:OUT20.TMIN | PCIE.DBGVECB36 |
| TCELL25:OUT21.TMIN | PCIE.DBGVECB37 |
| TCELL25:OUT22.TMIN | PCIE.DBGVECB38 |
| TCELL25:OUT23.TMIN | PCIE.XILUNCONNOUT6 |
| TCELL26:IMUX.IMUX0.DELAY | PCIE.PLDIRECTEDLTSSMNEW4 |
| TCELL26:IMUX.IMUX1.DELAY | PCIE.PLDIRECTEDLTSSMNEW5 |
| TCELL26:IMUX.IMUX2.DELAY | PCIE.PLDIRECTEDLTSSMSTALL |
| TCELL26:IMUX.IMUX3.DELAY | PCIE.TRNTD91 |
| TCELL26:IMUX.IMUX4.DELAY | PCIE.CFGERRAERHEADERLOG78 |
| TCELL26:IMUX.IMUX5.DELAY | PCIE.CFGERRAERHEADERLOG79 |
| TCELL26:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG80 |
| TCELL26:IMUX.IMUX7.DELAY | PCIE.CFGERRAERHEADERLOG81 |
| TCELL26:IMUX.IMUX8.DELAY | PCIE.CFGPMHALTASPML0SN |
| TCELL26:IMUX.IMUX9.DELAY | PCIE.CFGPMHALTASPML1N |
| TCELL26:IMUX.IMUX10.DELAY | PCIE.CFGPMFORCESTATEENN |
| TCELL26:IMUX.IMUX11.DELAY | PCIE.CFGPMFORCESTATE0 |
| TCELL26:IMUX.IMUX12.DELAY | PCIE.CFGREVID0 |
| TCELL26:IMUX.IMUX13.DELAY | PCIE.CFGREVID1 |
| TCELL26:IMUX.IMUX14.DELAY | PCIE.CFGREVID2 |
| TCELL26:IMUX.IMUX15.DELAY | PCIE.CFGREVID3 |
| TCELL26:IMUX.IMUX16.DELAY | PCIE.PLDBGMODE1 |
| TCELL26:IMUX.IMUX17.DELAY | PCIE.PLDBGMODE2 |
| TCELL26:OUT0.TMIN | PCIE.PLRXPMSTATE0 |
| TCELL26:OUT1.TMIN | PCIE.PLRXPMSTATE1 |
| TCELL26:OUT2.TMIN | PCIE.PLLINKUPCFGCAP |
| TCELL26:OUT3.TMIN | PCIE.PLLINKGEN2CAP |
| TCELL26:OUT4.TMIN | PCIE.TRNFCPD9 |
| TCELL26:OUT5.TMIN | PCIE.TRNFCPD10 |
| TCELL26:OUT6.TMIN | PCIE.TRNFCPD11 |
| TCELL26:OUT7.TMIN | PCIE.TRNFCNPH0 |
| TCELL26:OUT8.TMIN | PCIE.TL2ERRHDR19 |
| TCELL26:OUT9.TMIN | PCIE.PIPETX3DATA8 |
| TCELL26:OUT10.TMIN | PCIE.TL2ERRHDR20 |
| TCELL26:OUT11.TMIN | PCIE.PIPETX3DATA10 |
| TCELL26:OUT12.TMIN | PCIE.TL2ERRHDR21 |
| TCELL26:OUT13.TMIN | PCIE.PIPETX3DATA9 |
| TCELL26:OUT14.TMIN | PCIE.TL2ERRHDR22 |
| TCELL26:OUT15.TMIN | PCIE.PIPETX3DATA11 |
| TCELL26:OUT16.TMIN | PCIE.CFGINTERRUPTMMENABLE2 |
| TCELL26:OUT17.TMIN | PCIE.CFGINTERRUPTMSIENABLE |
| TCELL26:OUT18.TMIN | PCIE.DBGVECB39 |
| TCELL26:OUT19.TMIN | PCIE.DBGVECB40 |
| TCELL26:OUT20.TMIN | PCIE.DBGVECB41 |
| TCELL26:OUT21.TMIN | PCIE.DBGVECB42 |
| TCELL26:OUT22.TMIN | PCIE.XILUNCONNOUT7 |
| TCELL26:OUT23.TMIN | PCIE.XILUNCONNOUT8 |
| TCELL27:IMUX.IMUX0.DELAY | PCIE.TRNTD92 |
| TCELL27:IMUX.IMUX1.DELAY | PCIE.TRNTD93 |
| TCELL27:IMUX.IMUX2.DELAY | PCIE.TRNTD94 |
| TCELL27:IMUX.IMUX3.DELAY | PCIE.TRNTD95 |
| TCELL27:IMUX.IMUX4.DELAY | PCIE.CFGERRAERHEADERLOG82 |
| TCELL27:IMUX.IMUX5.DELAY | PCIE.CFGERRAERHEADERLOG83 |
| TCELL27:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG84 |
| TCELL27:IMUX.IMUX7.DELAY | PCIE.CFGERRAERHEADERLOG85 |
| TCELL27:IMUX.IMUX8.DELAY | PCIE.CFGPMFORCESTATE1 |
| TCELL27:IMUX.IMUX9.DELAY | PCIE.CFGPMWAKEN |
| TCELL27:IMUX.IMUX10.DELAY | PCIE.CFGPMTURNOFFOKN |
| TCELL27:IMUX.IMUX11.DELAY | PCIE.CFGPMSENDPMETON |
| TCELL27:IMUX.IMUX12.DELAY | PCIE.CFGREVID4 |
| TCELL27:IMUX.IMUX13.DELAY | PCIE.CFGREVID5 |
| TCELL27:IMUX.IMUX14.DELAY | PCIE.CFGREVID6 |
| TCELL27:IMUX.IMUX15.DELAY | PCIE.CFGREVID7 |
| TCELL27:OUT0.TMIN | PCIE.PIPETX3DATA4 |
| TCELL27:OUT1.TMIN | PCIE.PIPETX3POWERDOWN0 |
| TCELL27:OUT2.TMIN | PCIE.PIPETX3DATA6 |
| TCELL27:OUT3.TMIN | PCIE.PIPETX3ELECIDLE |
| TCELL27:OUT4.TMIN | PCIE.PIPETX3DATA5 |
| TCELL27:OUT5.TMIN | PCIE.PLLINKPARTNERGEN2SUPPORTED |
| TCELL27:OUT6.TMIN | PCIE.PIPETX3DATA7 |
| TCELL27:OUT7.TMIN | PCIE.PIPETX3POWERDOWN1 |
| TCELL27:OUT8.TMIN | PCIE.PLINITIALLINKWIDTH0 |
| TCELL27:OUT9.TMIN | PCIE.PLINITIALLINKWIDTH1 |
| TCELL27:OUT10.TMIN | PCIE.PLINITIALLINKWIDTH2 |
| TCELL27:OUT11.TMIN | PCIE.TRNFCNPH1 |
| TCELL27:OUT12.TMIN | PCIE.TRNFCNPH2 |
| TCELL27:OUT13.TMIN | PCIE.TRNFCNPH3 |
| TCELL27:OUT14.TMIN | PCIE.TRNFCNPH4 |
| TCELL27:OUT15.TMIN | PCIE.TL2ERRHDR23 |
| TCELL27:OUT16.TMIN | PCIE.PIPETX3CHARISK0 |
| TCELL27:OUT17.TMIN | PCIE.TL2ERRHDR24 |
| TCELL27:OUT18.TMIN | PCIE.DBGVECB43 |
| TCELL27:OUT19.TMIN | PCIE.DBGVECB44 |
| TCELL27:OUT20.TMIN | PCIE.DBGVECB45 |
| TCELL27:OUT21.TMIN | PCIE.DBGVECB46 |
| TCELL27:OUT22.TMIN | PCIE.XILUNCONNOUT9 |
| TCELL27:OUT23.TMIN | PCIE.XILUNCONNOUT10 |
| TCELL28:IMUX.IMUX0.DELAY | PCIE.TRNTD96 |
| TCELL28:IMUX.IMUX1.DELAY | PCIE.TRNTD97 |
| TCELL28:IMUX.IMUX2.DELAY | PCIE.TRNTD98 |
| TCELL28:IMUX.IMUX3.DELAY | PCIE.TRNTD99 |
| TCELL28:IMUX.IMUX4.DELAY | PCIE.CFGERRAERHEADERLOG86 |
| TCELL28:IMUX.IMUX5.DELAY | PCIE.CFGERRAERHEADERLOG87 |
| TCELL28:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG88 |
| TCELL28:IMUX.IMUX7.DELAY | PCIE.CFGERRAERHEADERLOG89 |
| TCELL28:IMUX.IMUX8.DELAY | PCIE.CFGPCIECAPINTERRUPTMSGNUM0 |
| TCELL28:IMUX.IMUX9.DELAY | PCIE.CFGPCIECAPINTERRUPTMSGNUM1 |
| TCELL28:IMUX.IMUX10.DELAY | PCIE.CFGPCIECAPINTERRUPTMSGNUM2 |
| TCELL28:IMUX.IMUX11.DELAY | PCIE.CFGPCIECAPINTERRUPTMSGNUM3 |
| TCELL28:IMUX.IMUX12.DELAY | PCIE.CFGSUBSYSID0 |
| TCELL28:IMUX.IMUX13.DELAY | PCIE.CFGSUBSYSID1 |
| TCELL28:IMUX.IMUX14.DELAY | PCIE.CFGSUBSYSID2 |
| TCELL28:IMUX.IMUX15.DELAY | PCIE.CFGSUBSYSID3 |
| TCELL28:IMUX.IMUX34.DELAY | PCIE.PIPERX3DATA15 |
| TCELL28:IMUX.IMUX35.DELAY | PCIE.PIPERX3DATA14 |
| TCELL28:IMUX.IMUX38.DELAY | PCIE.PIPERX3DATA13 |
| TCELL28:IMUX.IMUX39.DELAY | PCIE.PIPERX3DATA12 |
| TCELL28:OUT0.TMIN | PCIE.PLDIRECTEDCHANGEDONE |
| TCELL28:OUT1.TMIN | PCIE.PIPERX3POLARITY |
| TCELL28:OUT2.TMIN | PCIE.TRNTERRDROP |
| TCELL28:OUT3.TMIN | PCIE.PIPETX3COMPLIANCE |
| TCELL28:OUT4.TMIN | PCIE.TRNTBUFAV0 |
| TCELL28:OUT5.TMIN | PCIE.TRNTBUFAV1 |
| TCELL28:OUT6.TMIN | PCIE.TRNFCNPH5 |
| TCELL28:OUT7.TMIN | PCIE.TRNFCNPH6 |
| TCELL28:OUT8.TMIN | PCIE.TRNFCNPH7 |
| TCELL28:OUT9.TMIN | PCIE.PIPETX3DATA0 |
| TCELL28:OUT10.TMIN | PCIE.TRNFCNPD0 |
| TCELL28:OUT11.TMIN | PCIE.PIPETX3DATA2 |
| TCELL28:OUT12.TMIN | PCIE.TL2ERRHDR25 |
| TCELL28:OUT13.TMIN | PCIE.PIPETX3DATA1 |
| TCELL28:OUT14.TMIN | PCIE.TL2ERRHDR26 |
| TCELL28:OUT15.TMIN | PCIE.PIPETX3DATA3 |
| TCELL28:OUT16.TMIN | PCIE.TL2ERRHDR27 |
| TCELL28:OUT17.TMIN | PCIE.TL2ERRHDR28 |
| TCELL28:OUT18.TMIN | PCIE.DBGVECB47 |
| TCELL28:OUT19.TMIN | PCIE.DBGVECB48 |
| TCELL28:OUT20.TMIN | PCIE.DBGVECB49 |
| TCELL28:OUT21.TMIN | PCIE.DBGVECB50 |
| TCELL28:OUT22.TMIN | PCIE.XILUNCONNOUT11 |
| TCELL28:OUT23.TMIN | PCIE.XILUNCONNOUT12 |
| TCELL29:IMUX.IMUX0.DELAY | PCIE.TRNTD100 |
| TCELL29:IMUX.IMUX1.DELAY | PCIE.TRNTD101 |
| TCELL29:IMUX.IMUX2.DELAY | PCIE.TRNTD102 |
| TCELL29:IMUX.IMUX3.DELAY | PCIE.TRNTD103 |
| TCELL29:IMUX.IMUX4.DELAY | PCIE.CFGERRAERHEADERLOG90 |
| TCELL29:IMUX.IMUX5.DELAY | PCIE.CFGERRAERHEADERLOG91 |
| TCELL29:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG92 |
| TCELL29:IMUX.IMUX7.DELAY | PCIE.CFGERRAERHEADERLOG93 |
| TCELL29:IMUX.IMUX8.DELAY | PCIE.CFGPCIECAPINTERRUPTMSGNUM4 |
| TCELL29:IMUX.IMUX9.DELAY | PCIE.CFGTRNPENDINGN |
| TCELL29:IMUX.IMUX10.DELAY | PCIE.CFGFORCEMPS0 |
| TCELL29:IMUX.IMUX11.DELAY | PCIE.CFGFORCEMPS1 |
| TCELL29:IMUX.IMUX16.DELAY | PCIE.PIPERX3CHARISK1 |
| TCELL29:IMUX.IMUX32.DELAY | PCIE.PIPERX3DATA11 |
| TCELL29:IMUX.IMUX33.DELAY | PCIE.PIPERX3DATA10 |
| TCELL29:IMUX.IMUX34.DELAY | PCIE.PIPERX3ELECIDLE |
| TCELL29:IMUX.IMUX35.DELAY | PCIE.PIPERX3STATUS2 |
| TCELL29:IMUX.IMUX36.DELAY | PCIE.PIPERX3DATA9 |
| TCELL29:IMUX.IMUX37.DELAY | PCIE.PIPERX3DATA8 |
| TCELL29:IMUX.IMUX38.DELAY | PCIE.PIPERX3STATUS1 |
| TCELL29:IMUX.IMUX39.DELAY | PCIE.PIPERX3STATUS0 |
| TCELL29:OUT0.TMIN | PCIE.PIPETX1DATA12 |
| TCELL29:OUT1.TMIN | PCIE.TRNTBUFAV2 |
| TCELL29:OUT2.TMIN | PCIE.PIPETX1DATA14 |
| TCELL29:OUT3.TMIN | PCIE.TRNTBUFAV3 |
| TCELL29:OUT4.TMIN | PCIE.PIPETX1DATA13 |
| TCELL29:OUT5.TMIN | PCIE.TRNTBUFAV4 |
| TCELL29:OUT6.TMIN | PCIE.PIPETX1DATA15 |
| TCELL29:OUT7.TMIN | PCIE.TRNTBUFAV5 |
| TCELL29:OUT8.TMIN | PCIE.TRNFCNPD1 |
| TCELL29:OUT9.TMIN | PCIE.TRNFCNPD2 |
| TCELL29:OUT10.TMIN | PCIE.TRNFCNPD3 |
| TCELL29:OUT11.TMIN | PCIE.TRNFCNPD4 |
| TCELL29:OUT12.TMIN | PCIE.TL2ERRHDR29 |
| TCELL29:OUT13.TMIN | PCIE.TL2ERRHDR30 |
| TCELL29:OUT14.TMIN | PCIE.TL2ERRHDR31 |
| TCELL29:OUT15.TMIN | PCIE.TL2ERRHDR32 |
| TCELL29:OUT16.TMIN | PCIE.PIPETX1CHARISK1 |
| TCELL29:OUT17.TMIN | PCIE.CFGINTERRUPTMSIXENABLE |
| TCELL29:OUT18.TMIN | PCIE.DBGVECB51 |
| TCELL29:OUT19.TMIN | PCIE.DBGVECB52 |
| TCELL29:OUT20.TMIN | PCIE.DBGVECB53 |
| TCELL29:OUT21.TMIN | PCIE.DBGVECB54 |
| TCELL29:OUT22.TMIN | PCIE.XILUNCONNOUT13 |
| TCELL29:OUT23.TMIN | PCIE.XILUNCONNOUT14 |
| TCELL30:IMUX.IMUX0.DELAY | PCIE.TRNTD104 |
| TCELL30:IMUX.IMUX1.DELAY | PCIE.TRNTD105 |
| TCELL30:IMUX.IMUX2.DELAY | PCIE.TRNTD106 |
| TCELL30:IMUX.IMUX3.DELAY | PCIE.TRNTD107 |
| TCELL30:IMUX.IMUX4.DELAY | PCIE.CFGERRAERHEADERLOG94 |
| TCELL30:IMUX.IMUX5.DELAY | PCIE.CFGERRAERHEADERLOG95 |
| TCELL30:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG96 |
| TCELL30:IMUX.IMUX7.DELAY | PCIE.CFGERRAERHEADERLOG97 |
| TCELL30:IMUX.IMUX8.DELAY | PCIE.CFGFORCEMPS2 |
| TCELL30:IMUX.IMUX9.DELAY | PCIE.CFGFORCECOMMONCLOCKOFF |
| TCELL30:IMUX.IMUX10.DELAY | PCIE.CFGFORCEEXTENDEDSYNCON |
| TCELL30:IMUX.IMUX11.DELAY | PCIE.CFGDSN0 |
| TCELL30:IMUX.IMUX12.DELAY | PCIE.CFGSUBSYSID4 |
| TCELL30:IMUX.IMUX13.DELAY | PCIE.CFGSUBSYSID5 |
| TCELL30:IMUX.IMUX33.DELAY | PCIE.PIPERX3CHANISALIGNED |
| TCELL30:IMUX.IMUX34.DELAY | PCIE.PIPERX3DATA7 |
| TCELL30:IMUX.IMUX35.DELAY | PCIE.PIPERX3DATA6 |
| TCELL30:IMUX.IMUX36.DELAY | PCIE.PIPERX3VALID |
| TCELL30:IMUX.IMUX37.DELAY | PCIE.PIPERX3PHYSTATUS |
| TCELL30:IMUX.IMUX38.DELAY | PCIE.PIPERX3DATA5 |
| TCELL30:IMUX.IMUX39.DELAY | PCIE.PIPERX3DATA4 |
| TCELL30:OUT0.TMIN | PCIE.TRNTCFGREQ |
| TCELL30:OUT1.TMIN | PCIE.TRNRD0 |
| TCELL30:OUT2.TMIN | PCIE.TRNRD1 |
| TCELL30:OUT3.TMIN | PCIE.TRNRD2 |
| TCELL30:OUT4.TMIN | PCIE.TRNFCNPD5 |
| TCELL30:OUT5.TMIN | PCIE.TRNFCNPD6 |
| TCELL30:OUT6.TMIN | PCIE.TRNFCNPD7 |
| TCELL30:OUT7.TMIN | PCIE.TRNFCNPD8 |
| TCELL30:OUT8.TMIN | PCIE.TL2ERRHDR33 |
| TCELL30:OUT9.TMIN | PCIE.PIPETX1DATA8 |
| TCELL30:OUT10.TMIN | PCIE.TL2ERRHDR34 |
| TCELL30:OUT11.TMIN | PCIE.PIPETX1DATA10 |
| TCELL30:OUT12.TMIN | PCIE.TL2ERRHDR35 |
| TCELL30:OUT13.TMIN | PCIE.PIPETX1DATA9 |
| TCELL30:OUT14.TMIN | PCIE.TL2ERRHDR36 |
| TCELL30:OUT15.TMIN | PCIE.PIPETX1DATA11 |
| TCELL30:OUT16.TMIN | PCIE.CFGINTERRUPTMSIXFM |
| TCELL30:OUT17.TMIN | PCIE.CFGINTERRUPTDO0 |
| TCELL30:OUT18.TMIN | PCIE.DBGVECB55 |
| TCELL30:OUT19.TMIN | PCIE.DBGVECB56 |
| TCELL30:OUT20.TMIN | PCIE.DBGVECB57 |
| TCELL30:OUT21.TMIN | PCIE.DBGVECB58 |
| TCELL30:OUT22.TMIN | PCIE.XILUNCONNOUT15 |
| TCELL30:OUT23.TMIN | PCIE.XILUNCONNOUT16 |
| TCELL31:IMUX.IMUX0.DELAY | PCIE.TRNTD108 |
| TCELL31:IMUX.IMUX1.DELAY | PCIE.TRNTD109 |
| TCELL31:IMUX.IMUX2.DELAY | PCIE.TRNTD110 |
| TCELL31:IMUX.IMUX3.DELAY | PCIE.TRNTD111 |
| TCELL31:IMUX.IMUX4.DELAY | PCIE.CFGERRAERHEADERLOG98 |
| TCELL31:IMUX.IMUX5.DELAY | PCIE.CFGERRAERHEADERLOG99 |
| TCELL31:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG100 |
| TCELL31:IMUX.IMUX7.DELAY | PCIE.CFGERRAERHEADERLOG101 |
| TCELL31:IMUX.IMUX8.DELAY | PCIE.CFGDSN1 |
| TCELL31:IMUX.IMUX9.DELAY | PCIE.CFGDSN2 |
| TCELL31:IMUX.IMUX10.DELAY | PCIE.CFGDSN3 |
| TCELL31:IMUX.IMUX11.DELAY | PCIE.CFGDSN4 |
| TCELL31:IMUX.IMUX12.DELAY | PCIE.CFGSUBSYSID6 |
| TCELL31:IMUX.IMUX13.DELAY | PCIE.CFGSUBSYSID7 |
| TCELL31:IMUX.IMUX14.DELAY | PCIE.CFGSUBSYSID8 |
| TCELL31:IMUX.IMUX15.DELAY | PCIE.CFGSUBSYSID9 |
| TCELL31:IMUX.IMUX16.DELAY | PCIE.PIPERX3CHARISK0 |
| TCELL31:IMUX.IMUX32.DELAY | PCIE.PIPERX3DATA3 |
| TCELL31:IMUX.IMUX33.DELAY | PCIE.PIPERX3DATA2 |
| TCELL31:IMUX.IMUX36.DELAY | PCIE.PIPERX3DATA1 |
| TCELL31:IMUX.IMUX37.DELAY | PCIE.PIPERX3DATA0 |
| TCELL31:OUT0.TMIN | PCIE.PIPETX1DATA4 |
| TCELL31:OUT1.TMIN | PCIE.PIPETX1POWERDOWN0 |
| TCELL31:OUT2.TMIN | PCIE.PIPETX1DATA6 |
| TCELL31:OUT3.TMIN | PCIE.PIPETX1ELECIDLE |
| TCELL31:OUT4.TMIN | PCIE.PIPETX1DATA5 |
| TCELL31:OUT5.TMIN | PCIE.TRNRD3 |
| TCELL31:OUT6.TMIN | PCIE.PIPETX1DATA7 |
| TCELL31:OUT7.TMIN | PCIE.PIPETX1POWERDOWN1 |
| TCELL31:OUT8.TMIN | PCIE.TRNRD4 |
| TCELL31:OUT9.TMIN | PCIE.TRNRD5 |
| TCELL31:OUT10.TMIN | PCIE.TRNRD6 |
| TCELL31:OUT11.TMIN | PCIE.TRNFCNPD9 |
| TCELL31:OUT12.TMIN | PCIE.TRNFCNPD10 |
| TCELL31:OUT13.TMIN | PCIE.TRNFCNPD11 |
| TCELL31:OUT14.TMIN | PCIE.TRNFCCPLH0 |
| TCELL31:OUT15.TMIN | PCIE.TL2ERRHDR37 |
| TCELL31:OUT16.TMIN | PCIE.PIPETX1CHARISK0 |
| TCELL31:OUT17.TMIN | PCIE.TL2ERRHDR38 |
| TCELL31:OUT18.TMIN | PCIE.DBGVECB59 |
| TCELL31:OUT19.TMIN | PCIE.DBGVECB60 |
| TCELL31:OUT20.TMIN | PCIE.DBGVECB61 |
| TCELL31:OUT21.TMIN | PCIE.DBGVECB62 |
| TCELL31:OUT22.TMIN | PCIE.XILUNCONNOUT17 |
| TCELL31:OUT23.TMIN | PCIE.XILUNCONNOUT18 |
| TCELL32:IMUX.IMUX0.DELAY | PCIE.TRNTD112 |
| TCELL32:IMUX.IMUX1.DELAY | PCIE.TRNTD113 |
| TCELL32:IMUX.IMUX2.DELAY | PCIE.TRNTD114 |
| TCELL32:IMUX.IMUX3.DELAY | PCIE.TRNTD115 |
| TCELL32:IMUX.IMUX4.DELAY | PCIE.CFGERRAERHEADERLOG102 |
| TCELL32:IMUX.IMUX5.DELAY | PCIE.CFGERRAERHEADERLOG103 |
| TCELL32:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG104 |
| TCELL32:IMUX.IMUX7.DELAY | PCIE.CFGERRAERHEADERLOG105 |
| TCELL32:IMUX.IMUX8.DELAY | PCIE.CFGDSN5 |
| TCELL32:IMUX.IMUX9.DELAY | PCIE.CFGDSN6 |
| TCELL32:IMUX.IMUX10.DELAY | PCIE.CFGDSN7 |
| TCELL32:IMUX.IMUX11.DELAY | PCIE.CFGDSN8 |
| TCELL32:IMUX.IMUX12.DELAY | PCIE.CFGSUBSYSID10 |
| TCELL32:IMUX.IMUX13.DELAY | PCIE.CFGSUBSYSID11 |
| TCELL32:IMUX.IMUX14.DELAY | PCIE.CFGSUBSYSID12 |
| TCELL32:IMUX.IMUX15.DELAY | PCIE.CFGSUBSYSID13 |
| TCELL32:IMUX.IMUX34.DELAY | PCIE.PIPERX1DATA15 |
| TCELL32:IMUX.IMUX35.DELAY | PCIE.PIPERX1DATA14 |
| TCELL32:IMUX.IMUX38.DELAY | PCIE.PIPERX1DATA13 |
| TCELL32:IMUX.IMUX39.DELAY | PCIE.PIPERX1DATA12 |
| TCELL32:OUT0.TMIN | PCIE.TRNRD7 |
| TCELL32:OUT1.TMIN | PCIE.PIPERX1POLARITY |
| TCELL32:OUT2.TMIN | PCIE.TRNRD8 |
| TCELL32:OUT3.TMIN | PCIE.PIPETX1COMPLIANCE |
| TCELL32:OUT4.TMIN | PCIE.TRNRD9 |
| TCELL32:OUT5.TMIN | PCIE.TRNRD10 |
| TCELL32:OUT6.TMIN | PCIE.TRNFCCPLH1 |
| TCELL32:OUT7.TMIN | PCIE.TRNFCCPLH2 |
| TCELL32:OUT8.TMIN | PCIE.TRNFCCPLH3 |
| TCELL32:OUT9.TMIN | PCIE.PIPETX1DATA0 |
| TCELL32:OUT10.TMIN | PCIE.TRNFCCPLH4 |
| TCELL32:OUT11.TMIN | PCIE.PIPETX1DATA2 |
| TCELL32:OUT12.TMIN | PCIE.TL2ERRHDR39 |
| TCELL32:OUT13.TMIN | PCIE.PIPETX1DATA1 |
| TCELL32:OUT14.TMIN | PCIE.TL2ERRHDR40 |
| TCELL32:OUT15.TMIN | PCIE.PIPETX1DATA3 |
| TCELL32:OUT16.TMIN | PCIE.TL2ERRHDR41 |
| TCELL32:OUT17.TMIN | PCIE.TL2ERRHDR42 |
| TCELL32:OUT18.TMIN | PCIE.DBGVECB63 |
| TCELL32:OUT19.TMIN | PCIE.DBGVECC0 |
| TCELL32:OUT20.TMIN | PCIE.DBGVECC1 |
| TCELL32:OUT21.TMIN | PCIE.DBGVECC2 |
| TCELL32:OUT22.TMIN | PCIE.XILUNCONNOUT19 |
| TCELL32:OUT23.TMIN | PCIE.XILUNCONNOUT20 |
| TCELL33:IMUX.IMUX0.DELAY | PCIE.TRNTD116 |
| TCELL33:IMUX.IMUX1.DELAY | PCIE.TRNTD117 |
| TCELL33:IMUX.IMUX2.DELAY | PCIE.TRNTD118 |
| TCELL33:IMUX.IMUX3.DELAY | PCIE.TRNTD119 |
| TCELL33:IMUX.IMUX4.DELAY | PCIE.CFGERRAERHEADERLOG106 |
| TCELL33:IMUX.IMUX5.DELAY | PCIE.CFGERRAERHEADERLOG107 |
| TCELL33:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG108 |
| TCELL33:IMUX.IMUX7.DELAY | PCIE.CFGERRAERHEADERLOG109 |
| TCELL33:IMUX.IMUX8.DELAY | PCIE.CFGDSN9 |
| TCELL33:IMUX.IMUX9.DELAY | PCIE.CFGDSN10 |
| TCELL33:IMUX.IMUX10.DELAY | PCIE.CFGDSN11 |
| TCELL33:IMUX.IMUX11.DELAY | PCIE.CFGDSN12 |
| TCELL33:IMUX.IMUX16.DELAY | PCIE.PIPERX1CHARISK1 |
| TCELL33:IMUX.IMUX32.DELAY | PCIE.PIPERX1DATA11 |
| TCELL33:IMUX.IMUX33.DELAY | PCIE.PIPERX1DATA10 |
| TCELL33:IMUX.IMUX34.DELAY | PCIE.PIPERX1ELECIDLE |
| TCELL33:IMUX.IMUX35.DELAY | PCIE.PIPERX1STATUS2 |
| TCELL33:IMUX.IMUX36.DELAY | PCIE.PIPERX1DATA9 |
| TCELL33:IMUX.IMUX37.DELAY | PCIE.PIPERX1DATA8 |
| TCELL33:IMUX.IMUX38.DELAY | PCIE.PIPERX1STATUS1 |
| TCELL33:IMUX.IMUX39.DELAY | PCIE.PIPERX1STATUS0 |
| TCELL33:OUT0.TMIN | PCIE.TRNRD11 |
| TCELL33:OUT1.TMIN | PCIE.TRNRD12 |
| TCELL33:OUT2.TMIN | PCIE.TRNRD13 |
| TCELL33:OUT3.TMIN | PCIE.TRNRD14 |
| TCELL33:OUT4.TMIN | PCIE.TRNFCCPLH5 |
| TCELL33:OUT5.TMIN | PCIE.TRNFCCPLH6 |
| TCELL33:OUT6.TMIN | PCIE.TRNFCCPLH7 |
| TCELL33:OUT7.TMIN | PCIE.TRNFCCPLD0 |
| TCELL33:OUT8.TMIN | PCIE.TL2ERRHDR43 |
| TCELL33:OUT9.TMIN | PCIE.TL2ERRHDR44 |
| TCELL33:OUT10.TMIN | PCIE.TL2ERRHDR45 |
| TCELL33:OUT11.TMIN | PCIE.TL2ERRHDR46 |
| TCELL33:OUT12.TMIN | PCIE.CFGINTERRUPTDO1 |
| TCELL33:OUT13.TMIN | PCIE.CFGINTERRUPTDO2 |
| TCELL33:OUT14.TMIN | PCIE.CFGINTERRUPTDO3 |
| TCELL33:OUT15.TMIN | PCIE.CFGINTERRUPTDO4 |
| TCELL33:OUT16.TMIN | PCIE.CFGCOMMANDSERREN |
| TCELL33:OUT17.TMIN | PCIE.CFGBRIDGESERREN |
| TCELL33:OUT18.TMIN | PCIE.DBGVECC3 |
| TCELL33:OUT19.TMIN | PCIE.DBGVECC4 |
| TCELL33:OUT20.TMIN | PCIE.DBGVECC5 |
| TCELL33:OUT21.TMIN | PCIE.DBGVECC6 |
| TCELL33:OUT22.TMIN | PCIE.XILUNCONNOUT21 |
| TCELL33:OUT23.TMIN | PCIE.XILUNCONNOUT22 |
| TCELL34:IMUX.IMUX0.DELAY | PCIE.TRNTD120 |
| TCELL34:IMUX.IMUX1.DELAY | PCIE.TRNTD121 |
| TCELL34:IMUX.IMUX2.DELAY | PCIE.TRNTD122 |
| TCELL34:IMUX.IMUX3.DELAY | PCIE.TRNTD123 |
| TCELL34:IMUX.IMUX4.DELAY | PCIE.CFGERRAERHEADERLOG110 |
| TCELL34:IMUX.IMUX5.DELAY | PCIE.CFGERRAERHEADERLOG111 |
| TCELL34:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG112 |
| TCELL34:IMUX.IMUX7.DELAY | PCIE.CFGERRAERHEADERLOG113 |
| TCELL34:IMUX.IMUX8.DELAY | PCIE.CFGDSN13 |
| TCELL34:IMUX.IMUX9.DELAY | PCIE.CFGDSN14 |
| TCELL34:IMUX.IMUX10.DELAY | PCIE.CFGDSN15 |
| TCELL34:IMUX.IMUX11.DELAY | PCIE.CFGDSN16 |
| TCELL34:IMUX.IMUX12.DELAY | PCIE.CFGSUBSYSID14 |
| TCELL34:IMUX.IMUX13.DELAY | PCIE.CFGSUBSYSID15 |
| TCELL34:IMUX.IMUX33.DELAY | PCIE.PIPERX1CHANISALIGNED |
| TCELL34:IMUX.IMUX34.DELAY | PCIE.PIPERX1DATA7 |
| TCELL34:IMUX.IMUX35.DELAY | PCIE.PIPERX1DATA6 |
| TCELL34:IMUX.IMUX36.DELAY | PCIE.PIPERX1VALID |
| TCELL34:IMUX.IMUX37.DELAY | PCIE.PIPERX1PHYSTATUS |
| TCELL34:IMUX.IMUX38.DELAY | PCIE.PIPERX1DATA5 |
| TCELL34:IMUX.IMUX39.DELAY | PCIE.PIPERX1DATA4 |
| TCELL34:OUT0.TMIN | PCIE.TRNRD15 |
| TCELL34:OUT1.TMIN | PCIE.TRNRD16 |
| TCELL34:OUT2.TMIN | PCIE.TRNRD17 |
| TCELL34:OUT3.TMIN | PCIE.TRNRD18 |
| TCELL34:OUT4.TMIN | PCIE.TRNFCCPLD1 |
| TCELL34:OUT5.TMIN | PCIE.TRNFCCPLD2 |
| TCELL34:OUT6.TMIN | PCIE.TRNFCCPLD3 |
| TCELL34:OUT7.TMIN | PCIE.TRNFCCPLD4 |
| TCELL34:OUT8.TMIN | PCIE.TL2ERRHDR47 |
| TCELL34:OUT9.TMIN | PCIE.TL2ERRHDR48 |
| TCELL34:OUT10.TMIN | PCIE.TL2ERRHDR49 |
| TCELL34:OUT11.TMIN | PCIE.TL2ERRHDR50 |
| TCELL34:OUT12.TMIN | PCIE.CFGINTERRUPTDO5 |
| TCELL34:OUT13.TMIN | PCIE.CFGINTERRUPTDO6 |
| TCELL34:OUT14.TMIN | PCIE.CFGINTERRUPTDO7 |
| TCELL34:OUT15.TMIN | PCIE.CFGMSGRECEIVED |
| TCELL34:OUT16.TMIN | PCIE.CFGDEVSTATUSCORRERRDETECTED |
| TCELL34:OUT17.TMIN | PCIE.CFGDEVSTATUSNONFATALERRDETECTED |
| TCELL34:OUT18.TMIN | PCIE.DBGVECC7 |
| TCELL34:OUT19.TMIN | PCIE.DBGVECC8 |
| TCELL34:OUT20.TMIN | PCIE.DBGVECC9 |
| TCELL34:OUT21.TMIN | PCIE.DBGVECC10 |
| TCELL34:OUT22.TMIN | PCIE.XILUNCONNOUT23 |
| TCELL34:OUT23.TMIN | PCIE.XILUNCONNOUT24 |
| TCELL35:IMUX.IMUX0.DELAY | PCIE.TRNTD124 |
| TCELL35:IMUX.IMUX1.DELAY | PCIE.TRNTD125 |
| TCELL35:IMUX.IMUX2.DELAY | PCIE.TRNTD126 |
| TCELL35:IMUX.IMUX3.DELAY | PCIE.TRNTD127 |
| TCELL35:IMUX.IMUX4.DELAY | PCIE.CFGERRAERHEADERLOG114 |
| TCELL35:IMUX.IMUX5.DELAY | PCIE.CFGERRAERHEADERLOG115 |
| TCELL35:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG116 |
| TCELL35:IMUX.IMUX7.DELAY | PCIE.CFGERRAERHEADERLOG117 |
| TCELL35:IMUX.IMUX8.DELAY | PCIE.CFGDSN17 |
| TCELL35:IMUX.IMUX9.DELAY | PCIE.CFGDSN18 |
| TCELL35:IMUX.IMUX10.DELAY | PCIE.CFGDSN19 |
| TCELL35:IMUX.IMUX11.DELAY | PCIE.CFGDSN20 |
| TCELL35:IMUX.IMUX12.DELAY | PCIE.CFGSUBSYSVENDID0 |
| TCELL35:IMUX.IMUX13.DELAY | PCIE.CFGSUBSYSVENDID1 |
| TCELL35:IMUX.IMUX14.DELAY | PCIE.CFGSUBSYSVENDID2 |
| TCELL35:IMUX.IMUX15.DELAY | PCIE.CFGSUBSYSVENDID3 |
| TCELL35:IMUX.IMUX16.DELAY | PCIE.PIPERX1CHARISK0 |
| TCELL35:IMUX.IMUX32.DELAY | PCIE.PIPERX1DATA3 |
| TCELL35:IMUX.IMUX33.DELAY | PCIE.PIPERX1DATA2 |
| TCELL35:IMUX.IMUX36.DELAY | PCIE.PIPERX1DATA1 |
| TCELL35:IMUX.IMUX37.DELAY | PCIE.PIPERX1DATA0 |
| TCELL35:OUT0.TMIN | PCIE.TRNRD19 |
| TCELL35:OUT1.TMIN | PCIE.TRNRD20 |
| TCELL35:OUT2.TMIN | PCIE.TRNRD21 |
| TCELL35:OUT3.TMIN | PCIE.TRNRD22 |
| TCELL35:OUT4.TMIN | PCIE.TRNFCCPLD5 |
| TCELL35:OUT5.TMIN | PCIE.TRNFCCPLD6 |
| TCELL35:OUT6.TMIN | PCIE.TRNFCCPLD7 |
| TCELL35:OUT7.TMIN | PCIE.TRNFCCPLD8 |
| TCELL35:OUT8.TMIN | PCIE.TL2ERRHDR51 |
| TCELL35:OUT9.TMIN | PCIE.TL2ERRHDR52 |
| TCELL35:OUT10.TMIN | PCIE.TL2ERRHDR53 |
| TCELL35:OUT11.TMIN | PCIE.TL2ERRHDR54 |
| TCELL35:OUT12.TMIN | PCIE.CFGMSGDATA0 |
| TCELL35:OUT13.TMIN | PCIE.CFGMSGDATA1 |
| TCELL35:OUT14.TMIN | PCIE.CFGMSGDATA2 |
| TCELL35:OUT15.TMIN | PCIE.CFGMSGDATA3 |
| TCELL35:OUT16.TMIN | PCIE.CFGDEVSTATUSFATALERRDETECTED |
| TCELL35:OUT17.TMIN | PCIE.CFGDEVSTATUSURDETECTED |
| TCELL35:OUT18.TMIN | PCIE.DBGVECC11 |
| TCELL35:OUT19.TMIN | PCIE.DBGSCLRA |
| TCELL35:OUT20.TMIN | PCIE.DBGSCLRB |
| TCELL35:OUT21.TMIN | PCIE.DBGSCLRC |
| TCELL35:OUT22.TMIN | PCIE.XILUNCONNOUT25 |
| TCELL35:OUT23.TMIN | PCIE.XILUNCONNOUT26 |
| TCELL36:IMUX.IMUX0.DELAY | PCIE.TRNTREM0 |
| TCELL36:IMUX.IMUX1.DELAY | PCIE.TRNTREM1 |
| TCELL36:IMUX.IMUX2.DELAY | PCIE.TRNTSOF |
| TCELL36:IMUX.IMUX3.DELAY | PCIE.TRNTEOF |
| TCELL36:IMUX.IMUX4.DELAY | PCIE.CFGERRAERHEADERLOG118 |
| TCELL36:IMUX.IMUX5.DELAY | PCIE.CFGERRAERHEADERLOG119 |
| TCELL36:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG120 |
| TCELL36:IMUX.IMUX7.DELAY | PCIE.CFGERRAERHEADERLOG121 |
| TCELL36:IMUX.IMUX8.DELAY | PCIE.CFGDSN21 |
| TCELL36:IMUX.IMUX9.DELAY | PCIE.CFGDSN22 |
| TCELL36:IMUX.IMUX10.DELAY | PCIE.CFGDSN23 |
| TCELL36:IMUX.IMUX11.DELAY | PCIE.CFGDSN24 |
| TCELL36:IMUX.IMUX12.DELAY | PCIE.CFGSUBSYSVENDID4 |
| TCELL36:IMUX.IMUX13.DELAY | PCIE.CFGSUBSYSVENDID5 |
| TCELL36:IMUX.IMUX14.DELAY | PCIE.CFGSUBSYSVENDID6 |
| TCELL36:IMUX.IMUX15.DELAY | PCIE.CFGSUBSYSVENDID7 |
| TCELL36:OUT0.TMIN | PCIE.PIPETX2DATA12 |
| TCELL36:OUT1.TMIN | PCIE.TRNRD23 |
| TCELL36:OUT2.TMIN | PCIE.PIPETX2DATA14 |
| TCELL36:OUT3.TMIN | PCIE.TRNRD24 |
| TCELL36:OUT4.TMIN | PCIE.PIPETX2DATA13 |
| TCELL36:OUT5.TMIN | PCIE.TRNRD25 |
| TCELL36:OUT6.TMIN | PCIE.PIPETX2DATA15 |
| TCELL36:OUT7.TMIN | PCIE.TRNRD26 |
| TCELL36:OUT8.TMIN | PCIE.TRNFCCPLD9 |
| TCELL36:OUT9.TMIN | PCIE.TRNFCCPLD10 |
| TCELL36:OUT10.TMIN | PCIE.TRNFCCPLD11 |
| TCELL36:OUT11.TMIN | PCIE.TRNTDLLPDSTRDY |
| TCELL36:OUT12.TMIN | PCIE.TL2ERRHDR55 |
| TCELL36:OUT13.TMIN | PCIE.TL2ERRHDR56 |
| TCELL36:OUT14.TMIN | PCIE.TL2ERRHDR57 |
| TCELL36:OUT15.TMIN | PCIE.TL2ERRHDR58 |
| TCELL36:OUT16.TMIN | PCIE.PIPETX2CHARISK1 |
| TCELL36:OUT17.TMIN | PCIE.CFGMSGDATA4 |
| TCELL36:OUT18.TMIN | PCIE.CFGMSGDATA5 |
| TCELL36:OUT19.TMIN | PCIE.DBGSCLRD |
| TCELL36:OUT20.TMIN | PCIE.DBGSCLRE |
| TCELL36:OUT21.TMIN | PCIE.DBGSCLRF |
| TCELL36:OUT22.TMIN | PCIE.DBGSCLRG |
| TCELL36:OUT23.TMIN | PCIE.XILUNCONNOUT27 |
| TCELL37:IMUX.IMUX0.DELAY | PCIE.TRNTSRCRDY |
| TCELL37:IMUX.IMUX1.DELAY | PCIE.TRNTSRCDSC |
| TCELL37:IMUX.IMUX2.DELAY | PCIE.TRNTERRFWD |
| TCELL37:IMUX.IMUX3.DELAY | PCIE.TRNTECRCGEN |
| TCELL37:IMUX.IMUX4.DELAY | PCIE.CFGERRAERHEADERLOG122 |
| TCELL37:IMUX.IMUX5.DELAY | PCIE.CFGERRAERHEADERLOG123 |
| TCELL37:IMUX.IMUX6.DELAY | PCIE.CFGERRAERHEADERLOG124 |
| TCELL37:IMUX.IMUX7.DELAY | PCIE.CFGERRAERHEADERLOG125 |
| TCELL37:IMUX.IMUX8.DELAY | PCIE.CFGDSN25 |
| TCELL37:IMUX.IMUX9.DELAY | PCIE.CFGDSN26 |
| TCELL37:IMUX.IMUX10.DELAY | PCIE.CFGDSN27 |
| TCELL37:IMUX.IMUX11.DELAY | PCIE.CFGDSN28 |
| TCELL37:IMUX.IMUX12.DELAY | PCIE.CFGSUBSYSVENDID8 |
| TCELL37:IMUX.IMUX13.DELAY | PCIE.CFGSUBSYSVENDID9 |
| TCELL37:IMUX.IMUX14.DELAY | PCIE.CFGSUBSYSVENDID10 |
| TCELL37:IMUX.IMUX15.DELAY | PCIE.CFGSUBSYSVENDID11 |
| TCELL37:OUT0.TMIN | PCIE.TRNRD27 |
| TCELL37:OUT1.TMIN | PCIE.TRNRD28 |
| TCELL37:OUT2.TMIN | PCIE.TRNRD29 |
| TCELL37:OUT3.TMIN | PCIE.TRNRD30 |
| TCELL37:OUT4.TMIN | PCIE.TRNRDLLPDATA0 |
| TCELL37:OUT5.TMIN | PCIE.TRNRDLLPDATA1 |
| TCELL37:OUT6.TMIN | PCIE.TRNRDLLPDATA2 |
| TCELL37:OUT7.TMIN | PCIE.TRNRDLLPDATA3 |
| TCELL37:OUT8.TMIN | PCIE.TL2ERRHDR59 |
| TCELL37:OUT9.TMIN | PCIE.PIPETX2DATA8 |
| TCELL37:OUT10.TMIN | PCIE.TL2ERRHDR60 |
| TCELL37:OUT11.TMIN | PCIE.PIPETX2DATA10 |
| TCELL37:OUT12.TMIN | PCIE.TL2ERRHDR61 |
| TCELL37:OUT13.TMIN | PCIE.PIPETX2DATA9 |
| TCELL37:OUT14.TMIN | PCIE.TL2ERRHDR62 |
| TCELL37:OUT15.TMIN | PCIE.PIPETX2DATA11 |
| TCELL37:OUT16.TMIN | PCIE.CFGMSGDATA6 |
| TCELL37:OUT17.TMIN | PCIE.CFGMSGDATA7 |
| TCELL37:OUT18.TMIN | PCIE.CFGMSGDATA8 |
| TCELL37:OUT19.TMIN | PCIE.CFGMSGDATA9 |
| TCELL37:OUT20.TMIN | PCIE.CFGDEVCONTROLCORRERRREPORTINGEN |
| TCELL37:OUT21.TMIN | PCIE.CFGDEVCONTROLNONFATALREPORTINGEN |
| TCELL37:OUT22.TMIN | PCIE.DBGSCLRH |
| TCELL37:OUT23.TMIN | PCIE.DBGSCLRI |
| TCELL38:IMUX.IMUX0.DELAY | PCIE.TRNTSTR |
| TCELL38:IMUX.IMUX1.DELAY | PCIE.TRNTCFGGNT |
| TCELL38:IMUX.IMUX2.DELAY | PCIE.TRNRDSTRDY |
| TCELL38:IMUX.IMUX3.DELAY | PCIE.TRNRNPREQ |
| TCELL38:IMUX.IMUX4.DELAY | PCIE.CFGERRAERHEADERLOG126 |
| TCELL38:IMUX.IMUX5.DELAY | PCIE.CFGERRAERHEADERLOG127 |
| TCELL38:IMUX.IMUX6.DELAY | PCIE.CFGERRTLPCPLHEADER0 |
| TCELL38:IMUX.IMUX7.DELAY | PCIE.CFGERRTLPCPLHEADER1 |
| TCELL38:IMUX.IMUX8.DELAY | PCIE.CFGDSN29 |
| TCELL38:IMUX.IMUX9.DELAY | PCIE.CFGDSN30 |
| TCELL38:IMUX.IMUX10.DELAY | PCIE.CFGDSN31 |
| TCELL38:IMUX.IMUX11.DELAY | PCIE.CFGDSN32 |
| TCELL38:IMUX.IMUX12.DELAY | PCIE.CFGSUBSYSVENDID12 |
| TCELL38:IMUX.IMUX13.DELAY | PCIE.CFGSUBSYSVENDID13 |
| TCELL38:IMUX.IMUX14.DELAY | PCIE.CFGSUBSYSVENDID14 |
| TCELL38:IMUX.IMUX15.DELAY | PCIE.CFGSUBSYSVENDID15 |
| TCELL38:OUT0.TMIN | PCIE.PIPETX2DATA4 |
| TCELL38:OUT1.TMIN | PCIE.PIPETX2POWERDOWN0 |
| TCELL38:OUT2.TMIN | PCIE.PIPETX2DATA6 |
| TCELL38:OUT3.TMIN | PCIE.PIPETX2ELECIDLE |
| TCELL38:OUT4.TMIN | PCIE.PIPETX2DATA5 |
| TCELL38:OUT5.TMIN | PCIE.TRNRD31 |
| TCELL38:OUT6.TMIN | PCIE.PIPETX2DATA7 |
| TCELL38:OUT7.TMIN | PCIE.PIPETX2POWERDOWN1 |
| TCELL38:OUT8.TMIN | PCIE.TRNRD32 |
| TCELL38:OUT9.TMIN | PCIE.TRNRD33 |
| TCELL38:OUT10.TMIN | PCIE.TRNRD34 |
| TCELL38:OUT11.TMIN | PCIE.TRNRDLLPDATA4 |
| TCELL38:OUT12.TMIN | PCIE.TRNRDLLPDATA5 |
| TCELL38:OUT13.TMIN | PCIE.TRNRDLLPDATA6 |
| TCELL38:OUT14.TMIN | PCIE.TRNRDLLPDATA7 |
| TCELL38:OUT15.TMIN | PCIE.TL2ERRHDR63 |
| TCELL38:OUT16.TMIN | PCIE.PIPETX2CHARISK0 |
| TCELL38:OUT17.TMIN | PCIE.TL2ERRMALFORMED |
| TCELL38:OUT18.TMIN | PCIE.TL2ERRRXOVERFLOW |
| TCELL38:OUT19.TMIN | PCIE.TL2ERRFCPE |
| TCELL38:OUT20.TMIN | PCIE.CFGDEVCONTROLFATALERRREPORTINGEN |
| TCELL38:OUT21.TMIN | PCIE.CFGDEVCONTROLURERRREPORTINGEN |
| TCELL38:OUT22.TMIN | PCIE.DBGSCLRJ |
| TCELL38:OUT23.TMIN | PCIE.DBGSCLRK |
| TCELL39:IMUX.IMUX0.DELAY | PCIE.TRNRFCPRET |
| TCELL39:IMUX.IMUX1.DELAY | PCIE.TRNRNPOK |
| TCELL39:IMUX.IMUX2.DELAY | PCIE.TRNFCSEL0 |
| TCELL39:IMUX.IMUX3.DELAY | PCIE.TRNFCSEL1 |
| TCELL39:IMUX.IMUX4.DELAY | PCIE.CFGERRTLPCPLHEADER2 |
| TCELL39:IMUX.IMUX5.DELAY | PCIE.CFGERRTLPCPLHEADER3 |
| TCELL39:IMUX.IMUX6.DELAY | PCIE.CFGERRTLPCPLHEADER4 |
| TCELL39:IMUX.IMUX7.DELAY | PCIE.CFGERRTLPCPLHEADER5 |
| TCELL39:IMUX.IMUX8.DELAY | PCIE.CFGDSN33 |
| TCELL39:IMUX.IMUX9.DELAY | PCIE.CFGDSN34 |
| TCELL39:IMUX.IMUX10.DELAY | PCIE.CFGDSN35 |
| TCELL39:IMUX.IMUX11.DELAY | PCIE.CFGDSN36 |
| TCELL39:IMUX.IMUX12.DELAY | PCIE.CFGAERINTERRUPTMSGNUM0 |
| TCELL39:IMUX.IMUX13.DELAY | PCIE.CFGAERINTERRUPTMSGNUM1 |
| TCELL39:IMUX.IMUX14.DELAY | PCIE.CFGAERINTERRUPTMSGNUM2 |
| TCELL39:IMUX.IMUX15.DELAY | PCIE.CFGAERINTERRUPTMSGNUM3 |
| TCELL39:IMUX.IMUX34.DELAY | PCIE.PIPERX2DATA15 |
| TCELL39:IMUX.IMUX35.DELAY | PCIE.PIPERX2DATA14 |
| TCELL39:IMUX.IMUX38.DELAY | PCIE.PIPERX2DATA13 |
| TCELL39:IMUX.IMUX39.DELAY | PCIE.PIPERX2DATA12 |
| TCELL39:OUT0.TMIN | PCIE.TRNRD35 |
| TCELL39:OUT1.TMIN | PCIE.PIPERX2POLARITY |
| TCELL39:OUT2.TMIN | PCIE.TRNRD36 |
| TCELL39:OUT3.TMIN | PCIE.PIPETX2COMPLIANCE |
| TCELL39:OUT4.TMIN | PCIE.TRNRD37 |
| TCELL39:OUT5.TMIN | PCIE.TRNRD38 |
| TCELL39:OUT6.TMIN | PCIE.TRNRDLLPDATA8 |
| TCELL39:OUT7.TMIN | PCIE.TRNRDLLPDATA9 |
| TCELL39:OUT8.TMIN | PCIE.TRNRDLLPDATA10 |
| TCELL39:OUT9.TMIN | PCIE.PIPETX2DATA0 |
| TCELL39:OUT10.TMIN | PCIE.TRNRDLLPDATA11 |
| TCELL39:OUT11.TMIN | PCIE.PIPETX2DATA2 |
| TCELL39:OUT12.TMIN | PCIE.CFGMSGDATA10 |
| TCELL39:OUT13.TMIN | PCIE.PIPETX2DATA1 |
| TCELL39:OUT14.TMIN | PCIE.CFGMSGDATA11 |
| TCELL39:OUT15.TMIN | PCIE.PIPETX2DATA3 |
| TCELL39:OUT16.TMIN | PCIE.CFGMSGDATA12 |
| TCELL39:OUT17.TMIN | PCIE.CFGMSGDATA13 |
| TCELL39:OUT18.TMIN | PCIE.CFGDEVCONTROLENABLERO |
| TCELL39:OUT19.TMIN | PCIE.CFGDEVCONTROLMAXPAYLOAD0 |
| TCELL39:OUT20.TMIN | PCIE.CFGDEVCONTROLMAXPAYLOAD1 |
| TCELL39:OUT21.TMIN | PCIE.CFGDEVCONTROLMAXPAYLOAD2 |
| TCELL39:OUT22.TMIN | PCIE.PLDBGVEC0 |
| TCELL39:OUT23.TMIN | PCIE.PLDBGVEC1 |
| TCELL40:IMUX.IMUX0.DELAY | PCIE.TRNFCSEL2 |
| TCELL40:IMUX.IMUX1.DELAY | PCIE.TRNTDLLPDATA0 |
| TCELL40:IMUX.IMUX2.DELAY | PCIE.TRNTDLLPDATA1 |
| TCELL40:IMUX.IMUX3.DELAY | PCIE.TRNTDLLPDATA2 |
| TCELL40:IMUX.IMUX4.DELAY | PCIE.CFGERRTLPCPLHEADER6 |
| TCELL40:IMUX.IMUX5.DELAY | PCIE.CFGERRTLPCPLHEADER7 |
| TCELL40:IMUX.IMUX6.DELAY | PCIE.CFGERRTLPCPLHEADER8 |
| TCELL40:IMUX.IMUX7.DELAY | PCIE.CFGERRTLPCPLHEADER9 |
| TCELL40:IMUX.IMUX8.DELAY | PCIE.CFGDSN37 |
| TCELL40:IMUX.IMUX9.DELAY | PCIE.CFGDSN38 |
| TCELL40:IMUX.IMUX10.DELAY | PCIE.CFGDSN39 |
| TCELL40:IMUX.IMUX11.DELAY | PCIE.CFGDSN40 |
| TCELL40:IMUX.IMUX16.DELAY | PCIE.PIPERX2CHARISK1 |
| TCELL40:IMUX.IMUX32.DELAY | PCIE.PIPERX2DATA11 |
| TCELL40:IMUX.IMUX33.DELAY | PCIE.PIPERX2DATA10 |
| TCELL40:IMUX.IMUX34.DELAY | PCIE.PIPERX2ELECIDLE |
| TCELL40:IMUX.IMUX35.DELAY | PCIE.PIPERX2STATUS2 |
| TCELL40:IMUX.IMUX36.DELAY | PCIE.PIPERX2DATA9 |
| TCELL40:IMUX.IMUX37.DELAY | PCIE.PIPERX2DATA8 |
| TCELL40:IMUX.IMUX38.DELAY | PCIE.PIPERX2STATUS1 |
| TCELL40:IMUX.IMUX39.DELAY | PCIE.PIPERX2STATUS0 |
| TCELL40:OUT0.TMIN | PCIE.PIPETX0DATA12 |
| TCELL40:OUT1.TMIN | PCIE.TRNRD39 |
| TCELL40:OUT2.TMIN | PCIE.PIPETX0DATA14 |
| TCELL40:OUT3.TMIN | PCIE.TRNRD40 |
| TCELL40:OUT4.TMIN | PCIE.PIPETX0DATA13 |
| TCELL40:OUT5.TMIN | PCIE.TRNRD41 |
| TCELL40:OUT6.TMIN | PCIE.PIPETX0DATA15 |
| TCELL40:OUT7.TMIN | PCIE.TRNRD42 |
| TCELL40:OUT8.TMIN | PCIE.TRNRDLLPDATA12 |
| TCELL40:OUT9.TMIN | PCIE.TRNRDLLPDATA13 |
| TCELL40:OUT10.TMIN | PCIE.TRNRDLLPDATA14 |
| TCELL40:OUT11.TMIN | PCIE.TRNRDLLPDATA15 |
| TCELL40:OUT12.TMIN | PCIE.CFGMSGDATA14 |
| TCELL40:OUT13.TMIN | PCIE.CFGMSGDATA15 |
| TCELL40:OUT14.TMIN | PCIE.CFGMSGRECEIVEDERRCOR |
| TCELL40:OUT15.TMIN | PCIE.CFGMSGRECEIVEDERRNONFATAL |
| TCELL40:OUT16.TMIN | PCIE.PIPETX0CHARISK1 |
| TCELL40:OUT17.TMIN | PCIE.CFGDEVCONTROLEXTTAGEN |
| TCELL40:OUT18.TMIN | PCIE.CFGDEVCONTROLPHANTOMEN |
| TCELL40:OUT19.TMIN | PCIE.CFGDEVCONTROLAUXPOWEREN |
| TCELL40:OUT20.TMIN | PCIE.CFGDEVCONTROLNOSNOOPEN |
| TCELL40:OUT21.TMIN | PCIE.CFGDEVCONTROL2TLPPREFIXBLOCK |
| TCELL40:OUT22.TMIN | PCIE.CFGSLOTCONTROLELECTROMECHILCTLPULSE |
| TCELL40:OUT23.TMIN | PCIE.PLDBGVEC2 |
| TCELL41:IMUX.IMUX0.DELAY | PCIE.TRNTDLLPDATA3 |
| TCELL41:IMUX.IMUX1.DELAY | PCIE.TRNTDLLPDATA4 |
| TCELL41:IMUX.IMUX2.DELAY | PCIE.TRNTDLLPDATA5 |
| TCELL41:IMUX.IMUX3.DELAY | PCIE.TRNTDLLPDATA6 |
| TCELL41:IMUX.IMUX4.DELAY | PCIE.CFGERRTLPCPLHEADER10 |
| TCELL41:IMUX.IMUX5.DELAY | PCIE.CFGERRTLPCPLHEADER11 |
| TCELL41:IMUX.IMUX6.DELAY | PCIE.CFGERRTLPCPLHEADER12 |
| TCELL41:IMUX.IMUX7.DELAY | PCIE.CFGERRTLPCPLHEADER13 |
| TCELL41:IMUX.IMUX8.DELAY | PCIE.CFGDSN41 |
| TCELL41:IMUX.IMUX9.DELAY | PCIE.CFGDSN42 |
| TCELL41:IMUX.IMUX10.DELAY | PCIE.CFGDSN43 |
| TCELL41:IMUX.IMUX11.DELAY | PCIE.CFGDSN44 |
| TCELL41:IMUX.IMUX12.DELAY | PCIE.CFGAERINTERRUPTMSGNUM4 |
| TCELL41:IMUX.IMUX13.DELAY | PCIE.DRPEN |
| TCELL41:IMUX.IMUX33.DELAY | PCIE.PIPERX2CHANISALIGNED |
| TCELL41:IMUX.IMUX34.DELAY | PCIE.PIPERX2DATA7 |
| TCELL41:IMUX.IMUX35.DELAY | PCIE.PIPERX2DATA6 |
| TCELL41:IMUX.IMUX36.DELAY | PCIE.PIPERX2VALID |
| TCELL41:IMUX.IMUX37.DELAY | PCIE.PIPERX2PHYSTATUS |
| TCELL41:IMUX.IMUX38.DELAY | PCIE.PIPERX2DATA5 |
| TCELL41:IMUX.IMUX39.DELAY | PCIE.PIPERX2DATA4 |
| TCELL41:OUT0.TMIN | PCIE.TRNRD43 |
| TCELL41:OUT1.TMIN | PCIE.TRNRD44 |
| TCELL41:OUT2.TMIN | PCIE.TRNRD45 |
| TCELL41:OUT3.TMIN | PCIE.TRNRD46 |
| TCELL41:OUT4.TMIN | PCIE.TRNRDLLPDATA16 |
| TCELL41:OUT5.TMIN | PCIE.TRNRDLLPDATA17 |
| TCELL41:OUT6.TMIN | PCIE.TRNRDLLPDATA18 |
| TCELL41:OUT7.TMIN | PCIE.TRNRDLLPDATA19 |
| TCELL41:OUT8.TMIN | PCIE.CFGMSGRECEIVEDERRFATAL |
| TCELL41:OUT9.TMIN | PCIE.PIPETX0DATA8 |
| TCELL41:OUT10.TMIN | PCIE.CFGMSGRECEIVEDASSERTINTA |
| TCELL41:OUT11.TMIN | PCIE.PIPETX0DATA10 |
| TCELL41:OUT12.TMIN | PCIE.CFGMSGRECEIVEDDEASSERTINTA |
| TCELL41:OUT13.TMIN | PCIE.PIPETX0DATA9 |
| TCELL41:OUT14.TMIN | PCIE.CFGMSGRECEIVEDASSERTINTB |
| TCELL41:OUT15.TMIN | PCIE.PIPETX0DATA11 |
| TCELL41:OUT16.TMIN | PCIE.CFGDEVCONTROLMAXREADREQ0 |
| TCELL41:OUT17.TMIN | PCIE.CFGDEVCONTROLMAXREADREQ1 |
| TCELL41:OUT18.TMIN | PCIE.CFGDEVCONTROLMAXREADREQ2 |
| TCELL41:OUT19.TMIN | PCIE.CFGLINKSTATUSCURRENTSPEED0 |
| TCELL41:OUT20.TMIN | PCIE.CFGROOTCONTROLSYSERRCORRERREN |
| TCELL41:OUT21.TMIN | PCIE.CFGROOTCONTROLSYSERRNONFATALERREN |
| TCELL41:OUT22.TMIN | PCIE.PLDBGVEC3 |
| TCELL41:OUT23.TMIN | PCIE.PLDBGVEC4 |
| TCELL42:IMUX.IMUX0.DELAY | PCIE.TRNTDLLPDATA7 |
| TCELL42:IMUX.IMUX1.DELAY | PCIE.TRNTDLLPDATA8 |
| TCELL42:IMUX.IMUX2.DELAY | PCIE.TRNTDLLPDATA9 |
| TCELL42:IMUX.IMUX3.DELAY | PCIE.TRNTDLLPDATA10 |
| TCELL42:IMUX.IMUX4.DELAY | PCIE.CFGERRTLPCPLHEADER14 |
| TCELL42:IMUX.IMUX5.DELAY | PCIE.CFGERRTLPCPLHEADER15 |
| TCELL42:IMUX.IMUX6.DELAY | PCIE.CFGERRTLPCPLHEADER16 |
| TCELL42:IMUX.IMUX7.DELAY | PCIE.CFGERRTLPCPLHEADER17 |
| TCELL42:IMUX.IMUX8.DELAY | PCIE.CFGDSN45 |
| TCELL42:IMUX.IMUX9.DELAY | PCIE.CFGDSN46 |
| TCELL42:IMUX.IMUX10.DELAY | PCIE.CFGDSN47 |
| TCELL42:IMUX.IMUX11.DELAY | PCIE.CFGDSN48 |
| TCELL42:IMUX.IMUX12.DELAY | PCIE.DRPWE |
| TCELL42:IMUX.IMUX13.DELAY | PCIE.DRPADDR0 |
| TCELL42:IMUX.IMUX14.DELAY | PCIE.DRPADDR1 |
| TCELL42:IMUX.IMUX15.DELAY | PCIE.DRPADDR2 |
| TCELL42:IMUX.IMUX16.DELAY | PCIE.PIPERX2CHARISK0 |
| TCELL42:IMUX.IMUX32.DELAY | PCIE.PIPERX2DATA3 |
| TCELL42:IMUX.IMUX33.DELAY | PCIE.PIPERX2DATA2 |
| TCELL42:IMUX.IMUX36.DELAY | PCIE.PIPERX2DATA1 |
| TCELL42:IMUX.IMUX37.DELAY | PCIE.PIPERX2DATA0 |
| TCELL42:OUT0.TMIN | PCIE.PIPETX0DATA4 |
| TCELL42:OUT1.TMIN | PCIE.PIPETX0POWERDOWN0 |
| TCELL42:OUT2.TMIN | PCIE.PIPETX0DATA6 |
| TCELL42:OUT3.TMIN | PCIE.PIPETX0ELECIDLE |
| TCELL42:OUT4.TMIN | PCIE.PIPETX0DATA5 |
| TCELL42:OUT5.TMIN | PCIE.TRNRD47 |
| TCELL42:OUT6.TMIN | PCIE.PIPETX0DATA7 |
| TCELL42:OUT7.TMIN | PCIE.PIPETX0POWERDOWN1 |
| TCELL42:OUT8.TMIN | PCIE.TRNRD48 |
| TCELL42:OUT9.TMIN | PCIE.TRNRD49 |
| TCELL42:OUT10.TMIN | PCIE.TRNRD50 |
| TCELL42:OUT11.TMIN | PCIE.TRNRDLLPDATA20 |
| TCELL42:OUT12.TMIN | PCIE.TRNRDLLPDATA21 |
| TCELL42:OUT13.TMIN | PCIE.TRNRDLLPDATA22 |
| TCELL42:OUT14.TMIN | PCIE.TRNRDLLPDATA23 |
| TCELL42:OUT15.TMIN | PCIE.CFGMSGRECEIVEDDEASSERTINTB |
| TCELL42:OUT16.TMIN | PCIE.PIPETX0CHARISK0 |
| TCELL42:OUT17.TMIN | PCIE.CFGMSGRECEIVEDASSERTINTC |
| TCELL42:OUT18.TMIN | PCIE.CFGMSGRECEIVEDDEASSERTINTC |
| TCELL42:OUT19.TMIN | PCIE.CFGMSGRECEIVEDASSERTINTD |
| TCELL42:OUT20.TMIN | PCIE.CFGLINKSTATUSCURRENTSPEED1 |
| TCELL42:OUT21.TMIN | PCIE.CFGLINKSTATUSNEGOTIATEDWIDTH0 |
| TCELL42:OUT22.TMIN | PCIE.PLDBGVEC5 |
| TCELL42:OUT23.TMIN | PCIE.PLDBGVEC6 |
| TCELL43:IMUX.IMUX0.DELAY | PCIE.TRNTDLLPDATA11 |
| TCELL43:IMUX.IMUX1.DELAY | PCIE.TRNTDLLPDATA12 |
| TCELL43:IMUX.IMUX2.DELAY | PCIE.TRNTDLLPDATA13 |
| TCELL43:IMUX.IMUX3.DELAY | PCIE.TRNTDLLPDATA14 |
| TCELL43:IMUX.IMUX4.DELAY | PCIE.CFGERRTLPCPLHEADER18 |
| TCELL43:IMUX.IMUX5.DELAY | PCIE.CFGERRTLPCPLHEADER19 |
| TCELL43:IMUX.IMUX6.DELAY | PCIE.CFGERRTLPCPLHEADER20 |
| TCELL43:IMUX.IMUX7.DELAY | PCIE.CFGERRTLPCPLHEADER21 |
| TCELL43:IMUX.IMUX8.DELAY | PCIE.CFGDSN49 |
| TCELL43:IMUX.IMUX9.DELAY | PCIE.CFGDSN50 |
| TCELL43:IMUX.IMUX10.DELAY | PCIE.CFGDSN51 |
| TCELL43:IMUX.IMUX11.DELAY | PCIE.CFGDSN52 |
| TCELL43:IMUX.IMUX12.DELAY | PCIE.DRPADDR3 |
| TCELL43:IMUX.IMUX13.DELAY | PCIE.DRPADDR4 |
| TCELL43:IMUX.IMUX14.DELAY | PCIE.DRPADDR5 |
| TCELL43:IMUX.IMUX15.DELAY | PCIE.DRPADDR6 |
| TCELL43:IMUX.IMUX34.DELAY | PCIE.PIPERX0DATA15 |
| TCELL43:IMUX.IMUX35.DELAY | PCIE.PIPERX0DATA14 |
| TCELL43:IMUX.IMUX38.DELAY | PCIE.PIPERX0DATA13 |
| TCELL43:IMUX.IMUX39.DELAY | PCIE.PIPERX0DATA12 |
| TCELL43:OUT0.TMIN | PCIE.TRNRD51 |
| TCELL43:OUT1.TMIN | PCIE.PIPERX0POLARITY |
| TCELL43:OUT2.TMIN | PCIE.TRNRD52 |
| TCELL43:OUT3.TMIN | PCIE.PIPETX0COMPLIANCE |
| TCELL43:OUT4.TMIN | PCIE.TRNRD53 |
| TCELL43:OUT5.TMIN | PCIE.TRNRD54 |
| TCELL43:OUT6.TMIN | PCIE.TRNRDLLPDATA24 |
| TCELL43:OUT7.TMIN | PCIE.TRNRDLLPDATA25 |
| TCELL43:OUT8.TMIN | PCIE.TRNRDLLPDATA26 |
| TCELL43:OUT9.TMIN | PCIE.PIPETX0DATA0 |
| TCELL43:OUT10.TMIN | PCIE.TRNRDLLPDATA27 |
| TCELL43:OUT11.TMIN | PCIE.PIPETX0DATA2 |
| TCELL43:OUT12.TMIN | PCIE.CFGMSGRECEIVEDDEASSERTINTD |
| TCELL43:OUT13.TMIN | PCIE.PIPETX0DATA1 |
| TCELL43:OUT14.TMIN | PCIE.CFGMSGRECEIVEDPMPME |
| TCELL43:OUT15.TMIN | PCIE.PIPETX0DATA3 |
| TCELL43:OUT16.TMIN | PCIE.CFGMSGRECEIVEDPMETOACK |
| TCELL43:OUT17.TMIN | PCIE.CFGMSGRECEIVEDPMETO |
| TCELL43:OUT18.TMIN | PCIE.CFGLINKSTATUSNEGOTIATEDWIDTH1 |
| TCELL43:OUT19.TMIN | PCIE.CFGLINKSTATUSNEGOTIATEDWIDTH2 |
| TCELL43:OUT20.TMIN | PCIE.CFGLINKSTATUSNEGOTIATEDWIDTH3 |
| TCELL43:OUT21.TMIN | PCIE.CFGLINKSTATUSLINKTRAINING |
| TCELL43:OUT22.TMIN | PCIE.CFGROOTCONTROLSYSERRFATALERREN |
| TCELL43:OUT23.TMIN | PCIE.PLDBGVEC7 |
| TCELL44:IMUX.IMUX0.DELAY | PCIE.TRNTDLLPDATA15 |
| TCELL44:IMUX.IMUX1.DELAY | PCIE.TRNTDLLPDATA16 |
| TCELL44:IMUX.IMUX2.DELAY | PCIE.TRNTDLLPDATA17 |
| TCELL44:IMUX.IMUX3.DELAY | PCIE.TRNTDLLPDATA18 |
| TCELL44:IMUX.IMUX4.DELAY | PCIE.CFGERRTLPCPLHEADER22 |
| TCELL44:IMUX.IMUX5.DELAY | PCIE.CFGERRTLPCPLHEADER23 |
| TCELL44:IMUX.IMUX6.DELAY | PCIE.CFGERRTLPCPLHEADER24 |
| TCELL44:IMUX.IMUX7.DELAY | PCIE.CFGERRTLPCPLHEADER25 |
| TCELL44:IMUX.IMUX8.DELAY | PCIE.CFGDSN53 |
| TCELL44:IMUX.IMUX9.DELAY | PCIE.CFGDSN54 |
| TCELL44:IMUX.IMUX10.DELAY | PCIE.CFGDSN55 |
| TCELL44:IMUX.IMUX11.DELAY | PCIE.CFGDSN56 |
| TCELL44:IMUX.IMUX16.DELAY | PCIE.PIPERX0CHARISK1 |
| TCELL44:IMUX.IMUX32.DELAY | PCIE.PIPERX0DATA11 |
| TCELL44:IMUX.IMUX33.DELAY | PCIE.PIPERX0DATA10 |
| TCELL44:IMUX.IMUX34.DELAY | PCIE.PIPERX0ELECIDLE |
| TCELL44:IMUX.IMUX35.DELAY | PCIE.PIPERX0STATUS2 |
| TCELL44:IMUX.IMUX36.DELAY | PCIE.PIPERX0DATA9 |
| TCELL44:IMUX.IMUX37.DELAY | PCIE.PIPERX0DATA8 |
| TCELL44:IMUX.IMUX38.DELAY | PCIE.PIPERX0STATUS1 |
| TCELL44:IMUX.IMUX39.DELAY | PCIE.PIPERX0STATUS0 |
| TCELL44:OUT0.TMIN | PCIE.TRNRD55 |
| TCELL44:OUT1.TMIN | PCIE.TRNRD56 |
| TCELL44:OUT2.TMIN | PCIE.TRNRD57 |
| TCELL44:OUT3.TMIN | PCIE.TRNRD58 |
| TCELL44:OUT4.TMIN | PCIE.TRNRDLLPDATA28 |
| TCELL44:OUT5.TMIN | PCIE.TRNRDLLPDATA29 |
| TCELL44:OUT6.TMIN | PCIE.TRNRDLLPDATA30 |
| TCELL44:OUT7.TMIN | PCIE.TRNRDLLPDATA31 |
| TCELL44:OUT8.TMIN | PCIE.CFGMSGRECEIVEDSETSLOTPOWERLIMIT |
| TCELL44:OUT9.TMIN | PCIE.CFGMSGRECEIVEDUNLOCK |
| TCELL44:OUT10.TMIN | PCIE.CFGMSGRECEIVEDPMASNAK |
| TCELL44:OUT11.TMIN | PCIE.CFGPCIELINKSTATE0 |
| TCELL44:OUT12.TMIN | PCIE.CFGLINKSTATUSDLLACTIVE |
| TCELL44:OUT13.TMIN | PCIE.CFGLINKSTATUSBANDWIDTHSTATUS |
| TCELL44:OUT14.TMIN | PCIE.CFGLINKSTATUSAUTOBANDWIDTHSTATUS |
| TCELL44:OUT15.TMIN | PCIE.CFGLINKCONTROLASPMCONTROL0 |
| TCELL44:OUT16.TMIN | PCIE.CFGROOTCONTROLPMEINTEN |
| TCELL44:OUT17.TMIN | PCIE.CFGAERECRCCHECKEN |
| TCELL44:OUT18.TMIN | PCIE.CFGAERECRCGENEN |
| TCELL44:OUT19.TMIN | PCIE.CFGAERROOTERRCORRERRREPORTINGEN |
| TCELL44:OUT20.TMIN | PCIE.DRPDO7 |
| TCELL44:OUT21.TMIN | PCIE.DRPDO8 |
| TCELL44:OUT22.TMIN | PCIE.DRPDO9 |
| TCELL44:OUT23.TMIN | PCIE.DRPDO10 |
| TCELL45:IMUX.IMUX0.DELAY | PCIE.TRNTDLLPDATA19 |
| TCELL45:IMUX.IMUX1.DELAY | PCIE.TRNTDLLPDATA20 |
| TCELL45:IMUX.IMUX2.DELAY | PCIE.TRNTDLLPDATA21 |
| TCELL45:IMUX.IMUX3.DELAY | PCIE.TRNTDLLPDATA22 |
| TCELL45:IMUX.IMUX4.DELAY | PCIE.CFGERRTLPCPLHEADER26 |
| TCELL45:IMUX.IMUX5.DELAY | PCIE.CFGERRTLPCPLHEADER27 |
| TCELL45:IMUX.IMUX6.DELAY | PCIE.CFGERRTLPCPLHEADER28 |
| TCELL45:IMUX.IMUX7.DELAY | PCIE.CFGERRTLPCPLHEADER29 |
| TCELL45:IMUX.IMUX8.DELAY | PCIE.CFGDSN57 |
| TCELL45:IMUX.IMUX9.DELAY | PCIE.CFGDSN58 |
| TCELL45:IMUX.IMUX10.DELAY | PCIE.CFGDSN59 |
| TCELL45:IMUX.IMUX11.DELAY | PCIE.CFGDSN60 |
| TCELL45:IMUX.IMUX12.DELAY | PCIE.DRPADDR7 |
| TCELL45:IMUX.IMUX13.DELAY | PCIE.DRPADDR8 |
| TCELL45:IMUX.IMUX33.DELAY | PCIE.PIPERX0CHANISALIGNED |
| TCELL45:IMUX.IMUX34.DELAY | PCIE.PIPERX0DATA7 |
| TCELL45:IMUX.IMUX35.DELAY | PCIE.PIPERX0DATA6 |
| TCELL45:IMUX.IMUX36.DELAY | PCIE.PIPERX0VALID |
| TCELL45:IMUX.IMUX37.DELAY | PCIE.PIPERX0PHYSTATUS |
| TCELL45:IMUX.IMUX38.DELAY | PCIE.PIPERX0DATA5 |
| TCELL45:IMUX.IMUX39.DELAY | PCIE.PIPERX0DATA4 |
| TCELL45:OUT0.TMIN | PCIE.TRNRD59 |
| TCELL45:OUT1.TMIN | PCIE.TRNRD60 |
| TCELL45:OUT2.TMIN | PCIE.TRNRD61 |
| TCELL45:OUT3.TMIN | PCIE.TRNRD62 |
| TCELL45:OUT4.TMIN | PCIE.TRNRDLLPDATA32 |
| TCELL45:OUT5.TMIN | PCIE.TRNRDLLPDATA33 |
| TCELL45:OUT6.TMIN | PCIE.PIPETXMARGIN2 |
| TCELL45:OUT7.TMIN | PCIE.TRNRDLLPDATA34 |
| TCELL45:OUT8.TMIN | PCIE.TRNRDLLPDATA35 |
| TCELL45:OUT9.TMIN | PCIE.CFGPCIELINKSTATE1 |
| TCELL45:OUT10.TMIN | PCIE.CFGPCIELINKSTATE2 |
| TCELL45:OUT11.TMIN | PCIE.CFGPMRCVASREQL1N |
| TCELL45:OUT12.TMIN | PCIE.CFGPMRCVENTERL1N |
| TCELL45:OUT13.TMIN | PCIE.CFGLINKCONTROLASPMCONTROL1 |
| TCELL45:OUT14.TMIN | PCIE.CFGLINKCONTROLRCB |
| TCELL45:OUT15.TMIN | PCIE.CFGLINKCONTROLLINKDISABLE |
| TCELL45:OUT16.TMIN | PCIE.PIPETXMARGIN1 |
| TCELL45:OUT17.TMIN | PCIE.CFGLINKCONTROLRETRAINLINK |
| TCELL45:OUT18.TMIN | PCIE.PIPETXMARGIN0 |
| TCELL45:OUT19.TMIN | PCIE.CFGAERROOTERRNONFATALERRREPORTINGEN |
| TCELL45:OUT20.TMIN | PCIE.CFGAERROOTERRFATALERRREPORTINGEN |
| TCELL45:OUT21.TMIN | PCIE.CFGAERROOTERRCORRERRRECEIVED |
| TCELL45:OUT22.TMIN | PCIE.CFGAERROOTERRNONFATALERRRECEIVED |
| TCELL45:OUT23.TMIN | PCIE.PLDBGVEC8 |
| TCELL46:IMUX.IMUX0.DELAY | PCIE.TRNTDLLPDATA23 |
| TCELL46:IMUX.IMUX1.DELAY | PCIE.TRNTDLLPDATA24 |
| TCELL46:IMUX.IMUX2.DELAY | PCIE.TRNTDLLPDATA25 |
| TCELL46:IMUX.IMUX3.DELAY | PCIE.TRNTDLLPDATA26 |
| TCELL46:IMUX.IMUX4.DELAY | PCIE.CFGERRTLPCPLHEADER30 |
| TCELL46:IMUX.IMUX5.DELAY | PCIE.CFGERRTLPCPLHEADER31 |
| TCELL46:IMUX.IMUX6.DELAY | PCIE.CFGERRTLPCPLHEADER32 |
| TCELL46:IMUX.IMUX7.DELAY | PCIE.CFGERRTLPCPLHEADER33 |
| TCELL46:IMUX.IMUX8.DELAY | PCIE.CFGDSN61 |
| TCELL46:IMUX.IMUX9.DELAY | PCIE.CFGDSN62 |
| TCELL46:IMUX.IMUX10.DELAY | PCIE.CFGDSN63 |
| TCELL46:IMUX.IMUX11.DELAY | PCIE.CFGDEVID0 |
| TCELL46:IMUX.IMUX12.DELAY | PCIE.DRPDI0 |
| TCELL46:IMUX.IMUX13.DELAY | PCIE.DRPDI1 |
| TCELL46:IMUX.IMUX14.DELAY | PCIE.DRPDI2 |
| TCELL46:IMUX.IMUX15.DELAY | PCIE.DRPDI3 |
| TCELL46:IMUX.IMUX16.DELAY | PCIE.PIPERX0CHARISK0 |
| TCELL46:IMUX.IMUX32.DELAY | PCIE.PIPERX0DATA3 |
| TCELL46:IMUX.IMUX33.DELAY | PCIE.PIPERX0DATA2 |
| TCELL46:IMUX.IMUX36.DELAY | PCIE.PIPERX0DATA1 |
| TCELL46:IMUX.IMUX37.DELAY | PCIE.PIPERX0DATA0 |
| TCELL46:OUT0.TMIN | PCIE.TRNRD63 |
| TCELL46:OUT1.TMIN | PCIE.TRNRD64 |
| TCELL46:OUT2.TMIN | PCIE.TRNRD65 |
| TCELL46:OUT3.TMIN | PCIE.TRNRD66 |
| TCELL46:OUT4.TMIN | PCIE.TRNRDLLPDATA36 |
| TCELL46:OUT5.TMIN | PCIE.TRNRDLLPDATA37 |
| TCELL46:OUT6.TMIN | PCIE.TRNRDLLPDATA38 |
| TCELL46:OUT7.TMIN | PCIE.TRNRDLLPDATA39 |
| TCELL46:OUT8.TMIN | PCIE.CFGPMRCVENTERL23N |
| TCELL46:OUT9.TMIN | PCIE.CFGPMRCVREQACKN |
| TCELL46:OUT10.TMIN | PCIE.CFGPMCSRPOWERSTATE0 |
| TCELL46:OUT11.TMIN | PCIE.CFGPMCSRPOWERSTATE1 |
| TCELL46:OUT12.TMIN | PCIE.CFGLINKCONTROLCOMMONCLOCK |
| TCELL46:OUT13.TMIN | PCIE.CFGLINKCONTROLEXTENDEDSYNC |
| TCELL46:OUT14.TMIN | PCIE.CFGLINKCONTROLCLOCKPMEN |
| TCELL46:OUT15.TMIN | PCIE.CFGLINKCONTROLHWAUTOWIDTHDIS |
| TCELL46:OUT16.TMIN | PCIE.CFGAERROOTERRFATALERRRECEIVED |
| TCELL46:OUT17.TMIN | PCIE.CFGVCTCVCMAP0 |
| TCELL46:OUT18.TMIN | PCIE.CFGVCTCVCMAP1 |
| TCELL46:OUT19.TMIN | PCIE.CFGVCTCVCMAP2 |
| TCELL46:OUT20.TMIN | PCIE.DRPDO11 |
| TCELL46:OUT21.TMIN | PCIE.DRPDO12 |
| TCELL46:OUT22.TMIN | PCIE.DRPDO13 |
| TCELL46:OUT23.TMIN | PCIE.DRPDO14 |
| TCELL47:IMUX.IMUX0.DELAY | PCIE.TRNTDLLPDATA27 |
| TCELL47:IMUX.IMUX1.DELAY | PCIE.TRNTDLLPDATA28 |
| TCELL47:IMUX.IMUX2.DELAY | PCIE.TRNTDLLPDATA29 |
| TCELL47:IMUX.IMUX3.DELAY | PCIE.TRNTDLLPDATA30 |
| TCELL47:IMUX.IMUX4.DELAY | PCIE.CFGERRTLPCPLHEADER34 |
| TCELL47:IMUX.IMUX5.DELAY | PCIE.CFGERRTLPCPLHEADER35 |
| TCELL47:IMUX.IMUX6.DELAY | PCIE.CFGERRTLPCPLHEADER36 |
| TCELL47:IMUX.IMUX7.DELAY | PCIE.CFGERRTLPCPLHEADER37 |
| TCELL47:IMUX.IMUX8.DELAY | PCIE.CFGDEVID1 |
| TCELL47:IMUX.IMUX9.DELAY | PCIE.CFGDEVID2 |
| TCELL47:IMUX.IMUX10.DELAY | PCIE.CFGDEVID3 |
| TCELL47:IMUX.IMUX11.DELAY | PCIE.CFGDEVID4 |
| TCELL47:IMUX.IMUX12.DELAY | PCIE.DRPDI4 |
| TCELL47:IMUX.IMUX13.DELAY | PCIE.DRPDI5 |
| TCELL47:IMUX.IMUX14.DELAY | PCIE.DRPDI6 |
| TCELL47:IMUX.IMUX15.DELAY | PCIE.DRPDI7 |
| TCELL47:OUT0.TMIN | PCIE.TRNRD67 |
| TCELL47:OUT1.TMIN | PCIE.TRNRD68 |
| TCELL47:OUT2.TMIN | PCIE.TRNRD69 |
| TCELL47:OUT3.TMIN | PCIE.TRNRD70 |
| TCELL47:OUT4.TMIN | PCIE.TRNRDLLPDATA40 |
| TCELL47:OUT5.TMIN | PCIE.TRNRDLLPDATA41 |
| TCELL47:OUT6.TMIN | PCIE.TRNRDLLPDATA42 |
| TCELL47:OUT7.TMIN | PCIE.TRNRDLLPDATA43 |
| TCELL47:OUT8.TMIN | PCIE.CFGPMCSRPMEEN |
| TCELL47:OUT9.TMIN | PCIE.CFGPMCSRPMESTATUS |
| TCELL47:OUT10.TMIN | PCIE.CFGTRANSACTION |
| TCELL47:OUT11.TMIN | PCIE.CFGTRANSACTIONTYPE |
| TCELL47:OUT12.TMIN | PCIE.CFGLINKCONTROLBANDWIDTHINTEN |
| TCELL47:OUT13.TMIN | PCIE.CFGLINKCONTROLAUTOBANDWIDTHINTEN |
| TCELL47:OUT14.TMIN | PCIE.CFGDEVCONTROL2CPLTIMEOUTVAL0 |
| TCELL47:OUT15.TMIN | PCIE.CFGDEVCONTROL2CPLTIMEOUTVAL1 |
| TCELL47:OUT16.TMIN | PCIE.CFGVCTCVCMAP3 |
| TCELL47:OUT17.TMIN | PCIE.CFGVCTCVCMAP4 |
| TCELL47:OUT18.TMIN | PCIE.CFGVCTCVCMAP5 |
| TCELL47:OUT19.TMIN | PCIE.CFGVCTCVCMAP6 |
| TCELL47:OUT20.TMIN | PCIE.DRPDO15 |
| TCELL47:OUT21.TMIN | PCIE.DBGVECA0 |
| TCELL47:OUT22.TMIN | PCIE.DBGVECA1 |
| TCELL47:OUT23.TMIN | PCIE.DBGVECA2 |
| TCELL48:IMUX.IMUX0.DELAY | PCIE.TRNTDLLPDATA31 |
| TCELL48:IMUX.IMUX1.DELAY | PCIE.TRNTDLLPSRCRDY |
| TCELL48:IMUX.IMUX2.DELAY | PCIE.LL2TLPRCV |
| TCELL48:IMUX.IMUX3.DELAY | PCIE.LL2SENDENTERL1 |
| TCELL48:IMUX.IMUX4.DELAY | PCIE.CFGERRTLPCPLHEADER38 |
| TCELL48:IMUX.IMUX5.DELAY | PCIE.CFGERRTLPCPLHEADER39 |
| TCELL48:IMUX.IMUX6.DELAY | PCIE.CFGERRTLPCPLHEADER40 |
| TCELL48:IMUX.IMUX7.DELAY | PCIE.CFGERRTLPCPLHEADER41 |
| TCELL48:IMUX.IMUX8.DELAY | PCIE.CFGDEVID5 |
| TCELL48:IMUX.IMUX9.DELAY | PCIE.CFGDEVID6 |
| TCELL48:IMUX.IMUX10.DELAY | PCIE.CFGDEVID7 |
| TCELL48:IMUX.IMUX11.DELAY | PCIE.CFGDEVID8 |
| TCELL48:IMUX.IMUX12.DELAY | PCIE.DRPDI8 |
| TCELL48:IMUX.IMUX13.DELAY | PCIE.DRPDI9 |
| TCELL48:IMUX.IMUX14.DELAY | PCIE.DRPDI10 |
| TCELL48:IMUX.IMUX15.DELAY | PCIE.DRPDI11 |
| TCELL48:OUT0.TMIN | PCIE.TRNRD71 |
| TCELL48:OUT1.TMIN | PCIE.TRNRD72 |
| TCELL48:OUT2.TMIN | PCIE.TRNRD73 |
| TCELL48:OUT3.TMIN | PCIE.TRNRD74 |
| TCELL48:OUT4.TMIN | PCIE.TRNRDLLPDATA44 |
| TCELL48:OUT5.TMIN | PCIE.TRNRDLLPDATA45 |
| TCELL48:OUT6.TMIN | PCIE.TRNRDLLPDATA46 |
| TCELL48:OUT7.TMIN | PCIE.TRNRDLLPDATA47 |
| TCELL48:OUT8.TMIN | PCIE.CFGTRANSACTIONADDR0 |
| TCELL48:OUT9.TMIN | PCIE.CFGTRANSACTIONADDR1 |
| TCELL48:OUT10.TMIN | PCIE.CFGTRANSACTIONADDR2 |
| TCELL48:OUT11.TMIN | PCIE.CFGTRANSACTIONADDR3 |
| TCELL48:OUT12.TMIN | PCIE.CFGDEVCONTROL2CPLTIMEOUTVAL2 |
| TCELL48:OUT13.TMIN | PCIE.CFGDEVCONTROL2CPLTIMEOUTVAL3 |
| TCELL48:OUT14.TMIN | PCIE.CFGDEVCONTROL2CPLTIMEOUTDIS |
| TCELL48:OUT15.TMIN | PCIE.CFGDEVCONTROL2ARIFORWARDEN |
| TCELL48:OUT16.TMIN | PCIE.DRPRDY |
| TCELL48:OUT17.TMIN | PCIE.DRPDO0 |
| TCELL48:OUT18.TMIN | PCIE.DRPDO1 |
| TCELL48:OUT19.TMIN | PCIE.DRPDO2 |
| TCELL48:OUT20.TMIN | PCIE.DBGVECA3 |
| TCELL48:OUT21.TMIN | PCIE.DBGVECA4 |
| TCELL48:OUT22.TMIN | PCIE.DBGVECA5 |
| TCELL48:OUT23.TMIN | PCIE.DBGVECA6 |
| TCELL49:IMUX.IMUX0.DELAY | PCIE.LL2SENDENTERL23 |
| TCELL49:IMUX.IMUX1.DELAY | PCIE.LL2SENDASREQL1 |
| TCELL49:IMUX.IMUX2.DELAY | PCIE.LL2SENDPMACK |
| TCELL49:IMUX.IMUX3.DELAY | PCIE.PL2DIRECTEDLSTATE0 |
| TCELL49:IMUX.IMUX4.DELAY | PCIE.CFGERRTLPCPLHEADER42 |
| TCELL49:IMUX.IMUX5.DELAY | PCIE.CFGERRTLPCPLHEADER43 |
| TCELL49:IMUX.IMUX6.DELAY | PCIE.CFGERRTLPCPLHEADER44 |
| TCELL49:IMUX.IMUX7.DELAY | PCIE.CFGERRTLPCPLHEADER45 |
| TCELL49:IMUX.IMUX8.DELAY | PCIE.CFGDEVID9 |
| TCELL49:IMUX.IMUX9.DELAY | PCIE.CFGDEVID10 |
| TCELL49:IMUX.IMUX10.DELAY | PCIE.CFGDEVID11 |
| TCELL49:IMUX.IMUX11.DELAY | PCIE.CFGDEVID12 |
| TCELL49:IMUX.IMUX12.DELAY | PCIE.DRPDI12 |
| TCELL49:IMUX.IMUX13.DELAY | PCIE.DRPDI13 |
| TCELL49:IMUX.IMUX14.DELAY | PCIE.DRPDI14 |
| TCELL49:IMUX.IMUX15.DELAY | PCIE.DRPDI15 |
| TCELL49:OUT0.TMIN | PCIE.TRNRD75 |
| TCELL49:OUT1.TMIN | PCIE.TRNRD76 |
| TCELL49:OUT2.TMIN | PCIE.TRNRD77 |
| TCELL49:OUT3.TMIN | PCIE.TRNRD78 |
| TCELL49:OUT4.TMIN | PCIE.TRNRDLLPDATA48 |
| TCELL49:OUT5.TMIN | PCIE.TRNRDLLPDATA49 |
| TCELL49:OUT6.TMIN | PCIE.TRNRDLLPDATA50 |
| TCELL49:OUT7.TMIN | PCIE.TRNRDLLPDATA51 |
| TCELL49:OUT8.TMIN | PCIE.CFGTRANSACTIONADDR4 |
| TCELL49:OUT9.TMIN | PCIE.CFGTRANSACTIONADDR5 |
| TCELL49:OUT10.TMIN | PCIE.CFGTRANSACTIONADDR6 |
| TCELL49:OUT11.TMIN | PCIE.CFGCOMMANDIOENABLE |
| TCELL49:OUT12.TMIN | PCIE.CFGDEVCONTROL2ATOMICREQUESTEREN |
| TCELL49:OUT13.TMIN | PCIE.CFGDEVCONTROL2ATOMICEGRESSBLOCK |
| TCELL49:OUT14.TMIN | PCIE.CFGDEVCONTROL2IDOREQEN |
| TCELL49:OUT15.TMIN | PCIE.CFGDEVCONTROL2IDOCPLEN |
| TCELL49:OUT16.TMIN | PCIE.DRPDO3 |
| TCELL49:OUT17.TMIN | PCIE.DRPDO4 |
| TCELL49:OUT18.TMIN | PCIE.DRPDO5 |
| TCELL49:OUT19.TMIN | PCIE.DRPDO6 |
| TCELL49:OUT20.TMIN | PCIE.DBGVECA7 |
| TCELL49:OUT21.TMIN | PCIE.DBGVECA8 |
| TCELL49:OUT22.TMIN | PCIE.DBGVECA9 |
| TCELL49:OUT23.TMIN | PCIE.DBGVECA10 |
Bitstream
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[14] PCIE:DRP05[14] | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[15] PCIE:DRP05[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[12] PCIE:DRP05[12] | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[13] PCIE:DRP05[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[10] PCIE:DRP05[10] | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[11] PCIE:DRP05[11] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[8] PCIE:DRP05[8] | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[9] PCIE:DRP05[9] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[6] PCIE:DRP05[6] | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[7] PCIE:DRP05[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[4] PCIE:DRP05[4] | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[5] PCIE:DRP05[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[2] PCIE:DRP05[2] | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[3] PCIE:DRP05[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[0] PCIE:DRP05[0] | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[1] PCIE:DRP05[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP04[14] | PCIE:DRP04[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ON PCIE:DRP04[12] | PCIE:DRP04[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_NEXTPTR[10] PCIE:DRP04[10] | PCIE:AER_CAP_NEXTPTR[11] PCIE:DRP04[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_NEXTPTR[8] PCIE:DRP04[8] | PCIE:AER_CAP_NEXTPTR[9] PCIE:DRP04[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_NEXTPTR[6] PCIE:DRP04[6] | PCIE:AER_CAP_NEXTPTR[7] PCIE:DRP04[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_NEXTPTR[4] PCIE:DRP04[4] | PCIE:AER_CAP_NEXTPTR[5] PCIE:DRP04[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_NEXTPTR[2] PCIE:DRP04[2] | PCIE:AER_CAP_NEXTPTR[3] PCIE:DRP04[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_NEXTPTR[0] PCIE:DRP04[0] | PCIE:AER_CAP_NEXTPTR[1] PCIE:DRP04[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP03[14] | PCIE:DRP03[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP03[12] | PCIE:DRP03[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_BASE_PTR[10] PCIE:DRP03[10] | PCIE:AER_BASE_PTR[11] PCIE:DRP03[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_BASE_PTR[8] PCIE:DRP03[8] | PCIE:AER_BASE_PTR[9] PCIE:DRP03[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_BASE_PTR[6] PCIE:DRP03[6] | PCIE:AER_BASE_PTR[7] PCIE:DRP03[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_BASE_PTR[4] PCIE:DRP03[4] | PCIE:AER_BASE_PTR[5] PCIE:DRP03[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_BASE_PTR[2] PCIE:DRP03[2] | PCIE:AER_BASE_PTR[3] PCIE:DRP03[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_BASE_PTR[0] PCIE:DRP03[0] | PCIE:AER_BASE_PTR[1] PCIE:DRP03[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP02[14] | PCIE:DRP02[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP02[12] | PCIE:DRP02[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP02[10] | PCIE:DRP02[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP02[8] | PCIE:DRP02[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP02[6] | PCIE:DRP02[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_VERSION[3] PCIE:DRP02[4] | PCIE:DRP02[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_VERSION[1] PCIE:DRP02[2] | PCIE:AER_CAP_VERSION[2] PCIE:DRP02[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_PERMIT_ROOTERR_UPDATE PCIE:DRP02[0] | PCIE:AER_CAP_VERSION[0] PCIE:DRP02[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ID[14] PCIE:DRP01[14] | PCIE:AER_CAP_ID[15] PCIE:DRP01[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ID[12] PCIE:DRP01[12] | PCIE:AER_CAP_ID[13] PCIE:DRP01[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ID[10] PCIE:DRP01[10] | PCIE:AER_CAP_ID[11] PCIE:DRP01[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ID[8] PCIE:DRP01[8] | PCIE:AER_CAP_ID[9] PCIE:DRP01[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ID[6] PCIE:DRP01[6] | PCIE:AER_CAP_ID[7] PCIE:DRP01[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ID[4] PCIE:DRP01[4] | PCIE:AER_CAP_ID[5] PCIE:DRP01[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ID[2] PCIE:DRP01[2] | PCIE:AER_CAP_ID[3] PCIE:DRP01[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ID[0] PCIE:DRP01[0] | PCIE:AER_CAP_ID[1] PCIE:DRP01[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP00[14] | PCIE:DRP00[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP00[12] | PCIE:DRP00[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP00[10] | PCIE:DRP00[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP00[8] | PCIE:DRP00[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP00[6] | PCIE:DRP00[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP00[4] | PCIE:DRP00[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP00[2] | PCIE:DRP00[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_ECRC_CHECK_CAPABLE PCIE:DRP00[0] | PCIE:AER_CAP_ECRC_GEN_CAPABLE PCIE:DRP00[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[14] PCIE:DRP0B[14] | PCIE:BAR2[15] PCIE:DRP0B[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[12] PCIE:DRP0B[12] | PCIE:BAR2[13] PCIE:DRP0B[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[10] PCIE:DRP0B[10] | PCIE:BAR2[11] PCIE:DRP0B[11] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[8] PCIE:DRP0B[8] | PCIE:BAR2[9] PCIE:DRP0B[9] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[6] PCIE:DRP0B[6] | PCIE:BAR2[7] PCIE:DRP0B[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[4] PCIE:DRP0B[4] | PCIE:BAR2[5] PCIE:DRP0B[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[2] PCIE:DRP0B[2] | PCIE:BAR2[3] PCIE:DRP0B[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[0] PCIE:DRP0B[0] | PCIE:BAR2[1] PCIE:DRP0B[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[30] PCIE:DRP0A[14] | PCIE:BAR1[31] PCIE:DRP0A[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[28] PCIE:DRP0A[12] | PCIE:BAR1[29] PCIE:DRP0A[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[26] PCIE:DRP0A[10] | PCIE:BAR1[27] PCIE:DRP0A[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[24] PCIE:DRP0A[8] | PCIE:BAR1[25] PCIE:DRP0A[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[22] PCIE:DRP0A[6] | PCIE:BAR1[23] PCIE:DRP0A[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[20] PCIE:DRP0A[4] | PCIE:BAR1[21] PCIE:DRP0A[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[18] PCIE:DRP0A[2] | PCIE:BAR1[19] PCIE:DRP0A[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[16] PCIE:DRP0A[0] | PCIE:BAR1[17] PCIE:DRP0A[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[14] PCIE:DRP09[14] | PCIE:BAR1[15] PCIE:DRP09[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[12] PCIE:DRP09[12] | PCIE:BAR1[13] PCIE:DRP09[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[10] PCIE:DRP09[10] | PCIE:BAR1[11] PCIE:DRP09[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[8] PCIE:DRP09[8] | PCIE:BAR1[9] PCIE:DRP09[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[6] PCIE:DRP09[6] | PCIE:BAR1[7] PCIE:DRP09[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[4] PCIE:DRP09[4] | PCIE:BAR1[5] PCIE:DRP09[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[2] PCIE:DRP09[2] | PCIE:BAR1[3] PCIE:DRP09[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR1[0] PCIE:DRP09[0] | PCIE:BAR1[1] PCIE:DRP09[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[30] PCIE:DRP08[14] | PCIE:BAR0[31] PCIE:DRP08[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[28] PCIE:DRP08[12] | PCIE:BAR0[29] PCIE:DRP08[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[26] PCIE:DRP08[10] | PCIE:BAR0[27] PCIE:DRP08[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[24] PCIE:DRP08[8] | PCIE:BAR0[25] PCIE:DRP08[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[22] PCIE:DRP08[6] | PCIE:BAR0[23] PCIE:DRP08[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[20] PCIE:DRP08[4] | PCIE:BAR0[21] PCIE:DRP08[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[18] PCIE:DRP08[2] | PCIE:BAR0[19] PCIE:DRP08[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[16] PCIE:DRP08[0] | PCIE:BAR0[17] PCIE:DRP08[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[14] PCIE:DRP07[14] | PCIE:BAR0[15] PCIE:DRP07[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[12] PCIE:DRP07[12] | PCIE:BAR0[13] PCIE:DRP07[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[10] PCIE:DRP07[10] | PCIE:BAR0[11] PCIE:DRP07[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[8] PCIE:DRP07[8] | PCIE:BAR0[9] PCIE:DRP07[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[6] PCIE:DRP07[6] | PCIE:BAR0[7] PCIE:DRP07[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[4] PCIE:DRP07[4] | PCIE:BAR0[5] PCIE:DRP07[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[2] PCIE:DRP07[2] | PCIE:BAR0[3] PCIE:DRP07[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR0[0] PCIE:DRP07[0] | PCIE:BAR0[1] PCIE:DRP07[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP06[14] | PCIE:DRP06[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP06[12] | PCIE:DRP06[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP06[10] | PCIE:DRP06[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_MULTIHEADER PCIE:DRP06[8] | PCIE:DRP06[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[22] PCIE:DRP06[6] | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[23] PCIE:DRP06[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[20] PCIE:DRP06[4] | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[21] PCIE:DRP06[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[18] PCIE:DRP06[2] | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[19] PCIE:DRP06[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[16] PCIE:DRP06[0] | PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT[17] PCIE:DRP06[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[14] PCIE:DRP11[14] | PCIE:BAR5[15] PCIE:DRP11[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[12] PCIE:DRP11[12] | PCIE:BAR5[13] PCIE:DRP11[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[10] PCIE:DRP11[10] | PCIE:BAR5[11] PCIE:DRP11[11] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[8] PCIE:DRP11[8] | PCIE:BAR5[9] PCIE:DRP11[9] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[6] PCIE:DRP11[6] | PCIE:BAR5[7] PCIE:DRP11[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[4] PCIE:DRP11[4] | PCIE:BAR5[5] PCIE:DRP11[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[2] PCIE:DRP11[2] | PCIE:BAR5[3] PCIE:DRP11[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR5[0] PCIE:DRP11[0] | PCIE:BAR5[1] PCIE:DRP11[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[30] PCIE:DRP10[14] | PCIE:BAR4[31] PCIE:DRP10[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[28] PCIE:DRP10[12] | PCIE:BAR4[29] PCIE:DRP10[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[26] PCIE:DRP10[10] | PCIE:BAR4[27] PCIE:DRP10[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[24] PCIE:DRP10[8] | PCIE:BAR4[25] PCIE:DRP10[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[22] PCIE:DRP10[6] | PCIE:BAR4[23] PCIE:DRP10[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[20] PCIE:DRP10[4] | PCIE:BAR4[21] PCIE:DRP10[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[18] PCIE:DRP10[2] | PCIE:BAR4[19] PCIE:DRP10[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[16] PCIE:DRP10[0] | PCIE:BAR4[17] PCIE:DRP10[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[14] PCIE:DRP0F[14] | PCIE:BAR4[15] PCIE:DRP0F[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[12] PCIE:DRP0F[12] | PCIE:BAR4[13] PCIE:DRP0F[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[10] PCIE:DRP0F[10] | PCIE:BAR4[11] PCIE:DRP0F[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[8] PCIE:DRP0F[8] | PCIE:BAR4[9] PCIE:DRP0F[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[6] PCIE:DRP0F[6] | PCIE:BAR4[7] PCIE:DRP0F[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[4] PCIE:DRP0F[4] | PCIE:BAR4[5] PCIE:DRP0F[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[2] PCIE:DRP0F[2] | PCIE:BAR4[3] PCIE:DRP0F[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR4[0] PCIE:DRP0F[0] | PCIE:BAR4[1] PCIE:DRP0F[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[30] PCIE:DRP0E[14] | PCIE:BAR3[31] PCIE:DRP0E[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[28] PCIE:DRP0E[12] | PCIE:BAR3[29] PCIE:DRP0E[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[26] PCIE:DRP0E[10] | PCIE:BAR3[27] PCIE:DRP0E[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[24] PCIE:DRP0E[8] | PCIE:BAR3[25] PCIE:DRP0E[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[22] PCIE:DRP0E[6] | PCIE:BAR3[23] PCIE:DRP0E[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[20] PCIE:DRP0E[4] | PCIE:BAR3[21] PCIE:DRP0E[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[18] PCIE:DRP0E[2] | PCIE:BAR3[19] PCIE:DRP0E[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[16] PCIE:DRP0E[0] | PCIE:BAR3[17] PCIE:DRP0E[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[14] PCIE:DRP0D[14] | PCIE:BAR3[15] PCIE:DRP0D[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[12] PCIE:DRP0D[12] | PCIE:BAR3[13] PCIE:DRP0D[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[10] PCIE:DRP0D[10] | PCIE:BAR3[11] PCIE:DRP0D[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[8] PCIE:DRP0D[8] | PCIE:BAR3[9] PCIE:DRP0D[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[6] PCIE:DRP0D[6] | PCIE:BAR3[7] PCIE:DRP0D[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[4] PCIE:DRP0D[4] | PCIE:BAR3[5] PCIE:DRP0D[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[2] PCIE:DRP0D[2] | PCIE:BAR3[3] PCIE:DRP0D[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR3[0] PCIE:DRP0D[0] | PCIE:BAR3[1] PCIE:DRP0D[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[30] PCIE:DRP0C[14] | PCIE:BAR2[31] PCIE:DRP0C[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[28] PCIE:DRP0C[12] | PCIE:BAR2[29] PCIE:DRP0C[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[26] PCIE:DRP0C[10] | PCIE:BAR2[27] PCIE:DRP0C[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[24] PCIE:DRP0C[8] | PCIE:BAR2[25] PCIE:DRP0C[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[22] PCIE:DRP0C[6] | PCIE:BAR2[23] PCIE:DRP0C[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[20] PCIE:DRP0C[4] | PCIE:BAR2[21] PCIE:DRP0C[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[18] PCIE:DRP0C[2] | PCIE:BAR2[19] PCIE:DRP0C[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:BAR2[16] PCIE:DRP0C[0] | PCIE:BAR2[17] PCIE:DRP0C[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP23[14] PCIE:LINK_CAP_CLOCK_POWER_MANAGEMENT | PCIE:DRP23[15] PCIE:LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP23[12] PCIE:LINK_CAP_ASPM_SUPPORT[0] | PCIE:DRP23[13] PCIE:LINK_CAP_ASPM_SUPPORT[1] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP23[10] PCIE:LAST_CONFIG_DWORD[8] | PCIE:DRP23[11] PCIE:LAST_CONFIG_DWORD[9] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP23[8] PCIE:LAST_CONFIG_DWORD[6] | PCIE:DRP23[9] PCIE:LAST_CONFIG_DWORD[7] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP23[6] PCIE:LAST_CONFIG_DWORD[4] | PCIE:DRP23[7] PCIE:LAST_CONFIG_DWORD[5] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP23[4] PCIE:LAST_CONFIG_DWORD[2] | PCIE:DRP23[5] PCIE:LAST_CONFIG_DWORD[3] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP23[2] PCIE:LAST_CONFIG_DWORD[0] | PCIE:DRP23[3] PCIE:LAST_CONFIG_DWORD[1] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP23[0] PCIE:INTERRUPT_STAT_AUTO | PCIE:DRP23[1] PCIE:IS_SWITCH |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP22[14] PCIE:INTERRUPT_PIN[6] | PCIE:DRP22[15] PCIE:INTERRUPT_PIN[7] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP22[12] PCIE:INTERRUPT_PIN[4] | PCIE:DRP22[13] PCIE:INTERRUPT_PIN[5] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP22[10] PCIE:INTERRUPT_PIN[2] | PCIE:DRP22[11] PCIE:INTERRUPT_PIN[3] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP22[8] PCIE:INTERRUPT_PIN[0] | PCIE:DRP22[9] PCIE:INTERRUPT_PIN[1] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP22[6] PCIE:HEADER_TYPE[6] | PCIE:DRP22[7] PCIE:HEADER_TYPE[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP22[4] PCIE:HEADER_TYPE[4] | PCIE:DRP22[5] PCIE:HEADER_TYPE[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP22[2] PCIE:HEADER_TYPE[2] | PCIE:DRP22[3] PCIE:HEADER_TYPE[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP22[0] PCIE:HEADER_TYPE[0] | PCIE:DRP22[1] PCIE:HEADER_TYPE[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP21[14] | PCIE:DRP21[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP21[12] | PCIE:DRP21[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP21[10] | PCIE:DRP21[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP21[8] PCIE:EXT_CFG_XP_CAP_PTR[8] | PCIE:DRP21[9] PCIE:EXT_CFG_XP_CAP_PTR[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP21[6] PCIE:EXT_CFG_XP_CAP_PTR[6] | PCIE:DRP21[7] PCIE:EXT_CFG_XP_CAP_PTR[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP21[4] PCIE:EXT_CFG_XP_CAP_PTR[4] | PCIE:DRP21[5] PCIE:EXT_CFG_XP_CAP_PTR[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP21[2] PCIE:EXT_CFG_XP_CAP_PTR[2] | PCIE:DRP21[3] PCIE:EXT_CFG_XP_CAP_PTR[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP21[0] PCIE:EXT_CFG_XP_CAP_PTR[0] | PCIE:DRP21[1] PCIE:EXT_CFG_XP_CAP_PTR[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP20[14] | PCIE:DRP20[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP20[12] | PCIE:DRP20[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP20[10] | PCIE:DRP20[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP20[8] PCIE:EXT_CFG_CAP_PTR[4] | PCIE:DRP20[9] PCIE:EXT_CFG_CAP_PTR[5] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP20[6] PCIE:EXT_CFG_CAP_PTR[2] | PCIE:DRP20[7] PCIE:EXT_CFG_CAP_PTR[3] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP20[4] PCIE:EXT_CFG_CAP_PTR[0] | PCIE:DRP20[5] PCIE:EXT_CFG_CAP_PTR[1] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP20[2] PCIE:DSN_CAP_VERSION[2] | PCIE:DRP20[3] PCIE:DSN_CAP_VERSION[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP20[0] PCIE:DSN_CAP_VERSION[0] | PCIE:DRP20[1] PCIE:DSN_CAP_VERSION[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP1F[14] | PCIE:DRP1F[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP1F[12] PCIE:DSN_CAP_ON | PCIE:DRP1F[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP1F[10] PCIE:DSN_CAP_NEXTPTR[10] | PCIE:DRP1F[11] PCIE:DSN_CAP_NEXTPTR[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP1F[8] PCIE:DSN_CAP_NEXTPTR[8] | PCIE:DRP1F[9] PCIE:DSN_CAP_NEXTPTR[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP1F[6] PCIE:DSN_CAP_NEXTPTR[6] | PCIE:DRP1F[7] PCIE:DSN_CAP_NEXTPTR[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP1F[4] PCIE:DSN_CAP_NEXTPTR[4] | PCIE:DRP1F[5] PCIE:DSN_CAP_NEXTPTR[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP1F[2] PCIE:DSN_CAP_NEXTPTR[2] | PCIE:DRP1F[3] PCIE:DSN_CAP_NEXTPTR[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP1F[0] PCIE:DSN_CAP_NEXTPTR[0] | PCIE:DRP1F[1] PCIE:DSN_CAP_NEXTPTR[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP1E[14] PCIE:DSN_CAP_ID[14] | PCIE:DRP1E[15] PCIE:DSN_CAP_ID[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP1E[12] PCIE:DSN_CAP_ID[12] | PCIE:DRP1E[13] PCIE:DSN_CAP_ID[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP1E[10] PCIE:DSN_CAP_ID[10] | PCIE:DRP1E[11] PCIE:DSN_CAP_ID[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP1E[8] PCIE:DSN_CAP_ID[8] | PCIE:DRP1E[9] PCIE:DSN_CAP_ID[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP1E[6] PCIE:DSN_CAP_ID[6] | PCIE:DRP1E[7] PCIE:DSN_CAP_ID[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP1E[4] PCIE:DSN_CAP_ID[4] | PCIE:DRP1E[5] PCIE:DSN_CAP_ID[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP1E[2] PCIE:DSN_CAP_ID[2] | PCIE:DRP1E[3] PCIE:DSN_CAP_ID[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP1E[0] PCIE:DSN_CAP_ID[0] | PCIE:DRP1E[1] PCIE:DSN_CAP_ID[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3B[14] | PCIE:DRP3B[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3B[12] | PCIE:DRP3B[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3B[10] | PCIE:DRP3B[11] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3B[8] | PCIE:DRP3B[9] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3B[6] PCIE:PM_DATA7[6] | PCIE:DRP3B[7] PCIE:PM_DATA7[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3B[4] PCIE:PM_DATA7[4] | PCIE:DRP3B[5] PCIE:PM_DATA7[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3B[2] PCIE:PM_DATA7[2] | PCIE:DRP3B[3] PCIE:PM_DATA7[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3B[0] PCIE:PM_DATA7[0] | PCIE:DRP3B[1] PCIE:PM_DATA7[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3A[14] PCIE:PM_DATA6[6] | PCIE:DRP3A[15] PCIE:PM_DATA6[7] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3A[12] PCIE:PM_DATA6[4] | PCIE:DRP3A[13] PCIE:PM_DATA6[5] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3A[10] PCIE:PM_DATA6[2] | PCIE:DRP3A[11] PCIE:PM_DATA6[3] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3A[8] PCIE:PM_DATA6[0] | PCIE:DRP3A[9] PCIE:PM_DATA6[1] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3A[6] PCIE:PM_DATA5[6] | PCIE:DRP3A[7] PCIE:PM_DATA5[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3A[4] PCIE:PM_DATA5[4] | PCIE:DRP3A[5] PCIE:PM_DATA5[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3A[2] PCIE:PM_DATA5[2] | PCIE:DRP3A[3] PCIE:PM_DATA5[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3A[0] PCIE:PM_DATA5[0] | PCIE:DRP3A[1] PCIE:PM_DATA5[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP39[14] PCIE:PM_DATA4[6] | PCIE:DRP39[15] PCIE:PM_DATA4[7] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP39[12] PCIE:PM_DATA4[4] | PCIE:DRP39[13] PCIE:PM_DATA4[5] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP39[10] PCIE:PM_DATA4[2] | PCIE:DRP39[11] PCIE:PM_DATA4[3] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP39[8] PCIE:PM_DATA4[0] | PCIE:DRP39[9] PCIE:PM_DATA4[1] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP39[6] PCIE:PM_DATA3[6] | PCIE:DRP39[7] PCIE:PM_DATA3[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP39[4] PCIE:PM_DATA3[4] | PCIE:DRP39[5] PCIE:PM_DATA3[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP39[2] PCIE:PM_DATA3[2] | PCIE:DRP39[3] PCIE:PM_DATA3[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP39[0] PCIE:PM_DATA3[0] | PCIE:DRP39[1] PCIE:PM_DATA3[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP38[14] PCIE:PM_DATA2[6] | PCIE:DRP38[15] PCIE:PM_DATA2[7] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP38[12] PCIE:PM_DATA2[4] | PCIE:DRP38[13] PCIE:PM_DATA2[5] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP38[10] PCIE:PM_DATA2[2] | PCIE:DRP38[11] PCIE:PM_DATA2[3] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP38[8] PCIE:PM_DATA2[0] | PCIE:DRP38[9] PCIE:PM_DATA2[1] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP38[6] PCIE:PM_DATA1[6] | PCIE:DRP38[7] PCIE:PM_DATA1[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP38[4] PCIE:PM_DATA1[4] | PCIE:DRP38[5] PCIE:PM_DATA1[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP38[2] PCIE:PM_DATA1[2] | PCIE:DRP38[3] PCIE:PM_DATA1[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP38[0] PCIE:PM_DATA1[0] | PCIE:DRP38[1] PCIE:PM_DATA1[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP37[14] | PCIE:DRP37[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP37[12] PCIE:PM_DATA0[6] | PCIE:DRP37[13] PCIE:PM_DATA0[7] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP37[10] PCIE:PM_DATA0[4] | PCIE:DRP37[11] PCIE:PM_DATA0[5] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP37[8] PCIE:PM_DATA0[2] | PCIE:DRP37[9] PCIE:PM_DATA0[3] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP37[6] PCIE:PM_DATA0[0] | PCIE:DRP37[7] PCIE:PM_DATA0[1] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP37[4] PCIE:PM_DATA_SCALE7[0] | PCIE:DRP37[5] PCIE:PM_DATA_SCALE7[1] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP37[2] PCIE:PM_DATA_SCALE6[0] | PCIE:DRP37[3] PCIE:PM_DATA_SCALE6[1] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP37[0] PCIE:PM_DATA_SCALE5[0] | PCIE:DRP37[1] PCIE:PM_DATA_SCALE5[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP36[14] PCIE:PM_DATA_SCALE4[0] | PCIE:DRP36[15] PCIE:PM_DATA_SCALE4[1] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP36[12] PCIE:PM_DATA_SCALE3[0] | PCIE:DRP36[13] PCIE:PM_DATA_SCALE3[1] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP36[10] PCIE:PM_DATA_SCALE2[0] | PCIE:DRP36[11] PCIE:PM_DATA_SCALE2[1] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP36[8] PCIE:PM_DATA_SCALE1[0] | PCIE:DRP36[9] PCIE:PM_DATA_SCALE1[1] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP36[6] PCIE:PM_DATA_SCALE0[0] | PCIE:DRP36[7] PCIE:PM_DATA_SCALE0[1] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP36[4] PCIE:PM_CSR_BPCCEN | PCIE:DRP36[5] PCIE:PM_CSR_NOSOFTRST |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP36[2] PCIE:PM_CAP_VERSION[2] | PCIE:DRP36[3] PCIE:PM_CSR_B2B3 |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP36[0] PCIE:PM_CAP_VERSION[0] | PCIE:DRP36[1] PCIE:PM_CAP_VERSION[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP41[14] PCIE:RBAR_CAP_SUP0[30] | PCIE:DRP41[15] PCIE:RBAR_CAP_SUP0[31] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP41[12] PCIE:RBAR_CAP_SUP0[28] | PCIE:DRP41[13] PCIE:RBAR_CAP_SUP0[29] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP41[10] PCIE:RBAR_CAP_SUP0[26] | PCIE:DRP41[11] PCIE:RBAR_CAP_SUP0[27] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP41[8] PCIE:RBAR_CAP_SUP0[24] | PCIE:DRP41[9] PCIE:RBAR_CAP_SUP0[25] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP41[6] PCIE:RBAR_CAP_SUP0[22] | PCIE:DRP41[7] PCIE:RBAR_CAP_SUP0[23] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP41[4] PCIE:RBAR_CAP_SUP0[20] | PCIE:DRP41[5] PCIE:RBAR_CAP_SUP0[21] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP41[2] PCIE:RBAR_CAP_SUP0[18] | PCIE:DRP41[3] PCIE:RBAR_CAP_SUP0[19] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP41[0] PCIE:RBAR_CAP_SUP0[16] | PCIE:DRP41[1] PCIE:RBAR_CAP_SUP0[17] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP40[14] PCIE:RBAR_CAP_SUP0[14] | PCIE:DRP40[15] PCIE:RBAR_CAP_SUP0[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP40[12] PCIE:RBAR_CAP_SUP0[12] | PCIE:DRP40[13] PCIE:RBAR_CAP_SUP0[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP40[10] PCIE:RBAR_CAP_SUP0[10] | PCIE:DRP40[11] PCIE:RBAR_CAP_SUP0[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP40[8] PCIE:RBAR_CAP_SUP0[8] | PCIE:DRP40[9] PCIE:RBAR_CAP_SUP0[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP40[6] PCIE:RBAR_CAP_SUP0[6] | PCIE:DRP40[7] PCIE:RBAR_CAP_SUP0[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP40[4] PCIE:RBAR_CAP_SUP0[4] | PCIE:DRP40[5] PCIE:RBAR_CAP_SUP0[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP40[2] PCIE:RBAR_CAP_SUP0[2] | PCIE:DRP40[3] PCIE:RBAR_CAP_SUP0[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP40[0] PCIE:RBAR_CAP_SUP0[0] | PCIE:DRP40[1] PCIE:RBAR_CAP_SUP0[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3F[14] | PCIE:DRP3F[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3F[12] | PCIE:DRP3F[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3F[10] | PCIE:DRP3F[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3F[8] | PCIE:DRP3F[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3F[6] PCIE:RBAR_NUM[2] | PCIE:DRP3F[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3F[4] PCIE:RBAR_NUM[0] | PCIE:DRP3F[5] PCIE:RBAR_NUM[1] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3F[2] PCIE:RBAR_CAP_VERSION[2] | PCIE:DRP3F[3] PCIE:RBAR_CAP_VERSION[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3F[0] PCIE:RBAR_CAP_VERSION[0] | PCIE:DRP3F[1] PCIE:RBAR_CAP_VERSION[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3E[14] PCIE:RBAR_CAP_ID[14] | PCIE:DRP3E[15] PCIE:RBAR_CAP_ID[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3E[12] PCIE:RBAR_CAP_ID[12] | PCIE:DRP3E[13] PCIE:RBAR_CAP_ID[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3E[10] PCIE:RBAR_CAP_ID[10] | PCIE:DRP3E[11] PCIE:RBAR_CAP_ID[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3E[8] PCIE:RBAR_CAP_ID[8] | PCIE:DRP3E[9] PCIE:RBAR_CAP_ID[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3E[6] PCIE:RBAR_CAP_ID[6] | PCIE:DRP3E[7] PCIE:RBAR_CAP_ID[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3E[4] PCIE:RBAR_CAP_ID[4] | PCIE:DRP3E[5] PCIE:RBAR_CAP_ID[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3E[2] PCIE:RBAR_CAP_ID[2] | PCIE:DRP3E[3] PCIE:RBAR_CAP_ID[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3E[0] PCIE:RBAR_CAP_ID[0] | PCIE:DRP3E[1] PCIE:RBAR_CAP_ID[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3D[14] | PCIE:DRP3D[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3D[12] PCIE:RBAR_CAP_ON | PCIE:DRP3D[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3D[10] PCIE:RBAR_CAP_NEXTPTR[10] | PCIE:DRP3D[11] PCIE:RBAR_CAP_NEXTPTR[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3D[8] PCIE:RBAR_CAP_NEXTPTR[8] | PCIE:DRP3D[9] PCIE:RBAR_CAP_NEXTPTR[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3D[6] PCIE:RBAR_CAP_NEXTPTR[6] | PCIE:DRP3D[7] PCIE:RBAR_CAP_NEXTPTR[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3D[4] PCIE:RBAR_CAP_NEXTPTR[4] | PCIE:DRP3D[5] PCIE:RBAR_CAP_NEXTPTR[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3D[2] PCIE:RBAR_CAP_NEXTPTR[2] | PCIE:DRP3D[3] PCIE:RBAR_CAP_NEXTPTR[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3D[0] PCIE:RBAR_CAP_NEXTPTR[0] | PCIE:DRP3D[1] PCIE:RBAR_CAP_NEXTPTR[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3C[14] | PCIE:DRP3C[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3C[12] | PCIE:DRP3C[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3C[10] PCIE:RBAR_BASE_PTR[10] | PCIE:DRP3C[11] PCIE:RBAR_BASE_PTR[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3C[8] PCIE:RBAR_BASE_PTR[8] | PCIE:DRP3C[9] PCIE:RBAR_BASE_PTR[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3C[6] PCIE:RBAR_BASE_PTR[6] | PCIE:DRP3C[7] PCIE:RBAR_BASE_PTR[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3C[4] PCIE:RBAR_BASE_PTR[4] | PCIE:DRP3C[5] PCIE:RBAR_BASE_PTR[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3C[2] PCIE:RBAR_BASE_PTR[2] | PCIE:DRP3C[3] PCIE:RBAR_BASE_PTR[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP3C[0] PCIE:RBAR_BASE_PTR[0] | PCIE:DRP3C[1] PCIE:RBAR_BASE_PTR[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5F[14] PCIE:PM_ASPML0S_TIMEOUT[14] | PCIE:DRP5F[15] PCIE:PM_ASPML0S_TIMEOUT_EN |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5F[12] PCIE:PM_ASPML0S_TIMEOUT[12] | PCIE:DRP5F[13] PCIE:PM_ASPML0S_TIMEOUT[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5F[10] PCIE:PM_ASPML0S_TIMEOUT[10] | PCIE:DRP5F[11] PCIE:PM_ASPML0S_TIMEOUT[11] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5F[8] PCIE:PM_ASPML0S_TIMEOUT[8] | PCIE:DRP5F[9] PCIE:PM_ASPML0S_TIMEOUT[9] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5F[6] PCIE:PM_ASPML0S_TIMEOUT[6] | PCIE:DRP5F[7] PCIE:PM_ASPML0S_TIMEOUT[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5F[4] PCIE:PM_ASPML0S_TIMEOUT[4] | PCIE:DRP5F[5] PCIE:PM_ASPML0S_TIMEOUT[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5F[2] PCIE:PM_ASPML0S_TIMEOUT[2] | PCIE:DRP5F[3] PCIE:PM_ASPML0S_TIMEOUT[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5F[0] PCIE:PM_ASPML0S_TIMEOUT[0] | PCIE:DRP5F[1] PCIE:PM_ASPML0S_TIMEOUT[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5E[14] | PCIE:DRP5E[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5E[12] | PCIE:DRP5E[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5E[10] | PCIE:DRP5E[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5E[8] | PCIE:DRP5E[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5E[6] | PCIE:DRP5E[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5E[4] | PCIE:DRP5E[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5E[2] | PCIE:DRP5E[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5E[0] PCIE:LL_REPLAY_TIMEOUT_FUNC[0] | PCIE:DRP5E[1] PCIE:LL_REPLAY_TIMEOUT_FUNC[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5D[14] PCIE:LL_REPLAY_TIMEOUT[14] | PCIE:DRP5D[15] PCIE:LL_REPLAY_TIMEOUT_EN |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5D[12] PCIE:LL_REPLAY_TIMEOUT[12] | PCIE:DRP5D[13] PCIE:LL_REPLAY_TIMEOUT[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5D[10] PCIE:LL_REPLAY_TIMEOUT[10] | PCIE:DRP5D[11] PCIE:LL_REPLAY_TIMEOUT[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5D[8] PCIE:LL_REPLAY_TIMEOUT[8] | PCIE:DRP5D[9] PCIE:LL_REPLAY_TIMEOUT[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5D[6] PCIE:LL_REPLAY_TIMEOUT[6] | PCIE:DRP5D[7] PCIE:LL_REPLAY_TIMEOUT[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5D[4] PCIE:LL_REPLAY_TIMEOUT[4] | PCIE:DRP5D[5] PCIE:LL_REPLAY_TIMEOUT[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5D[2] PCIE:LL_REPLAY_TIMEOUT[2] | PCIE:DRP5D[3] PCIE:LL_REPLAY_TIMEOUT[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5D[0] PCIE:LL_REPLAY_TIMEOUT[0] | PCIE:DRP5D[1] PCIE:LL_REPLAY_TIMEOUT[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5C[14] | PCIE:DRP5C[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5C[12] | PCIE:DRP5C[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5C[10] | PCIE:DRP5C[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5C[8] | PCIE:DRP5C[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5C[6] | PCIE:DRP5C[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5C[4] | PCIE:DRP5C[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5C[2] | PCIE:DRP5C[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5C[0] PCIE:LL_ACK_TIMEOUT_FUNC[0] | PCIE:DRP5C[1] PCIE:LL_ACK_TIMEOUT_FUNC[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5B[14] PCIE:LL_ACK_TIMEOUT[14] | PCIE:DRP5B[15] PCIE:LL_ACK_TIMEOUT_EN |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5B[12] PCIE:LL_ACK_TIMEOUT[12] | PCIE:DRP5B[13] PCIE:LL_ACK_TIMEOUT[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5B[10] PCIE:LL_ACK_TIMEOUT[10] | PCIE:DRP5B[11] PCIE:LL_ACK_TIMEOUT[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5B[8] PCIE:LL_ACK_TIMEOUT[8] | PCIE:DRP5B[9] PCIE:LL_ACK_TIMEOUT[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5B[6] PCIE:LL_ACK_TIMEOUT[6] | PCIE:DRP5B[7] PCIE:LL_ACK_TIMEOUT[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5B[4] PCIE:LL_ACK_TIMEOUT[4] | PCIE:DRP5B[5] PCIE:LL_ACK_TIMEOUT[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5B[2] PCIE:LL_ACK_TIMEOUT[2] | PCIE:DRP5B[3] PCIE:LL_ACK_TIMEOUT[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5B[0] PCIE:LL_ACK_TIMEOUT[0] | PCIE:DRP5B[1] PCIE:LL_ACK_TIMEOUT[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5A[14] | PCIE:DRP5A[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CRM_MODULE_RSTS[5] PCIE:DRP5A[12] | PCIE:CRM_MODULE_RSTS[6] PCIE:DRP5A[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CRM_MODULE_RSTS[3] PCIE:DRP5A[10] | PCIE:CRM_MODULE_RSTS[4] PCIE:DRP5A[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CRM_MODULE_RSTS[1] PCIE:DRP5A[8] | PCIE:CRM_MODULE_RSTS[2] PCIE:DRP5A[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5A[6] PCIE:USER_CLK_FREQ[2] | PCIE:CRM_MODULE_RSTS[0] PCIE:DRP5A[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5A[4] PCIE:USER_CLK_FREQ[0] | PCIE:DRP5A[5] PCIE:USER_CLK_FREQ[1] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5A[2] PCIE:VSEC_CAP_VERSION[2] | PCIE:DRP5A[3] PCIE:VSEC_CAP_VERSION[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP5A[0] PCIE:VSEC_CAP_VERSION[0] | PCIE:DRP5A[1] PCIE:VSEC_CAP_VERSION[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP71[14] PCIE:SPARE_BYTE3[6] | PCIE:DRP71[15] PCIE:SPARE_BYTE3[7] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP71[12] PCIE:SPARE_BYTE3[4] | PCIE:DRP71[13] PCIE:SPARE_BYTE3[5] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP71[10] PCIE:SPARE_BYTE3[2] | PCIE:DRP71[11] PCIE:SPARE_BYTE3[3] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP71[8] PCIE:SPARE_BYTE3[0] | PCIE:DRP71[9] PCIE:SPARE_BYTE3[1] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP71[6] PCIE:SPARE_BYTE2[6] | PCIE:DRP71[7] PCIE:SPARE_BYTE2[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP71[4] PCIE:SPARE_BYTE2[4] | PCIE:DRP71[5] PCIE:SPARE_BYTE2[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP71[2] PCIE:SPARE_BYTE2[2] | PCIE:DRP71[3] PCIE:SPARE_BYTE2[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP71[0] PCIE:SPARE_BYTE2[0] | PCIE:DRP71[1] PCIE:SPARE_BYTE2[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP70[14] PCIE:SPARE_BYTE1[6] | PCIE:DRP70[15] PCIE:SPARE_BYTE1[7] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP70[12] PCIE:SPARE_BYTE1[4] | PCIE:DRP70[13] PCIE:SPARE_BYTE1[5] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP70[10] PCIE:SPARE_BYTE1[2] | PCIE:DRP70[11] PCIE:SPARE_BYTE1[3] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP70[8] PCIE:SPARE_BYTE1[0] | PCIE:DRP70[9] PCIE:SPARE_BYTE1[1] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP70[6] PCIE:SPARE_BYTE0[6] | PCIE:DRP70[7] PCIE:SPARE_BYTE0[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP70[4] PCIE:SPARE_BYTE0[4] | PCIE:DRP70[5] PCIE:SPARE_BYTE0[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP70[2] PCIE:SPARE_BYTE0[2] | PCIE:DRP70[3] PCIE:SPARE_BYTE0[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP70[0] PCIE:SPARE_BYTE0[0] | PCIE:DRP70[1] PCIE:SPARE_BYTE0[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6F[14] | PCIE:DRP6F[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6F[12] | PCIE:DRP6F[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6F[10] | PCIE:DRP6F[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6F[8] PCIE:SPARE_BIT7 | PCIE:DRP6F[9] PCIE:SPARE_BIT8 |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6F[6] PCIE:SPARE_BIT5 | PCIE:DRP6F[7] PCIE:SPARE_BIT6 |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6F[4] PCIE:SPARE_BIT3 | PCIE:DRP6F[5] PCIE:SPARE_BIT4 |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6F[2] PCIE:SPARE_BIT1 | PCIE:DRP6F[3] PCIE:SPARE_BIT2 |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6F[0] PCIE:TEST_MODE_PIN_CHAR | PCIE:DRP6F[1] PCIE:SPARE_BIT0 |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6E[14] PCIE:RP_AUTO_SPD_LOOPCNT[3] | PCIE:DRP6E[15] PCIE:RP_AUTO_SPD_LOOPCNT[4] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6E[12] PCIE:RP_AUTO_SPD_LOOPCNT[1] | PCIE:DRP6E[13] PCIE:RP_AUTO_SPD_LOOPCNT[2] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6E[10] PCIE:RP_AUTO_SPD[1] | PCIE:DRP6E[11] PCIE:RP_AUTO_SPD_LOOPCNT[0] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6E[8] PCIE:USER_CLK2_DIV2 | PCIE:DRP6E[9] PCIE:RP_AUTO_SPD[0] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6E[6] PCIE:TRN_DW | PCIE:DRP6E[7] PCIE:TRN_NP_FC |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6E[4] PCIE:UR_ATOMIC | PCIE:DRP6E[5] PCIE:UR_CFG1 |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6E[2] PCIE:UR_INV_REQ | PCIE:DRP6E[3] PCIE:UR_PRS_RESPONSE |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:CFG_ECRC_ERR_CPLSTAT[0] PCIE:DRP6E[0] | PCIE:CFG_ECRC_ERR_CPLSTAT[1] PCIE:DRP6E[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6D[14] PCIE:RECRC_CHK_TRIM | PCIE:DRP6D[15] PCIE:TECRC_EP_INV |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6D[12] PCIE:RECRC_CHK[0] | PCIE:DRP6D[13] PCIE:RECRC_CHK[1] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6D[10] PCIE:VC0_TX_LASTPACKET[3] | PCIE:DRP6D[11] PCIE:VC0_TX_LASTPACKET[4] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6D[8] PCIE:VC0_TX_LASTPACKET[1] | PCIE:DRP6D[9] PCIE:VC0_TX_LASTPACKET[2] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6D[6] PCIE:VC0_TOTAL_CREDITS_PH[6] | PCIE:DRP6D[7] PCIE:VC0_TX_LASTPACKET[0] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6D[4] PCIE:VC0_TOTAL_CREDITS_PH[4] | PCIE:DRP6D[5] PCIE:VC0_TOTAL_CREDITS_PH[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6D[2] PCIE:VC0_TOTAL_CREDITS_PH[2] | PCIE:DRP6D[3] PCIE:VC0_TOTAL_CREDITS_PH[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6D[0] PCIE:VC0_TOTAL_CREDITS_PH[0] | PCIE:DRP6D[1] PCIE:VC0_TOTAL_CREDITS_PH[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6C[14] | PCIE:DRP6C[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6C[12] | PCIE:DRP6C[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6C[10] PCIE:VC0_TOTAL_CREDITS_PD[10] | PCIE:DRP6C[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6C[8] PCIE:VC0_TOTAL_CREDITS_PD[8] | PCIE:DRP6C[9] PCIE:VC0_TOTAL_CREDITS_PD[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6C[6] PCIE:VC0_TOTAL_CREDITS_PD[6] | PCIE:DRP6C[7] PCIE:VC0_TOTAL_CREDITS_PD[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6C[4] PCIE:VC0_TOTAL_CREDITS_PD[4] | PCIE:DRP6C[5] PCIE:VC0_TOTAL_CREDITS_PD[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6C[2] PCIE:VC0_TOTAL_CREDITS_PD[2] | PCIE:DRP6C[3] PCIE:VC0_TOTAL_CREDITS_PD[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP6C[0] PCIE:VC0_TOTAL_CREDITS_PD[0] | PCIE:DRP6C[1] PCIE:VC0_TOTAL_CREDITS_PD[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7D[14] | PCIE:DRP7D[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7D[12] | PCIE:DRP7D[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7D[10] | PCIE:DRP7D[11] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7D[8] | PCIE:DRP7D[9] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7D[6] | PCIE:DRP7D[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7D[4] | PCIE:DRP7D[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7D[2] | PCIE:DRP7D[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7D[0] | PCIE:DRP7D[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7C[14] | PCIE:DRP7C[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7C[12] | PCIE:DRP7C[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7C[10] | PCIE:DRP7C[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7C[8] | PCIE:DRP7C[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7C[6] | PCIE:DRP7C[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7C[4] | PCIE:DRP7C[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7C[2] | PCIE:DRP7C[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7C[0] | PCIE:DRP7C[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7B[14] | PCIE:DRP7B[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7B[12] | PCIE:DRP7B[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7B[10] | PCIE:DRP7B[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7B[8] | PCIE:DRP7B[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7B[6] | PCIE:DRP7B[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7B[4] | PCIE:DRP7B[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7B[2] | PCIE:DRP7B[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7B[0] | PCIE:DRP7B[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7A[14] | PCIE:DRP7A[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7A[12] | PCIE:DRP7A[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7A[10] | PCIE:DRP7A[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7A[8] | PCIE:DRP7A[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7A[6] | PCIE:DRP7A[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7A[4] | PCIE:DRP7A[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7A[2] | PCIE:DRP7A[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7A[0] | PCIE:DRP7A[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP79[14] PCIE:SPARE_WORD3[30] | PCIE:DRP79[15] PCIE:SPARE_WORD3[31] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP79[12] PCIE:SPARE_WORD3[28] | PCIE:DRP79[13] PCIE:SPARE_WORD3[29] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP79[10] PCIE:SPARE_WORD3[26] | PCIE:DRP79[11] PCIE:SPARE_WORD3[27] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP79[8] PCIE:SPARE_WORD3[24] | PCIE:DRP79[9] PCIE:SPARE_WORD3[25] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP79[6] PCIE:SPARE_WORD3[22] | PCIE:DRP79[7] PCIE:SPARE_WORD3[23] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP79[4] PCIE:SPARE_WORD3[20] | PCIE:DRP79[5] PCIE:SPARE_WORD3[21] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP79[2] PCIE:SPARE_WORD3[18] | PCIE:DRP79[3] PCIE:SPARE_WORD3[19] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP79[0] PCIE:SPARE_WORD3[16] | PCIE:DRP79[1] PCIE:SPARE_WORD3[17] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP78[14] PCIE:SPARE_WORD3[14] | PCIE:DRP78[15] PCIE:SPARE_WORD3[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP78[12] PCIE:SPARE_WORD3[12] | PCIE:DRP78[13] PCIE:SPARE_WORD3[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP78[10] PCIE:SPARE_WORD3[10] | PCIE:DRP78[11] PCIE:SPARE_WORD3[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP78[8] PCIE:SPARE_WORD3[8] | PCIE:DRP78[9] PCIE:SPARE_WORD3[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP78[6] PCIE:SPARE_WORD3[6] | PCIE:DRP78[7] PCIE:SPARE_WORD3[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP78[4] PCIE:SPARE_WORD3[4] | PCIE:DRP78[5] PCIE:SPARE_WORD3[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP78[2] PCIE:SPARE_WORD3[2] | PCIE:DRP78[3] PCIE:SPARE_WORD3[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP78[0] PCIE:SPARE_WORD3[0] | PCIE:DRP78[1] PCIE:SPARE_WORD3[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP83[14] | PCIE:DRP83[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP83[12] | PCIE:DRP83[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP83[10] | PCIE:DRP83[11] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP83[8] | PCIE:DRP83[9] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP83[6] | PCIE:DRP83[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP83[4] | PCIE:DRP83[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP83[2] | PCIE:DRP83[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP83[0] | PCIE:DRP83[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP82[14] | PCIE:DRP82[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP82[12] | PCIE:DRP82[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP82[10] | PCIE:DRP82[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP82[8] | PCIE:DRP82[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP82[6] | PCIE:DRP82[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP82[4] | PCIE:DRP82[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP82[2] | PCIE:DRP82[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP82[0] | PCIE:DRP82[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP81[14] | PCIE:DRP81[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP81[12] | PCIE:DRP81[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP81[10] | PCIE:DRP81[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP81[8] | PCIE:DRP81[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP81[6] | PCIE:DRP81[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP81[4] | PCIE:DRP81[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP81[2] | PCIE:DRP81[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP81[0] | PCIE:DRP81[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP80[14] | PCIE:DRP80[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP80[12] | PCIE:DRP80[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP80[10] | PCIE:DRP80[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP80[8] | PCIE:DRP80[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP80[6] | PCIE:DRP80[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP80[4] | PCIE:DRP80[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP80[2] | PCIE:DRP80[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP80[0] | PCIE:DRP80[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7F[14] | PCIE:DRP7F[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7F[12] | PCIE:DRP7F[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7F[10] | PCIE:DRP7F[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7F[8] | PCIE:DRP7F[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7F[6] | PCIE:DRP7F[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7F[4] | PCIE:DRP7F[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7F[2] | PCIE:DRP7F[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7F[0] | PCIE:DRP7F[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7E[14] | PCIE:DRP7E[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7E[12] | PCIE:DRP7E[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7E[10] | PCIE:DRP7E[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7E[8] | PCIE:DRP7E[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7E[6] | PCIE:DRP7E[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7E[4] | PCIE:DRP7E[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7E[2] | PCIE:DRP7E[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP7E[0] | PCIE:DRP7E[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP89[14] | PCIE:DRP89[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP89[12] | PCIE:DRP89[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP89[10] | PCIE:DRP89[11] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP89[8] | PCIE:DRP89[9] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP89[6] | PCIE:DRP89[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP89[4] | PCIE:DRP89[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP89[2] | PCIE:DRP89[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP89[0] | PCIE:DRP89[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP88[14] | PCIE:DRP88[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP88[12] | PCIE:DRP88[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP88[10] | PCIE:DRP88[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP88[8] | PCIE:DRP88[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP88[6] | PCIE:DRP88[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP88[4] | PCIE:DRP88[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP88[2] | PCIE:DRP88[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP88[0] | PCIE:DRP88[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP87[14] | PCIE:DRP87[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP87[12] | PCIE:DRP87[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP87[10] | PCIE:DRP87[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP87[8] | PCIE:DRP87[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP87[6] | PCIE:DRP87[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP87[4] | PCIE:DRP87[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP87[2] | PCIE:DRP87[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP87[0] | PCIE:DRP87[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP86[14] | PCIE:DRP86[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP86[12] | PCIE:DRP86[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP86[10] | PCIE:DRP86[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP86[8] | PCIE:DRP86[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP86[6] | PCIE:DRP86[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP86[4] | PCIE:DRP86[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP86[2] | PCIE:DRP86[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP86[0] | PCIE:DRP86[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP85[14] | PCIE:DRP85[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP85[12] | PCIE:DRP85[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP85[10] | PCIE:DRP85[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP85[8] | PCIE:DRP85[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP85[6] | PCIE:DRP85[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP85[4] | PCIE:DRP85[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP85[2] | PCIE:DRP85[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP85[0] | PCIE:DRP85[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP84[14] | PCIE:DRP84[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP84[12] | PCIE:DRP84[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP84[10] | PCIE:DRP84[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP84[8] | PCIE:DRP84[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP84[6] | PCIE:DRP84[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP84[4] | PCIE:DRP84[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP84[2] | PCIE:DRP84[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP84[0] | PCIE:DRP84[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8F[14] | PCIE:DRP8F[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8F[12] | PCIE:DRP8F[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8F[10] | PCIE:DRP8F[11] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8F[8] | PCIE:DRP8F[9] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8F[6] | PCIE:DRP8F[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8F[4] | PCIE:DRP8F[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8F[2] | PCIE:DRP8F[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8F[0] | PCIE:DRP8F[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8E[14] | PCIE:DRP8E[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8E[12] | PCIE:DRP8E[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8E[10] | PCIE:DRP8E[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8E[8] | PCIE:DRP8E[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8E[6] | PCIE:DRP8E[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8E[4] | PCIE:DRP8E[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8E[2] | PCIE:DRP8E[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8E[0] | PCIE:DRP8E[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8D[14] | PCIE:DRP8D[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8D[12] | PCIE:DRP8D[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8D[10] | PCIE:DRP8D[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8D[8] | PCIE:DRP8D[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8D[6] | PCIE:DRP8D[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8D[4] | PCIE:DRP8D[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8D[2] | PCIE:DRP8D[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8D[0] | PCIE:DRP8D[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8C[14] | PCIE:DRP8C[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8C[12] | PCIE:DRP8C[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8C[10] | PCIE:DRP8C[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8C[8] | PCIE:DRP8C[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8C[6] | PCIE:DRP8C[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8C[4] | PCIE:DRP8C[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8C[2] | PCIE:DRP8C[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8C[0] | PCIE:DRP8C[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8B[14] | PCIE:DRP8B[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8B[12] | PCIE:DRP8B[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8B[10] | PCIE:DRP8B[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8B[8] | PCIE:DRP8B[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8B[6] | PCIE:DRP8B[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8B[4] | PCIE:DRP8B[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8B[2] | PCIE:DRP8B[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8B[0] | PCIE:DRP8B[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8A[14] | PCIE:DRP8A[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8A[12] | PCIE:DRP8A[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8A[10] | PCIE:DRP8A[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8A[8] | PCIE:DRP8A[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8A[6] | PCIE:DRP8A[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8A[4] | PCIE:DRP8A[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8A[2] | PCIE:DRP8A[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP8A[0] | PCIE:DRP8A[1] |
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | |
| 47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP95[14] | PCIE:DRP95[15] |
| 46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP95[12] | PCIE:DRP95[13] |
| 45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP95[10] | PCIE:DRP95[11] |
| 44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP95[8] | PCIE:DRP95[9] |
| 43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP95[6] | PCIE:DRP95[7] |
| 42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP95[4] | PCIE:DRP95[5] |
| 41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP95[2] | PCIE:DRP95[3] |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP95[0] | PCIE:DRP95[1] |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP94[14] | PCIE:DRP94[15] |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP94[12] | PCIE:DRP94[13] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP94[10] | PCIE:DRP94[11] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP94[8] | PCIE:DRP94[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP94[6] | PCIE:DRP94[7] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP94[4] | PCIE:DRP94[5] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP94[2] | PCIE:DRP94[3] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP94[0] | PCIE:DRP94[1] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP93[14] | PCIE:DRP93[15] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP93[12] | PCIE:DRP93[13] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP93[10] | PCIE:DRP93[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP93[8] | PCIE:DRP93[9] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP93[6] | PCIE:DRP93[7] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP93[4] | PCIE:DRP93[5] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP93[2] | PCIE:DRP93[3] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP93[0] | PCIE:DRP93[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP92[14] | PCIE:DRP92[15] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP92[12] | PCIE:DRP92[13] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP92[10] | PCIE:DRP92[11] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP92[8] | PCIE:DRP92[9] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP92[6] | PCIE:DRP92[7] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP92[4] | PCIE:DRP92[5] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP92[2] | PCIE:DRP92[3] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP92[0] | PCIE:DRP92[1] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP91[14] | PCIE:DRP91[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP91[12] | PCIE:DRP91[13] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP91[10] | PCIE:DRP91[11] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP91[8] | PCIE:DRP91[9] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP91[6] | PCIE:DRP91[7] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP91[4] | PCIE:DRP91[5] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP91[2] | PCIE:DRP91[3] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP91[0] | PCIE:DRP91[1] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP90[14] | PCIE:DRP90[15] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP90[12] | PCIE:DRP90[13] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP90[10] | PCIE:DRP90[11] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP90[8] | PCIE:DRP90[9] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP90[6] | PCIE:DRP90[7] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP90[4] | PCIE:DRP90[5] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP90[2] | PCIE:DRP90[3] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCIE:DRP90[0] | PCIE:DRP90[1] |
| PCIE:AER_BASE_PTR | 0.29.29 | 0.28.29 | 0.29.28 | 0.28.28 | 0.29.27 | 0.28.27 | 0.29.26 | 0.28.26 | 0.29.25 | 0.28.25 | 0.29.24 | 0.28.24 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:AER_CAP_NEXTPTR | 0.29.37 | 0.28.37 | 0.29.36 | 0.28.36 | 0.29.35 | 0.28.35 | 0.29.34 | 0.28.34 | 0.29.33 | 0.28.33 | 0.29.32 | 0.28.32 |
| PCIE:DSN_BASE_PTR | 4.29.45 | 4.28.45 | 4.29.44 | 4.28.44 | 4.29.43 | 4.28.43 | 4.29.42 | 4.28.42 | 4.29.41 | 4.28.41 | 4.29.40 | 4.28.40 |
| PCIE:DSN_CAP_NEXTPTR | 5.29.13 | 5.28.13 | 5.29.12 | 5.28.12 | 5.29.11 | 5.28.11 | 5.29.10 | 5.28.10 | 5.29.9 | 5.28.9 | 5.29.8 | 5.28.8 |
| PCIE:RBAR_BASE_PTR | 10.29.5 | 10.28.5 | 10.29.4 | 10.28.4 | 10.29.3 | 10.28.3 | 10.29.2 | 10.28.2 | 10.29.1 | 10.28.1 | 10.29.0 | 10.28.0 |
| PCIE:RBAR_CAP_NEXTPTR | 10.29.13 | 10.28.13 | 10.29.12 | 10.28.12 | 10.29.11 | 10.28.11 | 10.29.10 | 10.28.10 | 10.29.9 | 10.28.9 | 10.29.8 | 10.28.8 |
| PCIE:VC_BASE_PTR | 13.29.37 | 13.28.37 | 13.29.36 | 13.28.36 | 13.29.35 | 13.28.35 | 13.29.34 | 13.28.34 | 13.29.33 | 13.28.33 | 13.29.32 | 13.28.32 |
| PCIE:VC_CAP_NEXTPTR | 13.29.45 | 13.28.45 | 13.29.44 | 13.28.44 | 13.29.43 | 13.28.43 | 13.29.42 | 13.28.42 | 13.29.41 | 13.28.41 | 13.29.40 | 13.28.40 |
| PCIE:VSEC_BASE_PTR | 14.28.14 | 14.29.13 | 14.28.13 | 14.29.12 | 14.28.12 | 14.29.11 | 14.28.11 | 14.29.10 | 14.28.10 | 14.29.9 | 14.28.9 | 14.29.8 |
| PCIE:VSEC_CAP_HDR_LENGTH | 14.29.29 | 14.28.29 | 14.29.28 | 14.28.28 | 14.29.27 | 14.28.27 | 14.29.26 | 14.28.26 | 14.29.25 | 14.28.25 | 14.29.24 | 14.28.24 |
| PCIE:VSEC_CAP_NEXTPTR | 14.28.46 | 14.29.45 | 14.28.45 | 14.29.44 | 14.28.44 | 14.29.43 | 14.28.43 | 14.29.42 | 14.28.42 | 14.29.41 | 14.28.41 | 14.29.40 |
| non-inverted | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:AER_CAP_ECRC_CHECK_CAPABLE | 0.28.0 |
|---|---|
| PCIE:AER_CAP_ECRC_GEN_CAPABLE | 0.29.0 |
| PCIE:AER_CAP_MULTIHEADER | 1.28.4 |
| PCIE:AER_CAP_ON | 0.28.38 |
| PCIE:AER_CAP_PERMIT_ROOTERR_UPDATE | 0.28.16 |
| PCIE:ALLOW_X8_GEN2 | 16.28.32 |
| PCIE:CMD_INTX_IMPLEMENTED | 4.28.12 |
| PCIE:CPL_TIMEOUT_DISABLE_SUPPORTED | 4.29.12 |
| PCIE:DEV_CAP2_ARI_FORWARDING_SUPPORTED | 4.28.15 |
| PCIE:DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED | 4.28.16 |
| PCIE:DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED | 4.29.16 |
| PCIE:DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED | 4.29.15 |
| PCIE:DEV_CAP2_CAS128_COMPLETER_SUPPORTED | 4.28.17 |
| PCIE:DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED | 4.28.20 |
| PCIE:DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED | 4.29.19 |
| PCIE:DEV_CAP2_LTR_MECHANISM_SUPPORTED | 4.28.18 |
| PCIE:DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING | 4.29.17 |
| PCIE:DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE | 4.28.22 |
| PCIE:DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE | 4.29.22 |
| PCIE:DEV_CAP_EXT_TAG_SUPPORTED | 4.28.27 |
| PCIE:DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE | 4.29.27 |
| PCIE:DEV_CAP_ROLE_BASED_ERROR | 4.29.30 |
| PCIE:DEV_CONTROL_AUX_POWER_SUPPORTED | 4.28.36 |
| PCIE:DEV_CONTROL_EXT_TAG_DEFAULT | 4.29.36 |
| PCIE:DISABLE_ASPM_L1_TIMER | 16.28.40 |
| PCIE:DISABLE_BAR_FILTERING | 16.29.40 |
| PCIE:DISABLE_ERR_MSG | 17.29.5 |
| PCIE:DISABLE_ID_CHECK | 16.28.41 |
| PCIE:DISABLE_LANE_REVERSAL | 16.29.1 |
| PCIE:DISABLE_LOCKED_FILTER | 17.29.4 |
| PCIE:DISABLE_PPM_FILTER | 17.28.4 |
| PCIE:DISABLE_RX_POISONED_RESP | 16.28.42 |
| PCIE:DISABLE_RX_TC_FILTER | 16.29.41 |
| PCIE:DISABLE_SCRAMBLING | 16.28.2 |
| PCIE:DSN_CAP_ON | 5.28.14 |
| PCIE:ENABLE_RX_TD_ECRC_TRIM | 17.28.0 |
| PCIE:ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED | 4.29.21 |
| PCIE:ENTER_RVRY_EI_L0 | 16.29.2 |
| PCIE:EXIT_LOOPBACK_ON_EI | 16.29.35 |
| PCIE:INTERRUPT_STAT_AUTO | 5.28.40 |
| PCIE:IS_SWITCH | 5.29.40 |
| PCIE:LINK_CAP_ASPM_OPTIONALITY | 6.28.15 |
| PCIE:LINK_CAP_CLOCK_POWER_MANAGEMENT | 5.28.47 |
| PCIE:LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP | 5.29.47 |
| PCIE:LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP | 6.29.12 |
| PCIE:LINK_CAP_RSVD_23 | 6.29.15 |
| PCIE:LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE | 6.28.16 |
| PCIE:LINK_CONTROL_RCB | 6.29.16 |
| PCIE:LINK_CTRL2_DEEMPHASIS | 6.28.17 |
| PCIE:LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE | 6.29.17 |
| PCIE:LINK_STATUS_SLOT_CLOCK_CONFIG | 6.28.20 |
| PCIE:LL_ACK_TIMEOUT_EN | 15.29.15 |
| PCIE:LL_REPLAY_TIMEOUT_EN | 15.29.31 |
| PCIE:MPS_FORCE | 6.29.20 |
| PCIE:MSIX_CAP_ON | 7.28.12 |
| PCIE:MSI_CAP_64_BIT_ADDR_CAPABLE | 6.28.28 |
| PCIE:MSI_CAP_MULTIMSG_EXTENSION | 6.28.36 |
| PCIE:MSI_CAP_ON | 6.28.44 |
| PCIE:MSI_CAP_PER_VECTOR_MASKING_CAPABLE | 6.29.44 |
| PCIE:PCIE_CAP_ON | 8.28.24 |
| PCIE:PCIE_CAP_SLOT_IMPLEMENTED | 8.29.25 |
| PCIE:PL_FAST_TRAIN | 16.28.34 |
| PCIE:PM_ASPML0S_TIMEOUT_EN | 15.29.47 |
| PCIE:PM_ASPM_FASTEXIT | 16.28.1 |
| PCIE:PM_CAP_D1SUPPORT | 8.29.33 |
| PCIE:PM_CAP_D2SUPPORT | 8.28.34 |
| PCIE:PM_CAP_DSI | 8.29.34 |
| PCIE:PM_CAP_ON | 8.28.44 |
| PCIE:PM_CAP_PME_CLOCK | 8.29.44 |
| PCIE:PM_CAP_RSVD_04 | 8.29.47 |
| PCIE:PM_CSR_B2B3 | 9.29.1 |
| PCIE:PM_CSR_BPCCEN | 9.28.2 |
| PCIE:PM_CSR_NOSOFTRST | 9.29.2 |
| PCIE:PM_MF | 17.28.6 |
| PCIE:RBAR_CAP_ON | 10.28.14 |
| PCIE:RECRC_CHK_TRIM | 18.28.15 |
| PCIE:ROOT_CAP_CRS_SW_VISIBILITY | 13.29.10 |
| PCIE:SELECT_DLL_IF | 13.28.11 |
| PCIE:SLOT_CAP_ATT_BUTTON_PRESENT | 13.29.11 |
| PCIE:SLOT_CAP_ATT_INDICATOR_PRESENT | 13.28.12 |
| PCIE:SLOT_CAP_ELEC_INTERLOCK_PRESENT | 13.29.12 |
| PCIE:SLOT_CAP_HOTPLUG_CAPABLE | 13.28.13 |
| PCIE:SLOT_CAP_HOTPLUG_SURPRISE | 13.29.13 |
| PCIE:SLOT_CAP_MRL_SENSOR_PRESENT | 13.28.14 |
| PCIE:SLOT_CAP_NO_CMD_COMPLETED_SUPPORT | 13.29.14 |
| PCIE:SLOT_CAP_POWER_CONTROLLER_PRESENT | 13.29.22 |
| PCIE:SLOT_CAP_POWER_INDICATOR_PRESENT | 13.28.23 |
| PCIE:SPARE_BIT0 | 18.29.24 |
| PCIE:SPARE_BIT1 | 18.28.25 |
| PCIE:SPARE_BIT2 | 18.29.25 |
| PCIE:SPARE_BIT3 | 18.28.26 |
| PCIE:SPARE_BIT4 | 18.29.26 |
| PCIE:SPARE_BIT5 | 18.28.27 |
| PCIE:SPARE_BIT6 | 18.29.27 |
| PCIE:SPARE_BIT7 | 18.28.28 |
| PCIE:SPARE_BIT8 | 18.29.28 |
| PCIE:SSL_MESSAGE_AUTO | 13.28.29 |
| PCIE:TECRC_EP_INV | 18.29.15 |
| PCIE:TEST_MODE_PIN_CHAR | 18.28.24 |
| PCIE:TL_RBYPASS | 17.29.3 |
| PCIE:TL_RX_RAM_RADDR_LATENCY | 17.29.0 |
| PCIE:TL_RX_RAM_WRITE_LATENCY | 17.28.2 |
| PCIE:TL_TFC_DISABLE | 17.29.2 |
| PCIE:TL_TX_CHECKS_DISABLE | 17.28.3 |
| PCIE:TL_TX_RAM_RADDR_LATENCY | 17.29.6 |
| PCIE:TL_TX_RAM_WRITE_LATENCY | 17.28.8 |
| PCIE:TRN_DW | 18.28.19 |
| PCIE:TRN_NP_FC | 18.29.19 |
| PCIE:UPCONFIG_CAPABLE | 16.29.34 |
| PCIE:UPSTREAM_FACING | 16.28.35 |
| PCIE:UR_ATOMIC | 18.28.18 |
| PCIE:UR_CFG1 | 18.29.18 |
| PCIE:UR_INV_REQ | 18.28.17 |
| PCIE:UR_PRS_RESPONSE | 18.29.17 |
| PCIE:USER_CLK2_DIV2 | 18.28.20 |
| PCIE:USE_RID_PINS | 17.28.5 |
| PCIE:VC0_CPL_INFINITE | 17.29.10 |
| PCIE:VC_CAP_ON | 13.28.46 |
| PCIE:VC_CAP_REJECT_SNOOP_TRANSACTIONS | 14.28.8 |
| PCIE:VSEC_CAP_IS_LINK_VISIBLE | 14.28.40 |
| PCIE:VSEC_CAP_ON | 14.29.46 |
| non-inverted | [0] |
| PCIE:AER_CAP_ID | 0.29.15 | 0.28.15 | 0.29.14 | 0.28.14 | 0.29.13 | 0.28.13 | 0.29.12 | 0.28.12 | 0.29.11 | 0.28.11 | 0.29.10 | 0.28.10 | 0.29.9 | 0.28.9 | 0.29.8 | 0.28.8 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:DRP00 | 0.29.7 | 0.28.7 | 0.29.6 | 0.28.6 | 0.29.5 | 0.28.5 | 0.29.4 | 0.28.4 | 0.29.3 | 0.28.3 | 0.29.2 | 0.28.2 | 0.29.1 | 0.28.1 | 0.29.0 | 0.28.0 |
| PCIE:DRP01 | 0.29.15 | 0.28.15 | 0.29.14 | 0.28.14 | 0.29.13 | 0.28.13 | 0.29.12 | 0.28.12 | 0.29.11 | 0.28.11 | 0.29.10 | 0.28.10 | 0.29.9 | 0.28.9 | 0.29.8 | 0.28.8 |
| PCIE:DRP02 | 0.29.23 | 0.28.23 | 0.29.22 | 0.28.22 | 0.29.21 | 0.28.21 | 0.29.20 | 0.28.20 | 0.29.19 | 0.28.19 | 0.29.18 | 0.28.18 | 0.29.17 | 0.28.17 | 0.29.16 | 0.28.16 |
| PCIE:DRP03 | 0.29.31 | 0.28.31 | 0.29.30 | 0.28.30 | 0.29.29 | 0.28.29 | 0.29.28 | 0.28.28 | 0.29.27 | 0.28.27 | 0.29.26 | 0.28.26 | 0.29.25 | 0.28.25 | 0.29.24 | 0.28.24 |
| PCIE:DRP04 | 0.29.39 | 0.28.39 | 0.29.38 | 0.28.38 | 0.29.37 | 0.28.37 | 0.29.36 | 0.28.36 | 0.29.35 | 0.28.35 | 0.29.34 | 0.28.34 | 0.29.33 | 0.28.33 | 0.29.32 | 0.28.32 |
| PCIE:DRP05 | 0.29.47 | 0.28.47 | 0.29.46 | 0.28.46 | 0.29.45 | 0.28.45 | 0.29.44 | 0.28.44 | 0.29.43 | 0.28.43 | 0.29.42 | 0.28.42 | 0.29.41 | 0.28.41 | 0.29.40 | 0.28.40 |
| PCIE:DRP06 | 1.29.7 | 1.28.7 | 1.29.6 | 1.28.6 | 1.29.5 | 1.28.5 | 1.29.4 | 1.28.4 | 1.29.3 | 1.28.3 | 1.29.2 | 1.28.2 | 1.29.1 | 1.28.1 | 1.29.0 | 1.28.0 |
| PCIE:DRP07 | 1.29.15 | 1.28.15 | 1.29.14 | 1.28.14 | 1.29.13 | 1.28.13 | 1.29.12 | 1.28.12 | 1.29.11 | 1.28.11 | 1.29.10 | 1.28.10 | 1.29.9 | 1.28.9 | 1.29.8 | 1.28.8 |
| PCIE:DRP08 | 1.29.23 | 1.28.23 | 1.29.22 | 1.28.22 | 1.29.21 | 1.28.21 | 1.29.20 | 1.28.20 | 1.29.19 | 1.28.19 | 1.29.18 | 1.28.18 | 1.29.17 | 1.28.17 | 1.29.16 | 1.28.16 |
| PCIE:DRP09 | 1.29.31 | 1.28.31 | 1.29.30 | 1.28.30 | 1.29.29 | 1.28.29 | 1.29.28 | 1.28.28 | 1.29.27 | 1.28.27 | 1.29.26 | 1.28.26 | 1.29.25 | 1.28.25 | 1.29.24 | 1.28.24 |
| PCIE:DRP0A | 1.29.39 | 1.28.39 | 1.29.38 | 1.28.38 | 1.29.37 | 1.28.37 | 1.29.36 | 1.28.36 | 1.29.35 | 1.28.35 | 1.29.34 | 1.28.34 | 1.29.33 | 1.28.33 | 1.29.32 | 1.28.32 |
| PCIE:DRP0B | 1.29.47 | 1.28.47 | 1.29.46 | 1.28.46 | 1.29.45 | 1.28.45 | 1.29.44 | 1.28.44 | 1.29.43 | 1.28.43 | 1.29.42 | 1.28.42 | 1.29.41 | 1.28.41 | 1.29.40 | 1.28.40 |
| PCIE:DRP0C | 2.29.7 | 2.28.7 | 2.29.6 | 2.28.6 | 2.29.5 | 2.28.5 | 2.29.4 | 2.28.4 | 2.29.3 | 2.28.3 | 2.29.2 | 2.28.2 | 2.29.1 | 2.28.1 | 2.29.0 | 2.28.0 |
| PCIE:DRP0D | 2.29.15 | 2.28.15 | 2.29.14 | 2.28.14 | 2.29.13 | 2.28.13 | 2.29.12 | 2.28.12 | 2.29.11 | 2.28.11 | 2.29.10 | 2.28.10 | 2.29.9 | 2.28.9 | 2.29.8 | 2.28.8 |
| PCIE:DRP0E | 2.29.23 | 2.28.23 | 2.29.22 | 2.28.22 | 2.29.21 | 2.28.21 | 2.29.20 | 2.28.20 | 2.29.19 | 2.28.19 | 2.29.18 | 2.28.18 | 2.29.17 | 2.28.17 | 2.29.16 | 2.28.16 |
| PCIE:DRP0F | 2.29.31 | 2.28.31 | 2.29.30 | 2.28.30 | 2.29.29 | 2.28.29 | 2.29.28 | 2.28.28 | 2.29.27 | 2.28.27 | 2.29.26 | 2.28.26 | 2.29.25 | 2.28.25 | 2.29.24 | 2.28.24 |
| PCIE:DRP10 | 2.29.39 | 2.28.39 | 2.29.38 | 2.28.38 | 2.29.37 | 2.28.37 | 2.29.36 | 2.28.36 | 2.29.35 | 2.28.35 | 2.29.34 | 2.28.34 | 2.29.33 | 2.28.33 | 2.29.32 | 2.28.32 |
| PCIE:DRP11 | 2.29.47 | 2.28.47 | 2.29.46 | 2.28.46 | 2.29.45 | 2.28.45 | 2.29.44 | 2.28.44 | 2.29.43 | 2.28.43 | 2.29.42 | 2.28.42 | 2.29.41 | 2.28.41 | 2.29.40 | 2.28.40 |
| PCIE:DRP12 | 3.29.7 | 3.28.7 | 3.29.6 | 3.28.6 | 3.29.5 | 3.28.5 | 3.29.4 | 3.28.4 | 3.29.3 | 3.28.3 | 3.29.2 | 3.28.2 | 3.29.1 | 3.28.1 | 3.29.0 | 3.28.0 |
| PCIE:DRP13 | 3.29.15 | 3.28.15 | 3.29.14 | 3.28.14 | 3.29.13 | 3.28.13 | 3.29.12 | 3.28.12 | 3.29.11 | 3.28.11 | 3.29.10 | 3.28.10 | 3.29.9 | 3.28.9 | 3.29.8 | 3.28.8 |
| PCIE:DRP14 | 3.29.23 | 3.28.23 | 3.29.22 | 3.28.22 | 3.29.21 | 3.28.21 | 3.29.20 | 3.28.20 | 3.29.19 | 3.28.19 | 3.29.18 | 3.28.18 | 3.29.17 | 3.28.17 | 3.29.16 | 3.28.16 |
| PCIE:DRP15 | 3.29.31 | 3.28.31 | 3.29.30 | 3.28.30 | 3.29.29 | 3.28.29 | 3.29.28 | 3.28.28 | 3.29.27 | 3.28.27 | 3.29.26 | 3.28.26 | 3.29.25 | 3.28.25 | 3.29.24 | 3.28.24 |
| PCIE:DRP16 | 3.29.39 | 3.28.39 | 3.29.38 | 3.28.38 | 3.29.37 | 3.28.37 | 3.29.36 | 3.28.36 | 3.29.35 | 3.28.35 | 3.29.34 | 3.28.34 | 3.29.33 | 3.28.33 | 3.29.32 | 3.28.32 |
| PCIE:DRP17 | 3.29.47 | 3.28.47 | 3.29.46 | 3.28.46 | 3.29.45 | 3.28.45 | 3.29.44 | 3.28.44 | 3.29.43 | 3.28.43 | 3.29.42 | 3.28.42 | 3.29.41 | 3.28.41 | 3.29.40 | 3.28.40 |
| PCIE:DRP18 | 4.29.7 | 4.28.7 | 4.29.6 | 4.28.6 | 4.29.5 | 4.28.5 | 4.29.4 | 4.28.4 | 4.29.3 | 4.28.3 | 4.29.2 | 4.28.2 | 4.29.1 | 4.28.1 | 4.29.0 | 4.28.0 |
| PCIE:DRP19 | 4.29.15 | 4.28.15 | 4.29.14 | 4.28.14 | 4.29.13 | 4.28.13 | 4.29.12 | 4.28.12 | 4.29.11 | 4.28.11 | 4.29.10 | 4.28.10 | 4.29.9 | 4.28.9 | 4.29.8 | 4.28.8 |
| PCIE:DRP1A | 4.29.23 | 4.28.23 | 4.29.22 | 4.28.22 | 4.29.21 | 4.28.21 | 4.29.20 | 4.28.20 | 4.29.19 | 4.28.19 | 4.29.18 | 4.28.18 | 4.29.17 | 4.28.17 | 4.29.16 | 4.28.16 |
| PCIE:DRP1B | 4.29.31 | 4.28.31 | 4.29.30 | 4.28.30 | 4.29.29 | 4.28.29 | 4.29.28 | 4.28.28 | 4.29.27 | 4.28.27 | 4.29.26 | 4.28.26 | 4.29.25 | 4.28.25 | 4.29.24 | 4.28.24 |
| PCIE:DRP1C | 4.29.39 | 4.28.39 | 4.29.38 | 4.28.38 | 4.29.37 | 4.28.37 | 4.29.36 | 4.28.36 | 4.29.35 | 4.28.35 | 4.29.34 | 4.28.34 | 4.29.33 | 4.28.33 | 4.29.32 | 4.28.32 |
| PCIE:DRP1D | 4.29.47 | 4.28.47 | 4.29.46 | 4.28.46 | 4.29.45 | 4.28.45 | 4.29.44 | 4.28.44 | 4.29.43 | 4.28.43 | 4.29.42 | 4.28.42 | 4.29.41 | 4.28.41 | 4.29.40 | 4.28.40 |
| PCIE:DRP1E | 5.29.7 | 5.28.7 | 5.29.6 | 5.28.6 | 5.29.5 | 5.28.5 | 5.29.4 | 5.28.4 | 5.29.3 | 5.28.3 | 5.29.2 | 5.28.2 | 5.29.1 | 5.28.1 | 5.29.0 | 5.28.0 |
| PCIE:DRP1F | 5.29.15 | 5.28.15 | 5.29.14 | 5.28.14 | 5.29.13 | 5.28.13 | 5.29.12 | 5.28.12 | 5.29.11 | 5.28.11 | 5.29.10 | 5.28.10 | 5.29.9 | 5.28.9 | 5.29.8 | 5.28.8 |
| PCIE:DRP20 | 5.29.23 | 5.28.23 | 5.29.22 | 5.28.22 | 5.29.21 | 5.28.21 | 5.29.20 | 5.28.20 | 5.29.19 | 5.28.19 | 5.29.18 | 5.28.18 | 5.29.17 | 5.28.17 | 5.29.16 | 5.28.16 |
| PCIE:DRP21 | 5.29.31 | 5.28.31 | 5.29.30 | 5.28.30 | 5.29.29 | 5.28.29 | 5.29.28 | 5.28.28 | 5.29.27 | 5.28.27 | 5.29.26 | 5.28.26 | 5.29.25 | 5.28.25 | 5.29.24 | 5.28.24 |
| PCIE:DRP22 | 5.29.39 | 5.28.39 | 5.29.38 | 5.28.38 | 5.29.37 | 5.28.37 | 5.29.36 | 5.28.36 | 5.29.35 | 5.28.35 | 5.29.34 | 5.28.34 | 5.29.33 | 5.28.33 | 5.29.32 | 5.28.32 |
| PCIE:DRP23 | 5.29.47 | 5.28.47 | 5.29.46 | 5.28.46 | 5.29.45 | 5.28.45 | 5.29.44 | 5.28.44 | 5.29.43 | 5.28.43 | 5.29.42 | 5.28.42 | 5.29.41 | 5.28.41 | 5.29.40 | 5.28.40 |
| PCIE:DRP24 | 6.29.7 | 6.28.7 | 6.29.6 | 6.28.6 | 6.29.5 | 6.28.5 | 6.29.4 | 6.28.4 | 6.29.3 | 6.28.3 | 6.29.2 | 6.28.2 | 6.29.1 | 6.28.1 | 6.29.0 | 6.28.0 |
| PCIE:DRP25 | 6.29.15 | 6.28.15 | 6.29.14 | 6.28.14 | 6.29.13 | 6.28.13 | 6.29.12 | 6.28.12 | 6.29.11 | 6.28.11 | 6.29.10 | 6.28.10 | 6.29.9 | 6.28.9 | 6.29.8 | 6.28.8 |
| PCIE:DRP26 | 6.29.23 | 6.28.23 | 6.29.22 | 6.28.22 | 6.29.21 | 6.28.21 | 6.29.20 | 6.28.20 | 6.29.19 | 6.28.19 | 6.29.18 | 6.28.18 | 6.29.17 | 6.28.17 | 6.29.16 | 6.28.16 |
| PCIE:DRP27 | 6.29.31 | 6.28.31 | 6.29.30 | 6.28.30 | 6.29.29 | 6.28.29 | 6.29.28 | 6.28.28 | 6.29.27 | 6.28.27 | 6.29.26 | 6.28.26 | 6.29.25 | 6.28.25 | 6.29.24 | 6.28.24 |
| PCIE:DRP28 | 6.29.39 | 6.28.39 | 6.29.38 | 6.28.38 | 6.29.37 | 6.28.37 | 6.29.36 | 6.28.36 | 6.29.35 | 6.28.35 | 6.29.34 | 6.28.34 | 6.29.33 | 6.28.33 | 6.29.32 | 6.28.32 |
| PCIE:DRP29 | 6.29.47 | 6.28.47 | 6.29.46 | 6.28.46 | 6.29.45 | 6.28.45 | 6.29.44 | 6.28.44 | 6.29.43 | 6.28.43 | 6.29.42 | 6.28.42 | 6.29.41 | 6.28.41 | 6.29.40 | 6.28.40 |
| PCIE:DRP2A | 7.29.7 | 7.28.7 | 7.29.6 | 7.28.6 | 7.29.5 | 7.28.5 | 7.29.4 | 7.28.4 | 7.29.3 | 7.28.3 | 7.29.2 | 7.28.2 | 7.29.1 | 7.28.1 | 7.29.0 | 7.28.0 |
| PCIE:DRP2B | 7.29.15 | 7.28.15 | 7.29.14 | 7.28.14 | 7.29.13 | 7.28.13 | 7.29.12 | 7.28.12 | 7.29.11 | 7.28.11 | 7.29.10 | 7.28.10 | 7.29.9 | 7.28.9 | 7.29.8 | 7.28.8 |
| PCIE:DRP2C | 7.29.23 | 7.28.23 | 7.29.22 | 7.28.22 | 7.29.21 | 7.28.21 | 7.29.20 | 7.28.20 | 7.29.19 | 7.28.19 | 7.29.18 | 7.28.18 | 7.29.17 | 7.28.17 | 7.29.16 | 7.28.16 |
| PCIE:DRP2D | 7.29.31 | 7.28.31 | 7.29.30 | 7.28.30 | 7.29.29 | 7.28.29 | 7.29.28 | 7.28.28 | 7.29.27 | 7.28.27 | 7.29.26 | 7.28.26 | 7.29.25 | 7.28.25 | 7.29.24 | 7.28.24 |
| PCIE:DRP2E | 7.29.39 | 7.28.39 | 7.29.38 | 7.28.38 | 7.29.37 | 7.28.37 | 7.29.36 | 7.28.36 | 7.29.35 | 7.28.35 | 7.29.34 | 7.28.34 | 7.29.33 | 7.28.33 | 7.29.32 | 7.28.32 |
| PCIE:DRP2F | 7.29.47 | 7.28.47 | 7.29.46 | 7.28.46 | 7.29.45 | 7.28.45 | 7.29.44 | 7.28.44 | 7.29.43 | 7.28.43 | 7.29.42 | 7.28.42 | 7.29.41 | 7.28.41 | 7.29.40 | 7.28.40 |
| PCIE:DRP30 | 8.29.7 | 8.28.7 | 8.29.6 | 8.28.6 | 8.29.5 | 8.28.5 | 8.29.4 | 8.28.4 | 8.29.3 | 8.28.3 | 8.29.2 | 8.28.2 | 8.29.1 | 8.28.1 | 8.29.0 | 8.28.0 |
| PCIE:DRP31 | 8.29.15 | 8.28.15 | 8.29.14 | 8.28.14 | 8.29.13 | 8.28.13 | 8.29.12 | 8.28.12 | 8.29.11 | 8.28.11 | 8.29.10 | 8.28.10 | 8.29.9 | 8.28.9 | 8.29.8 | 8.28.8 |
| PCIE:DRP32 | 8.29.23 | 8.28.23 | 8.29.22 | 8.28.22 | 8.29.21 | 8.28.21 | 8.29.20 | 8.28.20 | 8.29.19 | 8.28.19 | 8.29.18 | 8.28.18 | 8.29.17 | 8.28.17 | 8.29.16 | 8.28.16 |
| PCIE:DRP33 | 8.29.31 | 8.28.31 | 8.29.30 | 8.28.30 | 8.29.29 | 8.28.29 | 8.29.28 | 8.28.28 | 8.29.27 | 8.28.27 | 8.29.26 | 8.28.26 | 8.29.25 | 8.28.25 | 8.29.24 | 8.28.24 |
| PCIE:DRP34 | 8.29.39 | 8.28.39 | 8.29.38 | 8.28.38 | 8.29.37 | 8.28.37 | 8.29.36 | 8.28.36 | 8.29.35 | 8.28.35 | 8.29.34 | 8.28.34 | 8.29.33 | 8.28.33 | 8.29.32 | 8.28.32 |
| PCIE:DRP35 | 8.29.47 | 8.28.47 | 8.29.46 | 8.28.46 | 8.29.45 | 8.28.45 | 8.29.44 | 8.28.44 | 8.29.43 | 8.28.43 | 8.29.42 | 8.28.42 | 8.29.41 | 8.28.41 | 8.29.40 | 8.28.40 |
| PCIE:DRP36 | 9.29.7 | 9.28.7 | 9.29.6 | 9.28.6 | 9.29.5 | 9.28.5 | 9.29.4 | 9.28.4 | 9.29.3 | 9.28.3 | 9.29.2 | 9.28.2 | 9.29.1 | 9.28.1 | 9.29.0 | 9.28.0 |
| PCIE:DRP37 | 9.29.15 | 9.28.15 | 9.29.14 | 9.28.14 | 9.29.13 | 9.28.13 | 9.29.12 | 9.28.12 | 9.29.11 | 9.28.11 | 9.29.10 | 9.28.10 | 9.29.9 | 9.28.9 | 9.29.8 | 9.28.8 |
| PCIE:DRP38 | 9.29.23 | 9.28.23 | 9.29.22 | 9.28.22 | 9.29.21 | 9.28.21 | 9.29.20 | 9.28.20 | 9.29.19 | 9.28.19 | 9.29.18 | 9.28.18 | 9.29.17 | 9.28.17 | 9.29.16 | 9.28.16 |
| PCIE:DRP39 | 9.29.31 | 9.28.31 | 9.29.30 | 9.28.30 | 9.29.29 | 9.28.29 | 9.29.28 | 9.28.28 | 9.29.27 | 9.28.27 | 9.29.26 | 9.28.26 | 9.29.25 | 9.28.25 | 9.29.24 | 9.28.24 |
| PCIE:DRP3A | 9.29.39 | 9.28.39 | 9.29.38 | 9.28.38 | 9.29.37 | 9.28.37 | 9.29.36 | 9.28.36 | 9.29.35 | 9.28.35 | 9.29.34 | 9.28.34 | 9.29.33 | 9.28.33 | 9.29.32 | 9.28.32 |
| PCIE:DRP3B | 9.29.47 | 9.28.47 | 9.29.46 | 9.28.46 | 9.29.45 | 9.28.45 | 9.29.44 | 9.28.44 | 9.29.43 | 9.28.43 | 9.29.42 | 9.28.42 | 9.29.41 | 9.28.41 | 9.29.40 | 9.28.40 |
| PCIE:DRP3C | 10.29.7 | 10.28.7 | 10.29.6 | 10.28.6 | 10.29.5 | 10.28.5 | 10.29.4 | 10.28.4 | 10.29.3 | 10.28.3 | 10.29.2 | 10.28.2 | 10.29.1 | 10.28.1 | 10.29.0 | 10.28.0 |
| PCIE:DRP3D | 10.29.15 | 10.28.15 | 10.29.14 | 10.28.14 | 10.29.13 | 10.28.13 | 10.29.12 | 10.28.12 | 10.29.11 | 10.28.11 | 10.29.10 | 10.28.10 | 10.29.9 | 10.28.9 | 10.29.8 | 10.28.8 |
| PCIE:DRP3E | 10.29.23 | 10.28.23 | 10.29.22 | 10.28.22 | 10.29.21 | 10.28.21 | 10.29.20 | 10.28.20 | 10.29.19 | 10.28.19 | 10.29.18 | 10.28.18 | 10.29.17 | 10.28.17 | 10.29.16 | 10.28.16 |
| PCIE:DRP3F | 10.29.31 | 10.28.31 | 10.29.30 | 10.28.30 | 10.29.29 | 10.28.29 | 10.29.28 | 10.28.28 | 10.29.27 | 10.28.27 | 10.29.26 | 10.28.26 | 10.29.25 | 10.28.25 | 10.29.24 | 10.28.24 |
| PCIE:DRP40 | 10.29.39 | 10.28.39 | 10.29.38 | 10.28.38 | 10.29.37 | 10.28.37 | 10.29.36 | 10.28.36 | 10.29.35 | 10.28.35 | 10.29.34 | 10.28.34 | 10.29.33 | 10.28.33 | 10.29.32 | 10.28.32 |
| PCIE:DRP41 | 10.29.47 | 10.28.47 | 10.29.46 | 10.28.46 | 10.29.45 | 10.28.45 | 10.29.44 | 10.28.44 | 10.29.43 | 10.28.43 | 10.29.42 | 10.28.42 | 10.29.41 | 10.28.41 | 10.29.40 | 10.28.40 |
| PCIE:DRP42 | 11.29.7 | 11.28.7 | 11.29.6 | 11.28.6 | 11.29.5 | 11.28.5 | 11.29.4 | 11.28.4 | 11.29.3 | 11.28.3 | 11.29.2 | 11.28.2 | 11.29.1 | 11.28.1 | 11.29.0 | 11.28.0 |
| PCIE:DRP43 | 11.29.15 | 11.28.15 | 11.29.14 | 11.28.14 | 11.29.13 | 11.28.13 | 11.29.12 | 11.28.12 | 11.29.11 | 11.28.11 | 11.29.10 | 11.28.10 | 11.29.9 | 11.28.9 | 11.29.8 | 11.28.8 |
| PCIE:DRP44 | 11.29.23 | 11.28.23 | 11.29.22 | 11.28.22 | 11.29.21 | 11.28.21 | 11.29.20 | 11.28.20 | 11.29.19 | 11.28.19 | 11.29.18 | 11.28.18 | 11.29.17 | 11.28.17 | 11.29.16 | 11.28.16 |
| PCIE:DRP45 | 11.29.31 | 11.28.31 | 11.29.30 | 11.28.30 | 11.29.29 | 11.28.29 | 11.29.28 | 11.28.28 | 11.29.27 | 11.28.27 | 11.29.26 | 11.28.26 | 11.29.25 | 11.28.25 | 11.29.24 | 11.28.24 |
| PCIE:DRP46 | 11.29.39 | 11.28.39 | 11.29.38 | 11.28.38 | 11.29.37 | 11.28.37 | 11.29.36 | 11.28.36 | 11.29.35 | 11.28.35 | 11.29.34 | 11.28.34 | 11.29.33 | 11.28.33 | 11.29.32 | 11.28.32 |
| PCIE:DRP47 | 11.29.47 | 11.28.47 | 11.29.46 | 11.28.46 | 11.29.45 | 11.28.45 | 11.29.44 | 11.28.44 | 11.29.43 | 11.28.43 | 11.29.42 | 11.28.42 | 11.29.41 | 11.28.41 | 11.29.40 | 11.28.40 |
| PCIE:DRP48 | 12.29.7 | 12.28.7 | 12.29.6 | 12.28.6 | 12.29.5 | 12.28.5 | 12.29.4 | 12.28.4 | 12.29.3 | 12.28.3 | 12.29.2 | 12.28.2 | 12.29.1 | 12.28.1 | 12.29.0 | 12.28.0 |
| PCIE:DRP49 | 12.29.15 | 12.28.15 | 12.29.14 | 12.28.14 | 12.29.13 | 12.28.13 | 12.29.12 | 12.28.12 | 12.29.11 | 12.28.11 | 12.29.10 | 12.28.10 | 12.29.9 | 12.28.9 | 12.29.8 | 12.28.8 |
| PCIE:DRP4A | 12.29.23 | 12.28.23 | 12.29.22 | 12.28.22 | 12.29.21 | 12.28.21 | 12.29.20 | 12.28.20 | 12.29.19 | 12.28.19 | 12.29.18 | 12.28.18 | 12.29.17 | 12.28.17 | 12.29.16 | 12.28.16 |
| PCIE:DRP4B | 12.29.31 | 12.28.31 | 12.29.30 | 12.28.30 | 12.29.29 | 12.28.29 | 12.29.28 | 12.28.28 | 12.29.27 | 12.28.27 | 12.29.26 | 12.28.26 | 12.29.25 | 12.28.25 | 12.29.24 | 12.28.24 |
| PCIE:DRP4C | 12.29.39 | 12.28.39 | 12.29.38 | 12.28.38 | 12.29.37 | 12.28.37 | 12.29.36 | 12.28.36 | 12.29.35 | 12.28.35 | 12.29.34 | 12.28.34 | 12.29.33 | 12.28.33 | 12.29.32 | 12.28.32 |
| PCIE:DRP4D | 12.29.47 | 12.28.47 | 12.29.46 | 12.28.46 | 12.29.45 | 12.28.45 | 12.29.44 | 12.28.44 | 12.29.43 | 12.28.43 | 12.29.42 | 12.28.42 | 12.29.41 | 12.28.41 | 12.29.40 | 12.28.40 |
| PCIE:DRP4E | 13.29.7 | 13.28.7 | 13.29.6 | 13.28.6 | 13.29.5 | 13.28.5 | 13.29.4 | 13.28.4 | 13.29.3 | 13.28.3 | 13.29.2 | 13.28.2 | 13.29.1 | 13.28.1 | 13.29.0 | 13.28.0 |
| PCIE:DRP4F | 13.29.15 | 13.28.15 | 13.29.14 | 13.28.14 | 13.29.13 | 13.28.13 | 13.29.12 | 13.28.12 | 13.29.11 | 13.28.11 | 13.29.10 | 13.28.10 | 13.29.9 | 13.28.9 | 13.29.8 | 13.28.8 |
| PCIE:DRP50 | 13.29.23 | 13.28.23 | 13.29.22 | 13.28.22 | 13.29.21 | 13.28.21 | 13.29.20 | 13.28.20 | 13.29.19 | 13.28.19 | 13.29.18 | 13.28.18 | 13.29.17 | 13.28.17 | 13.29.16 | 13.28.16 |
| PCIE:DRP51 | 13.29.31 | 13.28.31 | 13.29.30 | 13.28.30 | 13.29.29 | 13.28.29 | 13.29.28 | 13.28.28 | 13.29.27 | 13.28.27 | 13.29.26 | 13.28.26 | 13.29.25 | 13.28.25 | 13.29.24 | 13.28.24 |
| PCIE:DRP52 | 13.29.39 | 13.28.39 | 13.29.38 | 13.28.38 | 13.29.37 | 13.28.37 | 13.29.36 | 13.28.36 | 13.29.35 | 13.28.35 | 13.29.34 | 13.28.34 | 13.29.33 | 13.28.33 | 13.29.32 | 13.28.32 |
| PCIE:DRP53 | 13.29.47 | 13.28.47 | 13.29.46 | 13.28.46 | 13.29.45 | 13.28.45 | 13.29.44 | 13.28.44 | 13.29.43 | 13.28.43 | 13.29.42 | 13.28.42 | 13.29.41 | 13.28.41 | 13.29.40 | 13.28.40 |
| PCIE:DRP54 | 14.29.7 | 14.28.7 | 14.29.6 | 14.28.6 | 14.29.5 | 14.28.5 | 14.29.4 | 14.28.4 | 14.29.3 | 14.28.3 | 14.29.2 | 14.28.2 | 14.29.1 | 14.28.1 | 14.29.0 | 14.28.0 |
| PCIE:DRP55 | 14.29.15 | 14.28.15 | 14.29.14 | 14.28.14 | 14.29.13 | 14.28.13 | 14.29.12 | 14.28.12 | 14.29.11 | 14.28.11 | 14.29.10 | 14.28.10 | 14.29.9 | 14.28.9 | 14.29.8 | 14.28.8 |
| PCIE:DRP56 | 14.29.23 | 14.28.23 | 14.29.22 | 14.28.22 | 14.29.21 | 14.28.21 | 14.29.20 | 14.28.20 | 14.29.19 | 14.28.19 | 14.29.18 | 14.28.18 | 14.29.17 | 14.28.17 | 14.29.16 | 14.28.16 |
| PCIE:DRP57 | 14.29.31 | 14.28.31 | 14.29.30 | 14.28.30 | 14.29.29 | 14.28.29 | 14.29.28 | 14.28.28 | 14.29.27 | 14.28.27 | 14.29.26 | 14.28.26 | 14.29.25 | 14.28.25 | 14.29.24 | 14.28.24 |
| PCIE:DRP58 | 14.29.39 | 14.28.39 | 14.29.38 | 14.28.38 | 14.29.37 | 14.28.37 | 14.29.36 | 14.28.36 | 14.29.35 | 14.28.35 | 14.29.34 | 14.28.34 | 14.29.33 | 14.28.33 | 14.29.32 | 14.28.32 |
| PCIE:DRP59 | 14.29.47 | 14.28.47 | 14.29.46 | 14.28.46 | 14.29.45 | 14.28.45 | 14.29.44 | 14.28.44 | 14.29.43 | 14.28.43 | 14.29.42 | 14.28.42 | 14.29.41 | 14.28.41 | 14.29.40 | 14.28.40 |
| PCIE:DRP5A | 15.29.7 | 15.28.7 | 15.29.6 | 15.28.6 | 15.29.5 | 15.28.5 | 15.29.4 | 15.28.4 | 15.29.3 | 15.28.3 | 15.29.2 | 15.28.2 | 15.29.1 | 15.28.1 | 15.29.0 | 15.28.0 |
| PCIE:DRP5B | 15.29.15 | 15.28.15 | 15.29.14 | 15.28.14 | 15.29.13 | 15.28.13 | 15.29.12 | 15.28.12 | 15.29.11 | 15.28.11 | 15.29.10 | 15.28.10 | 15.29.9 | 15.28.9 | 15.29.8 | 15.28.8 |
| PCIE:DRP5C | 15.29.23 | 15.28.23 | 15.29.22 | 15.28.22 | 15.29.21 | 15.28.21 | 15.29.20 | 15.28.20 | 15.29.19 | 15.28.19 | 15.29.18 | 15.28.18 | 15.29.17 | 15.28.17 | 15.29.16 | 15.28.16 |
| PCIE:DRP5D | 15.29.31 | 15.28.31 | 15.29.30 | 15.28.30 | 15.29.29 | 15.28.29 | 15.29.28 | 15.28.28 | 15.29.27 | 15.28.27 | 15.29.26 | 15.28.26 | 15.29.25 | 15.28.25 | 15.29.24 | 15.28.24 |
| PCIE:DRP5E | 15.29.39 | 15.28.39 | 15.29.38 | 15.28.38 | 15.29.37 | 15.28.37 | 15.29.36 | 15.28.36 | 15.29.35 | 15.28.35 | 15.29.34 | 15.28.34 | 15.29.33 | 15.28.33 | 15.29.32 | 15.28.32 |
| PCIE:DRP5F | 15.29.47 | 15.28.47 | 15.29.46 | 15.28.46 | 15.29.45 | 15.28.45 | 15.29.44 | 15.28.44 | 15.29.43 | 15.28.43 | 15.29.42 | 15.28.42 | 15.29.41 | 15.28.41 | 15.29.40 | 15.28.40 |
| PCIE:DRP60 | 16.29.7 | 16.28.7 | 16.29.6 | 16.28.6 | 16.29.5 | 16.28.5 | 16.29.4 | 16.28.4 | 16.29.3 | 16.28.3 | 16.29.2 | 16.28.2 | 16.29.1 | 16.28.1 | 16.29.0 | 16.28.0 |
| PCIE:DRP61 | 16.29.15 | 16.28.15 | 16.29.14 | 16.28.14 | 16.29.13 | 16.28.13 | 16.29.12 | 16.28.12 | 16.29.11 | 16.28.11 | 16.29.10 | 16.28.10 | 16.29.9 | 16.28.9 | 16.29.8 | 16.28.8 |
| PCIE:DRP62 | 16.29.23 | 16.28.23 | 16.29.22 | 16.28.22 | 16.29.21 | 16.28.21 | 16.29.20 | 16.28.20 | 16.29.19 | 16.28.19 | 16.29.18 | 16.28.18 | 16.29.17 | 16.28.17 | 16.29.16 | 16.28.16 |
| PCIE:DRP63 | 16.29.31 | 16.28.31 | 16.29.30 | 16.28.30 | 16.29.29 | 16.28.29 | 16.29.28 | 16.28.28 | 16.29.27 | 16.28.27 | 16.29.26 | 16.28.26 | 16.29.25 | 16.28.25 | 16.29.24 | 16.28.24 |
| PCIE:DRP64 | 16.29.39 | 16.28.39 | 16.29.38 | 16.28.38 | 16.29.37 | 16.28.37 | 16.29.36 | 16.28.36 | 16.29.35 | 16.28.35 | 16.29.34 | 16.28.34 | 16.29.33 | 16.28.33 | 16.29.32 | 16.28.32 |
| PCIE:DRP65 | 16.29.47 | 16.28.47 | 16.29.46 | 16.28.46 | 16.29.45 | 16.28.45 | 16.29.44 | 16.28.44 | 16.29.43 | 16.28.43 | 16.29.42 | 16.28.42 | 16.29.41 | 16.28.41 | 16.29.40 | 16.28.40 |
| PCIE:DRP66 | 17.29.7 | 17.28.7 | 17.29.6 | 17.28.6 | 17.29.5 | 17.28.5 | 17.29.4 | 17.28.4 | 17.29.3 | 17.28.3 | 17.29.2 | 17.28.2 | 17.29.1 | 17.28.1 | 17.29.0 | 17.28.0 |
| PCIE:DRP67 | 17.29.15 | 17.28.15 | 17.29.14 | 17.28.14 | 17.29.13 | 17.28.13 | 17.29.12 | 17.28.12 | 17.29.11 | 17.28.11 | 17.29.10 | 17.28.10 | 17.29.9 | 17.28.9 | 17.29.8 | 17.28.8 |
| PCIE:DRP68 | 17.29.23 | 17.28.23 | 17.29.22 | 17.28.22 | 17.29.21 | 17.28.21 | 17.29.20 | 17.28.20 | 17.29.19 | 17.28.19 | 17.29.18 | 17.28.18 | 17.29.17 | 17.28.17 | 17.29.16 | 17.28.16 |
| PCIE:DRP69 | 17.29.31 | 17.28.31 | 17.29.30 | 17.28.30 | 17.29.29 | 17.28.29 | 17.29.28 | 17.28.28 | 17.29.27 | 17.28.27 | 17.29.26 | 17.28.26 | 17.29.25 | 17.28.25 | 17.29.24 | 17.28.24 |
| PCIE:DRP6A | 17.29.39 | 17.28.39 | 17.29.38 | 17.28.38 | 17.29.37 | 17.28.37 | 17.29.36 | 17.28.36 | 17.29.35 | 17.28.35 | 17.29.34 | 17.28.34 | 17.29.33 | 17.28.33 | 17.29.32 | 17.28.32 |
| PCIE:DRP6B | 17.29.47 | 17.28.47 | 17.29.46 | 17.28.46 | 17.29.45 | 17.28.45 | 17.29.44 | 17.28.44 | 17.29.43 | 17.28.43 | 17.29.42 | 17.28.42 | 17.29.41 | 17.28.41 | 17.29.40 | 17.28.40 |
| PCIE:DRP6C | 18.29.7 | 18.28.7 | 18.29.6 | 18.28.6 | 18.29.5 | 18.28.5 | 18.29.4 | 18.28.4 | 18.29.3 | 18.28.3 | 18.29.2 | 18.28.2 | 18.29.1 | 18.28.1 | 18.29.0 | 18.28.0 |
| PCIE:DRP6D | 18.29.15 | 18.28.15 | 18.29.14 | 18.28.14 | 18.29.13 | 18.28.13 | 18.29.12 | 18.28.12 | 18.29.11 | 18.28.11 | 18.29.10 | 18.28.10 | 18.29.9 | 18.28.9 | 18.29.8 | 18.28.8 |
| PCIE:DRP6E | 18.29.23 | 18.28.23 | 18.29.22 | 18.28.22 | 18.29.21 | 18.28.21 | 18.29.20 | 18.28.20 | 18.29.19 | 18.28.19 | 18.29.18 | 18.28.18 | 18.29.17 | 18.28.17 | 18.29.16 | 18.28.16 |
| PCIE:DRP6F | 18.29.31 | 18.28.31 | 18.29.30 | 18.28.30 | 18.29.29 | 18.28.29 | 18.29.28 | 18.28.28 | 18.29.27 | 18.28.27 | 18.29.26 | 18.28.26 | 18.29.25 | 18.28.25 | 18.29.24 | 18.28.24 |
| PCIE:DRP70 | 18.29.39 | 18.28.39 | 18.29.38 | 18.28.38 | 18.29.37 | 18.28.37 | 18.29.36 | 18.28.36 | 18.29.35 | 18.28.35 | 18.29.34 | 18.28.34 | 18.29.33 | 18.28.33 | 18.29.32 | 18.28.32 |
| PCIE:DRP71 | 18.29.47 | 18.28.47 | 18.29.46 | 18.28.46 | 18.29.45 | 18.28.45 | 18.29.44 | 18.28.44 | 18.29.43 | 18.28.43 | 18.29.42 | 18.28.42 | 18.29.41 | 18.28.41 | 18.29.40 | 18.28.40 |
| PCIE:DRP72 | 19.29.7 | 19.28.7 | 19.29.6 | 19.28.6 | 19.29.5 | 19.28.5 | 19.29.4 | 19.28.4 | 19.29.3 | 19.28.3 | 19.29.2 | 19.28.2 | 19.29.1 | 19.28.1 | 19.29.0 | 19.28.0 |
| PCIE:DRP73 | 19.29.15 | 19.28.15 | 19.29.14 | 19.28.14 | 19.29.13 | 19.28.13 | 19.29.12 | 19.28.12 | 19.29.11 | 19.28.11 | 19.29.10 | 19.28.10 | 19.29.9 | 19.28.9 | 19.29.8 | 19.28.8 |
| PCIE:DRP74 | 19.29.23 | 19.28.23 | 19.29.22 | 19.28.22 | 19.29.21 | 19.28.21 | 19.29.20 | 19.28.20 | 19.29.19 | 19.28.19 | 19.29.18 | 19.28.18 | 19.29.17 | 19.28.17 | 19.29.16 | 19.28.16 |
| PCIE:DRP75 | 19.29.31 | 19.28.31 | 19.29.30 | 19.28.30 | 19.29.29 | 19.28.29 | 19.29.28 | 19.28.28 | 19.29.27 | 19.28.27 | 19.29.26 | 19.28.26 | 19.29.25 | 19.28.25 | 19.29.24 | 19.28.24 |
| PCIE:DRP76 | 19.29.39 | 19.28.39 | 19.29.38 | 19.28.38 | 19.29.37 | 19.28.37 | 19.29.36 | 19.28.36 | 19.29.35 | 19.28.35 | 19.29.34 | 19.28.34 | 19.29.33 | 19.28.33 | 19.29.32 | 19.28.32 |
| PCIE:DRP77 | 19.29.47 | 19.28.47 | 19.29.46 | 19.28.46 | 19.29.45 | 19.28.45 | 19.29.44 | 19.28.44 | 19.29.43 | 19.28.43 | 19.29.42 | 19.28.42 | 19.29.41 | 19.28.41 | 19.29.40 | 19.28.40 |
| PCIE:DRP78 | 20.29.7 | 20.28.7 | 20.29.6 | 20.28.6 | 20.29.5 | 20.28.5 | 20.29.4 | 20.28.4 | 20.29.3 | 20.28.3 | 20.29.2 | 20.28.2 | 20.29.1 | 20.28.1 | 20.29.0 | 20.28.0 |
| PCIE:DRP79 | 20.29.15 | 20.28.15 | 20.29.14 | 20.28.14 | 20.29.13 | 20.28.13 | 20.29.12 | 20.28.12 | 20.29.11 | 20.28.11 | 20.29.10 | 20.28.10 | 20.29.9 | 20.28.9 | 20.29.8 | 20.28.8 |
| PCIE:DRP7A | 20.29.23 | 20.28.23 | 20.29.22 | 20.28.22 | 20.29.21 | 20.28.21 | 20.29.20 | 20.28.20 | 20.29.19 | 20.28.19 | 20.29.18 | 20.28.18 | 20.29.17 | 20.28.17 | 20.29.16 | 20.28.16 |
| PCIE:DRP7B | 20.29.31 | 20.28.31 | 20.29.30 | 20.28.30 | 20.29.29 | 20.28.29 | 20.29.28 | 20.28.28 | 20.29.27 | 20.28.27 | 20.29.26 | 20.28.26 | 20.29.25 | 20.28.25 | 20.29.24 | 20.28.24 |
| PCIE:DRP7C | 20.29.39 | 20.28.39 | 20.29.38 | 20.28.38 | 20.29.37 | 20.28.37 | 20.29.36 | 20.28.36 | 20.29.35 | 20.28.35 | 20.29.34 | 20.28.34 | 20.29.33 | 20.28.33 | 20.29.32 | 20.28.32 |
| PCIE:DRP7D | 20.29.47 | 20.28.47 | 20.29.46 | 20.28.46 | 20.29.45 | 20.28.45 | 20.29.44 | 20.28.44 | 20.29.43 | 20.28.43 | 20.29.42 | 20.28.42 | 20.29.41 | 20.28.41 | 20.29.40 | 20.28.40 |
| PCIE:DRP7E | 21.29.7 | 21.28.7 | 21.29.6 | 21.28.6 | 21.29.5 | 21.28.5 | 21.29.4 | 21.28.4 | 21.29.3 | 21.28.3 | 21.29.2 | 21.28.2 | 21.29.1 | 21.28.1 | 21.29.0 | 21.28.0 |
| PCIE:DRP7F | 21.29.15 | 21.28.15 | 21.29.14 | 21.28.14 | 21.29.13 | 21.28.13 | 21.29.12 | 21.28.12 | 21.29.11 | 21.28.11 | 21.29.10 | 21.28.10 | 21.29.9 | 21.28.9 | 21.29.8 | 21.28.8 |
| PCIE:DRP80 | 21.29.23 | 21.28.23 | 21.29.22 | 21.28.22 | 21.29.21 | 21.28.21 | 21.29.20 | 21.28.20 | 21.29.19 | 21.28.19 | 21.29.18 | 21.28.18 | 21.29.17 | 21.28.17 | 21.29.16 | 21.28.16 |
| PCIE:DRP81 | 21.29.31 | 21.28.31 | 21.29.30 | 21.28.30 | 21.29.29 | 21.28.29 | 21.29.28 | 21.28.28 | 21.29.27 | 21.28.27 | 21.29.26 | 21.28.26 | 21.29.25 | 21.28.25 | 21.29.24 | 21.28.24 |
| PCIE:DRP82 | 21.29.39 | 21.28.39 | 21.29.38 | 21.28.38 | 21.29.37 | 21.28.37 | 21.29.36 | 21.28.36 | 21.29.35 | 21.28.35 | 21.29.34 | 21.28.34 | 21.29.33 | 21.28.33 | 21.29.32 | 21.28.32 |
| PCIE:DRP83 | 21.29.47 | 21.28.47 | 21.29.46 | 21.28.46 | 21.29.45 | 21.28.45 | 21.29.44 | 21.28.44 | 21.29.43 | 21.28.43 | 21.29.42 | 21.28.42 | 21.29.41 | 21.28.41 | 21.29.40 | 21.28.40 |
| PCIE:DRP84 | 22.29.7 | 22.28.7 | 22.29.6 | 22.28.6 | 22.29.5 | 22.28.5 | 22.29.4 | 22.28.4 | 22.29.3 | 22.28.3 | 22.29.2 | 22.28.2 | 22.29.1 | 22.28.1 | 22.29.0 | 22.28.0 |
| PCIE:DRP85 | 22.29.15 | 22.28.15 | 22.29.14 | 22.28.14 | 22.29.13 | 22.28.13 | 22.29.12 | 22.28.12 | 22.29.11 | 22.28.11 | 22.29.10 | 22.28.10 | 22.29.9 | 22.28.9 | 22.29.8 | 22.28.8 |
| PCIE:DRP86 | 22.29.23 | 22.28.23 | 22.29.22 | 22.28.22 | 22.29.21 | 22.28.21 | 22.29.20 | 22.28.20 | 22.29.19 | 22.28.19 | 22.29.18 | 22.28.18 | 22.29.17 | 22.28.17 | 22.29.16 | 22.28.16 |
| PCIE:DRP87 | 22.29.31 | 22.28.31 | 22.29.30 | 22.28.30 | 22.29.29 | 22.28.29 | 22.29.28 | 22.28.28 | 22.29.27 | 22.28.27 | 22.29.26 | 22.28.26 | 22.29.25 | 22.28.25 | 22.29.24 | 22.28.24 |
| PCIE:DRP88 | 22.29.39 | 22.28.39 | 22.29.38 | 22.28.38 | 22.29.37 | 22.28.37 | 22.29.36 | 22.28.36 | 22.29.35 | 22.28.35 | 22.29.34 | 22.28.34 | 22.29.33 | 22.28.33 | 22.29.32 | 22.28.32 |
| PCIE:DRP89 | 22.29.47 | 22.28.47 | 22.29.46 | 22.28.46 | 22.29.45 | 22.28.45 | 22.29.44 | 22.28.44 | 22.29.43 | 22.28.43 | 22.29.42 | 22.28.42 | 22.29.41 | 22.28.41 | 22.29.40 | 22.28.40 |
| PCIE:DRP8A | 23.29.7 | 23.28.7 | 23.29.6 | 23.28.6 | 23.29.5 | 23.28.5 | 23.29.4 | 23.28.4 | 23.29.3 | 23.28.3 | 23.29.2 | 23.28.2 | 23.29.1 | 23.28.1 | 23.29.0 | 23.28.0 |
| PCIE:DRP8B | 23.29.15 | 23.28.15 | 23.29.14 | 23.28.14 | 23.29.13 | 23.28.13 | 23.29.12 | 23.28.12 | 23.29.11 | 23.28.11 | 23.29.10 | 23.28.10 | 23.29.9 | 23.28.9 | 23.29.8 | 23.28.8 |
| PCIE:DRP8C | 23.29.23 | 23.28.23 | 23.29.22 | 23.28.22 | 23.29.21 | 23.28.21 | 23.29.20 | 23.28.20 | 23.29.19 | 23.28.19 | 23.29.18 | 23.28.18 | 23.29.17 | 23.28.17 | 23.29.16 | 23.28.16 |
| PCIE:DRP8D | 23.29.31 | 23.28.31 | 23.29.30 | 23.28.30 | 23.29.29 | 23.28.29 | 23.29.28 | 23.28.28 | 23.29.27 | 23.28.27 | 23.29.26 | 23.28.26 | 23.29.25 | 23.28.25 | 23.29.24 | 23.28.24 |
| PCIE:DRP8E | 23.29.39 | 23.28.39 | 23.29.38 | 23.28.38 | 23.29.37 | 23.28.37 | 23.29.36 | 23.28.36 | 23.29.35 | 23.28.35 | 23.29.34 | 23.28.34 | 23.29.33 | 23.28.33 | 23.29.32 | 23.28.32 |
| PCIE:DRP8F | 23.29.47 | 23.28.47 | 23.29.46 | 23.28.46 | 23.29.45 | 23.28.45 | 23.29.44 | 23.28.44 | 23.29.43 | 23.28.43 | 23.29.42 | 23.28.42 | 23.29.41 | 23.28.41 | 23.29.40 | 23.28.40 |
| PCIE:DRP90 | 24.29.7 | 24.28.7 | 24.29.6 | 24.28.6 | 24.29.5 | 24.28.5 | 24.29.4 | 24.28.4 | 24.29.3 | 24.28.3 | 24.29.2 | 24.28.2 | 24.29.1 | 24.28.1 | 24.29.0 | 24.28.0 |
| PCIE:DRP91 | 24.29.15 | 24.28.15 | 24.29.14 | 24.28.14 | 24.29.13 | 24.28.13 | 24.29.12 | 24.28.12 | 24.29.11 | 24.28.11 | 24.29.10 | 24.28.10 | 24.29.9 | 24.28.9 | 24.29.8 | 24.28.8 |
| PCIE:DRP92 | 24.29.23 | 24.28.23 | 24.29.22 | 24.28.22 | 24.29.21 | 24.28.21 | 24.29.20 | 24.28.20 | 24.29.19 | 24.28.19 | 24.29.18 | 24.28.18 | 24.29.17 | 24.28.17 | 24.29.16 | 24.28.16 |
| PCIE:DRP93 | 24.29.31 | 24.28.31 | 24.29.30 | 24.28.30 | 24.29.29 | 24.28.29 | 24.29.28 | 24.28.28 | 24.29.27 | 24.28.27 | 24.29.26 | 24.28.26 | 24.29.25 | 24.28.25 | 24.29.24 | 24.28.24 |
| PCIE:DRP94 | 24.29.39 | 24.28.39 | 24.29.38 | 24.28.38 | 24.29.37 | 24.28.37 | 24.29.36 | 24.28.36 | 24.29.35 | 24.28.35 | 24.29.34 | 24.28.34 | 24.29.33 | 24.28.33 | 24.29.32 | 24.28.32 |
| PCIE:DRP95 | 24.29.47 | 24.28.47 | 24.29.46 | 24.28.46 | 24.29.45 | 24.28.45 | 24.29.44 | 24.28.44 | 24.29.43 | 24.28.43 | 24.29.42 | 24.28.42 | 24.29.41 | 24.28.41 | 24.29.40 | 24.28.40 |
| PCIE:DSN_CAP_ID | 5.29.7 | 5.28.7 | 5.29.6 | 5.28.6 | 5.29.5 | 5.28.5 | 5.29.4 | 5.28.4 | 5.29.3 | 5.28.3 | 5.29.2 | 5.28.2 | 5.29.1 | 5.28.1 | 5.29.0 | 5.28.0 |
| PCIE:RBAR_CAP_ID | 10.29.23 | 10.28.23 | 10.29.22 | 10.28.22 | 10.29.21 | 10.28.21 | 10.29.20 | 10.28.20 | 10.29.19 | 10.28.19 | 10.29.18 | 10.28.18 | 10.29.17 | 10.28.17 | 10.29.16 | 10.28.16 |
| PCIE:VC_CAP_ID | 14.29.7 | 14.28.7 | 14.29.6 | 14.28.6 | 14.29.5 | 14.28.5 | 14.29.4 | 14.28.4 | 14.29.3 | 14.28.3 | 14.29.2 | 14.28.2 | 14.29.1 | 14.28.1 | 14.29.0 | 14.28.0 |
| PCIE:VSEC_CAP_HDR_ID | 14.29.23 | 14.28.23 | 14.29.22 | 14.28.22 | 14.29.21 | 14.28.21 | 14.29.20 | 14.28.20 | 14.29.19 | 14.28.19 | 14.29.18 | 14.28.18 | 14.29.17 | 14.28.17 | 14.29.16 | 14.28.16 |
| PCIE:VSEC_CAP_ID | 14.29.39 | 14.28.39 | 14.29.38 | 14.28.38 | 14.29.37 | 14.28.37 | 14.29.36 | 14.28.36 | 14.29.35 | 14.28.35 | 14.29.34 | 14.28.34 | 14.29.33 | 14.28.33 | 14.29.32 | 14.28.32 |
| non-inverted | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:AER_CAP_OPTIONAL_ERR_SUPPORT | 1.29.3 | 1.28.3 | 1.29.2 | 1.28.2 | 1.29.1 | 1.28.1 | 1.29.0 | 1.28.0 | 0.29.47 | 0.28.47 | 0.29.46 | 0.28.46 | 0.29.45 | 0.28.45 | 0.29.44 | 0.28.44 | 0.29.43 | 0.28.43 | 0.29.42 | 0.28.42 | 0.29.41 | 0.28.41 | 0.29.40 | 0.28.40 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:CLASS_CODE | 4.29.11 | 4.28.11 | 4.29.10 | 4.28.10 | 4.29.9 | 4.28.9 | 4.29.8 | 4.28.8 | 4.29.7 | 4.28.7 | 4.29.6 | 4.28.6 | 4.29.5 | 4.28.5 | 4.29.4 | 4.28.4 | 4.29.3 | 4.28.3 | 4.29.2 | 4.28.2 | 4.29.1 | 4.28.1 | 4.29.0 | 4.28.0 |
| non-inverted | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:AER_CAP_VERSION | 0.28.18 | 0.29.17 | 0.28.17 | 0.29.16 |
|---|---|---|---|---|
| PCIE:CPL_TIMEOUT_RANGES_SUPPORTED | 4.29.14 | 4.28.14 | 4.29.13 | 4.28.13 |
| PCIE:DSN_CAP_VERSION | 5.29.17 | 5.28.17 | 5.29.16 | 5.28.16 |
| PCIE:LINK_CAP_MAX_LINK_SPEED | 6.29.14 | 6.28.14 | 6.29.13 | 6.28.13 |
| PCIE:LINK_CTRL2_TARGET_LINK_SPEED | 6.29.19 | 6.28.19 | 6.29.18 | 6.28.18 |
| PCIE:PCIE_CAP_CAPABILITY_VERSION | 8.29.17 | 8.28.17 | 8.29.16 | 8.28.16 |
| PCIE:PCIE_CAP_DEVICE_PORT_TYPE | 8.29.19 | 8.28.19 | 8.29.18 | 8.28.18 |
| PCIE:PCIE_REVISION | 8.29.27 | 8.28.27 | 8.29.26 | 8.28.26 |
| PCIE:RBAR_CAP_VERSION | 10.29.25 | 10.28.25 | 10.29.24 | 10.28.24 |
| PCIE:VC_CAP_VERSION | 17.28.10 | 17.29.9 | 17.28.9 | 17.29.8 |
| PCIE:VSEC_CAP_HDR_REVISION | 14.29.31 | 14.28.31 | 14.29.30 | 14.28.30 |
| PCIE:VSEC_CAP_VERSION | 15.29.1 | 15.28.1 | 15.29.0 | 15.28.0 |
| non-inverted | [3] | [2] | [1] | [0] |
| PCIE:BAR0 | 1.29.23 | 1.28.23 | 1.29.22 | 1.28.22 | 1.29.21 | 1.28.21 | 1.29.20 | 1.28.20 | 1.29.19 | 1.28.19 | 1.29.18 | 1.28.18 | 1.29.17 | 1.28.17 | 1.29.16 | 1.28.16 | 1.29.15 | 1.28.15 | 1.29.14 | 1.28.14 | 1.29.13 | 1.28.13 | 1.29.12 | 1.28.12 | 1.29.11 | 1.28.11 | 1.29.10 | 1.28.10 | 1.29.9 | 1.28.9 | 1.29.8 | 1.28.8 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:BAR1 | 1.29.39 | 1.28.39 | 1.29.38 | 1.28.38 | 1.29.37 | 1.28.37 | 1.29.36 | 1.28.36 | 1.29.35 | 1.28.35 | 1.29.34 | 1.28.34 | 1.29.33 | 1.28.33 | 1.29.32 | 1.28.32 | 1.29.31 | 1.28.31 | 1.29.30 | 1.28.30 | 1.29.29 | 1.28.29 | 1.29.28 | 1.28.28 | 1.29.27 | 1.28.27 | 1.29.26 | 1.28.26 | 1.29.25 | 1.28.25 | 1.29.24 | 1.28.24 |
| PCIE:BAR2 | 2.29.7 | 2.28.7 | 2.29.6 | 2.28.6 | 2.29.5 | 2.28.5 | 2.29.4 | 2.28.4 | 2.29.3 | 2.28.3 | 2.29.2 | 2.28.2 | 2.29.1 | 2.28.1 | 2.29.0 | 2.28.0 | 1.29.47 | 1.28.47 | 1.29.46 | 1.28.46 | 1.29.45 | 1.28.45 | 1.29.44 | 1.28.44 | 1.29.43 | 1.28.43 | 1.29.42 | 1.28.42 | 1.29.41 | 1.28.41 | 1.29.40 | 1.28.40 |
| PCIE:BAR3 | 2.29.23 | 2.28.23 | 2.29.22 | 2.28.22 | 2.29.21 | 2.28.21 | 2.29.20 | 2.28.20 | 2.29.19 | 2.28.19 | 2.29.18 | 2.28.18 | 2.29.17 | 2.28.17 | 2.29.16 | 2.28.16 | 2.29.15 | 2.28.15 | 2.29.14 | 2.28.14 | 2.29.13 | 2.28.13 | 2.29.12 | 2.28.12 | 2.29.11 | 2.28.11 | 2.29.10 | 2.28.10 | 2.29.9 | 2.28.9 | 2.29.8 | 2.28.8 |
| PCIE:BAR4 | 2.29.39 | 2.28.39 | 2.29.38 | 2.28.38 | 2.29.37 | 2.28.37 | 2.29.36 | 2.28.36 | 2.29.35 | 2.28.35 | 2.29.34 | 2.28.34 | 2.29.33 | 2.28.33 | 2.29.32 | 2.28.32 | 2.29.31 | 2.28.31 | 2.29.30 | 2.28.30 | 2.29.29 | 2.28.29 | 2.29.28 | 2.28.28 | 2.29.27 | 2.28.27 | 2.29.26 | 2.28.26 | 2.29.25 | 2.28.25 | 2.29.24 | 2.28.24 |
| PCIE:BAR5 | 3.29.7 | 3.28.7 | 3.29.6 | 3.28.6 | 3.29.5 | 3.28.5 | 3.29.4 | 3.28.4 | 3.29.3 | 3.28.3 | 3.29.2 | 3.28.2 | 3.29.1 | 3.28.1 | 3.29.0 | 3.28.0 | 2.29.47 | 2.28.47 | 2.29.46 | 2.28.46 | 2.29.45 | 2.28.45 | 2.29.44 | 2.28.44 | 2.29.43 | 2.28.43 | 2.29.42 | 2.28.42 | 2.29.41 | 2.28.41 | 2.29.40 | 2.28.40 |
| PCIE:CARDBUS_CIS_POINTER | 3.29.47 | 3.28.47 | 3.29.46 | 3.28.46 | 3.29.45 | 3.28.45 | 3.29.44 | 3.28.44 | 3.29.43 | 3.28.43 | 3.29.42 | 3.28.42 | 3.29.41 | 3.28.41 | 3.29.40 | 3.28.40 | 3.29.39 | 3.28.39 | 3.29.38 | 3.28.38 | 3.29.37 | 3.28.37 | 3.29.36 | 3.28.36 | 3.29.35 | 3.28.35 | 3.29.34 | 3.28.34 | 3.29.33 | 3.28.33 | 3.29.32 | 3.28.32 |
| PCIE:EXPANSION_ROM | 3.29.23 | 3.28.23 | 3.29.22 | 3.28.22 | 3.29.21 | 3.28.21 | 3.29.20 | 3.28.20 | 3.29.19 | 3.28.19 | 3.29.18 | 3.28.18 | 3.29.17 | 3.28.17 | 3.29.16 | 3.28.16 | 3.29.15 | 3.28.15 | 3.29.14 | 3.28.14 | 3.29.13 | 3.28.13 | 3.29.12 | 3.28.12 | 3.29.11 | 3.28.11 | 3.29.10 | 3.28.10 | 3.29.9 | 3.28.9 | 3.29.8 | 3.28.8 |
| PCIE:RBAR_CAP_SUP0 | 10.29.47 | 10.28.47 | 10.29.46 | 10.28.46 | 10.29.45 | 10.28.45 | 10.29.44 | 10.28.44 | 10.29.43 | 10.28.43 | 10.29.42 | 10.28.42 | 10.29.41 | 10.28.41 | 10.29.40 | 10.28.40 | 10.29.39 | 10.28.39 | 10.29.38 | 10.28.38 | 10.29.37 | 10.28.37 | 10.29.36 | 10.28.36 | 10.29.35 | 10.28.35 | 10.29.34 | 10.28.34 | 10.29.33 | 10.28.33 | 10.29.32 | 10.28.32 |
| PCIE:RBAR_CAP_SUP1 | 11.29.15 | 11.28.15 | 11.29.14 | 11.28.14 | 11.29.13 | 11.28.13 | 11.29.12 | 11.28.12 | 11.29.11 | 11.28.11 | 11.29.10 | 11.28.10 | 11.29.9 | 11.28.9 | 11.29.8 | 11.28.8 | 11.29.7 | 11.28.7 | 11.29.6 | 11.28.6 | 11.29.5 | 11.28.5 | 11.29.4 | 11.28.4 | 11.29.3 | 11.28.3 | 11.29.2 | 11.28.2 | 11.29.1 | 11.28.1 | 11.29.0 | 11.28.0 |
| PCIE:RBAR_CAP_SUP2 | 11.29.31 | 11.28.31 | 11.29.30 | 11.28.30 | 11.29.29 | 11.28.29 | 11.29.28 | 11.28.28 | 11.29.27 | 11.28.27 | 11.29.26 | 11.28.26 | 11.29.25 | 11.28.25 | 11.29.24 | 11.28.24 | 11.29.23 | 11.28.23 | 11.29.22 | 11.28.22 | 11.29.21 | 11.28.21 | 11.29.20 | 11.28.20 | 11.29.19 | 11.28.19 | 11.29.18 | 11.28.18 | 11.29.17 | 11.28.17 | 11.29.16 | 11.28.16 |
| PCIE:RBAR_CAP_SUP3 | 11.29.47 | 11.28.47 | 11.29.46 | 11.28.46 | 11.29.45 | 11.28.45 | 11.29.44 | 11.28.44 | 11.29.43 | 11.28.43 | 11.29.42 | 11.28.42 | 11.29.41 | 11.28.41 | 11.29.40 | 11.28.40 | 11.29.39 | 11.28.39 | 11.29.38 | 11.28.38 | 11.29.37 | 11.28.37 | 11.29.36 | 11.28.36 | 11.29.35 | 11.28.35 | 11.29.34 | 11.28.34 | 11.29.33 | 11.28.33 | 11.29.32 | 11.28.32 |
| PCIE:RBAR_CAP_SUP4 | 12.29.15 | 12.28.15 | 12.29.14 | 12.28.14 | 12.29.13 | 12.28.13 | 12.29.12 | 12.28.12 | 12.29.11 | 12.28.11 | 12.29.10 | 12.28.10 | 12.29.9 | 12.28.9 | 12.29.8 | 12.28.8 | 12.29.7 | 12.28.7 | 12.29.6 | 12.28.6 | 12.29.5 | 12.28.5 | 12.29.4 | 12.28.4 | 12.29.3 | 12.28.3 | 12.29.2 | 12.28.2 | 12.29.1 | 12.28.1 | 12.29.0 | 12.28.0 |
| PCIE:RBAR_CAP_SUP5 | 12.29.31 | 12.28.31 | 12.29.30 | 12.28.30 | 12.29.29 | 12.28.29 | 12.29.28 | 12.28.28 | 12.29.27 | 12.28.27 | 12.29.26 | 12.28.26 | 12.29.25 | 12.28.25 | 12.29.24 | 12.28.24 | 12.29.23 | 12.28.23 | 12.29.22 | 12.28.22 | 12.29.21 | 12.28.21 | 12.29.20 | 12.28.20 | 12.29.19 | 12.28.19 | 12.29.18 | 12.28.18 | 12.29.17 | 12.28.17 | 12.29.16 | 12.28.16 |
| PCIE:SPARE_WORD0 | 19.29.15 | 19.28.15 | 19.29.14 | 19.28.14 | 19.29.13 | 19.28.13 | 19.29.12 | 19.28.12 | 19.29.11 | 19.28.11 | 19.29.10 | 19.28.10 | 19.29.9 | 19.28.9 | 19.29.8 | 19.28.8 | 19.29.7 | 19.28.7 | 19.29.6 | 19.28.6 | 19.29.5 | 19.28.5 | 19.29.4 | 19.28.4 | 19.29.3 | 19.28.3 | 19.29.2 | 19.28.2 | 19.29.1 | 19.28.1 | 19.29.0 | 19.28.0 |
| PCIE:SPARE_WORD1 | 19.29.31 | 19.28.31 | 19.29.30 | 19.28.30 | 19.29.29 | 19.28.29 | 19.29.28 | 19.28.28 | 19.29.27 | 19.28.27 | 19.29.26 | 19.28.26 | 19.29.25 | 19.28.25 | 19.29.24 | 19.28.24 | 19.29.23 | 19.28.23 | 19.29.22 | 19.28.22 | 19.29.21 | 19.28.21 | 19.29.20 | 19.28.20 | 19.29.19 | 19.28.19 | 19.29.18 | 19.28.18 | 19.29.17 | 19.28.17 | 19.29.16 | 19.28.16 |
| PCIE:SPARE_WORD2 | 19.29.47 | 19.28.47 | 19.29.46 | 19.28.46 | 19.29.45 | 19.28.45 | 19.29.44 | 19.28.44 | 19.29.43 | 19.28.43 | 19.29.42 | 19.28.42 | 19.29.41 | 19.28.41 | 19.29.40 | 19.28.40 | 19.29.39 | 19.28.39 | 19.29.38 | 19.28.38 | 19.29.37 | 19.28.37 | 19.29.36 | 19.28.36 | 19.29.35 | 19.28.35 | 19.29.34 | 19.28.34 | 19.29.33 | 19.28.33 | 19.29.32 | 19.28.32 |
| PCIE:SPARE_WORD3 | 20.29.15 | 20.28.15 | 20.29.14 | 20.28.14 | 20.29.13 | 20.28.13 | 20.29.12 | 20.28.12 | 20.29.11 | 20.28.11 | 20.29.10 | 20.28.10 | 20.29.9 | 20.28.9 | 20.29.8 | 20.28.8 | 20.29.7 | 20.28.7 | 20.29.6 | 20.28.6 | 20.29.5 | 20.28.5 | 20.29.4 | 20.28.4 | 20.29.3 | 20.28.3 | 20.29.2 | 20.28.2 | 20.29.1 | 20.28.1 | 20.29.0 | 20.28.0 |
| non-inverted | [31] | [30] | [29] | [28] | [27] | [26] | [25] | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:CAPABILITIES_PTR | 3.29.27 | 3.28.27 | 3.29.26 | 3.28.26 | 3.29.25 | 3.28.25 | 3.29.24 | 3.28.24 |
|---|---|---|---|---|---|---|---|---|
| PCIE:DNSTREAM_LINK_NUM | 16.29.39 | 16.28.39 | 16.29.38 | 16.28.38 | 16.29.37 | 16.28.37 | 16.29.36 | 16.28.36 |
| PCIE:HEADER_TYPE | 5.29.35 | 5.28.35 | 5.29.34 | 5.28.34 | 5.29.33 | 5.28.33 | 5.29.32 | 5.28.32 |
| PCIE:INTERRUPT_PIN | 5.29.39 | 5.28.39 | 5.29.38 | 5.28.38 | 5.29.37 | 5.28.37 | 5.29.36 | 5.28.36 |
| PCIE:MSIX_BASE_PTR | 7.29.3 | 7.28.3 | 7.29.2 | 7.28.2 | 7.29.1 | 7.28.1 | 7.29.0 | 7.28.0 |
| PCIE:MSIX_CAP_ID | 7.29.7 | 7.28.7 | 7.29.6 | 7.28.6 | 7.29.5 | 7.28.5 | 7.29.4 | 7.28.4 |
| PCIE:MSIX_CAP_NEXTPTR | 7.29.11 | 7.28.11 | 7.29.10 | 7.28.10 | 7.29.9 | 7.28.9 | 7.29.8 | 7.28.8 |
| PCIE:MSI_BASE_PTR | 6.29.27 | 6.28.27 | 6.29.26 | 6.28.26 | 6.29.25 | 6.28.25 | 6.29.24 | 6.28.24 |
| PCIE:MSI_CAP_ID | 6.29.35 | 6.28.35 | 6.29.34 | 6.28.34 | 6.29.33 | 6.28.33 | 6.29.32 | 6.28.32 |
| PCIE:MSI_CAP_NEXTPTR | 6.29.43 | 6.28.43 | 6.29.42 | 6.28.42 | 6.29.41 | 6.28.41 | 6.29.40 | 6.28.40 |
| PCIE:N_FTS_COMCLK_GEN1 | 16.29.19 | 16.28.19 | 16.29.18 | 16.28.18 | 16.29.17 | 16.28.17 | 16.29.16 | 16.28.16 |
| PCIE:N_FTS_COMCLK_GEN2 | 16.29.23 | 16.28.23 | 16.29.22 | 16.28.22 | 16.29.21 | 16.28.21 | 16.29.20 | 16.28.20 |
| PCIE:N_FTS_GEN1 | 16.29.27 | 16.28.27 | 16.29.26 | 16.28.26 | 16.29.25 | 16.28.25 | 16.29.24 | 16.28.24 |
| PCIE:N_FTS_GEN2 | 16.29.31 | 16.28.31 | 16.29.30 | 16.28.30 | 16.29.29 | 16.28.29 | 16.29.28 | 16.28.28 |
| PCIE:PCIE_BASE_PTR | 8.29.11 | 8.28.11 | 8.29.10 | 8.28.10 | 8.29.9 | 8.28.9 | 8.29.8 | 8.28.8 |
| PCIE:PCIE_CAP_CAPABILITY_ID | 8.29.15 | 8.28.15 | 8.29.14 | 8.28.14 | 8.29.13 | 8.28.13 | 8.29.12 | 8.28.12 |
| PCIE:PCIE_CAP_NEXTPTR | 8.29.23 | 8.28.23 | 8.29.22 | 8.28.22 | 8.29.21 | 8.28.21 | 8.29.20 | 8.28.20 |
| PCIE:PM_BASE_PTR | 8.29.31 | 8.28.31 | 8.29.30 | 8.28.30 | 8.29.29 | 8.28.29 | 8.29.28 | 8.28.28 |
| PCIE:PM_CAP_ID | 8.29.38 | 8.28.38 | 8.29.37 | 8.28.37 | 8.29.36 | 8.28.36 | 8.29.35 | 8.28.35 |
| PCIE:PM_CAP_NEXTPTR | 8.29.43 | 8.28.43 | 8.29.42 | 8.28.42 | 8.29.41 | 8.28.41 | 8.29.40 | 8.28.40 |
| PCIE:PM_DATA0 | 9.29.14 | 9.28.14 | 9.29.13 | 9.28.13 | 9.29.12 | 9.28.12 | 9.29.11 | 9.28.11 |
| PCIE:PM_DATA1 | 9.29.19 | 9.28.19 | 9.29.18 | 9.28.18 | 9.29.17 | 9.28.17 | 9.29.16 | 9.28.16 |
| PCIE:PM_DATA2 | 9.29.23 | 9.28.23 | 9.29.22 | 9.28.22 | 9.29.21 | 9.28.21 | 9.29.20 | 9.28.20 |
| PCIE:PM_DATA3 | 9.29.27 | 9.28.27 | 9.29.26 | 9.28.26 | 9.29.25 | 9.28.25 | 9.29.24 | 9.28.24 |
| PCIE:PM_DATA4 | 9.29.31 | 9.28.31 | 9.29.30 | 9.28.30 | 9.29.29 | 9.28.29 | 9.29.28 | 9.28.28 |
| PCIE:PM_DATA5 | 9.29.35 | 9.28.35 | 9.29.34 | 9.28.34 | 9.29.33 | 9.28.33 | 9.29.32 | 9.28.32 |
| PCIE:PM_DATA6 | 9.29.39 | 9.28.39 | 9.29.38 | 9.28.38 | 9.29.37 | 9.28.37 | 9.29.36 | 9.28.36 |
| PCIE:PM_DATA7 | 9.29.43 | 9.28.43 | 9.29.42 | 9.28.42 | 9.29.41 | 9.28.41 | 9.29.40 | 9.28.40 |
| PCIE:SLOT_CAP_SLOT_POWER_LIMIT_VALUE | 13.29.28 | 13.28.28 | 13.29.27 | 13.28.27 | 13.29.26 | 13.28.26 | 13.29.25 | 13.28.25 |
| PCIE:SPARE_BYTE0 | 18.29.35 | 18.28.35 | 18.29.34 | 18.28.34 | 18.29.33 | 18.28.33 | 18.29.32 | 18.28.32 |
| PCIE:SPARE_BYTE1 | 18.29.39 | 18.28.39 | 18.29.38 | 18.28.38 | 18.29.37 | 18.28.37 | 18.29.36 | 18.28.36 |
| PCIE:SPARE_BYTE2 | 18.29.43 | 18.28.43 | 18.29.42 | 18.28.42 | 18.29.41 | 18.28.41 | 18.29.40 | 18.28.40 |
| PCIE:SPARE_BYTE3 | 18.29.47 | 18.28.47 | 18.29.46 | 18.28.46 | 18.29.45 | 18.28.45 | 18.29.44 | 18.28.44 |
| non-inverted | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:CFG_ECRC_ERR_CPLSTAT | 18.29.16 | 18.28.16 |
|---|---|---|
| PCIE:DEV_CAP2_MAX_ENDEND_TLP_PREFIXES | 4.28.21 | 4.29.20 |
| PCIE:DEV_CAP2_TPH_COMPLETER_SUPPORTED | 4.28.19 | 4.29.18 |
| PCIE:DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT | 4.28.30 | 4.29.29 |
| PCIE:DEV_CAP_RSVD_17_16 | 4.28.34 | 4.29.33 |
| PCIE:LINK_CAP_ASPM_SUPPORT | 5.29.46 | 5.28.46 |
| PCIE:LL_ACK_TIMEOUT_FUNC | 15.29.16 | 15.28.16 |
| PCIE:LL_REPLAY_TIMEOUT_FUNC | 15.29.32 | 15.28.32 |
| PCIE:PCIE_CAP_RSVD_15_14 | 8.28.25 | 8.29.24 |
| PCIE:PM_ASPML0S_TIMEOUT_FUNC | 16.29.0 | 16.28.0 |
| PCIE:PM_DATA_SCALE0 | 9.29.3 | 9.28.3 |
| PCIE:PM_DATA_SCALE1 | 9.29.4 | 9.28.4 |
| PCIE:PM_DATA_SCALE2 | 9.29.5 | 9.28.5 |
| PCIE:PM_DATA_SCALE3 | 9.29.6 | 9.28.6 |
| PCIE:PM_DATA_SCALE4 | 9.29.7 | 9.28.7 |
| PCIE:PM_DATA_SCALE5 | 9.29.8 | 9.28.8 |
| PCIE:PM_DATA_SCALE6 | 9.29.9 | 9.28.9 |
| PCIE:PM_DATA_SCALE7 | 9.29.10 | 9.28.10 |
| PCIE:RECRC_CHK | 18.29.14 | 18.28.14 |
| PCIE:RP_AUTO_SPD | 18.28.21 | 18.29.20 |
| PCIE:SLOT_CAP_SLOT_POWER_LIMIT_SCALE | 13.29.24 | 13.28.24 |
| PCIE:TL_RX_RAM_RDATA_LATENCY | 17.29.1 | 17.28.1 |
| PCIE:TL_TX_RAM_RDATA_LATENCY | 17.29.7 | 17.28.7 |
| non-inverted | [1] | [0] |
| PCIE:CRM_MODULE_RSTS | 15.29.6 | 15.28.6 | 15.29.5 | 15.28.5 | 15.29.4 | 15.28.4 | 15.29.3 |
|---|---|---|---|---|---|---|---|
| PCIE:VC0_TOTAL_CREDITS_CH | 17.28.35 | 17.29.34 | 17.28.34 | 17.29.33 | 17.28.33 | 17.29.32 | 17.28.32 |
| PCIE:VC0_TOTAL_CREDITS_NPH | 17.29.38 | 17.28.38 | 17.29.37 | 17.28.37 | 17.29.36 | 17.28.36 | 17.29.35 |
| PCIE:VC0_TOTAL_CREDITS_PH | 18.28.11 | 18.29.10 | 18.28.10 | 18.29.9 | 18.28.9 | 18.29.8 | 18.28.8 |
| non-inverted | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:DEV_CAP_ENDPOINT_L0S_LATENCY | 4.28.25 | 4.29.24 | 4.28.24 |
|---|---|---|---|
| PCIE:DEV_CAP_ENDPOINT_L1_LATENCY | 4.29.26 | 4.28.26 | 4.29.25 |
| PCIE:DEV_CAP_MAX_PAYLOAD_SUPPORTED | 4.28.29 | 4.29.28 | 4.28.28 |
| PCIE:DEV_CAP_RSVD_14_12 | 4.28.33 | 4.29.32 | 4.28.32 |
| PCIE:DEV_CAP_RSVD_31_29 | 4.29.35 | 4.28.35 | 4.29.34 |
| PCIE:LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 | 6.28.1 | 6.29.0 | 6.28.0 |
| PCIE:LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 | 6.29.2 | 6.28.2 | 6.29.1 |
| PCIE:LINK_CAP_L0S_EXIT_LATENCY_GEN1 | 6.28.4 | 6.29.3 | 6.28.3 |
| PCIE:LINK_CAP_L0S_EXIT_LATENCY_GEN2 | 6.29.5 | 6.28.5 | 6.29.4 |
| PCIE:LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 | 6.28.7 | 6.29.6 | 6.28.6 |
| PCIE:LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 | 6.28.9 | 6.29.8 | 6.28.8 |
| PCIE:LINK_CAP_L1_EXIT_LATENCY_GEN1 | 6.29.10 | 6.28.10 | 6.29.9 |
| PCIE:LINK_CAP_L1_EXIT_LATENCY_GEN2 | 6.28.12 | 6.29.11 | 6.28.11 |
| PCIE:MSIX_CAP_PBA_BIR | 7.29.13 | 7.28.13 | 7.29.12 |
| PCIE:MSIX_CAP_TABLE_BIR | 7.29.31 | 7.28.31 | 7.29.30 |
| PCIE:MSI_CAP_MULTIMSGCAP | 6.29.37 | 6.28.37 | 6.29.36 |
| PCIE:PL_AUTO_CONFIG | 16.29.33 | 16.28.33 | 16.29.32 |
| PCIE:PM_CAP_AUXCURRENT | 8.28.33 | 8.29.32 | 8.28.32 |
| PCIE:PM_CAP_VERSION | 9.28.1 | 9.29.0 | 9.28.0 |
| PCIE:RBAR_CAP_INDEX0 | 12.28.33 | 12.29.32 | 12.28.32 |
| PCIE:RBAR_CAP_INDEX1 | 12.29.34 | 12.28.34 | 12.29.33 |
| PCIE:RBAR_CAP_INDEX2 | 12.28.36 | 12.29.35 | 12.28.35 |
| PCIE:RBAR_CAP_INDEX3 | 12.29.37 | 12.28.37 | 12.29.36 |
| PCIE:RBAR_CAP_INDEX4 | 12.28.39 | 12.29.38 | 12.28.38 |
| PCIE:RBAR_CAP_INDEX5 | 12.28.41 | 12.29.40 | 12.28.40 |
| PCIE:RBAR_NUM | 10.28.27 | 10.29.26 | 10.28.26 |
| PCIE:USER_CLK_FREQ | 15.28.3 | 15.29.2 | 15.28.2 |
| non-inverted | [2] | [1] | [0] |
| PCIE:ENABLE_MSG_ROUTE | 16.29.47 | 16.28.47 | 16.29.46 | 16.28.46 | 16.29.45 | 16.28.45 | 16.29.44 | 16.28.44 | 16.29.43 | 16.28.43 | 16.29.42 |
|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:MSIX_CAP_TABLE_SIZE | 8.28.5 | 8.29.4 | 8.28.4 | 8.29.3 | 8.28.3 | 8.29.2 | 8.28.2 | 8.29.1 | 8.28.1 | 8.29.0 | 8.28.0 |
| PCIE:VC0_TOTAL_CREDITS_CD | 17.28.29 | 17.29.28 | 17.28.28 | 17.29.27 | 17.28.27 | 17.29.26 | 17.28.26 | 17.29.25 | 17.28.25 | 17.29.24 | 17.28.24 |
| PCIE:VC0_TOTAL_CREDITS_NPD | 17.28.45 | 17.29.44 | 17.28.44 | 17.29.43 | 17.28.43 | 17.29.42 | 17.28.42 | 17.29.41 | 17.28.41 | 17.29.40 | 17.28.40 |
| PCIE:VC0_TOTAL_CREDITS_PD | 18.28.5 | 18.29.4 | 18.28.4 | 18.29.3 | 18.28.3 | 18.29.2 | 18.28.2 | 18.29.1 | 18.28.1 | 18.29.0 | 18.28.0 |
| non-inverted | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:EXT_CFG_CAP_PTR | 5.29.20 | 5.28.20 | 5.29.19 | 5.28.19 | 5.29.18 | 5.28.18 |
|---|---|---|---|---|---|---|
| PCIE:LINK_CAP_MAX_LINK_WIDTH | 16.29.10 | 16.28.10 | 16.29.9 | 16.28.9 | 16.29.8 | 16.28.8 |
| PCIE:LTSSM_MAX_LINK_WIDTH | 16.29.13 | 16.28.13 | 16.29.12 | 16.28.12 | 16.29.11 | 16.28.11 |
| non-inverted | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:EXT_CFG_XP_CAP_PTR | 5.29.28 | 5.28.28 | 5.29.27 | 5.28.27 | 5.29.26 | 5.28.26 | 5.29.25 | 5.28.25 | 5.29.24 | 5.28.24 |
|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:LAST_CONFIG_DWORD | 5.29.45 | 5.28.45 | 5.29.44 | 5.28.44 | 5.29.43 | 5.28.43 | 5.29.42 | 5.28.42 | 5.29.41 | 5.28.41 |
| non-inverted | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:INFER_EI | 16.28.5 | 16.29.4 | 16.28.4 | 16.29.3 | 16.28.3 |
|---|---|---|---|---|---|
| PCIE:PM_CAP_PMESUPPORT | 8.28.47 | 8.29.46 | 8.28.46 | 8.29.45 | 8.28.45 |
| PCIE:RBAR_CAP_CONTROL_ENCODEDBAR0 | 12.29.43 | 12.28.43 | 12.29.42 | 12.28.42 | 12.29.41 |
| PCIE:RBAR_CAP_CONTROL_ENCODEDBAR1 | 12.28.46 | 12.29.45 | 12.28.45 | 12.29.44 | 12.28.44 |
| PCIE:RBAR_CAP_CONTROL_ENCODEDBAR2 | 13.28.2 | 13.29.1 | 13.28.1 | 13.29.0 | 13.28.0 |
| PCIE:RBAR_CAP_CONTROL_ENCODEDBAR3 | 13.29.4 | 13.28.4 | 13.29.3 | 13.28.3 | 13.29.2 |
| PCIE:RBAR_CAP_CONTROL_ENCODEDBAR4 | 13.28.7 | 13.29.6 | 13.28.6 | 13.29.5 | 13.28.5 |
| PCIE:RBAR_CAP_CONTROL_ENCODEDBAR5 | 13.28.10 | 13.29.9 | 13.28.9 | 13.29.8 | 13.28.8 |
| PCIE:RP_AUTO_SPD_LOOPCNT | 18.29.23 | 18.28.23 | 18.29.22 | 18.28.22 | 18.29.21 |
| PCIE:VC0_TX_LASTPACKET | 18.29.13 | 18.28.13 | 18.29.12 | 18.28.12 | 18.29.11 |
| non-inverted | [4] | [3] | [2] | [1] | [0] |
| PCIE:LL_ACK_TIMEOUT | 15.28.15 | 15.29.14 | 15.28.14 | 15.29.13 | 15.28.13 | 15.29.12 | 15.28.12 | 15.29.11 | 15.28.11 | 15.29.10 | 15.28.10 | 15.29.9 | 15.28.9 | 15.29.8 | 15.28.8 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:LL_REPLAY_TIMEOUT | 15.28.31 | 15.29.30 | 15.28.30 | 15.29.29 | 15.28.29 | 15.29.28 | 15.28.28 | 15.29.27 | 15.28.27 | 15.29.26 | 15.28.26 | 15.29.25 | 15.28.25 | 15.29.24 | 15.28.24 |
| PCIE:PM_ASPML0S_TIMEOUT | 15.28.47 | 15.29.46 | 15.28.46 | 15.29.45 | 15.28.45 | 15.29.44 | 15.28.44 | 15.29.43 | 15.28.43 | 15.29.42 | 15.28.42 | 15.29.41 | 15.28.41 | 15.29.40 | 15.28.40 |
| non-inverted | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:MSIX_CAP_PBA_OFFSET | 7.28.30 | 7.29.29 | 7.28.29 | 7.29.28 | 7.28.28 | 7.29.27 | 7.28.27 | 7.29.26 | 7.28.26 | 7.29.25 | 7.28.25 | 7.29.24 | 7.28.24 | 7.29.23 | 7.28.23 | 7.29.22 | 7.28.22 | 7.29.21 | 7.28.21 | 7.29.20 | 7.28.20 | 7.29.19 | 7.28.19 | 7.29.18 | 7.28.18 | 7.29.17 | 7.28.17 | 7.29.16 | 7.28.16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:MSIX_CAP_TABLE_OFFSET | 7.28.46 | 7.29.45 | 7.28.45 | 7.29.44 | 7.28.44 | 7.29.43 | 7.28.43 | 7.29.42 | 7.28.42 | 7.29.41 | 7.28.41 | 7.29.40 | 7.28.40 | 7.29.39 | 7.28.39 | 7.29.38 | 7.28.38 | 7.29.37 | 7.28.37 | 7.29.36 | 7.28.36 | 7.29.35 | 7.28.35 | 7.29.34 | 7.28.34 | 7.29.33 | 7.28.33 | 7.29.32 | 7.28.32 |
| non-inverted | [28] | [27] | [26] | [25] | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PCIE:SLOT_CAP_PHYSICAL_SLOT_NUM | 13.28.22 | 13.29.21 | 13.28.21 | 13.29.20 | 13.28.20 | 13.29.19 | 13.28.19 | 13.29.18 | 13.28.18 | 13.29.17 | 13.28.17 | 13.29.16 | 13.28.16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCIE:VC0_RX_RAM_LIMIT | 17.28.22 | 17.29.21 | 17.28.21 | 17.29.20 | 17.28.20 | 17.29.19 | 17.28.19 | 17.29.18 | 17.28.18 | 17.29.17 | 17.28.17 | 17.29.16 | 17.28.16 |
| non-inverted | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |