Configurable Logic Block

Tile CLB

Cells: 1

Switchbox INT

xc2000 CLB switchbox INT pass gates
Destination	Source	Bit
SINGLE_V[0]	OUT_CLB_Y_E	!MAIN[17][3]
SINGLE_V[1]	OUT_CLB_X_E	!MAIN[10][3]
SINGLE_V[2]	OUT_CLB_Y_E	!MAIN[6][3]
SINGLE_V[3]	OUT_CLB_X_E	!MAIN[9][4]
SINGLE_V[4]	OUT_CLB_Y_E	!MAIN[16][3]
LONG_V[0]	OUT_CLB_X_E	!MAIN[8][3]
LONG_V[1]	OUT_CLB_Y_E	!MAIN[7][3]

xc2000 CLB switchbox INT bidirectional pass gates
Side A	Side B	Bit
SINGLE_H[0]	SINGLE_H_E[0]	!MAIN[14][7]
SINGLE_H[0]	SINGLE_H_E[1]	!MAIN[15][7]
SINGLE_H[0]	SINGLE_V[1]	!MAIN[10][6]
SINGLE_H[0]	SINGLE_V_S[0]	!MAIN[9][5]
SINGLE_H[0]	SINGLE_V_S[1]	!MAIN[11][7]
SINGLE_H[0]	LONG_V[1]	!MAIN[6][5]
SINGLE_H[1]	SINGLE_H_E[0]	!MAIN[16][6]
SINGLE_H[1]	SINGLE_H_E[1]	!MAIN[15][6]
SINGLE_H[1]	SINGLE_V[0]	!MAIN[9][7]
SINGLE_H[1]	SINGLE_V[1]	!MAIN[10][7]
SINGLE_H[1]	SINGLE_V[4]	!MAIN[11][5]
SINGLE_H[1]	SINGLE_V_S[1]	!MAIN[11][6]
SINGLE_H[1]	SINGLE_V_S[4]	!MAIN[14][5]
SINGLE_H[1]	LONG_V[0]	!MAIN[10][5]
SINGLE_H[2]	SINGLE_H_E[2]	!MAIN[3][7]
SINGLE_H[2]	SINGLE_H_E[3]	!MAIN[1][6]
SINGLE_H[2]	SINGLE_V[3]	!MAIN[1][5]
SINGLE_H[2]	SINGLE_V[4]	!MAIN[12][5]
SINGLE_H[2]	SINGLE_V_S[2]	!MAIN[3][6]
SINGLE_H[2]	SINGLE_V_S[3]	!MAIN[1][7]
SINGLE_H[2]	SINGLE_V_S[4]	!MAIN[13][5]
SINGLE_H[2]	LONG_V[1]	!MAIN[5][5]
SINGLE_H[3]	SINGLE_H_E[2]	!MAIN[2][7]
SINGLE_H[3]	SINGLE_H_E[3]	!MAIN[2][6]
SINGLE_H[3]	SINGLE_V[2]	!MAIN[4][6]
SINGLE_H[3]	SINGLE_V[3]	!MAIN[0][6]
SINGLE_H[3]	SINGLE_V_S[3]	!MAIN[0][7]
SINGLE_H[3]	LONG_V[0]	!MAIN[7][5]
SINGLE_H_E[0]	SINGLE_V[0]	!MAIN[17][5]
SINGLE_H_E[0]	SINGLE_V_S[0]	!MAIN[16][7]
SINGLE_H_E[0]	SINGLE_V_S[1]	!MAIN[14][6]
SINGLE_H_E[1]	SINGLE_V[0]	!MAIN[17][6]
SINGLE_H_E[1]	SINGLE_V[1]	!MAIN[13][6]
SINGLE_H_E[1]	SINGLE_V_S[0]	!MAIN[17][7]
SINGLE_H_E[2]	SINGLE_V[2]	!MAIN[7][6]
SINGLE_H_E[2]	SINGLE_V_S[2]	!MAIN[6][7]
SINGLE_H_E[2]	SINGLE_V_S[3]	!MAIN[8][5]
SINGLE_H_E[3]	SINGLE_V[2]	!MAIN[7][7]
SINGLE_H_E[3]	SINGLE_V[3]	!MAIN[8][7]
SINGLE_H_E[3]	SINGLE_V_S[2]	!MAIN[6][6]
SINGLE_V[0]	SINGLE_V_S[0]	!MAIN[9][6]
SINGLE_V[0]	SINGLE_V_S[1]	!MAIN[12][7]
SINGLE_V[0]	LONG_H	!MAIN[16][5]
SINGLE_V[1]	SINGLE_V_S[0]	!MAIN[13][7]
SINGLE_V[1]	SINGLE_V_S[1]	!MAIN[12][6]
SINGLE_V[2]	SINGLE_V_S[2]	!MAIN[5][6]
SINGLE_V[2]	SINGLE_V_S[3]	!MAIN[4][7]
SINGLE_V[3]	SINGLE_V_S[2]	!MAIN[5][7]
SINGLE_V[3]	SINGLE_V_S[3]	!MAIN[8][6]
SINGLE_V[3]	LONG_H	!MAIN[3][5]
SINGLE_V[4]	SINGLE_V_S[4]	!MAIN[15][5]

xc2000 CLB switchbox INT muxes IMUX_CLB_A
Bits				Destination
MAIN[1][3]	MAIN[3][3]	MAIN[2][3]	MAIN[4][5]	IMUX_CLB_A
				Source
0	0	0	1	SINGLE_H[3]
0	0	1	1	SINGLE_H[0]
0	1	0	0	SINGLE_H[2]
0	1	1	0	OUT_CLB_X_S
1	1	0	1	LONG_H
1	1	1	1	SINGLE_H[1]

xc2000 CLB switchbox INT muxes IMUX_CLB_B
Bits						Destination
MAIN[7][4]	MAIN[17][4]	MAIN[6][4]	MAIN[15][4]	MAIN[14][4]	MAIN[11][4]	IMUX_CLB_B
						Source
0	0	0	1	1	1	OUT_CLB_Y_E
0	0	1	1	1	1	SINGLE_V[0]
0	1	0	0	1	1	SINGLE_V[1]
0	1	0	1	0	1	SINGLE_V[4]
0	1	0	1	1	0	LONG_V[0]
0	1	1	0	1	1	GCLK
0	1	1	1	0	1	SINGLE_V[3]
0	1	1	1	1	0	LONG_V[1]
1	1	0	1	1	1	OUT_CLB_X_S
1	1	1	1	1	1	SINGLE_V[2]

xc2000 CLB switchbox INT muxes IMUX_CLB_C
Bits					Destination
MAIN[10][4]	MAIN[16][4]	MAIN[8][4]	MAIN[13][4]	MAIN[12][4]	IMUX_CLB_C
					Source
0	0	0	1	1	SINGLE_V[0]
0	0	1	1	1	SINGLE_V[1]
0	1	0	0	1	SINGLE_V[3]
0	1	0	1	0	LONG_V[1]
0	1	1	0	1	SINGLE_V[4]
0	1	1	1	0	LONG_V[0]
1	1	0	1	1	SINGLE_V[2]
1	1	1	1	1	OUT_CLB_X_N

xc2000 CLB switchbox INT muxes IMUX_CLB_D
Bits				Destination
MAIN[0][3]	MAIN[4][3]	MAIN[2][5]	MAIN[5][3]	IMUX_CLB_D
				Source
0	0	0	1	SINGLE_H[3]
0	0	1	1	SINGLE_H[0]
0	1	0	0	SINGLE_H[2]
0	1	1	0	OUT_CLB_X
1	1	0	1	LONG_H
1	1	1	1	SINGLE_H[1]

xc2000 CLB switchbox INT muxes IMUX_CLB_K
Bits				Destination
MAIN[11][3]	MAIN[14][3]	MAIN[15][3]	MAIN[13][3]	IMUX_CLB_K
				Source
0	0	1	1	LONG_V[1]
0	1	0	1	GCLK
0	1	1	0	SPECIAL_CLB_C
0	1	1	1	~SPECIAL_CLB_G
1	1	1	1	off

Bels CLB

xc2000 CLB bel CLB pins
Pin	Direction	CLB
A	in	IMUX_CLB_A
B	in	IMUX_CLB_B
C	in	IMUX_CLB_C
D	in	IMUX_CLB_D_N
K	in	IMUX_CLB_K invert by !MAIN[12][3]
X	out	OUT_CLB_X
Y	out	OUT_CLB_Y

xc2000 CLB bel CLB attribute bits
Attribute	CLB
F bit 0	!MAIN[16][0]
F bit 1	!MAIN[17][0]
F bit 2	!MAIN[15][0]
F bit 3	!MAIN[14][0]
F bit 4	!MAIN[12][0]
F bit 5	!MAIN[13][0]
F bit 6	!MAIN[11][0]
F bit 7	!MAIN[10][0]
G bit 0	!MAIN[1][0]
G bit 1	!MAIN[0][0]
G bit 2	!MAIN[2][0]
G bit 3	!MAIN[3][0]
G bit 4	!MAIN[5][0]
G bit 5	!MAIN[4][0]
G bit 6	!MAIN[6][0]
G bit 7	!MAIN[7][0]
MODE	[enum: CLB_MODE]
FF_MODE	[enum: FF_MODE]
MUX_F1	[enum: CLB_MUX_I1]
MUX_G1	[enum: CLB_MUX_I1]
MUX_F2	[enum: CLB_MUX_I2]
MUX_G2	[enum: CLB_MUX_I2]
MUX_F3	[enum: CLB_MUX_I3]
MUX_G3	[enum: CLB_MUX_I3]
MUX_X	[enum: CLB_MUX_XY]
MUX_Y	[enum: CLB_MUX_XY]
MUX_RES	[enum: CLB_MUX_RES]
MUX_SET	[enum: CLB_MUX_SET]
READBACK_Q bit 0	!MAIN[3][2]

xc2000 CLB enum CLB_MODE
CLB.MODE	MAIN[8][0]
FGM	1
FG	0

xc2000 CLB enum FF_MODE
CLB.FF_MODE	MAIN[8][2]
FF	1
LATCH	0

xc2000 CLB enum CLB_MUX_I1
CLB.MUX_F1	MAIN[10][1]
CLB.MUX_G1	MAIN[6][1]
A	0
B	1

xc2000 CLB enum CLB_MUX_I2
CLB.MUX_F2	MAIN[11][1]
CLB.MUX_G2	MAIN[5][1]
B	0
C	1

xc2000 CLB enum CLB_MUX_I3
CLB.MUX_F3	MAIN[16][1]	MAIN[17][1]
CLB.MUX_G3	MAIN[1][1]	MAIN[0][1]
C	0	1
D	1	0
Q	1	1

xc2000 CLB enum CLB_MUX_XY
CLB.MUX_X	MAIN[7][2]	MAIN[6][2]
CLB.MUX_Y	MAIN[4][2]	MAIN[5][2]
F	0	1
G	1	0
Q	1	1

xc2000 CLB enum CLB_MUX_RES
CLB.MUX_RES	MAIN[16][2]	MAIN[17][2]
D	0	1
G	0	0
TIE_0	1	1

xc2000 CLB enum CLB_MUX_SET
CLB.MUX_SET	MAIN[15][2]	MAIN[14][2]
A	1	1
F	1	0
TIE_0	0	1

Bel wires

xc2000 CLB bel wires
Wire	Pins
IMUX_CLB_A	CLB.A
IMUX_CLB_B	CLB.B
IMUX_CLB_C	CLB.C
IMUX_CLB_D_N	CLB.D
IMUX_CLB_K	CLB.K
OUT_CLB_X	CLB.X
OUT_CLB_Y	CLB.Y

Bitstream

xc2000 CLB rect MAIN
Bit	Frame
Bit	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B7	INT: !bipass SINGLE_H_E[1] = SINGLE_V_S[0]	INT: !bipass SINGLE_H_E[0] = SINGLE_V_S[0]	INT: !bipass SINGLE_H[0] = SINGLE_H_E[1]	INT: !bipass SINGLE_H[0] = SINGLE_H_E[0]	INT: !bipass SINGLE_V[1] = SINGLE_V_S[0]	INT: !bipass SINGLE_V[0] = SINGLE_V_S[1]	INT: !bipass SINGLE_H[0] = SINGLE_V_S[1]	INT: !bipass SINGLE_H[1] = SINGLE_V[1]	INT: !bipass SINGLE_H[1] = SINGLE_V[0]	INT: !bipass SINGLE_H_E[3] = SINGLE_V[3]	INT: !bipass SINGLE_H_E[3] = SINGLE_V[2]	INT: !bipass SINGLE_H_E[2] = SINGLE_V_S[2]	INT: !bipass SINGLE_V[3] = SINGLE_V_S[2]	INT: !bipass SINGLE_V[2] = SINGLE_V_S[3]	INT: !bipass SINGLE_H[2] = SINGLE_H_E[2]	INT: !bipass SINGLE_H[3] = SINGLE_H_E[2]	INT: !bipass SINGLE_H[2] = SINGLE_V_S[3]	INT: !bipass SINGLE_H[3] = SINGLE_V_S[3]
B6	INT: !bipass SINGLE_H_E[1] = SINGLE_V[0]	INT: !bipass SINGLE_H[1] = SINGLE_H_E[0]	INT: !bipass SINGLE_H[1] = SINGLE_H_E[1]	INT: !bipass SINGLE_H_E[0] = SINGLE_V_S[1]	INT: !bipass SINGLE_H_E[1] = SINGLE_V[1]	INT: !bipass SINGLE_V[1] = SINGLE_V_S[1]	INT: !bipass SINGLE_H[1] = SINGLE_V_S[1]	INT: !bipass SINGLE_H[0] = SINGLE_V[1]	INT: !bipass SINGLE_V[0] = SINGLE_V_S[0]	INT: !bipass SINGLE_V[3] = SINGLE_V_S[3]	INT: !bipass SINGLE_H_E[2] = SINGLE_V[2]	INT: !bipass SINGLE_H_E[3] = SINGLE_V_S[2]	INT: !bipass SINGLE_V[2] = SINGLE_V_S[2]	INT: !bipass SINGLE_H[3] = SINGLE_V[2]	INT: !bipass SINGLE_H[2] = SINGLE_V_S[2]	INT: !bipass SINGLE_H[3] = SINGLE_H_E[3]	INT: !bipass SINGLE_H[2] = SINGLE_H_E[3]	INT: !bipass SINGLE_H[3] = SINGLE_V[3]
B5	INT: !bipass SINGLE_H_E[0] = SINGLE_V[0]	INT: !bipass SINGLE_V[0] = LONG_H	INT: !bipass SINGLE_V[4] = SINGLE_V_S[4]	INT: !bipass SINGLE_H[1] = SINGLE_V_S[4]	INT: !bipass SINGLE_H[2] = SINGLE_V_S[4]	INT: !bipass SINGLE_H[2] = SINGLE_V[4]	INT: !bipass SINGLE_H[1] = SINGLE_V[4]	INT: !bipass SINGLE_H[1] = LONG_V[0]	INT: !bipass SINGLE_H[0] = SINGLE_V_S[0]	INT: !bipass SINGLE_H_E[2] = SINGLE_V_S[3]	INT: !bipass SINGLE_H[3] = LONG_V[0]	INT: !bipass SINGLE_H[0] = LONG_V[1]	INT: !bipass SINGLE_H[2] = LONG_V[1]	INT: mux IMUX_CLB_A bit 0	INT: !bipass SINGLE_V[3] = LONG_H	INT: mux IMUX_CLB_D bit 1	INT: !bipass SINGLE_H[2] = SINGLE_V[3]	-
B4	INT: mux IMUX_CLB_B bit 4	INT: mux IMUX_CLB_C bit 3	INT: mux IMUX_CLB_B bit 2	INT: mux IMUX_CLB_B bit 1	INT: mux IMUX_CLB_C bit 1	INT: mux IMUX_CLB_C bit 0	INT: mux IMUX_CLB_B bit 0	INT: mux IMUX_CLB_C bit 4	INT: !pass SINGLE_V[3] ← OUT_CLB_X_E	INT: mux IMUX_CLB_C bit 2	INT: mux IMUX_CLB_B bit 5	INT: mux IMUX_CLB_B bit 3	-	-	-	-	-	-
B3	INT: !pass SINGLE_V[0] ← OUT_CLB_Y_E	INT: !pass SINGLE_V[4] ← OUT_CLB_Y_E	INT: mux IMUX_CLB_K bit 1	INT: mux IMUX_CLB_K bit 2	INT: mux IMUX_CLB_K bit 0	CLB: !invert K	INT: mux IMUX_CLB_K bit 3	INT: !pass SINGLE_V[1] ← OUT_CLB_X_E	-	INT: !pass LONG_V[0] ← OUT_CLB_X_E	INT: !pass LONG_V[1] ← OUT_CLB_Y_E	INT: !pass SINGLE_V[2] ← OUT_CLB_Y_E	INT: mux IMUX_CLB_D bit 0	INT: mux IMUX_CLB_D bit 2	INT: mux IMUX_CLB_A bit 2	INT: mux IMUX_CLB_A bit 1	INT: mux IMUX_CLB_A bit 3	INT: mux IMUX_CLB_D bit 3
B2	CLB: MUX_RES bit 0	CLB: MUX_RES bit 1	CLB: MUX_SET bit 1	CLB: MUX_SET bit 0	-	-	-	-	-	CLB: FF_MODE bit 0	CLB: MUX_X bit 1	CLB: MUX_X bit 0	CLB: MUX_Y bit 0	CLB: MUX_Y bit 1	CLB: ! READBACK_Q bit 0	-	-	-
B1	CLB: MUX_F3 bit 0	CLB: MUX_F3 bit 1	-	-	-	-	CLB: MUX_F2 bit 0	CLB: MUX_F1 bit 0	-	-	-	CLB: MUX_G1 bit 0	CLB: MUX_G2 bit 0	-	-	-	CLB: MUX_G3 bit 1	CLB: MUX_G3 bit 0
B0	CLB: ! F bit 1	CLB: ! F bit 0	CLB: ! F bit 2	CLB: ! F bit 3	CLB: ! F bit 5	CLB: ! F bit 4	CLB: ! F bit 6	CLB: ! F bit 7	-	CLB: MODE bit 0	CLB: ! G bit 7	CLB: ! G bit 6	CLB: ! G bit 4	CLB: ! G bit 5	CLB: ! G bit 3	CLB: ! G bit 2	CLB: ! G bit 0	CLB: ! G bit 1

Tile CLB_W

Cells: 2

Switchbox INT

xc2000 CLB_W switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[2]	CELL.OUT_IO_W_I_S1	!MAIN[12][5]
CELL.SINGLE_H[3]	CELL.OUT_IO_W_I[0]	!MAIN[7][5]
CELL.SINGLE_VW[0]	CELL.OUT_IO_W_I[0]	!MAIN[17][3]
CELL.SINGLE_VW[1]	CELL.OUT_IO_W_I[1]	!MAIN[10][3]
CELL.SINGLE_VW[2]	CELL.OUT_IO_W_I[0]	!MAIN[6][5]
CELL.SINGLE_VW[3]	CELL.OUT_IO_W_I[1]	!MAIN[9][4]
CELL.LONG_H	CELL.OUT_IO_W_I_S1	!MAIN[13][5]
CELL.LONG_V[0]	CELL.OUT_IO_W_I[0]	!MAIN[8][3]
CELL.LONG_V[1]	CELL.OUT_IO_W_I[1]	!MAIN[7][3]
CELL.LONG_IO_W	CELL.OUT_IO_W_I[0]	!MAIN[16][3]

xc2000 CLB_W switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.SINGLE_VW[1]	!MAIN[10][7]
CELL.SINGLE_H[0]	CELL.SINGLE_VW_S[0]	!MAIN[14][5]
CELL.SINGLE_H[0]	CELL.SINGLE_VW_S[1]	!MAIN[11][7]
CELL.SINGLE_H[0]	CELL.LONG_V[0]	!MAIN[11][5]
CELL.SINGLE_H[1]	CELL.SINGLE_VW[0]	!MAIN[15][7]
CELL.SINGLE_H[1]	CELL.SINGLE_VW[1]	!MAIN[9][7]
CELL.SINGLE_H[1]	CELL.SINGLE_VW_S[1]	!MAIN[8][7]
CELL.SINGLE_H[1]	CELL.LONG_V[1]	!MAIN[9][5]
CELL.SINGLE_H[2]	CELL.SINGLE_VW[3]	!MAIN[2][7]
CELL.SINGLE_H[2]	CELL.SINGLE_VW_S[2]	!MAIN[1][6]
CELL.SINGLE_H[2]	CELL.SINGLE_VW_S[3]	!MAIN[3][6]
CELL.SINGLE_H[3]	CELL.SINGLE_VW[2]	!MAIN[0][7]
CELL.SINGLE_H[3]	CELL.SINGLE_VW[3]	!MAIN[0][6]
CELL.SINGLE_H[3]	CELL.SINGLE_VW_S[3]	!MAIN[8][5]
CELL.SINGLE_VW[0]	CELL.SINGLE_VW_S[0]	!MAIN[16][7]
CELL.SINGLE_VW[0]	CELL.SINGLE_VW_S[1]	!MAIN[14][7]
CELL.SINGLE_VW[0]	CELL.LONG_H	!MAIN[16][5]
CELL.SINGLE_VW[1]	CELL.SINGLE_VW_S[0]	!MAIN[13][7]
CELL.SINGLE_VW[1]	CELL.SINGLE_VW_S[1]	!MAIN[12][7]
CELL.SINGLE_VW[2]	CELL.SINGLE_VW_S[2]	!MAIN[1][7]
CELL.SINGLE_VW[2]	CELL.SINGLE_VW_S[3]	!MAIN[3][7]
CELL.SINGLE_VW[3]	CELL.SINGLE_VW_S[2]	!MAIN[1][5]
CELL.SINGLE_VW[3]	CELL.SINGLE_VW_S[3]	!MAIN[2][6]
CELL.SINGLE_VW[3]	CELL.LONG_H	!MAIN[3][5]
CELL.LONG_H	CELL.LONG_V[0]	!MAIN[10][5]
CELL.LONG_H	CELL.LONG_V[1]	!MAIN[5][5]
CELL.LONG_H	CELL.LONG_IO_W	!MAIN[15][5]

xc2000 CLB_W switchbox INT muxes IMUX_CLB_A
Bits				Destination
MAIN[1][3]	MAIN[3][3]	MAIN[2][3]	MAIN[4][5]	CELL.IMUX_CLB_A
				Source
0	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	CELL.SINGLE_H[0]
0	1	0	0	CELL.SINGLE_H[2]
0	1	1	0	CELL.OUT_CLB_X_S
1	1	0	1	CELL.LONG_H
1	1	1	1	CELL.SINGLE_H[1]

xc2000 CLB_W switchbox INT muxes IMUX_CLB_B
Bits						Destination
MAIN[7][4]	MAIN[17][4]	MAIN[6][4]	MAIN[15][4]	MAIN[14][4]	MAIN[11][4]	CELL.IMUX_CLB_B
						Source
0	0	0	1	1	1	CELL.OUT_IO_W_I[1]
0	0	1	1	1	1	CELL.SINGLE_VW[0]
0	1	0	0	1	1	CELL.SINGLE_VW[1]
0	1	0	1	0	1	CELL.LONG_IO_W
0	1	0	1	1	0	CELL.LONG_V[0]
0	1	1	0	1	1	CELL.GCLK
0	1	1	1	0	1	CELL.SINGLE_VW[3]
0	1	1	1	1	0	CELL.LONG_V[1]
1	1	0	1	1	1	CELL.OUT_CLB_X_S
1	1	1	1	1	1	CELL.SINGLE_VW[2]

xc2000 CLB_W switchbox INT muxes IMUX_CLB_C
Bits					Destination
MAIN[10][4]	MAIN[16][4]	MAIN[8][4]	MAIN[13][4]	MAIN[12][4]	CELL.IMUX_CLB_C
					Source
0	0	0	1	1	CELL.SINGLE_VW[0]
0	0	1	1	1	CELL.SINGLE_VW[1]
0	1	0	0	1	CELL.SINGLE_VW[3]
0	1	0	1	0	CELL.LONG_V[1]
0	1	1	0	1	CELL.LONG_IO_W
0	1	1	1	0	CELL.LONG_V[0]
1	1	0	1	1	CELL.SINGLE_VW[2]
1	1	1	1	1	CELL.OUT_CLB_X_N

xc2000 CLB_W switchbox INT muxes IMUX_CLB_D
Bits				Destination
MAIN[0][3]	MAIN[4][3]	MAIN[2][5]	MAIN[5][3]	CELL.IMUX_CLB_D
				Source
0	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	CELL.SINGLE_H[0]
0	1	0	0	CELL.SINGLE_H[2]
0	1	1	0	CELL.OUT_CLB_X
1	1	0	1	CELL.LONG_H
1	1	1	1	CELL.SINGLE_H[1]

xc2000 CLB_W switchbox INT muxes IMUX_CLB_K
Bits				Destination
MAIN[11][3]	MAIN[14][3]	MAIN[15][3]	MAIN[13][3]	CELL.IMUX_CLB_K
				Source
0	0	1	1	CELL.LONG_V[1]
0	1	0	1	CELL.GCLK
0	1	1	0	CELL.SPECIAL_CLB_C
0	1	1	1	~CELL.SPECIAL_CLB_G
1	1	1	1	off

xc2000 CLB_W switchbox INT muxes IMUX_IO_W_O[0]
Bits				Destination
MAIN[17][7]	MAIN[18][7]	MAIN[17][5]	MAIN[19][7]	CELL.IMUX_IO_W_O[0]
				Source
0	0	0	1	CELL.SINGLE_VW[3]
0	0	1	1	CELL.SINGLE_H[2]
0	1	0	0	CELL.SINGLE_VW[1]
0	1	1	0	CELL.LONG_H
1	1	0	1	CELL.LONG_V[1]
1	1	1	1	CELL.SINGLE_H[0]

xc2000 CLB_W switchbox INT muxes IMUX_IO_W_O[1]
Bits				Destination
MAIN[18][1]	MAIN[19][1]	MAIN[20][1]	MAIN[18][0]	CELL.IMUX_IO_W_O[1]
				Source
0	0	1	0	S.SINGLE_H[1]
0	0	1	1	CELL.SINGLE_VW[0]
0	1	0	0	CELL.LONG_V[0]
0	1	0	1	CELL.LONG_IO_W
1	1	1	0	S.SINGLE_H[3]
1	1	1	1	CELL.SINGLE_VW[2]

xc2000 CLB_W switchbox INT muxes IMUX_IO_W_T[0]
Bits			Destination
MAIN[20][3]	MAIN[19][3]	MAIN[18][3]	CELL.IMUX_IO_W_T[0]
			Source
0	0	0	CELL.SINGLE_VW[0]
0	0	1	CELL.SINGLE_VW[2]
0	1	0	CELL.LONG_V[0]
0	1	1	CELL.LONG_IO_W
1	0	1	CELL.TIE_1
1	1	1	CELL.TIE_0

xc2000 CLB_W switchbox INT muxes IMUX_IO_W_T[1]
Bits			Destination
MAIN[20][2]	MAIN[19][2]	MAIN[18][2]	CELL.IMUX_IO_W_T[1]
			Source
0	0	0	CELL.SINGLE_VW[0]
0	0	1	CELL.SINGLE_VW[2]
0	1	0	CELL.LONG_V[0]
0	1	1	CELL.LONG_IO_W
1	0	1	CELL.TIE_1
1	1	1	CELL.TIE_0

Bels CLB

xc2000 CLB_W bel CLB pins
Pin	Direction	CLB
A	in	CELL.IMUX_CLB_A
B	in	CELL.IMUX_CLB_B
C	in	CELL.IMUX_CLB_C
D	in	CELL.IMUX_CLB_D_N
K	in	CELL.IMUX_CLB_K invert by !MAIN[12][3]
X	out	CELL.OUT_CLB_X
Y	out	CELL.OUT_CLB_Y

xc2000 CLB_W bel CLB attribute bits
Attribute	CLB
F bit 0	!MAIN[16][0]
F bit 1	!MAIN[17][0]
F bit 2	!MAIN[15][0]
F bit 3	!MAIN[14][0]
F bit 4	!MAIN[12][0]
F bit 5	!MAIN[13][0]
F bit 6	!MAIN[11][0]
F bit 7	!MAIN[10][0]
G bit 0	!MAIN[1][0]
G bit 1	!MAIN[0][0]
G bit 2	!MAIN[2][0]
G bit 3	!MAIN[3][0]
G bit 4	!MAIN[5][0]
G bit 5	!MAIN[4][0]
G bit 6	!MAIN[6][0]
G bit 7	!MAIN[7][0]
MODE	[enum: CLB_MODE]
FF_MODE	[enum: FF_MODE]
MUX_F1	[enum: CLB_MUX_I1]
MUX_G1	[enum: CLB_MUX_I1]
MUX_F2	[enum: CLB_MUX_I2]
MUX_G2	[enum: CLB_MUX_I2]
MUX_F3	[enum: CLB_MUX_I3]
MUX_G3	[enum: CLB_MUX_I3]
MUX_X	[enum: CLB_MUX_XY]
MUX_Y	[enum: CLB_MUX_XY]
MUX_RES	[enum: CLB_MUX_RES]
MUX_SET	[enum: CLB_MUX_SET]
READBACK_Q bit 0	!MAIN[3][2]

xc2000 CLB_W enum CLB_MODE
CLB.MODE	MAIN[8][0]
FGM	1
FG	0

xc2000 CLB_W enum FF_MODE
CLB.FF_MODE	MAIN[8][2]
FF	1
LATCH	0

xc2000 CLB_W enum CLB_MUX_I1
CLB.MUX_F1	MAIN[10][1]
CLB.MUX_G1	MAIN[6][1]
A	0
B	1

xc2000 CLB_W enum CLB_MUX_I2
CLB.MUX_F2	MAIN[11][1]
CLB.MUX_G2	MAIN[5][1]
B	0
C	1

xc2000 CLB_W enum CLB_MUX_I3
CLB.MUX_F3	MAIN[16][1]	MAIN[17][1]
CLB.MUX_G3	MAIN[1][1]	MAIN[0][1]
C	0	1
D	1	0
Q	1	1

xc2000 CLB_W enum CLB_MUX_XY
CLB.MUX_X	MAIN[7][2]	MAIN[6][2]
CLB.MUX_Y	MAIN[4][2]	MAIN[5][2]
F	0	1
G	1	0
Q	1	1

xc2000 CLB_W enum CLB_MUX_RES
CLB.MUX_RES	MAIN[16][2]	MAIN[17][2]
D	0	1
G	0	0
TIE_0	1	1

xc2000 CLB_W enum CLB_MUX_SET
CLB.MUX_SET	MAIN[15][2]	MAIN[14][2]
A	1	1
F	1	0
TIE_0	0	1

Bels IO

xc2000 CLB_W bel IO pins
Pin	Direction	IO_W[0]	IO_W[1]
O	in	CELL.IMUX_IO_W_O[0]	CELL.IMUX_IO_W_O[1]
T	in	CELL.IMUX_IO_W_T[0]	CELL.IMUX_IO_W_T[1]
K	in	CELL.IOCLK_W	CELL.IOCLK_W
I	out	CELL.OUT_IO_W_I[0]	CELL.OUT_IO_W_I[1]

xc2000 CLB_W bel IO attribute bits
Attribute	IO_W[0]	IO_W[1]
MUX_I	[enum: IO_MUX_I]	[enum: IO_MUX_I]
READBACK_Q bit 0	!MAIN[18][5]	!MAIN[20][0]

xc2000 CLB_W enum IO_MUX_I
IO_W[0].MUX_I	MAIN[20][7]
IO_W[1].MUX_I	MAIN[19][0]
PAD	0
Q	1

Bel wires

xc2000 CLB_W bel wires
Wire	Pins
CELL.IOCLK_W	IO_W[0].K, IO_W[1].K
CELL.IMUX_CLB_A	CLB.A
CELL.IMUX_CLB_B	CLB.B
CELL.IMUX_CLB_C	CLB.C
CELL.IMUX_CLB_D_N	CLB.D
CELL.IMUX_CLB_K	CLB.K
CELL.IMUX_IO_W_O[0]	IO_W[0].O
CELL.IMUX_IO_W_O[1]	IO_W[1].O
CELL.IMUX_IO_W_T[0]	IO_W[0].T
CELL.IMUX_IO_W_T[1]	IO_W[1].T
CELL.OUT_CLB_X	CLB.X
CELL.OUT_CLB_Y	CLB.Y
CELL.OUT_IO_W_I[0]	IO_W[0].I
CELL.OUT_IO_W_I[1]	IO_W[1].I

Bitstream

xc2000 CLB_W rect MAIN
Bit	Frame
Bit	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B7	IO_W[0]: MUX_I bit 0	INT: mux CELL.IMUX_IO_W_O[0] bit 0	INT: mux CELL.IMUX_IO_W_O[0] bit 2	INT: mux CELL.IMUX_IO_W_O[0] bit 3	INT: !bipass CELL.SINGLE_VW[0] = CELL.SINGLE_VW_S[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_VW[0]	INT: !bipass CELL.SINGLE_VW[0] = CELL.SINGLE_VW_S[1]	INT: !bipass CELL.SINGLE_VW[1] = CELL.SINGLE_VW_S[0]	INT: !bipass CELL.SINGLE_VW[1] = CELL.SINGLE_VW_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_VW_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_VW[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_VW[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_VW_S[1]	-	-	-	-	INT: !bipass CELL.SINGLE_VW[2] = CELL.SINGLE_VW_S[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_VW[3]	INT: !bipass CELL.SINGLE_VW[2] = CELL.SINGLE_VW_S[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_VW[2]
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_VW_S[3]	INT: !bipass CELL.SINGLE_VW[3] = CELL.SINGLE_VW_S[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_VW_S[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_VW[3]
B5	-	-	IO_W[0]: ! READBACK_Q bit 0	INT: mux CELL.IMUX_IO_W_O[0] bit 1	INT: !bipass CELL.SINGLE_VW[0] = CELL.LONG_H	INT: !bipass CELL.LONG_H = CELL.LONG_IO_W	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_VW_S[0]	INT: !pass CELL.LONG_H ← CELL.OUT_IO_W_I_S1	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_W_I_S1	INT: !bipass CELL.SINGLE_H[0] = CELL.LONG_V[0]	INT: !bipass CELL.LONG_H = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_VW_S[3]	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_W_I[0]	INT: !pass CELL.SINGLE_VW[2] ← CELL.OUT_IO_W_I[0]	INT: !bipass CELL.LONG_H = CELL.LONG_V[1]	INT: mux CELL.IMUX_CLB_A bit 0	INT: !bipass CELL.SINGLE_VW[3] = CELL.LONG_H	INT: mux CELL.IMUX_CLB_D bit 1	INT: !bipass CELL.SINGLE_VW[3] = CELL.SINGLE_VW_S[2]	-
B4	-	-	-	INT: mux CELL.IMUX_CLB_B bit 4	INT: mux CELL.IMUX_CLB_C bit 3	INT: mux CELL.IMUX_CLB_B bit 2	INT: mux CELL.IMUX_CLB_B bit 1	INT: mux CELL.IMUX_CLB_C bit 1	INT: mux CELL.IMUX_CLB_C bit 0	INT: mux CELL.IMUX_CLB_B bit 0	INT: mux CELL.IMUX_CLB_C bit 4	INT: !pass CELL.SINGLE_VW[3] ← CELL.OUT_IO_W_I[1]	INT: mux CELL.IMUX_CLB_C bit 2	INT: mux CELL.IMUX_CLB_B bit 5	INT: mux CELL.IMUX_CLB_B bit 3	-	-	-	-	-	-
B3	INT: mux CELL.IMUX_IO_W_T[0] bit 2	INT: mux CELL.IMUX_IO_W_T[0] bit 1	INT: mux CELL.IMUX_IO_W_T[0] bit 0	INT: !pass CELL.SINGLE_VW[0] ← CELL.OUT_IO_W_I[0]	INT: !pass CELL.LONG_IO_W ← CELL.OUT_IO_W_I[0]	INT: mux CELL.IMUX_CLB_K bit 1	INT: mux CELL.IMUX_CLB_K bit 2	INT: mux CELL.IMUX_CLB_K bit 0	CLB: !invert K	INT: mux CELL.IMUX_CLB_K bit 3	INT: !pass CELL.SINGLE_VW[1] ← CELL.OUT_IO_W_I[1]	-	INT: !pass CELL.LONG_V[0] ← CELL.OUT_IO_W_I[0]	INT: !pass CELL.LONG_V[1] ← CELL.OUT_IO_W_I[1]	-	INT: mux CELL.IMUX_CLB_D bit 0	INT: mux CELL.IMUX_CLB_D bit 2	INT: mux CELL.IMUX_CLB_A bit 2	INT: mux CELL.IMUX_CLB_A bit 1	INT: mux CELL.IMUX_CLB_A bit 3	INT: mux CELL.IMUX_CLB_D bit 3
B2	INT: mux CELL.IMUX_IO_W_T[1] bit 2	INT: mux CELL.IMUX_IO_W_T[1] bit 1	INT: mux CELL.IMUX_IO_W_T[1] bit 0	CLB: MUX_RES bit 0	CLB: MUX_RES bit 1	CLB: MUX_SET bit 1	CLB: MUX_SET bit 0	-	-	-	-	-	CLB: FF_MODE bit 0	CLB: MUX_X bit 1	CLB: MUX_X bit 0	CLB: MUX_Y bit 0	CLB: MUX_Y bit 1	CLB: ! READBACK_Q bit 0	-	-	-
B1	INT: mux CELL.IMUX_IO_W_O[1] bit 1	INT: mux CELL.IMUX_IO_W_O[1] bit 2	INT: mux CELL.IMUX_IO_W_O[1] bit 3	CLB: MUX_F3 bit 0	CLB: MUX_F3 bit 1	-	-	-	-	CLB: MUX_F2 bit 0	CLB: MUX_F1 bit 0	-	-	-	CLB: MUX_G1 bit 0	CLB: MUX_G2 bit 0	-	-	-	CLB: MUX_G3 bit 1	CLB: MUX_G3 bit 0
B0	IO_W[1]: ! READBACK_Q bit 0	IO_W[1]: MUX_I bit 0	INT: mux CELL.IMUX_IO_W_O[1] bit 0	CLB: ! F bit 1	CLB: ! F bit 0	CLB: ! F bit 2	CLB: ! F bit 3	CLB: ! F bit 5	CLB: ! F bit 4	CLB: ! F bit 6	CLB: ! F bit 7	-	CLB: MODE bit 0	CLB: ! G bit 7	CLB: ! G bit 6	CLB: ! G bit 4	CLB: ! G bit 5	CLB: ! G bit 3	CLB: ! G bit 2	CLB: ! G bit 0	CLB: ! G bit 1

Tile CLB_E

Cells: 2

Switchbox INT

xc2000 CLB_E switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[0]	CELL.OUT_IO_E_I[0]	!MAIN[1][4]
CELL.SINGLE_H[1]	CELL.OUT_IO_E_I_S1	!MAIN[3][4]
CELL.SINGLE_H[2]	CELL.OUT_IO_E_I[0]	!MAIN[7][4]
CELL.SINGLE_H[3]	CELL.OUT_IO_E_I_S1	!MAIN[4][4]
CELL.SINGLE_V[0]	CELL.OUT_CLB_Y_E	!MAIN[26][3]
CELL.SINGLE_V[1]	CELL.OUT_CLB_X_E	!MAIN[19][3]
CELL.SINGLE_V[2]	CELL.OUT_CLB_Y_E	!MAIN[15][3]
CELL.SINGLE_V[3]	CELL.OUT_CLB_X_E	!MAIN[18][4]
CELL.SINGLE_V[4]	CELL.OUT_CLB_Y_E	!MAIN[25][3]
CELL.SINGLE_VE[0]	CELL.OUT_CLB_Y	!MAIN[4][3]
CELL.SINGLE_VE[0]	CELL.OUT_IO_E_I[1]	!MAIN[3][1]
CELL.SINGLE_VE[1]	CELL.OUT_CLB_X	!MAIN[3][3]
CELL.SINGLE_VE[1]	CELL.OUT_IO_E_I[0]	!MAIN[2][4]
CELL.SINGLE_VE[2]	CELL.OUT_CLB_Y	!MAIN[6][3]
CELL.SINGLE_VE[2]	CELL.OUT_IO_E_I[1]	!MAIN[5][1]
CELL.SINGLE_VE[3]	CELL.OUT_CLB_X	!MAIN[8][3]
CELL.SINGLE_VE[3]	CELL.OUT_IO_E_I[0]	!MAIN[8][4]
CELL.LONG_H	CELL.OUT_IO_E_I[0]	!MAIN[6][2]
CELL.LONG_V[0]	CELL.OUT_CLB_X_E	!MAIN[17][3]
CELL.LONG_V[1]	CELL.OUT_CLB_Y_E	!MAIN[16][3]
CELL.LONG_VE[0]	CELL.OUT_CLB_Y	!MAIN[5][3]
CELL.LONG_VE[0]	CELL.OUT_IO_E_I[1]	!MAIN[4][1]
CELL.LONG_VE[1]	CELL.OUT_CLB_X	!MAIN[2][3]
CELL.LONG_VE[1]	CELL.OUT_IO_E_I[0]	!MAIN[0][4]
CELL.LONG_IO_E	CELL.OUT_CLB_Y	!MAIN[7][3]
CELL.LONG_IO_E	CELL.OUT_IO_E_I[1]	!MAIN[7][2]

xc2000 CLB_E switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.SINGLE_H_E[0]	!MAIN[23][7]
CELL.SINGLE_H[0]	CELL.SINGLE_H_E[1]	!MAIN[24][7]
CELL.SINGLE_H[0]	CELL.SINGLE_V[1]	!MAIN[19][6]
CELL.SINGLE_H[0]	CELL.SINGLE_V_S[0]	!MAIN[18][5]
CELL.SINGLE_H[0]	CELL.SINGLE_V_S[1]	!MAIN[20][7]
CELL.SINGLE_H[0]	CELL.SINGLE_VE[0]	!MAIN[2][5]
CELL.SINGLE_H[0]	CELL.SINGLE_VE_S[0]	!MAIN[1][6]
CELL.SINGLE_H[0]	CELL.SINGLE_VE_S[1]	!MAIN[1][7]
CELL.SINGLE_H[0]	CELL.LONG_V[1]	!MAIN[15][5]
CELL.SINGLE_H[0]	CELL.LONG_VE[1]	!MAIN[0][5]
CELL.SINGLE_H[1]	CELL.SINGLE_H_E[0]	!MAIN[25][6]
CELL.SINGLE_H[1]	CELL.SINGLE_H_E[1]	!MAIN[24][6]
CELL.SINGLE_H[1]	CELL.SINGLE_V[0]	!MAIN[18][7]
CELL.SINGLE_H[1]	CELL.SINGLE_V[1]	!MAIN[19][7]
CELL.SINGLE_H[1]	CELL.SINGLE_V[4]	!MAIN[20][5]
CELL.SINGLE_H[1]	CELL.SINGLE_V_S[1]	!MAIN[20][6]
CELL.SINGLE_H[1]	CELL.SINGLE_V_S[4]	!MAIN[23][5]
CELL.SINGLE_H[1]	CELL.SINGLE_VE[0]	!MAIN[3][5]
CELL.SINGLE_H[1]	CELL.SINGLE_VE[1]	!MAIN[0][7]
CELL.SINGLE_H[1]	CELL.SINGLE_VE_S[0]	!MAIN[0][6]
CELL.SINGLE_H[1]	CELL.LONG_V[0]	!MAIN[19][5]
CELL.SINGLE_H[1]	CELL.LONG_VE[0]	!MAIN[6][5]
CELL.SINGLE_H[2]	CELL.SINGLE_H_E[2]	!MAIN[12][7]
CELL.SINGLE_H[2]	CELL.SINGLE_H_E[3]	!MAIN[10][6]
CELL.SINGLE_H[2]	CELL.SINGLE_V[3]	!MAIN[10][5]
CELL.SINGLE_H[2]	CELL.SINGLE_V[4]	!MAIN[21][5]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[2]	!MAIN[12][6]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[3]	!MAIN[10][7]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[4]	!MAIN[22][5]
CELL.SINGLE_H[2]	CELL.SINGLE_VE[2]	!MAIN[6][6]
CELL.SINGLE_H[2]	CELL.SINGLE_VE_S[2]	!MAIN[6][7]
CELL.SINGLE_H[2]	CELL.SINGLE_VE_S[3]	!MAIN[8][7]
CELL.SINGLE_H[2]	CELL.LONG_V[1]	!MAIN[14][5]
CELL.SINGLE_H[2]	CELL.LONG_VE[1]	!MAIN[6][4]
CELL.SINGLE_H[3]	CELL.SINGLE_H_E[2]	!MAIN[11][7]
CELL.SINGLE_H[3]	CELL.SINGLE_H_E[3]	!MAIN[11][6]
CELL.SINGLE_H[3]	CELL.SINGLE_V[2]	!MAIN[13][6]
CELL.SINGLE_H[3]	CELL.SINGLE_V[3]	!MAIN[9][6]
CELL.SINGLE_H[3]	CELL.SINGLE_V_S[3]	!MAIN[9][7]
CELL.SINGLE_H[3]	CELL.SINGLE_VE[2]	!MAIN[4][6]
CELL.SINGLE_H[3]	CELL.SINGLE_VE[3]	!MAIN[7][6]
CELL.SINGLE_H[3]	CELL.SINGLE_VE_S[2]	!MAIN[4][7]
CELL.SINGLE_H[3]	CELL.LONG_V[0]	!MAIN[16][5]
CELL.SINGLE_H[3]	CELL.LONG_VE[0]	!MAIN[5][4]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V[0]	!MAIN[26][5]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V_S[0]	!MAIN[25][7]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V_S[1]	!MAIN[23][6]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V[0]	!MAIN[26][6]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V[1]	!MAIN[22][6]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V_S[0]	!MAIN[26][7]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V[2]	!MAIN[16][6]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V_S[2]	!MAIN[15][7]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V_S[3]	!MAIN[17][5]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V[2]	!MAIN[16][7]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V[3]	!MAIN[17][7]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V_S[2]	!MAIN[15][6]
CELL.SINGLE_V[0]	CELL.SINGLE_V_S[0]	!MAIN[18][6]
CELL.SINGLE_V[0]	CELL.SINGLE_V_S[1]	!MAIN[21][7]
CELL.SINGLE_V[0]	CELL.LONG_H	!MAIN[25][5]
CELL.SINGLE_V[1]	CELL.SINGLE_V_S[0]	!MAIN[22][7]
CELL.SINGLE_V[1]	CELL.SINGLE_V_S[1]	!MAIN[21][6]
CELL.SINGLE_V[2]	CELL.SINGLE_V_S[2]	!MAIN[14][6]
CELL.SINGLE_V[2]	CELL.SINGLE_V_S[3]	!MAIN[13][7]
CELL.SINGLE_V[3]	CELL.SINGLE_V_S[2]	!MAIN[14][7]
CELL.SINGLE_V[3]	CELL.SINGLE_V_S[3]	!MAIN[17][6]
CELL.SINGLE_V[3]	CELL.LONG_H	!MAIN[12][5]
CELL.SINGLE_V[4]	CELL.SINGLE_V_S[4]	!MAIN[24][5]
CELL.SINGLE_VE[0]	CELL.SINGLE_VE_S[0]	!MAIN[3][6]
CELL.SINGLE_VE[0]	CELL.SINGLE_VE_S[1]	!MAIN[3][7]
CELL.SINGLE_VE[0]	CELL.LONG_H	!MAIN[4][5]
CELL.SINGLE_VE[1]	CELL.SINGLE_VE_S[0]	!MAIN[2][7]
CELL.SINGLE_VE[1]	CELL.SINGLE_VE_S[1]	!MAIN[2][6]
CELL.SINGLE_VE[2]	CELL.SINGLE_VE_S[2]	!MAIN[5][7]
CELL.SINGLE_VE[2]	CELL.SINGLE_VE_S[3]	!MAIN[5][6]
CELL.SINGLE_VE[3]	CELL.SINGLE_VE_S[2]	!MAIN[7][7]
CELL.SINGLE_VE[3]	CELL.SINGLE_VE_S[3]	!MAIN[8][6]
CELL.SINGLE_VE[3]	CELL.LONG_H	!MAIN[8][5]
CELL.LONG_H	CELL.LONG_VE[0]	!MAIN[5][5]
CELL.LONG_H	CELL.LONG_VE[1]	!MAIN[1][5]
CELL.LONG_H	CELL.LONG_IO_E	!MAIN[7][5]

xc2000 CLB_E switchbox INT muxes IMUX_CLB_A
Bits				Destination
MAIN[10][3]	MAIN[12][3]	MAIN[11][3]	MAIN[13][5]	CELL.IMUX_CLB_A
				Source
0	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	CELL.SINGLE_H[0]
0	1	0	0	CELL.SINGLE_H[2]
0	1	1	0	CELL.OUT_CLB_X_S
1	1	0	1	CELL.LONG_H
1	1	1	1	CELL.SINGLE_H[1]

xc2000 CLB_E switchbox INT muxes IMUX_CLB_B
Bits						Destination
MAIN[16][4]	MAIN[26][4]	MAIN[15][4]	MAIN[24][4]	MAIN[23][4]	MAIN[20][4]	CELL.IMUX_CLB_B
						Source
0	0	0	1	1	1	CELL.OUT_CLB_Y_E
0	0	1	1	1	1	CELL.SINGLE_V[0]
0	1	0	0	1	1	CELL.SINGLE_V[1]
0	1	0	1	0	1	CELL.SINGLE_V[4]
0	1	0	1	1	0	CELL.LONG_V[0]
0	1	1	0	1	1	CELL.GCLK
0	1	1	1	0	1	CELL.SINGLE_V[3]
0	1	1	1	1	0	CELL.LONG_V[1]
1	1	0	1	1	1	CELL.OUT_CLB_X_S
1	1	1	1	1	1	CELL.SINGLE_V[2]

xc2000 CLB_E switchbox INT muxes IMUX_CLB_C
Bits					Destination
MAIN[19][4]	MAIN[25][4]	MAIN[17][4]	MAIN[22][4]	MAIN[21][4]	CELL.IMUX_CLB_C
					Source
0	0	0	1	1	CELL.SINGLE_V[0]
0	0	1	1	1	CELL.SINGLE_V[1]
0	1	0	0	1	CELL.SINGLE_V[3]
0	1	0	1	0	CELL.LONG_V[1]
0	1	1	0	1	CELL.SINGLE_V[4]
0	1	1	1	0	CELL.LONG_V[0]
1	1	0	1	1	CELL.SINGLE_V[2]
1	1	1	1	1	CELL.OUT_CLB_X_N

xc2000 CLB_E switchbox INT muxes IMUX_CLB_D
Bits				Destination
MAIN[9][3]	MAIN[13][3]	MAIN[11][5]	MAIN[14][3]	CELL.IMUX_CLB_D
				Source
0	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	CELL.SINGLE_H[0]
0	1	0	0	CELL.SINGLE_H[2]
0	1	1	0	CELL.OUT_CLB_X
1	1	0	1	CELL.LONG_H
1	1	1	1	CELL.SINGLE_H[1]

xc2000 CLB_E switchbox INT muxes IMUX_CLB_K
Bits				Destination
MAIN[20][3]	MAIN[23][3]	MAIN[24][3]	MAIN[22][3]	CELL.IMUX_CLB_K
				Source
0	0	1	1	CELL.LONG_V[1]
0	1	0	1	CELL.GCLK
0	1	1	0	CELL.SPECIAL_CLB_C
0	1	1	1	~CELL.SPECIAL_CLB_G
1	1	1	1	off

xc2000 CLB_E switchbox INT muxes IMUX_IO_E_O[0]
Bits					Destination
MAIN[0][2]	MAIN[1][3]	MAIN[1][2]	MAIN[2][2]	MAIN[3][2]	CELL.IMUX_IO_E_O[0]
					Source
0	0	0	1	1	CELL.SINGLE_H[1]
0	0	1	0	1	CELL.SINGLE_H[3]
0	0	1	1	0	CELL.OUT_CLB_X
0	1	0	1	1	CELL.SINGLE_VE[2]
0	1	1	0	1	CELL.LONG_VE[0]
0	1	1	1	0	CELL.SINGLE_VE[0]
1	0	1	1	1	CELL.OUT_CLB_Y
1	1	1	1	1	CELL.LONG_IO_E

xc2000 CLB_E switchbox INT muxes IMUX_IO_E_O[1]
Bits					Destination
MAIN[6][0]	MAIN[6][1]	MAIN[7][1]	MAIN[7][0]	MAIN[8][0]	CELL.IMUX_IO_E_O[1]
					Source
0	0	0	1	1	CELL.SINGLE_VE[3]
0	0	1	0	1	CELL.LONG_VE[1]
0	0	1	1	0	S.LONG_H
0	1	1	1	1	CELL.SINGLE_VE[1]
1	0	0	1	1	CELL.OUT_CLB_X
1	0	1	0	1	S.SINGLE_H[0]
1	0	1	1	0	S.SINGLE_H[2]
1	1	1	1	1	CELL.OUT_CLB_Y

xc2000 CLB_E switchbox INT muxes IMUX_IO_E_T[0]
Bits			Destination
MAIN[2][1]	MAIN[3][0]	MAIN[1][1]	CELL.IMUX_IO_E_T[0]
			Source
0	0	1	CELL.LONG_VE[1]
0	1	1	CELL.SINGLE_VE[3]
1	0	0	CELL.TIE_0
1	0	1	CELL.LONG_IO_E
1	1	0	CELL.TIE_1
1	1	1	CELL.SINGLE_VE[1]

xc2000 CLB_E switchbox INT muxes IMUX_IO_E_T[1]
Bits			Destination
MAIN[5][0]	MAIN[5][2]	MAIN[4][0]	CELL.IMUX_IO_E_T[1]
			Source
0	0	1	CELL.SINGLE_VE[1]
0	1	0	CELL.TIE_0
0	1	1	CELL.SINGLE_VE[3]
1	0	1	CELL.LONG_IO_E
1	1	0	CELL.TIE_1
1	1	1	CELL.LONG_VE[1]

Bels CLB

xc2000 CLB_E bel CLB pins
Pin	Direction	CLB
A	in	CELL.IMUX_CLB_A
B	in	CELL.IMUX_CLB_B
C	in	CELL.IMUX_CLB_C
D	in	CELL.IMUX_CLB_D_N
K	in	CELL.IMUX_CLB_K invert by !MAIN[21][3]
X	out	CELL.OUT_CLB_X
Y	out	CELL.OUT_CLB_Y

xc2000 CLB_E bel CLB attribute bits
Attribute	CLB
F bit 0	!MAIN[25][0]
F bit 1	!MAIN[26][0]
F bit 2	!MAIN[24][0]
F bit 3	!MAIN[23][0]
F bit 4	!MAIN[21][0]
F bit 5	!MAIN[22][0]
F bit 6	!MAIN[20][0]
F bit 7	!MAIN[19][0]
G bit 0	!MAIN[10][0]
G bit 1	!MAIN[9][0]
G bit 2	!MAIN[11][0]
G bit 3	!MAIN[12][0]
G bit 4	!MAIN[14][0]
G bit 5	!MAIN[13][0]
G bit 6	!MAIN[15][0]
G bit 7	!MAIN[16][0]
MODE	[enum: CLB_MODE]
FF_MODE	[enum: FF_MODE]
MUX_F1	[enum: CLB_MUX_I1]
MUX_G1	[enum: CLB_MUX_I1]
MUX_F2	[enum: CLB_MUX_I2]
MUX_G2	[enum: CLB_MUX_I2]
MUX_F3	[enum: CLB_MUX_I3]
MUX_G3	[enum: CLB_MUX_I3]
MUX_X	[enum: CLB_MUX_XY]
MUX_Y	[enum: CLB_MUX_XY]
MUX_RES	[enum: CLB_MUX_RES]
MUX_SET	[enum: CLB_MUX_SET]
READBACK_Q bit 0	!MAIN[12][2]

xc2000 CLB_E enum CLB_MODE
CLB.MODE	MAIN[17][0]
FGM	1
FG	0

xc2000 CLB_E enum FF_MODE
CLB.FF_MODE	MAIN[17][2]
FF	1
LATCH	0

xc2000 CLB_E enum CLB_MUX_I1
CLB.MUX_F1	MAIN[19][1]
CLB.MUX_G1	MAIN[15][1]
A	0
B	1

xc2000 CLB_E enum CLB_MUX_I2
CLB.MUX_F2	MAIN[20][1]
CLB.MUX_G2	MAIN[14][1]
B	0
C	1

xc2000 CLB_E enum CLB_MUX_I3
CLB.MUX_F3	MAIN[25][1]	MAIN[26][1]
CLB.MUX_G3	MAIN[10][1]	MAIN[9][1]
C	0	1
D	1	0
Q	1	1

xc2000 CLB_E enum CLB_MUX_XY
CLB.MUX_X	MAIN[16][2]	MAIN[15][2]
CLB.MUX_Y	MAIN[13][2]	MAIN[14][2]
F	0	1
G	1	0
Q	1	1

xc2000 CLB_E enum CLB_MUX_RES
CLB.MUX_RES	MAIN[25][2]	MAIN[26][2]
D	0	1
G	0	0
TIE_0	1	1

xc2000 CLB_E enum CLB_MUX_SET
CLB.MUX_SET	MAIN[24][2]	MAIN[23][2]
A	1	1
F	1	0
TIE_0	0	1

Bels IO

xc2000 CLB_E bel IO pins
Pin	Direction	IO_E[0]	IO_E[1]
O	in	CELL.IMUX_IO_E_O[0]	CELL.IMUX_IO_E_O[1]
T	in	CELL.IMUX_IO_E_T[0]	CELL.IMUX_IO_E_T[1]
K	in	CELL.IOCLK_E	CELL.IOCLK_E
I	out	CELL.OUT_IO_E_I[0]	CELL.OUT_IO_E_I[1]

xc2000 CLB_E bel IO attribute bits
Attribute	IO_E[0]	IO_E[1]
MUX_I	[enum: IO_MUX_I]	[enum: IO_MUX_I]
READBACK_Q bit 0	!MAIN[0][3]	!MAIN[8][2]

xc2000 CLB_E enum IO_MUX_I
IO_E[0].MUX_I	MAIN[0][1]
IO_E[1].MUX_I	MAIN[2][0]
PAD	0
Q	1

Bel wires

xc2000 CLB_E bel wires
Wire	Pins
CELL.IOCLK_E	IO_E[0].K, IO_E[1].K
CELL.IMUX_CLB_A	CLB.A
CELL.IMUX_CLB_B	CLB.B
CELL.IMUX_CLB_C	CLB.C
CELL.IMUX_CLB_D_N	CLB.D
CELL.IMUX_CLB_K	CLB.K
CELL.IMUX_IO_E_O[0]	IO_E[0].O
CELL.IMUX_IO_E_O[1]	IO_E[1].O
CELL.IMUX_IO_E_T[0]	IO_E[0].T
CELL.IMUX_IO_E_T[1]	IO_E[1].T
CELL.OUT_CLB_X	CLB.X
CELL.OUT_CLB_Y	CLB.Y
CELL.OUT_IO_E_I[0]	IO_E[0].I
CELL.OUT_IO_E_I[1]	IO_E[1].I

Bitstream

xc2000 CLB_E rect MAIN
Bit	Frame
Bit	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B7	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_VE_S[3]	INT: !bipass CELL.SINGLE_VE[3] = CELL.SINGLE_VE_S[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_VE_S[2]	INT: !bipass CELL.SINGLE_VE[2] = CELL.SINGLE_VE_S[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_VE_S[2]	INT: !bipass CELL.SINGLE_VE[0] = CELL.SINGLE_VE_S[1]	INT: !bipass CELL.SINGLE_VE[1] = CELL.SINGLE_VE_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_VE_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_VE[1]
B6	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_VE[3] = CELL.SINGLE_VE_S[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_VE[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_VE[2]	INT: !bipass CELL.SINGLE_VE[2] = CELL.SINGLE_VE_S[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_VE[2]	INT: !bipass CELL.SINGLE_VE[0] = CELL.SINGLE_VE_S[0]	INT: !bipass CELL.SINGLE_VE[1] = CELL.SINGLE_VE_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_VE_S[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_VE_S[0]
B5	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.LONG_H	INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[4]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[4]	INT: !bipass CELL.SINGLE_H[1] = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_H[2] = CELL.LONG_V[1]	INT: mux CELL.IMUX_CLB_A bit 0	INT: !bipass CELL.SINGLE_V[3] = CELL.LONG_H	INT: mux CELL.IMUX_CLB_D bit 1	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[3]	-	INT: !bipass CELL.SINGLE_VE[3] = CELL.LONG_H	INT: !bipass CELL.LONG_H = CELL.LONG_IO_E	INT: !bipass CELL.SINGLE_H[1] = CELL.LONG_VE[0]	INT: !bipass CELL.LONG_H = CELL.LONG_VE[0]	INT: !bipass CELL.SINGLE_VE[0] = CELL.LONG_H	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_VE[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_VE[0]	INT: !bipass CELL.LONG_H = CELL.LONG_VE[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.LONG_VE[1]
B4	INT: mux CELL.IMUX_CLB_B bit 4	INT: mux CELL.IMUX_CLB_C bit 3	INT: mux CELL.IMUX_CLB_B bit 2	INT: mux CELL.IMUX_CLB_B bit 1	INT: mux CELL.IMUX_CLB_C bit 1	INT: mux CELL.IMUX_CLB_C bit 0	INT: mux CELL.IMUX_CLB_B bit 0	INT: mux CELL.IMUX_CLB_C bit 4	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_X_E	INT: mux CELL.IMUX_CLB_C bit 2	INT: mux CELL.IMUX_CLB_B bit 5	INT: mux CELL.IMUX_CLB_B bit 3	-	-	-	-	-	-	INT: !pass CELL.SINGLE_VE[3] ← CELL.OUT_IO_E_I[0]	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_E_I[0]	INT: !bipass CELL.SINGLE_H[2] = CELL.LONG_VE[1]	INT: !bipass CELL.SINGLE_H[3] = CELL.LONG_VE[0]	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_E_I_S1	INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_E_I_S1	INT: !pass CELL.SINGLE_VE[1] ← CELL.OUT_IO_E_I[0]	INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_E_I[0]	INT: !pass CELL.LONG_VE[1] ← CELL.OUT_IO_E_I[0]
B3	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_Y_E	INT: mux CELL.IMUX_CLB_K bit 1	INT: mux CELL.IMUX_CLB_K bit 2	INT: mux CELL.IMUX_CLB_K bit 0	CLB: !invert K	INT: mux CELL.IMUX_CLB_K bit 3	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X_E	-	INT: !pass CELL.LONG_V[0] ← CELL.OUT_CLB_X_E	INT: !pass CELL.LONG_V[1] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E	INT: mux CELL.IMUX_CLB_D bit 0	INT: mux CELL.IMUX_CLB_D bit 2	INT: mux CELL.IMUX_CLB_A bit 2	INT: mux CELL.IMUX_CLB_A bit 1	INT: mux CELL.IMUX_CLB_A bit 3	INT: mux CELL.IMUX_CLB_D bit 3	INT: !pass CELL.SINGLE_VE[3] ← CELL.OUT_CLB_X	INT: !pass CELL.LONG_IO_E ← CELL.OUT_CLB_Y	INT: !pass CELL.SINGLE_VE[2] ← CELL.OUT_CLB_Y	INT: !pass CELL.LONG_VE[0] ← CELL.OUT_CLB_Y	INT: !pass CELL.SINGLE_VE[0] ← CELL.OUT_CLB_Y	INT: !pass CELL.SINGLE_VE[1] ← CELL.OUT_CLB_X	INT: !pass CELL.LONG_VE[1] ← CELL.OUT_CLB_X	INT: mux CELL.IMUX_IO_E_O[0] bit 3	IO_E[0]: ! READBACK_Q bit 0
B2	CLB: MUX_RES bit 0	CLB: MUX_RES bit 1	CLB: MUX_SET bit 1	CLB: MUX_SET bit 0	-	-	-	-	-	CLB: FF_MODE bit 0	CLB: MUX_X bit 1	CLB: MUX_X bit 0	CLB: MUX_Y bit 0	CLB: MUX_Y bit 1	CLB: ! READBACK_Q bit 0	-	-	-	IO_E[1]: ! READBACK_Q bit 0	INT: !pass CELL.LONG_IO_E ← CELL.OUT_IO_E_I[1]	INT: !pass CELL.LONG_H ← CELL.OUT_IO_E_I[0]	INT: mux CELL.IMUX_IO_E_T[1] bit 1	-	INT: mux CELL.IMUX_IO_E_O[0] bit 0	INT: mux CELL.IMUX_IO_E_O[0] bit 1	INT: mux CELL.IMUX_IO_E_O[0] bit 2	INT: mux CELL.IMUX_IO_E_O[0] bit 4
B1	CLB: MUX_F3 bit 0	CLB: MUX_F3 bit 1	-	-	-	-	CLB: MUX_F2 bit 0	CLB: MUX_F1 bit 0	-	-	-	CLB: MUX_G1 bit 0	CLB: MUX_G2 bit 0	-	-	-	CLB: MUX_G3 bit 1	CLB: MUX_G3 bit 0	-	INT: mux CELL.IMUX_IO_E_O[1] bit 2	INT: mux CELL.IMUX_IO_E_O[1] bit 3	INT: !pass CELL.SINGLE_VE[2] ← CELL.OUT_IO_E_I[1]	INT: !pass CELL.LONG_VE[0] ← CELL.OUT_IO_E_I[1]	INT: !pass CELL.SINGLE_VE[0] ← CELL.OUT_IO_E_I[1]	INT: mux CELL.IMUX_IO_E_T[0] bit 2	INT: mux CELL.IMUX_IO_E_T[0] bit 0	IO_E[0]: MUX_I bit 0
B0	CLB: ! F bit 1	CLB: ! F bit 0	CLB: ! F bit 2	CLB: ! F bit 3	CLB: ! F bit 5	CLB: ! F bit 4	CLB: ! F bit 6	CLB: ! F bit 7	-	CLB: MODE bit 0	CLB: ! G bit 7	CLB: ! G bit 6	CLB: ! G bit 4	CLB: ! G bit 5	CLB: ! G bit 3	CLB: ! G bit 2	CLB: ! G bit 0	CLB: ! G bit 1	INT: mux CELL.IMUX_IO_E_O[1] bit 0	INT: mux CELL.IMUX_IO_E_O[1] bit 1	INT: mux CELL.IMUX_IO_E_O[1] bit 4	INT: mux CELL.IMUX_IO_E_T[1] bit 2	INT: mux CELL.IMUX_IO_E_T[1] bit 0	INT: mux CELL.IMUX_IO_E_T[0] bit 1	IO_E[1]: MUX_I bit 0	-	-

Tile CLB_MW

Cells: 2

Switchbox INT

xc2000 CLB_MW switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[2]	CELL.OUT_IO_W_I_S1	!MAIN[12][5]
CELL.SINGLE_VW[1]	CELL.OUT_IO_W_I[1]	!MAIN[10][3]
CELL.SINGLE_VW[3]	CELL.OUT_IO_W_I[1]	!MAIN[9][4]
CELL.LONG_H	CELL.OUT_IO_W_I_S1	!MAIN[13][5]
CELL.LONG_V[1]	CELL.OUT_IO_W_I[1]	!MAIN[7][3]

xc2000 CLB_MW switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.SINGLE_VW[1]	!MAIN[10][7]
CELL.SINGLE_H[0]	CELL.SINGLE_VW_S[0]	!MAIN[14][5]
CELL.SINGLE_H[0]	CELL.SINGLE_VW_S[1]	!MAIN[11][7]
CELL.SINGLE_H[0]	CELL.LONG_V[0]	!MAIN[11][5]
CELL.SINGLE_H[1]	CELL.SINGLE_VW[0]	!MAIN[15][7]
CELL.SINGLE_H[1]	CELL.SINGLE_VW[1]	!MAIN[9][7]
CELL.SINGLE_H[1]	CELL.SINGLE_VW_S[1]	!MAIN[8][7]
CELL.SINGLE_H[1]	CELL.LONG_V[1]	!MAIN[9][5]
CELL.SINGLE_H[2]	CELL.SINGLE_VW[3]	!MAIN[2][7]
CELL.SINGLE_H[2]	CELL.SINGLE_VW_S[2]	!MAIN[1][6]
CELL.SINGLE_H[2]	CELL.SINGLE_VW_S[3]	!MAIN[3][6]
CELL.SINGLE_H[3]	CELL.SINGLE_VW[2]	!MAIN[0][7]
CELL.SINGLE_H[3]	CELL.SINGLE_VW[3]	!MAIN[0][6]
CELL.SINGLE_H[3]	CELL.SINGLE_VW_S[3]	!MAIN[8][5]
CELL.SINGLE_VW[0]	CELL.SINGLE_VW_S[0]	!MAIN[16][7]
CELL.SINGLE_VW[0]	CELL.SINGLE_VW_S[1]	!MAIN[14][7]
CELL.SINGLE_VW[0]	CELL.LONG_H	!MAIN[16][5]
CELL.SINGLE_VW[1]	CELL.SINGLE_VW_S[0]	!MAIN[13][7]
CELL.SINGLE_VW[1]	CELL.SINGLE_VW_S[1]	!MAIN[12][7]
CELL.SINGLE_VW[2]	CELL.SINGLE_VW_S[2]	!MAIN[1][7]
CELL.SINGLE_VW[2]	CELL.SINGLE_VW_S[3]	!MAIN[3][7]
CELL.SINGLE_VW[3]	CELL.SINGLE_VW_S[2]	!MAIN[1][5]
CELL.SINGLE_VW[3]	CELL.SINGLE_VW_S[3]	!MAIN[2][6]
CELL.SINGLE_VW[3]	CELL.LONG_H	!MAIN[3][5]
CELL.LONG_H	CELL.LONG_V[0]	!MAIN[10][5]
CELL.LONG_H	CELL.LONG_V[1]	!MAIN[5][5]
CELL.LONG_H	CELL.LONG_IO_W	!MAIN[15][5]

xc2000 CLB_MW switchbox INT muxes IMUX_CLB_A
Bits				Destination
MAIN[1][3]	MAIN[3][3]	MAIN[2][3]	MAIN[4][5]	CELL.IMUX_CLB_A
				Source
0	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	CELL.SINGLE_H[0]
0	1	0	0	CELL.SINGLE_H[2]
0	1	1	0	CELL.OUT_CLB_X_S
1	1	0	1	CELL.LONG_H
1	1	1	1	CELL.SINGLE_H[1]

xc2000 CLB_MW switchbox INT muxes IMUX_CLB_B
Bits						Destination
MAIN[7][4]	MAIN[17][4]	MAIN[6][4]	MAIN[15][4]	MAIN[14][4]	MAIN[11][4]	CELL.IMUX_CLB_B
						Source
0	0	0	1	1	1	CELL.OUT_IO_W_I[1]
0	0	1	1	1	1	CELL.SINGLE_VW[0]
0	1	0	0	1	1	CELL.SINGLE_VW[1]
0	1	0	1	0	1	CELL.LONG_IO_W
0	1	0	1	1	0	CELL.LONG_V[0]
0	1	1	0	1	1	CELL.GCLK
0	1	1	1	0	1	CELL.SINGLE_VW[3]
0	1	1	1	1	0	CELL.LONG_V[1]
1	1	0	1	1	1	CELL.OUT_CLB_X_S
1	1	1	1	1	1	CELL.SINGLE_VW[2]

xc2000 CLB_MW switchbox INT muxes IMUX_CLB_C
Bits					Destination
MAIN[10][4]	MAIN[16][4]	MAIN[8][4]	MAIN[13][4]	MAIN[12][4]	CELL.IMUX_CLB_C
					Source
0	0	0	1	1	CELL.SINGLE_VW[0]
0	0	1	1	1	CELL.SINGLE_VW[1]
0	1	0	0	1	CELL.SINGLE_VW[3]
0	1	0	1	0	CELL.LONG_V[1]
0	1	1	0	1	CELL.LONG_IO_W
0	1	1	1	0	CELL.LONG_V[0]
1	1	0	1	1	CELL.SINGLE_VW[2]
1	1	1	1	1	CELL.OUT_CLB_X_N

xc2000 CLB_MW switchbox INT muxes IMUX_CLB_D
Bits				Destination
MAIN[0][3]	MAIN[4][3]	MAIN[2][5]	MAIN[5][3]	CELL.IMUX_CLB_D
				Source
0	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	CELL.SINGLE_H[0]
0	1	0	0	CELL.SINGLE_H[2]
0	1	1	0	CELL.OUT_CLB_X
1	1	0	1	CELL.LONG_H
1	1	1	1	CELL.SINGLE_H[1]

xc2000 CLB_MW switchbox INT muxes IMUX_CLB_K
Bits				Destination
MAIN[11][3]	MAIN[14][3]	MAIN[15][3]	MAIN[13][3]	CELL.IMUX_CLB_K
				Source
0	0	1	1	CELL.LONG_V[1]
0	1	0	1	CELL.GCLK
0	1	1	0	CELL.SPECIAL_CLB_C
0	1	1	1	~CELL.SPECIAL_CLB_G
1	1	1	1	off

xc2000 CLB_MW switchbox INT muxes IMUX_IO_W_O[1]
Bits				Destination
MAIN[18][1]	MAIN[19][1]	MAIN[20][1]	MAIN[18][0]	CELL.IMUX_IO_W_O[1]
				Source
0	0	1	0	S.SINGLE_H[1]
0	0	1	1	CELL.SINGLE_VW[0]
0	1	0	0	CELL.LONG_V[0]
0	1	0	1	CELL.LONG_IO_W
1	1	1	0	S.SINGLE_H[3]
1	1	1	1	CELL.SINGLE_VW[2]

xc2000 CLB_MW switchbox INT muxes IMUX_IO_W_T[1]
Bits			Destination
MAIN[20][2]	MAIN[19][2]	MAIN[18][2]	CELL.IMUX_IO_W_T[1]
			Source
0	0	0	CELL.SINGLE_VW[0]
0	0	1	CELL.SINGLE_VW[2]
0	1	0	CELL.LONG_V[0]
0	1	1	CELL.LONG_IO_W
1	0	1	CELL.TIE_1
1	1	1	CELL.TIE_0

Bels CLB

xc2000 CLB_MW bel CLB pins
Pin	Direction	CLB
A	in	CELL.IMUX_CLB_A
B	in	CELL.IMUX_CLB_B
C	in	CELL.IMUX_CLB_C
D	in	CELL.IMUX_CLB_D_N
K	in	CELL.IMUX_CLB_K invert by !MAIN[12][3]
X	out	CELL.OUT_CLB_X
Y	out	CELL.OUT_CLB_Y

xc2000 CLB_MW bel CLB attribute bits
Attribute	CLB
F bit 0	!MAIN[16][0]
F bit 1	!MAIN[17][0]
F bit 2	!MAIN[15][0]
F bit 3	!MAIN[14][0]
F bit 4	!MAIN[12][0]
F bit 5	!MAIN[13][0]
F bit 6	!MAIN[11][0]
F bit 7	!MAIN[10][0]
G bit 0	!MAIN[1][0]
G bit 1	!MAIN[0][0]
G bit 2	!MAIN[2][0]
G bit 3	!MAIN[3][0]
G bit 4	!MAIN[5][0]
G bit 5	!MAIN[4][0]
G bit 6	!MAIN[6][0]
G bit 7	!MAIN[7][0]
MODE	[enum: CLB_MODE]
FF_MODE	[enum: FF_MODE]
MUX_F1	[enum: CLB_MUX_I1]
MUX_G1	[enum: CLB_MUX_I1]
MUX_F2	[enum: CLB_MUX_I2]
MUX_G2	[enum: CLB_MUX_I2]
MUX_F3	[enum: CLB_MUX_I3]
MUX_G3	[enum: CLB_MUX_I3]
MUX_X	[enum: CLB_MUX_XY]
MUX_Y	[enum: CLB_MUX_XY]
MUX_RES	[enum: CLB_MUX_RES]
MUX_SET	[enum: CLB_MUX_SET]
READBACK_Q bit 0	!MAIN[3][2]

xc2000 CLB_MW enum CLB_MODE
CLB.MODE	MAIN[8][0]
FGM	1
FG	0

xc2000 CLB_MW enum FF_MODE
CLB.FF_MODE	MAIN[8][2]
FF	1
LATCH	0

xc2000 CLB_MW enum CLB_MUX_I1
CLB.MUX_F1	MAIN[10][1]
CLB.MUX_G1	MAIN[6][1]
A	0
B	1

xc2000 CLB_MW enum CLB_MUX_I2
CLB.MUX_F2	MAIN[11][1]
CLB.MUX_G2	MAIN[5][1]
B	0
C	1

xc2000 CLB_MW enum CLB_MUX_I3
CLB.MUX_F3	MAIN[16][1]	MAIN[17][1]
CLB.MUX_G3	MAIN[1][1]	MAIN[0][1]
C	0	1
D	1	0
Q	1	1

xc2000 CLB_MW enum CLB_MUX_XY
CLB.MUX_X	MAIN[7][2]	MAIN[6][2]
CLB.MUX_Y	MAIN[4][2]	MAIN[5][2]
F	0	1
G	1	0
Q	1	1

xc2000 CLB_MW enum CLB_MUX_RES
CLB.MUX_RES	MAIN[16][2]	MAIN[17][2]
D	0	1
G	0	0
TIE_0	1	1

xc2000 CLB_MW enum CLB_MUX_SET
CLB.MUX_SET	MAIN[15][2]	MAIN[14][2]
A	1	1
F	1	0
TIE_0	0	1

Bels IO

xc2000 CLB_MW bel IO pins
Pin	Direction	IO_W[1]
O	in	CELL.IMUX_IO_W_O[1]
T	in	CELL.IMUX_IO_W_T[1]
K	in	CELL.IOCLK_W
I	out	CELL.OUT_IO_W_I[1]

xc2000 CLB_MW bel IO attribute bits
Attribute	IO_W[1]
MUX_I	[enum: IO_MUX_I]
READBACK_Q bit 0	!MAIN[20][0]

xc2000 CLB_MW enum IO_MUX_I
IO_W[1].MUX_I	MAIN[19][0]
PAD	0
Q	1

Bel wires

xc2000 CLB_MW bel wires
Wire	Pins
CELL.IOCLK_W	IO_W[1].K
CELL.IMUX_CLB_A	CLB.A
CELL.IMUX_CLB_B	CLB.B
CELL.IMUX_CLB_C	CLB.C
CELL.IMUX_CLB_D_N	CLB.D
CELL.IMUX_CLB_K	CLB.K
CELL.IMUX_IO_W_O[1]	IO_W[1].O
CELL.IMUX_IO_W_T[1]	IO_W[1].T
CELL.OUT_CLB_X	CLB.X
CELL.OUT_CLB_Y	CLB.Y
CELL.OUT_IO_W_I[1]	IO_W[1].I

Bitstream

xc2000 CLB_MW rect MAIN
Bit	Frame
Bit	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B7	-	-	-	-	INT: !bipass CELL.SINGLE_VW[0] = CELL.SINGLE_VW_S[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_VW[0]	INT: !bipass CELL.SINGLE_VW[0] = CELL.SINGLE_VW_S[1]	INT: !bipass CELL.SINGLE_VW[1] = CELL.SINGLE_VW_S[0]	INT: !bipass CELL.SINGLE_VW[1] = CELL.SINGLE_VW_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_VW_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_VW[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_VW[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_VW_S[1]	-	-	-	-	INT: !bipass CELL.SINGLE_VW[2] = CELL.SINGLE_VW_S[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_VW[3]	INT: !bipass CELL.SINGLE_VW[2] = CELL.SINGLE_VW_S[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_VW[2]
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_VW_S[3]	INT: !bipass CELL.SINGLE_VW[3] = CELL.SINGLE_VW_S[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_VW_S[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_VW[3]
B5	-	-	-	-	INT: !bipass CELL.SINGLE_VW[0] = CELL.LONG_H	INT: !bipass CELL.LONG_H = CELL.LONG_IO_W	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_VW_S[0]	INT: !pass CELL.LONG_H ← CELL.OUT_IO_W_I_S1	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_W_I_S1	INT: !bipass CELL.SINGLE_H[0] = CELL.LONG_V[0]	INT: !bipass CELL.LONG_H = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_VW_S[3]	-	-	INT: !bipass CELL.LONG_H = CELL.LONG_V[1]	INT: mux CELL.IMUX_CLB_A bit 0	INT: !bipass CELL.SINGLE_VW[3] = CELL.LONG_H	INT: mux CELL.IMUX_CLB_D bit 1	INT: !bipass CELL.SINGLE_VW[3] = CELL.SINGLE_VW_S[2]	-
B4	-	-	-	INT: mux CELL.IMUX_CLB_B bit 4	INT: mux CELL.IMUX_CLB_C bit 3	INT: mux CELL.IMUX_CLB_B bit 2	INT: mux CELL.IMUX_CLB_B bit 1	INT: mux CELL.IMUX_CLB_C bit 1	INT: mux CELL.IMUX_CLB_C bit 0	INT: mux CELL.IMUX_CLB_B bit 0	INT: mux CELL.IMUX_CLB_C bit 4	INT: !pass CELL.SINGLE_VW[3] ← CELL.OUT_IO_W_I[1]	INT: mux CELL.IMUX_CLB_C bit 2	INT: mux CELL.IMUX_CLB_B bit 5	INT: mux CELL.IMUX_CLB_B bit 3	-	-	-	-	-	-
B3	-	-	-	-	-	INT: mux CELL.IMUX_CLB_K bit 1	INT: mux CELL.IMUX_CLB_K bit 2	INT: mux CELL.IMUX_CLB_K bit 0	CLB: !invert K	INT: mux CELL.IMUX_CLB_K bit 3	INT: !pass CELL.SINGLE_VW[1] ← CELL.OUT_IO_W_I[1]	-	-	INT: !pass CELL.LONG_V[1] ← CELL.OUT_IO_W_I[1]	-	INT: mux CELL.IMUX_CLB_D bit 0	INT: mux CELL.IMUX_CLB_D bit 2	INT: mux CELL.IMUX_CLB_A bit 2	INT: mux CELL.IMUX_CLB_A bit 1	INT: mux CELL.IMUX_CLB_A bit 3	INT: mux CELL.IMUX_CLB_D bit 3
B2	INT: mux CELL.IMUX_IO_W_T[1] bit 2	INT: mux CELL.IMUX_IO_W_T[1] bit 1	INT: mux CELL.IMUX_IO_W_T[1] bit 0	CLB: MUX_RES bit 0	CLB: MUX_RES bit 1	CLB: MUX_SET bit 1	CLB: MUX_SET bit 0	-	-	-	-	-	CLB: FF_MODE bit 0	CLB: MUX_X bit 1	CLB: MUX_X bit 0	CLB: MUX_Y bit 0	CLB: MUX_Y bit 1	CLB: ! READBACK_Q bit 0	-	-	-
B1	INT: mux CELL.IMUX_IO_W_O[1] bit 1	INT: mux CELL.IMUX_IO_W_O[1] bit 2	INT: mux CELL.IMUX_IO_W_O[1] bit 3	CLB: MUX_F3 bit 0	CLB: MUX_F3 bit 1	-	-	-	-	CLB: MUX_F2 bit 0	CLB: MUX_F1 bit 0	-	-	-	CLB: MUX_G1 bit 0	CLB: MUX_G2 bit 0	-	-	-	CLB: MUX_G3 bit 1	CLB: MUX_G3 bit 0
B0	IO_W[1]: ! READBACK_Q bit 0	IO_W[1]: MUX_I bit 0	INT: mux CELL.IMUX_IO_W_O[1] bit 0	CLB: ! F bit 1	CLB: ! F bit 0	CLB: ! F bit 2	CLB: ! F bit 3	CLB: ! F bit 5	CLB: ! F bit 4	CLB: ! F bit 6	CLB: ! F bit 7	-	CLB: MODE bit 0	CLB: ! G bit 7	CLB: ! G bit 6	CLB: ! G bit 4	CLB: ! G bit 5	CLB: ! G bit 3	CLB: ! G bit 2	CLB: ! G bit 0	CLB: ! G bit 1

Tile CLB_ME

Cells: 2

Switchbox INT

xc2000 CLB_ME switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[1]	CELL.OUT_IO_E_I_S1	!MAIN[3][4]
CELL.SINGLE_H[3]	CELL.OUT_IO_E_I_S1	!MAIN[4][4]
CELL.SINGLE_V[0]	CELL.OUT_CLB_Y_E	!MAIN[26][3]
CELL.SINGLE_V[1]	CELL.OUT_CLB_X_E	!MAIN[19][3]
CELL.SINGLE_V[2]	CELL.OUT_CLB_Y_E	!MAIN[15][3]
CELL.SINGLE_V[3]	CELL.OUT_CLB_X_E	!MAIN[18][4]
CELL.SINGLE_V[4]	CELL.OUT_CLB_Y_E	!MAIN[25][3]
CELL.SINGLE_VE[0]	CELL.OUT_CLB_Y	!MAIN[4][3]
CELL.SINGLE_VE[0]	CELL.OUT_IO_E_I[1]	!MAIN[3][1]
CELL.SINGLE_VE[1]	CELL.OUT_CLB_X	!MAIN[3][3]
CELL.SINGLE_VE[2]	CELL.OUT_CLB_Y	!MAIN[6][3]
CELL.SINGLE_VE[2]	CELL.OUT_IO_E_I[1]	!MAIN[5][1]
CELL.SINGLE_VE[3]	CELL.OUT_CLB_X	!MAIN[8][3]
CELL.LONG_V[0]	CELL.OUT_CLB_X_E	!MAIN[17][3]
CELL.LONG_V[1]	CELL.OUT_CLB_Y_E	!MAIN[16][3]
CELL.LONG_VE[0]	CELL.OUT_CLB_Y	!MAIN[5][3]
CELL.LONG_VE[0]	CELL.OUT_IO_E_I[1]	!MAIN[4][1]
CELL.LONG_VE[1]	CELL.OUT_CLB_X	!MAIN[2][3]
CELL.LONG_IO_E	CELL.OUT_CLB_Y	!MAIN[7][3]
CELL.LONG_IO_E	CELL.OUT_IO_E_I[1]	!MAIN[7][2]

xc2000 CLB_ME switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.SINGLE_H_E[0]	!MAIN[23][7]
CELL.SINGLE_H[0]	CELL.SINGLE_H_E[1]	!MAIN[24][7]
CELL.SINGLE_H[0]	CELL.SINGLE_V[1]	!MAIN[19][6]
CELL.SINGLE_H[0]	CELL.SINGLE_V_S[0]	!MAIN[18][5]
CELL.SINGLE_H[0]	CELL.SINGLE_V_S[1]	!MAIN[20][7]
CELL.SINGLE_H[0]	CELL.SINGLE_VE[0]	!MAIN[2][5]
CELL.SINGLE_H[0]	CELL.SINGLE_VE_S[0]	!MAIN[1][6]
CELL.SINGLE_H[0]	CELL.SINGLE_VE_S[1]	!MAIN[1][7]
CELL.SINGLE_H[0]	CELL.LONG_V[1]	!MAIN[15][5]
CELL.SINGLE_H[0]	CELL.LONG_VE[1]	!MAIN[0][5]
CELL.SINGLE_H[1]	CELL.SINGLE_H_E[0]	!MAIN[25][6]
CELL.SINGLE_H[1]	CELL.SINGLE_H_E[1]	!MAIN[24][6]
CELL.SINGLE_H[1]	CELL.SINGLE_V[0]	!MAIN[18][7]
CELL.SINGLE_H[1]	CELL.SINGLE_V[1]	!MAIN[19][7]
CELL.SINGLE_H[1]	CELL.SINGLE_V[4]	!MAIN[20][5]
CELL.SINGLE_H[1]	CELL.SINGLE_V_S[1]	!MAIN[20][6]
CELL.SINGLE_H[1]	CELL.SINGLE_V_S[4]	!MAIN[23][5]
CELL.SINGLE_H[1]	CELL.SINGLE_VE[0]	!MAIN[3][5]
CELL.SINGLE_H[1]	CELL.SINGLE_VE[1]	!MAIN[0][7]
CELL.SINGLE_H[1]	CELL.SINGLE_VE_S[0]	!MAIN[0][6]
CELL.SINGLE_H[1]	CELL.LONG_V[0]	!MAIN[19][5]
CELL.SINGLE_H[1]	CELL.LONG_VE[0]	!MAIN[6][5]
CELL.SINGLE_H[2]	CELL.SINGLE_H_E[2]	!MAIN[12][7]
CELL.SINGLE_H[2]	CELL.SINGLE_H_E[3]	!MAIN[10][6]
CELL.SINGLE_H[2]	CELL.SINGLE_V[3]	!MAIN[10][5]
CELL.SINGLE_H[2]	CELL.SINGLE_V[4]	!MAIN[21][5]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[2]	!MAIN[12][6]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[3]	!MAIN[10][7]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[4]	!MAIN[22][5]
CELL.SINGLE_H[2]	CELL.SINGLE_VE[2]	!MAIN[6][6]
CELL.SINGLE_H[2]	CELL.SINGLE_VE_S[2]	!MAIN[6][7]
CELL.SINGLE_H[2]	CELL.SINGLE_VE_S[3]	!MAIN[8][7]
CELL.SINGLE_H[2]	CELL.LONG_V[1]	!MAIN[14][5]
CELL.SINGLE_H[2]	CELL.LONG_VE[1]	!MAIN[6][4]
CELL.SINGLE_H[3]	CELL.SINGLE_H_E[2]	!MAIN[11][7]
CELL.SINGLE_H[3]	CELL.SINGLE_H_E[3]	!MAIN[11][6]
CELL.SINGLE_H[3]	CELL.SINGLE_V[2]	!MAIN[13][6]
CELL.SINGLE_H[3]	CELL.SINGLE_V[3]	!MAIN[9][6]
CELL.SINGLE_H[3]	CELL.SINGLE_V_S[3]	!MAIN[9][7]
CELL.SINGLE_H[3]	CELL.SINGLE_VE[2]	!MAIN[4][6]
CELL.SINGLE_H[3]	CELL.SINGLE_VE[3]	!MAIN[7][6]
CELL.SINGLE_H[3]	CELL.SINGLE_VE_S[2]	!MAIN[4][7]
CELL.SINGLE_H[3]	CELL.LONG_V[0]	!MAIN[16][5]
CELL.SINGLE_H[3]	CELL.LONG_VE[0]	!MAIN[5][4]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V[0]	!MAIN[26][5]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V_S[0]	!MAIN[25][7]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V_S[1]	!MAIN[23][6]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V[0]	!MAIN[26][6]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V[1]	!MAIN[22][6]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V_S[0]	!MAIN[26][7]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V[2]	!MAIN[16][6]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V_S[2]	!MAIN[15][7]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V_S[3]	!MAIN[17][5]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V[2]	!MAIN[16][7]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V[3]	!MAIN[17][7]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V_S[2]	!MAIN[15][6]
CELL.SINGLE_V[0]	CELL.SINGLE_V_S[0]	!MAIN[18][6]
CELL.SINGLE_V[0]	CELL.SINGLE_V_S[1]	!MAIN[21][7]
CELL.SINGLE_V[0]	CELL.LONG_H	!MAIN[25][5]
CELL.SINGLE_V[1]	CELL.SINGLE_V_S[0]	!MAIN[22][7]
CELL.SINGLE_V[1]	CELL.SINGLE_V_S[1]	!MAIN[21][6]
CELL.SINGLE_V[2]	CELL.SINGLE_V_S[2]	!MAIN[14][6]
CELL.SINGLE_V[2]	CELL.SINGLE_V_S[3]	!MAIN[13][7]
CELL.SINGLE_V[3]	CELL.SINGLE_V_S[2]	!MAIN[14][7]
CELL.SINGLE_V[3]	CELL.SINGLE_V_S[3]	!MAIN[17][6]
CELL.SINGLE_V[3]	CELL.LONG_H	!MAIN[12][5]
CELL.SINGLE_V[4]	CELL.SINGLE_V_S[4]	!MAIN[24][5]
CELL.SINGLE_VE[0]	CELL.SINGLE_VE_S[0]	!MAIN[3][6]
CELL.SINGLE_VE[0]	CELL.SINGLE_VE_S[1]	!MAIN[3][7]
CELL.SINGLE_VE[0]	CELL.LONG_H	!MAIN[4][5]
CELL.SINGLE_VE[1]	CELL.SINGLE_VE_S[0]	!MAIN[2][7]
CELL.SINGLE_VE[1]	CELL.SINGLE_VE_S[1]	!MAIN[2][6]
CELL.SINGLE_VE[2]	CELL.SINGLE_VE_S[2]	!MAIN[5][7]
CELL.SINGLE_VE[2]	CELL.SINGLE_VE_S[3]	!MAIN[5][6]
CELL.SINGLE_VE[3]	CELL.SINGLE_VE_S[2]	!MAIN[7][7]
CELL.SINGLE_VE[3]	CELL.SINGLE_VE_S[3]	!MAIN[8][6]
CELL.SINGLE_VE[3]	CELL.LONG_H	!MAIN[8][5]
CELL.LONG_H	CELL.LONG_VE[0]	!MAIN[5][5]
CELL.LONG_H	CELL.LONG_VE[1]	!MAIN[1][5]
CELL.LONG_H	CELL.LONG_IO_E	!MAIN[7][5]

xc2000 CLB_ME switchbox INT muxes IMUX_CLB_A
Bits				Destination
MAIN[10][3]	MAIN[12][3]	MAIN[11][3]	MAIN[13][5]	CELL.IMUX_CLB_A
				Source
0	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	CELL.SINGLE_H[0]
0	1	0	0	CELL.SINGLE_H[2]
0	1	1	0	CELL.OUT_CLB_X_S
1	1	0	1	CELL.LONG_H
1	1	1	1	CELL.SINGLE_H[1]

xc2000 CLB_ME switchbox INT muxes IMUX_CLB_B
Bits						Destination
MAIN[16][4]	MAIN[26][4]	MAIN[15][4]	MAIN[24][4]	MAIN[23][4]	MAIN[20][4]	CELL.IMUX_CLB_B
						Source
0	0	0	1	1	1	CELL.OUT_CLB_Y_E
0	0	1	1	1	1	CELL.SINGLE_V[0]
0	1	0	0	1	1	CELL.SINGLE_V[1]
0	1	0	1	0	1	CELL.SINGLE_V[4]
0	1	0	1	1	0	CELL.LONG_V[0]
0	1	1	0	1	1	CELL.GCLK
0	1	1	1	0	1	CELL.SINGLE_V[3]
0	1	1	1	1	0	CELL.LONG_V[1]
1	1	0	1	1	1	CELL.OUT_CLB_X_S
1	1	1	1	1	1	CELL.SINGLE_V[2]

xc2000 CLB_ME switchbox INT muxes IMUX_CLB_C
Bits					Destination
MAIN[19][4]	MAIN[25][4]	MAIN[17][4]	MAIN[22][4]	MAIN[21][4]	CELL.IMUX_CLB_C
					Source
0	0	0	1	1	CELL.SINGLE_V[0]
0	0	1	1	1	CELL.SINGLE_V[1]
0	1	0	0	1	CELL.SINGLE_V[3]
0	1	0	1	0	CELL.LONG_V[1]
0	1	1	0	1	CELL.SINGLE_V[4]
0	1	1	1	0	CELL.LONG_V[0]
1	1	0	1	1	CELL.SINGLE_V[2]
1	1	1	1	1	CELL.OUT_CLB_X_N

xc2000 CLB_ME switchbox INT muxes IMUX_CLB_D
Bits				Destination
MAIN[9][3]	MAIN[13][3]	MAIN[11][5]	MAIN[14][3]	CELL.IMUX_CLB_D
				Source
0	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	CELL.SINGLE_H[0]
0	1	0	0	CELL.SINGLE_H[2]
0	1	1	0	CELL.OUT_CLB_X
1	1	0	1	CELL.LONG_H
1	1	1	1	CELL.SINGLE_H[1]

xc2000 CLB_ME switchbox INT muxes IMUX_CLB_K
Bits				Destination
MAIN[20][3]	MAIN[23][3]	MAIN[24][3]	MAIN[22][3]	CELL.IMUX_CLB_K
				Source
0	0	1	1	CELL.LONG_V[1]
0	1	0	1	CELL.GCLK
0	1	1	0	CELL.SPECIAL_CLB_C
0	1	1	1	~CELL.SPECIAL_CLB_G
1	1	1	1	off

xc2000 CLB_ME switchbox INT muxes IMUX_IO_E_O[1]
Bits					Destination
MAIN[6][0]	MAIN[6][1]	MAIN[7][1]	MAIN[7][0]	MAIN[8][0]	CELL.IMUX_IO_E_O[1]
					Source
0	0	0	1	1	CELL.SINGLE_VE[3]
0	0	1	0	1	CELL.LONG_VE[1]
0	0	1	1	0	S.LONG_H
0	1	1	1	1	CELL.SINGLE_VE[1]
1	0	0	1	1	CELL.OUT_CLB_X
1	0	1	0	1	S.SINGLE_H[0]
1	0	1	1	0	S.SINGLE_H[2]
1	1	1	1	1	CELL.OUT_CLB_Y

xc2000 CLB_ME switchbox INT muxes IMUX_IO_E_T[1]
Bits			Destination
MAIN[5][0]	MAIN[5][2]	MAIN[4][0]	CELL.IMUX_IO_E_T[1]
			Source
0	0	1	CELL.SINGLE_VE[1]
0	1	0	CELL.TIE_0
0	1	1	CELL.SINGLE_VE[3]
1	0	1	CELL.LONG_IO_E
1	1	0	CELL.TIE_1
1	1	1	CELL.LONG_VE[1]

Bels CLB

xc2000 CLB_ME bel CLB pins
Pin	Direction	CLB
A	in	CELL.IMUX_CLB_A
B	in	CELL.IMUX_CLB_B
C	in	CELL.IMUX_CLB_C
D	in	CELL.IMUX_CLB_D_N
K	in	CELL.IMUX_CLB_K invert by !MAIN[21][3]
X	out	CELL.OUT_CLB_X
Y	out	CELL.OUT_CLB_Y

xc2000 CLB_ME bel CLB attribute bits
Attribute	CLB
F bit 0	!MAIN[25][0]
F bit 1	!MAIN[26][0]
F bit 2	!MAIN[24][0]
F bit 3	!MAIN[23][0]
F bit 4	!MAIN[21][0]
F bit 5	!MAIN[22][0]
F bit 6	!MAIN[20][0]
F bit 7	!MAIN[19][0]
G bit 0	!MAIN[10][0]
G bit 1	!MAIN[9][0]
G bit 2	!MAIN[11][0]
G bit 3	!MAIN[12][0]
G bit 4	!MAIN[14][0]
G bit 5	!MAIN[13][0]
G bit 6	!MAIN[15][0]
G bit 7	!MAIN[16][0]
MODE	[enum: CLB_MODE]
FF_MODE	[enum: FF_MODE]
MUX_F1	[enum: CLB_MUX_I1]
MUX_G1	[enum: CLB_MUX_I1]
MUX_F2	[enum: CLB_MUX_I2]
MUX_G2	[enum: CLB_MUX_I2]
MUX_F3	[enum: CLB_MUX_I3]
MUX_G3	[enum: CLB_MUX_I3]
MUX_X	[enum: CLB_MUX_XY]
MUX_Y	[enum: CLB_MUX_XY]
MUX_RES	[enum: CLB_MUX_RES]
MUX_SET	[enum: CLB_MUX_SET]
READBACK_Q bit 0	!MAIN[12][2]

xc2000 CLB_ME enum CLB_MODE
CLB.MODE	MAIN[17][0]
FGM	1
FG	0

xc2000 CLB_ME enum FF_MODE
CLB.FF_MODE	MAIN[17][2]
FF	1
LATCH	0

xc2000 CLB_ME enum CLB_MUX_I1
CLB.MUX_F1	MAIN[19][1]
CLB.MUX_G1	MAIN[15][1]
A	0
B	1

xc2000 CLB_ME enum CLB_MUX_I2
CLB.MUX_F2	MAIN[20][1]
CLB.MUX_G2	MAIN[14][1]
B	0
C	1

xc2000 CLB_ME enum CLB_MUX_I3
CLB.MUX_F3	MAIN[25][1]	MAIN[26][1]
CLB.MUX_G3	MAIN[10][1]	MAIN[9][1]
C	0	1
D	1	0
Q	1	1

xc2000 CLB_ME enum CLB_MUX_XY
CLB.MUX_X	MAIN[16][2]	MAIN[15][2]
CLB.MUX_Y	MAIN[13][2]	MAIN[14][2]
F	0	1
G	1	0
Q	1	1

xc2000 CLB_ME enum CLB_MUX_RES
CLB.MUX_RES	MAIN[25][2]	MAIN[26][2]
D	0	1
G	0	0
TIE_0	1	1

xc2000 CLB_ME enum CLB_MUX_SET
CLB.MUX_SET	MAIN[24][2]	MAIN[23][2]
A	1	1
F	1	0
TIE_0	0	1

Bels IO

xc2000 CLB_ME bel IO pins
Pin	Direction	IO_E[1]
O	in	CELL.IMUX_IO_E_O[1]
T	in	CELL.IMUX_IO_E_T[1]
K	in	CELL.IOCLK_E
I	out	CELL.OUT_IO_E_I[1]

xc2000 CLB_ME bel IO attribute bits
Attribute	IO_E[1]
MUX_I	[enum: IO_MUX_I]
READBACK_Q bit 0	!MAIN[8][2]

xc2000 CLB_ME enum IO_MUX_I
IO_E[1].MUX_I	MAIN[2][0]
PAD	0
Q	1

Bels MISC_E

xc2000 CLB_ME bel MISC_E pins
Pin	Direction	MISC_E

xc2000 CLB_ME bel MISC_E attribute bits
Attribute	MISC_E
TLC	!MAIN[0][1]

Bel wires

xc2000 CLB_ME bel wires
Wire	Pins
CELL.IOCLK_E	IO_E[1].K
CELL.IMUX_CLB_A	CLB.A
CELL.IMUX_CLB_B	CLB.B
CELL.IMUX_CLB_C	CLB.C
CELL.IMUX_CLB_D_N	CLB.D
CELL.IMUX_CLB_K	CLB.K
CELL.IMUX_IO_E_O[1]	IO_E[1].O
CELL.IMUX_IO_E_T[1]	IO_E[1].T
CELL.OUT_CLB_X	CLB.X
CELL.OUT_CLB_Y	CLB.Y
CELL.OUT_IO_E_I[1]	IO_E[1].I

Bitstream

xc2000 CLB_ME rect MAIN
Bit	Frame
Bit	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B7	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_VE_S[3]	INT: !bipass CELL.SINGLE_VE[3] = CELL.SINGLE_VE_S[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_VE_S[2]	INT: !bipass CELL.SINGLE_VE[2] = CELL.SINGLE_VE_S[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_VE_S[2]	INT: !bipass CELL.SINGLE_VE[0] = CELL.SINGLE_VE_S[1]	INT: !bipass CELL.SINGLE_VE[1] = CELL.SINGLE_VE_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_VE_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_VE[1]
B6	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_VE[3] = CELL.SINGLE_VE_S[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_VE[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_VE[2]	INT: !bipass CELL.SINGLE_VE[2] = CELL.SINGLE_VE_S[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_VE[2]	INT: !bipass CELL.SINGLE_VE[0] = CELL.SINGLE_VE_S[0]	INT: !bipass CELL.SINGLE_VE[1] = CELL.SINGLE_VE_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_VE_S[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_VE_S[0]
B5	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.LONG_H	INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[4]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[4]	INT: !bipass CELL.SINGLE_H[1] = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_H[2] = CELL.LONG_V[1]	INT: mux CELL.IMUX_CLB_A bit 0	INT: !bipass CELL.SINGLE_V[3] = CELL.LONG_H	INT: mux CELL.IMUX_CLB_D bit 1	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[3]	-	INT: !bipass CELL.SINGLE_VE[3] = CELL.LONG_H	INT: !bipass CELL.LONG_H = CELL.LONG_IO_E	INT: !bipass CELL.SINGLE_H[1] = CELL.LONG_VE[0]	INT: !bipass CELL.LONG_H = CELL.LONG_VE[0]	INT: !bipass CELL.SINGLE_VE[0] = CELL.LONG_H	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_VE[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_VE[0]	INT: !bipass CELL.LONG_H = CELL.LONG_VE[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.LONG_VE[1]
B4	INT: mux CELL.IMUX_CLB_B bit 4	INT: mux CELL.IMUX_CLB_C bit 3	INT: mux CELL.IMUX_CLB_B bit 2	INT: mux CELL.IMUX_CLB_B bit 1	INT: mux CELL.IMUX_CLB_C bit 1	INT: mux CELL.IMUX_CLB_C bit 0	INT: mux CELL.IMUX_CLB_B bit 0	INT: mux CELL.IMUX_CLB_C bit 4	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_X_E	INT: mux CELL.IMUX_CLB_C bit 2	INT: mux CELL.IMUX_CLB_B bit 5	INT: mux CELL.IMUX_CLB_B bit 3	-	-	-	-	-	-	-	-	INT: !bipass CELL.SINGLE_H[2] = CELL.LONG_VE[1]	INT: !bipass CELL.SINGLE_H[3] = CELL.LONG_VE[0]	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_E_I_S1	INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_E_I_S1	-	-	-
B3	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_Y_E	INT: mux CELL.IMUX_CLB_K bit 1	INT: mux CELL.IMUX_CLB_K bit 2	INT: mux CELL.IMUX_CLB_K bit 0	CLB: !invert K	INT: mux CELL.IMUX_CLB_K bit 3	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X_E	-	INT: !pass CELL.LONG_V[0] ← CELL.OUT_CLB_X_E	INT: !pass CELL.LONG_V[1] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E	INT: mux CELL.IMUX_CLB_D bit 0	INT: mux CELL.IMUX_CLB_D bit 2	INT: mux CELL.IMUX_CLB_A bit 2	INT: mux CELL.IMUX_CLB_A bit 1	INT: mux CELL.IMUX_CLB_A bit 3	INT: mux CELL.IMUX_CLB_D bit 3	INT: !pass CELL.SINGLE_VE[3] ← CELL.OUT_CLB_X	INT: !pass CELL.LONG_IO_E ← CELL.OUT_CLB_Y	INT: !pass CELL.SINGLE_VE[2] ← CELL.OUT_CLB_Y	INT: !pass CELL.LONG_VE[0] ← CELL.OUT_CLB_Y	INT: !pass CELL.SINGLE_VE[0] ← CELL.OUT_CLB_Y	INT: !pass CELL.SINGLE_VE[1] ← CELL.OUT_CLB_X	INT: !pass CELL.LONG_VE[1] ← CELL.OUT_CLB_X	-	-
B2	CLB: MUX_RES bit 0	CLB: MUX_RES bit 1	CLB: MUX_SET bit 1	CLB: MUX_SET bit 0	-	-	-	-	-	CLB: FF_MODE bit 0	CLB: MUX_X bit 1	CLB: MUX_X bit 0	CLB: MUX_Y bit 0	CLB: MUX_Y bit 1	CLB: ! READBACK_Q bit 0	-	-	-	IO_E[1]: ! READBACK_Q bit 0	INT: !pass CELL.LONG_IO_E ← CELL.OUT_IO_E_I[1]	-	INT: mux CELL.IMUX_IO_E_T[1] bit 1	-	-	-	-	-
B1	CLB: MUX_F3 bit 0	CLB: MUX_F3 bit 1	-	-	-	-	CLB: MUX_F2 bit 0	CLB: MUX_F1 bit 0	-	-	-	CLB: MUX_G1 bit 0	CLB: MUX_G2 bit 0	-	-	-	CLB: MUX_G3 bit 1	CLB: MUX_G3 bit 0	-	INT: mux CELL.IMUX_IO_E_O[1] bit 2	INT: mux CELL.IMUX_IO_E_O[1] bit 3	INT: !pass CELL.SINGLE_VE[2] ← CELL.OUT_IO_E_I[1]	INT: !pass CELL.LONG_VE[0] ← CELL.OUT_IO_E_I[1]	INT: !pass CELL.SINGLE_VE[0] ← CELL.OUT_IO_E_I[1]	-	-	MISC_E: ! TLC
B0	CLB: ! F bit 1	CLB: ! F bit 0	CLB: ! F bit 2	CLB: ! F bit 3	CLB: ! F bit 5	CLB: ! F bit 4	CLB: ! F bit 6	CLB: ! F bit 7	-	CLB: MODE bit 0	CLB: ! G bit 7	CLB: ! G bit 6	CLB: ! G bit 4	CLB: ! G bit 5	CLB: ! G bit 3	CLB: ! G bit 2	CLB: ! G bit 0	CLB: ! G bit 1	INT: mux CELL.IMUX_IO_E_O[1] bit 0	INT: mux CELL.IMUX_IO_E_O[1] bit 1	INT: mux CELL.IMUX_IO_E_O[1] bit 4	INT: mux CELL.IMUX_IO_E_T[1] bit 2	INT: mux CELL.IMUX_IO_E_T[1] bit 0	-	IO_E[1]: MUX_I bit 0	-	-

Tile CLB_S

Cells: 2

Switchbox INT

xc2000 CLB_S switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_HS[0]	CELL.OUT_IO_S_I[1]	!MAIN[3][1]
CELL.SINGLE_HS[1]	CELL.OUT_IO_S_I[0]	!MAIN[8][3]
CELL.SINGLE_HS[2]	CELL.OUT_IO_S_I[1]	!MAIN[7][1]
CELL.SINGLE_HS[3]	CELL.OUT_IO_S_I[0]	!MAIN[11][2]
CELL.SINGLE_V[0]	CELL.OUT_CLB_Y_E	!MAIN[17][7]
CELL.SINGLE_V[0]	CELL.OUT_IO_S_I_E1	!MAIN[14][3]
CELL.SINGLE_V[1]	CELL.OUT_CLB_X_E	!MAIN[10][7]
CELL.SINGLE_V[1]	CELL.OUT_IO_S_I[0]	!MAIN[11][3]
CELL.SINGLE_V[2]	CELL.OUT_CLB_Y_E	!MAIN[6][7]
CELL.SINGLE_V[2]	CELL.OUT_IO_S_I_E1	!MAIN[7][3]
CELL.SINGLE_V[3]	CELL.OUT_CLB_X_E	!MAIN[9][8]
CELL.SINGLE_V[3]	CELL.OUT_IO_S_I[0]	!MAIN[10][1]
CELL.SINGLE_V[4]	CELL.OUT_CLB_Y_E	!MAIN[16][7]
CELL.SINGLE_V[4]	CELL.OUT_IO_S_I[0]	!MAIN[10][2]
CELL.LONG_HS	CELL.OUT_IO_S_I[0]	!MAIN[9][3]
CELL.LONG_IO_S	CELL.OUT_IO_S_I[1]	!MAIN[2][1]
CELL.LONG_V[0]	CELL.OUT_CLB_X_E	!MAIN[8][7]
CELL.LONG_V[0]	CELL.OUT_IO_S_I_E1	!MAIN[8][2]
CELL.LONG_V[1]	CELL.ACLK	!MAIN[9][1]
CELL.LONG_V[1]	CELL.OUT_CLB_Y_E	!MAIN[7][7]
CELL.LONG_V[1]	CELL.OUT_IO_S_I[0]	!MAIN[11][1]

xc2000 CLB_S switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.SINGLE_H_E[0]	!MAIN[14][11]
CELL.SINGLE_H[0]	CELL.SINGLE_H_E[1]	!MAIN[15][11]
CELL.SINGLE_H[0]	CELL.SINGLE_V[1]	!MAIN[10][10]
CELL.SINGLE_H[0]	CELL.SINGLE_V_S[0]	!MAIN[9][9]
CELL.SINGLE_H[0]	CELL.SINGLE_V_S[1]	!MAIN[11][11]
CELL.SINGLE_H[0]	CELL.LONG_V[1]	!MAIN[6][9]
CELL.SINGLE_H[1]	CELL.SINGLE_H_E[0]	!MAIN[16][10]
CELL.SINGLE_H[1]	CELL.SINGLE_H_E[1]	!MAIN[15][10]
CELL.SINGLE_H[1]	CELL.SINGLE_V[0]	!MAIN[9][11]
CELL.SINGLE_H[1]	CELL.SINGLE_V[1]	!MAIN[10][11]
CELL.SINGLE_H[1]	CELL.SINGLE_V[4]	!MAIN[11][9]
CELL.SINGLE_H[1]	CELL.SINGLE_V_S[1]	!MAIN[11][10]
CELL.SINGLE_H[1]	CELL.SINGLE_V_S[4]	!MAIN[14][9]
CELL.SINGLE_H[1]	CELL.LONG_V[0]	!MAIN[10][9]
CELL.SINGLE_H[2]	CELL.SINGLE_H_E[2]	!MAIN[3][11]
CELL.SINGLE_H[2]	CELL.SINGLE_H_E[3]	!MAIN[1][10]
CELL.SINGLE_H[2]	CELL.SINGLE_V[3]	!MAIN[1][9]
CELL.SINGLE_H[2]	CELL.SINGLE_V[4]	!MAIN[12][9]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[2]	!MAIN[3][10]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[3]	!MAIN[1][11]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[4]	!MAIN[13][9]
CELL.SINGLE_H[2]	CELL.LONG_V[1]	!MAIN[5][9]
CELL.SINGLE_H[3]	CELL.SINGLE_H_E[2]	!MAIN[2][11]
CELL.SINGLE_H[3]	CELL.SINGLE_H_E[3]	!MAIN[2][10]
CELL.SINGLE_H[3]	CELL.SINGLE_V[2]	!MAIN[4][10]
CELL.SINGLE_H[3]	CELL.SINGLE_V[3]	!MAIN[0][10]
CELL.SINGLE_H[3]	CELL.SINGLE_V_S[3]	!MAIN[0][11]
CELL.SINGLE_H[3]	CELL.LONG_V[0]	!MAIN[7][9]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V[0]	!MAIN[17][9]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V_S[0]	!MAIN[16][11]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V_S[1]	!MAIN[14][10]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V[0]	!MAIN[17][10]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V[1]	!MAIN[13][10]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V_S[0]	!MAIN[17][11]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V[2]	!MAIN[7][10]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V_S[2]	!MAIN[6][11]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V_S[3]	!MAIN[8][9]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V[2]	!MAIN[7][11]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V[3]	!MAIN[8][11]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V_S[2]	!MAIN[6][10]
CELL.SINGLE_HS[0]	CELL.SINGLE_HS_E[0]	!MAIN[3][3]
CELL.SINGLE_HS[0]	CELL.SINGLE_HS_E[1]	!MAIN[4][3]
CELL.SINGLE_HS[0]	CELL.SINGLE_V[2]	!MAIN[2][3]
CELL.SINGLE_HS[0]	CELL.SINGLE_V[3]	!MAIN[0][2]
CELL.SINGLE_HS[0]	CELL.LONG_V[0]	!MAIN[5][2]
CELL.SINGLE_HS[1]	CELL.SINGLE_HS_E[0]	!MAIN[1][2]
CELL.SINGLE_HS[1]	CELL.SINGLE_HS_E[1]	!MAIN[2][2]
CELL.SINGLE_HS[1]	CELL.SINGLE_V[3]	!MAIN[0][3]
CELL.SINGLE_HS[1]	CELL.SINGLE_V[4]	!MAIN[9][2]
CELL.SINGLE_HS[1]	CELL.LONG_V[1]	!MAIN[3][0]
CELL.SINGLE_HS[2]	CELL.SINGLE_HS_E[2]	!MAIN[16][3]
CELL.SINGLE_HS[2]	CELL.SINGLE_HS_E[3]	!MAIN[17][2]
CELL.SINGLE_HS[2]	CELL.SINGLE_V[0]	!MAIN[15][3]
CELL.SINGLE_HS[2]	CELL.SINGLE_V[1]	!MAIN[12][3]
CELL.SINGLE_HS[2]	CELL.SINGLE_V[4]	!MAIN[10][3]
CELL.SINGLE_HS[2]	CELL.LONG_V[0]	!MAIN[7][2]
CELL.SINGLE_HS[3]	CELL.SINGLE_HS_E[2]	!MAIN[13][2]
CELL.SINGLE_HS[3]	CELL.SINGLE_HS_E[3]	!MAIN[14][2]
CELL.SINGLE_HS[3]	CELL.SINGLE_V[1]	!MAIN[12][2]
CELL.SINGLE_HS[3]	CELL.LONG_V[1]	!MAIN[5][3]
CELL.SINGLE_HS_E[0]	CELL.SINGLE_V[2]	!MAIN[3][2]
CELL.SINGLE_HS_E[0]	CELL.SINGLE_V[3]	!MAIN[1][3]
CELL.SINGLE_HS_E[1]	CELL.SINGLE_V[2]	!MAIN[4][2]
CELL.SINGLE_HS_E[2]	CELL.SINGLE_V[0]	!MAIN[16][2]
CELL.SINGLE_HS_E[2]	CELL.SINGLE_V[1]	!MAIN[13][3]
CELL.SINGLE_HS_E[3]	CELL.SINGLE_V[0]	!MAIN[17][3]
CELL.SINGLE_V[0]	CELL.SINGLE_V_S[0]	!MAIN[9][10]
CELL.SINGLE_V[0]	CELL.SINGLE_V_S[1]	!MAIN[12][11]
CELL.SINGLE_V[0]	CELL.LONG_H	!MAIN[16][9]
CELL.SINGLE_V[0]	CELL.LONG_HS	!MAIN[15][2]
CELL.SINGLE_V[1]	CELL.SINGLE_V_S[0]	!MAIN[13][11]
CELL.SINGLE_V[1]	CELL.SINGLE_V_S[1]	!MAIN[12][10]
CELL.SINGLE_V[2]	CELL.SINGLE_V_S[2]	!MAIN[5][10]
CELL.SINGLE_V[2]	CELL.SINGLE_V_S[3]	!MAIN[4][11]
CELL.SINGLE_V[3]	CELL.SINGLE_V_S[2]	!MAIN[5][11]
CELL.SINGLE_V[3]	CELL.SINGLE_V_S[3]	!MAIN[8][10]
CELL.SINGLE_V[3]	CELL.LONG_H	!MAIN[3][9]
CELL.SINGLE_V[3]	CELL.LONG_HS	!MAIN[0][1]
CELL.SINGLE_V[4]	CELL.SINGLE_V_S[4]	!MAIN[15][9]
CELL.LONG_HS	CELL.LONG_V[0]	!MAIN[6][2]
CELL.LONG_HS	CELL.LONG_V[1]	!MAIN[6][3]
CELL.LONG_IO_S	CELL.LONG_V[0]	!MAIN[8][1]

xc2000 CLB_S switchbox INT muxes IMUX_CLB_A
Bits				Destination
MAIN[1][7]	MAIN[3][7]	MAIN[2][7]	MAIN[4][9]	CELL.IMUX_CLB_A
				Source
0	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	CELL.SINGLE_H[0]
0	1	0	0	CELL.SINGLE_H[2]
0	1	1	0	CELL.OUT_CLB_X_S
1	1	0	1	CELL.LONG_H
1	1	1	1	CELL.SINGLE_H[1]

xc2000 CLB_S switchbox INT muxes IMUX_CLB_B
Bits						Destination
MAIN[7][8]	MAIN[17][8]	MAIN[6][8]	MAIN[15][8]	MAIN[14][8]	MAIN[11][8]	CELL.IMUX_CLB_B
						Source
0	0	0	1	1	1	CELL.OUT_CLB_Y_E
0	0	1	1	1	1	CELL.SINGLE_V[0]
0	1	0	0	1	1	CELL.SINGLE_V[1]
0	1	0	1	0	1	CELL.SINGLE_V[4]
0	1	0	1	1	0	CELL.LONG_V[0]
0	1	1	0	1	1	CELL.GCLK
0	1	1	1	0	1	CELL.SINGLE_V[3]
0	1	1	1	1	0	CELL.LONG_V[1]
1	1	0	1	1	1	CELL.OUT_CLB_X_S
1	1	1	1	1	1	CELL.SINGLE_V[2]

xc2000 CLB_S switchbox INT muxes IMUX_CLB_C
Bits					Destination
MAIN[10][8]	MAIN[16][8]	MAIN[8][8]	MAIN[13][8]	MAIN[12][8]	CELL.IMUX_CLB_C
					Source
0	0	0	1	1	CELL.SINGLE_V[0]
0	0	1	1	1	CELL.SINGLE_V[1]
0	1	0	0	1	CELL.SINGLE_V[3]
0	1	0	1	0	CELL.LONG_V[1]
0	1	1	0	1	CELL.SINGLE_V[4]
0	1	1	1	0	CELL.LONG_V[0]
1	1	0	1	1	CELL.SINGLE_V[2]
1	1	1	1	1	CELL.OUT_IO_S_I[0]

xc2000 CLB_S switchbox INT muxes IMUX_CLB_D
Bits				Destination
MAIN[0][7]	MAIN[4][7]	MAIN[2][9]	MAIN[5][7]	CELL.IMUX_CLB_D
				Source
0	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	CELL.SINGLE_H[0]
0	1	0	0	CELL.SINGLE_H[2]
0	1	1	0	CELL.OUT_CLB_X
1	1	0	1	CELL.LONG_H
1	1	1	1	CELL.SINGLE_H[1]

xc2000 CLB_S switchbox INT muxes IMUX_CLB_D_N
Bits					Destination
MAIN[5][0]	MAIN[6][1]	MAIN[4][0]	MAIN[5][1]	MAIN[6][0]	CELL.IMUX_CLB_D_N
					Source
0	0	1	1	1	CELL.SINGLE_HS[0]
0	1	0	0	1	CELL.SINGLE_HS[1]
0	1	0	1	0	CELL.SINGLE_HS[2]
0	1	1	0	1	CELL.SINGLE_HS[3]
0	1	1	1	0	CELL.LONG_HS
1	1	0	1	1	CELL.LONG_IO_S
1	1	1	1	1	CELL.OUT_IO_S_I[0]

xc2000 CLB_S switchbox INT muxes IMUX_CLB_K
Bits				Destination
MAIN[11][7]	MAIN[14][7]	MAIN[15][7]	MAIN[13][7]	CELL.IMUX_CLB_K
				Source
0	0	1	1	CELL.LONG_V[1]
0	1	0	1	CELL.GCLK
0	1	1	0	CELL.SPECIAL_CLB_C
0	1	1	1	~CELL.SPECIAL_CLB_G
1	1	1	1	off

xc2000 CLB_S switchbox INT muxes IMUX_IO_S_O[0]
Bits				Destination
MAIN[16][0]	MAIN[15][1]	MAIN[16][1]	MAIN[17][0]	CELL.IMUX_IO_S_O[0]
				Source
0	0	0	1	CELL.LONG_V[0]
0	0	1	0	CELL.LONG_IO_S
0	1	1	1	CELL.SINGLE_HS[0]
1	0	0	1	CELL.SINGLE_HS[2]
1	0	1	0	CELL.SINGLE_V[2]
1	1	1	1	CELL.SINGLE_V[0]

xc2000 CLB_S switchbox INT muxes IMUX_IO_S_O[1]
Bits					Destination
MAIN_E[17][1]	MAIN[1][1]	MAIN[2][0]	MAIN[1][0]	MAIN[0][0]	CELL.IMUX_IO_S_O[1]
					Source
0	0	0	1	1	CELL.SINGLE_HS[1]
0	0	1	1	1	CELL.LONG_HS
0	1	0	0	1	CELL.OUT_CLB_X
0	1	0	1	0	E.SINGLE_V[3]
0	1	1	0	1	CELL.SINGLE_HS[3]
0	1	1	1	0	E.SINGLE_V[4]
1	1	0	1	1	E.SINGLE_V[1]
1	1	1	1	1	E.LONG_V[1]

xc2000 CLB_S switchbox INT muxes IMUX_IO_S_T[0]
Bits			Destination
MAIN[15][0]	MAIN[12][0]	MAIN[14][0]	CELL.IMUX_IO_S_T[0]
			Source
0	0	1	CELL.SINGLE_HS[3]
0	1	0	CELL.TIE_1
0	1	1	CELL.LONG_HS
1	0	1	CELL.LONG_IO_S
1	1	0	CELL.TIE_0
1	1	1	CELL.SINGLE_HS[1]

xc2000 CLB_S switchbox INT muxes IMUX_IO_S_T[1]
Bits			Destination
MAIN[10][0]	MAIN[11][0]	MAIN[9][0]	CELL.IMUX_IO_S_T[1]
			Source
0	0	1	CELL.SINGLE_HS[3]
0	1	0	CELL.TIE_0
0	1	1	CELL.LONG_HS
1	0	1	CELL.LONG_IO_S
1	1	0	CELL.TIE_1
1	1	1	CELL.SINGLE_HS[1]

Bels CLB

xc2000 CLB_S bel CLB pins
Pin	Direction	CLB
A	in	CELL.IMUX_CLB_A
B	in	CELL.IMUX_CLB_B
C	in	CELL.IMUX_CLB_C
D	in	CELL.IMUX_CLB_D_N
K	in	CELL.IMUX_CLB_K invert by !MAIN[12][7]
X	out	CELL.OUT_CLB_X
Y	out	CELL.OUT_CLB_Y

xc2000 CLB_S bel CLB attribute bits
Attribute	CLB
F bit 0	!MAIN[16][4]
F bit 1	!MAIN[17][4]
F bit 2	!MAIN[15][4]
F bit 3	!MAIN[14][4]
F bit 4	!MAIN[12][4]
F bit 5	!MAIN[13][4]
F bit 6	!MAIN[11][4]
F bit 7	!MAIN[10][4]
G bit 0	!MAIN[1][4]
G bit 1	!MAIN[0][4]
G bit 2	!MAIN[2][4]
G bit 3	!MAIN[3][4]
G bit 4	!MAIN[5][4]
G bit 5	!MAIN[4][4]
G bit 6	!MAIN[6][4]
G bit 7	!MAIN[7][4]
MODE	[enum: CLB_MODE]
FF_MODE	[enum: FF_MODE]
MUX_F1	[enum: CLB_MUX_I1]
MUX_G1	[enum: CLB_MUX_I1]
MUX_F2	[enum: CLB_MUX_I2]
MUX_G2	[enum: CLB_MUX_I2]
MUX_F3	[enum: CLB_MUX_I3]
MUX_G3	[enum: CLB_MUX_I3]
MUX_X	[enum: CLB_MUX_XY]
MUX_Y	[enum: CLB_MUX_XY]
MUX_RES	[enum: CLB_MUX_RES]
MUX_SET	[enum: CLB_MUX_SET]

xc2000 CLB_S enum CLB_MODE
CLB.MODE	MAIN[8][4]
FGM	1
FG	0

xc2000 CLB_S enum FF_MODE
CLB.FF_MODE	MAIN[8][6]
FF	1
LATCH	0

xc2000 CLB_S enum CLB_MUX_I1
CLB.MUX_F1	MAIN[10][5]
CLB.MUX_G1	MAIN[6][5]
A	0
B	1

xc2000 CLB_S enum CLB_MUX_I2
CLB.MUX_F2	MAIN[11][5]
CLB.MUX_G2	MAIN[5][5]
B	0
C	1

xc2000 CLB_S enum CLB_MUX_I3
CLB.MUX_F3	MAIN[16][5]	MAIN[17][5]
CLB.MUX_G3	MAIN[1][5]	MAIN[0][5]
C	0	1
D	1	0
Q	1	1

xc2000 CLB_S enum CLB_MUX_XY
CLB.MUX_X	MAIN[7][6]	MAIN[6][6]
CLB.MUX_Y	MAIN[4][6]	MAIN[5][6]
F	0	1
G	1	0
Q	1	1

xc2000 CLB_S enum CLB_MUX_RES
CLB.MUX_RES	MAIN[16][6]	MAIN[17][6]
D	0	1
G	0	0
TIE_0	1	1

xc2000 CLB_S enum CLB_MUX_SET
CLB.MUX_SET	MAIN[15][6]	MAIN[14][6]
A	1	1
F	1	0
TIE_0	0	1

Bels IO

xc2000 CLB_S bel IO pins
Pin	Direction	IO_S[0]	IO_S[1]
O	in	CELL.IMUX_IO_S_O[0]	CELL.IMUX_IO_S_O[1]
T	in	CELL.IMUX_IO_S_T[0]	CELL.IMUX_IO_S_T[1]
K	in	CELL.IOCLK_S	CELL.IOCLK_S
I	out	CELL.OUT_IO_S_I[0]	CELL.OUT_IO_S_I[1]

xc2000 CLB_S bel IO attribute bits
Attribute	IO_S[0]	IO_S[1]
MUX_I	[enum: IO_MUX_I]	[enum: IO_MUX_I]
READBACK_Q bit 0	!MAIN[4][1]	!MAIN[8][0]

xc2000 CLB_S enum IO_MUX_I
IO_S[0].MUX_I	MAIN[13][0]
IO_S[1].MUX_I	MAIN[7][0]
PAD	0
Q	1

Bel wires

xc2000 CLB_S bel wires
Wire	Pins
CELL.IOCLK_S	IO_S[0].K, IO_S[1].K
CELL.IMUX_CLB_A	CLB.A
CELL.IMUX_CLB_B	CLB.B
CELL.IMUX_CLB_C	CLB.C
CELL.IMUX_CLB_D_N	CLB.D
CELL.IMUX_CLB_K	CLB.K
CELL.IMUX_IO_S_O[0]	IO_S[0].O
CELL.IMUX_IO_S_O[1]	IO_S[1].O
CELL.IMUX_IO_S_T[0]	IO_S[0].T
CELL.IMUX_IO_S_T[1]	IO_S[1].T
CELL.OUT_CLB_X	CLB.X
CELL.OUT_CLB_Y	CLB.Y
CELL.OUT_IO_S_I[0]	IO_S[0].I
CELL.OUT_IO_S_I[1]	IO_S[1].I

Bitstream

xc2000 CLB_S rect MAIN
Bit	Frame
Bit	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B11	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3]
B10	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3]
B9	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.LONG_H	INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[4]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[4]	INT: !bipass CELL.SINGLE_H[1] = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_H[2] = CELL.LONG_V[1]	INT: mux CELL.IMUX_CLB_A bit 0	INT: !bipass CELL.SINGLE_V[3] = CELL.LONG_H	INT: mux CELL.IMUX_CLB_D bit 1	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[3]	-
B8	INT: mux CELL.IMUX_CLB_B bit 4	INT: mux CELL.IMUX_CLB_C bit 3	INT: mux CELL.IMUX_CLB_B bit 2	INT: mux CELL.IMUX_CLB_B bit 1	INT: mux CELL.IMUX_CLB_C bit 1	INT: mux CELL.IMUX_CLB_C bit 0	INT: mux CELL.IMUX_CLB_B bit 0	INT: mux CELL.IMUX_CLB_C bit 4	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_X_E	INT: mux CELL.IMUX_CLB_C bit 2	INT: mux CELL.IMUX_CLB_B bit 5	INT: mux CELL.IMUX_CLB_B bit 3	-	-	-	-	-	-
B7	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_Y_E	INT: mux CELL.IMUX_CLB_K bit 1	INT: mux CELL.IMUX_CLB_K bit 2	INT: mux CELL.IMUX_CLB_K bit 0	CLB: !invert K	INT: mux CELL.IMUX_CLB_K bit 3	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X_E	-	INT: !pass CELL.LONG_V[0] ← CELL.OUT_CLB_X_E	INT: !pass CELL.LONG_V[1] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E	INT: mux CELL.IMUX_CLB_D bit 0	INT: mux CELL.IMUX_CLB_D bit 2	INT: mux CELL.IMUX_CLB_A bit 2	INT: mux CELL.IMUX_CLB_A bit 1	INT: mux CELL.IMUX_CLB_A bit 3	INT: mux CELL.IMUX_CLB_D bit 3
B6	CLB: MUX_RES bit 0	CLB: MUX_RES bit 1	CLB: MUX_SET bit 1	CLB: MUX_SET bit 0	-	-	-	-	-	CLB: FF_MODE bit 0	CLB: MUX_X bit 1	CLB: MUX_X bit 0	CLB: MUX_Y bit 0	CLB: MUX_Y bit 1	-	-	-	-
B5	CLB: MUX_F3 bit 0	CLB: MUX_F3 bit 1	-	-	-	-	CLB: MUX_F2 bit 0	CLB: MUX_F1 bit 0	-	-	-	CLB: MUX_G1 bit 0	CLB: MUX_G2 bit 0	-	-	-	CLB: MUX_G3 bit 1	CLB: MUX_G3 bit 0
B4	CLB: ! F bit 1	CLB: ! F bit 0	CLB: ! F bit 2	CLB: ! F bit 3	CLB: ! F bit 5	CLB: ! F bit 4	CLB: ! F bit 6	CLB: ! F bit 7	-	CLB: MODE bit 0	CLB: ! G bit 7	CLB: ! G bit 6	CLB: ! G bit 4	CLB: ! G bit 5	CLB: ! G bit 3	CLB: ! G bit 2	CLB: ! G bit 0	CLB: ! G bit 1
B3	INT: !bipass CELL.SINGLE_HS_E[3] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_HS[2] = CELL.SINGLE_HS_E[2]	INT: !bipass CELL.SINGLE_HS[2] = CELL.SINGLE_V[0]	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_S_I_E1	INT: !bipass CELL.SINGLE_HS_E[2] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_HS[2] = CELL.SINGLE_V[1]	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_S_I[0]	INT: !bipass CELL.SINGLE_HS[2] = CELL.SINGLE_V[4]	INT: !pass CELL.LONG_HS ← CELL.OUT_IO_S_I[0]	INT: !pass CELL.SINGLE_HS[1] ← CELL.OUT_IO_S_I[0]	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_S_I_E1	INT: !bipass CELL.LONG_HS = CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_HS[3] = CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_HS[0] = CELL.SINGLE_HS_E[1]	INT: !bipass CELL.SINGLE_HS[0] = CELL.SINGLE_HS_E[0]	INT: !bipass CELL.SINGLE_HS[0] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_HS_E[0] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_HS[1] = CELL.SINGLE_V[3]
B2	INT: !bipass CELL.SINGLE_HS[2] = CELL.SINGLE_HS_E[3]	INT: !bipass CELL.SINGLE_HS_E[2] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.LONG_HS	INT: !bipass CELL.SINGLE_HS[3] = CELL.SINGLE_HS_E[3]	INT: !bipass CELL.SINGLE_HS[3] = CELL.SINGLE_HS_E[2]	INT: !bipass CELL.SINGLE_HS[3] = CELL.SINGLE_V[1]	INT: !pass CELL.SINGLE_HS[3] ← CELL.OUT_IO_S_I[0]	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_S_I[0]	INT: !bipass CELL.SINGLE_HS[1] = CELL.SINGLE_V[4]	INT: !pass CELL.LONG_V[0] ← CELL.OUT_IO_S_I_E1	INT: !bipass CELL.SINGLE_HS[2] = CELL.LONG_V[0]	INT: !bipass CELL.LONG_HS = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_HS[0] = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_HS_E[1] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_HS_E[0] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_HS[1] = CELL.SINGLE_HS_E[1]	INT: !bipass CELL.SINGLE_HS[1] = CELL.SINGLE_HS_E[0]	INT: !bipass CELL.SINGLE_HS[0] = CELL.SINGLE_V[3]
B1	-	INT: mux CELL.IMUX_IO_S_O[0] bit 1	INT: mux CELL.IMUX_IO_S_O[0] bit 2	-	-	-	INT: !pass CELL.LONG_V[1] ← CELL.OUT_IO_S_I[0]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_S_I[0]	INT: !pass CELL.LONG_V[1] ← CELL.ACLK	INT: !bipass CELL.LONG_IO_S = CELL.LONG_V[0]	INT: !pass CELL.SINGLE_HS[2] ← CELL.OUT_IO_S_I[1]	INT: mux CELL.IMUX_CLB_D_N bit 3	INT: mux CELL.IMUX_CLB_D_N bit 1	IO_S[0]: ! READBACK_Q bit 0	INT: !pass CELL.SINGLE_HS[0] ← CELL.OUT_IO_S_I[1]	INT: !pass CELL.LONG_IO_S ← CELL.OUT_IO_S_I[1]	INT: mux CELL.IMUX_IO_S_O[1] bit 3	INT: !bipass CELL.SINGLE_V[3] = CELL.LONG_HS
B0	INT: mux CELL.IMUX_IO_S_O[0] bit 0	INT: mux CELL.IMUX_IO_S_O[0] bit 3	INT: mux CELL.IMUX_IO_S_T[0] bit 2	INT: mux CELL.IMUX_IO_S_T[0] bit 0	IO_S[0]: MUX_I bit 0	INT: mux CELL.IMUX_IO_S_T[0] bit 1	INT: mux CELL.IMUX_IO_S_T[1] bit 1	INT: mux CELL.IMUX_IO_S_T[1] bit 2	INT: mux CELL.IMUX_IO_S_T[1] bit 0	IO_S[1]: ! READBACK_Q bit 0	IO_S[1]: MUX_I bit 0	INT: mux CELL.IMUX_CLB_D_N bit 0	INT: mux CELL.IMUX_CLB_D_N bit 4	INT: mux CELL.IMUX_CLB_D_N bit 2	INT: !bipass CELL.SINGLE_HS[1] = CELL.LONG_V[1]	INT: mux CELL.IMUX_IO_S_O[1] bit 2	INT: mux CELL.IMUX_IO_S_O[1] bit 1	INT: mux CELL.IMUX_IO_S_O[1] bit 0

xc2000 CLB_S rect MAIN_E
Bit	Frame
Bit	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	INT: mux CELL.IMUX_IO_S_O[1] bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile CLB_SE1

Cells: 2

Switchbox INT

xc2000 CLB_SE1 switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_HS[0]	CELL.OUT_IO_S_I[1]	!MAIN[3][1]
CELL.SINGLE_HS[1]	CELL.OUT_IO_S_I[0]	!MAIN[8][3]
CELL.SINGLE_HS[2]	CELL.OUT_IO_S_I[1]	!MAIN[7][1]
CELL.SINGLE_HS[3]	CELL.OUT_IO_S_I[0]	!MAIN[11][2]
CELL.SINGLE_V[0]	CELL.OUT_CLB_Y_E	!MAIN[17][7]
CELL.SINGLE_V[0]	CELL.OUT_IO_S_I_E1	!MAIN[14][3]
CELL.SINGLE_V[1]	CELL.OUT_CLB_X_E	!MAIN[10][7]
CELL.SINGLE_V[1]	CELL.OUT_IO_S_I[0]	!MAIN[11][3]
CELL.SINGLE_V[2]	CELL.OUT_CLB_Y_E	!MAIN[6][7]
CELL.SINGLE_V[2]	CELL.OUT_IO_S_I_E1	!MAIN[7][3]
CELL.SINGLE_V[3]	CELL.OUT_CLB_X_E	!MAIN[9][8]
CELL.SINGLE_V[3]	CELL.OUT_IO_S_I[0]	!MAIN[10][1]
CELL.SINGLE_V[4]	CELL.OUT_CLB_Y_E	!MAIN[16][7]
CELL.SINGLE_V[4]	CELL.OUT_IO_S_I[0]	!MAIN[10][2]
CELL.LONG_HS	CELL.OUT_IO_S_I[0]	!MAIN[9][3]
CELL.LONG_IO_S	CELL.OUT_IO_S_I[1]	!MAIN[2][1]
CELL.LONG_V[0]	CELL.OUT_CLB_X_E	!MAIN[8][7]
CELL.LONG_V[0]	CELL.OUT_IO_S_I_E1	!MAIN[8][2]
CELL.LONG_V[1]	CELL.ACLK	!MAIN[9][1]
CELL.LONG_V[1]	CELL.OUT_CLB_Y_E	!MAIN[7][7]
CELL.LONG_V[1]	CELL.OUT_IO_S_I[0]	!MAIN[11][1]

xc2000 CLB_SE1 switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.SINGLE_H_E[0]	!MAIN[14][11]
CELL.SINGLE_H[0]	CELL.SINGLE_H_E[1]	!MAIN[15][11]
CELL.SINGLE_H[0]	CELL.SINGLE_V[1]	!MAIN[10][10]
CELL.SINGLE_H[0]	CELL.SINGLE_V_S[0]	!MAIN[9][9]
CELL.SINGLE_H[0]	CELL.SINGLE_V_S[1]	!MAIN[11][11]
CELL.SINGLE_H[0]	CELL.LONG_V[1]	!MAIN[6][9]
CELL.SINGLE_H[1]	CELL.SINGLE_H_E[0]	!MAIN[16][10]
CELL.SINGLE_H[1]	CELL.SINGLE_H_E[1]	!MAIN[15][10]
CELL.SINGLE_H[1]	CELL.SINGLE_V[0]	!MAIN[9][11]
CELL.SINGLE_H[1]	CELL.SINGLE_V[1]	!MAIN[10][11]
CELL.SINGLE_H[1]	CELL.SINGLE_V[4]	!MAIN[11][9]
CELL.SINGLE_H[1]	CELL.SINGLE_V_S[1]	!MAIN[11][10]
CELL.SINGLE_H[1]	CELL.SINGLE_V_S[4]	!MAIN[14][9]
CELL.SINGLE_H[1]	CELL.LONG_V[0]	!MAIN[10][9]
CELL.SINGLE_H[2]	CELL.SINGLE_H_E[2]	!MAIN[3][11]
CELL.SINGLE_H[2]	CELL.SINGLE_H_E[3]	!MAIN[1][10]
CELL.SINGLE_H[2]	CELL.SINGLE_V[3]	!MAIN[1][9]
CELL.SINGLE_H[2]	CELL.SINGLE_V[4]	!MAIN[12][9]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[2]	!MAIN[3][10]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[3]	!MAIN[1][11]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[4]	!MAIN[13][9]
CELL.SINGLE_H[2]	CELL.LONG_V[1]	!MAIN[5][9]
CELL.SINGLE_H[3]	CELL.SINGLE_H_E[2]	!MAIN[2][11]
CELL.SINGLE_H[3]	CELL.SINGLE_H_E[3]	!MAIN[2][10]
CELL.SINGLE_H[3]	CELL.SINGLE_V[2]	!MAIN[4][10]
CELL.SINGLE_H[3]	CELL.SINGLE_V[3]	!MAIN[0][10]
CELL.SINGLE_H[3]	CELL.SINGLE_V_S[3]	!MAIN[0][11]
CELL.SINGLE_H[3]	CELL.LONG_V[0]	!MAIN[7][9]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V[0]	!MAIN[17][9]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V_S[0]	!MAIN[16][11]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V_S[1]	!MAIN[14][10]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V[0]	!MAIN[17][10]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V[1]	!MAIN[13][10]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V_S[0]	!MAIN[17][11]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V[2]	!MAIN[7][10]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V_S[2]	!MAIN[6][11]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V_S[3]	!MAIN[8][9]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V[2]	!MAIN[7][11]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V[3]	!MAIN[8][11]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V_S[2]	!MAIN[6][10]
CELL.SINGLE_HS[0]	CELL.SINGLE_HS_E[0]	!MAIN[3][3]
CELL.SINGLE_HS[0]	CELL.SINGLE_HS_E[1]	!MAIN[4][3]
CELL.SINGLE_HS[0]	CELL.SINGLE_V[2]	!MAIN[2][3]
CELL.SINGLE_HS[0]	CELL.SINGLE_V[3]	!MAIN[0][2]
CELL.SINGLE_HS[0]	CELL.LONG_V[0]	!MAIN[5][2]
CELL.SINGLE_HS[1]	CELL.SINGLE_HS_E[0]	!MAIN[1][2]
CELL.SINGLE_HS[1]	CELL.SINGLE_HS_E[1]	!MAIN[2][2]
CELL.SINGLE_HS[1]	CELL.SINGLE_V[3]	!MAIN[0][3]
CELL.SINGLE_HS[1]	CELL.SINGLE_V[4]	!MAIN[9][2]
CELL.SINGLE_HS[1]	CELL.LONG_V[1]	!MAIN[3][0]
CELL.SINGLE_HS[2]	CELL.SINGLE_HS_E[2]	!MAIN[16][3]
CELL.SINGLE_HS[2]	CELL.SINGLE_HS_E[3]	!MAIN[17][2]
CELL.SINGLE_HS[2]	CELL.SINGLE_V[0]	!MAIN[15][3]
CELL.SINGLE_HS[2]	CELL.SINGLE_V[1]	!MAIN[12][3]
CELL.SINGLE_HS[2]	CELL.SINGLE_V[4]	!MAIN[10][3]
CELL.SINGLE_HS[2]	CELL.LONG_V[0]	!MAIN[7][2]
CELL.SINGLE_HS[3]	CELL.SINGLE_HS_E[2]	!MAIN[13][2]
CELL.SINGLE_HS[3]	CELL.SINGLE_HS_E[3]	!MAIN[14][2]
CELL.SINGLE_HS[3]	CELL.SINGLE_V[1]	!MAIN[12][2]
CELL.SINGLE_HS[3]	CELL.LONG_V[1]	!MAIN[5][3]
CELL.SINGLE_HS_E[0]	CELL.SINGLE_V[2]	!MAIN[3][2]
CELL.SINGLE_HS_E[0]	CELL.SINGLE_V[3]	!MAIN[1][3]
CELL.SINGLE_HS_E[1]	CELL.SINGLE_V[2]	!MAIN[4][2]
CELL.SINGLE_HS_E[2]	CELL.SINGLE_V[0]	!MAIN[16][2]
CELL.SINGLE_HS_E[2]	CELL.SINGLE_V[1]	!MAIN[13][3]
CELL.SINGLE_HS_E[3]	CELL.SINGLE_V[0]	!MAIN[17][3]
CELL.SINGLE_V[0]	CELL.SINGLE_V_S[0]	!MAIN[9][10]
CELL.SINGLE_V[0]	CELL.SINGLE_V_S[1]	!MAIN[12][11]
CELL.SINGLE_V[0]	CELL.LONG_H	!MAIN[16][9]
CELL.SINGLE_V[0]	CELL.LONG_HS	!MAIN[15][2]
CELL.SINGLE_V[1]	CELL.SINGLE_V_S[0]	!MAIN[13][11]
CELL.SINGLE_V[1]	CELL.SINGLE_V_S[1]	!MAIN[12][10]
CELL.SINGLE_V[2]	CELL.SINGLE_V_S[2]	!MAIN[5][10]
CELL.SINGLE_V[2]	CELL.SINGLE_V_S[3]	!MAIN[4][11]
CELL.SINGLE_V[3]	CELL.SINGLE_V_S[2]	!MAIN[5][11]
CELL.SINGLE_V[3]	CELL.SINGLE_V_S[3]	!MAIN[8][10]
CELL.SINGLE_V[3]	CELL.LONG_H	!MAIN[3][9]
CELL.SINGLE_V[3]	CELL.LONG_HS	!MAIN[0][1]
CELL.SINGLE_V[4]	CELL.SINGLE_V_S[4]	!MAIN[15][9]
CELL.LONG_HS	CELL.LONG_V[0]	!MAIN[6][2]
CELL.LONG_HS	CELL.LONG_V[1]	!MAIN[6][3]
CELL.LONG_IO_S	CELL.LONG_V[0]	!MAIN[8][1]

xc2000 CLB_SE1 switchbox INT muxes IMUX_CLB_A
Bits				Destination
MAIN[1][7]	MAIN[3][7]	MAIN[2][7]	MAIN[4][9]	CELL.IMUX_CLB_A
				Source
0	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	CELL.SINGLE_H[0]
0	1	0	0	CELL.SINGLE_H[2]
0	1	1	0	CELL.OUT_CLB_X_S
1	1	0	1	CELL.LONG_H
1	1	1	1	CELL.SINGLE_H[1]

xc2000 CLB_SE1 switchbox INT muxes IMUX_CLB_B
Bits						Destination
MAIN[7][8]	MAIN[17][8]	MAIN[6][8]	MAIN[15][8]	MAIN[14][8]	MAIN[11][8]	CELL.IMUX_CLB_B
						Source
0	0	0	1	1	1	CELL.OUT_CLB_Y_E
0	0	1	1	1	1	CELL.SINGLE_V[0]
0	1	0	0	1	1	CELL.SINGLE_V[1]
0	1	0	1	0	1	CELL.SINGLE_V[4]
0	1	0	1	1	0	CELL.LONG_V[0]
0	1	1	0	1	1	CELL.GCLK
0	1	1	1	0	1	CELL.SINGLE_V[3]
0	1	1	1	1	0	CELL.LONG_V[1]
1	1	0	1	1	1	CELL.OUT_CLB_X_S
1	1	1	1	1	1	CELL.SINGLE_V[2]

xc2000 CLB_SE1 switchbox INT muxes IMUX_CLB_C
Bits					Destination
MAIN[10][8]	MAIN[16][8]	MAIN[8][8]	MAIN[13][8]	MAIN[12][8]	CELL.IMUX_CLB_C
					Source
0	0	0	1	1	CELL.SINGLE_V[0]
0	0	1	1	1	CELL.SINGLE_V[1]
0	1	0	0	1	CELL.SINGLE_V[3]
0	1	0	1	0	CELL.LONG_V[1]
0	1	1	0	1	CELL.SINGLE_V[4]
0	1	1	1	0	CELL.LONG_V[0]
1	1	0	1	1	CELL.SINGLE_V[2]
1	1	1	1	1	CELL.OUT_IO_S_I[0]

xc2000 CLB_SE1 switchbox INT muxes IMUX_CLB_D
Bits				Destination
MAIN[0][7]	MAIN[4][7]	MAIN[2][9]	MAIN[5][7]	CELL.IMUX_CLB_D
				Source
0	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	CELL.SINGLE_H[0]
0	1	0	0	CELL.SINGLE_H[2]
0	1	1	0	CELL.OUT_CLB_X
1	1	0	1	CELL.LONG_H
1	1	1	1	CELL.SINGLE_H[1]

xc2000 CLB_SE1 switchbox INT muxes IMUX_CLB_D_N
Bits					Destination
MAIN[5][0]	MAIN[6][1]	MAIN[4][0]	MAIN[5][1]	MAIN[6][0]	CELL.IMUX_CLB_D_N
					Source
0	0	1	1	1	CELL.SINGLE_HS[0]
0	1	0	0	1	CELL.SINGLE_HS[1]
0	1	0	1	0	CELL.SINGLE_HS[2]
0	1	1	0	1	CELL.SINGLE_HS[3]
0	1	1	1	0	CELL.LONG_HS
1	1	0	1	1	CELL.LONG_IO_S
1	1	1	1	1	CELL.OUT_IO_S_I[0]

xc2000 CLB_SE1 switchbox INT muxes IMUX_CLB_K
Bits				Destination
MAIN[11][7]	MAIN[14][7]	MAIN[15][7]	MAIN[13][7]	CELL.IMUX_CLB_K
				Source
0	0	1	1	CELL.LONG_V[1]
0	1	0	1	CELL.GCLK
0	1	1	0	CELL.SPECIAL_CLB_C
0	1	1	1	~CELL.SPECIAL_CLB_G
1	1	1	1	off

xc2000 CLB_SE1 switchbox INT muxes IMUX_IO_S_O[0]
Bits				Destination
MAIN[16][0]	MAIN[15][1]	MAIN[16][1]	MAIN[17][0]	CELL.IMUX_IO_S_O[0]
				Source
0	0	0	1	CELL.LONG_V[0]
0	0	1	0	CELL.LONG_IO_S
0	1	1	1	CELL.SINGLE_HS[0]
1	0	0	1	CELL.SINGLE_HS[2]
1	0	1	0	CELL.SINGLE_V[2]
1	1	1	1	CELL.SINGLE_V[0]

xc2000 CLB_SE1 switchbox INT muxes IMUX_IO_S_O[1]
Bits					Destination
MAIN_E[26][1]	MAIN[1][1]	MAIN[2][0]	MAIN[1][0]	MAIN[0][0]	CELL.IMUX_IO_S_O[1]
					Source
0	0	0	1	1	CELL.SINGLE_HS[1]
0	0	1	1	1	CELL.LONG_HS
0	1	0	0	1	CELL.OUT_CLB_X
0	1	0	1	0	E.SINGLE_V[3]
0	1	1	0	1	CELL.SINGLE_HS[3]
0	1	1	1	0	E.SINGLE_V[4]
1	1	0	1	1	E.SINGLE_V[1]
1	1	1	1	1	E.LONG_V[1]

xc2000 CLB_SE1 switchbox INT muxes IMUX_IO_S_T[0]
Bits			Destination
MAIN[15][0]	MAIN[12][0]	MAIN[14][0]	CELL.IMUX_IO_S_T[0]
			Source
0	0	1	CELL.SINGLE_HS[3]
0	1	0	CELL.TIE_1
0	1	1	CELL.LONG_HS
1	0	1	CELL.LONG_IO_S
1	1	0	CELL.TIE_0
1	1	1	CELL.SINGLE_HS[1]

xc2000 CLB_SE1 switchbox INT muxes IMUX_IO_S_T[1]
Bits			Destination
MAIN[10][0]	MAIN[11][0]	MAIN[9][0]	CELL.IMUX_IO_S_T[1]
			Source
0	0	1	CELL.SINGLE_HS[3]
0	1	0	CELL.TIE_0
0	1	1	CELL.LONG_HS
1	0	1	CELL.LONG_IO_S
1	1	0	CELL.TIE_1
1	1	1	CELL.SINGLE_HS[1]

Bels CLB

xc2000 CLB_SE1 bel CLB pins
Pin	Direction	CLB
A	in	CELL.IMUX_CLB_A
B	in	CELL.IMUX_CLB_B
C	in	CELL.IMUX_CLB_C
D	in	CELL.IMUX_CLB_D_N
K	in	CELL.IMUX_CLB_K invert by !MAIN[12][7]
X	out	CELL.OUT_CLB_X
Y	out	CELL.OUT_CLB_Y

xc2000 CLB_SE1 bel CLB attribute bits
Attribute	CLB
F bit 0	!MAIN[16][4]
F bit 1	!MAIN[17][4]
F bit 2	!MAIN[15][4]
F bit 3	!MAIN[14][4]
F bit 4	!MAIN[12][4]
F bit 5	!MAIN[13][4]
F bit 6	!MAIN[11][4]
F bit 7	!MAIN[10][4]
G bit 0	!MAIN[1][4]
G bit 1	!MAIN[0][4]
G bit 2	!MAIN[2][4]
G bit 3	!MAIN[3][4]
G bit 4	!MAIN[5][4]
G bit 5	!MAIN[4][4]
G bit 6	!MAIN[6][4]
G bit 7	!MAIN[7][4]
MODE	[enum: CLB_MODE]
FF_MODE	[enum: FF_MODE]
MUX_F1	[enum: CLB_MUX_I1]
MUX_G1	[enum: CLB_MUX_I1]
MUX_F2	[enum: CLB_MUX_I2]
MUX_G2	[enum: CLB_MUX_I2]
MUX_F3	[enum: CLB_MUX_I3]
MUX_G3	[enum: CLB_MUX_I3]
MUX_X	[enum: CLB_MUX_XY]
MUX_Y	[enum: CLB_MUX_XY]
MUX_RES	[enum: CLB_MUX_RES]
MUX_SET	[enum: CLB_MUX_SET]
READBACK_Q bit 0	!MAIN[3][6]

xc2000 CLB_SE1 enum CLB_MODE
CLB.MODE	MAIN[8][4]
FGM	1
FG	0

xc2000 CLB_SE1 enum FF_MODE
CLB.FF_MODE	MAIN[8][6]
FF	1
LATCH	0

xc2000 CLB_SE1 enum CLB_MUX_I1
CLB.MUX_F1	MAIN[10][5]
CLB.MUX_G1	MAIN[6][5]
A	0
B	1

xc2000 CLB_SE1 enum CLB_MUX_I2
CLB.MUX_F2	MAIN[11][5]
CLB.MUX_G2	MAIN[5][5]
B	0
C	1

xc2000 CLB_SE1 enum CLB_MUX_I3
CLB.MUX_F3	MAIN[16][5]	MAIN[17][5]
CLB.MUX_G3	MAIN[1][5]	MAIN[0][5]
C	0	1
D	1	0
Q	1	1

xc2000 CLB_SE1 enum CLB_MUX_XY
CLB.MUX_X	MAIN[7][6]	MAIN[6][6]
CLB.MUX_Y	MAIN[4][6]	MAIN[5][6]
F	0	1
G	1	0
Q	1	1

xc2000 CLB_SE1 enum CLB_MUX_RES
CLB.MUX_RES	MAIN[16][6]	MAIN[17][6]
D	0	1
G	0	0
TIE_0	1	1

xc2000 CLB_SE1 enum CLB_MUX_SET
CLB.MUX_SET	MAIN[15][6]	MAIN[14][6]
A	1	1
F	1	0
TIE_0	0	1

Bels IO

xc2000 CLB_SE1 bel IO pins
Pin	Direction	IO_S[0]	IO_S[1]
O	in	CELL.IMUX_IO_S_O[0]	CELL.IMUX_IO_S_O[1]
T	in	CELL.IMUX_IO_S_T[0]	CELL.IMUX_IO_S_T[1]
K	in	CELL.IOCLK_S	CELL.IOCLK_S
I	out	CELL.OUT_IO_S_I[0]	CELL.OUT_IO_S_I[1]

xc2000 CLB_SE1 bel IO attribute bits
Attribute	IO_S[0]	IO_S[1]
MUX_I	[enum: IO_MUX_I]	[enum: IO_MUX_I]
READBACK_Q bit 0	!MAIN[4][1]	!MAIN[8][0]

xc2000 CLB_SE1 enum IO_MUX_I
IO_S[0].MUX_I	MAIN[13][0]
IO_S[1].MUX_I	MAIN[7][0]
PAD	0
Q	1

Bel wires

xc2000 CLB_SE1 bel wires
Wire	Pins
CELL.IOCLK_S	IO_S[0].K, IO_S[1].K
CELL.IMUX_CLB_A	CLB.A
CELL.IMUX_CLB_B	CLB.B
CELL.IMUX_CLB_C	CLB.C
CELL.IMUX_CLB_D_N	CLB.D
CELL.IMUX_CLB_K	CLB.K
CELL.IMUX_IO_S_O[0]	IO_S[0].O
CELL.IMUX_IO_S_O[1]	IO_S[1].O
CELL.IMUX_IO_S_T[0]	IO_S[0].T
CELL.IMUX_IO_S_T[1]	IO_S[1].T
CELL.OUT_CLB_X	CLB.X
CELL.OUT_CLB_Y	CLB.Y
CELL.OUT_IO_S_I[0]	IO_S[0].I
CELL.OUT_IO_S_I[1]	IO_S[1].I

Bitstream

xc2000 CLB_SE1 rect MAIN
Bit	Frame
Bit	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B11	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3]
B10	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3]
B9	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.LONG_H	INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[4]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[4]	INT: !bipass CELL.SINGLE_H[1] = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_H[2] = CELL.LONG_V[1]	INT: mux CELL.IMUX_CLB_A bit 0	INT: !bipass CELL.SINGLE_V[3] = CELL.LONG_H	INT: mux CELL.IMUX_CLB_D bit 1	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[3]	-
B8	INT: mux CELL.IMUX_CLB_B bit 4	INT: mux CELL.IMUX_CLB_C bit 3	INT: mux CELL.IMUX_CLB_B bit 2	INT: mux CELL.IMUX_CLB_B bit 1	INT: mux CELL.IMUX_CLB_C bit 1	INT: mux CELL.IMUX_CLB_C bit 0	INT: mux CELL.IMUX_CLB_B bit 0	INT: mux CELL.IMUX_CLB_C bit 4	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_X_E	INT: mux CELL.IMUX_CLB_C bit 2	INT: mux CELL.IMUX_CLB_B bit 5	INT: mux CELL.IMUX_CLB_B bit 3	-	-	-	-	-	-
B7	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_Y_E	INT: mux CELL.IMUX_CLB_K bit 1	INT: mux CELL.IMUX_CLB_K bit 2	INT: mux CELL.IMUX_CLB_K bit 0	CLB: !invert K	INT: mux CELL.IMUX_CLB_K bit 3	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X_E	-	INT: !pass CELL.LONG_V[0] ← CELL.OUT_CLB_X_E	INT: !pass CELL.LONG_V[1] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E	INT: mux CELL.IMUX_CLB_D bit 0	INT: mux CELL.IMUX_CLB_D bit 2	INT: mux CELL.IMUX_CLB_A bit 2	INT: mux CELL.IMUX_CLB_A bit 1	INT: mux CELL.IMUX_CLB_A bit 3	INT: mux CELL.IMUX_CLB_D bit 3
B6	CLB: MUX_RES bit 0	CLB: MUX_RES bit 1	CLB: MUX_SET bit 1	CLB: MUX_SET bit 0	-	-	-	-	-	CLB: FF_MODE bit 0	CLB: MUX_X bit 1	CLB: MUX_X bit 0	CLB: MUX_Y bit 0	CLB: MUX_Y bit 1	CLB: ! READBACK_Q bit 0	-	-	-
B5	CLB: MUX_F3 bit 0	CLB: MUX_F3 bit 1	-	-	-	-	CLB: MUX_F2 bit 0	CLB: MUX_F1 bit 0	-	-	-	CLB: MUX_G1 bit 0	CLB: MUX_G2 bit 0	-	-	-	CLB: MUX_G3 bit 1	CLB: MUX_G3 bit 0
B4	CLB: ! F bit 1	CLB: ! F bit 0	CLB: ! F bit 2	CLB: ! F bit 3	CLB: ! F bit 5	CLB: ! F bit 4	CLB: ! F bit 6	CLB: ! F bit 7	-	CLB: MODE bit 0	CLB: ! G bit 7	CLB: ! G bit 6	CLB: ! G bit 4	CLB: ! G bit 5	CLB: ! G bit 3	CLB: ! G bit 2	CLB: ! G bit 0	CLB: ! G bit 1
B3	INT: !bipass CELL.SINGLE_HS_E[3] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_HS[2] = CELL.SINGLE_HS_E[2]	INT: !bipass CELL.SINGLE_HS[2] = CELL.SINGLE_V[0]	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_S_I_E1	INT: !bipass CELL.SINGLE_HS_E[2] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_HS[2] = CELL.SINGLE_V[1]	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_S_I[0]	INT: !bipass CELL.SINGLE_HS[2] = CELL.SINGLE_V[4]	INT: !pass CELL.LONG_HS ← CELL.OUT_IO_S_I[0]	INT: !pass CELL.SINGLE_HS[1] ← CELL.OUT_IO_S_I[0]	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_S_I_E1	INT: !bipass CELL.LONG_HS = CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_HS[3] = CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_HS[0] = CELL.SINGLE_HS_E[1]	INT: !bipass CELL.SINGLE_HS[0] = CELL.SINGLE_HS_E[0]	INT: !bipass CELL.SINGLE_HS[0] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_HS_E[0] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_HS[1] = CELL.SINGLE_V[3]
B2	INT: !bipass CELL.SINGLE_HS[2] = CELL.SINGLE_HS_E[3]	INT: !bipass CELL.SINGLE_HS_E[2] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.LONG_HS	INT: !bipass CELL.SINGLE_HS[3] = CELL.SINGLE_HS_E[3]	INT: !bipass CELL.SINGLE_HS[3] = CELL.SINGLE_HS_E[2]	INT: !bipass CELL.SINGLE_HS[3] = CELL.SINGLE_V[1]	INT: !pass CELL.SINGLE_HS[3] ← CELL.OUT_IO_S_I[0]	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_S_I[0]	INT: !bipass CELL.SINGLE_HS[1] = CELL.SINGLE_V[4]	INT: !pass CELL.LONG_V[0] ← CELL.OUT_IO_S_I_E1	INT: !bipass CELL.SINGLE_HS[2] = CELL.LONG_V[0]	INT: !bipass CELL.LONG_HS = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_HS[0] = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_HS_E[1] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_HS_E[0] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_HS[1] = CELL.SINGLE_HS_E[1]	INT: !bipass CELL.SINGLE_HS[1] = CELL.SINGLE_HS_E[0]	INT: !bipass CELL.SINGLE_HS[0] = CELL.SINGLE_V[3]
B1	-	INT: mux CELL.IMUX_IO_S_O[0] bit 1	INT: mux CELL.IMUX_IO_S_O[0] bit 2	-	-	-	INT: !pass CELL.LONG_V[1] ← CELL.OUT_IO_S_I[0]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_S_I[0]	INT: !pass CELL.LONG_V[1] ← CELL.ACLK	INT: !bipass CELL.LONG_IO_S = CELL.LONG_V[0]	INT: !pass CELL.SINGLE_HS[2] ← CELL.OUT_IO_S_I[1]	INT: mux CELL.IMUX_CLB_D_N bit 3	INT: mux CELL.IMUX_CLB_D_N bit 1	IO_S[0]: ! READBACK_Q bit 0	INT: !pass CELL.SINGLE_HS[0] ← CELL.OUT_IO_S_I[1]	INT: !pass CELL.LONG_IO_S ← CELL.OUT_IO_S_I[1]	INT: mux CELL.IMUX_IO_S_O[1] bit 3	INT: !bipass CELL.SINGLE_V[3] = CELL.LONG_HS
B0	INT: mux CELL.IMUX_IO_S_O[0] bit 0	INT: mux CELL.IMUX_IO_S_O[0] bit 3	INT: mux CELL.IMUX_IO_S_T[0] bit 2	INT: mux CELL.IMUX_IO_S_T[0] bit 0	IO_S[0]: MUX_I bit 0	INT: mux CELL.IMUX_IO_S_T[0] bit 1	INT: mux CELL.IMUX_IO_S_T[1] bit 1	INT: mux CELL.IMUX_IO_S_T[1] bit 2	INT: mux CELL.IMUX_IO_S_T[1] bit 0	IO_S[1]: ! READBACK_Q bit 0	IO_S[1]: MUX_I bit 0	INT: mux CELL.IMUX_CLB_D_N bit 0	INT: mux CELL.IMUX_CLB_D_N bit 4	INT: mux CELL.IMUX_CLB_D_N bit 2	INT: !bipass CELL.SINGLE_HS[1] = CELL.LONG_V[1]	INT: mux CELL.IMUX_IO_S_O[1] bit 2	INT: mux CELL.IMUX_IO_S_O[1] bit 1	INT: mux CELL.IMUX_IO_S_O[1] bit 0

xc2000 CLB_SE1 rect MAIN_E
Bit	Frame
Bit	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	INT: mux CELL.IMUX_IO_S_O[1] bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile CLB_SW

Cells: 2

Switchbox INT

xc2000 CLB_SW switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[2]	CELL.OUT_IO_W_I_S1	!MAIN[12][9]
CELL.SINGLE_H[3]	CELL.OUT_IO_W_I[0]	!MAIN[7][9]
CELL.SINGLE_HS[0]	CELL.OUT_IO_S_I[1]	!MAIN[3][1]
CELL.SINGLE_HS[1]	CELL.OUT_IO_S_I[0]	!MAIN[1][3]
CELL.SINGLE_HS[2]	CELL.OUT_IO_S_I[1]	!MAIN[7][1]
CELL.SINGLE_HS[3]	CELL.OUT_IO_S_I[0]	!MAIN[2][3]
CELL.SINGLE_VW[0]	CELL.OUT_IO_W_I[0]	!MAIN[17][7]
CELL.SINGLE_VW[1]	CELL.OUT_IO_S_I[0]	!MAIN[9][3]
CELL.SINGLE_VW[2]	CELL.OUT_IO_W_I[0]	!MAIN[6][9]
CELL.SINGLE_VW[3]	CELL.OUT_IO_S_I[0]	!MAIN[10][1]
CELL.LONG_H	CELL.OUT_IO_W_I_S1	!MAIN[13][9]
CELL.LONG_HS	CELL.OUT_IO_S_I[0]	!MAIN[3][3]
CELL.LONG_IO_S	CELL.OUT_IO_S_I[1]	!MAIN[2][1]
CELL.LONG_V[0]	CELL.OUT_IO_W_I[0]	!MAIN[8][7]
CELL.LONG_V[1]	CELL.ACLK	!MAIN[9][1]
CELL.LONG_V[1]	CELL.OUT_IO_S_I[0]	!MAIN[11][1]
CELL.LONG_IO_W	CELL.OUT_IO_W_I[0]	!MAIN[16][7]
CELL.LONG_IO_W	CELL.OUT_IO_S_I[0]	!MAIN[10][3]

xc2000 CLB_SW switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.SINGLE_VW[1]	!MAIN[10][11]
CELL.SINGLE_H[0]	CELL.SINGLE_VW_S[0]	!MAIN[14][9]
CELL.SINGLE_H[0]	CELL.SINGLE_VW_S[1]	!MAIN[11][11]
CELL.SINGLE_H[0]	CELL.LONG_V[0]	!MAIN[11][9]
CELL.SINGLE_H[1]	CELL.SINGLE_VW[0]	!MAIN[15][11]
CELL.SINGLE_H[1]	CELL.SINGLE_VW[1]	!MAIN[9][11]
CELL.SINGLE_H[1]	CELL.SINGLE_VW_S[1]	!MAIN[8][11]
CELL.SINGLE_H[1]	CELL.LONG_V[1]	!MAIN[9][9]
CELL.SINGLE_H[2]	CELL.SINGLE_VW[3]	!MAIN[2][11]
CELL.SINGLE_H[2]	CELL.SINGLE_VW_S[2]	!MAIN[1][10]
CELL.SINGLE_H[2]	CELL.SINGLE_VW_S[3]	!MAIN[3][10]
CELL.SINGLE_H[3]	CELL.SINGLE_VW[2]	!MAIN[0][11]
CELL.SINGLE_H[3]	CELL.SINGLE_VW[3]	!MAIN[0][10]
CELL.SINGLE_H[3]	CELL.SINGLE_VW_S[3]	!MAIN[8][9]
CELL.SINGLE_HS[0]	CELL.SINGLE_VW[3]	!MAIN[0][3]
CELL.SINGLE_HS[1]	CELL.SINGLE_VW[2]	!MAIN[6][3]
CELL.SINGLE_HS[1]	CELL.LONG_V[1]	!MAIN[3][0]
CELL.SINGLE_HS[2]	CELL.SINGLE_VW[1]	!MAIN[8][3]
CELL.SINGLE_HS[3]	CELL.SINGLE_VW[0]	!MAIN[12][3]
CELL.SINGLE_HS[3]	CELL.LONG_IO_W	!MAIN[11][3]
CELL.SINGLE_VW[0]	CELL.SINGLE_VW_S[0]	!MAIN[16][11]
CELL.SINGLE_VW[0]	CELL.SINGLE_VW_S[1]	!MAIN[14][11]
CELL.SINGLE_VW[0]	CELL.LONG_H	!MAIN[16][9]
CELL.SINGLE_VW[0]	CELL.LONG_IO_S	!MAIN[13][3]
CELL.SINGLE_VW[1]	CELL.SINGLE_VW_S[0]	!MAIN[13][11]
CELL.SINGLE_VW[1]	CELL.SINGLE_VW_S[1]	!MAIN[12][11]
CELL.SINGLE_VW[2]	CELL.SINGLE_VW_S[2]	!MAIN[1][11]
CELL.SINGLE_VW[2]	CELL.SINGLE_VW_S[3]	!MAIN[3][11]
CELL.SINGLE_VW[3]	CELL.SINGLE_VW_S[2]	!MAIN[1][9]
CELL.SINGLE_VW[3]	CELL.SINGLE_VW_S[3]	!MAIN[2][10]
CELL.SINGLE_VW[3]	CELL.LONG_H	!MAIN[3][9]
CELL.SINGLE_VW[3]	CELL.LONG_HS	!MAIN[0][1]
CELL.LONG_H	CELL.LONG_V[0]	!MAIN[10][9]
CELL.LONG_H	CELL.LONG_V[1]	!MAIN[5][9]
CELL.LONG_H	CELL.LONG_IO_W	!MAIN[15][9]
CELL.LONG_HS	CELL.LONG_V[0]	!MAIN[7][3]
CELL.LONG_HS	CELL.LONG_V[1]	!MAIN[4][3]
CELL.LONG_IO_S	CELL.LONG_V[0]	!MAIN[8][1]
CELL.LONG_IO_S	CELL.LONG_IO_W	!MAIN[14][3]

xc2000 CLB_SW switchbox INT muxes IOCLK_W
Bits				Destination
MAIN[17][3]	MAIN[18][3]	MAIN[19][3]	MAIN[20][3]	CELL.IOCLK_W
				Source
0	0	1	0	CELL.GCLK
0	0	1	1	CELL.SINGLE_VW[0]
0	1	0	0	CELL.SINGLE_VW[1]
0	1	0	1	CELL.SINGLE_VW[2]
1	1	1	0	CELL.SINGLE_VW[3]
1	1	1	1	CELL.LONG_V[0]

xc2000 CLB_SW switchbox INT muxes IOCLK_S
Bits				Destination
MAIN[15][3]	MAIN[18][1]	MAIN[19][1]	MAIN[16][3]	CELL.IOCLK_S
				Source
0	0	0	1	CELL.SINGLE_HS[0]
0	0	1	1	CELL.SINGLE_HS[2]
0	1	0	0	CELL.LONG_HS
0	1	1	0	CELL.SINGLE_HS[1]
1	1	0	1	CELL.GCLK
1	1	1	1	CELL.SINGLE_HS[3]

xc2000 CLB_SW switchbox INT muxes IMUX_CLB_A
Bits				Destination
MAIN[1][7]	MAIN[3][7]	MAIN[2][7]	MAIN[4][9]	CELL.IMUX_CLB_A
				Source
0	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	CELL.SINGLE_H[0]
0	1	0	0	CELL.SINGLE_H[2]
0	1	1	0	CELL.OUT_CLB_X_S
1	1	0	1	CELL.LONG_H
1	1	1	1	CELL.SINGLE_H[1]

xc2000 CLB_SW switchbox INT muxes IMUX_CLB_B
Bits						Destination
MAIN[7][8]	MAIN[17][8]	MAIN[6][8]	MAIN[15][8]	MAIN[14][8]	MAIN[11][8]	CELL.IMUX_CLB_B
						Source
0	0	0	1	1	1	CELL.OUT_IO_W_I[0]
0	0	1	1	1	1	CELL.SINGLE_VW[0]
0	1	0	0	1	1	CELL.SINGLE_VW[1]
0	1	0	1	0	1	CELL.LONG_IO_W
0	1	0	1	1	0	CELL.LONG_V[0]
0	1	1	0	1	1	CELL.GCLK
0	1	1	1	0	1	CELL.SINGLE_VW[3]
0	1	1	1	1	0	CELL.LONG_V[1]
1	1	0	1	1	1	CELL.OUT_CLB_X_S
1	1	1	1	1	1	CELL.SINGLE_VW[2]

xc2000 CLB_SW switchbox INT muxes IMUX_CLB_C
Bits					Destination
MAIN[10][8]	MAIN[16][8]	MAIN[8][8]	MAIN[13][8]	MAIN[12][8]	CELL.IMUX_CLB_C
					Source
0	0	0	1	1	CELL.SINGLE_VW[0]
0	0	1	1	1	CELL.SINGLE_VW[1]
0	1	0	0	1	CELL.SINGLE_VW[3]
0	1	0	1	0	CELL.LONG_V[1]
0	1	1	0	1	CELL.LONG_IO_W
0	1	1	1	0	CELL.LONG_V[0]
1	1	0	1	1	CELL.SINGLE_VW[2]
1	1	1	1	1	CELL.OUT_IO_S_I[0]

xc2000 CLB_SW switchbox INT muxes IMUX_CLB_D
Bits				Destination
MAIN[0][7]	MAIN[4][7]	MAIN[2][9]	MAIN[5][7]	CELL.IMUX_CLB_D
				Source
0	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	CELL.SINGLE_H[0]
0	1	0	0	CELL.SINGLE_H[2]
0	1	1	0	CELL.OUT_CLB_X
1	1	0	1	CELL.LONG_H
1	1	1	1	CELL.SINGLE_H[1]

xc2000 CLB_SW switchbox INT muxes IMUX_CLB_D_N
Bits					Destination
MAIN[5][0]	MAIN[6][1]	MAIN[4][0]	MAIN[5][1]	MAIN[6][0]	CELL.IMUX_CLB_D_N
					Source
0	0	1	1	1	CELL.SINGLE_HS[0]
0	1	0	0	1	CELL.SINGLE_HS[1]
0	1	0	1	0	CELL.SINGLE_HS[2]
0	1	1	0	1	CELL.SINGLE_HS[3]
0	1	1	1	0	CELL.LONG_HS
1	1	0	1	1	CELL.LONG_IO_S
1	1	1	1	1	CELL.OUT_IO_S_I[0]

xc2000 CLB_SW switchbox INT muxes IMUX_CLB_K
Bits				Destination
MAIN[11][7]	MAIN[14][7]	MAIN[15][7]	MAIN[13][7]	CELL.IMUX_CLB_K
				Source
0	0	1	1	CELL.LONG_V[1]
0	1	0	1	CELL.GCLK
0	1	1	0	CELL.SPECIAL_CLB_C
0	1	1	1	~CELL.SPECIAL_CLB_G
1	1	1	1	off

xc2000 CLB_SW switchbox INT muxes IMUX_IO_W_O[0]
Bits				Destination
MAIN[17][11]	MAIN[18][11]	MAIN[17][9]	MAIN[19][11]	CELL.IMUX_IO_W_O[0]
				Source
0	0	0	1	CELL.SINGLE_VW[3]
0	0	1	1	CELL.SINGLE_H[2]
0	1	0	0	CELL.SINGLE_VW[1]
0	1	1	0	CELL.LONG_H
1	1	0	1	CELL.LONG_V[1]
1	1	1	1	CELL.SINGLE_H[0]

xc2000 CLB_SW switchbox INT muxes IMUX_IO_W_T[0]
Bits			Destination
MAIN[20][7]	MAIN[19][7]	MAIN[18][7]	CELL.IMUX_IO_W_T[0]
			Source
0	0	0	CELL.SINGLE_VW[0]
0	0	1	CELL.SINGLE_VW[2]
0	1	0	CELL.LONG_V[0]
0	1	1	CELL.LONG_IO_W
1	0	1	CELL.TIE_1
1	1	1	CELL.TIE_0

xc2000 CLB_SW switchbox INT muxes IMUX_IO_S_O[0]
Bits					Destination
MAIN[16][0]	MAIN[15][1]	MAIN[16][1]	MAIN[17][0]	MAIN[17][1]	CELL.IMUX_IO_S_O[0]
					Source
0	0	0	1	1	CELL.LONG_V[0]
0	0	1	0	1	CELL.LONG_IO_S
0	0	1	1	0	CELL.LONG_IO_W
0	1	1	1	1	CELL.SINGLE_HS[0]
1	0	0	1	1	CELL.SINGLE_HS[2]
1	0	1	0	1	CELL.SINGLE_VW[2]
1	1	1	1	1	CELL.SINGLE_VW[0]

xc2000 CLB_SW switchbox INT muxes IMUX_IO_S_O[1]
Bits					Destination
MAIN_E[17][1]	MAIN[1][1]	MAIN[2][0]	MAIN[1][0]	MAIN[0][0]	CELL.IMUX_IO_S_O[1]
					Source
0	0	0	1	1	CELL.SINGLE_HS[1]
0	0	1	1	1	CELL.LONG_HS
0	1	0	0	1	CELL.OUT_CLB_X
0	1	0	1	0	E.SINGLE_V[3]
0	1	1	0	1	CELL.SINGLE_HS[3]
0	1	1	1	0	E.SINGLE_V[4]
1	1	0	1	1	E.SINGLE_V[1]
1	1	1	1	1	E.LONG_V[1]

xc2000 CLB_SW switchbox INT muxes IMUX_IO_S_T[0]
Bits			Destination
MAIN[15][0]	MAIN[12][0]	MAIN[14][0]	CELL.IMUX_IO_S_T[0]
			Source
0	0	1	CELL.SINGLE_HS[3]
0	1	0	CELL.TIE_1
0	1	1	CELL.LONG_HS
1	0	1	CELL.LONG_IO_S
1	1	0	CELL.TIE_0
1	1	1	CELL.SINGLE_HS[1]

xc2000 CLB_SW switchbox INT muxes IMUX_IO_S_T[1]
Bits			Destination
MAIN[10][0]	MAIN[11][0]	MAIN[9][0]	CELL.IMUX_IO_S_T[1]
			Source
0	0	1	CELL.SINGLE_HS[3]
0	1	0	CELL.TIE_0
0	1	1	CELL.LONG_HS
1	0	1	CELL.LONG_IO_S
1	1	0	CELL.TIE_1
1	1	1	CELL.SINGLE_HS[1]

Bels CLB

xc2000 CLB_SW bel CLB pins
Pin	Direction	CLB
A	in	CELL.IMUX_CLB_A
B	in	CELL.IMUX_CLB_B
C	in	CELL.IMUX_CLB_C
D	in	CELL.IMUX_CLB_D_N
K	in	CELL.IMUX_CLB_K invert by !MAIN[12][7]
X	out	CELL.OUT_CLB_X
Y	out	CELL.OUT_CLB_Y

xc2000 CLB_SW bel CLB attribute bits
Attribute	CLB
F bit 0	!MAIN[16][4]
F bit 1	!MAIN[17][4]
F bit 2	!MAIN[15][4]
F bit 3	!MAIN[14][4]
F bit 4	!MAIN[12][4]
F bit 5	!MAIN[13][4]
F bit 6	!MAIN[11][4]
F bit 7	!MAIN[10][4]
G bit 0	!MAIN[1][4]
G bit 1	!MAIN[0][4]
G bit 2	!MAIN[2][4]
G bit 3	!MAIN[3][4]
G bit 4	!MAIN[5][4]
G bit 5	!MAIN[4][4]
G bit 6	!MAIN[6][4]
G bit 7	!MAIN[7][4]
MODE	[enum: CLB_MODE]
FF_MODE	[enum: FF_MODE]
MUX_F1	[enum: CLB_MUX_I1]
MUX_G1	[enum: CLB_MUX_I1]
MUX_F2	[enum: CLB_MUX_I2]
MUX_G2	[enum: CLB_MUX_I2]
MUX_F3	[enum: CLB_MUX_I3]
MUX_G3	[enum: CLB_MUX_I3]
MUX_X	[enum: CLB_MUX_XY]
MUX_Y	[enum: CLB_MUX_XY]
MUX_RES	[enum: CLB_MUX_RES]
MUX_SET	[enum: CLB_MUX_SET]
READBACK_Q bit 0	!MAIN[3][6]

xc2000 CLB_SW enum CLB_MODE
CLB.MODE	MAIN[8][4]
FGM	1
FG	0

xc2000 CLB_SW enum FF_MODE
CLB.FF_MODE	MAIN[8][6]
FF	1
LATCH	0

xc2000 CLB_SW enum CLB_MUX_I1
CLB.MUX_F1	MAIN[10][5]
CLB.MUX_G1	MAIN[6][5]
A	0
B	1

xc2000 CLB_SW enum CLB_MUX_I2
CLB.MUX_F2	MAIN[11][5]
CLB.MUX_G2	MAIN[5][5]
B	0
C	1

xc2000 CLB_SW enum CLB_MUX_I3
CLB.MUX_F3	MAIN[16][5]	MAIN[17][5]
CLB.MUX_G3	MAIN[1][5]	MAIN[0][5]
C	0	1
D	1	0
Q	1	1

xc2000 CLB_SW enum CLB_MUX_XY
CLB.MUX_X	MAIN[7][6]	MAIN[6][6]
CLB.MUX_Y	MAIN[4][6]	MAIN[5][6]
F	0	1
G	1	0
Q	1	1

xc2000 CLB_SW enum CLB_MUX_RES
CLB.MUX_RES	MAIN[16][6]	MAIN[17][6]
D	0	1
G	0	0
TIE_0	1	1

xc2000 CLB_SW enum CLB_MUX_SET
CLB.MUX_SET	MAIN[15][6]	MAIN[14][6]
A	1	1
F	1	0
TIE_0	0	1

Bels IO

xc2000 CLB_SW bel IO pins
Pin	Direction	IO_W[0]	IO_S[0]	IO_S[1]
O	in	CELL.IMUX_IO_W_O[0]	CELL.IMUX_IO_S_O[0]	CELL.IMUX_IO_S_O[1]
T	in	CELL.IMUX_IO_W_T[0]	CELL.IMUX_IO_S_T[0]	CELL.IMUX_IO_S_T[1]
K	in	CELL.IOCLK_W	CELL.IOCLK_S	CELL.IOCLK_S
I	out	CELL.OUT_IO_W_I[0]	CELL.OUT_IO_S_I[0]	CELL.OUT_IO_S_I[1]

xc2000 CLB_SW bel IO attribute bits
Attribute	IO_W[0]	IO_S[0]	IO_S[1]
MUX_I	[enum: IO_MUX_I]	[enum: IO_MUX_I]	[enum: IO_MUX_I]
READBACK_Q bit 0	!MAIN[18][9]	!MAIN[4][1]	!MAIN[8][0]

xc2000 CLB_SW enum IO_MUX_I
IO_W[0].MUX_I	MAIN[20][11]
IO_S[0].MUX_I	MAIN[13][0]
IO_S[1].MUX_I	MAIN[7][0]
PAD	0
Q	1

Bels MISC_SW

xc2000 CLB_SW bel MISC_SW pins
Pin	Direction	MISC_SW

xc2000 CLB_SW bel MISC_SW attribute bits
Attribute	MISC_SW
READBACK_MODE	[enum: READBACK_MODE]

xc2000 CLB_SW enum READBACK_MODE
MISC_SW.READBACK_MODE	MAIN[19][0]	MAIN[18][0]
COMMAND	0	0
ONCE	0	1
DISABLE	1	1

Bel wires

xc2000 CLB_SW bel wires
Wire	Pins
CELL.IOCLK_W	IO_W[0].K
CELL.IOCLK_S	IO_S[0].K, IO_S[1].K
CELL.IMUX_CLB_A	CLB.A
CELL.IMUX_CLB_B	CLB.B
CELL.IMUX_CLB_C	CLB.C
CELL.IMUX_CLB_D_N	CLB.D
CELL.IMUX_CLB_K	CLB.K
CELL.IMUX_IO_W_O[0]	IO_W[0].O
CELL.IMUX_IO_W_T[0]	IO_W[0].T
CELL.IMUX_IO_S_O[0]	IO_S[0].O
CELL.IMUX_IO_S_O[1]	IO_S[1].O
CELL.IMUX_IO_S_T[0]	IO_S[0].T
CELL.IMUX_IO_S_T[1]	IO_S[1].T
CELL.OUT_CLB_X	CLB.X
CELL.OUT_CLB_Y	CLB.Y
CELL.OUT_IO_W_I[0]	IO_W[0].I
CELL.OUT_IO_S_I[0]	IO_S[0].I
CELL.OUT_IO_S_I[1]	IO_S[1].I

Bitstream

xc2000 CLB_SW rect MAIN
Bit	Frame
Bit	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B11	IO_W[0]: MUX_I bit 0	INT: mux CELL.IMUX_IO_W_O[0] bit 0	INT: mux CELL.IMUX_IO_W_O[0] bit 2	INT: mux CELL.IMUX_IO_W_O[0] bit 3	INT: !bipass CELL.SINGLE_VW[0] = CELL.SINGLE_VW_S[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_VW[0]	INT: !bipass CELL.SINGLE_VW[0] = CELL.SINGLE_VW_S[1]	INT: !bipass CELL.SINGLE_VW[1] = CELL.SINGLE_VW_S[0]	INT: !bipass CELL.SINGLE_VW[1] = CELL.SINGLE_VW_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_VW_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_VW[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_VW[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_VW_S[1]	-	-	-	-	INT: !bipass CELL.SINGLE_VW[2] = CELL.SINGLE_VW_S[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_VW[3]	INT: !bipass CELL.SINGLE_VW[2] = CELL.SINGLE_VW_S[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_VW[2]
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_VW_S[3]	INT: !bipass CELL.SINGLE_VW[3] = CELL.SINGLE_VW_S[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_VW_S[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_VW[3]
B9	-	-	IO_W[0]: ! READBACK_Q bit 0	INT: mux CELL.IMUX_IO_W_O[0] bit 1	INT: !bipass CELL.SINGLE_VW[0] = CELL.LONG_H	INT: !bipass CELL.LONG_H = CELL.LONG_IO_W	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_VW_S[0]	INT: !pass CELL.LONG_H ← CELL.OUT_IO_W_I_S1	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_W_I_S1	INT: !bipass CELL.SINGLE_H[0] = CELL.LONG_V[0]	INT: !bipass CELL.LONG_H = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_VW_S[3]	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_W_I[0]	INT: !pass CELL.SINGLE_VW[2] ← CELL.OUT_IO_W_I[0]	INT: !bipass CELL.LONG_H = CELL.LONG_V[1]	INT: mux CELL.IMUX_CLB_A bit 0	INT: !bipass CELL.SINGLE_VW[3] = CELL.LONG_H	INT: mux CELL.IMUX_CLB_D bit 1	INT: !bipass CELL.SINGLE_VW[3] = CELL.SINGLE_VW_S[2]	-
B8	-	-	-	INT: mux CELL.IMUX_CLB_B bit 4	INT: mux CELL.IMUX_CLB_C bit 3	INT: mux CELL.IMUX_CLB_B bit 2	INT: mux CELL.IMUX_CLB_B bit 1	INT: mux CELL.IMUX_CLB_C bit 1	INT: mux CELL.IMUX_CLB_C bit 0	INT: mux CELL.IMUX_CLB_B bit 0	INT: mux CELL.IMUX_CLB_C bit 4	-	INT: mux CELL.IMUX_CLB_C bit 2	INT: mux CELL.IMUX_CLB_B bit 5	INT: mux CELL.IMUX_CLB_B bit 3	-	-	-	-	-	-
B7	INT: mux CELL.IMUX_IO_W_T[0] bit 2	INT: mux CELL.IMUX_IO_W_T[0] bit 1	INT: mux CELL.IMUX_IO_W_T[0] bit 0	INT: !pass CELL.SINGLE_VW[0] ← CELL.OUT_IO_W_I[0]	INT: !pass CELL.LONG_IO_W ← CELL.OUT_IO_W_I[0]	INT: mux CELL.IMUX_CLB_K bit 1	INT: mux CELL.IMUX_CLB_K bit 2	INT: mux CELL.IMUX_CLB_K bit 0	CLB: !invert K	INT: mux CELL.IMUX_CLB_K bit 3	-	-	INT: !pass CELL.LONG_V[0] ← CELL.OUT_IO_W_I[0]	-	-	INT: mux CELL.IMUX_CLB_D bit 0	INT: mux CELL.IMUX_CLB_D bit 2	INT: mux CELL.IMUX_CLB_A bit 2	INT: mux CELL.IMUX_CLB_A bit 1	INT: mux CELL.IMUX_CLB_A bit 3	INT: mux CELL.IMUX_CLB_D bit 3
B6	-	-	-	CLB: MUX_RES bit 0	CLB: MUX_RES bit 1	CLB: MUX_SET bit 1	CLB: MUX_SET bit 0	-	-	-	-	-	CLB: FF_MODE bit 0	CLB: MUX_X bit 1	CLB: MUX_X bit 0	CLB: MUX_Y bit 0	CLB: MUX_Y bit 1	CLB: ! READBACK_Q bit 0	-	-	-
B5	-	-	-	CLB: MUX_F3 bit 0	CLB: MUX_F3 bit 1	-	-	-	-	CLB: MUX_F2 bit 0	CLB: MUX_F1 bit 0	-	-	-	CLB: MUX_G1 bit 0	CLB: MUX_G2 bit 0	-	-	-	CLB: MUX_G3 bit 1	CLB: MUX_G3 bit 0
B4	-	-	-	CLB: ! F bit 1	CLB: ! F bit 0	CLB: ! F bit 2	CLB: ! F bit 3	CLB: ! F bit 5	CLB: ! F bit 4	CLB: ! F bit 6	CLB: ! F bit 7	-	CLB: MODE bit 0	CLB: ! G bit 7	CLB: ! G bit 6	CLB: ! G bit 4	CLB: ! G bit 5	CLB: ! G bit 3	CLB: ! G bit 2	CLB: ! G bit 0	CLB: ! G bit 1
B3	INT: mux CELL.IOCLK_W bit 0	INT: mux CELL.IOCLK_W bit 1	INT: mux CELL.IOCLK_W bit 2	INT: mux CELL.IOCLK_W bit 3	INT: mux CELL.IOCLK_S bit 0	INT: mux CELL.IOCLK_S bit 3	INT: !bipass CELL.LONG_IO_S = CELL.LONG_IO_W	INT: !bipass CELL.SINGLE_VW[0] = CELL.LONG_IO_S	INT: !bipass CELL.SINGLE_HS[3] = CELL.SINGLE_VW[0]	INT: !bipass CELL.SINGLE_HS[3] = CELL.LONG_IO_W	INT: !pass CELL.LONG_IO_W ← CELL.OUT_IO_S_I[0]	INT: !pass CELL.SINGLE_VW[1] ← CELL.OUT_IO_S_I[0]	INT: !bipass CELL.SINGLE_HS[2] = CELL.SINGLE_VW[1]	INT: !bipass CELL.LONG_HS = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_HS[1] = CELL.SINGLE_VW[2]	-	INT: !bipass CELL.LONG_HS = CELL.LONG_V[1]	INT: !pass CELL.LONG_HS ← CELL.OUT_IO_S_I[0]	INT: !pass CELL.SINGLE_HS[3] ← CELL.OUT_IO_S_I[0]	INT: !pass CELL.SINGLE_HS[1] ← CELL.OUT_IO_S_I[0]	INT: !bipass CELL.SINGLE_HS[0] = CELL.SINGLE_VW[3]
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	INT: mux CELL.IOCLK_S bit 1	INT: mux CELL.IOCLK_S bit 2	INT: mux CELL.IMUX_IO_S_O[0] bit 0	INT: mux CELL.IMUX_IO_S_O[0] bit 2	INT: mux CELL.IMUX_IO_S_O[0] bit 3	-	-	-	INT: !pass CELL.LONG_V[1] ← CELL.OUT_IO_S_I[0]	INT: !pass CELL.SINGLE_VW[3] ← CELL.OUT_IO_S_I[0]	INT: !pass CELL.LONG_V[1] ← CELL.ACLK	INT: !bipass CELL.LONG_IO_S = CELL.LONG_V[0]	INT: !pass CELL.SINGLE_HS[2] ← CELL.OUT_IO_S_I[1]	INT: mux CELL.IMUX_CLB_D_N bit 3	INT: mux CELL.IMUX_CLB_D_N bit 1	IO_S[0]: ! READBACK_Q bit 0	INT: !pass CELL.SINGLE_HS[0] ← CELL.OUT_IO_S_I[1]	INT: !pass CELL.LONG_IO_S ← CELL.OUT_IO_S_I[1]	INT: mux CELL.IMUX_IO_S_O[1] bit 3	INT: !bipass CELL.SINGLE_VW[3] = CELL.LONG_HS
B0	-	MISC_SW: READBACK_MODE bit 1	MISC_SW: READBACK_MODE bit 0	INT: mux CELL.IMUX_IO_S_O[0] bit 1	INT: mux CELL.IMUX_IO_S_O[0] bit 4	INT: mux CELL.IMUX_IO_S_T[0] bit 2	INT: mux CELL.IMUX_IO_S_T[0] bit 0	IO_S[0]: MUX_I bit 0	INT: mux CELL.IMUX_IO_S_T[0] bit 1	INT: mux CELL.IMUX_IO_S_T[1] bit 1	INT: mux CELL.IMUX_IO_S_T[1] bit 2	INT: mux CELL.IMUX_IO_S_T[1] bit 0	IO_S[1]: ! READBACK_Q bit 0	IO_S[1]: MUX_I bit 0	INT: mux CELL.IMUX_CLB_D_N bit 0	INT: mux CELL.IMUX_CLB_D_N bit 4	INT: mux CELL.IMUX_CLB_D_N bit 2	INT: !bipass CELL.SINGLE_HS[1] = CELL.LONG_V[1]	INT: mux CELL.IMUX_IO_S_O[1] bit 2	INT: mux CELL.IMUX_IO_S_O[1] bit 1	INT: mux CELL.IMUX_IO_S_O[1] bit 0

xc2000 CLB_SW rect MAIN_E
Bit	Frame
Bit	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	INT: mux CELL.IMUX_IO_S_O[1] bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile CLB_SE

Cells: 1

Switchbox INT

xc2000 CLB_SE switchbox INT pass gates
Destination	Source	Bit
SINGLE_H[0]	OUT_IO_E_I[0]	!MAIN[1][8]
SINGLE_H[1]	OUT_IO_E_I_S1	!MAIN[3][8]
SINGLE_H[2]	OUT_IO_E_I[0]	!MAIN[7][8]
SINGLE_H[3]	OUT_IO_E_I_S1	!MAIN[4][8]
SINGLE_HS[0]	OUT_IO_S_I[1]	!MAIN[12][1]
SINGLE_HS[1]	OUT_IO_S_I[0]	!MAIN[17][3]
SINGLE_HS[2]	OUT_IO_S_I[1]	!MAIN[16][1]
SINGLE_HS[3]	OUT_IO_S_I[0]	!MAIN[20][2]
SINGLE_V[0]	OUT_CLB_Y_E	!MAIN[26][7]
SINGLE_V[0]	OUT_IO_S_I_E1	!MAIN[23][3]
SINGLE_V[1]	OUT_CLB_X_E	!MAIN[19][7]
SINGLE_V[1]	OUT_IO_S_I[0]	!MAIN[20][3]
SINGLE_V[2]	OUT_CLB_Y_E	!MAIN[15][7]
SINGLE_V[2]	OUT_IO_S_I_E1	!MAIN[16][3]
SINGLE_V[3]	OUT_CLB_X_E	!MAIN[18][8]
SINGLE_V[3]	OUT_IO_S_I[0]	!MAIN[19][1]
SINGLE_V[4]	OUT_CLB_Y_E	!MAIN[25][7]
SINGLE_V[4]	OUT_IO_S_I[0]	!MAIN[19][2]
SINGLE_VE[0]	OUT_CLB_Y	!MAIN[4][7]
SINGLE_VE[0]	OUT_IO_S_I[1]	!MAIN[3][5]
SINGLE_VE[1]	OUT_CLB_X	!MAIN[3][7]
SINGLE_VE[1]	OUT_IO_E_I[0]	!MAIN[2][8]
SINGLE_VE[2]	OUT_CLB_Y	!MAIN[6][7]
SINGLE_VE[2]	OUT_IO_S_I[1]	!MAIN[5][5]
SINGLE_VE[3]	OUT_CLB_X	!MAIN[8][7]
SINGLE_VE[3]	OUT_IO_E_I[0]	!MAIN[8][8]
LONG_H	OUT_IO_E_I[0]	!MAIN[6][6]
LONG_HS	OUT_IO_S_I[0]	!MAIN[18][3]
LONG_IO_S	OUT_IO_S_I[1]	!MAIN[11][1]
LONG_V[0]	OUT_CLB_X_E	!MAIN[17][7]
LONG_V[0]	OUT_IO_S_I_E1	!MAIN[17][2]
LONG_V[1]	ACLK	!MAIN[18][1]
LONG_V[1]	OUT_CLB_Y_E	!MAIN[16][7]
LONG_V[1]	OUT_IO_S_I[0]	!MAIN[20][1]
LONG_VE[0]	OUT_CLB_Y	!MAIN[5][7]
LONG_VE[0]	OUT_IO_S_I[1]	!MAIN[4][5]
LONG_VE[1]	OUT_CLB_X	!MAIN[2][7]
LONG_VE[1]	OUT_IO_E_I[0]	!MAIN[0][8]
LONG_IO_E	OUT_CLB_Y	!MAIN[7][7]
LONG_IO_E	OUT_IO_S_I[1]	!MAIN[7][6]

xc2000 CLB_SE switchbox INT bidirectional pass gates
Side A	Side B	Bit
SINGLE_H[0]	SINGLE_H_E[0]	!MAIN[23][11]
SINGLE_H[0]	SINGLE_H_E[1]	!MAIN[24][11]
SINGLE_H[0]	SINGLE_V[1]	!MAIN[19][10]
SINGLE_H[0]	SINGLE_V_S[0]	!MAIN[18][9]
SINGLE_H[0]	SINGLE_V_S[1]	!MAIN[20][11]
SINGLE_H[0]	SINGLE_VE[0]	!MAIN[2][9]
SINGLE_H[0]	SINGLE_VE_S[0]	!MAIN[1][10]
SINGLE_H[0]	SINGLE_VE_S[1]	!MAIN[1][11]
SINGLE_H[0]	LONG_V[1]	!MAIN[15][9]
SINGLE_H[0]	LONG_VE[1]	!MAIN[0][9]
SINGLE_H[1]	SINGLE_H_E[0]	!MAIN[25][10]
SINGLE_H[1]	SINGLE_H_E[1]	!MAIN[24][10]
SINGLE_H[1]	SINGLE_V[0]	!MAIN[18][11]
SINGLE_H[1]	SINGLE_V[1]	!MAIN[19][11]
SINGLE_H[1]	SINGLE_V[4]	!MAIN[20][9]
SINGLE_H[1]	SINGLE_V_S[1]	!MAIN[20][10]
SINGLE_H[1]	SINGLE_V_S[4]	!MAIN[23][9]
SINGLE_H[1]	SINGLE_VE[0]	!MAIN[3][9]
SINGLE_H[1]	SINGLE_VE[1]	!MAIN[0][11]
SINGLE_H[1]	SINGLE_VE_S[0]	!MAIN[0][10]
SINGLE_H[1]	LONG_V[0]	!MAIN[19][9]
SINGLE_H[1]	LONG_VE[0]	!MAIN[6][9]
SINGLE_H[2]	SINGLE_H_E[2]	!MAIN[12][11]
SINGLE_H[2]	SINGLE_H_E[3]	!MAIN[10][10]
SINGLE_H[2]	SINGLE_V[3]	!MAIN[10][9]
SINGLE_H[2]	SINGLE_V[4]	!MAIN[21][9]
SINGLE_H[2]	SINGLE_V_S[2]	!MAIN[12][10]
SINGLE_H[2]	SINGLE_V_S[3]	!MAIN[10][11]
SINGLE_H[2]	SINGLE_V_S[4]	!MAIN[22][9]
SINGLE_H[2]	SINGLE_VE[2]	!MAIN[6][10]
SINGLE_H[2]	SINGLE_VE_S[2]	!MAIN[6][11]
SINGLE_H[2]	SINGLE_VE_S[3]	!MAIN[8][11]
SINGLE_H[2]	LONG_V[1]	!MAIN[14][9]
SINGLE_H[2]	LONG_VE[1]	!MAIN[6][8]
SINGLE_H[3]	SINGLE_H_E[2]	!MAIN[11][11]
SINGLE_H[3]	SINGLE_H_E[3]	!MAIN[11][10]
SINGLE_H[3]	SINGLE_V[2]	!MAIN[13][10]
SINGLE_H[3]	SINGLE_V[3]	!MAIN[9][10]
SINGLE_H[3]	SINGLE_V_S[3]	!MAIN[9][11]
SINGLE_H[3]	SINGLE_VE[2]	!MAIN[4][10]
SINGLE_H[3]	SINGLE_VE[3]	!MAIN[7][10]
SINGLE_H[3]	SINGLE_VE_S[2]	!MAIN[4][11]
SINGLE_H[3]	LONG_V[0]	!MAIN[16][9]
SINGLE_H[3]	LONG_VE[0]	!MAIN[5][8]
SINGLE_H_E[0]	SINGLE_V[0]	!MAIN[26][9]
SINGLE_H_E[0]	SINGLE_V_S[0]	!MAIN[25][11]
SINGLE_H_E[0]	SINGLE_V_S[1]	!MAIN[23][10]
SINGLE_H_E[1]	SINGLE_V[0]	!MAIN[26][10]
SINGLE_H_E[1]	SINGLE_V[1]	!MAIN[22][10]
SINGLE_H_E[1]	SINGLE_V_S[0]	!MAIN[26][11]
SINGLE_H_E[2]	SINGLE_V[2]	!MAIN[16][10]
SINGLE_H_E[2]	SINGLE_V_S[2]	!MAIN[15][11]
SINGLE_H_E[2]	SINGLE_V_S[3]	!MAIN[17][9]
SINGLE_H_E[3]	SINGLE_V[2]	!MAIN[16][11]
SINGLE_H_E[3]	SINGLE_V[3]	!MAIN[17][11]
SINGLE_H_E[3]	SINGLE_V_S[2]	!MAIN[15][10]
SINGLE_HS[0]	SINGLE_HS_E[0]	!MAIN[12][3]
SINGLE_HS[0]	SINGLE_HS_E[1]	!MAIN[13][3]
SINGLE_HS[0]	SINGLE_V[2]	!MAIN[11][3]
SINGLE_HS[0]	SINGLE_V[3]	!MAIN[9][2]
SINGLE_HS[0]	SINGLE_VE[0]	!MAIN[3][3]
SINGLE_HS[0]	LONG_V[0]	!MAIN[14][2]
SINGLE_HS[1]	SINGLE_HS_E[0]	!MAIN[10][2]
SINGLE_HS[1]	SINGLE_HS_E[1]	!MAIN[11][2]
SINGLE_HS[1]	SINGLE_V[3]	!MAIN[9][3]
SINGLE_HS[1]	SINGLE_V[4]	!MAIN[18][2]
SINGLE_HS[1]	SINGLE_VE[1]	!MAIN[2][3]
SINGLE_HS[1]	LONG_V[1]	!MAIN[12][0]
SINGLE_HS[2]	SINGLE_HS_E[2]	!MAIN[25][3]
SINGLE_HS[2]	SINGLE_HS_E[3]	!MAIN[26][2]
SINGLE_HS[2]	SINGLE_V[0]	!MAIN[24][3]
SINGLE_HS[2]	SINGLE_V[1]	!MAIN[21][3]
SINGLE_HS[2]	SINGLE_V[4]	!MAIN[19][3]
SINGLE_HS[2]	SINGLE_VE[2]	!MAIN[5][3]
SINGLE_HS[2]	LONG_V[0]	!MAIN[16][2]
SINGLE_HS[3]	SINGLE_HS_E[2]	!MAIN[22][2]
SINGLE_HS[3]	SINGLE_HS_E[3]	!MAIN[23][2]
SINGLE_HS[3]	SINGLE_V[1]	!MAIN[21][2]
SINGLE_HS[3]	SINGLE_VE[3]	!MAIN[8][2]
SINGLE_HS[3]	LONG_V[1]	!MAIN[14][3]
SINGLE_HS[3]	LONG_IO_E	!MAIN[7][3]
SINGLE_HS_E[0]	SINGLE_V[2]	!MAIN[12][2]
SINGLE_HS_E[0]	SINGLE_V[3]	!MAIN[10][3]
SINGLE_HS_E[1]	SINGLE_V[2]	!MAIN[13][2]
SINGLE_HS_E[2]	SINGLE_V[0]	!MAIN[25][2]
SINGLE_HS_E[2]	SINGLE_V[1]	!MAIN[22][3]
SINGLE_HS_E[3]	SINGLE_V[0]	!MAIN[26][3]
SINGLE_V[0]	SINGLE_V_S[0]	!MAIN[18][10]
SINGLE_V[0]	SINGLE_V_S[1]	!MAIN[21][11]
SINGLE_V[0]	LONG_H	!MAIN[25][9]
SINGLE_V[0]	LONG_HS	!MAIN[24][2]
SINGLE_V[1]	SINGLE_V_S[0]	!MAIN[22][11]
SINGLE_V[1]	SINGLE_V_S[1]	!MAIN[21][10]
SINGLE_V[2]	SINGLE_V_S[2]	!MAIN[14][10]
SINGLE_V[2]	SINGLE_V_S[3]	!MAIN[13][11]
SINGLE_V[3]	SINGLE_V_S[2]	!MAIN[14][11]
SINGLE_V[3]	SINGLE_V_S[3]	!MAIN[17][10]
SINGLE_V[3]	LONG_H	!MAIN[12][9]
SINGLE_V[3]	LONG_HS	!MAIN[9][1]
SINGLE_V[4]	SINGLE_V_S[4]	!MAIN[24][9]
SINGLE_VE[0]	SINGLE_VE_S[0]	!MAIN[3][10]
SINGLE_VE[0]	SINGLE_VE_S[1]	!MAIN[3][11]
SINGLE_VE[0]	LONG_H	!MAIN[4][9]
SINGLE_VE[1]	SINGLE_VE_S[0]	!MAIN[2][11]
SINGLE_VE[1]	SINGLE_VE_S[1]	!MAIN[2][10]
SINGLE_VE[2]	SINGLE_VE_S[2]	!MAIN[5][11]
SINGLE_VE[2]	SINGLE_VE_S[3]	!MAIN[5][10]
SINGLE_VE[3]	SINGLE_VE_S[2]	!MAIN[7][11]
SINGLE_VE[3]	SINGLE_VE_S[3]	!MAIN[8][10]
SINGLE_VE[3]	LONG_H	!MAIN[8][9]
SINGLE_VE[3]	LONG_IO_S	!MAIN[8][3]
LONG_H	LONG_VE[0]	!MAIN[5][9]
LONG_H	LONG_VE[1]	!MAIN[1][9]
LONG_H	LONG_IO_E	!MAIN[7][9]
LONG_HS	LONG_V[0]	!MAIN[15][2]
LONG_HS	LONG_V[1]	!MAIN[15][3]
LONG_HS	LONG_VE[0]	!MAIN[4][3]
LONG_HS	LONG_VE[1]	!MAIN[1][3]
LONG_IO_S	LONG_V[0]	!MAIN[17][1]
LONG_IO_S	LONG_IO_E	!MAIN[6][3]

xc2000 CLB_SE switchbox INT muxes IMUX_CLB_A
Bits				Destination
MAIN[10][7]	MAIN[12][7]	MAIN[11][7]	MAIN[13][9]	IMUX_CLB_A
				Source
0	0	0	1	SINGLE_H[3]
0	0	1	1	SINGLE_H[0]
0	1	0	0	SINGLE_H[2]
0	1	1	0	OUT_CLB_X_S
1	1	0	1	LONG_H
1	1	1	1	SINGLE_H[1]

xc2000 CLB_SE switchbox INT muxes IMUX_CLB_B
Bits						Destination
MAIN[16][8]	MAIN[26][8]	MAIN[15][8]	MAIN[24][8]	MAIN[23][8]	MAIN[20][8]	IMUX_CLB_B
						Source
0	0	0	1	1	1	OUT_CLB_Y_E
0	0	1	1	1	1	SINGLE_V[0]
0	1	0	0	1	1	SINGLE_V[1]
0	1	0	1	0	1	SINGLE_V[4]
0	1	0	1	1	0	LONG_V[0]
0	1	1	0	1	1	GCLK
0	1	1	1	0	1	SINGLE_V[3]
0	1	1	1	1	0	LONG_V[1]
1	1	0	1	1	1	OUT_CLB_X_S
1	1	1	1	1	1	SINGLE_V[2]

xc2000 CLB_SE switchbox INT muxes IMUX_CLB_C
Bits					Destination
MAIN[19][8]	MAIN[25][8]	MAIN[17][8]	MAIN[22][8]	MAIN[21][8]	IMUX_CLB_C
					Source
0	0	0	1	1	SINGLE_V[0]
0	0	1	1	1	SINGLE_V[1]
0	1	0	0	1	SINGLE_V[3]
0	1	0	1	0	LONG_V[1]
0	1	1	0	1	SINGLE_V[4]
0	1	1	1	0	LONG_V[0]
1	1	0	1	1	SINGLE_V[2]
1	1	1	1	1	OUT_IO_S_I[0]

xc2000 CLB_SE switchbox INT muxes IMUX_CLB_D
Bits				Destination
MAIN[9][7]	MAIN[13][7]	MAIN[11][9]	MAIN[14][7]	IMUX_CLB_D
				Source
0	0	0	1	SINGLE_H[3]
0	0	1	1	SINGLE_H[0]
0	1	0	0	SINGLE_H[2]
0	1	1	0	OUT_CLB_X
1	1	0	1	LONG_H
1	1	1	1	SINGLE_H[1]

xc2000 CLB_SE switchbox INT muxes IMUX_CLB_D_N
Bits					Destination
MAIN[14][0]	MAIN[15][1]	MAIN[13][0]	MAIN[14][1]	MAIN[15][0]	IMUX_CLB_D_N
					Source
0	0	1	1	1	SINGLE_HS[0]
0	1	0	0	1	SINGLE_HS[1]
0	1	0	1	0	SINGLE_HS[2]
0	1	1	0	1	SINGLE_HS[3]
0	1	1	1	0	LONG_HS
1	1	0	1	1	LONG_IO_S
1	1	1	1	1	OUT_IO_S_I[0]

xc2000 CLB_SE switchbox INT muxes IMUX_CLB_K
Bits				Destination
MAIN[20][7]	MAIN[23][7]	MAIN[24][7]	MAIN[22][7]	IMUX_CLB_K
				Source
0	0	1	1	LONG_V[1]
0	1	0	1	GCLK
0	1	1	0	SPECIAL_CLB_C
0	1	1	1	~SPECIAL_CLB_G
1	1	1	1	off

xc2000 CLB_SE switchbox INT muxes IMUX_IO_E_O[0]
Bits					Destination
MAIN[0][6]	MAIN[1][7]	MAIN[1][6]	MAIN[2][6]	MAIN[3][6]	IMUX_IO_E_O[0]
					Source
0	0	0	1	1	SINGLE_H[1]
0	0	1	0	1	SINGLE_H[3]
0	0	1	1	0	OUT_CLB_X
0	1	0	1	1	SINGLE_VE[2]
0	1	1	0	1	LONG_VE[0]
0	1	1	1	0	SINGLE_VE[0]
1	0	1	1	1	OUT_CLB_Y
1	1	1	1	1	LONG_IO_E

xc2000 CLB_SE switchbox INT muxes IMUX_IO_E_T[0]
Bits			Destination
MAIN[2][5]	MAIN[3][4]	MAIN[1][5]	IMUX_IO_E_T[0]
			Source
0	0	1	LONG_VE[1]
0	1	1	SINGLE_VE[3]
1	0	0	TIE_0
1	0	1	LONG_IO_E
1	1	0	TIE_1
1	1	1	SINGLE_VE[1]

xc2000 CLB_SE switchbox INT muxes IMUX_IO_S_O[0]
Bits				Destination
MAIN[25][0]	MAIN[24][1]	MAIN[25][1]	MAIN[26][0]	IMUX_IO_S_O[0]
				Source
0	0	0	1	LONG_V[0]
0	0	1	0	LONG_IO_S
0	1	1	1	SINGLE_HS[0]
1	0	0	1	SINGLE_HS[2]
1	0	1	0	SINGLE_V[2]
1	1	1	1	SINGLE_V[0]

xc2000 CLB_SE switchbox INT muxes IMUX_IO_S_O[1]
Bits						Destination
MAIN[8][1]	MAIN[11][0]	MAIN[10][1]	MAIN[10][0]	MAIN[9][0]	MAIN[8][0]	IMUX_IO_S_O[1]
						Source
0	0	0	1	1	1	SINGLE_HS[1]
0	0	1	0	1	1	OUT_CLB_X
0	0	1	1	0	1	SINGLE_VE[3]
0	0	1	1	1	0	ACLK
0	1	0	1	1	1	LONG_HS
0	1	1	0	1	1	SINGLE_HS[3]
0	1	1	1	0	1	LONG_VE[1]
1	0	1	1	1	1	SINGLE_VE[1]
1	1	1	1	1	1	LONG_IO_E

xc2000 CLB_SE switchbox INT muxes IMUX_IO_S_T[0]
Bits			Destination
MAIN[24][0]	MAIN[21][0]	MAIN[23][0]	IMUX_IO_S_T[0]
			Source
0	0	1	SINGLE_HS[3]
0	1	0	TIE_1
0	1	1	LONG_HS
1	0	1	LONG_IO_S
1	1	0	TIE_0
1	1	1	SINGLE_HS[1]

xc2000 CLB_SE switchbox INT muxes IMUX_IO_S_T[1]
Bits			Destination
MAIN[19][0]	MAIN[20][0]	MAIN[18][0]	IMUX_IO_S_T[1]
			Source
0	0	1	SINGLE_HS[3]
0	1	0	TIE_0
0	1	1	LONG_HS
1	0	1	LONG_IO_S
1	1	0	TIE_1
1	1	1	SINGLE_HS[1]

xc2000 CLB_SE switchbox INT muxes IMUX_BUFG
Bits								Destination
MAIN[2][2]	MAIN[3][2]	MAIN[6][2]	MAIN[4][2]	MAIN[7][2]	MAIN[5][2]	MAIN[7][0]	MAIN[6][0]	IMUX_BUFG
								Source
0	0	1	1	1	1	1	1	SINGLE_VE[1]
0	1	0	1	1	1	1	1	LONG_HS
0	1	1	0	1	1	1	1	LONG_VE[1]
0	1	1	1	0	1	1	1	OUT_IO_E_I[0]
0	1	1	1	1	0	1	1	OUT_IO_S_I[1]
1	1	1	1	1	1	0	0	OUT_OSC
1	1	1	1	1	1	1	1	SINGLE_HS[1]

Switchbox BUFG

xc2000 CLB_SE switchbox BUFG permanent buffers
Destination	Source
ACLK	IMUX_BUFG

Bels CLB

xc2000 CLB_SE bel CLB pins
Pin	Direction	CLB
A	in	IMUX_CLB_A
B	in	IMUX_CLB_B
C	in	IMUX_CLB_C
D	in	IMUX_CLB_D_N
K	in	IMUX_CLB_K invert by !MAIN[21][7]
X	out	OUT_CLB_X
Y	out	OUT_CLB_Y

xc2000 CLB_SE bel CLB attribute bits
Attribute	CLB
F bit 0	!MAIN[25][4]
F bit 1	!MAIN[26][4]
F bit 2	!MAIN[24][4]
F bit 3	!MAIN[23][4]
F bit 4	!MAIN[21][4]
F bit 5	!MAIN[22][4]
F bit 6	!MAIN[20][4]
F bit 7	!MAIN[19][4]
G bit 0	!MAIN[10][4]
G bit 1	!MAIN[9][4]
G bit 2	!MAIN[11][4]
G bit 3	!MAIN[12][4]
G bit 4	!MAIN[14][4]
G bit 5	!MAIN[13][4]
G bit 6	!MAIN[15][4]
G bit 7	!MAIN[16][4]
MODE	[enum: CLB_MODE]
FF_MODE	[enum: FF_MODE]
MUX_F1	[enum: CLB_MUX_I1]
MUX_G1	[enum: CLB_MUX_I1]
MUX_F2	[enum: CLB_MUX_I2]
MUX_G2	[enum: CLB_MUX_I2]
MUX_F3	[enum: CLB_MUX_I3]
MUX_G3	[enum: CLB_MUX_I3]
MUX_X	[enum: CLB_MUX_XY]
MUX_Y	[enum: CLB_MUX_XY]
MUX_RES	[enum: CLB_MUX_RES]
MUX_SET	[enum: CLB_MUX_SET]
READBACK_Q bit 0	!MAIN[12][6]

xc2000 CLB_SE enum CLB_MODE
CLB.MODE	MAIN[17][4]
FGM	1
FG	0

xc2000 CLB_SE enum FF_MODE
CLB.FF_MODE	MAIN[17][6]
FF	1
LATCH	0

xc2000 CLB_SE enum CLB_MUX_I1
CLB.MUX_F1	MAIN[19][5]
CLB.MUX_G1	MAIN[15][5]
A	0
B	1

xc2000 CLB_SE enum CLB_MUX_I2
CLB.MUX_F2	MAIN[20][5]
CLB.MUX_G2	MAIN[14][5]
B	0
C	1

xc2000 CLB_SE enum CLB_MUX_I3
CLB.MUX_F3	MAIN[25][5]	MAIN[26][5]
CLB.MUX_G3	MAIN[10][5]	MAIN[9][5]
C	0	1
D	1	0
Q	1	1

xc2000 CLB_SE enum CLB_MUX_XY
CLB.MUX_X	MAIN[16][6]	MAIN[15][6]
CLB.MUX_Y	MAIN[13][6]	MAIN[14][6]
F	0	1
G	1	0
Q	1	1

xc2000 CLB_SE enum CLB_MUX_RES
CLB.MUX_RES	MAIN[25][6]	MAIN[26][6]
D	0	1
G	0	0
TIE_0	1	1

xc2000 CLB_SE enum CLB_MUX_SET
CLB.MUX_SET	MAIN[24][6]	MAIN[23][6]
A	1	1
F	1	0
TIE_0	0	1

Bels IO

xc2000 CLB_SE bel IO pins
Pin	Direction	IO_E[0]	IO_S[0]	IO_S[1]
O	in	IMUX_IO_E_O[0]	IMUX_IO_S_O[0]	IMUX_IO_S_O[1]
T	in	IMUX_IO_E_T[0]	IMUX_IO_S_T[0]	IMUX_IO_S_T[1]
K	in	IOCLK_E	IOCLK_S	IOCLK_S
I	out	OUT_IO_E_I[0]	OUT_IO_S_I[0]	OUT_IO_S_I[1]

xc2000 CLB_SE bel IO attribute bits
Attribute	IO_E[0]	IO_S[0]	IO_S[1]
MUX_I	[enum: IO_MUX_I]	[enum: IO_MUX_I]	[enum: IO_MUX_I]
READBACK_Q bit 0	!MAIN[0][7]	!MAIN[13][1]	!MAIN[17][0]

xc2000 CLB_SE enum IO_MUX_I
IO_E[0].MUX_I	MAIN[0][5]
IO_S[0].MUX_I	MAIN[22][0]
IO_S[1].MUX_I	MAIN[16][0]
PAD	0
Q	1

Bels OSC

xc2000 CLB_SE bel OSC pins
Pin	Direction	OSC
O	out	OUT_OSC

Bels MISC_SE

xc2000 CLB_SE bel MISC_SE pins
Pin	Direction	MISC_SE

xc2000 CLB_SE bel MISC_SE attribute bits
Attribute	MISC_SE
TLC	!MAIN[0][2]
DONE_PULLUP	!MAIN[0][3]
REPROGRAM_ENABLE	!MAIN[1][2]

Bel wires

xc2000 CLB_SE bel wires
Wire	Pins
IOCLK_E	IO_E[0].K
IOCLK_S	IO_S[0].K, IO_S[1].K
IMUX_CLB_A	CLB.A
IMUX_CLB_B	CLB.B
IMUX_CLB_C	CLB.C
IMUX_CLB_D_N	CLB.D
IMUX_CLB_K	CLB.K
IMUX_IO_E_O[0]	IO_E[0].O
IMUX_IO_E_T[0]	IO_E[0].T
IMUX_IO_S_O[0]	IO_S[0].O
IMUX_IO_S_O[1]	IO_S[1].O
IMUX_IO_S_T[0]	IO_S[0].T
IMUX_IO_S_T[1]	IO_S[1].T
OUT_CLB_X	CLB.X
OUT_CLB_Y	CLB.Y
OUT_IO_E_I[0]	IO_E[0].I
OUT_IO_S_I[0]	IO_S[0].I
OUT_IO_S_I[1]	IO_S[1].I
OUT_OSC	OSC.O

Bitstream

xc2000 CLB_SE rect MAIN
Bit	Frame
Bit	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B11	INT: !bipass SINGLE_H_E[1] = SINGLE_V_S[0]	INT: !bipass SINGLE_H_E[0] = SINGLE_V_S[0]	INT: !bipass SINGLE_H[0] = SINGLE_H_E[1]	INT: !bipass SINGLE_H[0] = SINGLE_H_E[0]	INT: !bipass SINGLE_V[1] = SINGLE_V_S[0]	INT: !bipass SINGLE_V[0] = SINGLE_V_S[1]	INT: !bipass SINGLE_H[0] = SINGLE_V_S[1]	INT: !bipass SINGLE_H[1] = SINGLE_V[1]	INT: !bipass SINGLE_H[1] = SINGLE_V[0]	INT: !bipass SINGLE_H_E[3] = SINGLE_V[3]	INT: !bipass SINGLE_H_E[3] = SINGLE_V[2]	INT: !bipass SINGLE_H_E[2] = SINGLE_V_S[2]	INT: !bipass SINGLE_V[3] = SINGLE_V_S[2]	INT: !bipass SINGLE_V[2] = SINGLE_V_S[3]	INT: !bipass SINGLE_H[2] = SINGLE_H_E[2]	INT: !bipass SINGLE_H[3] = SINGLE_H_E[2]	INT: !bipass SINGLE_H[2] = SINGLE_V_S[3]	INT: !bipass SINGLE_H[3] = SINGLE_V_S[3]	INT: !bipass SINGLE_H[2] = SINGLE_VE_S[3]	INT: !bipass SINGLE_VE[3] = SINGLE_VE_S[2]	INT: !bipass SINGLE_H[2] = SINGLE_VE_S[2]	INT: !bipass SINGLE_VE[2] = SINGLE_VE_S[2]	INT: !bipass SINGLE_H[3] = SINGLE_VE_S[2]	INT: !bipass SINGLE_VE[0] = SINGLE_VE_S[1]	INT: !bipass SINGLE_VE[1] = SINGLE_VE_S[0]	INT: !bipass SINGLE_H[0] = SINGLE_VE_S[1]	INT: !bipass SINGLE_H[1] = SINGLE_VE[1]
B10	INT: !bipass SINGLE_H_E[1] = SINGLE_V[0]	INT: !bipass SINGLE_H[1] = SINGLE_H_E[0]	INT: !bipass SINGLE_H[1] = SINGLE_H_E[1]	INT: !bipass SINGLE_H_E[0] = SINGLE_V_S[1]	INT: !bipass SINGLE_H_E[1] = SINGLE_V[1]	INT: !bipass SINGLE_V[1] = SINGLE_V_S[1]	INT: !bipass SINGLE_H[1] = SINGLE_V_S[1]	INT: !bipass SINGLE_H[0] = SINGLE_V[1]	INT: !bipass SINGLE_V[0] = SINGLE_V_S[0]	INT: !bipass SINGLE_V[3] = SINGLE_V_S[3]	INT: !bipass SINGLE_H_E[2] = SINGLE_V[2]	INT: !bipass SINGLE_H_E[3] = SINGLE_V_S[2]	INT: !bipass SINGLE_V[2] = SINGLE_V_S[2]	INT: !bipass SINGLE_H[3] = SINGLE_V[2]	INT: !bipass SINGLE_H[2] = SINGLE_V_S[2]	INT: !bipass SINGLE_H[3] = SINGLE_H_E[3]	INT: !bipass SINGLE_H[2] = SINGLE_H_E[3]	INT: !bipass SINGLE_H[3] = SINGLE_V[3]	INT: !bipass SINGLE_VE[3] = SINGLE_VE_S[3]	INT: !bipass SINGLE_H[3] = SINGLE_VE[3]	INT: !bipass SINGLE_H[2] = SINGLE_VE[2]	INT: !bipass SINGLE_VE[2] = SINGLE_VE_S[3]	INT: !bipass SINGLE_H[3] = SINGLE_VE[2]	INT: !bipass SINGLE_VE[0] = SINGLE_VE_S[0]	INT: !bipass SINGLE_VE[1] = SINGLE_VE_S[1]	INT: !bipass SINGLE_H[0] = SINGLE_VE_S[0]	INT: !bipass SINGLE_H[1] = SINGLE_VE_S[0]
B9	INT: !bipass SINGLE_H_E[0] = SINGLE_V[0]	INT: !bipass SINGLE_V[0] = LONG_H	INT: !bipass SINGLE_V[4] = SINGLE_V_S[4]	INT: !bipass SINGLE_H[1] = SINGLE_V_S[4]	INT: !bipass SINGLE_H[2] = SINGLE_V_S[4]	INT: !bipass SINGLE_H[2] = SINGLE_V[4]	INT: !bipass SINGLE_H[1] = SINGLE_V[4]	INT: !bipass SINGLE_H[1] = LONG_V[0]	INT: !bipass SINGLE_H[0] = SINGLE_V_S[0]	INT: !bipass SINGLE_H_E[2] = SINGLE_V_S[3]	INT: !bipass SINGLE_H[3] = LONG_V[0]	INT: !bipass SINGLE_H[0] = LONG_V[1]	INT: !bipass SINGLE_H[2] = LONG_V[1]	INT: mux IMUX_CLB_A bit 0	INT: !bipass SINGLE_V[3] = LONG_H	INT: mux IMUX_CLB_D bit 1	INT: !bipass SINGLE_H[2] = SINGLE_V[3]	-	INT: !bipass SINGLE_VE[3] = LONG_H	INT: !bipass LONG_H = LONG_IO_E	INT: !bipass SINGLE_H[1] = LONG_VE[0]	INT: !bipass LONG_H = LONG_VE[0]	INT: !bipass SINGLE_VE[0] = LONG_H	INT: !bipass SINGLE_H[1] = SINGLE_VE[0]	INT: !bipass SINGLE_H[0] = SINGLE_VE[0]	INT: !bipass LONG_H = LONG_VE[1]	INT: !bipass SINGLE_H[0] = LONG_VE[1]
B8	INT: mux IMUX_CLB_B bit 4	INT: mux IMUX_CLB_C bit 3	INT: mux IMUX_CLB_B bit 2	INT: mux IMUX_CLB_B bit 1	INT: mux IMUX_CLB_C bit 1	INT: mux IMUX_CLB_C bit 0	INT: mux IMUX_CLB_B bit 0	INT: mux IMUX_CLB_C bit 4	INT: !pass SINGLE_V[3] ← OUT_CLB_X_E	INT: mux IMUX_CLB_C bit 2	INT: mux IMUX_CLB_B bit 5	INT: mux IMUX_CLB_B bit 3	-	-	-	-	-	-	INT: !pass SINGLE_VE[3] ← OUT_IO_E_I[0]	INT: !pass SINGLE_H[2] ← OUT_IO_E_I[0]	INT: !bipass SINGLE_H[2] = LONG_VE[1]	INT: !bipass SINGLE_H[3] = LONG_VE[0]	INT: !pass SINGLE_H[3] ← OUT_IO_E_I_S1	INT: !pass SINGLE_H[1] ← OUT_IO_E_I_S1	INT: !pass SINGLE_VE[1] ← OUT_IO_E_I[0]	INT: !pass SINGLE_H[0] ← OUT_IO_E_I[0]	INT: !pass LONG_VE[1] ← OUT_IO_E_I[0]
B7	INT: !pass SINGLE_V[0] ← OUT_CLB_Y_E	INT: !pass SINGLE_V[4] ← OUT_CLB_Y_E	INT: mux IMUX_CLB_K bit 1	INT: mux IMUX_CLB_K bit 2	INT: mux IMUX_CLB_K bit 0	CLB: !invert K	INT: mux IMUX_CLB_K bit 3	INT: !pass SINGLE_V[1] ← OUT_CLB_X_E	-	INT: !pass LONG_V[0] ← OUT_CLB_X_E	INT: !pass LONG_V[1] ← OUT_CLB_Y_E	INT: !pass SINGLE_V[2] ← OUT_CLB_Y_E	INT: mux IMUX_CLB_D bit 0	INT: mux IMUX_CLB_D bit 2	INT: mux IMUX_CLB_A bit 2	INT: mux IMUX_CLB_A bit 1	INT: mux IMUX_CLB_A bit 3	INT: mux IMUX_CLB_D bit 3	INT: !pass SINGLE_VE[3] ← OUT_CLB_X	INT: !pass LONG_IO_E ← OUT_CLB_Y	INT: !pass SINGLE_VE[2] ← OUT_CLB_Y	INT: !pass LONG_VE[0] ← OUT_CLB_Y	INT: !pass SINGLE_VE[0] ← OUT_CLB_Y	INT: !pass SINGLE_VE[1] ← OUT_CLB_X	INT: !pass LONG_VE[1] ← OUT_CLB_X	INT: mux IMUX_IO_E_O[0] bit 3	IO_E[0]: ! READBACK_Q bit 0
B6	CLB: MUX_RES bit 0	CLB: MUX_RES bit 1	CLB: MUX_SET bit 1	CLB: MUX_SET bit 0	-	-	-	-	-	CLB: FF_MODE bit 0	CLB: MUX_X bit 1	CLB: MUX_X bit 0	CLB: MUX_Y bit 0	CLB: MUX_Y bit 1	CLB: ! READBACK_Q bit 0	-	-	-	-	INT: !pass LONG_IO_E ← OUT_IO_S_I[1]	INT: !pass LONG_H ← OUT_IO_E_I[0]	-	-	INT: mux IMUX_IO_E_O[0] bit 0	INT: mux IMUX_IO_E_O[0] bit 1	INT: mux IMUX_IO_E_O[0] bit 2	INT: mux IMUX_IO_E_O[0] bit 4
B5	CLB: MUX_F3 bit 0	CLB: MUX_F3 bit 1	-	-	-	-	CLB: MUX_F2 bit 0	CLB: MUX_F1 bit 0	-	-	-	CLB: MUX_G1 bit 0	CLB: MUX_G2 bit 0	-	-	-	CLB: MUX_G3 bit 1	CLB: MUX_G3 bit 0	-	-	-	INT: !pass SINGLE_VE[2] ← OUT_IO_S_I[1]	INT: !pass LONG_VE[0] ← OUT_IO_S_I[1]	INT: !pass SINGLE_VE[0] ← OUT_IO_S_I[1]	INT: mux IMUX_IO_E_T[0] bit 2	INT: mux IMUX_IO_E_T[0] bit 0	IO_E[0]: MUX_I bit 0
B4	CLB: ! F bit 1	CLB: ! F bit 0	CLB: ! F bit 2	CLB: ! F bit 3	CLB: ! F bit 5	CLB: ! F bit 4	CLB: ! F bit 6	CLB: ! F bit 7	-	CLB: MODE bit 0	CLB: ! G bit 7	CLB: ! G bit 6	CLB: ! G bit 4	CLB: ! G bit 5	CLB: ! G bit 3	CLB: ! G bit 2	CLB: ! G bit 0	CLB: ! G bit 1	-	-	-	-	-	INT: mux IMUX_IO_E_T[0] bit 1	-	-	-
B3	INT: !bipass SINGLE_HS_E[3] = SINGLE_V[0]	INT: !bipass SINGLE_HS[2] = SINGLE_HS_E[2]	INT: !bipass SINGLE_HS[2] = SINGLE_V[0]	INT: !pass SINGLE_V[0] ← OUT_IO_S_I_E1	INT: !bipass SINGLE_HS_E[2] = SINGLE_V[1]	INT: !bipass SINGLE_HS[2] = SINGLE_V[1]	INT: !pass SINGLE_V[1] ← OUT_IO_S_I[0]	INT: !bipass SINGLE_HS[2] = SINGLE_V[4]	INT: !pass LONG_HS ← OUT_IO_S_I[0]	INT: !pass SINGLE_HS[1] ← OUT_IO_S_I[0]	INT: !pass SINGLE_V[2] ← OUT_IO_S_I_E1	INT: !bipass LONG_HS = LONG_V[1]	INT: !bipass SINGLE_HS[3] = LONG_V[1]	INT: !bipass SINGLE_HS[0] = SINGLE_HS_E[1]	INT: !bipass SINGLE_HS[0] = SINGLE_HS_E[0]	INT: !bipass SINGLE_HS[0] = SINGLE_V[2]	INT: !bipass SINGLE_HS_E[0] = SINGLE_V[3]	INT: !bipass SINGLE_HS[1] = SINGLE_V[3]	INT: !bipass SINGLE_VE[3] = LONG_IO_S	INT: !bipass SINGLE_HS[3] = LONG_IO_E	INT: !bipass LONG_IO_S = LONG_IO_E	INT: !bipass SINGLE_HS[2] = SINGLE_VE[2]	INT: !bipass LONG_HS = LONG_VE[0]	INT: !bipass SINGLE_HS[0] = SINGLE_VE[0]	INT: !bipass SINGLE_HS[1] = SINGLE_VE[1]	INT: !bipass LONG_HS = LONG_VE[1]	MISC_SE: ! DONE_PULLUP
B2	INT: !bipass SINGLE_HS[2] = SINGLE_HS_E[3]	INT: !bipass SINGLE_HS_E[2] = SINGLE_V[0]	INT: !bipass SINGLE_V[0] = LONG_HS	INT: !bipass SINGLE_HS[3] = SINGLE_HS_E[3]	INT: !bipass SINGLE_HS[3] = SINGLE_HS_E[2]	INT: !bipass SINGLE_HS[3] = SINGLE_V[1]	INT: !pass SINGLE_HS[3] ← OUT_IO_S_I[0]	INT: !pass SINGLE_V[4] ← OUT_IO_S_I[0]	INT: !bipass SINGLE_HS[1] = SINGLE_V[4]	INT: !pass LONG_V[0] ← OUT_IO_S_I_E1	INT: !bipass SINGLE_HS[2] = LONG_V[0]	INT: !bipass LONG_HS = LONG_V[0]	INT: !bipass SINGLE_HS[0] = LONG_V[0]	INT: !bipass SINGLE_HS_E[1] = SINGLE_V[2]	INT: !bipass SINGLE_HS_E[0] = SINGLE_V[2]	INT: !bipass SINGLE_HS[1] = SINGLE_HS_E[1]	INT: !bipass SINGLE_HS[1] = SINGLE_HS_E[0]	INT: !bipass SINGLE_HS[0] = SINGLE_V[3]	INT: !bipass SINGLE_HS[3] = SINGLE_VE[3]	INT: mux IMUX_BUFG bit 3	INT: mux IMUX_BUFG bit 5	INT: mux IMUX_BUFG bit 2	INT: mux IMUX_BUFG bit 4	INT: mux IMUX_BUFG bit 6	INT: mux IMUX_BUFG bit 7	MISC_SE: ! REPROGRAM_ENABLE	MISC_SE: ! TLC
B1	-	INT: mux IMUX_IO_S_O[0] bit 1	INT: mux IMUX_IO_S_O[0] bit 2	-	-	-	INT: !pass LONG_V[1] ← OUT_IO_S_I[0]	INT: !pass SINGLE_V[3] ← OUT_IO_S_I[0]	INT: !pass LONG_V[1] ← ACLK	INT: !bipass LONG_IO_S = LONG_V[0]	INT: !pass SINGLE_HS[2] ← OUT_IO_S_I[1]	INT: mux IMUX_CLB_D_N bit 3	INT: mux IMUX_CLB_D_N bit 1	IO_S[0]: ! READBACK_Q bit 0	INT: !pass SINGLE_HS[0] ← OUT_IO_S_I[1]	INT: !pass LONG_IO_S ← OUT_IO_S_I[1]	INT: mux IMUX_IO_S_O[1] bit 3	INT: !bipass SINGLE_V[3] = LONG_HS	INT: mux IMUX_IO_S_O[1] bit 5	-	-	-	-	-	-	-	-
B0	INT: mux IMUX_IO_S_O[0] bit 0	INT: mux IMUX_IO_S_O[0] bit 3	INT: mux IMUX_IO_S_T[0] bit 2	INT: mux IMUX_IO_S_T[0] bit 0	IO_S[0]: MUX_I bit 0	INT: mux IMUX_IO_S_T[0] bit 1	INT: mux IMUX_IO_S_T[1] bit 1	INT: mux IMUX_IO_S_T[1] bit 2	INT: mux IMUX_IO_S_T[1] bit 0	IO_S[1]: ! READBACK_Q bit 0	IO_S[1]: MUX_I bit 0	INT: mux IMUX_CLB_D_N bit 0	INT: mux IMUX_CLB_D_N bit 4	INT: mux IMUX_CLB_D_N bit 2	INT: !bipass SINGLE_HS[1] = LONG_V[1]	INT: mux IMUX_IO_S_O[1] bit 4	INT: mux IMUX_IO_S_O[1] bit 2	INT: mux IMUX_IO_S_O[1] bit 1	INT: mux IMUX_IO_S_O[1] bit 0	INT: mux IMUX_BUFG bit 1	INT: mux IMUX_BUFG bit 0	-	-	-	-	-	-

Tile CLB_N

Cells: 2

Switchbox INT

xc2000 CLB_N switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_HN[0]	CELL.OUT_IO_N_I[0]	!MAIN[11][6]
CELL.SINGLE_HN[1]	CELL.OUT_IO_N_I[1]	!MAIN[7][7]
CELL.SINGLE_HN[2]	CELL.OUT_IO_N_I[0]	!MAIN[8][5]
CELL.SINGLE_HN[3]	CELL.OUT_IO_N_I[1]	!MAIN[3][7]
CELL.SINGLE_V[0]	CELL.OUT_CLB_Y_E	!MAIN[17][3]
CELL.SINGLE_V[0]	CELL.OUT_IO_N_I_E1	!MAIN[14][5]
CELL.SINGLE_V[1]	CELL.OUT_CLB_X_E	!MAIN[10][3]
CELL.SINGLE_V[1]	CELL.OUT_IO_N_I[0]	!MAIN[11][5]
CELL.SINGLE_V[2]	CELL.OUT_CLB_Y_E	!MAIN[6][3]
CELL.SINGLE_V[2]	CELL.OUT_IO_N_I_E1	!MAIN[7][5]
CELL.SINGLE_V[3]	CELL.OUT_CLB_X_E	!MAIN[12][4]
CELL.SINGLE_V[3]	CELL.OUT_IO_N_I[0]	!MAIN[10][7]
CELL.SINGLE_V[4]	CELL.OUT_CLB_Y_E	!MAIN[16][3]
CELL.SINGLE_V[4]	CELL.OUT_IO_N_I[0]	!MAIN[10][6]
CELL.LONG_H	CELL.OUT_IO_N_I[0]	!MAIN[9][5]
CELL.LONG_IO_N	CELL.OUT_IO_N_I[1]	!MAIN[2][7]
CELL.LONG_V[0]	CELL.OUT_CLB_X_E	!MAIN[8][3]
CELL.LONG_V[0]	CELL.OUT_IO_N_I_E1	!MAIN[8][6]
CELL.LONG_V[1]	CELL.OUT_CLB_Y_E	!MAIN[7][3]
CELL.LONG_V[1]	CELL.OUT_IO_N_I[0]	!MAIN[11][7]

xc2000 CLB_N switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_HN[0]	CELL.SINGLE_HN_E[0]	!MAIN[14][6]
CELL.SINGLE_HN[0]	CELL.SINGLE_HN_E[1]	!MAIN[13][6]
CELL.SINGLE_HN[0]	CELL.SINGLE_V[1]	!MAIN[12][6]
CELL.SINGLE_HN[0]	CELL.LONG_V[1]	!MAIN[5][5]
CELL.SINGLE_HN[1]	CELL.SINGLE_HN_E[0]	!MAIN[17][6]
CELL.SINGLE_HN[1]	CELL.SINGLE_HN_E[1]	!MAIN[16][5]
CELL.SINGLE_HN[1]	CELL.SINGLE_V[0]	!MAIN[15][5]
CELL.SINGLE_HN[1]	CELL.SINGLE_V[1]	!MAIN[12][5]
CELL.SINGLE_HN[1]	CELL.SINGLE_V[4]	!MAIN[10][5]
CELL.SINGLE_HN[1]	CELL.LONG_V[0]	!MAIN[7][6]
CELL.SINGLE_HN[2]	CELL.SINGLE_HN_E[2]	!MAIN[2][6]
CELL.SINGLE_HN[2]	CELL.SINGLE_HN_E[3]	!MAIN[1][6]
CELL.SINGLE_HN[2]	CELL.SINGLE_V[3]	!MAIN[0][5]
CELL.SINGLE_HN[2]	CELL.SINGLE_V[4]	!MAIN[9][6]
CELL.SINGLE_HN[2]	CELL.LONG_V[1]	!MAIN[3][8]
CELL.SINGLE_HN[3]	CELL.SINGLE_HN_E[2]	!MAIN[4][5]
CELL.SINGLE_HN[3]	CELL.SINGLE_HN_E[3]	!MAIN[3][5]
CELL.SINGLE_HN[3]	CELL.SINGLE_V[2]	!MAIN[2][5]
CELL.SINGLE_HN[3]	CELL.SINGLE_V[3]	!MAIN[0][6]
CELL.SINGLE_HN[3]	CELL.LONG_V[0]	!MAIN[5][6]
CELL.SINGLE_HN_E[0]	CELL.SINGLE_V[0]	!MAIN[17][5]
CELL.SINGLE_HN_E[1]	CELL.SINGLE_V[0]	!MAIN[16][6]
CELL.SINGLE_HN_E[1]	CELL.SINGLE_V[1]	!MAIN[13][5]
CELL.SINGLE_HN_E[2]	CELL.SINGLE_V[2]	!MAIN[4][6]
CELL.SINGLE_HN_E[3]	CELL.SINGLE_V[2]	!MAIN[3][6]
CELL.SINGLE_HN_E[3]	CELL.SINGLE_V[3]	!MAIN[1][5]
CELL.SINGLE_V[0]	CELL.LONG_H	!MAIN[15][6]
CELL.SINGLE_V[3]	CELL.LONG_H	!MAIN[0][7]
CELL.LONG_H	CELL.LONG_V[0]	!MAIN[6][6]
CELL.LONG_H	CELL.LONG_V[1]	!MAIN[6][5]
CELL.LONG_IO_N	CELL.LONG_V[0]	!MAIN[8][7]

xc2000 CLB_N switchbox INT muxes IMUX_CLB_A
Bits					Destination
MAIN[5][8]	MAIN[5][7]	MAIN[4][8]	MAIN[6][8]	MAIN[6][7]	CELL.IMUX_CLB_A
					Source
0	0	0	1	1	CELL.SINGLE_HN[2]
0	0	1	1	1	CELL.SINGLE_HN[0]
0	1	0	0	1	CELL.SINGLE_HN[1]
0	1	1	0	1	CELL.LONG_H
0	1	1	1	0	CELL.SINGLE_HN[3]
1	1	0	1	1	CELL.LONG_IO_N
1	1	1	1	1	CELL.OUT_IO_N_I[0]

xc2000 CLB_N switchbox INT muxes IMUX_CLB_B
Bits						Destination
MAIN[0][3]	MAIN[5][3]	MAIN[14][4]	MAIN[4][3]	MAIN[2][3]	MAIN[15][4]	CELL.IMUX_CLB_B
						Source
0	0	0	1	1	1	CELL.SINGLE_V[0]
0	0	1	0	1	1	CELL.SINGLE_V[1]
0	0	1	1	0	1	CELL.SINGLE_V[2]
0	0	1	1	1	0	CELL.OUT_CLB_Y_E
0	1	0	1	1	1	CELL.LONG_V[0]
0	1	1	0	1	1	CELL.LONG_V[1]
0	1	1	1	0	1	CELL.GCLK
0	1	1	1	1	0	CELL.SINGLE_V[4]
1	0	1	1	1	1	CELL.OUT_IO_N_I[0]
1	1	1	1	1	1	CELL.SINGLE_V[3]

xc2000 CLB_N switchbox INT muxes IMUX_CLB_C
Bits					Destination
MAIN[1][3]	MAIN[17][4]	MAIN[16][4]	MAIN[3][3]	MAIN[13][4]	CELL.IMUX_CLB_C
					Source
0	0	1	1	0	CELL.SINGLE_V[4]
0	0	1	1	1	CELL.SINGLE_V[0]
0	1	0	1	0	CELL.LONG_V[0]
0	1	0	1	1	CELL.SINGLE_V[1]
0	1	1	0	0	CELL.LONG_V[1]
0	1	1	0	1	CELL.SINGLE_V[2]
1	1	1	1	0	CELL.SINGLE_V[3]
1	1	1	1	1	CELL.OUT_CLB_X_N

xc2000 CLB_N switchbox INT muxes IMUX_CLB_K
Bits				Destination
MAIN[11][3]	MAIN[14][3]	MAIN[15][3]	MAIN[13][3]	CELL.IMUX_CLB_K
				Source
0	0	1	1	CELL.LONG_V[1]
0	1	0	1	CELL.GCLK
0	1	1	0	CELL.SPECIAL_CLB_C
0	1	1	1	~CELL.SPECIAL_CLB_G
1	1	1	1	off

xc2000 CLB_N switchbox INT muxes IMUX_IO_N_O[0]
Bits				Destination
MAIN[15][7]	MAIN[16][7]	MAIN[16][8]	MAIN[17][8]	CELL.IMUX_IO_N_O[0]
				Source
0	0	0	1	CELL.LONG_V[0]
0	0	1	1	CELL.SINGLE_HN[1]
0	1	0	0	CELL.LONG_IO_N
0	1	1	0	CELL.SINGLE_V[2]
1	1	0	1	CELL.SINGLE_HN[3]
1	1	1	1	CELL.SINGLE_V[0]

xc2000 CLB_N switchbox INT muxes IMUX_IO_N_O[1]
Bits					Destination
MAIN_E[17][7]	MAIN[1][8]	MAIN[1][7]	MAIN[2][8]	MAIN[0][8]	CELL.IMUX_IO_N_O[1]
					Source
0	0	1	0	1	CELL.OUT_CLB_X
0	0	1	1	1	CELL.SINGLE_HN[0]
0	1	0	0	1	CELL.SINGLE_HN[2]
0	1	0	1	1	CELL.LONG_H
0	1	1	0	0	E.SINGLE_V[3]
0	1	1	1	0	E.SINGLE_V[4]
1	1	1	0	1	E.SINGLE_V[1]
1	1	1	1	1	E.LONG_V[1]

xc2000 CLB_N switchbox INT muxes IMUX_IO_N_T[0]
Bits			Destination
MAIN[15][8]	MAIN[12][8]	MAIN[14][8]	CELL.IMUX_IO_N_T[0]
			Source
0	0	1	CELL.SINGLE_HN[0]
0	1	0	CELL.TIE_1
0	1	1	CELL.LONG_H
1	0	1	CELL.LONG_IO_N
1	1	0	CELL.TIE_0
1	1	1	CELL.SINGLE_HN[2]

xc2000 CLB_N switchbox INT muxes IMUX_IO_N_T[1]
Bits			Destination
MAIN[10][8]	MAIN[11][8]	MAIN[9][8]	CELL.IMUX_IO_N_T[1]
			Source
0	0	1	CELL.SINGLE_HN[0]
0	1	0	CELL.TIE_0
0	1	1	CELL.LONG_H
1	0	1	CELL.LONG_IO_N
1	1	0	CELL.TIE_1
1	1	1	CELL.SINGLE_HN[2]

Bels CLB

xc2000 CLB_N bel CLB pins
Pin	Direction	CLB
A	in	CELL.IMUX_CLB_A
B	in	CELL.IMUX_CLB_B
C	in	CELL.IMUX_CLB_C
D	in	CELL.IMUX_CLB_D_N
K	in	CELL.IMUX_CLB_K invert by !MAIN[12][3]
X	out	CELL.OUT_CLB_X
Y	out	CELL.OUT_CLB_Y

xc2000 CLB_N bel CLB attribute bits
Attribute	CLB
F bit 0	!MAIN[16][0]
F bit 1	!MAIN[17][0]
F bit 2	!MAIN[15][0]
F bit 3	!MAIN[14][0]
F bit 4	!MAIN[12][0]
F bit 5	!MAIN[13][0]
F bit 6	!MAIN[11][0]
F bit 7	!MAIN[10][0]
G bit 0	!MAIN[1][0]
G bit 1	!MAIN[0][0]
G bit 2	!MAIN[2][0]
G bit 3	!MAIN[3][0]
G bit 4	!MAIN[5][0]
G bit 5	!MAIN[4][0]
G bit 6	!MAIN[6][0]
G bit 7	!MAIN[7][0]
MODE	[enum: CLB_MODE]
FF_MODE	[enum: FF_MODE]
MUX_F1	[enum: CLB_MUX_I1]
MUX_G1	[enum: CLB_MUX_I1]
MUX_F2	[enum: CLB_MUX_I2]
MUX_G2	[enum: CLB_MUX_I2]
MUX_F3	[enum: CLB_MUX_I3]
MUX_G3	[enum: CLB_MUX_I3]
MUX_X	[enum: CLB_MUX_XY]
MUX_Y	[enum: CLB_MUX_XY]
MUX_RES	[enum: CLB_MUX_RES]
MUX_SET	[enum: CLB_MUX_SET]
READBACK_Q bit 0	!MAIN[3][2]

xc2000 CLB_N enum CLB_MODE
CLB.MODE	MAIN[8][0]
FGM	1
FG	0

xc2000 CLB_N enum FF_MODE
CLB.FF_MODE	MAIN[8][2]
FF	1
LATCH	0

xc2000 CLB_N enum CLB_MUX_I1
CLB.MUX_F1	MAIN[10][1]
CLB.MUX_G1	MAIN[6][1]
A	0
B	1

xc2000 CLB_N enum CLB_MUX_I2
CLB.MUX_F2	MAIN[11][1]
CLB.MUX_G2	MAIN[5][1]
B	0
C	1

xc2000 CLB_N enum CLB_MUX_I3
CLB.MUX_F3	MAIN[16][1]	MAIN[17][1]
CLB.MUX_G3	MAIN[1][1]	MAIN[0][1]
C	0	1
D	1	0
Q	1	1

xc2000 CLB_N enum CLB_MUX_XY
CLB.MUX_X	MAIN[7][2]	MAIN[6][2]
CLB.MUX_Y	MAIN[4][2]	MAIN[5][2]
F	0	1
G	1	0
Q	1	1

xc2000 CLB_N enum CLB_MUX_RES
CLB.MUX_RES	MAIN[16][2]	MAIN[17][2]
D	0	1
G	0	0
TIE_0	1	1

xc2000 CLB_N enum CLB_MUX_SET
CLB.MUX_SET	MAIN[15][2]	MAIN[14][2]
A	1	1
F	1	0
TIE_0	0	1

Bels IO

xc2000 CLB_N bel IO pins
Pin	Direction	IO_N[0]	IO_N[1]
O	in	CELL.IMUX_IO_N_O[0]	CELL.IMUX_IO_N_O[1]
T	in	CELL.IMUX_IO_N_T[0]	CELL.IMUX_IO_N_T[1]
K	in	CELL.IOCLK_N	CELL.IOCLK_N
I	out	CELL.OUT_IO_N_I[0]	CELL.OUT_IO_N_I[1]

xc2000 CLB_N bel IO attribute bits
Attribute	IO_N[0]	IO_N[1]
MUX_I	[enum: IO_MUX_I]	[enum: IO_MUX_I]
READBACK_Q bit 0	!MAIN[4][7]	!MAIN[8][8]

xc2000 CLB_N enum IO_MUX_I
IO_N[0].MUX_I	MAIN[13][8]
IO_N[1].MUX_I	MAIN[7][8]
PAD	0
Q	1

Bel wires

xc2000 CLB_N bel wires
Wire	Pins
CELL.IOCLK_N	IO_N[0].K, IO_N[1].K
CELL.IMUX_CLB_A	CLB.A
CELL.IMUX_CLB_B	CLB.B
CELL.IMUX_CLB_C	CLB.C
CELL.IMUX_CLB_D_N	CLB.D
CELL.IMUX_CLB_K	CLB.K
CELL.IMUX_IO_N_O[0]	IO_N[0].O
CELL.IMUX_IO_N_O[1]	IO_N[1].O
CELL.IMUX_IO_N_T[0]	IO_N[0].T
CELL.IMUX_IO_N_T[1]	IO_N[1].T
CELL.OUT_CLB_X	CLB.X
CELL.OUT_CLB_Y	CLB.Y
CELL.OUT_IO_N_I[0]	IO_N[0].I
CELL.OUT_IO_N_I[1]	IO_N[1].I

Bitstream

xc2000 CLB_N rect MAIN
Bit	Frame
Bit	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B8	INT: mux CELL.IMUX_IO_N_O[0] bit 0	INT: mux CELL.IMUX_IO_N_O[0] bit 1	INT: mux CELL.IMUX_IO_N_T[0] bit 2	INT: mux CELL.IMUX_IO_N_T[0] bit 0	IO_N[0]: MUX_I bit 0	INT: mux CELL.IMUX_IO_N_T[0] bit 1	INT: mux CELL.IMUX_IO_N_T[1] bit 1	INT: mux CELL.IMUX_IO_N_T[1] bit 2	INT: mux CELL.IMUX_IO_N_T[1] bit 0	IO_N[1]: ! READBACK_Q bit 0	IO_N[1]: MUX_I bit 0	INT: mux CELL.IMUX_CLB_A bit 1	INT: mux CELL.IMUX_CLB_A bit 4	INT: mux CELL.IMUX_CLB_A bit 2	INT: !bipass CELL.SINGLE_HN[2] = CELL.LONG_V[1]	INT: mux CELL.IMUX_IO_N_O[1] bit 1	INT: mux CELL.IMUX_IO_N_O[1] bit 3	INT: mux CELL.IMUX_IO_N_O[1] bit 0
B7	-	INT: mux CELL.IMUX_IO_N_O[0] bit 2	INT: mux CELL.IMUX_IO_N_O[0] bit 3	-	-	-	INT: !pass CELL.LONG_V[1] ← CELL.OUT_IO_N_I[0]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_N_I[0]	-	INT: !bipass CELL.LONG_IO_N = CELL.LONG_V[0]	INT: !pass CELL.SINGLE_HN[1] ← CELL.OUT_IO_N_I[1]	INT: mux CELL.IMUX_CLB_A bit 0	INT: mux CELL.IMUX_CLB_A bit 3	IO_N[0]: ! READBACK_Q bit 0	INT: !pass CELL.SINGLE_HN[3] ← CELL.OUT_IO_N_I[1]	INT: !pass CELL.LONG_IO_N ← CELL.OUT_IO_N_I[1]	INT: mux CELL.IMUX_IO_N_O[1] bit 2	INT: !bipass CELL.SINGLE_V[3] = CELL.LONG_H
B6	INT: !bipass CELL.SINGLE_HN[1] = CELL.SINGLE_HN_E[0]	INT: !bipass CELL.SINGLE_HN_E[1] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.LONG_H	INT: !bipass CELL.SINGLE_HN[0] = CELL.SINGLE_HN_E[0]	INT: !bipass CELL.SINGLE_HN[0] = CELL.SINGLE_HN_E[1]	INT: !bipass CELL.SINGLE_HN[0] = CELL.SINGLE_V[1]	INT: !pass CELL.SINGLE_HN[0] ← CELL.OUT_IO_N_I[0]	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_N_I[0]	INT: !bipass CELL.SINGLE_HN[2] = CELL.SINGLE_V[4]	INT: !pass CELL.LONG_V[0] ← CELL.OUT_IO_N_I_E1	INT: !bipass CELL.SINGLE_HN[1] = CELL.LONG_V[0]	INT: !bipass CELL.LONG_H = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_HN[3] = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_HN_E[2] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_HN_E[3] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_HN[2] = CELL.SINGLE_HN_E[2]	INT: !bipass CELL.SINGLE_HN[2] = CELL.SINGLE_HN_E[3]	INT: !bipass CELL.SINGLE_HN[3] = CELL.SINGLE_V[3]
B5	INT: !bipass CELL.SINGLE_HN_E[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_HN[1] = CELL.SINGLE_HN_E[1]	INT: !bipass CELL.SINGLE_HN[1] = CELL.SINGLE_V[0]	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_N_I_E1	INT: !bipass CELL.SINGLE_HN_E[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_HN[1] = CELL.SINGLE_V[1]	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_N_I[0]	INT: !bipass CELL.SINGLE_HN[1] = CELL.SINGLE_V[4]	INT: !pass CELL.LONG_H ← CELL.OUT_IO_N_I[0]	INT: !pass CELL.SINGLE_HN[2] ← CELL.OUT_IO_N_I[0]	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_N_I_E1	INT: !bipass CELL.LONG_H = CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_HN[0] = CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_HN[3] = CELL.SINGLE_HN_E[2]	INT: !bipass CELL.SINGLE_HN[3] = CELL.SINGLE_HN_E[3]	INT: !bipass CELL.SINGLE_HN[3] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_HN_E[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_HN[2] = CELL.SINGLE_V[3]
B4	INT: mux CELL.IMUX_CLB_C bit 3	INT: mux CELL.IMUX_CLB_C bit 2	INT: mux CELL.IMUX_CLB_B bit 0	INT: mux CELL.IMUX_CLB_B bit 3	INT: mux CELL.IMUX_CLB_C bit 0	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_X_E	-	-	-	-	-	-	-	-	-	-	-	-
B3	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_Y_E	INT: mux CELL.IMUX_CLB_K bit 1	INT: mux CELL.IMUX_CLB_K bit 2	INT: mux CELL.IMUX_CLB_K bit 0	CLB: !invert K	INT: mux CELL.IMUX_CLB_K bit 3	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X_E	-	INT: !pass CELL.LONG_V[0] ← CELL.OUT_CLB_X_E	INT: !pass CELL.LONG_V[1] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E	INT: mux CELL.IMUX_CLB_B bit 4	INT: mux CELL.IMUX_CLB_B bit 2	INT: mux CELL.IMUX_CLB_C bit 1	INT: mux CELL.IMUX_CLB_B bit 1	INT: mux CELL.IMUX_CLB_C bit 4	INT: mux CELL.IMUX_CLB_B bit 5
B2	CLB: MUX_RES bit 0	CLB: MUX_RES bit 1	CLB: MUX_SET bit 1	CLB: MUX_SET bit 0	-	-	-	-	-	CLB: FF_MODE bit 0	CLB: MUX_X bit 1	CLB: MUX_X bit 0	CLB: MUX_Y bit 0	CLB: MUX_Y bit 1	CLB: ! READBACK_Q bit 0	-	-	-
B1	CLB: MUX_F3 bit 0	CLB: MUX_F3 bit 1	-	-	-	-	CLB: MUX_F2 bit 0	CLB: MUX_F1 bit 0	-	-	-	CLB: MUX_G1 bit 0	CLB: MUX_G2 bit 0	-	-	-	CLB: MUX_G3 bit 1	CLB: MUX_G3 bit 0
B0	CLB: ! F bit 1	CLB: ! F bit 0	CLB: ! F bit 2	CLB: ! F bit 3	CLB: ! F bit 5	CLB: ! F bit 4	CLB: ! F bit 6	CLB: ! F bit 7	-	CLB: MODE bit 0	CLB: ! G bit 7	CLB: ! G bit 6	CLB: ! G bit 4	CLB: ! G bit 5	CLB: ! G bit 3	CLB: ! G bit 2	CLB: ! G bit 0	CLB: ! G bit 1

xc2000 CLB_N rect MAIN_E
Bit	Frame
Bit	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	INT: mux CELL.IMUX_IO_N_O[1] bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile CLB_NE1

Cells: 2

Switchbox INT

xc2000 CLB_NE1 switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_HN[0]	CELL.OUT_IO_N_I[0]	!MAIN[11][6]
CELL.SINGLE_HN[1]	CELL.OUT_IO_N_I[1]	!MAIN[7][7]
CELL.SINGLE_HN[2]	CELL.OUT_IO_N_I[0]	!MAIN[8][5]
CELL.SINGLE_HN[3]	CELL.OUT_IO_N_I[1]	!MAIN[3][7]
CELL.SINGLE_V[0]	CELL.OUT_CLB_Y_E	!MAIN[17][3]
CELL.SINGLE_V[0]	CELL.OUT_IO_N_I_E1	!MAIN[14][5]
CELL.SINGLE_V[1]	CELL.OUT_CLB_X_E	!MAIN[10][3]
CELL.SINGLE_V[1]	CELL.OUT_IO_N_I[0]	!MAIN[11][5]
CELL.SINGLE_V[2]	CELL.OUT_CLB_Y_E	!MAIN[6][3]
CELL.SINGLE_V[2]	CELL.OUT_IO_N_I_E1	!MAIN[7][5]
CELL.SINGLE_V[3]	CELL.OUT_CLB_X_E	!MAIN[12][4]
CELL.SINGLE_V[3]	CELL.OUT_IO_N_I[0]	!MAIN[10][7]
CELL.SINGLE_V[4]	CELL.OUT_CLB_Y_E	!MAIN[16][3]
CELL.SINGLE_V[4]	CELL.OUT_IO_N_I[0]	!MAIN[10][6]
CELL.LONG_H	CELL.OUT_IO_N_I[0]	!MAIN[9][5]
CELL.LONG_IO_N	CELL.OUT_IO_N_I[1]	!MAIN[2][7]
CELL.LONG_V[0]	CELL.OUT_CLB_X_E	!MAIN[8][3]
CELL.LONG_V[0]	CELL.OUT_IO_N_I_E1	!MAIN[8][6]
CELL.LONG_V[1]	CELL.OUT_CLB_Y_E	!MAIN[7][3]
CELL.LONG_V[1]	CELL.OUT_IO_N_I[0]	!MAIN[11][7]

xc2000 CLB_NE1 switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_HN[0]	CELL.SINGLE_HN_E[0]	!MAIN[14][6]
CELL.SINGLE_HN[0]	CELL.SINGLE_HN_E[1]	!MAIN[13][6]
CELL.SINGLE_HN[0]	CELL.SINGLE_V[1]	!MAIN[12][6]
CELL.SINGLE_HN[0]	CELL.LONG_V[1]	!MAIN[5][5]
CELL.SINGLE_HN[1]	CELL.SINGLE_HN_E[0]	!MAIN[17][6]
CELL.SINGLE_HN[1]	CELL.SINGLE_HN_E[1]	!MAIN[16][5]
CELL.SINGLE_HN[1]	CELL.SINGLE_V[0]	!MAIN[15][5]
CELL.SINGLE_HN[1]	CELL.SINGLE_V[1]	!MAIN[12][5]
CELL.SINGLE_HN[1]	CELL.SINGLE_V[4]	!MAIN[10][5]
CELL.SINGLE_HN[1]	CELL.LONG_V[0]	!MAIN[7][6]
CELL.SINGLE_HN[2]	CELL.SINGLE_HN_E[2]	!MAIN[2][6]
CELL.SINGLE_HN[2]	CELL.SINGLE_HN_E[3]	!MAIN[1][6]
CELL.SINGLE_HN[2]	CELL.SINGLE_V[3]	!MAIN[0][5]
CELL.SINGLE_HN[2]	CELL.SINGLE_V[4]	!MAIN[9][6]
CELL.SINGLE_HN[2]	CELL.LONG_V[1]	!MAIN[3][8]
CELL.SINGLE_HN[3]	CELL.SINGLE_HN_E[2]	!MAIN[4][5]
CELL.SINGLE_HN[3]	CELL.SINGLE_HN_E[3]	!MAIN[3][5]
CELL.SINGLE_HN[3]	CELL.SINGLE_V[2]	!MAIN[2][5]
CELL.SINGLE_HN[3]	CELL.SINGLE_V[3]	!MAIN[0][6]
CELL.SINGLE_HN[3]	CELL.LONG_V[0]	!MAIN[5][6]
CELL.SINGLE_HN_E[0]	CELL.SINGLE_V[0]	!MAIN[17][5]
CELL.SINGLE_HN_E[1]	CELL.SINGLE_V[0]	!MAIN[16][6]
CELL.SINGLE_HN_E[1]	CELL.SINGLE_V[1]	!MAIN[13][5]
CELL.SINGLE_HN_E[2]	CELL.SINGLE_V[2]	!MAIN[4][6]
CELL.SINGLE_HN_E[3]	CELL.SINGLE_V[2]	!MAIN[3][6]
CELL.SINGLE_HN_E[3]	CELL.SINGLE_V[3]	!MAIN[1][5]
CELL.SINGLE_V[0]	CELL.LONG_H	!MAIN[15][6]
CELL.SINGLE_V[3]	CELL.LONG_H	!MAIN[0][7]
CELL.LONG_H	CELL.LONG_V[0]	!MAIN[6][6]
CELL.LONG_H	CELL.LONG_V[1]	!MAIN[6][5]
CELL.LONG_IO_N	CELL.LONG_V[0]	!MAIN[8][7]

xc2000 CLB_NE1 switchbox INT muxes IMUX_CLB_A
Bits					Destination
MAIN[5][8]	MAIN[5][7]	MAIN[4][8]	MAIN[6][8]	MAIN[6][7]	CELL.IMUX_CLB_A
					Source
0	0	0	1	1	CELL.SINGLE_HN[2]
0	0	1	1	1	CELL.SINGLE_HN[0]
0	1	0	0	1	CELL.SINGLE_HN[1]
0	1	1	0	1	CELL.LONG_H
0	1	1	1	0	CELL.SINGLE_HN[3]
1	1	0	1	1	CELL.LONG_IO_N
1	1	1	1	1	CELL.OUT_IO_N_I[0]

xc2000 CLB_NE1 switchbox INT muxes IMUX_CLB_B
Bits						Destination
MAIN[0][3]	MAIN[5][3]	MAIN[14][4]	MAIN[4][3]	MAIN[2][3]	MAIN[15][4]	CELL.IMUX_CLB_B
						Source
0	0	0	1	1	1	CELL.SINGLE_V[0]
0	0	1	0	1	1	CELL.SINGLE_V[1]
0	0	1	1	0	1	CELL.SINGLE_V[2]
0	0	1	1	1	0	CELL.OUT_CLB_Y_E
0	1	0	1	1	1	CELL.LONG_V[0]
0	1	1	0	1	1	CELL.LONG_V[1]
0	1	1	1	0	1	CELL.GCLK
0	1	1	1	1	0	CELL.SINGLE_V[4]
1	0	1	1	1	1	CELL.OUT_IO_N_I[0]
1	1	1	1	1	1	CELL.SINGLE_V[3]

xc2000 CLB_NE1 switchbox INT muxes IMUX_CLB_C
Bits					Destination
MAIN[1][3]	MAIN[17][4]	MAIN[16][4]	MAIN[3][3]	MAIN[13][4]	CELL.IMUX_CLB_C
					Source
0	0	1	1	0	CELL.SINGLE_V[4]
0	0	1	1	1	CELL.SINGLE_V[0]
0	1	0	1	0	CELL.LONG_V[0]
0	1	0	1	1	CELL.SINGLE_V[1]
0	1	1	0	0	CELL.LONG_V[1]
0	1	1	0	1	CELL.SINGLE_V[2]
1	1	1	1	0	CELL.SINGLE_V[3]
1	1	1	1	1	CELL.OUT_CLB_X_N

xc2000 CLB_NE1 switchbox INT muxes IMUX_CLB_K
Bits				Destination
MAIN[11][3]	MAIN[14][3]	MAIN[15][3]	MAIN[13][3]	CELL.IMUX_CLB_K
				Source
0	0	1	1	CELL.LONG_V[1]
0	1	0	1	CELL.GCLK
0	1	1	0	CELL.SPECIAL_CLB_C
0	1	1	1	~CELL.SPECIAL_CLB_G
1	1	1	1	off

xc2000 CLB_NE1 switchbox INT muxes IMUX_IO_N_O[0]
Bits				Destination
MAIN[15][7]	MAIN[16][7]	MAIN[16][8]	MAIN[17][8]	CELL.IMUX_IO_N_O[0]
				Source
0	0	0	1	CELL.LONG_V[0]
0	0	1	1	CELL.SINGLE_HN[1]
0	1	0	0	CELL.LONG_IO_N
0	1	1	0	CELL.SINGLE_V[2]
1	1	0	1	CELL.SINGLE_HN[3]
1	1	1	1	CELL.SINGLE_V[0]

xc2000 CLB_NE1 switchbox INT muxes IMUX_IO_N_O[1]
Bits					Destination
MAIN_E[26][7]	MAIN[1][8]	MAIN[1][7]	MAIN[2][8]	MAIN[0][8]	CELL.IMUX_IO_N_O[1]
					Source
0	0	1	0	1	CELL.OUT_CLB_X
0	0	1	1	1	CELL.SINGLE_HN[0]
0	1	0	0	1	CELL.SINGLE_HN[2]
0	1	0	1	1	CELL.LONG_H
0	1	1	0	0	E.SINGLE_V[3]
0	1	1	1	0	E.SINGLE_V[4]
1	1	1	0	1	E.SINGLE_V[1]
1	1	1	1	1	E.LONG_V[1]

xc2000 CLB_NE1 switchbox INT muxes IMUX_IO_N_T[0]
Bits			Destination
MAIN[15][8]	MAIN[12][8]	MAIN[14][8]	CELL.IMUX_IO_N_T[0]
			Source
0	0	1	CELL.SINGLE_HN[0]
0	1	0	CELL.TIE_1
0	1	1	CELL.LONG_H
1	0	1	CELL.LONG_IO_N
1	1	0	CELL.TIE_0
1	1	1	CELL.SINGLE_HN[2]

xc2000 CLB_NE1 switchbox INT muxes IMUX_IO_N_T[1]
Bits			Destination
MAIN[10][8]	MAIN[11][8]	MAIN[9][8]	CELL.IMUX_IO_N_T[1]
			Source
0	0	1	CELL.SINGLE_HN[0]
0	1	0	CELL.TIE_0
0	1	1	CELL.LONG_H
1	0	1	CELL.LONG_IO_N
1	1	0	CELL.TIE_1
1	1	1	CELL.SINGLE_HN[2]

Bels CLB

xc2000 CLB_NE1 bel CLB pins
Pin	Direction	CLB
A	in	CELL.IMUX_CLB_A
B	in	CELL.IMUX_CLB_B
C	in	CELL.IMUX_CLB_C
D	in	CELL.IMUX_CLB_D_N
K	in	CELL.IMUX_CLB_K invert by !MAIN[12][3]
X	out	CELL.OUT_CLB_X
Y	out	CELL.OUT_CLB_Y

xc2000 CLB_NE1 bel CLB attribute bits
Attribute	CLB
F bit 0	!MAIN[16][0]
F bit 1	!MAIN[17][0]
F bit 2	!MAIN[15][0]
F bit 3	!MAIN[14][0]
F bit 4	!MAIN[12][0]
F bit 5	!MAIN[13][0]
F bit 6	!MAIN[11][0]
F bit 7	!MAIN[10][0]
G bit 0	!MAIN[1][0]
G bit 1	!MAIN[0][0]
G bit 2	!MAIN[2][0]
G bit 3	!MAIN[3][0]
G bit 4	!MAIN[5][0]
G bit 5	!MAIN[4][0]
G bit 6	!MAIN[6][0]
G bit 7	!MAIN[7][0]
MODE	[enum: CLB_MODE]
FF_MODE	[enum: FF_MODE]
MUX_F1	[enum: CLB_MUX_I1]
MUX_G1	[enum: CLB_MUX_I1]
MUX_F2	[enum: CLB_MUX_I2]
MUX_G2	[enum: CLB_MUX_I2]
MUX_F3	[enum: CLB_MUX_I3]
MUX_G3	[enum: CLB_MUX_I3]
MUX_X	[enum: CLB_MUX_XY]
MUX_Y	[enum: CLB_MUX_XY]
MUX_RES	[enum: CLB_MUX_RES]
MUX_SET	[enum: CLB_MUX_SET]
READBACK_Q bit 0	!MAIN[3][2]

xc2000 CLB_NE1 enum CLB_MODE
CLB.MODE	MAIN[8][0]
FGM	1
FG	0

xc2000 CLB_NE1 enum FF_MODE
CLB.FF_MODE	MAIN[8][2]
FF	1
LATCH	0

xc2000 CLB_NE1 enum CLB_MUX_I1
CLB.MUX_F1	MAIN[10][1]
CLB.MUX_G1	MAIN[6][1]
A	0
B	1

xc2000 CLB_NE1 enum CLB_MUX_I2
CLB.MUX_F2	MAIN[11][1]
CLB.MUX_G2	MAIN[5][1]
B	0
C	1

xc2000 CLB_NE1 enum CLB_MUX_I3
CLB.MUX_F3	MAIN[16][1]	MAIN[17][1]
CLB.MUX_G3	MAIN[1][1]	MAIN[0][1]
C	0	1
D	1	0
Q	1	1

xc2000 CLB_NE1 enum CLB_MUX_XY
CLB.MUX_X	MAIN[7][2]	MAIN[6][2]
CLB.MUX_Y	MAIN[4][2]	MAIN[5][2]
F	0	1
G	1	0
Q	1	1

xc2000 CLB_NE1 enum CLB_MUX_RES
CLB.MUX_RES	MAIN[16][2]	MAIN[17][2]
D	0	1
G	0	0
TIE_0	1	1

xc2000 CLB_NE1 enum CLB_MUX_SET
CLB.MUX_SET	MAIN[15][2]	MAIN[14][2]
A	1	1
F	1	0
TIE_0	0	1

Bels IO

xc2000 CLB_NE1 bel IO pins
Pin	Direction	IO_N[0]	IO_N[1]
O	in	CELL.IMUX_IO_N_O[0]	CELL.IMUX_IO_N_O[1]
T	in	CELL.IMUX_IO_N_T[0]	CELL.IMUX_IO_N_T[1]
K	in	CELL.IOCLK_N	CELL.IOCLK_N
I	out	CELL.OUT_IO_N_I[0]	CELL.OUT_IO_N_I[1]

xc2000 CLB_NE1 bel IO attribute bits
Attribute	IO_N[0]	IO_N[1]
MUX_I	[enum: IO_MUX_I]	[enum: IO_MUX_I]
READBACK_Q bit 0	!MAIN[4][7]	!MAIN[8][8]

xc2000 CLB_NE1 enum IO_MUX_I
IO_N[0].MUX_I	MAIN[13][8]
IO_N[1].MUX_I	MAIN[7][8]
PAD	0
Q	1

Bel wires

xc2000 CLB_NE1 bel wires
Wire	Pins
CELL.IOCLK_N	IO_N[0].K, IO_N[1].K
CELL.IMUX_CLB_A	CLB.A
CELL.IMUX_CLB_B	CLB.B
CELL.IMUX_CLB_C	CLB.C
CELL.IMUX_CLB_D_N	CLB.D
CELL.IMUX_CLB_K	CLB.K
CELL.IMUX_IO_N_O[0]	IO_N[0].O
CELL.IMUX_IO_N_O[1]	IO_N[1].O
CELL.IMUX_IO_N_T[0]	IO_N[0].T
CELL.IMUX_IO_N_T[1]	IO_N[1].T
CELL.OUT_CLB_X	CLB.X
CELL.OUT_CLB_Y	CLB.Y
CELL.OUT_IO_N_I[0]	IO_N[0].I
CELL.OUT_IO_N_I[1]	IO_N[1].I

Bitstream

xc2000 CLB_NE1 rect MAIN
Bit	Frame
Bit	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B8	INT: mux CELL.IMUX_IO_N_O[0] bit 0	INT: mux CELL.IMUX_IO_N_O[0] bit 1	INT: mux CELL.IMUX_IO_N_T[0] bit 2	INT: mux CELL.IMUX_IO_N_T[0] bit 0	IO_N[0]: MUX_I bit 0	INT: mux CELL.IMUX_IO_N_T[0] bit 1	INT: mux CELL.IMUX_IO_N_T[1] bit 1	INT: mux CELL.IMUX_IO_N_T[1] bit 2	INT: mux CELL.IMUX_IO_N_T[1] bit 0	IO_N[1]: ! READBACK_Q bit 0	IO_N[1]: MUX_I bit 0	INT: mux CELL.IMUX_CLB_A bit 1	INT: mux CELL.IMUX_CLB_A bit 4	INT: mux CELL.IMUX_CLB_A bit 2	INT: !bipass CELL.SINGLE_HN[2] = CELL.LONG_V[1]	INT: mux CELL.IMUX_IO_N_O[1] bit 1	INT: mux CELL.IMUX_IO_N_O[1] bit 3	INT: mux CELL.IMUX_IO_N_O[1] bit 0
B7	-	INT: mux CELL.IMUX_IO_N_O[0] bit 2	INT: mux CELL.IMUX_IO_N_O[0] bit 3	-	-	-	INT: !pass CELL.LONG_V[1] ← CELL.OUT_IO_N_I[0]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_N_I[0]	-	INT: !bipass CELL.LONG_IO_N = CELL.LONG_V[0]	INT: !pass CELL.SINGLE_HN[1] ← CELL.OUT_IO_N_I[1]	INT: mux CELL.IMUX_CLB_A bit 0	INT: mux CELL.IMUX_CLB_A bit 3	IO_N[0]: ! READBACK_Q bit 0	INT: !pass CELL.SINGLE_HN[3] ← CELL.OUT_IO_N_I[1]	INT: !pass CELL.LONG_IO_N ← CELL.OUT_IO_N_I[1]	INT: mux CELL.IMUX_IO_N_O[1] bit 2	INT: !bipass CELL.SINGLE_V[3] = CELL.LONG_H
B6	INT: !bipass CELL.SINGLE_HN[1] = CELL.SINGLE_HN_E[0]	INT: !bipass CELL.SINGLE_HN_E[1] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.LONG_H	INT: !bipass CELL.SINGLE_HN[0] = CELL.SINGLE_HN_E[0]	INT: !bipass CELL.SINGLE_HN[0] = CELL.SINGLE_HN_E[1]	INT: !bipass CELL.SINGLE_HN[0] = CELL.SINGLE_V[1]	INT: !pass CELL.SINGLE_HN[0] ← CELL.OUT_IO_N_I[0]	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_N_I[0]	INT: !bipass CELL.SINGLE_HN[2] = CELL.SINGLE_V[4]	INT: !pass CELL.LONG_V[0] ← CELL.OUT_IO_N_I_E1	INT: !bipass CELL.SINGLE_HN[1] = CELL.LONG_V[0]	INT: !bipass CELL.LONG_H = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_HN[3] = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_HN_E[2] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_HN_E[3] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_HN[2] = CELL.SINGLE_HN_E[2]	INT: !bipass CELL.SINGLE_HN[2] = CELL.SINGLE_HN_E[3]	INT: !bipass CELL.SINGLE_HN[3] = CELL.SINGLE_V[3]
B5	INT: !bipass CELL.SINGLE_HN_E[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_HN[1] = CELL.SINGLE_HN_E[1]	INT: !bipass CELL.SINGLE_HN[1] = CELL.SINGLE_V[0]	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_N_I_E1	INT: !bipass CELL.SINGLE_HN_E[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_HN[1] = CELL.SINGLE_V[1]	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_N_I[0]	INT: !bipass CELL.SINGLE_HN[1] = CELL.SINGLE_V[4]	INT: !pass CELL.LONG_H ← CELL.OUT_IO_N_I[0]	INT: !pass CELL.SINGLE_HN[2] ← CELL.OUT_IO_N_I[0]	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_N_I_E1	INT: !bipass CELL.LONG_H = CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_HN[0] = CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_HN[3] = CELL.SINGLE_HN_E[2]	INT: !bipass CELL.SINGLE_HN[3] = CELL.SINGLE_HN_E[3]	INT: !bipass CELL.SINGLE_HN[3] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_HN_E[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_HN[2] = CELL.SINGLE_V[3]
B4	INT: mux CELL.IMUX_CLB_C bit 3	INT: mux CELL.IMUX_CLB_C bit 2	INT: mux CELL.IMUX_CLB_B bit 0	INT: mux CELL.IMUX_CLB_B bit 3	INT: mux CELL.IMUX_CLB_C bit 0	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_X_E	-	-	-	-	-	-	-	-	-	-	-	-
B3	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_Y_E	INT: mux CELL.IMUX_CLB_K bit 1	INT: mux CELL.IMUX_CLB_K bit 2	INT: mux CELL.IMUX_CLB_K bit 0	CLB: !invert K	INT: mux CELL.IMUX_CLB_K bit 3	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X_E	-	INT: !pass CELL.LONG_V[0] ← CELL.OUT_CLB_X_E	INT: !pass CELL.LONG_V[1] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E	INT: mux CELL.IMUX_CLB_B bit 4	INT: mux CELL.IMUX_CLB_B bit 2	INT: mux CELL.IMUX_CLB_C bit 1	INT: mux CELL.IMUX_CLB_B bit 1	INT: mux CELL.IMUX_CLB_C bit 4	INT: mux CELL.IMUX_CLB_B bit 5
B2	CLB: MUX_RES bit 0	CLB: MUX_RES bit 1	CLB: MUX_SET bit 1	CLB: MUX_SET bit 0	-	-	-	-	-	CLB: FF_MODE bit 0	CLB: MUX_X bit 1	CLB: MUX_X bit 0	CLB: MUX_Y bit 0	CLB: MUX_Y bit 1	CLB: ! READBACK_Q bit 0	-	-	-
B1	CLB: MUX_F3 bit 0	CLB: MUX_F3 bit 1	-	-	-	-	CLB: MUX_F2 bit 0	CLB: MUX_F1 bit 0	-	-	-	CLB: MUX_G1 bit 0	CLB: MUX_G2 bit 0	-	-	-	CLB: MUX_G3 bit 1	CLB: MUX_G3 bit 0
B0	CLB: ! F bit 1	CLB: ! F bit 0	CLB: ! F bit 2	CLB: ! F bit 3	CLB: ! F bit 5	CLB: ! F bit 4	CLB: ! F bit 6	CLB: ! F bit 7	-	CLB: MODE bit 0	CLB: ! G bit 7	CLB: ! G bit 6	CLB: ! G bit 4	CLB: ! G bit 5	CLB: ! G bit 3	CLB: ! G bit 2	CLB: ! G bit 0	CLB: ! G bit 1

xc2000 CLB_NE1 rect MAIN_E
Bit	Frame
Bit	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	INT: mux CELL.IMUX_IO_N_O[1] bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile CLB_NW

Cells: 3

Switchbox INT

xc2000 CLB_NW switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_HN[0]	CELL.OUT_IO_N_I[0]	!MAIN[2][5]
CELL.SINGLE_HN[1]	CELL.OUT_IO_N_I[1]	!MAIN[7][7]
CELL.SINGLE_HN[2]	CELL.OUT_IO_N_I[0]	!MAIN[1][5]
CELL.SINGLE_HN[3]	CELL.OUT_IO_N_I[1]	!MAIN[3][7]
CELL.SINGLE_VW[1]	CELL.OUT_IO_W_I[1]	!MAIN[15][5]
CELL.SINGLE_VW[1]	CELL.OUT_IO_N_I[0]	!MAIN[9][5]
CELL.SINGLE_VW[3]	CELL.OUT_IO_W_I[1]	!MAIN[5][5]
CELL.SINGLE_VW[3]	CELL.OUT_IO_N_I[0]	!MAIN[10][7]
CELL.LONG_H	CELL.OUT_IO_N_I[0]	!MAIN[3][5]
CELL.LONG_IO_N	CELL.OUT_IO_N_I[1]	!MAIN[2][7]
CELL.LONG_V[1]	CELL.OUT_IO_W_I[1]	!MAIN[7][3]
CELL.LONG_V[1]	CELL.OUT_IO_N_I[0]	!MAIN[11][7]
CELL.LONG_IO_W	CELL.OUT_IO_N_I[0]	!MAIN[10][5]

xc2000 CLB_NW switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_HN[0]	CELL.SINGLE_VW[0]	!MAIN[12][5]
CELL.SINGLE_HN[0]	CELL.LONG_IO_W	!MAIN[11][5]
CELL.SINGLE_HN[1]	CELL.SINGLE_VW[1]	!MAIN[8][5]
CELL.SINGLE_HN[2]	CELL.SINGLE_VW[2]	!MAIN[6][5]
CELL.SINGLE_HN[2]	CELL.LONG_V[1]	!MAIN[3][8]
CELL.SINGLE_HN[3]	CELL.SINGLE_VW[3]	!MAIN[0][5]
CELL.SINGLE_VW[0]	CELL.LONG_IO_N	!MAIN[13][5]
CELL.SINGLE_VW[3]	CELL.LONG_H	!MAIN[0][7]
CELL.LONG_H	CELL.LONG_V[0]	!MAIN[7][5]
CELL.LONG_H	CELL.LONG_V[1]	!MAIN[4][5]
CELL.LONG_IO_N	CELL.LONG_V[0]	!MAIN[8][7]
CELL.LONG_IO_N	CELL.LONG_IO_W	!MAIN[14][5]

xc2000 CLB_NW switchbox INT muxes IMUX_CLB_A
Bits					Destination
MAIN[5][8]	MAIN[5][7]	MAIN[4][8]	MAIN[6][8]	MAIN[6][7]	CELL.IMUX_CLB_A
					Source
0	0	0	1	1	CELL.SINGLE_HN[2]
0	0	1	1	1	CELL.SINGLE_HN[0]
0	1	0	0	1	CELL.SINGLE_HN[1]
0	1	1	0	1	CELL.LONG_H
0	1	1	1	0	CELL.SINGLE_HN[3]
1	1	0	1	1	CELL.LONG_IO_N
1	1	1	1	1	CELL.OUT_IO_N_I[0]

xc2000 CLB_NW switchbox INT muxes IMUX_CLB_B
Bits						Destination
MAIN[0][3]	MAIN[5][3]	MAIN[14][4]	MAIN[4][3]	MAIN[2][3]	MAIN[15][4]	CELL.IMUX_CLB_B
						Source
0	0	0	1	1	1	CELL.SINGLE_VW[0]
0	0	1	0	1	1	CELL.SINGLE_VW[1]
0	0	1	1	0	1	CELL.SINGLE_VW[2]
0	0	1	1	1	0	CELL.OUT_IO_W_I[1]
0	1	0	1	1	1	CELL.LONG_V[0]
0	1	1	0	1	1	CELL.LONG_V[1]
0	1	1	1	0	1	CELL.GCLK
0	1	1	1	1	0	CELL.LONG_IO_W
1	0	1	1	1	1	CELL.OUT_IO_N_I[0]
1	1	1	1	1	1	CELL.SINGLE_VW[3]

xc2000 CLB_NW switchbox INT muxes IMUX_CLB_C
Bits					Destination
MAIN[1][3]	MAIN[17][4]	MAIN[16][4]	MAIN[3][3]	MAIN[13][4]	CELL.IMUX_CLB_C
					Source
0	0	1	1	0	CELL.LONG_IO_W
0	0	1	1	1	CELL.SINGLE_VW[0]
0	1	0	1	0	CELL.LONG_V[0]
0	1	0	1	1	CELL.SINGLE_VW[1]
0	1	1	0	0	CELL.LONG_V[1]
0	1	1	0	1	CELL.SINGLE_VW[2]
1	1	1	1	0	CELL.SINGLE_VW[3]
1	1	1	1	1	CELL.OUT_CLB_X_N

xc2000 CLB_NW switchbox INT muxes IMUX_CLB_K
Bits				Destination
MAIN[11][3]	MAIN[14][3]	MAIN[15][3]	MAIN[13][3]	CELL.IMUX_CLB_K
				Source
0	0	1	1	CELL.LONG_V[1]
0	1	0	1	CELL.GCLK
0	1	1	0	CELL.SPECIAL_CLB_C
0	1	1	1	~CELL.SPECIAL_CLB_G
1	1	1	1	off

xc2000 CLB_NW switchbox INT muxes IMUX_IO_W_O[1]
Bits				Destination
MAIN[18][1]	MAIN[19][1]	MAIN[20][1]	MAIN[18][0]	CELL.IMUX_IO_W_O[1]
				Source
0	0	1	0	S.SINGLE_H[1]
0	0	1	1	CELL.SINGLE_VW[0]
0	1	0	0	CELL.LONG_V[0]
0	1	0	1	CELL.LONG_IO_W
1	1	1	0	S.SINGLE_H[3]
1	1	1	1	CELL.SINGLE_VW[2]

xc2000 CLB_NW switchbox INT muxes IMUX_IO_W_T[1]
Bits			Destination
MAIN[20][2]	MAIN[19][2]	MAIN[18][2]	CELL.IMUX_IO_W_T[1]
			Source
0	0	0	CELL.SINGLE_VW[0]
0	0	1	CELL.SINGLE_VW[2]
0	1	0	CELL.LONG_V[0]
0	1	1	CELL.LONG_IO_W
1	0	1	CELL.TIE_1
1	1	1	CELL.TIE_0

xc2000 CLB_NW switchbox INT muxes IMUX_IO_N_O[0]
Bits					Destination
MAIN[15][7]	MAIN[16][7]	MAIN[16][8]	MAIN[17][8]	MAIN[18][7]	CELL.IMUX_IO_N_O[0]
					Source
0	0	0	1	1	CELL.LONG_V[0]
0	0	1	1	1	CELL.SINGLE_HN[1]
0	1	0	0	1	CELL.LONG_IO_N
0	1	0	1	0	CELL.GCLK
0	1	1	0	1	CELL.SINGLE_VW[2]
0	1	1	1	0	CELL.LONG_IO_W
1	1	0	1	1	CELL.SINGLE_HN[3]
1	1	1	1	1	CELL.SINGLE_VW[0]

xc2000 CLB_NW switchbox INT muxes IMUX_IO_N_O[1]
Bits					Destination
MAIN_E[17][7]	MAIN[1][8]	MAIN[1][7]	MAIN[2][8]	MAIN[0][8]	CELL.IMUX_IO_N_O[1]
					Source
0	0	1	0	1	CELL.OUT_CLB_X
0	0	1	1	1	CELL.SINGLE_HN[0]
0	1	0	0	1	CELL.SINGLE_HN[2]
0	1	0	1	1	CELL.LONG_H
0	1	1	0	0	E.SINGLE_V[3]
0	1	1	1	0	E.SINGLE_V[4]
1	1	1	0	1	E.SINGLE_V[1]
1	1	1	1	1	E.LONG_V[1]

xc2000 CLB_NW switchbox INT muxes IMUX_IO_N_T[0]
Bits			Destination
MAIN[15][8]	MAIN[12][8]	MAIN[14][8]	CELL.IMUX_IO_N_T[0]
			Source
0	0	1	CELL.SINGLE_HN[0]
0	1	0	CELL.TIE_1
0	1	1	CELL.LONG_H
1	0	1	CELL.LONG_IO_N
1	1	0	CELL.TIE_0
1	1	1	CELL.SINGLE_HN[2]

xc2000 CLB_NW switchbox INT muxes IMUX_IO_N_T[1]
Bits			Destination
MAIN[10][8]	MAIN[11][8]	MAIN[9][8]	CELL.IMUX_IO_N_T[1]
			Source
0	0	1	CELL.SINGLE_HN[0]
0	1	0	CELL.TIE_0
0	1	1	CELL.LONG_H
1	0	1	CELL.LONG_IO_N
1	1	0	CELL.TIE_1
1	1	1	CELL.SINGLE_HN[2]

xc2000 CLB_NW switchbox INT muxes IMUX_BUFG
Bits						Destination
MAIN[16][5]	MAIN[20][3]	MAIN[17][5]	MAIN[19][3]	MAIN[18][3]	MAIN[18][5]	CELL.IMUX_BUFG
						Source
0	0	1	1	1	1	CELL.SINGLE_VW[2]
0	1	0	1	1	1	CELL.LONG_H
0	1	1	0	1	1	CELL.LONG_V[0]
0	1	1	1	0	1	CELL.OUT_IO_W_I[1]
0	1	1	1	1	0	CELL.OUT_IO_N_I[0]
1	1	1	1	1	1	CELL.SINGLE_HN[2]

Switchbox BUFG

xc2000 CLB_NW switchbox BUFG permanent buffers
Destination	Source
CELL.GCLK	CELL.IMUX_BUFG

Bels CLB

xc2000 CLB_NW bel CLB pins
Pin	Direction	CLB
A	in	CELL.IMUX_CLB_A
B	in	CELL.IMUX_CLB_B
C	in	CELL.IMUX_CLB_C
D	in	CELL.IMUX_CLB_D_N
K	in	CELL.IMUX_CLB_K invert by !MAIN[12][3]
X	out	CELL.OUT_CLB_X
Y	out	CELL.OUT_CLB_Y

xc2000 CLB_NW bel CLB attribute bits
Attribute	CLB
F bit 0	!MAIN[16][0]
F bit 1	!MAIN[17][0]
F bit 2	!MAIN[15][0]
F bit 3	!MAIN[14][0]
F bit 4	!MAIN[12][0]
F bit 5	!MAIN[13][0]
F bit 6	!MAIN[11][0]
F bit 7	!MAIN[10][0]
G bit 0	!MAIN[1][0]
G bit 1	!MAIN[0][0]
G bit 2	!MAIN[2][0]
G bit 3	!MAIN[3][0]
G bit 4	!MAIN[5][0]
G bit 5	!MAIN[4][0]
G bit 6	!MAIN[6][0]
G bit 7	!MAIN[7][0]
MODE	[enum: CLB_MODE]
FF_MODE	[enum: FF_MODE]
MUX_F1	[enum: CLB_MUX_I1]
MUX_G1	[enum: CLB_MUX_I1]
MUX_F2	[enum: CLB_MUX_I2]
MUX_G2	[enum: CLB_MUX_I2]
MUX_F3	[enum: CLB_MUX_I3]
MUX_G3	[enum: CLB_MUX_I3]
MUX_X	[enum: CLB_MUX_XY]
MUX_Y	[enum: CLB_MUX_XY]
MUX_RES	[enum: CLB_MUX_RES]
MUX_SET	[enum: CLB_MUX_SET]
READBACK_Q bit 0	!MAIN[3][2]

xc2000 CLB_NW enum CLB_MODE
CLB.MODE	MAIN[8][0]
FGM	1
FG	0

xc2000 CLB_NW enum FF_MODE
CLB.FF_MODE	MAIN[8][2]
FF	1
LATCH	0

xc2000 CLB_NW enum CLB_MUX_I1
CLB.MUX_F1	MAIN[10][1]
CLB.MUX_G1	MAIN[6][1]
A	0
B	1

xc2000 CLB_NW enum CLB_MUX_I2
CLB.MUX_F2	MAIN[11][1]
CLB.MUX_G2	MAIN[5][1]
B	0
C	1

xc2000 CLB_NW enum CLB_MUX_I3
CLB.MUX_F3	MAIN[16][1]	MAIN[17][1]
CLB.MUX_G3	MAIN[1][1]	MAIN[0][1]
C	0	1
D	1	0
Q	1	1

xc2000 CLB_NW enum CLB_MUX_XY
CLB.MUX_X	MAIN[7][2]	MAIN[6][2]
CLB.MUX_Y	MAIN[4][2]	MAIN[5][2]
F	0	1
G	1	0
Q	1	1

xc2000 CLB_NW enum CLB_MUX_RES
CLB.MUX_RES	MAIN[16][2]	MAIN[17][2]
D	0	1
G	0	0
TIE_0	1	1

xc2000 CLB_NW enum CLB_MUX_SET
CLB.MUX_SET	MAIN[15][2]	MAIN[14][2]
A	1	1
F	1	0
TIE_0	0	1

Bels IO

xc2000 CLB_NW bel IO pins
Pin	Direction	IO_W[1]	IO_N[0]	IO_N[1]
O	in	CELL.IMUX_IO_W_O[1]	CELL.IMUX_IO_N_O[0]	CELL.IMUX_IO_N_O[1]
T	in	CELL.IMUX_IO_W_T[1]	CELL.IMUX_IO_N_T[0]	CELL.IMUX_IO_N_T[1]
K	in	CELL.IOCLK_W	CELL.IOCLK_N	CELL.IOCLK_N
I	out	CELL.OUT_IO_W_I[1]	CELL.OUT_IO_N_I[0]	CELL.OUT_IO_N_I[1]

xc2000 CLB_NW bel IO attribute bits
Attribute	IO_W[1]	IO_N[0]	IO_N[1]
MUX_I	[enum: IO_MUX_I]	[enum: IO_MUX_I]	[enum: IO_MUX_I]
READBACK_Q bit 0	!MAIN[20][0]	!MAIN[4][7]	!MAIN[8][8]

xc2000 CLB_NW enum IO_MUX_I
IO_W[1].MUX_I	MAIN[19][0]
IO_N[0].MUX_I	MAIN[13][8]
IO_N[1].MUX_I	MAIN[7][8]
PAD	0
Q	1

Bels MISC_NW

xc2000 CLB_NW bel MISC_NW pins
Pin	Direction	MISC_NW

xc2000 CLB_NW bel MISC_NW attribute bits
Attribute	MISC_NW
IO_INPUT_MODE	[enum: IO_INPUT_MODE]

xc2000 CLB_NW enum IO_INPUT_MODE
MISC_NW.IO_INPUT_MODE	MAIN[19][7]
TTL	1
CMOS	0

Bel wires

xc2000 CLB_NW bel wires
Wire	Pins
CELL.IOCLK_W	IO_W[1].K
CELL.IOCLK_N	IO_N[0].K, IO_N[1].K
CELL.IMUX_CLB_A	CLB.A
CELL.IMUX_CLB_B	CLB.B
CELL.IMUX_CLB_C	CLB.C
CELL.IMUX_CLB_D_N	CLB.D
CELL.IMUX_CLB_K	CLB.K
CELL.IMUX_IO_W_O[1]	IO_W[1].O
CELL.IMUX_IO_W_T[1]	IO_W[1].T
CELL.IMUX_IO_N_O[0]	IO_N[0].O
CELL.IMUX_IO_N_O[1]	IO_N[1].O
CELL.IMUX_IO_N_T[0]	IO_N[0].T
CELL.IMUX_IO_N_T[1]	IO_N[1].T
CELL.OUT_CLB_X	CLB.X
CELL.OUT_CLB_Y	CLB.Y
CELL.OUT_IO_W_I[1]	IO_W[1].I
CELL.OUT_IO_N_I[0]	IO_N[0].I
CELL.OUT_IO_N_I[1]	IO_N[1].I

Bitstream

xc2000 CLB_NW rect MAIN
Bit	Frame
Bit	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B8	-	-	-	INT: mux CELL.IMUX_IO_N_O[0] bit 1	INT: mux CELL.IMUX_IO_N_O[0] bit 2	INT: mux CELL.IMUX_IO_N_T[0] bit 2	INT: mux CELL.IMUX_IO_N_T[0] bit 0	IO_N[0]: MUX_I bit 0	INT: mux CELL.IMUX_IO_N_T[0] bit 1	INT: mux CELL.IMUX_IO_N_T[1] bit 1	INT: mux CELL.IMUX_IO_N_T[1] bit 2	INT: mux CELL.IMUX_IO_N_T[1] bit 0	IO_N[1]: ! READBACK_Q bit 0	IO_N[1]: MUX_I bit 0	INT: mux CELL.IMUX_CLB_A bit 1	INT: mux CELL.IMUX_CLB_A bit 4	INT: mux CELL.IMUX_CLB_A bit 2	INT: !bipass CELL.SINGLE_HN[2] = CELL.LONG_V[1]	INT: mux CELL.IMUX_IO_N_O[1] bit 1	INT: mux CELL.IMUX_IO_N_O[1] bit 3	INT: mux CELL.IMUX_IO_N_O[1] bit 0
B7	-	MISC_NW: IO_INPUT_MODE bit 0	INT: mux CELL.IMUX_IO_N_O[0] bit 0	-	INT: mux CELL.IMUX_IO_N_O[0] bit 3	INT: mux CELL.IMUX_IO_N_O[0] bit 4	-	-	-	INT: !pass CELL.LONG_V[1] ← CELL.OUT_IO_N_I[0]	INT: !pass CELL.SINGLE_VW[3] ← CELL.OUT_IO_N_I[0]	-	INT: !bipass CELL.LONG_IO_N = CELL.LONG_V[0]	INT: !pass CELL.SINGLE_HN[1] ← CELL.OUT_IO_N_I[1]	INT: mux CELL.IMUX_CLB_A bit 0	INT: mux CELL.IMUX_CLB_A bit 3	IO_N[0]: ! READBACK_Q bit 0	INT: !pass CELL.SINGLE_HN[3] ← CELL.OUT_IO_N_I[1]	INT: !pass CELL.LONG_IO_N ← CELL.OUT_IO_N_I[1]	INT: mux CELL.IMUX_IO_N_O[1] bit 2	INT: !bipass CELL.SINGLE_VW[3] = CELL.LONG_H
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	INT: mux CELL.IMUX_BUFG bit 0	INT: mux CELL.IMUX_BUFG bit 3	INT: mux CELL.IMUX_BUFG bit 5	INT: !pass CELL.SINGLE_VW[1] ← CELL.OUT_IO_W_I[1]	INT: !bipass CELL.LONG_IO_N = CELL.LONG_IO_W	INT: !bipass CELL.SINGLE_VW[0] = CELL.LONG_IO_N	INT: !bipass CELL.SINGLE_HN[0] = CELL.SINGLE_VW[0]	INT: !bipass CELL.SINGLE_HN[0] = CELL.LONG_IO_W	INT: !pass CELL.LONG_IO_W ← CELL.OUT_IO_N_I[0]	INT: !pass CELL.SINGLE_VW[1] ← CELL.OUT_IO_N_I[0]	INT: !bipass CELL.SINGLE_HN[1] = CELL.SINGLE_VW[1]	INT: !bipass CELL.LONG_H = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_HN[2] = CELL.SINGLE_VW[2]	INT: !pass CELL.SINGLE_VW[3] ← CELL.OUT_IO_W_I[1]	INT: !bipass CELL.LONG_H = CELL.LONG_V[1]	INT: !pass CELL.LONG_H ← CELL.OUT_IO_N_I[0]	INT: !pass CELL.SINGLE_HN[0] ← CELL.OUT_IO_N_I[0]	INT: !pass CELL.SINGLE_HN[2] ← CELL.OUT_IO_N_I[0]	INT: !bipass CELL.SINGLE_HN[3] = CELL.SINGLE_VW[3]
B4	-	-	-	INT: mux CELL.IMUX_CLB_C bit 3	INT: mux CELL.IMUX_CLB_C bit 2	INT: mux CELL.IMUX_CLB_B bit 0	INT: mux CELL.IMUX_CLB_B bit 3	INT: mux CELL.IMUX_CLB_C bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	INT: mux CELL.IMUX_BUFG bit 4	INT: mux CELL.IMUX_BUFG bit 2	INT: mux CELL.IMUX_BUFG bit 1	-	-	INT: mux CELL.IMUX_CLB_K bit 1	INT: mux CELL.IMUX_CLB_K bit 2	INT: mux CELL.IMUX_CLB_K bit 0	CLB: !invert K	INT: mux CELL.IMUX_CLB_K bit 3	-	-	-	INT: !pass CELL.LONG_V[1] ← CELL.OUT_IO_W_I[1]	-	INT: mux CELL.IMUX_CLB_B bit 4	INT: mux CELL.IMUX_CLB_B bit 2	INT: mux CELL.IMUX_CLB_C bit 1	INT: mux CELL.IMUX_CLB_B bit 1	INT: mux CELL.IMUX_CLB_C bit 4	INT: mux CELL.IMUX_CLB_B bit 5
B2	INT: mux CELL.IMUX_IO_W_T[1] bit 2	INT: mux CELL.IMUX_IO_W_T[1] bit 1	INT: mux CELL.IMUX_IO_W_T[1] bit 0	CLB: MUX_RES bit 0	CLB: MUX_RES bit 1	CLB: MUX_SET bit 1	CLB: MUX_SET bit 0	-	-	-	-	-	CLB: FF_MODE bit 0	CLB: MUX_X bit 1	CLB: MUX_X bit 0	CLB: MUX_Y bit 0	CLB: MUX_Y bit 1	CLB: ! READBACK_Q bit 0	-	-	-
B1	INT: mux CELL.IMUX_IO_W_O[1] bit 1	INT: mux CELL.IMUX_IO_W_O[1] bit 2	INT: mux CELL.IMUX_IO_W_O[1] bit 3	CLB: MUX_F3 bit 0	CLB: MUX_F3 bit 1	-	-	-	-	CLB: MUX_F2 bit 0	CLB: MUX_F1 bit 0	-	-	-	CLB: MUX_G1 bit 0	CLB: MUX_G2 bit 0	-	-	-	CLB: MUX_G3 bit 1	CLB: MUX_G3 bit 0
B0	IO_W[1]: ! READBACK_Q bit 0	IO_W[1]: MUX_I bit 0	INT: mux CELL.IMUX_IO_W_O[1] bit 0	CLB: ! F bit 1	CLB: ! F bit 0	CLB: ! F bit 2	CLB: ! F bit 3	CLB: ! F bit 5	CLB: ! F bit 4	CLB: ! F bit 6	CLB: ! F bit 7	-	CLB: MODE bit 0	CLB: ! G bit 7	CLB: ! G bit 6	CLB: ! G bit 4	CLB: ! G bit 5	CLB: ! G bit 3	CLB: ! G bit 2	CLB: ! G bit 0	CLB: ! G bit 1

xc2000 CLB_NW rect MAIN_E
Bit	Frame
Bit	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	INT: mux CELL.IMUX_IO_N_O[1] bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile CLB_NE

Cells: 2

Switchbox INT

xc2000 CLB_NE switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_HN[0]	CELL.OUT_IO_N_I[0]	!MAIN[20][6]
CELL.SINGLE_HN[1]	CELL.OUT_IO_N_I[1]	!MAIN[16][7]
CELL.SINGLE_HN[2]	CELL.OUT_IO_N_I[0]	!MAIN[17][5]
CELL.SINGLE_HN[3]	CELL.OUT_IO_N_I[1]	!MAIN[12][7]
CELL.SINGLE_V[0]	CELL.OUT_CLB_Y_E	!MAIN[26][3]
CELL.SINGLE_V[0]	CELL.OUT_IO_N_I_E1	!MAIN[23][5]
CELL.SINGLE_V[1]	CELL.OUT_CLB_X_E	!MAIN[19][3]
CELL.SINGLE_V[1]	CELL.OUT_IO_N_I[0]	!MAIN[20][5]
CELL.SINGLE_V[2]	CELL.OUT_CLB_Y_E	!MAIN[15][3]
CELL.SINGLE_V[2]	CELL.OUT_IO_N_I_E1	!MAIN[16][5]
CELL.SINGLE_V[3]	CELL.OUT_CLB_X_E	!MAIN[21][4]
CELL.SINGLE_V[3]	CELL.OUT_IO_N_I[0]	!MAIN[19][7]
CELL.SINGLE_V[4]	CELL.OUT_CLB_Y_E	!MAIN[25][3]
CELL.SINGLE_V[4]	CELL.OUT_IO_N_I[0]	!MAIN[19][6]
CELL.SINGLE_VE[0]	CELL.OUT_CLB_Y	!MAIN[4][3]
CELL.SINGLE_VE[0]	CELL.OUT_IO_E_I[1]	!MAIN[3][1]
CELL.SINGLE_VE[1]	CELL.OUT_CLB_X	!MAIN[3][3]
CELL.SINGLE_VE[1]	CELL.OUT_IO_N_I[1]	!MAIN[1][4]
CELL.SINGLE_VE[2]	CELL.OUT_CLB_Y	!MAIN[6][3]
CELL.SINGLE_VE[2]	CELL.OUT_IO_E_I[1]	!MAIN[5][1]
CELL.SINGLE_VE[3]	CELL.OUT_CLB_X	!MAIN[8][3]
CELL.SINGLE_VE[3]	CELL.OUT_IO_N_I[1]	!MAIN[8][4]
CELL.LONG_H	CELL.OUT_IO_N_I[0]	!MAIN[18][5]
CELL.LONG_IO_N	CELL.OUT_IO_N_I[1]	!MAIN[11][7]
CELL.LONG_V[0]	CELL.OUT_CLB_X_E	!MAIN[17][3]
CELL.LONG_V[0]	CELL.OUT_IO_N_I_E1	!MAIN[17][6]
CELL.LONG_V[1]	CELL.OUT_CLB_Y_E	!MAIN[16][3]
CELL.LONG_V[1]	CELL.OUT_IO_N_I[0]	!MAIN[20][7]
CELL.LONG_VE[0]	CELL.OUT_CLB_Y	!MAIN[5][3]
CELL.LONG_VE[0]	CELL.OUT_IO_E_I[1]	!MAIN[4][1]
CELL.LONG_VE[1]	CELL.OUT_CLB_X	!MAIN[2][3]
CELL.LONG_VE[1]	CELL.OUT_IO_N_I[1]	!MAIN[0][4]
CELL.LONG_IO_E	CELL.OUT_CLB_Y	!MAIN[7][3]
CELL.LONG_IO_E	CELL.OUT_IO_E_I[1]	!MAIN[7][2]
CELL.LONG_IO_E	CELL.OUT_IO_N_I[1]	!MAIN[5][4]

xc2000 CLB_NE switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_HN[0]	CELL.SINGLE_HN_E[0]	!MAIN[23][6]
CELL.SINGLE_HN[0]	CELL.SINGLE_HN_E[1]	!MAIN[22][6]
CELL.SINGLE_HN[0]	CELL.SINGLE_V[1]	!MAIN[21][6]
CELL.SINGLE_HN[0]	CELL.SINGLE_VE[3]	!MAIN[8][6]
CELL.SINGLE_HN[0]	CELL.LONG_V[1]	!MAIN[14][5]
CELL.SINGLE_HN[0]	CELL.LONG_IO_E	!MAIN[7][6]
CELL.SINGLE_HN[1]	CELL.SINGLE_HN_E[0]	!MAIN[26][6]
CELL.SINGLE_HN[1]	CELL.SINGLE_HN_E[1]	!MAIN[25][5]
CELL.SINGLE_HN[1]	CELL.SINGLE_V[0]	!MAIN[24][5]
CELL.SINGLE_HN[1]	CELL.SINGLE_V[1]	!MAIN[21][5]
CELL.SINGLE_HN[1]	CELL.SINGLE_V[4]	!MAIN[19][5]
CELL.SINGLE_HN[1]	CELL.SINGLE_VE[2]	!MAIN[4][4]
CELL.SINGLE_HN[1]	CELL.LONG_V[0]	!MAIN[16][6]
CELL.SINGLE_HN[2]	CELL.SINGLE_HN_E[2]	!MAIN[11][6]
CELL.SINGLE_HN[2]	CELL.SINGLE_HN_E[3]	!MAIN[10][6]
CELL.SINGLE_HN[2]	CELL.SINGLE_V[3]	!MAIN[9][5]
CELL.SINGLE_HN[2]	CELL.SINGLE_V[4]	!MAIN[18][6]
CELL.SINGLE_HN[2]	CELL.SINGLE_VE[1]	!MAIN[2][4]
CELL.SINGLE_HN[2]	CELL.LONG_V[1]	!MAIN[12][8]
CELL.SINGLE_HN[3]	CELL.SINGLE_HN_E[2]	!MAIN[13][5]
CELL.SINGLE_HN[3]	CELL.SINGLE_HN_E[3]	!MAIN[12][5]
CELL.SINGLE_HN[3]	CELL.SINGLE_V[2]	!MAIN[11][5]
CELL.SINGLE_HN[3]	CELL.SINGLE_V[3]	!MAIN[9][6]
CELL.SINGLE_HN[3]	CELL.SINGLE_VE[0]	!MAIN[3][4]
CELL.SINGLE_HN[3]	CELL.LONG_V[0]	!MAIN[14][6]
CELL.SINGLE_HN_E[0]	CELL.SINGLE_V[0]	!MAIN[26][5]
CELL.SINGLE_HN_E[1]	CELL.SINGLE_V[0]	!MAIN[25][6]
CELL.SINGLE_HN_E[1]	CELL.SINGLE_V[1]	!MAIN[22][5]
CELL.SINGLE_HN_E[2]	CELL.SINGLE_V[2]	!MAIN[13][6]
CELL.SINGLE_HN_E[3]	CELL.SINGLE_V[2]	!MAIN[12][6]
CELL.SINGLE_HN_E[3]	CELL.SINGLE_V[3]	!MAIN[10][5]
CELL.SINGLE_V[0]	CELL.LONG_H	!MAIN[24][6]
CELL.SINGLE_V[3]	CELL.LONG_H	!MAIN[9][7]
CELL.SINGLE_VE[3]	CELL.LONG_IO_N	!MAIN[7][4]
CELL.LONG_H	CELL.LONG_V[0]	!MAIN[15][6]
CELL.LONG_H	CELL.LONG_V[1]	!MAIN[15][5]
CELL.LONG_H	CELL.LONG_VE[0]	!MAIN[5][6]
CELL.LONG_H	CELL.LONG_VE[1]	!MAIN[6][6]
CELL.LONG_IO_N	CELL.LONG_V[0]	!MAIN[17][7]
CELL.LONG_IO_N	CELL.LONG_IO_E	!MAIN[6][4]

xc2000 CLB_NE switchbox INT muxes IOCLK_E
Bits				Destination
MAIN[2][6]	MAIN[3][6]	MAIN[1][6]	MAIN[4][6]	CELL.IOCLK_E
				Source
0	0	0	1	CELL.LONG_VE[1]
0	0	1	1	CELL.SINGLE_VE[0]
0	1	0	0	CELL.GCLK
0	1	1	0	CELL.SINGLE_VE[3]
1	1	0	1	CELL.SINGLE_VE[1]
1	1	1	1	CELL.SINGLE_VE[2]

xc2000 CLB_NE switchbox INT muxes IOCLK_N
Bits				Destination
MAIN[2][7]	MAIN[3][7]	MAIN[7][7]	MAIN[6][7]	CELL.IOCLK_N
				Source
0	0	0	1	CELL.SINGLE_HN[0]
0	0	1	0	CELL.GCLK
0	1	1	1	CELL.SINGLE_HN[2]
1	0	0	1	CELL.SINGLE_HN[3]
1	0	1	0	CELL.LONG_H
1	1	1	1	CELL.SINGLE_HN[1]

xc2000 CLB_NE switchbox INT muxes IMUX_CLB_A
Bits					Destination
MAIN[14][8]	MAIN[14][7]	MAIN[13][8]	MAIN[15][8]	MAIN[15][7]	CELL.IMUX_CLB_A
					Source
0	0	0	1	1	CELL.SINGLE_HN[2]
0	0	1	1	1	CELL.SINGLE_HN[0]
0	1	0	0	1	CELL.SINGLE_HN[1]
0	1	1	0	1	CELL.LONG_H
0	1	1	1	0	CELL.SINGLE_HN[3]
1	1	0	1	1	CELL.LONG_IO_N
1	1	1	1	1	CELL.OUT_IO_N_I[0]

xc2000 CLB_NE switchbox INT muxes IMUX_CLB_B
Bits						Destination
MAIN[9][3]	MAIN[14][3]	MAIN[23][4]	MAIN[13][3]	MAIN[11][3]	MAIN[24][4]	CELL.IMUX_CLB_B
						Source
0	0	0	1	1	1	CELL.SINGLE_V[0]
0	0	1	0	1	1	CELL.SINGLE_V[1]
0	0	1	1	0	1	CELL.SINGLE_V[2]
0	0	1	1	1	0	CELL.OUT_CLB_Y_E
0	1	0	1	1	1	CELL.LONG_V[0]
0	1	1	0	1	1	CELL.LONG_V[1]
0	1	1	1	0	1	CELL.GCLK
0	1	1	1	1	0	CELL.SINGLE_V[4]
1	0	1	1	1	1	CELL.OUT_IO_N_I[0]
1	1	1	1	1	1	CELL.SINGLE_V[3]

xc2000 CLB_NE switchbox INT muxes IMUX_CLB_C
Bits					Destination
MAIN[10][3]	MAIN[26][4]	MAIN[25][4]	MAIN[12][3]	MAIN[22][4]	CELL.IMUX_CLB_C
					Source
0	0	1	1	0	CELL.SINGLE_V[4]
0	0	1	1	1	CELL.SINGLE_V[0]
0	1	0	1	0	CELL.LONG_V[0]
0	1	0	1	1	CELL.SINGLE_V[1]
0	1	1	0	0	CELL.LONG_V[1]
0	1	1	0	1	CELL.SINGLE_V[2]
1	1	1	1	0	CELL.SINGLE_V[3]
1	1	1	1	1	CELL.OUT_CLB_X_N

xc2000 CLB_NE switchbox INT muxes IMUX_CLB_K
Bits				Destination
MAIN[20][3]	MAIN[23][3]	MAIN[24][3]	MAIN[22][3]	CELL.IMUX_CLB_K
				Source
0	0	1	1	CELL.LONG_V[1]
0	1	0	1	CELL.GCLK
0	1	1	0	CELL.SPECIAL_CLB_C
0	1	1	1	~CELL.SPECIAL_CLB_G
1	1	1	1	off

xc2000 CLB_NE switchbox INT muxes IMUX_IO_E_O[1]
Bits					Destination
MAIN[6][0]	MAIN[6][1]	MAIN[7][1]	MAIN[7][0]	MAIN[8][0]	CELL.IMUX_IO_E_O[1]
					Source
0	0	0	1	1	CELL.SINGLE_VE[3]
0	0	1	0	1	CELL.LONG_VE[1]
0	0	1	1	0	S.LONG_H
0	1	1	1	1	CELL.SINGLE_VE[1]
1	0	0	1	1	CELL.OUT_CLB_X
1	0	1	0	1	S.SINGLE_H[0]
1	0	1	1	0	S.SINGLE_H[2]
1	1	1	1	1	CELL.OUT_CLB_Y

xc2000 CLB_NE switchbox INT muxes IMUX_IO_E_T[1]
Bits			Destination
MAIN[5][0]	MAIN[5][2]	MAIN[4][0]	CELL.IMUX_IO_E_T[1]
			Source
0	0	1	CELL.SINGLE_VE[1]
0	1	0	CELL.TIE_0
0	1	1	CELL.SINGLE_VE[3]
1	0	1	CELL.LONG_IO_E
1	1	0	CELL.TIE_1
1	1	1	CELL.LONG_VE[1]

xc2000 CLB_NE switchbox INT muxes IMUX_IO_N_O[0]
Bits				Destination
MAIN[24][7]	MAIN[25][7]	MAIN[25][8]	MAIN[26][8]	CELL.IMUX_IO_N_O[0]
				Source
0	0	0	1	CELL.LONG_V[0]
0	0	1	1	CELL.SINGLE_HN[1]
0	1	0	0	CELL.LONG_IO_N
0	1	1	0	CELL.SINGLE_V[2]
1	1	0	1	CELL.SINGLE_HN[3]
1	1	1	1	CELL.SINGLE_V[0]

xc2000 CLB_NE switchbox INT muxes IMUX_IO_N_O[1]
Bits					Destination
MAIN[8][7]	MAIN[10][8]	MAIN[11][8]	MAIN[10][7]	MAIN[9][8]	CELL.IMUX_IO_N_O[1]
					Source
0	0	0	1	1	CELL.OUT_CLB_X
0	0	1	1	1	CELL.SINGLE_HN[0]
0	1	0	0	1	CELL.SINGLE_HN[2]
0	1	0	1	0	CELL.SINGLE_VE[0]
0	1	1	0	1	CELL.LONG_H
0	1	1	1	0	CELL.SINGLE_VE[2]
1	1	0	1	1	CELL.LONG_VE[0]
1	1	1	1	1	CELL.LONG_IO_E

xc2000 CLB_NE switchbox INT muxes IMUX_IO_N_T[0]
Bits			Destination
MAIN[24][8]	MAIN[21][8]	MAIN[23][8]	CELL.IMUX_IO_N_T[0]
			Source
0	0	1	CELL.SINGLE_HN[0]
0	1	0	CELL.TIE_1
0	1	1	CELL.LONG_H
1	0	1	CELL.LONG_IO_N
1	1	0	CELL.TIE_0
1	1	1	CELL.SINGLE_HN[2]

xc2000 CLB_NE switchbox INT muxes IMUX_IO_N_T[1]
Bits			Destination
MAIN[19][8]	MAIN[20][8]	MAIN[18][8]	CELL.IMUX_IO_N_T[1]
			Source
0	0	1	CELL.SINGLE_HN[0]
0	1	0	CELL.TIE_0
0	1	1	CELL.LONG_H
1	0	1	CELL.LONG_IO_N
1	1	0	CELL.TIE_1
1	1	1	CELL.SINGLE_HN[2]

Bels CLB

xc2000 CLB_NE bel CLB pins
Pin	Direction	CLB
A	in	CELL.IMUX_CLB_A
B	in	CELL.IMUX_CLB_B
C	in	CELL.IMUX_CLB_C
D	in	CELL.IMUX_CLB_D_N
K	in	CELL.IMUX_CLB_K invert by !MAIN[21][3]
X	out	CELL.OUT_CLB_X
Y	out	CELL.OUT_CLB_Y

xc2000 CLB_NE bel CLB attribute bits
Attribute	CLB
F bit 0	!MAIN[25][0]
F bit 1	!MAIN[26][0]
F bit 2	!MAIN[24][0]
F bit 3	!MAIN[23][0]
F bit 4	!MAIN[21][0]
F bit 5	!MAIN[22][0]
F bit 6	!MAIN[20][0]
F bit 7	!MAIN[19][0]
G bit 0	!MAIN[10][0]
G bit 1	!MAIN[9][0]
G bit 2	!MAIN[11][0]
G bit 3	!MAIN[12][0]
G bit 4	!MAIN[14][0]
G bit 5	!MAIN[13][0]
G bit 6	!MAIN[15][0]
G bit 7	!MAIN[16][0]
MODE	[enum: CLB_MODE]
FF_MODE	[enum: FF_MODE]
MUX_F1	[enum: CLB_MUX_I1]
MUX_G1	[enum: CLB_MUX_I1]
MUX_F2	[enum: CLB_MUX_I2]
MUX_G2	[enum: CLB_MUX_I2]
MUX_F3	[enum: CLB_MUX_I3]
MUX_G3	[enum: CLB_MUX_I3]
MUX_X	[enum: CLB_MUX_XY]
MUX_Y	[enum: CLB_MUX_XY]
MUX_RES	[enum: CLB_MUX_RES]
MUX_SET	[enum: CLB_MUX_SET]
READBACK_Q bit 0	!MAIN[12][2]

xc2000 CLB_NE enum CLB_MODE
CLB.MODE	MAIN[17][0]
FGM	1
FG	0

xc2000 CLB_NE enum FF_MODE
CLB.FF_MODE	MAIN[17][2]
FF	1
LATCH	0

xc2000 CLB_NE enum CLB_MUX_I1
CLB.MUX_F1	MAIN[19][1]
CLB.MUX_G1	MAIN[15][1]
A	0
B	1

xc2000 CLB_NE enum CLB_MUX_I2
CLB.MUX_F2	MAIN[20][1]
CLB.MUX_G2	MAIN[14][1]
B	0
C	1

xc2000 CLB_NE enum CLB_MUX_I3
CLB.MUX_F3	MAIN[25][1]	MAIN[26][1]
CLB.MUX_G3	MAIN[10][1]	MAIN[9][1]
C	0	1
D	1	0
Q	1	1

xc2000 CLB_NE enum CLB_MUX_XY
CLB.MUX_X	MAIN[16][2]	MAIN[15][2]
CLB.MUX_Y	MAIN[13][2]	MAIN[14][2]
F	0	1
G	1	0
Q	1	1

xc2000 CLB_NE enum CLB_MUX_RES
CLB.MUX_RES	MAIN[25][2]	MAIN[26][2]
D	0	1
G	0	0
TIE_0	1	1

xc2000 CLB_NE enum CLB_MUX_SET
CLB.MUX_SET	MAIN[24][2]	MAIN[23][2]
A	1	1
F	1	0
TIE_0	0	1

Bels IO

xc2000 CLB_NE bel IO pins
Pin	Direction	IO_E[1]	IO_N[0]	IO_N[1]
O	in	CELL.IMUX_IO_E_O[1]	CELL.IMUX_IO_N_O[0]	CELL.IMUX_IO_N_O[1]
T	in	CELL.IMUX_IO_E_T[1]	CELL.IMUX_IO_N_T[0]	CELL.IMUX_IO_N_T[1]
K	in	CELL.IOCLK_E	CELL.IOCLK_N	CELL.IOCLK_N
I	out	CELL.OUT_IO_E_I[1]	CELL.OUT_IO_N_I[0]	CELL.OUT_IO_N_I[1]

xc2000 CLB_NE bel IO attribute bits
Attribute	IO_E[1]	IO_N[0]	IO_N[1]
MUX_I	[enum: IO_MUX_I]	[enum: IO_MUX_I]	[enum: IO_MUX_I]
READBACK_Q bit 0	!MAIN[8][2]	!MAIN[13][7]	!MAIN[17][8]

xc2000 CLB_NE enum IO_MUX_I
IO_E[1].MUX_I	MAIN[2][0]
IO_N[0].MUX_I	MAIN[22][8]
IO_N[1].MUX_I	MAIN[16][8]
PAD	0
Q	1

Bels MISC_NE

xc2000 CLB_NE bel MISC_NE pins
Pin	Direction	MISC_NE

xc2000 CLB_NE bel MISC_NE attribute bits
Attribute	MISC_NE
TAC	!MAIN[8][8]

Bel wires

xc2000 CLB_NE bel wires
Wire	Pins
CELL.IOCLK_E	IO_E[1].K
CELL.IOCLK_N	IO_N[0].K, IO_N[1].K
CELL.IMUX_CLB_A	CLB.A
CELL.IMUX_CLB_B	CLB.B
CELL.IMUX_CLB_C	CLB.C
CELL.IMUX_CLB_D_N	CLB.D
CELL.IMUX_CLB_K	CLB.K
CELL.IMUX_IO_E_O[1]	IO_E[1].O
CELL.IMUX_IO_E_T[1]	IO_E[1].T
CELL.IMUX_IO_N_O[0]	IO_N[0].O
CELL.IMUX_IO_N_O[1]	IO_N[1].O
CELL.IMUX_IO_N_T[0]	IO_N[0].T
CELL.IMUX_IO_N_T[1]	IO_N[1].T
CELL.OUT_CLB_X	CLB.X
CELL.OUT_CLB_Y	CLB.Y
CELL.OUT_IO_E_I[1]	IO_E[1].I
CELL.OUT_IO_N_I[0]	IO_N[0].I
CELL.OUT_IO_N_I[1]	IO_N[1].I

Bitstream

xc2000 CLB_NE rect MAIN
Bit	Frame
Bit	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B8	INT: mux CELL.IMUX_IO_N_O[0] bit 0	INT: mux CELL.IMUX_IO_N_O[0] bit 1	INT: mux CELL.IMUX_IO_N_T[0] bit 2	INT: mux CELL.IMUX_IO_N_T[0] bit 0	IO_N[0]: MUX_I bit 0	INT: mux CELL.IMUX_IO_N_T[0] bit 1	INT: mux CELL.IMUX_IO_N_T[1] bit 1	INT: mux CELL.IMUX_IO_N_T[1] bit 2	INT: mux CELL.IMUX_IO_N_T[1] bit 0	IO_N[1]: ! READBACK_Q bit 0	IO_N[1]: MUX_I bit 0	INT: mux CELL.IMUX_CLB_A bit 1	INT: mux CELL.IMUX_CLB_A bit 4	INT: mux CELL.IMUX_CLB_A bit 2	INT: !bipass CELL.SINGLE_HN[2] = CELL.LONG_V[1]	INT: mux CELL.IMUX_IO_N_O[1] bit 2	INT: mux CELL.IMUX_IO_N_O[1] bit 3	INT: mux CELL.IMUX_IO_N_O[1] bit 0	MISC_NE: ! TAC	-	-	-	-	-	-	-	-
B7	-	INT: mux CELL.IMUX_IO_N_O[0] bit 2	INT: mux CELL.IMUX_IO_N_O[0] bit 3	-	-	-	INT: !pass CELL.LONG_V[1] ← CELL.OUT_IO_N_I[0]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_N_I[0]	-	INT: !bipass CELL.LONG_IO_N = CELL.LONG_V[0]	INT: !pass CELL.SINGLE_HN[1] ← CELL.OUT_IO_N_I[1]	INT: mux CELL.IMUX_CLB_A bit 0	INT: mux CELL.IMUX_CLB_A bit 3	IO_N[0]: ! READBACK_Q bit 0	INT: !pass CELL.SINGLE_HN[3] ← CELL.OUT_IO_N_I[1]	INT: !pass CELL.LONG_IO_N ← CELL.OUT_IO_N_I[1]	INT: mux CELL.IMUX_IO_N_O[1] bit 1	INT: !bipass CELL.SINGLE_V[3] = CELL.LONG_H	INT: mux CELL.IMUX_IO_N_O[1] bit 4	INT: mux CELL.IOCLK_N bit 1	INT: mux CELL.IOCLK_N bit 0	-	-	INT: mux CELL.IOCLK_N bit 2	INT: mux CELL.IOCLK_N bit 3	-	-
B6	INT: !bipass CELL.SINGLE_HN[1] = CELL.SINGLE_HN_E[0]	INT: !bipass CELL.SINGLE_HN_E[1] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.LONG_H	INT: !bipass CELL.SINGLE_HN[0] = CELL.SINGLE_HN_E[0]	INT: !bipass CELL.SINGLE_HN[0] = CELL.SINGLE_HN_E[1]	INT: !bipass CELL.SINGLE_HN[0] = CELL.SINGLE_V[1]	INT: !pass CELL.SINGLE_HN[0] ← CELL.OUT_IO_N_I[0]	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_N_I[0]	INT: !bipass CELL.SINGLE_HN[2] = CELL.SINGLE_V[4]	INT: !pass CELL.LONG_V[0] ← CELL.OUT_IO_N_I_E1	INT: !bipass CELL.SINGLE_HN[1] = CELL.LONG_V[0]	INT: !bipass CELL.LONG_H = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_HN[3] = CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_HN_E[2] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_HN_E[3] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_HN[2] = CELL.SINGLE_HN_E[2]	INT: !bipass CELL.SINGLE_HN[2] = CELL.SINGLE_HN_E[3]	INT: !bipass CELL.SINGLE_HN[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_HN[0] = CELL.SINGLE_VE[3]	INT: !bipass CELL.SINGLE_HN[0] = CELL.LONG_IO_E	INT: !bipass CELL.LONG_H = CELL.LONG_VE[1]	INT: !bipass CELL.LONG_H = CELL.LONG_VE[0]	INT: mux CELL.IOCLK_E bit 0	INT: mux CELL.IOCLK_E bit 2	INT: mux CELL.IOCLK_E bit 3	INT: mux CELL.IOCLK_E bit 1	-
B5	INT: !bipass CELL.SINGLE_HN_E[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_HN[1] = CELL.SINGLE_HN_E[1]	INT: !bipass CELL.SINGLE_HN[1] = CELL.SINGLE_V[0]	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_N_I_E1	INT: !bipass CELL.SINGLE_HN_E[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_HN[1] = CELL.SINGLE_V[1]	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_N_I[0]	INT: !bipass CELL.SINGLE_HN[1] = CELL.SINGLE_V[4]	INT: !pass CELL.LONG_H ← CELL.OUT_IO_N_I[0]	INT: !pass CELL.SINGLE_HN[2] ← CELL.OUT_IO_N_I[0]	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_N_I_E1	INT: !bipass CELL.LONG_H = CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_HN[0] = CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_HN[3] = CELL.SINGLE_HN_E[2]	INT: !bipass CELL.SINGLE_HN[3] = CELL.SINGLE_HN_E[3]	INT: !bipass CELL.SINGLE_HN[3] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_HN_E[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_HN[2] = CELL.SINGLE_V[3]	-	-	-	-	-	-	-	-	-
B4	INT: mux CELL.IMUX_CLB_C bit 3	INT: mux CELL.IMUX_CLB_C bit 2	INT: mux CELL.IMUX_CLB_B bit 0	INT: mux CELL.IMUX_CLB_B bit 3	INT: mux CELL.IMUX_CLB_C bit 0	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_X_E	-	-	-	-	-	-	-	-	-	-	-	-	INT: !pass CELL.SINGLE_VE[3] ← CELL.OUT_IO_N_I[1]	INT: !bipass CELL.SINGLE_VE[3] = CELL.LONG_IO_N	INT: !bipass CELL.LONG_IO_N = CELL.LONG_IO_E	INT: !pass CELL.LONG_IO_E ← CELL.OUT_IO_N_I[1]	INT: !bipass CELL.SINGLE_HN[1] = CELL.SINGLE_VE[2]	INT: !bipass CELL.SINGLE_HN[3] = CELL.SINGLE_VE[0]	INT: !bipass CELL.SINGLE_HN[2] = CELL.SINGLE_VE[1]	INT: !pass CELL.SINGLE_VE[1] ← CELL.OUT_IO_N_I[1]	INT: !pass CELL.LONG_VE[1] ← CELL.OUT_IO_N_I[1]
B3	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_Y_E	INT: mux CELL.IMUX_CLB_K bit 1	INT: mux CELL.IMUX_CLB_K bit 2	INT: mux CELL.IMUX_CLB_K bit 0	CLB: !invert K	INT: mux CELL.IMUX_CLB_K bit 3	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X_E	-	INT: !pass CELL.LONG_V[0] ← CELL.OUT_CLB_X_E	INT: !pass CELL.LONG_V[1] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E	INT: mux CELL.IMUX_CLB_B bit 4	INT: mux CELL.IMUX_CLB_B bit 2	INT: mux CELL.IMUX_CLB_C bit 1	INT: mux CELL.IMUX_CLB_B bit 1	INT: mux CELL.IMUX_CLB_C bit 4	INT: mux CELL.IMUX_CLB_B bit 5	INT: !pass CELL.SINGLE_VE[3] ← CELL.OUT_CLB_X	INT: !pass CELL.LONG_IO_E ← CELL.OUT_CLB_Y	INT: !pass CELL.SINGLE_VE[2] ← CELL.OUT_CLB_Y	INT: !pass CELL.LONG_VE[0] ← CELL.OUT_CLB_Y	INT: !pass CELL.SINGLE_VE[0] ← CELL.OUT_CLB_Y	INT: !pass CELL.SINGLE_VE[1] ← CELL.OUT_CLB_X	INT: !pass CELL.LONG_VE[1] ← CELL.OUT_CLB_X	-	-
B2	CLB: MUX_RES bit 0	CLB: MUX_RES bit 1	CLB: MUX_SET bit 1	CLB: MUX_SET bit 0	-	-	-	-	-	CLB: FF_MODE bit 0	CLB: MUX_X bit 1	CLB: MUX_X bit 0	CLB: MUX_Y bit 0	CLB: MUX_Y bit 1	CLB: ! READBACK_Q bit 0	-	-	-	IO_E[1]: ! READBACK_Q bit 0	INT: !pass CELL.LONG_IO_E ← CELL.OUT_IO_E_I[1]	-	INT: mux CELL.IMUX_IO_E_T[1] bit 1	-	-	-	-	-
B1	CLB: MUX_F3 bit 0	CLB: MUX_F3 bit 1	-	-	-	-	CLB: MUX_F2 bit 0	CLB: MUX_F1 bit 0	-	-	-	CLB: MUX_G1 bit 0	CLB: MUX_G2 bit 0	-	-	-	CLB: MUX_G3 bit 1	CLB: MUX_G3 bit 0	-	INT: mux CELL.IMUX_IO_E_O[1] bit 2	INT: mux CELL.IMUX_IO_E_O[1] bit 3	INT: !pass CELL.SINGLE_VE[2] ← CELL.OUT_IO_E_I[1]	INT: !pass CELL.LONG_VE[0] ← CELL.OUT_IO_E_I[1]	INT: !pass CELL.SINGLE_VE[0] ← CELL.OUT_IO_E_I[1]	-	-	-
B0	CLB: ! F bit 1	CLB: ! F bit 0	CLB: ! F bit 2	CLB: ! F bit 3	CLB: ! F bit 5	CLB: ! F bit 4	CLB: ! F bit 6	CLB: ! F bit 7	-	CLB: MODE bit 0	CLB: ! G bit 7	CLB: ! G bit 6	CLB: ! G bit 4	CLB: ! G bit 5	CLB: ! G bit 3	CLB: ! G bit 2	CLB: ! G bit 0	CLB: ! G bit 1	INT: mux CELL.IMUX_IO_E_O[1] bit 0	INT: mux CELL.IMUX_IO_E_O[1] bit 1	INT: mux CELL.IMUX_IO_E_O[1] bit 4	INT: mux CELL.IMUX_IO_E_T[1] bit 2	INT: mux CELL.IMUX_IO_E_T[1] bit 0	-	IO_E[1]: MUX_I bit 0	-	-

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