xc2000 tile slots

Slot	Tiles	Bel slots
MAIN	CLB, CLB_W, CLB_E, CLB_MW, CLB_ME, CLB_S, CLB_SW, CLB_SE, CLB_SE1, CLB_N, CLB_NW, CLB_NE, CLB_NE1	INT, CLB, IO_W[0], IO_W[1], IO_E[0], IO_E[1], IO_S[0], IO_S[1], IO_N[0], IO_N[1], BUFG, OSC, MISC_SW, MISC_SE, MISC_NW, MISC_NE, MISC_E
BIDIH	BIDIH, BIDIH_S, BIDIH_N	BIDIH
BIDIV	BIDIV, BIDIV_W, BIDIV_E	BIDIV

xc2000 bel slots

Slot	Class	Tile slot	Tiles
INT	routing	MAIN	CLB, CLB_W, CLB_E, CLB_MW, CLB_ME, CLB_S, CLB_SW, CLB_SE, CLB_SE1, CLB_N, CLB_NW, CLB_NE, CLB_NE1
CLB	CLB	MAIN	CLB, CLB_W, CLB_E, CLB_MW, CLB_ME, CLB_S, CLB_SW, CLB_SE, CLB_SE1, CLB_N, CLB_NW, CLB_NE, CLB_NE1
IO_W[0]	IO	MAIN	CLB_W, CLB_SW
IO_W[1]	IO	MAIN	CLB_W, CLB_MW, CLB_NW
IO_E[0]	IO	MAIN	CLB_E, CLB_SE
IO_E[1]	IO	MAIN	CLB_E, CLB_ME, CLB_NE
IO_S[0]	IO	MAIN	CLB_S, CLB_SW, CLB_SE, CLB_SE1
IO_S[1]	IO	MAIN	CLB_S, CLB_SW, CLB_SE, CLB_SE1
IO_N[0]	IO	MAIN	CLB_N, CLB_NW, CLB_NE, CLB_NE1
IO_N[1]	IO	MAIN	CLB_N, CLB_NW, CLB_NE, CLB_NE1
BUFG	routing	MAIN	CLB_SE, CLB_NW
OSC	OSC	MAIN	CLB_SE
MISC_SW	MISC_SW	MAIN	CLB_SW
MISC_SE	MISC_SE	MAIN	CLB_SE
MISC_NW	MISC_NW	MAIN	CLB_NW
MISC_NE	MISC_NE	MAIN	CLB_NE
MISC_E	MISC_E	MAIN	CLB_ME
BIDIH	routing	BIDIH	BIDIH, BIDIH_S, BIDIH_N
BIDIV	routing	BIDIV	BIDIV, BIDIV_W, BIDIV_E

xc2000 connector slots

Slot	Opposite	Connectors
W	E	PASS_W
E	W	PASS_E
S	N	PASS_S
N	S	PASS_N

xc2000 region slots

Slot	Wires
GLOBAL	GCLK, ACLK, IOCLK_W, IOCLK_E, IOCLK_S, IOCLK_N
LONG_H	LONG_H, LONG_HS, LONG_IO_S, LONG_IO_N
LONG_V	LONG_V[0], LONG_V[1], LONG_VE[0], LONG_VE[1], LONG_IO_W, LONG_IO_E

xc2000 wires

Wire	Kind
TIE_0	tie 0
TIE_1	tie 1
SPECIAL_CLB_C	special
SPECIAL_CLB_G	special
SINGLE_H[0]	multi_root
SINGLE_H[1]	multi_root
SINGLE_H[2]	multi_root
SINGLE_H[3]	multi_root
SINGLE_H_E[0]	multi_branch W
SINGLE_H_E[1]	multi_branch W
SINGLE_H_E[2]	multi_branch W
SINGLE_H_E[3]	multi_branch W
SINGLE_HS[0]	multi_root
SINGLE_HS[1]	multi_root
SINGLE_HS[2]	multi_root
SINGLE_HS[3]	multi_root
SINGLE_HS_E[0]	multi_branch W
SINGLE_HS_E[1]	multi_branch W
SINGLE_HS_E[2]	multi_branch W
SINGLE_HS_E[3]	multi_branch W
SINGLE_HN[0]	multi_root
SINGLE_HN[1]	multi_root
SINGLE_HN[2]	multi_root
SINGLE_HN[3]	multi_root
SINGLE_HN_E[0]	multi_branch W
SINGLE_HN_E[1]	multi_branch W
SINGLE_HN_E[2]	multi_branch W
SINGLE_HN_E[3]	multi_branch W
SINGLE_V[0]	multi_root
SINGLE_V[1]	multi_root
SINGLE_V[2]	multi_root
SINGLE_V[3]	multi_root
SINGLE_V[4]	multi_root
SINGLE_V_S[0]	multi_branch N
SINGLE_V_S[1]	multi_branch N
SINGLE_V_S[2]	multi_branch N
SINGLE_V_S[3]	multi_branch N
SINGLE_V_S[4]	multi_branch N
SINGLE_VW[0]	multi_root
SINGLE_VW[1]	multi_root
SINGLE_VW[2]	multi_root
SINGLE_VW[3]	multi_root
SINGLE_VW_S[0]	multi_branch N
SINGLE_VW_S[1]	multi_branch N
SINGLE_VW_S[2]	multi_branch N
SINGLE_VW_S[3]	multi_branch N
SINGLE_VE[0]	multi_root
SINGLE_VE[1]	multi_root
SINGLE_VE[2]	multi_root
SINGLE_VE[3]	multi_root
SINGLE_VE_S[0]	multi_branch N
SINGLE_VE_S[1]	multi_branch N
SINGLE_VE_S[2]	multi_branch N
SINGLE_VE_S[3]	multi_branch N
LONG_H	regional LONG_H
LONG_HS	regional LONG_H
LONG_IO_S	regional LONG_H
LONG_IO_N	regional LONG_H
LONG_V[0]	regional LONG_V
LONG_V[1]	regional LONG_V
LONG_VE[0]	regional LONG_V
LONG_VE[1]	regional LONG_V
LONG_IO_W	regional LONG_V
LONG_IO_E	regional LONG_V
GCLK	regional GLOBAL
ACLK	regional GLOBAL
IOCLK_W	regional GLOBAL
IOCLK_E	regional GLOBAL
IOCLK_S	regional GLOBAL
IOCLK_N	regional GLOBAL
IMUX_CLB_A	mux
IMUX_CLB_B	mux
IMUX_CLB_C	mux
IMUX_CLB_D	mux
IMUX_CLB_D_N	branch S
IMUX_CLB_K	mux
IMUX_IO_W_O[0]	mux
IMUX_IO_W_O[1]	mux
IMUX_IO_W_T[0]	mux
IMUX_IO_W_T[1]	mux
IMUX_IO_E_O[0]	mux
IMUX_IO_E_O[1]	mux
IMUX_IO_E_T[0]	mux
IMUX_IO_E_T[1]	mux
IMUX_IO_S_O[0]	mux
IMUX_IO_S_O[1]	mux
IMUX_IO_S_T[0]	mux
IMUX_IO_S_T[1]	mux
IMUX_IO_N_O[0]	mux
IMUX_IO_N_O[1]	mux
IMUX_IO_N_T[0]	mux
IMUX_IO_N_T[1]	mux
IMUX_BUFG	mux
OUT_CLB_X	bel
OUT_CLB_X_E	branch W
OUT_CLB_X_S	branch N
OUT_CLB_X_N	branch S
OUT_CLB_Y	bel
OUT_CLB_Y_E	branch W
OUT_IO_W_I[0]	bel
OUT_IO_W_I[1]	bel
OUT_IO_W_I_S1	branch N
OUT_IO_E_I[0]	bel
OUT_IO_E_I[1]	bel
OUT_IO_E_I_S1	branch N
OUT_IO_S_I[0]	bel
OUT_IO_S_I[1]	bel
OUT_IO_S_I_E1	branch W
OUT_IO_N_I[0]	bel
OUT_IO_N_I[1]	bel
OUT_IO_N_I_E1	branch W
OUT_OSC	bel

xc2000 wires

Wire	PASS_W
SINGLE_H_E[0]	→ SINGLE_H[0]
SINGLE_H_E[1]	→ SINGLE_H[1]
SINGLE_H_E[2]	→ SINGLE_H[2]
SINGLE_H_E[3]	→ SINGLE_H[3]
SINGLE_HS_E[0]	→ SINGLE_HS[0]
SINGLE_HS_E[1]	→ SINGLE_HS[1]
SINGLE_HS_E[2]	→ SINGLE_HS[2]
SINGLE_HS_E[3]	→ SINGLE_HS[3]
SINGLE_HN_E[0]	→ SINGLE_HN[0]
SINGLE_HN_E[1]	→ SINGLE_HN[1]
SINGLE_HN_E[2]	→ SINGLE_HN[2]
SINGLE_HN_E[3]	→ SINGLE_HN[3]
OUT_CLB_X_E	→ OUT_CLB_X
OUT_CLB_Y_E	→ OUT_CLB_Y
OUT_IO_S_I_E1	→ OUT_IO_S_I[1]
OUT_IO_N_I_E1	→ OUT_IO_N_I[1]

xc2000 wires

Wire	PASS_E

xc2000 wires

Wire	PASS_S
IMUX_CLB_D_N	→ IMUX_CLB_D
OUT_CLB_X_N	→ OUT_CLB_X

xc2000 wires

Wire	PASS_N
SINGLE_V_S[0]	→ SINGLE_V[0]
SINGLE_V_S[1]	→ SINGLE_V[1]
SINGLE_V_S[2]	→ SINGLE_V[2]
SINGLE_V_S[3]	→ SINGLE_V[3]
SINGLE_V_S[4]	→ SINGLE_V[4]
SINGLE_VW_S[0]	→ SINGLE_VW[0]
SINGLE_VW_S[1]	→ SINGLE_VW[1]
SINGLE_VW_S[2]	→ SINGLE_VW[2]
SINGLE_VW_S[3]	→ SINGLE_VW[3]
SINGLE_VE_S[0]	→ SINGLE_VE[0]
SINGLE_VE_S[1]	→ SINGLE_VE[1]
SINGLE_VE_S[2]	→ SINGLE_VE[2]
SINGLE_VE_S[3]	→ SINGLE_VE[3]
OUT_CLB_X_S	→ OUT_CLB_X
OUT_IO_W_I_S1	→ OUT_IO_W_I[1]
OUT_IO_E_I_S1	→ OUT_IO_E_I[1]