1.
Project Combine
SiliconBlue FPGAs
2.
iCE65 and iCE40
❱
2.1.
Device geometry
2.2.
General interconnect
2.3.
Logic block
2.4.
Input / Output
2.5.
Block RAM
2.6.
DSP
2.7.
SPRAM
2.8.
Clock interconnect
2.9.
Phase-Locked Loop
2.10.
SPI and I2C controllers
2.11.
Internal oscillators
2.12.
Led drivers
2.13.
Bitstream format
2.14.
iCE65L04
2.15.
iCE65P04
2.16.
iCE65L08
2.17.
iCE65L01
2.18.
iCE40LP1K
2.19.
iCE40LP384
2.20.
iCE40LP8K
2.21.
iCE40LM4K
2.22.
iCE5LP4K
2.23.
iCE40UP5K
2.24.
iCE40UL1K
Xilinx FPGAs
3.
XC2000
❱
3.1.
Device geometry
3.2.
Logic block
3.3.
Bidirectional buffers
4.
XC3000
❱
4.1.
Device geometry
4.2.
XC3000 tiles
❱
4.2.1.
Logic block
4.2.2.
Long line splitters
4.3.
XC3000A tiles
❱
4.3.1.
Logic block
4.3.2.
Long line splitters
5.
XC4000
❱
5.1.
Device geometry
5.2.
XC4000 tiles
❱
5.2.1.
Logic block
5.2.2.
Input / Output
5.2.3.
Corners
5.2.4.
Long line splitters
5.3.
XC4000A tiles
❱
5.3.1.
Logic block
5.3.2.
Input / Output
5.3.3.
Corners
5.3.4.
Long line splitters
5.4.
XC4000H tiles
❱
5.4.1.
Logic block
5.4.2.
Input / Output
5.4.3.
Corners
5.4.4.
Long line splitters
5.5.
XC4000E tiles
❱
5.5.1.
Logic block
5.5.2.
Input / Output
5.5.3.
Corners
5.5.4.
Long line splitters
5.6.
XC4000EX/XL tiles
❱
5.6.1.
Logic block
5.6.2.
Input / Output
5.6.3.
Corners
5.6.4.
Long line splitters
5.7.
XC4000XLA tiles
❱
5.7.1.
Logic block
5.7.2.
Input / Output
5.7.3.
Corners
5.7.4.
Long line splitters
5.8.
XC4000XV tiles
❱
5.8.1.
Logic block
5.8.2.
Input / Output
5.8.3.
Corners
5.8.4.
Long line splitters
5.9.
Spartan XL tiles
❱
5.9.1.
Logic block
5.9.2.
Input / Output
5.9.3.
Corners
5.9.4.
Long line splitters
6.
XC5200
❱
6.1.
Device geometry
6.2.
Logic block
6.3.
Input / Output
6.4.
Corners
6.5.
Long line splitters
7.
Virtex
❱
7.1.
Device geometry
7.2.
General interconnect
7.3.
Logic block
7.4.
Block RAM
7.5.
Clock interconnect
7.6.
Input / Output
❱
7.6.1.
I/O Interface
7.6.2.
I/O Buffers (Virtex)
7.6.3.
I/O Buffers (Virtex E)
7.7.
Delay-locked loop
7.8.
Hard PCI logic
7.9.
Corners
❱
7.9.1.
South-west
7.9.2.
North-west
7.9.3.
South-east
7.9.4.
North-east
7.10.
Configuration registers
8.
Virtex 2
❱
8.1.
Device geometry
8.2.
General interconnect
❱
8.2.1.
Interconnect tiles
8.2.2.
Terminator tiles
8.2.3.
PowerPC hole tiles
8.2.4.
Interface tiles
8.3.
Logic block
8.4.
Block RAM
8.5.
Clock interconnect
❱
8.5.1.
Global buffers
8.5.2.
Clock row distribution
8.5.3.
Clock column buffers
8.5.4.
DCM connections
8.6.
Input / Output
❱
8.6.1.
I/O Interface
8.6.2.
I/O Buffers (Virtex 2)
8.6.3.
I/O Buffers (Virtex 2 Pro)
8.7.
Digital Clock Managers
8.8.
PowerPC 405
8.9.
Multi-gigabit transceivers (Virtex 2 Pro)
8.10.
Multi-gigabit transceivers (Virtex 2 Pro X)
8.11.
Hard PCI logic
8.12.
Corners
❱
8.12.1.
South-west
8.12.2.
North-west
8.12.3.
South-east
8.12.4.
North-east
8.13.
Bitstream format
8.14.
Configuration registers
9.
Spartan 3
❱
9.1.
Device geometry
9.2.
General interconnect
❱
9.2.1.
Interconnect tiles
9.2.2.
Horizontal long line splitter tiles
9.2.3.
Vertical long line splitter tiles
9.2.4.
Interface tiles
9.3.
Logic block
9.4.
Block RAM
9.5.
DSP
9.6.
Clock interconnect
❱
9.6.1.
Primary global buffers
9.6.2.
Side global buffers
9.6.3.
Clock quadrant distribution
9.6.4.
Clock column buffers
9.7.
Input / Output
❱
9.7.1.
I/O Interface
9.7.2.
I/O Buffers (Spartan 3)
9.7.3.
I/O Buffers (Spartan 3E)
9.7.4.
I/O Buffers (Spartan 3A)
9.8.
Digital Clock Managers (Spartan 3)
9.9.
Digital Clock Managers (Spartan 3E, 3A)
9.10.
Hard PCI logic
9.11.
Corners
❱
9.11.1.
South-west
9.11.2.
North-west
9.11.3.
South-east
9.11.4.
North-east
9.12.
Configuration registers (Spartan 3, 3E)
9.13.
Configuration registers (Spartan 3A)
10.
FPGAcore
❱
10.1.
General interconnect
10.2.
Logic block
10.3.
Clock interconnect
❱
10.3.1.
Global buffers
10.3.2.
Clock quadrant distribution
10.3.3.
Clock column buffers
10.4.
Input / Output
10.5.
Corners
❱
10.5.1.
South-west
10.5.2.
North-west
10.5.3.
South-east
10.5.4.
North-east
10.6.
Configuration registers
11.
Spartan 6
❱
11.1.
Device geometry
11.2.
General interconnect
❱
11.2.1.
Interconnect tiles
11.2.2.
Interface tiles
11.3.
Logic block
11.4.
Block RAM
11.5.
DSP
11.6.
Clock interconnect
❱
11.6.1.
I/O clock buffers
11.6.2.
Global buffers
11.6.3.
Clock row buffers
11.6.4.
Clock column buffers
11.6.5.
Clock spine buffers
11.7.
Input / Output
11.8.
Hard PCI logic
11.9.
Memory Controller Block
11.10.
PCI Express
11.11.
GTP transceivers
11.12.
Digital Clock Managers
11.13.
Phase-Locked Loops
11.14.
Corners
❱
11.14.1.
South-west
11.14.2.
North-west
11.14.3.
South-east
11.14.4.
North-east
11.15.
Configuration registers
12.
Virtex 4
❱
12.1.
Device geometry
12.2.
General interconnect
12.3.
Logic block
12.4.
Block RAM
12.5.
DSP
12.6.
Clock interconnect
❱
12.6.1.
Clock row buffers
12.6.2.
Clock column buffers
12.6.3.
Clock I/O and DCM buffers
12.6.4.
Clock MGT buffers
12.6.5.
Clock spine multiplexers
12.7.
Input / Output
12.8.
Configuration center
12.9.
Digital Clock Manager
12.10.
Clock Companion Module
12.11.
System monitor
12.12.
PowerPC 405 and Ethernet MAC
12.13.
Multi-gigabit transceivers
12.14.
Configuration registers
13.
Virtex 5
❱
13.1.
Device geometry
13.2.
General interconnect
13.3.
Logic block
13.4.
Block RAM
13.5.
DSP
13.6.
Clock interconnect
❱
13.6.1.
Clock row buffers
13.6.2.
Clock column buffers
13.6.3.
Clock I/O and CMT buffers
13.6.4.
Clock MGT buffers
13.6.5.
Clock spine multiplexers
13.7.
Input / Output
13.8.
Configuration center
13.9.
Clock Management Tile
13.10.
PowerPC 440
13.11.
Ethernet MAC
13.12.
PCI Express
13.13.
GTP transceivers
13.14.
GTX transceivers
13.15.
Configuration registers
14.
Virtex 6
❱
14.1.
Device geometry
14.2.
General interconnect
14.3.
Logic block
14.4.
Block RAM
14.5.
DSP
14.6.
Clock interconnect
❱
14.6.1.
Global buffers
14.6.2.
Clock column buffers
14.6.3.
PMVIOB
14.7.
Input / Output
14.8.
Configuration center
14.9.
Clock Management Tile
14.10.
Ethernet MAC
14.11.
PCI Express
14.12.
GTX transceivers
14.13.
GTH transceivers
14.14.
Configuration registers
15.
Virtex 7
❱
15.1.
Device geometry
15.2.
General interconnect
15.3.
Logic block
15.4.
Block RAM
15.5.
DSP
15.6.
Clock interconnect
❱
15.6.1.
Global buffers
15.6.2.
Clock row buffers
15.6.3.
Clock column buffers
15.6.4.
Clock spine buffers
15.7.
Input / Output
15.8.
Configuration center
15.9.
Clock Management Tile
15.10.
PCI Express Gen 2
15.11.
PCI Express Gen 3
15.12.
GTP transceivers
15.13.
GTX transceivers
15.14.
GTH transceivers
15.15.
GTZ transceivers
15.16.
Configuration registers
16.
Ultrascale
17.
Ultrascale+
18.
Versal
Xilinx CPLDs
19.
XC9500
❱
19.1.
Device structure
19.2.
Bitstream (XC9500)
19.3.
Bitstream (XC9500XL)
19.4.
Database
19.5.
JTAG
19.6.
Devices
❱
19.6.1.
XC9536
19.6.2.
XC9572
19.6.3.
XC95108
19.6.4.
XC95144
19.6.5.
XC95216
19.6.6.
XC95288
19.6.7.
XC9536XL, XA9536XL
19.6.8.
XC9572XL, XA9572XL
19.6.9.
XC95144XL, XA95144XL
19.6.10.
XC95288XL
19.6.11.
XC9536XV
19.6.12.
XC9572XV
19.6.13.
XC95144XV
19.6.14.
XC95288XV
20.
XPLA3
❱
20.1.
Device structure
20.2.
Bitstream
20.3.
Database
20.4.
JTAG
20.5.
Devices
❱
20.5.1.
XCR3032XL
20.5.2.
XCR3064XL
20.5.3.
XCR3128XL
20.5.4.
XCR3256XL
20.5.5.
XCR3384XL
20.5.6.
XCR3512XL
21.
Coolrunner II
❱
21.1.
Device structure
21.2.
Bitstream
21.3.
Database
21.4.
JTAG
21.5.
Devices
❱
21.5.1.
XC2C32
21.5.2.
XC2C32A, XA2C32A
21.5.3.
XC2C64
21.5.4.
XC2C64A, XA2C64A
21.5.5.
XC2C128, XA2C128
21.5.6.
XC2C256, XA2C256
21.5.7.
XC2C384, XA2C384
21.5.8.
XC2C512
Programmers
22.
Digilent Adept
❱
22.1.
DMGT (board management)
22.2.
DJTG (JTAG controller)
22.3.
DPIO (GPIO)
22.4.
DEPP (EPP parallel port)
22.5.
DSTM (FX2 stream protocol)
22.6.
DSPI (SPI controller)
22.7.
DTWI (I2C controller)
22.8.
DACI (UART)
22.9.
Device list
Light
Rust
Coal
Navy
Ayu
Project Combine
XC4000