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Input/Output

Tile IO_W0

Cells: 4

Switchbox INT

spartanxl IO_W0 switchbox INT permanent buffers
DestinationSource
CELL.LONG_H_BUF[2]CELL.LONG_H[2]
CELL.LONG_H_BUF[3]CELL.LONG_H[3]
spartanxl IO_W0 switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I2_S1!MAIN[1][4]
CELL.SINGLE_H[1]CELL.LONG_IO_V[0]!MAIN[3][4]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I2[0]!MAIN[4][4]
CELL.SINGLE_H[2]CELL.LONG_IO_V[1]!MAIN[12][7]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I1[0]!MAIN[4][7]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I1_S1!MAIN[10][8]
CELL.SINGLE_H[4]CELL.OUT_IO_WE_I2_S1!MAIN[0][4]
CELL.SINGLE_H[5]CELL.LONG_IO_V[2]!MAIN[6][4]
CELL.SINGLE_H[5]CELL.OUT_IO_WE_I2[0]!MAIN[5][4]
CELL.SINGLE_H[6]CELL.LONG_IO_V[3]!MAIN[8][8]
CELL.SINGLE_H[6]CELL.OUT_IO_WE_I1[0]!MAIN[1][8]
CELL.SINGLE_H[7]CELL.OUT_IO_WE_I1_S1!MAIN[0][8]
CELL.DOUBLE_H0[0]CELL.OUT_IO_WE_I1_S1!MAIN[2][7]
CELL.DOUBLE_H0[1]CELL.OUT_IO_WE_I2[0]!MAIN[2][6]
CELL.DOUBLE_H1[0]CELL.OUT_IO_WE_I1[0]!MAIN[5][7]
CELL.DOUBLE_H1[1]CELL.OUT_IO_WE_I2_S1!MAIN[2][4]
CELL.DOUBLE_IO_W0[0]CELL.DBUF_IO_V[1]!MAIN[10][5]
CELL.DOUBLE_IO_W0[1]CELL.DBUF_IO_V[1]!MAIN[10][6]
CELL.DOUBLE_IO_W0[2]CELL.DBUF_IO_V[1]!MAIN[12][4]
CELL.DOUBLE_IO_W0[3]CELL.DBUF_IO_V[1]!MAIN[3][6]
CELL.DOUBLE_IO_W2[0]CELL.DBUF_IO_V[0]!MAIN[6][6]
CELL.DOUBLE_IO_W2[1]CELL.DBUF_IO_V[0]!MAIN[9][7]
CELL.DOUBLE_IO_W2[2]CELL.DBUF_IO_V[0]!MAIN[8][6]
CELL.DOUBLE_IO_W2[3]CELL.DBUF_IO_V[0]!MAIN[8][7]
spartanxl IO_W0 switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.DOUBLE_IO_W0[0]!MAIN[9][5]
CELL.SINGLE_H[0]CELL.DOUBLE_IO_W2[0]!MAIN[0][5]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_W1[0]!MAIN[6][5]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_W0[1]!MAIN[15][9]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_W2[1]!MAIN[9][9]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_W1[1]!MAIN[13][9]
CELL.SINGLE_H[4]CELL.DOUBLE_IO_W0[2]!MAIN[12][5]
CELL.SINGLE_H[4]CELL.DOUBLE_IO_W2[2]!MAIN[8][4]
CELL.SINGLE_H[5]CELL.DOUBLE_IO_W1[2]!MAIN[11][4]
CELL.SINGLE_H[6]CELL.DOUBLE_IO_W0[3]!MAIN[6][9]
CELL.SINGLE_H[6]CELL.DOUBLE_IO_W2[3]!MAIN[0][9]
CELL.SINGLE_H[7]CELL.DOUBLE_IO_W1[3]!MAIN[4][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W0[0]!MAIN[8][5]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W1[0]!MAIN[5][5]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W2[0]!MAIN[2][5]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W0[3]!MAIN[5][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W1[3]!MAIN[3][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W2[3]!MAIN[1][9]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W0[1]!MAIN[14][9]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W1[1]!MAIN[12][9]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W2[1]!MAIN[10][9]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W0[2]!MAIN[11][5]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W1[2]!MAIN[10][3]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W2[2]!MAIN[9][4]
CELL.DOUBLE_IO_W0[0]CELL.DOUBLE_IO_W2[0]!MAIN[3][5]
CELL.DOUBLE_IO_W0[1]CELL.DOUBLE_IO_W2[1]!MAIN[11][9]
CELL.DOUBLE_IO_W0[2]CELL.DOUBLE_IO_W2[2]!MAIN[10][4]
CELL.DOUBLE_IO_W0[3]CELL.DOUBLE_IO_W2[3]!MAIN[2][9]
spartanxl IO_W0 switchbox INT muxes DBUF_IO_V[0]
BitsDestination
MAIN[1][2]MAIN[3][2]MAIN[4][3]MAIN[3][3]CELL.DBUF_IO_V[0]
Source
0011CELL.DOUBLE_IO_W0[1]
0101CELL.DOUBLE_IO_W0[2]
0110CELL.DOUBLE_IO_W0[3]
1111CELL.DOUBLE_IO_W0[0]
spartanxl IO_W0 switchbox INT muxes DBUF_IO_V[1]
BitsDestination
MAIN[14][8]MAIN[17][8]MAIN[18][8]MAIN[15][8]CELL.DBUF_IO_V[1]
Source
0011CELL.DOUBLE_IO_W2[0]
0101CELL.DOUBLE_IO_W2[1]
0110CELL.DOUBLE_IO_W2[3]
1111CELL.DOUBLE_IO_W2[2]
spartanxl IO_W0 switchbox INT muxes LONG_H[0]
BitsDestination
MAIN[1][1]MAIN[0][1]MAIN[0][0]CELL.LONG_H[0]
Source
000CELL.LONG_IO_V[0]
011CELL.OUT_IO_WE_I2[1]
111off
spartanxl IO_W0 switchbox INT muxes LONG_H[1]
BitsDestination
MAIN[15][1]MAIN[15][0]MAIN[14][1]CELL.LONG_H[1]
Source
000CELL.LONG_IO_V[1]
011CELL.OUT_IO_WE_I2[1]
111off
spartanxl IO_W0 switchbox INT muxes LONG_H[4]
BitsDestination
MAIN[1][6]MAIN[3][7]MAIN[0][6]CELL.LONG_H[4]
Source
000CELL.LONG_IO_V[2]
011CELL.OUT_IO_WE_I2[0]
111off
spartanxl IO_W0 switchbox INT muxes LONG_H[5]
BitsDestination
MAIN[10][7]MAIN[6][7]MAIN[4][6]CELL.LONG_H[5]
Source
000CELL.LONG_IO_V[3]
011CELL.OUT_IO_WE_I2[0]
111off
spartanxl IO_W0 switchbox INT muxes LONG_IO_V[0]
BitsDestination
MAIN[4][5]MAIN[1][5]CELL.LONG_IO_V[0]
Source
00CELL.LONG_H[0]
01CELL.SINGLE_H[1]
11off
spartanxl IO_W0 switchbox INT muxes LONG_IO_V[1]
BitsDestination
MAIN[13][8]MAIN[11][8]MAIN[12][8]MAIN[17][9]CELL.LONG_IO_V[1]
Source
0001CELL.LONG_H[1]
0010CELL.LONG_H_BUF[3]
0111CELL.SINGLE_H[2]
1111off
spartanxl IO_W0 switchbox INT muxes LONG_IO_V[2]
BitsDestination
MAIN[5][8]MAIN[2][8]MAIN[3][8]MAIN[4][8]CELL.LONG_IO_V[2]
Source
0001CELL.LONG_H[4]
0010CELL.LONG_H_BUF[2]
0111CELL.SINGLE_H[5]
1111off
spartanxl IO_W0 switchbox INT muxes LONG_IO_V[3]
BitsDestination
MAIN[6][8]MAIN[9][8]CELL.LONG_IO_V[3]
Source
00CELL.LONG_H[5]
01CELL.SINGLE_H[6]
11off
spartanxl IO_W0 switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[2][1]MAIN[2][0]MAIN[4][1]MAIN[4][0]MAIN[3][0]CELL.IMUX_TBUF_I[0]
Source
00011CELL.OUT_IO_WE_I2[0]
00101CELL.DOUBLE_IO_W1[2]
00110CELL.LONG_IO_V[2]
01111CELL.DOUBLE_IO_W0[2]
10011CELL.DOUBLE_IO_W0[3]
10101CELL.DOUBLE_IO_W1[3]
10110CELL.OUT_IO_WE_I2[1]
11111CELL.TIE_0
spartanxl IO_W0 switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[11][1]MAIN[13][0]MAIN[13][1]MAIN[11][0]MAIN[12][0]MAIN[12][1]CELL.IMUX_TBUF_I[1]
Source
000111CELL.DOUBLE_IO_W0[2]
001011CELL.OUT_IO_WE_I2[0]
001101CELL.LONG_IO_V[1]
010111CELL.DOUBLE_IO_W1[3]
011011CELL.DOUBLE_IO_W0[3]
011110CELL.OUT_IO_WE_I2[1]
101111CELL.DOUBLE_IO_W1[2]
111111CELL.TIE_0
spartanxl IO_W0 switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[5][1]MAIN[6][0]MAIN[5][0]MAIN[8][0]MAIN[6][1]CELL.IMUX_TBUF_T[0]
Source
00011CELL.TIE_1
00111CELL.TIE_0
01001CELL.DOUBLE_IO_W0[1]
01010CELL.LONG_IO_V[3]
01101CELL.DOUBLE_IO_W1[1]
01110CELL.LONG_IO_V[2]
11011CELL.DOUBLE_IO_W0[0]
11111CELL.DOUBLE_IO_W1[0]
spartanxl IO_W0 switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[7][1]MAIN[8][1]MAIN[10][1]MAIN[10][0]MAIN[9][0]CELL.IMUX_TBUF_T[1]
Source
00011CELL.TIE_1
00111CELL.TIE_0
01001CELL.DOUBLE_IO_W1[0]
01010CELL.LONG_IO_V[2]
01101CELL.DOUBLE_IO_W0[0]
01110CELL.LONG_IO_V[3]
11011CELL.DOUBLE_IO_W1[1]
11111CELL.DOUBLE_IO_W0[1]
spartanxl IO_W0 switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[16][8]MAIN[19][8]MAIN[20][9]MAIN[19][9]MAIN[20][8]MAIN[18][9]CELL.IMUX_IO_O1[0]
Source
001111CELL.DOUBLE_H0[0]
011011CELL.LONG_H[4]
011101CELL.LONG_H[5]
011110CELL.LONG_H_BUF[3]
110111CELL.DOUBLE_H1[1]
111111CELL.TIE_0
spartanxl IO_W0 switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[16][1]MAIN[20][0]MAIN[19][0]MAIN[18][0]CELL.IMUX_IO_O1[1]
Source
0001CELL.LONG_H[0]
0010CELL.LONG_H[1]
0101CELL_S.DOUBLE_H0[1]
0110CELL.LONG_H_BUF[2]
1011CELL_S.DOUBLE_H1[0]
1111CELL.TIE_0
spartanxl IO_W0 switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[9][6]MAIN[17][5]MAIN[18][6]MAIN[12][6]MAIN[15][6]MAIN[14][6]MAIN[11][6]MAIN[16][6]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_H[3]
01011111CELL.SINGLE_H[4]
01101111CELL.SINGLE_H[5]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[2]
spartanxl IO_W0 switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[11][2]MAIN[18][2]MAIN[17][2]MAIN[13][2]MAIN[19][2]MAIN[12][2]MAIN[16][2]MAIN[20][2]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[2]
01111101CELL_S.SINGLE_H[4]
01111110CELL_S.SINGLE_H[5]
11111111CELL_S.SINGLE_H[3]
spartanxl IO_W0 switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[13][7]MAIN[20][7]MAIN[14][7]MAIN[16][7]MAIN[18][7]MAIN[17][7]MAIN[15][7]MAIN[19][7]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_H[2]
01011111CELL.SINGLE_H[3]
01101111CELL.SINGLE_H[5]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[4]
spartanxl IO_W0 switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[14][3]MAIN[18][1]MAIN[18][3]MAIN[14][2]MAIN[19][1]MAIN[17][1]MAIN[20][1]MAIN[15][2]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[2]
01111101CELL_S.SINGLE_H[3]
01111110CELL_S.SINGLE_H[4]
11111111CELL_S.SINGLE_H[5]
spartanxl IO_W0 switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[1][3]MAIN[4][2]MAIN[7][4]MAIN[2][3]MAIN[6][2]MAIN[6][3]MAIN[5][2]MAIN[5][3]CELL.IMUX_IO_T[0]
Source
00011111CELL.TIE_0
00100111CELL.LONG_IO_V[3]
00101011CELL.LONG_IO_V[0]
00110101CELL.LONG_IO_V[1]
00110110CELL.GCLK[0]
01101111CELL.DOUBLE_IO_W0[1]
01111101CELL.LONG_IO_V[2]
10110111CELL.DOUBLE_IO_W1[0]
10111011CELL.DOUBLE_IO_W1[1]
11111111CELL.DOUBLE_IO_W0[0]
spartanxl IO_W0 switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[2][2]MAIN[0][2]MAIN[7][2]MAIN[8][3]MAIN[9][3]MAIN[11][3]MAIN[9][2]MAIN[10][2]CELL.IMUX_IO_T[1]
Source
00011111CELL.TIE_0
00101101CELL.LONG_IO_V[0]
00110011CELL.DOUBLE_IO_W0[1]
00110101CELL.LONG_IO_V[2]
01101111CELL.DOUBLE_IO_W0[0]
01110111CELL.DOUBLE_IO_W1[1]
10111011CELL.LONG_IO_V[1]
10111101CELL.LONG_IO_V[3]
10111110CELL.GCLK[0]
11111111CELL.DOUBLE_IO_W1[0]

Bels TBUF

spartanxl IO_W0 bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
spartanxl IO_W0 bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[0][3]!MAIN[12][3]

Bels IO

spartanxl IO_W0 bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[23][6]CELL.IMUX_IO_IK[1] invert by !MAIN[23][3]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[24][9]CELL.IMUX_IO_OK[1] invert by !MAIN[23][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_G3_WCELL.IMUX_CLB_F3_W
TinCELL.IMUX_IO_T[0] invert by !MAIN[25][9]CELL.IMUX_IO_T[1] invert by !MAIN[24][0]
I1outCELL.OUT_IO_WE_I1[0]CELL.OUT_IO_WE_I1[1]
I2outCELL.OUT_IO_WE_I2[0]CELL.OUT_IO_WE_I2[1]
spartanxl IO_W0 bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[22][6]!MAIN[16][3]
OFF_SRVAL bit 0!MAIN[24][7]!MAIN[24][1]
READBACK_I1 bit 0!MAIN[25][8]!MAIN[21][3]
READBACK_I2 bit 0!MAIN[23][8]!MAIN[22][3]
READBACK_OQ bit 0!MAIN[22][8]!MAIN[23][2]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[22][7]!MAIN[24][2]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[21][7]MAIN[22][2]
IFF_CE_ENABLE!MAIN[7][8]!MAIN[7][7]
OFF_CE_ENABLE!MAIN[7][9]!MAIN[7][6]
SYNC_D[enum: IO_SYNC_D][enum: IO_SYNC_D]
IFF_CE_ENABLE_NO_IQ!MAIN[20][6]!MAIN[21][4]
MUX_T[enum: IO_MUX_T][enum: IO_MUX_T]
DRIVE[enum: IO_DRIVE][enum: IO_DRIVE]
_5V_TOLERANTMAIN[19][5]MAIN[20][4]
spartanxl IO_W0 enum IO_SLEW
IO[0].SLEWMAIN[23][9]
IO[1].SLEWMAIN[25][0]
FAST0
SLOW1
spartanxl IO_W0 enum IO_PULL
IO[0].PULLMAIN[17][6]MAIN[23][7]
IO[1].PULLMAIN[25][1]MAIN[23][1]
NONE11
PULLUP01
PULLDOWN10
spartanxl IO_W0 enum IO_MUX_I
IO[0].MUX_I1MAIN[23][5]MAIN[22][5]
IO[1].MUX_I1MAIN[25][4]MAIN[22][4]
IO[0].MUX_I2MAIN[25][5]MAIN[24][6]
IO[1].MUX_I2MAIN[24][4]MAIN[24][3]
I01
IQ11
IQL10
spartanxl IO_W0 enum IO_IFF_D
IO[0].IFF_DMAIN[24][5]MAIN[25][6]
IO[1].IFF_DMAIN[23][4]MAIN[25][3]
I11
DELAY00
MEDDELAY01
SYNC10
spartanxl IO_W0 enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[25][7]
IO[1].MUX_OFF_DMAIN[25][2]
O11
O20
spartanxl IO_W0 enum IO_MUX_O
IO[0].MUX_OMAIN[24][8]MAIN[21][8]MAIN[22][9]MAIN[21][9]
IO[1].MUX_OMAIN[22][1]MAIN[21][1]MAIN[22][0]MAIN[21][0]
O10000
O1_INV0001
O20111
O2_INV1111
OQ0010
MUX1011
spartanxl IO_W0 enum IO_SYNC_D
IO[0].SYNC_DMAIN[21][6]
IO[1].SYNC_DMAIN[21][2]
I1
DELAY0
spartanxl IO_W0 enum IO_MUX_T
IO[0].MUX_TMAIN[21][5]
IO[1].MUX_TMAIN[19][4]
T1
TQ0
spartanxl IO_W0 enum IO_DRIVE
IO[0].DRIVEMAIN[19][6]
IO[1].DRIVEMAIN[20][3]
_121
_240

Bels PULLUP

spartanxl IO_W0 bel PULLUP pins
PinDirectionPULLUP_TBUF[0]PULLUP_TBUF[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
spartanxl IO_W0 bel PULLUP attribute bits
AttributePULLUP_TBUF[0]PULLUP_TBUF[1]
ENABLE!MAIN_S[0][7]!MAIN[11][7]

Bel wires

spartanxl IO_W0 bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]TBUF[1].O, PULLUP_TBUF[1].O
CELL.IMUX_CLB_F3_WIO[1].O2
CELL.IMUX_CLB_G3_WIO[0].O2
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_WE_I1[0]IO[0].I1
CELL.OUT_IO_WE_I1[1]IO[1].I1
CELL.OUT_IO_WE_I2[0]IO[0].I2
CELL.OUT_IO_WE_I2[1]IO[1].I2

Bitstream

spartanxl IO_W0 rect MAIN
BitFrame
F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 IO[0]: !invert T IO[0]: !invert OK IO[0]: SLEW bit 0 IO[0]: MUX_O bit 1 IO[0]: MUX_O bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.LONG_IO_V[1] bit 0 - INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.DOUBLE_IO_W0[1] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W2[1] - IO[0]: ! OFF_CE_ENABLE INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_W0[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W0[3] INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_W1[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W1[3] INT: !bipass CELL.DOUBLE_IO_W0[3] = CELL.DOUBLE_IO_W2[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W2[3] INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_W2[3]
B8 IO[0]: ! READBACK_I1 bit 0 IO[0]: MUX_O bit 3 IO[0]: ! READBACK_I2 bit 0 IO[0]: ! READBACK_OQ bit 0 IO[0]: MUX_O bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.DBUF_IO_V[1] bit 1 INT: mux CELL.DBUF_IO_V[1] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 5 INT: mux CELL.DBUF_IO_V[1] bit 0 INT: mux CELL.DBUF_IO_V[1] bit 3 INT: mux CELL.LONG_IO_V[1] bit 3 INT: mux CELL.LONG_IO_V[1] bit 1 INT: mux CELL.LONG_IO_V[1] bit 2 INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1 INT: mux CELL.LONG_IO_V[3] bit 0 INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_IO_V[3] IO[0]: ! IFF_CE_ENABLE INT: mux CELL.LONG_IO_V[3] bit 1 INT: mux CELL.LONG_IO_V[2] bit 3 INT: mux CELL.LONG_IO_V[2] bit 0 INT: mux CELL.LONG_IO_V[2] bit 1 INT: mux CELL.LONG_IO_V[2] bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_IO_WE_I1_S1
B7 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_SRVAL bit 0 IO[0]: PULL bit 0 IO[0]: ! OFF_D_INV IO[0]: OFF_USED INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 7 INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[1] PULLUP_TBUF[1]: ! ENABLE INT: mux CELL.LONG_H[5] bit 2 INT: !pass CELL.DOUBLE_IO_W2[1] ← CELL.DBUF_IO_V[0] INT: !pass CELL.DOUBLE_IO_W2[3] ← CELL.DBUF_IO_V[0] IO[1]: ! IFF_CE_ENABLE INT: mux CELL.LONG_H[5] bit 1 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0] INT: mux CELL.LONG_H[4] bit 1 INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1_S1 - -
B6 IO[0]: IFF_D bit 0 IO[0]: MUX_I2 bit 0 IO[0]: !invert IK IO[0]: ! IFF_SRVAL bit 0 IO[0]: SYNC_D bit 0 IO[0]: ! IFF_CE_ENABLE_NO_IQ IO[0]: DRIVE bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 5 IO[0]: PULL bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 2 - INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: !pass CELL.DOUBLE_IO_W0[1] ← CELL.DBUF_IO_V[1] INT: mux CELL.IMUX_IO_OK[0] bit 7 INT: !pass CELL.DOUBLE_IO_W2[2] ← CELL.DBUF_IO_V[0] IO[1]: ! OFF_CE_ENABLE INT: !pass CELL.DOUBLE_IO_W2[0] ← CELL.DBUF_IO_V[0] - INT: mux CELL.LONG_H[5] bit 0 INT: !pass CELL.DOUBLE_IO_W0[3] ← CELL.DBUF_IO_V[1] INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2[0] INT: mux CELL.LONG_H[4] bit 2 INT: mux CELL.LONG_H[4] bit 0
B5 IO[0]: MUX_I2 bit 1 IO[0]: IFF_D bit 1 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_T bit 0 - IO[0]: _5V_TOLERANT - INT: mux CELL.IMUX_IO_OK[0] bit 6 - - - - INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_W0[2] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W0[2] INT: !pass CELL.DOUBLE_IO_W0[0] ← CELL.DBUF_IO_V[1] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W0[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W0[0] - INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W1[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W1[0] INT: mux CELL.LONG_IO_V[0] bit 1 INT: !bipass CELL.DOUBLE_IO_W0[0] = CELL.DOUBLE_IO_W2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W2[0] INT: mux CELL.LONG_IO_V[0] bit 0 INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W2[0]
B4 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I2 bit 1 IO[1]: IFF_D bit 1 IO[1]: MUX_I1 bit 0 IO[1]: ! IFF_CE_ENABLE_NO_IQ IO[1]: _5V_TOLERANT IO[1]: MUX_T bit 0 - - - - - - INT: !pass CELL.DOUBLE_IO_W0[2] ← CELL.DBUF_IO_V[1] INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_W1[2] INT: !bipass CELL.DOUBLE_IO_W0[2] = CELL.DOUBLE_IO_W2[2] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W2[2] INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_W2[2] INT: mux CELL.IMUX_IO_T[0] bit 5 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_IO_V[2] INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[0] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_WE_I2_S1
B3 IO[1]: IFF_D bit 0 IO[1]: MUX_I2 bit 0 IO[1]: !invert IK IO[1]: ! READBACK_I2 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: DRIVE bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 5 - IO[1]: ! IFF_SRVAL bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 7 - TBUF[1]: ! DRIVE1 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W1[2] INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 4 - INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.DBUF_IO_V[0] bit 1 INT: mux CELL.DBUF_IO_V[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 7 TBUF[0]: ! DRIVE1
B2 IO[1]: MUX_OFF_D bit 0 IO[1]: ! OFF_D_INV IO[1]: ! READBACK_OQ bit 0 IO[1]: OFF_USED IO[1]: SYNC_D bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 7 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 1 - INT: mux CELL.IMUX_IO_T[1] bit 5 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 6 INT: mux CELL.DBUF_IO_V[0] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 7 INT: mux CELL.DBUF_IO_V[0] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 6
B1 IO[1]: PULL bit 1 IO[1]: ! OFF_SRVAL bit 0 IO[1]: PULL bit 0 IO[1]: MUX_O bit 3 IO[1]: MUX_O bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.LONG_H[1] bit 2 INT: mux CELL.LONG_H[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 5 INT: mux CELL.IMUX_TBUF_T[1] bit 2 - INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 - INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.LONG_H[0] bit 2 INT: mux CELL.LONG_H[0] bit 1
B0 IO[1]: SLEW bit 0 IO[1]: !invert T IO[1]: !invert OK IO[1]: MUX_O bit 1 IO[1]: MUX_O bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 0 - - INT: mux CELL.LONG_H[1] bit 1 - INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 1 - INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 3 - INT: mux CELL.LONG_H[0] bit 0
spartanxl IO_W0 rect MAIN_S
BitFrame
F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - PULLUP_TBUF[0]: ! ENABLE
B6 - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_W0_N

Cells: 4

Switchbox INT

spartanxl IO_W0_N switchbox INT permanent buffers
DestinationSource
CELL.LONG_H_BUF[2]CELL.LONG_H[2]
CELL.LONG_H_BUF[3]CELL.LONG_H[3]
spartanxl IO_W0_N switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I2_S1!MAIN[1][4]
CELL.SINGLE_H[1]CELL.LONG_IO_V[0]!MAIN[3][4]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I2[0]!MAIN[4][4]
CELL.SINGLE_H[2]CELL.LONG_IO_V[1]!MAIN[12][7]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I1[0]!MAIN[4][7]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I1_S1!MAIN[10][8]
CELL.SINGLE_H[4]CELL.OUT_IO_WE_I2_S1!MAIN[0][4]
CELL.SINGLE_H[5]CELL.LONG_IO_V[2]!MAIN[6][4]
CELL.SINGLE_H[5]CELL.OUT_IO_WE_I2[0]!MAIN[5][4]
CELL.SINGLE_H[6]CELL.LONG_IO_V[3]!MAIN[8][8]
CELL.SINGLE_H[6]CELL.OUT_IO_WE_I1[0]!MAIN[1][8]
CELL.SINGLE_H[7]CELL.OUT_IO_WE_I1_S1!MAIN[0][8]
CELL.DOUBLE_H0[0]CELL.OUT_IO_WE_I1_S1!MAIN[2][7]
CELL.DOUBLE_H0[1]CELL.OUT_IO_WE_I2[0]!MAIN[2][6]
CELL.DOUBLE_H1[0]CELL.OUT_IO_WE_I1[0]!MAIN[5][7]
CELL.DOUBLE_H1[1]CELL.OUT_IO_WE_I2_S1!MAIN[2][4]
CELL.DOUBLE_IO_W0[0]CELL.DBUF_IO_V[1]!MAIN[10][5]
CELL.DOUBLE_IO_W0[1]CELL.DBUF_IO_V[1]!MAIN[10][6]
CELL.DOUBLE_IO_W0[2]CELL.DBUF_IO_V[1]!MAIN[12][4]
CELL.DOUBLE_IO_W0[3]CELL.DBUF_IO_V[1]!MAIN[3][6]
CELL.DOUBLE_IO_W2[0]CELL.DBUF_IO_V[0]!MAIN[6][6]
CELL.DOUBLE_IO_W2[1]CELL.DBUF_IO_V[0]!MAIN[9][7]
CELL.DOUBLE_IO_W2[2]CELL.DBUF_IO_V[0]!MAIN[8][6]
CELL.DOUBLE_IO_W2[3]CELL.DBUF_IO_V[0]!MAIN[8][7]
spartanxl IO_W0_N switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.DOUBLE_IO_W0[0]!MAIN[9][5]
CELL.SINGLE_H[0]CELL.DOUBLE_IO_W2[0]!MAIN[0][5]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_W1[0]!MAIN[6][5]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_W0[1]!MAIN[15][9]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_W2[1]!MAIN[9][9]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_W1[1]!MAIN[13][9]
CELL.SINGLE_H[4]CELL.DOUBLE_IO_W0[2]!MAIN[12][5]
CELL.SINGLE_H[4]CELL.DOUBLE_IO_W2[2]!MAIN[8][4]
CELL.SINGLE_H[5]CELL.DOUBLE_IO_W1[2]!MAIN[11][4]
CELL.SINGLE_H[6]CELL.DOUBLE_IO_W0[3]!MAIN[6][9]
CELL.SINGLE_H[6]CELL.DOUBLE_IO_W2[3]!MAIN[0][9]
CELL.SINGLE_H[7]CELL.DOUBLE_IO_W1[3]!MAIN[4][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W0[0]!MAIN[8][5]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W1[0]!MAIN[5][5]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W2[0]!MAIN[2][5]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W0[3]!MAIN[5][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W1[3]!MAIN[3][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W2[3]!MAIN[1][9]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W0[1]!MAIN[14][9]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W1[1]!MAIN[12][9]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W2[1]!MAIN[10][9]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W0[2]!MAIN[11][5]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W1[2]!MAIN[10][3]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W2[2]!MAIN[9][4]
CELL.DOUBLE_IO_W0[0]CELL.DOUBLE_IO_W2[0]!MAIN[3][5]
CELL.DOUBLE_IO_W0[1]CELL.DOUBLE_IO_W2[1]!MAIN[11][9]
CELL.DOUBLE_IO_W0[2]CELL.DOUBLE_IO_W2[2]!MAIN[10][4]
CELL.DOUBLE_IO_W0[3]CELL.DOUBLE_IO_W2[3]!MAIN[2][9]
spartanxl IO_W0_N switchbox INT muxes DBUF_IO_V[0]
BitsDestination
MAIN[1][2]MAIN[3][2]MAIN[4][3]MAIN[3][3]CELL.DBUF_IO_V[0]
Source
0011CELL.DOUBLE_IO_W0[1]
0101CELL.DOUBLE_IO_W0[2]
0110CELL.DOUBLE_IO_W0[3]
1111CELL.DOUBLE_IO_W0[0]
spartanxl IO_W0_N switchbox INT muxes DBUF_IO_V[1]
BitsDestination
MAIN[14][8]MAIN[17][8]MAIN[18][8]MAIN[15][8]CELL.DBUF_IO_V[1]
Source
0011CELL.DOUBLE_IO_W2[0]
0101CELL.DOUBLE_IO_W2[1]
0110CELL.DOUBLE_IO_W2[3]
1111CELL.DOUBLE_IO_W2[2]
spartanxl IO_W0_N switchbox INT muxes LONG_H[0]
BitsDestination
MAIN[1][1]MAIN[0][1]MAIN[0][0]CELL.LONG_H[0]
Source
000CELL.LONG_IO_V[0]
011CELL.OUT_IO_WE_I2[1]
111off
spartanxl IO_W0_N switchbox INT muxes LONG_H[1]
BitsDestination
MAIN[15][1]MAIN[15][0]MAIN[14][1]CELL.LONG_H[1]
Source
000CELL.LONG_IO_V[1]
011CELL.OUT_IO_WE_I2[1]
111off
spartanxl IO_W0_N switchbox INT muxes LONG_H[4]
BitsDestination
MAIN[1][6]MAIN[3][7]MAIN[0][6]CELL.LONG_H[4]
Source
000CELL.LONG_IO_V[2]
011CELL.OUT_IO_WE_I2[0]
111off
spartanxl IO_W0_N switchbox INT muxes LONG_H[5]
BitsDestination
MAIN[10][7]MAIN[6][7]MAIN[4][6]CELL.LONG_H[5]
Source
000CELL.LONG_IO_V[3]
011CELL.OUT_IO_WE_I2[0]
111off
spartanxl IO_W0_N switchbox INT muxes LONG_IO_V[0]
BitsDestination
MAIN[4][5]MAIN[1][5]CELL.LONG_IO_V[0]
Source
00CELL.LONG_H[0]
01CELL.SINGLE_H[1]
11off
spartanxl IO_W0_N switchbox INT muxes LONG_IO_V[1]
BitsDestination
MAIN[13][8]MAIN[11][8]MAIN[12][8]MAIN[17][9]CELL.LONG_IO_V[1]
Source
0001CELL.LONG_H[1]
0010CELL.LONG_H_BUF[3]
0111CELL.SINGLE_H[2]
1111off
spartanxl IO_W0_N switchbox INT muxes LONG_IO_V[2]
BitsDestination
MAIN[5][8]MAIN[2][8]MAIN[3][8]MAIN[4][8]CELL.LONG_IO_V[2]
Source
0001CELL.LONG_H[4]
0010CELL.LONG_H_BUF[2]
0111CELL.SINGLE_H[5]
1111off
spartanxl IO_W0_N switchbox INT muxes LONG_IO_V[3]
BitsDestination
MAIN[6][8]MAIN[9][8]CELL.LONG_IO_V[3]
Source
00CELL.LONG_H[5]
01CELL.SINGLE_H[6]
11off
spartanxl IO_W0_N switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[2][1]MAIN[2][0]MAIN[4][1]MAIN[4][0]MAIN[3][0]CELL.IMUX_TBUF_I[0]
Source
00011CELL.OUT_IO_WE_I2[0]
00101CELL.DOUBLE_IO_W1[2]
00110CELL.LONG_IO_V[2]
01111CELL.DOUBLE_IO_W0[2]
10011CELL.DOUBLE_IO_W0[3]
10101CELL.DOUBLE_IO_W1[3]
10110CELL.OUT_IO_WE_I2[1]
11111CELL.TIE_0
spartanxl IO_W0_N switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[11][1]MAIN[13][0]MAIN[13][1]MAIN[11][0]MAIN[12][0]MAIN[12][1]CELL.IMUX_TBUF_I[1]
Source
000111CELL.DOUBLE_IO_W0[2]
001011CELL.OUT_IO_WE_I2[0]
001101CELL.LONG_IO_V[1]
010111CELL.DOUBLE_IO_W1[3]
011011CELL.DOUBLE_IO_W0[3]
011110CELL.OUT_IO_WE_I2[1]
101111CELL.DOUBLE_IO_W1[2]
111111CELL.TIE_0
spartanxl IO_W0_N switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[5][1]MAIN[6][0]MAIN[5][0]MAIN[8][0]MAIN[6][1]CELL.IMUX_TBUF_T[0]
Source
00011CELL.TIE_1
00111CELL.TIE_0
01001CELL.DOUBLE_IO_W0[1]
01010CELL.LONG_IO_V[3]
01101CELL.DOUBLE_IO_W1[1]
01110CELL.LONG_IO_V[2]
11011CELL.DOUBLE_IO_W0[0]
11111CELL.DOUBLE_IO_W1[0]
spartanxl IO_W0_N switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[7][1]MAIN[8][1]MAIN[10][1]MAIN[10][0]MAIN[9][0]CELL.IMUX_TBUF_T[1]
Source
00011CELL.TIE_1
00111CELL.TIE_0
01001CELL.DOUBLE_IO_W1[0]
01010CELL.LONG_IO_V[2]
01101CELL.DOUBLE_IO_W0[0]
01110CELL.LONG_IO_V[3]
11011CELL.DOUBLE_IO_W1[1]
11111CELL.DOUBLE_IO_W0[1]
spartanxl IO_W0_N switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[16][8]MAIN[19][8]MAIN[20][9]MAIN[19][9]MAIN[20][8]MAIN[18][9]CELL.IMUX_IO_O1[0]
Source
001111CELL.DOUBLE_H0[0]
011011CELL.LONG_H[4]
011101CELL.LONG_H[5]
011110CELL.LONG_H_BUF[3]
110111CELL.DOUBLE_H1[1]
111111CELL.TIE_0
spartanxl IO_W0_N switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[16][1]MAIN[20][0]MAIN[19][0]MAIN[18][0]CELL.IMUX_IO_O1[1]
Source
0001CELL.LONG_H[0]
0010CELL.LONG_H[1]
0101CELL_S.DOUBLE_H0[1]
0110CELL.LONG_H_BUF[2]
1011CELL_S.DOUBLE_H1[0]
1111CELL.TIE_0
spartanxl IO_W0_N switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[9][6]MAIN[17][5]MAIN[18][6]MAIN[12][6]MAIN[15][6]MAIN[14][6]MAIN[11][6]MAIN[16][6]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_H[3]
01011111CELL.SINGLE_H[4]
01101111CELL.SINGLE_H[5]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[2]
spartanxl IO_W0_N switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[11][2]MAIN[18][2]MAIN[17][2]MAIN[13][2]MAIN[19][2]MAIN[12][2]MAIN[16][2]MAIN[20][2]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[2]
01111101CELL_S.SINGLE_H[4]
01111110CELL_S.SINGLE_H[5]
11111111CELL_S.SINGLE_H[3]
spartanxl IO_W0_N switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[13][7]MAIN[20][7]MAIN[14][7]MAIN[16][7]MAIN[18][7]MAIN[17][7]MAIN[15][7]MAIN[19][7]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_H[2]
01011111CELL.SINGLE_H[3]
01101111CELL.SINGLE_H[5]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[4]
spartanxl IO_W0_N switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[14][3]MAIN[18][1]MAIN[18][3]MAIN[14][2]MAIN[19][1]MAIN[17][1]MAIN[20][1]MAIN[15][2]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[2]
01111101CELL_S.SINGLE_H[3]
01111110CELL_S.SINGLE_H[4]
11111111CELL_S.SINGLE_H[5]
spartanxl IO_W0_N switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[1][3]MAIN[4][2]MAIN[7][4]MAIN[2][3]MAIN[6][2]MAIN[6][3]MAIN[5][2]MAIN[5][3]CELL.IMUX_IO_T[0]
Source
00011111CELL.TIE_0
00100111CELL.LONG_IO_V[3]
00101011CELL.LONG_IO_V[0]
00110101CELL.LONG_IO_V[1]
00110110CELL.GCLK[0]
01101111CELL.DOUBLE_IO_W0[1]
01111101CELL.LONG_IO_V[2]
10110111CELL.DOUBLE_IO_W1[0]
10111011CELL.DOUBLE_IO_W1[1]
11111111CELL.DOUBLE_IO_W0[0]
spartanxl IO_W0_N switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[2][2]MAIN[0][2]MAIN[7][2]MAIN[8][3]MAIN[9][3]MAIN[11][3]MAIN[9][2]MAIN[10][2]CELL.IMUX_IO_T[1]
Source
00011111CELL.TIE_0
00101101CELL.LONG_IO_V[0]
00110011CELL.DOUBLE_IO_W0[1]
00110101CELL.LONG_IO_V[2]
01101111CELL.DOUBLE_IO_W0[0]
01110111CELL.DOUBLE_IO_W1[1]
10111011CELL.LONG_IO_V[1]
10111101CELL.LONG_IO_V[3]
10111110CELL.GCLK[0]
11111111CELL.DOUBLE_IO_W1[0]

Bels TBUF

spartanxl IO_W0_N bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
spartanxl IO_W0_N bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[0][3]!MAIN[12][3]

Bels IO

spartanxl IO_W0_N bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[23][6]CELL.IMUX_IO_IK[1] invert by !MAIN[23][3]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[24][9]CELL.IMUX_IO_OK[1] invert by !MAIN[23][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_G3_WCELL.IMUX_CLB_F3_W
TinCELL.IMUX_IO_T[0] invert by !MAIN[25][9]CELL.IMUX_IO_T[1] invert by !MAIN[24][0]
I1outCELL.OUT_IO_WE_I1[0]CELL.OUT_IO_WE_I1[1]
I2outCELL.OUT_IO_WE_I2[0]CELL.OUT_IO_WE_I2[1]
CLKINoutCELL.OUT_IO_CLKIN-
spartanxl IO_W0_N bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[22][6]!MAIN[16][3]
OFF_SRVAL bit 0!MAIN[24][7]!MAIN[24][1]
READBACK_I1 bit 0!MAIN[25][8]!MAIN[21][3]
READBACK_I2 bit 0!MAIN[23][8]!MAIN[22][3]
READBACK_OQ bit 0!MAIN[22][8]!MAIN[23][2]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[22][7]!MAIN[24][2]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[21][7]MAIN[22][2]
IFF_CE_ENABLE!MAIN[7][8]!MAIN[7][7]
OFF_CE_ENABLE!MAIN[7][9]!MAIN[7][6]
SYNC_D[enum: IO_SYNC_D][enum: IO_SYNC_D]
IFF_CE_ENABLE_NO_IQ!MAIN[20][6]!MAIN[21][4]
MUX_T[enum: IO_MUX_T][enum: IO_MUX_T]
DRIVE[enum: IO_DRIVE][enum: IO_DRIVE]
_5V_TOLERANTMAIN[19][5]MAIN[20][4]
spartanxl IO_W0_N enum IO_SLEW
IO[0].SLEWMAIN[23][9]
IO[1].SLEWMAIN[25][0]
FAST0
SLOW1
spartanxl IO_W0_N enum IO_PULL
IO[0].PULLMAIN[17][6]MAIN[23][7]
IO[1].PULLMAIN[25][1]MAIN[23][1]
NONE11
PULLUP01
PULLDOWN10
spartanxl IO_W0_N enum IO_MUX_I
IO[0].MUX_I1MAIN[23][5]MAIN[22][5]
IO[1].MUX_I1MAIN[25][4]MAIN[22][4]
IO[0].MUX_I2MAIN[25][5]MAIN[24][6]
IO[1].MUX_I2MAIN[24][4]MAIN[24][3]
I01
IQ11
IQL10
spartanxl IO_W0_N enum IO_IFF_D
IO[0].IFF_DMAIN[24][5]MAIN[25][6]
IO[1].IFF_DMAIN[23][4]MAIN[25][3]
I11
DELAY00
MEDDELAY01
SYNC10
spartanxl IO_W0_N enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[25][7]
IO[1].MUX_OFF_DMAIN[25][2]
O11
O20
spartanxl IO_W0_N enum IO_MUX_O
IO[0].MUX_OMAIN[24][8]MAIN[21][8]MAIN[22][9]MAIN[21][9]
IO[1].MUX_OMAIN[22][1]MAIN[21][1]MAIN[22][0]MAIN[21][0]
O10000
O1_INV0001
O20111
O2_INV1111
OQ0010
MUX1011
spartanxl IO_W0_N enum IO_SYNC_D
IO[0].SYNC_DMAIN[21][6]
IO[1].SYNC_DMAIN[21][2]
I1
DELAY0
spartanxl IO_W0_N enum IO_MUX_T
IO[0].MUX_TMAIN[21][5]
IO[1].MUX_TMAIN[19][4]
T1
TQ0
spartanxl IO_W0_N enum IO_DRIVE
IO[0].DRIVEMAIN[19][6]
IO[1].DRIVEMAIN[20][3]
_121
_240

Bels PULLUP

spartanxl IO_W0_N bel PULLUP pins
PinDirectionPULLUP_TBUF[0]PULLUP_TBUF[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
spartanxl IO_W0_N bel PULLUP attribute bits
AttributePULLUP_TBUF[0]PULLUP_TBUF[1]
ENABLE!MAIN_S[0][7]!MAIN[11][7]

Bel wires

spartanxl IO_W0_N bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]TBUF[1].O, PULLUP_TBUF[1].O
CELL.IMUX_CLB_F3_WIO[1].O2
CELL.IMUX_CLB_G3_WIO[0].O2
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_WE_I1[0]IO[0].I1
CELL.OUT_IO_WE_I1[1]IO[1].I1
CELL.OUT_IO_WE_I2[0]IO[0].I2
CELL.OUT_IO_WE_I2[1]IO[1].I2
CELL.OUT_IO_CLKINIO[0].CLKIN

Bitstream

spartanxl IO_W0_N rect MAIN
BitFrame
F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 IO[0]: !invert T IO[0]: !invert OK IO[0]: SLEW bit 0 IO[0]: MUX_O bit 1 IO[0]: MUX_O bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.LONG_IO_V[1] bit 0 - INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.DOUBLE_IO_W0[1] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W2[1] - IO[0]: ! OFF_CE_ENABLE INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_W0[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W0[3] INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_W1[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W1[3] INT: !bipass CELL.DOUBLE_IO_W0[3] = CELL.DOUBLE_IO_W2[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W2[3] INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_W2[3]
B8 IO[0]: ! READBACK_I1 bit 0 IO[0]: MUX_O bit 3 IO[0]: ! READBACK_I2 bit 0 IO[0]: ! READBACK_OQ bit 0 IO[0]: MUX_O bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.DBUF_IO_V[1] bit 1 INT: mux CELL.DBUF_IO_V[1] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 5 INT: mux CELL.DBUF_IO_V[1] bit 0 INT: mux CELL.DBUF_IO_V[1] bit 3 INT: mux CELL.LONG_IO_V[1] bit 3 INT: mux CELL.LONG_IO_V[1] bit 1 INT: mux CELL.LONG_IO_V[1] bit 2 INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1 INT: mux CELL.LONG_IO_V[3] bit 0 INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_IO_V[3] IO[0]: ! IFF_CE_ENABLE INT: mux CELL.LONG_IO_V[3] bit 1 INT: mux CELL.LONG_IO_V[2] bit 3 INT: mux CELL.LONG_IO_V[2] bit 0 INT: mux CELL.LONG_IO_V[2] bit 1 INT: mux CELL.LONG_IO_V[2] bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_IO_WE_I1_S1
B7 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_SRVAL bit 0 IO[0]: PULL bit 0 IO[0]: ! OFF_D_INV IO[0]: OFF_USED INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 7 INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[1] PULLUP_TBUF[1]: ! ENABLE INT: mux CELL.LONG_H[5] bit 2 INT: !pass CELL.DOUBLE_IO_W2[1] ← CELL.DBUF_IO_V[0] INT: !pass CELL.DOUBLE_IO_W2[3] ← CELL.DBUF_IO_V[0] IO[1]: ! IFF_CE_ENABLE INT: mux CELL.LONG_H[5] bit 1 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0] INT: mux CELL.LONG_H[4] bit 1 INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1_S1 - -
B6 IO[0]: IFF_D bit 0 IO[0]: MUX_I2 bit 0 IO[0]: !invert IK IO[0]: ! IFF_SRVAL bit 0 IO[0]: SYNC_D bit 0 IO[0]: ! IFF_CE_ENABLE_NO_IQ IO[0]: DRIVE bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 5 IO[0]: PULL bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 2 - INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: !pass CELL.DOUBLE_IO_W0[1] ← CELL.DBUF_IO_V[1] INT: mux CELL.IMUX_IO_OK[0] bit 7 INT: !pass CELL.DOUBLE_IO_W2[2] ← CELL.DBUF_IO_V[0] IO[1]: ! OFF_CE_ENABLE INT: !pass CELL.DOUBLE_IO_W2[0] ← CELL.DBUF_IO_V[0] - INT: mux CELL.LONG_H[5] bit 0 INT: !pass CELL.DOUBLE_IO_W0[3] ← CELL.DBUF_IO_V[1] INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2[0] INT: mux CELL.LONG_H[4] bit 2 INT: mux CELL.LONG_H[4] bit 0
B5 IO[0]: MUX_I2 bit 1 IO[0]: IFF_D bit 1 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_T bit 0 - IO[0]: _5V_TOLERANT - INT: mux CELL.IMUX_IO_OK[0] bit 6 - - - - INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_W0[2] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W0[2] INT: !pass CELL.DOUBLE_IO_W0[0] ← CELL.DBUF_IO_V[1] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W0[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W0[0] - INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W1[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W1[0] INT: mux CELL.LONG_IO_V[0] bit 1 INT: !bipass CELL.DOUBLE_IO_W0[0] = CELL.DOUBLE_IO_W2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W2[0] INT: mux CELL.LONG_IO_V[0] bit 0 INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W2[0]
B4 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I2 bit 1 IO[1]: IFF_D bit 1 IO[1]: MUX_I1 bit 0 IO[1]: ! IFF_CE_ENABLE_NO_IQ IO[1]: _5V_TOLERANT IO[1]: MUX_T bit 0 - - - - - - INT: !pass CELL.DOUBLE_IO_W0[2] ← CELL.DBUF_IO_V[1] INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_W1[2] INT: !bipass CELL.DOUBLE_IO_W0[2] = CELL.DOUBLE_IO_W2[2] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W2[2] INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_W2[2] INT: mux CELL.IMUX_IO_T[0] bit 5 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_IO_V[2] INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[0] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_WE_I2_S1
B3 IO[1]: IFF_D bit 0 IO[1]: MUX_I2 bit 0 IO[1]: !invert IK IO[1]: ! READBACK_I2 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: DRIVE bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 5 - IO[1]: ! IFF_SRVAL bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 7 - TBUF[1]: ! DRIVE1 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W1[2] INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 4 - INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.DBUF_IO_V[0] bit 1 INT: mux CELL.DBUF_IO_V[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 7 TBUF[0]: ! DRIVE1
B2 IO[1]: MUX_OFF_D bit 0 IO[1]: ! OFF_D_INV IO[1]: ! READBACK_OQ bit 0 IO[1]: OFF_USED IO[1]: SYNC_D bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 7 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 1 - INT: mux CELL.IMUX_IO_T[1] bit 5 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 6 INT: mux CELL.DBUF_IO_V[0] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 7 INT: mux CELL.DBUF_IO_V[0] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 6
B1 IO[1]: PULL bit 1 IO[1]: ! OFF_SRVAL bit 0 IO[1]: PULL bit 0 IO[1]: MUX_O bit 3 IO[1]: MUX_O bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.LONG_H[1] bit 2 INT: mux CELL.LONG_H[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 5 INT: mux CELL.IMUX_TBUF_T[1] bit 2 - INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 - INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.LONG_H[0] bit 2 INT: mux CELL.LONG_H[0] bit 1
B0 IO[1]: SLEW bit 0 IO[1]: !invert T IO[1]: !invert OK IO[1]: MUX_O bit 1 IO[1]: MUX_O bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 0 - - INT: mux CELL.LONG_H[1] bit 1 - INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 1 - INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 3 - INT: mux CELL.LONG_H[0] bit 0
spartanxl IO_W0_N rect MAIN_S
BitFrame
F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - PULLUP_TBUF[0]: ! ENABLE
B6 - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_W1

Cells: 4

Switchbox INT

spartanxl IO_W1 switchbox INT permanent buffers
DestinationSource
CELL.LONG_H_BUF[2]CELL.LONG_H[2]
CELL.LONG_H_BUF[3]CELL.LONG_H[3]
spartanxl IO_W1 switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I2_S1!MAIN[1][4]
CELL.SINGLE_H[1]CELL.LONG_IO_V[0]!MAIN[3][4]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I2[0]!MAIN[4][4]
CELL.SINGLE_H[2]CELL.LONG_IO_V[1]!MAIN[12][7]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I1[0]!MAIN[4][7]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I1_S1!MAIN[10][8]
CELL.SINGLE_H[4]CELL.OUT_IO_WE_I2_S1!MAIN[0][4]
CELL.SINGLE_H[5]CELL.LONG_IO_V[2]!MAIN[6][4]
CELL.SINGLE_H[5]CELL.OUT_IO_WE_I2[0]!MAIN[5][4]
CELL.SINGLE_H[6]CELL.LONG_IO_V[3]!MAIN[8][8]
CELL.SINGLE_H[6]CELL.OUT_IO_WE_I1[0]!MAIN[1][8]
CELL.SINGLE_H[7]CELL.OUT_IO_WE_I1_S1!MAIN[0][8]
CELL.DOUBLE_H0[0]CELL.OUT_IO_WE_I1_S1!MAIN[2][7]
CELL.DOUBLE_H0[1]CELL.OUT_IO_WE_I2[0]!MAIN[2][6]
CELL.DOUBLE_H1[0]CELL.OUT_IO_WE_I1[0]!MAIN[5][7]
CELL.DOUBLE_H1[1]CELL.OUT_IO_WE_I2_S1!MAIN[2][4]
CELL.DOUBLE_IO_W0[0]CELL.DBUF_IO_V[1]!MAIN[10][5]
CELL.DOUBLE_IO_W0[1]CELL.DBUF_IO_V[1]!MAIN[10][6]
CELL.DOUBLE_IO_W0[2]CELL.DBUF_IO_V[1]!MAIN[12][4]
CELL.DOUBLE_IO_W0[3]CELL.DBUF_IO_V[1]!MAIN[3][6]
CELL.DOUBLE_IO_W2[0]CELL.DBUF_IO_V[0]!MAIN[6][6]
CELL.DOUBLE_IO_W2[1]CELL.DBUF_IO_V[0]!MAIN[9][7]
CELL.DOUBLE_IO_W2[2]CELL.DBUF_IO_V[0]!MAIN[8][6]
CELL.DOUBLE_IO_W2[3]CELL.DBUF_IO_V[0]!MAIN[8][7]
spartanxl IO_W1 switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.DOUBLE_IO_W1[0]!MAIN[6][5]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_W0[0]!MAIN[9][5]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_W2[0]!MAIN[0][5]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_W1[1]!MAIN[13][9]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_W0[1]!MAIN[15][9]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_W2[1]!MAIN[9][9]
CELL.SINGLE_H[4]CELL.DOUBLE_IO_W1[2]!MAIN[11][4]
CELL.SINGLE_H[5]CELL.DOUBLE_IO_W0[2]!MAIN[12][5]
CELL.SINGLE_H[5]CELL.DOUBLE_IO_W2[2]!MAIN[8][4]
CELL.SINGLE_H[6]CELL.DOUBLE_IO_W1[3]!MAIN[4][9]
CELL.SINGLE_H[7]CELL.DOUBLE_IO_W0[3]!MAIN[6][9]
CELL.SINGLE_H[7]CELL.DOUBLE_IO_W2[3]!MAIN[0][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W0[0]!MAIN[8][5]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W1[0]!MAIN[5][5]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W2[0]!MAIN[2][5]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W0[3]!MAIN[5][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W1[3]!MAIN[3][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W2[3]!MAIN[1][9]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W0[1]!MAIN[14][9]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W1[1]!MAIN[12][9]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W2[1]!MAIN[10][9]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W0[2]!MAIN[11][5]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W1[2]!MAIN[10][3]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W2[2]!MAIN[9][4]
CELL.DOUBLE_IO_W0[0]CELL.DOUBLE_IO_W2[0]!MAIN[3][5]
CELL.DOUBLE_IO_W0[1]CELL.DOUBLE_IO_W2[1]!MAIN[11][9]
CELL.DOUBLE_IO_W0[2]CELL.DOUBLE_IO_W2[2]!MAIN[10][4]
CELL.DOUBLE_IO_W0[3]CELL.DOUBLE_IO_W2[3]!MAIN[2][9]
spartanxl IO_W1 switchbox INT muxes DBUF_IO_V[0]
BitsDestination
MAIN[1][2]MAIN[3][2]MAIN[4][3]MAIN[3][3]CELL.DBUF_IO_V[0]
Source
0011CELL.DOUBLE_IO_W0[1]
0101CELL.DOUBLE_IO_W0[2]
0110CELL.DOUBLE_IO_W0[3]
1111CELL.DOUBLE_IO_W0[0]
spartanxl IO_W1 switchbox INT muxes DBUF_IO_V[1]
BitsDestination
MAIN[14][8]MAIN[17][8]MAIN[18][8]MAIN[15][8]CELL.DBUF_IO_V[1]
Source
0011CELL.DOUBLE_IO_W2[0]
0101CELL.DOUBLE_IO_W2[1]
0110CELL.DOUBLE_IO_W2[3]
1111CELL.DOUBLE_IO_W2[2]
spartanxl IO_W1 switchbox INT muxes LONG_H[0]
BitsDestination
MAIN[1][1]MAIN[0][1]MAIN[0][0]CELL.LONG_H[0]
Source
000CELL.LONG_IO_V[0]
011CELL.OUT_IO_WE_I2[1]
111off
spartanxl IO_W1 switchbox INT muxes LONG_H[1]
BitsDestination
MAIN[15][1]MAIN[15][0]MAIN[14][1]CELL.LONG_H[1]
Source
000CELL.LONG_IO_V[1]
011CELL.OUT_IO_WE_I2[1]
111off
spartanxl IO_W1 switchbox INT muxes LONG_H[4]
BitsDestination
MAIN[1][6]MAIN[3][7]MAIN[0][6]CELL.LONG_H[4]
Source
000CELL.LONG_IO_V[2]
011CELL.OUT_IO_WE_I2[0]
111off
spartanxl IO_W1 switchbox INT muxes LONG_H[5]
BitsDestination
MAIN[10][7]MAIN[6][7]MAIN[4][6]CELL.LONG_H[5]
Source
000CELL.LONG_IO_V[3]
011CELL.OUT_IO_WE_I2[0]
111off
spartanxl IO_W1 switchbox INT muxes LONG_IO_V[0]
BitsDestination
MAIN[4][5]MAIN[1][5]CELL.LONG_IO_V[0]
Source
00CELL.LONG_H[0]
01CELL.SINGLE_H[1]
11off
spartanxl IO_W1 switchbox INT muxes LONG_IO_V[1]
BitsDestination
MAIN[13][8]MAIN[11][8]MAIN[12][8]MAIN[17][9]CELL.LONG_IO_V[1]
Source
0001CELL.LONG_H[1]
0010CELL.LONG_H_BUF[3]
0111CELL.SINGLE_H[2]
1111off
spartanxl IO_W1 switchbox INT muxes LONG_IO_V[2]
BitsDestination
MAIN[5][8]MAIN[2][8]MAIN[3][8]MAIN[4][8]CELL.LONG_IO_V[2]
Source
0001CELL.LONG_H[4]
0010CELL.LONG_H_BUF[2]
0111CELL.SINGLE_H[5]
1111off
spartanxl IO_W1 switchbox INT muxes LONG_IO_V[3]
BitsDestination
MAIN[6][8]MAIN[9][8]CELL.LONG_IO_V[3]
Source
00CELL.LONG_H[5]
01CELL.SINGLE_H[6]
11off
spartanxl IO_W1 switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[2][1]MAIN[2][0]MAIN[4][1]MAIN[4][0]MAIN[3][0]CELL.IMUX_TBUF_I[0]
Source
00011CELL.OUT_IO_WE_I2[0]
00101CELL.DOUBLE_IO_W1[2]
00110CELL.LONG_IO_V[2]
01111CELL.DOUBLE_IO_W0[2]
10011CELL.DOUBLE_IO_W0[3]
10101CELL.DOUBLE_IO_W1[3]
10110CELL.OUT_IO_WE_I2[1]
11111CELL.TIE_0
spartanxl IO_W1 switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[11][1]MAIN[13][0]MAIN[13][1]MAIN[11][0]MAIN[12][0]MAIN[12][1]CELL.IMUX_TBUF_I[1]
Source
000111CELL.DOUBLE_IO_W0[2]
001011CELL.OUT_IO_WE_I2[0]
001101CELL.LONG_IO_V[1]
010111CELL.DOUBLE_IO_W1[3]
011011CELL.DOUBLE_IO_W0[3]
011110CELL.OUT_IO_WE_I2[1]
101111CELL.DOUBLE_IO_W1[2]
111111CELL.TIE_0
spartanxl IO_W1 switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[5][1]MAIN[6][0]MAIN[5][0]MAIN[8][0]MAIN[6][1]CELL.IMUX_TBUF_T[0]
Source
00011CELL.TIE_1
00111CELL.TIE_0
01001CELL.DOUBLE_IO_W0[1]
01010CELL.LONG_IO_V[3]
01101CELL.DOUBLE_IO_W1[1]
01110CELL.LONG_IO_V[2]
11011CELL.DOUBLE_IO_W0[0]
11111CELL.DOUBLE_IO_W1[0]
spartanxl IO_W1 switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[7][1]MAIN[8][1]MAIN[10][1]MAIN[10][0]MAIN[9][0]CELL.IMUX_TBUF_T[1]
Source
00011CELL.TIE_1
00111CELL.TIE_0
01001CELL.DOUBLE_IO_W1[0]
01010CELL.LONG_IO_V[2]
01101CELL.DOUBLE_IO_W0[0]
01110CELL.LONG_IO_V[3]
11011CELL.DOUBLE_IO_W1[1]
11111CELL.DOUBLE_IO_W0[1]
spartanxl IO_W1 switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[16][8]MAIN[19][8]MAIN[20][9]MAIN[19][9]MAIN[20][8]MAIN[18][9]CELL.IMUX_IO_O1[0]
Source
001111CELL.DOUBLE_H0[0]
011011CELL.LONG_H[4]
011101CELL.LONG_H[5]
011110CELL.LONG_H_BUF[3]
110111CELL.DOUBLE_H1[1]
111111CELL.TIE_0
spartanxl IO_W1 switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[16][1]MAIN[20][0]MAIN[19][0]MAIN[18][0]CELL.IMUX_IO_O1[1]
Source
0001CELL.LONG_H[0]
0010CELL.LONG_H[1]
0101CELL_S.DOUBLE_H0[1]
0110CELL.LONG_H_BUF[2]
1011CELL_S.DOUBLE_H1[0]
1111CELL.TIE_0
spartanxl IO_W1 switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[9][6]MAIN[17][5]MAIN[18][6]MAIN[12][6]MAIN[15][6]MAIN[14][6]MAIN[11][6]MAIN[16][6]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_H[3]
01011111CELL.SINGLE_H[4]
01101111CELL.SINGLE_H[5]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[2]
spartanxl IO_W1 switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[11][2]MAIN[18][2]MAIN[17][2]MAIN[13][2]MAIN[19][2]MAIN[12][2]MAIN[16][2]MAIN[20][2]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[2]
01111101CELL_S.SINGLE_H[4]
01111110CELL_S.SINGLE_H[5]
11111111CELL_S.SINGLE_H[3]
spartanxl IO_W1 switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[13][7]MAIN[20][7]MAIN[14][7]MAIN[16][7]MAIN[18][7]MAIN[17][7]MAIN[15][7]MAIN[19][7]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_H[2]
01011111CELL.SINGLE_H[3]
01101111CELL.SINGLE_H[5]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[4]
spartanxl IO_W1 switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[14][3]MAIN[18][1]MAIN[18][3]MAIN[14][2]MAIN[19][1]MAIN[17][1]MAIN[20][1]MAIN[15][2]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[2]
01111101CELL_S.SINGLE_H[3]
01111110CELL_S.SINGLE_H[4]
11111111CELL_S.SINGLE_H[5]
spartanxl IO_W1 switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[1][3]MAIN[4][2]MAIN[7][4]MAIN[2][3]MAIN[6][2]MAIN[6][3]MAIN[5][2]MAIN[5][3]CELL.IMUX_IO_T[0]
Source
00011111CELL.TIE_0
00100111CELL.LONG_IO_V[3]
00101011CELL.LONG_IO_V[0]
00110101CELL.LONG_IO_V[1]
00110110CELL.GCLK[0]
01101111CELL.DOUBLE_IO_W0[1]
01111101CELL.LONG_IO_V[2]
10110111CELL.DOUBLE_IO_W1[0]
10111011CELL.DOUBLE_IO_W1[1]
11111111CELL.DOUBLE_IO_W0[0]
spartanxl IO_W1 switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[2][2]MAIN[0][2]MAIN[7][2]MAIN[8][3]MAIN[9][3]MAIN[11][3]MAIN[9][2]MAIN[10][2]CELL.IMUX_IO_T[1]
Source
00011111CELL.TIE_0
00101101CELL.LONG_IO_V[0]
00110011CELL.DOUBLE_IO_W0[1]
00110101CELL.LONG_IO_V[2]
01101111CELL.DOUBLE_IO_W0[0]
01110111CELL.DOUBLE_IO_W1[1]
10111011CELL.LONG_IO_V[1]
10111101CELL.LONG_IO_V[3]
10111110CELL.GCLK[0]
11111111CELL.DOUBLE_IO_W1[0]

Bels TBUF

spartanxl IO_W1 bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
spartanxl IO_W1 bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[0][3]!MAIN[12][3]

Bels IO

spartanxl IO_W1 bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[23][6]CELL.IMUX_IO_IK[1] invert by !MAIN[23][3]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[24][9]CELL.IMUX_IO_OK[1] invert by !MAIN[23][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_G3_WCELL.IMUX_CLB_F3_W
TinCELL.IMUX_IO_T[0] invert by !MAIN[25][9]CELL.IMUX_IO_T[1] invert by !MAIN[24][0]
I1outCELL.OUT_IO_WE_I1[0]CELL.OUT_IO_WE_I1[1]
I2outCELL.OUT_IO_WE_I2[0]CELL.OUT_IO_WE_I2[1]
spartanxl IO_W1 bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[22][6]!MAIN[16][3]
OFF_SRVAL bit 0!MAIN[24][7]!MAIN[24][1]
READBACK_I1 bit 0!MAIN[25][8]!MAIN[21][3]
READBACK_I2 bit 0!MAIN[23][8]!MAIN[22][3]
READBACK_OQ bit 0!MAIN[22][8]!MAIN[23][2]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[22][7]!MAIN[24][2]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[21][7]MAIN[22][2]
IFF_CE_ENABLE!MAIN[7][8]!MAIN[7][7]
OFF_CE_ENABLE!MAIN[7][9]!MAIN[7][6]
SYNC_D[enum: IO_SYNC_D][enum: IO_SYNC_D]
IFF_CE_ENABLE_NO_IQ!MAIN[20][6]!MAIN[21][4]
MUX_T[enum: IO_MUX_T][enum: IO_MUX_T]
DRIVE[enum: IO_DRIVE][enum: IO_DRIVE]
_5V_TOLERANTMAIN[19][5]MAIN[20][4]
spartanxl IO_W1 enum IO_SLEW
IO[0].SLEWMAIN[23][9]
IO[1].SLEWMAIN[25][0]
FAST0
SLOW1
spartanxl IO_W1 enum IO_PULL
IO[0].PULLMAIN[17][6]MAIN[23][7]
IO[1].PULLMAIN[25][1]MAIN[23][1]
NONE11
PULLUP01
PULLDOWN10
spartanxl IO_W1 enum IO_MUX_I
IO[0].MUX_I1MAIN[23][5]MAIN[22][5]
IO[1].MUX_I1MAIN[25][4]MAIN[22][4]
IO[0].MUX_I2MAIN[25][5]MAIN[24][6]
IO[1].MUX_I2MAIN[24][4]MAIN[24][3]
I01
IQ11
IQL10
spartanxl IO_W1 enum IO_IFF_D
IO[0].IFF_DMAIN[24][5]MAIN[25][6]
IO[1].IFF_DMAIN[23][4]MAIN[25][3]
I11
DELAY00
MEDDELAY01
SYNC10
spartanxl IO_W1 enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[25][7]
IO[1].MUX_OFF_DMAIN[25][2]
O11
O20
spartanxl IO_W1 enum IO_MUX_O
IO[0].MUX_OMAIN[24][8]MAIN[21][8]MAIN[22][9]MAIN[21][9]
IO[1].MUX_OMAIN[22][1]MAIN[21][1]MAIN[22][0]MAIN[21][0]
O10000
O1_INV0001
O20111
O2_INV1111
OQ0010
MUX1011
spartanxl IO_W1 enum IO_SYNC_D
IO[0].SYNC_DMAIN[21][6]
IO[1].SYNC_DMAIN[21][2]
I1
DELAY0
spartanxl IO_W1 enum IO_MUX_T
IO[0].MUX_TMAIN[21][5]
IO[1].MUX_TMAIN[19][4]
T1
TQ0
spartanxl IO_W1 enum IO_DRIVE
IO[0].DRIVEMAIN[19][6]
IO[1].DRIVEMAIN[20][3]
_121
_240

Bels PULLUP

spartanxl IO_W1 bel PULLUP pins
PinDirectionPULLUP_TBUF[0]PULLUP_TBUF[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
spartanxl IO_W1 bel PULLUP attribute bits
AttributePULLUP_TBUF[0]PULLUP_TBUF[1]
ENABLE!MAIN_S[0][7]!MAIN[11][7]

Bel wires

spartanxl IO_W1 bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]TBUF[1].O, PULLUP_TBUF[1].O
CELL.IMUX_CLB_F3_WIO[1].O2
CELL.IMUX_CLB_G3_WIO[0].O2
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_WE_I1[0]IO[0].I1
CELL.OUT_IO_WE_I1[1]IO[1].I1
CELL.OUT_IO_WE_I2[0]IO[0].I2
CELL.OUT_IO_WE_I2[1]IO[1].I2

Bitstream

spartanxl IO_W1 rect MAIN
BitFrame
F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 IO[0]: !invert T IO[0]: !invert OK IO[0]: SLEW bit 0 IO[0]: MUX_O bit 1 IO[0]: MUX_O bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.LONG_IO_V[1] bit 0 - INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.DOUBLE_IO_W0[1] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W2[1] - IO[0]: ! OFF_CE_ENABLE INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_W0[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W0[3] INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_W1[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W1[3] INT: !bipass CELL.DOUBLE_IO_W0[3] = CELL.DOUBLE_IO_W2[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W2[3] INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_W2[3]
B8 IO[0]: ! READBACK_I1 bit 0 IO[0]: MUX_O bit 3 IO[0]: ! READBACK_I2 bit 0 IO[0]: ! READBACK_OQ bit 0 IO[0]: MUX_O bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.DBUF_IO_V[1] bit 1 INT: mux CELL.DBUF_IO_V[1] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 5 INT: mux CELL.DBUF_IO_V[1] bit 0 INT: mux CELL.DBUF_IO_V[1] bit 3 INT: mux CELL.LONG_IO_V[1] bit 3 INT: mux CELL.LONG_IO_V[1] bit 1 INT: mux CELL.LONG_IO_V[1] bit 2 INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1 INT: mux CELL.LONG_IO_V[3] bit 0 INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_IO_V[3] IO[0]: ! IFF_CE_ENABLE INT: mux CELL.LONG_IO_V[3] bit 1 INT: mux CELL.LONG_IO_V[2] bit 3 INT: mux CELL.LONG_IO_V[2] bit 0 INT: mux CELL.LONG_IO_V[2] bit 1 INT: mux CELL.LONG_IO_V[2] bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_IO_WE_I1_S1
B7 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_SRVAL bit 0 IO[0]: PULL bit 0 IO[0]: ! OFF_D_INV IO[0]: OFF_USED INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 7 INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[1] PULLUP_TBUF[1]: ! ENABLE INT: mux CELL.LONG_H[5] bit 2 INT: !pass CELL.DOUBLE_IO_W2[1] ← CELL.DBUF_IO_V[0] INT: !pass CELL.DOUBLE_IO_W2[3] ← CELL.DBUF_IO_V[0] IO[1]: ! IFF_CE_ENABLE INT: mux CELL.LONG_H[5] bit 1 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0] INT: mux CELL.LONG_H[4] bit 1 INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1_S1 - -
B6 IO[0]: IFF_D bit 0 IO[0]: MUX_I2 bit 0 IO[0]: !invert IK IO[0]: ! IFF_SRVAL bit 0 IO[0]: SYNC_D bit 0 IO[0]: ! IFF_CE_ENABLE_NO_IQ IO[0]: DRIVE bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 5 IO[0]: PULL bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 2 - INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: !pass CELL.DOUBLE_IO_W0[1] ← CELL.DBUF_IO_V[1] INT: mux CELL.IMUX_IO_OK[0] bit 7 INT: !pass CELL.DOUBLE_IO_W2[2] ← CELL.DBUF_IO_V[0] IO[1]: ! OFF_CE_ENABLE INT: !pass CELL.DOUBLE_IO_W2[0] ← CELL.DBUF_IO_V[0] - INT: mux CELL.LONG_H[5] bit 0 INT: !pass CELL.DOUBLE_IO_W0[3] ← CELL.DBUF_IO_V[1] INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2[0] INT: mux CELL.LONG_H[4] bit 2 INT: mux CELL.LONG_H[4] bit 0
B5 IO[0]: MUX_I2 bit 1 IO[0]: IFF_D bit 1 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_T bit 0 - IO[0]: _5V_TOLERANT - INT: mux CELL.IMUX_IO_OK[0] bit 6 - - - - INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_W0[2] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W0[2] INT: !pass CELL.DOUBLE_IO_W0[0] ← CELL.DBUF_IO_V[1] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W0[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W0[0] - INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W1[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W1[0] INT: mux CELL.LONG_IO_V[0] bit 1 INT: !bipass CELL.DOUBLE_IO_W0[0] = CELL.DOUBLE_IO_W2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W2[0] INT: mux CELL.LONG_IO_V[0] bit 0 INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W2[0]
B4 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I2 bit 1 IO[1]: IFF_D bit 1 IO[1]: MUX_I1 bit 0 IO[1]: ! IFF_CE_ENABLE_NO_IQ IO[1]: _5V_TOLERANT IO[1]: MUX_T bit 0 - - - - - - INT: !pass CELL.DOUBLE_IO_W0[2] ← CELL.DBUF_IO_V[1] INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_W1[2] INT: !bipass CELL.DOUBLE_IO_W0[2] = CELL.DOUBLE_IO_W2[2] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W2[2] INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_W2[2] INT: mux CELL.IMUX_IO_T[0] bit 5 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_IO_V[2] INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[0] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_WE_I2_S1
B3 IO[1]: IFF_D bit 0 IO[1]: MUX_I2 bit 0 IO[1]: !invert IK IO[1]: ! READBACK_I2 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: DRIVE bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 5 - IO[1]: ! IFF_SRVAL bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 7 - TBUF[1]: ! DRIVE1 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W1[2] INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 4 - INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.DBUF_IO_V[0] bit 1 INT: mux CELL.DBUF_IO_V[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 7 TBUF[0]: ! DRIVE1
B2 IO[1]: MUX_OFF_D bit 0 IO[1]: ! OFF_D_INV IO[1]: ! READBACK_OQ bit 0 IO[1]: OFF_USED IO[1]: SYNC_D bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 7 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 1 - INT: mux CELL.IMUX_IO_T[1] bit 5 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 6 INT: mux CELL.DBUF_IO_V[0] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 7 INT: mux CELL.DBUF_IO_V[0] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 6
B1 IO[1]: PULL bit 1 IO[1]: ! OFF_SRVAL bit 0 IO[1]: PULL bit 0 IO[1]: MUX_O bit 3 IO[1]: MUX_O bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.LONG_H[1] bit 2 INT: mux CELL.LONG_H[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 5 INT: mux CELL.IMUX_TBUF_T[1] bit 2 - INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 - INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.LONG_H[0] bit 2 INT: mux CELL.LONG_H[0] bit 1
B0 IO[1]: SLEW bit 0 IO[1]: !invert T IO[1]: !invert OK IO[1]: MUX_O bit 1 IO[1]: MUX_O bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 0 - - INT: mux CELL.LONG_H[1] bit 1 - INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 1 - INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 3 - INT: mux CELL.LONG_H[0] bit 0
spartanxl IO_W1 rect MAIN_S
BitFrame
F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - PULLUP_TBUF[0]: ! ENABLE
B6 - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_W1_S

Cells: 4

Switchbox INT

spartanxl IO_W1_S switchbox INT permanent buffers
DestinationSource
CELL.LONG_H_BUF[2]CELL.LONG_H[2]
CELL.LONG_H_BUF[3]CELL.LONG_H[3]
spartanxl IO_W1_S switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I2_S1!MAIN[1][4]
CELL.SINGLE_H[1]CELL.LONG_IO_V[0]!MAIN[3][4]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I2[0]!MAIN[4][4]
CELL.SINGLE_H[2]CELL.LONG_IO_V[1]!MAIN[12][7]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I1[0]!MAIN[4][7]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I1_S1!MAIN[10][8]
CELL.SINGLE_H[4]CELL.OUT_IO_WE_I2_S1!MAIN[0][4]
CELL.SINGLE_H[5]CELL.LONG_IO_V[2]!MAIN[6][4]
CELL.SINGLE_H[5]CELL.OUT_IO_WE_I2[0]!MAIN[5][4]
CELL.SINGLE_H[6]CELL.LONG_IO_V[3]!MAIN[8][8]
CELL.SINGLE_H[6]CELL.OUT_IO_WE_I1[0]!MAIN[1][8]
CELL.SINGLE_H[7]CELL.OUT_IO_WE_I1_S1!MAIN[0][8]
CELL.DOUBLE_H0[0]CELL.OUT_IO_WE_I1_S1!MAIN[2][7]
CELL.DOUBLE_H0[1]CELL.OUT_IO_WE_I2[0]!MAIN[2][6]
CELL.DOUBLE_H1[0]CELL.OUT_IO_WE_I1[0]!MAIN[5][7]
CELL.DOUBLE_H1[1]CELL.OUT_IO_WE_I2_S1!MAIN[2][4]
CELL.DOUBLE_IO_W0[0]CELL.DBUF_IO_V[1]!MAIN[10][5]
CELL.DOUBLE_IO_W0[1]CELL.DBUF_IO_V[1]!MAIN[10][6]
CELL.DOUBLE_IO_W0[2]CELL.DBUF_IO_V[1]!MAIN[12][4]
CELL.DOUBLE_IO_W0[3]CELL.DBUF_IO_V[1]!MAIN[3][6]
CELL.DOUBLE_IO_W2[0]CELL.DBUF_IO_V[0]!MAIN[6][6]
CELL.DOUBLE_IO_W2[1]CELL.DBUF_IO_V[0]!MAIN[9][7]
CELL.DOUBLE_IO_W2[2]CELL.DBUF_IO_V[0]!MAIN[8][6]
CELL.DOUBLE_IO_W2[3]CELL.DBUF_IO_V[0]!MAIN[8][7]
spartanxl IO_W1_S switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.DOUBLE_IO_W1[0]!MAIN[6][5]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_W0[0]!MAIN[9][5]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_W2[0]!MAIN[0][5]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_W1[1]!MAIN[13][9]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_W0[1]!MAIN[15][9]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_W2[1]!MAIN[9][9]
CELL.SINGLE_H[4]CELL.DOUBLE_IO_W1[2]!MAIN[11][4]
CELL.SINGLE_H[5]CELL.DOUBLE_IO_W0[2]!MAIN[12][5]
CELL.SINGLE_H[5]CELL.DOUBLE_IO_W2[2]!MAIN[8][4]
CELL.SINGLE_H[6]CELL.DOUBLE_IO_W1[3]!MAIN[4][9]
CELL.SINGLE_H[7]CELL.DOUBLE_IO_W0[3]!MAIN[6][9]
CELL.SINGLE_H[7]CELL.DOUBLE_IO_W2[3]!MAIN[0][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W0[0]!MAIN[8][5]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W1[0]!MAIN[5][5]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W2[0]!MAIN[2][5]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W0[3]!MAIN[5][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W1[3]!MAIN[3][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W2[3]!MAIN[1][9]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W0[1]!MAIN[14][9]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W1[1]!MAIN[12][9]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W2[1]!MAIN[10][9]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W0[2]!MAIN[11][5]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W1[2]!MAIN[10][3]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W2[2]!MAIN[9][4]
CELL.DOUBLE_IO_W0[0]CELL.DOUBLE_IO_W2[0]!MAIN[3][5]
CELL.DOUBLE_IO_W0[1]CELL.DOUBLE_IO_W2[1]!MAIN[11][9]
CELL.DOUBLE_IO_W0[2]CELL.DOUBLE_IO_W2[2]!MAIN[10][4]
CELL.DOUBLE_IO_W0[3]CELL.DOUBLE_IO_W2[3]!MAIN[2][9]
spartanxl IO_W1_S switchbox INT muxes DBUF_IO_V[0]
BitsDestination
MAIN[1][2]MAIN[3][2]MAIN[4][3]MAIN[3][3]CELL.DBUF_IO_V[0]
Source
0011CELL.DOUBLE_IO_W0[1]
0101CELL.DOUBLE_IO_W0[2]
0110CELL.DOUBLE_IO_W0[3]
1111CELL.DOUBLE_IO_W0[0]
spartanxl IO_W1_S switchbox INT muxes DBUF_IO_V[1]
BitsDestination
MAIN[14][8]MAIN[17][8]MAIN[18][8]MAIN[15][8]CELL.DBUF_IO_V[1]
Source
0011CELL.DOUBLE_IO_W2[0]
0101CELL.DOUBLE_IO_W2[1]
0110CELL.DOUBLE_IO_W2[3]
1111CELL.DOUBLE_IO_W2[2]
spartanxl IO_W1_S switchbox INT muxes LONG_H[0]
BitsDestination
MAIN[1][1]MAIN[0][1]MAIN[0][0]CELL.LONG_H[0]
Source
000CELL.LONG_IO_V[0]
011CELL.OUT_IO_WE_I2[1]
111off
spartanxl IO_W1_S switchbox INT muxes LONG_H[1]
BitsDestination
MAIN[15][1]MAIN[15][0]MAIN[14][1]CELL.LONG_H[1]
Source
000CELL.LONG_IO_V[1]
011CELL.OUT_IO_WE_I2[1]
111off
spartanxl IO_W1_S switchbox INT muxes LONG_H[4]
BitsDestination
MAIN[1][6]MAIN[3][7]MAIN[0][6]CELL.LONG_H[4]
Source
000CELL.LONG_IO_V[2]
011CELL.OUT_IO_WE_I2[0]
111off
spartanxl IO_W1_S switchbox INT muxes LONG_H[5]
BitsDestination
MAIN[10][7]MAIN[6][7]MAIN[4][6]CELL.LONG_H[5]
Source
000CELL.LONG_IO_V[3]
011CELL.OUT_IO_WE_I2[0]
111off
spartanxl IO_W1_S switchbox INT muxes LONG_IO_V[0]
BitsDestination
MAIN[4][5]MAIN[1][5]CELL.LONG_IO_V[0]
Source
00CELL.LONG_H[0]
01CELL.SINGLE_H[1]
11off
spartanxl IO_W1_S switchbox INT muxes LONG_IO_V[1]
BitsDestination
MAIN[13][8]MAIN[11][8]MAIN[12][8]MAIN[17][9]CELL.LONG_IO_V[1]
Source
0001CELL.LONG_H[1]
0010CELL.LONG_H_BUF[3]
0111CELL.SINGLE_H[2]
1111off
spartanxl IO_W1_S switchbox INT muxes LONG_IO_V[2]
BitsDestination
MAIN[5][8]MAIN[2][8]MAIN[3][8]MAIN[4][8]CELL.LONG_IO_V[2]
Source
0001CELL.LONG_H[4]
0010CELL.LONG_H_BUF[2]
0111CELL.SINGLE_H[5]
1111off
spartanxl IO_W1_S switchbox INT muxes LONG_IO_V[3]
BitsDestination
MAIN[6][8]MAIN[9][8]CELL.LONG_IO_V[3]
Source
00CELL.LONG_H[5]
01CELL.SINGLE_H[6]
11off
spartanxl IO_W1_S switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[2][1]MAIN[2][0]MAIN[4][1]MAIN[4][0]MAIN[3][0]CELL.IMUX_TBUF_I[0]
Source
00011CELL.OUT_IO_WE_I2[0]
00101CELL.DOUBLE_IO_W1[2]
00110CELL.LONG_IO_V[2]
01111CELL.DOUBLE_IO_W0[2]
10011CELL.DOUBLE_IO_W0[3]
10101CELL.DOUBLE_IO_W1[3]
10110CELL.OUT_IO_WE_I2[1]
11111CELL.TIE_0
spartanxl IO_W1_S switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[11][1]MAIN[13][0]MAIN[13][1]MAIN[11][0]MAIN[12][0]MAIN[12][1]CELL.IMUX_TBUF_I[1]
Source
000111CELL.DOUBLE_IO_W0[2]
001011CELL.OUT_IO_WE_I2[0]
001101CELL.LONG_IO_V[1]
010111CELL.DOUBLE_IO_W1[3]
011011CELL.DOUBLE_IO_W0[3]
011110CELL.OUT_IO_WE_I2[1]
101111CELL.DOUBLE_IO_W1[2]
111111CELL.TIE_0
spartanxl IO_W1_S switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[5][1]MAIN[6][0]MAIN[5][0]MAIN[8][0]MAIN[6][1]CELL.IMUX_TBUF_T[0]
Source
00011CELL.TIE_1
00111CELL.TIE_0
01001CELL.DOUBLE_IO_W0[1]
01010CELL.LONG_IO_V[3]
01101CELL.DOUBLE_IO_W1[1]
01110CELL.LONG_IO_V[2]
11011CELL.DOUBLE_IO_W0[0]
11111CELL.DOUBLE_IO_W1[0]
spartanxl IO_W1_S switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[7][1]MAIN[8][1]MAIN[10][1]MAIN[10][0]MAIN[9][0]CELL.IMUX_TBUF_T[1]
Source
00011CELL.TIE_1
00111CELL.TIE_0
01001CELL.DOUBLE_IO_W1[0]
01010CELL.LONG_IO_V[2]
01101CELL.DOUBLE_IO_W0[0]
01110CELL.LONG_IO_V[3]
11011CELL.DOUBLE_IO_W1[1]
11111CELL.DOUBLE_IO_W0[1]
spartanxl IO_W1_S switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[16][8]MAIN[19][8]MAIN[20][9]MAIN[19][9]MAIN[20][8]MAIN[18][9]CELL.IMUX_IO_O1[0]
Source
001111CELL.DOUBLE_H0[0]
011011CELL.LONG_H[4]
011101CELL.LONG_H[5]
011110CELL.LONG_H_BUF[3]
110111CELL.DOUBLE_H1[1]
111111CELL.TIE_0
spartanxl IO_W1_S switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[16][1]MAIN[20][0]MAIN[19][0]MAIN[18][0]CELL.IMUX_IO_O1[1]
Source
0001CELL.LONG_H[0]
0010CELL.LONG_H[1]
0101CELL_S.DOUBLE_H0[1]
0110CELL.LONG_H_BUF[2]
1011CELL_S.DOUBLE_H1[0]
1111CELL.TIE_0
spartanxl IO_W1_S switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[9][6]MAIN[17][5]MAIN[18][6]MAIN[12][6]MAIN[15][6]MAIN[14][6]MAIN[11][6]MAIN[16][6]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_H[3]
01011111CELL.SINGLE_H[4]
01101111CELL.SINGLE_H[5]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[2]
spartanxl IO_W1_S switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[11][2]MAIN[18][2]MAIN[17][2]MAIN[13][2]MAIN[19][2]MAIN[12][2]MAIN[16][2]MAIN[20][2]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[2]
01111101CELL_S.SINGLE_H[4]
01111110CELL_S.SINGLE_H[5]
11111111CELL_S.SINGLE_H[3]
spartanxl IO_W1_S switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[13][7]MAIN[20][7]MAIN[14][7]MAIN[16][7]MAIN[18][7]MAIN[17][7]MAIN[15][7]MAIN[19][7]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_H[2]
01011111CELL.SINGLE_H[3]
01101111CELL.SINGLE_H[5]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[4]
spartanxl IO_W1_S switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[14][3]MAIN[18][1]MAIN[18][3]MAIN[14][2]MAIN[19][1]MAIN[17][1]MAIN[20][1]MAIN[15][2]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[2]
01111101CELL_S.SINGLE_H[3]
01111110CELL_S.SINGLE_H[4]
11111111CELL_S.SINGLE_H[5]
spartanxl IO_W1_S switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[1][3]MAIN[4][2]MAIN[7][4]MAIN[2][3]MAIN[6][2]MAIN[6][3]MAIN[5][2]MAIN[5][3]CELL.IMUX_IO_T[0]
Source
00011111CELL.TIE_0
00100111CELL.LONG_IO_V[3]
00101011CELL.LONG_IO_V[0]
00110101CELL.LONG_IO_V[1]
00110110CELL.GCLK[0]
01101111CELL.DOUBLE_IO_W0[1]
01111101CELL.LONG_IO_V[2]
10110111CELL.DOUBLE_IO_W1[0]
10111011CELL.DOUBLE_IO_W1[1]
11111111CELL.DOUBLE_IO_W0[0]
spartanxl IO_W1_S switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[2][2]MAIN[0][2]MAIN[7][2]MAIN[8][3]MAIN[9][3]MAIN[11][3]MAIN[9][2]MAIN[10][2]CELL.IMUX_IO_T[1]
Source
00011111CELL.TIE_0
00101101CELL.LONG_IO_V[0]
00110011CELL.DOUBLE_IO_W0[1]
00110101CELL.LONG_IO_V[2]
01101111CELL.DOUBLE_IO_W0[0]
01110111CELL.DOUBLE_IO_W1[1]
10111011CELL.LONG_IO_V[1]
10111101CELL.LONG_IO_V[3]
10111110CELL.GCLK[0]
11111111CELL.DOUBLE_IO_W1[0]

Bels TBUF

spartanxl IO_W1_S bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
spartanxl IO_W1_S bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[0][3]!MAIN[12][3]

Bels IO

spartanxl IO_W1_S bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[23][6]CELL.IMUX_IO_IK[1] invert by !MAIN[23][3]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[24][9]CELL.IMUX_IO_OK[1] invert by !MAIN[23][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_G3_WCELL.IMUX_CLB_F3_W
TinCELL.IMUX_IO_T[0] invert by !MAIN[25][9]CELL.IMUX_IO_T[1] invert by !MAIN[24][0]
I1outCELL.OUT_IO_WE_I1[0]CELL.OUT_IO_WE_I1[1]
I2outCELL.OUT_IO_WE_I2[0]CELL.OUT_IO_WE_I2[1]
CLKINout-CELL.OUT_IO_CLKIN
spartanxl IO_W1_S bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[22][6]!MAIN[16][3]
OFF_SRVAL bit 0!MAIN[24][7]!MAIN[24][1]
READBACK_I1 bit 0!MAIN[25][8]!MAIN[21][3]
READBACK_I2 bit 0!MAIN[23][8]!MAIN[22][3]
READBACK_OQ bit 0!MAIN[22][8]!MAIN[23][2]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[22][7]!MAIN[24][2]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[21][7]MAIN[22][2]
IFF_CE_ENABLE!MAIN[7][8]!MAIN[7][7]
OFF_CE_ENABLE!MAIN[7][9]!MAIN[7][6]
SYNC_D[enum: IO_SYNC_D][enum: IO_SYNC_D]
IFF_CE_ENABLE_NO_IQ!MAIN[20][6]!MAIN[21][4]
MUX_T[enum: IO_MUX_T][enum: IO_MUX_T]
DRIVE[enum: IO_DRIVE][enum: IO_DRIVE]
_5V_TOLERANTMAIN[19][5]MAIN[20][4]
spartanxl IO_W1_S enum IO_SLEW
IO[0].SLEWMAIN[23][9]
IO[1].SLEWMAIN[25][0]
FAST0
SLOW1
spartanxl IO_W1_S enum IO_PULL
IO[0].PULLMAIN[17][6]MAIN[23][7]
IO[1].PULLMAIN[25][1]MAIN[23][1]
NONE11
PULLUP01
PULLDOWN10
spartanxl IO_W1_S enum IO_MUX_I
IO[0].MUX_I1MAIN[23][5]MAIN[22][5]
IO[1].MUX_I1MAIN[25][4]MAIN[22][4]
IO[0].MUX_I2MAIN[25][5]MAIN[24][6]
IO[1].MUX_I2MAIN[24][4]MAIN[24][3]
I01
IQ11
IQL10
spartanxl IO_W1_S enum IO_IFF_D
IO[0].IFF_DMAIN[24][5]MAIN[25][6]
IO[1].IFF_DMAIN[23][4]MAIN[25][3]
I11
DELAY00
MEDDELAY01
SYNC10
spartanxl IO_W1_S enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[25][7]
IO[1].MUX_OFF_DMAIN[25][2]
O11
O20
spartanxl IO_W1_S enum IO_MUX_O
IO[0].MUX_OMAIN[24][8]MAIN[21][8]MAIN[22][9]MAIN[21][9]
IO[1].MUX_OMAIN[22][1]MAIN[21][1]MAIN[22][0]MAIN[21][0]
O10000
O1_INV0001
O20111
O2_INV1111
OQ0010
MUX1011
spartanxl IO_W1_S enum IO_SYNC_D
IO[0].SYNC_DMAIN[21][6]
IO[1].SYNC_DMAIN[21][2]
I1
DELAY0
spartanxl IO_W1_S enum IO_MUX_T
IO[0].MUX_TMAIN[21][5]
IO[1].MUX_TMAIN[19][4]
T1
TQ0
spartanxl IO_W1_S enum IO_DRIVE
IO[0].DRIVEMAIN[19][6]
IO[1].DRIVEMAIN[20][3]
_121
_240

Bels PULLUP

spartanxl IO_W1_S bel PULLUP pins
PinDirectionPULLUP_TBUF[0]PULLUP_TBUF[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
spartanxl IO_W1_S bel PULLUP attribute bits
AttributePULLUP_TBUF[0]PULLUP_TBUF[1]
ENABLE!MAIN_S[0][10]!MAIN[11][7]

Bel wires

spartanxl IO_W1_S bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]TBUF[1].O, PULLUP_TBUF[1].O
CELL.IMUX_CLB_F3_WIO[1].O2
CELL.IMUX_CLB_G3_WIO[0].O2
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_WE_I1[0]IO[0].I1
CELL.OUT_IO_WE_I1[1]IO[1].I1
CELL.OUT_IO_WE_I2[0]IO[0].I2
CELL.OUT_IO_WE_I2[1]IO[1].I2
CELL.OUT_IO_CLKINIO[1].CLKIN

Bitstream

spartanxl IO_W1_S rect MAIN
BitFrame
F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 IO[0]: !invert T IO[0]: !invert OK IO[0]: SLEW bit 0 IO[0]: MUX_O bit 1 IO[0]: MUX_O bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.LONG_IO_V[1] bit 0 - INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.DOUBLE_IO_W0[1] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W2[1] - IO[0]: ! OFF_CE_ENABLE INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_W0[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W0[3] INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_W1[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W1[3] INT: !bipass CELL.DOUBLE_IO_W0[3] = CELL.DOUBLE_IO_W2[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W2[3] INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_W2[3]
B8 IO[0]: ! READBACK_I1 bit 0 IO[0]: MUX_O bit 3 IO[0]: ! READBACK_I2 bit 0 IO[0]: ! READBACK_OQ bit 0 IO[0]: MUX_O bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.DBUF_IO_V[1] bit 1 INT: mux CELL.DBUF_IO_V[1] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 5 INT: mux CELL.DBUF_IO_V[1] bit 0 INT: mux CELL.DBUF_IO_V[1] bit 3 INT: mux CELL.LONG_IO_V[1] bit 3 INT: mux CELL.LONG_IO_V[1] bit 1 INT: mux CELL.LONG_IO_V[1] bit 2 INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1 INT: mux CELL.LONG_IO_V[3] bit 0 INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_IO_V[3] IO[0]: ! IFF_CE_ENABLE INT: mux CELL.LONG_IO_V[3] bit 1 INT: mux CELL.LONG_IO_V[2] bit 3 INT: mux CELL.LONG_IO_V[2] bit 0 INT: mux CELL.LONG_IO_V[2] bit 1 INT: mux CELL.LONG_IO_V[2] bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_IO_WE_I1_S1
B7 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_SRVAL bit 0 IO[0]: PULL bit 0 IO[0]: ! OFF_D_INV IO[0]: OFF_USED INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 7 INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[1] PULLUP_TBUF[1]: ! ENABLE INT: mux CELL.LONG_H[5] bit 2 INT: !pass CELL.DOUBLE_IO_W2[1] ← CELL.DBUF_IO_V[0] INT: !pass CELL.DOUBLE_IO_W2[3] ← CELL.DBUF_IO_V[0] IO[1]: ! IFF_CE_ENABLE INT: mux CELL.LONG_H[5] bit 1 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0] INT: mux CELL.LONG_H[4] bit 1 INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1_S1 - -
B6 IO[0]: IFF_D bit 0 IO[0]: MUX_I2 bit 0 IO[0]: !invert IK IO[0]: ! IFF_SRVAL bit 0 IO[0]: SYNC_D bit 0 IO[0]: ! IFF_CE_ENABLE_NO_IQ IO[0]: DRIVE bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 5 IO[0]: PULL bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 2 - INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: !pass CELL.DOUBLE_IO_W0[1] ← CELL.DBUF_IO_V[1] INT: mux CELL.IMUX_IO_OK[0] bit 7 INT: !pass CELL.DOUBLE_IO_W2[2] ← CELL.DBUF_IO_V[0] IO[1]: ! OFF_CE_ENABLE INT: !pass CELL.DOUBLE_IO_W2[0] ← CELL.DBUF_IO_V[0] - INT: mux CELL.LONG_H[5] bit 0 INT: !pass CELL.DOUBLE_IO_W0[3] ← CELL.DBUF_IO_V[1] INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2[0] INT: mux CELL.LONG_H[4] bit 2 INT: mux CELL.LONG_H[4] bit 0
B5 IO[0]: MUX_I2 bit 1 IO[0]: IFF_D bit 1 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_T bit 0 - IO[0]: _5V_TOLERANT - INT: mux CELL.IMUX_IO_OK[0] bit 6 - - - - INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_W0[2] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W0[2] INT: !pass CELL.DOUBLE_IO_W0[0] ← CELL.DBUF_IO_V[1] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W0[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W0[0] - INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W1[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W1[0] INT: mux CELL.LONG_IO_V[0] bit 1 INT: !bipass CELL.DOUBLE_IO_W0[0] = CELL.DOUBLE_IO_W2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W2[0] INT: mux CELL.LONG_IO_V[0] bit 0 INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W2[0]
B4 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I2 bit 1 IO[1]: IFF_D bit 1 IO[1]: MUX_I1 bit 0 IO[1]: ! IFF_CE_ENABLE_NO_IQ IO[1]: _5V_TOLERANT IO[1]: MUX_T bit 0 - - - - - - INT: !pass CELL.DOUBLE_IO_W0[2] ← CELL.DBUF_IO_V[1] INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_W1[2] INT: !bipass CELL.DOUBLE_IO_W0[2] = CELL.DOUBLE_IO_W2[2] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W2[2] INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_W2[2] INT: mux CELL.IMUX_IO_T[0] bit 5 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_IO_V[2] INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[0] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_WE_I2_S1
B3 IO[1]: IFF_D bit 0 IO[1]: MUX_I2 bit 0 IO[1]: !invert IK IO[1]: ! READBACK_I2 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: DRIVE bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 5 - IO[1]: ! IFF_SRVAL bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 7 - TBUF[1]: ! DRIVE1 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W1[2] INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 4 - INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.DBUF_IO_V[0] bit 1 INT: mux CELL.DBUF_IO_V[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 7 TBUF[0]: ! DRIVE1
B2 IO[1]: MUX_OFF_D bit 0 IO[1]: ! OFF_D_INV IO[1]: ! READBACK_OQ bit 0 IO[1]: OFF_USED IO[1]: SYNC_D bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 7 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 1 - INT: mux CELL.IMUX_IO_T[1] bit 5 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 6 INT: mux CELL.DBUF_IO_V[0] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 7 INT: mux CELL.DBUF_IO_V[0] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 6
B1 IO[1]: PULL bit 1 IO[1]: ! OFF_SRVAL bit 0 IO[1]: PULL bit 0 IO[1]: MUX_O bit 3 IO[1]: MUX_O bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.LONG_H[1] bit 2 INT: mux CELL.LONG_H[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 5 INT: mux CELL.IMUX_TBUF_T[1] bit 2 - INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 - INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.LONG_H[0] bit 2 INT: mux CELL.LONG_H[0] bit 1
B0 IO[1]: SLEW bit 0 IO[1]: !invert T IO[1]: !invert OK IO[1]: MUX_O bit 1 IO[1]: MUX_O bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 0 - - INT: mux CELL.LONG_H[1] bit 1 - INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 1 - INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 3 - INT: mux CELL.LONG_H[0] bit 0
spartanxl IO_W1_S rect MAIN_S
BitFrame
F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B12 - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - PULLUP_TBUF[0]: ! ENABLE
B9 - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_E0

Cells: 3

Switchbox INT

spartanxl IO_E0 switchbox INT permanent buffers
DestinationSource
CELL.LONG_H_BUF[2]CELL.LONG_H[2]
CELL.LONG_H_BUF[3]CELL.LONG_H[3]
spartanxl IO_E0 switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[26][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[30][8]
CELL.LONG_H[2]CELL.SINGLE_V[3]!MAIN[27][4]
CELL.LONG_H[3]CELL.SINGLE_V[4]!MAIN[12][5]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[38][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[40][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[32][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[38][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[34][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[34][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[31][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[35][8]
spartanxl IO_E0 switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I2_S1!MAIN[24][4]
CELL.SINGLE_H[1]CELL.LONG_IO_V[0]!MAIN[22][4]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I2[0]!MAIN[21][4]
CELL.SINGLE_H[2]CELL.LONG_IO_V[1]!MAIN[13][7]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I1[0]!MAIN[21][7]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I1_S1!MAIN[15][8]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[33][4]
CELL.SINGLE_H[4]CELL.OUT_IO_WE_I2_S1!MAIN[25][4]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[27][3]
CELL.SINGLE_H[5]CELL.LONG_IO_V[2]!MAIN[19][4]
CELL.SINGLE_H[5]CELL.OUT_IO_WE_I2[0]!MAIN[20][4]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[34][9]
CELL.SINGLE_H[6]CELL.LONG_IO_V[3]!MAIN[17][8]
CELL.SINGLE_H[6]CELL.OUT_IO_WE_I1[0]!MAIN[24][8]
CELL.SINGLE_H[7]CELL.OUT_IO_WE_I1_S1!MAIN[25][8]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[32][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[40][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[39][7]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[26][6]
CELL.SINGLE_V[0]CELL.OUT_IO_WE_I2[0]!MAIN[28][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[28][8]
CELL.SINGLE_V[1]CELL.OUT_IO_WE_I2[1]!MAIN[29][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[34][8]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[30][4]
CELL.SINGLE_V[3]CELL.LONG_H_BUF[2]!MAIN_S[33][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[35][4]
CELL.SINGLE_V[4]CELL.LONG_H_BUF[3]!MAIN[26][7]
CELL.SINGLE_V[4]CELL.OUT_IO_WE_I2[0]!MAIN[39][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[40][5]
CELL.SINGLE_V[5]CELL.OUT_IO_WE_I2[1]!MAIN[36][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[40][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[39][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[26][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[38][3]
CELL.DOUBLE_H0[0]CELL.OUT_IO_WE_I1[0]!MAIN[20][7]
CELL.DOUBLE_H0[1]CELL.OUT_IO_WE_I2_S1!MAIN[23][4]
CELL.DOUBLE_H1[0]CELL.OUT_IO_WE_I1_S1!MAIN[23][7]
CELL.DOUBLE_H1[1]CELL.OUT_IO_WE_I2[0]!MAIN[23][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[26][4]
CELL.DOUBLE_V0[1]CELL.OUT_IO_WE_I2[1]!MAIN[37][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[31][4]
CELL.DOUBLE_V1[1]CELL.OUT_IO_WE_I2[0]!MAIN[40][4]
CELL.DOUBLE_IO_E0[0]CELL.DBUF_IO_V[0]!MAIN[19][6]
CELL.DOUBLE_IO_E0[1]CELL.DBUF_IO_V[0]!MAIN[16][7]
CELL.DOUBLE_IO_E0[2]CELL.DBUF_IO_V[0]!MAIN[17][6]
CELL.DOUBLE_IO_E0[3]CELL.DBUF_IO_V[0]!MAIN[17][7]
CELL.DOUBLE_IO_E2[0]CELL.DBUF_IO_V[1]!MAIN[15][5]
CELL.DOUBLE_IO_E2[1]CELL.DBUF_IO_V[1]!MAIN[15][6]
CELL.DOUBLE_IO_E2[2]CELL.DBUF_IO_V[1]!MAIN[13][4]
CELL.DOUBLE_IO_E2[3]CELL.DBUF_IO_V[1]!MAIN[22][6]
spartanxl IO_E0 switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[28][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[27][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[30][3]
CELL.SINGLE_H[0]CELL.DOUBLE_IO_E0[0]!MAIN[25][5]
CELL.SINGLE_H[0]CELL.DOUBLE_IO_E2[0]!MAIN[16][5]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[30][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[29][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[29][3]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_E1[0]!MAIN[19][5]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[32][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[31][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[33][8]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_E0[1]!MAIN[16][9]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_E2[1]!MAIN[10][9]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[31][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[28][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[30][7]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_E1[1]!MAIN[12][9]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[36][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[39][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[35][6]
CELL.SINGLE_H[4]CELL.DOUBLE_IO_E0[2]!MAIN[17][4]
CELL.SINGLE_H[4]CELL.DOUBLE_IO_E2[2]!MAIN[13][5]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[35][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[36][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[37][5]
CELL.SINGLE_H[5]CELL.DOUBLE_IO_E1[2]!MAIN[14][4]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[35][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[36][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[36][7]
CELL.SINGLE_H[6]CELL.DOUBLE_IO_E0[3]!MAIN[25][9]
CELL.SINGLE_H[6]CELL.DOUBLE_IO_E2[3]!MAIN[19][9]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[38][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[35][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[37][8]
CELL.SINGLE_H[7]CELL.DOUBLE_IO_E1[3]!MAIN[21][9]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[26][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[28][5]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[30][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[31][5]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[31][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[32][9]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[32][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[33][7]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[39][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[37][6]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[36][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[38][5]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[34][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[37][7]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[37][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[39][9]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[29][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[31][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[30][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[27][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[38][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[39][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[38][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[36][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[29][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[27][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[28][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E0[1]!MAIN[15][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E1[1]!MAIN[13][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E2[1]!MAIN[11][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[33][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[32][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[33][3]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E0[2]!MAIN[16][4]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E1[2]!MAIN[15][3]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E2[2]!MAIN[14][5]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E0[0]!MAIN[23][5]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E1[0]!MAIN[20][5]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E2[0]!MAIN[17][5]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E0[3]!MAIN[24][9]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E1[3]!MAIN[22][9]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E2[3]!MAIN[20][9]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[29][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[29][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[33][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[34][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[27][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[34][3]
CELL.DOUBLE_IO_E0[0]CELL.DOUBLE_IO_E2[0]!MAIN[22][5]
CELL.DOUBLE_IO_E0[1]CELL.DOUBLE_IO_E2[1]!MAIN[14][9]
CELL.DOUBLE_IO_E0[2]CELL.DOUBLE_IO_E2[2]!MAIN[15][4]
CELL.DOUBLE_IO_E0[3]CELL.DOUBLE_IO_E2[3]!MAIN[23][9]
spartanxl IO_E0 switchbox INT muxes DBUF_IO_V[0]
BitsDestination
MAIN[21][3]MAIN[24][2]MAIN[22][2]MAIN[22][3]CELL.DBUF_IO_V[0]
Source
0011CELL.DOUBLE_IO_E2[0]
0101CELL.DOUBLE_IO_E2[1]
0110CELL.DOUBLE_IO_E2[3]
1111CELL.DOUBLE_IO_E2[2]
spartanxl IO_E0 switchbox INT muxes DBUF_IO_V[1]
BitsDestination
MAIN[8][8]MAIN[9][8]MAIN[11][8]MAIN[10][8]CELL.DBUF_IO_V[1]
Source
0011CELL.DOUBLE_IO_E0[1]
0101CELL.DOUBLE_IO_E0[2]
0110CELL.DOUBLE_IO_E0[3]
1111CELL.DOUBLE_IO_E0[0]
spartanxl IO_E0 switchbox INT muxes LONG_H[0]
BitsDestination
MAIN[24][1]MAIN[25][1]MAIN[24][0]CELL.LONG_H[0]
Source
000CELL.LONG_IO_V[0]
011CELL.OUT_IO_WE_I2[1]
111off
spartanxl IO_E0 switchbox INT muxes LONG_H[1]
BitsDestination
MAIN[10][1]MAIN[11][0]MAIN[10][0]CELL.LONG_H[1]
Source
000CELL.LONG_IO_V[1]
011CELL.OUT_IO_WE_I2[1]
111off
spartanxl IO_E0 switchbox INT muxes LONG_H[4]
BitsDestination
MAIN[24][6]MAIN[24][7]MAIN[22][7]CELL.LONG_H[4]
Source
000CELL.LONG_IO_V[2]
011CELL.OUT_IO_WE_I2[0]
111off
spartanxl IO_E0 switchbox INT muxes LONG_H[5]
BitsDestination
MAIN[15][7]MAIN[21][6]MAIN[19][7]CELL.LONG_H[5]
Source
000CELL.LONG_IO_V[3]
011CELL.OUT_IO_WE_I2[0]
111off
spartanxl IO_E0 switchbox INT muxes LONG_IO_V[0]
BitsDestination
MAIN[21][5]MAIN[24][5]CELL.LONG_IO_V[0]
Source
00CELL.LONG_H[0]
01CELL.SINGLE_H[1]
11off
spartanxl IO_E0 switchbox INT muxes LONG_IO_V[1]
BitsDestination
MAIN[12][8]MAIN[8][9]MAIN[13][8]MAIN[14][8]CELL.LONG_IO_V[1]
Source
0001CELL.LONG_H[1]
0010CELL.LONG_H_BUF[3]
0111CELL.SINGLE_H[2]
1111off
spartanxl IO_E0 switchbox INT muxes LONG_IO_V[2]
BitsDestination
MAIN[20][8]MAIN[21][8]MAIN[22][8]MAIN[23][8]CELL.LONG_IO_V[2]
Source
0001CELL.LONG_H[4]
0010CELL.LONG_H_BUF[2]
0111CELL.SINGLE_H[5]
1111off
spartanxl IO_E0 switchbox INT muxes LONG_IO_V[3]
BitsDestination
MAIN[19][8]MAIN[16][8]CELL.LONG_IO_V[3]
Source
00CELL.LONG_H[5]
01CELL.SINGLE_H[6]
11off
spartanxl IO_E0 switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[31][2]MAIN[33][0]MAIN[32][1]MAIN[31][0]MAIN[32][3]MAIN[31][1]MAIN[32][0]MAIN[32][2]CELL.IMUX_CLB_F1
Source
00100111CELL.SINGLE_V[3]
00101011CELL.LONG_V[4]
00101110CELL.SINGLE_V[7]
00111111CELL.SINGLE_V[0]
01000111CELL.LONG_V[3]
01001011CELL.DOUBLE_V0[1]
01001110CELL.LONG_V[0]
01011111CELL.SINGLE_V[1]
01100101CELL.SINGLE_V[5]
01101001CELL.LONG_V[1]
01101100CELL.SINGLE_V[6]
01111101CELL.DOUBLE_V1[1]
11100111CELL.DOUBLE_V1[0]
11101011CELL.SINGLE_V[4]
11101110CELL.DOUBLE_V0[0]
11111111CELL.SINGLE_V[2]
spartanxl IO_E0 switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[38][2]MAIN[40][0]MAIN[39][2]MAIN[40][1]MAIN[38][0]MAIN[39][1]MAIN[40][2]MAIN[39][0]MAIN[40][3]CELL.IMUX_CLB_F3
Source
000011111CELL.SINGLE_V[0]
000111011CELL.DOUBLE_V0[0]
000111101CELL.LONG_V[2]
001111111CELL.SINGLE_V[3]
010001111CELL.DOUBLE_V1[1]
010010111CELL.LONG_V[1]
010101011CELL.DOUBLE_V0[1]
010101101CELL.LONG_V[5]
010110011CELL.SINGLE_V[4]
010110101CELL.LONG_V[4]
010111110CELL.GCLK[0]
011101111CELL.SINGLE_V[1]
011110111CELL.SINGLE_V[2]
110011111CELL.SINGLE_V[6]
110111011CELL.DOUBLE_V1[0]
110111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[7]
spartanxl IO_E0 switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[26][0]MAIN[26][3]MAIN[28][0]MAIN[28][1]MAIN[27][1]MAIN[26][1]MAIN[27][0]MAIN[26][2]CELL.IMUX_CLB_G1
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[2]
00011101CELL.SINGLE_V[4]
00101011CELL.LONG_V[4]
00101110CELL.LONG_V[3]
00110011CELL.SINGLE_V[1]
00110110CELL.DOUBLE_V1[0]
00111001CELL.DOUBLE_V0[1]
00111100CELL.LONG_V[0]
01101111CELL.SINGLE_V[3]
01110111CELL.DOUBLE_V0[0]
01111101CELL.SINGLE_V[7]
10011111CELL.DOUBLE_V1[1]
10111011CELL.LONG_V[1]
10111110CELL.SINGLE_V[5]
11111111CELL.SINGLE_V[6]
spartanxl IO_E0 switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[34][0]MAIN[33][2]MAIN[35][1]MAIN[33][1]MAIN[34][2]MAIN[35][0]MAIN[34][1]MAIN[35][2]MAIN[35][3]MAIN[12][3]CELL.IMUX_CLB_G3
Source
0001111111CELL.SPECIAL_CLB_CIN
0010011111CELL.SINGLE_V[0]
0010101111CELL.SINGLE_V[2]
0010111011CELL.SINGLE_V[4]
0011010111CELL.LONG_V[4]
0011011101CELL.LONG_V[2]
0011100111CELL.SINGLE_V[1]
0011101101CELL.SINGLE_V[6]
0011110011CELL.DOUBLE_V0[1]
0011111001CELL.LONG_V[5]
0011111110CELL.GCLK[0]
0111011111CELL.DOUBLE_V0[0]
0111101111CELL.SINGLE_V[5]
0111111011CELL.DOUBLE_V1[0]
1010111111CELL.DOUBLE_V1[1]
1011110111CELL.LONG_V[1]
1011111101CELL.SINGLE_V[7]
1111111111CELL.SINGLE_V[3]
spartanxl IO_E0 switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[36][0]MAIN[36][1]MAIN[37][1]MAIN[37][0]MAIN[36][2]MAIN[37][2]MAIN[37][3]MAIN[38][1]CELL.IMUX_CLB_C3
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[2]
00011110CELL.GCLK[2]
00101011CELL.SINGLE_V[3]
00101101CELL.SINGLE_V[7]
00110011CELL.DOUBLE_V0[0]
00110101CELL.DOUBLE_V1[0]
00111010CELL.LONG_V[3]
00111100CELL.LONG_V[2]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[1]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
spartanxl IO_E0 switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[23][1]MAIN[21][0]MAIN[23][0]MAIN[21][1]MAIN[22][0]CELL.IMUX_TBUF_I[0]
Source
00011CELL.DOUBLE_IO_E2[2]
00101CELL.OUT_IO_WE_I2[0]
00110CELL.LONG_IO_V[2]
01111CELL.DOUBLE_IO_E1[2]
10011CELL.DOUBLE_IO_E1[3]
10101CELL.DOUBLE_IO_E2[3]
10110CELL.OUT_IO_WE_I2[1]
11111CELL.TIE_0
spartanxl IO_E0 switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[12][1]MAIN[14][1]MAIN[12][0]MAIN[14][0]MAIN[13][0]MAIN[13][1]CELL.IMUX_TBUF_I[1]
Source
000111CELL.DOUBLE_IO_E1[2]
001111CELL.DOUBLE_IO_E1[3]
010011CELL.OUT_IO_WE_I2[0]
010101CELL.LONG_IO_V[1]
011011CELL.DOUBLE_IO_E2[3]
011110CELL.OUT_IO_WE_I2[1]
110111CELL.DOUBLE_IO_E2[2]
111111CELL.TIE_0
spartanxl IO_E0 switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[17][0]MAIN[19][0]MAIN[20][0]MAIN[20][1]MAIN[19][1]CELL.IMUX_TBUF_T[0]
Source
00011CELL.TIE_1
00111CELL.TIE_0
01001CELL.DOUBLE_IO_E2[0]
01010CELL.LONG_IO_V[3]
01101CELL.DOUBLE_IO_E1[0]
01110CELL.LONG_IO_V[2]
11011CELL.DOUBLE_IO_E2[1]
11111CELL.DOUBLE_IO_E1[1]
spartanxl IO_E0 switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[15][0]MAIN[17][1]MAIN[15][1]MAIN[18][1]MAIN[16][0]CELL.IMUX_TBUF_T[1]
Source
00011CELL.TIE_1
00111CELL.TIE_0
01001CELL.DOUBLE_IO_E1[1]
01010CELL.LONG_IO_V[2]
01101CELL.DOUBLE_IO_E2[1]
01110CELL.LONG_IO_V[3]
11011CELL.DOUBLE_IO_E1[0]
11111CELL.DOUBLE_IO_E2[0]
spartanxl IO_E0 switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[5][9]MAIN[5][8]MAIN[7][8]MAIN[6][9]MAIN[6][8]MAIN[7][9]CELL.IMUX_IO_O1[0]
Source
011111CELL.DOUBLE_H0[1]
100111CELL.DOUBLE_H1[0]
101011CELL.LONG_H[4]
101101CELL.LONG_H[5]
101110CELL.LONG_H_BUF[3]
111111CELL.TIE_0
spartanxl IO_E0 switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[6][0]MAIN[5][0]MAIN[9][1]MAIN[7][0]CELL.IMUX_IO_O1[1]
Source
0001CELL.LONG_H[0]
0010CELL.LONG_H[1]
0101CELL_S.DOUBLE_H1[1]
0110CELL.LONG_H_BUF[2]
1011CELL_S.DOUBLE_H0[0]
1111CELL.TIE_0
spartanxl IO_E0 switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[7][6]MAIN[16][6]MAIN[8][5]MAIN[13][6]MAIN[10][6]MAIN[11][6]MAIN[14][6]MAIN[9][6]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_H[2]
01011111CELL.SINGLE_H[3]
01101111CELL.SINGLE_H[5]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[4]
spartanxl IO_E0 switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[5][2]MAIN[7][2]MAIN[8][2]MAIN[12][2]MAIN[6][2]MAIN[13][2]MAIN[14][2]MAIN[9][2]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[2]
01111101CELL_S.SINGLE_H[3]
01111110CELL_S.SINGLE_H[4]
11111111CELL_S.SINGLE_H[5]
spartanxl IO_E0 switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[5][7]MAIN[11][7]MAIN[12][7]MAIN[9][7]MAIN[7][7]MAIN[8][7]MAIN[10][7]MAIN[6][7]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_H[3]
01011111CELL.SINGLE_H[4]
01101111CELL.SINGLE_H[5]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[2]
spartanxl IO_E0 switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[5][1]MAIN[7][1]MAIN[7][3]MAIN[11][2]MAIN[6][1]MAIN[8][1]MAIN[10][2]MAIN[11][3]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[2]
01111101CELL_S.SINGLE_H[4]
01111110CELL_S.SINGLE_H[5]
11111111CELL_S.SINGLE_H[3]
spartanxl IO_E0 switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[20][3]MAIN[18][4]MAIN[19][2]MAIN[21][2]MAIN[19][3]MAIN[23][3]MAIN[20][2]MAIN[24][3]CELL.IMUX_IO_T[0]
Source
00011011CELL.LONG_IO_V[3]
00011101CELL.LONG_IO_V[1]
00011110CELL.GCLK[0]
00101011CELL.LONG_IO_V[0]
00110011CELL.DOUBLE_IO_E2[1]
00110101CELL.LONG_IO_V[2]
01111111CELL.TIE_0
10011111CELL.DOUBLE_IO_E1[0]
10101111CELL.DOUBLE_IO_E1[1]
10110111CELL.DOUBLE_IO_E2[0]
spartanxl IO_E0 switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[16][3]MAIN[14][3]MAIN[18][2]MAIN[23][2]MAIN[17][3]MAIN[25][2]MAIN[16][2]MAIN[15][2]CELL.IMUX_IO_T[1]
Source
00011111CELL.TIE_0
00101011CELL.LONG_IO_V[1]
00101101CELL.LONG_IO_V[3]
00101110CELL.GCLK[0]
00110101CELL.LONG_IO_V[0]
01101111CELL.DOUBLE_IO_E1[0]
01110111CELL.DOUBLE_IO_E2[0]
10111011CELL.DOUBLE_IO_E2[1]
10111101CELL.LONG_IO_V[2]
11111111CELL.DOUBLE_IO_E1[1]

Bels TBUF

spartanxl IO_E0 bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
spartanxl IO_E0 bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[25][3]!MAIN[13][3]

Bels IO

spartanxl IO_E0 bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[2][6]CELL.IMUX_IO_IK[1] invert by !MAIN[2][3]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[1][9]CELL.IMUX_IO_OK[1] invert by !MAIN[2][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_G1CELL.IMUX_CLB_F1
TinCELL.IMUX_IO_T[0] invert by !MAIN[0][9]CELL.IMUX_IO_T[1] invert by !MAIN[1][0]
I1outCELL.OUT_IO_WE_I1[0]CELL.OUT_IO_WE_I1[1]
I2outCELL.OUT_IO_WE_I2[0]CELL.OUT_IO_WE_I2[1]
spartanxl IO_E0 bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[3][6]!MAIN[9][3]
OFF_SRVAL bit 0!MAIN[1][7]!MAIN[1][1]
READBACK_I1 bit 0!MAIN[0][8]!MAIN[4][3]
READBACK_I2 bit 0!MAIN[2][8]!MAIN[3][3]
READBACK_OQ bit 0!MAIN[3][8]!MAIN[2][2]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[3][7]!MAIN[1][2]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[4][7]MAIN[3][2]
IFF_CE_ENABLE!MAIN[18][8]!MAIN[18][7]
OFF_CE_ENABLE!MAIN[18][9]!MAIN[18][6]
SYNC_D[enum: IO_SYNC_D][enum: IO_SYNC_D]
IFF_CE_ENABLE_NO_IQ!MAIN[5][5]!MAIN[4][5]
MUX_T[enum: IO_MUX_T][enum: IO_MUX_T]
DRIVE[enum: IO_DRIVE][enum: IO_DRIVE]
_5V_TOLERANTMAIN[6][6]MAIN[5][6]
spartanxl IO_E0 enum IO_SLEW
IO[0].SLEWMAIN[2][9]
IO[1].SLEWMAIN[0][0]
FAST0
SLOW1
spartanxl IO_E0 enum IO_PULL
IO[0].PULLMAIN[8][6]MAIN[2][7]
IO[1].PULLMAIN[0][1]MAIN[2][1]
NONE11
PULLUP01
PULLDOWN10
spartanxl IO_E0 enum IO_MUX_I
IO[0].MUX_I1MAIN[2][5]MAIN[1][5]
IO[1].MUX_I1MAIN[2][4]MAIN[0][4]
IO[0].MUX_I2MAIN[0][5]MAIN[0][6]
IO[1].MUX_I2MAIN[1][4]MAIN[0][3]
I01
IQ11
IQL10
spartanxl IO_E0 enum IO_IFF_D
IO[0].IFF_DMAIN[3][5]MAIN[1][6]
IO[1].IFF_DMAIN[3][4]MAIN[1][3]
I11
DELAY00
MEDDELAY01
SYNC10
spartanxl IO_E0 enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[0][7]
IO[1].MUX_OFF_DMAIN[0][2]
O11
O20
spartanxl IO_E0 enum IO_MUX_O
IO[0].MUX_OMAIN[4][8]MAIN[1][8]MAIN[3][9]MAIN[4][9]
IO[1].MUX_OMAIN[4][1]MAIN[3][1]MAIN[3][0]MAIN[4][0]
O10000
O1_INV0001
O20111
O2_INV1111
OQ0010
MUX1011
spartanxl IO_E0 enum IO_SYNC_D
IO[0].SYNC_DMAIN[4][6]
IO[1].SYNC_DMAIN[4][2]
I1
DELAY0
spartanxl IO_E0 enum IO_MUX_T
IO[0].MUX_TMAIN[17][2]
IO[1].MUX_TMAIN[18][3]
T1
TQ0
spartanxl IO_E0 enum IO_DRIVE
IO[0].DRIVEMAIN[6][5]
IO[1].DRIVEMAIN[5][3]
_121
_240

Bels PULLUP

spartanxl IO_E0 bel PULLUP pins
PinDirectionPULLUP_TBUF[0]PULLUP_TBUF[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
spartanxl IO_E0 bel PULLUP attribute bits
AttributePULLUP_TBUF[0]PULLUP_TBUF[1]
ENABLE!MAIN_S[25][7]!MAIN[14][7]

Bel wires

spartanxl IO_E0 bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]TBUF[1].O, PULLUP_TBUF[1].O
CELL.IMUX_CLB_F1IO[1].O2
CELL.IMUX_CLB_G1IO[0].O2
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_WE_I1[0]IO[0].I1
CELL.OUT_IO_WE_I1[1]IO[1].I1
CELL.OUT_IO_WE_I2[0]IO[0].I2
CELL.OUT_IO_WE_I2[1]IO[1].I2

Bitstream

spartanxl IO_E0 rect MAIN
BitFrame
F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_E0[3] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E0[3] INT: !bipass CELL.DOUBLE_IO_E0[3] = CELL.DOUBLE_IO_E2[3] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E1[3] INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_E1[3] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E2[3] INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_E2[3] IO[0]: ! OFF_CE_ENABLE - INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E0[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E0[1] INT: !bipass CELL.DOUBLE_IO_E0[1] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E1[1] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E1[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E2[1] - INT: mux CELL.LONG_IO_V[1] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 5 IO[0]: MUX_O bit 0 IO[0]: MUX_O bit 1 IO[0]: SLEW bit 0 IO[0]: !invert OK IO[0]: !invert T
B8 - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_IO_WE_I1[0] INT: mux CELL.LONG_IO_V[2] bit 0 INT: mux CELL.LONG_IO_V[2] bit 1 INT: mux CELL.LONG_IO_V[2] bit 2 INT: mux CELL.LONG_IO_V[2] bit 3 INT: mux CELL.LONG_IO_V[3] bit 1 IO[0]: ! IFF_CE_ENABLE INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_IO_V[3] INT: mux CELL.LONG_IO_V[3] bit 0 INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1 INT: mux CELL.LONG_IO_V[1] bit 0 INT: mux CELL.LONG_IO_V[1] bit 1 INT: mux CELL.LONG_IO_V[1] bit 3 INT: mux CELL.DBUF_IO_V[1] bit 1 INT: mux CELL.DBUF_IO_V[1] bit 0 INT: mux CELL.DBUF_IO_V[1] bit 2 INT: mux CELL.DBUF_IO_V[1] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 4 IO[0]: MUX_O bit 3 IO[0]: ! READBACK_OQ bit 0 IO[0]: ! READBACK_I2 bit 0 IO[0]: MUX_O bit 2 IO[0]: ! READBACK_I1 bit 0
B7 INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H_BUF[3] - INT: mux CELL.LONG_H[4] bit 1 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1_S1 INT: mux CELL.LONG_H[4] bit 0 INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1[0] INT: mux CELL.LONG_H[5] bit 0 IO[1]: ! IFF_CE_ENABLE INT: !pass CELL.DOUBLE_IO_E0[3] ← CELL.DBUF_IO_V[0] INT: !pass CELL.DOUBLE_IO_E0[1] ← CELL.DBUF_IO_V[0] INT: mux CELL.LONG_H[5] bit 2 PULLUP_TBUF[1]: ! ENABLE INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[1] INT: mux CELL.IMUX_IO_IK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 7 IO[0]: OFF_USED IO[0]: ! OFF_D_INV IO[0]: PULL bit 0 IO[0]: ! OFF_SRVAL bit 0 IO[0]: MUX_OFF_D bit 0
B6 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] - INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 - INT: mux CELL.LONG_H[4] bit 2 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.DOUBLE_IO_E2[3] ← CELL.DBUF_IO_V[1] INT: mux CELL.LONG_H[5] bit 1 - INT: !pass CELL.DOUBLE_IO_E0[0] ← CELL.DBUF_IO_V[0] IO[1]: ! OFF_CE_ENABLE INT: !pass CELL.DOUBLE_IO_E0[2] ← CELL.DBUF_IO_V[0] INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: !pass CELL.DOUBLE_IO_E2[1] ← CELL.DBUF_IO_V[1] INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 4 - INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 0 IO[0]: PULL bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 7 IO[0]: _5V_TOLERANT IO[1]: _5V_TOLERANT IO[0]: SYNC_D bit 0 IO[0]: ! IFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: IFF_D bit 0 IO[0]: MUX_I2 bit 0
B5 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E0[0] INT: mux CELL.LONG_IO_V[0] bit 0 INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E0[0] INT: !bipass CELL.DOUBLE_IO_E0[0] = CELL.DOUBLE_IO_E2[0] INT: mux CELL.LONG_IO_V[0] bit 1 INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E1[0] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E1[0] - INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E2[0] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E2[0] INT: !pass CELL.DOUBLE_IO_E2[0] ← CELL.DBUF_IO_V[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E2[2] INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_E2[2] INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[4] - - - INT: mux CELL.IMUX_IO_OK[0] bit 5 - IO[0]: DRIVE bit 0 IO[0]: ! IFF_CE_ENABLE_NO_IQ IO[1]: ! IFF_CE_ENABLE_NO_IQ IO[0]: IFF_D bit 1 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I2 bit 1
B4 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_WE_I2[1] INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_WE_I2[1] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_WE_I2[1] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_WE_I2[0] INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[3] INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[0] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_IO_V[2] INT: mux CELL.IMUX_IO_T[0] bit 6 INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_E0[2] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E0[2] INT: !bipass CELL.DOUBLE_IO_E0[2] = CELL.DOUBLE_IO_E2[2] INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_E1[2] INT: !pass CELL.DOUBLE_IO_E2[2] ← CELL.DBUF_IO_V[1] - - - - - - - - - IO[1]: IFF_D bit 1 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I1 bit 0
B3 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 1 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 1 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 3 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] - INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 6 TBUF[0]: ! DRIVE1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.DBUF_IO_V[0] bit 0 INT: mux CELL.DBUF_IO_V[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 7 INT: mux CELL.IMUX_IO_T[0] bit 3 IO[1]: MUX_T bit 0 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 7 INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E1[2] INT: mux CELL.IMUX_IO_T[1] bit 6 TBUF[1]: ! DRIVE1 INT: mux CELL.IMUX_CLB_G3 bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 0 - IO[1]: ! IFF_SRVAL bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 5 - IO[1]: DRIVE bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I2 bit 0 IO[1]: !invert IK IO[1]: IFF_D bit 0 IO[1]: MUX_I2 bit 0
B2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F1 bit 0 INT: mux CELL.IMUX_CLB_F1 bit 7 - - - - INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.DBUF_IO_V[0] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.DBUF_IO_V[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 5 IO[0]: MUX_T bit 0 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 7 IO[1]: SYNC_D bit 0 IO[1]: OFF_USED IO[1]: ! READBACK_OQ bit 0 IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0
B1 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 2 - - INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 3 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.LONG_H[0] bit 1 INT: mux CELL.LONG_H[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 4 - INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 3 - INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 5 - INT: mux CELL.LONG_H[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 7 IO[1]: MUX_O bit 3 IO[1]: MUX_O bit 2 IO[1]: PULL bit 0 IO[1]: ! OFF_SRVAL bit 0 IO[1]: PULL bit 1
B0 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 4 - - INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 7 - INT: mux CELL.LONG_H[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 - INT: mux CELL.IMUX_TBUF_T[0] bit 4 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: mux CELL.LONG_H[1] bit 1 INT: mux CELL.LONG_H[1] bit 0 - - INT: mux CELL.IMUX_IO_O1[1] bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 2 IO[1]: MUX_O bit 0 IO[1]: MUX_O bit 1 IO[1]: !invert OK IO[1]: !invert T IO[1]: SLEW bit 0
spartanxl IO_E0 rect MAIN_S
BitFrame
F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H_BUF[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - PULLUP_TBUF[0]: ! ENABLE - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
spartanxl IO_E0 rect MAIN_W
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_E0_N

Cells: 3

Switchbox INT

spartanxl IO_E0_N switchbox INT permanent buffers
DestinationSource
CELL.LONG_H_BUF[2]CELL.LONG_H[2]
CELL.LONG_H_BUF[3]CELL.LONG_H[3]
spartanxl IO_E0_N switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[26][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[30][8]
CELL.LONG_H[2]CELL.SINGLE_V[3]!MAIN[27][4]
CELL.LONG_H[3]CELL.SINGLE_V[4]!MAIN[12][5]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[38][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[40][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[32][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[38][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[34][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[34][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[31][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[35][8]
spartanxl IO_E0_N switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I2_S1!MAIN[24][4]
CELL.SINGLE_H[1]CELL.LONG_IO_V[0]!MAIN[22][4]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I2[0]!MAIN[21][4]
CELL.SINGLE_H[2]CELL.LONG_IO_V[1]!MAIN[13][7]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I1[0]!MAIN[21][7]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I1_S1!MAIN[15][8]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[33][4]
CELL.SINGLE_H[4]CELL.OUT_IO_WE_I2_S1!MAIN[25][4]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[27][3]
CELL.SINGLE_H[5]CELL.LONG_IO_V[2]!MAIN[19][4]
CELL.SINGLE_H[5]CELL.OUT_IO_WE_I2[0]!MAIN[20][4]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[34][9]
CELL.SINGLE_H[6]CELL.LONG_IO_V[3]!MAIN[17][8]
CELL.SINGLE_H[6]CELL.OUT_IO_WE_I1[0]!MAIN[24][8]
CELL.SINGLE_H[7]CELL.OUT_IO_WE_I1_S1!MAIN[25][8]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[32][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[40][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[39][7]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[26][6]
CELL.SINGLE_V[0]CELL.OUT_IO_WE_I2[0]!MAIN[28][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[28][8]
CELL.SINGLE_V[1]CELL.OUT_IO_WE_I2[1]!MAIN[29][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[34][8]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[30][4]
CELL.SINGLE_V[3]CELL.LONG_H_BUF[2]!MAIN_S[33][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[35][4]
CELL.SINGLE_V[4]CELL.LONG_H_BUF[3]!MAIN[26][7]
CELL.SINGLE_V[4]CELL.OUT_IO_WE_I2[0]!MAIN[39][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[40][5]
CELL.SINGLE_V[5]CELL.OUT_IO_WE_I2[1]!MAIN[36][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[40][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[39][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[26][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[38][3]
CELL.DOUBLE_H0[0]CELL.OUT_IO_WE_I1[0]!MAIN[20][7]
CELL.DOUBLE_H0[1]CELL.OUT_IO_WE_I2_S1!MAIN[23][4]
CELL.DOUBLE_H1[0]CELL.OUT_IO_WE_I1_S1!MAIN[23][7]
CELL.DOUBLE_H1[1]CELL.OUT_IO_WE_I2[0]!MAIN[23][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[26][4]
CELL.DOUBLE_V0[1]CELL.OUT_IO_WE_I2[1]!MAIN[37][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[31][4]
CELL.DOUBLE_V1[1]CELL.OUT_IO_WE_I2[0]!MAIN[40][4]
CELL.DOUBLE_IO_E0[0]CELL.DBUF_IO_V[0]!MAIN[19][6]
CELL.DOUBLE_IO_E0[1]CELL.DBUF_IO_V[0]!MAIN[16][7]
CELL.DOUBLE_IO_E0[2]CELL.DBUF_IO_V[0]!MAIN[17][6]
CELL.DOUBLE_IO_E0[3]CELL.DBUF_IO_V[0]!MAIN[17][7]
CELL.DOUBLE_IO_E2[0]CELL.DBUF_IO_V[1]!MAIN[15][5]
CELL.DOUBLE_IO_E2[1]CELL.DBUF_IO_V[1]!MAIN[15][6]
CELL.DOUBLE_IO_E2[2]CELL.DBUF_IO_V[1]!MAIN[13][4]
CELL.DOUBLE_IO_E2[3]CELL.DBUF_IO_V[1]!MAIN[22][6]
spartanxl IO_E0_N switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[28][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[27][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[30][3]
CELL.SINGLE_H[0]CELL.DOUBLE_IO_E0[0]!MAIN[25][5]
CELL.SINGLE_H[0]CELL.DOUBLE_IO_E2[0]!MAIN[16][5]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[30][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[29][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[29][3]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_E1[0]!MAIN[19][5]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[32][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[31][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[33][8]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_E0[1]!MAIN[16][9]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_E2[1]!MAIN[10][9]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[31][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[28][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[30][7]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_E1[1]!MAIN[12][9]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[36][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[39][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[35][6]
CELL.SINGLE_H[4]CELL.DOUBLE_IO_E0[2]!MAIN[17][4]
CELL.SINGLE_H[4]CELL.DOUBLE_IO_E2[2]!MAIN[13][5]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[35][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[36][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[37][5]
CELL.SINGLE_H[5]CELL.DOUBLE_IO_E1[2]!MAIN[14][4]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[35][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[36][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[36][7]
CELL.SINGLE_H[6]CELL.DOUBLE_IO_E0[3]!MAIN[25][9]
CELL.SINGLE_H[6]CELL.DOUBLE_IO_E2[3]!MAIN[19][9]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[38][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[35][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[37][8]
CELL.SINGLE_H[7]CELL.DOUBLE_IO_E1[3]!MAIN[21][9]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[26][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[28][5]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[30][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[31][5]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[31][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[32][9]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[32][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[33][7]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[39][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[37][6]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[36][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[38][5]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[34][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[37][7]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[37][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[39][9]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[29][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[31][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[30][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[27][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[38][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[39][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[38][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[36][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[29][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[27][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[28][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E0[1]!MAIN[15][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E1[1]!MAIN[13][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E2[1]!MAIN[11][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[33][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[32][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[33][3]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E0[2]!MAIN[16][4]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E1[2]!MAIN[15][3]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E2[2]!MAIN[14][5]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E0[0]!MAIN[23][5]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E1[0]!MAIN[20][5]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E2[0]!MAIN[17][5]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E0[3]!MAIN[24][9]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E1[3]!MAIN[22][9]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E2[3]!MAIN[20][9]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[29][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[29][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[33][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[34][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[27][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[34][3]
CELL.DOUBLE_IO_E0[0]CELL.DOUBLE_IO_E2[0]!MAIN[22][5]
CELL.DOUBLE_IO_E0[1]CELL.DOUBLE_IO_E2[1]!MAIN[14][9]
CELL.DOUBLE_IO_E0[2]CELL.DOUBLE_IO_E2[2]!MAIN[15][4]
CELL.DOUBLE_IO_E0[3]CELL.DOUBLE_IO_E2[3]!MAIN[23][9]
spartanxl IO_E0_N switchbox INT muxes DBUF_IO_V[0]
BitsDestination
MAIN[21][3]MAIN[24][2]MAIN[22][2]MAIN[22][3]CELL.DBUF_IO_V[0]
Source
0011CELL.DOUBLE_IO_E2[0]
0101CELL.DOUBLE_IO_E2[1]
0110CELL.DOUBLE_IO_E2[3]
1111CELL.DOUBLE_IO_E2[2]
spartanxl IO_E0_N switchbox INT muxes DBUF_IO_V[1]
BitsDestination
MAIN[8][8]MAIN[9][8]MAIN[11][8]MAIN[10][8]CELL.DBUF_IO_V[1]
Source
0011CELL.DOUBLE_IO_E0[1]
0101CELL.DOUBLE_IO_E0[2]
0110CELL.DOUBLE_IO_E0[3]
1111CELL.DOUBLE_IO_E0[0]
spartanxl IO_E0_N switchbox INT muxes LONG_H[0]
BitsDestination
MAIN[24][1]MAIN[25][1]MAIN[24][0]CELL.LONG_H[0]
Source
000CELL.LONG_IO_V[0]
011CELL.OUT_IO_WE_I2[1]
111off
spartanxl IO_E0_N switchbox INT muxes LONG_H[1]
BitsDestination
MAIN[10][1]MAIN[11][0]MAIN[10][0]CELL.LONG_H[1]
Source
000CELL.LONG_IO_V[1]
011CELL.OUT_IO_WE_I2[1]
111off
spartanxl IO_E0_N switchbox INT muxes LONG_H[4]
BitsDestination
MAIN[24][6]MAIN[24][7]MAIN[22][7]CELL.LONG_H[4]
Source
000CELL.LONG_IO_V[2]
011CELL.OUT_IO_WE_I2[0]
111off
spartanxl IO_E0_N switchbox INT muxes LONG_H[5]
BitsDestination
MAIN[15][7]MAIN[21][6]MAIN[19][7]CELL.LONG_H[5]
Source
000CELL.LONG_IO_V[3]
011CELL.OUT_IO_WE_I2[0]
111off
spartanxl IO_E0_N switchbox INT muxes LONG_IO_V[0]
BitsDestination
MAIN[21][5]MAIN[24][5]CELL.LONG_IO_V[0]
Source
00CELL.LONG_H[0]
01CELL.SINGLE_H[1]
11off
spartanxl IO_E0_N switchbox INT muxes LONG_IO_V[1]
BitsDestination
MAIN[12][8]MAIN[8][9]MAIN[13][8]MAIN[14][8]CELL.LONG_IO_V[1]
Source
0001CELL.LONG_H[1]
0010CELL.LONG_H_BUF[3]
0111CELL.SINGLE_H[2]
1111off
spartanxl IO_E0_N switchbox INT muxes LONG_IO_V[2]
BitsDestination
MAIN[20][8]MAIN[21][8]MAIN[22][8]MAIN[23][8]CELL.LONG_IO_V[2]
Source
0001CELL.LONG_H[4]
0010CELL.LONG_H_BUF[2]
0111CELL.SINGLE_H[5]
1111off
spartanxl IO_E0_N switchbox INT muxes LONG_IO_V[3]
BitsDestination
MAIN[19][8]MAIN[16][8]CELL.LONG_IO_V[3]
Source
00CELL.LONG_H[5]
01CELL.SINGLE_H[6]
11off
spartanxl IO_E0_N switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[31][2]MAIN[33][0]MAIN[32][1]MAIN[31][0]MAIN[32][3]MAIN[31][1]MAIN[32][0]MAIN[32][2]CELL.IMUX_CLB_F1
Source
00100111CELL.SINGLE_V[3]
00101011CELL.LONG_V[4]
00101110CELL.SINGLE_V[7]
00111111CELL.SINGLE_V[0]
01000111CELL.LONG_V[3]
01001011CELL.DOUBLE_V0[1]
01001110CELL.LONG_V[0]
01011111CELL.SINGLE_V[1]
01100101CELL.SINGLE_V[5]
01101001CELL.LONG_V[1]
01101100CELL.SINGLE_V[6]
01111101CELL.DOUBLE_V1[1]
11100111CELL.DOUBLE_V1[0]
11101011CELL.SINGLE_V[4]
11101110CELL.DOUBLE_V0[0]
11111111CELL.SINGLE_V[2]
spartanxl IO_E0_N switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[38][2]MAIN[40][0]MAIN[39][2]MAIN[40][1]MAIN[38][0]MAIN[39][1]MAIN[40][2]MAIN[39][0]MAIN[40][3]CELL.IMUX_CLB_F3
Source
000011111CELL.SINGLE_V[0]
000111011CELL.DOUBLE_V0[0]
000111101CELL.LONG_V[2]
001111111CELL.SINGLE_V[3]
010001111CELL.DOUBLE_V1[1]
010010111CELL.LONG_V[1]
010101011CELL.DOUBLE_V0[1]
010101101CELL.LONG_V[5]
010110011CELL.SINGLE_V[4]
010110101CELL.LONG_V[4]
010111110CELL.GCLK[0]
011101111CELL.SINGLE_V[1]
011110111CELL.SINGLE_V[2]
110011111CELL.SINGLE_V[6]
110111011CELL.DOUBLE_V1[0]
110111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[7]
spartanxl IO_E0_N switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[26][0]MAIN[26][3]MAIN[28][0]MAIN[28][1]MAIN[27][1]MAIN[26][1]MAIN[27][0]MAIN[26][2]CELL.IMUX_CLB_G1
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[2]
00011101CELL.SINGLE_V[4]
00101011CELL.LONG_V[4]
00101110CELL.LONG_V[3]
00110011CELL.SINGLE_V[1]
00110110CELL.DOUBLE_V1[0]
00111001CELL.DOUBLE_V0[1]
00111100CELL.LONG_V[0]
01101111CELL.SINGLE_V[3]
01110111CELL.DOUBLE_V0[0]
01111101CELL.SINGLE_V[7]
10011111CELL.DOUBLE_V1[1]
10111011CELL.LONG_V[1]
10111110CELL.SINGLE_V[5]
11111111CELL.SINGLE_V[6]
spartanxl IO_E0_N switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[34][0]MAIN[33][2]MAIN[35][1]MAIN[33][1]MAIN[34][2]MAIN[35][0]MAIN[34][1]MAIN[35][2]MAIN[35][3]MAIN[12][3]CELL.IMUX_CLB_G3
Source
0001111111CELL.SPECIAL_CLB_CIN
0010011111CELL.SINGLE_V[0]
0010101111CELL.SINGLE_V[2]
0010111011CELL.SINGLE_V[4]
0011010111CELL.LONG_V[4]
0011011101CELL.LONG_V[2]
0011100111CELL.SINGLE_V[1]
0011101101CELL.SINGLE_V[6]
0011110011CELL.DOUBLE_V0[1]
0011111001CELL.LONG_V[5]
0011111110CELL.GCLK[0]
0111011111CELL.DOUBLE_V0[0]
0111101111CELL.SINGLE_V[5]
0111111011CELL.DOUBLE_V1[0]
1010111111CELL.DOUBLE_V1[1]
1011110111CELL.LONG_V[1]
1011111101CELL.SINGLE_V[7]
1111111111CELL.SINGLE_V[3]
spartanxl IO_E0_N switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[36][0]MAIN[36][1]MAIN[37][1]MAIN[37][0]MAIN[36][2]MAIN[37][2]MAIN[37][3]MAIN[38][1]CELL.IMUX_CLB_C3
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[2]
00011110CELL.GCLK[2]
00101011CELL.SINGLE_V[3]
00101101CELL.SINGLE_V[7]
00110011CELL.DOUBLE_V0[0]
00110101CELL.DOUBLE_V1[0]
00111010CELL.LONG_V[3]
00111100CELL.LONG_V[2]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[1]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
spartanxl IO_E0_N switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[23][1]MAIN[21][0]MAIN[23][0]MAIN[21][1]MAIN[22][0]CELL.IMUX_TBUF_I[0]
Source
00011CELL.DOUBLE_IO_E2[2]
00101CELL.OUT_IO_WE_I2[0]
00110CELL.LONG_IO_V[2]
01111CELL.DOUBLE_IO_E1[2]
10011CELL.DOUBLE_IO_E1[3]
10101CELL.DOUBLE_IO_E2[3]
10110CELL.OUT_IO_WE_I2[1]
11111CELL.TIE_0
spartanxl IO_E0_N switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[12][1]MAIN[14][1]MAIN[12][0]MAIN[14][0]MAIN[13][0]MAIN[13][1]CELL.IMUX_TBUF_I[1]
Source
000111CELL.DOUBLE_IO_E1[2]
001111CELL.DOUBLE_IO_E1[3]
010011CELL.OUT_IO_WE_I2[0]
010101CELL.LONG_IO_V[1]
011011CELL.DOUBLE_IO_E2[3]
011110CELL.OUT_IO_WE_I2[1]
110111CELL.DOUBLE_IO_E2[2]
111111CELL.TIE_0
spartanxl IO_E0_N switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[17][0]MAIN[19][0]MAIN[20][0]MAIN[20][1]MAIN[19][1]CELL.IMUX_TBUF_T[0]
Source
00011CELL.TIE_1
00111CELL.TIE_0
01001CELL.DOUBLE_IO_E2[0]
01010CELL.LONG_IO_V[3]
01101CELL.DOUBLE_IO_E1[0]
01110CELL.LONG_IO_V[2]
11011CELL.DOUBLE_IO_E2[1]
11111CELL.DOUBLE_IO_E1[1]
spartanxl IO_E0_N switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[15][0]MAIN[17][1]MAIN[15][1]MAIN[18][1]MAIN[16][0]CELL.IMUX_TBUF_T[1]
Source
00011CELL.TIE_1
00111CELL.TIE_0
01001CELL.DOUBLE_IO_E1[1]
01010CELL.LONG_IO_V[2]
01101CELL.DOUBLE_IO_E2[1]
01110CELL.LONG_IO_V[3]
11011CELL.DOUBLE_IO_E1[0]
11111CELL.DOUBLE_IO_E2[0]
spartanxl IO_E0_N switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[5][9]MAIN[5][8]MAIN[7][8]MAIN[6][9]MAIN[6][8]MAIN[7][9]CELL.IMUX_IO_O1[0]
Source
011111CELL.DOUBLE_H0[1]
100111CELL.DOUBLE_H1[0]
101011CELL.LONG_H[4]
101101CELL.LONG_H[5]
101110CELL.LONG_H_BUF[3]
111111CELL.TIE_0
spartanxl IO_E0_N switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[6][0]MAIN[5][0]MAIN[9][1]MAIN[7][0]CELL.IMUX_IO_O1[1]
Source
0001CELL.LONG_H[0]
0010CELL.LONG_H[1]
0101CELL_S.DOUBLE_H1[1]
0110CELL.LONG_H_BUF[2]
1011CELL_S.DOUBLE_H0[0]
1111CELL.TIE_0
spartanxl IO_E0_N switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[7][6]MAIN[16][6]MAIN[8][5]MAIN[13][6]MAIN[10][6]MAIN[11][6]MAIN[14][6]MAIN[9][6]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_H[2]
01011111CELL.SINGLE_H[3]
01101111CELL.SINGLE_H[5]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[4]
spartanxl IO_E0_N switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[5][2]MAIN[7][2]MAIN[8][2]MAIN[12][2]MAIN[6][2]MAIN[13][2]MAIN[14][2]MAIN[9][2]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[2]
01111101CELL_S.SINGLE_H[3]
01111110CELL_S.SINGLE_H[4]
11111111CELL_S.SINGLE_H[5]
spartanxl IO_E0_N switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[5][7]MAIN[11][7]MAIN[12][7]MAIN[9][7]MAIN[7][7]MAIN[8][7]MAIN[10][7]MAIN[6][7]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_H[3]
01011111CELL.SINGLE_H[4]
01101111CELL.SINGLE_H[5]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[2]
spartanxl IO_E0_N switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[5][1]MAIN[7][1]MAIN[7][3]MAIN[11][2]MAIN[6][1]MAIN[8][1]MAIN[10][2]MAIN[11][3]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[2]
01111101CELL_S.SINGLE_H[4]
01111110CELL_S.SINGLE_H[5]
11111111CELL_S.SINGLE_H[3]
spartanxl IO_E0_N switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[20][3]MAIN[18][4]MAIN[19][2]MAIN[21][2]MAIN[19][3]MAIN[23][3]MAIN[20][2]MAIN[24][3]CELL.IMUX_IO_T[0]
Source
00011011CELL.LONG_IO_V[3]
00011101CELL.LONG_IO_V[1]
00011110CELL.GCLK[0]
00101011CELL.LONG_IO_V[0]
00110011CELL.DOUBLE_IO_E2[1]
00110101CELL.LONG_IO_V[2]
01111111CELL.TIE_0
10011111CELL.DOUBLE_IO_E1[0]
10101111CELL.DOUBLE_IO_E1[1]
10110111CELL.DOUBLE_IO_E2[0]
spartanxl IO_E0_N switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[16][3]MAIN[14][3]MAIN[18][2]MAIN[23][2]MAIN[17][3]MAIN[25][2]MAIN[16][2]MAIN[15][2]CELL.IMUX_IO_T[1]
Source
00011111CELL.TIE_0
00101011CELL.LONG_IO_V[1]
00101101CELL.LONG_IO_V[3]
00101110CELL.GCLK[0]
00110101CELL.LONG_IO_V[0]
01101111CELL.DOUBLE_IO_E1[0]
01110111CELL.DOUBLE_IO_E2[0]
10111011CELL.DOUBLE_IO_E2[1]
10111101CELL.LONG_IO_V[2]
11111111CELL.DOUBLE_IO_E1[1]

Bels TBUF

spartanxl IO_E0_N bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
spartanxl IO_E0_N bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[25][3]!MAIN[13][3]

Bels IO

spartanxl IO_E0_N bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[2][6]CELL.IMUX_IO_IK[1] invert by !MAIN[2][3]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[1][9]CELL.IMUX_IO_OK[1] invert by !MAIN[2][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_G1CELL.IMUX_CLB_F1
TinCELL.IMUX_IO_T[0] invert by !MAIN[0][9]CELL.IMUX_IO_T[1] invert by !MAIN[1][0]
I1outCELL.OUT_IO_WE_I1[0]CELL.OUT_IO_WE_I1[1]
I2outCELL.OUT_IO_WE_I2[0]CELL.OUT_IO_WE_I2[1]
CLKINoutCELL.OUT_IO_CLKIN-
spartanxl IO_E0_N bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[3][6]!MAIN[9][3]
OFF_SRVAL bit 0!MAIN[1][7]!MAIN[1][1]
READBACK_I1 bit 0!MAIN[0][8]!MAIN[4][3]
READBACK_I2 bit 0!MAIN[2][8]!MAIN[3][3]
READBACK_OQ bit 0!MAIN[3][8]!MAIN[2][2]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[3][7]!MAIN[1][2]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[4][7]MAIN[3][2]
IFF_CE_ENABLE!MAIN[18][8]!MAIN[18][7]
OFF_CE_ENABLE!MAIN[18][9]!MAIN[18][6]
SYNC_D[enum: IO_SYNC_D][enum: IO_SYNC_D]
IFF_CE_ENABLE_NO_IQ!MAIN[5][5]!MAIN[4][5]
MUX_T[enum: IO_MUX_T][enum: IO_MUX_T]
DRIVE[enum: IO_DRIVE][enum: IO_DRIVE]
_5V_TOLERANTMAIN[6][6]MAIN[5][6]
spartanxl IO_E0_N enum IO_SLEW
IO[0].SLEWMAIN[2][9]
IO[1].SLEWMAIN[0][0]
FAST0
SLOW1
spartanxl IO_E0_N enum IO_PULL
IO[0].PULLMAIN[8][6]MAIN[2][7]
IO[1].PULLMAIN[0][1]MAIN[2][1]
NONE11
PULLUP01
PULLDOWN10
spartanxl IO_E0_N enum IO_MUX_I
IO[0].MUX_I1MAIN[2][5]MAIN[1][5]
IO[1].MUX_I1MAIN[2][4]MAIN[0][4]
IO[0].MUX_I2MAIN[0][5]MAIN[0][6]
IO[1].MUX_I2MAIN[1][4]MAIN[0][3]
I01
IQ11
IQL10
spartanxl IO_E0_N enum IO_IFF_D
IO[0].IFF_DMAIN[3][5]MAIN[1][6]
IO[1].IFF_DMAIN[3][4]MAIN[1][3]
I11
DELAY00
MEDDELAY01
SYNC10
spartanxl IO_E0_N enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[0][7]
IO[1].MUX_OFF_DMAIN[0][2]
O11
O20
spartanxl IO_E0_N enum IO_MUX_O
IO[0].MUX_OMAIN[4][8]MAIN[1][8]MAIN[3][9]MAIN[4][9]
IO[1].MUX_OMAIN[4][1]MAIN[3][1]MAIN[3][0]MAIN[4][0]
O10000
O1_INV0001
O20111
O2_INV1111
OQ0010
MUX1011
spartanxl IO_E0_N enum IO_SYNC_D
IO[0].SYNC_DMAIN[4][6]
IO[1].SYNC_DMAIN[4][2]
I1
DELAY0
spartanxl IO_E0_N enum IO_MUX_T
IO[0].MUX_TMAIN[17][2]
IO[1].MUX_TMAIN[18][3]
T1
TQ0
spartanxl IO_E0_N enum IO_DRIVE
IO[0].DRIVEMAIN[6][5]
IO[1].DRIVEMAIN[5][3]
_121
_240

Bels PULLUP

spartanxl IO_E0_N bel PULLUP pins
PinDirectionPULLUP_TBUF[0]PULLUP_TBUF[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
spartanxl IO_E0_N bel PULLUP attribute bits
AttributePULLUP_TBUF[0]PULLUP_TBUF[1]
ENABLE!MAIN_S[25][7]!MAIN[14][7]

Bel wires

spartanxl IO_E0_N bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]TBUF[1].O, PULLUP_TBUF[1].O
CELL.IMUX_CLB_F1IO[1].O2
CELL.IMUX_CLB_G1IO[0].O2
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_WE_I1[0]IO[0].I1
CELL.OUT_IO_WE_I1[1]IO[1].I1
CELL.OUT_IO_WE_I2[0]IO[0].I2
CELL.OUT_IO_WE_I2[1]IO[1].I2
CELL.OUT_IO_CLKINIO[0].CLKIN

Bitstream

spartanxl IO_E0_N rect MAIN
BitFrame
F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_E0[3] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E0[3] INT: !bipass CELL.DOUBLE_IO_E0[3] = CELL.DOUBLE_IO_E2[3] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E1[3] INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_E1[3] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E2[3] INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_E2[3] IO[0]: ! OFF_CE_ENABLE - INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E0[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E0[1] INT: !bipass CELL.DOUBLE_IO_E0[1] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E1[1] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E1[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E2[1] - INT: mux CELL.LONG_IO_V[1] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 5 IO[0]: MUX_O bit 0 IO[0]: MUX_O bit 1 IO[0]: SLEW bit 0 IO[0]: !invert OK IO[0]: !invert T
B8 - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_IO_WE_I1[0] INT: mux CELL.LONG_IO_V[2] bit 0 INT: mux CELL.LONG_IO_V[2] bit 1 INT: mux CELL.LONG_IO_V[2] bit 2 INT: mux CELL.LONG_IO_V[2] bit 3 INT: mux CELL.LONG_IO_V[3] bit 1 IO[0]: ! IFF_CE_ENABLE INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_IO_V[3] INT: mux CELL.LONG_IO_V[3] bit 0 INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1 INT: mux CELL.LONG_IO_V[1] bit 0 INT: mux CELL.LONG_IO_V[1] bit 1 INT: mux CELL.LONG_IO_V[1] bit 3 INT: mux CELL.DBUF_IO_V[1] bit 1 INT: mux CELL.DBUF_IO_V[1] bit 0 INT: mux CELL.DBUF_IO_V[1] bit 2 INT: mux CELL.DBUF_IO_V[1] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 4 IO[0]: MUX_O bit 3 IO[0]: ! READBACK_OQ bit 0 IO[0]: ! READBACK_I2 bit 0 IO[0]: MUX_O bit 2 IO[0]: ! READBACK_I1 bit 0
B7 INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H_BUF[3] - INT: mux CELL.LONG_H[4] bit 1 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1_S1 INT: mux CELL.LONG_H[4] bit 0 INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1[0] INT: mux CELL.LONG_H[5] bit 0 IO[1]: ! IFF_CE_ENABLE INT: !pass CELL.DOUBLE_IO_E0[3] ← CELL.DBUF_IO_V[0] INT: !pass CELL.DOUBLE_IO_E0[1] ← CELL.DBUF_IO_V[0] INT: mux CELL.LONG_H[5] bit 2 PULLUP_TBUF[1]: ! ENABLE INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[1] INT: mux CELL.IMUX_IO_IK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 7 IO[0]: OFF_USED IO[0]: ! OFF_D_INV IO[0]: PULL bit 0 IO[0]: ! OFF_SRVAL bit 0 IO[0]: MUX_OFF_D bit 0
B6 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] - INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 - INT: mux CELL.LONG_H[4] bit 2 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.DOUBLE_IO_E2[3] ← CELL.DBUF_IO_V[1] INT: mux CELL.LONG_H[5] bit 1 - INT: !pass CELL.DOUBLE_IO_E0[0] ← CELL.DBUF_IO_V[0] IO[1]: ! OFF_CE_ENABLE INT: !pass CELL.DOUBLE_IO_E0[2] ← CELL.DBUF_IO_V[0] INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: !pass CELL.DOUBLE_IO_E2[1] ← CELL.DBUF_IO_V[1] INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 4 - INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 0 IO[0]: PULL bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 7 IO[0]: _5V_TOLERANT IO[1]: _5V_TOLERANT IO[0]: SYNC_D bit 0 IO[0]: ! IFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: IFF_D bit 0 IO[0]: MUX_I2 bit 0
B5 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E0[0] INT: mux CELL.LONG_IO_V[0] bit 0 INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E0[0] INT: !bipass CELL.DOUBLE_IO_E0[0] = CELL.DOUBLE_IO_E2[0] INT: mux CELL.LONG_IO_V[0] bit 1 INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E1[0] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E1[0] - INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E2[0] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E2[0] INT: !pass CELL.DOUBLE_IO_E2[0] ← CELL.DBUF_IO_V[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E2[2] INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_E2[2] INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[4] - - - INT: mux CELL.IMUX_IO_OK[0] bit 5 - IO[0]: DRIVE bit 0 IO[0]: ! IFF_CE_ENABLE_NO_IQ IO[1]: ! IFF_CE_ENABLE_NO_IQ IO[0]: IFF_D bit 1 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I2 bit 1
B4 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_WE_I2[1] INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_WE_I2[1] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_WE_I2[1] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_WE_I2[0] INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[3] INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[0] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_IO_V[2] INT: mux CELL.IMUX_IO_T[0] bit 6 INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_E0[2] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E0[2] INT: !bipass CELL.DOUBLE_IO_E0[2] = CELL.DOUBLE_IO_E2[2] INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_E1[2] INT: !pass CELL.DOUBLE_IO_E2[2] ← CELL.DBUF_IO_V[1] - - - - - - - - - IO[1]: IFF_D bit 1 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I1 bit 0
B3 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 1 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 1 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 3 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] - INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 6 TBUF[0]: ! DRIVE1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.DBUF_IO_V[0] bit 0 INT: mux CELL.DBUF_IO_V[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 7 INT: mux CELL.IMUX_IO_T[0] bit 3 IO[1]: MUX_T bit 0 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 7 INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E1[2] INT: mux CELL.IMUX_IO_T[1] bit 6 TBUF[1]: ! DRIVE1 INT: mux CELL.IMUX_CLB_G3 bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 0 - IO[1]: ! IFF_SRVAL bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 5 - IO[1]: DRIVE bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I2 bit 0 IO[1]: !invert IK IO[1]: IFF_D bit 0 IO[1]: MUX_I2 bit 0
B2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F1 bit 0 INT: mux CELL.IMUX_CLB_F1 bit 7 - - - - INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.DBUF_IO_V[0] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.DBUF_IO_V[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 5 IO[0]: MUX_T bit 0 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 7 IO[1]: SYNC_D bit 0 IO[1]: OFF_USED IO[1]: ! READBACK_OQ bit 0 IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0
B1 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 2 - - INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 3 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.LONG_H[0] bit 1 INT: mux CELL.LONG_H[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 4 - INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 3 - INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 5 - INT: mux CELL.LONG_H[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 7 IO[1]: MUX_O bit 3 IO[1]: MUX_O bit 2 IO[1]: PULL bit 0 IO[1]: ! OFF_SRVAL bit 0 IO[1]: PULL bit 1
B0 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 4 - - INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 7 - INT: mux CELL.LONG_H[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 - INT: mux CELL.IMUX_TBUF_T[0] bit 4 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: mux CELL.LONG_H[1] bit 1 INT: mux CELL.LONG_H[1] bit 0 - - INT: mux CELL.IMUX_IO_O1[1] bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 2 IO[1]: MUX_O bit 0 IO[1]: MUX_O bit 1 IO[1]: !invert OK IO[1]: !invert T IO[1]: SLEW bit 0
spartanxl IO_E0_N rect MAIN_S
BitFrame
F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H_BUF[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - PULLUP_TBUF[0]: ! ENABLE - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
spartanxl IO_E0_N rect MAIN_W
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_E1

Cells: 3

Switchbox INT

spartanxl IO_E1 switchbox INT permanent buffers
DestinationSource
CELL.LONG_H_BUF[2]CELL.LONG_H[2]
CELL.LONG_H_BUF[3]CELL.LONG_H[3]
spartanxl IO_E1 switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[26][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[30][8]
CELL.LONG_H[2]CELL.SINGLE_V[3]!MAIN[27][4]
CELL.LONG_H[3]CELL.SINGLE_V[4]!MAIN[12][5]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[38][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[40][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[32][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[38][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[34][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[34][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[31][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[35][8]
spartanxl IO_E1 switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I2_S1!MAIN[24][4]
CELL.SINGLE_H[1]CELL.LONG_IO_V[0]!MAIN[22][4]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I2[0]!MAIN[21][4]
CELL.SINGLE_H[2]CELL.LONG_IO_V[1]!MAIN[13][7]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I1[0]!MAIN[21][7]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I1_S1!MAIN[15][8]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[33][4]
CELL.SINGLE_H[4]CELL.OUT_IO_WE_I2_S1!MAIN[25][4]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[27][3]
CELL.SINGLE_H[5]CELL.LONG_IO_V[2]!MAIN[19][4]
CELL.SINGLE_H[5]CELL.OUT_IO_WE_I2[0]!MAIN[20][4]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[34][9]
CELL.SINGLE_H[6]CELL.LONG_IO_V[3]!MAIN[17][8]
CELL.SINGLE_H[6]CELL.OUT_IO_WE_I1[0]!MAIN[24][8]
CELL.SINGLE_H[7]CELL.OUT_IO_WE_I1_S1!MAIN[25][8]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[32][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[40][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[39][7]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[26][6]
CELL.SINGLE_V[0]CELL.OUT_IO_WE_I2[0]!MAIN[28][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[28][8]
CELL.SINGLE_V[1]CELL.OUT_IO_WE_I2[1]!MAIN[29][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[34][8]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[30][4]
CELL.SINGLE_V[3]CELL.LONG_H_BUF[2]!MAIN_S[33][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[35][4]
CELL.SINGLE_V[4]CELL.LONG_H_BUF[3]!MAIN[26][7]
CELL.SINGLE_V[4]CELL.OUT_IO_WE_I2[0]!MAIN[39][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[40][5]
CELL.SINGLE_V[5]CELL.OUT_IO_WE_I2[1]!MAIN[36][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[40][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[39][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[26][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[38][3]
CELL.DOUBLE_H0[0]CELL.OUT_IO_WE_I1[0]!MAIN[20][7]
CELL.DOUBLE_H0[1]CELL.OUT_IO_WE_I2_S1!MAIN[23][4]
CELL.DOUBLE_H1[0]CELL.OUT_IO_WE_I1_S1!MAIN[23][7]
CELL.DOUBLE_H1[1]CELL.OUT_IO_WE_I2[0]!MAIN[23][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[26][4]
CELL.DOUBLE_V0[1]CELL.OUT_IO_WE_I2[1]!MAIN[37][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[31][4]
CELL.DOUBLE_V1[1]CELL.OUT_IO_WE_I2[0]!MAIN[40][4]
CELL.DOUBLE_IO_E0[0]CELL.DBUF_IO_V[0]!MAIN[19][6]
CELL.DOUBLE_IO_E0[1]CELL.DBUF_IO_V[0]!MAIN[16][7]
CELL.DOUBLE_IO_E0[2]CELL.DBUF_IO_V[0]!MAIN[17][6]
CELL.DOUBLE_IO_E0[3]CELL.DBUF_IO_V[0]!MAIN[17][7]
CELL.DOUBLE_IO_E2[0]CELL.DBUF_IO_V[1]!MAIN[15][5]
CELL.DOUBLE_IO_E2[1]CELL.DBUF_IO_V[1]!MAIN[15][6]
CELL.DOUBLE_IO_E2[2]CELL.DBUF_IO_V[1]!MAIN[13][4]
CELL.DOUBLE_IO_E2[3]CELL.DBUF_IO_V[1]!MAIN[22][6]
spartanxl IO_E1 switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[28][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[27][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[30][3]
CELL.SINGLE_H[0]CELL.DOUBLE_IO_E1[0]!MAIN[19][5]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[30][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[29][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[29][3]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_E0[0]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_E2[0]!MAIN[16][5]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[32][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[31][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[33][8]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_E1[1]!MAIN[12][9]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[31][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[28][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[30][7]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_E0[1]!MAIN[16][9]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_E2[1]!MAIN[10][9]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[36][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[39][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[35][6]
CELL.SINGLE_H[4]CELL.DOUBLE_IO_E1[2]!MAIN[14][4]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[35][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[36][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[37][5]
CELL.SINGLE_H[5]CELL.DOUBLE_IO_E0[2]!MAIN[17][4]
CELL.SINGLE_H[5]CELL.DOUBLE_IO_E2[2]!MAIN[13][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[35][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[36][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[36][7]
CELL.SINGLE_H[6]CELL.DOUBLE_IO_E1[3]!MAIN[21][9]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[38][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[35][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[37][8]
CELL.SINGLE_H[7]CELL.DOUBLE_IO_E0[3]!MAIN[25][9]
CELL.SINGLE_H[7]CELL.DOUBLE_IO_E2[3]!MAIN[19][9]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[26][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[28][5]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[30][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[31][5]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[31][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[32][9]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[32][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[33][7]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[39][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[37][6]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[36][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[38][5]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[34][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[37][7]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[37][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[39][9]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[29][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[31][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[30][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[27][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[38][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[39][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[38][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[36][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[29][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[27][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[28][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E0[1]!MAIN[15][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E1[1]!MAIN[13][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E2[1]!MAIN[11][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[33][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[32][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[33][3]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E0[2]!MAIN[16][4]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E1[2]!MAIN[15][3]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E2[2]!MAIN[14][5]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E0[0]!MAIN[23][5]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E1[0]!MAIN[20][5]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E2[0]!MAIN[17][5]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E0[3]!MAIN[24][9]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E1[3]!MAIN[22][9]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E2[3]!MAIN[20][9]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[29][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[29][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[33][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[34][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[27][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[34][3]
CELL.DOUBLE_IO_E0[0]CELL.DOUBLE_IO_E2[0]!MAIN[22][5]
CELL.DOUBLE_IO_E0[1]CELL.DOUBLE_IO_E2[1]!MAIN[14][9]
CELL.DOUBLE_IO_E0[2]CELL.DOUBLE_IO_E2[2]!MAIN[15][4]
CELL.DOUBLE_IO_E0[3]CELL.DOUBLE_IO_E2[3]!MAIN[23][9]
spartanxl IO_E1 switchbox INT muxes DBUF_IO_V[0]
BitsDestination
MAIN[21][3]MAIN[24][2]MAIN[22][2]MAIN[22][3]CELL.DBUF_IO_V[0]
Source
0011CELL.DOUBLE_IO_E2[0]
0101CELL.DOUBLE_IO_E2[1]
0110CELL.DOUBLE_IO_E2[3]
1111CELL.DOUBLE_IO_E2[2]
spartanxl IO_E1 switchbox INT muxes DBUF_IO_V[1]
BitsDestination
MAIN[8][8]MAIN[9][8]MAIN[11][8]MAIN[10][8]CELL.DBUF_IO_V[1]
Source
0011CELL.DOUBLE_IO_E0[1]
0101CELL.DOUBLE_IO_E0[2]
0110CELL.DOUBLE_IO_E0[3]
1111CELL.DOUBLE_IO_E0[0]
spartanxl IO_E1 switchbox INT muxes LONG_H[0]
BitsDestination
MAIN[24][1]MAIN[25][1]MAIN[24][0]CELL.LONG_H[0]
Source
000CELL.LONG_IO_V[0]
011CELL.OUT_IO_WE_I2[1]
111off
spartanxl IO_E1 switchbox INT muxes LONG_H[1]
BitsDestination
MAIN[10][1]MAIN[11][0]MAIN[10][0]CELL.LONG_H[1]
Source
000CELL.LONG_IO_V[1]
011CELL.OUT_IO_WE_I2[1]
111off
spartanxl IO_E1 switchbox INT muxes LONG_H[4]
BitsDestination
MAIN[24][6]MAIN[24][7]MAIN[22][7]CELL.LONG_H[4]
Source
000CELL.LONG_IO_V[2]
011CELL.OUT_IO_WE_I2[0]
111off
spartanxl IO_E1 switchbox INT muxes LONG_H[5]
BitsDestination
MAIN[15][7]MAIN[21][6]MAIN[19][7]CELL.LONG_H[5]
Source
000CELL.LONG_IO_V[3]
011CELL.OUT_IO_WE_I2[0]
111off
spartanxl IO_E1 switchbox INT muxes LONG_IO_V[0]
BitsDestination
MAIN[21][5]MAIN[24][5]CELL.LONG_IO_V[0]
Source
00CELL.LONG_H[0]
01CELL.SINGLE_H[1]
11off
spartanxl IO_E1 switchbox INT muxes LONG_IO_V[1]
BitsDestination
MAIN[12][8]MAIN[8][9]MAIN[13][8]MAIN[14][8]CELL.LONG_IO_V[1]
Source
0001CELL.LONG_H[1]
0010CELL.LONG_H_BUF[3]
0111CELL.SINGLE_H[2]
1111off
spartanxl IO_E1 switchbox INT muxes LONG_IO_V[2]
BitsDestination
MAIN[20][8]MAIN[21][8]MAIN[22][8]MAIN[23][8]CELL.LONG_IO_V[2]
Source
0001CELL.LONG_H[4]
0010CELL.LONG_H_BUF[2]
0111CELL.SINGLE_H[5]
1111off
spartanxl IO_E1 switchbox INT muxes LONG_IO_V[3]
BitsDestination
MAIN[19][8]MAIN[16][8]CELL.LONG_IO_V[3]
Source
00CELL.LONG_H[5]
01CELL.SINGLE_H[6]
11off
spartanxl IO_E1 switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[31][2]MAIN[33][0]MAIN[32][1]MAIN[31][0]MAIN[32][3]MAIN[31][1]MAIN[32][0]MAIN[32][2]CELL.IMUX_CLB_F1
Source
00100111CELL.SINGLE_V[3]
00101011CELL.LONG_V[4]
00101110CELL.SINGLE_V[7]
00111111CELL.SINGLE_V[0]
01000111CELL.LONG_V[3]
01001011CELL.DOUBLE_V0[1]
01001110CELL.LONG_V[0]
01011111CELL.SINGLE_V[1]
01100101CELL.SINGLE_V[5]
01101001CELL.LONG_V[1]
01101100CELL.SINGLE_V[6]
01111101CELL.DOUBLE_V1[1]
11100111CELL.DOUBLE_V1[0]
11101011CELL.SINGLE_V[4]
11101110CELL.DOUBLE_V0[0]
11111111CELL.SINGLE_V[2]
spartanxl IO_E1 switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[38][2]MAIN[40][0]MAIN[39][2]MAIN[40][1]MAIN[38][0]MAIN[39][1]MAIN[40][2]MAIN[39][0]MAIN[40][3]CELL.IMUX_CLB_F3
Source
000011111CELL.SINGLE_V[0]
000111011CELL.DOUBLE_V0[0]
000111101CELL.LONG_V[2]
001111111CELL.SINGLE_V[3]
010001111CELL.DOUBLE_V1[1]
010010111CELL.LONG_V[1]
010101011CELL.DOUBLE_V0[1]
010101101CELL.LONG_V[5]
010110011CELL.SINGLE_V[4]
010110101CELL.LONG_V[4]
010111110CELL.GCLK[0]
011101111CELL.SINGLE_V[1]
011110111CELL.SINGLE_V[2]
110011111CELL.SINGLE_V[6]
110111011CELL.DOUBLE_V1[0]
110111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[7]
spartanxl IO_E1 switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[26][0]MAIN[26][3]MAIN[28][0]MAIN[28][1]MAIN[27][1]MAIN[26][1]MAIN[27][0]MAIN[26][2]CELL.IMUX_CLB_G1
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[2]
00011101CELL.SINGLE_V[4]
00101011CELL.LONG_V[4]
00101110CELL.LONG_V[3]
00110011CELL.SINGLE_V[1]
00110110CELL.DOUBLE_V1[0]
00111001CELL.DOUBLE_V0[1]
00111100CELL.LONG_V[0]
01101111CELL.SINGLE_V[3]
01110111CELL.DOUBLE_V0[0]
01111101CELL.SINGLE_V[7]
10011111CELL.DOUBLE_V1[1]
10111011CELL.LONG_V[1]
10111110CELL.SINGLE_V[5]
11111111CELL.SINGLE_V[6]
spartanxl IO_E1 switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[34][0]MAIN[33][2]MAIN[35][1]MAIN[33][1]MAIN[34][2]MAIN[35][0]MAIN[34][1]MAIN[35][2]MAIN[35][3]MAIN[12][3]CELL.IMUX_CLB_G3
Source
0001111111CELL.SPECIAL_CLB_CIN
0010011111CELL.SINGLE_V[0]
0010101111CELL.SINGLE_V[2]
0010111011CELL.SINGLE_V[4]
0011010111CELL.LONG_V[4]
0011011101CELL.LONG_V[2]
0011100111CELL.SINGLE_V[1]
0011101101CELL.SINGLE_V[6]
0011110011CELL.DOUBLE_V0[1]
0011111001CELL.LONG_V[5]
0011111110CELL.GCLK[0]
0111011111CELL.DOUBLE_V0[0]
0111101111CELL.SINGLE_V[5]
0111111011CELL.DOUBLE_V1[0]
1010111111CELL.DOUBLE_V1[1]
1011110111CELL.LONG_V[1]
1011111101CELL.SINGLE_V[7]
1111111111CELL.SINGLE_V[3]
spartanxl IO_E1 switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[36][0]MAIN[36][1]MAIN[37][1]MAIN[37][0]MAIN[36][2]MAIN[37][2]MAIN[37][3]MAIN[38][1]CELL.IMUX_CLB_C3
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[2]
00011110CELL.GCLK[2]
00101011CELL.SINGLE_V[3]
00101101CELL.SINGLE_V[7]
00110011CELL.DOUBLE_V0[0]
00110101CELL.DOUBLE_V1[0]
00111010CELL.LONG_V[3]
00111100CELL.LONG_V[2]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[1]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
spartanxl IO_E1 switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[23][1]MAIN[21][0]MAIN[23][0]MAIN[21][1]MAIN[22][0]CELL.IMUX_TBUF_I[0]
Source
00011CELL.DOUBLE_IO_E2[2]
00101CELL.OUT_IO_WE_I2[0]
00110CELL.LONG_IO_V[2]
01111CELL.DOUBLE_IO_E1[2]
10011CELL.DOUBLE_IO_E1[3]
10101CELL.DOUBLE_IO_E2[3]
10110CELL.OUT_IO_WE_I2[1]
11111CELL.TIE_0
spartanxl IO_E1 switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[12][1]MAIN[14][1]MAIN[12][0]MAIN[14][0]MAIN[13][0]MAIN[13][1]CELL.IMUX_TBUF_I[1]
Source
000111CELL.DOUBLE_IO_E1[2]
001111CELL.DOUBLE_IO_E1[3]
010011CELL.OUT_IO_WE_I2[0]
010101CELL.LONG_IO_V[1]
011011CELL.DOUBLE_IO_E2[3]
011110CELL.OUT_IO_WE_I2[1]
110111CELL.DOUBLE_IO_E2[2]
111111CELL.TIE_0
spartanxl IO_E1 switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[17][0]MAIN[19][0]MAIN[20][0]MAIN[20][1]MAIN[19][1]CELL.IMUX_TBUF_T[0]
Source
00011CELL.TIE_1
00111CELL.TIE_0
01001CELL.DOUBLE_IO_E2[0]
01010CELL.LONG_IO_V[3]
01101CELL.DOUBLE_IO_E1[0]
01110CELL.LONG_IO_V[2]
11011CELL.DOUBLE_IO_E2[1]
11111CELL.DOUBLE_IO_E1[1]
spartanxl IO_E1 switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[15][0]MAIN[17][1]MAIN[15][1]MAIN[18][1]MAIN[16][0]CELL.IMUX_TBUF_T[1]
Source
00011CELL.TIE_1
00111CELL.TIE_0
01001CELL.DOUBLE_IO_E1[1]
01010CELL.LONG_IO_V[2]
01101CELL.DOUBLE_IO_E2[1]
01110CELL.LONG_IO_V[3]
11011CELL.DOUBLE_IO_E1[0]
11111CELL.DOUBLE_IO_E2[0]
spartanxl IO_E1 switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[5][9]MAIN[5][8]MAIN[7][8]MAIN[6][9]MAIN[6][8]MAIN[7][9]CELL.IMUX_IO_O1[0]
Source
011111CELL.DOUBLE_H0[1]
100111CELL.DOUBLE_H1[0]
101011CELL.LONG_H[4]
101101CELL.LONG_H[5]
101110CELL.LONG_H_BUF[3]
111111CELL.TIE_0
spartanxl IO_E1 switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[6][0]MAIN[5][0]MAIN[9][1]MAIN[7][0]CELL.IMUX_IO_O1[1]
Source
0001CELL.LONG_H[0]
0010CELL.LONG_H[1]
0101CELL_S.DOUBLE_H1[1]
0110CELL.LONG_H_BUF[2]
1011CELL_S.DOUBLE_H0[0]
1111CELL.TIE_0
spartanxl IO_E1 switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[7][6]MAIN[16][6]MAIN[8][5]MAIN[13][6]MAIN[10][6]MAIN[11][6]MAIN[14][6]MAIN[9][6]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_H[2]
01011111CELL.SINGLE_H[3]
01101111CELL.SINGLE_H[5]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[4]
spartanxl IO_E1 switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[5][2]MAIN[7][2]MAIN[8][2]MAIN[12][2]MAIN[6][2]MAIN[13][2]MAIN[14][2]MAIN[9][2]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[2]
01111101CELL_S.SINGLE_H[3]
01111110CELL_S.SINGLE_H[4]
11111111CELL_S.SINGLE_H[5]
spartanxl IO_E1 switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[5][7]MAIN[11][7]MAIN[12][7]MAIN[9][7]MAIN[7][7]MAIN[8][7]MAIN[10][7]MAIN[6][7]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_H[3]
01011111CELL.SINGLE_H[4]
01101111CELL.SINGLE_H[5]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[2]
spartanxl IO_E1 switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[5][1]MAIN[7][1]MAIN[7][3]MAIN[11][2]MAIN[6][1]MAIN[8][1]MAIN[10][2]MAIN[11][3]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[2]
01111101CELL_S.SINGLE_H[4]
01111110CELL_S.SINGLE_H[5]
11111111CELL_S.SINGLE_H[3]
spartanxl IO_E1 switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[20][3]MAIN[18][4]MAIN[19][2]MAIN[21][2]MAIN[19][3]MAIN[23][3]MAIN[20][2]MAIN[24][3]CELL.IMUX_IO_T[0]
Source
00011011CELL.LONG_IO_V[3]
00011101CELL.LONG_IO_V[1]
00011110CELL.GCLK[0]
00101011CELL.LONG_IO_V[0]
00110011CELL.DOUBLE_IO_E2[1]
00110101CELL.LONG_IO_V[2]
01111111CELL.TIE_0
10011111CELL.DOUBLE_IO_E1[0]
10101111CELL.DOUBLE_IO_E1[1]
10110111CELL.DOUBLE_IO_E2[0]
spartanxl IO_E1 switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[16][3]MAIN[14][3]MAIN[18][2]MAIN[23][2]MAIN[17][3]MAIN[25][2]MAIN[16][2]MAIN[15][2]CELL.IMUX_IO_T[1]
Source
00011111CELL.TIE_0
00101011CELL.LONG_IO_V[1]
00101101CELL.LONG_IO_V[3]
00101110CELL.GCLK[0]
00110101CELL.LONG_IO_V[0]
01101111CELL.DOUBLE_IO_E1[0]
01110111CELL.DOUBLE_IO_E2[0]
10111011CELL.DOUBLE_IO_E2[1]
10111101CELL.LONG_IO_V[2]
11111111CELL.DOUBLE_IO_E1[1]

Bels TBUF

spartanxl IO_E1 bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
spartanxl IO_E1 bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[25][3]!MAIN[13][3]

Bels IO

spartanxl IO_E1 bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[2][6]CELL.IMUX_IO_IK[1] invert by !MAIN[2][3]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[1][9]CELL.IMUX_IO_OK[1] invert by !MAIN[2][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_G1CELL.IMUX_CLB_F1
TinCELL.IMUX_IO_T[0] invert by !MAIN[0][9]CELL.IMUX_IO_T[1] invert by !MAIN[1][0]
I1outCELL.OUT_IO_WE_I1[0]CELL.OUT_IO_WE_I1[1]
I2outCELL.OUT_IO_WE_I2[0]CELL.OUT_IO_WE_I2[1]
spartanxl IO_E1 bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[3][6]!MAIN[9][3]
OFF_SRVAL bit 0!MAIN[1][7]!MAIN[1][1]
READBACK_I1 bit 0!MAIN[0][8]!MAIN[4][3]
READBACK_I2 bit 0!MAIN[2][8]!MAIN[3][3]
READBACK_OQ bit 0!MAIN[3][8]!MAIN[2][2]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[3][7]!MAIN[1][2]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[4][7]MAIN[3][2]
IFF_CE_ENABLE!MAIN[18][8]!MAIN[18][7]
OFF_CE_ENABLE!MAIN[18][9]!MAIN[18][6]
SYNC_D[enum: IO_SYNC_D][enum: IO_SYNC_D]
IFF_CE_ENABLE_NO_IQ!MAIN[5][5]!MAIN[4][5]
MUX_T[enum: IO_MUX_T][enum: IO_MUX_T]
DRIVE[enum: IO_DRIVE][enum: IO_DRIVE]
_5V_TOLERANTMAIN[6][6]MAIN[5][6]
spartanxl IO_E1 enum IO_SLEW
IO[0].SLEWMAIN[2][9]
IO[1].SLEWMAIN[0][0]
FAST0
SLOW1
spartanxl IO_E1 enum IO_PULL
IO[0].PULLMAIN[8][6]MAIN[2][7]
IO[1].PULLMAIN[0][1]MAIN[2][1]
NONE11
PULLUP01
PULLDOWN10
spartanxl IO_E1 enum IO_MUX_I
IO[0].MUX_I1MAIN[2][5]MAIN[1][5]
IO[1].MUX_I1MAIN[2][4]MAIN[0][4]
IO[0].MUX_I2MAIN[0][5]MAIN[0][6]
IO[1].MUX_I2MAIN[1][4]MAIN[0][3]
I01
IQ11
IQL10
spartanxl IO_E1 enum IO_IFF_D
IO[0].IFF_DMAIN[3][5]MAIN[1][6]
IO[1].IFF_DMAIN[3][4]MAIN[1][3]
I11
DELAY00
MEDDELAY01
SYNC10
spartanxl IO_E1 enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[0][7]
IO[1].MUX_OFF_DMAIN[0][2]
O11
O20
spartanxl IO_E1 enum IO_MUX_O
IO[0].MUX_OMAIN[4][8]MAIN[1][8]MAIN[3][9]MAIN[4][9]
IO[1].MUX_OMAIN[4][1]MAIN[3][1]MAIN[3][0]MAIN[4][0]
O10000
O1_INV0001
O20111
O2_INV1111
OQ0010
MUX1011
spartanxl IO_E1 enum IO_SYNC_D
IO[0].SYNC_DMAIN[4][6]
IO[1].SYNC_DMAIN[4][2]
I1
DELAY0
spartanxl IO_E1 enum IO_MUX_T
IO[0].MUX_TMAIN[17][2]
IO[1].MUX_TMAIN[18][3]
T1
TQ0
spartanxl IO_E1 enum IO_DRIVE
IO[0].DRIVEMAIN[6][5]
IO[1].DRIVEMAIN[5][3]
_121
_240

Bels PULLUP

spartanxl IO_E1 bel PULLUP pins
PinDirectionPULLUP_TBUF[0]PULLUP_TBUF[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
spartanxl IO_E1 bel PULLUP attribute bits
AttributePULLUP_TBUF[0]PULLUP_TBUF[1]
ENABLE!MAIN_S[25][7]!MAIN[14][7]

Bel wires

spartanxl IO_E1 bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]TBUF[1].O, PULLUP_TBUF[1].O
CELL.IMUX_CLB_F1IO[1].O2
CELL.IMUX_CLB_G1IO[0].O2
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_WE_I1[0]IO[0].I1
CELL.OUT_IO_WE_I1[1]IO[1].I1
CELL.OUT_IO_WE_I2[0]IO[0].I2
CELL.OUT_IO_WE_I2[1]IO[1].I2

Bitstream

spartanxl IO_E1 rect MAIN
BitFrame
F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_E0[3] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E0[3] INT: !bipass CELL.DOUBLE_IO_E0[3] = CELL.DOUBLE_IO_E2[3] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E1[3] INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_E1[3] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E2[3] INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_E2[3] IO[0]: ! OFF_CE_ENABLE - INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E0[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E0[1] INT: !bipass CELL.DOUBLE_IO_E0[1] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E1[1] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E1[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E2[1] - INT: mux CELL.LONG_IO_V[1] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 5 IO[0]: MUX_O bit 0 IO[0]: MUX_O bit 1 IO[0]: SLEW bit 0 IO[0]: !invert OK IO[0]: !invert T
B8 - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_IO_WE_I1[0] INT: mux CELL.LONG_IO_V[2] bit 0 INT: mux CELL.LONG_IO_V[2] bit 1 INT: mux CELL.LONG_IO_V[2] bit 2 INT: mux CELL.LONG_IO_V[2] bit 3 INT: mux CELL.LONG_IO_V[3] bit 1 IO[0]: ! IFF_CE_ENABLE INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_IO_V[3] INT: mux CELL.LONG_IO_V[3] bit 0 INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1 INT: mux CELL.LONG_IO_V[1] bit 0 INT: mux CELL.LONG_IO_V[1] bit 1 INT: mux CELL.LONG_IO_V[1] bit 3 INT: mux CELL.DBUF_IO_V[1] bit 1 INT: mux CELL.DBUF_IO_V[1] bit 0 INT: mux CELL.DBUF_IO_V[1] bit 2 INT: mux CELL.DBUF_IO_V[1] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 4 IO[0]: MUX_O bit 3 IO[0]: ! READBACK_OQ bit 0 IO[0]: ! READBACK_I2 bit 0 IO[0]: MUX_O bit 2 IO[0]: ! READBACK_I1 bit 0
B7 INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H_BUF[3] - INT: mux CELL.LONG_H[4] bit 1 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1_S1 INT: mux CELL.LONG_H[4] bit 0 INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1[0] INT: mux CELL.LONG_H[5] bit 0 IO[1]: ! IFF_CE_ENABLE INT: !pass CELL.DOUBLE_IO_E0[3] ← CELL.DBUF_IO_V[0] INT: !pass CELL.DOUBLE_IO_E0[1] ← CELL.DBUF_IO_V[0] INT: mux CELL.LONG_H[5] bit 2 PULLUP_TBUF[1]: ! ENABLE INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[1] INT: mux CELL.IMUX_IO_IK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 7 IO[0]: OFF_USED IO[0]: ! OFF_D_INV IO[0]: PULL bit 0 IO[0]: ! OFF_SRVAL bit 0 IO[0]: MUX_OFF_D bit 0
B6 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] - INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 - INT: mux CELL.LONG_H[4] bit 2 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.DOUBLE_IO_E2[3] ← CELL.DBUF_IO_V[1] INT: mux CELL.LONG_H[5] bit 1 - INT: !pass CELL.DOUBLE_IO_E0[0] ← CELL.DBUF_IO_V[0] IO[1]: ! OFF_CE_ENABLE INT: !pass CELL.DOUBLE_IO_E0[2] ← CELL.DBUF_IO_V[0] INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: !pass CELL.DOUBLE_IO_E2[1] ← CELL.DBUF_IO_V[1] INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 4 - INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 0 IO[0]: PULL bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 7 IO[0]: _5V_TOLERANT IO[1]: _5V_TOLERANT IO[0]: SYNC_D bit 0 IO[0]: ! IFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: IFF_D bit 0 IO[0]: MUX_I2 bit 0
B5 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E0[0] INT: mux CELL.LONG_IO_V[0] bit 0 INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E0[0] INT: !bipass CELL.DOUBLE_IO_E0[0] = CELL.DOUBLE_IO_E2[0] INT: mux CELL.LONG_IO_V[0] bit 1 INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E1[0] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E1[0] - INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E2[0] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E2[0] INT: !pass CELL.DOUBLE_IO_E2[0] ← CELL.DBUF_IO_V[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E2[2] INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_E2[2] INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[4] - - - INT: mux CELL.IMUX_IO_OK[0] bit 5 - IO[0]: DRIVE bit 0 IO[0]: ! IFF_CE_ENABLE_NO_IQ IO[1]: ! IFF_CE_ENABLE_NO_IQ IO[0]: IFF_D bit 1 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I2 bit 1
B4 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_WE_I2[1] INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_WE_I2[1] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_WE_I2[1] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_WE_I2[0] INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[3] INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[0] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_IO_V[2] INT: mux CELL.IMUX_IO_T[0] bit 6 INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_E0[2] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E0[2] INT: !bipass CELL.DOUBLE_IO_E0[2] = CELL.DOUBLE_IO_E2[2] INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_E1[2] INT: !pass CELL.DOUBLE_IO_E2[2] ← CELL.DBUF_IO_V[1] - - - - - - - - - IO[1]: IFF_D bit 1 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I1 bit 0
B3 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 1 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 1 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 3 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] - INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 6 TBUF[0]: ! DRIVE1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.DBUF_IO_V[0] bit 0 INT: mux CELL.DBUF_IO_V[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 7 INT: mux CELL.IMUX_IO_T[0] bit 3 IO[1]: MUX_T bit 0 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 7 INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E1[2] INT: mux CELL.IMUX_IO_T[1] bit 6 TBUF[1]: ! DRIVE1 INT: mux CELL.IMUX_CLB_G3 bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 0 - IO[1]: ! IFF_SRVAL bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 5 - IO[1]: DRIVE bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I2 bit 0 IO[1]: !invert IK IO[1]: IFF_D bit 0 IO[1]: MUX_I2 bit 0
B2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F1 bit 0 INT: mux CELL.IMUX_CLB_F1 bit 7 - - - - INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.DBUF_IO_V[0] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.DBUF_IO_V[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 5 IO[0]: MUX_T bit 0 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 7 IO[1]: SYNC_D bit 0 IO[1]: OFF_USED IO[1]: ! READBACK_OQ bit 0 IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0
B1 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 2 - - INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 3 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.LONG_H[0] bit 1 INT: mux CELL.LONG_H[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 4 - INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 3 - INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 5 - INT: mux CELL.LONG_H[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 7 IO[1]: MUX_O bit 3 IO[1]: MUX_O bit 2 IO[1]: PULL bit 0 IO[1]: ! OFF_SRVAL bit 0 IO[1]: PULL bit 1
B0 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 4 - - INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 7 - INT: mux CELL.LONG_H[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 - INT: mux CELL.IMUX_TBUF_T[0] bit 4 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: mux CELL.LONG_H[1] bit 1 INT: mux CELL.LONG_H[1] bit 0 - - INT: mux CELL.IMUX_IO_O1[1] bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 2 IO[1]: MUX_O bit 0 IO[1]: MUX_O bit 1 IO[1]: !invert OK IO[1]: !invert T IO[1]: SLEW bit 0
spartanxl IO_E1 rect MAIN_S
BitFrame
F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H_BUF[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - PULLUP_TBUF[0]: ! ENABLE - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
spartanxl IO_E1 rect MAIN_W
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_E1_S

Cells: 3

Switchbox INT

spartanxl IO_E1_S switchbox INT permanent buffers
DestinationSource
CELL.LONG_H_BUF[2]CELL.LONG_H[2]
CELL.LONG_H_BUF[3]CELL.LONG_H[3]
spartanxl IO_E1_S switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[26][11]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[30][11]
CELL.LONG_H[2]CELL.SINGLE_V[3]!MAIN[27][4]
CELL.LONG_H[3]CELL.SINGLE_V[4]!MAIN[12][5]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[38][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[40][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[32][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[38][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[34][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[34][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[31][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[35][8]
spartanxl IO_E1_S switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I2_S1!MAIN[24][4]
CELL.SINGLE_H[1]CELL.LONG_IO_V[0]!MAIN[22][4]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I2[0]!MAIN[21][4]
CELL.SINGLE_H[2]CELL.LONG_IO_V[1]!MAIN[13][7]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I1[0]!MAIN[21][7]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I1_S1!MAIN[15][8]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[33][4]
CELL.SINGLE_H[4]CELL.OUT_IO_WE_I2_S1!MAIN[25][4]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[27][3]
CELL.SINGLE_H[5]CELL.LONG_IO_V[2]!MAIN[19][4]
CELL.SINGLE_H[5]CELL.OUT_IO_WE_I2[0]!MAIN[20][4]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[34][9]
CELL.SINGLE_H[6]CELL.LONG_IO_V[3]!MAIN[17][8]
CELL.SINGLE_H[6]CELL.OUT_IO_WE_I1[0]!MAIN[24][8]
CELL.SINGLE_H[7]CELL.OUT_IO_WE_I1_S1!MAIN[25][8]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[32][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[40][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[39][7]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[26][6]
CELL.SINGLE_V[0]CELL.OUT_IO_WE_I2[0]!MAIN[28][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[28][11]
CELL.SINGLE_V[1]CELL.OUT_IO_WE_I2[1]!MAIN[29][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[34][11]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[30][4]
CELL.SINGLE_V[3]CELL.LONG_H_BUF[2]!MAIN_S[33][12]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[35][4]
CELL.SINGLE_V[4]CELL.LONG_H_BUF[3]!MAIN[26][7]
CELL.SINGLE_V[4]CELL.OUT_IO_WE_I2[0]!MAIN[39][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[40][5]
CELL.SINGLE_V[5]CELL.OUT_IO_WE_I2[1]!MAIN[36][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[40][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[39][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[26][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[38][3]
CELL.DOUBLE_H0[0]CELL.OUT_IO_WE_I1[0]!MAIN[20][7]
CELL.DOUBLE_H0[1]CELL.OUT_IO_WE_I2_S1!MAIN[23][4]
CELL.DOUBLE_H1[0]CELL.OUT_IO_WE_I1_S1!MAIN[23][7]
CELL.DOUBLE_H1[1]CELL.OUT_IO_WE_I2[0]!MAIN[23][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[26][4]
CELL.DOUBLE_V0[1]CELL.OUT_IO_WE_I2[1]!MAIN[37][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[31][4]
CELL.DOUBLE_V1[1]CELL.OUT_IO_WE_I2[0]!MAIN[40][4]
CELL.DOUBLE_IO_E0[0]CELL.DBUF_IO_V[0]!MAIN[19][6]
CELL.DOUBLE_IO_E0[1]CELL.DBUF_IO_V[0]!MAIN[16][7]
CELL.DOUBLE_IO_E0[2]CELL.DBUF_IO_V[0]!MAIN[17][6]
CELL.DOUBLE_IO_E0[3]CELL.DBUF_IO_V[0]!MAIN[17][7]
CELL.DOUBLE_IO_E2[0]CELL.DBUF_IO_V[1]!MAIN[15][5]
CELL.DOUBLE_IO_E2[1]CELL.DBUF_IO_V[1]!MAIN[15][6]
CELL.DOUBLE_IO_E2[2]CELL.DBUF_IO_V[1]!MAIN[13][4]
CELL.DOUBLE_IO_E2[3]CELL.DBUF_IO_V[1]!MAIN[22][6]
spartanxl IO_E1_S switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[28][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[27][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[30][3]
CELL.SINGLE_H[0]CELL.DOUBLE_IO_E1[0]!MAIN[19][5]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[30][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[29][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[29][3]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_E0[0]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_E2[0]!MAIN[16][5]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[32][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[31][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[33][8]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_E1[1]!MAIN[12][9]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[31][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[28][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[30][7]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_E0[1]!MAIN[16][9]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_E2[1]!MAIN[10][9]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[36][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[39][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[35][6]
CELL.SINGLE_H[4]CELL.DOUBLE_IO_E1[2]!MAIN[14][4]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[35][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[36][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[37][5]
CELL.SINGLE_H[5]CELL.DOUBLE_IO_E0[2]!MAIN[17][4]
CELL.SINGLE_H[5]CELL.DOUBLE_IO_E2[2]!MAIN[13][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[35][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[36][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[36][7]
CELL.SINGLE_H[6]CELL.DOUBLE_IO_E1[3]!MAIN[21][9]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[38][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[35][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[37][8]
CELL.SINGLE_H[7]CELL.DOUBLE_IO_E0[3]!MAIN[25][9]
CELL.SINGLE_H[7]CELL.DOUBLE_IO_E2[3]!MAIN[19][9]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[26][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[28][5]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[30][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[31][5]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[31][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[32][9]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[32][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[33][7]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[39][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[37][6]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[36][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[38][5]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[34][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[37][7]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[37][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[39][9]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[29][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[31][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[30][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[27][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[38][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[39][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[38][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[36][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[29][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[27][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[28][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E0[1]!MAIN[15][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E1[1]!MAIN[13][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E2[1]!MAIN[11][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[33][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[32][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[33][3]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E0[2]!MAIN[16][4]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E1[2]!MAIN[15][3]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E2[2]!MAIN[14][5]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E0[0]!MAIN[23][5]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E1[0]!MAIN[20][5]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E2[0]!MAIN[17][5]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E0[3]!MAIN[24][9]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E1[3]!MAIN[22][9]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E2[3]!MAIN[20][9]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[29][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[29][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[33][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[34][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[27][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[34][3]
CELL.DOUBLE_IO_E0[0]CELL.DOUBLE_IO_E2[0]!MAIN[22][5]
CELL.DOUBLE_IO_E0[1]CELL.DOUBLE_IO_E2[1]!MAIN[14][9]
CELL.DOUBLE_IO_E0[2]CELL.DOUBLE_IO_E2[2]!MAIN[15][4]
CELL.DOUBLE_IO_E0[3]CELL.DOUBLE_IO_E2[3]!MAIN[23][9]
spartanxl IO_E1_S switchbox INT muxes DBUF_IO_V[0]
BitsDestination
MAIN[21][3]MAIN[24][2]MAIN[22][2]MAIN[22][3]CELL.DBUF_IO_V[0]
Source
0011CELL.DOUBLE_IO_E2[0]
0101CELL.DOUBLE_IO_E2[1]
0110CELL.DOUBLE_IO_E2[3]
1111CELL.DOUBLE_IO_E2[2]
spartanxl IO_E1_S switchbox INT muxes DBUF_IO_V[1]
BitsDestination
MAIN[8][8]MAIN[9][8]MAIN[11][8]MAIN[10][8]CELL.DBUF_IO_V[1]
Source
0011CELL.DOUBLE_IO_E0[1]
0101CELL.DOUBLE_IO_E0[2]
0110CELL.DOUBLE_IO_E0[3]
1111CELL.DOUBLE_IO_E0[0]
spartanxl IO_E1_S switchbox INT muxes LONG_H[0]
BitsDestination
MAIN[24][1]MAIN[25][1]MAIN[24][0]CELL.LONG_H[0]
Source
000CELL.LONG_IO_V[0]
011CELL.OUT_IO_WE_I2[1]
111off
spartanxl IO_E1_S switchbox INT muxes LONG_H[1]
BitsDestination
MAIN[10][1]MAIN[11][0]MAIN[10][0]CELL.LONG_H[1]
Source
000CELL.LONG_IO_V[1]
011CELL.OUT_IO_WE_I2[1]
111off
spartanxl IO_E1_S switchbox INT muxes LONG_H[4]
BitsDestination
MAIN[24][6]MAIN[24][7]MAIN[22][7]CELL.LONG_H[4]
Source
000CELL.LONG_IO_V[2]
011CELL.OUT_IO_WE_I2[0]
111off
spartanxl IO_E1_S switchbox INT muxes LONG_H[5]
BitsDestination
MAIN[15][7]MAIN[21][6]MAIN[19][7]CELL.LONG_H[5]
Source
000CELL.LONG_IO_V[3]
011CELL.OUT_IO_WE_I2[0]
111off
spartanxl IO_E1_S switchbox INT muxes LONG_IO_V[0]
BitsDestination
MAIN[21][5]MAIN[24][5]CELL.LONG_IO_V[0]
Source
00CELL.LONG_H[0]
01CELL.SINGLE_H[1]
11off
spartanxl IO_E1_S switchbox INT muxes LONG_IO_V[1]
BitsDestination
MAIN[12][8]MAIN[8][9]MAIN[13][8]MAIN[14][8]CELL.LONG_IO_V[1]
Source
0001CELL.LONG_H[1]
0010CELL.LONG_H_BUF[3]
0111CELL.SINGLE_H[2]
1111off
spartanxl IO_E1_S switchbox INT muxes LONG_IO_V[2]
BitsDestination
MAIN[20][8]MAIN[21][8]MAIN[22][8]MAIN[23][8]CELL.LONG_IO_V[2]
Source
0001CELL.LONG_H[4]
0010CELL.LONG_H_BUF[2]
0111CELL.SINGLE_H[5]
1111off
spartanxl IO_E1_S switchbox INT muxes LONG_IO_V[3]
BitsDestination
MAIN[19][8]MAIN[16][8]CELL.LONG_IO_V[3]
Source
00CELL.LONG_H[5]
01CELL.SINGLE_H[6]
11off
spartanxl IO_E1_S switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[31][2]MAIN[33][0]MAIN[32][1]MAIN[31][0]MAIN[32][3]MAIN[31][1]MAIN[32][0]MAIN[32][2]CELL.IMUX_CLB_F1
Source
00100111CELL.SINGLE_V[3]
00101011CELL.LONG_V[4]
00101110CELL.SINGLE_V[7]
00111111CELL.SINGLE_V[0]
01000111CELL.LONG_V[3]
01001011CELL.DOUBLE_V0[1]
01001110CELL.LONG_V[0]
01011111CELL.SINGLE_V[1]
01100101CELL.SINGLE_V[5]
01101001CELL.LONG_V[1]
01101100CELL.SINGLE_V[6]
01111101CELL.DOUBLE_V1[1]
11100111CELL.DOUBLE_V1[0]
11101011CELL.SINGLE_V[4]
11101110CELL.DOUBLE_V0[0]
11111111CELL.SINGLE_V[2]
spartanxl IO_E1_S switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[38][2]MAIN[40][0]MAIN[39][2]MAIN[40][1]MAIN[38][0]MAIN[39][1]MAIN[40][2]MAIN[39][0]MAIN[40][3]CELL.IMUX_CLB_F3
Source
000011111CELL.SINGLE_V[0]
000111011CELL.DOUBLE_V0[0]
000111101CELL.LONG_V[2]
001111111CELL.SINGLE_V[3]
010001111CELL.DOUBLE_V1[1]
010010111CELL.LONG_V[1]
010101011CELL.DOUBLE_V0[1]
010101101CELL.LONG_V[5]
010110011CELL.SINGLE_V[4]
010110101CELL.LONG_V[4]
010111110CELL.GCLK[0]
011101111CELL.SINGLE_V[1]
011110111CELL.SINGLE_V[2]
110011111CELL.SINGLE_V[6]
110111011CELL.DOUBLE_V1[0]
110111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[7]
spartanxl IO_E1_S switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[26][0]MAIN[26][3]MAIN[28][0]MAIN[28][1]MAIN[27][1]MAIN[26][1]MAIN[27][0]MAIN[26][2]CELL.IMUX_CLB_G1
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[2]
00011101CELL.SINGLE_V[4]
00101011CELL.LONG_V[4]
00101110CELL.LONG_V[3]
00110011CELL.SINGLE_V[1]
00110110CELL.DOUBLE_V1[0]
00111001CELL.DOUBLE_V0[1]
00111100CELL.LONG_V[0]
01101111CELL.SINGLE_V[3]
01110111CELL.DOUBLE_V0[0]
01111101CELL.SINGLE_V[7]
10011111CELL.DOUBLE_V1[1]
10111011CELL.LONG_V[1]
10111110CELL.SINGLE_V[5]
11111111CELL.SINGLE_V[6]
spartanxl IO_E1_S switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[34][0]MAIN[33][2]MAIN[35][1]MAIN[33][1]MAIN[34][2]MAIN[35][0]MAIN[34][1]MAIN[35][2]MAIN[35][3]MAIN[12][3]CELL.IMUX_CLB_G3
Source
0001111111CELL.SPECIAL_CLB_CIN
0010011111CELL.SINGLE_V[0]
0010101111CELL.SINGLE_V[2]
0010111011CELL.SINGLE_V[4]
0011010111CELL.LONG_V[4]
0011011101CELL.LONG_V[2]
0011100111CELL.SINGLE_V[1]
0011101101CELL.SINGLE_V[6]
0011110011CELL.DOUBLE_V0[1]
0011111001CELL.LONG_V[5]
0011111110CELL.GCLK[0]
0111011111CELL.DOUBLE_V0[0]
0111101111CELL.SINGLE_V[5]
0111111011CELL.DOUBLE_V1[0]
1010111111CELL.DOUBLE_V1[1]
1011110111CELL.LONG_V[1]
1011111101CELL.SINGLE_V[7]
1111111111CELL.SINGLE_V[3]
spartanxl IO_E1_S switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[36][0]MAIN[36][1]MAIN[37][1]MAIN[37][0]MAIN[36][2]MAIN[37][2]MAIN[37][3]MAIN[38][1]CELL.IMUX_CLB_C3
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[2]
00011110CELL.GCLK[2]
00101011CELL.SINGLE_V[3]
00101101CELL.SINGLE_V[7]
00110011CELL.DOUBLE_V0[0]
00110101CELL.DOUBLE_V1[0]
00111010CELL.LONG_V[3]
00111100CELL.LONG_V[2]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[1]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
spartanxl IO_E1_S switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[23][1]MAIN[21][0]MAIN[23][0]MAIN[21][1]MAIN[22][0]CELL.IMUX_TBUF_I[0]
Source
00011CELL.DOUBLE_IO_E2[2]
00101CELL.OUT_IO_WE_I2[0]
00110CELL.LONG_IO_V[2]
01111CELL.DOUBLE_IO_E1[2]
10011CELL.DOUBLE_IO_E1[3]
10101CELL.DOUBLE_IO_E2[3]
10110CELL.OUT_IO_WE_I2[1]
11111CELL.TIE_0
spartanxl IO_E1_S switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[12][1]MAIN[14][1]MAIN[12][0]MAIN[14][0]MAIN[13][0]MAIN[13][1]CELL.IMUX_TBUF_I[1]
Source
000111CELL.DOUBLE_IO_E1[2]
001111CELL.DOUBLE_IO_E1[3]
010011CELL.OUT_IO_WE_I2[0]
010101CELL.LONG_IO_V[1]
011011CELL.DOUBLE_IO_E2[3]
011110CELL.OUT_IO_WE_I2[1]
110111CELL.DOUBLE_IO_E2[2]
111111CELL.TIE_0
spartanxl IO_E1_S switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[17][0]MAIN[19][0]MAIN[20][0]MAIN[20][1]MAIN[19][1]CELL.IMUX_TBUF_T[0]
Source
00011CELL.TIE_1
00111CELL.TIE_0
01001CELL.DOUBLE_IO_E2[0]
01010CELL.LONG_IO_V[3]
01101CELL.DOUBLE_IO_E1[0]
01110CELL.LONG_IO_V[2]
11011CELL.DOUBLE_IO_E2[1]
11111CELL.DOUBLE_IO_E1[1]
spartanxl IO_E1_S switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[15][0]MAIN[17][1]MAIN[15][1]MAIN[18][1]MAIN[16][0]CELL.IMUX_TBUF_T[1]
Source
00011CELL.TIE_1
00111CELL.TIE_0
01001CELL.DOUBLE_IO_E1[1]
01010CELL.LONG_IO_V[2]
01101CELL.DOUBLE_IO_E2[1]
01110CELL.LONG_IO_V[3]
11011CELL.DOUBLE_IO_E1[0]
11111CELL.DOUBLE_IO_E2[0]
spartanxl IO_E1_S switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[5][9]MAIN[5][8]MAIN[7][8]MAIN[6][9]MAIN[6][8]MAIN[7][9]CELL.IMUX_IO_O1[0]
Source
011111CELL.DOUBLE_H0[1]
100111CELL.DOUBLE_H1[0]
101011CELL.LONG_H[4]
101101CELL.LONG_H[5]
101110CELL.LONG_H_BUF[3]
111111CELL.TIE_0
spartanxl IO_E1_S switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[6][0]MAIN[5][0]MAIN[9][1]MAIN[7][0]CELL.IMUX_IO_O1[1]
Source
0001CELL.LONG_H[0]
0010CELL.LONG_H[1]
0101CELL_S.DOUBLE_H1[1]
0110CELL.LONG_H_BUF[2]
1011CELL_S.DOUBLE_H0[0]
1111CELL.TIE_0
spartanxl IO_E1_S switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[7][6]MAIN[16][6]MAIN[8][5]MAIN[13][6]MAIN[10][6]MAIN[11][6]MAIN[14][6]MAIN[9][6]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_H[2]
01011111CELL.SINGLE_H[3]
01101111CELL.SINGLE_H[5]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[4]
spartanxl IO_E1_S switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[5][2]MAIN[7][2]MAIN[8][2]MAIN[12][2]MAIN[6][2]MAIN[13][2]MAIN[14][2]MAIN[9][2]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[2]
01111101CELL_S.SINGLE_H[3]
01111110CELL_S.SINGLE_H[4]
11111111CELL_S.SINGLE_H[5]
spartanxl IO_E1_S switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[5][7]MAIN[11][7]MAIN[12][7]MAIN[9][7]MAIN[7][7]MAIN[8][7]MAIN[10][7]MAIN[6][7]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_H[3]
01011111CELL.SINGLE_H[4]
01101111CELL.SINGLE_H[5]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[2]
spartanxl IO_E1_S switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[5][1]MAIN[7][1]MAIN[7][3]MAIN[11][2]MAIN[6][1]MAIN[8][1]MAIN[10][2]MAIN[11][3]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[2]
01111101CELL_S.SINGLE_H[4]
01111110CELL_S.SINGLE_H[5]
11111111CELL_S.SINGLE_H[3]
spartanxl IO_E1_S switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[20][3]MAIN[18][4]MAIN[19][2]MAIN[21][2]MAIN[19][3]MAIN[23][3]MAIN[20][2]MAIN[24][3]CELL.IMUX_IO_T[0]
Source
00011011CELL.LONG_IO_V[3]
00011101CELL.LONG_IO_V[1]
00011110CELL.GCLK[0]
00101011CELL.LONG_IO_V[0]
00110011CELL.DOUBLE_IO_E2[1]
00110101CELL.LONG_IO_V[2]
01111111CELL.TIE_0
10011111CELL.DOUBLE_IO_E1[0]
10101111CELL.DOUBLE_IO_E1[1]
10110111CELL.DOUBLE_IO_E2[0]
spartanxl IO_E1_S switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[16][3]MAIN[14][3]MAIN[18][2]MAIN[23][2]MAIN[17][3]MAIN[25][2]MAIN[16][2]MAIN[15][2]CELL.IMUX_IO_T[1]
Source
00011111CELL.TIE_0
00101011CELL.LONG_IO_V[1]
00101101CELL.LONG_IO_V[3]
00101110CELL.GCLK[0]
00110101CELL.LONG_IO_V[0]
01101111CELL.DOUBLE_IO_E1[0]
01110111CELL.DOUBLE_IO_E2[0]
10111011CELL.DOUBLE_IO_E2[1]
10111101CELL.LONG_IO_V[2]
11111111CELL.DOUBLE_IO_E1[1]

Bels TBUF

spartanxl IO_E1_S bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
spartanxl IO_E1_S bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[25][3]!MAIN[13][3]

Bels IO

spartanxl IO_E1_S bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[2][6]CELL.IMUX_IO_IK[1] invert by !MAIN[2][3]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[1][9]CELL.IMUX_IO_OK[1] invert by !MAIN[2][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_G1CELL.IMUX_CLB_F1
TinCELL.IMUX_IO_T[0] invert by !MAIN[0][9]CELL.IMUX_IO_T[1] invert by !MAIN[1][0]
I1outCELL.OUT_IO_WE_I1[0]CELL.OUT_IO_WE_I1[1]
I2outCELL.OUT_IO_WE_I2[0]CELL.OUT_IO_WE_I2[1]
CLKINoutCELL.OUT_IO_CLKIN-
spartanxl IO_E1_S bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[3][6]!MAIN[9][3]
OFF_SRVAL bit 0!MAIN[1][7]!MAIN[1][1]
READBACK_I1 bit 0!MAIN[0][8]!MAIN[4][3]
READBACK_I2 bit 0!MAIN[2][8]!MAIN[3][3]
READBACK_OQ bit 0!MAIN[3][8]!MAIN[2][2]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[3][7]!MAIN[1][2]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[4][7]MAIN[3][2]
IFF_CE_ENABLE!MAIN[18][8]!MAIN[18][7]
OFF_CE_ENABLE!MAIN[18][9]!MAIN[18][6]
SYNC_D[enum: IO_SYNC_D][enum: IO_SYNC_D]
IFF_CE_ENABLE_NO_IQ!MAIN[5][5]!MAIN[4][5]
MUX_T[enum: IO_MUX_T][enum: IO_MUX_T]
DRIVE[enum: IO_DRIVE][enum: IO_DRIVE]
_5V_TOLERANTMAIN[6][6]MAIN[5][6]
spartanxl IO_E1_S enum IO_SLEW
IO[0].SLEWMAIN[2][9]
IO[1].SLEWMAIN[0][0]
FAST0
SLOW1
spartanxl IO_E1_S enum IO_PULL
IO[0].PULLMAIN[8][6]MAIN[2][7]
IO[1].PULLMAIN[0][1]MAIN[2][1]
NONE11
PULLUP01
PULLDOWN10
spartanxl IO_E1_S enum IO_MUX_I
IO[0].MUX_I1MAIN[2][5]MAIN[1][5]
IO[1].MUX_I1MAIN[2][4]MAIN[0][4]
IO[0].MUX_I2MAIN[0][5]MAIN[0][6]
IO[1].MUX_I2MAIN[1][4]MAIN[0][3]
I01
IQ11
IQL10
spartanxl IO_E1_S enum IO_IFF_D
IO[0].IFF_DMAIN[3][5]MAIN[1][6]
IO[1].IFF_DMAIN[3][4]MAIN[1][3]
I11
DELAY00
MEDDELAY01
SYNC10
spartanxl IO_E1_S enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[0][7]
IO[1].MUX_OFF_DMAIN[0][2]
O11
O20
spartanxl IO_E1_S enum IO_MUX_O
IO[0].MUX_OMAIN[4][8]MAIN[1][8]MAIN[3][9]MAIN[4][9]
IO[1].MUX_OMAIN[4][1]MAIN[3][1]MAIN[3][0]MAIN[4][0]
O10000
O1_INV0001
O20111
O2_INV1111
OQ0010
MUX1011
spartanxl IO_E1_S enum IO_SYNC_D
IO[0].SYNC_DMAIN[4][6]
IO[1].SYNC_DMAIN[4][2]
I1
DELAY0
spartanxl IO_E1_S enum IO_MUX_T
IO[0].MUX_TMAIN[17][2]
IO[1].MUX_TMAIN[18][3]
T1
TQ0
spartanxl IO_E1_S enum IO_DRIVE
IO[0].DRIVEMAIN[6][5]
IO[1].DRIVEMAIN[5][3]
_121
_240

Bels PULLUP

spartanxl IO_E1_S bel PULLUP pins
PinDirectionPULLUP_TBUF[0]PULLUP_TBUF[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
spartanxl IO_E1_S bel PULLUP attribute bits
AttributePULLUP_TBUF[0]PULLUP_TBUF[1]
ENABLE!MAIN_S[25][12]!MAIN[14][7]

Bel wires

spartanxl IO_E1_S bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]TBUF[1].O, PULLUP_TBUF[1].O
CELL.IMUX_CLB_F1IO[1].O2
CELL.IMUX_CLB_G1IO[0].O2
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_WE_I1[0]IO[0].I1
CELL.OUT_IO_WE_I1[1]IO[1].I1
CELL.OUT_IO_WE_I2[0]IO[0].I2
CELL.OUT_IO_WE_I2[1]IO[1].I2
CELL.OUT_IO_CLKINIO[0].CLKIN

Bitstream

spartanxl IO_E1_S rect MAIN
BitFrame
F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_E0[3] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E0[3] INT: !bipass CELL.DOUBLE_IO_E0[3] = CELL.DOUBLE_IO_E2[3] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E1[3] INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_E1[3] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E2[3] INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_E2[3] IO[0]: ! OFF_CE_ENABLE - INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E0[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E0[1] INT: !bipass CELL.DOUBLE_IO_E0[1] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E1[1] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E1[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E2[1] - INT: mux CELL.LONG_IO_V[1] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 5 IO[0]: MUX_O bit 0 IO[0]: MUX_O bit 1 IO[0]: SLEW bit 0 IO[0]: !invert OK IO[0]: !invert T
B8 - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_IO_WE_I1[0] INT: mux CELL.LONG_IO_V[2] bit 0 INT: mux CELL.LONG_IO_V[2] bit 1 INT: mux CELL.LONG_IO_V[2] bit 2 INT: mux CELL.LONG_IO_V[2] bit 3 INT: mux CELL.LONG_IO_V[3] bit 1 IO[0]: ! IFF_CE_ENABLE INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_IO_V[3] INT: mux CELL.LONG_IO_V[3] bit 0 INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1 INT: mux CELL.LONG_IO_V[1] bit 0 INT: mux CELL.LONG_IO_V[1] bit 1 INT: mux CELL.LONG_IO_V[1] bit 3 INT: mux CELL.DBUF_IO_V[1] bit 1 INT: mux CELL.DBUF_IO_V[1] bit 0 INT: mux CELL.DBUF_IO_V[1] bit 2 INT: mux CELL.DBUF_IO_V[1] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 4 IO[0]: MUX_O bit 3 IO[0]: ! READBACK_OQ bit 0 IO[0]: ! READBACK_I2 bit 0 IO[0]: MUX_O bit 2 IO[0]: ! READBACK_I1 bit 0
B7 INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H_BUF[3] - INT: mux CELL.LONG_H[4] bit 1 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1_S1 INT: mux CELL.LONG_H[4] bit 0 INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1[0] INT: mux CELL.LONG_H[5] bit 0 IO[1]: ! IFF_CE_ENABLE INT: !pass CELL.DOUBLE_IO_E0[3] ← CELL.DBUF_IO_V[0] INT: !pass CELL.DOUBLE_IO_E0[1] ← CELL.DBUF_IO_V[0] INT: mux CELL.LONG_H[5] bit 2 PULLUP_TBUF[1]: ! ENABLE INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[1] INT: mux CELL.IMUX_IO_IK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 7 IO[0]: OFF_USED IO[0]: ! OFF_D_INV IO[0]: PULL bit 0 IO[0]: ! OFF_SRVAL bit 0 IO[0]: MUX_OFF_D bit 0
B6 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] - INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 - INT: mux CELL.LONG_H[4] bit 2 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.DOUBLE_IO_E2[3] ← CELL.DBUF_IO_V[1] INT: mux CELL.LONG_H[5] bit 1 - INT: !pass CELL.DOUBLE_IO_E0[0] ← CELL.DBUF_IO_V[0] IO[1]: ! OFF_CE_ENABLE INT: !pass CELL.DOUBLE_IO_E0[2] ← CELL.DBUF_IO_V[0] INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: !pass CELL.DOUBLE_IO_E2[1] ← CELL.DBUF_IO_V[1] INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 4 - INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 0 IO[0]: PULL bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 7 IO[0]: _5V_TOLERANT IO[1]: _5V_TOLERANT IO[0]: SYNC_D bit 0 IO[0]: ! IFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: IFF_D bit 0 IO[0]: MUX_I2 bit 0
B5 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E0[0] INT: mux CELL.LONG_IO_V[0] bit 0 INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E0[0] INT: !bipass CELL.DOUBLE_IO_E0[0] = CELL.DOUBLE_IO_E2[0] INT: mux CELL.LONG_IO_V[0] bit 1 INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E1[0] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E1[0] - INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E2[0] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E2[0] INT: !pass CELL.DOUBLE_IO_E2[0] ← CELL.DBUF_IO_V[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E2[2] INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_E2[2] INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[4] - - - INT: mux CELL.IMUX_IO_OK[0] bit 5 - IO[0]: DRIVE bit 0 IO[0]: ! IFF_CE_ENABLE_NO_IQ IO[1]: ! IFF_CE_ENABLE_NO_IQ IO[0]: IFF_D bit 1 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I2 bit 1
B4 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_WE_I2[1] INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_WE_I2[1] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_WE_I2[1] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_WE_I2[0] INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[3] INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[0] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_IO_V[2] INT: mux CELL.IMUX_IO_T[0] bit 6 INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_E0[2] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E0[2] INT: !bipass CELL.DOUBLE_IO_E0[2] = CELL.DOUBLE_IO_E2[2] INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_E1[2] INT: !pass CELL.DOUBLE_IO_E2[2] ← CELL.DBUF_IO_V[1] - - - - - - - - - IO[1]: IFF_D bit 1 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I1 bit 0
B3 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 1 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 1 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 3 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] - INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 6 TBUF[0]: ! DRIVE1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.DBUF_IO_V[0] bit 0 INT: mux CELL.DBUF_IO_V[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 7 INT: mux CELL.IMUX_IO_T[0] bit 3 IO[1]: MUX_T bit 0 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 7 INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E1[2] INT: mux CELL.IMUX_IO_T[1] bit 6 TBUF[1]: ! DRIVE1 INT: mux CELL.IMUX_CLB_G3 bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 0 - IO[1]: ! IFF_SRVAL bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 5 - IO[1]: DRIVE bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I2 bit 0 IO[1]: !invert IK IO[1]: IFF_D bit 0 IO[1]: MUX_I2 bit 0
B2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F1 bit 0 INT: mux CELL.IMUX_CLB_F1 bit 7 - - - - INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.DBUF_IO_V[0] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.DBUF_IO_V[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 5 IO[0]: MUX_T bit 0 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 7 IO[1]: SYNC_D bit 0 IO[1]: OFF_USED IO[1]: ! READBACK_OQ bit 0 IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0
B1 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 2 - - INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 3 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.LONG_H[0] bit 1 INT: mux CELL.LONG_H[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 4 - INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 3 - INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 5 - INT: mux CELL.LONG_H[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 7 IO[1]: MUX_O bit 3 IO[1]: MUX_O bit 2 IO[1]: PULL bit 0 IO[1]: ! OFF_SRVAL bit 0 IO[1]: PULL bit 1
B0 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 4 - - INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 1 INT: mux CELL.IMUX_CLB_G1 bit 7 - INT: mux CELL.LONG_H[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 - INT: mux CELL.IMUX_TBUF_T[0] bit 4 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: mux CELL.LONG_H[1] bit 1 INT: mux CELL.LONG_H[1] bit 0 - - INT: mux CELL.IMUX_IO_O1[1] bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 2 IO[1]: MUX_O bit 0 IO[1]: MUX_O bit 1 IO[1]: !invert OK IO[1]: !invert T IO[1]: SLEW bit 0
spartanxl IO_E1_S rect MAIN_S
BitFrame
F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B12 - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H_BUF[2] - - - - - - - PULLUP_TBUF[0]: ! ENABLE - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
spartanxl IO_E1_S rect MAIN_W
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_S0

Cells: 4

Switchbox INT

spartanxl IO_S0 switchbox INT permanent buffers
DestinationSource
CELL.IMUX_CINCELL.LONG_V[0]
spartanxl IO_S0 switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[3]CELL.SINGLE_V[4]!MAIN[24][5]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[20][9]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[35][9]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[19][9]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[33][11]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[29][9]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[19][12]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[26][9]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[30][11]
spartanxl IO_S0 switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[12][8]
CELL.SINGLE_H[0]CELL.OUT_IO_SN_I2[0]!MAIN[14][8]
CELL.SINGLE_H[1]CELL.OUT_IO_SN_I2[1]!MAIN[15][9]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[14][10]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[11][10]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[13][12]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[20][12]
CELL.SINGLE_H[4]CELL.OUT_IO_SN_I2[0]!MAIN[15][8]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[22][9]
CELL.SINGLE_H[5]CELL.OUT_IO_SN_I2[1]!MAIN[17][9]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[13][9]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[29][12]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[15][10]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[12][12]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[14][12]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[18][9]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[35][12]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[34][10]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[22][8]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I2_E1!MAIN[22][5]
CELL.SINGLE_V[1]CELL.LONG_IO_H[0]!MAIN[15][4]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I2[0]!MAIN[22][6]
CELL.SINGLE_V[2]CELL.LONG_IO_H[1]!MAIN[17][4]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I1[0]!MAIN[25][4]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I1_E1!MAIN[29][4]
CELL.SINGLE_V[4]CELL.LONG_H[3]!MAIN[21][10]
CELL.SINGLE_V[4]CELL.OUT_IO_SN_I2_E1!MAIN[35][6]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[21][9]
CELL.SINGLE_V[5]CELL.LONG_IO_H[2]!MAIN[33][4]
CELL.SINGLE_V[5]CELL.OUT_IO_SN_I2[0]!MAIN[32][6]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[35][10]
CELL.SINGLE_V[6]CELL.LONG_IO_H[3]!MAIN[34][4]
CELL.SINGLE_V[6]CELL.OUT_IO_SN_I1[0]!MAIN[25][5]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[21][12]
CELL.SINGLE_V[7]CELL.OUT_IO_SN_I1_E1!MAIN[32][4]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[13][10]
CELL.DOUBLE_H0[1]CELL.OUT_IO_SN_I2[0]!MAIN[13][8]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[15][12]
CELL.DOUBLE_H1[1]CELL.OUT_IO_SN_I2[1]!MAIN[16][9]
CELL.DOUBLE_V0[0]CELL.OUT_IO_SN_I1_E1!MAIN[21][3]
CELL.DOUBLE_V0[1]CELL.OUT_IO_SN_I2[0]!MAIN[31][6]
CELL.DOUBLE_V1[0]CELL.OUT_IO_SN_I1[0]!MAIN[20][3]
CELL.DOUBLE_V1[1]CELL.OUT_IO_SN_I2_E1!MAIN[30][6]
CELL.DOUBLE_IO_S0[0]CELL.DBUF_IO_H[1]!MAIN[10][2]
CELL.DOUBLE_IO_S0[1]CELL.DBUF_IO_H[1]!MAIN[9][2]
CELL.DOUBLE_IO_S0[2]CELL.DBUF_IO_H[1]!MAIN[9][1]
CELL.DOUBLE_IO_S0[3]CELL.DBUF_IO_H[1]!MAIN[10][1]
CELL.DOUBLE_IO_S2[0]CELL.DBUF_IO_H[0]!MAIN[35][2]
CELL.DOUBLE_IO_S2[1]CELL.DBUF_IO_H[0]!MAIN[34][2]
CELL.DOUBLE_IO_S2[2]CELL.DBUF_IO_H[0]!MAIN[34][1]
CELL.DOUBLE_IO_S2[3]CELL.DBUF_IO_H[0]!MAIN[35][1]
spartanxl IO_S0 switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[18][8]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[21][8]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[17][8]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[25][8]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[24][8]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[23][8]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[27][11]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[26][11]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[28][11]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[26][10]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[23][10]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[25][10]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[31][9]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[34][9]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[30][9]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[31][8]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[30][8]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[33][8]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[30][10]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[31][11]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[31][10]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[33][12]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[30][12]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[32][11]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[20][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[19][8]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[24][9]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[25][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[26][12]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[27][12]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[27][10]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[28][10]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[34][11]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[32][9]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[32][8]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[34][8]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[29][10]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[32][10]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[32][12]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[34][12]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[16][8]
CELL.SINGLE_V[0]CELL.DOUBLE_IO_S0[0]!MAIN[22][2]
CELL.SINGLE_V[0]CELL.DOUBLE_IO_S2[0]!MAIN[24][2]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[23][9]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_S1[0]!MAIN[18][1]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[25][12]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_S0[1]!MAIN[27][2]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_S2[1]!MAIN[26][1]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[22][10]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_S1[1]!MAIN[25][3]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[33][9]
CELL.SINGLE_V[4]CELL.DOUBLE_IO_S0[2]!MAIN[30][2]
CELL.SINGLE_V[4]CELL.DOUBLE_IO_S2[2]!MAIN[29][1]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[35][8]
CELL.SINGLE_V[5]CELL.DOUBLE_IO_S1[2]!MAIN[28][2]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[33][10]
CELL.SINGLE_V[6]CELL.DOUBLE_IO_S0[3]!MAIN[32][1]
CELL.SINGLE_V[6]CELL.DOUBLE_IO_S2[3]!MAIN[32][2]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[31][12]
CELL.SINGLE_V[7]CELL.DOUBLE_IO_S1[3]!MAIN[31][3]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[24][12]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[22][12]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[23][12]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[28][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[27][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[26][8]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[24][10]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[24][11]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[28][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[29][8]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][11]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S0[1]!MAIN[26][2]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S1[1]!MAIN[24][3]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S2[1]!MAIN[27][1]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[27][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S0[2]!MAIN[28][1]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S1[2]!MAIN[29][2]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S2[2]!MAIN[30][1]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S0[0]!MAIN[21][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S1[0]!MAIN[20][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S2[0]!MAIN[25][2]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S0[3]!MAIN[31][2]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S1[3]!MAIN[31][1]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S2[3]!MAIN[33][2]
CELL.DOUBLE_IO_S0[0]CELL.DOUBLE_IO_S2[0]!MAIN[23][2]
CELL.DOUBLE_IO_S0[1]CELL.DOUBLE_IO_S2[1]!MAIN[25][1]
CELL.DOUBLE_IO_S0[2]CELL.DOUBLE_IO_S2[2]!MAIN[30][3]
CELL.DOUBLE_IO_S0[3]CELL.DOUBLE_IO_S2[3]!MAIN[32][3]
spartanxl IO_S0 switchbox INT muxes DBUF_IO_H[0]
BitsDestination
MAIN[7][2]MAIN[8][2]MAIN[7][1]MAIN[8][1]CELL.DBUF_IO_H[0]
Source
0011CELL.DOUBLE_IO_S0[0]
0101CELL.DOUBLE_IO_S0[2]
0110CELL.DOUBLE_IO_S0[3]
1111CELL.DOUBLE_IO_S0[1]
spartanxl IO_S0 switchbox INT muxes DBUF_IO_H[1]
BitsDestination
MAIN[33][3]MAIN[34][3]MAIN[35][3]MAIN[33][1]CELL.DBUF_IO_H[1]
Source
0011CELL.DOUBLE_IO_S2[1]
0101CELL.DOUBLE_IO_S2[2]
0110CELL.DOUBLE_IO_S2[3]
1111CELL.DOUBLE_IO_S2[0]
spartanxl IO_S0 switchbox INT muxes LONG_V[0]
BitsDestination
MAIN[26][5]MAIN[29][5]MAIN[27][5]CELL.LONG_V[0]
Source
000CELL.LONG_IO_H[0]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_S0 switchbox INT muxes LONG_V[1]
BitsDestination
MAIN[35][5]MAIN[34][6]MAIN[33][5]CELL.LONG_V[1]
Source
000CELL.LONG_IO_H[1]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_S0 switchbox INT muxes LONG_V[2]
BitsDestination
MAIN[31][5]MAIN[32][5]MAIN[30][5]CELL.LONG_V[2]
Source
000CELL.LONG_IO_H[2]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_S0 switchbox INT muxes LONG_V[3]
BitsDestination
MAIN[6][5]MAIN[7][6]MAIN[6][6]CELL.LONG_V[3]
Source
000CELL.LONG_IO_H[1]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_S0 switchbox INT muxes LONG_V[4]
BitsDestination
MAIN[5][5]MAIN[2][6]MAIN[1][6]CELL.LONG_V[4]
Source
000CELL.LONG_IO_H[2]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_S0 switchbox INT muxes LONG_V[5]
BitsDestination
MAIN[8][5]MAIN[9][5]MAIN[8][6]CELL.LONG_V[5]
Source
000CELL.LONG_IO_H[3]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_S0 switchbox INT muxes LONG_IO_H[0]
BitsDestination
MAIN[4][6]MAIN[16][4]CELL.LONG_IO_H[0]
Source
00CELL.LONG_V[0]
01CELL.SINGLE_V[1]
11off
spartanxl IO_S0 switchbox INT muxes LONG_IO_H[1]
BitsDestination
MAIN[23][3]MAIN[14][2]MAIN[18][4]MAIN[17][1]CELL.LONG_IO_H[1]
Source
0001CELL.LONG_V[1]
0010CELL.LONG_V[3]
0111CELL.SINGLE_V[2]
1111off
spartanxl IO_S0 switchbox INT muxes LONG_IO_H[2]
BitsDestination
MAIN[22][3]MAIN[20][4]MAIN[21][4]MAIN[22][4]CELL.LONG_IO_H[2]
Source
0001CELL.LONG_V[2]
0010CELL.LONG_V[4]
0111CELL.SINGLE_V[5]
1111off
spartanxl IO_S0 switchbox INT muxes LONG_IO_H[3]
BitsDestination
MAIN[4][5]MAIN[23][4]CELL.LONG_IO_H[3]
Source
00CELL.LONG_V[5]
01CELL.SINGLE_V[6]
11off
spartanxl IO_S0 switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[10][12]MAIN[10][10]MAIN[11][9]MAIN[11][11]MAIN[11][12]MAIN[12][11]MAIN[12][10]MAIN[12][9]CELL.IMUX_CLB_F2
Source
00110011CELL.SINGLE_H[5]
00110101CELL.LONG_H[5]
00110110CELL.DOUBLE_H1[1]
00111111CELL.SINGLE_H[0]
01010011CELL.SINGLE_H[4]
01010101CELL.DOUBLE_H0[1]
01010110CELL.LONG_H[4]
01011111CELL.SINGLE_H[1]
01100011CELL.SINGLE_H[6]
01100101CELL_N.LONG_H_BUF[2]
01100110CELL_N.LONG_H[0]
01101111CELL.SINGLE_H[3]
11110011CELL.DOUBLE_H0[0]
11110101CELL.SINGLE_H[7]
11110110CELL.DOUBLE_H1[0]
11111111CELL.SINGLE_H[2]
spartanxl IO_S0 switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[9][10]MAIN[9][11]MAIN[8][9]MAIN[8][10]MAIN[10][9]MAIN[8][12]MAIN[9][12]MAIN[10][11]CELL.IMUX_CLB_F4
Source
00001111CELL.SINGLE_H[0]
00011011CELL.DOUBLE_H1[0]
00011101CELL_N.LONG_H[0]
00111111CELL.SINGLE_H[1]
01000111CELL.LONG_H[5]
01001110CELL.LONG_H[3]
01010011CELL.SINGLE_H[2]
01010101CELL.SINGLE_H[3]
01011010CELL.SINGLE_H[7]
01011100CELL_N.LONG_H[1]
01110111CELL.DOUBLE_H1[1]
01111110CELL.DOUBLE_H0[1]
11001111CELL.SINGLE_H[5]
11011011CELL.DOUBLE_H0[0]
11011101CELL.SINGLE_H[6]
11111111CELL.SINGLE_H[4]
spartanxl IO_S0 switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[2][10]MAIN[3][10]MAIN[3][12]MAIN[2][9]MAIN[3][11]MAIN[2][11]MAIN[2][12]MAIN[3][9]MAIN[4][11]CELL.IMUX_CLB_G2
Source
000111111CELL.SPECIAL_CLB_COUT0
001001111CELL.LONG_H[4]
001011101CELL.SINGLE_H[4]
001011110CELL.LONG_H[5]
001100111CELL.SINGLE_H[2]
001101011CELL.SINGLE_H[3]
001110101CELL.SINGLE_H[7]
001110110CELL.DOUBLE_H0[0]
001111001CELL_N.LONG_H_BUF[2]
001111010CELL.SINGLE_H[6]
011011111CELL.SINGLE_H[1]
011110111CELL_N.LONG_H[0]
011111011CELL.DOUBLE_H1[0]
101101111CELL.DOUBLE_H1[1]
101111101CELL.SINGLE_H[5]
101111110CELL.DOUBLE_H0[1]
111111111CELL.SINGLE_H[0]
spartanxl IO_S0 switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[5][12]MAIN[4][12]MAIN[6][11]MAIN[4][9]MAIN[4][10]MAIN[5][10]MAIN[5][11]MAIN[5][9]CELL.IMUX_CLB_G4
Source
00001111CELL.SINGLE_H[0]
00010111CELL.SINGLE_H[1]
00011101CELL_N.LONG_H[0]
00101011CELL.DOUBLE_H1[1]
00101110CELL.LONG_H[3]
00110011CELL.LONG_H[5]
00110110CELL.DOUBLE_H0[1]
00111001CELL.SINGLE_H[3]
00111100CELL.SINGLE_H[6]
01011111CELL.DOUBLE_H1[0]
01111011CELL.SINGLE_H[2]
01111110CELL.DOUBLE_H0[0]
10101111CELL.SINGLE_H[5]
10110111CELL.SINGLE_H[4]
10111101CELL_N.LONG_H[1]
11111111CELL.SINGLE_H[7]
spartanxl IO_S0 switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[0][10]MAIN[0][9]MAIN[1][10]MAIN[1][12]MAIN[0][11]MAIN[0][12]MAIN[1][9]MAIN[1][11]CELL.IMUX_CLB_C2
Source
00001111CELL.LONG_H[4]
00011101CELL.SINGLE_H[5]
00011110CELL.LONG_H[3]
00111111CELL.SINGLE_H[0]
01000111CELL.SINGLE_H[2]
01001011CELL.SINGLE_H[3]
01010101CELL.SINGLE_H[7]
01010110CELL.DOUBLE_H0[0]
01011001CELL_N.LONG_H[1]
01011010CELL.SINGLE_H[6]
01110111CELL.DOUBLE_H1[0]
01111011CELL_N.LONG_H_BUF[2]
11001111CELL.DOUBLE_H1[1]
11011101CELL.SINGLE_H[4]
11011110CELL.DOUBLE_H0[1]
11111111CELL.SINGLE_H[1]
spartanxl IO_S0 switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[26][4]MAIN[26][3]MAIN[29][3]MAIN[28][4]MAIN[27][3]MAIN[28][3]MAIN[27][4]CELL.IMUX_IO_O1[0]
Source
0011111CELL.DOUBLE_V0[0]
0100110CELL.LONG_V[5]
0111011CELL.LONG_V[3]
0111101CELL.LONG_V[4]
1100111CELL.DOUBLE_V1[1]
1111111CELL.TIE_0
spartanxl IO_S0 switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[1][4]MAIN[0][4]MAIN[0][3]MAIN[1][3]MAIN[2][3]MAIN[2][4]MAIN[3][5]CELL.IMUX_IO_O1[1]
Source
0111101CELL.TIE_0
1011101CELL.LONG_IO_H[2]
1011110CELL_E.DOUBLE_V0[1]
1101101CELL_E.DOUBLE_V1[0]
1101110CELL_E.LONG_V[2]
1110101CELL_E.LONG_V[0]
1111001CELL_E.LONG_V[1]
spartanxl IO_S0 switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[23][5]MAIN[23][6]MAIN[24][6]MAIN[25][6]MAIN[28][6]MAIN[26][6]CELL.IMUX_IO_OK[0]
Source
001100CELL.GCLK[1]
001111CELL.SINGLE_V[3]
010100CELL.GCLK[2]
010111CELL.SINGLE_V[4]
011000CELL.GCLK[3]
011011CELL.SINGLE_V[5]
111100CELL.GCLK[0]
111111CELL.SINGLE_V[2]
spartanxl IO_S0 switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[11][6]MAIN[10][6]MAIN[10][5]MAIN[12][5]MAIN[11][5]MAIN[13][5]CELL.IMUX_IO_OK[1]
Source
000011CELL.GCLK[1]
000101CELL.GCLK[2]
000110CELL.GCLK[3]
001111CELL.GCLK[0]
110011CELL_E.SINGLE_V[2]
110101CELL_E.SINGLE_V[3]
110110CELL_E.SINGLE_V[5]
111111CELL_E.SINGLE_V[4]
spartanxl IO_S0 switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[18][5]MAIN[19][5]MAIN[20][5]MAIN[21][5]MAIN[19][6]MAIN[18][6]CELL.IMUX_IO_IK[0]
Source
001100CELL.GCLK[1]
001111CELL.SINGLE_V[2]
010100CELL.GCLK[2]
010111CELL.SINGLE_V[4]
011000CELL.GCLK[3]
011011CELL.SINGLE_V[5]
111100CELL.GCLK[0]
111111CELL.SINGLE_V[3]
spartanxl IO_S0 switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[16][6]MAIN[14][6]MAIN[14][5]MAIN[15][5]MAIN[16][5]MAIN[17][5]CELL.IMUX_IO_IK[1]
Source
000011CELL.GCLK[1]
000101CELL.GCLK[2]
000110CELL.GCLK[3]
001111CELL.GCLK[0]
110011CELL_E.SINGLE_V[2]
110101CELL_E.SINGLE_V[3]
110110CELL_E.SINGLE_V[4]
111111CELL_E.SINGLE_V[5]
spartanxl IO_S0 switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[5][2]MAIN[3][2]MAIN[6][0]MAIN[6][1]MAIN[6][2]MAIN[4][2]MAIN[5][1]MAIN[4][1]CELL.IMUX_IO_T[0]
Source
00011111CELL.TIE_0
00101110CELL.GCLK[0]
00110011CELL.LONG_IO_H[3]
00110101CELL.LONG_IO_H[0]
00110110CELL.LONG_IO_H[2]
01101111CELL.DOUBLE_IO_S0[1]
01110111CELL.DOUBLE_IO_S1[0]
10111011CELL.DOUBLE_IO_S1[1]
10111101CELL.LONG_IO_H[1]
11111111CELL.DOUBLE_IO_S0[0]
spartanxl IO_S0 switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[0][1]MAIN[1][2]MAIN[11][2]MAIN[2][1]MAIN[2][2]MAIN[3][1]MAIN[1][1]MAIN[0][2]CELL.IMUX_IO_T[1]
Source
00011111CELL.TIE_0
00100111CELL.LONG_IO_H[0]
00101011CELL.GCLK[0]
00110101CELL.LONG_IO_H[3]
00110110CELL.LONG_IO_H[2]
01101111CELL.DOUBLE_IO_S0[0]
01111101CELL.LONG_IO_H[1]
10110111CELL.DOUBLE_IO_S0[1]
10111011CELL.DOUBLE_IO_S1[1]
11111111CELL.DOUBLE_IO_S1[0]

Bels IO

spartanxl IO_S0 bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[22][0]CELL.IMUX_IO_IK[1] invert by !MAIN[13][0]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[32][0]CELL.IMUX_IO_OK[1] invert by !MAIN[2][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_F4CELL.IMUX_CLB_G4
TinCELL.IMUX_IO_T[0] invert by !MAIN[34][0]CELL.IMUX_IO_T[1] invert by !MAIN[0][0]
I1outCELL.OUT_IO_SN_I1[0]CELL.OUT_IO_SN_I1[1]
I2outCELL.OUT_IO_SN_I2[0]CELL.OUT_IO_SN_I2[1]
spartanxl IO_S0 bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[23][0]!MAIN[12][0]
OFF_SRVAL bit 0!MAIN[24][1]!MAIN[11][1]
READBACK_I1 bit 0!MAIN[18][3]!MAIN[17][2]
READBACK_I2 bit 0!MAIN[18][2]!MAIN[17][3]
READBACK_OQ bit 0!MAIN[16][3]!MAIN[16][2]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[25][0]!MAIN[9][0]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[24][0]MAIN[10][0]
IFF_CE_ENABLE!MAIN[19][1]!MAIN[13][2]
OFF_CE_ENABLE!MAIN[30][0]!MAIN[12][2]
SYNC_D[enum: IO_SYNC_D][enum: IO_SYNC_D]
IFF_CE_ENABLE_NO_IQ!MAIN[8][4]!MAIN[8][3]
MUX_T[enum: IO_MUX_T][enum: IO_MUX_T]
DRIVE[enum: IO_DRIVE][enum: IO_DRIVE]
_5V_TOLERANTMAIN[13][4]MAIN[12][4]
spartanxl IO_S0 enum IO_SLEW
IO[0].SLEWMAIN[33][0]
IO[1].SLEWMAIN[1][0]
FAST0
SLOW1
spartanxl IO_S0 enum IO_PULL
IO[0].PULLMAIN[22][1]MAIN[23][1]
IO[1].PULLMAIN[13][1]MAIN[12][1]
NONE11
PULLUP01
PULLDOWN10
spartanxl IO_S0 enum IO_MUX_I
IO[0].MUX_I1MAIN[19][0]MAIN[17][0]
IO[1].MUX_I1MAIN[16][0]MAIN[15][1]
IO[0].MUX_I2MAIN[21][0]MAIN[20][0]
IO[1].MUX_I2MAIN[15][0]MAIN[14][0]
I01
IQ11
IQL10
spartanxl IO_S0 enum IO_IFF_D
IO[0].IFF_DMAIN[18][0]MAIN[20][1]
IO[1].IFF_DMAIN[16][1]MAIN[14][1]
I11
DELAY00
MEDDELAY01
SYNC10
spartanxl IO_S0 enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[26][0]
IO[1].MUX_OFF_DMAIN[8][0]
O11
O20
spartanxl IO_S0 enum IO_MUX_O
IO[0].MUX_OMAIN[28][0]MAIN[27][0]MAIN[29][0]MAIN[31][0]
IO[1].MUX_OMAIN[4][0]MAIN[3][0]MAIN[7][0]MAIN[5][0]
O10000
O1_INV0001
O20111
O2_INV1111
OQ0010
MUX1011
spartanxl IO_S0 enum IO_SYNC_D
IO[0].SYNC_DMAIN[21][1]
IO[1].SYNC_DMAIN[11][0]
I1
DELAY0
spartanxl IO_S0 enum IO_MUX_T
IO[0].MUX_TMAIN[13][3]
IO[1].MUX_TMAIN[10][3]
T1
TQ0
spartanxl IO_S0 enum IO_DRIVE
IO[0].DRIVEMAIN[14][4]
IO[1].DRIVEMAIN[12][3]
_121
_240

Bels CIN

spartanxl IO_S0 bel CIN pins
PinDirectionCIN
IinCELL.IMUX_CIN

Bel wires

spartanxl IO_S0 bel wires
WirePins
CELL.IMUX_CLB_F4IO[0].O2
CELL.IMUX_CLB_G4IO[1].O2
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.IMUX_CINCIN.I
CELL.OUT_IO_SN_I1[0]IO[0].I1
CELL.OUT_IO_SN_I1[1]IO[1].I1
CELL.OUT_IO_SN_I2[0]IO[0].I2
CELL.OUT_IO_SN_I2[1]IO[1].I2

Bitstream

spartanxl IO_S0 rect MAIN
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B12 INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] - - - INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 2 - - INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 2
B11 - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - - - - - - - - - INT: mux CELL.IMUX_CLB_F2 bit 2 INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_F4 bit 6 - - INT: mux CELL.IMUX_CLB_G4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 3
B10 INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3] - - - - - INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 4 - - INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7
B9 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_SN_I2[1] - INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_F4 bit 3 - INT: mux CELL.IMUX_CLB_F4 bit 5 - - INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 6
B8 INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.LONG_V[1] bit 1 - INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1 - INT: mux CELL.IMUX_IO_OK[0] bit 1 - INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0] - - INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 5 - INT: mux CELL.IMUX_IO_IK[1] bit 4 - - INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 4 - INT: mux CELL.LONG_V[5] bit 0 INT: mux CELL.LONG_V[3] bit 1 INT: mux CELL.LONG_V[3] bit 0 - INT: mux CELL.LONG_IO_H[0] bit 1 - INT: mux CELL.LONG_V[4] bit 1 INT: mux CELL.LONG_V[4] bit 0 -
B5 INT: mux CELL.LONG_V[1] bit 2 - INT: mux CELL.LONG_V[1] bit 0 INT: mux CELL.LONG_V[2] bit 1 INT: mux CELL.LONG_V[2] bit 2 INT: mux CELL.LONG_V[2] bit 0 INT: mux CELL.LONG_V[0] bit 1 - INT: mux CELL.LONG_V[0] bit 0 INT: mux CELL.LONG_V[0] bit 2 INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_IO_SN_I1[0] INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[4] INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 5 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.LONG_V[5] bit 1 INT: mux CELL.LONG_V[5] bit 2 - INT: mux CELL.LONG_V[3] bit 2 INT: mux CELL.LONG_V[4] bit 2 INT: mux CELL.LONG_IO_H[3] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 0 - - -
B4 - INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_IO_H[3] INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_IO_H[2] INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_IO_SN_I1_E1 - - INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 6 INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0] - INT: mux CELL.LONG_IO_H[3] bit 0 INT: mux CELL.LONG_IO_H[2] bit 0 INT: mux CELL.LONG_IO_H[2] bit 1 INT: mux CELL.LONG_IO_H[2] bit 2 - INT: mux CELL.LONG_IO_H[1] bit 1 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[1] INT: mux CELL.LONG_IO_H[0] bit 0 INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[0] IO[0]: DRIVE bit 0 IO[0]: _5V_TOLERANT IO[1]: _5V_TOLERANT - - - IO[0]: ! IFF_CE_ENABLE_NO_IQ - - - - - INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 6 INT: mux CELL.IMUX_IO_O1[1] bit 5
B3 INT: mux CELL.DBUF_IO_H[1] bit 1 INT: mux CELL.DBUF_IO_H[1] bit 2 INT: mux CELL.DBUF_IO_H[1] bit 3 INT: !bipass CELL.DOUBLE_IO_S0[3] = CELL.DOUBLE_IO_S2[3] INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_S1[3] INT: !bipass CELL.DOUBLE_IO_S0[2] = CELL.DOUBLE_IO_S2[2] INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 5 INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S1[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S1[1] INT: mux CELL.LONG_IO_H[1] bit 3 INT: mux CELL.LONG_IO_H[2] bit 3 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0] - IO[0]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I2 bit 0 IO[0]: ! READBACK_OQ bit 0 - - IO[0]: MUX_T bit 0 IO[1]: DRIVE bit 0 - IO[1]: MUX_T bit 0 - IO[1]: ! IFF_CE_ENABLE_NO_IQ - - - - - INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 4
B2 INT: !pass CELL.DOUBLE_IO_S2[0] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_S2[1] ← CELL.DBUF_IO_H[0] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S2[3] INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_S2[3] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S0[3] INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_S0[2] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S1[2] INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_S1[2] INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S0[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S0[1] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.DOUBLE_IO_S0[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S1[0] - IO[0]: ! READBACK_I2 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_OQ bit 0 - INT: mux CELL.LONG_IO_H[1] bit 2 IO[1]: ! IFF_CE_ENABLE IO[1]: ! OFF_CE_ENABLE INT: mux CELL.IMUX_IO_T[1] bit 5 INT: !pass CELL.DOUBLE_IO_S0[0] ← CELL.DBUF_IO_H[1] INT: !pass CELL.DOUBLE_IO_S0[1] ← CELL.DBUF_IO_H[1] INT: mux CELL.DBUF_IO_H[0] bit 2 INT: mux CELL.DBUF_IO_H[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 7 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 6 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 6 INT: mux CELL.IMUX_IO_T[1] bit 0
B1 INT: !pass CELL.DOUBLE_IO_S2[3] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_S2[2] ← CELL.DBUF_IO_H[0] INT: mux CELL.DBUF_IO_H[1] bit 0 INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_S0[3] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S1[3] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S2[2] INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_S2[2] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S0[2] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S2[1] INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S2[1] INT: !bipass CELL.DOUBLE_IO_S0[1] = CELL.DOUBLE_IO_S2[1] IO[0]: ! OFF_SRVAL bit 0 IO[0]: PULL bit 0 IO[0]: PULL bit 1 IO[0]: SYNC_D bit 0 IO[0]: IFF_D bit 0 IO[0]: ! IFF_CE_ENABLE INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S1[0] INT: mux CELL.LONG_IO_H[1] bit 0 IO[1]: IFF_D bit 1 IO[1]: MUX_I1 bit 0 IO[1]: IFF_D bit 0 IO[1]: PULL bit 1 IO[1]: PULL bit 0 IO[1]: ! OFF_SRVAL bit 0 INT: !pass CELL.DOUBLE_IO_S0[3] ← CELL.DBUF_IO_H[1] INT: !pass CELL.DOUBLE_IO_S0[2] ← CELL.DBUF_IO_H[1] INT: mux CELL.DBUF_IO_H[0] bit 0 INT: mux CELL.DBUF_IO_H[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 7
B0 - IO[0]: !invert T IO[0]: SLEW bit 0 IO[0]: !invert OK IO[0]: MUX_O bit 0 IO[0]: ! OFF_CE_ENABLE IO[0]: MUX_O bit 1 IO[0]: MUX_O bit 3 IO[0]: MUX_O bit 2 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_D_INV IO[0]: OFF_USED IO[0]: ! IFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 1 IO[0]: MUX_I2 bit 0 IO[0]: MUX_I1 bit 1 IO[0]: IFF_D bit 1 IO[0]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I2 bit 0 IO[1]: !invert IK IO[1]: ! IFF_SRVAL bit 0 IO[1]: SYNC_D bit 0 IO[1]: OFF_USED IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0 IO[1]: MUX_O bit 1 INT: mux CELL.IMUX_IO_T[0] bit 5 IO[1]: MUX_O bit 0 IO[1]: MUX_O bit 3 IO[1]: MUX_O bit 2 IO[1]: !invert OK IO[1]: SLEW bit 0 IO[1]: !invert T
spartanxl IO_S0 rect MAIN_E
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_S0_E

Cells: 4

Switchbox INT

spartanxl IO_S0_E switchbox INT permanent buffers
DestinationSource
CELL.IMUX_CINCELL.LONG_V[0]
spartanxl IO_S0_E switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[3]CELL.SINGLE_V[4]!MAIN[24][5]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[20][9]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[35][9]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[19][9]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[33][11]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[29][9]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[19][12]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[26][9]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[30][11]
spartanxl IO_S0_E switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[12][8]
CELL.SINGLE_H[0]CELL.OUT_IO_SN_I2[0]!MAIN[14][8]
CELL.SINGLE_H[1]CELL.OUT_IO_SN_I2[1]!MAIN[15][9]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[14][10]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[11][10]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[13][12]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[20][12]
CELL.SINGLE_H[4]CELL.OUT_IO_SN_I2[0]!MAIN[15][8]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[22][9]
CELL.SINGLE_H[5]CELL.OUT_IO_SN_I2[1]!MAIN[17][9]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[13][9]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[29][12]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[15][10]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[12][12]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[14][12]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[18][9]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[35][12]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[34][10]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[22][8]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I2_E1!MAIN[22][5]
CELL.SINGLE_V[1]CELL.LONG_IO_H[0]!MAIN[15][4]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I2[0]!MAIN[22][6]
CELL.SINGLE_V[2]CELL.LONG_IO_H[1]!MAIN[17][4]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I1[0]!MAIN[25][4]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I1_E1!MAIN[29][4]
CELL.SINGLE_V[4]CELL.LONG_H[3]!MAIN[21][10]
CELL.SINGLE_V[4]CELL.OUT_IO_SN_I2_E1!MAIN[35][6]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[21][9]
CELL.SINGLE_V[5]CELL.LONG_IO_H[2]!MAIN[33][4]
CELL.SINGLE_V[5]CELL.OUT_IO_SN_I2[0]!MAIN[32][6]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[35][10]
CELL.SINGLE_V[6]CELL.LONG_IO_H[3]!MAIN[34][4]
CELL.SINGLE_V[6]CELL.OUT_IO_SN_I1[0]!MAIN[25][5]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[21][12]
CELL.SINGLE_V[7]CELL.OUT_IO_SN_I1_E1!MAIN[32][4]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[13][10]
CELL.DOUBLE_H0[1]CELL.OUT_IO_SN_I2[0]!MAIN[13][8]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[15][12]
CELL.DOUBLE_H1[1]CELL.OUT_IO_SN_I2[1]!MAIN[16][9]
CELL.DOUBLE_V0[0]CELL.OUT_IO_SN_I1_E1!MAIN[21][3]
CELL.DOUBLE_V0[1]CELL.OUT_IO_SN_I2[0]!MAIN[31][6]
CELL.DOUBLE_V1[0]CELL.OUT_IO_SN_I1[0]!MAIN[20][3]
CELL.DOUBLE_V1[1]CELL.OUT_IO_SN_I2_E1!MAIN[30][6]
CELL.DOUBLE_IO_S0[0]CELL.DBUF_IO_H[1]!MAIN[10][2]
CELL.DOUBLE_IO_S0[1]CELL.DBUF_IO_H[1]!MAIN[9][2]
CELL.DOUBLE_IO_S0[2]CELL.DBUF_IO_H[1]!MAIN[9][1]
CELL.DOUBLE_IO_S0[3]CELL.DBUF_IO_H[1]!MAIN[10][1]
CELL.DOUBLE_IO_S2[0]CELL.DBUF_IO_H[0]!MAIN[35][2]
CELL.DOUBLE_IO_S2[1]CELL.DBUF_IO_H[0]!MAIN[34][2]
CELL.DOUBLE_IO_S2[2]CELL.DBUF_IO_H[0]!MAIN[34][1]
CELL.DOUBLE_IO_S2[3]CELL.DBUF_IO_H[0]!MAIN[35][1]
spartanxl IO_S0_E switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[18][8]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[21][8]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[17][8]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[25][8]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[24][8]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[23][8]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[27][11]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[26][11]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[28][11]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[26][10]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[23][10]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[25][10]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[31][9]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[34][9]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[30][9]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[31][8]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[30][8]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[33][8]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[30][10]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[31][11]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[31][10]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[33][12]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[30][12]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[32][11]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[20][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[19][8]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[24][9]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[25][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[26][12]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[27][12]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[27][10]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[28][10]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[34][11]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[32][9]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[32][8]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[34][8]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[29][10]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[32][10]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[32][12]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[34][12]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[16][8]
CELL.SINGLE_V[0]CELL.DOUBLE_IO_S0[0]!MAIN[22][2]
CELL.SINGLE_V[0]CELL.DOUBLE_IO_S2[0]!MAIN[24][2]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[23][9]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_S1[0]!MAIN[18][1]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[25][12]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_S0[1]!MAIN[27][2]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_S2[1]!MAIN[26][1]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[22][10]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_S1[1]!MAIN[25][3]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[33][9]
CELL.SINGLE_V[4]CELL.DOUBLE_IO_S0[2]!MAIN[30][2]
CELL.SINGLE_V[4]CELL.DOUBLE_IO_S2[2]!MAIN[29][1]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[35][8]
CELL.SINGLE_V[5]CELL.DOUBLE_IO_S1[2]!MAIN[28][2]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[33][10]
CELL.SINGLE_V[6]CELL.DOUBLE_IO_S0[3]!MAIN[32][1]
CELL.SINGLE_V[6]CELL.DOUBLE_IO_S2[3]!MAIN[32][2]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[31][12]
CELL.SINGLE_V[7]CELL.DOUBLE_IO_S1[3]!MAIN[31][3]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[24][12]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[22][12]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[23][12]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[28][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[27][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[26][8]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[24][10]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[24][11]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[28][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[29][8]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][11]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S0[1]!MAIN[26][2]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S1[1]!MAIN[24][3]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S2[1]!MAIN[27][1]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[27][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S0[2]!MAIN[28][1]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S1[2]!MAIN[29][2]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S2[2]!MAIN[30][1]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S0[0]!MAIN[21][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S1[0]!MAIN[20][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S2[0]!MAIN[25][2]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S0[3]!MAIN[31][2]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S1[3]!MAIN[31][1]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S2[3]!MAIN[33][2]
CELL.DOUBLE_IO_S0[0]CELL.DOUBLE_IO_S2[0]!MAIN[23][2]
CELL.DOUBLE_IO_S0[1]CELL.DOUBLE_IO_S2[1]!MAIN[25][1]
CELL.DOUBLE_IO_S0[2]CELL.DOUBLE_IO_S2[2]!MAIN[30][3]
CELL.DOUBLE_IO_S0[3]CELL.DOUBLE_IO_S2[3]!MAIN[32][3]
spartanxl IO_S0_E switchbox INT muxes DBUF_IO_H[0]
BitsDestination
MAIN[7][2]MAIN[8][2]MAIN[7][1]MAIN[8][1]CELL.DBUF_IO_H[0]
Source
0011CELL.DOUBLE_IO_S0[0]
0101CELL.DOUBLE_IO_S0[2]
0110CELL.DOUBLE_IO_S0[3]
1111CELL.DOUBLE_IO_S0[1]
spartanxl IO_S0_E switchbox INT muxes DBUF_IO_H[1]
BitsDestination
MAIN[33][3]MAIN[34][3]MAIN[35][3]MAIN[33][1]CELL.DBUF_IO_H[1]
Source
0011CELL.DOUBLE_IO_S2[1]
0101CELL.DOUBLE_IO_S2[2]
0110CELL.DOUBLE_IO_S2[3]
1111CELL.DOUBLE_IO_S2[0]
spartanxl IO_S0_E switchbox INT muxes LONG_V[0]
BitsDestination
MAIN[26][5]MAIN[29][5]MAIN[27][5]CELL.LONG_V[0]
Source
000CELL.LONG_IO_H[0]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_S0_E switchbox INT muxes LONG_V[1]
BitsDestination
MAIN[35][5]MAIN[34][6]MAIN[33][5]CELL.LONG_V[1]
Source
000CELL.LONG_IO_H[1]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_S0_E switchbox INT muxes LONG_V[2]
BitsDestination
MAIN[31][5]MAIN[32][5]MAIN[30][5]CELL.LONG_V[2]
Source
000CELL.LONG_IO_H[2]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_S0_E switchbox INT muxes LONG_V[3]
BitsDestination
MAIN[6][5]MAIN[7][6]MAIN[6][6]CELL.LONG_V[3]
Source
000CELL.LONG_IO_H[1]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_S0_E switchbox INT muxes LONG_V[4]
BitsDestination
MAIN[5][5]MAIN[2][6]MAIN[1][6]CELL.LONG_V[4]
Source
000CELL.LONG_IO_H[2]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_S0_E switchbox INT muxes LONG_V[5]
BitsDestination
MAIN[8][5]MAIN[9][5]MAIN[8][6]CELL.LONG_V[5]
Source
000CELL.LONG_IO_H[3]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_S0_E switchbox INT muxes LONG_IO_H[0]
BitsDestination
MAIN[4][6]MAIN[16][4]CELL.LONG_IO_H[0]
Source
00CELL.LONG_V[0]
01CELL.SINGLE_V[1]
11off
spartanxl IO_S0_E switchbox INT muxes LONG_IO_H[1]
BitsDestination
MAIN[23][3]MAIN[14][2]MAIN[18][4]MAIN[17][1]CELL.LONG_IO_H[1]
Source
0001CELL.LONG_V[1]
0010CELL.LONG_V[3]
0111CELL.SINGLE_V[2]
1111off
spartanxl IO_S0_E switchbox INT muxes LONG_IO_H[2]
BitsDestination
MAIN[22][3]MAIN[20][4]MAIN[21][4]MAIN[22][4]CELL.LONG_IO_H[2]
Source
0001CELL.LONG_V[2]
0010CELL.LONG_V[4]
0111CELL.SINGLE_V[5]
1111off
spartanxl IO_S0_E switchbox INT muxes LONG_IO_H[3]
BitsDestination
MAIN[4][5]MAIN[23][4]CELL.LONG_IO_H[3]
Source
00CELL.LONG_V[5]
01CELL.SINGLE_V[6]
11off
spartanxl IO_S0_E switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[10][12]MAIN[10][10]MAIN[11][9]MAIN[11][11]MAIN[11][12]MAIN[12][11]MAIN[12][10]MAIN[12][9]CELL.IMUX_CLB_F2
Source
00110011CELL.SINGLE_H[5]
00110101CELL.LONG_H[5]
00110110CELL.DOUBLE_H1[1]
00111111CELL.SINGLE_H[0]
01010011CELL.SINGLE_H[4]
01010101CELL.DOUBLE_H0[1]
01010110CELL.LONG_H[4]
01011111CELL.SINGLE_H[1]
01100011CELL.SINGLE_H[6]
01100101CELL_N.LONG_H_BUF[2]
01100110CELL_N.LONG_H[0]
01101111CELL.SINGLE_H[3]
11110011CELL.DOUBLE_H0[0]
11110101CELL.SINGLE_H[7]
11110110CELL.DOUBLE_H1[0]
11111111CELL.SINGLE_H[2]
spartanxl IO_S0_E switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[9][10]MAIN[9][11]MAIN[8][9]MAIN[8][10]MAIN[10][9]MAIN[8][12]MAIN[9][12]MAIN[10][11]CELL.IMUX_CLB_F4
Source
00001111CELL.SINGLE_H[0]
00011011CELL.DOUBLE_H1[0]
00011101CELL_N.LONG_H[0]
00111111CELL.SINGLE_H[1]
01000111CELL.LONG_H[5]
01001110CELL.LONG_H[3]
01010011CELL.SINGLE_H[2]
01010101CELL.SINGLE_H[3]
01011010CELL.SINGLE_H[7]
01011100CELL_N.LONG_H[1]
01110111CELL.DOUBLE_H1[1]
01111110CELL.DOUBLE_H0[1]
11001111CELL.SINGLE_H[5]
11011011CELL.DOUBLE_H0[0]
11011101CELL.SINGLE_H[6]
11111111CELL.SINGLE_H[4]
spartanxl IO_S0_E switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[2][10]MAIN[3][10]MAIN[3][12]MAIN[2][9]MAIN[3][11]MAIN[2][11]MAIN[2][12]MAIN[3][9]MAIN[4][11]CELL.IMUX_CLB_G2
Source
000111111CELL.SPECIAL_CLB_COUT0
001001111CELL.LONG_H[4]
001011101CELL.SINGLE_H[4]
001011110CELL.LONG_H[5]
001100111CELL.SINGLE_H[2]
001101011CELL.SINGLE_H[3]
001110101CELL.SINGLE_H[7]
001110110CELL.DOUBLE_H0[0]
001111001CELL_N.LONG_H_BUF[2]
001111010CELL.SINGLE_H[6]
011011111CELL.SINGLE_H[1]
011110111CELL_N.LONG_H[0]
011111011CELL.DOUBLE_H1[0]
101101111CELL.DOUBLE_H1[1]
101111101CELL.SINGLE_H[5]
101111110CELL.DOUBLE_H0[1]
111111111CELL.SINGLE_H[0]
spartanxl IO_S0_E switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[5][12]MAIN[4][12]MAIN[6][11]MAIN[4][9]MAIN[4][10]MAIN[5][10]MAIN[5][11]MAIN[5][9]CELL.IMUX_CLB_G4
Source
00001111CELL.SINGLE_H[0]
00010111CELL.SINGLE_H[1]
00011101CELL_N.LONG_H[0]
00101011CELL.DOUBLE_H1[1]
00101110CELL.LONG_H[3]
00110011CELL.LONG_H[5]
00110110CELL.DOUBLE_H0[1]
00111001CELL.SINGLE_H[3]
00111100CELL.SINGLE_H[6]
01011111CELL.DOUBLE_H1[0]
01111011CELL.SINGLE_H[2]
01111110CELL.DOUBLE_H0[0]
10101111CELL.SINGLE_H[5]
10110111CELL.SINGLE_H[4]
10111101CELL_N.LONG_H[1]
11111111CELL.SINGLE_H[7]
spartanxl IO_S0_E switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[0][10]MAIN[0][9]MAIN[1][10]MAIN[1][12]MAIN[0][11]MAIN[0][12]MAIN[1][9]MAIN[1][11]CELL.IMUX_CLB_C2
Source
00001111CELL.LONG_H[4]
00011101CELL.SINGLE_H[5]
00011110CELL.LONG_H[3]
00111111CELL.SINGLE_H[0]
01000111CELL.SINGLE_H[2]
01001011CELL.SINGLE_H[3]
01010101CELL.SINGLE_H[7]
01010110CELL.DOUBLE_H0[0]
01011001CELL_N.LONG_H[1]
01011010CELL.SINGLE_H[6]
01110111CELL.DOUBLE_H1[0]
01111011CELL_N.LONG_H_BUF[2]
11001111CELL.DOUBLE_H1[1]
11011101CELL.SINGLE_H[4]
11011110CELL.DOUBLE_H0[1]
11111111CELL.SINGLE_H[1]
spartanxl IO_S0_E switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[26][4]MAIN[26][3]MAIN[29][3]MAIN[28][4]MAIN[27][3]MAIN[28][3]MAIN[27][4]CELL.IMUX_IO_O1[0]
Source
0011111CELL.DOUBLE_V0[0]
0100110CELL.LONG_V[5]
0111011CELL.LONG_V[3]
0111101CELL.LONG_V[4]
1100111CELL.DOUBLE_V1[1]
1111111CELL.TIE_0
spartanxl IO_S0_E switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[1][4]MAIN[0][4]MAIN[0][3]MAIN[1][3]MAIN[2][3]MAIN[2][4]MAIN[3][5]CELL.IMUX_IO_O1[1]
Source
0111101CELL.TIE_0
1011101CELL.LONG_IO_H[2]
1011110CELL_E.DOUBLE_V0[1]
1101101CELL_E.DOUBLE_V1[0]
1101110CELL_E.LONG_V[2]
1110101CELL_E.LONG_V[0]
1111001CELL_E.LONG_V[1]
spartanxl IO_S0_E switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[23][5]MAIN[23][6]MAIN[24][6]MAIN[25][6]MAIN[28][6]MAIN[26][6]CELL.IMUX_IO_OK[0]
Source
001100CELL.GCLK[1]
001111CELL.SINGLE_V[3]
010100CELL.GCLK[2]
010111CELL.SINGLE_V[4]
011000CELL.GCLK[3]
011011CELL.SINGLE_V[5]
111100CELL.GCLK[0]
111111CELL.SINGLE_V[2]
spartanxl IO_S0_E switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[11][6]MAIN[10][6]MAIN[10][5]MAIN[12][5]MAIN[11][5]MAIN[13][5]CELL.IMUX_IO_OK[1]
Source
000011CELL.GCLK[1]
000101CELL.GCLK[2]
000110CELL.GCLK[3]
001111CELL.GCLK[0]
110011CELL_E.SINGLE_V[2]
110101CELL_E.SINGLE_V[3]
110110CELL_E.SINGLE_V[5]
111111CELL_E.SINGLE_V[4]
spartanxl IO_S0_E switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[18][5]MAIN[19][5]MAIN[20][5]MAIN[21][5]MAIN[19][6]MAIN[18][6]CELL.IMUX_IO_IK[0]
Source
001100CELL.GCLK[1]
001111CELL.SINGLE_V[2]
010100CELL.GCLK[2]
010111CELL.SINGLE_V[4]
011000CELL.GCLK[3]
011011CELL.SINGLE_V[5]
111100CELL.GCLK[0]
111111CELL.SINGLE_V[3]
spartanxl IO_S0_E switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[16][6]MAIN[14][6]MAIN[14][5]MAIN[15][5]MAIN[16][5]MAIN[17][5]CELL.IMUX_IO_IK[1]
Source
000011CELL.GCLK[1]
000101CELL.GCLK[2]
000110CELL.GCLK[3]
001111CELL.GCLK[0]
110011CELL_E.SINGLE_V[2]
110101CELL_E.SINGLE_V[3]
110110CELL_E.SINGLE_V[4]
111111CELL_E.SINGLE_V[5]
spartanxl IO_S0_E switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[5][2]MAIN[3][2]MAIN[6][0]MAIN[6][1]MAIN[6][2]MAIN[4][2]MAIN[5][1]MAIN[4][1]CELL.IMUX_IO_T[0]
Source
00011111CELL.TIE_0
00101110CELL.GCLK[0]
00110011CELL.LONG_IO_H[3]
00110101CELL.LONG_IO_H[0]
00110110CELL.LONG_IO_H[2]
01101111CELL.DOUBLE_IO_S0[1]
01110111CELL.DOUBLE_IO_S1[0]
10111011CELL.DOUBLE_IO_S1[1]
10111101CELL.LONG_IO_H[1]
11111111CELL.DOUBLE_IO_S0[0]
spartanxl IO_S0_E switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[0][1]MAIN[1][2]MAIN[11][2]MAIN[2][1]MAIN[2][2]MAIN[3][1]MAIN[1][1]MAIN[0][2]CELL.IMUX_IO_T[1]
Source
00011111CELL.TIE_0
00100111CELL.LONG_IO_H[0]
00101011CELL.GCLK[0]
00110101CELL.LONG_IO_H[3]
00110110CELL.LONG_IO_H[2]
01101111CELL.DOUBLE_IO_S0[0]
01111101CELL.LONG_IO_H[1]
10110111CELL.DOUBLE_IO_S0[1]
10111011CELL.DOUBLE_IO_S1[1]
11111111CELL.DOUBLE_IO_S1[0]

Bels IO

spartanxl IO_S0_E bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[22][0]CELL.IMUX_IO_IK[1] invert by !MAIN[13][0]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[32][0]CELL.IMUX_IO_OK[1] invert by !MAIN[2][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_F4CELL.IMUX_CLB_G4
TinCELL.IMUX_IO_T[0] invert by !MAIN[34][0]CELL.IMUX_IO_T[1] invert by !MAIN[0][0]
I1outCELL.OUT_IO_SN_I1[0]CELL.OUT_IO_SN_I1[1]
I2outCELL.OUT_IO_SN_I2[0]CELL.OUT_IO_SN_I2[1]
CLKINout-CELL.OUT_IO_CLKIN
spartanxl IO_S0_E bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[23][0]!MAIN[12][0]
OFF_SRVAL bit 0!MAIN[24][1]!MAIN[11][1]
READBACK_I1 bit 0!MAIN[18][3]!MAIN[17][2]
READBACK_I2 bit 0!MAIN[18][2]!MAIN[17][3]
READBACK_OQ bit 0!MAIN[16][3]!MAIN[16][2]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[25][0]!MAIN[9][0]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[24][0]MAIN[10][0]
IFF_CE_ENABLE!MAIN[19][1]!MAIN[13][2]
OFF_CE_ENABLE!MAIN[30][0]!MAIN[12][2]
SYNC_D[enum: IO_SYNC_D][enum: IO_SYNC_D]
IFF_CE_ENABLE_NO_IQ!MAIN[8][4]!MAIN[8][3]
MUX_T[enum: IO_MUX_T][enum: IO_MUX_T]
DRIVE[enum: IO_DRIVE][enum: IO_DRIVE]
_5V_TOLERANTMAIN[13][4]MAIN[12][4]
spartanxl IO_S0_E enum IO_SLEW
IO[0].SLEWMAIN[33][0]
IO[1].SLEWMAIN[1][0]
FAST0
SLOW1
spartanxl IO_S0_E enum IO_PULL
IO[0].PULLMAIN[22][1]MAIN[23][1]
IO[1].PULLMAIN[13][1]MAIN[12][1]
NONE11
PULLUP01
PULLDOWN10
spartanxl IO_S0_E enum IO_MUX_I
IO[0].MUX_I1MAIN[19][0]MAIN[17][0]
IO[1].MUX_I1MAIN[16][0]MAIN[15][1]
IO[0].MUX_I2MAIN[21][0]MAIN[20][0]
IO[1].MUX_I2MAIN[15][0]MAIN[14][0]
I01
IQ11
IQL10
spartanxl IO_S0_E enum IO_IFF_D
IO[0].IFF_DMAIN[18][0]MAIN[20][1]
IO[1].IFF_DMAIN[16][1]MAIN[14][1]
I11
DELAY00
MEDDELAY01
SYNC10
spartanxl IO_S0_E enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[26][0]
IO[1].MUX_OFF_DMAIN[8][0]
O11
O20
spartanxl IO_S0_E enum IO_MUX_O
IO[0].MUX_OMAIN[28][0]MAIN[27][0]MAIN[29][0]MAIN[31][0]
IO[1].MUX_OMAIN[4][0]MAIN[3][0]MAIN[7][0]MAIN[5][0]
O10000
O1_INV0001
O20111
O2_INV1111
OQ0010
MUX1011
spartanxl IO_S0_E enum IO_SYNC_D
IO[0].SYNC_DMAIN[21][1]
IO[1].SYNC_DMAIN[11][0]
I1
DELAY0
spartanxl IO_S0_E enum IO_MUX_T
IO[0].MUX_TMAIN[13][3]
IO[1].MUX_TMAIN[10][3]
T1
TQ0
spartanxl IO_S0_E enum IO_DRIVE
IO[0].DRIVEMAIN[14][4]
IO[1].DRIVEMAIN[12][3]
_121
_240

Bels CIN

spartanxl IO_S0_E bel CIN pins
PinDirectionCIN
IinCELL.IMUX_CIN

Bel wires

spartanxl IO_S0_E bel wires
WirePins
CELL.IMUX_CLB_F4IO[0].O2
CELL.IMUX_CLB_G4IO[1].O2
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.IMUX_CINCIN.I
CELL.OUT_IO_SN_I1[0]IO[0].I1
CELL.OUT_IO_SN_I1[1]IO[1].I1
CELL.OUT_IO_SN_I2[0]IO[0].I2
CELL.OUT_IO_SN_I2[1]IO[1].I2
CELL.OUT_IO_CLKINIO[1].CLKIN

Bitstream

spartanxl IO_S0_E rect MAIN
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B12 INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] - - - INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 2 - - INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 2
B11 - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - - - - - - - - - INT: mux CELL.IMUX_CLB_F2 bit 2 INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_F4 bit 6 - - INT: mux CELL.IMUX_CLB_G4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 3
B10 INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3] - - - - - INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 4 - - INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7
B9 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_SN_I2[1] - INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_F4 bit 3 - INT: mux CELL.IMUX_CLB_F4 bit 5 - - INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 6
B8 INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.LONG_V[1] bit 1 - INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1 - INT: mux CELL.IMUX_IO_OK[0] bit 1 - INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0] - - INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 5 - INT: mux CELL.IMUX_IO_IK[1] bit 4 - - INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 4 - INT: mux CELL.LONG_V[5] bit 0 INT: mux CELL.LONG_V[3] bit 1 INT: mux CELL.LONG_V[3] bit 0 - INT: mux CELL.LONG_IO_H[0] bit 1 - INT: mux CELL.LONG_V[4] bit 1 INT: mux CELL.LONG_V[4] bit 0 -
B5 INT: mux CELL.LONG_V[1] bit 2 - INT: mux CELL.LONG_V[1] bit 0 INT: mux CELL.LONG_V[2] bit 1 INT: mux CELL.LONG_V[2] bit 2 INT: mux CELL.LONG_V[2] bit 0 INT: mux CELL.LONG_V[0] bit 1 - INT: mux CELL.LONG_V[0] bit 0 INT: mux CELL.LONG_V[0] bit 2 INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_IO_SN_I1[0] INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[4] INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 5 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.LONG_V[5] bit 1 INT: mux CELL.LONG_V[5] bit 2 - INT: mux CELL.LONG_V[3] bit 2 INT: mux CELL.LONG_V[4] bit 2 INT: mux CELL.LONG_IO_H[3] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 0 - - -
B4 - INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_IO_H[3] INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_IO_H[2] INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_IO_SN_I1_E1 - - INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 6 INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0] - INT: mux CELL.LONG_IO_H[3] bit 0 INT: mux CELL.LONG_IO_H[2] bit 0 INT: mux CELL.LONG_IO_H[2] bit 1 INT: mux CELL.LONG_IO_H[2] bit 2 - INT: mux CELL.LONG_IO_H[1] bit 1 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[1] INT: mux CELL.LONG_IO_H[0] bit 0 INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[0] IO[0]: DRIVE bit 0 IO[0]: _5V_TOLERANT IO[1]: _5V_TOLERANT - - - IO[0]: ! IFF_CE_ENABLE_NO_IQ - - - - - INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 6 INT: mux CELL.IMUX_IO_O1[1] bit 5
B3 INT: mux CELL.DBUF_IO_H[1] bit 1 INT: mux CELL.DBUF_IO_H[1] bit 2 INT: mux CELL.DBUF_IO_H[1] bit 3 INT: !bipass CELL.DOUBLE_IO_S0[3] = CELL.DOUBLE_IO_S2[3] INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_S1[3] INT: !bipass CELL.DOUBLE_IO_S0[2] = CELL.DOUBLE_IO_S2[2] INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 5 INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S1[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S1[1] INT: mux CELL.LONG_IO_H[1] bit 3 INT: mux CELL.LONG_IO_H[2] bit 3 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0] - IO[0]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I2 bit 0 IO[0]: ! READBACK_OQ bit 0 - - IO[0]: MUX_T bit 0 IO[1]: DRIVE bit 0 - IO[1]: MUX_T bit 0 - IO[1]: ! IFF_CE_ENABLE_NO_IQ - - - - - INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 4
B2 INT: !pass CELL.DOUBLE_IO_S2[0] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_S2[1] ← CELL.DBUF_IO_H[0] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S2[3] INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_S2[3] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S0[3] INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_S0[2] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S1[2] INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_S1[2] INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S0[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S0[1] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.DOUBLE_IO_S0[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S1[0] - IO[0]: ! READBACK_I2 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_OQ bit 0 - INT: mux CELL.LONG_IO_H[1] bit 2 IO[1]: ! IFF_CE_ENABLE IO[1]: ! OFF_CE_ENABLE INT: mux CELL.IMUX_IO_T[1] bit 5 INT: !pass CELL.DOUBLE_IO_S0[0] ← CELL.DBUF_IO_H[1] INT: !pass CELL.DOUBLE_IO_S0[1] ← CELL.DBUF_IO_H[1] INT: mux CELL.DBUF_IO_H[0] bit 2 INT: mux CELL.DBUF_IO_H[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 7 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 6 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 6 INT: mux CELL.IMUX_IO_T[1] bit 0
B1 INT: !pass CELL.DOUBLE_IO_S2[3] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_S2[2] ← CELL.DBUF_IO_H[0] INT: mux CELL.DBUF_IO_H[1] bit 0 INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_S0[3] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S1[3] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S2[2] INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_S2[2] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S0[2] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S2[1] INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S2[1] INT: !bipass CELL.DOUBLE_IO_S0[1] = CELL.DOUBLE_IO_S2[1] IO[0]: ! OFF_SRVAL bit 0 IO[0]: PULL bit 0 IO[0]: PULL bit 1 IO[0]: SYNC_D bit 0 IO[0]: IFF_D bit 0 IO[0]: ! IFF_CE_ENABLE INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S1[0] INT: mux CELL.LONG_IO_H[1] bit 0 IO[1]: IFF_D bit 1 IO[1]: MUX_I1 bit 0 IO[1]: IFF_D bit 0 IO[1]: PULL bit 1 IO[1]: PULL bit 0 IO[1]: ! OFF_SRVAL bit 0 INT: !pass CELL.DOUBLE_IO_S0[3] ← CELL.DBUF_IO_H[1] INT: !pass CELL.DOUBLE_IO_S0[2] ← CELL.DBUF_IO_H[1] INT: mux CELL.DBUF_IO_H[0] bit 0 INT: mux CELL.DBUF_IO_H[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 7
B0 - IO[0]: !invert T IO[0]: SLEW bit 0 IO[0]: !invert OK IO[0]: MUX_O bit 0 IO[0]: ! OFF_CE_ENABLE IO[0]: MUX_O bit 1 IO[0]: MUX_O bit 3 IO[0]: MUX_O bit 2 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_D_INV IO[0]: OFF_USED IO[0]: ! IFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 1 IO[0]: MUX_I2 bit 0 IO[0]: MUX_I1 bit 1 IO[0]: IFF_D bit 1 IO[0]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I2 bit 0 IO[1]: !invert IK IO[1]: ! IFF_SRVAL bit 0 IO[1]: SYNC_D bit 0 IO[1]: OFF_USED IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0 IO[1]: MUX_O bit 1 INT: mux CELL.IMUX_IO_T[0] bit 5 IO[1]: MUX_O bit 0 IO[1]: MUX_O bit 3 IO[1]: MUX_O bit 2 IO[1]: !invert OK IO[1]: SLEW bit 0 IO[1]: !invert T
spartanxl IO_S0_E rect MAIN_E
BitFrame
F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_S1

Cells: 4

Switchbox INT

spartanxl IO_S1 switchbox INT permanent buffers
DestinationSource
CELL.IMUX_CINCELL.LONG_V[0]
spartanxl IO_S1 switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[3]CELL.SINGLE_V[4]!MAIN[24][5]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[20][9]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[35][9]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[19][9]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[33][11]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[29][9]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[19][12]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[26][9]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[30][11]
spartanxl IO_S1 switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[12][8]
CELL.SINGLE_H[0]CELL.OUT_IO_SN_I2[0]!MAIN[14][8]
CELL.SINGLE_H[1]CELL.OUT_IO_SN_I2[1]!MAIN[15][9]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[14][10]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[11][10]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[13][12]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[20][12]
CELL.SINGLE_H[4]CELL.OUT_IO_SN_I2[0]!MAIN[15][8]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[22][9]
CELL.SINGLE_H[5]CELL.OUT_IO_SN_I2[1]!MAIN[17][9]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[13][9]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[29][12]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[15][10]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[12][12]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[14][12]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[18][9]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[35][12]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[34][10]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[22][8]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I2_E1!MAIN[22][5]
CELL.SINGLE_V[1]CELL.LONG_IO_H[0]!MAIN[15][4]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I2[0]!MAIN[22][6]
CELL.SINGLE_V[2]CELL.LONG_IO_H[1]!MAIN[17][4]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I1[0]!MAIN[25][4]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I1_E1!MAIN[29][4]
CELL.SINGLE_V[4]CELL.LONG_H[3]!MAIN[21][10]
CELL.SINGLE_V[4]CELL.OUT_IO_SN_I2_E1!MAIN[35][6]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[21][9]
CELL.SINGLE_V[5]CELL.LONG_IO_H[2]!MAIN[33][4]
CELL.SINGLE_V[5]CELL.OUT_IO_SN_I2[0]!MAIN[32][6]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[35][10]
CELL.SINGLE_V[6]CELL.LONG_IO_H[3]!MAIN[34][4]
CELL.SINGLE_V[6]CELL.OUT_IO_SN_I1[0]!MAIN[25][5]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[21][12]
CELL.SINGLE_V[7]CELL.OUT_IO_SN_I1_E1!MAIN[32][4]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[13][10]
CELL.DOUBLE_H0[1]CELL.OUT_IO_SN_I2[0]!MAIN[13][8]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[15][12]
CELL.DOUBLE_H1[1]CELL.OUT_IO_SN_I2[1]!MAIN[16][9]
CELL.DOUBLE_V0[0]CELL.OUT_IO_SN_I1_E1!MAIN[21][3]
CELL.DOUBLE_V0[1]CELL.OUT_IO_SN_I2[0]!MAIN[31][6]
CELL.DOUBLE_V1[0]CELL.OUT_IO_SN_I1[0]!MAIN[20][3]
CELL.DOUBLE_V1[1]CELL.OUT_IO_SN_I2_E1!MAIN[30][6]
CELL.DOUBLE_IO_S0[0]CELL.DBUF_IO_H[1]!MAIN[10][2]
CELL.DOUBLE_IO_S0[1]CELL.DBUF_IO_H[1]!MAIN[9][2]
CELL.DOUBLE_IO_S0[2]CELL.DBUF_IO_H[1]!MAIN[9][1]
CELL.DOUBLE_IO_S0[3]CELL.DBUF_IO_H[1]!MAIN[10][1]
CELL.DOUBLE_IO_S2[0]CELL.DBUF_IO_H[0]!MAIN[35][2]
CELL.DOUBLE_IO_S2[1]CELL.DBUF_IO_H[0]!MAIN[34][2]
CELL.DOUBLE_IO_S2[2]CELL.DBUF_IO_H[0]!MAIN[34][1]
CELL.DOUBLE_IO_S2[3]CELL.DBUF_IO_H[0]!MAIN[35][1]
spartanxl IO_S1 switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[18][8]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[21][8]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[17][8]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[25][8]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[24][8]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[23][8]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[27][11]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[26][11]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[28][11]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[26][10]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[23][10]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[25][10]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[31][9]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[34][9]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[30][9]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[31][8]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[30][8]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[33][8]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[30][10]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[31][11]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[31][10]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[33][12]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[30][12]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[32][11]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[20][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[19][8]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[24][9]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[25][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[26][12]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[27][12]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[27][10]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[28][10]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[34][11]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[32][9]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[32][8]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[34][8]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[29][10]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[32][10]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[32][12]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[34][12]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[16][8]
CELL.SINGLE_V[0]CELL.DOUBLE_IO_S1[0]!MAIN[18][1]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[23][9]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_S0[0]!MAIN[22][2]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_S2[0]!MAIN[24][2]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[25][12]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_S1[1]!MAIN[25][3]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[22][10]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_S0[1]!MAIN[27][2]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_S2[1]!MAIN[26][1]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[33][9]
CELL.SINGLE_V[4]CELL.DOUBLE_IO_S1[2]!MAIN[28][2]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[35][8]
CELL.SINGLE_V[5]CELL.DOUBLE_IO_S0[2]!MAIN[30][2]
CELL.SINGLE_V[5]CELL.DOUBLE_IO_S2[2]!MAIN[29][1]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[33][10]
CELL.SINGLE_V[6]CELL.DOUBLE_IO_S1[3]!MAIN[31][3]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[31][12]
CELL.SINGLE_V[7]CELL.DOUBLE_IO_S0[3]!MAIN[32][1]
CELL.SINGLE_V[7]CELL.DOUBLE_IO_S2[3]!MAIN[32][2]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[24][12]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[22][12]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[23][12]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[28][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[27][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[26][8]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[24][10]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[24][11]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[28][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[29][8]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][11]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S0[1]!MAIN[26][2]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S1[1]!MAIN[24][3]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S2[1]!MAIN[27][1]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[27][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S0[2]!MAIN[28][1]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S1[2]!MAIN[29][2]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S2[2]!MAIN[30][1]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S0[0]!MAIN[21][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S1[0]!MAIN[20][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S2[0]!MAIN[25][2]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S0[3]!MAIN[31][2]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S1[3]!MAIN[31][1]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S2[3]!MAIN[33][2]
CELL.DOUBLE_IO_S0[0]CELL.DOUBLE_IO_S2[0]!MAIN[23][2]
CELL.DOUBLE_IO_S0[1]CELL.DOUBLE_IO_S2[1]!MAIN[25][1]
CELL.DOUBLE_IO_S0[2]CELL.DOUBLE_IO_S2[2]!MAIN[30][3]
CELL.DOUBLE_IO_S0[3]CELL.DOUBLE_IO_S2[3]!MAIN[32][3]
spartanxl IO_S1 switchbox INT muxes DBUF_IO_H[0]
BitsDestination
MAIN[7][2]MAIN[8][2]MAIN[7][1]MAIN[8][1]CELL.DBUF_IO_H[0]
Source
0011CELL.DOUBLE_IO_S0[0]
0101CELL.DOUBLE_IO_S0[2]
0110CELL.DOUBLE_IO_S0[3]
1111CELL.DOUBLE_IO_S0[1]
spartanxl IO_S1 switchbox INT muxes DBUF_IO_H[1]
BitsDestination
MAIN[33][3]MAIN[34][3]MAIN[35][3]MAIN[33][1]CELL.DBUF_IO_H[1]
Source
0011CELL.DOUBLE_IO_S2[1]
0101CELL.DOUBLE_IO_S2[2]
0110CELL.DOUBLE_IO_S2[3]
1111CELL.DOUBLE_IO_S2[0]
spartanxl IO_S1 switchbox INT muxes LONG_V[0]
BitsDestination
MAIN[26][5]MAIN[29][5]MAIN[27][5]CELL.LONG_V[0]
Source
000CELL.LONG_IO_H[0]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_S1 switchbox INT muxes LONG_V[1]
BitsDestination
MAIN[35][5]MAIN[34][6]MAIN[33][5]CELL.LONG_V[1]
Source
000CELL.LONG_IO_H[1]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_S1 switchbox INT muxes LONG_V[2]
BitsDestination
MAIN[31][5]MAIN[32][5]MAIN[30][5]CELL.LONG_V[2]
Source
000CELL.LONG_IO_H[2]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_S1 switchbox INT muxes LONG_V[3]
BitsDestination
MAIN[6][5]MAIN[7][6]MAIN[6][6]CELL.LONG_V[3]
Source
000CELL.LONG_IO_H[1]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_S1 switchbox INT muxes LONG_V[4]
BitsDestination
MAIN[5][5]MAIN[2][6]MAIN[1][6]CELL.LONG_V[4]
Source
000CELL.LONG_IO_H[2]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_S1 switchbox INT muxes LONG_V[5]
BitsDestination
MAIN[8][5]MAIN[9][5]MAIN[8][6]CELL.LONG_V[5]
Source
000CELL.LONG_IO_H[3]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_S1 switchbox INT muxes LONG_IO_H[0]
BitsDestination
MAIN[4][6]MAIN[16][4]CELL.LONG_IO_H[0]
Source
00CELL.LONG_V[0]
01CELL.SINGLE_V[1]
11off
spartanxl IO_S1 switchbox INT muxes LONG_IO_H[1]
BitsDestination
MAIN[23][3]MAIN[14][2]MAIN[18][4]MAIN[17][1]CELL.LONG_IO_H[1]
Source
0001CELL.LONG_V[1]
0010CELL.LONG_V[3]
0111CELL.SINGLE_V[2]
1111off
spartanxl IO_S1 switchbox INT muxes LONG_IO_H[2]
BitsDestination
MAIN[22][3]MAIN[20][4]MAIN[21][4]MAIN[22][4]CELL.LONG_IO_H[2]
Source
0001CELL.LONG_V[2]
0010CELL.LONG_V[4]
0111CELL.SINGLE_V[5]
1111off
spartanxl IO_S1 switchbox INT muxes LONG_IO_H[3]
BitsDestination
MAIN[4][5]MAIN[23][4]CELL.LONG_IO_H[3]
Source
00CELL.LONG_V[5]
01CELL.SINGLE_V[6]
11off
spartanxl IO_S1 switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[10][12]MAIN[10][10]MAIN[11][9]MAIN[11][11]MAIN[11][12]MAIN[12][11]MAIN[12][10]MAIN[12][9]CELL.IMUX_CLB_F2
Source
00110011CELL.SINGLE_H[5]
00110101CELL.LONG_H[5]
00110110CELL.DOUBLE_H1[1]
00111111CELL.SINGLE_H[0]
01010011CELL.SINGLE_H[4]
01010101CELL.DOUBLE_H0[1]
01010110CELL.LONG_H[4]
01011111CELL.SINGLE_H[1]
01100011CELL.SINGLE_H[6]
01100101CELL_N.LONG_H_BUF[2]
01100110CELL_N.LONG_H[0]
01101111CELL.SINGLE_H[3]
11110011CELL.DOUBLE_H0[0]
11110101CELL.SINGLE_H[7]
11110110CELL.DOUBLE_H1[0]
11111111CELL.SINGLE_H[2]
spartanxl IO_S1 switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[9][10]MAIN[9][11]MAIN[8][9]MAIN[8][10]MAIN[10][9]MAIN[8][12]MAIN[9][12]MAIN[10][11]CELL.IMUX_CLB_F4
Source
00001111CELL.SINGLE_H[0]
00011011CELL.DOUBLE_H1[0]
00011101CELL_N.LONG_H[0]
00111111CELL.SINGLE_H[1]
01000111CELL.LONG_H[5]
01001110CELL.LONG_H[3]
01010011CELL.SINGLE_H[2]
01010101CELL.SINGLE_H[3]
01011010CELL.SINGLE_H[7]
01011100CELL_N.LONG_H[1]
01110111CELL.DOUBLE_H1[1]
01111110CELL.DOUBLE_H0[1]
11001111CELL.SINGLE_H[5]
11011011CELL.DOUBLE_H0[0]
11011101CELL.SINGLE_H[6]
11111111CELL.SINGLE_H[4]
spartanxl IO_S1 switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[2][10]MAIN[3][10]MAIN[3][12]MAIN[2][9]MAIN[3][11]MAIN[2][11]MAIN[2][12]MAIN[3][9]MAIN[4][11]CELL.IMUX_CLB_G2
Source
000111111CELL.SPECIAL_CLB_COUT0
001001111CELL.LONG_H[4]
001011101CELL.SINGLE_H[4]
001011110CELL.LONG_H[5]
001100111CELL.SINGLE_H[2]
001101011CELL.SINGLE_H[3]
001110101CELL.SINGLE_H[7]
001110110CELL.DOUBLE_H0[0]
001111001CELL_N.LONG_H_BUF[2]
001111010CELL.SINGLE_H[6]
011011111CELL.SINGLE_H[1]
011110111CELL_N.LONG_H[0]
011111011CELL.DOUBLE_H1[0]
101101111CELL.DOUBLE_H1[1]
101111101CELL.SINGLE_H[5]
101111110CELL.DOUBLE_H0[1]
111111111CELL.SINGLE_H[0]
spartanxl IO_S1 switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[5][12]MAIN[4][12]MAIN[6][11]MAIN[4][9]MAIN[4][10]MAIN[5][10]MAIN[5][11]MAIN[5][9]CELL.IMUX_CLB_G4
Source
00001111CELL.SINGLE_H[0]
00010111CELL.SINGLE_H[1]
00011101CELL_N.LONG_H[0]
00101011CELL.DOUBLE_H1[1]
00101110CELL.LONG_H[3]
00110011CELL.LONG_H[5]
00110110CELL.DOUBLE_H0[1]
00111001CELL.SINGLE_H[3]
00111100CELL.SINGLE_H[6]
01011111CELL.DOUBLE_H1[0]
01111011CELL.SINGLE_H[2]
01111110CELL.DOUBLE_H0[0]
10101111CELL.SINGLE_H[5]
10110111CELL.SINGLE_H[4]
10111101CELL_N.LONG_H[1]
11111111CELL.SINGLE_H[7]
spartanxl IO_S1 switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[0][10]MAIN[0][9]MAIN[1][10]MAIN[1][12]MAIN[0][11]MAIN[0][12]MAIN[1][9]MAIN[1][11]CELL.IMUX_CLB_C2
Source
00001111CELL.LONG_H[4]
00011101CELL.SINGLE_H[5]
00011110CELL.LONG_H[3]
00111111CELL.SINGLE_H[0]
01000111CELL.SINGLE_H[2]
01001011CELL.SINGLE_H[3]
01010101CELL.SINGLE_H[7]
01010110CELL.DOUBLE_H0[0]
01011001CELL_N.LONG_H[1]
01011010CELL.SINGLE_H[6]
01110111CELL.DOUBLE_H1[0]
01111011CELL_N.LONG_H_BUF[2]
11001111CELL.DOUBLE_H1[1]
11011101CELL.SINGLE_H[4]
11011110CELL.DOUBLE_H0[1]
11111111CELL.SINGLE_H[1]
spartanxl IO_S1 switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[26][4]MAIN[26][3]MAIN[29][3]MAIN[28][4]MAIN[27][3]MAIN[28][3]MAIN[27][4]CELL.IMUX_IO_O1[0]
Source
0011111CELL.DOUBLE_V0[0]
0100110CELL.LONG_V[5]
0111011CELL.LONG_V[3]
0111101CELL.LONG_V[4]
1100111CELL.DOUBLE_V1[1]
1111111CELL.TIE_0
spartanxl IO_S1 switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[1][4]MAIN[0][4]MAIN[0][3]MAIN[1][3]MAIN[2][3]MAIN[2][4]MAIN[3][5]CELL.IMUX_IO_O1[1]
Source
0111101CELL.TIE_0
1011101CELL.LONG_IO_H[2]
1011110CELL_E.DOUBLE_V0[1]
1101101CELL_E.DOUBLE_V1[0]
1101110CELL_E.LONG_V[2]
1110101CELL_E.LONG_V[0]
1111001CELL_E.LONG_V[1]
spartanxl IO_S1 switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[23][5]MAIN[23][6]MAIN[24][6]MAIN[25][6]MAIN[28][6]MAIN[26][6]CELL.IMUX_IO_OK[0]
Source
001100CELL.GCLK[1]
001111CELL.SINGLE_V[3]
010100CELL.GCLK[2]
010111CELL.SINGLE_V[4]
011000CELL.GCLK[3]
011011CELL.SINGLE_V[5]
111100CELL.GCLK[0]
111111CELL.SINGLE_V[2]
spartanxl IO_S1 switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[11][6]MAIN[10][6]MAIN[10][5]MAIN[12][5]MAIN[11][5]MAIN[13][5]CELL.IMUX_IO_OK[1]
Source
000011CELL.GCLK[1]
000101CELL.GCLK[2]
000110CELL.GCLK[3]
001111CELL.GCLK[0]
110011CELL_E.SINGLE_V[2]
110101CELL_E.SINGLE_V[3]
110110CELL_E.SINGLE_V[5]
111111CELL_E.SINGLE_V[4]
spartanxl IO_S1 switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[18][5]MAIN[19][5]MAIN[20][5]MAIN[21][5]MAIN[19][6]MAIN[18][6]CELL.IMUX_IO_IK[0]
Source
001100CELL.GCLK[1]
001111CELL.SINGLE_V[2]
010100CELL.GCLK[2]
010111CELL.SINGLE_V[4]
011000CELL.GCLK[3]
011011CELL.SINGLE_V[5]
111100CELL.GCLK[0]
111111CELL.SINGLE_V[3]
spartanxl IO_S1 switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[16][6]MAIN[14][6]MAIN[14][5]MAIN[15][5]MAIN[16][5]MAIN[17][5]CELL.IMUX_IO_IK[1]
Source
000011CELL.GCLK[1]
000101CELL.GCLK[2]
000110CELL.GCLK[3]
001111CELL.GCLK[0]
110011CELL_E.SINGLE_V[2]
110101CELL_E.SINGLE_V[3]
110110CELL_E.SINGLE_V[4]
111111CELL_E.SINGLE_V[5]
spartanxl IO_S1 switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[5][2]MAIN[3][2]MAIN[6][0]MAIN[6][1]MAIN[6][2]MAIN[4][2]MAIN[5][1]MAIN[4][1]CELL.IMUX_IO_T[0]
Source
00011111CELL.TIE_0
00101110CELL.GCLK[0]
00110011CELL.LONG_IO_H[3]
00110101CELL.LONG_IO_H[0]
00110110CELL.LONG_IO_H[2]
01101111CELL.DOUBLE_IO_S0[1]
01110111CELL.DOUBLE_IO_S1[0]
10111011CELL.DOUBLE_IO_S1[1]
10111101CELL.LONG_IO_H[1]
11111111CELL.DOUBLE_IO_S0[0]
spartanxl IO_S1 switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[0][1]MAIN[1][2]MAIN[11][2]MAIN[2][1]MAIN[2][2]MAIN[3][1]MAIN[1][1]MAIN[0][2]CELL.IMUX_IO_T[1]
Source
00011111CELL.TIE_0
00100111CELL.LONG_IO_H[0]
00101011CELL.GCLK[0]
00110101CELL.LONG_IO_H[3]
00110110CELL.LONG_IO_H[2]
01101111CELL.DOUBLE_IO_S0[0]
01111101CELL.LONG_IO_H[1]
10110111CELL.DOUBLE_IO_S0[1]
10111011CELL.DOUBLE_IO_S1[1]
11111111CELL.DOUBLE_IO_S1[0]

Bels IO

spartanxl IO_S1 bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[22][0]CELL.IMUX_IO_IK[1] invert by !MAIN[13][0]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[32][0]CELL.IMUX_IO_OK[1] invert by !MAIN[2][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_F4CELL.IMUX_CLB_G4
TinCELL.IMUX_IO_T[0] invert by !MAIN[34][0]CELL.IMUX_IO_T[1] invert by !MAIN[0][0]
I1outCELL.OUT_IO_SN_I1[0]CELL.OUT_IO_SN_I1[1]
I2outCELL.OUT_IO_SN_I2[0]CELL.OUT_IO_SN_I2[1]
spartanxl IO_S1 bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[23][0]!MAIN[12][0]
OFF_SRVAL bit 0!MAIN[24][1]!MAIN[11][1]
READBACK_I1 bit 0!MAIN[18][3]!MAIN[17][2]
READBACK_I2 bit 0!MAIN[18][2]!MAIN[17][3]
READBACK_OQ bit 0!MAIN[16][3]!MAIN[16][2]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[25][0]!MAIN[9][0]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[24][0]MAIN[10][0]
IFF_CE_ENABLE!MAIN[19][1]!MAIN[13][2]
OFF_CE_ENABLE!MAIN[30][0]!MAIN[12][2]
SYNC_D[enum: IO_SYNC_D][enum: IO_SYNC_D]
IFF_CE_ENABLE_NO_IQ!MAIN[8][4]!MAIN[8][3]
MUX_T[enum: IO_MUX_T][enum: IO_MUX_T]
DRIVE[enum: IO_DRIVE][enum: IO_DRIVE]
_5V_TOLERANTMAIN[13][4]MAIN[12][4]
spartanxl IO_S1 enum IO_SLEW
IO[0].SLEWMAIN[33][0]
IO[1].SLEWMAIN[1][0]
FAST0
SLOW1
spartanxl IO_S1 enum IO_PULL
IO[0].PULLMAIN[22][1]MAIN[23][1]
IO[1].PULLMAIN[13][1]MAIN[12][1]
NONE11
PULLUP01
PULLDOWN10
spartanxl IO_S1 enum IO_MUX_I
IO[0].MUX_I1MAIN[19][0]MAIN[17][0]
IO[1].MUX_I1MAIN[16][0]MAIN[15][1]
IO[0].MUX_I2MAIN[21][0]MAIN[20][0]
IO[1].MUX_I2MAIN[15][0]MAIN[14][0]
I01
IQ11
IQL10
spartanxl IO_S1 enum IO_IFF_D
IO[0].IFF_DMAIN[18][0]MAIN[20][1]
IO[1].IFF_DMAIN[16][1]MAIN[14][1]
I11
DELAY00
MEDDELAY01
SYNC10
spartanxl IO_S1 enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[26][0]
IO[1].MUX_OFF_DMAIN[8][0]
O11
O20
spartanxl IO_S1 enum IO_MUX_O
IO[0].MUX_OMAIN[28][0]MAIN[27][0]MAIN[29][0]MAIN[31][0]
IO[1].MUX_OMAIN[4][0]MAIN[3][0]MAIN[7][0]MAIN[5][0]
O10000
O1_INV0001
O20111
O2_INV1111
OQ0010
MUX1011
spartanxl IO_S1 enum IO_SYNC_D
IO[0].SYNC_DMAIN[21][1]
IO[1].SYNC_DMAIN[11][0]
I1
DELAY0
spartanxl IO_S1 enum IO_MUX_T
IO[0].MUX_TMAIN[13][3]
IO[1].MUX_TMAIN[10][3]
T1
TQ0
spartanxl IO_S1 enum IO_DRIVE
IO[0].DRIVEMAIN[14][4]
IO[1].DRIVEMAIN[12][3]
_121
_240

Bels CIN

spartanxl IO_S1 bel CIN pins
PinDirectionCIN
IinCELL.IMUX_CIN

Bel wires

spartanxl IO_S1 bel wires
WirePins
CELL.IMUX_CLB_F4IO[0].O2
CELL.IMUX_CLB_G4IO[1].O2
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.IMUX_CINCIN.I
CELL.OUT_IO_SN_I1[0]IO[0].I1
CELL.OUT_IO_SN_I1[1]IO[1].I1
CELL.OUT_IO_SN_I2[0]IO[0].I2
CELL.OUT_IO_SN_I2[1]IO[1].I2

Bitstream

spartanxl IO_S1 rect MAIN
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B12 INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] - - - INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 2 - - INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 2
B11 - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - - - - - - - - - INT: mux CELL.IMUX_CLB_F2 bit 2 INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_F4 bit 6 - - INT: mux CELL.IMUX_CLB_G4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 3
B10 INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3] - - - - - INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 4 - - INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7
B9 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_SN_I2[1] - INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_F4 bit 3 - INT: mux CELL.IMUX_CLB_F4 bit 5 - - INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 6
B8 INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.LONG_V[1] bit 1 - INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1 - INT: mux CELL.IMUX_IO_OK[0] bit 1 - INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0] - - INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 5 - INT: mux CELL.IMUX_IO_IK[1] bit 4 - - INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 4 - INT: mux CELL.LONG_V[5] bit 0 INT: mux CELL.LONG_V[3] bit 1 INT: mux CELL.LONG_V[3] bit 0 - INT: mux CELL.LONG_IO_H[0] bit 1 - INT: mux CELL.LONG_V[4] bit 1 INT: mux CELL.LONG_V[4] bit 0 -
B5 INT: mux CELL.LONG_V[1] bit 2 - INT: mux CELL.LONG_V[1] bit 0 INT: mux CELL.LONG_V[2] bit 1 INT: mux CELL.LONG_V[2] bit 2 INT: mux CELL.LONG_V[2] bit 0 INT: mux CELL.LONG_V[0] bit 1 - INT: mux CELL.LONG_V[0] bit 0 INT: mux CELL.LONG_V[0] bit 2 INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_IO_SN_I1[0] INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[4] INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 5 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.LONG_V[5] bit 1 INT: mux CELL.LONG_V[5] bit 2 - INT: mux CELL.LONG_V[3] bit 2 INT: mux CELL.LONG_V[4] bit 2 INT: mux CELL.LONG_IO_H[3] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 0 - - -
B4 - INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_IO_H[3] INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_IO_H[2] INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_IO_SN_I1_E1 - - INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 6 INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0] - INT: mux CELL.LONG_IO_H[3] bit 0 INT: mux CELL.LONG_IO_H[2] bit 0 INT: mux CELL.LONG_IO_H[2] bit 1 INT: mux CELL.LONG_IO_H[2] bit 2 - INT: mux CELL.LONG_IO_H[1] bit 1 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[1] INT: mux CELL.LONG_IO_H[0] bit 0 INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[0] IO[0]: DRIVE bit 0 IO[0]: _5V_TOLERANT IO[1]: _5V_TOLERANT - - - IO[0]: ! IFF_CE_ENABLE_NO_IQ - - - - - INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 6 INT: mux CELL.IMUX_IO_O1[1] bit 5
B3 INT: mux CELL.DBUF_IO_H[1] bit 1 INT: mux CELL.DBUF_IO_H[1] bit 2 INT: mux CELL.DBUF_IO_H[1] bit 3 INT: !bipass CELL.DOUBLE_IO_S0[3] = CELL.DOUBLE_IO_S2[3] INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_S1[3] INT: !bipass CELL.DOUBLE_IO_S0[2] = CELL.DOUBLE_IO_S2[2] INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 5 INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S1[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S1[1] INT: mux CELL.LONG_IO_H[1] bit 3 INT: mux CELL.LONG_IO_H[2] bit 3 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0] - IO[0]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I2 bit 0 IO[0]: ! READBACK_OQ bit 0 - - IO[0]: MUX_T bit 0 IO[1]: DRIVE bit 0 - IO[1]: MUX_T bit 0 - IO[1]: ! IFF_CE_ENABLE_NO_IQ - - - - - INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 4
B2 INT: !pass CELL.DOUBLE_IO_S2[0] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_S2[1] ← CELL.DBUF_IO_H[0] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S2[3] INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_S2[3] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S0[3] INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_S0[2] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S1[2] INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_S1[2] INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S0[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S0[1] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.DOUBLE_IO_S0[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S1[0] - IO[0]: ! READBACK_I2 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_OQ bit 0 - INT: mux CELL.LONG_IO_H[1] bit 2 IO[1]: ! IFF_CE_ENABLE IO[1]: ! OFF_CE_ENABLE INT: mux CELL.IMUX_IO_T[1] bit 5 INT: !pass CELL.DOUBLE_IO_S0[0] ← CELL.DBUF_IO_H[1] INT: !pass CELL.DOUBLE_IO_S0[1] ← CELL.DBUF_IO_H[1] INT: mux CELL.DBUF_IO_H[0] bit 2 INT: mux CELL.DBUF_IO_H[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 7 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 6 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 6 INT: mux CELL.IMUX_IO_T[1] bit 0
B1 INT: !pass CELL.DOUBLE_IO_S2[3] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_S2[2] ← CELL.DBUF_IO_H[0] INT: mux CELL.DBUF_IO_H[1] bit 0 INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_S0[3] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S1[3] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S2[2] INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_S2[2] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S0[2] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S2[1] INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S2[1] INT: !bipass CELL.DOUBLE_IO_S0[1] = CELL.DOUBLE_IO_S2[1] IO[0]: ! OFF_SRVAL bit 0 IO[0]: PULL bit 0 IO[0]: PULL bit 1 IO[0]: SYNC_D bit 0 IO[0]: IFF_D bit 0 IO[0]: ! IFF_CE_ENABLE INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S1[0] INT: mux CELL.LONG_IO_H[1] bit 0 IO[1]: IFF_D bit 1 IO[1]: MUX_I1 bit 0 IO[1]: IFF_D bit 0 IO[1]: PULL bit 1 IO[1]: PULL bit 0 IO[1]: ! OFF_SRVAL bit 0 INT: !pass CELL.DOUBLE_IO_S0[3] ← CELL.DBUF_IO_H[1] INT: !pass CELL.DOUBLE_IO_S0[2] ← CELL.DBUF_IO_H[1] INT: mux CELL.DBUF_IO_H[0] bit 0 INT: mux CELL.DBUF_IO_H[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 7
B0 - IO[0]: !invert T IO[0]: SLEW bit 0 IO[0]: !invert OK IO[0]: MUX_O bit 0 IO[0]: ! OFF_CE_ENABLE IO[0]: MUX_O bit 1 IO[0]: MUX_O bit 3 IO[0]: MUX_O bit 2 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_D_INV IO[0]: OFF_USED IO[0]: ! IFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 1 IO[0]: MUX_I2 bit 0 IO[0]: MUX_I1 bit 1 IO[0]: IFF_D bit 1 IO[0]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I2 bit 0 IO[1]: !invert IK IO[1]: ! IFF_SRVAL bit 0 IO[1]: SYNC_D bit 0 IO[1]: OFF_USED IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0 IO[1]: MUX_O bit 1 INT: mux CELL.IMUX_IO_T[0] bit 5 IO[1]: MUX_O bit 0 IO[1]: MUX_O bit 3 IO[1]: MUX_O bit 2 IO[1]: !invert OK IO[1]: SLEW bit 0 IO[1]: !invert T
spartanxl IO_S1 rect MAIN_E
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_S1_W

Cells: 4

Switchbox INT

spartanxl IO_S1_W switchbox INT permanent buffers
DestinationSource
CELL.IMUX_CINCELL.LONG_V[0]
spartanxl IO_S1_W switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[3]CELL.SINGLE_V[4]!MAIN[24][5]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[20][9]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[35][9]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[19][9]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[33][11]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[29][9]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[19][12]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[26][9]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[30][11]
spartanxl IO_S1_W switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[12][8]
CELL.SINGLE_H[0]CELL.OUT_IO_SN_I2[0]!MAIN[14][8]
CELL.SINGLE_H[1]CELL.OUT_IO_SN_I2[1]!MAIN[15][9]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[14][10]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[11][10]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[13][12]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[20][12]
CELL.SINGLE_H[4]CELL.OUT_IO_SN_I2[0]!MAIN[15][8]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[22][9]
CELL.SINGLE_H[5]CELL.OUT_IO_SN_I2[1]!MAIN[17][9]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[13][9]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[29][12]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[15][10]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[12][12]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[14][12]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[18][9]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[35][12]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[34][10]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[22][8]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I2_E1!MAIN[22][5]
CELL.SINGLE_V[1]CELL.LONG_IO_H[0]!MAIN[15][4]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I2[0]!MAIN[22][6]
CELL.SINGLE_V[2]CELL.LONG_IO_H[1]!MAIN[17][4]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I1[0]!MAIN[25][4]
CELL.SINGLE_V[4]CELL.LONG_H[3]!MAIN[21][10]
CELL.SINGLE_V[4]CELL.OUT_IO_SN_I2_E1!MAIN[35][6]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[21][9]
CELL.SINGLE_V[5]CELL.LONG_IO_H[2]!MAIN[33][4]
CELL.SINGLE_V[5]CELL.OUT_IO_SN_I2[0]!MAIN[32][6]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[35][10]
CELL.SINGLE_V[6]CELL.LONG_IO_H[3]!MAIN[34][4]
CELL.SINGLE_V[6]CELL.OUT_IO_SN_I1[0]!MAIN[25][5]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[21][12]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[13][10]
CELL.DOUBLE_H0[1]CELL.OUT_IO_SN_I2[0]!MAIN[13][8]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[15][12]
CELL.DOUBLE_H1[1]CELL.OUT_IO_SN_I2[1]!MAIN[16][9]
CELL.DOUBLE_V0[1]CELL.OUT_IO_SN_I2[0]!MAIN[31][6]
CELL.DOUBLE_V1[0]CELL.OUT_IO_SN_I1[0]!MAIN[20][3]
CELL.DOUBLE_V1[1]CELL.OUT_IO_SN_I2_E1!MAIN[30][6]
CELL.DOUBLE_IO_S0[0]CELL.DBUF_IO_H[1]!MAIN[10][2]
CELL.DOUBLE_IO_S0[1]CELL.DBUF_IO_H[1]!MAIN[9][2]
CELL.DOUBLE_IO_S0[2]CELL.DBUF_IO_H[1]!MAIN[9][1]
CELL.DOUBLE_IO_S0[3]CELL.DBUF_IO_H[1]!MAIN[10][1]
CELL.DOUBLE_IO_S2[0]CELL.DBUF_IO_H[0]!MAIN[35][2]
CELL.DOUBLE_IO_S2[1]CELL.DBUF_IO_H[0]!MAIN[34][2]
CELL.DOUBLE_IO_S2[2]CELL.DBUF_IO_H[0]!MAIN[34][1]
CELL.DOUBLE_IO_S2[3]CELL.DBUF_IO_H[0]!MAIN[35][1]
spartanxl IO_S1_W switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[18][8]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[21][8]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[17][8]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[25][8]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[24][8]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[23][8]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[27][11]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[26][11]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[28][11]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[26][10]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[23][10]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[25][10]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[31][9]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[34][9]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[30][9]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[31][8]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[30][8]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[33][8]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[30][10]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[31][11]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[31][10]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[33][12]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[30][12]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[32][11]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[20][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[19][8]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[24][9]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[25][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[26][12]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[27][12]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[27][10]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[28][10]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[34][11]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[32][9]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[32][8]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[34][8]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[29][10]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[32][10]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[32][12]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[34][12]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[16][8]
CELL.SINGLE_V[0]CELL.DOUBLE_IO_S1[0]!MAIN[18][1]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[23][9]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_S0[0]!MAIN[22][2]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_S2[0]!MAIN[24][2]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[25][12]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_S1[1]!MAIN[25][3]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[22][10]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_S0[1]!MAIN[27][2]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_S2[1]!MAIN[26][1]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[33][9]
CELL.SINGLE_V[4]CELL.DOUBLE_IO_S1[2]!MAIN[28][2]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[35][8]
CELL.SINGLE_V[5]CELL.DOUBLE_IO_S0[2]!MAIN[30][2]
CELL.SINGLE_V[5]CELL.DOUBLE_IO_S2[2]!MAIN[29][1]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[33][10]
CELL.SINGLE_V[6]CELL.DOUBLE_IO_S1[3]!MAIN[31][3]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[31][12]
CELL.SINGLE_V[7]CELL.DOUBLE_IO_S0[3]!MAIN[32][1]
CELL.SINGLE_V[7]CELL.DOUBLE_IO_S2[3]!MAIN[32][2]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[24][12]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[22][12]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[23][12]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[28][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[27][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[26][8]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[24][10]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[24][11]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[28][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[29][8]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][11]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S0[1]!MAIN[26][2]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S1[1]!MAIN[24][3]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S2[1]!MAIN[27][1]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[27][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S0[2]!MAIN[28][1]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S1[2]!MAIN[29][2]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S2[2]!MAIN[30][1]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S0[0]!MAIN[21][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S1[0]!MAIN[20][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S2[0]!MAIN[25][2]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S0[3]!MAIN[31][2]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S1[3]!MAIN[31][1]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S2[3]!MAIN[33][2]
CELL.DOUBLE_IO_S0[0]CELL.DOUBLE_IO_S2[0]!MAIN[23][2]
CELL.DOUBLE_IO_S0[1]CELL.DOUBLE_IO_S2[1]!MAIN[25][1]
CELL.DOUBLE_IO_S0[2]CELL.DOUBLE_IO_S2[2]!MAIN[30][3]
CELL.DOUBLE_IO_S0[3]CELL.DOUBLE_IO_S2[3]!MAIN[32][3]
spartanxl IO_S1_W switchbox INT muxes DBUF_IO_H[0]
BitsDestination
MAIN[7][2]MAIN[8][2]MAIN[7][1]MAIN[8][1]CELL.DBUF_IO_H[0]
Source
0011CELL.DOUBLE_IO_S0[0]
0101CELL.DOUBLE_IO_S0[2]
0110CELL.DOUBLE_IO_S0[3]
1111CELL.DOUBLE_IO_S0[1]
spartanxl IO_S1_W switchbox INT muxes DBUF_IO_H[1]
BitsDestination
MAIN[33][3]MAIN[34][3]MAIN[35][3]MAIN[33][1]CELL.DBUF_IO_H[1]
Source
0011CELL.DOUBLE_IO_S2[1]
0101CELL.DOUBLE_IO_S2[2]
0110CELL.DOUBLE_IO_S2[3]
1111CELL.DOUBLE_IO_S2[0]
spartanxl IO_S1_W switchbox INT muxes LONG_V[0]
BitsDestination
MAIN[26][5]MAIN[29][5]MAIN[27][5]CELL.LONG_V[0]
Source
000CELL.LONG_IO_H[0]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_S1_W switchbox INT muxes LONG_V[1]
BitsDestination
MAIN[35][5]MAIN[34][6]MAIN[33][5]CELL.LONG_V[1]
Source
000CELL.LONG_IO_H[1]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_S1_W switchbox INT muxes LONG_V[2]
BitsDestination
MAIN[31][5]MAIN[32][5]MAIN[30][5]CELL.LONG_V[2]
Source
000CELL.LONG_IO_H[2]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_S1_W switchbox INT muxes LONG_V[3]
BitsDestination
MAIN[6][5]MAIN[7][6]MAIN[6][6]CELL.LONG_V[3]
Source
000CELL.LONG_IO_H[1]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_S1_W switchbox INT muxes LONG_V[4]
BitsDestination
MAIN[5][5]MAIN[2][6]MAIN[1][6]CELL.LONG_V[4]
Source
000CELL.LONG_IO_H[2]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_S1_W switchbox INT muxes LONG_V[5]
BitsDestination
MAIN[8][5]MAIN[9][5]MAIN[8][6]CELL.LONG_V[5]
Source
000CELL.LONG_IO_H[3]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_S1_W switchbox INT muxes LONG_IO_H[0]
BitsDestination
MAIN[4][6]MAIN[16][4]CELL.LONG_IO_H[0]
Source
00CELL.LONG_V[0]
01CELL.SINGLE_V[1]
11off
spartanxl IO_S1_W switchbox INT muxes LONG_IO_H[1]
BitsDestination
MAIN[23][3]MAIN[14][2]MAIN[18][4]MAIN[17][1]CELL.LONG_IO_H[1]
Source
0001CELL.LONG_V[1]
0010CELL.LONG_V[3]
0111CELL.SINGLE_V[2]
1111off
spartanxl IO_S1_W switchbox INT muxes LONG_IO_H[2]
BitsDestination
MAIN[22][3]MAIN[20][4]MAIN[21][4]MAIN[22][4]CELL.LONG_IO_H[2]
Source
0001CELL.LONG_V[2]
0010CELL.LONG_V[4]
0111CELL.SINGLE_V[5]
1111off
spartanxl IO_S1_W switchbox INT muxes LONG_IO_H[3]
BitsDestination
MAIN[4][5]MAIN[23][4]CELL.LONG_IO_H[3]
Source
00CELL.LONG_V[5]
01CELL.SINGLE_V[6]
11off
spartanxl IO_S1_W switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[10][12]MAIN[10][10]MAIN[11][9]MAIN[11][11]MAIN[11][12]MAIN[12][11]MAIN[12][10]MAIN[12][9]CELL.IMUX_CLB_F2
Source
00110011CELL.SINGLE_H[5]
00110101CELL.LONG_H[5]
00110110CELL.DOUBLE_H1[1]
00111111CELL.SINGLE_H[0]
01010011CELL.SINGLE_H[4]
01010101CELL.DOUBLE_H0[1]
01010110CELL.LONG_H[4]
01011111CELL.SINGLE_H[1]
01100011CELL.SINGLE_H[6]
01100101CELL_N.LONG_H_BUF[2]
01100110CELL_N.LONG_H[0]
01101111CELL.SINGLE_H[3]
11110011CELL.DOUBLE_H0[0]
11110101CELL.SINGLE_H[7]
11110110CELL.DOUBLE_H1[0]
11111111CELL.SINGLE_H[2]
spartanxl IO_S1_W switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[9][10]MAIN[9][11]MAIN[8][9]MAIN[8][10]MAIN[10][9]MAIN[8][12]MAIN[9][12]MAIN[10][11]CELL.IMUX_CLB_F4
Source
00001111CELL.SINGLE_H[0]
00011011CELL.DOUBLE_H1[0]
00011101CELL_N.LONG_H[0]
00111111CELL.SINGLE_H[1]
01000111CELL.LONG_H[5]
01001110CELL.LONG_H[3]
01010011CELL.SINGLE_H[2]
01010101CELL.SINGLE_H[3]
01011010CELL.SINGLE_H[7]
01011100CELL_N.LONG_H[1]
01110111CELL.DOUBLE_H1[1]
01111110CELL.DOUBLE_H0[1]
11001111CELL.SINGLE_H[5]
11011011CELL.DOUBLE_H0[0]
11011101CELL.SINGLE_H[6]
11111111CELL.SINGLE_H[4]
spartanxl IO_S1_W switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[2][10]MAIN[3][10]MAIN[3][12]MAIN[2][9]MAIN[3][11]MAIN[2][11]MAIN[2][12]MAIN[3][9]MAIN[4][11]CELL.IMUX_CLB_G2
Source
000111111CELL.SPECIAL_CLB_COUT0
001001111CELL.LONG_H[4]
001011101CELL.SINGLE_H[4]
001011110CELL.LONG_H[5]
001100111CELL.SINGLE_H[2]
001101011CELL.SINGLE_H[3]
001110101CELL.SINGLE_H[7]
001110110CELL.DOUBLE_H0[0]
001111001CELL_N.LONG_H_BUF[2]
001111010CELL.SINGLE_H[6]
011011111CELL.SINGLE_H[1]
011110111CELL_N.LONG_H[0]
011111011CELL.DOUBLE_H1[0]
101101111CELL.DOUBLE_H1[1]
101111101CELL.SINGLE_H[5]
101111110CELL.DOUBLE_H0[1]
111111111CELL.SINGLE_H[0]
spartanxl IO_S1_W switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[5][12]MAIN[4][12]MAIN[6][11]MAIN[4][9]MAIN[4][10]MAIN[5][10]MAIN[5][11]MAIN[5][9]CELL.IMUX_CLB_G4
Source
00001111CELL.SINGLE_H[0]
00010111CELL.SINGLE_H[1]
00011101CELL_N.LONG_H[0]
00101011CELL.DOUBLE_H1[1]
00101110CELL.LONG_H[3]
00110011CELL.LONG_H[5]
00110110CELL.DOUBLE_H0[1]
00111001CELL.SINGLE_H[3]
00111100CELL.SINGLE_H[6]
01011111CELL.DOUBLE_H1[0]
01111011CELL.SINGLE_H[2]
01111110CELL.DOUBLE_H0[0]
10101111CELL.SINGLE_H[5]
10110111CELL.SINGLE_H[4]
10111101CELL_N.LONG_H[1]
11111111CELL.SINGLE_H[7]
spartanxl IO_S1_W switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[0][10]MAIN[0][9]MAIN[1][10]MAIN[1][12]MAIN[0][11]MAIN[0][12]MAIN[1][9]MAIN[1][11]CELL.IMUX_CLB_C2
Source
00001111CELL.LONG_H[4]
00011101CELL.SINGLE_H[5]
00011110CELL.LONG_H[3]
00111111CELL.SINGLE_H[0]
01000111CELL.SINGLE_H[2]
01001011CELL.SINGLE_H[3]
01010101CELL.SINGLE_H[7]
01010110CELL.DOUBLE_H0[0]
01011001CELL_N.LONG_H[1]
01011010CELL.SINGLE_H[6]
01110111CELL.DOUBLE_H1[0]
01111011CELL_N.LONG_H_BUF[2]
11001111CELL.DOUBLE_H1[1]
11011101CELL.SINGLE_H[4]
11011110CELL.DOUBLE_H0[1]
11111111CELL.SINGLE_H[1]
spartanxl IO_S1_W switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[26][4]MAIN[26][3]MAIN[29][3]MAIN[28][4]MAIN[27][3]MAIN[28][3]MAIN[27][4]CELL.IMUX_IO_O1[0]
Source
0011111CELL.DOUBLE_V0[0]
0100110CELL.LONG_V[5]
0111011CELL.LONG_V[3]
0111101CELL.LONG_V[4]
1100111CELL.DOUBLE_V1[1]
1111111CELL.TIE_0
spartanxl IO_S1_W switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[1][4]MAIN[0][4]MAIN[0][3]MAIN[1][3]MAIN[2][3]MAIN[2][4]MAIN[3][5]CELL.IMUX_IO_O1[1]
Source
0111101CELL.TIE_0
1011101CELL.LONG_IO_H[2]
1011110CELL_E.DOUBLE_V0[1]
1101101CELL_E.DOUBLE_V1[0]
1101110CELL_E.LONG_V[2]
1110101CELL_E.LONG_V[0]
1111001CELL_E.LONG_V[1]
spartanxl IO_S1_W switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[23][5]MAIN[23][6]MAIN[24][6]MAIN[25][6]MAIN[28][6]MAIN[26][6]CELL.IMUX_IO_OK[0]
Source
001100CELL.GCLK[1]
001111CELL.SINGLE_V[3]
010100CELL.GCLK[2]
010111CELL.SINGLE_V[4]
011000CELL.GCLK[3]
011011CELL.SINGLE_V[5]
111100CELL.GCLK[0]
111111CELL.SINGLE_V[2]
spartanxl IO_S1_W switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[11][6]MAIN[10][6]MAIN[10][5]MAIN[12][5]MAIN[11][5]MAIN[13][5]CELL.IMUX_IO_OK[1]
Source
000011CELL.GCLK[1]
000101CELL.GCLK[2]
000110CELL.GCLK[3]
001111CELL.GCLK[0]
110011CELL_E.SINGLE_V[2]
110101CELL_E.SINGLE_V[3]
110110CELL_E.SINGLE_V[5]
111111CELL_E.SINGLE_V[4]
spartanxl IO_S1_W switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[18][5]MAIN[19][5]MAIN[20][5]MAIN[21][5]MAIN[19][6]MAIN[18][6]CELL.IMUX_IO_IK[0]
Source
001100CELL.GCLK[1]
001111CELL.SINGLE_V[2]
010100CELL.GCLK[2]
010111CELL.SINGLE_V[4]
011000CELL.GCLK[3]
011011CELL.SINGLE_V[5]
111100CELL.GCLK[0]
111111CELL.SINGLE_V[3]
spartanxl IO_S1_W switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[16][6]MAIN[14][6]MAIN[14][5]MAIN[15][5]MAIN[16][5]MAIN[17][5]CELL.IMUX_IO_IK[1]
Source
000011CELL.GCLK[1]
000101CELL.GCLK[2]
000110CELL.GCLK[3]
001111CELL.GCLK[0]
110011CELL_E.SINGLE_V[2]
110101CELL_E.SINGLE_V[3]
110110CELL_E.SINGLE_V[4]
111111CELL_E.SINGLE_V[5]
spartanxl IO_S1_W switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[5][2]MAIN[3][2]MAIN[6][0]MAIN[6][1]MAIN[6][2]MAIN[4][2]MAIN[5][1]MAIN[4][1]CELL.IMUX_IO_T[0]
Source
00011111CELL.TIE_0
00101110CELL.GCLK[0]
00110011CELL.LONG_IO_H[3]
00110101CELL.LONG_IO_H[0]
00110110CELL.LONG_IO_H[2]
01101111CELL.DOUBLE_IO_S0[1]
01110111CELL.DOUBLE_IO_S1[0]
10111011CELL.DOUBLE_IO_S1[1]
10111101CELL.LONG_IO_H[1]
11111111CELL.DOUBLE_IO_S0[0]
spartanxl IO_S1_W switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[0][1]MAIN[1][2]MAIN[11][2]MAIN[2][1]MAIN[2][2]MAIN[3][1]MAIN[1][1]MAIN[0][2]CELL.IMUX_IO_T[1]
Source
00011111CELL.TIE_0
00100111CELL.LONG_IO_H[0]
00101011CELL.GCLK[0]
00110101CELL.LONG_IO_H[3]
00110110CELL.LONG_IO_H[2]
01101111CELL.DOUBLE_IO_S0[0]
01111101CELL.LONG_IO_H[1]
10110111CELL.DOUBLE_IO_S0[1]
10111011CELL.DOUBLE_IO_S1[1]
11111111CELL.DOUBLE_IO_S1[0]

Bels IO

spartanxl IO_S1_W bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[22][0]CELL.IMUX_IO_IK[1] invert by !MAIN[13][0]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[32][0]CELL.IMUX_IO_OK[1] invert by !MAIN[2][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_F4CELL.IMUX_CLB_G4
TinCELL.IMUX_IO_T[0] invert by !MAIN[34][0]CELL.IMUX_IO_T[1] invert by !MAIN[0][0]
I1outCELL.OUT_IO_SN_I1[0]CELL.OUT_IO_SN_I1[1]
I2outCELL.OUT_IO_SN_I2[0]CELL.OUT_IO_SN_I2[1]
CLKINoutCELL.OUT_IO_CLKIN-
spartanxl IO_S1_W bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[23][0]!MAIN[12][0]
OFF_SRVAL bit 0!MAIN[24][1]!MAIN[11][1]
READBACK_I1 bit 0!MAIN[18][3]!MAIN[17][2]
READBACK_I2 bit 0!MAIN[18][2]!MAIN[17][3]
READBACK_OQ bit 0!MAIN[16][3]!MAIN[16][2]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[25][0]!MAIN[9][0]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[24][0]MAIN[10][0]
IFF_CE_ENABLE!MAIN[19][1]!MAIN[13][2]
OFF_CE_ENABLE!MAIN[30][0]!MAIN[12][2]
SYNC_D[enum: IO_SYNC_D][enum: IO_SYNC_D]
IFF_CE_ENABLE_NO_IQ!MAIN[8][4]!MAIN[8][3]
MUX_T[enum: IO_MUX_T][enum: IO_MUX_T]
DRIVE[enum: IO_DRIVE][enum: IO_DRIVE]
_5V_TOLERANTMAIN[13][4]MAIN[12][4]
spartanxl IO_S1_W enum IO_SLEW
IO[0].SLEWMAIN[33][0]
IO[1].SLEWMAIN[1][0]
FAST0
SLOW1
spartanxl IO_S1_W enum IO_PULL
IO[0].PULLMAIN[22][1]MAIN[23][1]
IO[1].PULLMAIN[13][1]MAIN[12][1]
NONE11
PULLUP01
PULLDOWN10
spartanxl IO_S1_W enum IO_MUX_I
IO[0].MUX_I1MAIN[19][0]MAIN[17][0]
IO[1].MUX_I1MAIN[16][0]MAIN[15][1]
IO[0].MUX_I2MAIN[21][0]MAIN[20][0]
IO[1].MUX_I2MAIN[15][0]MAIN[14][0]
I01
IQ11
IQL10
spartanxl IO_S1_W enum IO_IFF_D
IO[0].IFF_DMAIN[18][0]MAIN[20][1]
IO[1].IFF_DMAIN[16][1]MAIN[14][1]
I11
DELAY00
MEDDELAY01
SYNC10
spartanxl IO_S1_W enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[26][0]
IO[1].MUX_OFF_DMAIN[8][0]
O11
O20
spartanxl IO_S1_W enum IO_MUX_O
IO[0].MUX_OMAIN[28][0]MAIN[27][0]MAIN[29][0]MAIN[31][0]
IO[1].MUX_OMAIN[4][0]MAIN[3][0]MAIN[7][0]MAIN[5][0]
O10000
O1_INV0001
O20111
O2_INV1111
OQ0010
MUX1011
spartanxl IO_S1_W enum IO_SYNC_D
IO[0].SYNC_DMAIN[21][1]
IO[1].SYNC_DMAIN[11][0]
I1
DELAY0
spartanxl IO_S1_W enum IO_MUX_T
IO[0].MUX_TMAIN[13][3]
IO[1].MUX_TMAIN[10][3]
T1
TQ0
spartanxl IO_S1_W enum IO_DRIVE
IO[0].DRIVEMAIN[14][4]
IO[1].DRIVEMAIN[12][3]
_121
_240

Bels CIN

spartanxl IO_S1_W bel CIN pins
PinDirectionCIN
IinCELL.IMUX_CIN

Bel wires

spartanxl IO_S1_W bel wires
WirePins
CELL.IMUX_CLB_F4IO[0].O2
CELL.IMUX_CLB_G4IO[1].O2
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.IMUX_CINCIN.I
CELL.OUT_IO_SN_I1[0]IO[0].I1
CELL.OUT_IO_SN_I1[1]IO[1].I1
CELL.OUT_IO_SN_I2[0]IO[0].I2
CELL.OUT_IO_SN_I2[1]IO[1].I2
CELL.OUT_IO_CLKINIO[0].CLKIN

Bitstream

spartanxl IO_S1_W rect MAIN
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B12 INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] - - - INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 2 - - INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 2
B11 - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - - - - - - - - - INT: mux CELL.IMUX_CLB_F2 bit 2 INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_F4 bit 6 - - INT: mux CELL.IMUX_CLB_G4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 3
B10 INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3] - - - - - INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 4 - - INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7
B9 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_SN_I2[1] - INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_F4 bit 3 - INT: mux CELL.IMUX_CLB_F4 bit 5 - - INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 6
B8 INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.LONG_V[1] bit 1 - INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1 - INT: mux CELL.IMUX_IO_OK[0] bit 1 - INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0] - - INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 5 - INT: mux CELL.IMUX_IO_IK[1] bit 4 - - INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 4 - INT: mux CELL.LONG_V[5] bit 0 INT: mux CELL.LONG_V[3] bit 1 INT: mux CELL.LONG_V[3] bit 0 - INT: mux CELL.LONG_IO_H[0] bit 1 - INT: mux CELL.LONG_V[4] bit 1 INT: mux CELL.LONG_V[4] bit 0 -
B5 INT: mux CELL.LONG_V[1] bit 2 - INT: mux CELL.LONG_V[1] bit 0 INT: mux CELL.LONG_V[2] bit 1 INT: mux CELL.LONG_V[2] bit 2 INT: mux CELL.LONG_V[2] bit 0 INT: mux CELL.LONG_V[0] bit 1 - INT: mux CELL.LONG_V[0] bit 0 INT: mux CELL.LONG_V[0] bit 2 INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_IO_SN_I1[0] INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[4] INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 5 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.LONG_V[5] bit 1 INT: mux CELL.LONG_V[5] bit 2 - INT: mux CELL.LONG_V[3] bit 2 INT: mux CELL.LONG_V[4] bit 2 INT: mux CELL.LONG_IO_H[3] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 0 - - -
B4 - INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_IO_H[3] INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_IO_H[2] - - - - INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 6 INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0] - INT: mux CELL.LONG_IO_H[3] bit 0 INT: mux CELL.LONG_IO_H[2] bit 0 INT: mux CELL.LONG_IO_H[2] bit 1 INT: mux CELL.LONG_IO_H[2] bit 2 - INT: mux CELL.LONG_IO_H[1] bit 1 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[1] INT: mux CELL.LONG_IO_H[0] bit 0 INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[0] IO[0]: DRIVE bit 0 IO[0]: _5V_TOLERANT IO[1]: _5V_TOLERANT - - - IO[0]: ! IFF_CE_ENABLE_NO_IQ - - - - - INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 6 INT: mux CELL.IMUX_IO_O1[1] bit 5
B3 INT: mux CELL.DBUF_IO_H[1] bit 1 INT: mux CELL.DBUF_IO_H[1] bit 2 INT: mux CELL.DBUF_IO_H[1] bit 3 INT: !bipass CELL.DOUBLE_IO_S0[3] = CELL.DOUBLE_IO_S2[3] INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_S1[3] INT: !bipass CELL.DOUBLE_IO_S0[2] = CELL.DOUBLE_IO_S2[2] INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 5 INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S1[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S1[1] INT: mux CELL.LONG_IO_H[1] bit 3 INT: mux CELL.LONG_IO_H[2] bit 3 - INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0] - IO[0]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I2 bit 0 IO[0]: ! READBACK_OQ bit 0 - - IO[0]: MUX_T bit 0 IO[1]: DRIVE bit 0 - IO[1]: MUX_T bit 0 - IO[1]: ! IFF_CE_ENABLE_NO_IQ - - - - - INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 4
B2 INT: !pass CELL.DOUBLE_IO_S2[0] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_S2[1] ← CELL.DBUF_IO_H[0] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S2[3] INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_S2[3] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S0[3] INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_S0[2] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S1[2] INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_S1[2] INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S0[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S0[1] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.DOUBLE_IO_S0[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S1[0] - IO[0]: ! READBACK_I2 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_OQ bit 0 - INT: mux CELL.LONG_IO_H[1] bit 2 IO[1]: ! IFF_CE_ENABLE IO[1]: ! OFF_CE_ENABLE INT: mux CELL.IMUX_IO_T[1] bit 5 INT: !pass CELL.DOUBLE_IO_S0[0] ← CELL.DBUF_IO_H[1] INT: !pass CELL.DOUBLE_IO_S0[1] ← CELL.DBUF_IO_H[1] INT: mux CELL.DBUF_IO_H[0] bit 2 INT: mux CELL.DBUF_IO_H[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 7 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 6 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 6 INT: mux CELL.IMUX_IO_T[1] bit 0
B1 INT: !pass CELL.DOUBLE_IO_S2[3] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_S2[2] ← CELL.DBUF_IO_H[0] INT: mux CELL.DBUF_IO_H[1] bit 0 INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_S0[3] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S1[3] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S2[2] INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_S2[2] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S0[2] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S2[1] INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S2[1] INT: !bipass CELL.DOUBLE_IO_S0[1] = CELL.DOUBLE_IO_S2[1] IO[0]: ! OFF_SRVAL bit 0 IO[0]: PULL bit 0 IO[0]: PULL bit 1 IO[0]: SYNC_D bit 0 IO[0]: IFF_D bit 0 IO[0]: ! IFF_CE_ENABLE INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S1[0] INT: mux CELL.LONG_IO_H[1] bit 0 IO[1]: IFF_D bit 1 IO[1]: MUX_I1 bit 0 IO[1]: IFF_D bit 0 IO[1]: PULL bit 1 IO[1]: PULL bit 0 IO[1]: ! OFF_SRVAL bit 0 INT: !pass CELL.DOUBLE_IO_S0[3] ← CELL.DBUF_IO_H[1] INT: !pass CELL.DOUBLE_IO_S0[2] ← CELL.DBUF_IO_H[1] INT: mux CELL.DBUF_IO_H[0] bit 0 INT: mux CELL.DBUF_IO_H[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 7
B0 - IO[0]: !invert T IO[0]: SLEW bit 0 IO[0]: !invert OK IO[0]: MUX_O bit 0 IO[0]: ! OFF_CE_ENABLE IO[0]: MUX_O bit 1 IO[0]: MUX_O bit 3 IO[0]: MUX_O bit 2 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_D_INV IO[0]: OFF_USED IO[0]: ! IFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 1 IO[0]: MUX_I2 bit 0 IO[0]: MUX_I1 bit 1 IO[0]: IFF_D bit 1 IO[0]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I2 bit 0 IO[1]: !invert IK IO[1]: ! IFF_SRVAL bit 0 IO[1]: SYNC_D bit 0 IO[1]: OFF_USED IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0 IO[1]: MUX_O bit 1 INT: mux CELL.IMUX_IO_T[0] bit 5 IO[1]: MUX_O bit 0 IO[1]: MUX_O bit 3 IO[1]: MUX_O bit 2 IO[1]: !invert OK IO[1]: SLEW bit 0 IO[1]: !invert T
spartanxl IO_S1_W rect MAIN_E
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_N0

Cells: 3

Switchbox INT

spartanxl IO_N0 switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[21][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[25][8]
CELL.LONG_H[2]CELL.SINGLE_V[3]!MAIN[24][1]
CELL.LONG_V[0]CELL.OUT_COUT_E!MAIN_W[5][0]
spartanxl IO_N0 switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I2_E1!MAIN[22][1]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[23][8]
CELL.SINGLE_V[1]CELL.LONG_IO_H[0]!MAIN[15][2]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I2[0]!MAIN[22][0]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[29][8]
CELL.SINGLE_V[2]CELL.LONG_IO_H[1]!MAIN[17][2]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I1[0]!MAIN[25][2]
CELL.SINGLE_V[3]CELL.LONG_H[2]!MAIN_S[28][9]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I1_E1!MAIN[29][2]
CELL.SINGLE_V[4]CELL.OUT_IO_SN_I2_E1!MAIN[35][0]
CELL.SINGLE_V[5]CELL.LONG_IO_H[2]!MAIN[33][2]
CELL.SINGLE_V[5]CELL.OUT_IO_SN_I2[0]!MAIN[32][0]
CELL.SINGLE_V[6]CELL.LONG_IO_H[3]!MAIN[34][2]
CELL.SINGLE_V[6]CELL.OUT_IO_SN_I1[0]!MAIN[25][1]
CELL.SINGLE_V[7]CELL.OUT_IO_SN_I1_E1!MAIN[32][2]
CELL.DOUBLE_V0[0]CELL.OUT_IO_SN_I1_E1!MAIN[21][3]
CELL.DOUBLE_V0[1]CELL.OUT_IO_SN_I2[0]!MAIN[31][0]
CELL.DOUBLE_V1[0]CELL.OUT_IO_SN_I1[0]!MAIN[20][3]
CELL.DOUBLE_V1[1]CELL.OUT_IO_SN_I2_E1!MAIN[30][0]
CELL.DOUBLE_IO_N0[0]CELL.DBUF_IO_H[0]!MAIN[35][4]
CELL.DOUBLE_IO_N0[1]CELL.DBUF_IO_H[0]!MAIN[34][4]
CELL.DOUBLE_IO_N0[2]CELL.DBUF_IO_H[0]!MAIN[34][5]
CELL.DOUBLE_IO_N0[3]CELL.DBUF_IO_H[0]!MAIN[35][5]
CELL.DOUBLE_IO_N2[0]CELL.DBUF_IO_H[1]!MAIN[10][4]
CELL.DOUBLE_IO_N2[1]CELL.DBUF_IO_H[1]!MAIN[9][4]
CELL.DOUBLE_IO_N2[2]CELL.DBUF_IO_H[1]!MAIN[9][5]
CELL.DOUBLE_IO_N2[3]CELL.DBUF_IO_H[1]!MAIN[10][5]
spartanxl IO_N0 switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_V[0]CELL.DOUBLE_IO_N0[0]!MAIN[24][4]
CELL.SINGLE_V[0]CELL.DOUBLE_IO_N2[0]!MAIN[22][4]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_N1[0]!MAIN[18][5]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_N0[1]!MAIN[26][5]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_N2[1]!MAIN[27][4]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_N1[1]!MAIN[25][3]
CELL.SINGLE_V[4]CELL.DOUBLE_IO_N0[2]!MAIN[29][5]
CELL.SINGLE_V[4]CELL.DOUBLE_IO_N2[2]!MAIN[30][4]
CELL.SINGLE_V[5]CELL.DOUBLE_IO_N1[2]!MAIN[28][4]
CELL.SINGLE_V[6]CELL.DOUBLE_IO_N0[3]!MAIN[32][4]
CELL.SINGLE_V[6]CELL.DOUBLE_IO_N2[3]!MAIN[32][5]
CELL.SINGLE_V[7]CELL.DOUBLE_IO_N1[3]!MAIN[31][3]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N0[1]!MAIN[27][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N1[1]!MAIN[24][3]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N2[1]!MAIN[26][4]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N0[2]!MAIN[30][5]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N1[2]!MAIN[29][4]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N2[2]!MAIN[28][5]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N0[0]!MAIN[25][4]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N1[0]!MAIN[20][4]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N2[0]!MAIN[21][4]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N0[3]!MAIN[33][4]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N1[3]!MAIN[31][5]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N2[3]!MAIN[31][4]
CELL.DOUBLE_IO_N0[0]CELL.DOUBLE_IO_N2[0]!MAIN[23][4]
CELL.DOUBLE_IO_N0[1]CELL.DOUBLE_IO_N2[1]!MAIN[25][5]
CELL.DOUBLE_IO_N0[2]CELL.DOUBLE_IO_N2[2]!MAIN[30][3]
CELL.DOUBLE_IO_N0[3]CELL.DOUBLE_IO_N2[3]!MAIN[32][3]
spartanxl IO_N0 switchbox INT muxes DBUF_IO_H[0]
BitsDestination
MAIN[7][4]MAIN[8][4]MAIN[7][5]MAIN[8][5]CELL.DBUF_IO_H[0]
Source
0011CELL.DOUBLE_IO_N2[0]
0101CELL.DOUBLE_IO_N2[2]
0110CELL.DOUBLE_IO_N2[3]
1111CELL.DOUBLE_IO_N2[1]
spartanxl IO_N0 switchbox INT muxes DBUF_IO_H[1]
BitsDestination
MAIN[33][3]MAIN[34][3]MAIN[35][3]MAIN[33][5]CELL.DBUF_IO_H[1]
Source
0011CELL.DOUBLE_IO_N0[1]
0101CELL.DOUBLE_IO_N0[2]
0110CELL.DOUBLE_IO_N0[3]
1111CELL.DOUBLE_IO_N0[0]
spartanxl IO_N0 switchbox INT muxes LONG_V[0]
BitsDestination
MAIN[26][1]MAIN[29][1]MAIN[27][1]CELL.LONG_V[0]
Source
000CELL.LONG_IO_H[0]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_N0 switchbox INT muxes LONG_V[1]
BitsDestination
MAIN[35][1]MAIN[34][0]MAIN[33][1]CELL.LONG_V[1]
Source
000CELL.LONG_IO_H[1]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_N0 switchbox INT muxes LONG_V[2]
BitsDestination
MAIN[31][1]MAIN[32][1]MAIN[30][1]CELL.LONG_V[2]
Source
000CELL.LONG_IO_H[2]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_N0 switchbox INT muxes LONG_V[3]
BitsDestination
MAIN[6][1]MAIN[7][0]MAIN[6][0]CELL.LONG_V[3]
Source
000CELL.LONG_IO_H[1]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_N0 switchbox INT muxes LONG_V[4]
BitsDestination
MAIN[5][1]MAIN[2][0]MAIN[1][0]CELL.LONG_V[4]
Source
000CELL.LONG_IO_H[2]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_N0 switchbox INT muxes LONG_V[5]
BitsDestination
MAIN[8][1]MAIN[9][1]MAIN[8][0]CELL.LONG_V[5]
Source
000CELL.LONG_IO_H[3]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_N0 switchbox INT muxes LONG_IO_H[0]
BitsDestination
MAIN[4][0]MAIN[16][2]CELL.LONG_IO_H[0]
Source
00CELL.LONG_V[0]
01CELL.SINGLE_V[1]
11off
spartanxl IO_N0 switchbox INT muxes LONG_IO_H[1]
BitsDestination
MAIN[23][3]MAIN[14][4]MAIN[18][2]MAIN[17][5]CELL.LONG_IO_H[1]
Source
0001CELL.LONG_V[1]
0010CELL.LONG_V[3]
0111CELL.SINGLE_V[2]
1111off
spartanxl IO_N0 switchbox INT muxes LONG_IO_H[2]
BitsDestination
MAIN[22][3]MAIN[20][2]MAIN[21][2]MAIN[22][2]CELL.LONG_IO_H[2]
Source
0001CELL.LONG_V[2]
0010CELL.LONG_V[4]
0111CELL.SINGLE_V[5]
1111off
spartanxl IO_N0 switchbox INT muxes LONG_IO_H[3]
BitsDestination
MAIN[4][1]MAIN[23][2]CELL.LONG_IO_H[3]
Source
00CELL.LONG_V[5]
01CELL.SINGLE_V[6]
11off
spartanxl IO_N0 switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[26][2]MAIN[26][3]MAIN[29][3]MAIN[28][2]MAIN[27][3]MAIN[28][3]MAIN[27][2]CELL.IMUX_IO_O1[0]
Source
0011111CELL.DOUBLE_V0[0]
0100110CELL.LONG_V[5]
0111011CELL.LONG_V[3]
0111101CELL.LONG_V[4]
1100111CELL.DOUBLE_V1[1]
1111111CELL.TIE_0
spartanxl IO_N0 switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[1][2]MAIN[0][2]MAIN[0][3]MAIN[1][3]MAIN[2][3]MAIN[2][2]MAIN[3][1]CELL.IMUX_IO_O1[1]
Source
0111101CELL.TIE_0
1011101CELL.LONG_IO_H[2]
1011110CELL_E.DOUBLE_V0[1]
1101101CELL_E.DOUBLE_V1[0]
1101110CELL_E.LONG_V[2]
1110101CELL_E.LONG_V[0]
1111001CELL_E.LONG_V[1]
spartanxl IO_N0 switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[23][1]MAIN[23][0]MAIN[24][0]MAIN[25][0]MAIN[28][0]MAIN[26][0]CELL.IMUX_IO_OK[0]
Source
001100CELL.GCLK[1]
001111CELL.SINGLE_V[3]
010100CELL.GCLK[2]
010111CELL.SINGLE_V[4]
011000CELL.GCLK[3]
011011CELL.SINGLE_V[5]
111100CELL.GCLK[0]
111111CELL.SINGLE_V[2]
spartanxl IO_N0 switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[11][0]MAIN[10][0]MAIN[10][1]MAIN[12][1]MAIN[11][1]MAIN[13][1]CELL.IMUX_IO_OK[1]
Source
000011CELL.GCLK[1]
000101CELL.GCLK[2]
000110CELL.GCLK[3]
001111CELL.GCLK[0]
110011CELL_E.SINGLE_V[2]
110101CELL_E.SINGLE_V[3]
110110CELL_E.SINGLE_V[5]
111111CELL_E.SINGLE_V[4]
spartanxl IO_N0 switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[18][1]MAIN[19][1]MAIN[20][1]MAIN[21][1]MAIN[19][0]MAIN[18][0]CELL.IMUX_IO_IK[0]
Source
001100CELL.GCLK[1]
001111CELL.SINGLE_V[2]
010100CELL.GCLK[2]
010111CELL.SINGLE_V[4]
011000CELL.GCLK[3]
011011CELL.SINGLE_V[5]
111100CELL.GCLK[0]
111111CELL.SINGLE_V[3]
spartanxl IO_N0 switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[16][0]MAIN[14][0]MAIN[14][1]MAIN[15][1]MAIN[16][1]MAIN[17][1]CELL.IMUX_IO_IK[1]
Source
000011CELL.GCLK[1]
000101CELL.GCLK[2]
000110CELL.GCLK[3]
001111CELL.GCLK[0]
110011CELL_E.SINGLE_V[2]
110101CELL_E.SINGLE_V[3]
110110CELL_E.SINGLE_V[4]
111111CELL_E.SINGLE_V[5]
spartanxl IO_N0 switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[5][4]MAIN[3][4]MAIN[6][6]MAIN[6][4]MAIN[4][4]MAIN[6][5]MAIN[5][5]MAIN[4][5]CELL.IMUX_IO_T[0]
Source
00011111CELL.TIE_0
00100111CELL.LONG_IO_H[3]
00101101CELL.LONG_IO_H[0]
00101110CELL.LONG_IO_H[2]
00111010CELL.GCLK[0]
01101111CELL.DOUBLE_IO_N1[0]
01111011CELL.DOUBLE_IO_N2[1]
10110111CELL.DOUBLE_IO_N1[1]
10111101CELL.LONG_IO_H[1]
11111111CELL.DOUBLE_IO_N2[0]
spartanxl IO_N0 switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[1][4]MAIN[0][5]MAIN[11][4]MAIN[3][5]MAIN[2][5]MAIN[2][4]MAIN[1][5]MAIN[0][4]CELL.IMUX_IO_T[1]
Source
00011111CELL.TIE_0
00100111CELL.GCLK[0]
00110011CELL.LONG_IO_H[0]
00111001CELL.LONG_IO_H[3]
00111010CELL.LONG_IO_H[2]
01101111CELL.DOUBLE_IO_N1[1]
01111011CELL.DOUBLE_IO_N2[1]
10110111CELL.DOUBLE_IO_N2[0]
10111101CELL.LONG_IO_H[1]
11111111CELL.DOUBLE_IO_N1[0]

Bels IO

spartanxl IO_N0 bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[22][6]CELL.IMUX_IO_IK[1] invert by !MAIN[13][6]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[32][6]CELL.IMUX_IO_OK[1] invert by !MAIN[2][6]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_F2_NCELL.IMUX_CLB_G2_N
TinCELL.IMUX_IO_T[0] invert by !MAIN[34][6]CELL.IMUX_IO_T[1] invert by !MAIN[0][6]
I1outCELL.OUT_IO_SN_I1[0]CELL.OUT_IO_SN_I1[1]
I2outCELL.OUT_IO_SN_I2[0]CELL.OUT_IO_SN_I2[1]
spartanxl IO_N0 bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[23][6]!MAIN[12][6]
OFF_SRVAL bit 0!MAIN[24][5]!MAIN[11][5]
READBACK_I1 bit 0!MAIN[18][3]!MAIN[17][4]
READBACK_I2 bit 0!MAIN[18][4]!MAIN[17][3]
READBACK_OQ bit 0!MAIN[16][3]!MAIN[16][4]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[25][6]!MAIN[9][6]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[24][6]MAIN[10][6]
IFF_CE_ENABLE!MAIN[19][5]!MAIN[13][4]
OFF_CE_ENABLE!MAIN[30][6]!MAIN[12][4]
SYNC_D[enum: IO_SYNC_D][enum: IO_SYNC_D]
IFF_CE_ENABLE_NO_IQ!MAIN[8][2]!MAIN[8][3]
MUX_T[enum: IO_MUX_T][enum: IO_MUX_T]
DRIVE[enum: IO_DRIVE][enum: IO_DRIVE]
_5V_TOLERANTMAIN[13][2]MAIN[12][2]
spartanxl IO_N0 enum IO_SLEW
IO[0].SLEWMAIN[33][6]
IO[1].SLEWMAIN[1][6]
FAST0
SLOW1
spartanxl IO_N0 enum IO_PULL
IO[0].PULLMAIN[22][5]MAIN[23][5]
IO[1].PULLMAIN[13][5]MAIN[12][5]
NONE11
PULLUP01
PULLDOWN10
spartanxl IO_N0 enum IO_MUX_I
IO[0].MUX_I1MAIN[19][6]MAIN[17][6]
IO[1].MUX_I1MAIN[16][6]MAIN[15][5]
IO[0].MUX_I2MAIN[21][6]MAIN[20][6]
IO[1].MUX_I2MAIN[15][6]MAIN[14][6]
I01
IQ11
IQL10
spartanxl IO_N0 enum IO_IFF_D
IO[0].IFF_DMAIN[18][6]MAIN[20][5]
IO[1].IFF_DMAIN[16][5]MAIN[14][5]
I11
DELAY00
MEDDELAY01
SYNC10
spartanxl IO_N0 enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[26][6]
IO[1].MUX_OFF_DMAIN[8][6]
O11
O20
spartanxl IO_N0 enum IO_MUX_O
IO[0].MUX_OMAIN[28][6]MAIN[27][6]MAIN[29][6]MAIN[31][6]
IO[1].MUX_OMAIN[4][6]MAIN[3][6]MAIN[7][6]MAIN[5][6]
O10000
O1_INV0001
O20111
O2_INV1111
OQ0010
MUX1011
spartanxl IO_N0 enum IO_SYNC_D
IO[0].SYNC_DMAIN[21][5]
IO[1].SYNC_DMAIN[11][6]
I1
DELAY0
spartanxl IO_N0 enum IO_MUX_T
IO[0].MUX_TMAIN[13][3]
IO[1].MUX_TMAIN[10][3]
T1
TQ0
spartanxl IO_N0 enum IO_DRIVE
IO[0].DRIVEMAIN[14][2]
IO[1].DRIVEMAIN[12][3]
_121
_240

Bels COUT

spartanxl IO_N0 bel COUT pins
PinDirectionCOUT
OoutCELL.OUT_COUT

Bel wires

spartanxl IO_N0 bel wires
WirePins
CELL.IMUX_CLB_F2_NIO[0].O2
CELL.IMUX_CLB_G2_NIO[1].O2
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_SN_I1[0]IO[0].I1
CELL.OUT_IO_SN_I1[1]IO[1].I1
CELL.OUT_IO_SN_I2[0]IO[0].I2
CELL.OUT_IO_SN_I2[1]IO[1].I2
CELL.OUT_COUTCOUT.O

Bitstream

spartanxl IO_N0 rect MAIN
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B6 - IO[0]: !invert T IO[0]: SLEW bit 0 IO[0]: !invert OK IO[0]: MUX_O bit 0 IO[0]: ! OFF_CE_ENABLE IO[0]: MUX_O bit 1 IO[0]: MUX_O bit 3 IO[0]: MUX_O bit 2 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_D_INV IO[0]: OFF_USED IO[0]: ! IFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 1 IO[0]: MUX_I2 bit 0 IO[0]: MUX_I1 bit 1 IO[0]: IFF_D bit 1 IO[0]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I2 bit 0 IO[1]: !invert IK IO[1]: ! IFF_SRVAL bit 0 IO[1]: SYNC_D bit 0 IO[1]: OFF_USED IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0 IO[1]: MUX_O bit 1 INT: mux CELL.IMUX_IO_T[0] bit 5 IO[1]: MUX_O bit 0 IO[1]: MUX_O bit 3 IO[1]: MUX_O bit 2 IO[1]: !invert OK IO[1]: SLEW bit 0 IO[1]: !invert T
B5 INT: !pass CELL.DOUBLE_IO_N0[3] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_N0[2] ← CELL.DBUF_IO_H[0] INT: mux CELL.DBUF_IO_H[1] bit 0 INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_N2[3] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N1[3] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N0[2] INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_N0[2] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N2[2] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N0[1] INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N0[1] INT: !bipass CELL.DOUBLE_IO_N0[1] = CELL.DOUBLE_IO_N2[1] IO[0]: ! OFF_SRVAL bit 0 IO[0]: PULL bit 0 IO[0]: PULL bit 1 IO[0]: SYNC_D bit 0 IO[0]: IFF_D bit 0 IO[0]: ! IFF_CE_ENABLE INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N1[0] INT: mux CELL.LONG_IO_H[1] bit 0 IO[1]: IFF_D bit 1 IO[1]: MUX_I1 bit 0 IO[1]: IFF_D bit 0 IO[1]: PULL bit 1 IO[1]: PULL bit 0 IO[1]: ! OFF_SRVAL bit 0 INT: !pass CELL.DOUBLE_IO_N2[3] ← CELL.DBUF_IO_H[1] INT: !pass CELL.DOUBLE_IO_N2[2] ← CELL.DBUF_IO_H[1] INT: mux CELL.DBUF_IO_H[0] bit 0 INT: mux CELL.DBUF_IO_H[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 6
B4 INT: !pass CELL.DOUBLE_IO_N0[0] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_N0[1] ← CELL.DBUF_IO_H[0] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N0[3] INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_N0[3] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N2[3] INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_N2[2] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N1[2] INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_N1[2] INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N2[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N2[1] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.DOUBLE_IO_N0[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N1[0] - IO[0]: ! READBACK_I2 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_OQ bit 0 - INT: mux CELL.LONG_IO_H[1] bit 2 IO[1]: ! IFF_CE_ENABLE IO[1]: ! OFF_CE_ENABLE INT: mux CELL.IMUX_IO_T[1] bit 5 INT: !pass CELL.DOUBLE_IO_N2[0] ← CELL.DBUF_IO_H[1] INT: !pass CELL.DOUBLE_IO_N2[1] ← CELL.DBUF_IO_H[1] INT: mux CELL.DBUF_IO_H[0] bit 2 INT: mux CELL.DBUF_IO_H[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 7 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 6 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 7 INT: mux CELL.IMUX_IO_T[1] bit 0
B3 INT: mux CELL.DBUF_IO_H[1] bit 1 INT: mux CELL.DBUF_IO_H[1] bit 2 INT: mux CELL.DBUF_IO_H[1] bit 3 INT: !bipass CELL.DOUBLE_IO_N0[3] = CELL.DOUBLE_IO_N2[3] INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_N1[3] INT: !bipass CELL.DOUBLE_IO_N0[2] = CELL.DOUBLE_IO_N2[2] INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 5 INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N1[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N1[1] INT: mux CELL.LONG_IO_H[1] bit 3 INT: mux CELL.LONG_IO_H[2] bit 3 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0] - IO[0]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I2 bit 0 IO[0]: ! READBACK_OQ bit 0 - - IO[0]: MUX_T bit 0 IO[1]: DRIVE bit 0 - IO[1]: MUX_T bit 0 - IO[1]: ! IFF_CE_ENABLE_NO_IQ - - - - - INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 4
B2 - INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_IO_H[3] INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_IO_H[2] INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_IO_SN_I1_E1 - - INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 6 INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0] - INT: mux CELL.LONG_IO_H[3] bit 0 INT: mux CELL.LONG_IO_H[2] bit 0 INT: mux CELL.LONG_IO_H[2] bit 1 INT: mux CELL.LONG_IO_H[2] bit 2 - INT: mux CELL.LONG_IO_H[1] bit 1 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[1] INT: mux CELL.LONG_IO_H[0] bit 0 INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[0] IO[0]: DRIVE bit 0 IO[0]: _5V_TOLERANT IO[1]: _5V_TOLERANT - - - IO[0]: ! IFF_CE_ENABLE_NO_IQ - - - - - INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 6 INT: mux CELL.IMUX_IO_O1[1] bit 5
B1 INT: mux CELL.LONG_V[1] bit 2 - INT: mux CELL.LONG_V[1] bit 0 INT: mux CELL.LONG_V[2] bit 1 INT: mux CELL.LONG_V[2] bit 2 INT: mux CELL.LONG_V[2] bit 0 INT: mux CELL.LONG_V[0] bit 1 - INT: mux CELL.LONG_V[0] bit 0 INT: mux CELL.LONG_V[0] bit 2 INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_IO_SN_I1[0] INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[3] INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 5 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.LONG_V[5] bit 1 INT: mux CELL.LONG_V[5] bit 2 - INT: mux CELL.LONG_V[3] bit 2 INT: mux CELL.LONG_V[4] bit 2 INT: mux CELL.LONG_IO_H[3] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 0 - - -
B0 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.LONG_V[1] bit 1 - INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1 - INT: mux CELL.IMUX_IO_OK[0] bit 1 - INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0] - - INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 5 - INT: mux CELL.IMUX_IO_IK[1] bit 4 - - INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 4 - INT: mux CELL.LONG_V[5] bit 0 INT: mux CELL.LONG_V[3] bit 1 INT: mux CELL.LONG_V[3] bit 0 - INT: mux CELL.LONG_IO_H[0] bit 1 - INT: mux CELL.LONG_V[4] bit 1 INT: mux CELL.LONG_V[4] bit 0 -
spartanxl IO_N0 rect MAIN_S
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
spartanxl IO_N0 rect MAIN_E
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
spartanxl IO_N0 rect MAIN_W
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: !buffer CELL.LONG_V[0] ← CELL.OUT_COUT_E - - - - -

Tile IO_N0_E

Cells: 3

Switchbox INT

spartanxl IO_N0_E switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[21][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[25][8]
CELL.LONG_H[2]CELL.SINGLE_V[3]!MAIN[24][1]
CELL.LONG_V[0]CELL.OUT_COUT_E!MAIN_W[5][0]
spartanxl IO_N0_E switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I2_E1!MAIN[22][1]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[23][8]
CELL.SINGLE_V[1]CELL.LONG_IO_H[0]!MAIN[15][2]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I2[0]!MAIN[22][0]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[29][8]
CELL.SINGLE_V[2]CELL.LONG_IO_H[1]!MAIN[17][2]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I1[0]!MAIN[25][2]
CELL.SINGLE_V[3]CELL.LONG_H[2]!MAIN_S[28][9]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I1_E1!MAIN[29][2]
CELL.SINGLE_V[4]CELL.OUT_IO_SN_I2_E1!MAIN[35][0]
CELL.SINGLE_V[5]CELL.LONG_IO_H[2]!MAIN[33][2]
CELL.SINGLE_V[5]CELL.OUT_IO_SN_I2[0]!MAIN[32][0]
CELL.SINGLE_V[6]CELL.LONG_IO_H[3]!MAIN[34][2]
CELL.SINGLE_V[6]CELL.OUT_IO_SN_I1[0]!MAIN[25][1]
CELL.SINGLE_V[7]CELL.OUT_IO_SN_I1_E1!MAIN[32][2]
CELL.DOUBLE_V0[0]CELL.OUT_IO_SN_I1_E1!MAIN[21][3]
CELL.DOUBLE_V0[1]CELL.OUT_IO_SN_I2[0]!MAIN[31][0]
CELL.DOUBLE_V1[0]CELL.OUT_IO_SN_I1[0]!MAIN[20][3]
CELL.DOUBLE_V1[1]CELL.OUT_IO_SN_I2_E1!MAIN[30][0]
CELL.DOUBLE_IO_N0[0]CELL.DBUF_IO_H[0]!MAIN[35][4]
CELL.DOUBLE_IO_N0[1]CELL.DBUF_IO_H[0]!MAIN[34][4]
CELL.DOUBLE_IO_N0[2]CELL.DBUF_IO_H[0]!MAIN[34][5]
CELL.DOUBLE_IO_N0[3]CELL.DBUF_IO_H[0]!MAIN[35][5]
CELL.DOUBLE_IO_N2[0]CELL.DBUF_IO_H[1]!MAIN[10][4]
CELL.DOUBLE_IO_N2[1]CELL.DBUF_IO_H[1]!MAIN[9][4]
CELL.DOUBLE_IO_N2[2]CELL.DBUF_IO_H[1]!MAIN[9][5]
CELL.DOUBLE_IO_N2[3]CELL.DBUF_IO_H[1]!MAIN[10][5]
spartanxl IO_N0_E switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_V[0]CELL.DOUBLE_IO_N0[0]!MAIN[24][4]
CELL.SINGLE_V[0]CELL.DOUBLE_IO_N2[0]!MAIN[22][4]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_N1[0]!MAIN[18][5]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_N0[1]!MAIN[26][5]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_N2[1]!MAIN[27][4]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_N1[1]!MAIN[25][3]
CELL.SINGLE_V[4]CELL.DOUBLE_IO_N0[2]!MAIN[29][5]
CELL.SINGLE_V[4]CELL.DOUBLE_IO_N2[2]!MAIN[30][4]
CELL.SINGLE_V[5]CELL.DOUBLE_IO_N1[2]!MAIN[28][4]
CELL.SINGLE_V[6]CELL.DOUBLE_IO_N0[3]!MAIN[32][4]
CELL.SINGLE_V[6]CELL.DOUBLE_IO_N2[3]!MAIN[32][5]
CELL.SINGLE_V[7]CELL.DOUBLE_IO_N1[3]!MAIN[31][3]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N0[1]!MAIN[27][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N1[1]!MAIN[24][3]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N2[1]!MAIN[26][4]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N0[2]!MAIN[30][5]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N1[2]!MAIN[29][4]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N2[2]!MAIN[28][5]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N0[0]!MAIN[25][4]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N1[0]!MAIN[20][4]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N2[0]!MAIN[21][4]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N0[3]!MAIN[33][4]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N1[3]!MAIN[31][5]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N2[3]!MAIN[31][4]
CELL.DOUBLE_IO_N0[0]CELL.DOUBLE_IO_N2[0]!MAIN[23][4]
CELL.DOUBLE_IO_N0[1]CELL.DOUBLE_IO_N2[1]!MAIN[25][5]
CELL.DOUBLE_IO_N0[2]CELL.DOUBLE_IO_N2[2]!MAIN[30][3]
CELL.DOUBLE_IO_N0[3]CELL.DOUBLE_IO_N2[3]!MAIN[32][3]
spartanxl IO_N0_E switchbox INT muxes DBUF_IO_H[0]
BitsDestination
MAIN[7][4]MAIN[8][4]MAIN[7][5]MAIN[8][5]CELL.DBUF_IO_H[0]
Source
0011CELL.DOUBLE_IO_N2[0]
0101CELL.DOUBLE_IO_N2[2]
0110CELL.DOUBLE_IO_N2[3]
1111CELL.DOUBLE_IO_N2[1]
spartanxl IO_N0_E switchbox INT muxes DBUF_IO_H[1]
BitsDestination
MAIN[33][3]MAIN[34][3]MAIN[35][3]MAIN[33][5]CELL.DBUF_IO_H[1]
Source
0011CELL.DOUBLE_IO_N0[1]
0101CELL.DOUBLE_IO_N0[2]
0110CELL.DOUBLE_IO_N0[3]
1111CELL.DOUBLE_IO_N0[0]
spartanxl IO_N0_E switchbox INT muxes LONG_V[0]
BitsDestination
MAIN[26][1]MAIN[29][1]MAIN[27][1]CELL.LONG_V[0]
Source
000CELL.LONG_IO_H[0]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_N0_E switchbox INT muxes LONG_V[1]
BitsDestination
MAIN[35][1]MAIN[34][0]MAIN[33][1]CELL.LONG_V[1]
Source
000CELL.LONG_IO_H[1]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_N0_E switchbox INT muxes LONG_V[2]
BitsDestination
MAIN[31][1]MAIN[32][1]MAIN[30][1]CELL.LONG_V[2]
Source
000CELL.LONG_IO_H[2]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_N0_E switchbox INT muxes LONG_V[3]
BitsDestination
MAIN[6][1]MAIN[7][0]MAIN[6][0]CELL.LONG_V[3]
Source
000CELL.LONG_IO_H[1]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_N0_E switchbox INT muxes LONG_V[4]
BitsDestination
MAIN[5][1]MAIN[2][0]MAIN[1][0]CELL.LONG_V[4]
Source
000CELL.LONG_IO_H[2]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_N0_E switchbox INT muxes LONG_V[5]
BitsDestination
MAIN[8][1]MAIN[9][1]MAIN[8][0]CELL.LONG_V[5]
Source
000CELL.LONG_IO_H[3]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_N0_E switchbox INT muxes LONG_IO_H[0]
BitsDestination
MAIN[4][0]MAIN[16][2]CELL.LONG_IO_H[0]
Source
00CELL.LONG_V[0]
01CELL.SINGLE_V[1]
11off
spartanxl IO_N0_E switchbox INT muxes LONG_IO_H[1]
BitsDestination
MAIN[23][3]MAIN[14][4]MAIN[18][2]MAIN[17][5]CELL.LONG_IO_H[1]
Source
0001CELL.LONG_V[1]
0010CELL.LONG_V[3]
0111CELL.SINGLE_V[2]
1111off
spartanxl IO_N0_E switchbox INT muxes LONG_IO_H[2]
BitsDestination
MAIN[22][3]MAIN[20][2]MAIN[21][2]MAIN[22][2]CELL.LONG_IO_H[2]
Source
0001CELL.LONG_V[2]
0010CELL.LONG_V[4]
0111CELL.SINGLE_V[5]
1111off
spartanxl IO_N0_E switchbox INT muxes LONG_IO_H[3]
BitsDestination
MAIN[4][1]MAIN[23][2]CELL.LONG_IO_H[3]
Source
00CELL.LONG_V[5]
01CELL.SINGLE_V[6]
11off
spartanxl IO_N0_E switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[26][2]MAIN[26][3]MAIN[29][3]MAIN[28][2]MAIN[27][3]MAIN[28][3]MAIN[27][2]CELL.IMUX_IO_O1[0]
Source
0011111CELL.DOUBLE_V0[0]
0100110CELL.LONG_V[5]
0111011CELL.LONG_V[3]
0111101CELL.LONG_V[4]
1100111CELL.DOUBLE_V1[1]
1111111CELL.TIE_0
spartanxl IO_N0_E switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[1][2]MAIN[0][2]MAIN[0][3]MAIN[1][3]MAIN[2][3]MAIN[2][2]MAIN[3][1]CELL.IMUX_IO_O1[1]
Source
0111101CELL.TIE_0
1011101CELL.LONG_IO_H[2]
1011110CELL_E.DOUBLE_V0[1]
1101101CELL_E.DOUBLE_V1[0]
1101110CELL_E.LONG_V[2]
1110101CELL_E.LONG_V[0]
1111001CELL_E.LONG_V[1]
spartanxl IO_N0_E switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[23][1]MAIN[23][0]MAIN[24][0]MAIN[25][0]MAIN[28][0]MAIN[26][0]CELL.IMUX_IO_OK[0]
Source
001100CELL.GCLK[1]
001111CELL.SINGLE_V[3]
010100CELL.GCLK[2]
010111CELL.SINGLE_V[4]
011000CELL.GCLK[3]
011011CELL.SINGLE_V[5]
111100CELL.GCLK[0]
111111CELL.SINGLE_V[2]
spartanxl IO_N0_E switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[11][0]MAIN[10][0]MAIN[10][1]MAIN[12][1]MAIN[11][1]MAIN[13][1]CELL.IMUX_IO_OK[1]
Source
000011CELL.GCLK[1]
000101CELL.GCLK[2]
000110CELL.GCLK[3]
001111CELL.GCLK[0]
110011CELL_E.SINGLE_V[2]
110101CELL_E.SINGLE_V[3]
110110CELL_E.SINGLE_V[5]
111111CELL_E.SINGLE_V[4]
spartanxl IO_N0_E switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[18][1]MAIN[19][1]MAIN[20][1]MAIN[21][1]MAIN[19][0]MAIN[18][0]CELL.IMUX_IO_IK[0]
Source
001100CELL.GCLK[1]
001111CELL.SINGLE_V[2]
010100CELL.GCLK[2]
010111CELL.SINGLE_V[4]
011000CELL.GCLK[3]
011011CELL.SINGLE_V[5]
111100CELL.GCLK[0]
111111CELL.SINGLE_V[3]
spartanxl IO_N0_E switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[16][0]MAIN[14][0]MAIN[14][1]MAIN[15][1]MAIN[16][1]MAIN[17][1]CELL.IMUX_IO_IK[1]
Source
000011CELL.GCLK[1]
000101CELL.GCLK[2]
000110CELL.GCLK[3]
001111CELL.GCLK[0]
110011CELL_E.SINGLE_V[2]
110101CELL_E.SINGLE_V[3]
110110CELL_E.SINGLE_V[4]
111111CELL_E.SINGLE_V[5]
spartanxl IO_N0_E switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[5][4]MAIN[3][4]MAIN[6][6]MAIN[6][4]MAIN[4][4]MAIN[6][5]MAIN[5][5]MAIN[4][5]CELL.IMUX_IO_T[0]
Source
00011111CELL.TIE_0
00100111CELL.LONG_IO_H[3]
00101101CELL.LONG_IO_H[0]
00101110CELL.LONG_IO_H[2]
00111010CELL.GCLK[0]
01101111CELL.DOUBLE_IO_N1[0]
01111011CELL.DOUBLE_IO_N2[1]
10110111CELL.DOUBLE_IO_N1[1]
10111101CELL.LONG_IO_H[1]
11111111CELL.DOUBLE_IO_N2[0]
spartanxl IO_N0_E switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[1][4]MAIN[0][5]MAIN[11][4]MAIN[3][5]MAIN[2][5]MAIN[2][4]MAIN[1][5]MAIN[0][4]CELL.IMUX_IO_T[1]
Source
00011111CELL.TIE_0
00100111CELL.GCLK[0]
00110011CELL.LONG_IO_H[0]
00111001CELL.LONG_IO_H[3]
00111010CELL.LONG_IO_H[2]
01101111CELL.DOUBLE_IO_N1[1]
01111011CELL.DOUBLE_IO_N2[1]
10110111CELL.DOUBLE_IO_N2[0]
10111101CELL.LONG_IO_H[1]
11111111CELL.DOUBLE_IO_N1[0]

Bels IO

spartanxl IO_N0_E bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[22][6]CELL.IMUX_IO_IK[1] invert by !MAIN[13][6]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[32][6]CELL.IMUX_IO_OK[1] invert by !MAIN[2][6]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_F2_NCELL.IMUX_CLB_G2_N
TinCELL.IMUX_IO_T[0] invert by !MAIN[34][6]CELL.IMUX_IO_T[1] invert by !MAIN[0][6]
I1outCELL.OUT_IO_SN_I1[0]CELL.OUT_IO_SN_I1[1]
I2outCELL.OUT_IO_SN_I2[0]CELL.OUT_IO_SN_I2[1]
CLKINoutCELL.OUT_IO_CLKIN-
spartanxl IO_N0_E bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[23][6]!MAIN[12][6]
OFF_SRVAL bit 0!MAIN[24][5]!MAIN[11][5]
READBACK_I1 bit 0!MAIN[18][3]!MAIN[17][4]
READBACK_I2 bit 0!MAIN[18][4]!MAIN[17][3]
READBACK_OQ bit 0!MAIN[16][3]!MAIN[16][4]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[25][6]!MAIN[9][6]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[24][6]MAIN[10][6]
IFF_CE_ENABLE!MAIN[19][5]!MAIN[13][4]
OFF_CE_ENABLE!MAIN[30][6]!MAIN[12][4]
SYNC_D[enum: IO_SYNC_D][enum: IO_SYNC_D]
IFF_CE_ENABLE_NO_IQ!MAIN[8][2]!MAIN[8][3]
MUX_T[enum: IO_MUX_T][enum: IO_MUX_T]
DRIVE[enum: IO_DRIVE][enum: IO_DRIVE]
_5V_TOLERANTMAIN[13][2]MAIN[12][2]
spartanxl IO_N0_E enum IO_SLEW
IO[0].SLEWMAIN[33][6]
IO[1].SLEWMAIN[1][6]
FAST0
SLOW1
spartanxl IO_N0_E enum IO_PULL
IO[0].PULLMAIN[22][5]MAIN[23][5]
IO[1].PULLMAIN[13][5]MAIN[12][5]
NONE11
PULLUP01
PULLDOWN10
spartanxl IO_N0_E enum IO_MUX_I
IO[0].MUX_I1MAIN[19][6]MAIN[17][6]
IO[1].MUX_I1MAIN[16][6]MAIN[15][5]
IO[0].MUX_I2MAIN[21][6]MAIN[20][6]
IO[1].MUX_I2MAIN[15][6]MAIN[14][6]
I01
IQ11
IQL10
spartanxl IO_N0_E enum IO_IFF_D
IO[0].IFF_DMAIN[18][6]MAIN[20][5]
IO[1].IFF_DMAIN[16][5]MAIN[14][5]
I11
DELAY00
MEDDELAY01
SYNC10
spartanxl IO_N0_E enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[26][6]
IO[1].MUX_OFF_DMAIN[8][6]
O11
O20
spartanxl IO_N0_E enum IO_MUX_O
IO[0].MUX_OMAIN[28][6]MAIN[27][6]MAIN[29][6]MAIN[31][6]
IO[1].MUX_OMAIN[4][6]MAIN[3][6]MAIN[7][6]MAIN[5][6]
O10000
O1_INV0001
O20111
O2_INV1111
OQ0010
MUX1011
spartanxl IO_N0_E enum IO_SYNC_D
IO[0].SYNC_DMAIN[21][5]
IO[1].SYNC_DMAIN[11][6]
I1
DELAY0
spartanxl IO_N0_E enum IO_MUX_T
IO[0].MUX_TMAIN[13][3]
IO[1].MUX_TMAIN[10][3]
T1
TQ0
spartanxl IO_N0_E enum IO_DRIVE
IO[0].DRIVEMAIN[14][2]
IO[1].DRIVEMAIN[12][3]
_121
_240

Bels COUT

spartanxl IO_N0_E bel COUT pins
PinDirectionCOUT
OoutCELL.OUT_COUT

Bel wires

spartanxl IO_N0_E bel wires
WirePins
CELL.IMUX_CLB_F2_NIO[0].O2
CELL.IMUX_CLB_G2_NIO[1].O2
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_SN_I1[0]IO[0].I1
CELL.OUT_IO_SN_I1[1]IO[1].I1
CELL.OUT_IO_SN_I2[0]IO[0].I2
CELL.OUT_IO_SN_I2[1]IO[1].I2
CELL.OUT_IO_CLKINIO[0].CLKIN
CELL.OUT_COUTCOUT.O

Bitstream

spartanxl IO_N0_E rect MAIN
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B6 - IO[0]: !invert T IO[0]: SLEW bit 0 IO[0]: !invert OK IO[0]: MUX_O bit 0 IO[0]: ! OFF_CE_ENABLE IO[0]: MUX_O bit 1 IO[0]: MUX_O bit 3 IO[0]: MUX_O bit 2 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_D_INV IO[0]: OFF_USED IO[0]: ! IFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 1 IO[0]: MUX_I2 bit 0 IO[0]: MUX_I1 bit 1 IO[0]: IFF_D bit 1 IO[0]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I2 bit 0 IO[1]: !invert IK IO[1]: ! IFF_SRVAL bit 0 IO[1]: SYNC_D bit 0 IO[1]: OFF_USED IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0 IO[1]: MUX_O bit 1 INT: mux CELL.IMUX_IO_T[0] bit 5 IO[1]: MUX_O bit 0 IO[1]: MUX_O bit 3 IO[1]: MUX_O bit 2 IO[1]: !invert OK IO[1]: SLEW bit 0 IO[1]: !invert T
B5 INT: !pass CELL.DOUBLE_IO_N0[3] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_N0[2] ← CELL.DBUF_IO_H[0] INT: mux CELL.DBUF_IO_H[1] bit 0 INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_N2[3] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N1[3] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N0[2] INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_N0[2] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N2[2] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N0[1] INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N0[1] INT: !bipass CELL.DOUBLE_IO_N0[1] = CELL.DOUBLE_IO_N2[1] IO[0]: ! OFF_SRVAL bit 0 IO[0]: PULL bit 0 IO[0]: PULL bit 1 IO[0]: SYNC_D bit 0 IO[0]: IFF_D bit 0 IO[0]: ! IFF_CE_ENABLE INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N1[0] INT: mux CELL.LONG_IO_H[1] bit 0 IO[1]: IFF_D bit 1 IO[1]: MUX_I1 bit 0 IO[1]: IFF_D bit 0 IO[1]: PULL bit 1 IO[1]: PULL bit 0 IO[1]: ! OFF_SRVAL bit 0 INT: !pass CELL.DOUBLE_IO_N2[3] ← CELL.DBUF_IO_H[1] INT: !pass CELL.DOUBLE_IO_N2[2] ← CELL.DBUF_IO_H[1] INT: mux CELL.DBUF_IO_H[0] bit 0 INT: mux CELL.DBUF_IO_H[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 6
B4 INT: !pass CELL.DOUBLE_IO_N0[0] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_N0[1] ← CELL.DBUF_IO_H[0] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N0[3] INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_N0[3] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N2[3] INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_N2[2] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N1[2] INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_N1[2] INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N2[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N2[1] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.DOUBLE_IO_N0[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N1[0] - IO[0]: ! READBACK_I2 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_OQ bit 0 - INT: mux CELL.LONG_IO_H[1] bit 2 IO[1]: ! IFF_CE_ENABLE IO[1]: ! OFF_CE_ENABLE INT: mux CELL.IMUX_IO_T[1] bit 5 INT: !pass CELL.DOUBLE_IO_N2[0] ← CELL.DBUF_IO_H[1] INT: !pass CELL.DOUBLE_IO_N2[1] ← CELL.DBUF_IO_H[1] INT: mux CELL.DBUF_IO_H[0] bit 2 INT: mux CELL.DBUF_IO_H[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 7 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 6 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 7 INT: mux CELL.IMUX_IO_T[1] bit 0
B3 INT: mux CELL.DBUF_IO_H[1] bit 1 INT: mux CELL.DBUF_IO_H[1] bit 2 INT: mux CELL.DBUF_IO_H[1] bit 3 INT: !bipass CELL.DOUBLE_IO_N0[3] = CELL.DOUBLE_IO_N2[3] INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_N1[3] INT: !bipass CELL.DOUBLE_IO_N0[2] = CELL.DOUBLE_IO_N2[2] INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 5 INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N1[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N1[1] INT: mux CELL.LONG_IO_H[1] bit 3 INT: mux CELL.LONG_IO_H[2] bit 3 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0] - IO[0]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I2 bit 0 IO[0]: ! READBACK_OQ bit 0 - - IO[0]: MUX_T bit 0 IO[1]: DRIVE bit 0 - IO[1]: MUX_T bit 0 - IO[1]: ! IFF_CE_ENABLE_NO_IQ - - - - - INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 4
B2 - INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_IO_H[3] INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_IO_H[2] INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_IO_SN_I1_E1 - - INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 6 INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0] - INT: mux CELL.LONG_IO_H[3] bit 0 INT: mux CELL.LONG_IO_H[2] bit 0 INT: mux CELL.LONG_IO_H[2] bit 1 INT: mux CELL.LONG_IO_H[2] bit 2 - INT: mux CELL.LONG_IO_H[1] bit 1 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[1] INT: mux CELL.LONG_IO_H[0] bit 0 INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[0] IO[0]: DRIVE bit 0 IO[0]: _5V_TOLERANT IO[1]: _5V_TOLERANT - - - IO[0]: ! IFF_CE_ENABLE_NO_IQ - - - - - INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 6 INT: mux CELL.IMUX_IO_O1[1] bit 5
B1 INT: mux CELL.LONG_V[1] bit 2 - INT: mux CELL.LONG_V[1] bit 0 INT: mux CELL.LONG_V[2] bit 1 INT: mux CELL.LONG_V[2] bit 2 INT: mux CELL.LONG_V[2] bit 0 INT: mux CELL.LONG_V[0] bit 1 - INT: mux CELL.LONG_V[0] bit 0 INT: mux CELL.LONG_V[0] bit 2 INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_IO_SN_I1[0] INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[3] INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 5 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.LONG_V[5] bit 1 INT: mux CELL.LONG_V[5] bit 2 - INT: mux CELL.LONG_V[3] bit 2 INT: mux CELL.LONG_V[4] bit 2 INT: mux CELL.LONG_IO_H[3] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 0 - - -
B0 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.LONG_V[1] bit 1 - INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1 - INT: mux CELL.IMUX_IO_OK[0] bit 1 - INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0] - - INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 5 - INT: mux CELL.IMUX_IO_IK[1] bit 4 - - INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 4 - INT: mux CELL.LONG_V[5] bit 0 INT: mux CELL.LONG_V[3] bit 1 INT: mux CELL.LONG_V[3] bit 0 - INT: mux CELL.LONG_IO_H[0] bit 1 - INT: mux CELL.LONG_V[4] bit 1 INT: mux CELL.LONG_V[4] bit 0 -
spartanxl IO_N0_E rect MAIN_S
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
spartanxl IO_N0_E rect MAIN_E
BitFrame
F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
spartanxl IO_N0_E rect MAIN_W
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: !buffer CELL.LONG_V[0] ← CELL.OUT_COUT_E - - - - -

Tile IO_N1

Cells: 3

Switchbox INT

spartanxl IO_N1 switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[21][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[25][8]
CELL.LONG_H[2]CELL.SINGLE_V[3]!MAIN[24][1]
CELL.LONG_V[0]CELL.OUT_COUT_E!MAIN_W[5][0]
spartanxl IO_N1 switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I2_E1!MAIN[22][1]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[23][8]
CELL.SINGLE_V[1]CELL.LONG_IO_H[0]!MAIN[15][2]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I2[0]!MAIN[22][0]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[29][8]
CELL.SINGLE_V[2]CELL.LONG_IO_H[1]!MAIN[17][2]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I1[0]!MAIN[25][2]
CELL.SINGLE_V[3]CELL.LONG_H[2]!MAIN_S[28][9]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I1_E1!MAIN[29][2]
CELL.SINGLE_V[4]CELL.OUT_IO_SN_I2_E1!MAIN[35][0]
CELL.SINGLE_V[5]CELL.LONG_IO_H[2]!MAIN[33][2]
CELL.SINGLE_V[5]CELL.OUT_IO_SN_I2[0]!MAIN[32][0]
CELL.SINGLE_V[6]CELL.LONG_IO_H[3]!MAIN[34][2]
CELL.SINGLE_V[6]CELL.OUT_IO_SN_I1[0]!MAIN[25][1]
CELL.SINGLE_V[7]CELL.OUT_IO_SN_I1_E1!MAIN[32][2]
CELL.DOUBLE_V0[0]CELL.OUT_IO_SN_I1_E1!MAIN[21][3]
CELL.DOUBLE_V0[1]CELL.OUT_IO_SN_I2[0]!MAIN[31][0]
CELL.DOUBLE_V1[0]CELL.OUT_IO_SN_I1[0]!MAIN[20][3]
CELL.DOUBLE_V1[1]CELL.OUT_IO_SN_I2_E1!MAIN[30][0]
CELL.DOUBLE_IO_N0[0]CELL.DBUF_IO_H[0]!MAIN[35][4]
CELL.DOUBLE_IO_N0[1]CELL.DBUF_IO_H[0]!MAIN[34][4]
CELL.DOUBLE_IO_N0[2]CELL.DBUF_IO_H[0]!MAIN[34][5]
CELL.DOUBLE_IO_N0[3]CELL.DBUF_IO_H[0]!MAIN[35][5]
CELL.DOUBLE_IO_N2[0]CELL.DBUF_IO_H[1]!MAIN[10][4]
CELL.DOUBLE_IO_N2[1]CELL.DBUF_IO_H[1]!MAIN[9][4]
CELL.DOUBLE_IO_N2[2]CELL.DBUF_IO_H[1]!MAIN[9][5]
CELL.DOUBLE_IO_N2[3]CELL.DBUF_IO_H[1]!MAIN[10][5]
spartanxl IO_N1 switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_V[0]CELL.DOUBLE_IO_N1[0]!MAIN[18][5]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_N0[0]!MAIN[24][4]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_N2[0]!MAIN[22][4]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_N1[1]!MAIN[25][3]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_N0[1]!MAIN[26][5]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_N2[1]!MAIN[27][4]
CELL.SINGLE_V[4]CELL.DOUBLE_IO_N1[2]!MAIN[28][4]
CELL.SINGLE_V[5]CELL.DOUBLE_IO_N0[2]!MAIN[29][5]
CELL.SINGLE_V[5]CELL.DOUBLE_IO_N2[2]!MAIN[30][4]
CELL.SINGLE_V[6]CELL.DOUBLE_IO_N1[3]!MAIN[31][3]
CELL.SINGLE_V[7]CELL.DOUBLE_IO_N0[3]!MAIN[32][4]
CELL.SINGLE_V[7]CELL.DOUBLE_IO_N2[3]!MAIN[32][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N0[1]!MAIN[27][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N1[1]!MAIN[24][3]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N2[1]!MAIN[26][4]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N0[2]!MAIN[30][5]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N1[2]!MAIN[29][4]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N2[2]!MAIN[28][5]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N0[0]!MAIN[25][4]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N1[0]!MAIN[20][4]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N2[0]!MAIN[21][4]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N0[3]!MAIN[33][4]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N1[3]!MAIN[31][5]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N2[3]!MAIN[31][4]
CELL.DOUBLE_IO_N0[0]CELL.DOUBLE_IO_N2[0]!MAIN[23][4]
CELL.DOUBLE_IO_N0[1]CELL.DOUBLE_IO_N2[1]!MAIN[25][5]
CELL.DOUBLE_IO_N0[2]CELL.DOUBLE_IO_N2[2]!MAIN[30][3]
CELL.DOUBLE_IO_N0[3]CELL.DOUBLE_IO_N2[3]!MAIN[32][3]
spartanxl IO_N1 switchbox INT muxes DBUF_IO_H[0]
BitsDestination
MAIN[7][4]MAIN[8][4]MAIN[7][5]MAIN[8][5]CELL.DBUF_IO_H[0]
Source
0011CELL.DOUBLE_IO_N2[0]
0101CELL.DOUBLE_IO_N2[2]
0110CELL.DOUBLE_IO_N2[3]
1111CELL.DOUBLE_IO_N2[1]
spartanxl IO_N1 switchbox INT muxes DBUF_IO_H[1]
BitsDestination
MAIN[33][3]MAIN[34][3]MAIN[35][3]MAIN[33][5]CELL.DBUF_IO_H[1]
Source
0011CELL.DOUBLE_IO_N0[1]
0101CELL.DOUBLE_IO_N0[2]
0110CELL.DOUBLE_IO_N0[3]
1111CELL.DOUBLE_IO_N0[0]
spartanxl IO_N1 switchbox INT muxes LONG_V[0]
BitsDestination
MAIN[26][1]MAIN[29][1]MAIN[27][1]CELL.LONG_V[0]
Source
000CELL.LONG_IO_H[0]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_N1 switchbox INT muxes LONG_V[1]
BitsDestination
MAIN[35][1]MAIN[34][0]MAIN[33][1]CELL.LONG_V[1]
Source
000CELL.LONG_IO_H[1]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_N1 switchbox INT muxes LONG_V[2]
BitsDestination
MAIN[31][1]MAIN[32][1]MAIN[30][1]CELL.LONG_V[2]
Source
000CELL.LONG_IO_H[2]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_N1 switchbox INT muxes LONG_V[3]
BitsDestination
MAIN[6][1]MAIN[7][0]MAIN[6][0]CELL.LONG_V[3]
Source
000CELL.LONG_IO_H[1]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_N1 switchbox INT muxes LONG_V[4]
BitsDestination
MAIN[5][1]MAIN[2][0]MAIN[1][0]CELL.LONG_V[4]
Source
000CELL.LONG_IO_H[2]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_N1 switchbox INT muxes LONG_V[5]
BitsDestination
MAIN[8][1]MAIN[9][1]MAIN[8][0]CELL.LONG_V[5]
Source
000CELL.LONG_IO_H[3]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_N1 switchbox INT muxes LONG_IO_H[0]
BitsDestination
MAIN[4][0]MAIN[16][2]CELL.LONG_IO_H[0]
Source
00CELL.LONG_V[0]
01CELL.SINGLE_V[1]
11off
spartanxl IO_N1 switchbox INT muxes LONG_IO_H[1]
BitsDestination
MAIN[23][3]MAIN[14][4]MAIN[18][2]MAIN[17][5]CELL.LONG_IO_H[1]
Source
0001CELL.LONG_V[1]
0010CELL.LONG_V[3]
0111CELL.SINGLE_V[2]
1111off
spartanxl IO_N1 switchbox INT muxes LONG_IO_H[2]
BitsDestination
MAIN[22][3]MAIN[20][2]MAIN[21][2]MAIN[22][2]CELL.LONG_IO_H[2]
Source
0001CELL.LONG_V[2]
0010CELL.LONG_V[4]
0111CELL.SINGLE_V[5]
1111off
spartanxl IO_N1 switchbox INT muxes LONG_IO_H[3]
BitsDestination
MAIN[4][1]MAIN[23][2]CELL.LONG_IO_H[3]
Source
00CELL.LONG_V[5]
01CELL.SINGLE_V[6]
11off
spartanxl IO_N1 switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[26][2]MAIN[26][3]MAIN[29][3]MAIN[28][2]MAIN[27][3]MAIN[28][3]MAIN[27][2]CELL.IMUX_IO_O1[0]
Source
0011111CELL.DOUBLE_V0[0]
0100110CELL.LONG_V[5]
0111011CELL.LONG_V[3]
0111101CELL.LONG_V[4]
1100111CELL.DOUBLE_V1[1]
1111111CELL.TIE_0
spartanxl IO_N1 switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[1][2]MAIN[0][2]MAIN[0][3]MAIN[1][3]MAIN[2][3]MAIN[2][2]MAIN[3][1]CELL.IMUX_IO_O1[1]
Source
0111101CELL.TIE_0
1011101CELL.LONG_IO_H[2]
1011110CELL_E.DOUBLE_V0[1]
1101101CELL_E.DOUBLE_V1[0]
1101110CELL_E.LONG_V[2]
1110101CELL_E.LONG_V[0]
1111001CELL_E.LONG_V[1]
spartanxl IO_N1 switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[23][1]MAIN[23][0]MAIN[24][0]MAIN[25][0]MAIN[28][0]MAIN[26][0]CELL.IMUX_IO_OK[0]
Source
001100CELL.GCLK[1]
001111CELL.SINGLE_V[3]
010100CELL.GCLK[2]
010111CELL.SINGLE_V[4]
011000CELL.GCLK[3]
011011CELL.SINGLE_V[5]
111100CELL.GCLK[0]
111111CELL.SINGLE_V[2]
spartanxl IO_N1 switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[11][0]MAIN[10][0]MAIN[10][1]MAIN[12][1]MAIN[11][1]MAIN[13][1]CELL.IMUX_IO_OK[1]
Source
000011CELL.GCLK[1]
000101CELL.GCLK[2]
000110CELL.GCLK[3]
001111CELL.GCLK[0]
110011CELL_E.SINGLE_V[2]
110101CELL_E.SINGLE_V[3]
110110CELL_E.SINGLE_V[5]
111111CELL_E.SINGLE_V[4]
spartanxl IO_N1 switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[18][1]MAIN[19][1]MAIN[20][1]MAIN[21][1]MAIN[19][0]MAIN[18][0]CELL.IMUX_IO_IK[0]
Source
001100CELL.GCLK[1]
001111CELL.SINGLE_V[2]
010100CELL.GCLK[2]
010111CELL.SINGLE_V[4]
011000CELL.GCLK[3]
011011CELL.SINGLE_V[5]
111100CELL.GCLK[0]
111111CELL.SINGLE_V[3]
spartanxl IO_N1 switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[16][0]MAIN[14][0]MAIN[14][1]MAIN[15][1]MAIN[16][1]MAIN[17][1]CELL.IMUX_IO_IK[1]
Source
000011CELL.GCLK[1]
000101CELL.GCLK[2]
000110CELL.GCLK[3]
001111CELL.GCLK[0]
110011CELL_E.SINGLE_V[2]
110101CELL_E.SINGLE_V[3]
110110CELL_E.SINGLE_V[4]
111111CELL_E.SINGLE_V[5]
spartanxl IO_N1 switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[5][4]MAIN[3][4]MAIN[6][6]MAIN[6][4]MAIN[4][4]MAIN[6][5]MAIN[5][5]MAIN[4][5]CELL.IMUX_IO_T[0]
Source
00011111CELL.TIE_0
00100111CELL.LONG_IO_H[3]
00101101CELL.LONG_IO_H[0]
00101110CELL.LONG_IO_H[2]
00111010CELL.GCLK[0]
01101111CELL.DOUBLE_IO_N1[0]
01111011CELL.DOUBLE_IO_N2[1]
10110111CELL.DOUBLE_IO_N1[1]
10111101CELL.LONG_IO_H[1]
11111111CELL.DOUBLE_IO_N2[0]
spartanxl IO_N1 switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[1][4]MAIN[0][5]MAIN[11][4]MAIN[3][5]MAIN[2][5]MAIN[2][4]MAIN[1][5]MAIN[0][4]CELL.IMUX_IO_T[1]
Source
00011111CELL.TIE_0
00100111CELL.GCLK[0]
00110011CELL.LONG_IO_H[0]
00111001CELL.LONG_IO_H[3]
00111010CELL.LONG_IO_H[2]
01101111CELL.DOUBLE_IO_N1[1]
01111011CELL.DOUBLE_IO_N2[1]
10110111CELL.DOUBLE_IO_N2[0]
10111101CELL.LONG_IO_H[1]
11111111CELL.DOUBLE_IO_N1[0]

Bels IO

spartanxl IO_N1 bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[22][6]CELL.IMUX_IO_IK[1] invert by !MAIN[13][6]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[32][6]CELL.IMUX_IO_OK[1] invert by !MAIN[2][6]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_F2_NCELL.IMUX_CLB_G2_N
TinCELL.IMUX_IO_T[0] invert by !MAIN[34][6]CELL.IMUX_IO_T[1] invert by !MAIN[0][6]
I1outCELL.OUT_IO_SN_I1[0]CELL.OUT_IO_SN_I1[1]
I2outCELL.OUT_IO_SN_I2[0]CELL.OUT_IO_SN_I2[1]
spartanxl IO_N1 bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[23][6]!MAIN[12][6]
OFF_SRVAL bit 0!MAIN[24][5]!MAIN[11][5]
READBACK_I1 bit 0!MAIN[18][3]!MAIN[17][4]
READBACK_I2 bit 0!MAIN[18][4]!MAIN[17][3]
READBACK_OQ bit 0!MAIN[16][3]!MAIN[16][4]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[25][6]!MAIN[9][6]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[24][6]MAIN[10][6]
IFF_CE_ENABLE!MAIN[19][5]!MAIN[13][4]
OFF_CE_ENABLE!MAIN[30][6]!MAIN[12][4]
SYNC_D[enum: IO_SYNC_D][enum: IO_SYNC_D]
IFF_CE_ENABLE_NO_IQ!MAIN[8][2]!MAIN[8][3]
MUX_T[enum: IO_MUX_T][enum: IO_MUX_T]
DRIVE[enum: IO_DRIVE][enum: IO_DRIVE]
_5V_TOLERANTMAIN[13][2]MAIN[12][2]
spartanxl IO_N1 enum IO_SLEW
IO[0].SLEWMAIN[33][6]
IO[1].SLEWMAIN[1][6]
FAST0
SLOW1
spartanxl IO_N1 enum IO_PULL
IO[0].PULLMAIN[22][5]MAIN[23][5]
IO[1].PULLMAIN[13][5]MAIN[12][5]
NONE11
PULLUP01
PULLDOWN10
spartanxl IO_N1 enum IO_MUX_I
IO[0].MUX_I1MAIN[19][6]MAIN[17][6]
IO[1].MUX_I1MAIN[16][6]MAIN[15][5]
IO[0].MUX_I2MAIN[21][6]MAIN[20][6]
IO[1].MUX_I2MAIN[15][6]MAIN[14][6]
I01
IQ11
IQL10
spartanxl IO_N1 enum IO_IFF_D
IO[0].IFF_DMAIN[18][6]MAIN[20][5]
IO[1].IFF_DMAIN[16][5]MAIN[14][5]
I11
DELAY00
MEDDELAY01
SYNC10
spartanxl IO_N1 enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[26][6]
IO[1].MUX_OFF_DMAIN[8][6]
O11
O20
spartanxl IO_N1 enum IO_MUX_O
IO[0].MUX_OMAIN[28][6]MAIN[27][6]MAIN[29][6]MAIN[31][6]
IO[1].MUX_OMAIN[4][6]MAIN[3][6]MAIN[7][6]MAIN[5][6]
O10000
O1_INV0001
O20111
O2_INV1111
OQ0010
MUX1011
spartanxl IO_N1 enum IO_SYNC_D
IO[0].SYNC_DMAIN[21][5]
IO[1].SYNC_DMAIN[11][6]
I1
DELAY0
spartanxl IO_N1 enum IO_MUX_T
IO[0].MUX_TMAIN[13][3]
IO[1].MUX_TMAIN[10][3]
T1
TQ0
spartanxl IO_N1 enum IO_DRIVE
IO[0].DRIVEMAIN[14][2]
IO[1].DRIVEMAIN[12][3]
_121
_240

Bels COUT

spartanxl IO_N1 bel COUT pins
PinDirectionCOUT
OoutCELL.OUT_COUT

Bel wires

spartanxl IO_N1 bel wires
WirePins
CELL.IMUX_CLB_F2_NIO[0].O2
CELL.IMUX_CLB_G2_NIO[1].O2
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_SN_I1[0]IO[0].I1
CELL.OUT_IO_SN_I1[1]IO[1].I1
CELL.OUT_IO_SN_I2[0]IO[0].I2
CELL.OUT_IO_SN_I2[1]IO[1].I2
CELL.OUT_COUTCOUT.O

Bitstream

spartanxl IO_N1 rect MAIN
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B6 - IO[0]: !invert T IO[0]: SLEW bit 0 IO[0]: !invert OK IO[0]: MUX_O bit 0 IO[0]: ! OFF_CE_ENABLE IO[0]: MUX_O bit 1 IO[0]: MUX_O bit 3 IO[0]: MUX_O bit 2 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_D_INV IO[0]: OFF_USED IO[0]: ! IFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 1 IO[0]: MUX_I2 bit 0 IO[0]: MUX_I1 bit 1 IO[0]: IFF_D bit 1 IO[0]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I2 bit 0 IO[1]: !invert IK IO[1]: ! IFF_SRVAL bit 0 IO[1]: SYNC_D bit 0 IO[1]: OFF_USED IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0 IO[1]: MUX_O bit 1 INT: mux CELL.IMUX_IO_T[0] bit 5 IO[1]: MUX_O bit 0 IO[1]: MUX_O bit 3 IO[1]: MUX_O bit 2 IO[1]: !invert OK IO[1]: SLEW bit 0 IO[1]: !invert T
B5 INT: !pass CELL.DOUBLE_IO_N0[3] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_N0[2] ← CELL.DBUF_IO_H[0] INT: mux CELL.DBUF_IO_H[1] bit 0 INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_N2[3] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N1[3] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N0[2] INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_N0[2] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N2[2] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N0[1] INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N0[1] INT: !bipass CELL.DOUBLE_IO_N0[1] = CELL.DOUBLE_IO_N2[1] IO[0]: ! OFF_SRVAL bit 0 IO[0]: PULL bit 0 IO[0]: PULL bit 1 IO[0]: SYNC_D bit 0 IO[0]: IFF_D bit 0 IO[0]: ! IFF_CE_ENABLE INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N1[0] INT: mux CELL.LONG_IO_H[1] bit 0 IO[1]: IFF_D bit 1 IO[1]: MUX_I1 bit 0 IO[1]: IFF_D bit 0 IO[1]: PULL bit 1 IO[1]: PULL bit 0 IO[1]: ! OFF_SRVAL bit 0 INT: !pass CELL.DOUBLE_IO_N2[3] ← CELL.DBUF_IO_H[1] INT: !pass CELL.DOUBLE_IO_N2[2] ← CELL.DBUF_IO_H[1] INT: mux CELL.DBUF_IO_H[0] bit 0 INT: mux CELL.DBUF_IO_H[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 6
B4 INT: !pass CELL.DOUBLE_IO_N0[0] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_N0[1] ← CELL.DBUF_IO_H[0] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N0[3] INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_N0[3] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N2[3] INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_N2[2] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N1[2] INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_N1[2] INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N2[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N2[1] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.DOUBLE_IO_N0[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N1[0] - IO[0]: ! READBACK_I2 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_OQ bit 0 - INT: mux CELL.LONG_IO_H[1] bit 2 IO[1]: ! IFF_CE_ENABLE IO[1]: ! OFF_CE_ENABLE INT: mux CELL.IMUX_IO_T[1] bit 5 INT: !pass CELL.DOUBLE_IO_N2[0] ← CELL.DBUF_IO_H[1] INT: !pass CELL.DOUBLE_IO_N2[1] ← CELL.DBUF_IO_H[1] INT: mux CELL.DBUF_IO_H[0] bit 2 INT: mux CELL.DBUF_IO_H[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 7 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 6 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 7 INT: mux CELL.IMUX_IO_T[1] bit 0
B3 INT: mux CELL.DBUF_IO_H[1] bit 1 INT: mux CELL.DBUF_IO_H[1] bit 2 INT: mux CELL.DBUF_IO_H[1] bit 3 INT: !bipass CELL.DOUBLE_IO_N0[3] = CELL.DOUBLE_IO_N2[3] INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_N1[3] INT: !bipass CELL.DOUBLE_IO_N0[2] = CELL.DOUBLE_IO_N2[2] INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 5 INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N1[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N1[1] INT: mux CELL.LONG_IO_H[1] bit 3 INT: mux CELL.LONG_IO_H[2] bit 3 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0] - IO[0]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I2 bit 0 IO[0]: ! READBACK_OQ bit 0 - - IO[0]: MUX_T bit 0 IO[1]: DRIVE bit 0 - IO[1]: MUX_T bit 0 - IO[1]: ! IFF_CE_ENABLE_NO_IQ - - - - - INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 4
B2 - INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_IO_H[3] INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_IO_H[2] INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_IO_SN_I1_E1 - - INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 6 INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0] - INT: mux CELL.LONG_IO_H[3] bit 0 INT: mux CELL.LONG_IO_H[2] bit 0 INT: mux CELL.LONG_IO_H[2] bit 1 INT: mux CELL.LONG_IO_H[2] bit 2 - INT: mux CELL.LONG_IO_H[1] bit 1 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[1] INT: mux CELL.LONG_IO_H[0] bit 0 INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[0] IO[0]: DRIVE bit 0 IO[0]: _5V_TOLERANT IO[1]: _5V_TOLERANT - - - IO[0]: ! IFF_CE_ENABLE_NO_IQ - - - - - INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 6 INT: mux CELL.IMUX_IO_O1[1] bit 5
B1 INT: mux CELL.LONG_V[1] bit 2 - INT: mux CELL.LONG_V[1] bit 0 INT: mux CELL.LONG_V[2] bit 1 INT: mux CELL.LONG_V[2] bit 2 INT: mux CELL.LONG_V[2] bit 0 INT: mux CELL.LONG_V[0] bit 1 - INT: mux CELL.LONG_V[0] bit 0 INT: mux CELL.LONG_V[0] bit 2 INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_IO_SN_I1[0] INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[3] INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 5 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.LONG_V[5] bit 1 INT: mux CELL.LONG_V[5] bit 2 - INT: mux CELL.LONG_V[3] bit 2 INT: mux CELL.LONG_V[4] bit 2 INT: mux CELL.LONG_IO_H[3] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 0 - - -
B0 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.LONG_V[1] bit 1 - INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1 - INT: mux CELL.IMUX_IO_OK[0] bit 1 - INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0] - - INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 5 - INT: mux CELL.IMUX_IO_IK[1] bit 4 - - INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 4 - INT: mux CELL.LONG_V[5] bit 0 INT: mux CELL.LONG_V[3] bit 1 INT: mux CELL.LONG_V[3] bit 0 - INT: mux CELL.LONG_IO_H[0] bit 1 - INT: mux CELL.LONG_V[4] bit 1 INT: mux CELL.LONG_V[4] bit 0 -
spartanxl IO_N1 rect MAIN_S
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
spartanxl IO_N1 rect MAIN_E
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
spartanxl IO_N1 rect MAIN_W
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: !buffer CELL.LONG_V[0] ← CELL.OUT_COUT_E - - - - -

Tile IO_N1_W

Cells: 3

Switchbox INT

spartanxl IO_N1_W switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[21][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[25][8]
CELL.LONG_H[2]CELL.SINGLE_V[3]!MAIN[24][1]
spartanxl IO_N1_W switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I2_E1!MAIN[22][1]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[23][8]
CELL.SINGLE_V[1]CELL.LONG_IO_H[0]!MAIN[15][2]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I2[0]!MAIN[22][0]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[29][8]
CELL.SINGLE_V[2]CELL.LONG_IO_H[1]!MAIN[17][2]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I1[0]!MAIN[25][2]
CELL.SINGLE_V[3]CELL.LONG_H[2]!MAIN_S[28][9]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I1_E1!MAIN[29][2]
CELL.SINGLE_V[4]CELL.OUT_IO_SN_I2_E1!MAIN[35][0]
CELL.SINGLE_V[5]CELL.LONG_IO_H[2]!MAIN[33][2]
CELL.SINGLE_V[5]CELL.OUT_IO_SN_I2[0]!MAIN[32][0]
CELL.SINGLE_V[6]CELL.LONG_IO_H[3]!MAIN[34][2]
CELL.SINGLE_V[6]CELL.OUT_IO_SN_I1[0]!MAIN[25][1]
CELL.SINGLE_V[7]CELL.OUT_IO_SN_I1_E1!MAIN[32][2]
CELL.DOUBLE_V0[0]CELL.OUT_IO_SN_I1_E1!MAIN[21][3]
CELL.DOUBLE_V0[1]CELL.OUT_IO_SN_I2[0]!MAIN[31][0]
CELL.DOUBLE_V1[0]CELL.OUT_IO_SN_I1[0]!MAIN[20][3]
CELL.DOUBLE_V1[1]CELL.OUT_IO_SN_I2_E1!MAIN[30][0]
CELL.DOUBLE_IO_N0[0]CELL.DBUF_IO_H[0]!MAIN[35][4]
CELL.DOUBLE_IO_N0[1]CELL.DBUF_IO_H[0]!MAIN[34][4]
CELL.DOUBLE_IO_N0[2]CELL.DBUF_IO_H[0]!MAIN[34][5]
CELL.DOUBLE_IO_N0[3]CELL.DBUF_IO_H[0]!MAIN[35][5]
CELL.DOUBLE_IO_N2[0]CELL.DBUF_IO_H[1]!MAIN[10][4]
CELL.DOUBLE_IO_N2[1]CELL.DBUF_IO_H[1]!MAIN[9][4]
CELL.DOUBLE_IO_N2[2]CELL.DBUF_IO_H[1]!MAIN[9][5]
CELL.DOUBLE_IO_N2[3]CELL.DBUF_IO_H[1]!MAIN[10][5]
spartanxl IO_N1_W switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_V[0]CELL.DOUBLE_IO_N1[0]!MAIN[18][5]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_N0[0]!MAIN[24][4]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_N2[0]!MAIN[22][4]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_N1[1]!MAIN[25][3]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_N0[1]!MAIN[26][5]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_N2[1]!MAIN[27][4]
CELL.SINGLE_V[4]CELL.DOUBLE_IO_N1[2]!MAIN[28][4]
CELL.SINGLE_V[5]CELL.DOUBLE_IO_N0[2]!MAIN[29][5]
CELL.SINGLE_V[5]CELL.DOUBLE_IO_N2[2]!MAIN[30][4]
CELL.SINGLE_V[6]CELL.DOUBLE_IO_N1[3]!MAIN[31][3]
CELL.SINGLE_V[7]CELL.DOUBLE_IO_N0[3]!MAIN[32][4]
CELL.SINGLE_V[7]CELL.DOUBLE_IO_N2[3]!MAIN[32][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N0[1]!MAIN[27][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N1[1]!MAIN[24][3]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N2[1]!MAIN[26][4]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N0[2]!MAIN[30][5]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N1[2]!MAIN[29][4]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N2[2]!MAIN[28][5]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N0[0]!MAIN[25][4]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N1[0]!MAIN[20][4]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N2[0]!MAIN[21][4]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N0[3]!MAIN[33][4]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N1[3]!MAIN[31][5]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N2[3]!MAIN[31][4]
CELL.DOUBLE_IO_N0[0]CELL.DOUBLE_IO_N2[0]!MAIN[23][4]
CELL.DOUBLE_IO_N0[1]CELL.DOUBLE_IO_N2[1]!MAIN[25][5]
CELL.DOUBLE_IO_N0[2]CELL.DOUBLE_IO_N2[2]!MAIN[30][3]
CELL.DOUBLE_IO_N0[3]CELL.DOUBLE_IO_N2[3]!MAIN[32][3]
spartanxl IO_N1_W switchbox INT muxes DBUF_IO_H[0]
BitsDestination
MAIN[7][4]MAIN[8][4]MAIN[7][5]MAIN[8][5]CELL.DBUF_IO_H[0]
Source
0011CELL.DOUBLE_IO_N2[0]
0101CELL.DOUBLE_IO_N2[2]
0110CELL.DOUBLE_IO_N2[3]
1111CELL.DOUBLE_IO_N2[1]
spartanxl IO_N1_W switchbox INT muxes DBUF_IO_H[1]
BitsDestination
MAIN[33][3]MAIN[34][3]MAIN[35][3]MAIN[33][5]CELL.DBUF_IO_H[1]
Source
0011CELL.DOUBLE_IO_N0[1]
0101CELL.DOUBLE_IO_N0[2]
0110CELL.DOUBLE_IO_N0[3]
1111CELL.DOUBLE_IO_N0[0]
spartanxl IO_N1_W switchbox INT muxes LONG_V[0]
BitsDestination
MAIN[26][1]MAIN[29][1]MAIN[27][1]CELL.LONG_V[0]
Source
000CELL.LONG_IO_H[0]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_N1_W switchbox INT muxes LONG_V[1]
BitsDestination
MAIN[35][1]MAIN[34][0]MAIN[33][1]CELL.LONG_V[1]
Source
000CELL.LONG_IO_H[1]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_N1_W switchbox INT muxes LONG_V[2]
BitsDestination
MAIN[31][1]MAIN[32][1]MAIN[30][1]CELL.LONG_V[2]
Source
000CELL.LONG_IO_H[2]
011CELL.OUT_IO_SN_I2_E1
111off
spartanxl IO_N1_W switchbox INT muxes LONG_V[3]
BitsDestination
MAIN[6][1]MAIN[7][0]MAIN[6][0]CELL.LONG_V[3]
Source
000CELL.LONG_IO_H[1]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_N1_W switchbox INT muxes LONG_V[4]
BitsDestination
MAIN[5][1]MAIN[2][0]MAIN[1][0]CELL.LONG_V[4]
Source
000CELL.LONG_IO_H[2]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_N1_W switchbox INT muxes LONG_V[5]
BitsDestination
MAIN[8][1]MAIN[9][1]MAIN[8][0]CELL.LONG_V[5]
Source
000CELL.LONG_IO_H[3]
011CELL.OUT_IO_SN_I2[0]
111off
spartanxl IO_N1_W switchbox INT muxes LONG_IO_H[0]
BitsDestination
MAIN[4][0]MAIN[16][2]CELL.LONG_IO_H[0]
Source
00CELL.LONG_V[0]
01CELL.SINGLE_V[1]
11off
spartanxl IO_N1_W switchbox INT muxes LONG_IO_H[1]
BitsDestination
MAIN[23][3]MAIN[14][4]MAIN[18][2]MAIN[17][5]CELL.LONG_IO_H[1]
Source
0001CELL.LONG_V[1]
0010CELL.LONG_V[3]
0111CELL.SINGLE_V[2]
1111off
spartanxl IO_N1_W switchbox INT muxes LONG_IO_H[2]
BitsDestination
MAIN[22][3]MAIN[20][2]MAIN[21][2]MAIN[22][2]CELL.LONG_IO_H[2]
Source
0001CELL.LONG_V[2]
0010CELL.LONG_V[4]
0111CELL.SINGLE_V[5]
1111off
spartanxl IO_N1_W switchbox INT muxes LONG_IO_H[3]
BitsDestination
MAIN[4][1]MAIN[23][2]CELL.LONG_IO_H[3]
Source
00CELL.LONG_V[5]
01CELL.SINGLE_V[6]
11off
spartanxl IO_N1_W switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[26][2]MAIN[26][3]MAIN[29][3]MAIN[28][2]MAIN[27][3]MAIN[28][3]MAIN[27][2]CELL.IMUX_IO_O1[0]
Source
0011111CELL.DOUBLE_V0[0]
0100110CELL.LONG_V[5]
0111011CELL.LONG_V[3]
0111101CELL.LONG_V[4]
1100111CELL.DOUBLE_V1[1]
1111111CELL.TIE_0
spartanxl IO_N1_W switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[1][2]MAIN[0][2]MAIN[0][3]MAIN[1][3]MAIN[2][3]MAIN[2][2]MAIN[3][1]CELL.IMUX_IO_O1[1]
Source
0111101CELL.TIE_0
1011101CELL.LONG_IO_H[2]
1011110CELL_E.DOUBLE_V0[1]
1101101CELL_E.DOUBLE_V1[0]
1101110CELL_E.LONG_V[2]
1110101CELL_E.LONG_V[0]
1111001CELL_E.LONG_V[1]
spartanxl IO_N1_W switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[23][1]MAIN[23][0]MAIN[24][0]MAIN[25][0]MAIN[28][0]MAIN[26][0]CELL.IMUX_IO_OK[0]
Source
001100CELL.GCLK[1]
001111CELL.SINGLE_V[3]
010100CELL.GCLK[2]
010111CELL.SINGLE_V[4]
011000CELL.GCLK[3]
011011CELL.SINGLE_V[5]
111100CELL.GCLK[0]
111111CELL.SINGLE_V[2]
spartanxl IO_N1_W switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[11][0]MAIN[10][0]MAIN[10][1]MAIN[12][1]MAIN[11][1]MAIN[13][1]CELL.IMUX_IO_OK[1]
Source
000011CELL.GCLK[1]
000101CELL.GCLK[2]
000110CELL.GCLK[3]
001111CELL.GCLK[0]
110011CELL_E.SINGLE_V[2]
110101CELL_E.SINGLE_V[3]
110110CELL_E.SINGLE_V[5]
111111CELL_E.SINGLE_V[4]
spartanxl IO_N1_W switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[18][1]MAIN[19][1]MAIN[20][1]MAIN[21][1]MAIN[19][0]MAIN[18][0]CELL.IMUX_IO_IK[0]
Source
001100CELL.GCLK[1]
001111CELL.SINGLE_V[2]
010100CELL.GCLK[2]
010111CELL.SINGLE_V[4]
011000CELL.GCLK[3]
011011CELL.SINGLE_V[5]
111100CELL.GCLK[0]
111111CELL.SINGLE_V[3]
spartanxl IO_N1_W switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[16][0]MAIN[14][0]MAIN[14][1]MAIN[15][1]MAIN[16][1]MAIN[17][1]CELL.IMUX_IO_IK[1]
Source
000011CELL.GCLK[1]
000101CELL.GCLK[2]
000110CELL.GCLK[3]
001111CELL.GCLK[0]
110011CELL_E.SINGLE_V[2]
110101CELL_E.SINGLE_V[3]
110110CELL_E.SINGLE_V[4]
111111CELL_E.SINGLE_V[5]
spartanxl IO_N1_W switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[5][4]MAIN[3][4]MAIN[6][6]MAIN[6][4]MAIN[4][4]MAIN[6][5]MAIN[5][5]MAIN[4][5]CELL.IMUX_IO_T[0]
Source
00011111CELL.TIE_0
00100111CELL.LONG_IO_H[3]
00101101CELL.LONG_IO_H[0]
00101110CELL.LONG_IO_H[2]
00111010CELL.GCLK[0]
01101111CELL.DOUBLE_IO_N1[0]
01111011CELL.DOUBLE_IO_N2[1]
10110111CELL.DOUBLE_IO_N1[1]
10111101CELL.LONG_IO_H[1]
11111111CELL.DOUBLE_IO_N2[0]
spartanxl IO_N1_W switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[1][4]MAIN[0][5]MAIN[11][4]MAIN[3][5]MAIN[2][5]MAIN[2][4]MAIN[1][5]MAIN[0][4]CELL.IMUX_IO_T[1]
Source
00011111CELL.TIE_0
00100111CELL.GCLK[0]
00110011CELL.LONG_IO_H[0]
00111001CELL.LONG_IO_H[3]
00111010CELL.LONG_IO_H[2]
01101111CELL.DOUBLE_IO_N1[1]
01111011CELL.DOUBLE_IO_N2[1]
10110111CELL.DOUBLE_IO_N2[0]
10111101CELL.LONG_IO_H[1]
11111111CELL.DOUBLE_IO_N1[0]

Bels IO

spartanxl IO_N1_W bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[22][6]CELL.IMUX_IO_IK[1] invert by !MAIN[13][6]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[32][6]CELL.IMUX_IO_OK[1] invert by !MAIN[2][6]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_F2_NCELL.IMUX_CLB_G2_N
TinCELL.IMUX_IO_T[0] invert by !MAIN[34][6]CELL.IMUX_IO_T[1] invert by !MAIN[0][6]
I1outCELL.OUT_IO_SN_I1[0]CELL.OUT_IO_SN_I1[1]
I2outCELL.OUT_IO_SN_I2[0]CELL.OUT_IO_SN_I2[1]
CLKINoutCELL.OUT_IO_CLKIN-
spartanxl IO_N1_W bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[23][6]!MAIN[12][6]
OFF_SRVAL bit 0!MAIN[24][5]!MAIN[11][5]
READBACK_I1 bit 0!MAIN[18][3]!MAIN[17][4]
READBACK_I2 bit 0!MAIN[18][4]!MAIN[17][3]
READBACK_OQ bit 0!MAIN[16][3]!MAIN[16][4]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[25][6]!MAIN[9][6]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[24][6]MAIN[10][6]
IFF_CE_ENABLE!MAIN[19][5]!MAIN[13][4]
OFF_CE_ENABLE!MAIN[30][6]!MAIN[12][4]
SYNC_D[enum: IO_SYNC_D][enum: IO_SYNC_D]
IFF_CE_ENABLE_NO_IQ!MAIN[8][2]!MAIN[8][3]
MUX_T[enum: IO_MUX_T][enum: IO_MUX_T]
DRIVE[enum: IO_DRIVE][enum: IO_DRIVE]
_5V_TOLERANTMAIN[13][2]MAIN[12][2]
spartanxl IO_N1_W enum IO_SLEW
IO[0].SLEWMAIN[33][6]
IO[1].SLEWMAIN[1][6]
FAST0
SLOW1
spartanxl IO_N1_W enum IO_PULL
IO[0].PULLMAIN[22][5]MAIN[23][5]
IO[1].PULLMAIN[13][5]MAIN[12][5]
NONE11
PULLUP01
PULLDOWN10
spartanxl IO_N1_W enum IO_MUX_I
IO[0].MUX_I1MAIN[19][6]MAIN[17][6]
IO[1].MUX_I1MAIN[16][6]MAIN[15][5]
IO[0].MUX_I2MAIN[21][6]MAIN[20][6]
IO[1].MUX_I2MAIN[15][6]MAIN[14][6]
I01
IQ11
IQL10
spartanxl IO_N1_W enum IO_IFF_D
IO[0].IFF_DMAIN[18][6]MAIN[20][5]
IO[1].IFF_DMAIN[16][5]MAIN[14][5]
I11
DELAY00
MEDDELAY01
SYNC10
spartanxl IO_N1_W enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[26][6]
IO[1].MUX_OFF_DMAIN[8][6]
O11
O20
spartanxl IO_N1_W enum IO_MUX_O
IO[0].MUX_OMAIN[28][6]MAIN[27][6]MAIN[29][6]MAIN[31][6]
IO[1].MUX_OMAIN[4][6]MAIN[3][6]MAIN[7][6]MAIN[5][6]
O10000
O1_INV0001
O20111
O2_INV1111
OQ0010
MUX1011
spartanxl IO_N1_W enum IO_SYNC_D
IO[0].SYNC_DMAIN[21][5]
IO[1].SYNC_DMAIN[11][6]
I1
DELAY0
spartanxl IO_N1_W enum IO_MUX_T
IO[0].MUX_TMAIN[13][3]
IO[1].MUX_TMAIN[10][3]
T1
TQ0
spartanxl IO_N1_W enum IO_DRIVE
IO[0].DRIVEMAIN[14][2]
IO[1].DRIVEMAIN[12][3]
_121
_240

Bels COUT

spartanxl IO_N1_W bel COUT pins
PinDirectionCOUT
OoutCELL.OUT_COUT

Bel wires

spartanxl IO_N1_W bel wires
WirePins
CELL.IMUX_CLB_F2_NIO[0].O2
CELL.IMUX_CLB_G2_NIO[1].O2
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_SN_I1[0]IO[0].I1
CELL.OUT_IO_SN_I1[1]IO[1].I1
CELL.OUT_IO_SN_I2[0]IO[0].I2
CELL.OUT_IO_SN_I2[1]IO[1].I2
CELL.OUT_IO_CLKINIO[0].CLKIN
CELL.OUT_COUTCOUT.O

Bitstream

spartanxl IO_N1_W rect MAIN
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B6 - IO[0]: !invert T IO[0]: SLEW bit 0 IO[0]: !invert OK IO[0]: MUX_O bit 0 IO[0]: ! OFF_CE_ENABLE IO[0]: MUX_O bit 1 IO[0]: MUX_O bit 3 IO[0]: MUX_O bit 2 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_D_INV IO[0]: OFF_USED IO[0]: ! IFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 1 IO[0]: MUX_I2 bit 0 IO[0]: MUX_I1 bit 1 IO[0]: IFF_D bit 1 IO[0]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I2 bit 0 IO[1]: !invert IK IO[1]: ! IFF_SRVAL bit 0 IO[1]: SYNC_D bit 0 IO[1]: OFF_USED IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0 IO[1]: MUX_O bit 1 INT: mux CELL.IMUX_IO_T[0] bit 5 IO[1]: MUX_O bit 0 IO[1]: MUX_O bit 3 IO[1]: MUX_O bit 2 IO[1]: !invert OK IO[1]: SLEW bit 0 IO[1]: !invert T
B5 INT: !pass CELL.DOUBLE_IO_N0[3] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_N0[2] ← CELL.DBUF_IO_H[0] INT: mux CELL.DBUF_IO_H[1] bit 0 INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_N2[3] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N1[3] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N0[2] INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_N0[2] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N2[2] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N0[1] INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N0[1] INT: !bipass CELL.DOUBLE_IO_N0[1] = CELL.DOUBLE_IO_N2[1] IO[0]: ! OFF_SRVAL bit 0 IO[0]: PULL bit 0 IO[0]: PULL bit 1 IO[0]: SYNC_D bit 0 IO[0]: IFF_D bit 0 IO[0]: ! IFF_CE_ENABLE INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N1[0] INT: mux CELL.LONG_IO_H[1] bit 0 IO[1]: IFF_D bit 1 IO[1]: MUX_I1 bit 0 IO[1]: IFF_D bit 0 IO[1]: PULL bit 1 IO[1]: PULL bit 0 IO[1]: ! OFF_SRVAL bit 0 INT: !pass CELL.DOUBLE_IO_N2[3] ← CELL.DBUF_IO_H[1] INT: !pass CELL.DOUBLE_IO_N2[2] ← CELL.DBUF_IO_H[1] INT: mux CELL.DBUF_IO_H[0] bit 0 INT: mux CELL.DBUF_IO_H[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 6
B4 INT: !pass CELL.DOUBLE_IO_N0[0] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_N0[1] ← CELL.DBUF_IO_H[0] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N0[3] INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_N0[3] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N2[3] INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_N2[2] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N1[2] INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_N1[2] INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N2[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N2[1] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.DOUBLE_IO_N0[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N1[0] - IO[0]: ! READBACK_I2 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_OQ bit 0 - INT: mux CELL.LONG_IO_H[1] bit 2 IO[1]: ! IFF_CE_ENABLE IO[1]: ! OFF_CE_ENABLE INT: mux CELL.IMUX_IO_T[1] bit 5 INT: !pass CELL.DOUBLE_IO_N2[0] ← CELL.DBUF_IO_H[1] INT: !pass CELL.DOUBLE_IO_N2[1] ← CELL.DBUF_IO_H[1] INT: mux CELL.DBUF_IO_H[0] bit 2 INT: mux CELL.DBUF_IO_H[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 7 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 6 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 7 INT: mux CELL.IMUX_IO_T[1] bit 0
B3 INT: mux CELL.DBUF_IO_H[1] bit 1 INT: mux CELL.DBUF_IO_H[1] bit 2 INT: mux CELL.DBUF_IO_H[1] bit 3 INT: !bipass CELL.DOUBLE_IO_N0[3] = CELL.DOUBLE_IO_N2[3] INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_N1[3] INT: !bipass CELL.DOUBLE_IO_N0[2] = CELL.DOUBLE_IO_N2[2] INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 5 INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N1[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N1[1] INT: mux CELL.LONG_IO_H[1] bit 3 INT: mux CELL.LONG_IO_H[2] bit 3 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0] - IO[0]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I2 bit 0 IO[0]: ! READBACK_OQ bit 0 - - IO[0]: MUX_T bit 0 IO[1]: DRIVE bit 0 - IO[1]: MUX_T bit 0 - IO[1]: ! IFF_CE_ENABLE_NO_IQ - - - - - INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 4
B2 - INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_IO_H[3] INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_IO_H[2] INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_IO_SN_I1_E1 - - INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 6 INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0] - INT: mux CELL.LONG_IO_H[3] bit 0 INT: mux CELL.LONG_IO_H[2] bit 0 INT: mux CELL.LONG_IO_H[2] bit 1 INT: mux CELL.LONG_IO_H[2] bit 2 - INT: mux CELL.LONG_IO_H[1] bit 1 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[1] INT: mux CELL.LONG_IO_H[0] bit 0 INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[0] IO[0]: DRIVE bit 0 IO[0]: _5V_TOLERANT IO[1]: _5V_TOLERANT - - - IO[0]: ! IFF_CE_ENABLE_NO_IQ - - - - - INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 6 INT: mux CELL.IMUX_IO_O1[1] bit 5
B1 INT: mux CELL.LONG_V[1] bit 2 - INT: mux CELL.LONG_V[1] bit 0 INT: mux CELL.LONG_V[2] bit 1 INT: mux CELL.LONG_V[2] bit 2 INT: mux CELL.LONG_V[2] bit 0 INT: mux CELL.LONG_V[0] bit 1 - INT: mux CELL.LONG_V[0] bit 0 INT: mux CELL.LONG_V[0] bit 2 INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_IO_SN_I1[0] INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[3] INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 5 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.LONG_V[5] bit 1 INT: mux CELL.LONG_V[5] bit 2 - INT: mux CELL.LONG_V[3] bit 2 INT: mux CELL.LONG_V[4] bit 2 INT: mux CELL.LONG_IO_H[3] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 0 - - -
B0 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.LONG_V[1] bit 1 - INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1 - INT: mux CELL.IMUX_IO_OK[0] bit 1 - INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0] - - INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 0 - INT: mux CELL.IMUX_IO_IK[1] bit 5 - INT: mux CELL.IMUX_IO_IK[1] bit 4 - - INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 4 - INT: mux CELL.LONG_V[5] bit 0 INT: mux CELL.LONG_V[3] bit 1 INT: mux CELL.LONG_V[3] bit 0 - INT: mux CELL.LONG_IO_H[0] bit 1 - INT: mux CELL.LONG_V[4] bit 1 INT: mux CELL.LONG_V[4] bit 0 -
spartanxl IO_N1_W rect MAIN_S
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
spartanxl IO_N1_W rect MAIN_E
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
spartanxl IO_N1_W rect MAIN_W
BitFrame
F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - -