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Splitters

Tile LLH.CLB

Cells: 2 IRIs: 0

Muxes

spartanxl LLH.CLB muxes
DestinationSources
TCELL0:LONG.H0TCELL1:LONG.H0
TCELL0:LONG.H1TCELL1:LONG.H1
TCELL0:LONG.H4TCELL1:LONG.H4
TCELL0:LONG.H5TCELL1:LONG.H5
TCELL1:LONG.H0TCELL0:LONG.H0
TCELL1:LONG.H1TCELL0:LONG.H1
TCELL1:LONG.H4TCELL0:LONG.H4
TCELL1:LONG.H5TCELL0:LONG.H5

Bel TBUF_SPLITTER0

spartanxl LLH.CLB bel TBUF_SPLITTER0
PinDirectionWires
Lin-outTCELL0:LONG.H2
Rin-outTCELL1:LONG.H2

Bel TBUF_SPLITTER1

spartanxl LLH.CLB bel TBUF_SPLITTER1
PinDirectionWires
Lin-outTCELL0:LONG.H3
Rin-outTCELL1:LONG.H3

Bel wires

spartanxl LLH.CLB bel wires
WirePins
TCELL0:LONG.H2TBUF_SPLITTER0.L
TCELL0:LONG.H3TBUF_SPLITTER1.L
TCELL1:LONG.H2TBUF_SPLITTER0.R
TCELL1:LONG.H3TBUF_SPLITTER1.R

Bitstream

spartanxl LLH.CLB bittile 0
BitFrame
1 0
9 - ~TBUF_SPLITTER1:BUF_W
8 - ~TBUF_SPLITTER1:BUF_E
7 - -
6 - -
5 - -
4 - -
3 ~TBUF_SPLITTER1:PASS -
2 - -
1 ~INT:BUF.0.LONG.H4.1.LONG.H4 ~INT:BUF.0.LONG.H5.1.LONG.H5
0 ~INT:BUF.1.LONG.H4.0.LONG.H4 ~INT:BUF.1.LONG.H5.0.LONG.H5
spartanxl LLH.CLB bittile 1
BitFrame
1 0
7 ~TBUF_SPLITTER0:BUF_W -
6 ~TBUF_SPLITTER0:BUF_E -
5 - ~INT:BUF.1.LONG.H1.0.LONG.H1
4 ~TBUF_SPLITTER0:PASS ~INT:BUF.0.LONG.H0.1.LONG.H0
3 - ~INT:BUF.1.LONG.H0.0.LONG.H0
2 - ~INT:BUF.0.LONG.H1.1.LONG.H1
1 - -
0 - -
INT:BUF.0.LONG.H0.1.LONG.H0 1.0.4
INT:BUF.0.LONG.H1.1.LONG.H1 1.0.2
INT:BUF.0.LONG.H4.1.LONG.H4 0.1.1
INT:BUF.0.LONG.H5.1.LONG.H5 0.0.1
INT:BUF.1.LONG.H0.0.LONG.H0 1.0.3
INT:BUF.1.LONG.H1.0.LONG.H1 1.0.5
INT:BUF.1.LONG.H4.0.LONG.H4 0.1.0
INT:BUF.1.LONG.H5.0.LONG.H5 0.0.0
TBUF_SPLITTER0:BUF_E 1.1.6
TBUF_SPLITTER0:BUF_W 1.1.7
TBUF_SPLITTER0:PASS 1.1.4
TBUF_SPLITTER1:BUF_E 0.0.8
TBUF_SPLITTER1:BUF_W 0.0.9
TBUF_SPLITTER1:PASS 0.1.3
inverted ~[0]

Tile LLH.CLB.B

Cells: 2 IRIs: 0

Muxes

spartanxl LLH.CLB.B muxes
DestinationSources
TCELL0:LONG.H0TCELL1:LONG.H0
TCELL0:LONG.H1TCELL1:LONG.H1
TCELL0:LONG.H4TCELL1:LONG.H4
TCELL0:LONG.H5TCELL1:LONG.H5
TCELL1:LONG.H0TCELL0:LONG.H0
TCELL1:LONG.H1TCELL0:LONG.H1
TCELL1:LONG.H4TCELL0:LONG.H4
TCELL1:LONG.H5TCELL0:LONG.H5

Bel TBUF_SPLITTER0

spartanxl LLH.CLB.B bel TBUF_SPLITTER0
PinDirectionWires
Lin-outTCELL0:LONG.H2
Rin-outTCELL1:LONG.H2

Bel TBUF_SPLITTER1

spartanxl LLH.CLB.B bel TBUF_SPLITTER1
PinDirectionWires
Lin-outTCELL0:LONG.H3
Rin-outTCELL1:LONG.H3

Bel wires

spartanxl LLH.CLB.B bel wires
WirePins
TCELL0:LONG.H2TBUF_SPLITTER0.L
TCELL0:LONG.H3TBUF_SPLITTER1.L
TCELL1:LONG.H2TBUF_SPLITTER0.R
TCELL1:LONG.H3TBUF_SPLITTER1.R

Bitstream

spartanxl LLH.CLB.B bittile 0
BitFrame
1 0
9 - ~TBUF_SPLITTER1:BUF_W
8 - ~TBUF_SPLITTER1:BUF_E
7 - -
6 - -
5 - -
4 - -
3 ~TBUF_SPLITTER1:PASS -
2 - -
1 ~INT:BUF.0.LONG.H4.1.LONG.H4 ~INT:BUF.0.LONG.H5.1.LONG.H5
0 ~INT:BUF.1.LONG.H4.0.LONG.H4 ~INT:BUF.1.LONG.H5.0.LONG.H5
spartanxl LLH.CLB.B bittile 1
BitFrame
1 0
12 ~INT:BUF.0.LONG.H0.1.LONG.H0 ~INT:BUF.1.LONG.H0.0.LONG.H0
11 ~INT:BUF.0.LONG.H1.1.LONG.H1 ~INT:BUF.1.LONG.H1.0.LONG.H1
10 - -
9 - -
8 ~TBUF_SPLITTER0:PASS ~TBUF_SPLITTER0:BUF_W
7 - -
6 - -
5 - -
4 - -
3 - -
2 - -
1 - -
0 ~TBUF_SPLITTER0:BUF_E -
INT:BUF.0.LONG.H0.1.LONG.H0 1.1.12
INT:BUF.0.LONG.H1.1.LONG.H1 1.1.11
INT:BUF.0.LONG.H4.1.LONG.H4 0.1.1
INT:BUF.0.LONG.H5.1.LONG.H5 0.0.1
INT:BUF.1.LONG.H0.0.LONG.H0 1.0.12
INT:BUF.1.LONG.H1.0.LONG.H1 1.0.11
INT:BUF.1.LONG.H4.0.LONG.H4 0.1.0
INT:BUF.1.LONG.H5.0.LONG.H5 0.0.0
TBUF_SPLITTER0:BUF_E 1.1.0
TBUF_SPLITTER0:BUF_W 1.0.8
TBUF_SPLITTER0:PASS 1.1.8
TBUF_SPLITTER1:BUF_E 0.0.8
TBUF_SPLITTER1:BUF_W 0.0.9
TBUF_SPLITTER1:PASS 0.1.3
inverted ~[0]

Tile LLH.IO.B

Cells: 2 IRIs: 0

Muxes

spartanxl LLH.IO.B muxes
DestinationSources
TCELL0:LONG.H3TCELL1:LONG.H3
TCELL0:LONG.H4TCELL1:LONG.H4
TCELL0:LONG.H5TCELL1:LONG.H5
TCELL0:LONG.IO.H0TCELL1:LONG.IO.H0
TCELL0:LONG.IO.H1TCELL1:LONG.IO.H1
TCELL0:LONG.IO.H2TCELL1:LONG.IO.H2
TCELL0:LONG.IO.H3TCELL1:LONG.IO.H3
TCELL1:LONG.H3TCELL0:LONG.H3
TCELL1:LONG.H4TCELL0:LONG.H4
TCELL1:LONG.H5TCELL0:LONG.H5
TCELL1:LONG.IO.H0TCELL0:LONG.IO.H0
TCELL1:LONG.IO.H1TCELL0:LONG.IO.H1
TCELL1:LONG.IO.H2TCELL0:LONG.IO.H2
TCELL1:LONG.IO.H3TCELL0:LONG.IO.H3

Bitstream

spartanxl LLH.IO.B bittile 0
BitFrame
1 0
10 ~INT:BUF.0.LONG.H3.1.LONG.H3 ~INT:BUF.1.LONG.H3.0.LONG.H3
9 - -
8 - -
7 ~INT:BUF.0.LONG.H4.1.LONG.H4 ~INT:BUF.1.LONG.H4.0.LONG.H4
6 ~INT:BUF.0.LONG.H5.1.LONG.H5 ~INT:BUF.1.LONG.H5.0.LONG.H5
5 ~INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0 ~INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0
4 ~INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1 ~INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1
3 ~INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2 ~INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2
2 ~INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3 ~INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3
1 - -
0 - -
INT:BUF.0.LONG.H3.1.LONG.H3 0.1.10
INT:BUF.0.LONG.H4.1.LONG.H4 0.1.7
INT:BUF.0.LONG.H5.1.LONG.H5 0.1.6
INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0 0.1.5
INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1 0.1.4
INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2 0.1.3
INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3 0.1.2
INT:BUF.1.LONG.H3.0.LONG.H3 0.0.10
INT:BUF.1.LONG.H4.0.LONG.H4 0.0.7
INT:BUF.1.LONG.H5.0.LONG.H5 0.0.6
INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0 0.0.5
INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1 0.0.4
INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2 0.0.3
INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3 0.0.2
inverted ~[0]

Tile LLH.IO.T

Cells: 2 IRIs: 0

Muxes

spartanxl LLH.IO.T muxes
DestinationSources
TCELL0:LONG.H0TCELL1:LONG.H0
TCELL0:LONG.H1TCELL1:LONG.H1
TCELL0:LONG.H2TCELL1:LONG.H2
TCELL0:LONG.IO.H0TCELL1:LONG.IO.H0
TCELL0:LONG.IO.H1TCELL1:LONG.IO.H1
TCELL0:LONG.IO.H2TCELL1:LONG.IO.H2
TCELL0:LONG.IO.H3TCELL1:LONG.IO.H3
TCELL1:LONG.H0TCELL0:LONG.H0
TCELL1:LONG.H1TCELL0:LONG.H1
TCELL1:LONG.H2TCELL0:LONG.H2
TCELL1:LONG.IO.H0TCELL0:LONG.IO.H0
TCELL1:LONG.IO.H1TCELL0:LONG.IO.H1
TCELL1:LONG.IO.H2TCELL0:LONG.IO.H2
TCELL1:LONG.IO.H3TCELL0:LONG.IO.H3

Bitstream

spartanxl LLH.IO.T bittile 0
BitFrame
1 0
5 ~INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3 ~INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3
4 ~INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2 ~INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2
3 - -
2 - -
1 ~INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1 ~INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1
0 ~INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0 ~INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0
spartanxl LLH.IO.T bittile 1
BitFrame
1 0
7 ~INT:BUF.0.LONG.H2.1.LONG.H2 -
6 ~INT:BUF.1.LONG.H2.0.LONG.H2 -
5 - ~INT:BUF.1.LONG.H1.0.LONG.H1
4 - ~INT:BUF.0.LONG.H0.1.LONG.H0
3 - ~INT:BUF.1.LONG.H0.0.LONG.H0
2 - ~INT:BUF.0.LONG.H1.1.LONG.H1
1 - -
0 - -
INT:BUF.0.LONG.H0.1.LONG.H0 1.0.4
INT:BUF.0.LONG.H1.1.LONG.H1 1.0.2
INT:BUF.0.LONG.H2.1.LONG.H2 1.1.7
INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0 0.0.0
INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1 0.1.1
INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2 0.1.4
INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3 0.1.5
INT:BUF.1.LONG.H0.0.LONG.H0 1.0.3
INT:BUF.1.LONG.H1.0.LONG.H1 1.0.5
INT:BUF.1.LONG.H2.0.LONG.H2 1.1.6
INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0 0.1.0
INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1 0.0.1
INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2 0.0.4
INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3 0.0.5
inverted ~[0]

Tile LLV.CLB

Cells: 2 IRIs: 0

Muxes

spartanxl LLV.CLB muxes
DestinationSources
TCELL0:LONG.V0TCELL1:LONG.V0
TCELL0:LONG.V1TCELL1:LONG.V1
TCELL0:LONG.V2TCELL1:LONG.V2
TCELL0:LONG.V3TCELL1:LONG.V3
TCELL0:LONG.V4TCELL1:LONG.V4
TCELL0:LONG.V5TCELL1:LONG.V5
TCELL1:LONG.V0TCELL0:LONG.V0
TCELL1:LONG.V1TCELL0:LONG.V1
TCELL1:LONG.V2TCELL0:LONG.V2
TCELL1:LONG.V3TCELL0:LONG.V3
TCELL1:LONG.V4TCELL0:LONG.V4
TCELL1:LONG.V5TCELL0:LONG.V5

Bel CLKH

spartanxl LLV.CLB bel CLKH
PinDirectionWires
O0outputTCELL0:GCLK0
O1outputTCELL0:GCLK1
O2outputTCELL0:GCLK2
O3outputTCELL0:GCLK3

Bel wires

spartanxl LLV.CLB bel wires
WirePins
TCELL0:GCLK0CLKH.O0
TCELL0:GCLK1CLKH.O1
TCELL0:GCLK2CLKH.O2
TCELL0:GCLK3CLKH.O3

Bitstream

spartanxl LLV.CLB bittile 0
BitFrame
35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 ~INT:BUF.1.LONG.V1.0.LONG.V1 ~INT:BUF.0.LONG.V1.1.LONG.V1 ~INT:BUF.1.LONG.V2.0.LONG.V2 ~INT:BUF.0.LONG.V2.1.LONG.V2 ~INT:BUF.1.LONG.V5.0.LONG.V5 ~INT:BUF.0.LONG.V5.1.LONG.V5 ~INT:BUF.1.LONG.V3.0.LONG.V3 ~INT:BUF.0.LONG.V3.1.LONG.V3 ~INT:BUF.1.LONG.V0.0.LONG.V0 ~INT:BUF.0.LONG.V0.1.LONG.V0 ~INT:BUF.1.LONG.V4.0.LONG.V4 ~INT:BUF.0.LONG.V4.1.LONG.V4 CLKH:MUX.O0[0] CLKH:MUX.O0[2] CLKH:MUX.O0[4] CLKH:MUX.O0[1] CLKH:MUX.O0[5] CLKH:MUX.O0[3] CLKH:MUX.O2[0] CLKH:MUX.O2[2] CLKH:MUX.O2[4] CLKH:MUX.O2[1] CLKH:MUX.O2[5] CLKH:MUX.O2[3] CLKH:MUX.O3[0] CLKH:MUX.O3[2] CLKH:MUX.O3[4] CLKH:MUX.O3[1] CLKH:MUX.O3[5] CLKH:MUX.O3[3] CLKH:MUX.O1[0] CLKH:MUX.O1[2] CLKH:MUX.O1[4] CLKH:MUX.O1[1] CLKH:MUX.O1[5] CLKH:MUX.O1[3]
0 - - - CLKH:ENABLE.I.UR.V CLKH:ENABLE.I.UL.H CLKH:ENABLE.I.LL.V CLKH:ENABLE.I.LR.V CLKH:ENABLE.I.UR.H CLKH:ENABLE.I.LL.H CLKH:ENABLE.I.UL.V CLKH:ENABLE.I.LR.H - - - - - - - - - - - - - - - - - - - - - - - - -
CLKH:ENABLE.I.LL.H 0.27.0
CLKH:ENABLE.I.LL.V 0.30.0
CLKH:ENABLE.I.LR.H 0.25.0
CLKH:ENABLE.I.LR.V 0.29.0
CLKH:ENABLE.I.UL.H 0.31.0
CLKH:ENABLE.I.UL.V 0.26.0
CLKH:ENABLE.I.UR.H 0.28.0
CLKH:ENABLE.I.UR.V 0.32.0
non-inverted [0]
CLKH:MUX.O0 0.19.1 0.21.1 0.18.1 0.22.1 0.20.1 0.23.1
CLKH:MUX.O1 0.1.1 0.3.1 0.0.1 0.4.1 0.2.1 0.5.1
CLKH:MUX.O2 0.13.1 0.15.1 0.12.1 0.16.1 0.14.1 0.17.1
CLKH:MUX.O3 0.7.1 0.9.1 0.6.1 0.10.1 0.8.1 0.11.1
I.LL.H 0 0 1 1 1 1
I.UL.V 0 1 1 0 1 1
I.UR.H 0 1 1 1 0 1
I.LR.V 0 1 1 1 1 0
I.LR.H 1 0 0 1 1 1
I.LL.V 1 1 0 0 1 1
I.UL.H 1 1 0 1 0 1
I.UR.V 1 1 0 1 1 0
NONE 1 1 1 1 1 1
INT:BUF.0.LONG.V0.1.LONG.V0 0.26.1
INT:BUF.0.LONG.V1.1.LONG.V1 0.34.1
INT:BUF.0.LONG.V2.1.LONG.V2 0.32.1
INT:BUF.0.LONG.V3.1.LONG.V3 0.28.1
INT:BUF.0.LONG.V4.1.LONG.V4 0.24.1
INT:BUF.0.LONG.V5.1.LONG.V5 0.30.1
INT:BUF.1.LONG.V0.0.LONG.V0 0.27.1
INT:BUF.1.LONG.V1.0.LONG.V1 0.35.1
INT:BUF.1.LONG.V2.0.LONG.V2 0.33.1
INT:BUF.1.LONG.V3.0.LONG.V3 0.29.1
INT:BUF.1.LONG.V4.0.LONG.V4 0.25.1
INT:BUF.1.LONG.V5.0.LONG.V5 0.31.1
inverted ~[0]

Tile LLV.IO.L

Cells: 2 IRIs: 0

Muxes

spartanxl LLV.IO.L muxes
DestinationSources
TCELL0:LONG.IO.V0TCELL1:LONG.IO.V0
TCELL0:LONG.IO.V1TCELL1:LONG.IO.V1
TCELL0:LONG.IO.V2TCELL1:LONG.IO.V2
TCELL0:LONG.IO.V3TCELL1:LONG.IO.V3
TCELL1:LONG.IO.V0TCELL0:LONG.IO.V0
TCELL1:LONG.IO.V1TCELL0:LONG.IO.V1
TCELL1:LONG.IO.V2TCELL0:LONG.IO.V2
TCELL1:LONG.IO.V3TCELL0:LONG.IO.V3

Bel CLKH

spartanxl LLV.IO.L bel CLKH
PinDirectionWires
O0outputTCELL0:GCLK0
O1outputTCELL0:GCLK1
O2outputTCELL0:GCLK2
O3outputTCELL0:GCLK3

Bel wires

spartanxl LLV.IO.L bel wires
WirePins
TCELL0:GCLK0CLKH.O0
TCELL0:GCLK1CLKH.O1
TCELL0:GCLK2CLKH.O2
TCELL0:GCLK3CLKH.O3

Bitstream

spartanxl LLV.IO.L bittile 0
BitFrame
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 CLKH:MUX.O3[0] CLKH:MUX.O3[2] CLKH:MUX.O3[5] CLKH:MUX.O3[3] CLKH:MUX.O1[0] CLKH:MUX.O1[2] CLKH:MUX.O1[5] CLKH:MUX.O1[3] CLKH:MUX.O0[0] CLKH:MUX.O0[2] CLKH:MUX.O0[5] CLKH:MUX.O0[3] CLKH:MUX.O2[0] CLKH:MUX.O2[2] CLKH:MUX.O2[5] CLKH:MUX.O2[3] ~INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 ~INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 ~INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 ~INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 ~INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 ~INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 ~INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 ~INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2
0 CLKH:ENABLE.I.LR.V CLKH:ENABLE.I.UR.H CLKH:MUX.O3[1] CLKH:MUX.O3[4] CLKH:ENABLE.I.LL.H CLKH:ENABLE.I.UL.V CLKH:MUX.O1[1] CLKH:MUX.O1[4] CLKH:ENABLE.I.LR.H CLKH:ENABLE.I.LL.V CLKH:MUX.O0[1] CLKH:MUX.O0[4] CLKH:ENABLE.I.UR.V CLKH:ENABLE.I.UL.H CLKH:MUX.O2[1] CLKH:MUX.O2[4] - - - - - - - -
CLKH:ENABLE.I.LL.H 0.19.0
CLKH:ENABLE.I.LL.V 0.14.0
CLKH:ENABLE.I.LR.H 0.15.0
CLKH:ENABLE.I.LR.V 0.23.0
CLKH:ENABLE.I.UL.H 0.10.0
CLKH:ENABLE.I.UL.V 0.18.0
CLKH:ENABLE.I.UR.H 0.22.0
CLKH:ENABLE.I.UR.V 0.11.0
non-inverted [0]
CLKH:MUX.O0 0.13.1 0.12.0 0.12.1 0.14.1 0.13.0 0.15.1
CLKH:MUX.O1 0.17.1 0.16.0 0.16.1 0.18.1 0.17.0 0.19.1
CLKH:MUX.O2 0.9.1 0.8.0 0.8.1 0.10.1 0.9.0 0.11.1
CLKH:MUX.O3 0.21.1 0.20.0 0.20.1 0.22.1 0.21.0 0.23.1
I.LL.H 0 0 1 1 1 1
I.UL.V 0 1 1 0 1 1
I.UR.H 0 1 1 1 0 1
I.LR.V 0 1 1 1 1 0
I.LR.H 1 0 0 1 1 1
I.LL.V 1 1 0 0 1 1
I.UL.H 1 1 0 1 0 1
I.UR.V 1 1 0 1 1 0
NONE 1 1 1 1 1 1
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 0.2.1
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 0.6.1
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 0.0.1
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 0.4.1
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 0.3.1
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 0.7.1
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 0.1.1
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 0.5.1
inverted ~[0]

Tile LLV.IO.R

Cells: 2 IRIs: 0

Muxes

spartanxl LLV.IO.R muxes
DestinationSources
TCELL0:LONG.V0TCELL1:LONG.V0
TCELL0:LONG.V1TCELL1:LONG.V1
TCELL0:LONG.V2TCELL1:LONG.V2
TCELL0:LONG.V3TCELL1:LONG.V3
TCELL0:LONG.V4TCELL1:LONG.V4
TCELL0:LONG.V5TCELL1:LONG.V5
TCELL0:LONG.IO.V0TCELL1:LONG.IO.V0
TCELL0:LONG.IO.V1TCELL1:LONG.IO.V1
TCELL0:LONG.IO.V2TCELL1:LONG.IO.V2
TCELL0:LONG.IO.V3TCELL1:LONG.IO.V3
TCELL1:LONG.V0TCELL0:LONG.V0
TCELL1:LONG.V1TCELL0:LONG.V1
TCELL1:LONG.V2TCELL0:LONG.V2
TCELL1:LONG.V3TCELL0:LONG.V3
TCELL1:LONG.V4TCELL0:LONG.V4
TCELL1:LONG.V5TCELL0:LONG.V5
TCELL1:LONG.IO.V0TCELL0:LONG.IO.V0
TCELL1:LONG.IO.V1TCELL0:LONG.IO.V1
TCELL1:LONG.IO.V2TCELL0:LONG.IO.V2
TCELL1:LONG.IO.V3TCELL0:LONG.IO.V3

Bel CLKH

spartanxl LLV.IO.R bel CLKH
PinDirectionWires
O0outputTCELL0:GCLK0
O1outputTCELL0:GCLK1
O2outputTCELL0:GCLK2
O3outputTCELL0:GCLK3

Bel wires

spartanxl LLV.IO.R bel wires
WirePins
TCELL0:GCLK0CLKH.O0
TCELL0:GCLK1CLKH.O1
TCELL0:GCLK2CLKH.O2
TCELL0:GCLK3CLKH.O3

Bitstream

spartanxl LLV.IO.R bittile 0
BitFrame
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 ~INT:BUF.1.LONG.V1.0.LONG.V1 ~INT:BUF.0.LONG.V1.1.LONG.V1 ~INT:BUF.1.LONG.V2.0.LONG.V2 ~INT:BUF.0.LONG.V2.1.LONG.V2 ~INT:BUF.1.LONG.V5.0.LONG.V5 ~INT:BUF.0.LONG.V5.1.LONG.V5 ~INT:BUF.1.LONG.V3.0.LONG.V3 ~INT:BUF.0.LONG.V3.1.LONG.V3 ~INT:BUF.1.LONG.V0.0.LONG.V0 ~INT:BUF.0.LONG.V0.1.LONG.V0 ~INT:BUF.1.LONG.V4.0.LONG.V4 ~INT:BUF.0.LONG.V4.1.LONG.V4 ~INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 ~INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 ~INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 ~INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 ~INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 ~INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 ~INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 ~INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 CLKH:MUX.O2[0] CLKH:MUX.O2[2] CLKH:MUX.O2[5] CLKH:MUX.O2[3] CLKH:MUX.O0[0] CLKH:MUX.O0[2] CLKH:MUX.O0[5] CLKH:MUX.O0[3] CLKH:MUX.O3[0] CLKH:MUX.O3[2] CLKH:MUX.O3[5] CLKH:MUX.O3[3] CLKH:MUX.O1[0] CLKH:MUX.O1[2] CLKH:MUX.O1[5] CLKH:MUX.O1[3] - - - - -
0 - - - - - - - - - - - - - - - - - - - ~MISC:TLC CLKH:ENABLE.I.LR.V CLKH:ENABLE.I.UR.H CLKH:MUX.O2[1] CLKH:MUX.O2[4] CLKH:ENABLE.I.LL.H CLKH:ENABLE.I.UL.V CLKH:MUX.O0[1] CLKH:MUX.O0[4] CLKH:ENABLE.I.LR.H CLKH:ENABLE.I.LL.V CLKH:MUX.O3[1] CLKH:MUX.O3[4] CLKH:ENABLE.I.UL.H CLKH:ENABLE.I.UR.V CLKH:MUX.O1[1] CLKH:MUX.O1[4] - - - - -
CLKH:ENABLE.I.LL.H 0.16.0
CLKH:ENABLE.I.LL.V 0.11.0
CLKH:ENABLE.I.LR.H 0.12.0
CLKH:ENABLE.I.LR.V 0.20.0
CLKH:ENABLE.I.UL.H 0.8.0
CLKH:ENABLE.I.UL.V 0.15.0
CLKH:ENABLE.I.UR.H 0.19.0
CLKH:ENABLE.I.UR.V 0.7.0
non-inverted [0]
CLKH:MUX.O0 0.14.1 0.13.0 0.13.1 0.15.1 0.14.0 0.16.1
CLKH:MUX.O1 0.6.1 0.5.0 0.5.1 0.7.1 0.6.0 0.8.1
CLKH:MUX.O2 0.18.1 0.17.0 0.17.1 0.19.1 0.18.0 0.20.1
CLKH:MUX.O3 0.10.1 0.9.0 0.9.1 0.11.1 0.10.0 0.12.1
I.LL.H 0 0 1 1 1 1
I.UL.V 0 1 1 0 1 1
I.UR.H 0 1 1 1 0 1
I.LR.V 0 1 1 1 1 0
I.LR.H 1 0 0 1 1 1
I.LL.V 1 1 0 0 1 1
I.UL.H 1 1 0 1 0 1
I.UR.V 1 1 0 1 1 0
NONE 1 1 1 1 1 1
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 0.25.1
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 0.21.1
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 0.27.1
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 0.23.1
INT:BUF.0.LONG.V0.1.LONG.V0 0.31.1
INT:BUF.0.LONG.V1.1.LONG.V1 0.39.1
INT:BUF.0.LONG.V2.1.LONG.V2 0.37.1
INT:BUF.0.LONG.V3.1.LONG.V3 0.33.1
INT:BUF.0.LONG.V4.1.LONG.V4 0.29.1
INT:BUF.0.LONG.V5.1.LONG.V5 0.35.1
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 0.26.1
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 0.22.1
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 0.28.1
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 0.24.1
INT:BUF.1.LONG.V0.0.LONG.V0 0.32.1
INT:BUF.1.LONG.V1.0.LONG.V1 0.40.1
INT:BUF.1.LONG.V2.0.LONG.V2 0.38.1
INT:BUF.1.LONG.V3.0.LONG.V3 0.34.1
INT:BUF.1.LONG.V4.0.LONG.V4 0.30.1
INT:BUF.1.LONG.V5.0.LONG.V5 0.36.1
MISC:TLC 0.21.0
inverted ~[0]