Keyboard shortcuts

Press ← or → to navigate between chapters

Press ? to show this help

Press Esc to hide this help

Splitters

Tile LLH.CLB

Cells: 2

Bel TBUF_SPLITTER0

spartanxl LLH.CLB bel TBUF_SPLITTER0
PinDirectionWires
Lin-outCELL0.LONG.H2
Rin-outCELL1.LONG.H2

Bel TBUF_SPLITTER1

spartanxl LLH.CLB bel TBUF_SPLITTER1
PinDirectionWires
Lin-outCELL0.LONG.H3
Rin-outCELL1.LONG.H3

Switchbox LLH

spartanxl LLH.CLB switchbox LLH
DestinationSourceKind
CELL0.LONG.H0CELL1.LONG.H0buffer
CELL0.LONG.H1CELL1.LONG.H1buffer
CELL0.LONG.H4CELL1.LONG.H4buffer
CELL0.LONG.H5CELL1.LONG.H5buffer
CELL1.LONG.H0CELL0.LONG.H0buffer
CELL1.LONG.H1CELL0.LONG.H1buffer
CELL1.LONG.H4CELL0.LONG.H4buffer
CELL1.LONG.H5CELL0.LONG.H5buffer

Bel wires

spartanxl LLH.CLB bel wires
WirePins
CELL0.LONG.H2TBUF_SPLITTER0.L
CELL0.LONG.H3TBUF_SPLITTER1.L
CELL1.LONG.H2TBUF_SPLITTER0.R
CELL1.LONG.H3TBUF_SPLITTER1.R

Bitstream

spartanxl LLH.CLB rect R0
BitFrame
F1 F0
B9 - ~TBUF_SPLITTER1:BUF_W
B8 - ~TBUF_SPLITTER1:BUF_E
B7 - -
B6 - -
B5 - -
B4 - -
B3 ~TBUF_SPLITTER1:PASS -
B2 - -
B1 ~LLH:BUF.0.LONG.H4.1.LONG.H4 ~LLH:BUF.0.LONG.H5.1.LONG.H5
B0 ~LLH:BUF.1.LONG.H4.0.LONG.H4 ~LLH:BUF.1.LONG.H5.0.LONG.H5
spartanxl LLH.CLB rect R1
BitFrame
F1 F0
B7 ~TBUF_SPLITTER0:BUF_W -
B6 ~TBUF_SPLITTER0:BUF_E -
B5 - ~LLH:BUF.1.LONG.H1.0.LONG.H1
B4 ~TBUF_SPLITTER0:PASS ~LLH:BUF.0.LONG.H0.1.LONG.H0
B3 - ~LLH:BUF.1.LONG.H0.0.LONG.H0
B2 - ~LLH:BUF.0.LONG.H1.1.LONG.H1
B1 - -
B0 - -
LLH:BUF.0.LONG.H0.1.LONG.H0 1.F0.B4
LLH:BUF.0.LONG.H1.1.LONG.H1 1.F0.B2
LLH:BUF.0.LONG.H4.1.LONG.H4 0.F1.B1
LLH:BUF.0.LONG.H5.1.LONG.H5 0.F0.B1
LLH:BUF.1.LONG.H0.0.LONG.H0 1.F0.B3
LLH:BUF.1.LONG.H1.0.LONG.H1 1.F0.B5
LLH:BUF.1.LONG.H4.0.LONG.H4 0.F1.B0
LLH:BUF.1.LONG.H5.0.LONG.H5 0.F0.B0
TBUF_SPLITTER0:BUF_E 1.F1.B6
TBUF_SPLITTER0:BUF_W 1.F1.B7
TBUF_SPLITTER0:PASS 1.F1.B4
TBUF_SPLITTER1:BUF_E 0.F0.B8
TBUF_SPLITTER1:BUF_W 0.F0.B9
TBUF_SPLITTER1:PASS 0.F1.B3
inverted ~[0]

Tile LLH.CLB.B

Cells: 2

Bel TBUF_SPLITTER0

spartanxl LLH.CLB.B bel TBUF_SPLITTER0
PinDirectionWires
Lin-outCELL0.LONG.H2
Rin-outCELL1.LONG.H2

Bel TBUF_SPLITTER1

spartanxl LLH.CLB.B bel TBUF_SPLITTER1
PinDirectionWires
Lin-outCELL0.LONG.H3
Rin-outCELL1.LONG.H3

Switchbox LLH

spartanxl LLH.CLB.B switchbox LLH
DestinationSourceKind
CELL0.LONG.H0CELL1.LONG.H0buffer
CELL0.LONG.H1CELL1.LONG.H1buffer
CELL0.LONG.H4CELL1.LONG.H4buffer
CELL0.LONG.H5CELL1.LONG.H5buffer
CELL1.LONG.H0CELL0.LONG.H0buffer
CELL1.LONG.H1CELL0.LONG.H1buffer
CELL1.LONG.H4CELL0.LONG.H4buffer
CELL1.LONG.H5CELL0.LONG.H5buffer

Bel wires

spartanxl LLH.CLB.B bel wires
WirePins
CELL0.LONG.H2TBUF_SPLITTER0.L
CELL0.LONG.H3TBUF_SPLITTER1.L
CELL1.LONG.H2TBUF_SPLITTER0.R
CELL1.LONG.H3TBUF_SPLITTER1.R

Bitstream

spartanxl LLH.CLB.B rect R0
BitFrame
F1 F0
B9 - ~TBUF_SPLITTER1:BUF_W
B8 - ~TBUF_SPLITTER1:BUF_E
B7 - -
B6 - -
B5 - -
B4 - -
B3 ~TBUF_SPLITTER1:PASS -
B2 - -
B1 ~LLH:BUF.0.LONG.H4.1.LONG.H4 ~LLH:BUF.0.LONG.H5.1.LONG.H5
B0 ~LLH:BUF.1.LONG.H4.0.LONG.H4 ~LLH:BUF.1.LONG.H5.0.LONG.H5
spartanxl LLH.CLB.B rect R1
BitFrame
F1 F0
B12 ~LLH:BUF.0.LONG.H0.1.LONG.H0 ~LLH:BUF.1.LONG.H0.0.LONG.H0
B11 ~LLH:BUF.0.LONG.H1.1.LONG.H1 ~LLH:BUF.1.LONG.H1.0.LONG.H1
B10 - -
B9 - -
B8 ~TBUF_SPLITTER0:PASS ~TBUF_SPLITTER0:BUF_W
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - -
B0 ~TBUF_SPLITTER0:BUF_E -
LLH:BUF.0.LONG.H0.1.LONG.H0 1.F1.B12
LLH:BUF.0.LONG.H1.1.LONG.H1 1.F1.B11
LLH:BUF.0.LONG.H4.1.LONG.H4 0.F1.B1
LLH:BUF.0.LONG.H5.1.LONG.H5 0.F0.B1
LLH:BUF.1.LONG.H0.0.LONG.H0 1.F0.B12
LLH:BUF.1.LONG.H1.0.LONG.H1 1.F0.B11
LLH:BUF.1.LONG.H4.0.LONG.H4 0.F1.B0
LLH:BUF.1.LONG.H5.0.LONG.H5 0.F0.B0
TBUF_SPLITTER0:BUF_E 1.F1.B0
TBUF_SPLITTER0:BUF_W 1.F0.B8
TBUF_SPLITTER0:PASS 1.F1.B8
TBUF_SPLITTER1:BUF_E 0.F0.B8
TBUF_SPLITTER1:BUF_W 0.F0.B9
TBUF_SPLITTER1:PASS 0.F1.B3
inverted ~[0]

Tile LLH.IO.B

Cells: 2

Switchbox LLH

spartanxl LLH.IO.B switchbox LLH
DestinationSourceKind
CELL0.LONG.H3CELL1.LONG.H3buffer
CELL0.LONG.H4CELL1.LONG.H4buffer
CELL0.LONG.H5CELL1.LONG.H5buffer
CELL0.LONG.IO.H0CELL1.LONG.IO.H0buffer
CELL0.LONG.IO.H1CELL1.LONG.IO.H1buffer
CELL0.LONG.IO.H2CELL1.LONG.IO.H2buffer
CELL0.LONG.IO.H3CELL1.LONG.IO.H3buffer
CELL1.LONG.H3CELL0.LONG.H3buffer
CELL1.LONG.H4CELL0.LONG.H4buffer
CELL1.LONG.H5CELL0.LONG.H5buffer
CELL1.LONG.IO.H0CELL0.LONG.IO.H0buffer
CELL1.LONG.IO.H1CELL0.LONG.IO.H1buffer
CELL1.LONG.IO.H2CELL0.LONG.IO.H2buffer
CELL1.LONG.IO.H3CELL0.LONG.IO.H3buffer

Bitstream

spartanxl LLH.IO.B rect R0
BitFrame
F1 F0
B10 ~LLH:BUF.0.LONG.H3.1.LONG.H3 ~LLH:BUF.1.LONG.H3.0.LONG.H3
B9 - -
B8 - -
B7 ~LLH:BUF.0.LONG.H4.1.LONG.H4 ~LLH:BUF.1.LONG.H4.0.LONG.H4
B6 ~LLH:BUF.0.LONG.H5.1.LONG.H5 ~LLH:BUF.1.LONG.H5.0.LONG.H5
B5 ~LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0 ~LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0
B4 ~LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1 ~LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1
B3 ~LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2 ~LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2
B2 ~LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3 ~LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3
B1 - -
B0 - -
LLH:BUF.0.LONG.H3.1.LONG.H3 0.F1.B10
LLH:BUF.0.LONG.H4.1.LONG.H4 0.F1.B7
LLH:BUF.0.LONG.H5.1.LONG.H5 0.F1.B6
LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0 0.F1.B5
LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1 0.F1.B4
LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2 0.F1.B3
LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3 0.F1.B2
LLH:BUF.1.LONG.H3.0.LONG.H3 0.F0.B10
LLH:BUF.1.LONG.H4.0.LONG.H4 0.F0.B7
LLH:BUF.1.LONG.H5.0.LONG.H5 0.F0.B6
LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0 0.F0.B5
LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1 0.F0.B4
LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2 0.F0.B3
LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3 0.F0.B2
inverted ~[0]

Tile LLH.IO.T

Cells: 2

Switchbox LLH

spartanxl LLH.IO.T switchbox LLH
DestinationSourceKind
CELL0.LONG.H0CELL1.LONG.H0buffer
CELL0.LONG.H1CELL1.LONG.H1buffer
CELL0.LONG.H2CELL1.LONG.H2buffer
CELL0.LONG.IO.H0CELL1.LONG.IO.H0buffer
CELL0.LONG.IO.H1CELL1.LONG.IO.H1buffer
CELL0.LONG.IO.H2CELL1.LONG.IO.H2buffer
CELL0.LONG.IO.H3CELL1.LONG.IO.H3buffer
CELL1.LONG.H0CELL0.LONG.H0buffer
CELL1.LONG.H1CELL0.LONG.H1buffer
CELL1.LONG.H2CELL0.LONG.H2buffer
CELL1.LONG.IO.H0CELL0.LONG.IO.H0buffer
CELL1.LONG.IO.H1CELL0.LONG.IO.H1buffer
CELL1.LONG.IO.H2CELL0.LONG.IO.H2buffer
CELL1.LONG.IO.H3CELL0.LONG.IO.H3buffer

Bitstream

spartanxl LLH.IO.T rect R0
BitFrame
F1 F0
B5 ~LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3 ~LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3
B4 ~LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2 ~LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2
B3 - -
B2 - -
B1 ~LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1 ~LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1
B0 ~LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0 ~LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0
spartanxl LLH.IO.T rect R1
BitFrame
F1 F0
B7 ~LLH:BUF.0.LONG.H2.1.LONG.H2 -
B6 ~LLH:BUF.1.LONG.H2.0.LONG.H2 -
B5 - ~LLH:BUF.1.LONG.H1.0.LONG.H1
B4 - ~LLH:BUF.0.LONG.H0.1.LONG.H0
B3 - ~LLH:BUF.1.LONG.H0.0.LONG.H0
B2 - ~LLH:BUF.0.LONG.H1.1.LONG.H1
B1 - -
B0 - -
LLH:BUF.0.LONG.H0.1.LONG.H0 1.F0.B4
LLH:BUF.0.LONG.H1.1.LONG.H1 1.F0.B2
LLH:BUF.0.LONG.H2.1.LONG.H2 1.F1.B7
LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0 0.F0.B0
LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1 0.F1.B1
LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2 0.F1.B4
LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3 0.F1.B5
LLH:BUF.1.LONG.H0.0.LONG.H0 1.F0.B3
LLH:BUF.1.LONG.H1.0.LONG.H1 1.F0.B5
LLH:BUF.1.LONG.H2.0.LONG.H2 1.F1.B6
LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0 0.F1.B0
LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1 0.F0.B1
LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2 0.F0.B4
LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3 0.F0.B5
inverted ~[0]

Tile LLV.CLB

Cells: 2

Switchbox LLV

spartanxl LLV.CLB switchbox LLV
DestinationSourceKind
CELL0.LONG.V0CELL1.LONG.V0buffer
CELL0.LONG.V1CELL1.LONG.V1buffer
CELL0.LONG.V2CELL1.LONG.V2buffer
CELL0.LONG.V3CELL1.LONG.V3buffer
CELL0.LONG.V4CELL1.LONG.V4buffer
CELL0.LONG.V5CELL1.LONG.V5buffer
CELL1.LONG.V0CELL0.LONG.V0buffer
CELL1.LONG.V1CELL0.LONG.V1buffer
CELL1.LONG.V2CELL0.LONG.V2buffer
CELL1.LONG.V3CELL0.LONG.V3buffer
CELL1.LONG.V4CELL0.LONG.V4buffer
CELL1.LONG.V5CELL0.LONG.V5buffer

Bel CLKH

spartanxl LLV.CLB bel CLKH
PinDirectionWires
O0outputCELL0.GCLK0
O1outputCELL0.GCLK1
O2outputCELL0.GCLK2
O3outputCELL0.GCLK3

Bel wires

spartanxl LLV.CLB bel wires
WirePins
CELL0.GCLK0CLKH.O0
CELL0.GCLK1CLKH.O1
CELL0.GCLK2CLKH.O2
CELL0.GCLK3CLKH.O3

Bitstream

spartanxl LLV.CLB rect R0
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B1 ~LLV:BUF.1.LONG.V1.0.LONG.V1 ~LLV:BUF.0.LONG.V1.1.LONG.V1 ~LLV:BUF.1.LONG.V2.0.LONG.V2 ~LLV:BUF.0.LONG.V2.1.LONG.V2 ~LLV:BUF.1.LONG.V5.0.LONG.V5 ~LLV:BUF.0.LONG.V5.1.LONG.V5 ~LLV:BUF.1.LONG.V3.0.LONG.V3 ~LLV:BUF.0.LONG.V3.1.LONG.V3 ~LLV:BUF.1.LONG.V0.0.LONG.V0 ~LLV:BUF.0.LONG.V0.1.LONG.V0 ~LLV:BUF.1.LONG.V4.0.LONG.V4 ~LLV:BUF.0.LONG.V4.1.LONG.V4 CLKH:MUX.O0[0] CLKH:MUX.O0[2] CLKH:MUX.O0[4] CLKH:MUX.O0[1] CLKH:MUX.O0[5] CLKH:MUX.O0[3] CLKH:MUX.O2[0] CLKH:MUX.O2[2] CLKH:MUX.O2[4] CLKH:MUX.O2[1] CLKH:MUX.O2[5] CLKH:MUX.O2[3] CLKH:MUX.O3[0] CLKH:MUX.O3[2] CLKH:MUX.O3[4] CLKH:MUX.O3[1] CLKH:MUX.O3[5] CLKH:MUX.O3[3] CLKH:MUX.O1[0] CLKH:MUX.O1[2] CLKH:MUX.O1[4] CLKH:MUX.O1[1] CLKH:MUX.O1[5] CLKH:MUX.O1[3]
B0 - - - CLKH:ENABLE.I.UR.V CLKH:ENABLE.I.UL.H CLKH:ENABLE.I.LL.V CLKH:ENABLE.I.LR.V CLKH:ENABLE.I.UR.H CLKH:ENABLE.I.LL.H CLKH:ENABLE.I.UL.V CLKH:ENABLE.I.LR.H - - - - - - - - - - - - - - - - - - - - - - - - -
CLKH:ENABLE.I.LL.H 0.F27.B0
CLKH:ENABLE.I.LL.V 0.F30.B0
CLKH:ENABLE.I.LR.H 0.F25.B0
CLKH:ENABLE.I.LR.V 0.F29.B0
CLKH:ENABLE.I.UL.H 0.F31.B0
CLKH:ENABLE.I.UL.V 0.F26.B0
CLKH:ENABLE.I.UR.H 0.F28.B0
CLKH:ENABLE.I.UR.V 0.F32.B0
non-inverted [0]
CLKH:MUX.O0 0.F19.B1 0.F21.B1 0.F18.B1 0.F22.B1 0.F20.B1 0.F23.B1
CLKH:MUX.O1 0.F1.B1 0.F3.B1 0.F0.B1 0.F4.B1 0.F2.B1 0.F5.B1
CLKH:MUX.O2 0.F13.B1 0.F15.B1 0.F12.B1 0.F16.B1 0.F14.B1 0.F17.B1
CLKH:MUX.O3 0.F7.B1 0.F9.B1 0.F6.B1 0.F10.B1 0.F8.B1 0.F11.B1
I.LL.H 0 0 1 1 1 1
I.UL.V 0 1 1 0 1 1
I.UR.H 0 1 1 1 0 1
I.LR.V 0 1 1 1 1 0
I.LR.H 1 0 0 1 1 1
I.LL.V 1 1 0 0 1 1
I.UL.H 1 1 0 1 0 1
I.UR.V 1 1 0 1 1 0
NONE 1 1 1 1 1 1
LLV:BUF.0.LONG.V0.1.LONG.V0 0.F26.B1
LLV:BUF.0.LONG.V1.1.LONG.V1 0.F34.B1
LLV:BUF.0.LONG.V2.1.LONG.V2 0.F32.B1
LLV:BUF.0.LONG.V3.1.LONG.V3 0.F28.B1
LLV:BUF.0.LONG.V4.1.LONG.V4 0.F24.B1
LLV:BUF.0.LONG.V5.1.LONG.V5 0.F30.B1
LLV:BUF.1.LONG.V0.0.LONG.V0 0.F27.B1
LLV:BUF.1.LONG.V1.0.LONG.V1 0.F35.B1
LLV:BUF.1.LONG.V2.0.LONG.V2 0.F33.B1
LLV:BUF.1.LONG.V3.0.LONG.V3 0.F29.B1
LLV:BUF.1.LONG.V4.0.LONG.V4 0.F25.B1
LLV:BUF.1.LONG.V5.0.LONG.V5 0.F31.B1
inverted ~[0]

Tile LLV.IO.L

Cells: 2

Switchbox LLV

spartanxl LLV.IO.L switchbox LLV
DestinationSourceKind
CELL0.LONG.IO.V0CELL1.LONG.IO.V0buffer
CELL0.LONG.IO.V1CELL1.LONG.IO.V1buffer
CELL0.LONG.IO.V2CELL1.LONG.IO.V2buffer
CELL0.LONG.IO.V3CELL1.LONG.IO.V3buffer
CELL1.LONG.IO.V0CELL0.LONG.IO.V0buffer
CELL1.LONG.IO.V1CELL0.LONG.IO.V1buffer
CELL1.LONG.IO.V2CELL0.LONG.IO.V2buffer
CELL1.LONG.IO.V3CELL0.LONG.IO.V3buffer

Bel CLKH

spartanxl LLV.IO.L bel CLKH
PinDirectionWires
O0outputCELL0.GCLK0
O1outputCELL0.GCLK1
O2outputCELL0.GCLK2
O3outputCELL0.GCLK3

Bel wires

spartanxl LLV.IO.L bel wires
WirePins
CELL0.GCLK0CLKH.O0
CELL0.GCLK1CLKH.O1
CELL0.GCLK2CLKH.O2
CELL0.GCLK3CLKH.O3

Bitstream

spartanxl LLV.IO.L rect R0
BitFrame
F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B1 CLKH:MUX.O3[0] CLKH:MUX.O3[2] CLKH:MUX.O3[5] CLKH:MUX.O3[3] CLKH:MUX.O1[0] CLKH:MUX.O1[2] CLKH:MUX.O1[5] CLKH:MUX.O1[3] CLKH:MUX.O0[0] CLKH:MUX.O0[2] CLKH:MUX.O0[5] CLKH:MUX.O0[3] CLKH:MUX.O2[0] CLKH:MUX.O2[2] CLKH:MUX.O2[5] CLKH:MUX.O2[3] ~LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1 ~LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1 ~LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3 ~LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3 ~LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0 ~LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0 ~LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2 ~LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2
B0 CLKH:ENABLE.I.LR.V CLKH:ENABLE.I.UR.H CLKH:MUX.O3[1] CLKH:MUX.O3[4] CLKH:ENABLE.I.LL.H CLKH:ENABLE.I.UL.V CLKH:MUX.O1[1] CLKH:MUX.O1[4] CLKH:ENABLE.I.LR.H CLKH:ENABLE.I.LL.V CLKH:MUX.O0[1] CLKH:MUX.O0[4] CLKH:ENABLE.I.UR.V CLKH:ENABLE.I.UL.H CLKH:MUX.O2[1] CLKH:MUX.O2[4] - - - - - - - -
CLKH:ENABLE.I.LL.H 0.F19.B0
CLKH:ENABLE.I.LL.V 0.F14.B0
CLKH:ENABLE.I.LR.H 0.F15.B0
CLKH:ENABLE.I.LR.V 0.F23.B0
CLKH:ENABLE.I.UL.H 0.F10.B0
CLKH:ENABLE.I.UL.V 0.F18.B0
CLKH:ENABLE.I.UR.H 0.F22.B0
CLKH:ENABLE.I.UR.V 0.F11.B0
non-inverted [0]
CLKH:MUX.O0 0.F13.B1 0.F12.B0 0.F12.B1 0.F14.B1 0.F13.B0 0.F15.B1
CLKH:MUX.O1 0.F17.B1 0.F16.B0 0.F16.B1 0.F18.B1 0.F17.B0 0.F19.B1
CLKH:MUX.O2 0.F9.B1 0.F8.B0 0.F8.B1 0.F10.B1 0.F9.B0 0.F11.B1
CLKH:MUX.O3 0.F21.B1 0.F20.B0 0.F20.B1 0.F22.B1 0.F21.B0 0.F23.B1
I.LL.H 0 0 1 1 1 1
I.UL.V 0 1 1 0 1 1
I.UR.H 0 1 1 1 0 1
I.LR.V 0 1 1 1 1 0
I.LR.H 1 0 0 1 1 1
I.LL.V 1 1 0 0 1 1
I.UL.H 1 1 0 1 0 1
I.UR.V 1 1 0 1 1 0
NONE 1 1 1 1 1 1
LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0 0.F2.B1
LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1 0.F6.B1
LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2 0.F0.B1
LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3 0.F4.B1
LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0 0.F3.B1
LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1 0.F7.B1
LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2 0.F1.B1
LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3 0.F5.B1
inverted ~[0]

Tile LLV.IO.R

Cells: 2

Switchbox LLV

spartanxl LLV.IO.R switchbox LLV
DestinationSourceKind
CELL0.LONG.V0CELL1.LONG.V0buffer
CELL0.LONG.V1CELL1.LONG.V1buffer
CELL0.LONG.V2CELL1.LONG.V2buffer
CELL0.LONG.V3CELL1.LONG.V3buffer
CELL0.LONG.V4CELL1.LONG.V4buffer
CELL0.LONG.V5CELL1.LONG.V5buffer
CELL0.LONG.IO.V0CELL1.LONG.IO.V0buffer
CELL0.LONG.IO.V1CELL1.LONG.IO.V1buffer
CELL0.LONG.IO.V2CELL1.LONG.IO.V2buffer
CELL0.LONG.IO.V3CELL1.LONG.IO.V3buffer
CELL1.LONG.V0CELL0.LONG.V0buffer
CELL1.LONG.V1CELL0.LONG.V1buffer
CELL1.LONG.V2CELL0.LONG.V2buffer
CELL1.LONG.V3CELL0.LONG.V3buffer
CELL1.LONG.V4CELL0.LONG.V4buffer
CELL1.LONG.V5CELL0.LONG.V5buffer
CELL1.LONG.IO.V0CELL0.LONG.IO.V0buffer
CELL1.LONG.IO.V1CELL0.LONG.IO.V1buffer
CELL1.LONG.IO.V2CELL0.LONG.IO.V2buffer
CELL1.LONG.IO.V3CELL0.LONG.IO.V3buffer

Bel CLKH

spartanxl LLV.IO.R bel CLKH
PinDirectionWires
O0outputCELL0.GCLK0
O1outputCELL0.GCLK1
O2outputCELL0.GCLK2
O3outputCELL0.GCLK3

Bel wires

spartanxl LLV.IO.R bel wires
WirePins
CELL0.GCLK0CLKH.O0
CELL0.GCLK1CLKH.O1
CELL0.GCLK2CLKH.O2
CELL0.GCLK3CLKH.O3

Bitstream

spartanxl LLV.IO.R rect R0
BitFrame
F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B1 ~LLV:BUF.1.LONG.V1.0.LONG.V1 ~LLV:BUF.0.LONG.V1.1.LONG.V1 ~LLV:BUF.1.LONG.V2.0.LONG.V2 ~LLV:BUF.0.LONG.V2.1.LONG.V2 ~LLV:BUF.1.LONG.V5.0.LONG.V5 ~LLV:BUF.0.LONG.V5.1.LONG.V5 ~LLV:BUF.1.LONG.V3.0.LONG.V3 ~LLV:BUF.0.LONG.V3.1.LONG.V3 ~LLV:BUF.1.LONG.V0.0.LONG.V0 ~LLV:BUF.0.LONG.V0.1.LONG.V0 ~LLV:BUF.1.LONG.V4.0.LONG.V4 ~LLV:BUF.0.LONG.V4.1.LONG.V4 ~LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2 ~LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2 ~LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0 ~LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0 ~LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3 ~LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3 ~LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1 ~LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1 CLKH:MUX.O2[0] CLKH:MUX.O2[2] CLKH:MUX.O2[5] CLKH:MUX.O2[3] CLKH:MUX.O0[0] CLKH:MUX.O0[2] CLKH:MUX.O0[5] CLKH:MUX.O0[3] CLKH:MUX.O3[0] CLKH:MUX.O3[2] CLKH:MUX.O3[5] CLKH:MUX.O3[3] CLKH:MUX.O1[0] CLKH:MUX.O1[2] CLKH:MUX.O1[5] CLKH:MUX.O1[3] - - - - -
B0 - - - - - - - - - - - - - - - - - - - ~MISC:TLC CLKH:ENABLE.I.LR.V CLKH:ENABLE.I.UR.H CLKH:MUX.O2[1] CLKH:MUX.O2[4] CLKH:ENABLE.I.LL.H CLKH:ENABLE.I.UL.V CLKH:MUX.O0[1] CLKH:MUX.O0[4] CLKH:ENABLE.I.LR.H CLKH:ENABLE.I.LL.V CLKH:MUX.O3[1] CLKH:MUX.O3[4] CLKH:ENABLE.I.UL.H CLKH:ENABLE.I.UR.V CLKH:MUX.O1[1] CLKH:MUX.O1[4] - - - - -
CLKH:ENABLE.I.LL.H 0.F16.B0
CLKH:ENABLE.I.LL.V 0.F11.B0
CLKH:ENABLE.I.LR.H 0.F12.B0
CLKH:ENABLE.I.LR.V 0.F20.B0
CLKH:ENABLE.I.UL.H 0.F8.B0
CLKH:ENABLE.I.UL.V 0.F15.B0
CLKH:ENABLE.I.UR.H 0.F19.B0
CLKH:ENABLE.I.UR.V 0.F7.B0
non-inverted [0]
CLKH:MUX.O0 0.F14.B1 0.F13.B0 0.F13.B1 0.F15.B1 0.F14.B0 0.F16.B1
CLKH:MUX.O1 0.F6.B1 0.F5.B0 0.F5.B1 0.F7.B1 0.F6.B0 0.F8.B1
CLKH:MUX.O2 0.F18.B1 0.F17.B0 0.F17.B1 0.F19.B1 0.F18.B0 0.F20.B1
CLKH:MUX.O3 0.F10.B1 0.F9.B0 0.F9.B1 0.F11.B1 0.F10.B0 0.F12.B1
I.LL.H 0 0 1 1 1 1
I.UL.V 0 1 1 0 1 1
I.UR.H 0 1 1 1 0 1
I.LR.V 0 1 1 1 1 0
I.LR.H 1 0 0 1 1 1
I.LL.V 1 1 0 0 1 1
I.UL.H 1 1 0 1 0 1
I.UR.V 1 1 0 1 1 0
NONE 1 1 1 1 1 1
LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0 0.F25.B1
LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1 0.F21.B1
LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2 0.F27.B1
LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3 0.F23.B1
LLV:BUF.0.LONG.V0.1.LONG.V0 0.F31.B1
LLV:BUF.0.LONG.V1.1.LONG.V1 0.F39.B1
LLV:BUF.0.LONG.V2.1.LONG.V2 0.F37.B1
LLV:BUF.0.LONG.V3.1.LONG.V3 0.F33.B1
LLV:BUF.0.LONG.V4.1.LONG.V4 0.F29.B1
LLV:BUF.0.LONG.V5.1.LONG.V5 0.F35.B1
LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0 0.F26.B1
LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1 0.F22.B1
LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2 0.F28.B1
LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3 0.F24.B1
LLV:BUF.1.LONG.V0.0.LONG.V0 0.F32.B1
LLV:BUF.1.LONG.V1.0.LONG.V1 0.F40.B1
LLV:BUF.1.LONG.V2.0.LONG.V2 0.F38.B1
LLV:BUF.1.LONG.V3.0.LONG.V3 0.F34.B1
LLV:BUF.1.LONG.V4.0.LONG.V4 0.F30.B1
LLV:BUF.1.LONG.V5.0.LONG.V5 0.F36.B1
MISC:TLC 0.F21.B0
inverted ~[0]