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Input/Output

Tile IO_W0

Cells: 4

Switchbox INT

xc4000a IO_W0 switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.LONG_IO_V[0]!MAIN[7][4]
CELL.SINGLE_H[0]CELL.DEC_V[1]!MAIN[8][7]
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I1[0]!MAIN[5][5]
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I2_S1!MAIN[5][4]
CELL.SINGLE_H[1]CELL.LONG_IO_V[1]!MAIN[7][5]
CELL.SINGLE_H[1]CELL.DEC_V[0]!MAIN[10][5]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I2[0]!MAIN[10][4]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I1_S1!MAIN[11][5]
CELL.SINGLE_H[2]CELL.LONG_IO_V[0]!MAIN[3][4]
CELL.SINGLE_H[2]CELL.DEC_V[1]!MAIN[7][7]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I1[0]!MAIN[6][4]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I2_S1!MAIN[4][4]
CELL.SINGLE_H[3]CELL.LONG_IO_V[1]!MAIN[8][5]
CELL.SINGLE_H[3]CELL.DEC_V[0]!MAIN[9][5]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I2[0]!MAIN[9][4]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I1_S1!MAIN[11][4]
CELL.DOUBLE_H0[0]CELL.OUT_IO_WE_I1_S1!MAIN[12][5]
CELL.DOUBLE_H0[1]CELL.OUT_IO_WE_I2[0]!MAIN[9][6]
CELL.DOUBLE_H1[0]CELL.OUT_IO_WE_I1[0]!MAIN[12][4]
CELL.DOUBLE_H1[1]CELL.OUT_IO_WE_I2_S1!MAIN[4][5]
CELL.DOUBLE_IO_W0[0]CELL.DBUF_IO_V[1]!MAIN[6][5]
CELL.DOUBLE_IO_W0[1]CELL.DBUF_IO_V[1]!MAIN[8][4]
CELL.DOUBLE_IO_W2[0]CELL.DBUF_IO_V[0]!MAIN[6][8]
CELL.DOUBLE_IO_W2[1]CELL.DBUF_IO_V[0]!MAIN[3][8]
xc4000a IO_W0 switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.DOUBLE_IO_W0[0]!MAIN[0][7]
CELL.SINGLE_H[0]CELL.DOUBLE_IO_W2[0]!MAIN[3][6]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_W1[0]!MAIN[2][7]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_W0[1]!MAIN[4][7]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_W2[1]!MAIN[4][8]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_W1[1]!MAIN[5][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W0[0]!MAIN[0][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W1[0]!MAIN[1][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W2[0]!MAIN[1][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W0[1]!MAIN[6][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W1[1]!MAIN[7][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W2[1]!MAIN[8][6]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W0[1]!MAIN[5][6]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W1[1]!MAIN[6][7]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W2[1]!MAIN[3][7]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W0[0]!MAIN[1][4]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W1[0]!MAIN[0][4]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W2[0]!MAIN[0][6]
CELL.DOUBLE_IO_W0[0]CELL.DOUBLE_IO_W2[0]!MAIN[2][6]
CELL.DOUBLE_IO_W0[1]CELL.DOUBLE_IO_W2[1]!MAIN[4][6]
xc4000a IO_W0 switchbox INT muxes DBUF_IO_V[0]
BitsDestination
MAIN[4][3]MAIN[3][3]CELL.DBUF_IO_V[0]
Source
00CELL.DOUBLE_IO_W0[1]
11CELL.DOUBLE_IO_W0[0]
xc4000a IO_W0 switchbox INT muxes DBUF_IO_V[1]
BitsDestination
MAIN[7][8]MAIN[4][9]CELL.DBUF_IO_V[1]
Source
00CELL.DOUBLE_IO_W2[0]
11CELL.DOUBLE_IO_W2[1]
xc4000a IO_W0 switchbox INT muxes LONG_H[0]
BitsDestination
MAIN[1][0]MAIN[0][0]MAIN[2][0]MAIN[3][0]CELL.LONG_H[0]
Source
0001CELL.LONG_IO_V[0]
0010CELL.DEC_V[0]
0111CELL.OUT_IO_WE_I2[1]
1111off
xc4000a IO_W0 switchbox INT muxes LONG_H[4]
BitsDestination
MAIN[13][9]MAIN[8][8]MAIN[9][9]MAIN[9][8]CELL.LONG_H[4]
Source
0001CELL.LONG_IO_V[1]
0010CELL.DEC_V[1]
0111CELL.OUT_IO_WE_I2[0]
1111off
xc4000a IO_W0 switchbox INT muxes LONG_IO_V[0]
BitsDestination
MAIN[2][4]MAIN[0][5]MAIN[3][5]MAIN[1][5]MAIN[2][5]CELL.LONG_IO_V[0]
Source
00011CELL.SINGLE_H[0]
00101CELL.LONG_H[0]
00110CELL.LONG_H[3]
01111CELL.SINGLE_H[2]
11111off
xc4000a IO_W0 switchbox INT muxes LONG_IO_V[1]
BitsDestination
MAIN[5][9]MAIN[1][8]MAIN[3][9]MAIN[2][8]MAIN[2][9]CELL.LONG_IO_V[1]
Source
00011CELL.SINGLE_H[3]
00101CELL.LONG_H[2]
00110CELL.LONG_H[4]
01111CELL.SINGLE_H[1]
11111off
xc4000a IO_W0 switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[0][1]MAIN[1][1]MAIN[4][1]MAIN[3][1]MAIN[2][1]CELL.IMUX_TBUF_I[0]
Source
00011CELL.DOUBLE_IO_W0[1]
00101CELL.OUT_IO_WE_I2[1]
00110CELL.DEC_V[1]
01111CELL.DOUBLE_IO_W1[1]
10011CELL.LONG_IO_V[1]
10101CELL.LONG_IO_V[0]
10110CELL.OUT_IO_WE_I2[0]
11111CELL.TIE_0
xc4000a IO_W0 switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[11][1]MAIN[9][1]MAIN[10][1]MAIN[10][0]MAIN[11][0]CELL.IMUX_TBUF_I[1]
Source
00011CELL.DOUBLE_IO_W1[1]
00101CELL.LONG_IO_V[0]
00110CELL.LONG_IO_V[1]
01111CELL.DOUBLE_IO_W0[1]
10011CELL.OUT_IO_WE_I2[0]
10101CELL.DEC_V[0]
10110CELL.OUT_IO_WE_I2[1]
11111CELL.TIE_0
xc4000a IO_W0 switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[5][0]MAIN[4][0]MAIN[6][1]MAIN[5][1]MAIN[6][0]CELL.IMUX_TBUF_T[0]
Source
00011CELL.DOUBLE_IO_W0[0]
00110CELL.DEC_V[1]
01111CELL.TIE_1
10011CELL.LONG_IO_V[1]
10101CELL.DOUBLE_IO_W1[0]
10110CELL.LONG_IO_V[0]
11111CELL.TIE_0
xc4000a IO_W0 switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[9][0]MAIN[7][1]MAIN[8][0]MAIN[8][1]MAIN[7][0]CELL.IMUX_TBUF_T[1]
Source
00011CELL.DOUBLE_IO_W0[0]
00110CELL.DEC_V[1]
01111CELL.TIE_1
10011CELL.LONG_IO_V[1]
10101CELL.DOUBLE_IO_W1[0]
10110CELL.LONG_IO_V[0]
11111CELL.TIE_0
xc4000a IO_W0 switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[12][9]MAIN[6][9]MAIN[7][9]MAIN[10][9]MAIN[10][8]CELL.IMUX_IO_O1[0]
Source
00011CELL.DOUBLE_H0[0]
00101CELL.LONG_H[4]
01111CELL.DOUBLE_H1[1]
10011CELL.LONG_H[3]
10101CELL.DEC_V[0]
10110CELL.DEC_V[1]
11111CELL.TIE_0
xc4000a IO_W0 switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[12][0]MAIN[13][1]MAIN[14][0]MAIN[14][1]MAIN[12][1]CELL.IMUX_IO_O1[1]
Source
00101CELL.DEC_V[1]
00111CELL.LONG_H[0]
01001CELL.DEC_V[0]
01011CELL.LONG_H[2]
01110CELL_S.DOUBLE_H0[1]
11101CELL_S.DOUBLE_H1[0]
11111CELL.TIE_0
xc4000a IO_W0 switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[9][7]MAIN[12][7]MAIN[15][8]MAIN[11][7]MAIN[14][7]MAIN[15][7]MAIN[13][7]MAIN[14][8]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_H[0]
01011111CELL.SINGLE_H[2]
01101111CELL.SINGLE_H[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[1]
xc4000a IO_W0 switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[8][2]MAIN[9][2]MAIN[15][2]MAIN[10][2]MAIN[13][2]MAIN[17][2]MAIN[16][2]MAIN[14][2]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[0]
01111101CELL_S.SINGLE_H[1]
01111110CELL_S.SINGLE_H[3]
11111111CELL_S.SINGLE_H[2]
xc4000a IO_W0 switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[10][7]MAIN[12][6]MAIN[14][6]MAIN[17][6]MAIN[11][6]MAIN[10][6]MAIN[15][6]MAIN[16][6]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_H[1]
01011111CELL.SINGLE_H[2]
01101111CELL.SINGLE_H[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[0]
xc4000a IO_W0 switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[10][3]MAIN[11][2]MAIN[14][3]MAIN[11][3]MAIN[12][2]MAIN[16][3]MAIN[17][3]MAIN[12][3]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[0]
01111101CELL_S.SINGLE_H[1]
01111110CELL_S.SINGLE_H[2]
11111111CELL_S.SINGLE_H[3]
xc4000a IO_W0 switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[1][3]MAIN[4][2]MAIN[5][2]MAIN[2][2]MAIN[2][3]MAIN[1][2]CELL.IMUX_IO_T[0]
Source
001111CELL.TIE_0
010011CELL.GCLK[0]
010101CELL.DOUBLE_IO_W1[1]
010110CELL.DEC_V[0]
011011CELL.DOUBLE_IO_W1[0]
011101CELL.LONG_IO_V[1]
011110CELL.LONG_IO_V[0]
110111CELL.DOUBLE_IO_W0[1]
111111CELL.DOUBLE_IO_W0[0]
xc4000a IO_W0 switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[6][3]MAIN[7][2]MAIN[8][3]MAIN[3][2]MAIN[7][3]MAIN[6][2]CELL.IMUX_IO_T[1]
Source
001111CELL.TIE_0
010011CELL.GCLK[0]
010111CELL.DOUBLE_IO_W0[0]
011001CELL.DOUBLE_IO_W0[1]
011010CELL.DEC_V[0]
011101CELL.LONG_IO_V[1]
011110CELL.LONG_IO_V[0]
111011CELL.DOUBLE_IO_W1[1]
111111CELL.DOUBLE_IO_W1[0]

Bels TBUF

xc4000a IO_W0 bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000a IO_W0 bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[0][3]!MAIN[9][3]

Bels IO

xc4000a IO_W0 bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[17][7]CELL.IMUX_IO_IK[1] invert by !MAIN[15][5]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[11][8]CELL.IMUX_IO_OK[1] invert by !MAIN[18][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_G3_WCELL.IMUX_CLB_F3_W
TinCELL.IMUX_IO_T[0] invert by !MAIN[19][9]CELL.IMUX_IO_T[1] invert by !MAIN[17][0]
I1outCELL.OUT_IO_WE_I1[0]CELL.OUT_IO_WE_I1[1]
I2outCELL.OUT_IO_WE_I2[0]CELL.OUT_IO_WE_I2[1]
xc4000a IO_W0 bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[16][7]!MAIN[18][2]
OFF_SRVAL bit 0!MAIN[13][8]!MAIN[18][1]
READBACK_I1 bit 0!MAIN[18][5]!MAIN[19][5]
READBACK_I2 bit 0!MAIN[16][8]!MAIN[20][5]
READBACK_OQ bit 0!MAIN[18][9]!MAIN[16][1]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[17][8]!MAIN[19][1]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[19][8]MAIN[20][2]
xc4000a IO_W0 enum IO_SLEW
IO[0].SLEWMAIN[14][9]MAIN[11][9]
IO[1].SLEWMAIN[19][0]MAIN[13][0]
FAST00
MEDFAST01
MEDSLOW10
SLOW11
xc4000a IO_W0 enum IO_PULL
IO[0].PULLMAIN[5][8]MAIN[18][8]
IO[1].PULLMAIN[20][1]MAIN[20][0]
NONE11
PULLUP01
PULLDOWN10
xc4000a IO_W0 enum IO_MUX_I
IO[0].MUX_I1MAIN[18][6]MAIN[20][6]MAIN[19][6]
IO[1].MUX_I1MAIN[18][4]MAIN[20][4]MAIN[19][4]
IO[0].MUX_I2MAIN[18][7]MAIN[20][7]MAIN[19][7]
IO[1].MUX_I2MAIN[18][3]MAIN[20][3]MAIN[19][3]
I001
IQ111
IQL010
xc4000a IO_W0 enum IO_IFF_D
IO[0].IFF_DMAIN[20][8]
IO[1].IFF_DMAIN[19][2]
I1
DELAY0
xc4000a IO_W0 enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[12][8]
IO[1].MUX_OFF_DMAIN[17][1]
O11
O20
xc4000a IO_W0 enum IO_MUX_O
IO[0].MUX_OMAIN[17][9]MAIN[16][9]MAIN[15][9]
IO[1].MUX_OMAIN[15][1]MAIN[16][0]MAIN[15][0]
O1001
O1_INV010
O2100
O2_INV011
OQ000

Bels DEC

xc4000a IO_W0 bel DEC pins
PinDirectionDEC[0]DEC[1]DEC[2]
IinCELL.OUT_IO_WE_I1[0]CELL.IMUX_CLB_C3_WCELL.OUT_IO_WE_I1[1]
O1bidirCELL.DEC_V[0]CELL.DEC_V[0]CELL.DEC_V[0]
O2bidirCELL.DEC_V[1]CELL.DEC_V[1]CELL.DEC_V[1]
xc4000a IO_W0 bel DEC attribute bits
AttributeDEC[0]DEC[1]DEC[2]
O1_P!MAIN[13][4]!MAIN[13][5]MAIN[14][5]
O1_NMAIN[13][3]MAIN[13][6]!MAIN[14][4]
O2_P!MAIN[15][4]!MAIN[17][5]MAIN[16][4]
O2_NMAIN[15][3]MAIN[17][4]!MAIN[16][5]

Bels PULLUP

xc4000a IO_W0 bel PULLUP pins
PinDirectionPULLUP_TBUF[0]PULLUP_TBUF[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000a IO_W0 bel PULLUP attribute bits
AttributePULLUP_TBUF[0]PULLUP_TBUF[1]
ENABLE!MAIN_S[0][9]!MAIN[8][9]

Bel wires

xc4000a IO_W0 bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]TBUF[1].O, PULLUP_TBUF[1].O
CELL.DEC_V[0]DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_V[1]DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.IMUX_CLB_F3_WIO[1].O2
CELL.IMUX_CLB_G3_WIO[0].O2
CELL.IMUX_CLB_C3_WDEC[1].I
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_WE_I1[0]IO[0].I1, DEC[0].I
CELL.OUT_IO_WE_I1[1]IO[1].I1, DEC[2].I
CELL.OUT_IO_WE_I2[0]IO[0].I2
CELL.OUT_IO_WE_I2[1]IO[1].I2

Bitstream

xc4000a IO_W0 rect MAIN
BitFrame
F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - IO[0]: !invert T IO[0]: ! READBACK_OQ bit 0 IO[0]: MUX_O bit 2 IO[0]: MUX_O bit 1 IO[0]: MUX_O bit 0 IO[0]: SLEW bit 1 INT: mux CELL.LONG_H[4] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 4 IO[0]: SLEW bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.LONG_H[4] bit 1 PULLUP_TBUF[1]: ! ENABLE INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.LONG_IO_V[1] bit 4 INT: mux CELL.DBUF_IO_V[1] bit 0 INT: mux CELL.LONG_IO_V[1] bit 2 INT: mux CELL.LONG_IO_V[1] bit 0 - -
B8 IO[0]: IFF_D bit 0 IO[0]: OFF_USED IO[0]: PULL bit 0 IO[0]: ! OFF_D_INV IO[0]: ! READBACK_I2 bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: mux CELL.IMUX_IO_OK[0] bit 0 IO[0]: ! OFF_SRVAL bit 0 IO[0]: MUX_OFF_D bit 0 IO[0]: !invert OK INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.LONG_H[4] bit 0 INT: mux CELL.LONG_H[4] bit 2 INT: mux CELL.DBUF_IO_V[1] bit 1 INT: !pass CELL.DOUBLE_IO_W2[0] ← CELL.DBUF_IO_V[0] IO[0]: PULL bit 1 INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W2[1] INT: !pass CELL.DOUBLE_IO_W2[1] ← CELL.DBUF_IO_V[0] INT: mux CELL.LONG_IO_V[1] bit 1 INT: mux CELL.LONG_IO_V[1] bit 3 INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W0[0]
B7 IO[0]: MUX_I2 bit 1 IO[0]: MUX_I2 bit 0 IO[0]: MUX_I2 bit 2 IO[0]: !invert IK IO[0]: ! IFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 7 INT: mux CELL.IMUX_IO_OK[0] bit 7 INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[1] INT: !pass CELL.SINGLE_H[2] ← CELL.DEC_V[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W1[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W1[0] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W0[0]
B6 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I1 bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 5 DEC[1]: O1_N INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2[0] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.DOUBLE_IO_W0[1] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W2[0] INT: !bipass CELL.DOUBLE_IO_W0[0] = CELL.DOUBLE_IO_W2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W2[0] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W2[0]
B5 IO[1]: ! READBACK_I2 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[0]: ! READBACK_I1 bit 0 DEC[1]: ! O2_P DEC[2]: ! O2_N IO[1]: !invert IK DEC[2]: O1_P DEC[1]: ! O1_P INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.SINGLE_H[1] ← CELL.DEC_V[0] INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[0] INT: !pass CELL.SINGLE_H[3] ← CELL.LONG_IO_V[1] INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[1] INT: !pass CELL.DOUBLE_IO_W0[0] ← CELL.DBUF_IO_V[1] INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2_S1 INT: mux CELL.LONG_IO_V[0] bit 2 INT: mux CELL.LONG_IO_V[0] bit 0 INT: mux CELL.LONG_IO_V[0] bit 1 INT: mux CELL.LONG_IO_V[0] bit 3
B4 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 2 DEC[1]: O2_N DEC[2]: O2_P DEC[0]: ! O2_P DEC[2]: ! O1_N DEC[0]: ! O1_P INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.DOUBLE_IO_W0[1] ← CELL.DBUF_IO_V[1] INT: !pass CELL.SINGLE_H[0] ← CELL.LONG_IO_V[0] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[0] INT: mux CELL.LONG_IO_V[0] bit 4 INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W0[0] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W1[0]
B3 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I2 bit 0 IO[1]: MUX_I2 bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 DEC[0]: O2_N INT: mux CELL.IMUX_IO_IK[1] bit 5 DEC[0]: O1_N INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 7 TBUF[1]: ! DRIVE1 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 5 - INT: mux CELL.DBUF_IO_V[0] bit 1 INT: mux CELL.DBUF_IO_V[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 5 TBUF[0]: ! DRIVE1
B2 IO[1]: OFF_USED IO[1]: IFF_D bit 0 IO[1]: ! IFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 7 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 0 -
B1 IO[1]: PULL bit 1 IO[1]: ! OFF_D_INV IO[1]: ! OFF_SRVAL bit 0 IO[1]: MUX_OFF_D bit 0 IO[1]: ! READBACK_OQ bit 0 IO[1]: MUX_O bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: mux CELL.IMUX_TBUF_I[0] bit 4
B0 IO[1]: PULL bit 0 IO[1]: SLEW bit 1 IO[1]: !invert OK IO[1]: !invert T IO[1]: MUX_O bit 1 IO[1]: MUX_O bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 2 IO[1]: SLEW bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 4 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.LONG_H[0] bit 0 INT: mux CELL.LONG_H[0] bit 1 INT: mux CELL.LONG_H[0] bit 3 INT: mux CELL.LONG_H[0] bit 2
xc4000a IO_W0 rect MAIN_S
BitFrame
F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - PULLUP_TBUF[0]: ! ENABLE
B8 - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - -

Tile IO_W0_N

Cells: 4

Switchbox INT

xc4000a IO_W0_N switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.LONG_IO_V[0]!MAIN[7][4]
CELL.SINGLE_H[0]CELL.DEC_V[1]!MAIN[8][7]
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I1[0]!MAIN[5][5]
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I2_S1!MAIN[5][4]
CELL.SINGLE_H[1]CELL.LONG_IO_V[1]!MAIN[7][5]
CELL.SINGLE_H[1]CELL.DEC_V[0]!MAIN[10][5]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I2[0]!MAIN[10][4]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I1_S1!MAIN[11][5]
CELL.SINGLE_H[2]CELL.LONG_IO_V[0]!MAIN[3][4]
CELL.SINGLE_H[2]CELL.DEC_V[1]!MAIN[7][7]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I1[0]!MAIN[6][4]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I2_S1!MAIN[4][4]
CELL.SINGLE_H[3]CELL.LONG_IO_V[1]!MAIN[8][5]
CELL.SINGLE_H[3]CELL.DEC_V[0]!MAIN[9][5]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I2[0]!MAIN[9][4]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I1_S1!MAIN[11][4]
CELL.DOUBLE_H0[0]CELL.OUT_IO_WE_I1_S1!MAIN[12][5]
CELL.DOUBLE_H0[1]CELL.OUT_IO_WE_I2[0]!MAIN[9][6]
CELL.DOUBLE_H1[0]CELL.OUT_IO_WE_I1[0]!MAIN[12][4]
CELL.DOUBLE_H1[1]CELL.OUT_IO_WE_I2_S1!MAIN[4][5]
CELL.DOUBLE_IO_W0[0]CELL.DBUF_IO_V[1]!MAIN[6][5]
CELL.DOUBLE_IO_W0[1]CELL.DBUF_IO_V[1]!MAIN[8][4]
CELL.DOUBLE_IO_W2[0]CELL.DBUF_IO_V[0]!MAIN[6][8]
CELL.DOUBLE_IO_W2[1]CELL.DBUF_IO_V[0]!MAIN[3][8]
xc4000a IO_W0_N switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.DOUBLE_IO_W0[0]!MAIN[0][7]
CELL.SINGLE_H[0]CELL.DOUBLE_IO_W2[0]!MAIN[3][6]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_W1[0]!MAIN[2][7]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_W0[1]!MAIN[4][7]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_W2[1]!MAIN[4][8]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_W1[1]!MAIN[5][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W0[0]!MAIN[0][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W1[0]!MAIN[1][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W2[0]!MAIN[1][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W0[1]!MAIN[6][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W1[1]!MAIN[7][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W2[1]!MAIN[8][6]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W0[1]!MAIN[5][6]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W1[1]!MAIN[6][7]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W2[1]!MAIN[3][7]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W0[0]!MAIN[1][4]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W1[0]!MAIN[0][4]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W2[0]!MAIN[0][6]
CELL.DOUBLE_IO_W0[0]CELL.DOUBLE_IO_W2[0]!MAIN[2][6]
CELL.DOUBLE_IO_W0[1]CELL.DOUBLE_IO_W2[1]!MAIN[4][6]
xc4000a IO_W0_N switchbox INT muxes DBUF_IO_V[0]
BitsDestination
MAIN[4][3]MAIN[3][3]CELL.DBUF_IO_V[0]
Source
00CELL.DOUBLE_IO_W0[1]
11CELL.DOUBLE_IO_W0[0]
xc4000a IO_W0_N switchbox INT muxes DBUF_IO_V[1]
BitsDestination
MAIN[7][8]MAIN[4][9]CELL.DBUF_IO_V[1]
Source
00CELL.DOUBLE_IO_W2[0]
11CELL.DOUBLE_IO_W2[1]
xc4000a IO_W0_N switchbox INT muxes LONG_H[0]
BitsDestination
MAIN[1][0]MAIN[0][0]MAIN[2][0]MAIN[3][0]CELL.LONG_H[0]
Source
0001CELL.LONG_IO_V[0]
0010CELL.DEC_V[0]
0111CELL.OUT_IO_WE_I2[1]
1111off
xc4000a IO_W0_N switchbox INT muxes LONG_H[4]
BitsDestination
MAIN[13][9]MAIN[8][8]MAIN[9][9]MAIN[9][8]CELL.LONG_H[4]
Source
0001CELL.LONG_IO_V[1]
0010CELL.DEC_V[1]
0111CELL.OUT_IO_WE_I2[0]
1111off
xc4000a IO_W0_N switchbox INT muxes LONG_IO_V[0]
BitsDestination
MAIN[2][4]MAIN[0][5]MAIN[3][5]MAIN[1][5]MAIN[2][5]CELL.LONG_IO_V[0]
Source
00011CELL.SINGLE_H[0]
00101CELL.LONG_H[0]
00110CELL.LONG_H[3]
01111CELL.SINGLE_H[2]
11111off
xc4000a IO_W0_N switchbox INT muxes LONG_IO_V[1]
BitsDestination
MAIN[5][9]MAIN[1][8]MAIN[3][9]MAIN[2][8]MAIN[2][9]CELL.LONG_IO_V[1]
Source
00011CELL.SINGLE_H[3]
00101CELL.LONG_H[2]
00110CELL.LONG_H[4]
01111CELL.SINGLE_H[1]
11111off
xc4000a IO_W0_N switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[0][1]MAIN[1][1]MAIN[4][1]MAIN[3][1]MAIN[2][1]CELL.IMUX_TBUF_I[0]
Source
00011CELL.DOUBLE_IO_W0[1]
00101CELL.OUT_IO_WE_I2[1]
00110CELL.DEC_V[1]
01111CELL.DOUBLE_IO_W1[1]
10011CELL.LONG_IO_V[1]
10101CELL.LONG_IO_V[0]
10110CELL.OUT_IO_WE_I2[0]
11111CELL.TIE_0
xc4000a IO_W0_N switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[11][1]MAIN[9][1]MAIN[10][1]MAIN[10][0]MAIN[11][0]CELL.IMUX_TBUF_I[1]
Source
00011CELL.DOUBLE_IO_W1[1]
00101CELL.LONG_IO_V[0]
00110CELL.LONG_IO_V[1]
01111CELL.DOUBLE_IO_W0[1]
10011CELL.OUT_IO_WE_I2[0]
10101CELL.DEC_V[0]
10110CELL.OUT_IO_WE_I2[1]
11111CELL.TIE_0
xc4000a IO_W0_N switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[5][0]MAIN[4][0]MAIN[6][1]MAIN[5][1]MAIN[6][0]CELL.IMUX_TBUF_T[0]
Source
00011CELL.DOUBLE_IO_W0[0]
00110CELL.DEC_V[1]
01111CELL.TIE_1
10011CELL.LONG_IO_V[1]
10101CELL.DOUBLE_IO_W1[0]
10110CELL.LONG_IO_V[0]
11111CELL.TIE_0
xc4000a IO_W0_N switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[9][0]MAIN[7][1]MAIN[8][0]MAIN[8][1]MAIN[7][0]CELL.IMUX_TBUF_T[1]
Source
00011CELL.DOUBLE_IO_W0[0]
00110CELL.DEC_V[1]
01111CELL.TIE_1
10011CELL.LONG_IO_V[1]
10101CELL.DOUBLE_IO_W1[0]
10110CELL.LONG_IO_V[0]
11111CELL.TIE_0
xc4000a IO_W0_N switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[12][9]MAIN[6][9]MAIN[7][9]MAIN[10][9]MAIN[10][8]CELL.IMUX_IO_O1[0]
Source
00011CELL.DOUBLE_H0[0]
00101CELL.LONG_H[4]
01111CELL.DOUBLE_H1[1]
10011CELL.LONG_H[3]
10101CELL.DEC_V[0]
10110CELL.DEC_V[1]
11111CELL.TIE_0
xc4000a IO_W0_N switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[12][0]MAIN[13][1]MAIN[14][0]MAIN[14][1]MAIN[12][1]CELL.IMUX_IO_O1[1]
Source
00101CELL.DEC_V[1]
00111CELL.LONG_H[0]
01001CELL.DEC_V[0]
01011CELL.LONG_H[2]
01110CELL_S.DOUBLE_H0[1]
11101CELL_S.DOUBLE_H1[0]
11111CELL.TIE_0
xc4000a IO_W0_N switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[9][7]MAIN[12][7]MAIN[15][8]MAIN[11][7]MAIN[14][7]MAIN[15][7]MAIN[13][7]MAIN[14][8]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_H[0]
01011111CELL.SINGLE_H[2]
01101111CELL.SINGLE_H[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[1]
xc4000a IO_W0_N switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[8][2]MAIN[9][2]MAIN[15][2]MAIN[10][2]MAIN[13][2]MAIN[17][2]MAIN[16][2]MAIN[14][2]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[0]
01111101CELL_S.SINGLE_H[1]
01111110CELL_S.SINGLE_H[3]
11111111CELL_S.SINGLE_H[2]
xc4000a IO_W0_N switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[10][7]MAIN[12][6]MAIN[14][6]MAIN[17][6]MAIN[11][6]MAIN[10][6]MAIN[15][6]MAIN[16][6]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_H[1]
01011111CELL.SINGLE_H[2]
01101111CELL.SINGLE_H[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[0]
xc4000a IO_W0_N switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[10][3]MAIN[11][2]MAIN[14][3]MAIN[11][3]MAIN[12][2]MAIN[16][3]MAIN[17][3]MAIN[12][3]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[0]
01111101CELL_S.SINGLE_H[1]
01111110CELL_S.SINGLE_H[2]
11111111CELL_S.SINGLE_H[3]
xc4000a IO_W0_N switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[1][3]MAIN[4][2]MAIN[5][2]MAIN[2][2]MAIN[2][3]MAIN[1][2]CELL.IMUX_IO_T[0]
Source
001111CELL.TIE_0
010011CELL.GCLK[0]
010101CELL.DOUBLE_IO_W1[1]
010110CELL.DEC_V[0]
011011CELL.DOUBLE_IO_W1[0]
011101CELL.LONG_IO_V[1]
011110CELL.LONG_IO_V[0]
110111CELL.DOUBLE_IO_W0[1]
111111CELL.DOUBLE_IO_W0[0]
xc4000a IO_W0_N switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[6][3]MAIN[7][2]MAIN[8][3]MAIN[3][2]MAIN[7][3]MAIN[6][2]CELL.IMUX_IO_T[1]
Source
001111CELL.TIE_0
010011CELL.GCLK[0]
010111CELL.DOUBLE_IO_W0[0]
011001CELL.DOUBLE_IO_W0[1]
011010CELL.DEC_V[0]
011101CELL.LONG_IO_V[1]
011110CELL.LONG_IO_V[0]
111011CELL.DOUBLE_IO_W1[1]
111111CELL.DOUBLE_IO_W1[0]

Bels TBUF

xc4000a IO_W0_N bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000a IO_W0_N bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[0][3]!MAIN[9][3]

Bels IO

xc4000a IO_W0_N bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[17][7]CELL.IMUX_IO_IK[1] invert by !MAIN[15][5]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[11][8]CELL.IMUX_IO_OK[1] invert by !MAIN[18][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_G3_WCELL.IMUX_CLB_F3_W
TinCELL.IMUX_IO_T[0] invert by !MAIN[19][9]CELL.IMUX_IO_T[1] invert by !MAIN[17][0]
I1outCELL.OUT_IO_WE_I1[0]CELL.OUT_IO_WE_I1[1]
I2outCELL.OUT_IO_WE_I2[0]CELL.OUT_IO_WE_I2[1]
CLKINoutCELL.OUT_IO_CLKIN-
xc4000a IO_W0_N bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[16][7]!MAIN[18][2]
OFF_SRVAL bit 0!MAIN[13][8]!MAIN[18][1]
READBACK_I1 bit 0!MAIN[18][5]!MAIN[19][5]
READBACK_I2 bit 0!MAIN[16][8]!MAIN[20][5]
READBACK_OQ bit 0!MAIN[18][9]!MAIN[16][1]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[17][8]!MAIN[19][1]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[19][8]MAIN[20][2]
xc4000a IO_W0_N enum IO_SLEW
IO[0].SLEWMAIN[14][9]MAIN[11][9]
IO[1].SLEWMAIN[19][0]MAIN[13][0]
FAST00
MEDFAST01
MEDSLOW10
SLOW11
xc4000a IO_W0_N enum IO_PULL
IO[0].PULLMAIN[5][8]MAIN[18][8]
IO[1].PULLMAIN[20][1]MAIN[20][0]
NONE11
PULLUP01
PULLDOWN10
xc4000a IO_W0_N enum IO_MUX_I
IO[0].MUX_I1MAIN[18][6]MAIN[20][6]MAIN[19][6]
IO[1].MUX_I1MAIN[18][4]MAIN[20][4]MAIN[19][4]
IO[0].MUX_I2MAIN[18][7]MAIN[20][7]MAIN[19][7]
IO[1].MUX_I2MAIN[18][3]MAIN[20][3]MAIN[19][3]
I001
IQ111
IQL010
xc4000a IO_W0_N enum IO_IFF_D
IO[0].IFF_DMAIN[20][8]
IO[1].IFF_DMAIN[19][2]
I1
DELAY0
xc4000a IO_W0_N enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[12][8]
IO[1].MUX_OFF_DMAIN[17][1]
O11
O20
xc4000a IO_W0_N enum IO_MUX_O
IO[0].MUX_OMAIN[17][9]MAIN[16][9]MAIN[15][9]
IO[1].MUX_OMAIN[15][1]MAIN[16][0]MAIN[15][0]
O1001
O1_INV010
O2100
O2_INV011
OQ000

Bels DEC

xc4000a IO_W0_N bel DEC pins
PinDirectionDEC[0]DEC[1]DEC[2]
IinCELL.OUT_IO_WE_I1[0]CELL.IMUX_CLB_C3_WCELL.OUT_IO_WE_I1[1]
O1bidirCELL.DEC_V[0]CELL.DEC_V[0]CELL.DEC_V[0]
O2bidirCELL.DEC_V[1]CELL.DEC_V[1]CELL.DEC_V[1]
xc4000a IO_W0_N bel DEC attribute bits
AttributeDEC[0]DEC[1]DEC[2]
O1_P!MAIN[13][4]!MAIN[13][5]MAIN[14][5]
O1_NMAIN[13][3]MAIN[13][6]!MAIN[14][4]
O2_P!MAIN[15][4]!MAIN[17][5]MAIN[16][4]
O2_NMAIN[15][3]MAIN[17][4]!MAIN[16][5]

Bels PULLUP

xc4000a IO_W0_N bel PULLUP pins
PinDirectionPULLUP_TBUF[0]PULLUP_TBUF[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000a IO_W0_N bel PULLUP attribute bits
AttributePULLUP_TBUF[0]PULLUP_TBUF[1]
ENABLE!MAIN_S[0][9]!MAIN[8][9]

Bel wires

xc4000a IO_W0_N bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]TBUF[1].O, PULLUP_TBUF[1].O
CELL.DEC_V[0]DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_V[1]DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.IMUX_CLB_F3_WIO[1].O2
CELL.IMUX_CLB_G3_WIO[0].O2
CELL.IMUX_CLB_C3_WDEC[1].I
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_WE_I1[0]IO[0].I1, DEC[0].I
CELL.OUT_IO_WE_I1[1]IO[1].I1, DEC[2].I
CELL.OUT_IO_WE_I2[0]IO[0].I2
CELL.OUT_IO_WE_I2[1]IO[1].I2
CELL.OUT_IO_CLKINIO[0].CLKIN

Bitstream

xc4000a IO_W0_N rect MAIN
BitFrame
F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - IO[0]: !invert T IO[0]: ! READBACK_OQ bit 0 IO[0]: MUX_O bit 2 IO[0]: MUX_O bit 1 IO[0]: MUX_O bit 0 IO[0]: SLEW bit 1 INT: mux CELL.LONG_H[4] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 4 IO[0]: SLEW bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.LONG_H[4] bit 1 PULLUP_TBUF[1]: ! ENABLE INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.LONG_IO_V[1] bit 4 INT: mux CELL.DBUF_IO_V[1] bit 0 INT: mux CELL.LONG_IO_V[1] bit 2 INT: mux CELL.LONG_IO_V[1] bit 0 - -
B8 IO[0]: IFF_D bit 0 IO[0]: OFF_USED IO[0]: PULL bit 0 IO[0]: ! OFF_D_INV IO[0]: ! READBACK_I2 bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: mux CELL.IMUX_IO_OK[0] bit 0 IO[0]: ! OFF_SRVAL bit 0 IO[0]: MUX_OFF_D bit 0 IO[0]: !invert OK INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.LONG_H[4] bit 0 INT: mux CELL.LONG_H[4] bit 2 INT: mux CELL.DBUF_IO_V[1] bit 1 INT: !pass CELL.DOUBLE_IO_W2[0] ← CELL.DBUF_IO_V[0] IO[0]: PULL bit 1 INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W2[1] INT: !pass CELL.DOUBLE_IO_W2[1] ← CELL.DBUF_IO_V[0] INT: mux CELL.LONG_IO_V[1] bit 1 INT: mux CELL.LONG_IO_V[1] bit 3 INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W0[0]
B7 IO[0]: MUX_I2 bit 1 IO[0]: MUX_I2 bit 0 IO[0]: MUX_I2 bit 2 IO[0]: !invert IK IO[0]: ! IFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 7 INT: mux CELL.IMUX_IO_OK[0] bit 7 INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[1] INT: !pass CELL.SINGLE_H[2] ← CELL.DEC_V[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W1[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W1[0] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W0[0]
B6 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I1 bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 5 DEC[1]: O1_N INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2[0] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.DOUBLE_IO_W0[1] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W2[0] INT: !bipass CELL.DOUBLE_IO_W0[0] = CELL.DOUBLE_IO_W2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W2[0] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W2[0]
B5 IO[1]: ! READBACK_I2 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[0]: ! READBACK_I1 bit 0 DEC[1]: ! O2_P DEC[2]: ! O2_N IO[1]: !invert IK DEC[2]: O1_P DEC[1]: ! O1_P INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.SINGLE_H[1] ← CELL.DEC_V[0] INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[0] INT: !pass CELL.SINGLE_H[3] ← CELL.LONG_IO_V[1] INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[1] INT: !pass CELL.DOUBLE_IO_W0[0] ← CELL.DBUF_IO_V[1] INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2_S1 INT: mux CELL.LONG_IO_V[0] bit 2 INT: mux CELL.LONG_IO_V[0] bit 0 INT: mux CELL.LONG_IO_V[0] bit 1 INT: mux CELL.LONG_IO_V[0] bit 3
B4 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 2 DEC[1]: O2_N DEC[2]: O2_P DEC[0]: ! O2_P DEC[2]: ! O1_N DEC[0]: ! O1_P INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.DOUBLE_IO_W0[1] ← CELL.DBUF_IO_V[1] INT: !pass CELL.SINGLE_H[0] ← CELL.LONG_IO_V[0] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[0] INT: mux CELL.LONG_IO_V[0] bit 4 INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W0[0] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W1[0]
B3 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I2 bit 0 IO[1]: MUX_I2 bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 DEC[0]: O2_N INT: mux CELL.IMUX_IO_IK[1] bit 5 DEC[0]: O1_N INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 7 TBUF[1]: ! DRIVE1 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 5 - INT: mux CELL.DBUF_IO_V[0] bit 1 INT: mux CELL.DBUF_IO_V[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 5 TBUF[0]: ! DRIVE1
B2 IO[1]: OFF_USED IO[1]: IFF_D bit 0 IO[1]: ! IFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 7 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 0 -
B1 IO[1]: PULL bit 1 IO[1]: ! OFF_D_INV IO[1]: ! OFF_SRVAL bit 0 IO[1]: MUX_OFF_D bit 0 IO[1]: ! READBACK_OQ bit 0 IO[1]: MUX_O bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: mux CELL.IMUX_TBUF_I[0] bit 4
B0 IO[1]: PULL bit 0 IO[1]: SLEW bit 1 IO[1]: !invert OK IO[1]: !invert T IO[1]: MUX_O bit 1 IO[1]: MUX_O bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 2 IO[1]: SLEW bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 4 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.LONG_H[0] bit 0 INT: mux CELL.LONG_H[0] bit 1 INT: mux CELL.LONG_H[0] bit 3 INT: mux CELL.LONG_H[0] bit 2
xc4000a IO_W0_N rect MAIN_S
BitFrame
F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - PULLUP_TBUF[0]: ! ENABLE
B8 - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - -

Tile IO_W1

Cells: 4

Switchbox INT

xc4000a IO_W1 switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.LONG_IO_V[0]!MAIN[7][4]
CELL.SINGLE_H[0]CELL.DEC_V[1]!MAIN[8][7]
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I1[0]!MAIN[5][5]
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I2_S1!MAIN[5][4]
CELL.SINGLE_H[1]CELL.LONG_IO_V[1]!MAIN[7][5]
CELL.SINGLE_H[1]CELL.DEC_V[0]!MAIN[10][5]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I2[0]!MAIN[10][4]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I1_S1!MAIN[11][5]
CELL.SINGLE_H[2]CELL.LONG_IO_V[0]!MAIN[3][4]
CELL.SINGLE_H[2]CELL.DEC_V[1]!MAIN[7][7]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I1[0]!MAIN[6][4]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I2_S1!MAIN[4][4]
CELL.SINGLE_H[3]CELL.LONG_IO_V[1]!MAIN[8][5]
CELL.SINGLE_H[3]CELL.DEC_V[0]!MAIN[9][5]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I2[0]!MAIN[9][4]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I1_S1!MAIN[11][4]
CELL.DOUBLE_H0[0]CELL.OUT_IO_WE_I1_S1!MAIN[12][5]
CELL.DOUBLE_H0[1]CELL.OUT_IO_WE_I2[0]!MAIN[9][6]
CELL.DOUBLE_H1[0]CELL.OUT_IO_WE_I1[0]!MAIN[12][4]
CELL.DOUBLE_H1[1]CELL.OUT_IO_WE_I2_S1!MAIN[4][5]
CELL.DOUBLE_IO_W0[0]CELL.DBUF_IO_V[1]!MAIN[6][5]
CELL.DOUBLE_IO_W0[1]CELL.DBUF_IO_V[1]!MAIN[8][4]
CELL.DOUBLE_IO_W2[0]CELL.DBUF_IO_V[0]!MAIN[6][8]
CELL.DOUBLE_IO_W2[1]CELL.DBUF_IO_V[0]!MAIN[3][8]
xc4000a IO_W1 switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.DOUBLE_IO_W1[0]!MAIN[2][7]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_W0[0]!MAIN[0][7]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_W2[0]!MAIN[3][6]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_W1[1]!MAIN[5][7]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_W0[1]!MAIN[4][7]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_W2[1]!MAIN[4][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W0[0]!MAIN[0][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W1[0]!MAIN[1][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W2[0]!MAIN[1][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W0[1]!MAIN[6][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W1[1]!MAIN[7][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W2[1]!MAIN[8][6]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W0[1]!MAIN[5][6]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W1[1]!MAIN[6][7]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W2[1]!MAIN[3][7]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W0[0]!MAIN[1][4]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W1[0]!MAIN[0][4]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W2[0]!MAIN[0][6]
CELL.DOUBLE_IO_W0[0]CELL.DOUBLE_IO_W2[0]!MAIN[2][6]
CELL.DOUBLE_IO_W0[1]CELL.DOUBLE_IO_W2[1]!MAIN[4][6]
xc4000a IO_W1 switchbox INT muxes DBUF_IO_V[0]
BitsDestination
MAIN[4][3]MAIN[3][3]CELL.DBUF_IO_V[0]
Source
00CELL.DOUBLE_IO_W0[1]
11CELL.DOUBLE_IO_W0[0]
xc4000a IO_W1 switchbox INT muxes DBUF_IO_V[1]
BitsDestination
MAIN[7][8]MAIN[4][9]CELL.DBUF_IO_V[1]
Source
00CELL.DOUBLE_IO_W2[0]
11CELL.DOUBLE_IO_W2[1]
xc4000a IO_W1 switchbox INT muxes LONG_H[0]
BitsDestination
MAIN[1][0]MAIN[0][0]MAIN[2][0]MAIN[3][0]CELL.LONG_H[0]
Source
0001CELL.LONG_IO_V[0]
0010CELL.DEC_V[0]
0111CELL.OUT_IO_WE_I2[1]
1111off
xc4000a IO_W1 switchbox INT muxes LONG_H[4]
BitsDestination
MAIN[13][9]MAIN[8][8]MAIN[9][9]MAIN[9][8]CELL.LONG_H[4]
Source
0001CELL.LONG_IO_V[1]
0010CELL.DEC_V[1]
0111CELL.OUT_IO_WE_I2[0]
1111off
xc4000a IO_W1 switchbox INT muxes LONG_IO_V[0]
BitsDestination
MAIN[2][4]MAIN[0][5]MAIN[3][5]MAIN[1][5]MAIN[2][5]CELL.LONG_IO_V[0]
Source
00011CELL.SINGLE_H[0]
00101CELL.LONG_H[0]
00110CELL.LONG_H[3]
01111CELL.SINGLE_H[2]
11111off
xc4000a IO_W1 switchbox INT muxes LONG_IO_V[1]
BitsDestination
MAIN[5][9]MAIN[1][8]MAIN[3][9]MAIN[2][8]MAIN[2][9]CELL.LONG_IO_V[1]
Source
00011CELL.SINGLE_H[3]
00101CELL.LONG_H[2]
00110CELL.LONG_H[4]
01111CELL.SINGLE_H[1]
11111off
xc4000a IO_W1 switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[0][1]MAIN[1][1]MAIN[4][1]MAIN[3][1]MAIN[2][1]CELL.IMUX_TBUF_I[0]
Source
00011CELL.DOUBLE_IO_W0[1]
00101CELL.OUT_IO_WE_I2[1]
00110CELL.DEC_V[1]
01111CELL.DOUBLE_IO_W1[1]
10011CELL.LONG_IO_V[1]
10101CELL.LONG_IO_V[0]
10110CELL.OUT_IO_WE_I2[0]
11111CELL.TIE_0
xc4000a IO_W1 switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[11][1]MAIN[9][1]MAIN[10][1]MAIN[10][0]MAIN[11][0]CELL.IMUX_TBUF_I[1]
Source
00011CELL.DOUBLE_IO_W1[1]
00101CELL.LONG_IO_V[0]
00110CELL.LONG_IO_V[1]
01111CELL.DOUBLE_IO_W0[1]
10011CELL.OUT_IO_WE_I2[0]
10101CELL.DEC_V[0]
10110CELL.OUT_IO_WE_I2[1]
11111CELL.TIE_0
xc4000a IO_W1 switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[5][0]MAIN[4][0]MAIN[6][1]MAIN[5][1]MAIN[6][0]CELL.IMUX_TBUF_T[0]
Source
00011CELL.DOUBLE_IO_W0[0]
00110CELL.DEC_V[1]
01111CELL.TIE_1
10011CELL.LONG_IO_V[1]
10101CELL.DOUBLE_IO_W1[0]
10110CELL.LONG_IO_V[0]
11111CELL.TIE_0
xc4000a IO_W1 switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[9][0]MAIN[7][1]MAIN[8][0]MAIN[8][1]MAIN[7][0]CELL.IMUX_TBUF_T[1]
Source
00011CELL.DOUBLE_IO_W0[0]
00110CELL.DEC_V[1]
01111CELL.TIE_1
10011CELL.LONG_IO_V[1]
10101CELL.DOUBLE_IO_W1[0]
10110CELL.LONG_IO_V[0]
11111CELL.TIE_0
xc4000a IO_W1 switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[12][9]MAIN[6][9]MAIN[7][9]MAIN[10][9]MAIN[10][8]CELL.IMUX_IO_O1[0]
Source
00011CELL.DOUBLE_H0[0]
00101CELL.LONG_H[4]
01111CELL.DOUBLE_H1[1]
10011CELL.LONG_H[3]
10101CELL.DEC_V[0]
10110CELL.DEC_V[1]
11111CELL.TIE_0
xc4000a IO_W1 switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[12][0]MAIN[13][1]MAIN[14][0]MAIN[14][1]MAIN[12][1]CELL.IMUX_IO_O1[1]
Source
00101CELL.DEC_V[1]
00111CELL.LONG_H[0]
01001CELL.DEC_V[0]
01011CELL.LONG_H[2]
01110CELL_S.DOUBLE_H0[1]
11101CELL_S.DOUBLE_H1[0]
11111CELL.TIE_0
xc4000a IO_W1 switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[9][7]MAIN[12][7]MAIN[15][8]MAIN[11][7]MAIN[14][7]MAIN[15][7]MAIN[13][7]MAIN[14][8]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_H[0]
01011111CELL.SINGLE_H[2]
01101111CELL.SINGLE_H[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[1]
xc4000a IO_W1 switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[8][2]MAIN[9][2]MAIN[15][2]MAIN[10][2]MAIN[13][2]MAIN[17][2]MAIN[16][2]MAIN[14][2]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[0]
01111101CELL_S.SINGLE_H[1]
01111110CELL_S.SINGLE_H[3]
11111111CELL_S.SINGLE_H[2]
xc4000a IO_W1 switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[10][7]MAIN[12][6]MAIN[14][6]MAIN[17][6]MAIN[11][6]MAIN[10][6]MAIN[15][6]MAIN[16][6]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_H[1]
01011111CELL.SINGLE_H[2]
01101111CELL.SINGLE_H[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[0]
xc4000a IO_W1 switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[10][3]MAIN[11][2]MAIN[14][3]MAIN[11][3]MAIN[12][2]MAIN[16][3]MAIN[17][3]MAIN[12][3]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[0]
01111101CELL_S.SINGLE_H[1]
01111110CELL_S.SINGLE_H[2]
11111111CELL_S.SINGLE_H[3]
xc4000a IO_W1 switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[1][3]MAIN[4][2]MAIN[5][2]MAIN[2][2]MAIN[2][3]MAIN[1][2]CELL.IMUX_IO_T[0]
Source
001111CELL.TIE_0
010011CELL.GCLK[0]
010101CELL.DOUBLE_IO_W1[1]
010110CELL.DEC_V[0]
011011CELL.DOUBLE_IO_W1[0]
011101CELL.LONG_IO_V[1]
011110CELL.LONG_IO_V[0]
110111CELL.DOUBLE_IO_W0[1]
111111CELL.DOUBLE_IO_W0[0]
xc4000a IO_W1 switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[6][3]MAIN[7][2]MAIN[8][3]MAIN[3][2]MAIN[7][3]MAIN[6][2]CELL.IMUX_IO_T[1]
Source
001111CELL.TIE_0
010011CELL.GCLK[0]
010111CELL.DOUBLE_IO_W0[0]
011001CELL.DOUBLE_IO_W0[1]
011010CELL.DEC_V[0]
011101CELL.LONG_IO_V[1]
011110CELL.LONG_IO_V[0]
111011CELL.DOUBLE_IO_W1[1]
111111CELL.DOUBLE_IO_W1[0]

Bels TBUF

xc4000a IO_W1 bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000a IO_W1 bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[0][3]!MAIN[9][3]

Bels IO

xc4000a IO_W1 bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[17][7]CELL.IMUX_IO_IK[1] invert by !MAIN[15][5]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[11][8]CELL.IMUX_IO_OK[1] invert by !MAIN[18][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_G3_WCELL.IMUX_CLB_F3_W
TinCELL.IMUX_IO_T[0] invert by !MAIN[19][9]CELL.IMUX_IO_T[1] invert by !MAIN[17][0]
I1outCELL.OUT_IO_WE_I1[0]CELL.OUT_IO_WE_I1[1]
I2outCELL.OUT_IO_WE_I2[0]CELL.OUT_IO_WE_I2[1]
xc4000a IO_W1 bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[16][7]!MAIN[18][2]
OFF_SRVAL bit 0!MAIN[13][8]!MAIN[18][1]
READBACK_I1 bit 0!MAIN[18][5]!MAIN[19][5]
READBACK_I2 bit 0!MAIN[16][8]!MAIN[20][5]
READBACK_OQ bit 0!MAIN[18][9]!MAIN[16][1]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[17][8]!MAIN[19][1]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[19][8]MAIN[20][2]
xc4000a IO_W1 enum IO_SLEW
IO[0].SLEWMAIN[14][9]MAIN[11][9]
IO[1].SLEWMAIN[19][0]MAIN[13][0]
FAST00
MEDFAST01
MEDSLOW10
SLOW11
xc4000a IO_W1 enum IO_PULL
IO[0].PULLMAIN[5][8]MAIN[18][8]
IO[1].PULLMAIN[20][1]MAIN[20][0]
NONE11
PULLUP01
PULLDOWN10
xc4000a IO_W1 enum IO_MUX_I
IO[0].MUX_I1MAIN[18][6]MAIN[20][6]MAIN[19][6]
IO[1].MUX_I1MAIN[18][4]MAIN[20][4]MAIN[19][4]
IO[0].MUX_I2MAIN[18][7]MAIN[20][7]MAIN[19][7]
IO[1].MUX_I2MAIN[18][3]MAIN[20][3]MAIN[19][3]
I001
IQ111
IQL010
xc4000a IO_W1 enum IO_IFF_D
IO[0].IFF_DMAIN[20][8]
IO[1].IFF_DMAIN[19][2]
I1
DELAY0
xc4000a IO_W1 enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[12][8]
IO[1].MUX_OFF_DMAIN[17][1]
O11
O20
xc4000a IO_W1 enum IO_MUX_O
IO[0].MUX_OMAIN[17][9]MAIN[16][9]MAIN[15][9]
IO[1].MUX_OMAIN[15][1]MAIN[16][0]MAIN[15][0]
O1001
O1_INV010
O2100
O2_INV011
OQ000

Bels DEC

xc4000a IO_W1 bel DEC pins
PinDirectionDEC[0]DEC[1]DEC[2]
IinCELL.OUT_IO_WE_I1[0]CELL.IMUX_CLB_C3_WCELL.OUT_IO_WE_I1[1]
O1bidirCELL.DEC_V[0]CELL.DEC_V[0]CELL.DEC_V[0]
O2bidirCELL.DEC_V[1]CELL.DEC_V[1]CELL.DEC_V[1]
xc4000a IO_W1 bel DEC attribute bits
AttributeDEC[0]DEC[1]DEC[2]
O1_P!MAIN[13][4]!MAIN[13][5]MAIN[14][5]
O1_NMAIN[13][3]MAIN[13][6]!MAIN[14][4]
O2_P!MAIN[15][4]!MAIN[17][5]MAIN[16][4]
O2_NMAIN[15][3]MAIN[17][4]!MAIN[16][5]

Bels PULLUP

xc4000a IO_W1 bel PULLUP pins
PinDirectionPULLUP_TBUF[0]PULLUP_TBUF[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000a IO_W1 bel PULLUP attribute bits
AttributePULLUP_TBUF[0]PULLUP_TBUF[1]
ENABLE!MAIN_S[0][9]!MAIN[8][9]

Bel wires

xc4000a IO_W1 bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]TBUF[1].O, PULLUP_TBUF[1].O
CELL.DEC_V[0]DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_V[1]DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.IMUX_CLB_F3_WIO[1].O2
CELL.IMUX_CLB_G3_WIO[0].O2
CELL.IMUX_CLB_C3_WDEC[1].I
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_WE_I1[0]IO[0].I1, DEC[0].I
CELL.OUT_IO_WE_I1[1]IO[1].I1, DEC[2].I
CELL.OUT_IO_WE_I2[0]IO[0].I2
CELL.OUT_IO_WE_I2[1]IO[1].I2

Bitstream

xc4000a IO_W1 rect MAIN
BitFrame
F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - IO[0]: !invert T IO[0]: ! READBACK_OQ bit 0 IO[0]: MUX_O bit 2 IO[0]: MUX_O bit 1 IO[0]: MUX_O bit 0 IO[0]: SLEW bit 1 INT: mux CELL.LONG_H[4] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 4 IO[0]: SLEW bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.LONG_H[4] bit 1 PULLUP_TBUF[1]: ! ENABLE INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.LONG_IO_V[1] bit 4 INT: mux CELL.DBUF_IO_V[1] bit 0 INT: mux CELL.LONG_IO_V[1] bit 2 INT: mux CELL.LONG_IO_V[1] bit 0 - -
B8 IO[0]: IFF_D bit 0 IO[0]: OFF_USED IO[0]: PULL bit 0 IO[0]: ! OFF_D_INV IO[0]: ! READBACK_I2 bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: mux CELL.IMUX_IO_OK[0] bit 0 IO[0]: ! OFF_SRVAL bit 0 IO[0]: MUX_OFF_D bit 0 IO[0]: !invert OK INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.LONG_H[4] bit 0 INT: mux CELL.LONG_H[4] bit 2 INT: mux CELL.DBUF_IO_V[1] bit 1 INT: !pass CELL.DOUBLE_IO_W2[0] ← CELL.DBUF_IO_V[0] IO[0]: PULL bit 1 INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W2[1] INT: !pass CELL.DOUBLE_IO_W2[1] ← CELL.DBUF_IO_V[0] INT: mux CELL.LONG_IO_V[1] bit 1 INT: mux CELL.LONG_IO_V[1] bit 3 INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W0[0]
B7 IO[0]: MUX_I2 bit 1 IO[0]: MUX_I2 bit 0 IO[0]: MUX_I2 bit 2 IO[0]: !invert IK IO[0]: ! IFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 7 INT: mux CELL.IMUX_IO_OK[0] bit 7 INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[1] INT: !pass CELL.SINGLE_H[2] ← CELL.DEC_V[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W1[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W1[0] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W0[0]
B6 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I1 bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 5 DEC[1]: O1_N INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2[0] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.DOUBLE_IO_W0[1] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W2[0] INT: !bipass CELL.DOUBLE_IO_W0[0] = CELL.DOUBLE_IO_W2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W2[0] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W2[0]
B5 IO[1]: ! READBACK_I2 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[0]: ! READBACK_I1 bit 0 DEC[1]: ! O2_P DEC[2]: ! O2_N IO[1]: !invert IK DEC[2]: O1_P DEC[1]: ! O1_P INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.SINGLE_H[1] ← CELL.DEC_V[0] INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[0] INT: !pass CELL.SINGLE_H[3] ← CELL.LONG_IO_V[1] INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[1] INT: !pass CELL.DOUBLE_IO_W0[0] ← CELL.DBUF_IO_V[1] INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2_S1 INT: mux CELL.LONG_IO_V[0] bit 2 INT: mux CELL.LONG_IO_V[0] bit 0 INT: mux CELL.LONG_IO_V[0] bit 1 INT: mux CELL.LONG_IO_V[0] bit 3
B4 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 2 DEC[1]: O2_N DEC[2]: O2_P DEC[0]: ! O2_P DEC[2]: ! O1_N DEC[0]: ! O1_P INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.DOUBLE_IO_W0[1] ← CELL.DBUF_IO_V[1] INT: !pass CELL.SINGLE_H[0] ← CELL.LONG_IO_V[0] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[0] INT: mux CELL.LONG_IO_V[0] bit 4 INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W0[0] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W1[0]
B3 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I2 bit 0 IO[1]: MUX_I2 bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 DEC[0]: O2_N INT: mux CELL.IMUX_IO_IK[1] bit 5 DEC[0]: O1_N INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 7 TBUF[1]: ! DRIVE1 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 5 - INT: mux CELL.DBUF_IO_V[0] bit 1 INT: mux CELL.DBUF_IO_V[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 5 TBUF[0]: ! DRIVE1
B2 IO[1]: OFF_USED IO[1]: IFF_D bit 0 IO[1]: ! IFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 7 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 0 -
B1 IO[1]: PULL bit 1 IO[1]: ! OFF_D_INV IO[1]: ! OFF_SRVAL bit 0 IO[1]: MUX_OFF_D bit 0 IO[1]: ! READBACK_OQ bit 0 IO[1]: MUX_O bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: mux CELL.IMUX_TBUF_I[0] bit 4
B0 IO[1]: PULL bit 0 IO[1]: SLEW bit 1 IO[1]: !invert OK IO[1]: !invert T IO[1]: MUX_O bit 1 IO[1]: MUX_O bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 2 IO[1]: SLEW bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 4 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.LONG_H[0] bit 0 INT: mux CELL.LONG_H[0] bit 1 INT: mux CELL.LONG_H[0] bit 3 INT: mux CELL.LONG_H[0] bit 2
xc4000a IO_W1 rect MAIN_S
BitFrame
F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - PULLUP_TBUF[0]: ! ENABLE
B8 - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - -

Tile IO_W1_S

Cells: 4

Switchbox INT

xc4000a IO_W1_S switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.LONG_IO_V[0]!MAIN[7][4]
CELL.SINGLE_H[0]CELL.DEC_V[1]!MAIN[8][7]
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I1[0]!MAIN[5][5]
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I2_S1!MAIN[5][4]
CELL.SINGLE_H[1]CELL.LONG_IO_V[1]!MAIN[7][5]
CELL.SINGLE_H[1]CELL.DEC_V[0]!MAIN[10][5]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I2[0]!MAIN[10][4]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I1_S1!MAIN[11][5]
CELL.SINGLE_H[2]CELL.LONG_IO_V[0]!MAIN[3][4]
CELL.SINGLE_H[2]CELL.DEC_V[1]!MAIN[7][7]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I1[0]!MAIN[6][4]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I2_S1!MAIN[4][4]
CELL.SINGLE_H[3]CELL.LONG_IO_V[1]!MAIN[8][5]
CELL.SINGLE_H[3]CELL.DEC_V[0]!MAIN[9][5]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I2[0]!MAIN[9][4]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I1_S1!MAIN[11][4]
CELL.DOUBLE_H0[0]CELL.OUT_IO_WE_I1_S1!MAIN[12][5]
CELL.DOUBLE_H0[1]CELL.OUT_IO_WE_I2[0]!MAIN[9][6]
CELL.DOUBLE_H1[0]CELL.OUT_IO_WE_I1[0]!MAIN[12][4]
CELL.DOUBLE_H1[1]CELL.OUT_IO_WE_I2_S1!MAIN[4][5]
CELL.DOUBLE_IO_W0[0]CELL.DBUF_IO_V[1]!MAIN[6][5]
CELL.DOUBLE_IO_W0[1]CELL.DBUF_IO_V[1]!MAIN[8][4]
CELL.DOUBLE_IO_W2[0]CELL.DBUF_IO_V[0]!MAIN[6][8]
CELL.DOUBLE_IO_W2[1]CELL.DBUF_IO_V[0]!MAIN[3][8]
xc4000a IO_W1_S switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.DOUBLE_IO_W1[0]!MAIN[2][7]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_W0[0]!MAIN[0][7]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_W2[0]!MAIN[3][6]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_W1[1]!MAIN[5][7]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_W0[1]!MAIN[4][7]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_W2[1]!MAIN[4][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W0[0]!MAIN[0][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W1[0]!MAIN[1][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_W2[0]!MAIN[1][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W0[1]!MAIN[6][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W1[1]!MAIN[7][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_W2[1]!MAIN[8][6]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W0[1]!MAIN[5][6]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W1[1]!MAIN[6][7]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_W2[1]!MAIN[3][7]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W0[0]!MAIN[1][4]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W1[0]!MAIN[0][4]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_W2[0]!MAIN[0][6]
CELL.DOUBLE_IO_W0[0]CELL.DOUBLE_IO_W2[0]!MAIN[2][6]
CELL.DOUBLE_IO_W0[1]CELL.DOUBLE_IO_W2[1]!MAIN[4][6]
xc4000a IO_W1_S switchbox INT muxes DBUF_IO_V[0]
BitsDestination
MAIN[4][3]MAIN[3][3]CELL.DBUF_IO_V[0]
Source
00CELL.DOUBLE_IO_W0[1]
11CELL.DOUBLE_IO_W0[0]
xc4000a IO_W1_S switchbox INT muxes DBUF_IO_V[1]
BitsDestination
MAIN[7][8]MAIN[4][9]CELL.DBUF_IO_V[1]
Source
00CELL.DOUBLE_IO_W2[0]
11CELL.DOUBLE_IO_W2[1]
xc4000a IO_W1_S switchbox INT muxes LONG_H[0]
BitsDestination
MAIN[1][0]MAIN[0][0]MAIN[2][0]MAIN[3][0]CELL.LONG_H[0]
Source
0001CELL.LONG_IO_V[0]
0010CELL.DEC_V[0]
0111CELL.OUT_IO_WE_I2[1]
1111off
xc4000a IO_W1_S switchbox INT muxes LONG_H[4]
BitsDestination
MAIN[13][9]MAIN[8][8]MAIN[9][9]MAIN[9][8]CELL.LONG_H[4]
Source
0001CELL.LONG_IO_V[1]
0010CELL.DEC_V[1]
0111CELL.OUT_IO_WE_I2[0]
1111off
xc4000a IO_W1_S switchbox INT muxes LONG_IO_V[0]
BitsDestination
MAIN[2][4]MAIN[0][5]MAIN[3][5]MAIN[1][5]MAIN[2][5]CELL.LONG_IO_V[0]
Source
00011CELL.SINGLE_H[0]
00101CELL.LONG_H[0]
00110CELL.LONG_H[3]
01111CELL.SINGLE_H[2]
11111off
xc4000a IO_W1_S switchbox INT muxes LONG_IO_V[1]
BitsDestination
MAIN[5][9]MAIN[1][8]MAIN[3][9]MAIN[2][8]MAIN[2][9]CELL.LONG_IO_V[1]
Source
00011CELL.SINGLE_H[3]
00101CELL.LONG_H[2]
00110CELL.LONG_H[4]
01111CELL.SINGLE_H[1]
11111off
xc4000a IO_W1_S switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[0][1]MAIN[1][1]MAIN[4][1]MAIN[3][1]MAIN[2][1]CELL.IMUX_TBUF_I[0]
Source
00011CELL.DOUBLE_IO_W0[1]
00101CELL.OUT_IO_WE_I2[1]
00110CELL.DEC_V[1]
01111CELL.DOUBLE_IO_W1[1]
10011CELL.LONG_IO_V[1]
10101CELL.LONG_IO_V[0]
10110CELL.OUT_IO_WE_I2[0]
11111CELL.TIE_0
xc4000a IO_W1_S switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[11][1]MAIN[9][1]MAIN[10][1]MAIN[10][0]MAIN[11][0]CELL.IMUX_TBUF_I[1]
Source
00011CELL.DOUBLE_IO_W1[1]
00101CELL.LONG_IO_V[0]
00110CELL.LONG_IO_V[1]
01111CELL.DOUBLE_IO_W0[1]
10011CELL.OUT_IO_WE_I2[0]
10101CELL.DEC_V[0]
10110CELL.OUT_IO_WE_I2[1]
11111CELL.TIE_0
xc4000a IO_W1_S switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[5][0]MAIN[4][0]MAIN[6][1]MAIN[5][1]MAIN[6][0]CELL.IMUX_TBUF_T[0]
Source
00011CELL.DOUBLE_IO_W0[0]
00110CELL.DEC_V[1]
01111CELL.TIE_1
10011CELL.LONG_IO_V[1]
10101CELL.DOUBLE_IO_W1[0]
10110CELL.LONG_IO_V[0]
11111CELL.TIE_0
xc4000a IO_W1_S switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[9][0]MAIN[7][1]MAIN[8][0]MAIN[8][1]MAIN[7][0]CELL.IMUX_TBUF_T[1]
Source
00011CELL.DOUBLE_IO_W0[0]
00110CELL.DEC_V[1]
01111CELL.TIE_1
10011CELL.LONG_IO_V[1]
10101CELL.DOUBLE_IO_W1[0]
10110CELL.LONG_IO_V[0]
11111CELL.TIE_0
xc4000a IO_W1_S switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[12][9]MAIN[6][9]MAIN[7][9]MAIN[10][9]MAIN[10][8]CELL.IMUX_IO_O1[0]
Source
00011CELL.DOUBLE_H0[0]
00101CELL.LONG_H[4]
01111CELL.DOUBLE_H1[1]
10011CELL.LONG_H[3]
10101CELL.DEC_V[0]
10110CELL.DEC_V[1]
11111CELL.TIE_0
xc4000a IO_W1_S switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[12][0]MAIN[13][1]MAIN[14][0]MAIN[14][1]MAIN[12][1]CELL.IMUX_IO_O1[1]
Source
00101CELL.DEC_V[1]
00111CELL.LONG_H[0]
01001CELL.DEC_V[0]
01011CELL.LONG_H[2]
01110CELL_S.DOUBLE_H0[1]
11101CELL_S.DOUBLE_H1[0]
11111CELL.TIE_0
xc4000a IO_W1_S switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[9][7]MAIN[12][7]MAIN[15][8]MAIN[11][7]MAIN[14][7]MAIN[15][7]MAIN[13][7]MAIN[14][8]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_H[0]
01011111CELL.SINGLE_H[2]
01101111CELL.SINGLE_H[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[1]
xc4000a IO_W1_S switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[8][2]MAIN[9][2]MAIN[15][2]MAIN[10][2]MAIN[13][2]MAIN[17][2]MAIN[16][2]MAIN[14][2]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[0]
01111101CELL_S.SINGLE_H[1]
01111110CELL_S.SINGLE_H[3]
11111111CELL_S.SINGLE_H[2]
xc4000a IO_W1_S switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[10][7]MAIN[12][6]MAIN[14][6]MAIN[17][6]MAIN[11][6]MAIN[10][6]MAIN[15][6]MAIN[16][6]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_H[1]
01011111CELL.SINGLE_H[2]
01101111CELL.SINGLE_H[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[0]
xc4000a IO_W1_S switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[10][3]MAIN[11][2]MAIN[14][3]MAIN[11][3]MAIN[12][2]MAIN[16][3]MAIN[17][3]MAIN[12][3]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[0]
01111101CELL_S.SINGLE_H[1]
01111110CELL_S.SINGLE_H[2]
11111111CELL_S.SINGLE_H[3]
xc4000a IO_W1_S switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[1][3]MAIN[4][2]MAIN[5][2]MAIN[2][2]MAIN[2][3]MAIN[1][2]CELL.IMUX_IO_T[0]
Source
001111CELL.TIE_0
010011CELL.GCLK[0]
010101CELL.DOUBLE_IO_W1[1]
010110CELL.DEC_V[0]
011011CELL.DOUBLE_IO_W1[0]
011101CELL.LONG_IO_V[1]
011110CELL.LONG_IO_V[0]
110111CELL.DOUBLE_IO_W0[1]
111111CELL.DOUBLE_IO_W0[0]
xc4000a IO_W1_S switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[6][3]MAIN[7][2]MAIN[8][3]MAIN[3][2]MAIN[7][3]MAIN[6][2]CELL.IMUX_IO_T[1]
Source
001111CELL.TIE_0
010011CELL.GCLK[0]
010111CELL.DOUBLE_IO_W0[0]
011001CELL.DOUBLE_IO_W0[1]
011010CELL.DEC_V[0]
011101CELL.LONG_IO_V[1]
011110CELL.LONG_IO_V[0]
111011CELL.DOUBLE_IO_W1[1]
111111CELL.DOUBLE_IO_W1[0]

Bels TBUF

xc4000a IO_W1_S bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000a IO_W1_S bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[0][3]!MAIN[9][3]

Bels IO

xc4000a IO_W1_S bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[17][7]CELL.IMUX_IO_IK[1] invert by !MAIN[15][5]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[11][8]CELL.IMUX_IO_OK[1] invert by !MAIN[18][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_G3_WCELL.IMUX_CLB_F3_W
TinCELL.IMUX_IO_T[0] invert by !MAIN[19][9]CELL.IMUX_IO_T[1] invert by !MAIN[17][0]
I1outCELL.OUT_IO_WE_I1[0]CELL.OUT_IO_WE_I1[1]
I2outCELL.OUT_IO_WE_I2[0]CELL.OUT_IO_WE_I2[1]
CLKINout-CELL.OUT_IO_CLKIN
xc4000a IO_W1_S bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[16][7]!MAIN[18][2]
OFF_SRVAL bit 0!MAIN[13][8]!MAIN[18][1]
READBACK_I1 bit 0!MAIN[18][5]!MAIN[19][5]
READBACK_I2 bit 0!MAIN[16][8]!MAIN[20][5]
READBACK_OQ bit 0!MAIN[18][9]!MAIN[16][1]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[17][8]!MAIN[19][1]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[19][8]MAIN[20][2]
xc4000a IO_W1_S enum IO_SLEW
IO[0].SLEWMAIN[14][9]MAIN[11][9]
IO[1].SLEWMAIN[19][0]MAIN[13][0]
FAST00
MEDFAST01
MEDSLOW10
SLOW11
xc4000a IO_W1_S enum IO_PULL
IO[0].PULLMAIN[5][8]MAIN[18][8]
IO[1].PULLMAIN[20][1]MAIN[20][0]
NONE11
PULLUP01
PULLDOWN10
xc4000a IO_W1_S enum IO_MUX_I
IO[0].MUX_I1MAIN[18][6]MAIN[20][6]MAIN[19][6]
IO[1].MUX_I1MAIN[18][4]MAIN[20][4]MAIN[19][4]
IO[0].MUX_I2MAIN[18][7]MAIN[20][7]MAIN[19][7]
IO[1].MUX_I2MAIN[18][3]MAIN[20][3]MAIN[19][3]
I001
IQ111
IQL010
xc4000a IO_W1_S enum IO_IFF_D
IO[0].IFF_DMAIN[20][8]
IO[1].IFF_DMAIN[19][2]
I1
DELAY0
xc4000a IO_W1_S enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[12][8]
IO[1].MUX_OFF_DMAIN[17][1]
O11
O20
xc4000a IO_W1_S enum IO_MUX_O
IO[0].MUX_OMAIN[17][9]MAIN[16][9]MAIN[15][9]
IO[1].MUX_OMAIN[15][1]MAIN[16][0]MAIN[15][0]
O1001
O1_INV010
O2100
O2_INV011
OQ000

Bels DEC

xc4000a IO_W1_S bel DEC pins
PinDirectionDEC[0]DEC[1]DEC[2]
IinCELL.OUT_IO_WE_I1[0]CELL.IMUX_CLB_C3_WCELL.OUT_IO_WE_I1[1]
O1bidirCELL.DEC_V[0]CELL.DEC_V[0]CELL.DEC_V[0]
O2bidirCELL.DEC_V[1]CELL.DEC_V[1]CELL.DEC_V[1]
xc4000a IO_W1_S bel DEC attribute bits
AttributeDEC[0]DEC[1]DEC[2]
O1_P!MAIN[13][4]!MAIN[13][5]MAIN[14][5]
O1_NMAIN[13][3]MAIN[13][6]!MAIN[14][4]
O2_P!MAIN[15][4]!MAIN[17][5]MAIN[16][4]
O2_NMAIN[15][3]MAIN[17][4]!MAIN[16][5]

Bels PULLUP

xc4000a IO_W1_S bel PULLUP pins
PinDirectionPULLUP_TBUF[0]PULLUP_TBUF[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000a IO_W1_S bel PULLUP attribute bits
AttributePULLUP_TBUF[0]PULLUP_TBUF[1]
ENABLE!MAIN_S[3][5]!MAIN[8][9]

Bel wires

xc4000a IO_W1_S bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]TBUF[1].O, PULLUP_TBUF[1].O
CELL.DEC_V[0]DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_V[1]DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.IMUX_CLB_F3_WIO[1].O2
CELL.IMUX_CLB_G3_WIO[0].O2
CELL.IMUX_CLB_C3_WDEC[1].I
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_WE_I1[0]IO[0].I1, DEC[0].I
CELL.OUT_IO_WE_I1[1]IO[1].I1, DEC[2].I
CELL.OUT_IO_WE_I2[0]IO[0].I2
CELL.OUT_IO_WE_I2[1]IO[1].I2
CELL.OUT_IO_CLKINIO[1].CLKIN

Bitstream

xc4000a IO_W1_S rect MAIN
BitFrame
F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - IO[0]: !invert T IO[0]: ! READBACK_OQ bit 0 IO[0]: MUX_O bit 2 IO[0]: MUX_O bit 1 IO[0]: MUX_O bit 0 IO[0]: SLEW bit 1 INT: mux CELL.LONG_H[4] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 4 IO[0]: SLEW bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.LONG_H[4] bit 1 PULLUP_TBUF[1]: ! ENABLE INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.LONG_IO_V[1] bit 4 INT: mux CELL.DBUF_IO_V[1] bit 0 INT: mux CELL.LONG_IO_V[1] bit 2 INT: mux CELL.LONG_IO_V[1] bit 0 - -
B8 IO[0]: IFF_D bit 0 IO[0]: OFF_USED IO[0]: PULL bit 0 IO[0]: ! OFF_D_INV IO[0]: ! READBACK_I2 bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: mux CELL.IMUX_IO_OK[0] bit 0 IO[0]: ! OFF_SRVAL bit 0 IO[0]: MUX_OFF_D bit 0 IO[0]: !invert OK INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.LONG_H[4] bit 0 INT: mux CELL.LONG_H[4] bit 2 INT: mux CELL.DBUF_IO_V[1] bit 1 INT: !pass CELL.DOUBLE_IO_W2[0] ← CELL.DBUF_IO_V[0] IO[0]: PULL bit 1 INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W2[1] INT: !pass CELL.DOUBLE_IO_W2[1] ← CELL.DBUF_IO_V[0] INT: mux CELL.LONG_IO_V[1] bit 1 INT: mux CELL.LONG_IO_V[1] bit 3 INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W0[0]
B7 IO[0]: MUX_I2 bit 1 IO[0]: MUX_I2 bit 0 IO[0]: MUX_I2 bit 2 IO[0]: !invert IK IO[0]: ! IFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 7 INT: mux CELL.IMUX_IO_OK[0] bit 7 INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[1] INT: !pass CELL.SINGLE_H[2] ← CELL.DEC_V[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W1[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W1[0] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W0[0]
B6 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I1 bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 5 DEC[1]: O1_N INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2[0] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W1[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W0[1] INT: !bipass CELL.DOUBLE_IO_W0[1] = CELL.DOUBLE_IO_W2[1] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W2[0] INT: !bipass CELL.DOUBLE_IO_W0[0] = CELL.DOUBLE_IO_W2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W2[0] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W2[0]
B5 IO[1]: ! READBACK_I2 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[0]: ! READBACK_I1 bit 0 DEC[1]: ! O2_P DEC[2]: ! O2_N IO[1]: !invert IK DEC[2]: O1_P DEC[1]: ! O1_P INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.SINGLE_H[1] ← CELL.DEC_V[0] INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[0] INT: !pass CELL.SINGLE_H[3] ← CELL.LONG_IO_V[1] INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[1] INT: !pass CELL.DOUBLE_IO_W0[0] ← CELL.DBUF_IO_V[1] INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2_S1 INT: mux CELL.LONG_IO_V[0] bit 2 INT: mux CELL.LONG_IO_V[0] bit 0 INT: mux CELL.LONG_IO_V[0] bit 1 INT: mux CELL.LONG_IO_V[0] bit 3
B4 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 2 DEC[1]: O2_N DEC[2]: O2_P DEC[0]: ! O2_P DEC[2]: ! O1_N DEC[0]: ! O1_P INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.DOUBLE_IO_W0[1] ← CELL.DBUF_IO_V[1] INT: !pass CELL.SINGLE_H[0] ← CELL.LONG_IO_V[0] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[0] INT: mux CELL.LONG_IO_V[0] bit 4 INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W0[0] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W1[0]
B3 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I2 bit 0 IO[1]: MUX_I2 bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 DEC[0]: O2_N INT: mux CELL.IMUX_IO_IK[1] bit 5 DEC[0]: O1_N INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 7 TBUF[1]: ! DRIVE1 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 5 - INT: mux CELL.DBUF_IO_V[0] bit 1 INT: mux CELL.DBUF_IO_V[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 5 TBUF[0]: ! DRIVE1
B2 IO[1]: OFF_USED IO[1]: IFF_D bit 0 IO[1]: ! IFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 7 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 0 -
B1 IO[1]: PULL bit 1 IO[1]: ! OFF_D_INV IO[1]: ! OFF_SRVAL bit 0 IO[1]: MUX_OFF_D bit 0 IO[1]: ! READBACK_OQ bit 0 IO[1]: MUX_O bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: mux CELL.IMUX_TBUF_I[0] bit 4
B0 IO[1]: PULL bit 0 IO[1]: SLEW bit 1 IO[1]: !invert OK IO[1]: !invert T IO[1]: MUX_O bit 1 IO[1]: MUX_O bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 2 IO[1]: SLEW bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 4 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.LONG_H[0] bit 0 INT: mux CELL.LONG_H[0] bit 1 INT: mux CELL.LONG_H[0] bit 3 INT: mux CELL.LONG_H[0] bit 2
xc4000a IO_W1_S rect MAIN_S
BitFrame
F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - PULLUP_TBUF[0]: ! ENABLE - - -
B4 - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - -

Tile IO_E0

Cells: 3

Switchbox INT

xc4000a IO_E0 switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[0]!MAIN_S[29][9]
CELL.LONG_H[2]CELL.SINGLE_V[1]!MAIN[22][5]
CELL.LONG_H[3]CELL.SINGLE_V[2]!MAIN[24][9]
CELL.LONG_H[4]CELL.SINGLE_V[3]!MAIN[26][9]
CELL.LONG_V[0]CELL.SINGLE_H_E[0]!MAIN[30][6]
CELL.LONG_V[1]CELL.SINGLE_H_E[1]!MAIN[28][5]
CELL.LONG_V[2]CELL.SINGLE_H[2]!MAIN[27][5]
CELL.LONG_V[3]CELL.SINGLE_H[3]!MAIN[27][7]
xc4000a IO_E0 switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.LONG_IO_V[0]!MAIN[13][4]
CELL.SINGLE_H[0]CELL.DEC_V[0]!MAIN[12][7]
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I1[0]!MAIN[15][5]
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I2_S1!MAIN[15][4]
CELL.SINGLE_H[1]CELL.LONG_IO_V[1]!MAIN[13][5]
CELL.SINGLE_H[1]CELL.DEC_V[1]!MAIN[10][5]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I2[0]!MAIN[10][4]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I1_S1!MAIN[9][5]
CELL.SINGLE_H[2]CELL.LONG_V[2]!MAIN[25][5]
CELL.SINGLE_H[2]CELL.LONG_IO_V[0]!MAIN[17][4]
CELL.SINGLE_H[2]CELL.DEC_V[0]!MAIN[13][7]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I1[0]!MAIN[14][4]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I2_S1!MAIN[16][4]
CELL.SINGLE_H[3]CELL.LONG_V[3]!MAIN[27][6]
CELL.SINGLE_H[3]CELL.LONG_IO_V[1]!MAIN[12][5]
CELL.SINGLE_H[3]CELL.DEC_V[1]!MAIN[11][5]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I2[0]!MAIN[11][4]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I1_S1!MAIN[9][4]
CELL.SINGLE_H_E[0]CELL.LONG_V[0]!MAIN[31][6]
CELL.SINGLE_H_E[1]CELL.LONG_V[1]!MAIN[30][5]
CELL.SINGLE_V[0]CELL.LONG_H[0]!MAIN_S[30][9]
CELL.SINGLE_V[0]CELL.OUT_CLB_Y_E!MAIN[31][5]
CELL.SINGLE_V[0]CELL.OUT_IO_WE_I2[0]!MAIN[30][4]
CELL.SINGLE_V[1]CELL.LONG_H[2]!MAIN_S[21][9]
CELL.SINGLE_V[1]CELL.OUT_CLB_YQ_E!MAIN[27][4]
CELL.SINGLE_V[1]CELL.OUT_IO_WE_I2[1]!MAIN[24][5]
CELL.SINGLE_V[2]CELL.LONG_H[3]!MAIN[31][9]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[29][5]
CELL.SINGLE_V[2]CELL.OUT_IO_WE_I2[0]!MAIN[29][4]
CELL.SINGLE_V[3]CELL.LONG_H[4]!MAIN[25][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[25][4]
CELL.SINGLE_V[3]CELL.OUT_IO_WE_I2[1]!MAIN[23][5]
CELL.DOUBLE_H0[0]CELL.OUT_IO_WE_I1[0]!MAIN[8][4]
CELL.DOUBLE_H0[1]CELL.OUT_IO_WE_I2_S1!MAIN[16][5]
CELL.DOUBLE_H1[0]CELL.OUT_IO_WE_I1_S1!MAIN[8][5]
CELL.DOUBLE_H1[1]CELL.OUT_IO_WE_I2[0]!MAIN[11][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[26][4]
CELL.DOUBLE_V0[1]CELL.OUT_IO_WE_I2[1]!MAIN[21][5]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[26][5]
CELL.DOUBLE_V1[1]CELL.OUT_IO_WE_I2[0]!MAIN[23][4]
CELL.DOUBLE_IO_E0[0]CELL.DBUF_IO_V[0]!MAIN[14][8]
CELL.DOUBLE_IO_E0[1]CELL.DBUF_IO_V[0]!MAIN[17][8]
CELL.DOUBLE_IO_E2[0]CELL.DBUF_IO_V[1]!MAIN[14][5]
CELL.DOUBLE_IO_E2[1]CELL.DBUF_IO_V[1]!MAIN[12][4]
xc4000a IO_E0 switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[28][7]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[29][6]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[28][6]
CELL.SINGLE_H[0]CELL.DOUBLE_IO_E0[0]!MAIN[17][6]
CELL.SINGLE_H[0]CELL.DOUBLE_IO_E2[0]!MAIN[20][7]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[19][8]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[21][4]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[18][8]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_E1[0]!MAIN[18][7]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[28][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[29][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[27][9]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_E0[1]!MAIN[16][8]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_E2[1]!MAIN[16][7]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[24][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[22][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[23][7]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_E1[1]!MAIN[15][7]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[29][7]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[31][7]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[22][9]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[21][8]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[28][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[31][8]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[26][6]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[26][7]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[30][7]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[23][9]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[30][8]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[25][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[25][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[27][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[24][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E0[1]!MAIN[17][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E1[1]!MAIN[14][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E2[1]!MAIN[15][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[23][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[21][7]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[21][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E0[0]!MAIN[20][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E1[0]!MAIN[20][4]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E2[0]!MAIN[19][4]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E0[0]!MAIN[19][6]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E1[0]!MAIN[19][7]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E2[0]!MAIN[20][8]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E0[1]!MAIN[12][6]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E1[1]!MAIN[13][6]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E2[1]!MAIN[14][6]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[26][8]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[23][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[24][6]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[25][6]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[22][6]
CELL.DOUBLE_IO_E0[0]CELL.DOUBLE_IO_E2[0]!MAIN[18][6]
CELL.DOUBLE_IO_E0[1]CELL.DOUBLE_IO_E2[1]!MAIN[16][6]
xc4000a IO_E0 switchbox INT muxes DBUF_IO_V[0]
BitsDestination
MAIN[17][3]MAIN[16][3]CELL.DBUF_IO_V[0]
Source
00CELL.DOUBLE_IO_E2[0]
11CELL.DOUBLE_IO_E2[1]
xc4000a IO_E0 switchbox INT muxes DBUF_IO_V[1]
BitsDestination
MAIN[14][9]MAIN[13][8]CELL.DBUF_IO_V[1]
Source
00CELL.DOUBLE_IO_E0[1]
11CELL.DOUBLE_IO_E0[0]
xc4000a IO_E0 switchbox INT muxes LONG_H[0]
BitsDestination
MAIN[19][0]MAIN[17][0]MAIN[18][0]MAIN[20][0]CELL.LONG_H[0]
Source
0001CELL.LONG_IO_V[0]
0010CELL.DEC_V[1]
0111CELL.OUT_IO_WE_I2[1]
1111off
xc4000a IO_E0 switchbox INT muxes LONG_H[4]
BitsDestination
MAIN[7][9]MAIN[11][8]MAIN[11][9]MAIN[12][8]CELL.LONG_H[4]
Source
0001CELL.LONG_IO_V[1]
0010CELL.DEC_V[0]
0111CELL.OUT_IO_WE_I2[0]
1111off
xc4000a IO_E0 switchbox INT muxes LONG_IO_V[0]
BitsDestination
MAIN[18][4]MAIN[17][5]MAIN[18][5]MAIN[20][5]MAIN[19][5]CELL.LONG_IO_V[0]
Source
00011CELL.SINGLE_H[0]
00101CELL.LONG_H[0]
00110CELL.LONG_H[3]
01111CELL.SINGLE_H[2]
11111off
xc4000a IO_E0 switchbox INT muxes LONG_IO_V[1]
BitsDestination
MAIN[16][9]MAIN[15][9]MAIN[17][9]MAIN[19][9]MAIN[18][9]CELL.LONG_IO_V[1]
Source
00011CELL.SINGLE_H[1]
00101CELL.LONG_H[2]
00110CELL.LONG_H[4]
01111CELL.SINGLE_H[3]
11111off
xc4000a IO_E0 switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[23][1]MAIN[24][1]MAIN[24][3]MAIN[21][0]MAIN[22][0]MAIN[23][0]MAIN[24][2]CELL.IMUX_CLB_F1
Source
0010011CELL.LONG_V[0]
0010101CELL.LONG_V[2]
0011111CELL.SINGLE_V[1]
0100011CELL.SINGLE_V[3]
0100101CELL.LONG_V[3]
0101111CELL.SINGLE_V[2]
0110010CELL.LONG_V[1]
0110100CELL.DOUBLE_V1[1]
0111110CELL.DOUBLE_V1[0]
1110011CELL.DOUBLE_V0[0]
1110101CELL.DOUBLE_V0[1]
1111111CELL.SINGLE_V[0]
xc4000a IO_E0 switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[31][1]MAIN[31][0]MAIN[31][2]MAIN[30][1]MAIN[31][3]MAIN[30][3]MAIN[30][0]MAIN[31][4]CELL.IMUX_CLB_F3
Source
00100111CELL.SINGLE_V[2]
00101011CELL.LONG_V[1]
00101101CELL.LONG_V[0]
00111111CELL.SINGLE_V[0]
01000111CELL.DOUBLE_V1[0]
01001011CELL.LONG_V[3]
01001101CELL.LONG_V[2]
01011111CELL.SINGLE_V[1]
01101110CELL.GCLK[0]
11100111CELL.DOUBLE_V1[1]
11101011CELL.SINGLE_V[3]
11101101CELL.DOUBLE_V0[0]
11111111CELL.DOUBLE_V0[1]
xc4000a IO_E0 switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[24][4]MAIN[24][0]MAIN[25][1]MAIN[25][2]MAIN[26][3]MAIN[25][3]MAIN[26][2]CELL.IMUX_CLB_G1
Source
0010011CELL.LONG_V[0]
0010101CELL.DOUBLE_V0[1]
0011111CELL.SINGLE_V[0]
0100011CELL.DOUBLE_V0[0]
0100101CELL.LONG_V[2]
0101111CELL.SINGLE_V[1]
0110010CELL.LONG_V[1]
0110100CELL.LONG_V[3]
0111110CELL.DOUBLE_V1[0]
1110011CELL.SINGLE_V[3]
1110101CELL.DOUBLE_V1[1]
1111111CELL.SINGLE_V[2]
xc4000a IO_E0 switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[28][2]MAIN[29][2]MAIN[28][3]MAIN[30][2]MAIN[29][0]MAIN[29][1]MAIN[29][3]MAIN[28][1]CELL.IMUX_CLB_G3
Source
00001111CELL.SPECIAL_CLB_CIN
00011101CELL.LONG_V[3]
00111111CELL.SINGLE_V[2]
01000111CELL.DOUBLE_V0[0]
01001011CELL.LONG_V[0]
01001110CELL.LONG_V[1]
01010101CELL.DOUBLE_V0[1]
01011001CELL.LONG_V[2]
01011100CELL.GCLK[0]
01110111CELL.SINGLE_V[0]
01111011CELL.SINGLE_V[1]
11001111CELL.SINGLE_V[3]
11011101CELL.DOUBLE_V1[1]
11111111CELL.DOUBLE_V1[0]
xc4000a IO_E0 switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[21][2]MAIN[22][2]MAIN[21][1]MAIN[21][3]MAIN[22][3]MAIN[23][2]MAIN[23][3]CELL.IMUX_CLB_C1
Source
0010011CELL.DOUBLE_V0[1]
0010110CELL.LONG_V[0]
0011111CELL.SINGLE_V[0]
0100011CELL.LONG_V[2]
0100110CELL.DOUBLE_V0[0]
0101111CELL.SINGLE_V[1]
0110001CELL.LONG_V[3]
0110100CELL.LONG_V[1]
0111101CELL.SINGLE_V[3]
1110011CELL.SINGLE_V[2]
1110110CELL.DOUBLE_V1[0]
1111111CELL.DOUBLE_V1[1]
xc4000a IO_E0 switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[26][1]MAIN[28][0]MAIN[25][0]MAIN[27][2]MAIN[27][3]MAIN[26][0]MAIN[27][1]MAIN[27][0]CELL.IMUX_CLB_C3
Source
00001111CELL.LONG_V[1]
00010111CELL.SINGLE_V[3]
00011011CELL.LONG_V[0]
00111111CELL.SINGLE_V[0]
01001101CELL.LONG_V[3]
01010101CELL.DOUBLE_V1[1]
01011001CELL.LONG_V[2]
01011110CELL.GCLK[2]
01111101CELL.DOUBLE_V0[1]
11001111CELL.SINGLE_V[2]
11010111CELL.DOUBLE_V1[0]
11011011CELL.DOUBLE_V0[0]
11111111CELL.SINGLE_V[1]
xc4000a IO_E0 switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[20][1]MAIN[16][1]MAIN[17][1]MAIN[19][1]MAIN[18][1]CELL.IMUX_TBUF_I[0]
Source
00011CELL.DOUBLE_IO_E2[1]
00101CELL.OUT_IO_WE_I2[1]
00110CELL.DEC_V[0]
01111CELL.DOUBLE_IO_E1[1]
10011CELL.LONG_IO_V[1]
10101CELL.LONG_IO_V[0]
10110CELL.OUT_IO_WE_I2[0]
11111CELL.TIE_0
xc4000a IO_E0 switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[9][1]MAIN[9][0]MAIN[10][1]MAIN[10][0]MAIN[11][1]CELL.IMUX_TBUF_I[1]
Source
00011CELL.DOUBLE_IO_E1[1]
00101CELL.LONG_IO_V[0]
00110CELL.LONG_IO_V[1]
01111CELL.DOUBLE_IO_E2[1]
10011CELL.OUT_IO_WE_I2[0]
10101CELL.DEC_V[1]
10110CELL.OUT_IO_WE_I2[1]
11111CELL.TIE_0
xc4000a IO_E0 switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[15][0]MAIN[14][1]MAIN[15][1]MAIN[16][0]MAIN[14][0]CELL.IMUX_TBUF_T[0]
Source
00101CELL.DOUBLE_IO_E2[0]
00110CELL.DEC_V[0]
01111CELL.TIE_1
10011CELL.DOUBLE_IO_E1[0]
10101CELL.LONG_IO_V[1]
10110CELL.LONG_IO_V[0]
11111CELL.TIE_0
xc4000a IO_E0 switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[12][1]MAIN[11][0]MAIN[13][1]MAIN[12][0]MAIN[13][0]CELL.IMUX_TBUF_T[1]
Source
00101CELL.DOUBLE_IO_E2[0]
00110CELL.DEC_V[0]
01111CELL.TIE_1
10011CELL.DOUBLE_IO_E1[0]
10101CELL.LONG_IO_V[1]
10110CELL.LONG_IO_V[0]
11111CELL.TIE_0
xc4000a IO_E0 switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[8][9]MAIN[9][9]MAIN[12][9]MAIN[13][9]MAIN[10][8]CELL.IMUX_IO_O1[0]
Source
00011CELL.DOUBLE_H1[0]
00101CELL.LONG_H[4]
01111CELL.DOUBLE_H0[1]
10011CELL.LONG_H[3]
10101CELL.DEC_V[1]
10110CELL.DEC_V[0]
11111CELL.TIE_0
xc4000a IO_E0 switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[6][0]MAIN[7][1]MAIN[8][0]MAIN[6][1]MAIN[8][1]CELL.IMUX_IO_O1[1]
Source
00101CELL.DEC_V[0]
00111CELL.LONG_H[0]
01001CELL.DEC_V[1]
01011CELL.LONG_H[2]
01110CELL_S.DOUBLE_H1[1]
11101CELL_S.DOUBLE_H0[0]
11111CELL.TIE_0
xc4000a IO_E0 switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[5][8]MAIN[8][7]MAIN[11][7]MAIN[9][7]MAIN[6][7]MAIN[5][7]MAIN[7][7]MAIN[6][8]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_H[0]
01011111CELL.SINGLE_H[1]
01101111CELL.SINGLE_H[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[2]
xc4000a IO_E0 switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[3][2]MAIN[11][2]MAIN[5][2]MAIN[10][2]MAIN[7][2]MAIN[4][2]MAIN[12][2]MAIN[6][2]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[1]
01111101CELL_S.SINGLE_H[2]
01111110CELL_S.SINGLE_H[3]
11111111CELL_S.SINGLE_H[0]
xc4000a IO_E0 switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[3][6]MAIN[10][7]MAIN[8][6]MAIN[6][6]MAIN[9][6]MAIN[10][6]MAIN[5][6]MAIN[4][6]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_H[0]
01011111CELL.SINGLE_H[1]
01101111CELL.SINGLE_H[2]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[3]
xc4000a IO_E0 switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[3][3]MAIN[9][2]MAIN[6][3]MAIN[9][3]MAIN[8][2]MAIN[4][3]MAIN[8][3]MAIN[10][3]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[0]
01111101CELL_S.SINGLE_H[2]
01111110CELL_S.SINGLE_H[3]
11111111CELL_S.SINGLE_H[1]
xc4000a IO_E0 switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[16][2]MAIN[17][2]MAIN[19][3]MAIN[15][2]MAIN[18][3]MAIN[19][2]CELL.IMUX_IO_T[0]
Source
001111CELL.TIE_0
010011CELL.GCLK[0]
010111CELL.DOUBLE_IO_E1[0]
011001CELL.DOUBLE_IO_E1[1]
011010CELL.DEC_V[1]
011101CELL.LONG_IO_V[1]
011110CELL.LONG_IO_V[0]
111011CELL.DOUBLE_IO_E2[1]
111111CELL.DOUBLE_IO_E2[0]
xc4000a IO_E0 switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[12][3]MAIN[18][2]MAIN[13][2]MAIN[13][3]MAIN[14][3]MAIN[14][2]CELL.IMUX_IO_T[1]
Source
001111CELL.TIE_0
010011CELL.GCLK[0]
010101CELL.DOUBLE_IO_E2[1]
010110CELL.DEC_V[1]
011011CELL.DOUBLE_IO_E2[0]
011101CELL.LONG_IO_V[1]
011110CELL.LONG_IO_V[0]
110111CELL.DOUBLE_IO_E1[1]
111111CELL.DOUBLE_IO_E1[0]

Bels TBUF

xc4000a IO_E0 bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000a IO_E0 bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[20][3]!MAIN[11][3]

Bels IO

xc4000a IO_E0 bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[3][7]CELL.IMUX_IO_IK[1] invert by !MAIN[5][5]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[9][8]CELL.IMUX_IO_OK[1] invert by !MAIN[2][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_G1CELL.IMUX_CLB_F1
TinCELL.IMUX_IO_T[0] invert by !MAIN[0][9]CELL.IMUX_IO_T[1] invert by !MAIN[3][0]
I1outCELL.OUT_IO_WE_I1[0]CELL.OUT_IO_WE_I1[1]
I2outCELL.OUT_IO_WE_I2[0]CELL.OUT_IO_WE_I2[1]
xc4000a IO_E0 bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[4][7]!MAIN[2][2]
OFF_SRVAL bit 0!MAIN[7][8]!MAIN[2][1]
READBACK_I1 bit 0!MAIN[2][5]!MAIN[1][5]
READBACK_I2 bit 0!MAIN[4][8]!MAIN[0][5]
READBACK_OQ bit 0!MAIN[2][9]!MAIN[4][1]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[3][8]!MAIN[1][1]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[1][8]MAIN[0][2]
xc4000a IO_E0 enum IO_SLEW
IO[0].SLEWMAIN[3][9]MAIN[6][9]
IO[1].SLEWMAIN[1][0]MAIN[7][0]
FAST00
MEDFAST01
MEDSLOW10
SLOW11
xc4000a IO_E0 enum IO_PULL
IO[0].PULLMAIN[15][8]MAIN[2][8]
IO[1].PULLMAIN[5][1]MAIN[0][0]
NONE11
PULLUP01
PULLDOWN10
xc4000a IO_E0 enum IO_MUX_I
IO[0].MUX_I1MAIN[0][6]MAIN[2][6]MAIN[1][6]
IO[1].MUX_I1MAIN[0][4]MAIN[2][4]MAIN[1][4]
IO[0].MUX_I2MAIN[0][7]MAIN[2][7]MAIN[1][7]
IO[1].MUX_I2MAIN[0][3]MAIN[2][3]MAIN[1][3]
I001
IQ111
IQL010
xc4000a IO_E0 enum IO_IFF_D
IO[0].IFF_DMAIN[0][8]
IO[1].IFF_DMAIN[1][2]
I1
DELAY0
xc4000a IO_E0 enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[8][8]
IO[1].MUX_OFF_DMAIN[3][1]
O11
O20
xc4000a IO_E0 enum IO_MUX_O
IO[0].MUX_OMAIN[1][9]MAIN[4][9]MAIN[5][9]
IO[1].MUX_OMAIN[0][1]MAIN[4][0]MAIN[5][0]
O1001
O1_INV010
O2100
O2_INV011
OQ000

Bels DEC

xc4000a IO_E0 bel DEC pins
PinDirectionDEC[0]DEC[1]DEC[2]
IinCELL.OUT_IO_WE_I1[0]CELL.IMUX_CLB_C1CELL.OUT_IO_WE_I1[1]
O1bidirCELL.DEC_V[0]CELL.DEC_V[0]CELL.DEC_V[0]
O2bidirCELL.DEC_V[1]CELL.DEC_V[1]CELL.DEC_V[1]
xc4000a IO_E0 bel DEC attribute bits
AttributeDEC[0]DEC[1]DEC[2]
O1_P!MAIN[5][4]!MAIN[3][5]MAIN[4][4]
O1_NMAIN[5][3]MAIN[3][4]!MAIN[4][5]
O2_P!MAIN[7][4]!MAIN[7][5]MAIN[6][5]
O2_NMAIN[7][3]MAIN[7][6]!MAIN[6][4]

Bels PULLUP

xc4000a IO_E0 bel PULLUP pins
PinDirectionPULLUP_TBUF[0]PULLUP_TBUF[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000a IO_E0 bel PULLUP attribute bits
AttributePULLUP_TBUF[0]PULLUP_TBUF[1]
ENABLE!MAIN_S[20][9]!MAIN[10][9]

Bel wires

xc4000a IO_E0 bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]TBUF[1].O, PULLUP_TBUF[1].O
CELL.DEC_V[0]DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_V[1]DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.IMUX_CLB_F1IO[1].O2
CELL.IMUX_CLB_G1IO[0].O2
CELL.IMUX_CLB_C1DEC[1].I
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_WE_I1[0]IO[0].I1, DEC[0].I
CELL.OUT_IO_WE_I1[1]IO[1].I1, DEC[2].I
CELL.OUT_IO_WE_I2[0]IO[0].I2
CELL.OUT_IO_WE_I2[1]IO[1].I2

Bitstream

xc4000a IO_E0 rect MAIN
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[3] - - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[3] INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[4] INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] - - INT: mux CELL.LONG_IO_V[1] bit 1 INT: mux CELL.LONG_IO_V[1] bit 0 INT: mux CELL.LONG_IO_V[1] bit 2 INT: mux CELL.LONG_IO_V[1] bit 4 INT: mux CELL.LONG_IO_V[1] bit 3 INT: mux CELL.DBUF_IO_V[1] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.LONG_H[4] bit 1 PULLUP_TBUF[1]: ! ENABLE INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.LONG_H[4] bit 3 IO[0]: SLEW bit 0 IO[0]: MUX_O bit 0 IO[0]: MUX_O bit 1 IO[0]: SLEW bit 1 IO[0]: ! READBACK_OQ bit 0 IO[0]: MUX_O bit 2 IO[0]: !invert T
B8 INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E2[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: !pass CELL.DOUBLE_IO_E0[1] ← CELL.DBUF_IO_V[0] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E0[1] IO[0]: PULL bit 1 INT: !pass CELL.DOUBLE_IO_E0[0] ← CELL.DBUF_IO_V[0] INT: mux CELL.DBUF_IO_V[1] bit 0 INT: mux CELL.LONG_H[4] bit 0 INT: mux CELL.LONG_H[4] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 0 IO[0]: !invert OK IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 7 IO[0]: ! READBACK_I2 bit 0 IO[0]: ! OFF_D_INV IO[0]: PULL bit 0 IO[0]: OFF_USED IO[0]: IFF_D bit 0
B7 INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E2[0] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E1[0] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E1[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E0[1] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E1[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E1[1] INT: !pass CELL.SINGLE_H[2] ← CELL.DEC_V[0] INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[0] INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 2 IO[0]: ! IFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 1 IO[0]: MUX_I2 bit 0 IO[0]: MUX_I2 bit 2
B6 INT: !pass CELL.SINGLE_H_E[0] ← CELL.LONG_V[0] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !pass CELL.SINGLE_H[3] ← CELL.LONG_V[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E0[0] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E0[0] INT: !bipass CELL.DOUBLE_IO_E0[0] = CELL.DOUBLE_IO_E2[0] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E0[0] INT: !bipass CELL.DOUBLE_IO_E0[1] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E1[1] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E0[1] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2[0] INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 5 DEC[1]: O2_N INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 7 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I1 bit 2
B5 INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[1] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[1] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H[2] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_V[2] INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_WE_I2[1] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_WE_I2[1] INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[1] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_WE_I2[1] INT: mux CELL.LONG_IO_V[0] bit 1 INT: mux CELL.LONG_IO_V[0] bit 0 INT: mux CELL.LONG_IO_V[0] bit 2 INT: mux CELL.LONG_IO_V[0] bit 3 INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.DOUBLE_IO_E2[0] ← CELL.DBUF_IO_V[1] INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[1] INT: !pass CELL.SINGLE_H[3] ← CELL.LONG_IO_V[1] INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[1] INT: !pass CELL.SINGLE_H[1] ← CELL.DEC_V[1] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1_S1 DEC[1]: ! O2_P DEC[2]: O2_P IO[1]: !invert IK DEC[2]: ! O1_N DEC[1]: ! O1_P IO[0]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I2 bit 0
B4 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_WE_I2[0] - INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_G1 bit 6 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_WE_I2[0] - INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E1[0] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E2[0] INT: mux CELL.LONG_IO_V[0] bit 4 INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[0] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[0] ← CELL.LONG_IO_V[0] INT: !pass CELL.DOUBLE_IO_E2[1] ← CELL.DBUF_IO_V[1] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1[0] DEC[0]: ! O2_P DEC[2]: ! O2_N DEC[0]: ! O1_P DEC[2]: O1_P DEC[1]: O1_N IO[1]: MUX_I1 bit 1 IO[1]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 2
B3 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 1 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 4 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 3 TBUF[0]: ! DRIVE1 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.DBUF_IO_V[0] bit 1 INT: mux CELL.DBUF_IO_V[0] bit 0 - INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 5 TBUF[1]: ! DRIVE1 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 1 DEC[0]: O2_N INT: mux CELL.IMUX_IO_IK[1] bit 5 DEC[0]: O1_N INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 7 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I2 bit 0 IO[1]: MUX_I2 bit 2
B2 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_G1 bit 3 INT: mux CELL.IMUX_CLB_F1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 6 - INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 5 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 7 IO[1]: ! IFF_SRVAL bit 0 IO[1]: IFF_D bit 0 IO[1]: OFF_USED
B1 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 1 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 6 - INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_IO_O1[1] bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 1 IO[1]: PULL bit 1 IO[1]: ! READBACK_OQ bit 0 IO[1]: MUX_OFF_D bit 0 IO[1]: ! OFF_SRVAL bit 0 IO[1]: ! OFF_D_INV IO[1]: MUX_O bit 2
B0 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_G3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.LONG_H[0] bit 0 INT: mux CELL.LONG_H[0] bit 3 INT: mux CELL.LONG_H[0] bit 1 INT: mux CELL.LONG_H[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 2 IO[1]: SLEW bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 4 IO[1]: MUX_O bit 0 IO[1]: MUX_O bit 1 IO[1]: !invert T IO[1]: !invert OK IO[1]: SLEW bit 1 IO[1]: PULL bit 0
xc4000a IO_E0 rect MAIN_S
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_H[0] INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[0] - - - - - - - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[2] PULLUP_TBUF[0]: ! ENABLE - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000a IO_E0 rect MAIN_W
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_E0_N

Cells: 3

Switchbox INT

xc4000a IO_E0_N switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[0]!MAIN_S[29][9]
CELL.LONG_H[2]CELL.SINGLE_V[1]!MAIN[22][5]
CELL.LONG_H[3]CELL.SINGLE_V[2]!MAIN[24][9]
CELL.LONG_H[4]CELL.SINGLE_V[3]!MAIN[26][9]
CELL.LONG_V[0]CELL.SINGLE_H_E[0]!MAIN[30][6]
CELL.LONG_V[1]CELL.SINGLE_H_E[1]!MAIN[28][5]
CELL.LONG_V[2]CELL.SINGLE_H[2]!MAIN[27][5]
CELL.LONG_V[3]CELL.SINGLE_H[3]!MAIN[27][7]
xc4000a IO_E0_N switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.LONG_IO_V[0]!MAIN[13][4]
CELL.SINGLE_H[0]CELL.DEC_V[0]!MAIN[12][7]
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I1[0]!MAIN[15][5]
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I2_S1!MAIN[15][4]
CELL.SINGLE_H[1]CELL.LONG_IO_V[1]!MAIN[13][5]
CELL.SINGLE_H[1]CELL.DEC_V[1]!MAIN[10][5]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I2[0]!MAIN[10][4]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I1_S1!MAIN[9][5]
CELL.SINGLE_H[2]CELL.LONG_V[2]!MAIN[25][5]
CELL.SINGLE_H[2]CELL.LONG_IO_V[0]!MAIN[17][4]
CELL.SINGLE_H[2]CELL.DEC_V[0]!MAIN[13][7]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I1[0]!MAIN[14][4]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I2_S1!MAIN[16][4]
CELL.SINGLE_H[3]CELL.LONG_V[3]!MAIN[27][6]
CELL.SINGLE_H[3]CELL.LONG_IO_V[1]!MAIN[12][5]
CELL.SINGLE_H[3]CELL.DEC_V[1]!MAIN[11][5]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I2[0]!MAIN[11][4]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I1_S1!MAIN[9][4]
CELL.SINGLE_H_E[0]CELL.LONG_V[0]!MAIN[31][6]
CELL.SINGLE_H_E[1]CELL.LONG_V[1]!MAIN[30][5]
CELL.SINGLE_V[0]CELL.LONG_H[0]!MAIN_S[30][9]
CELL.SINGLE_V[0]CELL.OUT_CLB_Y_E!MAIN[31][5]
CELL.SINGLE_V[0]CELL.OUT_IO_WE_I2[0]!MAIN[30][4]
CELL.SINGLE_V[1]CELL.LONG_H[2]!MAIN_S[21][9]
CELL.SINGLE_V[1]CELL.OUT_CLB_YQ_E!MAIN[27][4]
CELL.SINGLE_V[1]CELL.OUT_IO_WE_I2[1]!MAIN[24][5]
CELL.SINGLE_V[2]CELL.LONG_H[3]!MAIN[31][9]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[29][5]
CELL.SINGLE_V[2]CELL.OUT_IO_WE_I2[0]!MAIN[29][4]
CELL.SINGLE_V[3]CELL.LONG_H[4]!MAIN[25][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[25][4]
CELL.SINGLE_V[3]CELL.OUT_IO_WE_I2[1]!MAIN[23][5]
CELL.DOUBLE_H0[0]CELL.OUT_IO_WE_I1[0]!MAIN[8][4]
CELL.DOUBLE_H0[1]CELL.OUT_IO_WE_I2_S1!MAIN[16][5]
CELL.DOUBLE_H1[0]CELL.OUT_IO_WE_I1_S1!MAIN[8][5]
CELL.DOUBLE_H1[1]CELL.OUT_IO_WE_I2[0]!MAIN[11][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[26][4]
CELL.DOUBLE_V0[1]CELL.OUT_IO_WE_I2[1]!MAIN[21][5]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[26][5]
CELL.DOUBLE_V1[1]CELL.OUT_IO_WE_I2[0]!MAIN[23][4]
CELL.DOUBLE_IO_E0[0]CELL.DBUF_IO_V[0]!MAIN[14][8]
CELL.DOUBLE_IO_E0[1]CELL.DBUF_IO_V[0]!MAIN[17][8]
CELL.DOUBLE_IO_E2[0]CELL.DBUF_IO_V[1]!MAIN[14][5]
CELL.DOUBLE_IO_E2[1]CELL.DBUF_IO_V[1]!MAIN[12][4]
xc4000a IO_E0_N switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[28][7]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[29][6]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[28][6]
CELL.SINGLE_H[0]CELL.DOUBLE_IO_E0[0]!MAIN[17][6]
CELL.SINGLE_H[0]CELL.DOUBLE_IO_E2[0]!MAIN[20][7]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[19][8]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[21][4]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[18][8]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_E1[0]!MAIN[18][7]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[28][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[29][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[27][9]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_E0[1]!MAIN[16][8]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_E2[1]!MAIN[16][7]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[24][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[22][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[23][7]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_E1[1]!MAIN[15][7]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[29][7]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[31][7]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[22][9]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[21][8]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[28][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[31][8]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[26][6]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[26][7]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[30][7]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[23][9]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[30][8]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[25][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[25][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[27][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[24][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E0[1]!MAIN[17][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E1[1]!MAIN[14][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E2[1]!MAIN[15][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[23][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[21][7]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[21][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E0[0]!MAIN[20][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E1[0]!MAIN[20][4]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E2[0]!MAIN[19][4]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E0[0]!MAIN[19][6]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E1[0]!MAIN[19][7]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E2[0]!MAIN[20][8]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E0[1]!MAIN[12][6]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E1[1]!MAIN[13][6]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E2[1]!MAIN[14][6]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[26][8]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[23][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[24][6]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[25][6]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[22][6]
CELL.DOUBLE_IO_E0[0]CELL.DOUBLE_IO_E2[0]!MAIN[18][6]
CELL.DOUBLE_IO_E0[1]CELL.DOUBLE_IO_E2[1]!MAIN[16][6]
xc4000a IO_E0_N switchbox INT muxes DBUF_IO_V[0]
BitsDestination
MAIN[17][3]MAIN[16][3]CELL.DBUF_IO_V[0]
Source
00CELL.DOUBLE_IO_E2[0]
11CELL.DOUBLE_IO_E2[1]
xc4000a IO_E0_N switchbox INT muxes DBUF_IO_V[1]
BitsDestination
MAIN[14][9]MAIN[13][8]CELL.DBUF_IO_V[1]
Source
00CELL.DOUBLE_IO_E0[1]
11CELL.DOUBLE_IO_E0[0]
xc4000a IO_E0_N switchbox INT muxes LONG_H[0]
BitsDestination
MAIN[19][0]MAIN[17][0]MAIN[18][0]MAIN[20][0]CELL.LONG_H[0]
Source
0001CELL.LONG_IO_V[0]
0010CELL.DEC_V[1]
0111CELL.OUT_IO_WE_I2[1]
1111off
xc4000a IO_E0_N switchbox INT muxes LONG_H[4]
BitsDestination
MAIN[7][9]MAIN[11][8]MAIN[11][9]MAIN[12][8]CELL.LONG_H[4]
Source
0001CELL.LONG_IO_V[1]
0010CELL.DEC_V[0]
0111CELL.OUT_IO_WE_I2[0]
1111off
xc4000a IO_E0_N switchbox INT muxes LONG_IO_V[0]
BitsDestination
MAIN[18][4]MAIN[17][5]MAIN[18][5]MAIN[20][5]MAIN[19][5]CELL.LONG_IO_V[0]
Source
00011CELL.SINGLE_H[0]
00101CELL.LONG_H[0]
00110CELL.LONG_H[3]
01111CELL.SINGLE_H[2]
11111off
xc4000a IO_E0_N switchbox INT muxes LONG_IO_V[1]
BitsDestination
MAIN[16][9]MAIN[15][9]MAIN[17][9]MAIN[19][9]MAIN[18][9]CELL.LONG_IO_V[1]
Source
00011CELL.SINGLE_H[1]
00101CELL.LONG_H[2]
00110CELL.LONG_H[4]
01111CELL.SINGLE_H[3]
11111off
xc4000a IO_E0_N switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[23][1]MAIN[24][1]MAIN[24][3]MAIN[21][0]MAIN[22][0]MAIN[23][0]MAIN[24][2]CELL.IMUX_CLB_F1
Source
0010011CELL.LONG_V[0]
0010101CELL.LONG_V[2]
0011111CELL.SINGLE_V[1]
0100011CELL.SINGLE_V[3]
0100101CELL.LONG_V[3]
0101111CELL.SINGLE_V[2]
0110010CELL.LONG_V[1]
0110100CELL.DOUBLE_V1[1]
0111110CELL.DOUBLE_V1[0]
1110011CELL.DOUBLE_V0[0]
1110101CELL.DOUBLE_V0[1]
1111111CELL.SINGLE_V[0]
xc4000a IO_E0_N switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[31][1]MAIN[31][0]MAIN[31][2]MAIN[30][1]MAIN[31][3]MAIN[30][3]MAIN[30][0]MAIN[31][4]CELL.IMUX_CLB_F3
Source
00100111CELL.SINGLE_V[2]
00101011CELL.LONG_V[1]
00101101CELL.LONG_V[0]
00111111CELL.SINGLE_V[0]
01000111CELL.DOUBLE_V1[0]
01001011CELL.LONG_V[3]
01001101CELL.LONG_V[2]
01011111CELL.SINGLE_V[1]
01101110CELL.GCLK[0]
11100111CELL.DOUBLE_V1[1]
11101011CELL.SINGLE_V[3]
11101101CELL.DOUBLE_V0[0]
11111111CELL.DOUBLE_V0[1]
xc4000a IO_E0_N switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[24][4]MAIN[24][0]MAIN[25][1]MAIN[25][2]MAIN[26][3]MAIN[25][3]MAIN[26][2]CELL.IMUX_CLB_G1
Source
0010011CELL.LONG_V[0]
0010101CELL.DOUBLE_V0[1]
0011111CELL.SINGLE_V[0]
0100011CELL.DOUBLE_V0[0]
0100101CELL.LONG_V[2]
0101111CELL.SINGLE_V[1]
0110010CELL.LONG_V[1]
0110100CELL.LONG_V[3]
0111110CELL.DOUBLE_V1[0]
1110011CELL.SINGLE_V[3]
1110101CELL.DOUBLE_V1[1]
1111111CELL.SINGLE_V[2]
xc4000a IO_E0_N switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[28][2]MAIN[29][2]MAIN[28][3]MAIN[30][2]MAIN[29][0]MAIN[29][1]MAIN[29][3]MAIN[28][1]CELL.IMUX_CLB_G3
Source
00001111CELL.SPECIAL_CLB_CIN
00011101CELL.LONG_V[3]
00111111CELL.SINGLE_V[2]
01000111CELL.DOUBLE_V0[0]
01001011CELL.LONG_V[0]
01001110CELL.LONG_V[1]
01010101CELL.DOUBLE_V0[1]
01011001CELL.LONG_V[2]
01011100CELL.GCLK[0]
01110111CELL.SINGLE_V[0]
01111011CELL.SINGLE_V[1]
11001111CELL.SINGLE_V[3]
11011101CELL.DOUBLE_V1[1]
11111111CELL.DOUBLE_V1[0]
xc4000a IO_E0_N switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[21][2]MAIN[22][2]MAIN[21][1]MAIN[21][3]MAIN[22][3]MAIN[23][2]MAIN[23][3]CELL.IMUX_CLB_C1
Source
0010011CELL.DOUBLE_V0[1]
0010110CELL.LONG_V[0]
0011111CELL.SINGLE_V[0]
0100011CELL.LONG_V[2]
0100110CELL.DOUBLE_V0[0]
0101111CELL.SINGLE_V[1]
0110001CELL.LONG_V[3]
0110100CELL.LONG_V[1]
0111101CELL.SINGLE_V[3]
1110011CELL.SINGLE_V[2]
1110110CELL.DOUBLE_V1[0]
1111111CELL.DOUBLE_V1[1]
xc4000a IO_E0_N switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[26][1]MAIN[28][0]MAIN[25][0]MAIN[27][2]MAIN[27][3]MAIN[26][0]MAIN[27][1]MAIN[27][0]CELL.IMUX_CLB_C3
Source
00001111CELL.LONG_V[1]
00010111CELL.SINGLE_V[3]
00011011CELL.LONG_V[0]
00111111CELL.SINGLE_V[0]
01001101CELL.LONG_V[3]
01010101CELL.DOUBLE_V1[1]
01011001CELL.LONG_V[2]
01011110CELL.GCLK[2]
01111101CELL.DOUBLE_V0[1]
11001111CELL.SINGLE_V[2]
11010111CELL.DOUBLE_V1[0]
11011011CELL.DOUBLE_V0[0]
11111111CELL.SINGLE_V[1]
xc4000a IO_E0_N switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[20][1]MAIN[16][1]MAIN[17][1]MAIN[19][1]MAIN[18][1]CELL.IMUX_TBUF_I[0]
Source
00011CELL.DOUBLE_IO_E2[1]
00101CELL.OUT_IO_WE_I2[1]
00110CELL.DEC_V[0]
01111CELL.DOUBLE_IO_E1[1]
10011CELL.LONG_IO_V[1]
10101CELL.LONG_IO_V[0]
10110CELL.OUT_IO_WE_I2[0]
11111CELL.TIE_0
xc4000a IO_E0_N switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[9][1]MAIN[9][0]MAIN[10][1]MAIN[10][0]MAIN[11][1]CELL.IMUX_TBUF_I[1]
Source
00011CELL.DOUBLE_IO_E1[1]
00101CELL.LONG_IO_V[0]
00110CELL.LONG_IO_V[1]
01111CELL.DOUBLE_IO_E2[1]
10011CELL.OUT_IO_WE_I2[0]
10101CELL.DEC_V[1]
10110CELL.OUT_IO_WE_I2[1]
11111CELL.TIE_0
xc4000a IO_E0_N switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[15][0]MAIN[14][1]MAIN[15][1]MAIN[16][0]MAIN[14][0]CELL.IMUX_TBUF_T[0]
Source
00101CELL.DOUBLE_IO_E2[0]
00110CELL.DEC_V[0]
01111CELL.TIE_1
10011CELL.DOUBLE_IO_E1[0]
10101CELL.LONG_IO_V[1]
10110CELL.LONG_IO_V[0]
11111CELL.TIE_0
xc4000a IO_E0_N switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[12][1]MAIN[11][0]MAIN[13][1]MAIN[12][0]MAIN[13][0]CELL.IMUX_TBUF_T[1]
Source
00101CELL.DOUBLE_IO_E2[0]
00110CELL.DEC_V[0]
01111CELL.TIE_1
10011CELL.DOUBLE_IO_E1[0]
10101CELL.LONG_IO_V[1]
10110CELL.LONG_IO_V[0]
11111CELL.TIE_0
xc4000a IO_E0_N switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[8][9]MAIN[9][9]MAIN[12][9]MAIN[13][9]MAIN[10][8]CELL.IMUX_IO_O1[0]
Source
00011CELL.DOUBLE_H1[0]
00101CELL.LONG_H[4]
01111CELL.DOUBLE_H0[1]
10011CELL.LONG_H[3]
10101CELL.DEC_V[1]
10110CELL.DEC_V[0]
11111CELL.TIE_0
xc4000a IO_E0_N switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[6][0]MAIN[7][1]MAIN[8][0]MAIN[6][1]MAIN[8][1]CELL.IMUX_IO_O1[1]
Source
00101CELL.DEC_V[0]
00111CELL.LONG_H[0]
01001CELL.DEC_V[1]
01011CELL.LONG_H[2]
01110CELL_S.DOUBLE_H1[1]
11101CELL_S.DOUBLE_H0[0]
11111CELL.TIE_0
xc4000a IO_E0_N switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[5][8]MAIN[8][7]MAIN[11][7]MAIN[9][7]MAIN[6][7]MAIN[5][7]MAIN[7][7]MAIN[6][8]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_H[0]
01011111CELL.SINGLE_H[1]
01101111CELL.SINGLE_H[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[2]
xc4000a IO_E0_N switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[3][2]MAIN[11][2]MAIN[5][2]MAIN[10][2]MAIN[7][2]MAIN[4][2]MAIN[12][2]MAIN[6][2]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[1]
01111101CELL_S.SINGLE_H[2]
01111110CELL_S.SINGLE_H[3]
11111111CELL_S.SINGLE_H[0]
xc4000a IO_E0_N switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[3][6]MAIN[10][7]MAIN[8][6]MAIN[6][6]MAIN[9][6]MAIN[10][6]MAIN[5][6]MAIN[4][6]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_H[0]
01011111CELL.SINGLE_H[1]
01101111CELL.SINGLE_H[2]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[3]
xc4000a IO_E0_N switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[3][3]MAIN[9][2]MAIN[6][3]MAIN[9][3]MAIN[8][2]MAIN[4][3]MAIN[8][3]MAIN[10][3]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[0]
01111101CELL_S.SINGLE_H[2]
01111110CELL_S.SINGLE_H[3]
11111111CELL_S.SINGLE_H[1]
xc4000a IO_E0_N switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[16][2]MAIN[17][2]MAIN[19][3]MAIN[15][2]MAIN[18][3]MAIN[19][2]CELL.IMUX_IO_T[0]
Source
001111CELL.TIE_0
010011CELL.GCLK[0]
010111CELL.DOUBLE_IO_E1[0]
011001CELL.DOUBLE_IO_E1[1]
011010CELL.DEC_V[1]
011101CELL.LONG_IO_V[1]
011110CELL.LONG_IO_V[0]
111011CELL.DOUBLE_IO_E2[1]
111111CELL.DOUBLE_IO_E2[0]
xc4000a IO_E0_N switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[12][3]MAIN[18][2]MAIN[13][2]MAIN[13][3]MAIN[14][3]MAIN[14][2]CELL.IMUX_IO_T[1]
Source
001111CELL.TIE_0
010011CELL.GCLK[0]
010101CELL.DOUBLE_IO_E2[1]
010110CELL.DEC_V[1]
011011CELL.DOUBLE_IO_E2[0]
011101CELL.LONG_IO_V[1]
011110CELL.LONG_IO_V[0]
110111CELL.DOUBLE_IO_E1[1]
111111CELL.DOUBLE_IO_E1[0]

Bels TBUF

xc4000a IO_E0_N bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000a IO_E0_N bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[20][3]!MAIN[11][3]

Bels IO

xc4000a IO_E0_N bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[3][7]CELL.IMUX_IO_IK[1] invert by !MAIN[5][5]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[9][8]CELL.IMUX_IO_OK[1] invert by !MAIN[2][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_G1CELL.IMUX_CLB_F1
TinCELL.IMUX_IO_T[0] invert by !MAIN[0][9]CELL.IMUX_IO_T[1] invert by !MAIN[3][0]
I1outCELL.OUT_IO_WE_I1[0]CELL.OUT_IO_WE_I1[1]
I2outCELL.OUT_IO_WE_I2[0]CELL.OUT_IO_WE_I2[1]
CLKINoutCELL.OUT_IO_CLKIN-
xc4000a IO_E0_N bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[4][7]!MAIN[2][2]
OFF_SRVAL bit 0!MAIN[7][8]!MAIN[2][1]
READBACK_I1 bit 0!MAIN[2][5]!MAIN[1][5]
READBACK_I2 bit 0!MAIN[4][8]!MAIN[0][5]
READBACK_OQ bit 0!MAIN[2][9]!MAIN[4][1]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[3][8]!MAIN[1][1]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[1][8]MAIN[0][2]
xc4000a IO_E0_N enum IO_SLEW
IO[0].SLEWMAIN[3][9]MAIN[6][9]
IO[1].SLEWMAIN[1][0]MAIN[7][0]
FAST00
MEDFAST01
MEDSLOW10
SLOW11
xc4000a IO_E0_N enum IO_PULL
IO[0].PULLMAIN[15][8]MAIN[2][8]
IO[1].PULLMAIN[5][1]MAIN[0][0]
NONE11
PULLUP01
PULLDOWN10
xc4000a IO_E0_N enum IO_MUX_I
IO[0].MUX_I1MAIN[0][6]MAIN[2][6]MAIN[1][6]
IO[1].MUX_I1MAIN[0][4]MAIN[2][4]MAIN[1][4]
IO[0].MUX_I2MAIN[0][7]MAIN[2][7]MAIN[1][7]
IO[1].MUX_I2MAIN[0][3]MAIN[2][3]MAIN[1][3]
I001
IQ111
IQL010
xc4000a IO_E0_N enum IO_IFF_D
IO[0].IFF_DMAIN[0][8]
IO[1].IFF_DMAIN[1][2]
I1
DELAY0
xc4000a IO_E0_N enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[8][8]
IO[1].MUX_OFF_DMAIN[3][1]
O11
O20
xc4000a IO_E0_N enum IO_MUX_O
IO[0].MUX_OMAIN[1][9]MAIN[4][9]MAIN[5][9]
IO[1].MUX_OMAIN[0][1]MAIN[4][0]MAIN[5][0]
O1001
O1_INV010
O2100
O2_INV011
OQ000

Bels DEC

xc4000a IO_E0_N bel DEC pins
PinDirectionDEC[0]DEC[1]DEC[2]
IinCELL.OUT_IO_WE_I1[0]CELL.IMUX_CLB_C1CELL.OUT_IO_WE_I1[1]
O1bidirCELL.DEC_V[0]CELL.DEC_V[0]CELL.DEC_V[0]
O2bidirCELL.DEC_V[1]CELL.DEC_V[1]CELL.DEC_V[1]
xc4000a IO_E0_N bel DEC attribute bits
AttributeDEC[0]DEC[1]DEC[2]
O1_P!MAIN[5][4]!MAIN[3][5]MAIN[4][4]
O1_NMAIN[5][3]MAIN[3][4]!MAIN[4][5]
O2_P!MAIN[7][4]!MAIN[7][5]MAIN[6][5]
O2_NMAIN[7][3]MAIN[7][6]!MAIN[6][4]

Bels PULLUP

xc4000a IO_E0_N bel PULLUP pins
PinDirectionPULLUP_TBUF[0]PULLUP_TBUF[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000a IO_E0_N bel PULLUP attribute bits
AttributePULLUP_TBUF[0]PULLUP_TBUF[1]
ENABLE!MAIN_S[20][9]!MAIN[10][9]

Bel wires

xc4000a IO_E0_N bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]TBUF[1].O, PULLUP_TBUF[1].O
CELL.DEC_V[0]DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_V[1]DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.IMUX_CLB_F1IO[1].O2
CELL.IMUX_CLB_G1IO[0].O2
CELL.IMUX_CLB_C1DEC[1].I
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_WE_I1[0]IO[0].I1, DEC[0].I
CELL.OUT_IO_WE_I1[1]IO[1].I1, DEC[2].I
CELL.OUT_IO_WE_I2[0]IO[0].I2
CELL.OUT_IO_WE_I2[1]IO[1].I2
CELL.OUT_IO_CLKINIO[0].CLKIN

Bitstream

xc4000a IO_E0_N rect MAIN
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[3] - - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[3] INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[4] INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] - - INT: mux CELL.LONG_IO_V[1] bit 1 INT: mux CELL.LONG_IO_V[1] bit 0 INT: mux CELL.LONG_IO_V[1] bit 2 INT: mux CELL.LONG_IO_V[1] bit 4 INT: mux CELL.LONG_IO_V[1] bit 3 INT: mux CELL.DBUF_IO_V[1] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.LONG_H[4] bit 1 PULLUP_TBUF[1]: ! ENABLE INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.LONG_H[4] bit 3 IO[0]: SLEW bit 0 IO[0]: MUX_O bit 0 IO[0]: MUX_O bit 1 IO[0]: SLEW bit 1 IO[0]: ! READBACK_OQ bit 0 IO[0]: MUX_O bit 2 IO[0]: !invert T
B8 INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E2[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: !pass CELL.DOUBLE_IO_E0[1] ← CELL.DBUF_IO_V[0] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E0[1] IO[0]: PULL bit 1 INT: !pass CELL.DOUBLE_IO_E0[0] ← CELL.DBUF_IO_V[0] INT: mux CELL.DBUF_IO_V[1] bit 0 INT: mux CELL.LONG_H[4] bit 0 INT: mux CELL.LONG_H[4] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 0 IO[0]: !invert OK IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 7 IO[0]: ! READBACK_I2 bit 0 IO[0]: ! OFF_D_INV IO[0]: PULL bit 0 IO[0]: OFF_USED IO[0]: IFF_D bit 0
B7 INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E2[0] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E1[0] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E1[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E0[1] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E1[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E1[1] INT: !pass CELL.SINGLE_H[2] ← CELL.DEC_V[0] INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[0] INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 2 IO[0]: ! IFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 1 IO[0]: MUX_I2 bit 0 IO[0]: MUX_I2 bit 2
B6 INT: !pass CELL.SINGLE_H_E[0] ← CELL.LONG_V[0] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !pass CELL.SINGLE_H[3] ← CELL.LONG_V[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E0[0] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E0[0] INT: !bipass CELL.DOUBLE_IO_E0[0] = CELL.DOUBLE_IO_E2[0] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E0[0] INT: !bipass CELL.DOUBLE_IO_E0[1] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E1[1] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E0[1] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2[0] INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 5 DEC[1]: O2_N INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 7 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I1 bit 2
B5 INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[1] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[1] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H[2] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_V[2] INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_WE_I2[1] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_WE_I2[1] INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[1] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_WE_I2[1] INT: mux CELL.LONG_IO_V[0] bit 1 INT: mux CELL.LONG_IO_V[0] bit 0 INT: mux CELL.LONG_IO_V[0] bit 2 INT: mux CELL.LONG_IO_V[0] bit 3 INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.DOUBLE_IO_E2[0] ← CELL.DBUF_IO_V[1] INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[1] INT: !pass CELL.SINGLE_H[3] ← CELL.LONG_IO_V[1] INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[1] INT: !pass CELL.SINGLE_H[1] ← CELL.DEC_V[1] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1_S1 DEC[1]: ! O2_P DEC[2]: O2_P IO[1]: !invert IK DEC[2]: ! O1_N DEC[1]: ! O1_P IO[0]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I2 bit 0
B4 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_WE_I2[0] - INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_G1 bit 6 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_WE_I2[0] - INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E1[0] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E2[0] INT: mux CELL.LONG_IO_V[0] bit 4 INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[0] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[0] ← CELL.LONG_IO_V[0] INT: !pass CELL.DOUBLE_IO_E2[1] ← CELL.DBUF_IO_V[1] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1[0] DEC[0]: ! O2_P DEC[2]: ! O2_N DEC[0]: ! O1_P DEC[2]: O1_P DEC[1]: O1_N IO[1]: MUX_I1 bit 1 IO[1]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 2
B3 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 1 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 4 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 3 TBUF[0]: ! DRIVE1 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.DBUF_IO_V[0] bit 1 INT: mux CELL.DBUF_IO_V[0] bit 0 - INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 5 TBUF[1]: ! DRIVE1 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 1 DEC[0]: O2_N INT: mux CELL.IMUX_IO_IK[1] bit 5 DEC[0]: O1_N INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 7 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I2 bit 0 IO[1]: MUX_I2 bit 2
B2 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_G1 bit 3 INT: mux CELL.IMUX_CLB_F1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 6 - INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 5 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 7 IO[1]: ! IFF_SRVAL bit 0 IO[1]: IFF_D bit 0 IO[1]: OFF_USED
B1 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 1 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 6 - INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_IO_O1[1] bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 1 IO[1]: PULL bit 1 IO[1]: ! READBACK_OQ bit 0 IO[1]: MUX_OFF_D bit 0 IO[1]: ! OFF_SRVAL bit 0 IO[1]: ! OFF_D_INV IO[1]: MUX_O bit 2
B0 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_G3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.LONG_H[0] bit 0 INT: mux CELL.LONG_H[0] bit 3 INT: mux CELL.LONG_H[0] bit 1 INT: mux CELL.LONG_H[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 2 IO[1]: SLEW bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 4 IO[1]: MUX_O bit 0 IO[1]: MUX_O bit 1 IO[1]: !invert T IO[1]: !invert OK IO[1]: SLEW bit 1 IO[1]: PULL bit 0
xc4000a IO_E0_N rect MAIN_S
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_H[0] INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[0] - - - - - - - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[2] PULLUP_TBUF[0]: ! ENABLE - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000a IO_E0_N rect MAIN_W
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_E1

Cells: 3

Switchbox INT

xc4000a IO_E1 switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[0]!MAIN_S[29][9]
CELL.LONG_H[2]CELL.SINGLE_V[1]!MAIN[22][5]
CELL.LONG_H[3]CELL.SINGLE_V[2]!MAIN[24][9]
CELL.LONG_H[4]CELL.SINGLE_V[3]!MAIN[26][9]
CELL.LONG_V[0]CELL.SINGLE_H_E[0]!MAIN[30][6]
CELL.LONG_V[1]CELL.SINGLE_H_E[1]!MAIN[28][5]
CELL.LONG_V[2]CELL.SINGLE_H[2]!MAIN[27][5]
CELL.LONG_V[3]CELL.SINGLE_H[3]!MAIN[27][7]
xc4000a IO_E1 switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.LONG_IO_V[0]!MAIN[13][4]
CELL.SINGLE_H[0]CELL.DEC_V[0]!MAIN[12][7]
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I1[0]!MAIN[15][5]
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I2_S1!MAIN[15][4]
CELL.SINGLE_H[1]CELL.LONG_IO_V[1]!MAIN[13][5]
CELL.SINGLE_H[1]CELL.DEC_V[1]!MAIN[10][5]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I2[0]!MAIN[10][4]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I1_S1!MAIN[9][5]
CELL.SINGLE_H[2]CELL.LONG_V[2]!MAIN[25][5]
CELL.SINGLE_H[2]CELL.LONG_IO_V[0]!MAIN[17][4]
CELL.SINGLE_H[2]CELL.DEC_V[0]!MAIN[13][7]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I1[0]!MAIN[14][4]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I2_S1!MAIN[16][4]
CELL.SINGLE_H[3]CELL.LONG_V[3]!MAIN[27][6]
CELL.SINGLE_H[3]CELL.LONG_IO_V[1]!MAIN[12][5]
CELL.SINGLE_H[3]CELL.DEC_V[1]!MAIN[11][5]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I2[0]!MAIN[11][4]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I1_S1!MAIN[9][4]
CELL.SINGLE_H_E[0]CELL.LONG_V[0]!MAIN[31][6]
CELL.SINGLE_H_E[1]CELL.LONG_V[1]!MAIN[30][5]
CELL.SINGLE_V[0]CELL.LONG_H[0]!MAIN_S[30][9]
CELL.SINGLE_V[0]CELL.OUT_CLB_Y_E!MAIN[31][5]
CELL.SINGLE_V[0]CELL.OUT_IO_WE_I2[0]!MAIN[30][4]
CELL.SINGLE_V[1]CELL.LONG_H[2]!MAIN_S[21][9]
CELL.SINGLE_V[1]CELL.OUT_CLB_YQ_E!MAIN[27][4]
CELL.SINGLE_V[1]CELL.OUT_IO_WE_I2[1]!MAIN[24][5]
CELL.SINGLE_V[2]CELL.LONG_H[3]!MAIN[31][9]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[29][5]
CELL.SINGLE_V[2]CELL.OUT_IO_WE_I2[0]!MAIN[29][4]
CELL.SINGLE_V[3]CELL.LONG_H[4]!MAIN[25][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[25][4]
CELL.SINGLE_V[3]CELL.OUT_IO_WE_I2[1]!MAIN[23][5]
CELL.DOUBLE_H0[0]CELL.OUT_IO_WE_I1[0]!MAIN[8][4]
CELL.DOUBLE_H0[1]CELL.OUT_IO_WE_I2_S1!MAIN[16][5]
CELL.DOUBLE_H1[0]CELL.OUT_IO_WE_I1_S1!MAIN[8][5]
CELL.DOUBLE_H1[1]CELL.OUT_IO_WE_I2[0]!MAIN[11][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[26][4]
CELL.DOUBLE_V0[1]CELL.OUT_IO_WE_I2[1]!MAIN[21][5]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[26][5]
CELL.DOUBLE_V1[1]CELL.OUT_IO_WE_I2[0]!MAIN[23][4]
CELL.DOUBLE_IO_E0[0]CELL.DBUF_IO_V[0]!MAIN[14][8]
CELL.DOUBLE_IO_E0[1]CELL.DBUF_IO_V[0]!MAIN[17][8]
CELL.DOUBLE_IO_E2[0]CELL.DBUF_IO_V[1]!MAIN[14][5]
CELL.DOUBLE_IO_E2[1]CELL.DBUF_IO_V[1]!MAIN[12][4]
xc4000a IO_E1 switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[28][7]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[29][6]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[28][6]
CELL.SINGLE_H[0]CELL.DOUBLE_IO_E1[0]!MAIN[18][7]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[19][8]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[21][4]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[18][8]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_E0[0]!MAIN[17][6]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_E2[0]!MAIN[20][7]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[28][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[29][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[27][9]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_E1[1]!MAIN[15][7]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[24][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[22][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[23][7]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_E0[1]!MAIN[16][8]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_E2[1]!MAIN[16][7]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[29][7]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[31][7]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[22][9]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[21][8]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[28][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[31][8]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[26][6]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[26][7]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[30][7]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[23][9]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[30][8]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[25][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[25][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[27][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[24][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E0[1]!MAIN[17][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E1[1]!MAIN[14][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E2[1]!MAIN[15][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[23][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[21][7]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[21][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E0[0]!MAIN[20][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E1[0]!MAIN[20][4]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E2[0]!MAIN[19][4]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E0[0]!MAIN[19][6]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E1[0]!MAIN[19][7]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E2[0]!MAIN[20][8]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E0[1]!MAIN[12][6]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E1[1]!MAIN[13][6]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E2[1]!MAIN[14][6]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[26][8]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[23][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[24][6]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[25][6]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[22][6]
CELL.DOUBLE_IO_E0[0]CELL.DOUBLE_IO_E2[0]!MAIN[18][6]
CELL.DOUBLE_IO_E0[1]CELL.DOUBLE_IO_E2[1]!MAIN[16][6]
xc4000a IO_E1 switchbox INT muxes DBUF_IO_V[0]
BitsDestination
MAIN[17][3]MAIN[16][3]CELL.DBUF_IO_V[0]
Source
00CELL.DOUBLE_IO_E2[0]
11CELL.DOUBLE_IO_E2[1]
xc4000a IO_E1 switchbox INT muxes DBUF_IO_V[1]
BitsDestination
MAIN[14][9]MAIN[13][8]CELL.DBUF_IO_V[1]
Source
00CELL.DOUBLE_IO_E0[1]
11CELL.DOUBLE_IO_E0[0]
xc4000a IO_E1 switchbox INT muxes LONG_H[0]
BitsDestination
MAIN[19][0]MAIN[17][0]MAIN[18][0]MAIN[20][0]CELL.LONG_H[0]
Source
0001CELL.LONG_IO_V[0]
0010CELL.DEC_V[1]
0111CELL.OUT_IO_WE_I2[1]
1111off
xc4000a IO_E1 switchbox INT muxes LONG_H[4]
BitsDestination
MAIN[7][9]MAIN[11][8]MAIN[11][9]MAIN[12][8]CELL.LONG_H[4]
Source
0001CELL.LONG_IO_V[1]
0010CELL.DEC_V[0]
0111CELL.OUT_IO_WE_I2[0]
1111off
xc4000a IO_E1 switchbox INT muxes LONG_IO_V[0]
BitsDestination
MAIN[18][4]MAIN[17][5]MAIN[18][5]MAIN[20][5]MAIN[19][5]CELL.LONG_IO_V[0]
Source
00011CELL.SINGLE_H[0]
00101CELL.LONG_H[0]
00110CELL.LONG_H[3]
01111CELL.SINGLE_H[2]
11111off
xc4000a IO_E1 switchbox INT muxes LONG_IO_V[1]
BitsDestination
MAIN[16][9]MAIN[15][9]MAIN[17][9]MAIN[19][9]MAIN[18][9]CELL.LONG_IO_V[1]
Source
00011CELL.SINGLE_H[1]
00101CELL.LONG_H[2]
00110CELL.LONG_H[4]
01111CELL.SINGLE_H[3]
11111off
xc4000a IO_E1 switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[23][1]MAIN[24][1]MAIN[24][3]MAIN[21][0]MAIN[22][0]MAIN[23][0]MAIN[24][2]CELL.IMUX_CLB_F1
Source
0010011CELL.LONG_V[0]
0010101CELL.LONG_V[2]
0011111CELL.SINGLE_V[1]
0100011CELL.SINGLE_V[3]
0100101CELL.LONG_V[3]
0101111CELL.SINGLE_V[2]
0110010CELL.LONG_V[1]
0110100CELL.DOUBLE_V1[1]
0111110CELL.DOUBLE_V1[0]
1110011CELL.DOUBLE_V0[0]
1110101CELL.DOUBLE_V0[1]
1111111CELL.SINGLE_V[0]
xc4000a IO_E1 switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[31][1]MAIN[31][0]MAIN[31][2]MAIN[30][1]MAIN[31][3]MAIN[30][3]MAIN[30][0]MAIN[31][4]CELL.IMUX_CLB_F3
Source
00100111CELL.SINGLE_V[2]
00101011CELL.LONG_V[1]
00101101CELL.LONG_V[0]
00111111CELL.SINGLE_V[0]
01000111CELL.DOUBLE_V1[0]
01001011CELL.LONG_V[3]
01001101CELL.LONG_V[2]
01011111CELL.SINGLE_V[1]
01101110CELL.GCLK[0]
11100111CELL.DOUBLE_V1[1]
11101011CELL.SINGLE_V[3]
11101101CELL.DOUBLE_V0[0]
11111111CELL.DOUBLE_V0[1]
xc4000a IO_E1 switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[24][4]MAIN[24][0]MAIN[25][1]MAIN[25][2]MAIN[26][3]MAIN[25][3]MAIN[26][2]CELL.IMUX_CLB_G1
Source
0010011CELL.LONG_V[0]
0010101CELL.DOUBLE_V0[1]
0011111CELL.SINGLE_V[0]
0100011CELL.DOUBLE_V0[0]
0100101CELL.LONG_V[2]
0101111CELL.SINGLE_V[1]
0110010CELL.LONG_V[1]
0110100CELL.LONG_V[3]
0111110CELL.DOUBLE_V1[0]
1110011CELL.SINGLE_V[3]
1110101CELL.DOUBLE_V1[1]
1111111CELL.SINGLE_V[2]
xc4000a IO_E1 switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[28][2]MAIN[29][2]MAIN[28][3]MAIN[30][2]MAIN[29][0]MAIN[29][1]MAIN[29][3]MAIN[28][1]CELL.IMUX_CLB_G3
Source
00001111CELL.SPECIAL_CLB_CIN
00011101CELL.LONG_V[3]
00111111CELL.SINGLE_V[2]
01000111CELL.DOUBLE_V0[0]
01001011CELL.LONG_V[0]
01001110CELL.LONG_V[1]
01010101CELL.DOUBLE_V0[1]
01011001CELL.LONG_V[2]
01011100CELL.GCLK[0]
01110111CELL.SINGLE_V[0]
01111011CELL.SINGLE_V[1]
11001111CELL.SINGLE_V[3]
11011101CELL.DOUBLE_V1[1]
11111111CELL.DOUBLE_V1[0]
xc4000a IO_E1 switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[21][2]MAIN[22][2]MAIN[21][1]MAIN[21][3]MAIN[22][3]MAIN[23][2]MAIN[23][3]CELL.IMUX_CLB_C1
Source
0010011CELL.DOUBLE_V0[1]
0010110CELL.LONG_V[0]
0011111CELL.SINGLE_V[0]
0100011CELL.LONG_V[2]
0100110CELL.DOUBLE_V0[0]
0101111CELL.SINGLE_V[1]
0110001CELL.LONG_V[3]
0110100CELL.LONG_V[1]
0111101CELL.SINGLE_V[3]
1110011CELL.SINGLE_V[2]
1110110CELL.DOUBLE_V1[0]
1111111CELL.DOUBLE_V1[1]
xc4000a IO_E1 switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[26][1]MAIN[28][0]MAIN[25][0]MAIN[27][2]MAIN[27][3]MAIN[26][0]MAIN[27][1]MAIN[27][0]CELL.IMUX_CLB_C3
Source
00001111CELL.LONG_V[1]
00010111CELL.SINGLE_V[3]
00011011CELL.LONG_V[0]
00111111CELL.SINGLE_V[0]
01001101CELL.LONG_V[3]
01010101CELL.DOUBLE_V1[1]
01011001CELL.LONG_V[2]
01011110CELL.GCLK[2]
01111101CELL.DOUBLE_V0[1]
11001111CELL.SINGLE_V[2]
11010111CELL.DOUBLE_V1[0]
11011011CELL.DOUBLE_V0[0]
11111111CELL.SINGLE_V[1]
xc4000a IO_E1 switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[20][1]MAIN[16][1]MAIN[17][1]MAIN[19][1]MAIN[18][1]CELL.IMUX_TBUF_I[0]
Source
00011CELL.DOUBLE_IO_E2[1]
00101CELL.OUT_IO_WE_I2[1]
00110CELL.DEC_V[0]
01111CELL.DOUBLE_IO_E1[1]
10011CELL.LONG_IO_V[1]
10101CELL.LONG_IO_V[0]
10110CELL.OUT_IO_WE_I2[0]
11111CELL.TIE_0
xc4000a IO_E1 switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[9][1]MAIN[9][0]MAIN[10][1]MAIN[10][0]MAIN[11][1]CELL.IMUX_TBUF_I[1]
Source
00011CELL.DOUBLE_IO_E1[1]
00101CELL.LONG_IO_V[0]
00110CELL.LONG_IO_V[1]
01111CELL.DOUBLE_IO_E2[1]
10011CELL.OUT_IO_WE_I2[0]
10101CELL.DEC_V[1]
10110CELL.OUT_IO_WE_I2[1]
11111CELL.TIE_0
xc4000a IO_E1 switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[15][0]MAIN[14][1]MAIN[15][1]MAIN[16][0]MAIN[14][0]CELL.IMUX_TBUF_T[0]
Source
00101CELL.DOUBLE_IO_E2[0]
00110CELL.DEC_V[0]
01111CELL.TIE_1
10011CELL.DOUBLE_IO_E1[0]
10101CELL.LONG_IO_V[1]
10110CELL.LONG_IO_V[0]
11111CELL.TIE_0
xc4000a IO_E1 switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[12][1]MAIN[11][0]MAIN[13][1]MAIN[12][0]MAIN[13][0]CELL.IMUX_TBUF_T[1]
Source
00101CELL.DOUBLE_IO_E2[0]
00110CELL.DEC_V[0]
01111CELL.TIE_1
10011CELL.DOUBLE_IO_E1[0]
10101CELL.LONG_IO_V[1]
10110CELL.LONG_IO_V[0]
11111CELL.TIE_0
xc4000a IO_E1 switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[8][9]MAIN[9][9]MAIN[12][9]MAIN[13][9]MAIN[10][8]CELL.IMUX_IO_O1[0]
Source
00011CELL.DOUBLE_H1[0]
00101CELL.LONG_H[4]
01111CELL.DOUBLE_H0[1]
10011CELL.LONG_H[3]
10101CELL.DEC_V[1]
10110CELL.DEC_V[0]
11111CELL.TIE_0
xc4000a IO_E1 switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[6][0]MAIN[7][1]MAIN[8][0]MAIN[6][1]MAIN[8][1]CELL.IMUX_IO_O1[1]
Source
00101CELL.DEC_V[0]
00111CELL.LONG_H[0]
01001CELL.DEC_V[1]
01011CELL.LONG_H[2]
01110CELL_S.DOUBLE_H1[1]
11101CELL_S.DOUBLE_H0[0]
11111CELL.TIE_0
xc4000a IO_E1 switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[5][8]MAIN[8][7]MAIN[11][7]MAIN[9][7]MAIN[6][7]MAIN[5][7]MAIN[7][7]MAIN[6][8]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_H[0]
01011111CELL.SINGLE_H[1]
01101111CELL.SINGLE_H[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[2]
xc4000a IO_E1 switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[3][2]MAIN[11][2]MAIN[5][2]MAIN[10][2]MAIN[7][2]MAIN[4][2]MAIN[12][2]MAIN[6][2]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[1]
01111101CELL_S.SINGLE_H[2]
01111110CELL_S.SINGLE_H[3]
11111111CELL_S.SINGLE_H[0]
xc4000a IO_E1 switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[3][6]MAIN[10][7]MAIN[8][6]MAIN[6][6]MAIN[9][6]MAIN[10][6]MAIN[5][6]MAIN[4][6]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_H[0]
01011111CELL.SINGLE_H[1]
01101111CELL.SINGLE_H[2]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[3]
xc4000a IO_E1 switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[3][3]MAIN[9][2]MAIN[6][3]MAIN[9][3]MAIN[8][2]MAIN[4][3]MAIN[8][3]MAIN[10][3]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[0]
01111101CELL_S.SINGLE_H[2]
01111110CELL_S.SINGLE_H[3]
11111111CELL_S.SINGLE_H[1]
xc4000a IO_E1 switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[16][2]MAIN[17][2]MAIN[19][3]MAIN[15][2]MAIN[18][3]MAIN[19][2]CELL.IMUX_IO_T[0]
Source
001111CELL.TIE_0
010011CELL.GCLK[0]
010111CELL.DOUBLE_IO_E1[0]
011001CELL.DOUBLE_IO_E1[1]
011010CELL.DEC_V[1]
011101CELL.LONG_IO_V[1]
011110CELL.LONG_IO_V[0]
111011CELL.DOUBLE_IO_E2[1]
111111CELL.DOUBLE_IO_E2[0]
xc4000a IO_E1 switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[12][3]MAIN[18][2]MAIN[13][2]MAIN[13][3]MAIN[14][3]MAIN[14][2]CELL.IMUX_IO_T[1]
Source
001111CELL.TIE_0
010011CELL.GCLK[0]
010101CELL.DOUBLE_IO_E2[1]
010110CELL.DEC_V[1]
011011CELL.DOUBLE_IO_E2[0]
011101CELL.LONG_IO_V[1]
011110CELL.LONG_IO_V[0]
110111CELL.DOUBLE_IO_E1[1]
111111CELL.DOUBLE_IO_E1[0]

Bels TBUF

xc4000a IO_E1 bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000a IO_E1 bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[20][3]!MAIN[11][3]

Bels IO

xc4000a IO_E1 bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[3][7]CELL.IMUX_IO_IK[1] invert by !MAIN[5][5]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[9][8]CELL.IMUX_IO_OK[1] invert by !MAIN[2][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_G1CELL.IMUX_CLB_F1
TinCELL.IMUX_IO_T[0] invert by !MAIN[0][9]CELL.IMUX_IO_T[1] invert by !MAIN[3][0]
I1outCELL.OUT_IO_WE_I1[0]CELL.OUT_IO_WE_I1[1]
I2outCELL.OUT_IO_WE_I2[0]CELL.OUT_IO_WE_I2[1]
xc4000a IO_E1 bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[4][7]!MAIN[2][2]
OFF_SRVAL bit 0!MAIN[7][8]!MAIN[2][1]
READBACK_I1 bit 0!MAIN[2][5]!MAIN[1][5]
READBACK_I2 bit 0!MAIN[4][8]!MAIN[0][5]
READBACK_OQ bit 0!MAIN[2][9]!MAIN[4][1]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[3][8]!MAIN[1][1]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[1][8]MAIN[0][2]
xc4000a IO_E1 enum IO_SLEW
IO[0].SLEWMAIN[3][9]MAIN[6][9]
IO[1].SLEWMAIN[1][0]MAIN[7][0]
FAST00
MEDFAST01
MEDSLOW10
SLOW11
xc4000a IO_E1 enum IO_PULL
IO[0].PULLMAIN[15][8]MAIN[2][8]
IO[1].PULLMAIN[5][1]MAIN[0][0]
NONE11
PULLUP01
PULLDOWN10
xc4000a IO_E1 enum IO_MUX_I
IO[0].MUX_I1MAIN[0][6]MAIN[2][6]MAIN[1][6]
IO[1].MUX_I1MAIN[0][4]MAIN[2][4]MAIN[1][4]
IO[0].MUX_I2MAIN[0][7]MAIN[2][7]MAIN[1][7]
IO[1].MUX_I2MAIN[0][3]MAIN[2][3]MAIN[1][3]
I001
IQ111
IQL010
xc4000a IO_E1 enum IO_IFF_D
IO[0].IFF_DMAIN[0][8]
IO[1].IFF_DMAIN[1][2]
I1
DELAY0
xc4000a IO_E1 enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[8][8]
IO[1].MUX_OFF_DMAIN[3][1]
O11
O20
xc4000a IO_E1 enum IO_MUX_O
IO[0].MUX_OMAIN[1][9]MAIN[4][9]MAIN[5][9]
IO[1].MUX_OMAIN[0][1]MAIN[4][0]MAIN[5][0]
O1001
O1_INV010
O2100
O2_INV011
OQ000

Bels DEC

xc4000a IO_E1 bel DEC pins
PinDirectionDEC[0]DEC[1]DEC[2]
IinCELL.OUT_IO_WE_I1[0]CELL.IMUX_CLB_C1CELL.OUT_IO_WE_I1[1]
O1bidirCELL.DEC_V[0]CELL.DEC_V[0]CELL.DEC_V[0]
O2bidirCELL.DEC_V[1]CELL.DEC_V[1]CELL.DEC_V[1]
xc4000a IO_E1 bel DEC attribute bits
AttributeDEC[0]DEC[1]DEC[2]
O1_P!MAIN[5][4]!MAIN[3][5]MAIN[4][4]
O1_NMAIN[5][3]MAIN[3][4]!MAIN[4][5]
O2_P!MAIN[7][4]!MAIN[7][5]MAIN[6][5]
O2_NMAIN[7][3]MAIN[7][6]!MAIN[6][4]

Bels PULLUP

xc4000a IO_E1 bel PULLUP pins
PinDirectionPULLUP_TBUF[0]PULLUP_TBUF[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000a IO_E1 bel PULLUP attribute bits
AttributePULLUP_TBUF[0]PULLUP_TBUF[1]
ENABLE!MAIN_S[20][9]!MAIN[10][9]

Bel wires

xc4000a IO_E1 bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]TBUF[1].O, PULLUP_TBUF[1].O
CELL.DEC_V[0]DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_V[1]DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.IMUX_CLB_F1IO[1].O2
CELL.IMUX_CLB_G1IO[0].O2
CELL.IMUX_CLB_C1DEC[1].I
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_WE_I1[0]IO[0].I1, DEC[0].I
CELL.OUT_IO_WE_I1[1]IO[1].I1, DEC[2].I
CELL.OUT_IO_WE_I2[0]IO[0].I2
CELL.OUT_IO_WE_I2[1]IO[1].I2

Bitstream

xc4000a IO_E1 rect MAIN
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[3] - - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[3] INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[4] INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] - - INT: mux CELL.LONG_IO_V[1] bit 1 INT: mux CELL.LONG_IO_V[1] bit 0 INT: mux CELL.LONG_IO_V[1] bit 2 INT: mux CELL.LONG_IO_V[1] bit 4 INT: mux CELL.LONG_IO_V[1] bit 3 INT: mux CELL.DBUF_IO_V[1] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.LONG_H[4] bit 1 PULLUP_TBUF[1]: ! ENABLE INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.LONG_H[4] bit 3 IO[0]: SLEW bit 0 IO[0]: MUX_O bit 0 IO[0]: MUX_O bit 1 IO[0]: SLEW bit 1 IO[0]: ! READBACK_OQ bit 0 IO[0]: MUX_O bit 2 IO[0]: !invert T
B8 INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E2[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: !pass CELL.DOUBLE_IO_E0[1] ← CELL.DBUF_IO_V[0] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E0[1] IO[0]: PULL bit 1 INT: !pass CELL.DOUBLE_IO_E0[0] ← CELL.DBUF_IO_V[0] INT: mux CELL.DBUF_IO_V[1] bit 0 INT: mux CELL.LONG_H[4] bit 0 INT: mux CELL.LONG_H[4] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 0 IO[0]: !invert OK IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 7 IO[0]: ! READBACK_I2 bit 0 IO[0]: ! OFF_D_INV IO[0]: PULL bit 0 IO[0]: OFF_USED IO[0]: IFF_D bit 0
B7 INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E2[0] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E1[0] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E1[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E0[1] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E1[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E1[1] INT: !pass CELL.SINGLE_H[2] ← CELL.DEC_V[0] INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[0] INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 2 IO[0]: ! IFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 1 IO[0]: MUX_I2 bit 0 IO[0]: MUX_I2 bit 2
B6 INT: !pass CELL.SINGLE_H_E[0] ← CELL.LONG_V[0] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !pass CELL.SINGLE_H[3] ← CELL.LONG_V[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E0[0] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E0[0] INT: !bipass CELL.DOUBLE_IO_E0[0] = CELL.DOUBLE_IO_E2[0] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E0[0] INT: !bipass CELL.DOUBLE_IO_E0[1] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E1[1] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E0[1] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2[0] INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 5 DEC[1]: O2_N INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 7 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I1 bit 2
B5 INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[1] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[1] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H[2] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_V[2] INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_WE_I2[1] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_WE_I2[1] INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[1] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_WE_I2[1] INT: mux CELL.LONG_IO_V[0] bit 1 INT: mux CELL.LONG_IO_V[0] bit 0 INT: mux CELL.LONG_IO_V[0] bit 2 INT: mux CELL.LONG_IO_V[0] bit 3 INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.DOUBLE_IO_E2[0] ← CELL.DBUF_IO_V[1] INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[1] INT: !pass CELL.SINGLE_H[3] ← CELL.LONG_IO_V[1] INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[1] INT: !pass CELL.SINGLE_H[1] ← CELL.DEC_V[1] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1_S1 DEC[1]: ! O2_P DEC[2]: O2_P IO[1]: !invert IK DEC[2]: ! O1_N DEC[1]: ! O1_P IO[0]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I2 bit 0
B4 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_WE_I2[0] - INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_G1 bit 6 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_WE_I2[0] - INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E1[0] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E2[0] INT: mux CELL.LONG_IO_V[0] bit 4 INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[0] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[0] ← CELL.LONG_IO_V[0] INT: !pass CELL.DOUBLE_IO_E2[1] ← CELL.DBUF_IO_V[1] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1[0] DEC[0]: ! O2_P DEC[2]: ! O2_N DEC[0]: ! O1_P DEC[2]: O1_P DEC[1]: O1_N IO[1]: MUX_I1 bit 1 IO[1]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 2
B3 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 1 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 4 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 3 TBUF[0]: ! DRIVE1 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.DBUF_IO_V[0] bit 1 INT: mux CELL.DBUF_IO_V[0] bit 0 - INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 5 TBUF[1]: ! DRIVE1 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 1 DEC[0]: O2_N INT: mux CELL.IMUX_IO_IK[1] bit 5 DEC[0]: O1_N INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 7 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I2 bit 0 IO[1]: MUX_I2 bit 2
B2 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_G1 bit 3 INT: mux CELL.IMUX_CLB_F1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 6 - INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 5 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 7 IO[1]: ! IFF_SRVAL bit 0 IO[1]: IFF_D bit 0 IO[1]: OFF_USED
B1 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 1 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 6 - INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_IO_O1[1] bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 1 IO[1]: PULL bit 1 IO[1]: ! READBACK_OQ bit 0 IO[1]: MUX_OFF_D bit 0 IO[1]: ! OFF_SRVAL bit 0 IO[1]: ! OFF_D_INV IO[1]: MUX_O bit 2
B0 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_G3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.LONG_H[0] bit 0 INT: mux CELL.LONG_H[0] bit 3 INT: mux CELL.LONG_H[0] bit 1 INT: mux CELL.LONG_H[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 2 IO[1]: SLEW bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 4 IO[1]: MUX_O bit 0 IO[1]: MUX_O bit 1 IO[1]: !invert T IO[1]: !invert OK IO[1]: SLEW bit 1 IO[1]: PULL bit 0
xc4000a IO_E1 rect MAIN_S
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_H[0] INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[0] - - - - - - - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[2] PULLUP_TBUF[0]: ! ENABLE - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000a IO_E1 rect MAIN_W
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_E1_S

Cells: 3

Switchbox INT

xc4000a IO_E1_S switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[0]!MAIN_S[23][6]
CELL.LONG_H[2]CELL.SINGLE_V[1]!MAIN[22][5]
CELL.LONG_H[3]CELL.SINGLE_V[2]!MAIN[24][9]
CELL.LONG_H[4]CELL.SINGLE_V[3]!MAIN[26][9]
CELL.LONG_V[0]CELL.SINGLE_H_E[0]!MAIN[30][6]
CELL.LONG_V[1]CELL.SINGLE_H_E[1]!MAIN[28][5]
CELL.LONG_V[2]CELL.SINGLE_H[2]!MAIN[27][5]
CELL.LONG_V[3]CELL.SINGLE_H[3]!MAIN[27][7]
xc4000a IO_E1_S switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.LONG_IO_V[0]!MAIN[13][4]
CELL.SINGLE_H[0]CELL.DEC_V[0]!MAIN[12][7]
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I1[0]!MAIN[15][5]
CELL.SINGLE_H[0]CELL.OUT_IO_WE_I2_S1!MAIN[15][4]
CELL.SINGLE_H[1]CELL.LONG_IO_V[1]!MAIN[13][5]
CELL.SINGLE_H[1]CELL.DEC_V[1]!MAIN[10][5]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I2[0]!MAIN[10][4]
CELL.SINGLE_H[1]CELL.OUT_IO_WE_I1_S1!MAIN[9][5]
CELL.SINGLE_H[2]CELL.LONG_V[2]!MAIN[25][5]
CELL.SINGLE_H[2]CELL.LONG_IO_V[0]!MAIN[17][4]
CELL.SINGLE_H[2]CELL.DEC_V[0]!MAIN[13][7]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I1[0]!MAIN[14][4]
CELL.SINGLE_H[2]CELL.OUT_IO_WE_I2_S1!MAIN[16][4]
CELL.SINGLE_H[3]CELL.LONG_V[3]!MAIN[27][6]
CELL.SINGLE_H[3]CELL.LONG_IO_V[1]!MAIN[12][5]
CELL.SINGLE_H[3]CELL.DEC_V[1]!MAIN[11][5]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I2[0]!MAIN[11][4]
CELL.SINGLE_H[3]CELL.OUT_IO_WE_I1_S1!MAIN[9][4]
CELL.SINGLE_H_E[0]CELL.LONG_V[0]!MAIN[31][6]
CELL.SINGLE_H_E[1]CELL.LONG_V[1]!MAIN[30][5]
CELL.SINGLE_V[0]CELL.LONG_H[0]!MAIN_S[25][9]
CELL.SINGLE_V[0]CELL.OUT_CLB_Y_E!MAIN[31][5]
CELL.SINGLE_V[0]CELL.OUT_IO_WE_I2[0]!MAIN[30][4]
CELL.SINGLE_V[1]CELL.LONG_H[2]!MAIN_S[24][8]
CELL.SINGLE_V[1]CELL.OUT_CLB_YQ_E!MAIN[27][4]
CELL.SINGLE_V[1]CELL.OUT_IO_WE_I2[1]!MAIN[24][5]
CELL.SINGLE_V[2]CELL.LONG_H[3]!MAIN[31][9]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[29][5]
CELL.SINGLE_V[2]CELL.OUT_IO_WE_I2[0]!MAIN[29][4]
CELL.SINGLE_V[3]CELL.LONG_H[4]!MAIN[25][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[25][4]
CELL.SINGLE_V[3]CELL.OUT_IO_WE_I2[1]!MAIN[23][5]
CELL.DOUBLE_H0[0]CELL.OUT_IO_WE_I1[0]!MAIN[8][4]
CELL.DOUBLE_H0[1]CELL.OUT_IO_WE_I2_S1!MAIN[16][5]
CELL.DOUBLE_H1[0]CELL.OUT_IO_WE_I1_S1!MAIN[8][5]
CELL.DOUBLE_H1[1]CELL.OUT_IO_WE_I2[0]!MAIN[11][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[26][4]
CELL.DOUBLE_V0[1]CELL.OUT_IO_WE_I2[1]!MAIN[21][5]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[26][5]
CELL.DOUBLE_V1[1]CELL.OUT_IO_WE_I2[0]!MAIN[23][4]
CELL.DOUBLE_IO_E0[0]CELL.DBUF_IO_V[0]!MAIN[14][8]
CELL.DOUBLE_IO_E0[1]CELL.DBUF_IO_V[0]!MAIN[17][8]
CELL.DOUBLE_IO_E2[0]CELL.DBUF_IO_V[1]!MAIN[14][5]
CELL.DOUBLE_IO_E2[1]CELL.DBUF_IO_V[1]!MAIN[12][4]
xc4000a IO_E1_S switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[28][7]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[29][6]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[28][6]
CELL.SINGLE_H[0]CELL.DOUBLE_IO_E1[0]!MAIN[18][7]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[19][8]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[21][4]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[18][8]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_E0[0]!MAIN[17][6]
CELL.SINGLE_H[1]CELL.DOUBLE_IO_E2[0]!MAIN[20][7]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[28][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[29][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[27][9]
CELL.SINGLE_H[2]CELL.DOUBLE_IO_E1[1]!MAIN[15][7]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[24][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[22][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[23][7]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_E0[1]!MAIN[16][8]
CELL.SINGLE_H[3]CELL.DOUBLE_IO_E2[1]!MAIN[16][7]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[29][7]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[31][7]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[22][9]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[21][8]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[28][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[31][8]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[26][6]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[26][7]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[30][7]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[23][9]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[30][8]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[25][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[25][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[27][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[24][8]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E0[1]!MAIN[17][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E1[1]!MAIN[14][7]
CELL.DOUBLE_H0[0]CELL.DOUBLE_IO_E2[1]!MAIN[15][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[23][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[21][7]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[21][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E0[0]!MAIN[20][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E1[0]!MAIN[20][4]
CELL.DOUBLE_H0[1]CELL.DOUBLE_IO_E2[0]!MAIN[19][4]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E0[0]!MAIN[19][6]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E1[0]!MAIN[19][7]
CELL.DOUBLE_H1[0]CELL.DOUBLE_IO_E2[0]!MAIN[20][8]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E0[1]!MAIN[12][6]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E1[1]!MAIN[13][6]
CELL.DOUBLE_H1[1]CELL.DOUBLE_IO_E2[1]!MAIN[14][6]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[26][8]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[23][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[24][6]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[25][6]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[22][6]
CELL.DOUBLE_IO_E0[0]CELL.DOUBLE_IO_E2[0]!MAIN[18][6]
CELL.DOUBLE_IO_E0[1]CELL.DOUBLE_IO_E2[1]!MAIN[16][6]
xc4000a IO_E1_S switchbox INT muxes DBUF_IO_V[0]
BitsDestination
MAIN[17][3]MAIN[16][3]CELL.DBUF_IO_V[0]
Source
00CELL.DOUBLE_IO_E2[0]
11CELL.DOUBLE_IO_E2[1]
xc4000a IO_E1_S switchbox INT muxes DBUF_IO_V[1]
BitsDestination
MAIN[14][9]MAIN[13][8]CELL.DBUF_IO_V[1]
Source
00CELL.DOUBLE_IO_E0[1]
11CELL.DOUBLE_IO_E0[0]
xc4000a IO_E1_S switchbox INT muxes LONG_H[0]
BitsDestination
MAIN[19][0]MAIN[17][0]MAIN[18][0]MAIN[20][0]CELL.LONG_H[0]
Source
0001CELL.LONG_IO_V[0]
0010CELL.DEC_V[1]
0111CELL.OUT_IO_WE_I2[1]
1111off
xc4000a IO_E1_S switchbox INT muxes LONG_H[4]
BitsDestination
MAIN[7][9]MAIN[11][8]MAIN[11][9]MAIN[12][8]CELL.LONG_H[4]
Source
0001CELL.LONG_IO_V[1]
0010CELL.DEC_V[0]
0111CELL.OUT_IO_WE_I2[0]
1111off
xc4000a IO_E1_S switchbox INT muxes LONG_IO_V[0]
BitsDestination
MAIN[18][4]MAIN[17][5]MAIN[18][5]MAIN[20][5]MAIN[19][5]CELL.LONG_IO_V[0]
Source
00011CELL.SINGLE_H[0]
00101CELL.LONG_H[0]
00110CELL.LONG_H[3]
01111CELL.SINGLE_H[2]
11111off
xc4000a IO_E1_S switchbox INT muxes LONG_IO_V[1]
BitsDestination
MAIN[16][9]MAIN[15][9]MAIN[17][9]MAIN[19][9]MAIN[18][9]CELL.LONG_IO_V[1]
Source
00011CELL.SINGLE_H[1]
00101CELL.LONG_H[2]
00110CELL.LONG_H[4]
01111CELL.SINGLE_H[3]
11111off
xc4000a IO_E1_S switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[23][1]MAIN[24][1]MAIN[24][3]MAIN[21][0]MAIN[22][0]MAIN[23][0]MAIN[24][2]CELL.IMUX_CLB_F1
Source
0010011CELL.LONG_V[0]
0010101CELL.LONG_V[2]
0011111CELL.SINGLE_V[1]
0100011CELL.SINGLE_V[3]
0100101CELL.LONG_V[3]
0101111CELL.SINGLE_V[2]
0110010CELL.LONG_V[1]
0110100CELL.DOUBLE_V1[1]
0111110CELL.DOUBLE_V1[0]
1110011CELL.DOUBLE_V0[0]
1110101CELL.DOUBLE_V0[1]
1111111CELL.SINGLE_V[0]
xc4000a IO_E1_S switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[31][1]MAIN[31][0]MAIN[31][2]MAIN[30][1]MAIN[31][3]MAIN[30][3]MAIN[30][0]MAIN[31][4]CELL.IMUX_CLB_F3
Source
00100111CELL.SINGLE_V[2]
00101011CELL.LONG_V[1]
00101101CELL.LONG_V[0]
00111111CELL.SINGLE_V[0]
01000111CELL.DOUBLE_V1[0]
01001011CELL.LONG_V[3]
01001101CELL.LONG_V[2]
01011111CELL.SINGLE_V[1]
01101110CELL.GCLK[0]
11100111CELL.DOUBLE_V1[1]
11101011CELL.SINGLE_V[3]
11101101CELL.DOUBLE_V0[0]
11111111CELL.DOUBLE_V0[1]
xc4000a IO_E1_S switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[24][4]MAIN[24][0]MAIN[25][1]MAIN[25][2]MAIN[26][3]MAIN[25][3]MAIN[26][2]CELL.IMUX_CLB_G1
Source
0010011CELL.LONG_V[0]
0010101CELL.DOUBLE_V0[1]
0011111CELL.SINGLE_V[0]
0100011CELL.DOUBLE_V0[0]
0100101CELL.LONG_V[2]
0101111CELL.SINGLE_V[1]
0110010CELL.LONG_V[1]
0110100CELL.LONG_V[3]
0111110CELL.DOUBLE_V1[0]
1110011CELL.SINGLE_V[3]
1110101CELL.DOUBLE_V1[1]
1111111CELL.SINGLE_V[2]
xc4000a IO_E1_S switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[28][2]MAIN[29][2]MAIN[28][3]MAIN[30][2]MAIN[29][0]MAIN[29][1]MAIN[29][3]MAIN[28][1]CELL.IMUX_CLB_G3
Source
00001111CELL.SPECIAL_CLB_CIN
00011101CELL.LONG_V[3]
00111111CELL.SINGLE_V[2]
01000111CELL.DOUBLE_V0[0]
01001011CELL.LONG_V[0]
01001110CELL.LONG_V[1]
01010101CELL.DOUBLE_V0[1]
01011001CELL.LONG_V[2]
01011100CELL.GCLK[0]
01110111CELL.SINGLE_V[0]
01111011CELL.SINGLE_V[1]
11001111CELL.SINGLE_V[3]
11011101CELL.DOUBLE_V1[1]
11111111CELL.DOUBLE_V1[0]
xc4000a IO_E1_S switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[21][2]MAIN[22][2]MAIN[21][1]MAIN[21][3]MAIN[22][3]MAIN[23][2]MAIN[23][3]CELL.IMUX_CLB_C1
Source
0010011CELL.DOUBLE_V0[1]
0010110CELL.LONG_V[0]
0011111CELL.SINGLE_V[0]
0100011CELL.LONG_V[2]
0100110CELL.DOUBLE_V0[0]
0101111CELL.SINGLE_V[1]
0110001CELL.LONG_V[3]
0110100CELL.LONG_V[1]
0111101CELL.SINGLE_V[3]
1110011CELL.SINGLE_V[2]
1110110CELL.DOUBLE_V1[0]
1111111CELL.DOUBLE_V1[1]
xc4000a IO_E1_S switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[26][1]MAIN[28][0]MAIN[25][0]MAIN[27][2]MAIN[27][3]MAIN[26][0]MAIN[27][1]MAIN[27][0]CELL.IMUX_CLB_C3
Source
00001111CELL.LONG_V[1]
00010111CELL.SINGLE_V[3]
00011011CELL.LONG_V[0]
00111111CELL.SINGLE_V[0]
01001101CELL.LONG_V[3]
01010101CELL.DOUBLE_V1[1]
01011001CELL.LONG_V[2]
01011110CELL.GCLK[2]
01111101CELL.DOUBLE_V0[1]
11001111CELL.SINGLE_V[2]
11010111CELL.DOUBLE_V1[0]
11011011CELL.DOUBLE_V0[0]
11111111CELL.SINGLE_V[1]
xc4000a IO_E1_S switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[20][1]MAIN[16][1]MAIN[17][1]MAIN[19][1]MAIN[18][1]CELL.IMUX_TBUF_I[0]
Source
00011CELL.DOUBLE_IO_E2[1]
00101CELL.OUT_IO_WE_I2[1]
00110CELL.DEC_V[0]
01111CELL.DOUBLE_IO_E1[1]
10011CELL.LONG_IO_V[1]
10101CELL.LONG_IO_V[0]
10110CELL.OUT_IO_WE_I2[0]
11111CELL.TIE_0
xc4000a IO_E1_S switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[9][1]MAIN[9][0]MAIN[10][1]MAIN[10][0]MAIN[11][1]CELL.IMUX_TBUF_I[1]
Source
00011CELL.DOUBLE_IO_E1[1]
00101CELL.LONG_IO_V[0]
00110CELL.LONG_IO_V[1]
01111CELL.DOUBLE_IO_E2[1]
10011CELL.OUT_IO_WE_I2[0]
10101CELL.DEC_V[1]
10110CELL.OUT_IO_WE_I2[1]
11111CELL.TIE_0
xc4000a IO_E1_S switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[15][0]MAIN[14][1]MAIN[15][1]MAIN[16][0]MAIN[14][0]CELL.IMUX_TBUF_T[0]
Source
00101CELL.DOUBLE_IO_E2[0]
00110CELL.DEC_V[0]
01111CELL.TIE_1
10011CELL.DOUBLE_IO_E1[0]
10101CELL.LONG_IO_V[1]
10110CELL.LONG_IO_V[0]
11111CELL.TIE_0
xc4000a IO_E1_S switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[12][1]MAIN[11][0]MAIN[13][1]MAIN[12][0]MAIN[13][0]CELL.IMUX_TBUF_T[1]
Source
00101CELL.DOUBLE_IO_E2[0]
00110CELL.DEC_V[0]
01111CELL.TIE_1
10011CELL.DOUBLE_IO_E1[0]
10101CELL.LONG_IO_V[1]
10110CELL.LONG_IO_V[0]
11111CELL.TIE_0
xc4000a IO_E1_S switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[8][9]MAIN[9][9]MAIN[12][9]MAIN[13][9]MAIN[10][8]CELL.IMUX_IO_O1[0]
Source
00011CELL.DOUBLE_H1[0]
00101CELL.LONG_H[4]
01111CELL.DOUBLE_H0[1]
10011CELL.LONG_H[3]
10101CELL.DEC_V[1]
10110CELL.DEC_V[0]
11111CELL.TIE_0
xc4000a IO_E1_S switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[6][0]MAIN[7][1]MAIN[8][0]MAIN[6][1]MAIN[8][1]CELL.IMUX_IO_O1[1]
Source
00101CELL.DEC_V[0]
00111CELL.LONG_H[0]
01001CELL.DEC_V[1]
01011CELL.LONG_H[2]
01110CELL_S.DOUBLE_H1[1]
11101CELL_S.DOUBLE_H0[0]
11111CELL.TIE_0
xc4000a IO_E1_S switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[5][8]MAIN[8][7]MAIN[11][7]MAIN[9][7]MAIN[6][7]MAIN[5][7]MAIN[7][7]MAIN[6][8]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_H[0]
01011111CELL.SINGLE_H[1]
01101111CELL.SINGLE_H[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[2]
xc4000a IO_E1_S switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[3][2]MAIN[11][2]MAIN[5][2]MAIN[10][2]MAIN[7][2]MAIN[4][2]MAIN[12][2]MAIN[6][2]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[1]
01111101CELL_S.SINGLE_H[2]
01111110CELL_S.SINGLE_H[3]
11111111CELL_S.SINGLE_H[0]
xc4000a IO_E1_S switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[3][6]MAIN[10][7]MAIN[8][6]MAIN[6][6]MAIN[9][6]MAIN[10][6]MAIN[5][6]MAIN[4][6]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_H[0]
01011111CELL.SINGLE_H[1]
01101111CELL.SINGLE_H[2]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_H[3]
xc4000a IO_E1_S switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[3][3]MAIN[9][2]MAIN[6][3]MAIN[9][3]MAIN[8][2]MAIN[4][3]MAIN[8][3]MAIN[10][3]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_S.SINGLE_H[0]
01111101CELL_S.SINGLE_H[2]
01111110CELL_S.SINGLE_H[3]
11111111CELL_S.SINGLE_H[1]
xc4000a IO_E1_S switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[16][2]MAIN[17][2]MAIN[19][3]MAIN[15][2]MAIN[18][3]MAIN[19][2]CELL.IMUX_IO_T[0]
Source
001111CELL.TIE_0
010011CELL.GCLK[0]
010111CELL.DOUBLE_IO_E1[0]
011001CELL.DOUBLE_IO_E1[1]
011010CELL.DEC_V[1]
011101CELL.LONG_IO_V[1]
011110CELL.LONG_IO_V[0]
111011CELL.DOUBLE_IO_E2[1]
111111CELL.DOUBLE_IO_E2[0]
xc4000a IO_E1_S switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[12][3]MAIN[18][2]MAIN[13][2]MAIN[13][3]MAIN[14][3]MAIN[14][2]CELL.IMUX_IO_T[1]
Source
001111CELL.TIE_0
010011CELL.GCLK[0]
010101CELL.DOUBLE_IO_E2[1]
010110CELL.DEC_V[1]
011011CELL.DOUBLE_IO_E2[0]
011101CELL.LONG_IO_V[1]
011110CELL.LONG_IO_V[0]
110111CELL.DOUBLE_IO_E1[1]
111111CELL.DOUBLE_IO_E1[0]

Bels TBUF

xc4000a IO_E1_S bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000a IO_E1_S bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[20][3]!MAIN[11][3]

Bels IO

xc4000a IO_E1_S bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[3][7]CELL.IMUX_IO_IK[1] invert by !MAIN[5][5]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[9][8]CELL.IMUX_IO_OK[1] invert by !MAIN[2][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_G1CELL.IMUX_CLB_F1
TinCELL.IMUX_IO_T[0] invert by !MAIN[0][9]CELL.IMUX_IO_T[1] invert by !MAIN[3][0]
I1outCELL.OUT_IO_WE_I1[0]CELL.OUT_IO_WE_I1[1]
I2outCELL.OUT_IO_WE_I2[0]CELL.OUT_IO_WE_I2[1]
CLKINoutCELL.OUT_IO_CLKIN-
xc4000a IO_E1_S bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[4][7]!MAIN[2][2]
OFF_SRVAL bit 0!MAIN[7][8]!MAIN[2][1]
READBACK_I1 bit 0!MAIN[2][5]!MAIN[1][5]
READBACK_I2 bit 0!MAIN[4][8]!MAIN[0][5]
READBACK_OQ bit 0!MAIN[2][9]!MAIN[4][1]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[3][8]!MAIN[1][1]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[1][8]MAIN[0][2]
xc4000a IO_E1_S enum IO_SLEW
IO[0].SLEWMAIN[3][9]MAIN[6][9]
IO[1].SLEWMAIN[1][0]MAIN[7][0]
FAST00
MEDFAST01
MEDSLOW10
SLOW11
xc4000a IO_E1_S enum IO_PULL
IO[0].PULLMAIN[15][8]MAIN[2][8]
IO[1].PULLMAIN[5][1]MAIN[0][0]
NONE11
PULLUP01
PULLDOWN10
xc4000a IO_E1_S enum IO_MUX_I
IO[0].MUX_I1MAIN[0][6]MAIN[2][6]MAIN[1][6]
IO[1].MUX_I1MAIN[0][4]MAIN[2][4]MAIN[1][4]
IO[0].MUX_I2MAIN[0][7]MAIN[2][7]MAIN[1][7]
IO[1].MUX_I2MAIN[0][3]MAIN[2][3]MAIN[1][3]
I001
IQ111
IQL010
xc4000a IO_E1_S enum IO_IFF_D
IO[0].IFF_DMAIN[0][8]
IO[1].IFF_DMAIN[1][2]
I1
DELAY0
xc4000a IO_E1_S enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[8][8]
IO[1].MUX_OFF_DMAIN[3][1]
O11
O20
xc4000a IO_E1_S enum IO_MUX_O
IO[0].MUX_OMAIN[1][9]MAIN[4][9]MAIN[5][9]
IO[1].MUX_OMAIN[0][1]MAIN[4][0]MAIN[5][0]
O1001
O1_INV010
O2100
O2_INV011
OQ000

Bels DEC

xc4000a IO_E1_S bel DEC pins
PinDirectionDEC[0]DEC[1]DEC[2]
IinCELL.OUT_IO_WE_I1[0]CELL.IMUX_CLB_C1CELL.OUT_IO_WE_I1[1]
O1bidirCELL.DEC_V[0]CELL.DEC_V[0]CELL.DEC_V[0]
O2bidirCELL.DEC_V[1]CELL.DEC_V[1]CELL.DEC_V[1]
xc4000a IO_E1_S bel DEC attribute bits
AttributeDEC[0]DEC[1]DEC[2]
O1_P!MAIN[5][4]!MAIN[3][5]MAIN[4][4]
O1_NMAIN[5][3]MAIN[3][4]!MAIN[4][5]
O2_P!MAIN[7][4]!MAIN[7][5]MAIN[6][5]
O2_NMAIN[7][3]MAIN[7][6]!MAIN[6][4]

Bels PULLUP

xc4000a IO_E1_S bel PULLUP pins
PinDirectionPULLUP_TBUF[0]PULLUP_TBUF[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000a IO_E1_S bel PULLUP attribute bits
AttributePULLUP_TBUF[0]PULLUP_TBUF[1]
ENABLE!MAIN_S[31][7]!MAIN[10][9]

Bel wires

xc4000a IO_E1_S bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]TBUF[1].O, PULLUP_TBUF[1].O
CELL.DEC_V[0]DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_V[1]DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.IMUX_CLB_F1IO[1].O2
CELL.IMUX_CLB_G1IO[0].O2
CELL.IMUX_CLB_C1DEC[1].I
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_WE_I1[0]IO[0].I1, DEC[0].I
CELL.OUT_IO_WE_I1[1]IO[1].I1, DEC[2].I
CELL.OUT_IO_WE_I2[0]IO[0].I2
CELL.OUT_IO_WE_I2[1]IO[1].I2
CELL.OUT_IO_CLKINIO[0].CLKIN

Bitstream

xc4000a IO_E1_S rect MAIN
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[3] - - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[3] INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[4] INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] - - INT: mux CELL.LONG_IO_V[1] bit 1 INT: mux CELL.LONG_IO_V[1] bit 0 INT: mux CELL.LONG_IO_V[1] bit 2 INT: mux CELL.LONG_IO_V[1] bit 4 INT: mux CELL.LONG_IO_V[1] bit 3 INT: mux CELL.DBUF_IO_V[1] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: mux CELL.LONG_H[4] bit 1 PULLUP_TBUF[1]: ! ENABLE INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.LONG_H[4] bit 3 IO[0]: SLEW bit 0 IO[0]: MUX_O bit 0 IO[0]: MUX_O bit 1 IO[0]: SLEW bit 1 IO[0]: ! READBACK_OQ bit 0 IO[0]: MUX_O bit 2 IO[0]: !invert T
B8 INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E2[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: !pass CELL.DOUBLE_IO_E0[1] ← CELL.DBUF_IO_V[0] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E0[1] IO[0]: PULL bit 1 INT: !pass CELL.DOUBLE_IO_E0[0] ← CELL.DBUF_IO_V[0] INT: mux CELL.DBUF_IO_V[1] bit 0 INT: mux CELL.LONG_H[4] bit 0 INT: mux CELL.LONG_H[4] bit 2 INT: mux CELL.IMUX_IO_O1[0] bit 0 IO[0]: !invert OK IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 7 IO[0]: ! READBACK_I2 bit 0 IO[0]: ! OFF_D_INV IO[0]: PULL bit 0 IO[0]: OFF_USED IO[0]: IFF_D bit 0
B7 INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E2[0] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E1[0] INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E1[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E0[1] INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E1[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E1[1] INT: !pass CELL.SINGLE_H[2] ← CELL.DEC_V[0] INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[0] INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 2 IO[0]: ! IFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 1 IO[0]: MUX_I2 bit 0 IO[0]: MUX_I2 bit 2
B6 INT: !pass CELL.SINGLE_H_E[0] ← CELL.LONG_V[0] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !pass CELL.SINGLE_H[3] ← CELL.LONG_V[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E0[0] INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E0[0] INT: !bipass CELL.DOUBLE_IO_E0[0] = CELL.DOUBLE_IO_E2[0] INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E0[0] INT: !bipass CELL.DOUBLE_IO_E0[1] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E2[1] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E1[1] INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E0[1] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2[0] INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 5 DEC[1]: O2_N INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 1 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 7 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I1 bit 2
B5 INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[1] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[1] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H[2] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_V[2] INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_WE_I2[1] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_WE_I2[1] INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[1] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_WE_I2[1] INT: mux CELL.LONG_IO_V[0] bit 1 INT: mux CELL.LONG_IO_V[0] bit 0 INT: mux CELL.LONG_IO_V[0] bit 2 INT: mux CELL.LONG_IO_V[0] bit 3 INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.DOUBLE_IO_E2[0] ← CELL.DBUF_IO_V[1] INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[1] INT: !pass CELL.SINGLE_H[3] ← CELL.LONG_IO_V[1] INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[1] INT: !pass CELL.SINGLE_H[1] ← CELL.DEC_V[1] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1_S1 DEC[1]: ! O2_P DEC[2]: O2_P IO[1]: !invert IK DEC[2]: ! O1_N DEC[1]: ! O1_P IO[0]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I1 bit 0 IO[1]: ! READBACK_I2 bit 0
B4 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_WE_I2[0] - INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_G1 bit 6 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_WE_I2[0] - INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E1[0] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E2[0] INT: mux CELL.LONG_IO_V[0] bit 4 INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[0] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1 INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0] INT: !pass CELL.SINGLE_H[0] ← CELL.LONG_IO_V[0] INT: !pass CELL.DOUBLE_IO_E2[1] ← CELL.DBUF_IO_V[1] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1 INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1[0] DEC[0]: ! O2_P DEC[2]: ! O2_N DEC[0]: ! O1_P DEC[2]: O1_P DEC[1]: O1_N IO[1]: MUX_I1 bit 1 IO[1]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 2
B3 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 1 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 4 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 3 TBUF[0]: ! DRIVE1 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.DBUF_IO_V[0] bit 1 INT: mux CELL.DBUF_IO_V[0] bit 0 - INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 5 TBUF[1]: ! DRIVE1 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 1 DEC[0]: O2_N INT: mux CELL.IMUX_IO_IK[1] bit 5 DEC[0]: O1_N INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 7 IO[1]: MUX_I2 bit 1 IO[1]: MUX_I2 bit 0 IO[1]: MUX_I2 bit 2
B2 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_G1 bit 3 INT: mux CELL.IMUX_CLB_F1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 6 - INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[0] bit 5 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_OK[1] bit 0 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 2 INT: mux CELL.IMUX_IO_OK[1] bit 7 IO[1]: ! IFF_SRVAL bit 0 IO[1]: IFF_D bit 0 IO[1]: OFF_USED
B1 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 1 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 6 - INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_IO_O1[1] bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 1 IO[1]: PULL bit 1 IO[1]: ! READBACK_OQ bit 0 IO[1]: MUX_OFF_D bit 0 IO[1]: ! OFF_SRVAL bit 0 IO[1]: ! OFF_D_INV IO[1]: MUX_O bit 2
B0 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_G3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.LONG_H[0] bit 0 INT: mux CELL.LONG_H[0] bit 3 INT: mux CELL.LONG_H[0] bit 1 INT: mux CELL.LONG_H[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 2 IO[1]: SLEW bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 4 IO[1]: MUX_O bit 0 IO[1]: MUX_O bit 1 IO[1]: !invert T IO[1]: !invert OK IO[1]: SLEW bit 1 IO[1]: PULL bit 0
xc4000a IO_E1_S rect MAIN_S
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_H[0] - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - - - - -
B7 PULLUP_TBUF[0]: ! ENABLE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[0] - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000a IO_E1_S rect MAIN_W
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_S0

Cells: 4

Switchbox INT

xc4000a IO_S0 switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[3]CELL.SINGLE_V[2]!MAIN[18][5]
CELL.LONG_H[4]CELL.SINGLE_V[3]!MAIN[21][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[0]!MAIN[29][6]
CELL.LONG_V[1]CELL.SINGLE_H_E[1]!MAIN[14][7]
CELL.LONG_V[2]CELL.SINGLE_H[2]!MAIN[12][7]
CELL.LONG_V[3]CELL.SINGLE_H[3]!MAIN[13][7]
xc4000a IO_S0 switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[12][9]
CELL.SINGLE_H[0]CELL.OUT_CLB_X_S!MAIN[11][6]
CELL.SINGLE_H[0]CELL.OUT_IO_SN_I2[1]!MAIN[16][6]
CELL.SINGLE_H[1]CELL.OUT_CLB_XQ_S!MAIN[9][6]
CELL.SINGLE_H[1]CELL.OUT_IO_SN_I2[0]!MAIN[14][6]
CELL.SINGLE_H[2]CELL.LONG_V[2]!MAIN[25][7]
CELL.SINGLE_H[2]CELL.OUT_CLB_X_S!MAIN[13][6]
CELL.SINGLE_H[2]CELL.OUT_IO_SN_I2[1]!MAIN[20][6]
CELL.SINGLE_H[3]CELL.LONG_V[3]!MAIN[17][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_XQ_S!MAIN[10][6]
CELL.SINGLE_H[3]CELL.OUT_IO_SN_I2[0]!MAIN[15][6]
CELL.SINGLE_H_E[0]CELL.LONG_V[0]!MAIN[30][6]
CELL.SINGLE_H_E[1]CELL.LONG_V[1]!MAIN[29][7]
CELL.SINGLE_V[0]CELL.LONG_IO_H[0]!MAIN[31][5]
CELL.SINGLE_V[0]CELL.DEC_H[1]!MAIN[28][5]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I1[0]!MAIN[30][5]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I2_E1!MAIN[29][5]
CELL.SINGLE_V[1]CELL.LONG_IO_H[1]!MAIN[25][4]
CELL.SINGLE_V[1]CELL.DEC_H[0]!MAIN[22][4]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I2[0]!MAIN[23][4]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I1_E1!MAIN[24][4]
CELL.SINGLE_V[2]CELL.TIE_0!MAIN[13][9]
CELL.SINGLE_V[2]CELL.LONG_H[3]!MAIN[30][7]
CELL.SINGLE_V[2]CELL.LONG_IO_H[0]!MAIN[31][4]
CELL.SINGLE_V[2]CELL.DEC_H[1]!MAIN[27][4]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I1[0]!MAIN[30][4]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I2_E1!MAIN[29][4]
CELL.SINGLE_V[3]CELL.LONG_H[4]!MAIN[24][7]
CELL.SINGLE_V[3]CELL.LONG_IO_H[1]!MAIN[20][4]
CELL.SINGLE_V[3]CELL.DEC_H[0]!MAIN[19][5]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I2[0]!MAIN[21][4]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I1_E1!MAIN[17][5]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[8][6]
CELL.DOUBLE_H0[1]CELL.OUT_IO_SN_I2[0]!MAIN[18][6]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[12][6]
CELL.DOUBLE_H1[1]CELL.OUT_IO_SN_I2[1]!MAIN[19][6]
CELL.DOUBLE_V0[0]CELL.OUT_IO_SN_I1_E1!MAIN[28][4]
CELL.DOUBLE_V0[1]CELL.OUT_IO_SN_I2[0]!MAIN[19][4]
CELL.DOUBLE_V1[0]CELL.OUT_IO_SN_I1[0]!MAIN[26][4]
CELL.DOUBLE_V1[1]CELL.OUT_IO_SN_I2_E1!MAIN[16][5]
CELL.DOUBLE_IO_S0[0]CELL.DBUF_IO_H[1]!MAIN[18][4]
CELL.DOUBLE_IO_S0[1]CELL.DBUF_IO_H[1]!MAIN[16][4]
CELL.DOUBLE_IO_S2[0]CELL.DBUF_IO_H[0]!MAIN[10][4]
CELL.DOUBLE_IO_S2[1]CELL.DBUF_IO_H[0]!MAIN[11][4]
xc4000a IO_S0 switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[28][9]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[27][9]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[26][9]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[17][8]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[17][9]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[16][9]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[26][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[25][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[25][6]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[26][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[26][6]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[30][9]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[29][9]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[19][8]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[18][8]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[29][8]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[28][8]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[28][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[24][6]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[31][9]
CELL.SINGLE_V[0]CELL.DOUBLE_IO_S0[0]!MAIN[26][3]
CELL.SINGLE_V[0]CELL.DOUBLE_IO_S2[0]!MAIN[28][3]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[20][8]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_S1[0]!MAIN[19][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[30][8]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_S0[1]!MAIN[11][3]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_S2[1]!MAIN[18][3]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[27][7]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_S1[1]!MAIN[2][4]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[20][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[21][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[19][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[19][7]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[20][7]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[18][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[23][9]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[24][9]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[22][7]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[23][7]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][9]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S0[1]!MAIN[12][3]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S1[1]!MAIN[5][4]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S2[1]!MAIN[15][3]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[21][7]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S0[0]!MAIN[24][3]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S1[0]!MAIN[21][3]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S2[0]!MAIN[27][3]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S0[0]!MAIN[25][3]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S1[0]!MAIN[22][3]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S2[0]!MAIN[29][3]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S0[1]!MAIN[7][4]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S1[1]!MAIN[6][4]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S2[1]!MAIN[17][3]
CELL.DOUBLE_IO_S0[0]CELL.DOUBLE_IO_S2[0]!MAIN[23][3]
CELL.DOUBLE_IO_S0[1]CELL.DOUBLE_IO_S2[1]!MAIN[14][3]
xc4000a IO_S0 switchbox INT muxes DBUF_IO_H[0]
BitsDestination
MAIN[14][4]MAIN[12][4]CELL.DBUF_IO_H[0]
Source
00CELL.DOUBLE_IO_S0[1]
11CELL.DOUBLE_IO_S0[0]
xc4000a IO_S0 switchbox INT muxes DBUF_IO_H[1]
BitsDestination
MAIN[9][4]MAIN[8][4]CELL.DBUF_IO_H[1]
Source
00CELL.DOUBLE_IO_S2[0]
11CELL.DOUBLE_IO_S2[1]
xc4000a IO_S0 switchbox INT muxes LONG_V[0]
BitsDestination
MAIN[27][5]MAIN[24][5]MAIN[25][5]MAIN[26][5]CELL.LONG_V[0]
Source
0001CELL.LONG_IO_H[0]
0010CELL.DEC_H[0]
0111CELL.OUT_IO_SN_I2_E1
1111off
xc4000a IO_S0 switchbox INT muxes LONG_V[1]
BitsDestination
MAIN[15][5]MAIN[12][5]MAIN[14][5]MAIN[17][4]CELL.LONG_V[1]
Source
0001CELL.LONG_IO_H[1]
0010CELL.DEC_H[1]
0111CELL.OUT_IO_SN_I2_E1
1111off
xc4000a IO_S0 switchbox INT muxes LONG_V[2]
BitsDestination
MAIN[11][5]MAIN[9][5]MAIN[13][5]MAIN[10][5]CELL.LONG_V[2]
Source
0001CELL.LONG_IO_H[0]
0010CELL.DEC_H[0]
0111CELL.OUT_IO_SN_I2[0]
1111off
xc4000a IO_S0 switchbox INT muxes LONG_V[3]
BitsDestination
MAIN[23][5]MAIN[20][5]MAIN[21][5]MAIN[22][5]CELL.LONG_V[3]
Source
0001CELL.LONG_IO_H[1]
0010CELL.DEC_H[1]
0111CELL.OUT_IO_SN_I2[0]
1111off
xc4000a IO_S0 switchbox INT muxes LONG_IO_H[0]
BitsDestination
MAIN[2][3]MAIN[3][3]MAIN[5][3]MAIN[4][3]MAIN[6][3]CELL.LONG_IO_H[0]
Source
00011CELL.SINGLE_V[2]
00101CELL.LONG_V[0]
00110CELL.LONG_V[2]
01111CELL.SINGLE_V[0]
11111off
xc4000a IO_S0 switchbox INT muxes LONG_IO_H[1]
BitsDestination
MAIN[1][4]MAIN[7][3]MAIN[8][3]MAIN[10][3]MAIN[9][3]CELL.LONG_IO_H[1]
Source
00011CELL.SINGLE_V[3]
00101CELL.LONG_V[1]
00110CELL.LONG_V[3]
01111CELL.SINGLE_V[1]
11111off
xc4000a IO_S0 switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[8][8]MAIN[10][7]MAIN[9][8]MAIN[10][8]MAIN[11][9]MAIN[11][8]MAIN[11][7]CELL.IMUX_CLB_F2
Source
0010011CELL.LONG_H[4]
0010101CELL.LONG_H[3]
0011111CELL.SINGLE_H[0]
0100011CELL_N.LONG_H[0]
0100101CELL_N.LONG_H[2]
0101111CELL.SINGLE_H[1]
0110010CELL.DOUBLE_H0[0]
0110100CELL.DOUBLE_H1[1]
0111110CELL.DOUBLE_H1[0]
1110011CELL.SINGLE_H[2]
1110101CELL.SINGLE_H[3]
1111111CELL.DOUBLE_H0[1]
xc4000a IO_S0 switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[6][8]MAIN[6][6]MAIN[5][9]MAIN[7][8]MAIN[5][8]MAIN[6][7]MAIN[8][9]CELL.IMUX_CLB_F4
Source
0000111CELL.LONG_H[4]
0001011CELL.LONG_H[3]
0011111CELL.SINGLE_H[0]
0100101CELL.DOUBLE_H0[0]
0100110CELL_N.LONG_H[0]
0101001CELL.DOUBLE_H1[1]
0101010CELL_N.LONG_H[2]
0111101CELL.DOUBLE_H1[0]
0111110CELL.DOUBLE_H0[1]
1100111CELL.SINGLE_H[2]
1101011CELL.SINGLE_H[3]
1111111CELL.SINGLE_H[1]
xc4000a IO_S0 switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[0][6]MAIN[2][7]MAIN[3][9]MAIN[2][6]MAIN[2][9]MAIN[3][8]MAIN[1][6]MAIN[3][6]CELL.IMUX_CLB_G2
Source
00011111CELL.SPECIAL_CLB_COUT0
00100111CELL.SINGLE_H[1]
00101011CELL_N.LONG_H[2]
00101110CELL.LONG_H[3]
00110101CELL.DOUBLE_H0[1]
00111001CELL_N.LONG_H[0]
00111100CELL.LONG_H[4]
01101111CELL.SINGLE_H[0]
01111101CELL.DOUBLE_H1[0]
10110111CELL.SINGLE_H[2]
10111011CELL.SINGLE_H[3]
10111110CELL.DOUBLE_H1[1]
11111111CELL.DOUBLE_H0[0]
xc4000a IO_S0 switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[4][7]MAIN[5][6]MAIN[3][7]MAIN[4][8]MAIN[4][9]MAIN[4][6]MAIN[5][7]CELL.IMUX_CLB_G4
Source
0000111CELL.SINGLE_H[1]
0001011CELL_N.LONG_H[2]
0001101CELL.LONG_H[3]
0011111CELL.SINGLE_H[0]
0100110CELL.DOUBLE_H0[1]
0101010CELL_N.LONG_H[0]
0101100CELL.LONG_H[4]
0111110CELL.DOUBLE_H1[0]
1100111CELL.SINGLE_H[2]
1101011CELL.SINGLE_H[3]
1101101CELL.DOUBLE_H0[0]
1111111CELL.DOUBLE_H1[1]
xc4000a IO_S0 switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[0][8]MAIN[2][8]MAIN[0][9]MAIN[0][7]MAIN[1][9]MAIN[1][8]MAIN[1][7]CELL.IMUX_CLB_C2
Source
0000111CELL.SINGLE_H[0]
0001011CELL_N.LONG_H[2]
0001110CELL.LONG_H[3]
0011111CELL.SINGLE_H[1]
0100101CELL.DOUBLE_H1[0]
0101001CELL_N.LONG_H[0]
0101100CELL.LONG_H[4]
0111101CELL.DOUBLE_H0[1]
1100111CELL.DOUBLE_H0[0]
1101011CELL.SINGLE_H[3]
1101110CELL.DOUBLE_H1[1]
1111111CELL.SINGLE_H[2]
xc4000a IO_S0 switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[7][9]MAIN[9][7]MAIN[10][9]MAIN[7][7]MAIN[9][9]MAIN[7][6]MAIN[8][7]CELL.IMUX_CLB_C4
Source
0010101CELL.LONG_H[4]
0010110CELL.LONG_H[3]
0011111CELL.SINGLE_H[0]
0100101CELL_N.LONG_H[0]
0100110CELL_N.LONG_H[2]
0101111CELL.SINGLE_H[1]
0110001CELL.SINGLE_H[2]
0110010CELL.SINGLE_H[3]
0111011CELL.DOUBLE_H0[1]
1110101CELL.DOUBLE_H0[0]
1110110CELL.DOUBLE_H1[1]
1111111CELL.DOUBLE_H1[0]
xc4000a IO_S0 switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[21][2]MAIN[19][2]MAIN[20][3]MAIN[20][2]MAIN[22][2]CELL.IMUX_IO_O1[0]
Source
00011CELL.DOUBLE_V0[0]
00101CELL.LONG_V[2]
01111CELL.DOUBLE_V1[1]
10011CELL.DEC_H[0]
10101CELL.DEC_H[1]
10110CELL.LONG_V[3]
11111CELL.TIE_0
xc4000a IO_S0 switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[7][2]MAIN[10][2]MAIN[9][2]MAIN[8][2]MAIN[9][1]CELL.IMUX_IO_O1[1]
Source
00011CELL.DEC_H[0]
00101CELL.DEC_H[1]
01011CELL_E.LONG_V[0]
01101CELL_E.DOUBLE_V0[1]
01110CELL_E.LONG_V[1]
10111CELL_E.DOUBLE_V1[0]
11111CELL.TIE_0
xc4000a IO_S0 switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[23][2]MAIN[31][2]MAIN[31][3]MAIN[26][2]MAIN[29][2]MAIN[28][2]MAIN[27][2]MAIN[30][2]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[2]
01101111CELL.SINGLE_V[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[1]
xc4000a IO_S0 switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[0][3]MAIN[5][1]MAIN[1][1]MAIN[2][1]MAIN[4][1]MAIN[0][0]MAIN[1][3]MAIN[0][1]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_E.SINGLE_V[1]
01111101CELL_E.SINGLE_V[2]
01111110CELL_E.SINGLE_V[3]
11111111CELL_E.SINGLE_V[0]
xc4000a IO_S0 switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[23][1]MAIN[30][1]MAIN[25][2]MAIN[30][3]MAIN[28][1]MAIN[27][1]MAIN[26][1]MAIN[29][1]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[1]
01101111CELL.SINGLE_V[2]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[3]
xc4000a IO_S0 switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[0][2]MAIN[6][1]MAIN[5][2]MAIN[3][1]MAIN[7][1]MAIN[1][2]MAIN[2][2]MAIN[3][2]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_E.SINGLE_V[0]
01111101CELL_E.SINGLE_V[1]
01111110CELL_E.SINGLE_V[3]
11111111CELL_E.SINGLE_V[2]
xc4000a IO_S0 switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[14][2]MAIN[17][1]MAIN[15][2]MAIN[18][2]MAIN[17][2]MAIN[16][2]CELL.IMUX_IO_T[0]
Source
001111CELL.TIE_0
010011CELL.DOUBLE_IO_S0[1]
010111CELL.DOUBLE_IO_S0[0]
011001CELL.DEC_H[0]
011010CELL.LONG_IO_H[1]
011101CELL.LONG_IO_H[0]
011110CELL.GCLK[0]
111011CELL.DOUBLE_IO_S1[0]
111111CELL.DOUBLE_IO_S1[1]
xc4000a IO_S0 switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[12][2]MAIN[14][1]MAIN[11][2]MAIN[13][2]MAIN[16][1]MAIN[15][1]CELL.IMUX_IO_T[1]
Source
001111CELL.TIE_0
010011CELL.DOUBLE_IO_S1[1]
010101CELL.LONG_IO_H[0]
010110CELL.GCLK[0]
011011CELL.DOUBLE_IO_S1[0]
011101CELL.LONG_IO_H[1]
011110CELL.DEC_H[0]
110111CELL.DOUBLE_IO_S0[0]
111111CELL.DOUBLE_IO_S0[1]

Bels IO

xc4000a IO_S0 bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[21][0]CELL.IMUX_IO_IK[1] invert by !MAIN[11][0]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[28][0]CELL.IMUX_IO_OK[1] invert by !MAIN[4][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_F4CELL.IMUX_CLB_G4
TinCELL.IMUX_IO_T[0] invert by !MAIN[29][0]CELL.IMUX_IO_T[1] invert by !MAIN[3][0]
I1outCELL.OUT_IO_SN_I1[0]CELL.OUT_IO_SN_I1[1]
I2outCELL.OUT_IO_SN_I2[0]CELL.OUT_IO_SN_I2[1]
xc4000a IO_S0 bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[19][1]!MAIN[10][0]
OFF_SRVAL bit 0!MAIN[22][0]!MAIN[10][1]
READBACK_I1 bit 0!MAIN[15][4]!MAIN[16][3]
READBACK_I2 bit 0!MAIN[13][4]!MAIN[13][3]
READBACK_OQ bit 0!MAIN[24][1]!MAIN[4][2]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[25][0]!MAIN[7][0]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[23][0]MAIN[9][0]
xc4000a IO_S0 enum IO_SLEW
IO[0].SLEWMAIN[31][0]MAIN[30][0]
IO[1].SLEWMAIN[1][0]MAIN[2][0]
FAST00
MEDFAST01
MEDSLOW10
SLOW11
xc4000a IO_S0 enum IO_PULL
IO[0].PULLMAIN[21][1]MAIN[24][0]
IO[1].PULLMAIN[11][1]MAIN[8][0]
NONE11
PULLUP01
PULLDOWN10
xc4000a IO_S0 enum IO_MUX_I
IO[0].MUX_I1MAIN[17][0]MAIN[19][0]MAIN[18][0]
IO[1].MUX_I1MAIN[14][0]MAIN[16][0]MAIN[15][0]
IO[0].MUX_I2MAIN[20][0]MAIN[20][1]MAIN[22][1]
IO[1].MUX_I2MAIN[12][0]MAIN[12][1]MAIN[13][0]
I001
IQ111
IQL010
xc4000a IO_S0 enum IO_IFF_D
IO[0].IFF_DMAIN[18][1]
IO[1].IFF_DMAIN[13][1]
I1
DELAY0
xc4000a IO_S0 enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[26][0]
IO[1].MUX_OFF_DMAIN[6][0]
O11
O20
xc4000a IO_S0 enum IO_MUX_O
IO[0].MUX_OMAIN[27][0]MAIN[24][2]MAIN[25][1]
IO[1].MUX_OMAIN[5][0]MAIN[6][2]MAIN[8][1]
O1001
O1_INV010
O2100
O2_INV011
OQ000

Bels DEC

xc4000a IO_S0 bel DEC pins
PinDirectionDEC[0]DEC[1]DEC[2]
IinCELL.OUT_IO_SN_I1[0]CELL.IMUX_CLB_C4CELL.OUT_IO_SN_I1[1]
O1bidirCELL.DEC_H[0]CELL.DEC_H[0]CELL.DEC_H[0]
O2bidirCELL.DEC_H[1]CELL.DEC_H[1]CELL.DEC_H[1]
xc4000a IO_S0 bel DEC attribute bits
AttributeDEC[0]DEC[1]DEC[2]
O1_P!MAIN[6][5]!MAIN[8][5]MAIN[4][5]
O1_NMAIN[5][5]MAIN[4][4]!MAIN[7][5]
O2_P!MAIN[3][5]!MAIN[3][4]MAIN[0][5]
O2_NMAIN[1][5]MAIN[0][4]!MAIN[2][5]

Bel wires

xc4000a IO_S0 bel wires
WirePins
CELL.DEC_H[0]DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_H[1]DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.IMUX_CLB_F4IO[0].O2
CELL.IMUX_CLB_G4IO[1].O2
CELL.IMUX_CLB_C4DEC[1].I
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_SN_I1[0]IO[0].I1, DEC[0].I
CELL.OUT_IO_SN_I1[1]IO[1].I1, DEC[2].I
CELL.OUT_IO_SN_I2[0]IO[0].I2
CELL.OUT_IO_SN_I2[1]IO[1].I2

Bitstream

xc4000a IO_S0 rect MAIN
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] - - INT: !pass CELL.SINGLE_V[2] ← CELL.TIE_0 INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 6 - INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_C2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 4
B8 - INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] - - - - INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] - - - - - INT: mux CELL.IMUX_CLB_F2 bit 1 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 6
B7 - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[3] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_V[2] INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[4] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: !pass CELL.SINGLE_H[3] ← CELL.LONG_V[3] - - INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[1] INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[3] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H[2] INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 3
B6 - INT: !pass CELL.SINGLE_H_E[0] ← CELL.LONG_V[0] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[0] - - INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] - - INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[3] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_SN_I2[0] - INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_X_S INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 7
B5 INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_IO_H[0] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1 INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[1] INT: mux CELL.LONG_V[0] bit 3 INT: mux CELL.LONG_V[0] bit 0 INT: mux CELL.LONG_V[0] bit 1 INT: mux CELL.LONG_V[0] bit 2 INT: mux CELL.LONG_V[3] bit 3 INT: mux CELL.LONG_V[3] bit 0 INT: mux CELL.LONG_V[3] bit 1 INT: mux CELL.LONG_V[3] bit 2 INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[0] INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[2] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.LONG_V[1] bit 3 INT: mux CELL.LONG_V[1] bit 1 INT: mux CELL.LONG_V[2] bit 1 INT: mux CELL.LONG_V[1] bit 2 INT: mux CELL.LONG_V[2] bit 3 INT: mux CELL.LONG_V[2] bit 0 INT: mux CELL.LONG_V[2] bit 2 DEC[1]: ! O1_P DEC[2]: ! O1_N DEC[0]: ! O1_P DEC[0]: O1_N DEC[2]: O1_P DEC[0]: ! O2_P DEC[2]: ! O2_N DEC[0]: O2_N DEC[2]: O2_P
B4 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I2_E1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.SINGLE_V[2] ← CELL.DEC_H[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[1] INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_V[1] ← CELL.DEC_H[0] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_IO_H[1] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_IO_S0[0] ← CELL.DBUF_IO_H[1] INT: mux CELL.LONG_V[1] bit 0 INT: !pass CELL.DOUBLE_IO_S0[1] ← CELL.DBUF_IO_H[1] IO[0]: ! READBACK_I1 bit 0 INT: mux CELL.DBUF_IO_H[0] bit 1 IO[0]: ! READBACK_I2 bit 0 INT: mux CELL.DBUF_IO_H[0] bit 0 INT: !pass CELL.DOUBLE_IO_S2[1] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_S2[0] ← CELL.DBUF_IO_H[0] INT: mux CELL.DBUF_IO_H[1] bit 1 INT: mux CELL.DBUF_IO_H[1] bit 0 INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S0[1] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S1[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S1[1] DEC[1]: O1_N DEC[1]: ! O2_P INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S1[1] INT: mux CELL.LONG_IO_H[1] bit 4 DEC[1]: O2_N
B3 INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_IO_S0[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S1[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S1[0] INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S1[0] INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S2[1] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S2[1] IO[1]: ! READBACK_I1 bit 0 INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S2[1] INT: !bipass CELL.DOUBLE_IO_S0[1] = CELL.DOUBLE_IO_S2[1] IO[1]: ! READBACK_I2 bit 0 INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S0[1] INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S0[1] INT: mux CELL.LONG_IO_H[1] bit 1 INT: mux CELL.LONG_IO_H[1] bit 0 INT: mux CELL.LONG_IO_H[1] bit 2 INT: mux CELL.LONG_IO_H[1] bit 3 INT: mux CELL.LONG_IO_H[0] bit 0 INT: mux CELL.LONG_IO_H[0] bit 2 INT: mux CELL.LONG_IO_H[0] bit 1 INT: mux CELL.LONG_IO_H[0] bit 3 INT: mux CELL.LONG_IO_H[0] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 7
B2 INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 5 IO[0]: MUX_O bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 7 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 4 IO[1]: MUX_O bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 5 IO[1]: ! READBACK_OQ bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 7
B1 - INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 1 IO[0]: MUX_O bit 0 IO[0]: ! READBACK_OQ bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 7 IO[0]: MUX_I2 bit 0 IO[0]: PULL bit 1 IO[0]: MUX_I2 bit 1 IO[0]: ! IFF_SRVAL bit 0 IO[0]: IFF_D bit 0 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 4 IO[1]: IFF_D bit 0 IO[1]: MUX_I2 bit 1 IO[1]: PULL bit 1 IO[1]: ! OFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 0 IO[1]: MUX_O bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 0
B0 IO[0]: SLEW bit 1 IO[0]: SLEW bit 0 IO[0]: !invert T IO[0]: !invert OK IO[0]: MUX_O bit 2 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_D_INV IO[0]: PULL bit 0 IO[0]: OFF_USED IO[0]: ! OFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 2 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I1 bit 2 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 2 IO[1]: MUX_I2 bit 0 IO[1]: MUX_I2 bit 2 IO[1]: !invert IK IO[1]: ! IFF_SRVAL bit 0 IO[1]: OFF_USED IO[1]: PULL bit 0 IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0 IO[1]: MUX_O bit 2 IO[1]: !invert OK IO[1]: !invert T IO[1]: SLEW bit 0 IO[1]: SLEW bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 2
xc4000a IO_S0 rect MAIN_E
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_S0_E

Cells: 4

Switchbox INT

xc4000a IO_S0_E switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[3]CELL.SINGLE_V[2]!MAIN[18][5]
CELL.LONG_H[4]CELL.SINGLE_V[3]!MAIN[21][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[0]!MAIN[29][6]
CELL.LONG_V[1]CELL.SINGLE_H_E[1]!MAIN[14][7]
CELL.LONG_V[2]CELL.SINGLE_H[2]!MAIN[12][7]
CELL.LONG_V[3]CELL.SINGLE_H[3]!MAIN[13][7]
xc4000a IO_S0_E switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[12][9]
CELL.SINGLE_H[0]CELL.OUT_CLB_X_S!MAIN[11][6]
CELL.SINGLE_H[0]CELL.OUT_IO_SN_I2[1]!MAIN[16][6]
CELL.SINGLE_H[1]CELL.OUT_CLB_XQ_S!MAIN[9][6]
CELL.SINGLE_H[1]CELL.OUT_IO_SN_I2[0]!MAIN[14][6]
CELL.SINGLE_H[2]CELL.LONG_V[2]!MAIN[25][7]
CELL.SINGLE_H[2]CELL.OUT_CLB_X_S!MAIN[13][6]
CELL.SINGLE_H[2]CELL.OUT_IO_SN_I2[1]!MAIN[20][6]
CELL.SINGLE_H[3]CELL.LONG_V[3]!MAIN[17][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_XQ_S!MAIN[10][6]
CELL.SINGLE_H[3]CELL.OUT_IO_SN_I2[0]!MAIN[15][6]
CELL.SINGLE_H_E[0]CELL.LONG_V[0]!MAIN[30][6]
CELL.SINGLE_H_E[1]CELL.LONG_V[1]!MAIN[29][7]
CELL.SINGLE_V[0]CELL.LONG_IO_H[0]!MAIN[31][5]
CELL.SINGLE_V[0]CELL.DEC_H[1]!MAIN[28][5]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I1[0]!MAIN[30][5]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I2_E1!MAIN[29][5]
CELL.SINGLE_V[1]CELL.LONG_IO_H[1]!MAIN[25][4]
CELL.SINGLE_V[1]CELL.DEC_H[0]!MAIN[22][4]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I2[0]!MAIN[23][4]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I1_E1!MAIN[24][4]
CELL.SINGLE_V[2]CELL.TIE_0!MAIN[13][9]
CELL.SINGLE_V[2]CELL.LONG_H[3]!MAIN[30][7]
CELL.SINGLE_V[2]CELL.LONG_IO_H[0]!MAIN[31][4]
CELL.SINGLE_V[2]CELL.DEC_H[1]!MAIN[27][4]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I1[0]!MAIN[30][4]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I2_E1!MAIN[29][4]
CELL.SINGLE_V[3]CELL.LONG_H[4]!MAIN[24][7]
CELL.SINGLE_V[3]CELL.LONG_IO_H[1]!MAIN[20][4]
CELL.SINGLE_V[3]CELL.DEC_H[0]!MAIN[19][5]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I2[0]!MAIN[21][4]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I1_E1!MAIN[17][5]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[8][6]
CELL.DOUBLE_H0[1]CELL.OUT_IO_SN_I2[0]!MAIN[18][6]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[12][6]
CELL.DOUBLE_H1[1]CELL.OUT_IO_SN_I2[1]!MAIN[19][6]
CELL.DOUBLE_V0[0]CELL.OUT_IO_SN_I1_E1!MAIN[28][4]
CELL.DOUBLE_V0[1]CELL.OUT_IO_SN_I2[0]!MAIN[19][4]
CELL.DOUBLE_V1[0]CELL.OUT_IO_SN_I1[0]!MAIN[26][4]
CELL.DOUBLE_V1[1]CELL.OUT_IO_SN_I2_E1!MAIN[16][5]
CELL.DOUBLE_IO_S0[0]CELL.DBUF_IO_H[1]!MAIN[18][4]
CELL.DOUBLE_IO_S0[1]CELL.DBUF_IO_H[1]!MAIN[16][4]
CELL.DOUBLE_IO_S2[0]CELL.DBUF_IO_H[0]!MAIN[10][4]
CELL.DOUBLE_IO_S2[1]CELL.DBUF_IO_H[0]!MAIN[11][4]
xc4000a IO_S0_E switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[28][9]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[27][9]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[26][9]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[17][8]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[17][9]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[16][9]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[26][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[25][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[25][6]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[26][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[26][6]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[30][9]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[29][9]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[19][8]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[18][8]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[29][8]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[28][8]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[28][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[24][6]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[31][9]
CELL.SINGLE_V[0]CELL.DOUBLE_IO_S0[0]!MAIN[26][3]
CELL.SINGLE_V[0]CELL.DOUBLE_IO_S2[0]!MAIN[28][3]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[20][8]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_S1[0]!MAIN[19][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[30][8]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_S0[1]!MAIN[11][3]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_S2[1]!MAIN[18][3]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[27][7]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_S1[1]!MAIN[2][4]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[20][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[21][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[19][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[19][7]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[20][7]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[18][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[23][9]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[24][9]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[22][7]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[23][7]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][9]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S0[1]!MAIN[12][3]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S1[1]!MAIN[5][4]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S2[1]!MAIN[15][3]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[21][7]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S0[0]!MAIN[24][3]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S1[0]!MAIN[21][3]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S2[0]!MAIN[27][3]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S0[0]!MAIN[25][3]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S1[0]!MAIN[22][3]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S2[0]!MAIN[29][3]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S0[1]!MAIN[7][4]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S1[1]!MAIN[6][4]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S2[1]!MAIN[17][3]
CELL.DOUBLE_IO_S0[0]CELL.DOUBLE_IO_S2[0]!MAIN[23][3]
CELL.DOUBLE_IO_S0[1]CELL.DOUBLE_IO_S2[1]!MAIN[14][3]
xc4000a IO_S0_E switchbox INT muxes DBUF_IO_H[0]
BitsDestination
MAIN[14][4]MAIN[12][4]CELL.DBUF_IO_H[0]
Source
00CELL.DOUBLE_IO_S0[1]
11CELL.DOUBLE_IO_S0[0]
xc4000a IO_S0_E switchbox INT muxes DBUF_IO_H[1]
BitsDestination
MAIN[9][4]MAIN[8][4]CELL.DBUF_IO_H[1]
Source
00CELL.DOUBLE_IO_S2[0]
11CELL.DOUBLE_IO_S2[1]
xc4000a IO_S0_E switchbox INT muxes LONG_V[0]
BitsDestination
MAIN[27][5]MAIN[24][5]MAIN[25][5]MAIN[26][5]CELL.LONG_V[0]
Source
0001CELL.LONG_IO_H[0]
0010CELL.DEC_H[0]
0111CELL.OUT_IO_SN_I2_E1
1111off
xc4000a IO_S0_E switchbox INT muxes LONG_V[1]
BitsDestination
MAIN[15][5]MAIN[12][5]MAIN[14][5]MAIN[17][4]CELL.LONG_V[1]
Source
0001CELL.LONG_IO_H[1]
0010CELL.DEC_H[1]
0111CELL.OUT_IO_SN_I2_E1
1111off
xc4000a IO_S0_E switchbox INT muxes LONG_V[2]
BitsDestination
MAIN[11][5]MAIN[9][5]MAIN[13][5]MAIN[10][5]CELL.LONG_V[2]
Source
0001CELL.LONG_IO_H[0]
0010CELL.DEC_H[0]
0111CELL.OUT_IO_SN_I2[0]
1111off
xc4000a IO_S0_E switchbox INT muxes LONG_V[3]
BitsDestination
MAIN[23][5]MAIN[20][5]MAIN[21][5]MAIN[22][5]CELL.LONG_V[3]
Source
0001CELL.LONG_IO_H[1]
0010CELL.DEC_H[1]
0111CELL.OUT_IO_SN_I2[0]
1111off
xc4000a IO_S0_E switchbox INT muxes LONG_IO_H[0]
BitsDestination
MAIN[2][3]MAIN[3][3]MAIN[5][3]MAIN[4][3]MAIN[6][3]CELL.LONG_IO_H[0]
Source
00011CELL.SINGLE_V[2]
00101CELL.LONG_V[0]
00110CELL.LONG_V[2]
01111CELL.SINGLE_V[0]
11111off
xc4000a IO_S0_E switchbox INT muxes LONG_IO_H[1]
BitsDestination
MAIN[1][4]MAIN[7][3]MAIN[8][3]MAIN[10][3]MAIN[9][3]CELL.LONG_IO_H[1]
Source
00011CELL.SINGLE_V[3]
00101CELL.LONG_V[1]
00110CELL.LONG_V[3]
01111CELL.SINGLE_V[1]
11111off
xc4000a IO_S0_E switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[8][8]MAIN[10][7]MAIN[9][8]MAIN[10][8]MAIN[11][9]MAIN[11][8]MAIN[11][7]CELL.IMUX_CLB_F2
Source
0010011CELL.LONG_H[4]
0010101CELL.LONG_H[3]
0011111CELL.SINGLE_H[0]
0100011CELL_N.LONG_H[0]
0100101CELL_N.LONG_H[2]
0101111CELL.SINGLE_H[1]
0110010CELL.DOUBLE_H0[0]
0110100CELL.DOUBLE_H1[1]
0111110CELL.DOUBLE_H1[0]
1110011CELL.SINGLE_H[2]
1110101CELL.SINGLE_H[3]
1111111CELL.DOUBLE_H0[1]
xc4000a IO_S0_E switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[6][8]MAIN[6][6]MAIN[5][9]MAIN[7][8]MAIN[5][8]MAIN[6][7]MAIN[8][9]CELL.IMUX_CLB_F4
Source
0000111CELL.LONG_H[4]
0001011CELL.LONG_H[3]
0011111CELL.SINGLE_H[0]
0100101CELL.DOUBLE_H0[0]
0100110CELL_N.LONG_H[0]
0101001CELL.DOUBLE_H1[1]
0101010CELL_N.LONG_H[2]
0111101CELL.DOUBLE_H1[0]
0111110CELL.DOUBLE_H0[1]
1100111CELL.SINGLE_H[2]
1101011CELL.SINGLE_H[3]
1111111CELL.SINGLE_H[1]
xc4000a IO_S0_E switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[0][6]MAIN[2][7]MAIN[3][9]MAIN[2][6]MAIN[2][9]MAIN[3][8]MAIN[1][6]MAIN[3][6]CELL.IMUX_CLB_G2
Source
00011111CELL.SPECIAL_CLB_COUT0
00100111CELL.SINGLE_H[1]
00101011CELL_N.LONG_H[2]
00101110CELL.LONG_H[3]
00110101CELL.DOUBLE_H0[1]
00111001CELL_N.LONG_H[0]
00111100CELL.LONG_H[4]
01101111CELL.SINGLE_H[0]
01111101CELL.DOUBLE_H1[0]
10110111CELL.SINGLE_H[2]
10111011CELL.SINGLE_H[3]
10111110CELL.DOUBLE_H1[1]
11111111CELL.DOUBLE_H0[0]
xc4000a IO_S0_E switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[4][7]MAIN[5][6]MAIN[3][7]MAIN[4][8]MAIN[4][9]MAIN[4][6]MAIN[5][7]CELL.IMUX_CLB_G4
Source
0000111CELL.SINGLE_H[1]
0001011CELL_N.LONG_H[2]
0001101CELL.LONG_H[3]
0011111CELL.SINGLE_H[0]
0100110CELL.DOUBLE_H0[1]
0101010CELL_N.LONG_H[0]
0101100CELL.LONG_H[4]
0111110CELL.DOUBLE_H1[0]
1100111CELL.SINGLE_H[2]
1101011CELL.SINGLE_H[3]
1101101CELL.DOUBLE_H0[0]
1111111CELL.DOUBLE_H1[1]
xc4000a IO_S0_E switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[0][8]MAIN[2][8]MAIN[0][9]MAIN[0][7]MAIN[1][9]MAIN[1][8]MAIN[1][7]CELL.IMUX_CLB_C2
Source
0000111CELL.SINGLE_H[0]
0001011CELL_N.LONG_H[2]
0001110CELL.LONG_H[3]
0011111CELL.SINGLE_H[1]
0100101CELL.DOUBLE_H1[0]
0101001CELL_N.LONG_H[0]
0101100CELL.LONG_H[4]
0111101CELL.DOUBLE_H0[1]
1100111CELL.DOUBLE_H0[0]
1101011CELL.SINGLE_H[3]
1101110CELL.DOUBLE_H1[1]
1111111CELL.SINGLE_H[2]
xc4000a IO_S0_E switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[7][9]MAIN[9][7]MAIN[10][9]MAIN[7][7]MAIN[9][9]MAIN[7][6]MAIN[8][7]CELL.IMUX_CLB_C4
Source
0010101CELL.LONG_H[4]
0010110CELL.LONG_H[3]
0011111CELL.SINGLE_H[0]
0100101CELL_N.LONG_H[0]
0100110CELL_N.LONG_H[2]
0101111CELL.SINGLE_H[1]
0110001CELL.SINGLE_H[2]
0110010CELL.SINGLE_H[3]
0111011CELL.DOUBLE_H0[1]
1110101CELL.DOUBLE_H0[0]
1110110CELL.DOUBLE_H1[1]
1111111CELL.DOUBLE_H1[0]
xc4000a IO_S0_E switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[21][2]MAIN[19][2]MAIN[20][3]MAIN[20][2]MAIN[22][2]CELL.IMUX_IO_O1[0]
Source
00011CELL.DOUBLE_V0[0]
00101CELL.LONG_V[2]
01111CELL.DOUBLE_V1[1]
10011CELL.DEC_H[0]
10101CELL.DEC_H[1]
10110CELL.LONG_V[3]
11111CELL.TIE_0
xc4000a IO_S0_E switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[7][2]MAIN[10][2]MAIN[9][2]MAIN[8][2]MAIN[9][1]CELL.IMUX_IO_O1[1]
Source
00011CELL.DEC_H[0]
00101CELL.DEC_H[1]
01011CELL_E.LONG_V[0]
01101CELL_E.DOUBLE_V0[1]
01110CELL_E.LONG_V[1]
10111CELL_E.DOUBLE_V1[0]
11111CELL.TIE_0
xc4000a IO_S0_E switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[23][2]MAIN[31][2]MAIN[31][3]MAIN[26][2]MAIN[29][2]MAIN[28][2]MAIN[27][2]MAIN[30][2]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[2]
01101111CELL.SINGLE_V[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[1]
xc4000a IO_S0_E switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[0][3]MAIN[5][1]MAIN[1][1]MAIN[2][1]MAIN[4][1]MAIN[0][0]MAIN[1][3]MAIN[0][1]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_E.SINGLE_V[1]
01111101CELL_E.SINGLE_V[2]
01111110CELL_E.SINGLE_V[3]
11111111CELL_E.SINGLE_V[0]
xc4000a IO_S0_E switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[23][1]MAIN[30][1]MAIN[25][2]MAIN[30][3]MAIN[28][1]MAIN[27][1]MAIN[26][1]MAIN[29][1]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[1]
01101111CELL.SINGLE_V[2]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[3]
xc4000a IO_S0_E switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[0][2]MAIN[6][1]MAIN[5][2]MAIN[3][1]MAIN[7][1]MAIN[1][2]MAIN[2][2]MAIN[3][2]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_E.SINGLE_V[0]
01111101CELL_E.SINGLE_V[1]
01111110CELL_E.SINGLE_V[3]
11111111CELL_E.SINGLE_V[2]
xc4000a IO_S0_E switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[14][2]MAIN[17][1]MAIN[15][2]MAIN[18][2]MAIN[17][2]MAIN[16][2]CELL.IMUX_IO_T[0]
Source
001111CELL.TIE_0
010011CELL.DOUBLE_IO_S0[1]
010111CELL.DOUBLE_IO_S0[0]
011001CELL.DEC_H[0]
011010CELL.LONG_IO_H[1]
011101CELL.LONG_IO_H[0]
011110CELL.GCLK[0]
111011CELL.DOUBLE_IO_S1[0]
111111CELL.DOUBLE_IO_S1[1]
xc4000a IO_S0_E switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[12][2]MAIN[14][1]MAIN[11][2]MAIN[13][2]MAIN[16][1]MAIN[15][1]CELL.IMUX_IO_T[1]
Source
001111CELL.TIE_0
010011CELL.DOUBLE_IO_S1[1]
010101CELL.LONG_IO_H[0]
010110CELL.GCLK[0]
011011CELL.DOUBLE_IO_S1[0]
011101CELL.LONG_IO_H[1]
011110CELL.DEC_H[0]
110111CELL.DOUBLE_IO_S0[0]
111111CELL.DOUBLE_IO_S0[1]

Bels IO

xc4000a IO_S0_E bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[21][0]CELL.IMUX_IO_IK[1] invert by !MAIN[11][0]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[28][0]CELL.IMUX_IO_OK[1] invert by !MAIN[4][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_F4CELL.IMUX_CLB_G4
TinCELL.IMUX_IO_T[0] invert by !MAIN[29][0]CELL.IMUX_IO_T[1] invert by !MAIN[3][0]
I1outCELL.OUT_IO_SN_I1[0]CELL.OUT_IO_SN_I1[1]
I2outCELL.OUT_IO_SN_I2[0]CELL.OUT_IO_SN_I2[1]
CLKINout-CELL.OUT_IO_CLKIN
xc4000a IO_S0_E bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[19][1]!MAIN[10][0]
OFF_SRVAL bit 0!MAIN[22][0]!MAIN[10][1]
READBACK_I1 bit 0!MAIN[15][4]!MAIN[16][3]
READBACK_I2 bit 0!MAIN[13][4]!MAIN[13][3]
READBACK_OQ bit 0!MAIN[24][1]!MAIN[4][2]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[25][0]!MAIN[7][0]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[23][0]MAIN[9][0]
xc4000a IO_S0_E enum IO_SLEW
IO[0].SLEWMAIN[31][0]MAIN[30][0]
IO[1].SLEWMAIN[1][0]MAIN[2][0]
FAST00
MEDFAST01
MEDSLOW10
SLOW11
xc4000a IO_S0_E enum IO_PULL
IO[0].PULLMAIN[21][1]MAIN[24][0]
IO[1].PULLMAIN[11][1]MAIN[8][0]
NONE11
PULLUP01
PULLDOWN10
xc4000a IO_S0_E enum IO_MUX_I
IO[0].MUX_I1MAIN[17][0]MAIN[19][0]MAIN[18][0]
IO[1].MUX_I1MAIN[14][0]MAIN[16][0]MAIN[15][0]
IO[0].MUX_I2MAIN[20][0]MAIN[20][1]MAIN[22][1]
IO[1].MUX_I2MAIN[12][0]MAIN[12][1]MAIN[13][0]
I001
IQ111
IQL010
xc4000a IO_S0_E enum IO_IFF_D
IO[0].IFF_DMAIN[18][1]
IO[1].IFF_DMAIN[13][1]
I1
DELAY0
xc4000a IO_S0_E enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[26][0]
IO[1].MUX_OFF_DMAIN[6][0]
O11
O20
xc4000a IO_S0_E enum IO_MUX_O
IO[0].MUX_OMAIN[27][0]MAIN[24][2]MAIN[25][1]
IO[1].MUX_OMAIN[5][0]MAIN[6][2]MAIN[8][1]
O1001
O1_INV010
O2100
O2_INV011
OQ000

Bels DEC

xc4000a IO_S0_E bel DEC pins
PinDirectionDEC[0]DEC[1]DEC[2]
IinCELL.OUT_IO_SN_I1[0]CELL.IMUX_CLB_C4CELL.OUT_IO_SN_I1[1]
O1bidirCELL.DEC_H[0]CELL.DEC_H[0]CELL.DEC_H[0]
O2bidirCELL.DEC_H[1]CELL.DEC_H[1]CELL.DEC_H[1]
xc4000a IO_S0_E bel DEC attribute bits
AttributeDEC[0]DEC[1]DEC[2]
O1_P!MAIN[6][5]!MAIN[8][5]MAIN[4][5]
O1_NMAIN[5][5]MAIN[4][4]!MAIN[7][5]
O2_P!MAIN[3][5]!MAIN[3][4]MAIN[0][5]
O2_NMAIN[1][5]MAIN[0][4]!MAIN[2][5]

Bel wires

xc4000a IO_S0_E bel wires
WirePins
CELL.DEC_H[0]DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_H[1]DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.IMUX_CLB_F4IO[0].O2
CELL.IMUX_CLB_G4IO[1].O2
CELL.IMUX_CLB_C4DEC[1].I
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_SN_I1[0]IO[0].I1, DEC[0].I
CELL.OUT_IO_SN_I1[1]IO[1].I1, DEC[2].I
CELL.OUT_IO_SN_I2[0]IO[0].I2
CELL.OUT_IO_SN_I2[1]IO[1].I2
CELL.OUT_IO_CLKINIO[1].CLKIN

Bitstream

xc4000a IO_S0_E rect MAIN
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] - - INT: !pass CELL.SINGLE_V[2] ← CELL.TIE_0 INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 6 - INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_C2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 4
B8 - INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] - - - - INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] - - - - - INT: mux CELL.IMUX_CLB_F2 bit 1 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 6
B7 - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[3] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_V[2] INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[4] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: !pass CELL.SINGLE_H[3] ← CELL.LONG_V[3] - - INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[1] INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[3] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H[2] INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 3
B6 - INT: !pass CELL.SINGLE_H_E[0] ← CELL.LONG_V[0] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[0] - - INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] - - INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[3] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_SN_I2[0] - INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_X_S INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 7
B5 INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_IO_H[0] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1 INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[1] INT: mux CELL.LONG_V[0] bit 3 INT: mux CELL.LONG_V[0] bit 0 INT: mux CELL.LONG_V[0] bit 1 INT: mux CELL.LONG_V[0] bit 2 INT: mux CELL.LONG_V[3] bit 3 INT: mux CELL.LONG_V[3] bit 0 INT: mux CELL.LONG_V[3] bit 1 INT: mux CELL.LONG_V[3] bit 2 INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[0] INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[2] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.LONG_V[1] bit 3 INT: mux CELL.LONG_V[1] bit 1 INT: mux CELL.LONG_V[2] bit 1 INT: mux CELL.LONG_V[1] bit 2 INT: mux CELL.LONG_V[2] bit 3 INT: mux CELL.LONG_V[2] bit 0 INT: mux CELL.LONG_V[2] bit 2 DEC[1]: ! O1_P DEC[2]: ! O1_N DEC[0]: ! O1_P DEC[0]: O1_N DEC[2]: O1_P DEC[0]: ! O2_P DEC[2]: ! O2_N DEC[0]: O2_N DEC[2]: O2_P
B4 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I2_E1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.SINGLE_V[2] ← CELL.DEC_H[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[1] INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_V[1] ← CELL.DEC_H[0] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_IO_H[1] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_IO_S0[0] ← CELL.DBUF_IO_H[1] INT: mux CELL.LONG_V[1] bit 0 INT: !pass CELL.DOUBLE_IO_S0[1] ← CELL.DBUF_IO_H[1] IO[0]: ! READBACK_I1 bit 0 INT: mux CELL.DBUF_IO_H[0] bit 1 IO[0]: ! READBACK_I2 bit 0 INT: mux CELL.DBUF_IO_H[0] bit 0 INT: !pass CELL.DOUBLE_IO_S2[1] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_S2[0] ← CELL.DBUF_IO_H[0] INT: mux CELL.DBUF_IO_H[1] bit 1 INT: mux CELL.DBUF_IO_H[1] bit 0 INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S0[1] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S1[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S1[1] DEC[1]: O1_N DEC[1]: ! O2_P INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S1[1] INT: mux CELL.LONG_IO_H[1] bit 4 DEC[1]: O2_N
B3 INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_IO_S0[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S1[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S1[0] INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S1[0] INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S2[1] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S2[1] IO[1]: ! READBACK_I1 bit 0 INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S2[1] INT: !bipass CELL.DOUBLE_IO_S0[1] = CELL.DOUBLE_IO_S2[1] IO[1]: ! READBACK_I2 bit 0 INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S0[1] INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S0[1] INT: mux CELL.LONG_IO_H[1] bit 1 INT: mux CELL.LONG_IO_H[1] bit 0 INT: mux CELL.LONG_IO_H[1] bit 2 INT: mux CELL.LONG_IO_H[1] bit 3 INT: mux CELL.LONG_IO_H[0] bit 0 INT: mux CELL.LONG_IO_H[0] bit 2 INT: mux CELL.LONG_IO_H[0] bit 1 INT: mux CELL.LONG_IO_H[0] bit 3 INT: mux CELL.LONG_IO_H[0] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 7
B2 INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 5 IO[0]: MUX_O bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 7 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 4 IO[1]: MUX_O bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 5 IO[1]: ! READBACK_OQ bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 7
B1 - INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 1 IO[0]: MUX_O bit 0 IO[0]: ! READBACK_OQ bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 7 IO[0]: MUX_I2 bit 0 IO[0]: PULL bit 1 IO[0]: MUX_I2 bit 1 IO[0]: ! IFF_SRVAL bit 0 IO[0]: IFF_D bit 0 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 4 IO[1]: IFF_D bit 0 IO[1]: MUX_I2 bit 1 IO[1]: PULL bit 1 IO[1]: ! OFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 0 IO[1]: MUX_O bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 0
B0 IO[0]: SLEW bit 1 IO[0]: SLEW bit 0 IO[0]: !invert T IO[0]: !invert OK IO[0]: MUX_O bit 2 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_D_INV IO[0]: PULL bit 0 IO[0]: OFF_USED IO[0]: ! OFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 2 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I1 bit 2 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 2 IO[1]: MUX_I2 bit 0 IO[1]: MUX_I2 bit 2 IO[1]: !invert IK IO[1]: ! IFF_SRVAL bit 0 IO[1]: OFF_USED IO[1]: PULL bit 0 IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0 IO[1]: MUX_O bit 2 IO[1]: !invert OK IO[1]: !invert T IO[1]: SLEW bit 0 IO[1]: SLEW bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 2
xc4000a IO_S0_E rect MAIN_E
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_S1

Cells: 4

Switchbox INT

xc4000a IO_S1 switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[3]CELL.SINGLE_V[2]!MAIN[18][5]
CELL.LONG_H[4]CELL.SINGLE_V[3]!MAIN[21][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[0]!MAIN[29][6]
CELL.LONG_V[1]CELL.SINGLE_H_E[1]!MAIN[14][7]
CELL.LONG_V[2]CELL.SINGLE_H[2]!MAIN[12][7]
CELL.LONG_V[3]CELL.SINGLE_H[3]!MAIN[13][7]
xc4000a IO_S1 switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[12][9]
CELL.SINGLE_H[0]CELL.OUT_CLB_X_S!MAIN[11][6]
CELL.SINGLE_H[0]CELL.OUT_IO_SN_I2[1]!MAIN[16][6]
CELL.SINGLE_H[1]CELL.OUT_CLB_XQ_S!MAIN[9][6]
CELL.SINGLE_H[1]CELL.OUT_IO_SN_I2[0]!MAIN[14][6]
CELL.SINGLE_H[2]CELL.LONG_V[2]!MAIN[25][7]
CELL.SINGLE_H[2]CELL.OUT_CLB_X_S!MAIN[13][6]
CELL.SINGLE_H[2]CELL.OUT_IO_SN_I2[1]!MAIN[20][6]
CELL.SINGLE_H[3]CELL.LONG_V[3]!MAIN[17][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_XQ_S!MAIN[10][6]
CELL.SINGLE_H[3]CELL.OUT_IO_SN_I2[0]!MAIN[15][6]
CELL.SINGLE_H_E[0]CELL.LONG_V[0]!MAIN[30][6]
CELL.SINGLE_H_E[1]CELL.LONG_V[1]!MAIN[29][7]
CELL.SINGLE_V[0]CELL.LONG_IO_H[0]!MAIN[31][5]
CELL.SINGLE_V[0]CELL.DEC_H[1]!MAIN[28][5]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I1[0]!MAIN[30][5]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I2_E1!MAIN[29][5]
CELL.SINGLE_V[1]CELL.LONG_IO_H[1]!MAIN[25][4]
CELL.SINGLE_V[1]CELL.DEC_H[0]!MAIN[22][4]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I2[0]!MAIN[23][4]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I1_E1!MAIN[24][4]
CELL.SINGLE_V[2]CELL.TIE_0!MAIN[13][9]
CELL.SINGLE_V[2]CELL.LONG_H[3]!MAIN[30][7]
CELL.SINGLE_V[2]CELL.LONG_IO_H[0]!MAIN[31][4]
CELL.SINGLE_V[2]CELL.DEC_H[1]!MAIN[27][4]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I1[0]!MAIN[30][4]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I2_E1!MAIN[29][4]
CELL.SINGLE_V[3]CELL.LONG_H[4]!MAIN[24][7]
CELL.SINGLE_V[3]CELL.LONG_IO_H[1]!MAIN[20][4]
CELL.SINGLE_V[3]CELL.DEC_H[0]!MAIN[19][5]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I2[0]!MAIN[21][4]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I1_E1!MAIN[17][5]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[8][6]
CELL.DOUBLE_H0[1]CELL.OUT_IO_SN_I2[0]!MAIN[18][6]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[12][6]
CELL.DOUBLE_H1[1]CELL.OUT_IO_SN_I2[1]!MAIN[19][6]
CELL.DOUBLE_V0[0]CELL.OUT_IO_SN_I1_E1!MAIN[28][4]
CELL.DOUBLE_V0[1]CELL.OUT_IO_SN_I2[0]!MAIN[19][4]
CELL.DOUBLE_V1[0]CELL.OUT_IO_SN_I1[0]!MAIN[26][4]
CELL.DOUBLE_V1[1]CELL.OUT_IO_SN_I2_E1!MAIN[16][5]
CELL.DOUBLE_IO_S0[0]CELL.DBUF_IO_H[1]!MAIN[18][4]
CELL.DOUBLE_IO_S0[1]CELL.DBUF_IO_H[1]!MAIN[16][4]
CELL.DOUBLE_IO_S2[0]CELL.DBUF_IO_H[0]!MAIN[10][4]
CELL.DOUBLE_IO_S2[1]CELL.DBUF_IO_H[0]!MAIN[11][4]
xc4000a IO_S1 switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[28][9]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[27][9]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[26][9]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[17][8]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[17][9]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[16][9]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[26][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[25][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[25][6]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[26][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[26][6]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[30][9]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[29][9]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[19][8]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[18][8]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[29][8]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[28][8]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[28][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[24][6]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[31][9]
CELL.SINGLE_V[0]CELL.DOUBLE_IO_S1[0]!MAIN[19][3]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[20][8]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_S0[0]!MAIN[26][3]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_S2[0]!MAIN[28][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[30][8]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_S1[1]!MAIN[2][4]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[27][7]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_S0[1]!MAIN[11][3]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_S2[1]!MAIN[18][3]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[20][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[21][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[19][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[19][7]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[20][7]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[18][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[23][9]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[24][9]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[22][7]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[23][7]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][9]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S0[1]!MAIN[12][3]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S1[1]!MAIN[5][4]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S2[1]!MAIN[15][3]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[21][7]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S0[0]!MAIN[24][3]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S1[0]!MAIN[21][3]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S2[0]!MAIN[27][3]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S0[0]!MAIN[25][3]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S1[0]!MAIN[22][3]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S2[0]!MAIN[29][3]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S0[1]!MAIN[7][4]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S1[1]!MAIN[6][4]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S2[1]!MAIN[17][3]
CELL.DOUBLE_IO_S0[0]CELL.DOUBLE_IO_S2[0]!MAIN[23][3]
CELL.DOUBLE_IO_S0[1]CELL.DOUBLE_IO_S2[1]!MAIN[14][3]
xc4000a IO_S1 switchbox INT muxes DBUF_IO_H[0]
BitsDestination
MAIN[14][4]MAIN[12][4]CELL.DBUF_IO_H[0]
Source
00CELL.DOUBLE_IO_S0[1]
11CELL.DOUBLE_IO_S0[0]
xc4000a IO_S1 switchbox INT muxes DBUF_IO_H[1]
BitsDestination
MAIN[9][4]MAIN[8][4]CELL.DBUF_IO_H[1]
Source
00CELL.DOUBLE_IO_S2[0]
11CELL.DOUBLE_IO_S2[1]
xc4000a IO_S1 switchbox INT muxes LONG_V[0]
BitsDestination
MAIN[27][5]MAIN[24][5]MAIN[25][5]MAIN[26][5]CELL.LONG_V[0]
Source
0001CELL.LONG_IO_H[0]
0010CELL.DEC_H[0]
0111CELL.OUT_IO_SN_I2_E1
1111off
xc4000a IO_S1 switchbox INT muxes LONG_V[1]
BitsDestination
MAIN[15][5]MAIN[12][5]MAIN[14][5]MAIN[17][4]CELL.LONG_V[1]
Source
0001CELL.LONG_IO_H[1]
0010CELL.DEC_H[1]
0111CELL.OUT_IO_SN_I2_E1
1111off
xc4000a IO_S1 switchbox INT muxes LONG_V[2]
BitsDestination
MAIN[11][5]MAIN[9][5]MAIN[13][5]MAIN[10][5]CELL.LONG_V[2]
Source
0001CELL.LONG_IO_H[0]
0010CELL.DEC_H[0]
0111CELL.OUT_IO_SN_I2[0]
1111off
xc4000a IO_S1 switchbox INT muxes LONG_V[3]
BitsDestination
MAIN[23][5]MAIN[20][5]MAIN[21][5]MAIN[22][5]CELL.LONG_V[3]
Source
0001CELL.LONG_IO_H[1]
0010CELL.DEC_H[1]
0111CELL.OUT_IO_SN_I2[0]
1111off
xc4000a IO_S1 switchbox INT muxes LONG_IO_H[0]
BitsDestination
MAIN[2][3]MAIN[3][3]MAIN[5][3]MAIN[4][3]MAIN[6][3]CELL.LONG_IO_H[0]
Source
00011CELL.SINGLE_V[2]
00101CELL.LONG_V[0]
00110CELL.LONG_V[2]
01111CELL.SINGLE_V[0]
11111off
xc4000a IO_S1 switchbox INT muxes LONG_IO_H[1]
BitsDestination
MAIN[1][4]MAIN[7][3]MAIN[8][3]MAIN[10][3]MAIN[9][3]CELL.LONG_IO_H[1]
Source
00011CELL.SINGLE_V[3]
00101CELL.LONG_V[1]
00110CELL.LONG_V[3]
01111CELL.SINGLE_V[1]
11111off
xc4000a IO_S1 switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[8][8]MAIN[10][7]MAIN[9][8]MAIN[10][8]MAIN[11][9]MAIN[11][8]MAIN[11][7]CELL.IMUX_CLB_F2
Source
0010011CELL.LONG_H[4]
0010101CELL.LONG_H[3]
0011111CELL.SINGLE_H[0]
0100011CELL_N.LONG_H[0]
0100101CELL_N.LONG_H[2]
0101111CELL.SINGLE_H[1]
0110010CELL.DOUBLE_H0[0]
0110100CELL.DOUBLE_H1[1]
0111110CELL.DOUBLE_H1[0]
1110011CELL.SINGLE_H[2]
1110101CELL.SINGLE_H[3]
1111111CELL.DOUBLE_H0[1]
xc4000a IO_S1 switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[6][8]MAIN[6][6]MAIN[5][9]MAIN[7][8]MAIN[5][8]MAIN[6][7]MAIN[8][9]CELL.IMUX_CLB_F4
Source
0000111CELL.LONG_H[4]
0001011CELL.LONG_H[3]
0011111CELL.SINGLE_H[0]
0100101CELL.DOUBLE_H0[0]
0100110CELL_N.LONG_H[0]
0101001CELL.DOUBLE_H1[1]
0101010CELL_N.LONG_H[2]
0111101CELL.DOUBLE_H1[0]
0111110CELL.DOUBLE_H0[1]
1100111CELL.SINGLE_H[2]
1101011CELL.SINGLE_H[3]
1111111CELL.SINGLE_H[1]
xc4000a IO_S1 switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[0][6]MAIN[2][7]MAIN[3][9]MAIN[2][6]MAIN[2][9]MAIN[3][8]MAIN[1][6]MAIN[3][6]CELL.IMUX_CLB_G2
Source
00011111CELL.SPECIAL_CLB_COUT0
00100111CELL.SINGLE_H[1]
00101011CELL_N.LONG_H[2]
00101110CELL.LONG_H[3]
00110101CELL.DOUBLE_H0[1]
00111001CELL_N.LONG_H[0]
00111100CELL.LONG_H[4]
01101111CELL.SINGLE_H[0]
01111101CELL.DOUBLE_H1[0]
10110111CELL.SINGLE_H[2]
10111011CELL.SINGLE_H[3]
10111110CELL.DOUBLE_H1[1]
11111111CELL.DOUBLE_H0[0]
xc4000a IO_S1 switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[4][7]MAIN[5][6]MAIN[3][7]MAIN[4][8]MAIN[4][9]MAIN[4][6]MAIN[5][7]CELL.IMUX_CLB_G4
Source
0000111CELL.SINGLE_H[1]
0001011CELL_N.LONG_H[2]
0001101CELL.LONG_H[3]
0011111CELL.SINGLE_H[0]
0100110CELL.DOUBLE_H0[1]
0101010CELL_N.LONG_H[0]
0101100CELL.LONG_H[4]
0111110CELL.DOUBLE_H1[0]
1100111CELL.SINGLE_H[2]
1101011CELL.SINGLE_H[3]
1101101CELL.DOUBLE_H0[0]
1111111CELL.DOUBLE_H1[1]
xc4000a IO_S1 switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[0][8]MAIN[2][8]MAIN[0][9]MAIN[0][7]MAIN[1][9]MAIN[1][8]MAIN[1][7]CELL.IMUX_CLB_C2
Source
0000111CELL.SINGLE_H[0]
0001011CELL_N.LONG_H[2]
0001110CELL.LONG_H[3]
0011111CELL.SINGLE_H[1]
0100101CELL.DOUBLE_H1[0]
0101001CELL_N.LONG_H[0]
0101100CELL.LONG_H[4]
0111101CELL.DOUBLE_H0[1]
1100111CELL.DOUBLE_H0[0]
1101011CELL.SINGLE_H[3]
1101110CELL.DOUBLE_H1[1]
1111111CELL.SINGLE_H[2]
xc4000a IO_S1 switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[7][9]MAIN[9][7]MAIN[10][9]MAIN[7][7]MAIN[9][9]MAIN[7][6]MAIN[8][7]CELL.IMUX_CLB_C4
Source
0010101CELL.LONG_H[4]
0010110CELL.LONG_H[3]
0011111CELL.SINGLE_H[0]
0100101CELL_N.LONG_H[0]
0100110CELL_N.LONG_H[2]
0101111CELL.SINGLE_H[1]
0110001CELL.SINGLE_H[2]
0110010CELL.SINGLE_H[3]
0111011CELL.DOUBLE_H0[1]
1110101CELL.DOUBLE_H0[0]
1110110CELL.DOUBLE_H1[1]
1111111CELL.DOUBLE_H1[0]
xc4000a IO_S1 switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[21][2]MAIN[19][2]MAIN[20][3]MAIN[20][2]MAIN[22][2]CELL.IMUX_IO_O1[0]
Source
00011CELL.DOUBLE_V0[0]
00101CELL.LONG_V[2]
01111CELL.DOUBLE_V1[1]
10011CELL.DEC_H[0]
10101CELL.DEC_H[1]
10110CELL.LONG_V[3]
11111CELL.TIE_0
xc4000a IO_S1 switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[7][2]MAIN[10][2]MAIN[9][2]MAIN[8][2]MAIN[9][1]CELL.IMUX_IO_O1[1]
Source
00011CELL.DEC_H[0]
00101CELL.DEC_H[1]
01011CELL_E.LONG_V[0]
01101CELL_E.DOUBLE_V0[1]
01110CELL_E.LONG_V[1]
10111CELL_E.DOUBLE_V1[0]
11111CELL.TIE_0
xc4000a IO_S1 switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[23][2]MAIN[31][2]MAIN[31][3]MAIN[26][2]MAIN[29][2]MAIN[28][2]MAIN[27][2]MAIN[30][2]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[2]
01101111CELL.SINGLE_V[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[1]
xc4000a IO_S1 switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[0][3]MAIN[5][1]MAIN[1][1]MAIN[2][1]MAIN[4][1]MAIN[0][0]MAIN[1][3]MAIN[0][1]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_E.SINGLE_V[1]
01111101CELL_E.SINGLE_V[2]
01111110CELL_E.SINGLE_V[3]
11111111CELL_E.SINGLE_V[0]
xc4000a IO_S1 switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[23][1]MAIN[30][1]MAIN[25][2]MAIN[30][3]MAIN[28][1]MAIN[27][1]MAIN[26][1]MAIN[29][1]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[1]
01101111CELL.SINGLE_V[2]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[3]
xc4000a IO_S1 switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[0][2]MAIN[6][1]MAIN[5][2]MAIN[3][1]MAIN[7][1]MAIN[1][2]MAIN[2][2]MAIN[3][2]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_E.SINGLE_V[0]
01111101CELL_E.SINGLE_V[1]
01111110CELL_E.SINGLE_V[3]
11111111CELL_E.SINGLE_V[2]
xc4000a IO_S1 switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[14][2]MAIN[17][1]MAIN[15][2]MAIN[18][2]MAIN[17][2]MAIN[16][2]CELL.IMUX_IO_T[0]
Source
001111CELL.TIE_0
010011CELL.DOUBLE_IO_S0[1]
010111CELL.DOUBLE_IO_S0[0]
011001CELL.DEC_H[0]
011010CELL.LONG_IO_H[1]
011101CELL.LONG_IO_H[0]
011110CELL.GCLK[0]
111011CELL.DOUBLE_IO_S1[0]
111111CELL.DOUBLE_IO_S1[1]
xc4000a IO_S1 switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[12][2]MAIN[14][1]MAIN[11][2]MAIN[13][2]MAIN[16][1]MAIN[15][1]CELL.IMUX_IO_T[1]
Source
001111CELL.TIE_0
010011CELL.DOUBLE_IO_S1[1]
010101CELL.LONG_IO_H[0]
010110CELL.GCLK[0]
011011CELL.DOUBLE_IO_S1[0]
011101CELL.LONG_IO_H[1]
011110CELL.DEC_H[0]
110111CELL.DOUBLE_IO_S0[0]
111111CELL.DOUBLE_IO_S0[1]

Bels IO

xc4000a IO_S1 bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[21][0]CELL.IMUX_IO_IK[1] invert by !MAIN[11][0]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[28][0]CELL.IMUX_IO_OK[1] invert by !MAIN[4][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_F4CELL.IMUX_CLB_G4
TinCELL.IMUX_IO_T[0] invert by !MAIN[29][0]CELL.IMUX_IO_T[1] invert by !MAIN[3][0]
I1outCELL.OUT_IO_SN_I1[0]CELL.OUT_IO_SN_I1[1]
I2outCELL.OUT_IO_SN_I2[0]CELL.OUT_IO_SN_I2[1]
xc4000a IO_S1 bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[19][1]!MAIN[10][0]
OFF_SRVAL bit 0!MAIN[22][0]!MAIN[10][1]
READBACK_I1 bit 0!MAIN[15][4]!MAIN[16][3]
READBACK_I2 bit 0!MAIN[13][4]!MAIN[13][3]
READBACK_OQ bit 0!MAIN[24][1]!MAIN[4][2]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[25][0]!MAIN[7][0]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[23][0]MAIN[9][0]
xc4000a IO_S1 enum IO_SLEW
IO[0].SLEWMAIN[31][0]MAIN[30][0]
IO[1].SLEWMAIN[1][0]MAIN[2][0]
FAST00
MEDFAST01
MEDSLOW10
SLOW11
xc4000a IO_S1 enum IO_PULL
IO[0].PULLMAIN[21][1]MAIN[24][0]
IO[1].PULLMAIN[11][1]MAIN[8][0]
NONE11
PULLUP01
PULLDOWN10
xc4000a IO_S1 enum IO_MUX_I
IO[0].MUX_I1MAIN[17][0]MAIN[19][0]MAIN[18][0]
IO[1].MUX_I1MAIN[14][0]MAIN[16][0]MAIN[15][0]
IO[0].MUX_I2MAIN[20][0]MAIN[20][1]MAIN[22][1]
IO[1].MUX_I2MAIN[12][0]MAIN[12][1]MAIN[13][0]
I001
IQ111
IQL010
xc4000a IO_S1 enum IO_IFF_D
IO[0].IFF_DMAIN[18][1]
IO[1].IFF_DMAIN[13][1]
I1
DELAY0
xc4000a IO_S1 enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[26][0]
IO[1].MUX_OFF_DMAIN[6][0]
O11
O20
xc4000a IO_S1 enum IO_MUX_O
IO[0].MUX_OMAIN[27][0]MAIN[24][2]MAIN[25][1]
IO[1].MUX_OMAIN[5][0]MAIN[6][2]MAIN[8][1]
O1001
O1_INV010
O2100
O2_INV011
OQ000

Bels DEC

xc4000a IO_S1 bel DEC pins
PinDirectionDEC[0]DEC[1]DEC[2]
IinCELL.OUT_IO_SN_I1[0]CELL.IMUX_CLB_C4CELL.OUT_IO_SN_I1[1]
O1bidirCELL.DEC_H[0]CELL.DEC_H[0]CELL.DEC_H[0]
O2bidirCELL.DEC_H[1]CELL.DEC_H[1]CELL.DEC_H[1]
xc4000a IO_S1 bel DEC attribute bits
AttributeDEC[0]DEC[1]DEC[2]
O1_P!MAIN[6][5]!MAIN[8][5]MAIN[4][5]
O1_NMAIN[5][5]MAIN[4][4]!MAIN[7][5]
O2_P!MAIN[3][5]!MAIN[3][4]MAIN[0][5]
O2_NMAIN[1][5]MAIN[0][4]!MAIN[2][5]

Bel wires

xc4000a IO_S1 bel wires
WirePins
CELL.DEC_H[0]DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_H[1]DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.IMUX_CLB_F4IO[0].O2
CELL.IMUX_CLB_G4IO[1].O2
CELL.IMUX_CLB_C4DEC[1].I
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_SN_I1[0]IO[0].I1, DEC[0].I
CELL.OUT_IO_SN_I1[1]IO[1].I1, DEC[2].I
CELL.OUT_IO_SN_I2[0]IO[0].I2
CELL.OUT_IO_SN_I2[1]IO[1].I2

Bitstream

xc4000a IO_S1 rect MAIN
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] - - INT: !pass CELL.SINGLE_V[2] ← CELL.TIE_0 INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 6 - INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_C2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 4
B8 - INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] - - - - INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] - - - - - INT: mux CELL.IMUX_CLB_F2 bit 1 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 6
B7 - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[3] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_V[2] INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[4] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: !pass CELL.SINGLE_H[3] ← CELL.LONG_V[3] - - INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[1] INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[3] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H[2] INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 3
B6 - INT: !pass CELL.SINGLE_H_E[0] ← CELL.LONG_V[0] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[0] - - INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] - - INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[3] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_SN_I2[0] - INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_X_S INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 7
B5 INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_IO_H[0] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1 INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[1] INT: mux CELL.LONG_V[0] bit 3 INT: mux CELL.LONG_V[0] bit 0 INT: mux CELL.LONG_V[0] bit 1 INT: mux CELL.LONG_V[0] bit 2 INT: mux CELL.LONG_V[3] bit 3 INT: mux CELL.LONG_V[3] bit 0 INT: mux CELL.LONG_V[3] bit 1 INT: mux CELL.LONG_V[3] bit 2 INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[0] INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[2] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.LONG_V[1] bit 3 INT: mux CELL.LONG_V[1] bit 1 INT: mux CELL.LONG_V[2] bit 1 INT: mux CELL.LONG_V[1] bit 2 INT: mux CELL.LONG_V[2] bit 3 INT: mux CELL.LONG_V[2] bit 0 INT: mux CELL.LONG_V[2] bit 2 DEC[1]: ! O1_P DEC[2]: ! O1_N DEC[0]: ! O1_P DEC[0]: O1_N DEC[2]: O1_P DEC[0]: ! O2_P DEC[2]: ! O2_N DEC[0]: O2_N DEC[2]: O2_P
B4 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I2_E1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.SINGLE_V[2] ← CELL.DEC_H[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[1] INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_V[1] ← CELL.DEC_H[0] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_IO_H[1] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_IO_S0[0] ← CELL.DBUF_IO_H[1] INT: mux CELL.LONG_V[1] bit 0 INT: !pass CELL.DOUBLE_IO_S0[1] ← CELL.DBUF_IO_H[1] IO[0]: ! READBACK_I1 bit 0 INT: mux CELL.DBUF_IO_H[0] bit 1 IO[0]: ! READBACK_I2 bit 0 INT: mux CELL.DBUF_IO_H[0] bit 0 INT: !pass CELL.DOUBLE_IO_S2[1] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_S2[0] ← CELL.DBUF_IO_H[0] INT: mux CELL.DBUF_IO_H[1] bit 1 INT: mux CELL.DBUF_IO_H[1] bit 0 INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S0[1] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S1[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S1[1] DEC[1]: O1_N DEC[1]: ! O2_P INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S1[1] INT: mux CELL.LONG_IO_H[1] bit 4 DEC[1]: O2_N
B3 INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_IO_S0[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S1[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S1[0] INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S1[0] INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S2[1] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S2[1] IO[1]: ! READBACK_I1 bit 0 INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S2[1] INT: !bipass CELL.DOUBLE_IO_S0[1] = CELL.DOUBLE_IO_S2[1] IO[1]: ! READBACK_I2 bit 0 INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S0[1] INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S0[1] INT: mux CELL.LONG_IO_H[1] bit 1 INT: mux CELL.LONG_IO_H[1] bit 0 INT: mux CELL.LONG_IO_H[1] bit 2 INT: mux CELL.LONG_IO_H[1] bit 3 INT: mux CELL.LONG_IO_H[0] bit 0 INT: mux CELL.LONG_IO_H[0] bit 2 INT: mux CELL.LONG_IO_H[0] bit 1 INT: mux CELL.LONG_IO_H[0] bit 3 INT: mux CELL.LONG_IO_H[0] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 7
B2 INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 5 IO[0]: MUX_O bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 7 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 4 IO[1]: MUX_O bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 5 IO[1]: ! READBACK_OQ bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 7
B1 - INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 1 IO[0]: MUX_O bit 0 IO[0]: ! READBACK_OQ bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 7 IO[0]: MUX_I2 bit 0 IO[0]: PULL bit 1 IO[0]: MUX_I2 bit 1 IO[0]: ! IFF_SRVAL bit 0 IO[0]: IFF_D bit 0 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 4 IO[1]: IFF_D bit 0 IO[1]: MUX_I2 bit 1 IO[1]: PULL bit 1 IO[1]: ! OFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 0 IO[1]: MUX_O bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 0
B0 IO[0]: SLEW bit 1 IO[0]: SLEW bit 0 IO[0]: !invert T IO[0]: !invert OK IO[0]: MUX_O bit 2 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_D_INV IO[0]: PULL bit 0 IO[0]: OFF_USED IO[0]: ! OFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 2 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I1 bit 2 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 2 IO[1]: MUX_I2 bit 0 IO[1]: MUX_I2 bit 2 IO[1]: !invert IK IO[1]: ! IFF_SRVAL bit 0 IO[1]: OFF_USED IO[1]: PULL bit 0 IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0 IO[1]: MUX_O bit 2 IO[1]: !invert OK IO[1]: !invert T IO[1]: SLEW bit 0 IO[1]: SLEW bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 2
xc4000a IO_S1 rect MAIN_E
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_S1_W

Cells: 4

Switchbox INT

xc4000a IO_S1_W switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[3]CELL.SINGLE_V[2]!MAIN[18][5]
CELL.LONG_H[4]CELL.SINGLE_V[3]!MAIN[21][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[0]!MAIN[29][6]
CELL.LONG_V[1]CELL.SINGLE_H_E[1]!MAIN[14][7]
CELL.LONG_V[2]CELL.SINGLE_H[2]!MAIN[12][7]
CELL.LONG_V[3]CELL.SINGLE_H[3]!MAIN[13][7]
xc4000a IO_S1_W switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[12][9]
CELL.SINGLE_H[0]CELL.OUT_CLB_X_S!MAIN[11][6]
CELL.SINGLE_H[0]CELL.OUT_IO_SN_I2[1]!MAIN[16][6]
CELL.SINGLE_H[1]CELL.OUT_CLB_XQ_S!MAIN[9][6]
CELL.SINGLE_H[1]CELL.OUT_IO_SN_I2[0]!MAIN[14][6]
CELL.SINGLE_H[2]CELL.LONG_V[2]!MAIN[25][7]
CELL.SINGLE_H[2]CELL.OUT_CLB_X_S!MAIN[13][6]
CELL.SINGLE_H[2]CELL.OUT_IO_SN_I2[1]!MAIN[20][6]
CELL.SINGLE_H[3]CELL.LONG_V[3]!MAIN[17][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_XQ_S!MAIN[10][6]
CELL.SINGLE_H[3]CELL.OUT_IO_SN_I2[0]!MAIN[15][6]
CELL.SINGLE_H_E[0]CELL.LONG_V[0]!MAIN[30][6]
CELL.SINGLE_H_E[1]CELL.LONG_V[1]!MAIN[29][7]
CELL.SINGLE_V[0]CELL.LONG_IO_H[0]!MAIN[31][5]
CELL.SINGLE_V[0]CELL.DEC_H[1]!MAIN[28][5]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I1[0]!MAIN[30][5]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I2_E1!MAIN[29][5]
CELL.SINGLE_V[1]CELL.LONG_IO_H[1]!MAIN[25][4]
CELL.SINGLE_V[1]CELL.DEC_H[0]!MAIN[22][4]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I2[0]!MAIN[23][4]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I1_E1!MAIN[24][4]
CELL.SINGLE_V[2]CELL.TIE_0!MAIN[13][9]
CELL.SINGLE_V[2]CELL.LONG_H[3]!MAIN[30][7]
CELL.SINGLE_V[2]CELL.LONG_IO_H[0]!MAIN[31][4]
CELL.SINGLE_V[2]CELL.DEC_H[1]!MAIN[27][4]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I1[0]!MAIN[30][4]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I2_E1!MAIN[29][4]
CELL.SINGLE_V[3]CELL.LONG_H[4]!MAIN[24][7]
CELL.SINGLE_V[3]CELL.LONG_IO_H[1]!MAIN[20][4]
CELL.SINGLE_V[3]CELL.DEC_H[0]!MAIN[19][5]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I2[0]!MAIN[21][4]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I1_E1!MAIN[17][5]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[8][6]
CELL.DOUBLE_H0[1]CELL.OUT_IO_SN_I2[0]!MAIN[18][6]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[12][6]
CELL.DOUBLE_H1[1]CELL.OUT_IO_SN_I2[1]!MAIN[19][6]
CELL.DOUBLE_V0[0]CELL.OUT_IO_SN_I1_E1!MAIN[28][4]
CELL.DOUBLE_V0[1]CELL.OUT_IO_SN_I2[0]!MAIN[19][4]
CELL.DOUBLE_V1[0]CELL.OUT_IO_SN_I1[0]!MAIN[26][4]
CELL.DOUBLE_V1[1]CELL.OUT_IO_SN_I2_E1!MAIN[16][5]
CELL.DOUBLE_IO_S0[0]CELL.DBUF_IO_H[1]!MAIN[18][4]
CELL.DOUBLE_IO_S0[1]CELL.DBUF_IO_H[1]!MAIN[16][4]
CELL.DOUBLE_IO_S2[0]CELL.DBUF_IO_H[0]!MAIN[10][4]
CELL.DOUBLE_IO_S2[1]CELL.DBUF_IO_H[0]!MAIN[11][4]
xc4000a IO_S1_W switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[28][9]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[27][9]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[26][9]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[17][8]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[17][9]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[16][9]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[26][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[25][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[25][6]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[26][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[26][6]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[30][9]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[29][9]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[19][8]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[18][8]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[29][8]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[28][8]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[28][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[24][6]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[31][9]
CELL.SINGLE_V[0]CELL.DOUBLE_IO_S1[0]!MAIN[19][3]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[20][8]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_S0[0]!MAIN[26][3]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_S2[0]!MAIN[28][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[30][8]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_S1[1]!MAIN[2][4]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[27][7]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_S0[1]!MAIN[11][3]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_S2[1]!MAIN[18][3]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[20][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[21][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[19][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[19][7]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[20][7]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[18][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[23][9]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[24][9]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[22][7]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[23][7]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][9]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S0[1]!MAIN[12][3]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S1[1]!MAIN[5][4]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_S2[1]!MAIN[15][3]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[21][7]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S0[0]!MAIN[24][3]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S1[0]!MAIN[21][3]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_S2[0]!MAIN[27][3]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S0[0]!MAIN[25][3]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S1[0]!MAIN[22][3]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_S2[0]!MAIN[29][3]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S0[1]!MAIN[7][4]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S1[1]!MAIN[6][4]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_S2[1]!MAIN[17][3]
CELL.DOUBLE_IO_S0[0]CELL.DOUBLE_IO_S2[0]!MAIN[23][3]
CELL.DOUBLE_IO_S0[1]CELL.DOUBLE_IO_S2[1]!MAIN[14][3]
xc4000a IO_S1_W switchbox INT muxes DBUF_IO_H[0]
BitsDestination
MAIN[14][4]MAIN[12][4]CELL.DBUF_IO_H[0]
Source
00CELL.DOUBLE_IO_S0[1]
11CELL.DOUBLE_IO_S0[0]
xc4000a IO_S1_W switchbox INT muxes DBUF_IO_H[1]
BitsDestination
MAIN[9][4]MAIN[8][4]CELL.DBUF_IO_H[1]
Source
00CELL.DOUBLE_IO_S2[0]
11CELL.DOUBLE_IO_S2[1]
xc4000a IO_S1_W switchbox INT muxes LONG_V[0]
BitsDestination
MAIN[27][5]MAIN[24][5]MAIN[25][5]MAIN[26][5]CELL.LONG_V[0]
Source
0001CELL.LONG_IO_H[0]
0010CELL.DEC_H[0]
0111CELL.OUT_IO_SN_I2_E1
1111off
xc4000a IO_S1_W switchbox INT muxes LONG_V[1]
BitsDestination
MAIN[15][5]MAIN[12][5]MAIN[14][5]MAIN[17][4]CELL.LONG_V[1]
Source
0001CELL.LONG_IO_H[1]
0010CELL.DEC_H[1]
0111CELL.OUT_IO_SN_I2_E1
1111off
xc4000a IO_S1_W switchbox INT muxes LONG_V[2]
BitsDestination
MAIN[11][5]MAIN[9][5]MAIN[13][5]MAIN[10][5]CELL.LONG_V[2]
Source
0001CELL.LONG_IO_H[0]
0010CELL.DEC_H[0]
0111CELL.OUT_IO_SN_I2[0]
1111off
xc4000a IO_S1_W switchbox INT muxes LONG_V[3]
BitsDestination
MAIN[23][5]MAIN[20][5]MAIN[21][5]MAIN[22][5]CELL.LONG_V[3]
Source
0001CELL.LONG_IO_H[1]
0010CELL.DEC_H[1]
0111CELL.OUT_IO_SN_I2[0]
1111off
xc4000a IO_S1_W switchbox INT muxes LONG_IO_H[0]
BitsDestination
MAIN[2][3]MAIN[3][3]MAIN[5][3]MAIN[4][3]MAIN[6][3]CELL.LONG_IO_H[0]
Source
00011CELL.SINGLE_V[2]
00101CELL.LONG_V[0]
00110CELL.LONG_V[2]
01111CELL.SINGLE_V[0]
11111off
xc4000a IO_S1_W switchbox INT muxes LONG_IO_H[1]
BitsDestination
MAIN[1][4]MAIN[7][3]MAIN[8][3]MAIN[10][3]MAIN[9][3]CELL.LONG_IO_H[1]
Source
00011CELL.SINGLE_V[3]
00101CELL.LONG_V[1]
00110CELL.LONG_V[3]
01111CELL.SINGLE_V[1]
11111off
xc4000a IO_S1_W switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[8][8]MAIN[10][7]MAIN[9][8]MAIN[10][8]MAIN[11][9]MAIN[11][8]MAIN[11][7]CELL.IMUX_CLB_F2
Source
0010011CELL.LONG_H[4]
0010101CELL.LONG_H[3]
0011111CELL.SINGLE_H[0]
0100011CELL_N.LONG_H[0]
0100101CELL_N.LONG_H[2]
0101111CELL.SINGLE_H[1]
0110010CELL.DOUBLE_H0[0]
0110100CELL.DOUBLE_H1[1]
0111110CELL.DOUBLE_H1[0]
1110011CELL.SINGLE_H[2]
1110101CELL.SINGLE_H[3]
1111111CELL.DOUBLE_H0[1]
xc4000a IO_S1_W switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[6][8]MAIN[6][6]MAIN[5][9]MAIN[7][8]MAIN[5][8]MAIN[6][7]MAIN[8][9]CELL.IMUX_CLB_F4
Source
0000111CELL.LONG_H[4]
0001011CELL.LONG_H[3]
0011111CELL.SINGLE_H[0]
0100101CELL.DOUBLE_H0[0]
0100110CELL_N.LONG_H[0]
0101001CELL.DOUBLE_H1[1]
0101010CELL_N.LONG_H[2]
0111101CELL.DOUBLE_H1[0]
0111110CELL.DOUBLE_H0[1]
1100111CELL.SINGLE_H[2]
1101011CELL.SINGLE_H[3]
1111111CELL.SINGLE_H[1]
xc4000a IO_S1_W switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[0][6]MAIN[2][7]MAIN[3][9]MAIN[2][6]MAIN[2][9]MAIN[3][8]MAIN[1][6]MAIN[3][6]CELL.IMUX_CLB_G2
Source
00011111CELL.SPECIAL_CLB_COUT0
00100111CELL.SINGLE_H[1]
00101011CELL_N.LONG_H[2]
00101110CELL.LONG_H[3]
00110101CELL.DOUBLE_H0[1]
00111001CELL_N.LONG_H[0]
00111100CELL.LONG_H[4]
01101111CELL.SINGLE_H[0]
01111101CELL.DOUBLE_H1[0]
10110111CELL.SINGLE_H[2]
10111011CELL.SINGLE_H[3]
10111110CELL.DOUBLE_H1[1]
11111111CELL.DOUBLE_H0[0]
xc4000a IO_S1_W switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[4][7]MAIN[5][6]MAIN[3][7]MAIN[4][8]MAIN[4][9]MAIN[4][6]MAIN[5][7]CELL.IMUX_CLB_G4
Source
0000111CELL.SINGLE_H[1]
0001011CELL_N.LONG_H[2]
0001101CELL.LONG_H[3]
0011111CELL.SINGLE_H[0]
0100110CELL.DOUBLE_H0[1]
0101010CELL_N.LONG_H[0]
0101100CELL.LONG_H[4]
0111110CELL.DOUBLE_H1[0]
1100111CELL.SINGLE_H[2]
1101011CELL.SINGLE_H[3]
1101101CELL.DOUBLE_H0[0]
1111111CELL.DOUBLE_H1[1]
xc4000a IO_S1_W switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[0][8]MAIN[2][8]MAIN[0][9]MAIN[0][7]MAIN[1][9]MAIN[1][8]MAIN[1][7]CELL.IMUX_CLB_C2
Source
0000111CELL.SINGLE_H[0]
0001011CELL_N.LONG_H[2]
0001110CELL.LONG_H[3]
0011111CELL.SINGLE_H[1]
0100101CELL.DOUBLE_H1[0]
0101001CELL_N.LONG_H[0]
0101100CELL.LONG_H[4]
0111101CELL.DOUBLE_H0[1]
1100111CELL.DOUBLE_H0[0]
1101011CELL.SINGLE_H[3]
1101110CELL.DOUBLE_H1[1]
1111111CELL.SINGLE_H[2]
xc4000a IO_S1_W switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[7][9]MAIN[9][7]MAIN[10][9]MAIN[7][7]MAIN[9][9]MAIN[7][6]MAIN[8][7]CELL.IMUX_CLB_C4
Source
0010101CELL.LONG_H[4]
0010110CELL.LONG_H[3]
0011111CELL.SINGLE_H[0]
0100101CELL_N.LONG_H[0]
0100110CELL_N.LONG_H[2]
0101111CELL.SINGLE_H[1]
0110001CELL.SINGLE_H[2]
0110010CELL.SINGLE_H[3]
0111011CELL.DOUBLE_H0[1]
1110101CELL.DOUBLE_H0[0]
1110110CELL.DOUBLE_H1[1]
1111111CELL.DOUBLE_H1[0]
xc4000a IO_S1_W switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[21][2]MAIN[19][2]MAIN[20][3]MAIN[20][2]MAIN[22][2]CELL.IMUX_IO_O1[0]
Source
00011CELL.DOUBLE_V0[0]
00101CELL.LONG_V[2]
01111CELL.DOUBLE_V1[1]
10011CELL.DEC_H[0]
10101CELL.DEC_H[1]
10110CELL.LONG_V[3]
11111CELL.TIE_0
xc4000a IO_S1_W switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[7][2]MAIN[10][2]MAIN[9][2]MAIN[8][2]MAIN[9][1]CELL.IMUX_IO_O1[1]
Source
00011CELL.DEC_H[0]
00101CELL.DEC_H[1]
01011CELL_E.LONG_V[0]
01101CELL_E.DOUBLE_V0[1]
01110CELL_E.LONG_V[1]
10111CELL_E.DOUBLE_V1[0]
11111CELL.TIE_0
xc4000a IO_S1_W switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[23][2]MAIN[31][2]MAIN[31][3]MAIN[26][2]MAIN[29][2]MAIN[28][2]MAIN[27][2]MAIN[30][2]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[2]
01101111CELL.SINGLE_V[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[1]
xc4000a IO_S1_W switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[0][3]MAIN[5][1]MAIN[1][1]MAIN[2][1]MAIN[4][1]MAIN[0][0]MAIN[1][3]MAIN[0][1]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_E.SINGLE_V[1]
01111101CELL_E.SINGLE_V[2]
01111110CELL_E.SINGLE_V[3]
11111111CELL_E.SINGLE_V[0]
xc4000a IO_S1_W switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[23][1]MAIN[30][1]MAIN[25][2]MAIN[30][3]MAIN[28][1]MAIN[27][1]MAIN[26][1]MAIN[29][1]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[1]
01101111CELL.SINGLE_V[2]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[3]
xc4000a IO_S1_W switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[0][2]MAIN[6][1]MAIN[5][2]MAIN[3][1]MAIN[7][1]MAIN[1][2]MAIN[2][2]MAIN[3][2]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_E.SINGLE_V[0]
01111101CELL_E.SINGLE_V[1]
01111110CELL_E.SINGLE_V[3]
11111111CELL_E.SINGLE_V[2]
xc4000a IO_S1_W switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[14][2]MAIN[17][1]MAIN[15][2]MAIN[18][2]MAIN[17][2]MAIN[16][2]CELL.IMUX_IO_T[0]
Source
001111CELL.TIE_0
010011CELL.DOUBLE_IO_S0[1]
010111CELL.DOUBLE_IO_S0[0]
011001CELL.DEC_H[0]
011010CELL.LONG_IO_H[1]
011101CELL.LONG_IO_H[0]
011110CELL.GCLK[0]
111011CELL.DOUBLE_IO_S1[0]
111111CELL.DOUBLE_IO_S1[1]
xc4000a IO_S1_W switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[12][2]MAIN[14][1]MAIN[11][2]MAIN[13][2]MAIN[16][1]MAIN[15][1]CELL.IMUX_IO_T[1]
Source
001111CELL.TIE_0
010011CELL.DOUBLE_IO_S1[1]
010101CELL.LONG_IO_H[0]
010110CELL.GCLK[0]
011011CELL.DOUBLE_IO_S1[0]
011101CELL.LONG_IO_H[1]
011110CELL.DEC_H[0]
110111CELL.DOUBLE_IO_S0[0]
111111CELL.DOUBLE_IO_S0[1]

Bels IO

xc4000a IO_S1_W bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[21][0]CELL.IMUX_IO_IK[1] invert by !MAIN[11][0]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[28][0]CELL.IMUX_IO_OK[1] invert by !MAIN[4][0]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_F4CELL.IMUX_CLB_G4
TinCELL.IMUX_IO_T[0] invert by !MAIN[29][0]CELL.IMUX_IO_T[1] invert by !MAIN[3][0]
I1outCELL.OUT_IO_SN_I1[0]CELL.OUT_IO_SN_I1[1]
I2outCELL.OUT_IO_SN_I2[0]CELL.OUT_IO_SN_I2[1]
CLKINoutCELL.OUT_IO_CLKIN-
xc4000a IO_S1_W bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[19][1]!MAIN[10][0]
OFF_SRVAL bit 0!MAIN[22][0]!MAIN[10][1]
READBACK_I1 bit 0!MAIN[15][4]!MAIN[16][3]
READBACK_I2 bit 0!MAIN[13][4]!MAIN[13][3]
READBACK_OQ bit 0!MAIN[24][1]!MAIN[4][2]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[25][0]!MAIN[7][0]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[23][0]MAIN[9][0]
xc4000a IO_S1_W enum IO_SLEW
IO[0].SLEWMAIN[31][0]MAIN[30][0]
IO[1].SLEWMAIN[1][0]MAIN[2][0]
FAST00
MEDFAST01
MEDSLOW10
SLOW11
xc4000a IO_S1_W enum IO_PULL
IO[0].PULLMAIN[21][1]MAIN[24][0]
IO[1].PULLMAIN[11][1]MAIN[8][0]
NONE11
PULLUP01
PULLDOWN10
xc4000a IO_S1_W enum IO_MUX_I
IO[0].MUX_I1MAIN[17][0]MAIN[19][0]MAIN[18][0]
IO[1].MUX_I1MAIN[14][0]MAIN[16][0]MAIN[15][0]
IO[0].MUX_I2MAIN[20][0]MAIN[20][1]MAIN[22][1]
IO[1].MUX_I2MAIN[12][0]MAIN[12][1]MAIN[13][0]
I001
IQ111
IQL010
xc4000a IO_S1_W enum IO_IFF_D
IO[0].IFF_DMAIN[18][1]
IO[1].IFF_DMAIN[13][1]
I1
DELAY0
xc4000a IO_S1_W enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[26][0]
IO[1].MUX_OFF_DMAIN[6][0]
O11
O20
xc4000a IO_S1_W enum IO_MUX_O
IO[0].MUX_OMAIN[27][0]MAIN[24][2]MAIN[25][1]
IO[1].MUX_OMAIN[5][0]MAIN[6][2]MAIN[8][1]
O1001
O1_INV010
O2100
O2_INV011
OQ000

Bels DEC

xc4000a IO_S1_W bel DEC pins
PinDirectionDEC[0]DEC[1]DEC[2]
IinCELL.OUT_IO_SN_I1[0]CELL.IMUX_CLB_C4CELL.OUT_IO_SN_I1[1]
O1bidirCELL.DEC_H[0]CELL.DEC_H[0]CELL.DEC_H[0]
O2bidirCELL.DEC_H[1]CELL.DEC_H[1]CELL.DEC_H[1]
xc4000a IO_S1_W bel DEC attribute bits
AttributeDEC[0]DEC[1]DEC[2]
O1_P!MAIN[6][5]!MAIN[8][5]MAIN[4][5]
O1_NMAIN[5][5]MAIN[4][4]!MAIN[7][5]
O2_P!MAIN[3][5]!MAIN[3][4]MAIN[0][5]
O2_NMAIN[1][5]MAIN[0][4]!MAIN[2][5]

Bel wires

xc4000a IO_S1_W bel wires
WirePins
CELL.DEC_H[0]DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_H[1]DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.IMUX_CLB_F4IO[0].O2
CELL.IMUX_CLB_G4IO[1].O2
CELL.IMUX_CLB_C4DEC[1].I
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_SN_I1[0]IO[0].I1, DEC[0].I
CELL.OUT_IO_SN_I1[1]IO[1].I1, DEC[2].I
CELL.OUT_IO_SN_I2[0]IO[0].I2
CELL.OUT_IO_SN_I2[1]IO[1].I2
CELL.OUT_IO_CLKINIO[0].CLKIN

Bitstream

xc4000a IO_S1_W rect MAIN
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] - - INT: !pass CELL.SINGLE_V[2] ← CELL.TIE_0 INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 6 - INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_C2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 4
B8 - INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] - - - - INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] - - - - - INT: mux CELL.IMUX_CLB_F2 bit 1 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 6
B7 - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[3] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_V[2] INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[4] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: !pass CELL.SINGLE_H[3] ← CELL.LONG_V[3] - - INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[1] INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[3] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H[2] INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 3
B6 - INT: !pass CELL.SINGLE_H_E[0] ← CELL.LONG_V[0] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[0] - - INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] - - INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[3] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_SN_I2[0] - INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_SN_I2[1] INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_X_S INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 7
B5 INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_IO_H[0] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1 INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[1] INT: mux CELL.LONG_V[0] bit 3 INT: mux CELL.LONG_V[0] bit 0 INT: mux CELL.LONG_V[0] bit 1 INT: mux CELL.LONG_V[0] bit 2 INT: mux CELL.LONG_V[3] bit 3 INT: mux CELL.LONG_V[3] bit 0 INT: mux CELL.LONG_V[3] bit 1 INT: mux CELL.LONG_V[3] bit 2 INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[0] INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[2] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.LONG_V[1] bit 3 INT: mux CELL.LONG_V[1] bit 1 INT: mux CELL.LONG_V[2] bit 1 INT: mux CELL.LONG_V[1] bit 2 INT: mux CELL.LONG_V[2] bit 3 INT: mux CELL.LONG_V[2] bit 0 INT: mux CELL.LONG_V[2] bit 2 DEC[1]: ! O1_P DEC[2]: ! O1_N DEC[0]: ! O1_P DEC[0]: O1_N DEC[2]: O1_P DEC[0]: ! O2_P DEC[2]: ! O2_N DEC[0]: O2_N DEC[2]: O2_P
B4 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I2_E1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.SINGLE_V[2] ← CELL.DEC_H[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[1] INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_V[1] ← CELL.DEC_H[0] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_IO_H[1] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_IO_S0[0] ← CELL.DBUF_IO_H[1] INT: mux CELL.LONG_V[1] bit 0 INT: !pass CELL.DOUBLE_IO_S0[1] ← CELL.DBUF_IO_H[1] IO[0]: ! READBACK_I1 bit 0 INT: mux CELL.DBUF_IO_H[0] bit 1 IO[0]: ! READBACK_I2 bit 0 INT: mux CELL.DBUF_IO_H[0] bit 0 INT: !pass CELL.DOUBLE_IO_S2[1] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_S2[0] ← CELL.DBUF_IO_H[0] INT: mux CELL.DBUF_IO_H[1] bit 1 INT: mux CELL.DBUF_IO_H[1] bit 0 INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S0[1] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S1[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S1[1] DEC[1]: O1_N DEC[1]: ! O2_P INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S1[1] INT: mux CELL.LONG_IO_H[1] bit 4 DEC[1]: O2_N
B3 INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S0[0] INT: !bipass CELL.DOUBLE_IO_S0[0] = CELL.DOUBLE_IO_S2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S1[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S1[0] INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S1[0] INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S2[1] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S2[1] IO[1]: ! READBACK_I1 bit 0 INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S2[1] INT: !bipass CELL.DOUBLE_IO_S0[1] = CELL.DOUBLE_IO_S2[1] IO[1]: ! READBACK_I2 bit 0 INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S0[1] INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S0[1] INT: mux CELL.LONG_IO_H[1] bit 1 INT: mux CELL.LONG_IO_H[1] bit 0 INT: mux CELL.LONG_IO_H[1] bit 2 INT: mux CELL.LONG_IO_H[1] bit 3 INT: mux CELL.LONG_IO_H[0] bit 0 INT: mux CELL.LONG_IO_H[0] bit 2 INT: mux CELL.LONG_IO_H[0] bit 1 INT: mux CELL.LONG_IO_H[0] bit 3 INT: mux CELL.LONG_IO_H[0] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 7
B2 INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 5 IO[0]: MUX_O bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 7 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_T[1] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 4 IO[1]: MUX_O bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 5 IO[1]: ! READBACK_OQ bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 7
B1 - INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 1 IO[0]: MUX_O bit 0 IO[0]: ! READBACK_OQ bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 7 IO[0]: MUX_I2 bit 0 IO[0]: PULL bit 1 IO[0]: MUX_I2 bit 1 IO[0]: ! IFF_SRVAL bit 0 IO[0]: IFF_D bit 0 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 4 IO[1]: IFF_D bit 0 IO[1]: MUX_I2 bit 1 IO[1]: PULL bit 1 IO[1]: ! OFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 0 IO[1]: MUX_O bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 0
B0 IO[0]: SLEW bit 1 IO[0]: SLEW bit 0 IO[0]: !invert T IO[0]: !invert OK IO[0]: MUX_O bit 2 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_D_INV IO[0]: PULL bit 0 IO[0]: OFF_USED IO[0]: ! OFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 2 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I1 bit 2 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 2 IO[1]: MUX_I2 bit 0 IO[1]: MUX_I2 bit 2 IO[1]: !invert IK IO[1]: ! IFF_SRVAL bit 0 IO[1]: OFF_USED IO[1]: PULL bit 0 IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0 IO[1]: MUX_O bit 2 IO[1]: !invert OK IO[1]: !invert T IO[1]: SLEW bit 0 IO[1]: SLEW bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 2
xc4000a IO_S1_W rect MAIN_E
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_N0

Cells: 3

Switchbox INT

xc4000a IO_N0 switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[0]!MAIN_S[29][9]
CELL.LONG_H[2]CELL.SINGLE_V[1]!MAIN[18][0]
xc4000a IO_N0 switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_V[0]CELL.LONG_H[0]!MAIN_S[30][9]
CELL.SINGLE_V[0]CELL.LONG_IO_H[0]!MAIN[31][0]
CELL.SINGLE_V[0]CELL.DEC_H[0]!MAIN[28][0]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I1[0]!MAIN[30][0]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I2_E1!MAIN[29][0]
CELL.SINGLE_V[1]CELL.LONG_H[2]!MAIN_S[21][9]
CELL.SINGLE_V[1]CELL.LONG_IO_H[1]!MAIN[25][1]
CELL.SINGLE_V[1]CELL.DEC_H[1]!MAIN[22][1]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I2[0]!MAIN[23][1]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I1_E1!MAIN[24][1]
CELL.SINGLE_V[2]CELL.LONG_IO_H[0]!MAIN[31][1]
CELL.SINGLE_V[2]CELL.DEC_H[0]!MAIN[27][1]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I1[0]!MAIN[30][1]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I2_E1!MAIN[29][1]
CELL.SINGLE_V[3]CELL.LONG_IO_H[1]!MAIN[20][1]
CELL.SINGLE_V[3]CELL.DEC_H[1]!MAIN[19][0]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I2[0]!MAIN[21][1]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I1_E1!MAIN[17][0]
CELL.DOUBLE_V0[0]CELL.OUT_IO_SN_I1_E1!MAIN[28][1]
CELL.DOUBLE_V0[1]CELL.OUT_IO_SN_I2[0]!MAIN[19][1]
CELL.DOUBLE_V1[0]CELL.OUT_IO_SN_I1[0]!MAIN[26][1]
CELL.DOUBLE_V1[1]CELL.OUT_IO_SN_I2_E1!MAIN[16][0]
CELL.DOUBLE_IO_N0[0]CELL.DBUF_IO_H[0]!MAIN[10][1]
CELL.DOUBLE_IO_N0[1]CELL.DBUF_IO_H[0]!MAIN[11][1]
CELL.DOUBLE_IO_N2[0]CELL.DBUF_IO_H[1]!MAIN[18][1]
CELL.DOUBLE_IO_N2[1]CELL.DBUF_IO_H[1]!MAIN[16][1]
xc4000a IO_N0 switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_V[0]CELL.DOUBLE_IO_N0[0]!MAIN[28][2]
CELL.SINGLE_V[0]CELL.DOUBLE_IO_N2[0]!MAIN[26][2]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_N1[0]!MAIN[19][2]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_N0[1]!MAIN[18][2]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_N2[1]!MAIN[11][2]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_N1[1]!MAIN[2][1]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N0[1]!MAIN[15][2]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N1[1]!MAIN[5][1]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N2[1]!MAIN[12][2]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N0[0]!MAIN[27][2]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N1[0]!MAIN[21][2]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N2[0]!MAIN[24][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N0[0]!MAIN[29][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N1[0]!MAIN[22][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N2[0]!MAIN[25][2]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N0[1]!MAIN[17][2]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N1[1]!MAIN[6][1]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N2[1]!MAIN[7][1]
CELL.DOUBLE_IO_N0[0]CELL.DOUBLE_IO_N2[0]!MAIN[23][2]
CELL.DOUBLE_IO_N0[1]CELL.DOUBLE_IO_N2[1]!MAIN[14][2]
xc4000a IO_N0 switchbox INT muxes DBUF_IO_H[0]
BitsDestination
MAIN[14][1]MAIN[12][1]CELL.DBUF_IO_H[0]
Source
00CELL.DOUBLE_IO_N2[1]
11CELL.DOUBLE_IO_N2[0]
xc4000a IO_N0 switchbox INT muxes DBUF_IO_H[1]
BitsDestination
MAIN[9][1]MAIN[8][1]CELL.DBUF_IO_H[1]
Source
00CELL.DOUBLE_IO_N0[0]
11CELL.DOUBLE_IO_N0[1]
xc4000a IO_N0 switchbox INT muxes LONG_V[0]
BitsDestination
MAIN[27][0]MAIN[24][0]MAIN[25][0]MAIN[26][0]CELL.LONG_V[0]
Source
0001CELL.LONG_IO_H[0]
0010CELL.DEC_H[1]
0111CELL.OUT_IO_SN_I2_E1
1111off
xc4000a IO_N0 switchbox INT muxes LONG_V[1]
BitsDestination
MAIN[15][0]MAIN[12][0]MAIN[14][0]MAIN[17][1]CELL.LONG_V[1]
Source
0001CELL.LONG_IO_H[1]
0010CELL.DEC_H[0]
0111CELL.OUT_IO_SN_I2_E1
1111off
xc4000a IO_N0 switchbox INT muxes LONG_V[2]
BitsDestination
MAIN[11][0]MAIN[9][0]MAIN[13][0]MAIN[10][0]CELL.LONG_V[2]
Source
0001CELL.LONG_IO_H[0]
0010CELL.DEC_H[1]
0111CELL.OUT_IO_SN_I2[0]
1111off
xc4000a IO_N0 switchbox INT muxes LONG_V[3]
BitsDestination
MAIN[23][0]MAIN[20][0]MAIN[21][0]MAIN[22][0]CELL.LONG_V[3]
Source
0001CELL.LONG_IO_H[1]
0010CELL.DEC_H[0]
0111CELL.OUT_IO_SN_I2[0]
1111off
xc4000a IO_N0 switchbox INT muxes LONG_IO_H[0]
BitsDestination
MAIN[2][2]MAIN[3][2]MAIN[5][2]MAIN[4][2]MAIN[6][2]CELL.LONG_IO_H[0]
Source
00011CELL.SINGLE_V[2]
00101CELL.LONG_V[0]
00110CELL.LONG_V[2]
01111CELL.SINGLE_V[0]
11111off
xc4000a IO_N0 switchbox INT muxes LONG_IO_H[1]
BitsDestination
MAIN[1][1]MAIN[7][2]MAIN[8][2]MAIN[10][2]MAIN[9][2]CELL.LONG_IO_H[1]
Source
00011CELL.SINGLE_V[3]
00101CELL.LONG_V[1]
00110CELL.LONG_V[3]
01111CELL.SINGLE_V[1]
11111off
xc4000a IO_N0 switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[21][3]MAIN[19][3]MAIN[20][2]MAIN[20][3]MAIN[22][3]CELL.IMUX_IO_O1[0]
Source
00011CELL.DOUBLE_V0[0]
00101CELL.LONG_V[2]
01111CELL.DOUBLE_V1[1]
10011CELL.DEC_H[1]
10101CELL.DEC_H[0]
10110CELL.LONG_V[3]
11111CELL.TIE_0
xc4000a IO_N0 switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[7][3]MAIN[10][3]MAIN[8][3]MAIN[9][3]MAIN[9][4]CELL.IMUX_IO_O1[1]
Source
00011CELL.DEC_H[0]
00101CELL.DEC_H[1]
01011CELL_E.DOUBLE_V0[1]
01101CELL_E.LONG_V[0]
01110CELL_E.LONG_V[1]
10111CELL_E.DOUBLE_V1[0]
11111CELL.TIE_0
xc4000a IO_N0 switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[23][3]MAIN[31][3]MAIN[31][2]MAIN[26][3]MAIN[29][3]MAIN[28][3]MAIN[27][3]MAIN[30][3]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[2]
01101111CELL.SINGLE_V[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[1]
xc4000a IO_N0 switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[0][2]MAIN[5][4]MAIN[1][4]MAIN[2][4]MAIN[4][4]MAIN[0][5]MAIN[1][2]MAIN[0][4]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_E.SINGLE_V[1]
01111101CELL_E.SINGLE_V[2]
01111110CELL_E.SINGLE_V[3]
11111111CELL_E.SINGLE_V[0]
xc4000a IO_N0 switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[23][4]MAIN[30][4]MAIN[25][3]MAIN[30][2]MAIN[28][4]MAIN[27][4]MAIN[26][4]MAIN[29][4]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[1]
01101111CELL.SINGLE_V[2]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[3]
xc4000a IO_N0 switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[0][3]MAIN[6][4]MAIN[5][3]MAIN[3][4]MAIN[7][4]MAIN[1][3]MAIN[2][3]MAIN[3][3]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_E.SINGLE_V[0]
01111101CELL_E.SINGLE_V[1]
01111110CELL_E.SINGLE_V[3]
11111111CELL_E.SINGLE_V[2]
xc4000a IO_N0 switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[14][3]MAIN[17][4]MAIN[18][3]MAIN[15][3]MAIN[17][3]MAIN[16][3]CELL.IMUX_IO_T[0]
Source
001111CELL.TIE_0
010011CELL.DOUBLE_IO_N2[1]
010101CELL.DEC_H[1]
010110CELL.LONG_IO_H[1]
011011CELL.DOUBLE_IO_N2[0]
011101CELL.LONG_IO_H[0]
011110CELL.GCLK[0]
110111CELL.DOUBLE_IO_N1[0]
111111CELL.DOUBLE_IO_N1[1]
xc4000a IO_N0 switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[12][3]MAIN[14][4]MAIN[13][3]MAIN[11][3]MAIN[16][4]MAIN[15][4]CELL.IMUX_IO_T[1]
Source
001111CELL.TIE_0
010011CELL.DOUBLE_IO_N1[1]
010111CELL.DOUBLE_IO_N1[0]
011001CELL.LONG_IO_H[0]
011010CELL.GCLK[0]
011101CELL.LONG_IO_H[1]
011110CELL.DEC_H[1]
111011CELL.DOUBLE_IO_N2[0]
111111CELL.DOUBLE_IO_N2[1]

Bels IO

xc4000a IO_N0 bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[21][5]CELL.IMUX_IO_IK[1] invert by !MAIN[11][5]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[28][5]CELL.IMUX_IO_OK[1] invert by !MAIN[4][5]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_F2_NCELL.IMUX_CLB_G2_N
TinCELL.IMUX_IO_T[0] invert by !MAIN[29][5]CELL.IMUX_IO_T[1] invert by !MAIN[3][5]
I1outCELL.OUT_IO_SN_I1[0]CELL.OUT_IO_SN_I1[1]
I2outCELL.OUT_IO_SN_I2[0]CELL.OUT_IO_SN_I2[1]
xc4000a IO_N0 bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[19][4]!MAIN[10][5]
OFF_SRVAL bit 0!MAIN[22][5]!MAIN[10][4]
READBACK_I1 bit 0!MAIN[15][1]!MAIN[16][2]
READBACK_I2 bit 0!MAIN[13][1]!MAIN[13][2]
READBACK_OQ bit 0!MAIN[24][4]!MAIN[4][3]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[25][5]!MAIN[7][5]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[23][5]MAIN[9][5]
xc4000a IO_N0 enum IO_SLEW
IO[0].SLEWMAIN[31][5]MAIN[30][5]
IO[1].SLEWMAIN[1][5]MAIN[2][5]
FAST00
MEDFAST01
MEDSLOW10
SLOW11
xc4000a IO_N0 enum IO_PULL
IO[0].PULLMAIN[21][4]MAIN[24][5]
IO[1].PULLMAIN[11][4]MAIN[8][5]
NONE11
PULLUP01
PULLDOWN10
xc4000a IO_N0 enum IO_MUX_I
IO[0].MUX_I1MAIN[17][5]MAIN[19][5]MAIN[18][5]
IO[1].MUX_I1MAIN[14][5]MAIN[16][5]MAIN[15][5]
IO[0].MUX_I2MAIN[20][5]MAIN[20][4]MAIN[22][4]
IO[1].MUX_I2MAIN[12][5]MAIN[12][4]MAIN[13][5]
I001
IQ111
IQL010
xc4000a IO_N0 enum IO_IFF_D
IO[0].IFF_DMAIN[18][4]
IO[1].IFF_DMAIN[13][4]
I1
DELAY0
xc4000a IO_N0 enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[26][5]
IO[1].MUX_OFF_DMAIN[6][5]
O11
O20
xc4000a IO_N0 enum IO_MUX_O
IO[0].MUX_OMAIN[27][5]MAIN[24][3]MAIN[25][4]
IO[1].MUX_OMAIN[5][5]MAIN[6][3]MAIN[8][4]
O1001
O1_INV010
O2100
O2_INV011
OQ000

Bels DEC

xc4000a IO_N0 bel DEC pins
PinDirectionDEC[0]DEC[1]DEC[2]
IinCELL.OUT_IO_SN_I1[0]CELL.IMUX_CLB_C2_NCELL.OUT_IO_SN_I1[1]
O1bidirCELL.DEC_H[0]CELL.DEC_H[0]CELL.DEC_H[0]
O2bidirCELL.DEC_H[1]CELL.DEC_H[1]CELL.DEC_H[1]
xc4000a IO_N0 bel DEC attribute bits
AttributeDEC[0]DEC[1]DEC[2]
O1_P!MAIN[3][0]!MAIN[3][1]MAIN[0][0]
O1_NMAIN[1][0]MAIN[0][1]!MAIN[2][0]
O2_P!MAIN[6][0]!MAIN[8][0]MAIN[4][0]
O2_NMAIN[5][0]MAIN[4][1]!MAIN[7][0]

Bel wires

xc4000a IO_N0 bel wires
WirePins
CELL.DEC_H[0]DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_H[1]DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.IMUX_CLB_F2_NIO[0].O2
CELL.IMUX_CLB_G2_NIO[1].O2
CELL.IMUX_CLB_C2_NDEC[1].I
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_SN_I1[0]IO[0].I1, DEC[0].I
CELL.OUT_IO_SN_I1[1]IO[1].I1, DEC[2].I
CELL.OUT_IO_SN_I2[0]IO[0].I2
CELL.OUT_IO_SN_I2[1]IO[1].I2

Bitstream

xc4000a IO_N0 rect MAIN
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B5 IO[0]: SLEW bit 1 IO[0]: SLEW bit 0 IO[0]: !invert T IO[0]: !invert OK IO[0]: MUX_O bit 2 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_D_INV IO[0]: PULL bit 0 IO[0]: OFF_USED IO[0]: ! OFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 2 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I1 bit 2 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 2 IO[1]: MUX_I2 bit 0 IO[1]: MUX_I2 bit 2 IO[1]: !invert IK IO[1]: ! IFF_SRVAL bit 0 IO[1]: OFF_USED IO[1]: PULL bit 0 IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0 IO[1]: MUX_O bit 2 IO[1]: !invert OK IO[1]: !invert T IO[1]: SLEW bit 0 IO[1]: SLEW bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 2
B4 - INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 1 IO[0]: MUX_O bit 0 IO[0]: ! READBACK_OQ bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 7 IO[0]: MUX_I2 bit 0 IO[0]: PULL bit 1 IO[0]: MUX_I2 bit 1 IO[0]: ! IFF_SRVAL bit 0 IO[0]: IFF_D bit 0 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 4 IO[1]: IFF_D bit 0 IO[1]: MUX_I2 bit 1 IO[1]: PULL bit 1 IO[1]: ! OFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 0 IO[1]: MUX_O bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 0
B3 INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 5 IO[0]: MUX_O bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 7 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 4 IO[1]: MUX_O bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 5 IO[1]: ! READBACK_OQ bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 7
B2 INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_IO_N0[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N1[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N1[0] INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N1[0] INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N0[1] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N0[1] IO[1]: ! READBACK_I1 bit 0 INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N0[1] INT: !bipass CELL.DOUBLE_IO_N0[1] = CELL.DOUBLE_IO_N2[1] IO[1]: ! READBACK_I2 bit 0 INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N2[1] INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N2[1] INT: mux CELL.LONG_IO_H[1] bit 1 INT: mux CELL.LONG_IO_H[1] bit 0 INT: mux CELL.LONG_IO_H[1] bit 2 INT: mux CELL.LONG_IO_H[1] bit 3 INT: mux CELL.LONG_IO_H[0] bit 0 INT: mux CELL.LONG_IO_H[0] bit 2 INT: mux CELL.LONG_IO_H[0] bit 1 INT: mux CELL.LONG_IO_H[0] bit 3 INT: mux CELL.LONG_IO_H[0] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 7
B1 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I2_E1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.SINGLE_V[2] ← CELL.DEC_H[0] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[1] INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_V[1] ← CELL.DEC_H[1] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_IO_H[1] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_IO_N2[0] ← CELL.DBUF_IO_H[1] INT: mux CELL.LONG_V[1] bit 0 INT: !pass CELL.DOUBLE_IO_N2[1] ← CELL.DBUF_IO_H[1] IO[0]: ! READBACK_I1 bit 0 INT: mux CELL.DBUF_IO_H[0] bit 1 IO[0]: ! READBACK_I2 bit 0 INT: mux CELL.DBUF_IO_H[0] bit 0 INT: !pass CELL.DOUBLE_IO_N0[1] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_N0[0] ← CELL.DBUF_IO_H[0] INT: mux CELL.DBUF_IO_H[1] bit 1 INT: mux CELL.DBUF_IO_H[1] bit 0 INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N2[1] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N1[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N1[1] DEC[1]: O2_N DEC[1]: ! O1_P INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N1[1] INT: mux CELL.LONG_IO_H[1] bit 4 DEC[1]: O1_N
B0 INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_IO_H[0] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1 INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[0] INT: mux CELL.LONG_V[0] bit 3 INT: mux CELL.LONG_V[0] bit 0 INT: mux CELL.LONG_V[0] bit 1 INT: mux CELL.LONG_V[0] bit 2 INT: mux CELL.LONG_V[3] bit 3 INT: mux CELL.LONG_V[3] bit 0 INT: mux CELL.LONG_V[3] bit 1 INT: mux CELL.LONG_V[3] bit 2 INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[1] INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[1] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.LONG_V[1] bit 3 INT: mux CELL.LONG_V[1] bit 1 INT: mux CELL.LONG_V[2] bit 1 INT: mux CELL.LONG_V[1] bit 2 INT: mux CELL.LONG_V[2] bit 3 INT: mux CELL.LONG_V[2] bit 0 INT: mux CELL.LONG_V[2] bit 2 DEC[1]: ! O2_P DEC[2]: ! O2_N DEC[0]: ! O2_P DEC[0]: O2_N DEC[2]: O2_P DEC[0]: ! O1_P DEC[2]: ! O1_N DEC[0]: O1_N DEC[2]: O1_P
xc4000a IO_N0 rect MAIN_S
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_H[0] INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[0] - - - - - - - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000a IO_N0 rect MAIN_E
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000a IO_N0 rect MAIN_W
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_N0_E

Cells: 3

Switchbox INT

xc4000a IO_N0_E switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[0]!MAIN_S[29][9]
CELL.LONG_H[2]CELL.SINGLE_V[1]!MAIN[18][0]
xc4000a IO_N0_E switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_V[0]CELL.LONG_H[0]!MAIN_S[30][9]
CELL.SINGLE_V[0]CELL.LONG_IO_H[0]!MAIN[31][0]
CELL.SINGLE_V[0]CELL.DEC_H[0]!MAIN[28][0]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I1[0]!MAIN[30][0]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I2_E1!MAIN[29][0]
CELL.SINGLE_V[1]CELL.LONG_H[2]!MAIN_S[21][9]
CELL.SINGLE_V[1]CELL.LONG_IO_H[1]!MAIN[25][1]
CELL.SINGLE_V[1]CELL.DEC_H[1]!MAIN[22][1]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I2[0]!MAIN[23][1]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I1_E1!MAIN[24][1]
CELL.SINGLE_V[2]CELL.LONG_IO_H[0]!MAIN[31][1]
CELL.SINGLE_V[2]CELL.DEC_H[0]!MAIN[27][1]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I1[0]!MAIN[30][1]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I2_E1!MAIN[29][1]
CELL.SINGLE_V[3]CELL.LONG_IO_H[1]!MAIN[20][1]
CELL.SINGLE_V[3]CELL.DEC_H[1]!MAIN[19][0]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I2[0]!MAIN[21][1]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I1_E1!MAIN[17][0]
CELL.DOUBLE_V0[0]CELL.OUT_IO_SN_I1_E1!MAIN[28][1]
CELL.DOUBLE_V0[1]CELL.OUT_IO_SN_I2[0]!MAIN[19][1]
CELL.DOUBLE_V1[0]CELL.OUT_IO_SN_I1[0]!MAIN[26][1]
CELL.DOUBLE_V1[1]CELL.OUT_IO_SN_I2_E1!MAIN[16][0]
CELL.DOUBLE_IO_N0[0]CELL.DBUF_IO_H[0]!MAIN[10][1]
CELL.DOUBLE_IO_N0[1]CELL.DBUF_IO_H[0]!MAIN[11][1]
CELL.DOUBLE_IO_N2[0]CELL.DBUF_IO_H[1]!MAIN[18][1]
CELL.DOUBLE_IO_N2[1]CELL.DBUF_IO_H[1]!MAIN[16][1]
xc4000a IO_N0_E switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_V[0]CELL.DOUBLE_IO_N0[0]!MAIN[28][2]
CELL.SINGLE_V[0]CELL.DOUBLE_IO_N2[0]!MAIN[26][2]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_N1[0]!MAIN[19][2]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_N0[1]!MAIN[18][2]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_N2[1]!MAIN[11][2]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_N1[1]!MAIN[2][1]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N0[1]!MAIN[15][2]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N1[1]!MAIN[5][1]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N2[1]!MAIN[12][2]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N0[0]!MAIN[27][2]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N1[0]!MAIN[21][2]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N2[0]!MAIN[24][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N0[0]!MAIN[29][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N1[0]!MAIN[22][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N2[0]!MAIN[25][2]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N0[1]!MAIN[17][2]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N1[1]!MAIN[6][1]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N2[1]!MAIN[7][1]
CELL.DOUBLE_IO_N0[0]CELL.DOUBLE_IO_N2[0]!MAIN[23][2]
CELL.DOUBLE_IO_N0[1]CELL.DOUBLE_IO_N2[1]!MAIN[14][2]
xc4000a IO_N0_E switchbox INT muxes DBUF_IO_H[0]
BitsDestination
MAIN[14][1]MAIN[12][1]CELL.DBUF_IO_H[0]
Source
00CELL.DOUBLE_IO_N2[1]
11CELL.DOUBLE_IO_N2[0]
xc4000a IO_N0_E switchbox INT muxes DBUF_IO_H[1]
BitsDestination
MAIN[9][1]MAIN[8][1]CELL.DBUF_IO_H[1]
Source
00CELL.DOUBLE_IO_N0[0]
11CELL.DOUBLE_IO_N0[1]
xc4000a IO_N0_E switchbox INT muxes LONG_V[0]
BitsDestination
MAIN[27][0]MAIN[24][0]MAIN[25][0]MAIN[26][0]CELL.LONG_V[0]
Source
0001CELL.LONG_IO_H[0]
0010CELL.DEC_H[1]
0111CELL.OUT_IO_SN_I2_E1
1111off
xc4000a IO_N0_E switchbox INT muxes LONG_V[1]
BitsDestination
MAIN[15][0]MAIN[12][0]MAIN[14][0]MAIN[17][1]CELL.LONG_V[1]
Source
0001CELL.LONG_IO_H[1]
0010CELL.DEC_H[0]
0111CELL.OUT_IO_SN_I2_E1
1111off
xc4000a IO_N0_E switchbox INT muxes LONG_V[2]
BitsDestination
MAIN[11][0]MAIN[9][0]MAIN[13][0]MAIN[10][0]CELL.LONG_V[2]
Source
0001CELL.LONG_IO_H[0]
0010CELL.DEC_H[1]
0111CELL.OUT_IO_SN_I2[0]
1111off
xc4000a IO_N0_E switchbox INT muxes LONG_V[3]
BitsDestination
MAIN[23][0]MAIN[20][0]MAIN[21][0]MAIN[22][0]CELL.LONG_V[3]
Source
0001CELL.LONG_IO_H[1]
0010CELL.DEC_H[0]
0111CELL.OUT_IO_SN_I2[0]
1111off
xc4000a IO_N0_E switchbox INT muxes LONG_IO_H[0]
BitsDestination
MAIN[2][2]MAIN[3][2]MAIN[5][2]MAIN[4][2]MAIN[6][2]CELL.LONG_IO_H[0]
Source
00011CELL.SINGLE_V[2]
00101CELL.LONG_V[0]
00110CELL.LONG_V[2]
01111CELL.SINGLE_V[0]
11111off
xc4000a IO_N0_E switchbox INT muxes LONG_IO_H[1]
BitsDestination
MAIN[1][1]MAIN[7][2]MAIN[8][2]MAIN[10][2]MAIN[9][2]CELL.LONG_IO_H[1]
Source
00011CELL.SINGLE_V[3]
00101CELL.LONG_V[1]
00110CELL.LONG_V[3]
01111CELL.SINGLE_V[1]
11111off
xc4000a IO_N0_E switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[21][3]MAIN[19][3]MAIN[20][2]MAIN[20][3]MAIN[22][3]CELL.IMUX_IO_O1[0]
Source
00011CELL.DOUBLE_V0[0]
00101CELL.LONG_V[2]
01111CELL.DOUBLE_V1[1]
10011CELL.DEC_H[1]
10101CELL.DEC_H[0]
10110CELL.LONG_V[3]
11111CELL.TIE_0
xc4000a IO_N0_E switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[7][3]MAIN[10][3]MAIN[8][3]MAIN[9][3]MAIN[9][4]CELL.IMUX_IO_O1[1]
Source
00011CELL.DEC_H[0]
00101CELL.DEC_H[1]
01011CELL_E.DOUBLE_V0[1]
01101CELL_E.LONG_V[0]
01110CELL_E.LONG_V[1]
10111CELL_E.DOUBLE_V1[0]
11111CELL.TIE_0
xc4000a IO_N0_E switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[23][3]MAIN[31][3]MAIN[31][2]MAIN[26][3]MAIN[29][3]MAIN[28][3]MAIN[27][3]MAIN[30][3]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[2]
01101111CELL.SINGLE_V[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[1]
xc4000a IO_N0_E switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[0][2]MAIN[5][4]MAIN[1][4]MAIN[2][4]MAIN[4][4]MAIN[0][5]MAIN[1][2]MAIN[0][4]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_E.SINGLE_V[1]
01111101CELL_E.SINGLE_V[2]
01111110CELL_E.SINGLE_V[3]
11111111CELL_E.SINGLE_V[0]
xc4000a IO_N0_E switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[23][4]MAIN[30][4]MAIN[25][3]MAIN[30][2]MAIN[28][4]MAIN[27][4]MAIN[26][4]MAIN[29][4]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[1]
01101111CELL.SINGLE_V[2]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[3]
xc4000a IO_N0_E switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[0][3]MAIN[6][4]MAIN[5][3]MAIN[3][4]MAIN[7][4]MAIN[1][3]MAIN[2][3]MAIN[3][3]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_E.SINGLE_V[0]
01111101CELL_E.SINGLE_V[1]
01111110CELL_E.SINGLE_V[3]
11111111CELL_E.SINGLE_V[2]
xc4000a IO_N0_E switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[14][3]MAIN[17][4]MAIN[18][3]MAIN[15][3]MAIN[17][3]MAIN[16][3]CELL.IMUX_IO_T[0]
Source
001111CELL.TIE_0
010011CELL.DOUBLE_IO_N2[1]
010101CELL.DEC_H[1]
010110CELL.LONG_IO_H[1]
011011CELL.DOUBLE_IO_N2[0]
011101CELL.LONG_IO_H[0]
011110CELL.GCLK[0]
110111CELL.DOUBLE_IO_N1[0]
111111CELL.DOUBLE_IO_N1[1]
xc4000a IO_N0_E switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[12][3]MAIN[14][4]MAIN[13][3]MAIN[11][3]MAIN[16][4]MAIN[15][4]CELL.IMUX_IO_T[1]
Source
001111CELL.TIE_0
010011CELL.DOUBLE_IO_N1[1]
010111CELL.DOUBLE_IO_N1[0]
011001CELL.LONG_IO_H[0]
011010CELL.GCLK[0]
011101CELL.LONG_IO_H[1]
011110CELL.DEC_H[1]
111011CELL.DOUBLE_IO_N2[0]
111111CELL.DOUBLE_IO_N2[1]

Bels IO

xc4000a IO_N0_E bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[21][5]CELL.IMUX_IO_IK[1] invert by !MAIN[11][5]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[28][5]CELL.IMUX_IO_OK[1] invert by !MAIN[4][5]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_F2_NCELL.IMUX_CLB_G2_N
TinCELL.IMUX_IO_T[0] invert by !MAIN[29][5]CELL.IMUX_IO_T[1] invert by !MAIN[3][5]
I1outCELL.OUT_IO_SN_I1[0]CELL.OUT_IO_SN_I1[1]
I2outCELL.OUT_IO_SN_I2[0]CELL.OUT_IO_SN_I2[1]
CLKINoutCELL.OUT_IO_CLKIN-
xc4000a IO_N0_E bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[19][4]!MAIN[10][5]
OFF_SRVAL bit 0!MAIN[22][5]!MAIN[10][4]
READBACK_I1 bit 0!MAIN[15][1]!MAIN[16][2]
READBACK_I2 bit 0!MAIN[13][1]!MAIN[13][2]
READBACK_OQ bit 0!MAIN[24][4]!MAIN[4][3]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[25][5]!MAIN[7][5]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[23][5]MAIN[9][5]
xc4000a IO_N0_E enum IO_SLEW
IO[0].SLEWMAIN[31][5]MAIN[30][5]
IO[1].SLEWMAIN[1][5]MAIN[2][5]
FAST00
MEDFAST01
MEDSLOW10
SLOW11
xc4000a IO_N0_E enum IO_PULL
IO[0].PULLMAIN[21][4]MAIN[24][5]
IO[1].PULLMAIN[11][4]MAIN[8][5]
NONE11
PULLUP01
PULLDOWN10
xc4000a IO_N0_E enum IO_MUX_I
IO[0].MUX_I1MAIN[17][5]MAIN[19][5]MAIN[18][5]
IO[1].MUX_I1MAIN[14][5]MAIN[16][5]MAIN[15][5]
IO[0].MUX_I2MAIN[20][5]MAIN[20][4]MAIN[22][4]
IO[1].MUX_I2MAIN[12][5]MAIN[12][4]MAIN[13][5]
I001
IQ111
IQL010
xc4000a IO_N0_E enum IO_IFF_D
IO[0].IFF_DMAIN[18][4]
IO[1].IFF_DMAIN[13][4]
I1
DELAY0
xc4000a IO_N0_E enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[26][5]
IO[1].MUX_OFF_DMAIN[6][5]
O11
O20
xc4000a IO_N0_E enum IO_MUX_O
IO[0].MUX_OMAIN[27][5]MAIN[24][3]MAIN[25][4]
IO[1].MUX_OMAIN[5][5]MAIN[6][3]MAIN[8][4]
O1001
O1_INV010
O2100
O2_INV011
OQ000

Bels DEC

xc4000a IO_N0_E bel DEC pins
PinDirectionDEC[0]DEC[1]DEC[2]
IinCELL.OUT_IO_SN_I1[0]CELL.IMUX_CLB_C2_NCELL.OUT_IO_SN_I1[1]
O1bidirCELL.DEC_H[0]CELL.DEC_H[0]CELL.DEC_H[0]
O2bidirCELL.DEC_H[1]CELL.DEC_H[1]CELL.DEC_H[1]
xc4000a IO_N0_E bel DEC attribute bits
AttributeDEC[0]DEC[1]DEC[2]
O1_P!MAIN[3][0]!MAIN[3][1]MAIN[0][0]
O1_NMAIN[1][0]MAIN[0][1]!MAIN[2][0]
O2_P!MAIN[6][0]!MAIN[8][0]MAIN[4][0]
O2_NMAIN[5][0]MAIN[4][1]!MAIN[7][0]

Bel wires

xc4000a IO_N0_E bel wires
WirePins
CELL.DEC_H[0]DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_H[1]DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.IMUX_CLB_F2_NIO[0].O2
CELL.IMUX_CLB_G2_NIO[1].O2
CELL.IMUX_CLB_C2_NDEC[1].I
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_SN_I1[0]IO[0].I1, DEC[0].I
CELL.OUT_IO_SN_I1[1]IO[1].I1, DEC[2].I
CELL.OUT_IO_SN_I2[0]IO[0].I2
CELL.OUT_IO_SN_I2[1]IO[1].I2
CELL.OUT_IO_CLKINIO[0].CLKIN

Bitstream

xc4000a IO_N0_E rect MAIN
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B5 IO[0]: SLEW bit 1 IO[0]: SLEW bit 0 IO[0]: !invert T IO[0]: !invert OK IO[0]: MUX_O bit 2 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_D_INV IO[0]: PULL bit 0 IO[0]: OFF_USED IO[0]: ! OFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 2 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I1 bit 2 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 2 IO[1]: MUX_I2 bit 0 IO[1]: MUX_I2 bit 2 IO[1]: !invert IK IO[1]: ! IFF_SRVAL bit 0 IO[1]: OFF_USED IO[1]: PULL bit 0 IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0 IO[1]: MUX_O bit 2 IO[1]: !invert OK IO[1]: !invert T IO[1]: SLEW bit 0 IO[1]: SLEW bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 2
B4 - INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 1 IO[0]: MUX_O bit 0 IO[0]: ! READBACK_OQ bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 7 IO[0]: MUX_I2 bit 0 IO[0]: PULL bit 1 IO[0]: MUX_I2 bit 1 IO[0]: ! IFF_SRVAL bit 0 IO[0]: IFF_D bit 0 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 4 IO[1]: IFF_D bit 0 IO[1]: MUX_I2 bit 1 IO[1]: PULL bit 1 IO[1]: ! OFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 0 IO[1]: MUX_O bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 0
B3 INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 5 IO[0]: MUX_O bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 7 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 4 IO[1]: MUX_O bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 5 IO[1]: ! READBACK_OQ bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 7
B2 INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_IO_N0[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N1[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N1[0] INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N1[0] INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N0[1] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N0[1] IO[1]: ! READBACK_I1 bit 0 INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N0[1] INT: !bipass CELL.DOUBLE_IO_N0[1] = CELL.DOUBLE_IO_N2[1] IO[1]: ! READBACK_I2 bit 0 INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N2[1] INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N2[1] INT: mux CELL.LONG_IO_H[1] bit 1 INT: mux CELL.LONG_IO_H[1] bit 0 INT: mux CELL.LONG_IO_H[1] bit 2 INT: mux CELL.LONG_IO_H[1] bit 3 INT: mux CELL.LONG_IO_H[0] bit 0 INT: mux CELL.LONG_IO_H[0] bit 2 INT: mux CELL.LONG_IO_H[0] bit 1 INT: mux CELL.LONG_IO_H[0] bit 3 INT: mux CELL.LONG_IO_H[0] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 7
B1 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I2_E1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.SINGLE_V[2] ← CELL.DEC_H[0] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[1] INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_V[1] ← CELL.DEC_H[1] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_IO_H[1] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_IO_N2[0] ← CELL.DBUF_IO_H[1] INT: mux CELL.LONG_V[1] bit 0 INT: !pass CELL.DOUBLE_IO_N2[1] ← CELL.DBUF_IO_H[1] IO[0]: ! READBACK_I1 bit 0 INT: mux CELL.DBUF_IO_H[0] bit 1 IO[0]: ! READBACK_I2 bit 0 INT: mux CELL.DBUF_IO_H[0] bit 0 INT: !pass CELL.DOUBLE_IO_N0[1] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_N0[0] ← CELL.DBUF_IO_H[0] INT: mux CELL.DBUF_IO_H[1] bit 1 INT: mux CELL.DBUF_IO_H[1] bit 0 INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N2[1] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N1[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N1[1] DEC[1]: O2_N DEC[1]: ! O1_P INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N1[1] INT: mux CELL.LONG_IO_H[1] bit 4 DEC[1]: O1_N
B0 INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_IO_H[0] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1 INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[0] INT: mux CELL.LONG_V[0] bit 3 INT: mux CELL.LONG_V[0] bit 0 INT: mux CELL.LONG_V[0] bit 1 INT: mux CELL.LONG_V[0] bit 2 INT: mux CELL.LONG_V[3] bit 3 INT: mux CELL.LONG_V[3] bit 0 INT: mux CELL.LONG_V[3] bit 1 INT: mux CELL.LONG_V[3] bit 2 INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[1] INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[1] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.LONG_V[1] bit 3 INT: mux CELL.LONG_V[1] bit 1 INT: mux CELL.LONG_V[2] bit 1 INT: mux CELL.LONG_V[1] bit 2 INT: mux CELL.LONG_V[2] bit 3 INT: mux CELL.LONG_V[2] bit 0 INT: mux CELL.LONG_V[2] bit 2 DEC[1]: ! O2_P DEC[2]: ! O2_N DEC[0]: ! O2_P DEC[0]: O2_N DEC[2]: O2_P DEC[0]: ! O1_P DEC[2]: ! O1_N DEC[0]: O1_N DEC[2]: O1_P
xc4000a IO_N0_E rect MAIN_S
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_H[0] INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[0] - - - - - - - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000a IO_N0_E rect MAIN_E
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000a IO_N0_E rect MAIN_W
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_N1

Cells: 3

Switchbox INT

xc4000a IO_N1 switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[0]!MAIN_S[29][9]
CELL.LONG_H[2]CELL.SINGLE_V[1]!MAIN[18][0]
xc4000a IO_N1 switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_V[0]CELL.LONG_H[0]!MAIN_S[30][9]
CELL.SINGLE_V[0]CELL.LONG_IO_H[0]!MAIN[31][0]
CELL.SINGLE_V[0]CELL.DEC_H[0]!MAIN[28][0]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I1[0]!MAIN[30][0]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I2_E1!MAIN[29][0]
CELL.SINGLE_V[1]CELL.LONG_H[2]!MAIN_S[21][9]
CELL.SINGLE_V[1]CELL.LONG_IO_H[1]!MAIN[25][1]
CELL.SINGLE_V[1]CELL.DEC_H[1]!MAIN[22][1]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I2[0]!MAIN[23][1]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I1_E1!MAIN[24][1]
CELL.SINGLE_V[2]CELL.LONG_IO_H[0]!MAIN[31][1]
CELL.SINGLE_V[2]CELL.DEC_H[0]!MAIN[27][1]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I1[0]!MAIN[30][1]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I2_E1!MAIN[29][1]
CELL.SINGLE_V[3]CELL.LONG_IO_H[1]!MAIN[20][1]
CELL.SINGLE_V[3]CELL.DEC_H[1]!MAIN[19][0]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I2[0]!MAIN[21][1]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I1_E1!MAIN[17][0]
CELL.DOUBLE_V0[0]CELL.OUT_IO_SN_I1_E1!MAIN[28][1]
CELL.DOUBLE_V0[1]CELL.OUT_IO_SN_I2[0]!MAIN[19][1]
CELL.DOUBLE_V1[0]CELL.OUT_IO_SN_I1[0]!MAIN[26][1]
CELL.DOUBLE_V1[1]CELL.OUT_IO_SN_I2_E1!MAIN[16][0]
CELL.DOUBLE_IO_N0[0]CELL.DBUF_IO_H[0]!MAIN[10][1]
CELL.DOUBLE_IO_N0[1]CELL.DBUF_IO_H[0]!MAIN[11][1]
CELL.DOUBLE_IO_N2[0]CELL.DBUF_IO_H[1]!MAIN[18][1]
CELL.DOUBLE_IO_N2[1]CELL.DBUF_IO_H[1]!MAIN[16][1]
xc4000a IO_N1 switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_V[0]CELL.DOUBLE_IO_N1[0]!MAIN[19][2]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_N0[0]!MAIN[28][2]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_N2[0]!MAIN[26][2]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_N1[1]!MAIN[2][1]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_N0[1]!MAIN[18][2]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_N2[1]!MAIN[11][2]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N0[1]!MAIN[15][2]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N1[1]!MAIN[5][1]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N2[1]!MAIN[12][2]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N0[0]!MAIN[27][2]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N1[0]!MAIN[21][2]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N2[0]!MAIN[24][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N0[0]!MAIN[29][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N1[0]!MAIN[22][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N2[0]!MAIN[25][2]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N0[1]!MAIN[17][2]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N1[1]!MAIN[6][1]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N2[1]!MAIN[7][1]
CELL.DOUBLE_IO_N0[0]CELL.DOUBLE_IO_N2[0]!MAIN[23][2]
CELL.DOUBLE_IO_N0[1]CELL.DOUBLE_IO_N2[1]!MAIN[14][2]
xc4000a IO_N1 switchbox INT muxes DBUF_IO_H[0]
BitsDestination
MAIN[14][1]MAIN[12][1]CELL.DBUF_IO_H[0]
Source
00CELL.DOUBLE_IO_N2[1]
11CELL.DOUBLE_IO_N2[0]
xc4000a IO_N1 switchbox INT muxes DBUF_IO_H[1]
BitsDestination
MAIN[9][1]MAIN[8][1]CELL.DBUF_IO_H[1]
Source
00CELL.DOUBLE_IO_N0[0]
11CELL.DOUBLE_IO_N0[1]
xc4000a IO_N1 switchbox INT muxes LONG_V[0]
BitsDestination
MAIN[27][0]MAIN[24][0]MAIN[25][0]MAIN[26][0]CELL.LONG_V[0]
Source
0001CELL.LONG_IO_H[0]
0010CELL.DEC_H[1]
0111CELL.OUT_IO_SN_I2_E1
1111off
xc4000a IO_N1 switchbox INT muxes LONG_V[1]
BitsDestination
MAIN[15][0]MAIN[12][0]MAIN[14][0]MAIN[17][1]CELL.LONG_V[1]
Source
0001CELL.LONG_IO_H[1]
0010CELL.DEC_H[0]
0111CELL.OUT_IO_SN_I2_E1
1111off
xc4000a IO_N1 switchbox INT muxes LONG_V[2]
BitsDestination
MAIN[11][0]MAIN[9][0]MAIN[13][0]MAIN[10][0]CELL.LONG_V[2]
Source
0001CELL.LONG_IO_H[0]
0010CELL.DEC_H[1]
0111CELL.OUT_IO_SN_I2[0]
1111off
xc4000a IO_N1 switchbox INT muxes LONG_V[3]
BitsDestination
MAIN[23][0]MAIN[20][0]MAIN[21][0]MAIN[22][0]CELL.LONG_V[3]
Source
0001CELL.LONG_IO_H[1]
0010CELL.DEC_H[0]
0111CELL.OUT_IO_SN_I2[0]
1111off
xc4000a IO_N1 switchbox INT muxes LONG_IO_H[0]
BitsDestination
MAIN[2][2]MAIN[3][2]MAIN[5][2]MAIN[4][2]MAIN[6][2]CELL.LONG_IO_H[0]
Source
00011CELL.SINGLE_V[2]
00101CELL.LONG_V[0]
00110CELL.LONG_V[2]
01111CELL.SINGLE_V[0]
11111off
xc4000a IO_N1 switchbox INT muxes LONG_IO_H[1]
BitsDestination
MAIN[1][1]MAIN[7][2]MAIN[8][2]MAIN[10][2]MAIN[9][2]CELL.LONG_IO_H[1]
Source
00011CELL.SINGLE_V[3]
00101CELL.LONG_V[1]
00110CELL.LONG_V[3]
01111CELL.SINGLE_V[1]
11111off
xc4000a IO_N1 switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[21][3]MAIN[19][3]MAIN[20][2]MAIN[20][3]MAIN[22][3]CELL.IMUX_IO_O1[0]
Source
00011CELL.DOUBLE_V0[0]
00101CELL.LONG_V[2]
01111CELL.DOUBLE_V1[1]
10011CELL.DEC_H[1]
10101CELL.DEC_H[0]
10110CELL.LONG_V[3]
11111CELL.TIE_0
xc4000a IO_N1 switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[7][3]MAIN[10][3]MAIN[8][3]MAIN[9][3]MAIN[9][4]CELL.IMUX_IO_O1[1]
Source
00011CELL.DEC_H[0]
00101CELL.DEC_H[1]
01011CELL_E.DOUBLE_V0[1]
01101CELL_E.LONG_V[0]
01110CELL_E.LONG_V[1]
10111CELL_E.DOUBLE_V1[0]
11111CELL.TIE_0
xc4000a IO_N1 switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[23][3]MAIN[31][3]MAIN[31][2]MAIN[26][3]MAIN[29][3]MAIN[28][3]MAIN[27][3]MAIN[30][3]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[2]
01101111CELL.SINGLE_V[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[1]
xc4000a IO_N1 switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[0][2]MAIN[5][4]MAIN[1][4]MAIN[2][4]MAIN[4][4]MAIN[0][5]MAIN[1][2]MAIN[0][4]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_E.SINGLE_V[1]
01111101CELL_E.SINGLE_V[2]
01111110CELL_E.SINGLE_V[3]
11111111CELL_E.SINGLE_V[0]
xc4000a IO_N1 switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[23][4]MAIN[30][4]MAIN[25][3]MAIN[30][2]MAIN[28][4]MAIN[27][4]MAIN[26][4]MAIN[29][4]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[1]
01101111CELL.SINGLE_V[2]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[3]
xc4000a IO_N1 switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[0][3]MAIN[6][4]MAIN[5][3]MAIN[3][4]MAIN[7][4]MAIN[1][3]MAIN[2][3]MAIN[3][3]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_E.SINGLE_V[0]
01111101CELL_E.SINGLE_V[1]
01111110CELL_E.SINGLE_V[3]
11111111CELL_E.SINGLE_V[2]
xc4000a IO_N1 switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[14][3]MAIN[17][4]MAIN[18][3]MAIN[15][3]MAIN[17][3]MAIN[16][3]CELL.IMUX_IO_T[0]
Source
001111CELL.TIE_0
010011CELL.DOUBLE_IO_N2[1]
010101CELL.DEC_H[1]
010110CELL.LONG_IO_H[1]
011011CELL.DOUBLE_IO_N2[0]
011101CELL.LONG_IO_H[0]
011110CELL.GCLK[0]
110111CELL.DOUBLE_IO_N1[0]
111111CELL.DOUBLE_IO_N1[1]
xc4000a IO_N1 switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[12][3]MAIN[14][4]MAIN[13][3]MAIN[11][3]MAIN[16][4]MAIN[15][4]CELL.IMUX_IO_T[1]
Source
001111CELL.TIE_0
010011CELL.DOUBLE_IO_N1[1]
010111CELL.DOUBLE_IO_N1[0]
011001CELL.LONG_IO_H[0]
011010CELL.GCLK[0]
011101CELL.LONG_IO_H[1]
011110CELL.DEC_H[1]
111011CELL.DOUBLE_IO_N2[0]
111111CELL.DOUBLE_IO_N2[1]

Bels IO

xc4000a IO_N1 bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[21][5]CELL.IMUX_IO_IK[1] invert by !MAIN[11][5]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[28][5]CELL.IMUX_IO_OK[1] invert by !MAIN[4][5]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_F2_NCELL.IMUX_CLB_G2_N
TinCELL.IMUX_IO_T[0] invert by !MAIN[29][5]CELL.IMUX_IO_T[1] invert by !MAIN[3][5]
I1outCELL.OUT_IO_SN_I1[0]CELL.OUT_IO_SN_I1[1]
I2outCELL.OUT_IO_SN_I2[0]CELL.OUT_IO_SN_I2[1]
xc4000a IO_N1 bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[19][4]!MAIN[10][5]
OFF_SRVAL bit 0!MAIN[22][5]!MAIN[10][4]
READBACK_I1 bit 0!MAIN[15][1]!MAIN[16][2]
READBACK_I2 bit 0!MAIN[13][1]!MAIN[13][2]
READBACK_OQ bit 0!MAIN[24][4]!MAIN[4][3]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[25][5]!MAIN[7][5]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[23][5]MAIN[9][5]
xc4000a IO_N1 enum IO_SLEW
IO[0].SLEWMAIN[31][5]MAIN[30][5]
IO[1].SLEWMAIN[1][5]MAIN[2][5]
FAST00
MEDFAST01
MEDSLOW10
SLOW11
xc4000a IO_N1 enum IO_PULL
IO[0].PULLMAIN[21][4]MAIN[24][5]
IO[1].PULLMAIN[11][4]MAIN[8][5]
NONE11
PULLUP01
PULLDOWN10
xc4000a IO_N1 enum IO_MUX_I
IO[0].MUX_I1MAIN[17][5]MAIN[19][5]MAIN[18][5]
IO[1].MUX_I1MAIN[14][5]MAIN[16][5]MAIN[15][5]
IO[0].MUX_I2MAIN[20][5]MAIN[20][4]MAIN[22][4]
IO[1].MUX_I2MAIN[12][5]MAIN[12][4]MAIN[13][5]
I001
IQ111
IQL010
xc4000a IO_N1 enum IO_IFF_D
IO[0].IFF_DMAIN[18][4]
IO[1].IFF_DMAIN[13][4]
I1
DELAY0
xc4000a IO_N1 enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[26][5]
IO[1].MUX_OFF_DMAIN[6][5]
O11
O20
xc4000a IO_N1 enum IO_MUX_O
IO[0].MUX_OMAIN[27][5]MAIN[24][3]MAIN[25][4]
IO[1].MUX_OMAIN[5][5]MAIN[6][3]MAIN[8][4]
O1001
O1_INV010
O2100
O2_INV011
OQ000

Bels DEC

xc4000a IO_N1 bel DEC pins
PinDirectionDEC[0]DEC[1]DEC[2]
IinCELL.OUT_IO_SN_I1[0]CELL.IMUX_CLB_C2_NCELL.OUT_IO_SN_I1[1]
O1bidirCELL.DEC_H[0]CELL.DEC_H[0]CELL.DEC_H[0]
O2bidirCELL.DEC_H[1]CELL.DEC_H[1]CELL.DEC_H[1]
xc4000a IO_N1 bel DEC attribute bits
AttributeDEC[0]DEC[1]DEC[2]
O1_P!MAIN[3][0]!MAIN[3][1]MAIN[0][0]
O1_NMAIN[1][0]MAIN[0][1]!MAIN[2][0]
O2_P!MAIN[6][0]!MAIN[8][0]MAIN[4][0]
O2_NMAIN[5][0]MAIN[4][1]!MAIN[7][0]

Bel wires

xc4000a IO_N1 bel wires
WirePins
CELL.DEC_H[0]DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_H[1]DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.IMUX_CLB_F2_NIO[0].O2
CELL.IMUX_CLB_G2_NIO[1].O2
CELL.IMUX_CLB_C2_NDEC[1].I
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_SN_I1[0]IO[0].I1, DEC[0].I
CELL.OUT_IO_SN_I1[1]IO[1].I1, DEC[2].I
CELL.OUT_IO_SN_I2[0]IO[0].I2
CELL.OUT_IO_SN_I2[1]IO[1].I2

Bitstream

xc4000a IO_N1 rect MAIN
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B5 IO[0]: SLEW bit 1 IO[0]: SLEW bit 0 IO[0]: !invert T IO[0]: !invert OK IO[0]: MUX_O bit 2 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_D_INV IO[0]: PULL bit 0 IO[0]: OFF_USED IO[0]: ! OFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 2 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I1 bit 2 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 2 IO[1]: MUX_I2 bit 0 IO[1]: MUX_I2 bit 2 IO[1]: !invert IK IO[1]: ! IFF_SRVAL bit 0 IO[1]: OFF_USED IO[1]: PULL bit 0 IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0 IO[1]: MUX_O bit 2 IO[1]: !invert OK IO[1]: !invert T IO[1]: SLEW bit 0 IO[1]: SLEW bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 2
B4 - INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 1 IO[0]: MUX_O bit 0 IO[0]: ! READBACK_OQ bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 7 IO[0]: MUX_I2 bit 0 IO[0]: PULL bit 1 IO[0]: MUX_I2 bit 1 IO[0]: ! IFF_SRVAL bit 0 IO[0]: IFF_D bit 0 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 4 IO[1]: IFF_D bit 0 IO[1]: MUX_I2 bit 1 IO[1]: PULL bit 1 IO[1]: ! OFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 0 IO[1]: MUX_O bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 0
B3 INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 5 IO[0]: MUX_O bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 7 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 4 IO[1]: MUX_O bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 5 IO[1]: ! READBACK_OQ bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 7
B2 INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_IO_N0[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N1[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N1[0] INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N1[0] INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N0[1] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N0[1] IO[1]: ! READBACK_I1 bit 0 INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N0[1] INT: !bipass CELL.DOUBLE_IO_N0[1] = CELL.DOUBLE_IO_N2[1] IO[1]: ! READBACK_I2 bit 0 INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N2[1] INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N2[1] INT: mux CELL.LONG_IO_H[1] bit 1 INT: mux CELL.LONG_IO_H[1] bit 0 INT: mux CELL.LONG_IO_H[1] bit 2 INT: mux CELL.LONG_IO_H[1] bit 3 INT: mux CELL.LONG_IO_H[0] bit 0 INT: mux CELL.LONG_IO_H[0] bit 2 INT: mux CELL.LONG_IO_H[0] bit 1 INT: mux CELL.LONG_IO_H[0] bit 3 INT: mux CELL.LONG_IO_H[0] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 7
B1 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I2_E1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.SINGLE_V[2] ← CELL.DEC_H[0] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[1] INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_V[1] ← CELL.DEC_H[1] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_IO_H[1] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_IO_N2[0] ← CELL.DBUF_IO_H[1] INT: mux CELL.LONG_V[1] bit 0 INT: !pass CELL.DOUBLE_IO_N2[1] ← CELL.DBUF_IO_H[1] IO[0]: ! READBACK_I1 bit 0 INT: mux CELL.DBUF_IO_H[0] bit 1 IO[0]: ! READBACK_I2 bit 0 INT: mux CELL.DBUF_IO_H[0] bit 0 INT: !pass CELL.DOUBLE_IO_N0[1] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_N0[0] ← CELL.DBUF_IO_H[0] INT: mux CELL.DBUF_IO_H[1] bit 1 INT: mux CELL.DBUF_IO_H[1] bit 0 INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N2[1] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N1[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N1[1] DEC[1]: O2_N DEC[1]: ! O1_P INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N1[1] INT: mux CELL.LONG_IO_H[1] bit 4 DEC[1]: O1_N
B0 INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_IO_H[0] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1 INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[0] INT: mux CELL.LONG_V[0] bit 3 INT: mux CELL.LONG_V[0] bit 0 INT: mux CELL.LONG_V[0] bit 1 INT: mux CELL.LONG_V[0] bit 2 INT: mux CELL.LONG_V[3] bit 3 INT: mux CELL.LONG_V[3] bit 0 INT: mux CELL.LONG_V[3] bit 1 INT: mux CELL.LONG_V[3] bit 2 INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[1] INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[1] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.LONG_V[1] bit 3 INT: mux CELL.LONG_V[1] bit 1 INT: mux CELL.LONG_V[2] bit 1 INT: mux CELL.LONG_V[1] bit 2 INT: mux CELL.LONG_V[2] bit 3 INT: mux CELL.LONG_V[2] bit 0 INT: mux CELL.LONG_V[2] bit 2 DEC[1]: ! O2_P DEC[2]: ! O2_N DEC[0]: ! O2_P DEC[0]: O2_N DEC[2]: O2_P DEC[0]: ! O1_P DEC[2]: ! O1_N DEC[0]: O1_N DEC[2]: O1_P
xc4000a IO_N1 rect MAIN_S
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_H[0] INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[0] - - - - - - - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000a IO_N1 rect MAIN_E
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000a IO_N1 rect MAIN_W
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile IO_N1_W

Cells: 3

Switchbox INT

xc4000a IO_N1_W switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[0]!MAIN_S[29][9]
CELL.LONG_H[2]CELL.SINGLE_V[1]!MAIN[18][0]
xc4000a IO_N1_W switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_V[0]CELL.LONG_H[0]!MAIN_S[30][9]
CELL.SINGLE_V[0]CELL.LONG_IO_H[0]!MAIN[31][0]
CELL.SINGLE_V[0]CELL.DEC_H[0]!MAIN[28][0]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I1[0]!MAIN[30][0]
CELL.SINGLE_V[0]CELL.OUT_IO_SN_I2_E1!MAIN[29][0]
CELL.SINGLE_V[1]CELL.LONG_H[2]!MAIN_S[21][9]
CELL.SINGLE_V[1]CELL.LONG_IO_H[1]!MAIN[25][1]
CELL.SINGLE_V[1]CELL.DEC_H[1]!MAIN[22][1]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I2[0]!MAIN[23][1]
CELL.SINGLE_V[1]CELL.OUT_IO_SN_I1_E1!MAIN[24][1]
CELL.SINGLE_V[2]CELL.LONG_IO_H[0]!MAIN[31][1]
CELL.SINGLE_V[2]CELL.DEC_H[0]!MAIN[27][1]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I1[0]!MAIN[30][1]
CELL.SINGLE_V[2]CELL.OUT_IO_SN_I2_E1!MAIN[29][1]
CELL.SINGLE_V[3]CELL.LONG_IO_H[1]!MAIN[20][1]
CELL.SINGLE_V[3]CELL.DEC_H[1]!MAIN[19][0]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I2[0]!MAIN[21][1]
CELL.SINGLE_V[3]CELL.OUT_IO_SN_I1_E1!MAIN[17][0]
CELL.DOUBLE_V0[0]CELL.OUT_IO_SN_I1_E1!MAIN[28][1]
CELL.DOUBLE_V0[1]CELL.OUT_IO_SN_I2[0]!MAIN[19][1]
CELL.DOUBLE_V1[0]CELL.OUT_IO_SN_I1[0]!MAIN[26][1]
CELL.DOUBLE_V1[1]CELL.OUT_IO_SN_I2_E1!MAIN[16][0]
CELL.DOUBLE_IO_N0[0]CELL.DBUF_IO_H[0]!MAIN[10][1]
CELL.DOUBLE_IO_N0[1]CELL.DBUF_IO_H[0]!MAIN[11][1]
CELL.DOUBLE_IO_N2[0]CELL.DBUF_IO_H[1]!MAIN[18][1]
CELL.DOUBLE_IO_N2[1]CELL.DBUF_IO_H[1]!MAIN[16][1]
xc4000a IO_N1_W switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_V[0]CELL.DOUBLE_IO_N1[0]!MAIN[19][2]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_N0[0]!MAIN[28][2]
CELL.SINGLE_V[1]CELL.DOUBLE_IO_N2[0]!MAIN[26][2]
CELL.SINGLE_V[2]CELL.DOUBLE_IO_N1[1]!MAIN[2][1]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_N0[1]!MAIN[18][2]
CELL.SINGLE_V[3]CELL.DOUBLE_IO_N2[1]!MAIN[11][2]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N0[1]!MAIN[15][2]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N1[1]!MAIN[5][1]
CELL.DOUBLE_V0[0]CELL.DOUBLE_IO_N2[1]!MAIN[12][2]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N0[0]!MAIN[27][2]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N1[0]!MAIN[21][2]
CELL.DOUBLE_V0[1]CELL.DOUBLE_IO_N2[0]!MAIN[24][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N0[0]!MAIN[29][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N1[0]!MAIN[22][2]
CELL.DOUBLE_V1[0]CELL.DOUBLE_IO_N2[0]!MAIN[25][2]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N0[1]!MAIN[17][2]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N1[1]!MAIN[6][1]
CELL.DOUBLE_V1[1]CELL.DOUBLE_IO_N2[1]!MAIN[7][1]
CELL.DOUBLE_IO_N0[0]CELL.DOUBLE_IO_N2[0]!MAIN[23][2]
CELL.DOUBLE_IO_N0[1]CELL.DOUBLE_IO_N2[1]!MAIN[14][2]
xc4000a IO_N1_W switchbox INT muxes DBUF_IO_H[0]
BitsDestination
MAIN[14][1]MAIN[12][1]CELL.DBUF_IO_H[0]
Source
00CELL.DOUBLE_IO_N2[1]
11CELL.DOUBLE_IO_N2[0]
xc4000a IO_N1_W switchbox INT muxes DBUF_IO_H[1]
BitsDestination
MAIN[9][1]MAIN[8][1]CELL.DBUF_IO_H[1]
Source
00CELL.DOUBLE_IO_N0[0]
11CELL.DOUBLE_IO_N0[1]
xc4000a IO_N1_W switchbox INT muxes LONG_V[0]
BitsDestination
MAIN[27][0]MAIN[24][0]MAIN[25][0]MAIN[26][0]CELL.LONG_V[0]
Source
0001CELL.LONG_IO_H[0]
0010CELL.DEC_H[1]
0111CELL.OUT_IO_SN_I2_E1
1111off
xc4000a IO_N1_W switchbox INT muxes LONG_V[1]
BitsDestination
MAIN[15][0]MAIN[12][0]MAIN[14][0]MAIN[17][1]CELL.LONG_V[1]
Source
0001CELL.LONG_IO_H[1]
0010CELL.DEC_H[0]
0111CELL.OUT_IO_SN_I2_E1
1111off
xc4000a IO_N1_W switchbox INT muxes LONG_V[2]
BitsDestination
MAIN[11][0]MAIN[9][0]MAIN[13][0]MAIN[10][0]CELL.LONG_V[2]
Source
0001CELL.LONG_IO_H[0]
0010CELL.DEC_H[1]
0111CELL.OUT_IO_SN_I2[0]
1111off
xc4000a IO_N1_W switchbox INT muxes LONG_V[3]
BitsDestination
MAIN[23][0]MAIN[20][0]MAIN[21][0]MAIN[22][0]CELL.LONG_V[3]
Source
0001CELL.LONG_IO_H[1]
0010CELL.DEC_H[0]
0111CELL.OUT_IO_SN_I2[0]
1111off
xc4000a IO_N1_W switchbox INT muxes LONG_IO_H[0]
BitsDestination
MAIN[2][2]MAIN[3][2]MAIN[5][2]MAIN[4][2]MAIN[6][2]CELL.LONG_IO_H[0]
Source
00011CELL.SINGLE_V[2]
00101CELL.LONG_V[0]
00110CELL.LONG_V[2]
01111CELL.SINGLE_V[0]
11111off
xc4000a IO_N1_W switchbox INT muxes LONG_IO_H[1]
BitsDestination
MAIN[1][1]MAIN[7][2]MAIN[8][2]MAIN[10][2]MAIN[9][2]CELL.LONG_IO_H[1]
Source
00011CELL.SINGLE_V[3]
00101CELL.LONG_V[1]
00110CELL.LONG_V[3]
01111CELL.SINGLE_V[1]
11111off
xc4000a IO_N1_W switchbox INT muxes IMUX_IO_O1[0]
BitsDestination
MAIN[21][3]MAIN[19][3]MAIN[20][2]MAIN[20][3]MAIN[22][3]CELL.IMUX_IO_O1[0]
Source
00011CELL.DOUBLE_V0[0]
00101CELL.LONG_V[2]
01111CELL.DOUBLE_V1[1]
10011CELL.DEC_H[1]
10101CELL.DEC_H[0]
10110CELL.LONG_V[3]
11111CELL.TIE_0
xc4000a IO_N1_W switchbox INT muxes IMUX_IO_O1[1]
BitsDestination
MAIN[7][3]MAIN[10][3]MAIN[8][3]MAIN[9][3]MAIN[9][4]CELL.IMUX_IO_O1[1]
Source
00011CELL.DEC_H[0]
00101CELL.DEC_H[1]
01011CELL_E.DOUBLE_V0[1]
01101CELL_E.LONG_V[0]
01110CELL_E.LONG_V[1]
10111CELL_E.DOUBLE_V1[0]
11111CELL.TIE_0
xc4000a IO_N1_W switchbox INT muxes IMUX_IO_OK[0]
BitsDestination
MAIN[23][3]MAIN[31][3]MAIN[31][2]MAIN[26][3]MAIN[29][3]MAIN[28][3]MAIN[27][3]MAIN[30][3]CELL.IMUX_IO_OK[0]
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[2]
01101111CELL.SINGLE_V[3]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[1]
xc4000a IO_N1_W switchbox INT muxes IMUX_IO_OK[1]
BitsDestination
MAIN[0][2]MAIN[5][4]MAIN[1][4]MAIN[2][4]MAIN[4][4]MAIN[0][5]MAIN[1][2]MAIN[0][4]CELL.IMUX_IO_OK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_E.SINGLE_V[1]
01111101CELL_E.SINGLE_V[2]
01111110CELL_E.SINGLE_V[3]
11111111CELL_E.SINGLE_V[0]
xc4000a IO_N1_W switchbox INT muxes IMUX_IO_IK[0]
BitsDestination
MAIN[23][4]MAIN[30][4]MAIN[25][3]MAIN[30][2]MAIN[28][4]MAIN[27][4]MAIN[26][4]MAIN[29][4]CELL.IMUX_IO_IK[0]
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[1]
01101111CELL.SINGLE_V[2]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[3]
xc4000a IO_N1_W switchbox INT muxes IMUX_IO_IK[1]
BitsDestination
MAIN[0][3]MAIN[6][4]MAIN[5][3]MAIN[3][4]MAIN[7][4]MAIN[1][3]MAIN[2][3]MAIN[3][3]CELL.IMUX_IO_IK[1]
Source
00111111CELL.GCLK[0]
01011111CELL.GCLK[1]
01101111CELL.GCLK[2]
01110111CELL.GCLK[3]
01111011CELL_E.SINGLE_V[0]
01111101CELL_E.SINGLE_V[1]
01111110CELL_E.SINGLE_V[3]
11111111CELL_E.SINGLE_V[2]
xc4000a IO_N1_W switchbox INT muxes IMUX_IO_T[0]
BitsDestination
MAIN[14][3]MAIN[17][4]MAIN[18][3]MAIN[15][3]MAIN[17][3]MAIN[16][3]CELL.IMUX_IO_T[0]
Source
001111CELL.TIE_0
010011CELL.DOUBLE_IO_N2[1]
010101CELL.DEC_H[1]
010110CELL.LONG_IO_H[1]
011011CELL.DOUBLE_IO_N2[0]
011101CELL.LONG_IO_H[0]
011110CELL.GCLK[0]
110111CELL.DOUBLE_IO_N1[0]
111111CELL.DOUBLE_IO_N1[1]
xc4000a IO_N1_W switchbox INT muxes IMUX_IO_T[1]
BitsDestination
MAIN[12][3]MAIN[14][4]MAIN[13][3]MAIN[11][3]MAIN[16][4]MAIN[15][4]CELL.IMUX_IO_T[1]
Source
001111CELL.TIE_0
010011CELL.DOUBLE_IO_N1[1]
010111CELL.DOUBLE_IO_N1[0]
011001CELL.LONG_IO_H[0]
011010CELL.GCLK[0]
011101CELL.LONG_IO_H[1]
011110CELL.DEC_H[1]
111011CELL.DOUBLE_IO_N2[0]
111111CELL.DOUBLE_IO_N2[1]

Bels IO

xc4000a IO_N1_W bel IO pins
PinDirectionIO[0]IO[1]
IKinCELL.IMUX_IO_IK[0] invert by !MAIN[21][5]CELL.IMUX_IO_IK[1] invert by !MAIN[11][5]
OKinCELL.IMUX_IO_OK[0] invert by !MAIN[28][5]CELL.IMUX_IO_OK[1] invert by !MAIN[4][5]
O1inCELL.IMUX_IO_O1[0]CELL.IMUX_IO_O1[1]
O2inCELL.IMUX_CLB_F2_NCELL.IMUX_CLB_G2_N
TinCELL.IMUX_IO_T[0] invert by !MAIN[29][5]CELL.IMUX_IO_T[1] invert by !MAIN[3][5]
I1outCELL.OUT_IO_SN_I1[0]CELL.OUT_IO_SN_I1[1]
I2outCELL.OUT_IO_SN_I2[0]CELL.OUT_IO_SN_I2[1]
CLKINoutCELL.OUT_IO_CLKIN-
xc4000a IO_N1_W bel IO attribute bits
AttributeIO[0]IO[1]
SLEW[enum: IO_SLEW][enum: IO_SLEW]
PULL[enum: IO_PULL][enum: IO_PULL]
IFF_SRVAL bit 0!MAIN[19][4]!MAIN[10][5]
OFF_SRVAL bit 0!MAIN[22][5]!MAIN[10][4]
READBACK_I1 bit 0!MAIN[15][1]!MAIN[16][2]
READBACK_I2 bit 0!MAIN[13][1]!MAIN[13][2]
READBACK_OQ bit 0!MAIN[24][4]!MAIN[4][3]
MUX_I1[enum: IO_MUX_I][enum: IO_MUX_I]
MUX_I2[enum: IO_MUX_I][enum: IO_MUX_I]
IFF_D[enum: IO_IFF_D][enum: IO_IFF_D]
OFF_D_INV!MAIN[25][5]!MAIN[7][5]
MUX_OFF_D[enum: IO_MUX_OFF_D][enum: IO_MUX_OFF_D]
MUX_O[enum: IO_MUX_O][enum: IO_MUX_O]
OFF_USEDMAIN[23][5]MAIN[9][5]
xc4000a IO_N1_W enum IO_SLEW
IO[0].SLEWMAIN[31][5]MAIN[30][5]
IO[1].SLEWMAIN[1][5]MAIN[2][5]
FAST00
MEDFAST01
MEDSLOW10
SLOW11
xc4000a IO_N1_W enum IO_PULL
IO[0].PULLMAIN[21][4]MAIN[24][5]
IO[1].PULLMAIN[11][4]MAIN[8][5]
NONE11
PULLUP01
PULLDOWN10
xc4000a IO_N1_W enum IO_MUX_I
IO[0].MUX_I1MAIN[17][5]MAIN[19][5]MAIN[18][5]
IO[1].MUX_I1MAIN[14][5]MAIN[16][5]MAIN[15][5]
IO[0].MUX_I2MAIN[20][5]MAIN[20][4]MAIN[22][4]
IO[1].MUX_I2MAIN[12][5]MAIN[12][4]MAIN[13][5]
I001
IQ111
IQL010
xc4000a IO_N1_W enum IO_IFF_D
IO[0].IFF_DMAIN[18][4]
IO[1].IFF_DMAIN[13][4]
I1
DELAY0
xc4000a IO_N1_W enum IO_MUX_OFF_D
IO[0].MUX_OFF_DMAIN[26][5]
IO[1].MUX_OFF_DMAIN[6][5]
O11
O20
xc4000a IO_N1_W enum IO_MUX_O
IO[0].MUX_OMAIN[27][5]MAIN[24][3]MAIN[25][4]
IO[1].MUX_OMAIN[5][5]MAIN[6][3]MAIN[8][4]
O1001
O1_INV010
O2100
O2_INV011
OQ000

Bels DEC

xc4000a IO_N1_W bel DEC pins
PinDirectionDEC[0]DEC[1]DEC[2]
IinCELL.OUT_IO_SN_I1[0]CELL.IMUX_CLB_C2_NCELL.OUT_IO_SN_I1[1]
O1bidirCELL.DEC_H[0]CELL.DEC_H[0]CELL.DEC_H[0]
O2bidirCELL.DEC_H[1]CELL.DEC_H[1]CELL.DEC_H[1]
xc4000a IO_N1_W bel DEC attribute bits
AttributeDEC[0]DEC[1]DEC[2]
O1_P!MAIN[3][0]!MAIN[3][1]MAIN[0][0]
O1_NMAIN[1][0]MAIN[0][1]!MAIN[2][0]
O2_P!MAIN[6][0]!MAIN[8][0]MAIN[4][0]
O2_NMAIN[5][0]MAIN[4][1]!MAIN[7][0]

Bel wires

xc4000a IO_N1_W bel wires
WirePins
CELL.DEC_H[0]DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_H[1]DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.IMUX_CLB_F2_NIO[0].O2
CELL.IMUX_CLB_G2_NIO[1].O2
CELL.IMUX_CLB_C2_NDEC[1].I
CELL.IMUX_IO_O1[0]IO[0].O1
CELL.IMUX_IO_O1[1]IO[1].O1
CELL.IMUX_IO_OK[0]IO[0].OK
CELL.IMUX_IO_OK[1]IO[1].OK
CELL.IMUX_IO_IK[0]IO[0].IK
CELL.IMUX_IO_IK[1]IO[1].IK
CELL.IMUX_IO_T[0]IO[0].T
CELL.IMUX_IO_T[1]IO[1].T
CELL.OUT_IO_SN_I1[0]IO[0].I1, DEC[0].I
CELL.OUT_IO_SN_I1[1]IO[1].I1, DEC[2].I
CELL.OUT_IO_SN_I2[0]IO[0].I2
CELL.OUT_IO_SN_I2[1]IO[1].I2
CELL.OUT_IO_CLKINIO[0].CLKIN

Bitstream

xc4000a IO_N1_W rect MAIN
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B5 IO[0]: SLEW bit 1 IO[0]: SLEW bit 0 IO[0]: !invert T IO[0]: !invert OK IO[0]: MUX_O bit 2 IO[0]: MUX_OFF_D bit 0 IO[0]: ! OFF_D_INV IO[0]: PULL bit 0 IO[0]: OFF_USED IO[0]: ! OFF_SRVAL bit 0 IO[0]: !invert IK IO[0]: MUX_I2 bit 2 IO[0]: MUX_I1 bit 1 IO[0]: MUX_I1 bit 0 IO[0]: MUX_I1 bit 2 IO[1]: MUX_I1 bit 1 IO[1]: MUX_I1 bit 0 IO[1]: MUX_I1 bit 2 IO[1]: MUX_I2 bit 0 IO[1]: MUX_I2 bit 2 IO[1]: !invert IK IO[1]: ! IFF_SRVAL bit 0 IO[1]: OFF_USED IO[1]: PULL bit 0 IO[1]: ! OFF_D_INV IO[1]: MUX_OFF_D bit 0 IO[1]: MUX_O bit 2 IO[1]: !invert OK IO[1]: !invert T IO[1]: SLEW bit 0 IO[1]: SLEW bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 2
B4 - INT: mux CELL.IMUX_IO_IK[0] bit 6 INT: mux CELL.IMUX_IO_IK[0] bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 3 INT: mux CELL.IMUX_IO_IK[0] bit 2 INT: mux CELL.IMUX_IO_IK[0] bit 1 IO[0]: MUX_O bit 0 IO[0]: ! READBACK_OQ bit 0 INT: mux CELL.IMUX_IO_IK[0] bit 7 IO[0]: MUX_I2 bit 0 IO[0]: PULL bit 1 IO[0]: MUX_I2 bit 1 IO[0]: ! IFF_SRVAL bit 0 IO[0]: IFF_D bit 0 INT: mux CELL.IMUX_IO_T[0] bit 4 INT: mux CELL.IMUX_IO_T[1] bit 1 INT: mux CELL.IMUX_IO_T[1] bit 0 INT: mux CELL.IMUX_IO_T[1] bit 4 IO[1]: IFF_D bit 0 IO[1]: MUX_I2 bit 1 IO[1]: PULL bit 1 IO[1]: ! OFF_SRVAL bit 0 INT: mux CELL.IMUX_IO_O1[1] bit 0 IO[1]: MUX_O bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 6 INT: mux CELL.IMUX_IO_OK[1] bit 3 INT: mux CELL.IMUX_IO_IK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 5 INT: mux CELL.IMUX_IO_OK[1] bit 0
B3 INT: mux CELL.IMUX_IO_OK[0] bit 6 INT: mux CELL.IMUX_IO_OK[0] bit 0 INT: mux CELL.IMUX_IO_OK[0] bit 3 INT: mux CELL.IMUX_IO_OK[0] bit 2 INT: mux CELL.IMUX_IO_OK[0] bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 4 INT: mux CELL.IMUX_IO_IK[0] bit 5 IO[0]: MUX_O bit 1 INT: mux CELL.IMUX_IO_OK[0] bit 7 INT: mux CELL.IMUX_IO_O1[0] bit 0 INT: mux CELL.IMUX_IO_O1[0] bit 4 INT: mux CELL.IMUX_IO_O1[0] bit 1 INT: mux CELL.IMUX_IO_O1[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 3 INT: mux CELL.IMUX_IO_T[0] bit 1 INT: mux CELL.IMUX_IO_T[0] bit 0 INT: mux CELL.IMUX_IO_T[0] bit 2 INT: mux CELL.IMUX_IO_T[0] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 3 INT: mux CELL.IMUX_IO_T[1] bit 5 INT: mux CELL.IMUX_IO_T[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 3 INT: mux CELL.IMUX_IO_O1[1] bit 1 INT: mux CELL.IMUX_IO_O1[1] bit 2 INT: mux CELL.IMUX_IO_O1[1] bit 4 IO[1]: MUX_O bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 5 IO[1]: ! READBACK_OQ bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 0 INT: mux CELL.IMUX_IO_IK[1] bit 1 INT: mux CELL.IMUX_IO_IK[1] bit 2 INT: mux CELL.IMUX_IO_IK[1] bit 7
B2 INT: mux CELL.IMUX_IO_OK[0] bit 5 INT: mux CELL.IMUX_IO_IK[0] bit 4 INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N0[0] INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_IO_N0[0] = CELL.DOUBLE_IO_N2[0] INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N1[0] INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N1[0] INT: mux CELL.IMUX_IO_O1[0] bit 2 INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N1[0] INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N0[1] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N0[1] IO[1]: ! READBACK_I1 bit 0 INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N0[1] INT: !bipass CELL.DOUBLE_IO_N0[1] = CELL.DOUBLE_IO_N2[1] IO[1]: ! READBACK_I2 bit 0 INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N2[1] INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N2[1] INT: mux CELL.LONG_IO_H[1] bit 1 INT: mux CELL.LONG_IO_H[1] bit 0 INT: mux CELL.LONG_IO_H[1] bit 2 INT: mux CELL.LONG_IO_H[1] bit 3 INT: mux CELL.LONG_IO_H[0] bit 0 INT: mux CELL.LONG_IO_H[0] bit 2 INT: mux CELL.LONG_IO_H[0] bit 1 INT: mux CELL.LONG_IO_H[0] bit 3 INT: mux CELL.LONG_IO_H[0] bit 4 INT: mux CELL.IMUX_IO_OK[1] bit 1 INT: mux CELL.IMUX_IO_OK[1] bit 7
B1 INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I2_E1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.SINGLE_V[2] ← CELL.DEC_H[0] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[1] INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_V[1] ← CELL.DEC_H[1] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_IO_H[1] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0] INT: !pass CELL.DOUBLE_IO_N2[0] ← CELL.DBUF_IO_H[1] INT: mux CELL.LONG_V[1] bit 0 INT: !pass CELL.DOUBLE_IO_N2[1] ← CELL.DBUF_IO_H[1] IO[0]: ! READBACK_I1 bit 0 INT: mux CELL.DBUF_IO_H[0] bit 1 IO[0]: ! READBACK_I2 bit 0 INT: mux CELL.DBUF_IO_H[0] bit 0 INT: !pass CELL.DOUBLE_IO_N0[1] ← CELL.DBUF_IO_H[0] INT: !pass CELL.DOUBLE_IO_N0[0] ← CELL.DBUF_IO_H[0] INT: mux CELL.DBUF_IO_H[1] bit 1 INT: mux CELL.DBUF_IO_H[1] bit 0 INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N2[1] INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N1[1] INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N1[1] DEC[1]: O2_N DEC[1]: ! O1_P INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N1[1] INT: mux CELL.LONG_IO_H[1] bit 4 DEC[1]: O1_N
B0 INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_IO_H[0] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I1[0] INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1 INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[0] INT: mux CELL.LONG_V[0] bit 3 INT: mux CELL.LONG_V[0] bit 0 INT: mux CELL.LONG_V[0] bit 1 INT: mux CELL.LONG_V[0] bit 2 INT: mux CELL.LONG_V[3] bit 3 INT: mux CELL.LONG_V[3] bit 0 INT: mux CELL.LONG_V[3] bit 1 INT: mux CELL.LONG_V[3] bit 2 INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[1] INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[1] INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1 INT: mux CELL.LONG_V[1] bit 3 INT: mux CELL.LONG_V[1] bit 1 INT: mux CELL.LONG_V[2] bit 1 INT: mux CELL.LONG_V[1] bit 2 INT: mux CELL.LONG_V[2] bit 3 INT: mux CELL.LONG_V[2] bit 0 INT: mux CELL.LONG_V[2] bit 2 DEC[1]: ! O2_P DEC[2]: ! O2_N DEC[0]: ! O2_P DEC[0]: O2_N DEC[2]: O2_P DEC[0]: ! O1_P DEC[2]: ! O1_N DEC[0]: O1_N DEC[2]: O1_P
xc4000a IO_N1_W rect MAIN_S
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_H[0] INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[0] - - - - - - - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000a IO_N1_W rect MAIN_E
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000a IO_N1_W rect MAIN_W
BitFrame
F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B5 - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - -