Corners

Tile CNR_SW

Cells: 2

Switchbox INT

xc4000a CNR_SW switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[0]	CELL.LONG_IO_V[0]	!MAIN[2][7]
CELL.SINGLE_H[0]	CELL.DEC_V[1]	!MAIN[18][7]
CELL.SINGLE_H[0]	CELL.OUT_IO_WE_I2_S1	!MAIN[4][7]
CELL.SINGLE_H[0]	CELL.OUT_MD0_I	!MAIN[9][7]
CELL.SINGLE_H[1]	CELL.LONG_IO_V[1]	!MAIN[6][7]
CELL.SINGLE_H[1]	CELL.DEC_V[0]	!MAIN[1][7]
CELL.SINGLE_H[1]	CELL.OUT_IO_WE_I1_S1	!MAIN[13][7]
CELL.SINGLE_H[1]	CELL.OUT_RDBK_DATA	!MAIN[15][7]
CELL.SINGLE_H[2]	CELL.LONG_IO_V[0]	!MAIN[3][7]
CELL.SINGLE_H[2]	CELL.DEC_V[1]	!MAIN[17][7]
CELL.SINGLE_H[2]	CELL.OUT_IO_WE_I2_S1	!MAIN[5][7]
CELL.SINGLE_H[2]	CELL.OUT_MD0_I	!MAIN[10][7]
CELL.SINGLE_H[3]	CELL.LONG_IO_V[1]	!MAIN[7][7]
CELL.SINGLE_H[3]	CELL.DEC_V[0]	!MAIN[0][7]
CELL.SINGLE_H[3]	CELL.OUT_IO_WE_I1_S1	!MAIN[12][7]
CELL.SINGLE_H[3]	CELL.OUT_RDBK_DATA	!MAIN[16][7]
CELL.DOUBLE_H0[0]	CELL.OUT_IO_WE_I1_S1	!MAIN[11][7]
CELL.DOUBLE_H0[1]	CELL.OUT_RDBK_DATA	!MAIN[14][7]
CELL.DOUBLE_H1[0]	CELL.OUT_MD0_I	!MAIN[0][8]
CELL.DOUBLE_H1[1]	CELL.OUT_IO_WE_I2_S1	!MAIN[8][7]
CELL.DOUBLE_IO_S0[0]	CELL.DBUF_IO_V[1]	!MAIN[7][8]
CELL.DOUBLE_IO_S0[1]	CELL.DBUF_IO_V[1]	!MAIN[6][8]
CELL.DOUBLE_IO_W2[0]	CELL.DBUF_IO_V[0]	!MAIN[10][8]
CELL.DOUBLE_IO_W2[1]	CELL.DBUF_IO_V[0]	!MAIN[11][8]

xc4000a CNR_SW switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.DOUBLE_IO_S0[0]	!MAIN[5][8]
CELL.SINGLE_H[0]	CELL.DOUBLE_IO_W2[0]	!MAIN[7][9]
CELL.SINGLE_H[1]	CELL.DOUBLE_IO_W1[0]	!MAIN[8][9]
CELL.SINGLE_H[2]	CELL.DOUBLE_IO_S0[1]	!MAIN[14][8]
CELL.SINGLE_H[2]	CELL.DOUBLE_IO_W2[1]	!MAIN[13][8]
CELL.SINGLE_H[3]	CELL.DOUBLE_IO_W1[1]	!MAIN[15][8]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_S0[0]	!MAIN[0][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_W1[0]	!MAIN[2][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_W2[0]	!MAIN[1][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_S0[1]	!MAIN[17][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_W1[1]	!MAIN[16][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_W2[1]	!MAIN[15][9]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_S0[1]	!MAIN[13][9]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_W1[1]	!MAIN[14][9]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_W2[1]	!MAIN[12][9]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_S0[0]	!MAIN[3][8]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_W1[0]	!MAIN[3][9]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_W2[0]	!MAIN[4][9]
CELL.DOUBLE_IO_S0[0]	CELL.DOUBLE_IO_W2[0]	!MAIN[4][8]
CELL.DOUBLE_IO_S0[1]	CELL.DOUBLE_IO_W2[1]	!MAIN[12][8]

xc4000a CNR_SW switchbox INT muxes DBUF_IO_V[0]
Bits		Destination
MAIN[9][8]	MAIN[8][8]	CELL.DBUF_IO_V[0]
		Source
0	0	CELL.DOUBLE_IO_S0[0]
1	1	CELL.DOUBLE_IO_S0[1]

xc4000a CNR_SW switchbox INT muxes DBUF_IO_V[1]
Bits		Destination
MAIN[6][9]	MAIN[5][9]	CELL.DBUF_IO_V[1]
		Source
0	0	CELL.DOUBLE_IO_W2[1]
1	1	CELL.DOUBLE_IO_W2[0]

xc4000a CNR_SW switchbox INT muxes LONG_H[3]
Bits				Destination
MAIN[5][6]	MAIN[1][6]	MAIN[3][6]	MAIN[4][6]	CELL.LONG_H[3]
				Source
0	0	0	1	CELL.LONG_IO_V[0]
0	0	1	0	CELL.DEC_V[0]
0	1	1	1	CELL.OUT_RDBK_DATA
1	1	1	1	off

xc4000a CNR_SW switchbox INT muxes LONG_H[4]
Bits				Destination
MAIN[9][6]	MAIN[10][6]	MAIN[11][6]	MAIN[12][6]	CELL.LONG_H[4]
				Source
0	0	0	1	CELL.LONG_IO_V[1]
0	0	1	0	CELL.DEC_V[1]
0	1	1	1	CELL.OUT_RDBK_DATA
1	1	1	1	off

xc4000a CNR_SW switchbox INT muxes LONG_IO_H[0]
Bits		Destination
MAIN[11][4]	MAIN[6][4]	CELL.LONG_IO_H[0]
		Source
0	0	CELL.LONG_IO_V[1]
0	1	CELL.LONG_IO_V[0]
1	1	off

xc4000a CNR_SW switchbox INT muxes LONG_IO_H[1]
Bits		Destination
MAIN[10][4]	MAIN[8][4]	CELL.LONG_IO_H[1]
		Source
0	0	CELL.LONG_IO_V[0]
0	1	CELL.LONG_IO_V[1]
1	1	off

xc4000a CNR_SW switchbox INT muxes LONG_IO_V[0]
Bits						Destination
MAIN[7][4]	MAIN[13][5]	MAIN[14][5]	MAIN[18][3]	MAIN[15][4]	MAIN[19][3]	CELL.LONG_IO_V[0]
						Source
0	0	0	1	1	1	CELL.SINGLE_H[2]
0	0	1	0	1	1	CELL.LONG_H[3]
0	0	1	1	0	1	CELL.LONG_IO_H[0]
0	0	1	1	1	0	CELL.LONG_IO_H[1]
0	1	1	1	1	1	CELL.SINGLE_H[0]
1	1	1	1	1	1	off

xc4000a CNR_SW switchbox INT muxes LONG_IO_V[1]
Bits						Destination
MAIN[9][4]	MAIN[11][5]	MAIN[12][5]	MAIN[13][4]	MAIN[14][4]	MAIN[12][4]	CELL.LONG_IO_V[1]
						Source
0	0	0	1	1	1	CELL.SINGLE_H[3]
0	0	1	0	1	1	CELL.LONG_H[4]
0	0	1	1	0	1	CELL.LONG_IO_H[0]
0	0	1	1	1	0	CELL.LONG_IO_H[1]
0	1	1	1	1	1	CELL.SINGLE_H[1]
1	1	1	1	1	1	off

xc4000a CNR_SW switchbox INT muxes IMUX_IO_O1[1]
Bits					Destination
MAIN[12][3]	MAIN[8][3]	MAIN[11][3]	MAIN[9][3]	MAIN[10][3]	CELL.IMUX_IO_O1[1]
					Source
0	0	0	1	1	CELL.SINGLE_H[1]
0	0	1	0	1	CELL_N.LONG_V[0]
0	0	1	1	0	CELL_N.LONG_V[1]
0	1	1	1	1	CELL.SINGLE_H[0]
1	0	0	1	1	CELL.SINGLE_H[2]
1	0	1	0	1	CELL.SINGLE_H[3]
1	0	1	1	0	CELL_N.DOUBLE_V1[0]
1	1	1	1	1	CELL_N.DOUBLE_V0[1]

xc4000a CNR_SW switchbox INT muxes IMUX_IO_IK[1]
Bits					Destination
MAIN[14][3]	MAIN[17][3]	MAIN[15][3]	MAIN[16][3]	MAIN[13][3]	CELL.IMUX_IO_IK[1]
					Source
0	0	1	1	0	CELL_N.SINGLE_V[3]
0	0	1	1	1	CELL.DOUBLE_H0[0]
0	1	0	1	0	CELL_N.SINGLE_V[2]
0	1	0	1	1	CELL.LONG_H[3]
0	1	1	0	0	CELL_N.SINGLE_V[1]
0	1	1	0	1	CELL.LONG_H[4]
1	1	1	1	0	CELL_N.SINGLE_V[0]
1	1	1	1	1	CELL.DOUBLE_H1[1]

xc4000a CNR_SW switchbox INT muxes IMUX_BUFG_H
Bits	Destination
MAIN[15][5]	CELL.IMUX_BUFG_H
	Source
0	CELL.OUT_IO_CLKIN_W
1	off

xc4000a CNR_SW switchbox INT muxes IMUX_BUFG_V
Bits						Destination
MAIN[2][3]	MAIN[6][3]	MAIN[4][3]	MAIN[3][3]	MAIN[5][3]	MAIN[7][3]	CELL.IMUX_BUFG_V
						Source
0	0	0	1	1	1	CELL.DOUBLE_IO_S0[0]
0	0	1	0	1	1	CELL.DOUBLE_IO_W1[0]
0	0	1	1	0	1	CELL.DOUBLE_IO_W1[1]
0	1	1	1	1	0	CELL.OUT_IO_CLKIN_S
0	1	1	1	1	1	off
1	0	1	1	1	1	CELL.DOUBLE_IO_S0[1]

xc4000a CNR_SW switchbox INT muxes IMUX_RDBK_TRIG
Bits				Destination
MAIN[13][6]	MAIN[14][6]	MAIN[15][6]	MAIN[16][6]	CELL.IMUX_RDBK_TRIG
				Source
0	0	1	1	CELL.SINGLE_H[1]
0	1	0	1	CELL.SINGLE_H[2]
0	1	1	0	CELL.SINGLE_H[3]
1	1	1	1	CELL.SINGLE_H[0]

Bels PULLUP

xc4000a CNR_SW bel PULLUP pins
Pin	Direction	PULLUP_DEC_H[0]	PULLUP_DEC_H[1]	PULLUP_DEC_V[0]	PULLUP_DEC_V[1]
O	bidir	CELL.DEC_H[0]	CELL.DEC_H[1]	CELL.DEC_V[0]	CELL.DEC_V[1]

xc4000a CNR_SW bel PULLUP attribute bits
Attribute	PULLUP_DEC_H[0]	PULLUP_DEC_H[1]	PULLUP_DEC_V[0]	PULLUP_DEC_V[1]
ENABLE	!MAIN[2][4]	!MAIN[3][4]	!MAIN[2][5]	!MAIN[16][5]

Bels BUFG

xc4000a CNR_SW bel BUFG pins
Pin	Direction	BUFG_H	BUFG_V
I	in	CELL.IMUX_BUFG_H	CELL.IMUX_BUFG_V
O	out	CELL.BUFGLS[2]	CELL.BUFGLS[1]

xc4000a CNR_SW bel BUFG attribute bits
Attribute	BUFG_H	BUFG_V

Bels IBUF

xc4000a CNR_SW bel IBUF pins
Pin	Direction	MD0	MD2
I	out	CELL.OUT_MD0_I	CELL.OUT_IO_SN_I1[1]

xc4000a CNR_SW bel IBUF attribute bits
Attribute	MD0	MD2

Bels MD1

xc4000a CNR_SW bel MD1 pins
Pin	Direction	MD1
O	in	CELL.IMUX_IO_O1[1]
T	in	CELL.IMUX_IO_IK[1]

xc4000a CNR_SW bel MD1 attribute bits
Attribute	MD1
PULL	[enum: IO_PULL]
T_ENABLE	!MAIN[19][9]
O_ENABLE	!MAIN[20][9]

xc4000a CNR_SW enum IO_PULL
MD1.PULL	MAIN[20][5]	MAIN[19][5]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

Bels RDBK

xc4000a CNR_SW bel RDBK pins
Pin	Direction	RDBK
TRIG	in	CELL.IMUX_RDBK_TRIG
DATA	out	CELL.OUT_RDBK_DATA
RIP	out	CELL.OUT_IO_SN_I2[1]

xc4000a CNR_SW bel RDBK attribute bits
Attribute	RDBK
ENABLE	!MAIN[17][6]
READ_ABORT	!MAIN[18][0]
READ_CAPTURE	!MAIN[18][5]

Bels MISC_SW

xc4000a CNR_SW bel MISC_SW pins
Pin	Direction	MISC_SW

xc4000a CNR_SW bel MISC_SW attribute bits
Attribute	MISC_SW
TM_BOT	!MAIN[5][4]

Bel wires

xc4000a CNR_SW bel wires
Wire	Pins
CELL.DEC_H[0]	PULLUP_DEC_H[0].O
CELL.DEC_H[1]	PULLUP_DEC_H[1].O
CELL.DEC_V[0]	PULLUP_DEC_V[0].O
CELL.DEC_V[1]	PULLUP_DEC_V[1].O
CELL.BUFGLS[1]	BUFG_V.O
CELL.BUFGLS[2]	BUFG_H.O
CELL.IMUX_IO_O1[1]	MD1.O
CELL.IMUX_IO_IK[1]	MD1.T
CELL.IMUX_BUFG_H	BUFG_H.I
CELL.IMUX_BUFG_V	BUFG_V.I
CELL.IMUX_RDBK_TRIG	RDBK.TRIG
CELL.OUT_IO_SN_I1[1]	MD2.I
CELL.OUT_IO_SN_I2[1]	RDBK.RIP
CELL.OUT_MD0_I	MD0.I
CELL.OUT_RDBK_DATA	RDBK.DATA

Bitstream

xc4000a CNR_SW rect MAIN
Bit	Frame
Bit	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	MD1: ! O_ENABLE	MD1: ! T_ENABLE	-	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_S0[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W1[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W2[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W1[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_S0[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W2[1]	-	-	-	INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W1[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W2[0]	INT: mux CELL.DBUF_IO_V[1] bit 1	INT: mux CELL.DBUF_IO_V[1] bit 0	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W2[0]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W1[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W1[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_S0[0]
B8	-	-	-	-	-	INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W1[1]	INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_S0[1]	INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W2[1]	INT: !bipass CELL.DOUBLE_IO_S0[1] = CELL.DOUBLE_IO_W2[1]	INT: !pass CELL.DOUBLE_IO_W2[1] ← CELL.DBUF_IO_V[0]	INT: !pass CELL.DOUBLE_IO_W2[0] ← CELL.DBUF_IO_V[0]	INT: mux CELL.DBUF_IO_V[0] bit 1	INT: mux CELL.DBUF_IO_V[0] bit 0	INT: !pass CELL.DOUBLE_IO_S0[0] ← CELL.DBUF_IO_V[1]	INT: !pass CELL.DOUBLE_IO_S0[1] ← CELL.DBUF_IO_V[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_S0[0]	INT: !bipass CELL.DOUBLE_IO_S0[0] = CELL.DOUBLE_IO_W2[0]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_S0[0]	-	-	INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_MD0_I
B7	-	-	INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[1]	INT: !pass CELL.SINGLE_H[2] ← CELL.DEC_V[1]	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_RDBK_DATA	INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_RDBK_DATA	INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_RDBK_DATA	INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I1_S1	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1	INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1_S1	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_MD0_I	INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_MD0_I	INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[3] ← CELL.LONG_IO_V[1]	INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[1]	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[0]	INT: !pass CELL.SINGLE_H[0] ← CELL.LONG_IO_V[0]	INT: !pass CELL.SINGLE_H[1] ← CELL.DEC_V[0]	INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[0]
B6	-	-	-	RDBK: ! ENABLE	INT: mux CELL.IMUX_RDBK_TRIG bit 0	INT: mux CELL.IMUX_RDBK_TRIG bit 1	INT: mux CELL.IMUX_RDBK_TRIG bit 2	INT: mux CELL.IMUX_RDBK_TRIG bit 3	INT: mux CELL.LONG_H[4] bit 0	INT: mux CELL.LONG_H[4] bit 1	INT: mux CELL.LONG_H[4] bit 2	INT: mux CELL.LONG_H[4] bit 3	-	-	-	INT: mux CELL.LONG_H[3] bit 3	INT: mux CELL.LONG_H[3] bit 0	INT: mux CELL.LONG_H[3] bit 1	-	INT: mux CELL.LONG_H[3] bit 2	-
B5	MD1: PULL bit 1	MD1: PULL bit 0	RDBK: ! READ_CAPTURE	-	PULLUP_DEC_V[1]: ! ENABLE	INT: mux CELL.IMUX_BUFG_H bit 0	INT: mux CELL.LONG_IO_V[0] bit 3	INT: mux CELL.LONG_IO_V[0] bit 4	INT: mux CELL.LONG_IO_V[1] bit 3	INT: mux CELL.LONG_IO_V[1] bit 4	-	-	-	-	-	-	-	-	PULLUP_DEC_V[0]: ! ENABLE	-	-
B4	-	-	-	-	-	INT: mux CELL.LONG_IO_V[0] bit 1	INT: mux CELL.LONG_IO_V[1] bit 1	INT: mux CELL.LONG_IO_V[1] bit 2	INT: mux CELL.LONG_IO_V[1] bit 0	INT: mux CELL.LONG_IO_H[0] bit 1	INT: mux CELL.LONG_IO_H[1] bit 1	INT: mux CELL.LONG_IO_V[1] bit 5	INT: mux CELL.LONG_IO_H[1] bit 0	INT: mux CELL.LONG_IO_V[0] bit 5	INT: mux CELL.LONG_IO_H[0] bit 0	MISC_SW: ! TM_BOT	-	PULLUP_DEC_H[1]: ! ENABLE	PULLUP_DEC_H[0]: ! ENABLE	-	-
B3	-	INT: mux CELL.LONG_IO_V[0] bit 0	INT: mux CELL.LONG_IO_V[0] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 3	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 0	INT: mux CELL.IMUX_IO_O1[1] bit 4	INT: mux CELL.IMUX_IO_O1[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 0	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_BUFG_V bit 0	INT: mux CELL.IMUX_BUFG_V bit 4	INT: mux CELL.IMUX_BUFG_V bit 1	INT: mux CELL.IMUX_BUFG_V bit 3	INT: mux CELL.IMUX_BUFG_V bit 2	INT: mux CELL.IMUX_BUFG_V bit 5	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	RDBK: ! READ_ABORT	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile CNR_NW

Cells: 4

Switchbox INT

xc4000a CNR_NW switchbox INT muxes LONG_H[0]
Bits				Destination
MAIN[6][0]	MAIN[3][0]	MAIN[5][0]	MAIN[4][0]	CELL.LONG_H[0]
				Source
0	0	0	1	CELL.LONG_IO_V[0]
0	0	1	0	CELL.DEC_V[0]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000a CNR_NW switchbox INT muxes LONG_H[2]
Bits				Destination
MAIN[12][0]	MAIN[10][0]	MAIN[17][0]	MAIN[11][0]	CELL.LONG_H[2]
				Source
0	0	0	1	CELL.LONG_IO_V[1]
0	0	1	0	CELL.DEC_V[1]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000a CNR_NW switchbox INT muxes LONG_IO_H[0]
Bits		Destination
MAIN[13][1]	MAIN[6][1]	CELL.LONG_IO_H[0]
		Source
0	0	CELL.LONG_IO_V[1]
0	1	CELL.LONG_IO_V[0]
1	1	off

xc4000a CNR_NW switchbox INT muxes LONG_IO_H[1]
Bits		Destination
MAIN[10][1]	MAIN[8][1]	CELL.LONG_IO_H[1]
		Source
0	0	CELL.LONG_IO_V[0]
0	1	CELL.LONG_IO_V[1]
1	1	off

xc4000a CNR_NW switchbox INT muxes LONG_IO_V[0]
Bits				Destination
MAIN[7][1]	MAIN[15][1]	MAIN[18][2]	MAIN[19][2]	CELL.LONG_IO_V[0]
				Source
0	0	0	1	CELL.LONG_H[0]
0	0	1	0	CELL.LONG_IO_H[1]
0	1	1	1	CELL.LONG_IO_H[0]
1	1	1	1	off

xc4000a CNR_NW switchbox INT muxes LONG_IO_V[1]
Bits				Destination
MAIN[9][1]	MAIN[11][1]	MAIN[12][1]	MAIN[14][1]	CELL.LONG_IO_V[1]
				Source
0	0	0	1	CELL.LONG_H[2]
0	0	1	0	CELL.LONG_IO_H[0]
0	1	1	1	CELL.LONG_IO_H[1]
1	1	1	1	off

xc4000a CNR_NW switchbox INT muxes IMUX_BUFG_H
Bits						Destination
MAIN[2][2]	MAIN[6][2]	MAIN[4][2]	MAIN[3][2]	MAIN[5][2]	MAIN[7][2]	CELL.IMUX_BUFG_H
						Source
0	0	0	1	1	1	CELL.DOUBLE_IO_N1[0]
0	0	1	0	1	1	CELL.DOUBLE_IO_N2[0]
0	0	1	1	0	1	CELL.DOUBLE_IO_N2[1]
0	1	1	1	1	0	CELL.OUT_IO_CLKIN_W
0	1	1	1	1	1	off
1	0	1	1	1	1	CELL.DOUBLE_IO_N1[1]

xc4000a CNR_NW switchbox INT muxes IMUX_BUFG_V
Bits	Destination
MAIN[16][0]	CELL.IMUX_BUFG_V
	Source
0	CELL.OUT_IO_CLKIN_N
1	off

xc4000a CNR_NW switchbox INT muxes IMUX_BSCAN_TDO1
Bits					Destination
MAIN[8][2]	MAIN[10][2]	MAIN[12][2]	MAIN[9][2]	MAIN[11][2]	CELL.IMUX_BSCAN_TDO1
					Source
0	0	0	1	1	CELL_E.LONG_V[1]
0	0	1	1	1	CELL_E.DOUBLE_V1[0]
0	1	0	0	1	CELL_E.LONG_V[0]
0	1	0	1	0	CELL_S.SINGLE_H[1]
0	1	1	0	1	CELL_S.SINGLE_H[3]
0	1	1	1	0	CELL_S.SINGLE_H[2]
1	1	0	1	1	CELL_S.SINGLE_H[0]
1	1	1	1	1	CELL_E.DOUBLE_V0[1]

xc4000a CNR_NW switchbox INT muxes IMUX_BSCAN_TDO2
Bits					Destination
MAIN[14][2]	MAIN[16][2]	MAIN[15][2]	MAIN[13][2]	MAIN[17][2]	CELL.IMUX_BSCAN_TDO2
					Source
0	0	1	0	1	CELL_E.SINGLE_V[1]
0	0	1	1	1	CELL.LONG_H[0]
0	1	0	0	1	CELL_E.SINGLE_V[2]
0	1	0	1	1	CELL.LONG_H[2]
0	1	1	0	0	CELL_E.SINGLE_V[3]
0	1	1	1	0	CELL_S.DOUBLE_H0[1]
1	1	1	0	1	CELL_E.SINGLE_V[0]
1	1	1	1	1	CELL_S.DOUBLE_H1[0]

Bels PULLUP

xc4000a CNR_NW bel PULLUP pins
Pin	Direction	PULLUP_DEC_H[0]	PULLUP_DEC_H[1]	PULLUP_DEC_V[0]	PULLUP_DEC_V[1]
O	bidir	CELL.DEC_H[0]	CELL.DEC_H[1]	CELL.DEC_V[0]	CELL.DEC_V[1]

xc4000a CNR_NW bel PULLUP attribute bits
Attribute	PULLUP_DEC_H[0]	PULLUP_DEC_H[1]	PULLUP_DEC_V[0]	PULLUP_DEC_V[1]
ENABLE	!MAIN[3][1]	!MAIN[2][1]	!MAIN[2][0]	!MAIN[18][0]

Bels BUFG

xc4000a CNR_NW bel BUFG pins
Pin	Direction	BUFG_H	BUFG_V
I	in	CELL.IMUX_BUFG_H	CELL.IMUX_BUFG_V
O	out	CELL.BUFGLS[7]	CELL.BUFGLS[0]

xc4000a CNR_NW bel BUFG attribute bits
Attribute	BUFG_H	BUFG_V

Bels BSCAN

xc4000a CNR_NW bel BSCAN pins
Pin	Direction	BSCAN
TDO1	in	CELL.IMUX_BSCAN_TDO1
TDO2	in	CELL.IMUX_BSCAN_TDO2
DRCK	out	CELL.OUT_IO_SN_I2[1]
IDLE	out	CELL.OUT_IO_WE_I2[1]
SEL1	out	CELL.OUT_IO_WE_I1[1]
SEL2	out	CELL.OUT_IO_SN_I1[1]

xc4000a CNR_NW bel BSCAN attribute bits
Attribute	BSCAN
ENABLE	MAIN[19][0]

Bels MISC_NW

xc4000a CNR_NW bel MISC_NW pins
Pin	Direction	MISC_NW

xc4000a CNR_NW bel MISC_NW attribute bits
Attribute	MISC_NW
IO_ISTD	[enum: IO_STD]
TM_LEFT	!MAIN[4][1]
TM_TOP	!MAIN[5][1]

xc4000a CNR_NW enum IO_STD
MISC_NW.IO_ISTD	MAIN[18][5]
CMOS	0
TTL	1

Bel wires

xc4000a CNR_NW bel wires
Wire	Pins
CELL.DEC_H[0]	PULLUP_DEC_H[0].O
CELL.DEC_H[1]	PULLUP_DEC_H[1].O
CELL.DEC_V[0]	PULLUP_DEC_V[0].O
CELL.DEC_V[1]	PULLUP_DEC_V[1].O
CELL.BUFGLS[0]	BUFG_V.O
CELL.BUFGLS[7]	BUFG_H.O
CELL.IMUX_BUFG_H	BUFG_H.I
CELL.IMUX_BUFG_V	BUFG_V.I
CELL.IMUX_BSCAN_TDO1	BSCAN.TDO1
CELL.IMUX_BSCAN_TDO2	BSCAN.TDO2
CELL.OUT_IO_SN_I1[1]	BSCAN.SEL2
CELL.OUT_IO_SN_I2[1]	BSCAN.DRCK
CELL.OUT_IO_WE_I1[1]	BSCAN.SEL1
CELL.OUT_IO_WE_I2[1]	BSCAN.IDLE

Bitstream

xc4000a CNR_NW rect MAIN
Bit	Frame
Bit	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B5	-	-	MISC_NW: IO_ISTD bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	INT: mux CELL.LONG_IO_V[0] bit 0	INT: mux CELL.LONG_IO_V[0] bit 1	INT: mux CELL.IMUX_BSCAN_TDO2 bit 0	INT: mux CELL.IMUX_BSCAN_TDO2 bit 3	INT: mux CELL.IMUX_BSCAN_TDO2 bit 2	INT: mux CELL.IMUX_BSCAN_TDO2 bit 4	INT: mux CELL.IMUX_BSCAN_TDO2 bit 1	INT: mux CELL.IMUX_BSCAN_TDO1 bit 2	INT: mux CELL.IMUX_BSCAN_TDO1 bit 0	INT: mux CELL.IMUX_BSCAN_TDO1 bit 3	INT: mux CELL.IMUX_BSCAN_TDO1 bit 1	INT: mux CELL.IMUX_BSCAN_TDO1 bit 4	INT: mux CELL.IMUX_BUFG_H bit 0	INT: mux CELL.IMUX_BUFG_H bit 4	INT: mux CELL.IMUX_BUFG_H bit 1	INT: mux CELL.IMUX_BUFG_H bit 3	INT: mux CELL.IMUX_BUFG_H bit 2	INT: mux CELL.IMUX_BUFG_H bit 5	-	-
B1	-	-	-	-	-	INT: mux CELL.LONG_IO_V[0] bit 2	INT: mux CELL.LONG_IO_V[1] bit 0	INT: mux CELL.LONG_IO_H[0] bit 1	INT: mux CELL.LONG_IO_V[1] bit 1	INT: mux CELL.LONG_IO_V[1] bit 2	INT: mux CELL.LONG_IO_H[1] bit 1	INT: mux CELL.LONG_IO_V[1] bit 3	INT: mux CELL.LONG_IO_H[1] bit 0	INT: mux CELL.LONG_IO_V[0] bit 3	INT: mux CELL.LONG_IO_H[0] bit 0	MISC_NW: ! TM_TOP	MISC_NW: ! TM_LEFT	PULLUP_DEC_H[0]: ! ENABLE	PULLUP_DEC_H[1]: ! ENABLE	-	-
B0	-	BSCAN: ENABLE	PULLUP_DEC_V[1]: ! ENABLE	INT: mux CELL.LONG_H[2] bit 1	INT: mux CELL.IMUX_BUFG_V bit 0	-	-	-	INT: mux CELL.LONG_H[2] bit 3	INT: mux CELL.LONG_H[2] bit 0	INT: mux CELL.LONG_H[2] bit 2	-	-	-	INT: mux CELL.LONG_H[0] bit 3	INT: mux CELL.LONG_H[0] bit 1	INT: mux CELL.LONG_H[0] bit 0	INT: mux CELL.LONG_H[0] bit 2	PULLUP_DEC_V[0]: ! ENABLE	-	-

Tile CNR_SE

Cells: 1

Switchbox INT

xc4000a CNR_SE switchbox INT programmable buffers
Destination	Source	Bit
LONG_H[3]	SINGLE_V[2]	!MAIN[18][5]
LONG_H[4]	SINGLE_V[3]	!MAIN[21][6]
LONG_V[0]	SINGLE_H_E[0]	!MAIN[27][6]
LONG_V[1]	SINGLE_H_E[1]	!MAIN[16][6]
LONG_V[2]	SINGLE_H[2]	!MAIN[15][6]
LONG_V[3]	SINGLE_H[3]	!MAIN[10][6]

xc4000a CNR_SE switchbox INT pass gates
Destination	Source	Bit
SINGLE_H[0]	LONG_IO_V[0]	!MAIN[14][7]
SINGLE_H[0]	DEC_V[0]	!MAIN[0][7]
SINGLE_H[0]	OUT_IO_WE_I2_S1	!MAIN[14][6]
SINGLE_H[0]	OUT_STARTUP_Q1Q4	!MAIN[11][7]
SINGLE_H[1]	LONG_IO_V[1]	!MAIN[12][6]
SINGLE_H[1]	DEC_V[1]	!MAIN[15][7]
SINGLE_H[1]	OUT_IO_WE_I1_S1	!MAIN[7][7]
SINGLE_H[1]	OUT_STARTUP_Q3	!MAIN[17][7]
SINGLE_H[2]	LONG_V[2]	!MAIN[25][7]
SINGLE_H[2]	LONG_IO_V[0]	!MAIN[13][7]
SINGLE_H[2]	DEC_V[0]	!MAIN[1][7]
SINGLE_H[2]	OUT_IO_WE_I2_S1	!MAIN[13][6]
SINGLE_H[2]	OUT_STARTUP_Q1Q4	!MAIN[10][7]
SINGLE_H[3]	LONG_V[3]	!MAIN[19][6]
SINGLE_H[3]	LONG_IO_V[1]	!MAIN[11][6]
SINGLE_H[3]	DEC_V[1]	!MAIN[16][7]
SINGLE_H[3]	OUT_IO_WE_I1_S1	!MAIN[8][7]
SINGLE_H[3]	OUT_STARTUP_Q3	!MAIN[18][6]
SINGLE_H_E[0]	LONG_V[0]	!MAIN[30][6]
SINGLE_H_E[1]	LONG_V[1]	!MAIN[29][7]
SINGLE_V[0]	LONG_IO_H[0]	!MAIN[31][5]
SINGLE_V[0]	DEC_H[1]	!MAIN[28][5]
SINGLE_V[0]	OUT_IO_SN_I2_E1	!MAIN[29][5]
SINGLE_V[0]	OUT_STARTUP_Q2	!MAIN[30][5]
SINGLE_V[1]	LONG_IO_H[1]	!MAIN[25][4]
SINGLE_V[1]	DEC_H[0]	!MAIN[22][4]
SINGLE_V[1]	OUT_IO_SN_I1_E1	!MAIN[24][4]
SINGLE_V[1]	OUT_STARTUP_DONEIN	!MAIN[23][4]
SINGLE_V[2]	LONG_H[3]	!MAIN[30][7]
SINGLE_V[2]	LONG_IO_H[0]	!MAIN[31][4]
SINGLE_V[2]	DEC_H[1]	!MAIN[27][4]
SINGLE_V[2]	OUT_IO_SN_I2_E1	!MAIN[29][4]
SINGLE_V[2]	OUT_STARTUP_Q2	!MAIN[30][4]
SINGLE_V[3]	LONG_H[4]	!MAIN[24][7]
SINGLE_V[3]	LONG_IO_H[1]	!MAIN[20][4]
SINGLE_V[3]	DEC_H[0]	!MAIN[19][5]
SINGLE_V[3]	OUT_IO_SN_I1_E1	!MAIN[17][5]
SINGLE_V[3]	OUT_STARTUP_DONEIN	!MAIN[21][4]
DOUBLE_H0[0]	OUT_STARTUP_Q1Q4	!MAIN[18][7]
DOUBLE_H0[1]	OUT_IO_WE_I2_S1	!MAIN[12][7]
DOUBLE_H1[0]	OUT_IO_WE_I1_S1	!MAIN[9][7]
DOUBLE_H1[1]	OUT_STARTUP_Q3	!MAIN[17][6]
DOUBLE_V0[0]	OUT_IO_SN_I1_E1	!MAIN[28][4]
DOUBLE_V0[1]	OUT_STARTUP_DONEIN	!MAIN[19][4]
DOUBLE_V1[0]	OUT_STARTUP_Q2	!MAIN[26][4]
DOUBLE_V1[1]	OUT_IO_SN_I2_E1	!MAIN[16][5]
DOUBLE_IO_S1[0]	DBUF_IO_V[1]	!MAIN[11][8]
DOUBLE_IO_S1[1]	DBUF_IO_V[1]	!MAIN[12][8]
DOUBLE_IO_S2[0]	DBUF_IO_H[0]	!MAIN[12][4]
DOUBLE_IO_S2[1]	DBUF_IO_H[0]	!MAIN[13][4]
DOUBLE_IO_E0[0]	DBUF_IO_V[0]	!MAIN[10][8]
DOUBLE_IO_E0[1]	DBUF_IO_V[0]	!MAIN[9][8]
DOUBLE_IO_E1[0]	DBUF_IO_H[1]	!MAIN[18][4]
DOUBLE_IO_E1[1]	DBUF_IO_H[1]	!MAIN[16][4]

xc4000a CNR_SE switchbox INT bidirectional pass gates
Side A	Side B	Bit
SINGLE_H[0]	SINGLE_H_E[0]	!MAIN[28][9]
SINGLE_H[0]	SINGLE_V[0]	!MAIN[27][9]
SINGLE_H[0]	SINGLE_V_S[0]	!MAIN[26][9]
SINGLE_H[0]	DOUBLE_IO_S1[0]	!MAIN[13][8]
SINGLE_H[0]	DOUBLE_IO_E0[0]	!MAIN[13][9]
SINGLE_H[1]	SINGLE_H_E[1]	!MAIN[18][8]
SINGLE_H[1]	SINGLE_V[1]	!MAIN[19][8]
SINGLE_H[1]	SINGLE_V_S[1]	!MAIN[20][8]
SINGLE_H[1]	DOUBLE_IO_E1[0]	!MAIN[12][9]
SINGLE_H[2]	SINGLE_H_E[2]	!MAIN[27][8]
SINGLE_H[2]	SINGLE_V[2]	!MAIN[26][8]
SINGLE_H[2]	SINGLE_V_S[2]	!MAIN[25][8]
SINGLE_H[2]	DOUBLE_IO_S1[1]	!MAIN[6][8]
SINGLE_H[2]	DOUBLE_IO_E0[1]	!MAIN[7][8]
SINGLE_H[3]	SINGLE_H_E[3]	!MAIN[25][6]
SINGLE_H[3]	SINGLE_V[3]	!MAIN[26][7]
SINGLE_H[3]	SINGLE_V_S[3]	!MAIN[26][6]
SINGLE_H[3]	DOUBLE_IO_E1[1]	!MAIN[5][8]
SINGLE_H_E[0]	SINGLE_V[0]	!MAIN[30][9]
SINGLE_H_E[0]	SINGLE_V_S[0]	!MAIN[29][9]
SINGLE_H_E[1]	SINGLE_V[1]	!MAIN[22][8]
SINGLE_H_E[1]	SINGLE_V_S[1]	!MAIN[21][8]
SINGLE_H_E[2]	SINGLE_V[2]	!MAIN[29][8]
SINGLE_H_E[2]	SINGLE_V_S[2]	!MAIN[28][8]
SINGLE_H_E[3]	SINGLE_V[3]	!MAIN[28][7]
SINGLE_H_E[3]	SINGLE_V_S[3]	!MAIN[24][6]
SINGLE_V[0]	SINGLE_V_S[0]	!MAIN[31][9]
SINGLE_V[0]	DOUBLE_IO_S1[0]	!MAIN[19][3]
SINGLE_V[1]	SINGLE_V_S[1]	!MAIN[23][8]
SINGLE_V[1]	DOUBLE_IO_S2[0]	!MAIN[28][3]
SINGLE_V[1]	DOUBLE_IO_E1[0]	!MAIN[26][3]
SINGLE_V[2]	SINGLE_V_S[2]	!MAIN[30][8]
SINGLE_V[2]	DOUBLE_IO_S1[1]	!MAIN[6][4]
SINGLE_V[3]	SINGLE_V_S[3]	!MAIN[27][7]
SINGLE_V[3]	DOUBLE_IO_S2[1]	!MAIN[18][3]
SINGLE_V[3]	DOUBLE_IO_E1[1]	!MAIN[13][3]
DOUBLE_H0[0]	DOUBLE_H2[0]	!MAIN[20][9]
DOUBLE_H0[0]	DOUBLE_V0[0]	!MAIN[21][9]
DOUBLE_H0[0]	DOUBLE_V2[0]	!MAIN[19][9]
DOUBLE_H0[0]	DOUBLE_IO_S1[1]	!MAIN[7][9]
DOUBLE_H0[0]	DOUBLE_IO_E0[1]	!MAIN[8][9]
DOUBLE_H0[0]	DOUBLE_IO_E1[1]	!MAIN[6][9]
DOUBLE_H0[1]	DOUBLE_H2[1]	!MAIN[19][7]
DOUBLE_H0[1]	DOUBLE_V0[1]	!MAIN[20][7]
DOUBLE_H0[1]	DOUBLE_V2[1]	!MAIN[20][6]
DOUBLE_H0[1]	DOUBLE_IO_S1[0]	!MAIN[15][8]
DOUBLE_H0[1]	DOUBLE_IO_E0[0]	!MAIN[16][9]
DOUBLE_H0[1]	DOUBLE_IO_E1[0]	!MAIN[17][9]
DOUBLE_H1[0]	DOUBLE_IO_S1[0]	!MAIN[17][8]
DOUBLE_H1[0]	DOUBLE_IO_E0[0]	!MAIN[16][8]
DOUBLE_H1[0]	DOUBLE_IO_E1[0]	!MAIN[18][9]
DOUBLE_H1[1]	DOUBLE_IO_S1[1]	!MAIN[3][9]
DOUBLE_H1[1]	DOUBLE_IO_E0[1]	!MAIN[5][9]
DOUBLE_H1[1]	DOUBLE_IO_E1[1]	!MAIN[4][9]
DOUBLE_H2[0]	DOUBLE_V0[0]	!MAIN[23][9]
DOUBLE_H2[0]	DOUBLE_V2[0]	!MAIN[24][9]
DOUBLE_H2[1]	DOUBLE_V0[1]	!MAIN[22][7]
DOUBLE_H2[1]	DOUBLE_V2[1]	!MAIN[23][7]
DOUBLE_V0[0]	DOUBLE_V2[0]	!MAIN[22][9]
DOUBLE_V0[0]	DOUBLE_IO_S1[1]	!MAIN[7][4]
DOUBLE_V0[0]	DOUBLE_IO_S2[1]	!MAIN[16][3]
DOUBLE_V0[0]	DOUBLE_IO_E1[1]	!MAIN[14][3]
DOUBLE_V0[1]	DOUBLE_V2[1]	!MAIN[21][7]
DOUBLE_V0[1]	DOUBLE_IO_S1[0]	!MAIN[21][3]
DOUBLE_V0[1]	DOUBLE_IO_S2[0]	!MAIN[27][3]
DOUBLE_V0[1]	DOUBLE_IO_E1[0]	!MAIN[24][3]
DOUBLE_V1[0]	DOUBLE_IO_S1[0]	!MAIN[22][3]
DOUBLE_V1[0]	DOUBLE_IO_S2[0]	!MAIN[29][3]
DOUBLE_V1[0]	DOUBLE_IO_E1[0]	!MAIN[25][3]
DOUBLE_V1[1]	DOUBLE_IO_S1[1]	!MAIN[8][4]
DOUBLE_V1[1]	DOUBLE_IO_S2[1]	!MAIN[17][3]
DOUBLE_V1[1]	DOUBLE_IO_E1[1]	!MAIN[9][4]
DOUBLE_IO_S1[0]	DOUBLE_IO_E0[0]	!MAIN[14][8]
DOUBLE_IO_S1[1]	DOUBLE_IO_E0[1]	!MAIN[8][8]
DOUBLE_IO_S2[0]	DOUBLE_IO_E1[0]	!MAIN[23][3]
DOUBLE_IO_S2[1]	DOUBLE_IO_E1[1]	!MAIN[15][3]

xc4000a CNR_SE switchbox INT muxes DBUF_IO_H[0]
Bits		Destination
MAIN[15][4]	MAIN[14][4]	DBUF_IO_H[0]
		Source
0	0	DOUBLE_IO_E1[1]
1	1	DOUBLE_IO_E1[0]

xc4000a CNR_SE switchbox INT muxes DBUF_IO_H[1]
Bits		Destination
MAIN[11][4]	MAIN[10][4]	DBUF_IO_H[1]
		Source
0	0	DOUBLE_IO_S2[0]
1	1	DOUBLE_IO_S2[1]

xc4000a CNR_SE switchbox INT muxes DBUF_IO_V[0]
Bits		Destination
MAIN[10][9]	MAIN[9][9]	DBUF_IO_V[0]
		Source
0	0	DOUBLE_IO_S1[0]
1	1	DOUBLE_IO_S1[1]

xc4000a CNR_SE switchbox INT muxes DBUF_IO_V[1]
Bits		Destination
MAIN[15][9]	MAIN[14][9]	DBUF_IO_V[1]
		Source
0	0	DOUBLE_IO_E0[1]
1	1	DOUBLE_IO_E0[0]

xc4000a CNR_SE switchbox INT muxes LONG_H[3]
Bits				Destination
MAIN[20][2]	MAIN[15][2]	MAIN[16][2]	MAIN[19][2]	LONG_H[3]
				Source
0	0	0	1	LONG_IO_V[0]
0	0	1	0	DEC_V[1]
0	1	1	1	OUT_STARTUP_Q3
1	1	1	1	off

xc4000a CNR_SE switchbox INT muxes LONG_H[4]
Bits				Destination
MAIN[3][3]	MAIN[5][2]	MAIN[7][2]	MAIN[6][2]	LONG_H[4]
				Source
0	0	0	1	LONG_IO_V[1]
0	0	1	0	DEC_V[0]
0	1	1	1	OUT_STARTUP_Q3
1	1	1	1	off

xc4000a CNR_SE switchbox INT muxes LONG_V[0]
Bits				Destination
MAIN[27][5]	MAIN[24][5]	MAIN[25][5]	MAIN[26][5]	LONG_V[0]
				Source
0	0	0	1	LONG_IO_H[0]
0	0	1	0	DEC_H[0]
0	1	1	1	OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000a CNR_SE switchbox INT muxes LONG_V[1]
Bits				Destination
MAIN[15][5]	MAIN[13][5]	MAIN[14][5]	MAIN[17][4]	LONG_V[1]
				Source
0	0	0	1	LONG_IO_H[1]
0	0	1	0	DEC_H[1]
0	1	1	1	OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000a CNR_SE switchbox INT muxes LONG_V[2]
Bits				Destination
MAIN[11][5]	MAIN[9][5]	MAIN[12][5]	MAIN[10][5]	LONG_V[2]
				Source
0	0	0	1	LONG_IO_H[0]
0	0	1	0	DEC_H[0]
0	1	1	1	OUT_STARTUP_DONEIN
1	1	1	1	off

xc4000a CNR_SE switchbox INT muxes LONG_V[3]
Bits				Destination
MAIN[23][5]	MAIN[20][5]	MAIN[21][5]	MAIN[22][5]	LONG_V[3]
				Source
0	0	0	1	LONG_IO_H[1]
0	0	1	0	DEC_H[1]
0	1	1	1	OUT_STARTUP_DONEIN
1	1	1	1	off

xc4000a CNR_SE switchbox INT muxes LONG_IO_H[0]
Bits							Destination
MAIN[1][3]	MAIN[4][3]	MAIN[6][3]	MAIN[5][3]	MAIN[7][3]	MAIN[5][5]	MAIN[4][5]	LONG_IO_H[0]
							Source
0	0	0	1	1	1	1	SINGLE_V[2]
0	0	1	0	1	1	1	LONG_V[0]
0	0	1	1	0	1	1	LONG_V[2]
0	1	1	1	1	1	1	SINGLE_V[0]
1	1	1	1	1	0	0	LONG_IO_V[0]
1	1	1	1	1	0	1	LONG_IO_V[1]
1	1	1	1	1	1	1	off

xc4000a CNR_SE switchbox INT muxes LONG_IO_H[1]
Bits							Destination
MAIN[8][3]	MAIN[9][3]	MAIN[10][3]	MAIN[12][3]	MAIN[11][3]	MAIN[6][5]	MAIN[8][5]	LONG_IO_H[1]
							Source
0	0	0	1	1	1	1	SINGLE_V[3]
0	0	1	0	1	1	1	LONG_V[1]
0	0	1	1	0	1	1	LONG_V[3]
0	1	1	1	1	1	1	SINGLE_V[1]
1	1	1	1	1	0	0	LONG_IO_V[1]
1	1	1	1	1	0	1	LONG_IO_V[0]
1	1	1	1	1	1	1	off

xc4000a CNR_SE switchbox INT muxes LONG_IO_V[0]
Bits						Destination
MAIN[4][6]	MAIN[2][7]	MAIN[3][7]	MAIN[2][8]	MAIN[5][7]	MAIN[4][7]	LONG_IO_V[0]
						Source
0	0	0	1	1	1	SINGLE_H[0]
0	0	1	0	1	1	LONG_H[3]
0	0	1	1	0	1	LONG_IO_H[0]
0	0	1	1	1	0	LONG_IO_H[1]
0	1	1	1	1	1	SINGLE_H[2]
1	1	1	1	1	1	off

xc4000a CNR_SE switchbox INT muxes LONG_IO_V[1]
Bits						Destination
MAIN[5][6]	MAIN[6][7]	MAIN[9][6]	MAIN[7][6]	MAIN[6][6]	MAIN[8][6]	LONG_IO_V[1]
						Source
0	0	0	1	1	1	SINGLE_H[1]
0	0	1	0	1	1	LONG_H[4]
0	0	1	1	0	1	LONG_IO_H[0]
0	0	1	1	1	0	LONG_IO_H[1]
0	1	1	1	1	1	SINGLE_H[3]
1	1	1	1	1	1	off

xc4000a CNR_SE switchbox INT muxes IMUX_STARTUP_CLK
Bits				Destination
MAIN[28][2]	MAIN[31][3]	MAIN[30][3]	MAIN[31][2]	IMUX_STARTUP_CLK
				Source
0	0	1	1	SINGLE_V[0]
0	1	0	1	SINGLE_V[2]
0	1	1	0	SINGLE_V[3]
1	1	1	1	SINGLE_V[1]

xc4000a CNR_SE switchbox INT muxes IMUX_STARTUP_GSR
Bits					Destination
MAIN[8][2]	MAIN[9][2]	MAIN[10][2]	MAIN[11][2]	MAIN[12][2]	IMUX_STARTUP_GSR
					Source
0	0	0	1	1	SINGLE_H[1]
0	0	1	0	1	SINGLE_H[3]
0	0	1	1	0	DOUBLE_V0[0]
0	1	1	1	1	SINGLE_H[0]
1	0	0	1	1	LONG_V[2]
1	0	1	0	1	LONG_V[3]
1	0	1	1	0	DOUBLE_V1[1]
1	1	1	1	1	SINGLE_H[2]

xc4000a CNR_SE switchbox INT muxes IMUX_STARTUP_GTS
Bits					Destination
MAIN[26][2]	MAIN[29][2]	MAIN[25][2]	MAIN[30][2]	MAIN[27][2]	IMUX_STARTUP_GTS
					Source
0	0	0	1	1	LONG_H[3]
0	0	1	1	1	SINGLE_V[0]
0	1	0	0	1	SINGLE_V[3]
0	1	0	1	0	LONG_H[4]
0	1	1	0	1	SINGLE_V[2]
0	1	1	1	0	DOUBLE_H1[0]
1	1	0	1	1	SINGLE_V[1]
1	1	1	1	1	DOUBLE_H0[1]

xc4000a CNR_SE switchbox INT muxes IMUX_READCLK_I
Bits				Destination
MAIN[13][2]	MAIN[17][2]	MAIN[14][2]	MAIN[18][2]	IMUX_READCLK_I
				Source
0	0	1	1	SINGLE_H[1]
0	1	0	1	SINGLE_H[2]
0	1	1	0	SINGLE_H[3]
1	1	1	1	SINGLE_H[0]

xc4000a CNR_SE switchbox INT muxes IMUX_BUFG_H
Bits						Destination
MAIN[21][2]	MAIN[20][3]	MAIN[24][2]	MAIN[22][2]	MAIN[23][2]	MAIN[21][1]	IMUX_BUFG_H
						Source
0	0	0	1	1	1	DOUBLE_IO_S1[0]
0	0	1	0	1	1	DOUBLE_IO_S1[1]
0	0	1	1	0	1	DOUBLE_IO_E1[0]
0	1	1	1	1	0	OUT_IO_CLKIN_E
0	1	1	1	1	1	off
1	0	1	1	1	1	DOUBLE_IO_E1[1]

xc4000a CNR_SE switchbox INT muxes IMUX_BUFG_V
Bits	Destination
MAIN[2][3]	IMUX_BUFG_V
	Source
0	OUT_IO_CLKIN_S
1	off

Bels PULLUP

xc4000a CNR_SE bel PULLUP pins
Pin	Direction	PULLUP_DEC_H[0]	PULLUP_DEC_H[1]	PULLUP_DEC_V[0]	PULLUP_DEC_V[1]
O	bidir	DEC_H[0]	DEC_H[1]	DEC_V[0]	DEC_V[1]

xc4000a CNR_SE bel PULLUP attribute bits
Attribute	PULLUP_DEC_H[0]	PULLUP_DEC_H[1]	PULLUP_DEC_V[0]	PULLUP_DEC_V[1]
ENABLE	!MAIN[5][4]	!MAIN[2][5]	!MAIN[3][5]	!MAIN[22][1]

Bels BUFG

xc4000a CNR_SE bel BUFG pins
Pin	Direction	BUFG_H	BUFG_V
I	in	IMUX_BUFG_H	IMUX_BUFG_V
O	out	BUFGLS[3]	BUFGLS[4]

xc4000a CNR_SE bel BUFG attribute bits
Attribute	BUFG_H	BUFG_V

Bels STARTUP

xc4000a CNR_SE bel STARTUP pins
Pin	Direction	STARTUP
CLK	in	IMUX_STARTUP_CLK
GSR	in	IMUX_STARTUP_GSR invert by !MAIN[31][0]
GTS	in	IMUX_STARTUP_GTS invert by !MAIN[23][0]
DONEIN	out	OUT_STARTUP_DONEIN
Q1Q4	out	OUT_STARTUP_Q1Q4
Q2	out	OUT_STARTUP_Q2
Q3	out	OUT_STARTUP_Q3

xc4000a CNR_SE bel STARTUP attribute bits
Attribute	STARTUP
GSR_ENABLE	!MAIN[31][1]
GTS_ENABLE	!MAIN[21][0]
CONFIG_RATE	[enum: CONFIG_RATE]
CRC	!MAIN[0][1]
DONE_TIMING	[enum: DONE_TIMING]
GTS_TIMING	[enum: GTS_GSR_TIMING]
GSR_TIMING	[enum: GTS_GSR_TIMING]
SYNC_TO_DONE	!MAIN[24][0]
MUX_CLK	[enum: STARTUP_MUX_CLK]

xc4000a CNR_SE enum CONFIG_RATE
STARTUP.CONFIG_RATE	MAIN[0][0]
SLOW	1
FAST	0

xc4000a CNR_SE enum DONE_TIMING
STARTUP.DONE_TIMING	MAIN[25][0]	MAIN[26][0]
Q0	1	1
Q1Q4	0	1
Q2	0	0
Q3	1	0

xc4000a CNR_SE enum GTS_GSR_TIMING
STARTUP.GTS_TIMING	MAIN[30][0]	MAIN[29][1]
Q1Q4	1	1
Q2	0	1
Q3	0	0
DONE_IN	1	0

xc4000a CNR_SE enum GTS_GSR_TIMING
STARTUP.GSR_TIMING	MAIN[29][0]	MAIN[27][0]
Q1Q4	0	1
Q2	1	1
Q3	1	0
DONE_IN	0	0

xc4000a CNR_SE enum STARTUP_MUX_CLK
STARTUP.MUX_CLK	MAIN[23][1]
CCLK	0
USERCLK	1

Bels READCLK

xc4000a CNR_SE bel READCLK pins
Pin	Direction	READCLK
I	in	IMUX_READCLK_I

Bels MISC_SE

xc4000a CNR_SE bel MISC_SE pins
Pin	Direction	MISC_SE

xc4000a CNR_SE bel MISC_SE attribute bits
Attribute	MISC_SE
DONE_PULLUP	!MAIN[22][0]
OSC_ENABLE	MAIN[0][9]
OSC_MUX_OUT0	[enum: OSC_MUX_OUT]
OSC_MUX_OUT1	[enum: OSC_MUX_OUT]
TCTEST	!MAIN[0][3]

xc4000a CNR_SE enum OSC_MUX_OUT
MISC_SE.OSC_MUX_OUT0	MAIN[0][5]	MAIN[1][9]	MAIN[2][9]	MAIN[1][6]
MISC_SE.OSC_MUX_OUT1	MAIN[1][5]	MAIN[1][8]	MAIN[3][6]	MAIN[2][6]
F500K	0	0	1	1
F16K	0	1	0	1
F490	0	1	1	0
F15	1	1	1	1

Bel wires

xc4000a CNR_SE bel wires
Wire	Pins
DEC_H[0]	PULLUP_DEC_H[0].O
DEC_H[1]	PULLUP_DEC_H[1].O
DEC_V[0]	PULLUP_DEC_V[0].O
DEC_V[1]	PULLUP_DEC_V[1].O
BUFGLS[3]	BUFG_H.O
BUFGLS[4]	BUFG_V.O
IMUX_STARTUP_CLK	STARTUP.CLK
IMUX_STARTUP_GSR	STARTUP.GSR
IMUX_STARTUP_GTS	STARTUP.GTS
IMUX_READCLK_I	READCLK.I
IMUX_BUFG_H	BUFG_H.I
IMUX_BUFG_V	BUFG_V.I
OUT_STARTUP_DONEIN	STARTUP.DONEIN
OUT_STARTUP_Q1Q4	STARTUP.Q1Q4
OUT_STARTUP_Q2	STARTUP.Q2
OUT_STARTUP_Q3	STARTUP.Q3

Bitstream

xc4000a CNR_SE rect MAIN
Bit	Frame
Bit	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	INT: !bipass SINGLE_V[0] = SINGLE_V_S[0]	INT: !bipass SINGLE_H_E[0] = SINGLE_V[0]	INT: !bipass SINGLE_H_E[0] = SINGLE_V_S[0]	INT: !bipass SINGLE_H[0] = SINGLE_H_E[0]	INT: !bipass SINGLE_H[0] = SINGLE_V[0]	INT: !bipass SINGLE_H[0] = SINGLE_V_S[0]	-	INT: !bipass DOUBLE_H2[0] = DOUBLE_V2[0]	INT: !bipass DOUBLE_H2[0] = DOUBLE_V0[0]	INT: !bipass DOUBLE_V0[0] = DOUBLE_V2[0]	INT: !bipass DOUBLE_H0[0] = DOUBLE_V0[0]	INT: !bipass DOUBLE_H0[0] = DOUBLE_H2[0]	INT: !bipass DOUBLE_H0[0] = DOUBLE_V2[0]	INT: !bipass DOUBLE_H1[0] = DOUBLE_IO_E1[0]	INT: !bipass DOUBLE_H0[1] = DOUBLE_IO_E1[0]	INT: !bipass DOUBLE_H0[1] = DOUBLE_IO_E0[0]	INT: mux DBUF_IO_V[1] bit 1	INT: mux DBUF_IO_V[1] bit 0	INT: !bipass SINGLE_H[0] = DOUBLE_IO_E0[0]	INT: !bipass SINGLE_H[1] = DOUBLE_IO_E1[0]	-	INT: mux DBUF_IO_V[0] bit 1	INT: mux DBUF_IO_V[0] bit 0	INT: !bipass DOUBLE_H0[0] = DOUBLE_IO_E0[1]	INT: !bipass DOUBLE_H0[0] = DOUBLE_IO_S1[1]	INT: !bipass DOUBLE_H0[0] = DOUBLE_IO_E1[1]	INT: !bipass DOUBLE_H1[1] = DOUBLE_IO_E0[1]	INT: !bipass DOUBLE_H1[1] = DOUBLE_IO_E1[1]	INT: !bipass DOUBLE_H1[1] = DOUBLE_IO_S1[1]	MISC_SE: OSC_MUX_OUT0 bit 1	MISC_SE: OSC_MUX_OUT0 bit 2	MISC_SE: OSC_ENABLE
B8	-	INT: !bipass SINGLE_V[2] = SINGLE_V_S[2]	INT: !bipass SINGLE_H_E[2] = SINGLE_V[2]	INT: !bipass SINGLE_H_E[2] = SINGLE_V_S[2]	INT: !bipass SINGLE_H[2] = SINGLE_H_E[2]	INT: !bipass SINGLE_H[2] = SINGLE_V[2]	INT: !bipass SINGLE_H[2] = SINGLE_V_S[2]	-	INT: !bipass SINGLE_V[1] = SINGLE_V_S[1]	INT: !bipass SINGLE_H_E[1] = SINGLE_V[1]	INT: !bipass SINGLE_H_E[1] = SINGLE_V_S[1]	INT: !bipass SINGLE_H[1] = SINGLE_V_S[1]	INT: !bipass SINGLE_H[1] = SINGLE_V[1]	INT: !bipass SINGLE_H[1] = SINGLE_H_E[1]	INT: !bipass DOUBLE_H1[0] = DOUBLE_IO_S1[0]	INT: !bipass DOUBLE_H1[0] = DOUBLE_IO_E0[0]	INT: !bipass DOUBLE_H0[1] = DOUBLE_IO_S1[0]	INT: !bipass DOUBLE_IO_S1[0] = DOUBLE_IO_E0[0]	INT: !bipass SINGLE_H[0] = DOUBLE_IO_S1[0]	INT: !pass DOUBLE_IO_S1[1] ← DBUF_IO_V[1]	INT: !pass DOUBLE_IO_S1[0] ← DBUF_IO_V[1]	INT: !pass DOUBLE_IO_E0[0] ← DBUF_IO_V[0]	INT: !pass DOUBLE_IO_E0[1] ← DBUF_IO_V[0]	INT: !bipass DOUBLE_IO_S1[1] = DOUBLE_IO_E0[1]	INT: !bipass SINGLE_H[2] = DOUBLE_IO_E0[1]	INT: !bipass SINGLE_H[2] = DOUBLE_IO_S1[1]	INT: !bipass SINGLE_H[3] = DOUBLE_IO_E1[1]	-	-	INT: mux LONG_IO_V[0] bit 2	MISC_SE: OSC_MUX_OUT1 bit 2	-
B7	-	INT: !pass SINGLE_V[2] ← LONG_H[3]	INT: !pass SINGLE_H_E[1] ← LONG_V[1]	INT: !bipass SINGLE_H_E[3] = SINGLE_V[3]	INT: !bipass SINGLE_V[3] = SINGLE_V_S[3]	INT: !bipass SINGLE_H[3] = SINGLE_V[3]	INT: !pass SINGLE_H[2] ← LONG_V[2]	INT: !pass SINGLE_V[3] ← LONG_H[4]	INT: !bipass DOUBLE_H2[1] = DOUBLE_V2[1]	INT: !bipass DOUBLE_H2[1] = DOUBLE_V0[1]	INT: !bipass DOUBLE_V0[1] = DOUBLE_V2[1]	INT: !bipass DOUBLE_H0[1] = DOUBLE_V0[1]	INT: !bipass DOUBLE_H0[1] = DOUBLE_H2[1]	INT: !pass DOUBLE_H0[0] ← OUT_STARTUP_Q1Q4	INT: !pass SINGLE_H[1] ← OUT_STARTUP_Q3	INT: !pass SINGLE_H[3] ← DEC_V[1]	INT: !pass SINGLE_H[1] ← DEC_V[1]	INT: !pass SINGLE_H[0] ← LONG_IO_V[0]	INT: !pass SINGLE_H[2] ← LONG_IO_V[0]	INT: !pass DOUBLE_H0[1] ← OUT_IO_WE_I2_S1	INT: !pass SINGLE_H[0] ← OUT_STARTUP_Q1Q4	INT: !pass SINGLE_H[2] ← OUT_STARTUP_Q1Q4	INT: !pass DOUBLE_H1[0] ← OUT_IO_WE_I1_S1	INT: !pass SINGLE_H[3] ← OUT_IO_WE_I1_S1	INT: !pass SINGLE_H[1] ← OUT_IO_WE_I1_S1	INT: mux LONG_IO_V[1] bit 4	INT: mux LONG_IO_V[0] bit 1	INT: mux LONG_IO_V[0] bit 0	INT: mux LONG_IO_V[0] bit 3	INT: mux LONG_IO_V[0] bit 4	INT: !pass SINGLE_H[2] ← DEC_V[0]	INT: !pass SINGLE_H[0] ← DEC_V[0]
B6	-	INT: !pass SINGLE_H_E[0] ← LONG_V[0]	-	-	INT: !buffer LONG_V[0] ← SINGLE_H_E[0]	INT: !bipass SINGLE_H[3] = SINGLE_V_S[3]	INT: !bipass SINGLE_H[3] = SINGLE_H_E[3]	INT: !bipass SINGLE_H_E[3] = SINGLE_V_S[3]	-	-	INT: !buffer LONG_H[4] ← SINGLE_V[3]	INT: !bipass DOUBLE_H0[1] = DOUBLE_V2[1]	INT: !pass SINGLE_H[3] ← LONG_V[3]	INT: !pass SINGLE_H[3] ← OUT_STARTUP_Q3	INT: !pass DOUBLE_H1[1] ← OUT_STARTUP_Q3	INT: !buffer LONG_V[1] ← SINGLE_H_E[1]	INT: !buffer LONG_V[2] ← SINGLE_H[2]	INT: !pass SINGLE_H[0] ← OUT_IO_WE_I2_S1	INT: !pass SINGLE_H[2] ← OUT_IO_WE_I2_S1	INT: !pass SINGLE_H[1] ← LONG_IO_V[1]	INT: !pass SINGLE_H[3] ← LONG_IO_V[1]	INT: !buffer LONG_V[3] ← SINGLE_H[3]	INT: mux LONG_IO_V[1] bit 3	INT: mux LONG_IO_V[1] bit 0	INT: mux LONG_IO_V[1] bit 2	INT: mux LONG_IO_V[1] bit 1	INT: mux LONG_IO_V[1] bit 5	INT: mux LONG_IO_V[0] bit 5	MISC_SE: OSC_MUX_OUT1 bit 1	MISC_SE: OSC_MUX_OUT1 bit 0	MISC_SE: OSC_MUX_OUT0 bit 0	-
B5	INT: !pass SINGLE_V[0] ← LONG_IO_H[0]	INT: !pass SINGLE_V[0] ← OUT_STARTUP_Q2	INT: !pass SINGLE_V[0] ← OUT_IO_SN_I2_E1	INT: !pass SINGLE_V[0] ← DEC_H[1]	INT: mux LONG_V[0] bit 3	INT: mux LONG_V[0] bit 0	INT: mux LONG_V[0] bit 1	INT: mux LONG_V[0] bit 2	INT: mux LONG_V[3] bit 3	INT: mux LONG_V[3] bit 0	INT: mux LONG_V[3] bit 1	INT: mux LONG_V[3] bit 2	INT: !pass SINGLE_V[3] ← DEC_H[0]	INT: !buffer LONG_H[3] ← SINGLE_V[2]	INT: !pass SINGLE_V[3] ← OUT_IO_SN_I1_E1	INT: !pass DOUBLE_V1[1] ← OUT_IO_SN_I2_E1	INT: mux LONG_V[1] bit 3	INT: mux LONG_V[1] bit 1	INT: mux LONG_V[1] bit 2	INT: mux LONG_V[2] bit 1	INT: mux LONG_V[2] bit 3	INT: mux LONG_V[2] bit 0	INT: mux LONG_V[2] bit 2	INT: mux LONG_IO_H[1] bit 0	-	INT: mux LONG_IO_H[1] bit 1	INT: mux LONG_IO_H[0] bit 1	INT: mux LONG_IO_H[0] bit 0	PULLUP_DEC_V[0]: ! ENABLE	PULLUP_DEC_H[1]: ! ENABLE	MISC_SE: OSC_MUX_OUT1 bit 3	MISC_SE: OSC_MUX_OUT0 bit 3
B4	INT: !pass SINGLE_V[2] ← LONG_IO_H[0]	INT: !pass SINGLE_V[2] ← OUT_STARTUP_Q2	INT: !pass SINGLE_V[2] ← OUT_IO_SN_I2_E1	INT: !pass DOUBLE_V0[0] ← OUT_IO_SN_I1_E1	INT: !pass SINGLE_V[2] ← DEC_H[1]	INT: !pass DOUBLE_V1[0] ← OUT_STARTUP_Q2	INT: !pass SINGLE_V[1] ← LONG_IO_H[1]	INT: !pass SINGLE_V[1] ← OUT_IO_SN_I1_E1	INT: !pass SINGLE_V[1] ← OUT_STARTUP_DONEIN	INT: !pass SINGLE_V[1] ← DEC_H[0]	INT: !pass SINGLE_V[3] ← OUT_STARTUP_DONEIN	INT: !pass SINGLE_V[3] ← LONG_IO_H[1]	INT: !pass DOUBLE_V0[1] ← OUT_STARTUP_DONEIN	INT: !pass DOUBLE_IO_E1[0] ← DBUF_IO_H[1]	INT: mux LONG_V[1] bit 0	INT: !pass DOUBLE_IO_E1[1] ← DBUF_IO_H[1]	INT: mux DBUF_IO_H[0] bit 1	INT: mux DBUF_IO_H[0] bit 0	INT: !pass DOUBLE_IO_S2[1] ← DBUF_IO_H[0]	INT: !pass DOUBLE_IO_S2[0] ← DBUF_IO_H[0]	INT: mux DBUF_IO_H[1] bit 1	INT: mux DBUF_IO_H[1] bit 0	INT: !bipass DOUBLE_V1[1] = DOUBLE_IO_E1[1]	INT: !bipass DOUBLE_V1[1] = DOUBLE_IO_S1[1]	INT: !bipass DOUBLE_V0[0] = DOUBLE_IO_S1[1]	INT: !bipass SINGLE_V[2] = DOUBLE_IO_S1[1]	PULLUP_DEC_H[0]: ! ENABLE	-	-	-	-	-
B3	INT: mux IMUX_STARTUP_CLK bit 2	INT: mux IMUX_STARTUP_CLK bit 1	INT: !bipass DOUBLE_V1[0] = DOUBLE_IO_S2[0]	INT: !bipass SINGLE_V[1] = DOUBLE_IO_S2[0]	INT: !bipass DOUBLE_V0[1] = DOUBLE_IO_S2[0]	INT: !bipass SINGLE_V[1] = DOUBLE_IO_E1[0]	INT: !bipass DOUBLE_V1[0] = DOUBLE_IO_E1[0]	INT: !bipass DOUBLE_V0[1] = DOUBLE_IO_E1[0]	INT: !bipass DOUBLE_IO_S2[0] = DOUBLE_IO_E1[0]	INT: !bipass DOUBLE_V1[0] = DOUBLE_IO_S1[0]	INT: !bipass DOUBLE_V0[1] = DOUBLE_IO_S1[0]	INT: mux IMUX_BUFG_H bit 4	INT: !bipass SINGLE_V[0] = DOUBLE_IO_S1[0]	INT: !bipass SINGLE_V[3] = DOUBLE_IO_S2[1]	INT: !bipass DOUBLE_V1[1] = DOUBLE_IO_S2[1]	INT: !bipass DOUBLE_V0[0] = DOUBLE_IO_S2[1]	INT: !bipass DOUBLE_IO_S2[1] = DOUBLE_IO_E1[1]	INT: !bipass DOUBLE_V0[0] = DOUBLE_IO_E1[1]	INT: !bipass SINGLE_V[3] = DOUBLE_IO_E1[1]	INT: mux LONG_IO_H[1] bit 3	INT: mux LONG_IO_H[1] bit 2	INT: mux LONG_IO_H[1] bit 4	INT: mux LONG_IO_H[1] bit 5	INT: mux LONG_IO_H[1] bit 6	INT: mux LONG_IO_H[0] bit 2	INT: mux LONG_IO_H[0] bit 4	INT: mux LONG_IO_H[0] bit 3	INT: mux LONG_IO_H[0] bit 5	INT: mux LONG_H[4] bit 3	INT: mux IMUX_BUFG_V bit 0	INT: mux LONG_IO_H[0] bit 6	MISC_SE: ! TCTEST
B2	INT: mux IMUX_STARTUP_CLK bit 0	INT: mux IMUX_STARTUP_GTS bit 1	INT: mux IMUX_STARTUP_GTS bit 3	INT: mux IMUX_STARTUP_CLK bit 3	INT: mux IMUX_STARTUP_GTS bit 0	INT: mux IMUX_STARTUP_GTS bit 4	INT: mux IMUX_STARTUP_GTS bit 2	INT: mux IMUX_BUFG_H bit 3	INT: mux IMUX_BUFG_H bit 1	INT: mux IMUX_BUFG_H bit 2	INT: mux IMUX_BUFG_H bit 5	INT: mux LONG_H[3] bit 3	INT: mux LONG_H[3] bit 0	INT: mux IMUX_READCLK_I bit 0	INT: mux IMUX_READCLK_I bit 2	INT: mux LONG_H[3] bit 1	INT: mux LONG_H[3] bit 2	INT: mux IMUX_READCLK_I bit 1	INT: mux IMUX_READCLK_I bit 3	INT: mux IMUX_STARTUP_GSR bit 0	INT: mux IMUX_STARTUP_GSR bit 1	INT: mux IMUX_STARTUP_GSR bit 2	INT: mux IMUX_STARTUP_GSR bit 3	INT: mux IMUX_STARTUP_GSR bit 4	INT: mux LONG_H[4] bit 1	INT: mux LONG_H[4] bit 0	INT: mux LONG_H[4] bit 2	-	-	-	-	-
B1	STARTUP: ! GSR_ENABLE	-	STARTUP: GTS_TIMING bit 0	-	-	-	-	-	STARTUP: MUX_CLK bit 0	PULLUP_DEC_V[1]: ! ENABLE	INT: mux IMUX_BUFG_H bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	STARTUP: ! CRC
B0	STARTUP: !invert GSR	STARTUP: GTS_TIMING bit 1	STARTUP: GSR_TIMING bit 1	-	STARTUP: GSR_TIMING bit 0	STARTUP: DONE_TIMING bit 0	STARTUP: DONE_TIMING bit 1	STARTUP: ! SYNC_TO_DONE	STARTUP: !invert GTS	MISC_SE: ! DONE_PULLUP	STARTUP: ! GTS_ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	STARTUP: CONFIG_RATE bit 0

Tile CNR_NE

Cells: 2

Switchbox INT

xc4000a CNR_NE switchbox INT programmable buffers
Destination	Source	Bit
CELL.LONG_H[0]	CELL.SINGLE_V[0]	!MAIN_S[29][9]
CELL.LONG_H[2]	CELL.SINGLE_V[1]	!MAIN[18][0]

xc4000a CNR_NE switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_V[0]	CELL.LONG_H[0]	!MAIN_S[30][9]
CELL.SINGLE_V[0]	CELL.LONG_IO_H[0]	!MAIN[31][0]
CELL.SINGLE_V[0]	CELL.DEC_H[0]	!MAIN[28][0]
CELL.SINGLE_V[0]	CELL.OUT_IO_SN_I2_E1	!MAIN[29][0]
CELL.SINGLE_V[0]	CELL.OUT_UPDATE_O	!MAIN[30][0]
CELL.SINGLE_V[1]	CELL.LONG_H[2]	!MAIN_S[21][9]
CELL.SINGLE_V[1]	CELL.LONG_IO_H[1]	!MAIN[25][1]
CELL.SINGLE_V[1]	CELL.DEC_H[1]	!MAIN[22][1]
CELL.SINGLE_V[1]	CELL.OUT_IO_SN_I1_E1	!MAIN[24][1]
CELL.SINGLE_V[1]	CELL.OUT_OSC_MUX1	!MAIN[23][1]
CELL.SINGLE_V[2]	CELL.LONG_IO_H[0]	!MAIN[31][1]
CELL.SINGLE_V[2]	CELL.DEC_H[0]	!MAIN[27][1]
CELL.SINGLE_V[2]	CELL.OUT_IO_SN_I2_E1	!MAIN[29][1]
CELL.SINGLE_V[2]	CELL.OUT_UPDATE_O	!MAIN[30][1]
CELL.SINGLE_V[3]	CELL.LONG_IO_H[1]	!MAIN[20][1]
CELL.SINGLE_V[3]	CELL.DEC_H[1]	!MAIN[19][0]
CELL.SINGLE_V[3]	CELL.OUT_IO_SN_I1_E1	!MAIN[17][0]
CELL.SINGLE_V[3]	CELL.OUT_OSC_MUX1	!MAIN[21][1]
CELL.DOUBLE_V0[0]	CELL.OUT_IO_SN_I1_E1	!MAIN[28][1]
CELL.DOUBLE_V0[1]	CELL.OUT_OSC_MUX1	!MAIN[19][1]
CELL.DOUBLE_V1[0]	CELL.OUT_UPDATE_O	!MAIN[26][1]
CELL.DOUBLE_V1[1]	CELL.OUT_IO_SN_I2_E1	!MAIN[16][0]
CELL.DOUBLE_IO_E2[0]	CELL.DBUF_IO_H[1]	!MAIN[18][1]
CELL.DOUBLE_IO_E2[1]	CELL.DBUF_IO_H[1]	!MAIN[16][1]
CELL.DOUBLE_IO_N0[0]	CELL.DBUF_IO_H[0]	!MAIN[12][1]
CELL.DOUBLE_IO_N0[1]	CELL.DBUF_IO_H[0]	!MAIN[13][1]

xc4000a CNR_NE switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_V[0]	CELL.DOUBLE_IO_E1[0]	!MAIN[19][2]
CELL.SINGLE_V[1]	CELL.DOUBLE_IO_E2[0]	!MAIN[26][2]
CELL.SINGLE_V[1]	CELL.DOUBLE_IO_N0[0]	!MAIN[28][2]
CELL.SINGLE_V[2]	CELL.DOUBLE_IO_E1[1]	!MAIN[6][1]
CELL.SINGLE_V[3]	CELL.DOUBLE_IO_E2[1]	!MAIN[13][2]
CELL.SINGLE_V[3]	CELL.DOUBLE_IO_N0[1]	!MAIN[18][2]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_E1[1]	!MAIN[7][1]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_E2[1]	!MAIN[14][2]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_N0[1]	!MAIN[16][2]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_E1[0]	!MAIN[21][2]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_E2[0]	!MAIN[24][2]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_N0[0]	!MAIN[27][2]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_E1[0]	!MAIN[22][2]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_E2[0]	!MAIN[25][2]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_N0[0]	!MAIN[29][2]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_E1[1]	!MAIN[8][1]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_E2[1]	!MAIN[9][1]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_N0[1]	!MAIN[17][2]
CELL.DOUBLE_IO_E2[0]	CELL.DOUBLE_IO_N0[0]	!MAIN[23][2]
CELL.DOUBLE_IO_E2[1]	CELL.DOUBLE_IO_N0[1]	!MAIN[15][2]

xc4000a CNR_NE switchbox INT muxes DBUF_IO_H[0]
Bits		Destination
MAIN[15][1]	MAIN[14][1]	CELL.DBUF_IO_H[0]
		Source
0	0	CELL.DOUBLE_IO_E2[1]
1	1	CELL.DOUBLE_IO_E2[0]

xc4000a CNR_NE switchbox INT muxes DBUF_IO_H[1]
Bits		Destination
MAIN[11][1]	MAIN[10][1]	CELL.DBUF_IO_H[1]
		Source
0	0	CELL.DOUBLE_IO_N0[0]
1	1	CELL.DOUBLE_IO_N0[1]

xc4000a CNR_NE switchbox INT muxes LONG_H[0]
Bits				Destination
MAIN[24][3]	MAIN[21][3]	MAIN[28][3]	MAIN[30][3]	CELL.LONG_H[0]
				Source
0	0	0	1	CELL.LONG_IO_V[0]
0	0	1	0	CELL.DEC_V[1]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000a CNR_NE switchbox INT muxes LONG_H[2]
Bits				Destination
MAIN[3][2]	MAIN[5][3]	MAIN[7][3]	MAIN[6][3]	CELL.LONG_H[2]
				Source
0	0	0	1	CELL.LONG_IO_V[1]
0	0	1	0	CELL.DEC_V[0]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000a CNR_NE switchbox INT muxes LONG_V[0]
Bits				Destination
MAIN[27][0]	MAIN[24][0]	MAIN[25][0]	MAIN[26][0]	CELL.LONG_V[0]
				Source
0	0	0	1	CELL.LONG_IO_H[0]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000a CNR_NE switchbox INT muxes LONG_V[1]
Bits				Destination
MAIN[15][0]	MAIN[13][0]	MAIN[14][0]	MAIN[17][1]	CELL.LONG_V[1]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[0]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000a CNR_NE switchbox INT muxes LONG_V[2]
Bits				Destination
MAIN[11][0]	MAIN[9][0]	MAIN[12][0]	MAIN[10][0]	CELL.LONG_V[2]
				Source
0	0	0	1	CELL.LONG_IO_H[0]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_OSC_MUX1
1	1	1	1	off

xc4000a CNR_NE switchbox INT muxes LONG_V[3]
Bits				Destination
MAIN[23][0]	MAIN[20][0]	MAIN[21][0]	MAIN[22][0]	CELL.LONG_V[3]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[0]
0	1	1	1	CELL.OUT_OSC_MUX1
1	1	1	1	off

xc4000a CNR_NE switchbox INT muxes LONG_IO_H[0]
Bits							Destination
MAIN[1][2]	MAIN[4][2]	MAIN[6][2]	MAIN[5][2]	MAIN[7][2]	MAIN[5][0]	MAIN[4][0]	CELL.LONG_IO_H[0]
							Source
0	0	0	1	1	1	1	CELL.SINGLE_V[2]
0	0	1	0	1	1	1	CELL.LONG_V[0]
0	0	1	1	0	1	1	CELL.LONG_V[2]
0	1	1	1	1	1	1	CELL.SINGLE_V[0]
1	1	1	1	1	0	0	CELL.LONG_IO_V[0]
1	1	1	1	1	0	1	CELL.LONG_IO_V[1]
1	1	1	1	1	1	1	off

xc4000a CNR_NE switchbox INT muxes LONG_IO_H[1]
Bits							Destination
MAIN[8][2]	MAIN[9][2]	MAIN[10][2]	MAIN[12][2]	MAIN[11][2]	MAIN[6][0]	MAIN[8][0]	CELL.LONG_IO_H[1]
							Source
0	0	0	1	1	1	1	CELL.SINGLE_V[3]
0	0	1	0	1	1	1	CELL.LONG_V[1]
0	0	1	1	0	1	1	CELL.LONG_V[3]
0	1	1	1	1	1	1	CELL.SINGLE_V[1]
1	1	1	1	1	0	0	CELL.LONG_IO_V[1]
1	1	1	1	1	0	1	CELL.LONG_IO_V[0]
1	1	1	1	1	1	1	off

xc4000a CNR_NE switchbox INT muxes LONG_IO_V[0]
Bits				Destination
MAIN[17][3]	MAIN[18][3]	MAIN[20][3]	MAIN[19][3]	CELL.LONG_IO_V[0]
				Source
0	0	0	1	CELL.LONG_H[0]
0	0	1	0	CELL.LONG_IO_H[1]
0	1	1	1	CELL.LONG_IO_H[0]
1	1	1	1	off

xc4000a CNR_NE switchbox INT muxes LONG_IO_V[1]
Bits				Destination
MAIN[16][3]	MAIN[13][3]	MAIN[15][3]	MAIN[14][3]	CELL.LONG_IO_V[1]
				Source
0	0	0	1	CELL.LONG_H[2]
0	0	1	0	CELL.LONG_IO_H[0]
0	1	1	1	CELL.LONG_IO_H[1]
1	1	1	1	off

xc4000a CNR_NE switchbox INT muxes IMUX_BUFG_H
Bits	Destination
MAIN[2][2]	CELL.IMUX_BUFG_H
	Source
0	CELL.OUT_IO_CLKIN_E
1	off

xc4000a CNR_NE switchbox INT muxes IMUX_BUFG_V
Bits						Destination
MAIN[22][3]	MAIN[29][4]	MAIN[26][3]	MAIN[25][3]	MAIN[27][3]	MAIN[23][3]	CELL.IMUX_BUFG_V
						Source
0	0	0	1	1	1	CELL.DOUBLE_IO_E1[1]
0	0	1	0	1	1	CELL.DOUBLE_IO_E2[0]
0	0	1	1	0	1	CELL.DOUBLE_IO_E2[1]
0	1	1	1	1	0	CELL.OUT_IO_CLKIN_N
0	1	1	1	1	1	off
1	0	1	1	1	1	CELL.DOUBLE_IO_E1[0]

xc4000a CNR_NE switchbox INT muxes IMUX_TDO_O
Bits					Destination
MAIN[29][3]	MAIN[31][2]	MAIN[31][3]	MAIN[30][2]	MAIN[30][4]	CELL.IMUX_TDO_O
					Source
0	0	0	1	1	CELL.LONG_H[0]
0	0	1	1	1	CELL.SINGLE_V[0]
0	1	0	0	1	CELL.SINGLE_V[3]
0	1	0	1	0	CELL.LONG_H[2]
0	1	1	0	1	CELL.SINGLE_V[2]
0	1	1	1	0	CELL_S.DOUBLE_H1[1]
1	1	0	1	1	CELL.SINGLE_V[1]
1	1	1	1	1	CELL_S.DOUBLE_H0[0]

xc4000a CNR_NE switchbox INT muxes IMUX_TDO_T
Bits					Destination
MAIN[9][3]	MAIN[12][3]	MAIN[8][3]	MAIN[10][3]	MAIN[11][3]	CELL.IMUX_TDO_T
					Source
0	0	0	1	1	CELL.DOUBLE_V0[0]
0	0	1	1	1	CELL.DOUBLE_V1[1]
0	1	0	0	1	CELL_S.SINGLE_H[1]
0	1	0	1	0	CELL_S.SINGLE_H[3]
0	1	1	0	1	CELL.LONG_V[2]
0	1	1	1	0	CELL.LONG_V[3]
1	1	0	1	1	CELL_S.SINGLE_H[0]
1	1	1	1	1	CELL_S.SINGLE_H[2]

Bels PULLUP

xc4000a CNR_NE bel PULLUP pins
Pin	Direction	PULLUP_DEC_H[0]	PULLUP_DEC_H[1]	PULLUP_DEC_V[0]	PULLUP_DEC_V[1]
O	bidir	CELL.DEC_H[0]	CELL.DEC_H[1]	CELL.DEC_V[0]	CELL.DEC_V[1]

xc4000a CNR_NE bel PULLUP attribute bits
Attribute	PULLUP_DEC_H[0]	PULLUP_DEC_H[1]	PULLUP_DEC_V[0]	PULLUP_DEC_V[1]
ENABLE	!MAIN[2][0]	!MAIN[5][1]	!MAIN[3][0]	!MAIN[20][2]

Bels BUFG

xc4000a CNR_NE bel BUFG pins
Pin	Direction	BUFG_H	BUFG_V
I	in	CELL.IMUX_BUFG_H	CELL.IMUX_BUFG_V
O	out	CELL.BUFGLS[6]	CELL.BUFGLS[5]

xc4000a CNR_NE bel BUFG attribute bits
Attribute	BUFG_H	BUFG_V

Bels UPDATE

xc4000a CNR_NE bel UPDATE pins
Pin	Direction	UPDATE
O	out	CELL.OUT_UPDATE_O

Bels OSC

xc4000a CNR_NE bel OSC pins
Pin	Direction	OSC
F8M	out	CELL.OUT_IO_WE_I1[1]
OUT0	out	CELL.OUT_IO_WE_I2[1]
OUT1	out	CELL.OUT_OSC_MUX1

Bels TDO

xc4000a CNR_NE bel TDO pins
Pin	Direction	TDO
O	in	CELL.IMUX_TDO_O
T	in	CELL.IMUX_TDO_T

xc4000a CNR_NE bel TDO attribute bits
Attribute	TDO
PULL	[enum: IO_PULL]
BSCAN_ENABLE	MAIN[30][5]
T_ENABLE	!MAIN[0][2]
O_ENABLE	!MAIN[29][5]

xc4000a CNR_NE enum IO_PULL
TDO.PULL	MAIN[4][1]	MAIN[3][1]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

Bels MISC_NE

xc4000a CNR_NE bel MISC_NE pins
Pin	Direction	MISC_NE

xc4000a CNR_NE bel MISC_NE attribute bits
Attribute	MISC_NE
TM_RIGHT	!MAIN[7][0]
TAC	!MAIN[1][0]
READCLK	[enum: RDBK_MUX_CLK]

xc4000a CNR_NE enum RDBK_MUX_CLK
MISC_NE.READCLK	MAIN[0][0]
CCLK	1
RDBK	0

Bel wires

xc4000a CNR_NE bel wires
Wire	Pins
CELL.DEC_H[0]	PULLUP_DEC_H[0].O
CELL.DEC_H[1]	PULLUP_DEC_H[1].O
CELL.DEC_V[0]	PULLUP_DEC_V[0].O
CELL.DEC_V[1]	PULLUP_DEC_V[1].O
CELL.BUFGLS[5]	BUFG_V.O
CELL.BUFGLS[6]	BUFG_H.O
CELL.IMUX_BUFG_H	BUFG_H.I
CELL.IMUX_BUFG_V	BUFG_V.I
CELL.IMUX_TDO_O	TDO.O
CELL.IMUX_TDO_T	TDO.T
CELL.OUT_IO_WE_I1[1]	OSC.F8M
CELL.OUT_IO_WE_I2[1]	OSC.OUT0
CELL.OUT_OSC_MUX1	OSC.OUT1
CELL.OUT_UPDATE_O	UPDATE.O

Bitstream

xc4000a CNR_NE rect MAIN
Bit	Frame
Bit	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B5	-	TDO: BSCAN_ENABLE	TDO: ! O_ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	INT: mux CELL.IMUX_TDO_O bit 0	INT: mux CELL.IMUX_BUFG_V bit 4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	INT: mux CELL.IMUX_TDO_O bit 2	INT: mux CELL.LONG_H[0] bit 0	INT: mux CELL.IMUX_TDO_O bit 4	INT: mux CELL.LONG_H[0] bit 1	INT: mux CELL.IMUX_BUFG_V bit 1	INT: mux CELL.IMUX_BUFG_V bit 3	INT: mux CELL.IMUX_BUFG_V bit 2	INT: mux CELL.LONG_H[0] bit 3	INT: mux CELL.IMUX_BUFG_V bit 0	INT: mux CELL.IMUX_BUFG_V bit 5	INT: mux CELL.LONG_H[0] bit 2	INT: mux CELL.LONG_IO_V[0] bit 1	INT: mux CELL.LONG_IO_V[0] bit 0	INT: mux CELL.LONG_IO_V[0] bit 2	INT: mux CELL.LONG_IO_V[0] bit 3	INT: mux CELL.LONG_IO_V[1] bit 3	INT: mux CELL.LONG_IO_V[1] bit 1	INT: mux CELL.LONG_IO_V[1] bit 0	INT: mux CELL.LONG_IO_V[1] bit 2	INT: mux CELL.IMUX_TDO_T bit 3	INT: mux CELL.IMUX_TDO_T bit 0	INT: mux CELL.IMUX_TDO_T bit 1	INT: mux CELL.IMUX_TDO_T bit 4	INT: mux CELL.IMUX_TDO_T bit 2	INT: mux CELL.LONG_H[2] bit 1	INT: mux CELL.LONG_H[2] bit 0	INT: mux CELL.LONG_H[2] bit 2	-	-	-	-	-
B2	INT: mux CELL.IMUX_TDO_O bit 3	INT: mux CELL.IMUX_TDO_O bit 1	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N0[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N0[0]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N0[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_E2[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_E2[0]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_E2[0]	INT: !bipass CELL.DOUBLE_IO_E2[0] = CELL.DOUBLE_IO_N0[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_E1[0]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_E1[0]	PULLUP_DEC_V[1]: ! ENABLE	INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_E1[0]	INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N0[1]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N0[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N0[1]	INT: !bipass CELL.DOUBLE_IO_E2[1] = CELL.DOUBLE_IO_N0[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_E2[1]	INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_E2[1]	INT: mux CELL.LONG_IO_H[1] bit 3	INT: mux CELL.LONG_IO_H[1] bit 2	INT: mux CELL.LONG_IO_H[1] bit 4	INT: mux CELL.LONG_IO_H[1] bit 5	INT: mux CELL.LONG_IO_H[1] bit 6	INT: mux CELL.LONG_IO_H[0] bit 2	INT: mux CELL.LONG_IO_H[0] bit 4	INT: mux CELL.LONG_IO_H[0] bit 3	INT: mux CELL.LONG_IO_H[0] bit 5	INT: mux CELL.LONG_H[2] bit 3	INT: mux CELL.IMUX_BUFG_H bit 0	INT: mux CELL.LONG_IO_H[0] bit 6	TDO: ! T_ENABLE
B1	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[0]	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_UPDATE_O	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I2_E1	INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.SINGLE_V[2] ← CELL.DEC_H[0]	INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_UPDATE_O	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[1]	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_OSC_MUX1	INT: !pass CELL.SINGLE_V[1] ← CELL.DEC_H[1]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_OSC_MUX1	INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_IO_H[1]	INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_OSC_MUX1	INT: !pass CELL.DOUBLE_IO_E2[0] ← CELL.DBUF_IO_H[1]	INT: mux CELL.LONG_V[1] bit 0	INT: !pass CELL.DOUBLE_IO_E2[1] ← CELL.DBUF_IO_H[1]	INT: mux CELL.DBUF_IO_H[0] bit 1	INT: mux CELL.DBUF_IO_H[0] bit 0	INT: !pass CELL.DOUBLE_IO_N0[1] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_N0[0] ← CELL.DBUF_IO_H[0]	INT: mux CELL.DBUF_IO_H[1] bit 1	INT: mux CELL.DBUF_IO_H[1] bit 0	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_E2[1]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_E1[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_E1[1]	INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_E1[1]	PULLUP_DEC_H[1]: ! ENABLE	TDO: PULL bit 1	TDO: PULL bit 0	-	-	-
B0	INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_IO_H[0]	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_UPDATE_O	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1	INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[0]	INT: mux CELL.LONG_V[0] bit 3	INT: mux CELL.LONG_V[0] bit 0	INT: mux CELL.LONG_V[0] bit 1	INT: mux CELL.LONG_V[0] bit 2	INT: mux CELL.LONG_V[3] bit 3	INT: mux CELL.LONG_V[3] bit 0	INT: mux CELL.LONG_V[3] bit 1	INT: mux CELL.LONG_V[3] bit 2	INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[1]	INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[1]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.LONG_V[1] bit 3	INT: mux CELL.LONG_V[1] bit 1	INT: mux CELL.LONG_V[1] bit 2	INT: mux CELL.LONG_V[2] bit 1	INT: mux CELL.LONG_V[2] bit 3	INT: mux CELL.LONG_V[2] bit 0	INT: mux CELL.LONG_V[2] bit 2	INT: mux CELL.LONG_IO_H[1] bit 0	MISC_NE: ! TM_RIGHT	INT: mux CELL.LONG_IO_H[1] bit 1	INT: mux CELL.LONG_IO_H[0] bit 1	INT: mux CELL.LONG_IO_H[0] bit 0	PULLUP_DEC_V[0]: ! ENABLE	PULLUP_DEC_H[0]: ! ENABLE	MISC_NE: ! TAC	MISC_NE: READCLK bit 0

xc4000a CNR_NE rect MAIN_S
Bit	Frame
Bit	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	-	INT: !pass CELL.SINGLE_V[0] ← CELL.LONG_H[0]	INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[0]	-	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[2]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

xc4000a CNR_NE rect MAIN_W
Bit	Frame
Bit	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Keyboard shortcuts

Project Combine