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Corners

Tile CNR.BL

Cells: 2 IRIs: 0

Muxes

xc4000a CNR.BL muxes
DestinationSources
TCELL0:SINGLE.H0TCELL0:IO.DOUBLE.0.S.0, TCELL0:IO.DOUBLE.0.W.2, TCELL0:LONG.IO.V0, TCELL0:DEC.V1, TCELL0:OUT.LR.IOB1.I2.S, TCELL0:OUT.MD0.I
TCELL0:SINGLE.H1TCELL0:IO.DOUBLE.0.W.1, TCELL0:LONG.IO.V1, TCELL0:DEC.V0, TCELL0:OUT.LR.IOB1.I1.S, TCELL0:OUT.RDBK.DATA
TCELL0:SINGLE.H2TCELL0:IO.DOUBLE.1.S.0, TCELL0:IO.DOUBLE.1.W.2, TCELL0:LONG.IO.V0, TCELL0:DEC.V1, TCELL0:OUT.LR.IOB1.I2.S, TCELL0:OUT.MD0.I
TCELL0:SINGLE.H3TCELL0:IO.DOUBLE.1.W.1, TCELL0:LONG.IO.V1, TCELL0:DEC.V0, TCELL0:OUT.LR.IOB1.I1.S, TCELL0:OUT.RDBK.DATA
TCELL0:DOUBLE.H0.0TCELL0:IO.DOUBLE.0.S.0, TCELL0:IO.DOUBLE.0.W.1, TCELL0:IO.DOUBLE.0.W.2, TCELL0:OUT.LR.IOB1.I1.S
TCELL0:DOUBLE.H0.1TCELL0:IO.DOUBLE.1.S.0, TCELL0:IO.DOUBLE.1.W.1, TCELL0:IO.DOUBLE.1.W.2, TCELL0:OUT.MD0.I
TCELL0:DOUBLE.H1.0TCELL0:IO.DOUBLE.1.S.0, TCELL0:IO.DOUBLE.1.W.1, TCELL0:IO.DOUBLE.1.W.2, TCELL0:OUT.RDBK.DATA
TCELL0:DOUBLE.H1.1TCELL0:IO.DOUBLE.0.S.0, TCELL0:IO.DOUBLE.0.W.1, TCELL0:IO.DOUBLE.0.W.2, TCELL0:OUT.LR.IOB1.I2.S
TCELL0:IO.DOUBLE.0.S.0TCELL0:SINGLE.H0, TCELL0:DOUBLE.H0.0, TCELL0:DOUBLE.H1.1, TCELL0:IO.DOUBLE.0.W.2, TCELL0:IO.DBUF.V1
TCELL0:IO.DOUBLE.0.W.1TCELL0:SINGLE.H1, TCELL0:DOUBLE.H0.0, TCELL0:DOUBLE.H1.1
TCELL0:IO.DOUBLE.0.W.2TCELL0:SINGLE.H0, TCELL0:DOUBLE.H0.0, TCELL0:DOUBLE.H1.1, TCELL0:IO.DOUBLE.0.S.0, TCELL0:IO.DBUF.V0
TCELL0:IO.DOUBLE.1.S.0TCELL0:SINGLE.H2, TCELL0:DOUBLE.H0.1, TCELL0:DOUBLE.H1.0, TCELL0:IO.DOUBLE.1.W.2, TCELL0:IO.DBUF.V1
TCELL0:IO.DOUBLE.1.W.1TCELL0:SINGLE.H3, TCELL0:DOUBLE.H0.1, TCELL0:DOUBLE.H1.0
TCELL0:IO.DOUBLE.1.W.2TCELL0:SINGLE.H2, TCELL0:DOUBLE.H0.1, TCELL0:DOUBLE.H1.0, TCELL0:IO.DOUBLE.1.S.0, TCELL0:IO.DBUF.V0
TCELL0:IO.DBUF.V0TCELL0:IO.DOUBLE.0.S.0, TCELL0:IO.DOUBLE.1.S.0
TCELL0:IO.DBUF.V1TCELL0:IO.DOUBLE.0.W.2, TCELL0:IO.DOUBLE.1.W.2
TCELL0:LONG.H2TCELL0:LONG.IO.V0, TCELL0:DEC.V0, TCELL0:OUT.RDBK.DATA
TCELL0:LONG.H3TCELL0:LONG.IO.V1, TCELL0:DEC.V1, TCELL0:OUT.RDBK.DATA
TCELL0:LONG.IO.H0TCELL0:LONG.IO.V0, TCELL0:LONG.IO.V1
TCELL0:LONG.IO.H1TCELL0:LONG.IO.V0, TCELL0:LONG.IO.V1
TCELL0:LONG.IO.V0TCELL0:SINGLE.H0, TCELL0:SINGLE.H2, TCELL0:LONG.H2, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.H1
TCELL0:LONG.IO.V1TCELL0:SINGLE.H1, TCELL0:SINGLE.H3, TCELL0:LONG.H3, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.H1
TCELL0:IMUX.IOB1.O1TCELL0:SINGLE.H0, TCELL0:SINGLE.H1, TCELL0:SINGLE.H2, TCELL0:SINGLE.H3, TCELL1:DOUBLE.V0.1, TCELL1:DOUBLE.V1.0, TCELL1:LONG.V0, TCELL1:LONG.V1
TCELL0:IMUX.IOB1.IKTCELL0:DOUBLE.H0.0, TCELL0:DOUBLE.H1.1, TCELL0:LONG.H2, TCELL0:LONG.H3, TCELL1:SINGLE.V0, TCELL1:SINGLE.V1, TCELL1:SINGLE.V2, TCELL1:SINGLE.V3
TCELL0:IMUX.BUFG.HTCELL0:OUT.IOB.CLKIN.W
TCELL0:IMUX.BUFG.VTCELL0:IO.DOUBLE.0.S.0, TCELL0:IO.DOUBLE.0.W.1, TCELL0:IO.DOUBLE.1.S.0, TCELL0:IO.DOUBLE.1.W.1, TCELL0:OUT.IOB.CLKIN.S
TCELL0:IMUX.RDBK.TRIGTCELL0:SINGLE.H0, TCELL0:SINGLE.H1, TCELL0:SINGLE.H2, TCELL0:SINGLE.H3

Bel PULLUP_DEC0_H

xc4000a CNR.BL bel PULLUP_DEC0_H
PinDirectionWires
OoutputTCELL0:DEC.H0

Bel PULLUP_DEC1_H

xc4000a CNR.BL bel PULLUP_DEC1_H
PinDirectionWires
OoutputTCELL0:DEC.H1

Bel PULLUP_DEC0_V

xc4000a CNR.BL bel PULLUP_DEC0_V
PinDirectionWires
OoutputTCELL0:DEC.V0

Bel PULLUP_DEC1_V

xc4000a CNR.BL bel PULLUP_DEC1_V
PinDirectionWires
OoutputTCELL0:DEC.V1

Bel BUFGLS_H

xc4000a CNR.BL bel BUFGLS_H
PinDirectionWires
IinputTCELL0:IMUX.BUFG.H

Bel BUFGLS_V

xc4000a CNR.BL bel BUFGLS_V
PinDirectionWires
IinputTCELL0:IMUX.BUFG.V

Bel CIN

xc4000a CNR.BL bel CIN
PinDirectionWires

Bel MD0

xc4000a CNR.BL bel MD0
PinDirectionWires
IoutputTCELL0:OUT.MD0.I

Bel MD1

xc4000a CNR.BL bel MD1
PinDirectionWires
OinputTCELL0:IMUX.IOB1.O1
TinputTCELL0:IMUX.IOB1.IK

Bel MD2

xc4000a CNR.BL bel MD2
PinDirectionWires
IoutputTCELL0:OUT.BT.IOB1.I1

Bel RDBK

xc4000a CNR.BL bel RDBK
PinDirectionWires
DATAoutputTCELL0:OUT.RDBK.DATA
RIPoutputTCELL0:OUT.BT.IOB1.I2
TRIGinputTCELL0:IMUX.RDBK.TRIG

Bel wires

xc4000a CNR.BL bel wires
WirePins
TCELL0:DEC.H0PULLUP_DEC0_H.O
TCELL0:DEC.H1PULLUP_DEC1_H.O
TCELL0:DEC.V0PULLUP_DEC0_V.O
TCELL0:DEC.V1PULLUP_DEC1_V.O
TCELL0:IMUX.IOB1.O1MD1.O
TCELL0:IMUX.IOB1.IKMD1.T
TCELL0:IMUX.BUFG.HBUFGLS_H.I
TCELL0:IMUX.BUFG.VBUFGLS_V.I
TCELL0:IMUX.RDBK.TRIGRDBK.TRIG
TCELL0:OUT.BT.IOB1.I1MD2.I
TCELL0:OUT.BT.IOB1.I2RDBK.RIP
TCELL0:OUT.MD0.IMD0.I
TCELL0:OUT.RDBK.DATARDBK.DATA

Bitstream

xc4000a CNR.BL bittile 0
BitFrame
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
9 ~MD1:ENABLE.O ~MD1:ENABLE.T - ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.S.0 ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.W.1 ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.W.2 ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.1 ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.S.0 ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.2 - - - ~INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.W.1 ~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.W.2 INT:MUX.IO.DBUF.V1[1] INT:MUX.IO.DBUF.V1[0] ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.W.2 ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.W.1 ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.1 ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.2 ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.S.0
8 - - - - - ~INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.W.1 ~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.0 ~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.W.2 ~INT:BIPASS.IO.DOUBLE.1.S.0.IO.DOUBLE.1.W.2 ~INT:PASS.IO.DOUBLE.1.W.2.0.IO.DBUF.V0 ~INT:PASS.IO.DOUBLE.0.W.2.0.IO.DBUF.V0 INT:MUX.IO.DBUF.V0[1] INT:MUX.IO.DBUF.V0[0] ~INT:PASS.IO.DOUBLE.0.S.0.0.IO.DBUF.V1 ~INT:PASS.IO.DOUBLE.1.S.0.0.IO.DBUF.V1 ~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.0 ~INT:BIPASS.IO.DOUBLE.0.S.0.IO.DOUBLE.0.W.2 ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.S.0 - - ~INT:PASS.DOUBLE.H0.1.0.OUT.MD0.I
7 - - ~INT:PASS.SINGLE.H0.0.DEC.V1 ~INT:PASS.SINGLE.H2.0.DEC.V1 ~INT:PASS.SINGLE.H3.0.OUT.RDBK.DATA ~INT:PASS.SINGLE.H1.0.OUT.RDBK.DATA ~INT:PASS.DOUBLE.H1.0.0.OUT.RDBK.DATA ~INT:PASS.SINGLE.H1.0.OUT.LR.IOB1.I1.S ~INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S ~INT:PASS.DOUBLE.H0.0.0.OUT.LR.IOB1.I1.S ~INT:PASS.SINGLE.H2.0.OUT.MD0.I ~INT:PASS.SINGLE.H0.0.OUT.MD0.I ~INT:PASS.DOUBLE.H1.1.0.OUT.LR.IOB1.I2.S ~INT:PASS.SINGLE.H3.0.LONG.IO.V1 ~INT:PASS.SINGLE.H1.0.LONG.IO.V1 ~INT:PASS.SINGLE.H2.0.OUT.LR.IOB1.I2.S ~INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S ~INT:PASS.SINGLE.H2.0.LONG.IO.V0 ~INT:PASS.SINGLE.H0.0.LONG.IO.V0 ~INT:PASS.SINGLE.H1.0.DEC.V0 ~INT:PASS.SINGLE.H3.0.DEC.V0
6 - - - ~RDBK:ENABLE INT:MUX.IMUX.RDBK.TRIG[0] INT:MUX.IMUX.RDBK.TRIG[1] INT:MUX.IMUX.RDBK.TRIG[2] INT:MUX.IMUX.RDBK.TRIG[3] INT:MUX.LONG.H3[0] INT:MUX.LONG.H3[1] INT:MUX.LONG.H3[2] INT:MUX.LONG.H3[3] - - - INT:MUX.LONG.H2[3] INT:MUX.LONG.H2[0] INT:MUX.LONG.H2[1] - INT:MUX.LONG.H2[2] -
5 MD1:PULL[1] MD1:PULL[0] ~MISC:READ_CAPTURE - ~PULLUP_DEC1_V:ENABLE INT:MUX.IMUX.BUFG.H[0] INT:MUX.LONG.IO.V0[3] INT:MUX.LONG.IO.V0[4] INT:MUX.LONG.IO.V1[3] INT:MUX.LONG.IO.V1[4] - - - - - - - - ~PULLUP_DEC0_V:ENABLE - -
4 - - - - - INT:MUX.LONG.IO.V0[1] INT:MUX.LONG.IO.V1[1] INT:MUX.LONG.IO.V1[2] INT:MUX.LONG.IO.V1[0] INT:MUX.LONG.IO.H0[1] INT:MUX.LONG.IO.H1[1] INT:MUX.LONG.IO.V1[5] INT:MUX.LONG.IO.H1[0] INT:MUX.LONG.IO.V0[5] INT:MUX.LONG.IO.H0[0] ~MISC:TM_BOT - ~PULLUP_DEC1_H:ENABLE ~PULLUP_DEC0_H:ENABLE - -
3 - INT:MUX.LONG.IO.V0[0] INT:MUX.LONG.IO.V0[2] INT:MUX.IMUX.IOB1.IK[3] INT:MUX.IMUX.IOB1.IK[1] INT:MUX.IMUX.IOB1.IK[2] INT:MUX.IMUX.IOB1.IK[4] INT:MUX.IMUX.IOB1.IK[0] INT:MUX.IMUX.IOB1.O1[4] INT:MUX.IMUX.IOB1.O1[2] INT:MUX.IMUX.IOB1.O1[0] INT:MUX.IMUX.IOB1.O1[1] INT:MUX.IMUX.IOB1.O1[3] INT:MUX.IMUX.BUFG.V[0] INT:MUX.IMUX.BUFG.V[5] INT:MUX.IMUX.BUFG.V[1] INT:MUX.IMUX.BUFG.V[3] INT:MUX.IMUX.BUFG.V[2] INT:MUX.IMUX.BUFG.V[4] - -
2 - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - -
0 - - ~MISC:READ_ABORT - - - - - - - - - - - - - - - - - -
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.S.0 0.0.9
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.1 0.2.9
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.2 0.1.9
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.S.0 0.13.9
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.1 0.14.9
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.2 0.12.9
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.S.0 0.17.9
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.W.1 0.16.9
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.W.2 0.15.9
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.S.0 0.3.8
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.W.1 0.3.9
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.W.2 0.4.9
INT:BIPASS.IO.DOUBLE.0.S.0.IO.DOUBLE.0.W.2 0.4.8
INT:BIPASS.IO.DOUBLE.1.S.0.IO.DOUBLE.1.W.2 0.12.8
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.0 0.5.8
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.W.2 0.7.9
INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.W.1 0.8.9
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.0 0.14.8
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.W.2 0.13.8
INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.W.1 0.15.8
INT:PASS.DOUBLE.H0.0.0.OUT.LR.IOB1.I1.S 0.11.7
INT:PASS.DOUBLE.H0.1.0.OUT.MD0.I 0.0.8
INT:PASS.DOUBLE.H1.0.0.OUT.RDBK.DATA 0.14.7
INT:PASS.DOUBLE.H1.1.0.OUT.LR.IOB1.I2.S 0.8.7
INT:PASS.IO.DOUBLE.0.S.0.0.IO.DBUF.V1 0.7.8
INT:PASS.IO.DOUBLE.0.W.2.0.IO.DBUF.V0 0.10.8
INT:PASS.IO.DOUBLE.1.S.0.0.IO.DBUF.V1 0.6.8
INT:PASS.IO.DOUBLE.1.W.2.0.IO.DBUF.V0 0.11.8
INT:PASS.SINGLE.H0.0.DEC.V1 0.18.7
INT:PASS.SINGLE.H0.0.LONG.IO.V0 0.2.7
INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S 0.4.7
INT:PASS.SINGLE.H0.0.OUT.MD0.I 0.9.7
INT:PASS.SINGLE.H1.0.DEC.V0 0.1.7
INT:PASS.SINGLE.H1.0.LONG.IO.V1 0.6.7
INT:PASS.SINGLE.H1.0.OUT.LR.IOB1.I1.S 0.13.7
INT:PASS.SINGLE.H1.0.OUT.RDBK.DATA 0.15.7
INT:PASS.SINGLE.H2.0.DEC.V1 0.17.7
INT:PASS.SINGLE.H2.0.LONG.IO.V0 0.3.7
INT:PASS.SINGLE.H2.0.OUT.LR.IOB1.I2.S 0.5.7
INT:PASS.SINGLE.H2.0.OUT.MD0.I 0.10.7
INT:PASS.SINGLE.H3.0.DEC.V0 0.0.7
INT:PASS.SINGLE.H3.0.LONG.IO.V1 0.7.7
INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S 0.12.7
INT:PASS.SINGLE.H3.0.OUT.RDBK.DATA 0.16.7
MD1:ENABLE.O 0.20.9
MD1:ENABLE.T 0.19.9
MISC:READ_ABORT 0.18.0
MISC:READ_CAPTURE 0.18.5
MISC:TM_BOT 0.5.4
PULLUP_DEC0_H:ENABLE 0.2.4
PULLUP_DEC0_V:ENABLE 0.2.5
PULLUP_DEC1_H:ENABLE 0.3.4
PULLUP_DEC1_V:ENABLE 0.16.5
RDBK:ENABLE 0.17.6
inverted ~[0]
INT:MUX.IMUX.BUFG.H 0.15.5
0.OUT.IOB.CLKIN.W 0
NONE 1
INT:MUX.IMUX.BUFG.V 0.6.3 0.2.3 0.4.3 0.3.3 0.5.3 0.7.3
0.IO.DOUBLE.0.S.0 0 0 0 1 1 1
0.IO.DOUBLE.0.W.1 0 0 1 0 1 1
0.IO.DOUBLE.1.W.1 0 0 1 1 0 1
0.IO.DOUBLE.1.S.0 0 1 1 1 1 1
0.OUT.IOB.CLKIN.S 1 0 1 1 1 0
NONE 1 0 1 1 1 1
INT:MUX.IMUX.IOB1.IK 0.14.3 0.17.3 0.15.3 0.16.3 0.13.3
1.SINGLE.V3 0 0 1 1 0
0.DOUBLE.H0.0 0 0 1 1 1
1.SINGLE.V2 0 1 0 1 0
0.LONG.H2 0 1 0 1 1
1.SINGLE.V1 0 1 1 0 0
0.LONG.H3 0 1 1 0 1
1.SINGLE.V0 1 1 1 1 0
0.DOUBLE.H1.1 1 1 1 1 1
INT:MUX.IMUX.IOB1.O1 0.12.3 0.8.3 0.11.3 0.9.3 0.10.3
0.SINGLE.H1 0 0 0 1 1
1.LONG.V0 0 0 1 0 1
1.LONG.V1 0 0 1 1 0
0.SINGLE.H0 0 1 1 1 1
0.SINGLE.H2 1 0 0 1 1
0.SINGLE.H3 1 0 1 0 1
1.DOUBLE.V0.1 1 0 1 1 0
1.DOUBLE.V1.0 1 1 1 1 1
INT:MUX.IMUX.RDBK.TRIG 0.13.6 0.14.6 0.15.6 0.16.6
0.SINGLE.H1 0 0 1 1
0.SINGLE.H2 0 1 0 1
0.SINGLE.H3 0 1 1 0
0.SINGLE.H0 1 1 1 1
INT:MUX.IO.DBUF.V0 0.9.8 0.8.8
0.IO.DOUBLE.0.S.0 0 0
0.IO.DOUBLE.1.S.0 1 1
INT:MUX.IO.DBUF.V1 0.6.9 0.5.9
0.IO.DOUBLE.1.W.2 0 0
0.IO.DOUBLE.0.W.2 1 1
INT:MUX.LONG.H2 0.5.6 0.1.6 0.3.6 0.4.6
0.LONG.IO.V0 0 0 0 1
0.DEC.V0 0 0 1 0
0.OUT.RDBK.DATA 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.H3 0.9.6 0.10.6 0.11.6 0.12.6
0.LONG.IO.V1 0 0 0 1
0.DEC.V1 0 0 1 0
0.OUT.RDBK.DATA 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.H0 0.11.4 0.6.4
0.LONG.IO.V1 0 0
0.LONG.IO.V0 0 1
NONE 1 1
INT:MUX.LONG.IO.H1 0.10.4 0.8.4
0.LONG.IO.V0 0 0
0.LONG.IO.V1 0 1
NONE 1 1
INT:MUX.LONG.IO.V0 0.7.4 0.13.5 0.14.5 0.18.3 0.15.4 0.19.3
0.SINGLE.H2 0 0 0 1 1 1
0.LONG.H2 0 0 1 0 1 1
0.LONG.IO.H0 0 0 1 1 0 1
0.LONG.IO.H1 0 0 1 1 1 0
0.SINGLE.H0 0 1 1 1 1 1
NONE 1 1 1 1 1 1
INT:MUX.LONG.IO.V1 0.9.4 0.11.5 0.12.5 0.13.4 0.14.4 0.12.4
0.SINGLE.H3 0 0 0 1 1 1
0.LONG.H3 0 0 1 0 1 1
0.LONG.IO.H0 0 0 1 1 0 1
0.LONG.IO.H1 0 0 1 1 1 0
0.SINGLE.H1 0 1 1 1 1 1
NONE 1 1 1 1 1 1
MD1:PULL 0.20.5 0.19.5
PULLUP 0 1
PULLDOWN 1 0
PULLNONE 1 1

Tile CNR.TL

Cells: 4 IRIs: 0

Muxes

xc4000a CNR.TL muxes
DestinationSources
TCELL0:LONG.H0TCELL0:LONG.IO.V0, TCELL0:DEC.V0, TCELL0:OUT.LR.IOB1.I2
TCELL0:LONG.H1TCELL0:LONG.IO.V1, TCELL0:DEC.V1, TCELL0:OUT.LR.IOB1.I2
TCELL0:LONG.IO.H0TCELL0:LONG.IO.V0, TCELL0:LONG.IO.V1
TCELL0:LONG.IO.H1TCELL0:LONG.IO.V0, TCELL0:LONG.IO.V1
TCELL0:LONG.IO.V0TCELL0:LONG.H0, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.H1
TCELL0:LONG.IO.V1TCELL0:LONG.H1, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.H1
TCELL0:IMUX.BUFG.HTCELL0:IO.DOUBLE.0.W.0, TCELL0:IO.DOUBLE.0.W.1, TCELL0:IO.DOUBLE.1.W.0, TCELL0:IO.DOUBLE.1.W.1, TCELL0:OUT.IOB.CLKIN.W
TCELL0:IMUX.BUFG.VTCELL0:OUT.IOB.CLKIN.N
TCELL0:IMUX.BSCAN.TDO1TCELL1:DOUBLE.V0.1, TCELL1:DOUBLE.V1.0, TCELL1:LONG.V0, TCELL1:LONG.V1, TCELL2:SINGLE.H0, TCELL2:SINGLE.H1, TCELL2:SINGLE.H2, TCELL2:SINGLE.H3
TCELL0:IMUX.BSCAN.TDO2TCELL0:LONG.H0, TCELL0:LONG.H1, TCELL1:SINGLE.V0, TCELL1:SINGLE.V1, TCELL1:SINGLE.V2, TCELL1:SINGLE.V3, TCELL2:DOUBLE.H0.1, TCELL2:DOUBLE.H1.0

Bel PULLUP_DEC0_H

xc4000a CNR.TL bel PULLUP_DEC0_H
PinDirectionWires
OoutputTCELL0:DEC.H0

Bel PULLUP_DEC1_H

xc4000a CNR.TL bel PULLUP_DEC1_H
PinDirectionWires
OoutputTCELL0:DEC.H1

Bel PULLUP_DEC0_V

xc4000a CNR.TL bel PULLUP_DEC0_V
PinDirectionWires
OoutputTCELL0:DEC.V0

Bel PULLUP_DEC1_V

xc4000a CNR.TL bel PULLUP_DEC1_V
PinDirectionWires
OoutputTCELL0:DEC.V1

Bel BUFGLS_H

xc4000a CNR.TL bel BUFGLS_H
PinDirectionWires
IinputTCELL0:IMUX.BUFG.H

Bel BUFGLS_V

xc4000a CNR.TL bel BUFGLS_V
PinDirectionWires
IinputTCELL0:IMUX.BUFG.V

Bel CIN

xc4000a CNR.TL bel CIN
PinDirectionWires

Bel BSCAN

xc4000a CNR.TL bel BSCAN
PinDirectionWires
DRCKoutputTCELL0:OUT.BT.IOB1.I2
IDLEoutputTCELL0:OUT.LR.IOB1.I2
SEL1outputTCELL0:OUT.LR.IOB1.I1
SEL2outputTCELL0:OUT.BT.IOB1.I1
TDO1inputTCELL0:IMUX.BSCAN.TDO1
TDO2inputTCELL0:IMUX.BSCAN.TDO2

Bel wires

xc4000a CNR.TL bel wires
WirePins
TCELL0:DEC.H0PULLUP_DEC0_H.O
TCELL0:DEC.H1PULLUP_DEC1_H.O
TCELL0:DEC.V0PULLUP_DEC0_V.O
TCELL0:DEC.V1PULLUP_DEC1_V.O
TCELL0:IMUX.BUFG.HBUFGLS_H.I
TCELL0:IMUX.BUFG.VBUFGLS_V.I
TCELL0:IMUX.BSCAN.TDO1BSCAN.TDO1
TCELL0:IMUX.BSCAN.TDO2BSCAN.TDO2
TCELL0:OUT.BT.IOB1.I1BSCAN.SEL2
TCELL0:OUT.BT.IOB1.I2BSCAN.DRCK
TCELL0:OUT.LR.IOB1.I1BSCAN.SEL1
TCELL0:OUT.LR.IOB1.I2BSCAN.IDLE

Bitstream

xc4000a CNR.TL bittile 0
BitFrame
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5 - MISC:INPUT[0] - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - -
2 INT:MUX.LONG.IO.V0[0] INT:MUX.LONG.IO.V0[1] INT:MUX.IMUX.BSCAN.TDO2[0] INT:MUX.IMUX.BSCAN.TDO2[3] INT:MUX.IMUX.BSCAN.TDO2[2] INT:MUX.IMUX.BSCAN.TDO2[4] INT:MUX.IMUX.BSCAN.TDO2[1] INT:MUX.IMUX.BSCAN.TDO1[2] INT:MUX.IMUX.BSCAN.TDO1[0] INT:MUX.IMUX.BSCAN.TDO1[3] INT:MUX.IMUX.BSCAN.TDO1[1] INT:MUX.IMUX.BSCAN.TDO1[4] INT:MUX.IMUX.BUFG.H[0] INT:MUX.IMUX.BUFG.H[5] INT:MUX.IMUX.BUFG.H[1] INT:MUX.IMUX.BUFG.H[3] INT:MUX.IMUX.BUFG.H[2] INT:MUX.IMUX.BUFG.H[4] - -
1 - - - - INT:MUX.LONG.IO.V0[2] INT:MUX.LONG.IO.V1[0] INT:MUX.LONG.IO.H0[1] INT:MUX.LONG.IO.V1[1] INT:MUX.LONG.IO.V1[2] INT:MUX.LONG.IO.H1[1] INT:MUX.LONG.IO.V1[3] INT:MUX.LONG.IO.H1[0] INT:MUX.LONG.IO.V0[3] INT:MUX.LONG.IO.H0[0] ~MISC:TM_TOP ~MISC:TM_LEFT ~PULLUP_DEC0_H:ENABLE ~PULLUP_DEC1_H:ENABLE - -
0 BSCAN:ENABLE ~PULLUP_DEC1_V:ENABLE INT:MUX.LONG.H1[1] INT:MUX.IMUX.BUFG.V[0] - - - INT:MUX.LONG.H1[3] INT:MUX.LONG.H1[0] INT:MUX.LONG.H1[2] - - - INT:MUX.LONG.H0[3] INT:MUX.LONG.H0[1] INT:MUX.LONG.H0[0] INT:MUX.LONG.H0[2] ~PULLUP_DEC0_V:ENABLE - -
BSCAN:ENABLE 0.19.0
non-inverted [0]
INT:MUX.IMUX.BSCAN.TDO1 0.8.2 0.10.2 0.12.2 0.9.2 0.11.2
1.LONG.V1 0 0 0 1 1
1.DOUBLE.V0.1 0 0 1 1 1
1.LONG.V0 0 1 0 0 1
2.SINGLE.H1 0 1 0 1 0
2.SINGLE.H3 0 1 1 0 1
2.SINGLE.H2 0 1 1 1 0
2.SINGLE.H0 1 1 0 1 1
1.DOUBLE.V1.0 1 1 1 1 1
INT:MUX.IMUX.BSCAN.TDO2 0.14.2 0.16.2 0.15.2 0.13.2 0.17.2
1.SINGLE.V1 0 0 1 0 1
0.LONG.H0 0 0 1 1 1
1.SINGLE.V2 0 1 0 0 1
0.LONG.H1 0 1 0 1 1
1.SINGLE.V3 0 1 1 0 0
2.DOUBLE.H1.0 0 1 1 1 0
1.SINGLE.V0 1 1 1 0 1
2.DOUBLE.H0.1 1 1 1 1 1
INT:MUX.IMUX.BUFG.H 0.6.2 0.2.2 0.4.2 0.3.2 0.5.2 0.7.2
0.IO.DOUBLE.0.W.0 0 0 0 1 1 1
0.IO.DOUBLE.0.W.1 0 0 1 0 1 1
0.IO.DOUBLE.1.W.1 0 0 1 1 0 1
0.IO.DOUBLE.1.W.0 0 1 1 1 1 1
0.OUT.IOB.CLKIN.W 1 0 1 1 1 0
NONE 1 0 1 1 1 1
INT:MUX.IMUX.BUFG.V 0.16.0
0.OUT.IOB.CLKIN.N 0
NONE 1
INT:MUX.LONG.H0 0.6.0 0.3.0 0.5.0 0.4.0
0.LONG.IO.V0 0 0 0 1
0.DEC.V0 0 0 1 0
0.OUT.LR.IOB1.I2 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.H1 0.12.0 0.10.0 0.17.0 0.11.0
0.LONG.IO.V1 0 0 0 1
0.DEC.V1 0 0 1 0
0.OUT.LR.IOB1.I2 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.H0 0.13.1 0.6.1
0.LONG.IO.V1 0 0
0.LONG.IO.V0 0 1
NONE 1 1
INT:MUX.LONG.IO.H1 0.10.1 0.8.1
0.LONG.IO.V0 0 0
0.LONG.IO.V1 0 1
NONE 1 1
INT:MUX.LONG.IO.V0 0.7.1 0.15.1 0.18.2 0.19.2
0.LONG.H0 0 0 0 1
0.LONG.IO.H1 0 0 1 0
0.LONG.IO.H0 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.V1 0.9.1 0.11.1 0.12.1 0.14.1
0.LONG.H1 0 0 0 1
0.LONG.IO.H0 0 0 1 0
0.LONG.IO.H1 0 1 1 1
NONE 1 1 1 1
MISC:INPUT 0.18.5
CMOS 0
TTL 1
MISC:TM_LEFT 0.4.1
MISC:TM_TOP 0.5.1
PULLUP_DEC0_H:ENABLE 0.3.1
PULLUP_DEC0_V:ENABLE 0.2.0
PULLUP_DEC1_H:ENABLE 0.2.1
PULLUP_DEC1_V:ENABLE 0.18.0
inverted ~[0]

Tile CNR.BR

Cells: 1 IRIs: 0

Muxes

xc4000a CNR.BR muxes
DestinationSources
SINGLE.H0SINGLE.H0.E, SINGLE.V0, SINGLE.V0.S, IO.DOUBLE.0.E.0, IO.DOUBLE.0.S.1, LONG.IO.V0, DEC.V0, OUT.LR.IOB1.I2.S, OUT.STARTUP.Q1Q4
SINGLE.H0.ESINGLE.H0, SINGLE.V0, SINGLE.V0.S, LONG.V0
SINGLE.H1SINGLE.H1.E, SINGLE.V1, SINGLE.V1.S, IO.DOUBLE.0.E.1, LONG.IO.V1, DEC.V1, OUT.LR.IOB1.I1.S, OUT.STARTUP.Q3
SINGLE.H1.ESINGLE.H1, SINGLE.V1, SINGLE.V1.S, LONG.V1
SINGLE.H2SINGLE.H2.E, SINGLE.V2, SINGLE.V2.S, IO.DOUBLE.1.E.0, IO.DOUBLE.1.S.1, LONG.V2, LONG.IO.V0, DEC.V0, OUT.LR.IOB1.I2.S, OUT.STARTUP.Q1Q4
SINGLE.H2.ESINGLE.H2, SINGLE.V2, SINGLE.V2.S
SINGLE.H3SINGLE.H3.E, SINGLE.V3, SINGLE.V3.S, IO.DOUBLE.1.E.1, LONG.V3, LONG.IO.V1, DEC.V1, OUT.LR.IOB1.I1.S, OUT.STARTUP.Q3
SINGLE.H3.ESINGLE.H3, SINGLE.V3, SINGLE.V3.S
SINGLE.V0SINGLE.H0, SINGLE.H0.E, SINGLE.V0.S, IO.DOUBLE.0.S.1, LONG.IO.H0, DEC.H1, OUT.BT.IOB1.I2.E, OUT.STARTUP.Q2
SINGLE.V0.SSINGLE.H0, SINGLE.H0.E, SINGLE.V0
SINGLE.V1SINGLE.H1, SINGLE.H1.E, SINGLE.V1.S, IO.DOUBLE.0.E.1, IO.DOUBLE.0.S.2, LONG.IO.H1, DEC.H0, OUT.BT.IOB1.I1.E, OUT.STARTUP.DONEIN
SINGLE.V1.SSINGLE.H1, SINGLE.H1.E, SINGLE.V1
SINGLE.V2SINGLE.H2, SINGLE.H2.E, SINGLE.V2.S, IO.DOUBLE.1.S.1, LONG.H2, LONG.IO.H0, DEC.H1, OUT.BT.IOB1.I2.E, OUT.STARTUP.Q2
SINGLE.V2.SSINGLE.H2, SINGLE.H2.E, SINGLE.V2
SINGLE.V3SINGLE.H3, SINGLE.H3.E, SINGLE.V3.S, IO.DOUBLE.1.E.1, IO.DOUBLE.1.S.2, LONG.H3, LONG.IO.H1, DEC.H0, OUT.BT.IOB1.I1.E, OUT.STARTUP.DONEIN
SINGLE.V3.SSINGLE.H3, SINGLE.H3.E, SINGLE.V3
DOUBLE.H0.0DOUBLE.H0.2, DOUBLE.V0.0, DOUBLE.V0.2, IO.DOUBLE.1.E.0, IO.DOUBLE.1.E.1, IO.DOUBLE.1.S.1, OUT.STARTUP.Q1Q4
DOUBLE.H0.1IO.DOUBLE.0.E.0, IO.DOUBLE.0.E.1, IO.DOUBLE.0.S.1, OUT.LR.IOB1.I1.S
DOUBLE.H0.2DOUBLE.H0.0, DOUBLE.V0.0, DOUBLE.V0.2
DOUBLE.H1.0DOUBLE.H1.2, DOUBLE.V1.0, DOUBLE.V1.2, IO.DOUBLE.0.E.0, IO.DOUBLE.0.E.1, IO.DOUBLE.0.S.1, OUT.LR.IOB1.I2.S
DOUBLE.H1.1IO.DOUBLE.1.E.0, IO.DOUBLE.1.E.1, IO.DOUBLE.1.S.1, OUT.STARTUP.Q3
DOUBLE.H1.2DOUBLE.H1.0, DOUBLE.V1.0, DOUBLE.V1.2
DOUBLE.V0.0DOUBLE.H0.0, DOUBLE.H0.2, DOUBLE.V0.2, IO.DOUBLE.1.E.1, IO.DOUBLE.1.S.1, IO.DOUBLE.1.S.2, OUT.BT.IOB1.I1.E
DOUBLE.V0.1IO.DOUBLE.0.E.1, IO.DOUBLE.0.S.1, IO.DOUBLE.0.S.2, OUT.STARTUP.Q2
DOUBLE.V0.2DOUBLE.H0.0, DOUBLE.H0.2, DOUBLE.V0.0
DOUBLE.V1.0DOUBLE.H1.0, DOUBLE.H1.2, DOUBLE.V1.2, IO.DOUBLE.0.E.1, IO.DOUBLE.0.S.1, IO.DOUBLE.0.S.2, OUT.STARTUP.DONEIN
DOUBLE.V1.1IO.DOUBLE.1.E.1, IO.DOUBLE.1.S.1, IO.DOUBLE.1.S.2, OUT.BT.IOB1.I2.E
DOUBLE.V1.2DOUBLE.H1.0, DOUBLE.H1.2, DOUBLE.V1.0
IO.DOUBLE.0.E.0SINGLE.H0, DOUBLE.H0.1, DOUBLE.H1.0, IO.DOUBLE.0.S.1, IO.DBUF.V0
IO.DOUBLE.0.E.1SINGLE.H1, SINGLE.V1, DOUBLE.H0.1, DOUBLE.H1.0, DOUBLE.V0.1, DOUBLE.V1.0, IO.DOUBLE.0.S.2, IO.DBUF.H1
IO.DOUBLE.0.S.1SINGLE.H0, SINGLE.V0, DOUBLE.H0.1, DOUBLE.H1.0, DOUBLE.V0.1, DOUBLE.V1.0, IO.DOUBLE.0.E.0, IO.DBUF.V1
IO.DOUBLE.0.S.2SINGLE.V1, DOUBLE.V0.1, DOUBLE.V1.0, IO.DOUBLE.0.E.1, IO.DBUF.H0
IO.DOUBLE.1.E.0SINGLE.H2, DOUBLE.H0.0, DOUBLE.H1.1, IO.DOUBLE.1.S.1, IO.DBUF.V0
IO.DOUBLE.1.E.1SINGLE.H3, SINGLE.V3, DOUBLE.H0.0, DOUBLE.H1.1, DOUBLE.V0.0, DOUBLE.V1.1, IO.DOUBLE.1.S.2, IO.DBUF.H1
IO.DOUBLE.1.S.1SINGLE.H2, SINGLE.V2, DOUBLE.H0.0, DOUBLE.H1.1, DOUBLE.V0.0, DOUBLE.V1.1, IO.DOUBLE.1.E.0, IO.DBUF.V1
IO.DOUBLE.1.S.2SINGLE.V3, DOUBLE.V0.0, DOUBLE.V1.1, IO.DOUBLE.1.E.1, IO.DBUF.H0
IO.DBUF.H0IO.DOUBLE.0.E.1, IO.DOUBLE.1.E.1
IO.DBUF.H1IO.DOUBLE.0.S.2, IO.DOUBLE.1.S.2
IO.DBUF.V0IO.DOUBLE.0.S.1, IO.DOUBLE.1.S.1
IO.DBUF.V1IO.DOUBLE.0.E.0, IO.DOUBLE.1.E.0
LONG.H2SINGLE.V2, LONG.IO.V0, DEC.V1, OUT.STARTUP.Q3
LONG.H3SINGLE.V3, LONG.IO.V1, DEC.V0, OUT.STARTUP.Q3
LONG.V0SINGLE.H0.E, LONG.IO.H0, DEC.H0, OUT.BT.IOB1.I2.E
LONG.V1SINGLE.H1.E, LONG.IO.H1, DEC.H1, OUT.BT.IOB1.I2.E
LONG.V2SINGLE.H2, LONG.IO.H0, DEC.H0, OUT.STARTUP.DONEIN
LONG.V3SINGLE.H3, LONG.IO.H1, DEC.H1, OUT.STARTUP.DONEIN
LONG.IO.H0SINGLE.V0, SINGLE.V2, LONG.V0, LONG.V2, LONG.IO.V0, LONG.IO.V1
LONG.IO.H1SINGLE.V1, SINGLE.V3, LONG.V1, LONG.V3, LONG.IO.V0, LONG.IO.V1
LONG.IO.V0SINGLE.H0, SINGLE.H2, LONG.H2, LONG.IO.H0, LONG.IO.H1
LONG.IO.V1SINGLE.H1, SINGLE.H3, LONG.H3, LONG.IO.H0, LONG.IO.H1
IMUX.STARTUP.CLKSINGLE.V0, SINGLE.V1, SINGLE.V2, SINGLE.V3
IMUX.STARTUP.GSRSINGLE.H0, SINGLE.H1, SINGLE.H2, SINGLE.H3, DOUBLE.V0.0, DOUBLE.V1.1, LONG.V2, LONG.V3
IMUX.STARTUP.GTSSINGLE.V0, SINGLE.V1, SINGLE.V2, SINGLE.V3, DOUBLE.H0.1, DOUBLE.H1.0, LONG.H2, LONG.H3
IMUX.READCLK.ISINGLE.H0, SINGLE.H1, SINGLE.H2, SINGLE.H3
IMUX.BUFG.HIO.DOUBLE.0.E.1, IO.DOUBLE.0.S.1, IO.DOUBLE.1.E.1, IO.DOUBLE.1.S.1, OUT.IOB.CLKIN.E
IMUX.BUFG.VOUT.IOB.CLKIN.S

Bel PULLUP_DEC0_H

xc4000a CNR.BR bel PULLUP_DEC0_H
PinDirectionWires
OoutputDEC.H0

Bel PULLUP_DEC1_H

xc4000a CNR.BR bel PULLUP_DEC1_H
PinDirectionWires
OoutputDEC.H1

Bel PULLUP_DEC0_V

xc4000a CNR.BR bel PULLUP_DEC0_V
PinDirectionWires
OoutputDEC.V0

Bel PULLUP_DEC1_V

xc4000a CNR.BR bel PULLUP_DEC1_V
PinDirectionWires
OoutputDEC.V1

Bel BUFGLS_H

xc4000a CNR.BR bel BUFGLS_H
PinDirectionWires
IinputIMUX.BUFG.H

Bel BUFGLS_V

xc4000a CNR.BR bel BUFGLS_V
PinDirectionWires
IinputIMUX.BUFG.V

Bel COUT

xc4000a CNR.BR bel COUT
PinDirectionWires

Bel STARTUP

xc4000a CNR.BR bel STARTUP
PinDirectionWires
CLKinputIMUX.STARTUP.CLK
DONEINoutputOUT.STARTUP.DONEIN
GSRinputIMUX.STARTUP.GSR
GTSinputIMUX.STARTUP.GTS
Q1Q4outputOUT.STARTUP.Q1Q4
Q2outputOUT.STARTUP.Q2
Q3outputOUT.STARTUP.Q3

Bel READCLK

xc4000a CNR.BR bel READCLK
PinDirectionWires
IinputIMUX.READCLK.I

Bel wires

xc4000a CNR.BR bel wires
WirePins
DEC.H0PULLUP_DEC0_H.O
DEC.H1PULLUP_DEC1_H.O
DEC.V0PULLUP_DEC0_V.O
DEC.V1PULLUP_DEC1_V.O
IMUX.STARTUP.CLKSTARTUP.CLK
IMUX.STARTUP.GSRSTARTUP.GSR
IMUX.STARTUP.GTSSTARTUP.GTS
IMUX.READCLK.IREADCLK.I
IMUX.BUFG.HBUFGLS_H.I
IMUX.BUFG.VBUFGLS_V.I
OUT.STARTUP.DONEINSTARTUP.DONEIN
OUT.STARTUP.Q1Q4STARTUP.Q1Q4
OUT.STARTUP.Q2STARTUP.Q2
OUT.STARTUP.Q3STARTUP.Q3

Bitstream

xc4000a CNR.BR bittile 0
BitFrame
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
9 ~INT:BIPASS.SINGLE.V0.SINGLE.V0.S ~INT:BIPASS.SINGLE.H0.E.SINGLE.V0 ~INT:BIPASS.SINGLE.H0.E.SINGLE.V0.S ~INT:BIPASS.SINGLE.H0.SINGLE.H0.E ~INT:BIPASS.SINGLE.H0.SINGLE.V0 ~INT:BIPASS.SINGLE.H0.SINGLE.V0.S - ~INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.2 ~INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.0 ~INT:BIPASS.DOUBLE.V0.0.DOUBLE.V0.2 ~INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.0 ~INT:BIPASS.DOUBLE.H0.0.DOUBLE.H0.2 ~INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.2 ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.1 ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.E.1 ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.E.0 INT:MUX.IO.DBUF.V1[1] INT:MUX.IO.DBUF.V1[0] ~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.E.0 ~INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.E.1 - INT:MUX.IO.DBUF.V0[1] INT:MUX.IO.DBUF.V0[0] ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.0 ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.S.1 ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.1 ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.E.0 ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.E.1 ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.S.1 OSC:MUX.OUT0[1] OSC:MUX.OUT0[2] OSC:ENABLE
8 - ~INT:BIPASS.SINGLE.V2.SINGLE.V2.S ~INT:BIPASS.SINGLE.H2.E.SINGLE.V2 ~INT:BIPASS.SINGLE.H2.E.SINGLE.V2.S ~INT:BIPASS.SINGLE.H2.SINGLE.H2.E ~INT:BIPASS.SINGLE.H2.SINGLE.V2 ~INT:BIPASS.SINGLE.H2.SINGLE.V2.S - ~INT:BIPASS.SINGLE.V1.SINGLE.V1.S ~INT:BIPASS.SINGLE.H1.E.SINGLE.V1 ~INT:BIPASS.SINGLE.H1.E.SINGLE.V1.S ~INT:BIPASS.SINGLE.H1.SINGLE.V1.S ~INT:BIPASS.SINGLE.H1.SINGLE.V1 ~INT:BIPASS.SINGLE.H1.SINGLE.H1.E ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.S.1 ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.0 ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.S.1 ~INT:BIPASS.IO.DOUBLE.0.E.0.IO.DOUBLE.0.S.1 ~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.1 ~INT:PASS.IO.DOUBLE.1.S.1.0.IO.DBUF.V1 ~INT:PASS.IO.DOUBLE.0.S.1.0.IO.DBUF.V1 ~INT:PASS.IO.DOUBLE.0.E.0.0.IO.DBUF.V0 ~INT:PASS.IO.DOUBLE.1.E.0.0.IO.DBUF.V0 ~INT:BIPASS.IO.DOUBLE.1.E.0.IO.DOUBLE.1.S.1 ~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.E.0 ~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.1 ~INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.E.1 - - INT:MUX.LONG.IO.V0[2] OSC:MUX.OUT1[2] -
7 - ~INT:PASS.SINGLE.V2.0.LONG.H2 ~INT:PASS.SINGLE.H1.E.0.LONG.V1 ~INT:BIPASS.SINGLE.H3.E.SINGLE.V3 ~INT:BIPASS.SINGLE.V3.SINGLE.V3.S ~INT:BIPASS.SINGLE.H3.SINGLE.V3 ~INT:PASS.SINGLE.H2.0.LONG.V2 ~INT:PASS.SINGLE.V3.0.LONG.H3 ~INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.2 ~INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.0 ~INT:BIPASS.DOUBLE.V1.0.DOUBLE.V1.2 ~INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.0 ~INT:BIPASS.DOUBLE.H1.0.DOUBLE.H1.2 ~INT:PASS.DOUBLE.H0.0.0.OUT.STARTUP.Q1Q4 ~INT:PASS.SINGLE.H1.0.OUT.STARTUP.Q3 ~INT:PASS.SINGLE.H3.0.DEC.V1 ~INT:PASS.SINGLE.H1.0.DEC.V1 ~INT:PASS.SINGLE.H0.0.LONG.IO.V0 ~INT:PASS.SINGLE.H2.0.LONG.IO.V0 ~INT:PASS.DOUBLE.H1.0.0.OUT.LR.IOB1.I2.S ~INT:PASS.SINGLE.H0.0.OUT.STARTUP.Q1Q4 ~INT:PASS.SINGLE.H2.0.OUT.STARTUP.Q1Q4 ~INT:PASS.DOUBLE.H0.1.0.OUT.LR.IOB1.I1.S ~INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S ~INT:PASS.SINGLE.H1.0.OUT.LR.IOB1.I1.S INT:MUX.LONG.IO.V1[4] INT:MUX.LONG.IO.V0[1] INT:MUX.LONG.IO.V0[0] INT:MUX.LONG.IO.V0[3] INT:MUX.LONG.IO.V0[4] ~INT:PASS.SINGLE.H2.0.DEC.V0 ~INT:PASS.SINGLE.H0.0.DEC.V0
6 - ~INT:PASS.SINGLE.H0.E.0.LONG.V0 - - ~INT:BUF.LONG.V0.0.SINGLE.H0.E ~INT:BIPASS.SINGLE.H3.SINGLE.V3.S ~INT:BIPASS.SINGLE.H3.SINGLE.H3.E ~INT:BIPASS.SINGLE.H3.E.SINGLE.V3.S - - ~INT:BUF.LONG.H3.0.SINGLE.V3 ~INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.2 ~INT:PASS.SINGLE.H3.0.LONG.V3 ~INT:PASS.SINGLE.H3.0.OUT.STARTUP.Q3 ~INT:PASS.DOUBLE.H1.1.0.OUT.STARTUP.Q3 ~INT:BUF.LONG.V1.0.SINGLE.H1.E ~INT:BUF.LONG.V2.0.SINGLE.H2 ~INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S ~INT:PASS.SINGLE.H2.0.OUT.LR.IOB1.I2.S ~INT:PASS.SINGLE.H1.0.LONG.IO.V1 ~INT:PASS.SINGLE.H3.0.LONG.IO.V1 ~INT:BUF.LONG.V3.0.SINGLE.H3 INT:MUX.LONG.IO.V1[3] INT:MUX.LONG.IO.V1[0] INT:MUX.LONG.IO.V1[2] INT:MUX.LONG.IO.V1[1] INT:MUX.LONG.IO.V1[5] INT:MUX.LONG.IO.V0[5] OSC:MUX.OUT1[1] OSC:MUX.OUT1[0] OSC:MUX.OUT0[0] -
5 ~INT:PASS.SINGLE.V0.0.LONG.IO.H0 ~INT:PASS.SINGLE.V0.0.OUT.STARTUP.Q2 ~INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E ~INT:PASS.SINGLE.V0.0.DEC.H1 INT:MUX.LONG.V0[3] INT:MUX.LONG.V0[0] INT:MUX.LONG.V0[1] INT:MUX.LONG.V0[2] INT:MUX.LONG.V3[3] INT:MUX.LONG.V3[0] INT:MUX.LONG.V3[1] INT:MUX.LONG.V3[2] ~INT:PASS.SINGLE.V3.0.DEC.H0 ~INT:BUF.LONG.H2.0.SINGLE.V2 ~INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E ~INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E INT:MUX.LONG.V1[3] INT:MUX.LONG.V1[1] INT:MUX.LONG.V1[2] INT:MUX.LONG.V2[1] INT:MUX.LONG.V2[3] INT:MUX.LONG.V2[0] INT:MUX.LONG.V2[2] INT:MUX.LONG.IO.H1[0] - INT:MUX.LONG.IO.H1[1] INT:MUX.LONG.IO.H0[1] INT:MUX.LONG.IO.H0[0] ~PULLUP_DEC0_V:ENABLE ~PULLUP_DEC1_H:ENABLE OSC:MUX.OUT1[3] OSC:MUX.OUT0[3]
4 ~INT:PASS.SINGLE.V2.0.LONG.IO.H0 ~INT:PASS.SINGLE.V2.0.OUT.STARTUP.Q2 ~INT:PASS.SINGLE.V2.0.OUT.BT.IOB1.I2.E ~INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E ~INT:PASS.SINGLE.V2.0.DEC.H1 ~INT:PASS.DOUBLE.V0.1.0.OUT.STARTUP.Q2 ~INT:PASS.SINGLE.V1.0.LONG.IO.H1 ~INT:PASS.SINGLE.V1.0.OUT.BT.IOB1.I1.E ~INT:PASS.SINGLE.V1.0.OUT.STARTUP.DONEIN ~INT:PASS.SINGLE.V1.0.DEC.H0 ~INT:PASS.SINGLE.V3.0.OUT.STARTUP.DONEIN ~INT:PASS.SINGLE.V3.0.LONG.IO.H1 ~INT:PASS.DOUBLE.V1.0.0.OUT.STARTUP.DONEIN ~INT:PASS.IO.DOUBLE.0.E.1.0.IO.DBUF.H1 INT:MUX.LONG.V1[0] ~INT:PASS.IO.DOUBLE.1.E.1.0.IO.DBUF.H1 INT:MUX.IO.DBUF.H0[1] INT:MUX.IO.DBUF.H0[0] ~INT:PASS.IO.DOUBLE.1.S.2.0.IO.DBUF.H0 ~INT:PASS.IO.DOUBLE.0.S.2.0.IO.DBUF.H0 INT:MUX.IO.DBUF.H1[1] INT:MUX.IO.DBUF.H1[0] ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.1 ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.S.1 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.1 ~INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.S.1 ~PULLUP_DEC0_H:ENABLE - - - - -
3 INT:MUX.IMUX.STARTUP.CLK[2] INT:MUX.IMUX.STARTUP.CLK[1] ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.2 ~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.S.2 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.S.2 ~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.1 ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.1 ~INT:BIPASS.IO.DOUBLE.0.E.1.IO.DOUBLE.0.S.2 ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.1 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.S.1 INT:MUX.IMUX.BUFG.H[5] ~INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.S.1 ~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.S.2 ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.S.2 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.2 ~INT:BIPASS.IO.DOUBLE.1.E.1.IO.DOUBLE.1.S.2 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1 ~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.1 INT:MUX.LONG.IO.H1[3] INT:MUX.LONG.IO.H1[2] INT:MUX.LONG.IO.H1[4] INT:MUX.LONG.IO.H1[5] INT:MUX.LONG.IO.H1[6] INT:MUX.LONG.IO.H0[2] INT:MUX.LONG.IO.H0[4] INT:MUX.LONG.IO.H0[3] INT:MUX.LONG.IO.H0[5] INT:MUX.LONG.H3[3] INT:MUX.IMUX.BUFG.V[0] INT:MUX.LONG.IO.H0[6] ~MISC:TCTEST
2 INT:MUX.IMUX.STARTUP.CLK[0] INT:MUX.IMUX.STARTUP.GTS[1] INT:MUX.IMUX.STARTUP.GTS[3] INT:MUX.IMUX.STARTUP.CLK[3] INT:MUX.IMUX.STARTUP.GTS[0] INT:MUX.IMUX.STARTUP.GTS[4] INT:MUX.IMUX.STARTUP.GTS[2] INT:MUX.IMUX.BUFG.H[2] INT:MUX.IMUX.BUFG.H[3] INT:MUX.IMUX.BUFG.H[1] INT:MUX.IMUX.BUFG.H[4] INT:MUX.LONG.H2[3] INT:MUX.LONG.H2[0] INT:MUX.IMUX.READCLK.I[0] INT:MUX.IMUX.READCLK.I[2] INT:MUX.LONG.H2[1] INT:MUX.LONG.H2[2] INT:MUX.IMUX.READCLK.I[1] INT:MUX.IMUX.READCLK.I[3] INT:MUX.IMUX.STARTUP.GSR[0] INT:MUX.IMUX.STARTUP.GSR[1] INT:MUX.IMUX.STARTUP.GSR[2] INT:MUX.IMUX.STARTUP.GSR[3] INT:MUX.IMUX.STARTUP.GSR[4] INT:MUX.LONG.H3[1] INT:MUX.LONG.H3[0] INT:MUX.LONG.H3[2] - - - - -
1 ~STARTUP:ENABLE.GSR - STARTUP:OUTPUTS_ACTIVE[1] - - - - - STARTUP:STARTUP_CLK[0] ~PULLUP_DEC1_V:ENABLE INT:MUX.IMUX.BUFG.H[0] - - - - - - - - - - - - - - - - - - - - ~STARTUP:CRC
0 ~STARTUP:INV.GSR STARTUP:OUTPUTS_ACTIVE[0] STARTUP:GSR_INACTIVE[0] - STARTUP:GSR_INACTIVE[1] STARTUP:DONE_ACTIVE[1] STARTUP:DONE_ACTIVE[0] ~STARTUP:SYNC_TO_DONE ~STARTUP:INV.GTS DONE:PULL[0] ~STARTUP:ENABLE.GTS - - - - - - - - - - - - - - - - - - - - STARTUP:CONFIG_RATE[0]
DONE:PULL 0.22.0
PULLUP 0
PULLNONE 1
INT:BIPASS.DOUBLE.H0.0.DOUBLE.H0.2 0.20.9
INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.0 0.21.9
INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.2 0.19.9
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.0 0.8.9
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.1 0.6.9
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.S.1 0.7.9
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.0 0.16.8
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.1 0.18.9
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.S.1 0.17.8
INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.0 0.23.9
INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.2 0.24.9
INT:BIPASS.DOUBLE.H1.0.DOUBLE.H1.2 0.19.7
INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.0 0.20.7
INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.2 0.20.6
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.E.0 0.16.9
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.E.1 0.17.9
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.S.1 0.15.8
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.E.0 0.5.9
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.E.1 0.4.9
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.S.1 0.3.9
INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.0 0.22.7
INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.2 0.23.7
INT:BIPASS.DOUBLE.V0.0.DOUBLE.V0.2 0.22.9
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1 0.14.3
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.1 0.7.4
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.2 0.16.3
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1 0.25.3
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.1 0.22.3
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.2 0.29.3
INT:BIPASS.DOUBLE.V1.0.DOUBLE.V1.2 0.21.7
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.1 0.24.3
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.S.1 0.21.3
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.S.2 0.27.3
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.1 0.9.4
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.S.1 0.8.4
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.S.2 0.17.3
INT:BIPASS.IO.DOUBLE.0.E.0.IO.DOUBLE.0.S.1 0.14.8
INT:BIPASS.IO.DOUBLE.0.E.1.IO.DOUBLE.0.S.2 0.23.3
INT:BIPASS.IO.DOUBLE.1.E.0.IO.DOUBLE.1.S.1 0.8.8
INT:BIPASS.IO.DOUBLE.1.E.1.IO.DOUBLE.1.S.2 0.15.3
INT:BIPASS.SINGLE.H0.E.SINGLE.V0 0.30.9
INT:BIPASS.SINGLE.H0.E.SINGLE.V0.S 0.29.9
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.E.0 0.13.9
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.1 0.13.8
INT:BIPASS.SINGLE.H0.SINGLE.H0.E 0.28.9
INT:BIPASS.SINGLE.H0.SINGLE.V0 0.27.9
INT:BIPASS.SINGLE.H0.SINGLE.V0.S 0.26.9
INT:BIPASS.SINGLE.H1.E.SINGLE.V1 0.22.8
INT:BIPASS.SINGLE.H1.E.SINGLE.V1.S 0.21.8
INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.E.1 0.12.9
INT:BIPASS.SINGLE.H1.SINGLE.H1.E 0.18.8
INT:BIPASS.SINGLE.H1.SINGLE.V1 0.19.8
INT:BIPASS.SINGLE.H1.SINGLE.V1.S 0.20.8
INT:BIPASS.SINGLE.H2.E.SINGLE.V2 0.29.8
INT:BIPASS.SINGLE.H2.E.SINGLE.V2.S 0.28.8
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.E.0 0.7.8
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.1 0.6.8
INT:BIPASS.SINGLE.H2.SINGLE.H2.E 0.27.8
INT:BIPASS.SINGLE.H2.SINGLE.V2 0.26.8
INT:BIPASS.SINGLE.H2.SINGLE.V2.S 0.25.8
INT:BIPASS.SINGLE.H3.E.SINGLE.V3 0.28.7
INT:BIPASS.SINGLE.H3.E.SINGLE.V3.S 0.24.6
INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.E.1 0.5.8
INT:BIPASS.SINGLE.H3.SINGLE.H3.E 0.25.6
INT:BIPASS.SINGLE.H3.SINGLE.V3 0.26.7
INT:BIPASS.SINGLE.H3.SINGLE.V3.S 0.26.6
INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.S.1 0.19.3
INT:BIPASS.SINGLE.V0.SINGLE.V0.S 0.31.9
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.1 0.26.3
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.S.2 0.28.3
INT:BIPASS.SINGLE.V1.SINGLE.V1.S 0.23.8
INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.S.1 0.6.4
INT:BIPASS.SINGLE.V2.SINGLE.V2.S 0.30.8
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.1 0.13.3
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.S.2 0.18.3
INT:BIPASS.SINGLE.V3.SINGLE.V3.S 0.27.7
INT:BUF.LONG.H2.0.SINGLE.V2 0.18.5
INT:BUF.LONG.H3.0.SINGLE.V3 0.21.6
INT:BUF.LONG.V0.0.SINGLE.H0.E 0.27.6
INT:BUF.LONG.V1.0.SINGLE.H1.E 0.16.6
INT:BUF.LONG.V2.0.SINGLE.H2 0.15.6
INT:BUF.LONG.V3.0.SINGLE.H3 0.10.6
INT:PASS.DOUBLE.H0.0.0.OUT.STARTUP.Q1Q4 0.18.7
INT:PASS.DOUBLE.H0.1.0.OUT.LR.IOB1.I1.S 0.9.7
INT:PASS.DOUBLE.H1.0.0.OUT.LR.IOB1.I2.S 0.12.7
INT:PASS.DOUBLE.H1.1.0.OUT.STARTUP.Q3 0.17.6
INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E 0.28.4
INT:PASS.DOUBLE.V0.1.0.OUT.STARTUP.Q2 0.26.4
INT:PASS.DOUBLE.V1.0.0.OUT.STARTUP.DONEIN 0.19.4
INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E 0.16.5
INT:PASS.IO.DOUBLE.0.E.0.0.IO.DBUF.V0 0.10.8
INT:PASS.IO.DOUBLE.0.E.1.0.IO.DBUF.H1 0.18.4
INT:PASS.IO.DOUBLE.0.S.1.0.IO.DBUF.V1 0.11.8
INT:PASS.IO.DOUBLE.0.S.2.0.IO.DBUF.H0 0.12.4
INT:PASS.IO.DOUBLE.1.E.0.0.IO.DBUF.V0 0.9.8
INT:PASS.IO.DOUBLE.1.E.1.0.IO.DBUF.H1 0.16.4
INT:PASS.IO.DOUBLE.1.S.1.0.IO.DBUF.V1 0.12.8
INT:PASS.IO.DOUBLE.1.S.2.0.IO.DBUF.H0 0.13.4
INT:PASS.SINGLE.H0.0.DEC.V0 0.0.7
INT:PASS.SINGLE.H0.0.LONG.IO.V0 0.14.7
INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S 0.14.6
INT:PASS.SINGLE.H0.0.OUT.STARTUP.Q1Q4 0.11.7
INT:PASS.SINGLE.H0.E.0.LONG.V0 0.30.6
INT:PASS.SINGLE.H1.0.DEC.V1 0.15.7
INT:PASS.SINGLE.H1.0.LONG.IO.V1 0.12.6
INT:PASS.SINGLE.H1.0.OUT.LR.IOB1.I1.S 0.7.7
INT:PASS.SINGLE.H1.0.OUT.STARTUP.Q3 0.17.7
INT:PASS.SINGLE.H1.E.0.LONG.V1 0.29.7
INT:PASS.SINGLE.H2.0.DEC.V0 0.1.7
INT:PASS.SINGLE.H2.0.LONG.IO.V0 0.13.7
INT:PASS.SINGLE.H2.0.LONG.V2 0.25.7
INT:PASS.SINGLE.H2.0.OUT.LR.IOB1.I2.S 0.13.6
INT:PASS.SINGLE.H2.0.OUT.STARTUP.Q1Q4 0.10.7
INT:PASS.SINGLE.H3.0.DEC.V1 0.16.7
INT:PASS.SINGLE.H3.0.LONG.IO.V1 0.11.6
INT:PASS.SINGLE.H3.0.LONG.V3 0.19.6
INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S 0.8.7
INT:PASS.SINGLE.H3.0.OUT.STARTUP.Q3 0.18.6
INT:PASS.SINGLE.V0.0.DEC.H1 0.28.5
INT:PASS.SINGLE.V0.0.LONG.IO.H0 0.31.5
INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E 0.29.5
INT:PASS.SINGLE.V0.0.OUT.STARTUP.Q2 0.30.5
INT:PASS.SINGLE.V1.0.DEC.H0 0.22.4
INT:PASS.SINGLE.V1.0.LONG.IO.H1 0.25.4
INT:PASS.SINGLE.V1.0.OUT.BT.IOB1.I1.E 0.24.4
INT:PASS.SINGLE.V1.0.OUT.STARTUP.DONEIN 0.23.4
INT:PASS.SINGLE.V2.0.DEC.H1 0.27.4
INT:PASS.SINGLE.V2.0.LONG.H2 0.30.7
INT:PASS.SINGLE.V2.0.LONG.IO.H0 0.31.4
INT:PASS.SINGLE.V2.0.OUT.BT.IOB1.I2.E 0.29.4
INT:PASS.SINGLE.V2.0.OUT.STARTUP.Q2 0.30.4
INT:PASS.SINGLE.V3.0.DEC.H0 0.19.5
INT:PASS.SINGLE.V3.0.LONG.H3 0.24.7
INT:PASS.SINGLE.V3.0.LONG.IO.H1 0.20.4
INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E 0.17.5
INT:PASS.SINGLE.V3.0.OUT.STARTUP.DONEIN 0.21.4
MISC:TCTEST 0.0.3
PULLUP_DEC0_H:ENABLE 0.5.4
PULLUP_DEC0_V:ENABLE 0.3.5
PULLUP_DEC1_H:ENABLE 0.2.5
PULLUP_DEC1_V:ENABLE 0.22.1
STARTUP:CRC 0.0.1
STARTUP:ENABLE.GSR 0.31.1
STARTUP:ENABLE.GTS 0.21.0
STARTUP:INV.GSR 0.31.0
STARTUP:INV.GTS 0.23.0
STARTUP:SYNC_TO_DONE 0.24.0
inverted ~[0]
INT:MUX.IMUX.BUFG.H 0.20.3 0.21.2 0.23.2 0.24.2 0.22.2 0.21.1
0.IO.DOUBLE.0.E.1 0 0 0 1 1 1
0.IO.DOUBLE.0.S.1 0 0 1 0 1 1
0.IO.DOUBLE.1.S.1 0 0 1 1 0 1
0.IO.DOUBLE.1.E.1 0 1 1 1 1 1
0.OUT.IOB.CLKIN.E 1 0 1 1 1 0
NONE 1 0 1 1 1 1
INT:MUX.IMUX.BUFG.V 0.2.3
0.OUT.IOB.CLKIN.S 0
NONE 1
INT:MUX.IMUX.READCLK.I 0.13.2 0.17.2 0.14.2 0.18.2
0.SINGLE.H1 0 0 1 1
0.SINGLE.H2 0 1 0 1
0.SINGLE.H3 0 1 1 0
0.SINGLE.H0 1 1 1 1
INT:MUX.IMUX.STARTUP.CLK 0.28.2 0.31.3 0.30.3 0.31.2
0.SINGLE.V0 0 0 1 1
0.SINGLE.V2 0 1 0 1
0.SINGLE.V3 0 1 1 0
0.SINGLE.V1 1 1 1 1
INT:MUX.IMUX.STARTUP.GSR 0.8.2 0.9.2 0.10.2 0.11.2 0.12.2
0.SINGLE.H1 0 0 0 1 1
0.SINGLE.H3 0 0 1 0 1
0.DOUBLE.V0.0 0 0 1 1 0
0.SINGLE.H0 0 1 1 1 1
0.LONG.V2 1 0 0 1 1
0.LONG.V3 1 0 1 0 1
0.DOUBLE.V1.1 1 0 1 1 0
0.SINGLE.H2 1 1 1 1 1
INT:MUX.IMUX.STARTUP.GTS 0.26.2 0.29.2 0.25.2 0.30.2 0.27.2
0.LONG.H2 0 0 0 1 1
0.SINGLE.V0 0 0 1 1 1
0.SINGLE.V3 0 1 0 0 1
0.LONG.H3 0 1 0 1 0
0.SINGLE.V2 0 1 1 0 1
0.DOUBLE.H0.1 0 1 1 1 0
0.SINGLE.V1 1 1 0 1 1
0.DOUBLE.H1.0 1 1 1 1 1
INT:MUX.IO.DBUF.H0 0.15.4 0.14.4
0.IO.DOUBLE.1.E.1 0 0
0.IO.DOUBLE.0.E.1 1 1
INT:MUX.IO.DBUF.H1 0.11.4 0.10.4
0.IO.DOUBLE.0.S.2 0 0
0.IO.DOUBLE.1.S.2 1 1
INT:MUX.IO.DBUF.V0 0.10.9 0.9.9
0.IO.DOUBLE.0.S.1 0 0
0.IO.DOUBLE.1.S.1 1 1
INT:MUX.IO.DBUF.V1 0.15.9 0.14.9
0.IO.DOUBLE.1.E.0 0 0
0.IO.DOUBLE.0.E.0 1 1
INT:MUX.LONG.H2 0.20.2 0.15.2 0.16.2 0.19.2
0.LONG.IO.V0 0 0 0 1
0.DEC.V1 0 0 1 0
0.OUT.STARTUP.Q3 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.H3 0.3.3 0.5.2 0.7.2 0.6.2
0.LONG.IO.V1 0 0 0 1
0.DEC.V0 0 0 1 0
0.OUT.STARTUP.Q3 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.H0 0.1.3 0.4.3 0.6.3 0.5.3 0.7.3 0.5.5 0.4.5
0.SINGLE.V2 0 0 0 1 1 1 1
0.LONG.V0 0 0 1 0 1 1 1
0.LONG.V2 0 0 1 1 0 1 1
0.SINGLE.V0 0 1 1 1 1 1 1
0.LONG.IO.V0 1 1 1 1 1 0 0
0.LONG.IO.V1 1 1 1 1 1 0 1
NONE 1 1 1 1 1 1 1
INT:MUX.LONG.IO.H1 0.8.3 0.9.3 0.10.3 0.12.3 0.11.3 0.6.5 0.8.5
0.SINGLE.V3 0 0 0 1 1 1 1
0.LONG.V1 0 0 1 0 1 1 1
0.LONG.V3 0 0 1 1 0 1 1
0.SINGLE.V1 0 1 1 1 1 1 1
0.LONG.IO.V1 1 1 1 1 1 0 0
0.LONG.IO.V0 1 1 1 1 1 0 1
NONE 1 1 1 1 1 1 1
INT:MUX.LONG.IO.V0 0.4.6 0.2.7 0.3.7 0.2.8 0.5.7 0.4.7
0.SINGLE.H0 0 0 0 1 1 1
0.LONG.H2 0 0 1 0 1 1
0.LONG.IO.H0 0 0 1 1 0 1
0.LONG.IO.H1 0 0 1 1 1 0
0.SINGLE.H2 0 1 1 1 1 1
NONE 1 1 1 1 1 1
INT:MUX.LONG.IO.V1 0.5.6 0.6.7 0.9.6 0.7.6 0.6.6 0.8.6
0.SINGLE.H1 0 0 0 1 1 1
0.LONG.H3 0 0 1 0 1 1
0.LONG.IO.H0 0 0 1 1 0 1
0.LONG.IO.H1 0 0 1 1 1 0
0.SINGLE.H3 0 1 1 1 1 1
NONE 1 1 1 1 1 1
INT:MUX.LONG.V0 0.27.5 0.24.5 0.25.5 0.26.5
0.LONG.IO.H0 0 0 0 1
0.DEC.H0 0 0 1 0
0.OUT.BT.IOB1.I2.E 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V1 0.15.5 0.13.5 0.14.5 0.17.4
0.LONG.IO.H1 0 0 0 1
0.DEC.H1 0 0 1 0
0.OUT.BT.IOB1.I2.E 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V2 0.11.5 0.9.5 0.12.5 0.10.5
0.LONG.IO.H0 0 0 0 1
0.DEC.H0 0 0 1 0
0.OUT.STARTUP.DONEIN 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V3 0.23.5 0.20.5 0.21.5 0.22.5
0.LONG.IO.H1 0 0 0 1
0.DEC.H1 0 0 1 0
0.OUT.STARTUP.DONEIN 0 1 1 1
NONE 1 1 1 1
OSC:ENABLE 0.0.9
non-inverted [0]
OSC:MUX.OUT0 0.0.5 0.1.9 0.2.9 0.1.6
OSC:MUX.OUT1 0.1.5 0.1.8 0.3.6 0.2.6
F500K 0 0 1 1
F16K 0 1 0 1
F490 0 1 1 0
F15 1 1 1 1
STARTUP:CONFIG_RATE 0.0.0
FAST 0
SLOW 1
STARTUP:DONE_ACTIVE 0.26.0 0.25.0
Q2 0 0
Q3 0 1
Q1Q4 1 0
Q0 1 1
STARTUP:GSR_INACTIVE 0.27.0 0.29.0
DONE_IN 0 0
Q3 0 1
Q1Q4 1 0
Q2 1 1
STARTUP:OUTPUTS_ACTIVE 0.29.1 0.30.0
Q3 0 0
DONE_IN 0 1
Q2 1 0
Q1Q4 1 1
STARTUP:STARTUP_CLK 0.23.1
CCLK 0
USERCLK 1

Tile CNR.TR

Cells: 2 IRIs: 0

Muxes

xc4000a CNR.TR muxes
DestinationSources
TCELL0:SINGLE.V0TCELL0:IO.DOUBLE.0.E.1, TCELL0:LONG.H0, TCELL0:LONG.IO.H0, TCELL0:DEC.H0, TCELL0:OUT.BT.IOB1.I2.E, TCELL0:OUT.UPDATE.O
TCELL0:SINGLE.V1TCELL0:IO.DOUBLE.0.N.0, TCELL0:IO.DOUBLE.0.E.2, TCELL0:LONG.H1, TCELL0:LONG.IO.H1, TCELL0:DEC.H1, TCELL0:OUT.BT.IOB1.I1.E, TCELL0:OUT.OSC.MUX1
TCELL0:SINGLE.V2TCELL0:IO.DOUBLE.1.E.1, TCELL0:LONG.IO.H0, TCELL0:DEC.H0, TCELL0:OUT.BT.IOB1.I2.E, TCELL0:OUT.UPDATE.O
TCELL0:SINGLE.V3TCELL0:IO.DOUBLE.1.N.0, TCELL0:IO.DOUBLE.1.E.2, TCELL0:LONG.IO.H1, TCELL0:DEC.H1, TCELL0:OUT.BT.IOB1.I1.E, TCELL0:OUT.OSC.MUX1
TCELL0:DOUBLE.V0.0TCELL0:IO.DOUBLE.1.N.0, TCELL0:IO.DOUBLE.1.E.1, TCELL0:IO.DOUBLE.1.E.2, TCELL0:OUT.BT.IOB1.I1.E
TCELL0:DOUBLE.V0.1TCELL0:IO.DOUBLE.0.N.0, TCELL0:IO.DOUBLE.0.E.1, TCELL0:IO.DOUBLE.0.E.2, TCELL0:OUT.UPDATE.O
TCELL0:DOUBLE.V1.0TCELL0:IO.DOUBLE.0.N.0, TCELL0:IO.DOUBLE.0.E.1, TCELL0:IO.DOUBLE.0.E.2, TCELL0:OUT.OSC.MUX1
TCELL0:DOUBLE.V1.1TCELL0:IO.DOUBLE.1.N.0, TCELL0:IO.DOUBLE.1.E.1, TCELL0:IO.DOUBLE.1.E.2, TCELL0:OUT.BT.IOB1.I2.E
TCELL0:IO.DOUBLE.0.N.0TCELL0:SINGLE.V1, TCELL0:DOUBLE.V0.1, TCELL0:DOUBLE.V1.0, TCELL0:IO.DOUBLE.0.E.2, TCELL0:IO.DBUF.H0
TCELL0:IO.DOUBLE.0.E.1TCELL0:SINGLE.V0, TCELL0:DOUBLE.V0.1, TCELL0:DOUBLE.V1.0
TCELL0:IO.DOUBLE.0.E.2TCELL0:SINGLE.V1, TCELL0:DOUBLE.V0.1, TCELL0:DOUBLE.V1.0, TCELL0:IO.DOUBLE.0.N.0, TCELL0:IO.DBUF.H1
TCELL0:IO.DOUBLE.1.N.0TCELL0:SINGLE.V3, TCELL0:DOUBLE.V0.0, TCELL0:DOUBLE.V1.1, TCELL0:IO.DOUBLE.1.E.2, TCELL0:IO.DBUF.H0
TCELL0:IO.DOUBLE.1.E.1TCELL0:SINGLE.V2, TCELL0:DOUBLE.V0.0, TCELL0:DOUBLE.V1.1
TCELL0:IO.DOUBLE.1.E.2TCELL0:SINGLE.V3, TCELL0:DOUBLE.V0.0, TCELL0:DOUBLE.V1.1, TCELL0:IO.DOUBLE.1.N.0, TCELL0:IO.DBUF.H1
TCELL0:IO.DBUF.H0TCELL0:IO.DOUBLE.0.E.2, TCELL0:IO.DOUBLE.1.E.2
TCELL0:IO.DBUF.H1TCELL0:IO.DOUBLE.0.N.0, TCELL0:IO.DOUBLE.1.N.0
TCELL0:LONG.H0TCELL0:SINGLE.V0, TCELL0:LONG.IO.V0, TCELL0:DEC.V1, TCELL0:OUT.LR.IOB1.I2
TCELL0:LONG.H1TCELL0:SINGLE.V1, TCELL0:LONG.IO.V1, TCELL0:DEC.V0, TCELL0:OUT.LR.IOB1.I2
TCELL0:LONG.V0TCELL0:LONG.IO.H0, TCELL0:DEC.H1, TCELL0:OUT.BT.IOB1.I2.E
TCELL0:LONG.V1TCELL0:LONG.IO.H1, TCELL0:DEC.H0, TCELL0:OUT.BT.IOB1.I2.E
TCELL0:LONG.V2TCELL0:LONG.IO.H0, TCELL0:DEC.H1, TCELL0:OUT.OSC.MUX1
TCELL0:LONG.V3TCELL0:LONG.IO.H1, TCELL0:DEC.H0, TCELL0:OUT.OSC.MUX1
TCELL0:LONG.IO.H0TCELL0:SINGLE.V0, TCELL0:SINGLE.V2, TCELL0:LONG.V0, TCELL0:LONG.V2, TCELL0:LONG.IO.V0, TCELL0:LONG.IO.V1
TCELL0:LONG.IO.H1TCELL0:SINGLE.V1, TCELL0:SINGLE.V3, TCELL0:LONG.V1, TCELL0:LONG.V3, TCELL0:LONG.IO.V0, TCELL0:LONG.IO.V1
TCELL0:LONG.IO.V0TCELL0:LONG.H0, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.H1
TCELL0:LONG.IO.V1TCELL0:LONG.H1, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.H1
TCELL0:IMUX.BUFG.HTCELL0:OUT.IOB.CLKIN.E
TCELL0:IMUX.BUFG.VTCELL0:IO.DOUBLE.0.E.1, TCELL0:IO.DOUBLE.0.E.2, TCELL0:IO.DOUBLE.1.E.1, TCELL0:IO.DOUBLE.1.E.2, TCELL0:OUT.IOB.CLKIN.N
TCELL0:IMUX.TDO.OTCELL0:SINGLE.V0, TCELL0:SINGLE.V1, TCELL0:SINGLE.V2, TCELL0:SINGLE.V3, TCELL0:LONG.H0, TCELL0:LONG.H1, TCELL1:DOUBLE.H0.0, TCELL1:DOUBLE.H1.1
TCELL0:IMUX.TDO.TTCELL0:DOUBLE.V0.0, TCELL0:DOUBLE.V1.1, TCELL0:LONG.V2, TCELL0:LONG.V3, TCELL1:SINGLE.H0, TCELL1:SINGLE.H1, TCELL1:SINGLE.H2, TCELL1:SINGLE.H3

Bel PULLUP_DEC0_H

xc4000a CNR.TR bel PULLUP_DEC0_H
PinDirectionWires
OoutputTCELL0:DEC.H0

Bel PULLUP_DEC1_H

xc4000a CNR.TR bel PULLUP_DEC1_H
PinDirectionWires
OoutputTCELL0:DEC.H1

Bel PULLUP_DEC0_V

xc4000a CNR.TR bel PULLUP_DEC0_V
PinDirectionWires
OoutputTCELL0:DEC.V0

Bel PULLUP_DEC1_V

xc4000a CNR.TR bel PULLUP_DEC1_V
PinDirectionWires
OoutputTCELL0:DEC.V1

Bel BUFGLS_H

xc4000a CNR.TR bel BUFGLS_H
PinDirectionWires
IinputTCELL0:IMUX.BUFG.H

Bel BUFGLS_V

xc4000a CNR.TR bel BUFGLS_V
PinDirectionWires
IinputTCELL0:IMUX.BUFG.V

Bel COUT

xc4000a CNR.TR bel COUT
PinDirectionWires

Bel UPDATE

xc4000a CNR.TR bel UPDATE
PinDirectionWires
OoutputTCELL0:OUT.UPDATE.O

Bel OSC

xc4000a CNR.TR bel OSC
PinDirectionWires
F8MoutputTCELL0:OUT.LR.IOB1.I1
OUT0outputTCELL0:OUT.LR.IOB1.I2
OUT1outputTCELL0:OUT.OSC.MUX1

Bel TDO

xc4000a CNR.TR bel TDO
PinDirectionWires
OinputTCELL0:IMUX.TDO.O
TinputTCELL0:IMUX.TDO.T

Bel wires

xc4000a CNR.TR bel wires
WirePins
TCELL0:DEC.H0PULLUP_DEC0_H.O
TCELL0:DEC.H1PULLUP_DEC1_H.O
TCELL0:DEC.V0PULLUP_DEC0_V.O
TCELL0:DEC.V1PULLUP_DEC1_V.O
TCELL0:IMUX.BUFG.HBUFGLS_H.I
TCELL0:IMUX.BUFG.VBUFGLS_V.I
TCELL0:IMUX.TDO.OTDO.O
TCELL0:IMUX.TDO.TTDO.T
TCELL0:OUT.LR.IOB1.I1OSC.F8M
TCELL0:OUT.LR.IOB1.I2OSC.OUT0
TCELL0:OUT.OSC.MUX1OSC.OUT1
TCELL0:OUT.UPDATE.OUPDATE.O

Bitstream

xc4000a CNR.TR bittile 0
BitFrame
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5 - BSCAN:ENABLE ~TDO:ENABLE.O - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - INT:MUX.IMUX.TDO.O[0] INT:MUX.IMUX.BUFG.V[5] - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 INT:MUX.IMUX.TDO.O[2] INT:MUX.LONG.H0[0] INT:MUX.IMUX.TDO.O[4] INT:MUX.LONG.H0[1] INT:MUX.IMUX.BUFG.V[1] INT:MUX.IMUX.BUFG.V[2] INT:MUX.IMUX.BUFG.V[3] INT:MUX.LONG.H0[3] INT:MUX.IMUX.BUFG.V[0] INT:MUX.IMUX.BUFG.V[4] INT:MUX.LONG.H0[2] INT:MUX.LONG.IO.V0[1] INT:MUX.LONG.IO.V0[0] INT:MUX.LONG.IO.V0[2] INT:MUX.LONG.IO.V0[3] INT:MUX.LONG.IO.V1[3] INT:MUX.LONG.IO.V1[1] INT:MUX.LONG.IO.V1[0] INT:MUX.LONG.IO.V1[2] INT:MUX.IMUX.TDO.T[3] INT:MUX.IMUX.TDO.T[0] INT:MUX.IMUX.TDO.T[1] INT:MUX.IMUX.TDO.T[4] INT:MUX.IMUX.TDO.T[2] INT:MUX.LONG.H1[1] INT:MUX.LONG.H1[0] INT:MUX.LONG.H1[2] - - - - -
2 INT:MUX.IMUX.TDO.O[3] INT:MUX.IMUX.TDO.O[1] ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.N.0 ~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.N.0 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.N.0 ~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.2 ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.2 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.2 ~INT:BIPASS.IO.DOUBLE.0.N.0.IO.DOUBLE.0.E.2 ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.1 ~PULLUP_DEC1_V:ENABLE ~INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.E.1 ~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.N.0 ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.N.0 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.N.0 ~INT:BIPASS.IO.DOUBLE.1.N.0.IO.DOUBLE.1.E.2 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.2 ~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.2 INT:MUX.LONG.IO.H1[3] INT:MUX.LONG.IO.H1[2] INT:MUX.LONG.IO.H1[4] INT:MUX.LONG.IO.H1[5] INT:MUX.LONG.IO.H1[6] INT:MUX.LONG.IO.H0[2] INT:MUX.LONG.IO.H0[4] INT:MUX.LONG.IO.H0[3] INT:MUX.LONG.IO.H0[5] INT:MUX.LONG.H1[3] INT:MUX.IMUX.BUFG.H[0] INT:MUX.LONG.IO.H0[6] ~TDO:ENABLE.T
1 ~INT:PASS.SINGLE.V2.0.LONG.IO.H0 ~INT:PASS.SINGLE.V2.0.OUT.UPDATE.O ~INT:PASS.SINGLE.V2.0.OUT.BT.IOB1.I2.E ~INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E ~INT:PASS.SINGLE.V2.0.DEC.H0 ~INT:PASS.DOUBLE.V0.1.0.OUT.UPDATE.O ~INT:PASS.SINGLE.V1.0.LONG.IO.H1 ~INT:PASS.SINGLE.V1.0.OUT.BT.IOB1.I1.E ~INT:PASS.SINGLE.V1.0.OUT.OSC.MUX1 ~INT:PASS.SINGLE.V1.0.DEC.H1 ~INT:PASS.SINGLE.V3.0.OUT.OSC.MUX1 ~INT:PASS.SINGLE.V3.0.LONG.IO.H1 ~INT:PASS.DOUBLE.V1.0.0.OUT.OSC.MUX1 ~INT:PASS.IO.DOUBLE.0.E.2.0.IO.DBUF.H1 INT:MUX.LONG.V1[0] ~INT:PASS.IO.DOUBLE.1.E.2.0.IO.DBUF.H1 INT:MUX.IO.DBUF.H0[1] INT:MUX.IO.DBUF.H0[0] ~INT:PASS.IO.DOUBLE.1.N.0.0.IO.DBUF.H0 ~INT:PASS.IO.DOUBLE.0.N.0.0.IO.DBUF.H0 INT:MUX.IO.DBUF.H1[1] INT:MUX.IO.DBUF.H1[0] ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.2 ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.1 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1 ~INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.E.1 ~PULLUP_DEC1_H:ENABLE TDO:PULL[1] TDO:PULL[0] - - -
0 ~INT:PASS.SINGLE.V0.0.LONG.IO.H0 ~INT:PASS.SINGLE.V0.0.OUT.UPDATE.O ~INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E ~INT:PASS.SINGLE.V0.0.DEC.H0 INT:MUX.LONG.V0[3] INT:MUX.LONG.V0[0] INT:MUX.LONG.V0[1] INT:MUX.LONG.V0[2] INT:MUX.LONG.V3[3] INT:MUX.LONG.V3[0] INT:MUX.LONG.V3[1] INT:MUX.LONG.V3[2] ~INT:PASS.SINGLE.V3.0.DEC.H1 ~INT:BUF.LONG.H1.0.SINGLE.V1 ~INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E ~INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E INT:MUX.LONG.V1[3] INT:MUX.LONG.V1[1] INT:MUX.LONG.V1[2] INT:MUX.LONG.V2[1] INT:MUX.LONG.V2[3] INT:MUX.LONG.V2[0] INT:MUX.LONG.V2[2] INT:MUX.LONG.IO.H1[0] ~MISC:TM_RIGHT INT:MUX.LONG.IO.H1[1] INT:MUX.LONG.IO.H0[1] INT:MUX.LONG.IO.H0[0] ~PULLUP_DEC0_V:ENABLE ~PULLUP_DEC0_H:ENABLE ~MISC:TAC READCLK:READ_CLK[0]
xc4000a CNR.TR bittile 1
BitFrame
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
9 ~INT:PASS.SINGLE.V0.0.LONG.H0 ~INT:BUF.LONG.H0.0.SINGLE.V0 - - - - - - - ~INT:PASS.SINGLE.V1.0.LONG.H1 - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BSCAN:ENABLE 0.30.5
non-inverted [0]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1 0.7.1
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.2 0.14.2
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.N.0 0.16.2
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1 0.22.2
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.2 0.25.2
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.N.0 0.29.2
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.1 0.21.2
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.2 0.24.2
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.N.0 0.27.2
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.1 0.8.1
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.2 0.9.1
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.N.0 0.17.2
INT:BIPASS.IO.DOUBLE.0.N.0.IO.DOUBLE.0.E.2 0.23.2
INT:BIPASS.IO.DOUBLE.1.N.0.IO.DOUBLE.1.E.2 0.15.2
INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.E.1 0.19.2
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.2 0.26.2
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.N.0 0.28.2
INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.E.1 0.6.1
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.2 0.13.2
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.N.0 0.18.2
INT:BUF.LONG.H0.0.SINGLE.V0 1.29.9
INT:BUF.LONG.H1.0.SINGLE.V1 0.18.0
INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E 0.28.1
INT:PASS.DOUBLE.V0.1.0.OUT.UPDATE.O 0.26.1
INT:PASS.DOUBLE.V1.0.0.OUT.OSC.MUX1 0.19.1
INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E 0.16.0
INT:PASS.IO.DOUBLE.0.E.2.0.IO.DBUF.H1 0.18.1
INT:PASS.IO.DOUBLE.0.N.0.0.IO.DBUF.H0 0.12.1
INT:PASS.IO.DOUBLE.1.E.2.0.IO.DBUF.H1 0.16.1
INT:PASS.IO.DOUBLE.1.N.0.0.IO.DBUF.H0 0.13.1
INT:PASS.SINGLE.V0.0.DEC.H0 0.28.0
INT:PASS.SINGLE.V0.0.LONG.H0 1.30.9
INT:PASS.SINGLE.V0.0.LONG.IO.H0 0.31.0
INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E 0.29.0
INT:PASS.SINGLE.V0.0.OUT.UPDATE.O 0.30.0
INT:PASS.SINGLE.V1.0.DEC.H1 0.22.1
INT:PASS.SINGLE.V1.0.LONG.H1 1.21.9
INT:PASS.SINGLE.V1.0.LONG.IO.H1 0.25.1
INT:PASS.SINGLE.V1.0.OUT.BT.IOB1.I1.E 0.24.1
INT:PASS.SINGLE.V1.0.OUT.OSC.MUX1 0.23.1
INT:PASS.SINGLE.V2.0.DEC.H0 0.27.1
INT:PASS.SINGLE.V2.0.LONG.IO.H0 0.31.1
INT:PASS.SINGLE.V2.0.OUT.BT.IOB1.I2.E 0.29.1
INT:PASS.SINGLE.V2.0.OUT.UPDATE.O 0.30.1
INT:PASS.SINGLE.V3.0.DEC.H1 0.19.0
INT:PASS.SINGLE.V3.0.LONG.IO.H1 0.20.1
INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E 0.17.0
INT:PASS.SINGLE.V3.0.OUT.OSC.MUX1 0.21.1
MISC:TAC 0.1.0
MISC:TM_RIGHT 0.7.0
PULLUP_DEC0_H:ENABLE 0.2.0
PULLUP_DEC0_V:ENABLE 0.3.0
PULLUP_DEC1_H:ENABLE 0.5.1
PULLUP_DEC1_V:ENABLE 0.20.2
TDO:ENABLE.O 0.29.5
TDO:ENABLE.T 0.0.2
inverted ~[0]
INT:MUX.IMUX.BUFG.H 0.2.2
0.OUT.IOB.CLKIN.E 0
NONE 1
INT:MUX.IMUX.BUFG.V 0.29.4 0.22.3 0.25.3 0.26.3 0.27.3 0.23.3
0.IO.DOUBLE.0.E.2 0 0 0 1 1 1
0.IO.DOUBLE.1.E.1 0 0 1 0 1 1
0.IO.DOUBLE.1.E.2 0 0 1 1 0 1
0.IO.DOUBLE.0.E.1 0 1 1 1 1 1
0.OUT.IOB.CLKIN.N 1 0 1 1 1 0
NONE 1 0 1 1 1 1
INT:MUX.IMUX.TDO.O 0.29.3 0.31.2 0.31.3 0.30.2 0.30.4
0.LONG.H0 0 0 0 1 1
0.SINGLE.V0 0 0 1 1 1
0.SINGLE.V3 0 1 0 0 1
0.LONG.H1 0 1 0 1 0
0.SINGLE.V2 0 1 1 0 1
1.DOUBLE.H1.1 0 1 1 1 0
0.SINGLE.V1 1 1 0 1 1
1.DOUBLE.H0.0 1 1 1 1 1
INT:MUX.IMUX.TDO.T 0.9.3 0.12.3 0.8.3 0.10.3 0.11.3
0.DOUBLE.V0.0 0 0 0 1 1
0.DOUBLE.V1.1 0 0 1 1 1
1.SINGLE.H1 0 1 0 0 1
1.SINGLE.H3 0 1 0 1 0
0.LONG.V2 0 1 1 0 1
0.LONG.V3 0 1 1 1 0
1.SINGLE.H0 1 1 0 1 1
1.SINGLE.H2 1 1 1 1 1
INT:MUX.IO.DBUF.H0 0.15.1 0.14.1
0.IO.DOUBLE.1.E.2 0 0
0.IO.DOUBLE.0.E.2 1 1
INT:MUX.IO.DBUF.H1 0.11.1 0.10.1
0.IO.DOUBLE.0.N.0 0 0
0.IO.DOUBLE.1.N.0 1 1
INT:MUX.LONG.H0 0.24.3 0.21.3 0.28.3 0.30.3
0.LONG.IO.V0 0 0 0 1
0.DEC.V1 0 0 1 0
0.OUT.LR.IOB1.I2 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.H1 0.3.2 0.5.3 0.7.3 0.6.3
0.LONG.IO.V1 0 0 0 1
0.DEC.V0 0 0 1 0
0.OUT.LR.IOB1.I2 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.H0 0.1.2 0.4.2 0.6.2 0.5.2 0.7.2 0.5.0 0.4.0
0.SINGLE.V2 0 0 0 1 1 1 1
0.LONG.V0 0 0 1 0 1 1 1
0.LONG.V2 0 0 1 1 0 1 1
0.SINGLE.V0 0 1 1 1 1 1 1
0.LONG.IO.V0 1 1 1 1 1 0 0
0.LONG.IO.V1 1 1 1 1 1 0 1
NONE 1 1 1 1 1 1 1
INT:MUX.LONG.IO.H1 0.8.2 0.9.2 0.10.2 0.12.2 0.11.2 0.6.0 0.8.0
0.SINGLE.V3 0 0 0 1 1 1 1
0.LONG.V1 0 0 1 0 1 1 1
0.LONG.V3 0 0 1 1 0 1 1
0.SINGLE.V1 0 1 1 1 1 1 1
0.LONG.IO.V1 1 1 1 1 1 0 0
0.LONG.IO.V0 1 1 1 1 1 0 1
NONE 1 1 1 1 1 1 1
INT:MUX.LONG.IO.V0 0.17.3 0.18.3 0.20.3 0.19.3
0.LONG.H0 0 0 0 1
0.LONG.IO.H1 0 0 1 0
0.LONG.IO.H0 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.V1 0.16.3 0.13.3 0.15.3 0.14.3
0.LONG.H1 0 0 0 1
0.LONG.IO.H0 0 0 1 0
0.LONG.IO.H1 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V0 0.27.0 0.24.0 0.25.0 0.26.0
0.LONG.IO.H0 0 0 0 1
0.DEC.H1 0 0 1 0
0.OUT.BT.IOB1.I2.E 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V1 0.15.0 0.13.0 0.14.0 0.17.1
0.LONG.IO.H1 0 0 0 1
0.DEC.H0 0 0 1 0
0.OUT.BT.IOB1.I2.E 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V2 0.11.0 0.9.0 0.12.0 0.10.0
0.LONG.IO.H0 0 0 0 1
0.DEC.H1 0 0 1 0
0.OUT.OSC.MUX1 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V3 0.23.0 0.20.0 0.21.0 0.22.0
0.LONG.IO.H1 0 0 0 1
0.DEC.H0 0 0 1 0
0.OUT.OSC.MUX1 0 1 1 1
NONE 1 1 1 1
READCLK:READ_CLK 0.0.0
RDBK 0
CCLK 1
TDO:PULL 0.4.1 0.3.1
PULLUP 0 1
PULLDOWN 1 0
PULLNONE 1 1