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Corners

Tile CNR.BL

Cells: 2

Switchbox INT

xc4000a CNR.BL switchbox INT
DestinationSourceKind
CELL0.SINGLE.H0CELL0.LONG.IO.V0pass transistor
CELL0.DEC.V1pass transistor
CELL0.OUT.LR.IOB1.I2.Spass transistor
CELL0.OUT.MD0.Ipass transistor
CELL0.IO.DOUBLE.0.S.0bidirectional pass transistor
CELL0.IO.DOUBLE.0.W.2bidirectional pass transistor
CELL0.SINGLE.H1CELL0.LONG.IO.V1pass transistor
CELL0.DEC.V0pass transistor
CELL0.OUT.LR.IOB1.I1.Spass transistor
CELL0.OUT.RDBK.DATApass transistor
CELL0.IO.DOUBLE.0.W.1bidirectional pass transistor
CELL0.SINGLE.H2CELL0.LONG.IO.V0pass transistor
CELL0.DEC.V1pass transistor
CELL0.OUT.LR.IOB1.I2.Spass transistor
CELL0.OUT.MD0.Ipass transistor
CELL0.IO.DOUBLE.1.S.0bidirectional pass transistor
CELL0.IO.DOUBLE.1.W.2bidirectional pass transistor
CELL0.SINGLE.H3CELL0.LONG.IO.V1pass transistor
CELL0.DEC.V0pass transistor
CELL0.OUT.LR.IOB1.I1.Spass transistor
CELL0.OUT.RDBK.DATApass transistor
CELL0.IO.DOUBLE.1.W.1bidirectional pass transistor
CELL0.DOUBLE.H0.0CELL0.OUT.LR.IOB1.I1.Spass transistor
CELL0.IO.DOUBLE.0.S.0bidirectional pass transistor
CELL0.IO.DOUBLE.0.W.1bidirectional pass transistor
CELL0.IO.DOUBLE.0.W.2bidirectional pass transistor
CELL0.DOUBLE.H0.1CELL0.OUT.MD0.Ipass transistor
CELL0.IO.DOUBLE.1.S.0bidirectional pass transistor
CELL0.IO.DOUBLE.1.W.1bidirectional pass transistor
CELL0.IO.DOUBLE.1.W.2bidirectional pass transistor
CELL0.DOUBLE.H1.0CELL0.OUT.RDBK.DATApass transistor
CELL0.IO.DOUBLE.1.S.0bidirectional pass transistor
CELL0.IO.DOUBLE.1.W.1bidirectional pass transistor
CELL0.IO.DOUBLE.1.W.2bidirectional pass transistor
CELL0.DOUBLE.H1.1CELL0.OUT.LR.IOB1.I2.Spass transistor
CELL0.IO.DOUBLE.0.S.0bidirectional pass transistor
CELL0.IO.DOUBLE.0.W.1bidirectional pass transistor
CELL0.IO.DOUBLE.0.W.2bidirectional pass transistor
CELL0.IO.DOUBLE.0.S.0CELL0.IO.DBUF.V1pass transistor
CELL0.SINGLE.H0bidirectional pass transistor
CELL0.DOUBLE.H0.0bidirectional pass transistor
CELL0.DOUBLE.H1.1bidirectional pass transistor
CELL0.IO.DOUBLE.0.W.2bidirectional pass transistor
CELL0.IO.DOUBLE.0.W.1CELL0.SINGLE.H1bidirectional pass transistor
CELL0.DOUBLE.H0.0bidirectional pass transistor
CELL0.DOUBLE.H1.1bidirectional pass transistor
CELL0.IO.DOUBLE.0.W.2CELL0.IO.DBUF.V0pass transistor
CELL0.SINGLE.H0bidirectional pass transistor
CELL0.DOUBLE.H0.0bidirectional pass transistor
CELL0.DOUBLE.H1.1bidirectional pass transistor
CELL0.IO.DOUBLE.0.S.0bidirectional pass transistor
CELL0.IO.DOUBLE.1.S.0CELL0.IO.DBUF.V1pass transistor
CELL0.SINGLE.H2bidirectional pass transistor
CELL0.DOUBLE.H0.1bidirectional pass transistor
CELL0.DOUBLE.H1.0bidirectional pass transistor
CELL0.IO.DOUBLE.1.W.2bidirectional pass transistor
CELL0.IO.DOUBLE.1.W.1CELL0.SINGLE.H3bidirectional pass transistor
CELL0.DOUBLE.H0.1bidirectional pass transistor
CELL0.DOUBLE.H1.0bidirectional pass transistor
CELL0.IO.DOUBLE.1.W.2CELL0.IO.DBUF.V0pass transistor
CELL0.SINGLE.H2bidirectional pass transistor
CELL0.DOUBLE.H0.1bidirectional pass transistor
CELL0.DOUBLE.H1.0bidirectional pass transistor
CELL0.IO.DOUBLE.1.S.0bidirectional pass transistor
CELL0.IO.DBUF.V0CELL0.IO.DOUBLE.0.S.0mux
CELL0.IO.DOUBLE.1.S.0mux
CELL0.IO.DBUF.V1CELL0.IO.DOUBLE.0.W.2mux
CELL0.IO.DOUBLE.1.W.2mux
CELL0.LONG.H2CELL0.LONG.IO.V0mux
CELL0.DEC.V0mux
CELL0.OUT.RDBK.DATAmux
CELL0.LONG.H3CELL0.LONG.IO.V1mux
CELL0.DEC.V1mux
CELL0.OUT.RDBK.DATAmux
CELL0.LONG.IO.H0CELL0.LONG.IO.V0mux
CELL0.LONG.IO.V1mux
CELL0.LONG.IO.H1CELL0.LONG.IO.V0mux
CELL0.LONG.IO.V1mux
CELL0.LONG.IO.V0CELL0.SINGLE.H0mux
CELL0.SINGLE.H2mux
CELL0.LONG.H2mux
CELL0.LONG.IO.H0mux
CELL0.LONG.IO.H1mux
CELL0.LONG.IO.V1CELL0.SINGLE.H1mux
CELL0.SINGLE.H3mux
CELL0.LONG.H3mux
CELL0.LONG.IO.H0mux
CELL0.LONG.IO.H1mux
CELL0.IMUX.IOB1.O1CELL0.SINGLE.H0mux
CELL0.SINGLE.H1mux
CELL0.SINGLE.H2mux
CELL0.SINGLE.H3mux
CELL1.DOUBLE.V0.1mux
CELL1.DOUBLE.V1.0mux
CELL1.LONG.V0mux
CELL1.LONG.V1mux
CELL0.IMUX.IOB1.IKCELL0.DOUBLE.H0.0mux
CELL0.DOUBLE.H1.1mux
CELL0.LONG.H2mux
CELL0.LONG.H3mux
CELL1.SINGLE.V0mux
CELL1.SINGLE.V1mux
CELL1.SINGLE.V2mux
CELL1.SINGLE.V3mux
CELL0.IMUX.BUFG.HCELL0.OUT.IOB.CLKIN.Wmux
CELL0.IMUX.BUFG.VCELL0.IO.DOUBLE.0.S.0mux
CELL0.IO.DOUBLE.0.W.1mux
CELL0.IO.DOUBLE.1.S.0mux
CELL0.IO.DOUBLE.1.W.1mux
CELL0.OUT.IOB.CLKIN.Smux
CELL0.IMUX.RDBK.TRIGCELL0.SINGLE.H0mux
CELL0.SINGLE.H1mux
CELL0.SINGLE.H2mux
CELL0.SINGLE.H3mux

Bel PULLUP_DEC0_H

xc4000a CNR.BL bel PULLUP_DEC0_H
PinDirectionWires
OoutputCELL0.DEC.H0

Bel PULLUP_DEC1_H

xc4000a CNR.BL bel PULLUP_DEC1_H
PinDirectionWires
OoutputCELL0.DEC.H1

Bel PULLUP_DEC0_V

xc4000a CNR.BL bel PULLUP_DEC0_V
PinDirectionWires
OoutputCELL0.DEC.V0

Bel PULLUP_DEC1_V

xc4000a CNR.BL bel PULLUP_DEC1_V
PinDirectionWires
OoutputCELL0.DEC.V1

Bel BUFGLS_H

xc4000a CNR.BL bel BUFGLS_H
PinDirectionWires
IinputCELL0.IMUX.BUFG.H

Bel BUFGLS_V

xc4000a CNR.BL bel BUFGLS_V
PinDirectionWires
IinputCELL0.IMUX.BUFG.V

Bel CIN

xc4000a CNR.BL bel CIN
PinDirectionWires

Bel MD0

xc4000a CNR.BL bel MD0
PinDirectionWires
IoutputCELL0.OUT.MD0.I

Bel MD1

xc4000a CNR.BL bel MD1
PinDirectionWires
OinputCELL0.IMUX.IOB1.O1
TinputCELL0.IMUX.IOB1.IK

Bel MD2

xc4000a CNR.BL bel MD2
PinDirectionWires
IoutputCELL0.OUT.BT.IOB1.I1

Bel RDBK

xc4000a CNR.BL bel RDBK
PinDirectionWires
DATAoutputCELL0.OUT.RDBK.DATA
RIPoutputCELL0.OUT.BT.IOB1.I2
TRIGinputCELL0.IMUX.RDBK.TRIG

Bel wires

xc4000a CNR.BL bel wires
WirePins
CELL0.DEC.H0PULLUP_DEC0_H.O
CELL0.DEC.H1PULLUP_DEC1_H.O
CELL0.DEC.V0PULLUP_DEC0_V.O
CELL0.DEC.V1PULLUP_DEC1_V.O
CELL0.IMUX.IOB1.O1MD1.O
CELL0.IMUX.IOB1.IKMD1.T
CELL0.IMUX.BUFG.HBUFGLS_H.I
CELL0.IMUX.BUFG.VBUFGLS_V.I
CELL0.IMUX.RDBK.TRIGRDBK.TRIG
CELL0.OUT.BT.IOB1.I1MD2.I
CELL0.OUT.BT.IOB1.I2RDBK.RIP
CELL0.OUT.MD0.IMD0.I
CELL0.OUT.RDBK.DATARDBK.DATA

Bitstream

xc4000a CNR.BL rect R0
BitFrame
F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 ~MD1:ENABLE.O ~MD1:ENABLE.T - ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.S.0 ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.W.1 ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.W.2 ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.1 ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.S.0 ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.2 - - - ~INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.W.1 ~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.W.2 INT:MUX.IO.DBUF.V1[1] INT:MUX.IO.DBUF.V1[0] ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.W.2 ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.W.1 ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.1 ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.2 ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.S.0
B8 - - - - - ~INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.W.1 ~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.0 ~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.W.2 ~INT:BIPASS.IO.DOUBLE.1.S.0.IO.DOUBLE.1.W.2 ~INT:PASS.IO.DOUBLE.1.W.2.0.IO.DBUF.V0 ~INT:PASS.IO.DOUBLE.0.W.2.0.IO.DBUF.V0 INT:MUX.IO.DBUF.V0[1] INT:MUX.IO.DBUF.V0[0] ~INT:PASS.IO.DOUBLE.0.S.0.0.IO.DBUF.V1 ~INT:PASS.IO.DOUBLE.1.S.0.0.IO.DBUF.V1 ~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.0 ~INT:BIPASS.IO.DOUBLE.0.S.0.IO.DOUBLE.0.W.2 ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.S.0 - - ~INT:PASS.DOUBLE.H0.1.0.OUT.MD0.I
B7 - - ~INT:PASS.SINGLE.H0.0.DEC.V1 ~INT:PASS.SINGLE.H2.0.DEC.V1 ~INT:PASS.SINGLE.H3.0.OUT.RDBK.DATA ~INT:PASS.SINGLE.H1.0.OUT.RDBK.DATA ~INT:PASS.DOUBLE.H1.0.0.OUT.RDBK.DATA ~INT:PASS.SINGLE.H1.0.OUT.LR.IOB1.I1.S ~INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S ~INT:PASS.DOUBLE.H0.0.0.OUT.LR.IOB1.I1.S ~INT:PASS.SINGLE.H2.0.OUT.MD0.I ~INT:PASS.SINGLE.H0.0.OUT.MD0.I ~INT:PASS.DOUBLE.H1.1.0.OUT.LR.IOB1.I2.S ~INT:PASS.SINGLE.H3.0.LONG.IO.V1 ~INT:PASS.SINGLE.H1.0.LONG.IO.V1 ~INT:PASS.SINGLE.H2.0.OUT.LR.IOB1.I2.S ~INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S ~INT:PASS.SINGLE.H2.0.LONG.IO.V0 ~INT:PASS.SINGLE.H0.0.LONG.IO.V0 ~INT:PASS.SINGLE.H1.0.DEC.V0 ~INT:PASS.SINGLE.H3.0.DEC.V0
B6 - - - ~RDBK:ENABLE INT:MUX.IMUX.RDBK.TRIG[0] INT:MUX.IMUX.RDBK.TRIG[1] INT:MUX.IMUX.RDBK.TRIG[2] INT:MUX.IMUX.RDBK.TRIG[3] INT:MUX.LONG.H3[0] INT:MUX.LONG.H3[1] INT:MUX.LONG.H3[2] INT:MUX.LONG.H3[3] - - - INT:MUX.LONG.H2[3] INT:MUX.LONG.H2[0] INT:MUX.LONG.H2[1] - INT:MUX.LONG.H2[2] -
B5 MD1:PULL[1] MD1:PULL[0] ~MISC:READ_CAPTURE - ~PULLUP_DEC1_V:ENABLE INT:MUX.IMUX.BUFG.H[0] INT:MUX.LONG.IO.V0[3] INT:MUX.LONG.IO.V0[4] INT:MUX.LONG.IO.V1[3] INT:MUX.LONG.IO.V1[4] - - - - - - - - ~PULLUP_DEC0_V:ENABLE - -
B4 - - - - - INT:MUX.LONG.IO.V0[1] INT:MUX.LONG.IO.V1[1] INT:MUX.LONG.IO.V1[2] INT:MUX.LONG.IO.V1[0] INT:MUX.LONG.IO.H0[1] INT:MUX.LONG.IO.H1[1] INT:MUX.LONG.IO.V1[5] INT:MUX.LONG.IO.H1[0] INT:MUX.LONG.IO.V0[5] INT:MUX.LONG.IO.H0[0] ~MISC:TM_BOT - ~PULLUP_DEC1_H:ENABLE ~PULLUP_DEC0_H:ENABLE - -
B3 - INT:MUX.LONG.IO.V0[0] INT:MUX.LONG.IO.V0[2] INT:MUX.IMUX.IOB1.IK[3] INT:MUX.IMUX.IOB1.IK[1] INT:MUX.IMUX.IOB1.IK[2] INT:MUX.IMUX.IOB1.IK[4] INT:MUX.IMUX.IOB1.IK[0] INT:MUX.IMUX.IOB1.O1[4] INT:MUX.IMUX.IOB1.O1[2] INT:MUX.IMUX.IOB1.O1[0] INT:MUX.IMUX.IOB1.O1[1] INT:MUX.IMUX.IOB1.O1[3] INT:MUX.IMUX.BUFG.V[0] INT:MUX.IMUX.BUFG.V[5] INT:MUX.IMUX.BUFG.V[1] INT:MUX.IMUX.BUFG.V[3] INT:MUX.IMUX.BUFG.V[2] INT:MUX.IMUX.BUFG.V[4] - -
B2 - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - -
B0 - - ~MISC:READ_ABORT - - - - - - - - - - - - - - - - - -
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.S.0 0.F0.B9
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.1 0.F2.B9
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.2 0.F1.B9
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.S.0 0.F13.B9
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.1 0.F14.B9
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.2 0.F12.B9
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.S.0 0.F17.B9
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.W.1 0.F16.B9
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.1.W.2 0.F15.B9
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.S.0 0.F3.B8
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.W.1 0.F3.B9
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.0.W.2 0.F4.B9
INT:BIPASS.IO.DOUBLE.0.S.0.IO.DOUBLE.0.W.2 0.F4.B8
INT:BIPASS.IO.DOUBLE.1.S.0.IO.DOUBLE.1.W.2 0.F12.B8
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.0 0.F5.B8
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.W.2 0.F7.B9
INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.W.1 0.F8.B9
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.0 0.F14.B8
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.W.2 0.F13.B8
INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.W.1 0.F15.B8
INT:PASS.DOUBLE.H0.0.0.OUT.LR.IOB1.I1.S 0.F11.B7
INT:PASS.DOUBLE.H0.1.0.OUT.MD0.I 0.F0.B8
INT:PASS.DOUBLE.H1.0.0.OUT.RDBK.DATA 0.F14.B7
INT:PASS.DOUBLE.H1.1.0.OUT.LR.IOB1.I2.S 0.F8.B7
INT:PASS.IO.DOUBLE.0.S.0.0.IO.DBUF.V1 0.F7.B8
INT:PASS.IO.DOUBLE.0.W.2.0.IO.DBUF.V0 0.F10.B8
INT:PASS.IO.DOUBLE.1.S.0.0.IO.DBUF.V1 0.F6.B8
INT:PASS.IO.DOUBLE.1.W.2.0.IO.DBUF.V0 0.F11.B8
INT:PASS.SINGLE.H0.0.DEC.V1 0.F18.B7
INT:PASS.SINGLE.H0.0.LONG.IO.V0 0.F2.B7
INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S 0.F4.B7
INT:PASS.SINGLE.H0.0.OUT.MD0.I 0.F9.B7
INT:PASS.SINGLE.H1.0.DEC.V0 0.F1.B7
INT:PASS.SINGLE.H1.0.LONG.IO.V1 0.F6.B7
INT:PASS.SINGLE.H1.0.OUT.LR.IOB1.I1.S 0.F13.B7
INT:PASS.SINGLE.H1.0.OUT.RDBK.DATA 0.F15.B7
INT:PASS.SINGLE.H2.0.DEC.V1 0.F17.B7
INT:PASS.SINGLE.H2.0.LONG.IO.V0 0.F3.B7
INT:PASS.SINGLE.H2.0.OUT.LR.IOB1.I2.S 0.F5.B7
INT:PASS.SINGLE.H2.0.OUT.MD0.I 0.F10.B7
INT:PASS.SINGLE.H3.0.DEC.V0 0.F0.B7
INT:PASS.SINGLE.H3.0.LONG.IO.V1 0.F7.B7
INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S 0.F12.B7
INT:PASS.SINGLE.H3.0.OUT.RDBK.DATA 0.F16.B7
MD1:ENABLE.O 0.F20.B9
MD1:ENABLE.T 0.F19.B9
MISC:READ_ABORT 0.F18.B0
MISC:READ_CAPTURE 0.F18.B5
MISC:TM_BOT 0.F5.B4
PULLUP_DEC0_H:ENABLE 0.F2.B4
PULLUP_DEC0_V:ENABLE 0.F2.B5
PULLUP_DEC1_H:ENABLE 0.F3.B4
PULLUP_DEC1_V:ENABLE 0.F16.B5
RDBK:ENABLE 0.F17.B6
inverted ~[0]
INT:MUX.IMUX.BUFG.H 0.F15.B5
0.OUT.IOB.CLKIN.W 0
NONE 1
INT:MUX.IMUX.BUFG.V 0.F6.B3 0.F2.B3 0.F4.B3 0.F3.B3 0.F5.B3 0.F7.B3
0.IO.DOUBLE.0.S.0 0 0 0 1 1 1
0.IO.DOUBLE.0.W.1 0 0 1 0 1 1
0.IO.DOUBLE.1.W.1 0 0 1 1 0 1
0.IO.DOUBLE.1.S.0 0 1 1 1 1 1
0.OUT.IOB.CLKIN.S 1 0 1 1 1 0
NONE 1 0 1 1 1 1
INT:MUX.IMUX.IOB1.IK 0.F14.B3 0.F17.B3 0.F15.B3 0.F16.B3 0.F13.B3
1.SINGLE.V3 0 0 1 1 0
0.DOUBLE.H0.0 0 0 1 1 1
1.SINGLE.V2 0 1 0 1 0
0.LONG.H2 0 1 0 1 1
1.SINGLE.V1 0 1 1 0 0
0.LONG.H3 0 1 1 0 1
1.SINGLE.V0 1 1 1 1 0
0.DOUBLE.H1.1 1 1 1 1 1
INT:MUX.IMUX.IOB1.O1 0.F12.B3 0.F8.B3 0.F11.B3 0.F9.B3 0.F10.B3
0.SINGLE.H1 0 0 0 1 1
1.LONG.V0 0 0 1 0 1
1.LONG.V1 0 0 1 1 0
0.SINGLE.H0 0 1 1 1 1
0.SINGLE.H2 1 0 0 1 1
0.SINGLE.H3 1 0 1 0 1
1.DOUBLE.V0.1 1 0 1 1 0
1.DOUBLE.V1.0 1 1 1 1 1
INT:MUX.IMUX.RDBK.TRIG 0.F13.B6 0.F14.B6 0.F15.B6 0.F16.B6
0.SINGLE.H1 0 0 1 1
0.SINGLE.H2 0 1 0 1
0.SINGLE.H3 0 1 1 0
0.SINGLE.H0 1 1 1 1
INT:MUX.IO.DBUF.V0 0.F9.B8 0.F8.B8
0.IO.DOUBLE.0.S.0 0 0
0.IO.DOUBLE.1.S.0 1 1
INT:MUX.IO.DBUF.V1 0.F6.B9 0.F5.B9
0.IO.DOUBLE.1.W.2 0 0
0.IO.DOUBLE.0.W.2 1 1
INT:MUX.LONG.H2 0.F5.B6 0.F1.B6 0.F3.B6 0.F4.B6
0.LONG.IO.V0 0 0 0 1
0.DEC.V0 0 0 1 0
0.OUT.RDBK.DATA 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.H3 0.F9.B6 0.F10.B6 0.F11.B6 0.F12.B6
0.LONG.IO.V1 0 0 0 1
0.DEC.V1 0 0 1 0
0.OUT.RDBK.DATA 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.H0 0.F11.B4 0.F6.B4
0.LONG.IO.V1 0 0
0.LONG.IO.V0 0 1
NONE 1 1
INT:MUX.LONG.IO.H1 0.F10.B4 0.F8.B4
0.LONG.IO.V0 0 0
0.LONG.IO.V1 0 1
NONE 1 1
INT:MUX.LONG.IO.V0 0.F7.B4 0.F13.B5 0.F14.B5 0.F18.B3 0.F15.B4 0.F19.B3
0.SINGLE.H2 0 0 0 1 1 1
0.LONG.H2 0 0 1 0 1 1
0.LONG.IO.H0 0 0 1 1 0 1
0.LONG.IO.H1 0 0 1 1 1 0
0.SINGLE.H0 0 1 1 1 1 1
NONE 1 1 1 1 1 1
INT:MUX.LONG.IO.V1 0.F9.B4 0.F11.B5 0.F12.B5 0.F13.B4 0.F14.B4 0.F12.B4
0.SINGLE.H3 0 0 0 1 1 1
0.LONG.H3 0 0 1 0 1 1
0.LONG.IO.H0 0 0 1 1 0 1
0.LONG.IO.H1 0 0 1 1 1 0
0.SINGLE.H1 0 1 1 1 1 1
NONE 1 1 1 1 1 1
MD1:PULL 0.F20.B5 0.F19.B5
PULLUP 0 1
PULLDOWN 1 0
PULLNONE 1 1

Tile CNR.TL

Cells: 4

Switchbox INT

xc4000a CNR.TL switchbox INT
DestinationSourceKind
CELL0.LONG.H0CELL0.LONG.IO.V0mux
CELL0.DEC.V0mux
CELL0.OUT.LR.IOB1.I2mux
CELL0.LONG.H1CELL0.LONG.IO.V1mux
CELL0.DEC.V1mux
CELL0.OUT.LR.IOB1.I2mux
CELL0.LONG.IO.H0CELL0.LONG.IO.V0mux
CELL0.LONG.IO.V1mux
CELL0.LONG.IO.H1CELL0.LONG.IO.V0mux
CELL0.LONG.IO.V1mux
CELL0.LONG.IO.V0CELL0.LONG.H0mux
CELL0.LONG.IO.H0mux
CELL0.LONG.IO.H1mux
CELL0.LONG.IO.V1CELL0.LONG.H1mux
CELL0.LONG.IO.H0mux
CELL0.LONG.IO.H1mux
CELL0.IMUX.BUFG.HCELL0.IO.DOUBLE.0.W.0mux
CELL0.IO.DOUBLE.0.W.1mux
CELL0.IO.DOUBLE.1.W.0mux
CELL0.IO.DOUBLE.1.W.1mux
CELL0.OUT.IOB.CLKIN.Wmux
CELL0.IMUX.BUFG.VCELL0.OUT.IOB.CLKIN.Nmux
CELL0.IMUX.BSCAN.TDO1CELL1.DOUBLE.V0.1mux
CELL1.DOUBLE.V1.0mux
CELL1.LONG.V0mux
CELL1.LONG.V1mux
CELL2.SINGLE.H0mux
CELL2.SINGLE.H1mux
CELL2.SINGLE.H2mux
CELL2.SINGLE.H3mux
CELL0.IMUX.BSCAN.TDO2CELL0.LONG.H0mux
CELL0.LONG.H1mux
CELL1.SINGLE.V0mux
CELL1.SINGLE.V1mux
CELL1.SINGLE.V2mux
CELL1.SINGLE.V3mux
CELL2.DOUBLE.H0.1mux
CELL2.DOUBLE.H1.0mux

Bel PULLUP_DEC0_H

xc4000a CNR.TL bel PULLUP_DEC0_H
PinDirectionWires
OoutputCELL0.DEC.H0

Bel PULLUP_DEC1_H

xc4000a CNR.TL bel PULLUP_DEC1_H
PinDirectionWires
OoutputCELL0.DEC.H1

Bel PULLUP_DEC0_V

xc4000a CNR.TL bel PULLUP_DEC0_V
PinDirectionWires
OoutputCELL0.DEC.V0

Bel PULLUP_DEC1_V

xc4000a CNR.TL bel PULLUP_DEC1_V
PinDirectionWires
OoutputCELL0.DEC.V1

Bel BUFGLS_H

xc4000a CNR.TL bel BUFGLS_H
PinDirectionWires
IinputCELL0.IMUX.BUFG.H

Bel BUFGLS_V

xc4000a CNR.TL bel BUFGLS_V
PinDirectionWires
IinputCELL0.IMUX.BUFG.V

Bel CIN

xc4000a CNR.TL bel CIN
PinDirectionWires

Bel BSCAN

xc4000a CNR.TL bel BSCAN
PinDirectionWires
DRCKoutputCELL0.OUT.BT.IOB1.I2
IDLEoutputCELL0.OUT.LR.IOB1.I2
SEL1outputCELL0.OUT.LR.IOB1.I1
SEL2outputCELL0.OUT.BT.IOB1.I1
TDO1inputCELL0.IMUX.BSCAN.TDO1
TDO2inputCELL0.IMUX.BSCAN.TDO2

Bel wires

xc4000a CNR.TL bel wires
WirePins
CELL0.DEC.H0PULLUP_DEC0_H.O
CELL0.DEC.H1PULLUP_DEC1_H.O
CELL0.DEC.V0PULLUP_DEC0_V.O
CELL0.DEC.V1PULLUP_DEC1_V.O
CELL0.IMUX.BUFG.HBUFGLS_H.I
CELL0.IMUX.BUFG.VBUFGLS_V.I
CELL0.IMUX.BSCAN.TDO1BSCAN.TDO1
CELL0.IMUX.BSCAN.TDO2BSCAN.TDO2
CELL0.OUT.BT.IOB1.I1BSCAN.SEL2
CELL0.OUT.BT.IOB1.I2BSCAN.DRCK
CELL0.OUT.LR.IOB1.I1BSCAN.SEL1
CELL0.OUT.LR.IOB1.I2BSCAN.IDLE

Bitstream

xc4000a CNR.TL rect R0
BitFrame
F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B5 - MISC:INPUT[0] - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - -
B2 INT:MUX.LONG.IO.V0[0] INT:MUX.LONG.IO.V0[1] INT:MUX.IMUX.BSCAN.TDO2[0] INT:MUX.IMUX.BSCAN.TDO2[3] INT:MUX.IMUX.BSCAN.TDO2[2] INT:MUX.IMUX.BSCAN.TDO2[4] INT:MUX.IMUX.BSCAN.TDO2[1] INT:MUX.IMUX.BSCAN.TDO1[2] INT:MUX.IMUX.BSCAN.TDO1[0] INT:MUX.IMUX.BSCAN.TDO1[3] INT:MUX.IMUX.BSCAN.TDO1[1] INT:MUX.IMUX.BSCAN.TDO1[4] INT:MUX.IMUX.BUFG.H[0] INT:MUX.IMUX.BUFG.H[5] INT:MUX.IMUX.BUFG.H[1] INT:MUX.IMUX.BUFG.H[3] INT:MUX.IMUX.BUFG.H[2] INT:MUX.IMUX.BUFG.H[4] - -
B1 - - - - INT:MUX.LONG.IO.V0[2] INT:MUX.LONG.IO.V1[0] INT:MUX.LONG.IO.H0[1] INT:MUX.LONG.IO.V1[1] INT:MUX.LONG.IO.V1[2] INT:MUX.LONG.IO.H1[1] INT:MUX.LONG.IO.V1[3] INT:MUX.LONG.IO.H1[0] INT:MUX.LONG.IO.V0[3] INT:MUX.LONG.IO.H0[0] ~MISC:TM_TOP ~MISC:TM_LEFT ~PULLUP_DEC0_H:ENABLE ~PULLUP_DEC1_H:ENABLE - -
B0 BSCAN:ENABLE ~PULLUP_DEC1_V:ENABLE INT:MUX.LONG.H1[1] INT:MUX.IMUX.BUFG.V[0] - - - INT:MUX.LONG.H1[3] INT:MUX.LONG.H1[0] INT:MUX.LONG.H1[2] - - - INT:MUX.LONG.H0[3] INT:MUX.LONG.H0[1] INT:MUX.LONG.H0[0] INT:MUX.LONG.H0[2] ~PULLUP_DEC0_V:ENABLE - -
BSCAN:ENABLE 0.F19.B0
non-inverted [0]
INT:MUX.IMUX.BSCAN.TDO1 0.F8.B2 0.F10.B2 0.F12.B2 0.F9.B2 0.F11.B2
1.LONG.V1 0 0 0 1 1
1.DOUBLE.V0.1 0 0 1 1 1
1.LONG.V0 0 1 0 0 1
2.SINGLE.H1 0 1 0 1 0
2.SINGLE.H3 0 1 1 0 1
2.SINGLE.H2 0 1 1 1 0
2.SINGLE.H0 1 1 0 1 1
1.DOUBLE.V1.0 1 1 1 1 1
INT:MUX.IMUX.BSCAN.TDO2 0.F14.B2 0.F16.B2 0.F15.B2 0.F13.B2 0.F17.B2
1.SINGLE.V1 0 0 1 0 1
0.LONG.H0 0 0 1 1 1
1.SINGLE.V2 0 1 0 0 1
0.LONG.H1 0 1 0 1 1
1.SINGLE.V3 0 1 1 0 0
2.DOUBLE.H1.0 0 1 1 1 0
1.SINGLE.V0 1 1 1 0 1
2.DOUBLE.H0.1 1 1 1 1 1
INT:MUX.IMUX.BUFG.H 0.F6.B2 0.F2.B2 0.F4.B2 0.F3.B2 0.F5.B2 0.F7.B2
0.IO.DOUBLE.0.W.0 0 0 0 1 1 1
0.IO.DOUBLE.0.W.1 0 0 1 0 1 1
0.IO.DOUBLE.1.W.1 0 0 1 1 0 1
0.IO.DOUBLE.1.W.0 0 1 1 1 1 1
0.OUT.IOB.CLKIN.W 1 0 1 1 1 0
NONE 1 0 1 1 1 1
INT:MUX.IMUX.BUFG.V 0.F16.B0
0.OUT.IOB.CLKIN.N 0
NONE 1
INT:MUX.LONG.H0 0.F6.B0 0.F3.B0 0.F5.B0 0.F4.B0
0.LONG.IO.V0 0 0 0 1
0.DEC.V0 0 0 1 0
0.OUT.LR.IOB1.I2 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.H1 0.F12.B0 0.F10.B0 0.F17.B0 0.F11.B0
0.LONG.IO.V1 0 0 0 1
0.DEC.V1 0 0 1 0
0.OUT.LR.IOB1.I2 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.H0 0.F13.B1 0.F6.B1
0.LONG.IO.V1 0 0
0.LONG.IO.V0 0 1
NONE 1 1
INT:MUX.LONG.IO.H1 0.F10.B1 0.F8.B1
0.LONG.IO.V0 0 0
0.LONG.IO.V1 0 1
NONE 1 1
INT:MUX.LONG.IO.V0 0.F7.B1 0.F15.B1 0.F18.B2 0.F19.B2
0.LONG.H0 0 0 0 1
0.LONG.IO.H1 0 0 1 0
0.LONG.IO.H0 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.V1 0.F9.B1 0.F11.B1 0.F12.B1 0.F14.B1
0.LONG.H1 0 0 0 1
0.LONG.IO.H0 0 0 1 0
0.LONG.IO.H1 0 1 1 1
NONE 1 1 1 1
MISC:INPUT 0.F18.B5
CMOS 0
TTL 1
MISC:TM_LEFT 0.F4.B1
MISC:TM_TOP 0.F5.B1
PULLUP_DEC0_H:ENABLE 0.F3.B1
PULLUP_DEC0_V:ENABLE 0.F2.B0
PULLUP_DEC1_H:ENABLE 0.F2.B1
PULLUP_DEC1_V:ENABLE 0.F18.B0
inverted ~[0]

Tile CNR.BR

Cells: 1

Switchbox INT

xc4000a CNR.BR switchbox INT
DestinationSourceKind
SINGLE.H0LONG.IO.V0pass transistor
DEC.V0pass transistor
OUT.LR.IOB1.I2.Spass transistor
OUT.STARTUP.Q1Q4pass transistor
SINGLE.H0.Ebidirectional pass transistor
SINGLE.V0bidirectional pass transistor
SINGLE.V0.Sbidirectional pass transistor
IO.DOUBLE.0.E.0bidirectional pass transistor
IO.DOUBLE.0.S.1bidirectional pass transistor
SINGLE.H0.ELONG.V0pass transistor
SINGLE.H0bidirectional pass transistor
SINGLE.V0bidirectional pass transistor
SINGLE.V0.Sbidirectional pass transistor
SINGLE.H1LONG.IO.V1pass transistor
DEC.V1pass transistor
OUT.LR.IOB1.I1.Spass transistor
OUT.STARTUP.Q3pass transistor
SINGLE.H1.Ebidirectional pass transistor
SINGLE.V1bidirectional pass transistor
SINGLE.V1.Sbidirectional pass transistor
IO.DOUBLE.0.E.1bidirectional pass transistor
SINGLE.H1.ELONG.V1pass transistor
SINGLE.H1bidirectional pass transistor
SINGLE.V1bidirectional pass transistor
SINGLE.V1.Sbidirectional pass transistor
SINGLE.H2LONG.V2pass transistor
LONG.IO.V0pass transistor
DEC.V0pass transistor
OUT.LR.IOB1.I2.Spass transistor
OUT.STARTUP.Q1Q4pass transistor
SINGLE.H2.Ebidirectional pass transistor
SINGLE.V2bidirectional pass transistor
SINGLE.V2.Sbidirectional pass transistor
IO.DOUBLE.1.E.0bidirectional pass transistor
IO.DOUBLE.1.S.1bidirectional pass transistor
SINGLE.H2.ESINGLE.H2bidirectional pass transistor
SINGLE.V2bidirectional pass transistor
SINGLE.V2.Sbidirectional pass transistor
SINGLE.H3LONG.V3pass transistor
LONG.IO.V1pass transistor
DEC.V1pass transistor
OUT.LR.IOB1.I1.Spass transistor
OUT.STARTUP.Q3pass transistor
SINGLE.H3.Ebidirectional pass transistor
SINGLE.V3bidirectional pass transistor
SINGLE.V3.Sbidirectional pass transistor
IO.DOUBLE.1.E.1bidirectional pass transistor
SINGLE.H3.ESINGLE.H3bidirectional pass transistor
SINGLE.V3bidirectional pass transistor
SINGLE.V3.Sbidirectional pass transistor
SINGLE.V0LONG.IO.H0pass transistor
DEC.H1pass transistor
OUT.BT.IOB1.I2.Epass transistor
OUT.STARTUP.Q2pass transistor
SINGLE.H0bidirectional pass transistor
SINGLE.H0.Ebidirectional pass transistor
SINGLE.V0.Sbidirectional pass transistor
IO.DOUBLE.0.S.1bidirectional pass transistor
SINGLE.V0.SSINGLE.H0bidirectional pass transistor
SINGLE.H0.Ebidirectional pass transistor
SINGLE.V0bidirectional pass transistor
SINGLE.V1LONG.IO.H1pass transistor
DEC.H0pass transistor
OUT.BT.IOB1.I1.Epass transistor
OUT.STARTUP.DONEINpass transistor
SINGLE.H1bidirectional pass transistor
SINGLE.H1.Ebidirectional pass transistor
SINGLE.V1.Sbidirectional pass transistor
IO.DOUBLE.0.E.1bidirectional pass transistor
IO.DOUBLE.0.S.2bidirectional pass transistor
SINGLE.V1.SSINGLE.H1bidirectional pass transistor
SINGLE.H1.Ebidirectional pass transistor
SINGLE.V1bidirectional pass transistor
SINGLE.V2LONG.H2pass transistor
LONG.IO.H0pass transistor
DEC.H1pass transistor
OUT.BT.IOB1.I2.Epass transistor
OUT.STARTUP.Q2pass transistor
SINGLE.H2bidirectional pass transistor
SINGLE.H2.Ebidirectional pass transistor
SINGLE.V2.Sbidirectional pass transistor
IO.DOUBLE.1.S.1bidirectional pass transistor
SINGLE.V2.SSINGLE.H2bidirectional pass transistor
SINGLE.H2.Ebidirectional pass transistor
SINGLE.V2bidirectional pass transistor
SINGLE.V3LONG.H3pass transistor
LONG.IO.H1pass transistor
DEC.H0pass transistor
OUT.BT.IOB1.I1.Epass transistor
OUT.STARTUP.DONEINpass transistor
SINGLE.H3bidirectional pass transistor
SINGLE.H3.Ebidirectional pass transistor
SINGLE.V3.Sbidirectional pass transistor
IO.DOUBLE.1.E.1bidirectional pass transistor
IO.DOUBLE.1.S.2bidirectional pass transistor
SINGLE.V3.SSINGLE.H3bidirectional pass transistor
SINGLE.H3.Ebidirectional pass transistor
SINGLE.V3bidirectional pass transistor
DOUBLE.H0.0OUT.STARTUP.Q1Q4pass transistor
DOUBLE.H0.2bidirectional pass transistor
DOUBLE.V0.0bidirectional pass transistor
DOUBLE.V0.2bidirectional pass transistor
IO.DOUBLE.1.E.0bidirectional pass transistor
IO.DOUBLE.1.E.1bidirectional pass transistor
IO.DOUBLE.1.S.1bidirectional pass transistor
DOUBLE.H0.1OUT.LR.IOB1.I1.Spass transistor
IO.DOUBLE.0.E.0bidirectional pass transistor
IO.DOUBLE.0.E.1bidirectional pass transistor
IO.DOUBLE.0.S.1bidirectional pass transistor
DOUBLE.H0.2DOUBLE.H0.0bidirectional pass transistor
DOUBLE.V0.0bidirectional pass transistor
DOUBLE.V0.2bidirectional pass transistor
DOUBLE.H1.0OUT.LR.IOB1.I2.Spass transistor
DOUBLE.H1.2bidirectional pass transistor
DOUBLE.V1.0bidirectional pass transistor
DOUBLE.V1.2bidirectional pass transistor
IO.DOUBLE.0.E.0bidirectional pass transistor
IO.DOUBLE.0.E.1bidirectional pass transistor
IO.DOUBLE.0.S.1bidirectional pass transistor
DOUBLE.H1.1OUT.STARTUP.Q3pass transistor
IO.DOUBLE.1.E.0bidirectional pass transistor
IO.DOUBLE.1.E.1bidirectional pass transistor
IO.DOUBLE.1.S.1bidirectional pass transistor
DOUBLE.H1.2DOUBLE.H1.0bidirectional pass transistor
DOUBLE.V1.0bidirectional pass transistor
DOUBLE.V1.2bidirectional pass transistor
DOUBLE.V0.0OUT.BT.IOB1.I1.Epass transistor
DOUBLE.H0.0bidirectional pass transistor
DOUBLE.H0.2bidirectional pass transistor
DOUBLE.V0.2bidirectional pass transistor
IO.DOUBLE.1.E.1bidirectional pass transistor
IO.DOUBLE.1.S.1bidirectional pass transistor
IO.DOUBLE.1.S.2bidirectional pass transistor
DOUBLE.V0.1OUT.STARTUP.Q2pass transistor
IO.DOUBLE.0.E.1bidirectional pass transistor
IO.DOUBLE.0.S.1bidirectional pass transistor
IO.DOUBLE.0.S.2bidirectional pass transistor
DOUBLE.V0.2DOUBLE.H0.0bidirectional pass transistor
DOUBLE.H0.2bidirectional pass transistor
DOUBLE.V0.0bidirectional pass transistor
DOUBLE.V1.0OUT.STARTUP.DONEINpass transistor
DOUBLE.H1.0bidirectional pass transistor
DOUBLE.H1.2bidirectional pass transistor
DOUBLE.V1.2bidirectional pass transistor
IO.DOUBLE.0.E.1bidirectional pass transistor
IO.DOUBLE.0.S.1bidirectional pass transistor
IO.DOUBLE.0.S.2bidirectional pass transistor
DOUBLE.V1.1OUT.BT.IOB1.I2.Epass transistor
IO.DOUBLE.1.E.1bidirectional pass transistor
IO.DOUBLE.1.S.1bidirectional pass transistor
IO.DOUBLE.1.S.2bidirectional pass transistor
DOUBLE.V1.2DOUBLE.H1.0bidirectional pass transistor
DOUBLE.H1.2bidirectional pass transistor
DOUBLE.V1.0bidirectional pass transistor
IO.DOUBLE.0.E.0IO.DBUF.V0pass transistor
SINGLE.H0bidirectional pass transistor
DOUBLE.H0.1bidirectional pass transistor
DOUBLE.H1.0bidirectional pass transistor
IO.DOUBLE.0.S.1bidirectional pass transistor
IO.DOUBLE.0.E.1IO.DBUF.H1pass transistor
SINGLE.H1bidirectional pass transistor
SINGLE.V1bidirectional pass transistor
DOUBLE.H0.1bidirectional pass transistor
DOUBLE.H1.0bidirectional pass transistor
DOUBLE.V0.1bidirectional pass transistor
DOUBLE.V1.0bidirectional pass transistor
IO.DOUBLE.0.S.2bidirectional pass transistor
IO.DOUBLE.0.S.1IO.DBUF.V1pass transistor
SINGLE.H0bidirectional pass transistor
SINGLE.V0bidirectional pass transistor
DOUBLE.H0.1bidirectional pass transistor
DOUBLE.H1.0bidirectional pass transistor
DOUBLE.V0.1bidirectional pass transistor
DOUBLE.V1.0bidirectional pass transistor
IO.DOUBLE.0.E.0bidirectional pass transistor
IO.DOUBLE.0.S.2IO.DBUF.H0pass transistor
SINGLE.V1bidirectional pass transistor
DOUBLE.V0.1bidirectional pass transistor
DOUBLE.V1.0bidirectional pass transistor
IO.DOUBLE.0.E.1bidirectional pass transistor
IO.DOUBLE.1.E.0IO.DBUF.V0pass transistor
SINGLE.H2bidirectional pass transistor
DOUBLE.H0.0bidirectional pass transistor
DOUBLE.H1.1bidirectional pass transistor
IO.DOUBLE.1.S.1bidirectional pass transistor
IO.DOUBLE.1.E.1IO.DBUF.H1pass transistor
SINGLE.H3bidirectional pass transistor
SINGLE.V3bidirectional pass transistor
DOUBLE.H0.0bidirectional pass transistor
DOUBLE.H1.1bidirectional pass transistor
DOUBLE.V0.0bidirectional pass transistor
DOUBLE.V1.1bidirectional pass transistor
IO.DOUBLE.1.S.2bidirectional pass transistor
IO.DOUBLE.1.S.1IO.DBUF.V1pass transistor
SINGLE.H2bidirectional pass transistor
SINGLE.V2bidirectional pass transistor
DOUBLE.H0.0bidirectional pass transistor
DOUBLE.H1.1bidirectional pass transistor
DOUBLE.V0.0bidirectional pass transistor
DOUBLE.V1.1bidirectional pass transistor
IO.DOUBLE.1.E.0bidirectional pass transistor
IO.DOUBLE.1.S.2IO.DBUF.H0pass transistor
SINGLE.V3bidirectional pass transistor
DOUBLE.V0.0bidirectional pass transistor
DOUBLE.V1.1bidirectional pass transistor
IO.DOUBLE.1.E.1bidirectional pass transistor
IO.DBUF.H0IO.DOUBLE.0.E.1mux
IO.DOUBLE.1.E.1mux
IO.DBUF.H1IO.DOUBLE.0.S.2mux
IO.DOUBLE.1.S.2mux
IO.DBUF.V0IO.DOUBLE.0.S.1mux
IO.DOUBLE.1.S.1mux
IO.DBUF.V1IO.DOUBLE.0.E.0mux
IO.DOUBLE.1.E.0mux
LONG.H2LONG.IO.V0mux
DEC.V1mux
OUT.STARTUP.Q3mux
SINGLE.V2buffer
LONG.H3LONG.IO.V1mux
DEC.V0mux
OUT.STARTUP.Q3mux
SINGLE.V3buffer
LONG.V0LONG.IO.H0mux
DEC.H0mux
OUT.BT.IOB1.I2.Emux
SINGLE.H0.Ebuffer
LONG.V1LONG.IO.H1mux
DEC.H1mux
OUT.BT.IOB1.I2.Emux
SINGLE.H1.Ebuffer
LONG.V2LONG.IO.H0mux
DEC.H0mux
OUT.STARTUP.DONEINmux
SINGLE.H2buffer
LONG.V3LONG.IO.H1mux
DEC.H1mux
OUT.STARTUP.DONEINmux
SINGLE.H3buffer
LONG.IO.H0SINGLE.V0mux
SINGLE.V2mux
LONG.V0mux
LONG.V2mux
LONG.IO.V0mux
LONG.IO.V1mux
LONG.IO.H1SINGLE.V1mux
SINGLE.V3mux
LONG.V1mux
LONG.V3mux
LONG.IO.V0mux
LONG.IO.V1mux
LONG.IO.V0SINGLE.H0mux
SINGLE.H2mux
LONG.H2mux
LONG.IO.H0mux
LONG.IO.H1mux
LONG.IO.V1SINGLE.H1mux
SINGLE.H3mux
LONG.H3mux
LONG.IO.H0mux
LONG.IO.H1mux
IMUX.STARTUP.CLKSINGLE.V0mux
SINGLE.V1mux
SINGLE.V2mux
SINGLE.V3mux
IMUX.STARTUP.GSRSINGLE.H0mux
SINGLE.H1mux
SINGLE.H2mux
SINGLE.H3mux
DOUBLE.V0.0mux
DOUBLE.V1.1mux
LONG.V2mux
LONG.V3mux
IMUX.STARTUP.GTSSINGLE.V0mux
SINGLE.V1mux
SINGLE.V2mux
SINGLE.V3mux
DOUBLE.H0.1mux
DOUBLE.H1.0mux
LONG.H2mux
LONG.H3mux
IMUX.READCLK.ISINGLE.H0mux
SINGLE.H1mux
SINGLE.H2mux
SINGLE.H3mux
IMUX.BUFG.HIO.DOUBLE.0.E.1mux
IO.DOUBLE.0.S.1mux
IO.DOUBLE.1.E.1mux
IO.DOUBLE.1.S.1mux
OUT.IOB.CLKIN.Emux
IMUX.BUFG.VOUT.IOB.CLKIN.Smux

Bel PULLUP_DEC0_H

xc4000a CNR.BR bel PULLUP_DEC0_H
PinDirectionWires
OoutputDEC.H0

Bel PULLUP_DEC1_H

xc4000a CNR.BR bel PULLUP_DEC1_H
PinDirectionWires
OoutputDEC.H1

Bel PULLUP_DEC0_V

xc4000a CNR.BR bel PULLUP_DEC0_V
PinDirectionWires
OoutputDEC.V0

Bel PULLUP_DEC1_V

xc4000a CNR.BR bel PULLUP_DEC1_V
PinDirectionWires
OoutputDEC.V1

Bel BUFGLS_H

xc4000a CNR.BR bel BUFGLS_H
PinDirectionWires
IinputIMUX.BUFG.H

Bel BUFGLS_V

xc4000a CNR.BR bel BUFGLS_V
PinDirectionWires
IinputIMUX.BUFG.V

Bel COUT

xc4000a CNR.BR bel COUT
PinDirectionWires

Bel STARTUP

xc4000a CNR.BR bel STARTUP
PinDirectionWires
CLKinputIMUX.STARTUP.CLK
DONEINoutputOUT.STARTUP.DONEIN
GSRinputIMUX.STARTUP.GSR
GTSinputIMUX.STARTUP.GTS
Q1Q4outputOUT.STARTUP.Q1Q4
Q2outputOUT.STARTUP.Q2
Q3outputOUT.STARTUP.Q3

Bel READCLK

xc4000a CNR.BR bel READCLK
PinDirectionWires
IinputIMUX.READCLK.I

Bel wires

xc4000a CNR.BR bel wires
WirePins
DEC.H0PULLUP_DEC0_H.O
DEC.H1PULLUP_DEC1_H.O
DEC.V0PULLUP_DEC0_V.O
DEC.V1PULLUP_DEC1_V.O
IMUX.STARTUP.CLKSTARTUP.CLK
IMUX.STARTUP.GSRSTARTUP.GSR
IMUX.STARTUP.GTSSTARTUP.GTS
IMUX.READCLK.IREADCLK.I
IMUX.BUFG.HBUFGLS_H.I
IMUX.BUFG.VBUFGLS_V.I
OUT.STARTUP.DONEINSTARTUP.DONEIN
OUT.STARTUP.Q1Q4STARTUP.Q1Q4
OUT.STARTUP.Q2STARTUP.Q2
OUT.STARTUP.Q3STARTUP.Q3

Bitstream

xc4000a CNR.BR rect R0
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 ~INT:BIPASS.SINGLE.V0.SINGLE.V0.S ~INT:BIPASS.SINGLE.H0.E.SINGLE.V0 ~INT:BIPASS.SINGLE.H0.E.SINGLE.V0.S ~INT:BIPASS.SINGLE.H0.SINGLE.H0.E ~INT:BIPASS.SINGLE.H0.SINGLE.V0 ~INT:BIPASS.SINGLE.H0.SINGLE.V0.S - ~INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.2 ~INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.0 ~INT:BIPASS.DOUBLE.V0.0.DOUBLE.V0.2 ~INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.0 ~INT:BIPASS.DOUBLE.H0.0.DOUBLE.H0.2 ~INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.2 ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.1 ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.E.1 ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.E.0 INT:MUX.IO.DBUF.V1[1] INT:MUX.IO.DBUF.V1[0] ~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.E.0 ~INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.E.1 - INT:MUX.IO.DBUF.V0[1] INT:MUX.IO.DBUF.V0[0] ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.0 ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.S.1 ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.1 ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.E.0 ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.E.1 ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.S.1 OSC:MUX.OUT0[1] OSC:MUX.OUT0[2] OSC:ENABLE
B8 - ~INT:BIPASS.SINGLE.V2.SINGLE.V2.S ~INT:BIPASS.SINGLE.H2.E.SINGLE.V2 ~INT:BIPASS.SINGLE.H2.E.SINGLE.V2.S ~INT:BIPASS.SINGLE.H2.SINGLE.H2.E ~INT:BIPASS.SINGLE.H2.SINGLE.V2 ~INT:BIPASS.SINGLE.H2.SINGLE.V2.S - ~INT:BIPASS.SINGLE.V1.SINGLE.V1.S ~INT:BIPASS.SINGLE.H1.E.SINGLE.V1 ~INT:BIPASS.SINGLE.H1.E.SINGLE.V1.S ~INT:BIPASS.SINGLE.H1.SINGLE.V1.S ~INT:BIPASS.SINGLE.H1.SINGLE.V1 ~INT:BIPASS.SINGLE.H1.SINGLE.H1.E ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.S.1 ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.0 ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.S.1 ~INT:BIPASS.IO.DOUBLE.0.E.0.IO.DOUBLE.0.S.1 ~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.1 ~INT:PASS.IO.DOUBLE.1.S.1.0.IO.DBUF.V1 ~INT:PASS.IO.DOUBLE.0.S.1.0.IO.DBUF.V1 ~INT:PASS.IO.DOUBLE.0.E.0.0.IO.DBUF.V0 ~INT:PASS.IO.DOUBLE.1.E.0.0.IO.DBUF.V0 ~INT:BIPASS.IO.DOUBLE.1.E.0.IO.DOUBLE.1.S.1 ~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.E.0 ~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.1 ~INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.E.1 - - INT:MUX.LONG.IO.V0[2] OSC:MUX.OUT1[2] -
B7 - ~INT:PASS.SINGLE.V2.0.LONG.H2 ~INT:PASS.SINGLE.H1.E.0.LONG.V1 ~INT:BIPASS.SINGLE.H3.E.SINGLE.V3 ~INT:BIPASS.SINGLE.V3.SINGLE.V3.S ~INT:BIPASS.SINGLE.H3.SINGLE.V3 ~INT:PASS.SINGLE.H2.0.LONG.V2 ~INT:PASS.SINGLE.V3.0.LONG.H3 ~INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.2 ~INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.0 ~INT:BIPASS.DOUBLE.V1.0.DOUBLE.V1.2 ~INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.0 ~INT:BIPASS.DOUBLE.H1.0.DOUBLE.H1.2 ~INT:PASS.DOUBLE.H0.0.0.OUT.STARTUP.Q1Q4 ~INT:PASS.SINGLE.H1.0.OUT.STARTUP.Q3 ~INT:PASS.SINGLE.H3.0.DEC.V1 ~INT:PASS.SINGLE.H1.0.DEC.V1 ~INT:PASS.SINGLE.H0.0.LONG.IO.V0 ~INT:PASS.SINGLE.H2.0.LONG.IO.V0 ~INT:PASS.DOUBLE.H1.0.0.OUT.LR.IOB1.I2.S ~INT:PASS.SINGLE.H0.0.OUT.STARTUP.Q1Q4 ~INT:PASS.SINGLE.H2.0.OUT.STARTUP.Q1Q4 ~INT:PASS.DOUBLE.H0.1.0.OUT.LR.IOB1.I1.S ~INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S ~INT:PASS.SINGLE.H1.0.OUT.LR.IOB1.I1.S INT:MUX.LONG.IO.V1[4] INT:MUX.LONG.IO.V0[1] INT:MUX.LONG.IO.V0[0] INT:MUX.LONG.IO.V0[3] INT:MUX.LONG.IO.V0[4] ~INT:PASS.SINGLE.H2.0.DEC.V0 ~INT:PASS.SINGLE.H0.0.DEC.V0
B6 - ~INT:PASS.SINGLE.H0.E.0.LONG.V0 - - ~INT:BUF.LONG.V0.0.SINGLE.H0.E ~INT:BIPASS.SINGLE.H3.SINGLE.V3.S ~INT:BIPASS.SINGLE.H3.SINGLE.H3.E ~INT:BIPASS.SINGLE.H3.E.SINGLE.V3.S - - ~INT:BUF.LONG.H3.0.SINGLE.V3 ~INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.2 ~INT:PASS.SINGLE.H3.0.LONG.V3 ~INT:PASS.SINGLE.H3.0.OUT.STARTUP.Q3 ~INT:PASS.DOUBLE.H1.1.0.OUT.STARTUP.Q3 ~INT:BUF.LONG.V1.0.SINGLE.H1.E ~INT:BUF.LONG.V2.0.SINGLE.H2 ~INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S ~INT:PASS.SINGLE.H2.0.OUT.LR.IOB1.I2.S ~INT:PASS.SINGLE.H1.0.LONG.IO.V1 ~INT:PASS.SINGLE.H3.0.LONG.IO.V1 ~INT:BUF.LONG.V3.0.SINGLE.H3 INT:MUX.LONG.IO.V1[3] INT:MUX.LONG.IO.V1[0] INT:MUX.LONG.IO.V1[2] INT:MUX.LONG.IO.V1[1] INT:MUX.LONG.IO.V1[5] INT:MUX.LONG.IO.V0[5] OSC:MUX.OUT1[1] OSC:MUX.OUT1[0] OSC:MUX.OUT0[0] -
B5 ~INT:PASS.SINGLE.V0.0.LONG.IO.H0 ~INT:PASS.SINGLE.V0.0.OUT.STARTUP.Q2 ~INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E ~INT:PASS.SINGLE.V0.0.DEC.H1 INT:MUX.LONG.V0[3] INT:MUX.LONG.V0[0] INT:MUX.LONG.V0[1] INT:MUX.LONG.V0[2] INT:MUX.LONG.V3[3] INT:MUX.LONG.V3[0] INT:MUX.LONG.V3[1] INT:MUX.LONG.V3[2] ~INT:PASS.SINGLE.V3.0.DEC.H0 ~INT:BUF.LONG.H2.0.SINGLE.V2 ~INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E ~INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E INT:MUX.LONG.V1[3] INT:MUX.LONG.V1[1] INT:MUX.LONG.V1[2] INT:MUX.LONG.V2[1] INT:MUX.LONG.V2[3] INT:MUX.LONG.V2[0] INT:MUX.LONG.V2[2] INT:MUX.LONG.IO.H1[0] - INT:MUX.LONG.IO.H1[1] INT:MUX.LONG.IO.H0[1] INT:MUX.LONG.IO.H0[0] ~PULLUP_DEC0_V:ENABLE ~PULLUP_DEC1_H:ENABLE OSC:MUX.OUT1[3] OSC:MUX.OUT0[3]
B4 ~INT:PASS.SINGLE.V2.0.LONG.IO.H0 ~INT:PASS.SINGLE.V2.0.OUT.STARTUP.Q2 ~INT:PASS.SINGLE.V2.0.OUT.BT.IOB1.I2.E ~INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E ~INT:PASS.SINGLE.V2.0.DEC.H1 ~INT:PASS.DOUBLE.V0.1.0.OUT.STARTUP.Q2 ~INT:PASS.SINGLE.V1.0.LONG.IO.H1 ~INT:PASS.SINGLE.V1.0.OUT.BT.IOB1.I1.E ~INT:PASS.SINGLE.V1.0.OUT.STARTUP.DONEIN ~INT:PASS.SINGLE.V1.0.DEC.H0 ~INT:PASS.SINGLE.V3.0.OUT.STARTUP.DONEIN ~INT:PASS.SINGLE.V3.0.LONG.IO.H1 ~INT:PASS.DOUBLE.V1.0.0.OUT.STARTUP.DONEIN ~INT:PASS.IO.DOUBLE.0.E.1.0.IO.DBUF.H1 INT:MUX.LONG.V1[0] ~INT:PASS.IO.DOUBLE.1.E.1.0.IO.DBUF.H1 INT:MUX.IO.DBUF.H0[1] INT:MUX.IO.DBUF.H0[0] ~INT:PASS.IO.DOUBLE.1.S.2.0.IO.DBUF.H0 ~INT:PASS.IO.DOUBLE.0.S.2.0.IO.DBUF.H0 INT:MUX.IO.DBUF.H1[1] INT:MUX.IO.DBUF.H1[0] ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.1 ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.S.1 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.1 ~INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.S.1 ~PULLUP_DEC0_H:ENABLE - - - - -
B3 INT:MUX.IMUX.STARTUP.CLK[2] INT:MUX.IMUX.STARTUP.CLK[1] ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.2 ~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.S.2 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.S.2 ~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.1 ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.1 ~INT:BIPASS.IO.DOUBLE.0.E.1.IO.DOUBLE.0.S.2 ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.1 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.S.1 INT:MUX.IMUX.BUFG.H[5] ~INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.S.1 ~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.S.2 ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.S.2 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.2 ~INT:BIPASS.IO.DOUBLE.1.E.1.IO.DOUBLE.1.S.2 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1 ~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.1 INT:MUX.LONG.IO.H1[3] INT:MUX.LONG.IO.H1[2] INT:MUX.LONG.IO.H1[4] INT:MUX.LONG.IO.H1[5] INT:MUX.LONG.IO.H1[6] INT:MUX.LONG.IO.H0[2] INT:MUX.LONG.IO.H0[4] INT:MUX.LONG.IO.H0[3] INT:MUX.LONG.IO.H0[5] INT:MUX.LONG.H3[3] INT:MUX.IMUX.BUFG.V[0] INT:MUX.LONG.IO.H0[6] ~MISC:TCTEST
B2 INT:MUX.IMUX.STARTUP.CLK[0] INT:MUX.IMUX.STARTUP.GTS[1] INT:MUX.IMUX.STARTUP.GTS[3] INT:MUX.IMUX.STARTUP.CLK[3] INT:MUX.IMUX.STARTUP.GTS[0] INT:MUX.IMUX.STARTUP.GTS[4] INT:MUX.IMUX.STARTUP.GTS[2] INT:MUX.IMUX.BUFG.H[2] INT:MUX.IMUX.BUFG.H[3] INT:MUX.IMUX.BUFG.H[1] INT:MUX.IMUX.BUFG.H[4] INT:MUX.LONG.H2[3] INT:MUX.LONG.H2[0] INT:MUX.IMUX.READCLK.I[0] INT:MUX.IMUX.READCLK.I[2] INT:MUX.LONG.H2[1] INT:MUX.LONG.H2[2] INT:MUX.IMUX.READCLK.I[1] INT:MUX.IMUX.READCLK.I[3] INT:MUX.IMUX.STARTUP.GSR[0] INT:MUX.IMUX.STARTUP.GSR[1] INT:MUX.IMUX.STARTUP.GSR[2] INT:MUX.IMUX.STARTUP.GSR[3] INT:MUX.IMUX.STARTUP.GSR[4] INT:MUX.LONG.H3[1] INT:MUX.LONG.H3[0] INT:MUX.LONG.H3[2] - - - - -
B1 ~STARTUP:ENABLE.GSR - STARTUP:OUTPUTS_ACTIVE[1] - - - - - STARTUP:STARTUP_CLK[0] ~PULLUP_DEC1_V:ENABLE INT:MUX.IMUX.BUFG.H[0] - - - - - - - - - - - - - - - - - - - - ~STARTUP:CRC
B0 ~STARTUP:INV.GSR STARTUP:OUTPUTS_ACTIVE[0] STARTUP:GSR_INACTIVE[0] - STARTUP:GSR_INACTIVE[1] STARTUP:DONE_ACTIVE[1] STARTUP:DONE_ACTIVE[0] ~STARTUP:SYNC_TO_DONE ~STARTUP:INV.GTS DONE:PULL[0] ~STARTUP:ENABLE.GTS - - - - - - - - - - - - - - - - - - - - STARTUP:CONFIG_RATE[0]
DONE:PULL 0.F22.B0
PULLUP 0
PULLNONE 1
INT:BIPASS.DOUBLE.H0.0.DOUBLE.H0.2 0.F20.B9
INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.0 0.F21.B9
INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.2 0.F19.B9
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.0 0.F8.B9
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.1 0.F6.B9
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.S.1 0.F7.B9
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.0 0.F16.B8
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.1 0.F18.B9
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.S.1 0.F17.B8
INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.0 0.F23.B9
INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.2 0.F24.B9
INT:BIPASS.DOUBLE.H1.0.DOUBLE.H1.2 0.F19.B7
INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.0 0.F20.B7
INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.2 0.F20.B6
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.E.0 0.F16.B9
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.E.1 0.F17.B9
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.0.S.1 0.F15.B8
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.E.0 0.F5.B9
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.E.1 0.F4.B9
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.1.S.1 0.F3.B9
INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.0 0.F22.B7
INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.2 0.F23.B7
INT:BIPASS.DOUBLE.V0.0.DOUBLE.V0.2 0.F22.B9
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1 0.F14.B3
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.1 0.F7.B4
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.2 0.F16.B3
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1 0.F25.B3
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.1 0.F22.B3
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.2 0.F29.B3
INT:BIPASS.DOUBLE.V1.0.DOUBLE.V1.2 0.F21.B7
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.1 0.F24.B3
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.S.1 0.F21.B3
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.S.2 0.F27.B3
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.1 0.F9.B4
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.S.1 0.F8.B4
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.S.2 0.F17.B3
INT:BIPASS.IO.DOUBLE.0.E.0.IO.DOUBLE.0.S.1 0.F14.B8
INT:BIPASS.IO.DOUBLE.0.E.1.IO.DOUBLE.0.S.2 0.F23.B3
INT:BIPASS.IO.DOUBLE.1.E.0.IO.DOUBLE.1.S.1 0.F8.B8
INT:BIPASS.IO.DOUBLE.1.E.1.IO.DOUBLE.1.S.2 0.F15.B3
INT:BIPASS.SINGLE.H0.E.SINGLE.V0 0.F30.B9
INT:BIPASS.SINGLE.H0.E.SINGLE.V0.S 0.F29.B9
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.E.0 0.F13.B9
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.1 0.F13.B8
INT:BIPASS.SINGLE.H0.SINGLE.H0.E 0.F28.B9
INT:BIPASS.SINGLE.H0.SINGLE.V0 0.F27.B9
INT:BIPASS.SINGLE.H0.SINGLE.V0.S 0.F26.B9
INT:BIPASS.SINGLE.H1.E.SINGLE.V1 0.F22.B8
INT:BIPASS.SINGLE.H1.E.SINGLE.V1.S 0.F21.B8
INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.E.1 0.F12.B9
INT:BIPASS.SINGLE.H1.SINGLE.H1.E 0.F18.B8
INT:BIPASS.SINGLE.H1.SINGLE.V1 0.F19.B8
INT:BIPASS.SINGLE.H1.SINGLE.V1.S 0.F20.B8
INT:BIPASS.SINGLE.H2.E.SINGLE.V2 0.F29.B8
INT:BIPASS.SINGLE.H2.E.SINGLE.V2.S 0.F28.B8
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.E.0 0.F7.B8
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.1 0.F6.B8
INT:BIPASS.SINGLE.H2.SINGLE.H2.E 0.F27.B8
INT:BIPASS.SINGLE.H2.SINGLE.V2 0.F26.B8
INT:BIPASS.SINGLE.H2.SINGLE.V2.S 0.F25.B8
INT:BIPASS.SINGLE.H3.E.SINGLE.V3 0.F28.B7
INT:BIPASS.SINGLE.H3.E.SINGLE.V3.S 0.F24.B6
INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.E.1 0.F5.B8
INT:BIPASS.SINGLE.H3.SINGLE.H3.E 0.F25.B6
INT:BIPASS.SINGLE.H3.SINGLE.V3 0.F26.B7
INT:BIPASS.SINGLE.H3.SINGLE.V3.S 0.F26.B6
INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.S.1 0.F19.B3
INT:BIPASS.SINGLE.V0.SINGLE.V0.S 0.F31.B9
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.1 0.F26.B3
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.S.2 0.F28.B3
INT:BIPASS.SINGLE.V1.SINGLE.V1.S 0.F23.B8
INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.S.1 0.F6.B4
INT:BIPASS.SINGLE.V2.SINGLE.V2.S 0.F30.B8
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.1 0.F13.B3
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.S.2 0.F18.B3
INT:BIPASS.SINGLE.V3.SINGLE.V3.S 0.F27.B7
INT:BUF.LONG.H2.0.SINGLE.V2 0.F18.B5
INT:BUF.LONG.H3.0.SINGLE.V3 0.F21.B6
INT:BUF.LONG.V0.0.SINGLE.H0.E 0.F27.B6
INT:BUF.LONG.V1.0.SINGLE.H1.E 0.F16.B6
INT:BUF.LONG.V2.0.SINGLE.H2 0.F15.B6
INT:BUF.LONG.V3.0.SINGLE.H3 0.F10.B6
INT:PASS.DOUBLE.H0.0.0.OUT.STARTUP.Q1Q4 0.F18.B7
INT:PASS.DOUBLE.H0.1.0.OUT.LR.IOB1.I1.S 0.F9.B7
INT:PASS.DOUBLE.H1.0.0.OUT.LR.IOB1.I2.S 0.F12.B7
INT:PASS.DOUBLE.H1.1.0.OUT.STARTUP.Q3 0.F17.B6
INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E 0.F28.B4
INT:PASS.DOUBLE.V0.1.0.OUT.STARTUP.Q2 0.F26.B4
INT:PASS.DOUBLE.V1.0.0.OUT.STARTUP.DONEIN 0.F19.B4
INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E 0.F16.B5
INT:PASS.IO.DOUBLE.0.E.0.0.IO.DBUF.V0 0.F10.B8
INT:PASS.IO.DOUBLE.0.E.1.0.IO.DBUF.H1 0.F18.B4
INT:PASS.IO.DOUBLE.0.S.1.0.IO.DBUF.V1 0.F11.B8
INT:PASS.IO.DOUBLE.0.S.2.0.IO.DBUF.H0 0.F12.B4
INT:PASS.IO.DOUBLE.1.E.0.0.IO.DBUF.V0 0.F9.B8
INT:PASS.IO.DOUBLE.1.E.1.0.IO.DBUF.H1 0.F16.B4
INT:PASS.IO.DOUBLE.1.S.1.0.IO.DBUF.V1 0.F12.B8
INT:PASS.IO.DOUBLE.1.S.2.0.IO.DBUF.H0 0.F13.B4
INT:PASS.SINGLE.H0.0.DEC.V0 0.F0.B7
INT:PASS.SINGLE.H0.0.LONG.IO.V0 0.F14.B7
INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S 0.F14.B6
INT:PASS.SINGLE.H0.0.OUT.STARTUP.Q1Q4 0.F11.B7
INT:PASS.SINGLE.H0.E.0.LONG.V0 0.F30.B6
INT:PASS.SINGLE.H1.0.DEC.V1 0.F15.B7
INT:PASS.SINGLE.H1.0.LONG.IO.V1 0.F12.B6
INT:PASS.SINGLE.H1.0.OUT.LR.IOB1.I1.S 0.F7.B7
INT:PASS.SINGLE.H1.0.OUT.STARTUP.Q3 0.F17.B7
INT:PASS.SINGLE.H1.E.0.LONG.V1 0.F29.B7
INT:PASS.SINGLE.H2.0.DEC.V0 0.F1.B7
INT:PASS.SINGLE.H2.0.LONG.IO.V0 0.F13.B7
INT:PASS.SINGLE.H2.0.LONG.V2 0.F25.B7
INT:PASS.SINGLE.H2.0.OUT.LR.IOB1.I2.S 0.F13.B6
INT:PASS.SINGLE.H2.0.OUT.STARTUP.Q1Q4 0.F10.B7
INT:PASS.SINGLE.H3.0.DEC.V1 0.F16.B7
INT:PASS.SINGLE.H3.0.LONG.IO.V1 0.F11.B6
INT:PASS.SINGLE.H3.0.LONG.V3 0.F19.B6
INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S 0.F8.B7
INT:PASS.SINGLE.H3.0.OUT.STARTUP.Q3 0.F18.B6
INT:PASS.SINGLE.V0.0.DEC.H1 0.F28.B5
INT:PASS.SINGLE.V0.0.LONG.IO.H0 0.F31.B5
INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E 0.F29.B5
INT:PASS.SINGLE.V0.0.OUT.STARTUP.Q2 0.F30.B5
INT:PASS.SINGLE.V1.0.DEC.H0 0.F22.B4
INT:PASS.SINGLE.V1.0.LONG.IO.H1 0.F25.B4
INT:PASS.SINGLE.V1.0.OUT.BT.IOB1.I1.E 0.F24.B4
INT:PASS.SINGLE.V1.0.OUT.STARTUP.DONEIN 0.F23.B4
INT:PASS.SINGLE.V2.0.DEC.H1 0.F27.B4
INT:PASS.SINGLE.V2.0.LONG.H2 0.F30.B7
INT:PASS.SINGLE.V2.0.LONG.IO.H0 0.F31.B4
INT:PASS.SINGLE.V2.0.OUT.BT.IOB1.I2.E 0.F29.B4
INT:PASS.SINGLE.V2.0.OUT.STARTUP.Q2 0.F30.B4
INT:PASS.SINGLE.V3.0.DEC.H0 0.F19.B5
INT:PASS.SINGLE.V3.0.LONG.H3 0.F24.B7
INT:PASS.SINGLE.V3.0.LONG.IO.H1 0.F20.B4
INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E 0.F17.B5
INT:PASS.SINGLE.V3.0.OUT.STARTUP.DONEIN 0.F21.B4
MISC:TCTEST 0.F0.B3
PULLUP_DEC0_H:ENABLE 0.F5.B4
PULLUP_DEC0_V:ENABLE 0.F3.B5
PULLUP_DEC1_H:ENABLE 0.F2.B5
PULLUP_DEC1_V:ENABLE 0.F22.B1
STARTUP:CRC 0.F0.B1
STARTUP:ENABLE.GSR 0.F31.B1
STARTUP:ENABLE.GTS 0.F21.B0
STARTUP:INV.GSR 0.F31.B0
STARTUP:INV.GTS 0.F23.B0
STARTUP:SYNC_TO_DONE 0.F24.B0
inverted ~[0]
INT:MUX.IMUX.BUFG.H 0.F20.B3 0.F21.B2 0.F23.B2 0.F24.B2 0.F22.B2 0.F21.B1
0.IO.DOUBLE.0.E.1 0 0 0 1 1 1
0.IO.DOUBLE.0.S.1 0 0 1 0 1 1
0.IO.DOUBLE.1.S.1 0 0 1 1 0 1
0.IO.DOUBLE.1.E.1 0 1 1 1 1 1
0.OUT.IOB.CLKIN.E 1 0 1 1 1 0
NONE 1 0 1 1 1 1
INT:MUX.IMUX.BUFG.V 0.F2.B3
0.OUT.IOB.CLKIN.S 0
NONE 1
INT:MUX.IMUX.READCLK.I 0.F13.B2 0.F17.B2 0.F14.B2 0.F18.B2
0.SINGLE.H1 0 0 1 1
0.SINGLE.H2 0 1 0 1
0.SINGLE.H3 0 1 1 0
0.SINGLE.H0 1 1 1 1
INT:MUX.IMUX.STARTUP.CLK 0.F28.B2 0.F31.B3 0.F30.B3 0.F31.B2
0.SINGLE.V0 0 0 1 1
0.SINGLE.V2 0 1 0 1
0.SINGLE.V3 0 1 1 0
0.SINGLE.V1 1 1 1 1
INT:MUX.IMUX.STARTUP.GSR 0.F8.B2 0.F9.B2 0.F10.B2 0.F11.B2 0.F12.B2
0.SINGLE.H1 0 0 0 1 1
0.SINGLE.H3 0 0 1 0 1
0.DOUBLE.V0.0 0 0 1 1 0
0.SINGLE.H0 0 1 1 1 1
0.LONG.V2 1 0 0 1 1
0.LONG.V3 1 0 1 0 1
0.DOUBLE.V1.1 1 0 1 1 0
0.SINGLE.H2 1 1 1 1 1
INT:MUX.IMUX.STARTUP.GTS 0.F26.B2 0.F29.B2 0.F25.B2 0.F30.B2 0.F27.B2
0.LONG.H2 0 0 0 1 1
0.SINGLE.V0 0 0 1 1 1
0.SINGLE.V3 0 1 0 0 1
0.LONG.H3 0 1 0 1 0
0.SINGLE.V2 0 1 1 0 1
0.DOUBLE.H0.1 0 1 1 1 0
0.SINGLE.V1 1 1 0 1 1
0.DOUBLE.H1.0 1 1 1 1 1
INT:MUX.IO.DBUF.H0 0.F15.B4 0.F14.B4
0.IO.DOUBLE.1.E.1 0 0
0.IO.DOUBLE.0.E.1 1 1
INT:MUX.IO.DBUF.H1 0.F11.B4 0.F10.B4
0.IO.DOUBLE.0.S.2 0 0
0.IO.DOUBLE.1.S.2 1 1
INT:MUX.IO.DBUF.V0 0.F10.B9 0.F9.B9
0.IO.DOUBLE.0.S.1 0 0
0.IO.DOUBLE.1.S.1 1 1
INT:MUX.IO.DBUF.V1 0.F15.B9 0.F14.B9
0.IO.DOUBLE.1.E.0 0 0
0.IO.DOUBLE.0.E.0 1 1
INT:MUX.LONG.H2 0.F20.B2 0.F15.B2 0.F16.B2 0.F19.B2
0.LONG.IO.V0 0 0 0 1
0.DEC.V1 0 0 1 0
0.OUT.STARTUP.Q3 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.H3 0.F3.B3 0.F5.B2 0.F7.B2 0.F6.B2
0.LONG.IO.V1 0 0 0 1
0.DEC.V0 0 0 1 0
0.OUT.STARTUP.Q3 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.H0 0.F1.B3 0.F4.B3 0.F6.B3 0.F5.B3 0.F7.B3 0.F5.B5 0.F4.B5
0.SINGLE.V2 0 0 0 1 1 1 1
0.LONG.V0 0 0 1 0 1 1 1
0.LONG.V2 0 0 1 1 0 1 1
0.SINGLE.V0 0 1 1 1 1 1 1
0.LONG.IO.V0 1 1 1 1 1 0 0
0.LONG.IO.V1 1 1 1 1 1 0 1
NONE 1 1 1 1 1 1 1
INT:MUX.LONG.IO.H1 0.F8.B3 0.F9.B3 0.F10.B3 0.F12.B3 0.F11.B3 0.F6.B5 0.F8.B5
0.SINGLE.V3 0 0 0 1 1 1 1
0.LONG.V1 0 0 1 0 1 1 1
0.LONG.V3 0 0 1 1 0 1 1
0.SINGLE.V1 0 1 1 1 1 1 1
0.LONG.IO.V1 1 1 1 1 1 0 0
0.LONG.IO.V0 1 1 1 1 1 0 1
NONE 1 1 1 1 1 1 1
INT:MUX.LONG.IO.V0 0.F4.B6 0.F2.B7 0.F3.B7 0.F2.B8 0.F5.B7 0.F4.B7
0.SINGLE.H0 0 0 0 1 1 1
0.LONG.H2 0 0 1 0 1 1
0.LONG.IO.H0 0 0 1 1 0 1
0.LONG.IO.H1 0 0 1 1 1 0
0.SINGLE.H2 0 1 1 1 1 1
NONE 1 1 1 1 1 1
INT:MUX.LONG.IO.V1 0.F5.B6 0.F6.B7 0.F9.B6 0.F7.B6 0.F6.B6 0.F8.B6
0.SINGLE.H1 0 0 0 1 1 1
0.LONG.H3 0 0 1 0 1 1
0.LONG.IO.H0 0 0 1 1 0 1
0.LONG.IO.H1 0 0 1 1 1 0
0.SINGLE.H3 0 1 1 1 1 1
NONE 1 1 1 1 1 1
INT:MUX.LONG.V0 0.F27.B5 0.F24.B5 0.F25.B5 0.F26.B5
0.LONG.IO.H0 0 0 0 1
0.DEC.H0 0 0 1 0
0.OUT.BT.IOB1.I2.E 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V1 0.F15.B5 0.F13.B5 0.F14.B5 0.F17.B4
0.LONG.IO.H1 0 0 0 1
0.DEC.H1 0 0 1 0
0.OUT.BT.IOB1.I2.E 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V2 0.F11.B5 0.F9.B5 0.F12.B5 0.F10.B5
0.LONG.IO.H0 0 0 0 1
0.DEC.H0 0 0 1 0
0.OUT.STARTUP.DONEIN 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V3 0.F23.B5 0.F20.B5 0.F21.B5 0.F22.B5
0.LONG.IO.H1 0 0 0 1
0.DEC.H1 0 0 1 0
0.OUT.STARTUP.DONEIN 0 1 1 1
NONE 1 1 1 1
OSC:ENABLE 0.F0.B9
non-inverted [0]
OSC:MUX.OUT0 0.F0.B5 0.F1.B9 0.F2.B9 0.F1.B6
OSC:MUX.OUT1 0.F1.B5 0.F1.B8 0.F3.B6 0.F2.B6
F500K 0 0 1 1
F16K 0 1 0 1
F490 0 1 1 0
F15 1 1 1 1
STARTUP:CONFIG_RATE 0.F0.B0
FAST 0
SLOW 1
STARTUP:DONE_ACTIVE 0.F26.B0 0.F25.B0
Q2 0 0
Q3 0 1
Q1Q4 1 0
Q0 1 1
STARTUP:GSR_INACTIVE 0.F27.B0 0.F29.B0
DONE_IN 0 0
Q3 0 1
Q1Q4 1 0
Q2 1 1
STARTUP:OUTPUTS_ACTIVE 0.F29.B1 0.F30.B0
Q3 0 0
DONE_IN 0 1
Q2 1 0
Q1Q4 1 1
STARTUP:STARTUP_CLK 0.F23.B1
CCLK 0
USERCLK 1

Tile CNR.TR

Cells: 2

Switchbox INT

xc4000a CNR.TR switchbox INT
DestinationSourceKind
CELL0.SINGLE.V0CELL0.LONG.H0pass transistor
CELL0.LONG.IO.H0pass transistor
CELL0.DEC.H0pass transistor
CELL0.OUT.BT.IOB1.I2.Epass transistor
CELL0.OUT.UPDATE.Opass transistor
CELL0.IO.DOUBLE.0.E.1bidirectional pass transistor
CELL0.SINGLE.V1CELL0.LONG.H1pass transistor
CELL0.LONG.IO.H1pass transistor
CELL0.DEC.H1pass transistor
CELL0.OUT.BT.IOB1.I1.Epass transistor
CELL0.OUT.OSC.MUX1pass transistor
CELL0.IO.DOUBLE.0.N.0bidirectional pass transistor
CELL0.IO.DOUBLE.0.E.2bidirectional pass transistor
CELL0.SINGLE.V2CELL0.LONG.IO.H0pass transistor
CELL0.DEC.H0pass transistor
CELL0.OUT.BT.IOB1.I2.Epass transistor
CELL0.OUT.UPDATE.Opass transistor
CELL0.IO.DOUBLE.1.E.1bidirectional pass transistor
CELL0.SINGLE.V3CELL0.LONG.IO.H1pass transistor
CELL0.DEC.H1pass transistor
CELL0.OUT.BT.IOB1.I1.Epass transistor
CELL0.OUT.OSC.MUX1pass transistor
CELL0.IO.DOUBLE.1.N.0bidirectional pass transistor
CELL0.IO.DOUBLE.1.E.2bidirectional pass transistor
CELL0.DOUBLE.V0.0CELL0.OUT.BT.IOB1.I1.Epass transistor
CELL0.IO.DOUBLE.1.N.0bidirectional pass transistor
CELL0.IO.DOUBLE.1.E.1bidirectional pass transistor
CELL0.IO.DOUBLE.1.E.2bidirectional pass transistor
CELL0.DOUBLE.V0.1CELL0.OUT.UPDATE.Opass transistor
CELL0.IO.DOUBLE.0.N.0bidirectional pass transistor
CELL0.IO.DOUBLE.0.E.1bidirectional pass transistor
CELL0.IO.DOUBLE.0.E.2bidirectional pass transistor
CELL0.DOUBLE.V1.0CELL0.OUT.OSC.MUX1pass transistor
CELL0.IO.DOUBLE.0.N.0bidirectional pass transistor
CELL0.IO.DOUBLE.0.E.1bidirectional pass transistor
CELL0.IO.DOUBLE.0.E.2bidirectional pass transistor
CELL0.DOUBLE.V1.1CELL0.OUT.BT.IOB1.I2.Epass transistor
CELL0.IO.DOUBLE.1.N.0bidirectional pass transistor
CELL0.IO.DOUBLE.1.E.1bidirectional pass transistor
CELL0.IO.DOUBLE.1.E.2bidirectional pass transistor
CELL0.IO.DOUBLE.0.N.0CELL0.IO.DBUF.H0pass transistor
CELL0.SINGLE.V1bidirectional pass transistor
CELL0.DOUBLE.V0.1bidirectional pass transistor
CELL0.DOUBLE.V1.0bidirectional pass transistor
CELL0.IO.DOUBLE.0.E.2bidirectional pass transistor
CELL0.IO.DOUBLE.0.E.1CELL0.SINGLE.V0bidirectional pass transistor
CELL0.DOUBLE.V0.1bidirectional pass transistor
CELL0.DOUBLE.V1.0bidirectional pass transistor
CELL0.IO.DOUBLE.0.E.2CELL0.IO.DBUF.H1pass transistor
CELL0.SINGLE.V1bidirectional pass transistor
CELL0.DOUBLE.V0.1bidirectional pass transistor
CELL0.DOUBLE.V1.0bidirectional pass transistor
CELL0.IO.DOUBLE.0.N.0bidirectional pass transistor
CELL0.IO.DOUBLE.1.N.0CELL0.IO.DBUF.H0pass transistor
CELL0.SINGLE.V3bidirectional pass transistor
CELL0.DOUBLE.V0.0bidirectional pass transistor
CELL0.DOUBLE.V1.1bidirectional pass transistor
CELL0.IO.DOUBLE.1.E.2bidirectional pass transistor
CELL0.IO.DOUBLE.1.E.1CELL0.SINGLE.V2bidirectional pass transistor
CELL0.DOUBLE.V0.0bidirectional pass transistor
CELL0.DOUBLE.V1.1bidirectional pass transistor
CELL0.IO.DOUBLE.1.E.2CELL0.IO.DBUF.H1pass transistor
CELL0.SINGLE.V3bidirectional pass transistor
CELL0.DOUBLE.V0.0bidirectional pass transistor
CELL0.DOUBLE.V1.1bidirectional pass transistor
CELL0.IO.DOUBLE.1.N.0bidirectional pass transistor
CELL0.IO.DBUF.H0CELL0.IO.DOUBLE.0.E.2mux
CELL0.IO.DOUBLE.1.E.2mux
CELL0.IO.DBUF.H1CELL0.IO.DOUBLE.0.N.0mux
CELL0.IO.DOUBLE.1.N.0mux
CELL0.LONG.H0CELL0.LONG.IO.V0mux
CELL0.DEC.V1mux
CELL0.OUT.LR.IOB1.I2mux
CELL0.SINGLE.V0buffer
CELL0.LONG.H1CELL0.LONG.IO.V1mux
CELL0.DEC.V0mux
CELL0.OUT.LR.IOB1.I2mux
CELL0.SINGLE.V1buffer
CELL0.LONG.V0CELL0.LONG.IO.H0mux
CELL0.DEC.H1mux
CELL0.OUT.BT.IOB1.I2.Emux
CELL0.LONG.V1CELL0.LONG.IO.H1mux
CELL0.DEC.H0mux
CELL0.OUT.BT.IOB1.I2.Emux
CELL0.LONG.V2CELL0.LONG.IO.H0mux
CELL0.DEC.H1mux
CELL0.OUT.OSC.MUX1mux
CELL0.LONG.V3CELL0.LONG.IO.H1mux
CELL0.DEC.H0mux
CELL0.OUT.OSC.MUX1mux
CELL0.LONG.IO.H0CELL0.SINGLE.V0mux
CELL0.SINGLE.V2mux
CELL0.LONG.V0mux
CELL0.LONG.V2mux
CELL0.LONG.IO.V0mux
CELL0.LONG.IO.V1mux
CELL0.LONG.IO.H1CELL0.SINGLE.V1mux
CELL0.SINGLE.V3mux
CELL0.LONG.V1mux
CELL0.LONG.V3mux
CELL0.LONG.IO.V0mux
CELL0.LONG.IO.V1mux
CELL0.LONG.IO.V0CELL0.LONG.H0mux
CELL0.LONG.IO.H0mux
CELL0.LONG.IO.H1mux
CELL0.LONG.IO.V1CELL0.LONG.H1mux
CELL0.LONG.IO.H0mux
CELL0.LONG.IO.H1mux
CELL0.IMUX.BUFG.HCELL0.OUT.IOB.CLKIN.Emux
CELL0.IMUX.BUFG.VCELL0.IO.DOUBLE.0.E.1mux
CELL0.IO.DOUBLE.0.E.2mux
CELL0.IO.DOUBLE.1.E.1mux
CELL0.IO.DOUBLE.1.E.2mux
CELL0.OUT.IOB.CLKIN.Nmux
CELL0.IMUX.TDO.OCELL0.SINGLE.V0mux
CELL0.SINGLE.V1mux
CELL0.SINGLE.V2mux
CELL0.SINGLE.V3mux
CELL0.LONG.H0mux
CELL0.LONG.H1mux
CELL1.DOUBLE.H0.0mux
CELL1.DOUBLE.H1.1mux
CELL0.IMUX.TDO.TCELL0.DOUBLE.V0.0mux
CELL0.DOUBLE.V1.1mux
CELL0.LONG.V2mux
CELL0.LONG.V3mux
CELL1.SINGLE.H0mux
CELL1.SINGLE.H1mux
CELL1.SINGLE.H2mux
CELL1.SINGLE.H3mux

Bel PULLUP_DEC0_H

xc4000a CNR.TR bel PULLUP_DEC0_H
PinDirectionWires
OoutputCELL0.DEC.H0

Bel PULLUP_DEC1_H

xc4000a CNR.TR bel PULLUP_DEC1_H
PinDirectionWires
OoutputCELL0.DEC.H1

Bel PULLUP_DEC0_V

xc4000a CNR.TR bel PULLUP_DEC0_V
PinDirectionWires
OoutputCELL0.DEC.V0

Bel PULLUP_DEC1_V

xc4000a CNR.TR bel PULLUP_DEC1_V
PinDirectionWires
OoutputCELL0.DEC.V1

Bel BUFGLS_H

xc4000a CNR.TR bel BUFGLS_H
PinDirectionWires
IinputCELL0.IMUX.BUFG.H

Bel BUFGLS_V

xc4000a CNR.TR bel BUFGLS_V
PinDirectionWires
IinputCELL0.IMUX.BUFG.V

Bel COUT

xc4000a CNR.TR bel COUT
PinDirectionWires

Bel UPDATE

xc4000a CNR.TR bel UPDATE
PinDirectionWires
OoutputCELL0.OUT.UPDATE.O

Bel OSC

xc4000a CNR.TR bel OSC
PinDirectionWires
F8MoutputCELL0.OUT.LR.IOB1.I1
OUT0outputCELL0.OUT.LR.IOB1.I2
OUT1outputCELL0.OUT.OSC.MUX1

Bel TDO

xc4000a CNR.TR bel TDO
PinDirectionWires
OinputCELL0.IMUX.TDO.O
TinputCELL0.IMUX.TDO.T

Bel wires

xc4000a CNR.TR bel wires
WirePins
CELL0.DEC.H0PULLUP_DEC0_H.O
CELL0.DEC.H1PULLUP_DEC1_H.O
CELL0.DEC.V0PULLUP_DEC0_V.O
CELL0.DEC.V1PULLUP_DEC1_V.O
CELL0.IMUX.BUFG.HBUFGLS_H.I
CELL0.IMUX.BUFG.VBUFGLS_V.I
CELL0.IMUX.TDO.OTDO.O
CELL0.IMUX.TDO.TTDO.T
CELL0.OUT.LR.IOB1.I1OSC.F8M
CELL0.OUT.LR.IOB1.I2OSC.OUT0
CELL0.OUT.OSC.MUX1OSC.OUT1
CELL0.OUT.UPDATE.OUPDATE.O

Bitstream

xc4000a CNR.TR rect R0
BitFrame
F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B5 - BSCAN:ENABLE ~TDO:ENABLE.O - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - INT:MUX.IMUX.TDO.O[0] INT:MUX.IMUX.BUFG.V[5] - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 INT:MUX.IMUX.TDO.O[2] INT:MUX.LONG.H0[0] INT:MUX.IMUX.TDO.O[4] INT:MUX.LONG.H0[1] INT:MUX.IMUX.BUFG.V[1] INT:MUX.IMUX.BUFG.V[2] INT:MUX.IMUX.BUFG.V[3] INT:MUX.LONG.H0[3] INT:MUX.IMUX.BUFG.V[0] INT:MUX.IMUX.BUFG.V[4] INT:MUX.LONG.H0[2] INT:MUX.LONG.IO.V0[1] INT:MUX.LONG.IO.V0[0] INT:MUX.LONG.IO.V0[2] INT:MUX.LONG.IO.V0[3] INT:MUX.LONG.IO.V1[3] INT:MUX.LONG.IO.V1[1] INT:MUX.LONG.IO.V1[0] INT:MUX.LONG.IO.V1[2] INT:MUX.IMUX.TDO.T[3] INT:MUX.IMUX.TDO.T[0] INT:MUX.IMUX.TDO.T[1] INT:MUX.IMUX.TDO.T[4] INT:MUX.IMUX.TDO.T[2] INT:MUX.LONG.H1[1] INT:MUX.LONG.H1[0] INT:MUX.LONG.H1[2] - - - - -
B2 INT:MUX.IMUX.TDO.O[3] INT:MUX.IMUX.TDO.O[1] ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.N.0 ~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.N.0 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.N.0 ~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.2 ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.2 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.2 ~INT:BIPASS.IO.DOUBLE.0.N.0.IO.DOUBLE.0.E.2 ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.1 ~PULLUP_DEC1_V:ENABLE ~INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.E.1 ~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.N.0 ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.N.0 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.N.0 ~INT:BIPASS.IO.DOUBLE.1.N.0.IO.DOUBLE.1.E.2 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.2 ~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.2 INT:MUX.LONG.IO.H1[3] INT:MUX.LONG.IO.H1[2] INT:MUX.LONG.IO.H1[4] INT:MUX.LONG.IO.H1[5] INT:MUX.LONG.IO.H1[6] INT:MUX.LONG.IO.H0[2] INT:MUX.LONG.IO.H0[4] INT:MUX.LONG.IO.H0[3] INT:MUX.LONG.IO.H0[5] INT:MUX.LONG.H1[3] INT:MUX.IMUX.BUFG.H[0] INT:MUX.LONG.IO.H0[6] ~TDO:ENABLE.T
B1 ~INT:PASS.SINGLE.V2.0.LONG.IO.H0 ~INT:PASS.SINGLE.V2.0.OUT.UPDATE.O ~INT:PASS.SINGLE.V2.0.OUT.BT.IOB1.I2.E ~INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E ~INT:PASS.SINGLE.V2.0.DEC.H0 ~INT:PASS.DOUBLE.V0.1.0.OUT.UPDATE.O ~INT:PASS.SINGLE.V1.0.LONG.IO.H1 ~INT:PASS.SINGLE.V1.0.OUT.BT.IOB1.I1.E ~INT:PASS.SINGLE.V1.0.OUT.OSC.MUX1 ~INT:PASS.SINGLE.V1.0.DEC.H1 ~INT:PASS.SINGLE.V3.0.OUT.OSC.MUX1 ~INT:PASS.SINGLE.V3.0.LONG.IO.H1 ~INT:PASS.DOUBLE.V1.0.0.OUT.OSC.MUX1 ~INT:PASS.IO.DOUBLE.0.E.2.0.IO.DBUF.H1 INT:MUX.LONG.V1[0] ~INT:PASS.IO.DOUBLE.1.E.2.0.IO.DBUF.H1 INT:MUX.IO.DBUF.H0[1] INT:MUX.IO.DBUF.H0[0] ~INT:PASS.IO.DOUBLE.1.N.0.0.IO.DBUF.H0 ~INT:PASS.IO.DOUBLE.0.N.0.0.IO.DBUF.H0 INT:MUX.IO.DBUF.H1[1] INT:MUX.IO.DBUF.H1[0] ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.2 ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.1 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1 ~INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.E.1 ~PULLUP_DEC1_H:ENABLE TDO:PULL[1] TDO:PULL[0] - - -
B0 ~INT:PASS.SINGLE.V0.0.LONG.IO.H0 ~INT:PASS.SINGLE.V0.0.OUT.UPDATE.O ~INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E ~INT:PASS.SINGLE.V0.0.DEC.H0 INT:MUX.LONG.V0[3] INT:MUX.LONG.V0[0] INT:MUX.LONG.V0[1] INT:MUX.LONG.V0[2] INT:MUX.LONG.V3[3] INT:MUX.LONG.V3[0] INT:MUX.LONG.V3[1] INT:MUX.LONG.V3[2] ~INT:PASS.SINGLE.V3.0.DEC.H1 ~INT:BUF.LONG.H1.0.SINGLE.V1 ~INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E ~INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E INT:MUX.LONG.V1[3] INT:MUX.LONG.V1[1] INT:MUX.LONG.V1[2] INT:MUX.LONG.V2[1] INT:MUX.LONG.V2[3] INT:MUX.LONG.V2[0] INT:MUX.LONG.V2[2] INT:MUX.LONG.IO.H1[0] ~MISC:TM_RIGHT INT:MUX.LONG.IO.H1[1] INT:MUX.LONG.IO.H0[1] INT:MUX.LONG.IO.H0[0] ~PULLUP_DEC0_V:ENABLE ~PULLUP_DEC0_H:ENABLE ~MISC:TAC READCLK:READ_CLK[0]
xc4000a CNR.TR rect R1
BitFrame
F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 ~INT:PASS.SINGLE.V0.0.LONG.H0 ~INT:BUF.LONG.H0.0.SINGLE.V0 - - - - - - - ~INT:PASS.SINGLE.V1.0.LONG.H1 - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BSCAN:ENABLE 0.F30.B5
non-inverted [0]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1 0.F7.B1
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.2 0.F14.B2
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.N.0 0.F16.B2
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1 0.F22.B2
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.2 0.F25.B2
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.N.0 0.F29.B2
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.1 0.F21.B2
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.E.2 0.F24.B2
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.0.N.0 0.F27.B2
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.1 0.F8.B1
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.E.2 0.F9.B1
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.1.N.0 0.F17.B2
INT:BIPASS.IO.DOUBLE.0.N.0.IO.DOUBLE.0.E.2 0.F23.B2
INT:BIPASS.IO.DOUBLE.1.N.0.IO.DOUBLE.1.E.2 0.F15.B2
INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.E.1 0.F19.B2
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.2 0.F26.B2
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.N.0 0.F28.B2
INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.E.1 0.F6.B1
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.2 0.F13.B2
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.N.0 0.F18.B2
INT:BUF.LONG.H0.0.SINGLE.V0 1.F29.B9
INT:BUF.LONG.H1.0.SINGLE.V1 0.F18.B0
INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E 0.F28.B1
INT:PASS.DOUBLE.V0.1.0.OUT.UPDATE.O 0.F26.B1
INT:PASS.DOUBLE.V1.0.0.OUT.OSC.MUX1 0.F19.B1
INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E 0.F16.B0
INT:PASS.IO.DOUBLE.0.E.2.0.IO.DBUF.H1 0.F18.B1
INT:PASS.IO.DOUBLE.0.N.0.0.IO.DBUF.H0 0.F12.B1
INT:PASS.IO.DOUBLE.1.E.2.0.IO.DBUF.H1 0.F16.B1
INT:PASS.IO.DOUBLE.1.N.0.0.IO.DBUF.H0 0.F13.B1
INT:PASS.SINGLE.V0.0.DEC.H0 0.F28.B0
INT:PASS.SINGLE.V0.0.LONG.H0 1.F30.B9
INT:PASS.SINGLE.V0.0.LONG.IO.H0 0.F31.B0
INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E 0.F29.B0
INT:PASS.SINGLE.V0.0.OUT.UPDATE.O 0.F30.B0
INT:PASS.SINGLE.V1.0.DEC.H1 0.F22.B1
INT:PASS.SINGLE.V1.0.LONG.H1 1.F21.B9
INT:PASS.SINGLE.V1.0.LONG.IO.H1 0.F25.B1
INT:PASS.SINGLE.V1.0.OUT.BT.IOB1.I1.E 0.F24.B1
INT:PASS.SINGLE.V1.0.OUT.OSC.MUX1 0.F23.B1
INT:PASS.SINGLE.V2.0.DEC.H0 0.F27.B1
INT:PASS.SINGLE.V2.0.LONG.IO.H0 0.F31.B1
INT:PASS.SINGLE.V2.0.OUT.BT.IOB1.I2.E 0.F29.B1
INT:PASS.SINGLE.V2.0.OUT.UPDATE.O 0.F30.B1
INT:PASS.SINGLE.V3.0.DEC.H1 0.F19.B0
INT:PASS.SINGLE.V3.0.LONG.IO.H1 0.F20.B1
INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E 0.F17.B0
INT:PASS.SINGLE.V3.0.OUT.OSC.MUX1 0.F21.B1
MISC:TAC 0.F1.B0
MISC:TM_RIGHT 0.F7.B0
PULLUP_DEC0_H:ENABLE 0.F2.B0
PULLUP_DEC0_V:ENABLE 0.F3.B0
PULLUP_DEC1_H:ENABLE 0.F5.B1
PULLUP_DEC1_V:ENABLE 0.F20.B2
TDO:ENABLE.O 0.F29.B5
TDO:ENABLE.T 0.F0.B2
inverted ~[0]
INT:MUX.IMUX.BUFG.H 0.F2.B2
0.OUT.IOB.CLKIN.E 0
NONE 1
INT:MUX.IMUX.BUFG.V 0.F29.B4 0.F22.B3 0.F25.B3 0.F26.B3 0.F27.B3 0.F23.B3
0.IO.DOUBLE.0.E.2 0 0 0 1 1 1
0.IO.DOUBLE.1.E.1 0 0 1 0 1 1
0.IO.DOUBLE.1.E.2 0 0 1 1 0 1
0.IO.DOUBLE.0.E.1 0 1 1 1 1 1
0.OUT.IOB.CLKIN.N 1 0 1 1 1 0
NONE 1 0 1 1 1 1
INT:MUX.IMUX.TDO.O 0.F29.B3 0.F31.B2 0.F31.B3 0.F30.B2 0.F30.B4
0.LONG.H0 0 0 0 1 1
0.SINGLE.V0 0 0 1 1 1
0.SINGLE.V3 0 1 0 0 1
0.LONG.H1 0 1 0 1 0
0.SINGLE.V2 0 1 1 0 1
1.DOUBLE.H1.1 0 1 1 1 0
0.SINGLE.V1 1 1 0 1 1
1.DOUBLE.H0.0 1 1 1 1 1
INT:MUX.IMUX.TDO.T 0.F9.B3 0.F12.B3 0.F8.B3 0.F10.B3 0.F11.B3
0.DOUBLE.V0.0 0 0 0 1 1
0.DOUBLE.V1.1 0 0 1 1 1
1.SINGLE.H1 0 1 0 0 1
1.SINGLE.H3 0 1 0 1 0
0.LONG.V2 0 1 1 0 1
0.LONG.V3 0 1 1 1 0
1.SINGLE.H0 1 1 0 1 1
1.SINGLE.H2 1 1 1 1 1
INT:MUX.IO.DBUF.H0 0.F15.B1 0.F14.B1
0.IO.DOUBLE.1.E.2 0 0
0.IO.DOUBLE.0.E.2 1 1
INT:MUX.IO.DBUF.H1 0.F11.B1 0.F10.B1
0.IO.DOUBLE.0.N.0 0 0
0.IO.DOUBLE.1.N.0 1 1
INT:MUX.LONG.H0 0.F24.B3 0.F21.B3 0.F28.B3 0.F30.B3
0.LONG.IO.V0 0 0 0 1
0.DEC.V1 0 0 1 0
0.OUT.LR.IOB1.I2 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.H1 0.F3.B2 0.F5.B3 0.F7.B3 0.F6.B3
0.LONG.IO.V1 0 0 0 1
0.DEC.V0 0 0 1 0
0.OUT.LR.IOB1.I2 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.H0 0.F1.B2 0.F4.B2 0.F6.B2 0.F5.B2 0.F7.B2 0.F5.B0 0.F4.B0
0.SINGLE.V2 0 0 0 1 1 1 1
0.LONG.V0 0 0 1 0 1 1 1
0.LONG.V2 0 0 1 1 0 1 1
0.SINGLE.V0 0 1 1 1 1 1 1
0.LONG.IO.V0 1 1 1 1 1 0 0
0.LONG.IO.V1 1 1 1 1 1 0 1
NONE 1 1 1 1 1 1 1
INT:MUX.LONG.IO.H1 0.F8.B2 0.F9.B2 0.F10.B2 0.F12.B2 0.F11.B2 0.F6.B0 0.F8.B0
0.SINGLE.V3 0 0 0 1 1 1 1
0.LONG.V1 0 0 1 0 1 1 1
0.LONG.V3 0 0 1 1 0 1 1
0.SINGLE.V1 0 1 1 1 1 1 1
0.LONG.IO.V1 1 1 1 1 1 0 0
0.LONG.IO.V0 1 1 1 1 1 0 1
NONE 1 1 1 1 1 1 1
INT:MUX.LONG.IO.V0 0.F17.B3 0.F18.B3 0.F20.B3 0.F19.B3
0.LONG.H0 0 0 0 1
0.LONG.IO.H1 0 0 1 0
0.LONG.IO.H0 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.V1 0.F16.B3 0.F13.B3 0.F15.B3 0.F14.B3
0.LONG.H1 0 0 0 1
0.LONG.IO.H0 0 0 1 0
0.LONG.IO.H1 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V0 0.F27.B0 0.F24.B0 0.F25.B0 0.F26.B0
0.LONG.IO.H0 0 0 0 1
0.DEC.H1 0 0 1 0
0.OUT.BT.IOB1.I2.E 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V1 0.F15.B0 0.F13.B0 0.F14.B0 0.F17.B1
0.LONG.IO.H1 0 0 0 1
0.DEC.H0 0 0 1 0
0.OUT.BT.IOB1.I2.E 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V2 0.F11.B0 0.F9.B0 0.F12.B0 0.F10.B0
0.LONG.IO.H0 0 0 0 1
0.DEC.H1 0 0 1 0
0.OUT.OSC.MUX1 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V3 0.F23.B0 0.F20.B0 0.F21.B0 0.F22.B0
0.LONG.IO.H1 0 0 0 1
0.DEC.H0 0 0 1 0
0.OUT.OSC.MUX1 0 1 1 1
NONE 1 1 1 1
READCLK:READ_CLK 0.F0.B0
RDBK 0
CCLK 1
TDO:PULL 0.F4.B1 0.F3.B1
PULLUP 0 1
PULLDOWN 1 0
PULLNONE 1 1