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Splitters

Tile LLH.CLB

Cells: 2 IRIs: 0

Muxes

xc4000a LLH.CLB muxes
DestinationSources
TCELL0:LONG.H0TCELL1:LONG.H0
TCELL0:LONG.H1TCELL1:LONG.H1
TCELL0:LONG.H2TCELL1:LONG.H2
TCELL0:LONG.H3TCELL1:LONG.H3
TCELL1:LONG.H0TCELL0:LONG.H0
TCELL1:LONG.H1TCELL0:LONG.H1
TCELL1:LONG.H2TCELL0:LONG.H2
TCELL1:LONG.H3TCELL0:LONG.H3

Bitstream

xc4000a LLH.CLB bittile 0
BitFrame
0
7 ~INT:BIPASS.0.LONG.H3.1.LONG.H3
6 ~INT:BIPASS.0.LONG.H2.1.LONG.H2
5 -
4 -
3 -
2 -
1 -
0 -
xc4000a LLH.CLB bittile 1
BitFrame
0
8 ~INT:BIPASS.0.LONG.H1.1.LONG.H1
7 -
6 -
5 -
4 ~INT:BIPASS.0.LONG.H0.1.LONG.H0
3 -
2 -
1 -
0 -
INT:BIPASS.0.LONG.H0.1.LONG.H0 1.0.4
INT:BIPASS.0.LONG.H1.1.LONG.H1 1.0.8
INT:BIPASS.0.LONG.H2.1.LONG.H2 0.0.6
INT:BIPASS.0.LONG.H3.1.LONG.H3 0.0.7
inverted ~[0]

Tile LLH.CLB.B

Cells: 2 IRIs: 0

Muxes

xc4000a LLH.CLB.B muxes
DestinationSources
TCELL0:LONG.H0TCELL1:LONG.H0
TCELL0:LONG.H1TCELL1:LONG.H1
TCELL0:LONG.H2TCELL1:LONG.H2
TCELL0:LONG.H3TCELL1:LONG.H3
TCELL1:LONG.H0TCELL0:LONG.H0
TCELL1:LONG.H1TCELL0:LONG.H1
TCELL1:LONG.H2TCELL0:LONG.H2
TCELL1:LONG.H3TCELL0:LONG.H3

Bitstream

xc4000a LLH.CLB.B bittile 0
BitFrame
0
7 ~INT:BIPASS.0.LONG.H3.1.LONG.H3
6 ~INT:BIPASS.0.LONG.H2.1.LONG.H2
5 -
4 -
3 -
2 -
1 -
0 -
xc4000a LLH.CLB.B bittile 1
BitFrame
0
9 ~INT:BIPASS.0.LONG.H0.1.LONG.H0
8 ~INT:BIPASS.0.LONG.H1.1.LONG.H1
7 -
6 -
5 -
4 -
3 -
2 -
1 -
0 -
INT:BIPASS.0.LONG.H0.1.LONG.H0 1.0.9
INT:BIPASS.0.LONG.H1.1.LONG.H1 1.0.8
INT:BIPASS.0.LONG.H2.1.LONG.H2 0.0.6
INT:BIPASS.0.LONG.H3.1.LONG.H3 0.0.7
inverted ~[0]

Tile LLH.IO.B

Cells: 2 IRIs: 0

Muxes

xc4000a LLH.IO.B muxes
DestinationSources
TCELL0:LONG.H2TCELL1:LONG.H2
TCELL0:LONG.H3TCELL1:LONG.H3
TCELL0:LONG.IO.H0TCELL1:LONG.IO.H0
TCELL0:LONG.IO.H1TCELL1:LONG.IO.H1
TCELL0:DEC.H0TCELL1:DEC.H0
TCELL0:DEC.H1TCELL1:DEC.H1
TCELL1:LONG.H2TCELL0:LONG.H2
TCELL1:LONG.H3TCELL0:LONG.H3
TCELL1:LONG.IO.H0TCELL0:LONG.IO.H0
TCELL1:LONG.IO.H1TCELL0:LONG.IO.H1
TCELL1:DEC.H0TCELL0:DEC.H0
TCELL1:DEC.H1TCELL0:DEC.H1

Bitstream

xc4000a LLH.IO.B bittile 0
BitFrame
0
7 ~INT:BIPASS.0.LONG.H3.1.LONG.H3
6 ~INT:BIPASS.0.LONG.H2.1.LONG.H2
5 ~INT:BIPASS.0.DEC.H1.1.DEC.H1
4 ~INT:BIPASS.0.DEC.H0.1.DEC.H0
3 ~INT:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0
2 ~INT:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1
1 -
0 -
INT:BIPASS.0.DEC.H0.1.DEC.H0 0.0.4
INT:BIPASS.0.DEC.H1.1.DEC.H1 0.0.5
INT:BIPASS.0.LONG.H2.1.LONG.H2 0.0.6
INT:BIPASS.0.LONG.H3.1.LONG.H3 0.0.7
INT:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0 0.0.3
INT:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1 0.0.2
inverted ~[0]

Tile LLH.IO.T

Cells: 2 IRIs: 0

Muxes

xc4000a LLH.IO.T muxes
DestinationSources
TCELL0:LONG.H0TCELL1:LONG.H0
TCELL0:LONG.H1TCELL1:LONG.H1
TCELL0:LONG.IO.H0TCELL1:LONG.IO.H0
TCELL0:LONG.IO.H1TCELL1:LONG.IO.H1
TCELL0:DEC.H0TCELL1:DEC.H0
TCELL0:DEC.H1TCELL1:DEC.H1
TCELL1:LONG.H0TCELL0:LONG.H0
TCELL1:LONG.H1TCELL0:LONG.H1
TCELL1:LONG.IO.H0TCELL0:LONG.IO.H0
TCELL1:LONG.IO.H1TCELL0:LONG.IO.H1
TCELL1:DEC.H0TCELL0:DEC.H0
TCELL1:DEC.H1TCELL0:DEC.H1

Bitstream

xc4000a LLH.IO.T bittile 0
BitFrame
0
3 ~INT:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1
2 ~INT:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0
1 ~INT:BIPASS.0.DEC.H1.1.DEC.H1
0 ~INT:BIPASS.0.DEC.H0.1.DEC.H0
xc4000a LLH.IO.T bittile 1
BitFrame
0
8 ~INT:BIPASS.0.LONG.H1.1.LONG.H1
7 -
6 -
5 -
4 ~INT:BIPASS.0.LONG.H0.1.LONG.H0
3 -
2 -
1 -
0 -
INT:BIPASS.0.DEC.H0.1.DEC.H0 0.0.0
INT:BIPASS.0.DEC.H1.1.DEC.H1 0.0.1
INT:BIPASS.0.LONG.H0.1.LONG.H0 1.0.4
INT:BIPASS.0.LONG.H1.1.LONG.H1 1.0.8
INT:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0 0.0.2
INT:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1 0.0.3
inverted ~[0]

Tile LLV.CLB

Cells: 2 IRIs: 0

Muxes

xc4000a LLV.CLB muxes
DestinationSources
TCELL0:LONG.V0TCELL1:LONG.V0
TCELL0:LONG.V1TCELL1:LONG.V1
TCELL0:LONG.V2TCELL1:LONG.V2
TCELL0:LONG.V3TCELL1:LONG.V3
TCELL1:LONG.V0TCELL0:LONG.V0
TCELL1:LONG.V1TCELL0:LONG.V1
TCELL1:LONG.V2TCELL0:LONG.V2
TCELL1:LONG.V3TCELL0:LONG.V3

Bel CLKH

xc4000a LLV.CLB bel CLKH
PinDirectionWires
O0outputTCELL0:GCLK0
O1outputTCELL0:GCLK1
O2outputTCELL0:GCLK2
O3outputTCELL0:GCLK3

Bel wires

xc4000a LLV.CLB bel wires
WirePins
TCELL0:GCLK0CLKH.O0
TCELL0:GCLK1CLKH.O1
TCELL0:GCLK2CLKH.O2
TCELL0:GCLK3CLKH.O3

Bitstream

xc4000a LLV.CLB bittile 0
BitFrame
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 ~INT:BIPASS.0.LONG.V3.1.LONG.V3 ~INT:BIPASS.0.LONG.V0.1.LONG.V0 ~INT:BIPASS.0.LONG.V1.1.LONG.V1 ~INT:BIPASS.0.LONG.V2.1.LONG.V2 - CLKH:MUX.O0[3] CLKH:MUX.O0[1] CLKH:MUX.O0[0] CLKH:MUX.O0[2] CLKH:MUX.O0[4] CLKH:MUX.O2[4] CLKH:MUX.O2[2] CLKH:MUX.O2[0] CLKH:MUX.O2[1] CLKH:MUX.O2[3] CLKH:MUX.O3[4] CLKH:MUX.O3[2] CLKH:MUX.O3[0] CLKH:MUX.O3[1] CLKH:MUX.O3[3] - CLKH:MUX.O1[4] CLKH:MUX.O1[2] CLKH:MUX.O1[0] CLKH:MUX.O1[1] CLKH:MUX.O1[3] - -
CLKH:MUX.O0 0.18.0 0.22.0 0.19.0 0.21.0 0.20.0
I.UL.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O1 0.6.0 0.2.0 0.5.0 0.3.0 0.4.0
I.LL.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O2 0.17.0 0.13.0 0.16.0 0.14.0 0.15.0
I.LR.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O3 0.12.0 0.8.0 0.11.0 0.9.0 0.10.0
I.UR.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
INT:BIPASS.0.LONG.V0.1.LONG.V0 0.26.0
INT:BIPASS.0.LONG.V1.1.LONG.V1 0.25.0
INT:BIPASS.0.LONG.V2.1.LONG.V2 0.24.0
INT:BIPASS.0.LONG.V3.1.LONG.V3 0.27.0
inverted ~[0]

Tile LLV.IO.L

Cells: 2 IRIs: 0

Muxes

xc4000a LLV.IO.L muxes
DestinationSources
TCELL0:LONG.IO.V0TCELL1:LONG.IO.V0
TCELL0:LONG.IO.V1TCELL1:LONG.IO.V1
TCELL0:DEC.V0TCELL1:DEC.V0
TCELL0:DEC.V1TCELL1:DEC.V1
TCELL1:LONG.IO.V0TCELL0:LONG.IO.V0
TCELL1:LONG.IO.V1TCELL0:LONG.IO.V1
TCELL1:DEC.V0TCELL0:DEC.V0
TCELL1:DEC.V1TCELL0:DEC.V1

Bel CLKH

xc4000a LLV.IO.L bel CLKH
PinDirectionWires
O0outputTCELL0:GCLK0
O1outputTCELL0:GCLK1
O2outputTCELL0:GCLK2
O3outputTCELL0:GCLK3

Bel wires

xc4000a LLV.IO.L bel wires
WirePins
TCELL0:GCLK0CLKH.O0
TCELL0:GCLK1CLKH.O1
TCELL0:GCLK2CLKH.O2
TCELL0:GCLK3CLKH.O3

Bitstream

xc4000a LLV.IO.L bittile 0
BitFrame
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 CLKH:MUX.O3[4] CLKH:MUX.O3[2] CLKH:MUX.O3[0] CLKH:MUX.O3[1] CLKH:MUX.O3[3] ~INT:BIPASS.0.DEC.V1.1.DEC.V1 CLKH:MUX.O1[4] CLKH:MUX.O1[2] CLKH:MUX.O1[0] CLKH:MUX.O1[1] CLKH:MUX.O1[3] ~INT:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1 CLKH:MUX.O0[4] CLKH:MUX.O0[2] CLKH:MUX.O0[0] CLKH:MUX.O0[1] CLKH:MUX.O0[3] ~INT:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0 CLKH:MUX.O2[4] CLKH:MUX.O2[2] CLKH:MUX.O2[0]
xc4000a LLV.IO.L bittile 1
BitFrame
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 CLKH:MUX.O2[1] CLKH:MUX.O2[3] ~INT:BIPASS.0.DEC.V0.1.DEC.V0 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
CLKH:MUX.O0 0.8.0 0.4.0 0.7.0 0.5.0 0.6.0
I.UL.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O1 0.14.0 0.10.0 0.13.0 0.11.0 0.12.0
I.LL.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O2 0.2.0 1.29.0 0.1.0 1.30.0 0.0.0
I.LR.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O3 0.20.0 0.16.0 0.19.0 0.17.0 0.18.0
I.UR.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
INT:BIPASS.0.DEC.V0.1.DEC.V0 1.28.0
INT:BIPASS.0.DEC.V1.1.DEC.V1 0.15.0
INT:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0 0.3.0
INT:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1 0.9.0
inverted ~[0]

Tile LLV.IO.R

Cells: 2 IRIs: 0

Muxes

xc4000a LLV.IO.R muxes
DestinationSources
TCELL0:LONG.V0TCELL1:LONG.V0
TCELL0:LONG.V1TCELL1:LONG.V1
TCELL0:LONG.V2TCELL1:LONG.V2
TCELL0:LONG.V3TCELL1:LONG.V3
TCELL0:LONG.IO.V0TCELL1:LONG.IO.V0
TCELL0:LONG.IO.V1TCELL1:LONG.IO.V1
TCELL0:DEC.V0TCELL1:DEC.V0
TCELL0:DEC.V1TCELL1:DEC.V1
TCELL1:LONG.V0TCELL0:LONG.V0
TCELL1:LONG.V1TCELL0:LONG.V1
TCELL1:LONG.V2TCELL0:LONG.V2
TCELL1:LONG.V3TCELL0:LONG.V3
TCELL1:LONG.IO.V0TCELL0:LONG.IO.V0
TCELL1:LONG.IO.V1TCELL0:LONG.IO.V1
TCELL1:DEC.V0TCELL0:DEC.V0
TCELL1:DEC.V1TCELL0:DEC.V1

Bel CLKH

xc4000a LLV.IO.R bel CLKH
PinDirectionWires
O0outputTCELL0:GCLK0
O1outputTCELL0:GCLK1
O2outputTCELL0:GCLK2
O3outputTCELL0:GCLK3

Bel wires

xc4000a LLV.IO.R bel wires
WirePins
TCELL0:GCLK0CLKH.O0
TCELL0:GCLK1CLKH.O1
TCELL0:GCLK2CLKH.O2
TCELL0:GCLK3CLKH.O3

Bitstream

xc4000a LLV.IO.R bittile 0
BitFrame
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 ~MISC:TLC ~INT:BIPASS.0.LONG.V3.1.LONG.V3 ~INT:BIPASS.0.LONG.V0.1.LONG.V0 ~INT:BIPASS.0.LONG.V1.1.LONG.V1 ~INT:BIPASS.0.LONG.V2.1.LONG.V2 ~INT:BIPASS.0.DEC.V1.1.DEC.V1 CLKH:MUX.O2[3] CLKH:MUX.O2[1] CLKH:MUX.O2[0] CLKH:MUX.O2[2] CLKH:MUX.O2[4] ~INT:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0 CLKH:MUX.O0[3] CLKH:MUX.O0[1] CLKH:MUX.O0[0] CLKH:MUX.O0[2] CLKH:MUX.O0[4] ~INT:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1 CLKH:MUX.O1[3] CLKH:MUX.O1[1] CLKH:MUX.O1[0] CLKH:MUX.O1[2] CLKH:MUX.O1[4] ~INT:BIPASS.0.DEC.V0.1.DEC.V0 CLKH:MUX.O3[3] CLKH:MUX.O3[1] CLKH:MUX.O3[0] CLKH:MUX.O3[2] CLKH:MUX.O3[4]
CLKH:MUX.O0 0.12.0 0.16.0 0.13.0 0.15.0 0.14.0
I.UL.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O1 0.6.0 0.10.0 0.7.0 0.9.0 0.8.0
I.LL.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O2 0.18.0 0.22.0 0.19.0 0.21.0 0.20.0
I.LR.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O3 0.0.0 0.4.0 0.1.0 0.3.0 0.2.0
I.UR.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
INT:BIPASS.0.DEC.V0.1.DEC.V0 0.5.0
INT:BIPASS.0.DEC.V1.1.DEC.V1 0.23.0
INT:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0 0.17.0
INT:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1 0.11.0
INT:BIPASS.0.LONG.V0.1.LONG.V0 0.26.0
INT:BIPASS.0.LONG.V1.1.LONG.V1 0.25.0
INT:BIPASS.0.LONG.V2.1.LONG.V2 0.24.0
INT:BIPASS.0.LONG.V3.1.LONG.V3 0.27.0
MISC:TLC 0.28.0
inverted ~[0]