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Splitters

Tile LLH.CLB

Cells: 2

Switchbox LLH

xc4000a LLH.CLB switchbox LLH
DestinationSourceKind
CELL0.LONG.H0CELL1.LONG.H0bidirectional pass transistor
CELL0.LONG.H1CELL1.LONG.H1bidirectional pass transistor
CELL0.LONG.H2CELL1.LONG.H2bidirectional pass transistor
CELL0.LONG.H3CELL1.LONG.H3bidirectional pass transistor
CELL1.LONG.H0CELL0.LONG.H0bidirectional pass transistor
CELL1.LONG.H1CELL0.LONG.H1bidirectional pass transistor
CELL1.LONG.H2CELL0.LONG.H2bidirectional pass transistor
CELL1.LONG.H3CELL0.LONG.H3bidirectional pass transistor

Bitstream

xc4000a LLH.CLB rect R0
BitFrame
F0
B7 ~LLH:BIPASS.0.LONG.H3.1.LONG.H3
B6 ~LLH:BIPASS.0.LONG.H2.1.LONG.H2
B5 -
B4 -
B3 -
B2 -
B1 -
B0 -
xc4000a LLH.CLB rect R1
BitFrame
F0
B8 ~LLH:BIPASS.0.LONG.H1.1.LONG.H1
B7 -
B6 -
B5 -
B4 ~LLH:BIPASS.0.LONG.H0.1.LONG.H0
B3 -
B2 -
B1 -
B0 -
LLH:BIPASS.0.LONG.H0.1.LONG.H0 1.F0.B4
LLH:BIPASS.0.LONG.H1.1.LONG.H1 1.F0.B8
LLH:BIPASS.0.LONG.H2.1.LONG.H2 0.F0.B6
LLH:BIPASS.0.LONG.H3.1.LONG.H3 0.F0.B7
inverted ~[0]

Tile LLH.CLB.B

Cells: 2

Switchbox LLH

xc4000a LLH.CLB.B switchbox LLH
DestinationSourceKind
CELL0.LONG.H0CELL1.LONG.H0bidirectional pass transistor
CELL0.LONG.H1CELL1.LONG.H1bidirectional pass transistor
CELL0.LONG.H2CELL1.LONG.H2bidirectional pass transistor
CELL0.LONG.H3CELL1.LONG.H3bidirectional pass transistor
CELL1.LONG.H0CELL0.LONG.H0bidirectional pass transistor
CELL1.LONG.H1CELL0.LONG.H1bidirectional pass transistor
CELL1.LONG.H2CELL0.LONG.H2bidirectional pass transistor
CELL1.LONG.H3CELL0.LONG.H3bidirectional pass transistor

Bitstream

xc4000a LLH.CLB.B rect R0
BitFrame
F0
B7 ~LLH:BIPASS.0.LONG.H3.1.LONG.H3
B6 ~LLH:BIPASS.0.LONG.H2.1.LONG.H2
B5 -
B4 -
B3 -
B2 -
B1 -
B0 -
xc4000a LLH.CLB.B rect R1
BitFrame
F0
B9 ~LLH:BIPASS.0.LONG.H0.1.LONG.H0
B8 ~LLH:BIPASS.0.LONG.H1.1.LONG.H1
B7 -
B6 -
B5 -
B4 -
B3 -
B2 -
B1 -
B0 -
LLH:BIPASS.0.LONG.H0.1.LONG.H0 1.F0.B9
LLH:BIPASS.0.LONG.H1.1.LONG.H1 1.F0.B8
LLH:BIPASS.0.LONG.H2.1.LONG.H2 0.F0.B6
LLH:BIPASS.0.LONG.H3.1.LONG.H3 0.F0.B7
inverted ~[0]

Tile LLH.IO.B

Cells: 2

Switchbox LLH

xc4000a LLH.IO.B switchbox LLH
DestinationSourceKind
CELL0.LONG.H2CELL1.LONG.H2bidirectional pass transistor
CELL0.LONG.H3CELL1.LONG.H3bidirectional pass transistor
CELL0.LONG.IO.H0CELL1.LONG.IO.H0bidirectional pass transistor
CELL0.LONG.IO.H1CELL1.LONG.IO.H1bidirectional pass transistor
CELL0.DEC.H0CELL1.DEC.H0bidirectional pass transistor
CELL0.DEC.H1CELL1.DEC.H1bidirectional pass transistor
CELL1.LONG.H2CELL0.LONG.H2bidirectional pass transistor
CELL1.LONG.H3CELL0.LONG.H3bidirectional pass transistor
CELL1.LONG.IO.H0CELL0.LONG.IO.H0bidirectional pass transistor
CELL1.LONG.IO.H1CELL0.LONG.IO.H1bidirectional pass transistor
CELL1.DEC.H0CELL0.DEC.H0bidirectional pass transistor
CELL1.DEC.H1CELL0.DEC.H1bidirectional pass transistor

Bitstream

xc4000a LLH.IO.B rect R0
BitFrame
F0
B7 ~LLH:BIPASS.0.LONG.H3.1.LONG.H3
B6 ~LLH:BIPASS.0.LONG.H2.1.LONG.H2
B5 ~LLH:BIPASS.0.DEC.H1.1.DEC.H1
B4 ~LLH:BIPASS.0.DEC.H0.1.DEC.H0
B3 ~LLH:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0
B2 ~LLH:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1
B1 -
B0 -
LLH:BIPASS.0.DEC.H0.1.DEC.H0 0.F0.B4
LLH:BIPASS.0.DEC.H1.1.DEC.H1 0.F0.B5
LLH:BIPASS.0.LONG.H2.1.LONG.H2 0.F0.B6
LLH:BIPASS.0.LONG.H3.1.LONG.H3 0.F0.B7
LLH:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0 0.F0.B3
LLH:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1 0.F0.B2
inverted ~[0]

Tile LLH.IO.T

Cells: 2

Switchbox LLH

xc4000a LLH.IO.T switchbox LLH
DestinationSourceKind
CELL0.LONG.H0CELL1.LONG.H0bidirectional pass transistor
CELL0.LONG.H1CELL1.LONG.H1bidirectional pass transistor
CELL0.LONG.IO.H0CELL1.LONG.IO.H0bidirectional pass transistor
CELL0.LONG.IO.H1CELL1.LONG.IO.H1bidirectional pass transistor
CELL0.DEC.H0CELL1.DEC.H0bidirectional pass transistor
CELL0.DEC.H1CELL1.DEC.H1bidirectional pass transistor
CELL1.LONG.H0CELL0.LONG.H0bidirectional pass transistor
CELL1.LONG.H1CELL0.LONG.H1bidirectional pass transistor
CELL1.LONG.IO.H0CELL0.LONG.IO.H0bidirectional pass transistor
CELL1.LONG.IO.H1CELL0.LONG.IO.H1bidirectional pass transistor
CELL1.DEC.H0CELL0.DEC.H0bidirectional pass transistor
CELL1.DEC.H1CELL0.DEC.H1bidirectional pass transistor

Bitstream

xc4000a LLH.IO.T rect R0
BitFrame
F0
B3 ~LLH:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1
B2 ~LLH:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0
B1 ~LLH:BIPASS.0.DEC.H1.1.DEC.H1
B0 ~LLH:BIPASS.0.DEC.H0.1.DEC.H0
xc4000a LLH.IO.T rect R1
BitFrame
F0
B8 ~LLH:BIPASS.0.LONG.H1.1.LONG.H1
B7 -
B6 -
B5 -
B4 ~LLH:BIPASS.0.LONG.H0.1.LONG.H0
B3 -
B2 -
B1 -
B0 -
LLH:BIPASS.0.DEC.H0.1.DEC.H0 0.F0.B0
LLH:BIPASS.0.DEC.H1.1.DEC.H1 0.F0.B1
LLH:BIPASS.0.LONG.H0.1.LONG.H0 1.F0.B4
LLH:BIPASS.0.LONG.H1.1.LONG.H1 1.F0.B8
LLH:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0 0.F0.B2
LLH:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1 0.F0.B3
inverted ~[0]

Tile LLV.CLB

Cells: 2

Switchbox LLV

xc4000a LLV.CLB switchbox LLV
DestinationSourceKind
CELL0.LONG.V0CELL1.LONG.V0bidirectional pass transistor
CELL0.LONG.V1CELL1.LONG.V1bidirectional pass transistor
CELL0.LONG.V2CELL1.LONG.V2bidirectional pass transistor
CELL0.LONG.V3CELL1.LONG.V3bidirectional pass transistor
CELL1.LONG.V0CELL0.LONG.V0bidirectional pass transistor
CELL1.LONG.V1CELL0.LONG.V1bidirectional pass transistor
CELL1.LONG.V2CELL0.LONG.V2bidirectional pass transistor
CELL1.LONG.V3CELL0.LONG.V3bidirectional pass transistor

Bel CLKH

xc4000a LLV.CLB bel CLKH
PinDirectionWires
O0outputCELL0.GCLK0
O1outputCELL0.GCLK1
O2outputCELL0.GCLK2
O3outputCELL0.GCLK3

Bel wires

xc4000a LLV.CLB bel wires
WirePins
CELL0.GCLK0CLKH.O0
CELL0.GCLK1CLKH.O1
CELL0.GCLK2CLKH.O2
CELL0.GCLK3CLKH.O3

Bitstream

xc4000a LLV.CLB rect R0
BitFrame
F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B0 ~LLV:BIPASS.0.LONG.V3.1.LONG.V3 ~LLV:BIPASS.0.LONG.V0.1.LONG.V0 ~LLV:BIPASS.0.LONG.V1.1.LONG.V1 ~LLV:BIPASS.0.LONG.V2.1.LONG.V2 - CLKH:MUX.O0[3] CLKH:MUX.O0[1] CLKH:MUX.O0[0] CLKH:MUX.O0[2] CLKH:MUX.O0[4] CLKH:MUX.O2[4] CLKH:MUX.O2[2] CLKH:MUX.O2[0] CLKH:MUX.O2[1] CLKH:MUX.O2[3] CLKH:MUX.O3[4] CLKH:MUX.O3[2] CLKH:MUX.O3[0] CLKH:MUX.O3[1] CLKH:MUX.O3[3] - CLKH:MUX.O1[4] CLKH:MUX.O1[2] CLKH:MUX.O1[0] CLKH:MUX.O1[1] CLKH:MUX.O1[3] - -
CLKH:MUX.O0 0.F18.B0 0.F22.B0 0.F19.B0 0.F21.B0 0.F20.B0
I.UL.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O1 0.F6.B0 0.F2.B0 0.F5.B0 0.F3.B0 0.F4.B0
I.LL.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O2 0.F17.B0 0.F13.B0 0.F16.B0 0.F14.B0 0.F15.B0
I.LR.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O3 0.F12.B0 0.F8.B0 0.F11.B0 0.F9.B0 0.F10.B0
I.UR.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
LLV:BIPASS.0.LONG.V0.1.LONG.V0 0.F26.B0
LLV:BIPASS.0.LONG.V1.1.LONG.V1 0.F25.B0
LLV:BIPASS.0.LONG.V2.1.LONG.V2 0.F24.B0
LLV:BIPASS.0.LONG.V3.1.LONG.V3 0.F27.B0
inverted ~[0]

Tile LLV.IO.L

Cells: 2

Switchbox LLV

xc4000a LLV.IO.L switchbox LLV
DestinationSourceKind
CELL0.LONG.IO.V0CELL1.LONG.IO.V0bidirectional pass transistor
CELL0.LONG.IO.V1CELL1.LONG.IO.V1bidirectional pass transistor
CELL0.DEC.V0CELL1.DEC.V0bidirectional pass transistor
CELL0.DEC.V1CELL1.DEC.V1bidirectional pass transistor
CELL1.LONG.IO.V0CELL0.LONG.IO.V0bidirectional pass transistor
CELL1.LONG.IO.V1CELL0.LONG.IO.V1bidirectional pass transistor
CELL1.DEC.V0CELL0.DEC.V0bidirectional pass transistor
CELL1.DEC.V1CELL0.DEC.V1bidirectional pass transistor

Bel CLKH

xc4000a LLV.IO.L bel CLKH
PinDirectionWires
O0outputCELL0.GCLK0
O1outputCELL0.GCLK1
O2outputCELL0.GCLK2
O3outputCELL0.GCLK3

Bel wires

xc4000a LLV.IO.L bel wires
WirePins
CELL0.GCLK0CLKH.O0
CELL0.GCLK1CLKH.O1
CELL0.GCLK2CLKH.O2
CELL0.GCLK3CLKH.O3

Bitstream

xc4000a LLV.IO.L rect R0
BitFrame
F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B0 CLKH:MUX.O3[4] CLKH:MUX.O3[2] CLKH:MUX.O3[0] CLKH:MUX.O3[1] CLKH:MUX.O3[3] ~LLV:BIPASS.0.DEC.V1.1.DEC.V1 CLKH:MUX.O1[4] CLKH:MUX.O1[2] CLKH:MUX.O1[0] CLKH:MUX.O1[1] CLKH:MUX.O1[3] ~LLV:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1 CLKH:MUX.O0[4] CLKH:MUX.O0[2] CLKH:MUX.O0[0] CLKH:MUX.O0[1] CLKH:MUX.O0[3] ~LLV:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0 CLKH:MUX.O2[4] CLKH:MUX.O2[2] CLKH:MUX.O2[0]
xc4000a LLV.IO.L rect R1
BitFrame
F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B0 CLKH:MUX.O2[1] CLKH:MUX.O2[3] ~LLV:BIPASS.0.DEC.V0.1.DEC.V0 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
CLKH:MUX.O0 0.F8.B0 0.F4.B0 0.F7.B0 0.F5.B0 0.F6.B0
I.UL.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O1 0.F14.B0 0.F10.B0 0.F13.B0 0.F11.B0 0.F12.B0
I.LL.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O2 0.F2.B0 1.F29.B0 0.F1.B0 1.F30.B0 0.F0.B0
I.LR.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O3 0.F20.B0 0.F16.B0 0.F19.B0 0.F17.B0 0.F18.B0
I.UR.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
LLV:BIPASS.0.DEC.V0.1.DEC.V0 1.F28.B0
LLV:BIPASS.0.DEC.V1.1.DEC.V1 0.F15.B0
LLV:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0 0.F3.B0
LLV:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1 0.F9.B0
inverted ~[0]

Tile LLV.IO.R

Cells: 2

Switchbox LLV

xc4000a LLV.IO.R switchbox LLV
DestinationSourceKind
CELL0.LONG.V0CELL1.LONG.V0bidirectional pass transistor
CELL0.LONG.V1CELL1.LONG.V1bidirectional pass transistor
CELL0.LONG.V2CELL1.LONG.V2bidirectional pass transistor
CELL0.LONG.V3CELL1.LONG.V3bidirectional pass transistor
CELL0.LONG.IO.V0CELL1.LONG.IO.V0bidirectional pass transistor
CELL0.LONG.IO.V1CELL1.LONG.IO.V1bidirectional pass transistor
CELL0.DEC.V0CELL1.DEC.V0bidirectional pass transistor
CELL0.DEC.V1CELL1.DEC.V1bidirectional pass transistor
CELL1.LONG.V0CELL0.LONG.V0bidirectional pass transistor
CELL1.LONG.V1CELL0.LONG.V1bidirectional pass transistor
CELL1.LONG.V2CELL0.LONG.V2bidirectional pass transistor
CELL1.LONG.V3CELL0.LONG.V3bidirectional pass transistor
CELL1.LONG.IO.V0CELL0.LONG.IO.V0bidirectional pass transistor
CELL1.LONG.IO.V1CELL0.LONG.IO.V1bidirectional pass transistor
CELL1.DEC.V0CELL0.DEC.V0bidirectional pass transistor
CELL1.DEC.V1CELL0.DEC.V1bidirectional pass transistor

Bel CLKH

xc4000a LLV.IO.R bel CLKH
PinDirectionWires
O0outputCELL0.GCLK0
O1outputCELL0.GCLK1
O2outputCELL0.GCLK2
O3outputCELL0.GCLK3

Bel wires

xc4000a LLV.IO.R bel wires
WirePins
CELL0.GCLK0CLKH.O0
CELL0.GCLK1CLKH.O1
CELL0.GCLK2CLKH.O2
CELL0.GCLK3CLKH.O3

Bitstream

xc4000a LLV.IO.R rect R0
BitFrame
F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B0 ~MISC:TLC ~LLV:BIPASS.0.LONG.V3.1.LONG.V3 ~LLV:BIPASS.0.LONG.V0.1.LONG.V0 ~LLV:BIPASS.0.LONG.V1.1.LONG.V1 ~LLV:BIPASS.0.LONG.V2.1.LONG.V2 ~LLV:BIPASS.0.DEC.V1.1.DEC.V1 CLKH:MUX.O2[3] CLKH:MUX.O2[1] CLKH:MUX.O2[0] CLKH:MUX.O2[2] CLKH:MUX.O2[4] ~LLV:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0 CLKH:MUX.O0[3] CLKH:MUX.O0[1] CLKH:MUX.O0[0] CLKH:MUX.O0[2] CLKH:MUX.O0[4] ~LLV:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1 CLKH:MUX.O1[3] CLKH:MUX.O1[1] CLKH:MUX.O1[0] CLKH:MUX.O1[2] CLKH:MUX.O1[4] ~LLV:BIPASS.0.DEC.V0.1.DEC.V0 CLKH:MUX.O3[3] CLKH:MUX.O3[1] CLKH:MUX.O3[0] CLKH:MUX.O3[2] CLKH:MUX.O3[4]
CLKH:MUX.O0 0.F12.B0 0.F16.B0 0.F13.B0 0.F15.B0 0.F14.B0
I.UL.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O1 0.F6.B0 0.F10.B0 0.F7.B0 0.F9.B0 0.F8.B0
I.LL.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O2 0.F18.B0 0.F22.B0 0.F19.B0 0.F21.B0 0.F20.B0
I.LR.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
CLKH:MUX.O3 0.F0.B0 0.F4.B0 0.F1.B0 0.F3.B0 0.F2.B0
I.UR.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
NONE 1 1 1 1 1
LLV:BIPASS.0.DEC.V0.1.DEC.V0 0.F5.B0
LLV:BIPASS.0.DEC.V1.1.DEC.V1 0.F23.B0
LLV:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0 0.F17.B0
LLV:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1 0.F11.B0
LLV:BIPASS.0.LONG.V0.1.LONG.V0 0.F26.B0
LLV:BIPASS.0.LONG.V1.1.LONG.V1 0.F25.B0
LLV:BIPASS.0.LONG.V2.1.LONG.V2 0.F24.B0
LLV:BIPASS.0.LONG.V3.1.LONG.V3 0.F27.B0
MISC:TLC 0.F28.B0
inverted ~[0]