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Configurable Logic Block

Tile CLB

Cells: 3

Switchbox INT

xc4000e CLB switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[21][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[25][8]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[33][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[35][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[27][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[33][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[29][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[29][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[26][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[30][8]
xc4000e CLB switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[14][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y!MAIN[2][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ!MAIN[6][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[11][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[13][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[28][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y!MAIN[1][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[22][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ!MAIN[0][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[13][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[29][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[12][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[27][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[35][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[34][7]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[21][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ!MAIN[23][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[23][8]
CELL.SINGLE_V[1]CELL.OUT_CLB_X!MAIN[24][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[29][8]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[25][4]
CELL.SINGLE_V[3]CELL.LONG_H[2]!MAIN_S[28][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[30][4]
CELL.SINGLE_V[4]CELL.LONG_H[3]!MAIN[21][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ!MAIN[34][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[35][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X!MAIN[31][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[35][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[34][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[21][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[33][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[13][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y!MAIN[10][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ!MAIN[15][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[21][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X!MAIN[32][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ!MAIN[35][4]
xc4000e CLB switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[23][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[25][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[24][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[24][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[26][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[28][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[26][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[23][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[25][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[31][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[34][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[30][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[30][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[31][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[32][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[30][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[31][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[31][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[33][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[30][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[32][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[21][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[23][5]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[25][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[26][5]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[26][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[27][9]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[27][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[28][7]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[34][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[32][6]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[31][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[29][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[32][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[34][9]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[24][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[26][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[25][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[31][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[24][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[22][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[23][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[27][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[28][3]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[24][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[24][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[28][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[29][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
xc4000e CLB switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[26][2]MAIN[28][0]MAIN[27][1]MAIN[26][0]MAIN[27][3]MAIN[26][1]MAIN[27][0]MAIN[27][2]MAIN_W[1][1]CELL.IMUX_CLB_F1
Source
001001111CELL.SINGLE_V[3]
001010111CELL.LONG_V[4]
001011101CELL.SINGLE_V[7]
001111111CELL.SINGLE_V[0]
010001111CELL.LONG_V[3]
010010111CELL.DOUBLE_V0[1]
010011101CELL.LONG_V[0]
010111111CELL.SINGLE_V[1]
011001011CELL.SINGLE_V[5]
011010011CELL.LONG_V[1]
011011001CELL.SINGLE_V[6]
011011110CELL.GCLK[1]
011111011CELL.DOUBLE_V1[1]
111001111CELL.DOUBLE_V1[0]
111010111CELL.SINGLE_V[4]
111011101CELL.DOUBLE_V0[0]
111111111CELL.SINGLE_V[2]
xc4000e CLB switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[10][9]MAIN[10][7]MAIN[11][6]MAIN[11][8]MAIN[11][9]MAIN[12][8]MAIN[12][7]MAIN[12][6]CELL.IMUX_CLB_F2
Source
00110011CELL.SINGLE_H[5]
00110101CELL.LONG_H[5]
00110110CELL.DOUBLE_H1[1]
00111111CELL.SINGLE_H[0]
01010011CELL.SINGLE_H[4]
01010101CELL.DOUBLE_H0[1]
01010110CELL.LONG_H[4]
01011111CELL.SINGLE_H[1]
01100011CELL.SINGLE_H[6]
01100101CELL_N.LONG_H[2]
01100110CELL_N.LONG_H[0]
01101111CELL.SINGLE_H[3]
11110011CELL.DOUBLE_H0[0]
11110101CELL.SINGLE_H[7]
11110110CELL.DOUBLE_H1[0]
11111111CELL.SINGLE_H[2]
xc4000e CLB switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[33][2]MAIN[35][0]MAIN[34][2]MAIN[35][1]MAIN[33][0]MAIN[34][1]MAIN[35][2]MAIN[34][0]MAIN[35][3]CELL.IMUX_CLB_F3
Source
000011111CELL.SINGLE_V[0]
000111011CELL.DOUBLE_V0[0]
000111101CELL.LONG_V[2]
001111111CELL.SINGLE_V[3]
010001111CELL.DOUBLE_V1[1]
010010111CELL.LONG_V[1]
010101011CELL.DOUBLE_V0[1]
010101101CELL.LONG_V[5]
010110011CELL.SINGLE_V[4]
010110101CELL.LONG_V[4]
010111110CELL.GCLK[0]
011101111CELL.SINGLE_V[1]
011110111CELL.SINGLE_V[2]
110011111CELL.SINGLE_V[6]
110111011CELL.DOUBLE_V1[0]
110111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[7]
xc4000e CLB switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[9][7]MAIN[8][6]MAIN[9][6]MAIN[9][8]MAIN[8][7]MAIN[10][6]MAIN[8][9]MAIN[9][9]MAIN[10][8]CELL.IMUX_CLB_F4
Source
000111111CELL.SPECIAL_CLB_CIN
001001111CELL.SINGLE_H[0]
001011011CELL.DOUBLE_H1[0]
001011101CELL_N.LONG_H[0]
001100111CELL.LONG_H[5]
001101110CELL.LONG_H[3]
001110011CELL.SINGLE_H[2]
001110101CELL.SINGLE_H[3]
001111010CELL.SINGLE_H[7]
001111100CELL_N.LONG_H[1]
011011111CELL.SINGLE_H[1]
011110111CELL.DOUBLE_H1[1]
011111110CELL.DOUBLE_H0[1]
101101111CELL.SINGLE_H[5]
101111011CELL.DOUBLE_H0[0]
101111101CELL.SINGLE_H[6]
111111111CELL.SINGLE_H[4]
xc4000e CLB switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[21][0]MAIN[21][3]MAIN[23][0]MAIN[23][1]MAIN[22][1]MAIN[21][1]MAIN[22][0]MAIN[21][2]MAIN[22][2]CELL.IMUX_CLB_G1
Source
000011111CELL.SINGLE_V[0]
000101111CELL.SINGLE_V[2]
000111011CELL.SINGLE_V[4]
001010111CELL.LONG_V[4]
001011101CELL.LONG_V[3]
001100111CELL.SINGLE_V[1]
001101101CELL.DOUBLE_V1[0]
001110011CELL.DOUBLE_V0[1]
001111001CELL.LONG_V[0]
001111110CELL.GCLK[1]
011011111CELL.SINGLE_V[3]
011101111CELL.DOUBLE_V0[0]
011111011CELL.SINGLE_V[7]
100111111CELL.DOUBLE_V1[1]
101110111CELL.LONG_V[1]
101111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[6]
xc4000e CLB switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[2][7]MAIN[3][7]MAIN[3][9]MAIN[2][6]MAIN[3][8]MAIN[2][8]MAIN[2][9]MAIN[3][6]MAIN[4][8]CELL.IMUX_CLB_G2
Source
000111111CELL.SPECIAL_CLB_COUT0
001001111CELL.LONG_H[4]
001011101CELL.SINGLE_H[4]
001011110CELL.LONG_H[5]
001100111CELL.SINGLE_H[2]
001101011CELL.SINGLE_H[3]
001110101CELL.SINGLE_H[7]
001110110CELL.DOUBLE_H0[0]
001111001CELL_N.LONG_H[2]
001111010CELL.SINGLE_H[6]
011011111CELL.SINGLE_H[1]
011110111CELL_N.LONG_H[0]
011111011CELL.DOUBLE_H1[0]
101101111CELL.DOUBLE_H1[1]
101111101CELL.SINGLE_H[5]
101111110CELL.DOUBLE_H0[1]
111111111CELL.SINGLE_H[0]
xc4000e CLB switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[29][0]MAIN[28][2]MAIN[30][1]MAIN[28][1]MAIN[29][2]MAIN[30][0]MAIN[29][1]MAIN[30][2]MAIN[30][3]MAIN_W[0][1]CELL.IMUX_CLB_G3
Source
0001111111CELL.SPECIAL_CLB_CIN
0010011111CELL.SINGLE_V[0]
0010101111CELL.SINGLE_V[2]
0010111011CELL.SINGLE_V[4]
0011010111CELL.LONG_V[4]
0011011101CELL.LONG_V[2]
0011100111CELL.SINGLE_V[1]
0011101101CELL.SINGLE_V[6]
0011110011CELL.DOUBLE_V0[1]
0011111001CELL.LONG_V[5]
0011111110CELL.GCLK[0]
0111011111CELL.DOUBLE_V0[0]
0111101111CELL.SINGLE_V[5]
0111111011CELL.DOUBLE_V1[0]
1010111111CELL.DOUBLE_V1[1]
1011110111CELL.LONG_V[1]
1011111101CELL.SINGLE_V[7]
1111111111CELL.SINGLE_V[3]
xc4000e CLB switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[5][9]MAIN[4][9]MAIN[6][8]MAIN[4][6]MAIN[4][7]MAIN[5][7]MAIN[5][8]MAIN[5][6]CELL.IMUX_CLB_G4
Source
00001111CELL.SINGLE_H[0]
00010111CELL.SINGLE_H[1]
00011101CELL_N.LONG_H[0]
00101011CELL.DOUBLE_H1[1]
00101110CELL.LONG_H[3]
00110011CELL.LONG_H[5]
00110110CELL.DOUBLE_H0[1]
00111001CELL.SINGLE_H[3]
00111100CELL.SINGLE_H[6]
01011111CELL.DOUBLE_H1[0]
01111011CELL.SINGLE_H[2]
01111110CELL.DOUBLE_H0[0]
10101111CELL.SINGLE_H[5]
10110111CELL.SINGLE_H[4]
10111101CELL_N.LONG_H[1]
11111111CELL.SINGLE_H[7]
xc4000e CLB switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[23][3]MAIN[23][2]MAIN[25][1]MAIN[24][0]MAIN[24][1]MAIN[25][2]MAIN[24][2]MAIN[25][0]CELL.IMUX_CLB_C1
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[1]
00011110CELL.GCLK[3]
00101011CELL.DOUBLE_V0[0]
00101101CELL.DOUBLE_V1[0]
00110011CELL.SINGLE_V[3]
00110101CELL.SINGLE_V[7]
00111010CELL.LONG_V[2]
00111100CELL.LONG_V[3]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[2]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[0][7]MAIN[0][6]MAIN[1][7]MAIN[1][9]MAIN[0][8]MAIN[0][9]MAIN[1][6]MAIN[1][8]CELL.IMUX_CLB_C2
Source
00001111CELL.LONG_H[4]
00011101CELL.SINGLE_H[5]
00011110CELL.LONG_H[3]
00111111CELL.SINGLE_H[0]
01000111CELL.SINGLE_H[2]
01001011CELL.SINGLE_H[3]
01010101CELL.SINGLE_H[7]
01010110CELL.DOUBLE_H0[0]
01011001CELL_N.LONG_H[1]
01011010CELL.SINGLE_H[6]
01110111CELL.DOUBLE_H1[0]
01111011CELL_N.LONG_H[2]
11001111CELL.DOUBLE_H1[1]
11011101CELL.SINGLE_H[4]
11011110CELL.DOUBLE_H0[1]
11111111CELL.SINGLE_H[1]
xc4000e CLB switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[31][0]MAIN[31][1]MAIN[32][1]MAIN[32][0]MAIN[31][2]MAIN[32][2]MAIN[32][3]MAIN[33][1]CELL.IMUX_CLB_C3
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[2]
00011110CELL.GCLK[2]
00101011CELL.SINGLE_V[3]
00101101CELL.SINGLE_V[7]
00110011CELL.DOUBLE_V0[0]
00110101CELL.DOUBLE_V1[0]
00111010CELL.LONG_V[3]
00111100CELL.LONG_V[2]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[1]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[7][7]MAIN[8][8]MAIN[6][7]MAIN[6][6]MAIN[7][9]MAIN[7][8]MAIN[6][9]MAIN[7][6]CELL.IMUX_CLB_C4
Source
00001111CELL.SINGLE_H[1]
00011011CELL.DOUBLE_H0[0]
00011101CELL.SINGLE_H[6]
00111111CELL.SINGLE_H[0]
01000111CELL.LONG_H[4]
01001110CELL.LONG_H[3]
01010011CELL.SINGLE_H[2]
01010101CELL.SINGLE_H[3]
01011010CELL.DOUBLE_H1[0]
01011100CELL_N.LONG_H[1]
01110111CELL.DOUBLE_H1[1]
01111110CELL.DOUBLE_H0[1]
11001111CELL.SINGLE_H[4]
11011011CELL.SINGLE_H[7]
11011101CELL_N.LONG_H[2]
11111111CELL.SINGLE_H[5]
xc4000e CLB switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[14][4]MAIN[20][4]MAIN[19][5]MAIN[17][5]MAIN[20][5]MAIN[19][4]MAIN[18][5]MAIN[18][4]CELL.IMUX_CLB_K
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[3]
01101111CELL.SINGLE_V[6]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[5]
xc4000e CLB switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[20][6]MAIN[16][6]MAIN[19][6]MAIN[17][6]MAIN[18][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[20][7]MAIN[16][7]MAIN[19][7]MAIN[17][7]MAIN[18][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[16][8]MAIN[18][8]MAIN[19][8]MAIN[17][8]MAIN[20][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000e CLB switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[16][9]MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000e CLB bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000e CLB bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[19][0]
F bit 1!MAIN[15][0]
F bit 2!MAIN[20][0]
F bit 3!MAIN[16][0]
F bit 4!MAIN[20][2]
F bit 5!MAIN[16][2]
F bit 6!MAIN[19][2]
F bit 7!MAIN[15][2]
F bit 8!MAIN[17][0]
F bit 9!MAIN[13][0]
F bit 10!MAIN[18][0]
F bit 11!MAIN[14][0]
F bit 12!MAIN[18][2]
F bit 13!MAIN[14][2]
F bit 14!MAIN[17][2]
F bit 15!MAIN[13][2]
G bit 0!MAIN[1][2]
G bit 1!MAIN[0][0]
G bit 2!MAIN[3][2]
G bit 3!MAIN[2][0]
G bit 4!MAIN[5][2]
G bit 5!MAIN[4][0]
G bit 6!MAIN[7][2]
G bit 7!MAIN[6][0]
G bit 8!MAIN[0][2]
G bit 9!MAIN[1][0]
G bit 10!MAIN[2][2]
G bit 11!MAIN[3][0]
G bit 12!MAIN[4][2]
G bit 13!MAIN[5][0]
G bit 14!MAIN[6][2]
G bit 15!MAIN[7][0]
H bit 0!MAIN[6][3]
H bit 1!MAIN[7][3]
H bit 2!MAIN[5][3]
H bit 3!MAIN[4][3]
H bit 4!MAIN[9][3]
H bit 5!MAIN[8][3]
H bit 6!MAIN[10][3]
H bit 7!MAIN[13][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[11][4]
FFY_SRVAL bit 0!MAIN[9][5]
FFX_EC_ENABLE!MAIN[13][5]
FFY_EC_ENABLE!MAIN[7][5]
FFX_SR_ENABLE!MAIN[11][5]
FFY_SR_ENABLE!MAIN[8][5]
FFX_CLK_INV!MAIN[16][5]
FFY_CLK_INV!MAIN[15][5]
MUX_CIN[enum: CLB_MUX_CIN]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[11][3]
READBACK_X bit 0!MAIN[16][4]
READBACK_Y bit 0!MAIN[3][5]
READBACK_XQ bit 0!MAIN[12][5]
READBACK_YQ bit 0!MAIN[8][4]
F_RAM_ENABLE!MAIN[12][2]
G_RAM_ENABLE!MAIN[8][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[2][1]
RAM_SYNC_ENABLE!MAIN[6][1]
RAM_CLK_INV!MAIN[5][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
xc4000e CLB enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[13][4]MAIN[16][3]MAIN[15][3]MAIN[15][4]
C11111
C20011
C30101
C40110
xc4000e CLB enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[17][3]MAIN[19][3]MAIN[18][3]MAIN[17][4]
C10011
C21111
C30101
C40110
xc4000e CLB enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[2][3]MAIN[3][4]MAIN[3][3]MAIN[4][4]
C10011
C20101
C31111
C40110
xc4000e CLB enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[0][4]MAIN[1][4]MAIN[2][4]MAIN[1][3]
C10011
C20101
C30110
C41111
xc4000e CLB enum CLB_MUX_X
CLB.MUX_XMAIN[14][3]
F0
H1
xc4000e CLB enum CLB_MUX_Y
CLB.MUX_YMAIN[5][4]
G0
H1
xc4000e CLB enum CLB_MUX_XQ
CLB.MUX_XQMAIN[20][3]
DIN0
FFX1
xc4000e CLB enum CLB_MUX_YQ
CLB.MUX_YQMAIN[0][3]
EC0
FFY1
xc4000e CLB enum CLB_MUX_D
CLB.MUX_DXMAIN[9][4]MAIN[14][6]MAIN[10][4]MAIN[12][4]
CLB.MUX_DYMAIN[4][5]MAIN[5][5]MAIN[7][4]MAIN[6][4]
F1111
G0011
H0101
DIN0110
xc4000e CLB enum CLB_MUX_CIN
CLB.MUX_CINMAIN[9][0]
COUT_S1
COUT_N0
xc4000e CLB enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[11][2]MAIN[12][0]
ADD01
SUB11
ADDSUB10
xc4000e CLB enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[12][3]MAIN[9][2]
CONST_011
CONST_110
XOR01
xc4000e CLB enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[10][0]MAIN[11][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000e CLB enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[8][0]
CONST_11
XOR0
xc4000e CLB enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[10][2]
_32X11
_16X20
xc4000e CLB enum CLB_MUX_H0
CLB.MUX_H0MAIN[3][1]
G1
SR0
xc4000e CLB enum CLB_MUX_H2
CLB.MUX_H2MAIN[7][1]
F1
DIN0

Bels TBUF

xc4000e CLB bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000e CLB bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[22][4]!MAIN[22][6]

Bel wires

xc4000e CLB bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000e CLB rect MAIN
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 2
B8 - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 2 INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 3
B7 INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7
B6 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 6
B5 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 3 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_K bit 4 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE CLB: ! READBACK_XQ bit 0 CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 CLB: ! READBACK_Y bit 0 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ
B4 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 CLB: MUX_DIN bit 0 CLB: ! READBACK_X bit 0 CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 7 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 CLB: ! READBACK_YQ bit 0 CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3
B3 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 1 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 1 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 4 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 7 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 7 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0
B2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_G1 bit 1 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 CLB: ! G bit 8
B1 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 3 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 3 - - - - - - - - - - - - - CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV - CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE - -
B0 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 8 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: MUX_CIN bit 0 CLB: CARRY_GPROP bit 0 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1
xc4000e CLB rect MAIN_S
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB rect MAIN_W
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_F1 bit 0 INT: mux CELL.IMUX_CLB_G3 bit 0
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB rect MAIN_N
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB rect MAIN_E
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLB_W

Cells: 3

Switchbox INT

xc4000e CLB_W switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[21][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[25][8]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[33][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[35][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[27][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[33][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[29][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[29][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[26][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[30][8]
xc4000e CLB_W switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[14][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y!MAIN[2][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ!MAIN[6][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[11][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[13][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[28][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y!MAIN[1][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[22][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ!MAIN[0][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[13][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[29][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[12][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[27][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[35][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[34][7]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[21][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ!MAIN[23][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[23][8]
CELL.SINGLE_V[1]CELL.OUT_CLB_X!MAIN[24][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[29][8]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[25][4]
CELL.SINGLE_V[3]CELL.LONG_H[2]!MAIN_S[28][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[30][4]
CELL.SINGLE_V[4]CELL.LONG_H[3]!MAIN[21][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ!MAIN[34][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[35][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X!MAIN[31][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[35][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[34][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[21][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[33][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[13][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y!MAIN[10][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ!MAIN[15][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[21][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X!MAIN[32][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ!MAIN[35][4]
xc4000e CLB_W switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[23][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[25][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[24][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[24][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[26][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[28][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[26][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[23][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[25][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[31][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[34][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[30][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[30][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[31][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[32][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[30][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[31][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[31][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[33][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[30][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[32][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[21][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[23][5]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[25][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[26][5]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[26][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[27][9]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[27][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[28][7]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[34][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[32][6]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[31][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[29][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[32][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[34][9]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[24][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[26][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[25][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[31][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[24][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[22][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[23][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[27][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[28][3]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[24][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[24][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[28][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[29][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
xc4000e CLB_W switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[26][2]MAIN[28][0]MAIN[27][1]MAIN[26][0]MAIN[27][3]MAIN[26][1]MAIN[27][0]MAIN[27][2]MAIN_W[7][3]CELL.IMUX_CLB_F1
Source
001001111CELL.SINGLE_V[3]
001010111CELL.LONG_V[4]
001011101CELL.SINGLE_V[7]
001111111CELL.SINGLE_V[0]
010001111CELL.LONG_V[3]
010010111CELL.DOUBLE_V0[1]
010011101CELL.LONG_V[0]
010111111CELL.SINGLE_V[1]
011001011CELL.SINGLE_V[5]
011010011CELL.LONG_V[1]
011011001CELL.SINGLE_V[6]
011011110CELL.GCLK[1]
011111011CELL.DOUBLE_V1[1]
111001111CELL.DOUBLE_V1[0]
111010111CELL.SINGLE_V[4]
111011101CELL.DOUBLE_V0[0]
111111111CELL.SINGLE_V[2]
xc4000e CLB_W switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[10][9]MAIN[10][7]MAIN[11][6]MAIN[11][8]MAIN[11][9]MAIN[12][8]MAIN[12][7]MAIN[12][6]CELL.IMUX_CLB_F2
Source
00110011CELL.SINGLE_H[5]
00110101CELL.LONG_H[5]
00110110CELL.DOUBLE_H1[1]
00111111CELL.SINGLE_H[0]
01010011CELL.SINGLE_H[4]
01010101CELL.DOUBLE_H0[1]
01010110CELL.LONG_H[4]
01011111CELL.SINGLE_H[1]
01100011CELL.SINGLE_H[6]
01100101CELL_N.LONG_H[2]
01100110CELL_N.LONG_H[0]
01101111CELL.SINGLE_H[3]
11110011CELL.DOUBLE_H0[0]
11110101CELL.SINGLE_H[7]
11110110CELL.DOUBLE_H1[0]
11111111CELL.SINGLE_H[2]
xc4000e CLB_W switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[33][2]MAIN[35][0]MAIN[34][2]MAIN[35][1]MAIN[33][0]MAIN[34][1]MAIN[35][2]MAIN[34][0]MAIN[35][3]CELL.IMUX_CLB_F3
Source
000011111CELL.SINGLE_V[0]
000111011CELL.DOUBLE_V0[0]
000111101CELL.LONG_V[2]
001111111CELL.SINGLE_V[3]
010001111CELL.DOUBLE_V1[1]
010010111CELL.LONG_V[1]
010101011CELL.DOUBLE_V0[1]
010101101CELL.LONG_V[5]
010110011CELL.SINGLE_V[4]
010110101CELL.LONG_V[4]
010111110CELL.GCLK[0]
011101111CELL.SINGLE_V[1]
011110111CELL.SINGLE_V[2]
110011111CELL.SINGLE_V[6]
110111011CELL.DOUBLE_V1[0]
110111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[7]
xc4000e CLB_W switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[9][7]MAIN[8][6]MAIN[9][6]MAIN[9][8]MAIN[8][7]MAIN[10][6]MAIN[8][9]MAIN[9][9]MAIN[10][8]CELL.IMUX_CLB_F4
Source
000111111CELL.SPECIAL_CLB_CIN
001001111CELL.SINGLE_H[0]
001011011CELL.DOUBLE_H1[0]
001011101CELL_N.LONG_H[0]
001100111CELL.LONG_H[5]
001101110CELL.LONG_H[3]
001110011CELL.SINGLE_H[2]
001110101CELL.SINGLE_H[3]
001111010CELL.SINGLE_H[7]
001111100CELL_N.LONG_H[1]
011011111CELL.SINGLE_H[1]
011110111CELL.DOUBLE_H1[1]
011111110CELL.DOUBLE_H0[1]
101101111CELL.SINGLE_H[5]
101111011CELL.DOUBLE_H0[0]
101111101CELL.SINGLE_H[6]
111111111CELL.SINGLE_H[4]
xc4000e CLB_W switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[21][0]MAIN[21][3]MAIN[23][0]MAIN[23][1]MAIN[22][1]MAIN[21][1]MAIN[22][0]MAIN[21][2]MAIN[22][2]CELL.IMUX_CLB_G1
Source
000011111CELL.SINGLE_V[0]
000101111CELL.SINGLE_V[2]
000111011CELL.SINGLE_V[4]
001010111CELL.LONG_V[4]
001011101CELL.LONG_V[3]
001100111CELL.SINGLE_V[1]
001101101CELL.DOUBLE_V1[0]
001110011CELL.DOUBLE_V0[1]
001111001CELL.LONG_V[0]
001111110CELL.GCLK[1]
011011111CELL.SINGLE_V[3]
011101111CELL.DOUBLE_V0[0]
011111011CELL.SINGLE_V[7]
100111111CELL.DOUBLE_V1[1]
101110111CELL.LONG_V[1]
101111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[6]
xc4000e CLB_W switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[2][7]MAIN[3][7]MAIN[3][9]MAIN[2][6]MAIN[3][8]MAIN[2][8]MAIN[2][9]MAIN[3][6]MAIN[4][8]CELL.IMUX_CLB_G2
Source
000111111CELL.SPECIAL_CLB_COUT0
001001111CELL.LONG_H[4]
001011101CELL.SINGLE_H[4]
001011110CELL.LONG_H[5]
001100111CELL.SINGLE_H[2]
001101011CELL.SINGLE_H[3]
001110101CELL.SINGLE_H[7]
001110110CELL.DOUBLE_H0[0]
001111001CELL_N.LONG_H[2]
001111010CELL.SINGLE_H[6]
011011111CELL.SINGLE_H[1]
011110111CELL_N.LONG_H[0]
011111011CELL.DOUBLE_H1[0]
101101111CELL.DOUBLE_H1[1]
101111101CELL.SINGLE_H[5]
101111110CELL.DOUBLE_H0[1]
111111111CELL.SINGLE_H[0]
xc4000e CLB_W switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[29][0]MAIN[28][2]MAIN[28][1]MAIN[29][2]MAIN[30][0]MAIN[29][1]MAIN[30][2]MAIN[30][3]MAIN_W[8][2]CELL.IMUX_CLB_G3
Source
000011111CELL.SINGLE_V[0]
000101111CELL.SINGLE_V[2]
000111011CELL.SINGLE_V[4]
001010111CELL.LONG_V[4]
001011101CELL.LONG_V[2]
001100111CELL.SINGLE_V[1]
001101101CELL.SINGLE_V[6]
001110011CELL.DOUBLE_V0[1]
001111001CELL.LONG_V[5]
001111110CELL.GCLK[0]
011011111CELL.DOUBLE_V0[0]
011101111CELL.SINGLE_V[5]
011111011CELL.DOUBLE_V1[0]
100111111CELL.DOUBLE_V1[1]
101110111CELL.LONG_V[1]
101111101CELL.SINGLE_V[7]
111111111CELL.SINGLE_V[3]
xc4000e CLB_W switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[5][9]MAIN[4][9]MAIN[6][8]MAIN[4][6]MAIN[4][7]MAIN[5][7]MAIN[5][8]MAIN[5][6]CELL.IMUX_CLB_G4
Source
00001111CELL.SINGLE_H[0]
00010111CELL.SINGLE_H[1]
00011101CELL_N.LONG_H[0]
00101011CELL.DOUBLE_H1[1]
00101110CELL.LONG_H[3]
00110011CELL.LONG_H[5]
00110110CELL.DOUBLE_H0[1]
00111001CELL.SINGLE_H[3]
00111100CELL.SINGLE_H[6]
01011111CELL.DOUBLE_H1[0]
01111011CELL.SINGLE_H[2]
01111110CELL.DOUBLE_H0[0]
10101111CELL.SINGLE_H[5]
10110111CELL.SINGLE_H[4]
10111101CELL_N.LONG_H[1]
11111111CELL.SINGLE_H[7]
xc4000e CLB_W switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[23][3]MAIN[23][2]MAIN[25][1]MAIN[24][0]MAIN[24][1]MAIN[25][2]MAIN[24][2]MAIN[25][0]CELL.IMUX_CLB_C1
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[1]
00011110CELL.GCLK[3]
00101011CELL.DOUBLE_V0[0]
00101101CELL.DOUBLE_V1[0]
00110011CELL.SINGLE_V[3]
00110101CELL.SINGLE_V[7]
00111010CELL.LONG_V[2]
00111100CELL.LONG_V[3]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[2]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB_W switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[0][7]MAIN[0][6]MAIN[1][7]MAIN[1][9]MAIN[0][8]MAIN[0][9]MAIN[1][6]MAIN[1][8]CELL.IMUX_CLB_C2
Source
00001111CELL.LONG_H[4]
00011101CELL.SINGLE_H[5]
00011110CELL.LONG_H[3]
00111111CELL.SINGLE_H[0]
01000111CELL.SINGLE_H[2]
01001011CELL.SINGLE_H[3]
01010101CELL.SINGLE_H[7]
01010110CELL.DOUBLE_H0[0]
01011001CELL_N.LONG_H[1]
01011010CELL.SINGLE_H[6]
01110111CELL.DOUBLE_H1[0]
01111011CELL_N.LONG_H[2]
11001111CELL.DOUBLE_H1[1]
11011101CELL.SINGLE_H[4]
11011110CELL.DOUBLE_H0[1]
11111111CELL.SINGLE_H[1]
xc4000e CLB_W switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[31][0]MAIN[31][1]MAIN[32][1]MAIN[32][0]MAIN[31][2]MAIN[32][2]MAIN[32][3]MAIN[33][1]CELL.IMUX_CLB_C3
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[2]
00011110CELL.GCLK[2]
00101011CELL.SINGLE_V[3]
00101101CELL.SINGLE_V[7]
00110011CELL.DOUBLE_V0[0]
00110101CELL.DOUBLE_V1[0]
00111010CELL.LONG_V[3]
00111100CELL.LONG_V[2]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[1]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB_W switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[7][7]MAIN[8][8]MAIN[6][7]MAIN[6][6]MAIN[7][9]MAIN[7][8]MAIN[6][9]MAIN[7][6]CELL.IMUX_CLB_C4
Source
00001111CELL.SINGLE_H[1]
00011011CELL.DOUBLE_H0[0]
00011101CELL.SINGLE_H[6]
00111111CELL.SINGLE_H[0]
01000111CELL.LONG_H[4]
01001110CELL.LONG_H[3]
01010011CELL.SINGLE_H[2]
01010101CELL.SINGLE_H[3]
01011010CELL.DOUBLE_H1[0]
01011100CELL_N.LONG_H[1]
01110111CELL.DOUBLE_H1[1]
01111110CELL.DOUBLE_H0[1]
11001111CELL.SINGLE_H[4]
11011011CELL.SINGLE_H[7]
11011101CELL_N.LONG_H[2]
11111111CELL.SINGLE_H[5]
xc4000e CLB_W switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[14][4]MAIN[20][4]MAIN[19][5]MAIN[17][5]MAIN[20][5]MAIN[19][4]MAIN[18][5]MAIN[18][4]CELL.IMUX_CLB_K
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[3]
01101111CELL.SINGLE_V[6]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[5]
xc4000e CLB_W switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[20][6]MAIN[16][6]MAIN[19][6]MAIN[17][6]MAIN[18][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB_W switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[20][7]MAIN[16][7]MAIN[19][7]MAIN[17][7]MAIN[18][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB_W switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[16][8]MAIN[18][8]MAIN[19][8]MAIN[17][8]MAIN[20][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000e CLB_W switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[16][9]MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000e CLB_W bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000e CLB_W bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[19][0]
F bit 1!MAIN[15][0]
F bit 2!MAIN[20][0]
F bit 3!MAIN[16][0]
F bit 4!MAIN[20][2]
F bit 5!MAIN[16][2]
F bit 6!MAIN[19][2]
F bit 7!MAIN[15][2]
F bit 8!MAIN[17][0]
F bit 9!MAIN[13][0]
F bit 10!MAIN[18][0]
F bit 11!MAIN[14][0]
F bit 12!MAIN[18][2]
F bit 13!MAIN[14][2]
F bit 14!MAIN[17][2]
F bit 15!MAIN[13][2]
G bit 0!MAIN[1][2]
G bit 1!MAIN[0][0]
G bit 2!MAIN[3][2]
G bit 3!MAIN[2][0]
G bit 4!MAIN[5][2]
G bit 5!MAIN[4][0]
G bit 6!MAIN[7][2]
G bit 7!MAIN[6][0]
G bit 8!MAIN[0][2]
G bit 9!MAIN[1][0]
G bit 10!MAIN[2][2]
G bit 11!MAIN[3][0]
G bit 12!MAIN[4][2]
G bit 13!MAIN[5][0]
G bit 14!MAIN[6][2]
G bit 15!MAIN[7][0]
H bit 0!MAIN[6][3]
H bit 1!MAIN[7][3]
H bit 2!MAIN[5][3]
H bit 3!MAIN[4][3]
H bit 4!MAIN[9][3]
H bit 5!MAIN[8][3]
H bit 6!MAIN[10][3]
H bit 7!MAIN[13][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[11][4]
FFY_SRVAL bit 0!MAIN[9][5]
FFX_EC_ENABLE!MAIN[13][5]
FFY_EC_ENABLE!MAIN[7][5]
FFX_SR_ENABLE!MAIN[11][5]
FFY_SR_ENABLE!MAIN[8][5]
FFX_CLK_INV!MAIN[16][5]
FFY_CLK_INV!MAIN[15][5]
MUX_CIN[enum: CLB_MUX_CIN]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[11][3]
READBACK_X bit 0!MAIN[16][4]
READBACK_Y bit 0!MAIN[3][5]
READBACK_XQ bit 0!MAIN[12][5]
READBACK_YQ bit 0!MAIN[8][4]
F_RAM_ENABLE!MAIN[12][2]
G_RAM_ENABLE!MAIN[8][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[2][1]
RAM_SYNC_ENABLE!MAIN[6][1]
RAM_CLK_INV!MAIN[5][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
xc4000e CLB_W enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[13][4]MAIN[16][3]MAIN[15][3]MAIN[15][4]
C11111
C20011
C30101
C40110
xc4000e CLB_W enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[17][3]MAIN[19][3]MAIN[18][3]MAIN[17][4]
C10011
C21111
C30101
C40110
xc4000e CLB_W enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[2][3]MAIN[3][4]MAIN[3][3]MAIN[4][4]
C10011
C20101
C31111
C40110
xc4000e CLB_W enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[0][4]MAIN[1][4]MAIN[2][4]MAIN[1][3]
C10011
C20101
C30110
C41111
xc4000e CLB_W enum CLB_MUX_X
CLB.MUX_XMAIN[14][3]
F0
H1
xc4000e CLB_W enum CLB_MUX_Y
CLB.MUX_YMAIN[5][4]
G0
H1
xc4000e CLB_W enum CLB_MUX_XQ
CLB.MUX_XQMAIN[20][3]
DIN0
FFX1
xc4000e CLB_W enum CLB_MUX_YQ
CLB.MUX_YQMAIN[0][3]
EC0
FFY1
xc4000e CLB_W enum CLB_MUX_D
CLB.MUX_DXMAIN[9][4]MAIN[14][6]MAIN[10][4]MAIN[12][4]
CLB.MUX_DYMAIN[4][5]MAIN[5][5]MAIN[7][4]MAIN[6][4]
F1111
G0011
H0101
DIN0110
xc4000e CLB_W enum CLB_MUX_CIN
CLB.MUX_CINMAIN[9][0]
COUT_S1
COUT_N0
xc4000e CLB_W enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[11][2]MAIN[12][0]
ADD01
SUB11
ADDSUB10
xc4000e CLB_W enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[12][3]MAIN[9][2]
CONST_011
CONST_110
XOR01
xc4000e CLB_W enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[10][0]MAIN[11][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000e CLB_W enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[8][0]
CONST_11
XOR0
xc4000e CLB_W enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[10][2]
_32X11
_16X20
xc4000e CLB_W enum CLB_MUX_H0
CLB.MUX_H0MAIN[3][1]
G1
SR0
xc4000e CLB_W enum CLB_MUX_H2
CLB.MUX_H2MAIN[7][1]
F1
DIN0

Bels TBUF

xc4000e CLB_W bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000e CLB_W bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[22][4]!MAIN[22][6]

Bel wires

xc4000e CLB_W bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000e CLB_W rect MAIN
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 2
B8 - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 2 INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 3
B7 INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7
B6 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 6
B5 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 3 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_K bit 4 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE CLB: ! READBACK_XQ bit 0 CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 CLB: ! READBACK_Y bit 0 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ
B4 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 CLB: MUX_DIN bit 0 CLB: ! READBACK_X bit 0 CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 7 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 CLB: ! READBACK_YQ bit 0 CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3
B3 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 1 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 1 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 4 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 7 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 7 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0
B2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_G1 bit 1 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 CLB: ! G bit 8
B1 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 6 - INT: mux CELL.IMUX_CLB_G3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 3 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 3 - - - - - - - - - - - - - CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV - CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE - -
B0 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 8 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: MUX_CIN bit 0 CLB: CARRY_GPROP bit 0 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1
xc4000e CLB_W rect MAIN_S
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_W rect MAIN_W
BitFrame
F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_F1 bit 0 - - - - - - -
B2 - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_G3 bit 0 - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_W rect MAIN_N
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_W rect MAIN_E
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLB_E

Cells: 3

Switchbox INT

xc4000e CLB_E switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[21][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[25][8]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[33][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[35][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[27][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[33][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[29][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[29][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[26][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[30][8]
xc4000e CLB_E switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[14][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y!MAIN[2][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ!MAIN[6][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[11][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[13][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[28][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y!MAIN[1][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[22][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ!MAIN[0][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[13][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[29][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[12][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[27][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[35][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[34][7]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[21][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ!MAIN[23][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[23][8]
CELL.SINGLE_V[1]CELL.OUT_CLB_X!MAIN[24][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[29][8]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[25][4]
CELL.SINGLE_V[3]CELL.LONG_H[2]!MAIN_S[28][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[30][4]
CELL.SINGLE_V[4]CELL.LONG_H[3]!MAIN[21][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ!MAIN[34][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[35][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X!MAIN[31][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[35][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[34][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[21][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[33][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[13][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y!MAIN[10][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ!MAIN[15][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[21][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X!MAIN[32][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ!MAIN[35][4]
xc4000e CLB_E switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[23][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[25][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[24][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[24][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[26][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[28][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[26][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[23][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[25][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[31][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[34][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[30][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[30][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[31][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[32][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[30][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[31][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[31][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[33][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[30][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[32][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[21][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[23][5]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[25][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[26][5]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[26][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[27][9]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[27][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[28][7]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[34][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[32][6]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[31][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[29][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[32][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[34][9]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[24][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[26][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[25][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[31][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[24][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[22][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[23][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[27][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[28][3]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[24][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[24][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[28][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[29][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
xc4000e CLB_E switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[26][2]MAIN[28][0]MAIN[27][1]MAIN[26][0]MAIN[27][3]MAIN[26][1]MAIN[27][0]MAIN[27][2]MAIN_W[1][1]CELL.IMUX_CLB_F1
Source
001001111CELL.SINGLE_V[3]
001010111CELL.LONG_V[4]
001011101CELL.SINGLE_V[7]
001111111CELL.SINGLE_V[0]
010001111CELL.LONG_V[3]
010010111CELL.DOUBLE_V0[1]
010011101CELL.LONG_V[0]
010111111CELL.SINGLE_V[1]
011001011CELL.SINGLE_V[5]
011010011CELL.LONG_V[1]
011011001CELL.SINGLE_V[6]
011011110CELL.GCLK[1]
011111011CELL.DOUBLE_V1[1]
111001111CELL.DOUBLE_V1[0]
111010111CELL.SINGLE_V[4]
111011101CELL.DOUBLE_V0[0]
111111111CELL.SINGLE_V[2]
xc4000e CLB_E switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[10][9]MAIN[10][7]MAIN[11][6]MAIN[11][8]MAIN[11][9]MAIN[12][8]MAIN[12][7]MAIN[12][6]CELL.IMUX_CLB_F2
Source
00110011CELL.SINGLE_H[5]
00110101CELL.LONG_H[5]
00110110CELL.DOUBLE_H1[1]
00111111CELL.SINGLE_H[0]
01010011CELL.SINGLE_H[4]
01010101CELL.DOUBLE_H0[1]
01010110CELL.LONG_H[4]
01011111CELL.SINGLE_H[1]
01100011CELL.SINGLE_H[6]
01100101CELL_N.LONG_H[2]
01100110CELL_N.LONG_H[0]
01101111CELL.SINGLE_H[3]
11110011CELL.DOUBLE_H0[0]
11110101CELL.SINGLE_H[7]
11110110CELL.DOUBLE_H1[0]
11111111CELL.SINGLE_H[2]
xc4000e CLB_E switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[33][2]MAIN[35][0]MAIN[34][2]MAIN[35][1]MAIN[33][0]MAIN[34][1]MAIN[35][2]MAIN[34][0]MAIN[35][3]CELL.IMUX_CLB_F3
Source
000011111CELL.SINGLE_V[0]
000111011CELL.DOUBLE_V0[0]
000111101CELL.LONG_V[2]
001111111CELL.SINGLE_V[3]
010001111CELL.DOUBLE_V1[1]
010010111CELL.LONG_V[1]
010101011CELL.DOUBLE_V0[1]
010101101CELL.LONG_V[5]
010110011CELL.SINGLE_V[4]
010110101CELL.LONG_V[4]
010111110CELL.GCLK[0]
011101111CELL.SINGLE_V[1]
011110111CELL.SINGLE_V[2]
110011111CELL.SINGLE_V[6]
110111011CELL.DOUBLE_V1[0]
110111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[7]
xc4000e CLB_E switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[9][7]MAIN[8][6]MAIN[9][6]MAIN[9][8]MAIN[8][7]MAIN[10][6]MAIN[8][9]MAIN[9][9]MAIN[10][8]CELL.IMUX_CLB_F4
Source
000111111CELL.SPECIAL_CLB_CIN
001001111CELL.SINGLE_H[0]
001011011CELL.DOUBLE_H1[0]
001011101CELL_N.LONG_H[0]
001100111CELL.LONG_H[5]
001101110CELL.LONG_H[3]
001110011CELL.SINGLE_H[2]
001110101CELL.SINGLE_H[3]
001111010CELL.SINGLE_H[7]
001111100CELL_N.LONG_H[1]
011011111CELL.SINGLE_H[1]
011110111CELL.DOUBLE_H1[1]
011111110CELL.DOUBLE_H0[1]
101101111CELL.SINGLE_H[5]
101111011CELL.DOUBLE_H0[0]
101111101CELL.SINGLE_H[6]
111111111CELL.SINGLE_H[4]
xc4000e CLB_E switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[21][0]MAIN[21][3]MAIN[23][0]MAIN[23][1]MAIN[22][1]MAIN[21][1]MAIN[22][0]MAIN[21][2]MAIN[22][2]CELL.IMUX_CLB_G1
Source
000011111CELL.SINGLE_V[0]
000101111CELL.SINGLE_V[2]
000111011CELL.SINGLE_V[4]
001010111CELL.LONG_V[4]
001011101CELL.LONG_V[3]
001100111CELL.SINGLE_V[1]
001101101CELL.DOUBLE_V1[0]
001110011CELL.DOUBLE_V0[1]
001111001CELL.LONG_V[0]
001111110CELL.GCLK[1]
011011111CELL.SINGLE_V[3]
011101111CELL.DOUBLE_V0[0]
011111011CELL.SINGLE_V[7]
100111111CELL.DOUBLE_V1[1]
101110111CELL.LONG_V[1]
101111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[6]
xc4000e CLB_E switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[2][7]MAIN[3][7]MAIN[3][9]MAIN[2][6]MAIN[3][8]MAIN[2][8]MAIN[2][9]MAIN[3][6]MAIN[4][8]CELL.IMUX_CLB_G2
Source
000111111CELL.SPECIAL_CLB_COUT0
001001111CELL.LONG_H[4]
001011101CELL.SINGLE_H[4]
001011110CELL.LONG_H[5]
001100111CELL.SINGLE_H[2]
001101011CELL.SINGLE_H[3]
001110101CELL.SINGLE_H[7]
001110110CELL.DOUBLE_H0[0]
001111001CELL_N.LONG_H[2]
001111010CELL.SINGLE_H[6]
011011111CELL.SINGLE_H[1]
011110111CELL_N.LONG_H[0]
011111011CELL.DOUBLE_H1[0]
101101111CELL.DOUBLE_H1[1]
101111101CELL.SINGLE_H[5]
101111110CELL.DOUBLE_H0[1]
111111111CELL.SINGLE_H[0]
xc4000e CLB_E switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[29][0]MAIN[28][2]MAIN[30][1]MAIN[28][1]MAIN[29][2]MAIN[30][0]MAIN[29][1]MAIN[30][2]MAIN[30][3]MAIN_W[0][1]CELL.IMUX_CLB_G3
Source
0001111111CELL.SPECIAL_CLB_CIN
0010011111CELL.SINGLE_V[0]
0010101111CELL.SINGLE_V[2]
0010111011CELL.SINGLE_V[4]
0011010111CELL.LONG_V[4]
0011011101CELL.LONG_V[2]
0011100111CELL.SINGLE_V[1]
0011101101CELL.SINGLE_V[6]
0011110011CELL.DOUBLE_V0[1]
0011111001CELL.LONG_V[5]
0011111110CELL.GCLK[0]
0111011111CELL.DOUBLE_V0[0]
0111101111CELL.SINGLE_V[5]
0111111011CELL.DOUBLE_V1[0]
1010111111CELL.DOUBLE_V1[1]
1011110111CELL.LONG_V[1]
1011111101CELL.SINGLE_V[7]
1111111111CELL.SINGLE_V[3]
xc4000e CLB_E switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[5][9]MAIN[4][9]MAIN[6][8]MAIN[4][6]MAIN[4][7]MAIN[5][7]MAIN[5][8]MAIN[5][6]CELL.IMUX_CLB_G4
Source
00001111CELL.SINGLE_H[0]
00010111CELL.SINGLE_H[1]
00011101CELL_N.LONG_H[0]
00101011CELL.DOUBLE_H1[1]
00101110CELL.LONG_H[3]
00110011CELL.LONG_H[5]
00110110CELL.DOUBLE_H0[1]
00111001CELL.SINGLE_H[3]
00111100CELL.SINGLE_H[6]
01011111CELL.DOUBLE_H1[0]
01111011CELL.SINGLE_H[2]
01111110CELL.DOUBLE_H0[0]
10101111CELL.SINGLE_H[5]
10110111CELL.SINGLE_H[4]
10111101CELL_N.LONG_H[1]
11111111CELL.SINGLE_H[7]
xc4000e CLB_E switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[23][3]MAIN[23][2]MAIN[25][1]MAIN[24][0]MAIN[24][1]MAIN[25][2]MAIN[24][2]MAIN[25][0]CELL.IMUX_CLB_C1
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[1]
00011110CELL.GCLK[3]
00101011CELL.DOUBLE_V0[0]
00101101CELL.DOUBLE_V1[0]
00110011CELL.SINGLE_V[3]
00110101CELL.SINGLE_V[7]
00111010CELL.LONG_V[2]
00111100CELL.LONG_V[3]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[2]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB_E switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[0][7]MAIN[0][6]MAIN[1][7]MAIN[1][9]MAIN[0][8]MAIN[0][9]MAIN[1][6]MAIN[1][8]CELL.IMUX_CLB_C2
Source
00001111CELL.LONG_H[4]
00011101CELL.SINGLE_H[5]
00011110CELL.LONG_H[3]
00111111CELL.SINGLE_H[0]
01000111CELL.SINGLE_H[2]
01001011CELL.SINGLE_H[3]
01010101CELL.SINGLE_H[7]
01010110CELL.DOUBLE_H0[0]
01011001CELL_N.LONG_H[1]
01011010CELL.SINGLE_H[6]
01110111CELL.DOUBLE_H1[0]
01111011CELL_N.LONG_H[2]
11001111CELL.DOUBLE_H1[1]
11011101CELL.SINGLE_H[4]
11011110CELL.DOUBLE_H0[1]
11111111CELL.SINGLE_H[1]
xc4000e CLB_E switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[31][0]MAIN[31][1]MAIN[32][1]MAIN[32][0]MAIN[31][2]MAIN[32][2]MAIN[32][3]MAIN[33][1]CELL.IMUX_CLB_C3
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[2]
00011110CELL.GCLK[2]
00101011CELL.SINGLE_V[3]
00101101CELL.SINGLE_V[7]
00110011CELL.DOUBLE_V0[0]
00110101CELL.DOUBLE_V1[0]
00111010CELL.LONG_V[3]
00111100CELL.LONG_V[2]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[1]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB_E switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[7][7]MAIN[8][8]MAIN[6][7]MAIN[6][6]MAIN[7][9]MAIN[7][8]MAIN[6][9]MAIN[7][6]CELL.IMUX_CLB_C4
Source
00001111CELL.SINGLE_H[1]
00011011CELL.DOUBLE_H0[0]
00011101CELL.SINGLE_H[6]
00111111CELL.SINGLE_H[0]
01000111CELL.LONG_H[4]
01001110CELL.LONG_H[3]
01010011CELL.SINGLE_H[2]
01010101CELL.SINGLE_H[3]
01011010CELL.DOUBLE_H1[0]
01011100CELL_N.LONG_H[1]
01110111CELL.DOUBLE_H1[1]
01111110CELL.DOUBLE_H0[1]
11001111CELL.SINGLE_H[4]
11011011CELL.SINGLE_H[7]
11011101CELL_N.LONG_H[2]
11111111CELL.SINGLE_H[5]
xc4000e CLB_E switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[14][4]MAIN[20][4]MAIN[19][5]MAIN[17][5]MAIN[20][5]MAIN[19][4]MAIN[18][5]MAIN[18][4]CELL.IMUX_CLB_K
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[3]
01101111CELL.SINGLE_V[6]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[5]
xc4000e CLB_E switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[20][6]MAIN[16][6]MAIN[19][6]MAIN[17][6]MAIN[18][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB_E switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[20][7]MAIN[16][7]MAIN[19][7]MAIN[17][7]MAIN[18][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB_E switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[16][8]MAIN[18][8]MAIN[19][8]MAIN[17][8]MAIN[20][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000e CLB_E switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[16][9]MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000e CLB_E bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000e CLB_E bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[19][0]
F bit 1!MAIN[15][0]
F bit 2!MAIN[20][0]
F bit 3!MAIN[16][0]
F bit 4!MAIN[20][2]
F bit 5!MAIN[16][2]
F bit 6!MAIN[19][2]
F bit 7!MAIN[15][2]
F bit 8!MAIN[17][0]
F bit 9!MAIN[13][0]
F bit 10!MAIN[18][0]
F bit 11!MAIN[14][0]
F bit 12!MAIN[18][2]
F bit 13!MAIN[14][2]
F bit 14!MAIN[17][2]
F bit 15!MAIN[13][2]
G bit 0!MAIN[1][2]
G bit 1!MAIN[0][0]
G bit 2!MAIN[3][2]
G bit 3!MAIN[2][0]
G bit 4!MAIN[5][2]
G bit 5!MAIN[4][0]
G bit 6!MAIN[7][2]
G bit 7!MAIN[6][0]
G bit 8!MAIN[0][2]
G bit 9!MAIN[1][0]
G bit 10!MAIN[2][2]
G bit 11!MAIN[3][0]
G bit 12!MAIN[4][2]
G bit 13!MAIN[5][0]
G bit 14!MAIN[6][2]
G bit 15!MAIN[7][0]
H bit 0!MAIN[6][3]
H bit 1!MAIN[7][3]
H bit 2!MAIN[5][3]
H bit 3!MAIN[4][3]
H bit 4!MAIN[9][3]
H bit 5!MAIN[8][3]
H bit 6!MAIN[10][3]
H bit 7!MAIN[13][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[11][4]
FFY_SRVAL bit 0!MAIN[9][5]
FFX_EC_ENABLE!MAIN[13][5]
FFY_EC_ENABLE!MAIN[7][5]
FFX_SR_ENABLE!MAIN[11][5]
FFY_SR_ENABLE!MAIN[8][5]
FFX_CLK_INV!MAIN[16][5]
FFY_CLK_INV!MAIN[15][5]
MUX_CIN[enum: CLB_MUX_CIN]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[11][3]
READBACK_X bit 0!MAIN[16][4]
READBACK_Y bit 0!MAIN[3][5]
READBACK_XQ bit 0!MAIN[12][5]
READBACK_YQ bit 0!MAIN[8][4]
F_RAM_ENABLE!MAIN[12][2]
G_RAM_ENABLE!MAIN[8][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[2][1]
RAM_SYNC_ENABLE!MAIN[6][1]
RAM_CLK_INV!MAIN[5][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
xc4000e CLB_E enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[13][4]MAIN[16][3]MAIN[15][3]MAIN[15][4]
C11111
C20011
C30101
C40110
xc4000e CLB_E enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[17][3]MAIN[19][3]MAIN[18][3]MAIN[17][4]
C10011
C21111
C30101
C40110
xc4000e CLB_E enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[2][3]MAIN[3][4]MAIN[3][3]MAIN[4][4]
C10011
C20101
C31111
C40110
xc4000e CLB_E enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[0][4]MAIN[1][4]MAIN[2][4]MAIN[1][3]
C10011
C20101
C30110
C41111
xc4000e CLB_E enum CLB_MUX_X
CLB.MUX_XMAIN[14][3]
F0
H1
xc4000e CLB_E enum CLB_MUX_Y
CLB.MUX_YMAIN[5][4]
G0
H1
xc4000e CLB_E enum CLB_MUX_XQ
CLB.MUX_XQMAIN[20][3]
DIN0
FFX1
xc4000e CLB_E enum CLB_MUX_YQ
CLB.MUX_YQMAIN[0][3]
EC0
FFY1
xc4000e CLB_E enum CLB_MUX_D
CLB.MUX_DXMAIN[9][4]MAIN[14][6]MAIN[10][4]MAIN[12][4]
CLB.MUX_DYMAIN[4][5]MAIN[5][5]MAIN[7][4]MAIN[6][4]
F1111
G0011
H0101
DIN0110
xc4000e CLB_E enum CLB_MUX_CIN
CLB.MUX_CINMAIN[9][0]
COUT_S1
COUT_N0
xc4000e CLB_E enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[11][2]MAIN[12][0]
ADD01
SUB11
ADDSUB10
xc4000e CLB_E enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[12][3]MAIN[9][2]
CONST_011
CONST_110
XOR01
xc4000e CLB_E enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[10][0]MAIN[11][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000e CLB_E enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[8][0]
CONST_11
XOR0
xc4000e CLB_E enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[10][2]
_32X11
_16X20
xc4000e CLB_E enum CLB_MUX_H0
CLB.MUX_H0MAIN[3][1]
G1
SR0
xc4000e CLB_E enum CLB_MUX_H2
CLB.MUX_H2MAIN[7][1]
F1
DIN0

Bels TBUF

xc4000e CLB_E bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000e CLB_E bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[22][4]!MAIN[22][6]

Bel wires

xc4000e CLB_E bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000e CLB_E rect MAIN
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 2
B8 - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 2 INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 3
B7 INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7
B6 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 6
B5 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 3 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_K bit 4 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE CLB: ! READBACK_XQ bit 0 CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 CLB: ! READBACK_Y bit 0 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ
B4 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 CLB: MUX_DIN bit 0 CLB: ! READBACK_X bit 0 CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 7 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 CLB: ! READBACK_YQ bit 0 CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3
B3 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 1 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 1 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 4 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 7 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 7 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0
B2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_G1 bit 1 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 CLB: ! G bit 8
B1 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 3 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 3 - - - - - - - - - - - - - CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV - CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE - -
B0 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 8 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: MUX_CIN bit 0 CLB: CARRY_GPROP bit 0 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1
xc4000e CLB_E rect MAIN_S
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_E rect MAIN_W
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_F1 bit 0 INT: mux CELL.IMUX_CLB_G3 bit 0
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_E rect MAIN_N
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_E rect MAIN_E
BitFrame
F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLB_S

Cells: 3

Switchbox INT

xc4000e CLB_S switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[21][11]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[25][11]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[33][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[35][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[27][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[33][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[29][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[29][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[26][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[30][8]
xc4000e CLB_S switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[14][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y!MAIN[2][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ!MAIN[6][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[11][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[13][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[28][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y!MAIN[1][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[22][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ!MAIN[0][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[13][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[29][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[12][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[27][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[35][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[34][7]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[21][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ!MAIN[23][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[23][11]
CELL.SINGLE_V[1]CELL.OUT_CLB_X!MAIN[24][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[29][11]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[25][4]
CELL.SINGLE_V[3]CELL.LONG_H[2]!MAIN_S[28][12]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[30][4]
CELL.SINGLE_V[4]CELL.LONG_H[3]!MAIN[21][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ!MAIN[34][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[35][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X!MAIN[31][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[35][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[34][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[21][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[33][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[13][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y!MAIN[10][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ!MAIN[15][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[21][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X!MAIN[32][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ!MAIN[35][4]
xc4000e CLB_S switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[23][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[25][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[24][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[24][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[26][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[28][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[26][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[23][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[25][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[31][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[34][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[30][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[30][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[31][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[32][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[30][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[31][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[31][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[33][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[30][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[32][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[21][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[23][5]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[25][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[26][5]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[26][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[27][9]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[27][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[28][7]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[34][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[32][6]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[31][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[29][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[32][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[34][9]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[24][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[26][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[25][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[31][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[24][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[22][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[23][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[27][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[28][3]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[24][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[24][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[28][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[29][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
xc4000e CLB_S switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[26][2]MAIN[28][0]MAIN[27][1]MAIN[26][0]MAIN[27][3]MAIN[26][1]MAIN[27][0]MAIN[27][2]MAIN_W[1][1]CELL.IMUX_CLB_F1
Source
001001111CELL.SINGLE_V[3]
001010111CELL.LONG_V[4]
001011101CELL.SINGLE_V[7]
001111111CELL.SINGLE_V[0]
010001111CELL.LONG_V[3]
010010111CELL.DOUBLE_V0[1]
010011101CELL.LONG_V[0]
010111111CELL.SINGLE_V[1]
011001011CELL.SINGLE_V[5]
011010011CELL.LONG_V[1]
011011001CELL.SINGLE_V[6]
011011110CELL.GCLK[1]
011111011CELL.DOUBLE_V1[1]
111001111CELL.DOUBLE_V1[0]
111010111CELL.SINGLE_V[4]
111011101CELL.DOUBLE_V0[0]
111111111CELL.SINGLE_V[2]
xc4000e CLB_S switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[10][9]MAIN[10][7]MAIN[11][6]MAIN[11][8]MAIN[11][9]MAIN[12][8]MAIN[12][7]MAIN[12][6]CELL.IMUX_CLB_F2
Source
00110011CELL.SINGLE_H[5]
00110101CELL.LONG_H[5]
00110110CELL.DOUBLE_H1[1]
00111111CELL.SINGLE_H[0]
01010011CELL.SINGLE_H[4]
01010101CELL.DOUBLE_H0[1]
01010110CELL.LONG_H[4]
01011111CELL.SINGLE_H[1]
01100011CELL.SINGLE_H[6]
01100101CELL_N.LONG_H[2]
01100110CELL_N.LONG_H[0]
01101111CELL.SINGLE_H[3]
11110011CELL.DOUBLE_H0[0]
11110101CELL.SINGLE_H[7]
11110110CELL.DOUBLE_H1[0]
11111111CELL.SINGLE_H[2]
xc4000e CLB_S switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[33][2]MAIN[35][0]MAIN[34][2]MAIN[35][1]MAIN[33][0]MAIN[34][1]MAIN[35][2]MAIN[34][0]MAIN[35][3]CELL.IMUX_CLB_F3
Source
000011111CELL.SINGLE_V[0]
000111011CELL.DOUBLE_V0[0]
000111101CELL.LONG_V[2]
001111111CELL.SINGLE_V[3]
010001111CELL.DOUBLE_V1[1]
010010111CELL.LONG_V[1]
010101011CELL.DOUBLE_V0[1]
010101101CELL.LONG_V[5]
010110011CELL.SINGLE_V[4]
010110101CELL.LONG_V[4]
010111110CELL.GCLK[0]
011101111CELL.SINGLE_V[1]
011110111CELL.SINGLE_V[2]
110011111CELL.SINGLE_V[6]
110111011CELL.DOUBLE_V1[0]
110111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[7]
xc4000e CLB_S switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[9][7]MAIN[8][6]MAIN[9][6]MAIN[9][8]MAIN[8][7]MAIN[10][6]MAIN[8][9]MAIN[9][9]MAIN[10][8]CELL.IMUX_CLB_F4
Source
000111111CELL.SPECIAL_CLB_CIN
001001111CELL.SINGLE_H[0]
001011011CELL.DOUBLE_H1[0]
001011101CELL_N.LONG_H[0]
001100111CELL.LONG_H[5]
001101110CELL.LONG_H[3]
001110011CELL.SINGLE_H[2]
001110101CELL.SINGLE_H[3]
001111010CELL.SINGLE_H[7]
001111100CELL_N.LONG_H[1]
011011111CELL.SINGLE_H[1]
011110111CELL.DOUBLE_H1[1]
011111110CELL.DOUBLE_H0[1]
101101111CELL.SINGLE_H[5]
101111011CELL.DOUBLE_H0[0]
101111101CELL.SINGLE_H[6]
111111111CELL.SINGLE_H[4]
xc4000e CLB_S switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[21][0]MAIN[21][3]MAIN[23][0]MAIN[23][1]MAIN[22][1]MAIN[21][1]MAIN[22][0]MAIN[21][2]MAIN[22][2]CELL.IMUX_CLB_G1
Source
000011111CELL.SINGLE_V[0]
000101111CELL.SINGLE_V[2]
000111011CELL.SINGLE_V[4]
001010111CELL.LONG_V[4]
001011101CELL.LONG_V[3]
001100111CELL.SINGLE_V[1]
001101101CELL.DOUBLE_V1[0]
001110011CELL.DOUBLE_V0[1]
001111001CELL.LONG_V[0]
001111110CELL.GCLK[1]
011011111CELL.SINGLE_V[3]
011101111CELL.DOUBLE_V0[0]
011111011CELL.SINGLE_V[7]
100111111CELL.DOUBLE_V1[1]
101110111CELL.LONG_V[1]
101111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[6]
xc4000e CLB_S switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[2][7]MAIN[3][7]MAIN[3][9]MAIN[2][6]MAIN[3][8]MAIN[2][8]MAIN[2][9]MAIN[3][6]MAIN[4][8]CELL.IMUX_CLB_G2
Source
000111111CELL.SPECIAL_CLB_COUT0
001001111CELL.LONG_H[4]
001011101CELL.SINGLE_H[4]
001011110CELL.LONG_H[5]
001100111CELL.SINGLE_H[2]
001101011CELL.SINGLE_H[3]
001110101CELL.SINGLE_H[7]
001110110CELL.DOUBLE_H0[0]
001111001CELL_N.LONG_H[2]
001111010CELL.SINGLE_H[6]
011011111CELL.SINGLE_H[1]
011110111CELL_N.LONG_H[0]
011111011CELL.DOUBLE_H1[0]
101101111CELL.DOUBLE_H1[1]
101111101CELL.SINGLE_H[5]
101111110CELL.DOUBLE_H0[1]
111111111CELL.SINGLE_H[0]
xc4000e CLB_S switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[29][0]MAIN[28][2]MAIN[30][1]MAIN[28][1]MAIN[29][2]MAIN[30][0]MAIN[29][1]MAIN[30][2]MAIN[30][3]MAIN_W[0][1]CELL.IMUX_CLB_G3
Source
0001111111CELL.SPECIAL_CLB_CIN
0010011111CELL.SINGLE_V[0]
0010101111CELL.SINGLE_V[2]
0010111011CELL.SINGLE_V[4]
0011010111CELL.LONG_V[4]
0011011101CELL.LONG_V[2]
0011100111CELL.SINGLE_V[1]
0011101101CELL.SINGLE_V[6]
0011110011CELL.DOUBLE_V0[1]
0011111001CELL.LONG_V[5]
0011111110CELL.GCLK[0]
0111011111CELL.DOUBLE_V0[0]
0111101111CELL.SINGLE_V[5]
0111111011CELL.DOUBLE_V1[0]
1010111111CELL.DOUBLE_V1[1]
1011110111CELL.LONG_V[1]
1011111101CELL.SINGLE_V[7]
1111111111CELL.SINGLE_V[3]
xc4000e CLB_S switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[5][9]MAIN[4][9]MAIN[6][8]MAIN[4][6]MAIN[4][7]MAIN[5][7]MAIN[5][8]MAIN[5][6]CELL.IMUX_CLB_G4
Source
00001111CELL.SINGLE_H[0]
00010111CELL.SINGLE_H[1]
00011101CELL_N.LONG_H[0]
00101011CELL.DOUBLE_H1[1]
00101110CELL.LONG_H[3]
00110011CELL.LONG_H[5]
00110110CELL.DOUBLE_H0[1]
00111001CELL.SINGLE_H[3]
00111100CELL.SINGLE_H[6]
01011111CELL.DOUBLE_H1[0]
01111011CELL.SINGLE_H[2]
01111110CELL.DOUBLE_H0[0]
10101111CELL.SINGLE_H[5]
10110111CELL.SINGLE_H[4]
10111101CELL_N.LONG_H[1]
11111111CELL.SINGLE_H[7]
xc4000e CLB_S switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[23][3]MAIN[23][2]MAIN[25][1]MAIN[24][0]MAIN[24][1]MAIN[25][2]MAIN[24][2]MAIN[25][0]CELL.IMUX_CLB_C1
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[1]
00011110CELL.GCLK[3]
00101011CELL.DOUBLE_V0[0]
00101101CELL.DOUBLE_V1[0]
00110011CELL.SINGLE_V[3]
00110101CELL.SINGLE_V[7]
00111010CELL.LONG_V[2]
00111100CELL.LONG_V[3]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[2]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB_S switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[0][7]MAIN[0][6]MAIN[1][7]MAIN[1][9]MAIN[0][8]MAIN[0][9]MAIN[1][6]MAIN[1][8]CELL.IMUX_CLB_C2
Source
00001111CELL.LONG_H[4]
00011101CELL.SINGLE_H[5]
00011110CELL.LONG_H[3]
00111111CELL.SINGLE_H[0]
01000111CELL.SINGLE_H[2]
01001011CELL.SINGLE_H[3]
01010101CELL.SINGLE_H[7]
01010110CELL.DOUBLE_H0[0]
01011001CELL_N.LONG_H[1]
01011010CELL.SINGLE_H[6]
01110111CELL.DOUBLE_H1[0]
01111011CELL_N.LONG_H[2]
11001111CELL.DOUBLE_H1[1]
11011101CELL.SINGLE_H[4]
11011110CELL.DOUBLE_H0[1]
11111111CELL.SINGLE_H[1]
xc4000e CLB_S switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[31][0]MAIN[31][1]MAIN[32][1]MAIN[32][0]MAIN[31][2]MAIN[32][2]MAIN[32][3]MAIN[33][1]CELL.IMUX_CLB_C3
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[2]
00011110CELL.GCLK[2]
00101011CELL.SINGLE_V[3]
00101101CELL.SINGLE_V[7]
00110011CELL.DOUBLE_V0[0]
00110101CELL.DOUBLE_V1[0]
00111010CELL.LONG_V[3]
00111100CELL.LONG_V[2]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[1]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB_S switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[7][7]MAIN[8][8]MAIN[6][7]MAIN[6][6]MAIN[7][9]MAIN[7][8]MAIN[6][9]MAIN[7][6]CELL.IMUX_CLB_C4
Source
00001111CELL.SINGLE_H[1]
00011011CELL.DOUBLE_H0[0]
00011101CELL.SINGLE_H[6]
00111111CELL.SINGLE_H[0]
01000111CELL.LONG_H[4]
01001110CELL.LONG_H[3]
01010011CELL.SINGLE_H[2]
01010101CELL.SINGLE_H[3]
01011010CELL.DOUBLE_H1[0]
01011100CELL_N.LONG_H[1]
01110111CELL.DOUBLE_H1[1]
01111110CELL.DOUBLE_H0[1]
11001111CELL.SINGLE_H[4]
11011011CELL.SINGLE_H[7]
11011101CELL_N.LONG_H[2]
11111111CELL.SINGLE_H[5]
xc4000e CLB_S switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[14][4]MAIN[20][4]MAIN[19][5]MAIN[17][5]MAIN[20][5]MAIN[19][4]MAIN[18][5]MAIN[18][4]CELL.IMUX_CLB_K
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[3]
01101111CELL.SINGLE_V[6]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[5]
xc4000e CLB_S switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[20][6]MAIN[16][6]MAIN[19][6]MAIN[17][6]MAIN[18][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB_S switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[20][7]MAIN[16][7]MAIN[19][7]MAIN[17][7]MAIN[18][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB_S switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[16][8]MAIN[18][8]MAIN[19][8]MAIN[17][8]MAIN[20][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000e CLB_S switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[16][9]MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000e CLB_S bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000e CLB_S bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[19][0]
F bit 1!MAIN[15][0]
F bit 2!MAIN[20][0]
F bit 3!MAIN[16][0]
F bit 4!MAIN[20][2]
F bit 5!MAIN[16][2]
F bit 6!MAIN[19][2]
F bit 7!MAIN[15][2]
F bit 8!MAIN[17][0]
F bit 9!MAIN[13][0]
F bit 10!MAIN[18][0]
F bit 11!MAIN[14][0]
F bit 12!MAIN[18][2]
F bit 13!MAIN[14][2]
F bit 14!MAIN[17][2]
F bit 15!MAIN[13][2]
G bit 0!MAIN[1][2]
G bit 1!MAIN[0][0]
G bit 2!MAIN[3][2]
G bit 3!MAIN[2][0]
G bit 4!MAIN[5][2]
G bit 5!MAIN[4][0]
G bit 6!MAIN[7][2]
G bit 7!MAIN[6][0]
G bit 8!MAIN[0][2]
G bit 9!MAIN[1][0]
G bit 10!MAIN[2][2]
G bit 11!MAIN[3][0]
G bit 12!MAIN[4][2]
G bit 13!MAIN[5][0]
G bit 14!MAIN[6][2]
G bit 15!MAIN[7][0]
H bit 0!MAIN[6][3]
H bit 1!MAIN[7][3]
H bit 2!MAIN[5][3]
H bit 3!MAIN[4][3]
H bit 4!MAIN[9][3]
H bit 5!MAIN[8][3]
H bit 6!MAIN[10][3]
H bit 7!MAIN[13][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[11][4]
FFY_SRVAL bit 0!MAIN[9][5]
FFX_EC_ENABLE!MAIN[13][5]
FFY_EC_ENABLE!MAIN[7][5]
FFX_SR_ENABLE!MAIN[11][5]
FFY_SR_ENABLE!MAIN[8][5]
FFX_CLK_INV!MAIN[16][5]
FFY_CLK_INV!MAIN[15][5]
MUX_CIN[enum: CLB_MUX_CIN]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[11][3]
READBACK_X bit 0!MAIN[16][4]
READBACK_Y bit 0!MAIN[3][5]
READBACK_XQ bit 0!MAIN[12][5]
READBACK_YQ bit 0!MAIN[8][4]
F_RAM_ENABLE!MAIN[12][2]
G_RAM_ENABLE!MAIN[8][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[2][1]
RAM_SYNC_ENABLE!MAIN[6][1]
RAM_CLK_INV!MAIN[5][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
xc4000e CLB_S enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[13][4]MAIN[16][3]MAIN[15][3]MAIN[15][4]
C11111
C20011
C30101
C40110
xc4000e CLB_S enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[17][3]MAIN[19][3]MAIN[18][3]MAIN[17][4]
C10011
C21111
C30101
C40110
xc4000e CLB_S enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[2][3]MAIN[3][4]MAIN[3][3]MAIN[4][4]
C10011
C20101
C31111
C40110
xc4000e CLB_S enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[0][4]MAIN[1][4]MAIN[2][4]MAIN[1][3]
C10011
C20101
C30110
C41111
xc4000e CLB_S enum CLB_MUX_X
CLB.MUX_XMAIN[14][3]
F0
H1
xc4000e CLB_S enum CLB_MUX_Y
CLB.MUX_YMAIN[5][4]
G0
H1
xc4000e CLB_S enum CLB_MUX_XQ
CLB.MUX_XQMAIN[20][3]
DIN0
FFX1
xc4000e CLB_S enum CLB_MUX_YQ
CLB.MUX_YQMAIN[0][3]
EC0
FFY1
xc4000e CLB_S enum CLB_MUX_D
CLB.MUX_DXMAIN[9][4]MAIN[14][6]MAIN[10][4]MAIN[12][4]
CLB.MUX_DYMAIN[4][5]MAIN[5][5]MAIN[7][4]MAIN[6][4]
F1111
G0011
H0101
DIN0110
xc4000e CLB_S enum CLB_MUX_CIN
CLB.MUX_CINMAIN[9][0]
COUT_S1
COUT_N0
xc4000e CLB_S enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[11][2]MAIN[12][0]
ADD01
SUB11
ADDSUB10
xc4000e CLB_S enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[12][3]MAIN[9][2]
CONST_011
CONST_110
XOR01
xc4000e CLB_S enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[10][0]MAIN[11][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000e CLB_S enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[8][0]
CONST_11
XOR0
xc4000e CLB_S enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[10][2]
_32X11
_16X20
xc4000e CLB_S enum CLB_MUX_H0
CLB.MUX_H0MAIN[3][1]
G1
SR0
xc4000e CLB_S enum CLB_MUX_H2
CLB.MUX_H2MAIN[7][1]
F1
DIN0

Bels TBUF

xc4000e CLB_S bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000e CLB_S bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[22][4]!MAIN[22][6]

Bel wires

xc4000e CLB_S bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000e CLB_S rect MAIN
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 2
B8 - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 2 INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 3
B7 INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7
B6 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 6
B5 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 3 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_K bit 4 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE CLB: ! READBACK_XQ bit 0 CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 CLB: ! READBACK_Y bit 0 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ
B4 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 CLB: MUX_DIN bit 0 CLB: ! READBACK_X bit 0 CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 7 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 CLB: ! READBACK_YQ bit 0 CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3
B3 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 1 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 1 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 4 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 7 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 7 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0
B2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_G1 bit 1 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 CLB: ! G bit 8
B1 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 3 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 3 - - - - - - - - - - - - - CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV - CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE - -
B0 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 8 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: MUX_CIN bit 0 CLB: CARRY_GPROP bit 0 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1
xc4000e CLB_S rect MAIN_S
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B12 - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_S rect MAIN_W
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_F1 bit 0 INT: mux CELL.IMUX_CLB_G3 bit 0
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_S rect MAIN_N
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_S rect MAIN_E
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLB_SW

Cells: 3

Switchbox INT

xc4000e CLB_SW switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[21][11]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[25][11]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[33][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[35][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[27][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[33][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[29][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[29][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[26][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[30][8]
xc4000e CLB_SW switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[14][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y!MAIN[2][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ!MAIN[6][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[11][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[13][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[28][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y!MAIN[1][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[22][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ!MAIN[0][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[13][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[29][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[12][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[27][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[35][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[34][7]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[21][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ!MAIN[23][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[23][11]
CELL.SINGLE_V[1]CELL.OUT_CLB_X!MAIN[24][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[29][11]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[25][4]
CELL.SINGLE_V[3]CELL.LONG_H[2]!MAIN_S[28][12]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[30][4]
CELL.SINGLE_V[4]CELL.LONG_H[3]!MAIN[21][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ!MAIN[34][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[35][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X!MAIN[31][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[35][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[34][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[21][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[33][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[13][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y!MAIN[10][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ!MAIN[15][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[21][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X!MAIN[32][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ!MAIN[35][4]
xc4000e CLB_SW switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[23][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[25][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[24][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[24][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[26][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[28][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[26][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[23][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[25][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[31][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[34][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[30][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[30][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[31][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[32][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[30][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[31][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[31][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[33][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[30][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[32][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[21][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[23][5]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[25][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[26][5]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[26][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[27][9]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[27][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[28][7]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[34][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[32][6]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[31][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[29][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[32][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[34][9]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[24][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[26][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[25][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[31][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[24][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[22][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[23][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[27][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[28][3]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[24][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[24][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[28][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[29][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
xc4000e CLB_SW switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[26][2]MAIN[28][0]MAIN[27][1]MAIN[26][0]MAIN[27][3]MAIN[26][1]MAIN[27][0]MAIN[27][2]MAIN_W[7][3]CELL.IMUX_CLB_F1
Source
001001111CELL.SINGLE_V[3]
001010111CELL.LONG_V[4]
001011101CELL.SINGLE_V[7]
001111111CELL.SINGLE_V[0]
010001111CELL.LONG_V[3]
010010111CELL.DOUBLE_V0[1]
010011101CELL.LONG_V[0]
010111111CELL.SINGLE_V[1]
011001011CELL.SINGLE_V[5]
011010011CELL.LONG_V[1]
011011001CELL.SINGLE_V[6]
011011110CELL.GCLK[1]
011111011CELL.DOUBLE_V1[1]
111001111CELL.DOUBLE_V1[0]
111010111CELL.SINGLE_V[4]
111011101CELL.DOUBLE_V0[0]
111111111CELL.SINGLE_V[2]
xc4000e CLB_SW switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[10][9]MAIN[10][7]MAIN[11][6]MAIN[11][8]MAIN[11][9]MAIN[12][8]MAIN[12][7]MAIN[12][6]CELL.IMUX_CLB_F2
Source
00110011CELL.SINGLE_H[5]
00110101CELL.LONG_H[5]
00110110CELL.DOUBLE_H1[1]
00111111CELL.SINGLE_H[0]
01010011CELL.SINGLE_H[4]
01010101CELL.DOUBLE_H0[1]
01010110CELL.LONG_H[4]
01011111CELL.SINGLE_H[1]
01100011CELL.SINGLE_H[6]
01100101CELL_N.LONG_H[2]
01100110CELL_N.LONG_H[0]
01101111CELL.SINGLE_H[3]
11110011CELL.DOUBLE_H0[0]
11110101CELL.SINGLE_H[7]
11110110CELL.DOUBLE_H1[0]
11111111CELL.SINGLE_H[2]
xc4000e CLB_SW switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[33][2]MAIN[35][0]MAIN[34][2]MAIN[35][1]MAIN[33][0]MAIN[34][1]MAIN[35][2]MAIN[34][0]MAIN[35][3]CELL.IMUX_CLB_F3
Source
000011111CELL.SINGLE_V[0]
000111011CELL.DOUBLE_V0[0]
000111101CELL.LONG_V[2]
001111111CELL.SINGLE_V[3]
010001111CELL.DOUBLE_V1[1]
010010111CELL.LONG_V[1]
010101011CELL.DOUBLE_V0[1]
010101101CELL.LONG_V[5]
010110011CELL.SINGLE_V[4]
010110101CELL.LONG_V[4]
010111110CELL.GCLK[0]
011101111CELL.SINGLE_V[1]
011110111CELL.SINGLE_V[2]
110011111CELL.SINGLE_V[6]
110111011CELL.DOUBLE_V1[0]
110111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[7]
xc4000e CLB_SW switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[9][7]MAIN[8][6]MAIN[9][6]MAIN[9][8]MAIN[8][7]MAIN[10][6]MAIN[8][9]MAIN[9][9]MAIN[10][8]CELL.IMUX_CLB_F4
Source
000111111CELL.SPECIAL_CLB_CIN
001001111CELL.SINGLE_H[0]
001011011CELL.DOUBLE_H1[0]
001011101CELL_N.LONG_H[0]
001100111CELL.LONG_H[5]
001101110CELL.LONG_H[3]
001110011CELL.SINGLE_H[2]
001110101CELL.SINGLE_H[3]
001111010CELL.SINGLE_H[7]
001111100CELL_N.LONG_H[1]
011011111CELL.SINGLE_H[1]
011110111CELL.DOUBLE_H1[1]
011111110CELL.DOUBLE_H0[1]
101101111CELL.SINGLE_H[5]
101111011CELL.DOUBLE_H0[0]
101111101CELL.SINGLE_H[6]
111111111CELL.SINGLE_H[4]
xc4000e CLB_SW switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[21][0]MAIN[21][3]MAIN[23][0]MAIN[23][1]MAIN[22][1]MAIN[21][1]MAIN[22][0]MAIN[21][2]MAIN[22][2]CELL.IMUX_CLB_G1
Source
000011111CELL.SINGLE_V[0]
000101111CELL.SINGLE_V[2]
000111011CELL.SINGLE_V[4]
001010111CELL.LONG_V[4]
001011101CELL.LONG_V[3]
001100111CELL.SINGLE_V[1]
001101101CELL.DOUBLE_V1[0]
001110011CELL.DOUBLE_V0[1]
001111001CELL.LONG_V[0]
001111110CELL.GCLK[1]
011011111CELL.SINGLE_V[3]
011101111CELL.DOUBLE_V0[0]
011111011CELL.SINGLE_V[7]
100111111CELL.DOUBLE_V1[1]
101110111CELL.LONG_V[1]
101111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[6]
xc4000e CLB_SW switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[2][7]MAIN[3][7]MAIN[3][9]MAIN[2][6]MAIN[3][8]MAIN[2][8]MAIN[2][9]MAIN[3][6]MAIN[4][8]CELL.IMUX_CLB_G2
Source
000111111CELL.SPECIAL_CLB_COUT0
001001111CELL.LONG_H[4]
001011101CELL.SINGLE_H[4]
001011110CELL.LONG_H[5]
001100111CELL.SINGLE_H[2]
001101011CELL.SINGLE_H[3]
001110101CELL.SINGLE_H[7]
001110110CELL.DOUBLE_H0[0]
001111001CELL_N.LONG_H[2]
001111010CELL.SINGLE_H[6]
011011111CELL.SINGLE_H[1]
011110111CELL_N.LONG_H[0]
011111011CELL.DOUBLE_H1[0]
101101111CELL.DOUBLE_H1[1]
101111101CELL.SINGLE_H[5]
101111110CELL.DOUBLE_H0[1]
111111111CELL.SINGLE_H[0]
xc4000e CLB_SW switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[29][0]MAIN[28][2]MAIN[28][1]MAIN[29][2]MAIN[30][0]MAIN[29][1]MAIN[30][2]MAIN[30][3]MAIN_W[8][2]CELL.IMUX_CLB_G3
Source
000011111CELL.SINGLE_V[0]
000101111CELL.SINGLE_V[2]
000111011CELL.SINGLE_V[4]
001010111CELL.LONG_V[4]
001011101CELL.LONG_V[2]
001100111CELL.SINGLE_V[1]
001101101CELL.SINGLE_V[6]
001110011CELL.DOUBLE_V0[1]
001111001CELL.LONG_V[5]
001111110CELL.GCLK[0]
011011111CELL.DOUBLE_V0[0]
011101111CELL.SINGLE_V[5]
011111011CELL.DOUBLE_V1[0]
100111111CELL.DOUBLE_V1[1]
101110111CELL.LONG_V[1]
101111101CELL.SINGLE_V[7]
111111111CELL.SINGLE_V[3]
xc4000e CLB_SW switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[5][9]MAIN[4][9]MAIN[6][8]MAIN[4][6]MAIN[4][7]MAIN[5][7]MAIN[5][8]MAIN[5][6]CELL.IMUX_CLB_G4
Source
00001111CELL.SINGLE_H[0]
00010111CELL.SINGLE_H[1]
00011101CELL_N.LONG_H[0]
00101011CELL.DOUBLE_H1[1]
00101110CELL.LONG_H[3]
00110011CELL.LONG_H[5]
00110110CELL.DOUBLE_H0[1]
00111001CELL.SINGLE_H[3]
00111100CELL.SINGLE_H[6]
01011111CELL.DOUBLE_H1[0]
01111011CELL.SINGLE_H[2]
01111110CELL.DOUBLE_H0[0]
10101111CELL.SINGLE_H[5]
10110111CELL.SINGLE_H[4]
10111101CELL_N.LONG_H[1]
11111111CELL.SINGLE_H[7]
xc4000e CLB_SW switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[23][3]MAIN[23][2]MAIN[25][1]MAIN[24][0]MAIN[24][1]MAIN[25][2]MAIN[24][2]MAIN[25][0]CELL.IMUX_CLB_C1
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[1]
00011110CELL.GCLK[3]
00101011CELL.DOUBLE_V0[0]
00101101CELL.DOUBLE_V1[0]
00110011CELL.SINGLE_V[3]
00110101CELL.SINGLE_V[7]
00111010CELL.LONG_V[2]
00111100CELL.LONG_V[3]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[2]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB_SW switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[0][7]MAIN[0][6]MAIN[1][7]MAIN[1][9]MAIN[0][8]MAIN[0][9]MAIN[1][6]MAIN[1][8]CELL.IMUX_CLB_C2
Source
00001111CELL.LONG_H[4]
00011101CELL.SINGLE_H[5]
00011110CELL.LONG_H[3]
00111111CELL.SINGLE_H[0]
01000111CELL.SINGLE_H[2]
01001011CELL.SINGLE_H[3]
01010101CELL.SINGLE_H[7]
01010110CELL.DOUBLE_H0[0]
01011001CELL_N.LONG_H[1]
01011010CELL.SINGLE_H[6]
01110111CELL.DOUBLE_H1[0]
01111011CELL_N.LONG_H[2]
11001111CELL.DOUBLE_H1[1]
11011101CELL.SINGLE_H[4]
11011110CELL.DOUBLE_H0[1]
11111111CELL.SINGLE_H[1]
xc4000e CLB_SW switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[31][0]MAIN[31][1]MAIN[32][1]MAIN[32][0]MAIN[31][2]MAIN[32][2]MAIN[32][3]MAIN[33][1]CELL.IMUX_CLB_C3
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[2]
00011110CELL.GCLK[2]
00101011CELL.SINGLE_V[3]
00101101CELL.SINGLE_V[7]
00110011CELL.DOUBLE_V0[0]
00110101CELL.DOUBLE_V1[0]
00111010CELL.LONG_V[3]
00111100CELL.LONG_V[2]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[1]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB_SW switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[7][7]MAIN[8][8]MAIN[6][7]MAIN[6][6]MAIN[7][9]MAIN[7][8]MAIN[6][9]MAIN[7][6]CELL.IMUX_CLB_C4
Source
00001111CELL.SINGLE_H[1]
00011011CELL.DOUBLE_H0[0]
00011101CELL.SINGLE_H[6]
00111111CELL.SINGLE_H[0]
01000111CELL.LONG_H[4]
01001110CELL.LONG_H[3]
01010011CELL.SINGLE_H[2]
01010101CELL.SINGLE_H[3]
01011010CELL.DOUBLE_H1[0]
01011100CELL_N.LONG_H[1]
01110111CELL.DOUBLE_H1[1]
01111110CELL.DOUBLE_H0[1]
11001111CELL.SINGLE_H[4]
11011011CELL.SINGLE_H[7]
11011101CELL_N.LONG_H[2]
11111111CELL.SINGLE_H[5]
xc4000e CLB_SW switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[14][4]MAIN[20][4]MAIN[19][5]MAIN[17][5]MAIN[20][5]MAIN[19][4]MAIN[18][5]MAIN[18][4]CELL.IMUX_CLB_K
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[3]
01101111CELL.SINGLE_V[6]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[5]
xc4000e CLB_SW switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[20][6]MAIN[16][6]MAIN[19][6]MAIN[17][6]MAIN[18][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB_SW switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[20][7]MAIN[16][7]MAIN[19][7]MAIN[17][7]MAIN[18][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB_SW switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[16][8]MAIN[18][8]MAIN[19][8]MAIN[17][8]MAIN[20][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000e CLB_SW switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[16][9]MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000e CLB_SW bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000e CLB_SW bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[19][0]
F bit 1!MAIN[15][0]
F bit 2!MAIN[20][0]
F bit 3!MAIN[16][0]
F bit 4!MAIN[20][2]
F bit 5!MAIN[16][2]
F bit 6!MAIN[19][2]
F bit 7!MAIN[15][2]
F bit 8!MAIN[17][0]
F bit 9!MAIN[13][0]
F bit 10!MAIN[18][0]
F bit 11!MAIN[14][0]
F bit 12!MAIN[18][2]
F bit 13!MAIN[14][2]
F bit 14!MAIN[17][2]
F bit 15!MAIN[13][2]
G bit 0!MAIN[1][2]
G bit 1!MAIN[0][0]
G bit 2!MAIN[3][2]
G bit 3!MAIN[2][0]
G bit 4!MAIN[5][2]
G bit 5!MAIN[4][0]
G bit 6!MAIN[7][2]
G bit 7!MAIN[6][0]
G bit 8!MAIN[0][2]
G bit 9!MAIN[1][0]
G bit 10!MAIN[2][2]
G bit 11!MAIN[3][0]
G bit 12!MAIN[4][2]
G bit 13!MAIN[5][0]
G bit 14!MAIN[6][2]
G bit 15!MAIN[7][0]
H bit 0!MAIN[6][3]
H bit 1!MAIN[7][3]
H bit 2!MAIN[5][3]
H bit 3!MAIN[4][3]
H bit 4!MAIN[9][3]
H bit 5!MAIN[8][3]
H bit 6!MAIN[10][3]
H bit 7!MAIN[13][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[11][4]
FFY_SRVAL bit 0!MAIN[9][5]
FFX_EC_ENABLE!MAIN[13][5]
FFY_EC_ENABLE!MAIN[7][5]
FFX_SR_ENABLE!MAIN[11][5]
FFY_SR_ENABLE!MAIN[8][5]
FFX_CLK_INV!MAIN[16][5]
FFY_CLK_INV!MAIN[15][5]
MUX_CIN[enum: CLB_MUX_CIN]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[11][3]
READBACK_X bit 0!MAIN[16][4]
READBACK_Y bit 0!MAIN[3][5]
READBACK_XQ bit 0!MAIN[12][5]
READBACK_YQ bit 0!MAIN[8][4]
F_RAM_ENABLE!MAIN[12][2]
G_RAM_ENABLE!MAIN[8][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[2][1]
RAM_SYNC_ENABLE!MAIN[6][1]
RAM_CLK_INV!MAIN[5][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
xc4000e CLB_SW enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[13][4]MAIN[16][3]MAIN[15][3]MAIN[15][4]
C11111
C20011
C30101
C40110
xc4000e CLB_SW enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[17][3]MAIN[19][3]MAIN[18][3]MAIN[17][4]
C10011
C21111
C30101
C40110
xc4000e CLB_SW enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[2][3]MAIN[3][4]MAIN[3][3]MAIN[4][4]
C10011
C20101
C31111
C40110
xc4000e CLB_SW enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[0][4]MAIN[1][4]MAIN[2][4]MAIN[1][3]
C10011
C20101
C30110
C41111
xc4000e CLB_SW enum CLB_MUX_X
CLB.MUX_XMAIN[14][3]
F0
H1
xc4000e CLB_SW enum CLB_MUX_Y
CLB.MUX_YMAIN[5][4]
G0
H1
xc4000e CLB_SW enum CLB_MUX_XQ
CLB.MUX_XQMAIN[20][3]
DIN0
FFX1
xc4000e CLB_SW enum CLB_MUX_YQ
CLB.MUX_YQMAIN[0][3]
EC0
FFY1
xc4000e CLB_SW enum CLB_MUX_D
CLB.MUX_DXMAIN[9][4]MAIN[14][6]MAIN[10][4]MAIN[12][4]
CLB.MUX_DYMAIN[4][5]MAIN[5][5]MAIN[7][4]MAIN[6][4]
F1111
G0011
H0101
DIN0110
xc4000e CLB_SW enum CLB_MUX_CIN
CLB.MUX_CINMAIN[9][0]
COUT_S1
COUT_N0
xc4000e CLB_SW enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[11][2]MAIN[12][0]
ADD01
SUB11
ADDSUB10
xc4000e CLB_SW enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[12][3]MAIN[9][2]
CONST_011
CONST_110
XOR01
xc4000e CLB_SW enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[10][0]MAIN[11][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000e CLB_SW enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[8][0]
CONST_11
XOR0
xc4000e CLB_SW enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[10][2]
_32X11
_16X20
xc4000e CLB_SW enum CLB_MUX_H0
CLB.MUX_H0MAIN[3][1]
G1
SR0
xc4000e CLB_SW enum CLB_MUX_H2
CLB.MUX_H2MAIN[7][1]
F1
DIN0

Bels TBUF

xc4000e CLB_SW bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000e CLB_SW bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[22][4]!MAIN[22][6]

Bel wires

xc4000e CLB_SW bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000e CLB_SW rect MAIN
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 2
B8 - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 2 INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 3
B7 INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7
B6 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 6
B5 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 3 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_K bit 4 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE CLB: ! READBACK_XQ bit 0 CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 CLB: ! READBACK_Y bit 0 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ
B4 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 CLB: MUX_DIN bit 0 CLB: ! READBACK_X bit 0 CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 7 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 CLB: ! READBACK_YQ bit 0 CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3
B3 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 1 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 1 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 4 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 7 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 7 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0
B2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_G1 bit 1 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 CLB: ! G bit 8
B1 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 6 - INT: mux CELL.IMUX_CLB_G3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 3 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 3 - - - - - - - - - - - - - CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV - CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE - -
B0 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 8 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: MUX_CIN bit 0 CLB: CARRY_GPROP bit 0 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1
xc4000e CLB_SW rect MAIN_S
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B12 - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_SW rect MAIN_W
BitFrame
F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_F1 bit 0 - - - - - - -
B2 - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_G3 bit 0 - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_SW rect MAIN_N
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_SW rect MAIN_E
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLB_SE

Cells: 3

Switchbox INT

xc4000e CLB_SE switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[21][11]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[25][11]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[33][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[35][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[27][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[33][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[29][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[29][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[26][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[30][8]
xc4000e CLB_SE switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[14][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y!MAIN[2][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ!MAIN[6][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[11][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[13][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[28][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y!MAIN[1][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[22][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ!MAIN[0][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[13][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[29][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[12][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[27][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[35][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[34][7]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[21][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ!MAIN[23][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[23][11]
CELL.SINGLE_V[1]CELL.OUT_CLB_X!MAIN[24][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[29][11]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[25][4]
CELL.SINGLE_V[3]CELL.LONG_H[2]!MAIN_S[28][12]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[30][4]
CELL.SINGLE_V[4]CELL.LONG_H[3]!MAIN[21][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ!MAIN[34][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[35][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X!MAIN[31][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[35][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[34][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[21][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[33][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[13][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y!MAIN[10][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ!MAIN[15][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[21][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X!MAIN[32][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ!MAIN[35][4]
xc4000e CLB_SE switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[23][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[25][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[24][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[24][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[26][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[28][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[26][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[23][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[25][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[31][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[34][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[30][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[30][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[31][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[32][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[30][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[31][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[31][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[33][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[30][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[32][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[21][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[23][5]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[25][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[26][5]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[26][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[27][9]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[27][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[28][7]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[34][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[32][6]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[31][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[29][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[32][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[34][9]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[24][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[26][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[25][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[31][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[24][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[22][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[23][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[27][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[28][3]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[24][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[24][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[28][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[29][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
xc4000e CLB_SE switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[26][2]MAIN[28][0]MAIN[27][1]MAIN[26][0]MAIN[27][3]MAIN[26][1]MAIN[27][0]MAIN[27][2]MAIN_W[1][1]CELL.IMUX_CLB_F1
Source
001001111CELL.SINGLE_V[3]
001010111CELL.LONG_V[4]
001011101CELL.SINGLE_V[7]
001111111CELL.SINGLE_V[0]
010001111CELL.LONG_V[3]
010010111CELL.DOUBLE_V0[1]
010011101CELL.LONG_V[0]
010111111CELL.SINGLE_V[1]
011001011CELL.SINGLE_V[5]
011010011CELL.LONG_V[1]
011011001CELL.SINGLE_V[6]
011011110CELL.GCLK[1]
011111011CELL.DOUBLE_V1[1]
111001111CELL.DOUBLE_V1[0]
111010111CELL.SINGLE_V[4]
111011101CELL.DOUBLE_V0[0]
111111111CELL.SINGLE_V[2]
xc4000e CLB_SE switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[10][9]MAIN[10][7]MAIN[11][6]MAIN[11][8]MAIN[11][9]MAIN[12][8]MAIN[12][7]MAIN[12][6]CELL.IMUX_CLB_F2
Source
00110011CELL.SINGLE_H[5]
00110101CELL.LONG_H[5]
00110110CELL.DOUBLE_H1[1]
00111111CELL.SINGLE_H[0]
01010011CELL.SINGLE_H[4]
01010101CELL.DOUBLE_H0[1]
01010110CELL.LONG_H[4]
01011111CELL.SINGLE_H[1]
01100011CELL.SINGLE_H[6]
01100101CELL_N.LONG_H[2]
01100110CELL_N.LONG_H[0]
01101111CELL.SINGLE_H[3]
11110011CELL.DOUBLE_H0[0]
11110101CELL.SINGLE_H[7]
11110110CELL.DOUBLE_H1[0]
11111111CELL.SINGLE_H[2]
xc4000e CLB_SE switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[33][2]MAIN[35][0]MAIN[34][2]MAIN[35][1]MAIN[33][0]MAIN[34][1]MAIN[35][2]MAIN[34][0]MAIN[35][3]CELL.IMUX_CLB_F3
Source
000011111CELL.SINGLE_V[0]
000111011CELL.DOUBLE_V0[0]
000111101CELL.LONG_V[2]
001111111CELL.SINGLE_V[3]
010001111CELL.DOUBLE_V1[1]
010010111CELL.LONG_V[1]
010101011CELL.DOUBLE_V0[1]
010101101CELL.LONG_V[5]
010110011CELL.SINGLE_V[4]
010110101CELL.LONG_V[4]
010111110CELL.GCLK[0]
011101111CELL.SINGLE_V[1]
011110111CELL.SINGLE_V[2]
110011111CELL.SINGLE_V[6]
110111011CELL.DOUBLE_V1[0]
110111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[7]
xc4000e CLB_SE switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[9][7]MAIN[8][6]MAIN[9][6]MAIN[9][8]MAIN[8][7]MAIN[10][6]MAIN[8][9]MAIN[9][9]MAIN[10][8]CELL.IMUX_CLB_F4
Source
000111111CELL.SPECIAL_CLB_CIN
001001111CELL.SINGLE_H[0]
001011011CELL.DOUBLE_H1[0]
001011101CELL_N.LONG_H[0]
001100111CELL.LONG_H[5]
001101110CELL.LONG_H[3]
001110011CELL.SINGLE_H[2]
001110101CELL.SINGLE_H[3]
001111010CELL.SINGLE_H[7]
001111100CELL_N.LONG_H[1]
011011111CELL.SINGLE_H[1]
011110111CELL.DOUBLE_H1[1]
011111110CELL.DOUBLE_H0[1]
101101111CELL.SINGLE_H[5]
101111011CELL.DOUBLE_H0[0]
101111101CELL.SINGLE_H[6]
111111111CELL.SINGLE_H[4]
xc4000e CLB_SE switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[21][0]MAIN[21][3]MAIN[23][0]MAIN[23][1]MAIN[22][1]MAIN[21][1]MAIN[22][0]MAIN[21][2]MAIN[22][2]CELL.IMUX_CLB_G1
Source
000011111CELL.SINGLE_V[0]
000101111CELL.SINGLE_V[2]
000111011CELL.SINGLE_V[4]
001010111CELL.LONG_V[4]
001011101CELL.LONG_V[3]
001100111CELL.SINGLE_V[1]
001101101CELL.DOUBLE_V1[0]
001110011CELL.DOUBLE_V0[1]
001111001CELL.LONG_V[0]
001111110CELL.GCLK[1]
011011111CELL.SINGLE_V[3]
011101111CELL.DOUBLE_V0[0]
011111011CELL.SINGLE_V[7]
100111111CELL.DOUBLE_V1[1]
101110111CELL.LONG_V[1]
101111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[6]
xc4000e CLB_SE switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[2][7]MAIN[3][7]MAIN[3][9]MAIN[2][6]MAIN[3][8]MAIN[2][8]MAIN[2][9]MAIN[3][6]MAIN[4][8]CELL.IMUX_CLB_G2
Source
000111111CELL.SPECIAL_CLB_COUT0
001001111CELL.LONG_H[4]
001011101CELL.SINGLE_H[4]
001011110CELL.LONG_H[5]
001100111CELL.SINGLE_H[2]
001101011CELL.SINGLE_H[3]
001110101CELL.SINGLE_H[7]
001110110CELL.DOUBLE_H0[0]
001111001CELL_N.LONG_H[2]
001111010CELL.SINGLE_H[6]
011011111CELL.SINGLE_H[1]
011110111CELL_N.LONG_H[0]
011111011CELL.DOUBLE_H1[0]
101101111CELL.DOUBLE_H1[1]
101111101CELL.SINGLE_H[5]
101111110CELL.DOUBLE_H0[1]
111111111CELL.SINGLE_H[0]
xc4000e CLB_SE switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[29][0]MAIN[28][2]MAIN[30][1]MAIN[28][1]MAIN[29][2]MAIN[30][0]MAIN[29][1]MAIN[30][2]MAIN[30][3]MAIN_W[0][1]CELL.IMUX_CLB_G3
Source
0001111111CELL.SPECIAL_CLB_CIN
0010011111CELL.SINGLE_V[0]
0010101111CELL.SINGLE_V[2]
0010111011CELL.SINGLE_V[4]
0011010111CELL.LONG_V[4]
0011011101CELL.LONG_V[2]
0011100111CELL.SINGLE_V[1]
0011101101CELL.SINGLE_V[6]
0011110011CELL.DOUBLE_V0[1]
0011111001CELL.LONG_V[5]
0011111110CELL.GCLK[0]
0111011111CELL.DOUBLE_V0[0]
0111101111CELL.SINGLE_V[5]
0111111011CELL.DOUBLE_V1[0]
1010111111CELL.DOUBLE_V1[1]
1011110111CELL.LONG_V[1]
1011111101CELL.SINGLE_V[7]
1111111111CELL.SINGLE_V[3]
xc4000e CLB_SE switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[5][9]MAIN[4][9]MAIN[6][8]MAIN[4][6]MAIN[4][7]MAIN[5][7]MAIN[5][8]MAIN[5][6]CELL.IMUX_CLB_G4
Source
00001111CELL.SINGLE_H[0]
00010111CELL.SINGLE_H[1]
00011101CELL_N.LONG_H[0]
00101011CELL.DOUBLE_H1[1]
00101110CELL.LONG_H[3]
00110011CELL.LONG_H[5]
00110110CELL.DOUBLE_H0[1]
00111001CELL.SINGLE_H[3]
00111100CELL.SINGLE_H[6]
01011111CELL.DOUBLE_H1[0]
01111011CELL.SINGLE_H[2]
01111110CELL.DOUBLE_H0[0]
10101111CELL.SINGLE_H[5]
10110111CELL.SINGLE_H[4]
10111101CELL_N.LONG_H[1]
11111111CELL.SINGLE_H[7]
xc4000e CLB_SE switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[23][3]MAIN[23][2]MAIN[25][1]MAIN[24][0]MAIN[24][1]MAIN[25][2]MAIN[24][2]MAIN[25][0]CELL.IMUX_CLB_C1
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[1]
00011110CELL.GCLK[3]
00101011CELL.DOUBLE_V0[0]
00101101CELL.DOUBLE_V1[0]
00110011CELL.SINGLE_V[3]
00110101CELL.SINGLE_V[7]
00111010CELL.LONG_V[2]
00111100CELL.LONG_V[3]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[2]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB_SE switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[0][7]MAIN[0][6]MAIN[1][7]MAIN[1][9]MAIN[0][8]MAIN[0][9]MAIN[1][6]MAIN[1][8]CELL.IMUX_CLB_C2
Source
00001111CELL.LONG_H[4]
00011101CELL.SINGLE_H[5]
00011110CELL.LONG_H[3]
00111111CELL.SINGLE_H[0]
01000111CELL.SINGLE_H[2]
01001011CELL.SINGLE_H[3]
01010101CELL.SINGLE_H[7]
01010110CELL.DOUBLE_H0[0]
01011001CELL_N.LONG_H[1]
01011010CELL.SINGLE_H[6]
01110111CELL.DOUBLE_H1[0]
01111011CELL_N.LONG_H[2]
11001111CELL.DOUBLE_H1[1]
11011101CELL.SINGLE_H[4]
11011110CELL.DOUBLE_H0[1]
11111111CELL.SINGLE_H[1]
xc4000e CLB_SE switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[31][0]MAIN[31][1]MAIN[32][1]MAIN[32][0]MAIN[31][2]MAIN[32][2]MAIN[32][3]MAIN[33][1]CELL.IMUX_CLB_C3
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[2]
00011110CELL.GCLK[2]
00101011CELL.SINGLE_V[3]
00101101CELL.SINGLE_V[7]
00110011CELL.DOUBLE_V0[0]
00110101CELL.DOUBLE_V1[0]
00111010CELL.LONG_V[3]
00111100CELL.LONG_V[2]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[1]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB_SE switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[7][7]MAIN[8][8]MAIN[6][7]MAIN[6][6]MAIN[7][9]MAIN[7][8]MAIN[6][9]MAIN[7][6]CELL.IMUX_CLB_C4
Source
00001111CELL.SINGLE_H[1]
00011011CELL.DOUBLE_H0[0]
00011101CELL.SINGLE_H[6]
00111111CELL.SINGLE_H[0]
01000111CELL.LONG_H[4]
01001110CELL.LONG_H[3]
01010011CELL.SINGLE_H[2]
01010101CELL.SINGLE_H[3]
01011010CELL.DOUBLE_H1[0]
01011100CELL_N.LONG_H[1]
01110111CELL.DOUBLE_H1[1]
01111110CELL.DOUBLE_H0[1]
11001111CELL.SINGLE_H[4]
11011011CELL.SINGLE_H[7]
11011101CELL_N.LONG_H[2]
11111111CELL.SINGLE_H[5]
xc4000e CLB_SE switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[14][4]MAIN[20][4]MAIN[19][5]MAIN[17][5]MAIN[20][5]MAIN[19][4]MAIN[18][5]MAIN[18][4]CELL.IMUX_CLB_K
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[3]
01101111CELL.SINGLE_V[6]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[5]
xc4000e CLB_SE switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[20][6]MAIN[16][6]MAIN[19][6]MAIN[17][6]MAIN[18][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB_SE switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[20][7]MAIN[16][7]MAIN[19][7]MAIN[17][7]MAIN[18][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB_SE switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[16][8]MAIN[18][8]MAIN[19][8]MAIN[17][8]MAIN[20][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000e CLB_SE switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[16][9]MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000e CLB_SE bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000e CLB_SE bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[19][0]
F bit 1!MAIN[15][0]
F bit 2!MAIN[20][0]
F bit 3!MAIN[16][0]
F bit 4!MAIN[20][2]
F bit 5!MAIN[16][2]
F bit 6!MAIN[19][2]
F bit 7!MAIN[15][2]
F bit 8!MAIN[17][0]
F bit 9!MAIN[13][0]
F bit 10!MAIN[18][0]
F bit 11!MAIN[14][0]
F bit 12!MAIN[18][2]
F bit 13!MAIN[14][2]
F bit 14!MAIN[17][2]
F bit 15!MAIN[13][2]
G bit 0!MAIN[1][2]
G bit 1!MAIN[0][0]
G bit 2!MAIN[3][2]
G bit 3!MAIN[2][0]
G bit 4!MAIN[5][2]
G bit 5!MAIN[4][0]
G bit 6!MAIN[7][2]
G bit 7!MAIN[6][0]
G bit 8!MAIN[0][2]
G bit 9!MAIN[1][0]
G bit 10!MAIN[2][2]
G bit 11!MAIN[3][0]
G bit 12!MAIN[4][2]
G bit 13!MAIN[5][0]
G bit 14!MAIN[6][2]
G bit 15!MAIN[7][0]
H bit 0!MAIN[6][3]
H bit 1!MAIN[7][3]
H bit 2!MAIN[5][3]
H bit 3!MAIN[4][3]
H bit 4!MAIN[9][3]
H bit 5!MAIN[8][3]
H bit 6!MAIN[10][3]
H bit 7!MAIN[13][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[11][4]
FFY_SRVAL bit 0!MAIN[9][5]
FFX_EC_ENABLE!MAIN[13][5]
FFY_EC_ENABLE!MAIN[7][5]
FFX_SR_ENABLE!MAIN[11][5]
FFY_SR_ENABLE!MAIN[8][5]
FFX_CLK_INV!MAIN[16][5]
FFY_CLK_INV!MAIN[15][5]
MUX_CIN[enum: CLB_MUX_CIN]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[11][3]
READBACK_X bit 0!MAIN[16][4]
READBACK_Y bit 0!MAIN[3][5]
READBACK_XQ bit 0!MAIN[12][5]
READBACK_YQ bit 0!MAIN[8][4]
F_RAM_ENABLE!MAIN[12][2]
G_RAM_ENABLE!MAIN[8][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[2][1]
RAM_SYNC_ENABLE!MAIN[6][1]
RAM_CLK_INV!MAIN[5][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
xc4000e CLB_SE enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[13][4]MAIN[16][3]MAIN[15][3]MAIN[15][4]
C11111
C20011
C30101
C40110
xc4000e CLB_SE enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[17][3]MAIN[19][3]MAIN[18][3]MAIN[17][4]
C10011
C21111
C30101
C40110
xc4000e CLB_SE enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[2][3]MAIN[3][4]MAIN[3][3]MAIN[4][4]
C10011
C20101
C31111
C40110
xc4000e CLB_SE enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[0][4]MAIN[1][4]MAIN[2][4]MAIN[1][3]
C10011
C20101
C30110
C41111
xc4000e CLB_SE enum CLB_MUX_X
CLB.MUX_XMAIN[14][3]
F0
H1
xc4000e CLB_SE enum CLB_MUX_Y
CLB.MUX_YMAIN[5][4]
G0
H1
xc4000e CLB_SE enum CLB_MUX_XQ
CLB.MUX_XQMAIN[20][3]
DIN0
FFX1
xc4000e CLB_SE enum CLB_MUX_YQ
CLB.MUX_YQMAIN[0][3]
EC0
FFY1
xc4000e CLB_SE enum CLB_MUX_D
CLB.MUX_DXMAIN[9][4]MAIN[14][6]MAIN[10][4]MAIN[12][4]
CLB.MUX_DYMAIN[4][5]MAIN[5][5]MAIN[7][4]MAIN[6][4]
F1111
G0011
H0101
DIN0110
xc4000e CLB_SE enum CLB_MUX_CIN
CLB.MUX_CINMAIN[9][0]
COUT_S1
COUT_N0
xc4000e CLB_SE enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[11][2]MAIN[12][0]
ADD01
SUB11
ADDSUB10
xc4000e CLB_SE enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[12][3]MAIN[9][2]
CONST_011
CONST_110
XOR01
xc4000e CLB_SE enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[10][0]MAIN[11][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000e CLB_SE enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[8][0]
CONST_11
XOR0
xc4000e CLB_SE enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[10][2]
_32X11
_16X20
xc4000e CLB_SE enum CLB_MUX_H0
CLB.MUX_H0MAIN[3][1]
G1
SR0
xc4000e CLB_SE enum CLB_MUX_H2
CLB.MUX_H2MAIN[7][1]
F1
DIN0

Bels TBUF

xc4000e CLB_SE bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000e CLB_SE bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[22][4]!MAIN[22][6]

Bel wires

xc4000e CLB_SE bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000e CLB_SE rect MAIN
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 2
B8 - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 2 INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 3
B7 INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_G2 bit 8 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7
B6 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 6
B5 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 3 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_K bit 4 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE CLB: ! READBACK_XQ bit 0 CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 CLB: ! READBACK_Y bit 0 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ
B4 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 CLB: MUX_DIN bit 0 CLB: ! READBACK_X bit 0 CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 7 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 CLB: ! READBACK_YQ bit 0 CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3
B3 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 1 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 1 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 4 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 7 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 7 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0
B2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_G1 bit 1 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 CLB: ! G bit 8
B1 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 3 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 3 - - - - - - - - - - - - - CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV - CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE - -
B0 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 8 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: MUX_CIN bit 0 CLB: CARRY_GPROP bit 0 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1
xc4000e CLB_SE rect MAIN_S
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B12 - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_SE rect MAIN_W
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_F1 bit 0 INT: mux CELL.IMUX_CLB_G3 bit 0
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_SE rect MAIN_N
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_SE rect MAIN_E
BitFrame
F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLB_N

Cells: 3

Switchbox INT

xc4000e CLB_N switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[21][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[25][8]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[33][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[35][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[27][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[33][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[29][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[29][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[26][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[30][8]
xc4000e CLB_N switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[14][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y!MAIN[2][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ!MAIN[6][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[11][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[13][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[28][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y!MAIN[1][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[22][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ!MAIN[0][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[13][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[29][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[12][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[27][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[35][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[34][7]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[21][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ!MAIN[23][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[23][8]
CELL.SINGLE_V[1]CELL.OUT_CLB_X!MAIN[24][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[29][8]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[25][4]
CELL.SINGLE_V[3]CELL.LONG_H[2]!MAIN_S[28][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[30][4]
CELL.SINGLE_V[4]CELL.LONG_H[3]!MAIN[21][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ!MAIN[34][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[35][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X!MAIN[31][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[35][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[34][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[21][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[33][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[13][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y!MAIN[10][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ!MAIN[15][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[21][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X!MAIN[32][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ!MAIN[35][4]
xc4000e CLB_N switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[23][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[25][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[24][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[24][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[26][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[28][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[26][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[23][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[25][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[31][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[34][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[30][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[30][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[31][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[32][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[30][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[31][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[31][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[33][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[30][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[32][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[21][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[23][5]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[25][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[26][5]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[26][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[27][9]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[27][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[28][7]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[34][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[32][6]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[31][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[29][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[32][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[34][9]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[24][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[26][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[25][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[31][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[24][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[22][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[23][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[27][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[28][3]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[24][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[24][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[28][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[29][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
xc4000e CLB_N switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[26][2]MAIN[28][0]MAIN[27][1]MAIN[26][0]MAIN[27][3]MAIN[26][1]MAIN[27][0]MAIN[27][2]MAIN_W[1][1]CELL.IMUX_CLB_F1
Source
001001111CELL.SINGLE_V[3]
001010111CELL.LONG_V[4]
001011101CELL.SINGLE_V[7]
001111111CELL.SINGLE_V[0]
010001111CELL.LONG_V[3]
010010111CELL.DOUBLE_V0[1]
010011101CELL.LONG_V[0]
010111111CELL.SINGLE_V[1]
011001011CELL.SINGLE_V[5]
011010011CELL.LONG_V[1]
011011001CELL.SINGLE_V[6]
011011110CELL.GCLK[1]
011111011CELL.DOUBLE_V1[1]
111001111CELL.DOUBLE_V1[0]
111010111CELL.SINGLE_V[4]
111011101CELL.DOUBLE_V0[0]
111111111CELL.SINGLE_V[2]
xc4000e CLB_N switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[10][9]MAIN[10][7]MAIN[11][6]MAIN[11][8]MAIN[11][9]MAIN[12][8]MAIN[12][7]MAIN[12][6]CELL.IMUX_CLB_F2
Source
00110011CELL.SINGLE_H[5]
00110101CELL.LONG_H[5]
00110110CELL.DOUBLE_H1[1]
00111111CELL.SINGLE_H[0]
01010011CELL.SINGLE_H[4]
01010101CELL.DOUBLE_H0[1]
01010110CELL.LONG_H[4]
01011111CELL.SINGLE_H[1]
01100011CELL.SINGLE_H[6]
01100101CELL_N.LONG_H[2]
01100110CELL_N.LONG_H[0]
01101111CELL.SINGLE_H[3]
11110011CELL.DOUBLE_H0[0]
11110101CELL.SINGLE_H[7]
11110110CELL.DOUBLE_H1[0]
11111111CELL.SINGLE_H[2]
xc4000e CLB_N switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[33][2]MAIN[35][0]MAIN[34][2]MAIN[35][1]MAIN[33][0]MAIN[34][1]MAIN[35][2]MAIN[34][0]MAIN[35][3]CELL.IMUX_CLB_F3
Source
000011111CELL.SINGLE_V[0]
000111011CELL.DOUBLE_V0[0]
000111101CELL.LONG_V[2]
001111111CELL.SINGLE_V[3]
010001111CELL.DOUBLE_V1[1]
010010111CELL.LONG_V[1]
010101011CELL.DOUBLE_V0[1]
010101101CELL.LONG_V[5]
010110011CELL.SINGLE_V[4]
010110101CELL.LONG_V[4]
010111110CELL.GCLK[0]
011101111CELL.SINGLE_V[1]
011110111CELL.SINGLE_V[2]
110011111CELL.SINGLE_V[6]
110111011CELL.DOUBLE_V1[0]
110111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[7]
xc4000e CLB_N switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[9][7]MAIN[8][6]MAIN[9][6]MAIN[9][8]MAIN[8][7]MAIN[10][6]MAIN[8][9]MAIN[9][9]MAIN[10][8]CELL.IMUX_CLB_F4
Source
000111111CELL.SPECIAL_CLB_CIN
001001111CELL.SINGLE_H[0]
001011011CELL.DOUBLE_H1[0]
001011101CELL_N.LONG_H[0]
001100111CELL.LONG_H[5]
001101110CELL.LONG_H[3]
001110011CELL.SINGLE_H[2]
001110101CELL.SINGLE_H[3]
001111010CELL.SINGLE_H[7]
001111100CELL_N.LONG_H[1]
011011111CELL.SINGLE_H[1]
011110111CELL.DOUBLE_H1[1]
011111110CELL.DOUBLE_H0[1]
101101111CELL.SINGLE_H[5]
101111011CELL.DOUBLE_H0[0]
101111101CELL.SINGLE_H[6]
111111111CELL.SINGLE_H[4]
xc4000e CLB_N switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[21][0]MAIN[21][3]MAIN[23][0]MAIN[23][1]MAIN[22][1]MAIN[21][1]MAIN[22][0]MAIN[21][2]MAIN[22][2]CELL.IMUX_CLB_G1
Source
000011111CELL.SINGLE_V[0]
000101111CELL.SINGLE_V[2]
000111011CELL.SINGLE_V[4]
001010111CELL.LONG_V[4]
001011101CELL.LONG_V[3]
001100111CELL.SINGLE_V[1]
001101101CELL.DOUBLE_V1[0]
001110011CELL.DOUBLE_V0[1]
001111001CELL.LONG_V[0]
001111110CELL.GCLK[1]
011011111CELL.SINGLE_V[3]
011101111CELL.DOUBLE_V0[0]
011111011CELL.SINGLE_V[7]
100111111CELL.DOUBLE_V1[1]
101110111CELL.LONG_V[1]
101111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[6]
xc4000e CLB_N switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[2][7]MAIN[2][6]MAIN[3][7]MAIN[3][8]MAIN[2][8]MAIN[2][9]MAIN[3][6]MAIN[4][8]CELL.IMUX_CLB_G2
Source
00001111CELL.LONG_H[4]
00011101CELL.SINGLE_H[4]
00011110CELL.LONG_H[5]
00111111CELL.SINGLE_H[1]
01000111CELL.SINGLE_H[2]
01001011CELL.SINGLE_H[3]
01010101CELL.SINGLE_H[7]
01010110CELL.DOUBLE_H0[0]
01011001CELL_N.LONG_H[2]
01011010CELL.SINGLE_H[6]
01110111CELL_N.LONG_H[0]
01111011CELL.DOUBLE_H1[0]
11001111CELL.DOUBLE_H1[1]
11011101CELL.SINGLE_H[5]
11011110CELL.DOUBLE_H0[1]
11111111CELL.SINGLE_H[0]
xc4000e CLB_N switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[29][0]MAIN[28][2]MAIN[30][1]MAIN[28][1]MAIN[29][2]MAIN[30][0]MAIN[29][1]MAIN[30][2]MAIN[30][3]MAIN_W[0][1]CELL.IMUX_CLB_G3
Source
0001111111CELL.SPECIAL_CLB_CIN
0010011111CELL.SINGLE_V[0]
0010101111CELL.SINGLE_V[2]
0010111011CELL.SINGLE_V[4]
0011010111CELL.LONG_V[4]
0011011101CELL.LONG_V[2]
0011100111CELL.SINGLE_V[1]
0011101101CELL.SINGLE_V[6]
0011110011CELL.DOUBLE_V0[1]
0011111001CELL.LONG_V[5]
0011111110CELL.GCLK[0]
0111011111CELL.DOUBLE_V0[0]
0111101111CELL.SINGLE_V[5]
0111111011CELL.DOUBLE_V1[0]
1010111111CELL.DOUBLE_V1[1]
1011110111CELL.LONG_V[1]
1011111101CELL.SINGLE_V[7]
1111111111CELL.SINGLE_V[3]
xc4000e CLB_N switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[5][9]MAIN[4][9]MAIN[6][8]MAIN[4][6]MAIN[4][7]MAIN[5][7]MAIN[5][8]MAIN[5][6]CELL.IMUX_CLB_G4
Source
00001111CELL.SINGLE_H[0]
00010111CELL.SINGLE_H[1]
00011101CELL_N.LONG_H[0]
00101011CELL.DOUBLE_H1[1]
00101110CELL.LONG_H[3]
00110011CELL.LONG_H[5]
00110110CELL.DOUBLE_H0[1]
00111001CELL.SINGLE_H[3]
00111100CELL.SINGLE_H[6]
01011111CELL.DOUBLE_H1[0]
01111011CELL.SINGLE_H[2]
01111110CELL.DOUBLE_H0[0]
10101111CELL.SINGLE_H[5]
10110111CELL.SINGLE_H[4]
10111101CELL_N.LONG_H[1]
11111111CELL.SINGLE_H[7]
xc4000e CLB_N switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[23][3]MAIN[23][2]MAIN[25][1]MAIN[24][0]MAIN[24][1]MAIN[25][2]MAIN[24][2]MAIN[25][0]CELL.IMUX_CLB_C1
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[1]
00011110CELL.GCLK[3]
00101011CELL.DOUBLE_V0[0]
00101101CELL.DOUBLE_V1[0]
00110011CELL.SINGLE_V[3]
00110101CELL.SINGLE_V[7]
00111010CELL.LONG_V[2]
00111100CELL.LONG_V[3]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[2]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB_N switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[0][7]MAIN[0][6]MAIN[1][7]MAIN[1][9]MAIN[0][8]MAIN[0][9]MAIN[1][6]MAIN[1][8]CELL.IMUX_CLB_C2
Source
00001111CELL.LONG_H[4]
00011101CELL.SINGLE_H[5]
00011110CELL.LONG_H[3]
00111111CELL.SINGLE_H[0]
01000111CELL.SINGLE_H[2]
01001011CELL.SINGLE_H[3]
01010101CELL.SINGLE_H[7]
01010110CELL.DOUBLE_H0[0]
01011001CELL_N.LONG_H[1]
01011010CELL.SINGLE_H[6]
01110111CELL.DOUBLE_H1[0]
01111011CELL_N.LONG_H[2]
11001111CELL.DOUBLE_H1[1]
11011101CELL.SINGLE_H[4]
11011110CELL.DOUBLE_H0[1]
11111111CELL.SINGLE_H[1]
xc4000e CLB_N switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[31][0]MAIN[31][1]MAIN[32][1]MAIN[32][0]MAIN[31][2]MAIN[32][2]MAIN[32][3]MAIN[33][1]CELL.IMUX_CLB_C3
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[2]
00011110CELL.GCLK[2]
00101011CELL.SINGLE_V[3]
00101101CELL.SINGLE_V[7]
00110011CELL.DOUBLE_V0[0]
00110101CELL.DOUBLE_V1[0]
00111010CELL.LONG_V[3]
00111100CELL.LONG_V[2]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[1]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB_N switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[7][7]MAIN[8][8]MAIN[6][7]MAIN[6][6]MAIN[7][9]MAIN[7][8]MAIN[6][9]MAIN[7][6]CELL.IMUX_CLB_C4
Source
00001111CELL.SINGLE_H[1]
00011011CELL.DOUBLE_H0[0]
00011101CELL.SINGLE_H[6]
00111111CELL.SINGLE_H[0]
01000111CELL.LONG_H[4]
01001110CELL.LONG_H[3]
01010011CELL.SINGLE_H[2]
01010101CELL.SINGLE_H[3]
01011010CELL.DOUBLE_H1[0]
01011100CELL_N.LONG_H[1]
01110111CELL.DOUBLE_H1[1]
01111110CELL.DOUBLE_H0[1]
11001111CELL.SINGLE_H[4]
11011011CELL.SINGLE_H[7]
11011101CELL_N.LONG_H[2]
11111111CELL.SINGLE_H[5]
xc4000e CLB_N switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[14][4]MAIN[20][4]MAIN[19][5]MAIN[17][5]MAIN[20][5]MAIN[19][4]MAIN[18][5]MAIN[18][4]CELL.IMUX_CLB_K
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[3]
01101111CELL.SINGLE_V[6]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[5]
xc4000e CLB_N switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[20][6]MAIN[16][6]MAIN[19][6]MAIN[17][6]MAIN[18][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB_N switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[20][7]MAIN[16][7]MAIN[19][7]MAIN[17][7]MAIN[18][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB_N switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[16][8]MAIN[18][8]MAIN[19][8]MAIN[17][8]MAIN[20][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000e CLB_N switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[16][9]MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000e CLB_N bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000e CLB_N bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[19][0]
F bit 1!MAIN[15][0]
F bit 2!MAIN[20][0]
F bit 3!MAIN[16][0]
F bit 4!MAIN[20][2]
F bit 5!MAIN[16][2]
F bit 6!MAIN[19][2]
F bit 7!MAIN[15][2]
F bit 8!MAIN[17][0]
F bit 9!MAIN[13][0]
F bit 10!MAIN[18][0]
F bit 11!MAIN[14][0]
F bit 12!MAIN[18][2]
F bit 13!MAIN[14][2]
F bit 14!MAIN[17][2]
F bit 15!MAIN[13][2]
G bit 0!MAIN[1][2]
G bit 1!MAIN[0][0]
G bit 2!MAIN[3][2]
G bit 3!MAIN[2][0]
G bit 4!MAIN[5][2]
G bit 5!MAIN[4][0]
G bit 6!MAIN[7][2]
G bit 7!MAIN[6][0]
G bit 8!MAIN[0][2]
G bit 9!MAIN[1][0]
G bit 10!MAIN[2][2]
G bit 11!MAIN[3][0]
G bit 12!MAIN[4][2]
G bit 13!MAIN[5][0]
G bit 14!MAIN[6][2]
G bit 15!MAIN[7][0]
H bit 0!MAIN[6][3]
H bit 1!MAIN[7][3]
H bit 2!MAIN[5][3]
H bit 3!MAIN[4][3]
H bit 4!MAIN[9][3]
H bit 5!MAIN[8][3]
H bit 6!MAIN[10][3]
H bit 7!MAIN[13][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[11][4]
FFY_SRVAL bit 0!MAIN[9][5]
FFX_EC_ENABLE!MAIN[13][5]
FFY_EC_ENABLE!MAIN[7][5]
FFX_SR_ENABLE!MAIN[11][5]
FFY_SR_ENABLE!MAIN[8][5]
FFX_CLK_INV!MAIN[16][5]
FFY_CLK_INV!MAIN[15][5]
MUX_CIN[enum: CLB_MUX_CIN]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[11][3]
READBACK_X bit 0!MAIN[16][4]
READBACK_Y bit 0!MAIN[3][5]
READBACK_XQ bit 0!MAIN[12][5]
READBACK_YQ bit 0!MAIN[8][4]
F_RAM_ENABLE!MAIN[12][2]
G_RAM_ENABLE!MAIN[8][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[2][1]
RAM_SYNC_ENABLE!MAIN[6][1]
RAM_CLK_INV!MAIN[5][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
xc4000e CLB_N enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[13][4]MAIN[16][3]MAIN[15][3]MAIN[15][4]
C11111
C20011
C30101
C40110
xc4000e CLB_N enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[17][3]MAIN[19][3]MAIN[18][3]MAIN[17][4]
C10011
C21111
C30101
C40110
xc4000e CLB_N enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[2][3]MAIN[3][4]MAIN[3][3]MAIN[4][4]
C10011
C20101
C31111
C40110
xc4000e CLB_N enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[0][4]MAIN[1][4]MAIN[2][4]MAIN[1][3]
C10011
C20101
C30110
C41111
xc4000e CLB_N enum CLB_MUX_X
CLB.MUX_XMAIN[14][3]
F0
H1
xc4000e CLB_N enum CLB_MUX_Y
CLB.MUX_YMAIN[5][4]
G0
H1
xc4000e CLB_N enum CLB_MUX_XQ
CLB.MUX_XQMAIN[20][3]
DIN0
FFX1
xc4000e CLB_N enum CLB_MUX_YQ
CLB.MUX_YQMAIN[0][3]
EC0
FFY1
xc4000e CLB_N enum CLB_MUX_D
CLB.MUX_DXMAIN[9][4]MAIN[14][6]MAIN[10][4]MAIN[12][4]
CLB.MUX_DYMAIN[4][5]MAIN[5][5]MAIN[7][4]MAIN[6][4]
F1111
G0011
H0101
DIN0110
xc4000e CLB_N enum CLB_MUX_CIN
CLB.MUX_CINMAIN[9][0]
COUT_S1
COUT_N0
xc4000e CLB_N enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[11][2]MAIN[12][0]
ADD01
SUB11
ADDSUB10
xc4000e CLB_N enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[12][3]MAIN[9][2]
CONST_011
CONST_110
XOR01
xc4000e CLB_N enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[10][0]MAIN[11][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000e CLB_N enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[8][0]
CONST_11
XOR0
xc4000e CLB_N enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[10][2]
_32X11
_16X20
xc4000e CLB_N enum CLB_MUX_H0
CLB.MUX_H0MAIN[3][1]
G1
SR0
xc4000e CLB_N enum CLB_MUX_H2
CLB.MUX_H2MAIN[7][1]
F1
DIN0

Bels TBUF

xc4000e CLB_N bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000e CLB_N bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[22][4]!MAIN[22][6]

Bel wires

xc4000e CLB_N bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000e CLB_N rect MAIN
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 6 - INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 2
B8 - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 2 INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 3
B7 INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7
B6 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 6
B5 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 3 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_K bit 4 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE CLB: ! READBACK_XQ bit 0 CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 CLB: ! READBACK_Y bit 0 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ
B4 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 CLB: MUX_DIN bit 0 CLB: ! READBACK_X bit 0 CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 7 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 CLB: ! READBACK_YQ bit 0 CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3
B3 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 1 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 1 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 4 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 7 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 7 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0
B2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_G1 bit 1 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 CLB: ! G bit 8
B1 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 3 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 3 - - - - - - - - - - - - - CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV - CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE - -
B0 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 8 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: MUX_CIN bit 0 CLB: CARRY_GPROP bit 0 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1
xc4000e CLB_N rect MAIN_S
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_N rect MAIN_W
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_F1 bit 0 INT: mux CELL.IMUX_CLB_G3 bit 0
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_N rect MAIN_N
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_N rect MAIN_E
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLB_NW

Cells: 3

Switchbox INT

xc4000e CLB_NW switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[21][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[25][8]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[33][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[35][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[27][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[33][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[29][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[29][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[26][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[30][8]
xc4000e CLB_NW switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[14][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y!MAIN[2][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ!MAIN[6][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[11][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[13][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[28][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y!MAIN[1][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[22][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ!MAIN[0][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[13][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[29][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[12][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[27][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[35][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[34][7]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[21][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ!MAIN[23][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[23][8]
CELL.SINGLE_V[1]CELL.OUT_CLB_X!MAIN[24][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[29][8]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[25][4]
CELL.SINGLE_V[3]CELL.LONG_H[2]!MAIN_S[28][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[30][4]
CELL.SINGLE_V[4]CELL.LONG_H[3]!MAIN[21][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ!MAIN[34][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[35][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X!MAIN[31][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[35][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[34][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[21][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[33][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[13][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y!MAIN[10][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ!MAIN[15][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[21][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X!MAIN[32][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ!MAIN[35][4]
xc4000e CLB_NW switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[23][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[25][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[24][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[24][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[26][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[28][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[26][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[23][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[25][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[31][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[34][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[30][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[30][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[31][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[32][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[30][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[31][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[31][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[33][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[30][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[32][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[21][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[23][5]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[25][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[26][5]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[26][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[27][9]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[27][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[28][7]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[34][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[32][6]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[31][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[29][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[32][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[34][9]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[24][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[26][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[25][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[31][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[24][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[22][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[23][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[27][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[28][3]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[24][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[24][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[28][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[29][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
xc4000e CLB_NW switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[26][2]MAIN[28][0]MAIN[27][1]MAIN[26][0]MAIN[27][3]MAIN[26][1]MAIN[27][0]MAIN[27][2]MAIN_W[7][3]CELL.IMUX_CLB_F1
Source
001001111CELL.SINGLE_V[3]
001010111CELL.LONG_V[4]
001011101CELL.SINGLE_V[7]
001111111CELL.SINGLE_V[0]
010001111CELL.LONG_V[3]
010010111CELL.DOUBLE_V0[1]
010011101CELL.LONG_V[0]
010111111CELL.SINGLE_V[1]
011001011CELL.SINGLE_V[5]
011010011CELL.LONG_V[1]
011011001CELL.SINGLE_V[6]
011011110CELL.GCLK[1]
011111011CELL.DOUBLE_V1[1]
111001111CELL.DOUBLE_V1[0]
111010111CELL.SINGLE_V[4]
111011101CELL.DOUBLE_V0[0]
111111111CELL.SINGLE_V[2]
xc4000e CLB_NW switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[10][9]MAIN[10][7]MAIN[11][6]MAIN[11][8]MAIN[11][9]MAIN[12][8]MAIN[12][7]MAIN[12][6]CELL.IMUX_CLB_F2
Source
00110011CELL.SINGLE_H[5]
00110101CELL.LONG_H[5]
00110110CELL.DOUBLE_H1[1]
00111111CELL.SINGLE_H[0]
01010011CELL.SINGLE_H[4]
01010101CELL.DOUBLE_H0[1]
01010110CELL.LONG_H[4]
01011111CELL.SINGLE_H[1]
01100011CELL.SINGLE_H[6]
01100101CELL_N.LONG_H[2]
01100110CELL_N.LONG_H[0]
01101111CELL.SINGLE_H[3]
11110011CELL.DOUBLE_H0[0]
11110101CELL.SINGLE_H[7]
11110110CELL.DOUBLE_H1[0]
11111111CELL.SINGLE_H[2]
xc4000e CLB_NW switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[33][2]MAIN[35][0]MAIN[34][2]MAIN[35][1]MAIN[33][0]MAIN[34][1]MAIN[35][2]MAIN[34][0]MAIN[35][3]CELL.IMUX_CLB_F3
Source
000011111CELL.SINGLE_V[0]
000111011CELL.DOUBLE_V0[0]
000111101CELL.LONG_V[2]
001111111CELL.SINGLE_V[3]
010001111CELL.DOUBLE_V1[1]
010010111CELL.LONG_V[1]
010101011CELL.DOUBLE_V0[1]
010101101CELL.LONG_V[5]
010110011CELL.SINGLE_V[4]
010110101CELL.LONG_V[4]
010111110CELL.GCLK[0]
011101111CELL.SINGLE_V[1]
011110111CELL.SINGLE_V[2]
110011111CELL.SINGLE_V[6]
110111011CELL.DOUBLE_V1[0]
110111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[7]
xc4000e CLB_NW switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[9][7]MAIN[8][6]MAIN[9][6]MAIN[9][8]MAIN[8][7]MAIN[10][6]MAIN[8][9]MAIN[9][9]MAIN[10][8]CELL.IMUX_CLB_F4
Source
000111111CELL.SPECIAL_CLB_CIN
001001111CELL.SINGLE_H[0]
001011011CELL.DOUBLE_H1[0]
001011101CELL_N.LONG_H[0]
001100111CELL.LONG_H[5]
001101110CELL.LONG_H[3]
001110011CELL.SINGLE_H[2]
001110101CELL.SINGLE_H[3]
001111010CELL.SINGLE_H[7]
001111100CELL_N.LONG_H[1]
011011111CELL.SINGLE_H[1]
011110111CELL.DOUBLE_H1[1]
011111110CELL.DOUBLE_H0[1]
101101111CELL.SINGLE_H[5]
101111011CELL.DOUBLE_H0[0]
101111101CELL.SINGLE_H[6]
111111111CELL.SINGLE_H[4]
xc4000e CLB_NW switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[21][0]MAIN[21][3]MAIN[23][0]MAIN[23][1]MAIN[22][1]MAIN[21][1]MAIN[22][0]MAIN[21][2]MAIN[22][2]CELL.IMUX_CLB_G1
Source
000011111CELL.SINGLE_V[0]
000101111CELL.SINGLE_V[2]
000111011CELL.SINGLE_V[4]
001010111CELL.LONG_V[4]
001011101CELL.LONG_V[3]
001100111CELL.SINGLE_V[1]
001101101CELL.DOUBLE_V1[0]
001110011CELL.DOUBLE_V0[1]
001111001CELL.LONG_V[0]
001111110CELL.GCLK[1]
011011111CELL.SINGLE_V[3]
011101111CELL.DOUBLE_V0[0]
011111011CELL.SINGLE_V[7]
100111111CELL.DOUBLE_V1[1]
101110111CELL.LONG_V[1]
101111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[6]
xc4000e CLB_NW switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[2][7]MAIN[2][6]MAIN[3][7]MAIN[3][8]MAIN[2][8]MAIN[2][9]MAIN[3][6]MAIN[4][8]CELL.IMUX_CLB_G2
Source
00001111CELL.LONG_H[4]
00011101CELL.SINGLE_H[4]
00011110CELL.LONG_H[5]
00111111CELL.SINGLE_H[1]
01000111CELL.SINGLE_H[2]
01001011CELL.SINGLE_H[3]
01010101CELL.SINGLE_H[7]
01010110CELL.DOUBLE_H0[0]
01011001CELL_N.LONG_H[2]
01011010CELL.SINGLE_H[6]
01110111CELL_N.LONG_H[0]
01111011CELL.DOUBLE_H1[0]
11001111CELL.DOUBLE_H1[1]
11011101CELL.SINGLE_H[5]
11011110CELL.DOUBLE_H0[1]
11111111CELL.SINGLE_H[0]
xc4000e CLB_NW switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[29][0]MAIN[28][2]MAIN[28][1]MAIN[29][2]MAIN[30][0]MAIN[29][1]MAIN[30][2]MAIN[30][3]MAIN_W[8][2]CELL.IMUX_CLB_G3
Source
000011111CELL.SINGLE_V[0]
000101111CELL.SINGLE_V[2]
000111011CELL.SINGLE_V[4]
001010111CELL.LONG_V[4]
001011101CELL.LONG_V[2]
001100111CELL.SINGLE_V[1]
001101101CELL.SINGLE_V[6]
001110011CELL.DOUBLE_V0[1]
001111001CELL.LONG_V[5]
001111110CELL.GCLK[0]
011011111CELL.DOUBLE_V0[0]
011101111CELL.SINGLE_V[5]
011111011CELL.DOUBLE_V1[0]
100111111CELL.DOUBLE_V1[1]
101110111CELL.LONG_V[1]
101111101CELL.SINGLE_V[7]
111111111CELL.SINGLE_V[3]
xc4000e CLB_NW switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[5][9]MAIN[4][9]MAIN[6][8]MAIN[4][6]MAIN[4][7]MAIN[5][7]MAIN[5][8]MAIN[5][6]CELL.IMUX_CLB_G4
Source
00001111CELL.SINGLE_H[0]
00010111CELL.SINGLE_H[1]
00011101CELL_N.LONG_H[0]
00101011CELL.DOUBLE_H1[1]
00101110CELL.LONG_H[3]
00110011CELL.LONG_H[5]
00110110CELL.DOUBLE_H0[1]
00111001CELL.SINGLE_H[3]
00111100CELL.SINGLE_H[6]
01011111CELL.DOUBLE_H1[0]
01111011CELL.SINGLE_H[2]
01111110CELL.DOUBLE_H0[0]
10101111CELL.SINGLE_H[5]
10110111CELL.SINGLE_H[4]
10111101CELL_N.LONG_H[1]
11111111CELL.SINGLE_H[7]
xc4000e CLB_NW switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[23][3]MAIN[23][2]MAIN[25][1]MAIN[24][0]MAIN[24][1]MAIN[25][2]MAIN[24][2]MAIN[25][0]CELL.IMUX_CLB_C1
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[1]
00011110CELL.GCLK[3]
00101011CELL.DOUBLE_V0[0]
00101101CELL.DOUBLE_V1[0]
00110011CELL.SINGLE_V[3]
00110101CELL.SINGLE_V[7]
00111010CELL.LONG_V[2]
00111100CELL.LONG_V[3]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[2]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB_NW switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[0][7]MAIN[0][6]MAIN[1][7]MAIN[1][9]MAIN[0][8]MAIN[0][9]MAIN[1][6]MAIN[1][8]CELL.IMUX_CLB_C2
Source
00001111CELL.LONG_H[4]
00011101CELL.SINGLE_H[5]
00011110CELL.LONG_H[3]
00111111CELL.SINGLE_H[0]
01000111CELL.SINGLE_H[2]
01001011CELL.SINGLE_H[3]
01010101CELL.SINGLE_H[7]
01010110CELL.DOUBLE_H0[0]
01011001CELL_N.LONG_H[1]
01011010CELL.SINGLE_H[6]
01110111CELL.DOUBLE_H1[0]
01111011CELL_N.LONG_H[2]
11001111CELL.DOUBLE_H1[1]
11011101CELL.SINGLE_H[4]
11011110CELL.DOUBLE_H0[1]
11111111CELL.SINGLE_H[1]
xc4000e CLB_NW switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[31][0]MAIN[31][1]MAIN[32][1]MAIN[32][0]MAIN[31][2]MAIN[32][2]MAIN[32][3]MAIN[33][1]CELL.IMUX_CLB_C3
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[2]
00011110CELL.GCLK[2]
00101011CELL.SINGLE_V[3]
00101101CELL.SINGLE_V[7]
00110011CELL.DOUBLE_V0[0]
00110101CELL.DOUBLE_V1[0]
00111010CELL.LONG_V[3]
00111100CELL.LONG_V[2]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[1]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB_NW switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[7][7]MAIN[8][8]MAIN[6][7]MAIN[6][6]MAIN[7][9]MAIN[7][8]MAIN[6][9]MAIN[7][6]CELL.IMUX_CLB_C4
Source
00001111CELL.SINGLE_H[1]
00011011CELL.DOUBLE_H0[0]
00011101CELL.SINGLE_H[6]
00111111CELL.SINGLE_H[0]
01000111CELL.LONG_H[4]
01001110CELL.LONG_H[3]
01010011CELL.SINGLE_H[2]
01010101CELL.SINGLE_H[3]
01011010CELL.DOUBLE_H1[0]
01011100CELL_N.LONG_H[1]
01110111CELL.DOUBLE_H1[1]
01111110CELL.DOUBLE_H0[1]
11001111CELL.SINGLE_H[4]
11011011CELL.SINGLE_H[7]
11011101CELL_N.LONG_H[2]
11111111CELL.SINGLE_H[5]
xc4000e CLB_NW switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[14][4]MAIN[20][4]MAIN[19][5]MAIN[17][5]MAIN[20][5]MAIN[19][4]MAIN[18][5]MAIN[18][4]CELL.IMUX_CLB_K
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[3]
01101111CELL.SINGLE_V[6]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[5]
xc4000e CLB_NW switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[20][6]MAIN[16][6]MAIN[19][6]MAIN[17][6]MAIN[18][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB_NW switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[20][7]MAIN[16][7]MAIN[19][7]MAIN[17][7]MAIN[18][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB_NW switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[16][8]MAIN[18][8]MAIN[19][8]MAIN[17][8]MAIN[20][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000e CLB_NW switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[16][9]MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000e CLB_NW bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000e CLB_NW bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[19][0]
F bit 1!MAIN[15][0]
F bit 2!MAIN[20][0]
F bit 3!MAIN[16][0]
F bit 4!MAIN[20][2]
F bit 5!MAIN[16][2]
F bit 6!MAIN[19][2]
F bit 7!MAIN[15][2]
F bit 8!MAIN[17][0]
F bit 9!MAIN[13][0]
F bit 10!MAIN[18][0]
F bit 11!MAIN[14][0]
F bit 12!MAIN[18][2]
F bit 13!MAIN[14][2]
F bit 14!MAIN[17][2]
F bit 15!MAIN[13][2]
G bit 0!MAIN[1][2]
G bit 1!MAIN[0][0]
G bit 2!MAIN[3][2]
G bit 3!MAIN[2][0]
G bit 4!MAIN[5][2]
G bit 5!MAIN[4][0]
G bit 6!MAIN[7][2]
G bit 7!MAIN[6][0]
G bit 8!MAIN[0][2]
G bit 9!MAIN[1][0]
G bit 10!MAIN[2][2]
G bit 11!MAIN[3][0]
G bit 12!MAIN[4][2]
G bit 13!MAIN[5][0]
G bit 14!MAIN[6][2]
G bit 15!MAIN[7][0]
H bit 0!MAIN[6][3]
H bit 1!MAIN[7][3]
H bit 2!MAIN[5][3]
H bit 3!MAIN[4][3]
H bit 4!MAIN[9][3]
H bit 5!MAIN[8][3]
H bit 6!MAIN[10][3]
H bit 7!MAIN[13][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[11][4]
FFY_SRVAL bit 0!MAIN[9][5]
FFX_EC_ENABLE!MAIN[13][5]
FFY_EC_ENABLE!MAIN[7][5]
FFX_SR_ENABLE!MAIN[11][5]
FFY_SR_ENABLE!MAIN[8][5]
FFX_CLK_INV!MAIN[16][5]
FFY_CLK_INV!MAIN[15][5]
MUX_CIN[enum: CLB_MUX_CIN]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[11][3]
READBACK_X bit 0!MAIN[16][4]
READBACK_Y bit 0!MAIN[3][5]
READBACK_XQ bit 0!MAIN[12][5]
READBACK_YQ bit 0!MAIN[8][4]
F_RAM_ENABLE!MAIN[12][2]
G_RAM_ENABLE!MAIN[8][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[2][1]
RAM_SYNC_ENABLE!MAIN[6][1]
RAM_CLK_INV!MAIN[5][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
xc4000e CLB_NW enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[13][4]MAIN[16][3]MAIN[15][3]MAIN[15][4]
C11111
C20011
C30101
C40110
xc4000e CLB_NW enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[17][3]MAIN[19][3]MAIN[18][3]MAIN[17][4]
C10011
C21111
C30101
C40110
xc4000e CLB_NW enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[2][3]MAIN[3][4]MAIN[3][3]MAIN[4][4]
C10011
C20101
C31111
C40110
xc4000e CLB_NW enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[0][4]MAIN[1][4]MAIN[2][4]MAIN[1][3]
C10011
C20101
C30110
C41111
xc4000e CLB_NW enum CLB_MUX_X
CLB.MUX_XMAIN[14][3]
F0
H1
xc4000e CLB_NW enum CLB_MUX_Y
CLB.MUX_YMAIN[5][4]
G0
H1
xc4000e CLB_NW enum CLB_MUX_XQ
CLB.MUX_XQMAIN[20][3]
DIN0
FFX1
xc4000e CLB_NW enum CLB_MUX_YQ
CLB.MUX_YQMAIN[0][3]
EC0
FFY1
xc4000e CLB_NW enum CLB_MUX_D
CLB.MUX_DXMAIN[9][4]MAIN[14][6]MAIN[10][4]MAIN[12][4]
CLB.MUX_DYMAIN[4][5]MAIN[5][5]MAIN[7][4]MAIN[6][4]
F1111
G0011
H0101
DIN0110
xc4000e CLB_NW enum CLB_MUX_CIN
CLB.MUX_CINMAIN[9][0]
COUT_S1
COUT_N0
xc4000e CLB_NW enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[11][2]MAIN[12][0]
ADD01
SUB11
ADDSUB10
xc4000e CLB_NW enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[12][3]MAIN[9][2]
CONST_011
CONST_110
XOR01
xc4000e CLB_NW enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[10][0]MAIN[11][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000e CLB_NW enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[8][0]
CONST_11
XOR0
xc4000e CLB_NW enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[10][2]
_32X11
_16X20
xc4000e CLB_NW enum CLB_MUX_H0
CLB.MUX_H0MAIN[3][1]
G1
SR0
xc4000e CLB_NW enum CLB_MUX_H2
CLB.MUX_H2MAIN[7][1]
F1
DIN0

Bels TBUF

xc4000e CLB_NW bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000e CLB_NW bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[22][4]!MAIN[22][6]

Bel wires

xc4000e CLB_NW bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000e CLB_NW rect MAIN
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 6 - INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 2
B8 - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 2 INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 3
B7 INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7
B6 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 6
B5 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 3 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_K bit 4 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE CLB: ! READBACK_XQ bit 0 CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 CLB: ! READBACK_Y bit 0 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ
B4 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 CLB: MUX_DIN bit 0 CLB: ! READBACK_X bit 0 CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 7 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 CLB: ! READBACK_YQ bit 0 CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3
B3 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 1 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 1 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 4 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 7 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 7 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0
B2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_G1 bit 1 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 CLB: ! G bit 8
B1 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 6 - INT: mux CELL.IMUX_CLB_G3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 3 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 3 - - - - - - - - - - - - - CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV - CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE - -
B0 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 8 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: MUX_CIN bit 0 CLB: CARRY_GPROP bit 0 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1
xc4000e CLB_NW rect MAIN_S
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_NW rect MAIN_W
BitFrame
F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_F1 bit 0 - - - - - - -
B2 - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_G3 bit 0 - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_NW rect MAIN_N
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_NW rect MAIN_E
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tile CLB_NE

Cells: 3

Switchbox INT

xc4000e CLB_NE switchbox INT programmable buffers
DestinationSourceBit
CELL.LONG_H[0]CELL.SINGLE_V[1]!MAIN_S[21][8]
CELL.LONG_H[1]CELL.SINGLE_V[2]!MAIN_S[25][8]
CELL.LONG_H[4]CELL.SINGLE_V[5]!MAIN[33][4]
CELL.LONG_H[5]CELL.SINGLE_V[6]!MAIN[35][6]
CELL.LONG_V[0]CELL.SINGLE_H_E[1]!MAIN[27][4]
CELL.LONG_V[1]CELL.SINGLE_H_E[2]!MAIN[33][8]
CELL.LONG_V[2]CELL.SINGLE_H_E[3]!MAIN[29][6]
CELL.LONG_V[3]CELL.SINGLE_H[4]!MAIN[29][4]
CELL.LONG_V[4]CELL.SINGLE_H[5]!MAIN[26][6]
CELL.LONG_V[5]CELL.SINGLE_H[6]!MAIN[30][8]
xc4000e CLB_NE switchbox INT pass gates
DestinationSourceBit
CELL.SINGLE_H[0]CELL.TIE_0!MAIN[14][5]
CELL.SINGLE_H[0]CELL.OUT_CLB_Y!MAIN[2][5]
CELL.SINGLE_H[1]CELL.OUT_CLB_YQ!MAIN[6][5]
CELL.SINGLE_H[2]CELL.OUT_CLB_XQ_S!MAIN[14][7]
CELL.SINGLE_H[3]CELL.TIE_0!MAIN[11][7]
CELL.SINGLE_H[3]CELL.OUT_CLB_X_S!MAIN[13][9]
CELL.SINGLE_H[4]CELL.LONG_V[3]!MAIN[28][4]
CELL.SINGLE_H[4]CELL.OUT_CLB_Y!MAIN[1][5]
CELL.SINGLE_H[5]CELL.LONG_V[4]!MAIN[22][3]
CELL.SINGLE_H[5]CELL.OUT_CLB_YQ!MAIN[0][5]
CELL.SINGLE_H[6]CELL.TIE_0!MAIN[13][6]
CELL.SINGLE_H[6]CELL.LONG_V[5]!MAIN[29][9]
CELL.SINGLE_H[6]CELL.OUT_CLB_XQ_S!MAIN[15][7]
CELL.SINGLE_H[7]CELL.TIE_0!MAIN[12][9]
CELL.SINGLE_H[7]CELL.OUT_CLB_X_S!MAIN[14][9]
CELL.SINGLE_H_E[1]CELL.LONG_V[0]!MAIN[27][5]
CELL.SINGLE_H_E[2]CELL.LONG_V[1]!MAIN[35][9]
CELL.SINGLE_H_E[3]CELL.LONG_V[2]!MAIN[34][7]
CELL.SINGLE_V[0]CELL.TIE_0!MAIN[21][6]
CELL.SINGLE_V[0]CELL.OUT_CLB_XQ!MAIN[23][4]
CELL.SINGLE_V[1]CELL.LONG_H[0]!MAIN_S[23][8]
CELL.SINGLE_V[1]CELL.OUT_CLB_X!MAIN[24][4]
CELL.SINGLE_V[2]CELL.LONG_H[1]!MAIN_S[29][8]
CELL.SINGLE_V[2]CELL.OUT_CLB_Y_E!MAIN[25][4]
CELL.SINGLE_V[3]CELL.LONG_H[2]!MAIN_S[28][9]
CELL.SINGLE_V[3]CELL.OUT_CLB_YQ_E!MAIN[30][4]
CELL.SINGLE_V[4]CELL.LONG_H[3]!MAIN[21][7]
CELL.SINGLE_V[4]CELL.OUT_CLB_XQ!MAIN[34][3]
CELL.SINGLE_V[5]CELL.LONG_H[4]!MAIN[35][5]
CELL.SINGLE_V[5]CELL.OUT_CLB_X!MAIN[31][4]
CELL.SINGLE_V[6]CELL.LONG_H[5]!MAIN[35][7]
CELL.SINGLE_V[6]CELL.OUT_CLB_Y_E!MAIN[34][4]
CELL.SINGLE_V[7]CELL.TIE_0!MAIN[21][9]
CELL.SINGLE_V[7]CELL.OUT_CLB_YQ_E!MAIN[33][3]
CELL.DOUBLE_H0[0]CELL.OUT_CLB_XQ_S!MAIN[13][7]
CELL.DOUBLE_H0[1]CELL.OUT_CLB_Y!MAIN[10][5]
CELL.DOUBLE_H1[0]CELL.OUT_CLB_X_S!MAIN[15][9]
CELL.DOUBLE_H1[1]CELL.OUT_CLB_YQ!MAIN[15][6]
CELL.DOUBLE_V0[0]CELL.OUT_CLB_YQ_E!MAIN[21][4]
CELL.DOUBLE_V0[1]CELL.OUT_CLB_X!MAIN[32][4]
CELL.DOUBLE_V1[0]CELL.OUT_CLB_Y_E!MAIN[26][4]
CELL.DOUBLE_V1[1]CELL.OUT_CLB_XQ!MAIN[35][4]
xc4000e CLB_NE switchbox INT bidirectional pass gates
Side ASide BBit
CELL.SINGLE_H[0]CELL.SINGLE_H_E[0]!MAIN[23][6]
CELL.SINGLE_H[0]CELL.SINGLE_V[0]!MAIN[22][5]
CELL.SINGLE_H[0]CELL.SINGLE_V_S[0]!MAIN[25][3]
CELL.SINGLE_H[1]CELL.SINGLE_H_E[1]!MAIN[25][5]
CELL.SINGLE_H[1]CELL.SINGLE_V[1]!MAIN[24][5]
CELL.SINGLE_H[1]CELL.SINGLE_V_S[1]!MAIN[24][3]
CELL.SINGLE_H[2]CELL.SINGLE_H_E[2]!MAIN[27][8]
CELL.SINGLE_H[2]CELL.SINGLE_V[2]!MAIN[26][8]
CELL.SINGLE_H[2]CELL.SINGLE_V_S[2]!MAIN[28][8]
CELL.SINGLE_H[3]CELL.SINGLE_H_E[3]!MAIN[26][7]
CELL.SINGLE_H[3]CELL.SINGLE_V[3]!MAIN[23][7]
CELL.SINGLE_H[3]CELL.SINGLE_V_S[3]!MAIN[25][7]
CELL.SINGLE_H[4]CELL.SINGLE_H_E[4]!MAIN[31][6]
CELL.SINGLE_H[4]CELL.SINGLE_V[4]!MAIN[34][6]
CELL.SINGLE_H[4]CELL.SINGLE_V_S[4]!MAIN[30][6]
CELL.SINGLE_H[5]CELL.SINGLE_H_E[5]!MAIN[30][5]
CELL.SINGLE_H[5]CELL.SINGLE_V[5]!MAIN[31][3]
CELL.SINGLE_H[5]CELL.SINGLE_V_S[5]!MAIN[32][5]
CELL.SINGLE_H[6]CELL.SINGLE_H_E[6]!MAIN[30][7]
CELL.SINGLE_H[6]CELL.SINGLE_V[6]!MAIN[31][8]
CELL.SINGLE_H[6]CELL.SINGLE_V_S[6]!MAIN[31][7]
CELL.SINGLE_H[7]CELL.SINGLE_H_E[7]!MAIN[33][9]
CELL.SINGLE_H[7]CELL.SINGLE_V[7]!MAIN[30][9]
CELL.SINGLE_H[7]CELL.SINGLE_V_S[7]!MAIN[32][8]
CELL.SINGLE_H_E[0]CELL.SINGLE_V[0]!MAIN[21][5]
CELL.SINGLE_H_E[0]CELL.SINGLE_V_S[0]!MAIN[23][5]
CELL.SINGLE_H_E[1]CELL.SINGLE_V[1]!MAIN[25][6]
CELL.SINGLE_H_E[1]CELL.SINGLE_V_S[1]!MAIN[26][5]
CELL.SINGLE_H_E[2]CELL.SINGLE_V[2]!MAIN[26][9]
CELL.SINGLE_H_E[2]CELL.SINGLE_V_S[2]!MAIN[27][9]
CELL.SINGLE_H_E[3]CELL.SINGLE_V[3]!MAIN[27][7]
CELL.SINGLE_H_E[3]CELL.SINGLE_V_S[3]!MAIN[28][7]
CELL.SINGLE_H_E[4]CELL.SINGLE_V[4]!MAIN[34][8]
CELL.SINGLE_H_E[4]CELL.SINGLE_V_S[4]!MAIN[32][6]
CELL.SINGLE_H_E[5]CELL.SINGLE_V[5]!MAIN[31][5]
CELL.SINGLE_H_E[5]CELL.SINGLE_V_S[5]!MAIN[33][5]
CELL.SINGLE_H_E[6]CELL.SINGLE_V[6]!MAIN[29][7]
CELL.SINGLE_H_E[6]CELL.SINGLE_V_S[6]!MAIN[32][7]
CELL.SINGLE_H_E[7]CELL.SINGLE_V[7]!MAIN[32][9]
CELL.SINGLE_H_E[7]CELL.SINGLE_V_S[7]!MAIN[34][9]
CELL.SINGLE_V[0]CELL.SINGLE_V_S[0]!MAIN[24][6]
CELL.SINGLE_V[1]CELL.SINGLE_V_S[1]!MAIN[26][3]
CELL.SINGLE_V[2]CELL.SINGLE_V_S[2]!MAIN[25][9]
CELL.SINGLE_V[3]CELL.SINGLE_V_S[3]!MAIN[22][7]
CELL.SINGLE_V[4]CELL.SINGLE_V_S[4]!MAIN[33][6]
CELL.SINGLE_V[5]CELL.SINGLE_V_S[5]!MAIN[34][5]
CELL.SINGLE_V[6]CELL.SINGLE_V_S[6]!MAIN[33][7]
CELL.SINGLE_V[7]CELL.SINGLE_V_S[7]!MAIN[31][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_H2[0]!MAIN[24][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V0[0]!MAIN[22][9]
CELL.DOUBLE_H0[0]CELL.DOUBLE_V2[0]!MAIN[23][9]
CELL.DOUBLE_H0[1]CELL.DOUBLE_H2[1]!MAIN[28][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V0[1]!MAIN[27][6]
CELL.DOUBLE_H0[1]CELL.DOUBLE_V2[1]!MAIN[28][3]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V0[0]!MAIN[24][7]
CELL.DOUBLE_H2[0]CELL.DOUBLE_V2[0]!MAIN[24][8]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V0[1]!MAIN[28][5]
CELL.DOUBLE_H2[1]CELL.DOUBLE_V2[1]!MAIN[29][5]
CELL.DOUBLE_V0[0]CELL.DOUBLE_V2[0]!MAIN[22][8]
CELL.DOUBLE_V0[1]CELL.DOUBLE_V2[1]!MAIN[29][3]
xc4000e CLB_NE switchbox INT muxes IMUX_CLB_F1
BitsDestination
MAIN[26][2]MAIN[28][0]MAIN[27][1]MAIN[26][0]MAIN[27][3]MAIN[26][1]MAIN[27][0]MAIN[27][2]MAIN_W[1][1]CELL.IMUX_CLB_F1
Source
001001111CELL.SINGLE_V[3]
001010111CELL.LONG_V[4]
001011101CELL.SINGLE_V[7]
001111111CELL.SINGLE_V[0]
010001111CELL.LONG_V[3]
010010111CELL.DOUBLE_V0[1]
010011101CELL.LONG_V[0]
010111111CELL.SINGLE_V[1]
011001011CELL.SINGLE_V[5]
011010011CELL.LONG_V[1]
011011001CELL.SINGLE_V[6]
011011110CELL.GCLK[1]
011111011CELL.DOUBLE_V1[1]
111001111CELL.DOUBLE_V1[0]
111010111CELL.SINGLE_V[4]
111011101CELL.DOUBLE_V0[0]
111111111CELL.SINGLE_V[2]
xc4000e CLB_NE switchbox INT muxes IMUX_CLB_F2
BitsDestination
MAIN[10][9]MAIN[10][7]MAIN[11][6]MAIN[11][8]MAIN[11][9]MAIN[12][8]MAIN[12][7]MAIN[12][6]CELL.IMUX_CLB_F2
Source
00110011CELL.SINGLE_H[5]
00110101CELL.LONG_H[5]
00110110CELL.DOUBLE_H1[1]
00111111CELL.SINGLE_H[0]
01010011CELL.SINGLE_H[4]
01010101CELL.DOUBLE_H0[1]
01010110CELL.LONG_H[4]
01011111CELL.SINGLE_H[1]
01100011CELL.SINGLE_H[6]
01100101CELL_N.LONG_H[2]
01100110CELL_N.LONG_H[0]
01101111CELL.SINGLE_H[3]
11110011CELL.DOUBLE_H0[0]
11110101CELL.SINGLE_H[7]
11110110CELL.DOUBLE_H1[0]
11111111CELL.SINGLE_H[2]
xc4000e CLB_NE switchbox INT muxes IMUX_CLB_F3
BitsDestination
MAIN[33][2]MAIN[35][0]MAIN[34][2]MAIN[35][1]MAIN[33][0]MAIN[34][1]MAIN[35][2]MAIN[34][0]MAIN[35][3]CELL.IMUX_CLB_F3
Source
000011111CELL.SINGLE_V[0]
000111011CELL.DOUBLE_V0[0]
000111101CELL.LONG_V[2]
001111111CELL.SINGLE_V[3]
010001111CELL.DOUBLE_V1[1]
010010111CELL.LONG_V[1]
010101011CELL.DOUBLE_V0[1]
010101101CELL.LONG_V[5]
010110011CELL.SINGLE_V[4]
010110101CELL.LONG_V[4]
010111110CELL.GCLK[0]
011101111CELL.SINGLE_V[1]
011110111CELL.SINGLE_V[2]
110011111CELL.SINGLE_V[6]
110111011CELL.DOUBLE_V1[0]
110111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[7]
xc4000e CLB_NE switchbox INT muxes IMUX_CLB_F4
BitsDestination
MAIN[9][7]MAIN[8][6]MAIN[9][6]MAIN[9][8]MAIN[8][7]MAIN[10][6]MAIN[8][9]MAIN[9][9]MAIN[10][8]CELL.IMUX_CLB_F4
Source
000111111CELL.SPECIAL_CLB_CIN
001001111CELL.SINGLE_H[0]
001011011CELL.DOUBLE_H1[0]
001011101CELL_N.LONG_H[0]
001100111CELL.LONG_H[5]
001101110CELL.LONG_H[3]
001110011CELL.SINGLE_H[2]
001110101CELL.SINGLE_H[3]
001111010CELL.SINGLE_H[7]
001111100CELL_N.LONG_H[1]
011011111CELL.SINGLE_H[1]
011110111CELL.DOUBLE_H1[1]
011111110CELL.DOUBLE_H0[1]
101101111CELL.SINGLE_H[5]
101111011CELL.DOUBLE_H0[0]
101111101CELL.SINGLE_H[6]
111111111CELL.SINGLE_H[4]
xc4000e CLB_NE switchbox INT muxes IMUX_CLB_G1
BitsDestination
MAIN[21][0]MAIN[21][3]MAIN[23][0]MAIN[23][1]MAIN[22][1]MAIN[21][1]MAIN[22][0]MAIN[21][2]MAIN[22][2]CELL.IMUX_CLB_G1
Source
000011111CELL.SINGLE_V[0]
000101111CELL.SINGLE_V[2]
000111011CELL.SINGLE_V[4]
001010111CELL.LONG_V[4]
001011101CELL.LONG_V[3]
001100111CELL.SINGLE_V[1]
001101101CELL.DOUBLE_V1[0]
001110011CELL.DOUBLE_V0[1]
001111001CELL.LONG_V[0]
001111110CELL.GCLK[1]
011011111CELL.SINGLE_V[3]
011101111CELL.DOUBLE_V0[0]
011111011CELL.SINGLE_V[7]
100111111CELL.DOUBLE_V1[1]
101110111CELL.LONG_V[1]
101111101CELL.SINGLE_V[5]
111111111CELL.SINGLE_V[6]
xc4000e CLB_NE switchbox INT muxes IMUX_CLB_G2
BitsDestination
MAIN[2][7]MAIN[2][6]MAIN[3][7]MAIN[3][8]MAIN[2][8]MAIN[2][9]MAIN[3][6]MAIN[4][8]CELL.IMUX_CLB_G2
Source
00001111CELL.LONG_H[4]
00011101CELL.SINGLE_H[4]
00011110CELL.LONG_H[5]
00111111CELL.SINGLE_H[1]
01000111CELL.SINGLE_H[2]
01001011CELL.SINGLE_H[3]
01010101CELL.SINGLE_H[7]
01010110CELL.DOUBLE_H0[0]
01011001CELL_N.LONG_H[2]
01011010CELL.SINGLE_H[6]
01110111CELL_N.LONG_H[0]
01111011CELL.DOUBLE_H1[0]
11001111CELL.DOUBLE_H1[1]
11011101CELL.SINGLE_H[5]
11011110CELL.DOUBLE_H0[1]
11111111CELL.SINGLE_H[0]
xc4000e CLB_NE switchbox INT muxes IMUX_CLB_G3
BitsDestination
MAIN[29][0]MAIN[28][2]MAIN[30][1]MAIN[28][1]MAIN[29][2]MAIN[30][0]MAIN[29][1]MAIN[30][2]MAIN[30][3]MAIN_W[0][1]CELL.IMUX_CLB_G3
Source
0001111111CELL.SPECIAL_CLB_CIN
0010011111CELL.SINGLE_V[0]
0010101111CELL.SINGLE_V[2]
0010111011CELL.SINGLE_V[4]
0011010111CELL.LONG_V[4]
0011011101CELL.LONG_V[2]
0011100111CELL.SINGLE_V[1]
0011101101CELL.SINGLE_V[6]
0011110011CELL.DOUBLE_V0[1]
0011111001CELL.LONG_V[5]
0011111110CELL.GCLK[0]
0111011111CELL.DOUBLE_V0[0]
0111101111CELL.SINGLE_V[5]
0111111011CELL.DOUBLE_V1[0]
1010111111CELL.DOUBLE_V1[1]
1011110111CELL.LONG_V[1]
1011111101CELL.SINGLE_V[7]
1111111111CELL.SINGLE_V[3]
xc4000e CLB_NE switchbox INT muxes IMUX_CLB_G4
BitsDestination
MAIN[5][9]MAIN[4][9]MAIN[6][8]MAIN[4][6]MAIN[4][7]MAIN[5][7]MAIN[5][8]MAIN[5][6]CELL.IMUX_CLB_G4
Source
00001111CELL.SINGLE_H[0]
00010111CELL.SINGLE_H[1]
00011101CELL_N.LONG_H[0]
00101011CELL.DOUBLE_H1[1]
00101110CELL.LONG_H[3]
00110011CELL.LONG_H[5]
00110110CELL.DOUBLE_H0[1]
00111001CELL.SINGLE_H[3]
00111100CELL.SINGLE_H[6]
01011111CELL.DOUBLE_H1[0]
01111011CELL.SINGLE_H[2]
01111110CELL.DOUBLE_H0[0]
10101111CELL.SINGLE_H[5]
10110111CELL.SINGLE_H[4]
10111101CELL_N.LONG_H[1]
11111111CELL.SINGLE_H[7]
xc4000e CLB_NE switchbox INT muxes IMUX_CLB_C1
BitsDestination
MAIN[23][3]MAIN[23][2]MAIN[25][1]MAIN[24][0]MAIN[24][1]MAIN[25][2]MAIN[24][2]MAIN[25][0]CELL.IMUX_CLB_C1
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[1]
00011110CELL.GCLK[3]
00101011CELL.DOUBLE_V0[0]
00101101CELL.DOUBLE_V1[0]
00110011CELL.SINGLE_V[3]
00110101CELL.SINGLE_V[7]
00111010CELL.LONG_V[2]
00111100CELL.LONG_V[3]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[2]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB_NE switchbox INT muxes IMUX_CLB_C2
BitsDestination
MAIN[0][7]MAIN[0][6]MAIN[1][7]MAIN[1][9]MAIN[0][8]MAIN[0][9]MAIN[1][6]MAIN[1][8]CELL.IMUX_CLB_C2
Source
00001111CELL.LONG_H[4]
00011101CELL.SINGLE_H[5]
00011110CELL.LONG_H[3]
00111111CELL.SINGLE_H[0]
01000111CELL.SINGLE_H[2]
01001011CELL.SINGLE_H[3]
01010101CELL.SINGLE_H[7]
01010110CELL.DOUBLE_H0[0]
01011001CELL_N.LONG_H[1]
01011010CELL.SINGLE_H[6]
01110111CELL.DOUBLE_H1[0]
01111011CELL_N.LONG_H[2]
11001111CELL.DOUBLE_H1[1]
11011101CELL.SINGLE_H[4]
11011110CELL.DOUBLE_H0[1]
11111111CELL.SINGLE_H[1]
xc4000e CLB_NE switchbox INT muxes IMUX_CLB_C3
BitsDestination
MAIN[31][0]MAIN[31][1]MAIN[32][1]MAIN[32][0]MAIN[31][2]MAIN[32][2]MAIN[32][3]MAIN[33][1]CELL.IMUX_CLB_C3
Source
00001111CELL.SINGLE_V[0]
00010111CELL.SINGLE_V[2]
00011110CELL.GCLK[2]
00101011CELL.SINGLE_V[3]
00101101CELL.SINGLE_V[7]
00110011CELL.DOUBLE_V0[0]
00110101CELL.DOUBLE_V1[0]
00111010CELL.LONG_V[3]
00111100CELL.LONG_V[2]
01101111CELL.DOUBLE_V1[1]
01110111CELL.SINGLE_V[1]
10011111CELL.DOUBLE_V0[1]
10111011CELL.SINGLE_V[5]
10111101CELL.SINGLE_V[6]
11111111CELL.SINGLE_V[4]
xc4000e CLB_NE switchbox INT muxes IMUX_CLB_C4
BitsDestination
MAIN[7][7]MAIN[8][8]MAIN[6][7]MAIN[6][6]MAIN[7][9]MAIN[7][8]MAIN[6][9]MAIN[7][6]CELL.IMUX_CLB_C4
Source
00001111CELL.SINGLE_H[1]
00011011CELL.DOUBLE_H0[0]
00011101CELL.SINGLE_H[6]
00111111CELL.SINGLE_H[0]
01000111CELL.LONG_H[4]
01001110CELL.LONG_H[3]
01010011CELL.SINGLE_H[2]
01010101CELL.SINGLE_H[3]
01011010CELL.DOUBLE_H1[0]
01011100CELL_N.LONG_H[1]
01110111CELL.DOUBLE_H1[1]
01111110CELL.DOUBLE_H0[1]
11001111CELL.SINGLE_H[4]
11011011CELL.SINGLE_H[7]
11011101CELL_N.LONG_H[2]
11111111CELL.SINGLE_H[5]
xc4000e CLB_NE switchbox INT muxes IMUX_CLB_K
BitsDestination
MAIN[14][4]MAIN[20][4]MAIN[19][5]MAIN[17][5]MAIN[20][5]MAIN[19][4]MAIN[18][5]MAIN[18][4]CELL.IMUX_CLB_K
Source
00111111CELL.SINGLE_V[0]
01011111CELL.SINGLE_V[3]
01101111CELL.SINGLE_V[6]
01110111CELL.GCLK[0]
01111011CELL.GCLK[1]
01111101CELL.GCLK[2]
01111110CELL.GCLK[3]
11111111CELL.SINGLE_V[5]
xc4000e CLB_NE switchbox INT muxes IMUX_TBUF_I[0]
BitsDestination
MAIN[20][6]MAIN[16][6]MAIN[19][6]MAIN[17][6]MAIN[18][6]CELL.IMUX_TBUF_I[0]
Source
00011CELL.SINGLE_V[6]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[3]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB_NE switchbox INT muxes IMUX_TBUF_I[1]
BitsDestination
MAIN[20][7]MAIN[16][7]MAIN[19][7]MAIN[17][7]MAIN[18][7]CELL.IMUX_TBUF_I[1]
Source
00011CELL.SINGLE_V[4]
00101CELL.OUT_CLB_X
00110CELL.OUT_CLB_XQ
01111CELL.SINGLE_V[1]
10011CELL.OUT_CLB_YQ
10101CELL.OUT_CLB_Y
11111CELL.TIE_0
xc4000e CLB_NE switchbox INT muxes IMUX_TBUF_T[0]
BitsDestination
MAIN[16][8]MAIN[18][8]MAIN[19][8]MAIN[17][8]MAIN[20][8]CELL.IMUX_TBUF_T[0]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[2]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[7]
xc4000e CLB_NE switchbox INT muxes IMUX_TBUF_T[1]
BitsDestination
MAIN[16][9]MAIN[17][9]MAIN[18][9]MAIN[19][9]MAIN[20][9]CELL.IMUX_TBUF_T[1]
Source
00011CELL.LONG_V[5]
00111CELL.TIE_0
01001CELL.SINGLE_V[7]
01010CELL.LONG_V[0]
01111CELL.TIE_1
11011CELL.SINGLE_V[2]

Bels CLB

xc4000e CLB_NE bel CLB pins
PinDirectionCLB
F1inCELL.IMUX_CLB_F1
F2inCELL.IMUX_CLB_F2_N
F3inCELL.IMUX_CLB_F3_W
F4inCELL.IMUX_CLB_F4
G1inCELL.IMUX_CLB_G1
G2inCELL.IMUX_CLB_G2_N
G3inCELL.IMUX_CLB_G3_W
G4inCELL.IMUX_CLB_G4
C1inCELL.IMUX_CLB_C1
C2inCELL.IMUX_CLB_C2_N
C3inCELL.IMUX_CLB_C3_W
C4inCELL.IMUX_CLB_C4
KinCELL.IMUX_CLB_K
XoutCELL.OUT_CLB_X
XQoutCELL.OUT_CLB_XQ
YoutCELL.OUT_CLB_Y
YQoutCELL.OUT_CLB_YQ
xc4000e CLB_NE bel CLB attribute bits
AttributeCLB
F bit 0!MAIN[19][0]
F bit 1!MAIN[15][0]
F bit 2!MAIN[20][0]
F bit 3!MAIN[16][0]
F bit 4!MAIN[20][2]
F bit 5!MAIN[16][2]
F bit 6!MAIN[19][2]
F bit 7!MAIN[15][2]
F bit 8!MAIN[17][0]
F bit 9!MAIN[13][0]
F bit 10!MAIN[18][0]
F bit 11!MAIN[14][0]
F bit 12!MAIN[18][2]
F bit 13!MAIN[14][2]
F bit 14!MAIN[17][2]
F bit 15!MAIN[13][2]
G bit 0!MAIN[1][2]
G bit 1!MAIN[0][0]
G bit 2!MAIN[3][2]
G bit 3!MAIN[2][0]
G bit 4!MAIN[5][2]
G bit 5!MAIN[4][0]
G bit 6!MAIN[7][2]
G bit 7!MAIN[6][0]
G bit 8!MAIN[0][2]
G bit 9!MAIN[1][0]
G bit 10!MAIN[2][2]
G bit 11!MAIN[3][0]
G bit 12!MAIN[4][2]
G bit 13!MAIN[5][0]
G bit 14!MAIN[6][2]
G bit 15!MAIN[7][0]
H bit 0!MAIN[6][3]
H bit 1!MAIN[7][3]
H bit 2!MAIN[5][3]
H bit 3!MAIN[4][3]
H bit 4!MAIN[9][3]
H bit 5!MAIN[8][3]
H bit 6!MAIN[10][3]
H bit 7!MAIN[13][3]
MUX_H1[enum: CLB_MUX_CTRL]
MUX_DIN[enum: CLB_MUX_CTRL]
MUX_SR[enum: CLB_MUX_CTRL]
MUX_EC[enum: CLB_MUX_CTRL]
MUX_X[enum: CLB_MUX_X]
MUX_Y[enum: CLB_MUX_Y]
MUX_XQ[enum: CLB_MUX_XQ]
MUX_YQ[enum: CLB_MUX_YQ]
MUX_DX[enum: CLB_MUX_D]
MUX_DY[enum: CLB_MUX_D]
FFX_SRVAL bit 0!MAIN[11][4]
FFY_SRVAL bit 0!MAIN[9][5]
FFX_EC_ENABLE!MAIN[13][5]
FFY_EC_ENABLE!MAIN[7][5]
FFX_SR_ENABLE!MAIN[11][5]
FFY_SR_ENABLE!MAIN[8][5]
FFX_CLK_INV!MAIN[16][5]
FFY_CLK_INV!MAIN[15][5]
MUX_CIN[enum: CLB_MUX_CIN]
CARRY_ADDSUB[enum: CLB_CARRY_ADDSUB]
CARRY_FPROP[enum: CLB_CARRY_PROP]
CARRY_FGEN[enum: CLB_CARRY_FGEN]
CARRY_GPROP[enum: CLB_CARRY_PROP]
CARRY_OP2_ENABLE!MAIN[11][3]
READBACK_X bit 0!MAIN[16][4]
READBACK_Y bit 0!MAIN[3][5]
READBACK_XQ bit 0!MAIN[12][5]
READBACK_YQ bit 0!MAIN[8][4]
F_RAM_ENABLE!MAIN[12][2]
G_RAM_ENABLE!MAIN[8][2]
RAM_DIMS[enum: CLB_RAM_DIMS]
RAM_DP_ENABLE!MAIN[2][1]
RAM_SYNC_ENABLE!MAIN[6][1]
RAM_CLK_INV!MAIN[5][1]
MUX_H0[enum: CLB_MUX_H0]
MUX_H2[enum: CLB_MUX_H2]
xc4000e CLB_NE enum CLB_MUX_CTRL
CLB.MUX_H1MAIN[13][4]MAIN[16][3]MAIN[15][3]MAIN[15][4]
C11111
C20011
C30101
C40110
xc4000e CLB_NE enum CLB_MUX_CTRL
CLB.MUX_DINMAIN[17][3]MAIN[19][3]MAIN[18][3]MAIN[17][4]
C10011
C21111
C30101
C40110
xc4000e CLB_NE enum CLB_MUX_CTRL
CLB.MUX_SRMAIN[2][3]MAIN[3][4]MAIN[3][3]MAIN[4][4]
C10011
C20101
C31111
C40110
xc4000e CLB_NE enum CLB_MUX_CTRL
CLB.MUX_ECMAIN[0][4]MAIN[1][4]MAIN[2][4]MAIN[1][3]
C10011
C20101
C30110
C41111
xc4000e CLB_NE enum CLB_MUX_X
CLB.MUX_XMAIN[14][3]
F0
H1
xc4000e CLB_NE enum CLB_MUX_Y
CLB.MUX_YMAIN[5][4]
G0
H1
xc4000e CLB_NE enum CLB_MUX_XQ
CLB.MUX_XQMAIN[20][3]
DIN0
FFX1
xc4000e CLB_NE enum CLB_MUX_YQ
CLB.MUX_YQMAIN[0][3]
EC0
FFY1
xc4000e CLB_NE enum CLB_MUX_D
CLB.MUX_DXMAIN[9][4]MAIN[14][6]MAIN[10][4]MAIN[12][4]
CLB.MUX_DYMAIN[4][5]MAIN[5][5]MAIN[7][4]MAIN[6][4]
F1111
G0011
H0101
DIN0110
xc4000e CLB_NE enum CLB_MUX_CIN
CLB.MUX_CINMAIN[9][0]
COUT_S1
COUT_N0
xc4000e CLB_NE enum CLB_CARRY_ADDSUB
CLB.CARRY_ADDSUBMAIN[11][2]MAIN[12][0]
ADD01
SUB11
ADDSUB10
xc4000e CLB_NE enum CLB_CARRY_PROP
CLB.CARRY_FPROPMAIN[12][3]MAIN[9][2]
CONST_011
CONST_110
XOR01
xc4000e CLB_NE enum CLB_CARRY_FGEN
CLB.CARRY_FGENMAIN[10][0]MAIN[11][0]
F100
F3_INV01
CONST_OP2_ENABLE11
xc4000e CLB_NE enum CLB_CARRY_PROP
CLB.CARRY_GPROPMAIN[8][0]
CONST_11
XOR0
xc4000e CLB_NE enum CLB_RAM_DIMS
CLB.RAM_DIMSMAIN[10][2]
_32X11
_16X20
xc4000e CLB_NE enum CLB_MUX_H0
CLB.MUX_H0MAIN[3][1]
G1
SR0
xc4000e CLB_NE enum CLB_MUX_H2
CLB.MUX_H2MAIN[7][1]
F1
DIN0

Bels TBUF

xc4000e CLB_NE bel TBUF pins
PinDirectionTBUF[0]TBUF[1]
IinCELL.IMUX_TBUF_I[0]CELL.IMUX_TBUF_I[1]
TinCELL.IMUX_TBUF_T[0]CELL.IMUX_TBUF_T[1]
ObidirCELL.LONG_H[2]CELL.LONG_H[3]
xc4000e CLB_NE bel TBUF attribute bits
AttributeTBUF[0]TBUF[1]
DRIVE1!MAIN[22][4]!MAIN[22][6]

Bel wires

xc4000e CLB_NE bel wires
WirePins
CELL.LONG_H[2]TBUF[0].O
CELL.LONG_H[3]TBUF[1].O
CELL.IMUX_CLB_F1CLB.F1
CELL.IMUX_CLB_F4CLB.F4
CELL.IMUX_CLB_G1CLB.G1
CELL.IMUX_CLB_G4CLB.G4
CELL.IMUX_CLB_C1CLB.C1
CELL.IMUX_CLB_C4CLB.C4
CELL.IMUX_CLB_F2_NCLB.F2
CELL.IMUX_CLB_G2_NCLB.G2
CELL.IMUX_CLB_C2_NCLB.C2
CELL.IMUX_CLB_F3_WCLB.F3
CELL.IMUX_CLB_G3_WCLB.G3
CELL.IMUX_CLB_C3_WCLB.C3
CELL.IMUX_CLB_KCLB.K
CELL.IMUX_TBUF_I[0]TBUF[0].I
CELL.IMUX_TBUF_I[1]TBUF[1].I
CELL.IMUX_TBUF_T[0]TBUF[0].T
CELL.IMUX_TBUF_T[1]TBUF[1].T
CELL.OUT_CLB_XCLB.X
CELL.OUT_CLB_XQCLB.XQ
CELL.OUT_CLB_YCLB.Y
CELL.OUT_CLB_YQCLB.YQ

Bitstream

xc4000e CLB_NE rect MAIN
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7] INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7] INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7] INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5] - INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2] INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0] INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0] INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_T[1] bit 0 INT: mux CELL.IMUX_TBUF_T[1] bit 1 INT: mux CELL.IMUX_TBUF_T[1] bit 2 INT: mux CELL.IMUX_TBUF_T[1] bit 3 INT: mux CELL.IMUX_TBUF_T[1] bit 4 INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 3 INT: mux CELL.IMUX_CLB_F2 bit 7 INT: mux CELL.IMUX_CLB_F4 bit 1 INT: mux CELL.IMUX_CLB_F4 bit 2 INT: mux CELL.IMUX_CLB_C4 bit 3 INT: mux CELL.IMUX_CLB_C4 bit 1 INT: mux CELL.IMUX_CLB_G4 bit 7 INT: mux CELL.IMUX_CLB_G4 bit 6 - INT: mux CELL.IMUX_CLB_G2 bit 2 INT: mux CELL.IMUX_CLB_C2 bit 4 INT: mux CELL.IMUX_CLB_C2 bit 2
B8 - INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4] INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6] INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6] - INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2] INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2] - INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0] - INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0] - INT: mux CELL.IMUX_TBUF_T[0] bit 0 INT: mux CELL.IMUX_TBUF_T[0] bit 2 INT: mux CELL.IMUX_TBUF_T[0] bit 3 INT: mux CELL.IMUX_TBUF_T[0] bit 1 INT: mux CELL.IMUX_TBUF_T[0] bit 4 - - - INT: mux CELL.IMUX_CLB_F2 bit 2 INT: mux CELL.IMUX_CLB_F2 bit 4 INT: mux CELL.IMUX_CLB_F4 bit 0 INT: mux CELL.IMUX_CLB_F4 bit 5 INT: mux CELL.IMUX_CLB_C4 bit 6 INT: mux CELL.IMUX_CLB_C4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 0 INT: mux CELL.IMUX_CLB_G2 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 3 INT: mux CELL.IMUX_CLB_C2 bit 0 INT: mux CELL.IMUX_CLB_C2 bit 3
B7 INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5] INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2] INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6] INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6] INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3] INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0] INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3] INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3] INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3] INT: mux CELL.IMUX_TBUF_I[1] bit 4 INT: mux CELL.IMUX_TBUF_I[1] bit 2 INT: mux CELL.IMUX_TBUF_I[1] bit 0 INT: mux CELL.IMUX_TBUF_I[1] bit 1 INT: mux CELL.IMUX_TBUF_I[1] bit 3 INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S INT: mux CELL.IMUX_CLB_F2 bit 1 INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 8 INT: mux CELL.IMUX_CLB_F4 bit 4 INT: mux CELL.IMUX_CLB_C4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 5 INT: mux CELL.IMUX_CLB_G4 bit 2 INT: mux CELL.IMUX_CLB_G4 bit 3 INT: mux CELL.IMUX_CLB_G2 bit 5 INT: mux CELL.IMUX_CLB_G2 bit 7 INT: mux CELL.IMUX_CLB_C2 bit 5 INT: mux CELL.IMUX_CLB_C2 bit 7
B6 INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4] INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4] INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4] INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1] INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0] TBUF[1]: ! DRIVE1 INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0 INT: mux CELL.IMUX_TBUF_I[0] bit 4 INT: mux CELL.IMUX_TBUF_I[0] bit 2 INT: mux CELL.IMUX_TBUF_I[0] bit 0 INT: mux CELL.IMUX_TBUF_I[0] bit 1 INT: mux CELL.IMUX_TBUF_I[0] bit 3 INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_CLB_YQ CLB: MUX_DX bit 2 INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0 INT: mux CELL.IMUX_CLB_F2 bit 0 INT: mux CELL.IMUX_CLB_F2 bit 5 INT: mux CELL.IMUX_CLB_F4 bit 3 INT: mux CELL.IMUX_CLB_F4 bit 6 INT: mux CELL.IMUX_CLB_F4 bit 7 INT: mux CELL.IMUX_CLB_C4 bit 0 INT: mux CELL.IMUX_CLB_C4 bit 4 INT: mux CELL.IMUX_CLB_G4 bit 0 INT: mux CELL.IMUX_CLB_G4 bit 4 INT: mux CELL.IMUX_CLB_G2 bit 1 INT: mux CELL.IMUX_CLB_G2 bit 6 INT: mux CELL.IMUX_CLB_C2 bit 1 INT: mux CELL.IMUX_CLB_C2 bit 6
B5 INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4] INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5] INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5] INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1] INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0] INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0] INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0] INT: mux CELL.IMUX_CLB_K bit 3 INT: mux CELL.IMUX_CLB_K bit 5 INT: mux CELL.IMUX_CLB_K bit 1 INT: mux CELL.IMUX_CLB_K bit 4 CLB: ! FFX_CLK_INV CLB: ! FFY_CLK_INV INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0 CLB: ! FFX_EC_ENABLE CLB: ! READBACK_XQ bit 0 CLB: ! FFX_SR_ENABLE INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_CLB_Y CLB: ! FFY_SRVAL bit 0 CLB: ! FFY_SR_ENABLE CLB: ! FFY_EC_ENABLE INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_CLB_YQ CLB: MUX_DY bit 2 CLB: MUX_DY bit 3 CLB: ! READBACK_Y bit 0 INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_CLB_Y INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_CLB_YQ
B4 INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5] INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4] INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3] INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1] INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_CLB_X INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_CLB_XQ TBUF[0]: ! DRIVE1 INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_K bit 6 INT: mux CELL.IMUX_CLB_K bit 2 INT: mux CELL.IMUX_CLB_K bit 0 CLB: MUX_DIN bit 0 CLB: ! READBACK_X bit 0 CLB: MUX_H1 bit 0 INT: mux CELL.IMUX_CLB_K bit 7 CLB: MUX_H1 bit 3 CLB: MUX_DX bit 0 CLB: ! FFX_SRVAL bit 0 CLB: MUX_DX bit 1 CLB: MUX_DX bit 3 CLB: ! READBACK_YQ bit 0 CLB: MUX_DY bit 1 CLB: MUX_DY bit 0 CLB: MUX_Y bit 0 CLB: MUX_SR bit 0 CLB: MUX_SR bit 2 CLB: MUX_EC bit 1 CLB: MUX_EC bit 2 CLB: MUX_EC bit 3
B3 INT: mux CELL.IMUX_CLB_F3 bit 0 INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_CLB_XQ INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E INT: mux CELL.IMUX_CLB_C3 bit 1 INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5] INT: mux CELL.IMUX_CLB_G3 bit 1 INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1] INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1] INT: mux CELL.IMUX_CLB_F1 bit 4 INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1] INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0] INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1] INT: mux CELL.IMUX_CLB_C1 bit 7 INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4] INT: mux CELL.IMUX_CLB_G1 bit 7 CLB: MUX_XQ bit 0 CLB: MUX_DIN bit 2 CLB: MUX_DIN bit 1 CLB: MUX_DIN bit 3 CLB: MUX_H1 bit 2 CLB: MUX_H1 bit 1 CLB: MUX_X bit 0 CLB: ! H bit 7 CLB: CARRY_FPROP bit 1 CLB: ! CARRY_OP2_ENABLE CLB: ! H bit 6 CLB: ! H bit 4 CLB: ! H bit 5 CLB: ! H bit 1 CLB: ! H bit 0 CLB: ! H bit 2 CLB: ! H bit 3 CLB: MUX_SR bit 1 CLB: MUX_SR bit 3 CLB: MUX_EC bit 0 CLB: MUX_YQ bit 0
B2 INT: mux CELL.IMUX_CLB_F3 bit 2 INT: mux CELL.IMUX_CLB_F3 bit 6 INT: mux CELL.IMUX_CLB_F3 bit 8 INT: mux CELL.IMUX_CLB_C3 bit 2 INT: mux CELL.IMUX_CLB_C3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 2 INT: mux CELL.IMUX_CLB_G3 bit 5 INT: mux CELL.IMUX_CLB_G3 bit 8 INT: mux CELL.IMUX_CLB_F1 bit 1 INT: mux CELL.IMUX_CLB_F1 bit 8 INT: mux CELL.IMUX_CLB_C1 bit 2 INT: mux CELL.IMUX_CLB_C1 bit 1 INT: mux CELL.IMUX_CLB_C1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 0 INT: mux CELL.IMUX_CLB_G1 bit 1 CLB: ! F bit 4 CLB: ! F bit 6 CLB: ! F bit 12 CLB: ! F bit 14 CLB: ! F bit 5 CLB: ! F bit 7 CLB: ! F bit 13 CLB: ! F bit 15 CLB: ! F_RAM_ENABLE CLB: CARRY_ADDSUB bit 1 CLB: RAM_DIMS bit 0 CLB: CARRY_FPROP bit 0 CLB: ! G_RAM_ENABLE CLB: ! G bit 6 CLB: ! G bit 14 CLB: ! G bit 4 CLB: ! G bit 12 CLB: ! G bit 2 CLB: ! G bit 10 CLB: ! G bit 0 CLB: ! G bit 8
B1 INT: mux CELL.IMUX_CLB_F3 bit 5 INT: mux CELL.IMUX_CLB_F3 bit 3 INT: mux CELL.IMUX_CLB_C3 bit 0 INT: mux CELL.IMUX_CLB_C3 bit 5 INT: mux CELL.IMUX_CLB_C3 bit 6 INT: mux CELL.IMUX_CLB_G3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 3 INT: mux CELL.IMUX_CLB_G3 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 6 INT: mux CELL.IMUX_CLB_F1 bit 3 INT: mux CELL.IMUX_CLB_C1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 3 INT: mux CELL.IMUX_CLB_G1 bit 5 INT: mux CELL.IMUX_CLB_G1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 3 - - - - - - - - - - - - - CLB: MUX_H2 bit 0 CLB: ! RAM_SYNC_ENABLE CLB: ! RAM_CLK_INV - CLB: MUX_H0 bit 0 CLB: ! RAM_DP_ENABLE - -
B0 INT: mux CELL.IMUX_CLB_F3 bit 7 INT: mux CELL.IMUX_CLB_F3 bit 1 INT: mux CELL.IMUX_CLB_F3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 4 INT: mux CELL.IMUX_CLB_C3 bit 7 INT: mux CELL.IMUX_CLB_G3 bit 4 INT: mux CELL.IMUX_CLB_G3 bit 9 INT: mux CELL.IMUX_CLB_F1 bit 7 INT: mux CELL.IMUX_CLB_F1 bit 2 INT: mux CELL.IMUX_CLB_F1 bit 5 INT: mux CELL.IMUX_CLB_C1 bit 0 INT: mux CELL.IMUX_CLB_C1 bit 4 INT: mux CELL.IMUX_CLB_G1 bit 6 INT: mux CELL.IMUX_CLB_G1 bit 2 INT: mux CELL.IMUX_CLB_G1 bit 8 CLB: ! F bit 2 CLB: ! F bit 0 CLB: ! F bit 10 CLB: ! F bit 8 CLB: ! F bit 3 CLB: ! F bit 1 CLB: ! F bit 11 CLB: ! F bit 9 CLB: CARRY_ADDSUB bit 0 CLB: CARRY_FGEN bit 0 CLB: CARRY_FGEN bit 1 CLB: MUX_CIN bit 0 CLB: CARRY_GPROP bit 0 CLB: ! G bit 15 CLB: ! G bit 7 CLB: ! G bit 13 CLB: ! G bit 5 CLB: ! G bit 11 CLB: ! G bit 3 CLB: ! G bit 9 CLB: ! G bit 1
xc4000e CLB_NE rect MAIN_S
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2] - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1] - - - INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2] - INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0] - INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1] - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_NE rect MAIN_W
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT: mux CELL.IMUX_CLB_F1 bit 0 INT: mux CELL.IMUX_CLB_G3 bit 0
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_NE rect MAIN_N
BitFrame
F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
xc4000e CLB_NE rect MAIN_E
BitFrame
F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -