Corners

Tile CNR.BL

Cells: 2 IRIs: 0

Muxes

xc4000ex CNR.BL muxes
Destination	Sources
TCELL0:SINGLE.H0	TCELL0:IO.DOUBLE.0.S.0, TCELL0:IO.DOUBLE.0.W.2, TCELL0:DEC.V3, TCELL0:OUT.LR.IOB1.I2.S
TCELL0:SINGLE.H1	TCELL0:IO.DOUBLE.0.W.1, TCELL0:LONG.IO.V0, TCELL0:OUT.RDBK.DATA
TCELL0:SINGLE.H2	TCELL0:IO.DOUBLE.1.S.0, TCELL0:IO.DOUBLE.1.W.2, TCELL0:LONG.IO.V1, TCELL0:OUT.MD0.I
TCELL0:SINGLE.H3	TCELL0:IO.DOUBLE.1.W.1, TCELL0:DEC.V2, TCELL0:OUT.LR.IOB1.I1.S
TCELL0:SINGLE.H4	TCELL0:IO.DOUBLE.2.S.0, TCELL0:IO.DOUBLE.2.W.2, TCELL0:DEC.V1, TCELL0:OUT.LR.IOB1.I2.S
TCELL0:SINGLE.H5	TCELL0:IO.DOUBLE.2.W.1, TCELL0:LONG.IO.V2, TCELL0:OUT.RDBK.DATA
TCELL0:SINGLE.H6	TCELL0:IO.DOUBLE.3.S.0, TCELL0:IO.DOUBLE.3.W.2, TCELL0:LONG.IO.V3, TCELL0:OUT.MD0.I
TCELL0:SINGLE.H7	TCELL0:IO.DOUBLE.3.W.1, TCELL0:DEC.V0, TCELL0:OUT.LR.IOB1.I1.S
TCELL0:DOUBLE.H0.0	TCELL0:IO.DOUBLE.0.S.0, TCELL0:IO.DOUBLE.0.W.1, TCELL0:IO.DOUBLE.0.W.2, TCELL0:OUT.LR.IOB1.I1.S
TCELL0:DOUBLE.H0.1	TCELL0:IO.DOUBLE.1.S.0, TCELL0:IO.DOUBLE.1.W.1, TCELL0:IO.DOUBLE.1.W.2, TCELL0:OUT.MD0.I
TCELL0:DOUBLE.H1.0	TCELL0:IO.DOUBLE.3.S.0, TCELL0:IO.DOUBLE.3.W.1, TCELL0:IO.DOUBLE.3.W.2, TCELL0:OUT.RDBK.DATA
TCELL0:DOUBLE.H1.1	TCELL0:IO.DOUBLE.2.S.0, TCELL0:IO.DOUBLE.2.W.1, TCELL0:IO.DOUBLE.2.W.2, TCELL0:OUT.LR.IOB1.I2.S
TCELL0:IO.DOUBLE.0.S.0	TCELL0:SINGLE.H0, TCELL0:DOUBLE.H0.0, TCELL0:IO.DOUBLE.0.W.2, TCELL0:IO.DBUF.V1
TCELL0:IO.DOUBLE.0.W.1	TCELL0:SINGLE.H1, TCELL0:DOUBLE.H0.0, TCELL0:QUAD.H0.1
TCELL0:IO.DOUBLE.0.W.2	TCELL0:SINGLE.H0, TCELL0:DOUBLE.H0.0, TCELL0:IO.DOUBLE.0.S.0, TCELL0:IO.DBUF.V0, TCELL0:QUAD.H0.2
TCELL0:IO.DOUBLE.1.S.0	TCELL0:SINGLE.H2, TCELL0:DOUBLE.H0.1, TCELL0:IO.DOUBLE.1.W.2, TCELL0:IO.DBUF.V1
TCELL0:IO.DOUBLE.1.W.1	TCELL0:SINGLE.H3, TCELL0:DOUBLE.H0.1, TCELL0:QUAD.H1.2
TCELL0:IO.DOUBLE.1.W.2	TCELL0:SINGLE.H2, TCELL0:DOUBLE.H0.1, TCELL0:IO.DOUBLE.1.S.0, TCELL0:IO.DBUF.V0, TCELL0:QUAD.H0.0
TCELL0:IO.DOUBLE.2.S.0	TCELL0:SINGLE.H4, TCELL0:DOUBLE.H1.1, TCELL0:IO.DOUBLE.2.W.2, TCELL0:IO.DBUF.V1
TCELL0:IO.DOUBLE.2.W.1	TCELL0:SINGLE.H5, TCELL0:DOUBLE.H1.1, TCELL0:QUAD.H2.2
TCELL0:IO.DOUBLE.2.W.2	TCELL0:SINGLE.H4, TCELL0:DOUBLE.H1.1, TCELL0:IO.DOUBLE.2.S.0, TCELL0:IO.DBUF.V0, TCELL0:QUAD.H1.1
TCELL0:IO.DOUBLE.3.S.0	TCELL0:SINGLE.H6, TCELL0:DOUBLE.H1.0, TCELL0:IO.DOUBLE.3.W.2, TCELL0:IO.DBUF.V1
TCELL0:IO.DOUBLE.3.W.1	TCELL0:SINGLE.H7, TCELL0:DOUBLE.H1.0, TCELL0:QUAD.H2.0
TCELL0:IO.DOUBLE.3.W.2	TCELL0:SINGLE.H6, TCELL0:DOUBLE.H1.0, TCELL0:IO.DOUBLE.3.S.0, TCELL0:IO.DBUF.V0, TCELL0:QUAD.H2.1
TCELL0:IO.DBUF.V0	TCELL0:IO.DOUBLE.0.S.0, TCELL0:IO.DOUBLE.1.S.0, TCELL0:IO.DOUBLE.2.S.0, TCELL0:IO.DOUBLE.3.S.0
TCELL0:IO.DBUF.V1	TCELL0:IO.DOUBLE.0.W.2, TCELL0:IO.DOUBLE.1.W.2, TCELL0:IO.DOUBLE.2.W.2, TCELL0:IO.DOUBLE.3.W.2
TCELL0:QUAD.H0.0	TCELL0:IO.DOUBLE.1.W.2
TCELL0:QUAD.H0.1	TCELL0:IO.DOUBLE.0.W.1
TCELL0:QUAD.H0.2	TCELL0:IO.DOUBLE.0.W.2, TCELL0:DEC.V0
TCELL0:QUAD.H0.3	TCELL0:LONG.IO.V3, TCELL0:OUT.LR.IOB1.I2.S
TCELL0:QUAD.H1.0	TCELL0:OUT.LR.IOB1.I1.S
TCELL0:QUAD.H1.1	TCELL0:IO.DOUBLE.2.W.2
TCELL0:QUAD.H1.2	TCELL0:IO.DOUBLE.1.W.1, TCELL0:DEC.V1
TCELL0:QUAD.H1.3	TCELL0:LONG.IO.V2
TCELL0:QUAD.H2.0	TCELL0:IO.DOUBLE.3.W.1, TCELL0:OUT.LR.IOB1.I2.S
TCELL0:QUAD.H2.1	TCELL0:IO.DOUBLE.3.W.2
TCELL0:QUAD.H2.2	TCELL0:IO.DOUBLE.2.W.1, TCELL0:DEC.V2
TCELL0:QUAD.H2.3	TCELL0:LONG.IO.V1, TCELL0:OUT.LR.IOB1.I1.S
TCELL0:LONG.H3	TCELL0:LONG.IO.V1, TCELL0:DEC.V1
TCELL0:LONG.H4	TCELL0:LONG.IO.V2, TCELL0:DEC.V2, TCELL0:OUT.RDBK.DATA
TCELL0:LONG.H5	TCELL0:LONG.IO.V3, TCELL0:DEC.V3, TCELL0:OUT.RDBK.DATA
TCELL0:LONG.IO.H0	TCELL0:LONG.IO.V0, TCELL0:LONG.IO.V2
TCELL0:LONG.IO.H1	TCELL0:LONG.IO.V1, TCELL0:LONG.IO.V3
TCELL0:LONG.IO.H2	TCELL0:LONG.IO.V0, TCELL0:LONG.IO.V2
TCELL0:LONG.IO.H3	TCELL0:LONG.IO.V1, TCELL0:LONG.IO.V3
TCELL0:LONG.IO.V0	TCELL0:SINGLE.H1, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.H2
TCELL0:LONG.IO.V1	TCELL0:SINGLE.H2, TCELL0:QUAD.H2.3, TCELL0:LONG.H3, TCELL0:LONG.IO.H1, TCELL0:LONG.IO.H3
TCELL0:LONG.IO.V2	TCELL0:SINGLE.H5, TCELL0:QUAD.H1.3, TCELL0:LONG.H4, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.H2
TCELL0:LONG.IO.V3	TCELL0:SINGLE.H6, TCELL0:QUAD.H0.3, TCELL0:LONG.H5, TCELL0:LONG.IO.H1, TCELL0:LONG.IO.H3
TCELL0:ECLK.V	TCELL0:SINGLE.H2, TCELL0:SINGLE.H3, TCELL0:SINGLE.H4, TCELL0:SINGLE.H5, TCELL0:IO.DOUBLE.3.W.2, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.H1, TCELL0:LONG.IO.H3, TCELL0:OUT.BUFGE.H
TCELL0:BUFGE.H	TCELL0:OUT.BUFGE.H
TCELL0:BUFGE.V0	TCELL0:OUT.BUFGE.V
TCELL0:IMUX.CLB.F2	TCELL1:LONG.V7, TCELL1:LONG.V8, TCELL1:LONG.V9, TCELL1:GCLK7
TCELL0:IMUX.CLB.G2	TCELL1:LONG.V6, TCELL1:LONG.V8, TCELL1:LONG.V9, TCELL1:GCLK7
TCELL0:IMUX.CLB.C2	TCELL1:LONG.V1, TCELL1:LONG.V5, TCELL1:LONG.V7, TCELL1:LONG.V8, TCELL1:GCLK6
TCELL0:IMUX.IOB1.O1	TCELL0:SINGLE.H2, TCELL0:SINGLE.H3, TCELL0:SINGLE.H4, TCELL0:SINGLE.H5, TCELL1:DOUBLE.V0.1, TCELL1:DOUBLE.V1.0, TCELL1:LONG.V0, TCELL1:LONG.V1, TCELL1:LONG.V2
TCELL0:IMUX.IOB1.IK	TCELL0:DOUBLE.H0.0, TCELL0:DOUBLE.H1.1, TCELL0:LONG.H3, TCELL0:LONG.H4, TCELL0:LONG.H5, TCELL1:SINGLE.V2, TCELL1:SINGLE.V3, TCELL1:SINGLE.V4, TCELL1:SINGLE.V5
TCELL0:IMUX.BUFG.H	TCELL0:IO.DOUBLE.0.S.0, TCELL0:IO.DOUBLE.0.W.1, TCELL0:IO.DOUBLE.1.S.0, TCELL0:IO.DOUBLE.1.W.1, TCELL0:IO.DOUBLE.2.S.0, TCELL0:IO.DOUBLE.2.W.1, TCELL0:IO.DOUBLE.3.S.0, TCELL0:IO.DOUBLE.3.W.1, TCELL0:OUT.IOB.CLKIN.W
TCELL0:IMUX.BUFG.V	TCELL0:IO.OCTAL.S.0, TCELL0:IO.OCTAL.S.7, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.V0, TCELL0:OUT.IOB.CLKIN.S
TCELL0:IMUX.RDBK.TRIG	TCELL0:SINGLE.H2, TCELL0:SINGLE.H3, TCELL0:SINGLE.H4, TCELL0:SINGLE.H5

Bel PULLUP_DEC0_H

xc4000ex CNR.BL bel PULLUP_DEC0_H
Pin	Direction	Wires
O	output	TCELL0:DEC.H0

Bel PULLUP_DEC1_H

xc4000ex CNR.BL bel PULLUP_DEC1_H
Pin	Direction	Wires
O	output	TCELL0:DEC.H1

Bel PULLUP_DEC2_H

xc4000ex CNR.BL bel PULLUP_DEC2_H
Pin	Direction	Wires
O	output	TCELL0:DEC.H2

Bel PULLUP_DEC3_H

xc4000ex CNR.BL bel PULLUP_DEC3_H
Pin	Direction	Wires
O	output	TCELL0:DEC.H3

Bel PULLUP_DEC0_V

xc4000ex CNR.BL bel PULLUP_DEC0_V
Pin	Direction	Wires
O	output	TCELL0:DEC.V0

Bel PULLUP_DEC1_V

xc4000ex CNR.BL bel PULLUP_DEC1_V
Pin	Direction	Wires
O	output	TCELL0:DEC.V1

Bel PULLUP_DEC2_V

xc4000ex CNR.BL bel PULLUP_DEC2_V
Pin	Direction	Wires
O	output	TCELL0:DEC.V2

Bel PULLUP_DEC3_V

xc4000ex CNR.BL bel PULLUP_DEC3_V
Pin	Direction	Wires
O	output	TCELL0:DEC.V3

Bel BUFGLS_H

xc4000ex CNR.BL bel BUFGLS_H
Pin	Direction	Wires

Bel BUFGLS_V

xc4000ex CNR.BL bel BUFGLS_V
Pin	Direction	Wires

Bel BUFGE_H

xc4000ex CNR.BL bel BUFGE_H
Pin	Direction	Wires
O	output	TCELL0:OUT.BUFGE.H

Bel BUFGE_V

xc4000ex CNR.BL bel BUFGE_V
Pin	Direction	Wires
O	output	TCELL0:OUT.BUFGE.V

Bel BUFG_H

xc4000ex CNR.BL bel BUFG_H
Pin	Direction	Wires
I	input	TCELL0:IMUX.BUFG.H

Bel BUFG_V

xc4000ex CNR.BL bel BUFG_V
Pin	Direction	Wires
I	input	TCELL0:IMUX.BUFG.V

Bel MD0

xc4000ex CNR.BL bel MD0
Pin	Direction	Wires
I	output	TCELL0:OUT.MD0.I

Bel MD1

xc4000ex CNR.BL bel MD1
Pin	Direction	Wires
O	input	TCELL0:IMUX.IOB1.O1
T	input	TCELL0:IMUX.IOB1.IK

Bel MD2

xc4000ex CNR.BL bel MD2
Pin	Direction	Wires
I	output	TCELL0:OUT.BT.IOB1.I1

Bel RDBK

xc4000ex CNR.BL bel RDBK
Pin	Direction	Wires
DATA	output	TCELL0:OUT.RDBK.DATA
RIP	output	TCELL0:OUT.BT.IOB1.I2
TRIG	input	TCELL0:IMUX.RDBK.TRIG

Bel wires

xc4000ex CNR.BL bel wires
Wire	Pins
TCELL0:DEC.H0	PULLUP_DEC0_H.O
TCELL0:DEC.H1	PULLUP_DEC1_H.O
TCELL0:DEC.H2	PULLUP_DEC2_H.O
TCELL0:DEC.H3	PULLUP_DEC3_H.O
TCELL0:DEC.V0	PULLUP_DEC0_V.O
TCELL0:DEC.V1	PULLUP_DEC1_V.O
TCELL0:DEC.V2	PULLUP_DEC2_V.O
TCELL0:DEC.V3	PULLUP_DEC3_V.O
TCELL0:IMUX.IOB1.O1	MD1.O
TCELL0:IMUX.IOB1.IK	MD1.T
TCELL0:IMUX.BUFG.H	BUFG_H.I
TCELL0:IMUX.BUFG.V	BUFG_V.I
TCELL0:IMUX.RDBK.TRIG	RDBK.TRIG
TCELL0:OUT.BT.IOB1.I1	MD2.I
TCELL0:OUT.BT.IOB1.I2	RDBK.RIP
TCELL0:OUT.MD0.I	MD0.I
TCELL0:OUT.RDBK.DATA	RDBK.DATA
TCELL0:OUT.BUFGE.H	BUFGE_H.O
TCELL0:OUT.BUFGE.V	BUFGE_V.O

Bitstream

xc4000ex CNR.BL bittile 0
Bit	Frame
Bit	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
15	-	-	-	-	-	-	-	-	INT:MUX.IMUX.CLB.C2[2]	INT:MUX.IMUX.CLB.C2[0]	INT:MUX.IMUX.CLB.F2[0]	-	INT:MUX.IMUX.CLB.G2[1]	-	-	~INT:BIPASS.IO.DOUBLE.2.W.1.QUAD.H2.2	~INT:PASS.QUAD.H2.2.0.DEC.V2	~INT:BIPASS.IO.DOUBLE.0.W.2.QUAD.H0.2	~INT:PASS.QUAD.H0.2.0.DEC.V0	~INT:BIPASS.IO.DOUBLE.1.W.1.QUAD.H1.2	~INT:PASS.QUAD.H1.2.0.DEC.V1	~INT:BIPASS.IO.DOUBLE.2.W.2.QUAD.H1.1	~INT:BIPASS.IO.DOUBLE.3.W.2.QUAD.H2.1	~INT:BIPASS.IO.DOUBLE.0.W.1.QUAD.H0.1	~INT:BIPASS.QUAD.H1.3.LONG.IO.V2	-	-
14	-	INT:MUX.ECLK.V[0]	INT:MUX.ECLK.V[1]	-	INT:MUX.ECLK.V[3]	INT:MUX.ECLK.V[4]	INT:MUX.ECLK.V[5]	INT:MUX.IMUX.CLB.C2[1]	INT:MUX.IMUX.CLB.C2[4]	INT:MUX.IMUX.CLB.C2[3]	INT:MUX.IMUX.CLB.F2[1]	INT:MUX.ECLK.V[6]	INT:MUX.IMUX.CLB.G2[0]	INT:MUX.ECLK.V[2]	-	~INT:PASS.QUAD.H1.0.0.OUT.LR.IOB1.I1.S	~INT:BIPASS.QUAD.H2.3.LONG.IO.V1	~INT:PASS.QUAD.H2.3.0.OUT.LR.IOB1.I1.S	~INT:BIPASS.IO.DOUBLE.1.W.2.QUAD.H0.0	-	-	~INT:BIPASS.QUAD.H0.3.LONG.IO.V3	-	~INT:BIPASS.IO.DOUBLE.3.W.1.QUAD.H2.0	~INT:PASS.QUAD.H2.0.0.OUT.LR.IOB1.I2.S	~INT:PASS.QUAD.H0.3.0.OUT.LR.IOB1.I2.S	-
13	-	-	-	-	-	-	-	-	-	~INT:PASS.SINGLE.H3.0.DEC.V2	~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.0	~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.S.0	~INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.W.1	~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.1	~INT:BIPASS.IO.DOUBLE.1.S.0.IO.DOUBLE.1.W.2	~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.2	~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.W.2	~INT:PASS.SINGLE.H7.0.DEC.V0	-	~INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.S.0	~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.S.0	~INT:BIPASS.SINGLE.H7.IO.DOUBLE.3.W.1	~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.W.1	~INT:BIPASS.IO.DOUBLE.3.S.0.IO.DOUBLE.3.W.2	~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.W.2	~INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.W.2	-
12	MD1:PULL[1]	MD1:PULL[0]	~PULLUP_DEC3_V:ENABLE	~PULLUP_DEC1_V:ENABLE	~PULLUP_DEC0_V:ENABLE	~PULLUP_DEC2_V:ENABLE	-	~INT:PASS.SINGLE.H2.0.LONG.IO.V1	INT:MUX.IO.DBUF.V1[2]	INT:MUX.IO.DBUF.V1[1]	INT:MUX.IO.DBUF.V1[0]	-	-	-	-	~INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S	~INT:PASS.IO.DOUBLE.1.W.2.0.IO.DBUF.V0	-	-	-	-	~INT:PASS.DOUBLE.H0.1.0.OUT.MD0.I	~INT:PASS.SINGLE.H6.0.LONG.IO.V3	-	~INT:PASS.SINGLE.H6.0.OUT.MD0.I	~INT:PASS.SINGLE.H7.0.OUT.LR.IOB1.I1.S	-
11	-	~MD1:ENABLE.T	~MD1:ENABLE.O	-	-	-	-	INT:MUX.LONG.H3[0]	-	-	INT:MUX.IO.DBUF.V1[3]	-	-	-	-	INT:MUX.LONG.H5[3]	INT:MUX.LONG.H5[0]	~INT:PASS.IO.DOUBLE.3.W.2.0.IO.DBUF.V0	-	INT:MUX.LONG.H5[1]	-	~INT:PASS.SINGLE.H2.0.OUT.MD0.I	INT:MUX.LONG.H4[1]	~INT:PASS.DOUBLE.H0.0.0.OUT.LR.IOB1.I1.S	INT:MUX.LONG.H4[0]	-	-
10	-	-	-	-	-	-	-	-	-	-	-	-	INT:MUX.LONG.H3[1]	-	-	~INT:PASS.IO.DOUBLE.1.S.0.0.IO.DBUF.V1	-	~INT:PASS.IO.DOUBLE.2.W.2.0.IO.DBUF.V0	-	~INT:PASS.IO.DOUBLE.0.W.2.0.IO.DBUF.V0	INT:MUX.LONG.H5[2]	-	~INT:PASS.IO.DOUBLE.3.S.0.0.IO.DBUF.V1	~INT:PASS.DOUBLE.H1.0.0.OUT.RDBK.DATA	INT:MUX.LONG.H4[3]	INT:MUX.LONG.H4[2]	-
9	-	-	-	-	-	-	-	-	-	-	-	~INT:PASS.SINGLE.H4.0.DEC.V1	~INT:PASS.IO.DOUBLE.2.S.0.0.IO.DBUF.V1	~INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.S.0	~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.S.0	~INT:PASS.IO.DOUBLE.0.S.0.0.IO.DBUF.V1	~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.0	~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.S.0	-	~INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.W.1	~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.1	-	~INT:BIPASS.IO.DOUBLE.0.S.0.IO.DOUBLE.0.W.2	~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.2	-	~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.W.2	-
8	-	-	-	-	-	-	-	-	-	-	-	-	~INT:BIPASS.SINGLE.H5.IO.DOUBLE.2.W.1	~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.W.1	~INT:BIPASS.IO.DOUBLE.2.S.0.IO.DOUBLE.2.W.2	~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.W.2	~INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.W.2	~INT:PASS.SINGLE.H0.0.DEC.V3	-	~INT:PASS.SINGLE.H5.0.LONG.IO.V2	~INT:PASS.SINGLE.H5.0.OUT.RDBK.DATA	~INT:PASS.SINGLE.H1.0.OUT.RDBK.DATA	~INT:PASS.SINGLE.H1.0.LONG.IO.V0	~INT:PASS.DOUBLE.H1.1.0.OUT.LR.IOB1.I2.S	~INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S	~INT:PASS.SINGLE.H4.0.OUT.LR.IOB1.I2.S	-
7	-	-	-	-	-	-	-	-	-	-	-	-	-	INT:MUX.IO.DBUF.V0[1]	INT:MUX.IO.DBUF.V0[0]	INT:MUX.IO.DBUF.V0[2]	INT:MUX.IO.DBUF.V0[3]	-	-	-	-	-	-	INT:MUX.IMUX.IOB1.IK[5]	INT:MUX.IMUX.IOB1.IK[1]	INT:MUX.IMUX.IOB1.IK[4]	-
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INT:MUX.LONG.IO.V3[4]	INT:MUX.LONG.IO.V2[4]	INT:MUX.IMUX.IOB1.IK[0]	INT:MUX.IMUX.IOB1.IK[2]	INT:MUX.IMUX.IOB1.IK[3]	-	-
5	-	-	~RDBK:ENABLE	INT:MUX.LONG.IO.V0[3]	INT:MUX.LONG.IO.V0[1]	INT:MUX.LONG.IO.V0[0]	INT:MUX.LONG.IO.V0[2]	INT:MUX.IMUX.RDBK.TRIG[0]	INT:MUX.IMUX.RDBK.TRIG[1]	INT:MUX.LONG.IO.V1[0]	INT:MUX.LONG.IO.V1[2]	INT:MUX.LONG.IO.V1[1]	INT:MUX.LONG.IO.V1[4]	INT:MUX.LONG.IO.V1[3]	INT:MUX.LONG.IO.V3[0]	INT:MUX.LONG.IO.V3[2]	INT:MUX.LONG.IO.V3[1]	INT:MUX.LONG.IO.V3[3]	INT:MUX.IMUX.IOB1.O1[0]	INT:MUX.IMUX.IOB1.O1[1]	INT:MUX.IMUX.IOB1.O1[3]	INT:MUX.IMUX.IOB1.O1[5]	INT:MUX.LONG.IO.V2[0]	INT:MUX.LONG.IO.V2[2]	INT:MUX.LONG.IO.V2[1]	INT:MUX.LONG.IO.V2[3]	-
4	-	MD0:PULL[1]	MD0:PULL[0]	INT:MUX.IMUX.BUFG.V[0]	INT:MUX.LONG.IO.H1[0]	INT:MUX.IMUX.BUFG.V[5]	INT:MUX.LONG.IO.H1[1]	INT:MUX.IMUX.BUFG.V[2]	INT:MUX.LONG.IO.H3[1]	INT:MUX.LONG.IO.H3[0]	~MISC:READ_ABORT	INT:MUX.LONG.IO.H0[0]	~MISC:READ_CAPTURE	INT:MUX.LONG.IO.H0[1]	INT:MUX.IMUX.BUFG.V[1]	INT:MUX.LONG.IO.H2[1]	INT:MUX.LONG.IO.H2[0]	INT:MUX.IMUX.BUFG.V[3]	~MISC:TM_BOT	INT:MUX.IMUX.RDBK.TRIG[2]	INT:MUX.IMUX.RDBK.TRIG[3]	INT:MUX.IMUX.IOB1.O1[2]	~PULLUP_DEC3_H:ENABLE	~PULLUP_DEC2_H:ENABLE	~PULLUP_DEC1_H:ENABLE	~PULLUP_DEC0_H:ENABLE	-
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INT:MUX.IMUX.BUFG.V[4]	-	INT:MUX.IMUX.IOB1.O1[4]	INT:MUX.IMUX.BUFG.H[0]	INT:MUX.IMUX.BUFG.H[6]	INT:MUX.IMUX.BUFG.H[3]	INT:MUX.IMUX.BUFG.H[4]	-
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MD2:PULL[1]	MD2:PULL[0]	INT:MUX.IMUX.BUFG.H[5]	INT:MUX.IMUX.BUFG.H[2]	INT:MUX.IMUX.BUFG.H[1]	-
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.S.0	0.9.9
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.1	0.6.9
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.2	0.3.9
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.S.0	0.15.13
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.1	0.13.13
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.2	0.11.13
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.S.0	0.6.13
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.W.1	0.4.13
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.W.2	0.2.13
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.S.0	0.12.9
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.W.1	0.13.8
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.W.2	0.11.8
INT:BIPASS.IO.DOUBLE.0.S.0.IO.DOUBLE.0.W.2	0.4.9
INT:BIPASS.IO.DOUBLE.0.W.1.QUAD.H0.1	0.3.15
INT:BIPASS.IO.DOUBLE.0.W.2.QUAD.H0.2	0.9.15
INT:BIPASS.IO.DOUBLE.1.S.0.IO.DOUBLE.1.W.2	0.12.13
INT:BIPASS.IO.DOUBLE.1.W.1.QUAD.H1.2	0.7.15
INT:BIPASS.IO.DOUBLE.1.W.2.QUAD.H0.0	0.8.14
INT:BIPASS.IO.DOUBLE.2.S.0.IO.DOUBLE.2.W.2	0.12.8
INT:BIPASS.IO.DOUBLE.2.W.1.QUAD.H2.2	0.11.15
INT:BIPASS.IO.DOUBLE.2.W.2.QUAD.H1.1	0.5.15
INT:BIPASS.IO.DOUBLE.3.S.0.IO.DOUBLE.3.W.2	0.3.13
INT:BIPASS.IO.DOUBLE.3.W.1.QUAD.H2.0	0.3.14
INT:BIPASS.IO.DOUBLE.3.W.2.QUAD.H2.1	0.4.15
INT:BIPASS.QUAD.H0.3.LONG.IO.V3	0.5.14
INT:BIPASS.QUAD.H1.3.LONG.IO.V2	0.2.15
INT:BIPASS.QUAD.H2.3.LONG.IO.V1	0.10.14
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.0	0.10.9
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.W.2	0.1.9
INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.W.1	0.7.9
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.0	0.16.13
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.W.2	0.10.13
INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.W.1	0.14.13
INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.S.0	0.13.9
INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.W.2	0.10.8
INT:BIPASS.SINGLE.H5.IO.DOUBLE.2.W.1	0.14.8
INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.S.0	0.7.13
INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.W.2	0.1.13
INT:BIPASS.SINGLE.H7.IO.DOUBLE.3.W.1	0.5.13
INT:PASS.DOUBLE.H0.0.0.OUT.LR.IOB1.I1.S	0.3.11
INT:PASS.DOUBLE.H0.1.0.OUT.MD0.I	0.5.12
INT:PASS.DOUBLE.H1.0.0.OUT.RDBK.DATA	0.3.10
INT:PASS.DOUBLE.H1.1.0.OUT.LR.IOB1.I2.S	0.3.8
INT:PASS.IO.DOUBLE.0.S.0.0.IO.DBUF.V1	0.11.9
INT:PASS.IO.DOUBLE.0.W.2.0.IO.DBUF.V0	0.7.10
INT:PASS.IO.DOUBLE.1.S.0.0.IO.DBUF.V1	0.11.10
INT:PASS.IO.DOUBLE.1.W.2.0.IO.DBUF.V0	0.10.12
INT:PASS.IO.DOUBLE.2.S.0.0.IO.DBUF.V1	0.14.9
INT:PASS.IO.DOUBLE.2.W.2.0.IO.DBUF.V0	0.9.10
INT:PASS.IO.DOUBLE.3.S.0.0.IO.DBUF.V1	0.4.10
INT:PASS.IO.DOUBLE.3.W.2.0.IO.DBUF.V0	0.9.11
INT:PASS.QUAD.H0.2.0.DEC.V0	0.8.15
INT:PASS.QUAD.H0.3.0.OUT.LR.IOB1.I2.S	0.1.14
INT:PASS.QUAD.H1.0.0.OUT.LR.IOB1.I1.S	0.11.14
INT:PASS.QUAD.H1.2.0.DEC.V1	0.6.15
INT:PASS.QUAD.H2.0.0.OUT.LR.IOB1.I2.S	0.2.14
INT:PASS.QUAD.H2.2.0.DEC.V2	0.10.15
INT:PASS.QUAD.H2.3.0.OUT.LR.IOB1.I1.S	0.9.14
INT:PASS.SINGLE.H0.0.DEC.V3	0.9.8
INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S	0.2.8
INT:PASS.SINGLE.H1.0.LONG.IO.V0	0.4.8
INT:PASS.SINGLE.H1.0.OUT.RDBK.DATA	0.5.8
INT:PASS.SINGLE.H2.0.LONG.IO.V1	0.19.12
INT:PASS.SINGLE.H2.0.OUT.MD0.I	0.5.11
INT:PASS.SINGLE.H3.0.DEC.V2	0.17.13
INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S	0.11.12
INT:PASS.SINGLE.H4.0.DEC.V1	0.15.9
INT:PASS.SINGLE.H4.0.OUT.LR.IOB1.I2.S	0.1.8
INT:PASS.SINGLE.H5.0.LONG.IO.V2	0.7.8
INT:PASS.SINGLE.H5.0.OUT.RDBK.DATA	0.6.8
INT:PASS.SINGLE.H6.0.LONG.IO.V3	0.4.12
INT:PASS.SINGLE.H6.0.OUT.MD0.I	0.2.12
INT:PASS.SINGLE.H7.0.DEC.V0	0.9.13
INT:PASS.SINGLE.H7.0.OUT.LR.IOB1.I1.S	0.1.12
MD1:ENABLE.O	0.24.11
MD1:ENABLE.T	0.25.11
MISC:READ_ABORT	0.16.4
MISC:READ_CAPTURE	0.14.4
MISC:TM_BOT	0.8.4
PULLUP_DEC0_H:ENABLE	0.1.4
PULLUP_DEC0_V:ENABLE	0.22.12
PULLUP_DEC1_H:ENABLE	0.2.4
PULLUP_DEC1_V:ENABLE	0.23.12
PULLUP_DEC2_H:ENABLE	0.3.4
PULLUP_DEC2_V:ENABLE	0.21.12
PULLUP_DEC3_H:ENABLE	0.4.4
PULLUP_DEC3_V:ENABLE	0.24.12
RDBK:ENABLE	0.24.5
inverted	~[0]

INT:MUX.ECLK.V	0.15.14	0.20.14	0.21.14	0.22.14	0.13.14	0.24.14	0.25.14
0.LONG.IO.H0	0	0	1	1	0	0	1
0.SINGLE.H2	0	0	1	1	1	1	1
0.LONG.IO.H1	0	1	0	1	0	0	1
0.SINGLE.H3	0	1	0	1	1	1	1
0.LONG.IO.H3	0	1	1	0	0	0	1
0.SINGLE.H4	0	1	1	0	1	1	1
0.OUT.BUFGE.H	0	1	1	1	0	1	0
0.IO.DOUBLE.3.W.2	1	1	1	1	0	0	1
0.SINGLE.H5	1	1	1	1	1	1	1

INT:MUX.IMUX.BUFG.H	0.3.3	0.3.2	0.1.3	0.2.3	0.2.2	0.1.2	0.4.3
0.IO.DOUBLE.0.S.0	0	0	0	0	1	1	1
0.IO.DOUBLE.1.S.0	0	0	0	1	0	1	1
0.IO.DOUBLE.2.S.0	0	0	0	1	1	0	1
0.IO.DOUBLE.0.W.1	0	0	1	1	1	1	1
0.IO.DOUBLE.2.W.1	0	1	0	0	1	1	1
0.IO.DOUBLE.3.S.0	0	1	0	1	0	1	1
0.IO.DOUBLE.3.W.1	0	1	0	1	1	0	1
0.IO.DOUBLE.1.W.1	0	1	1	1	1	1	1
0.OUT.IOB.CLKIN.W	1	1	0	1	1	1	0
NONE	1	1	0	1	1	1	1

INT:MUX.IMUX.BUFG.V	0.21.4	0.7.3	0.9.4	0.19.4	0.12.4	0.23.4
0.IO.OCTAL.S.0	0	0	0	1	1	1
0.LONG.IO.H0	0	0	1	0	1	1
0.LONG.IO.V0	0	0	1	1	0	1
0.IO.OCTAL.S.7	0	1	1	1	1	1
0.OUT.IOB.CLKIN.S	1	0	1	1	1	0
NONE	1	0	1	1	1	1

INT:MUX.IMUX.CLB.C2	0.18.14	0.17.14	0.18.15	0.19.14	0.17.15
1.LONG.V1	0	1	1	1	1
1.LONG.V5	1	0	1	1	1
1.LONG.V7	1	1	0	1	1
1.LONG.V8	1	1	1	0	1
1.GCLK6	1	1	1	1	0
NONE	1	1	1	1	1

INT:MUX.IMUX.CLB.F2	0.16.14	0.16.15
1.LONG.V7	0	0
1.LONG.V8	0	1
1.LONG.V9	1	0
1.GCLK7	1	1

INT:MUX.IMUX.CLB.G2	0.14.15	0.14.14
1.LONG.V6	0	0
1.LONG.V8	0	1
1.GCLK7	1	0
1.LONG.V9	1	1

INT:MUX.IMUX.IOB1.IK	0.3.7	0.1.7	0.2.6	0.3.6	0.2.7	0.4.6
0.LONG.H3	0	0	0	1	1	1
0.LONG.H4	0	0	1	0	1	1
0.LONG.H5	0	0	1	1	0	1
0.DOUBLE.H0.0	0	1	1	1	1	1
1.SINGLE.V2	1	0	0	1	1	1
1.SINGLE.V3	1	0	1	0	1	1
1.SINGLE.V4	1	0	1	1	0	1
1.SINGLE.V5	1	0	1	1	1	0
0.DOUBLE.H1.1	1	1	1	1	1	1

INT:MUX.IMUX.IOB1.O1	0.5.5	0.5.3	0.6.5	0.5.4	0.7.5	0.8.5
1.LONG.V0	0	0	1	1	1	0
0.SINGLE.H2	0	0	1	1	1	1
1.LONG.V1	0	1	0	1	1	0
0.SINGLE.H3	0	1	0	1	1	1
1.LONG.V2	0	1	1	0	1	0
0.SINGLE.H4	0	1	1	0	1	1
0.SINGLE.H5	0	1	1	1	0	1
1.DOUBLE.V1.0	1	1	1	1	1	0
1.DOUBLE.V0.1	1	1	1	1	1	1

INT:MUX.IMUX.RDBK.TRIG	0.6.4	0.7.4	0.18.5	0.19.5
0.SINGLE.H3	0	0	1	1
0.SINGLE.H4	0	1	0	1
0.SINGLE.H5	0	1	1	0
0.SINGLE.H2	1	1	1	1

INT:MUX.IO.DBUF.V0	0.10.7	0.11.7	0.13.7	0.12.7
0.IO.DOUBLE.1.S.0	0	0	1	1
0.IO.DOUBLE.2.S.0	0	1	0	1
0.IO.DOUBLE.3.S.0	0	1	1	0
0.IO.DOUBLE.0.S.0	1	1	1	1

INT:MUX.IO.DBUF.V1	0.16.11	0.18.12	0.17.12	0.16.12
0.IO.DOUBLE.0.W.2	0	0	1	1
0.IO.DOUBLE.1.W.2	0	1	0	1
0.IO.DOUBLE.3.W.2	0	1	1	0
0.IO.DOUBLE.2.W.2	1	1	1	1

INT:MUX.LONG.H3	0.14.10	0.19.11
0.DEC.V1	0	0
0.LONG.IO.V1	0	1
NONE	1	1

INT:MUX.LONG.H4	0.2.10	0.1.10	0.4.11	0.2.11
0.LONG.IO.V2	0	0	0	1
0.DEC.V2	0	0	1	0
0.OUT.RDBK.DATA	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.H5	0.11.11	0.6.10	0.7.11	0.10.11
0.LONG.IO.V3	0	0	0	1
0.DEC.V3	0	0	1	0
0.OUT.RDBK.DATA	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.IO.H0	0.13.4	0.15.4
0.LONG.IO.V2	0	0
0.LONG.IO.V0	0	1
NONE	1	1

INT:MUX.LONG.IO.H1	0.20.4	0.22.4
0.LONG.IO.V3	0	0
0.LONG.IO.V1	0	1
NONE	1	1

INT:MUX.LONG.IO.H2	0.11.4	0.10.4
0.LONG.IO.V0	0	0
0.LONG.IO.V2	0	1
NONE	1	1

INT:MUX.LONG.IO.H3	0.18.4	0.17.4
0.LONG.IO.V1	0	0
0.LONG.IO.V3	0	1
NONE	1	1

INT:MUX.LONG.IO.V0	0.23.5	0.20.5	0.22.5	0.21.5
0.LONG.IO.H0	0	0	0	1
0.LONG.IO.H2	0	0	1	0
0.SINGLE.H1	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.IO.V1	0.14.5	0.13.5	0.16.5	0.15.5	0.17.5
0.LONG.H3	0	0	0	1	1
0.LONG.IO.H1	0	0	1	0	1
0.LONG.IO.H3	0	0	1	1	0
0.SINGLE.H2	0	1	1	1	1
NONE	1	1	1	1	1

INT:MUX.LONG.IO.V2	0.5.6	0.1.5	0.3.5	0.2.5	0.4.5
0.LONG.H4	0	0	0	1	1
0.LONG.IO.H0	0	0	1	0	1
0.LONG.IO.H2	0	0	1	1	0
0.SINGLE.H5	0	1	1	1	1
NONE	1	1	1	1	1

INT:MUX.LONG.IO.V3	0.6.6	0.9.5	0.11.5	0.10.5	0.12.5
0.LONG.H5	0	0	0	1	1
0.LONG.IO.H1	0	0	1	0	1
0.LONG.IO.H3	0	0	1	1	0
0.SINGLE.H6	0	1	1	1	1
NONE	1	1	1	1	1

MD0:PULL	0.25.4	0.24.4
MD1:PULL	0.26.12	0.25.12
MD2:PULL	0.5.2	0.4.2
PULLUP	0	1
PULLDOWN	1	0
PULLNONE	1	1

Tile CNR.TL

Cells: 4 IRIs: 0

Muxes

xc4000ex CNR.TL muxes
Destination	Sources
TCELL0:LONG.H0	TCELL0:LONG.IO.V0, TCELL0:DEC.V0, TCELL0:OUT.LR.IOB1.I2
TCELL0:LONG.H1	TCELL0:LONG.IO.V1, TCELL0:DEC.V1, TCELL0:OUT.LR.IOB1.I2
TCELL0:LONG.H2	TCELL0:LONG.IO.V2, TCELL0:DEC.V2
TCELL0:LONG.IO.H0	TCELL0:LONG.IO.V0, TCELL0:LONG.IO.V2
TCELL0:LONG.IO.H1	TCELL0:LONG.IO.V1, TCELL0:LONG.IO.V3
TCELL0:LONG.IO.H2	TCELL0:LONG.IO.V0, TCELL0:LONG.IO.V2
TCELL0:LONG.IO.H3	TCELL0:LONG.IO.V1, TCELL0:LONG.IO.V3
TCELL0:LONG.IO.V0	TCELL0:LONG.H0, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.H2
TCELL0:LONG.IO.V1	TCELL0:LONG.H1, TCELL0:LONG.IO.H1, TCELL0:LONG.IO.H3
TCELL0:LONG.IO.V2	TCELL0:LONG.H2, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.H2
TCELL0:LONG.IO.V3	TCELL0:LONG.IO.H1, TCELL0:LONG.IO.H3
TCELL0:BUFGE.H	TCELL0:OUT.BUFGE.H
TCELL0:BUFGE.V1	TCELL0:OUT.BUFGE.V
TCELL0:IMUX.BUFG.H	TCELL0:IO.DOUBLE.0.N.1, TCELL0:IO.DOUBLE.0.N.2, TCELL0:IO.DOUBLE.1.N.1, TCELL0:IO.DOUBLE.1.N.2, TCELL0:IO.DOUBLE.2.N.1, TCELL0:IO.DOUBLE.2.N.2, TCELL0:IO.DOUBLE.3.N.1, TCELL0:IO.DOUBLE.3.N.2, TCELL0:OUT.IOB.CLKIN.W
TCELL0:IMUX.BUFG.V	TCELL0:IO.OCTAL.W.0, TCELL0:IO.OCTAL.W.7, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.V0, TCELL0:OUT.IOB.CLKIN.N
TCELL0:IMUX.BSCAN.TDO1	TCELL1:DOUBLE.V0.1, TCELL1:DOUBLE.V1.0, TCELL1:LONG.V0, TCELL1:LONG.V1, TCELL1:LONG.V2, TCELL2:SINGLE.H2, TCELL2:SINGLE.H3, TCELL2:SINGLE.H4, TCELL2:SINGLE.H5
TCELL0:IMUX.BSCAN.TDO2	TCELL0:LONG.H0, TCELL0:LONG.H1, TCELL0:LONG.H2, TCELL1:SINGLE.V2, TCELL1:SINGLE.V3, TCELL1:SINGLE.V4, TCELL1:SINGLE.V5, TCELL2:DOUBLE.H0.1, TCELL2:DOUBLE.H1.0

Bel PULLUP_DEC0_H

xc4000ex CNR.TL bel PULLUP_DEC0_H
Pin	Direction	Wires
O	output	TCELL0:DEC.H0

Bel PULLUP_DEC1_H

xc4000ex CNR.TL bel PULLUP_DEC1_H
Pin	Direction	Wires
O	output	TCELL0:DEC.H1

Bel PULLUP_DEC2_H

xc4000ex CNR.TL bel PULLUP_DEC2_H
Pin	Direction	Wires
O	output	TCELL0:DEC.H2

Bel PULLUP_DEC3_H

xc4000ex CNR.TL bel PULLUP_DEC3_H
Pin	Direction	Wires
O	output	TCELL0:DEC.H3

Bel PULLUP_DEC0_V

xc4000ex CNR.TL bel PULLUP_DEC0_V
Pin	Direction	Wires
O	output	TCELL0:DEC.V0

Bel PULLUP_DEC1_V

xc4000ex CNR.TL bel PULLUP_DEC1_V
Pin	Direction	Wires
O	output	TCELL0:DEC.V1

Bel PULLUP_DEC2_V

xc4000ex CNR.TL bel PULLUP_DEC2_V
Pin	Direction	Wires
O	output	TCELL0:DEC.V2

Bel PULLUP_DEC3_V

xc4000ex CNR.TL bel PULLUP_DEC3_V
Pin	Direction	Wires
O	output	TCELL0:DEC.V3

Bel BUFGLS_H

xc4000ex CNR.TL bel BUFGLS_H
Pin	Direction	Wires

Bel BUFGLS_V

xc4000ex CNR.TL bel BUFGLS_V
Pin	Direction	Wires

Bel BUFGE_H

xc4000ex CNR.TL bel BUFGE_H
Pin	Direction	Wires
O	output	TCELL0:OUT.BUFGE.H

Bel BUFGE_V

xc4000ex CNR.TL bel BUFGE_V
Pin	Direction	Wires
O	output	TCELL0:OUT.BUFGE.V

Bel BUFG_H

xc4000ex CNR.TL bel BUFG_H
Pin	Direction	Wires
I	input	TCELL0:IMUX.BUFG.H

Bel BUFG_V

xc4000ex CNR.TL bel BUFG_V
Pin	Direction	Wires
I	input	TCELL0:IMUX.BUFG.V

Bel BSCAN

xc4000ex CNR.TL bel BSCAN
Pin	Direction	Wires
DRCK	output	TCELL0:OUT.BT.IOB1.I2
IDLE	output	TCELL0:OUT.LR.IOB1.I2
SEL1	output	TCELL0:OUT.LR.IOB1.I1
SEL2	output	TCELL0:OUT.BT.IOB1.I1
TDO1	input	TCELL0:IMUX.BSCAN.TDO1
TDO2	input	TCELL0:IMUX.BSCAN.TDO2

Bel wires

xc4000ex CNR.TL bel wires
Wire	Pins
TCELL0:DEC.H0	PULLUP_DEC0_H.O
TCELL0:DEC.H1	PULLUP_DEC1_H.O
TCELL0:DEC.H2	PULLUP_DEC2_H.O
TCELL0:DEC.H3	PULLUP_DEC3_H.O
TCELL0:DEC.V0	PULLUP_DEC0_V.O
TCELL0:DEC.V1	PULLUP_DEC1_V.O
TCELL0:DEC.V2	PULLUP_DEC2_V.O
TCELL0:DEC.V3	PULLUP_DEC3_V.O
TCELL0:IMUX.BUFG.H	BUFG_H.I
TCELL0:IMUX.BUFG.V	BUFG_V.I
TCELL0:IMUX.BSCAN.TDO1	BSCAN.TDO1
TCELL0:IMUX.BSCAN.TDO2	BSCAN.TDO2
TCELL0:OUT.BT.IOB1.I1	BSCAN.SEL2
TCELL0:OUT.BT.IOB1.I2	BSCAN.DRCK
TCELL0:OUT.LR.IOB1.I1	BSCAN.SEL1
TCELL0:OUT.LR.IOB1.I2	BSCAN.IDLE
TCELL0:OUT.BUFGE.H	BUFGE_H.O
TCELL0:OUT.BUFGE.V	BUFGE_V.O

Bitstream

xc4000ex CNR.TL bittile 0
Bit	Frame
Bit	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~MISC:3V	MISC:INPUT[0]	INT:MUX.IMUX.BUFG.H[4]	-
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INT:MUX.IMUX.BUFG.H[5]	INT:MUX.IMUX.BUFG.H[1]	-
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~MISC:TM_TOP	INT:MUX.LONG.IO.H1[1]	INT:MUX.IMUX.BUFG.H[0]	INT:MUX.IMUX.BUFG.H[6]	INT:MUX.IMUX.BUFG.H[2]	INT:MUX.IMUX.BUFG.H[3]	INT:MUX.LONG.IO.H3[1]	-
4	-	-	-	-	-	-	-	BSCAN:ENABLE	INT:MUX.LONG.IO.V3[1]	INT:MUX.LONG.IO.V3[0]	~MISC:TM_LEFT	INT:MUX.LONG.IO.V1[0]	INT:MUX.LONG.IO.V1[1]	INT:MUX.LONG.IO.V1[2]	-	INT:MUX.LONG.IO.V1[3]	~PULLUP_DEC0_H:ENABLE	INT:MUX.LONG.IO.H1[0]	~PULLUP_DEC1_H:ENABLE	INT:MUX.LONG.IO.H3[0]	INT:MUX.IMUX.BSCAN.TDO1[1]	INT:MUX.IMUX.BSCAN.TDO1[5]	INT:MUX.IMUX.BSCAN.TDO1[4]	-
3	-	-	-	MISC:OUTPUT[0]	INT:MUX.LONG.H1[3]	INT:MUX.LONG.H1[1]	INT:MUX.LONG.H1[0]	INT:MUX.LONG.H1[2]	INT:MUX.LONG.H0[0]	INT:MUX.LONG.H0[1]	INT:MUX.LONG.H0[2]	INT:MUX.LONG.H0[3]	-	-	-	-	INT:MUX.LONG.IO.V0[2]	~PULLUP_DEC3_H:ENABLE	~PULLUP_DEC2_H:ENABLE	INT:MUX.IMUX.BSCAN.TDO1[0]	INT:MUX.IMUX.BSCAN.TDO1[3]	INT:MUX.IMUX.BSCAN.TDO1[2]	INT:MUX.LONG.IO.H0[1]	-
2	-	-	-	INT:MUX.IMUX.BUFG.V[0]	INT:MUX.LONG.H2[1]	INT:MUX.LONG.H2[0]	-	INT:MUX.LONG.IO.V2[3]	INT:MUX.LONG.IO.V2[1]	INT:MUX.LONG.IO.V2[0]	INT:MUX.LONG.IO.V2[2]	INT:MUX.LONG.IO.V0[0]	INT:MUX.LONG.IO.V0[1]	INT:MUX.LONG.IO.V0[3]	-	-	INT:MUX.LONG.IO.H2[1]	INT:MUX.LONG.IO.H2[0]	-	INT:MUX.LONG.IO.H0[0]	INT:MUX.IMUX.BSCAN.TDO2[4]	INT:MUX.IMUX.BSCAN.TDO2[3]	INT:MUX.IMUX.BSCAN.TDO2[0]	-
1	INT:MUX.IMUX.BUFG.V[5]	INT:MUX.IMUX.BUFG.V[3]	INT:MUX.IMUX.BUFG.V[2]	INT:MUX.IMUX.BUFG.V[1]	INT:MUX.IMUX.BUFG.V[4]	-	-	~PULLUP_DEC3_V:ENABLE	-	-	-	-	~PULLUP_DEC1_V:ENABLE	~PULLUP_DEC2_V:ENABLE	~PULLUP_DEC0_V:ENABLE	-	-	-	-	-	INT:MUX.IMUX.BSCAN.TDO2[2]	INT:MUX.IMUX.BSCAN.TDO2[1]	INT:MUX.IMUX.BSCAN.TDO2[5]	-
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

BSCAN:ENABLE	0.16.4
non-inverted	[0]

INT:MUX.IMUX.BSCAN.TDO1	0.2.4	0.1.4	0.3.3	0.2.3	0.3.4	0.4.3
1.LONG.V0	0	0	0	1	1	1
1.LONG.V1	0	0	1	0	1	1
1.LONG.V2	0	0	1	1	0	1
1.DOUBLE.V1.0	0	1	1	1	1	1
2.SINGLE.H2	1	0	0	1	1	1
2.SINGLE.H3	1	0	1	0	1	1
2.SINGLE.H4	1	0	1	1	0	1
2.SINGLE.H5	1	0	1	1	1	0
1.DOUBLE.V0.1	1	1	1	1	1	1

INT:MUX.IMUX.BSCAN.TDO2	0.1.1	0.3.2	0.2.2	0.3.1	0.2.1	0.1.2
0.LONG.H0	0	0	0	1	1	1
0.LONG.H1	0	0	1	0	1	1
0.LONG.H2	0	0	1	1	0	1
1.SINGLE.V2	0	1	0	1	1	1
1.SINGLE.V3	0	1	1	0	1	1
1.SINGLE.V4	0	1	1	1	0	1
1.SINGLE.V5	0	1	1	1	1	0
2.DOUBLE.H1.0	1	0	1	1	1	1
2.DOUBLE.H0.1	1	1	1	1	1	1

INT:MUX.IMUX.BUFG.H	0.4.5	0.2.6	0.1.7	0.2.5	0.3.5	0.1.6	0.5.5
0.IO.DOUBLE.0.N.1	0	0	0	0	1	1	1
0.IO.DOUBLE.1.N.1	0	0	0	1	0	1	1
0.IO.DOUBLE.2.N.1	0	0	0	1	1	0	1
0.IO.DOUBLE.0.N.2	0	0	1	1	1	1	1
0.IO.DOUBLE.2.N.2	0	1	0	0	1	1	1
0.IO.DOUBLE.3.N.1	0	1	0	1	0	1	1
0.IO.DOUBLE.3.N.2	0	1	0	1	1	0	1
0.IO.DOUBLE.1.N.2	0	1	1	1	1	1	1
0.OUT.IOB.CLKIN.W	1	1	0	1	1	1	0
NONE	1	1	0	1	1	1	1

INT:MUX.IMUX.BUFG.V	0.23.1	0.19.1	0.22.1	0.21.1	0.20.1	0.20.2
0.IO.OCTAL.W.0	0	0	0	1	1	1
0.IO.OCTAL.W.7	0	0	1	0	1	1
0.LONG.IO.V0	0	0	1	1	0	1
0.LONG.IO.H0	0	1	1	1	1	1
0.OUT.IOB.CLKIN.N	1	0	1	1	1	0
NONE	1	0	1	1	1	1

INT:MUX.LONG.H0	0.12.3	0.13.3	0.14.3	0.15.3
0.LONG.IO.V0	0	0	0	1
0.DEC.V0	0	0	1	0
0.OUT.LR.IOB1.I2	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.H1	0.19.3	0.16.3	0.18.3	0.17.3
0.LONG.IO.V1	0	0	0	1
0.DEC.V1	0	0	1	0
0.OUT.LR.IOB1.I2	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.H2	0.19.2	0.18.2
0.LONG.IO.V2	0	0
0.DEC.V2	0	1
NONE	1	1

INT:MUX.LONG.IO.H0	0.1.3	0.4.2
0.LONG.IO.V2	0	0
0.LONG.IO.V0	0	1
NONE	1	1

INT:MUX.LONG.IO.H1	0.6.5	0.6.4
0.LONG.IO.V3	0	0
0.LONG.IO.V1	0	1
NONE	1	1

INT:MUX.LONG.IO.H2	0.7.2	0.6.2
0.LONG.IO.V0	0	0
0.LONG.IO.V2	0	1
NONE	1	1

INT:MUX.LONG.IO.H3	0.1.5	0.4.4
0.LONG.IO.V1	0	0
0.LONG.IO.V3	0	1
NONE	1	1

INT:MUX.LONG.IO.V0	0.10.2	0.7.3	0.11.2	0.12.2
0.LONG.H0	0	0	0	1
0.LONG.IO.H2	0	0	1	0
0.LONG.IO.H0	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.IO.V1	0.8.4	0.10.4	0.11.4	0.12.4
0.LONG.H1	0	0	0	1
0.LONG.IO.H3	0	0	1	0
0.LONG.IO.H1	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.IO.V2	0.16.2	0.13.2	0.15.2	0.14.2
0.LONG.H2	0	0	0	1
0.LONG.IO.H0	0	0	1	0
0.LONG.IO.H2	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.IO.V3	0.15.4	0.14.4
0.LONG.IO.H1	0	0
0.LONG.IO.H3	0	1
NONE	1	1

MISC:3V	0.3.7
MISC:TM_LEFT	0.13.4
MISC:TM_TOP	0.7.5
PULLUP_DEC0_H:ENABLE	0.7.4
PULLUP_DEC0_V:ENABLE	0.9.1
PULLUP_DEC1_H:ENABLE	0.5.4
PULLUP_DEC1_V:ENABLE	0.11.1
PULLUP_DEC2_H:ENABLE	0.5.3
PULLUP_DEC2_V:ENABLE	0.10.1
PULLUP_DEC3_H:ENABLE	0.6.3
PULLUP_DEC3_V:ENABLE	0.16.1
inverted	~[0]

MISC:INPUT	0.2.7
MISC:OUTPUT	0.20.3
CMOS	0
TTL	1

Tile CNR.BR

Cells: 1 IRIs: 0

Muxes

xc4000ex CNR.BR muxes
Destination	Sources
SINGLE.H0	SINGLE.H0.E, SINGLE.V0, SINGLE.V0.S, IO.DOUBLE.0.E.0, IO.DOUBLE.0.S.1, DEC.V0, OUT.LR.IOB1.I2.S
SINGLE.H0.E	SINGLE.H0, SINGLE.V0, SINGLE.V0.S, QUAD.V0.1, LONG.V6
SINGLE.H1	SINGLE.H1.E, SINGLE.V1, SINGLE.V1.S, IO.DOUBLE.0.E.1, LONG.IO.V0, OUT.STARTUP.Q3
SINGLE.H1.E	SINGLE.H1, SINGLE.V1, SINGLE.V1.S, QUAD.V0.3, LONG.V0
SINGLE.H2	SINGLE.H2.E, SINGLE.V2, SINGLE.V2.S, IO.DOUBLE.1.E.0, IO.DOUBLE.1.S.1, LONG.IO.V1, OUT.STARTUP.Q1Q4
SINGLE.H2.E	SINGLE.H2, SINGLE.V2, SINGLE.V2.S, QUAD.V0.2, LONG.V1
SINGLE.H3	SINGLE.H3.E, SINGLE.V3, SINGLE.V3.S, IO.DOUBLE.1.E.1, DEC.V1, OUT.LR.IOB1.I1.S
SINGLE.H3.E	SINGLE.H3, SINGLE.V3, SINGLE.V3.S, QUAD.V1.0, LONG.V2, LONG.V7
SINGLE.H4	SINGLE.H4.E, SINGLE.V4, SINGLE.V4.S, IO.DOUBLE.2.E.0, IO.DOUBLE.2.S.1, LONG.V3, DEC.V2, OUT.LR.IOB1.I2.S
SINGLE.H4.E	SINGLE.H4, SINGLE.V4, SINGLE.V4.S, QUAD.V2.0, LONG.V8
SINGLE.H5	SINGLE.H5.E, SINGLE.V5, SINGLE.V5.S, IO.DOUBLE.2.E.1, LONG.V4, LONG.IO.V2, OUT.STARTUP.Q3
SINGLE.H5.E	SINGLE.H5, SINGLE.V5, SINGLE.V5.S, QUAD.V1.1
SINGLE.H6	SINGLE.H6.E, SINGLE.V6, SINGLE.V6.S, IO.DOUBLE.3.E.0, IO.DOUBLE.3.S.1, LONG.V5, LONG.IO.V3, OUT.STARTUP.Q1Q4
SINGLE.H6.E	SINGLE.H6, SINGLE.V6, SINGLE.V6.S, QUAD.V2.3
SINGLE.H7	SINGLE.H7.E, SINGLE.V7, SINGLE.V7.S, IO.DOUBLE.3.E.1, DEC.V3, OUT.LR.IOB1.I1.S
SINGLE.H7.E	SINGLE.H7, SINGLE.V7, SINGLE.V7.S, QUAD.V2.2, LONG.V9
SINGLE.V0	GND, SINGLE.H0, SINGLE.H0.E, SINGLE.V0.S, IO.DOUBLE.0.S.1, DEC.H3, OUT.BT.IOB1.I2.E
SINGLE.V0.S	SINGLE.H0, SINGLE.H0.E, SINGLE.V0, QUAD.H0.2
SINGLE.V1	SINGLE.H1, SINGLE.H1.E, SINGLE.V1.S, IO.DOUBLE.0.E.1, IO.DOUBLE.0.S.2, LONG.IO.H0, OUT.STARTUP.DONEIN
SINGLE.V1.S	SINGLE.H1, SINGLE.H1.E, SINGLE.V1, QUAD.H0.0
SINGLE.V2	SINGLE.H2, SINGLE.H2.E, SINGLE.V2.S, IO.DOUBLE.1.S.1, LONG.IO.H1, OUT.STARTUP.Q2
SINGLE.V2.S	SINGLE.H2, SINGLE.H2.E, SINGLE.V2, QUAD.H1.2
SINGLE.V3	SINGLE.H3, SINGLE.H3.E, SINGLE.V3.S, IO.DOUBLE.1.E.1, IO.DOUBLE.1.S.2, DEC.H2, OUT.BT.IOB1.I1.E
SINGLE.V3.S	SINGLE.H3, SINGLE.H3.E, SINGLE.V3, QUAD.H1.1
SINGLE.V4	SINGLE.H4, SINGLE.H4.E, SINGLE.V4.S, IO.DOUBLE.2.S.1, LONG.H3, DEC.H1, OUT.BT.IOB1.I2.E
SINGLE.V4.S	SINGLE.H4, SINGLE.H4.E, SINGLE.V4, QUAD.H1.0
SINGLE.V5	SINGLE.H5, SINGLE.H5.E, SINGLE.V5.S, IO.DOUBLE.2.E.1, IO.DOUBLE.2.S.2, LONG.H4, LONG.IO.H2, OUT.STARTUP.DONEIN
SINGLE.V5.S	SINGLE.H5, SINGLE.H5.E, SINGLE.V5, QUAD.H2.3
SINGLE.V6	SINGLE.H6, SINGLE.H6.E, SINGLE.V6.S, IO.DOUBLE.3.S.1, LONG.H5, LONG.IO.H3, OUT.STARTUP.Q2
SINGLE.V6.S	SINGLE.H6, SINGLE.H6.E, SINGLE.V6, QUAD.H2.2
SINGLE.V7	GND, SINGLE.H7, SINGLE.H7.E, SINGLE.V7.S, IO.DOUBLE.3.E.1, IO.DOUBLE.3.S.2, DEC.H0, OUT.BT.IOB1.I1.E
SINGLE.V7.S	SINGLE.H7, SINGLE.H7.E, SINGLE.V7, QUAD.H2.1
DOUBLE.H0.0	DOUBLE.H0.2, DOUBLE.V0.0, DOUBLE.V0.2, IO.DOUBLE.1.E.0, IO.DOUBLE.1.E.1, IO.DOUBLE.1.S.1, OUT.STARTUP.Q1Q4
DOUBLE.H0.1	IO.DOUBLE.0.E.0, IO.DOUBLE.0.E.1, IO.DOUBLE.0.S.1, OUT.LR.IOB1.I1.S
DOUBLE.H0.2	DOUBLE.H0.0, DOUBLE.V0.0, DOUBLE.V0.2, QUAD.V0.0
DOUBLE.H1.0	DOUBLE.H1.2, DOUBLE.V1.0, DOUBLE.V1.2, IO.DOUBLE.2.E.0, IO.DOUBLE.2.E.1, IO.DOUBLE.2.S.1, OUT.LR.IOB1.I2.S
DOUBLE.H1.1	IO.DOUBLE.3.E.0, IO.DOUBLE.3.E.1, IO.DOUBLE.3.S.1, QUAD.V1.3, OUT.STARTUP.Q3
DOUBLE.H1.2	DOUBLE.H1.0, DOUBLE.V1.0, DOUBLE.V1.2
DOUBLE.V0.0	DOUBLE.H0.0, DOUBLE.H0.2, DOUBLE.V0.2, IO.DOUBLE.1.E.1, IO.DOUBLE.1.S.1, IO.DOUBLE.1.S.2, OUT.BT.IOB1.I1.E
DOUBLE.V0.1	IO.DOUBLE.0.E.1, IO.DOUBLE.0.S.1, IO.DOUBLE.0.S.2, OUT.STARTUP.Q2
DOUBLE.V0.2	DOUBLE.H0.0, DOUBLE.H0.2, DOUBLE.V0.0, QUAD.H0.3
DOUBLE.V1.0	DOUBLE.H1.0, DOUBLE.H1.2, DOUBLE.V1.2, IO.DOUBLE.2.E.1, IO.DOUBLE.2.S.1, IO.DOUBLE.2.S.2, OUT.STARTUP.DONEIN
DOUBLE.V1.1	IO.DOUBLE.3.E.1, IO.DOUBLE.3.S.1, IO.DOUBLE.3.S.2, QUAD.H2.0, OUT.BT.IOB1.I2.E
DOUBLE.V1.2	DOUBLE.H1.0, DOUBLE.H1.2, DOUBLE.V1.0
IO.DOUBLE.0.E.0	SINGLE.H0, DOUBLE.H0.1, IO.DOUBLE.0.S.1, IO.DBUF.V0, QUAD.H0.3
IO.DOUBLE.0.E.1	SINGLE.H1, SINGLE.V1, DOUBLE.H0.1, DOUBLE.V0.1, IO.DOUBLE.0.S.2, IO.DBUF.H1, QUAD.H0.2
IO.DOUBLE.0.S.1	SINGLE.H0, SINGLE.V0, DOUBLE.H0.1, DOUBLE.V0.1, IO.DOUBLE.0.E.0, IO.DBUF.V1, QUAD.V0.2, GCLK4
IO.DOUBLE.0.S.2	SINGLE.V1, DOUBLE.V0.1, IO.DOUBLE.0.E.1, IO.DBUF.H0, QUAD.V0.1, LONG.V9
IO.DOUBLE.1.E.0	SINGLE.H2, DOUBLE.H0.0, IO.DOUBLE.1.S.1, IO.DBUF.V0, QUAD.H0.1
IO.DOUBLE.1.E.1	SINGLE.H3, SINGLE.V3, DOUBLE.H0.0, DOUBLE.V0.0, IO.DOUBLE.1.S.2, IO.DBUF.H1, QUAD.H1.2
IO.DOUBLE.1.S.1	SINGLE.H2, SINGLE.V2, DOUBLE.H0.0, DOUBLE.V0.0, IO.DOUBLE.1.E.0, IO.DBUF.V1, QUAD.V1.1, LONG.V8
IO.DOUBLE.1.S.2	SINGLE.V3, DOUBLE.V0.0, IO.DOUBLE.1.E.1, IO.DBUF.H0, QUAD.V0.3, GCLK5
IO.DOUBLE.2.E.0	SINGLE.H4, DOUBLE.H1.0, IO.DOUBLE.2.S.1, IO.DBUF.V0, QUAD.H1.1
IO.DOUBLE.2.E.1	SINGLE.H5, SINGLE.V5, DOUBLE.H1.0, DOUBLE.V1.0, IO.DOUBLE.2.S.2, IO.DBUF.H1, QUAD.H2.3
IO.DOUBLE.2.S.1	SINGLE.H4, SINGLE.V4, DOUBLE.H1.0, DOUBLE.V1.0, IO.DOUBLE.2.E.0, IO.DBUF.V1, QUAD.V1.3, LONG.V7
IO.DOUBLE.2.S.2	SINGLE.V5, DOUBLE.V1.0, IO.DOUBLE.2.E.1, IO.DBUF.H0, QUAD.V1.2, GCLK6
IO.DOUBLE.3.E.0	SINGLE.H6, DOUBLE.H1.1, IO.DOUBLE.3.S.1, IO.DBUF.V0, QUAD.H2.2
IO.DOUBLE.3.E.1	SINGLE.H7, SINGLE.V7, DOUBLE.H1.1, DOUBLE.V1.1, IO.DOUBLE.3.S.2, IO.DBUF.H1, QUAD.H2.1
IO.DOUBLE.3.S.1	SINGLE.H6, SINGLE.V6, DOUBLE.H1.1, DOUBLE.V1.1, IO.DOUBLE.3.E.0, IO.DBUF.V1, QUAD.V2.2, GCLK7
IO.DOUBLE.3.S.2	SINGLE.V7, DOUBLE.V1.1, IO.DOUBLE.3.E.1, IO.DBUF.H0, QUAD.V2.1, LONG.V6
IO.DBUF.H0	IO.DOUBLE.0.E.1, IO.DOUBLE.1.E.1, IO.DOUBLE.2.E.1, IO.DOUBLE.3.E.1
IO.DBUF.H1	IO.DOUBLE.0.S.2, IO.DOUBLE.1.S.2, IO.DOUBLE.2.S.2, IO.DOUBLE.3.S.2
IO.DBUF.V0	IO.DOUBLE.0.S.1, IO.DOUBLE.1.S.1, IO.DOUBLE.2.S.1, IO.DOUBLE.3.S.1
IO.DBUF.V1	IO.DOUBLE.0.E.0, IO.DOUBLE.1.E.0, IO.DOUBLE.2.E.0, IO.DOUBLE.3.E.0
QUAD.H0.0	SINGLE.V1.S, QUAD.H0.4, QUAD.V0.0, QUAD.V0.4, QBUF.0, LONG.IO.V3
QUAD.H0.1	IO.DOUBLE.1.E.0, DEC.V3
QUAD.H0.2	SINGLE.V0.S, IO.DOUBLE.0.E.1
QUAD.H0.3	DOUBLE.V0.2, IO.DOUBLE.0.E.0, OUT.LR.IOB1.I2.S
QUAD.H0.4	QUAD.H0.0, QUAD.V0.0, QUAD.V0.4, QBUF.0
QUAD.H1.0	SINGLE.V4.S, QUAD.H1.4, QUAD.V1.0, QUAD.V1.4, QBUF.1, LONG.IO.V2, OUT.LR.IOB1.I1.S
QUAD.H1.1	SINGLE.V3.S, IO.DOUBLE.2.E.0, DEC.V2
QUAD.H1.2	SINGLE.V2.S, IO.DOUBLE.1.E.1
QUAD.H1.4	QUAD.H1.0, QUAD.V1.0, QUAD.V1.4, QBUF.1
QUAD.H2.0	DOUBLE.V1.1, QUAD.H2.4, QUAD.V2.0, QUAD.V2.4, QBUF.2, LONG.IO.V1, OUT.LR.IOB1.I2.S
QUAD.H2.1	SINGLE.V7.S, IO.DOUBLE.3.E.1, DEC.V1
QUAD.H2.2	SINGLE.V6.S, IO.DOUBLE.3.E.0
QUAD.H2.3	SINGLE.V5.S, IO.DOUBLE.2.E.1, OUT.LR.IOB1.I1.S
QUAD.H2.4	QUAD.H2.0, QUAD.V2.0, QUAD.V2.4, QBUF.2
QUAD.V0.0	DOUBLE.H0.2, QUAD.H0.0, QUAD.H0.4, QUAD.V0.4, QBUF.0, LONG.IO.H0
QUAD.V0.1	SINGLE.H0.E, IO.DOUBLE.0.S.2
QUAD.V0.2	SINGLE.H2.E, IO.DOUBLE.0.S.1
QUAD.V0.3	SINGLE.H1.E, IO.DOUBLE.1.S.2, DEC.H2, OUT.BT.IOB1.I2.E
QUAD.V0.4	QUAD.H0.0, QUAD.H0.4, QUAD.V0.0, QBUF.0
QUAD.V1.0	SINGLE.H3.E, QUAD.H1.0, QUAD.H1.4, QUAD.V1.4, QBUF.1, LONG.IO.H1, OUT.BT.IOB1.I1.E
QUAD.V1.1	SINGLE.H5.E, IO.DOUBLE.1.S.1
QUAD.V1.2	IO.DOUBLE.2.S.2
QUAD.V1.3	DOUBLE.H1.1, IO.DOUBLE.2.S.1, DEC.H1
QUAD.V1.4	QUAD.H1.0, QUAD.H1.4, QUAD.V1.0, QBUF.1
QUAD.V2.0	SINGLE.H4.E, QUAD.H2.0, QUAD.H2.4, QUAD.V2.4, QBUF.2, LONG.IO.H3, OUT.BT.IOB1.I2.E
QUAD.V2.1	IO.DOUBLE.3.S.2
QUAD.V2.2	SINGLE.H7.E, IO.DOUBLE.3.S.1
QUAD.V2.3	SINGLE.H6.E, DEC.H0, OUT.BT.IOB1.I1.E
QUAD.V2.4	QUAD.H2.0, QUAD.H2.4, QUAD.V2.0, QBUF.2
QBUF.0	QUAD.H0.0, QUAD.H0.4, QUAD.V0.0, QUAD.V0.4
QBUF.1	QUAD.H1.0, QUAD.H1.4, QUAD.V1.0, QUAD.V1.4
QBUF.2	QUAD.H2.0, QUAD.H2.4, QUAD.V2.0, QUAD.V2.4
LONG.H3	SINGLE.V4, LONG.IO.V1, DEC.V2
LONG.H4	SINGLE.V5, LONG.IO.V2, DEC.V1, OUT.STARTUP.Q3
LONG.H5	SINGLE.V6, LONG.IO.V3, DEC.V0, OUT.STARTUP.Q3
LONG.V0	SINGLE.H1.E, LONG.IO.H0, DEC.H0, OUT.BT.IOB1.I2.E
LONG.V1	SINGLE.H2.E, LONG.IO.H1, DEC.H1, OUT.BT.IOB1.I2.E
LONG.V2	SINGLE.H3.E, LONG.IO.H2, DEC.H2, OUT.BT.IOB1.I2.E
LONG.V3	SINGLE.H4, LONG.IO.H1, DEC.H1, OUT.STARTUP.DONEIN
LONG.V4	SINGLE.H5, LONG.IO.H2, DEC.H2, OUT.STARTUP.DONEIN
LONG.V5	SINGLE.H6, LONG.IO.H3, DEC.H3, OUT.STARTUP.DONEIN
LONG.V6	SINGLE.H0.E, LONG.IO.H0.EXCL
LONG.V7	SINGLE.H3.E, LONG.IO.H1.EXCL
LONG.V8	SINGLE.H4.E, LONG.IO.H2.EXCL
LONG.V9	SINGLE.H7.E, LONG.IO.H3.EXCL
LONG.IO.H0	SINGLE.V1, QUAD.V0.0, LONG.V0, LONG.IO.H0.EXCL, LONG.IO.V0, LONG.IO.V2
LONG.IO.H0.EXCL	LONG.V6, LONG.IO.H0, GCLK4
LONG.IO.H1	SINGLE.V2, QUAD.V1.0, LONG.V1, LONG.V3, LONG.IO.H1.EXCL, LONG.IO.V1, LONG.IO.V3
LONG.IO.H1.EXCL	LONG.V7, LONG.IO.H1, GCLK5
LONG.IO.H2	SINGLE.V5, LONG.V2, LONG.V4, LONG.IO.H2.EXCL, LONG.IO.V0, LONG.IO.V2
LONG.IO.H2.EXCL	LONG.V8, LONG.IO.H2, GCLK6
LONG.IO.H3	SINGLE.V6, QUAD.V2.0, LONG.V5, LONG.IO.H3.EXCL, LONG.IO.V1, LONG.IO.V3
LONG.IO.H3.EXCL	LONG.V9, LONG.IO.H3, GCLK7
LONG.IO.V0	SINGLE.H1, LONG.IO.H0, LONG.IO.H2
LONG.IO.V1	SINGLE.H2, QUAD.H2.0, LONG.H3, LONG.IO.H1, LONG.IO.H3
LONG.IO.V2	SINGLE.H5, QUAD.H1.0, LONG.H4, LONG.IO.H0, LONG.IO.H2
LONG.IO.V3	SINGLE.H6, QUAD.H0.0, LONG.H5, LONG.IO.H1, LONG.IO.H3
VCLK	IO.DOUBLE.0.S.2, IO.DOUBLE.1.S.1, IO.DOUBLE.2.S.1, IO.DOUBLE.3.S.2, QUAD.V0.0, LONG.IO.H0, LONG.IO.H1, LONG.IO.H3, ECLK.H, BUFGE.H, OUT.BT.IOB1.I1.E
ECLK.V	SINGLE.H2, SINGLE.H3, SINGLE.H4, SINGLE.H5, IO.DOUBLE.3.E.1, LONG.IO.H0, LONG.IO.H1, LONG.IO.H3, OUT.BUFGE.H
ECLK.H	SINGLE.V2, SINGLE.V3, SINGLE.V4, SINGLE.V5, LONG.IO.H0, LONG.IO.H1, LONG.IO.H3, GCLK4, GCLK5, GCLK6, GCLK7, OUT.BUFGE.V
BUFGE.H	OUT.BUFGE.H
BUFGE.V0	OUT.BUFGE.V
IMUX.CLB.F4	LONG.V7, LONG.V9, GCLK4
IMUX.CLB.G4	LONG.V6, LONG.V9, GCLK4
IMUX.CLB.C4	LONG.V0, LONG.V4, LONG.V6, LONG.V8, GCLK5
IMUX.STARTUP.CLK	SINGLE.V2, SINGLE.V3, SINGLE.V4, SINGLE.V5
IMUX.STARTUP.GSR	SINGLE.H2, SINGLE.H3, SINGLE.H4, SINGLE.H5, DOUBLE.V0.0, DOUBLE.V1.1, LONG.V3, LONG.V4, LONG.V5
IMUX.STARTUP.GTS	SINGLE.V2, SINGLE.V3, SINGLE.V4, SINGLE.V5, DOUBLE.H0.1, DOUBLE.H1.0, LONG.H3, LONG.H4, LONG.H5
IMUX.READCLK.I	SINGLE.H2, SINGLE.H3, SINGLE.H4, SINGLE.H5
IMUX.BUFG.H	IO.DOUBLE.0.E.1, IO.DOUBLE.0.S.1, IO.DOUBLE.1.E.1, IO.DOUBLE.1.S.1, IO.DOUBLE.2.E.1, IO.DOUBLE.2.S.1, IO.DOUBLE.3.E.1, IO.DOUBLE.3.S.1, OUT.IOB.CLKIN.E
IMUX.BUFG.V	IO.OCTAL.E.0, IO.OCTAL.E.7, LONG.IO.H0, LONG.IO.V0, OUT.IOB.CLKIN.S

Bel PULLUP_DEC0_H

xc4000ex CNR.BR bel PULLUP_DEC0_H
Pin	Direction	Wires
O	output	DEC.H0

Bel PULLUP_DEC1_H

xc4000ex CNR.BR bel PULLUP_DEC1_H
Pin	Direction	Wires
O	output	DEC.H1

Bel PULLUP_DEC2_H

xc4000ex CNR.BR bel PULLUP_DEC2_H
Pin	Direction	Wires
O	output	DEC.H2

Bel PULLUP_DEC3_H

xc4000ex CNR.BR bel PULLUP_DEC3_H
Pin	Direction	Wires
O	output	DEC.H3

Bel PULLUP_DEC0_V

xc4000ex CNR.BR bel PULLUP_DEC0_V
Pin	Direction	Wires
O	output	DEC.V0

Bel PULLUP_DEC1_V

xc4000ex CNR.BR bel PULLUP_DEC1_V
Pin	Direction	Wires
O	output	DEC.V1

Bel PULLUP_DEC2_V

xc4000ex CNR.BR bel PULLUP_DEC2_V
Pin	Direction	Wires
O	output	DEC.V2

Bel PULLUP_DEC3_V

xc4000ex CNR.BR bel PULLUP_DEC3_V
Pin	Direction	Wires
O	output	DEC.V3

Bel BUFGLS_H

xc4000ex CNR.BR bel BUFGLS_H
Pin	Direction	Wires

Bel BUFGLS_V

xc4000ex CNR.BR bel BUFGLS_V
Pin	Direction	Wires

Bel BUFGE_H

xc4000ex CNR.BR bel BUFGE_H
Pin	Direction	Wires
O	output	OUT.BUFGE.H

Bel BUFGE_V

xc4000ex CNR.BR bel BUFGE_V
Pin	Direction	Wires
O	output	OUT.BUFGE.V

Bel BUFG_H

xc4000ex CNR.BR bel BUFG_H
Pin	Direction	Wires
I	input	IMUX.BUFG.H

Bel BUFG_V

xc4000ex CNR.BR bel BUFG_V
Pin	Direction	Wires
I	input	IMUX.BUFG.V

Bel STARTUP

xc4000ex CNR.BR bel STARTUP
Pin	Direction	Wires
CLK	input	IMUX.STARTUP.CLK
DONEIN	output	OUT.STARTUP.DONEIN
GSR	input	IMUX.STARTUP.GSR
GTS	input	IMUX.STARTUP.GTS
Q1Q4	output	OUT.STARTUP.Q1Q4
Q2	output	OUT.STARTUP.Q2
Q3	output	OUT.STARTUP.Q3

Bel READCLK

xc4000ex CNR.BR bel READCLK
Pin	Direction	Wires
I	input	IMUX.READCLK.I

Bel wires

xc4000ex CNR.BR bel wires
Wire	Pins
DEC.H0	PULLUP_DEC0_H.O
DEC.H1	PULLUP_DEC1_H.O
DEC.H2	PULLUP_DEC2_H.O
DEC.H3	PULLUP_DEC3_H.O
DEC.V0	PULLUP_DEC0_V.O
DEC.V1	PULLUP_DEC1_V.O
DEC.V2	PULLUP_DEC2_V.O
DEC.V3	PULLUP_DEC3_V.O
IMUX.STARTUP.CLK	STARTUP.CLK
IMUX.STARTUP.GSR	STARTUP.GSR
IMUX.STARTUP.GTS	STARTUP.GTS
IMUX.READCLK.I	READCLK.I
IMUX.BUFG.H	BUFG_H.I
IMUX.BUFG.V	BUFG_V.I
OUT.STARTUP.DONEIN	STARTUP.DONEIN
OUT.STARTUP.Q1Q4	STARTUP.Q1Q4
OUT.STARTUP.Q2	STARTUP.Q2
OUT.STARTUP.Q3	STARTUP.Q3
OUT.BUFGE.H	BUFGE_H.O
OUT.BUFGE.V	BUFGE_V.O

Bitstream

xc4000ex CNR.BR bittile 0
Bit	Frame
Bit	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
15	~INT:PASS.QUAD.V2.0.0.QBUF.2	~INT:BIPASS.QUAD.H2.0.QUAD.V2.0	~INT:BIPASS.QUAD.H2.0.QUAD.H2.4	~INT:BIPASS.QUAD.H2.4.QUAD.V2.0	~INT:BIPASS.QUAD.H2.4.QUAD.V2.4	~INT:BIPASS.QUAD.H2.0.QUAD.V2.4	~INT:BIPASS.QUAD.V2.0.QUAD.V2.4	~INT:BIPASS.QUAD.H0.0.QUAD.V0.0	~INT:BIPASS.QUAD.H0.0.QUAD.H0.4	~INT:BIPASS.QUAD.H0.4.QUAD.V0.0	~INT:BIPASS.QUAD.H0.4.QUAD.V0.4	~INT:BIPASS.QUAD.H0.0.QUAD.V0.4	~INT:BIPASS.QUAD.V0.0.QUAD.V0.4	~INT:BIPASS.SINGLE.V4.S.QUAD.H1.0	~INT:BIPASS.SINGLE.V6.S.QUAD.H2.2	-	~INT:BIPASS.SINGLE.V2.S.QUAD.H1.2	~INT:BIPASS.SINGLE.V0.S.QUAD.H0.2	-	-	-	-	-	-	-	-	INT:MUX.IMUX.CLB.C4[2]	INT:MUX.IMUX.CLB.C4[0]	~INT:BIPASS.IO.DOUBLE.0.E.1.QUAD.H0.2	-	~INT:BIPASS.IO.DOUBLE.1.E.1.QUAD.H1.2	-	~INT:BIPASS.IO.DOUBLE.3.E.0.QUAD.H2.2	~INT:BIPASS.QUAD.H1.0.LONG.IO.V2	~INT:PASS.QUAD.H1.0.0.OUT.LR.IOB1.I1.S	~INT:PASS.QUAD.H2.3.0.OUT.LR.IOB1.I1.S	INT:MUX.IMUX.CLB.F4[0]	-	INT:MUX.IMUX.CLB.G4[1]	-	-	-	-	-	-	-	~INT:PASS.QUAD.H1.1.0.DEC.V2	~INT:BIPASS.IO.DOUBLE.2.E.0.QUAD.H1.1	-	~INT:BIPASS.IO.DOUBLE.2.E.1.QUAD.H2.3	-	-
14	~INT:PASS.QUAD.H2.0.0.QBUF.2	~INT:PASS.QUAD.H2.4.0.QBUF.2	~INT:PASS.QUAD.V2.4.0.QBUF.2	INT:MUX.QBUF.2[1]	INT:MUX.QBUF.2[0]	~INT:PASS.QUAD.V0.0.0.QBUF.0	~INT:PASS.QUAD.H0.0.0.QBUF.0	~INT:PASS.QUAD.H0.4.0.QBUF.0	~INT:PASS.QUAD.V0.4.0.QBUF.0	~INT:PASS.QUAD.V1.0.0.QBUF.1	INT:MUX.QBUF.0[1]	INT:MUX.QBUF.0[0]	~INT:BIPASS.SINGLE.V5.S.QUAD.H2.3	~INT:BIPASS.DOUBLE.V1.1.QUAD.H2.0	~INT:BIPASS.SINGLE.V7.S.QUAD.H2.1	~INT:BIPASS.SINGLE.V3.S.QUAD.H1.1	~INT:BIPASS.SINGLE.V1.S.QUAD.H0.0	~INT:BIPASS.DOUBLE.V0.2.QUAD.H0.3	-	-	-	-	-	-	-	-	INT:MUX.IMUX.CLB.C4[4]	INT:MUX.IMUX.CLB.C4[3]	INT:MUX.IMUX.CLB.C4[1]	-	~INT:PASS.QUAD.H2.0.0.OUT.LR.IOB1.I2.S	~INT:BIPASS.QUAD.H2.0.LONG.IO.V1	~INT:PASS.QUAD.H0.3.0.OUT.LR.IOB1.I2.S	~INT:BIPASS.IO.DOUBLE.0.E.0.QUAD.H0.3	~INT:BIPASS.IO.DOUBLE.3.E.1.QUAD.H2.1	~INT:PASS.QUAD.H2.1.0.DEC.V1	INT:MUX.IMUX.CLB.F4[1]	INT:MUX.ECLK.V[0]	INT:MUX.IMUX.CLB.G4[0]	INT:MUX.ECLK.V[1]	INT:MUX.ECLK.V[5]	INT:MUX.ECLK.V[4]	INT:MUX.ECLK.V[3]	INT:MUX.ECLK.V[2]	INT:MUX.ECLK.V[6]	-	~INT:PASS.QUAD.H0.1.0.DEC.V3	~INT:BIPASS.IO.DOUBLE.1.E.0.QUAD.H0.1	-	~INT:BIPASS.QUAD.H0.0.LONG.IO.V3	-	-
13	~INT:BIPASS.QUAD.H1.4.QUAD.V1.4	~INT:BIPASS.QUAD.H1.4.QUAD.V1.0	~INT:BIPASS.QUAD.V1.0.QUAD.V1.4	~INT:BIPASS.QUAD.H1.0.QUAD.V1.4	~INT:BIPASS.QUAD.H1.0.QUAD.V1.0	INT:MUX.QBUF.1[1]	INT:MUX.QBUF.1[0]	~INT:PASS.QUAD.H1.4.0.QBUF.1	~INT:PASS.QUAD.V1.4.0.QBUF.1	~INT:PASS.QUAD.H1.0.0.QBUF.1	~INT:PASS.SINGLE.H2.E.0.LONG.V1	~INT:BIPASS.SINGLE.H7.E.SINGLE.V7.S	~INT:BIPASS.SINGLE.H7.SINGLE.H7.E	~INT:BIPASS.SINGLE.H7.E.SINGLE.V7	~INT:BIPASS.SINGLE.V7.SINGLE.V7.S	~INT:BIPASS.SINGLE.H7.SINGLE.V7	~INT:PASS.SINGLE.H6.0.LONG.V5	-	~INT:BIPASS.SINGLE.H2.E.SINGLE.V2.S	~INT:BIPASS.SINGLE.H2.E.SINGLE.V2	~INT:BIPASS.SINGLE.V2.SINGLE.V2.S	~INT:BIPASS.DOUBLE.H0.0.DOUBLE.H0.2	~INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.2	~INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.0	~INT:PASS.SINGLE.V7.0.GND	-	-	~INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.E.0	~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.E.0	~INT:BIPASS.SINGLE.H7.IO.DOUBLE.3.E.1	~INT:BIPASS.IO.DOUBLE.3.E.0.IO.DOUBLE.3.S.1	~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.E.1	~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.S.1	~INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.S.1	~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.1	~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.S.1	~INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.E.1	INT:MUX.IO.DBUF.V1[0]	INT:MUX.IO.DBUF.V1[2]	INT:MUX.IO.DBUF.V1[1]	~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.1	~INT:BIPASS.IO.DOUBLE.0.E.0.IO.DOUBLE.0.S.1	INT:MUX.IO.DBUF.V1[3]	~INT:PASS.SINGLE.H3.0.DEC.V1	INT:MUX.IO.DBUF.V0[1]	INT:MUX.IO.DBUF.V0[0]	INT:MUX.IO.DBUF.V0[2]	~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.E.0	~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.0	~INT:BIPASS.IO.DOUBLE.1.E.0.IO.DOUBLE.1.S.1	~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.S.1	~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.1
12	-	~INT:BIPASS.SINGLE.H3.E.QUAD.V1.0	~INT:BIPASS.QUAD.H1.0.QUAD.H1.4	~INT:BIPASS.SINGLE.H6.E.QUAD.V2.3	~INT:BIPASS.SINGLE.H5.E.QUAD.V1.1	-	~INT:BIPASS.DOUBLE.H1.1.QUAD.V1.3	~INT:BIPASS.DOUBLE.H0.2.QUAD.V0.0	~INT:BIPASS.SINGLE.H7.E.QUAD.V2.2	~INT:BIPASS.SINGLE.H2.E.QUAD.V0.2	-	~INT:BIPASS.SINGLE.H4.E.SINGLE.V4	~INT:BUF.LONG.V1.0.SINGLE.H2.E	~INT:BIPASS.SINGLE.H7.SINGLE.V7.S	~INT:BIPASS.SINGLE.H6.SINGLE.V6	~INT:BUF.LONG.V5.0.SINGLE.H6	-	~INT:BIPASS.SINGLE.H2.SINGLE.V2.S	~INT:BIPASS.SINGLE.H2.SINGLE.H2.E	~INT:BIPASS.SINGLE.H2.SINGLE.V2	-	~INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.2	-	~INT:BIPASS.DOUBLE.V0.0.DOUBLE.V0.2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
11	-	~INT:BUF.LONG.V9.0.SINGLE.H7.E	~INT:BUF.LONG.V8.0.SINGLE.H4.E	~INT:BIPASS.SINGLE.H0.E.QUAD.V0.1	~INT:PASS.SINGLE.H0.E.0.LONG.V6	~INT:BIPASS.SINGLE.H1.E.QUAD.V0.3	~INT:BIPASS.SINGLE.H4.E.QUAD.V2.0	~INT:BUF.LONG.V6.0.SINGLE.H0.E	~INT:BUF.LONG.V7.0.SINGLE.H3.E	~INT:PASS.SINGLE.H3.E.0.LONG.V7	~INT:PASS.SINGLE.V6.0.LONG.H5	-	~INT:BIPASS.SINGLE.V6.SINGLE.V6.S	~INT:BIPASS.SINGLE.H6.E.SINGLE.V6.S	~INT:BIPASS.SINGLE.H6.SINGLE.V6.S	~INT:BIPASS.SINGLE.H6.SINGLE.H6.E	~INT:BIPASS.SINGLE.H6.E.SINGLE.V6	~INT:BIPASS.SINGLE.H3.E.SINGLE.V3.S	~INT:BIPASS.SINGLE.H3.E.SINGLE.V3	~INT:BIPASS.SINGLE.H3.SINGLE.H3.E	~INT:BIPASS.SINGLE.H3.SINGLE.V3.S	~INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.0	~INT:BIPASS.SINGLE.H3.SINGLE.V3	~INT:BIPASS.SINGLE.V3.SINGLE.V3.S	~INT:PASS.SINGLE.V4.0.LONG.H3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~INT:PASS.SINGLE.H6.0.OUT.STARTUP.Q1Q4	~INT:PASS.DOUBLE.H0.0.0.OUT.STARTUP.Q1Q4	~INT:PASS.SINGLE.H2.0.OUT.STARTUP.Q1Q4	INT:MUX.IO.DBUF.V0[3]	~INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.E.0	~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.E.0	~INT:BIPASS.IO.DOUBLE.2.E.0.IO.DOUBLE.2.S.1	OSC:MUX.OUT0[2]
10	-	-	-	-	-	-	-	-	-	-	-	~INT:BIPASS.SINGLE.H4.SINGLE.V4	~INT:BIPASS.SINGLE.V4.SINGLE.V4.S	~INT:BIPASS.SINGLE.H4.E.SINGLE.V4.S	~INT:BIPASS.SINGLE.H4.SINGLE.H4.E	~INT:BIPASS.SINGLE.H4.SINGLE.V4.S	~INT:PASS.SINGLE.H3.E.0.LONG.V2	~INT:BIPASS.DOUBLE.H1.0.DOUBLE.H1.2	~INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.0	-	~INT:BIPASS.SINGLE.H1.E.SINGLE.V1	~INT:BIPASS.SINGLE.V0.SINGLE.V0.S	~INT:BIPASS.SINGLE.H0.SINGLE.H0.E	-	~INT:PASS.SINGLE.V0.0.GND	-	~INT:PASS.DOUBLE.H1.0.0.OUT.LR.IOB1.I2.S	~INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S	~INT:PASS.SINGLE.H4.0.OUT.LR.IOB1.I2.S	~INT:PASS.SINGLE.H5.0.OUT.STARTUP.Q3	~INT:PASS.DOUBLE.H1.1.0.OUT.STARTUP.Q3	~INT:PASS.SINGLE.H1.0.OUT.STARTUP.Q3	~INT:BUF.LONG.V2.0.SINGLE.H3.E	~INT:BUF.LONG.H5.0.SINGLE.V6	-	~INT:PASS.SINGLE.H1.0.LONG.IO.V0	~INT:PASS.SINGLE.H6.0.LONG.IO.V3	~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.0	~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.E.0	~INT:PASS.IO.DOUBLE.3.E.0.0.IO.DBUF.V0	~INT:PASS.IO.DOUBLE.2.E.0.0.IO.DBUF.V0	~INT:PASS.IO.DOUBLE.0.S.1.0.IO.DBUF.V1	~INT:PASS.IO.DOUBLE.2.S.1.0.IO.DBUF.V1	~INT:PASS.IO.DOUBLE.3.S.1.0.IO.DBUF.V1	~INT:PASS.IO.DOUBLE.1.S.1.0.IO.DBUF.V1	~INT:PASS.SINGLE.H7.0.OUT.LR.IOB1.I1.S	~INT:PASS.SINGLE.H7.0.DEC.V3	~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.E.1	~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.1	~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.S.1	~INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.S.1	OSC:MUX.OUT1[2]
9	-	-	-	-	-	-	-	-	-	-	~INT:PASS.SINGLE.V5.0.LONG.H4	~INT:BIPASS.SINGLE.V5.SINGLE.V5.S	~INT:BIPASS.SINGLE.H5.E.SINGLE.V5.S	~INT:BIPASS.SINGLE.H5.SINGLE.V5.S	~INT:BIPASS.SINGLE.H5.E.SINGLE.V5	~INT:BIPASS.SINGLE.H5.SINGLE.H5.E	~INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.2	~INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.0	~INT:PASS.SINGLE.H1.E.0.LONG.V0	~INT:BIPASS.SINGLE.H1.E.SINGLE.V1.S	~INT:BIPASS.SINGLE.H1.SINGLE.H1.E	~INT:BIPASS.SINGLE.H1.SINGLE.V1	~INT:BIPASS.SINGLE.H0.E.SINGLE.V0.S	~INT:BIPASS.SINGLE.H0.SINGLE.V0	~INT:BIPASS.SINGLE.H0.E.SINGLE.V0	-	-	-	-	-	-	-	~INT:BUF.LONG.H4.0.SINGLE.V5	~INT:BUF.LONG.V0.0.SINGLE.H1.E	~INT:BUF.LONG.V4.0.SINGLE.H5	~INT:PASS.SINGLE.H2.0.LONG.IO.V1	~INT:BUF.LONG.V3.0.SINGLE.H4	~INT:PASS.IO.DOUBLE.0.E.0.0.IO.DBUF.V0	~INT:PASS.IO.DOUBLE.1.E.0.0.IO.DBUF.V0	~INT:PASS.DOUBLE.H0.1.0.OUT.LR.IOB1.I1.S	~INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S	~INT:PASS.SINGLE.H0.0.DEC.V0	~INT:PASS.SINGLE.H5.0.LONG.IO.V2	~INT:PASS.SINGLE.H4.0.DEC.V2	INT:MUX.IMUX.READCLK.I[2]	INT:MUX.IMUX.READCLK.I[1]	INT:MUX.IMUX.READCLK.I[0]	INT:MUX.IMUX.READCLK.I[3]	~INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.E.1	~INT:BIPASS.SINGLE.H5.IO.DOUBLE.2.E.1	OSC:MUX.OUT0[1]	OSC:MUX.OUT1[1]
8	-	-	~INT:PASS.SINGLE.H7.E.0.LONG.V9	~INT:PASS.SINGLE.H4.E.0.LONG.V8	-	-	-	-	-	-	INT:MUX.IMUX.STARTUP.CLK[0]	INT:MUX.IMUX.STARTUP.CLK[1]	INT:MUX.IMUX.STARTUP.CLK[2]	INT:MUX.IMUX.STARTUP.CLK[3]	~INT:BIPASS.SINGLE.H5.SINGLE.V5	~INT:PASS.SINGLE.H4.0.LONG.V3	~INT:BIPASS.DOUBLE.V1.0.DOUBLE.V1.2	~INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.2	-	~INT:BIPASS.SINGLE.V1.SINGLE.V1.S	~INT:BIPASS.SINGLE.H0.SINGLE.V0.S	~INT:BIPASS.SINGLE.H1.SINGLE.V1.S	~INT:PASS.SINGLE.H5.0.LONG.V4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
6	-	-	INT:MUX.LONG.IO.H2[2]	INT:MUX.LONG.IO.H2[3]	~INT:BUF.LONG.V8.0.LONG.IO.H2	-	-	INT:MUX.LONG.IO.H3[3]	~INT:BUF.LONG.V9.0.LONG.IO.H3	INT:MUX.LONG.IO.H3[2]	~INT:PASS.SINGLE.V4.0.OUT.BT.IOB1.I2.E	~INT:PASS.SINGLE.V4.0.DEC.H1	~INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E	INT:MUX.LONG.V1[2]	~INT:PASS.SINGLE.V3.0.DEC.H2	INT:MUX.LONG.V3[1]	INT:MUX.LONG.V3[2]	INT:MUX.IMUX.STARTUP.GSR[3]	INT:MUX.IMUX.STARTUP.GSR[0]	INT:MUX.IMUX.STARTUP.GSR[2]	INT:MUX.IMUX.STARTUP.GSR[1]	INT:MUX.IMUX.STARTUP.GSR[5]	INT:MUX.IMUX.STARTUP.GSR[4]	~INT:PASS.SINGLE.V1.0.OUT.STARTUP.DONEIN	INT:MUX.LONG.V2[0]	-	INT:MUX.LONG.V2[2]	~INT:BUF.LONG.H3.0.SINGLE.V4	-	INT:MUX.LONG.H3[0]	INT:MUX.LONG.H5[1]	INT:MUX.IMUX.BUFG.V[2]	INT:MUX.IMUX.BUFG.V[1]	INT:MUX.IMUX.BUFG.V[3]	INT:MUX.IMUX.BUFG.V[4]	INT:MUX.IMUX.BUFG.V[5]	INT:MUX.IMUX.BUFG.V[0]	-	~INT:PASS.DOUBLE.V0.1.0.OUT.STARTUP.Q2	~INT:PASS.SINGLE.V2.0.OUT.STARTUP.Q2	~INT:PASS.SINGLE.V6.0.OUT.STARTUP.Q2	INT:MUX.LONG.H4[3]	INT:MUX.LONG.H4[1]	-	INT:MUX.LONG.H4[0]	INT:MUX.LONG.H4[2]	-	-	-	-	-	-
5	-	~INT:PASS.QUAD.V2.3.0.DEC.H0	INT:MUX.LONG.IO.H0[2]	INT:MUX.LONG.IO.H0[3]	~INT:BUF.LONG.V6.0.LONG.IO.H0	~INT:BUF.LONG.V7.0.LONG.IO.H1	INT:MUX.LONG.IO.H1[3]	~INT:PASS.QUAD.V0.3.0.OUT.BT.IOB1.I2.E	INT:MUX.LONG.IO.H1[2]	~INT:PASS.QUAD.V2.0.0.OUT.BT.IOB1.I2.E	-	INT:MUX.LONG.V1[0]	INT:MUX.LONG.V1[3]	INT:MUX.LONG.V1[1]	INT:MUX.LONG.V3[0]	INT:MUX.LONG.V3[3]	INT:MUX.IMUX.STARTUP.GTS[1]	INT:MUX.IMUX.STARTUP.GTS[2]	INT:MUX.IMUX.STARTUP.GTS[3]	INT:MUX.IMUX.STARTUP.GTS[4]	INT:MUX.IMUX.STARTUP.GTS[5]	INT:MUX.IMUX.STARTUP.GTS[0]	INT:MUX.LONG.V2[3]	INT:MUX.LONG.V2[1]	~INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E	-	INT:MUX.LONG.V4[3]	INT:MUX.LONG.V4[0]	INT:MUX.LONG.V4[1]	INT:MUX.LONG.V4[2]	INT:MUX.LONG.H3[1]	INT:MUX.LONG.H5[0]	INT:MUX.LONG.H5[2]	INT:MUX.LONG.H5[3]	-	INT:MUX.LONG.IO.V2[2]	INT:MUX.LONG.IO.V0[2]	INT:MUX.LONG.IO.V2[1]	INT:MUX.LONG.IO.V2[0]	~PULLUP_DEC3_V:ENABLE	~PULLUP_DEC1_V:ENABLE	~INT:PASS.SINGLE.V6.0.LONG.IO.H3	~PULLUP_DEC2_V:ENABLE	~PULLUP_DEC0_V:ENABLE	INT:MUX.LONG.IO.V1[2]	INT:MUX.LONG.IO.V1[0]	INT:MUX.LONG.IO.V1[1]	INT:MUX.LONG.IO.V2[3]	INT:MUX.LONG.IO.V3[3]	-	OSC:MUX.OUT0[0]	OSC:MUX.OUT1[0]
4	~INT:BIPASS.QUAD.V1.0.LONG.IO.H1	~INT:BIPASS.QUAD.V2.0.LONG.IO.H3	~INT:PASS.QUAD.V2.3.0.OUT.BT.IOB1.I1.E	-	-	-	INT:MUX.ECLK.H[3]	INT:MUX.ECLK.H[1]	INT:MUX.ECLK.H[0]	INT:MUX.ECLK.H[2]	-	~PULLUP_DEC3_H:ENABLE	~PULLUP_DEC2_H:ENABLE	~PULLUP_DEC1_H:ENABLE	~INT:PASS.SINGLE.V7.0.OUT.BT.IOB1.I1.E	INT:MUX.LONG.V5[3]	~INT:PASS.SINGLE.V7.0.DEC.H0	INT:MUX.LONG.V5[1]	INT:MUX.LONG.V5[0]	INT:MUX.LONG.V5[2]	~INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E	~INT:PASS.DOUBLE.V1.0.0.OUT.STARTUP.DONEIN	~INT:PASS.SINGLE.V5.0.LONG.IO.H2	~INT:PASS.SINGLE.V5.0.OUT.STARTUP.DONEIN	INT:MUX.LONG.IO.H3[4]	-	INT:MUX.LONG.V0[0]	INT:MUX.LONG.V0[1]	INT:MUX.LONG.IO.V2[4]	INT:MUX.LONG.V0[2]	INT:MUX.LONG.IO.V0[3]	INT:MUX.LONG.V0[3]	~INT:PASS.SINGLE.V2.0.LONG.IO.H1	~INT:PASS.SINGLE.V1.0.LONG.IO.H0	INT:MUX.LONG.IO.V3[4]	INT:MUX.LONG.IO.V0[0]	INT:MUX.LONG.IO.V0[1]	~INT:PASS.SINGLE.V0.0.DEC.H3	~INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E	INT:MUX.LONG.IO.V3[0]	INT:MUX.IO.DBUF.H0[2]	INT:MUX.LONG.IO.V1[4]	INT:MUX.IO.DBUF.H0[0]	INT:MUX.IO.DBUF.H0[1]	INT:MUX.IO.DBUF.H0[3]	INT:MUX.LONG.IO.V3[2]	INT:MUX.LONG.IO.V1[3]	INT:MUX.LONG.IO.V3[1]	OSC:MUX.OUT1[3]	-	OSC:MUX.OUT0[3]	OSC:ENABLE
3	-	~INT:BIPASS.QUAD.V0.0.LONG.IO.H0	~INT:PASS.IO.DOUBLE.1.S.1.0.LONG.V8	-	-	-	-	INT:MUX.ECLK.H[4]	INT:MUX.ECLK.H[5]	INT:MUX.ECLK.H[6]	-	~PULLUP_DEC0_H:ENABLE	INT:MUX.LONG.IO.H2[5]	INT:MUX.LONG.IO.H2[4]	INT:MUX.LONG.IO.H2[7]	INT:MUX.LONG.IO.H3[5]	INT:MUX.LONG.IO.H2[6]	INT:MUX.LONG.IO.H1[7]	INT:MUX.LONG.IO.H1[5]	INT:MUX.LONG.IO.H1[4]	INT:MUX.LONG.IO.H1[6]	INT:MUX.LONG.IO.H0[5]	INT:MUX.LONG.IO.H0[4]	~INT:BIPASS.IO.DOUBLE.1.E.1.IO.DOUBLE.1.S.2	~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.1	INT:MUX.IMUX.BUFG.H[2]	~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.1	~INT:BIPASS.IO.DOUBLE.0.E.1.IO.DOUBLE.0.S.2	INT:MUX.LONG.IO.H0[1]	INT:MUX.LONG.IO.H0[0]	INT:MUX.IMUX.BUFG.H[5]	INT:MUX.LONG.IO.H2[0]	INT:MUX.LONG.IO.H2[1]	STARTUP:OUTPUTS_ACTIVE[1]	STARTUP:OUTPUTS_ACTIVE[0]	STARTUP:GSR_INACTIVE[0]	STARTUP:GSR_INACTIVE[1]	INT:MUX.LONG.IO.H1[1]	INT:MUX.LONG.IO.H1[0]	STARTUP:DONE_ACTIVE[1]	INT:MUX.LONG.IO.H3[0]	INT:MUX.LONG.IO.H3[1]	-	-	~STARTUP:EXPRESS_MODE	-	-	-	-	-	~MISC:FIX_DISCHARGE	-
2	~INT:BIPASS.IO.DOUBLE.1.S.2.QUAD.V0.3	~INT:PASS.IO.DOUBLE.0.S.2.0.LONG.V9	INT:MUX.VCLK[5]	~INT:PASS.IO.DOUBLE.3.S.2.0.LONG.V6	~INT:BIPASS.IO.DOUBLE.1.S.1.QUAD.V1.1	~INT:BIPASS.IO.DOUBLE.0.S.2.QUAD.V0.1	~INT:PASS.QUAD.V1.3.0.DEC.H1	~INT:PASS.IO.DOUBLE.0.S.1.0.GCLK4	~INT:PASS.IO.DOUBLE.1.S.2.0.GCLK5	~INT:PASS.IO.DOUBLE.3.S.1.0.GCLK7	-	INT:MUX.IO.DBUF.H1[2]	INT:MUX.IO.DBUF.H1[3]	~INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.S.2	~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.S.2	~INT:BIPASS.IO.DOUBLE.3.E.1.IO.DOUBLE.3.S.2	~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.S.1	~INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.S.2	~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.S.2	~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.S.2	~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.2	~INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.S.1	~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1	~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.S.2	~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.2	INT:MUX.IMUX.BUFG.H[4]	~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1	~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.1	~INT:PASS.IO.DOUBLE.0.E.1.0.IO.DBUF.H1	~INT:PASS.IO.DOUBLE.2.E.1.0.IO.DBUF.H1	~INT:PASS.IO.DOUBLE.1.E.1.0.IO.DBUF.H1	INT:MUX.IMUX.BUFG.H[0]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
1	INT:MUX.VCLK[0]	INT:MUX.VCLK[1]	INT:MUX.VCLK[2]	INT:MUX.VCLK[4]	INT:MUX.VCLK[3]	~INT:BIPASS.IO.DOUBLE.0.S.1.QUAD.V0.2	~INT:BIPASS.IO.DOUBLE.2.S.1.QUAD.V1.3	~INT:BIPASS.IO.DOUBLE.3.S.2.QUAD.V2.1	~INT:BIPASS.IO.DOUBLE.3.S.1.QUAD.V2.2	-	-	INT:MUX.IO.DBUF.H1[0]	INT:MUX.IO.DBUF.H1[1]	~INT:BIPASS.SINGLE.V6.IO.DOUBLE.3.S.1	~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.1	~INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.E.1	~INT:PASS.IO.DOUBLE.3.S.2.0.IO.DBUF.H0	~INT:PASS.IO.DOUBLE.2.S.2.0.IO.DBUF.H0	~INT:PASS.IO.DOUBLE.1.S.2.0.IO.DBUF.H0	~INT:PASS.IO.DOUBLE.0.S.2.0.IO.DBUF.H0	~INT:BIPASS.IO.DOUBLE.2.E.1.IO.DOUBLE.2.S.2	~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.S.1	~INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.E.1	~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.1	~INT:BIPASS.SINGLE.V4.IO.DOUBLE.2.S.1	INT:MUX.IMUX.BUFG.H[3]	~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.1	~INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.S.1	~INT:PASS.IO.DOUBLE.3.E.1.0.IO.DBUF.H1	INT:MUX.IMUX.BUFG.H[6]	INT:MUX.IMUX.BUFG.H[1]	-	-	-	-	-	-	-	-	STARTUP:DONE_ACTIVE[0]	~STARTUP:SYNC_TO_DONE	STARTUP:STARTUP_CLK[0]	~STARTUP:INV.GSR	~STARTUP:ENABLE.GSR	~STARTUP:INV.GTS	DONE:PULL[0]	~STARTUP:ENABLE.GTS	~MISC:TCTEST	-	-	-	~STARTUP:CRC
0	-	~INT:PASS.IO.DOUBLE.2.S.1.0.LONG.V7	-	-	INT:MUX.VCLK[6]	~INT:PASS.QUAD.V0.3.0.DEC.H2	-	~INT:BIPASS.IO.DOUBLE.2.S.2.QUAD.V1.2	~INT:PASS.QUAD.V1.0.0.OUT.BT.IOB1.I1.E	~INT:PASS.IO.DOUBLE.2.S.2.0.GCLK6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	STARTUP:CONFIG_RATE[0]

DONE:PULL	0.6.1
PULLUP	0
PULLNONE	1

INT:BIPASS.DOUBLE.H0.0.DOUBLE.H0.2	0.30.13
INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.0	0.28.13
INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.2	0.29.13
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.0	0.3.13
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.1	0.3.10
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.S.1	0.1.13
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.0	0.14.10
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.1	0.11.13
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.S.1	0.16.13
INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.0	0.30.11
INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.2	0.30.12
INT:BIPASS.DOUBLE.H0.2.QUAD.V0.0	0.44.12
INT:BIPASS.DOUBLE.H1.0.DOUBLE.H1.2	0.34.10
INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.0	0.33.10
INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.2	0.34.8
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.E.0	0.2.11
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.E.1	0.4.10
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.S.1	0.2.10
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.E.0	0.23.13
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.E.1	0.20.13
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.S.1	0.19.13
INT:BIPASS.DOUBLE.H1.1.QUAD.V1.3	0.45.12
INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.0	0.34.9
INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.2	0.35.9
INT:BIPASS.DOUBLE.V0.0.DOUBLE.V0.2	0.28.12
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1	0.29.2
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.1	0.27.3
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.2	0.31.2
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1	0.25.2
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.1	0.25.3
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.2	0.27.2
INT:BIPASS.DOUBLE.V0.2.QUAD.H0.3	0.34.14
INT:BIPASS.DOUBLE.V1.0.DOUBLE.V1.2	0.35.8
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.1	0.28.1
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.S.1	0.30.1
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.S.2	0.33.2
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.1	0.37.1
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.S.1	0.35.2
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.S.2	0.37.2
INT:BIPASS.DOUBLE.V1.1.QUAD.H2.0	0.38.14
INT:BIPASS.IO.DOUBLE.0.E.0.IO.DOUBLE.0.S.1	0.10.13
INT:BIPASS.IO.DOUBLE.0.E.0.QUAD.H0.3	0.18.14
INT:BIPASS.IO.DOUBLE.0.E.1.IO.DOUBLE.0.S.2	0.24.3
INT:BIPASS.IO.DOUBLE.0.E.1.QUAD.H0.2	0.23.15
INT:BIPASS.IO.DOUBLE.0.S.1.QUAD.V0.2	0.46.1
INT:BIPASS.IO.DOUBLE.0.S.2.QUAD.V0.1	0.46.2
INT:BIPASS.IO.DOUBLE.1.E.0.IO.DOUBLE.1.S.1	0.2.13
INT:BIPASS.IO.DOUBLE.1.E.0.QUAD.H0.1	0.4.14
INT:BIPASS.IO.DOUBLE.1.E.1.IO.DOUBLE.1.S.2	0.28.3
INT:BIPASS.IO.DOUBLE.1.E.1.QUAD.H1.2	0.21.15
INT:BIPASS.IO.DOUBLE.1.S.1.QUAD.V1.1	0.47.2
INT:BIPASS.IO.DOUBLE.1.S.2.QUAD.V0.3	0.51.2
INT:BIPASS.IO.DOUBLE.2.E.0.IO.DOUBLE.2.S.1	0.1.11
INT:BIPASS.IO.DOUBLE.2.E.0.QUAD.H1.1	0.4.15
INT:BIPASS.IO.DOUBLE.2.E.1.IO.DOUBLE.2.S.2	0.31.1
INT:BIPASS.IO.DOUBLE.2.E.1.QUAD.H2.3	0.2.15
INT:BIPASS.IO.DOUBLE.2.S.1.QUAD.V1.3	0.45.1
INT:BIPASS.IO.DOUBLE.2.S.2.QUAD.V1.2	0.44.0
INT:BIPASS.IO.DOUBLE.3.E.0.IO.DOUBLE.3.S.1	0.21.13
INT:BIPASS.IO.DOUBLE.3.E.0.QUAD.H2.2	0.19.15
INT:BIPASS.IO.DOUBLE.3.E.1.IO.DOUBLE.3.S.2	0.36.2
INT:BIPASS.IO.DOUBLE.3.E.1.QUAD.H2.1	0.17.14
INT:BIPASS.IO.DOUBLE.3.S.1.QUAD.V2.2	0.43.1
INT:BIPASS.IO.DOUBLE.3.S.2.QUAD.V2.1	0.44.1
INT:BIPASS.QUAD.H0.0.LONG.IO.V3	0.2.14
INT:BIPASS.QUAD.H0.0.QUAD.H0.4	0.43.15
INT:BIPASS.QUAD.H0.0.QUAD.V0.0	0.44.15
INT:BIPASS.QUAD.H0.0.QUAD.V0.4	0.40.15
INT:BIPASS.QUAD.H0.4.QUAD.V0.0	0.42.15
INT:BIPASS.QUAD.H0.4.QUAD.V0.4	0.41.15
INT:BIPASS.QUAD.H1.0.LONG.IO.V2	0.18.15
INT:BIPASS.QUAD.H1.0.QUAD.H1.4	0.49.12
INT:BIPASS.QUAD.H1.0.QUAD.V1.0	0.47.13
INT:BIPASS.QUAD.H1.0.QUAD.V1.4	0.48.13
INT:BIPASS.QUAD.H1.4.QUAD.V1.0	0.50.13
INT:BIPASS.QUAD.H1.4.QUAD.V1.4	0.51.13
INT:BIPASS.QUAD.H2.0.LONG.IO.V1	0.20.14
INT:BIPASS.QUAD.H2.0.QUAD.H2.4	0.49.15
INT:BIPASS.QUAD.H2.0.QUAD.V2.0	0.50.15
INT:BIPASS.QUAD.H2.0.QUAD.V2.4	0.46.15
INT:BIPASS.QUAD.H2.4.QUAD.V2.0	0.48.15
INT:BIPASS.QUAD.H2.4.QUAD.V2.4	0.47.15
INT:BIPASS.QUAD.V0.0.LONG.IO.H0	0.50.3
INT:BIPASS.QUAD.V0.0.QUAD.V0.4	0.39.15
INT:BIPASS.QUAD.V1.0.LONG.IO.H1	0.51.4
INT:BIPASS.QUAD.V1.0.QUAD.V1.4	0.49.13
INT:BIPASS.QUAD.V2.0.LONG.IO.H3	0.50.4
INT:BIPASS.QUAD.V2.0.QUAD.V2.4	0.45.15
INT:BIPASS.SINGLE.H0.E.QUAD.V0.1	0.48.11
INT:BIPASS.SINGLE.H0.E.SINGLE.V0	0.27.9
INT:BIPASS.SINGLE.H0.E.SINGLE.V0.S	0.29.9
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.E.0	0.13.10
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.1	0.17.13
INT:BIPASS.SINGLE.H0.SINGLE.H0.E	0.29.10
INT:BIPASS.SINGLE.H0.SINGLE.V0	0.28.9
INT:BIPASS.SINGLE.H0.SINGLE.V0.S	0.31.8
INT:BIPASS.SINGLE.H1.E.QUAD.V0.3	0.46.11
INT:BIPASS.SINGLE.H1.E.SINGLE.V1	0.31.10
INT:BIPASS.SINGLE.H1.E.SINGLE.V1.S	0.32.9
INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.E.1	0.15.13
INT:BIPASS.SINGLE.H1.SINGLE.H1.E	0.31.9
INT:BIPASS.SINGLE.H1.SINGLE.V1	0.30.9
INT:BIPASS.SINGLE.H1.SINGLE.V1.S	0.30.8
INT:BIPASS.SINGLE.H2.E.QUAD.V0.2	0.42.12
INT:BIPASS.SINGLE.H2.E.SINGLE.V2	0.32.13
INT:BIPASS.SINGLE.H2.E.SINGLE.V2.S	0.33.13
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.E.0	0.4.13
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.1	0.0.13
INT:BIPASS.SINGLE.H2.SINGLE.H2.E	0.33.12
INT:BIPASS.SINGLE.H2.SINGLE.V2	0.32.12
INT:BIPASS.SINGLE.H2.SINGLE.V2.S	0.34.12
INT:BIPASS.SINGLE.H3.E.QUAD.V1.0	0.50.12
INT:BIPASS.SINGLE.H3.E.SINGLE.V3	0.33.11
INT:BIPASS.SINGLE.H3.E.SINGLE.V3.S	0.34.11
INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.E.1	0.3.9
INT:BIPASS.SINGLE.H3.SINGLE.H3.E	0.32.11
INT:BIPASS.SINGLE.H3.SINGLE.V3	0.29.11
INT:BIPASS.SINGLE.H3.SINGLE.V3.S	0.31.11
INT:BIPASS.SINGLE.H4.E.QUAD.V2.0	0.45.11
INT:BIPASS.SINGLE.H4.E.SINGLE.V4	0.40.12
INT:BIPASS.SINGLE.H4.E.SINGLE.V4.S	0.38.10
INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.E.0	0.3.11
INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.S.1	0.1.10
INT:BIPASS.SINGLE.H4.SINGLE.H4.E	0.37.10
INT:BIPASS.SINGLE.H4.SINGLE.V4	0.40.10
INT:BIPASS.SINGLE.H4.SINGLE.V4.S	0.36.10
INT:BIPASS.SINGLE.H5.E.QUAD.V1.1	0.47.12
INT:BIPASS.SINGLE.H5.E.SINGLE.V5	0.37.9
INT:BIPASS.SINGLE.H5.E.SINGLE.V5.S	0.39.9
INT:BIPASS.SINGLE.H5.IO.DOUBLE.2.E.1	0.2.9
INT:BIPASS.SINGLE.H5.SINGLE.H5.E	0.36.9
INT:BIPASS.SINGLE.H5.SINGLE.V5	0.37.8
INT:BIPASS.SINGLE.H5.SINGLE.V5.S	0.38.9
INT:BIPASS.SINGLE.H6.E.QUAD.V2.3	0.48.12
INT:BIPASS.SINGLE.H6.E.SINGLE.V6	0.35.11
INT:BIPASS.SINGLE.H6.E.SINGLE.V6.S	0.38.11
INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.E.0	0.24.13
INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.S.1	0.18.13
INT:BIPASS.SINGLE.H6.SINGLE.H6.E	0.36.11
INT:BIPASS.SINGLE.H6.SINGLE.V6	0.37.12
INT:BIPASS.SINGLE.H6.SINGLE.V6.S	0.37.11
INT:BIPASS.SINGLE.H7.E.QUAD.V2.2	0.43.12
INT:BIPASS.SINGLE.H7.E.SINGLE.V7	0.38.13
INT:BIPASS.SINGLE.H7.E.SINGLE.V7.S	0.40.13
INT:BIPASS.SINGLE.H7.IO.DOUBLE.3.E.1	0.22.13
INT:BIPASS.SINGLE.H7.SINGLE.H7.E	0.39.13
INT:BIPASS.SINGLE.H7.SINGLE.V7	0.36.13
INT:BIPASS.SINGLE.H7.SINGLE.V7.S	0.38.12
INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.S.1	0.24.1
INT:BIPASS.SINGLE.V0.S.QUAD.H0.2	0.34.15
INT:BIPASS.SINGLE.V0.SINGLE.V0.S	0.30.10
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.1	0.24.2
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.S.2	0.28.2
INT:BIPASS.SINGLE.V1.S.QUAD.H0.0	0.35.14
INT:BIPASS.SINGLE.V1.SINGLE.V1.S	0.32.8
INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.S.1	0.30.2
INT:BIPASS.SINGLE.V2.S.QUAD.H1.2	0.35.15
INT:BIPASS.SINGLE.V2.SINGLE.V2.S	0.31.13
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.1	0.25.1
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.S.2	0.32.2
INT:BIPASS.SINGLE.V3.S.QUAD.H1.1	0.36.14
INT:BIPASS.SINGLE.V3.SINGLE.V3.S	0.28.11
INT:BIPASS.SINGLE.V4.IO.DOUBLE.2.S.1	0.27.1
INT:BIPASS.SINGLE.V4.S.QUAD.H1.0	0.38.15
INT:BIPASS.SINGLE.V4.SINGLE.V4.S	0.39.10
INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.E.1	0.29.1
INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.S.2	0.34.2
INT:BIPASS.SINGLE.V5.S.QUAD.H2.3	0.39.14
INT:BIPASS.SINGLE.V5.SINGLE.V5.S	0.40.9
INT:BIPASS.SINGLE.V6.IO.DOUBLE.3.S.1	0.38.1
INT:BIPASS.SINGLE.V6.S.QUAD.H2.2	0.37.15
INT:BIPASS.SINGLE.V6.SINGLE.V6.S	0.39.11
INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.E.1	0.36.1
INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.S.2	0.38.2
INT:BIPASS.SINGLE.V7.S.QUAD.H2.1	0.37.14
INT:BIPASS.SINGLE.V7.SINGLE.V7.S	0.37.13
INT:BUF.LONG.H3.0.SINGLE.V4	0.24.6
INT:BUF.LONG.H4.0.SINGLE.V5	0.19.9
INT:BUF.LONG.H5.0.SINGLE.V6	0.18.10
INT:BUF.LONG.V0.0.SINGLE.H1.E	0.18.9
INT:BUF.LONG.V1.0.SINGLE.H2.E	0.39.12
INT:BUF.LONG.V2.0.SINGLE.H3.E	0.19.10
INT:BUF.LONG.V3.0.SINGLE.H4	0.15.9
INT:BUF.LONG.V4.0.SINGLE.H5	0.17.9
INT:BUF.LONG.V5.0.SINGLE.H6	0.36.12
INT:BUF.LONG.V6.0.LONG.IO.H0	0.47.5
INT:BUF.LONG.V6.0.SINGLE.H0.E	0.44.11
INT:BUF.LONG.V7.0.LONG.IO.H1	0.46.5
INT:BUF.LONG.V7.0.SINGLE.H3.E	0.43.11
INT:BUF.LONG.V8.0.LONG.IO.H2	0.47.6
INT:BUF.LONG.V8.0.SINGLE.H4.E	0.49.11
INT:BUF.LONG.V9.0.LONG.IO.H3	0.43.6
INT:BUF.LONG.V9.0.SINGLE.H7.E	0.50.11
INT:PASS.DOUBLE.H0.0.0.OUT.STARTUP.Q1Q4	0.6.11
INT:PASS.DOUBLE.H0.1.0.OUT.LR.IOB1.I1.S	0.12.9
INT:PASS.DOUBLE.H1.0.0.OUT.LR.IOB1.I2.S	0.25.10
INT:PASS.DOUBLE.H1.1.0.OUT.STARTUP.Q3	0.21.10
INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E	0.13.4
INT:PASS.DOUBLE.V0.1.0.OUT.STARTUP.Q2	0.13.6
INT:PASS.DOUBLE.V1.0.0.OUT.STARTUP.DONEIN	0.30.4
INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E	0.39.6
INT:PASS.IO.DOUBLE.0.E.0.0.IO.DBUF.V0	0.14.9
INT:PASS.IO.DOUBLE.0.E.1.0.IO.DBUF.H1	0.23.2
INT:PASS.IO.DOUBLE.0.S.1.0.GCLK4	0.44.2
INT:PASS.IO.DOUBLE.0.S.1.0.IO.DBUF.V1	0.10.10
INT:PASS.IO.DOUBLE.0.S.2.0.IO.DBUF.H0	0.32.1
INT:PASS.IO.DOUBLE.0.S.2.0.LONG.V9	0.50.2
INT:PASS.IO.DOUBLE.1.E.0.0.IO.DBUF.V0	0.13.9
INT:PASS.IO.DOUBLE.1.E.1.0.IO.DBUF.H1	0.21.2
INT:PASS.IO.DOUBLE.1.S.1.0.IO.DBUF.V1	0.7.10
INT:PASS.IO.DOUBLE.1.S.1.0.LONG.V8	0.49.3
INT:PASS.IO.DOUBLE.1.S.2.0.GCLK5	0.43.2
INT:PASS.IO.DOUBLE.1.S.2.0.IO.DBUF.H0	0.33.1
INT:PASS.IO.DOUBLE.2.E.0.0.IO.DBUF.V0	0.11.10
INT:PASS.IO.DOUBLE.2.E.1.0.IO.DBUF.H1	0.22.2
INT:PASS.IO.DOUBLE.2.S.1.0.IO.DBUF.V1	0.9.10
INT:PASS.IO.DOUBLE.2.S.1.0.LONG.V7	0.50.0
INT:PASS.IO.DOUBLE.2.S.2.0.GCLK6	0.42.0
INT:PASS.IO.DOUBLE.2.S.2.0.IO.DBUF.H0	0.34.1
INT:PASS.IO.DOUBLE.3.E.0.0.IO.DBUF.V0	0.12.10
INT:PASS.IO.DOUBLE.3.E.1.0.IO.DBUF.H1	0.23.1
INT:PASS.IO.DOUBLE.3.S.1.0.GCLK7	0.42.2
INT:PASS.IO.DOUBLE.3.S.1.0.IO.DBUF.V1	0.8.10
INT:PASS.IO.DOUBLE.3.S.2.0.IO.DBUF.H0	0.35.1
INT:PASS.IO.DOUBLE.3.S.2.0.LONG.V6	0.48.2
INT:PASS.QUAD.H0.0.0.QBUF.0	0.45.14
INT:PASS.QUAD.H0.1.0.DEC.V3	0.5.14
INT:PASS.QUAD.H0.3.0.OUT.LR.IOB1.I2.S	0.19.14
INT:PASS.QUAD.H0.4.0.QBUF.0	0.44.14
INT:PASS.QUAD.H1.0.0.OUT.LR.IOB1.I1.S	0.17.15
INT:PASS.QUAD.H1.0.0.QBUF.1	0.42.13
INT:PASS.QUAD.H1.1.0.DEC.V2	0.5.15
INT:PASS.QUAD.H1.4.0.QBUF.1	0.44.13
INT:PASS.QUAD.H2.0.0.OUT.LR.IOB1.I2.S	0.21.14
INT:PASS.QUAD.H2.0.0.QBUF.2	0.51.14
INT:PASS.QUAD.H2.1.0.DEC.V1	0.16.14
INT:PASS.QUAD.H2.3.0.OUT.LR.IOB1.I1.S	0.16.15
INT:PASS.QUAD.H2.4.0.QBUF.2	0.50.14
INT:PASS.QUAD.V0.0.0.QBUF.0	0.46.14
INT:PASS.QUAD.V0.3.0.DEC.H2	0.46.0
INT:PASS.QUAD.V0.3.0.OUT.BT.IOB1.I2.E	0.44.5
INT:PASS.QUAD.V0.4.0.QBUF.0	0.43.14
INT:PASS.QUAD.V1.0.0.OUT.BT.IOB1.I1.E	0.43.0
INT:PASS.QUAD.V1.0.0.QBUF.1	0.42.14
INT:PASS.QUAD.V1.3.0.DEC.H1	0.45.2
INT:PASS.QUAD.V1.4.0.QBUF.1	0.43.13
INT:PASS.QUAD.V2.0.0.OUT.BT.IOB1.I2.E	0.42.5
INT:PASS.QUAD.V2.0.0.QBUF.2	0.51.15
INT:PASS.QUAD.V2.3.0.DEC.H0	0.50.5
INT:PASS.QUAD.V2.3.0.OUT.BT.IOB1.I1.E	0.49.4
INT:PASS.QUAD.V2.4.0.QBUF.2	0.49.14
INT:PASS.SINGLE.H0.0.DEC.V0	0.10.9
INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S	0.24.10
INT:PASS.SINGLE.H0.E.0.LONG.V6	0.47.11
INT:PASS.SINGLE.H1.0.LONG.IO.V0	0.16.10
INT:PASS.SINGLE.H1.0.OUT.STARTUP.Q3	0.20.10
INT:PASS.SINGLE.H1.E.0.LONG.V0	0.33.9
INT:PASS.SINGLE.H2.0.LONG.IO.V1	0.16.9
INT:PASS.SINGLE.H2.0.OUT.STARTUP.Q1Q4	0.5.11
INT:PASS.SINGLE.H2.E.0.LONG.V1	0.41.13
INT:PASS.SINGLE.H3.0.DEC.V1	0.8.13
INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S	0.11.9
INT:PASS.SINGLE.H3.E.0.LONG.V2	0.35.10
INT:PASS.SINGLE.H3.E.0.LONG.V7	0.42.11
INT:PASS.SINGLE.H4.0.DEC.V2	0.8.9
INT:PASS.SINGLE.H4.0.LONG.V3	0.36.8
INT:PASS.SINGLE.H4.0.OUT.LR.IOB1.I2.S	0.23.10
INT:PASS.SINGLE.H4.E.0.LONG.V8	0.48.8
INT:PASS.SINGLE.H5.0.LONG.IO.V2	0.9.9
INT:PASS.SINGLE.H5.0.LONG.V4	0.29.8
INT:PASS.SINGLE.H5.0.OUT.STARTUP.Q3	0.22.10
INT:PASS.SINGLE.H6.0.LONG.IO.V3	0.15.10
INT:PASS.SINGLE.H6.0.LONG.V5	0.35.13
INT:PASS.SINGLE.H6.0.OUT.STARTUP.Q1Q4	0.7.11
INT:PASS.SINGLE.H7.0.DEC.V3	0.5.10
INT:PASS.SINGLE.H7.0.OUT.LR.IOB1.I1.S	0.6.10
INT:PASS.SINGLE.H7.E.0.LONG.V9	0.49.8
INT:PASS.SINGLE.V0.0.DEC.H3	0.14.4
INT:PASS.SINGLE.V0.0.GND	0.27.10
INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E	0.27.5
INT:PASS.SINGLE.V1.0.LONG.IO.H0	0.18.4
INT:PASS.SINGLE.V1.0.OUT.STARTUP.DONEIN	0.28.6
INT:PASS.SINGLE.V2.0.LONG.IO.H1	0.19.4
INT:PASS.SINGLE.V2.0.OUT.STARTUP.Q2	0.12.6
INT:PASS.SINGLE.V3.0.DEC.H2	0.37.6
INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E	0.31.4
INT:PASS.SINGLE.V4.0.DEC.H1	0.40.6
INT:PASS.SINGLE.V4.0.LONG.H3	0.27.11
INT:PASS.SINGLE.V4.0.OUT.BT.IOB1.I2.E	0.41.6
INT:PASS.SINGLE.V5.0.LONG.H4	0.41.9
INT:PASS.SINGLE.V5.0.LONG.IO.H2	0.29.4
INT:PASS.SINGLE.V5.0.OUT.STARTUP.DONEIN	0.28.4
INT:PASS.SINGLE.V6.0.LONG.H5	0.41.11
INT:PASS.SINGLE.V6.0.LONG.IO.H3	0.10.5
INT:PASS.SINGLE.V6.0.OUT.STARTUP.Q2	0.11.6
INT:PASS.SINGLE.V7.0.DEC.H0	0.35.4
INT:PASS.SINGLE.V7.0.GND	0.27.13
INT:PASS.SINGLE.V7.0.OUT.BT.IOB1.I1.E	0.37.4
MISC:FIX_DISCHARGE	0.1.3
MISC:TCTEST	0.4.1
PULLUP_DEC0_H:ENABLE	0.40.3
PULLUP_DEC0_V:ENABLE	0.8.5
PULLUP_DEC1_H:ENABLE	0.38.4
PULLUP_DEC1_V:ENABLE	0.11.5
PULLUP_DEC2_H:ENABLE	0.39.4
PULLUP_DEC2_V:ENABLE	0.9.5
PULLUP_DEC3_H:ENABLE	0.40.4
PULLUP_DEC3_V:ENABLE	0.12.5
STARTUP:CRC	0.0.1
STARTUP:ENABLE.GSR	0.8.1
STARTUP:ENABLE.GTS	0.5.1
STARTUP:EXPRESS_MODE	0.7.3
STARTUP:INV.GSR	0.9.1
STARTUP:INV.GTS	0.7.1
STARTUP:SYNC_TO_DONE	0.11.1
inverted	~[0]

INT:MUX.ECLK.H	0.42.3	0.43.3	0.44.3	0.45.4	0.42.4	0.44.4	0.43.4
0.LONG.IO.H1	0	0	1	1	0	0	1
0.GCLK5	0	0	1	1	0	1	0
0.SINGLE.V3	0	0	1	1	1	1	1
0.OUT.BUFGE.V	0	1	0	1	0	0	1
0.GCLK6	0	1	0	1	0	1	0
0.SINGLE.V4	0	1	0	1	1	1	1
0.LONG.IO.H3	0	1	1	0	0	0	1
0.GCLK7	0	1	1	0	0	1	0
0.SINGLE.V5	0	1	1	0	1	1	1
0.LONG.IO.H0	1	1	1	1	0	0	1
0.GCLK4	1	1	1	1	0	1	0
0.SINGLE.V2	1	1	1	1	1	1	1

INT:MUX.ECLK.V	0.7.14	0.11.14	0.10.14	0.9.14	0.8.14	0.12.14	0.14.14
0.LONG.IO.H3	0	0	1	1	0	0	1
0.SINGLE.H2	0	0	1	1	1	1	1
0.LONG.IO.H1	0	1	0	1	0	0	1
0.SINGLE.H3	0	1	0	1	1	1	1
0.LONG.IO.H0	0	1	1	0	0	0	1
0.SINGLE.H4	0	1	1	0	1	1	1
0.OUT.BUFGE.H	0	1	1	1	0	1	0
0.IO.DOUBLE.3.E.1	1	1	1	1	0	0	1
0.SINGLE.H5	1	1	1	1	1	1	1

INT:MUX.IMUX.BUFG.H	0.22.1	0.21.3	0.26.2	0.26.1	0.26.3	0.21.1	0.20.2
0.IO.DOUBLE.3.E.1	0	0	0	1	1	0	1
0.IO.DOUBLE.0.E.1	0	0	0	1	1	1	1
0.IO.DOUBLE.2.S.1	0	0	1	0	1	0	1
0.IO.DOUBLE.0.S.1	0	0	1	0	1	1	1
0.IO.DOUBLE.3.S.1	0	0	1	1	0	0	1
0.IO.DOUBLE.1.E.1	0	0	1	1	0	1	1
0.IO.DOUBLE.1.S.1	0	1	1	1	1	0	1
0.IO.DOUBLE.2.E.1	0	1	1	1	1	1	1
0.OUT.IOB.CLKIN.E	1	0	1	1	1	1	0
NONE	1	0	1	1	1	1	1

INT:MUX.IMUX.BUFG.V	0.16.6	0.17.6	0.18.6	0.20.6	0.19.6	0.15.6
0.IO.OCTAL.E.7	0	0	0	1	1	1
0.LONG.IO.H0	0	0	1	0	1	1
0.LONG.IO.V0	0	0	1	1	0	1
0.IO.OCTAL.E.0	0	1	1	1	1	1
0.OUT.IOB.CLKIN.S	1	0	1	1	1	0
NONE	1	0	1	1	1	1

INT:MUX.IMUX.CLB.C4	0.25.14	0.24.14	0.25.15	0.23.14	0.24.15
0.LONG.V0	0	1	1	1	1
0.LONG.V4	1	0	1	1	1
0.LONG.V6	1	1	0	1	1
0.LONG.V8	1	1	1	0	1
0.GCLK5	1	1	1	1	0
NONE	1	1	1	1	1

INT:MUX.IMUX.CLB.F4	0.15.14	0.15.15
0.LONG.V7	0	1
0.LONG.V9	1	0
0.GCLK4	1	1

INT:MUX.IMUX.CLB.G4	0.13.15	0.13.14
0.LONG.V9	0	1
0.GCLK4	1	0
0.LONG.V6	1	1

INT:MUX.IMUX.READCLK.I	0.4.9	0.7.9	0.6.9	0.5.9
0.SINGLE.H2	0	0	1	1
0.SINGLE.H3	0	1	0	1
0.SINGLE.H4	0	1	1	0
0.SINGLE.H5	1	1	1	1

INT:MUX.IMUX.STARTUP.CLK	0.38.8	0.39.8	0.40.8	0.41.8
0.SINGLE.V3	0	0	1	1
0.SINGLE.V4	0	1	0	1
0.SINGLE.V5	0	1	1	0
0.SINGLE.V2	1	1	1	1

INT:MUX.IMUX.STARTUP.GSR	0.30.6	0.29.6	0.34.6	0.32.6	0.31.6	0.33.6
0.SINGLE.H2	0	0	0	1	1	1
0.SINGLE.H3	0	0	1	0	1	1
0.LONG.V4	0	0	1	1	1	0
0.LONG.V5	0	1	0	1	1	1
0.DOUBLE.V1.1	0	1	1	0	1	1
0.SINGLE.H4	0	1	1	1	0	1
0.LONG.V3	0	1	1	1	1	0
0.DOUBLE.V0.0	1	0	1	1	1	1
0.SINGLE.H5	1	1	1	1	1	1

INT:MUX.IMUX.STARTUP.GTS	0.31.5	0.32.5	0.33.5	0.34.5	0.35.5	0.30.5
0.LONG.H3	0	0	1	1	1	0
0.SINGLE.V2	0	0	1	1	1	1
0.SINGLE.V3	0	1	0	1	1	1
0.LONG.H5	0	1	1	0	1	0
0.SINGLE.V4	0	1	1	0	1	1
0.LONG.H4	0	1	1	1	0	0
0.SINGLE.V5	0	1	1	1	0	1
0.DOUBLE.H1.0	1	1	1	1	1	0
0.DOUBLE.H0.1	1	1	1	1	1	1

INT:MUX.IO.DBUF.H0	0.7.4	0.11.4	0.8.4	0.9.4
0.IO.DOUBLE.0.E.1	0	0	1	1
0.IO.DOUBLE.2.E.1	0	1	0	1
0.IO.DOUBLE.3.E.1	0	1	1	0
0.IO.DOUBLE.1.E.1	1	1	1	1

INT:MUX.IO.DBUF.H1	0.39.2	0.40.2	0.39.1	0.40.1
0.IO.DOUBLE.1.S.2	0	0	1	1
0.IO.DOUBLE.2.S.2	0	1	0	1
0.IO.DOUBLE.3.S.2	0	1	1	0
0.IO.DOUBLE.0.S.2	1	1	1	1

INT:MUX.IO.DBUF.V0	0.4.11	0.5.13	0.7.13	0.6.13
0.IO.DOUBLE.1.S.1	0	0	1	1
0.IO.DOUBLE.2.S.1	0	1	0	1
0.IO.DOUBLE.3.S.1	0	1	1	0
0.IO.DOUBLE.0.S.1	1	1	1	1

INT:MUX.IO.DBUF.V1	0.9.13	0.13.13	0.12.13	0.14.13
0.IO.DOUBLE.0.E.0	0	0	1	1
0.IO.DOUBLE.1.E.0	0	1	0	1
0.IO.DOUBLE.3.E.0	0	1	1	0
0.IO.DOUBLE.2.E.0	1	1	1	1

INT:MUX.LONG.H3	0.21.5	0.22.6
0.LONG.IO.V1	0	0
0.DEC.V2	0	1
NONE	1	1

INT:MUX.LONG.H4	0.10.6	0.6.6	0.9.6	0.7.6
0.LONG.IO.V2	0	0	0	1
0.DEC.V1	0	0	1	0
0.OUT.STARTUP.Q3	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.H5	0.18.5	0.19.5	0.21.6	0.20.5
0.LONG.IO.V3	0	0	0	1
0.DEC.V0	0	0	1	0
0.OUT.STARTUP.Q3	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.IO.H0	0.30.3	0.29.3	0.48.5	0.49.5	0.23.3	0.22.3
0.LONG.V0	0	0	1	1	1	1
0.SINGLE.V1	0	1	1	1	1	1
0.LONG.V6	1	1	0	0	1	1
0.GCLK4	1	1	0	1	1	1
0.LONG.IO.V2	1	1	1	1	0	0
0.LONG.IO.V0	1	1	1	1	0	1
NONE	1	1	1	1	1	1

INT:MUX.LONG.IO.H1	0.34.3	0.31.3	0.33.3	0.32.3	0.45.5	0.43.5	0.14.3	0.13.3
0.LONG.V1	0	0	0	1	1	1	1	1
0.LONG.V3	0	0	1	0	1	1	1	1
0.SINGLE.V2	0	1	1	1	1	1	1	1
0.LONG.V7	1	1	1	1	0	0	1	1
0.GCLK5	1	1	1	1	0	1	1	1
0.LONG.IO.V3	1	1	1	1	1	1	0	0
0.LONG.IO.V1	1	1	1	1	1	1	0	1
NONE	1	1	1	1	1	1	1	1

INT:MUX.LONG.IO.H2	0.37.3	0.35.3	0.39.3	0.38.3	0.48.6	0.49.6	0.19.3	0.20.3
0.LONG.V2	0	0	0	1	1	1	1	1
0.LONG.V4	0	0	1	0	1	1	1	1
0.SINGLE.V5	0	1	1	1	1	1	1	1
0.LONG.V8	1	1	1	1	0	0	1	1
0.GCLK6	1	1	1	1	0	1	1	1
0.LONG.IO.V0	1	1	1	1	1	1	0	0
0.LONG.IO.V2	1	1	1	1	1	1	0	1
NONE	1	1	1	1	1	1	1	1

INT:MUX.LONG.IO.H3	0.36.3	0.27.4	0.44.6	0.42.6	0.10.3	0.11.3
0.LONG.V5	0	0	1	1	1	1
0.SINGLE.V6	0	1	1	1	1	1
0.LONG.V9	1	1	0	0	1	1
0.GCLK7	1	1	0	1	1	1
0.LONG.IO.V1	1	1	1	1	0	0
0.LONG.IO.V3	1	1	1	1	0	1
NONE	1	1	1	1	1	1

INT:MUX.LONG.IO.V0	0.21.4	0.15.5	0.15.4	0.16.4
0.LONG.IO.H0	0	0	0	1
0.LONG.IO.H2	0	0	1	0
0.SINGLE.H1	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.IO.V1	0.10.4	0.5.4	0.7.5	0.5.5	0.6.5
0.LONG.H3	0	0	0	1	1
0.LONG.IO.H1	0	0	1	0	1
0.LONG.IO.H3	0	0	1	1	0
0.SINGLE.H2	0	1	1	1	1
NONE	1	1	1	1	1

INT:MUX.LONG.IO.V2	0.23.4	0.4.5	0.16.5	0.14.5	0.13.5
0.LONG.H4	0	0	0	1	1
0.LONG.IO.H0	0	0	1	0	1
0.LONG.IO.H2	0	0	1	1	0
0.SINGLE.H5	0	1	1	1	1
NONE	1	1	1	1	1

INT:MUX.LONG.IO.V3	0.17.4	0.3.5	0.6.4	0.4.4	0.12.4
0.LONG.H5	0	0	0	1	1
0.LONG.IO.H1	0	0	1	0	1
0.LONG.IO.H3	0	0	1	1	0
0.SINGLE.H6	0	1	1	1	1
NONE	1	1	1	1	1

INT:MUX.LONG.V0	0.20.4	0.22.4	0.24.4	0.25.4
0.LONG.IO.H0	0	0	0	1
0.DEC.H0	0	0	1	0
0.OUT.BT.IOB1.I2.E	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.V1	0.39.5	0.38.6	0.38.5	0.40.5
0.LONG.IO.H1	0	0	0	1
0.DEC.H1	0	0	1	0
0.OUT.BT.IOB1.I2.E	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.V2	0.29.5	0.25.6	0.28.5	0.27.6
0.LONG.IO.H2	0	0	0	1
0.DEC.H2	0	0	1	0
0.OUT.BT.IOB1.I2.E	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.V3	0.36.5	0.35.6	0.36.6	0.37.5
0.LONG.IO.H1	0	0	0	1
0.DEC.H1	0	0	1	0
0.OUT.STARTUP.DONEIN	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.V4	0.25.5	0.22.5	0.23.5	0.24.5
0.LONG.IO.H2	0	0	0	1
0.DEC.H2	0	0	1	0
0.OUT.STARTUP.DONEIN	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.V5	0.36.4	0.32.4	0.34.4	0.33.4
0.LONG.IO.H3	0	0	0	1
0.DEC.H3	0	0	1	0
0.OUT.STARTUP.DONEIN	0	1	1	1
NONE	1	1	1	1

INT:MUX.QBUF.0	0.41.14	0.40.14
0.QUAD.V0.4	0	0
0.QUAD.H0.0	0	1
0.QUAD.V0.0	1	0
0.QUAD.H0.4	1	1

INT:MUX.QBUF.1	0.46.13	0.45.13
0.QUAD.V1.4	0	0
0.QUAD.H1.0	0	1
0.QUAD.V1.0	1	0
0.QUAD.H1.4	1	1

INT:MUX.QBUF.2	0.48.14	0.47.14
0.QUAD.V2.4	0	0
0.QUAD.H2.0	0	1
0.QUAD.V2.0	1	0
0.QUAD.H2.4	1	1

INT:MUX.VCLK	0.47.0	0.49.2	0.48.1	0.47.1	0.49.1	0.50.1	0.51.1
0.LONG.IO.H0	0	0	1	1	0	0	1
0.LONG.IO.H1	0	0	1	1	0	1	0
0.IO.DOUBLE.0.S.2	0	0	1	1	1	1	1
NONE	0	1	0	1	0	0	1
0.OUT.BT.IOB1.I1.E	0	1	0	1	0	1	0
0.IO.DOUBLE.1.S.1	0	1	0	1	1	1	1
0.QUAD.V0.0	0	1	1	0	0	0	1
0.LONG.IO.H3	0	1	1	0	0	1	0
0.IO.DOUBLE.2.S.1	0	1	1	0	1	1	1
0.ECLK.H	1	1	1	1	0	0	1
0.BUFGE.H	1	1	1	1	0	1	0
0.IO.DOUBLE.3.S.2	1	1	1	1	1	1	1

OSC:ENABLE	0.0.4
non-inverted	[0]

OSC:MUX.OUT0	0.1.4	0.0.11	0.1.9	0.1.5
OSC:MUX.OUT1	0.3.4	0.0.10	0.0.9	0.0.5
F500K	0	0	1	1
F16K	0	1	0	1
F490	0	1	1	0
F15	1	1	1	1

STARTUP:CONFIG_RATE	0.0.0
FAST	0
SLOW	1

STARTUP:DONE_ACTIVE	0.12.3	0.12.1
Q2	0	0
Q3	0	1
Q1Q4	1	0
Q0	1	1

STARTUP:GSR_INACTIVE	0.15.3	0.16.3
DONE_IN	0	0
Q3	0	1
Q1Q4	1	0
Q2	1	1

STARTUP:OUTPUTS_ACTIVE	0.18.3	0.17.3
Q3	0	0
DONE_IN	0	1
Q2	1	0
Q1Q4	1	1

STARTUP:STARTUP_CLK	0.10.1
CCLK	0
USERCLK	1

Tile CNR.TR

Cells: 2 IRIs: 0

Muxes

xc4000ex CNR.TR muxes
Destination	Sources
TCELL0:SINGLE.V0	TCELL0:IO.DOUBLE.0.E.1, TCELL0:DEC.H0, TCELL0:OUT.BT.IOB1.I2.E
TCELL0:SINGLE.V1	TCELL0:IO.DOUBLE.0.N.0, TCELL0:IO.DOUBLE.0.E.2, TCELL0:LONG.H0, TCELL0:LONG.IO.H0, TCELL0:OUT.OSC.MUX1
TCELL0:SINGLE.V2	TCELL0:IO.DOUBLE.1.E.1, TCELL0:LONG.H1, TCELL0:LONG.IO.H1, TCELL0:OUT.UPDATE.O
TCELL0:SINGLE.V3	TCELL0:IO.DOUBLE.1.N.0, TCELL0:IO.DOUBLE.1.E.2, TCELL0:LONG.H2, TCELL0:DEC.H1, TCELL0:OUT.BT.IOB1.I1.E
TCELL0:SINGLE.V4	TCELL0:IO.DOUBLE.2.E.1, TCELL0:DEC.H2, TCELL0:OUT.BT.IOB1.I2.E
TCELL0:SINGLE.V5	TCELL0:IO.DOUBLE.2.N.0, TCELL0:IO.DOUBLE.2.E.2, TCELL0:LONG.IO.H2, TCELL0:OUT.OSC.MUX1
TCELL0:SINGLE.V6	TCELL0:IO.DOUBLE.3.E.1, TCELL0:LONG.IO.H3, TCELL0:OUT.UPDATE.O
TCELL0:SINGLE.V7	TCELL0:IO.DOUBLE.3.N.0, TCELL0:IO.DOUBLE.3.E.2, TCELL0:DEC.H3, TCELL0:OUT.BT.IOB1.I1.E
TCELL0:DOUBLE.V0.0	TCELL0:IO.DOUBLE.1.N.0, TCELL0:IO.DOUBLE.1.E.1, TCELL0:IO.DOUBLE.1.E.2, TCELL0:OUT.BT.IOB1.I1.E
TCELL0:DOUBLE.V0.1	TCELL0:IO.DOUBLE.0.N.0, TCELL0:IO.DOUBLE.0.E.1, TCELL0:IO.DOUBLE.0.E.2, TCELL0:OUT.UPDATE.O
TCELL0:DOUBLE.V1.0	TCELL0:IO.DOUBLE.2.N.0, TCELL0:IO.DOUBLE.2.E.1, TCELL0:IO.DOUBLE.2.E.2, TCELL0:OUT.OSC.MUX1
TCELL0:DOUBLE.V1.1	TCELL0:IO.DOUBLE.3.N.0, TCELL0:IO.DOUBLE.3.E.1, TCELL0:IO.DOUBLE.3.E.2, TCELL0:OUT.BT.IOB1.I2.E
TCELL0:IO.DOUBLE.0.N.0	TCELL0:SINGLE.V1, TCELL0:DOUBLE.V0.1, TCELL0:IO.DOUBLE.0.E.2, TCELL0:IO.DBUF.H0, TCELL0:QUAD.V0.1, TCELL0:LONG.V9
TCELL0:IO.DOUBLE.0.E.1	TCELL0:SINGLE.V0, TCELL0:DOUBLE.V0.1, TCELL0:QUAD.V0.2, TCELL0:GCLK4
TCELL0:IO.DOUBLE.0.E.2	TCELL0:SINGLE.V1, TCELL0:DOUBLE.V0.1, TCELL0:IO.DOUBLE.0.N.0, TCELL0:IO.DBUF.H1
TCELL0:IO.DOUBLE.1.N.0	TCELL0:SINGLE.V3, TCELL0:DOUBLE.V0.0, TCELL0:IO.DOUBLE.1.E.2, TCELL0:IO.DBUF.H0, TCELL0:QUAD.V0.0, TCELL0:GCLK5
TCELL0:IO.DOUBLE.1.E.1	TCELL0:SINGLE.V2, TCELL0:DOUBLE.V0.0, TCELL0:QUAD.V1.1, TCELL0:LONG.V8
TCELL0:IO.DOUBLE.1.E.2	TCELL0:SINGLE.V3, TCELL0:DOUBLE.V0.0, TCELL0:IO.DOUBLE.1.N.0, TCELL0:IO.DBUF.H1
TCELL0:IO.DOUBLE.2.N.0	TCELL0:SINGLE.V5, TCELL0:DOUBLE.V1.0, TCELL0:IO.DOUBLE.2.E.2, TCELL0:IO.DBUF.H0, TCELL0:QUAD.V1.2, TCELL0:GCLK6
TCELL0:IO.DOUBLE.2.E.1	TCELL0:SINGLE.V4, TCELL0:DOUBLE.V1.0, TCELL0:QUAD.V1.0, TCELL0:LONG.V7
TCELL0:IO.DOUBLE.2.E.2	TCELL0:SINGLE.V5, TCELL0:DOUBLE.V1.0, TCELL0:IO.DOUBLE.2.N.0, TCELL0:IO.DBUF.H1
TCELL0:IO.DOUBLE.3.N.0	TCELL0:SINGLE.V7, TCELL0:DOUBLE.V1.1, TCELL0:IO.DOUBLE.3.E.2, TCELL0:IO.DBUF.H0, TCELL0:QUAD.V2.1, TCELL0:LONG.V6
TCELL0:IO.DOUBLE.3.E.1	TCELL0:SINGLE.V6, TCELL0:DOUBLE.V1.1, TCELL0:QUAD.V2.0, TCELL0:GCLK7
TCELL0:IO.DOUBLE.3.E.2	TCELL0:SINGLE.V7, TCELL0:DOUBLE.V1.1, TCELL0:IO.DOUBLE.3.N.0, TCELL0:IO.DBUF.H1
TCELL0:IO.DBUF.H0	TCELL0:IO.DOUBLE.0.E.2, TCELL0:IO.DOUBLE.1.E.2, TCELL0:IO.DOUBLE.2.E.2, TCELL0:IO.DOUBLE.3.E.2
TCELL0:IO.DBUF.H1	TCELL0:IO.DOUBLE.0.N.0, TCELL0:IO.DOUBLE.1.N.0, TCELL0:IO.DOUBLE.2.N.0, TCELL0:IO.DOUBLE.3.N.0
TCELL0:QUAD.V0.0	TCELL0:IO.DOUBLE.1.N.0
TCELL0:QUAD.V0.1	TCELL0:IO.DOUBLE.0.N.0
TCELL0:QUAD.V0.2	TCELL0:IO.DOUBLE.0.E.1, TCELL0:DEC.H1, TCELL0:OUT.TOP.COUT.E
TCELL0:QUAD.V0.3	TCELL0:LONG.IO.H0, TCELL0:OUT.BT.IOB1.I2.E
TCELL0:QUAD.V1.0	TCELL0:IO.DOUBLE.2.E.1, TCELL0:OUT.BT.IOB1.I1.E
TCELL0:QUAD.V1.1	TCELL0:IO.DOUBLE.1.E.1
TCELL0:QUAD.V1.2	TCELL0:IO.DOUBLE.2.N.0, TCELL0:DEC.H2
TCELL0:QUAD.V1.3	TCELL0:LONG.IO.H1
TCELL0:QUAD.V2.0	TCELL0:IO.DOUBLE.3.E.1, TCELL0:OUT.BT.IOB1.I2.E
TCELL0:QUAD.V2.1	TCELL0:IO.DOUBLE.3.N.0
TCELL0:QUAD.V2.2	TCELL0:DEC.H3
TCELL0:QUAD.V2.3	TCELL0:LONG.IO.H3, TCELL0:OUT.BT.IOB1.I1.E
TCELL0:LONG.H0	TCELL0:SINGLE.V1, TCELL0:LONG.IO.V0, TCELL0:DEC.V3, TCELL0:OUT.LR.IOB1.I2
TCELL0:LONG.H1	TCELL0:SINGLE.V2, TCELL0:LONG.IO.V1, TCELL0:DEC.V2, TCELL0:OUT.LR.IOB1.I2
TCELL0:LONG.H2	TCELL0:SINGLE.V3, TCELL0:LONG.IO.V2, TCELL0:DEC.V1
TCELL0:LONG.V0	TCELL0:LONG.IO.H0, TCELL0:DEC.H3, TCELL0:OUT.BT.IOB1.I2.E
TCELL0:LONG.V1	TCELL0:LONG.IO.H1, TCELL0:DEC.H2, TCELL0:OUT.BT.IOB1.I2.E
TCELL0:LONG.V2	TCELL0:LONG.IO.H2, TCELL0:DEC.H1, TCELL0:OUT.BT.IOB1.I2.E
TCELL0:LONG.V3	TCELL0:LONG.IO.H1, TCELL0:DEC.H2, TCELL0:OUT.OSC.MUX1
TCELL0:LONG.V4	TCELL0:LONG.IO.H2, TCELL0:DEC.H1, TCELL0:OUT.OSC.MUX1
TCELL0:LONG.V5	TCELL0:LONG.IO.H3, TCELL0:DEC.H0, TCELL0:OUT.OSC.MUX1
TCELL0:LONG.V6	TCELL0:LONG.IO.H0.EXCL
TCELL0:LONG.V7	TCELL0:LONG.IO.H1.EXCL
TCELL0:LONG.V8	TCELL0:LONG.IO.H2.EXCL
TCELL0:LONG.V9	TCELL0:LONG.IO.H3.EXCL
TCELL0:LONG.IO.H0	TCELL0:SINGLE.V1, TCELL0:QUAD.V0.3, TCELL0:LONG.V0, TCELL0:LONG.IO.H0.EXCL, TCELL0:LONG.IO.V0, TCELL0:LONG.IO.V2
TCELL0:LONG.IO.H0.EXCL	TCELL0:LONG.V6, TCELL0:LONG.IO.H0, TCELL0:GCLK4
TCELL0:LONG.IO.H1	TCELL0:SINGLE.V2, TCELL0:QUAD.V1.3, TCELL0:LONG.V1, TCELL0:LONG.V3, TCELL0:LONG.IO.H1.EXCL, TCELL0:LONG.IO.V1, TCELL0:LONG.IO.V3
TCELL0:LONG.IO.H1.EXCL	TCELL0:LONG.V7, TCELL0:LONG.IO.H1, TCELL0:GCLK5
TCELL0:LONG.IO.H2	TCELL0:SINGLE.V5, TCELL0:LONG.V2, TCELL0:LONG.V4, TCELL0:LONG.IO.H2.EXCL, TCELL0:LONG.IO.V0, TCELL0:LONG.IO.V2
TCELL0:LONG.IO.H2.EXCL	TCELL0:LONG.V8, TCELL0:LONG.IO.H2, TCELL0:GCLK6
TCELL0:LONG.IO.H3	TCELL0:SINGLE.V6, TCELL0:QUAD.V2.3, TCELL0:LONG.V5, TCELL0:LONG.IO.H3.EXCL, TCELL0:LONG.IO.V1, TCELL0:LONG.IO.V3
TCELL0:LONG.IO.H3.EXCL	TCELL0:LONG.V9, TCELL0:LONG.IO.H3, TCELL0:GCLK7
TCELL0:LONG.IO.V0	TCELL0:LONG.H0, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.H2
TCELL0:LONG.IO.V1	TCELL0:LONG.H1, TCELL0:LONG.IO.H1, TCELL0:LONG.IO.H3
TCELL0:LONG.IO.V2	TCELL0:LONG.H2, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.H2
TCELL0:LONG.IO.V3	TCELL0:LONG.IO.H1, TCELL0:LONG.IO.H3
TCELL0:VCLK	TCELL0:IO.DOUBLE.0.N.0, TCELL0:IO.DOUBLE.1.E.1, TCELL0:IO.DOUBLE.2.E.1, TCELL0:IO.DOUBLE.3.N.0, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.H1, TCELL0:LONG.IO.H3, TCELL0:ECLK.H, TCELL0:BUFGE.H, TCELL0:OUT.BT.IOB1.I1.E, TCELL0:OUT.TOP.COUT.E
TCELL0:ECLK.H	TCELL0:SINGLE.V2, TCELL0:SINGLE.V3, TCELL0:SINGLE.V4, TCELL0:SINGLE.V5, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.H1, TCELL0:LONG.IO.H3, TCELL0:GCLK4, TCELL0:GCLK5, TCELL0:GCLK6, TCELL0:GCLK7, TCELL0:OUT.BUFGE.V
TCELL0:BUFGE.H	TCELL0:OUT.BUFGE.H
TCELL0:BUFGE.V1	TCELL0:OUT.BUFGE.V
TCELL0:IMUX.BUFG.H	TCELL0:IO.DOUBLE.0.E.1, TCELL0:IO.DOUBLE.0.E.2, TCELL0:IO.DOUBLE.1.E.1, TCELL0:IO.DOUBLE.1.E.2, TCELL0:IO.DOUBLE.2.E.1, TCELL0:IO.DOUBLE.2.E.2, TCELL0:IO.DOUBLE.3.E.1, TCELL0:IO.DOUBLE.3.E.2, TCELL0:OUT.IOB.CLKIN.E
TCELL0:IMUX.BUFG.V	TCELL0:IO.OCTAL.N.0, TCELL0:IO.OCTAL.N.7, TCELL0:LONG.IO.H0, TCELL0:LONG.IO.V0, TCELL0:OUT.IOB.CLKIN.N
TCELL0:IMUX.TDO.O	TCELL0:SINGLE.V2, TCELL0:SINGLE.V3, TCELL0:SINGLE.V4, TCELL0:SINGLE.V5, TCELL0:LONG.H0, TCELL0:LONG.H1, TCELL0:LONG.H2, TCELL1:DOUBLE.H0.0, TCELL1:DOUBLE.H1.1
TCELL0:IMUX.TDO.T	TCELL0:DOUBLE.V0.0, TCELL0:DOUBLE.V1.1, TCELL0:LONG.V3, TCELL0:LONG.V4, TCELL0:LONG.V5, TCELL1:SINGLE.H2, TCELL1:SINGLE.H3, TCELL1:SINGLE.H4, TCELL1:SINGLE.H5

Bel PULLUP_DEC0_H

xc4000ex CNR.TR bel PULLUP_DEC0_H
Pin	Direction	Wires
O	output	TCELL0:DEC.H0

Bel PULLUP_DEC1_H

xc4000ex CNR.TR bel PULLUP_DEC1_H
Pin	Direction	Wires
O	output	TCELL0:DEC.H1

Bel PULLUP_DEC2_H

xc4000ex CNR.TR bel PULLUP_DEC2_H
Pin	Direction	Wires
O	output	TCELL0:DEC.H2

Bel PULLUP_DEC3_H

xc4000ex CNR.TR bel PULLUP_DEC3_H
Pin	Direction	Wires
O	output	TCELL0:DEC.H3

Bel PULLUP_DEC0_V

xc4000ex CNR.TR bel PULLUP_DEC0_V
Pin	Direction	Wires
O	output	TCELL0:DEC.V0

Bel PULLUP_DEC1_V

xc4000ex CNR.TR bel PULLUP_DEC1_V
Pin	Direction	Wires
O	output	TCELL0:DEC.V1

Bel PULLUP_DEC2_V

xc4000ex CNR.TR bel PULLUP_DEC2_V
Pin	Direction	Wires
O	output	TCELL0:DEC.V2

Bel PULLUP_DEC3_V

xc4000ex CNR.TR bel PULLUP_DEC3_V
Pin	Direction	Wires
O	output	TCELL0:DEC.V3

Bel BUFGLS_H

xc4000ex CNR.TR bel BUFGLS_H
Pin	Direction	Wires

Bel BUFGLS_V

xc4000ex CNR.TR bel BUFGLS_V
Pin	Direction	Wires

Bel BUFGE_H

xc4000ex CNR.TR bel BUFGE_H
Pin	Direction	Wires
O	output	TCELL0:OUT.BUFGE.H

Bel BUFGE_V

xc4000ex CNR.TR bel BUFGE_V
Pin	Direction	Wires
O	output	TCELL0:OUT.BUFGE.V

Bel BUFG_H

xc4000ex CNR.TR bel BUFG_H
Pin	Direction	Wires
I	input	TCELL0:IMUX.BUFG.H

Bel BUFG_V

xc4000ex CNR.TR bel BUFG_V
Pin	Direction	Wires
I	input	TCELL0:IMUX.BUFG.V

Bel UPDATE

xc4000ex CNR.TR bel UPDATE
Pin	Direction	Wires
O	output	TCELL0:OUT.UPDATE.O

Bel OSC

xc4000ex CNR.TR bel OSC
Pin	Direction	Wires
F8M	output	TCELL0:OUT.LR.IOB1.I1
OUT0	output	TCELL0:OUT.LR.IOB1.I2
OUT1	output	TCELL0:OUT.OSC.MUX1

Bel TDO

xc4000ex CNR.TR bel TDO
Pin	Direction	Wires
O	input	TCELL0:IMUX.TDO.O
T	input	TCELL0:IMUX.TDO.T

Bel wires

xc4000ex CNR.TR bel wires
Wire	Pins
TCELL0:DEC.H0	PULLUP_DEC0_H.O
TCELL0:DEC.H1	PULLUP_DEC1_H.O
TCELL0:DEC.H2	PULLUP_DEC2_H.O
TCELL0:DEC.H3	PULLUP_DEC3_H.O
TCELL0:DEC.V0	PULLUP_DEC0_V.O
TCELL0:DEC.V1	PULLUP_DEC1_V.O
TCELL0:DEC.V2	PULLUP_DEC2_V.O
TCELL0:DEC.V3	PULLUP_DEC3_V.O
TCELL0:IMUX.BUFG.H	BUFG_H.I
TCELL0:IMUX.BUFG.V	BUFG_V.I
TCELL0:IMUX.TDO.O	TDO.O
TCELL0:IMUX.TDO.T	TDO.T
TCELL0:OUT.LR.IOB1.I1	OSC.F8M
TCELL0:OUT.LR.IOB1.I2	OSC.OUT0
TCELL0:OUT.OSC.MUX1	OSC.OUT1
TCELL0:OUT.UPDATE.O	UPDATE.O
TCELL0:OUT.BUFGE.H	BUFGE_H.O
TCELL0:OUT.BUFGE.V	BUFGE_V.O

Bitstream

xc4000ex CNR.TR bittile 0
Bit	Frame
Bit	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
7	-	~INT:PASS.IO.DOUBLE.2.E.1.0.LONG.V7	-	-	INT:MUX.VCLK[6]	~INT:PASS.QUAD.V0.2.0.DEC.H1	-	~INT:BIPASS.IO.DOUBLE.2.N.0.QUAD.V1.2	~INT:PASS.QUAD.V1.0.0.OUT.BT.IOB1.I1.E	~INT:PASS.IO.DOUBLE.2.N.0.0.GCLK6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC:ADDRESS_LINES[0]	-
6	INT:MUX.VCLK[0]	INT:MUX.VCLK[1]	INT:MUX.VCLK[2]	INT:MUX.VCLK[4]	INT:MUX.VCLK[3]	~INT:BIPASS.IO.DOUBLE.0.E.1.QUAD.V0.2	~INT:BIPASS.IO.DOUBLE.2.E.1.QUAD.V1.0	~INT:BIPASS.IO.DOUBLE.3.N.0.QUAD.V2.1	~INT:BIPASS.IO.DOUBLE.3.E.1.QUAD.V2.0	-	-	INT:MUX.IO.DBUF.H1[0]	INT:MUX.IO.DBUF.H1[1]	~INT:BIPASS.SINGLE.V6.IO.DOUBLE.3.E.1	~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.2	~INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.E.2	~INT:PASS.IO.DOUBLE.3.N.0.0.IO.DBUF.H0	~INT:PASS.IO.DOUBLE.2.N.0.0.IO.DBUF.H0	~INT:PASS.IO.DOUBLE.1.N.0.0.IO.DBUF.H0	~INT:PASS.IO.DOUBLE.0.N.0.0.IO.DBUF.H0	~INT:BIPASS.IO.DOUBLE.2.N.0.IO.DOUBLE.2.E.2	~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.1	~INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.E.2	~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.2	~INT:BIPASS.SINGLE.V4.IO.DOUBLE.2.E.1	INT:MUX.IMUX.BUFG.H[4]	~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.2	~INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.E.1	~INT:PASS.IO.DOUBLE.3.E.2.0.IO.DBUF.H1	INT:MUX.IMUX.BUFG.H[6]	INT:MUX.IMUX.BUFG.H[2]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
5	~INT:BIPASS.IO.DOUBLE.1.N.0.QUAD.V0.0	~INT:PASS.IO.DOUBLE.0.N.0.0.LONG.V9	INT:MUX.VCLK[5]	~INT:PASS.IO.DOUBLE.3.N.0.0.LONG.V6	~INT:BIPASS.IO.DOUBLE.1.E.1.QUAD.V1.1	~INT:BIPASS.IO.DOUBLE.0.N.0.QUAD.V0.1	~INT:PASS.QUAD.V1.2.0.DEC.H2	~INT:PASS.IO.DOUBLE.0.E.1.0.GCLK4	~INT:PASS.IO.DOUBLE.1.N.0.0.GCLK5	~INT:PASS.IO.DOUBLE.3.E.1.0.GCLK7	-	INT:MUX.IO.DBUF.H1[2]	INT:MUX.IO.DBUF.H1[3]	~INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.N.0	~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.N.0	~INT:BIPASS.IO.DOUBLE.3.N.0.IO.DOUBLE.3.E.2	~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.1	~INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.N.0	~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.N.0	~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.N.0	~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.N.0	~INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.E.1	~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.2	~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.N.0	~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.N.0	INT:MUX.IMUX.BUFG.H[3]	~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.2	~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.2	~INT:PASS.IO.DOUBLE.0.E.2.0.IO.DBUF.H1	~INT:PASS.IO.DOUBLE.2.E.2.0.IO.DBUF.H1	~INT:PASS.IO.DOUBLE.1.E.2.0.IO.DBUF.H1	INT:MUX.IMUX.BUFG.H[0]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
4	-	~INT:BIPASS.QUAD.V0.3.LONG.IO.H0	~INT:PASS.IO.DOUBLE.1.E.1.0.LONG.V8	-	-	-	-	INT:MUX.ECLK.H[4]	INT:MUX.ECLK.H[5]	INT:MUX.ECLK.H[6]	-	~PULLUP_DEC3_H:ENABLE	INT:MUX.LONG.IO.H2[5]	INT:MUX.LONG.IO.H2[4]	INT:MUX.LONG.IO.H2[7]	INT:MUX.LONG.IO.H3[5]	INT:MUX.LONG.IO.H2[6]	INT:MUX.LONG.IO.H1[7]	INT:MUX.LONG.IO.H1[5]	INT:MUX.LONG.IO.H1[4]	INT:MUX.LONG.IO.H1[6]	INT:MUX.LONG.IO.H0[5]	INT:MUX.LONG.IO.H0[4]	~INT:BIPASS.IO.DOUBLE.1.N.0.IO.DOUBLE.1.E.2	~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1	INT:MUX.IMUX.BUFG.H[1]	~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1	~INT:BIPASS.IO.DOUBLE.0.N.0.IO.DOUBLE.0.E.2	INT:MUX.LONG.IO.H0[1]	INT:MUX.LONG.IO.H0[0]	INT:MUX.IMUX.BUFG.H[5]	INT:MUX.LONG.IO.H2[0]	INT:MUX.LONG.IO.H2[1]	TDO:PULL[1]	BSCAN:ENABLE	TDO:PULL[0]	~MISC:TAC	INT:MUX.LONG.IO.H1[1]	INT:MUX.LONG.IO.H1[0]	READCLK:READ_CLK[0]	INT:MUX.LONG.IO.H3[0]	INT:MUX.LONG.IO.H3[1]	-	~TDO:ENABLE.O	~TDO:ENABLE.T	-	-	-	-	-	-	-
3	~INT:BIPASS.QUAD.V1.3.LONG.IO.H1	~INT:BIPASS.QUAD.V2.3.LONG.IO.H3	~INT:PASS.QUAD.V2.3.0.OUT.BT.IOB1.I1.E	-	-	-	INT:MUX.ECLK.H[3]	INT:MUX.ECLK.H[1]	INT:MUX.ECLK.H[0]	INT:MUX.ECLK.H[2]	-	~PULLUP_DEC0_H:ENABLE	~PULLUP_DEC1_H:ENABLE	~PULLUP_DEC2_H:ENABLE	~INT:PASS.SINGLE.V7.0.OUT.BT.IOB1.I1.E	INT:MUX.LONG.V5[3]	~INT:PASS.SINGLE.V7.0.DEC.H3	INT:MUX.LONG.V5[1]	INT:MUX.LONG.V5[0]	INT:MUX.LONG.V5[2]	~INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E	~INT:PASS.DOUBLE.V1.0.0.OUT.OSC.MUX1	~INT:PASS.SINGLE.V5.0.LONG.IO.H2	~INT:PASS.SINGLE.V5.0.OUT.OSC.MUX1	INT:MUX.LONG.IO.H3[4]	-	INT:MUX.LONG.V0[0]	INT:MUX.LONG.V0[1]	INT:MUX.LONG.IO.V2[3]	INT:MUX.LONG.V0[2]	INT:MUX.LONG.IO.V0[3]	INT:MUX.LONG.V0[3]	~INT:PASS.SINGLE.V2.0.LONG.IO.H1	~INT:PASS.SINGLE.V1.0.LONG.IO.H0	INT:MUX.LONG.IO.V3[1]	INT:MUX.LONG.IO.V0[0]	INT:MUX.LONG.IO.V0[2]	~INT:PASS.SINGLE.V0.0.DEC.H0	~INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E	INT:MUX.LONG.IO.V3[0]	INT:MUX.IO.DBUF.H0[2]	INT:MUX.LONG.IO.V1[3]	INT:MUX.IO.DBUF.H0[0]	INT:MUX.IO.DBUF.H0[1]	INT:MUX.IO.DBUF.H0[3]	-	-	-	-	-	-	-
2	~INT:PASS.QUAD.V2.2.0.DEC.H3	~INT:PASS.QUAD.V0.2.0.OUT.TOP.COUT.E	INT:MUX.LONG.IO.H0[2]	INT:MUX.LONG.IO.H0[3]	~INT:BUF.LONG.V6.0.LONG.IO.H0	~INT:BUF.LONG.V7.0.LONG.IO.H1	INT:MUX.LONG.IO.H1[3]	~INT:PASS.QUAD.V0.3.0.OUT.BT.IOB1.I2.E	INT:MUX.LONG.IO.H1[2]	~INT:PASS.QUAD.V2.0.0.OUT.BT.IOB1.I2.E	-	INT:MUX.LONG.V1[0]	INT:MUX.LONG.V1[3]	INT:MUX.LONG.V1[1]	INT:MUX.LONG.V3[0]	INT:MUX.LONG.V3[3]	INT:MUX.IMUX.TDO.O[1]	INT:MUX.IMUX.TDO.O[2]	INT:MUX.IMUX.TDO.O[3]	INT:MUX.IMUX.TDO.O[4]	INT:MUX.IMUX.TDO.O[5]	INT:MUX.IMUX.TDO.O[0]	INT:MUX.LONG.V2[3]	INT:MUX.LONG.V2[1]	~INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E	-	INT:MUX.LONG.V4[3]	INT:MUX.LONG.V4[0]	INT:MUX.LONG.V4[1]	INT:MUX.LONG.V4[2]	INT:MUX.LONG.H2[1]	INT:MUX.LONG.H0[0]	INT:MUX.LONG.H0[2]	INT:MUX.LONG.H0[3]	-	INT:MUX.LONG.IO.V2[1]	INT:MUX.LONG.IO.V0[1]	INT:MUX.LONG.IO.V2[0]	INT:MUX.LONG.IO.V2[2]	~PULLUP_DEC3_V:ENABLE	~PULLUP_DEC1_V:ENABLE	~INT:PASS.SINGLE.V6.0.LONG.IO.H3	~PULLUP_DEC2_V:ENABLE	~PULLUP_DEC0_V:ENABLE	INT:MUX.LONG.IO.V1[1]	INT:MUX.LONG.IO.V1[0]	INT:MUX.LONG.IO.V1[2]	-	-	-	-	-
1	-	-	INT:MUX.LONG.IO.H2[2]	INT:MUX.LONG.IO.H2[3]	~INT:BUF.LONG.V8.0.LONG.IO.H2	-	-	INT:MUX.LONG.IO.H3[3]	~INT:BUF.LONG.V9.0.LONG.IO.H3	INT:MUX.LONG.IO.H3[2]	~INT:PASS.SINGLE.V4.0.OUT.BT.IOB1.I2.E	~INT:PASS.SINGLE.V4.0.DEC.H2	~INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E	INT:MUX.LONG.V1[2]	~INT:PASS.SINGLE.V3.0.DEC.H1	INT:MUX.LONG.V3[1]	INT:MUX.LONG.V3[2]	INT:MUX.IMUX.TDO.T[1]	INT:MUX.IMUX.TDO.T[2]	INT:MUX.IMUX.TDO.T[3]	INT:MUX.IMUX.TDO.T[0]	INT:MUX.IMUX.TDO.T[4]	INT:MUX.IMUX.TDO.T[5]	~INT:PASS.SINGLE.V1.0.OUT.OSC.MUX1	INT:MUX.LONG.V2[0]	-	INT:MUX.LONG.V2[2]	~INT:BUF.LONG.H2.0.SINGLE.V3	-	INT:MUX.LONG.H2[0]	INT:MUX.LONG.H0[1]	INT:MUX.IMUX.BUFG.V[2]	INT:MUX.IMUX.BUFG.V[1]	INT:MUX.IMUX.BUFG.V[3]	INT:MUX.IMUX.BUFG.V[4]	INT:MUX.IMUX.BUFG.V[5]	INT:MUX.IMUX.BUFG.V[0]	~MISC:TM_RIGHT	~INT:PASS.DOUBLE.V0.1.0.OUT.UPDATE.O	~INT:PASS.SINGLE.V2.0.OUT.UPDATE.O	~INT:PASS.SINGLE.V6.0.OUT.UPDATE.O	INT:MUX.LONG.H1[3]	INT:MUX.LONG.H1[1]	-	INT:MUX.LONG.H1[0]	INT:MUX.LONG.H1[2]	-	-	-	-	-	-
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

xc4000ex CNR.TR bittile 1
Bit	Frame
Bit	35	34	33	32	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
9	-	~INT:PASS.SINGLE.V3.0.LONG.H2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
8	~INT:PASS.SINGLE.V2.0.LONG.H1	-	-	-	~INT:BUF.LONG.H1.0.SINGLE.V2	-	~INT:PASS.SINGLE.V1.0.LONG.H0	-	~INT:BUF.LONG.H0.0.SINGLE.V1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

BSCAN:ENABLE	0.17.4
non-inverted	[0]

INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1	0.27.4
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.2	0.29.5
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.N.0	0.31.5
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1	0.25.4
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.2	0.25.5
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.N.0	0.27.5
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.1	0.30.6
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.2	0.28.6
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.N.0	0.33.5
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.1	0.35.5
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.2	0.37.6
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.N.0	0.37.5
INT:BIPASS.IO.DOUBLE.0.E.1.QUAD.V0.2	0.46.6
INT:BIPASS.IO.DOUBLE.0.N.0.IO.DOUBLE.0.E.2	0.24.4
INT:BIPASS.IO.DOUBLE.0.N.0.QUAD.V0.1	0.46.5
INT:BIPASS.IO.DOUBLE.1.E.1.QUAD.V1.1	0.47.5
INT:BIPASS.IO.DOUBLE.1.N.0.IO.DOUBLE.1.E.2	0.28.4
INT:BIPASS.IO.DOUBLE.1.N.0.QUAD.V0.0	0.51.5
INT:BIPASS.IO.DOUBLE.2.E.1.QUAD.V1.0	0.45.6
INT:BIPASS.IO.DOUBLE.2.N.0.IO.DOUBLE.2.E.2	0.31.6
INT:BIPASS.IO.DOUBLE.2.N.0.QUAD.V1.2	0.44.7
INT:BIPASS.IO.DOUBLE.3.E.1.QUAD.V2.0	0.43.6
INT:BIPASS.IO.DOUBLE.3.N.0.IO.DOUBLE.3.E.2	0.36.5
INT:BIPASS.IO.DOUBLE.3.N.0.QUAD.V2.1	0.44.6
INT:BIPASS.QUAD.V0.3.LONG.IO.H0	0.50.4
INT:BIPASS.QUAD.V1.3.LONG.IO.H1	0.51.3
INT:BIPASS.QUAD.V2.3.LONG.IO.H3	0.50.3
INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.E.1	0.24.6
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.2	0.24.5
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.N.0	0.28.5
INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.E.1	0.30.5
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.2	0.25.6
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.N.0	0.32.5
INT:BIPASS.SINGLE.V4.IO.DOUBLE.2.E.1	0.27.6
INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.E.2	0.29.6
INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.N.0	0.34.5
INT:BIPASS.SINGLE.V6.IO.DOUBLE.3.E.1	0.38.6
INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.E.2	0.36.6
INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.N.0	0.38.5
INT:BUF.LONG.H0.0.SINGLE.V1	1.27.8
INT:BUF.LONG.H1.0.SINGLE.V2	1.31.8
INT:BUF.LONG.H2.0.SINGLE.V3	0.24.1
INT:BUF.LONG.V6.0.LONG.IO.H0	0.47.2
INT:BUF.LONG.V7.0.LONG.IO.H1	0.46.2
INT:BUF.LONG.V8.0.LONG.IO.H2	0.47.1
INT:BUF.LONG.V9.0.LONG.IO.H3	0.43.1
INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E	0.13.3
INT:PASS.DOUBLE.V0.1.0.OUT.UPDATE.O	0.13.1
INT:PASS.DOUBLE.V1.0.0.OUT.OSC.MUX1	0.30.3
INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E	0.39.1
INT:PASS.IO.DOUBLE.0.E.1.0.GCLK4	0.44.5
INT:PASS.IO.DOUBLE.0.E.2.0.IO.DBUF.H1	0.23.5
INT:PASS.IO.DOUBLE.0.N.0.0.IO.DBUF.H0	0.32.6
INT:PASS.IO.DOUBLE.0.N.0.0.LONG.V9	0.50.5
INT:PASS.IO.DOUBLE.1.E.1.0.LONG.V8	0.49.4
INT:PASS.IO.DOUBLE.1.E.2.0.IO.DBUF.H1	0.21.5
INT:PASS.IO.DOUBLE.1.N.0.0.GCLK5	0.43.5
INT:PASS.IO.DOUBLE.1.N.0.0.IO.DBUF.H0	0.33.6
INT:PASS.IO.DOUBLE.2.E.1.0.LONG.V7	0.50.7
INT:PASS.IO.DOUBLE.2.E.2.0.IO.DBUF.H1	0.22.5
INT:PASS.IO.DOUBLE.2.N.0.0.GCLK6	0.42.7
INT:PASS.IO.DOUBLE.2.N.0.0.IO.DBUF.H0	0.34.6
INT:PASS.IO.DOUBLE.3.E.1.0.GCLK7	0.42.5
INT:PASS.IO.DOUBLE.3.E.2.0.IO.DBUF.H1	0.23.6
INT:PASS.IO.DOUBLE.3.N.0.0.IO.DBUF.H0	0.35.6
INT:PASS.IO.DOUBLE.3.N.0.0.LONG.V6	0.48.5
INT:PASS.QUAD.V0.2.0.DEC.H1	0.46.7
INT:PASS.QUAD.V0.2.0.OUT.TOP.COUT.E	0.50.2
INT:PASS.QUAD.V0.3.0.OUT.BT.IOB1.I2.E	0.44.2
INT:PASS.QUAD.V1.0.0.OUT.BT.IOB1.I1.E	0.43.7
INT:PASS.QUAD.V1.2.0.DEC.H2	0.45.5
INT:PASS.QUAD.V2.0.0.OUT.BT.IOB1.I2.E	0.42.2
INT:PASS.QUAD.V2.2.0.DEC.H3	0.51.2
INT:PASS.QUAD.V2.3.0.OUT.BT.IOB1.I1.E	0.49.3
INT:PASS.SINGLE.V0.0.DEC.H0	0.14.3
INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E	0.27.2
INT:PASS.SINGLE.V1.0.LONG.H0	1.29.8
INT:PASS.SINGLE.V1.0.LONG.IO.H0	0.18.3
INT:PASS.SINGLE.V1.0.OUT.OSC.MUX1	0.28.1
INT:PASS.SINGLE.V2.0.LONG.H1	1.35.8
INT:PASS.SINGLE.V2.0.LONG.IO.H1	0.19.3
INT:PASS.SINGLE.V2.0.OUT.UPDATE.O	0.12.1
INT:PASS.SINGLE.V3.0.DEC.H1	0.37.1
INT:PASS.SINGLE.V3.0.LONG.H2	1.34.9
INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E	0.31.3
INT:PASS.SINGLE.V4.0.DEC.H2	0.40.1
INT:PASS.SINGLE.V4.0.OUT.BT.IOB1.I2.E	0.41.1
INT:PASS.SINGLE.V5.0.LONG.IO.H2	0.29.3
INT:PASS.SINGLE.V5.0.OUT.OSC.MUX1	0.28.3
INT:PASS.SINGLE.V6.0.LONG.IO.H3	0.10.2
INT:PASS.SINGLE.V6.0.OUT.UPDATE.O	0.11.1
INT:PASS.SINGLE.V7.0.DEC.H3	0.35.3
INT:PASS.SINGLE.V7.0.OUT.BT.IOB1.I1.E	0.37.3
MISC:TAC	0.15.4
MISC:TM_RIGHT	0.14.1
PULLUP_DEC0_H:ENABLE	0.40.3
PULLUP_DEC0_V:ENABLE	0.8.2
PULLUP_DEC1_H:ENABLE	0.39.3
PULLUP_DEC1_V:ENABLE	0.11.2
PULLUP_DEC2_H:ENABLE	0.38.3
PULLUP_DEC2_V:ENABLE	0.9.2
PULLUP_DEC3_H:ENABLE	0.40.4
PULLUP_DEC3_V:ENABLE	0.12.2
TDO:ENABLE.O	0.8.4
TDO:ENABLE.T	0.7.4
inverted	~[0]

INT:MUX.ECLK.H	0.42.4	0.43.4	0.44.4	0.45.3	0.42.3	0.44.3	0.43.3
0.LONG.IO.H1	0	0	1	1	0	0	1
0.GCLK5	0	0	1	1	0	1	0
0.SINGLE.V3	0	0	1	1	1	1	1
0.OUT.BUFGE.V	0	1	0	1	0	0	1
0.GCLK6	0	1	0	1	0	1	0
0.SINGLE.V4	0	1	0	1	1	1	1
0.LONG.IO.H3	0	1	1	0	0	0	1
0.GCLK7	0	1	1	0	0	1	0
0.SINGLE.V5	0	1	1	0	1	1	1
0.LONG.IO.H0	1	1	1	1	0	0	1
0.GCLK4	1	1	1	1	0	1	0
0.SINGLE.V2	1	1	1	1	1	1	1

INT:MUX.IMUX.BUFG.H	0.22.6	0.21.4	0.26.6	0.26.5	0.21.6	0.26.4	0.20.5
0.IO.DOUBLE.2.E.1	0	0	0	1	0	1	1
0.IO.DOUBLE.0.E.1	0	0	0	1	1	1	1
0.IO.DOUBLE.3.E.2	0	0	1	0	0	1	1
0.IO.DOUBLE.0.E.2	0	0	1	0	1	1	1
0.IO.DOUBLE.3.E.1	0	0	1	1	0	0	1
0.IO.DOUBLE.1.E.2	0	0	1	1	1	0	1
0.IO.DOUBLE.1.E.1	0	1	1	1	0	1	1
0.IO.DOUBLE.2.E.2	0	1	1	1	1	1	1
0.OUT.IOB.CLKIN.E	1	0	1	1	1	1	0
NONE	1	0	1	1	1	1	1

INT:MUX.IMUX.BUFG.V	0.16.1	0.17.1	0.18.1	0.20.1	0.19.1	0.15.1
0.IO.OCTAL.N.7	0	0	0	1	1	1
0.LONG.IO.H0	0	0	1	0	1	1
0.LONG.IO.V0	0	0	1	1	0	1
0.IO.OCTAL.N.0	0	1	1	1	1	1
0.OUT.IOB.CLKIN.N	1	0	1	1	1	0
NONE	1	0	1	1	1	1

INT:MUX.IMUX.TDO.O	0.31.2	0.32.2	0.33.2	0.34.2	0.35.2	0.30.2
0.LONG.H0	0	0	1	1	1	0
0.SINGLE.V2	0	0	1	1	1	1
0.SINGLE.V3	0	1	0	1	1	1
0.LONG.H1	0	1	1	0	1	0
0.SINGLE.V4	0	1	1	0	1	1
0.LONG.H2	0	1	1	1	0	0
0.SINGLE.V5	0	1	1	1	0	1
1.DOUBLE.H1.1	1	1	1	1	1	0
1.DOUBLE.H0.0	1	1	1	1	1	1

INT:MUX.IMUX.TDO.T	0.29.1	0.30.1	0.32.1	0.33.1	0.34.1	0.31.1
1.SINGLE.H3	0	0	0	1	1	1
0.LONG.V4	0	0	1	0	1	1
1.SINGLE.H2	0	0	1	1	0	1
0.DOUBLE.V0.0	0	1	1	1	1	1
0.DOUBLE.V1.1	1	0	0	1	1	1
0.LONG.V3	1	0	1	0	1	1
0.LONG.V5	1	0	1	1	0	1
1.SINGLE.H4	1	0	1	1	1	0
1.SINGLE.H5	1	1	1	1	1	1

INT:MUX.IO.DBUF.H0	0.7.3	0.11.3	0.8.3	0.9.3
0.IO.DOUBLE.0.E.2	0	0	1	1
0.IO.DOUBLE.2.E.2	0	1	0	1
0.IO.DOUBLE.3.E.2	0	1	1	0
0.IO.DOUBLE.1.E.2	1	1	1	1

INT:MUX.IO.DBUF.H1	0.39.5	0.40.5	0.39.6	0.40.6
0.IO.DOUBLE.1.N.0	0	0	1	1
0.IO.DOUBLE.2.N.0	0	1	0	1
0.IO.DOUBLE.3.N.0	0	1	1	0
0.IO.DOUBLE.0.N.0	1	1	1	1

INT:MUX.LONG.H0	0.18.2	0.19.2	0.21.1	0.20.2
0.LONG.IO.V0	0	0	0	1
0.DEC.V3	0	0	1	0
0.OUT.LR.IOB1.I2	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.H1	0.10.1	0.6.1	0.9.1	0.7.1
0.LONG.IO.V1	0	0	0	1
0.DEC.V2	0	0	1	0
0.OUT.LR.IOB1.I2	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.H2	0.21.2	0.22.1
0.LONG.IO.V2	0	0
0.DEC.V1	0	1
NONE	1	1

INT:MUX.LONG.IO.H0	0.30.4	0.29.4	0.48.2	0.49.2	0.23.4	0.22.4
0.LONG.V0	0	0	1	1	1	1
0.SINGLE.V1	0	1	1	1	1	1
0.LONG.V6	1	1	0	0	1	1
0.GCLK4	1	1	0	1	1	1
0.LONG.IO.V2	1	1	1	1	0	0
0.LONG.IO.V0	1	1	1	1	0	1
NONE	1	1	1	1	1	1

INT:MUX.LONG.IO.H1	0.34.4	0.31.4	0.33.4	0.32.4	0.45.2	0.43.2	0.14.4	0.13.4
0.LONG.V1	0	0	0	1	1	1	1	1
0.LONG.V3	0	0	1	0	1	1	1	1
0.SINGLE.V2	0	1	1	1	1	1	1	1
0.LONG.V7	1	1	1	1	0	0	1	1
0.GCLK5	1	1	1	1	0	1	1	1
0.LONG.IO.V3	1	1	1	1	1	1	0	0
0.LONG.IO.V1	1	1	1	1	1	1	0	1
NONE	1	1	1	1	1	1	1	1

INT:MUX.LONG.IO.H2	0.37.4	0.35.4	0.39.4	0.38.4	0.48.1	0.49.1	0.19.4	0.20.4
0.LONG.V2	0	0	0	1	1	1	1	1
0.LONG.V4	0	0	1	0	1	1	1	1
0.SINGLE.V5	0	1	1	1	1	1	1	1
0.LONG.V8	1	1	1	1	0	0	1	1
0.GCLK6	1	1	1	1	0	1	1	1
0.LONG.IO.V0	1	1	1	1	1	1	0	0
0.LONG.IO.V2	1	1	1	1	1	1	0	1
NONE	1	1	1	1	1	1	1	1

INT:MUX.LONG.IO.H3	0.36.4	0.27.3	0.44.1	0.42.1	0.10.4	0.11.4
0.LONG.V5	0	0	1	1	1	1
0.SINGLE.V6	0	1	1	1	1	1
0.LONG.V9	1	1	0	0	1	1
0.GCLK7	1	1	0	1	1	1
0.LONG.IO.V1	1	1	1	1	0	0
0.LONG.IO.V3	1	1	1	1	0	1
NONE	1	1	1	1	1	1

INT:MUX.LONG.IO.V0	0.21.3	0.15.3	0.15.2	0.16.3
0.LONG.H0	0	0	0	1
0.LONG.IO.H2	0	0	1	0
0.LONG.IO.H0	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.IO.V1	0.10.3	0.5.2	0.7.2	0.6.2
0.LONG.H1	0	0	0	1
0.LONG.IO.H3	0	0	1	0
0.LONG.IO.H1	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.IO.V2	0.23.3	0.13.2	0.16.2	0.14.2
0.LONG.H2	0	0	0	1
0.LONG.IO.H0	0	0	1	0
0.LONG.IO.H2	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.IO.V3	0.17.3	0.12.3
0.LONG.IO.H1	0	0
0.LONG.IO.H3	0	1
NONE	1	1

INT:MUX.LONG.V0	0.20.3	0.22.3	0.24.3	0.25.3
0.LONG.IO.H0	0	0	0	1
0.DEC.H3	0	0	1	0
0.OUT.BT.IOB1.I2.E	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.V1	0.39.2	0.38.1	0.38.2	0.40.2
0.LONG.IO.H1	0	0	0	1
0.DEC.H2	0	0	1	0
0.OUT.BT.IOB1.I2.E	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.V2	0.29.2	0.25.1	0.28.2	0.27.1
0.LONG.IO.H2	0	0	0	1
0.DEC.H1	0	0	1	0
0.OUT.BT.IOB1.I2.E	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.V3	0.36.2	0.35.1	0.36.1	0.37.2
0.LONG.IO.H1	0	0	0	1
0.DEC.H2	0	0	1	0
0.OUT.OSC.MUX1	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.V4	0.25.2	0.22.2	0.23.2	0.24.2
0.LONG.IO.H2	0	0	0	1
0.DEC.H1	0	0	1	0
0.OUT.OSC.MUX1	0	1	1	1
NONE	1	1	1	1

INT:MUX.LONG.V5	0.36.3	0.32.3	0.34.3	0.33.3
0.LONG.IO.H3	0	0	0	1
0.DEC.H0	0	0	1	0
0.OUT.OSC.MUX1	0	1	1	1
NONE	1	1	1	1

INT:MUX.VCLK	0.47.7	0.49.5	0.48.6	0.47.6	0.49.6	0.50.6	0.51.6
0.LONG.IO.H0	0	0	1	1	0	0	1
0.LONG.IO.H1	0	0	1	1	0	1	0
0.IO.DOUBLE.0.N.0	0	0	1	1	1	1	1
NONE	0	1	0	1	0	0	1
0.OUT.BT.IOB1.I1.E	0	1	0	1	0	1	0
0.IO.DOUBLE.1.E.1	0	1	0	1	1	1	1
0.OUT.TOP.COUT.E	0	1	1	0	0	0	1
0.LONG.IO.H3	0	1	1	0	0	1	0
0.IO.DOUBLE.2.E.1	0	1	1	0	1	1	1
0.ECLK.H	1	1	1	1	0	0	1
0.BUFGE.H	1	1	1	1	0	1	0
0.IO.DOUBLE.3.N.0	1	1	1	1	1	1	1

MISC:ADDRESS_LINES	0.1.7
22	0
18	1

READCLK:READ_CLK	0.12.4
RDBK	0
CCLK	1

TDO:PULL	0.18.4	0.16.4
PULLUP	0	1
PULLDOWN	1	0
PULLNONE	1	1

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