Splitters

Tile LLHC_CLB

Cells: 2

Switchbox LLH

xc4000ex LLHC_CLB switchbox LLH programmable buffers
Destination	Source	Bit
W.LONG_H[0]	E.LONG_H[0]	!LLH_S[0][6]
W.LONG_H[1]	E.LONG_H[1]	!LLH_S[0][4]
W.LONG_H[4]	E.LONG_H[4]	!LLH[0][1]
W.LONG_H[5]	E.LONG_H[5]	!LLH[0][3]
E.LONG_H[0]	W.LONG_H[0]	!LLH_S[0][5]
E.LONG_H[1]	W.LONG_H[1]	!LLH_S[0][7]
E.LONG_H[4]	W.LONG_H[4]	!LLH[0][0]
E.LONG_H[5]	W.LONG_H[5]	!LLH[0][2]

Bels PULLUP

xc4000ex LLHC_CLB bel PULLUP pins
Pin	Direction	PULLUP_TBUF_W[0]	PULLUP_TBUF_W[1]	PULLUP_TBUF_E[0]	PULLUP_TBUF_E[1]
O	bidir	W.LONG_H[2]	W.LONG_H[3]	E.LONG_H[2]	E.LONG_H[3]

xc4000ex LLHC_CLB bel PULLUP attribute bits
Attribute	PULLUP_TBUF_W[0]	PULLUP_TBUF_W[1]	PULLUP_TBUF_E[0]	PULLUP_TBUF_E[1]
ENABLE	!LLH_S[1][4]	!LLH[1][10]	!LLH_S[0][9]	!LLH[1][7]

Bels TBUF_SPLITTER

xc4000ex LLHC_CLB bel TBUF_SPLITTER pins
Pin	Direction	TBUF_SPLITTER[0]	TBUF_SPLITTER[1]
W	bidir	W.LONG_H[2]	W.LONG_H[3]
E	bidir	E.LONG_H[2]	E.LONG_H[3]

xc4000ex LLHC_CLB bel TBUF_SPLITTER attribute bits
Attribute	TBUF_SPLITTER[0]	TBUF_SPLITTER[1]
BUF_W	!LLH_S[1][9]	!LLH[0][11]
BUF_E	!LLH_S[1][8]	!LLH[0][10]
PASS	!LLH_S[1][6]	!LLH[1][5]

Bel wires

xc4000ex LLHC_CLB bel wires
Wire	Pins
W.LONG_H[2]	PULLUP_TBUF_W[0].O, TBUF_SPLITTER[0].W
W.LONG_H[3]	PULLUP_TBUF_W[1].O, TBUF_SPLITTER[1].W
E.LONG_H[2]	PULLUP_TBUF_E[0].O, TBUF_SPLITTER[0].E
E.LONG_H[3]	PULLUP_TBUF_E[1].O, TBUF_SPLITTER[1].E

Bitstream

xc4000ex LLHC_CLB rect LLH
Bit	Frame
Bit	F1	F0
B11	-	TBUF_SPLITTER[1]: ! BUF_W
B10	PULLUP_TBUF_W[1]: ! ENABLE	TBUF_SPLITTER[1]: ! BUF_E
B9	-	-
B8	-	-
B7	PULLUP_TBUF_E[1]: ! ENABLE	-
B6	-	-
B5	TBUF_SPLITTER[1]: ! PASS	-
B4	-	-
B3	-	LLH: !buffer W.LONG_H[5] ← E.LONG_H[5]
B2	-	LLH: !buffer E.LONG_H[5] ← W.LONG_H[5]
B1	-	LLH: !buffer W.LONG_H[4] ← E.LONG_H[4]
B0	-	LLH: !buffer E.LONG_H[4] ← W.LONG_H[4]

xc4000ex LLHC_CLB rect LLH_S
Bit	Frame
Bit	F1	F0
B11	-	-
B10	-	-
B9	TBUF_SPLITTER[0]: ! BUF_W	PULLUP_TBUF_E[0]: ! ENABLE
B8	TBUF_SPLITTER[0]: ! BUF_E	-
B7	-	LLH: !buffer E.LONG_H[1] ← W.LONG_H[1]
B6	TBUF_SPLITTER[0]: ! PASS	LLH: !buffer W.LONG_H[0] ← E.LONG_H[0]
B5	-	LLH: !buffer E.LONG_H[0] ← W.LONG_H[0]
B4	PULLUP_TBUF_W[0]: ! ENABLE	LLH: !buffer W.LONG_H[1] ← E.LONG_H[1]
B3	-	-
B2	-	-
B1	-	-
B0	-	-

Tile LLHC_CLB_S

Cells: 2

Switchbox LLH

xc4000ex LLHC_CLB_S switchbox LLH programmable buffers
Destination	Source	Bit
W.LONG_H[0]	E.LONG_H[0]	!LLH_S[0][15]
W.LONG_H[1]	E.LONG_H[1]	!LLH_S[0][13]
W.LONG_H[4]	E.LONG_H[4]	!LLH[0][1]
W.LONG_H[5]	E.LONG_H[5]	!LLH[0][3]
E.LONG_H[0]	W.LONG_H[0]	!LLH_S[1][15]
E.LONG_H[1]	W.LONG_H[1]	!LLH_S[1][14]
E.LONG_H[4]	W.LONG_H[4]	!LLH[0][0]
E.LONG_H[5]	W.LONG_H[5]	!LLH[0][2]

Bels PULLUP

xc4000ex LLHC_CLB_S bel PULLUP pins
Pin	Direction	PULLUP_TBUF_W[0]	PULLUP_TBUF_W[1]	PULLUP_TBUF_E[0]	PULLUP_TBUF_E[1]
O	bidir	W.LONG_H[2]	W.LONG_H[3]	E.LONG_H[2]	E.LONG_H[3]

xc4000ex LLHC_CLB_S bel PULLUP attribute bits
Attribute	PULLUP_TBUF_W[0]	PULLUP_TBUF_W[1]	PULLUP_TBUF_E[0]	PULLUP_TBUF_E[1]
ENABLE	!MAIN_SW[0][12]	!LLH[1][10]	!LLH_S[0][12]	!LLH[1][7]

Bels TBUF_SPLITTER

xc4000ex LLHC_CLB_S bel TBUF_SPLITTER pins
Pin	Direction	TBUF_SPLITTER[0]	TBUF_SPLITTER[1]
W	bidir	W.LONG_H[2]	W.LONG_H[3]
E	bidir	E.LONG_H[2]	E.LONG_H[3]

xc4000ex LLHC_CLB_S bel TBUF_SPLITTER attribute bits
Attribute	TBUF_SPLITTER[0]	TBUF_SPLITTER[1]
BUF_W	!LLH_S[0][11]	!LLH[0][11]
BUF_E	!LLH_S[1][11]	!LLH[0][10]
PASS	!LLH_S[0][14]	!LLH[1][5]

Bel wires

xc4000ex LLHC_CLB_S bel wires
Wire	Pins
W.LONG_H[2]	PULLUP_TBUF_W[0].O, TBUF_SPLITTER[0].W
W.LONG_H[3]	PULLUP_TBUF_W[1].O, TBUF_SPLITTER[1].W
E.LONG_H[2]	PULLUP_TBUF_E[0].O, TBUF_SPLITTER[0].E
E.LONG_H[3]	PULLUP_TBUF_E[1].O, TBUF_SPLITTER[1].E

Bitstream

xc4000ex LLHC_CLB_S rect LLH
Bit	Frame
Bit	F1	F0
B11	-	TBUF_SPLITTER[1]: ! BUF_W
B10	PULLUP_TBUF_W[1]: ! ENABLE	TBUF_SPLITTER[1]: ! BUF_E
B9	-	-
B8	-	-
B7	PULLUP_TBUF_E[1]: ! ENABLE	-
B6	-	-
B5	TBUF_SPLITTER[1]: ! PASS	-
B4	-	-
B3	-	LLH: !buffer W.LONG_H[5] ← E.LONG_H[5]
B2	-	LLH: !buffer E.LONG_H[5] ← W.LONG_H[5]
B1	-	LLH: !buffer W.LONG_H[4] ← E.LONG_H[4]
B0	-	LLH: !buffer E.LONG_H[4] ← W.LONG_H[4]

xc4000ex LLHC_CLB_S rect LLH_S
Bit	Frame
Bit	F1	F0
B15	LLH: !buffer E.LONG_H[0] ← W.LONG_H[0]	LLH: !buffer W.LONG_H[0] ← E.LONG_H[0]
B14	LLH: !buffer E.LONG_H[1] ← W.LONG_H[1]	TBUF_SPLITTER[0]: ! PASS
B13	-	LLH: !buffer W.LONG_H[1] ← E.LONG_H[1]
B12	-	PULLUP_TBUF_E[0]: ! ENABLE
B11	TBUF_SPLITTER[0]: ! BUF_E	TBUF_SPLITTER[0]: ! BUF_W
B10	-	-
B9	-	-
B8	-	-
B7	-	-
B6	-	-
B5	-	-
B4	-	-
B3	-	-
B2	-	-
B1	-	-
B0	-	-

xc4000ex LLHC_CLB_S rect MAIN_SW
Bit	Frame
Bit	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PULLUP_TBUF_W[0]: ! ENABLE
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile LLHC_IO_S

Cells: 2

Switchbox LLH

xc4000ex LLHC_IO_S switchbox LLH programmable buffers
Destination	Source	Bit
W.LONG_H[3]	E.LONG_H[3]	!LLH[0][8]
W.LONG_H[4]	E.LONG_H[4]	!LLH[0][5]
W.LONG_H[5]	E.LONG_H[5]	!LLH[0][3]
W.LONG_IO_H[0]	E.LONG_IO_H[0]	!LLH[0][7]
W.LONG_IO_H[1]	E.LONG_IO_H[1]	!MAIN_W[0][4]
W.LONG_IO_H[2]	E.LONG_IO_H[2]	!MAIN_W[0][2]
W.LONG_IO_H[3]	E.LONG_IO_H[3]	!LLH[0][0]
E.LONG_H[3]	W.LONG_H[3]	!LLH[1][9]
E.LONG_H[4]	W.LONG_H[4]	!LLH[1][5]
E.LONG_H[5]	W.LONG_H[5]	!LLH[1][3]
E.LONG_IO_H[0]	W.LONG_IO_H[0]	!LLH[1][6]
E.LONG_IO_H[1]	W.LONG_IO_H[1]	!LLH[1][7]
E.LONG_IO_H[2]	W.LONG_IO_H[2]	!LLH[1][2]
E.LONG_IO_H[3]	W.LONG_IO_H[3]	!LLH[1][1]

xc4000ex LLHC_IO_S switchbox LLH bidirectional pass gates
Side A	Side B	Bit
W.DEC_H[0]	E.DEC_H[0]	!MAIN_W[0][10]
W.DEC_H[1]	E.DEC_H[1]	!LLH[0][10]
W.DEC_H[2]	E.DEC_H[2]	!LLH[0][4]
W.DEC_H[3]	E.DEC_H[3]	!LLH[1][4]

Bels PULLUP

xc4000ex LLHC_IO_S bel PULLUP pins
Pin	Direction	PULLUP_DEC_W[0]	PULLUP_DEC_W[1]	PULLUP_DEC_W[2]	PULLUP_DEC_W[3]	PULLUP_DEC_E[0]	PULLUP_DEC_E[1]	PULLUP_DEC_E[2]	PULLUP_DEC_E[3]
O	bidir	W.DEC_H[0]	W.DEC_H[1]	W.DEC_H[2]	W.DEC_H[3]	E.DEC_H[0]	E.DEC_H[1]	E.DEC_H[2]	E.DEC_H[3]

xc4000ex LLHC_IO_S bel PULLUP attribute bits
Attribute	PULLUP_DEC_W[0]	PULLUP_DEC_W[1]	PULLUP_DEC_W[2]	PULLUP_DEC_W[3]	PULLUP_DEC_E[0]	PULLUP_DEC_E[1]	PULLUP_DEC_E[2]	PULLUP_DEC_E[3]
ENABLE	!MAIN_W[0][13]	!MAIN_W[0][15]	!LLH[1][12]	!LLH[1][0]	!MAIN_W[0][14]	!LLH[1][13]	!LLH[1][10]	!LLH[0][1]

Bel wires

xc4000ex LLHC_IO_S bel wires
Wire	Pins
W.DEC_H[0]	PULLUP_DEC_W[0].O
W.DEC_H[1]	PULLUP_DEC_W[1].O
W.DEC_H[2]	PULLUP_DEC_W[2].O
W.DEC_H[3]	PULLUP_DEC_W[3].O
E.DEC_H[0]	PULLUP_DEC_E[0].O
E.DEC_H[1]	PULLUP_DEC_E[1].O
E.DEC_H[2]	PULLUP_DEC_E[2].O
E.DEC_H[3]	PULLUP_DEC_E[3].O

Bitstream

xc4000ex LLHC_IO_S rect LLH
Bit	Frame
Bit	F1	F0
B15	-	-
B14	-	-
B13	PULLUP_DEC_E[1]: ! ENABLE	-
B12	PULLUP_DEC_W[2]: ! ENABLE	-
B11	-	-
B10	PULLUP_DEC_E[2]: ! ENABLE	LLH: !bipass W.DEC_H[1] = E.DEC_H[1]
B9	LLH: !buffer E.LONG_H[3] ← W.LONG_H[3]	-
B8	-	LLH: !buffer W.LONG_H[3] ← E.LONG_H[3]
B7	LLH: !buffer E.LONG_IO_H[1] ← W.LONG_IO_H[1]	LLH: !buffer W.LONG_IO_H[0] ← E.LONG_IO_H[0]
B6	LLH: !buffer E.LONG_IO_H[0] ← W.LONG_IO_H[0]	-
B5	LLH: !buffer E.LONG_H[4] ← W.LONG_H[4]	LLH: !buffer W.LONG_H[4] ← E.LONG_H[4]
B4	LLH: !bipass W.DEC_H[3] = E.DEC_H[3]	LLH: !bipass W.DEC_H[2] = E.DEC_H[2]
B3	LLH: !buffer E.LONG_H[5] ← W.LONG_H[5]	LLH: !buffer W.LONG_H[5] ← E.LONG_H[5]
B2	LLH: !buffer E.LONG_IO_H[2] ← W.LONG_IO_H[2]	-
B1	LLH: !buffer E.LONG_IO_H[3] ← W.LONG_IO_H[3]	PULLUP_DEC_E[3]: ! ENABLE
B0	PULLUP_DEC_W[3]: ! ENABLE	LLH: !buffer W.LONG_IO_H[3] ← E.LONG_IO_H[3]

xc4000ex LLHC_IO_S rect MAIN_W
Bit	Frame
Bit	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PULLUP_DEC_W[1]: ! ENABLE
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PULLUP_DEC_E[0]: ! ENABLE
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PULLUP_DEC_W[0]: ! ENABLE
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !bipass W.DEC_H[0] = E.DEC_H[0]
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !buffer W.LONG_IO_H[1] ← E.LONG_IO_H[1]
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !buffer W.LONG_IO_H[2] ← E.LONG_IO_H[2]
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile LLHC_IO_N

Cells: 2

Switchbox LLH

xc4000ex LLHC_IO_N switchbox LLH programmable buffers
Destination	Source	Bit
W.LONG_H[0]	E.LONG_H[0]	!LLH_S[0][6]
W.LONG_H[1]	E.LONG_H[1]	!LLH_S[0][4]
W.LONG_H[2]	E.LONG_H[2]	!LLH_S[1][9]
W.LONG_IO_H[0]	E.LONG_IO_H[0]	!MAIN_W[0][0]
W.LONG_IO_H[1]	E.LONG_IO_H[1]	!LLH[1][1]
W.LONG_IO_H[2]	E.LONG_IO_H[2]	!LLH[1][4]
W.LONG_IO_H[3]	E.LONG_IO_H[3]	!LLH[1][5]
E.LONG_H[0]	W.LONG_H[0]	!LLH_S[0][5]
E.LONG_H[1]	W.LONG_H[1]	!LLH_S[0][7]
E.LONG_H[2]	W.LONG_H[2]	!LLH_S[1][8]
E.LONG_IO_H[0]	W.LONG_IO_H[0]	!MAIN_W[0][1]
E.LONG_IO_H[1]	W.LONG_IO_H[1]	!LLH[0][1]
E.LONG_IO_H[2]	W.LONG_IO_H[2]	!LLH[0][4]
E.LONG_IO_H[3]	W.LONG_IO_H[3]	!LLH[0][5]

xc4000ex LLHC_IO_N switchbox LLH bidirectional pass gates
Side A	Side B	Bit
W.DEC_H[0]	E.DEC_H[0]	!MAIN_W[0][3]
W.DEC_H[1]	E.DEC_H[1]	!MAIN_W[0][5]
W.DEC_H[2]	E.DEC_H[2]	!MAIN_W[0][7]
W.DEC_H[3]	E.DEC_H[3]	!MAIN_W[0][2]

Bels PULLUP

xc4000ex LLHC_IO_N bel PULLUP pins
Pin	Direction	PULLUP_DEC_W[0]	PULLUP_DEC_W[1]	PULLUP_DEC_W[2]	PULLUP_DEC_W[3]	PULLUP_DEC_E[0]	PULLUP_DEC_E[1]	PULLUP_DEC_E[2]	PULLUP_DEC_E[3]
O	bidir	W.DEC_H[0]	W.DEC_H[1]	W.DEC_H[2]	W.DEC_H[3]	E.DEC_H[0]	E.DEC_H[1]	E.DEC_H[2]	E.DEC_H[3]

xc4000ex LLHC_IO_N bel PULLUP attribute bits
Attribute	PULLUP_DEC_W[0]	PULLUP_DEC_W[1]	PULLUP_DEC_W[2]	PULLUP_DEC_W[3]	PULLUP_DEC_E[0]	PULLUP_DEC_E[1]	PULLUP_DEC_E[2]	PULLUP_DEC_E[3]
ENABLE	!LLH[0][2]	!LLH[0][6]	!LLH[1][3]	!LLH[1][0]	!LLH[1][2]	!LLH[1][6]	!LLH[0][3]	!LLH[0][0]

Bel wires

xc4000ex LLHC_IO_N bel wires
Wire	Pins
W.DEC_H[0]	PULLUP_DEC_W[0].O
W.DEC_H[1]	PULLUP_DEC_W[1].O
W.DEC_H[2]	PULLUP_DEC_W[2].O
W.DEC_H[3]	PULLUP_DEC_W[3].O
E.DEC_H[0]	PULLUP_DEC_E[0].O
E.DEC_H[1]	PULLUP_DEC_E[1].O
E.DEC_H[2]	PULLUP_DEC_E[2].O
E.DEC_H[3]	PULLUP_DEC_E[3].O

Bitstream

xc4000ex LLHC_IO_N rect LLH
Bit	Frame
Bit	F1	F0
B7	-	-
B6	PULLUP_DEC_E[1]: ! ENABLE	PULLUP_DEC_W[1]: ! ENABLE
B5	LLH: !buffer W.LONG_IO_H[3] ← E.LONG_IO_H[3]	LLH: !buffer E.LONG_IO_H[3] ← W.LONG_IO_H[3]
B4	LLH: !buffer W.LONG_IO_H[2] ← E.LONG_IO_H[2]	LLH: !buffer E.LONG_IO_H[2] ← W.LONG_IO_H[2]
B3	PULLUP_DEC_W[2]: ! ENABLE	PULLUP_DEC_E[2]: ! ENABLE
B2	PULLUP_DEC_E[0]: ! ENABLE	PULLUP_DEC_W[0]: ! ENABLE
B1	LLH: !buffer W.LONG_IO_H[1] ← E.LONG_IO_H[1]	LLH: !buffer E.LONG_IO_H[1] ← W.LONG_IO_H[1]
B0	PULLUP_DEC_W[3]: ! ENABLE	PULLUP_DEC_E[3]: ! ENABLE

xc4000ex LLHC_IO_N rect LLH_S
Bit	Frame
Bit	F1	F0
B11	-	-
B10	-	-
B9	LLH: !buffer W.LONG_H[2] ← E.LONG_H[2]	-
B8	LLH: !buffer E.LONG_H[2] ← W.LONG_H[2]	-
B7	-	LLH: !buffer E.LONG_H[1] ← W.LONG_H[1]
B6	-	LLH: !buffer W.LONG_H[0] ← E.LONG_H[0]
B5	-	LLH: !buffer E.LONG_H[0] ← W.LONG_H[0]
B4	-	LLH: !buffer W.LONG_H[1] ← E.LONG_H[1]
B3	-	-
B2	-	-
B1	-	-
B0	-	-

xc4000ex LLHC_IO_N rect MAIN_W
Bit	Frame
Bit	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !bipass W.DEC_H[2] = E.DEC_H[2]
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !bipass W.DEC_H[1] = E.DEC_H[1]
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !bipass W.DEC_H[0] = E.DEC_H[0]
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !bipass W.DEC_H[3] = E.DEC_H[3]
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !buffer E.LONG_IO_H[0] ← W.LONG_IO_H[0]
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !buffer W.LONG_IO_H[0] ← E.LONG_IO_H[0]

Tile LLHQ_CLB

Cells: 2

Switchbox LLH

xc4000ex LLHQ_CLB switchbox LLH programmable buffers
Destination	Source	Bit
W.LONG_H[0]	E.LONG_H[0]	!LLH_S[0][10]
W.LONG_H[1]	E.LONG_H[1]	!LLH_S[0][8]
W.LONG_H[4]	E.LONG_H[4]	!LLH[0][3]
W.LONG_H[5]	E.LONG_H[5]	!LLH[0][0]
E.LONG_H[0]	W.LONG_H[0]	!LLH_S[0][11]
E.LONG_H[1]	W.LONG_H[1]	!LLH_S[0][9]
E.LONG_H[4]	W.LONG_H[4]	!LLH[0][2]
E.LONG_H[5]	W.LONG_H[5]	!LLH[0][1]

Bels PULLUP

xc4000ex LLHQ_CLB bel PULLUP pins
Pin	Direction	PULLUP_TBUF_W[0]	PULLUP_TBUF_W[1]	PULLUP_TBUF_E[0]	PULLUP_TBUF_E[1]
O	bidir	W.LONG_H[2]	W.LONG_H[3]	E.LONG_H[2]	E.LONG_H[3]

xc4000ex LLHQ_CLB bel PULLUP attribute bits
Attribute	PULLUP_TBUF_W[0]	PULLUP_TBUF_W[1]	PULLUP_TBUF_E[0]	PULLUP_TBUF_E[1]
ENABLE	!LLH_S[0][6]	!LLH[0][4]	!LLH_S[0][7]	!LLH[0][5]

Bel wires

xc4000ex LLHQ_CLB bel wires
Wire	Pins
W.LONG_H[2]	PULLUP_TBUF_W[0].O
W.LONG_H[3]	PULLUP_TBUF_W[1].O
E.LONG_H[2]	PULLUP_TBUF_E[0].O
E.LONG_H[3]	PULLUP_TBUF_E[1].O

Bitstream

xc4000ex LLHQ_CLB rect LLH
Bit	Frame
Bit	F0
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	PULLUP_TBUF_E[1]: ! ENABLE
B4	PULLUP_TBUF_W[1]: ! ENABLE
B3	LLH: !buffer W.LONG_H[4] ← E.LONG_H[4]
B2	LLH: !buffer E.LONG_H[4] ← W.LONG_H[4]
B1	LLH: !buffer E.LONG_H[5] ← W.LONG_H[5]
B0	LLH: !buffer W.LONG_H[5] ← E.LONG_H[5]

xc4000ex LLHQ_CLB rect LLH_S
Bit	Frame
Bit	F0
B11	LLH: !buffer E.LONG_H[0] ← W.LONG_H[0]
B10	LLH: !buffer W.LONG_H[0] ← E.LONG_H[0]
B9	LLH: !buffer E.LONG_H[1] ← W.LONG_H[1]
B8	LLH: !buffer W.LONG_H[1] ← E.LONG_H[1]
B7	PULLUP_TBUF_E[0]: ! ENABLE
B6	PULLUP_TBUF_W[0]: ! ENABLE
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

Tile LLHQ_CLB_S

Cells: 2

Switchbox LLH

xc4000ex LLHQ_CLB_S switchbox LLH programmable buffers
Destination	Source	Bit
W.LONG_H[0]	E.LONG_H[0]	!MAIN_SW[0][13]
W.LONG_H[1]	E.LONG_H[1]	!MAIN_SW[0][11]
W.LONG_H[4]	E.LONG_H[4]	!LLH[0][3]
W.LONG_H[5]	E.LONG_H[5]	!LLH[0][0]
E.LONG_H[0]	W.LONG_H[0]	!MAIN_SW[0][12]
E.LONG_H[1]	W.LONG_H[1]	!MAIN_SW[0][10]
E.LONG_H[4]	W.LONG_H[4]	!LLH[0][2]
E.LONG_H[5]	W.LONG_H[5]	!LLH[0][1]

Bels PULLUP

xc4000ex LLHQ_CLB_S bel PULLUP pins
Pin	Direction	PULLUP_TBUF_W[0]	PULLUP_TBUF_W[1]	PULLUP_TBUF_E[0]	PULLUP_TBUF_E[1]
O	bidir	W.LONG_H[2]	W.LONG_H[3]	E.LONG_H[2]	E.LONG_H[3]

xc4000ex LLHQ_CLB_S bel PULLUP attribute bits
Attribute	PULLUP_TBUF_W[0]	PULLUP_TBUF_W[1]	PULLUP_TBUF_E[0]	PULLUP_TBUF_E[1]
ENABLE	!MAIN_SW[0][14]	!LLH[0][4]	!MAIN_SW[0][15]	!LLH[0][5]

Bel wires

xc4000ex LLHQ_CLB_S bel wires
Wire	Pins
W.LONG_H[2]	PULLUP_TBUF_W[0].O
W.LONG_H[3]	PULLUP_TBUF_W[1].O
E.LONG_H[2]	PULLUP_TBUF_E[0].O
E.LONG_H[3]	PULLUP_TBUF_E[1].O

Bitstream

xc4000ex LLHQ_CLB_S rect LLH
Bit	Frame
Bit	F0
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	PULLUP_TBUF_E[1]: ! ENABLE
B4	PULLUP_TBUF_W[1]: ! ENABLE
B3	LLH: !buffer W.LONG_H[4] ← E.LONG_H[4]
B2	LLH: !buffer E.LONG_H[4] ← W.LONG_H[4]
B1	LLH: !buffer E.LONG_H[5] ← W.LONG_H[5]
B0	LLH: !buffer W.LONG_H[5] ← E.LONG_H[5]

xc4000ex LLHQ_CLB_S rect LLH_S
Bit	Frame
Bit	F0
B15	-
B14	-
B13	-
B12	-
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

xc4000ex LLHQ_CLB_S rect MAIN_SW
Bit	Frame
Bit	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PULLUP_TBUF_E[0]: ! ENABLE
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PULLUP_TBUF_W[0]: ! ENABLE
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !buffer W.LONG_H[0] ← E.LONG_H[0]
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !buffer E.LONG_H[0] ← W.LONG_H[0]
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !buffer W.LONG_H[1] ← E.LONG_H[1]
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !buffer E.LONG_H[1] ← W.LONG_H[1]
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile LLHQ_CLB_N

Cells: 2

Switchbox LLH

xc4000ex LLHQ_CLB_N switchbox LLH programmable buffers
Destination	Source	Bit
W.LONG_H[0]	E.LONG_H[0]	!LLH_S[0][10]
W.LONG_H[1]	E.LONG_H[1]	!LLH_S[0][8]
W.LONG_H[4]	E.LONG_H[4]	!LLH[0][3]
W.LONG_H[5]	E.LONG_H[5]	!LLH[0][0]
E.LONG_H[0]	W.LONG_H[0]	!LLH_S[0][11]
E.LONG_H[1]	W.LONG_H[1]	!LLH_S[0][9]
E.LONG_H[4]	W.LONG_H[4]	!LLH[0][2]
E.LONG_H[5]	W.LONG_H[5]	!LLH[0][1]

Bels PULLUP

xc4000ex LLHQ_CLB_N bel PULLUP pins
Pin	Direction	PULLUP_TBUF_W[0]	PULLUP_TBUF_W[1]	PULLUP_TBUF_E[0]	PULLUP_TBUF_E[1]
O	bidir	W.LONG_H[2]	W.LONG_H[3]	E.LONG_H[2]	E.LONG_H[3]

xc4000ex LLHQ_CLB_N bel PULLUP attribute bits
Attribute	PULLUP_TBUF_W[0]	PULLUP_TBUF_W[1]	PULLUP_TBUF_E[0]	PULLUP_TBUF_E[1]
ENABLE	!LLH_S[0][6]	!LLH[0][5]	!LLH_S[0][7]	!LLH[0][4]

Bel wires

xc4000ex LLHQ_CLB_N bel wires
Wire	Pins
W.LONG_H[2]	PULLUP_TBUF_W[0].O
W.LONG_H[3]	PULLUP_TBUF_W[1].O
E.LONG_H[2]	PULLUP_TBUF_E[0].O
E.LONG_H[3]	PULLUP_TBUF_E[1].O

Bitstream

xc4000ex LLHQ_CLB_N rect LLH
Bit	Frame
Bit	F0
B11	-
B10	-
B9	-
B8	-
B7	-
B6	-
B5	PULLUP_TBUF_W[1]: ! ENABLE
B4	PULLUP_TBUF_E[1]: ! ENABLE
B3	LLH: !buffer W.LONG_H[4] ← E.LONG_H[4]
B2	LLH: !buffer E.LONG_H[4] ← W.LONG_H[4]
B1	LLH: !buffer E.LONG_H[5] ← W.LONG_H[5]
B0	LLH: !buffer W.LONG_H[5] ← E.LONG_H[5]

xc4000ex LLHQ_CLB_N rect LLH_S
Bit	Frame
Bit	F0
B11	LLH: !buffer E.LONG_H[0] ← W.LONG_H[0]
B10	LLH: !buffer W.LONG_H[0] ← E.LONG_H[0]
B9	LLH: !buffer E.LONG_H[1] ← W.LONG_H[1]
B8	LLH: !buffer W.LONG_H[1] ← E.LONG_H[1]
B7	PULLUP_TBUF_E[0]: ! ENABLE
B6	PULLUP_TBUF_W[0]: ! ENABLE
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

Tile LLHQ_IO_S

Cells: 2

Switchbox LLH

xc4000ex LLHQ_IO_S switchbox LLH programmable buffers
Destination	Source	Bit
W.LONG_H[3]	E.LONG_H[3]	!LLH[0][11]
W.LONG_H[4]	E.LONG_H[4]	!MAIN_W[0][6]
W.LONG_H[5]	E.LONG_H[5]	!LLH[0][6]
W.LONG_IO_H[0]	E.LONG_IO_H[0]	!MAIN_W[0][4]
W.LONG_IO_H[1]	E.LONG_IO_H[1]	!LLH[0][4]
W.LONG_IO_H[2]	E.LONG_IO_H[2]	!MAIN_W[0][0]
W.LONG_IO_H[3]	E.LONG_IO_H[3]	!LLH[0][0]
E.LONG_H[3]	W.LONG_H[3]	!LLH[0][10]
E.LONG_H[4]	W.LONG_H[4]	!MAIN_W[0][7]
E.LONG_H[5]	W.LONG_H[5]	!LLH[0][7]
E.LONG_IO_H[0]	W.LONG_IO_H[0]	!MAIN_W[0][5]
E.LONG_IO_H[1]	W.LONG_IO_H[1]	!LLH[0][5]
E.LONG_IO_H[2]	W.LONG_IO_H[2]	!MAIN_W[0][1]
E.LONG_IO_H[3]	W.LONG_IO_H[3]	!LLH[0][1]

Bitstream

xc4000ex LLHQ_IO_S rect LLH
Bit	Frame
Bit	F0
B15	-
B14	-
B13	-
B12	-
B11	LLH: !buffer W.LONG_H[3] ← E.LONG_H[3]
B10	LLH: !buffer E.LONG_H[3] ← W.LONG_H[3]
B9	-
B8	-
B7	LLH: !buffer E.LONG_H[5] ← W.LONG_H[5]
B6	LLH: !buffer W.LONG_H[5] ← E.LONG_H[5]
B5	LLH: !buffer E.LONG_IO_H[1] ← W.LONG_IO_H[1]
B4	LLH: !buffer W.LONG_IO_H[1] ← E.LONG_IO_H[1]
B3	-
B2	-
B1	LLH: !buffer E.LONG_IO_H[3] ← W.LONG_IO_H[3]
B0	LLH: !buffer W.LONG_IO_H[3] ← E.LONG_IO_H[3]

xc4000ex LLHQ_IO_S rect MAIN_W
Bit	Frame
Bit	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !buffer E.LONG_H[4] ← W.LONG_H[4]
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !buffer W.LONG_H[4] ← E.LONG_H[4]
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !buffer E.LONG_IO_H[0] ← W.LONG_IO_H[0]
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !buffer W.LONG_IO_H[0] ← E.LONG_IO_H[0]
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !buffer E.LONG_IO_H[2] ← W.LONG_IO_H[2]
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LLH: !buffer W.LONG_IO_H[2] ← E.LONG_IO_H[2]

Tile LLHQ_IO_N

Cells: 2

Switchbox LLH

xc4000ex LLHQ_IO_N switchbox LLH programmable buffers
Destination	Source	Bit
W.LONG_H[0]	E.LONG_H[0]	!LLH_S[0][10]
W.LONG_H[1]	E.LONG_H[1]	!LLH_S[0][8]
W.LONG_H[2]	E.LONG_H[2]	!LLH_S[0][6]
W.LONG_IO_H[0]	E.LONG_IO_H[0]	!LLH[0][1]
W.LONG_IO_H[1]	E.LONG_IO_H[1]	!LLH[0][3]
W.LONG_IO_H[2]	E.LONG_IO_H[2]	!LLH[0][5]
W.LONG_IO_H[3]	E.LONG_IO_H[3]	!LLH[0][7]
E.LONG_H[0]	W.LONG_H[0]	!LLH_S[0][11]
E.LONG_H[1]	W.LONG_H[1]	!LLH_S[0][9]
E.LONG_H[2]	W.LONG_H[2]	!LLH_S[0][7]
E.LONG_IO_H[0]	W.LONG_IO_H[0]	!LLH[0][0]
E.LONG_IO_H[1]	W.LONG_IO_H[1]	!LLH[0][2]
E.LONG_IO_H[2]	W.LONG_IO_H[2]	!LLH[0][4]
E.LONG_IO_H[3]	W.LONG_IO_H[3]	!LLH[0][6]

Bitstream

xc4000ex LLHQ_IO_N rect LLH
Bit	Frame
Bit	F0
B7	LLH: !buffer W.LONG_IO_H[3] ← E.LONG_IO_H[3]
B6	LLH: !buffer E.LONG_IO_H[3] ← W.LONG_IO_H[3]
B5	LLH: !buffer W.LONG_IO_H[2] ← E.LONG_IO_H[2]
B4	LLH: !buffer E.LONG_IO_H[2] ← W.LONG_IO_H[2]
B3	LLH: !buffer W.LONG_IO_H[1] ← E.LONG_IO_H[1]
B2	LLH: !buffer E.LONG_IO_H[1] ← W.LONG_IO_H[1]
B1	LLH: !buffer W.LONG_IO_H[0] ← E.LONG_IO_H[0]
B0	LLH: !buffer E.LONG_IO_H[0] ← W.LONG_IO_H[0]

xc4000ex LLHQ_IO_N rect LLH_S
Bit	Frame
Bit	F0
B11	LLH: !buffer E.LONG_H[0] ← W.LONG_H[0]
B10	LLH: !buffer W.LONG_H[0] ← E.LONG_H[0]
B9	LLH: !buffer E.LONG_H[1] ← W.LONG_H[1]
B8	LLH: !buffer W.LONG_H[1] ← E.LONG_H[1]
B7	LLH: !buffer E.LONG_H[2] ← W.LONG_H[2]
B6	LLH: !buffer W.LONG_H[2] ← E.LONG_H[2]
B5	-
B4	-
B3	-
B2	-
B1	-
B0	-

xc4000ex LLHQ_IO_N rect MAIN_W
Bit	Frame
Bit	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile LLVC_CLB

Cells: 2

Switchbox LLV

xc4000ex LLVC_CLB switchbox LLV programmable buffers
Destination	Source	Bit
S.LONG_V[0]	N.LONG_V[0]	!LLV[26][1]
S.LONG_V[1]	N.LONG_V[1]	!LLV[28][1]
S.LONG_V[2]	N.LONG_V[2]	!LLV[22][1]
S.LONG_V[3]	N.LONG_V[3]	!LLV[41][1]
S.LONG_V[4]	N.LONG_V[4]	!LLV[24][1]
S.LONG_V[5]	N.LONG_V[5]	!LLV[43][1]
S.LONG_V[6]	N.LONG_V[6]	!LLV[45][1]
S.LONG_V[7]	N.LONG_V[7]	!LLV[38][1]
S.LONG_V[8]	N.LONG_V[8]	!LLV[34][1]
S.LONG_V[9]	N.LONG_V[9]	!LLV[33][1]
N.LONG_V[0]	S.LONG_V[0]	!LLV[25][1]
N.LONG_V[1]	S.LONG_V[1]	!LLV[27][1]
N.LONG_V[2]	S.LONG_V[2]	!LLV[23][1]
N.LONG_V[3]	S.LONG_V[3]	!LLV[40][1]
N.LONG_V[4]	S.LONG_V[4]	!LLV[30][1]
N.LONG_V[5]	S.LONG_V[5]	!LLV[42][1]
N.LONG_V[6]	S.LONG_V[6]	!LLV[44][1]
N.LONG_V[7]	S.LONG_V[7]	!LLV[39][1]
N.LONG_V[8]	S.LONG_V[8]	!LLV[35][1]
N.LONG_V[9]	S.LONG_V[9]	!LLV[32][1]

xc4000ex LLVC_CLB switchbox LLV muxes VCLK
Bits							Destination
LLV[5][0]	LLV[6][0]	LLV[15][0]	LLV[35][0]	LLV[14][0]	LLV[8][0]	LLV[7][0]	S.VCLK	-
LLV[19][0]	LLV[18][0]	LLV[23][0]	LLV[34][0]	LLV[29][0]	LLV[28][0]	LLV[22][0]	-	N.VCLK
							Source
0	0	0	0	1	1	1	S.QUAD_V4[0]	S.QUAD_V4[1]
0	0	0	1	0	1	1	N.LONG_V[0]	N.SINGLE_V[1]
0	0	1	0	1	0	1	N.QUAD_V0[2]	N.QUAD_V0[0]
0	0	1	0	1	1	0	N.LONG_V[6]	S.LONG_V[8]
0	0	1	1	0	0	1	N.SINGLE_V[1]	S.LONG_V[1]
0	0	1	1	0	1	0	N.SINGLE_V[2]	N.SINGLE_V[4]
0	1	0	1	1	1	1	-	S.LONG_V[5]
0	1	1	0	1	1	1	N.GCLK[5]	-
0	1	1	1	0	1	1	N.SINGLE_V[4]	-
0	1	1	1	1	0	1	-	N.SINGLE_V[6]
0	1	1	1	1	1	0	-	S.GCLK[1]
1	0	0	1	1	1	1	N.SINGLE_V[5]	-
1	0	1	0	1	1	1	-	S.GCLK[4]
1	0	1	1	0	1	1	-	N.SINGLE_V[5]
1	0	1	1	1	0	1	N.LONG_V[4]	-
1	0	1	1	1	1	0	N.GCLK[2]	-
1	1	1	1	1	1	1	N.SINGLE_V[0]	N.SINGLE_V[0]

Bitstream

xc4000ex LLVC_CLB rect LLV
Bit	Frame
Bit	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B1	-	LLV: !buffer S.LONG_V[6] ← N.LONG_V[6]	LLV: !buffer N.LONG_V[6] ← S.LONG_V[6]	LLV: !buffer S.LONG_V[5] ← N.LONG_V[5]	LLV: !buffer N.LONG_V[5] ← S.LONG_V[5]	LLV: !buffer S.LONG_V[3] ← N.LONG_V[3]	LLV: !buffer N.LONG_V[3] ← S.LONG_V[3]	LLV: !buffer N.LONG_V[7] ← S.LONG_V[7]	LLV: !buffer S.LONG_V[7] ← N.LONG_V[7]	-	-	LLV: !buffer N.LONG_V[8] ← S.LONG_V[8]	LLV: !buffer S.LONG_V[8] ← N.LONG_V[8]	LLV: !buffer S.LONG_V[9] ← N.LONG_V[9]	LLV: !buffer N.LONG_V[9] ← S.LONG_V[9]	-	LLV: !buffer N.LONG_V[4] ← S.LONG_V[4]	-	LLV: !buffer S.LONG_V[1] ← N.LONG_V[1]	LLV: !buffer N.LONG_V[1] ← S.LONG_V[1]	LLV: !buffer S.LONG_V[0] ← N.LONG_V[0]	LLV: !buffer N.LONG_V[0] ← S.LONG_V[0]	LLV: !buffer S.LONG_V[4] ← N.LONG_V[4]	LLV: !buffer N.LONG_V[2] ← S.LONG_V[2]	LLV: !buffer S.LONG_V[2] ← N.LONG_V[2]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	LLV: mux S.VCLK bit 3	LLV: mux N.VCLK bit 3	-	-	-	-	LLV: mux N.VCLK bit 2	LLV: mux N.VCLK bit 1	-	-	-	-	LLV: mux N.VCLK bit 4	LLV: mux N.VCLK bit 0	-	-	LLV: mux N.VCLK bit 6	LLV: mux N.VCLK bit 5	-	-	LLV: mux S.VCLK bit 4	LLV: mux S.VCLK bit 2	-	-	-	-	-	LLV: mux S.VCLK bit 1	LLV: mux S.VCLK bit 0	LLV: mux S.VCLK bit 5	LLV: mux S.VCLK bit 6	-	-	-	-	-

Tile LLVC_IO_W

Cells: 2

Switchbox LLV

xc4000ex LLVC_IO_W switchbox LLV programmable buffers
Destination	Source	Bit
S.LONG_IO_V[0]	N.LONG_IO_V[0]	!LLV[10][1]
S.LONG_IO_V[1]	N.LONG_IO_V[1]	!LLV[13][1]
S.LONG_IO_V[2]	N.LONG_IO_V[2]	!LLV[6][1]
S.LONG_IO_V[3]	N.LONG_IO_V[3]	!LLV[5][1]
N.LONG_IO_V[0]	S.LONG_IO_V[0]	!LLV[11][1]
N.LONG_IO_V[1]	S.LONG_IO_V[1]	!LLV[12][1]
N.LONG_IO_V[2]	S.LONG_IO_V[2]	!LLV[7][1]
N.LONG_IO_V[3]	S.LONG_IO_V[3]	!LLV[4][1]

xc4000ex LLVC_IO_W switchbox LLV bidirectional pass gates
Side A	Side B	Bit
S.DEC_V[0]	N.DEC_V[0]	!LLV[17][1]
S.DEC_V[1]	N.DEC_V[1]	!LLV[25][1]
S.DEC_V[2]	N.DEC_V[2]	!LLV[16][1]
S.DEC_V[3]	N.DEC_V[3]	!LLV[24][1]

Bels PULLUP

xc4000ex LLVC_IO_W bel PULLUP pins
Pin	Direction	PULLUP_DEC_S[0]	PULLUP_DEC_S[1]	PULLUP_DEC_S[2]	PULLUP_DEC_S[3]	PULLUP_DEC_N[0]	PULLUP_DEC_N[1]	PULLUP_DEC_N[2]	PULLUP_DEC_N[3]
O	bidir	S.DEC_V[0]	S.DEC_V[1]	S.DEC_V[2]	S.DEC_V[3]	N.DEC_V[0]	N.DEC_V[1]	N.DEC_V[2]	N.DEC_V[3]

xc4000ex LLVC_IO_W bel PULLUP attribute bits
Attribute	PULLUP_DEC_S[0]	PULLUP_DEC_S[1]	PULLUP_DEC_S[2]	PULLUP_DEC_S[3]	PULLUP_DEC_N[0]	PULLUP_DEC_N[1]	PULLUP_DEC_N[2]	PULLUP_DEC_N[3]
ENABLE	!LLV[14][1]	!LLV[20][1]	!LLV[19][1]	!LLV[23][1]	!LLV[15][1]	!LLV[21][1]	!LLV[18][1]	!LLV[22][1]

Bel wires

xc4000ex LLVC_IO_W bel wires
Wire	Pins
S.DEC_V[0]	PULLUP_DEC_S[0].O
S.DEC_V[1]	PULLUP_DEC_S[1].O
S.DEC_V[2]	PULLUP_DEC_S[2].O
S.DEC_V[3]	PULLUP_DEC_S[3].O
N.DEC_V[0]	PULLUP_DEC_N[0].O
N.DEC_V[1]	PULLUP_DEC_N[1].O
N.DEC_V[2]	PULLUP_DEC_N[2].O
N.DEC_V[3]	PULLUP_DEC_N[3].O

Bitstream

xc4000ex LLVC_IO_W rect LLV
Bit	Frame
Bit	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B1	-	LLV: !bipass S.DEC_V[1] = N.DEC_V[1]	LLV: !bipass S.DEC_V[3] = N.DEC_V[3]	PULLUP_DEC_S[3]: ! ENABLE	PULLUP_DEC_N[3]: ! ENABLE	PULLUP_DEC_N[1]: ! ENABLE	PULLUP_DEC_S[1]: ! ENABLE	PULLUP_DEC_S[2]: ! ENABLE	PULLUP_DEC_N[2]: ! ENABLE	LLV: !bipass S.DEC_V[0] = N.DEC_V[0]	LLV: !bipass S.DEC_V[2] = N.DEC_V[2]	PULLUP_DEC_N[0]: ! ENABLE	PULLUP_DEC_S[0]: ! ENABLE	LLV: !buffer S.LONG_IO_V[1] ← N.LONG_IO_V[1]	LLV: !buffer N.LONG_IO_V[1] ← S.LONG_IO_V[1]	LLV: !buffer N.LONG_IO_V[0] ← S.LONG_IO_V[0]	LLV: !buffer S.LONG_IO_V[0] ← N.LONG_IO_V[0]	-	-	LLV: !buffer N.LONG_IO_V[2] ← S.LONG_IO_V[2]	LLV: !buffer S.LONG_IO_V[2] ← N.LONG_IO_V[2]	LLV: !buffer S.LONG_IO_V[3] ← N.LONG_IO_V[3]	LLV: !buffer N.LONG_IO_V[3] ← S.LONG_IO_V[3]	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

xc4000ex LLVC_IO_W rect LLV_E
Bit	Frame
Bit	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile LLVC_IO_E

Cells: 2

Switchbox LLV

xc4000ex LLVC_IO_E switchbox LLV programmable buffers
Destination	Source	Bit
S.LONG_V[0]	N.LONG_V[0]	!LLV[16][1]
S.LONG_V[1]	N.LONG_V[1]	!LLV[34][1]
S.LONG_V[2]	N.LONG_V[2]	!LLV[27][1]
S.LONG_V[3]	N.LONG_V[3]	!LLV[20][1]
S.LONG_V[4]	N.LONG_V[4]	!LLV[26][1]
S.LONG_V[5]	N.LONG_V[5]	!LLV[9][1]
S.LONG_V[6]	N.LONG_V[6]	!LLV[50][1]
S.LONG_V[7]	N.LONG_V[7]	!LLV[43][1]
S.LONG_V[8]	N.LONG_V[8]	!LLV[39][1]
S.LONG_V[9]	N.LONG_V[9]	!LLV[38][1]
S.LONG_IO_V[0]	N.LONG_IO_V[0]	!LLV[30][1]
S.LONG_IO_V[1]	N.LONG_IO_V[1]	!LLV[13][1]
S.LONG_IO_V[2]	N.LONG_IO_V[2]	!LLV[23][1]
S.LONG_IO_V[3]	N.LONG_IO_V[3]	!LLV[18][1]
N.LONG_V[0]	S.LONG_V[0]	!LLV[15][1]
N.LONG_V[1]	S.LONG_V[1]	!LLV[32][1]
N.LONG_V[2]	S.LONG_V[2]	!LLV[28][1]
N.LONG_V[3]	S.LONG_V[3]	!LLV[19][1]
N.LONG_V[4]	S.LONG_V[4]	!LLV[25][1]
N.LONG_V[5]	S.LONG_V[5]	!LLV[10][1]
N.LONG_V[6]	S.LONG_V[6]	!LLV[49][1]
N.LONG_V[7]	S.LONG_V[7]	!LLV[44][1]
N.LONG_V[8]	S.LONG_V[8]	!LLV[40][1]
N.LONG_V[9]	S.LONG_V[9]	!LLV[37][1]
N.LONG_IO_V[0]	S.LONG_IO_V[0]	!LLV[29][1]
N.LONG_IO_V[1]	S.LONG_IO_V[1]	!LLV[14][1]
N.LONG_IO_V[2]	S.LONG_IO_V[2]	!LLV[24][1]
N.LONG_IO_V[3]	S.LONG_IO_V[3]	!LLV[17][1]

xc4000ex LLVC_IO_E switchbox LLV bidirectional pass gates
Side A	Side B	Bit
S.DEC_V[0]	N.DEC_V[0]	!LLV[4][0]
S.DEC_V[1]	N.DEC_V[1]	!LLV[7][0]
S.DEC_V[2]	N.DEC_V[2]	!LLV[5][0]
S.DEC_V[3]	N.DEC_V[3]	!LLV[35][1]

xc4000ex LLVC_IO_E switchbox LLV muxes VCLK
Bits							Destination
LLV[9][0]	LLV[10][0]	LLV[20][0]	LLV[40][0]	LLV[19][0]	LLV[12][0]	LLV[11][0]	S.VCLK	-
LLV[24][0]	LLV[23][0]	LLV[28][0]	LLV[39][0]	LLV[34][0]	LLV[33][0]	LLV[27][0]	-	N.VCLK
							Source
0	0	0	0	1	1	1	S.QUAD_V4[0]	S.QUAD_V4[1]
0	0	0	1	0	1	1	N.LONG_V[0]	N.SINGLE_V[1]
0	0	1	0	1	0	1	N.QUAD_V0[2]	N.QUAD_V0[0]
0	0	1	0	1	1	0	N.LONG_V[6]	S.LONG_V[8]
0	0	1	1	0	0	1	N.SINGLE_V[1]	S.LONG_V[1]
0	0	1	1	0	1	0	N.SINGLE_V[2]	N.SINGLE_V[4]
0	1	0	1	1	1	1	-	S.LONG_V[5]
0	1	1	0	1	1	1	N.GCLK[5]	-
0	1	1	1	0	1	1	N.SINGLE_V[4]	-
0	1	1	1	1	0	1	-	N.SINGLE_V[6]
0	1	1	1	1	1	0	-	S.GCLK[1]
1	0	0	1	1	1	1	N.SINGLE_V[5]	-
1	0	1	0	1	1	1	-	S.GCLK[4]
1	0	1	1	0	1	1	-	N.SINGLE_V[5]
1	0	1	1	1	0	1	N.LONG_V[4]	-
1	0	1	1	1	1	0	N.GCLK[2]	-
1	1	1	1	1	1	1	N.SINGLE_V[0]	N.SINGLE_V[0]

Bels PULLUP

xc4000ex LLVC_IO_E bel PULLUP pins
Pin	Direction	PULLUP_DEC_S[0]	PULLUP_DEC_S[1]	PULLUP_DEC_S[2]	PULLUP_DEC_S[3]	PULLUP_DEC_N[0]	PULLUP_DEC_N[1]	PULLUP_DEC_N[2]	PULLUP_DEC_N[3]
O	bidir	S.DEC_V[0]	S.DEC_V[1]	S.DEC_V[2]	S.DEC_V[3]	N.DEC_V[0]	N.DEC_V[1]	N.DEC_V[2]	N.DEC_V[3]

xc4000ex LLVC_IO_E bel PULLUP attribute bits
Attribute	PULLUP_DEC_S[0]	PULLUP_DEC_S[1]	PULLUP_DEC_S[2]	PULLUP_DEC_S[3]	PULLUP_DEC_N[0]	PULLUP_DEC_N[1]	PULLUP_DEC_N[2]	PULLUP_DEC_N[3]
ENABLE	!LLV[4][1]	!LLV[12][1]	!LLV[5][1]	!LLV[33][1]	!LLV[7][1]	!LLV[11][1]	!LLV[6][1]	!LLV[31][1]

Bels MISC_E

xc4000ex LLVC_IO_E bel MISC_E pins
Pin	Direction	MISC_E

xc4000ex LLVC_IO_E bel MISC_E attribute bits
Attribute	MISC_E
TLC	!LLV[2][0]

Bel wires

xc4000ex LLVC_IO_E bel wires
Wire	Pins
S.DEC_V[0]	PULLUP_DEC_S[0].O
S.DEC_V[1]	PULLUP_DEC_S[1].O
S.DEC_V[2]	PULLUP_DEC_S[2].O
S.DEC_V[3]	PULLUP_DEC_S[3].O
N.DEC_V[0]	PULLUP_DEC_N[0].O
N.DEC_V[1]	PULLUP_DEC_N[1].O
N.DEC_V[2]	PULLUP_DEC_N[2].O
N.DEC_V[3]	PULLUP_DEC_N[3].O

Bitstream

xc4000ex LLVC_IO_E rect LLV
Bit	Frame
Bit	F51	F50	F49	F48	F47	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B1	-	LLV: !buffer S.LONG_V[6] ← N.LONG_V[6]	LLV: !buffer N.LONG_V[6] ← S.LONG_V[6]	-	-	-	-	LLV: !buffer N.LONG_V[7] ← S.LONG_V[7]	LLV: !buffer S.LONG_V[7] ← N.LONG_V[7]	-	-	LLV: !buffer N.LONG_V[8] ← S.LONG_V[8]	LLV: !buffer S.LONG_V[8] ← N.LONG_V[8]	LLV: !buffer S.LONG_V[9] ← N.LONG_V[9]	LLV: !buffer N.LONG_V[9] ← S.LONG_V[9]	-	LLV: !bipass S.DEC_V[3] = N.DEC_V[3]	LLV: !buffer S.LONG_V[1] ← N.LONG_V[1]	PULLUP_DEC_S[3]: ! ENABLE	LLV: !buffer N.LONG_V[1] ← S.LONG_V[1]	PULLUP_DEC_N[3]: ! ENABLE	LLV: !buffer S.LONG_IO_V[0] ← N.LONG_IO_V[0]	LLV: !buffer N.LONG_IO_V[0] ← S.LONG_IO_V[0]	LLV: !buffer N.LONG_V[2] ← S.LONG_V[2]	LLV: !buffer S.LONG_V[2] ← N.LONG_V[2]	LLV: !buffer S.LONG_V[4] ← N.LONG_V[4]	LLV: !buffer N.LONG_V[4] ← S.LONG_V[4]	LLV: !buffer N.LONG_IO_V[2] ← S.LONG_IO_V[2]	LLV: !buffer S.LONG_IO_V[2] ← N.LONG_IO_V[2]	-	-	LLV: !buffer S.LONG_V[3] ← N.LONG_V[3]	LLV: !buffer N.LONG_V[3] ← S.LONG_V[3]	LLV: !buffer S.LONG_IO_V[3] ← N.LONG_IO_V[3]	LLV: !buffer N.LONG_IO_V[3] ← S.LONG_IO_V[3]	LLV: !buffer S.LONG_V[0] ← N.LONG_V[0]	LLV: !buffer N.LONG_V[0] ← S.LONG_V[0]	LLV: !buffer N.LONG_IO_V[1] ← S.LONG_IO_V[1]	LLV: !buffer S.LONG_IO_V[1] ← N.LONG_IO_V[1]	PULLUP_DEC_S[1]: ! ENABLE	PULLUP_DEC_N[1]: ! ENABLE	LLV: !buffer N.LONG_V[5] ← S.LONG_V[5]	LLV: !buffer S.LONG_V[5] ← N.LONG_V[5]	-	PULLUP_DEC_N[0]: ! ENABLE	PULLUP_DEC_N[2]: ! ENABLE	PULLUP_DEC_S[2]: ! ENABLE	PULLUP_DEC_S[0]: ! ENABLE	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	LLV: mux S.VCLK bit 3	LLV: mux N.VCLK bit 3	-	-	-	-	LLV: mux N.VCLK bit 2	LLV: mux N.VCLK bit 1	-	-	-	-	LLV: mux N.VCLK bit 4	LLV: mux N.VCLK bit 0	-	-	LLV: mux N.VCLK bit 6	LLV: mux N.VCLK bit 5	-	-	LLV: mux S.VCLK bit 4	LLV: mux S.VCLK bit 2	-	-	-	-	-	-	LLV: mux S.VCLK bit 1	LLV: mux S.VCLK bit 0	LLV: mux S.VCLK bit 5	LLV: mux S.VCLK bit 6	-	LLV: !bipass S.DEC_V[1] = N.DEC_V[1]	-	LLV: !bipass S.DEC_V[2] = N.DEC_V[2]	LLV: !bipass S.DEC_V[0] = N.DEC_V[0]	-	MISC_E: ! TLC	-	-

Tile LLVQ_CLB

Cells: 2

Switchbox LLV

xc4000ex LLVQ_CLB switchbox LLV programmable buffers
Destination	Source	Bit
S.LONG_V[0]	N.LONG_V[0]	!LLV[4][1]
S.LONG_V[1]	N.LONG_V[1]	!LLV[20][1]
S.LONG_V[2]	N.LONG_V[2]	!LLV[31][1]
S.LONG_V[3]	N.LONG_V[3]	!LLV[9][1]
S.LONG_V[4]	N.LONG_V[4]	!LLV[25][1]
S.LONG_V[5]	N.LONG_V[5]	!LLV[15][1]
S.LONG_V[6]	N.LONG_V[6]	!LLV[46][1]
S.LONG_V[7]	N.LONG_V[7]	!LLV[45][1]
S.LONG_V[8]	N.LONG_V[8]	!LLV[42][1]
N.LONG_V[0]	S.LONG_V[0]	!LLV[4][0]
N.LONG_V[1]	S.LONG_V[1]	!LLV[20][0]
N.LONG_V[2]	S.LONG_V[2]	!LLV[31][0]
N.LONG_V[3]	S.LONG_V[3]	!LLV[9][0]
N.LONG_V[4]	S.LONG_V[4]	!LLV[25][0]
N.LONG_V[5]	S.LONG_V[5]	!LLV[15][0]
N.LONG_V[6]	S.LONG_V[6]	!LLV[46][0]
N.LONG_V[8]	S.LONG_V[8]	!LLV[44][0]
N.LONG_V[9]	S.LONG_V[9]	!LLV[37][1]

xc4000ex LLVQ_CLB switchbox LLV pass gates
Destination	Source	Bit
S.QUAD_V4[1]	S.VCLK	!LLV[43][0]
S.QUAD_V4[2]	N.VCLK	!LLV[42][0]
N.SINGLE_V[0]	S.VCLK	!LLV[17][0]
N.SINGLE_V[1]	N.VCLK	!LLV[26][1]
N.SINGLE_V[2]	S.VCLK	!LLV[14][0]
N.SINGLE_V[3]	N.VCLK	!LLV[27][0]
N.SINGLE_V[4]	S.VCLK	!LLV[38][0]
N.SINGLE_V[5]	N.VCLK	!LLV[28][0]
N.SINGLE_V[6]	S.VCLK	!LLV[37][0]
N.SINGLE_V[7]	N.VCLK	!LLV[32][0]
N.QUAD_V0[0]	N.VCLK	!LLV[44][1]
N.QUAD_V0[2]	S.VCLK	!LLV[22][0]

xc4000ex LLVQ_CLB switchbox LLV muxes LONG_V[9]
Bits		Destination
LLV[36][0]	LLV[36][1]	S.LONG_V[9]
		Source
0	0	N.LONG_V[9]
0	1	N.VCLK
1	1	off

xc4000ex LLVQ_CLB switchbox LLV muxes GCLK[0]
Bits							Destination
LLV[28][1]	LLV[30][1]	LLV[30][0]	LLV[29][1]	LLV[29][0]	LLV[26][0]	LLV[27][1]	S.GCLK[0]
							Source
0	0	1	1	1	1	1	S.QUAD_V3[0]
0	1	0	1	1	1	1	S.VCLK
0	1	1	0	1	1	1	N.SINGLE_V[0]
0	1	1	1	0	1	1	N.VCLK
1	0	1	1	1	0	1	N.BUFGLS_H[4]
1	0	1	1	1	1	0	N.BUFGLS_H[5]
1	1	0	1	1	0	1	N.BUFGLS_H[2]
1	1	0	1	1	1	0	N.BUFGLS_H[3]
1	1	1	0	1	0	1	N.BUFGLS_H[6]
1	1	1	0	1	1	0	N.BUFGLS_H[7]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_CLB switchbox LLV muxes GCLK[1]
Bits							Destination
LLV[1][1]	LLV[3][1]	LLV[3][0]	LLV[2][1]	LLV[2][0]	LLV[0][0]	LLV[0][1]	S.GCLK[1]
							Source
0	0	1	1	1	1	1	S.QUAD_V4[0]
0	1	0	1	1	1	1	S.VCLK
0	1	1	0	1	1	1	N.SINGLE_V[1]
0	1	1	1	0	1	1	N.VCLK
1	0	1	1	1	0	1	N.BUFGLS_H[4]
1	0	1	1	1	1	0	N.BUFGLS_H[5]
1	1	0	1	1	0	1	N.BUFGLS_H[2]
1	1	0	1	1	1	0	N.BUFGLS_H[3]
1	1	1	0	1	0	1	N.BUFGLS_H[6]
1	1	1	0	1	1	0	N.BUFGLS_H[7]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_CLB switchbox LLV muxes GCLK[2]
Bits							Destination
LLV[11][1]	LLV[13][0]	LLV[12][1]	LLV[13][1]	LLV[12][0]	LLV[10][0]	LLV[10][1]	S.GCLK[2]
							Source
0	0	1	1	1	1	1	S.VCLK
0	1	0	1	1	1	1	N.SINGLE_V[2]
0	1	1	0	1	1	1	N.QUAD_V0[0]
0	1	1	1	0	1	1	N.VCLK
1	0	1	1	1	0	1	N.BUFGLS_H[2]
1	0	1	1	1	1	0	N.BUFGLS_H[3]
1	1	0	1	1	0	1	N.BUFGLS_H[6]
1	1	0	1	1	1	0	N.BUFGLS_H[7]
1	1	1	0	1	0	1	N.BUFGLS_H[4]
1	1	1	0	1	1	0	N.BUFGLS_H[5]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_CLB switchbox LLV muxes GCLK[3]
Bits							Destination
LLV[6][1]	LLV[8][1]	LLV[8][0]	LLV[7][1]	LLV[7][0]	LLV[5][0]	LLV[5][1]	S.GCLK[3]
							Source
0	0	1	1	1	1	1	S.QUAD_V4[1]
0	1	0	1	1	1	1	S.VCLK
0	1	1	0	1	1	1	N.SINGLE_V[3]
0	1	1	1	0	1	1	N.VCLK
1	0	1	1	1	0	1	N.BUFGLS_H[4]
1	0	1	1	1	1	0	N.BUFGLS_H[5]
1	1	0	1	1	0	1	N.BUFGLS_H[2]
1	1	0	1	1	1	0	N.BUFGLS_H[3]
1	1	1	0	1	0	1	N.BUFGLS_H[6]
1	1	1	0	1	1	0	N.BUFGLS_H[7]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_CLB switchbox LLV muxes GCLK[4]
Bits							Destination
LLV[39][1]	LLV[41][0]	LLV[40][1]	LLV[41][1]	LLV[40][0]	LLV[39][0]	LLV[38][1]	S.GCLK[4]
							Source
0	0	1	1	1	1	1	S.VCLK
0	1	0	1	1	1	1	N.SINGLE_V[4]
0	1	1	0	1	1	1	N.QUAD_V0[1]
0	1	1	1	0	1	1	N.VCLK
1	0	1	1	1	0	1	N.BUFGLS_H[2]
1	0	1	1	1	1	0	N.BUFGLS_H[3]
1	1	0	1	1	0	1	N.BUFGLS_H[6]
1	1	0	1	1	1	0	N.BUFGLS_H[7]
1	1	1	0	1	0	1	N.BUFGLS_H[4]
1	1	1	0	1	1	0	N.BUFGLS_H[5]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_CLB switchbox LLV muxes GCLK[5]
Bits							Destination
LLV[33][1]	LLV[35][1]	LLV[35][0]	LLV[34][1]	LLV[34][0]	LLV[33][0]	LLV[32][1]	S.GCLK[5]
							Source
0	0	1	1	1	1	1	S.QUAD_V3[2]
0	1	0	1	1	1	1	S.VCLK
0	1	1	0	1	1	1	N.SINGLE_V[5]
0	1	1	1	0	1	1	N.VCLK
1	0	1	1	1	0	1	N.BUFGLS_H[4]
1	0	1	1	1	1	0	N.BUFGLS_H[5]
1	1	0	1	1	0	1	N.BUFGLS_H[2]
1	1	0	1	1	1	0	N.BUFGLS_H[3]
1	1	1	0	1	0	1	N.BUFGLS_H[6]
1	1	1	0	1	1	0	N.BUFGLS_H[7]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_CLB switchbox LLV muxes GCLK[6]
Bits							Destination
LLV[22][1]	LLV[24][1]	LLV[24][0]	LLV[23][1]	LLV[23][0]	LLV[21][0]	LLV[21][1]	S.GCLK[6]
							Source
0	0	1	1	1	1	1	S.QUAD_V4[2]
0	1	0	1	1	1	1	S.VCLK
0	1	1	0	1	1	1	N.SINGLE_V[6]
0	1	1	1	0	1	1	N.VCLK
1	0	1	1	1	0	1	N.BUFGLS_H[4]
1	0	1	1	1	1	0	N.BUFGLS_H[5]
1	1	0	1	1	0	1	N.BUFGLS_H[2]
1	1	0	1	1	1	0	N.BUFGLS_H[3]
1	1	1	0	1	0	1	N.BUFGLS_H[6]
1	1	1	0	1	1	0	N.BUFGLS_H[7]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_CLB switchbox LLV muxes GCLK[7]
Bits							Destination
LLV[17][1]	LLV[19][0]	LLV[18][1]	LLV[19][1]	LLV[18][0]	LLV[16][0]	LLV[16][1]	S.GCLK[7]
							Source
0	0	1	1	1	1	1	S.VCLK
0	1	0	1	1	1	1	N.SINGLE_V[7]
0	1	1	0	1	1	1	N.QUAD_V0[2]
0	1	1	1	0	1	1	N.VCLK
1	0	1	1	1	0	1	N.BUFGLS_H[2]
1	0	1	1	1	1	0	N.BUFGLS_H[3]
1	1	0	1	1	0	1	N.BUFGLS_H[6]
1	1	0	1	1	1	0	N.BUFGLS_H[7]
1	1	1	0	1	0	1	N.BUFGLS_H[4]
1	1	1	0	1	1	0	N.BUFGLS_H[5]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_CLB switchbox LLV muxes LONG_V[7]
Bits		Destination
LLV[45][0]	LLV[43][1]	N.LONG_V[7]
		Source
0	0	S.LONG_V[7]
0	1	S.VCLK
1	1	off

Bitstream

xc4000ex LLVQ_CLB rect LLV
Bit	Frame
Bit	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B1	LLV: !buffer S.LONG_V[6] ← N.LONG_V[6]	LLV: !buffer S.LONG_V[7] ← N.LONG_V[7]	LLV: !pass N.QUAD_V0[0] ← N.VCLK	LLV: mux N.LONG_V[7] bit 0	LLV: !buffer S.LONG_V[8] ← N.LONG_V[8]	LLV: mux S.GCLK[4] bit 3	LLV: mux S.GCLK[4] bit 4	LLV: mux S.GCLK[4] bit 6	LLV: mux S.GCLK[4] bit 0	LLV: !buffer N.LONG_V[9] ← S.LONG_V[9]	LLV: mux S.LONG_V[9] bit 0	LLV: mux S.GCLK[5] bit 5	LLV: mux S.GCLK[5] bit 3	LLV: mux S.GCLK[5] bit 6	LLV: mux S.GCLK[5] bit 0	LLV: !buffer S.LONG_V[2] ← N.LONG_V[2]	LLV: mux S.GCLK[0] bit 5	LLV: mux S.GCLK[0] bit 3	LLV: mux S.GCLK[0] bit 6	LLV: mux S.GCLK[0] bit 0	LLV: !pass N.SINGLE_V[1] ← N.VCLK	LLV: !buffer S.LONG_V[4] ← N.LONG_V[4]	LLV: mux S.GCLK[6] bit 5	LLV: mux S.GCLK[6] bit 3	LLV: mux S.GCLK[6] bit 6	LLV: mux S.GCLK[6] bit 0	LLV: !buffer S.LONG_V[1] ← N.LONG_V[1]	LLV: mux S.GCLK[7] bit 3	LLV: mux S.GCLK[7] bit 4	LLV: mux S.GCLK[7] bit 6	LLV: mux S.GCLK[7] bit 0	LLV: !buffer S.LONG_V[5] ← N.LONG_V[5]	-	LLV: mux S.GCLK[2] bit 3	LLV: mux S.GCLK[2] bit 4	LLV: mux S.GCLK[2] bit 6	LLV: mux S.GCLK[2] bit 0	LLV: !buffer S.LONG_V[3] ← N.LONG_V[3]	LLV: mux S.GCLK[3] bit 5	LLV: mux S.GCLK[3] bit 3	LLV: mux S.GCLK[3] bit 6	LLV: mux S.GCLK[3] bit 0	LLV: !buffer S.LONG_V[0] ← N.LONG_V[0]	LLV: mux S.GCLK[1] bit 5	LLV: mux S.GCLK[1] bit 3	LLV: mux S.GCLK[1] bit 6	LLV: mux S.GCLK[1] bit 0
B0	LLV: !buffer N.LONG_V[6] ← S.LONG_V[6]	LLV: mux N.LONG_V[7] bit 1	LLV: !buffer N.LONG_V[8] ← S.LONG_V[8]	LLV: !pass S.QUAD_V4[1] ← S.VCLK	LLV: !pass S.QUAD_V4[2] ← N.VCLK	LLV: mux S.GCLK[4] bit 5	LLV: mux S.GCLK[4] bit 2	LLV: mux S.GCLK[4] bit 1	LLV: !pass N.SINGLE_V[4] ← S.VCLK	LLV: !pass N.SINGLE_V[6] ← S.VCLK	LLV: mux S.LONG_V[9] bit 1	LLV: mux S.GCLK[5] bit 4	LLV: mux S.GCLK[5] bit 2	LLV: mux S.GCLK[5] bit 1	LLV: !pass N.SINGLE_V[7] ← N.VCLK	LLV: !buffer N.LONG_V[2] ← S.LONG_V[2]	LLV: mux S.GCLK[0] bit 4	LLV: mux S.GCLK[0] bit 2	LLV: !pass N.SINGLE_V[5] ← N.VCLK	LLV: !pass N.SINGLE_V[3] ← N.VCLK	LLV: mux S.GCLK[0] bit 1	LLV: !buffer N.LONG_V[4] ← S.LONG_V[4]	LLV: mux S.GCLK[6] bit 4	LLV: mux S.GCLK[6] bit 2	LLV: !pass N.QUAD_V0[2] ← S.VCLK	LLV: mux S.GCLK[6] bit 1	LLV: !buffer N.LONG_V[1] ← S.LONG_V[1]	LLV: mux S.GCLK[7] bit 5	LLV: mux S.GCLK[7] bit 2	LLV: !pass N.SINGLE_V[0] ← S.VCLK	LLV: mux S.GCLK[7] bit 1	LLV: !buffer N.LONG_V[5] ← S.LONG_V[5]	LLV: !pass N.SINGLE_V[2] ← S.VCLK	LLV: mux S.GCLK[2] bit 5	LLV: mux S.GCLK[2] bit 2	-	LLV: mux S.GCLK[2] bit 1	LLV: !buffer N.LONG_V[3] ← S.LONG_V[3]	LLV: mux S.GCLK[3] bit 4	LLV: mux S.GCLK[3] bit 2	-	LLV: mux S.GCLK[3] bit 1	LLV: !buffer N.LONG_V[0] ← S.LONG_V[0]	LLV: mux S.GCLK[1] bit 4	LLV: mux S.GCLK[1] bit 2	-	LLV: mux S.GCLK[1] bit 1

Tile LLVQ_IO_SW

Cells: 2

Switchbox LLV

xc4000ex LLVQ_IO_SW switchbox LLV programmable buffers
Destination	Source	Bit
S.LONG_IO_V[0]	N.LONG_IO_V[0]	!LLV[7][1]
S.LONG_IO_V[1]	N.LONG_IO_V[1]	!LLV[9][1]
S.LONG_IO_V[2]	N.LONG_IO_V[2]	!LLV[5][1]
S.LONG_IO_V[3]	N.LONG_IO_V[3]	!LLV[8][1]
N.LONG_IO_V[0]	S.LONG_IO_V[0]	!LLV[7][0]
N.LONG_IO_V[1]	S.LONG_IO_V[1]	!LLV[9][0]
N.LONG_IO_V[2]	S.LONG_IO_V[2]	!LLV[5][0]
N.LONG_IO_V[3]	S.LONG_IO_V[3]	!LLV[8][0]

xc4000ex LLVQ_IO_SW switchbox LLV pass gates
Destination	Source	Bit
S.DOUBLE_IO_W1[0]	S.ECLK_V	!LLV[15][0]
S.DOUBLE_IO_W1[1]	S.ECLK_V	!LLV[11][0]
S.DOUBLE_IO_W1[2]	S.ECLK_V	!LLV[6][1]
S.DOUBLE_IO_W2[1]	S.ECLK_V	!LLV[19][0]
S.DOUBLE_IO_W2[3]	S.ECLK_V	!LLV[23][0]

xc4000ex LLVQ_IO_SW switchbox LLV muxes GCLK[0]
Bits							Destination
LLV[16][1]	LLV[18][1]	LLV[17][1]	LLV[18][0]	LLV[17][0]	LLV[16][0]	LLV[15][1]	S.GCLK[0]
							Source
0	0	1	1	1	1	1	S.DOUBLE_IO_W1[0]
0	1	0	1	1	1	1	S.DOUBLE_IO_W1[2]
0	1	1	0	1	1	1	S.BUFGE_V[1]
0	1	1	1	0	1	1	N.OUT_BUFF
1	0	1	1	1	0	1	N.BUFGLS_H[4]
1	0	1	1	1	1	0	N.BUFGLS_H[5]
1	1	0	1	1	0	1	N.BUFGLS_H[6]
1	1	0	1	1	1	0	N.BUFGLS_H[7]
1	1	1	0	1	0	1	N.BUFGLS_H[2]
1	1	1	0	1	1	0	N.BUFGLS_H[3]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_SW switchbox LLV muxes GCLK[1]
Bits							Destination
LLV[24][1]	LLV[26][1]	LLV[25][1]	LLV[26][0]	LLV[25][0]	LLV[24][0]	LLV[23][1]	S.GCLK[1]
							Source
0	0	1	1	1	1	1	S.DOUBLE_IO_W2[0]
0	1	0	1	1	1	1	S.DOUBLE_IO_W2[2]
0	1	1	0	1	1	1	S.ECLK_V
0	1	1	1	0	1	1	S.BUFGE_V[0]
1	0	1	1	1	0	1	N.BUFGLS_H[4]
1	0	1	1	1	1	0	N.BUFGLS_H[5]
1	1	0	1	1	0	1	N.BUFGLS_H[6]
1	1	0	1	1	1	0	N.BUFGLS_H[7]
1	1	1	0	1	0	1	N.BUFGLS_H[2]
1	1	1	0	1	1	0	N.BUFGLS_H[3]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_SW switchbox LLV muxes GCLK[2]
Bits							Destination
LLV[12][1]	LLV[13][1]	LLV[14][1]	LLV[14][0]	LLV[13][0]	LLV[12][0]	LLV[11][1]	S.GCLK[2]
							Source
0	0	1	1	1	1	1	S.DOUBLE_IO_W1[1]
0	1	0	1	1	1	1	S.DOUBLE_IO_W1[3]
0	1	1	0	1	1	1	S.ECLK_V
0	1	1	1	0	1	1	N.OUT_BUFF
1	0	1	1	1	0	1	N.BUFGLS_H[6]
1	0	1	1	1	1	0	N.BUFGLS_H[7]
1	1	0	1	1	0	1	N.BUFGLS_H[4]
1	1	0	1	1	1	0	N.BUFGLS_H[5]
1	1	1	0	1	0	1	N.BUFGLS_H[2]
1	1	1	0	1	1	0	N.BUFGLS_H[3]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_SW switchbox LLV muxes GCLK[3]
Bits							Destination
LLV[20][1]	LLV[21][1]	LLV[22][1]	LLV[21][0]	LLV[22][0]	LLV[20][0]	LLV[19][1]	S.GCLK[3]
							Source
0	0	1	1	1	1	1	S.DOUBLE_IO_W2[1]
0	1	0	1	1	1	1	S.DOUBLE_IO_W2[3]
0	1	1	0	1	1	1	S.BUFGE_V[0]
0	1	1	1	0	1	1	S.BUFGE_V[1]
1	0	1	1	1	0	1	N.BUFGLS_H[6]
1	0	1	1	1	1	0	N.BUFGLS_H[7]
1	1	0	1	1	0	1	N.BUFGLS_H[4]
1	1	0	1	1	1	0	N.BUFGLS_H[5]
1	1	1	0	1	0	1	N.BUFGLS_H[0]
1	1	1	0	1	1	0	N.BUFGLS_H[1]
1	1	1	1	0	0	1	N.BUFGLS_H[2]
1	1	1	1	0	1	0	N.BUFGLS_H[3]
1	1	1	1	1	1	1	off

Bels BUFF

xc4000ex LLVQ_IO_SW bel BUFF pins
Pin	Direction	BUFF
O	out	N.OUT_BUFF

Bel wires

xc4000ex LLVQ_IO_SW bel wires
Wire	Pins
N.OUT_BUFF	BUFF.O

Bitstream

xc4000ex LLVQ_IO_SW rect LLV
Bit	Frame
Bit	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B1	LLV: mux S.GCLK[1] bit 5	LLV: mux S.GCLK[1] bit 4	LLV: mux S.GCLK[1] bit 6	LLV: mux S.GCLK[1] bit 0	LLV: mux S.GCLK[3] bit 4	LLV: mux S.GCLK[3] bit 5	LLV: mux S.GCLK[3] bit 6	LLV: mux S.GCLK[3] bit 0	LLV: mux S.GCLK[0] bit 5	LLV: mux S.GCLK[0] bit 4	LLV: mux S.GCLK[0] bit 6	LLV: mux S.GCLK[0] bit 0	LLV: mux S.GCLK[2] bit 4	LLV: mux S.GCLK[2] bit 5	LLV: mux S.GCLK[2] bit 6	LLV: mux S.GCLK[2] bit 0	-	LLV: !buffer S.LONG_IO_V[1] ← N.LONG_IO_V[1]	LLV: !buffer S.LONG_IO_V[3] ← N.LONG_IO_V[3]	LLV: !buffer S.LONG_IO_V[0] ← N.LONG_IO_V[0]	LLV: !pass S.DOUBLE_IO_W1[2] ← S.ECLK_V	LLV: !buffer S.LONG_IO_V[2] ← N.LONG_IO_V[2]	-	-	-	-	-
B0	LLV: mux S.GCLK[1] bit 3	LLV: mux S.GCLK[1] bit 2	LLV: mux S.GCLK[1] bit 1	LLV: !pass S.DOUBLE_IO_W2[3] ← S.ECLK_V	LLV: mux S.GCLK[3] bit 2	LLV: mux S.GCLK[3] bit 3	LLV: mux S.GCLK[3] bit 1	LLV: !pass S.DOUBLE_IO_W2[1] ← S.ECLK_V	LLV: mux S.GCLK[0] bit 3	LLV: mux S.GCLK[0] bit 2	LLV: mux S.GCLK[0] bit 1	LLV: !pass S.DOUBLE_IO_W1[0] ← S.ECLK_V	LLV: mux S.GCLK[2] bit 3	LLV: mux S.GCLK[2] bit 2	LLV: mux S.GCLK[2] bit 1	LLV: !pass S.DOUBLE_IO_W1[1] ← S.ECLK_V	-	LLV: !buffer N.LONG_IO_V[1] ← S.LONG_IO_V[1]	LLV: !buffer N.LONG_IO_V[3] ← S.LONG_IO_V[3]	LLV: !buffer N.LONG_IO_V[0] ← S.LONG_IO_V[0]	-	LLV: !buffer N.LONG_IO_V[2] ← S.LONG_IO_V[2]	-	-	-	-	-

xc4000ex LLVQ_IO_SW rect LLV_E
Bit	Frame
Bit	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile LLVQ_IO_NW

Cells: 2

Switchbox LLV

xc4000ex LLVQ_IO_NW switchbox LLV programmable buffers
Destination	Source	Bit
S.LONG_IO_V[0]	N.LONG_IO_V[0]	!LLV[7][1]
S.LONG_IO_V[1]	N.LONG_IO_V[1]	!LLV[9][1]
S.LONG_IO_V[2]	N.LONG_IO_V[2]	!LLV[5][1]
S.LONG_IO_V[3]	N.LONG_IO_V[3]	!LLV[8][1]
N.LONG_IO_V[0]	S.LONG_IO_V[0]	!LLV[7][0]
N.LONG_IO_V[1]	S.LONG_IO_V[1]	!LLV[9][0]
N.LONG_IO_V[2]	S.LONG_IO_V[2]	!LLV[5][0]
N.LONG_IO_V[3]	S.LONG_IO_V[3]	!LLV[8][0]

xc4000ex LLVQ_IO_NW switchbox LLV pass gates
Destination	Source	Bit
S.DOUBLE_IO_W1[0]	N.ECLK_V	!LLV[15][0]
S.DOUBLE_IO_W1[1]	N.ECLK_V	!LLV[11][0]
S.DOUBLE_IO_W1[2]	N.ECLK_V	!LLV[6][1]
S.DOUBLE_IO_W2[1]	N.ECLK_V	!LLV[19][0]
S.DOUBLE_IO_W2[3]	N.ECLK_V	!LLV[23][0]

xc4000ex LLVQ_IO_NW switchbox LLV muxes GCLK[0]
Bits							Destination
LLV[16][1]	LLV[18][1]	LLV[17][1]	LLV[18][0]	LLV[17][0]	LLV[16][0]	LLV[15][1]	S.GCLK[0]
							Source
0	0	1	1	1	1	1	S.DOUBLE_IO_W1[0]
0	1	0	1	1	1	1	S.DOUBLE_IO_W1[2]
0	1	1	0	1	1	1	S.BUFGE_V[0]
0	1	1	1	0	1	1	N.OUT_BUFF
1	0	1	1	1	0	1	N.BUFGLS_H[4]
1	0	1	1	1	1	0	N.BUFGLS_H[5]
1	1	0	1	1	0	1	N.BUFGLS_H[6]
1	1	0	1	1	1	0	N.BUFGLS_H[7]
1	1	1	0	1	0	1	N.BUFGLS_H[2]
1	1	1	0	1	1	0	N.BUFGLS_H[3]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_NW switchbox LLV muxes GCLK[1]
Bits							Destination
LLV[24][1]	LLV[26][1]	LLV[25][1]	LLV[25][0]	LLV[26][0]	LLV[24][0]	LLV[23][1]	S.GCLK[1]
							Source
0	0	1	1	1	1	1	S.DOUBLE_IO_W2[0]
0	1	0	1	1	1	1	S.DOUBLE_IO_W2[2]
0	1	1	0	1	1	1	S.BUFGE_V[1]
0	1	1	1	0	1	1	N.ECLK_V
1	0	1	1	1	0	1	N.BUFGLS_H[4]
1	0	1	1	1	1	0	N.BUFGLS_H[5]
1	1	0	1	1	0	1	N.BUFGLS_H[6]
1	1	0	1	1	1	0	N.BUFGLS_H[7]
1	1	1	0	1	0	1	N.BUFGLS_H[0]
1	1	1	0	1	1	0	N.BUFGLS_H[1]
1	1	1	1	0	0	1	N.BUFGLS_H[2]
1	1	1	1	0	1	0	N.BUFGLS_H[3]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_NW switchbox LLV muxes GCLK[2]
Bits							Destination
LLV[12][1]	LLV[13][1]	LLV[14][1]	LLV[14][0]	LLV[13][0]	LLV[12][0]	LLV[11][1]	S.GCLK[2]
							Source
0	0	1	1	1	1	1	S.DOUBLE_IO_W1[1]
0	1	0	1	1	1	1	S.DOUBLE_IO_W1[3]
0	1	1	0	1	1	1	N.ECLK_V
0	1	1	1	0	1	1	N.OUT_BUFF
1	0	1	1	1	0	1	N.BUFGLS_H[6]
1	0	1	1	1	1	0	N.BUFGLS_H[7]
1	1	0	1	1	0	1	N.BUFGLS_H[4]
1	1	0	1	1	1	0	N.BUFGLS_H[5]
1	1	1	0	1	0	1	N.BUFGLS_H[2]
1	1	1	0	1	1	0	N.BUFGLS_H[3]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_NW switchbox LLV muxes GCLK[3]
Bits							Destination
LLV[20][1]	LLV[21][1]	LLV[22][1]	LLV[22][0]	LLV[21][0]	LLV[20][0]	LLV[19][1]	S.GCLK[3]
							Source
0	0	1	1	1	1	1	S.DOUBLE_IO_W2[1]
0	1	0	1	1	1	1	S.DOUBLE_IO_W2[3]
0	1	1	0	1	1	1	S.BUFGE_V[0]
0	1	1	1	0	1	1	S.BUFGE_V[1]
1	0	1	1	1	0	1	N.BUFGLS_H[6]
1	0	1	1	1	1	0	N.BUFGLS_H[7]
1	1	0	1	1	0	1	N.BUFGLS_H[4]
1	1	0	1	1	1	0	N.BUFGLS_H[5]
1	1	1	0	1	0	1	N.BUFGLS_H[2]
1	1	1	0	1	1	0	N.BUFGLS_H[3]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

Bels BUFF

xc4000ex LLVQ_IO_NW bel BUFF pins
Pin	Direction	BUFF
O	out	N.OUT_BUFF

Bel wires

xc4000ex LLVQ_IO_NW bel wires
Wire	Pins
N.OUT_BUFF	BUFF.O

Bitstream

xc4000ex LLVQ_IO_NW rect LLV
Bit	Frame
Bit	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B1	LLV: mux S.GCLK[1] bit 5	LLV: mux S.GCLK[1] bit 4	LLV: mux S.GCLK[1] bit 6	LLV: mux S.GCLK[1] bit 0	LLV: mux S.GCLK[3] bit 4	LLV: mux S.GCLK[3] bit 5	LLV: mux S.GCLK[3] bit 6	LLV: mux S.GCLK[3] bit 0	LLV: mux S.GCLK[0] bit 5	LLV: mux S.GCLK[0] bit 4	LLV: mux S.GCLK[0] bit 6	LLV: mux S.GCLK[0] bit 0	LLV: mux S.GCLK[2] bit 4	LLV: mux S.GCLK[2] bit 5	LLV: mux S.GCLK[2] bit 6	LLV: mux S.GCLK[2] bit 0	-	LLV: !buffer S.LONG_IO_V[1] ← N.LONG_IO_V[1]	LLV: !buffer S.LONG_IO_V[3] ← N.LONG_IO_V[3]	LLV: !buffer S.LONG_IO_V[0] ← N.LONG_IO_V[0]	LLV: !pass S.DOUBLE_IO_W1[2] ← N.ECLK_V	LLV: !buffer S.LONG_IO_V[2] ← N.LONG_IO_V[2]	-	-	-	-	-
B0	LLV: mux S.GCLK[1] bit 2	LLV: mux S.GCLK[1] bit 3	LLV: mux S.GCLK[1] bit 1	LLV: !pass S.DOUBLE_IO_W2[3] ← N.ECLK_V	LLV: mux S.GCLK[3] bit 3	LLV: mux S.GCLK[3] bit 2	LLV: mux S.GCLK[3] bit 1	LLV: !pass S.DOUBLE_IO_W2[1] ← N.ECLK_V	LLV: mux S.GCLK[0] bit 3	LLV: mux S.GCLK[0] bit 2	LLV: mux S.GCLK[0] bit 1	LLV: !pass S.DOUBLE_IO_W1[0] ← N.ECLK_V	LLV: mux S.GCLK[2] bit 3	LLV: mux S.GCLK[2] bit 2	LLV: mux S.GCLK[2] bit 1	LLV: !pass S.DOUBLE_IO_W1[1] ← N.ECLK_V	-	LLV: !buffer N.LONG_IO_V[1] ← S.LONG_IO_V[1]	LLV: !buffer N.LONG_IO_V[3] ← S.LONG_IO_V[3]	LLV: !buffer N.LONG_IO_V[0] ← S.LONG_IO_V[0]	-	LLV: !buffer N.LONG_IO_V[2] ← S.LONG_IO_V[2]	-	-	-	-	-

xc4000ex LLVQ_IO_NW rect LLV_E
Bit	Frame
Bit	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile LLVQ_IO_SE

Cells: 2

Switchbox LLV

xc4000ex LLVQ_IO_SE switchbox LLV programmable buffers
Destination	Source	Bit
S.LONG_V[0]	N.LONG_V[0]	!LLV[31][1]
S.LONG_V[1]	N.LONG_V[1]	!LLV[27][1]
S.LONG_V[2]	N.LONG_V[2]	!LLV[33][1]
S.LONG_V[3]	N.LONG_V[3]	!LLV[34][1]
S.LONG_V[4]	N.LONG_V[4]	!LLV[29][1]
S.LONG_V[5]	N.LONG_V[5]	!LLV[35][1]
S.LONG_V[6]	N.LONG_V[6]	!LLV[26][1]
S.LONG_V[7]	N.LONG_V[7]	!LLV[25][1]
S.LONG_V[8]	N.LONG_V[8]	!LLV[23][1]
S.LONG_IO_V[0]	N.LONG_IO_V[0]	!LLV[20][1]
S.LONG_IO_V[1]	N.LONG_IO_V[1]	!LLV[16][1]
S.LONG_IO_V[2]	N.LONG_IO_V[2]	!LLV[18][1]
S.LONG_IO_V[3]	N.LONG_IO_V[3]	!LLV[17][1]
N.LONG_V[0]	S.LONG_V[0]	!LLV[31][0]
N.LONG_V[1]	S.LONG_V[1]	!LLV[27][0]
N.LONG_V[2]	S.LONG_V[2]	!LLV[33][0]
N.LONG_V[3]	S.LONG_V[3]	!LLV[34][0]
N.LONG_V[4]	S.LONG_V[4]	!LLV[29][0]
N.LONG_V[5]	S.LONG_V[5]	!LLV[35][0]
N.LONG_V[6]	S.LONG_V[6]	!LLV[26][0]
N.LONG_V[8]	S.LONG_V[8]	!LLV[23][0]
N.LONG_V[9]	S.LONG_V[9]	!LLV[22][1]
N.LONG_IO_V[0]	S.LONG_IO_V[0]	!LLV[20][0]
N.LONG_IO_V[1]	S.LONG_IO_V[1]	!LLV[16][0]
N.LONG_IO_V[2]	S.LONG_IO_V[2]	!LLV[18][0]
N.LONG_IO_V[3]	S.LONG_IO_V[3]	!LLV[17][0]

xc4000ex LLVQ_IO_SE switchbox LLV pass gates
Destination	Source	Bit
S.DOUBLE_IO_E0[1]	S.ECLK_V	!LLV[9][0]
S.DOUBLE_IO_E0[3]	S.ECLK_V	!LLV[19][1]
S.DOUBLE_IO_E1[0]	S.ECLK_V	!LLV[19][0]
S.DOUBLE_IO_E1[1]	S.ECLK_V	!LLV[5][0]
S.DOUBLE_IO_E1[2]	S.ECLK_V	!LLV[1][0]
S.QUAD_V4[1]	S.VCLK	!LLV[30][1]
S.QUAD_V4[2]	N.VCLK	!LLV[32][0]
N.SINGLE_V[0]	S.VCLK	!LLV[24][0]
N.SINGLE_V[1]	N.VCLK	!LLV[21][0]
N.SINGLE_V[2]	S.VCLK	!LLV[28][0]
N.SINGLE_V[3]	N.VCLK	!LLV[28][1]
N.SINGLE_V[4]	S.VCLK	!LLV[48][0]
N.SINGLE_V[5]	N.VCLK	!LLV[45][0]
N.SINGLE_V[6]	S.VCLK	!LLV[41][0]
N.SINGLE_V[7]	N.VCLK	!LLV[36][0]
N.QUAD_V0[0]	N.VCLK	!LLV[30][0]
N.QUAD_V0[2]	S.VCLK	!LLV[32][1]

xc4000ex LLVQ_IO_SE switchbox LLV muxes LONG_V[9]
Bits		Destination
LLV[22][0]	LLV[21][1]	S.LONG_V[9]
		Source
0	0	N.LONG_V[9]
0	1	N.VCLK
1	1	off

xc4000ex LLVQ_IO_SE switchbox LLV muxes GCLK[0]
Bits							Destination
LLV[9][1]	LLV[11][1]	LLV[10][1]	LLV[11][0]	LLV[10][0]	LLV[8][0]	LLV[8][1]	S.GCLK[0]
							Source
0	0	1	1	1	1	1	S.DOUBLE_IO_E1[0]
0	1	0	1	1	1	1	S.DOUBLE_IO_E1[2]
0	1	1	0	1	1	1	S.BUFGE_V[1]
0	1	1	1	0	1	1	N.OUT_BUFF
1	0	1	1	1	0	1	N.BUFGLS_H[4]
1	0	1	1	1	1	0	N.BUFGLS_H[5]
1	1	0	1	1	0	1	N.BUFGLS_H[6]
1	1	0	1	1	1	0	N.BUFGLS_H[7]
1	1	1	0	1	0	1	N.BUFGLS_H[2]
1	1	1	0	1	1	0	N.BUFGLS_H[3]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_SE switchbox LLV muxes GCLK[1]
Bits							Destination
LLV[5][1]	LLV[7][1]	LLV[6][1]	LLV[7][0]	LLV[6][0]	LLV[4][0]	LLV[4][1]	S.GCLK[1]
							Source
0	0	1	1	1	1	1	S.DOUBLE_IO_E0[0]
0	1	0	1	1	1	1	S.DOUBLE_IO_E0[2]
0	1	1	0	1	1	1	S.ECLK_V
0	1	1	1	0	1	1	S.BUFGE_V[0]
1	0	1	1	1	0	1	N.BUFGLS_H[4]
1	0	1	1	1	1	0	N.BUFGLS_H[5]
1	1	0	1	1	0	1	N.BUFGLS_H[6]
1	1	0	1	1	1	0	N.BUFGLS_H[7]
1	1	1	0	1	0	1	N.BUFGLS_H[2]
1	1	1	0	1	1	0	N.BUFGLS_H[3]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_SE switchbox LLV muxes GCLK[2]
Bits							Destination
LLV[13][1]	LLV[14][1]	LLV[15][1]	LLV[15][0]	LLV[14][0]	LLV[12][0]	LLV[12][1]	S.GCLK[2]
							Source
0	0	1	1	1	1	1	S.DOUBLE_IO_E1[1]
0	1	0	1	1	1	1	S.DOUBLE_IO_E1[3]
0	1	1	0	1	1	1	S.ECLK_V
0	1	1	1	0	1	1	N.OUT_BUFF
1	0	1	1	1	0	1	N.BUFGLS_H[6]
1	0	1	1	1	1	0	N.BUFGLS_H[7]
1	1	0	1	1	0	1	N.BUFGLS_H[4]
1	1	0	1	1	1	0	N.BUFGLS_H[5]
1	1	1	0	1	0	1	N.BUFGLS_H[2]
1	1	1	0	1	1	0	N.BUFGLS_H[3]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_SE switchbox LLV muxes GCLK[3]
Bits							Destination
LLV[1][1]	LLV[2][1]	LLV[3][1]	LLV[2][0]	LLV[3][0]	LLV[0][0]	LLV[0][1]	S.GCLK[3]
							Source
0	0	1	1	1	1	1	S.DOUBLE_IO_E0[1]
0	1	0	1	1	1	1	S.DOUBLE_IO_E0[3]
0	1	1	0	1	1	1	S.BUFGE_V[0]
0	1	1	1	0	1	1	S.BUFGE_V[1]
1	0	1	1	1	0	1	N.BUFGLS_H[6]
1	0	1	1	1	1	0	N.BUFGLS_H[7]
1	1	0	1	1	0	1	N.BUFGLS_H[4]
1	1	0	1	1	1	0	N.BUFGLS_H[5]
1	1	1	0	1	0	1	N.BUFGLS_H[0]
1	1	1	0	1	1	0	N.BUFGLS_H[1]
1	1	1	1	0	0	1	N.BUFGLS_H[2]
1	1	1	1	0	1	0	N.BUFGLS_H[3]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_SE switchbox LLV muxes GCLK[4]
Bits							Destination
LLV[49][1]	LLV[51][0]	LLV[50][1]	LLV[51][1]	LLV[50][0]	LLV[49][0]	LLV[48][1]	S.GCLK[4]
							Source
0	0	1	1	1	1	1	S.VCLK
0	1	0	1	1	1	1	N.SINGLE_V[4]
0	1	1	0	1	1	1	N.QUAD_V0[1]
0	1	1	1	0	1	1	N.VCLK
1	0	1	1	1	0	1	N.BUFGLS_H[2]
1	0	1	1	1	1	0	N.BUFGLS_H[3]
1	1	0	1	1	0	1	N.BUFGLS_H[6]
1	1	0	1	1	1	0	N.BUFGLS_H[7]
1	1	1	0	1	0	1	N.BUFGLS_H[4]
1	1	1	0	1	1	0	N.BUFGLS_H[5]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_SE switchbox LLV muxes GCLK[5]
Bits							Destination
LLV[45][1]	LLV[47][1]	LLV[47][0]	LLV[46][1]	LLV[46][0]	LLV[44][0]	LLV[44][1]	S.GCLK[5]
							Source
0	0	1	1	1	1	1	S.QUAD_V3[2]
0	1	0	1	1	1	1	S.VCLK
0	1	1	0	1	1	1	N.SINGLE_V[5]
0	1	1	1	0	1	1	N.VCLK
1	0	1	1	1	0	1	N.BUFGLS_H[4]
1	0	1	1	1	1	0	N.BUFGLS_H[5]
1	1	0	1	1	0	1	N.BUFGLS_H[2]
1	1	0	1	1	1	0	N.BUFGLS_H[3]
1	1	1	0	1	0	1	N.BUFGLS_H[6]
1	1	1	0	1	1	0	N.BUFGLS_H[7]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_SE switchbox LLV muxes GCLK[6]
Bits							Destination
LLV[41][1]	LLV[43][1]	LLV[43][0]	LLV[42][1]	LLV[42][0]	LLV[40][0]	LLV[40][1]	S.GCLK[6]
							Source
0	0	1	1	1	1	1	S.QUAD_V4[2]
0	1	0	1	1	1	1	S.VCLK
0	1	1	0	1	1	1	N.SINGLE_V[6]
0	1	1	1	0	1	1	N.VCLK
1	0	1	1	1	0	1	N.BUFGLS_H[4]
1	0	1	1	1	1	0	N.BUFGLS_H[5]
1	1	0	1	1	0	1	N.BUFGLS_H[2]
1	1	0	1	1	1	0	N.BUFGLS_H[3]
1	1	1	0	1	0	1	N.BUFGLS_H[6]
1	1	1	0	1	1	0	N.BUFGLS_H[7]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_SE switchbox LLV muxes GCLK[7]
Bits							Destination
LLV[37][1]	LLV[39][0]	LLV[38][1]	LLV[39][1]	LLV[38][0]	LLV[37][0]	LLV[36][1]	S.GCLK[7]
							Source
0	0	1	1	1	1	1	S.VCLK
0	1	0	1	1	1	1	N.SINGLE_V[7]
0	1	1	0	1	1	1	N.QUAD_V0[2]
0	1	1	1	0	1	1	N.VCLK
1	0	1	1	1	0	1	N.BUFGLS_H[2]
1	0	1	1	1	1	0	N.BUFGLS_H[3]
1	1	0	1	1	0	1	N.BUFGLS_H[6]
1	1	0	1	1	1	0	N.BUFGLS_H[7]
1	1	1	0	1	0	1	N.BUFGLS_H[4]
1	1	1	0	1	1	0	N.BUFGLS_H[5]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_SE switchbox LLV muxes LONG_V[7]
Bits		Destination
LLV[25][0]	LLV[24][1]	N.LONG_V[7]
		Source
0	0	S.LONG_V[7]
0	1	S.VCLK
1	1	off

Bels BUFF

xc4000ex LLVQ_IO_SE bel BUFF pins
Pin	Direction	BUFF
O	out	N.OUT_BUFF

Bel wires

xc4000ex LLVQ_IO_SE bel wires
Wire	Pins
N.OUT_BUFF	BUFF.O

Bitstream

xc4000ex LLVQ_IO_SE rect LLV
Bit	Frame
Bit	F51	F50	F49	F48	F47	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B1	LLV: mux S.GCLK[4] bit 3	LLV: mux S.GCLK[4] bit 4	LLV: mux S.GCLK[4] bit 6	LLV: mux S.GCLK[4] bit 0	LLV: mux S.GCLK[5] bit 5	LLV: mux S.GCLK[5] bit 3	LLV: mux S.GCLK[5] bit 6	LLV: mux S.GCLK[5] bit 0	LLV: mux S.GCLK[6] bit 5	LLV: mux S.GCLK[6] bit 3	LLV: mux S.GCLK[6] bit 6	LLV: mux S.GCLK[6] bit 0	LLV: mux S.GCLK[7] bit 3	LLV: mux S.GCLK[7] bit 4	LLV: mux S.GCLK[7] bit 6	LLV: mux S.GCLK[7] bit 0	LLV: !buffer S.LONG_V[5] ← N.LONG_V[5]	LLV: !buffer S.LONG_V[3] ← N.LONG_V[3]	LLV: !buffer S.LONG_V[2] ← N.LONG_V[2]	LLV: !pass N.QUAD_V0[2] ← S.VCLK	LLV: !buffer S.LONG_V[0] ← N.LONG_V[0]	LLV: !pass S.QUAD_V4[1] ← S.VCLK	LLV: !buffer S.LONG_V[4] ← N.LONG_V[4]	LLV: !pass N.SINGLE_V[3] ← N.VCLK	LLV: !buffer S.LONG_V[1] ← N.LONG_V[1]	LLV: !buffer S.LONG_V[6] ← N.LONG_V[6]	LLV: !buffer S.LONG_V[7] ← N.LONG_V[7]	LLV: mux N.LONG_V[7] bit 0	LLV: !buffer S.LONG_V[8] ← N.LONG_V[8]	LLV: !buffer N.LONG_V[9] ← S.LONG_V[9]	LLV: mux S.LONG_V[9] bit 0	LLV: !buffer S.LONG_IO_V[0] ← N.LONG_IO_V[0]	LLV: !pass S.DOUBLE_IO_E0[3] ← S.ECLK_V	LLV: !buffer S.LONG_IO_V[2] ← N.LONG_IO_V[2]	LLV: !buffer S.LONG_IO_V[3] ← N.LONG_IO_V[3]	LLV: !buffer S.LONG_IO_V[1] ← N.LONG_IO_V[1]	LLV: mux S.GCLK[2] bit 4	LLV: mux S.GCLK[2] bit 5	LLV: mux S.GCLK[2] bit 6	LLV: mux S.GCLK[2] bit 0	LLV: mux S.GCLK[0] bit 5	LLV: mux S.GCLK[0] bit 4	LLV: mux S.GCLK[0] bit 6	LLV: mux S.GCLK[0] bit 0	LLV: mux S.GCLK[1] bit 5	LLV: mux S.GCLK[1] bit 4	LLV: mux S.GCLK[1] bit 6	LLV: mux S.GCLK[1] bit 0	LLV: mux S.GCLK[3] bit 4	LLV: mux S.GCLK[3] bit 5	LLV: mux S.GCLK[3] bit 6	LLV: mux S.GCLK[3] bit 0
B0	LLV: mux S.GCLK[4] bit 5	LLV: mux S.GCLK[4] bit 2	LLV: mux S.GCLK[4] bit 1	LLV: !pass N.SINGLE_V[4] ← S.VCLK	LLV: mux S.GCLK[5] bit 4	LLV: mux S.GCLK[5] bit 2	LLV: !pass N.SINGLE_V[5] ← N.VCLK	LLV: mux S.GCLK[5] bit 1	LLV: mux S.GCLK[6] bit 4	LLV: mux S.GCLK[6] bit 2	LLV: !pass N.SINGLE_V[6] ← S.VCLK	LLV: mux S.GCLK[6] bit 1	LLV: mux S.GCLK[7] bit 5	LLV: mux S.GCLK[7] bit 2	LLV: mux S.GCLK[7] bit 1	LLV: !pass N.SINGLE_V[7] ← N.VCLK	LLV: !buffer N.LONG_V[5] ← S.LONG_V[5]	LLV: !buffer N.LONG_V[3] ← S.LONG_V[3]	LLV: !buffer N.LONG_V[2] ← S.LONG_V[2]	LLV: !pass S.QUAD_V4[2] ← N.VCLK	LLV: !buffer N.LONG_V[0] ← S.LONG_V[0]	LLV: !pass N.QUAD_V0[0] ← N.VCLK	LLV: !buffer N.LONG_V[4] ← S.LONG_V[4]	LLV: !pass N.SINGLE_V[2] ← S.VCLK	LLV: !buffer N.LONG_V[1] ← S.LONG_V[1]	LLV: !buffer N.LONG_V[6] ← S.LONG_V[6]	LLV: mux N.LONG_V[7] bit 1	LLV: !pass N.SINGLE_V[0] ← S.VCLK	LLV: !buffer N.LONG_V[8] ← S.LONG_V[8]	LLV: mux S.LONG_V[9] bit 1	LLV: !pass N.SINGLE_V[1] ← N.VCLK	LLV: !buffer N.LONG_IO_V[0] ← S.LONG_IO_V[0]	LLV: !pass S.DOUBLE_IO_E1[0] ← S.ECLK_V	LLV: !buffer N.LONG_IO_V[2] ← S.LONG_IO_V[2]	LLV: !buffer N.LONG_IO_V[3] ← S.LONG_IO_V[3]	LLV: !buffer N.LONG_IO_V[1] ← S.LONG_IO_V[1]	LLV: mux S.GCLK[2] bit 3	LLV: mux S.GCLK[2] bit 2	-	LLV: mux S.GCLK[2] bit 1	LLV: mux S.GCLK[0] bit 3	LLV: mux S.GCLK[0] bit 2	LLV: !pass S.DOUBLE_IO_E0[1] ← S.ECLK_V	LLV: mux S.GCLK[0] bit 1	LLV: mux S.GCLK[1] bit 3	LLV: mux S.GCLK[1] bit 2	LLV: !pass S.DOUBLE_IO_E1[1] ← S.ECLK_V	LLV: mux S.GCLK[1] bit 1	LLV: mux S.GCLK[3] bit 2	LLV: mux S.GCLK[3] bit 3	LLV: !pass S.DOUBLE_IO_E1[2] ← S.ECLK_V	LLV: mux S.GCLK[3] bit 1

Tile LLVQ_IO_NE

Cells: 2

Switchbox LLV

xc4000ex LLVQ_IO_NE switchbox LLV programmable buffers
Destination	Source	Bit
S.LONG_V[0]	N.LONG_V[0]	!LLV[31][1]
S.LONG_V[1]	N.LONG_V[1]	!LLV[27][1]
S.LONG_V[2]	N.LONG_V[2]	!LLV[33][1]
S.LONG_V[3]	N.LONG_V[3]	!LLV[34][1]
S.LONG_V[4]	N.LONG_V[4]	!LLV[29][1]
S.LONG_V[5]	N.LONG_V[5]	!LLV[35][1]
S.LONG_V[6]	N.LONG_V[6]	!LLV[26][1]
S.LONG_V[7]	N.LONG_V[7]	!LLV[25][1]
S.LONG_V[8]	N.LONG_V[8]	!LLV[23][1]
S.LONG_IO_V[0]	N.LONG_IO_V[0]	!LLV[20][1]
S.LONG_IO_V[1]	N.LONG_IO_V[1]	!LLV[16][1]
S.LONG_IO_V[2]	N.LONG_IO_V[2]	!LLV[18][1]
S.LONG_IO_V[3]	N.LONG_IO_V[3]	!LLV[17][1]
N.LONG_V[0]	S.LONG_V[0]	!LLV[31][0]
N.LONG_V[1]	S.LONG_V[1]	!LLV[27][0]
N.LONG_V[2]	S.LONG_V[2]	!LLV[33][0]
N.LONG_V[3]	S.LONG_V[3]	!LLV[34][0]
N.LONG_V[4]	S.LONG_V[4]	!LLV[29][0]
N.LONG_V[5]	S.LONG_V[5]	!LLV[35][0]
N.LONG_V[6]	S.LONG_V[6]	!LLV[26][0]
N.LONG_V[8]	S.LONG_V[8]	!LLV[23][0]
N.LONG_V[9]	S.LONG_V[9]	!LLV[22][1]
N.LONG_IO_V[0]	S.LONG_IO_V[0]	!LLV[20][0]
N.LONG_IO_V[1]	S.LONG_IO_V[1]	!LLV[16][0]
N.LONG_IO_V[2]	S.LONG_IO_V[2]	!LLV[18][0]
N.LONG_IO_V[3]	S.LONG_IO_V[3]	!LLV[17][0]

xc4000ex LLVQ_IO_NE switchbox LLV pass gates
Destination	Source	Bit
S.DOUBLE_IO_E0[1]	N.ECLK_V	!LLV[9][0]
S.DOUBLE_IO_E0[3]	N.ECLK_V	!LLV[19][1]
S.DOUBLE_IO_E1[0]	N.ECLK_V	!LLV[19][0]
S.DOUBLE_IO_E1[1]	N.ECLK_V	!LLV[5][0]
S.DOUBLE_IO_E1[2]	N.ECLK_V	!LLV[1][0]
S.QUAD_V4[1]	S.VCLK	!LLV[30][1]
S.QUAD_V4[2]	N.VCLK	!LLV[32][0]
N.SINGLE_V[0]	S.VCLK	!LLV[24][0]
N.SINGLE_V[1]	N.VCLK	!LLV[21][0]
N.SINGLE_V[2]	S.VCLK	!LLV[28][0]
N.SINGLE_V[3]	N.VCLK	!LLV[28][1]
N.SINGLE_V[4]	S.VCLK	!LLV[48][0]
N.SINGLE_V[5]	N.VCLK	!LLV[45][0]
N.SINGLE_V[6]	S.VCLK	!LLV[41][0]
N.SINGLE_V[7]	N.VCLK	!LLV[36][0]
N.QUAD_V0[0]	N.VCLK	!LLV[30][0]
N.QUAD_V0[2]	S.VCLK	!LLV[32][1]

xc4000ex LLVQ_IO_NE switchbox LLV muxes LONG_V[9]
Bits		Destination
LLV[22][0]	LLV[21][1]	S.LONG_V[9]
		Source
0	0	N.LONG_V[9]
0	1	N.VCLK
1	1	off

xc4000ex LLVQ_IO_NE switchbox LLV muxes GCLK[0]
Bits							Destination
LLV[9][1]	LLV[11][1]	LLV[10][1]	LLV[11][0]	LLV[10][0]	LLV[8][0]	LLV[8][1]	S.GCLK[0]
							Source
0	0	1	1	1	1	1	S.DOUBLE_IO_E1[0]
0	1	0	1	1	1	1	S.DOUBLE_IO_E1[2]
0	1	1	0	1	1	1	S.BUFGE_V[0]
0	1	1	1	0	1	1	N.OUT_BUFF
1	0	1	1	1	0	1	N.BUFGLS_H[4]
1	0	1	1	1	1	0	N.BUFGLS_H[5]
1	1	0	1	1	0	1	N.BUFGLS_H[6]
1	1	0	1	1	1	0	N.BUFGLS_H[7]
1	1	1	0	1	0	1	N.BUFGLS_H[2]
1	1	1	0	1	1	0	N.BUFGLS_H[3]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_NE switchbox LLV muxes GCLK[1]
Bits							Destination
LLV[5][1]	LLV[7][1]	LLV[6][1]	LLV[6][0]	LLV[7][0]	LLV[4][0]	LLV[4][1]	S.GCLK[1]
							Source
0	0	1	1	1	1	1	S.DOUBLE_IO_E0[0]
0	1	0	1	1	1	1	S.DOUBLE_IO_E0[2]
0	1	1	0	1	1	1	S.BUFGE_V[1]
0	1	1	1	0	1	1	N.ECLK_V
1	0	1	1	1	0	1	N.BUFGLS_H[4]
1	0	1	1	1	1	0	N.BUFGLS_H[5]
1	1	0	1	1	0	1	N.BUFGLS_H[6]
1	1	0	1	1	1	0	N.BUFGLS_H[7]
1	1	1	0	1	0	1	N.BUFGLS_H[0]
1	1	1	0	1	1	0	N.BUFGLS_H[1]
1	1	1	1	0	0	1	N.BUFGLS_H[2]
1	1	1	1	0	1	0	N.BUFGLS_H[3]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_NE switchbox LLV muxes GCLK[2]
Bits							Destination
LLV[13][1]	LLV[14][1]	LLV[15][1]	LLV[15][0]	LLV[14][0]	LLV[12][0]	LLV[12][1]	S.GCLK[2]
							Source
0	0	1	1	1	1	1	S.DOUBLE_IO_E1[1]
0	1	0	1	1	1	1	S.DOUBLE_IO_E1[3]
0	1	1	0	1	1	1	N.ECLK_V
0	1	1	1	0	1	1	N.OUT_BUFF
1	0	1	1	1	0	1	N.BUFGLS_H[6]
1	0	1	1	1	1	0	N.BUFGLS_H[7]
1	1	0	1	1	0	1	N.BUFGLS_H[4]
1	1	0	1	1	1	0	N.BUFGLS_H[5]
1	1	1	0	1	0	1	N.BUFGLS_H[2]
1	1	1	0	1	1	0	N.BUFGLS_H[3]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_NE switchbox LLV muxes GCLK[3]
Bits							Destination
LLV[1][1]	LLV[2][1]	LLV[3][1]	LLV[3][0]	LLV[2][0]	LLV[0][0]	LLV[0][1]	S.GCLK[3]
							Source
0	0	1	1	1	1	1	S.DOUBLE_IO_E0[1]
0	1	0	1	1	1	1	S.DOUBLE_IO_E0[3]
0	1	1	0	1	1	1	S.BUFGE_V[0]
0	1	1	1	0	1	1	S.BUFGE_V[1]
1	0	1	1	1	0	1	N.BUFGLS_H[6]
1	0	1	1	1	1	0	N.BUFGLS_H[7]
1	1	0	1	1	0	1	N.BUFGLS_H[4]
1	1	0	1	1	1	0	N.BUFGLS_H[5]
1	1	1	0	1	0	1	N.BUFGLS_H[2]
1	1	1	0	1	1	0	N.BUFGLS_H[3]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_NE switchbox LLV muxes GCLK[4]
Bits							Destination
LLV[49][1]	LLV[51][0]	LLV[50][1]	LLV[51][1]	LLV[50][0]	LLV[49][0]	LLV[48][1]	S.GCLK[4]
							Source
0	0	1	1	1	1	1	S.VCLK
0	1	0	1	1	1	1	N.SINGLE_V[4]
0	1	1	0	1	1	1	N.QUAD_V0[1]
0	1	1	1	0	1	1	N.VCLK
1	0	1	1	1	0	1	N.BUFGLS_H[2]
1	0	1	1	1	1	0	N.BUFGLS_H[3]
1	1	0	1	1	0	1	N.BUFGLS_H[6]
1	1	0	1	1	1	0	N.BUFGLS_H[7]
1	1	1	0	1	0	1	N.BUFGLS_H[4]
1	1	1	0	1	1	0	N.BUFGLS_H[5]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_NE switchbox LLV muxes GCLK[5]
Bits							Destination
LLV[45][1]	LLV[47][1]	LLV[47][0]	LLV[46][1]	LLV[46][0]	LLV[44][0]	LLV[44][1]	S.GCLK[5]
							Source
0	0	1	1	1	1	1	S.QUAD_V3[2]
0	1	0	1	1	1	1	S.VCLK
0	1	1	0	1	1	1	N.SINGLE_V[5]
0	1	1	1	0	1	1	N.VCLK
1	0	1	1	1	0	1	N.BUFGLS_H[4]
1	0	1	1	1	1	0	N.BUFGLS_H[5]
1	1	0	1	1	0	1	N.BUFGLS_H[2]
1	1	0	1	1	1	0	N.BUFGLS_H[3]
1	1	1	0	1	0	1	N.BUFGLS_H[6]
1	1	1	0	1	1	0	N.BUFGLS_H[7]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_NE switchbox LLV muxes GCLK[6]
Bits							Destination
LLV[41][1]	LLV[43][1]	LLV[43][0]	LLV[42][1]	LLV[42][0]	LLV[40][0]	LLV[40][1]	S.GCLK[6]
							Source
0	0	1	1	1	1	1	S.QUAD_V4[2]
0	1	0	1	1	1	1	S.VCLK
0	1	1	0	1	1	1	N.SINGLE_V[6]
0	1	1	1	0	1	1	N.VCLK
1	0	1	1	1	0	1	N.BUFGLS_H[4]
1	0	1	1	1	1	0	N.BUFGLS_H[5]
1	1	0	1	1	0	1	N.BUFGLS_H[2]
1	1	0	1	1	1	0	N.BUFGLS_H[3]
1	1	1	0	1	0	1	N.BUFGLS_H[6]
1	1	1	0	1	1	0	N.BUFGLS_H[7]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_NE switchbox LLV muxes GCLK[7]
Bits							Destination
LLV[37][1]	LLV[39][0]	LLV[38][1]	LLV[39][1]	LLV[38][0]	LLV[37][0]	LLV[36][1]	S.GCLK[7]
							Source
0	0	1	1	1	1	1	S.VCLK
0	1	0	1	1	1	1	N.SINGLE_V[7]
0	1	1	0	1	1	1	N.QUAD_V0[2]
0	1	1	1	0	1	1	N.VCLK
1	0	1	1	1	0	1	N.BUFGLS_H[2]
1	0	1	1	1	1	0	N.BUFGLS_H[3]
1	1	0	1	1	0	1	N.BUFGLS_H[6]
1	1	0	1	1	1	0	N.BUFGLS_H[7]
1	1	1	0	1	0	1	N.BUFGLS_H[4]
1	1	1	0	1	1	0	N.BUFGLS_H[5]
1	1	1	1	0	0	1	N.BUFGLS_H[0]
1	1	1	1	0	1	0	N.BUFGLS_H[1]
1	1	1	1	1	1	1	off

xc4000ex LLVQ_IO_NE switchbox LLV muxes LONG_V[7]
Bits		Destination
LLV[25][0]	LLV[24][1]	N.LONG_V[7]
		Source
0	0	S.LONG_V[7]
0	1	S.VCLK
1	1	off

Bels BUFF

xc4000ex LLVQ_IO_NE bel BUFF pins
Pin	Direction	BUFF
O	out	N.OUT_BUFF

Bel wires

xc4000ex LLVQ_IO_NE bel wires
Wire	Pins
N.OUT_BUFF	BUFF.O

Bitstream

xc4000ex LLVQ_IO_NE rect LLV
Bit	Frame
Bit	F51	F50	F49	F48	F47	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B1	LLV: mux S.GCLK[4] bit 3	LLV: mux S.GCLK[4] bit 4	LLV: mux S.GCLK[4] bit 6	LLV: mux S.GCLK[4] bit 0	LLV: mux S.GCLK[5] bit 5	LLV: mux S.GCLK[5] bit 3	LLV: mux S.GCLK[5] bit 6	LLV: mux S.GCLK[5] bit 0	LLV: mux S.GCLK[6] bit 5	LLV: mux S.GCLK[6] bit 3	LLV: mux S.GCLK[6] bit 6	LLV: mux S.GCLK[6] bit 0	LLV: mux S.GCLK[7] bit 3	LLV: mux S.GCLK[7] bit 4	LLV: mux S.GCLK[7] bit 6	LLV: mux S.GCLK[7] bit 0	LLV: !buffer S.LONG_V[5] ← N.LONG_V[5]	LLV: !buffer S.LONG_V[3] ← N.LONG_V[3]	LLV: !buffer S.LONG_V[2] ← N.LONG_V[2]	LLV: !pass N.QUAD_V0[2] ← S.VCLK	LLV: !buffer S.LONG_V[0] ← N.LONG_V[0]	LLV: !pass S.QUAD_V4[1] ← S.VCLK	LLV: !buffer S.LONG_V[4] ← N.LONG_V[4]	LLV: !pass N.SINGLE_V[3] ← N.VCLK	LLV: !buffer S.LONG_V[1] ← N.LONG_V[1]	LLV: !buffer S.LONG_V[6] ← N.LONG_V[6]	LLV: !buffer S.LONG_V[7] ← N.LONG_V[7]	LLV: mux N.LONG_V[7] bit 0	LLV: !buffer S.LONG_V[8] ← N.LONG_V[8]	LLV: !buffer N.LONG_V[9] ← S.LONG_V[9]	LLV: mux S.LONG_V[9] bit 0	LLV: !buffer S.LONG_IO_V[0] ← N.LONG_IO_V[0]	LLV: !pass S.DOUBLE_IO_E0[3] ← N.ECLK_V	LLV: !buffer S.LONG_IO_V[2] ← N.LONG_IO_V[2]	LLV: !buffer S.LONG_IO_V[3] ← N.LONG_IO_V[3]	LLV: !buffer S.LONG_IO_V[1] ← N.LONG_IO_V[1]	LLV: mux S.GCLK[2] bit 4	LLV: mux S.GCLK[2] bit 5	LLV: mux S.GCLK[2] bit 6	LLV: mux S.GCLK[2] bit 0	LLV: mux S.GCLK[0] bit 5	LLV: mux S.GCLK[0] bit 4	LLV: mux S.GCLK[0] bit 6	LLV: mux S.GCLK[0] bit 0	LLV: mux S.GCLK[1] bit 5	LLV: mux S.GCLK[1] bit 4	LLV: mux S.GCLK[1] bit 6	LLV: mux S.GCLK[1] bit 0	LLV: mux S.GCLK[3] bit 4	LLV: mux S.GCLK[3] bit 5	LLV: mux S.GCLK[3] bit 6	LLV: mux S.GCLK[3] bit 0
B0	LLV: mux S.GCLK[4] bit 5	LLV: mux S.GCLK[4] bit 2	LLV: mux S.GCLK[4] bit 1	LLV: !pass N.SINGLE_V[4] ← S.VCLK	LLV: mux S.GCLK[5] bit 4	LLV: mux S.GCLK[5] bit 2	LLV: !pass N.SINGLE_V[5] ← N.VCLK	LLV: mux S.GCLK[5] bit 1	LLV: mux S.GCLK[6] bit 4	LLV: mux S.GCLK[6] bit 2	LLV: !pass N.SINGLE_V[6] ← S.VCLK	LLV: mux S.GCLK[6] bit 1	LLV: mux S.GCLK[7] bit 5	LLV: mux S.GCLK[7] bit 2	LLV: mux S.GCLK[7] bit 1	LLV: !pass N.SINGLE_V[7] ← N.VCLK	LLV: !buffer N.LONG_V[5] ← S.LONG_V[5]	LLV: !buffer N.LONG_V[3] ← S.LONG_V[3]	LLV: !buffer N.LONG_V[2] ← S.LONG_V[2]	LLV: !pass S.QUAD_V4[2] ← N.VCLK	LLV: !buffer N.LONG_V[0] ← S.LONG_V[0]	LLV: !pass N.QUAD_V0[0] ← N.VCLK	LLV: !buffer N.LONG_V[4] ← S.LONG_V[4]	LLV: !pass N.SINGLE_V[2] ← S.VCLK	LLV: !buffer N.LONG_V[1] ← S.LONG_V[1]	LLV: !buffer N.LONG_V[6] ← S.LONG_V[6]	LLV: mux N.LONG_V[7] bit 1	LLV: !pass N.SINGLE_V[0] ← S.VCLK	LLV: !buffer N.LONG_V[8] ← S.LONG_V[8]	LLV: mux S.LONG_V[9] bit 1	LLV: !pass N.SINGLE_V[1] ← N.VCLK	LLV: !buffer N.LONG_IO_V[0] ← S.LONG_IO_V[0]	LLV: !pass S.DOUBLE_IO_E1[0] ← N.ECLK_V	LLV: !buffer N.LONG_IO_V[2] ← S.LONG_IO_V[2]	LLV: !buffer N.LONG_IO_V[3] ← S.LONG_IO_V[3]	LLV: !buffer N.LONG_IO_V[1] ← S.LONG_IO_V[1]	LLV: mux S.GCLK[2] bit 3	LLV: mux S.GCLK[2] bit 2	-	LLV: mux S.GCLK[2] bit 1	LLV: mux S.GCLK[0] bit 3	LLV: mux S.GCLK[0] bit 2	LLV: !pass S.DOUBLE_IO_E0[1] ← N.ECLK_V	LLV: mux S.GCLK[0] bit 1	LLV: mux S.GCLK[1] bit 2	LLV: mux S.GCLK[1] bit 3	LLV: !pass S.DOUBLE_IO_E1[1] ← N.ECLK_V	LLV: mux S.GCLK[1] bit 1	LLV: mux S.GCLK[3] bit 3	LLV: mux S.GCLK[3] bit 2	LLV: !pass S.DOUBLE_IO_E1[2] ← N.ECLK_V	LLV: mux S.GCLK[3] bit 1

Tile CLKQC

Cells: 1

Switchbox CLKQC

xc4000ex CLKQC switchbox CLKQC
Destination	Source	Kind
BUFGLS_H[0]	BUFGLS[0]	fixed buffer
BUFGLS_H[1]	BUFGLS[1]	fixed buffer
BUFGLS_H[2]	BUFGLS[2]	fixed buffer
BUFGLS_H[3]	BUFGLS[3]	fixed buffer
BUFGLS_H[4]	BUFGLS[4]	fixed buffer
BUFGLS_H[5]	BUFGLS[5]	fixed buffer
BUFGLS_H[6]	BUFGLS[6]	fixed buffer
BUFGLS_H[7]	BUFGLS[7]	fixed buffer

Keyboard shortcuts

Project Combine