Splitters
Tile LLHC.CLB
Cells: 2 IRIs: 0
Muxes
Destination | Sources |
---|---|
TCELL0:LONG.H0 | TCELL1:LONG.H0 |
TCELL0:LONG.H1 | TCELL1:LONG.H1 |
TCELL0:LONG.H4 | TCELL1:LONG.H4 |
TCELL0:LONG.H5 | TCELL1:LONG.H5 |
TCELL1:LONG.H0 | TCELL0:LONG.H0 |
TCELL1:LONG.H1 | TCELL0:LONG.H1 |
TCELL1:LONG.H4 | TCELL0:LONG.H4 |
TCELL1:LONG.H5 | TCELL0:LONG.H5 |
Bel PULLUP_TBUF0_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:LONG.H2 |
Bel PULLUP_TBUF1_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:LONG.H3 |
Bel PULLUP_TBUF0_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:LONG.H2 |
Bel PULLUP_TBUF1_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:LONG.H3 |
Bel TBUF_SPLITTER0
Pin | Direction | Wires |
---|---|---|
L | in-out | TCELL0:LONG.H2 |
R | in-out | TCELL1:LONG.H2 |
Bel TBUF_SPLITTER1
Pin | Direction | Wires |
---|---|---|
L | in-out | TCELL0:LONG.H3 |
R | in-out | TCELL1:LONG.H3 |
Bel wires
Wire | Pins |
---|---|
TCELL0:LONG.H2 | PULLUP_TBUF0_W.O, TBUF_SPLITTER0.L |
TCELL0:LONG.H3 | PULLUP_TBUF1_W.O, TBUF_SPLITTER1.L |
TCELL1:LONG.H2 | PULLUP_TBUF0_E.O, TBUF_SPLITTER0.R |
TCELL1:LONG.H3 | PULLUP_TBUF1_E.O, TBUF_SPLITTER1.R |
Bitstream
Bit | Frame | |
---|---|---|
1 | 0 | |
11 | - | ~TBUF_SPLITTER1:BUF_W |
10 | ~PULLUP_TBUF1_W:ENABLE | ~TBUF_SPLITTER1:BUF_E |
9 | - | - |
8 | - | - |
7 | ~PULLUP_TBUF1_E:ENABLE | - |
6 | - | - |
5 | ~TBUF_SPLITTER1:PASS | - |
4 | - | - |
3 | - | ~INT:BUF.0.LONG.H5.1.LONG.H5 |
2 | - | ~INT:BUF.1.LONG.H5.0.LONG.H5 |
1 | - | ~INT:BUF.0.LONG.H4.1.LONG.H4 |
0 | - | ~INT:BUF.1.LONG.H4.0.LONG.H4 |
Bit | Frame | |
---|---|---|
1 | 0 | |
9 | ~TBUF_SPLITTER0:BUF_W | ~PULLUP_TBUF0_E:ENABLE |
8 | ~TBUF_SPLITTER0:BUF_E | - |
7 | - | ~INT:BUF.1.LONG.H1.0.LONG.H1 |
6 | ~TBUF_SPLITTER0:PASS | ~INT:BUF.0.LONG.H0.1.LONG.H0 |
5 | - | ~INT:BUF.1.LONG.H0.0.LONG.H0 |
4 | ~PULLUP_TBUF0_W:ENABLE | ~INT:BUF.0.LONG.H1.1.LONG.H1 |
3 | - | - |
2 | - | - |
1 | - | - |
0 | - | - |
INT:BUF.0.LONG.H0.1.LONG.H0 | 1.0.6 |
---|---|
INT:BUF.0.LONG.H1.1.LONG.H1 | 1.0.4 |
INT:BUF.0.LONG.H4.1.LONG.H4 | 0.0.1 |
INT:BUF.0.LONG.H5.1.LONG.H5 | 0.0.3 |
INT:BUF.1.LONG.H0.0.LONG.H0 | 1.0.5 |
INT:BUF.1.LONG.H1.0.LONG.H1 | 1.0.7 |
INT:BUF.1.LONG.H4.0.LONG.H4 | 0.0.0 |
INT:BUF.1.LONG.H5.0.LONG.H5 | 0.0.2 |
PULLUP_TBUF0_E:ENABLE | 1.0.9 |
PULLUP_TBUF0_W:ENABLE | 1.1.4 |
PULLUP_TBUF1_E:ENABLE | 0.1.7 |
PULLUP_TBUF1_W:ENABLE | 0.1.10 |
TBUF_SPLITTER0:BUF_E | 1.1.8 |
TBUF_SPLITTER0:BUF_W | 1.1.9 |
TBUF_SPLITTER0:PASS | 1.1.6 |
TBUF_SPLITTER1:BUF_E | 0.0.10 |
TBUF_SPLITTER1:BUF_W | 0.0.11 |
TBUF_SPLITTER1:PASS | 0.1.5 |
inverted | ~[0] |
Tile LLHC.CLB.B
Cells: 2 IRIs: 0
Muxes
Destination | Sources |
---|---|
TCELL0:LONG.H0 | TCELL1:LONG.H0 |
TCELL0:LONG.H1 | TCELL1:LONG.H1 |
TCELL0:LONG.H4 | TCELL1:LONG.H4 |
TCELL0:LONG.H5 | TCELL1:LONG.H5 |
TCELL1:LONG.H0 | TCELL0:LONG.H0 |
TCELL1:LONG.H1 | TCELL0:LONG.H1 |
TCELL1:LONG.H4 | TCELL0:LONG.H4 |
TCELL1:LONG.H5 | TCELL0:LONG.H5 |
Bel PULLUP_TBUF0_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:LONG.H2 |
Bel PULLUP_TBUF1_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:LONG.H3 |
Bel PULLUP_TBUF0_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:LONG.H2 |
Bel PULLUP_TBUF1_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:LONG.H3 |
Bel TBUF_SPLITTER0
Pin | Direction | Wires |
---|---|---|
L | in-out | TCELL0:LONG.H2 |
R | in-out | TCELL1:LONG.H2 |
Bel TBUF_SPLITTER1
Pin | Direction | Wires |
---|---|---|
L | in-out | TCELL0:LONG.H3 |
R | in-out | TCELL1:LONG.H3 |
Bel wires
Wire | Pins |
---|---|
TCELL0:LONG.H2 | PULLUP_TBUF0_W.O, TBUF_SPLITTER0.L |
TCELL0:LONG.H3 | PULLUP_TBUF1_W.O, TBUF_SPLITTER1.L |
TCELL1:LONG.H2 | PULLUP_TBUF0_E.O, TBUF_SPLITTER0.R |
TCELL1:LONG.H3 | PULLUP_TBUF1_E.O, TBUF_SPLITTER1.R |
Bitstream
Bit | Frame | |
---|---|---|
1 | 0 | |
11 | - | ~TBUF_SPLITTER1:BUF_W |
10 | ~PULLUP_TBUF1_W:ENABLE | ~TBUF_SPLITTER1:BUF_E |
9 | - | - |
8 | - | - |
7 | ~PULLUP_TBUF1_E:ENABLE | - |
6 | - | - |
5 | ~TBUF_SPLITTER1:PASS | - |
4 | - | - |
3 | - | ~INT:BUF.0.LONG.H5.1.LONG.H5 |
2 | - | ~INT:BUF.1.LONG.H5.0.LONG.H5 |
1 | - | ~INT:BUF.0.LONG.H4.1.LONG.H4 |
0 | - | ~INT:BUF.1.LONG.H4.0.LONG.H4 |
Bit | Frame | |
---|---|---|
1 | 0 | |
15 | ~INT:BUF.1.LONG.H0.0.LONG.H0 | ~INT:BUF.0.LONG.H0.1.LONG.H0 |
14 | ~INT:BUF.1.LONG.H1.0.LONG.H1 | ~TBUF_SPLITTER0:PASS |
13 | - | ~INT:BUF.0.LONG.H1.1.LONG.H1 |
12 | - | ~PULLUP_TBUF0_E:ENABLE |
11 | ~TBUF_SPLITTER0:BUF_E | ~TBUF_SPLITTER0:BUF_W |
10 | - | - |
9 | - | - |
8 | - | - |
7 | - | - |
6 | - | - |
5 | - | - |
4 | - | - |
3 | - | - |
2 | - | - |
1 | - | - |
0 | - | - |
Bit | Frame |
---|---|
0 | |
12 | ~PULLUP_TBUF0_W:ENABLE |
11 | - |
10 | - |
9 | - |
8 | - |
7 | - |
6 | - |
5 | - |
4 | - |
3 | - |
2 | - |
1 | - |
0 | - |
INT:BUF.0.LONG.H0.1.LONG.H0 | 1.0.15 |
---|---|
INT:BUF.0.LONG.H1.1.LONG.H1 | 1.0.13 |
INT:BUF.0.LONG.H4.1.LONG.H4 | 0.0.1 |
INT:BUF.0.LONG.H5.1.LONG.H5 | 0.0.3 |
INT:BUF.1.LONG.H0.0.LONG.H0 | 1.1.15 |
INT:BUF.1.LONG.H1.0.LONG.H1 | 1.1.14 |
INT:BUF.1.LONG.H4.0.LONG.H4 | 0.0.0 |
INT:BUF.1.LONG.H5.0.LONG.H5 | 0.0.2 |
PULLUP_TBUF0_E:ENABLE | 1.0.12 |
PULLUP_TBUF0_W:ENABLE | 2.0.12 |
PULLUP_TBUF1_E:ENABLE | 0.1.7 |
PULLUP_TBUF1_W:ENABLE | 0.1.10 |
TBUF_SPLITTER0:BUF_E | 1.1.11 |
TBUF_SPLITTER0:BUF_W | 1.0.11 |
TBUF_SPLITTER0:PASS | 1.0.14 |
TBUF_SPLITTER1:BUF_E | 0.0.10 |
TBUF_SPLITTER1:BUF_W | 0.0.11 |
TBUF_SPLITTER1:PASS | 0.1.5 |
inverted | ~[0] |
Tile LLHC.IO.B
Cells: 2 IRIs: 0
Muxes
Destination | Sources |
---|---|
TCELL0:LONG.H3 | TCELL1:LONG.H3 |
TCELL0:LONG.H4 | TCELL1:LONG.H4 |
TCELL0:LONG.H5 | TCELL1:LONG.H5 |
TCELL0:LONG.IO.H0 | TCELL1:LONG.IO.H0 |
TCELL0:LONG.IO.H1 | TCELL1:LONG.IO.H1 |
TCELL0:LONG.IO.H2 | TCELL1:LONG.IO.H2 |
TCELL0:LONG.IO.H3 | TCELL1:LONG.IO.H3 |
TCELL0:DEC.H0 | TCELL1:DEC.H0 |
TCELL0:DEC.H1 | TCELL1:DEC.H1 |
TCELL0:DEC.H2 | TCELL1:DEC.H2 |
TCELL0:DEC.H3 | TCELL1:DEC.H3 |
TCELL1:LONG.H3 | TCELL0:LONG.H3 |
TCELL1:LONG.H4 | TCELL0:LONG.H4 |
TCELL1:LONG.H5 | TCELL0:LONG.H5 |
TCELL1:LONG.IO.H0 | TCELL0:LONG.IO.H0 |
TCELL1:LONG.IO.H1 | TCELL0:LONG.IO.H1 |
TCELL1:LONG.IO.H2 | TCELL0:LONG.IO.H2 |
TCELL1:LONG.IO.H3 | TCELL0:LONG.IO.H3 |
TCELL1:DEC.H0 | TCELL0:DEC.H0 |
TCELL1:DEC.H1 | TCELL0:DEC.H1 |
TCELL1:DEC.H2 | TCELL0:DEC.H2 |
TCELL1:DEC.H3 | TCELL0:DEC.H3 |
Bel PULLUP_DEC0_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:DEC.H0 |
Bel PULLUP_DEC1_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:DEC.H1 |
Bel PULLUP_DEC2_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:DEC.H2 |
Bel PULLUP_DEC3_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:DEC.H3 |
Bel PULLUP_DEC0_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:DEC.H0 |
Bel PULLUP_DEC1_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:DEC.H1 |
Bel PULLUP_DEC2_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:DEC.H2 |
Bel PULLUP_DEC3_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:DEC.H3 |
Bel wires
Wire | Pins |
---|---|
TCELL0:DEC.H0 | PULLUP_DEC0_W.O |
TCELL0:DEC.H1 | PULLUP_DEC1_W.O |
TCELL0:DEC.H2 | PULLUP_DEC2_W.O |
TCELL0:DEC.H3 | PULLUP_DEC3_W.O |
TCELL1:DEC.H0 | PULLUP_DEC0_E.O |
TCELL1:DEC.H1 | PULLUP_DEC1_E.O |
TCELL1:DEC.H2 | PULLUP_DEC2_E.O |
TCELL1:DEC.H3 | PULLUP_DEC3_E.O |
Bitstream
Bit | Frame |
---|---|
0 | |
15 | ~PULLUP_DEC1_W:ENABLE |
14 | ~PULLUP_DEC0_E:ENABLE |
13 | ~PULLUP_DEC0_W:ENABLE |
12 | - |
11 | - |
10 | ~INT:BIPASS.0.DEC.H0.1.DEC.H0 |
9 | - |
8 | - |
7 | - |
6 | - |
5 | - |
4 | ~INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1 |
3 | - |
2 | ~INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2 |
1 | - |
0 | - |
INT:BIPASS.0.DEC.H0.1.DEC.H0 | 1.0.10 |
---|---|
INT:BIPASS.0.DEC.H1.1.DEC.H1 | 0.0.10 |
INT:BIPASS.0.DEC.H2.1.DEC.H2 | 0.0.4 |
INT:BIPASS.0.DEC.H3.1.DEC.H3 | 0.1.4 |
INT:BUF.0.LONG.H3.1.LONG.H3 | 0.0.8 |
INT:BUF.0.LONG.H4.1.LONG.H4 | 0.0.5 |
INT:BUF.0.LONG.H5.1.LONG.H5 | 0.0.3 |
INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0 | 0.0.7 |
INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1 | 1.0.4 |
INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2 | 1.0.2 |
INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3 | 0.0.0 |
INT:BUF.1.LONG.H3.0.LONG.H3 | 0.1.9 |
INT:BUF.1.LONG.H4.0.LONG.H4 | 0.1.5 |
INT:BUF.1.LONG.H5.0.LONG.H5 | 0.1.3 |
INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0 | 0.1.6 |
INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1 | 0.1.7 |
INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2 | 0.1.2 |
INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3 | 0.1.1 |
PULLUP_DEC0_E:ENABLE | 1.0.14 |
PULLUP_DEC0_W:ENABLE | 1.0.13 |
PULLUP_DEC1_E:ENABLE | 0.1.13 |
PULLUP_DEC1_W:ENABLE | 1.0.15 |
PULLUP_DEC2_E:ENABLE | 0.1.10 |
PULLUP_DEC2_W:ENABLE | 0.1.12 |
PULLUP_DEC3_E:ENABLE | 0.0.1 |
PULLUP_DEC3_W:ENABLE | 0.1.0 |
inverted | ~[0] |
Tile LLHC.IO.T
Cells: 2 IRIs: 0
Muxes
Destination | Sources |
---|---|
TCELL0:LONG.H0 | TCELL1:LONG.H0 |
TCELL0:LONG.H1 | TCELL1:LONG.H1 |
TCELL0:LONG.H2 | TCELL1:LONG.H2 |
TCELL0:LONG.IO.H0 | TCELL1:LONG.IO.H0 |
TCELL0:LONG.IO.H1 | TCELL1:LONG.IO.H1 |
TCELL0:LONG.IO.H2 | TCELL1:LONG.IO.H2 |
TCELL0:LONG.IO.H3 | TCELL1:LONG.IO.H3 |
TCELL0:DEC.H0 | TCELL1:DEC.H0 |
TCELL0:DEC.H1 | TCELL1:DEC.H1 |
TCELL0:DEC.H2 | TCELL1:DEC.H2 |
TCELL0:DEC.H3 | TCELL1:DEC.H3 |
TCELL1:LONG.H0 | TCELL0:LONG.H0 |
TCELL1:LONG.H1 | TCELL0:LONG.H1 |
TCELL1:LONG.H2 | TCELL0:LONG.H2 |
TCELL1:LONG.IO.H0 | TCELL0:LONG.IO.H0 |
TCELL1:LONG.IO.H1 | TCELL0:LONG.IO.H1 |
TCELL1:LONG.IO.H2 | TCELL0:LONG.IO.H2 |
TCELL1:LONG.IO.H3 | TCELL0:LONG.IO.H3 |
TCELL1:DEC.H0 | TCELL0:DEC.H0 |
TCELL1:DEC.H1 | TCELL0:DEC.H1 |
TCELL1:DEC.H2 | TCELL0:DEC.H2 |
TCELL1:DEC.H3 | TCELL0:DEC.H3 |
Bel PULLUP_DEC0_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:DEC.H0 |
Bel PULLUP_DEC1_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:DEC.H1 |
Bel PULLUP_DEC2_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:DEC.H2 |
Bel PULLUP_DEC3_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:DEC.H3 |
Bel PULLUP_DEC0_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:DEC.H0 |
Bel PULLUP_DEC1_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:DEC.H1 |
Bel PULLUP_DEC2_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:DEC.H2 |
Bel PULLUP_DEC3_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:DEC.H3 |
Bel wires
Wire | Pins |
---|---|
TCELL0:DEC.H0 | PULLUP_DEC0_W.O |
TCELL0:DEC.H1 | PULLUP_DEC1_W.O |
TCELL0:DEC.H2 | PULLUP_DEC2_W.O |
TCELL0:DEC.H3 | PULLUP_DEC3_W.O |
TCELL1:DEC.H0 | PULLUP_DEC0_E.O |
TCELL1:DEC.H1 | PULLUP_DEC1_E.O |
TCELL1:DEC.H2 | PULLUP_DEC2_E.O |
TCELL1:DEC.H3 | PULLUP_DEC3_E.O |
Bitstream
Bit | Frame | |
---|---|---|
1 | 0 | |
9 | ~INT:BUF.0.LONG.H2.1.LONG.H2 | - |
8 | ~INT:BUF.1.LONG.H2.0.LONG.H2 | - |
7 | - | ~INT:BUF.1.LONG.H1.0.LONG.H1 |
6 | - | ~INT:BUF.0.LONG.H0.1.LONG.H0 |
5 | - | ~INT:BUF.1.LONG.H0.0.LONG.H0 |
4 | - | ~INT:BUF.0.LONG.H1.1.LONG.H1 |
3 | - | - |
2 | - | - |
1 | - | - |
0 | - | - |
Bit | Frame |
---|---|
0 | |
7 | ~INT:BIPASS.0.DEC.H2.1.DEC.H2 |
6 | - |
5 | ~INT:BIPASS.0.DEC.H1.1.DEC.H1 |
4 | - |
3 | ~INT:BIPASS.0.DEC.H0.1.DEC.H0 |
2 | ~INT:BIPASS.0.DEC.H3.1.DEC.H3 |
1 | ~INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0 |
0 | ~INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0 |
INT:BIPASS.0.DEC.H0.1.DEC.H0 | 2.0.3 |
---|---|
INT:BIPASS.0.DEC.H1.1.DEC.H1 | 2.0.5 |
INT:BIPASS.0.DEC.H2.1.DEC.H2 | 2.0.7 |
INT:BIPASS.0.DEC.H3.1.DEC.H3 | 2.0.2 |
INT:BUF.0.LONG.H0.1.LONG.H0 | 1.0.6 |
INT:BUF.0.LONG.H1.1.LONG.H1 | 1.0.4 |
INT:BUF.0.LONG.H2.1.LONG.H2 | 1.1.9 |
INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0 | 2.0.0 |
INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1 | 0.1.1 |
INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2 | 0.1.4 |
INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3 | 0.1.5 |
INT:BUF.1.LONG.H0.0.LONG.H0 | 1.0.5 |
INT:BUF.1.LONG.H1.0.LONG.H1 | 1.0.7 |
INT:BUF.1.LONG.H2.0.LONG.H2 | 1.1.8 |
INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0 | 2.0.1 |
INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1 | 0.0.1 |
INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2 | 0.0.4 |
INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3 | 0.0.5 |
PULLUP_DEC0_E:ENABLE | 0.1.2 |
PULLUP_DEC0_W:ENABLE | 0.0.2 |
PULLUP_DEC1_E:ENABLE | 0.1.6 |
PULLUP_DEC1_W:ENABLE | 0.0.6 |
PULLUP_DEC2_E:ENABLE | 0.0.3 |
PULLUP_DEC2_W:ENABLE | 0.1.3 |
PULLUP_DEC3_E:ENABLE | 0.0.0 |
PULLUP_DEC3_W:ENABLE | 0.1.0 |
inverted | ~[0] |
Tile LLHQ.CLB
Cells: 2 IRIs: 0
Muxes
Destination | Sources |
---|---|
TCELL0:LONG.H0 | TCELL1:LONG.H0 |
TCELL0:LONG.H1 | TCELL1:LONG.H1 |
TCELL0:LONG.H4 | TCELL1:LONG.H4 |
TCELL0:LONG.H5 | TCELL1:LONG.H5 |
TCELL1:LONG.H0 | TCELL0:LONG.H0 |
TCELL1:LONG.H1 | TCELL0:LONG.H1 |
TCELL1:LONG.H4 | TCELL0:LONG.H4 |
TCELL1:LONG.H5 | TCELL0:LONG.H5 |
Bel PULLUP_TBUF0_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:LONG.H2 |
Bel PULLUP_TBUF1_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:LONG.H3 |
Bel PULLUP_TBUF0_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:LONG.H2 |
Bel PULLUP_TBUF1_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:LONG.H3 |
Bel wires
Wire | Pins |
---|---|
TCELL0:LONG.H2 | PULLUP_TBUF0_W.O, PULLUP_TBUF0_E.O |
TCELL0:LONG.H3 | PULLUP_TBUF1_W.O, PULLUP_TBUF1_E.O |
Bitstream
Bit | Frame |
---|---|
0 | |
5 | ~PULLUP_TBUF1_E:ENABLE |
4 | ~PULLUP_TBUF1_W:ENABLE |
3 | ~INT:BUF.0.LONG.H4.1.LONG.H4 |
2 | ~INT:BUF.1.LONG.H4.0.LONG.H4 |
1 | ~INT:BUF.1.LONG.H5.0.LONG.H5 |
0 | ~INT:BUF.0.LONG.H5.1.LONG.H5 |
Bit | Frame |
---|---|
0 | |
11 | ~INT:BUF.1.LONG.H0.0.LONG.H0 |
10 | ~INT:BUF.0.LONG.H0.1.LONG.H0 |
9 | ~INT:BUF.1.LONG.H1.0.LONG.H1 |
8 | ~INT:BUF.0.LONG.H1.1.LONG.H1 |
7 | ~PULLUP_TBUF0_E:ENABLE |
6 | ~PULLUP_TBUF0_W:ENABLE |
5 | - |
4 | - |
3 | - |
2 | - |
1 | - |
0 | - |
INT:BUF.0.LONG.H0.1.LONG.H0 | 1.0.10 |
---|---|
INT:BUF.0.LONG.H1.1.LONG.H1 | 1.0.8 |
INT:BUF.0.LONG.H4.1.LONG.H4 | 0.0.3 |
INT:BUF.0.LONG.H5.1.LONG.H5 | 0.0.0 |
INT:BUF.1.LONG.H0.0.LONG.H0 | 1.0.11 |
INT:BUF.1.LONG.H1.0.LONG.H1 | 1.0.9 |
INT:BUF.1.LONG.H4.0.LONG.H4 | 0.0.2 |
INT:BUF.1.LONG.H5.0.LONG.H5 | 0.0.1 |
PULLUP_TBUF0_E:ENABLE | 1.0.7 |
PULLUP_TBUF0_W:ENABLE | 1.0.6 |
PULLUP_TBUF1_E:ENABLE | 0.0.5 |
PULLUP_TBUF1_W:ENABLE | 0.0.4 |
inverted | ~[0] |
Tile LLHQ.CLB.B
Cells: 2 IRIs: 0
Muxes
Destination | Sources |
---|---|
TCELL0:LONG.H0 | TCELL1:LONG.H0 |
TCELL0:LONG.H1 | TCELL1:LONG.H1 |
TCELL0:LONG.H4 | TCELL1:LONG.H4 |
TCELL0:LONG.H5 | TCELL1:LONG.H5 |
TCELL1:LONG.H0 | TCELL0:LONG.H0 |
TCELL1:LONG.H1 | TCELL0:LONG.H1 |
TCELL1:LONG.H4 | TCELL0:LONG.H4 |
TCELL1:LONG.H5 | TCELL0:LONG.H5 |
Bel PULLUP_TBUF0_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:LONG.H2 |
Bel PULLUP_TBUF1_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:LONG.H3 |
Bel PULLUP_TBUF0_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:LONG.H2 |
Bel PULLUP_TBUF1_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:LONG.H3 |
Bel wires
Wire | Pins |
---|---|
TCELL0:LONG.H2 | PULLUP_TBUF0_W.O, PULLUP_TBUF0_E.O |
TCELL0:LONG.H3 | PULLUP_TBUF1_W.O, PULLUP_TBUF1_E.O |
Bitstream
Bit | Frame |
---|---|
0 | |
5 | ~PULLUP_TBUF1_E:ENABLE |
4 | ~PULLUP_TBUF1_W:ENABLE |
3 | ~INT:BUF.0.LONG.H4.1.LONG.H4 |
2 | ~INT:BUF.1.LONG.H4.0.LONG.H4 |
1 | ~INT:BUF.1.LONG.H5.0.LONG.H5 |
0 | ~INT:BUF.0.LONG.H5.1.LONG.H5 |
Bit | Frame |
---|
Bit | Frame |
---|---|
0 | |
15 | ~PULLUP_TBUF0_E:ENABLE |
14 | ~PULLUP_TBUF0_W:ENABLE |
13 | ~INT:BUF.0.LONG.H0.1.LONG.H0 |
12 | ~INT:BUF.1.LONG.H0.0.LONG.H0 |
11 | ~INT:BUF.0.LONG.H1.1.LONG.H1 |
10 | ~INT:BUF.1.LONG.H1.0.LONG.H1 |
9 | - |
8 | - |
7 | - |
6 | - |
5 | - |
4 | - |
3 | - |
2 | - |
1 | - |
0 | - |
INT:BUF.0.LONG.H0.1.LONG.H0 | 2.0.13 |
---|---|
INT:BUF.0.LONG.H1.1.LONG.H1 | 2.0.11 |
INT:BUF.0.LONG.H4.1.LONG.H4 | 0.0.3 |
INT:BUF.0.LONG.H5.1.LONG.H5 | 0.0.0 |
INT:BUF.1.LONG.H0.0.LONG.H0 | 2.0.12 |
INT:BUF.1.LONG.H1.0.LONG.H1 | 2.0.10 |
INT:BUF.1.LONG.H4.0.LONG.H4 | 0.0.2 |
INT:BUF.1.LONG.H5.0.LONG.H5 | 0.0.1 |
PULLUP_TBUF0_E:ENABLE | 2.0.15 |
PULLUP_TBUF0_W:ENABLE | 2.0.14 |
PULLUP_TBUF1_E:ENABLE | 0.0.5 |
PULLUP_TBUF1_W:ENABLE | 0.0.4 |
inverted | ~[0] |
Tile LLHQ.CLB.T
Cells: 2 IRIs: 0
Muxes
Destination | Sources |
---|---|
TCELL0:LONG.H0 | TCELL1:LONG.H0 |
TCELL0:LONG.H1 | TCELL1:LONG.H1 |
TCELL0:LONG.H4 | TCELL1:LONG.H4 |
TCELL0:LONG.H5 | TCELL1:LONG.H5 |
TCELL1:LONG.H0 | TCELL0:LONG.H0 |
TCELL1:LONG.H1 | TCELL0:LONG.H1 |
TCELL1:LONG.H4 | TCELL0:LONG.H4 |
TCELL1:LONG.H5 | TCELL0:LONG.H5 |
Bel PULLUP_TBUF0_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:LONG.H2 |
Bel PULLUP_TBUF1_W
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:LONG.H3 |
Bel PULLUP_TBUF0_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:LONG.H2 |
Bel PULLUP_TBUF1_E
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:LONG.H3 |
Bel wires
Wire | Pins |
---|---|
TCELL0:LONG.H2 | PULLUP_TBUF0_W.O, PULLUP_TBUF0_E.O |
TCELL0:LONG.H3 | PULLUP_TBUF1_W.O, PULLUP_TBUF1_E.O |
Bitstream
Bit | Frame |
---|---|
0 | |
5 | ~PULLUP_TBUF1_W:ENABLE |
4 | ~PULLUP_TBUF1_E:ENABLE |
3 | ~INT:BUF.0.LONG.H4.1.LONG.H4 |
2 | ~INT:BUF.1.LONG.H4.0.LONG.H4 |
1 | ~INT:BUF.1.LONG.H5.0.LONG.H5 |
0 | ~INT:BUF.0.LONG.H5.1.LONG.H5 |
Bit | Frame |
---|---|
0 | |
11 | ~INT:BUF.1.LONG.H0.0.LONG.H0 |
10 | ~INT:BUF.0.LONG.H0.1.LONG.H0 |
9 | ~INT:BUF.1.LONG.H1.0.LONG.H1 |
8 | ~INT:BUF.0.LONG.H1.1.LONG.H1 |
7 | ~PULLUP_TBUF0_E:ENABLE |
6 | ~PULLUP_TBUF0_W:ENABLE |
5 | - |
4 | - |
3 | - |
2 | - |
1 | - |
0 | - |
INT:BUF.0.LONG.H0.1.LONG.H0 | 1.0.10 |
---|---|
INT:BUF.0.LONG.H1.1.LONG.H1 | 1.0.8 |
INT:BUF.0.LONG.H4.1.LONG.H4 | 0.0.3 |
INT:BUF.0.LONG.H5.1.LONG.H5 | 0.0.0 |
INT:BUF.1.LONG.H0.0.LONG.H0 | 1.0.11 |
INT:BUF.1.LONG.H1.0.LONG.H1 | 1.0.9 |
INT:BUF.1.LONG.H4.0.LONG.H4 | 0.0.2 |
INT:BUF.1.LONG.H5.0.LONG.H5 | 0.0.1 |
PULLUP_TBUF0_E:ENABLE | 1.0.7 |
PULLUP_TBUF0_W:ENABLE | 1.0.6 |
PULLUP_TBUF1_E:ENABLE | 0.0.4 |
PULLUP_TBUF1_W:ENABLE | 0.0.5 |
inverted | ~[0] |
Tile LLHQ.IO.B
Cells: 2 IRIs: 0
Muxes
Destination | Sources |
---|---|
TCELL0:LONG.H3 | TCELL1:LONG.H3 |
TCELL0:LONG.H4 | TCELL1:LONG.H4 |
TCELL0:LONG.H5 | TCELL1:LONG.H5 |
TCELL0:LONG.IO.H0 | TCELL1:LONG.IO.H0 |
TCELL0:LONG.IO.H1 | TCELL1:LONG.IO.H1 |
TCELL0:LONG.IO.H2 | TCELL1:LONG.IO.H2 |
TCELL0:LONG.IO.H3 | TCELL1:LONG.IO.H3 |
TCELL1:LONG.H3 | TCELL0:LONG.H3 |
TCELL1:LONG.H4 | TCELL0:LONG.H4 |
TCELL1:LONG.H5 | TCELL0:LONG.H5 |
TCELL1:LONG.IO.H0 | TCELL0:LONG.IO.H0 |
TCELL1:LONG.IO.H1 | TCELL0:LONG.IO.H1 |
TCELL1:LONG.IO.H2 | TCELL0:LONG.IO.H2 |
TCELL1:LONG.IO.H3 | TCELL0:LONG.IO.H3 |
Bitstream
Bit | Frame |
---|---|
0 | |
11 | ~INT:BUF.0.LONG.H3.1.LONG.H3 |
10 | ~INT:BUF.1.LONG.H3.0.LONG.H3 |
9 | - |
8 | - |
7 | ~INT:BUF.1.LONG.H5.0.LONG.H5 |
6 | ~INT:BUF.0.LONG.H5.1.LONG.H5 |
5 | ~INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1 |
4 | ~INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1 |
3 | - |
2 | - |
1 | ~INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3 |
0 | ~INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3 |
Bit | Frame |
---|---|
0 | |
7 | ~INT:BUF.1.LONG.H4.0.LONG.H4 |
6 | ~INT:BUF.0.LONG.H4.1.LONG.H4 |
5 | ~INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0 |
4 | ~INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0 |
3 | - |
2 | - |
1 | ~INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2 |
0 | ~INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2 |
INT:BUF.0.LONG.H3.1.LONG.H3 | 0.0.11 |
---|---|
INT:BUF.0.LONG.H4.1.LONG.H4 | 1.0.6 |
INT:BUF.0.LONG.H5.1.LONG.H5 | 0.0.6 |
INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0 | 1.0.4 |
INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1 | 0.0.4 |
INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2 | 1.0.0 |
INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3 | 0.0.0 |
INT:BUF.1.LONG.H3.0.LONG.H3 | 0.0.10 |
INT:BUF.1.LONG.H4.0.LONG.H4 | 1.0.7 |
INT:BUF.1.LONG.H5.0.LONG.H5 | 0.0.7 |
INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0 | 1.0.5 |
INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1 | 0.0.5 |
INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2 | 1.0.1 |
INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3 | 0.0.1 |
inverted | ~[0] |
Tile LLHQ.IO.T
Cells: 2 IRIs: 0
Muxes
Destination | Sources |
---|---|
TCELL0:LONG.H0 | TCELL1:LONG.H0 |
TCELL0:LONG.H1 | TCELL1:LONG.H1 |
TCELL0:LONG.H2 | TCELL1:LONG.H2 |
TCELL0:LONG.IO.H0 | TCELL1:LONG.IO.H0 |
TCELL0:LONG.IO.H1 | TCELL1:LONG.IO.H1 |
TCELL0:LONG.IO.H2 | TCELL1:LONG.IO.H2 |
TCELL0:LONG.IO.H3 | TCELL1:LONG.IO.H3 |
TCELL1:LONG.H0 | TCELL0:LONG.H0 |
TCELL1:LONG.H1 | TCELL0:LONG.H1 |
TCELL1:LONG.H2 | TCELL0:LONG.H2 |
TCELL1:LONG.IO.H0 | TCELL0:LONG.IO.H0 |
TCELL1:LONG.IO.H1 | TCELL0:LONG.IO.H1 |
TCELL1:LONG.IO.H2 | TCELL0:LONG.IO.H2 |
TCELL1:LONG.IO.H3 | TCELL0:LONG.IO.H3 |
Bitstream
Bit | Frame |
---|---|
0 | |
11 | ~INT:BUF.1.LONG.H0.0.LONG.H0 |
10 | ~INT:BUF.0.LONG.H0.1.LONG.H0 |
9 | ~INT:BUF.1.LONG.H1.0.LONG.H1 |
8 | ~INT:BUF.0.LONG.H1.1.LONG.H1 |
7 | ~INT:BUF.1.LONG.H2.0.LONG.H2 |
6 | ~INT:BUF.0.LONG.H2.1.LONG.H2 |
5 | - |
4 | - |
3 | - |
2 | - |
1 | - |
0 | - |
INT:BUF.0.LONG.H0.1.LONG.H0 | 1.0.10 |
---|---|
INT:BUF.0.LONG.H1.1.LONG.H1 | 1.0.8 |
INT:BUF.0.LONG.H2.1.LONG.H2 | 1.0.6 |
INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0 | 0.0.1 |
INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1 | 0.0.3 |
INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2 | 0.0.5 |
INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3 | 0.0.7 |
INT:BUF.1.LONG.H0.0.LONG.H0 | 1.0.11 |
INT:BUF.1.LONG.H1.0.LONG.H1 | 1.0.9 |
INT:BUF.1.LONG.H2.0.LONG.H2 | 1.0.7 |
INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0 | 0.0.0 |
INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1 | 0.0.2 |
INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2 | 0.0.4 |
INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3 | 0.0.6 |
inverted | ~[0] |
Tile LLVC.CLB
Cells: 2 IRIs: 0
Muxes
Destination | Sources |
---|---|
TCELL0:LONG.V0 | TCELL1:LONG.V0 |
TCELL0:LONG.V1 | TCELL1:LONG.V1 |
TCELL0:LONG.V2 | TCELL1:LONG.V2 |
TCELL0:LONG.V3 | TCELL1:LONG.V3 |
TCELL0:LONG.V4 | TCELL1:LONG.V4 |
TCELL0:LONG.V5 | TCELL1:LONG.V5 |
TCELL0:LONG.V6 | TCELL1:LONG.V6 |
TCELL0:LONG.V7 | TCELL1:LONG.V7 |
TCELL0:LONG.V8 | TCELL1:LONG.V8 |
TCELL0:LONG.V9 | TCELL1:LONG.V9 |
TCELL0:VCLK | TCELL0:QUAD.V0.4, TCELL1:SINGLE.V0, TCELL1:SINGLE.V1, TCELL1:SINGLE.V2, TCELL1:SINGLE.V4, TCELL1:SINGLE.V5, TCELL1:QUAD.V2.0, TCELL1:LONG.V0, TCELL1:LONG.V4, TCELL1:LONG.V6, TCELL1:GCLK2, TCELL1:GCLK5 |
TCELL1:LONG.V0 | TCELL0:LONG.V0 |
TCELL1:LONG.V1 | TCELL0:LONG.V1 |
TCELL1:LONG.V2 | TCELL0:LONG.V2 |
TCELL1:LONG.V3 | TCELL0:LONG.V3 |
TCELL1:LONG.V4 | TCELL0:LONG.V4 |
TCELL1:LONG.V5 | TCELL0:LONG.V5 |
TCELL1:LONG.V6 | TCELL0:LONG.V6 |
TCELL1:LONG.V7 | TCELL0:LONG.V7 |
TCELL1:LONG.V8 | TCELL0:LONG.V8 |
TCELL1:LONG.V9 | TCELL0:LONG.V9 |
TCELL1:VCLK | TCELL0:QUAD.V1.4, TCELL0:LONG.V1, TCELL0:LONG.V5, TCELL0:LONG.V8, TCELL0:GCLK1, TCELL0:GCLK4, TCELL1:SINGLE.V0, TCELL1:SINGLE.V1, TCELL1:SINGLE.V4, TCELL1:SINGLE.V5, TCELL1:SINGLE.V6, TCELL1:QUAD.V0.0 |
Bitstream
INT:BUF.0.LONG.V0.1.LONG.V0 | 0.26.1 |
---|---|
INT:BUF.0.LONG.V1.1.LONG.V1 | 0.28.1 |
INT:BUF.0.LONG.V2.1.LONG.V2 | 0.22.1 |
INT:BUF.0.LONG.V3.1.LONG.V3 | 0.41.1 |
INT:BUF.0.LONG.V4.1.LONG.V4 | 0.24.1 |
INT:BUF.0.LONG.V5.1.LONG.V5 | 0.43.1 |
INT:BUF.0.LONG.V6.1.LONG.V6 | 0.45.1 |
INT:BUF.0.LONG.V7.1.LONG.V7 | 0.38.1 |
INT:BUF.0.LONG.V8.1.LONG.V8 | 0.34.1 |
INT:BUF.0.LONG.V9.1.LONG.V9 | 0.33.1 |
INT:BUF.1.LONG.V0.0.LONG.V0 | 0.25.1 |
INT:BUF.1.LONG.V1.0.LONG.V1 | 0.27.1 |
INT:BUF.1.LONG.V2.0.LONG.V2 | 0.23.1 |
INT:BUF.1.LONG.V3.0.LONG.V3 | 0.40.1 |
INT:BUF.1.LONG.V4.0.LONG.V4 | 0.30.1 |
INT:BUF.1.LONG.V5.0.LONG.V5 | 0.42.1 |
INT:BUF.1.LONG.V6.0.LONG.V6 | 0.44.1 |
INT:BUF.1.LONG.V7.0.LONG.V7 | 0.39.1 |
INT:BUF.1.LONG.V8.0.LONG.V8 | 0.35.1 |
INT:BUF.1.LONG.V9.0.LONG.V9 | 0.32.1 |
inverted | ~[0] |
INT:MUX.0.VCLK | 0.5.0 | 0.6.0 | 0.15.0 | 0.35.0 | 0.14.0 | 0.8.0 | 0.7.0 |
---|---|---|---|---|---|---|---|
0.QUAD.V0.4 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
1.LONG.V0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 |
1.QUAD.V2.0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
1.LONG.V6 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
1.SINGLE.V1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
1.SINGLE.V2 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
1.GCLK5 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.SINGLE.V4 | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.SINGLE.V5 | 1 | 0 | 0 | 1 | 1 | 1 | 1 |
1.LONG.V4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.GCLK2 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.SINGLE.V0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.1.VCLK | 0.19.0 | 0.18.0 | 0.23.0 | 0.34.0 | 0.29.0 | 0.28.0 | 0.22.0 |
---|---|---|---|---|---|---|---|
0.QUAD.V1.4 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
1.SINGLE.V1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 |
1.QUAD.V0.0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
0.LONG.V8 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
0.LONG.V1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
1.SINGLE.V4 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
0.LONG.V5 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.SINGLE.V6 | 0 | 1 | 1 | 1 | 1 | 0 | 1 |
0.GCLK1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 |
0.GCLK4 | 1 | 0 | 1 | 0 | 1 | 1 | 1 |
1.SINGLE.V5 | 1 | 0 | 1 | 1 | 0 | 1 | 1 |
1.SINGLE.V0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Tile LLVC.IO.L
Cells: 2 IRIs: 0
Muxes
Destination | Sources |
---|---|
TCELL0:LONG.IO.V0 | TCELL1:LONG.IO.V0 |
TCELL0:LONG.IO.V1 | TCELL1:LONG.IO.V1 |
TCELL0:LONG.IO.V2 | TCELL1:LONG.IO.V2 |
TCELL0:LONG.IO.V3 | TCELL1:LONG.IO.V3 |
TCELL0:DEC.V0 | TCELL1:DEC.V0 |
TCELL0:DEC.V1 | TCELL1:DEC.V1 |
TCELL0:DEC.V2 | TCELL1:DEC.V2 |
TCELL0:DEC.V3 | TCELL1:DEC.V3 |
TCELL1:LONG.IO.V0 | TCELL0:LONG.IO.V0 |
TCELL1:LONG.IO.V1 | TCELL0:LONG.IO.V1 |
TCELL1:LONG.IO.V2 | TCELL0:LONG.IO.V2 |
TCELL1:LONG.IO.V3 | TCELL0:LONG.IO.V3 |
TCELL1:DEC.V0 | TCELL0:DEC.V0 |
TCELL1:DEC.V1 | TCELL0:DEC.V1 |
TCELL1:DEC.V2 | TCELL0:DEC.V2 |
TCELL1:DEC.V3 | TCELL0:DEC.V3 |
Bel PULLUP_DEC0_S
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:DEC.V0 |
Bel PULLUP_DEC1_S
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:DEC.V1 |
Bel PULLUP_DEC2_S
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:DEC.V2 |
Bel PULLUP_DEC3_S
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:DEC.V3 |
Bel PULLUP_DEC0_N
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:DEC.V0 |
Bel PULLUP_DEC1_N
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:DEC.V1 |
Bel PULLUP_DEC2_N
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:DEC.V2 |
Bel PULLUP_DEC3_N
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:DEC.V3 |
Bel wires
Wire | Pins |
---|---|
TCELL0:DEC.V0 | PULLUP_DEC0_S.O |
TCELL0:DEC.V1 | PULLUP_DEC1_S.O |
TCELL0:DEC.V2 | PULLUP_DEC2_S.O |
TCELL0:DEC.V3 | PULLUP_DEC3_S.O |
TCELL1:DEC.V0 | PULLUP_DEC0_N.O |
TCELL1:DEC.V1 | PULLUP_DEC1_N.O |
TCELL1:DEC.V2 | PULLUP_DEC2_N.O |
TCELL1:DEC.V3 | PULLUP_DEC3_N.O |
Bitstream
Bit | Frame | |||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
1 | ~INT:BIPASS.0.DEC.V1.1.DEC.V1 | ~INT:BIPASS.0.DEC.V3.1.DEC.V3 | ~PULLUP_DEC3_S:ENABLE | ~PULLUP_DEC3_N:ENABLE | ~PULLUP_DEC1_N:ENABLE | ~PULLUP_DEC1_S:ENABLE | ~PULLUP_DEC2_S:ENABLE | ~PULLUP_DEC2_N:ENABLE | ~INT:BIPASS.0.DEC.V0.1.DEC.V0 | ~INT:BIPASS.0.DEC.V2.1.DEC.V2 | ~PULLUP_DEC0_N:ENABLE | ~PULLUP_DEC0_S:ENABLE | ~INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 | ~INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 | ~INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 | ~INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 | - | - | ~INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 | ~INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 | ~INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 | ~INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 | - | - | - | - |
0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
INT:BIPASS.0.DEC.V0.1.DEC.V0 | 0.17.1 |
---|---|
INT:BIPASS.0.DEC.V1.1.DEC.V1 | 0.25.1 |
INT:BIPASS.0.DEC.V2.1.DEC.V2 | 0.16.1 |
INT:BIPASS.0.DEC.V3.1.DEC.V3 | 0.24.1 |
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 | 0.10.1 |
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 | 0.13.1 |
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 | 0.6.1 |
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 | 0.5.1 |
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 | 0.11.1 |
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 | 0.12.1 |
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 | 0.7.1 |
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 | 0.4.1 |
PULLUP_DEC0_N:ENABLE | 0.15.1 |
PULLUP_DEC0_S:ENABLE | 0.14.1 |
PULLUP_DEC1_N:ENABLE | 0.21.1 |
PULLUP_DEC1_S:ENABLE | 0.20.1 |
PULLUP_DEC2_N:ENABLE | 0.18.1 |
PULLUP_DEC2_S:ENABLE | 0.19.1 |
PULLUP_DEC3_N:ENABLE | 0.22.1 |
PULLUP_DEC3_S:ENABLE | 0.23.1 |
inverted | ~[0] |
Tile LLVC.IO.R
Cells: 2 IRIs: 0
Muxes
Destination | Sources |
---|---|
TCELL0:LONG.V0 | TCELL1:LONG.V0 |
TCELL0:LONG.V1 | TCELL1:LONG.V1 |
TCELL0:LONG.V2 | TCELL1:LONG.V2 |
TCELL0:LONG.V3 | TCELL1:LONG.V3 |
TCELL0:LONG.V4 | TCELL1:LONG.V4 |
TCELL0:LONG.V5 | TCELL1:LONG.V5 |
TCELL0:LONG.V6 | TCELL1:LONG.V6 |
TCELL0:LONG.V7 | TCELL1:LONG.V7 |
TCELL0:LONG.V8 | TCELL1:LONG.V8 |
TCELL0:LONG.V9 | TCELL1:LONG.V9 |
TCELL0:LONG.IO.V0 | TCELL1:LONG.IO.V0 |
TCELL0:LONG.IO.V1 | TCELL1:LONG.IO.V1 |
TCELL0:LONG.IO.V2 | TCELL1:LONG.IO.V2 |
TCELL0:LONG.IO.V3 | TCELL1:LONG.IO.V3 |
TCELL0:DEC.V0 | TCELL1:DEC.V0 |
TCELL0:DEC.V1 | TCELL1:DEC.V1 |
TCELL0:DEC.V2 | TCELL1:DEC.V2 |
TCELL0:DEC.V3 | TCELL1:DEC.V3 |
TCELL0:VCLK | TCELL0:QUAD.V0.4, TCELL1:SINGLE.V0, TCELL1:SINGLE.V1, TCELL1:SINGLE.V2, TCELL1:SINGLE.V4, TCELL1:SINGLE.V5, TCELL1:QUAD.V2.0, TCELL1:LONG.V0, TCELL1:LONG.V4, TCELL1:LONG.V6, TCELL1:GCLK2, TCELL1:GCLK5 |
TCELL1:LONG.V0 | TCELL0:LONG.V0 |
TCELL1:LONG.V1 | TCELL0:LONG.V1 |
TCELL1:LONG.V2 | TCELL0:LONG.V2 |
TCELL1:LONG.V3 | TCELL0:LONG.V3 |
TCELL1:LONG.V4 | TCELL0:LONG.V4 |
TCELL1:LONG.V5 | TCELL0:LONG.V5 |
TCELL1:LONG.V6 | TCELL0:LONG.V6 |
TCELL1:LONG.V7 | TCELL0:LONG.V7 |
TCELL1:LONG.V8 | TCELL0:LONG.V8 |
TCELL1:LONG.V9 | TCELL0:LONG.V9 |
TCELL1:LONG.IO.V0 | TCELL0:LONG.IO.V0 |
TCELL1:LONG.IO.V1 | TCELL0:LONG.IO.V1 |
TCELL1:LONG.IO.V2 | TCELL0:LONG.IO.V2 |
TCELL1:LONG.IO.V3 | TCELL0:LONG.IO.V3 |
TCELL1:DEC.V0 | TCELL0:DEC.V0 |
TCELL1:DEC.V1 | TCELL0:DEC.V1 |
TCELL1:DEC.V2 | TCELL0:DEC.V2 |
TCELL1:DEC.V3 | TCELL0:DEC.V3 |
TCELL1:VCLK | TCELL0:QUAD.V1.4, TCELL0:LONG.V1, TCELL0:LONG.V5, TCELL0:LONG.V8, TCELL0:GCLK1, TCELL0:GCLK4, TCELL1:SINGLE.V0, TCELL1:SINGLE.V1, TCELL1:SINGLE.V4, TCELL1:SINGLE.V5, TCELL1:SINGLE.V6, TCELL1:QUAD.V0.0 |
Bel PULLUP_DEC0_S
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:DEC.V0 |
Bel PULLUP_DEC1_S
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:DEC.V1 |
Bel PULLUP_DEC2_S
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:DEC.V2 |
Bel PULLUP_DEC3_S
Pin | Direction | Wires |
---|---|---|
O | output | TCELL0:DEC.V3 |
Bel PULLUP_DEC0_N
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:DEC.V0 |
Bel PULLUP_DEC1_N
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:DEC.V1 |
Bel PULLUP_DEC2_N
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:DEC.V2 |
Bel PULLUP_DEC3_N
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:DEC.V3 |
Bel wires
Wire | Pins |
---|---|
TCELL0:DEC.V0 | PULLUP_DEC0_S.O |
TCELL0:DEC.V1 | PULLUP_DEC1_S.O |
TCELL0:DEC.V2 | PULLUP_DEC2_S.O |
TCELL0:DEC.V3 | PULLUP_DEC3_S.O |
TCELL1:DEC.V0 | PULLUP_DEC0_N.O |
TCELL1:DEC.V1 | PULLUP_DEC1_N.O |
TCELL1:DEC.V2 | PULLUP_DEC2_N.O |
TCELL1:DEC.V3 | PULLUP_DEC3_N.O |
Bitstream
INT:BIPASS.0.DEC.V0.1.DEC.V0 | 0.4.0 |
---|---|
INT:BIPASS.0.DEC.V1.1.DEC.V1 | 0.7.0 |
INT:BIPASS.0.DEC.V2.1.DEC.V2 | 0.5.0 |
INT:BIPASS.0.DEC.V3.1.DEC.V3 | 0.35.1 |
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 | 0.30.1 |
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 | 0.13.1 |
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 | 0.23.1 |
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 | 0.18.1 |
INT:BUF.0.LONG.V0.1.LONG.V0 | 0.16.1 |
INT:BUF.0.LONG.V1.1.LONG.V1 | 0.34.1 |
INT:BUF.0.LONG.V2.1.LONG.V2 | 0.27.1 |
INT:BUF.0.LONG.V3.1.LONG.V3 | 0.20.1 |
INT:BUF.0.LONG.V4.1.LONG.V4 | 0.26.1 |
INT:BUF.0.LONG.V5.1.LONG.V5 | 0.9.1 |
INT:BUF.0.LONG.V6.1.LONG.V6 | 0.50.1 |
INT:BUF.0.LONG.V7.1.LONG.V7 | 0.43.1 |
INT:BUF.0.LONG.V8.1.LONG.V8 | 0.39.1 |
INT:BUF.0.LONG.V9.1.LONG.V9 | 0.38.1 |
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 | 0.29.1 |
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 | 0.14.1 |
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 | 0.24.1 |
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 | 0.17.1 |
INT:BUF.1.LONG.V0.0.LONG.V0 | 0.15.1 |
INT:BUF.1.LONG.V1.0.LONG.V1 | 0.32.1 |
INT:BUF.1.LONG.V2.0.LONG.V2 | 0.28.1 |
INT:BUF.1.LONG.V3.0.LONG.V3 | 0.19.1 |
INT:BUF.1.LONG.V4.0.LONG.V4 | 0.25.1 |
INT:BUF.1.LONG.V5.0.LONG.V5 | 0.10.1 |
INT:BUF.1.LONG.V6.0.LONG.V6 | 0.49.1 |
INT:BUF.1.LONG.V7.0.LONG.V7 | 0.44.1 |
INT:BUF.1.LONG.V8.0.LONG.V8 | 0.40.1 |
INT:BUF.1.LONG.V9.0.LONG.V9 | 0.37.1 |
MISC:TLC | 0.2.0 |
PULLUP_DEC0_N:ENABLE | 0.7.1 |
PULLUP_DEC0_S:ENABLE | 0.4.1 |
PULLUP_DEC1_N:ENABLE | 0.11.1 |
PULLUP_DEC1_S:ENABLE | 0.12.1 |
PULLUP_DEC2_N:ENABLE | 0.6.1 |
PULLUP_DEC2_S:ENABLE | 0.5.1 |
PULLUP_DEC3_N:ENABLE | 0.31.1 |
PULLUP_DEC3_S:ENABLE | 0.33.1 |
inverted | ~[0] |
INT:MUX.0.VCLK | 0.9.0 | 0.10.0 | 0.20.0 | 0.40.0 | 0.19.0 | 0.12.0 | 0.11.0 |
---|---|---|---|---|---|---|---|
0.QUAD.V0.4 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
1.LONG.V0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 |
1.QUAD.V2.0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
1.LONG.V6 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
1.SINGLE.V1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
1.SINGLE.V2 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
1.GCLK5 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.SINGLE.V4 | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.SINGLE.V5 | 1 | 0 | 0 | 1 | 1 | 1 | 1 |
1.LONG.V4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.GCLK2 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.SINGLE.V0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.1.VCLK | 0.24.0 | 0.23.0 | 0.28.0 | 0.39.0 | 0.34.0 | 0.33.0 | 0.27.0 |
---|---|---|---|---|---|---|---|
0.QUAD.V1.4 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
1.SINGLE.V1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 |
1.QUAD.V0.0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
0.LONG.V8 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
0.LONG.V1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
1.SINGLE.V4 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
0.LONG.V5 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.SINGLE.V6 | 0 | 1 | 1 | 1 | 1 | 0 | 1 |
0.GCLK1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 |
0.GCLK4 | 1 | 0 | 1 | 0 | 1 | 1 | 1 |
1.SINGLE.V5 | 1 | 0 | 1 | 1 | 0 | 1 | 1 |
1.SINGLE.V0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Tile LLVQ.CLB
Cells: 2 IRIs: 0
Muxes
Destination | Sources |
---|---|
TCELL0:QUAD.V1.4 | TCELL0:VCLK |
TCELL0:QUAD.V2.4 | TCELL1:VCLK |
TCELL0:LONG.V0 | TCELL1:LONG.V0 |
TCELL0:LONG.V1 | TCELL1:LONG.V1 |
TCELL0:LONG.V2 | TCELL1:LONG.V2 |
TCELL0:LONG.V3 | TCELL1:LONG.V3 |
TCELL0:LONG.V4 | TCELL1:LONG.V4 |
TCELL0:LONG.V5 | TCELL1:LONG.V5 |
TCELL0:LONG.V6 | TCELL1:LONG.V6 |
TCELL0:LONG.V7 | TCELL1:LONG.V7.EXCL |
TCELL0:LONG.V8 | TCELL1:LONG.V8 |
TCELL0:LONG.V9 | TCELL1:LONG.V9.EXCL |
TCELL0:GCLK0 | TCELL0:QUAD.V0.3, TCELL0:VCLK, TCELL1:SINGLE.V0, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK1 | TCELL0:QUAD.V0.4, TCELL0:VCLK, TCELL1:SINGLE.V1, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK2 | TCELL0:VCLK, TCELL1:SINGLE.V2, TCELL1:QUAD.V0.0, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK3 | TCELL0:QUAD.V1.4, TCELL0:VCLK, TCELL1:SINGLE.V3, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK4 | TCELL0:VCLK, TCELL1:SINGLE.V4, TCELL1:QUAD.V1.0, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK5 | TCELL0:QUAD.V2.3, TCELL0:VCLK, TCELL1:SINGLE.V5, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK6 | TCELL0:QUAD.V2.4, TCELL0:VCLK, TCELL1:SINGLE.V6, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK7 | TCELL0:VCLK, TCELL1:SINGLE.V7, TCELL1:QUAD.V2.0, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL1:SINGLE.V0 | TCELL0:VCLK |
TCELL1:SINGLE.V1 | TCELL1:VCLK |
TCELL1:SINGLE.V2 | TCELL0:VCLK |
TCELL1:SINGLE.V3 | TCELL1:VCLK |
TCELL1:SINGLE.V4 | TCELL0:VCLK |
TCELL1:SINGLE.V5 | TCELL1:VCLK |
TCELL1:SINGLE.V6 | TCELL0:VCLK |
TCELL1:SINGLE.V7 | TCELL1:VCLK |
TCELL1:QUAD.V0.0 | TCELL1:VCLK |
TCELL1:QUAD.V2.0 | TCELL0:VCLK |
TCELL1:LONG.V0 | TCELL0:LONG.V0 |
TCELL1:LONG.V1 | TCELL0:LONG.V1 |
TCELL1:LONG.V2 | TCELL0:LONG.V2 |
TCELL1:LONG.V3 | TCELL0:LONG.V3 |
TCELL1:LONG.V4 | TCELL0:LONG.V4 |
TCELL1:LONG.V5 | TCELL0:LONG.V5 |
TCELL1:LONG.V6 | TCELL0:LONG.V6 |
TCELL1:LONG.V7 | TCELL1:LONG.V7.EXCL |
TCELL1:LONG.V7.EXCL | TCELL0:LONG.V7, TCELL0:VCLK, TCELL1:LONG.V7 |
TCELL1:LONG.V8 | TCELL0:LONG.V8 |
TCELL1:LONG.V9 | TCELL1:LONG.V9.EXCL |
TCELL1:LONG.V9.EXCL | TCELL0:LONG.V9, TCELL1:LONG.V9, TCELL1:VCLK |
Bitstream
INT:BUF.0.LONG.V0.1.LONG.V0 | 0.4.1 |
---|---|
INT:BUF.0.LONG.V1.1.LONG.V1 | 0.20.1 |
INT:BUF.0.LONG.V2.1.LONG.V2 | 0.31.1 |
INT:BUF.0.LONG.V3.1.LONG.V3 | 0.9.1 |
INT:BUF.0.LONG.V4.1.LONG.V4 | 0.25.1 |
INT:BUF.0.LONG.V5.1.LONG.V5 | 0.15.1 |
INT:BUF.0.LONG.V6.1.LONG.V6 | 0.46.1 |
INT:BUF.0.LONG.V7.1.LONG.V7 | 0.45.1 |
INT:BUF.0.LONG.V8.1.LONG.V8 | 0.42.1 |
INT:BUF.1.LONG.V0.0.LONG.V0 | 0.4.0 |
INT:BUF.1.LONG.V1.0.LONG.V1 | 0.20.0 |
INT:BUF.1.LONG.V2.0.LONG.V2 | 0.31.0 |
INT:BUF.1.LONG.V3.0.LONG.V3 | 0.9.0 |
INT:BUF.1.LONG.V4.0.LONG.V4 | 0.25.0 |
INT:BUF.1.LONG.V5.0.LONG.V5 | 0.15.0 |
INT:BUF.1.LONG.V6.0.LONG.V6 | 0.46.0 |
INT:BUF.1.LONG.V8.0.LONG.V8 | 0.44.0 |
INT:BUF.1.LONG.V9.0.LONG.V9 | 0.37.1 |
INT:PASS.0.QUAD.V1.4.0.VCLK | 0.43.0 |
INT:PASS.0.QUAD.V2.4.1.VCLK | 0.42.0 |
INT:PASS.1.QUAD.V0.0.1.VCLK | 0.44.1 |
INT:PASS.1.QUAD.V2.0.0.VCLK | 0.22.0 |
INT:PASS.1.SINGLE.V0.0.VCLK | 0.17.0 |
INT:PASS.1.SINGLE.V1.1.VCLK | 0.26.1 |
INT:PASS.1.SINGLE.V2.0.VCLK | 0.14.0 |
INT:PASS.1.SINGLE.V3.1.VCLK | 0.27.0 |
INT:PASS.1.SINGLE.V4.0.VCLK | 0.38.0 |
INT:PASS.1.SINGLE.V5.1.VCLK | 0.28.0 |
INT:PASS.1.SINGLE.V6.0.VCLK | 0.37.0 |
INT:PASS.1.SINGLE.V7.1.VCLK | 0.32.0 |
inverted | ~[0] |
INT:MUX.0.GCLK0 | 0.28.1 | 0.30.1 | 0.30.0 | 0.29.1 | 0.29.0 | 0.26.0 | 0.27.1 |
---|---|---|---|---|---|---|---|
0.QUAD.V0.3 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.VCLK | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.SINGLE.V0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.VCLK | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK1 | 0.1.1 | 0.3.1 | 0.3.0 | 0.2.1 | 0.2.0 | 0.0.0 | 0.0.1 |
---|---|---|---|---|---|---|---|
0.QUAD.V0.4 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.VCLK | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.SINGLE.V1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.VCLK | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK2 | 0.11.1 | 0.13.0 | 0.12.1 | 0.13.1 | 0.12.0 | 0.10.0 | 0.10.1 |
---|---|---|---|---|---|---|---|
0.VCLK | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
1.SINGLE.V2 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.QUAD.V0.0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.VCLK | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H2 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H4 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK3 | 0.6.1 | 0.8.1 | 0.8.0 | 0.7.1 | 0.7.0 | 0.5.0 | 0.5.1 |
---|---|---|---|---|---|---|---|
0.QUAD.V1.4 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.VCLK | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.SINGLE.V3 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.VCLK | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK4 | 0.39.1 | 0.41.0 | 0.40.1 | 0.41.1 | 0.40.0 | 0.39.0 | 0.38.1 |
---|---|---|---|---|---|---|---|
0.VCLK | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
1.SINGLE.V4 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.QUAD.V1.0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.VCLK | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H2 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H4 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK5 | 0.33.1 | 0.35.1 | 0.35.0 | 0.34.1 | 0.34.0 | 0.33.0 | 0.32.1 |
---|---|---|---|---|---|---|---|
0.QUAD.V2.3 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.VCLK | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.SINGLE.V5 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.VCLK | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK6 | 0.22.1 | 0.24.1 | 0.24.0 | 0.23.1 | 0.23.0 | 0.21.0 | 0.21.1 |
---|---|---|---|---|---|---|---|
0.QUAD.V2.4 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.VCLK | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.SINGLE.V6 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.VCLK | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK7 | 0.17.1 | 0.19.0 | 0.18.1 | 0.19.1 | 0.18.0 | 0.16.0 | 0.16.1 |
---|---|---|---|---|---|---|---|
0.VCLK | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
1.SINGLE.V7 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.QUAD.V2.0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.VCLK | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H2 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H4 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.LONG.V9 | 0.36.0 | 0.36.1 |
---|---|---|
1.LONG.V9 | 0 | 0 |
1.VCLK | 0 | 1 |
NONE | 1 | 1 |
INT:MUX.1.LONG.V7 | 0.45.0 | 0.43.1 |
---|---|---|
0.LONG.V7 | 0 | 0 |
0.VCLK | 0 | 1 |
NONE | 1 | 1 |
Tile LLVQ.IO.L.B
Cells: 2 IRIs: 0
Muxes
Destination | Sources |
---|---|
TCELL0:IO.DOUBLE.0.W.1 | TCELL0:ECLK.V |
TCELL0:IO.DOUBLE.1.W.1 | TCELL0:ECLK.V |
TCELL0:IO.DOUBLE.1.W.2 | TCELL0:ECLK.V |
TCELL0:IO.DOUBLE.2.W.1 | TCELL0:ECLK.V |
TCELL0:IO.DOUBLE.3.W.2 | TCELL0:ECLK.V |
TCELL0:LONG.IO.V0 | TCELL1:LONG.IO.V0 |
TCELL0:LONG.IO.V1 | TCELL1:LONG.IO.V1 |
TCELL0:LONG.IO.V2 | TCELL1:LONG.IO.V2 |
TCELL0:LONG.IO.V3 | TCELL1:LONG.IO.V3 |
TCELL0:GCLK0 | TCELL0:IO.DOUBLE.0.W.1, TCELL0:IO.DOUBLE.2.W.1, TCELL0:BUFGE.V1, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7, TCELL1:OUT.BUFF |
TCELL0:GCLK1 | TCELL0:IO.DOUBLE.0.W.2, TCELL0:IO.DOUBLE.2.W.2, TCELL0:ECLK.V, TCELL0:BUFGE.V0, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK2 | TCELL0:IO.DOUBLE.1.W.1, TCELL0:IO.DOUBLE.3.W.1, TCELL0:ECLK.V, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7, TCELL1:OUT.BUFF |
TCELL0:GCLK3 | TCELL0:IO.DOUBLE.1.W.2, TCELL0:IO.DOUBLE.3.W.2, TCELL0:BUFGE.V0, TCELL0:BUFGE.V1, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL1:LONG.IO.V0 | TCELL0:LONG.IO.V0 |
TCELL1:LONG.IO.V1 | TCELL0:LONG.IO.V1 |
TCELL1:LONG.IO.V2 | TCELL0:LONG.IO.V2 |
TCELL1:LONG.IO.V3 | TCELL0:LONG.IO.V3 |
Bel BUFF
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:OUT.BUFF |
Bel wires
Wire | Pins |
---|---|
TCELL1:OUT.BUFF | BUFF.O |
Bitstream
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 | 0.7.1 |
---|---|
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 | 0.9.1 |
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 | 0.5.1 |
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 | 0.8.1 |
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 | 0.7.0 |
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 | 0.9.0 |
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 | 0.5.0 |
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 | 0.8.0 |
INT:PASS.0.IO.DOUBLE.0.W.1.0.ECLK.V | 0.15.0 |
INT:PASS.0.IO.DOUBLE.1.W.1.0.ECLK.V | 0.11.0 |
INT:PASS.0.IO.DOUBLE.1.W.2.0.ECLK.V | 0.19.0 |
INT:PASS.0.IO.DOUBLE.2.W.1.0.ECLK.V | 0.6.1 |
INT:PASS.0.IO.DOUBLE.3.W.2.0.ECLK.V | 0.23.0 |
inverted | ~[0] |
INT:MUX.0.GCLK0 | 0.16.1 | 0.18.1 | 0.17.1 | 0.18.0 | 0.17.0 | 0.16.0 | 0.15.1 |
---|---|---|---|---|---|---|---|
0.IO.DOUBLE.0.W.1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.IO.DOUBLE.2.W.1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
0.BUFGE.V1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.OUT.BUFF | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK1 | 0.24.1 | 0.26.1 | 0.25.1 | 0.26.0 | 0.25.0 | 0.24.0 | 0.23.1 |
---|---|---|---|---|---|---|---|
0.IO.DOUBLE.0.W.2 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.IO.DOUBLE.2.W.2 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
0.ECLK.V | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
0.BUFGE.V0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK2 | 0.12.1 | 0.13.1 | 0.14.1 | 0.14.0 | 0.13.0 | 0.12.0 | 0.11.1 |
---|---|---|---|---|---|---|---|
0.IO.DOUBLE.1.W.1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.IO.DOUBLE.3.W.1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
0.ECLK.V | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.OUT.BUFF | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H6 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H4 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK3 | 0.20.1 | 0.21.1 | 0.22.1 | 0.21.0 | 0.22.0 | 0.20.0 | 0.19.1 |
---|---|---|---|---|---|---|---|
0.IO.DOUBLE.1.W.2 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.IO.DOUBLE.3.W.2 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
0.BUFGE.V0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
0.BUFGE.V1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H6 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H4 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Tile LLVQ.IO.L.T
Cells: 2 IRIs: 0
Muxes
Destination | Sources |
---|---|
TCELL0:IO.DOUBLE.0.W.1 | TCELL1:ECLK.V |
TCELL0:IO.DOUBLE.1.W.1 | TCELL1:ECLK.V |
TCELL0:IO.DOUBLE.1.W.2 | TCELL1:ECLK.V |
TCELL0:IO.DOUBLE.2.W.1 | TCELL1:ECLK.V |
TCELL0:IO.DOUBLE.3.W.2 | TCELL1:ECLK.V |
TCELL0:LONG.IO.V0 | TCELL1:LONG.IO.V0 |
TCELL0:LONG.IO.V1 | TCELL1:LONG.IO.V1 |
TCELL0:LONG.IO.V2 | TCELL1:LONG.IO.V2 |
TCELL0:LONG.IO.V3 | TCELL1:LONG.IO.V3 |
TCELL0:GCLK0 | TCELL0:IO.DOUBLE.0.W.1, TCELL0:IO.DOUBLE.2.W.1, TCELL0:BUFGE.V0, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7, TCELL1:OUT.BUFF |
TCELL0:GCLK1 | TCELL0:IO.DOUBLE.0.W.2, TCELL0:IO.DOUBLE.2.W.2, TCELL0:BUFGE.V1, TCELL1:ECLK.V, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK2 | TCELL0:IO.DOUBLE.1.W.1, TCELL0:IO.DOUBLE.3.W.1, TCELL1:ECLK.V, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7, TCELL1:OUT.BUFF |
TCELL0:GCLK3 | TCELL0:IO.DOUBLE.1.W.2, TCELL0:IO.DOUBLE.3.W.2, TCELL0:BUFGE.V0, TCELL0:BUFGE.V1, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL1:LONG.IO.V0 | TCELL0:LONG.IO.V0 |
TCELL1:LONG.IO.V1 | TCELL0:LONG.IO.V1 |
TCELL1:LONG.IO.V2 | TCELL0:LONG.IO.V2 |
TCELL1:LONG.IO.V3 | TCELL0:LONG.IO.V3 |
Bel BUFF
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:OUT.BUFF |
Bel wires
Wire | Pins |
---|---|
TCELL1:OUT.BUFF | BUFF.O |
Bitstream
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 | 0.7.1 |
---|---|
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 | 0.9.1 |
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 | 0.5.1 |
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 | 0.8.1 |
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 | 0.7.0 |
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 | 0.9.0 |
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 | 0.5.0 |
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 | 0.8.0 |
INT:PASS.0.IO.DOUBLE.0.W.1.1.ECLK.V | 0.15.0 |
INT:PASS.0.IO.DOUBLE.1.W.1.1.ECLK.V | 0.11.0 |
INT:PASS.0.IO.DOUBLE.1.W.2.1.ECLK.V | 0.19.0 |
INT:PASS.0.IO.DOUBLE.2.W.1.1.ECLK.V | 0.6.1 |
INT:PASS.0.IO.DOUBLE.3.W.2.1.ECLK.V | 0.23.0 |
inverted | ~[0] |
INT:MUX.0.GCLK0 | 0.16.1 | 0.18.1 | 0.17.1 | 0.18.0 | 0.17.0 | 0.16.0 | 0.15.1 |
---|---|---|---|---|---|---|---|
0.IO.DOUBLE.0.W.1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.IO.DOUBLE.2.W.1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
0.BUFGE.V0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.OUT.BUFF | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK1 | 0.24.1 | 0.26.1 | 0.25.1 | 0.25.0 | 0.26.0 | 0.24.0 | 0.23.1 |
---|---|---|---|---|---|---|---|
0.IO.DOUBLE.0.W.2 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.IO.DOUBLE.2.W.2 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
0.BUFGE.V1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.ECLK.V | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK2 | 0.12.1 | 0.13.1 | 0.14.1 | 0.14.0 | 0.13.0 | 0.12.0 | 0.11.1 |
---|---|---|---|---|---|---|---|
0.IO.DOUBLE.1.W.1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.IO.DOUBLE.3.W.1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.ECLK.V | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.OUT.BUFF | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H6 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H4 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK3 | 0.20.1 | 0.21.1 | 0.22.1 | 0.22.0 | 0.21.0 | 0.20.0 | 0.19.1 |
---|---|---|---|---|---|---|---|
0.IO.DOUBLE.1.W.2 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.IO.DOUBLE.3.W.2 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
0.BUFGE.V0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
0.BUFGE.V1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H6 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H4 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Tile LLVQ.IO.R.B
Cells: 2 IRIs: 0
Muxes
Destination | Sources |
---|---|
TCELL0:IO.DOUBLE.0.E.1 | TCELL0:ECLK.V |
TCELL0:IO.DOUBLE.1.E.0 | TCELL0:ECLK.V |
TCELL0:IO.DOUBLE.1.E.1 | TCELL0:ECLK.V |
TCELL0:IO.DOUBLE.2.E.1 | TCELL0:ECLK.V |
TCELL0:IO.DOUBLE.3.E.0 | TCELL0:ECLK.V |
TCELL0:QUAD.V1.4 | TCELL0:VCLK |
TCELL0:QUAD.V2.4 | TCELL1:VCLK |
TCELL0:LONG.V0 | TCELL1:LONG.V0 |
TCELL0:LONG.V1 | TCELL1:LONG.V1 |
TCELL0:LONG.V2 | TCELL1:LONG.V2 |
TCELL0:LONG.V3 | TCELL1:LONG.V3 |
TCELL0:LONG.V4 | TCELL1:LONG.V4 |
TCELL0:LONG.V5 | TCELL1:LONG.V5 |
TCELL0:LONG.V6 | TCELL1:LONG.V6 |
TCELL0:LONG.V7 | TCELL1:LONG.V7.EXCL |
TCELL0:LONG.V8 | TCELL1:LONG.V8 |
TCELL0:LONG.V9 | TCELL1:LONG.V9.EXCL |
TCELL0:LONG.IO.V0 | TCELL1:LONG.IO.V0 |
TCELL0:LONG.IO.V1 | TCELL1:LONG.IO.V1 |
TCELL0:LONG.IO.V2 | TCELL1:LONG.IO.V2 |
TCELL0:LONG.IO.V3 | TCELL1:LONG.IO.V3 |
TCELL0:GCLK0 | TCELL0:IO.DOUBLE.0.E.1, TCELL0:IO.DOUBLE.2.E.1, TCELL0:BUFGE.V1, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7, TCELL1:OUT.BUFF |
TCELL0:GCLK1 | TCELL0:IO.DOUBLE.0.E.0, TCELL0:IO.DOUBLE.2.E.0, TCELL0:ECLK.V, TCELL0:BUFGE.V0, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK2 | TCELL0:IO.DOUBLE.1.E.1, TCELL0:IO.DOUBLE.3.E.1, TCELL0:ECLK.V, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7, TCELL1:OUT.BUFF |
TCELL0:GCLK3 | TCELL0:IO.DOUBLE.1.E.0, TCELL0:IO.DOUBLE.3.E.0, TCELL0:BUFGE.V0, TCELL0:BUFGE.V1, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK4 | TCELL0:VCLK, TCELL1:SINGLE.V4, TCELL1:QUAD.V1.0, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK5 | TCELL0:QUAD.V2.3, TCELL0:VCLK, TCELL1:SINGLE.V5, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK6 | TCELL0:QUAD.V2.4, TCELL0:VCLK, TCELL1:SINGLE.V6, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK7 | TCELL0:VCLK, TCELL1:SINGLE.V7, TCELL1:QUAD.V2.0, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL1:SINGLE.V0 | TCELL0:VCLK |
TCELL1:SINGLE.V1 | TCELL1:VCLK |
TCELL1:SINGLE.V2 | TCELL0:VCLK |
TCELL1:SINGLE.V3 | TCELL1:VCLK |
TCELL1:SINGLE.V4 | TCELL0:VCLK |
TCELL1:SINGLE.V5 | TCELL1:VCLK |
TCELL1:SINGLE.V6 | TCELL0:VCLK |
TCELL1:SINGLE.V7 | TCELL1:VCLK |
TCELL1:QUAD.V0.0 | TCELL1:VCLK |
TCELL1:QUAD.V2.0 | TCELL0:VCLK |
TCELL1:LONG.V0 | TCELL0:LONG.V0 |
TCELL1:LONG.V1 | TCELL0:LONG.V1 |
TCELL1:LONG.V2 | TCELL0:LONG.V2 |
TCELL1:LONG.V3 | TCELL0:LONG.V3 |
TCELL1:LONG.V4 | TCELL0:LONG.V4 |
TCELL1:LONG.V5 | TCELL0:LONG.V5 |
TCELL1:LONG.V6 | TCELL0:LONG.V6 |
TCELL1:LONG.V7 | TCELL1:LONG.V7.EXCL |
TCELL1:LONG.V7.EXCL | TCELL0:LONG.V7, TCELL0:VCLK, TCELL1:LONG.V7 |
TCELL1:LONG.V8 | TCELL0:LONG.V8 |
TCELL1:LONG.V9 | TCELL1:LONG.V9.EXCL |
TCELL1:LONG.V9.EXCL | TCELL0:LONG.V9, TCELL1:LONG.V9, TCELL1:VCLK |
TCELL1:LONG.IO.V0 | TCELL0:LONG.IO.V0 |
TCELL1:LONG.IO.V1 | TCELL0:LONG.IO.V1 |
TCELL1:LONG.IO.V2 | TCELL0:LONG.IO.V2 |
TCELL1:LONG.IO.V3 | TCELL0:LONG.IO.V3 |
Bel BUFF
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:OUT.BUFF |
Bel wires
Wire | Pins |
---|---|
TCELL1:OUT.BUFF | BUFF.O |
Bitstream
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 | 0.20.1 |
---|---|
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 | 0.16.1 |
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 | 0.18.1 |
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 | 0.17.1 |
INT:BUF.0.LONG.V0.1.LONG.V0 | 0.31.1 |
INT:BUF.0.LONG.V1.1.LONG.V1 | 0.27.1 |
INT:BUF.0.LONG.V2.1.LONG.V2 | 0.33.1 |
INT:BUF.0.LONG.V3.1.LONG.V3 | 0.34.1 |
INT:BUF.0.LONG.V4.1.LONG.V4 | 0.29.1 |
INT:BUF.0.LONG.V5.1.LONG.V5 | 0.35.1 |
INT:BUF.0.LONG.V6.1.LONG.V6 | 0.26.1 |
INT:BUF.0.LONG.V7.1.LONG.V7 | 0.25.1 |
INT:BUF.0.LONG.V8.1.LONG.V8 | 0.23.1 |
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 | 0.20.0 |
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 | 0.16.0 |
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 | 0.18.0 |
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 | 0.17.0 |
INT:BUF.1.LONG.V0.0.LONG.V0 | 0.31.0 |
INT:BUF.1.LONG.V1.0.LONG.V1 | 0.27.0 |
INT:BUF.1.LONG.V2.0.LONG.V2 | 0.33.0 |
INT:BUF.1.LONG.V3.0.LONG.V3 | 0.34.0 |
INT:BUF.1.LONG.V4.0.LONG.V4 | 0.29.0 |
INT:BUF.1.LONG.V5.0.LONG.V5 | 0.35.0 |
INT:BUF.1.LONG.V6.0.LONG.V6 | 0.26.0 |
INT:BUF.1.LONG.V8.0.LONG.V8 | 0.23.0 |
INT:BUF.1.LONG.V9.0.LONG.V9 | 0.22.1 |
INT:PASS.0.IO.DOUBLE.0.E.1.0.ECLK.V | 0.19.0 |
INT:PASS.0.IO.DOUBLE.1.E.0.0.ECLK.V | 0.9.0 |
INT:PASS.0.IO.DOUBLE.1.E.1.0.ECLK.V | 0.5.0 |
INT:PASS.0.IO.DOUBLE.2.E.1.0.ECLK.V | 0.1.0 |
INT:PASS.0.IO.DOUBLE.3.E.0.0.ECLK.V | 0.19.1 |
INT:PASS.0.QUAD.V1.4.0.VCLK | 0.30.1 |
INT:PASS.0.QUAD.V2.4.1.VCLK | 0.32.0 |
INT:PASS.1.QUAD.V0.0.1.VCLK | 0.30.0 |
INT:PASS.1.QUAD.V2.0.0.VCLK | 0.32.1 |
INT:PASS.1.SINGLE.V0.0.VCLK | 0.24.0 |
INT:PASS.1.SINGLE.V1.1.VCLK | 0.21.0 |
INT:PASS.1.SINGLE.V2.0.VCLK | 0.28.0 |
INT:PASS.1.SINGLE.V3.1.VCLK | 0.28.1 |
INT:PASS.1.SINGLE.V4.0.VCLK | 0.48.0 |
INT:PASS.1.SINGLE.V5.1.VCLK | 0.45.0 |
INT:PASS.1.SINGLE.V6.0.VCLK | 0.41.0 |
INT:PASS.1.SINGLE.V7.1.VCLK | 0.36.0 |
inverted | ~[0] |
INT:MUX.0.GCLK0 | 0.9.1 | 0.11.1 | 0.10.1 | 0.11.0 | 0.10.0 | 0.8.0 | 0.8.1 |
---|---|---|---|---|---|---|---|
0.IO.DOUBLE.0.E.1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.IO.DOUBLE.2.E.1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
0.BUFGE.V1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.OUT.BUFF | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK1 | 0.5.1 | 0.7.1 | 0.6.1 | 0.7.0 | 0.6.0 | 0.4.0 | 0.4.1 |
---|---|---|---|---|---|---|---|
0.IO.DOUBLE.0.E.0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.IO.DOUBLE.2.E.0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
0.ECLK.V | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
0.BUFGE.V0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK2 | 0.13.1 | 0.14.1 | 0.15.1 | 0.15.0 | 0.14.0 | 0.12.0 | 0.12.1 |
---|---|---|---|---|---|---|---|
0.IO.DOUBLE.1.E.1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.IO.DOUBLE.3.E.1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
0.ECLK.V | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.OUT.BUFF | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H6 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H4 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK3 | 0.1.1 | 0.2.1 | 0.3.1 | 0.2.0 | 0.3.0 | 0.0.0 | 0.0.1 |
---|---|---|---|---|---|---|---|
0.IO.DOUBLE.1.E.0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.IO.DOUBLE.3.E.0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
0.BUFGE.V0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
0.BUFGE.V1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H6 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H4 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK4 | 0.49.1 | 0.51.0 | 0.50.1 | 0.51.1 | 0.50.0 | 0.49.0 | 0.48.1 |
---|---|---|---|---|---|---|---|
0.VCLK | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
1.SINGLE.V4 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.QUAD.V1.0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.VCLK | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H2 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H4 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK5 | 0.45.1 | 0.47.1 | 0.47.0 | 0.46.1 | 0.46.0 | 0.44.0 | 0.44.1 |
---|---|---|---|---|---|---|---|
0.QUAD.V2.3 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.VCLK | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.SINGLE.V5 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.VCLK | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK6 | 0.41.1 | 0.43.1 | 0.43.0 | 0.42.1 | 0.42.0 | 0.40.0 | 0.40.1 |
---|---|---|---|---|---|---|---|
0.QUAD.V2.4 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.VCLK | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.SINGLE.V6 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.VCLK | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK7 | 0.37.1 | 0.39.0 | 0.38.1 | 0.39.1 | 0.38.0 | 0.37.0 | 0.36.1 |
---|---|---|---|---|---|---|---|
0.VCLK | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
1.SINGLE.V7 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.QUAD.V2.0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.VCLK | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H2 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H4 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.LONG.V9 | 0.22.0 | 0.21.1 |
---|---|---|
1.LONG.V9 | 0 | 0 |
1.VCLK | 0 | 1 |
NONE | 1 | 1 |
INT:MUX.1.LONG.V7 | 0.25.0 | 0.24.1 |
---|---|---|
0.LONG.V7 | 0 | 0 |
0.VCLK | 0 | 1 |
NONE | 1 | 1 |
Tile LLVQ.IO.R.T
Cells: 2 IRIs: 0
Muxes
Destination | Sources |
---|---|
TCELL0:IO.DOUBLE.0.E.1 | TCELL1:ECLK.V |
TCELL0:IO.DOUBLE.1.E.0 | TCELL1:ECLK.V |
TCELL0:IO.DOUBLE.1.E.1 | TCELL1:ECLK.V |
TCELL0:IO.DOUBLE.2.E.1 | TCELL1:ECLK.V |
TCELL0:IO.DOUBLE.3.E.0 | TCELL1:ECLK.V |
TCELL0:QUAD.V1.4 | TCELL0:VCLK |
TCELL0:QUAD.V2.4 | TCELL1:VCLK |
TCELL0:LONG.V0 | TCELL1:LONG.V0 |
TCELL0:LONG.V1 | TCELL1:LONG.V1 |
TCELL0:LONG.V2 | TCELL1:LONG.V2 |
TCELL0:LONG.V3 | TCELL1:LONG.V3 |
TCELL0:LONG.V4 | TCELL1:LONG.V4 |
TCELL0:LONG.V5 | TCELL1:LONG.V5 |
TCELL0:LONG.V6 | TCELL1:LONG.V6 |
TCELL0:LONG.V7 | TCELL1:LONG.V7.EXCL |
TCELL0:LONG.V8 | TCELL1:LONG.V8 |
TCELL0:LONG.V9 | TCELL1:LONG.V9.EXCL |
TCELL0:LONG.IO.V0 | TCELL1:LONG.IO.V0 |
TCELL0:LONG.IO.V1 | TCELL1:LONG.IO.V1 |
TCELL0:LONG.IO.V2 | TCELL1:LONG.IO.V2 |
TCELL0:LONG.IO.V3 | TCELL1:LONG.IO.V3 |
TCELL0:GCLK0 | TCELL0:IO.DOUBLE.0.E.1, TCELL0:IO.DOUBLE.2.E.1, TCELL0:BUFGE.V0, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7, TCELL1:OUT.BUFF |
TCELL0:GCLK1 | TCELL0:IO.DOUBLE.0.E.0, TCELL0:IO.DOUBLE.2.E.0, TCELL0:BUFGE.V1, TCELL1:ECLK.V, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK2 | TCELL0:IO.DOUBLE.1.E.1, TCELL0:IO.DOUBLE.3.E.1, TCELL1:ECLK.V, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7, TCELL1:OUT.BUFF |
TCELL0:GCLK3 | TCELL0:IO.DOUBLE.1.E.0, TCELL0:IO.DOUBLE.3.E.0, TCELL0:BUFGE.V0, TCELL0:BUFGE.V1, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK4 | TCELL0:VCLK, TCELL1:SINGLE.V4, TCELL1:QUAD.V1.0, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK5 | TCELL0:QUAD.V2.3, TCELL0:VCLK, TCELL1:SINGLE.V5, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK6 | TCELL0:QUAD.V2.4, TCELL0:VCLK, TCELL1:SINGLE.V6, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL0:GCLK7 | TCELL0:VCLK, TCELL1:SINGLE.V7, TCELL1:QUAD.V2.0, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7 |
TCELL1:SINGLE.V0 | TCELL0:VCLK |
TCELL1:SINGLE.V1 | TCELL1:VCLK |
TCELL1:SINGLE.V2 | TCELL0:VCLK |
TCELL1:SINGLE.V3 | TCELL1:VCLK |
TCELL1:SINGLE.V4 | TCELL0:VCLK |
TCELL1:SINGLE.V5 | TCELL1:VCLK |
TCELL1:SINGLE.V6 | TCELL0:VCLK |
TCELL1:SINGLE.V7 | TCELL1:VCLK |
TCELL1:QUAD.V0.0 | TCELL1:VCLK |
TCELL1:QUAD.V2.0 | TCELL0:VCLK |
TCELL1:LONG.V0 | TCELL0:LONG.V0 |
TCELL1:LONG.V1 | TCELL0:LONG.V1 |
TCELL1:LONG.V2 | TCELL0:LONG.V2 |
TCELL1:LONG.V3 | TCELL0:LONG.V3 |
TCELL1:LONG.V4 | TCELL0:LONG.V4 |
TCELL1:LONG.V5 | TCELL0:LONG.V5 |
TCELL1:LONG.V6 | TCELL0:LONG.V6 |
TCELL1:LONG.V7 | TCELL1:LONG.V7.EXCL |
TCELL1:LONG.V7.EXCL | TCELL0:LONG.V7, TCELL0:VCLK, TCELL1:LONG.V7 |
TCELL1:LONG.V8 | TCELL0:LONG.V8 |
TCELL1:LONG.V9 | TCELL1:LONG.V9.EXCL |
TCELL1:LONG.V9.EXCL | TCELL0:LONG.V9, TCELL1:LONG.V9, TCELL1:VCLK |
TCELL1:LONG.IO.V0 | TCELL0:LONG.IO.V0 |
TCELL1:LONG.IO.V1 | TCELL0:LONG.IO.V1 |
TCELL1:LONG.IO.V2 | TCELL0:LONG.IO.V2 |
TCELL1:LONG.IO.V3 | TCELL0:LONG.IO.V3 |
Bel BUFF
Pin | Direction | Wires |
---|---|---|
O | output | TCELL1:OUT.BUFF |
Bel wires
Wire | Pins |
---|---|
TCELL1:OUT.BUFF | BUFF.O |
Bitstream
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 | 0.20.1 |
---|---|
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 | 0.16.1 |
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 | 0.18.1 |
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 | 0.17.1 |
INT:BUF.0.LONG.V0.1.LONG.V0 | 0.31.1 |
INT:BUF.0.LONG.V1.1.LONG.V1 | 0.27.1 |
INT:BUF.0.LONG.V2.1.LONG.V2 | 0.33.1 |
INT:BUF.0.LONG.V3.1.LONG.V3 | 0.34.1 |
INT:BUF.0.LONG.V4.1.LONG.V4 | 0.29.1 |
INT:BUF.0.LONG.V5.1.LONG.V5 | 0.35.1 |
INT:BUF.0.LONG.V6.1.LONG.V6 | 0.26.1 |
INT:BUF.0.LONG.V7.1.LONG.V7 | 0.25.1 |
INT:BUF.0.LONG.V8.1.LONG.V8 | 0.23.1 |
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 | 0.20.0 |
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 | 0.16.0 |
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 | 0.18.0 |
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 | 0.17.0 |
INT:BUF.1.LONG.V0.0.LONG.V0 | 0.31.0 |
INT:BUF.1.LONG.V1.0.LONG.V1 | 0.27.0 |
INT:BUF.1.LONG.V2.0.LONG.V2 | 0.33.0 |
INT:BUF.1.LONG.V3.0.LONG.V3 | 0.34.0 |
INT:BUF.1.LONG.V4.0.LONG.V4 | 0.29.0 |
INT:BUF.1.LONG.V5.0.LONG.V5 | 0.35.0 |
INT:BUF.1.LONG.V6.0.LONG.V6 | 0.26.0 |
INT:BUF.1.LONG.V8.0.LONG.V8 | 0.23.0 |
INT:BUF.1.LONG.V9.0.LONG.V9 | 0.22.1 |
INT:PASS.0.IO.DOUBLE.0.E.1.1.ECLK.V | 0.19.0 |
INT:PASS.0.IO.DOUBLE.1.E.0.1.ECLK.V | 0.9.0 |
INT:PASS.0.IO.DOUBLE.1.E.1.1.ECLK.V | 0.5.0 |
INT:PASS.0.IO.DOUBLE.2.E.1.1.ECLK.V | 0.1.0 |
INT:PASS.0.IO.DOUBLE.3.E.0.1.ECLK.V | 0.19.1 |
INT:PASS.0.QUAD.V1.4.0.VCLK | 0.30.1 |
INT:PASS.0.QUAD.V2.4.1.VCLK | 0.32.0 |
INT:PASS.1.QUAD.V0.0.1.VCLK | 0.30.0 |
INT:PASS.1.QUAD.V2.0.0.VCLK | 0.32.1 |
INT:PASS.1.SINGLE.V0.0.VCLK | 0.24.0 |
INT:PASS.1.SINGLE.V1.1.VCLK | 0.21.0 |
INT:PASS.1.SINGLE.V2.0.VCLK | 0.28.0 |
INT:PASS.1.SINGLE.V3.1.VCLK | 0.28.1 |
INT:PASS.1.SINGLE.V4.0.VCLK | 0.48.0 |
INT:PASS.1.SINGLE.V5.1.VCLK | 0.45.0 |
INT:PASS.1.SINGLE.V6.0.VCLK | 0.41.0 |
INT:PASS.1.SINGLE.V7.1.VCLK | 0.36.0 |
inverted | ~[0] |
INT:MUX.0.GCLK0 | 0.9.1 | 0.11.1 | 0.10.1 | 0.11.0 | 0.10.0 | 0.8.0 | 0.8.1 |
---|---|---|---|---|---|---|---|
0.IO.DOUBLE.0.E.1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.IO.DOUBLE.2.E.1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
0.BUFGE.V0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.OUT.BUFF | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK1 | 0.5.1 | 0.7.1 | 0.6.1 | 0.6.0 | 0.7.0 | 0.4.0 | 0.4.1 |
---|---|---|---|---|---|---|---|
0.IO.DOUBLE.0.E.0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.IO.DOUBLE.2.E.0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
0.BUFGE.V1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.ECLK.V | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK2 | 0.13.1 | 0.14.1 | 0.15.1 | 0.15.0 | 0.14.0 | 0.12.0 | 0.12.1 |
---|---|---|---|---|---|---|---|
0.IO.DOUBLE.1.E.1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.IO.DOUBLE.3.E.1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.ECLK.V | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.OUT.BUFF | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H6 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H4 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK3 | 0.1.1 | 0.2.1 | 0.3.1 | 0.3.0 | 0.2.0 | 0.0.0 | 0.0.1 |
---|---|---|---|---|---|---|---|
0.IO.DOUBLE.1.E.0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.IO.DOUBLE.3.E.0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
0.BUFGE.V0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
0.BUFGE.V1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H6 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H4 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK4 | 0.49.1 | 0.51.0 | 0.50.1 | 0.51.1 | 0.50.0 | 0.49.0 | 0.48.1 |
---|---|---|---|---|---|---|---|
0.VCLK | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
1.SINGLE.V4 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.QUAD.V1.0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.VCLK | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H2 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H4 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK5 | 0.45.1 | 0.47.1 | 0.47.0 | 0.46.1 | 0.46.0 | 0.44.0 | 0.44.1 |
---|---|---|---|---|---|---|---|
0.QUAD.V2.3 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.VCLK | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.SINGLE.V5 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.VCLK | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK6 | 0.41.1 | 0.43.1 | 0.43.0 | 0.42.1 | 0.42.0 | 0.40.0 | 0.40.1 |
---|---|---|---|---|---|---|---|
0.QUAD.V2.4 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
0.VCLK | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.SINGLE.V6 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.VCLK | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H4 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H2 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.GCLK7 | 0.37.1 | 0.39.0 | 0.38.1 | 0.39.1 | 0.38.0 | 0.37.0 | 0.36.1 |
---|---|---|---|---|---|---|---|
0.VCLK | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
1.SINGLE.V7 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
1.QUAD.V2.0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |
1.VCLK | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1.BUFGLS.H2 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1.BUFGLS.H3 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
1.BUFGLS.H6 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
1.BUFGLS.H7 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
1.BUFGLS.H4 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
1.BUFGLS.H5 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1.BUFGLS.H0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
1.BUFGLS.H1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
NONE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
INT:MUX.0.LONG.V9 | 0.22.0 | 0.21.1 |
---|---|---|
1.LONG.V9 | 0 | 0 |
1.VCLK | 0 | 1 |
NONE | 1 | 1 |
INT:MUX.1.LONG.V7 | 0.25.0 | 0.24.1 |
---|---|---|
0.LONG.V7 | 0 | 0 |
0.VCLK | 0 | 1 |
NONE | 1 | 1 |
Tile CLKC
Cells: 0 IRIs: 0
Bel CLKC
Pin | Direction | Wires |
---|
Tile CLKQC
Cells: 1 IRIs: 0
Bel CLKQC
Pin | Direction | Wires |
---|---|---|
O.LL.H | output | BUFGLS.H2 |
O.LL.V | output | BUFGLS.H1 |
O.LR.H | output | BUFGLS.H3 |
O.LR.V | output | BUFGLS.H4 |
O.UL.H | output | BUFGLS.H7 |
O.UL.V | output | BUFGLS.H0 |
O.UR.H | output | BUFGLS.H6 |
O.UR.V | output | BUFGLS.H5 |
Bel wires
Wire | Pins |
---|---|
BUFGLS.H0 | CLKQC.O.UL.V |
BUFGLS.H1 | CLKQC.O.LL.V |
BUFGLS.H2 | CLKQC.O.LL.H |
BUFGLS.H3 | CLKQC.O.LR.H |
BUFGLS.H4 | CLKQC.O.LR.V |
BUFGLS.H5 | CLKQC.O.UR.V |
BUFGLS.H6 | CLKQC.O.UR.H |
BUFGLS.H7 | CLKQC.O.UL.H |