Splitters

Tile LLHC.CLB

Cells: 2

Bel PULLUP_TBUF0_W

xc4000ex LLHC.CLB bel PULLUP_TBUF0_W
Pin	Direction	Wires
O	output	TCELL0:LONG.H2

Bel PULLUP_TBUF1_W

xc4000ex LLHC.CLB bel PULLUP_TBUF1_W
Pin	Direction	Wires
O	output	TCELL0:LONG.H3

Bel PULLUP_TBUF0_E

xc4000ex LLHC.CLB bel PULLUP_TBUF0_E
Pin	Direction	Wires
O	output	TCELL1:LONG.H2

Bel PULLUP_TBUF1_E

xc4000ex LLHC.CLB bel PULLUP_TBUF1_E
Pin	Direction	Wires
O	output	TCELL1:LONG.H3

Bel TBUF_SPLITTER0

xc4000ex LLHC.CLB bel TBUF_SPLITTER0
Pin	Direction	Wires
L	in-out	TCELL0:LONG.H2
R	in-out	TCELL1:LONG.H2

Bel TBUF_SPLITTER1

xc4000ex LLHC.CLB bel TBUF_SPLITTER1
Pin	Direction	Wires
L	in-out	TCELL0:LONG.H3
R	in-out	TCELL1:LONG.H3

Bel LLH

Switchbox LLH

xc4000ex LLHC.CLB switchbox LLH
Destination	Source	Kind
TCELL0_LONG.H0	TCELL1_LONG.H0	buffer
TCELL0_LONG.H1	TCELL1_LONG.H1	buffer
TCELL0_LONG.H4	TCELL1_LONG.H4	buffer
TCELL0_LONG.H5	TCELL1_LONG.H5	buffer
TCELL1_LONG.H0	TCELL0_LONG.H0	buffer
TCELL1_LONG.H1	TCELL0_LONG.H1	buffer
TCELL1_LONG.H4	TCELL0_LONG.H4	buffer
TCELL1_LONG.H5	TCELL0_LONG.H5	buffer

Bel wires

xc4000ex LLHC.CLB bel wires
Wire	Pins
TCELL0:LONG.H2	PULLUP_TBUF0_W.O, TBUF_SPLITTER0.L
TCELL0:LONG.H3	PULLUP_TBUF1_W.O, TBUF_SPLITTER1.L
TCELL1:LONG.H2	PULLUP_TBUF0_E.O, TBUF_SPLITTER0.R
TCELL1:LONG.H3	PULLUP_TBUF1_E.O, TBUF_SPLITTER1.R

Bitstream

xc4000ex LLHC.CLB bittile 0
Bit	Frame
Bit	1	0
11	-	~TBUF_SPLITTER1:BUF_W
10	~PULLUP_TBUF1_W:ENABLE	~TBUF_SPLITTER1:BUF_E
9	-	-
8	-	-
7	~PULLUP_TBUF1_E:ENABLE	-
6	-	-
5	~TBUF_SPLITTER1:PASS	-
4	-	-
3	-	~LLH:BUF.0.LONG.H5.1.LONG.H5
2	-	~LLH:BUF.1.LONG.H5.0.LONG.H5
1	-	~LLH:BUF.0.LONG.H4.1.LONG.H4
0	-	~LLH:BUF.1.LONG.H4.0.LONG.H4

xc4000ex LLHC.CLB bittile 1
Bit	Frame
Bit	1	0
9	~TBUF_SPLITTER0:BUF_W	~PULLUP_TBUF0_E:ENABLE
8	~TBUF_SPLITTER0:BUF_E	-
7	-	~LLH:BUF.1.LONG.H1.0.LONG.H1
6	~TBUF_SPLITTER0:PASS	~LLH:BUF.0.LONG.H0.1.LONG.H0
5	-	~LLH:BUF.1.LONG.H0.0.LONG.H0
4	~PULLUP_TBUF0_W:ENABLE	~LLH:BUF.0.LONG.H1.1.LONG.H1
3	-	-
2	-	-
1	-	-
0	-	-

LLH:BUF.0.LONG.H0.1.LONG.H0	1.0.6
LLH:BUF.0.LONG.H1.1.LONG.H1	1.0.4
LLH:BUF.0.LONG.H4.1.LONG.H4	0.0.1
LLH:BUF.0.LONG.H5.1.LONG.H5	0.0.3
LLH:BUF.1.LONG.H0.0.LONG.H0	1.0.5
LLH:BUF.1.LONG.H1.0.LONG.H1	1.0.7
LLH:BUF.1.LONG.H4.0.LONG.H4	0.0.0
LLH:BUF.1.LONG.H5.0.LONG.H5	0.0.2
PULLUP_TBUF0_E:ENABLE	1.0.9
PULLUP_TBUF0_W:ENABLE	1.1.4
PULLUP_TBUF1_E:ENABLE	0.1.7
PULLUP_TBUF1_W:ENABLE	0.1.10
TBUF_SPLITTER0:BUF_E	1.1.8
TBUF_SPLITTER0:BUF_W	1.1.9
TBUF_SPLITTER0:PASS	1.1.6
TBUF_SPLITTER1:BUF_E	0.0.10
TBUF_SPLITTER1:BUF_W	0.0.11
TBUF_SPLITTER1:PASS	0.1.5
inverted	~[0]

Tile LLHC.CLB.B

Cells: 2

Bel PULLUP_TBUF0_W

xc4000ex LLHC.CLB.B bel PULLUP_TBUF0_W
Pin	Direction	Wires
O	output	TCELL0:LONG.H2

Bel PULLUP_TBUF1_W

xc4000ex LLHC.CLB.B bel PULLUP_TBUF1_W
Pin	Direction	Wires
O	output	TCELL0:LONG.H3

Bel PULLUP_TBUF0_E

xc4000ex LLHC.CLB.B bel PULLUP_TBUF0_E
Pin	Direction	Wires
O	output	TCELL1:LONG.H2

Bel PULLUP_TBUF1_E

xc4000ex LLHC.CLB.B bel PULLUP_TBUF1_E
Pin	Direction	Wires
O	output	TCELL1:LONG.H3

Bel TBUF_SPLITTER0

xc4000ex LLHC.CLB.B bel TBUF_SPLITTER0
Pin	Direction	Wires
L	in-out	TCELL0:LONG.H2
R	in-out	TCELL1:LONG.H2

Bel TBUF_SPLITTER1

xc4000ex LLHC.CLB.B bel TBUF_SPLITTER1
Pin	Direction	Wires
L	in-out	TCELL0:LONG.H3
R	in-out	TCELL1:LONG.H3

Bel LLH

Switchbox LLH

xc4000ex LLHC.CLB.B switchbox LLH
Destination	Source	Kind
TCELL0_LONG.H0	TCELL1_LONG.H0	buffer
TCELL0_LONG.H1	TCELL1_LONG.H1	buffer
TCELL0_LONG.H4	TCELL1_LONG.H4	buffer
TCELL0_LONG.H5	TCELL1_LONG.H5	buffer
TCELL1_LONG.H0	TCELL0_LONG.H0	buffer
TCELL1_LONG.H1	TCELL0_LONG.H1	buffer
TCELL1_LONG.H4	TCELL0_LONG.H4	buffer
TCELL1_LONG.H5	TCELL0_LONG.H5	buffer

Bel wires

xc4000ex LLHC.CLB.B bel wires
Wire	Pins
TCELL0:LONG.H2	PULLUP_TBUF0_W.O, TBUF_SPLITTER0.L
TCELL0:LONG.H3	PULLUP_TBUF1_W.O, TBUF_SPLITTER1.L
TCELL1:LONG.H2	PULLUP_TBUF0_E.O, TBUF_SPLITTER0.R
TCELL1:LONG.H3	PULLUP_TBUF1_E.O, TBUF_SPLITTER1.R

Bitstream

xc4000ex LLHC.CLB.B bittile 0
Bit	Frame
Bit	1	0
11	-	~TBUF_SPLITTER1:BUF_W
10	~PULLUP_TBUF1_W:ENABLE	~TBUF_SPLITTER1:BUF_E
9	-	-
8	-	-
7	~PULLUP_TBUF1_E:ENABLE	-
6	-	-
5	~TBUF_SPLITTER1:PASS	-
4	-	-
3	-	~LLH:BUF.0.LONG.H5.1.LONG.H5
2	-	~LLH:BUF.1.LONG.H5.0.LONG.H5
1	-	~LLH:BUF.0.LONG.H4.1.LONG.H4
0	-	~LLH:BUF.1.LONG.H4.0.LONG.H4

xc4000ex LLHC.CLB.B bittile 1
Bit	Frame
Bit	1	0
15	~LLH:BUF.1.LONG.H0.0.LONG.H0	~LLH:BUF.0.LONG.H0.1.LONG.H0
14	~LLH:BUF.1.LONG.H1.0.LONG.H1	~TBUF_SPLITTER0:PASS
13	-	~LLH:BUF.0.LONG.H1.1.LONG.H1
12	-	~PULLUP_TBUF0_E:ENABLE
11	~TBUF_SPLITTER0:BUF_E	~TBUF_SPLITTER0:BUF_W
10	-	-
9	-	-
8	-	-
7	-	-
6	-	-
5	-	-
4	-	-
3	-	-
2	-	-
1	-	-
0	-	-

xc4000ex LLHC.CLB.B bittile 2
Bit	Frame
Bit	0
12	~PULLUP_TBUF0_W:ENABLE
11	-
10	-
9	-
8	-
7	-
6	-
5	-
4	-
3	-
2	-
1	-
0	-

LLH:BUF.0.LONG.H0.1.LONG.H0	1.0.15
LLH:BUF.0.LONG.H1.1.LONG.H1	1.0.13
LLH:BUF.0.LONG.H4.1.LONG.H4	0.0.1
LLH:BUF.0.LONG.H5.1.LONG.H5	0.0.3
LLH:BUF.1.LONG.H0.0.LONG.H0	1.1.15
LLH:BUF.1.LONG.H1.0.LONG.H1	1.1.14
LLH:BUF.1.LONG.H4.0.LONG.H4	0.0.0
LLH:BUF.1.LONG.H5.0.LONG.H5	0.0.2
PULLUP_TBUF0_E:ENABLE	1.0.12
PULLUP_TBUF0_W:ENABLE	2.0.12
PULLUP_TBUF1_E:ENABLE	0.1.7
PULLUP_TBUF1_W:ENABLE	0.1.10
TBUF_SPLITTER0:BUF_E	1.1.11
TBUF_SPLITTER0:BUF_W	1.0.11
TBUF_SPLITTER0:PASS	1.0.14
TBUF_SPLITTER1:BUF_E	0.0.10
TBUF_SPLITTER1:BUF_W	0.0.11
TBUF_SPLITTER1:PASS	0.1.5
inverted	~[0]

Tile LLHC.IO.B

Cells: 2

Bel PULLUP_DEC0_W

xc4000ex LLHC.IO.B bel PULLUP_DEC0_W
Pin	Direction	Wires
O	output	TCELL0:DEC.H0

Bel PULLUP_DEC1_W

xc4000ex LLHC.IO.B bel PULLUP_DEC1_W
Pin	Direction	Wires
O	output	TCELL0:DEC.H1

Bel PULLUP_DEC2_W

xc4000ex LLHC.IO.B bel PULLUP_DEC2_W
Pin	Direction	Wires
O	output	TCELL0:DEC.H2

Bel PULLUP_DEC3_W

xc4000ex LLHC.IO.B bel PULLUP_DEC3_W
Pin	Direction	Wires
O	output	TCELL0:DEC.H3

Bel PULLUP_DEC0_E

xc4000ex LLHC.IO.B bel PULLUP_DEC0_E
Pin	Direction	Wires
O	output	TCELL1:DEC.H0

Bel PULLUP_DEC1_E

xc4000ex LLHC.IO.B bel PULLUP_DEC1_E
Pin	Direction	Wires
O	output	TCELL1:DEC.H1

Bel PULLUP_DEC2_E

xc4000ex LLHC.IO.B bel PULLUP_DEC2_E
Pin	Direction	Wires
O	output	TCELL1:DEC.H2

Bel PULLUP_DEC3_E

xc4000ex LLHC.IO.B bel PULLUP_DEC3_E
Pin	Direction	Wires
O	output	TCELL1:DEC.H3

Bel LLH

Switchbox LLH

xc4000ex LLHC.IO.B switchbox LLH
Destination	Source	Kind
TCELL0_LONG.H3	TCELL1_LONG.H3	buffer
TCELL0_LONG.H4	TCELL1_LONG.H4	buffer
TCELL0_LONG.H5	TCELL1_LONG.H5	buffer
TCELL0_LONG.IO.H0	TCELL1_LONG.IO.H0	buffer
TCELL0_LONG.IO.H1	TCELL1_LONG.IO.H1	buffer
TCELL0_LONG.IO.H2	TCELL1_LONG.IO.H2	buffer
TCELL0_LONG.IO.H3	TCELL1_LONG.IO.H3	buffer
TCELL0_DEC.H0	TCELL1_DEC.H0	bidirectional pass transistor
TCELL0_DEC.H1	TCELL1_DEC.H1	bidirectional pass transistor
TCELL0_DEC.H2	TCELL1_DEC.H2	bidirectional pass transistor
TCELL0_DEC.H3	TCELL1_DEC.H3	bidirectional pass transistor
TCELL1_LONG.H3	TCELL0_LONG.H3	buffer
TCELL1_LONG.H4	TCELL0_LONG.H4	buffer
TCELL1_LONG.H5	TCELL0_LONG.H5	buffer
TCELL1_LONG.IO.H0	TCELL0_LONG.IO.H0	buffer
TCELL1_LONG.IO.H1	TCELL0_LONG.IO.H1	buffer
TCELL1_LONG.IO.H2	TCELL0_LONG.IO.H2	buffer
TCELL1_LONG.IO.H3	TCELL0_LONG.IO.H3	buffer
TCELL1_DEC.H0	TCELL0_DEC.H0	bidirectional pass transistor
TCELL1_DEC.H1	TCELL0_DEC.H1	bidirectional pass transistor
TCELL1_DEC.H2	TCELL0_DEC.H2	bidirectional pass transistor
TCELL1_DEC.H3	TCELL0_DEC.H3	bidirectional pass transistor

Bel wires

xc4000ex LLHC.IO.B bel wires
Wire	Pins
TCELL0:DEC.H0	PULLUP_DEC0_W.O
TCELL0:DEC.H1	PULLUP_DEC1_W.O
TCELL0:DEC.H2	PULLUP_DEC2_W.O
TCELL0:DEC.H3	PULLUP_DEC3_W.O
TCELL1:DEC.H0	PULLUP_DEC0_E.O
TCELL1:DEC.H1	PULLUP_DEC1_E.O
TCELL1:DEC.H2	PULLUP_DEC2_E.O
TCELL1:DEC.H3	PULLUP_DEC3_E.O

Bitstream

xc4000ex LLHC.IO.B bittile 0
Bit	Frame
Bit	1	0
13	~PULLUP_DEC1_E:ENABLE	-
12	~PULLUP_DEC2_W:ENABLE	-
11	-	-
10	~PULLUP_DEC2_E:ENABLE	~LLH:BIPASS.0.DEC.H1.1.DEC.H1
9	~LLH:BUF.1.LONG.H3.0.LONG.H3	-
8	-	~LLH:BUF.0.LONG.H3.1.LONG.H3
7	~LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1	~LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0
6	~LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0	-
5	~LLH:BUF.1.LONG.H4.0.LONG.H4	~LLH:BUF.0.LONG.H4.1.LONG.H4
4	~LLH:BIPASS.0.DEC.H3.1.DEC.H3	~LLH:BIPASS.0.DEC.H2.1.DEC.H2
3	~LLH:BUF.1.LONG.H5.0.LONG.H5	~LLH:BUF.0.LONG.H5.1.LONG.H5
2	~LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2	-
1	~LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3	~PULLUP_DEC3_E:ENABLE
0	~PULLUP_DEC3_W:ENABLE	~LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3

xc4000ex LLHC.IO.B bittile 1
Bit	Frame
Bit	0
15	~PULLUP_DEC1_W:ENABLE
14	~PULLUP_DEC0_E:ENABLE
13	~PULLUP_DEC0_W:ENABLE
12	-
11	-
10	~LLH:BIPASS.0.DEC.H0.1.DEC.H0
9	-
8	-
7	-
6	-
5	-
4	~LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1
3	-
2	~LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2
1	-
0	-

LLH:BIPASS.0.DEC.H0.1.DEC.H0	1.0.10
LLH:BIPASS.0.DEC.H1.1.DEC.H1	0.0.10
LLH:BIPASS.0.DEC.H2.1.DEC.H2	0.0.4
LLH:BIPASS.0.DEC.H3.1.DEC.H3	0.1.4
LLH:BUF.0.LONG.H3.1.LONG.H3	0.0.8
LLH:BUF.0.LONG.H4.1.LONG.H4	0.0.5
LLH:BUF.0.LONG.H5.1.LONG.H5	0.0.3
LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0	0.0.7
LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1	1.0.4
LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2	1.0.2
LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3	0.0.0
LLH:BUF.1.LONG.H3.0.LONG.H3	0.1.9
LLH:BUF.1.LONG.H4.0.LONG.H4	0.1.5
LLH:BUF.1.LONG.H5.0.LONG.H5	0.1.3
LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0	0.1.6
LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1	0.1.7
LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2	0.1.2
LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3	0.1.1
PULLUP_DEC0_E:ENABLE	1.0.14
PULLUP_DEC0_W:ENABLE	1.0.13
PULLUP_DEC1_E:ENABLE	0.1.13
PULLUP_DEC1_W:ENABLE	1.0.15
PULLUP_DEC2_E:ENABLE	0.1.10
PULLUP_DEC2_W:ENABLE	0.1.12
PULLUP_DEC3_E:ENABLE	0.0.1
PULLUP_DEC3_W:ENABLE	0.1.0
inverted	~[0]

Tile LLHC.IO.T

Cells: 2

Bel PULLUP_DEC0_W

xc4000ex LLHC.IO.T bel PULLUP_DEC0_W
Pin	Direction	Wires
O	output	TCELL0:DEC.H0

Bel PULLUP_DEC1_W

xc4000ex LLHC.IO.T bel PULLUP_DEC1_W
Pin	Direction	Wires
O	output	TCELL0:DEC.H1

Bel PULLUP_DEC2_W

xc4000ex LLHC.IO.T bel PULLUP_DEC2_W
Pin	Direction	Wires
O	output	TCELL0:DEC.H2

Bel PULLUP_DEC3_W

xc4000ex LLHC.IO.T bel PULLUP_DEC3_W
Pin	Direction	Wires
O	output	TCELL0:DEC.H3

Bel PULLUP_DEC0_E

xc4000ex LLHC.IO.T bel PULLUP_DEC0_E
Pin	Direction	Wires
O	output	TCELL1:DEC.H0

Bel PULLUP_DEC1_E

xc4000ex LLHC.IO.T bel PULLUP_DEC1_E
Pin	Direction	Wires
O	output	TCELL1:DEC.H1

Bel PULLUP_DEC2_E

xc4000ex LLHC.IO.T bel PULLUP_DEC2_E
Pin	Direction	Wires
O	output	TCELL1:DEC.H2

Bel PULLUP_DEC3_E

xc4000ex LLHC.IO.T bel PULLUP_DEC3_E
Pin	Direction	Wires
O	output	TCELL1:DEC.H3

Bel LLH

Switchbox LLH

xc4000ex LLHC.IO.T switchbox LLH
Destination	Source	Kind
TCELL0_LONG.H0	TCELL1_LONG.H0	buffer
TCELL0_LONG.H1	TCELL1_LONG.H1	buffer
TCELL0_LONG.H2	TCELL1_LONG.H2	buffer
TCELL0_LONG.IO.H0	TCELL1_LONG.IO.H0	buffer
TCELL0_LONG.IO.H1	TCELL1_LONG.IO.H1	buffer
TCELL0_LONG.IO.H2	TCELL1_LONG.IO.H2	buffer
TCELL0_LONG.IO.H3	TCELL1_LONG.IO.H3	buffer
TCELL0_DEC.H0	TCELL1_DEC.H0	bidirectional pass transistor
TCELL0_DEC.H1	TCELL1_DEC.H1	bidirectional pass transistor
TCELL0_DEC.H2	TCELL1_DEC.H2	bidirectional pass transistor
TCELL0_DEC.H3	TCELL1_DEC.H3	bidirectional pass transistor
TCELL1_LONG.H0	TCELL0_LONG.H0	buffer
TCELL1_LONG.H1	TCELL0_LONG.H1	buffer
TCELL1_LONG.H2	TCELL0_LONG.H2	buffer
TCELL1_LONG.IO.H0	TCELL0_LONG.IO.H0	buffer
TCELL1_LONG.IO.H1	TCELL0_LONG.IO.H1	buffer
TCELL1_LONG.IO.H2	TCELL0_LONG.IO.H2	buffer
TCELL1_LONG.IO.H3	TCELL0_LONG.IO.H3	buffer
TCELL1_DEC.H0	TCELL0_DEC.H0	bidirectional pass transistor
TCELL1_DEC.H1	TCELL0_DEC.H1	bidirectional pass transistor
TCELL1_DEC.H2	TCELL0_DEC.H2	bidirectional pass transistor
TCELL1_DEC.H3	TCELL0_DEC.H3	bidirectional pass transistor

Bel wires

xc4000ex LLHC.IO.T bel wires
Wire	Pins
TCELL0:DEC.H0	PULLUP_DEC0_W.O
TCELL0:DEC.H1	PULLUP_DEC1_W.O
TCELL0:DEC.H2	PULLUP_DEC2_W.O
TCELL0:DEC.H3	PULLUP_DEC3_W.O
TCELL1:DEC.H0	PULLUP_DEC0_E.O
TCELL1:DEC.H1	PULLUP_DEC1_E.O
TCELL1:DEC.H2	PULLUP_DEC2_E.O
TCELL1:DEC.H3	PULLUP_DEC3_E.O

Bitstream

xc4000ex LLHC.IO.T bittile 0
Bit	Frame
Bit	1	0
6	~PULLUP_DEC1_E:ENABLE	~PULLUP_DEC1_W:ENABLE
5	~LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3	~LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3
4	~LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2	~LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2
3	~PULLUP_DEC2_W:ENABLE	~PULLUP_DEC2_E:ENABLE
2	~PULLUP_DEC0_E:ENABLE	~PULLUP_DEC0_W:ENABLE
1	~LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1	~LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1
0	~PULLUP_DEC3_W:ENABLE	~PULLUP_DEC3_E:ENABLE

xc4000ex LLHC.IO.T bittile 1
Bit	Frame
Bit	1	0
9	~LLH:BUF.0.LONG.H2.1.LONG.H2	-
8	~LLH:BUF.1.LONG.H2.0.LONG.H2	-
7	-	~LLH:BUF.1.LONG.H1.0.LONG.H1
6	-	~LLH:BUF.0.LONG.H0.1.LONG.H0
5	-	~LLH:BUF.1.LONG.H0.0.LONG.H0
4	-	~LLH:BUF.0.LONG.H1.1.LONG.H1
3	-	-
2	-	-
1	-	-
0	-	-

xc4000ex LLHC.IO.T bittile 2
Bit	Frame
Bit	0
7	~LLH:BIPASS.0.DEC.H2.1.DEC.H2
6	-
5	~LLH:BIPASS.0.DEC.H1.1.DEC.H1
4	-
3	~LLH:BIPASS.0.DEC.H0.1.DEC.H0
2	~LLH:BIPASS.0.DEC.H3.1.DEC.H3
1	~LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0
0	~LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0

LLH:BIPASS.0.DEC.H0.1.DEC.H0	2.0.3
LLH:BIPASS.0.DEC.H1.1.DEC.H1	2.0.5
LLH:BIPASS.0.DEC.H2.1.DEC.H2	2.0.7
LLH:BIPASS.0.DEC.H3.1.DEC.H3	2.0.2
LLH:BUF.0.LONG.H0.1.LONG.H0	1.0.6
LLH:BUF.0.LONG.H1.1.LONG.H1	1.0.4
LLH:BUF.0.LONG.H2.1.LONG.H2	1.1.9
LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0	2.0.0
LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1	0.1.1
LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2	0.1.4
LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3	0.1.5
LLH:BUF.1.LONG.H0.0.LONG.H0	1.0.5
LLH:BUF.1.LONG.H1.0.LONG.H1	1.0.7
LLH:BUF.1.LONG.H2.0.LONG.H2	1.1.8
LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0	2.0.1
LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1	0.0.1
LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2	0.0.4
LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3	0.0.5
PULLUP_DEC0_E:ENABLE	0.1.2
PULLUP_DEC0_W:ENABLE	0.0.2
PULLUP_DEC1_E:ENABLE	0.1.6
PULLUP_DEC1_W:ENABLE	0.0.6
PULLUP_DEC2_E:ENABLE	0.0.3
PULLUP_DEC2_W:ENABLE	0.1.3
PULLUP_DEC3_E:ENABLE	0.0.0
PULLUP_DEC3_W:ENABLE	0.1.0
inverted	~[0]

Tile LLHQ.CLB

Cells: 2

Bel PULLUP_TBUF0_W

xc4000ex LLHQ.CLB bel PULLUP_TBUF0_W
Pin	Direction	Wires
O	output	TCELL0:LONG.H2

Bel PULLUP_TBUF1_W

xc4000ex LLHQ.CLB bel PULLUP_TBUF1_W
Pin	Direction	Wires
O	output	TCELL0:LONG.H3

Bel PULLUP_TBUF0_E

xc4000ex LLHQ.CLB bel PULLUP_TBUF0_E
Pin	Direction	Wires
O	output	TCELL0:LONG.H2

Bel PULLUP_TBUF1_E

xc4000ex LLHQ.CLB bel PULLUP_TBUF1_E
Pin	Direction	Wires
O	output	TCELL0:LONG.H3

Bel LLH

Switchbox LLH

xc4000ex LLHQ.CLB switchbox LLH
Destination	Source	Kind
TCELL0_LONG.H0	TCELL1_LONG.H0	buffer
TCELL0_LONG.H1	TCELL1_LONG.H1	buffer
TCELL0_LONG.H4	TCELL1_LONG.H4	buffer
TCELL0_LONG.H5	TCELL1_LONG.H5	buffer
TCELL1_LONG.H0	TCELL0_LONG.H0	buffer
TCELL1_LONG.H1	TCELL0_LONG.H1	buffer
TCELL1_LONG.H4	TCELL0_LONG.H4	buffer
TCELL1_LONG.H5	TCELL0_LONG.H5	buffer

Bel wires

xc4000ex LLHQ.CLB bel wires
Wire	Pins
TCELL0:LONG.H2	PULLUP_TBUF0_W.O, PULLUP_TBUF0_E.O
TCELL0:LONG.H3	PULLUP_TBUF1_W.O, PULLUP_TBUF1_E.O

Bitstream

xc4000ex LLHQ.CLB bittile 0
Bit	Frame
Bit	0
5	~PULLUP_TBUF1_E:ENABLE
4	~PULLUP_TBUF1_W:ENABLE
3	~LLH:BUF.0.LONG.H4.1.LONG.H4
2	~LLH:BUF.1.LONG.H4.0.LONG.H4
1	~LLH:BUF.1.LONG.H5.0.LONG.H5
0	~LLH:BUF.0.LONG.H5.1.LONG.H5

xc4000ex LLHQ.CLB bittile 1
Bit	Frame
Bit	0
11	~LLH:BUF.1.LONG.H0.0.LONG.H0
10	~LLH:BUF.0.LONG.H0.1.LONG.H0
9	~LLH:BUF.1.LONG.H1.0.LONG.H1
8	~LLH:BUF.0.LONG.H1.1.LONG.H1
7	~PULLUP_TBUF0_E:ENABLE
6	~PULLUP_TBUF0_W:ENABLE
5	-
4	-
3	-
2	-
1	-
0	-

LLH:BUF.0.LONG.H0.1.LONG.H0	1.0.10
LLH:BUF.0.LONG.H1.1.LONG.H1	1.0.8
LLH:BUF.0.LONG.H4.1.LONG.H4	0.0.3
LLH:BUF.0.LONG.H5.1.LONG.H5	0.0.0
LLH:BUF.1.LONG.H0.0.LONG.H0	1.0.11
LLH:BUF.1.LONG.H1.0.LONG.H1	1.0.9
LLH:BUF.1.LONG.H4.0.LONG.H4	0.0.2
LLH:BUF.1.LONG.H5.0.LONG.H5	0.0.1
PULLUP_TBUF0_E:ENABLE	1.0.7
PULLUP_TBUF0_W:ENABLE	1.0.6
PULLUP_TBUF1_E:ENABLE	0.0.5
PULLUP_TBUF1_W:ENABLE	0.0.4
inverted	~[0]

Tile LLHQ.CLB.B

Cells: 2

Bel PULLUP_TBUF0_W

xc4000ex LLHQ.CLB.B bel PULLUP_TBUF0_W
Pin	Direction	Wires
O	output	TCELL0:LONG.H2

Bel PULLUP_TBUF1_W

xc4000ex LLHQ.CLB.B bel PULLUP_TBUF1_W
Pin	Direction	Wires
O	output	TCELL0:LONG.H3

Bel PULLUP_TBUF0_E

xc4000ex LLHQ.CLB.B bel PULLUP_TBUF0_E
Pin	Direction	Wires
O	output	TCELL0:LONG.H2

Bel PULLUP_TBUF1_E

xc4000ex LLHQ.CLB.B bel PULLUP_TBUF1_E
Pin	Direction	Wires
O	output	TCELL0:LONG.H3

Bel LLH

Switchbox LLH

xc4000ex LLHQ.CLB.B switchbox LLH
Destination	Source	Kind
TCELL0_LONG.H0	TCELL1_LONG.H0	buffer
TCELL0_LONG.H1	TCELL1_LONG.H1	buffer
TCELL0_LONG.H4	TCELL1_LONG.H4	buffer
TCELL0_LONG.H5	TCELL1_LONG.H5	buffer
TCELL1_LONG.H0	TCELL0_LONG.H0	buffer
TCELL1_LONG.H1	TCELL0_LONG.H1	buffer
TCELL1_LONG.H4	TCELL0_LONG.H4	buffer
TCELL1_LONG.H5	TCELL0_LONG.H5	buffer

Bel wires

xc4000ex LLHQ.CLB.B bel wires
Wire	Pins
TCELL0:LONG.H2	PULLUP_TBUF0_W.O, PULLUP_TBUF0_E.O
TCELL0:LONG.H3	PULLUP_TBUF1_W.O, PULLUP_TBUF1_E.O

Bitstream

xc4000ex LLHQ.CLB.B bittile 0
Bit	Frame
Bit	0
5	~PULLUP_TBUF1_E:ENABLE
4	~PULLUP_TBUF1_W:ENABLE
3	~LLH:BUF.0.LONG.H4.1.LONG.H4
2	~LLH:BUF.1.LONG.H4.0.LONG.H4
1	~LLH:BUF.1.LONG.H5.0.LONG.H5
0	~LLH:BUF.0.LONG.H5.1.LONG.H5

xc4000ex LLHQ.CLB.B bittile 1
Bit	Frame
Bit

xc4000ex LLHQ.CLB.B bittile 2
Bit	Frame
Bit	0
15	~PULLUP_TBUF0_E:ENABLE
14	~PULLUP_TBUF0_W:ENABLE
13	~LLH:BUF.0.LONG.H0.1.LONG.H0
12	~LLH:BUF.1.LONG.H0.0.LONG.H0
11	~LLH:BUF.0.LONG.H1.1.LONG.H1
10	~LLH:BUF.1.LONG.H1.0.LONG.H1
9	-
8	-
7	-
6	-
5	-
4	-
3	-
2	-
1	-
0	-

LLH:BUF.0.LONG.H0.1.LONG.H0	2.0.13
LLH:BUF.0.LONG.H1.1.LONG.H1	2.0.11
LLH:BUF.0.LONG.H4.1.LONG.H4	0.0.3
LLH:BUF.0.LONG.H5.1.LONG.H5	0.0.0
LLH:BUF.1.LONG.H0.0.LONG.H0	2.0.12
LLH:BUF.1.LONG.H1.0.LONG.H1	2.0.10
LLH:BUF.1.LONG.H4.0.LONG.H4	0.0.2
LLH:BUF.1.LONG.H5.0.LONG.H5	0.0.1
PULLUP_TBUF0_E:ENABLE	2.0.15
PULLUP_TBUF0_W:ENABLE	2.0.14
PULLUP_TBUF1_E:ENABLE	0.0.5
PULLUP_TBUF1_W:ENABLE	0.0.4
inverted	~[0]

Tile LLHQ.CLB.T

Cells: 2

Bel PULLUP_TBUF0_W

xc4000ex LLHQ.CLB.T bel PULLUP_TBUF0_W
Pin	Direction	Wires
O	output	TCELL0:LONG.H2

Bel PULLUP_TBUF1_W

xc4000ex LLHQ.CLB.T bel PULLUP_TBUF1_W
Pin	Direction	Wires
O	output	TCELL0:LONG.H3

Bel PULLUP_TBUF0_E

xc4000ex LLHQ.CLB.T bel PULLUP_TBUF0_E
Pin	Direction	Wires
O	output	TCELL0:LONG.H2

Bel PULLUP_TBUF1_E

xc4000ex LLHQ.CLB.T bel PULLUP_TBUF1_E
Pin	Direction	Wires
O	output	TCELL0:LONG.H3

Bel LLH

Switchbox LLH

xc4000ex LLHQ.CLB.T switchbox LLH
Destination	Source	Kind
TCELL0_LONG.H0	TCELL1_LONG.H0	buffer
TCELL0_LONG.H1	TCELL1_LONG.H1	buffer
TCELL0_LONG.H4	TCELL1_LONG.H4	buffer
TCELL0_LONG.H5	TCELL1_LONG.H5	buffer
TCELL1_LONG.H0	TCELL0_LONG.H0	buffer
TCELL1_LONG.H1	TCELL0_LONG.H1	buffer
TCELL1_LONG.H4	TCELL0_LONG.H4	buffer
TCELL1_LONG.H5	TCELL0_LONG.H5	buffer

Bel wires

xc4000ex LLHQ.CLB.T bel wires
Wire	Pins
TCELL0:LONG.H2	PULLUP_TBUF0_W.O, PULLUP_TBUF0_E.O
TCELL0:LONG.H3	PULLUP_TBUF1_W.O, PULLUP_TBUF1_E.O

Bitstream

xc4000ex LLHQ.CLB.T bittile 0
Bit	Frame
Bit	0
5	~PULLUP_TBUF1_W:ENABLE
4	~PULLUP_TBUF1_E:ENABLE
3	~LLH:BUF.0.LONG.H4.1.LONG.H4
2	~LLH:BUF.1.LONG.H4.0.LONG.H4
1	~LLH:BUF.1.LONG.H5.0.LONG.H5
0	~LLH:BUF.0.LONG.H5.1.LONG.H5

xc4000ex LLHQ.CLB.T bittile 1
Bit	Frame
Bit	0
11	~LLH:BUF.1.LONG.H0.0.LONG.H0
10	~LLH:BUF.0.LONG.H0.1.LONG.H0
9	~LLH:BUF.1.LONG.H1.0.LONG.H1
8	~LLH:BUF.0.LONG.H1.1.LONG.H1
7	~PULLUP_TBUF0_E:ENABLE
6	~PULLUP_TBUF0_W:ENABLE
5	-
4	-
3	-
2	-
1	-
0	-

LLH:BUF.0.LONG.H0.1.LONG.H0	1.0.10
LLH:BUF.0.LONG.H1.1.LONG.H1	1.0.8
LLH:BUF.0.LONG.H4.1.LONG.H4	0.0.3
LLH:BUF.0.LONG.H5.1.LONG.H5	0.0.0
LLH:BUF.1.LONG.H0.0.LONG.H0	1.0.11
LLH:BUF.1.LONG.H1.0.LONG.H1	1.0.9
LLH:BUF.1.LONG.H4.0.LONG.H4	0.0.2
LLH:BUF.1.LONG.H5.0.LONG.H5	0.0.1
PULLUP_TBUF0_E:ENABLE	1.0.7
PULLUP_TBUF0_W:ENABLE	1.0.6
PULLUP_TBUF1_E:ENABLE	0.0.4
PULLUP_TBUF1_W:ENABLE	0.0.5
inverted	~[0]

Tile LLHQ.IO.B

Cells: 2

Bel LLH

Switchbox LLH

xc4000ex LLHQ.IO.B switchbox LLH
Destination	Source	Kind
TCELL0_LONG.H3	TCELL1_LONG.H3	buffer
TCELL0_LONG.H4	TCELL1_LONG.H4	buffer
TCELL0_LONG.H5	TCELL1_LONG.H5	buffer
TCELL0_LONG.IO.H0	TCELL1_LONG.IO.H0	buffer
TCELL0_LONG.IO.H1	TCELL1_LONG.IO.H1	buffer
TCELL0_LONG.IO.H2	TCELL1_LONG.IO.H2	buffer
TCELL0_LONG.IO.H3	TCELL1_LONG.IO.H3	buffer
TCELL1_LONG.H3	TCELL0_LONG.H3	buffer
TCELL1_LONG.H4	TCELL0_LONG.H4	buffer
TCELL1_LONG.H5	TCELL0_LONG.H5	buffer
TCELL1_LONG.IO.H0	TCELL0_LONG.IO.H0	buffer
TCELL1_LONG.IO.H1	TCELL0_LONG.IO.H1	buffer
TCELL1_LONG.IO.H2	TCELL0_LONG.IO.H2	buffer
TCELL1_LONG.IO.H3	TCELL0_LONG.IO.H3	buffer

Bitstream

xc4000ex LLHQ.IO.B bittile 0
Bit	Frame
Bit	0
11	~LLH:BUF.0.LONG.H3.1.LONG.H3
10	~LLH:BUF.1.LONG.H3.0.LONG.H3
9	-
8	-
7	~LLH:BUF.1.LONG.H5.0.LONG.H5
6	~LLH:BUF.0.LONG.H5.1.LONG.H5
5	~LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1
4	~LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1
3	-
2	-
1	~LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3
0	~LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3

xc4000ex LLHQ.IO.B bittile 1
Bit	Frame
Bit	0
7	~LLH:BUF.1.LONG.H4.0.LONG.H4
6	~LLH:BUF.0.LONG.H4.1.LONG.H4
5	~LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0
4	~LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0
3	-
2	-
1	~LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2
0	~LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2

LLH:BUF.0.LONG.H3.1.LONG.H3	0.0.11
LLH:BUF.0.LONG.H4.1.LONG.H4	1.0.6
LLH:BUF.0.LONG.H5.1.LONG.H5	0.0.6
LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0	1.0.4
LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1	0.0.4
LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2	1.0.0
LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3	0.0.0
LLH:BUF.1.LONG.H3.0.LONG.H3	0.0.10
LLH:BUF.1.LONG.H4.0.LONG.H4	1.0.7
LLH:BUF.1.LONG.H5.0.LONG.H5	0.0.7
LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0	1.0.5
LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1	0.0.5
LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2	1.0.1
LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3	0.0.1
inverted	~[0]

Tile LLHQ.IO.T

Cells: 2

Bel LLH

Switchbox LLH

xc4000ex LLHQ.IO.T switchbox LLH
Destination	Source	Kind
TCELL0_LONG.H0	TCELL1_LONG.H0	buffer
TCELL0_LONG.H1	TCELL1_LONG.H1	buffer
TCELL0_LONG.H2	TCELL1_LONG.H2	buffer
TCELL0_LONG.IO.H0	TCELL1_LONG.IO.H0	buffer
TCELL0_LONG.IO.H1	TCELL1_LONG.IO.H1	buffer
TCELL0_LONG.IO.H2	TCELL1_LONG.IO.H2	buffer
TCELL0_LONG.IO.H3	TCELL1_LONG.IO.H3	buffer
TCELL1_LONG.H0	TCELL0_LONG.H0	buffer
TCELL1_LONG.H1	TCELL0_LONG.H1	buffer
TCELL1_LONG.H2	TCELL0_LONG.H2	buffer
TCELL1_LONG.IO.H0	TCELL0_LONG.IO.H0	buffer
TCELL1_LONG.IO.H1	TCELL0_LONG.IO.H1	buffer
TCELL1_LONG.IO.H2	TCELL0_LONG.IO.H2	buffer
TCELL1_LONG.IO.H3	TCELL0_LONG.IO.H3	buffer

Bitstream

xc4000ex LLHQ.IO.T bittile 0
Bit	Frame
Bit	0
7	~LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3
6	~LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3
5	~LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2
4	~LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2
3	~LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1
2	~LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1
1	~LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0
0	~LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0

xc4000ex LLHQ.IO.T bittile 1
Bit	Frame
Bit	0
11	~LLH:BUF.1.LONG.H0.0.LONG.H0
10	~LLH:BUF.0.LONG.H0.1.LONG.H0
9	~LLH:BUF.1.LONG.H1.0.LONG.H1
8	~LLH:BUF.0.LONG.H1.1.LONG.H1
7	~LLH:BUF.1.LONG.H2.0.LONG.H2
6	~LLH:BUF.0.LONG.H2.1.LONG.H2
5	-
4	-
3	-
2	-
1	-
0	-

LLH:BUF.0.LONG.H0.1.LONG.H0	1.0.10
LLH:BUF.0.LONG.H1.1.LONG.H1	1.0.8
LLH:BUF.0.LONG.H2.1.LONG.H2	1.0.6
LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0	0.0.1
LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1	0.0.3
LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2	0.0.5
LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3	0.0.7
LLH:BUF.1.LONG.H0.0.LONG.H0	1.0.11
LLH:BUF.1.LONG.H1.0.LONG.H1	1.0.9
LLH:BUF.1.LONG.H2.0.LONG.H2	1.0.7
LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0	0.0.0
LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1	0.0.2
LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2	0.0.4
LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3	0.0.6
inverted	~[0]

Tile LLVC.CLB

Cells: 2

Bel LLV

Switchbox LLV

xc4000ex LLVC.CLB switchbox LLV
Destination	Source	Kind
TCELL0_LONG.V0	TCELL1_LONG.V0	buffer
TCELL0_LONG.V1	TCELL1_LONG.V1	buffer
TCELL0_LONG.V2	TCELL1_LONG.V2	buffer
TCELL0_LONG.V3	TCELL1_LONG.V3	buffer
TCELL0_LONG.V4	TCELL1_LONG.V4	buffer
TCELL0_LONG.V5	TCELL1_LONG.V5	buffer
TCELL0_LONG.V6	TCELL1_LONG.V6	buffer
TCELL0_LONG.V7	TCELL1_LONG.V7	buffer
TCELL0_LONG.V8	TCELL1_LONG.V8	buffer
TCELL0_LONG.V9	TCELL1_LONG.V9	buffer
TCELL0_VCLK	TCELL0_QUAD.V0.4	mux
	TCELL1_SINGLE.V0	mux
	TCELL1_SINGLE.V1	mux
	TCELL1_SINGLE.V2	mux
	TCELL1_SINGLE.V4	mux
	TCELL1_SINGLE.V5	mux
	TCELL1_QUAD.V2.0	mux
	TCELL1_LONG.V0	mux
	TCELL1_LONG.V4	mux
	TCELL1_LONG.V6	mux
	TCELL1_GCLK2	mux
	TCELL1_GCLK5	mux
TCELL1_LONG.V0	TCELL0_LONG.V0	buffer
TCELL1_LONG.V1	TCELL0_LONG.V1	buffer
TCELL1_LONG.V2	TCELL0_LONG.V2	buffer
TCELL1_LONG.V3	TCELL0_LONG.V3	buffer
TCELL1_LONG.V4	TCELL0_LONG.V4	buffer
TCELL1_LONG.V5	TCELL0_LONG.V5	buffer
TCELL1_LONG.V6	TCELL0_LONG.V6	buffer
TCELL1_LONG.V7	TCELL0_LONG.V7	buffer
TCELL1_LONG.V8	TCELL0_LONG.V8	buffer
TCELL1_LONG.V9	TCELL0_LONG.V9	buffer
TCELL1_VCLK	TCELL0_QUAD.V1.4	mux
	TCELL0_LONG.V1	mux
	TCELL0_LONG.V5	mux
	TCELL0_LONG.V8	mux
	TCELL0_GCLK1	mux
	TCELL0_GCLK4	mux
	TCELL1_SINGLE.V0	mux
	TCELL1_SINGLE.V1	mux
	TCELL1_SINGLE.V4	mux
	TCELL1_SINGLE.V5	mux
	TCELL1_SINGLE.V6	mux
	TCELL1_QUAD.V0.0	mux

Bitstream

xc4000ex LLVC.CLB bittile 0
Bit	Frame
Bit	45	44	43	42	41	40	39	38	37	36	35	34	33	32	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	~LLV:BUF.0.LONG.V6.1.LONG.V6	~LLV:BUF.1.LONG.V6.0.LONG.V6	~LLV:BUF.0.LONG.V5.1.LONG.V5	~LLV:BUF.1.LONG.V5.0.LONG.V5	~LLV:BUF.0.LONG.V3.1.LONG.V3	~LLV:BUF.1.LONG.V3.0.LONG.V3	~LLV:BUF.1.LONG.V7.0.LONG.V7	~LLV:BUF.0.LONG.V7.1.LONG.V7	-	-	~LLV:BUF.1.LONG.V8.0.LONG.V8	~LLV:BUF.0.LONG.V8.1.LONG.V8	~LLV:BUF.0.LONG.V9.1.LONG.V9	~LLV:BUF.1.LONG.V9.0.LONG.V9	-	~LLV:BUF.1.LONG.V4.0.LONG.V4	-	~LLV:BUF.0.LONG.V1.1.LONG.V1	~LLV:BUF.1.LONG.V1.0.LONG.V1	~LLV:BUF.0.LONG.V0.1.LONG.V0	~LLV:BUF.1.LONG.V0.0.LONG.V0	~LLV:BUF.0.LONG.V4.1.LONG.V4	~LLV:BUF.1.LONG.V2.0.LONG.V2	~LLV:BUF.0.LONG.V2.1.LONG.V2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0	-	-	-	-	-	-	-	-	-	-	LLV:MUX.0.VCLK[3]	LLV:MUX.1.VCLK[3]	-	-	-	-	LLV:MUX.1.VCLK[2]	LLV:MUX.1.VCLK[1]	-	-	-	-	LLV:MUX.1.VCLK[4]	LLV:MUX.1.VCLK[0]	-	-	LLV:MUX.1.VCLK[6]	LLV:MUX.1.VCLK[5]	-	-	LLV:MUX.0.VCLK[4]	LLV:MUX.0.VCLK[2]	-	-	-	-	-	LLV:MUX.0.VCLK[1]	LLV:MUX.0.VCLK[0]	LLV:MUX.0.VCLK[5]	LLV:MUX.0.VCLK[6]	-	-	-	-	-

LLV:BUF.0.LONG.V0.1.LONG.V0	0.26.1
LLV:BUF.0.LONG.V1.1.LONG.V1	0.28.1
LLV:BUF.0.LONG.V2.1.LONG.V2	0.22.1
LLV:BUF.0.LONG.V3.1.LONG.V3	0.41.1
LLV:BUF.0.LONG.V4.1.LONG.V4	0.24.1
LLV:BUF.0.LONG.V5.1.LONG.V5	0.43.1
LLV:BUF.0.LONG.V6.1.LONG.V6	0.45.1
LLV:BUF.0.LONG.V7.1.LONG.V7	0.38.1
LLV:BUF.0.LONG.V8.1.LONG.V8	0.34.1
LLV:BUF.0.LONG.V9.1.LONG.V9	0.33.1
LLV:BUF.1.LONG.V0.0.LONG.V0	0.25.1
LLV:BUF.1.LONG.V1.0.LONG.V1	0.27.1
LLV:BUF.1.LONG.V2.0.LONG.V2	0.23.1
LLV:BUF.1.LONG.V3.0.LONG.V3	0.40.1
LLV:BUF.1.LONG.V4.0.LONG.V4	0.30.1
LLV:BUF.1.LONG.V5.0.LONG.V5	0.42.1
LLV:BUF.1.LONG.V6.0.LONG.V6	0.44.1
LLV:BUF.1.LONG.V7.0.LONG.V7	0.39.1
LLV:BUF.1.LONG.V8.0.LONG.V8	0.35.1
LLV:BUF.1.LONG.V9.0.LONG.V9	0.32.1
inverted	~[0]

LLV:MUX.0.VCLK	0.5.0	0.6.0	0.15.0	0.35.0	0.14.0	0.8.0	0.7.0
0.QUAD.V0.4	0	0	0	0	1	1	1
1.LONG.V0	0	0	0	1	0	1	1
1.QUAD.V2.0	0	0	1	0	1	0	1
1.LONG.V6	0	0	1	0	1	1	0
1.SINGLE.V1	0	0	1	1	0	0	1
1.SINGLE.V2	0	0	1	1	0	1	0
1.GCLK5	0	1	1	0	1	1	1
1.SINGLE.V4	0	1	1	1	0	1	1
1.SINGLE.V5	1	0	0	1	1	1	1
1.LONG.V4	1	0	1	1	1	0	1
1.GCLK2	1	0	1	1	1	1	0
1.SINGLE.V0	1	1	1	1	1	1	1

LLV:MUX.1.VCLK	0.19.0	0.18.0	0.23.0	0.34.0	0.29.0	0.28.0	0.22.0
0.QUAD.V1.4	0	0	0	0	1	1	1
1.SINGLE.V1	0	0	0	1	0	1	1
1.QUAD.V0.0	0	0	1	0	1	0	1
0.LONG.V8	0	0	1	0	1	1	0
0.LONG.V1	0	0	1	1	0	0	1
1.SINGLE.V4	0	0	1	1	0	1	0
0.LONG.V5	0	1	0	1	1	1	1
1.SINGLE.V6	0	1	1	1	1	0	1
0.GCLK1	0	1	1	1	1	1	0
0.GCLK4	1	0	1	0	1	1	1
1.SINGLE.V5	1	0	1	1	0	1	1
1.SINGLE.V0	1	1	1	1	1	1	1

Tile LLVC.IO.L

Cells: 2

Bel PULLUP_DEC0_S

xc4000ex LLVC.IO.L bel PULLUP_DEC0_S
Pin	Direction	Wires
O	output	TCELL0:DEC.V0

Bel PULLUP_DEC1_S

xc4000ex LLVC.IO.L bel PULLUP_DEC1_S
Pin	Direction	Wires
O	output	TCELL0:DEC.V1

Bel PULLUP_DEC2_S

xc4000ex LLVC.IO.L bel PULLUP_DEC2_S
Pin	Direction	Wires
O	output	TCELL0:DEC.V2

Bel PULLUP_DEC3_S

xc4000ex LLVC.IO.L bel PULLUP_DEC3_S
Pin	Direction	Wires
O	output	TCELL0:DEC.V3

Bel PULLUP_DEC0_N

xc4000ex LLVC.IO.L bel PULLUP_DEC0_N
Pin	Direction	Wires
O	output	TCELL1:DEC.V0

Bel PULLUP_DEC1_N

xc4000ex LLVC.IO.L bel PULLUP_DEC1_N
Pin	Direction	Wires
O	output	TCELL1:DEC.V1

Bel PULLUP_DEC2_N

xc4000ex LLVC.IO.L bel PULLUP_DEC2_N
Pin	Direction	Wires
O	output	TCELL1:DEC.V2

Bel PULLUP_DEC3_N

xc4000ex LLVC.IO.L bel PULLUP_DEC3_N
Pin	Direction	Wires
O	output	TCELL1:DEC.V3

Bel LLV

Switchbox LLV

xc4000ex LLVC.IO.L switchbox LLV
Destination	Source	Kind
TCELL0_LONG.IO.V0	TCELL1_LONG.IO.V0	buffer
TCELL0_LONG.IO.V1	TCELL1_LONG.IO.V1	buffer
TCELL0_LONG.IO.V2	TCELL1_LONG.IO.V2	buffer
TCELL0_LONG.IO.V3	TCELL1_LONG.IO.V3	buffer
TCELL0_DEC.V0	TCELL1_DEC.V0	bidirectional pass transistor
TCELL0_DEC.V1	TCELL1_DEC.V1	bidirectional pass transistor
TCELL0_DEC.V2	TCELL1_DEC.V2	bidirectional pass transistor
TCELL0_DEC.V3	TCELL1_DEC.V3	bidirectional pass transistor
TCELL1_LONG.IO.V0	TCELL0_LONG.IO.V0	buffer
TCELL1_LONG.IO.V1	TCELL0_LONG.IO.V1	buffer
TCELL1_LONG.IO.V2	TCELL0_LONG.IO.V2	buffer
TCELL1_LONG.IO.V3	TCELL0_LONG.IO.V3	buffer
TCELL1_DEC.V0	TCELL0_DEC.V0	bidirectional pass transistor
TCELL1_DEC.V1	TCELL0_DEC.V1	bidirectional pass transistor
TCELL1_DEC.V2	TCELL0_DEC.V2	bidirectional pass transistor
TCELL1_DEC.V3	TCELL0_DEC.V3	bidirectional pass transistor

Bel wires

xc4000ex LLVC.IO.L bel wires
Wire	Pins
TCELL0:DEC.V0	PULLUP_DEC0_S.O
TCELL0:DEC.V1	PULLUP_DEC1_S.O
TCELL0:DEC.V2	PULLUP_DEC2_S.O
TCELL0:DEC.V3	PULLUP_DEC3_S.O
TCELL1:DEC.V0	PULLUP_DEC0_N.O
TCELL1:DEC.V1	PULLUP_DEC1_N.O
TCELL1:DEC.V2	PULLUP_DEC2_N.O
TCELL1:DEC.V3	PULLUP_DEC3_N.O

Bitstream

xc4000ex LLVC.IO.L bittile 0
Bit	Frame
Bit	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	~LLV:BIPASS.0.DEC.V1.1.DEC.V1	~LLV:BIPASS.0.DEC.V3.1.DEC.V3	~PULLUP_DEC3_S:ENABLE	~PULLUP_DEC3_N:ENABLE	~PULLUP_DEC1_N:ENABLE	~PULLUP_DEC1_S:ENABLE	~PULLUP_DEC2_S:ENABLE	~PULLUP_DEC2_N:ENABLE	~LLV:BIPASS.0.DEC.V0.1.DEC.V0	~LLV:BIPASS.0.DEC.V2.1.DEC.V2	~PULLUP_DEC0_N:ENABLE	~PULLUP_DEC0_S:ENABLE	~LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1	~LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1	~LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0	~LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0	-	-	~LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2	~LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2	~LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3	~LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3	-	-	-	-
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

LLV:BIPASS.0.DEC.V0.1.DEC.V0	0.17.1
LLV:BIPASS.0.DEC.V1.1.DEC.V1	0.25.1
LLV:BIPASS.0.DEC.V2.1.DEC.V2	0.16.1
LLV:BIPASS.0.DEC.V3.1.DEC.V3	0.24.1
LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0	0.10.1
LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1	0.13.1
LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2	0.6.1
LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3	0.5.1
LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0	0.11.1
LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1	0.12.1
LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2	0.7.1
LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3	0.4.1
PULLUP_DEC0_N:ENABLE	0.15.1
PULLUP_DEC0_S:ENABLE	0.14.1
PULLUP_DEC1_N:ENABLE	0.21.1
PULLUP_DEC1_S:ENABLE	0.20.1
PULLUP_DEC2_N:ENABLE	0.18.1
PULLUP_DEC2_S:ENABLE	0.19.1
PULLUP_DEC3_N:ENABLE	0.22.1
PULLUP_DEC3_S:ENABLE	0.23.1
inverted	~[0]

Tile LLVC.IO.R

Cells: 2

Bel PULLUP_DEC0_S

xc4000ex LLVC.IO.R bel PULLUP_DEC0_S
Pin	Direction	Wires
O	output	TCELL0:DEC.V0

Bel PULLUP_DEC1_S

xc4000ex LLVC.IO.R bel PULLUP_DEC1_S
Pin	Direction	Wires
O	output	TCELL0:DEC.V1

Bel PULLUP_DEC2_S

xc4000ex LLVC.IO.R bel PULLUP_DEC2_S
Pin	Direction	Wires
O	output	TCELL0:DEC.V2

Bel PULLUP_DEC3_S

xc4000ex LLVC.IO.R bel PULLUP_DEC3_S
Pin	Direction	Wires
O	output	TCELL0:DEC.V3

Bel PULLUP_DEC0_N

xc4000ex LLVC.IO.R bel PULLUP_DEC0_N
Pin	Direction	Wires
O	output	TCELL1:DEC.V0

Bel PULLUP_DEC1_N

xc4000ex LLVC.IO.R bel PULLUP_DEC1_N
Pin	Direction	Wires
O	output	TCELL1:DEC.V1

Bel PULLUP_DEC2_N

xc4000ex LLVC.IO.R bel PULLUP_DEC2_N
Pin	Direction	Wires
O	output	TCELL1:DEC.V2

Bel PULLUP_DEC3_N

xc4000ex LLVC.IO.R bel PULLUP_DEC3_N
Pin	Direction	Wires
O	output	TCELL1:DEC.V3

Bel LLV

Switchbox LLV

xc4000ex LLVC.IO.R switchbox LLV
Destination	Source	Kind
TCELL0_LONG.V0	TCELL1_LONG.V0	buffer
TCELL0_LONG.V1	TCELL1_LONG.V1	buffer
TCELL0_LONG.V2	TCELL1_LONG.V2	buffer
TCELL0_LONG.V3	TCELL1_LONG.V3	buffer
TCELL0_LONG.V4	TCELL1_LONG.V4	buffer
TCELL0_LONG.V5	TCELL1_LONG.V5	buffer
TCELL0_LONG.V6	TCELL1_LONG.V6	buffer
TCELL0_LONG.V7	TCELL1_LONG.V7	buffer
TCELL0_LONG.V8	TCELL1_LONG.V8	buffer
TCELL0_LONG.V9	TCELL1_LONG.V9	buffer
TCELL0_LONG.IO.V0	TCELL1_LONG.IO.V0	buffer
TCELL0_LONG.IO.V1	TCELL1_LONG.IO.V1	buffer
TCELL0_LONG.IO.V2	TCELL1_LONG.IO.V2	buffer
TCELL0_LONG.IO.V3	TCELL1_LONG.IO.V3	buffer
TCELL0_DEC.V0	TCELL1_DEC.V0	bidirectional pass transistor
TCELL0_DEC.V1	TCELL1_DEC.V1	bidirectional pass transistor
TCELL0_DEC.V2	TCELL1_DEC.V2	bidirectional pass transistor
TCELL0_DEC.V3	TCELL1_DEC.V3	bidirectional pass transistor
TCELL0_VCLK	TCELL0_QUAD.V0.4	mux
	TCELL1_SINGLE.V0	mux
	TCELL1_SINGLE.V1	mux
	TCELL1_SINGLE.V2	mux
	TCELL1_SINGLE.V4	mux
	TCELL1_SINGLE.V5	mux
	TCELL1_QUAD.V2.0	mux
	TCELL1_LONG.V0	mux
	TCELL1_LONG.V4	mux
	TCELL1_LONG.V6	mux
	TCELL1_GCLK2	mux
	TCELL1_GCLK5	mux
TCELL1_LONG.V0	TCELL0_LONG.V0	buffer
TCELL1_LONG.V1	TCELL0_LONG.V1	buffer
TCELL1_LONG.V2	TCELL0_LONG.V2	buffer
TCELL1_LONG.V3	TCELL0_LONG.V3	buffer
TCELL1_LONG.V4	TCELL0_LONG.V4	buffer
TCELL1_LONG.V5	TCELL0_LONG.V5	buffer
TCELL1_LONG.V6	TCELL0_LONG.V6	buffer
TCELL1_LONG.V7	TCELL0_LONG.V7	buffer
TCELL1_LONG.V8	TCELL0_LONG.V8	buffer
TCELL1_LONG.V9	TCELL0_LONG.V9	buffer
TCELL1_LONG.IO.V0	TCELL0_LONG.IO.V0	buffer
TCELL1_LONG.IO.V1	TCELL0_LONG.IO.V1	buffer
TCELL1_LONG.IO.V2	TCELL0_LONG.IO.V2	buffer
TCELL1_LONG.IO.V3	TCELL0_LONG.IO.V3	buffer
TCELL1_DEC.V0	TCELL0_DEC.V0	bidirectional pass transistor
TCELL1_DEC.V1	TCELL0_DEC.V1	bidirectional pass transistor
TCELL1_DEC.V2	TCELL0_DEC.V2	bidirectional pass transistor
TCELL1_DEC.V3	TCELL0_DEC.V3	bidirectional pass transistor
TCELL1_VCLK	TCELL0_QUAD.V1.4	mux
	TCELL0_LONG.V1	mux
	TCELL0_LONG.V5	mux
	TCELL0_LONG.V8	mux
	TCELL0_GCLK1	mux
	TCELL0_GCLK4	mux
	TCELL1_SINGLE.V0	mux
	TCELL1_SINGLE.V1	mux
	TCELL1_SINGLE.V4	mux
	TCELL1_SINGLE.V5	mux
	TCELL1_SINGLE.V6	mux
	TCELL1_QUAD.V0.0	mux

Bel wires

xc4000ex LLVC.IO.R bel wires
Wire	Pins
TCELL0:DEC.V0	PULLUP_DEC0_S.O
TCELL0:DEC.V1	PULLUP_DEC1_S.O
TCELL0:DEC.V2	PULLUP_DEC2_S.O
TCELL0:DEC.V3	PULLUP_DEC3_S.O
TCELL1:DEC.V0	PULLUP_DEC0_N.O
TCELL1:DEC.V1	PULLUP_DEC1_N.O
TCELL1:DEC.V2	PULLUP_DEC2_N.O
TCELL1:DEC.V3	PULLUP_DEC3_N.O

Bitstream

xc4000ex LLVC.IO.R bittile 0
Bit	Frame
Bit	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	~LLV:BUF.0.LONG.V6.1.LONG.V6	~LLV:BUF.1.LONG.V6.0.LONG.V6	-	-	-	-	~LLV:BUF.1.LONG.V7.0.LONG.V7	~LLV:BUF.0.LONG.V7.1.LONG.V7	-	-	~LLV:BUF.1.LONG.V8.0.LONG.V8	~LLV:BUF.0.LONG.V8.1.LONG.V8	~LLV:BUF.0.LONG.V9.1.LONG.V9	~LLV:BUF.1.LONG.V9.0.LONG.V9	-	~LLV:BIPASS.0.DEC.V3.1.DEC.V3	~LLV:BUF.0.LONG.V1.1.LONG.V1	~PULLUP_DEC3_S:ENABLE	~LLV:BUF.1.LONG.V1.0.LONG.V1	~PULLUP_DEC3_N:ENABLE	~LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0	~LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0	~LLV:BUF.1.LONG.V2.0.LONG.V2	~LLV:BUF.0.LONG.V2.1.LONG.V2	~LLV:BUF.0.LONG.V4.1.LONG.V4	~LLV:BUF.1.LONG.V4.0.LONG.V4	~LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2	~LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2	-	-	~LLV:BUF.0.LONG.V3.1.LONG.V3	~LLV:BUF.1.LONG.V3.0.LONG.V3	~LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3	~LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3	~LLV:BUF.0.LONG.V0.1.LONG.V0	~LLV:BUF.1.LONG.V0.0.LONG.V0	~LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1	~LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1	~PULLUP_DEC1_S:ENABLE	~PULLUP_DEC1_N:ENABLE	~LLV:BUF.1.LONG.V5.0.LONG.V5	~LLV:BUF.0.LONG.V5.1.LONG.V5	-	~PULLUP_DEC0_N:ENABLE	~PULLUP_DEC2_N:ENABLE	~PULLUP_DEC2_S:ENABLE	~PULLUP_DEC0_S:ENABLE	-	-	-	-
0	-	-	-	-	-	-	-	-	-	-	LLV:MUX.0.VCLK[3]	LLV:MUX.1.VCLK[3]	-	-	-	-	LLV:MUX.1.VCLK[2]	LLV:MUX.1.VCLK[1]	-	-	-	-	LLV:MUX.1.VCLK[4]	LLV:MUX.1.VCLK[0]	-	-	LLV:MUX.1.VCLK[6]	LLV:MUX.1.VCLK[5]	-	-	LLV:MUX.0.VCLK[4]	LLV:MUX.0.VCLK[2]	-	-	-	-	-	-	LLV:MUX.0.VCLK[1]	LLV:MUX.0.VCLK[0]	LLV:MUX.0.VCLK[5]	LLV:MUX.0.VCLK[6]	-	~LLV:BIPASS.0.DEC.V1.1.DEC.V1	-	~LLV:BIPASS.0.DEC.V2.1.DEC.V2	~LLV:BIPASS.0.DEC.V0.1.DEC.V0	-	~MISC:TLC	-	-

LLV:BIPASS.0.DEC.V0.1.DEC.V0	0.4.0
LLV:BIPASS.0.DEC.V1.1.DEC.V1	0.7.0
LLV:BIPASS.0.DEC.V2.1.DEC.V2	0.5.0
LLV:BIPASS.0.DEC.V3.1.DEC.V3	0.35.1
LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0	0.30.1
LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1	0.13.1
LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2	0.23.1
LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3	0.18.1
LLV:BUF.0.LONG.V0.1.LONG.V0	0.16.1
LLV:BUF.0.LONG.V1.1.LONG.V1	0.34.1
LLV:BUF.0.LONG.V2.1.LONG.V2	0.27.1
LLV:BUF.0.LONG.V3.1.LONG.V3	0.20.1
LLV:BUF.0.LONG.V4.1.LONG.V4	0.26.1
LLV:BUF.0.LONG.V5.1.LONG.V5	0.9.1
LLV:BUF.0.LONG.V6.1.LONG.V6	0.50.1
LLV:BUF.0.LONG.V7.1.LONG.V7	0.43.1
LLV:BUF.0.LONG.V8.1.LONG.V8	0.39.1
LLV:BUF.0.LONG.V9.1.LONG.V9	0.38.1
LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0	0.29.1
LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1	0.14.1
LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2	0.24.1
LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3	0.17.1
LLV:BUF.1.LONG.V0.0.LONG.V0	0.15.1
LLV:BUF.1.LONG.V1.0.LONG.V1	0.32.1
LLV:BUF.1.LONG.V2.0.LONG.V2	0.28.1
LLV:BUF.1.LONG.V3.0.LONG.V3	0.19.1
LLV:BUF.1.LONG.V4.0.LONG.V4	0.25.1
LLV:BUF.1.LONG.V5.0.LONG.V5	0.10.1
LLV:BUF.1.LONG.V6.0.LONG.V6	0.49.1
LLV:BUF.1.LONG.V7.0.LONG.V7	0.44.1
LLV:BUF.1.LONG.V8.0.LONG.V8	0.40.1
LLV:BUF.1.LONG.V9.0.LONG.V9	0.37.1
MISC:TLC	0.2.0
PULLUP_DEC0_N:ENABLE	0.7.1
PULLUP_DEC0_S:ENABLE	0.4.1
PULLUP_DEC1_N:ENABLE	0.11.1
PULLUP_DEC1_S:ENABLE	0.12.1
PULLUP_DEC2_N:ENABLE	0.6.1
PULLUP_DEC2_S:ENABLE	0.5.1
PULLUP_DEC3_N:ENABLE	0.31.1
PULLUP_DEC3_S:ENABLE	0.33.1
inverted	~[0]

LLV:MUX.0.VCLK	0.9.0	0.10.0	0.20.0	0.40.0	0.19.0	0.12.0	0.11.0
0.QUAD.V0.4	0	0	0	0	1	1	1
1.LONG.V0	0	0	0	1	0	1	1
1.QUAD.V2.0	0	0	1	0	1	0	1
1.LONG.V6	0	0	1	0	1	1	0
1.SINGLE.V1	0	0	1	1	0	0	1
1.SINGLE.V2	0	0	1	1	0	1	0
1.GCLK5	0	1	1	0	1	1	1
1.SINGLE.V4	0	1	1	1	0	1	1
1.SINGLE.V5	1	0	0	1	1	1	1
1.LONG.V4	1	0	1	1	1	0	1
1.GCLK2	1	0	1	1	1	1	0
1.SINGLE.V0	1	1	1	1	1	1	1

LLV:MUX.1.VCLK	0.24.0	0.23.0	0.28.0	0.39.0	0.34.0	0.33.0	0.27.0
0.QUAD.V1.4	0	0	0	0	1	1	1
1.SINGLE.V1	0	0	0	1	0	1	1
1.QUAD.V0.0	0	0	1	0	1	0	1
0.LONG.V8	0	0	1	0	1	1	0
0.LONG.V1	0	0	1	1	0	0	1
1.SINGLE.V4	0	0	1	1	0	1	0
0.LONG.V5	0	1	0	1	1	1	1
1.SINGLE.V6	0	1	1	1	1	0	1
0.GCLK1	0	1	1	1	1	1	0
0.GCLK4	1	0	1	0	1	1	1
1.SINGLE.V5	1	0	1	1	0	1	1
1.SINGLE.V0	1	1	1	1	1	1	1

Tile LLVQ.CLB

Cells: 2

Bel LLV

Switchbox LLV

xc4000ex LLVQ.CLB switchbox LLV
Destination	Source	Kind
TCELL0_QUAD.V1.4	TCELL0_VCLK	pass transistor
TCELL0_QUAD.V2.4	TCELL1_VCLK	pass transistor
TCELL0_LONG.V0	TCELL1_LONG.V0	buffer
TCELL0_LONG.V1	TCELL1_LONG.V1	buffer
TCELL0_LONG.V2	TCELL1_LONG.V2	buffer
TCELL0_LONG.V3	TCELL1_LONG.V3	buffer
TCELL0_LONG.V4	TCELL1_LONG.V4	buffer
TCELL0_LONG.V5	TCELL1_LONG.V5	buffer
TCELL0_LONG.V6	TCELL1_LONG.V6	buffer
TCELL0_LONG.V7	TCELL1_LONG.V7.EXCL	mux
TCELL0_LONG.V8	TCELL1_LONG.V8	buffer
TCELL0_LONG.V9	TCELL1_LONG.V9.EXCL	mux
TCELL0_GCLK0	TCELL0_QUAD.V0.3	mux
	TCELL0_VCLK	mux
	TCELL1_SINGLE.V0	mux
	TCELL1_VCLK	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK1	TCELL0_QUAD.V0.4	mux
	TCELL0_VCLK	mux
	TCELL1_SINGLE.V1	mux
	TCELL1_VCLK	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK2	TCELL0_VCLK	mux
	TCELL1_SINGLE.V2	mux
	TCELL1_QUAD.V0.0	mux
	TCELL1_VCLK	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK3	TCELL0_QUAD.V1.4	mux
	TCELL0_VCLK	mux
	TCELL1_SINGLE.V3	mux
	TCELL1_VCLK	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK4	TCELL0_VCLK	mux
	TCELL1_SINGLE.V4	mux
	TCELL1_QUAD.V1.0	mux
	TCELL1_VCLK	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK5	TCELL0_QUAD.V2.3	mux
	TCELL0_VCLK	mux
	TCELL1_SINGLE.V5	mux
	TCELL1_VCLK	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK6	TCELL0_QUAD.V2.4	mux
	TCELL0_VCLK	mux
	TCELL1_SINGLE.V6	mux
	TCELL1_VCLK	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK7	TCELL0_VCLK	mux
	TCELL1_SINGLE.V7	mux
	TCELL1_QUAD.V2.0	mux
	TCELL1_VCLK	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL1_SINGLE.V0	TCELL0_VCLK	pass transistor
TCELL1_SINGLE.V1	TCELL1_VCLK	pass transistor
TCELL1_SINGLE.V2	TCELL0_VCLK	pass transistor
TCELL1_SINGLE.V3	TCELL1_VCLK	pass transistor
TCELL1_SINGLE.V4	TCELL0_VCLK	pass transistor
TCELL1_SINGLE.V5	TCELL1_VCLK	pass transistor
TCELL1_SINGLE.V6	TCELL0_VCLK	pass transistor
TCELL1_SINGLE.V7	TCELL1_VCLK	pass transistor
TCELL1_QUAD.V0.0	TCELL1_VCLK	pass transistor
TCELL1_QUAD.V2.0	TCELL0_VCLK	pass transistor
TCELL1_LONG.V0	TCELL0_LONG.V0	buffer
TCELL1_LONG.V1	TCELL0_LONG.V1	buffer
TCELL1_LONG.V2	TCELL0_LONG.V2	buffer
TCELL1_LONG.V3	TCELL0_LONG.V3	buffer
TCELL1_LONG.V4	TCELL0_LONG.V4	buffer
TCELL1_LONG.V5	TCELL0_LONG.V5	buffer
TCELL1_LONG.V6	TCELL0_LONG.V6	buffer
TCELL1_LONG.V7	TCELL1_LONG.V7.EXCL	mux
TCELL1_LONG.V7.EXCL	TCELL0_LONG.V7	mux
	TCELL0_VCLK	mux
	TCELL1_LONG.V7	mux
TCELL1_LONG.V8	TCELL0_LONG.V8	buffer
TCELL1_LONG.V9	TCELL1_LONG.V9.EXCL	mux
TCELL1_LONG.V9.EXCL	TCELL0_LONG.V9	mux
	TCELL1_LONG.V9	mux
	TCELL1_VCLK	mux

Bitstream

xc4000ex LLVQ.CLB bittile 0
Bit	Frame
Bit	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	~LLV:BUF.0.LONG.V6.1.LONG.V6	~LLV:BUF.0.LONG.V7.1.LONG.V7	~LLV:PASS.1.QUAD.V0.0.1.VCLK	LLV:MUX.1.LONG.V7[0]	~LLV:BUF.0.LONG.V8.1.LONG.V8	LLV:MUX.0.GCLK4[3]	LLV:MUX.0.GCLK4[4]	LLV:MUX.0.GCLK4[6]	LLV:MUX.0.GCLK4[0]	~LLV:BUF.1.LONG.V9.0.LONG.V9	LLV:MUX.0.LONG.V9[0]	LLV:MUX.0.GCLK5[5]	LLV:MUX.0.GCLK5[3]	LLV:MUX.0.GCLK5[6]	LLV:MUX.0.GCLK5[0]	~LLV:BUF.0.LONG.V2.1.LONG.V2	LLV:MUX.0.GCLK0[5]	LLV:MUX.0.GCLK0[3]	LLV:MUX.0.GCLK0[6]	LLV:MUX.0.GCLK0[0]	~LLV:PASS.1.SINGLE.V1.1.VCLK	~LLV:BUF.0.LONG.V4.1.LONG.V4	LLV:MUX.0.GCLK6[5]	LLV:MUX.0.GCLK6[3]	LLV:MUX.0.GCLK6[6]	LLV:MUX.0.GCLK6[0]	~LLV:BUF.0.LONG.V1.1.LONG.V1	LLV:MUX.0.GCLK7[3]	LLV:MUX.0.GCLK7[4]	LLV:MUX.0.GCLK7[6]	LLV:MUX.0.GCLK7[0]	~LLV:BUF.0.LONG.V5.1.LONG.V5	-	LLV:MUX.0.GCLK2[3]	LLV:MUX.0.GCLK2[4]	LLV:MUX.0.GCLK2[6]	LLV:MUX.0.GCLK2[0]	~LLV:BUF.0.LONG.V3.1.LONG.V3	LLV:MUX.0.GCLK3[5]	LLV:MUX.0.GCLK3[3]	LLV:MUX.0.GCLK3[6]	LLV:MUX.0.GCLK3[0]	~LLV:BUF.0.LONG.V0.1.LONG.V0	LLV:MUX.0.GCLK1[5]	LLV:MUX.0.GCLK1[3]	LLV:MUX.0.GCLK1[6]	LLV:MUX.0.GCLK1[0]
0	~LLV:BUF.1.LONG.V6.0.LONG.V6	LLV:MUX.1.LONG.V7[1]	~LLV:BUF.1.LONG.V8.0.LONG.V8	~LLV:PASS.0.QUAD.V1.4.0.VCLK	~LLV:PASS.0.QUAD.V2.4.1.VCLK	LLV:MUX.0.GCLK4[5]	LLV:MUX.0.GCLK4[2]	LLV:MUX.0.GCLK4[1]	~LLV:PASS.1.SINGLE.V4.0.VCLK	~LLV:PASS.1.SINGLE.V6.0.VCLK	LLV:MUX.0.LONG.V9[1]	LLV:MUX.0.GCLK5[4]	LLV:MUX.0.GCLK5[2]	LLV:MUX.0.GCLK5[1]	~LLV:PASS.1.SINGLE.V7.1.VCLK	~LLV:BUF.1.LONG.V2.0.LONG.V2	LLV:MUX.0.GCLK0[4]	LLV:MUX.0.GCLK0[2]	~LLV:PASS.1.SINGLE.V5.1.VCLK	~LLV:PASS.1.SINGLE.V3.1.VCLK	LLV:MUX.0.GCLK0[1]	~LLV:BUF.1.LONG.V4.0.LONG.V4	LLV:MUX.0.GCLK6[4]	LLV:MUX.0.GCLK6[2]	~LLV:PASS.1.QUAD.V2.0.0.VCLK	LLV:MUX.0.GCLK6[1]	~LLV:BUF.1.LONG.V1.0.LONG.V1	LLV:MUX.0.GCLK7[5]	LLV:MUX.0.GCLK7[2]	~LLV:PASS.1.SINGLE.V0.0.VCLK	LLV:MUX.0.GCLK7[1]	~LLV:BUF.1.LONG.V5.0.LONG.V5	~LLV:PASS.1.SINGLE.V2.0.VCLK	LLV:MUX.0.GCLK2[5]	LLV:MUX.0.GCLK2[2]	-	LLV:MUX.0.GCLK2[1]	~LLV:BUF.1.LONG.V3.0.LONG.V3	LLV:MUX.0.GCLK3[4]	LLV:MUX.0.GCLK3[2]	-	LLV:MUX.0.GCLK3[1]	~LLV:BUF.1.LONG.V0.0.LONG.V0	LLV:MUX.0.GCLK1[4]	LLV:MUX.0.GCLK1[2]	-	LLV:MUX.0.GCLK1[1]

LLV:BUF.0.LONG.V0.1.LONG.V0	0.4.1
LLV:BUF.0.LONG.V1.1.LONG.V1	0.20.1
LLV:BUF.0.LONG.V2.1.LONG.V2	0.31.1
LLV:BUF.0.LONG.V3.1.LONG.V3	0.9.1
LLV:BUF.0.LONG.V4.1.LONG.V4	0.25.1
LLV:BUF.0.LONG.V5.1.LONG.V5	0.15.1
LLV:BUF.0.LONG.V6.1.LONG.V6	0.46.1
LLV:BUF.0.LONG.V7.1.LONG.V7	0.45.1
LLV:BUF.0.LONG.V8.1.LONG.V8	0.42.1
LLV:BUF.1.LONG.V0.0.LONG.V0	0.4.0
LLV:BUF.1.LONG.V1.0.LONG.V1	0.20.0
LLV:BUF.1.LONG.V2.0.LONG.V2	0.31.0
LLV:BUF.1.LONG.V3.0.LONG.V3	0.9.0
LLV:BUF.1.LONG.V4.0.LONG.V4	0.25.0
LLV:BUF.1.LONG.V5.0.LONG.V5	0.15.0
LLV:BUF.1.LONG.V6.0.LONG.V6	0.46.0
LLV:BUF.1.LONG.V8.0.LONG.V8	0.44.0
LLV:BUF.1.LONG.V9.0.LONG.V9	0.37.1
LLV:PASS.0.QUAD.V1.4.0.VCLK	0.43.0
LLV:PASS.0.QUAD.V2.4.1.VCLK	0.42.0
LLV:PASS.1.QUAD.V0.0.1.VCLK	0.44.1
LLV:PASS.1.QUAD.V2.0.0.VCLK	0.22.0
LLV:PASS.1.SINGLE.V0.0.VCLK	0.17.0
LLV:PASS.1.SINGLE.V1.1.VCLK	0.26.1
LLV:PASS.1.SINGLE.V2.0.VCLK	0.14.0
LLV:PASS.1.SINGLE.V3.1.VCLK	0.27.0
LLV:PASS.1.SINGLE.V4.0.VCLK	0.38.0
LLV:PASS.1.SINGLE.V5.1.VCLK	0.28.0
LLV:PASS.1.SINGLE.V6.0.VCLK	0.37.0
LLV:PASS.1.SINGLE.V7.1.VCLK	0.32.0
inverted	~[0]

LLV:MUX.0.GCLK0	0.28.1	0.30.1	0.30.0	0.29.1	0.29.0	0.26.0	0.27.1
0.QUAD.V0.3	0	0	1	1	1	1	1
0.VCLK	0	1	0	1	1	1	1
1.SINGLE.V0	0	1	1	0	1	1	1
1.VCLK	0	1	1	1	0	1	1
1.BUFGLS.H4	1	0	1	1	1	0	1
1.BUFGLS.H5	1	0	1	1	1	1	0
1.BUFGLS.H2	1	1	0	1	1	0	1
1.BUFGLS.H3	1	1	0	1	1	1	0
1.BUFGLS.H6	1	1	1	0	1	0	1
1.BUFGLS.H7	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK1	0.1.1	0.3.1	0.3.0	0.2.1	0.2.0	0.0.0	0.0.1
0.QUAD.V0.4	0	0	1	1	1	1	1
0.VCLK	0	1	0	1	1	1	1
1.SINGLE.V1	0	1	1	0	1	1	1
1.VCLK	0	1	1	1	0	1	1
1.BUFGLS.H4	1	0	1	1	1	0	1
1.BUFGLS.H5	1	0	1	1	1	1	0
1.BUFGLS.H2	1	1	0	1	1	0	1
1.BUFGLS.H3	1	1	0	1	1	1	0
1.BUFGLS.H6	1	1	1	0	1	0	1
1.BUFGLS.H7	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK2	0.11.1	0.13.0	0.12.1	0.13.1	0.12.0	0.10.0	0.10.1
0.VCLK	0	0	1	1	1	1	1
1.SINGLE.V2	0	1	0	1	1	1	1
1.QUAD.V0.0	0	1	1	0	1	1	1
1.VCLK	0	1	1	1	0	1	1
1.BUFGLS.H2	1	0	1	1	1	0	1
1.BUFGLS.H3	1	0	1	1	1	1	0
1.BUFGLS.H6	1	1	0	1	1	0	1
1.BUFGLS.H7	1	1	0	1	1	1	0
1.BUFGLS.H4	1	1	1	0	1	0	1
1.BUFGLS.H5	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK3	0.6.1	0.8.1	0.8.0	0.7.1	0.7.0	0.5.0	0.5.1
0.QUAD.V1.4	0	0	1	1	1	1	1
0.VCLK	0	1	0	1	1	1	1
1.SINGLE.V3	0	1	1	0	1	1	1
1.VCLK	0	1	1	1	0	1	1
1.BUFGLS.H4	1	0	1	1	1	0	1
1.BUFGLS.H5	1	0	1	1	1	1	0
1.BUFGLS.H2	1	1	0	1	1	0	1
1.BUFGLS.H3	1	1	0	1	1	1	0
1.BUFGLS.H6	1	1	1	0	1	0	1
1.BUFGLS.H7	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK4	0.39.1	0.41.0	0.40.1	0.41.1	0.40.0	0.39.0	0.38.1
0.VCLK	0	0	1	1	1	1	1
1.SINGLE.V4	0	1	0	1	1	1	1
1.QUAD.V1.0	0	1	1	0	1	1	1
1.VCLK	0	1	1	1	0	1	1
1.BUFGLS.H2	1	0	1	1	1	0	1
1.BUFGLS.H3	1	0	1	1	1	1	0
1.BUFGLS.H6	1	1	0	1	1	0	1
1.BUFGLS.H7	1	1	0	1	1	1	0
1.BUFGLS.H4	1	1	1	0	1	0	1
1.BUFGLS.H5	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK5	0.33.1	0.35.1	0.35.0	0.34.1	0.34.0	0.33.0	0.32.1
0.QUAD.V2.3	0	0	1	1	1	1	1
0.VCLK	0	1	0	1	1	1	1
1.SINGLE.V5	0	1	1	0	1	1	1
1.VCLK	0	1	1	1	0	1	1
1.BUFGLS.H4	1	0	1	1	1	0	1
1.BUFGLS.H5	1	0	1	1	1	1	0
1.BUFGLS.H2	1	1	0	1	1	0	1
1.BUFGLS.H3	1	1	0	1	1	1	0
1.BUFGLS.H6	1	1	1	0	1	0	1
1.BUFGLS.H7	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK6	0.22.1	0.24.1	0.24.0	0.23.1	0.23.0	0.21.0	0.21.1
0.QUAD.V2.4	0	0	1	1	1	1	1
0.VCLK	0	1	0	1	1	1	1
1.SINGLE.V6	0	1	1	0	1	1	1
1.VCLK	0	1	1	1	0	1	1
1.BUFGLS.H4	1	0	1	1	1	0	1
1.BUFGLS.H5	1	0	1	1	1	1	0
1.BUFGLS.H2	1	1	0	1	1	0	1
1.BUFGLS.H3	1	1	0	1	1	1	0
1.BUFGLS.H6	1	1	1	0	1	0	1
1.BUFGLS.H7	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK7	0.17.1	0.19.0	0.18.1	0.19.1	0.18.0	0.16.0	0.16.1
0.VCLK	0	0	1	1	1	1	1
1.SINGLE.V7	0	1	0	1	1	1	1
1.QUAD.V2.0	0	1	1	0	1	1	1
1.VCLK	0	1	1	1	0	1	1
1.BUFGLS.H2	1	0	1	1	1	0	1
1.BUFGLS.H3	1	0	1	1	1	1	0
1.BUFGLS.H6	1	1	0	1	1	0	1
1.BUFGLS.H7	1	1	0	1	1	1	0
1.BUFGLS.H4	1	1	1	0	1	0	1
1.BUFGLS.H5	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.LONG.V9	0.36.0	0.36.1
1.LONG.V9	0	0
1.VCLK	0	1
NONE	1	1

LLV:MUX.1.LONG.V7	0.45.0	0.43.1
0.LONG.V7	0	0
0.VCLK	0	1
NONE	1	1

Tile LLVQ.IO.L.B

Cells: 2

Bel BUFF

xc4000ex LLVQ.IO.L.B bel BUFF
Pin	Direction	Wires
O	output	TCELL1:OUT.BUFF

Bel LLV

Switchbox LLV

xc4000ex LLVQ.IO.L.B switchbox LLV
Destination	Source	Kind
TCELL0_IO.DOUBLE.0.W.1	TCELL0_ECLK.V	pass transistor
TCELL0_IO.DOUBLE.1.W.1	TCELL0_ECLK.V	pass transistor
TCELL0_IO.DOUBLE.1.W.2	TCELL0_ECLK.V	pass transistor
TCELL0_IO.DOUBLE.2.W.1	TCELL0_ECLK.V	pass transistor
TCELL0_IO.DOUBLE.3.W.2	TCELL0_ECLK.V	pass transistor
TCELL0_LONG.IO.V0	TCELL1_LONG.IO.V0	buffer
TCELL0_LONG.IO.V1	TCELL1_LONG.IO.V1	buffer
TCELL0_LONG.IO.V2	TCELL1_LONG.IO.V2	buffer
TCELL0_LONG.IO.V3	TCELL1_LONG.IO.V3	buffer
TCELL0_GCLK0	TCELL0_IO.DOUBLE.0.W.1	mux
	TCELL0_IO.DOUBLE.2.W.1	mux
	TCELL0_BUFGE.V1	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
	TCELL1_OUT.BUFF	mux
TCELL0_GCLK1	TCELL0_IO.DOUBLE.0.W.2	mux
	TCELL0_IO.DOUBLE.2.W.2	mux
	TCELL0_ECLK.V	mux
	TCELL0_BUFGE.V0	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK2	TCELL0_IO.DOUBLE.1.W.1	mux
	TCELL0_IO.DOUBLE.3.W.1	mux
	TCELL0_ECLK.V	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
	TCELL1_OUT.BUFF	mux
TCELL0_GCLK3	TCELL0_IO.DOUBLE.1.W.2	mux
	TCELL0_IO.DOUBLE.3.W.2	mux
	TCELL0_BUFGE.V0	mux
	TCELL0_BUFGE.V1	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL1_LONG.IO.V0	TCELL0_LONG.IO.V0	buffer
TCELL1_LONG.IO.V1	TCELL0_LONG.IO.V1	buffer
TCELL1_LONG.IO.V2	TCELL0_LONG.IO.V2	buffer
TCELL1_LONG.IO.V3	TCELL0_LONG.IO.V3	buffer

Bel wires

xc4000ex LLVQ.IO.L.B bel wires
Wire	Pins
TCELL1:OUT.BUFF	BUFF.O

Bitstream

xc4000ex LLVQ.IO.L.B bittile 0
Bit	Frame
Bit	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	LLV:MUX.0.GCLK1[5]	LLV:MUX.0.GCLK1[4]	LLV:MUX.0.GCLK1[6]	LLV:MUX.0.GCLK1[0]	LLV:MUX.0.GCLK3[4]	LLV:MUX.0.GCLK3[5]	LLV:MUX.0.GCLK3[6]	LLV:MUX.0.GCLK3[0]	LLV:MUX.0.GCLK0[5]	LLV:MUX.0.GCLK0[4]	LLV:MUX.0.GCLK0[6]	LLV:MUX.0.GCLK0[0]	LLV:MUX.0.GCLK2[4]	LLV:MUX.0.GCLK2[5]	LLV:MUX.0.GCLK2[6]	LLV:MUX.0.GCLK2[0]	-	~LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1	~LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3	~LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0	~LLV:PASS.0.IO.DOUBLE.2.W.1.0.ECLK.V	~LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2	-	-	-	-	-
0	LLV:MUX.0.GCLK1[3]	LLV:MUX.0.GCLK1[2]	LLV:MUX.0.GCLK1[1]	~LLV:PASS.0.IO.DOUBLE.3.W.2.0.ECLK.V	LLV:MUX.0.GCLK3[2]	LLV:MUX.0.GCLK3[3]	LLV:MUX.0.GCLK3[1]	~LLV:PASS.0.IO.DOUBLE.1.W.2.0.ECLK.V	LLV:MUX.0.GCLK0[3]	LLV:MUX.0.GCLK0[2]	LLV:MUX.0.GCLK0[1]	~LLV:PASS.0.IO.DOUBLE.0.W.1.0.ECLK.V	LLV:MUX.0.GCLK2[3]	LLV:MUX.0.GCLK2[2]	LLV:MUX.0.GCLK2[1]	~LLV:PASS.0.IO.DOUBLE.1.W.1.0.ECLK.V	-	~LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1	~LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3	~LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0	-	~LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2	-	-	-	-	-

LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0	0.7.1
LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1	0.9.1
LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2	0.5.1
LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3	0.8.1
LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0	0.7.0
LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1	0.9.0
LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2	0.5.0
LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3	0.8.0
LLV:PASS.0.IO.DOUBLE.0.W.1.0.ECLK.V	0.15.0
LLV:PASS.0.IO.DOUBLE.1.W.1.0.ECLK.V	0.11.0
LLV:PASS.0.IO.DOUBLE.1.W.2.0.ECLK.V	0.19.0
LLV:PASS.0.IO.DOUBLE.2.W.1.0.ECLK.V	0.6.1
LLV:PASS.0.IO.DOUBLE.3.W.2.0.ECLK.V	0.23.0
inverted	~[0]

LLV:MUX.0.GCLK0	0.16.1	0.18.1	0.17.1	0.18.0	0.17.0	0.16.0	0.15.1
0.IO.DOUBLE.0.W.1	0	0	1	1	1	1	1
0.IO.DOUBLE.2.W.1	0	1	0	1	1	1	1
0.BUFGE.V1	0	1	1	0	1	1	1
1.OUT.BUFF	0	1	1	1	0	1	1
1.BUFGLS.H4	1	0	1	1	1	0	1
1.BUFGLS.H5	1	0	1	1	1	1	0
1.BUFGLS.H6	1	1	0	1	1	0	1
1.BUFGLS.H7	1	1	0	1	1	1	0
1.BUFGLS.H2	1	1	1	0	1	0	1
1.BUFGLS.H3	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK1	0.24.1	0.26.1	0.25.1	0.26.0	0.25.0	0.24.0	0.23.1
0.IO.DOUBLE.0.W.2	0	0	1	1	1	1	1
0.IO.DOUBLE.2.W.2	0	1	0	1	1	1	1
0.ECLK.V	0	1	1	0	1	1	1
0.BUFGE.V0	0	1	1	1	0	1	1
1.BUFGLS.H4	1	0	1	1	1	0	1
1.BUFGLS.H5	1	0	1	1	1	1	0
1.BUFGLS.H6	1	1	0	1	1	0	1
1.BUFGLS.H7	1	1	0	1	1	1	0
1.BUFGLS.H2	1	1	1	0	1	0	1
1.BUFGLS.H3	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK2	0.12.1	0.13.1	0.14.1	0.14.0	0.13.0	0.12.0	0.11.1
0.IO.DOUBLE.1.W.1	0	0	1	1	1	1	1
0.IO.DOUBLE.3.W.1	0	1	0	1	1	1	1
0.ECLK.V	0	1	1	0	1	1	1
1.OUT.BUFF	0	1	1	1	0	1	1
1.BUFGLS.H6	1	0	1	1	1	0	1
1.BUFGLS.H7	1	0	1	1	1	1	0
1.BUFGLS.H4	1	1	0	1	1	0	1
1.BUFGLS.H5	1	1	0	1	1	1	0
1.BUFGLS.H2	1	1	1	0	1	0	1
1.BUFGLS.H3	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK3	0.20.1	0.21.1	0.22.1	0.21.0	0.22.0	0.20.0	0.19.1
0.IO.DOUBLE.1.W.2	0	0	1	1	1	1	1
0.IO.DOUBLE.3.W.2	0	1	0	1	1	1	1
0.BUFGE.V0	0	1	1	0	1	1	1
0.BUFGE.V1	0	1	1	1	0	1	1
1.BUFGLS.H6	1	0	1	1	1	0	1
1.BUFGLS.H7	1	0	1	1	1	1	0
1.BUFGLS.H4	1	1	0	1	1	0	1
1.BUFGLS.H5	1	1	0	1	1	1	0
1.BUFGLS.H0	1	1	1	0	1	0	1
1.BUFGLS.H1	1	1	1	0	1	1	0
1.BUFGLS.H2	1	1	1	1	0	0	1
1.BUFGLS.H3	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

Tile LLVQ.IO.L.T

Cells: 2

Bel BUFF

xc4000ex LLVQ.IO.L.T bel BUFF
Pin	Direction	Wires
O	output	TCELL1:OUT.BUFF

Bel LLV

Switchbox LLV

xc4000ex LLVQ.IO.L.T switchbox LLV
Destination	Source	Kind
TCELL0_IO.DOUBLE.0.W.1	TCELL1_ECLK.V	pass transistor
TCELL0_IO.DOUBLE.1.W.1	TCELL1_ECLK.V	pass transistor
TCELL0_IO.DOUBLE.1.W.2	TCELL1_ECLK.V	pass transistor
TCELL0_IO.DOUBLE.2.W.1	TCELL1_ECLK.V	pass transistor
TCELL0_IO.DOUBLE.3.W.2	TCELL1_ECLK.V	pass transistor
TCELL0_LONG.IO.V0	TCELL1_LONG.IO.V0	buffer
TCELL0_LONG.IO.V1	TCELL1_LONG.IO.V1	buffer
TCELL0_LONG.IO.V2	TCELL1_LONG.IO.V2	buffer
TCELL0_LONG.IO.V3	TCELL1_LONG.IO.V3	buffer
TCELL0_GCLK0	TCELL0_IO.DOUBLE.0.W.1	mux
	TCELL0_IO.DOUBLE.2.W.1	mux
	TCELL0_BUFGE.V0	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
	TCELL1_OUT.BUFF	mux
TCELL0_GCLK1	TCELL0_IO.DOUBLE.0.W.2	mux
	TCELL0_IO.DOUBLE.2.W.2	mux
	TCELL0_BUFGE.V1	mux
	TCELL1_ECLK.V	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK2	TCELL0_IO.DOUBLE.1.W.1	mux
	TCELL0_IO.DOUBLE.3.W.1	mux
	TCELL1_ECLK.V	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
	TCELL1_OUT.BUFF	mux
TCELL0_GCLK3	TCELL0_IO.DOUBLE.1.W.2	mux
	TCELL0_IO.DOUBLE.3.W.2	mux
	TCELL0_BUFGE.V0	mux
	TCELL0_BUFGE.V1	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL1_LONG.IO.V0	TCELL0_LONG.IO.V0	buffer
TCELL1_LONG.IO.V1	TCELL0_LONG.IO.V1	buffer
TCELL1_LONG.IO.V2	TCELL0_LONG.IO.V2	buffer
TCELL1_LONG.IO.V3	TCELL0_LONG.IO.V3	buffer

Bel wires

xc4000ex LLVQ.IO.L.T bel wires
Wire	Pins
TCELL1:OUT.BUFF	BUFF.O

Bitstream

xc4000ex LLVQ.IO.L.T bittile 0
Bit	Frame
Bit	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	LLV:MUX.0.GCLK1[5]	LLV:MUX.0.GCLK1[4]	LLV:MUX.0.GCLK1[6]	LLV:MUX.0.GCLK1[0]	LLV:MUX.0.GCLK3[4]	LLV:MUX.0.GCLK3[5]	LLV:MUX.0.GCLK3[6]	LLV:MUX.0.GCLK3[0]	LLV:MUX.0.GCLK0[5]	LLV:MUX.0.GCLK0[4]	LLV:MUX.0.GCLK0[6]	LLV:MUX.0.GCLK0[0]	LLV:MUX.0.GCLK2[4]	LLV:MUX.0.GCLK2[5]	LLV:MUX.0.GCLK2[6]	LLV:MUX.0.GCLK2[0]	-	~LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1	~LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3	~LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0	~LLV:PASS.0.IO.DOUBLE.2.W.1.1.ECLK.V	~LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2	-	-	-	-	-
0	LLV:MUX.0.GCLK1[2]	LLV:MUX.0.GCLK1[3]	LLV:MUX.0.GCLK1[1]	~LLV:PASS.0.IO.DOUBLE.3.W.2.1.ECLK.V	LLV:MUX.0.GCLK3[3]	LLV:MUX.0.GCLK3[2]	LLV:MUX.0.GCLK3[1]	~LLV:PASS.0.IO.DOUBLE.1.W.2.1.ECLK.V	LLV:MUX.0.GCLK0[3]	LLV:MUX.0.GCLK0[2]	LLV:MUX.0.GCLK0[1]	~LLV:PASS.0.IO.DOUBLE.0.W.1.1.ECLK.V	LLV:MUX.0.GCLK2[3]	LLV:MUX.0.GCLK2[2]	LLV:MUX.0.GCLK2[1]	~LLV:PASS.0.IO.DOUBLE.1.W.1.1.ECLK.V	-	~LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1	~LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3	~LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0	-	~LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2	-	-	-	-	-

LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0	0.7.1
LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1	0.9.1
LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2	0.5.1
LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3	0.8.1
LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0	0.7.0
LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1	0.9.0
LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2	0.5.0
LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3	0.8.0
LLV:PASS.0.IO.DOUBLE.0.W.1.1.ECLK.V	0.15.0
LLV:PASS.0.IO.DOUBLE.1.W.1.1.ECLK.V	0.11.0
LLV:PASS.0.IO.DOUBLE.1.W.2.1.ECLK.V	0.19.0
LLV:PASS.0.IO.DOUBLE.2.W.1.1.ECLK.V	0.6.1
LLV:PASS.0.IO.DOUBLE.3.W.2.1.ECLK.V	0.23.0
inverted	~[0]

LLV:MUX.0.GCLK0	0.16.1	0.18.1	0.17.1	0.18.0	0.17.0	0.16.0	0.15.1
0.IO.DOUBLE.0.W.1	0	0	1	1	1	1	1
0.IO.DOUBLE.2.W.1	0	1	0	1	1	1	1
0.BUFGE.V0	0	1	1	0	1	1	1
1.OUT.BUFF	0	1	1	1	0	1	1
1.BUFGLS.H4	1	0	1	1	1	0	1
1.BUFGLS.H5	1	0	1	1	1	1	0
1.BUFGLS.H6	1	1	0	1	1	0	1
1.BUFGLS.H7	1	1	0	1	1	1	0
1.BUFGLS.H2	1	1	1	0	1	0	1
1.BUFGLS.H3	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK1	0.24.1	0.26.1	0.25.1	0.25.0	0.26.0	0.24.0	0.23.1
0.IO.DOUBLE.0.W.2	0	0	1	1	1	1	1
0.IO.DOUBLE.2.W.2	0	1	0	1	1	1	1
0.BUFGE.V1	0	1	1	0	1	1	1
1.ECLK.V	0	1	1	1	0	1	1
1.BUFGLS.H4	1	0	1	1	1	0	1
1.BUFGLS.H5	1	0	1	1	1	1	0
1.BUFGLS.H6	1	1	0	1	1	0	1
1.BUFGLS.H7	1	1	0	1	1	1	0
1.BUFGLS.H0	1	1	1	0	1	0	1
1.BUFGLS.H1	1	1	1	0	1	1	0
1.BUFGLS.H2	1	1	1	1	0	0	1
1.BUFGLS.H3	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK2	0.12.1	0.13.1	0.14.1	0.14.0	0.13.0	0.12.0	0.11.1
0.IO.DOUBLE.1.W.1	0	0	1	1	1	1	1
0.IO.DOUBLE.3.W.1	0	1	0	1	1	1	1
1.ECLK.V	0	1	1	0	1	1	1
1.OUT.BUFF	0	1	1	1	0	1	1
1.BUFGLS.H6	1	0	1	1	1	0	1
1.BUFGLS.H7	1	0	1	1	1	1	0
1.BUFGLS.H4	1	1	0	1	1	0	1
1.BUFGLS.H5	1	1	0	1	1	1	0
1.BUFGLS.H2	1	1	1	0	1	0	1
1.BUFGLS.H3	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK3	0.20.1	0.21.1	0.22.1	0.22.0	0.21.0	0.20.0	0.19.1
0.IO.DOUBLE.1.W.2	0	0	1	1	1	1	1
0.IO.DOUBLE.3.W.2	0	1	0	1	1	1	1
0.BUFGE.V0	0	1	1	0	1	1	1
0.BUFGE.V1	0	1	1	1	0	1	1
1.BUFGLS.H6	1	0	1	1	1	0	1
1.BUFGLS.H7	1	0	1	1	1	1	0
1.BUFGLS.H4	1	1	0	1	1	0	1
1.BUFGLS.H5	1	1	0	1	1	1	0
1.BUFGLS.H2	1	1	1	0	1	0	1
1.BUFGLS.H3	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

Tile LLVQ.IO.R.B

Cells: 2

Bel BUFF

xc4000ex LLVQ.IO.R.B bel BUFF
Pin	Direction	Wires
O	output	TCELL1:OUT.BUFF

Bel LLV

Switchbox LLV

xc4000ex LLVQ.IO.R.B switchbox LLV
Destination	Source	Kind
TCELL0_IO.DOUBLE.0.E.1	TCELL0_ECLK.V	pass transistor
TCELL0_IO.DOUBLE.1.E.0	TCELL0_ECLK.V	pass transistor
TCELL0_IO.DOUBLE.1.E.1	TCELL0_ECLK.V	pass transistor
TCELL0_IO.DOUBLE.2.E.1	TCELL0_ECLK.V	pass transistor
TCELL0_IO.DOUBLE.3.E.0	TCELL0_ECLK.V	pass transistor
TCELL0_QUAD.V1.4	TCELL0_VCLK	pass transistor
TCELL0_QUAD.V2.4	TCELL1_VCLK	pass transistor
TCELL0_LONG.V0	TCELL1_LONG.V0	buffer
TCELL0_LONG.V1	TCELL1_LONG.V1	buffer
TCELL0_LONG.V2	TCELL1_LONG.V2	buffer
TCELL0_LONG.V3	TCELL1_LONG.V3	buffer
TCELL0_LONG.V4	TCELL1_LONG.V4	buffer
TCELL0_LONG.V5	TCELL1_LONG.V5	buffer
TCELL0_LONG.V6	TCELL1_LONG.V6	buffer
TCELL0_LONG.V7	TCELL1_LONG.V7.EXCL	mux
TCELL0_LONG.V8	TCELL1_LONG.V8	buffer
TCELL0_LONG.V9	TCELL1_LONG.V9.EXCL	mux
TCELL0_LONG.IO.V0	TCELL1_LONG.IO.V0	buffer
TCELL0_LONG.IO.V1	TCELL1_LONG.IO.V1	buffer
TCELL0_LONG.IO.V2	TCELL1_LONG.IO.V2	buffer
TCELL0_LONG.IO.V3	TCELL1_LONG.IO.V3	buffer
TCELL0_GCLK0	TCELL0_IO.DOUBLE.0.E.1	mux
	TCELL0_IO.DOUBLE.2.E.1	mux
	TCELL0_BUFGE.V1	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
	TCELL1_OUT.BUFF	mux
TCELL0_GCLK1	TCELL0_IO.DOUBLE.0.E.0	mux
	TCELL0_IO.DOUBLE.2.E.0	mux
	TCELL0_ECLK.V	mux
	TCELL0_BUFGE.V0	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK2	TCELL0_IO.DOUBLE.1.E.1	mux
	TCELL0_IO.DOUBLE.3.E.1	mux
	TCELL0_ECLK.V	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
	TCELL1_OUT.BUFF	mux
TCELL0_GCLK3	TCELL0_IO.DOUBLE.1.E.0	mux
	TCELL0_IO.DOUBLE.3.E.0	mux
	TCELL0_BUFGE.V0	mux
	TCELL0_BUFGE.V1	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK4	TCELL0_VCLK	mux
	TCELL1_SINGLE.V4	mux
	TCELL1_QUAD.V1.0	mux
	TCELL1_VCLK	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK5	TCELL0_QUAD.V2.3	mux
	TCELL0_VCLK	mux
	TCELL1_SINGLE.V5	mux
	TCELL1_VCLK	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK6	TCELL0_QUAD.V2.4	mux
	TCELL0_VCLK	mux
	TCELL1_SINGLE.V6	mux
	TCELL1_VCLK	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK7	TCELL0_VCLK	mux
	TCELL1_SINGLE.V7	mux
	TCELL1_QUAD.V2.0	mux
	TCELL1_VCLK	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL1_SINGLE.V0	TCELL0_VCLK	pass transistor
TCELL1_SINGLE.V1	TCELL1_VCLK	pass transistor
TCELL1_SINGLE.V2	TCELL0_VCLK	pass transistor
TCELL1_SINGLE.V3	TCELL1_VCLK	pass transistor
TCELL1_SINGLE.V4	TCELL0_VCLK	pass transistor
TCELL1_SINGLE.V5	TCELL1_VCLK	pass transistor
TCELL1_SINGLE.V6	TCELL0_VCLK	pass transistor
TCELL1_SINGLE.V7	TCELL1_VCLK	pass transistor
TCELL1_QUAD.V0.0	TCELL1_VCLK	pass transistor
TCELL1_QUAD.V2.0	TCELL0_VCLK	pass transistor
TCELL1_LONG.V0	TCELL0_LONG.V0	buffer
TCELL1_LONG.V1	TCELL0_LONG.V1	buffer
TCELL1_LONG.V2	TCELL0_LONG.V2	buffer
TCELL1_LONG.V3	TCELL0_LONG.V3	buffer
TCELL1_LONG.V4	TCELL0_LONG.V4	buffer
TCELL1_LONG.V5	TCELL0_LONG.V5	buffer
TCELL1_LONG.V6	TCELL0_LONG.V6	buffer
TCELL1_LONG.V7	TCELL1_LONG.V7.EXCL	mux
TCELL1_LONG.V7.EXCL	TCELL0_LONG.V7	mux
	TCELL0_VCLK	mux
	TCELL1_LONG.V7	mux
TCELL1_LONG.V8	TCELL0_LONG.V8	buffer
TCELL1_LONG.V9	TCELL1_LONG.V9.EXCL	mux
TCELL1_LONG.V9.EXCL	TCELL0_LONG.V9	mux
	TCELL1_LONG.V9	mux
	TCELL1_VCLK	mux
TCELL1_LONG.IO.V0	TCELL0_LONG.IO.V0	buffer
TCELL1_LONG.IO.V1	TCELL0_LONG.IO.V1	buffer
TCELL1_LONG.IO.V2	TCELL0_LONG.IO.V2	buffer
TCELL1_LONG.IO.V3	TCELL0_LONG.IO.V3	buffer

Bel wires

xc4000ex LLVQ.IO.R.B bel wires
Wire	Pins
TCELL1:OUT.BUFF	BUFF.O

Bitstream

xc4000ex LLVQ.IO.R.B bittile 0
Bit	Frame
Bit	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	LLV:MUX.0.GCLK4[3]	LLV:MUX.0.GCLK4[4]	LLV:MUX.0.GCLK4[6]	LLV:MUX.0.GCLK4[0]	LLV:MUX.0.GCLK5[5]	LLV:MUX.0.GCLK5[3]	LLV:MUX.0.GCLK5[6]	LLV:MUX.0.GCLK5[0]	LLV:MUX.0.GCLK6[5]	LLV:MUX.0.GCLK6[3]	LLV:MUX.0.GCLK6[6]	LLV:MUX.0.GCLK6[0]	LLV:MUX.0.GCLK7[3]	LLV:MUX.0.GCLK7[4]	LLV:MUX.0.GCLK7[6]	LLV:MUX.0.GCLK7[0]	~LLV:BUF.0.LONG.V5.1.LONG.V5	~LLV:BUF.0.LONG.V3.1.LONG.V3	~LLV:BUF.0.LONG.V2.1.LONG.V2	~LLV:PASS.1.QUAD.V2.0.0.VCLK	~LLV:BUF.0.LONG.V0.1.LONG.V0	~LLV:PASS.0.QUAD.V1.4.0.VCLK	~LLV:BUF.0.LONG.V4.1.LONG.V4	~LLV:PASS.1.SINGLE.V3.1.VCLK	~LLV:BUF.0.LONG.V1.1.LONG.V1	~LLV:BUF.0.LONG.V6.1.LONG.V6	~LLV:BUF.0.LONG.V7.1.LONG.V7	LLV:MUX.1.LONG.V7[0]	~LLV:BUF.0.LONG.V8.1.LONG.V8	~LLV:BUF.1.LONG.V9.0.LONG.V9	LLV:MUX.0.LONG.V9[0]	~LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0	~LLV:PASS.0.IO.DOUBLE.3.E.0.0.ECLK.V	~LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2	~LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3	~LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1	LLV:MUX.0.GCLK2[4]	LLV:MUX.0.GCLK2[5]	LLV:MUX.0.GCLK2[6]	LLV:MUX.0.GCLK2[0]	LLV:MUX.0.GCLK0[5]	LLV:MUX.0.GCLK0[4]	LLV:MUX.0.GCLK0[6]	LLV:MUX.0.GCLK0[0]	LLV:MUX.0.GCLK1[5]	LLV:MUX.0.GCLK1[4]	LLV:MUX.0.GCLK1[6]	LLV:MUX.0.GCLK1[0]	LLV:MUX.0.GCLK3[4]	LLV:MUX.0.GCLK3[5]	LLV:MUX.0.GCLK3[6]	LLV:MUX.0.GCLK3[0]
0	LLV:MUX.0.GCLK4[5]	LLV:MUX.0.GCLK4[2]	LLV:MUX.0.GCLK4[1]	~LLV:PASS.1.SINGLE.V4.0.VCLK	LLV:MUX.0.GCLK5[4]	LLV:MUX.0.GCLK5[2]	~LLV:PASS.1.SINGLE.V5.1.VCLK	LLV:MUX.0.GCLK5[1]	LLV:MUX.0.GCLK6[4]	LLV:MUX.0.GCLK6[2]	~LLV:PASS.1.SINGLE.V6.0.VCLK	LLV:MUX.0.GCLK6[1]	LLV:MUX.0.GCLK7[5]	LLV:MUX.0.GCLK7[2]	LLV:MUX.0.GCLK7[1]	~LLV:PASS.1.SINGLE.V7.1.VCLK	~LLV:BUF.1.LONG.V5.0.LONG.V5	~LLV:BUF.1.LONG.V3.0.LONG.V3	~LLV:BUF.1.LONG.V2.0.LONG.V2	~LLV:PASS.0.QUAD.V2.4.1.VCLK	~LLV:BUF.1.LONG.V0.0.LONG.V0	~LLV:PASS.1.QUAD.V0.0.1.VCLK	~LLV:BUF.1.LONG.V4.0.LONG.V4	~LLV:PASS.1.SINGLE.V2.0.VCLK	~LLV:BUF.1.LONG.V1.0.LONG.V1	~LLV:BUF.1.LONG.V6.0.LONG.V6	LLV:MUX.1.LONG.V7[1]	~LLV:PASS.1.SINGLE.V0.0.VCLK	~LLV:BUF.1.LONG.V8.0.LONG.V8	LLV:MUX.0.LONG.V9[1]	~LLV:PASS.1.SINGLE.V1.1.VCLK	~LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0	~LLV:PASS.0.IO.DOUBLE.0.E.1.0.ECLK.V	~LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2	~LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3	~LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1	LLV:MUX.0.GCLK2[3]	LLV:MUX.0.GCLK2[2]	-	LLV:MUX.0.GCLK2[1]	LLV:MUX.0.GCLK0[3]	LLV:MUX.0.GCLK0[2]	~LLV:PASS.0.IO.DOUBLE.1.E.0.0.ECLK.V	LLV:MUX.0.GCLK0[1]	LLV:MUX.0.GCLK1[3]	LLV:MUX.0.GCLK1[2]	~LLV:PASS.0.IO.DOUBLE.1.E.1.0.ECLK.V	LLV:MUX.0.GCLK1[1]	LLV:MUX.0.GCLK3[2]	LLV:MUX.0.GCLK3[3]	~LLV:PASS.0.IO.DOUBLE.2.E.1.0.ECLK.V	LLV:MUX.0.GCLK3[1]

LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0	0.20.1
LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1	0.16.1
LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2	0.18.1
LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3	0.17.1
LLV:BUF.0.LONG.V0.1.LONG.V0	0.31.1
LLV:BUF.0.LONG.V1.1.LONG.V1	0.27.1
LLV:BUF.0.LONG.V2.1.LONG.V2	0.33.1
LLV:BUF.0.LONG.V3.1.LONG.V3	0.34.1
LLV:BUF.0.LONG.V4.1.LONG.V4	0.29.1
LLV:BUF.0.LONG.V5.1.LONG.V5	0.35.1
LLV:BUF.0.LONG.V6.1.LONG.V6	0.26.1
LLV:BUF.0.LONG.V7.1.LONG.V7	0.25.1
LLV:BUF.0.LONG.V8.1.LONG.V8	0.23.1
LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0	0.20.0
LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1	0.16.0
LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2	0.18.0
LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3	0.17.0
LLV:BUF.1.LONG.V0.0.LONG.V0	0.31.0
LLV:BUF.1.LONG.V1.0.LONG.V1	0.27.0
LLV:BUF.1.LONG.V2.0.LONG.V2	0.33.0
LLV:BUF.1.LONG.V3.0.LONG.V3	0.34.0
LLV:BUF.1.LONG.V4.0.LONG.V4	0.29.0
LLV:BUF.1.LONG.V5.0.LONG.V5	0.35.0
LLV:BUF.1.LONG.V6.0.LONG.V6	0.26.0
LLV:BUF.1.LONG.V8.0.LONG.V8	0.23.0
LLV:BUF.1.LONG.V9.0.LONG.V9	0.22.1
LLV:PASS.0.IO.DOUBLE.0.E.1.0.ECLK.V	0.19.0
LLV:PASS.0.IO.DOUBLE.1.E.0.0.ECLK.V	0.9.0
LLV:PASS.0.IO.DOUBLE.1.E.1.0.ECLK.V	0.5.0
LLV:PASS.0.IO.DOUBLE.2.E.1.0.ECLK.V	0.1.0
LLV:PASS.0.IO.DOUBLE.3.E.0.0.ECLK.V	0.19.1
LLV:PASS.0.QUAD.V1.4.0.VCLK	0.30.1
LLV:PASS.0.QUAD.V2.4.1.VCLK	0.32.0
LLV:PASS.1.QUAD.V0.0.1.VCLK	0.30.0
LLV:PASS.1.QUAD.V2.0.0.VCLK	0.32.1
LLV:PASS.1.SINGLE.V0.0.VCLK	0.24.0
LLV:PASS.1.SINGLE.V1.1.VCLK	0.21.0
LLV:PASS.1.SINGLE.V2.0.VCLK	0.28.0
LLV:PASS.1.SINGLE.V3.1.VCLK	0.28.1
LLV:PASS.1.SINGLE.V4.0.VCLK	0.48.0
LLV:PASS.1.SINGLE.V5.1.VCLK	0.45.0
LLV:PASS.1.SINGLE.V6.0.VCLK	0.41.0
LLV:PASS.1.SINGLE.V7.1.VCLK	0.36.0
inverted	~[0]

LLV:MUX.0.GCLK0	0.9.1	0.11.1	0.10.1	0.11.0	0.10.0	0.8.0	0.8.1
0.IO.DOUBLE.0.E.1	0	0	1	1	1	1	1
0.IO.DOUBLE.2.E.1	0	1	0	1	1	1	1
0.BUFGE.V1	0	1	1	0	1	1	1
1.OUT.BUFF	0	1	1	1	0	1	1
1.BUFGLS.H4	1	0	1	1	1	0	1
1.BUFGLS.H5	1	0	1	1	1	1	0
1.BUFGLS.H6	1	1	0	1	1	0	1
1.BUFGLS.H7	1	1	0	1	1	1	0
1.BUFGLS.H2	1	1	1	0	1	0	1
1.BUFGLS.H3	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK1	0.5.1	0.7.1	0.6.1	0.7.0	0.6.0	0.4.0	0.4.1
0.IO.DOUBLE.0.E.0	0	0	1	1	1	1	1
0.IO.DOUBLE.2.E.0	0	1	0	1	1	1	1
0.ECLK.V	0	1	1	0	1	1	1
0.BUFGE.V0	0	1	1	1	0	1	1
1.BUFGLS.H4	1	0	1	1	1	0	1
1.BUFGLS.H5	1	0	1	1	1	1	0
1.BUFGLS.H6	1	1	0	1	1	0	1
1.BUFGLS.H7	1	1	0	1	1	1	0
1.BUFGLS.H2	1	1	1	0	1	0	1
1.BUFGLS.H3	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK2	0.13.1	0.14.1	0.15.1	0.15.0	0.14.0	0.12.0	0.12.1
0.IO.DOUBLE.1.E.1	0	0	1	1	1	1	1
0.IO.DOUBLE.3.E.1	0	1	0	1	1	1	1
0.ECLK.V	0	1	1	0	1	1	1
1.OUT.BUFF	0	1	1	1	0	1	1
1.BUFGLS.H6	1	0	1	1	1	0	1
1.BUFGLS.H7	1	0	1	1	1	1	0
1.BUFGLS.H4	1	1	0	1	1	0	1
1.BUFGLS.H5	1	1	0	1	1	1	0
1.BUFGLS.H2	1	1	1	0	1	0	1
1.BUFGLS.H3	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK3	0.1.1	0.2.1	0.3.1	0.2.0	0.3.0	0.0.0	0.0.1
0.IO.DOUBLE.1.E.0	0	0	1	1	1	1	1
0.IO.DOUBLE.3.E.0	0	1	0	1	1	1	1
0.BUFGE.V0	0	1	1	0	1	1	1
0.BUFGE.V1	0	1	1	1	0	1	1
1.BUFGLS.H6	1	0	1	1	1	0	1
1.BUFGLS.H7	1	0	1	1	1	1	0
1.BUFGLS.H4	1	1	0	1	1	0	1
1.BUFGLS.H5	1	1	0	1	1	1	0
1.BUFGLS.H0	1	1	1	0	1	0	1
1.BUFGLS.H1	1	1	1	0	1	1	0
1.BUFGLS.H2	1	1	1	1	0	0	1
1.BUFGLS.H3	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK4	0.49.1	0.51.0	0.50.1	0.51.1	0.50.0	0.49.0	0.48.1
0.VCLK	0	0	1	1	1	1	1
1.SINGLE.V4	0	1	0	1	1	1	1
1.QUAD.V1.0	0	1	1	0	1	1	1
1.VCLK	0	1	1	1	0	1	1
1.BUFGLS.H2	1	0	1	1	1	0	1
1.BUFGLS.H3	1	0	1	1	1	1	0
1.BUFGLS.H6	1	1	0	1	1	0	1
1.BUFGLS.H7	1	1	0	1	1	1	0
1.BUFGLS.H4	1	1	1	0	1	0	1
1.BUFGLS.H5	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK5	0.45.1	0.47.1	0.47.0	0.46.1	0.46.0	0.44.0	0.44.1
0.QUAD.V2.3	0	0	1	1	1	1	1
0.VCLK	0	1	0	1	1	1	1
1.SINGLE.V5	0	1	1	0	1	1	1
1.VCLK	0	1	1	1	0	1	1
1.BUFGLS.H4	1	0	1	1	1	0	1
1.BUFGLS.H5	1	0	1	1	1	1	0
1.BUFGLS.H2	1	1	0	1	1	0	1
1.BUFGLS.H3	1	1	0	1	1	1	0
1.BUFGLS.H6	1	1	1	0	1	0	1
1.BUFGLS.H7	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK6	0.41.1	0.43.1	0.43.0	0.42.1	0.42.0	0.40.0	0.40.1
0.QUAD.V2.4	0	0	1	1	1	1	1
0.VCLK	0	1	0	1	1	1	1
1.SINGLE.V6	0	1	1	0	1	1	1
1.VCLK	0	1	1	1	0	1	1
1.BUFGLS.H4	1	0	1	1	1	0	1
1.BUFGLS.H5	1	0	1	1	1	1	0
1.BUFGLS.H2	1	1	0	1	1	0	1
1.BUFGLS.H3	1	1	0	1	1	1	0
1.BUFGLS.H6	1	1	1	0	1	0	1
1.BUFGLS.H7	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK7	0.37.1	0.39.0	0.38.1	0.39.1	0.38.0	0.37.0	0.36.1
0.VCLK	0	0	1	1	1	1	1
1.SINGLE.V7	0	1	0	1	1	1	1
1.QUAD.V2.0	0	1	1	0	1	1	1
1.VCLK	0	1	1	1	0	1	1
1.BUFGLS.H2	1	0	1	1	1	0	1
1.BUFGLS.H3	1	0	1	1	1	1	0
1.BUFGLS.H6	1	1	0	1	1	0	1
1.BUFGLS.H7	1	1	0	1	1	1	0
1.BUFGLS.H4	1	1	1	0	1	0	1
1.BUFGLS.H5	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.LONG.V9	0.22.0	0.21.1
1.LONG.V9	0	0
1.VCLK	0	1
NONE	1	1

LLV:MUX.1.LONG.V7	0.25.0	0.24.1
0.LONG.V7	0	0
0.VCLK	0	1
NONE	1	1

Tile LLVQ.IO.R.T

Cells: 2

Bel BUFF

xc4000ex LLVQ.IO.R.T bel BUFF
Pin	Direction	Wires
O	output	TCELL1:OUT.BUFF

Bel LLV

Switchbox LLV

xc4000ex LLVQ.IO.R.T switchbox LLV
Destination	Source	Kind
TCELL0_IO.DOUBLE.0.E.1	TCELL1_ECLK.V	pass transistor
TCELL0_IO.DOUBLE.1.E.0	TCELL1_ECLK.V	pass transistor
TCELL0_IO.DOUBLE.1.E.1	TCELL1_ECLK.V	pass transistor
TCELL0_IO.DOUBLE.2.E.1	TCELL1_ECLK.V	pass transistor
TCELL0_IO.DOUBLE.3.E.0	TCELL1_ECLK.V	pass transistor
TCELL0_QUAD.V1.4	TCELL0_VCLK	pass transistor
TCELL0_QUAD.V2.4	TCELL1_VCLK	pass transistor
TCELL0_LONG.V0	TCELL1_LONG.V0	buffer
TCELL0_LONG.V1	TCELL1_LONG.V1	buffer
TCELL0_LONG.V2	TCELL1_LONG.V2	buffer
TCELL0_LONG.V3	TCELL1_LONG.V3	buffer
TCELL0_LONG.V4	TCELL1_LONG.V4	buffer
TCELL0_LONG.V5	TCELL1_LONG.V5	buffer
TCELL0_LONG.V6	TCELL1_LONG.V6	buffer
TCELL0_LONG.V7	TCELL1_LONG.V7.EXCL	mux
TCELL0_LONG.V8	TCELL1_LONG.V8	buffer
TCELL0_LONG.V9	TCELL1_LONG.V9.EXCL	mux
TCELL0_LONG.IO.V0	TCELL1_LONG.IO.V0	buffer
TCELL0_LONG.IO.V1	TCELL1_LONG.IO.V1	buffer
TCELL0_LONG.IO.V2	TCELL1_LONG.IO.V2	buffer
TCELL0_LONG.IO.V3	TCELL1_LONG.IO.V3	buffer
TCELL0_GCLK0	TCELL0_IO.DOUBLE.0.E.1	mux
	TCELL0_IO.DOUBLE.2.E.1	mux
	TCELL0_BUFGE.V0	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
	TCELL1_OUT.BUFF	mux
TCELL0_GCLK1	TCELL0_IO.DOUBLE.0.E.0	mux
	TCELL0_IO.DOUBLE.2.E.0	mux
	TCELL0_BUFGE.V1	mux
	TCELL1_ECLK.V	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK2	TCELL0_IO.DOUBLE.1.E.1	mux
	TCELL0_IO.DOUBLE.3.E.1	mux
	TCELL1_ECLK.V	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
	TCELL1_OUT.BUFF	mux
TCELL0_GCLK3	TCELL0_IO.DOUBLE.1.E.0	mux
	TCELL0_IO.DOUBLE.3.E.0	mux
	TCELL0_BUFGE.V0	mux
	TCELL0_BUFGE.V1	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK4	TCELL0_VCLK	mux
	TCELL1_SINGLE.V4	mux
	TCELL1_QUAD.V1.0	mux
	TCELL1_VCLK	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK5	TCELL0_QUAD.V2.3	mux
	TCELL0_VCLK	mux
	TCELL1_SINGLE.V5	mux
	TCELL1_VCLK	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK6	TCELL0_QUAD.V2.4	mux
	TCELL0_VCLK	mux
	TCELL1_SINGLE.V6	mux
	TCELL1_VCLK	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL0_GCLK7	TCELL0_VCLK	mux
	TCELL1_SINGLE.V7	mux
	TCELL1_QUAD.V2.0	mux
	TCELL1_VCLK	mux
	TCELL1_BUFGLS.H0	mux
	TCELL1_BUFGLS.H1	mux
	TCELL1_BUFGLS.H2	mux
	TCELL1_BUFGLS.H3	mux
	TCELL1_BUFGLS.H4	mux
	TCELL1_BUFGLS.H5	mux
	TCELL1_BUFGLS.H6	mux
	TCELL1_BUFGLS.H7	mux
TCELL1_SINGLE.V0	TCELL0_VCLK	pass transistor
TCELL1_SINGLE.V1	TCELL1_VCLK	pass transistor
TCELL1_SINGLE.V2	TCELL0_VCLK	pass transistor
TCELL1_SINGLE.V3	TCELL1_VCLK	pass transistor
TCELL1_SINGLE.V4	TCELL0_VCLK	pass transistor
TCELL1_SINGLE.V5	TCELL1_VCLK	pass transistor
TCELL1_SINGLE.V6	TCELL0_VCLK	pass transistor
TCELL1_SINGLE.V7	TCELL1_VCLK	pass transistor
TCELL1_QUAD.V0.0	TCELL1_VCLK	pass transistor
TCELL1_QUAD.V2.0	TCELL0_VCLK	pass transistor
TCELL1_LONG.V0	TCELL0_LONG.V0	buffer
TCELL1_LONG.V1	TCELL0_LONG.V1	buffer
TCELL1_LONG.V2	TCELL0_LONG.V2	buffer
TCELL1_LONG.V3	TCELL0_LONG.V3	buffer
TCELL1_LONG.V4	TCELL0_LONG.V4	buffer
TCELL1_LONG.V5	TCELL0_LONG.V5	buffer
TCELL1_LONG.V6	TCELL0_LONG.V6	buffer
TCELL1_LONG.V7	TCELL1_LONG.V7.EXCL	mux
TCELL1_LONG.V7.EXCL	TCELL0_LONG.V7	mux
	TCELL0_VCLK	mux
	TCELL1_LONG.V7	mux
TCELL1_LONG.V8	TCELL0_LONG.V8	buffer
TCELL1_LONG.V9	TCELL1_LONG.V9.EXCL	mux
TCELL1_LONG.V9.EXCL	TCELL0_LONG.V9	mux
	TCELL1_LONG.V9	mux
	TCELL1_VCLK	mux
TCELL1_LONG.IO.V0	TCELL0_LONG.IO.V0	buffer
TCELL1_LONG.IO.V1	TCELL0_LONG.IO.V1	buffer
TCELL1_LONG.IO.V2	TCELL0_LONG.IO.V2	buffer
TCELL1_LONG.IO.V3	TCELL0_LONG.IO.V3	buffer

Bel wires

xc4000ex LLVQ.IO.R.T bel wires
Wire	Pins
TCELL1:OUT.BUFF	BUFF.O

Bitstream

xc4000ex LLVQ.IO.R.T bittile 0
Bit	Frame
Bit	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	LLV:MUX.0.GCLK4[3]	LLV:MUX.0.GCLK4[4]	LLV:MUX.0.GCLK4[6]	LLV:MUX.0.GCLK4[0]	LLV:MUX.0.GCLK5[5]	LLV:MUX.0.GCLK5[3]	LLV:MUX.0.GCLK5[6]	LLV:MUX.0.GCLK5[0]	LLV:MUX.0.GCLK6[5]	LLV:MUX.0.GCLK6[3]	LLV:MUX.0.GCLK6[6]	LLV:MUX.0.GCLK6[0]	LLV:MUX.0.GCLK7[3]	LLV:MUX.0.GCLK7[4]	LLV:MUX.0.GCLK7[6]	LLV:MUX.0.GCLK7[0]	~LLV:BUF.0.LONG.V5.1.LONG.V5	~LLV:BUF.0.LONG.V3.1.LONG.V3	~LLV:BUF.0.LONG.V2.1.LONG.V2	~LLV:PASS.1.QUAD.V2.0.0.VCLK	~LLV:BUF.0.LONG.V0.1.LONG.V0	~LLV:PASS.0.QUAD.V1.4.0.VCLK	~LLV:BUF.0.LONG.V4.1.LONG.V4	~LLV:PASS.1.SINGLE.V3.1.VCLK	~LLV:BUF.0.LONG.V1.1.LONG.V1	~LLV:BUF.0.LONG.V6.1.LONG.V6	~LLV:BUF.0.LONG.V7.1.LONG.V7	LLV:MUX.1.LONG.V7[0]	~LLV:BUF.0.LONG.V8.1.LONG.V8	~LLV:BUF.1.LONG.V9.0.LONG.V9	LLV:MUX.0.LONG.V9[0]	~LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0	~LLV:PASS.0.IO.DOUBLE.3.E.0.1.ECLK.V	~LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2	~LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3	~LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1	LLV:MUX.0.GCLK2[4]	LLV:MUX.0.GCLK2[5]	LLV:MUX.0.GCLK2[6]	LLV:MUX.0.GCLK2[0]	LLV:MUX.0.GCLK0[5]	LLV:MUX.0.GCLK0[4]	LLV:MUX.0.GCLK0[6]	LLV:MUX.0.GCLK0[0]	LLV:MUX.0.GCLK1[5]	LLV:MUX.0.GCLK1[4]	LLV:MUX.0.GCLK1[6]	LLV:MUX.0.GCLK1[0]	LLV:MUX.0.GCLK3[4]	LLV:MUX.0.GCLK3[5]	LLV:MUX.0.GCLK3[6]	LLV:MUX.0.GCLK3[0]
0	LLV:MUX.0.GCLK4[5]	LLV:MUX.0.GCLK4[2]	LLV:MUX.0.GCLK4[1]	~LLV:PASS.1.SINGLE.V4.0.VCLK	LLV:MUX.0.GCLK5[4]	LLV:MUX.0.GCLK5[2]	~LLV:PASS.1.SINGLE.V5.1.VCLK	LLV:MUX.0.GCLK5[1]	LLV:MUX.0.GCLK6[4]	LLV:MUX.0.GCLK6[2]	~LLV:PASS.1.SINGLE.V6.0.VCLK	LLV:MUX.0.GCLK6[1]	LLV:MUX.0.GCLK7[5]	LLV:MUX.0.GCLK7[2]	LLV:MUX.0.GCLK7[1]	~LLV:PASS.1.SINGLE.V7.1.VCLK	~LLV:BUF.1.LONG.V5.0.LONG.V5	~LLV:BUF.1.LONG.V3.0.LONG.V3	~LLV:BUF.1.LONG.V2.0.LONG.V2	~LLV:PASS.0.QUAD.V2.4.1.VCLK	~LLV:BUF.1.LONG.V0.0.LONG.V0	~LLV:PASS.1.QUAD.V0.0.1.VCLK	~LLV:BUF.1.LONG.V4.0.LONG.V4	~LLV:PASS.1.SINGLE.V2.0.VCLK	~LLV:BUF.1.LONG.V1.0.LONG.V1	~LLV:BUF.1.LONG.V6.0.LONG.V6	LLV:MUX.1.LONG.V7[1]	~LLV:PASS.1.SINGLE.V0.0.VCLK	~LLV:BUF.1.LONG.V8.0.LONG.V8	LLV:MUX.0.LONG.V9[1]	~LLV:PASS.1.SINGLE.V1.1.VCLK	~LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0	~LLV:PASS.0.IO.DOUBLE.0.E.1.1.ECLK.V	~LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2	~LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3	~LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1	LLV:MUX.0.GCLK2[3]	LLV:MUX.0.GCLK2[2]	-	LLV:MUX.0.GCLK2[1]	LLV:MUX.0.GCLK0[3]	LLV:MUX.0.GCLK0[2]	~LLV:PASS.0.IO.DOUBLE.1.E.0.1.ECLK.V	LLV:MUX.0.GCLK0[1]	LLV:MUX.0.GCLK1[2]	LLV:MUX.0.GCLK1[3]	~LLV:PASS.0.IO.DOUBLE.1.E.1.1.ECLK.V	LLV:MUX.0.GCLK1[1]	LLV:MUX.0.GCLK3[3]	LLV:MUX.0.GCLK3[2]	~LLV:PASS.0.IO.DOUBLE.2.E.1.1.ECLK.V	LLV:MUX.0.GCLK3[1]

LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0	0.20.1
LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1	0.16.1
LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2	0.18.1
LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3	0.17.1
LLV:BUF.0.LONG.V0.1.LONG.V0	0.31.1
LLV:BUF.0.LONG.V1.1.LONG.V1	0.27.1
LLV:BUF.0.LONG.V2.1.LONG.V2	0.33.1
LLV:BUF.0.LONG.V3.1.LONG.V3	0.34.1
LLV:BUF.0.LONG.V4.1.LONG.V4	0.29.1
LLV:BUF.0.LONG.V5.1.LONG.V5	0.35.1
LLV:BUF.0.LONG.V6.1.LONG.V6	0.26.1
LLV:BUF.0.LONG.V7.1.LONG.V7	0.25.1
LLV:BUF.0.LONG.V8.1.LONG.V8	0.23.1
LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0	0.20.0
LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1	0.16.0
LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2	0.18.0
LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3	0.17.0
LLV:BUF.1.LONG.V0.0.LONG.V0	0.31.0
LLV:BUF.1.LONG.V1.0.LONG.V1	0.27.0
LLV:BUF.1.LONG.V2.0.LONG.V2	0.33.0
LLV:BUF.1.LONG.V3.0.LONG.V3	0.34.0
LLV:BUF.1.LONG.V4.0.LONG.V4	0.29.0
LLV:BUF.1.LONG.V5.0.LONG.V5	0.35.0
LLV:BUF.1.LONG.V6.0.LONG.V6	0.26.0
LLV:BUF.1.LONG.V8.0.LONG.V8	0.23.0
LLV:BUF.1.LONG.V9.0.LONG.V9	0.22.1
LLV:PASS.0.IO.DOUBLE.0.E.1.1.ECLK.V	0.19.0
LLV:PASS.0.IO.DOUBLE.1.E.0.1.ECLK.V	0.9.0
LLV:PASS.0.IO.DOUBLE.1.E.1.1.ECLK.V	0.5.0
LLV:PASS.0.IO.DOUBLE.2.E.1.1.ECLK.V	0.1.0
LLV:PASS.0.IO.DOUBLE.3.E.0.1.ECLK.V	0.19.1
LLV:PASS.0.QUAD.V1.4.0.VCLK	0.30.1
LLV:PASS.0.QUAD.V2.4.1.VCLK	0.32.0
LLV:PASS.1.QUAD.V0.0.1.VCLK	0.30.0
LLV:PASS.1.QUAD.V2.0.0.VCLK	0.32.1
LLV:PASS.1.SINGLE.V0.0.VCLK	0.24.0
LLV:PASS.1.SINGLE.V1.1.VCLK	0.21.0
LLV:PASS.1.SINGLE.V2.0.VCLK	0.28.0
LLV:PASS.1.SINGLE.V3.1.VCLK	0.28.1
LLV:PASS.1.SINGLE.V4.0.VCLK	0.48.0
LLV:PASS.1.SINGLE.V5.1.VCLK	0.45.0
LLV:PASS.1.SINGLE.V6.0.VCLK	0.41.0
LLV:PASS.1.SINGLE.V7.1.VCLK	0.36.0
inverted	~[0]

LLV:MUX.0.GCLK0	0.9.1	0.11.1	0.10.1	0.11.0	0.10.0	0.8.0	0.8.1
0.IO.DOUBLE.0.E.1	0	0	1	1	1	1	1
0.IO.DOUBLE.2.E.1	0	1	0	1	1	1	1
0.BUFGE.V0	0	1	1	0	1	1	1
1.OUT.BUFF	0	1	1	1	0	1	1
1.BUFGLS.H4	1	0	1	1	1	0	1
1.BUFGLS.H5	1	0	1	1	1	1	0
1.BUFGLS.H6	1	1	0	1	1	0	1
1.BUFGLS.H7	1	1	0	1	1	1	0
1.BUFGLS.H2	1	1	1	0	1	0	1
1.BUFGLS.H3	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK1	0.5.1	0.7.1	0.6.1	0.6.0	0.7.0	0.4.0	0.4.1
0.IO.DOUBLE.0.E.0	0	0	1	1	1	1	1
0.IO.DOUBLE.2.E.0	0	1	0	1	1	1	1
0.BUFGE.V1	0	1	1	0	1	1	1
1.ECLK.V	0	1	1	1	0	1	1
1.BUFGLS.H4	1	0	1	1	1	0	1
1.BUFGLS.H5	1	0	1	1	1	1	0
1.BUFGLS.H6	1	1	0	1	1	0	1
1.BUFGLS.H7	1	1	0	1	1	1	0
1.BUFGLS.H0	1	1	1	0	1	0	1
1.BUFGLS.H1	1	1	1	0	1	1	0
1.BUFGLS.H2	1	1	1	1	0	0	1
1.BUFGLS.H3	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK2	0.13.1	0.14.1	0.15.1	0.15.0	0.14.0	0.12.0	0.12.1
0.IO.DOUBLE.1.E.1	0	0	1	1	1	1	1
0.IO.DOUBLE.3.E.1	0	1	0	1	1	1	1
1.ECLK.V	0	1	1	0	1	1	1
1.OUT.BUFF	0	1	1	1	0	1	1
1.BUFGLS.H6	1	0	1	1	1	0	1
1.BUFGLS.H7	1	0	1	1	1	1	0
1.BUFGLS.H4	1	1	0	1	1	0	1
1.BUFGLS.H5	1	1	0	1	1	1	0
1.BUFGLS.H2	1	1	1	0	1	0	1
1.BUFGLS.H3	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK3	0.1.1	0.2.1	0.3.1	0.3.0	0.2.0	0.0.0	0.0.1
0.IO.DOUBLE.1.E.0	0	0	1	1	1	1	1
0.IO.DOUBLE.3.E.0	0	1	0	1	1	1	1
0.BUFGE.V0	0	1	1	0	1	1	1
0.BUFGE.V1	0	1	1	1	0	1	1
1.BUFGLS.H6	1	0	1	1	1	0	1
1.BUFGLS.H7	1	0	1	1	1	1	0
1.BUFGLS.H4	1	1	0	1	1	0	1
1.BUFGLS.H5	1	1	0	1	1	1	0
1.BUFGLS.H2	1	1	1	0	1	0	1
1.BUFGLS.H3	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK4	0.49.1	0.51.0	0.50.1	0.51.1	0.50.0	0.49.0	0.48.1
0.VCLK	0	0	1	1	1	1	1
1.SINGLE.V4	0	1	0	1	1	1	1
1.QUAD.V1.0	0	1	1	0	1	1	1
1.VCLK	0	1	1	1	0	1	1
1.BUFGLS.H2	1	0	1	1	1	0	1
1.BUFGLS.H3	1	0	1	1	1	1	0
1.BUFGLS.H6	1	1	0	1	1	0	1
1.BUFGLS.H7	1	1	0	1	1	1	0
1.BUFGLS.H4	1	1	1	0	1	0	1
1.BUFGLS.H5	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK5	0.45.1	0.47.1	0.47.0	0.46.1	0.46.0	0.44.0	0.44.1
0.QUAD.V2.3	0	0	1	1	1	1	1
0.VCLK	0	1	0	1	1	1	1
1.SINGLE.V5	0	1	1	0	1	1	1
1.VCLK	0	1	1	1	0	1	1
1.BUFGLS.H4	1	0	1	1	1	0	1
1.BUFGLS.H5	1	0	1	1	1	1	0
1.BUFGLS.H2	1	1	0	1	1	0	1
1.BUFGLS.H3	1	1	0	1	1	1	0
1.BUFGLS.H6	1	1	1	0	1	0	1
1.BUFGLS.H7	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK6	0.41.1	0.43.1	0.43.0	0.42.1	0.42.0	0.40.0	0.40.1
0.QUAD.V2.4	0	0	1	1	1	1	1
0.VCLK	0	1	0	1	1	1	1
1.SINGLE.V6	0	1	1	0	1	1	1
1.VCLK	0	1	1	1	0	1	1
1.BUFGLS.H4	1	0	1	1	1	0	1
1.BUFGLS.H5	1	0	1	1	1	1	0
1.BUFGLS.H2	1	1	0	1	1	0	1
1.BUFGLS.H3	1	1	0	1	1	1	0
1.BUFGLS.H6	1	1	1	0	1	0	1
1.BUFGLS.H7	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.GCLK7	0.37.1	0.39.0	0.38.1	0.39.1	0.38.0	0.37.0	0.36.1
0.VCLK	0	0	1	1	1	1	1
1.SINGLE.V7	0	1	0	1	1	1	1
1.QUAD.V2.0	0	1	1	0	1	1	1
1.VCLK	0	1	1	1	0	1	1
1.BUFGLS.H2	1	0	1	1	1	0	1
1.BUFGLS.H3	1	0	1	1	1	1	0
1.BUFGLS.H6	1	1	0	1	1	0	1
1.BUFGLS.H7	1	1	0	1	1	1	0
1.BUFGLS.H4	1	1	1	0	1	0	1
1.BUFGLS.H5	1	1	1	0	1	1	0
1.BUFGLS.H0	1	1	1	1	0	0	1
1.BUFGLS.H1	1	1	1	1	0	1	0
NONE	1	1	1	1	1	1	1

LLV:MUX.0.LONG.V9	0.22.0	0.21.1
1.LONG.V9	0	0
1.VCLK	0	1
NONE	1	1

LLV:MUX.1.LONG.V7	0.25.0	0.24.1
0.LONG.V7	0	0
0.VCLK	0	1
NONE	1	1

Tile CLKC

Cells: 0

Bel CLKC

xc4000ex CLKC bel CLKC
Pin	Direction	Wires

Tile CLKQC

Cells: 1

Bel CLKQC

xc4000ex CLKQC bel CLKQC
Pin	Direction	Wires
O.LL.H	output	BUFGLS.H2
O.LL.V	output	BUFGLS.H1
O.LR.H	output	BUFGLS.H3
O.LR.V	output	BUFGLS.H4
O.UL.H	output	BUFGLS.H7
O.UL.V	output	BUFGLS.H0
O.UR.H	output	BUFGLS.H6
O.UR.V	output	BUFGLS.H5

Bel wires

xc4000ex CLKQC bel wires
Wire	Pins
BUFGLS.H0	CLKQC.O.UL.V
BUFGLS.H1	CLKQC.O.LL.V
BUFGLS.H2	CLKQC.O.LL.H
BUFGLS.H3	CLKQC.O.LR.H
BUFGLS.H4	CLKQC.O.LR.V
BUFGLS.H5	CLKQC.O.UR.V
BUFGLS.H6	CLKQC.O.UR.H
BUFGLS.H7	CLKQC.O.UL.H

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