Input/Output

Tile IO_W0

Cells: 4

Switchbox INT

xc4000h IO_W0 switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[0]	CELL.DEC_V[3]	!MAIN[7][5]
CELL.SINGLE_H[0]	CELL.OUT_IO_WE_I2_S1	!MAIN[1][4]
CELL.SINGLE_H[1]	CELL.LONG_IO_V[0]	!MAIN[3][4]
CELL.SINGLE_H[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[4][4]
CELL.SINGLE_H[2]	CELL.LONG_IO_V[1]	!MAIN[12][7]
CELL.SINGLE_H[2]	CELL.OUT_IO_WE_I1[0]	!MAIN[4][7]
CELL.SINGLE_H[3]	CELL.DEC_V[2]	!MAIN[16][9]
CELL.SINGLE_H[3]	CELL.OUT_IO_WE_I1_S1	!MAIN[10][8]
CELL.SINGLE_H[4]	CELL.DEC_V[1]	!MAIN[15][5]
CELL.SINGLE_H[4]	CELL.OUT_IO_WE_I2_S1	!MAIN[0][4]
CELL.SINGLE_H[5]	CELL.LONG_IO_V[2]	!MAIN[6][4]
CELL.SINGLE_H[5]	CELL.OUT_IO_WE_I2[0]	!MAIN[5][4]
CELL.SINGLE_H[6]	CELL.LONG_IO_V[3]	!MAIN[8][8]
CELL.SINGLE_H[6]	CELL.OUT_IO_WE_I1[0]	!MAIN[1][8]
CELL.SINGLE_H[7]	CELL.DEC_V[0]	!MAIN[8][9]
CELL.SINGLE_H[7]	CELL.OUT_IO_WE_I1_S1	!MAIN[0][8]
CELL.DOUBLE_H0[0]	CELL.OUT_IO_WE_I1_S1	!MAIN[2][7]
CELL.DOUBLE_H0[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[2][6]
CELL.DOUBLE_H1[0]	CELL.OUT_IO_WE_I1[0]	!MAIN[5][7]
CELL.DOUBLE_H1[1]	CELL.OUT_IO_WE_I2_S1	!MAIN[2][4]
CELL.DOUBLE_IO_W0[0]	CELL.DBUF_IO_V[1]	!MAIN[10][5]
CELL.DOUBLE_IO_W0[1]	CELL.DBUF_IO_V[1]	!MAIN[10][6]
CELL.DOUBLE_IO_W0[2]	CELL.DBUF_IO_V[1]	!MAIN[12][4]
CELL.DOUBLE_IO_W0[3]	CELL.DBUF_IO_V[1]	!MAIN[3][6]
CELL.DOUBLE_IO_W2[0]	CELL.DBUF_IO_V[0]	!MAIN[6][6]
CELL.DOUBLE_IO_W2[1]	CELL.DBUF_IO_V[0]	!MAIN[9][7]
CELL.DOUBLE_IO_W2[2]	CELL.DBUF_IO_V[0]	!MAIN[8][6]
CELL.DOUBLE_IO_W2[3]	CELL.DBUF_IO_V[0]	!MAIN[8][7]

xc4000h IO_W0 switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.DOUBLE_IO_W0[0]	!MAIN[9][5]
CELL.SINGLE_H[0]	CELL.DOUBLE_IO_W2[0]	!MAIN[0][5]
CELL.SINGLE_H[1]	CELL.DOUBLE_IO_W1[0]	!MAIN[6][5]
CELL.SINGLE_H[2]	CELL.DOUBLE_IO_W0[1]	!MAIN[15][9]
CELL.SINGLE_H[2]	CELL.DOUBLE_IO_W2[1]	!MAIN[9][9]
CELL.SINGLE_H[3]	CELL.DOUBLE_IO_W1[1]	!MAIN[13][9]
CELL.SINGLE_H[4]	CELL.DOUBLE_IO_W0[2]	!MAIN[12][5]
CELL.SINGLE_H[4]	CELL.DOUBLE_IO_W2[2]	!MAIN[8][4]
CELL.SINGLE_H[5]	CELL.DOUBLE_IO_W1[2]	!MAIN[11][4]
CELL.SINGLE_H[6]	CELL.DOUBLE_IO_W0[3]	!MAIN[6][9]
CELL.SINGLE_H[6]	CELL.DOUBLE_IO_W2[3]	!MAIN[0][9]
CELL.SINGLE_H[7]	CELL.DOUBLE_IO_W1[3]	!MAIN[4][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_W0[0]	!MAIN[8][5]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_W1[0]	!MAIN[5][5]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_W2[0]	!MAIN[2][5]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_W0[3]	!MAIN[5][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_W1[3]	!MAIN[3][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_W2[3]	!MAIN[1][9]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_W0[1]	!MAIN[14][9]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_W1[1]	!MAIN[12][9]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_W2[1]	!MAIN[10][9]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_W0[2]	!MAIN[11][5]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_W1[2]	!MAIN[10][3]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_W2[2]	!MAIN[9][4]
CELL.DOUBLE_IO_W0[0]	CELL.DOUBLE_IO_W2[0]	!MAIN[3][5]
CELL.DOUBLE_IO_W0[1]	CELL.DOUBLE_IO_W2[1]	!MAIN[11][9]
CELL.DOUBLE_IO_W0[2]	CELL.DOUBLE_IO_W2[2]	!MAIN[10][4]
CELL.DOUBLE_IO_W0[3]	CELL.DOUBLE_IO_W2[3]	!MAIN[2][9]

xc4000h IO_W0 switchbox INT muxes DBUF_IO_V[0]
Bits				Destination
MAIN[1][2]	MAIN[3][2]	MAIN[4][3]	MAIN[3][3]	CELL.DBUF_IO_V[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_W0[1]
0	1	0	1	CELL.DOUBLE_IO_W0[2]
0	1	1	0	CELL.DOUBLE_IO_W0[3]
1	1	1	1	CELL.DOUBLE_IO_W0[0]

xc4000h IO_W0 switchbox INT muxes DBUF_IO_V[1]
Bits				Destination
MAIN[14][8]	MAIN[17][8]	MAIN[16][8]	MAIN[15][8]	CELL.DBUF_IO_V[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_W2[0]
0	1	0	1	CELL.DOUBLE_IO_W2[1]
0	1	1	0	CELL.DOUBLE_IO_W2[3]
1	1	1	1	CELL.DOUBLE_IO_W2[2]

xc4000h IO_W0 switchbox INT muxes LONG_H[0]
Bits				Destination
MAIN[1][1]	MAIN[0][1]	MAIN[0][0]	MAIN[1][0]	CELL.LONG_H[0]
				Source
0	0	0	1	CELL.LONG_IO_V[0]
0	0	1	0	CELL.DEC_V[0]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000h IO_W0 switchbox INT muxes LONG_H[1]
Bits				Destination
MAIN[15][1]	MAIN[14][1]	MAIN[15][0]	MAIN[14][0]	CELL.LONG_H[1]
				Source
0	0	0	1	CELL.LONG_IO_V[1]
0	0	1	0	CELL.DEC_V[1]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000h IO_W0 switchbox INT muxes LONG_H[4]
Bits				Destination
MAIN[1][6]	MAIN[0][6]	MAIN[3][7]	MAIN[1][7]	CELL.LONG_H[4]
				Source
0	0	0	1	CELL.LONG_IO_V[2]
0	0	1	0	CELL.DEC_V[2]
0	1	1	1	CELL.OUT_IO_WE_I2[0]
1	1	1	1	off

xc4000h IO_W0 switchbox INT muxes LONG_H[5]
Bits				Destination
MAIN[10][7]	MAIN[4][6]	MAIN[6][7]	MAIN[5][6]	CELL.LONG_H[5]
				Source
0	0	0	1	CELL.LONG_IO_V[3]
0	0	1	0	CELL.DEC_V[3]
0	1	1	1	CELL.OUT_IO_WE_I2[0]
1	1	1	1	off

xc4000h IO_W0 switchbox INT muxes LONG_IO_V[0]
Bits		Destination
MAIN[4][5]	MAIN[1][5]	CELL.LONG_IO_V[0]
		Source
0	0	CELL.LONG_H[0]
0	1	CELL.SINGLE_H[1]
1	1	off

xc4000h IO_W0 switchbox INT muxes LONG_IO_V[1]
Bits				Destination
MAIN[13][8]	MAIN[11][8]	MAIN[12][8]	MAIN[17][9]	CELL.LONG_IO_V[1]
				Source
0	0	0	1	CELL.LONG_H[1]
0	0	1	0	CELL.LONG_H[3]
0	1	1	1	CELL.SINGLE_H[2]
1	1	1	1	off

xc4000h IO_W0 switchbox INT muxes LONG_IO_V[2]
Bits				Destination
MAIN[5][8]	MAIN[2][8]	MAIN[4][8]	MAIN[3][8]	CELL.LONG_IO_V[2]
				Source
0	0	0	1	CELL.LONG_H[2]
0	0	1	0	CELL.LONG_H[4]
0	1	1	1	CELL.SINGLE_H[5]
1	1	1	1	off

xc4000h IO_W0 switchbox INT muxes LONG_IO_V[3]
Bits		Destination
MAIN[6][8]	MAIN[9][8]	CELL.LONG_IO_V[3]
		Source
0	0	CELL.LONG_H[5]
0	1	CELL.SINGLE_H[6]
1	1	off

xc4000h IO_W0 switchbox INT muxes IMUX_TBUF_I[0]
Bits						Destination
MAIN[2][1]	MAIN[2][0]	MAIN[4][1]	MAIN[4][0]	MAIN[3][0]	MAIN[3][1]	CELL.IMUX_TBUF_I[0]
						Source
0	0	0	1	1	1	CELL.OUT_IO_WE_I2[0]
0	0	1	0	1	1	CELL.DOUBLE_IO_W1[2]
0	0	1	1	0	1	CELL.LONG_IO_V[2]
0	0	1	1	1	0	CELL.DEC_V[2]
0	1	1	1	1	1	CELL.DOUBLE_IO_W0[2]
1	0	0	1	1	1	CELL.DOUBLE_IO_W0[3]
1	0	1	0	1	1	CELL.DOUBLE_IO_W1[3]
1	0	1	1	0	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_W0 switchbox INT muxes IMUX_TBUF_I[1]
Bits						Destination
MAIN[11][1]	MAIN[13][0]	MAIN[13][1]	MAIN[11][0]	MAIN[12][0]	MAIN[12][1]	CELL.IMUX_TBUF_I[1]
						Source
0	0	0	1	1	1	CELL.DOUBLE_IO_W0[2]
0	0	1	0	1	1	CELL.OUT_IO_WE_I2[0]
0	0	1	1	0	1	CELL.LONG_IO_V[1]
0	0	1	1	1	0	CELL.DEC_V[1]
0	1	0	1	1	1	CELL.DOUBLE_IO_W1[3]
0	1	1	0	1	1	CELL.DOUBLE_IO_W0[3]
0	1	1	1	1	0	CELL.OUT_IO_WE_I2[1]
1	0	1	1	1	1	CELL.DOUBLE_IO_W1[2]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_W0 switchbox INT muxes IMUX_TBUF_T[0]
Bits						Destination
MAIN[5][1]	MAIN[6][0]	MAIN[5][0]	MAIN[8][0]	MAIN[6][1]	MAIN[7][0]	CELL.IMUX_TBUF_T[0]
						Source
0	0	0	1	1	1	CELL.TIE_1
0	0	1	1	1	1	CELL.TIE_0
0	1	0	0	1	1	CELL.DOUBLE_IO_W0[1]
0	1	0	1	0	1	CELL.LONG_IO_V[3]
0	1	0	1	1	0	CELL.DEC_V[0]
0	1	1	0	1	1	CELL.DOUBLE_IO_W1[1]
0	1	1	1	0	1	CELL.LONG_IO_V[2]
0	1	1	1	1	0	CELL.DEC_V[3]
1	1	0	1	1	1	CELL.DOUBLE_IO_W0[0]
1	1	1	1	1	1	CELL.DOUBLE_IO_W1[0]

xc4000h IO_W0 switchbox INT muxes IMUX_TBUF_T[1]
Bits						Destination
MAIN[7][1]	MAIN[8][1]	MAIN[10][1]	MAIN[10][0]	MAIN[9][0]	MAIN[9][1]	CELL.IMUX_TBUF_T[1]
						Source
0	0	0	1	1	1	CELL.TIE_1
0	0	1	1	1	1	CELL.TIE_0
0	1	0	0	1	1	CELL.DOUBLE_IO_W1[0]
0	1	0	1	0	1	CELL.LONG_IO_V[2]
0	1	0	1	1	0	CELL.DEC_V[3]
0	1	1	0	1	1	CELL.DOUBLE_IO_W0[0]
0	1	1	1	0	1	CELL.LONG_IO_V[3]
0	1	1	1	1	0	CELL.DEC_V[0]
1	1	0	1	1	1	CELL.DOUBLE_IO_W1[1]
1	1	1	1	1	1	CELL.DOUBLE_IO_W0[1]

xc4000h IO_W0 switchbox INT muxes IMUX_IO_O1[0]
Bits						Destination
MAIN[18][8]	MAIN[19][8]	MAIN[20][9]	MAIN[18][9]	MAIN[19][9]	MAIN[20][8]	CELL.IMUX_IO_O1[0]
						Source
0	0	0	1	1	1	CELL.DEC_V[0]
0	0	1	1	1	1	CELL.DOUBLE_H0[0]
0	1	0	0	1	1	CELL.DEC_V[1]
0	1	0	1	0	1	CELL.DEC_V[2]
0	1	0	1	1	0	CELL.DEC_V[3]
0	1	1	0	1	1	CELL.LONG_H[3]
0	1	1	1	0	1	CELL.LONG_H[4]
0	1	1	1	1	0	CELL.LONG_H[5]
1	1	0	1	1	1	CELL.DOUBLE_H1[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_W0 switchbox INT muxes IMUX_IO_O1[1]
Bits						Destination
MAIN[16][1]	MAIN[20][0]	MAIN[19][0]	MAIN[18][0]	MAIN[16][0]	MAIN[17][0]	CELL.IMUX_IO_O1[1]
						Source
0	0	0	1	1	1	CELL.LONG_H[0]
0	0	1	0	1	1	CELL.LONG_H[1]
0	0	1	1	0	1	CELL.DEC_V[0]
0	0	1	1	1	0	CELL.DEC_V[1]
0	1	0	1	1	1	CELL_S.DOUBLE_H0[1]
0	1	1	0	1	1	CELL.LONG_H[2]
0	1	1	1	0	1	CELL.DEC_V[2]
0	1	1	1	1	0	CELL.DEC_V[3]
1	0	1	1	1	1	CELL_S.DOUBLE_H1[0]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_W0 switchbox INT muxes IMUX_IO_OK[0]
Bits								Destination
MAIN[9][6]	MAIN[17][5]	MAIN[18][6]	MAIN[12][6]	MAIN[15][6]	MAIN[14][6]	MAIN[11][6]	MAIN[16][6]	CELL.IMUX_IO_OK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_H[3]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[2]

xc4000h IO_W0 switchbox INT muxes IMUX_IO_OK[1]
Bits								Destination
MAIN[11][2]	MAIN[18][2]	MAIN[17][2]	MAIN[13][2]	MAIN[19][2]	MAIN[12][2]	MAIN[16][2]	MAIN[20][2]	CELL.IMUX_IO_OK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_S.SINGLE_H[2]
0	1	1	1	1	1	0	1	CELL_S.SINGLE_H[4]
0	1	1	1	1	1	1	0	CELL_S.SINGLE_H[5]
1	1	1	1	1	1	1	1	CELL_S.SINGLE_H[3]

xc4000h IO_W0 switchbox INT muxes IMUX_IO_IK[0]
Bits								Destination
MAIN[13][7]	MAIN[20][7]	MAIN[14][7]	MAIN[16][7]	MAIN[18][7]	MAIN[17][7]	MAIN[15][7]	MAIN[19][7]	CELL.IMUX_IO_IK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_H[2]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[3]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[4]

xc4000h IO_W0 switchbox INT muxes IMUX_IO_IK[1]
Bits								Destination
MAIN[14][3]	MAIN[18][1]	MAIN[18][3]	MAIN[14][2]	MAIN[19][1]	MAIN[17][1]	MAIN[20][1]	MAIN[15][2]	CELL.IMUX_IO_IK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_S.SINGLE_H[2]
0	1	1	1	1	1	0	1	CELL_S.SINGLE_H[3]
0	1	1	1	1	1	1	0	CELL_S.SINGLE_H[4]
1	1	1	1	1	1	1	1	CELL_S.SINGLE_H[5]

xc4000h IO_W0 switchbox INT muxes IMUX_IO_T[0]
Bits								Destination
MAIN[1][3]	MAIN[4][2]	MAIN[7][4]	MAIN[2][3]	MAIN[6][2]	MAIN[6][3]	MAIN[5][2]	MAIN[5][3]	CELL.IMUX_IO_T[0]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	0	1	1	1	CELL.LONG_IO_V[3]
0	0	1	0	1	0	1	1	CELL.LONG_IO_V[0]
0	0	1	1	0	1	0	1	CELL.LONG_IO_V[1]
0	0	1	1	0	1	1	0	CELL.GCLK[0]
0	0	1	1	1	0	0	1	CELL.DEC_V[1]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_W0[1]
0	1	1	1	1	1	0	1	CELL.LONG_IO_V[2]
0	1	1	1	1	1	1	0	CELL.DEC_V[0]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_W1[0]
1	0	1	1	1	0	1	1	CELL.DOUBLE_IO_W1[1]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_W0[0]

xc4000h IO_W0 switchbox INT muxes IMUX_IO_T[1]
Bits								Destination
MAIN[2][2]	MAIN[0][2]	MAIN[7][2]	MAIN[8][3]	MAIN[9][3]	MAIN[11][3]	MAIN[9][2]	MAIN[10][2]	CELL.IMUX_IO_T[1]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	1	0	1	1	CELL.DEC_V[1]
0	0	1	0	1	1	0	1	CELL.LONG_IO_V[0]
0	0	1	1	0	0	1	1	CELL.DOUBLE_IO_W0[1]
0	0	1	1	0	1	0	1	CELL.LONG_IO_V[2]
0	0	1	1	0	1	1	0	CELL.DEC_V[0]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_W0[0]
0	1	1	1	0	1	1	1	CELL.DOUBLE_IO_W1[1]
1	0	1	1	1	0	1	1	CELL.LONG_IO_V[1]
1	0	1	1	1	1	0	1	CELL.LONG_IO_V[3]
1	0	1	1	1	1	1	0	CELL.GCLK[0]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_W1[0]

xc4000h IO_W0 switchbox INT muxes IMUX_HIO_O[0]
Bits	Destination
MAIN[25][7]	CELL.IMUX_HIO_O[0]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_G3_W

xc4000h IO_W0 switchbox INT muxes IMUX_HIO_O[1]
Bits	Destination
MAIN[22][6]	CELL.IMUX_HIO_O[1]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_G3_W

xc4000h IO_W0 switchbox INT muxes IMUX_HIO_O[2]
Bits	Destination
MAIN[21][2]	CELL.IMUX_HIO_O[2]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_F3_W

xc4000h IO_W0 switchbox INT muxes IMUX_HIO_O[3]
Bits	Destination
MAIN[23][1]	CELL.IMUX_HIO_O[3]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_F3_W

xc4000h IO_W0 switchbox INT muxes IMUX_HIO_T[0]
Bits	Destination
MAIN[21][8]	CELL.IMUX_HIO_T[0]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_OK[0]

xc4000h IO_W0 switchbox INT muxes IMUX_HIO_T[1]
Bits	Destination
MAIN[24][6]	CELL.IMUX_HIO_T[1]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_IK[0]

xc4000h IO_W0 switchbox INT muxes IMUX_HIO_T[2]
Bits	Destination
MAIN[24][3]	CELL.IMUX_HIO_T[2]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_IK[1]

xc4000h IO_W0 switchbox INT muxes IMUX_HIO_T[3]
Bits	Destination
MAIN[21][1]	CELL.IMUX_HIO_T[3]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_OK[1]

xc4000h IO_W0 switchbox INT muxes OUT_IO_WE_I1[0]
Bits	Destination
MAIN[25][5]	CELL.OUT_IO_WE_I1[0]
	Source
0	CELL.OUT_HIO_I[1]
1	CELL.OUT_HIO_I[0]

xc4000h IO_W0 switchbox INT muxes OUT_IO_WE_I1[1]
Bits	Destination
MAIN[24][4]	CELL.OUT_IO_WE_I1[1]
	Source
0	CELL.OUT_HIO_I[2]
1	CELL.OUT_HIO_I[3]

xc4000h IO_W0 switchbox INT muxes OUT_IO_WE_I2[0]
Bits	Destination
MAIN[22][9]	CELL.OUT_IO_WE_I2[0]
	Source
0	CELL.OUT_HIO_I[0]
1	CELL.OUT_HIO_I[1]

xc4000h IO_W0 switchbox INT muxes OUT_IO_WE_I2[1]
Bits	Destination
MAIN[22][0]	CELL.OUT_IO_WE_I2[1]
	Source
0	CELL.OUT_HIO_I[3]
1	CELL.OUT_HIO_I[2]

Bels TBUF

xc4000h IO_W0 bel TBUF pins
Pin	Direction	TBUF[0]	TBUF[1]
I	in	CELL.IMUX_TBUF_I[0]	CELL.IMUX_TBUF_I[1]
T	in	CELL.IMUX_TBUF_T[0]	CELL.IMUX_TBUF_T[1]
O	bidir	CELL.LONG_H[2]	CELL.LONG_H[3]

xc4000h IO_W0 bel TBUF attribute bits
Attribute	TBUF[0]	TBUF[1]
DRIVE1	!MAIN[0][3]	!MAIN[12][3]

Bels HIO

xc4000h IO_W0 bel HIO pins
Pin	Direction	HIO[0]	HIO[1]	HIO[2]	HIO[3]
O	in	CELL.IMUX_HIO_O[0] invert by !MAIN[24][8]	CELL.IMUX_HIO_O[1] invert by !MAIN[23][6]	CELL.IMUX_HIO_O[2] invert by !MAIN[23][3]	CELL.IMUX_HIO_O[3] invert by !MAIN[22][1]
T	in	CELL.IMUX_HIO_T[0] invert by !MAIN[21][9]	CELL.IMUX_HIO_T[1] invert by !MAIN[25][6]	CELL.IMUX_HIO_T[2] invert by !MAIN[25][3]	CELL.IMUX_HIO_T[3] invert by !MAIN[21][0]
I	out	CELL.OUT_HIO_I[0]	CELL.OUT_HIO_I[1]	CELL.OUT_HIO_I[2]	CELL.OUT_HIO_I[3]

xc4000h IO_W0 bel HIO attribute bits
Attribute	HIO[0]	HIO[1]	HIO[2]	HIO[3]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
ISTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OSTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OMODE	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]
I_INV	!MAIN[23][9]	!MAIN[24][5]	!MAIN[25][4]	!MAIN[23][0]
READBACK_I bit 0	!MAIN[23][8]	!MAIN[25][8]	!MAIN[21][3]	!MAIN[22][3]

xc4000h IO_W0 enum IO_PULL
HIO[0].PULL	MAIN[24][7]	MAIN[23][7]
HIO[1].PULL	MAIN[21][6]	MAIN[17][6]
HIO[2].PULL	MAIN[16][3]	MAIN[22][2]
HIO[3].PULL	MAIN[25][1]	MAIN[24][1]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

xc4000h IO_W0 enum IO_STD
HIO[0].ISTD	MAIN[24][9]
HIO[1].ISTD	MAIN[23][5]
HIO[2].ISTD	MAIN[23][4]
HIO[3].ISTD	MAIN[24][0]
CMOS	0
TTL	1

xc4000h IO_W0 enum IO_STD
HIO[0].OSTD	MAIN[25][9]
HIO[1].OSTD	MAIN[22][5]
HIO[2].OSTD	MAIN[22][4]
HIO[3].OSTD	MAIN[25][0]
CMOS	1
TTL	0

xc4000h IO_W0 enum HIO_OMODE
HIO[0].OMODE	MAIN[22][7]
HIO[1].OMODE	MAIN[21][7]
HIO[2].OMODE	MAIN[24][2]
HIO[3].OMODE	MAIN[25][2]
CAP	1
RES	0

Bels DEC

xc4000h IO_W0 bel DEC pins
Pin	Direction	DEC[0]	DEC[1]	DEC[2]
I	in	CELL.OUT_IO_WE_I1[0]	CELL.IMUX_CLB_C3_W	CELL.OUT_IO_WE_I1[1]
O1	bidir	CELL.DEC_V[0]	CELL.DEC_V[0]	CELL.DEC_V[0]
O2	bidir	CELL.DEC_V[1]	CELL.DEC_V[1]	CELL.DEC_V[1]
O3	bidir	CELL.DEC_V[2]	CELL.DEC_V[2]	CELL.DEC_V[2]
O4	bidir	CELL.DEC_V[3]	CELL.DEC_V[3]	CELL.DEC_V[3]

xc4000h IO_W0 bel DEC attribute bits
Attribute	DEC[0]	DEC[1]	DEC[2]
O1_P	!MAIN[13][4]	!MAIN[13][5]	MAIN[14][5]
O1_N	MAIN[13][3]	MAIN[13][6]	!MAIN[14][4]
O2_P	!MAIN[19][3]	!MAIN[19][6]	MAIN[18][4]
O2_N	MAIN[19][4]	MAIN[19][5]	!MAIN[18][5]
O3_P	!MAIN[15][4]	!MAIN[17][3]	MAIN[16][4]
O3_N	MAIN[15][3]	MAIN[17][4]	!MAIN[16][5]
O4_P	!MAIN[20][4]	!MAIN[20][6]	MAIN[21][5]
O4_N	MAIN[20][3]	MAIN[20][5]	!MAIN[21][4]

Bels PULLUP

xc4000h IO_W0 bel PULLUP pins
Pin	Direction	PULLUP_TBUF[0]	PULLUP_TBUF[1]
O	bidir	CELL.LONG_H[2]	CELL.LONG_H[3]

xc4000h IO_W0 bel PULLUP attribute bits
Attribute	PULLUP_TBUF[0]	PULLUP_TBUF[1]
ENABLE	!MAIN_S[0][7]	!MAIN[11][7]

Bel wires

xc4000h IO_W0 bel wires
Wire	Pins
CELL.LONG_H[2]	TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]	TBUF[1].O, PULLUP_TBUF[1].O
CELL.DEC_V[0]	DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_V[1]	DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.DEC_V[2]	DEC[0].O3, DEC[1].O3, DEC[2].O3
CELL.DEC_V[3]	DEC[0].O4, DEC[1].O4, DEC[2].O4
CELL.IMUX_CLB_C3_W	DEC[1].I
CELL.IMUX_TBUF_I[0]	TBUF[0].I
CELL.IMUX_TBUF_I[1]	TBUF[1].I
CELL.IMUX_TBUF_T[0]	TBUF[0].T
CELL.IMUX_TBUF_T[1]	TBUF[1].T
CELL.IMUX_HIO_O[0]	HIO[0].O
CELL.IMUX_HIO_O[1]	HIO[1].O
CELL.IMUX_HIO_O[2]	HIO[2].O
CELL.IMUX_HIO_O[3]	HIO[3].O
CELL.IMUX_HIO_T[0]	HIO[0].T
CELL.IMUX_HIO_T[1]	HIO[1].T
CELL.IMUX_HIO_T[2]	HIO[2].T
CELL.IMUX_HIO_T[3]	HIO[3].T
CELL.OUT_IO_WE_I1[0]	DEC[0].I
CELL.OUT_IO_WE_I1[1]	DEC[2].I
CELL.OUT_HIO_I[0]	HIO[0].I
CELL.OUT_HIO_I[1]	HIO[1].I
CELL.OUT_HIO_I[2]	HIO[2].I
CELL.OUT_HIO_I[3]	HIO[3].I

Bitstream

xc4000h IO_W0 rect MAIN
Bit	Frame
Bit	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	HIO[0]: OSTD bit 0	HIO[0]: ISTD bit 0	HIO[0]: ! I_INV	INT: mux CELL.OUT_IO_WE_I2[0] bit 0	HIO[0]: !invert T	INT: mux CELL.IMUX_IO_O1[0] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 1	INT: mux CELL.IMUX_IO_O1[0] bit 2	INT: mux CELL.LONG_IO_V[1] bit 0	INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W0[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W0[1]	INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W1[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W1[1]	INT: !bipass CELL.DOUBLE_IO_W0[1] = CELL.DOUBLE_IO_W2[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W2[1]	INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W2[1]	INT: !pass CELL.SINGLE_H[7] ← CELL.DEC_V[0]	-	INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_W0[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W0[3]	INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_W1[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W1[3]	INT: !bipass CELL.DOUBLE_IO_W0[3] = CELL.DOUBLE_IO_W2[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W2[3]	INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_W2[3]
B8	HIO[1]: ! READBACK_I bit 0	HIO[0]: !invert O	HIO[0]: ! READBACK_I bit 0	-	INT: mux CELL.IMUX_HIO_T[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 4	INT: mux CELL.IMUX_IO_O1[0] bit 5	INT: mux CELL.DBUF_IO_V[1] bit 2	INT: mux CELL.DBUF_IO_V[1] bit 1	INT: mux CELL.DBUF_IO_V[1] bit 0	INT: mux CELL.DBUF_IO_V[1] bit 3	INT: mux CELL.LONG_IO_V[1] bit 3	INT: mux CELL.LONG_IO_V[1] bit 1	INT: mux CELL.LONG_IO_V[1] bit 2	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1	INT: mux CELL.LONG_IO_V[3] bit 0	INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_IO_V[3]	-	INT: mux CELL.LONG_IO_V[3] bit 1	INT: mux CELL.LONG_IO_V[2] bit 3	INT: mux CELL.LONG_IO_V[2] bit 1	INT: mux CELL.LONG_IO_V[2] bit 0	INT: mux CELL.LONG_IO_V[2] bit 2	INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_IO_WE_I1[0]	INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_IO_WE_I1_S1
B7	INT: mux CELL.IMUX_HIO_O[0] bit 0	HIO[0]: PULL bit 1	HIO[0]: PULL bit 0	HIO[0]: OMODE bit 0	HIO[1]: OMODE bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 6	INT: mux CELL.IMUX_IO_IK[0] bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 3	INT: mux CELL.IMUX_IO_IK[0] bit 2	INT: mux CELL.IMUX_IO_IK[0] bit 4	INT: mux CELL.IMUX_IO_IK[0] bit 1	INT: mux CELL.IMUX_IO_IK[0] bit 5	INT: mux CELL.IMUX_IO_IK[0] bit 7	INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[1]	PULLUP_TBUF[1]: ! ENABLE	INT: mux CELL.LONG_H[5] bit 3	INT: !pass CELL.DOUBLE_IO_W2[1] ← CELL.DBUF_IO_V[0]	INT: !pass CELL.DOUBLE_IO_W2[3] ← CELL.DBUF_IO_V[0]	-	INT: mux CELL.LONG_H[5] bit 1	INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1[0]	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0]	INT: mux CELL.LONG_H[4] bit 1	INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1_S1	INT: mux CELL.LONG_H[4] bit 0	-
B6	HIO[1]: !invert T	INT: mux CELL.IMUX_HIO_T[1] bit 0	HIO[1]: !invert O	INT: mux CELL.IMUX_HIO_O[1] bit 0	HIO[1]: PULL bit 1	DEC[1]: ! O4_P	DEC[1]: ! O2_P	INT: mux CELL.IMUX_IO_OK[0] bit 5	HIO[1]: PULL bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 3	INT: mux CELL.IMUX_IO_OK[0] bit 2	DEC[1]: O1_N	INT: mux CELL.IMUX_IO_OK[0] bit 4	INT: mux CELL.IMUX_IO_OK[0] bit 1	INT: !pass CELL.DOUBLE_IO_W0[1] ← CELL.DBUF_IO_V[1]	INT: mux CELL.IMUX_IO_OK[0] bit 7	INT: !pass CELL.DOUBLE_IO_W2[2] ← CELL.DBUF_IO_V[0]	-	INT: !pass CELL.DOUBLE_IO_W2[0] ← CELL.DBUF_IO_V[0]	INT: mux CELL.LONG_H[5] bit 0	INT: mux CELL.LONG_H[5] bit 2	INT: !pass CELL.DOUBLE_IO_W0[3] ← CELL.DBUF_IO_V[1]	INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2[0]	INT: mux CELL.LONG_H[4] bit 3	INT: mux CELL.LONG_H[4] bit 2
B5	INT: mux CELL.OUT_IO_WE_I1[0] bit 0	HIO[1]: ! I_INV	HIO[1]: ISTD bit 0	HIO[1]: OSTD bit 0	DEC[2]: O4_P	DEC[1]: O4_N	DEC[1]: O2_N	DEC[2]: ! O2_N	INT: mux CELL.IMUX_IO_OK[0] bit 6	DEC[2]: ! O3_N	INT: !pass CELL.SINGLE_H[4] ← CELL.DEC_V[1]	DEC[2]: O1_P	DEC[1]: ! O1_P	INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_W0[2]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W0[2]	INT: !pass CELL.DOUBLE_IO_W0[0] ← CELL.DBUF_IO_V[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W0[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W0[0]	INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[3]	INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W1[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W1[0]	INT: mux CELL.LONG_IO_V[0] bit 1	INT: !bipass CELL.DOUBLE_IO_W0[0] = CELL.DOUBLE_IO_W2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W2[0]	INT: mux CELL.LONG_IO_V[0] bit 0	INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W2[0]
B4	HIO[2]: ! I_INV	INT: mux CELL.OUT_IO_WE_I1[1] bit 0	HIO[2]: ISTD bit 0	HIO[2]: OSTD bit 0	DEC[2]: ! O4_N	DEC[0]: ! O4_P	DEC[0]: O2_N	DEC[2]: O2_P	DEC[1]: O3_N	DEC[2]: O3_P	DEC[0]: ! O3_P	DEC[2]: ! O1_N	DEC[0]: ! O1_P	INT: !pass CELL.DOUBLE_IO_W0[2] ← CELL.DBUF_IO_V[1]	INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_W1[2]	INT: !bipass CELL.DOUBLE_IO_W0[2] = CELL.DOUBLE_IO_W2[2]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W2[2]	INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_W2[2]	INT: mux CELL.IMUX_IO_T[0] bit 5	INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_IO_V[2]	INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[0]	INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_WE_I2_S1
B3	HIO[2]: !invert T	INT: mux CELL.IMUX_HIO_T[2] bit 0	HIO[2]: !invert O	HIO[3]: ! READBACK_I bit 0	HIO[2]: ! READBACK_I bit 0	DEC[0]: O4_N	DEC[0]: ! O2_P	INT: mux CELL.IMUX_IO_IK[1] bit 5	DEC[1]: ! O3_P	HIO[2]: PULL bit 1	DEC[0]: O3_N	INT: mux CELL.IMUX_IO_IK[1] bit 7	DEC[0]: O1_N	TBUF[1]: ! DRIVE1	INT: mux CELL.IMUX_IO_T[1] bit 2	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W1[2]	INT: mux CELL.IMUX_IO_T[1] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 4	-	INT: mux CELL.IMUX_IO_T[0] bit 2	INT: mux CELL.IMUX_IO_T[0] bit 0	INT: mux CELL.DBUF_IO_V[0] bit 1	INT: mux CELL.DBUF_IO_V[0] bit 0	INT: mux CELL.IMUX_IO_T[0] bit 4	INT: mux CELL.IMUX_IO_T[0] bit 7	TBUF[0]: ! DRIVE1
B2	HIO[3]: OMODE bit 0	HIO[2]: OMODE bit 0	-	HIO[2]: PULL bit 0	INT: mux CELL.IMUX_HIO_O[2] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 3	INT: mux CELL.IMUX_IO_OK[1] bit 6	INT: mux CELL.IMUX_IO_OK[1] bit 5	INT: mux CELL.IMUX_IO_OK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 0	INT: mux CELL.IMUX_IO_IK[1] bit 4	INT: mux CELL.IMUX_IO_OK[1] bit 4	INT: mux CELL.IMUX_IO_OK[1] bit 2	INT: mux CELL.IMUX_IO_OK[1] bit 7	INT: mux CELL.IMUX_IO_T[1] bit 0	INT: mux CELL.IMUX_IO_T[1] bit 1	-	INT: mux CELL.IMUX_IO_T[1] bit 5	INT: mux CELL.IMUX_IO_T[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 6	INT: mux CELL.DBUF_IO_V[0] bit 2	INT: mux CELL.IMUX_IO_T[1] bit 7	INT: mux CELL.DBUF_IO_V[0] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 6
B1	HIO[3]: PULL bit 1	HIO[3]: PULL bit 0	INT: mux CELL.IMUX_HIO_O[3] bit 0	HIO[3]: !invert O	INT: mux CELL.IMUX_HIO_T[3] bit 0	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 3	INT: mux CELL.IMUX_IO_IK[1] bit 6	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 5	INT: mux CELL.LONG_H[1] bit 3	INT: mux CELL.LONG_H[1] bit 2	INT: mux CELL.IMUX_TBUF_I[1] bit 3	INT: mux CELL.IMUX_TBUF_I[1] bit 0	INT: mux CELL.IMUX_TBUF_I[1] bit 5	INT: mux CELL.IMUX_TBUF_T[1] bit 3	INT: mux CELL.IMUX_TBUF_T[1] bit 0	INT: mux CELL.IMUX_TBUF_T[1] bit 4	INT: mux CELL.IMUX_TBUF_T[1] bit 5	INT: mux CELL.IMUX_TBUF_T[0] bit 1	INT: mux CELL.IMUX_TBUF_T[0] bit 5	INT: mux CELL.IMUX_TBUF_I[0] bit 3	INT: mux CELL.IMUX_TBUF_I[0] bit 0	INT: mux CELL.IMUX_TBUF_I[0] bit 5	INT: mux CELL.LONG_H[0] bit 3	INT: mux CELL.LONG_H[0] bit 2
B0	HIO[3]: OSTD bit 0	HIO[3]: ISTD bit 0	HIO[3]: ! I_INV	INT: mux CELL.OUT_IO_WE_I2[1] bit 0	HIO[3]: !invert T	INT: mux CELL.IMUX_IO_O1[1] bit 4	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 0	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.LONG_H[1] bit 1	INT: mux CELL.LONG_H[1] bit 0	INT: mux CELL.IMUX_TBUF_I[1] bit 4	INT: mux CELL.IMUX_TBUF_I[1] bit 1	INT: mux CELL.IMUX_TBUF_I[1] bit 2	INT: mux CELL.IMUX_TBUF_T[1] bit 2	INT: mux CELL.IMUX_TBUF_T[1] bit 1	INT: mux CELL.IMUX_TBUF_T[0] bit 2	INT: mux CELL.IMUX_TBUF_T[0] bit 0	INT: mux CELL.IMUX_TBUF_T[0] bit 4	INT: mux CELL.IMUX_TBUF_T[0] bit 3	INT: mux CELL.IMUX_TBUF_I[0] bit 2	INT: mux CELL.IMUX_TBUF_I[0] bit 1	INT: mux CELL.IMUX_TBUF_I[0] bit 4	INT: mux CELL.LONG_H[0] bit 0	INT: mux CELL.LONG_H[0] bit 1

xc4000h IO_W0 rect MAIN_S
Bit	Frame
Bit	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PULLUP_TBUF[0]: ! ENABLE
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile IO_W0_N

Cells: 4

Switchbox INT

xc4000h IO_W0_N switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[0]	CELL.DEC_V[3]	!MAIN[7][5]
CELL.SINGLE_H[0]	CELL.OUT_IO_WE_I2_S1	!MAIN[1][4]
CELL.SINGLE_H[1]	CELL.LONG_IO_V[0]	!MAIN[3][4]
CELL.SINGLE_H[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[4][4]
CELL.SINGLE_H[2]	CELL.LONG_IO_V[1]	!MAIN[12][7]
CELL.SINGLE_H[2]	CELL.OUT_IO_WE_I1[0]	!MAIN[4][7]
CELL.SINGLE_H[3]	CELL.DEC_V[2]	!MAIN[16][9]
CELL.SINGLE_H[3]	CELL.OUT_IO_WE_I1_S1	!MAIN[10][8]
CELL.SINGLE_H[4]	CELL.DEC_V[1]	!MAIN[15][5]
CELL.SINGLE_H[4]	CELL.OUT_IO_WE_I2_S1	!MAIN[0][4]
CELL.SINGLE_H[5]	CELL.LONG_IO_V[2]	!MAIN[6][4]
CELL.SINGLE_H[5]	CELL.OUT_IO_WE_I2[0]	!MAIN[5][4]
CELL.SINGLE_H[6]	CELL.LONG_IO_V[3]	!MAIN[8][8]
CELL.SINGLE_H[6]	CELL.OUT_IO_WE_I1[0]	!MAIN[1][8]
CELL.SINGLE_H[7]	CELL.DEC_V[0]	!MAIN[8][9]
CELL.SINGLE_H[7]	CELL.OUT_IO_WE_I1_S1	!MAIN[0][8]
CELL.DOUBLE_H0[0]	CELL.OUT_IO_WE_I1_S1	!MAIN[2][7]
CELL.DOUBLE_H0[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[2][6]
CELL.DOUBLE_H1[0]	CELL.OUT_IO_WE_I1[0]	!MAIN[5][7]
CELL.DOUBLE_H1[1]	CELL.OUT_IO_WE_I2_S1	!MAIN[2][4]
CELL.DOUBLE_IO_W0[0]	CELL.DBUF_IO_V[1]	!MAIN[10][5]
CELL.DOUBLE_IO_W0[1]	CELL.DBUF_IO_V[1]	!MAIN[10][6]
CELL.DOUBLE_IO_W0[2]	CELL.DBUF_IO_V[1]	!MAIN[12][4]
CELL.DOUBLE_IO_W0[3]	CELL.DBUF_IO_V[1]	!MAIN[3][6]
CELL.DOUBLE_IO_W2[0]	CELL.DBUF_IO_V[0]	!MAIN[6][6]
CELL.DOUBLE_IO_W2[1]	CELL.DBUF_IO_V[0]	!MAIN[9][7]
CELL.DOUBLE_IO_W2[2]	CELL.DBUF_IO_V[0]	!MAIN[8][6]
CELL.DOUBLE_IO_W2[3]	CELL.DBUF_IO_V[0]	!MAIN[8][7]

xc4000h IO_W0_N switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.DOUBLE_IO_W0[0]	!MAIN[9][5]
CELL.SINGLE_H[0]	CELL.DOUBLE_IO_W2[0]	!MAIN[0][5]
CELL.SINGLE_H[1]	CELL.DOUBLE_IO_W1[0]	!MAIN[6][5]
CELL.SINGLE_H[2]	CELL.DOUBLE_IO_W0[1]	!MAIN[15][9]
CELL.SINGLE_H[2]	CELL.DOUBLE_IO_W2[1]	!MAIN[9][9]
CELL.SINGLE_H[3]	CELL.DOUBLE_IO_W1[1]	!MAIN[13][9]
CELL.SINGLE_H[4]	CELL.DOUBLE_IO_W0[2]	!MAIN[12][5]
CELL.SINGLE_H[4]	CELL.DOUBLE_IO_W2[2]	!MAIN[8][4]
CELL.SINGLE_H[5]	CELL.DOUBLE_IO_W1[2]	!MAIN[11][4]
CELL.SINGLE_H[6]	CELL.DOUBLE_IO_W0[3]	!MAIN[6][9]
CELL.SINGLE_H[6]	CELL.DOUBLE_IO_W2[3]	!MAIN[0][9]
CELL.SINGLE_H[7]	CELL.DOUBLE_IO_W1[3]	!MAIN[4][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_W0[0]	!MAIN[8][5]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_W1[0]	!MAIN[5][5]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_W2[0]	!MAIN[2][5]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_W0[3]	!MAIN[5][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_W1[3]	!MAIN[3][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_W2[3]	!MAIN[1][9]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_W0[1]	!MAIN[14][9]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_W1[1]	!MAIN[12][9]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_W2[1]	!MAIN[10][9]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_W0[2]	!MAIN[11][5]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_W1[2]	!MAIN[10][3]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_W2[2]	!MAIN[9][4]
CELL.DOUBLE_IO_W0[0]	CELL.DOUBLE_IO_W2[0]	!MAIN[3][5]
CELL.DOUBLE_IO_W0[1]	CELL.DOUBLE_IO_W2[1]	!MAIN[11][9]
CELL.DOUBLE_IO_W0[2]	CELL.DOUBLE_IO_W2[2]	!MAIN[10][4]
CELL.DOUBLE_IO_W0[3]	CELL.DOUBLE_IO_W2[3]	!MAIN[2][9]

xc4000h IO_W0_N switchbox INT muxes DBUF_IO_V[0]
Bits				Destination
MAIN[1][2]	MAIN[3][2]	MAIN[4][3]	MAIN[3][3]	CELL.DBUF_IO_V[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_W0[1]
0	1	0	1	CELL.DOUBLE_IO_W0[2]
0	1	1	0	CELL.DOUBLE_IO_W0[3]
1	1	1	1	CELL.DOUBLE_IO_W0[0]

xc4000h IO_W0_N switchbox INT muxes DBUF_IO_V[1]
Bits				Destination
MAIN[14][8]	MAIN[17][8]	MAIN[16][8]	MAIN[15][8]	CELL.DBUF_IO_V[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_W2[0]
0	1	0	1	CELL.DOUBLE_IO_W2[1]
0	1	1	0	CELL.DOUBLE_IO_W2[3]
1	1	1	1	CELL.DOUBLE_IO_W2[2]

xc4000h IO_W0_N switchbox INT muxes LONG_H[0]
Bits				Destination
MAIN[1][1]	MAIN[0][1]	MAIN[0][0]	MAIN[1][0]	CELL.LONG_H[0]
				Source
0	0	0	1	CELL.LONG_IO_V[0]
0	0	1	0	CELL.DEC_V[0]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000h IO_W0_N switchbox INT muxes LONG_H[1]
Bits				Destination
MAIN[15][1]	MAIN[14][1]	MAIN[15][0]	MAIN[14][0]	CELL.LONG_H[1]
				Source
0	0	0	1	CELL.LONG_IO_V[1]
0	0	1	0	CELL.DEC_V[1]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000h IO_W0_N switchbox INT muxes LONG_H[4]
Bits				Destination
MAIN[1][6]	MAIN[0][6]	MAIN[3][7]	MAIN[1][7]	CELL.LONG_H[4]
				Source
0	0	0	1	CELL.LONG_IO_V[2]
0	0	1	0	CELL.DEC_V[2]
0	1	1	1	CELL.OUT_IO_WE_I2[0]
1	1	1	1	off

xc4000h IO_W0_N switchbox INT muxes LONG_H[5]
Bits				Destination
MAIN[10][7]	MAIN[4][6]	MAIN[6][7]	MAIN[5][6]	CELL.LONG_H[5]
				Source
0	0	0	1	CELL.LONG_IO_V[3]
0	0	1	0	CELL.DEC_V[3]
0	1	1	1	CELL.OUT_IO_WE_I2[0]
1	1	1	1	off

xc4000h IO_W0_N switchbox INT muxes LONG_IO_V[0]
Bits		Destination
MAIN[4][5]	MAIN[1][5]	CELL.LONG_IO_V[0]
		Source
0	0	CELL.LONG_H[0]
0	1	CELL.SINGLE_H[1]
1	1	off

xc4000h IO_W0_N switchbox INT muxes LONG_IO_V[1]
Bits				Destination
MAIN[13][8]	MAIN[11][8]	MAIN[12][8]	MAIN[17][9]	CELL.LONG_IO_V[1]
				Source
0	0	0	1	CELL.LONG_H[1]
0	0	1	0	CELL.LONG_H[3]
0	1	1	1	CELL.SINGLE_H[2]
1	1	1	1	off

xc4000h IO_W0_N switchbox INT muxes LONG_IO_V[2]
Bits				Destination
MAIN[5][8]	MAIN[2][8]	MAIN[4][8]	MAIN[3][8]	CELL.LONG_IO_V[2]
				Source
0	0	0	1	CELL.LONG_H[2]
0	0	1	0	CELL.LONG_H[4]
0	1	1	1	CELL.SINGLE_H[5]
1	1	1	1	off

xc4000h IO_W0_N switchbox INT muxes LONG_IO_V[3]
Bits		Destination
MAIN[6][8]	MAIN[9][8]	CELL.LONG_IO_V[3]
		Source
0	0	CELL.LONG_H[5]
0	1	CELL.SINGLE_H[6]
1	1	off

xc4000h IO_W0_N switchbox INT muxes IMUX_TBUF_I[0]
Bits						Destination
MAIN[2][1]	MAIN[2][0]	MAIN[4][1]	MAIN[4][0]	MAIN[3][0]	MAIN[3][1]	CELL.IMUX_TBUF_I[0]
						Source
0	0	0	1	1	1	CELL.OUT_IO_WE_I2[0]
0	0	1	0	1	1	CELL.DOUBLE_IO_W1[2]
0	0	1	1	0	1	CELL.LONG_IO_V[2]
0	0	1	1	1	0	CELL.DEC_V[2]
0	1	1	1	1	1	CELL.DOUBLE_IO_W0[2]
1	0	0	1	1	1	CELL.DOUBLE_IO_W0[3]
1	0	1	0	1	1	CELL.DOUBLE_IO_W1[3]
1	0	1	1	0	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_W0_N switchbox INT muxes IMUX_TBUF_I[1]
Bits						Destination
MAIN[11][1]	MAIN[13][0]	MAIN[13][1]	MAIN[11][0]	MAIN[12][0]	MAIN[12][1]	CELL.IMUX_TBUF_I[1]
						Source
0	0	0	1	1	1	CELL.DOUBLE_IO_W0[2]
0	0	1	0	1	1	CELL.OUT_IO_WE_I2[0]
0	0	1	1	0	1	CELL.LONG_IO_V[1]
0	0	1	1	1	0	CELL.DEC_V[1]
0	1	0	1	1	1	CELL.DOUBLE_IO_W1[3]
0	1	1	0	1	1	CELL.DOUBLE_IO_W0[3]
0	1	1	1	1	0	CELL.OUT_IO_WE_I2[1]
1	0	1	1	1	1	CELL.DOUBLE_IO_W1[2]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_W0_N switchbox INT muxes IMUX_TBUF_T[0]
Bits						Destination
MAIN[5][1]	MAIN[6][0]	MAIN[5][0]	MAIN[8][0]	MAIN[6][1]	MAIN[7][0]	CELL.IMUX_TBUF_T[0]
						Source
0	0	0	1	1	1	CELL.TIE_1
0	0	1	1	1	1	CELL.TIE_0
0	1	0	0	1	1	CELL.DOUBLE_IO_W0[1]
0	1	0	1	0	1	CELL.LONG_IO_V[3]
0	1	0	1	1	0	CELL.DEC_V[0]
0	1	1	0	1	1	CELL.DOUBLE_IO_W1[1]
0	1	1	1	0	1	CELL.LONG_IO_V[2]
0	1	1	1	1	0	CELL.DEC_V[3]
1	1	0	1	1	1	CELL.DOUBLE_IO_W0[0]
1	1	1	1	1	1	CELL.DOUBLE_IO_W1[0]

xc4000h IO_W0_N switchbox INT muxes IMUX_TBUF_T[1]
Bits						Destination
MAIN[7][1]	MAIN[8][1]	MAIN[10][1]	MAIN[10][0]	MAIN[9][0]	MAIN[9][1]	CELL.IMUX_TBUF_T[1]
						Source
0	0	0	1	1	1	CELL.TIE_1
0	0	1	1	1	1	CELL.TIE_0
0	1	0	0	1	1	CELL.DOUBLE_IO_W1[0]
0	1	0	1	0	1	CELL.LONG_IO_V[2]
0	1	0	1	1	0	CELL.DEC_V[3]
0	1	1	0	1	1	CELL.DOUBLE_IO_W0[0]
0	1	1	1	0	1	CELL.LONG_IO_V[3]
0	1	1	1	1	0	CELL.DEC_V[0]
1	1	0	1	1	1	CELL.DOUBLE_IO_W1[1]
1	1	1	1	1	1	CELL.DOUBLE_IO_W0[1]

xc4000h IO_W0_N switchbox INT muxes IMUX_IO_O1[0]
Bits						Destination
MAIN[18][8]	MAIN[19][8]	MAIN[20][9]	MAIN[18][9]	MAIN[19][9]	MAIN[20][8]	CELL.IMUX_IO_O1[0]
						Source
0	0	0	1	1	1	CELL.DEC_V[0]
0	0	1	1	1	1	CELL.DOUBLE_H0[0]
0	1	0	0	1	1	CELL.DEC_V[1]
0	1	0	1	0	1	CELL.DEC_V[2]
0	1	0	1	1	0	CELL.DEC_V[3]
0	1	1	0	1	1	CELL.LONG_H[3]
0	1	1	1	0	1	CELL.LONG_H[4]
0	1	1	1	1	0	CELL.LONG_H[5]
1	1	0	1	1	1	CELL.DOUBLE_H1[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_W0_N switchbox INT muxes IMUX_IO_O1[1]
Bits						Destination
MAIN[16][1]	MAIN[20][0]	MAIN[19][0]	MAIN[18][0]	MAIN[16][0]	MAIN[17][0]	CELL.IMUX_IO_O1[1]
						Source
0	0	0	1	1	1	CELL.LONG_H[0]
0	0	1	0	1	1	CELL.LONG_H[1]
0	0	1	1	0	1	CELL.DEC_V[0]
0	0	1	1	1	0	CELL.DEC_V[1]
0	1	0	1	1	1	CELL_S.DOUBLE_H0[1]
0	1	1	0	1	1	CELL.LONG_H[2]
0	1	1	1	0	1	CELL.DEC_V[2]
0	1	1	1	1	0	CELL.DEC_V[3]
1	0	1	1	1	1	CELL_S.DOUBLE_H1[0]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_W0_N switchbox INT muxes IMUX_IO_OK[0]
Bits								Destination
MAIN[9][6]	MAIN[17][5]	MAIN[18][6]	MAIN[12][6]	MAIN[15][6]	MAIN[14][6]	MAIN[11][6]	MAIN[16][6]	CELL.IMUX_IO_OK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_H[3]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[2]

xc4000h IO_W0_N switchbox INT muxes IMUX_IO_OK[1]
Bits								Destination
MAIN[11][2]	MAIN[18][2]	MAIN[17][2]	MAIN[13][2]	MAIN[19][2]	MAIN[12][2]	MAIN[16][2]	MAIN[20][2]	CELL.IMUX_IO_OK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_S.SINGLE_H[2]
0	1	1	1	1	1	0	1	CELL_S.SINGLE_H[4]
0	1	1	1	1	1	1	0	CELL_S.SINGLE_H[5]
1	1	1	1	1	1	1	1	CELL_S.SINGLE_H[3]

xc4000h IO_W0_N switchbox INT muxes IMUX_IO_IK[0]
Bits								Destination
MAIN[13][7]	MAIN[20][7]	MAIN[14][7]	MAIN[16][7]	MAIN[18][7]	MAIN[17][7]	MAIN[15][7]	MAIN[19][7]	CELL.IMUX_IO_IK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_H[2]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[3]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[4]

xc4000h IO_W0_N switchbox INT muxes IMUX_IO_IK[1]
Bits								Destination
MAIN[14][3]	MAIN[18][1]	MAIN[18][3]	MAIN[14][2]	MAIN[19][1]	MAIN[17][1]	MAIN[20][1]	MAIN[15][2]	CELL.IMUX_IO_IK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_S.SINGLE_H[2]
0	1	1	1	1	1	0	1	CELL_S.SINGLE_H[3]
0	1	1	1	1	1	1	0	CELL_S.SINGLE_H[4]
1	1	1	1	1	1	1	1	CELL_S.SINGLE_H[5]

xc4000h IO_W0_N switchbox INT muxes IMUX_IO_T[0]
Bits								Destination
MAIN[1][3]	MAIN[4][2]	MAIN[7][4]	MAIN[2][3]	MAIN[6][2]	MAIN[6][3]	MAIN[5][2]	MAIN[5][3]	CELL.IMUX_IO_T[0]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	0	1	1	1	CELL.LONG_IO_V[3]
0	0	1	0	1	0	1	1	CELL.LONG_IO_V[0]
0	0	1	1	0	1	0	1	CELL.LONG_IO_V[1]
0	0	1	1	0	1	1	0	CELL.GCLK[0]
0	0	1	1	1	0	0	1	CELL.DEC_V[1]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_W0[1]
0	1	1	1	1	1	0	1	CELL.LONG_IO_V[2]
0	1	1	1	1	1	1	0	CELL.DEC_V[0]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_W1[0]
1	0	1	1	1	0	1	1	CELL.DOUBLE_IO_W1[1]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_W0[0]

xc4000h IO_W0_N switchbox INT muxes IMUX_IO_T[1]
Bits								Destination
MAIN[2][2]	MAIN[0][2]	MAIN[7][2]	MAIN[8][3]	MAIN[9][3]	MAIN[11][3]	MAIN[9][2]	MAIN[10][2]	CELL.IMUX_IO_T[1]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	1	0	1	1	CELL.DEC_V[1]
0	0	1	0	1	1	0	1	CELL.LONG_IO_V[0]
0	0	1	1	0	0	1	1	CELL.DOUBLE_IO_W0[1]
0	0	1	1	0	1	0	1	CELL.LONG_IO_V[2]
0	0	1	1	0	1	1	0	CELL.DEC_V[0]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_W0[0]
0	1	1	1	0	1	1	1	CELL.DOUBLE_IO_W1[1]
1	0	1	1	1	0	1	1	CELL.LONG_IO_V[1]
1	0	1	1	1	1	0	1	CELL.LONG_IO_V[3]
1	0	1	1	1	1	1	0	CELL.GCLK[0]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_W1[0]

xc4000h IO_W0_N switchbox INT muxes IMUX_HIO_O[0]
Bits	Destination
MAIN[25][7]	CELL.IMUX_HIO_O[0]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_G3_W

xc4000h IO_W0_N switchbox INT muxes IMUX_HIO_O[1]
Bits	Destination
MAIN[22][6]	CELL.IMUX_HIO_O[1]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_G3_W

xc4000h IO_W0_N switchbox INT muxes IMUX_HIO_O[2]
Bits	Destination
MAIN[21][2]	CELL.IMUX_HIO_O[2]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_F3_W

xc4000h IO_W0_N switchbox INT muxes IMUX_HIO_O[3]
Bits	Destination
MAIN[23][1]	CELL.IMUX_HIO_O[3]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_F3_W

xc4000h IO_W0_N switchbox INT muxes IMUX_HIO_T[0]
Bits	Destination
MAIN[21][8]	CELL.IMUX_HIO_T[0]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_OK[0]

xc4000h IO_W0_N switchbox INT muxes IMUX_HIO_T[1]
Bits	Destination
MAIN[24][6]	CELL.IMUX_HIO_T[1]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_IK[0]

xc4000h IO_W0_N switchbox INT muxes IMUX_HIO_T[2]
Bits	Destination
MAIN[24][3]	CELL.IMUX_HIO_T[2]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_IK[1]

xc4000h IO_W0_N switchbox INT muxes IMUX_HIO_T[3]
Bits	Destination
MAIN[21][1]	CELL.IMUX_HIO_T[3]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_OK[1]

xc4000h IO_W0_N switchbox INT muxes OUT_IO_WE_I1[0]
Bits	Destination
MAIN[25][5]	CELL.OUT_IO_WE_I1[0]
	Source
0	CELL.OUT_HIO_I[1]
1	CELL.OUT_HIO_I[0]

xc4000h IO_W0_N switchbox INT muxes OUT_IO_WE_I1[1]
Bits	Destination
MAIN[24][4]	CELL.OUT_IO_WE_I1[1]
	Source
0	CELL.OUT_HIO_I[2]
1	CELL.OUT_HIO_I[3]

xc4000h IO_W0_N switchbox INT muxes OUT_IO_WE_I2[0]
Bits	Destination
MAIN[22][9]	CELL.OUT_IO_WE_I2[0]
	Source
0	CELL.OUT_HIO_I[0]
1	CELL.OUT_HIO_I[1]

xc4000h IO_W0_N switchbox INT muxes OUT_IO_WE_I2[1]
Bits	Destination
MAIN[22][0]	CELL.OUT_IO_WE_I2[1]
	Source
0	CELL.OUT_HIO_I[3]
1	CELL.OUT_HIO_I[2]

Bels TBUF

xc4000h IO_W0_N bel TBUF pins
Pin	Direction	TBUF[0]	TBUF[1]
I	in	CELL.IMUX_TBUF_I[0]	CELL.IMUX_TBUF_I[1]
T	in	CELL.IMUX_TBUF_T[0]	CELL.IMUX_TBUF_T[1]
O	bidir	CELL.LONG_H[2]	CELL.LONG_H[3]

xc4000h IO_W0_N bel TBUF attribute bits
Attribute	TBUF[0]	TBUF[1]
DRIVE1	!MAIN[0][3]	!MAIN[12][3]

Bels HIO

xc4000h IO_W0_N bel HIO pins
Pin	Direction	HIO[0]	HIO[1]	HIO[2]	HIO[3]
O	in	CELL.IMUX_HIO_O[0] invert by !MAIN[24][8]	CELL.IMUX_HIO_O[1] invert by !MAIN[23][6]	CELL.IMUX_HIO_O[2] invert by !MAIN[23][3]	CELL.IMUX_HIO_O[3] invert by !MAIN[22][1]
T	in	CELL.IMUX_HIO_T[0] invert by !MAIN[21][9]	CELL.IMUX_HIO_T[1] invert by !MAIN[25][6]	CELL.IMUX_HIO_T[2] invert by !MAIN[25][3]	CELL.IMUX_HIO_T[3] invert by !MAIN[21][0]
I	out	CELL.OUT_HIO_I[0]	CELL.OUT_HIO_I[1]	CELL.OUT_HIO_I[2]	CELL.OUT_HIO_I[3]
CLKIN	out	CELL.OUT_IO_CLKIN	-	-	-

xc4000h IO_W0_N bel HIO attribute bits
Attribute	HIO[0]	HIO[1]	HIO[2]	HIO[3]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
ISTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OSTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OMODE	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]
I_INV	!MAIN[23][9]	!MAIN[24][5]	!MAIN[25][4]	!MAIN[23][0]
READBACK_I bit 0	!MAIN[23][8]	!MAIN[25][8]	!MAIN[21][3]	!MAIN[22][3]

xc4000h IO_W0_N enum IO_PULL
HIO[0].PULL	MAIN[24][7]	MAIN[23][7]
HIO[1].PULL	MAIN[21][6]	MAIN[17][6]
HIO[2].PULL	MAIN[16][3]	MAIN[22][2]
HIO[3].PULL	MAIN[25][1]	MAIN[24][1]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

xc4000h IO_W0_N enum IO_STD
HIO[0].ISTD	MAIN[24][9]
HIO[1].ISTD	MAIN[23][5]
HIO[2].ISTD	MAIN[23][4]
HIO[3].ISTD	MAIN[24][0]
CMOS	0
TTL	1

xc4000h IO_W0_N enum IO_STD
HIO[0].OSTD	MAIN[25][9]
HIO[1].OSTD	MAIN[22][5]
HIO[2].OSTD	MAIN[22][4]
HIO[3].OSTD	MAIN[25][0]
CMOS	1
TTL	0

xc4000h IO_W0_N enum HIO_OMODE
HIO[0].OMODE	MAIN[22][7]
HIO[1].OMODE	MAIN[21][7]
HIO[2].OMODE	MAIN[24][2]
HIO[3].OMODE	MAIN[25][2]
CAP	1
RES	0

Bels DEC

xc4000h IO_W0_N bel DEC pins
Pin	Direction	DEC[0]	DEC[1]	DEC[2]
I	in	CELL.OUT_IO_WE_I1[0]	CELL.IMUX_CLB_C3_W	CELL.OUT_IO_WE_I1[1]
O1	bidir	CELL.DEC_V[0]	CELL.DEC_V[0]	CELL.DEC_V[0]
O2	bidir	CELL.DEC_V[1]	CELL.DEC_V[1]	CELL.DEC_V[1]
O3	bidir	CELL.DEC_V[2]	CELL.DEC_V[2]	CELL.DEC_V[2]
O4	bidir	CELL.DEC_V[3]	CELL.DEC_V[3]	CELL.DEC_V[3]

xc4000h IO_W0_N bel DEC attribute bits
Attribute	DEC[0]	DEC[1]	DEC[2]
O1_P	!MAIN[13][4]	!MAIN[13][5]	MAIN[14][5]
O1_N	MAIN[13][3]	MAIN[13][6]	!MAIN[14][4]
O2_P	!MAIN[19][3]	!MAIN[19][6]	MAIN[18][4]
O2_N	MAIN[19][4]	MAIN[19][5]	!MAIN[18][5]
O3_P	!MAIN[15][4]	!MAIN[17][3]	MAIN[16][4]
O3_N	MAIN[15][3]	MAIN[17][4]	!MAIN[16][5]
O4_P	!MAIN[20][4]	!MAIN[20][6]	MAIN[21][5]
O4_N	MAIN[20][3]	MAIN[20][5]	!MAIN[21][4]

Bels PULLUP

xc4000h IO_W0_N bel PULLUP pins
Pin	Direction	PULLUP_TBUF[0]	PULLUP_TBUF[1]
O	bidir	CELL.LONG_H[2]	CELL.LONG_H[3]

xc4000h IO_W0_N bel PULLUP attribute bits
Attribute	PULLUP_TBUF[0]	PULLUP_TBUF[1]
ENABLE	!MAIN_S[0][7]	!MAIN[11][7]

Bel wires

xc4000h IO_W0_N bel wires
Wire	Pins
CELL.LONG_H[2]	TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]	TBUF[1].O, PULLUP_TBUF[1].O
CELL.DEC_V[0]	DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_V[1]	DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.DEC_V[2]	DEC[0].O3, DEC[1].O3, DEC[2].O3
CELL.DEC_V[3]	DEC[0].O4, DEC[1].O4, DEC[2].O4
CELL.IMUX_CLB_C3_W	DEC[1].I
CELL.IMUX_TBUF_I[0]	TBUF[0].I
CELL.IMUX_TBUF_I[1]	TBUF[1].I
CELL.IMUX_TBUF_T[0]	TBUF[0].T
CELL.IMUX_TBUF_T[1]	TBUF[1].T
CELL.IMUX_HIO_O[0]	HIO[0].O
CELL.IMUX_HIO_O[1]	HIO[1].O
CELL.IMUX_HIO_O[2]	HIO[2].O
CELL.IMUX_HIO_O[3]	HIO[3].O
CELL.IMUX_HIO_T[0]	HIO[0].T
CELL.IMUX_HIO_T[1]	HIO[1].T
CELL.IMUX_HIO_T[2]	HIO[2].T
CELL.IMUX_HIO_T[3]	HIO[3].T
CELL.OUT_IO_WE_I1[0]	DEC[0].I
CELL.OUT_IO_WE_I1[1]	DEC[2].I
CELL.OUT_HIO_I[0]	HIO[0].I
CELL.OUT_HIO_I[1]	HIO[1].I
CELL.OUT_HIO_I[2]	HIO[2].I
CELL.OUT_HIO_I[3]	HIO[3].I
CELL.OUT_IO_CLKIN	HIO[0].CLKIN

Bitstream

xc4000h IO_W0_N rect MAIN
Bit	Frame
Bit	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	HIO[0]: OSTD bit 0	HIO[0]: ISTD bit 0	HIO[0]: ! I_INV	INT: mux CELL.OUT_IO_WE_I2[0] bit 0	HIO[0]: !invert T	INT: mux CELL.IMUX_IO_O1[0] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 1	INT: mux CELL.IMUX_IO_O1[0] bit 2	INT: mux CELL.LONG_IO_V[1] bit 0	INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W0[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W0[1]	INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W1[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W1[1]	INT: !bipass CELL.DOUBLE_IO_W0[1] = CELL.DOUBLE_IO_W2[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W2[1]	INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W2[1]	INT: !pass CELL.SINGLE_H[7] ← CELL.DEC_V[0]	-	INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_W0[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W0[3]	INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_W1[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W1[3]	INT: !bipass CELL.DOUBLE_IO_W0[3] = CELL.DOUBLE_IO_W2[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W2[3]	INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_W2[3]
B8	HIO[1]: ! READBACK_I bit 0	HIO[0]: !invert O	HIO[0]: ! READBACK_I bit 0	-	INT: mux CELL.IMUX_HIO_T[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 4	INT: mux CELL.IMUX_IO_O1[0] bit 5	INT: mux CELL.DBUF_IO_V[1] bit 2	INT: mux CELL.DBUF_IO_V[1] bit 1	INT: mux CELL.DBUF_IO_V[1] bit 0	INT: mux CELL.DBUF_IO_V[1] bit 3	INT: mux CELL.LONG_IO_V[1] bit 3	INT: mux CELL.LONG_IO_V[1] bit 1	INT: mux CELL.LONG_IO_V[1] bit 2	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1	INT: mux CELL.LONG_IO_V[3] bit 0	INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_IO_V[3]	-	INT: mux CELL.LONG_IO_V[3] bit 1	INT: mux CELL.LONG_IO_V[2] bit 3	INT: mux CELL.LONG_IO_V[2] bit 1	INT: mux CELL.LONG_IO_V[2] bit 0	INT: mux CELL.LONG_IO_V[2] bit 2	INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_IO_WE_I1[0]	INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_IO_WE_I1_S1
B7	INT: mux CELL.IMUX_HIO_O[0] bit 0	HIO[0]: PULL bit 1	HIO[0]: PULL bit 0	HIO[0]: OMODE bit 0	HIO[1]: OMODE bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 6	INT: mux CELL.IMUX_IO_IK[0] bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 3	INT: mux CELL.IMUX_IO_IK[0] bit 2	INT: mux CELL.IMUX_IO_IK[0] bit 4	INT: mux CELL.IMUX_IO_IK[0] bit 1	INT: mux CELL.IMUX_IO_IK[0] bit 5	INT: mux CELL.IMUX_IO_IK[0] bit 7	INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[1]	PULLUP_TBUF[1]: ! ENABLE	INT: mux CELL.LONG_H[5] bit 3	INT: !pass CELL.DOUBLE_IO_W2[1] ← CELL.DBUF_IO_V[0]	INT: !pass CELL.DOUBLE_IO_W2[3] ← CELL.DBUF_IO_V[0]	-	INT: mux CELL.LONG_H[5] bit 1	INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1[0]	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0]	INT: mux CELL.LONG_H[4] bit 1	INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1_S1	INT: mux CELL.LONG_H[4] bit 0	-
B6	HIO[1]: !invert T	INT: mux CELL.IMUX_HIO_T[1] bit 0	HIO[1]: !invert O	INT: mux CELL.IMUX_HIO_O[1] bit 0	HIO[1]: PULL bit 1	DEC[1]: ! O4_P	DEC[1]: ! O2_P	INT: mux CELL.IMUX_IO_OK[0] bit 5	HIO[1]: PULL bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 3	INT: mux CELL.IMUX_IO_OK[0] bit 2	DEC[1]: O1_N	INT: mux CELL.IMUX_IO_OK[0] bit 4	INT: mux CELL.IMUX_IO_OK[0] bit 1	INT: !pass CELL.DOUBLE_IO_W0[1] ← CELL.DBUF_IO_V[1]	INT: mux CELL.IMUX_IO_OK[0] bit 7	INT: !pass CELL.DOUBLE_IO_W2[2] ← CELL.DBUF_IO_V[0]	-	INT: !pass CELL.DOUBLE_IO_W2[0] ← CELL.DBUF_IO_V[0]	INT: mux CELL.LONG_H[5] bit 0	INT: mux CELL.LONG_H[5] bit 2	INT: !pass CELL.DOUBLE_IO_W0[3] ← CELL.DBUF_IO_V[1]	INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2[0]	INT: mux CELL.LONG_H[4] bit 3	INT: mux CELL.LONG_H[4] bit 2
B5	INT: mux CELL.OUT_IO_WE_I1[0] bit 0	HIO[1]: ! I_INV	HIO[1]: ISTD bit 0	HIO[1]: OSTD bit 0	DEC[2]: O4_P	DEC[1]: O4_N	DEC[1]: O2_N	DEC[2]: ! O2_N	INT: mux CELL.IMUX_IO_OK[0] bit 6	DEC[2]: ! O3_N	INT: !pass CELL.SINGLE_H[4] ← CELL.DEC_V[1]	DEC[2]: O1_P	DEC[1]: ! O1_P	INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_W0[2]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W0[2]	INT: !pass CELL.DOUBLE_IO_W0[0] ← CELL.DBUF_IO_V[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W0[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W0[0]	INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[3]	INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W1[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W1[0]	INT: mux CELL.LONG_IO_V[0] bit 1	INT: !bipass CELL.DOUBLE_IO_W0[0] = CELL.DOUBLE_IO_W2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W2[0]	INT: mux CELL.LONG_IO_V[0] bit 0	INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W2[0]
B4	HIO[2]: ! I_INV	INT: mux CELL.OUT_IO_WE_I1[1] bit 0	HIO[2]: ISTD bit 0	HIO[2]: OSTD bit 0	DEC[2]: ! O4_N	DEC[0]: ! O4_P	DEC[0]: O2_N	DEC[2]: O2_P	DEC[1]: O3_N	DEC[2]: O3_P	DEC[0]: ! O3_P	DEC[2]: ! O1_N	DEC[0]: ! O1_P	INT: !pass CELL.DOUBLE_IO_W0[2] ← CELL.DBUF_IO_V[1]	INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_W1[2]	INT: !bipass CELL.DOUBLE_IO_W0[2] = CELL.DOUBLE_IO_W2[2]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W2[2]	INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_W2[2]	INT: mux CELL.IMUX_IO_T[0] bit 5	INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_IO_V[2]	INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[0]	INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_WE_I2_S1
B3	HIO[2]: !invert T	INT: mux CELL.IMUX_HIO_T[2] bit 0	HIO[2]: !invert O	HIO[3]: ! READBACK_I bit 0	HIO[2]: ! READBACK_I bit 0	DEC[0]: O4_N	DEC[0]: ! O2_P	INT: mux CELL.IMUX_IO_IK[1] bit 5	DEC[1]: ! O3_P	HIO[2]: PULL bit 1	DEC[0]: O3_N	INT: mux CELL.IMUX_IO_IK[1] bit 7	DEC[0]: O1_N	TBUF[1]: ! DRIVE1	INT: mux CELL.IMUX_IO_T[1] bit 2	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W1[2]	INT: mux CELL.IMUX_IO_T[1] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 4	-	INT: mux CELL.IMUX_IO_T[0] bit 2	INT: mux CELL.IMUX_IO_T[0] bit 0	INT: mux CELL.DBUF_IO_V[0] bit 1	INT: mux CELL.DBUF_IO_V[0] bit 0	INT: mux CELL.IMUX_IO_T[0] bit 4	INT: mux CELL.IMUX_IO_T[0] bit 7	TBUF[0]: ! DRIVE1
B2	HIO[3]: OMODE bit 0	HIO[2]: OMODE bit 0	-	HIO[2]: PULL bit 0	INT: mux CELL.IMUX_HIO_O[2] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 3	INT: mux CELL.IMUX_IO_OK[1] bit 6	INT: mux CELL.IMUX_IO_OK[1] bit 5	INT: mux CELL.IMUX_IO_OK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 0	INT: mux CELL.IMUX_IO_IK[1] bit 4	INT: mux CELL.IMUX_IO_OK[1] bit 4	INT: mux CELL.IMUX_IO_OK[1] bit 2	INT: mux CELL.IMUX_IO_OK[1] bit 7	INT: mux CELL.IMUX_IO_T[1] bit 0	INT: mux CELL.IMUX_IO_T[1] bit 1	-	INT: mux CELL.IMUX_IO_T[1] bit 5	INT: mux CELL.IMUX_IO_T[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 6	INT: mux CELL.DBUF_IO_V[0] bit 2	INT: mux CELL.IMUX_IO_T[1] bit 7	INT: mux CELL.DBUF_IO_V[0] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 6
B1	HIO[3]: PULL bit 1	HIO[3]: PULL bit 0	INT: mux CELL.IMUX_HIO_O[3] bit 0	HIO[3]: !invert O	INT: mux CELL.IMUX_HIO_T[3] bit 0	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 3	INT: mux CELL.IMUX_IO_IK[1] bit 6	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 5	INT: mux CELL.LONG_H[1] bit 3	INT: mux CELL.LONG_H[1] bit 2	INT: mux CELL.IMUX_TBUF_I[1] bit 3	INT: mux CELL.IMUX_TBUF_I[1] bit 0	INT: mux CELL.IMUX_TBUF_I[1] bit 5	INT: mux CELL.IMUX_TBUF_T[1] bit 3	INT: mux CELL.IMUX_TBUF_T[1] bit 0	INT: mux CELL.IMUX_TBUF_T[1] bit 4	INT: mux CELL.IMUX_TBUF_T[1] bit 5	INT: mux CELL.IMUX_TBUF_T[0] bit 1	INT: mux CELL.IMUX_TBUF_T[0] bit 5	INT: mux CELL.IMUX_TBUF_I[0] bit 3	INT: mux CELL.IMUX_TBUF_I[0] bit 0	INT: mux CELL.IMUX_TBUF_I[0] bit 5	INT: mux CELL.LONG_H[0] bit 3	INT: mux CELL.LONG_H[0] bit 2
B0	HIO[3]: OSTD bit 0	HIO[3]: ISTD bit 0	HIO[3]: ! I_INV	INT: mux CELL.OUT_IO_WE_I2[1] bit 0	HIO[3]: !invert T	INT: mux CELL.IMUX_IO_O1[1] bit 4	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 0	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.LONG_H[1] bit 1	INT: mux CELL.LONG_H[1] bit 0	INT: mux CELL.IMUX_TBUF_I[1] bit 4	INT: mux CELL.IMUX_TBUF_I[1] bit 1	INT: mux CELL.IMUX_TBUF_I[1] bit 2	INT: mux CELL.IMUX_TBUF_T[1] bit 2	INT: mux CELL.IMUX_TBUF_T[1] bit 1	INT: mux CELL.IMUX_TBUF_T[0] bit 2	INT: mux CELL.IMUX_TBUF_T[0] bit 0	INT: mux CELL.IMUX_TBUF_T[0] bit 4	INT: mux CELL.IMUX_TBUF_T[0] bit 3	INT: mux CELL.IMUX_TBUF_I[0] bit 2	INT: mux CELL.IMUX_TBUF_I[0] bit 1	INT: mux CELL.IMUX_TBUF_I[0] bit 4	INT: mux CELL.LONG_H[0] bit 0	INT: mux CELL.LONG_H[0] bit 1

xc4000h IO_W0_N rect MAIN_S
Bit	Frame
Bit	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PULLUP_TBUF[0]: ! ENABLE
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile IO_W1

Cells: 4

Switchbox INT

xc4000h IO_W1 switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[0]	CELL.DEC_V[3]	!MAIN[7][5]
CELL.SINGLE_H[0]	CELL.OUT_IO_WE_I2_S1	!MAIN[1][4]
CELL.SINGLE_H[1]	CELL.LONG_IO_V[0]	!MAIN[3][4]
CELL.SINGLE_H[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[4][4]
CELL.SINGLE_H[2]	CELL.LONG_IO_V[1]	!MAIN[12][7]
CELL.SINGLE_H[2]	CELL.OUT_IO_WE_I1[0]	!MAIN[4][7]
CELL.SINGLE_H[3]	CELL.DEC_V[2]	!MAIN[16][9]
CELL.SINGLE_H[3]	CELL.OUT_IO_WE_I1_S1	!MAIN[10][8]
CELL.SINGLE_H[4]	CELL.DEC_V[1]	!MAIN[15][5]
CELL.SINGLE_H[4]	CELL.OUT_IO_WE_I2_S1	!MAIN[0][4]
CELL.SINGLE_H[5]	CELL.LONG_IO_V[2]	!MAIN[6][4]
CELL.SINGLE_H[5]	CELL.OUT_IO_WE_I2[0]	!MAIN[5][4]
CELL.SINGLE_H[6]	CELL.LONG_IO_V[3]	!MAIN[8][8]
CELL.SINGLE_H[6]	CELL.OUT_IO_WE_I1[0]	!MAIN[1][8]
CELL.SINGLE_H[7]	CELL.DEC_V[0]	!MAIN[8][9]
CELL.SINGLE_H[7]	CELL.OUT_IO_WE_I1_S1	!MAIN[0][8]
CELL.DOUBLE_H0[0]	CELL.OUT_IO_WE_I1_S1	!MAIN[2][7]
CELL.DOUBLE_H0[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[2][6]
CELL.DOUBLE_H1[0]	CELL.OUT_IO_WE_I1[0]	!MAIN[5][7]
CELL.DOUBLE_H1[1]	CELL.OUT_IO_WE_I2_S1	!MAIN[2][4]
CELL.DOUBLE_IO_W0[0]	CELL.DBUF_IO_V[1]	!MAIN[10][5]
CELL.DOUBLE_IO_W0[1]	CELL.DBUF_IO_V[1]	!MAIN[10][6]
CELL.DOUBLE_IO_W0[2]	CELL.DBUF_IO_V[1]	!MAIN[12][4]
CELL.DOUBLE_IO_W0[3]	CELL.DBUF_IO_V[1]	!MAIN[3][6]
CELL.DOUBLE_IO_W2[0]	CELL.DBUF_IO_V[0]	!MAIN[6][6]
CELL.DOUBLE_IO_W2[1]	CELL.DBUF_IO_V[0]	!MAIN[9][7]
CELL.DOUBLE_IO_W2[2]	CELL.DBUF_IO_V[0]	!MAIN[8][6]
CELL.DOUBLE_IO_W2[3]	CELL.DBUF_IO_V[0]	!MAIN[8][7]

xc4000h IO_W1 switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.DOUBLE_IO_W1[0]	!MAIN[6][5]
CELL.SINGLE_H[1]	CELL.DOUBLE_IO_W0[0]	!MAIN[9][5]
CELL.SINGLE_H[1]	CELL.DOUBLE_IO_W2[0]	!MAIN[0][5]
CELL.SINGLE_H[2]	CELL.DOUBLE_IO_W1[1]	!MAIN[13][9]
CELL.SINGLE_H[3]	CELL.DOUBLE_IO_W0[1]	!MAIN[15][9]
CELL.SINGLE_H[3]	CELL.DOUBLE_IO_W2[1]	!MAIN[9][9]
CELL.SINGLE_H[4]	CELL.DOUBLE_IO_W1[2]	!MAIN[11][4]
CELL.SINGLE_H[5]	CELL.DOUBLE_IO_W0[2]	!MAIN[12][5]
CELL.SINGLE_H[5]	CELL.DOUBLE_IO_W2[2]	!MAIN[8][4]
CELL.SINGLE_H[6]	CELL.DOUBLE_IO_W1[3]	!MAIN[4][9]
CELL.SINGLE_H[7]	CELL.DOUBLE_IO_W0[3]	!MAIN[6][9]
CELL.SINGLE_H[7]	CELL.DOUBLE_IO_W2[3]	!MAIN[0][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_W0[0]	!MAIN[8][5]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_W1[0]	!MAIN[5][5]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_W2[0]	!MAIN[2][5]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_W0[3]	!MAIN[5][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_W1[3]	!MAIN[3][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_W2[3]	!MAIN[1][9]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_W0[1]	!MAIN[14][9]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_W1[1]	!MAIN[12][9]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_W2[1]	!MAIN[10][9]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_W0[2]	!MAIN[11][5]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_W1[2]	!MAIN[10][3]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_W2[2]	!MAIN[9][4]
CELL.DOUBLE_IO_W0[0]	CELL.DOUBLE_IO_W2[0]	!MAIN[3][5]
CELL.DOUBLE_IO_W0[1]	CELL.DOUBLE_IO_W2[1]	!MAIN[11][9]
CELL.DOUBLE_IO_W0[2]	CELL.DOUBLE_IO_W2[2]	!MAIN[10][4]
CELL.DOUBLE_IO_W0[3]	CELL.DOUBLE_IO_W2[3]	!MAIN[2][9]

xc4000h IO_W1 switchbox INT muxes DBUF_IO_V[0]
Bits				Destination
MAIN[1][2]	MAIN[3][2]	MAIN[4][3]	MAIN[3][3]	CELL.DBUF_IO_V[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_W0[1]
0	1	0	1	CELL.DOUBLE_IO_W0[2]
0	1	1	0	CELL.DOUBLE_IO_W0[3]
1	1	1	1	CELL.DOUBLE_IO_W0[0]

xc4000h IO_W1 switchbox INT muxes DBUF_IO_V[1]
Bits				Destination
MAIN[14][8]	MAIN[17][8]	MAIN[16][8]	MAIN[15][8]	CELL.DBUF_IO_V[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_W2[0]
0	1	0	1	CELL.DOUBLE_IO_W2[1]
0	1	1	0	CELL.DOUBLE_IO_W2[3]
1	1	1	1	CELL.DOUBLE_IO_W2[2]

xc4000h IO_W1 switchbox INT muxes LONG_H[0]
Bits				Destination
MAIN[1][1]	MAIN[0][1]	MAIN[0][0]	MAIN[1][0]	CELL.LONG_H[0]
				Source
0	0	0	1	CELL.LONG_IO_V[0]
0	0	1	0	CELL.DEC_V[0]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000h IO_W1 switchbox INT muxes LONG_H[1]
Bits				Destination
MAIN[15][1]	MAIN[14][1]	MAIN[15][0]	MAIN[14][0]	CELL.LONG_H[1]
				Source
0	0	0	1	CELL.LONG_IO_V[1]
0	0	1	0	CELL.DEC_V[1]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000h IO_W1 switchbox INT muxes LONG_H[4]
Bits				Destination
MAIN[1][6]	MAIN[0][6]	MAIN[3][7]	MAIN[1][7]	CELL.LONG_H[4]
				Source
0	0	0	1	CELL.LONG_IO_V[2]
0	0	1	0	CELL.DEC_V[2]
0	1	1	1	CELL.OUT_IO_WE_I2[0]
1	1	1	1	off

xc4000h IO_W1 switchbox INT muxes LONG_H[5]
Bits				Destination
MAIN[10][7]	MAIN[4][6]	MAIN[6][7]	MAIN[5][6]	CELL.LONG_H[5]
				Source
0	0	0	1	CELL.LONG_IO_V[3]
0	0	1	0	CELL.DEC_V[3]
0	1	1	1	CELL.OUT_IO_WE_I2[0]
1	1	1	1	off

xc4000h IO_W1 switchbox INT muxes LONG_IO_V[0]
Bits		Destination
MAIN[4][5]	MAIN[1][5]	CELL.LONG_IO_V[0]
		Source
0	0	CELL.LONG_H[0]
0	1	CELL.SINGLE_H[1]
1	1	off

xc4000h IO_W1 switchbox INT muxes LONG_IO_V[1]
Bits				Destination
MAIN[13][8]	MAIN[11][8]	MAIN[12][8]	MAIN[17][9]	CELL.LONG_IO_V[1]
				Source
0	0	0	1	CELL.LONG_H[1]
0	0	1	0	CELL.LONG_H[3]
0	1	1	1	CELL.SINGLE_H[2]
1	1	1	1	off

xc4000h IO_W1 switchbox INT muxes LONG_IO_V[2]
Bits				Destination
MAIN[5][8]	MAIN[2][8]	MAIN[4][8]	MAIN[3][8]	CELL.LONG_IO_V[2]
				Source
0	0	0	1	CELL.LONG_H[2]
0	0	1	0	CELL.LONG_H[4]
0	1	1	1	CELL.SINGLE_H[5]
1	1	1	1	off

xc4000h IO_W1 switchbox INT muxes LONG_IO_V[3]
Bits		Destination
MAIN[6][8]	MAIN[9][8]	CELL.LONG_IO_V[3]
		Source
0	0	CELL.LONG_H[5]
0	1	CELL.SINGLE_H[6]
1	1	off

xc4000h IO_W1 switchbox INT muxes IMUX_TBUF_I[0]
Bits						Destination
MAIN[2][1]	MAIN[2][0]	MAIN[4][1]	MAIN[4][0]	MAIN[3][0]	MAIN[3][1]	CELL.IMUX_TBUF_I[0]
						Source
0	0	0	1	1	1	CELL.OUT_IO_WE_I2[0]
0	0	1	0	1	1	CELL.DOUBLE_IO_W1[2]
0	0	1	1	0	1	CELL.LONG_IO_V[2]
0	0	1	1	1	0	CELL.DEC_V[2]
0	1	1	1	1	1	CELL.DOUBLE_IO_W0[2]
1	0	0	1	1	1	CELL.DOUBLE_IO_W0[3]
1	0	1	0	1	1	CELL.DOUBLE_IO_W1[3]
1	0	1	1	0	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_W1 switchbox INT muxes IMUX_TBUF_I[1]
Bits						Destination
MAIN[11][1]	MAIN[13][0]	MAIN[13][1]	MAIN[11][0]	MAIN[12][0]	MAIN[12][1]	CELL.IMUX_TBUF_I[1]
						Source
0	0	0	1	1	1	CELL.DOUBLE_IO_W0[2]
0	0	1	0	1	1	CELL.OUT_IO_WE_I2[0]
0	0	1	1	0	1	CELL.LONG_IO_V[1]
0	0	1	1	1	0	CELL.DEC_V[1]
0	1	0	1	1	1	CELL.DOUBLE_IO_W1[3]
0	1	1	0	1	1	CELL.DOUBLE_IO_W0[3]
0	1	1	1	1	0	CELL.OUT_IO_WE_I2[1]
1	0	1	1	1	1	CELL.DOUBLE_IO_W1[2]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_W1 switchbox INT muxes IMUX_TBUF_T[0]
Bits						Destination
MAIN[5][1]	MAIN[6][0]	MAIN[5][0]	MAIN[8][0]	MAIN[6][1]	MAIN[7][0]	CELL.IMUX_TBUF_T[0]
						Source
0	0	0	1	1	1	CELL.TIE_1
0	0	1	1	1	1	CELL.TIE_0
0	1	0	0	1	1	CELL.DOUBLE_IO_W0[1]
0	1	0	1	0	1	CELL.LONG_IO_V[3]
0	1	0	1	1	0	CELL.DEC_V[0]
0	1	1	0	1	1	CELL.DOUBLE_IO_W1[1]
0	1	1	1	0	1	CELL.LONG_IO_V[2]
0	1	1	1	1	0	CELL.DEC_V[3]
1	1	0	1	1	1	CELL.DOUBLE_IO_W0[0]
1	1	1	1	1	1	CELL.DOUBLE_IO_W1[0]

xc4000h IO_W1 switchbox INT muxes IMUX_TBUF_T[1]
Bits						Destination
MAIN[7][1]	MAIN[8][1]	MAIN[10][1]	MAIN[10][0]	MAIN[9][0]	MAIN[9][1]	CELL.IMUX_TBUF_T[1]
						Source
0	0	0	1	1	1	CELL.TIE_1
0	0	1	1	1	1	CELL.TIE_0
0	1	0	0	1	1	CELL.DOUBLE_IO_W1[0]
0	1	0	1	0	1	CELL.LONG_IO_V[2]
0	1	0	1	1	0	CELL.DEC_V[3]
0	1	1	0	1	1	CELL.DOUBLE_IO_W0[0]
0	1	1	1	0	1	CELL.LONG_IO_V[3]
0	1	1	1	1	0	CELL.DEC_V[0]
1	1	0	1	1	1	CELL.DOUBLE_IO_W1[1]
1	1	1	1	1	1	CELL.DOUBLE_IO_W0[1]

xc4000h IO_W1 switchbox INT muxes IMUX_IO_O1[0]
Bits						Destination
MAIN[18][8]	MAIN[19][8]	MAIN[20][9]	MAIN[18][9]	MAIN[19][9]	MAIN[20][8]	CELL.IMUX_IO_O1[0]
						Source
0	0	0	1	1	1	CELL.DEC_V[0]
0	0	1	1	1	1	CELL.DOUBLE_H0[0]
0	1	0	0	1	1	CELL.DEC_V[1]
0	1	0	1	0	1	CELL.DEC_V[2]
0	1	0	1	1	0	CELL.DEC_V[3]
0	1	1	0	1	1	CELL.LONG_H[3]
0	1	1	1	0	1	CELL.LONG_H[4]
0	1	1	1	1	0	CELL.LONG_H[5]
1	1	0	1	1	1	CELL.DOUBLE_H1[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_W1 switchbox INT muxes IMUX_IO_O1[1]
Bits						Destination
MAIN[16][1]	MAIN[20][0]	MAIN[19][0]	MAIN[18][0]	MAIN[16][0]	MAIN[17][0]	CELL.IMUX_IO_O1[1]
						Source
0	0	0	1	1	1	CELL.LONG_H[0]
0	0	1	0	1	1	CELL.LONG_H[1]
0	0	1	1	0	1	CELL.DEC_V[0]
0	0	1	1	1	0	CELL.DEC_V[1]
0	1	0	1	1	1	CELL_S.DOUBLE_H0[1]
0	1	1	0	1	1	CELL.LONG_H[2]
0	1	1	1	0	1	CELL.DEC_V[2]
0	1	1	1	1	0	CELL.DEC_V[3]
1	0	1	1	1	1	CELL_S.DOUBLE_H1[0]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_W1 switchbox INT muxes IMUX_IO_OK[0]
Bits								Destination
MAIN[9][6]	MAIN[17][5]	MAIN[18][6]	MAIN[12][6]	MAIN[15][6]	MAIN[14][6]	MAIN[11][6]	MAIN[16][6]	CELL.IMUX_IO_OK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_H[3]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[2]

xc4000h IO_W1 switchbox INT muxes IMUX_IO_OK[1]
Bits								Destination
MAIN[11][2]	MAIN[18][2]	MAIN[17][2]	MAIN[13][2]	MAIN[19][2]	MAIN[12][2]	MAIN[16][2]	MAIN[20][2]	CELL.IMUX_IO_OK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_S.SINGLE_H[2]
0	1	1	1	1	1	0	1	CELL_S.SINGLE_H[4]
0	1	1	1	1	1	1	0	CELL_S.SINGLE_H[5]
1	1	1	1	1	1	1	1	CELL_S.SINGLE_H[3]

xc4000h IO_W1 switchbox INT muxes IMUX_IO_IK[0]
Bits								Destination
MAIN[13][7]	MAIN[20][7]	MAIN[14][7]	MAIN[16][7]	MAIN[18][7]	MAIN[17][7]	MAIN[15][7]	MAIN[19][7]	CELL.IMUX_IO_IK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_H[2]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[3]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[4]

xc4000h IO_W1 switchbox INT muxes IMUX_IO_IK[1]
Bits								Destination
MAIN[14][3]	MAIN[18][1]	MAIN[18][3]	MAIN[14][2]	MAIN[19][1]	MAIN[17][1]	MAIN[20][1]	MAIN[15][2]	CELL.IMUX_IO_IK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_S.SINGLE_H[2]
0	1	1	1	1	1	0	1	CELL_S.SINGLE_H[3]
0	1	1	1	1	1	1	0	CELL_S.SINGLE_H[4]
1	1	1	1	1	1	1	1	CELL_S.SINGLE_H[5]

xc4000h IO_W1 switchbox INT muxes IMUX_IO_T[0]
Bits								Destination
MAIN[1][3]	MAIN[4][2]	MAIN[7][4]	MAIN[2][3]	MAIN[6][2]	MAIN[6][3]	MAIN[5][2]	MAIN[5][3]	CELL.IMUX_IO_T[0]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	0	1	1	1	CELL.LONG_IO_V[3]
0	0	1	0	1	0	1	1	CELL.LONG_IO_V[0]
0	0	1	1	0	1	0	1	CELL.LONG_IO_V[1]
0	0	1	1	0	1	1	0	CELL.GCLK[0]
0	0	1	1	1	0	0	1	CELL.DEC_V[1]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_W0[1]
0	1	1	1	1	1	0	1	CELL.LONG_IO_V[2]
0	1	1	1	1	1	1	0	CELL.DEC_V[0]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_W1[0]
1	0	1	1	1	0	1	1	CELL.DOUBLE_IO_W1[1]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_W0[0]

xc4000h IO_W1 switchbox INT muxes IMUX_IO_T[1]
Bits								Destination
MAIN[2][2]	MAIN[0][2]	MAIN[7][2]	MAIN[8][3]	MAIN[9][3]	MAIN[11][3]	MAIN[9][2]	MAIN[10][2]	CELL.IMUX_IO_T[1]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	1	0	1	1	CELL.DEC_V[1]
0	0	1	0	1	1	0	1	CELL.LONG_IO_V[0]
0	0	1	1	0	0	1	1	CELL.DOUBLE_IO_W0[1]
0	0	1	1	0	1	0	1	CELL.LONG_IO_V[2]
0	0	1	1	0	1	1	0	CELL.DEC_V[0]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_W0[0]
0	1	1	1	0	1	1	1	CELL.DOUBLE_IO_W1[1]
1	0	1	1	1	0	1	1	CELL.LONG_IO_V[1]
1	0	1	1	1	1	0	1	CELL.LONG_IO_V[3]
1	0	1	1	1	1	1	0	CELL.GCLK[0]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_W1[0]

xc4000h IO_W1 switchbox INT muxes IMUX_HIO_O[0]
Bits	Destination
MAIN[25][7]	CELL.IMUX_HIO_O[0]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_G3_W

xc4000h IO_W1 switchbox INT muxes IMUX_HIO_O[1]
Bits	Destination
MAIN[22][6]	CELL.IMUX_HIO_O[1]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_G3_W

xc4000h IO_W1 switchbox INT muxes IMUX_HIO_O[2]
Bits	Destination
MAIN[21][2]	CELL.IMUX_HIO_O[2]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_F3_W

xc4000h IO_W1 switchbox INT muxes IMUX_HIO_O[3]
Bits	Destination
MAIN[23][1]	CELL.IMUX_HIO_O[3]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_F3_W

xc4000h IO_W1 switchbox INT muxes IMUX_HIO_T[0]
Bits	Destination
MAIN[21][8]	CELL.IMUX_HIO_T[0]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_OK[0]

xc4000h IO_W1 switchbox INT muxes IMUX_HIO_T[1]
Bits	Destination
MAIN[24][6]	CELL.IMUX_HIO_T[1]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_IK[0]

xc4000h IO_W1 switchbox INT muxes IMUX_HIO_T[2]
Bits	Destination
MAIN[24][3]	CELL.IMUX_HIO_T[2]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_IK[1]

xc4000h IO_W1 switchbox INT muxes IMUX_HIO_T[3]
Bits	Destination
MAIN[21][1]	CELL.IMUX_HIO_T[3]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_OK[1]

xc4000h IO_W1 switchbox INT muxes OUT_IO_WE_I1[0]
Bits	Destination
MAIN[25][5]	CELL.OUT_IO_WE_I1[0]
	Source
0	CELL.OUT_HIO_I[1]
1	CELL.OUT_HIO_I[0]

xc4000h IO_W1 switchbox INT muxes OUT_IO_WE_I1[1]
Bits	Destination
MAIN[24][4]	CELL.OUT_IO_WE_I1[1]
	Source
0	CELL.OUT_HIO_I[2]
1	CELL.OUT_HIO_I[3]

xc4000h IO_W1 switchbox INT muxes OUT_IO_WE_I2[0]
Bits	Destination
MAIN[22][9]	CELL.OUT_IO_WE_I2[0]
	Source
0	CELL.OUT_HIO_I[0]
1	CELL.OUT_HIO_I[1]

xc4000h IO_W1 switchbox INT muxes OUT_IO_WE_I2[1]
Bits	Destination
MAIN[22][0]	CELL.OUT_IO_WE_I2[1]
	Source
0	CELL.OUT_HIO_I[3]
1	CELL.OUT_HIO_I[2]

Bels TBUF

xc4000h IO_W1 bel TBUF pins
Pin	Direction	TBUF[0]	TBUF[1]
I	in	CELL.IMUX_TBUF_I[0]	CELL.IMUX_TBUF_I[1]
T	in	CELL.IMUX_TBUF_T[0]	CELL.IMUX_TBUF_T[1]
O	bidir	CELL.LONG_H[2]	CELL.LONG_H[3]

xc4000h IO_W1 bel TBUF attribute bits
Attribute	TBUF[0]	TBUF[1]
DRIVE1	!MAIN[0][3]	!MAIN[12][3]

Bels HIO

xc4000h IO_W1 bel HIO pins
Pin	Direction	HIO[0]	HIO[1]	HIO[2]	HIO[3]
O	in	CELL.IMUX_HIO_O[0] invert by !MAIN[24][8]	CELL.IMUX_HIO_O[1] invert by !MAIN[23][6]	CELL.IMUX_HIO_O[2] invert by !MAIN[23][3]	CELL.IMUX_HIO_O[3] invert by !MAIN[22][1]
T	in	CELL.IMUX_HIO_T[0] invert by !MAIN[21][9]	CELL.IMUX_HIO_T[1] invert by !MAIN[25][6]	CELL.IMUX_HIO_T[2] invert by !MAIN[25][3]	CELL.IMUX_HIO_T[3] invert by !MAIN[21][0]
I	out	CELL.OUT_HIO_I[0]	CELL.OUT_HIO_I[1]	CELL.OUT_HIO_I[2]	CELL.OUT_HIO_I[3]

xc4000h IO_W1 bel HIO attribute bits
Attribute	HIO[0]	HIO[1]	HIO[2]	HIO[3]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
ISTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OSTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OMODE	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]
I_INV	!MAIN[23][9]	!MAIN[24][5]	!MAIN[25][4]	!MAIN[23][0]
READBACK_I bit 0	!MAIN[23][8]	!MAIN[25][8]	!MAIN[21][3]	!MAIN[22][3]

xc4000h IO_W1 enum IO_PULL
HIO[0].PULL	MAIN[24][7]	MAIN[23][7]
HIO[1].PULL	MAIN[21][6]	MAIN[17][6]
HIO[2].PULL	MAIN[16][3]	MAIN[22][2]
HIO[3].PULL	MAIN[25][1]	MAIN[24][1]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

xc4000h IO_W1 enum IO_STD
HIO[0].ISTD	MAIN[24][9]
HIO[1].ISTD	MAIN[23][5]
HIO[2].ISTD	MAIN[23][4]
HIO[3].ISTD	MAIN[24][0]
CMOS	0
TTL	1

xc4000h IO_W1 enum IO_STD
HIO[0].OSTD	MAIN[25][9]
HIO[1].OSTD	MAIN[22][5]
HIO[2].OSTD	MAIN[22][4]
HIO[3].OSTD	MAIN[25][0]
CMOS	1
TTL	0

xc4000h IO_W1 enum HIO_OMODE
HIO[0].OMODE	MAIN[22][7]
HIO[1].OMODE	MAIN[21][7]
HIO[2].OMODE	MAIN[24][2]
HIO[3].OMODE	MAIN[25][2]
CAP	1
RES	0

Bels DEC

xc4000h IO_W1 bel DEC pins
Pin	Direction	DEC[0]	DEC[1]	DEC[2]
I	in	CELL.OUT_IO_WE_I1[0]	CELL.IMUX_CLB_C3_W	CELL.OUT_IO_WE_I1[1]
O1	bidir	CELL.DEC_V[0]	CELL.DEC_V[0]	CELL.DEC_V[0]
O2	bidir	CELL.DEC_V[1]	CELL.DEC_V[1]	CELL.DEC_V[1]
O3	bidir	CELL.DEC_V[2]	CELL.DEC_V[2]	CELL.DEC_V[2]
O4	bidir	CELL.DEC_V[3]	CELL.DEC_V[3]	CELL.DEC_V[3]

xc4000h IO_W1 bel DEC attribute bits
Attribute	DEC[0]	DEC[1]	DEC[2]
O1_P	!MAIN[13][4]	!MAIN[13][5]	MAIN[14][5]
O1_N	MAIN[13][3]	MAIN[13][6]	!MAIN[14][4]
O2_P	!MAIN[19][3]	!MAIN[19][6]	MAIN[18][4]
O2_N	MAIN[19][4]	MAIN[19][5]	!MAIN[18][5]
O3_P	!MAIN[15][4]	!MAIN[17][3]	MAIN[16][4]
O3_N	MAIN[15][3]	MAIN[17][4]	!MAIN[16][5]
O4_P	!MAIN[20][4]	!MAIN[20][6]	MAIN[21][5]
O4_N	MAIN[20][3]	MAIN[20][5]	!MAIN[21][4]

Bels PULLUP

xc4000h IO_W1 bel PULLUP pins
Pin	Direction	PULLUP_TBUF[0]	PULLUP_TBUF[1]
O	bidir	CELL.LONG_H[2]	CELL.LONG_H[3]

xc4000h IO_W1 bel PULLUP attribute bits
Attribute	PULLUP_TBUF[0]	PULLUP_TBUF[1]
ENABLE	!MAIN_S[0][7]	!MAIN[11][7]

Bel wires

xc4000h IO_W1 bel wires
Wire	Pins
CELL.LONG_H[2]	TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]	TBUF[1].O, PULLUP_TBUF[1].O
CELL.DEC_V[0]	DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_V[1]	DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.DEC_V[2]	DEC[0].O3, DEC[1].O3, DEC[2].O3
CELL.DEC_V[3]	DEC[0].O4, DEC[1].O4, DEC[2].O4
CELL.IMUX_CLB_C3_W	DEC[1].I
CELL.IMUX_TBUF_I[0]	TBUF[0].I
CELL.IMUX_TBUF_I[1]	TBUF[1].I
CELL.IMUX_TBUF_T[0]	TBUF[0].T
CELL.IMUX_TBUF_T[1]	TBUF[1].T
CELL.IMUX_HIO_O[0]	HIO[0].O
CELL.IMUX_HIO_O[1]	HIO[1].O
CELL.IMUX_HIO_O[2]	HIO[2].O
CELL.IMUX_HIO_O[3]	HIO[3].O
CELL.IMUX_HIO_T[0]	HIO[0].T
CELL.IMUX_HIO_T[1]	HIO[1].T
CELL.IMUX_HIO_T[2]	HIO[2].T
CELL.IMUX_HIO_T[3]	HIO[3].T
CELL.OUT_IO_WE_I1[0]	DEC[0].I
CELL.OUT_IO_WE_I1[1]	DEC[2].I
CELL.OUT_HIO_I[0]	HIO[0].I
CELL.OUT_HIO_I[1]	HIO[1].I
CELL.OUT_HIO_I[2]	HIO[2].I
CELL.OUT_HIO_I[3]	HIO[3].I

Bitstream

xc4000h IO_W1 rect MAIN
Bit	Frame
Bit	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	HIO[0]: OSTD bit 0	HIO[0]: ISTD bit 0	HIO[0]: ! I_INV	INT: mux CELL.OUT_IO_WE_I2[0] bit 0	HIO[0]: !invert T	INT: mux CELL.IMUX_IO_O1[0] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 1	INT: mux CELL.IMUX_IO_O1[0] bit 2	INT: mux CELL.LONG_IO_V[1] bit 0	INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W0[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W0[1]	INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W1[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W1[1]	INT: !bipass CELL.DOUBLE_IO_W0[1] = CELL.DOUBLE_IO_W2[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W2[1]	INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W2[1]	INT: !pass CELL.SINGLE_H[7] ← CELL.DEC_V[0]	-	INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_W0[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W0[3]	INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_W1[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W1[3]	INT: !bipass CELL.DOUBLE_IO_W0[3] = CELL.DOUBLE_IO_W2[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W2[3]	INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_W2[3]
B8	HIO[1]: ! READBACK_I bit 0	HIO[0]: !invert O	HIO[0]: ! READBACK_I bit 0	-	INT: mux CELL.IMUX_HIO_T[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 4	INT: mux CELL.IMUX_IO_O1[0] bit 5	INT: mux CELL.DBUF_IO_V[1] bit 2	INT: mux CELL.DBUF_IO_V[1] bit 1	INT: mux CELL.DBUF_IO_V[1] bit 0	INT: mux CELL.DBUF_IO_V[1] bit 3	INT: mux CELL.LONG_IO_V[1] bit 3	INT: mux CELL.LONG_IO_V[1] bit 1	INT: mux CELL.LONG_IO_V[1] bit 2	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1	INT: mux CELL.LONG_IO_V[3] bit 0	INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_IO_V[3]	-	INT: mux CELL.LONG_IO_V[3] bit 1	INT: mux CELL.LONG_IO_V[2] bit 3	INT: mux CELL.LONG_IO_V[2] bit 1	INT: mux CELL.LONG_IO_V[2] bit 0	INT: mux CELL.LONG_IO_V[2] bit 2	INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_IO_WE_I1[0]	INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_IO_WE_I1_S1
B7	INT: mux CELL.IMUX_HIO_O[0] bit 0	HIO[0]: PULL bit 1	HIO[0]: PULL bit 0	HIO[0]: OMODE bit 0	HIO[1]: OMODE bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 6	INT: mux CELL.IMUX_IO_IK[0] bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 3	INT: mux CELL.IMUX_IO_IK[0] bit 2	INT: mux CELL.IMUX_IO_IK[0] bit 4	INT: mux CELL.IMUX_IO_IK[0] bit 1	INT: mux CELL.IMUX_IO_IK[0] bit 5	INT: mux CELL.IMUX_IO_IK[0] bit 7	INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[1]	PULLUP_TBUF[1]: ! ENABLE	INT: mux CELL.LONG_H[5] bit 3	INT: !pass CELL.DOUBLE_IO_W2[1] ← CELL.DBUF_IO_V[0]	INT: !pass CELL.DOUBLE_IO_W2[3] ← CELL.DBUF_IO_V[0]	-	INT: mux CELL.LONG_H[5] bit 1	INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1[0]	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0]	INT: mux CELL.LONG_H[4] bit 1	INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1_S1	INT: mux CELL.LONG_H[4] bit 0	-
B6	HIO[1]: !invert T	INT: mux CELL.IMUX_HIO_T[1] bit 0	HIO[1]: !invert O	INT: mux CELL.IMUX_HIO_O[1] bit 0	HIO[1]: PULL bit 1	DEC[1]: ! O4_P	DEC[1]: ! O2_P	INT: mux CELL.IMUX_IO_OK[0] bit 5	HIO[1]: PULL bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 3	INT: mux CELL.IMUX_IO_OK[0] bit 2	DEC[1]: O1_N	INT: mux CELL.IMUX_IO_OK[0] bit 4	INT: mux CELL.IMUX_IO_OK[0] bit 1	INT: !pass CELL.DOUBLE_IO_W0[1] ← CELL.DBUF_IO_V[1]	INT: mux CELL.IMUX_IO_OK[0] bit 7	INT: !pass CELL.DOUBLE_IO_W2[2] ← CELL.DBUF_IO_V[0]	-	INT: !pass CELL.DOUBLE_IO_W2[0] ← CELL.DBUF_IO_V[0]	INT: mux CELL.LONG_H[5] bit 0	INT: mux CELL.LONG_H[5] bit 2	INT: !pass CELL.DOUBLE_IO_W0[3] ← CELL.DBUF_IO_V[1]	INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2[0]	INT: mux CELL.LONG_H[4] bit 3	INT: mux CELL.LONG_H[4] bit 2
B5	INT: mux CELL.OUT_IO_WE_I1[0] bit 0	HIO[1]: ! I_INV	HIO[1]: ISTD bit 0	HIO[1]: OSTD bit 0	DEC[2]: O4_P	DEC[1]: O4_N	DEC[1]: O2_N	DEC[2]: ! O2_N	INT: mux CELL.IMUX_IO_OK[0] bit 6	DEC[2]: ! O3_N	INT: !pass CELL.SINGLE_H[4] ← CELL.DEC_V[1]	DEC[2]: O1_P	DEC[1]: ! O1_P	INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_W0[2]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W0[2]	INT: !pass CELL.DOUBLE_IO_W0[0] ← CELL.DBUF_IO_V[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W0[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W0[0]	INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[3]	INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W1[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W1[0]	INT: mux CELL.LONG_IO_V[0] bit 1	INT: !bipass CELL.DOUBLE_IO_W0[0] = CELL.DOUBLE_IO_W2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W2[0]	INT: mux CELL.LONG_IO_V[0] bit 0	INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W2[0]
B4	HIO[2]: ! I_INV	INT: mux CELL.OUT_IO_WE_I1[1] bit 0	HIO[2]: ISTD bit 0	HIO[2]: OSTD bit 0	DEC[2]: ! O4_N	DEC[0]: ! O4_P	DEC[0]: O2_N	DEC[2]: O2_P	DEC[1]: O3_N	DEC[2]: O3_P	DEC[0]: ! O3_P	DEC[2]: ! O1_N	DEC[0]: ! O1_P	INT: !pass CELL.DOUBLE_IO_W0[2] ← CELL.DBUF_IO_V[1]	INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_W1[2]	INT: !bipass CELL.DOUBLE_IO_W0[2] = CELL.DOUBLE_IO_W2[2]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W2[2]	INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_W2[2]	INT: mux CELL.IMUX_IO_T[0] bit 5	INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_IO_V[2]	INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[0]	INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_WE_I2_S1
B3	HIO[2]: !invert T	INT: mux CELL.IMUX_HIO_T[2] bit 0	HIO[2]: !invert O	HIO[3]: ! READBACK_I bit 0	HIO[2]: ! READBACK_I bit 0	DEC[0]: O4_N	DEC[0]: ! O2_P	INT: mux CELL.IMUX_IO_IK[1] bit 5	DEC[1]: ! O3_P	HIO[2]: PULL bit 1	DEC[0]: O3_N	INT: mux CELL.IMUX_IO_IK[1] bit 7	DEC[0]: O1_N	TBUF[1]: ! DRIVE1	INT: mux CELL.IMUX_IO_T[1] bit 2	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W1[2]	INT: mux CELL.IMUX_IO_T[1] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 4	-	INT: mux CELL.IMUX_IO_T[0] bit 2	INT: mux CELL.IMUX_IO_T[0] bit 0	INT: mux CELL.DBUF_IO_V[0] bit 1	INT: mux CELL.DBUF_IO_V[0] bit 0	INT: mux CELL.IMUX_IO_T[0] bit 4	INT: mux CELL.IMUX_IO_T[0] bit 7	TBUF[0]: ! DRIVE1
B2	HIO[3]: OMODE bit 0	HIO[2]: OMODE bit 0	-	HIO[2]: PULL bit 0	INT: mux CELL.IMUX_HIO_O[2] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 3	INT: mux CELL.IMUX_IO_OK[1] bit 6	INT: mux CELL.IMUX_IO_OK[1] bit 5	INT: mux CELL.IMUX_IO_OK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 0	INT: mux CELL.IMUX_IO_IK[1] bit 4	INT: mux CELL.IMUX_IO_OK[1] bit 4	INT: mux CELL.IMUX_IO_OK[1] bit 2	INT: mux CELL.IMUX_IO_OK[1] bit 7	INT: mux CELL.IMUX_IO_T[1] bit 0	INT: mux CELL.IMUX_IO_T[1] bit 1	-	INT: mux CELL.IMUX_IO_T[1] bit 5	INT: mux CELL.IMUX_IO_T[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 6	INT: mux CELL.DBUF_IO_V[0] bit 2	INT: mux CELL.IMUX_IO_T[1] bit 7	INT: mux CELL.DBUF_IO_V[0] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 6
B1	HIO[3]: PULL bit 1	HIO[3]: PULL bit 0	INT: mux CELL.IMUX_HIO_O[3] bit 0	HIO[3]: !invert O	INT: mux CELL.IMUX_HIO_T[3] bit 0	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 3	INT: mux CELL.IMUX_IO_IK[1] bit 6	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 5	INT: mux CELL.LONG_H[1] bit 3	INT: mux CELL.LONG_H[1] bit 2	INT: mux CELL.IMUX_TBUF_I[1] bit 3	INT: mux CELL.IMUX_TBUF_I[1] bit 0	INT: mux CELL.IMUX_TBUF_I[1] bit 5	INT: mux CELL.IMUX_TBUF_T[1] bit 3	INT: mux CELL.IMUX_TBUF_T[1] bit 0	INT: mux CELL.IMUX_TBUF_T[1] bit 4	INT: mux CELL.IMUX_TBUF_T[1] bit 5	INT: mux CELL.IMUX_TBUF_T[0] bit 1	INT: mux CELL.IMUX_TBUF_T[0] bit 5	INT: mux CELL.IMUX_TBUF_I[0] bit 3	INT: mux CELL.IMUX_TBUF_I[0] bit 0	INT: mux CELL.IMUX_TBUF_I[0] bit 5	INT: mux CELL.LONG_H[0] bit 3	INT: mux CELL.LONG_H[0] bit 2
B0	HIO[3]: OSTD bit 0	HIO[3]: ISTD bit 0	HIO[3]: ! I_INV	INT: mux CELL.OUT_IO_WE_I2[1] bit 0	HIO[3]: !invert T	INT: mux CELL.IMUX_IO_O1[1] bit 4	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 0	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.LONG_H[1] bit 1	INT: mux CELL.LONG_H[1] bit 0	INT: mux CELL.IMUX_TBUF_I[1] bit 4	INT: mux CELL.IMUX_TBUF_I[1] bit 1	INT: mux CELL.IMUX_TBUF_I[1] bit 2	INT: mux CELL.IMUX_TBUF_T[1] bit 2	INT: mux CELL.IMUX_TBUF_T[1] bit 1	INT: mux CELL.IMUX_TBUF_T[0] bit 2	INT: mux CELL.IMUX_TBUF_T[0] bit 0	INT: mux CELL.IMUX_TBUF_T[0] bit 4	INT: mux CELL.IMUX_TBUF_T[0] bit 3	INT: mux CELL.IMUX_TBUF_I[0] bit 2	INT: mux CELL.IMUX_TBUF_I[0] bit 1	INT: mux CELL.IMUX_TBUF_I[0] bit 4	INT: mux CELL.LONG_H[0] bit 0	INT: mux CELL.LONG_H[0] bit 1

xc4000h IO_W1 rect MAIN_S
Bit	Frame
Bit	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PULLUP_TBUF[0]: ! ENABLE
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile IO_W1_S

Cells: 4

Switchbox INT

xc4000h IO_W1_S switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[0]	CELL.DEC_V[3]	!MAIN[7][5]
CELL.SINGLE_H[0]	CELL.OUT_IO_WE_I2_S1	!MAIN[1][4]
CELL.SINGLE_H[1]	CELL.LONG_IO_V[0]	!MAIN[3][4]
CELL.SINGLE_H[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[4][4]
CELL.SINGLE_H[2]	CELL.LONG_IO_V[1]	!MAIN[12][7]
CELL.SINGLE_H[2]	CELL.OUT_IO_WE_I1[0]	!MAIN[4][7]
CELL.SINGLE_H[3]	CELL.DEC_V[2]	!MAIN[16][9]
CELL.SINGLE_H[3]	CELL.OUT_IO_WE_I1_S1	!MAIN[10][8]
CELL.SINGLE_H[4]	CELL.DEC_V[1]	!MAIN[15][5]
CELL.SINGLE_H[4]	CELL.OUT_IO_WE_I2_S1	!MAIN[0][4]
CELL.SINGLE_H[5]	CELL.LONG_IO_V[2]	!MAIN[6][4]
CELL.SINGLE_H[5]	CELL.OUT_IO_WE_I2[0]	!MAIN[5][4]
CELL.SINGLE_H[6]	CELL.LONG_IO_V[3]	!MAIN[8][8]
CELL.SINGLE_H[6]	CELL.OUT_IO_WE_I1[0]	!MAIN[1][8]
CELL.SINGLE_H[7]	CELL.DEC_V[0]	!MAIN[8][9]
CELL.SINGLE_H[7]	CELL.OUT_IO_WE_I1_S1	!MAIN[0][8]
CELL.DOUBLE_H0[0]	CELL.OUT_IO_WE_I1_S1	!MAIN[2][7]
CELL.DOUBLE_H0[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[2][6]
CELL.DOUBLE_H1[0]	CELL.OUT_IO_WE_I1[0]	!MAIN[5][7]
CELL.DOUBLE_H1[1]	CELL.OUT_IO_WE_I2_S1	!MAIN[2][4]
CELL.DOUBLE_IO_W0[0]	CELL.DBUF_IO_V[1]	!MAIN[10][5]
CELL.DOUBLE_IO_W0[1]	CELL.DBUF_IO_V[1]	!MAIN[10][6]
CELL.DOUBLE_IO_W0[2]	CELL.DBUF_IO_V[1]	!MAIN[12][4]
CELL.DOUBLE_IO_W0[3]	CELL.DBUF_IO_V[1]	!MAIN[3][6]
CELL.DOUBLE_IO_W2[0]	CELL.DBUF_IO_V[0]	!MAIN[6][6]
CELL.DOUBLE_IO_W2[1]	CELL.DBUF_IO_V[0]	!MAIN[9][7]
CELL.DOUBLE_IO_W2[2]	CELL.DBUF_IO_V[0]	!MAIN[8][6]
CELL.DOUBLE_IO_W2[3]	CELL.DBUF_IO_V[0]	!MAIN[8][7]

xc4000h IO_W1_S switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.DOUBLE_IO_W1[0]	!MAIN[6][5]
CELL.SINGLE_H[1]	CELL.DOUBLE_IO_W0[0]	!MAIN[9][5]
CELL.SINGLE_H[1]	CELL.DOUBLE_IO_W2[0]	!MAIN[0][5]
CELL.SINGLE_H[2]	CELL.DOUBLE_IO_W1[1]	!MAIN[13][9]
CELL.SINGLE_H[3]	CELL.DOUBLE_IO_W0[1]	!MAIN[15][9]
CELL.SINGLE_H[3]	CELL.DOUBLE_IO_W2[1]	!MAIN[9][9]
CELL.SINGLE_H[4]	CELL.DOUBLE_IO_W1[2]	!MAIN[11][4]
CELL.SINGLE_H[5]	CELL.DOUBLE_IO_W0[2]	!MAIN[12][5]
CELL.SINGLE_H[5]	CELL.DOUBLE_IO_W2[2]	!MAIN[8][4]
CELL.SINGLE_H[6]	CELL.DOUBLE_IO_W1[3]	!MAIN[4][9]
CELL.SINGLE_H[7]	CELL.DOUBLE_IO_W0[3]	!MAIN[6][9]
CELL.SINGLE_H[7]	CELL.DOUBLE_IO_W2[3]	!MAIN[0][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_W0[0]	!MAIN[8][5]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_W1[0]	!MAIN[5][5]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_W2[0]	!MAIN[2][5]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_W0[3]	!MAIN[5][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_W1[3]	!MAIN[3][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_W2[3]	!MAIN[1][9]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_W0[1]	!MAIN[14][9]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_W1[1]	!MAIN[12][9]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_W2[1]	!MAIN[10][9]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_W0[2]	!MAIN[11][5]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_W1[2]	!MAIN[10][3]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_W2[2]	!MAIN[9][4]
CELL.DOUBLE_IO_W0[0]	CELL.DOUBLE_IO_W2[0]	!MAIN[3][5]
CELL.DOUBLE_IO_W0[1]	CELL.DOUBLE_IO_W2[1]	!MAIN[11][9]
CELL.DOUBLE_IO_W0[2]	CELL.DOUBLE_IO_W2[2]	!MAIN[10][4]
CELL.DOUBLE_IO_W0[3]	CELL.DOUBLE_IO_W2[3]	!MAIN[2][9]

xc4000h IO_W1_S switchbox INT muxes DBUF_IO_V[0]
Bits				Destination
MAIN[1][2]	MAIN[3][2]	MAIN[4][3]	MAIN[3][3]	CELL.DBUF_IO_V[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_W0[1]
0	1	0	1	CELL.DOUBLE_IO_W0[2]
0	1	1	0	CELL.DOUBLE_IO_W0[3]
1	1	1	1	CELL.DOUBLE_IO_W0[0]

xc4000h IO_W1_S switchbox INT muxes DBUF_IO_V[1]
Bits				Destination
MAIN[14][8]	MAIN[17][8]	MAIN[16][8]	MAIN[15][8]	CELL.DBUF_IO_V[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_W2[0]
0	1	0	1	CELL.DOUBLE_IO_W2[1]
0	1	1	0	CELL.DOUBLE_IO_W2[3]
1	1	1	1	CELL.DOUBLE_IO_W2[2]

xc4000h IO_W1_S switchbox INT muxes LONG_H[0]
Bits				Destination
MAIN[1][1]	MAIN[0][1]	MAIN[0][0]	MAIN[1][0]	CELL.LONG_H[0]
				Source
0	0	0	1	CELL.LONG_IO_V[0]
0	0	1	0	CELL.DEC_V[0]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000h IO_W1_S switchbox INT muxes LONG_H[1]
Bits				Destination
MAIN[15][1]	MAIN[14][1]	MAIN[15][0]	MAIN[14][0]	CELL.LONG_H[1]
				Source
0	0	0	1	CELL.LONG_IO_V[1]
0	0	1	0	CELL.DEC_V[1]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000h IO_W1_S switchbox INT muxes LONG_H[4]
Bits				Destination
MAIN[1][6]	MAIN[0][6]	MAIN[3][7]	MAIN[1][7]	CELL.LONG_H[4]
				Source
0	0	0	1	CELL.LONG_IO_V[2]
0	0	1	0	CELL.DEC_V[2]
0	1	1	1	CELL.OUT_IO_WE_I2[0]
1	1	1	1	off

xc4000h IO_W1_S switchbox INT muxes LONG_H[5]
Bits				Destination
MAIN[10][7]	MAIN[4][6]	MAIN[6][7]	MAIN[5][6]	CELL.LONG_H[5]
				Source
0	0	0	1	CELL.LONG_IO_V[3]
0	0	1	0	CELL.DEC_V[3]
0	1	1	1	CELL.OUT_IO_WE_I2[0]
1	1	1	1	off

xc4000h IO_W1_S switchbox INT muxes LONG_IO_V[0]
Bits		Destination
MAIN[4][5]	MAIN[1][5]	CELL.LONG_IO_V[0]
		Source
0	0	CELL.LONG_H[0]
0	1	CELL.SINGLE_H[1]
1	1	off

xc4000h IO_W1_S switchbox INT muxes LONG_IO_V[1]
Bits				Destination
MAIN[13][8]	MAIN[11][8]	MAIN[12][8]	MAIN[17][9]	CELL.LONG_IO_V[1]
				Source
0	0	0	1	CELL.LONG_H[1]
0	0	1	0	CELL.LONG_H[3]
0	1	1	1	CELL.SINGLE_H[2]
1	1	1	1	off

xc4000h IO_W1_S switchbox INT muxes LONG_IO_V[2]
Bits				Destination
MAIN[5][8]	MAIN[2][8]	MAIN[4][8]	MAIN[3][8]	CELL.LONG_IO_V[2]
				Source
0	0	0	1	CELL.LONG_H[2]
0	0	1	0	CELL.LONG_H[4]
0	1	1	1	CELL.SINGLE_H[5]
1	1	1	1	off

xc4000h IO_W1_S switchbox INT muxes LONG_IO_V[3]
Bits		Destination
MAIN[6][8]	MAIN[9][8]	CELL.LONG_IO_V[3]
		Source
0	0	CELL.LONG_H[5]
0	1	CELL.SINGLE_H[6]
1	1	off

xc4000h IO_W1_S switchbox INT muxes IMUX_TBUF_I[0]
Bits						Destination
MAIN[2][1]	MAIN[2][0]	MAIN[4][1]	MAIN[4][0]	MAIN[3][0]	MAIN[3][1]	CELL.IMUX_TBUF_I[0]
						Source
0	0	0	1	1	1	CELL.OUT_IO_WE_I2[0]
0	0	1	0	1	1	CELL.DOUBLE_IO_W1[2]
0	0	1	1	0	1	CELL.LONG_IO_V[2]
0	0	1	1	1	0	CELL.DEC_V[2]
0	1	1	1	1	1	CELL.DOUBLE_IO_W0[2]
1	0	0	1	1	1	CELL.DOUBLE_IO_W0[3]
1	0	1	0	1	1	CELL.DOUBLE_IO_W1[3]
1	0	1	1	0	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_W1_S switchbox INT muxes IMUX_TBUF_I[1]
Bits						Destination
MAIN[11][1]	MAIN[13][0]	MAIN[13][1]	MAIN[11][0]	MAIN[12][0]	MAIN[12][1]	CELL.IMUX_TBUF_I[1]
						Source
0	0	0	1	1	1	CELL.DOUBLE_IO_W0[2]
0	0	1	0	1	1	CELL.OUT_IO_WE_I2[0]
0	0	1	1	0	1	CELL.LONG_IO_V[1]
0	0	1	1	1	0	CELL.DEC_V[1]
0	1	0	1	1	1	CELL.DOUBLE_IO_W1[3]
0	1	1	0	1	1	CELL.DOUBLE_IO_W0[3]
0	1	1	1	1	0	CELL.OUT_IO_WE_I2[1]
1	0	1	1	1	1	CELL.DOUBLE_IO_W1[2]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_W1_S switchbox INT muxes IMUX_TBUF_T[0]
Bits						Destination
MAIN[5][1]	MAIN[6][0]	MAIN[5][0]	MAIN[8][0]	MAIN[6][1]	MAIN[7][0]	CELL.IMUX_TBUF_T[0]
						Source
0	0	0	1	1	1	CELL.TIE_1
0	0	1	1	1	1	CELL.TIE_0
0	1	0	0	1	1	CELL.DOUBLE_IO_W0[1]
0	1	0	1	0	1	CELL.LONG_IO_V[3]
0	1	0	1	1	0	CELL.DEC_V[0]
0	1	1	0	1	1	CELL.DOUBLE_IO_W1[1]
0	1	1	1	0	1	CELL.LONG_IO_V[2]
0	1	1	1	1	0	CELL.DEC_V[3]
1	1	0	1	1	1	CELL.DOUBLE_IO_W0[0]
1	1	1	1	1	1	CELL.DOUBLE_IO_W1[0]

xc4000h IO_W1_S switchbox INT muxes IMUX_TBUF_T[1]
Bits						Destination
MAIN[7][1]	MAIN[8][1]	MAIN[10][1]	MAIN[10][0]	MAIN[9][0]	MAIN[9][1]	CELL.IMUX_TBUF_T[1]
						Source
0	0	0	1	1	1	CELL.TIE_1
0	0	1	1	1	1	CELL.TIE_0
0	1	0	0	1	1	CELL.DOUBLE_IO_W1[0]
0	1	0	1	0	1	CELL.LONG_IO_V[2]
0	1	0	1	1	0	CELL.DEC_V[3]
0	1	1	0	1	1	CELL.DOUBLE_IO_W0[0]
0	1	1	1	0	1	CELL.LONG_IO_V[3]
0	1	1	1	1	0	CELL.DEC_V[0]
1	1	0	1	1	1	CELL.DOUBLE_IO_W1[1]
1	1	1	1	1	1	CELL.DOUBLE_IO_W0[1]

xc4000h IO_W1_S switchbox INT muxes IMUX_IO_O1[0]
Bits						Destination
MAIN[18][8]	MAIN[19][8]	MAIN[20][9]	MAIN[18][9]	MAIN[19][9]	MAIN[20][8]	CELL.IMUX_IO_O1[0]
						Source
0	0	0	1	1	1	CELL.DEC_V[0]
0	0	1	1	1	1	CELL.DOUBLE_H0[0]
0	1	0	0	1	1	CELL.DEC_V[1]
0	1	0	1	0	1	CELL.DEC_V[2]
0	1	0	1	1	0	CELL.DEC_V[3]
0	1	1	0	1	1	CELL.LONG_H[3]
0	1	1	1	0	1	CELL.LONG_H[4]
0	1	1	1	1	0	CELL.LONG_H[5]
1	1	0	1	1	1	CELL.DOUBLE_H1[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_W1_S switchbox INT muxes IMUX_IO_O1[1]
Bits						Destination
MAIN[16][1]	MAIN[20][0]	MAIN[19][0]	MAIN[18][0]	MAIN[16][0]	MAIN[17][0]	CELL.IMUX_IO_O1[1]
						Source
0	0	0	1	1	1	CELL.LONG_H[0]
0	0	1	0	1	1	CELL.LONG_H[1]
0	0	1	1	0	1	CELL.DEC_V[0]
0	0	1	1	1	0	CELL.DEC_V[1]
0	1	0	1	1	1	CELL_S.DOUBLE_H0[1]
0	1	1	0	1	1	CELL.LONG_H[2]
0	1	1	1	0	1	CELL.DEC_V[2]
0	1	1	1	1	0	CELL.DEC_V[3]
1	0	1	1	1	1	CELL_S.DOUBLE_H1[0]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_W1_S switchbox INT muxes IMUX_IO_OK[0]
Bits								Destination
MAIN[9][6]	MAIN[17][5]	MAIN[18][6]	MAIN[12][6]	MAIN[15][6]	MAIN[14][6]	MAIN[11][6]	MAIN[16][6]	CELL.IMUX_IO_OK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_H[3]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[2]

xc4000h IO_W1_S switchbox INT muxes IMUX_IO_OK[1]
Bits								Destination
MAIN[11][2]	MAIN[18][2]	MAIN[17][2]	MAIN[13][2]	MAIN[19][2]	MAIN[12][2]	MAIN[16][2]	MAIN[20][2]	CELL.IMUX_IO_OK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_S.SINGLE_H[2]
0	1	1	1	1	1	0	1	CELL_S.SINGLE_H[4]
0	1	1	1	1	1	1	0	CELL_S.SINGLE_H[5]
1	1	1	1	1	1	1	1	CELL_S.SINGLE_H[3]

xc4000h IO_W1_S switchbox INT muxes IMUX_IO_IK[0]
Bits								Destination
MAIN[13][7]	MAIN[20][7]	MAIN[14][7]	MAIN[16][7]	MAIN[18][7]	MAIN[17][7]	MAIN[15][7]	MAIN[19][7]	CELL.IMUX_IO_IK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_H[2]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[3]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[4]

xc4000h IO_W1_S switchbox INT muxes IMUX_IO_IK[1]
Bits								Destination
MAIN[14][3]	MAIN[18][1]	MAIN[18][3]	MAIN[14][2]	MAIN[19][1]	MAIN[17][1]	MAIN[20][1]	MAIN[15][2]	CELL.IMUX_IO_IK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_S.SINGLE_H[2]
0	1	1	1	1	1	0	1	CELL_S.SINGLE_H[3]
0	1	1	1	1	1	1	0	CELL_S.SINGLE_H[4]
1	1	1	1	1	1	1	1	CELL_S.SINGLE_H[5]

xc4000h IO_W1_S switchbox INT muxes IMUX_IO_T[0]
Bits								Destination
MAIN[1][3]	MAIN[4][2]	MAIN[7][4]	MAIN[2][3]	MAIN[6][2]	MAIN[6][3]	MAIN[5][2]	MAIN[5][3]	CELL.IMUX_IO_T[0]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	0	1	1	1	CELL.LONG_IO_V[3]
0	0	1	0	1	0	1	1	CELL.LONG_IO_V[0]
0	0	1	1	0	1	0	1	CELL.LONG_IO_V[1]
0	0	1	1	0	1	1	0	CELL.GCLK[0]
0	0	1	1	1	0	0	1	CELL.DEC_V[1]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_W0[1]
0	1	1	1	1	1	0	1	CELL.LONG_IO_V[2]
0	1	1	1	1	1	1	0	CELL.DEC_V[0]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_W1[0]
1	0	1	1	1	0	1	1	CELL.DOUBLE_IO_W1[1]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_W0[0]

xc4000h IO_W1_S switchbox INT muxes IMUX_IO_T[1]
Bits								Destination
MAIN[2][2]	MAIN[0][2]	MAIN[7][2]	MAIN[8][3]	MAIN[9][3]	MAIN[11][3]	MAIN[9][2]	MAIN[10][2]	CELL.IMUX_IO_T[1]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	1	0	1	1	CELL.DEC_V[1]
0	0	1	0	1	1	0	1	CELL.LONG_IO_V[0]
0	0	1	1	0	0	1	1	CELL.DOUBLE_IO_W0[1]
0	0	1	1	0	1	0	1	CELL.LONG_IO_V[2]
0	0	1	1	0	1	1	0	CELL.DEC_V[0]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_W0[0]
0	1	1	1	0	1	1	1	CELL.DOUBLE_IO_W1[1]
1	0	1	1	1	0	1	1	CELL.LONG_IO_V[1]
1	0	1	1	1	1	0	1	CELL.LONG_IO_V[3]
1	0	1	1	1	1	1	0	CELL.GCLK[0]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_W1[0]

xc4000h IO_W1_S switchbox INT muxes IMUX_HIO_O[0]
Bits	Destination
MAIN[25][7]	CELL.IMUX_HIO_O[0]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_G3_W

xc4000h IO_W1_S switchbox INT muxes IMUX_HIO_O[1]
Bits	Destination
MAIN[22][6]	CELL.IMUX_HIO_O[1]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_G3_W

xc4000h IO_W1_S switchbox INT muxes IMUX_HIO_O[2]
Bits	Destination
MAIN[21][2]	CELL.IMUX_HIO_O[2]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_F3_W

xc4000h IO_W1_S switchbox INT muxes IMUX_HIO_O[3]
Bits	Destination
MAIN[23][1]	CELL.IMUX_HIO_O[3]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_F3_W

xc4000h IO_W1_S switchbox INT muxes IMUX_HIO_T[0]
Bits	Destination
MAIN[21][8]	CELL.IMUX_HIO_T[0]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_OK[0]

xc4000h IO_W1_S switchbox INT muxes IMUX_HIO_T[1]
Bits	Destination
MAIN[24][6]	CELL.IMUX_HIO_T[1]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_IK[0]

xc4000h IO_W1_S switchbox INT muxes IMUX_HIO_T[2]
Bits	Destination
MAIN[24][3]	CELL.IMUX_HIO_T[2]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_IK[1]

xc4000h IO_W1_S switchbox INT muxes IMUX_HIO_T[3]
Bits	Destination
MAIN[21][1]	CELL.IMUX_HIO_T[3]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_OK[1]

xc4000h IO_W1_S switchbox INT muxes OUT_IO_WE_I1[0]
Bits	Destination
MAIN[25][5]	CELL.OUT_IO_WE_I1[0]
	Source
0	CELL.OUT_HIO_I[1]
1	CELL.OUT_HIO_I[0]

xc4000h IO_W1_S switchbox INT muxes OUT_IO_WE_I1[1]
Bits	Destination
MAIN[24][4]	CELL.OUT_IO_WE_I1[1]
	Source
0	CELL.OUT_HIO_I[2]
1	CELL.OUT_HIO_I[3]

xc4000h IO_W1_S switchbox INT muxes OUT_IO_WE_I2[0]
Bits	Destination
MAIN[22][9]	CELL.OUT_IO_WE_I2[0]
	Source
0	CELL.OUT_HIO_I[0]
1	CELL.OUT_HIO_I[1]

xc4000h IO_W1_S switchbox INT muxes OUT_IO_WE_I2[1]
Bits	Destination
MAIN[22][0]	CELL.OUT_IO_WE_I2[1]
	Source
0	CELL.OUT_HIO_I[3]
1	CELL.OUT_HIO_I[2]

Bels TBUF

xc4000h IO_W1_S bel TBUF pins
Pin	Direction	TBUF[0]	TBUF[1]
I	in	CELL.IMUX_TBUF_I[0]	CELL.IMUX_TBUF_I[1]
T	in	CELL.IMUX_TBUF_T[0]	CELL.IMUX_TBUF_T[1]
O	bidir	CELL.LONG_H[2]	CELL.LONG_H[3]

xc4000h IO_W1_S bel TBUF attribute bits
Attribute	TBUF[0]	TBUF[1]
DRIVE1	!MAIN[0][3]	!MAIN[12][3]

Bels HIO

xc4000h IO_W1_S bel HIO pins
Pin	Direction	HIO[0]	HIO[1]	HIO[2]	HIO[3]
O	in	CELL.IMUX_HIO_O[0] invert by !MAIN[24][8]	CELL.IMUX_HIO_O[1] invert by !MAIN[23][6]	CELL.IMUX_HIO_O[2] invert by !MAIN[23][3]	CELL.IMUX_HIO_O[3] invert by !MAIN[22][1]
T	in	CELL.IMUX_HIO_T[0] invert by !MAIN[21][9]	CELL.IMUX_HIO_T[1] invert by !MAIN[25][6]	CELL.IMUX_HIO_T[2] invert by !MAIN[25][3]	CELL.IMUX_HIO_T[3] invert by !MAIN[21][0]
I	out	CELL.OUT_HIO_I[0]	CELL.OUT_HIO_I[1]	CELL.OUT_HIO_I[2]	CELL.OUT_HIO_I[3]
CLKIN	out	-	-	-	CELL.OUT_IO_CLKIN

xc4000h IO_W1_S bel HIO attribute bits
Attribute	HIO[0]	HIO[1]	HIO[2]	HIO[3]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
ISTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OSTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OMODE	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]
I_INV	!MAIN[23][9]	!MAIN[24][5]	!MAIN[25][4]	!MAIN[23][0]
READBACK_I bit 0	!MAIN[23][8]	!MAIN[25][8]	!MAIN[21][3]	!MAIN[22][3]

xc4000h IO_W1_S enum IO_PULL
HIO[0].PULL	MAIN[24][7]	MAIN[23][7]
HIO[1].PULL	MAIN[21][6]	MAIN[17][6]
HIO[2].PULL	MAIN[16][3]	MAIN[22][2]
HIO[3].PULL	MAIN[25][1]	MAIN[24][1]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

xc4000h IO_W1_S enum IO_STD
HIO[0].ISTD	MAIN[24][9]
HIO[1].ISTD	MAIN[23][5]
HIO[2].ISTD	MAIN[23][4]
HIO[3].ISTD	MAIN[24][0]
CMOS	0
TTL	1

xc4000h IO_W1_S enum IO_STD
HIO[0].OSTD	MAIN[25][9]
HIO[1].OSTD	MAIN[22][5]
HIO[2].OSTD	MAIN[22][4]
HIO[3].OSTD	MAIN[25][0]
CMOS	1
TTL	0

xc4000h IO_W1_S enum HIO_OMODE
HIO[0].OMODE	MAIN[22][7]
HIO[1].OMODE	MAIN[21][7]
HIO[2].OMODE	MAIN[24][2]
HIO[3].OMODE	MAIN[25][2]
CAP	1
RES	0

Bels DEC

xc4000h IO_W1_S bel DEC pins
Pin	Direction	DEC[0]	DEC[1]	DEC[2]
I	in	CELL.OUT_IO_WE_I1[0]	CELL.IMUX_CLB_C3_W	CELL.OUT_IO_WE_I1[1]
O1	bidir	CELL.DEC_V[0]	CELL.DEC_V[0]	CELL.DEC_V[0]
O2	bidir	CELL.DEC_V[1]	CELL.DEC_V[1]	CELL.DEC_V[1]
O3	bidir	CELL.DEC_V[2]	CELL.DEC_V[2]	CELL.DEC_V[2]
O4	bidir	CELL.DEC_V[3]	CELL.DEC_V[3]	CELL.DEC_V[3]

xc4000h IO_W1_S bel DEC attribute bits
Attribute	DEC[0]	DEC[1]	DEC[2]
O1_P	!MAIN[13][4]	!MAIN[13][5]	MAIN[14][5]
O1_N	MAIN[13][3]	MAIN[13][6]	!MAIN[14][4]
O2_P	!MAIN[19][3]	!MAIN[19][6]	MAIN[18][4]
O2_N	MAIN[19][4]	MAIN[19][5]	!MAIN[18][5]
O3_P	!MAIN[15][4]	!MAIN[17][3]	MAIN[16][4]
O3_N	MAIN[15][3]	MAIN[17][4]	!MAIN[16][5]
O4_P	!MAIN[20][4]	!MAIN[20][6]	MAIN[21][5]
O4_N	MAIN[20][3]	MAIN[20][5]	!MAIN[21][4]

Bels PULLUP

xc4000h IO_W1_S bel PULLUP pins
Pin	Direction	PULLUP_TBUF[0]	PULLUP_TBUF[1]
O	bidir	CELL.LONG_H[2]	CELL.LONG_H[3]

xc4000h IO_W1_S bel PULLUP attribute bits
Attribute	PULLUP_TBUF[0]	PULLUP_TBUF[1]
ENABLE	!MAIN_S[0][10]	!MAIN[11][7]

Bel wires

xc4000h IO_W1_S bel wires
Wire	Pins
CELL.LONG_H[2]	TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]	TBUF[1].O, PULLUP_TBUF[1].O
CELL.DEC_V[0]	DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_V[1]	DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.DEC_V[2]	DEC[0].O3, DEC[1].O3, DEC[2].O3
CELL.DEC_V[3]	DEC[0].O4, DEC[1].O4, DEC[2].O4
CELL.IMUX_CLB_C3_W	DEC[1].I
CELL.IMUX_TBUF_I[0]	TBUF[0].I
CELL.IMUX_TBUF_I[1]	TBUF[1].I
CELL.IMUX_TBUF_T[0]	TBUF[0].T
CELL.IMUX_TBUF_T[1]	TBUF[1].T
CELL.IMUX_HIO_O[0]	HIO[0].O
CELL.IMUX_HIO_O[1]	HIO[1].O
CELL.IMUX_HIO_O[2]	HIO[2].O
CELL.IMUX_HIO_O[3]	HIO[3].O
CELL.IMUX_HIO_T[0]	HIO[0].T
CELL.IMUX_HIO_T[1]	HIO[1].T
CELL.IMUX_HIO_T[2]	HIO[2].T
CELL.IMUX_HIO_T[3]	HIO[3].T
CELL.OUT_IO_WE_I1[0]	DEC[0].I
CELL.OUT_IO_WE_I1[1]	DEC[2].I
CELL.OUT_HIO_I[0]	HIO[0].I
CELL.OUT_HIO_I[1]	HIO[1].I
CELL.OUT_HIO_I[2]	HIO[2].I
CELL.OUT_HIO_I[3]	HIO[3].I
CELL.OUT_IO_CLKIN	HIO[3].CLKIN

Bitstream

xc4000h IO_W1_S rect MAIN
Bit	Frame
Bit	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	HIO[0]: OSTD bit 0	HIO[0]: ISTD bit 0	HIO[0]: ! I_INV	INT: mux CELL.OUT_IO_WE_I2[0] bit 0	HIO[0]: !invert T	INT: mux CELL.IMUX_IO_O1[0] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 1	INT: mux CELL.IMUX_IO_O1[0] bit 2	INT: mux CELL.LONG_IO_V[1] bit 0	INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[2]	INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W0[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W0[1]	INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W1[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W1[1]	INT: !bipass CELL.DOUBLE_IO_W0[1] = CELL.DOUBLE_IO_W2[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W2[1]	INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W2[1]	INT: !pass CELL.SINGLE_H[7] ← CELL.DEC_V[0]	-	INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_W0[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W0[3]	INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_W1[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W1[3]	INT: !bipass CELL.DOUBLE_IO_W0[3] = CELL.DOUBLE_IO_W2[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W2[3]	INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_W2[3]
B8	HIO[1]: ! READBACK_I bit 0	HIO[0]: !invert O	HIO[0]: ! READBACK_I bit 0	-	INT: mux CELL.IMUX_HIO_T[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 4	INT: mux CELL.IMUX_IO_O1[0] bit 5	INT: mux CELL.DBUF_IO_V[1] bit 2	INT: mux CELL.DBUF_IO_V[1] bit 1	INT: mux CELL.DBUF_IO_V[1] bit 0	INT: mux CELL.DBUF_IO_V[1] bit 3	INT: mux CELL.LONG_IO_V[1] bit 3	INT: mux CELL.LONG_IO_V[1] bit 1	INT: mux CELL.LONG_IO_V[1] bit 2	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1	INT: mux CELL.LONG_IO_V[3] bit 0	INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_IO_V[3]	-	INT: mux CELL.LONG_IO_V[3] bit 1	INT: mux CELL.LONG_IO_V[2] bit 3	INT: mux CELL.LONG_IO_V[2] bit 1	INT: mux CELL.LONG_IO_V[2] bit 0	INT: mux CELL.LONG_IO_V[2] bit 2	INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_IO_WE_I1[0]	INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_IO_WE_I1_S1
B7	INT: mux CELL.IMUX_HIO_O[0] bit 0	HIO[0]: PULL bit 1	HIO[0]: PULL bit 0	HIO[0]: OMODE bit 0	HIO[1]: OMODE bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 6	INT: mux CELL.IMUX_IO_IK[0] bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 3	INT: mux CELL.IMUX_IO_IK[0] bit 2	INT: mux CELL.IMUX_IO_IK[0] bit 4	INT: mux CELL.IMUX_IO_IK[0] bit 1	INT: mux CELL.IMUX_IO_IK[0] bit 5	INT: mux CELL.IMUX_IO_IK[0] bit 7	INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[1]	PULLUP_TBUF[1]: ! ENABLE	INT: mux CELL.LONG_H[5] bit 3	INT: !pass CELL.DOUBLE_IO_W2[1] ← CELL.DBUF_IO_V[0]	INT: !pass CELL.DOUBLE_IO_W2[3] ← CELL.DBUF_IO_V[0]	-	INT: mux CELL.LONG_H[5] bit 1	INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1[0]	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0]	INT: mux CELL.LONG_H[4] bit 1	INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1_S1	INT: mux CELL.LONG_H[4] bit 0	-
B6	HIO[1]: !invert T	INT: mux CELL.IMUX_HIO_T[1] bit 0	HIO[1]: !invert O	INT: mux CELL.IMUX_HIO_O[1] bit 0	HIO[1]: PULL bit 1	DEC[1]: ! O4_P	DEC[1]: ! O2_P	INT: mux CELL.IMUX_IO_OK[0] bit 5	HIO[1]: PULL bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 3	INT: mux CELL.IMUX_IO_OK[0] bit 2	DEC[1]: O1_N	INT: mux CELL.IMUX_IO_OK[0] bit 4	INT: mux CELL.IMUX_IO_OK[0] bit 1	INT: !pass CELL.DOUBLE_IO_W0[1] ← CELL.DBUF_IO_V[1]	INT: mux CELL.IMUX_IO_OK[0] bit 7	INT: !pass CELL.DOUBLE_IO_W2[2] ← CELL.DBUF_IO_V[0]	-	INT: !pass CELL.DOUBLE_IO_W2[0] ← CELL.DBUF_IO_V[0]	INT: mux CELL.LONG_H[5] bit 0	INT: mux CELL.LONG_H[5] bit 2	INT: !pass CELL.DOUBLE_IO_W0[3] ← CELL.DBUF_IO_V[1]	INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2[0]	INT: mux CELL.LONG_H[4] bit 3	INT: mux CELL.LONG_H[4] bit 2
B5	INT: mux CELL.OUT_IO_WE_I1[0] bit 0	HIO[1]: ! I_INV	HIO[1]: ISTD bit 0	HIO[1]: OSTD bit 0	DEC[2]: O4_P	DEC[1]: O4_N	DEC[1]: O2_N	DEC[2]: ! O2_N	INT: mux CELL.IMUX_IO_OK[0] bit 6	DEC[2]: ! O3_N	INT: !pass CELL.SINGLE_H[4] ← CELL.DEC_V[1]	DEC[2]: O1_P	DEC[1]: ! O1_P	INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_W0[2]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W0[2]	INT: !pass CELL.DOUBLE_IO_W0[0] ← CELL.DBUF_IO_V[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W0[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W0[0]	INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[3]	INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W1[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W1[0]	INT: mux CELL.LONG_IO_V[0] bit 1	INT: !bipass CELL.DOUBLE_IO_W0[0] = CELL.DOUBLE_IO_W2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W2[0]	INT: mux CELL.LONG_IO_V[0] bit 0	INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W2[0]
B4	HIO[2]: ! I_INV	INT: mux CELL.OUT_IO_WE_I1[1] bit 0	HIO[2]: ISTD bit 0	HIO[2]: OSTD bit 0	DEC[2]: ! O4_N	DEC[0]: ! O4_P	DEC[0]: O2_N	DEC[2]: O2_P	DEC[1]: O3_N	DEC[2]: O3_P	DEC[0]: ! O3_P	DEC[2]: ! O1_N	DEC[0]: ! O1_P	INT: !pass CELL.DOUBLE_IO_W0[2] ← CELL.DBUF_IO_V[1]	INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_W1[2]	INT: !bipass CELL.DOUBLE_IO_W0[2] = CELL.DOUBLE_IO_W2[2]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W2[2]	INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_W2[2]	INT: mux CELL.IMUX_IO_T[0] bit 5	INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_IO_V[2]	INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[0]	INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_WE_I2_S1
B3	HIO[2]: !invert T	INT: mux CELL.IMUX_HIO_T[2] bit 0	HIO[2]: !invert O	HIO[3]: ! READBACK_I bit 0	HIO[2]: ! READBACK_I bit 0	DEC[0]: O4_N	DEC[0]: ! O2_P	INT: mux CELL.IMUX_IO_IK[1] bit 5	DEC[1]: ! O3_P	HIO[2]: PULL bit 1	DEC[0]: O3_N	INT: mux CELL.IMUX_IO_IK[1] bit 7	DEC[0]: O1_N	TBUF[1]: ! DRIVE1	INT: mux CELL.IMUX_IO_T[1] bit 2	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W1[2]	INT: mux CELL.IMUX_IO_T[1] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 4	-	INT: mux CELL.IMUX_IO_T[0] bit 2	INT: mux CELL.IMUX_IO_T[0] bit 0	INT: mux CELL.DBUF_IO_V[0] bit 1	INT: mux CELL.DBUF_IO_V[0] bit 0	INT: mux CELL.IMUX_IO_T[0] bit 4	INT: mux CELL.IMUX_IO_T[0] bit 7	TBUF[0]: ! DRIVE1
B2	HIO[3]: OMODE bit 0	HIO[2]: OMODE bit 0	-	HIO[2]: PULL bit 0	INT: mux CELL.IMUX_HIO_O[2] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 3	INT: mux CELL.IMUX_IO_OK[1] bit 6	INT: mux CELL.IMUX_IO_OK[1] bit 5	INT: mux CELL.IMUX_IO_OK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 0	INT: mux CELL.IMUX_IO_IK[1] bit 4	INT: mux CELL.IMUX_IO_OK[1] bit 4	INT: mux CELL.IMUX_IO_OK[1] bit 2	INT: mux CELL.IMUX_IO_OK[1] bit 7	INT: mux CELL.IMUX_IO_T[1] bit 0	INT: mux CELL.IMUX_IO_T[1] bit 1	-	INT: mux CELL.IMUX_IO_T[1] bit 5	INT: mux CELL.IMUX_IO_T[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 6	INT: mux CELL.DBUF_IO_V[0] bit 2	INT: mux CELL.IMUX_IO_T[1] bit 7	INT: mux CELL.DBUF_IO_V[0] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 6
B1	HIO[3]: PULL bit 1	HIO[3]: PULL bit 0	INT: mux CELL.IMUX_HIO_O[3] bit 0	HIO[3]: !invert O	INT: mux CELL.IMUX_HIO_T[3] bit 0	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 3	INT: mux CELL.IMUX_IO_IK[1] bit 6	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 5	INT: mux CELL.LONG_H[1] bit 3	INT: mux CELL.LONG_H[1] bit 2	INT: mux CELL.IMUX_TBUF_I[1] bit 3	INT: mux CELL.IMUX_TBUF_I[1] bit 0	INT: mux CELL.IMUX_TBUF_I[1] bit 5	INT: mux CELL.IMUX_TBUF_T[1] bit 3	INT: mux CELL.IMUX_TBUF_T[1] bit 0	INT: mux CELL.IMUX_TBUF_T[1] bit 4	INT: mux CELL.IMUX_TBUF_T[1] bit 5	INT: mux CELL.IMUX_TBUF_T[0] bit 1	INT: mux CELL.IMUX_TBUF_T[0] bit 5	INT: mux CELL.IMUX_TBUF_I[0] bit 3	INT: mux CELL.IMUX_TBUF_I[0] bit 0	INT: mux CELL.IMUX_TBUF_I[0] bit 5	INT: mux CELL.LONG_H[0] bit 3	INT: mux CELL.LONG_H[0] bit 2
B0	HIO[3]: OSTD bit 0	HIO[3]: ISTD bit 0	HIO[3]: ! I_INV	INT: mux CELL.OUT_IO_WE_I2[1] bit 0	HIO[3]: !invert T	INT: mux CELL.IMUX_IO_O1[1] bit 4	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 0	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.LONG_H[1] bit 1	INT: mux CELL.LONG_H[1] bit 0	INT: mux CELL.IMUX_TBUF_I[1] bit 4	INT: mux CELL.IMUX_TBUF_I[1] bit 1	INT: mux CELL.IMUX_TBUF_I[1] bit 2	INT: mux CELL.IMUX_TBUF_T[1] bit 2	INT: mux CELL.IMUX_TBUF_T[1] bit 1	INT: mux CELL.IMUX_TBUF_T[0] bit 2	INT: mux CELL.IMUX_TBUF_T[0] bit 0	INT: mux CELL.IMUX_TBUF_T[0] bit 4	INT: mux CELL.IMUX_TBUF_T[0] bit 3	INT: mux CELL.IMUX_TBUF_I[0] bit 2	INT: mux CELL.IMUX_TBUF_I[0] bit 1	INT: mux CELL.IMUX_TBUF_I[0] bit 4	INT: mux CELL.LONG_H[0] bit 0	INT: mux CELL.LONG_H[0] bit 1

xc4000h IO_W1_S rect MAIN_S
Bit	Frame
Bit	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PULLUP_TBUF[0]: ! ENABLE
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile IO_E0

Cells: 3

Switchbox INT

xc4000h IO_E0 switchbox INT programmable buffers
Destination	Source	Bit
CELL.LONG_H[0]	CELL.SINGLE_V[1]	!MAIN_S[26][8]
CELL.LONG_H[1]	CELL.SINGLE_V[2]	!MAIN_S[30][8]
CELL.LONG_H[2]	CELL.SINGLE_V[3]	!MAIN[27][4]
CELL.LONG_H[3]	CELL.SINGLE_V[4]	!MAIN[27][6]
CELL.LONG_H[4]	CELL.SINGLE_V[5]	!MAIN[38][4]
CELL.LONG_H[5]	CELL.SINGLE_V[6]	!MAIN[40][6]
CELL.LONG_V[0]	CELL.SINGLE_H_E[1]	!MAIN[32][4]
CELL.LONG_V[1]	CELL.SINGLE_H_E[2]	!MAIN[38][8]
CELL.LONG_V[2]	CELL.SINGLE_H_E[3]	!MAIN[34][6]
CELL.LONG_V[3]	CELL.SINGLE_H[4]	!MAIN[34][4]
CELL.LONG_V[4]	CELL.SINGLE_H[5]	!MAIN[31][6]
CELL.LONG_V[5]	CELL.SINGLE_H[6]	!MAIN[35][8]

xc4000h IO_E0 switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[0]	CELL.DEC_V[0]	!MAIN[18][5]
CELL.SINGLE_H[0]	CELL.OUT_IO_WE_I2_S1	!MAIN[24][4]
CELL.SINGLE_H[1]	CELL.LONG_IO_V[0]	!MAIN[22][4]
CELL.SINGLE_H[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[21][4]
CELL.SINGLE_H[2]	CELL.LONG_IO_V[1]	!MAIN[13][7]
CELL.SINGLE_H[2]	CELL.OUT_IO_WE_I1[0]	!MAIN[21][7]
CELL.SINGLE_H[3]	CELL.DEC_V[1]	!MAIN[9][9]
CELL.SINGLE_H[3]	CELL.OUT_IO_WE_I1_S1	!MAIN[15][8]
CELL.SINGLE_H[4]	CELL.LONG_V[3]	!MAIN[33][4]
CELL.SINGLE_H[4]	CELL.DEC_V[2]	!MAIN[10][5]
CELL.SINGLE_H[4]	CELL.OUT_IO_WE_I2_S1	!MAIN[25][4]
CELL.SINGLE_H[5]	CELL.LONG_V[4]	!MAIN[27][3]
CELL.SINGLE_H[5]	CELL.LONG_IO_V[2]	!MAIN[19][4]
CELL.SINGLE_H[5]	CELL.OUT_IO_WE_I2[0]	!MAIN[20][4]
CELL.SINGLE_H[6]	CELL.LONG_V[5]	!MAIN[34][9]
CELL.SINGLE_H[6]	CELL.LONG_IO_V[3]	!MAIN[17][8]
CELL.SINGLE_H[6]	CELL.OUT_IO_WE_I1[0]	!MAIN[24][8]
CELL.SINGLE_H[7]	CELL.DEC_V[3]	!MAIN[17][9]
CELL.SINGLE_H[7]	CELL.OUT_IO_WE_I1_S1	!MAIN[25][8]
CELL.SINGLE_H_E[1]	CELL.LONG_V[0]	!MAIN[32][5]
CELL.SINGLE_H_E[2]	CELL.LONG_V[1]	!MAIN[40][9]
CELL.SINGLE_H_E[3]	CELL.LONG_V[2]	!MAIN[39][7]
CELL.SINGLE_V[0]	CELL.TIE_0	!MAIN[26][6]
CELL.SINGLE_V[0]	CELL.OUT_IO_WE_I2[0]	!MAIN[28][4]
CELL.SINGLE_V[1]	CELL.LONG_H[0]	!MAIN_S[28][8]
CELL.SINGLE_V[1]	CELL.OUT_IO_WE_I2[1]	!MAIN[29][4]
CELL.SINGLE_V[2]	CELL.LONG_H[1]	!MAIN_S[34][8]
CELL.SINGLE_V[2]	CELL.OUT_CLB_Y_E	!MAIN[30][4]
CELL.SINGLE_V[3]	CELL.LONG_H[2]	!MAIN_S[33][9]
CELL.SINGLE_V[3]	CELL.OUT_CLB_YQ_E	!MAIN[35][4]
CELL.SINGLE_V[4]	CELL.LONG_H[3]	!MAIN[26][7]
CELL.SINGLE_V[4]	CELL.OUT_IO_WE_I2[0]	!MAIN[39][3]
CELL.SINGLE_V[5]	CELL.LONG_H[4]	!MAIN[40][5]
CELL.SINGLE_V[5]	CELL.OUT_IO_WE_I2[1]	!MAIN[36][4]
CELL.SINGLE_V[6]	CELL.LONG_H[5]	!MAIN[40][7]
CELL.SINGLE_V[6]	CELL.OUT_CLB_Y_E	!MAIN[39][4]
CELL.SINGLE_V[7]	CELL.TIE_0	!MAIN[26][9]
CELL.SINGLE_V[7]	CELL.OUT_CLB_YQ_E	!MAIN[38][3]
CELL.DOUBLE_H0[0]	CELL.OUT_IO_WE_I1[0]	!MAIN[20][7]
CELL.DOUBLE_H0[1]	CELL.OUT_IO_WE_I2_S1	!MAIN[23][4]
CELL.DOUBLE_H1[0]	CELL.OUT_IO_WE_I1_S1	!MAIN[23][7]
CELL.DOUBLE_H1[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[23][6]
CELL.DOUBLE_V0[0]	CELL.OUT_CLB_YQ_E	!MAIN[26][4]
CELL.DOUBLE_V0[1]	CELL.OUT_IO_WE_I2[1]	!MAIN[37][4]
CELL.DOUBLE_V1[0]	CELL.OUT_CLB_Y_E	!MAIN[31][4]
CELL.DOUBLE_V1[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[40][4]
CELL.DOUBLE_IO_E0[0]	CELL.DBUF_IO_V[0]	!MAIN[19][6]
CELL.DOUBLE_IO_E0[1]	CELL.DBUF_IO_V[0]	!MAIN[16][7]
CELL.DOUBLE_IO_E0[2]	CELL.DBUF_IO_V[0]	!MAIN[17][6]
CELL.DOUBLE_IO_E0[3]	CELL.DBUF_IO_V[0]	!MAIN[17][7]
CELL.DOUBLE_IO_E2[0]	CELL.DBUF_IO_V[1]	!MAIN[15][5]
CELL.DOUBLE_IO_E2[1]	CELL.DBUF_IO_V[1]	!MAIN[15][6]
CELL.DOUBLE_IO_E2[2]	CELL.DBUF_IO_V[1]	!MAIN[13][4]
CELL.DOUBLE_IO_E2[3]	CELL.DBUF_IO_V[1]	!MAIN[22][6]

xc4000h IO_E0 switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.SINGLE_H_E[0]	!MAIN[28][6]
CELL.SINGLE_H[0]	CELL.SINGLE_V[0]	!MAIN[27][5]
CELL.SINGLE_H[0]	CELL.SINGLE_V_S[0]	!MAIN[30][3]
CELL.SINGLE_H[0]	CELL.DOUBLE_IO_E0[0]	!MAIN[25][5]
CELL.SINGLE_H[0]	CELL.DOUBLE_IO_E2[0]	!MAIN[16][5]
CELL.SINGLE_H[1]	CELL.SINGLE_H_E[1]	!MAIN[30][5]
CELL.SINGLE_H[1]	CELL.SINGLE_V[1]	!MAIN[29][5]
CELL.SINGLE_H[1]	CELL.SINGLE_V_S[1]	!MAIN[29][3]
CELL.SINGLE_H[1]	CELL.DOUBLE_IO_E1[0]	!MAIN[19][5]
CELL.SINGLE_H[2]	CELL.SINGLE_H_E[2]	!MAIN[32][8]
CELL.SINGLE_H[2]	CELL.SINGLE_V[2]	!MAIN[31][8]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[2]	!MAIN[33][8]
CELL.SINGLE_H[2]	CELL.DOUBLE_IO_E0[1]	!MAIN[16][9]
CELL.SINGLE_H[2]	CELL.DOUBLE_IO_E2[1]	!MAIN[10][9]
CELL.SINGLE_H[3]	CELL.SINGLE_H_E[3]	!MAIN[31][7]
CELL.SINGLE_H[3]	CELL.SINGLE_V[3]	!MAIN[28][7]
CELL.SINGLE_H[3]	CELL.SINGLE_V_S[3]	!MAIN[30][7]
CELL.SINGLE_H[3]	CELL.DOUBLE_IO_E1[1]	!MAIN[12][9]
CELL.SINGLE_H[4]	CELL.SINGLE_H_E[4]	!MAIN[36][6]
CELL.SINGLE_H[4]	CELL.SINGLE_V[4]	!MAIN[39][6]
CELL.SINGLE_H[4]	CELL.SINGLE_V_S[4]	!MAIN[35][6]
CELL.SINGLE_H[4]	CELL.DOUBLE_IO_E0[2]	!MAIN[17][4]
CELL.SINGLE_H[4]	CELL.DOUBLE_IO_E2[2]	!MAIN[13][5]
CELL.SINGLE_H[5]	CELL.SINGLE_H_E[5]	!MAIN[35][5]
CELL.SINGLE_H[5]	CELL.SINGLE_V[5]	!MAIN[36][3]
CELL.SINGLE_H[5]	CELL.SINGLE_V_S[5]	!MAIN[37][5]
CELL.SINGLE_H[5]	CELL.DOUBLE_IO_E1[2]	!MAIN[14][4]
CELL.SINGLE_H[6]	CELL.SINGLE_H_E[6]	!MAIN[35][7]
CELL.SINGLE_H[6]	CELL.SINGLE_V[6]	!MAIN[36][8]
CELL.SINGLE_H[6]	CELL.SINGLE_V_S[6]	!MAIN[36][7]
CELL.SINGLE_H[6]	CELL.DOUBLE_IO_E0[3]	!MAIN[25][9]
CELL.SINGLE_H[6]	CELL.DOUBLE_IO_E2[3]	!MAIN[19][9]
CELL.SINGLE_H[7]	CELL.SINGLE_H_E[7]	!MAIN[38][9]
CELL.SINGLE_H[7]	CELL.SINGLE_V[7]	!MAIN[35][9]
CELL.SINGLE_H[7]	CELL.SINGLE_V_S[7]	!MAIN[37][8]
CELL.SINGLE_H[7]	CELL.DOUBLE_IO_E1[3]	!MAIN[21][9]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V[0]	!MAIN[26][5]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V_S[0]	!MAIN[28][5]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V[1]	!MAIN[30][6]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V_S[1]	!MAIN[31][5]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V[2]	!MAIN[31][9]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V_S[2]	!MAIN[32][9]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V[3]	!MAIN[32][7]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V_S[3]	!MAIN[33][7]
CELL.SINGLE_H_E[4]	CELL.SINGLE_V[4]	!MAIN[39][8]
CELL.SINGLE_H_E[4]	CELL.SINGLE_V_S[4]	!MAIN[37][6]
CELL.SINGLE_H_E[5]	CELL.SINGLE_V[5]	!MAIN[36][5]
CELL.SINGLE_H_E[5]	CELL.SINGLE_V_S[5]	!MAIN[38][5]
CELL.SINGLE_H_E[6]	CELL.SINGLE_V[6]	!MAIN[34][7]
CELL.SINGLE_H_E[6]	CELL.SINGLE_V_S[6]	!MAIN[37][7]
CELL.SINGLE_H_E[7]	CELL.SINGLE_V[7]	!MAIN[37][9]
CELL.SINGLE_H_E[7]	CELL.SINGLE_V_S[7]	!MAIN[39][9]
CELL.SINGLE_V[0]	CELL.SINGLE_V_S[0]	!MAIN[29][6]
CELL.SINGLE_V[1]	CELL.SINGLE_V_S[1]	!MAIN[31][3]
CELL.SINGLE_V[2]	CELL.SINGLE_V_S[2]	!MAIN[30][9]
CELL.SINGLE_V[3]	CELL.SINGLE_V_S[3]	!MAIN[27][7]
CELL.SINGLE_V[4]	CELL.SINGLE_V_S[4]	!MAIN[38][6]
CELL.SINGLE_V[5]	CELL.SINGLE_V_S[5]	!MAIN[39][5]
CELL.SINGLE_V[6]	CELL.SINGLE_V_S[6]	!MAIN[38][7]
CELL.SINGLE_V[7]	CELL.SINGLE_V_S[7]	!MAIN[36][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_H2[0]	!MAIN[29][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_V0[0]	!MAIN[27][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_V2[0]	!MAIN[28][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_E0[1]	!MAIN[15][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_E1[1]	!MAIN[13][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_E2[1]	!MAIN[11][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_H2[1]	!MAIN[33][6]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_V0[1]	!MAIN[32][6]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_V2[1]	!MAIN[33][3]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_E0[2]	!MAIN[16][4]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_E1[2]	!MAIN[15][3]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_E2[2]	!MAIN[14][5]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_E0[0]	!MAIN[23][5]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_E1[0]	!MAIN[20][5]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_E2[0]	!MAIN[17][5]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_E0[3]	!MAIN[24][9]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_E1[3]	!MAIN[22][9]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_E2[3]	!MAIN[20][9]
CELL.DOUBLE_H2[0]	CELL.DOUBLE_V0[0]	!MAIN[29][7]
CELL.DOUBLE_H2[0]	CELL.DOUBLE_V2[0]	!MAIN[29][8]
CELL.DOUBLE_H2[1]	CELL.DOUBLE_V0[1]	!MAIN[33][5]
CELL.DOUBLE_H2[1]	CELL.DOUBLE_V2[1]	!MAIN[34][5]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_V2[0]	!MAIN[27][8]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_V2[1]	!MAIN[34][3]
CELL.DOUBLE_IO_E0[0]	CELL.DOUBLE_IO_E2[0]	!MAIN[22][5]
CELL.DOUBLE_IO_E0[1]	CELL.DOUBLE_IO_E2[1]	!MAIN[14][9]
CELL.DOUBLE_IO_E0[2]	CELL.DOUBLE_IO_E2[2]	!MAIN[15][4]
CELL.DOUBLE_IO_E0[3]	CELL.DOUBLE_IO_E2[3]	!MAIN[23][9]

xc4000h IO_E0 switchbox INT muxes DBUF_IO_V[0]
Bits				Destination
MAIN[21][3]	MAIN[24][2]	MAIN[22][2]	MAIN[22][3]	CELL.DBUF_IO_V[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_E2[0]
0	1	0	1	CELL.DOUBLE_IO_E2[1]
0	1	1	0	CELL.DOUBLE_IO_E2[3]
1	1	1	1	CELL.DOUBLE_IO_E2[2]

xc4000h IO_E0 switchbox INT muxes DBUF_IO_V[1]
Bits				Destination
MAIN[8][8]	MAIN[9][8]	MAIN[11][8]	MAIN[10][8]	CELL.DBUF_IO_V[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_E0[1]
0	1	0	1	CELL.DOUBLE_IO_E0[2]
0	1	1	0	CELL.DOUBLE_IO_E0[3]
1	1	1	1	CELL.DOUBLE_IO_E0[0]

xc4000h IO_E0 switchbox INT muxes LONG_H[0]
Bits				Destination
MAIN[24][1]	MAIN[24][0]	MAIN[25][1]	MAIN[25][0]	CELL.LONG_H[0]
				Source
0	0	0	1	CELL.LONG_IO_V[0]
0	0	1	0	CELL.DEC_V[3]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000h IO_E0 switchbox INT muxes LONG_H[1]
Bits				Destination
MAIN[10][1]	MAIN[10][0]	MAIN[11][0]	MAIN[11][1]	CELL.LONG_H[1]
				Source
0	0	0	1	CELL.LONG_IO_V[1]
0	0	1	0	CELL.DEC_V[2]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000h IO_E0 switchbox INT muxes LONG_H[4]
Bits				Destination
MAIN[24][6]	MAIN[22][7]	MAIN[24][7]	MAIN[25][6]	CELL.LONG_H[4]
				Source
0	0	0	1	CELL.LONG_IO_V[2]
0	0	1	0	CELL.DEC_V[1]
0	1	1	1	CELL.OUT_IO_WE_I2[0]
1	1	1	1	off

xc4000h IO_E0 switchbox INT muxes LONG_H[5]
Bits				Destination
MAIN[15][7]	MAIN[19][7]	MAIN[21][6]	MAIN[20][6]	CELL.LONG_H[5]
				Source
0	0	0	1	CELL.LONG_IO_V[3]
0	0	1	0	CELL.DEC_V[0]
0	1	1	1	CELL.OUT_IO_WE_I2[0]
1	1	1	1	off

xc4000h IO_E0 switchbox INT muxes LONG_IO_V[0]
Bits		Destination
MAIN[21][5]	MAIN[24][5]	CELL.LONG_IO_V[0]
		Source
0	0	CELL.LONG_H[0]
0	1	CELL.SINGLE_H[1]
1	1	off

xc4000h IO_E0 switchbox INT muxes LONG_IO_V[1]
Bits				Destination
MAIN[12][8]	MAIN[8][9]	MAIN[13][8]	MAIN[14][8]	CELL.LONG_IO_V[1]
				Source
0	0	0	1	CELL.LONG_H[1]
0	0	1	0	CELL.LONG_H[3]
0	1	1	1	CELL.SINGLE_H[2]
1	1	1	1	off

xc4000h IO_E0 switchbox INT muxes LONG_IO_V[2]
Bits				Destination
MAIN[20][8]	MAIN[21][8]	MAIN[23][8]	MAIN[22][8]	CELL.LONG_IO_V[2]
				Source
0	0	0	1	CELL.LONG_H[2]
0	0	1	0	CELL.LONG_H[4]
0	1	1	1	CELL.SINGLE_H[5]
1	1	1	1	off

xc4000h IO_E0 switchbox INT muxes LONG_IO_V[3]
Bits		Destination
MAIN[19][8]	MAIN[16][8]	CELL.LONG_IO_V[3]
		Source
0	0	CELL.LONG_H[5]
0	1	CELL.SINGLE_H[6]
1	1	off

xc4000h IO_E0 switchbox INT muxes IMUX_CLB_F1
Bits								Destination
MAIN[31][2]	MAIN[33][0]	MAIN[32][1]	MAIN[31][0]	MAIN[32][3]	MAIN[31][1]	MAIN[32][0]	MAIN[32][2]	CELL.IMUX_CLB_F1
								Source
0	0	1	0	0	1	1	1	CELL.SINGLE_V[3]
0	0	1	0	1	0	1	1	CELL.LONG_V[4]
0	0	1	0	1	1	1	0	CELL.SINGLE_V[7]
0	0	1	1	1	1	1	1	CELL.SINGLE_V[0]
0	1	0	0	0	1	1	1	CELL.LONG_V[3]
0	1	0	0	1	0	1	1	CELL.DOUBLE_V0[1]
0	1	0	0	1	1	1	0	CELL.LONG_V[0]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[1]
0	1	1	0	0	1	0	1	CELL.SINGLE_V[5]
0	1	1	0	1	0	0	1	CELL.LONG_V[1]
0	1	1	0	1	1	0	0	CELL.SINGLE_V[6]
0	1	1	1	1	1	0	1	CELL.DOUBLE_V1[1]
1	1	1	0	0	1	1	1	CELL.DOUBLE_V1[0]
1	1	1	0	1	0	1	1	CELL.SINGLE_V[4]
1	1	1	0	1	1	1	0	CELL.DOUBLE_V0[0]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[2]

xc4000h IO_E0 switchbox INT muxes IMUX_CLB_F3
Bits									Destination
MAIN[38][2]	MAIN[40][0]	MAIN[39][2]	MAIN[40][1]	MAIN[38][0]	MAIN[39][1]	MAIN[40][2]	MAIN[39][0]	MAIN[40][3]	CELL.IMUX_CLB_F3
									Source
0	0	0	0	1	1	1	1	1	CELL.SINGLE_V[0]
0	0	0	1	1	1	0	1	1	CELL.DOUBLE_V0[0]
0	0	0	1	1	1	1	0	1	CELL.LONG_V[2]
0	0	1	1	1	1	1	1	1	CELL.SINGLE_V[3]
0	1	0	0	0	1	1	1	1	CELL.DOUBLE_V1[1]
0	1	0	0	1	0	1	1	1	CELL.LONG_V[1]
0	1	0	1	0	1	0	1	1	CELL.DOUBLE_V0[1]
0	1	0	1	0	1	1	0	1	CELL.LONG_V[5]
0	1	0	1	1	0	0	1	1	CELL.SINGLE_V[4]
0	1	0	1	1	0	1	0	1	CELL.LONG_V[4]
0	1	0	1	1	1	1	1	0	CELL.GCLK[0]
0	1	1	1	0	1	1	1	1	CELL.SINGLE_V[1]
0	1	1	1	1	0	1	1	1	CELL.SINGLE_V[2]
1	1	0	0	1	1	1	1	1	CELL.SINGLE_V[6]
1	1	0	1	1	1	0	1	1	CELL.DOUBLE_V1[0]
1	1	0	1	1	1	1	0	1	CELL.SINGLE_V[5]
1	1	1	1	1	1	1	1	1	CELL.SINGLE_V[7]

xc4000h IO_E0 switchbox INT muxes IMUX_CLB_G1
Bits								Destination
MAIN[26][0]	MAIN[26][3]	MAIN[28][0]	MAIN[28][1]	MAIN[27][1]	MAIN[26][1]	MAIN[27][0]	MAIN[26][2]	CELL.IMUX_CLB_G1
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_V[0]
0	0	0	1	0	1	1	1	CELL.SINGLE_V[2]
0	0	0	1	1	1	0	1	CELL.SINGLE_V[4]
0	0	1	0	1	0	1	1	CELL.LONG_V[4]
0	0	1	0	1	1	1	0	CELL.LONG_V[3]
0	0	1	1	0	0	1	1	CELL.SINGLE_V[1]
0	0	1	1	0	1	1	0	CELL.DOUBLE_V1[0]
0	0	1	1	1	0	0	1	CELL.DOUBLE_V0[1]
0	0	1	1	1	1	0	0	CELL.LONG_V[0]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[3]
0	1	1	1	0	1	1	1	CELL.DOUBLE_V0[0]
0	1	1	1	1	1	0	1	CELL.SINGLE_V[7]
1	0	0	1	1	1	1	1	CELL.DOUBLE_V1[1]
1	0	1	1	1	0	1	1	CELL.LONG_V[1]
1	0	1	1	1	1	1	0	CELL.SINGLE_V[5]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[6]

xc4000h IO_E0 switchbox INT muxes IMUX_CLB_G3
Bits									Destination
MAIN[34][0]	MAIN[33][2]	MAIN[35][1]	MAIN[33][1]	MAIN[34][2]	MAIN[35][0]	MAIN[34][1]	MAIN[35][2]	MAIN[35][3]	CELL.IMUX_CLB_G3
									Source
0	0	0	1	1	1	1	1	1	CELL.SPECIAL_CLB_CIN
0	0	1	0	0	1	1	1	1	CELL.SINGLE_V[0]
0	0	1	0	1	0	1	1	1	CELL.SINGLE_V[2]
0	0	1	0	1	1	1	0	1	CELL.SINGLE_V[4]
0	0	1	1	0	1	0	1	1	CELL.LONG_V[4]
0	0	1	1	0	1	1	1	0	CELL.LONG_V[2]
0	0	1	1	1	0	0	1	1	CELL.SINGLE_V[1]
0	0	1	1	1	0	1	1	0	CELL.SINGLE_V[6]
0	0	1	1	1	1	0	0	1	CELL.DOUBLE_V0[1]
0	0	1	1	1	1	1	0	0	CELL.LONG_V[5]
0	1	1	1	0	1	1	1	1	CELL.DOUBLE_V0[0]
0	1	1	1	1	0	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	1	1	1	0	1	CELL.DOUBLE_V1[0]
1	0	1	0	1	1	1	1	1	CELL.DOUBLE_V1[1]
1	0	1	1	1	1	0	1	1	CELL.LONG_V[1]
1	0	1	1	1	1	1	1	0	CELL.SINGLE_V[7]
1	1	1	1	1	1	1	1	1	CELL.SINGLE_V[3]

xc4000h IO_E0 switchbox INT muxes IMUX_CLB_C1
Bits								Destination
MAIN[28][3]	MAIN[28][2]	MAIN[30][1]	MAIN[29][0]	MAIN[29][1]	MAIN[30][2]	MAIN[29][2]	MAIN[30][0]	CELL.IMUX_CLB_C1
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_V[0]
0	0	0	1	0	1	1	1	CELL.SINGLE_V[1]
0	0	1	0	1	0	1	1	CELL.DOUBLE_V0[0]
0	0	1	0	1	1	0	1	CELL.DOUBLE_V1[0]
0	0	1	1	0	0	1	1	CELL.SINGLE_V[3]
0	0	1	1	0	1	0	1	CELL.SINGLE_V[7]
0	0	1	1	1	0	1	0	CELL.LONG_V[2]
0	0	1	1	1	1	0	0	CELL.LONG_V[3]
0	1	1	0	1	1	1	1	CELL.DOUBLE_V1[1]
0	1	1	1	0	1	1	1	CELL.SINGLE_V[2]
1	0	0	1	1	1	1	1	CELL.DOUBLE_V0[1]
1	0	1	1	1	0	1	1	CELL.SINGLE_V[5]
1	0	1	1	1	1	0	1	CELL.SINGLE_V[6]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[4]

xc4000h IO_E0 switchbox INT muxes IMUX_CLB_C3
Bits								Destination
MAIN[36][0]	MAIN[36][1]	MAIN[37][1]	MAIN[37][0]	MAIN[36][2]	MAIN[37][2]	MAIN[37][3]	MAIN[38][1]	CELL.IMUX_CLB_C3
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_V[0]
0	0	0	1	0	1	1	1	CELL.SINGLE_V[2]
0	0	0	1	1	1	1	0	CELL.GCLK[2]
0	0	1	0	1	0	1	1	CELL.SINGLE_V[3]
0	0	1	0	1	1	0	1	CELL.SINGLE_V[7]
0	0	1	1	0	0	1	1	CELL.DOUBLE_V0[0]
0	0	1	1	0	1	0	1	CELL.DOUBLE_V1[0]
0	0	1	1	1	0	1	0	CELL.LONG_V[3]
0	0	1	1	1	1	0	0	CELL.LONG_V[2]
0	1	1	0	1	1	1	1	CELL.DOUBLE_V1[1]
0	1	1	1	0	1	1	1	CELL.SINGLE_V[1]
1	0	0	1	1	1	1	1	CELL.DOUBLE_V0[1]
1	0	1	1	1	0	1	1	CELL.SINGLE_V[5]
1	0	1	1	1	1	0	1	CELL.SINGLE_V[6]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[4]

xc4000h IO_E0 switchbox INT muxes IMUX_TBUF_I[0]
Bits						Destination
MAIN[23][1]	MAIN[21][0]	MAIN[23][0]	MAIN[21][1]	MAIN[22][0]	MAIN[22][1]	CELL.IMUX_TBUF_I[0]
						Source
0	0	0	1	1	1	CELL.DOUBLE_IO_E2[2]
0	0	1	0	1	1	CELL.OUT_IO_WE_I2[0]
0	0	1	1	0	1	CELL.LONG_IO_V[2]
0	0	1	1	1	0	CELL.DEC_V[1]
0	1	1	1	1	1	CELL.DOUBLE_IO_E1[2]
1	0	0	1	1	1	CELL.DOUBLE_IO_E1[3]
1	0	1	0	1	1	CELL.DOUBLE_IO_E2[3]
1	0	1	1	0	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_E0 switchbox INT muxes IMUX_TBUF_I[1]
Bits						Destination
MAIN[12][1]	MAIN[14][1]	MAIN[12][0]	MAIN[14][0]	MAIN[13][0]	MAIN[13][1]	CELL.IMUX_TBUF_I[1]
						Source
0	0	0	1	1	1	CELL.DOUBLE_IO_E1[2]
0	0	1	1	1	1	CELL.DOUBLE_IO_E1[3]
0	1	0	0	1	1	CELL.OUT_IO_WE_I2[0]
0	1	0	1	0	1	CELL.LONG_IO_V[1]
0	1	0	1	1	0	CELL.DEC_V[2]
0	1	1	0	1	1	CELL.DOUBLE_IO_E2[3]
0	1	1	1	1	0	CELL.OUT_IO_WE_I2[1]
1	1	0	1	1	1	CELL.DOUBLE_IO_E2[2]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_E0 switchbox INT muxes IMUX_TBUF_T[0]
Bits						Destination
MAIN[17][0]	MAIN[19][0]	MAIN[20][0]	MAIN[20][1]	MAIN[19][1]	MAIN[18][0]	CELL.IMUX_TBUF_T[0]
						Source
0	0	0	1	1	1	CELL.TIE_1
0	0	1	1	1	1	CELL.TIE_0
0	1	0	0	1	1	CELL.DOUBLE_IO_E2[0]
0	1	0	1	0	1	CELL.LONG_IO_V[3]
0	1	0	1	1	0	CELL.DEC_V[3]
0	1	1	0	1	1	CELL.DOUBLE_IO_E1[0]
0	1	1	1	0	1	CELL.LONG_IO_V[2]
0	1	1	1	1	0	CELL.DEC_V[0]
1	1	0	1	1	1	CELL.DOUBLE_IO_E2[1]
1	1	1	1	1	1	CELL.DOUBLE_IO_E1[1]

xc4000h IO_E0 switchbox INT muxes IMUX_TBUF_T[1]
Bits						Destination
MAIN[15][0]	MAIN[17][1]	MAIN[15][1]	MAIN[18][1]	MAIN[16][0]	MAIN[16][1]	CELL.IMUX_TBUF_T[1]
						Source
0	0	0	1	1	1	CELL.TIE_1
0	0	1	1	1	1	CELL.TIE_0
0	1	0	0	1	1	CELL.DOUBLE_IO_E1[1]
0	1	0	1	0	1	CELL.LONG_IO_V[2]
0	1	0	1	1	0	CELL.DEC_V[0]
0	1	1	0	1	1	CELL.DOUBLE_IO_E2[1]
0	1	1	1	0	1	CELL.LONG_IO_V[3]
0	1	1	1	1	0	CELL.DEC_V[3]
1	1	0	1	1	1	CELL.DOUBLE_IO_E1[0]
1	1	1	1	1	1	CELL.DOUBLE_IO_E2[0]

xc4000h IO_E0 switchbox INT muxes IMUX_IO_O1[0]
Bits						Destination
MAIN[5][9]	MAIN[5][8]	MAIN[7][8]	MAIN[7][9]	MAIN[6][9]	MAIN[6][8]	CELL.IMUX_IO_O1[0]
						Source
0	0	0	1	1	1	CELL.DEC_V[3]
0	0	1	0	1	1	CELL.DEC_V[2]
0	0	1	1	0	1	CELL.DEC_V[1]
0	0	1	1	1	0	CELL.DEC_V[0]
0	1	1	1	1	1	CELL.DOUBLE_H0[1]
1	0	0	1	1	1	CELL.DOUBLE_H1[0]
1	0	1	0	1	1	CELL.LONG_H[3]
1	0	1	1	0	1	CELL.LONG_H[4]
1	0	1	1	1	0	CELL.LONG_H[5]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_E0 switchbox INT muxes IMUX_IO_O1[1]
Bits						Destination
MAIN[6][0]	MAIN[5][0]	MAIN[9][1]	MAIN[7][0]	MAIN[8][0]	MAIN[9][0]	CELL.IMUX_IO_O1[1]
						Source
0	0	0	1	1	1	CELL.LONG_H[0]
0	0	1	0	1	1	CELL.LONG_H[1]
0	0	1	1	0	1	CELL.DEC_V[2]
0	0	1	1	1	0	CELL.DEC_V[3]
0	1	0	1	1	1	CELL_S.DOUBLE_H1[1]
0	1	1	0	1	1	CELL.LONG_H[2]
0	1	1	1	0	1	CELL.DEC_V[0]
0	1	1	1	1	0	CELL.DEC_V[1]
1	0	1	1	1	1	CELL_S.DOUBLE_H0[0]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_E0 switchbox INT muxes IMUX_IO_OK[0]
Bits								Destination
MAIN[7][6]	MAIN[16][6]	MAIN[8][5]	MAIN[13][6]	MAIN[10][6]	MAIN[11][6]	MAIN[14][6]	MAIN[9][6]	CELL.IMUX_IO_OK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_H[2]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[3]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[4]

xc4000h IO_E0 switchbox INT muxes IMUX_IO_OK[1]
Bits								Destination
MAIN[5][2]	MAIN[7][2]	MAIN[8][2]	MAIN[12][2]	MAIN[6][2]	MAIN[13][2]	MAIN[14][2]	MAIN[9][2]	CELL.IMUX_IO_OK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_S.SINGLE_H[2]
0	1	1	1	1	1	0	1	CELL_S.SINGLE_H[3]
0	1	1	1	1	1	1	0	CELL_S.SINGLE_H[4]
1	1	1	1	1	1	1	1	CELL_S.SINGLE_H[5]

xc4000h IO_E0 switchbox INT muxes IMUX_IO_IK[0]
Bits								Destination
MAIN[5][7]	MAIN[11][7]	MAIN[12][7]	MAIN[9][7]	MAIN[7][7]	MAIN[8][7]	MAIN[10][7]	MAIN[6][7]	CELL.IMUX_IO_IK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_H[3]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[2]

xc4000h IO_E0 switchbox INT muxes IMUX_IO_IK[1]
Bits								Destination
MAIN[5][1]	MAIN[7][1]	MAIN[7][3]	MAIN[11][2]	MAIN[6][1]	MAIN[8][1]	MAIN[10][2]	MAIN[11][3]	CELL.IMUX_IO_IK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_S.SINGLE_H[2]
0	1	1	1	1	1	0	1	CELL_S.SINGLE_H[4]
0	1	1	1	1	1	1	0	CELL_S.SINGLE_H[5]
1	1	1	1	1	1	1	1	CELL_S.SINGLE_H[3]

xc4000h IO_E0 switchbox INT muxes IMUX_IO_T[0]
Bits								Destination
MAIN[20][3]	MAIN[18][4]	MAIN[19][2]	MAIN[21][2]	MAIN[19][3]	MAIN[23][3]	MAIN[20][2]	MAIN[24][3]	CELL.IMUX_IO_T[0]
								Source
0	0	0	1	1	0	1	1	CELL.LONG_IO_V[3]
0	0	0	1	1	1	0	1	CELL.LONG_IO_V[1]
0	0	0	1	1	1	1	0	CELL.GCLK[0]
0	0	1	0	1	0	1	1	CELL.LONG_IO_V[0]
0	0	1	0	1	1	0	1	CELL.DEC_V[2]
0	0	1	1	0	0	1	1	CELL.DOUBLE_IO_E2[1]
0	0	1	1	0	1	0	1	CELL.LONG_IO_V[2]
0	0	1	1	0	1	1	0	CELL.DEC_V[3]
0	1	1	1	1	1	1	1	CELL.TIE_0
1	0	0	1	1	1	1	1	CELL.DOUBLE_IO_E1[0]
1	0	1	0	1	1	1	1	CELL.DOUBLE_IO_E1[1]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_E2[0]

xc4000h IO_E0 switchbox INT muxes IMUX_IO_T[1]
Bits								Destination
MAIN[16][3]	MAIN[14][3]	MAIN[18][2]	MAIN[23][2]	MAIN[17][3]	MAIN[25][2]	MAIN[16][2]	MAIN[15][2]	CELL.IMUX_IO_T[1]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	1	0	1	1	CELL.LONG_IO_V[1]
0	0	1	0	1	1	0	1	CELL.LONG_IO_V[3]
0	0	1	0	1	1	1	0	CELL.GCLK[0]
0	0	1	1	0	0	1	1	CELL.DEC_V[2]
0	0	1	1	0	1	0	1	CELL.LONG_IO_V[0]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_E1[0]
0	1	1	1	0	1	1	1	CELL.DOUBLE_IO_E2[0]
1	0	1	1	1	0	1	1	CELL.DOUBLE_IO_E2[1]
1	0	1	1	1	1	0	1	CELL.LONG_IO_V[2]
1	0	1	1	1	1	1	0	CELL.DEC_V[3]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_E1[1]

xc4000h IO_E0 switchbox INT muxes IMUX_HIO_O[0]
Bits	Destination
MAIN[0][7]	CELL.IMUX_HIO_O[0]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_G1

xc4000h IO_E0 switchbox INT muxes IMUX_HIO_O[1]
Bits	Destination
MAIN[3][6]	CELL.IMUX_HIO_O[1]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_G1

xc4000h IO_E0 switchbox INT muxes IMUX_HIO_O[2]
Bits	Destination
MAIN[4][2]	CELL.IMUX_HIO_O[2]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_F1

xc4000h IO_E0 switchbox INT muxes IMUX_HIO_O[3]
Bits	Destination
MAIN[2][1]	CELL.IMUX_HIO_O[3]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_F1

xc4000h IO_E0 switchbox INT muxes IMUX_HIO_T[0]
Bits	Destination
MAIN[4][8]	CELL.IMUX_HIO_T[0]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_OK[0]

xc4000h IO_E0 switchbox INT muxes IMUX_HIO_T[1]
Bits	Destination
MAIN[1][6]	CELL.IMUX_HIO_T[1]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_IK[0]

xc4000h IO_E0 switchbox INT muxes IMUX_HIO_T[2]
Bits	Destination
MAIN[1][3]	CELL.IMUX_HIO_T[2]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_IK[1]

xc4000h IO_E0 switchbox INT muxes IMUX_HIO_T[3]
Bits	Destination
MAIN[4][1]	CELL.IMUX_HIO_T[3]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_OK[1]

xc4000h IO_E0 switchbox INT muxes OUT_IO_WE_I1[0]
Bits	Destination
MAIN[0][5]	CELL.OUT_IO_WE_I1[0]
	Source
0	CELL.OUT_HIO_I[1]
1	CELL.OUT_HIO_I[0]

xc4000h IO_E0 switchbox INT muxes OUT_IO_WE_I1[1]
Bits	Destination
MAIN[1][4]	CELL.OUT_IO_WE_I1[1]
	Source
0	CELL.OUT_HIO_I[2]
1	CELL.OUT_HIO_I[3]

xc4000h IO_E0 switchbox INT muxes OUT_IO_WE_I2[0]
Bits	Destination
MAIN[3][9]	CELL.OUT_IO_WE_I2[0]
	Source
0	CELL.OUT_HIO_I[0]
1	CELL.OUT_HIO_I[1]

xc4000h IO_E0 switchbox INT muxes OUT_IO_WE_I2[1]
Bits	Destination
MAIN[3][0]	CELL.OUT_IO_WE_I2[1]
	Source
0	CELL.OUT_HIO_I[3]
1	CELL.OUT_HIO_I[2]

Bels TBUF

xc4000h IO_E0 bel TBUF pins
Pin	Direction	TBUF[0]	TBUF[1]
I	in	CELL.IMUX_TBUF_I[0]	CELL.IMUX_TBUF_I[1]
T	in	CELL.IMUX_TBUF_T[0]	CELL.IMUX_TBUF_T[1]
O	bidir	CELL.LONG_H[2]	CELL.LONG_H[3]

xc4000h IO_E0 bel TBUF attribute bits
Attribute	TBUF[0]	TBUF[1]
DRIVE1	!MAIN[25][3]	!MAIN[13][3]

Bels HIO

xc4000h IO_E0 bel HIO pins
Pin	Direction	HIO[0]	HIO[1]	HIO[2]	HIO[3]
O	in	CELL.IMUX_HIO_O[0] invert by !MAIN[1][8]	CELL.IMUX_HIO_O[1] invert by !MAIN[2][6]	CELL.IMUX_HIO_O[2] invert by !MAIN[2][3]	CELL.IMUX_HIO_O[3] invert by !MAIN[3][1]
T	in	CELL.IMUX_HIO_T[0] invert by !MAIN[4][9]	CELL.IMUX_HIO_T[1] invert by !MAIN[0][6]	CELL.IMUX_HIO_T[2] invert by !MAIN[0][3]	CELL.IMUX_HIO_T[3] invert by !MAIN[4][0]
I	out	CELL.OUT_HIO_I[0]	CELL.OUT_HIO_I[1]	CELL.OUT_HIO_I[2]	CELL.OUT_HIO_I[3]

xc4000h IO_E0 bel HIO attribute bits
Attribute	HIO[0]	HIO[1]	HIO[2]	HIO[3]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
ISTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OSTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OMODE	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]
I_INV	!MAIN[2][9]	!MAIN[1][5]	!MAIN[0][4]	!MAIN[2][0]
READBACK_I bit 0	!MAIN[2][8]	!MAIN[0][8]	!MAIN[4][3]	!MAIN[3][3]

xc4000h IO_E0 enum IO_PULL
HIO[0].PULL	MAIN[1][7]	MAIN[2][7]
HIO[1].PULL	MAIN[4][6]	MAIN[8][6]
HIO[2].PULL	MAIN[9][3]	MAIN[3][2]
HIO[3].PULL	MAIN[0][1]	MAIN[1][1]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

xc4000h IO_E0 enum IO_STD
HIO[0].ISTD	MAIN[1][9]
HIO[1].ISTD	MAIN[2][5]
HIO[2].ISTD	MAIN[2][4]
HIO[3].ISTD	MAIN[1][0]
CMOS	0
TTL	1

xc4000h IO_E0 enum IO_STD
HIO[0].OSTD	MAIN[0][9]
HIO[1].OSTD	MAIN[3][5]
HIO[2].OSTD	MAIN[3][4]
HIO[3].OSTD	MAIN[0][0]
CMOS	1
TTL	0

xc4000h IO_E0 enum HIO_OMODE
HIO[0].OMODE	MAIN[3][7]
HIO[1].OMODE	MAIN[4][7]
HIO[2].OMODE	MAIN[1][2]
HIO[3].OMODE	MAIN[0][2]
CAP	1
RES	0

Bels DEC

xc4000h IO_E0 bel DEC pins
Pin	Direction	DEC[0]	DEC[1]	DEC[2]
I	in	CELL.OUT_IO_WE_I1[0]	CELL.IMUX_CLB_C1	CELL.OUT_IO_WE_I1[1]
O1	bidir	CELL.DEC_V[0]	CELL.DEC_V[0]	CELL.DEC_V[0]
O2	bidir	CELL.DEC_V[1]	CELL.DEC_V[1]	CELL.DEC_V[1]
O3	bidir	CELL.DEC_V[2]	CELL.DEC_V[2]	CELL.DEC_V[2]
O4	bidir	CELL.DEC_V[3]	CELL.DEC_V[3]	CELL.DEC_V[3]

xc4000h IO_E0 bel DEC attribute bits
Attribute	DEC[0]	DEC[1]	DEC[2]
O1_P	!MAIN[5][4]	!MAIN[5][6]	MAIN[4][5]
O1_N	MAIN[5][3]	MAIN[5][5]	!MAIN[4][4]
O2_P	!MAIN[10][4]	!MAIN[8][3]	MAIN[9][4]
O2_N	MAIN[10][3]	MAIN[8][4]	!MAIN[9][5]
O3_P	!MAIN[6][3]	!MAIN[6][6]	MAIN[7][4]
O3_N	MAIN[6][4]	MAIN[6][5]	!MAIN[7][5]
O4_P	!MAIN[12][4]	!MAIN[12][5]	MAIN[11][5]
O4_N	MAIN[12][3]	MAIN[12][6]	!MAIN[11][4]

Bels PULLUP

xc4000h IO_E0 bel PULLUP pins
Pin	Direction	PULLUP_TBUF[0]	PULLUP_TBUF[1]
O	bidir	CELL.LONG_H[2]	CELL.LONG_H[3]

xc4000h IO_E0 bel PULLUP attribute bits
Attribute	PULLUP_TBUF[0]	PULLUP_TBUF[1]
ENABLE	!MAIN_S[25][7]	!MAIN[14][7]

Bel wires

xc4000h IO_E0 bel wires
Wire	Pins
CELL.LONG_H[2]	TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]	TBUF[1].O, PULLUP_TBUF[1].O
CELL.DEC_V[0]	DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_V[1]	DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.DEC_V[2]	DEC[0].O3, DEC[1].O3, DEC[2].O3
CELL.DEC_V[3]	DEC[0].O4, DEC[1].O4, DEC[2].O4
CELL.IMUX_CLB_C1	DEC[1].I
CELL.IMUX_TBUF_I[0]	TBUF[0].I
CELL.IMUX_TBUF_I[1]	TBUF[1].I
CELL.IMUX_TBUF_T[0]	TBUF[0].T
CELL.IMUX_TBUF_T[1]	TBUF[1].T
CELL.IMUX_HIO_O[0]	HIO[0].O
CELL.IMUX_HIO_O[1]	HIO[1].O
CELL.IMUX_HIO_O[2]	HIO[2].O
CELL.IMUX_HIO_O[3]	HIO[3].O
CELL.IMUX_HIO_T[0]	HIO[0].T
CELL.IMUX_HIO_T[1]	HIO[1].T
CELL.IMUX_HIO_T[2]	HIO[2].T
CELL.IMUX_HIO_T[3]	HIO[3].T
CELL.OUT_IO_WE_I1[0]	DEC[0].I
CELL.OUT_IO_WE_I1[1]	DEC[2].I
CELL.OUT_HIO_I[0]	HIO[0].I
CELL.OUT_HIO_I[1]	HIO[1].I
CELL.OUT_HIO_I[2]	HIO[2].I
CELL.OUT_HIO_I[3]	HIO[3].I

Bitstream

xc4000h IO_E0 rect MAIN
Bit	Frame
Bit	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7]	INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7]	INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7]	INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5]	-	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0]	INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0	INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_E0[3]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E0[3]	INT: !bipass CELL.DOUBLE_IO_E0[3] = CELL.DOUBLE_IO_E2[3]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E1[3]	INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_E1[3]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E2[3]	INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_E2[3]	-	INT: !pass CELL.SINGLE_H[7] ← CELL.DEC_V[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E0[1]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E0[1]	INT: !bipass CELL.DOUBLE_IO_E0[1] = CELL.DOUBLE_IO_E2[1]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E1[1]	INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E1[1]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E2[1]	INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E2[1]	INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[1]	INT: mux CELL.LONG_IO_V[1] bit 2	INT: mux CELL.IMUX_IO_O1[0] bit 2	INT: mux CELL.IMUX_IO_O1[0] bit 1	INT: mux CELL.IMUX_IO_O1[0] bit 5	HIO[0]: !invert T	INT: mux CELL.OUT_IO_WE_I2[0] bit 0	HIO[0]: ! I_INV	HIO[0]: ISTD bit 0	HIO[0]: OSTD bit 0
B8	-	INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4]	INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6]	INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6]	-	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2]	-	INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0]	-	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0]	-	INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_IO_WE_I1_S1	INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_IO_WE_I1[0]	INT: mux CELL.LONG_IO_V[2] bit 1	INT: mux CELL.LONG_IO_V[2] bit 0	INT: mux CELL.LONG_IO_V[2] bit 2	INT: mux CELL.LONG_IO_V[2] bit 3	INT: mux CELL.LONG_IO_V[3] bit 1	-	INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_IO_V[3]	INT: mux CELL.LONG_IO_V[3] bit 0	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1	INT: mux CELL.LONG_IO_V[1] bit 0	INT: mux CELL.LONG_IO_V[1] bit 1	INT: mux CELL.LONG_IO_V[1] bit 3	INT: mux CELL.DBUF_IO_V[1] bit 1	INT: mux CELL.DBUF_IO_V[1] bit 0	INT: mux CELL.DBUF_IO_V[1] bit 2	INT: mux CELL.DBUF_IO_V[1] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 4	INT: mux CELL.IMUX_HIO_T[0] bit 0	-	HIO[0]: ! READBACK_I bit 0	HIO[0]: !invert O	HIO[1]: ! READBACK_I bit 0
B7	INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5]	INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2]	INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6]	INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3]	INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3]	-	INT: mux CELL.LONG_H[4] bit 1	INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1_S1	INT: mux CELL.LONG_H[4] bit 2	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0]	INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1[0]	INT: mux CELL.LONG_H[5] bit 2	-	INT: !pass CELL.DOUBLE_IO_E0[3] ← CELL.DBUF_IO_V[0]	INT: !pass CELL.DOUBLE_IO_E0[1] ← CELL.DBUF_IO_V[0]	INT: mux CELL.LONG_H[5] bit 3	PULLUP_TBUF[1]: ! ENABLE	INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[1]	INT: mux CELL.IMUX_IO_IK[0] bit 5	INT: mux CELL.IMUX_IO_IK[0] bit 6	INT: mux CELL.IMUX_IO_IK[0] bit 1	INT: mux CELL.IMUX_IO_IK[0] bit 4	INT: mux CELL.IMUX_IO_IK[0] bit 2	INT: mux CELL.IMUX_IO_IK[0] bit 3	INT: mux CELL.IMUX_IO_IK[0] bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 7	HIO[1]: OMODE bit 0	HIO[0]: OMODE bit 0	HIO[0]: PULL bit 0	HIO[0]: PULL bit 1	INT: mux CELL.IMUX_HIO_O[0] bit 0
B6	INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4]	INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4]	INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1]	INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5]	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0]	INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[4]	INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0	INT: mux CELL.LONG_H[4] bit 0	INT: mux CELL.LONG_H[4] bit 3	INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.DOUBLE_IO_E2[3] ← CELL.DBUF_IO_V[1]	INT: mux CELL.LONG_H[5] bit 1	INT: mux CELL.LONG_H[5] bit 0	INT: !pass CELL.DOUBLE_IO_E0[0] ← CELL.DBUF_IO_V[0]	-	INT: !pass CELL.DOUBLE_IO_E0[2] ← CELL.DBUF_IO_V[0]	INT: mux CELL.IMUX_IO_OK[0] bit 6	INT: !pass CELL.DOUBLE_IO_E2[1] ← CELL.DBUF_IO_V[1]	INT: mux CELL.IMUX_IO_OK[0] bit 1	INT: mux CELL.IMUX_IO_OK[0] bit 4	DEC[1]: O4_N	INT: mux CELL.IMUX_IO_OK[0] bit 2	INT: mux CELL.IMUX_IO_OK[0] bit 3	INT: mux CELL.IMUX_IO_OK[0] bit 0	HIO[1]: PULL bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 7	DEC[1]: ! O3_P	DEC[1]: ! O1_P	HIO[1]: PULL bit 1	INT: mux CELL.IMUX_HIO_O[1] bit 0	HIO[1]: !invert O	INT: mux CELL.IMUX_HIO_T[1] bit 0	HIO[1]: !invert T
B5	INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4]	INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5]	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5]	INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1]	INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1]	INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E0[0]	INT: mux CELL.LONG_IO_V[0] bit 0	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E0[0]	INT: !bipass CELL.DOUBLE_IO_E0[0] = CELL.DOUBLE_IO_E2[0]	INT: mux CELL.LONG_IO_V[0] bit 1	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E1[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E1[0]	INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[0]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E2[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E2[0]	INT: !pass CELL.DOUBLE_IO_E2[0] ← CELL.DBUF_IO_V[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E2[2]	INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_E2[2]	DEC[1]: ! O4_P	DEC[2]: O4_P	INT: !pass CELL.SINGLE_H[4] ← CELL.DEC_V[2]	DEC[2]: ! O2_N	INT: mux CELL.IMUX_IO_OK[0] bit 5	DEC[2]: ! O3_N	DEC[1]: O3_N	DEC[1]: O1_N	DEC[2]: O1_P	HIO[1]: OSTD bit 0	HIO[1]: ISTD bit 0	HIO[1]: ! I_INV	INT: mux CELL.OUT_IO_WE_I1[0] bit 0
B4	INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E	INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5]	INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_WE_I2[1]	INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_WE_I2[1]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E	INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4]	INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3]	INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1]	INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_WE_I2[1]	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_WE_I2[0]	INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[3]	INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E	INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[0]	INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_IO_V[2]	INT: mux CELL.IMUX_IO_T[0] bit 6	INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_E0[2]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E0[2]	INT: !bipass CELL.DOUBLE_IO_E0[2] = CELL.DOUBLE_IO_E2[2]	INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_E1[2]	INT: !pass CELL.DOUBLE_IO_E2[2] ← CELL.DBUF_IO_V[1]	DEC[0]: ! O4_P	DEC[2]: ! O4_N	DEC[0]: ! O2_P	DEC[2]: O2_P	DEC[1]: O2_N	DEC[2]: O3_P	DEC[0]: O3_N	DEC[0]: ! O1_P	DEC[2]: ! O1_N	HIO[2]: OSTD bit 0	HIO[2]: ISTD bit 0	INT: mux CELL.OUT_IO_WE_I1[1] bit 0	HIO[2]: ! I_INV
B3	INT: mux CELL.IMUX_CLB_F3 bit 0	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E	INT: mux CELL.IMUX_CLB_C3 bit 1	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5]	INT: mux CELL.IMUX_CLB_G3 bit 0	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1]	INT: mux CELL.IMUX_CLB_F1 bit 3	INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1]	INT: mux CELL.IMUX_CLB_C1 bit 7	INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4]	INT: mux CELL.IMUX_CLB_G1 bit 6	TBUF[0]: ! DRIVE1	INT: mux CELL.IMUX_IO_T[0] bit 0	INT: mux CELL.IMUX_IO_T[0] bit 2	INT: mux CELL.DBUF_IO_V[0] bit 0	INT: mux CELL.DBUF_IO_V[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 7	INT: mux CELL.IMUX_IO_T[0] bit 3	-	INT: mux CELL.IMUX_IO_T[1] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 7	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E1[2]	INT: mux CELL.IMUX_IO_T[1] bit 6	TBUF[1]: ! DRIVE1	DEC[0]: O4_N	INT: mux CELL.IMUX_IO_IK[1] bit 0	DEC[0]: O2_N	HIO[2]: PULL bit 1	DEC[1]: ! O2_P	INT: mux CELL.IMUX_IO_IK[1] bit 5	DEC[0]: ! O3_P	DEC[0]: O1_N	HIO[2]: ! READBACK_I bit 0	HIO[3]: ! READBACK_I bit 0	HIO[2]: !invert O	INT: mux CELL.IMUX_HIO_T[2] bit 0	HIO[2]: !invert T
B2	INT: mux CELL.IMUX_CLB_F3 bit 2	INT: mux CELL.IMUX_CLB_F3 bit 6	INT: mux CELL.IMUX_CLB_F3 bit 8	INT: mux CELL.IMUX_CLB_C3 bit 2	INT: mux CELL.IMUX_CLB_C3 bit 3	INT: mux CELL.IMUX_CLB_G3 bit 1	INT: mux CELL.IMUX_CLB_G3 bit 4	INT: mux CELL.IMUX_CLB_G3 bit 7	INT: mux CELL.IMUX_CLB_F1 bit 0	INT: mux CELL.IMUX_CLB_F1 bit 7	INT: mux CELL.IMUX_CLB_C1 bit 2	INT: mux CELL.IMUX_CLB_C1 bit 1	INT: mux CELL.IMUX_CLB_C1 bit 6	-	INT: mux CELL.IMUX_CLB_G1 bit 0	INT: mux CELL.IMUX_IO_T[1] bit 2	INT: mux CELL.DBUF_IO_V[0] bit 2	INT: mux CELL.IMUX_IO_T[1] bit 4	INT: mux CELL.DBUF_IO_V[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 4	INT: mux CELL.IMUX_IO_T[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 5	INT: mux CELL.IMUX_IO_T[1] bit 5	-	INT: mux CELL.IMUX_IO_T[1] bit 1	INT: mux CELL.IMUX_IO_T[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 1	INT: mux CELL.IMUX_IO_OK[1] bit 2	INT: mux CELL.IMUX_IO_OK[1] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_OK[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 5	INT: mux CELL.IMUX_IO_OK[1] bit 6	INT: mux CELL.IMUX_IO_OK[1] bit 3	INT: mux CELL.IMUX_IO_OK[1] bit 7	INT: mux CELL.IMUX_HIO_O[2] bit 0	HIO[2]: PULL bit 0	-	HIO[2]: OMODE bit 0	HIO[3]: OMODE bit 0
B1	INT: mux CELL.IMUX_CLB_F3 bit 5	INT: mux CELL.IMUX_CLB_F3 bit 3	INT: mux CELL.IMUX_CLB_C3 bit 0	INT: mux CELL.IMUX_CLB_C3 bit 5	INT: mux CELL.IMUX_CLB_C3 bit 6	INT: mux CELL.IMUX_CLB_G3 bit 6	INT: mux CELL.IMUX_CLB_G3 bit 2	INT: mux CELL.IMUX_CLB_G3 bit 5	INT: mux CELL.IMUX_CLB_F1 bit 5	INT: mux CELL.IMUX_CLB_F1 bit 2	INT: mux CELL.IMUX_CLB_C1 bit 5	INT: mux CELL.IMUX_CLB_C1 bit 3	INT: mux CELL.IMUX_CLB_G1 bit 4	INT: mux CELL.IMUX_CLB_G1 bit 3	INT: mux CELL.IMUX_CLB_G1 bit 2	INT: mux CELL.LONG_H[0] bit 1	INT: mux CELL.LONG_H[0] bit 3	INT: mux CELL.IMUX_TBUF_I[0] bit 5	INT: mux CELL.IMUX_TBUF_I[0] bit 0	INT: mux CELL.IMUX_TBUF_I[0] bit 2	INT: mux CELL.IMUX_TBUF_T[0] bit 2	INT: mux CELL.IMUX_TBUF_T[0] bit 1	INT: mux CELL.IMUX_TBUF_T[1] bit 2	INT: mux CELL.IMUX_TBUF_T[1] bit 4	INT: mux CELL.IMUX_TBUF_T[1] bit 0	INT: mux CELL.IMUX_TBUF_T[1] bit 3	INT: mux CELL.IMUX_TBUF_I[1] bit 4	INT: mux CELL.IMUX_TBUF_I[1] bit 0	INT: mux CELL.IMUX_TBUF_I[1] bit 5	INT: mux CELL.LONG_H[1] bit 0	INT: mux CELL.LONG_H[1] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 6	INT: mux CELL.IMUX_IO_IK[1] bit 3	INT: mux CELL.IMUX_IO_IK[1] bit 7	INT: mux CELL.IMUX_HIO_T[3] bit 0	HIO[3]: !invert O	INT: mux CELL.IMUX_HIO_O[3] bit 0	HIO[3]: PULL bit 0	HIO[3]: PULL bit 1
B0	INT: mux CELL.IMUX_CLB_F3 bit 7	INT: mux CELL.IMUX_CLB_F3 bit 1	INT: mux CELL.IMUX_CLB_F3 bit 4	INT: mux CELL.IMUX_CLB_C3 bit 4	INT: mux CELL.IMUX_CLB_C3 bit 7	INT: mux CELL.IMUX_CLB_G3 bit 3	INT: mux CELL.IMUX_CLB_G3 bit 8	INT: mux CELL.IMUX_CLB_F1 bit 6	INT: mux CELL.IMUX_CLB_F1 bit 1	INT: mux CELL.IMUX_CLB_F1 bit 4	INT: mux CELL.IMUX_CLB_C1 bit 0	INT: mux CELL.IMUX_CLB_C1 bit 4	INT: mux CELL.IMUX_CLB_G1 bit 5	INT: mux CELL.IMUX_CLB_G1 bit 1	INT: mux CELL.IMUX_CLB_G1 bit 7	INT: mux CELL.LONG_H[0] bit 0	INT: mux CELL.LONG_H[0] bit 2	INT: mux CELL.IMUX_TBUF_I[0] bit 3	INT: mux CELL.IMUX_TBUF_I[0] bit 1	INT: mux CELL.IMUX_TBUF_I[0] bit 4	INT: mux CELL.IMUX_TBUF_T[0] bit 3	INT: mux CELL.IMUX_TBUF_T[0] bit 4	INT: mux CELL.IMUX_TBUF_T[0] bit 0	INT: mux CELL.IMUX_TBUF_T[0] bit 5	INT: mux CELL.IMUX_TBUF_T[1] bit 1	INT: mux CELL.IMUX_TBUF_T[1] bit 5	INT: mux CELL.IMUX_TBUF_I[1] bit 2	INT: mux CELL.IMUX_TBUF_I[1] bit 1	INT: mux CELL.IMUX_TBUF_I[1] bit 3	INT: mux CELL.LONG_H[1] bit 1	INT: mux CELL.LONG_H[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 0	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.IMUX_IO_O1[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 5	INT: mux CELL.IMUX_IO_O1[1] bit 4	HIO[3]: !invert T	INT: mux CELL.OUT_IO_WE_I2[1] bit 0	HIO[3]: ! I_INV	HIO[3]: ISTD bit 0	HIO[3]: OSTD bit 0

xc4000h IO_E0 rect MAIN_S
Bit	Frame
Bit	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	-	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1]	-	-	-	INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2]	-	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0]	-	INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PULLUP_TBUF[0]: ! ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

xc4000h IO_E0 rect MAIN_W
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile IO_E0_N

Cells: 3

Switchbox INT

xc4000h IO_E0_N switchbox INT programmable buffers
Destination	Source	Bit
CELL.LONG_H[0]	CELL.SINGLE_V[1]	!MAIN_S[26][8]
CELL.LONG_H[1]	CELL.SINGLE_V[2]	!MAIN_S[30][8]
CELL.LONG_H[2]	CELL.SINGLE_V[3]	!MAIN[27][4]
CELL.LONG_H[3]	CELL.SINGLE_V[4]	!MAIN[27][6]
CELL.LONG_H[4]	CELL.SINGLE_V[5]	!MAIN[38][4]
CELL.LONG_H[5]	CELL.SINGLE_V[6]	!MAIN[40][6]
CELL.LONG_V[0]	CELL.SINGLE_H_E[1]	!MAIN[32][4]
CELL.LONG_V[1]	CELL.SINGLE_H_E[2]	!MAIN[38][8]
CELL.LONG_V[2]	CELL.SINGLE_H_E[3]	!MAIN[34][6]
CELL.LONG_V[3]	CELL.SINGLE_H[4]	!MAIN[34][4]
CELL.LONG_V[4]	CELL.SINGLE_H[5]	!MAIN[31][6]
CELL.LONG_V[5]	CELL.SINGLE_H[6]	!MAIN[35][8]

xc4000h IO_E0_N switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[0]	CELL.DEC_V[0]	!MAIN[18][5]
CELL.SINGLE_H[0]	CELL.OUT_IO_WE_I2_S1	!MAIN[24][4]
CELL.SINGLE_H[1]	CELL.LONG_IO_V[0]	!MAIN[22][4]
CELL.SINGLE_H[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[21][4]
CELL.SINGLE_H[2]	CELL.LONG_IO_V[1]	!MAIN[13][7]
CELL.SINGLE_H[2]	CELL.OUT_IO_WE_I1[0]	!MAIN[21][7]
CELL.SINGLE_H[3]	CELL.DEC_V[1]	!MAIN[9][9]
CELL.SINGLE_H[3]	CELL.OUT_IO_WE_I1_S1	!MAIN[15][8]
CELL.SINGLE_H[4]	CELL.LONG_V[3]	!MAIN[33][4]
CELL.SINGLE_H[4]	CELL.DEC_V[2]	!MAIN[10][5]
CELL.SINGLE_H[4]	CELL.OUT_IO_WE_I2_S1	!MAIN[25][4]
CELL.SINGLE_H[5]	CELL.LONG_V[4]	!MAIN[27][3]
CELL.SINGLE_H[5]	CELL.LONG_IO_V[2]	!MAIN[19][4]
CELL.SINGLE_H[5]	CELL.OUT_IO_WE_I2[0]	!MAIN[20][4]
CELL.SINGLE_H[6]	CELL.LONG_V[5]	!MAIN[34][9]
CELL.SINGLE_H[6]	CELL.LONG_IO_V[3]	!MAIN[17][8]
CELL.SINGLE_H[6]	CELL.OUT_IO_WE_I1[0]	!MAIN[24][8]
CELL.SINGLE_H[7]	CELL.DEC_V[3]	!MAIN[17][9]
CELL.SINGLE_H[7]	CELL.OUT_IO_WE_I1_S1	!MAIN[25][8]
CELL.SINGLE_H_E[1]	CELL.LONG_V[0]	!MAIN[32][5]
CELL.SINGLE_H_E[2]	CELL.LONG_V[1]	!MAIN[40][9]
CELL.SINGLE_H_E[3]	CELL.LONG_V[2]	!MAIN[39][7]
CELL.SINGLE_V[0]	CELL.TIE_0	!MAIN[26][6]
CELL.SINGLE_V[0]	CELL.OUT_IO_WE_I2[0]	!MAIN[28][4]
CELL.SINGLE_V[1]	CELL.LONG_H[0]	!MAIN_S[28][8]
CELL.SINGLE_V[1]	CELL.OUT_IO_WE_I2[1]	!MAIN[29][4]
CELL.SINGLE_V[2]	CELL.LONG_H[1]	!MAIN_S[34][8]
CELL.SINGLE_V[2]	CELL.OUT_CLB_Y_E	!MAIN[30][4]
CELL.SINGLE_V[3]	CELL.LONG_H[2]	!MAIN_S[33][9]
CELL.SINGLE_V[3]	CELL.OUT_CLB_YQ_E	!MAIN[35][4]
CELL.SINGLE_V[4]	CELL.LONG_H[3]	!MAIN[26][7]
CELL.SINGLE_V[4]	CELL.OUT_IO_WE_I2[0]	!MAIN[39][3]
CELL.SINGLE_V[5]	CELL.LONG_H[4]	!MAIN[40][5]
CELL.SINGLE_V[5]	CELL.OUT_IO_WE_I2[1]	!MAIN[36][4]
CELL.SINGLE_V[6]	CELL.LONG_H[5]	!MAIN[40][7]
CELL.SINGLE_V[6]	CELL.OUT_CLB_Y_E	!MAIN[39][4]
CELL.SINGLE_V[7]	CELL.TIE_0	!MAIN[26][9]
CELL.SINGLE_V[7]	CELL.OUT_CLB_YQ_E	!MAIN[38][3]
CELL.DOUBLE_H0[0]	CELL.OUT_IO_WE_I1[0]	!MAIN[20][7]
CELL.DOUBLE_H0[1]	CELL.OUT_IO_WE_I2_S1	!MAIN[23][4]
CELL.DOUBLE_H1[0]	CELL.OUT_IO_WE_I1_S1	!MAIN[23][7]
CELL.DOUBLE_H1[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[23][6]
CELL.DOUBLE_V0[0]	CELL.OUT_CLB_YQ_E	!MAIN[26][4]
CELL.DOUBLE_V0[1]	CELL.OUT_IO_WE_I2[1]	!MAIN[37][4]
CELL.DOUBLE_V1[0]	CELL.OUT_CLB_Y_E	!MAIN[31][4]
CELL.DOUBLE_V1[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[40][4]
CELL.DOUBLE_IO_E0[0]	CELL.DBUF_IO_V[0]	!MAIN[19][6]
CELL.DOUBLE_IO_E0[1]	CELL.DBUF_IO_V[0]	!MAIN[16][7]
CELL.DOUBLE_IO_E0[2]	CELL.DBUF_IO_V[0]	!MAIN[17][6]
CELL.DOUBLE_IO_E0[3]	CELL.DBUF_IO_V[0]	!MAIN[17][7]
CELL.DOUBLE_IO_E2[0]	CELL.DBUF_IO_V[1]	!MAIN[15][5]
CELL.DOUBLE_IO_E2[1]	CELL.DBUF_IO_V[1]	!MAIN[15][6]
CELL.DOUBLE_IO_E2[2]	CELL.DBUF_IO_V[1]	!MAIN[13][4]
CELL.DOUBLE_IO_E2[3]	CELL.DBUF_IO_V[1]	!MAIN[22][6]

xc4000h IO_E0_N switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.SINGLE_H_E[0]	!MAIN[28][6]
CELL.SINGLE_H[0]	CELL.SINGLE_V[0]	!MAIN[27][5]
CELL.SINGLE_H[0]	CELL.SINGLE_V_S[0]	!MAIN[30][3]
CELL.SINGLE_H[0]	CELL.DOUBLE_IO_E0[0]	!MAIN[25][5]
CELL.SINGLE_H[0]	CELL.DOUBLE_IO_E2[0]	!MAIN[16][5]
CELL.SINGLE_H[1]	CELL.SINGLE_H_E[1]	!MAIN[30][5]
CELL.SINGLE_H[1]	CELL.SINGLE_V[1]	!MAIN[29][5]
CELL.SINGLE_H[1]	CELL.SINGLE_V_S[1]	!MAIN[29][3]
CELL.SINGLE_H[1]	CELL.DOUBLE_IO_E1[0]	!MAIN[19][5]
CELL.SINGLE_H[2]	CELL.SINGLE_H_E[2]	!MAIN[32][8]
CELL.SINGLE_H[2]	CELL.SINGLE_V[2]	!MAIN[31][8]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[2]	!MAIN[33][8]
CELL.SINGLE_H[2]	CELL.DOUBLE_IO_E0[1]	!MAIN[16][9]
CELL.SINGLE_H[2]	CELL.DOUBLE_IO_E2[1]	!MAIN[10][9]
CELL.SINGLE_H[3]	CELL.SINGLE_H_E[3]	!MAIN[31][7]
CELL.SINGLE_H[3]	CELL.SINGLE_V[3]	!MAIN[28][7]
CELL.SINGLE_H[3]	CELL.SINGLE_V_S[3]	!MAIN[30][7]
CELL.SINGLE_H[3]	CELL.DOUBLE_IO_E1[1]	!MAIN[12][9]
CELL.SINGLE_H[4]	CELL.SINGLE_H_E[4]	!MAIN[36][6]
CELL.SINGLE_H[4]	CELL.SINGLE_V[4]	!MAIN[39][6]
CELL.SINGLE_H[4]	CELL.SINGLE_V_S[4]	!MAIN[35][6]
CELL.SINGLE_H[4]	CELL.DOUBLE_IO_E0[2]	!MAIN[17][4]
CELL.SINGLE_H[4]	CELL.DOUBLE_IO_E2[2]	!MAIN[13][5]
CELL.SINGLE_H[5]	CELL.SINGLE_H_E[5]	!MAIN[35][5]
CELL.SINGLE_H[5]	CELL.SINGLE_V[5]	!MAIN[36][3]
CELL.SINGLE_H[5]	CELL.SINGLE_V_S[5]	!MAIN[37][5]
CELL.SINGLE_H[5]	CELL.DOUBLE_IO_E1[2]	!MAIN[14][4]
CELL.SINGLE_H[6]	CELL.SINGLE_H_E[6]	!MAIN[35][7]
CELL.SINGLE_H[6]	CELL.SINGLE_V[6]	!MAIN[36][8]
CELL.SINGLE_H[6]	CELL.SINGLE_V_S[6]	!MAIN[36][7]
CELL.SINGLE_H[6]	CELL.DOUBLE_IO_E0[3]	!MAIN[25][9]
CELL.SINGLE_H[6]	CELL.DOUBLE_IO_E2[3]	!MAIN[19][9]
CELL.SINGLE_H[7]	CELL.SINGLE_H_E[7]	!MAIN[38][9]
CELL.SINGLE_H[7]	CELL.SINGLE_V[7]	!MAIN[35][9]
CELL.SINGLE_H[7]	CELL.SINGLE_V_S[7]	!MAIN[37][8]
CELL.SINGLE_H[7]	CELL.DOUBLE_IO_E1[3]	!MAIN[21][9]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V[0]	!MAIN[26][5]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V_S[0]	!MAIN[28][5]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V[1]	!MAIN[30][6]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V_S[1]	!MAIN[31][5]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V[2]	!MAIN[31][9]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V_S[2]	!MAIN[32][9]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V[3]	!MAIN[32][7]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V_S[3]	!MAIN[33][7]
CELL.SINGLE_H_E[4]	CELL.SINGLE_V[4]	!MAIN[39][8]
CELL.SINGLE_H_E[4]	CELL.SINGLE_V_S[4]	!MAIN[37][6]
CELL.SINGLE_H_E[5]	CELL.SINGLE_V[5]	!MAIN[36][5]
CELL.SINGLE_H_E[5]	CELL.SINGLE_V_S[5]	!MAIN[38][5]
CELL.SINGLE_H_E[6]	CELL.SINGLE_V[6]	!MAIN[34][7]
CELL.SINGLE_H_E[6]	CELL.SINGLE_V_S[6]	!MAIN[37][7]
CELL.SINGLE_H_E[7]	CELL.SINGLE_V[7]	!MAIN[37][9]
CELL.SINGLE_H_E[7]	CELL.SINGLE_V_S[7]	!MAIN[39][9]
CELL.SINGLE_V[0]	CELL.SINGLE_V_S[0]	!MAIN[29][6]
CELL.SINGLE_V[1]	CELL.SINGLE_V_S[1]	!MAIN[31][3]
CELL.SINGLE_V[2]	CELL.SINGLE_V_S[2]	!MAIN[30][9]
CELL.SINGLE_V[3]	CELL.SINGLE_V_S[3]	!MAIN[27][7]
CELL.SINGLE_V[4]	CELL.SINGLE_V_S[4]	!MAIN[38][6]
CELL.SINGLE_V[5]	CELL.SINGLE_V_S[5]	!MAIN[39][5]
CELL.SINGLE_V[6]	CELL.SINGLE_V_S[6]	!MAIN[38][7]
CELL.SINGLE_V[7]	CELL.SINGLE_V_S[7]	!MAIN[36][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_H2[0]	!MAIN[29][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_V0[0]	!MAIN[27][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_V2[0]	!MAIN[28][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_E0[1]	!MAIN[15][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_E1[1]	!MAIN[13][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_E2[1]	!MAIN[11][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_H2[1]	!MAIN[33][6]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_V0[1]	!MAIN[32][6]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_V2[1]	!MAIN[33][3]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_E0[2]	!MAIN[16][4]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_E1[2]	!MAIN[15][3]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_E2[2]	!MAIN[14][5]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_E0[0]	!MAIN[23][5]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_E1[0]	!MAIN[20][5]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_E2[0]	!MAIN[17][5]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_E0[3]	!MAIN[24][9]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_E1[3]	!MAIN[22][9]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_E2[3]	!MAIN[20][9]
CELL.DOUBLE_H2[0]	CELL.DOUBLE_V0[0]	!MAIN[29][7]
CELL.DOUBLE_H2[0]	CELL.DOUBLE_V2[0]	!MAIN[29][8]
CELL.DOUBLE_H2[1]	CELL.DOUBLE_V0[1]	!MAIN[33][5]
CELL.DOUBLE_H2[1]	CELL.DOUBLE_V2[1]	!MAIN[34][5]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_V2[0]	!MAIN[27][8]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_V2[1]	!MAIN[34][3]
CELL.DOUBLE_IO_E0[0]	CELL.DOUBLE_IO_E2[0]	!MAIN[22][5]
CELL.DOUBLE_IO_E0[1]	CELL.DOUBLE_IO_E2[1]	!MAIN[14][9]
CELL.DOUBLE_IO_E0[2]	CELL.DOUBLE_IO_E2[2]	!MAIN[15][4]
CELL.DOUBLE_IO_E0[3]	CELL.DOUBLE_IO_E2[3]	!MAIN[23][9]

xc4000h IO_E0_N switchbox INT muxes DBUF_IO_V[0]
Bits				Destination
MAIN[21][3]	MAIN[24][2]	MAIN[22][2]	MAIN[22][3]	CELL.DBUF_IO_V[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_E2[0]
0	1	0	1	CELL.DOUBLE_IO_E2[1]
0	1	1	0	CELL.DOUBLE_IO_E2[3]
1	1	1	1	CELL.DOUBLE_IO_E2[2]

xc4000h IO_E0_N switchbox INT muxes DBUF_IO_V[1]
Bits				Destination
MAIN[8][8]	MAIN[9][8]	MAIN[11][8]	MAIN[10][8]	CELL.DBUF_IO_V[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_E0[1]
0	1	0	1	CELL.DOUBLE_IO_E0[2]
0	1	1	0	CELL.DOUBLE_IO_E0[3]
1	1	1	1	CELL.DOUBLE_IO_E0[0]

xc4000h IO_E0_N switchbox INT muxes LONG_H[0]
Bits				Destination
MAIN[24][1]	MAIN[24][0]	MAIN[25][1]	MAIN[25][0]	CELL.LONG_H[0]
				Source
0	0	0	1	CELL.LONG_IO_V[0]
0	0	1	0	CELL.DEC_V[3]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000h IO_E0_N switchbox INT muxes LONG_H[1]
Bits				Destination
MAIN[10][1]	MAIN[10][0]	MAIN[11][0]	MAIN[11][1]	CELL.LONG_H[1]
				Source
0	0	0	1	CELL.LONG_IO_V[1]
0	0	1	0	CELL.DEC_V[2]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000h IO_E0_N switchbox INT muxes LONG_H[4]
Bits				Destination
MAIN[24][6]	MAIN[22][7]	MAIN[24][7]	MAIN[25][6]	CELL.LONG_H[4]
				Source
0	0	0	1	CELL.LONG_IO_V[2]
0	0	1	0	CELL.DEC_V[1]
0	1	1	1	CELL.OUT_IO_WE_I2[0]
1	1	1	1	off

xc4000h IO_E0_N switchbox INT muxes LONG_H[5]
Bits				Destination
MAIN[15][7]	MAIN[19][7]	MAIN[21][6]	MAIN[20][6]	CELL.LONG_H[5]
				Source
0	0	0	1	CELL.LONG_IO_V[3]
0	0	1	0	CELL.DEC_V[0]
0	1	1	1	CELL.OUT_IO_WE_I2[0]
1	1	1	1	off

xc4000h IO_E0_N switchbox INT muxes LONG_IO_V[0]
Bits		Destination
MAIN[21][5]	MAIN[24][5]	CELL.LONG_IO_V[0]
		Source
0	0	CELL.LONG_H[0]
0	1	CELL.SINGLE_H[1]
1	1	off

xc4000h IO_E0_N switchbox INT muxes LONG_IO_V[1]
Bits				Destination
MAIN[12][8]	MAIN[8][9]	MAIN[13][8]	MAIN[14][8]	CELL.LONG_IO_V[1]
				Source
0	0	0	1	CELL.LONG_H[1]
0	0	1	0	CELL.LONG_H[3]
0	1	1	1	CELL.SINGLE_H[2]
1	1	1	1	off

xc4000h IO_E0_N switchbox INT muxes LONG_IO_V[2]
Bits				Destination
MAIN[20][8]	MAIN[21][8]	MAIN[23][8]	MAIN[22][8]	CELL.LONG_IO_V[2]
				Source
0	0	0	1	CELL.LONG_H[2]
0	0	1	0	CELL.LONG_H[4]
0	1	1	1	CELL.SINGLE_H[5]
1	1	1	1	off

xc4000h IO_E0_N switchbox INT muxes LONG_IO_V[3]
Bits		Destination
MAIN[19][8]	MAIN[16][8]	CELL.LONG_IO_V[3]
		Source
0	0	CELL.LONG_H[5]
0	1	CELL.SINGLE_H[6]
1	1	off

xc4000h IO_E0_N switchbox INT muxes IMUX_CLB_F1
Bits								Destination
MAIN[31][2]	MAIN[33][0]	MAIN[32][1]	MAIN[31][0]	MAIN[32][3]	MAIN[31][1]	MAIN[32][0]	MAIN[32][2]	CELL.IMUX_CLB_F1
								Source
0	0	1	0	0	1	1	1	CELL.SINGLE_V[3]
0	0	1	0	1	0	1	1	CELL.LONG_V[4]
0	0	1	0	1	1	1	0	CELL.SINGLE_V[7]
0	0	1	1	1	1	1	1	CELL.SINGLE_V[0]
0	1	0	0	0	1	1	1	CELL.LONG_V[3]
0	1	0	0	1	0	1	1	CELL.DOUBLE_V0[1]
0	1	0	0	1	1	1	0	CELL.LONG_V[0]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[1]
0	1	1	0	0	1	0	1	CELL.SINGLE_V[5]
0	1	1	0	1	0	0	1	CELL.LONG_V[1]
0	1	1	0	1	1	0	0	CELL.SINGLE_V[6]
0	1	1	1	1	1	0	1	CELL.DOUBLE_V1[1]
1	1	1	0	0	1	1	1	CELL.DOUBLE_V1[0]
1	1	1	0	1	0	1	1	CELL.SINGLE_V[4]
1	1	1	0	1	1	1	0	CELL.DOUBLE_V0[0]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[2]

xc4000h IO_E0_N switchbox INT muxes IMUX_CLB_F3
Bits									Destination
MAIN[38][2]	MAIN[40][0]	MAIN[39][2]	MAIN[40][1]	MAIN[38][0]	MAIN[39][1]	MAIN[40][2]	MAIN[39][0]	MAIN[40][3]	CELL.IMUX_CLB_F3
									Source
0	0	0	0	1	1	1	1	1	CELL.SINGLE_V[0]
0	0	0	1	1	1	0	1	1	CELL.DOUBLE_V0[0]
0	0	0	1	1	1	1	0	1	CELL.LONG_V[2]
0	0	1	1	1	1	1	1	1	CELL.SINGLE_V[3]
0	1	0	0	0	1	1	1	1	CELL.DOUBLE_V1[1]
0	1	0	0	1	0	1	1	1	CELL.LONG_V[1]
0	1	0	1	0	1	0	1	1	CELL.DOUBLE_V0[1]
0	1	0	1	0	1	1	0	1	CELL.LONG_V[5]
0	1	0	1	1	0	0	1	1	CELL.SINGLE_V[4]
0	1	0	1	1	0	1	0	1	CELL.LONG_V[4]
0	1	0	1	1	1	1	1	0	CELL.GCLK[0]
0	1	1	1	0	1	1	1	1	CELL.SINGLE_V[1]
0	1	1	1	1	0	1	1	1	CELL.SINGLE_V[2]
1	1	0	0	1	1	1	1	1	CELL.SINGLE_V[6]
1	1	0	1	1	1	0	1	1	CELL.DOUBLE_V1[0]
1	1	0	1	1	1	1	0	1	CELL.SINGLE_V[5]
1	1	1	1	1	1	1	1	1	CELL.SINGLE_V[7]

xc4000h IO_E0_N switchbox INT muxes IMUX_CLB_G1
Bits								Destination
MAIN[26][0]	MAIN[26][3]	MAIN[28][0]	MAIN[28][1]	MAIN[27][1]	MAIN[26][1]	MAIN[27][0]	MAIN[26][2]	CELL.IMUX_CLB_G1
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_V[0]
0	0	0	1	0	1	1	1	CELL.SINGLE_V[2]
0	0	0	1	1	1	0	1	CELL.SINGLE_V[4]
0	0	1	0	1	0	1	1	CELL.LONG_V[4]
0	0	1	0	1	1	1	0	CELL.LONG_V[3]
0	0	1	1	0	0	1	1	CELL.SINGLE_V[1]
0	0	1	1	0	1	1	0	CELL.DOUBLE_V1[0]
0	0	1	1	1	0	0	1	CELL.DOUBLE_V0[1]
0	0	1	1	1	1	0	0	CELL.LONG_V[0]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[3]
0	1	1	1	0	1	1	1	CELL.DOUBLE_V0[0]
0	1	1	1	1	1	0	1	CELL.SINGLE_V[7]
1	0	0	1	1	1	1	1	CELL.DOUBLE_V1[1]
1	0	1	1	1	0	1	1	CELL.LONG_V[1]
1	0	1	1	1	1	1	0	CELL.SINGLE_V[5]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[6]

xc4000h IO_E0_N switchbox INT muxes IMUX_CLB_G3
Bits									Destination
MAIN[34][0]	MAIN[33][2]	MAIN[35][1]	MAIN[33][1]	MAIN[34][2]	MAIN[35][0]	MAIN[34][1]	MAIN[35][2]	MAIN[35][3]	CELL.IMUX_CLB_G3
									Source
0	0	0	1	1	1	1	1	1	CELL.SPECIAL_CLB_CIN
0	0	1	0	0	1	1	1	1	CELL.SINGLE_V[0]
0	0	1	0	1	0	1	1	1	CELL.SINGLE_V[2]
0	0	1	0	1	1	1	0	1	CELL.SINGLE_V[4]
0	0	1	1	0	1	0	1	1	CELL.LONG_V[4]
0	0	1	1	0	1	1	1	0	CELL.LONG_V[2]
0	0	1	1	1	0	0	1	1	CELL.SINGLE_V[1]
0	0	1	1	1	0	1	1	0	CELL.SINGLE_V[6]
0	0	1	1	1	1	0	0	1	CELL.DOUBLE_V0[1]
0	0	1	1	1	1	1	0	0	CELL.LONG_V[5]
0	1	1	1	0	1	1	1	1	CELL.DOUBLE_V0[0]
0	1	1	1	1	0	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	1	1	1	0	1	CELL.DOUBLE_V1[0]
1	0	1	0	1	1	1	1	1	CELL.DOUBLE_V1[1]
1	0	1	1	1	1	0	1	1	CELL.LONG_V[1]
1	0	1	1	1	1	1	1	0	CELL.SINGLE_V[7]
1	1	1	1	1	1	1	1	1	CELL.SINGLE_V[3]

xc4000h IO_E0_N switchbox INT muxes IMUX_CLB_C1
Bits								Destination
MAIN[28][3]	MAIN[28][2]	MAIN[30][1]	MAIN[29][0]	MAIN[29][1]	MAIN[30][2]	MAIN[29][2]	MAIN[30][0]	CELL.IMUX_CLB_C1
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_V[0]
0	0	0	1	0	1	1	1	CELL.SINGLE_V[1]
0	0	1	0	1	0	1	1	CELL.DOUBLE_V0[0]
0	0	1	0	1	1	0	1	CELL.DOUBLE_V1[0]
0	0	1	1	0	0	1	1	CELL.SINGLE_V[3]
0	0	1	1	0	1	0	1	CELL.SINGLE_V[7]
0	0	1	1	1	0	1	0	CELL.LONG_V[2]
0	0	1	1	1	1	0	0	CELL.LONG_V[3]
0	1	1	0	1	1	1	1	CELL.DOUBLE_V1[1]
0	1	1	1	0	1	1	1	CELL.SINGLE_V[2]
1	0	0	1	1	1	1	1	CELL.DOUBLE_V0[1]
1	0	1	1	1	0	1	1	CELL.SINGLE_V[5]
1	0	1	1	1	1	0	1	CELL.SINGLE_V[6]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[4]

xc4000h IO_E0_N switchbox INT muxes IMUX_CLB_C3
Bits								Destination
MAIN[36][0]	MAIN[36][1]	MAIN[37][1]	MAIN[37][0]	MAIN[36][2]	MAIN[37][2]	MAIN[37][3]	MAIN[38][1]	CELL.IMUX_CLB_C3
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_V[0]
0	0	0	1	0	1	1	1	CELL.SINGLE_V[2]
0	0	0	1	1	1	1	0	CELL.GCLK[2]
0	0	1	0	1	0	1	1	CELL.SINGLE_V[3]
0	0	1	0	1	1	0	1	CELL.SINGLE_V[7]
0	0	1	1	0	0	1	1	CELL.DOUBLE_V0[0]
0	0	1	1	0	1	0	1	CELL.DOUBLE_V1[0]
0	0	1	1	1	0	1	0	CELL.LONG_V[3]
0	0	1	1	1	1	0	0	CELL.LONG_V[2]
0	1	1	0	1	1	1	1	CELL.DOUBLE_V1[1]
0	1	1	1	0	1	1	1	CELL.SINGLE_V[1]
1	0	0	1	1	1	1	1	CELL.DOUBLE_V0[1]
1	0	1	1	1	0	1	1	CELL.SINGLE_V[5]
1	0	1	1	1	1	0	1	CELL.SINGLE_V[6]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[4]

xc4000h IO_E0_N switchbox INT muxes IMUX_TBUF_I[0]
Bits						Destination
MAIN[23][1]	MAIN[21][0]	MAIN[23][0]	MAIN[21][1]	MAIN[22][0]	MAIN[22][1]	CELL.IMUX_TBUF_I[0]
						Source
0	0	0	1	1	1	CELL.DOUBLE_IO_E2[2]
0	0	1	0	1	1	CELL.OUT_IO_WE_I2[0]
0	0	1	1	0	1	CELL.LONG_IO_V[2]
0	0	1	1	1	0	CELL.DEC_V[1]
0	1	1	1	1	1	CELL.DOUBLE_IO_E1[2]
1	0	0	1	1	1	CELL.DOUBLE_IO_E1[3]
1	0	1	0	1	1	CELL.DOUBLE_IO_E2[3]
1	0	1	1	0	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_E0_N switchbox INT muxes IMUX_TBUF_I[1]
Bits						Destination
MAIN[12][1]	MAIN[14][1]	MAIN[12][0]	MAIN[14][0]	MAIN[13][0]	MAIN[13][1]	CELL.IMUX_TBUF_I[1]
						Source
0	0	0	1	1	1	CELL.DOUBLE_IO_E1[2]
0	0	1	1	1	1	CELL.DOUBLE_IO_E1[3]
0	1	0	0	1	1	CELL.OUT_IO_WE_I2[0]
0	1	0	1	0	1	CELL.LONG_IO_V[1]
0	1	0	1	1	0	CELL.DEC_V[2]
0	1	1	0	1	1	CELL.DOUBLE_IO_E2[3]
0	1	1	1	1	0	CELL.OUT_IO_WE_I2[1]
1	1	0	1	1	1	CELL.DOUBLE_IO_E2[2]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_E0_N switchbox INT muxes IMUX_TBUF_T[0]
Bits						Destination
MAIN[17][0]	MAIN[19][0]	MAIN[20][0]	MAIN[20][1]	MAIN[19][1]	MAIN[18][0]	CELL.IMUX_TBUF_T[0]
						Source
0	0	0	1	1	1	CELL.TIE_1
0	0	1	1	1	1	CELL.TIE_0
0	1	0	0	1	1	CELL.DOUBLE_IO_E2[0]
0	1	0	1	0	1	CELL.LONG_IO_V[3]
0	1	0	1	1	0	CELL.DEC_V[3]
0	1	1	0	1	1	CELL.DOUBLE_IO_E1[0]
0	1	1	1	0	1	CELL.LONG_IO_V[2]
0	1	1	1	1	0	CELL.DEC_V[0]
1	1	0	1	1	1	CELL.DOUBLE_IO_E2[1]
1	1	1	1	1	1	CELL.DOUBLE_IO_E1[1]

xc4000h IO_E0_N switchbox INT muxes IMUX_TBUF_T[1]
Bits						Destination
MAIN[15][0]	MAIN[17][1]	MAIN[15][1]	MAIN[18][1]	MAIN[16][0]	MAIN[16][1]	CELL.IMUX_TBUF_T[1]
						Source
0	0	0	1	1	1	CELL.TIE_1
0	0	1	1	1	1	CELL.TIE_0
0	1	0	0	1	1	CELL.DOUBLE_IO_E1[1]
0	1	0	1	0	1	CELL.LONG_IO_V[2]
0	1	0	1	1	0	CELL.DEC_V[0]
0	1	1	0	1	1	CELL.DOUBLE_IO_E2[1]
0	1	1	1	0	1	CELL.LONG_IO_V[3]
0	1	1	1	1	0	CELL.DEC_V[3]
1	1	0	1	1	1	CELL.DOUBLE_IO_E1[0]
1	1	1	1	1	1	CELL.DOUBLE_IO_E2[0]

xc4000h IO_E0_N switchbox INT muxes IMUX_IO_O1[0]
Bits						Destination
MAIN[5][9]	MAIN[5][8]	MAIN[7][8]	MAIN[7][9]	MAIN[6][9]	MAIN[6][8]	CELL.IMUX_IO_O1[0]
						Source
0	0	0	1	1	1	CELL.DEC_V[3]
0	0	1	0	1	1	CELL.DEC_V[2]
0	0	1	1	0	1	CELL.DEC_V[1]
0	0	1	1	1	0	CELL.DEC_V[0]
0	1	1	1	1	1	CELL.DOUBLE_H0[1]
1	0	0	1	1	1	CELL.DOUBLE_H1[0]
1	0	1	0	1	1	CELL.LONG_H[3]
1	0	1	1	0	1	CELL.LONG_H[4]
1	0	1	1	1	0	CELL.LONG_H[5]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_E0_N switchbox INT muxes IMUX_IO_O1[1]
Bits						Destination
MAIN[6][0]	MAIN[5][0]	MAIN[9][1]	MAIN[7][0]	MAIN[8][0]	MAIN[9][0]	CELL.IMUX_IO_O1[1]
						Source
0	0	0	1	1	1	CELL.LONG_H[0]
0	0	1	0	1	1	CELL.LONG_H[1]
0	0	1	1	0	1	CELL.DEC_V[2]
0	0	1	1	1	0	CELL.DEC_V[3]
0	1	0	1	1	1	CELL_S.DOUBLE_H1[1]
0	1	1	0	1	1	CELL.LONG_H[2]
0	1	1	1	0	1	CELL.DEC_V[0]
0	1	1	1	1	0	CELL.DEC_V[1]
1	0	1	1	1	1	CELL_S.DOUBLE_H0[0]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_E0_N switchbox INT muxes IMUX_IO_OK[0]
Bits								Destination
MAIN[7][6]	MAIN[16][6]	MAIN[8][5]	MAIN[13][6]	MAIN[10][6]	MAIN[11][6]	MAIN[14][6]	MAIN[9][6]	CELL.IMUX_IO_OK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_H[2]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[3]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[4]

xc4000h IO_E0_N switchbox INT muxes IMUX_IO_OK[1]
Bits								Destination
MAIN[5][2]	MAIN[7][2]	MAIN[8][2]	MAIN[12][2]	MAIN[6][2]	MAIN[13][2]	MAIN[14][2]	MAIN[9][2]	CELL.IMUX_IO_OK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_S.SINGLE_H[2]
0	1	1	1	1	1	0	1	CELL_S.SINGLE_H[3]
0	1	1	1	1	1	1	0	CELL_S.SINGLE_H[4]
1	1	1	1	1	1	1	1	CELL_S.SINGLE_H[5]

xc4000h IO_E0_N switchbox INT muxes IMUX_IO_IK[0]
Bits								Destination
MAIN[5][7]	MAIN[11][7]	MAIN[12][7]	MAIN[9][7]	MAIN[7][7]	MAIN[8][7]	MAIN[10][7]	MAIN[6][7]	CELL.IMUX_IO_IK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_H[3]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[2]

xc4000h IO_E0_N switchbox INT muxes IMUX_IO_IK[1]
Bits								Destination
MAIN[5][1]	MAIN[7][1]	MAIN[7][3]	MAIN[11][2]	MAIN[6][1]	MAIN[8][1]	MAIN[10][2]	MAIN[11][3]	CELL.IMUX_IO_IK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_S.SINGLE_H[2]
0	1	1	1	1	1	0	1	CELL_S.SINGLE_H[4]
0	1	1	1	1	1	1	0	CELL_S.SINGLE_H[5]
1	1	1	1	1	1	1	1	CELL_S.SINGLE_H[3]

xc4000h IO_E0_N switchbox INT muxes IMUX_IO_T[0]
Bits								Destination
MAIN[20][3]	MAIN[18][4]	MAIN[19][2]	MAIN[21][2]	MAIN[19][3]	MAIN[23][3]	MAIN[20][2]	MAIN[24][3]	CELL.IMUX_IO_T[0]
								Source
0	0	0	1	1	0	1	1	CELL.LONG_IO_V[3]
0	0	0	1	1	1	0	1	CELL.LONG_IO_V[1]
0	0	0	1	1	1	1	0	CELL.GCLK[0]
0	0	1	0	1	0	1	1	CELL.LONG_IO_V[0]
0	0	1	0	1	1	0	1	CELL.DEC_V[2]
0	0	1	1	0	0	1	1	CELL.DOUBLE_IO_E2[1]
0	0	1	1	0	1	0	1	CELL.LONG_IO_V[2]
0	0	1	1	0	1	1	0	CELL.DEC_V[3]
0	1	1	1	1	1	1	1	CELL.TIE_0
1	0	0	1	1	1	1	1	CELL.DOUBLE_IO_E1[0]
1	0	1	0	1	1	1	1	CELL.DOUBLE_IO_E1[1]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_E2[0]

xc4000h IO_E0_N switchbox INT muxes IMUX_IO_T[1]
Bits								Destination
MAIN[16][3]	MAIN[14][3]	MAIN[18][2]	MAIN[23][2]	MAIN[17][3]	MAIN[25][2]	MAIN[16][2]	MAIN[15][2]	CELL.IMUX_IO_T[1]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	1	0	1	1	CELL.LONG_IO_V[1]
0	0	1	0	1	1	0	1	CELL.LONG_IO_V[3]
0	0	1	0	1	1	1	0	CELL.GCLK[0]
0	0	1	1	0	0	1	1	CELL.DEC_V[2]
0	0	1	1	0	1	0	1	CELL.LONG_IO_V[0]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_E1[0]
0	1	1	1	0	1	1	1	CELL.DOUBLE_IO_E2[0]
1	0	1	1	1	0	1	1	CELL.DOUBLE_IO_E2[1]
1	0	1	1	1	1	0	1	CELL.LONG_IO_V[2]
1	0	1	1	1	1	1	0	CELL.DEC_V[3]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_E1[1]

xc4000h IO_E0_N switchbox INT muxes IMUX_HIO_O[0]
Bits	Destination
MAIN[0][7]	CELL.IMUX_HIO_O[0]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_G1

xc4000h IO_E0_N switchbox INT muxes IMUX_HIO_O[1]
Bits	Destination
MAIN[3][6]	CELL.IMUX_HIO_O[1]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_G1

xc4000h IO_E0_N switchbox INT muxes IMUX_HIO_O[2]
Bits	Destination
MAIN[4][2]	CELL.IMUX_HIO_O[2]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_F1

xc4000h IO_E0_N switchbox INT muxes IMUX_HIO_O[3]
Bits	Destination
MAIN[2][1]	CELL.IMUX_HIO_O[3]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_F1

xc4000h IO_E0_N switchbox INT muxes IMUX_HIO_T[0]
Bits	Destination
MAIN[4][8]	CELL.IMUX_HIO_T[0]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_OK[0]

xc4000h IO_E0_N switchbox INT muxes IMUX_HIO_T[1]
Bits	Destination
MAIN[1][6]	CELL.IMUX_HIO_T[1]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_IK[0]

xc4000h IO_E0_N switchbox INT muxes IMUX_HIO_T[2]
Bits	Destination
MAIN[1][3]	CELL.IMUX_HIO_T[2]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_IK[1]

xc4000h IO_E0_N switchbox INT muxes IMUX_HIO_T[3]
Bits	Destination
MAIN[4][1]	CELL.IMUX_HIO_T[3]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_OK[1]

xc4000h IO_E0_N switchbox INT muxes OUT_IO_WE_I1[0]
Bits	Destination
MAIN[0][5]	CELL.OUT_IO_WE_I1[0]
	Source
0	CELL.OUT_HIO_I[1]
1	CELL.OUT_HIO_I[0]

xc4000h IO_E0_N switchbox INT muxes OUT_IO_WE_I1[1]
Bits	Destination
MAIN[1][4]	CELL.OUT_IO_WE_I1[1]
	Source
0	CELL.OUT_HIO_I[2]
1	CELL.OUT_HIO_I[3]

xc4000h IO_E0_N switchbox INT muxes OUT_IO_WE_I2[0]
Bits	Destination
MAIN[3][9]	CELL.OUT_IO_WE_I2[0]
	Source
0	CELL.OUT_HIO_I[0]
1	CELL.OUT_HIO_I[1]

xc4000h IO_E0_N switchbox INT muxes OUT_IO_WE_I2[1]
Bits	Destination
MAIN[3][0]	CELL.OUT_IO_WE_I2[1]
	Source
0	CELL.OUT_HIO_I[3]
1	CELL.OUT_HIO_I[2]

Bels TBUF

xc4000h IO_E0_N bel TBUF pins
Pin	Direction	TBUF[0]	TBUF[1]
I	in	CELL.IMUX_TBUF_I[0]	CELL.IMUX_TBUF_I[1]
T	in	CELL.IMUX_TBUF_T[0]	CELL.IMUX_TBUF_T[1]
O	bidir	CELL.LONG_H[2]	CELL.LONG_H[3]

xc4000h IO_E0_N bel TBUF attribute bits
Attribute	TBUF[0]	TBUF[1]
DRIVE1	!MAIN[25][3]	!MAIN[13][3]

Bels HIO

xc4000h IO_E0_N bel HIO pins
Pin	Direction	HIO[0]	HIO[1]	HIO[2]	HIO[3]
O	in	CELL.IMUX_HIO_O[0] invert by !MAIN[1][8]	CELL.IMUX_HIO_O[1] invert by !MAIN[2][6]	CELL.IMUX_HIO_O[2] invert by !MAIN[2][3]	CELL.IMUX_HIO_O[3] invert by !MAIN[3][1]
T	in	CELL.IMUX_HIO_T[0] invert by !MAIN[4][9]	CELL.IMUX_HIO_T[1] invert by !MAIN[0][6]	CELL.IMUX_HIO_T[2] invert by !MAIN[0][3]	CELL.IMUX_HIO_T[3] invert by !MAIN[4][0]
I	out	CELL.OUT_HIO_I[0]	CELL.OUT_HIO_I[1]	CELL.OUT_HIO_I[2]	CELL.OUT_HIO_I[3]
CLKIN	out	CELL.OUT_IO_CLKIN	-	-	-

xc4000h IO_E0_N bel HIO attribute bits
Attribute	HIO[0]	HIO[1]	HIO[2]	HIO[3]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
ISTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OSTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OMODE	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]
I_INV	!MAIN[2][9]	!MAIN[1][5]	!MAIN[0][4]	!MAIN[2][0]
READBACK_I bit 0	!MAIN[2][8]	!MAIN[0][8]	!MAIN[4][3]	!MAIN[3][3]

xc4000h IO_E0_N enum IO_PULL
HIO[0].PULL	MAIN[1][7]	MAIN[2][7]
HIO[1].PULL	MAIN[4][6]	MAIN[8][6]
HIO[2].PULL	MAIN[9][3]	MAIN[3][2]
HIO[3].PULL	MAIN[0][1]	MAIN[1][1]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

xc4000h IO_E0_N enum IO_STD
HIO[0].ISTD	MAIN[1][9]
HIO[1].ISTD	MAIN[2][5]
HIO[2].ISTD	MAIN[2][4]
HIO[3].ISTD	MAIN[1][0]
CMOS	0
TTL	1

xc4000h IO_E0_N enum IO_STD
HIO[0].OSTD	MAIN[0][9]
HIO[1].OSTD	MAIN[3][5]
HIO[2].OSTD	MAIN[3][4]
HIO[3].OSTD	MAIN[0][0]
CMOS	1
TTL	0

xc4000h IO_E0_N enum HIO_OMODE
HIO[0].OMODE	MAIN[3][7]
HIO[1].OMODE	MAIN[4][7]
HIO[2].OMODE	MAIN[1][2]
HIO[3].OMODE	MAIN[0][2]
CAP	1
RES	0

Bels DEC

xc4000h IO_E0_N bel DEC pins
Pin	Direction	DEC[0]	DEC[1]	DEC[2]
I	in	CELL.OUT_IO_WE_I1[0]	CELL.IMUX_CLB_C1	CELL.OUT_IO_WE_I1[1]
O1	bidir	CELL.DEC_V[0]	CELL.DEC_V[0]	CELL.DEC_V[0]
O2	bidir	CELL.DEC_V[1]	CELL.DEC_V[1]	CELL.DEC_V[1]
O3	bidir	CELL.DEC_V[2]	CELL.DEC_V[2]	CELL.DEC_V[2]
O4	bidir	CELL.DEC_V[3]	CELL.DEC_V[3]	CELL.DEC_V[3]

xc4000h IO_E0_N bel DEC attribute bits
Attribute	DEC[0]	DEC[1]	DEC[2]
O1_P	!MAIN[5][4]	!MAIN[5][6]	MAIN[4][5]
O1_N	MAIN[5][3]	MAIN[5][5]	!MAIN[4][4]
O2_P	!MAIN[10][4]	!MAIN[8][3]	MAIN[9][4]
O2_N	MAIN[10][3]	MAIN[8][4]	!MAIN[9][5]
O3_P	!MAIN[6][3]	!MAIN[6][6]	MAIN[7][4]
O3_N	MAIN[6][4]	MAIN[6][5]	!MAIN[7][5]
O4_P	!MAIN[12][4]	!MAIN[12][5]	MAIN[11][5]
O4_N	MAIN[12][3]	MAIN[12][6]	!MAIN[11][4]

Bels PULLUP

xc4000h IO_E0_N bel PULLUP pins
Pin	Direction	PULLUP_TBUF[0]	PULLUP_TBUF[1]
O	bidir	CELL.LONG_H[2]	CELL.LONG_H[3]

xc4000h IO_E0_N bel PULLUP attribute bits
Attribute	PULLUP_TBUF[0]	PULLUP_TBUF[1]
ENABLE	!MAIN_S[25][7]	!MAIN[14][7]

Bel wires

xc4000h IO_E0_N bel wires
Wire	Pins
CELL.LONG_H[2]	TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]	TBUF[1].O, PULLUP_TBUF[1].O
CELL.DEC_V[0]	DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_V[1]	DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.DEC_V[2]	DEC[0].O3, DEC[1].O3, DEC[2].O3
CELL.DEC_V[3]	DEC[0].O4, DEC[1].O4, DEC[2].O4
CELL.IMUX_CLB_C1	DEC[1].I
CELL.IMUX_TBUF_I[0]	TBUF[0].I
CELL.IMUX_TBUF_I[1]	TBUF[1].I
CELL.IMUX_TBUF_T[0]	TBUF[0].T
CELL.IMUX_TBUF_T[1]	TBUF[1].T
CELL.IMUX_HIO_O[0]	HIO[0].O
CELL.IMUX_HIO_O[1]	HIO[1].O
CELL.IMUX_HIO_O[2]	HIO[2].O
CELL.IMUX_HIO_O[3]	HIO[3].O
CELL.IMUX_HIO_T[0]	HIO[0].T
CELL.IMUX_HIO_T[1]	HIO[1].T
CELL.IMUX_HIO_T[2]	HIO[2].T
CELL.IMUX_HIO_T[3]	HIO[3].T
CELL.OUT_IO_WE_I1[0]	DEC[0].I
CELL.OUT_IO_WE_I1[1]	DEC[2].I
CELL.OUT_HIO_I[0]	HIO[0].I
CELL.OUT_HIO_I[1]	HIO[1].I
CELL.OUT_HIO_I[2]	HIO[2].I
CELL.OUT_HIO_I[3]	HIO[3].I
CELL.OUT_IO_CLKIN	HIO[0].CLKIN

Bitstream

xc4000h IO_E0_N rect MAIN
Bit	Frame
Bit	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7]	INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7]	INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7]	INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5]	-	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0]	INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0	INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_E0[3]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E0[3]	INT: !bipass CELL.DOUBLE_IO_E0[3] = CELL.DOUBLE_IO_E2[3]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E1[3]	INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_E1[3]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E2[3]	INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_E2[3]	-	INT: !pass CELL.SINGLE_H[7] ← CELL.DEC_V[3]	INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E0[1]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E0[1]	INT: !bipass CELL.DOUBLE_IO_E0[1] = CELL.DOUBLE_IO_E2[1]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E1[1]	INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E1[1]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E2[1]	INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E2[1]	INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[1]	INT: mux CELL.LONG_IO_V[1] bit 2	INT: mux CELL.IMUX_IO_O1[0] bit 2	INT: mux CELL.IMUX_IO_O1[0] bit 1	INT: mux CELL.IMUX_IO_O1[0] bit 5	HIO[0]: !invert T	INT: mux CELL.OUT_IO_WE_I2[0] bit 0	HIO[0]: ! I_INV	HIO[0]: ISTD bit 0	HIO[0]: OSTD bit 0
B8	-	INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4]	INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6]	INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6]	-	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2]	-	INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0]	-	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0]	-	INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_IO_WE_I1_S1	INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_IO_WE_I1[0]	INT: mux CELL.LONG_IO_V[2] bit 1	INT: mux CELL.LONG_IO_V[2] bit 0	INT: mux CELL.LONG_IO_V[2] bit 2	INT: mux CELL.LONG_IO_V[2] bit 3	INT: mux CELL.LONG_IO_V[3] bit 1	-	INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_IO_V[3]	INT: mux CELL.LONG_IO_V[3] bit 0	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1	INT: mux CELL.LONG_IO_V[1] bit 0	INT: mux CELL.LONG_IO_V[1] bit 1	INT: mux CELL.LONG_IO_V[1] bit 3	INT: mux CELL.DBUF_IO_V[1] bit 1	INT: mux CELL.DBUF_IO_V[1] bit 0	INT: mux CELL.DBUF_IO_V[1] bit 2	INT: mux CELL.DBUF_IO_V[1] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 4	INT: mux CELL.IMUX_HIO_T[0] bit 0	-	HIO[0]: ! READBACK_I bit 0	HIO[0]: !invert O	HIO[1]: ! READBACK_I bit 0
B7	INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5]	INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2]	INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6]	INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3]	INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3]	-	INT: mux CELL.LONG_H[4] bit 1	INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1_S1	INT: mux CELL.LONG_H[4] bit 2	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0]	INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1[0]	INT: mux CELL.LONG_H[5] bit 2	-	INT: !pass CELL.DOUBLE_IO_E0[3] ← CELL.DBUF_IO_V[0]	INT: !pass CELL.DOUBLE_IO_E0[1] ← CELL.DBUF_IO_V[0]	INT: mux CELL.LONG_H[5] bit 3	PULLUP_TBUF[1]: ! ENABLE	INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[1]	INT: mux CELL.IMUX_IO_IK[0] bit 5	INT: mux CELL.IMUX_IO_IK[0] bit 6	INT: mux CELL.IMUX_IO_IK[0] bit 1	INT: mux CELL.IMUX_IO_IK[0] bit 4	INT: mux CELL.IMUX_IO_IK[0] bit 2	INT: mux CELL.IMUX_IO_IK[0] bit 3	INT: mux CELL.IMUX_IO_IK[0] bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 7	HIO[1]: OMODE bit 0	HIO[0]: OMODE bit 0	HIO[0]: PULL bit 0	HIO[0]: PULL bit 1	INT: mux CELL.IMUX_HIO_O[0] bit 0
B6	INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4]	INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4]	INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1]	INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5]	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0]	INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[4]	INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0	INT: mux CELL.LONG_H[4] bit 0	INT: mux CELL.LONG_H[4] bit 3	INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.DOUBLE_IO_E2[3] ← CELL.DBUF_IO_V[1]	INT: mux CELL.LONG_H[5] bit 1	INT: mux CELL.LONG_H[5] bit 0	INT: !pass CELL.DOUBLE_IO_E0[0] ← CELL.DBUF_IO_V[0]	-	INT: !pass CELL.DOUBLE_IO_E0[2] ← CELL.DBUF_IO_V[0]	INT: mux CELL.IMUX_IO_OK[0] bit 6	INT: !pass CELL.DOUBLE_IO_E2[1] ← CELL.DBUF_IO_V[1]	INT: mux CELL.IMUX_IO_OK[0] bit 1	INT: mux CELL.IMUX_IO_OK[0] bit 4	DEC[1]: O4_N	INT: mux CELL.IMUX_IO_OK[0] bit 2	INT: mux CELL.IMUX_IO_OK[0] bit 3	INT: mux CELL.IMUX_IO_OK[0] bit 0	HIO[1]: PULL bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 7	DEC[1]: ! O3_P	DEC[1]: ! O1_P	HIO[1]: PULL bit 1	INT: mux CELL.IMUX_HIO_O[1] bit 0	HIO[1]: !invert O	INT: mux CELL.IMUX_HIO_T[1] bit 0	HIO[1]: !invert T
B5	INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4]	INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5]	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5]	INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1]	INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1]	INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E0[0]	INT: mux CELL.LONG_IO_V[0] bit 0	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E0[0]	INT: !bipass CELL.DOUBLE_IO_E0[0] = CELL.DOUBLE_IO_E2[0]	INT: mux CELL.LONG_IO_V[0] bit 1	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E1[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E1[0]	INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[0]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E2[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E2[0]	INT: !pass CELL.DOUBLE_IO_E2[0] ← CELL.DBUF_IO_V[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E2[2]	INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_E2[2]	DEC[1]: ! O4_P	DEC[2]: O4_P	INT: !pass CELL.SINGLE_H[4] ← CELL.DEC_V[2]	DEC[2]: ! O2_N	INT: mux CELL.IMUX_IO_OK[0] bit 5	DEC[2]: ! O3_N	DEC[1]: O3_N	DEC[1]: O1_N	DEC[2]: O1_P	HIO[1]: OSTD bit 0	HIO[1]: ISTD bit 0	HIO[1]: ! I_INV	INT: mux CELL.OUT_IO_WE_I1[0] bit 0
B4	INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E	INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5]	INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_WE_I2[1]	INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_WE_I2[1]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E	INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4]	INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3]	INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1]	INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_WE_I2[1]	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_WE_I2[0]	INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[3]	INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E	INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[0]	INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_IO_V[2]	INT: mux CELL.IMUX_IO_T[0] bit 6	INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_E0[2]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E0[2]	INT: !bipass CELL.DOUBLE_IO_E0[2] = CELL.DOUBLE_IO_E2[2]	INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_E1[2]	INT: !pass CELL.DOUBLE_IO_E2[2] ← CELL.DBUF_IO_V[1]	DEC[0]: ! O4_P	DEC[2]: ! O4_N	DEC[0]: ! O2_P	DEC[2]: O2_P	DEC[1]: O2_N	DEC[2]: O3_P	DEC[0]: O3_N	DEC[0]: ! O1_P	DEC[2]: ! O1_N	HIO[2]: OSTD bit 0	HIO[2]: ISTD bit 0	INT: mux CELL.OUT_IO_WE_I1[1] bit 0	HIO[2]: ! I_INV
B3	INT: mux CELL.IMUX_CLB_F3 bit 0	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E	INT: mux CELL.IMUX_CLB_C3 bit 1	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5]	INT: mux CELL.IMUX_CLB_G3 bit 0	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1]	INT: mux CELL.IMUX_CLB_F1 bit 3	INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1]	INT: mux CELL.IMUX_CLB_C1 bit 7	INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4]	INT: mux CELL.IMUX_CLB_G1 bit 6	TBUF[0]: ! DRIVE1	INT: mux CELL.IMUX_IO_T[0] bit 0	INT: mux CELL.IMUX_IO_T[0] bit 2	INT: mux CELL.DBUF_IO_V[0] bit 0	INT: mux CELL.DBUF_IO_V[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 7	INT: mux CELL.IMUX_IO_T[0] bit 3	-	INT: mux CELL.IMUX_IO_T[1] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 7	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E1[2]	INT: mux CELL.IMUX_IO_T[1] bit 6	TBUF[1]: ! DRIVE1	DEC[0]: O4_N	INT: mux CELL.IMUX_IO_IK[1] bit 0	DEC[0]: O2_N	HIO[2]: PULL bit 1	DEC[1]: ! O2_P	INT: mux CELL.IMUX_IO_IK[1] bit 5	DEC[0]: ! O3_P	DEC[0]: O1_N	HIO[2]: ! READBACK_I bit 0	HIO[3]: ! READBACK_I bit 0	HIO[2]: !invert O	INT: mux CELL.IMUX_HIO_T[2] bit 0	HIO[2]: !invert T
B2	INT: mux CELL.IMUX_CLB_F3 bit 2	INT: mux CELL.IMUX_CLB_F3 bit 6	INT: mux CELL.IMUX_CLB_F3 bit 8	INT: mux CELL.IMUX_CLB_C3 bit 2	INT: mux CELL.IMUX_CLB_C3 bit 3	INT: mux CELL.IMUX_CLB_G3 bit 1	INT: mux CELL.IMUX_CLB_G3 bit 4	INT: mux CELL.IMUX_CLB_G3 bit 7	INT: mux CELL.IMUX_CLB_F1 bit 0	INT: mux CELL.IMUX_CLB_F1 bit 7	INT: mux CELL.IMUX_CLB_C1 bit 2	INT: mux CELL.IMUX_CLB_C1 bit 1	INT: mux CELL.IMUX_CLB_C1 bit 6	-	INT: mux CELL.IMUX_CLB_G1 bit 0	INT: mux CELL.IMUX_IO_T[1] bit 2	INT: mux CELL.DBUF_IO_V[0] bit 2	INT: mux CELL.IMUX_IO_T[1] bit 4	INT: mux CELL.DBUF_IO_V[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 4	INT: mux CELL.IMUX_IO_T[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 5	INT: mux CELL.IMUX_IO_T[1] bit 5	-	INT: mux CELL.IMUX_IO_T[1] bit 1	INT: mux CELL.IMUX_IO_T[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 1	INT: mux CELL.IMUX_IO_OK[1] bit 2	INT: mux CELL.IMUX_IO_OK[1] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_OK[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 5	INT: mux CELL.IMUX_IO_OK[1] bit 6	INT: mux CELL.IMUX_IO_OK[1] bit 3	INT: mux CELL.IMUX_IO_OK[1] bit 7	INT: mux CELL.IMUX_HIO_O[2] bit 0	HIO[2]: PULL bit 0	-	HIO[2]: OMODE bit 0	HIO[3]: OMODE bit 0
B1	INT: mux CELL.IMUX_CLB_F3 bit 5	INT: mux CELL.IMUX_CLB_F3 bit 3	INT: mux CELL.IMUX_CLB_C3 bit 0	INT: mux CELL.IMUX_CLB_C3 bit 5	INT: mux CELL.IMUX_CLB_C3 bit 6	INT: mux CELL.IMUX_CLB_G3 bit 6	INT: mux CELL.IMUX_CLB_G3 bit 2	INT: mux CELL.IMUX_CLB_G3 bit 5	INT: mux CELL.IMUX_CLB_F1 bit 5	INT: mux CELL.IMUX_CLB_F1 bit 2	INT: mux CELL.IMUX_CLB_C1 bit 5	INT: mux CELL.IMUX_CLB_C1 bit 3	INT: mux CELL.IMUX_CLB_G1 bit 4	INT: mux CELL.IMUX_CLB_G1 bit 3	INT: mux CELL.IMUX_CLB_G1 bit 2	INT: mux CELL.LONG_H[0] bit 1	INT: mux CELL.LONG_H[0] bit 3	INT: mux CELL.IMUX_TBUF_I[0] bit 5	INT: mux CELL.IMUX_TBUF_I[0] bit 0	INT: mux CELL.IMUX_TBUF_I[0] bit 2	INT: mux CELL.IMUX_TBUF_T[0] bit 2	INT: mux CELL.IMUX_TBUF_T[0] bit 1	INT: mux CELL.IMUX_TBUF_T[1] bit 2	INT: mux CELL.IMUX_TBUF_T[1] bit 4	INT: mux CELL.IMUX_TBUF_T[1] bit 0	INT: mux CELL.IMUX_TBUF_T[1] bit 3	INT: mux CELL.IMUX_TBUF_I[1] bit 4	INT: mux CELL.IMUX_TBUF_I[1] bit 0	INT: mux CELL.IMUX_TBUF_I[1] bit 5	INT: mux CELL.LONG_H[1] bit 0	INT: mux CELL.LONG_H[1] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 6	INT: mux CELL.IMUX_IO_IK[1] bit 3	INT: mux CELL.IMUX_IO_IK[1] bit 7	INT: mux CELL.IMUX_HIO_T[3] bit 0	HIO[3]: !invert O	INT: mux CELL.IMUX_HIO_O[3] bit 0	HIO[3]: PULL bit 0	HIO[3]: PULL bit 1
B0	INT: mux CELL.IMUX_CLB_F3 bit 7	INT: mux CELL.IMUX_CLB_F3 bit 1	INT: mux CELL.IMUX_CLB_F3 bit 4	INT: mux CELL.IMUX_CLB_C3 bit 4	INT: mux CELL.IMUX_CLB_C3 bit 7	INT: mux CELL.IMUX_CLB_G3 bit 3	INT: mux CELL.IMUX_CLB_G3 bit 8	INT: mux CELL.IMUX_CLB_F1 bit 6	INT: mux CELL.IMUX_CLB_F1 bit 1	INT: mux CELL.IMUX_CLB_F1 bit 4	INT: mux CELL.IMUX_CLB_C1 bit 0	INT: mux CELL.IMUX_CLB_C1 bit 4	INT: mux CELL.IMUX_CLB_G1 bit 5	INT: mux CELL.IMUX_CLB_G1 bit 1	INT: mux CELL.IMUX_CLB_G1 bit 7	INT: mux CELL.LONG_H[0] bit 0	INT: mux CELL.LONG_H[0] bit 2	INT: mux CELL.IMUX_TBUF_I[0] bit 3	INT: mux CELL.IMUX_TBUF_I[0] bit 1	INT: mux CELL.IMUX_TBUF_I[0] bit 4	INT: mux CELL.IMUX_TBUF_T[0] bit 3	INT: mux CELL.IMUX_TBUF_T[0] bit 4	INT: mux CELL.IMUX_TBUF_T[0] bit 0	INT: mux CELL.IMUX_TBUF_T[0] bit 5	INT: mux CELL.IMUX_TBUF_T[1] bit 1	INT: mux CELL.IMUX_TBUF_T[1] bit 5	INT: mux CELL.IMUX_TBUF_I[1] bit 2	INT: mux CELL.IMUX_TBUF_I[1] bit 1	INT: mux CELL.IMUX_TBUF_I[1] bit 3	INT: mux CELL.LONG_H[1] bit 1	INT: mux CELL.LONG_H[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 0	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.IMUX_IO_O1[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 5	INT: mux CELL.IMUX_IO_O1[1] bit 4	HIO[3]: !invert T	INT: mux CELL.OUT_IO_WE_I2[1] bit 0	HIO[3]: ! I_INV	HIO[3]: ISTD bit 0	HIO[3]: OSTD bit 0

xc4000h IO_E0_N rect MAIN_S
Bit	Frame
Bit	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	-	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1]	-	-	-	INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2]	-	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0]	-	INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PULLUP_TBUF[0]: ! ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

xc4000h IO_E0_N rect MAIN_W
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile IO_E1

Cells: 3

Switchbox INT

xc4000h IO_E1 switchbox INT programmable buffers
Destination	Source	Bit
CELL.LONG_H[0]	CELL.SINGLE_V[1]	!MAIN_S[26][8]
CELL.LONG_H[1]	CELL.SINGLE_V[2]	!MAIN_S[30][8]
CELL.LONG_H[2]	CELL.SINGLE_V[3]	!MAIN[27][4]
CELL.LONG_H[3]	CELL.SINGLE_V[4]	!MAIN[27][6]
CELL.LONG_H[4]	CELL.SINGLE_V[5]	!MAIN[38][4]
CELL.LONG_H[5]	CELL.SINGLE_V[6]	!MAIN[40][6]
CELL.LONG_V[0]	CELL.SINGLE_H_E[1]	!MAIN[32][4]
CELL.LONG_V[1]	CELL.SINGLE_H_E[2]	!MAIN[38][8]
CELL.LONG_V[2]	CELL.SINGLE_H_E[3]	!MAIN[34][6]
CELL.LONG_V[3]	CELL.SINGLE_H[4]	!MAIN[34][4]
CELL.LONG_V[4]	CELL.SINGLE_H[5]	!MAIN[31][6]
CELL.LONG_V[5]	CELL.SINGLE_H[6]	!MAIN[35][8]

xc4000h IO_E1 switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[0]	CELL.DEC_V[0]	!MAIN[18][5]
CELL.SINGLE_H[0]	CELL.OUT_IO_WE_I2_S1	!MAIN[24][4]
CELL.SINGLE_H[1]	CELL.LONG_IO_V[0]	!MAIN[22][4]
CELL.SINGLE_H[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[21][4]
CELL.SINGLE_H[2]	CELL.LONG_IO_V[1]	!MAIN[13][7]
CELL.SINGLE_H[2]	CELL.OUT_IO_WE_I1[0]	!MAIN[21][7]
CELL.SINGLE_H[3]	CELL.DEC_V[1]	!MAIN[9][9]
CELL.SINGLE_H[3]	CELL.OUT_IO_WE_I1_S1	!MAIN[15][8]
CELL.SINGLE_H[4]	CELL.LONG_V[3]	!MAIN[33][4]
CELL.SINGLE_H[4]	CELL.DEC_V[2]	!MAIN[10][5]
CELL.SINGLE_H[4]	CELL.OUT_IO_WE_I2_S1	!MAIN[25][4]
CELL.SINGLE_H[5]	CELL.LONG_V[4]	!MAIN[27][3]
CELL.SINGLE_H[5]	CELL.LONG_IO_V[2]	!MAIN[19][4]
CELL.SINGLE_H[5]	CELL.OUT_IO_WE_I2[0]	!MAIN[20][4]
CELL.SINGLE_H[6]	CELL.LONG_V[5]	!MAIN[34][9]
CELL.SINGLE_H[6]	CELL.LONG_IO_V[3]	!MAIN[17][8]
CELL.SINGLE_H[6]	CELL.OUT_IO_WE_I1[0]	!MAIN[24][8]
CELL.SINGLE_H[7]	CELL.DEC_V[3]	!MAIN[17][9]
CELL.SINGLE_H[7]	CELL.OUT_IO_WE_I1_S1	!MAIN[25][8]
CELL.SINGLE_H_E[1]	CELL.LONG_V[0]	!MAIN[32][5]
CELL.SINGLE_H_E[2]	CELL.LONG_V[1]	!MAIN[40][9]
CELL.SINGLE_H_E[3]	CELL.LONG_V[2]	!MAIN[39][7]
CELL.SINGLE_V[0]	CELL.TIE_0	!MAIN[26][6]
CELL.SINGLE_V[0]	CELL.OUT_IO_WE_I2[0]	!MAIN[28][4]
CELL.SINGLE_V[1]	CELL.LONG_H[0]	!MAIN_S[28][8]
CELL.SINGLE_V[1]	CELL.OUT_IO_WE_I2[1]	!MAIN[29][4]
CELL.SINGLE_V[2]	CELL.LONG_H[1]	!MAIN_S[34][8]
CELL.SINGLE_V[2]	CELL.OUT_CLB_Y_E	!MAIN[30][4]
CELL.SINGLE_V[3]	CELL.LONG_H[2]	!MAIN_S[33][9]
CELL.SINGLE_V[3]	CELL.OUT_CLB_YQ_E	!MAIN[35][4]
CELL.SINGLE_V[4]	CELL.LONG_H[3]	!MAIN[26][7]
CELL.SINGLE_V[4]	CELL.OUT_IO_WE_I2[0]	!MAIN[39][3]
CELL.SINGLE_V[5]	CELL.LONG_H[4]	!MAIN[40][5]
CELL.SINGLE_V[5]	CELL.OUT_IO_WE_I2[1]	!MAIN[36][4]
CELL.SINGLE_V[6]	CELL.LONG_H[5]	!MAIN[40][7]
CELL.SINGLE_V[6]	CELL.OUT_CLB_Y_E	!MAIN[39][4]
CELL.SINGLE_V[7]	CELL.TIE_0	!MAIN[26][9]
CELL.SINGLE_V[7]	CELL.OUT_CLB_YQ_E	!MAIN[38][3]
CELL.DOUBLE_H0[0]	CELL.OUT_IO_WE_I1[0]	!MAIN[20][7]
CELL.DOUBLE_H0[1]	CELL.OUT_IO_WE_I2_S1	!MAIN[23][4]
CELL.DOUBLE_H1[0]	CELL.OUT_IO_WE_I1_S1	!MAIN[23][7]
CELL.DOUBLE_H1[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[23][6]
CELL.DOUBLE_V0[0]	CELL.OUT_CLB_YQ_E	!MAIN[26][4]
CELL.DOUBLE_V0[1]	CELL.OUT_IO_WE_I2[1]	!MAIN[37][4]
CELL.DOUBLE_V1[0]	CELL.OUT_CLB_Y_E	!MAIN[31][4]
CELL.DOUBLE_V1[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[40][4]
CELL.DOUBLE_IO_E0[0]	CELL.DBUF_IO_V[0]	!MAIN[19][6]
CELL.DOUBLE_IO_E0[1]	CELL.DBUF_IO_V[0]	!MAIN[16][7]
CELL.DOUBLE_IO_E0[2]	CELL.DBUF_IO_V[0]	!MAIN[17][6]
CELL.DOUBLE_IO_E0[3]	CELL.DBUF_IO_V[0]	!MAIN[17][7]
CELL.DOUBLE_IO_E2[0]	CELL.DBUF_IO_V[1]	!MAIN[15][5]
CELL.DOUBLE_IO_E2[1]	CELL.DBUF_IO_V[1]	!MAIN[15][6]
CELL.DOUBLE_IO_E2[2]	CELL.DBUF_IO_V[1]	!MAIN[13][4]
CELL.DOUBLE_IO_E2[3]	CELL.DBUF_IO_V[1]	!MAIN[22][6]

xc4000h IO_E1 switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.SINGLE_H_E[0]	!MAIN[28][6]
CELL.SINGLE_H[0]	CELL.SINGLE_V[0]	!MAIN[27][5]
CELL.SINGLE_H[0]	CELL.SINGLE_V_S[0]	!MAIN[30][3]
CELL.SINGLE_H[0]	CELL.DOUBLE_IO_E1[0]	!MAIN[19][5]
CELL.SINGLE_H[1]	CELL.SINGLE_H_E[1]	!MAIN[30][5]
CELL.SINGLE_H[1]	CELL.SINGLE_V[1]	!MAIN[29][5]
CELL.SINGLE_H[1]	CELL.SINGLE_V_S[1]	!MAIN[29][3]
CELL.SINGLE_H[1]	CELL.DOUBLE_IO_E0[0]	!MAIN[25][5]
CELL.SINGLE_H[1]	CELL.DOUBLE_IO_E2[0]	!MAIN[16][5]
CELL.SINGLE_H[2]	CELL.SINGLE_H_E[2]	!MAIN[32][8]
CELL.SINGLE_H[2]	CELL.SINGLE_V[2]	!MAIN[31][8]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[2]	!MAIN[33][8]
CELL.SINGLE_H[2]	CELL.DOUBLE_IO_E1[1]	!MAIN[12][9]
CELL.SINGLE_H[3]	CELL.SINGLE_H_E[3]	!MAIN[31][7]
CELL.SINGLE_H[3]	CELL.SINGLE_V[3]	!MAIN[28][7]
CELL.SINGLE_H[3]	CELL.SINGLE_V_S[3]	!MAIN[30][7]
CELL.SINGLE_H[3]	CELL.DOUBLE_IO_E0[1]	!MAIN[16][9]
CELL.SINGLE_H[3]	CELL.DOUBLE_IO_E2[1]	!MAIN[10][9]
CELL.SINGLE_H[4]	CELL.SINGLE_H_E[4]	!MAIN[36][6]
CELL.SINGLE_H[4]	CELL.SINGLE_V[4]	!MAIN[39][6]
CELL.SINGLE_H[4]	CELL.SINGLE_V_S[4]	!MAIN[35][6]
CELL.SINGLE_H[4]	CELL.DOUBLE_IO_E1[2]	!MAIN[14][4]
CELL.SINGLE_H[5]	CELL.SINGLE_H_E[5]	!MAIN[35][5]
CELL.SINGLE_H[5]	CELL.SINGLE_V[5]	!MAIN[36][3]
CELL.SINGLE_H[5]	CELL.SINGLE_V_S[5]	!MAIN[37][5]
CELL.SINGLE_H[5]	CELL.DOUBLE_IO_E0[2]	!MAIN[17][4]
CELL.SINGLE_H[5]	CELL.DOUBLE_IO_E2[2]	!MAIN[13][5]
CELL.SINGLE_H[6]	CELL.SINGLE_H_E[6]	!MAIN[35][7]
CELL.SINGLE_H[6]	CELL.SINGLE_V[6]	!MAIN[36][8]
CELL.SINGLE_H[6]	CELL.SINGLE_V_S[6]	!MAIN[36][7]
CELL.SINGLE_H[6]	CELL.DOUBLE_IO_E1[3]	!MAIN[21][9]
CELL.SINGLE_H[7]	CELL.SINGLE_H_E[7]	!MAIN[38][9]
CELL.SINGLE_H[7]	CELL.SINGLE_V[7]	!MAIN[35][9]
CELL.SINGLE_H[7]	CELL.SINGLE_V_S[7]	!MAIN[37][8]
CELL.SINGLE_H[7]	CELL.DOUBLE_IO_E0[3]	!MAIN[25][9]
CELL.SINGLE_H[7]	CELL.DOUBLE_IO_E2[3]	!MAIN[19][9]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V[0]	!MAIN[26][5]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V_S[0]	!MAIN[28][5]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V[1]	!MAIN[30][6]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V_S[1]	!MAIN[31][5]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V[2]	!MAIN[31][9]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V_S[2]	!MAIN[32][9]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V[3]	!MAIN[32][7]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V_S[3]	!MAIN[33][7]
CELL.SINGLE_H_E[4]	CELL.SINGLE_V[4]	!MAIN[39][8]
CELL.SINGLE_H_E[4]	CELL.SINGLE_V_S[4]	!MAIN[37][6]
CELL.SINGLE_H_E[5]	CELL.SINGLE_V[5]	!MAIN[36][5]
CELL.SINGLE_H_E[5]	CELL.SINGLE_V_S[5]	!MAIN[38][5]
CELL.SINGLE_H_E[6]	CELL.SINGLE_V[6]	!MAIN[34][7]
CELL.SINGLE_H_E[6]	CELL.SINGLE_V_S[6]	!MAIN[37][7]
CELL.SINGLE_H_E[7]	CELL.SINGLE_V[7]	!MAIN[37][9]
CELL.SINGLE_H_E[7]	CELL.SINGLE_V_S[7]	!MAIN[39][9]
CELL.SINGLE_V[0]	CELL.SINGLE_V_S[0]	!MAIN[29][6]
CELL.SINGLE_V[1]	CELL.SINGLE_V_S[1]	!MAIN[31][3]
CELL.SINGLE_V[2]	CELL.SINGLE_V_S[2]	!MAIN[30][9]
CELL.SINGLE_V[3]	CELL.SINGLE_V_S[3]	!MAIN[27][7]
CELL.SINGLE_V[4]	CELL.SINGLE_V_S[4]	!MAIN[38][6]
CELL.SINGLE_V[5]	CELL.SINGLE_V_S[5]	!MAIN[39][5]
CELL.SINGLE_V[6]	CELL.SINGLE_V_S[6]	!MAIN[38][7]
CELL.SINGLE_V[7]	CELL.SINGLE_V_S[7]	!MAIN[36][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_H2[0]	!MAIN[29][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_V0[0]	!MAIN[27][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_V2[0]	!MAIN[28][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_E0[1]	!MAIN[15][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_E1[1]	!MAIN[13][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_E2[1]	!MAIN[11][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_H2[1]	!MAIN[33][6]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_V0[1]	!MAIN[32][6]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_V2[1]	!MAIN[33][3]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_E0[2]	!MAIN[16][4]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_E1[2]	!MAIN[15][3]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_E2[2]	!MAIN[14][5]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_E0[0]	!MAIN[23][5]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_E1[0]	!MAIN[20][5]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_E2[0]	!MAIN[17][5]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_E0[3]	!MAIN[24][9]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_E1[3]	!MAIN[22][9]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_E2[3]	!MAIN[20][9]
CELL.DOUBLE_H2[0]	CELL.DOUBLE_V0[0]	!MAIN[29][7]
CELL.DOUBLE_H2[0]	CELL.DOUBLE_V2[0]	!MAIN[29][8]
CELL.DOUBLE_H2[1]	CELL.DOUBLE_V0[1]	!MAIN[33][5]
CELL.DOUBLE_H2[1]	CELL.DOUBLE_V2[1]	!MAIN[34][5]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_V2[0]	!MAIN[27][8]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_V2[1]	!MAIN[34][3]
CELL.DOUBLE_IO_E0[0]	CELL.DOUBLE_IO_E2[0]	!MAIN[22][5]
CELL.DOUBLE_IO_E0[1]	CELL.DOUBLE_IO_E2[1]	!MAIN[14][9]
CELL.DOUBLE_IO_E0[2]	CELL.DOUBLE_IO_E2[2]	!MAIN[15][4]
CELL.DOUBLE_IO_E0[3]	CELL.DOUBLE_IO_E2[3]	!MAIN[23][9]

xc4000h IO_E1 switchbox INT muxes DBUF_IO_V[0]
Bits				Destination
MAIN[21][3]	MAIN[24][2]	MAIN[22][2]	MAIN[22][3]	CELL.DBUF_IO_V[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_E2[0]
0	1	0	1	CELL.DOUBLE_IO_E2[1]
0	1	1	0	CELL.DOUBLE_IO_E2[3]
1	1	1	1	CELL.DOUBLE_IO_E2[2]

xc4000h IO_E1 switchbox INT muxes DBUF_IO_V[1]
Bits				Destination
MAIN[8][8]	MAIN[9][8]	MAIN[11][8]	MAIN[10][8]	CELL.DBUF_IO_V[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_E0[1]
0	1	0	1	CELL.DOUBLE_IO_E0[2]
0	1	1	0	CELL.DOUBLE_IO_E0[3]
1	1	1	1	CELL.DOUBLE_IO_E0[0]

xc4000h IO_E1 switchbox INT muxes LONG_H[0]
Bits				Destination
MAIN[24][1]	MAIN[24][0]	MAIN[25][1]	MAIN[25][0]	CELL.LONG_H[0]
				Source
0	0	0	1	CELL.LONG_IO_V[0]
0	0	1	0	CELL.DEC_V[3]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000h IO_E1 switchbox INT muxes LONG_H[1]
Bits				Destination
MAIN[10][1]	MAIN[10][0]	MAIN[11][0]	MAIN[11][1]	CELL.LONG_H[1]
				Source
0	0	0	1	CELL.LONG_IO_V[1]
0	0	1	0	CELL.DEC_V[2]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000h IO_E1 switchbox INT muxes LONG_H[4]
Bits				Destination
MAIN[24][6]	MAIN[22][7]	MAIN[24][7]	MAIN[25][6]	CELL.LONG_H[4]
				Source
0	0	0	1	CELL.LONG_IO_V[2]
0	0	1	0	CELL.DEC_V[1]
0	1	1	1	CELL.OUT_IO_WE_I2[0]
1	1	1	1	off

xc4000h IO_E1 switchbox INT muxes LONG_H[5]
Bits				Destination
MAIN[15][7]	MAIN[19][7]	MAIN[21][6]	MAIN[20][6]	CELL.LONG_H[5]
				Source
0	0	0	1	CELL.LONG_IO_V[3]
0	0	1	0	CELL.DEC_V[0]
0	1	1	1	CELL.OUT_IO_WE_I2[0]
1	1	1	1	off

xc4000h IO_E1 switchbox INT muxes LONG_IO_V[0]
Bits		Destination
MAIN[21][5]	MAIN[24][5]	CELL.LONG_IO_V[0]
		Source
0	0	CELL.LONG_H[0]
0	1	CELL.SINGLE_H[1]
1	1	off

xc4000h IO_E1 switchbox INT muxes LONG_IO_V[1]
Bits				Destination
MAIN[12][8]	MAIN[8][9]	MAIN[13][8]	MAIN[14][8]	CELL.LONG_IO_V[1]
				Source
0	0	0	1	CELL.LONG_H[1]
0	0	1	0	CELL.LONG_H[3]
0	1	1	1	CELL.SINGLE_H[2]
1	1	1	1	off

xc4000h IO_E1 switchbox INT muxes LONG_IO_V[2]
Bits				Destination
MAIN[20][8]	MAIN[21][8]	MAIN[23][8]	MAIN[22][8]	CELL.LONG_IO_V[2]
				Source
0	0	0	1	CELL.LONG_H[2]
0	0	1	0	CELL.LONG_H[4]
0	1	1	1	CELL.SINGLE_H[5]
1	1	1	1	off

xc4000h IO_E1 switchbox INT muxes LONG_IO_V[3]
Bits		Destination
MAIN[19][8]	MAIN[16][8]	CELL.LONG_IO_V[3]
		Source
0	0	CELL.LONG_H[5]
0	1	CELL.SINGLE_H[6]
1	1	off

xc4000h IO_E1 switchbox INT muxes IMUX_CLB_F1
Bits								Destination
MAIN[31][2]	MAIN[33][0]	MAIN[32][1]	MAIN[31][0]	MAIN[32][3]	MAIN[31][1]	MAIN[32][0]	MAIN[32][2]	CELL.IMUX_CLB_F1
								Source
0	0	1	0	0	1	1	1	CELL.SINGLE_V[3]
0	0	1	0	1	0	1	1	CELL.LONG_V[4]
0	0	1	0	1	1	1	0	CELL.SINGLE_V[7]
0	0	1	1	1	1	1	1	CELL.SINGLE_V[0]
0	1	0	0	0	1	1	1	CELL.LONG_V[3]
0	1	0	0	1	0	1	1	CELL.DOUBLE_V0[1]
0	1	0	0	1	1	1	0	CELL.LONG_V[0]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[1]
0	1	1	0	0	1	0	1	CELL.SINGLE_V[5]
0	1	1	0	1	0	0	1	CELL.LONG_V[1]
0	1	1	0	1	1	0	0	CELL.SINGLE_V[6]
0	1	1	1	1	1	0	1	CELL.DOUBLE_V1[1]
1	1	1	0	0	1	1	1	CELL.DOUBLE_V1[0]
1	1	1	0	1	0	1	1	CELL.SINGLE_V[4]
1	1	1	0	1	1	1	0	CELL.DOUBLE_V0[0]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[2]

xc4000h IO_E1 switchbox INT muxes IMUX_CLB_F3
Bits									Destination
MAIN[38][2]	MAIN[40][0]	MAIN[39][2]	MAIN[40][1]	MAIN[38][0]	MAIN[39][1]	MAIN[40][2]	MAIN[39][0]	MAIN[40][3]	CELL.IMUX_CLB_F3
									Source
0	0	0	0	1	1	1	1	1	CELL.SINGLE_V[0]
0	0	0	1	1	1	0	1	1	CELL.DOUBLE_V0[0]
0	0	0	1	1	1	1	0	1	CELL.LONG_V[2]
0	0	1	1	1	1	1	1	1	CELL.SINGLE_V[3]
0	1	0	0	0	1	1	1	1	CELL.DOUBLE_V1[1]
0	1	0	0	1	0	1	1	1	CELL.LONG_V[1]
0	1	0	1	0	1	0	1	1	CELL.DOUBLE_V0[1]
0	1	0	1	0	1	1	0	1	CELL.LONG_V[5]
0	1	0	1	1	0	0	1	1	CELL.SINGLE_V[4]
0	1	0	1	1	0	1	0	1	CELL.LONG_V[4]
0	1	0	1	1	1	1	1	0	CELL.GCLK[0]
0	1	1	1	0	1	1	1	1	CELL.SINGLE_V[1]
0	1	1	1	1	0	1	1	1	CELL.SINGLE_V[2]
1	1	0	0	1	1	1	1	1	CELL.SINGLE_V[6]
1	1	0	1	1	1	0	1	1	CELL.DOUBLE_V1[0]
1	1	0	1	1	1	1	0	1	CELL.SINGLE_V[5]
1	1	1	1	1	1	1	1	1	CELL.SINGLE_V[7]

xc4000h IO_E1 switchbox INT muxes IMUX_CLB_G1
Bits								Destination
MAIN[26][0]	MAIN[26][3]	MAIN[28][0]	MAIN[28][1]	MAIN[27][1]	MAIN[26][1]	MAIN[27][0]	MAIN[26][2]	CELL.IMUX_CLB_G1
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_V[0]
0	0	0	1	0	1	1	1	CELL.SINGLE_V[2]
0	0	0	1	1	1	0	1	CELL.SINGLE_V[4]
0	0	1	0	1	0	1	1	CELL.LONG_V[4]
0	0	1	0	1	1	1	0	CELL.LONG_V[3]
0	0	1	1	0	0	1	1	CELL.SINGLE_V[1]
0	0	1	1	0	1	1	0	CELL.DOUBLE_V1[0]
0	0	1	1	1	0	0	1	CELL.DOUBLE_V0[1]
0	0	1	1	1	1	0	0	CELL.LONG_V[0]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[3]
0	1	1	1	0	1	1	1	CELL.DOUBLE_V0[0]
0	1	1	1	1	1	0	1	CELL.SINGLE_V[7]
1	0	0	1	1	1	1	1	CELL.DOUBLE_V1[1]
1	0	1	1	1	0	1	1	CELL.LONG_V[1]
1	0	1	1	1	1	1	0	CELL.SINGLE_V[5]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[6]

xc4000h IO_E1 switchbox INT muxes IMUX_CLB_G3
Bits									Destination
MAIN[34][0]	MAIN[33][2]	MAIN[35][1]	MAIN[33][1]	MAIN[34][2]	MAIN[35][0]	MAIN[34][1]	MAIN[35][2]	MAIN[35][3]	CELL.IMUX_CLB_G3
									Source
0	0	0	1	1	1	1	1	1	CELL.SPECIAL_CLB_CIN
0	0	1	0	0	1	1	1	1	CELL.SINGLE_V[0]
0	0	1	0	1	0	1	1	1	CELL.SINGLE_V[2]
0	0	1	0	1	1	1	0	1	CELL.SINGLE_V[4]
0	0	1	1	0	1	0	1	1	CELL.LONG_V[4]
0	0	1	1	0	1	1	1	0	CELL.LONG_V[2]
0	0	1	1	1	0	0	1	1	CELL.SINGLE_V[1]
0	0	1	1	1	0	1	1	0	CELL.SINGLE_V[6]
0	0	1	1	1	1	0	0	1	CELL.DOUBLE_V0[1]
0	0	1	1	1	1	1	0	0	CELL.LONG_V[5]
0	1	1	1	0	1	1	1	1	CELL.DOUBLE_V0[0]
0	1	1	1	1	0	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	1	1	1	0	1	CELL.DOUBLE_V1[0]
1	0	1	0	1	1	1	1	1	CELL.DOUBLE_V1[1]
1	0	1	1	1	1	0	1	1	CELL.LONG_V[1]
1	0	1	1	1	1	1	1	0	CELL.SINGLE_V[7]
1	1	1	1	1	1	1	1	1	CELL.SINGLE_V[3]

xc4000h IO_E1 switchbox INT muxes IMUX_CLB_C1
Bits								Destination
MAIN[28][3]	MAIN[28][2]	MAIN[30][1]	MAIN[29][0]	MAIN[29][1]	MAIN[30][2]	MAIN[29][2]	MAIN[30][0]	CELL.IMUX_CLB_C1
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_V[0]
0	0	0	1	0	1	1	1	CELL.SINGLE_V[1]
0	0	1	0	1	0	1	1	CELL.DOUBLE_V0[0]
0	0	1	0	1	1	0	1	CELL.DOUBLE_V1[0]
0	0	1	1	0	0	1	1	CELL.SINGLE_V[3]
0	0	1	1	0	1	0	1	CELL.SINGLE_V[7]
0	0	1	1	1	0	1	0	CELL.LONG_V[2]
0	0	1	1	1	1	0	0	CELL.LONG_V[3]
0	1	1	0	1	1	1	1	CELL.DOUBLE_V1[1]
0	1	1	1	0	1	1	1	CELL.SINGLE_V[2]
1	0	0	1	1	1	1	1	CELL.DOUBLE_V0[1]
1	0	1	1	1	0	1	1	CELL.SINGLE_V[5]
1	0	1	1	1	1	0	1	CELL.SINGLE_V[6]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[4]

xc4000h IO_E1 switchbox INT muxes IMUX_CLB_C3
Bits								Destination
MAIN[36][0]	MAIN[36][1]	MAIN[37][1]	MAIN[37][0]	MAIN[36][2]	MAIN[37][2]	MAIN[37][3]	MAIN[38][1]	CELL.IMUX_CLB_C3
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_V[0]
0	0	0	1	0	1	1	1	CELL.SINGLE_V[2]
0	0	0	1	1	1	1	0	CELL.GCLK[2]
0	0	1	0	1	0	1	1	CELL.SINGLE_V[3]
0	0	1	0	1	1	0	1	CELL.SINGLE_V[7]
0	0	1	1	0	0	1	1	CELL.DOUBLE_V0[0]
0	0	1	1	0	1	0	1	CELL.DOUBLE_V1[0]
0	0	1	1	1	0	1	0	CELL.LONG_V[3]
0	0	1	1	1	1	0	0	CELL.LONG_V[2]
0	1	1	0	1	1	1	1	CELL.DOUBLE_V1[1]
0	1	1	1	0	1	1	1	CELL.SINGLE_V[1]
1	0	0	1	1	1	1	1	CELL.DOUBLE_V0[1]
1	0	1	1	1	0	1	1	CELL.SINGLE_V[5]
1	0	1	1	1	1	0	1	CELL.SINGLE_V[6]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[4]

xc4000h IO_E1 switchbox INT muxes IMUX_TBUF_I[0]
Bits						Destination
MAIN[23][1]	MAIN[21][0]	MAIN[23][0]	MAIN[21][1]	MAIN[22][0]	MAIN[22][1]	CELL.IMUX_TBUF_I[0]
						Source
0	0	0	1	1	1	CELL.DOUBLE_IO_E2[2]
0	0	1	0	1	1	CELL.OUT_IO_WE_I2[0]
0	0	1	1	0	1	CELL.LONG_IO_V[2]
0	0	1	1	1	0	CELL.DEC_V[1]
0	1	1	1	1	1	CELL.DOUBLE_IO_E1[2]
1	0	0	1	1	1	CELL.DOUBLE_IO_E1[3]
1	0	1	0	1	1	CELL.DOUBLE_IO_E2[3]
1	0	1	1	0	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_E1 switchbox INT muxes IMUX_TBUF_I[1]
Bits						Destination
MAIN[12][1]	MAIN[14][1]	MAIN[12][0]	MAIN[14][0]	MAIN[13][0]	MAIN[13][1]	CELL.IMUX_TBUF_I[1]
						Source
0	0	0	1	1	1	CELL.DOUBLE_IO_E1[2]
0	0	1	1	1	1	CELL.DOUBLE_IO_E1[3]
0	1	0	0	1	1	CELL.OUT_IO_WE_I2[0]
0	1	0	1	0	1	CELL.LONG_IO_V[1]
0	1	0	1	1	0	CELL.DEC_V[2]
0	1	1	0	1	1	CELL.DOUBLE_IO_E2[3]
0	1	1	1	1	0	CELL.OUT_IO_WE_I2[1]
1	1	0	1	1	1	CELL.DOUBLE_IO_E2[2]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_E1 switchbox INT muxes IMUX_TBUF_T[0]
Bits						Destination
MAIN[17][0]	MAIN[19][0]	MAIN[20][0]	MAIN[20][1]	MAIN[19][1]	MAIN[18][0]	CELL.IMUX_TBUF_T[0]
						Source
0	0	0	1	1	1	CELL.TIE_1
0	0	1	1	1	1	CELL.TIE_0
0	1	0	0	1	1	CELL.DOUBLE_IO_E2[0]
0	1	0	1	0	1	CELL.LONG_IO_V[3]
0	1	0	1	1	0	CELL.DEC_V[3]
0	1	1	0	1	1	CELL.DOUBLE_IO_E1[0]
0	1	1	1	0	1	CELL.LONG_IO_V[2]
0	1	1	1	1	0	CELL.DEC_V[0]
1	1	0	1	1	1	CELL.DOUBLE_IO_E2[1]
1	1	1	1	1	1	CELL.DOUBLE_IO_E1[1]

xc4000h IO_E1 switchbox INT muxes IMUX_TBUF_T[1]
Bits						Destination
MAIN[15][0]	MAIN[17][1]	MAIN[15][1]	MAIN[18][1]	MAIN[16][0]	MAIN[16][1]	CELL.IMUX_TBUF_T[1]
						Source
0	0	0	1	1	1	CELL.TIE_1
0	0	1	1	1	1	CELL.TIE_0
0	1	0	0	1	1	CELL.DOUBLE_IO_E1[1]
0	1	0	1	0	1	CELL.LONG_IO_V[2]
0	1	0	1	1	0	CELL.DEC_V[0]
0	1	1	0	1	1	CELL.DOUBLE_IO_E2[1]
0	1	1	1	0	1	CELL.LONG_IO_V[3]
0	1	1	1	1	0	CELL.DEC_V[3]
1	1	0	1	1	1	CELL.DOUBLE_IO_E1[0]
1	1	1	1	1	1	CELL.DOUBLE_IO_E2[0]

xc4000h IO_E1 switchbox INT muxes IMUX_IO_O1[0]
Bits						Destination
MAIN[5][9]	MAIN[5][8]	MAIN[7][8]	MAIN[7][9]	MAIN[6][9]	MAIN[6][8]	CELL.IMUX_IO_O1[0]
						Source
0	0	0	1	1	1	CELL.DEC_V[3]
0	0	1	0	1	1	CELL.DEC_V[2]
0	0	1	1	0	1	CELL.DEC_V[1]
0	0	1	1	1	0	CELL.DEC_V[0]
0	1	1	1	1	1	CELL.DOUBLE_H0[1]
1	0	0	1	1	1	CELL.DOUBLE_H1[0]
1	0	1	0	1	1	CELL.LONG_H[3]
1	0	1	1	0	1	CELL.LONG_H[4]
1	0	1	1	1	0	CELL.LONG_H[5]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_E1 switchbox INT muxes IMUX_IO_O1[1]
Bits						Destination
MAIN[6][0]	MAIN[5][0]	MAIN[9][1]	MAIN[7][0]	MAIN[8][0]	MAIN[9][0]	CELL.IMUX_IO_O1[1]
						Source
0	0	0	1	1	1	CELL.LONG_H[0]
0	0	1	0	1	1	CELL.LONG_H[1]
0	0	1	1	0	1	CELL.DEC_V[2]
0	0	1	1	1	0	CELL.DEC_V[3]
0	1	0	1	1	1	CELL_S.DOUBLE_H1[1]
0	1	1	0	1	1	CELL.LONG_H[2]
0	1	1	1	0	1	CELL.DEC_V[0]
0	1	1	1	1	0	CELL.DEC_V[1]
1	0	1	1	1	1	CELL_S.DOUBLE_H0[0]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_E1 switchbox INT muxes IMUX_IO_OK[0]
Bits								Destination
MAIN[7][6]	MAIN[16][6]	MAIN[8][5]	MAIN[13][6]	MAIN[10][6]	MAIN[11][6]	MAIN[14][6]	MAIN[9][6]	CELL.IMUX_IO_OK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_H[2]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[3]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[4]

xc4000h IO_E1 switchbox INT muxes IMUX_IO_OK[1]
Bits								Destination
MAIN[5][2]	MAIN[7][2]	MAIN[8][2]	MAIN[12][2]	MAIN[6][2]	MAIN[13][2]	MAIN[14][2]	MAIN[9][2]	CELL.IMUX_IO_OK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_S.SINGLE_H[2]
0	1	1	1	1	1	0	1	CELL_S.SINGLE_H[3]
0	1	1	1	1	1	1	0	CELL_S.SINGLE_H[4]
1	1	1	1	1	1	1	1	CELL_S.SINGLE_H[5]

xc4000h IO_E1 switchbox INT muxes IMUX_IO_IK[0]
Bits								Destination
MAIN[5][7]	MAIN[11][7]	MAIN[12][7]	MAIN[9][7]	MAIN[7][7]	MAIN[8][7]	MAIN[10][7]	MAIN[6][7]	CELL.IMUX_IO_IK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_H[3]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[2]

xc4000h IO_E1 switchbox INT muxes IMUX_IO_IK[1]
Bits								Destination
MAIN[5][1]	MAIN[7][1]	MAIN[7][3]	MAIN[11][2]	MAIN[6][1]	MAIN[8][1]	MAIN[10][2]	MAIN[11][3]	CELL.IMUX_IO_IK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_S.SINGLE_H[2]
0	1	1	1	1	1	0	1	CELL_S.SINGLE_H[4]
0	1	1	1	1	1	1	0	CELL_S.SINGLE_H[5]
1	1	1	1	1	1	1	1	CELL_S.SINGLE_H[3]

xc4000h IO_E1 switchbox INT muxes IMUX_IO_T[0]
Bits								Destination
MAIN[20][3]	MAIN[18][4]	MAIN[19][2]	MAIN[21][2]	MAIN[19][3]	MAIN[23][3]	MAIN[20][2]	MAIN[24][3]	CELL.IMUX_IO_T[0]
								Source
0	0	0	1	1	0	1	1	CELL.LONG_IO_V[3]
0	0	0	1	1	1	0	1	CELL.LONG_IO_V[1]
0	0	0	1	1	1	1	0	CELL.GCLK[0]
0	0	1	0	1	0	1	1	CELL.LONG_IO_V[0]
0	0	1	0	1	1	0	1	CELL.DEC_V[2]
0	0	1	1	0	0	1	1	CELL.DOUBLE_IO_E2[1]
0	0	1	1	0	1	0	1	CELL.LONG_IO_V[2]
0	0	1	1	0	1	1	0	CELL.DEC_V[3]
0	1	1	1	1	1	1	1	CELL.TIE_0
1	0	0	1	1	1	1	1	CELL.DOUBLE_IO_E1[0]
1	0	1	0	1	1	1	1	CELL.DOUBLE_IO_E1[1]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_E2[0]

xc4000h IO_E1 switchbox INT muxes IMUX_IO_T[1]
Bits								Destination
MAIN[16][3]	MAIN[14][3]	MAIN[18][2]	MAIN[23][2]	MAIN[17][3]	MAIN[25][2]	MAIN[16][2]	MAIN[15][2]	CELL.IMUX_IO_T[1]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	1	0	1	1	CELL.LONG_IO_V[1]
0	0	1	0	1	1	0	1	CELL.LONG_IO_V[3]
0	0	1	0	1	1	1	0	CELL.GCLK[0]
0	0	1	1	0	0	1	1	CELL.DEC_V[2]
0	0	1	1	0	1	0	1	CELL.LONG_IO_V[0]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_E1[0]
0	1	1	1	0	1	1	1	CELL.DOUBLE_IO_E2[0]
1	0	1	1	1	0	1	1	CELL.DOUBLE_IO_E2[1]
1	0	1	1	1	1	0	1	CELL.LONG_IO_V[2]
1	0	1	1	1	1	1	0	CELL.DEC_V[3]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_E1[1]

xc4000h IO_E1 switchbox INT muxes IMUX_HIO_O[0]
Bits	Destination
MAIN[0][7]	CELL.IMUX_HIO_O[0]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_G1

xc4000h IO_E1 switchbox INT muxes IMUX_HIO_O[1]
Bits	Destination
MAIN[3][6]	CELL.IMUX_HIO_O[1]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_G1

xc4000h IO_E1 switchbox INT muxes IMUX_HIO_O[2]
Bits	Destination
MAIN[4][2]	CELL.IMUX_HIO_O[2]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_F1

xc4000h IO_E1 switchbox INT muxes IMUX_HIO_O[3]
Bits	Destination
MAIN[2][1]	CELL.IMUX_HIO_O[3]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_F1

xc4000h IO_E1 switchbox INT muxes IMUX_HIO_T[0]
Bits	Destination
MAIN[4][8]	CELL.IMUX_HIO_T[0]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_OK[0]

xc4000h IO_E1 switchbox INT muxes IMUX_HIO_T[1]
Bits	Destination
MAIN[1][6]	CELL.IMUX_HIO_T[1]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_IK[0]

xc4000h IO_E1 switchbox INT muxes IMUX_HIO_T[2]
Bits	Destination
MAIN[1][3]	CELL.IMUX_HIO_T[2]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_IK[1]

xc4000h IO_E1 switchbox INT muxes IMUX_HIO_T[3]
Bits	Destination
MAIN[4][1]	CELL.IMUX_HIO_T[3]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_OK[1]

xc4000h IO_E1 switchbox INT muxes OUT_IO_WE_I1[0]
Bits	Destination
MAIN[0][5]	CELL.OUT_IO_WE_I1[0]
	Source
0	CELL.OUT_HIO_I[1]
1	CELL.OUT_HIO_I[0]

xc4000h IO_E1 switchbox INT muxes OUT_IO_WE_I1[1]
Bits	Destination
MAIN[1][4]	CELL.OUT_IO_WE_I1[1]
	Source
0	CELL.OUT_HIO_I[2]
1	CELL.OUT_HIO_I[3]

xc4000h IO_E1 switchbox INT muxes OUT_IO_WE_I2[0]
Bits	Destination
MAIN[3][9]	CELL.OUT_IO_WE_I2[0]
	Source
0	CELL.OUT_HIO_I[0]
1	CELL.OUT_HIO_I[1]

xc4000h IO_E1 switchbox INT muxes OUT_IO_WE_I2[1]
Bits	Destination
MAIN[3][0]	CELL.OUT_IO_WE_I2[1]
	Source
0	CELL.OUT_HIO_I[3]
1	CELL.OUT_HIO_I[2]

Bels TBUF

xc4000h IO_E1 bel TBUF pins
Pin	Direction	TBUF[0]	TBUF[1]
I	in	CELL.IMUX_TBUF_I[0]	CELL.IMUX_TBUF_I[1]
T	in	CELL.IMUX_TBUF_T[0]	CELL.IMUX_TBUF_T[1]
O	bidir	CELL.LONG_H[2]	CELL.LONG_H[3]

xc4000h IO_E1 bel TBUF attribute bits
Attribute	TBUF[0]	TBUF[1]
DRIVE1	!MAIN[25][3]	!MAIN[13][3]

Bels HIO

xc4000h IO_E1 bel HIO pins
Pin	Direction	HIO[0]	HIO[1]	HIO[2]	HIO[3]
O	in	CELL.IMUX_HIO_O[0] invert by !MAIN[1][8]	CELL.IMUX_HIO_O[1] invert by !MAIN[2][6]	CELL.IMUX_HIO_O[2] invert by !MAIN[2][3]	CELL.IMUX_HIO_O[3] invert by !MAIN[3][1]
T	in	CELL.IMUX_HIO_T[0] invert by !MAIN[4][9]	CELL.IMUX_HIO_T[1] invert by !MAIN[0][6]	CELL.IMUX_HIO_T[2] invert by !MAIN[0][3]	CELL.IMUX_HIO_T[3] invert by !MAIN[4][0]
I	out	CELL.OUT_HIO_I[0]	CELL.OUT_HIO_I[1]	CELL.OUT_HIO_I[2]	CELL.OUT_HIO_I[3]

xc4000h IO_E1 bel HIO attribute bits
Attribute	HIO[0]	HIO[1]	HIO[2]	HIO[3]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
ISTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OSTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OMODE	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]
I_INV	!MAIN[2][9]	!MAIN[1][5]	!MAIN[0][4]	!MAIN[2][0]
READBACK_I bit 0	!MAIN[2][8]	!MAIN[0][8]	!MAIN[4][3]	!MAIN[3][3]

xc4000h IO_E1 enum IO_PULL
HIO[0].PULL	MAIN[1][7]	MAIN[2][7]
HIO[1].PULL	MAIN[4][6]	MAIN[8][6]
HIO[2].PULL	MAIN[9][3]	MAIN[3][2]
HIO[3].PULL	MAIN[0][1]	MAIN[1][1]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

xc4000h IO_E1 enum IO_STD
HIO[0].ISTD	MAIN[1][9]
HIO[1].ISTD	MAIN[2][5]
HIO[2].ISTD	MAIN[2][4]
HIO[3].ISTD	MAIN[1][0]
CMOS	0
TTL	1

xc4000h IO_E1 enum IO_STD
HIO[0].OSTD	MAIN[0][9]
HIO[1].OSTD	MAIN[3][5]
HIO[2].OSTD	MAIN[3][4]
HIO[3].OSTD	MAIN[0][0]
CMOS	1
TTL	0

xc4000h IO_E1 enum HIO_OMODE
HIO[0].OMODE	MAIN[3][7]
HIO[1].OMODE	MAIN[4][7]
HIO[2].OMODE	MAIN[1][2]
HIO[3].OMODE	MAIN[0][2]
CAP	1
RES	0

Bels DEC

xc4000h IO_E1 bel DEC pins
Pin	Direction	DEC[0]	DEC[1]	DEC[2]
I	in	CELL.OUT_IO_WE_I1[0]	CELL.IMUX_CLB_C1	CELL.OUT_IO_WE_I1[1]
O1	bidir	CELL.DEC_V[0]	CELL.DEC_V[0]	CELL.DEC_V[0]
O2	bidir	CELL.DEC_V[1]	CELL.DEC_V[1]	CELL.DEC_V[1]
O3	bidir	CELL.DEC_V[2]	CELL.DEC_V[2]	CELL.DEC_V[2]
O4	bidir	CELL.DEC_V[3]	CELL.DEC_V[3]	CELL.DEC_V[3]

xc4000h IO_E1 bel DEC attribute bits
Attribute	DEC[0]	DEC[1]	DEC[2]
O1_P	!MAIN[5][4]	!MAIN[5][6]	MAIN[4][5]
O1_N	MAIN[5][3]	MAIN[5][5]	!MAIN[4][4]
O2_P	!MAIN[10][4]	!MAIN[8][3]	MAIN[9][4]
O2_N	MAIN[10][3]	MAIN[8][4]	!MAIN[9][5]
O3_P	!MAIN[6][3]	!MAIN[6][6]	MAIN[7][4]
O3_N	MAIN[6][4]	MAIN[6][5]	!MAIN[7][5]
O4_P	!MAIN[12][4]	!MAIN[12][5]	MAIN[11][5]
O4_N	MAIN[12][3]	MAIN[12][6]	!MAIN[11][4]

Bels PULLUP

xc4000h IO_E1 bel PULLUP pins
Pin	Direction	PULLUP_TBUF[0]	PULLUP_TBUF[1]
O	bidir	CELL.LONG_H[2]	CELL.LONG_H[3]

xc4000h IO_E1 bel PULLUP attribute bits
Attribute	PULLUP_TBUF[0]	PULLUP_TBUF[1]
ENABLE	!MAIN_S[25][7]	!MAIN[14][7]

Bel wires

xc4000h IO_E1 bel wires
Wire	Pins
CELL.LONG_H[2]	TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]	TBUF[1].O, PULLUP_TBUF[1].O
CELL.DEC_V[0]	DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_V[1]	DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.DEC_V[2]	DEC[0].O3, DEC[1].O3, DEC[2].O3
CELL.DEC_V[3]	DEC[0].O4, DEC[1].O4, DEC[2].O4
CELL.IMUX_CLB_C1	DEC[1].I
CELL.IMUX_TBUF_I[0]	TBUF[0].I
CELL.IMUX_TBUF_I[1]	TBUF[1].I
CELL.IMUX_TBUF_T[0]	TBUF[0].T
CELL.IMUX_TBUF_T[1]	TBUF[1].T
CELL.IMUX_HIO_O[0]	HIO[0].O
CELL.IMUX_HIO_O[1]	HIO[1].O
CELL.IMUX_HIO_O[2]	HIO[2].O
CELL.IMUX_HIO_O[3]	HIO[3].O
CELL.IMUX_HIO_T[0]	HIO[0].T
CELL.IMUX_HIO_T[1]	HIO[1].T
CELL.IMUX_HIO_T[2]	HIO[2].T
CELL.IMUX_HIO_T[3]	HIO[3].T
CELL.OUT_IO_WE_I1[0]	DEC[0].I
CELL.OUT_IO_WE_I1[1]	DEC[2].I
CELL.OUT_HIO_I[0]	HIO[0].I
CELL.OUT_HIO_I[1]	HIO[1].I
CELL.OUT_HIO_I[2]	HIO[2].I
CELL.OUT_HIO_I[3]	HIO[3].I

Bitstream

xc4000h IO_E1 rect MAIN
Bit	Frame
Bit	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7]	INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7]	INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7]	INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5]	-	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0]	INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0	INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_E0[3]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E0[3]	INT: !bipass CELL.DOUBLE_IO_E0[3] = CELL.DOUBLE_IO_E2[3]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E1[3]	INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_E1[3]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E2[3]	INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_E2[3]	-	INT: !pass CELL.SINGLE_H[7] ← CELL.DEC_V[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E0[1]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E0[1]	INT: !bipass CELL.DOUBLE_IO_E0[1] = CELL.DOUBLE_IO_E2[1]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E1[1]	INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E1[1]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E2[1]	INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E2[1]	INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[1]	INT: mux CELL.LONG_IO_V[1] bit 2	INT: mux CELL.IMUX_IO_O1[0] bit 2	INT: mux CELL.IMUX_IO_O1[0] bit 1	INT: mux CELL.IMUX_IO_O1[0] bit 5	HIO[0]: !invert T	INT: mux CELL.OUT_IO_WE_I2[0] bit 0	HIO[0]: ! I_INV	HIO[0]: ISTD bit 0	HIO[0]: OSTD bit 0
B8	-	INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4]	INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6]	INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6]	-	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2]	-	INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0]	-	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0]	-	INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_IO_WE_I1_S1	INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_IO_WE_I1[0]	INT: mux CELL.LONG_IO_V[2] bit 1	INT: mux CELL.LONG_IO_V[2] bit 0	INT: mux CELL.LONG_IO_V[2] bit 2	INT: mux CELL.LONG_IO_V[2] bit 3	INT: mux CELL.LONG_IO_V[3] bit 1	-	INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_IO_V[3]	INT: mux CELL.LONG_IO_V[3] bit 0	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1	INT: mux CELL.LONG_IO_V[1] bit 0	INT: mux CELL.LONG_IO_V[1] bit 1	INT: mux CELL.LONG_IO_V[1] bit 3	INT: mux CELL.DBUF_IO_V[1] bit 1	INT: mux CELL.DBUF_IO_V[1] bit 0	INT: mux CELL.DBUF_IO_V[1] bit 2	INT: mux CELL.DBUF_IO_V[1] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 4	INT: mux CELL.IMUX_HIO_T[0] bit 0	-	HIO[0]: ! READBACK_I bit 0	HIO[0]: !invert O	HIO[1]: ! READBACK_I bit 0
B7	INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5]	INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2]	INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6]	INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3]	INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3]	-	INT: mux CELL.LONG_H[4] bit 1	INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1_S1	INT: mux CELL.LONG_H[4] bit 2	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0]	INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1[0]	INT: mux CELL.LONG_H[5] bit 2	-	INT: !pass CELL.DOUBLE_IO_E0[3] ← CELL.DBUF_IO_V[0]	INT: !pass CELL.DOUBLE_IO_E0[1] ← CELL.DBUF_IO_V[0]	INT: mux CELL.LONG_H[5] bit 3	PULLUP_TBUF[1]: ! ENABLE	INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[1]	INT: mux CELL.IMUX_IO_IK[0] bit 5	INT: mux CELL.IMUX_IO_IK[0] bit 6	INT: mux CELL.IMUX_IO_IK[0] bit 1	INT: mux CELL.IMUX_IO_IK[0] bit 4	INT: mux CELL.IMUX_IO_IK[0] bit 2	INT: mux CELL.IMUX_IO_IK[0] bit 3	INT: mux CELL.IMUX_IO_IK[0] bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 7	HIO[1]: OMODE bit 0	HIO[0]: OMODE bit 0	HIO[0]: PULL bit 0	HIO[0]: PULL bit 1	INT: mux CELL.IMUX_HIO_O[0] bit 0
B6	INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4]	INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4]	INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1]	INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5]	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0]	INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[4]	INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0	INT: mux CELL.LONG_H[4] bit 0	INT: mux CELL.LONG_H[4] bit 3	INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.DOUBLE_IO_E2[3] ← CELL.DBUF_IO_V[1]	INT: mux CELL.LONG_H[5] bit 1	INT: mux CELL.LONG_H[5] bit 0	INT: !pass CELL.DOUBLE_IO_E0[0] ← CELL.DBUF_IO_V[0]	-	INT: !pass CELL.DOUBLE_IO_E0[2] ← CELL.DBUF_IO_V[0]	INT: mux CELL.IMUX_IO_OK[0] bit 6	INT: !pass CELL.DOUBLE_IO_E2[1] ← CELL.DBUF_IO_V[1]	INT: mux CELL.IMUX_IO_OK[0] bit 1	INT: mux CELL.IMUX_IO_OK[0] bit 4	DEC[1]: O4_N	INT: mux CELL.IMUX_IO_OK[0] bit 2	INT: mux CELL.IMUX_IO_OK[0] bit 3	INT: mux CELL.IMUX_IO_OK[0] bit 0	HIO[1]: PULL bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 7	DEC[1]: ! O3_P	DEC[1]: ! O1_P	HIO[1]: PULL bit 1	INT: mux CELL.IMUX_HIO_O[1] bit 0	HIO[1]: !invert O	INT: mux CELL.IMUX_HIO_T[1] bit 0	HIO[1]: !invert T
B5	INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4]	INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5]	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5]	INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1]	INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1]	INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E0[0]	INT: mux CELL.LONG_IO_V[0] bit 0	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E0[0]	INT: !bipass CELL.DOUBLE_IO_E0[0] = CELL.DOUBLE_IO_E2[0]	INT: mux CELL.LONG_IO_V[0] bit 1	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E1[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E1[0]	INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[0]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E2[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E2[0]	INT: !pass CELL.DOUBLE_IO_E2[0] ← CELL.DBUF_IO_V[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E2[2]	INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_E2[2]	DEC[1]: ! O4_P	DEC[2]: O4_P	INT: !pass CELL.SINGLE_H[4] ← CELL.DEC_V[2]	DEC[2]: ! O2_N	INT: mux CELL.IMUX_IO_OK[0] bit 5	DEC[2]: ! O3_N	DEC[1]: O3_N	DEC[1]: O1_N	DEC[2]: O1_P	HIO[1]: OSTD bit 0	HIO[1]: ISTD bit 0	HIO[1]: ! I_INV	INT: mux CELL.OUT_IO_WE_I1[0] bit 0
B4	INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E	INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5]	INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_WE_I2[1]	INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_WE_I2[1]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E	INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4]	INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3]	INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1]	INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_WE_I2[1]	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_WE_I2[0]	INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[3]	INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E	INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[0]	INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_IO_V[2]	INT: mux CELL.IMUX_IO_T[0] bit 6	INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_E0[2]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E0[2]	INT: !bipass CELL.DOUBLE_IO_E0[2] = CELL.DOUBLE_IO_E2[2]	INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_E1[2]	INT: !pass CELL.DOUBLE_IO_E2[2] ← CELL.DBUF_IO_V[1]	DEC[0]: ! O4_P	DEC[2]: ! O4_N	DEC[0]: ! O2_P	DEC[2]: O2_P	DEC[1]: O2_N	DEC[2]: O3_P	DEC[0]: O3_N	DEC[0]: ! O1_P	DEC[2]: ! O1_N	HIO[2]: OSTD bit 0	HIO[2]: ISTD bit 0	INT: mux CELL.OUT_IO_WE_I1[1] bit 0	HIO[2]: ! I_INV
B3	INT: mux CELL.IMUX_CLB_F3 bit 0	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E	INT: mux CELL.IMUX_CLB_C3 bit 1	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5]	INT: mux CELL.IMUX_CLB_G3 bit 0	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1]	INT: mux CELL.IMUX_CLB_F1 bit 3	INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1]	INT: mux CELL.IMUX_CLB_C1 bit 7	INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4]	INT: mux CELL.IMUX_CLB_G1 bit 6	TBUF[0]: ! DRIVE1	INT: mux CELL.IMUX_IO_T[0] bit 0	INT: mux CELL.IMUX_IO_T[0] bit 2	INT: mux CELL.DBUF_IO_V[0] bit 0	INT: mux CELL.DBUF_IO_V[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 7	INT: mux CELL.IMUX_IO_T[0] bit 3	-	INT: mux CELL.IMUX_IO_T[1] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 7	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E1[2]	INT: mux CELL.IMUX_IO_T[1] bit 6	TBUF[1]: ! DRIVE1	DEC[0]: O4_N	INT: mux CELL.IMUX_IO_IK[1] bit 0	DEC[0]: O2_N	HIO[2]: PULL bit 1	DEC[1]: ! O2_P	INT: mux CELL.IMUX_IO_IK[1] bit 5	DEC[0]: ! O3_P	DEC[0]: O1_N	HIO[2]: ! READBACK_I bit 0	HIO[3]: ! READBACK_I bit 0	HIO[2]: !invert O	INT: mux CELL.IMUX_HIO_T[2] bit 0	HIO[2]: !invert T
B2	INT: mux CELL.IMUX_CLB_F3 bit 2	INT: mux CELL.IMUX_CLB_F3 bit 6	INT: mux CELL.IMUX_CLB_F3 bit 8	INT: mux CELL.IMUX_CLB_C3 bit 2	INT: mux CELL.IMUX_CLB_C3 bit 3	INT: mux CELL.IMUX_CLB_G3 bit 1	INT: mux CELL.IMUX_CLB_G3 bit 4	INT: mux CELL.IMUX_CLB_G3 bit 7	INT: mux CELL.IMUX_CLB_F1 bit 0	INT: mux CELL.IMUX_CLB_F1 bit 7	INT: mux CELL.IMUX_CLB_C1 bit 2	INT: mux CELL.IMUX_CLB_C1 bit 1	INT: mux CELL.IMUX_CLB_C1 bit 6	-	INT: mux CELL.IMUX_CLB_G1 bit 0	INT: mux CELL.IMUX_IO_T[1] bit 2	INT: mux CELL.DBUF_IO_V[0] bit 2	INT: mux CELL.IMUX_IO_T[1] bit 4	INT: mux CELL.DBUF_IO_V[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 4	INT: mux CELL.IMUX_IO_T[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 5	INT: mux CELL.IMUX_IO_T[1] bit 5	-	INT: mux CELL.IMUX_IO_T[1] bit 1	INT: mux CELL.IMUX_IO_T[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 1	INT: mux CELL.IMUX_IO_OK[1] bit 2	INT: mux CELL.IMUX_IO_OK[1] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_OK[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 5	INT: mux CELL.IMUX_IO_OK[1] bit 6	INT: mux CELL.IMUX_IO_OK[1] bit 3	INT: mux CELL.IMUX_IO_OK[1] bit 7	INT: mux CELL.IMUX_HIO_O[2] bit 0	HIO[2]: PULL bit 0	-	HIO[2]: OMODE bit 0	HIO[3]: OMODE bit 0
B1	INT: mux CELL.IMUX_CLB_F3 bit 5	INT: mux CELL.IMUX_CLB_F3 bit 3	INT: mux CELL.IMUX_CLB_C3 bit 0	INT: mux CELL.IMUX_CLB_C3 bit 5	INT: mux CELL.IMUX_CLB_C3 bit 6	INT: mux CELL.IMUX_CLB_G3 bit 6	INT: mux CELL.IMUX_CLB_G3 bit 2	INT: mux CELL.IMUX_CLB_G3 bit 5	INT: mux CELL.IMUX_CLB_F1 bit 5	INT: mux CELL.IMUX_CLB_F1 bit 2	INT: mux CELL.IMUX_CLB_C1 bit 5	INT: mux CELL.IMUX_CLB_C1 bit 3	INT: mux CELL.IMUX_CLB_G1 bit 4	INT: mux CELL.IMUX_CLB_G1 bit 3	INT: mux CELL.IMUX_CLB_G1 bit 2	INT: mux CELL.LONG_H[0] bit 1	INT: mux CELL.LONG_H[0] bit 3	INT: mux CELL.IMUX_TBUF_I[0] bit 5	INT: mux CELL.IMUX_TBUF_I[0] bit 0	INT: mux CELL.IMUX_TBUF_I[0] bit 2	INT: mux CELL.IMUX_TBUF_T[0] bit 2	INT: mux CELL.IMUX_TBUF_T[0] bit 1	INT: mux CELL.IMUX_TBUF_T[1] bit 2	INT: mux CELL.IMUX_TBUF_T[1] bit 4	INT: mux CELL.IMUX_TBUF_T[1] bit 0	INT: mux CELL.IMUX_TBUF_T[1] bit 3	INT: mux CELL.IMUX_TBUF_I[1] bit 4	INT: mux CELL.IMUX_TBUF_I[1] bit 0	INT: mux CELL.IMUX_TBUF_I[1] bit 5	INT: mux CELL.LONG_H[1] bit 0	INT: mux CELL.LONG_H[1] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 6	INT: mux CELL.IMUX_IO_IK[1] bit 3	INT: mux CELL.IMUX_IO_IK[1] bit 7	INT: mux CELL.IMUX_HIO_T[3] bit 0	HIO[3]: !invert O	INT: mux CELL.IMUX_HIO_O[3] bit 0	HIO[3]: PULL bit 0	HIO[3]: PULL bit 1
B0	INT: mux CELL.IMUX_CLB_F3 bit 7	INT: mux CELL.IMUX_CLB_F3 bit 1	INT: mux CELL.IMUX_CLB_F3 bit 4	INT: mux CELL.IMUX_CLB_C3 bit 4	INT: mux CELL.IMUX_CLB_C3 bit 7	INT: mux CELL.IMUX_CLB_G3 bit 3	INT: mux CELL.IMUX_CLB_G3 bit 8	INT: mux CELL.IMUX_CLB_F1 bit 6	INT: mux CELL.IMUX_CLB_F1 bit 1	INT: mux CELL.IMUX_CLB_F1 bit 4	INT: mux CELL.IMUX_CLB_C1 bit 0	INT: mux CELL.IMUX_CLB_C1 bit 4	INT: mux CELL.IMUX_CLB_G1 bit 5	INT: mux CELL.IMUX_CLB_G1 bit 1	INT: mux CELL.IMUX_CLB_G1 bit 7	INT: mux CELL.LONG_H[0] bit 0	INT: mux CELL.LONG_H[0] bit 2	INT: mux CELL.IMUX_TBUF_I[0] bit 3	INT: mux CELL.IMUX_TBUF_I[0] bit 1	INT: mux CELL.IMUX_TBUF_I[0] bit 4	INT: mux CELL.IMUX_TBUF_T[0] bit 3	INT: mux CELL.IMUX_TBUF_T[0] bit 4	INT: mux CELL.IMUX_TBUF_T[0] bit 0	INT: mux CELL.IMUX_TBUF_T[0] bit 5	INT: mux CELL.IMUX_TBUF_T[1] bit 1	INT: mux CELL.IMUX_TBUF_T[1] bit 5	INT: mux CELL.IMUX_TBUF_I[1] bit 2	INT: mux CELL.IMUX_TBUF_I[1] bit 1	INT: mux CELL.IMUX_TBUF_I[1] bit 3	INT: mux CELL.LONG_H[1] bit 1	INT: mux CELL.LONG_H[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 0	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.IMUX_IO_O1[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 5	INT: mux CELL.IMUX_IO_O1[1] bit 4	HIO[3]: !invert T	INT: mux CELL.OUT_IO_WE_I2[1] bit 0	HIO[3]: ! I_INV	HIO[3]: ISTD bit 0	HIO[3]: OSTD bit 0

xc4000h IO_E1 rect MAIN_S
Bit	Frame
Bit	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	-	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1]	-	-	-	INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2]	-	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0]	-	INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	PULLUP_TBUF[0]: ! ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

xc4000h IO_E1 rect MAIN_W
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile IO_E1_S

Cells: 3

Switchbox INT

xc4000h IO_E1_S switchbox INT programmable buffers
Destination	Source	Bit
CELL.LONG_H[0]	CELL.SINGLE_V[1]	!MAIN_S[26][11]
CELL.LONG_H[1]	CELL.SINGLE_V[2]	!MAIN_S[30][11]
CELL.LONG_H[2]	CELL.SINGLE_V[3]	!MAIN[27][4]
CELL.LONG_H[3]	CELL.SINGLE_V[4]	!MAIN[27][6]
CELL.LONG_H[4]	CELL.SINGLE_V[5]	!MAIN[38][4]
CELL.LONG_H[5]	CELL.SINGLE_V[6]	!MAIN[40][6]
CELL.LONG_V[0]	CELL.SINGLE_H_E[1]	!MAIN[32][4]
CELL.LONG_V[1]	CELL.SINGLE_H_E[2]	!MAIN[38][8]
CELL.LONG_V[2]	CELL.SINGLE_H_E[3]	!MAIN[34][6]
CELL.LONG_V[3]	CELL.SINGLE_H[4]	!MAIN[34][4]
CELL.LONG_V[4]	CELL.SINGLE_H[5]	!MAIN[31][6]
CELL.LONG_V[5]	CELL.SINGLE_H[6]	!MAIN[35][8]

xc4000h IO_E1_S switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[0]	CELL.DEC_V[0]	!MAIN[18][5]
CELL.SINGLE_H[0]	CELL.OUT_IO_WE_I2_S1	!MAIN[24][4]
CELL.SINGLE_H[1]	CELL.LONG_IO_V[0]	!MAIN[22][4]
CELL.SINGLE_H[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[21][4]
CELL.SINGLE_H[2]	CELL.LONG_IO_V[1]	!MAIN[13][7]
CELL.SINGLE_H[2]	CELL.OUT_IO_WE_I1[0]	!MAIN[21][7]
CELL.SINGLE_H[3]	CELL.DEC_V[1]	!MAIN[9][9]
CELL.SINGLE_H[3]	CELL.OUT_IO_WE_I1_S1	!MAIN[15][8]
CELL.SINGLE_H[4]	CELL.LONG_V[3]	!MAIN[33][4]
CELL.SINGLE_H[4]	CELL.DEC_V[2]	!MAIN[10][5]
CELL.SINGLE_H[4]	CELL.OUT_IO_WE_I2_S1	!MAIN[25][4]
CELL.SINGLE_H[5]	CELL.LONG_V[4]	!MAIN[27][3]
CELL.SINGLE_H[5]	CELL.LONG_IO_V[2]	!MAIN[19][4]
CELL.SINGLE_H[5]	CELL.OUT_IO_WE_I2[0]	!MAIN[20][4]
CELL.SINGLE_H[6]	CELL.LONG_V[5]	!MAIN[34][9]
CELL.SINGLE_H[6]	CELL.LONG_IO_V[3]	!MAIN[17][8]
CELL.SINGLE_H[6]	CELL.OUT_IO_WE_I1[0]	!MAIN[24][8]
CELL.SINGLE_H[7]	CELL.DEC_V[3]	!MAIN[17][9]
CELL.SINGLE_H[7]	CELL.OUT_IO_WE_I1_S1	!MAIN[25][8]
CELL.SINGLE_H_E[1]	CELL.LONG_V[0]	!MAIN[32][5]
CELL.SINGLE_H_E[2]	CELL.LONG_V[1]	!MAIN[40][9]
CELL.SINGLE_H_E[3]	CELL.LONG_V[2]	!MAIN[39][7]
CELL.SINGLE_V[0]	CELL.TIE_0	!MAIN[26][6]
CELL.SINGLE_V[0]	CELL.OUT_IO_WE_I2[0]	!MAIN[28][4]
CELL.SINGLE_V[1]	CELL.LONG_H[0]	!MAIN_S[28][11]
CELL.SINGLE_V[1]	CELL.OUT_IO_WE_I2[1]	!MAIN[29][4]
CELL.SINGLE_V[2]	CELL.LONG_H[1]	!MAIN_S[34][11]
CELL.SINGLE_V[2]	CELL.OUT_CLB_Y_E	!MAIN[30][4]
CELL.SINGLE_V[3]	CELL.LONG_H[2]	!MAIN_S[33][12]
CELL.SINGLE_V[3]	CELL.OUT_CLB_YQ_E	!MAIN[35][4]
CELL.SINGLE_V[4]	CELL.LONG_H[3]	!MAIN[26][7]
CELL.SINGLE_V[4]	CELL.OUT_IO_WE_I2[0]	!MAIN[39][3]
CELL.SINGLE_V[5]	CELL.LONG_H[4]	!MAIN[40][5]
CELL.SINGLE_V[5]	CELL.OUT_IO_WE_I2[1]	!MAIN[36][4]
CELL.SINGLE_V[6]	CELL.LONG_H[5]	!MAIN[40][7]
CELL.SINGLE_V[6]	CELL.OUT_CLB_Y_E	!MAIN[39][4]
CELL.SINGLE_V[7]	CELL.TIE_0	!MAIN[26][9]
CELL.SINGLE_V[7]	CELL.OUT_CLB_YQ_E	!MAIN[38][3]
CELL.DOUBLE_H0[0]	CELL.OUT_IO_WE_I1[0]	!MAIN[20][7]
CELL.DOUBLE_H0[1]	CELL.OUT_IO_WE_I2_S1	!MAIN[23][4]
CELL.DOUBLE_H1[0]	CELL.OUT_IO_WE_I1_S1	!MAIN[23][7]
CELL.DOUBLE_H1[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[23][6]
CELL.DOUBLE_V0[0]	CELL.OUT_CLB_YQ_E	!MAIN[26][4]
CELL.DOUBLE_V0[1]	CELL.OUT_IO_WE_I2[1]	!MAIN[37][4]
CELL.DOUBLE_V1[0]	CELL.OUT_CLB_Y_E	!MAIN[31][4]
CELL.DOUBLE_V1[1]	CELL.OUT_IO_WE_I2[0]	!MAIN[40][4]
CELL.DOUBLE_IO_E0[0]	CELL.DBUF_IO_V[0]	!MAIN[19][6]
CELL.DOUBLE_IO_E0[1]	CELL.DBUF_IO_V[0]	!MAIN[16][7]
CELL.DOUBLE_IO_E0[2]	CELL.DBUF_IO_V[0]	!MAIN[17][6]
CELL.DOUBLE_IO_E0[3]	CELL.DBUF_IO_V[0]	!MAIN[17][7]
CELL.DOUBLE_IO_E2[0]	CELL.DBUF_IO_V[1]	!MAIN[15][5]
CELL.DOUBLE_IO_E2[1]	CELL.DBUF_IO_V[1]	!MAIN[15][6]
CELL.DOUBLE_IO_E2[2]	CELL.DBUF_IO_V[1]	!MAIN[13][4]
CELL.DOUBLE_IO_E2[3]	CELL.DBUF_IO_V[1]	!MAIN[22][6]

xc4000h IO_E1_S switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.SINGLE_H_E[0]	!MAIN[28][6]
CELL.SINGLE_H[0]	CELL.SINGLE_V[0]	!MAIN[27][5]
CELL.SINGLE_H[0]	CELL.SINGLE_V_S[0]	!MAIN[30][3]
CELL.SINGLE_H[0]	CELL.DOUBLE_IO_E1[0]	!MAIN[19][5]
CELL.SINGLE_H[1]	CELL.SINGLE_H_E[1]	!MAIN[30][5]
CELL.SINGLE_H[1]	CELL.SINGLE_V[1]	!MAIN[29][5]
CELL.SINGLE_H[1]	CELL.SINGLE_V_S[1]	!MAIN[29][3]
CELL.SINGLE_H[1]	CELL.DOUBLE_IO_E0[0]	!MAIN[25][5]
CELL.SINGLE_H[1]	CELL.DOUBLE_IO_E2[0]	!MAIN[16][5]
CELL.SINGLE_H[2]	CELL.SINGLE_H_E[2]	!MAIN[32][8]
CELL.SINGLE_H[2]	CELL.SINGLE_V[2]	!MAIN[31][8]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[2]	!MAIN[33][8]
CELL.SINGLE_H[2]	CELL.DOUBLE_IO_E1[1]	!MAIN[12][9]
CELL.SINGLE_H[3]	CELL.SINGLE_H_E[3]	!MAIN[31][7]
CELL.SINGLE_H[3]	CELL.SINGLE_V[3]	!MAIN[28][7]
CELL.SINGLE_H[3]	CELL.SINGLE_V_S[3]	!MAIN[30][7]
CELL.SINGLE_H[3]	CELL.DOUBLE_IO_E0[1]	!MAIN[16][9]
CELL.SINGLE_H[3]	CELL.DOUBLE_IO_E2[1]	!MAIN[10][9]
CELL.SINGLE_H[4]	CELL.SINGLE_H_E[4]	!MAIN[36][6]
CELL.SINGLE_H[4]	CELL.SINGLE_V[4]	!MAIN[39][6]
CELL.SINGLE_H[4]	CELL.SINGLE_V_S[4]	!MAIN[35][6]
CELL.SINGLE_H[4]	CELL.DOUBLE_IO_E1[2]	!MAIN[14][4]
CELL.SINGLE_H[5]	CELL.SINGLE_H_E[5]	!MAIN[35][5]
CELL.SINGLE_H[5]	CELL.SINGLE_V[5]	!MAIN[36][3]
CELL.SINGLE_H[5]	CELL.SINGLE_V_S[5]	!MAIN[37][5]
CELL.SINGLE_H[5]	CELL.DOUBLE_IO_E0[2]	!MAIN[17][4]
CELL.SINGLE_H[5]	CELL.DOUBLE_IO_E2[2]	!MAIN[13][5]
CELL.SINGLE_H[6]	CELL.SINGLE_H_E[6]	!MAIN[35][7]
CELL.SINGLE_H[6]	CELL.SINGLE_V[6]	!MAIN[36][8]
CELL.SINGLE_H[6]	CELL.SINGLE_V_S[6]	!MAIN[36][7]
CELL.SINGLE_H[6]	CELL.DOUBLE_IO_E1[3]	!MAIN[21][9]
CELL.SINGLE_H[7]	CELL.SINGLE_H_E[7]	!MAIN[38][9]
CELL.SINGLE_H[7]	CELL.SINGLE_V[7]	!MAIN[35][9]
CELL.SINGLE_H[7]	CELL.SINGLE_V_S[7]	!MAIN[37][8]
CELL.SINGLE_H[7]	CELL.DOUBLE_IO_E0[3]	!MAIN[25][9]
CELL.SINGLE_H[7]	CELL.DOUBLE_IO_E2[3]	!MAIN[19][9]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V[0]	!MAIN[26][5]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V_S[0]	!MAIN[28][5]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V[1]	!MAIN[30][6]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V_S[1]	!MAIN[31][5]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V[2]	!MAIN[31][9]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V_S[2]	!MAIN[32][9]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V[3]	!MAIN[32][7]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V_S[3]	!MAIN[33][7]
CELL.SINGLE_H_E[4]	CELL.SINGLE_V[4]	!MAIN[39][8]
CELL.SINGLE_H_E[4]	CELL.SINGLE_V_S[4]	!MAIN[37][6]
CELL.SINGLE_H_E[5]	CELL.SINGLE_V[5]	!MAIN[36][5]
CELL.SINGLE_H_E[5]	CELL.SINGLE_V_S[5]	!MAIN[38][5]
CELL.SINGLE_H_E[6]	CELL.SINGLE_V[6]	!MAIN[34][7]
CELL.SINGLE_H_E[6]	CELL.SINGLE_V_S[6]	!MAIN[37][7]
CELL.SINGLE_H_E[7]	CELL.SINGLE_V[7]	!MAIN[37][9]
CELL.SINGLE_H_E[7]	CELL.SINGLE_V_S[7]	!MAIN[39][9]
CELL.SINGLE_V[0]	CELL.SINGLE_V_S[0]	!MAIN[29][6]
CELL.SINGLE_V[1]	CELL.SINGLE_V_S[1]	!MAIN[31][3]
CELL.SINGLE_V[2]	CELL.SINGLE_V_S[2]	!MAIN[30][9]
CELL.SINGLE_V[3]	CELL.SINGLE_V_S[3]	!MAIN[27][7]
CELL.SINGLE_V[4]	CELL.SINGLE_V_S[4]	!MAIN[38][6]
CELL.SINGLE_V[5]	CELL.SINGLE_V_S[5]	!MAIN[39][5]
CELL.SINGLE_V[6]	CELL.SINGLE_V_S[6]	!MAIN[38][7]
CELL.SINGLE_V[7]	CELL.SINGLE_V_S[7]	!MAIN[36][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_H2[0]	!MAIN[29][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_V0[0]	!MAIN[27][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_V2[0]	!MAIN[28][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_E0[1]	!MAIN[15][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_E1[1]	!MAIN[13][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_E2[1]	!MAIN[11][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_H2[1]	!MAIN[33][6]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_V0[1]	!MAIN[32][6]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_V2[1]	!MAIN[33][3]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_E0[2]	!MAIN[16][4]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_E1[2]	!MAIN[15][3]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_E2[2]	!MAIN[14][5]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_E0[0]	!MAIN[23][5]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_E1[0]	!MAIN[20][5]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_E2[0]	!MAIN[17][5]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_E0[3]	!MAIN[24][9]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_E1[3]	!MAIN[22][9]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_E2[3]	!MAIN[20][9]
CELL.DOUBLE_H2[0]	CELL.DOUBLE_V0[0]	!MAIN[29][7]
CELL.DOUBLE_H2[0]	CELL.DOUBLE_V2[0]	!MAIN[29][8]
CELL.DOUBLE_H2[1]	CELL.DOUBLE_V0[1]	!MAIN[33][5]
CELL.DOUBLE_H2[1]	CELL.DOUBLE_V2[1]	!MAIN[34][5]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_V2[0]	!MAIN[27][8]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_V2[1]	!MAIN[34][3]
CELL.DOUBLE_IO_E0[0]	CELL.DOUBLE_IO_E2[0]	!MAIN[22][5]
CELL.DOUBLE_IO_E0[1]	CELL.DOUBLE_IO_E2[1]	!MAIN[14][9]
CELL.DOUBLE_IO_E0[2]	CELL.DOUBLE_IO_E2[2]	!MAIN[15][4]
CELL.DOUBLE_IO_E0[3]	CELL.DOUBLE_IO_E2[3]	!MAIN[23][9]

xc4000h IO_E1_S switchbox INT muxes DBUF_IO_V[0]
Bits				Destination
MAIN[21][3]	MAIN[24][2]	MAIN[22][2]	MAIN[22][3]	CELL.DBUF_IO_V[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_E2[0]
0	1	0	1	CELL.DOUBLE_IO_E2[1]
0	1	1	0	CELL.DOUBLE_IO_E2[3]
1	1	1	1	CELL.DOUBLE_IO_E2[2]

xc4000h IO_E1_S switchbox INT muxes DBUF_IO_V[1]
Bits				Destination
MAIN[8][8]	MAIN[9][8]	MAIN[11][8]	MAIN[10][8]	CELL.DBUF_IO_V[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_E0[1]
0	1	0	1	CELL.DOUBLE_IO_E0[2]
0	1	1	0	CELL.DOUBLE_IO_E0[3]
1	1	1	1	CELL.DOUBLE_IO_E0[0]

xc4000h IO_E1_S switchbox INT muxes LONG_H[0]
Bits				Destination
MAIN[24][1]	MAIN[24][0]	MAIN[25][1]	MAIN[25][0]	CELL.LONG_H[0]
				Source
0	0	0	1	CELL.LONG_IO_V[0]
0	0	1	0	CELL.DEC_V[3]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000h IO_E1_S switchbox INT muxes LONG_H[1]
Bits				Destination
MAIN[10][1]	MAIN[10][0]	MAIN[11][0]	MAIN[11][1]	CELL.LONG_H[1]
				Source
0	0	0	1	CELL.LONG_IO_V[1]
0	0	1	0	CELL.DEC_V[2]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000h IO_E1_S switchbox INT muxes LONG_H[4]
Bits				Destination
MAIN[24][6]	MAIN[22][7]	MAIN[24][7]	MAIN[25][6]	CELL.LONG_H[4]
				Source
0	0	0	1	CELL.LONG_IO_V[2]
0	0	1	0	CELL.DEC_V[1]
0	1	1	1	CELL.OUT_IO_WE_I2[0]
1	1	1	1	off

xc4000h IO_E1_S switchbox INT muxes LONG_H[5]
Bits				Destination
MAIN[15][7]	MAIN[19][7]	MAIN[21][6]	MAIN[20][6]	CELL.LONG_H[5]
				Source
0	0	0	1	CELL.LONG_IO_V[3]
0	0	1	0	CELL.DEC_V[0]
0	1	1	1	CELL.OUT_IO_WE_I2[0]
1	1	1	1	off

xc4000h IO_E1_S switchbox INT muxes LONG_IO_V[0]
Bits		Destination
MAIN[21][5]	MAIN[24][5]	CELL.LONG_IO_V[0]
		Source
0	0	CELL.LONG_H[0]
0	1	CELL.SINGLE_H[1]
1	1	off

xc4000h IO_E1_S switchbox INT muxes LONG_IO_V[1]
Bits				Destination
MAIN[12][8]	MAIN[8][9]	MAIN[13][8]	MAIN[14][8]	CELL.LONG_IO_V[1]
				Source
0	0	0	1	CELL.LONG_H[1]
0	0	1	0	CELL.LONG_H[3]
0	1	1	1	CELL.SINGLE_H[2]
1	1	1	1	off

xc4000h IO_E1_S switchbox INT muxes LONG_IO_V[2]
Bits				Destination
MAIN[20][8]	MAIN[21][8]	MAIN[23][8]	MAIN[22][8]	CELL.LONG_IO_V[2]
				Source
0	0	0	1	CELL.LONG_H[2]
0	0	1	0	CELL.LONG_H[4]
0	1	1	1	CELL.SINGLE_H[5]
1	1	1	1	off

xc4000h IO_E1_S switchbox INT muxes LONG_IO_V[3]
Bits		Destination
MAIN[19][8]	MAIN[16][8]	CELL.LONG_IO_V[3]
		Source
0	0	CELL.LONG_H[5]
0	1	CELL.SINGLE_H[6]
1	1	off

xc4000h IO_E1_S switchbox INT muxes IMUX_CLB_F1
Bits								Destination
MAIN[31][2]	MAIN[33][0]	MAIN[32][1]	MAIN[31][0]	MAIN[32][3]	MAIN[31][1]	MAIN[32][0]	MAIN[32][2]	CELL.IMUX_CLB_F1
								Source
0	0	1	0	0	1	1	1	CELL.SINGLE_V[3]
0	0	1	0	1	0	1	1	CELL.LONG_V[4]
0	0	1	0	1	1	1	0	CELL.SINGLE_V[7]
0	0	1	1	1	1	1	1	CELL.SINGLE_V[0]
0	1	0	0	0	1	1	1	CELL.LONG_V[3]
0	1	0	0	1	0	1	1	CELL.DOUBLE_V0[1]
0	1	0	0	1	1	1	0	CELL.LONG_V[0]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[1]
0	1	1	0	0	1	0	1	CELL.SINGLE_V[5]
0	1	1	0	1	0	0	1	CELL.LONG_V[1]
0	1	1	0	1	1	0	0	CELL.SINGLE_V[6]
0	1	1	1	1	1	0	1	CELL.DOUBLE_V1[1]
1	1	1	0	0	1	1	1	CELL.DOUBLE_V1[0]
1	1	1	0	1	0	1	1	CELL.SINGLE_V[4]
1	1	1	0	1	1	1	0	CELL.DOUBLE_V0[0]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[2]

xc4000h IO_E1_S switchbox INT muxes IMUX_CLB_F3
Bits									Destination
MAIN[38][2]	MAIN[40][0]	MAIN[39][2]	MAIN[40][1]	MAIN[38][0]	MAIN[39][1]	MAIN[40][2]	MAIN[39][0]	MAIN[40][3]	CELL.IMUX_CLB_F3
									Source
0	0	0	0	1	1	1	1	1	CELL.SINGLE_V[0]
0	0	0	1	1	1	0	1	1	CELL.DOUBLE_V0[0]
0	0	0	1	1	1	1	0	1	CELL.LONG_V[2]
0	0	1	1	1	1	1	1	1	CELL.SINGLE_V[3]
0	1	0	0	0	1	1	1	1	CELL.DOUBLE_V1[1]
0	1	0	0	1	0	1	1	1	CELL.LONG_V[1]
0	1	0	1	0	1	0	1	1	CELL.DOUBLE_V0[1]
0	1	0	1	0	1	1	0	1	CELL.LONG_V[5]
0	1	0	1	1	0	0	1	1	CELL.SINGLE_V[4]
0	1	0	1	1	0	1	0	1	CELL.LONG_V[4]
0	1	0	1	1	1	1	1	0	CELL.GCLK[0]
0	1	1	1	0	1	1	1	1	CELL.SINGLE_V[1]
0	1	1	1	1	0	1	1	1	CELL.SINGLE_V[2]
1	1	0	0	1	1	1	1	1	CELL.SINGLE_V[6]
1	1	0	1	1	1	0	1	1	CELL.DOUBLE_V1[0]
1	1	0	1	1	1	1	0	1	CELL.SINGLE_V[5]
1	1	1	1	1	1	1	1	1	CELL.SINGLE_V[7]

xc4000h IO_E1_S switchbox INT muxes IMUX_CLB_G1
Bits								Destination
MAIN[26][0]	MAIN[26][3]	MAIN[28][0]	MAIN[28][1]	MAIN[27][1]	MAIN[26][1]	MAIN[27][0]	MAIN[26][2]	CELL.IMUX_CLB_G1
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_V[0]
0	0	0	1	0	1	1	1	CELL.SINGLE_V[2]
0	0	0	1	1	1	0	1	CELL.SINGLE_V[4]
0	0	1	0	1	0	1	1	CELL.LONG_V[4]
0	0	1	0	1	1	1	0	CELL.LONG_V[3]
0	0	1	1	0	0	1	1	CELL.SINGLE_V[1]
0	0	1	1	0	1	1	0	CELL.DOUBLE_V1[0]
0	0	1	1	1	0	0	1	CELL.DOUBLE_V0[1]
0	0	1	1	1	1	0	0	CELL.LONG_V[0]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[3]
0	1	1	1	0	1	1	1	CELL.DOUBLE_V0[0]
0	1	1	1	1	1	0	1	CELL.SINGLE_V[7]
1	0	0	1	1	1	1	1	CELL.DOUBLE_V1[1]
1	0	1	1	1	0	1	1	CELL.LONG_V[1]
1	0	1	1	1	1	1	0	CELL.SINGLE_V[5]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[6]

xc4000h IO_E1_S switchbox INT muxes IMUX_CLB_G3
Bits									Destination
MAIN[34][0]	MAIN[33][2]	MAIN[35][1]	MAIN[33][1]	MAIN[34][2]	MAIN[35][0]	MAIN[34][1]	MAIN[35][2]	MAIN[35][3]	CELL.IMUX_CLB_G3
									Source
0	0	0	1	1	1	1	1	1	CELL.SPECIAL_CLB_CIN
0	0	1	0	0	1	1	1	1	CELL.SINGLE_V[0]
0	0	1	0	1	0	1	1	1	CELL.SINGLE_V[2]
0	0	1	0	1	1	1	0	1	CELL.SINGLE_V[4]
0	0	1	1	0	1	0	1	1	CELL.LONG_V[4]
0	0	1	1	0	1	1	1	0	CELL.LONG_V[2]
0	0	1	1	1	0	0	1	1	CELL.SINGLE_V[1]
0	0	1	1	1	0	1	1	0	CELL.SINGLE_V[6]
0	0	1	1	1	1	0	0	1	CELL.DOUBLE_V0[1]
0	0	1	1	1	1	1	0	0	CELL.LONG_V[5]
0	1	1	1	0	1	1	1	1	CELL.DOUBLE_V0[0]
0	1	1	1	1	0	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	1	1	1	0	1	CELL.DOUBLE_V1[0]
1	0	1	0	1	1	1	1	1	CELL.DOUBLE_V1[1]
1	0	1	1	1	1	0	1	1	CELL.LONG_V[1]
1	0	1	1	1	1	1	1	0	CELL.SINGLE_V[7]
1	1	1	1	1	1	1	1	1	CELL.SINGLE_V[3]

xc4000h IO_E1_S switchbox INT muxes IMUX_CLB_C1
Bits								Destination
MAIN[28][3]	MAIN[28][2]	MAIN[30][1]	MAIN[29][0]	MAIN[29][1]	MAIN[30][2]	MAIN[29][2]	MAIN[30][0]	CELL.IMUX_CLB_C1
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_V[0]
0	0	0	1	0	1	1	1	CELL.SINGLE_V[1]
0	0	1	0	1	0	1	1	CELL.DOUBLE_V0[0]
0	0	1	0	1	1	0	1	CELL.DOUBLE_V1[0]
0	0	1	1	0	0	1	1	CELL.SINGLE_V[3]
0	0	1	1	0	1	0	1	CELL.SINGLE_V[7]
0	0	1	1	1	0	1	0	CELL.LONG_V[2]
0	0	1	1	1	1	0	0	CELL.LONG_V[3]
0	1	1	0	1	1	1	1	CELL.DOUBLE_V1[1]
0	1	1	1	0	1	1	1	CELL.SINGLE_V[2]
1	0	0	1	1	1	1	1	CELL.DOUBLE_V0[1]
1	0	1	1	1	0	1	1	CELL.SINGLE_V[5]
1	0	1	1	1	1	0	1	CELL.SINGLE_V[6]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[4]

xc4000h IO_E1_S switchbox INT muxes IMUX_CLB_C3
Bits								Destination
MAIN[36][0]	MAIN[36][1]	MAIN[37][1]	MAIN[37][0]	MAIN[36][2]	MAIN[37][2]	MAIN[37][3]	MAIN[38][1]	CELL.IMUX_CLB_C3
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_V[0]
0	0	0	1	0	1	1	1	CELL.SINGLE_V[2]
0	0	0	1	1	1	1	0	CELL.GCLK[2]
0	0	1	0	1	0	1	1	CELL.SINGLE_V[3]
0	0	1	0	1	1	0	1	CELL.SINGLE_V[7]
0	0	1	1	0	0	1	1	CELL.DOUBLE_V0[0]
0	0	1	1	0	1	0	1	CELL.DOUBLE_V1[0]
0	0	1	1	1	0	1	0	CELL.LONG_V[3]
0	0	1	1	1	1	0	0	CELL.LONG_V[2]
0	1	1	0	1	1	1	1	CELL.DOUBLE_V1[1]
0	1	1	1	0	1	1	1	CELL.SINGLE_V[1]
1	0	0	1	1	1	1	1	CELL.DOUBLE_V0[1]
1	0	1	1	1	0	1	1	CELL.SINGLE_V[5]
1	0	1	1	1	1	0	1	CELL.SINGLE_V[6]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[4]

xc4000h IO_E1_S switchbox INT muxes IMUX_TBUF_I[0]
Bits						Destination
MAIN[23][1]	MAIN[21][0]	MAIN[23][0]	MAIN[21][1]	MAIN[22][0]	MAIN[22][1]	CELL.IMUX_TBUF_I[0]
						Source
0	0	0	1	1	1	CELL.DOUBLE_IO_E2[2]
0	0	1	0	1	1	CELL.OUT_IO_WE_I2[0]
0	0	1	1	0	1	CELL.LONG_IO_V[2]
0	0	1	1	1	0	CELL.DEC_V[1]
0	1	1	1	1	1	CELL.DOUBLE_IO_E1[2]
1	0	0	1	1	1	CELL.DOUBLE_IO_E1[3]
1	0	1	0	1	1	CELL.DOUBLE_IO_E2[3]
1	0	1	1	0	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_E1_S switchbox INT muxes IMUX_TBUF_I[1]
Bits						Destination
MAIN[12][1]	MAIN[14][1]	MAIN[12][0]	MAIN[14][0]	MAIN[13][0]	MAIN[13][1]	CELL.IMUX_TBUF_I[1]
						Source
0	0	0	1	1	1	CELL.DOUBLE_IO_E1[2]
0	0	1	1	1	1	CELL.DOUBLE_IO_E1[3]
0	1	0	0	1	1	CELL.OUT_IO_WE_I2[0]
0	1	0	1	0	1	CELL.LONG_IO_V[1]
0	1	0	1	1	0	CELL.DEC_V[2]
0	1	1	0	1	1	CELL.DOUBLE_IO_E2[3]
0	1	1	1	1	0	CELL.OUT_IO_WE_I2[1]
1	1	0	1	1	1	CELL.DOUBLE_IO_E2[2]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_E1_S switchbox INT muxes IMUX_TBUF_T[0]
Bits						Destination
MAIN[17][0]	MAIN[19][0]	MAIN[20][0]	MAIN[20][1]	MAIN[19][1]	MAIN[18][0]	CELL.IMUX_TBUF_T[0]
						Source
0	0	0	1	1	1	CELL.TIE_1
0	0	1	1	1	1	CELL.TIE_0
0	1	0	0	1	1	CELL.DOUBLE_IO_E2[0]
0	1	0	1	0	1	CELL.LONG_IO_V[3]
0	1	0	1	1	0	CELL.DEC_V[3]
0	1	1	0	1	1	CELL.DOUBLE_IO_E1[0]
0	1	1	1	0	1	CELL.LONG_IO_V[2]
0	1	1	1	1	0	CELL.DEC_V[0]
1	1	0	1	1	1	CELL.DOUBLE_IO_E2[1]
1	1	1	1	1	1	CELL.DOUBLE_IO_E1[1]

xc4000h IO_E1_S switchbox INT muxes IMUX_TBUF_T[1]
Bits						Destination
MAIN[15][0]	MAIN[17][1]	MAIN[15][1]	MAIN[18][1]	MAIN[16][0]	MAIN[16][1]	CELL.IMUX_TBUF_T[1]
						Source
0	0	0	1	1	1	CELL.TIE_1
0	0	1	1	1	1	CELL.TIE_0
0	1	0	0	1	1	CELL.DOUBLE_IO_E1[1]
0	1	0	1	0	1	CELL.LONG_IO_V[2]
0	1	0	1	1	0	CELL.DEC_V[0]
0	1	1	0	1	1	CELL.DOUBLE_IO_E2[1]
0	1	1	1	0	1	CELL.LONG_IO_V[3]
0	1	1	1	1	0	CELL.DEC_V[3]
1	1	0	1	1	1	CELL.DOUBLE_IO_E1[0]
1	1	1	1	1	1	CELL.DOUBLE_IO_E2[0]

xc4000h IO_E1_S switchbox INT muxes IMUX_IO_O1[0]
Bits						Destination
MAIN[5][9]	MAIN[5][8]	MAIN[7][8]	MAIN[7][9]	MAIN[6][9]	MAIN[6][8]	CELL.IMUX_IO_O1[0]
						Source
0	0	0	1	1	1	CELL.DEC_V[3]
0	0	1	0	1	1	CELL.DEC_V[2]
0	0	1	1	0	1	CELL.DEC_V[1]
0	0	1	1	1	0	CELL.DEC_V[0]
0	1	1	1	1	1	CELL.DOUBLE_H0[1]
1	0	0	1	1	1	CELL.DOUBLE_H1[0]
1	0	1	0	1	1	CELL.LONG_H[3]
1	0	1	1	0	1	CELL.LONG_H[4]
1	0	1	1	1	0	CELL.LONG_H[5]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_E1_S switchbox INT muxes IMUX_IO_O1[1]
Bits						Destination
MAIN[6][0]	MAIN[5][0]	MAIN[9][1]	MAIN[7][0]	MAIN[8][0]	MAIN[9][0]	CELL.IMUX_IO_O1[1]
						Source
0	0	0	1	1	1	CELL.LONG_H[0]
0	0	1	0	1	1	CELL.LONG_H[1]
0	0	1	1	0	1	CELL.DEC_V[2]
0	0	1	1	1	0	CELL.DEC_V[3]
0	1	0	1	1	1	CELL_S.DOUBLE_H1[1]
0	1	1	0	1	1	CELL.LONG_H[2]
0	1	1	1	0	1	CELL.DEC_V[0]
0	1	1	1	1	0	CELL.DEC_V[1]
1	0	1	1	1	1	CELL_S.DOUBLE_H0[0]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_E1_S switchbox INT muxes IMUX_IO_OK[0]
Bits								Destination
MAIN[7][6]	MAIN[16][6]	MAIN[8][5]	MAIN[13][6]	MAIN[10][6]	MAIN[11][6]	MAIN[14][6]	MAIN[9][6]	CELL.IMUX_IO_OK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_H[2]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[3]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[4]

xc4000h IO_E1_S switchbox INT muxes IMUX_IO_OK[1]
Bits								Destination
MAIN[5][2]	MAIN[7][2]	MAIN[8][2]	MAIN[12][2]	MAIN[6][2]	MAIN[13][2]	MAIN[14][2]	MAIN[9][2]	CELL.IMUX_IO_OK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_S.SINGLE_H[2]
0	1	1	1	1	1	0	1	CELL_S.SINGLE_H[3]
0	1	1	1	1	1	1	0	CELL_S.SINGLE_H[4]
1	1	1	1	1	1	1	1	CELL_S.SINGLE_H[5]

xc4000h IO_E1_S switchbox INT muxes IMUX_IO_IK[0]
Bits								Destination
MAIN[5][7]	MAIN[11][7]	MAIN[12][7]	MAIN[9][7]	MAIN[7][7]	MAIN[8][7]	MAIN[10][7]	MAIN[6][7]	CELL.IMUX_IO_IK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_H[3]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[2]

xc4000h IO_E1_S switchbox INT muxes IMUX_IO_IK[1]
Bits								Destination
MAIN[5][1]	MAIN[7][1]	MAIN[7][3]	MAIN[11][2]	MAIN[6][1]	MAIN[8][1]	MAIN[10][2]	MAIN[11][3]	CELL.IMUX_IO_IK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_S.SINGLE_H[2]
0	1	1	1	1	1	0	1	CELL_S.SINGLE_H[4]
0	1	1	1	1	1	1	0	CELL_S.SINGLE_H[5]
1	1	1	1	1	1	1	1	CELL_S.SINGLE_H[3]

xc4000h IO_E1_S switchbox INT muxes IMUX_IO_T[0]
Bits								Destination
MAIN[20][3]	MAIN[18][4]	MAIN[19][2]	MAIN[21][2]	MAIN[19][3]	MAIN[23][3]	MAIN[20][2]	MAIN[24][3]	CELL.IMUX_IO_T[0]
								Source
0	0	0	1	1	0	1	1	CELL.LONG_IO_V[3]
0	0	0	1	1	1	0	1	CELL.LONG_IO_V[1]
0	0	0	1	1	1	1	0	CELL.GCLK[0]
0	0	1	0	1	0	1	1	CELL.LONG_IO_V[0]
0	0	1	0	1	1	0	1	CELL.DEC_V[2]
0	0	1	1	0	0	1	1	CELL.DOUBLE_IO_E2[1]
0	0	1	1	0	1	0	1	CELL.LONG_IO_V[2]
0	0	1	1	0	1	1	0	CELL.DEC_V[3]
0	1	1	1	1	1	1	1	CELL.TIE_0
1	0	0	1	1	1	1	1	CELL.DOUBLE_IO_E1[0]
1	0	1	0	1	1	1	1	CELL.DOUBLE_IO_E1[1]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_E2[0]

xc4000h IO_E1_S switchbox INT muxes IMUX_IO_T[1]
Bits								Destination
MAIN[16][3]	MAIN[14][3]	MAIN[18][2]	MAIN[23][2]	MAIN[17][3]	MAIN[25][2]	MAIN[16][2]	MAIN[15][2]	CELL.IMUX_IO_T[1]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	1	0	1	1	CELL.LONG_IO_V[1]
0	0	1	0	1	1	0	1	CELL.LONG_IO_V[3]
0	0	1	0	1	1	1	0	CELL.GCLK[0]
0	0	1	1	0	0	1	1	CELL.DEC_V[2]
0	0	1	1	0	1	0	1	CELL.LONG_IO_V[0]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_E1[0]
0	1	1	1	0	1	1	1	CELL.DOUBLE_IO_E2[0]
1	0	1	1	1	0	1	1	CELL.DOUBLE_IO_E2[1]
1	0	1	1	1	1	0	1	CELL.LONG_IO_V[2]
1	0	1	1	1	1	1	0	CELL.DEC_V[3]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_E1[1]

xc4000h IO_E1_S switchbox INT muxes IMUX_HIO_O[0]
Bits	Destination
MAIN[0][7]	CELL.IMUX_HIO_O[0]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_G1

xc4000h IO_E1_S switchbox INT muxes IMUX_HIO_O[1]
Bits	Destination
MAIN[3][6]	CELL.IMUX_HIO_O[1]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_G1

xc4000h IO_E1_S switchbox INT muxes IMUX_HIO_O[2]
Bits	Destination
MAIN[4][2]	CELL.IMUX_HIO_O[2]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_F1

xc4000h IO_E1_S switchbox INT muxes IMUX_HIO_O[3]
Bits	Destination
MAIN[2][1]	CELL.IMUX_HIO_O[3]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_F1

xc4000h IO_E1_S switchbox INT muxes IMUX_HIO_T[0]
Bits	Destination
MAIN[4][8]	CELL.IMUX_HIO_T[0]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_OK[0]

xc4000h IO_E1_S switchbox INT muxes IMUX_HIO_T[1]
Bits	Destination
MAIN[1][6]	CELL.IMUX_HIO_T[1]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_IK[0]

xc4000h IO_E1_S switchbox INT muxes IMUX_HIO_T[2]
Bits	Destination
MAIN[1][3]	CELL.IMUX_HIO_T[2]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_IK[1]

xc4000h IO_E1_S switchbox INT muxes IMUX_HIO_T[3]
Bits	Destination
MAIN[4][1]	CELL.IMUX_HIO_T[3]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_OK[1]

xc4000h IO_E1_S switchbox INT muxes OUT_IO_WE_I1[0]
Bits	Destination
MAIN[0][5]	CELL.OUT_IO_WE_I1[0]
	Source
0	CELL.OUT_HIO_I[1]
1	CELL.OUT_HIO_I[0]

xc4000h IO_E1_S switchbox INT muxes OUT_IO_WE_I1[1]
Bits	Destination
MAIN[1][4]	CELL.OUT_IO_WE_I1[1]
	Source
0	CELL.OUT_HIO_I[2]
1	CELL.OUT_HIO_I[3]

xc4000h IO_E1_S switchbox INT muxes OUT_IO_WE_I2[0]
Bits	Destination
MAIN[3][9]	CELL.OUT_IO_WE_I2[0]
	Source
0	CELL.OUT_HIO_I[0]
1	CELL.OUT_HIO_I[1]

xc4000h IO_E1_S switchbox INT muxes OUT_IO_WE_I2[1]
Bits	Destination
MAIN[3][0]	CELL.OUT_IO_WE_I2[1]
	Source
0	CELL.OUT_HIO_I[3]
1	CELL.OUT_HIO_I[2]

Bels TBUF

xc4000h IO_E1_S bel TBUF pins
Pin	Direction	TBUF[0]	TBUF[1]
I	in	CELL.IMUX_TBUF_I[0]	CELL.IMUX_TBUF_I[1]
T	in	CELL.IMUX_TBUF_T[0]	CELL.IMUX_TBUF_T[1]
O	bidir	CELL.LONG_H[2]	CELL.LONG_H[3]

xc4000h IO_E1_S bel TBUF attribute bits
Attribute	TBUF[0]	TBUF[1]
DRIVE1	!MAIN[25][3]	!MAIN[13][3]

Bels HIO

xc4000h IO_E1_S bel HIO pins
Pin	Direction	HIO[0]	HIO[1]	HIO[2]	HIO[3]
O	in	CELL.IMUX_HIO_O[0] invert by !MAIN[1][8]	CELL.IMUX_HIO_O[1] invert by !MAIN[2][6]	CELL.IMUX_HIO_O[2] invert by !MAIN[2][3]	CELL.IMUX_HIO_O[3] invert by !MAIN[3][1]
T	in	CELL.IMUX_HIO_T[0] invert by !MAIN[4][9]	CELL.IMUX_HIO_T[1] invert by !MAIN[0][6]	CELL.IMUX_HIO_T[2] invert by !MAIN[0][3]	CELL.IMUX_HIO_T[3] invert by !MAIN[4][0]
I	out	CELL.OUT_HIO_I[0]	CELL.OUT_HIO_I[1]	CELL.OUT_HIO_I[2]	CELL.OUT_HIO_I[3]
CLKIN	out	-	-	CELL.OUT_IO_CLKIN	-

xc4000h IO_E1_S bel HIO attribute bits
Attribute	HIO[0]	HIO[1]	HIO[2]	HIO[3]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
ISTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OSTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OMODE	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]
I_INV	!MAIN[2][9]	!MAIN[1][5]	!MAIN[0][4]	!MAIN[2][0]
READBACK_I bit 0	!MAIN[2][8]	!MAIN[0][8]	!MAIN[4][3]	!MAIN[3][3]

xc4000h IO_E1_S enum IO_PULL
HIO[0].PULL	MAIN[1][7]	MAIN[2][7]
HIO[1].PULL	MAIN[4][6]	MAIN[8][6]
HIO[2].PULL	MAIN[9][3]	MAIN[3][2]
HIO[3].PULL	MAIN[0][1]	MAIN[1][1]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

xc4000h IO_E1_S enum IO_STD
HIO[0].ISTD	MAIN[1][9]
HIO[1].ISTD	MAIN[2][5]
HIO[2].ISTD	MAIN[2][4]
HIO[3].ISTD	MAIN[1][0]
CMOS	0
TTL	1

xc4000h IO_E1_S enum IO_STD
HIO[0].OSTD	MAIN[0][9]
HIO[1].OSTD	MAIN[3][5]
HIO[2].OSTD	MAIN[3][4]
HIO[3].OSTD	MAIN[0][0]
CMOS	1
TTL	0

xc4000h IO_E1_S enum HIO_OMODE
HIO[0].OMODE	MAIN[3][7]
HIO[1].OMODE	MAIN[4][7]
HIO[2].OMODE	MAIN[1][2]
HIO[3].OMODE	MAIN[0][2]
CAP	1
RES	0

Bels DEC

xc4000h IO_E1_S bel DEC pins
Pin	Direction	DEC[0]	DEC[1]	DEC[2]
I	in	CELL.OUT_IO_WE_I1[0]	CELL.IMUX_CLB_C1	CELL.OUT_IO_WE_I1[1]
O1	bidir	CELL.DEC_V[0]	CELL.DEC_V[0]	CELL.DEC_V[0]
O2	bidir	CELL.DEC_V[1]	CELL.DEC_V[1]	CELL.DEC_V[1]
O3	bidir	CELL.DEC_V[2]	CELL.DEC_V[2]	CELL.DEC_V[2]
O4	bidir	CELL.DEC_V[3]	CELL.DEC_V[3]	CELL.DEC_V[3]

xc4000h IO_E1_S bel DEC attribute bits
Attribute	DEC[0]	DEC[1]	DEC[2]
O1_P	!MAIN[5][4]	!MAIN[5][6]	MAIN[4][5]
O1_N	MAIN[5][3]	MAIN[5][5]	!MAIN[4][4]
O2_P	!MAIN[10][4]	!MAIN[8][3]	MAIN[9][4]
O2_N	MAIN[10][3]	MAIN[8][4]	!MAIN[9][5]
O3_P	!MAIN[6][3]	!MAIN[6][6]	MAIN[7][4]
O3_N	MAIN[6][4]	MAIN[6][5]	!MAIN[7][5]
O4_P	!MAIN[12][4]	!MAIN[12][5]	MAIN[11][5]
O4_N	MAIN[12][3]	MAIN[12][6]	!MAIN[11][4]

Bels PULLUP

xc4000h IO_E1_S bel PULLUP pins
Pin	Direction	PULLUP_TBUF[0]	PULLUP_TBUF[1]
O	bidir	CELL.LONG_H[2]	CELL.LONG_H[3]

xc4000h IO_E1_S bel PULLUP attribute bits
Attribute	PULLUP_TBUF[0]	PULLUP_TBUF[1]
ENABLE	!MAIN_S[25][12]	!MAIN[14][7]

Bel wires

xc4000h IO_E1_S bel wires
Wire	Pins
CELL.LONG_H[2]	TBUF[0].O, PULLUP_TBUF[0].O
CELL.LONG_H[3]	TBUF[1].O, PULLUP_TBUF[1].O
CELL.DEC_V[0]	DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_V[1]	DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.DEC_V[2]	DEC[0].O3, DEC[1].O3, DEC[2].O3
CELL.DEC_V[3]	DEC[0].O4, DEC[1].O4, DEC[2].O4
CELL.IMUX_CLB_C1	DEC[1].I
CELL.IMUX_TBUF_I[0]	TBUF[0].I
CELL.IMUX_TBUF_I[1]	TBUF[1].I
CELL.IMUX_TBUF_T[0]	TBUF[0].T
CELL.IMUX_TBUF_T[1]	TBUF[1].T
CELL.IMUX_HIO_O[0]	HIO[0].O
CELL.IMUX_HIO_O[1]	HIO[1].O
CELL.IMUX_HIO_O[2]	HIO[2].O
CELL.IMUX_HIO_O[3]	HIO[3].O
CELL.IMUX_HIO_T[0]	HIO[0].T
CELL.IMUX_HIO_T[1]	HIO[1].T
CELL.IMUX_HIO_T[2]	HIO[2].T
CELL.IMUX_HIO_T[3]	HIO[3].T
CELL.OUT_IO_WE_I1[0]	DEC[0].I
CELL.OUT_IO_WE_I1[1]	DEC[2].I
CELL.OUT_HIO_I[0]	HIO[0].I
CELL.OUT_HIO_I[1]	HIO[1].I
CELL.OUT_HIO_I[2]	HIO[2].I
CELL.OUT_HIO_I[3]	HIO[3].I
CELL.OUT_IO_CLKIN	HIO[2].CLKIN

Bitstream

xc4000h IO_E1_S rect MAIN
Bit	Frame
Bit	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7]	INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7]	INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7]	INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5]	-	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0]	INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0	INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_E0[3]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E0[3]	INT: !bipass CELL.DOUBLE_IO_E0[3] = CELL.DOUBLE_IO_E2[3]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E1[3]	INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_E1[3]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_E2[3]	INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_E2[3]	-	INT: !pass CELL.SINGLE_H[7] ← CELL.DEC_V[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E0[1]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E0[1]	INT: !bipass CELL.DOUBLE_IO_E0[1] = CELL.DOUBLE_IO_E2[1]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E1[1]	INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_E1[1]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_E2[1]	INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_E2[1]	INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[1]	INT: mux CELL.LONG_IO_V[1] bit 2	INT: mux CELL.IMUX_IO_O1[0] bit 2	INT: mux CELL.IMUX_IO_O1[0] bit 1	INT: mux CELL.IMUX_IO_O1[0] bit 5	HIO[0]: !invert T	INT: mux CELL.OUT_IO_WE_I2[0] bit 0	HIO[0]: ! I_INV	HIO[0]: ISTD bit 0	HIO[0]: OSTD bit 0
B8	-	INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4]	INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6]	INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6]	-	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2]	-	INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0]	-	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0]	-	INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_IO_WE_I1_S1	INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_IO_WE_I1[0]	INT: mux CELL.LONG_IO_V[2] bit 1	INT: mux CELL.LONG_IO_V[2] bit 0	INT: mux CELL.LONG_IO_V[2] bit 2	INT: mux CELL.LONG_IO_V[2] bit 3	INT: mux CELL.LONG_IO_V[3] bit 1	-	INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_IO_V[3]	INT: mux CELL.LONG_IO_V[3] bit 0	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1	INT: mux CELL.LONG_IO_V[1] bit 0	INT: mux CELL.LONG_IO_V[1] bit 1	INT: mux CELL.LONG_IO_V[1] bit 3	INT: mux CELL.DBUF_IO_V[1] bit 1	INT: mux CELL.DBUF_IO_V[1] bit 0	INT: mux CELL.DBUF_IO_V[1] bit 2	INT: mux CELL.DBUF_IO_V[1] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 4	INT: mux CELL.IMUX_HIO_T[0] bit 0	-	HIO[0]: ! READBACK_I bit 0	HIO[0]: !invert O	HIO[1]: ! READBACK_I bit 0
B7	INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5]	INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2]	INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6]	INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3]	INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3]	-	INT: mux CELL.LONG_H[4] bit 1	INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_IO_WE_I1_S1	INT: mux CELL.LONG_H[4] bit 2	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_IO_WE_I1[0]	INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1[0]	INT: mux CELL.LONG_H[5] bit 2	-	INT: !pass CELL.DOUBLE_IO_E0[3] ← CELL.DBUF_IO_V[0]	INT: !pass CELL.DOUBLE_IO_E0[1] ← CELL.DBUF_IO_V[0]	INT: mux CELL.LONG_H[5] bit 3	PULLUP_TBUF[1]: ! ENABLE	INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[1]	INT: mux CELL.IMUX_IO_IK[0] bit 5	INT: mux CELL.IMUX_IO_IK[0] bit 6	INT: mux CELL.IMUX_IO_IK[0] bit 1	INT: mux CELL.IMUX_IO_IK[0] bit 4	INT: mux CELL.IMUX_IO_IK[0] bit 2	INT: mux CELL.IMUX_IO_IK[0] bit 3	INT: mux CELL.IMUX_IO_IK[0] bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 7	HIO[1]: OMODE bit 0	HIO[0]: OMODE bit 0	HIO[0]: PULL bit 0	HIO[0]: PULL bit 1	INT: mux CELL.IMUX_HIO_O[0] bit 0
B6	INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4]	INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4]	INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1]	INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5]	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0]	INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[4]	INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0	INT: mux CELL.LONG_H[4] bit 0	INT: mux CELL.LONG_H[4] bit 3	INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.DOUBLE_IO_E2[3] ← CELL.DBUF_IO_V[1]	INT: mux CELL.LONG_H[5] bit 1	INT: mux CELL.LONG_H[5] bit 0	INT: !pass CELL.DOUBLE_IO_E0[0] ← CELL.DBUF_IO_V[0]	-	INT: !pass CELL.DOUBLE_IO_E0[2] ← CELL.DBUF_IO_V[0]	INT: mux CELL.IMUX_IO_OK[0] bit 6	INT: !pass CELL.DOUBLE_IO_E2[1] ← CELL.DBUF_IO_V[1]	INT: mux CELL.IMUX_IO_OK[0] bit 1	INT: mux CELL.IMUX_IO_OK[0] bit 4	DEC[1]: O4_N	INT: mux CELL.IMUX_IO_OK[0] bit 2	INT: mux CELL.IMUX_IO_OK[0] bit 3	INT: mux CELL.IMUX_IO_OK[0] bit 0	HIO[1]: PULL bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 7	DEC[1]: ! O3_P	DEC[1]: ! O1_P	HIO[1]: PULL bit 1	INT: mux CELL.IMUX_HIO_O[1] bit 0	HIO[1]: !invert O	INT: mux CELL.IMUX_HIO_T[1] bit 0	HIO[1]: !invert T
B5	INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4]	INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5]	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5]	INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1]	INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1]	INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E0[0]	INT: mux CELL.LONG_IO_V[0] bit 0	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E0[0]	INT: !bipass CELL.DOUBLE_IO_E0[0] = CELL.DOUBLE_IO_E2[0]	INT: mux CELL.LONG_IO_V[0] bit 1	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E1[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_E1[0]	INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[0]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_E2[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_E2[0]	INT: !pass CELL.DOUBLE_IO_E2[0] ← CELL.DBUF_IO_V[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E2[2]	INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_E2[2]	DEC[1]: ! O4_P	DEC[2]: O4_P	INT: !pass CELL.SINGLE_H[4] ← CELL.DEC_V[2]	DEC[2]: ! O2_N	INT: mux CELL.IMUX_IO_OK[0] bit 5	DEC[2]: ! O3_N	DEC[1]: O3_N	DEC[1]: O1_N	DEC[2]: O1_P	HIO[1]: OSTD bit 0	HIO[1]: ISTD bit 0	HIO[1]: ! I_INV	INT: mux CELL.OUT_IO_WE_I1[0] bit 0
B4	INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_CLB_Y_E	INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5]	INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_WE_I2[1]	INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_WE_I2[1]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_CLB_YQ_E	INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4]	INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3]	INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1]	INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_CLB_Y_E	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_WE_I2[1]	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_WE_I2[0]	INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[3]	INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_CLB_YQ_E	INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[0]	INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_IO_V[2]	INT: mux CELL.IMUX_IO_T[0] bit 6	INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_E0[2]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E0[2]	INT: !bipass CELL.DOUBLE_IO_E0[2] = CELL.DOUBLE_IO_E2[2]	INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_E1[2]	INT: !pass CELL.DOUBLE_IO_E2[2] ← CELL.DBUF_IO_V[1]	DEC[0]: ! O4_P	DEC[2]: ! O4_N	DEC[0]: ! O2_P	DEC[2]: O2_P	DEC[1]: O2_N	DEC[2]: O3_P	DEC[0]: O3_N	DEC[0]: ! O1_P	DEC[2]: ! O1_N	HIO[2]: OSTD bit 0	HIO[2]: ISTD bit 0	INT: mux CELL.OUT_IO_WE_I1[1] bit 0	HIO[2]: ! I_INV
B3	INT: mux CELL.IMUX_CLB_F3 bit 0	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_WE_I2[0]	INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_CLB_YQ_E	INT: mux CELL.IMUX_CLB_C3 bit 1	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5]	INT: mux CELL.IMUX_CLB_G3 bit 0	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1]	INT: mux CELL.IMUX_CLB_F1 bit 3	INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1]	INT: mux CELL.IMUX_CLB_C1 bit 7	INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4]	INT: mux CELL.IMUX_CLB_G1 bit 6	TBUF[0]: ! DRIVE1	INT: mux CELL.IMUX_IO_T[0] bit 0	INT: mux CELL.IMUX_IO_T[0] bit 2	INT: mux CELL.DBUF_IO_V[0] bit 0	INT: mux CELL.DBUF_IO_V[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 7	INT: mux CELL.IMUX_IO_T[0] bit 3	-	INT: mux CELL.IMUX_IO_T[1] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 7	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_E1[2]	INT: mux CELL.IMUX_IO_T[1] bit 6	TBUF[1]: ! DRIVE1	DEC[0]: O4_N	INT: mux CELL.IMUX_IO_IK[1] bit 0	DEC[0]: O2_N	HIO[2]: PULL bit 1	DEC[1]: ! O2_P	INT: mux CELL.IMUX_IO_IK[1] bit 5	DEC[0]: ! O3_P	DEC[0]: O1_N	HIO[2]: ! READBACK_I bit 0	HIO[3]: ! READBACK_I bit 0	HIO[2]: !invert O	INT: mux CELL.IMUX_HIO_T[2] bit 0	HIO[2]: !invert T
B2	INT: mux CELL.IMUX_CLB_F3 bit 2	INT: mux CELL.IMUX_CLB_F3 bit 6	INT: mux CELL.IMUX_CLB_F3 bit 8	INT: mux CELL.IMUX_CLB_C3 bit 2	INT: mux CELL.IMUX_CLB_C3 bit 3	INT: mux CELL.IMUX_CLB_G3 bit 1	INT: mux CELL.IMUX_CLB_G3 bit 4	INT: mux CELL.IMUX_CLB_G3 bit 7	INT: mux CELL.IMUX_CLB_F1 bit 0	INT: mux CELL.IMUX_CLB_F1 bit 7	INT: mux CELL.IMUX_CLB_C1 bit 2	INT: mux CELL.IMUX_CLB_C1 bit 1	INT: mux CELL.IMUX_CLB_C1 bit 6	-	INT: mux CELL.IMUX_CLB_G1 bit 0	INT: mux CELL.IMUX_IO_T[1] bit 2	INT: mux CELL.DBUF_IO_V[0] bit 2	INT: mux CELL.IMUX_IO_T[1] bit 4	INT: mux CELL.DBUF_IO_V[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 4	INT: mux CELL.IMUX_IO_T[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 5	INT: mux CELL.IMUX_IO_T[1] bit 5	-	INT: mux CELL.IMUX_IO_T[1] bit 1	INT: mux CELL.IMUX_IO_T[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 1	INT: mux CELL.IMUX_IO_OK[1] bit 2	INT: mux CELL.IMUX_IO_OK[1] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_OK[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 5	INT: mux CELL.IMUX_IO_OK[1] bit 6	INT: mux CELL.IMUX_IO_OK[1] bit 3	INT: mux CELL.IMUX_IO_OK[1] bit 7	INT: mux CELL.IMUX_HIO_O[2] bit 0	HIO[2]: PULL bit 0	-	HIO[2]: OMODE bit 0	HIO[3]: OMODE bit 0
B1	INT: mux CELL.IMUX_CLB_F3 bit 5	INT: mux CELL.IMUX_CLB_F3 bit 3	INT: mux CELL.IMUX_CLB_C3 bit 0	INT: mux CELL.IMUX_CLB_C3 bit 5	INT: mux CELL.IMUX_CLB_C3 bit 6	INT: mux CELL.IMUX_CLB_G3 bit 6	INT: mux CELL.IMUX_CLB_G3 bit 2	INT: mux CELL.IMUX_CLB_G3 bit 5	INT: mux CELL.IMUX_CLB_F1 bit 5	INT: mux CELL.IMUX_CLB_F1 bit 2	INT: mux CELL.IMUX_CLB_C1 bit 5	INT: mux CELL.IMUX_CLB_C1 bit 3	INT: mux CELL.IMUX_CLB_G1 bit 4	INT: mux CELL.IMUX_CLB_G1 bit 3	INT: mux CELL.IMUX_CLB_G1 bit 2	INT: mux CELL.LONG_H[0] bit 1	INT: mux CELL.LONG_H[0] bit 3	INT: mux CELL.IMUX_TBUF_I[0] bit 5	INT: mux CELL.IMUX_TBUF_I[0] bit 0	INT: mux CELL.IMUX_TBUF_I[0] bit 2	INT: mux CELL.IMUX_TBUF_T[0] bit 2	INT: mux CELL.IMUX_TBUF_T[0] bit 1	INT: mux CELL.IMUX_TBUF_T[1] bit 2	INT: mux CELL.IMUX_TBUF_T[1] bit 4	INT: mux CELL.IMUX_TBUF_T[1] bit 0	INT: mux CELL.IMUX_TBUF_T[1] bit 3	INT: mux CELL.IMUX_TBUF_I[1] bit 4	INT: mux CELL.IMUX_TBUF_I[1] bit 0	INT: mux CELL.IMUX_TBUF_I[1] bit 5	INT: mux CELL.LONG_H[1] bit 0	INT: mux CELL.LONG_H[1] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 6	INT: mux CELL.IMUX_IO_IK[1] bit 3	INT: mux CELL.IMUX_IO_IK[1] bit 7	INT: mux CELL.IMUX_HIO_T[3] bit 0	HIO[3]: !invert O	INT: mux CELL.IMUX_HIO_O[3] bit 0	HIO[3]: PULL bit 0	HIO[3]: PULL bit 1
B0	INT: mux CELL.IMUX_CLB_F3 bit 7	INT: mux CELL.IMUX_CLB_F3 bit 1	INT: mux CELL.IMUX_CLB_F3 bit 4	INT: mux CELL.IMUX_CLB_C3 bit 4	INT: mux CELL.IMUX_CLB_C3 bit 7	INT: mux CELL.IMUX_CLB_G3 bit 3	INT: mux CELL.IMUX_CLB_G3 bit 8	INT: mux CELL.IMUX_CLB_F1 bit 6	INT: mux CELL.IMUX_CLB_F1 bit 1	INT: mux CELL.IMUX_CLB_F1 bit 4	INT: mux CELL.IMUX_CLB_C1 bit 0	INT: mux CELL.IMUX_CLB_C1 bit 4	INT: mux CELL.IMUX_CLB_G1 bit 5	INT: mux CELL.IMUX_CLB_G1 bit 1	INT: mux CELL.IMUX_CLB_G1 bit 7	INT: mux CELL.LONG_H[0] bit 0	INT: mux CELL.LONG_H[0] bit 2	INT: mux CELL.IMUX_TBUF_I[0] bit 3	INT: mux CELL.IMUX_TBUF_I[0] bit 1	INT: mux CELL.IMUX_TBUF_I[0] bit 4	INT: mux CELL.IMUX_TBUF_T[0] bit 3	INT: mux CELL.IMUX_TBUF_T[0] bit 4	INT: mux CELL.IMUX_TBUF_T[0] bit 0	INT: mux CELL.IMUX_TBUF_T[0] bit 5	INT: mux CELL.IMUX_TBUF_T[1] bit 1	INT: mux CELL.IMUX_TBUF_T[1] bit 5	INT: mux CELL.IMUX_TBUF_I[1] bit 2	INT: mux CELL.IMUX_TBUF_I[1] bit 1	INT: mux CELL.IMUX_TBUF_I[1] bit 3	INT: mux CELL.LONG_H[1] bit 1	INT: mux CELL.LONG_H[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 0	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.IMUX_IO_O1[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 5	INT: mux CELL.IMUX_IO_O1[1] bit 4	HIO[3]: !invert T	INT: mux CELL.OUT_IO_WE_I2[1] bit 0	HIO[3]: ! I_INV	HIO[3]: ISTD bit 0	HIO[3]: OSTD bit 0

xc4000h IO_E1_S rect MAIN_S
Bit	Frame
Bit	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B12	-	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2]	-	-	-	-	-	-	-	PULLUP_TBUF[0]: ! ENABLE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1]	-	-	-	INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2]	-	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0]	-	INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

xc4000h IO_E1_S rect MAIN_W
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile IO_S0

Cells: 4

Switchbox INT

xc4000h IO_S0 switchbox INT programmable buffers
Destination	Source	Bit
CELL.LONG_H[3]	CELL.SINGLE_V[4]	!MAIN[24][5]
CELL.LONG_H[4]	CELL.SINGLE_V[5]	!MAIN[14][8]
CELL.LONG_H[5]	CELL.SINGLE_V[6]	!MAIN[18][12]
CELL.LONG_V[0]	CELL.SINGLE_H_E[1]	!MAIN[13][8]
CELL.LONG_V[1]	CELL.SINGLE_H_E[2]	!MAIN[33][11]
CELL.LONG_V[2]	CELL.SINGLE_H_E[3]	!MAIN[19][12]
CELL.LONG_V[3]	CELL.SINGLE_H[4]	!MAIN[9][8]
CELL.LONG_V[4]	CELL.SINGLE_H[5]	!MAIN[12][8]
CELL.LONG_V[5]	CELL.SINGLE_H[6]	!MAIN[30][11]

xc4000h IO_S0 switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[0]	CELL.TIE_0	!MAIN[7][8]
CELL.SINGLE_H[0]	CELL.OUT_IO_SN_I2[0]	!MAIN[19][9]
CELL.SINGLE_H[1]	CELL.OUT_IO_SN_I2[1]	!MAIN[15][9]
CELL.SINGLE_H[2]	CELL.OUT_CLB_XQ_S	!MAIN[14][10]
CELL.SINGLE_H[3]	CELL.TIE_0	!MAIN[11][10]
CELL.SINGLE_H[3]	CELL.OUT_CLB_X_S	!MAIN[13][12]
CELL.SINGLE_H[4]	CELL.LONG_V[3]	!MAIN[30][7]
CELL.SINGLE_H[4]	CELL.OUT_IO_SN_I2[0]	!MAIN[18][9]
CELL.SINGLE_H[5]	CELL.LONG_V[4]	!MAIN[23][7]
CELL.SINGLE_H[5]	CELL.OUT_IO_SN_I2[1]	!MAIN[17][9]
CELL.SINGLE_H[6]	CELL.TIE_0	!MAIN[13][9]
CELL.SINGLE_H[6]	CELL.LONG_V[5]	!MAIN[29][12]
CELL.SINGLE_H[6]	CELL.OUT_CLB_XQ_S	!MAIN[15][10]
CELL.SINGLE_H[7]	CELL.TIE_0	!MAIN[12][12]
CELL.SINGLE_H[7]	CELL.OUT_CLB_X_S	!MAIN[14][12]
CELL.SINGLE_H_E[1]	CELL.LONG_V[0]	!MAIN[27][8]
CELL.SINGLE_H_E[2]	CELL.LONG_V[1]	!MAIN[35][12]
CELL.SINGLE_H_E[3]	CELL.LONG_V[2]	!MAIN[29][9]
CELL.SINGLE_V[0]	CELL.TIE_0	!MAIN[21][9]
CELL.SINGLE_V[0]	CELL.DEC_H[3]	!MAIN[19][4]
CELL.SINGLE_V[0]	CELL.OUT_IO_SN_I2_E1	!MAIN[22][5]
CELL.SINGLE_V[1]	CELL.LONG_IO_H[0]	!MAIN[15][4]
CELL.SINGLE_V[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[22][6]
CELL.SINGLE_V[2]	CELL.LONG_IO_H[1]	!MAIN[17][4]
CELL.SINGLE_V[2]	CELL.OUT_IO_SN_I1[0]	!MAIN[25][4]
CELL.SINGLE_V[3]	CELL.DEC_H[2]	!MAIN[30][4]
CELL.SINGLE_V[3]	CELL.OUT_IO_SN_I1_E1	!MAIN[29][4]
CELL.SINGLE_V[4]	CELL.LONG_H[3]	!MAIN[21][10]
CELL.SINGLE_V[4]	CELL.DEC_H[1]	!MAIN[35][4]
CELL.SINGLE_V[4]	CELL.OUT_IO_SN_I2_E1	!MAIN[35][6]
CELL.SINGLE_V[5]	CELL.LONG_H[4]	!MAIN[35][8]
CELL.SINGLE_V[5]	CELL.LONG_IO_H[2]	!MAIN[33][4]
CELL.SINGLE_V[5]	CELL.OUT_IO_SN_I2[0]	!MAIN[32][6]
CELL.SINGLE_V[6]	CELL.LONG_H[5]	!MAIN[35][10]
CELL.SINGLE_V[6]	CELL.LONG_IO_H[3]	!MAIN[34][4]
CELL.SINGLE_V[6]	CELL.OUT_IO_SN_I1[0]	!MAIN[25][5]
CELL.SINGLE_V[7]	CELL.TIE_0	!MAIN[21][12]
CELL.SINGLE_V[7]	CELL.DEC_H[0]	!MAIN[31][4]
CELL.SINGLE_V[7]	CELL.OUT_IO_SN_I1_E1	!MAIN[32][4]
CELL.DOUBLE_H0[0]	CELL.OUT_CLB_XQ_S	!MAIN[13][10]
CELL.DOUBLE_H0[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[20][9]
CELL.DOUBLE_H1[0]	CELL.OUT_CLB_X_S	!MAIN[15][12]
CELL.DOUBLE_H1[1]	CELL.OUT_IO_SN_I2[1]	!MAIN[16][9]
CELL.DOUBLE_V0[0]	CELL.OUT_IO_SN_I1_E1	!MAIN[21][3]
CELL.DOUBLE_V0[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[30][6]
CELL.DOUBLE_V1[0]	CELL.OUT_IO_SN_I1[0]	!MAIN[20][3]
CELL.DOUBLE_V1[1]	CELL.OUT_IO_SN_I2_E1	!MAIN[31][6]
CELL.DOUBLE_IO_S0[0]	CELL.DBUF_IO_H[1]	!MAIN[10][2]
CELL.DOUBLE_IO_S0[1]	CELL.DBUF_IO_H[1]	!MAIN[9][2]
CELL.DOUBLE_IO_S0[2]	CELL.DBUF_IO_H[1]	!MAIN[9][1]
CELL.DOUBLE_IO_S0[3]	CELL.DBUF_IO_H[1]	!MAIN[10][1]
CELL.DOUBLE_IO_S2[0]	CELL.DBUF_IO_H[0]	!MAIN[35][2]
CELL.DOUBLE_IO_S2[1]	CELL.DBUF_IO_H[0]	!MAIN[34][2]
CELL.DOUBLE_IO_S2[2]	CELL.DBUF_IO_H[0]	!MAIN[34][1]
CELL.DOUBLE_IO_S2[3]	CELL.DBUF_IO_H[0]	!MAIN[35][1]

xc4000h IO_S0 switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.SINGLE_H_E[0]	!MAIN[23][9]
CELL.SINGLE_H[0]	CELL.SINGLE_V[0]	!MAIN[22][8]
CELL.SINGLE_H[0]	CELL.SINGLE_V_S[0]	!MAIN[25][7]
CELL.SINGLE_H[1]	CELL.SINGLE_H_E[1]	!MAIN[25][8]
CELL.SINGLE_H[1]	CELL.SINGLE_V[1]	!MAIN[24][8]
CELL.SINGLE_H[1]	CELL.SINGLE_V_S[1]	!MAIN[24][7]
CELL.SINGLE_H[2]	CELL.SINGLE_H_E[2]	!MAIN[27][11]
CELL.SINGLE_H[2]	CELL.SINGLE_V[2]	!MAIN[26][11]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[2]	!MAIN[28][11]
CELL.SINGLE_H[3]	CELL.SINGLE_H_E[3]	!MAIN[26][10]
CELL.SINGLE_H[3]	CELL.SINGLE_V[3]	!MAIN[23][10]
CELL.SINGLE_H[3]	CELL.SINGLE_V_S[3]	!MAIN[25][10]
CELL.SINGLE_H[4]	CELL.SINGLE_H_E[4]	!MAIN[31][9]
CELL.SINGLE_H[4]	CELL.SINGLE_V[4]	!MAIN[34][9]
CELL.SINGLE_H[4]	CELL.SINGLE_V_S[4]	!MAIN[30][9]
CELL.SINGLE_H[5]	CELL.SINGLE_H_E[5]	!MAIN[30][8]
CELL.SINGLE_H[5]	CELL.SINGLE_V[5]	!MAIN[31][7]
CELL.SINGLE_H[5]	CELL.SINGLE_V_S[5]	!MAIN[32][8]
CELL.SINGLE_H[6]	CELL.SINGLE_H_E[6]	!MAIN[30][10]
CELL.SINGLE_H[6]	CELL.SINGLE_V[6]	!MAIN[31][11]
CELL.SINGLE_H[6]	CELL.SINGLE_V_S[6]	!MAIN[31][10]
CELL.SINGLE_H[7]	CELL.SINGLE_H_E[7]	!MAIN[33][12]
CELL.SINGLE_H[7]	CELL.SINGLE_V[7]	!MAIN[30][12]
CELL.SINGLE_H[7]	CELL.SINGLE_V_S[7]	!MAIN[32][11]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V[0]	!MAIN[21][8]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V_S[0]	!MAIN[23][8]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V[1]	!MAIN[25][9]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V_S[1]	!MAIN[26][8]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V[2]	!MAIN[26][12]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V_S[2]	!MAIN[27][12]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V[3]	!MAIN[27][10]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V_S[3]	!MAIN[28][10]
CELL.SINGLE_H_E[4]	CELL.SINGLE_V[4]	!MAIN[34][11]
CELL.SINGLE_H_E[4]	CELL.SINGLE_V_S[4]	!MAIN[32][9]
CELL.SINGLE_H_E[5]	CELL.SINGLE_V[5]	!MAIN[31][8]
CELL.SINGLE_H_E[5]	CELL.SINGLE_V_S[5]	!MAIN[33][8]
CELL.SINGLE_H_E[6]	CELL.SINGLE_V[6]	!MAIN[29][10]
CELL.SINGLE_H_E[6]	CELL.SINGLE_V_S[6]	!MAIN[32][10]
CELL.SINGLE_H_E[7]	CELL.SINGLE_V[7]	!MAIN[32][12]
CELL.SINGLE_H_E[7]	CELL.SINGLE_V_S[7]	!MAIN[34][12]
CELL.SINGLE_V[0]	CELL.SINGLE_V_S[0]	!MAIN[24][9]
CELL.SINGLE_V[0]	CELL.DOUBLE_IO_S0[0]	!MAIN[22][2]
CELL.SINGLE_V[0]	CELL.DOUBLE_IO_S2[0]	!MAIN[24][2]
CELL.SINGLE_V[1]	CELL.SINGLE_V_S[1]	!MAIN[26][7]
CELL.SINGLE_V[1]	CELL.DOUBLE_IO_S1[0]	!MAIN[19][2]
CELL.SINGLE_V[2]	CELL.SINGLE_V_S[2]	!MAIN[25][12]
CELL.SINGLE_V[2]	CELL.DOUBLE_IO_S0[1]	!MAIN[27][2]
CELL.SINGLE_V[2]	CELL.DOUBLE_IO_S2[1]	!MAIN[26][1]
CELL.SINGLE_V[3]	CELL.SINGLE_V_S[3]	!MAIN[22][10]
CELL.SINGLE_V[3]	CELL.DOUBLE_IO_S1[1]	!MAIN[25][3]
CELL.SINGLE_V[4]	CELL.SINGLE_V_S[4]	!MAIN[33][9]
CELL.SINGLE_V[4]	CELL.DOUBLE_IO_S0[2]	!MAIN[30][2]
CELL.SINGLE_V[4]	CELL.DOUBLE_IO_S2[2]	!MAIN[29][1]
CELL.SINGLE_V[5]	CELL.SINGLE_V_S[5]	!MAIN[34][8]
CELL.SINGLE_V[5]	CELL.DOUBLE_IO_S1[2]	!MAIN[28][2]
CELL.SINGLE_V[6]	CELL.SINGLE_V_S[6]	!MAIN[33][10]
CELL.SINGLE_V[6]	CELL.DOUBLE_IO_S0[3]	!MAIN[32][1]
CELL.SINGLE_V[6]	CELL.DOUBLE_IO_S2[3]	!MAIN[32][2]
CELL.SINGLE_V[7]	CELL.SINGLE_V_S[7]	!MAIN[31][12]
CELL.SINGLE_V[7]	CELL.DOUBLE_IO_S1[3]	!MAIN[31][3]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_H2[0]	!MAIN[24][12]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_V0[0]	!MAIN[22][12]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_V2[0]	!MAIN[23][12]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_H2[1]	!MAIN[28][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_V0[1]	!MAIN[27][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_V2[1]	!MAIN[28][7]
CELL.DOUBLE_H2[0]	CELL.DOUBLE_V0[0]	!MAIN[24][10]
CELL.DOUBLE_H2[0]	CELL.DOUBLE_V2[0]	!MAIN[24][11]
CELL.DOUBLE_H2[1]	CELL.DOUBLE_V0[1]	!MAIN[28][8]
CELL.DOUBLE_H2[1]	CELL.DOUBLE_V2[1]	!MAIN[29][8]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_V2[0]	!MAIN[22][11]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_S0[1]	!MAIN[26][2]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_S1[1]	!MAIN[24][3]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_S2[1]	!MAIN[27][1]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_V2[1]	!MAIN[29][7]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_S0[2]	!MAIN[28][1]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_S1[2]	!MAIN[29][2]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_S2[2]	!MAIN[30][1]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_S0[0]	!MAIN[21][2]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_S1[0]	!MAIN[20][2]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_S2[0]	!MAIN[25][2]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_S0[3]	!MAIN[31][2]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_S1[3]	!MAIN[31][1]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_S2[3]	!MAIN[33][2]
CELL.DOUBLE_IO_S0[0]	CELL.DOUBLE_IO_S2[0]	!MAIN[23][2]
CELL.DOUBLE_IO_S0[1]	CELL.DOUBLE_IO_S2[1]	!MAIN[25][1]
CELL.DOUBLE_IO_S0[2]	CELL.DOUBLE_IO_S2[2]	!MAIN[30][3]
CELL.DOUBLE_IO_S0[3]	CELL.DOUBLE_IO_S2[3]	!MAIN[32][3]

xc4000h IO_S0 switchbox INT muxes DBUF_IO_H[0]
Bits				Destination
MAIN[7][2]	MAIN[8][2]	MAIN[7][1]	MAIN[8][1]	CELL.DBUF_IO_H[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_S0[0]
0	1	0	1	CELL.DOUBLE_IO_S0[2]
0	1	1	0	CELL.DOUBLE_IO_S0[3]
1	1	1	1	CELL.DOUBLE_IO_S0[1]

xc4000h IO_S0 switchbox INT muxes DBUF_IO_H[1]
Bits				Destination
MAIN[33][3]	MAIN[34][3]	MAIN[35][3]	MAIN[33][1]	CELL.DBUF_IO_H[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_S2[1]
0	1	0	1	CELL.DOUBLE_IO_S2[2]
0	1	1	0	CELL.DOUBLE_IO_S2[3]
1	1	1	1	CELL.DOUBLE_IO_S2[0]

xc4000h IO_S0 switchbox INT muxes LONG_V[0]
Bits				Destination
MAIN[26][5]	MAIN[27][5]	MAIN[29][5]	MAIN[28][5]	CELL.LONG_V[0]
				Source
0	0	0	1	CELL.LONG_IO_H[0]
0	0	1	0	CELL.DEC_H[0]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_S0 switchbox INT muxes LONG_V[1]
Bits				Destination
MAIN[35][5]	MAIN[33][5]	MAIN[34][6]	MAIN[34][5]	CELL.LONG_V[1]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_S0 switchbox INT muxes LONG_V[2]
Bits				Destination
MAIN[31][5]	MAIN[30][5]	MAIN[32][5]	MAIN[33][6]	CELL.LONG_V[2]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_S0 switchbox INT muxes LONG_V[3]
Bits				Destination
MAIN[6][5]	MAIN[6][6]	MAIN[7][6]	MAIN[7][5]	CELL.LONG_V[3]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_S0 switchbox INT muxes LONG_V[4]
Bits				Destination
MAIN[5][5]	MAIN[1][6]	MAIN[2][6]	MAIN[2][5]	CELL.LONG_V[4]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_S0 switchbox INT muxes LONG_V[5]
Bits				Destination
MAIN[8][5]	MAIN[8][6]	MAIN[9][5]	MAIN[9][6]	CELL.LONG_V[5]
				Source
0	0	0	1	CELL.LONG_IO_H[3]
0	0	1	0	CELL.DEC_H[3]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_S0 switchbox INT muxes LONG_IO_H[0]
Bits		Destination
MAIN[4][6]	MAIN[16][4]	CELL.LONG_IO_H[0]
		Source
0	0	CELL.LONG_V[0]
0	1	CELL.SINGLE_V[1]
1	1	off

xc4000h IO_S0 switchbox INT muxes LONG_IO_H[1]
Bits				Destination
MAIN[23][3]	MAIN[15][3]	MAIN[18][4]	MAIN[16][3]	CELL.LONG_IO_H[1]
				Source
0	0	0	1	CELL.LONG_V[1]
0	0	1	0	CELL.LONG_V[3]
0	1	1	1	CELL.SINGLE_V[2]
1	1	1	1	off

xc4000h IO_S0 switchbox INT muxes LONG_IO_H[2]
Bits				Destination
MAIN[22][3]	MAIN[20][4]	MAIN[21][4]	MAIN[22][4]	CELL.LONG_IO_H[2]
				Source
0	0	0	1	CELL.LONG_V[2]
0	0	1	0	CELL.LONG_V[4]
0	1	1	1	CELL.SINGLE_V[5]
1	1	1	1	off

xc4000h IO_S0 switchbox INT muxes LONG_IO_H[3]
Bits		Destination
MAIN[4][5]	MAIN[23][4]	CELL.LONG_IO_H[3]
		Source
0	0	CELL.LONG_V[5]
0	1	CELL.SINGLE_V[6]
1	1	off

xc4000h IO_S0 switchbox INT muxes IMUX_CLB_F2
Bits								Destination
MAIN[10][12]	MAIN[10][10]	MAIN[11][9]	MAIN[11][11]	MAIN[11][12]	MAIN[12][11]	MAIN[12][10]	MAIN[12][9]	CELL.IMUX_CLB_F2
								Source
0	0	1	1	0	0	1	1	CELL.SINGLE_H[5]
0	0	1	1	0	1	0	1	CELL.LONG_H[5]
0	0	1	1	0	1	1	0	CELL.DOUBLE_H1[1]
0	0	1	1	1	1	1	1	CELL.SINGLE_H[0]
0	1	0	1	0	0	1	1	CELL.SINGLE_H[4]
0	1	0	1	0	1	0	1	CELL.DOUBLE_H0[1]
0	1	0	1	0	1	1	0	CELL.LONG_H[4]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[1]
0	1	1	0	0	0	1	1	CELL.SINGLE_H[6]
0	1	1	0	0	1	0	1	CELL_N.LONG_H[2]
0	1	1	0	0	1	1	0	CELL_N.LONG_H[0]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[3]
1	1	1	1	0	0	1	1	CELL.DOUBLE_H0[0]
1	1	1	1	0	1	0	1	CELL.SINGLE_H[7]
1	1	1	1	0	1	1	0	CELL.DOUBLE_H1[0]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[2]

xc4000h IO_S0 switchbox INT muxes IMUX_CLB_F4
Bits								Destination
MAIN[9][10]	MAIN[9][11]	MAIN[8][9]	MAIN[8][10]	MAIN[10][9]	MAIN[8][12]	MAIN[9][12]	MAIN[10][11]	CELL.IMUX_CLB_F4
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_H[0]
0	0	0	1	1	0	1	1	CELL.DOUBLE_H1[0]
0	0	0	1	1	1	0	1	CELL_N.LONG_H[0]
0	0	1	1	1	1	1	1	CELL.SINGLE_H[1]
0	1	0	0	0	1	1	1	CELL.LONG_H[5]
0	1	0	0	1	1	1	0	CELL.LONG_H[3]
0	1	0	1	0	0	1	1	CELL.SINGLE_H[2]
0	1	0	1	0	1	0	1	CELL.SINGLE_H[3]
0	1	0	1	1	0	1	0	CELL.SINGLE_H[7]
0	1	0	1	1	1	0	0	CELL_N.LONG_H[1]
0	1	1	1	0	1	1	1	CELL.DOUBLE_H1[1]
0	1	1	1	1	1	1	0	CELL.DOUBLE_H0[1]
1	1	0	0	1	1	1	1	CELL.SINGLE_H[5]
1	1	0	1	1	0	1	1	CELL.DOUBLE_H0[0]
1	1	0	1	1	1	0	1	CELL.SINGLE_H[6]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[4]

xc4000h IO_S0 switchbox INT muxes IMUX_CLB_G2
Bits									Destination
MAIN[2][10]	MAIN[3][10]	MAIN[3][12]	MAIN[2][9]	MAIN[3][11]	MAIN[2][11]	MAIN[2][12]	MAIN[3][9]	MAIN[4][11]	CELL.IMUX_CLB_G2
									Source
0	0	0	1	1	1	1	1	1	CELL.SPECIAL_CLB_COUT0
0	0	1	0	0	1	1	1	1	CELL.LONG_H[4]
0	0	1	0	1	1	1	0	1	CELL.SINGLE_H[4]
0	0	1	0	1	1	1	1	0	CELL.LONG_H[5]
0	0	1	1	0	0	1	1	1	CELL.SINGLE_H[2]
0	0	1	1	0	1	0	1	1	CELL.SINGLE_H[3]
0	0	1	1	1	0	1	0	1	CELL.SINGLE_H[7]
0	0	1	1	1	0	1	1	0	CELL.DOUBLE_H0[0]
0	0	1	1	1	1	0	0	1	CELL_N.LONG_H[2]
0	0	1	1	1	1	0	1	0	CELL.SINGLE_H[6]
0	1	1	0	1	1	1	1	1	CELL.SINGLE_H[1]
0	1	1	1	1	0	1	1	1	CELL_N.LONG_H[0]
0	1	1	1	1	1	0	1	1	CELL.DOUBLE_H1[0]
1	0	1	1	0	1	1	1	1	CELL.DOUBLE_H1[1]
1	0	1	1	1	1	1	0	1	CELL.SINGLE_H[5]
1	0	1	1	1	1	1	1	0	CELL.DOUBLE_H0[1]
1	1	1	1	1	1	1	1	1	CELL.SINGLE_H[0]

xc4000h IO_S0 switchbox INT muxes IMUX_CLB_G4
Bits								Destination
MAIN[5][12]	MAIN[4][12]	MAIN[6][11]	MAIN[4][9]	MAIN[4][10]	MAIN[5][10]	MAIN[5][11]	MAIN[5][9]	CELL.IMUX_CLB_G4
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_H[0]
0	0	0	1	0	1	1	1	CELL.SINGLE_H[1]
0	0	0	1	1	1	0	1	CELL_N.LONG_H[0]
0	0	1	0	1	0	1	1	CELL.DOUBLE_H1[1]
0	0	1	0	1	1	1	0	CELL.LONG_H[3]
0	0	1	1	0	0	1	1	CELL.LONG_H[5]
0	0	1	1	0	1	1	0	CELL.DOUBLE_H0[1]
0	0	1	1	1	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	1	1	0	0	CELL.SINGLE_H[6]
0	1	0	1	1	1	1	1	CELL.DOUBLE_H1[0]
0	1	1	1	1	0	1	1	CELL.SINGLE_H[2]
0	1	1	1	1	1	1	0	CELL.DOUBLE_H0[0]
1	0	1	0	1	1	1	1	CELL.SINGLE_H[5]
1	0	1	1	0	1	1	1	CELL.SINGLE_H[4]
1	0	1	1	1	1	0	1	CELL_N.LONG_H[1]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[7]

xc4000h IO_S0 switchbox INT muxes IMUX_CLB_C2
Bits								Destination
MAIN[0][10]	MAIN[0][9]	MAIN[1][10]	MAIN[1][12]	MAIN[0][11]	MAIN[0][12]	MAIN[1][9]	MAIN[1][11]	CELL.IMUX_CLB_C2
								Source
0	0	0	0	1	1	1	1	CELL.LONG_H[4]
0	0	0	1	1	1	0	1	CELL.SINGLE_H[5]
0	0	0	1	1	1	1	0	CELL.LONG_H[3]
0	0	1	1	1	1	1	1	CELL.SINGLE_H[0]
0	1	0	0	0	1	1	1	CELL.SINGLE_H[2]
0	1	0	0	1	0	1	1	CELL.SINGLE_H[3]
0	1	0	1	0	1	0	1	CELL.SINGLE_H[7]
0	1	0	1	0	1	1	0	CELL.DOUBLE_H0[0]
0	1	0	1	1	0	0	1	CELL_N.LONG_H[1]
0	1	0	1	1	0	1	0	CELL.SINGLE_H[6]
0	1	1	1	0	1	1	1	CELL.DOUBLE_H1[0]
0	1	1	1	1	0	1	1	CELL_N.LONG_H[2]
1	1	0	0	1	1	1	1	CELL.DOUBLE_H1[1]
1	1	0	1	1	1	0	1	CELL.SINGLE_H[4]
1	1	0	1	1	1	1	0	CELL.DOUBLE_H0[1]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[1]

xc4000h IO_S0 switchbox INT muxes IMUX_CLB_C4
Bits								Destination
MAIN[7][10]	MAIN[8][11]	MAIN[6][10]	MAIN[6][9]	MAIN[7][12]	MAIN[7][11]	MAIN[6][12]	MAIN[7][9]	CELL.IMUX_CLB_C4
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_H[1]
0	0	0	1	1	0	1	1	CELL.DOUBLE_H0[0]
0	0	0	1	1	1	0	1	CELL.SINGLE_H[6]
0	0	1	1	1	1	1	1	CELL.SINGLE_H[0]
0	1	0	0	0	1	1	1	CELL.LONG_H[4]
0	1	0	0	1	1	1	0	CELL.LONG_H[3]
0	1	0	1	0	0	1	1	CELL.SINGLE_H[2]
0	1	0	1	0	1	0	1	CELL.SINGLE_H[3]
0	1	0	1	1	0	1	0	CELL.DOUBLE_H1[0]
0	1	0	1	1	1	0	0	CELL_N.LONG_H[1]
0	1	1	1	0	1	1	1	CELL.DOUBLE_H1[1]
0	1	1	1	1	1	1	0	CELL.DOUBLE_H0[1]
1	1	0	0	1	1	1	1	CELL.SINGLE_H[4]
1	1	0	1	1	0	1	1	CELL.SINGLE_H[7]
1	1	0	1	1	1	0	1	CELL_N.LONG_H[2]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[5]

xc4000h IO_S0 switchbox INT muxes IMUX_IO_O1[0]
Bits						Destination
MAIN[26][4]	MAIN[26][3]	MAIN[28][4]	MAIN[27][3]	MAIN[28][3]	MAIN[27][4]	CELL.IMUX_IO_O1[0]
						Source
0	0	0	1	1	1	CELL.DEC_H[2]
0	0	1	1	1	1	CELL.DOUBLE_V0[0]
0	1	0	0	1	1	CELL.DEC_H[0]
0	1	0	1	0	1	CELL.DEC_H[3]
0	1	0	1	1	0	CELL.LONG_V[5]
0	1	1	0	1	1	CELL.LONG_V[3]
0	1	1	1	0	1	CELL.LONG_V[4]
0	1	1	1	1	0	CELL.DEC_H[1]
1	1	0	1	1	1	CELL.DOUBLE_V1[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_S0 switchbox INT muxes IMUX_IO_O1[1]
Bits						Destination
MAIN[0][4]	MAIN[2][4]	MAIN[2][3]	MAIN[1][4]	MAIN[1][3]	MAIN[0][3]	CELL.IMUX_IO_O1[1]
						Source
0	0	0	1	1	1	CELL.DEC_H[0]
0	0	1	0	1	1	CELL.DEC_H[2]
0	0	1	1	0	1	CELL.DEC_H[3]
0	0	1	1	1	0	CELL_E.LONG_V[2]
0	1	0	1	1	1	CELL_E.LONG_V[1]
0	1	1	0	1	1	CELL.DEC_H[1]
0	1	1	1	0	1	CELL_E.LONG_V[0]
0	1	1	1	1	0	CELL_E.DOUBLE_V1[0]
1	0	1	1	1	1	CELL_E.DOUBLE_V0[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_S0 switchbox INT muxes IMUX_IO_OK[0]
Bits								Destination
MAIN[23][5]	MAIN[29][6]	MAIN[28][6]	MAIN[27][6]	MAIN[24][6]	MAIN[23][6]	MAIN[25][6]	MAIN[26][6]	CELL.IMUX_IO_OK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_V[3]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[2]

xc4000h IO_S0 switchbox INT muxes IMUX_IO_OK[1]
Bits								Destination
MAIN[10][5]	MAIN[12][6]	MAIN[13][6]	MAIN[11][6]	MAIN[10][6]	MAIN[13][5]	MAIN[12][5]	MAIN[11][5]	CELL.IMUX_IO_OK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_E.SINGLE_V[2]
0	1	1	1	1	1	0	1	CELL_E.SINGLE_V[3]
0	1	1	1	1	1	1	0	CELL_E.SINGLE_V[5]
1	1	1	1	1	1	1	1	CELL_E.SINGLE_V[4]

xc4000h IO_S0 switchbox INT muxes IMUX_IO_IK[0]
Bits								Destination
MAIN[18][5]	MAIN[19][5]	MAIN[20][5]	MAIN[21][5]	MAIN[19][6]	MAIN[18][6]	MAIN[20][6]	MAIN[21][6]	CELL.IMUX_IO_IK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_V[2]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[3]

xc4000h IO_S0 switchbox INT muxes IMUX_IO_IK[1]
Bits								Destination
MAIN[14][5]	MAIN[16][6]	MAIN[17][6]	MAIN[15][6]	MAIN[14][6]	MAIN[17][5]	MAIN[16][5]	MAIN[15][5]	CELL.IMUX_IO_IK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_E.SINGLE_V[2]
0	1	1	1	1	1	0	1	CELL_E.SINGLE_V[3]
0	1	1	1	1	1	1	0	CELL_E.SINGLE_V[4]
1	1	1	1	1	1	1	1	CELL_E.SINGLE_V[5]

xc4000h IO_S0 switchbox INT muxes IMUX_IO_T[0]
Bits								Destination
MAIN[5][2]	MAIN[3][2]	MAIN[6][0]	MAIN[6][1]	MAIN[6][2]	MAIN[4][2]	MAIN[5][1]	MAIN[4][1]	CELL.IMUX_IO_T[0]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	1	1	0	1	CELL.DEC_H[1]
0	0	1	0	1	1	1	0	CELL.GCLK[0]
0	0	1	1	0	0	1	1	CELL.LONG_IO_H[3]
0	0	1	1	0	1	0	1	CELL.LONG_IO_H[0]
0	0	1	1	0	1	1	0	CELL.LONG_IO_H[2]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_S0[1]
0	1	1	1	0	1	1	1	CELL.DOUBLE_IO_S1[0]
1	0	1	1	1	0	1	1	CELL.DOUBLE_IO_S1[1]
1	0	1	1	1	1	0	1	CELL.LONG_IO_H[1]
1	0	1	1	1	1	1	0	CELL.DEC_H[0]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_S0[0]

xc4000h IO_S0 switchbox INT muxes IMUX_IO_T[1]
Bits								Destination
MAIN[0][1]	MAIN[1][2]	MAIN[11][2]	MAIN[2][1]	MAIN[2][2]	MAIN[3][1]	MAIN[1][1]	MAIN[0][2]	CELL.IMUX_IO_T[1]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	0	1	1	1	CELL.LONG_IO_H[0]
0	0	1	0	1	0	1	1	CELL.GCLK[0]
0	0	1	1	0	1	0	1	CELL.LONG_IO_H[3]
0	0	1	1	0	1	1	0	CELL.LONG_IO_H[2]
0	0	1	1	1	0	0	1	CELL.DEC_H[0]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_S0[0]
0	1	1	1	1	1	0	1	CELL.LONG_IO_H[1]
0	1	1	1	1	1	1	0	CELL.DEC_H[1]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_S0[1]
1	0	1	1	1	0	1	1	CELL.DOUBLE_IO_S1[1]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_S1[0]

xc4000h IO_S0 switchbox INT muxes IMUX_HIO_O[0]
Bits	Destination
MAIN[26][0]	CELL.IMUX_HIO_O[0]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_F4

xc4000h IO_S0 switchbox INT muxes IMUX_HIO_O[1]
Bits	Destination
MAIN[21][0]	CELL.IMUX_HIO_O[1]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_F4

xc4000h IO_S0 switchbox INT muxes IMUX_HIO_O[2]
Bits	Destination
MAIN[12][0]	CELL.IMUX_HIO_O[2]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_G4

xc4000h IO_S0 switchbox INT muxes IMUX_HIO_O[3]
Bits	Destination
MAIN[8][0]	CELL.IMUX_HIO_O[3]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_G4

xc4000h IO_S0 switchbox INT muxes IMUX_HIO_T[0]
Bits	Destination
MAIN[28][0]	CELL.IMUX_HIO_T[0]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_OK[0]

xc4000h IO_S0 switchbox INT muxes IMUX_HIO_T[1]
Bits	Destination
MAIN[21][1]	CELL.IMUX_HIO_T[1]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_IK[0]

xc4000h IO_S0 switchbox INT muxes IMUX_HIO_T[2]
Bits	Destination
MAIN[14][0]	CELL.IMUX_HIO_T[2]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_IK[1]

xc4000h IO_S0 switchbox INT muxes IMUX_HIO_T[3]
Bits	Destination
MAIN[5][0]	CELL.IMUX_HIO_T[3]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_OK[1]

xc4000h IO_S0 switchbox INT muxes OUT_IO_SN_I1[0]
Bits	Destination
MAIN[20][1]	CELL.OUT_IO_SN_I1[0]
	Source
0	CELL.OUT_HIO_I[1]
1	CELL.OUT_HIO_I[0]

xc4000h IO_S0 switchbox INT muxes OUT_IO_SN_I1[1]
Bits	Destination
MAIN[15][0]	CELL.OUT_IO_SN_I1[1]
	Source
0	CELL.OUT_HIO_I[2]
1	CELL.OUT_HIO_I[3]

xc4000h IO_S0 switchbox INT muxes OUT_IO_SN_I2[0]
Bits	Destination
MAIN[31][0]	CELL.OUT_IO_SN_I2[0]
	Source
0	CELL.OUT_HIO_I[0]
1	CELL.OUT_HIO_I[1]

xc4000h IO_S0 switchbox INT muxes OUT_IO_SN_I2[1]
Bits	Destination
MAIN[3][0]	CELL.OUT_IO_SN_I2[1]
	Source
0	CELL.OUT_HIO_I[3]
1	CELL.OUT_HIO_I[2]

Bels HIO

xc4000h IO_S0 bel HIO pins
Pin	Direction	HIO[0]	HIO[1]	HIO[2]	HIO[3]
O	in	CELL.IMUX_HIO_O[0] invert by !MAIN[27][0]	CELL.IMUX_HIO_O[1] invert by !MAIN[22][0]	CELL.IMUX_HIO_O[2] invert by !MAIN[13][0]	CELL.IMUX_HIO_O[3] invert by !MAIN[7][0]
T	in	CELL.IMUX_HIO_T[0] invert by !MAIN[29][0]	CELL.IMUX_HIO_T[1] invert by !MAIN[20][0]	CELL.IMUX_HIO_T[2] invert by !MAIN[14][1]	CELL.IMUX_HIO_T[3] invert by !MAIN[4][0]
I	out	CELL.OUT_HIO_I[0]	CELL.OUT_HIO_I[1]	CELL.OUT_HIO_I[2]	CELL.OUT_HIO_I[3]

xc4000h IO_S0 bel HIO attribute bits
Attribute	HIO[0]	HIO[1]	HIO[2]	HIO[3]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
ISTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OSTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OMODE	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]
I_INV	!MAIN[32][0]	!MAIN[19][0]	!MAIN[16][0]	!MAIN[2][0]
READBACK_I bit 0	!MAIN[18][2]	!MAIN[18][3]	!MAIN[16][2]	!MAIN[17][3]

xc4000h IO_S0 enum IO_PULL
HIO[0].PULL	MAIN[24][0]	MAIN[25][0]
HIO[1].PULL	MAIN[24][1]	MAIN[22][1]
HIO[2].PULL	MAIN[11][1]	MAIN[13][1]
HIO[3].PULL	MAIN[10][0]	MAIN[9][0]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

xc4000h IO_S0 enum IO_STD
HIO[0].ISTD	MAIN[33][0]
HIO[1].ISTD	MAIN[18][0]
HIO[2].ISTD	MAIN[15][1]
HIO[3].ISTD	MAIN[1][0]
CMOS	0
TTL	1

xc4000h IO_S0 enum IO_STD
HIO[0].OSTD	MAIN[34][0]
HIO[1].OSTD	MAIN[18][1]
HIO[2].OSTD	MAIN[16][1]
HIO[3].OSTD	MAIN[0][0]
CMOS	1
TTL	0

xc4000h IO_S0 enum HIO_OMODE
HIO[0].OMODE	MAIN[23][0]
HIO[1].OMODE	MAIN[23][1]
HIO[2].OMODE	MAIN[12][1]
HIO[3].OMODE	MAIN[11][0]
CAP	1
RES	0

Bels DEC

xc4000h IO_S0 bel DEC pins
Pin	Direction	DEC[0]	DEC[1]	DEC[2]
I	in	CELL.OUT_IO_SN_I1[0]	CELL.IMUX_CLB_C4	CELL.OUT_IO_SN_I1[1]
O1	bidir	CELL.DEC_H[0]	CELL.DEC_H[0]	CELL.DEC_H[0]
O2	bidir	CELL.DEC_H[1]	CELL.DEC_H[1]	CELL.DEC_H[1]
O3	bidir	CELL.DEC_H[2]	CELL.DEC_H[2]	CELL.DEC_H[2]
O4	bidir	CELL.DEC_H[3]	CELL.DEC_H[3]	CELL.DEC_H[3]

xc4000h IO_S0 bel DEC attribute bits
Attribute	DEC[0]	DEC[1]	DEC[2]
O1_P	!MAIN[14][3]	!MAIN[12][4]	MAIN[13][3]
O1_N	MAIN[14][4]	MAIN[12][3]	!MAIN[13][4]
O2_P	!MAIN[9][3]	!MAIN[11][4]	MAIN[10][3]
O2_N	MAIN[9][4]	MAIN[11][3]	!MAIN[10][4]
O3_P	!MAIN[3][3]	!MAIN[5][4]	MAIN[4][3]
O3_N	MAIN[3][4]	MAIN[5][3]	!MAIN[4][4]
O4_P	!MAIN[8][3]	!MAIN[6][4]	MAIN[7][3]
O4_N	MAIN[8][4]	MAIN[6][3]	!MAIN[7][4]

Bel wires

xc4000h IO_S0 bel wires
Wire	Pins
CELL.DEC_H[0]	DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_H[1]	DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.DEC_H[2]	DEC[0].O3, DEC[1].O3, DEC[2].O3
CELL.DEC_H[3]	DEC[0].O4, DEC[1].O4, DEC[2].O4
CELL.IMUX_CLB_C4	DEC[1].I
CELL.IMUX_HIO_O[0]	HIO[0].O
CELL.IMUX_HIO_O[1]	HIO[1].O
CELL.IMUX_HIO_O[2]	HIO[2].O
CELL.IMUX_HIO_O[3]	HIO[3].O
CELL.IMUX_HIO_T[0]	HIO[0].T
CELL.IMUX_HIO_T[1]	HIO[1].T
CELL.IMUX_HIO_T[2]	HIO[2].T
CELL.IMUX_HIO_T[3]	HIO[3].T
CELL.OUT_IO_SN_I1[0]	DEC[0].I
CELL.OUT_IO_SN_I1[1]	DEC[2].I
CELL.OUT_HIO_I[0]	HIO[0].I
CELL.OUT_HIO_I[1]	HIO[1].I
CELL.OUT_HIO_I[2]	HIO[2].I
CELL.OUT_HIO_I[3]	HIO[3].I

Bitstream

xc4000h IO_S0 rect MAIN
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B12	INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7]	INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7]	INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7]	INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5]	-	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0]	INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0	-	INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3]	INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6]	-	-	INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S	INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S	INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0	INT: mux CELL.IMUX_CLB_F2 bit 3	INT: mux CELL.IMUX_CLB_F2 bit 7	INT: mux CELL.IMUX_CLB_F4 bit 1	INT: mux CELL.IMUX_CLB_F4 bit 2	INT: mux CELL.IMUX_CLB_C4 bit 3	INT: mux CELL.IMUX_CLB_C4 bit 1	INT: mux CELL.IMUX_CLB_G4 bit 7	INT: mux CELL.IMUX_CLB_G4 bit 6	INT: mux CELL.IMUX_CLB_G2 bit 6	INT: mux CELL.IMUX_CLB_G2 bit 2	INT: mux CELL.IMUX_CLB_C2 bit 4	INT: mux CELL.IMUX_CLB_C2 bit 2
B11	-	INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4]	INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6]	INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6]	-	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2]	-	INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0]	-	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0]	-	-	-	-	-	-	-	-	-	INT: mux CELL.IMUX_CLB_F2 bit 2	INT: mux CELL.IMUX_CLB_F2 bit 4	INT: mux CELL.IMUX_CLB_F4 bit 0	INT: mux CELL.IMUX_CLB_F4 bit 6	INT: mux CELL.IMUX_CLB_C4 bit 6	INT: mux CELL.IMUX_CLB_C4 bit 2	INT: mux CELL.IMUX_CLB_G4 bit 5	INT: mux CELL.IMUX_CLB_G4 bit 1	INT: mux CELL.IMUX_CLB_G2 bit 0	INT: mux CELL.IMUX_CLB_G2 bit 4	INT: mux CELL.IMUX_CLB_G2 bit 3	INT: mux CELL.IMUX_CLB_C2 bit 0	INT: mux CELL.IMUX_CLB_C2 bit 3
B10	INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5]	-	INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6]	INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3]	INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3]	-	-	-	-	-	INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S	INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S	INT: mux CELL.IMUX_CLB_F2 bit 1	INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0	INT: mux CELL.IMUX_CLB_F2 bit 6	INT: mux CELL.IMUX_CLB_F4 bit 7	INT: mux CELL.IMUX_CLB_F4 bit 4	INT: mux CELL.IMUX_CLB_C4 bit 7	INT: mux CELL.IMUX_CLB_C4 bit 5	INT: mux CELL.IMUX_CLB_G4 bit 2	INT: mux CELL.IMUX_CLB_G4 bit 3	INT: mux CELL.IMUX_CLB_G2 bit 7	INT: mux CELL.IMUX_CLB_G2 bit 8	INT: mux CELL.IMUX_CLB_C2 bit 5	INT: mux CELL.IMUX_CLB_C2 bit 7
B9	-	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4]	INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4]	INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1]	-	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0]	-	INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0	INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_SN_I2[1]	INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_SN_I2[1]	INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_SN_I2[1]	-	INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0	INT: mux CELL.IMUX_CLB_F2 bit 0	INT: mux CELL.IMUX_CLB_F2 bit 5	INT: mux CELL.IMUX_CLB_F4 bit 3	-	INT: mux CELL.IMUX_CLB_F4 bit 5	INT: mux CELL.IMUX_CLB_C4 bit 0	INT: mux CELL.IMUX_CLB_C4 bit 4	INT: mux CELL.IMUX_CLB_G4 bit 0	INT: mux CELL.IMUX_CLB_G4 bit 4	INT: mux CELL.IMUX_CLB_G2 bit 1	INT: mux CELL.IMUX_CLB_G2 bit 5	INT: mux CELL.IMUX_CLB_C2 bit 1	INT: mux CELL.IMUX_CLB_C2 bit 6
B8	INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4]	INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5]	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5]	INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1]	INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1]	INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0]	-	-	-	-	-	-	INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5]	INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1]	INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5]	-	-	INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4]	-	INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0	-	-	-	-	-	-	-
B7	-	-	-	-	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5]	INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1]	-	INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1]	INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.LONG_V[1] bit 1	INT: mux CELL.LONG_V[2] bit 0	INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1	INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0]	INT: mux CELL.IMUX_IO_OK[0] bit 6	INT: mux CELL.IMUX_IO_OK[0] bit 5	INT: mux CELL.IMUX_IO_OK[0] bit 4	INT: mux CELL.IMUX_IO_OK[0] bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 1	INT: mux CELL.IMUX_IO_OK[0] bit 3	INT: mux CELL.IMUX_IO_OK[0] bit 2	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0]	INT: mux CELL.IMUX_IO_IK[0] bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 1	INT: mux CELL.IMUX_IO_IK[0] bit 3	INT: mux CELL.IMUX_IO_IK[0] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 5	INT: mux CELL.IMUX_IO_IK[1] bit 6	INT: mux CELL.IMUX_IO_IK[1] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 3	INT: mux CELL.IMUX_IO_OK[1] bit 5	INT: mux CELL.IMUX_IO_OK[1] bit 6	INT: mux CELL.IMUX_IO_OK[1] bit 4	INT: mux CELL.IMUX_IO_OK[1] bit 3	INT: mux CELL.LONG_V[5] bit 0	INT: mux CELL.LONG_V[5] bit 2	INT: mux CELL.LONG_V[3] bit 1	INT: mux CELL.LONG_V[3] bit 2	-	INT: mux CELL.LONG_IO_H[0] bit 1	-	INT: mux CELL.LONG_V[4] bit 1	INT: mux CELL.LONG_V[4] bit 2	-
B5	INT: mux CELL.LONG_V[1] bit 3	INT: mux CELL.LONG_V[1] bit 0	INT: mux CELL.LONG_V[1] bit 2	INT: mux CELL.LONG_V[2] bit 1	INT: mux CELL.LONG_V[2] bit 3	INT: mux CELL.LONG_V[2] bit 2	INT: mux CELL.LONG_V[0] bit 1	INT: mux CELL.LONG_V[0] bit 0	INT: mux CELL.LONG_V[0] bit 2	INT: mux CELL.LONG_V[0] bit 3	INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_IO_SN_I1[0]	INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[4]	INT: mux CELL.IMUX_IO_OK[0] bit 7	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.IMUX_IO_IK[0] bit 4	INT: mux CELL.IMUX_IO_IK[0] bit 5	INT: mux CELL.IMUX_IO_IK[0] bit 6	INT: mux CELL.IMUX_IO_IK[0] bit 7	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 0	INT: mux CELL.IMUX_IO_IK[1] bit 7	INT: mux CELL.IMUX_IO_OK[1] bit 2	INT: mux CELL.IMUX_IO_OK[1] bit 1	INT: mux CELL.IMUX_IO_OK[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 7	INT: mux CELL.LONG_V[5] bit 1	INT: mux CELL.LONG_V[5] bit 3	INT: mux CELL.LONG_V[3] bit 0	INT: mux CELL.LONG_V[3] bit 3	INT: mux CELL.LONG_V[4] bit 3	INT: mux CELL.LONG_IO_H[3] bit 1	-	INT: mux CELL.LONG_V[4] bit 0	-	-
B4	INT: !pass CELL.SINGLE_V[4] ← CELL.DEC_H[1]	INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_IO_H[3]	INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_IO_H[2]	INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.SINGLE_V[7] ← CELL.DEC_H[0]	INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[2]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1	INT: mux CELL.IMUX_IO_O1[0] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 5	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0]	-	INT: mux CELL.LONG_IO_H[3] bit 0	INT: mux CELL.LONG_IO_H[2] bit 0	INT: mux CELL.LONG_IO_H[2] bit 1	INT: mux CELL.LONG_IO_H[2] bit 2	INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[3]	INT: mux CELL.LONG_IO_H[1] bit 1	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[1]	INT: mux CELL.LONG_IO_H[0] bit 0	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[0]	DEC[0]: O1_N	DEC[2]: ! O1_N	DEC[1]: ! O1_P	DEC[1]: ! O2_P	DEC[2]: ! O2_N	DEC[0]: O2_N	DEC[0]: O4_N	DEC[2]: ! O4_N	DEC[1]: ! O4_P	DEC[1]: ! O3_P	DEC[2]: ! O3_N	DEC[0]: O3_N	INT: mux CELL.IMUX_IO_O1[1] bit 4	INT: mux CELL.IMUX_IO_O1[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 5
B3	INT: mux CELL.DBUF_IO_H[1] bit 1	INT: mux CELL.DBUF_IO_H[1] bit 2	INT: mux CELL.DBUF_IO_H[1] bit 3	INT: !bipass CELL.DOUBLE_IO_S0[3] = CELL.DOUBLE_IO_S2[3]	INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_S1[3]	INT: !bipass CELL.DOUBLE_IO_S0[2] = CELL.DOUBLE_IO_S2[2]	-	INT: mux CELL.IMUX_IO_O1[0] bit 1	INT: mux CELL.IMUX_IO_O1[0] bit 2	INT: mux CELL.IMUX_IO_O1[0] bit 4	INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S1[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S1[1]	INT: mux CELL.LONG_IO_H[1] bit 3	INT: mux CELL.LONG_IO_H[2] bit 3	INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0]	-	HIO[1]: ! READBACK_I bit 0	HIO[3]: ! READBACK_I bit 0	INT: mux CELL.LONG_IO_H[1] bit 0	INT: mux CELL.LONG_IO_H[1] bit 2	DEC[0]: ! O1_P	DEC[2]: O1_P	DEC[1]: O1_N	DEC[1]: O2_N	DEC[2]: O2_P	DEC[0]: ! O2_P	DEC[0]: ! O4_P	DEC[2]: O4_P	DEC[1]: O4_N	DEC[1]: O3_N	DEC[2]: O3_P	DEC[0]: ! O3_P	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.IMUX_IO_O1[1] bit 0
B2	INT: !pass CELL.DOUBLE_IO_S2[0] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_S2[1] ← CELL.DBUF_IO_H[0]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S2[3]	INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_S2[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S0[3]	INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_S0[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S1[2]	INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_S1[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S0[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S0[1]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S2[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S2[0]	INT: !bipass CELL.DOUBLE_IO_S0[0] = CELL.DOUBLE_IO_S2[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S0[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S0[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S1[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S1[0]	HIO[0]: ! READBACK_I bit 0	-	HIO[2]: ! READBACK_I bit 0	-	-	-	-	INT: mux CELL.IMUX_IO_T[1] bit 5	INT: !pass CELL.DOUBLE_IO_S0[0] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_S0[1] ← CELL.DBUF_IO_H[1]	INT: mux CELL.DBUF_IO_H[0] bit 2	INT: mux CELL.DBUF_IO_H[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 7	INT: mux CELL.IMUX_IO_T[0] bit 2	INT: mux CELL.IMUX_IO_T[0] bit 6	INT: mux CELL.IMUX_IO_T[1] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 6	INT: mux CELL.IMUX_IO_T[1] bit 0
B1	INT: !pass CELL.DOUBLE_IO_S2[3] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_S2[2] ← CELL.DBUF_IO_H[0]	INT: mux CELL.DBUF_IO_H[1] bit 0	INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_S0[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S1[3]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S2[2]	INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_S2[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S0[2]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S2[1]	INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S2[1]	INT: !bipass CELL.DOUBLE_IO_S0[1] = CELL.DOUBLE_IO_S2[1]	HIO[1]: PULL bit 1	HIO[1]: OMODE bit 0	HIO[1]: PULL bit 0	INT: mux CELL.IMUX_HIO_T[1] bit 0	INT: mux CELL.OUT_IO_SN_I1[0] bit 0	-	HIO[1]: OSTD bit 0	-	HIO[2]: OSTD bit 0	HIO[2]: ISTD bit 0	HIO[2]: !invert T	HIO[2]: PULL bit 0	HIO[2]: OMODE bit 0	HIO[2]: PULL bit 1	INT: !pass CELL.DOUBLE_IO_S0[3] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_S0[2] ← CELL.DBUF_IO_H[1]	INT: mux CELL.DBUF_IO_H[0] bit 0	INT: mux CELL.DBUF_IO_H[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 4	INT: mux CELL.IMUX_IO_T[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 0	INT: mux CELL.IMUX_IO_T[1] bit 2	INT: mux CELL.IMUX_IO_T[1] bit 4	INT: mux CELL.IMUX_IO_T[1] bit 1	INT: mux CELL.IMUX_IO_T[1] bit 7
B0	-	HIO[0]: OSTD bit 0	HIO[0]: ISTD bit 0	HIO[0]: ! I_INV	INT: mux CELL.OUT_IO_SN_I2[0] bit 0	-	HIO[0]: !invert T	INT: mux CELL.IMUX_HIO_T[0] bit 0	HIO[0]: !invert O	INT: mux CELL.IMUX_HIO_O[0] bit 0	HIO[0]: PULL bit 0	HIO[0]: PULL bit 1	HIO[0]: OMODE bit 0	HIO[1]: !invert O	INT: mux CELL.IMUX_HIO_O[1] bit 0	HIO[1]: !invert T	HIO[1]: ! I_INV	HIO[1]: ISTD bit 0	-	HIO[2]: ! I_INV	INT: mux CELL.OUT_IO_SN_I1[1] bit 0	INT: mux CELL.IMUX_HIO_T[2] bit 0	HIO[2]: !invert O	INT: mux CELL.IMUX_HIO_O[2] bit 0	HIO[3]: OMODE bit 0	HIO[3]: PULL bit 1	HIO[3]: PULL bit 0	INT: mux CELL.IMUX_HIO_O[3] bit 0	HIO[3]: !invert O	INT: mux CELL.IMUX_IO_T[0] bit 5	INT: mux CELL.IMUX_HIO_T[3] bit 0	HIO[3]: !invert T	INT: mux CELL.OUT_IO_SN_I2[1] bit 0	HIO[3]: ! I_INV	HIO[3]: ISTD bit 0	HIO[3]: OSTD bit 0

xc4000h IO_S0 rect MAIN_E
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile IO_S0_E

Cells: 4

Switchbox INT

xc4000h IO_S0_E switchbox INT programmable buffers
Destination	Source	Bit
CELL.LONG_H[3]	CELL.SINGLE_V[4]	!MAIN[24][5]
CELL.LONG_H[4]	CELL.SINGLE_V[5]	!MAIN[14][8]
CELL.LONG_H[5]	CELL.SINGLE_V[6]	!MAIN[18][12]
CELL.LONG_V[0]	CELL.SINGLE_H_E[1]	!MAIN[13][8]
CELL.LONG_V[1]	CELL.SINGLE_H_E[2]	!MAIN[33][11]
CELL.LONG_V[2]	CELL.SINGLE_H_E[3]	!MAIN[19][12]
CELL.LONG_V[3]	CELL.SINGLE_H[4]	!MAIN[9][8]
CELL.LONG_V[4]	CELL.SINGLE_H[5]	!MAIN[12][8]
CELL.LONG_V[5]	CELL.SINGLE_H[6]	!MAIN[30][11]

xc4000h IO_S0_E switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[0]	CELL.TIE_0	!MAIN[7][8]
CELL.SINGLE_H[0]	CELL.OUT_IO_SN_I2[0]	!MAIN[19][9]
CELL.SINGLE_H[1]	CELL.OUT_IO_SN_I2[1]	!MAIN[15][9]
CELL.SINGLE_H[2]	CELL.OUT_CLB_XQ_S	!MAIN[14][10]
CELL.SINGLE_H[3]	CELL.TIE_0	!MAIN[11][10]
CELL.SINGLE_H[3]	CELL.OUT_CLB_X_S	!MAIN[13][12]
CELL.SINGLE_H[4]	CELL.LONG_V[3]	!MAIN[30][7]
CELL.SINGLE_H[4]	CELL.OUT_IO_SN_I2[0]	!MAIN[18][9]
CELL.SINGLE_H[5]	CELL.LONG_V[4]	!MAIN[23][7]
CELL.SINGLE_H[5]	CELL.OUT_IO_SN_I2[1]	!MAIN[17][9]
CELL.SINGLE_H[6]	CELL.TIE_0	!MAIN[13][9]
CELL.SINGLE_H[6]	CELL.LONG_V[5]	!MAIN[29][12]
CELL.SINGLE_H[6]	CELL.OUT_CLB_XQ_S	!MAIN[15][10]
CELL.SINGLE_H[7]	CELL.TIE_0	!MAIN[12][12]
CELL.SINGLE_H[7]	CELL.OUT_CLB_X_S	!MAIN[14][12]
CELL.SINGLE_H_E[1]	CELL.LONG_V[0]	!MAIN[27][8]
CELL.SINGLE_H_E[2]	CELL.LONG_V[1]	!MAIN[35][12]
CELL.SINGLE_H_E[3]	CELL.LONG_V[2]	!MAIN[29][9]
CELL.SINGLE_V[0]	CELL.TIE_0	!MAIN[21][9]
CELL.SINGLE_V[0]	CELL.DEC_H[3]	!MAIN[19][4]
CELL.SINGLE_V[0]	CELL.OUT_IO_SN_I2_E1	!MAIN[22][5]
CELL.SINGLE_V[1]	CELL.LONG_IO_H[0]	!MAIN[15][4]
CELL.SINGLE_V[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[22][6]
CELL.SINGLE_V[2]	CELL.LONG_IO_H[1]	!MAIN[17][4]
CELL.SINGLE_V[2]	CELL.OUT_IO_SN_I1[0]	!MAIN[25][4]
CELL.SINGLE_V[3]	CELL.DEC_H[2]	!MAIN[30][4]
CELL.SINGLE_V[3]	CELL.OUT_IO_SN_I1_E1	!MAIN[29][4]
CELL.SINGLE_V[4]	CELL.LONG_H[3]	!MAIN[21][10]
CELL.SINGLE_V[4]	CELL.DEC_H[1]	!MAIN[35][4]
CELL.SINGLE_V[4]	CELL.OUT_IO_SN_I2_E1	!MAIN[35][6]
CELL.SINGLE_V[5]	CELL.LONG_H[4]	!MAIN[35][8]
CELL.SINGLE_V[5]	CELL.LONG_IO_H[2]	!MAIN[33][4]
CELL.SINGLE_V[5]	CELL.OUT_IO_SN_I2[0]	!MAIN[32][6]
CELL.SINGLE_V[6]	CELL.LONG_H[5]	!MAIN[35][10]
CELL.SINGLE_V[6]	CELL.LONG_IO_H[3]	!MAIN[34][4]
CELL.SINGLE_V[6]	CELL.OUT_IO_SN_I1[0]	!MAIN[25][5]
CELL.SINGLE_V[7]	CELL.TIE_0	!MAIN[21][12]
CELL.SINGLE_V[7]	CELL.DEC_H[0]	!MAIN[31][4]
CELL.SINGLE_V[7]	CELL.OUT_IO_SN_I1_E1	!MAIN[32][4]
CELL.DOUBLE_H0[0]	CELL.OUT_CLB_XQ_S	!MAIN[13][10]
CELL.DOUBLE_H0[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[20][9]
CELL.DOUBLE_H1[0]	CELL.OUT_CLB_X_S	!MAIN[15][12]
CELL.DOUBLE_H1[1]	CELL.OUT_IO_SN_I2[1]	!MAIN[16][9]
CELL.DOUBLE_V0[0]	CELL.OUT_IO_SN_I1_E1	!MAIN[21][3]
CELL.DOUBLE_V0[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[30][6]
CELL.DOUBLE_V1[0]	CELL.OUT_IO_SN_I1[0]	!MAIN[20][3]
CELL.DOUBLE_V1[1]	CELL.OUT_IO_SN_I2_E1	!MAIN[31][6]
CELL.DOUBLE_IO_S0[0]	CELL.DBUF_IO_H[1]	!MAIN[10][2]
CELL.DOUBLE_IO_S0[1]	CELL.DBUF_IO_H[1]	!MAIN[9][2]
CELL.DOUBLE_IO_S0[2]	CELL.DBUF_IO_H[1]	!MAIN[9][1]
CELL.DOUBLE_IO_S0[3]	CELL.DBUF_IO_H[1]	!MAIN[10][1]
CELL.DOUBLE_IO_S2[0]	CELL.DBUF_IO_H[0]	!MAIN[35][2]
CELL.DOUBLE_IO_S2[1]	CELL.DBUF_IO_H[0]	!MAIN[34][2]
CELL.DOUBLE_IO_S2[2]	CELL.DBUF_IO_H[0]	!MAIN[34][1]
CELL.DOUBLE_IO_S2[3]	CELL.DBUF_IO_H[0]	!MAIN[35][1]

xc4000h IO_S0_E switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.SINGLE_H_E[0]	!MAIN[23][9]
CELL.SINGLE_H[0]	CELL.SINGLE_V[0]	!MAIN[22][8]
CELL.SINGLE_H[0]	CELL.SINGLE_V_S[0]	!MAIN[25][7]
CELL.SINGLE_H[1]	CELL.SINGLE_H_E[1]	!MAIN[25][8]
CELL.SINGLE_H[1]	CELL.SINGLE_V[1]	!MAIN[24][8]
CELL.SINGLE_H[1]	CELL.SINGLE_V_S[1]	!MAIN[24][7]
CELL.SINGLE_H[2]	CELL.SINGLE_H_E[2]	!MAIN[27][11]
CELL.SINGLE_H[2]	CELL.SINGLE_V[2]	!MAIN[26][11]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[2]	!MAIN[28][11]
CELL.SINGLE_H[3]	CELL.SINGLE_H_E[3]	!MAIN[26][10]
CELL.SINGLE_H[3]	CELL.SINGLE_V[3]	!MAIN[23][10]
CELL.SINGLE_H[3]	CELL.SINGLE_V_S[3]	!MAIN[25][10]
CELL.SINGLE_H[4]	CELL.SINGLE_H_E[4]	!MAIN[31][9]
CELL.SINGLE_H[4]	CELL.SINGLE_V[4]	!MAIN[34][9]
CELL.SINGLE_H[4]	CELL.SINGLE_V_S[4]	!MAIN[30][9]
CELL.SINGLE_H[5]	CELL.SINGLE_H_E[5]	!MAIN[30][8]
CELL.SINGLE_H[5]	CELL.SINGLE_V[5]	!MAIN[31][7]
CELL.SINGLE_H[5]	CELL.SINGLE_V_S[5]	!MAIN[32][8]
CELL.SINGLE_H[6]	CELL.SINGLE_H_E[6]	!MAIN[30][10]
CELL.SINGLE_H[6]	CELL.SINGLE_V[6]	!MAIN[31][11]
CELL.SINGLE_H[6]	CELL.SINGLE_V_S[6]	!MAIN[31][10]
CELL.SINGLE_H[7]	CELL.SINGLE_H_E[7]	!MAIN[33][12]
CELL.SINGLE_H[7]	CELL.SINGLE_V[7]	!MAIN[30][12]
CELL.SINGLE_H[7]	CELL.SINGLE_V_S[7]	!MAIN[32][11]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V[0]	!MAIN[21][8]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V_S[0]	!MAIN[23][8]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V[1]	!MAIN[25][9]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V_S[1]	!MAIN[26][8]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V[2]	!MAIN[26][12]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V_S[2]	!MAIN[27][12]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V[3]	!MAIN[27][10]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V_S[3]	!MAIN[28][10]
CELL.SINGLE_H_E[4]	CELL.SINGLE_V[4]	!MAIN[34][11]
CELL.SINGLE_H_E[4]	CELL.SINGLE_V_S[4]	!MAIN[32][9]
CELL.SINGLE_H_E[5]	CELL.SINGLE_V[5]	!MAIN[31][8]
CELL.SINGLE_H_E[5]	CELL.SINGLE_V_S[5]	!MAIN[33][8]
CELL.SINGLE_H_E[6]	CELL.SINGLE_V[6]	!MAIN[29][10]
CELL.SINGLE_H_E[6]	CELL.SINGLE_V_S[6]	!MAIN[32][10]
CELL.SINGLE_H_E[7]	CELL.SINGLE_V[7]	!MAIN[32][12]
CELL.SINGLE_H_E[7]	CELL.SINGLE_V_S[7]	!MAIN[34][12]
CELL.SINGLE_V[0]	CELL.SINGLE_V_S[0]	!MAIN[24][9]
CELL.SINGLE_V[0]	CELL.DOUBLE_IO_S0[0]	!MAIN[22][2]
CELL.SINGLE_V[0]	CELL.DOUBLE_IO_S2[0]	!MAIN[24][2]
CELL.SINGLE_V[1]	CELL.SINGLE_V_S[1]	!MAIN[26][7]
CELL.SINGLE_V[1]	CELL.DOUBLE_IO_S1[0]	!MAIN[19][2]
CELL.SINGLE_V[2]	CELL.SINGLE_V_S[2]	!MAIN[25][12]
CELL.SINGLE_V[2]	CELL.DOUBLE_IO_S0[1]	!MAIN[27][2]
CELL.SINGLE_V[2]	CELL.DOUBLE_IO_S2[1]	!MAIN[26][1]
CELL.SINGLE_V[3]	CELL.SINGLE_V_S[3]	!MAIN[22][10]
CELL.SINGLE_V[3]	CELL.DOUBLE_IO_S1[1]	!MAIN[25][3]
CELL.SINGLE_V[4]	CELL.SINGLE_V_S[4]	!MAIN[33][9]
CELL.SINGLE_V[4]	CELL.DOUBLE_IO_S0[2]	!MAIN[30][2]
CELL.SINGLE_V[4]	CELL.DOUBLE_IO_S2[2]	!MAIN[29][1]
CELL.SINGLE_V[5]	CELL.SINGLE_V_S[5]	!MAIN[34][8]
CELL.SINGLE_V[5]	CELL.DOUBLE_IO_S1[2]	!MAIN[28][2]
CELL.SINGLE_V[6]	CELL.SINGLE_V_S[6]	!MAIN[33][10]
CELL.SINGLE_V[6]	CELL.DOUBLE_IO_S0[3]	!MAIN[32][1]
CELL.SINGLE_V[6]	CELL.DOUBLE_IO_S2[3]	!MAIN[32][2]
CELL.SINGLE_V[7]	CELL.SINGLE_V_S[7]	!MAIN[31][12]
CELL.SINGLE_V[7]	CELL.DOUBLE_IO_S1[3]	!MAIN[31][3]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_H2[0]	!MAIN[24][12]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_V0[0]	!MAIN[22][12]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_V2[0]	!MAIN[23][12]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_H2[1]	!MAIN[28][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_V0[1]	!MAIN[27][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_V2[1]	!MAIN[28][7]
CELL.DOUBLE_H2[0]	CELL.DOUBLE_V0[0]	!MAIN[24][10]
CELL.DOUBLE_H2[0]	CELL.DOUBLE_V2[0]	!MAIN[24][11]
CELL.DOUBLE_H2[1]	CELL.DOUBLE_V0[1]	!MAIN[28][8]
CELL.DOUBLE_H2[1]	CELL.DOUBLE_V2[1]	!MAIN[29][8]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_V2[0]	!MAIN[22][11]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_S0[1]	!MAIN[26][2]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_S1[1]	!MAIN[24][3]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_S2[1]	!MAIN[27][1]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_V2[1]	!MAIN[29][7]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_S0[2]	!MAIN[28][1]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_S1[2]	!MAIN[29][2]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_S2[2]	!MAIN[30][1]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_S0[0]	!MAIN[21][2]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_S1[0]	!MAIN[20][2]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_S2[0]	!MAIN[25][2]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_S0[3]	!MAIN[31][2]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_S1[3]	!MAIN[31][1]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_S2[3]	!MAIN[33][2]
CELL.DOUBLE_IO_S0[0]	CELL.DOUBLE_IO_S2[0]	!MAIN[23][2]
CELL.DOUBLE_IO_S0[1]	CELL.DOUBLE_IO_S2[1]	!MAIN[25][1]
CELL.DOUBLE_IO_S0[2]	CELL.DOUBLE_IO_S2[2]	!MAIN[30][3]
CELL.DOUBLE_IO_S0[3]	CELL.DOUBLE_IO_S2[3]	!MAIN[32][3]

xc4000h IO_S0_E switchbox INT muxes DBUF_IO_H[0]
Bits				Destination
MAIN[7][2]	MAIN[8][2]	MAIN[7][1]	MAIN[8][1]	CELL.DBUF_IO_H[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_S0[0]
0	1	0	1	CELL.DOUBLE_IO_S0[2]
0	1	1	0	CELL.DOUBLE_IO_S0[3]
1	1	1	1	CELL.DOUBLE_IO_S0[1]

xc4000h IO_S0_E switchbox INT muxes DBUF_IO_H[1]
Bits				Destination
MAIN[33][3]	MAIN[34][3]	MAIN[35][3]	MAIN[33][1]	CELL.DBUF_IO_H[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_S2[1]
0	1	0	1	CELL.DOUBLE_IO_S2[2]
0	1	1	0	CELL.DOUBLE_IO_S2[3]
1	1	1	1	CELL.DOUBLE_IO_S2[0]

xc4000h IO_S0_E switchbox INT muxes LONG_V[0]
Bits				Destination
MAIN[26][5]	MAIN[27][5]	MAIN[29][5]	MAIN[28][5]	CELL.LONG_V[0]
				Source
0	0	0	1	CELL.LONG_IO_H[0]
0	0	1	0	CELL.DEC_H[0]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_S0_E switchbox INT muxes LONG_V[1]
Bits				Destination
MAIN[35][5]	MAIN[33][5]	MAIN[34][6]	MAIN[34][5]	CELL.LONG_V[1]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_S0_E switchbox INT muxes LONG_V[2]
Bits				Destination
MAIN[31][5]	MAIN[30][5]	MAIN[32][5]	MAIN[33][6]	CELL.LONG_V[2]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_S0_E switchbox INT muxes LONG_V[3]
Bits				Destination
MAIN[6][5]	MAIN[6][6]	MAIN[7][6]	MAIN[7][5]	CELL.LONG_V[3]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_S0_E switchbox INT muxes LONG_V[4]
Bits				Destination
MAIN[5][5]	MAIN[1][6]	MAIN[2][6]	MAIN[2][5]	CELL.LONG_V[4]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_S0_E switchbox INT muxes LONG_V[5]
Bits				Destination
MAIN[8][5]	MAIN[8][6]	MAIN[9][5]	MAIN[9][6]	CELL.LONG_V[5]
				Source
0	0	0	1	CELL.LONG_IO_H[3]
0	0	1	0	CELL.DEC_H[3]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_S0_E switchbox INT muxes LONG_IO_H[0]
Bits		Destination
MAIN[4][6]	MAIN[16][4]	CELL.LONG_IO_H[0]
		Source
0	0	CELL.LONG_V[0]
0	1	CELL.SINGLE_V[1]
1	1	off

xc4000h IO_S0_E switchbox INT muxes LONG_IO_H[1]
Bits				Destination
MAIN[23][3]	MAIN[15][3]	MAIN[18][4]	MAIN[16][3]	CELL.LONG_IO_H[1]
				Source
0	0	0	1	CELL.LONG_V[1]
0	0	1	0	CELL.LONG_V[3]
0	1	1	1	CELL.SINGLE_V[2]
1	1	1	1	off

xc4000h IO_S0_E switchbox INT muxes LONG_IO_H[2]
Bits				Destination
MAIN[22][3]	MAIN[20][4]	MAIN[21][4]	MAIN[22][4]	CELL.LONG_IO_H[2]
				Source
0	0	0	1	CELL.LONG_V[2]
0	0	1	0	CELL.LONG_V[4]
0	1	1	1	CELL.SINGLE_V[5]
1	1	1	1	off

xc4000h IO_S0_E switchbox INT muxes LONG_IO_H[3]
Bits		Destination
MAIN[4][5]	MAIN[23][4]	CELL.LONG_IO_H[3]
		Source
0	0	CELL.LONG_V[5]
0	1	CELL.SINGLE_V[6]
1	1	off

xc4000h IO_S0_E switchbox INT muxes IMUX_CLB_F2
Bits								Destination
MAIN[10][12]	MAIN[10][10]	MAIN[11][9]	MAIN[11][11]	MAIN[11][12]	MAIN[12][11]	MAIN[12][10]	MAIN[12][9]	CELL.IMUX_CLB_F2
								Source
0	0	1	1	0	0	1	1	CELL.SINGLE_H[5]
0	0	1	1	0	1	0	1	CELL.LONG_H[5]
0	0	1	1	0	1	1	0	CELL.DOUBLE_H1[1]
0	0	1	1	1	1	1	1	CELL.SINGLE_H[0]
0	1	0	1	0	0	1	1	CELL.SINGLE_H[4]
0	1	0	1	0	1	0	1	CELL.DOUBLE_H0[1]
0	1	0	1	0	1	1	0	CELL.LONG_H[4]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[1]
0	1	1	0	0	0	1	1	CELL.SINGLE_H[6]
0	1	1	0	0	1	0	1	CELL_N.LONG_H[2]
0	1	1	0	0	1	1	0	CELL_N.LONG_H[0]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[3]
1	1	1	1	0	0	1	1	CELL.DOUBLE_H0[0]
1	1	1	1	0	1	0	1	CELL.SINGLE_H[7]
1	1	1	1	0	1	1	0	CELL.DOUBLE_H1[0]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[2]

xc4000h IO_S0_E switchbox INT muxes IMUX_CLB_F4
Bits								Destination
MAIN[9][10]	MAIN[9][11]	MAIN[8][9]	MAIN[8][10]	MAIN[10][9]	MAIN[8][12]	MAIN[9][12]	MAIN[10][11]	CELL.IMUX_CLB_F4
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_H[0]
0	0	0	1	1	0	1	1	CELL.DOUBLE_H1[0]
0	0	0	1	1	1	0	1	CELL_N.LONG_H[0]
0	0	1	1	1	1	1	1	CELL.SINGLE_H[1]
0	1	0	0	0	1	1	1	CELL.LONG_H[5]
0	1	0	0	1	1	1	0	CELL.LONG_H[3]
0	1	0	1	0	0	1	1	CELL.SINGLE_H[2]
0	1	0	1	0	1	0	1	CELL.SINGLE_H[3]
0	1	0	1	1	0	1	0	CELL.SINGLE_H[7]
0	1	0	1	1	1	0	0	CELL_N.LONG_H[1]
0	1	1	1	0	1	1	1	CELL.DOUBLE_H1[1]
0	1	1	1	1	1	1	0	CELL.DOUBLE_H0[1]
1	1	0	0	1	1	1	1	CELL.SINGLE_H[5]
1	1	0	1	1	0	1	1	CELL.DOUBLE_H0[0]
1	1	0	1	1	1	0	1	CELL.SINGLE_H[6]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[4]

xc4000h IO_S0_E switchbox INT muxes IMUX_CLB_G2
Bits									Destination
MAIN[2][10]	MAIN[3][10]	MAIN[3][12]	MAIN[2][9]	MAIN[3][11]	MAIN[2][11]	MAIN[2][12]	MAIN[3][9]	MAIN[4][11]	CELL.IMUX_CLB_G2
									Source
0	0	0	1	1	1	1	1	1	CELL.SPECIAL_CLB_COUT0
0	0	1	0	0	1	1	1	1	CELL.LONG_H[4]
0	0	1	0	1	1	1	0	1	CELL.SINGLE_H[4]
0	0	1	0	1	1	1	1	0	CELL.LONG_H[5]
0	0	1	1	0	0	1	1	1	CELL.SINGLE_H[2]
0	0	1	1	0	1	0	1	1	CELL.SINGLE_H[3]
0	0	1	1	1	0	1	0	1	CELL.SINGLE_H[7]
0	0	1	1	1	0	1	1	0	CELL.DOUBLE_H0[0]
0	0	1	1	1	1	0	0	1	CELL_N.LONG_H[2]
0	0	1	1	1	1	0	1	0	CELL.SINGLE_H[6]
0	1	1	0	1	1	1	1	1	CELL.SINGLE_H[1]
0	1	1	1	1	0	1	1	1	CELL_N.LONG_H[0]
0	1	1	1	1	1	0	1	1	CELL.DOUBLE_H1[0]
1	0	1	1	0	1	1	1	1	CELL.DOUBLE_H1[1]
1	0	1	1	1	1	1	0	1	CELL.SINGLE_H[5]
1	0	1	1	1	1	1	1	0	CELL.DOUBLE_H0[1]
1	1	1	1	1	1	1	1	1	CELL.SINGLE_H[0]

xc4000h IO_S0_E switchbox INT muxes IMUX_CLB_G4
Bits								Destination
MAIN[5][12]	MAIN[4][12]	MAIN[6][11]	MAIN[4][9]	MAIN[4][10]	MAIN[5][10]	MAIN[5][11]	MAIN[5][9]	CELL.IMUX_CLB_G4
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_H[0]
0	0	0	1	0	1	1	1	CELL.SINGLE_H[1]
0	0	0	1	1	1	0	1	CELL_N.LONG_H[0]
0	0	1	0	1	0	1	1	CELL.DOUBLE_H1[1]
0	0	1	0	1	1	1	0	CELL.LONG_H[3]
0	0	1	1	0	0	1	1	CELL.LONG_H[5]
0	0	1	1	0	1	1	0	CELL.DOUBLE_H0[1]
0	0	1	1	1	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	1	1	0	0	CELL.SINGLE_H[6]
0	1	0	1	1	1	1	1	CELL.DOUBLE_H1[0]
0	1	1	1	1	0	1	1	CELL.SINGLE_H[2]
0	1	1	1	1	1	1	0	CELL.DOUBLE_H0[0]
1	0	1	0	1	1	1	1	CELL.SINGLE_H[5]
1	0	1	1	0	1	1	1	CELL.SINGLE_H[4]
1	0	1	1	1	1	0	1	CELL_N.LONG_H[1]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[7]

xc4000h IO_S0_E switchbox INT muxes IMUX_CLB_C2
Bits								Destination
MAIN[0][10]	MAIN[0][9]	MAIN[1][10]	MAIN[1][12]	MAIN[0][11]	MAIN[0][12]	MAIN[1][9]	MAIN[1][11]	CELL.IMUX_CLB_C2
								Source
0	0	0	0	1	1	1	1	CELL.LONG_H[4]
0	0	0	1	1	1	0	1	CELL.SINGLE_H[5]
0	0	0	1	1	1	1	0	CELL.LONG_H[3]
0	0	1	1	1	1	1	1	CELL.SINGLE_H[0]
0	1	0	0	0	1	1	1	CELL.SINGLE_H[2]
0	1	0	0	1	0	1	1	CELL.SINGLE_H[3]
0	1	0	1	0	1	0	1	CELL.SINGLE_H[7]
0	1	0	1	0	1	1	0	CELL.DOUBLE_H0[0]
0	1	0	1	1	0	0	1	CELL_N.LONG_H[1]
0	1	0	1	1	0	1	0	CELL.SINGLE_H[6]
0	1	1	1	0	1	1	1	CELL.DOUBLE_H1[0]
0	1	1	1	1	0	1	1	CELL_N.LONG_H[2]
1	1	0	0	1	1	1	1	CELL.DOUBLE_H1[1]
1	1	0	1	1	1	0	1	CELL.SINGLE_H[4]
1	1	0	1	1	1	1	0	CELL.DOUBLE_H0[1]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[1]

xc4000h IO_S0_E switchbox INT muxes IMUX_CLB_C4
Bits								Destination
MAIN[7][10]	MAIN[8][11]	MAIN[6][10]	MAIN[6][9]	MAIN[7][12]	MAIN[7][11]	MAIN[6][12]	MAIN[7][9]	CELL.IMUX_CLB_C4
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_H[1]
0	0	0	1	1	0	1	1	CELL.DOUBLE_H0[0]
0	0	0	1	1	1	0	1	CELL.SINGLE_H[6]
0	0	1	1	1	1	1	1	CELL.SINGLE_H[0]
0	1	0	0	0	1	1	1	CELL.LONG_H[4]
0	1	0	0	1	1	1	0	CELL.LONG_H[3]
0	1	0	1	0	0	1	1	CELL.SINGLE_H[2]
0	1	0	1	0	1	0	1	CELL.SINGLE_H[3]
0	1	0	1	1	0	1	0	CELL.DOUBLE_H1[0]
0	1	0	1	1	1	0	0	CELL_N.LONG_H[1]
0	1	1	1	0	1	1	1	CELL.DOUBLE_H1[1]
0	1	1	1	1	1	1	0	CELL.DOUBLE_H0[1]
1	1	0	0	1	1	1	1	CELL.SINGLE_H[4]
1	1	0	1	1	0	1	1	CELL.SINGLE_H[7]
1	1	0	1	1	1	0	1	CELL_N.LONG_H[2]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[5]

xc4000h IO_S0_E switchbox INT muxes IMUX_IO_O1[0]
Bits						Destination
MAIN[26][4]	MAIN[26][3]	MAIN[28][4]	MAIN[27][3]	MAIN[28][3]	MAIN[27][4]	CELL.IMUX_IO_O1[0]
						Source
0	0	0	1	1	1	CELL.DEC_H[2]
0	0	1	1	1	1	CELL.DOUBLE_V0[0]
0	1	0	0	1	1	CELL.DEC_H[0]
0	1	0	1	0	1	CELL.DEC_H[3]
0	1	0	1	1	0	CELL.LONG_V[5]
0	1	1	0	1	1	CELL.LONG_V[3]
0	1	1	1	0	1	CELL.LONG_V[4]
0	1	1	1	1	0	CELL.DEC_H[1]
1	1	0	1	1	1	CELL.DOUBLE_V1[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_S0_E switchbox INT muxes IMUX_IO_O1[1]
Bits						Destination
MAIN[0][4]	MAIN[2][4]	MAIN[2][3]	MAIN[1][4]	MAIN[1][3]	MAIN[0][3]	CELL.IMUX_IO_O1[1]
						Source
0	0	0	1	1	1	CELL.DEC_H[0]
0	0	1	0	1	1	CELL.DEC_H[2]
0	0	1	1	0	1	CELL.DEC_H[3]
0	0	1	1	1	0	CELL_E.LONG_V[2]
0	1	0	1	1	1	CELL_E.LONG_V[1]
0	1	1	0	1	1	CELL.DEC_H[1]
0	1	1	1	0	1	CELL_E.LONG_V[0]
0	1	1	1	1	0	CELL_E.DOUBLE_V1[0]
1	0	1	1	1	1	CELL_E.DOUBLE_V0[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_S0_E switchbox INT muxes IMUX_IO_OK[0]
Bits								Destination
MAIN[23][5]	MAIN[29][6]	MAIN[28][6]	MAIN[27][6]	MAIN[24][6]	MAIN[23][6]	MAIN[25][6]	MAIN[26][6]	CELL.IMUX_IO_OK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_V[3]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[2]

xc4000h IO_S0_E switchbox INT muxes IMUX_IO_OK[1]
Bits								Destination
MAIN[10][5]	MAIN[12][6]	MAIN[13][6]	MAIN[11][6]	MAIN[10][6]	MAIN[13][5]	MAIN[12][5]	MAIN[11][5]	CELL.IMUX_IO_OK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_E.SINGLE_V[2]
0	1	1	1	1	1	0	1	CELL_E.SINGLE_V[3]
0	1	1	1	1	1	1	0	CELL_E.SINGLE_V[5]
1	1	1	1	1	1	1	1	CELL_E.SINGLE_V[4]

xc4000h IO_S0_E switchbox INT muxes IMUX_IO_IK[0]
Bits								Destination
MAIN[18][5]	MAIN[19][5]	MAIN[20][5]	MAIN[21][5]	MAIN[19][6]	MAIN[18][6]	MAIN[20][6]	MAIN[21][6]	CELL.IMUX_IO_IK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_V[2]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[3]

xc4000h IO_S0_E switchbox INT muxes IMUX_IO_IK[1]
Bits								Destination
MAIN[14][5]	MAIN[16][6]	MAIN[17][6]	MAIN[15][6]	MAIN[14][6]	MAIN[17][5]	MAIN[16][5]	MAIN[15][5]	CELL.IMUX_IO_IK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_E.SINGLE_V[2]
0	1	1	1	1	1	0	1	CELL_E.SINGLE_V[3]
0	1	1	1	1	1	1	0	CELL_E.SINGLE_V[4]
1	1	1	1	1	1	1	1	CELL_E.SINGLE_V[5]

xc4000h IO_S0_E switchbox INT muxes IMUX_IO_T[0]
Bits								Destination
MAIN[5][2]	MAIN[3][2]	MAIN[6][0]	MAIN[6][1]	MAIN[6][2]	MAIN[4][2]	MAIN[5][1]	MAIN[4][1]	CELL.IMUX_IO_T[0]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	1	1	0	1	CELL.DEC_H[1]
0	0	1	0	1	1	1	0	CELL.GCLK[0]
0	0	1	1	0	0	1	1	CELL.LONG_IO_H[3]
0	0	1	1	0	1	0	1	CELL.LONG_IO_H[0]
0	0	1	1	0	1	1	0	CELL.LONG_IO_H[2]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_S0[1]
0	1	1	1	0	1	1	1	CELL.DOUBLE_IO_S1[0]
1	0	1	1	1	0	1	1	CELL.DOUBLE_IO_S1[1]
1	0	1	1	1	1	0	1	CELL.LONG_IO_H[1]
1	0	1	1	1	1	1	0	CELL.DEC_H[0]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_S0[0]

xc4000h IO_S0_E switchbox INT muxes IMUX_IO_T[1]
Bits								Destination
MAIN[0][1]	MAIN[1][2]	MAIN[11][2]	MAIN[2][1]	MAIN[2][2]	MAIN[3][1]	MAIN[1][1]	MAIN[0][2]	CELL.IMUX_IO_T[1]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	0	1	1	1	CELL.LONG_IO_H[0]
0	0	1	0	1	0	1	1	CELL.GCLK[0]
0	0	1	1	0	1	0	1	CELL.LONG_IO_H[3]
0	0	1	1	0	1	1	0	CELL.LONG_IO_H[2]
0	0	1	1	1	0	0	1	CELL.DEC_H[0]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_S0[0]
0	1	1	1	1	1	0	1	CELL.LONG_IO_H[1]
0	1	1	1	1	1	1	0	CELL.DEC_H[1]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_S0[1]
1	0	1	1	1	0	1	1	CELL.DOUBLE_IO_S1[1]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_S1[0]

xc4000h IO_S0_E switchbox INT muxes IMUX_HIO_O[0]
Bits	Destination
MAIN[26][0]	CELL.IMUX_HIO_O[0]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_F4

xc4000h IO_S0_E switchbox INT muxes IMUX_HIO_O[1]
Bits	Destination
MAIN[21][0]	CELL.IMUX_HIO_O[1]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_F4

xc4000h IO_S0_E switchbox INT muxes IMUX_HIO_O[2]
Bits	Destination
MAIN[12][0]	CELL.IMUX_HIO_O[2]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_G4

xc4000h IO_S0_E switchbox INT muxes IMUX_HIO_O[3]
Bits	Destination
MAIN[8][0]	CELL.IMUX_HIO_O[3]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_G4

xc4000h IO_S0_E switchbox INT muxes IMUX_HIO_T[0]
Bits	Destination
MAIN[28][0]	CELL.IMUX_HIO_T[0]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_OK[0]

xc4000h IO_S0_E switchbox INT muxes IMUX_HIO_T[1]
Bits	Destination
MAIN[21][1]	CELL.IMUX_HIO_T[1]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_IK[0]

xc4000h IO_S0_E switchbox INT muxes IMUX_HIO_T[2]
Bits	Destination
MAIN[14][0]	CELL.IMUX_HIO_T[2]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_IK[1]

xc4000h IO_S0_E switchbox INT muxes IMUX_HIO_T[3]
Bits	Destination
MAIN[5][0]	CELL.IMUX_HIO_T[3]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_OK[1]

xc4000h IO_S0_E switchbox INT muxes OUT_IO_SN_I1[0]
Bits	Destination
MAIN[20][1]	CELL.OUT_IO_SN_I1[0]
	Source
0	CELL.OUT_HIO_I[1]
1	CELL.OUT_HIO_I[0]

xc4000h IO_S0_E switchbox INT muxes OUT_IO_SN_I1[1]
Bits	Destination
MAIN[15][0]	CELL.OUT_IO_SN_I1[1]
	Source
0	CELL.OUT_HIO_I[2]
1	CELL.OUT_HIO_I[3]

xc4000h IO_S0_E switchbox INT muxes OUT_IO_SN_I2[0]
Bits	Destination
MAIN[31][0]	CELL.OUT_IO_SN_I2[0]
	Source
0	CELL.OUT_HIO_I[0]
1	CELL.OUT_HIO_I[1]

xc4000h IO_S0_E switchbox INT muxes OUT_IO_SN_I2[1]
Bits	Destination
MAIN[3][0]	CELL.OUT_IO_SN_I2[1]
	Source
0	CELL.OUT_HIO_I[3]
1	CELL.OUT_HIO_I[2]

Bels HIO

xc4000h IO_S0_E bel HIO pins
Pin	Direction	HIO[0]	HIO[1]	HIO[2]	HIO[3]
O	in	CELL.IMUX_HIO_O[0] invert by !MAIN[27][0]	CELL.IMUX_HIO_O[1] invert by !MAIN[22][0]	CELL.IMUX_HIO_O[2] invert by !MAIN[13][0]	CELL.IMUX_HIO_O[3] invert by !MAIN[7][0]
T	in	CELL.IMUX_HIO_T[0] invert by !MAIN[29][0]	CELL.IMUX_HIO_T[1] invert by !MAIN[20][0]	CELL.IMUX_HIO_T[2] invert by !MAIN[14][1]	CELL.IMUX_HIO_T[3] invert by !MAIN[4][0]
I	out	CELL.OUT_HIO_I[0]	CELL.OUT_HIO_I[1]	CELL.OUT_HIO_I[2]	CELL.OUT_HIO_I[3]
CLKIN	out	-	-	-	CELL.OUT_IO_CLKIN

xc4000h IO_S0_E bel HIO attribute bits
Attribute	HIO[0]	HIO[1]	HIO[2]	HIO[3]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
ISTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OSTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OMODE	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]
I_INV	!MAIN[32][0]	!MAIN[19][0]	!MAIN[16][0]	!MAIN[2][0]
READBACK_I bit 0	!MAIN[18][2]	!MAIN[18][3]	!MAIN[16][2]	!MAIN[17][3]

xc4000h IO_S0_E enum IO_PULL
HIO[0].PULL	MAIN[24][0]	MAIN[25][0]
HIO[1].PULL	MAIN[24][1]	MAIN[22][1]
HIO[2].PULL	MAIN[11][1]	MAIN[13][1]
HIO[3].PULL	MAIN[10][0]	MAIN[9][0]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

xc4000h IO_S0_E enum IO_STD
HIO[0].ISTD	MAIN[33][0]
HIO[1].ISTD	MAIN[18][0]
HIO[2].ISTD	MAIN[15][1]
HIO[3].ISTD	MAIN[1][0]
CMOS	0
TTL	1

xc4000h IO_S0_E enum IO_STD
HIO[0].OSTD	MAIN[34][0]
HIO[1].OSTD	MAIN[18][1]
HIO[2].OSTD	MAIN[16][1]
HIO[3].OSTD	MAIN[0][0]
CMOS	1
TTL	0

xc4000h IO_S0_E enum HIO_OMODE
HIO[0].OMODE	MAIN[23][0]
HIO[1].OMODE	MAIN[23][1]
HIO[2].OMODE	MAIN[12][1]
HIO[3].OMODE	MAIN[11][0]
CAP	1
RES	0

Bels DEC

xc4000h IO_S0_E bel DEC pins
Pin	Direction	DEC[0]	DEC[1]	DEC[2]
I	in	CELL.OUT_IO_SN_I1[0]	CELL.IMUX_CLB_C4	CELL.OUT_IO_SN_I1[1]
O1	bidir	CELL.DEC_H[0]	CELL.DEC_H[0]	CELL.DEC_H[0]
O2	bidir	CELL.DEC_H[1]	CELL.DEC_H[1]	CELL.DEC_H[1]
O3	bidir	CELL.DEC_H[2]	CELL.DEC_H[2]	CELL.DEC_H[2]
O4	bidir	CELL.DEC_H[3]	CELL.DEC_H[3]	CELL.DEC_H[3]

xc4000h IO_S0_E bel DEC attribute bits
Attribute	DEC[0]	DEC[1]	DEC[2]
O1_P	!MAIN[14][3]	!MAIN[12][4]	MAIN[13][3]
O1_N	MAIN[14][4]	MAIN[12][3]	!MAIN[13][4]
O2_P	!MAIN[9][3]	!MAIN[11][4]	MAIN[10][3]
O2_N	MAIN[9][4]	MAIN[11][3]	!MAIN[10][4]
O3_P	!MAIN[3][3]	!MAIN[5][4]	MAIN[4][3]
O3_N	MAIN[3][4]	MAIN[5][3]	!MAIN[4][4]
O4_P	!MAIN[8][3]	!MAIN[6][4]	MAIN[7][3]
O4_N	MAIN[8][4]	MAIN[6][3]	!MAIN[7][4]

Bel wires

xc4000h IO_S0_E bel wires
Wire	Pins
CELL.DEC_H[0]	DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_H[1]	DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.DEC_H[2]	DEC[0].O3, DEC[1].O3, DEC[2].O3
CELL.DEC_H[3]	DEC[0].O4, DEC[1].O4, DEC[2].O4
CELL.IMUX_CLB_C4	DEC[1].I
CELL.IMUX_HIO_O[0]	HIO[0].O
CELL.IMUX_HIO_O[1]	HIO[1].O
CELL.IMUX_HIO_O[2]	HIO[2].O
CELL.IMUX_HIO_O[3]	HIO[3].O
CELL.IMUX_HIO_T[0]	HIO[0].T
CELL.IMUX_HIO_T[1]	HIO[1].T
CELL.IMUX_HIO_T[2]	HIO[2].T
CELL.IMUX_HIO_T[3]	HIO[3].T
CELL.OUT_IO_SN_I1[0]	DEC[0].I
CELL.OUT_IO_SN_I1[1]	DEC[2].I
CELL.OUT_HIO_I[0]	HIO[0].I
CELL.OUT_HIO_I[1]	HIO[1].I
CELL.OUT_HIO_I[2]	HIO[2].I
CELL.OUT_HIO_I[3]	HIO[3].I
CELL.OUT_IO_CLKIN	HIO[3].CLKIN

Bitstream

xc4000h IO_S0_E rect MAIN
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B12	INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7]	INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7]	INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7]	INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5]	-	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0]	INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0	-	INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3]	INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6]	-	-	INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S	INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S	INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0	INT: mux CELL.IMUX_CLB_F2 bit 3	INT: mux CELL.IMUX_CLB_F2 bit 7	INT: mux CELL.IMUX_CLB_F4 bit 1	INT: mux CELL.IMUX_CLB_F4 bit 2	INT: mux CELL.IMUX_CLB_C4 bit 3	INT: mux CELL.IMUX_CLB_C4 bit 1	INT: mux CELL.IMUX_CLB_G4 bit 7	INT: mux CELL.IMUX_CLB_G4 bit 6	INT: mux CELL.IMUX_CLB_G2 bit 6	INT: mux CELL.IMUX_CLB_G2 bit 2	INT: mux CELL.IMUX_CLB_C2 bit 4	INT: mux CELL.IMUX_CLB_C2 bit 2
B11	-	INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4]	INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6]	INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6]	-	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2]	-	INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0]	-	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0]	-	-	-	-	-	-	-	-	-	INT: mux CELL.IMUX_CLB_F2 bit 2	INT: mux CELL.IMUX_CLB_F2 bit 4	INT: mux CELL.IMUX_CLB_F4 bit 0	INT: mux CELL.IMUX_CLB_F4 bit 6	INT: mux CELL.IMUX_CLB_C4 bit 6	INT: mux CELL.IMUX_CLB_C4 bit 2	INT: mux CELL.IMUX_CLB_G4 bit 5	INT: mux CELL.IMUX_CLB_G4 bit 1	INT: mux CELL.IMUX_CLB_G2 bit 0	INT: mux CELL.IMUX_CLB_G2 bit 4	INT: mux CELL.IMUX_CLB_G2 bit 3	INT: mux CELL.IMUX_CLB_C2 bit 0	INT: mux CELL.IMUX_CLB_C2 bit 3
B10	INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5]	-	INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6]	INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3]	INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3]	-	-	-	-	-	INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S	INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S	INT: mux CELL.IMUX_CLB_F2 bit 1	INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0	INT: mux CELL.IMUX_CLB_F2 bit 6	INT: mux CELL.IMUX_CLB_F4 bit 7	INT: mux CELL.IMUX_CLB_F4 bit 4	INT: mux CELL.IMUX_CLB_C4 bit 7	INT: mux CELL.IMUX_CLB_C4 bit 5	INT: mux CELL.IMUX_CLB_G4 bit 2	INT: mux CELL.IMUX_CLB_G4 bit 3	INT: mux CELL.IMUX_CLB_G2 bit 7	INT: mux CELL.IMUX_CLB_G2 bit 8	INT: mux CELL.IMUX_CLB_C2 bit 5	INT: mux CELL.IMUX_CLB_C2 bit 7
B9	-	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4]	INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4]	INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1]	-	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0]	-	INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0	INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_SN_I2[1]	INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_SN_I2[1]	INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_SN_I2[1]	-	INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0	INT: mux CELL.IMUX_CLB_F2 bit 0	INT: mux CELL.IMUX_CLB_F2 bit 5	INT: mux CELL.IMUX_CLB_F4 bit 3	-	INT: mux CELL.IMUX_CLB_F4 bit 5	INT: mux CELL.IMUX_CLB_C4 bit 0	INT: mux CELL.IMUX_CLB_C4 bit 4	INT: mux CELL.IMUX_CLB_G4 bit 0	INT: mux CELL.IMUX_CLB_G4 bit 4	INT: mux CELL.IMUX_CLB_G2 bit 1	INT: mux CELL.IMUX_CLB_G2 bit 5	INT: mux CELL.IMUX_CLB_C2 bit 1	INT: mux CELL.IMUX_CLB_C2 bit 6
B8	INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4]	INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5]	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5]	INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1]	INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1]	INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0]	-	-	-	-	-	-	INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5]	INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1]	INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5]	-	-	INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4]	-	INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0	-	-	-	-	-	-	-
B7	-	-	-	-	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5]	INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1]	-	INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1]	INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.LONG_V[1] bit 1	INT: mux CELL.LONG_V[2] bit 0	INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1	INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0]	INT: mux CELL.IMUX_IO_OK[0] bit 6	INT: mux CELL.IMUX_IO_OK[0] bit 5	INT: mux CELL.IMUX_IO_OK[0] bit 4	INT: mux CELL.IMUX_IO_OK[0] bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 1	INT: mux CELL.IMUX_IO_OK[0] bit 3	INT: mux CELL.IMUX_IO_OK[0] bit 2	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0]	INT: mux CELL.IMUX_IO_IK[0] bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 1	INT: mux CELL.IMUX_IO_IK[0] bit 3	INT: mux CELL.IMUX_IO_IK[0] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 5	INT: mux CELL.IMUX_IO_IK[1] bit 6	INT: mux CELL.IMUX_IO_IK[1] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 3	INT: mux CELL.IMUX_IO_OK[1] bit 5	INT: mux CELL.IMUX_IO_OK[1] bit 6	INT: mux CELL.IMUX_IO_OK[1] bit 4	INT: mux CELL.IMUX_IO_OK[1] bit 3	INT: mux CELL.LONG_V[5] bit 0	INT: mux CELL.LONG_V[5] bit 2	INT: mux CELL.LONG_V[3] bit 1	INT: mux CELL.LONG_V[3] bit 2	-	INT: mux CELL.LONG_IO_H[0] bit 1	-	INT: mux CELL.LONG_V[4] bit 1	INT: mux CELL.LONG_V[4] bit 2	-
B5	INT: mux CELL.LONG_V[1] bit 3	INT: mux CELL.LONG_V[1] bit 0	INT: mux CELL.LONG_V[1] bit 2	INT: mux CELL.LONG_V[2] bit 1	INT: mux CELL.LONG_V[2] bit 3	INT: mux CELL.LONG_V[2] bit 2	INT: mux CELL.LONG_V[0] bit 1	INT: mux CELL.LONG_V[0] bit 0	INT: mux CELL.LONG_V[0] bit 2	INT: mux CELL.LONG_V[0] bit 3	INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_IO_SN_I1[0]	INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[4]	INT: mux CELL.IMUX_IO_OK[0] bit 7	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.IMUX_IO_IK[0] bit 4	INT: mux CELL.IMUX_IO_IK[0] bit 5	INT: mux CELL.IMUX_IO_IK[0] bit 6	INT: mux CELL.IMUX_IO_IK[0] bit 7	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 0	INT: mux CELL.IMUX_IO_IK[1] bit 7	INT: mux CELL.IMUX_IO_OK[1] bit 2	INT: mux CELL.IMUX_IO_OK[1] bit 1	INT: mux CELL.IMUX_IO_OK[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 7	INT: mux CELL.LONG_V[5] bit 1	INT: mux CELL.LONG_V[5] bit 3	INT: mux CELL.LONG_V[3] bit 0	INT: mux CELL.LONG_V[3] bit 3	INT: mux CELL.LONG_V[4] bit 3	INT: mux CELL.LONG_IO_H[3] bit 1	-	INT: mux CELL.LONG_V[4] bit 0	-	-
B4	INT: !pass CELL.SINGLE_V[4] ← CELL.DEC_H[1]	INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_IO_H[3]	INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_IO_H[2]	INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.SINGLE_V[7] ← CELL.DEC_H[0]	INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[2]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1	INT: mux CELL.IMUX_IO_O1[0] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 5	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0]	-	INT: mux CELL.LONG_IO_H[3] bit 0	INT: mux CELL.LONG_IO_H[2] bit 0	INT: mux CELL.LONG_IO_H[2] bit 1	INT: mux CELL.LONG_IO_H[2] bit 2	INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[3]	INT: mux CELL.LONG_IO_H[1] bit 1	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[1]	INT: mux CELL.LONG_IO_H[0] bit 0	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[0]	DEC[0]: O1_N	DEC[2]: ! O1_N	DEC[1]: ! O1_P	DEC[1]: ! O2_P	DEC[2]: ! O2_N	DEC[0]: O2_N	DEC[0]: O4_N	DEC[2]: ! O4_N	DEC[1]: ! O4_P	DEC[1]: ! O3_P	DEC[2]: ! O3_N	DEC[0]: O3_N	INT: mux CELL.IMUX_IO_O1[1] bit 4	INT: mux CELL.IMUX_IO_O1[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 5
B3	INT: mux CELL.DBUF_IO_H[1] bit 1	INT: mux CELL.DBUF_IO_H[1] bit 2	INT: mux CELL.DBUF_IO_H[1] bit 3	INT: !bipass CELL.DOUBLE_IO_S0[3] = CELL.DOUBLE_IO_S2[3]	INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_S1[3]	INT: !bipass CELL.DOUBLE_IO_S0[2] = CELL.DOUBLE_IO_S2[2]	-	INT: mux CELL.IMUX_IO_O1[0] bit 1	INT: mux CELL.IMUX_IO_O1[0] bit 2	INT: mux CELL.IMUX_IO_O1[0] bit 4	INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S1[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S1[1]	INT: mux CELL.LONG_IO_H[1] bit 3	INT: mux CELL.LONG_IO_H[2] bit 3	INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0]	-	HIO[1]: ! READBACK_I bit 0	HIO[3]: ! READBACK_I bit 0	INT: mux CELL.LONG_IO_H[1] bit 0	INT: mux CELL.LONG_IO_H[1] bit 2	DEC[0]: ! O1_P	DEC[2]: O1_P	DEC[1]: O1_N	DEC[1]: O2_N	DEC[2]: O2_P	DEC[0]: ! O2_P	DEC[0]: ! O4_P	DEC[2]: O4_P	DEC[1]: O4_N	DEC[1]: O3_N	DEC[2]: O3_P	DEC[0]: ! O3_P	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.IMUX_IO_O1[1] bit 0
B2	INT: !pass CELL.DOUBLE_IO_S2[0] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_S2[1] ← CELL.DBUF_IO_H[0]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S2[3]	INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_S2[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S0[3]	INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_S0[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S1[2]	INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_S1[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S0[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S0[1]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S2[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S2[0]	INT: !bipass CELL.DOUBLE_IO_S0[0] = CELL.DOUBLE_IO_S2[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S0[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S0[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S1[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S1[0]	HIO[0]: ! READBACK_I bit 0	-	HIO[2]: ! READBACK_I bit 0	-	-	-	-	INT: mux CELL.IMUX_IO_T[1] bit 5	INT: !pass CELL.DOUBLE_IO_S0[0] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_S0[1] ← CELL.DBUF_IO_H[1]	INT: mux CELL.DBUF_IO_H[0] bit 2	INT: mux CELL.DBUF_IO_H[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 7	INT: mux CELL.IMUX_IO_T[0] bit 2	INT: mux CELL.IMUX_IO_T[0] bit 6	INT: mux CELL.IMUX_IO_T[1] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 6	INT: mux CELL.IMUX_IO_T[1] bit 0
B1	INT: !pass CELL.DOUBLE_IO_S2[3] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_S2[2] ← CELL.DBUF_IO_H[0]	INT: mux CELL.DBUF_IO_H[1] bit 0	INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_S0[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S1[3]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S2[2]	INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_S2[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S0[2]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S2[1]	INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S2[1]	INT: !bipass CELL.DOUBLE_IO_S0[1] = CELL.DOUBLE_IO_S2[1]	HIO[1]: PULL bit 1	HIO[1]: OMODE bit 0	HIO[1]: PULL bit 0	INT: mux CELL.IMUX_HIO_T[1] bit 0	INT: mux CELL.OUT_IO_SN_I1[0] bit 0	-	HIO[1]: OSTD bit 0	-	HIO[2]: OSTD bit 0	HIO[2]: ISTD bit 0	HIO[2]: !invert T	HIO[2]: PULL bit 0	HIO[2]: OMODE bit 0	HIO[2]: PULL bit 1	INT: !pass CELL.DOUBLE_IO_S0[3] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_S0[2] ← CELL.DBUF_IO_H[1]	INT: mux CELL.DBUF_IO_H[0] bit 0	INT: mux CELL.DBUF_IO_H[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 4	INT: mux CELL.IMUX_IO_T[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 0	INT: mux CELL.IMUX_IO_T[1] bit 2	INT: mux CELL.IMUX_IO_T[1] bit 4	INT: mux CELL.IMUX_IO_T[1] bit 1	INT: mux CELL.IMUX_IO_T[1] bit 7
B0	-	HIO[0]: OSTD bit 0	HIO[0]: ISTD bit 0	HIO[0]: ! I_INV	INT: mux CELL.OUT_IO_SN_I2[0] bit 0	-	HIO[0]: !invert T	INT: mux CELL.IMUX_HIO_T[0] bit 0	HIO[0]: !invert O	INT: mux CELL.IMUX_HIO_O[0] bit 0	HIO[0]: PULL bit 0	HIO[0]: PULL bit 1	HIO[0]: OMODE bit 0	HIO[1]: !invert O	INT: mux CELL.IMUX_HIO_O[1] bit 0	HIO[1]: !invert T	HIO[1]: ! I_INV	HIO[1]: ISTD bit 0	-	HIO[2]: ! I_INV	INT: mux CELL.OUT_IO_SN_I1[1] bit 0	INT: mux CELL.IMUX_HIO_T[2] bit 0	HIO[2]: !invert O	INT: mux CELL.IMUX_HIO_O[2] bit 0	HIO[3]: OMODE bit 0	HIO[3]: PULL bit 1	HIO[3]: PULL bit 0	INT: mux CELL.IMUX_HIO_O[3] bit 0	HIO[3]: !invert O	INT: mux CELL.IMUX_IO_T[0] bit 5	INT: mux CELL.IMUX_HIO_T[3] bit 0	HIO[3]: !invert T	INT: mux CELL.OUT_IO_SN_I2[1] bit 0	HIO[3]: ! I_INV	HIO[3]: ISTD bit 0	HIO[3]: OSTD bit 0

xc4000h IO_S0_E rect MAIN_E
Bit	Frame
Bit	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile IO_S1

Cells: 4

Switchbox INT

xc4000h IO_S1 switchbox INT programmable buffers
Destination	Source	Bit
CELL.LONG_H[3]	CELL.SINGLE_V[4]	!MAIN[24][5]
CELL.LONG_H[4]	CELL.SINGLE_V[5]	!MAIN[14][8]
CELL.LONG_H[5]	CELL.SINGLE_V[6]	!MAIN[18][12]
CELL.LONG_V[0]	CELL.SINGLE_H_E[1]	!MAIN[13][8]
CELL.LONG_V[1]	CELL.SINGLE_H_E[2]	!MAIN[33][11]
CELL.LONG_V[2]	CELL.SINGLE_H_E[3]	!MAIN[19][12]
CELL.LONG_V[3]	CELL.SINGLE_H[4]	!MAIN[9][8]
CELL.LONG_V[4]	CELL.SINGLE_H[5]	!MAIN[12][8]
CELL.LONG_V[5]	CELL.SINGLE_H[6]	!MAIN[30][11]

xc4000h IO_S1 switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[0]	CELL.TIE_0	!MAIN[7][8]
CELL.SINGLE_H[0]	CELL.OUT_IO_SN_I2[0]	!MAIN[19][9]
CELL.SINGLE_H[1]	CELL.OUT_IO_SN_I2[1]	!MAIN[15][9]
CELL.SINGLE_H[2]	CELL.OUT_CLB_XQ_S	!MAIN[14][10]
CELL.SINGLE_H[3]	CELL.TIE_0	!MAIN[11][10]
CELL.SINGLE_H[3]	CELL.OUT_CLB_X_S	!MAIN[13][12]
CELL.SINGLE_H[4]	CELL.LONG_V[3]	!MAIN[30][7]
CELL.SINGLE_H[4]	CELL.OUT_IO_SN_I2[0]	!MAIN[18][9]
CELL.SINGLE_H[5]	CELL.LONG_V[4]	!MAIN[23][7]
CELL.SINGLE_H[5]	CELL.OUT_IO_SN_I2[1]	!MAIN[17][9]
CELL.SINGLE_H[6]	CELL.TIE_0	!MAIN[13][9]
CELL.SINGLE_H[6]	CELL.LONG_V[5]	!MAIN[29][12]
CELL.SINGLE_H[6]	CELL.OUT_CLB_XQ_S	!MAIN[15][10]
CELL.SINGLE_H[7]	CELL.TIE_0	!MAIN[12][12]
CELL.SINGLE_H[7]	CELL.OUT_CLB_X_S	!MAIN[14][12]
CELL.SINGLE_H_E[1]	CELL.LONG_V[0]	!MAIN[27][8]
CELL.SINGLE_H_E[2]	CELL.LONG_V[1]	!MAIN[35][12]
CELL.SINGLE_H_E[3]	CELL.LONG_V[2]	!MAIN[29][9]
CELL.SINGLE_V[0]	CELL.TIE_0	!MAIN[21][9]
CELL.SINGLE_V[0]	CELL.DEC_H[3]	!MAIN[19][4]
CELL.SINGLE_V[0]	CELL.OUT_IO_SN_I2_E1	!MAIN[22][5]
CELL.SINGLE_V[1]	CELL.LONG_IO_H[0]	!MAIN[15][4]
CELL.SINGLE_V[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[22][6]
CELL.SINGLE_V[2]	CELL.LONG_IO_H[1]	!MAIN[17][4]
CELL.SINGLE_V[2]	CELL.OUT_IO_SN_I1[0]	!MAIN[25][4]
CELL.SINGLE_V[3]	CELL.DEC_H[2]	!MAIN[30][4]
CELL.SINGLE_V[3]	CELL.OUT_IO_SN_I1_E1	!MAIN[29][4]
CELL.SINGLE_V[4]	CELL.LONG_H[3]	!MAIN[21][10]
CELL.SINGLE_V[4]	CELL.DEC_H[1]	!MAIN[35][4]
CELL.SINGLE_V[4]	CELL.OUT_IO_SN_I2_E1	!MAIN[35][6]
CELL.SINGLE_V[5]	CELL.LONG_H[4]	!MAIN[35][8]
CELL.SINGLE_V[5]	CELL.LONG_IO_H[2]	!MAIN[33][4]
CELL.SINGLE_V[5]	CELL.OUT_IO_SN_I2[0]	!MAIN[32][6]
CELL.SINGLE_V[6]	CELL.LONG_H[5]	!MAIN[35][10]
CELL.SINGLE_V[6]	CELL.LONG_IO_H[3]	!MAIN[34][4]
CELL.SINGLE_V[6]	CELL.OUT_IO_SN_I1[0]	!MAIN[25][5]
CELL.SINGLE_V[7]	CELL.TIE_0	!MAIN[21][12]
CELL.SINGLE_V[7]	CELL.DEC_H[0]	!MAIN[31][4]
CELL.SINGLE_V[7]	CELL.OUT_IO_SN_I1_E1	!MAIN[32][4]
CELL.DOUBLE_H0[0]	CELL.OUT_CLB_XQ_S	!MAIN[13][10]
CELL.DOUBLE_H0[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[20][9]
CELL.DOUBLE_H1[0]	CELL.OUT_CLB_X_S	!MAIN[15][12]
CELL.DOUBLE_H1[1]	CELL.OUT_IO_SN_I2[1]	!MAIN[16][9]
CELL.DOUBLE_V0[0]	CELL.OUT_IO_SN_I1_E1	!MAIN[21][3]
CELL.DOUBLE_V0[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[30][6]
CELL.DOUBLE_V1[0]	CELL.OUT_IO_SN_I1[0]	!MAIN[20][3]
CELL.DOUBLE_V1[1]	CELL.OUT_IO_SN_I2_E1	!MAIN[31][6]
CELL.DOUBLE_IO_S0[0]	CELL.DBUF_IO_H[1]	!MAIN[10][2]
CELL.DOUBLE_IO_S0[1]	CELL.DBUF_IO_H[1]	!MAIN[9][2]
CELL.DOUBLE_IO_S0[2]	CELL.DBUF_IO_H[1]	!MAIN[9][1]
CELL.DOUBLE_IO_S0[3]	CELL.DBUF_IO_H[1]	!MAIN[10][1]
CELL.DOUBLE_IO_S2[0]	CELL.DBUF_IO_H[0]	!MAIN[35][2]
CELL.DOUBLE_IO_S2[1]	CELL.DBUF_IO_H[0]	!MAIN[34][2]
CELL.DOUBLE_IO_S2[2]	CELL.DBUF_IO_H[0]	!MAIN[34][1]
CELL.DOUBLE_IO_S2[3]	CELL.DBUF_IO_H[0]	!MAIN[35][1]

xc4000h IO_S1 switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.SINGLE_H_E[0]	!MAIN[23][9]
CELL.SINGLE_H[0]	CELL.SINGLE_V[0]	!MAIN[22][8]
CELL.SINGLE_H[0]	CELL.SINGLE_V_S[0]	!MAIN[25][7]
CELL.SINGLE_H[1]	CELL.SINGLE_H_E[1]	!MAIN[25][8]
CELL.SINGLE_H[1]	CELL.SINGLE_V[1]	!MAIN[24][8]
CELL.SINGLE_H[1]	CELL.SINGLE_V_S[1]	!MAIN[24][7]
CELL.SINGLE_H[2]	CELL.SINGLE_H_E[2]	!MAIN[27][11]
CELL.SINGLE_H[2]	CELL.SINGLE_V[2]	!MAIN[26][11]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[2]	!MAIN[28][11]
CELL.SINGLE_H[3]	CELL.SINGLE_H_E[3]	!MAIN[26][10]
CELL.SINGLE_H[3]	CELL.SINGLE_V[3]	!MAIN[23][10]
CELL.SINGLE_H[3]	CELL.SINGLE_V_S[3]	!MAIN[25][10]
CELL.SINGLE_H[4]	CELL.SINGLE_H_E[4]	!MAIN[31][9]
CELL.SINGLE_H[4]	CELL.SINGLE_V[4]	!MAIN[34][9]
CELL.SINGLE_H[4]	CELL.SINGLE_V_S[4]	!MAIN[30][9]
CELL.SINGLE_H[5]	CELL.SINGLE_H_E[5]	!MAIN[30][8]
CELL.SINGLE_H[5]	CELL.SINGLE_V[5]	!MAIN[31][7]
CELL.SINGLE_H[5]	CELL.SINGLE_V_S[5]	!MAIN[32][8]
CELL.SINGLE_H[6]	CELL.SINGLE_H_E[6]	!MAIN[30][10]
CELL.SINGLE_H[6]	CELL.SINGLE_V[6]	!MAIN[31][11]
CELL.SINGLE_H[6]	CELL.SINGLE_V_S[6]	!MAIN[31][10]
CELL.SINGLE_H[7]	CELL.SINGLE_H_E[7]	!MAIN[33][12]
CELL.SINGLE_H[7]	CELL.SINGLE_V[7]	!MAIN[30][12]
CELL.SINGLE_H[7]	CELL.SINGLE_V_S[7]	!MAIN[32][11]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V[0]	!MAIN[21][8]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V_S[0]	!MAIN[23][8]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V[1]	!MAIN[25][9]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V_S[1]	!MAIN[26][8]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V[2]	!MAIN[26][12]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V_S[2]	!MAIN[27][12]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V[3]	!MAIN[27][10]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V_S[3]	!MAIN[28][10]
CELL.SINGLE_H_E[4]	CELL.SINGLE_V[4]	!MAIN[34][11]
CELL.SINGLE_H_E[4]	CELL.SINGLE_V_S[4]	!MAIN[32][9]
CELL.SINGLE_H_E[5]	CELL.SINGLE_V[5]	!MAIN[31][8]
CELL.SINGLE_H_E[5]	CELL.SINGLE_V_S[5]	!MAIN[33][8]
CELL.SINGLE_H_E[6]	CELL.SINGLE_V[6]	!MAIN[29][10]
CELL.SINGLE_H_E[6]	CELL.SINGLE_V_S[6]	!MAIN[32][10]
CELL.SINGLE_H_E[7]	CELL.SINGLE_V[7]	!MAIN[32][12]
CELL.SINGLE_H_E[7]	CELL.SINGLE_V_S[7]	!MAIN[34][12]
CELL.SINGLE_V[0]	CELL.SINGLE_V_S[0]	!MAIN[24][9]
CELL.SINGLE_V[0]	CELL.DOUBLE_IO_S1[0]	!MAIN[19][2]
CELL.SINGLE_V[1]	CELL.SINGLE_V_S[1]	!MAIN[26][7]
CELL.SINGLE_V[1]	CELL.DOUBLE_IO_S0[0]	!MAIN[22][2]
CELL.SINGLE_V[1]	CELL.DOUBLE_IO_S2[0]	!MAIN[24][2]
CELL.SINGLE_V[2]	CELL.SINGLE_V_S[2]	!MAIN[25][12]
CELL.SINGLE_V[2]	CELL.DOUBLE_IO_S1[1]	!MAIN[25][3]
CELL.SINGLE_V[3]	CELL.SINGLE_V_S[3]	!MAIN[22][10]
CELL.SINGLE_V[3]	CELL.DOUBLE_IO_S0[1]	!MAIN[27][2]
CELL.SINGLE_V[3]	CELL.DOUBLE_IO_S2[1]	!MAIN[26][1]
CELL.SINGLE_V[4]	CELL.SINGLE_V_S[4]	!MAIN[33][9]
CELL.SINGLE_V[4]	CELL.DOUBLE_IO_S1[2]	!MAIN[28][2]
CELL.SINGLE_V[5]	CELL.SINGLE_V_S[5]	!MAIN[34][8]
CELL.SINGLE_V[5]	CELL.DOUBLE_IO_S0[2]	!MAIN[30][2]
CELL.SINGLE_V[5]	CELL.DOUBLE_IO_S2[2]	!MAIN[29][1]
CELL.SINGLE_V[6]	CELL.SINGLE_V_S[6]	!MAIN[33][10]
CELL.SINGLE_V[6]	CELL.DOUBLE_IO_S1[3]	!MAIN[31][3]
CELL.SINGLE_V[7]	CELL.SINGLE_V_S[7]	!MAIN[31][12]
CELL.SINGLE_V[7]	CELL.DOUBLE_IO_S0[3]	!MAIN[32][1]
CELL.SINGLE_V[7]	CELL.DOUBLE_IO_S2[3]	!MAIN[32][2]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_H2[0]	!MAIN[24][12]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_V0[0]	!MAIN[22][12]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_V2[0]	!MAIN[23][12]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_H2[1]	!MAIN[28][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_V0[1]	!MAIN[27][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_V2[1]	!MAIN[28][7]
CELL.DOUBLE_H2[0]	CELL.DOUBLE_V0[0]	!MAIN[24][10]
CELL.DOUBLE_H2[0]	CELL.DOUBLE_V2[0]	!MAIN[24][11]
CELL.DOUBLE_H2[1]	CELL.DOUBLE_V0[1]	!MAIN[28][8]
CELL.DOUBLE_H2[1]	CELL.DOUBLE_V2[1]	!MAIN[29][8]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_V2[0]	!MAIN[22][11]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_S0[1]	!MAIN[26][2]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_S1[1]	!MAIN[24][3]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_S2[1]	!MAIN[27][1]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_V2[1]	!MAIN[29][7]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_S0[2]	!MAIN[28][1]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_S1[2]	!MAIN[29][2]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_S2[2]	!MAIN[30][1]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_S0[0]	!MAIN[21][2]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_S1[0]	!MAIN[20][2]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_S2[0]	!MAIN[25][2]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_S0[3]	!MAIN[31][2]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_S1[3]	!MAIN[31][1]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_S2[3]	!MAIN[33][2]
CELL.DOUBLE_IO_S0[0]	CELL.DOUBLE_IO_S2[0]	!MAIN[23][2]
CELL.DOUBLE_IO_S0[1]	CELL.DOUBLE_IO_S2[1]	!MAIN[25][1]
CELL.DOUBLE_IO_S0[2]	CELL.DOUBLE_IO_S2[2]	!MAIN[30][3]
CELL.DOUBLE_IO_S0[3]	CELL.DOUBLE_IO_S2[3]	!MAIN[32][3]

xc4000h IO_S1 switchbox INT muxes DBUF_IO_H[0]
Bits				Destination
MAIN[7][2]	MAIN[8][2]	MAIN[7][1]	MAIN[8][1]	CELL.DBUF_IO_H[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_S0[0]
0	1	0	1	CELL.DOUBLE_IO_S0[2]
0	1	1	0	CELL.DOUBLE_IO_S0[3]
1	1	1	1	CELL.DOUBLE_IO_S0[1]

xc4000h IO_S1 switchbox INT muxes DBUF_IO_H[1]
Bits				Destination
MAIN[33][3]	MAIN[34][3]	MAIN[35][3]	MAIN[33][1]	CELL.DBUF_IO_H[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_S2[1]
0	1	0	1	CELL.DOUBLE_IO_S2[2]
0	1	1	0	CELL.DOUBLE_IO_S2[3]
1	1	1	1	CELL.DOUBLE_IO_S2[0]

xc4000h IO_S1 switchbox INT muxes LONG_V[0]
Bits				Destination
MAIN[26][5]	MAIN[27][5]	MAIN[29][5]	MAIN[28][5]	CELL.LONG_V[0]
				Source
0	0	0	1	CELL.LONG_IO_H[0]
0	0	1	0	CELL.DEC_H[0]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_S1 switchbox INT muxes LONG_V[1]
Bits				Destination
MAIN[35][5]	MAIN[33][5]	MAIN[34][6]	MAIN[34][5]	CELL.LONG_V[1]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_S1 switchbox INT muxes LONG_V[2]
Bits				Destination
MAIN[31][5]	MAIN[30][5]	MAIN[32][5]	MAIN[33][6]	CELL.LONG_V[2]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_S1 switchbox INT muxes LONG_V[3]
Bits				Destination
MAIN[6][5]	MAIN[6][6]	MAIN[7][6]	MAIN[7][5]	CELL.LONG_V[3]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_S1 switchbox INT muxes LONG_V[4]
Bits				Destination
MAIN[5][5]	MAIN[1][6]	MAIN[2][6]	MAIN[2][5]	CELL.LONG_V[4]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_S1 switchbox INT muxes LONG_V[5]
Bits				Destination
MAIN[8][5]	MAIN[8][6]	MAIN[9][5]	MAIN[9][6]	CELL.LONG_V[5]
				Source
0	0	0	1	CELL.LONG_IO_H[3]
0	0	1	0	CELL.DEC_H[3]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_S1 switchbox INT muxes LONG_IO_H[0]
Bits		Destination
MAIN[4][6]	MAIN[16][4]	CELL.LONG_IO_H[0]
		Source
0	0	CELL.LONG_V[0]
0	1	CELL.SINGLE_V[1]
1	1	off

xc4000h IO_S1 switchbox INT muxes LONG_IO_H[1]
Bits				Destination
MAIN[23][3]	MAIN[15][3]	MAIN[18][4]	MAIN[16][3]	CELL.LONG_IO_H[1]
				Source
0	0	0	1	CELL.LONG_V[1]
0	0	1	0	CELL.LONG_V[3]
0	1	1	1	CELL.SINGLE_V[2]
1	1	1	1	off

xc4000h IO_S1 switchbox INT muxes LONG_IO_H[2]
Bits				Destination
MAIN[22][3]	MAIN[20][4]	MAIN[21][4]	MAIN[22][4]	CELL.LONG_IO_H[2]
				Source
0	0	0	1	CELL.LONG_V[2]
0	0	1	0	CELL.LONG_V[4]
0	1	1	1	CELL.SINGLE_V[5]
1	1	1	1	off

xc4000h IO_S1 switchbox INT muxes LONG_IO_H[3]
Bits		Destination
MAIN[4][5]	MAIN[23][4]	CELL.LONG_IO_H[3]
		Source
0	0	CELL.LONG_V[5]
0	1	CELL.SINGLE_V[6]
1	1	off

xc4000h IO_S1 switchbox INT muxes IMUX_CLB_F2
Bits								Destination
MAIN[10][12]	MAIN[10][10]	MAIN[11][9]	MAIN[11][11]	MAIN[11][12]	MAIN[12][11]	MAIN[12][10]	MAIN[12][9]	CELL.IMUX_CLB_F2
								Source
0	0	1	1	0	0	1	1	CELL.SINGLE_H[5]
0	0	1	1	0	1	0	1	CELL.LONG_H[5]
0	0	1	1	0	1	1	0	CELL.DOUBLE_H1[1]
0	0	1	1	1	1	1	1	CELL.SINGLE_H[0]
0	1	0	1	0	0	1	1	CELL.SINGLE_H[4]
0	1	0	1	0	1	0	1	CELL.DOUBLE_H0[1]
0	1	0	1	0	1	1	0	CELL.LONG_H[4]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[1]
0	1	1	0	0	0	1	1	CELL.SINGLE_H[6]
0	1	1	0	0	1	0	1	CELL_N.LONG_H[2]
0	1	1	0	0	1	1	0	CELL_N.LONG_H[0]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[3]
1	1	1	1	0	0	1	1	CELL.DOUBLE_H0[0]
1	1	1	1	0	1	0	1	CELL.SINGLE_H[7]
1	1	1	1	0	1	1	0	CELL.DOUBLE_H1[0]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[2]

xc4000h IO_S1 switchbox INT muxes IMUX_CLB_F4
Bits								Destination
MAIN[9][10]	MAIN[9][11]	MAIN[8][9]	MAIN[8][10]	MAIN[10][9]	MAIN[8][12]	MAIN[9][12]	MAIN[10][11]	CELL.IMUX_CLB_F4
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_H[0]
0	0	0	1	1	0	1	1	CELL.DOUBLE_H1[0]
0	0	0	1	1	1	0	1	CELL_N.LONG_H[0]
0	0	1	1	1	1	1	1	CELL.SINGLE_H[1]
0	1	0	0	0	1	1	1	CELL.LONG_H[5]
0	1	0	0	1	1	1	0	CELL.LONG_H[3]
0	1	0	1	0	0	1	1	CELL.SINGLE_H[2]
0	1	0	1	0	1	0	1	CELL.SINGLE_H[3]
0	1	0	1	1	0	1	0	CELL.SINGLE_H[7]
0	1	0	1	1	1	0	0	CELL_N.LONG_H[1]
0	1	1	1	0	1	1	1	CELL.DOUBLE_H1[1]
0	1	1	1	1	1	1	0	CELL.DOUBLE_H0[1]
1	1	0	0	1	1	1	1	CELL.SINGLE_H[5]
1	1	0	1	1	0	1	1	CELL.DOUBLE_H0[0]
1	1	0	1	1	1	0	1	CELL.SINGLE_H[6]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[4]

xc4000h IO_S1 switchbox INT muxes IMUX_CLB_G2
Bits									Destination
MAIN[2][10]	MAIN[3][10]	MAIN[3][12]	MAIN[2][9]	MAIN[3][11]	MAIN[2][11]	MAIN[2][12]	MAIN[3][9]	MAIN[4][11]	CELL.IMUX_CLB_G2
									Source
0	0	0	1	1	1	1	1	1	CELL.SPECIAL_CLB_COUT0
0	0	1	0	0	1	1	1	1	CELL.LONG_H[4]
0	0	1	0	1	1	1	0	1	CELL.SINGLE_H[4]
0	0	1	0	1	1	1	1	0	CELL.LONG_H[5]
0	0	1	1	0	0	1	1	1	CELL.SINGLE_H[2]
0	0	1	1	0	1	0	1	1	CELL.SINGLE_H[3]
0	0	1	1	1	0	1	0	1	CELL.SINGLE_H[7]
0	0	1	1	1	0	1	1	0	CELL.DOUBLE_H0[0]
0	0	1	1	1	1	0	0	1	CELL_N.LONG_H[2]
0	0	1	1	1	1	0	1	0	CELL.SINGLE_H[6]
0	1	1	0	1	1	1	1	1	CELL.SINGLE_H[1]
0	1	1	1	1	0	1	1	1	CELL_N.LONG_H[0]
0	1	1	1	1	1	0	1	1	CELL.DOUBLE_H1[0]
1	0	1	1	0	1	1	1	1	CELL.DOUBLE_H1[1]
1	0	1	1	1	1	1	0	1	CELL.SINGLE_H[5]
1	0	1	1	1	1	1	1	0	CELL.DOUBLE_H0[1]
1	1	1	1	1	1	1	1	1	CELL.SINGLE_H[0]

xc4000h IO_S1 switchbox INT muxes IMUX_CLB_G4
Bits								Destination
MAIN[5][12]	MAIN[4][12]	MAIN[6][11]	MAIN[4][9]	MAIN[4][10]	MAIN[5][10]	MAIN[5][11]	MAIN[5][9]	CELL.IMUX_CLB_G4
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_H[0]
0	0	0	1	0	1	1	1	CELL.SINGLE_H[1]
0	0	0	1	1	1	0	1	CELL_N.LONG_H[0]
0	0	1	0	1	0	1	1	CELL.DOUBLE_H1[1]
0	0	1	0	1	1	1	0	CELL.LONG_H[3]
0	0	1	1	0	0	1	1	CELL.LONG_H[5]
0	0	1	1	0	1	1	0	CELL.DOUBLE_H0[1]
0	0	1	1	1	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	1	1	0	0	CELL.SINGLE_H[6]
0	1	0	1	1	1	1	1	CELL.DOUBLE_H1[0]
0	1	1	1	1	0	1	1	CELL.SINGLE_H[2]
0	1	1	1	1	1	1	0	CELL.DOUBLE_H0[0]
1	0	1	0	1	1	1	1	CELL.SINGLE_H[5]
1	0	1	1	0	1	1	1	CELL.SINGLE_H[4]
1	0	1	1	1	1	0	1	CELL_N.LONG_H[1]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[7]

xc4000h IO_S1 switchbox INT muxes IMUX_CLB_C2
Bits								Destination
MAIN[0][10]	MAIN[0][9]	MAIN[1][10]	MAIN[1][12]	MAIN[0][11]	MAIN[0][12]	MAIN[1][9]	MAIN[1][11]	CELL.IMUX_CLB_C2
								Source
0	0	0	0	1	1	1	1	CELL.LONG_H[4]
0	0	0	1	1	1	0	1	CELL.SINGLE_H[5]
0	0	0	1	1	1	1	0	CELL.LONG_H[3]
0	0	1	1	1	1	1	1	CELL.SINGLE_H[0]
0	1	0	0	0	1	1	1	CELL.SINGLE_H[2]
0	1	0	0	1	0	1	1	CELL.SINGLE_H[3]
0	1	0	1	0	1	0	1	CELL.SINGLE_H[7]
0	1	0	1	0	1	1	0	CELL.DOUBLE_H0[0]
0	1	0	1	1	0	0	1	CELL_N.LONG_H[1]
0	1	0	1	1	0	1	0	CELL.SINGLE_H[6]
0	1	1	1	0	1	1	1	CELL.DOUBLE_H1[0]
0	1	1	1	1	0	1	1	CELL_N.LONG_H[2]
1	1	0	0	1	1	1	1	CELL.DOUBLE_H1[1]
1	1	0	1	1	1	0	1	CELL.SINGLE_H[4]
1	1	0	1	1	1	1	0	CELL.DOUBLE_H0[1]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[1]

xc4000h IO_S1 switchbox INT muxes IMUX_CLB_C4
Bits								Destination
MAIN[7][10]	MAIN[8][11]	MAIN[6][10]	MAIN[6][9]	MAIN[7][12]	MAIN[7][11]	MAIN[6][12]	MAIN[7][9]	CELL.IMUX_CLB_C4
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_H[1]
0	0	0	1	1	0	1	1	CELL.DOUBLE_H0[0]
0	0	0	1	1	1	0	1	CELL.SINGLE_H[6]
0	0	1	1	1	1	1	1	CELL.SINGLE_H[0]
0	1	0	0	0	1	1	1	CELL.LONG_H[4]
0	1	0	0	1	1	1	0	CELL.LONG_H[3]
0	1	0	1	0	0	1	1	CELL.SINGLE_H[2]
0	1	0	1	0	1	0	1	CELL.SINGLE_H[3]
0	1	0	1	1	0	1	0	CELL.DOUBLE_H1[0]
0	1	0	1	1	1	0	0	CELL_N.LONG_H[1]
0	1	1	1	0	1	1	1	CELL.DOUBLE_H1[1]
0	1	1	1	1	1	1	0	CELL.DOUBLE_H0[1]
1	1	0	0	1	1	1	1	CELL.SINGLE_H[4]
1	1	0	1	1	0	1	1	CELL.SINGLE_H[7]
1	1	0	1	1	1	0	1	CELL_N.LONG_H[2]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[5]

xc4000h IO_S1 switchbox INT muxes IMUX_IO_O1[0]
Bits						Destination
MAIN[26][4]	MAIN[26][3]	MAIN[28][4]	MAIN[27][3]	MAIN[28][3]	MAIN[27][4]	CELL.IMUX_IO_O1[0]
						Source
0	0	0	1	1	1	CELL.DEC_H[2]
0	0	1	1	1	1	CELL.DOUBLE_V0[0]
0	1	0	0	1	1	CELL.DEC_H[0]
0	1	0	1	0	1	CELL.DEC_H[3]
0	1	0	1	1	0	CELL.LONG_V[5]
0	1	1	0	1	1	CELL.LONG_V[3]
0	1	1	1	0	1	CELL.LONG_V[4]
0	1	1	1	1	0	CELL.DEC_H[1]
1	1	0	1	1	1	CELL.DOUBLE_V1[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_S1 switchbox INT muxes IMUX_IO_O1[1]
Bits						Destination
MAIN[0][4]	MAIN[2][4]	MAIN[2][3]	MAIN[1][4]	MAIN[1][3]	MAIN[0][3]	CELL.IMUX_IO_O1[1]
						Source
0	0	0	1	1	1	CELL.DEC_H[0]
0	0	1	0	1	1	CELL.DEC_H[2]
0	0	1	1	0	1	CELL.DEC_H[3]
0	0	1	1	1	0	CELL_E.LONG_V[2]
0	1	0	1	1	1	CELL_E.LONG_V[1]
0	1	1	0	1	1	CELL.DEC_H[1]
0	1	1	1	0	1	CELL_E.LONG_V[0]
0	1	1	1	1	0	CELL_E.DOUBLE_V1[0]
1	0	1	1	1	1	CELL_E.DOUBLE_V0[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_S1 switchbox INT muxes IMUX_IO_OK[0]
Bits								Destination
MAIN[23][5]	MAIN[29][6]	MAIN[28][6]	MAIN[27][6]	MAIN[24][6]	MAIN[23][6]	MAIN[25][6]	MAIN[26][6]	CELL.IMUX_IO_OK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_V[3]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[2]

xc4000h IO_S1 switchbox INT muxes IMUX_IO_OK[1]
Bits								Destination
MAIN[10][5]	MAIN[12][6]	MAIN[13][6]	MAIN[11][6]	MAIN[10][6]	MAIN[13][5]	MAIN[12][5]	MAIN[11][5]	CELL.IMUX_IO_OK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_E.SINGLE_V[2]
0	1	1	1	1	1	0	1	CELL_E.SINGLE_V[3]
0	1	1	1	1	1	1	0	CELL_E.SINGLE_V[5]
1	1	1	1	1	1	1	1	CELL_E.SINGLE_V[4]

xc4000h IO_S1 switchbox INT muxes IMUX_IO_IK[0]
Bits								Destination
MAIN[18][5]	MAIN[19][5]	MAIN[20][5]	MAIN[21][5]	MAIN[19][6]	MAIN[18][6]	MAIN[20][6]	MAIN[21][6]	CELL.IMUX_IO_IK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_V[2]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[3]

xc4000h IO_S1 switchbox INT muxes IMUX_IO_IK[1]
Bits								Destination
MAIN[14][5]	MAIN[16][6]	MAIN[17][6]	MAIN[15][6]	MAIN[14][6]	MAIN[17][5]	MAIN[16][5]	MAIN[15][5]	CELL.IMUX_IO_IK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_E.SINGLE_V[2]
0	1	1	1	1	1	0	1	CELL_E.SINGLE_V[3]
0	1	1	1	1	1	1	0	CELL_E.SINGLE_V[4]
1	1	1	1	1	1	1	1	CELL_E.SINGLE_V[5]

xc4000h IO_S1 switchbox INT muxes IMUX_IO_T[0]
Bits								Destination
MAIN[5][2]	MAIN[3][2]	MAIN[6][0]	MAIN[6][1]	MAIN[6][2]	MAIN[4][2]	MAIN[5][1]	MAIN[4][1]	CELL.IMUX_IO_T[0]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	1	1	0	1	CELL.DEC_H[1]
0	0	1	0	1	1	1	0	CELL.GCLK[0]
0	0	1	1	0	0	1	1	CELL.LONG_IO_H[3]
0	0	1	1	0	1	0	1	CELL.LONG_IO_H[0]
0	0	1	1	0	1	1	0	CELL.LONG_IO_H[2]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_S0[1]
0	1	1	1	0	1	1	1	CELL.DOUBLE_IO_S1[0]
1	0	1	1	1	0	1	1	CELL.DOUBLE_IO_S1[1]
1	0	1	1	1	1	0	1	CELL.LONG_IO_H[1]
1	0	1	1	1	1	1	0	CELL.DEC_H[0]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_S0[0]

xc4000h IO_S1 switchbox INT muxes IMUX_IO_T[1]
Bits								Destination
MAIN[0][1]	MAIN[1][2]	MAIN[11][2]	MAIN[2][1]	MAIN[2][2]	MAIN[3][1]	MAIN[1][1]	MAIN[0][2]	CELL.IMUX_IO_T[1]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	0	1	1	1	CELL.LONG_IO_H[0]
0	0	1	0	1	0	1	1	CELL.GCLK[0]
0	0	1	1	0	1	0	1	CELL.LONG_IO_H[3]
0	0	1	1	0	1	1	0	CELL.LONG_IO_H[2]
0	0	1	1	1	0	0	1	CELL.DEC_H[0]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_S0[0]
0	1	1	1	1	1	0	1	CELL.LONG_IO_H[1]
0	1	1	1	1	1	1	0	CELL.DEC_H[1]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_S0[1]
1	0	1	1	1	0	1	1	CELL.DOUBLE_IO_S1[1]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_S1[0]

xc4000h IO_S1 switchbox INT muxes IMUX_HIO_O[0]
Bits	Destination
MAIN[26][0]	CELL.IMUX_HIO_O[0]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_F4

xc4000h IO_S1 switchbox INT muxes IMUX_HIO_O[1]
Bits	Destination
MAIN[21][0]	CELL.IMUX_HIO_O[1]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_F4

xc4000h IO_S1 switchbox INT muxes IMUX_HIO_O[2]
Bits	Destination
MAIN[12][0]	CELL.IMUX_HIO_O[2]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_G4

xc4000h IO_S1 switchbox INT muxes IMUX_HIO_O[3]
Bits	Destination
MAIN[8][0]	CELL.IMUX_HIO_O[3]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_G4

xc4000h IO_S1 switchbox INT muxes IMUX_HIO_T[0]
Bits	Destination
MAIN[28][0]	CELL.IMUX_HIO_T[0]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_OK[0]

xc4000h IO_S1 switchbox INT muxes IMUX_HIO_T[1]
Bits	Destination
MAIN[21][1]	CELL.IMUX_HIO_T[1]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_IK[0]

xc4000h IO_S1 switchbox INT muxes IMUX_HIO_T[2]
Bits	Destination
MAIN[14][0]	CELL.IMUX_HIO_T[2]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_IK[1]

xc4000h IO_S1 switchbox INT muxes IMUX_HIO_T[3]
Bits	Destination
MAIN[5][0]	CELL.IMUX_HIO_T[3]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_OK[1]

xc4000h IO_S1 switchbox INT muxes OUT_IO_SN_I1[0]
Bits	Destination
MAIN[20][1]	CELL.OUT_IO_SN_I1[0]
	Source
0	CELL.OUT_HIO_I[1]
1	CELL.OUT_HIO_I[0]

xc4000h IO_S1 switchbox INT muxes OUT_IO_SN_I1[1]
Bits	Destination
MAIN[15][0]	CELL.OUT_IO_SN_I1[1]
	Source
0	CELL.OUT_HIO_I[2]
1	CELL.OUT_HIO_I[3]

xc4000h IO_S1 switchbox INT muxes OUT_IO_SN_I2[0]
Bits	Destination
MAIN[31][0]	CELL.OUT_IO_SN_I2[0]
	Source
0	CELL.OUT_HIO_I[0]
1	CELL.OUT_HIO_I[1]

xc4000h IO_S1 switchbox INT muxes OUT_IO_SN_I2[1]
Bits	Destination
MAIN[3][0]	CELL.OUT_IO_SN_I2[1]
	Source
0	CELL.OUT_HIO_I[3]
1	CELL.OUT_HIO_I[2]

Bels HIO

xc4000h IO_S1 bel HIO pins
Pin	Direction	HIO[0]	HIO[1]	HIO[2]	HIO[3]
O	in	CELL.IMUX_HIO_O[0] invert by !MAIN[27][0]	CELL.IMUX_HIO_O[1] invert by !MAIN[22][0]	CELL.IMUX_HIO_O[2] invert by !MAIN[13][0]	CELL.IMUX_HIO_O[3] invert by !MAIN[7][0]
T	in	CELL.IMUX_HIO_T[0] invert by !MAIN[29][0]	CELL.IMUX_HIO_T[1] invert by !MAIN[20][0]	CELL.IMUX_HIO_T[2] invert by !MAIN[14][1]	CELL.IMUX_HIO_T[3] invert by !MAIN[4][0]
I	out	CELL.OUT_HIO_I[0]	CELL.OUT_HIO_I[1]	CELL.OUT_HIO_I[2]	CELL.OUT_HIO_I[3]

xc4000h IO_S1 bel HIO attribute bits
Attribute	HIO[0]	HIO[1]	HIO[2]	HIO[3]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
ISTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OSTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OMODE	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]
I_INV	!MAIN[32][0]	!MAIN[19][0]	!MAIN[16][0]	!MAIN[2][0]
READBACK_I bit 0	!MAIN[18][2]	!MAIN[18][3]	!MAIN[16][2]	!MAIN[17][3]

xc4000h IO_S1 enum IO_PULL
HIO[0].PULL	MAIN[24][0]	MAIN[25][0]
HIO[1].PULL	MAIN[24][1]	MAIN[22][1]
HIO[2].PULL	MAIN[11][1]	MAIN[13][1]
HIO[3].PULL	MAIN[10][0]	MAIN[9][0]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

xc4000h IO_S1 enum IO_STD
HIO[0].ISTD	MAIN[33][0]
HIO[1].ISTD	MAIN[18][0]
HIO[2].ISTD	MAIN[15][1]
HIO[3].ISTD	MAIN[1][0]
CMOS	0
TTL	1

xc4000h IO_S1 enum IO_STD
HIO[0].OSTD	MAIN[34][0]
HIO[1].OSTD	MAIN[18][1]
HIO[2].OSTD	MAIN[16][1]
HIO[3].OSTD	MAIN[0][0]
CMOS	1
TTL	0

xc4000h IO_S1 enum HIO_OMODE
HIO[0].OMODE	MAIN[23][0]
HIO[1].OMODE	MAIN[23][1]
HIO[2].OMODE	MAIN[12][1]
HIO[3].OMODE	MAIN[11][0]
CAP	1
RES	0

Bels DEC

xc4000h IO_S1 bel DEC pins
Pin	Direction	DEC[0]	DEC[1]	DEC[2]
I	in	CELL.OUT_IO_SN_I1[0]	CELL.IMUX_CLB_C4	CELL.OUT_IO_SN_I1[1]
O1	bidir	CELL.DEC_H[0]	CELL.DEC_H[0]	CELL.DEC_H[0]
O2	bidir	CELL.DEC_H[1]	CELL.DEC_H[1]	CELL.DEC_H[1]
O3	bidir	CELL.DEC_H[2]	CELL.DEC_H[2]	CELL.DEC_H[2]
O4	bidir	CELL.DEC_H[3]	CELL.DEC_H[3]	CELL.DEC_H[3]

xc4000h IO_S1 bel DEC attribute bits
Attribute	DEC[0]	DEC[1]	DEC[2]
O1_P	!MAIN[14][3]	!MAIN[12][4]	MAIN[13][3]
O1_N	MAIN[14][4]	MAIN[12][3]	!MAIN[13][4]
O2_P	!MAIN[9][3]	!MAIN[11][4]	MAIN[10][3]
O2_N	MAIN[9][4]	MAIN[11][3]	!MAIN[10][4]
O3_P	!MAIN[3][3]	!MAIN[5][4]	MAIN[4][3]
O3_N	MAIN[3][4]	MAIN[5][3]	!MAIN[4][4]
O4_P	!MAIN[8][3]	!MAIN[6][4]	MAIN[7][3]
O4_N	MAIN[8][4]	MAIN[6][3]	!MAIN[7][4]

Bel wires

xc4000h IO_S1 bel wires
Wire	Pins
CELL.DEC_H[0]	DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_H[1]	DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.DEC_H[2]	DEC[0].O3, DEC[1].O3, DEC[2].O3
CELL.DEC_H[3]	DEC[0].O4, DEC[1].O4, DEC[2].O4
CELL.IMUX_CLB_C4	DEC[1].I
CELL.IMUX_HIO_O[0]	HIO[0].O
CELL.IMUX_HIO_O[1]	HIO[1].O
CELL.IMUX_HIO_O[2]	HIO[2].O
CELL.IMUX_HIO_O[3]	HIO[3].O
CELL.IMUX_HIO_T[0]	HIO[0].T
CELL.IMUX_HIO_T[1]	HIO[1].T
CELL.IMUX_HIO_T[2]	HIO[2].T
CELL.IMUX_HIO_T[3]	HIO[3].T
CELL.OUT_IO_SN_I1[0]	DEC[0].I
CELL.OUT_IO_SN_I1[1]	DEC[2].I
CELL.OUT_HIO_I[0]	HIO[0].I
CELL.OUT_HIO_I[1]	HIO[1].I
CELL.OUT_HIO_I[2]	HIO[2].I
CELL.OUT_HIO_I[3]	HIO[3].I

Bitstream

xc4000h IO_S1 rect MAIN
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B12	INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7]	INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7]	INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7]	INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5]	-	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0]	INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0	-	INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3]	INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6]	-	-	INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S	INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S	INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0	INT: mux CELL.IMUX_CLB_F2 bit 3	INT: mux CELL.IMUX_CLB_F2 bit 7	INT: mux CELL.IMUX_CLB_F4 bit 1	INT: mux CELL.IMUX_CLB_F4 bit 2	INT: mux CELL.IMUX_CLB_C4 bit 3	INT: mux CELL.IMUX_CLB_C4 bit 1	INT: mux CELL.IMUX_CLB_G4 bit 7	INT: mux CELL.IMUX_CLB_G4 bit 6	INT: mux CELL.IMUX_CLB_G2 bit 6	INT: mux CELL.IMUX_CLB_G2 bit 2	INT: mux CELL.IMUX_CLB_C2 bit 4	INT: mux CELL.IMUX_CLB_C2 bit 2
B11	-	INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4]	INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6]	INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6]	-	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2]	-	INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0]	-	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0]	-	-	-	-	-	-	-	-	-	INT: mux CELL.IMUX_CLB_F2 bit 2	INT: mux CELL.IMUX_CLB_F2 bit 4	INT: mux CELL.IMUX_CLB_F4 bit 0	INT: mux CELL.IMUX_CLB_F4 bit 6	INT: mux CELL.IMUX_CLB_C4 bit 6	INT: mux CELL.IMUX_CLB_C4 bit 2	INT: mux CELL.IMUX_CLB_G4 bit 5	INT: mux CELL.IMUX_CLB_G4 bit 1	INT: mux CELL.IMUX_CLB_G2 bit 0	INT: mux CELL.IMUX_CLB_G2 bit 4	INT: mux CELL.IMUX_CLB_G2 bit 3	INT: mux CELL.IMUX_CLB_C2 bit 0	INT: mux CELL.IMUX_CLB_C2 bit 3
B10	INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5]	-	INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6]	INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3]	INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3]	-	-	-	-	-	INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S	INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S	INT: mux CELL.IMUX_CLB_F2 bit 1	INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0	INT: mux CELL.IMUX_CLB_F2 bit 6	INT: mux CELL.IMUX_CLB_F4 bit 7	INT: mux CELL.IMUX_CLB_F4 bit 4	INT: mux CELL.IMUX_CLB_C4 bit 7	INT: mux CELL.IMUX_CLB_C4 bit 5	INT: mux CELL.IMUX_CLB_G4 bit 2	INT: mux CELL.IMUX_CLB_G4 bit 3	INT: mux CELL.IMUX_CLB_G2 bit 7	INT: mux CELL.IMUX_CLB_G2 bit 8	INT: mux CELL.IMUX_CLB_C2 bit 5	INT: mux CELL.IMUX_CLB_C2 bit 7
B9	-	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4]	INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4]	INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1]	-	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0]	-	INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0	INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_SN_I2[1]	INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_SN_I2[1]	INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_SN_I2[1]	-	INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0	INT: mux CELL.IMUX_CLB_F2 bit 0	INT: mux CELL.IMUX_CLB_F2 bit 5	INT: mux CELL.IMUX_CLB_F4 bit 3	-	INT: mux CELL.IMUX_CLB_F4 bit 5	INT: mux CELL.IMUX_CLB_C4 bit 0	INT: mux CELL.IMUX_CLB_C4 bit 4	INT: mux CELL.IMUX_CLB_G4 bit 0	INT: mux CELL.IMUX_CLB_G4 bit 4	INT: mux CELL.IMUX_CLB_G2 bit 1	INT: mux CELL.IMUX_CLB_G2 bit 5	INT: mux CELL.IMUX_CLB_C2 bit 1	INT: mux CELL.IMUX_CLB_C2 bit 6
B8	INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4]	INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5]	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5]	INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1]	INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1]	INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0]	-	-	-	-	-	-	INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5]	INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1]	INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5]	-	-	INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4]	-	INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0	-	-	-	-	-	-	-
B7	-	-	-	-	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5]	INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1]	-	INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1]	INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.LONG_V[1] bit 1	INT: mux CELL.LONG_V[2] bit 0	INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1	INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0]	INT: mux CELL.IMUX_IO_OK[0] bit 6	INT: mux CELL.IMUX_IO_OK[0] bit 5	INT: mux CELL.IMUX_IO_OK[0] bit 4	INT: mux CELL.IMUX_IO_OK[0] bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 1	INT: mux CELL.IMUX_IO_OK[0] bit 3	INT: mux CELL.IMUX_IO_OK[0] bit 2	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0]	INT: mux CELL.IMUX_IO_IK[0] bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 1	INT: mux CELL.IMUX_IO_IK[0] bit 3	INT: mux CELL.IMUX_IO_IK[0] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 5	INT: mux CELL.IMUX_IO_IK[1] bit 6	INT: mux CELL.IMUX_IO_IK[1] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 3	INT: mux CELL.IMUX_IO_OK[1] bit 5	INT: mux CELL.IMUX_IO_OK[1] bit 6	INT: mux CELL.IMUX_IO_OK[1] bit 4	INT: mux CELL.IMUX_IO_OK[1] bit 3	INT: mux CELL.LONG_V[5] bit 0	INT: mux CELL.LONG_V[5] bit 2	INT: mux CELL.LONG_V[3] bit 1	INT: mux CELL.LONG_V[3] bit 2	-	INT: mux CELL.LONG_IO_H[0] bit 1	-	INT: mux CELL.LONG_V[4] bit 1	INT: mux CELL.LONG_V[4] bit 2	-
B5	INT: mux CELL.LONG_V[1] bit 3	INT: mux CELL.LONG_V[1] bit 0	INT: mux CELL.LONG_V[1] bit 2	INT: mux CELL.LONG_V[2] bit 1	INT: mux CELL.LONG_V[2] bit 3	INT: mux CELL.LONG_V[2] bit 2	INT: mux CELL.LONG_V[0] bit 1	INT: mux CELL.LONG_V[0] bit 0	INT: mux CELL.LONG_V[0] bit 2	INT: mux CELL.LONG_V[0] bit 3	INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_IO_SN_I1[0]	INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[4]	INT: mux CELL.IMUX_IO_OK[0] bit 7	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.IMUX_IO_IK[0] bit 4	INT: mux CELL.IMUX_IO_IK[0] bit 5	INT: mux CELL.IMUX_IO_IK[0] bit 6	INT: mux CELL.IMUX_IO_IK[0] bit 7	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 0	INT: mux CELL.IMUX_IO_IK[1] bit 7	INT: mux CELL.IMUX_IO_OK[1] bit 2	INT: mux CELL.IMUX_IO_OK[1] bit 1	INT: mux CELL.IMUX_IO_OK[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 7	INT: mux CELL.LONG_V[5] bit 1	INT: mux CELL.LONG_V[5] bit 3	INT: mux CELL.LONG_V[3] bit 0	INT: mux CELL.LONG_V[3] bit 3	INT: mux CELL.LONG_V[4] bit 3	INT: mux CELL.LONG_IO_H[3] bit 1	-	INT: mux CELL.LONG_V[4] bit 0	-	-
B4	INT: !pass CELL.SINGLE_V[4] ← CELL.DEC_H[1]	INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_IO_H[3]	INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_IO_H[2]	INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.SINGLE_V[7] ← CELL.DEC_H[0]	INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[2]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1	INT: mux CELL.IMUX_IO_O1[0] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 5	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0]	-	INT: mux CELL.LONG_IO_H[3] bit 0	INT: mux CELL.LONG_IO_H[2] bit 0	INT: mux CELL.LONG_IO_H[2] bit 1	INT: mux CELL.LONG_IO_H[2] bit 2	INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[3]	INT: mux CELL.LONG_IO_H[1] bit 1	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[1]	INT: mux CELL.LONG_IO_H[0] bit 0	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[0]	DEC[0]: O1_N	DEC[2]: ! O1_N	DEC[1]: ! O1_P	DEC[1]: ! O2_P	DEC[2]: ! O2_N	DEC[0]: O2_N	DEC[0]: O4_N	DEC[2]: ! O4_N	DEC[1]: ! O4_P	DEC[1]: ! O3_P	DEC[2]: ! O3_N	DEC[0]: O3_N	INT: mux CELL.IMUX_IO_O1[1] bit 4	INT: mux CELL.IMUX_IO_O1[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 5
B3	INT: mux CELL.DBUF_IO_H[1] bit 1	INT: mux CELL.DBUF_IO_H[1] bit 2	INT: mux CELL.DBUF_IO_H[1] bit 3	INT: !bipass CELL.DOUBLE_IO_S0[3] = CELL.DOUBLE_IO_S2[3]	INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_S1[3]	INT: !bipass CELL.DOUBLE_IO_S0[2] = CELL.DOUBLE_IO_S2[2]	-	INT: mux CELL.IMUX_IO_O1[0] bit 1	INT: mux CELL.IMUX_IO_O1[0] bit 2	INT: mux CELL.IMUX_IO_O1[0] bit 4	INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S1[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S1[1]	INT: mux CELL.LONG_IO_H[1] bit 3	INT: mux CELL.LONG_IO_H[2] bit 3	INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0]	-	HIO[1]: ! READBACK_I bit 0	HIO[3]: ! READBACK_I bit 0	INT: mux CELL.LONG_IO_H[1] bit 0	INT: mux CELL.LONG_IO_H[1] bit 2	DEC[0]: ! O1_P	DEC[2]: O1_P	DEC[1]: O1_N	DEC[1]: O2_N	DEC[2]: O2_P	DEC[0]: ! O2_P	DEC[0]: ! O4_P	DEC[2]: O4_P	DEC[1]: O4_N	DEC[1]: O3_N	DEC[2]: O3_P	DEC[0]: ! O3_P	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.IMUX_IO_O1[1] bit 0
B2	INT: !pass CELL.DOUBLE_IO_S2[0] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_S2[1] ← CELL.DBUF_IO_H[0]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S2[3]	INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_S2[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S0[3]	INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_S0[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S1[2]	INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_S1[2]	INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S0[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S0[1]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S2[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S2[0]	INT: !bipass CELL.DOUBLE_IO_S0[0] = CELL.DOUBLE_IO_S2[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S0[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S0[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S1[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S1[0]	HIO[0]: ! READBACK_I bit 0	-	HIO[2]: ! READBACK_I bit 0	-	-	-	-	INT: mux CELL.IMUX_IO_T[1] bit 5	INT: !pass CELL.DOUBLE_IO_S0[0] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_S0[1] ← CELL.DBUF_IO_H[1]	INT: mux CELL.DBUF_IO_H[0] bit 2	INT: mux CELL.DBUF_IO_H[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 7	INT: mux CELL.IMUX_IO_T[0] bit 2	INT: mux CELL.IMUX_IO_T[0] bit 6	INT: mux CELL.IMUX_IO_T[1] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 6	INT: mux CELL.IMUX_IO_T[1] bit 0
B1	INT: !pass CELL.DOUBLE_IO_S2[3] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_S2[2] ← CELL.DBUF_IO_H[0]	INT: mux CELL.DBUF_IO_H[1] bit 0	INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_S0[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S1[3]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S2[2]	INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_S2[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S0[2]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S2[1]	INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S2[1]	INT: !bipass CELL.DOUBLE_IO_S0[1] = CELL.DOUBLE_IO_S2[1]	HIO[1]: PULL bit 1	HIO[1]: OMODE bit 0	HIO[1]: PULL bit 0	INT: mux CELL.IMUX_HIO_T[1] bit 0	INT: mux CELL.OUT_IO_SN_I1[0] bit 0	-	HIO[1]: OSTD bit 0	-	HIO[2]: OSTD bit 0	HIO[2]: ISTD bit 0	HIO[2]: !invert T	HIO[2]: PULL bit 0	HIO[2]: OMODE bit 0	HIO[2]: PULL bit 1	INT: !pass CELL.DOUBLE_IO_S0[3] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_S0[2] ← CELL.DBUF_IO_H[1]	INT: mux CELL.DBUF_IO_H[0] bit 0	INT: mux CELL.DBUF_IO_H[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 4	INT: mux CELL.IMUX_IO_T[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 0	INT: mux CELL.IMUX_IO_T[1] bit 2	INT: mux CELL.IMUX_IO_T[1] bit 4	INT: mux CELL.IMUX_IO_T[1] bit 1	INT: mux CELL.IMUX_IO_T[1] bit 7
B0	-	HIO[0]: OSTD bit 0	HIO[0]: ISTD bit 0	HIO[0]: ! I_INV	INT: mux CELL.OUT_IO_SN_I2[0] bit 0	-	HIO[0]: !invert T	INT: mux CELL.IMUX_HIO_T[0] bit 0	HIO[0]: !invert O	INT: mux CELL.IMUX_HIO_O[0] bit 0	HIO[0]: PULL bit 0	HIO[0]: PULL bit 1	HIO[0]: OMODE bit 0	HIO[1]: !invert O	INT: mux CELL.IMUX_HIO_O[1] bit 0	HIO[1]: !invert T	HIO[1]: ! I_INV	HIO[1]: ISTD bit 0	-	HIO[2]: ! I_INV	INT: mux CELL.OUT_IO_SN_I1[1] bit 0	INT: mux CELL.IMUX_HIO_T[2] bit 0	HIO[2]: !invert O	INT: mux CELL.IMUX_HIO_O[2] bit 0	HIO[3]: OMODE bit 0	HIO[3]: PULL bit 1	HIO[3]: PULL bit 0	INT: mux CELL.IMUX_HIO_O[3] bit 0	HIO[3]: !invert O	INT: mux CELL.IMUX_IO_T[0] bit 5	INT: mux CELL.IMUX_HIO_T[3] bit 0	HIO[3]: !invert T	INT: mux CELL.OUT_IO_SN_I2[1] bit 0	HIO[3]: ! I_INV	HIO[3]: ISTD bit 0	HIO[3]: OSTD bit 0

xc4000h IO_S1 rect MAIN_E
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile IO_S1_W

Cells: 4

Switchbox INT

xc4000h IO_S1_W switchbox INT programmable buffers
Destination	Source	Bit
CELL.LONG_H[3]	CELL.SINGLE_V[4]	!MAIN[24][5]
CELL.LONG_H[4]	CELL.SINGLE_V[5]	!MAIN[14][8]
CELL.LONG_H[5]	CELL.SINGLE_V[6]	!MAIN[18][12]
CELL.LONG_V[0]	CELL.SINGLE_H_E[1]	!MAIN[13][8]
CELL.LONG_V[1]	CELL.SINGLE_H_E[2]	!MAIN[33][11]
CELL.LONG_V[2]	CELL.SINGLE_H_E[3]	!MAIN[19][12]
CELL.LONG_V[3]	CELL.SINGLE_H[4]	!MAIN[9][8]
CELL.LONG_V[4]	CELL.SINGLE_H[5]	!MAIN[12][8]
CELL.LONG_V[5]	CELL.SINGLE_H[6]	!MAIN[30][11]

xc4000h IO_S1_W switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[0]	CELL.TIE_0	!MAIN[7][8]
CELL.SINGLE_H[0]	CELL.OUT_IO_SN_I2[0]	!MAIN[19][9]
CELL.SINGLE_H[1]	CELL.OUT_IO_SN_I2[1]	!MAIN[15][9]
CELL.SINGLE_H[2]	CELL.OUT_CLB_XQ_S	!MAIN[14][10]
CELL.SINGLE_H[3]	CELL.TIE_0	!MAIN[11][10]
CELL.SINGLE_H[3]	CELL.OUT_CLB_X_S	!MAIN[13][12]
CELL.SINGLE_H[4]	CELL.LONG_V[3]	!MAIN[30][7]
CELL.SINGLE_H[4]	CELL.OUT_IO_SN_I2[0]	!MAIN[18][9]
CELL.SINGLE_H[5]	CELL.LONG_V[4]	!MAIN[23][7]
CELL.SINGLE_H[5]	CELL.OUT_IO_SN_I2[1]	!MAIN[17][9]
CELL.SINGLE_H[6]	CELL.TIE_0	!MAIN[13][9]
CELL.SINGLE_H[6]	CELL.LONG_V[5]	!MAIN[29][12]
CELL.SINGLE_H[6]	CELL.OUT_CLB_XQ_S	!MAIN[15][10]
CELL.SINGLE_H[7]	CELL.TIE_0	!MAIN[12][12]
CELL.SINGLE_H[7]	CELL.OUT_CLB_X_S	!MAIN[14][12]
CELL.SINGLE_H_E[1]	CELL.LONG_V[0]	!MAIN[27][8]
CELL.SINGLE_H_E[2]	CELL.LONG_V[1]	!MAIN[35][12]
CELL.SINGLE_H_E[3]	CELL.LONG_V[2]	!MAIN[29][9]
CELL.SINGLE_V[0]	CELL.TIE_0	!MAIN[21][9]
CELL.SINGLE_V[0]	CELL.DEC_H[3]	!MAIN[19][4]
CELL.SINGLE_V[0]	CELL.OUT_IO_SN_I2_E1	!MAIN[22][5]
CELL.SINGLE_V[1]	CELL.LONG_IO_H[0]	!MAIN[15][4]
CELL.SINGLE_V[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[22][6]
CELL.SINGLE_V[2]	CELL.LONG_IO_H[1]	!MAIN[17][4]
CELL.SINGLE_V[2]	CELL.OUT_IO_SN_I1[0]	!MAIN[25][4]
CELL.SINGLE_V[3]	CELL.DEC_H[2]	!MAIN[30][4]
CELL.SINGLE_V[3]	CELL.OUT_IO_SN_I1_E1	!MAIN[29][4]
CELL.SINGLE_V[4]	CELL.LONG_H[3]	!MAIN[21][10]
CELL.SINGLE_V[4]	CELL.DEC_H[1]	!MAIN[35][4]
CELL.SINGLE_V[4]	CELL.OUT_IO_SN_I2_E1	!MAIN[35][6]
CELL.SINGLE_V[5]	CELL.LONG_H[4]	!MAIN[35][8]
CELL.SINGLE_V[5]	CELL.LONG_IO_H[2]	!MAIN[33][4]
CELL.SINGLE_V[5]	CELL.OUT_IO_SN_I2[0]	!MAIN[32][6]
CELL.SINGLE_V[6]	CELL.LONG_H[5]	!MAIN[35][10]
CELL.SINGLE_V[6]	CELL.LONG_IO_H[3]	!MAIN[34][4]
CELL.SINGLE_V[6]	CELL.OUT_IO_SN_I1[0]	!MAIN[25][5]
CELL.SINGLE_V[7]	CELL.TIE_0	!MAIN[21][12]
CELL.SINGLE_V[7]	CELL.DEC_H[0]	!MAIN[31][4]
CELL.SINGLE_V[7]	CELL.OUT_IO_SN_I1_E1	!MAIN[32][4]
CELL.DOUBLE_H0[0]	CELL.OUT_CLB_XQ_S	!MAIN[13][10]
CELL.DOUBLE_H0[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[20][9]
CELL.DOUBLE_H1[0]	CELL.OUT_CLB_X_S	!MAIN[15][12]
CELL.DOUBLE_H1[1]	CELL.OUT_IO_SN_I2[1]	!MAIN[16][9]
CELL.DOUBLE_V0[0]	CELL.OUT_IO_SN_I1_E1	!MAIN[21][3]
CELL.DOUBLE_V0[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[30][6]
CELL.DOUBLE_V1[0]	CELL.OUT_IO_SN_I1[0]	!MAIN[20][3]
CELL.DOUBLE_V1[1]	CELL.OUT_IO_SN_I2_E1	!MAIN[31][6]
CELL.DOUBLE_IO_S0[0]	CELL.DBUF_IO_H[1]	!MAIN[10][2]
CELL.DOUBLE_IO_S0[1]	CELL.DBUF_IO_H[1]	!MAIN[9][2]
CELL.DOUBLE_IO_S0[2]	CELL.DBUF_IO_H[1]	!MAIN[9][1]
CELL.DOUBLE_IO_S0[3]	CELL.DBUF_IO_H[1]	!MAIN[10][1]
CELL.DOUBLE_IO_S2[0]	CELL.DBUF_IO_H[0]	!MAIN[35][2]
CELL.DOUBLE_IO_S2[1]	CELL.DBUF_IO_H[0]	!MAIN[34][2]
CELL.DOUBLE_IO_S2[2]	CELL.DBUF_IO_H[0]	!MAIN[34][1]
CELL.DOUBLE_IO_S2[3]	CELL.DBUF_IO_H[0]	!MAIN[35][1]

xc4000h IO_S1_W switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.SINGLE_H_E[0]	!MAIN[23][9]
CELL.SINGLE_H[0]	CELL.SINGLE_V[0]	!MAIN[22][8]
CELL.SINGLE_H[0]	CELL.SINGLE_V_S[0]	!MAIN[25][7]
CELL.SINGLE_H[1]	CELL.SINGLE_H_E[1]	!MAIN[25][8]
CELL.SINGLE_H[1]	CELL.SINGLE_V[1]	!MAIN[24][8]
CELL.SINGLE_H[1]	CELL.SINGLE_V_S[1]	!MAIN[24][7]
CELL.SINGLE_H[2]	CELL.SINGLE_H_E[2]	!MAIN[27][11]
CELL.SINGLE_H[2]	CELL.SINGLE_V[2]	!MAIN[26][11]
CELL.SINGLE_H[2]	CELL.SINGLE_V_S[2]	!MAIN[28][11]
CELL.SINGLE_H[3]	CELL.SINGLE_H_E[3]	!MAIN[26][10]
CELL.SINGLE_H[3]	CELL.SINGLE_V[3]	!MAIN[23][10]
CELL.SINGLE_H[3]	CELL.SINGLE_V_S[3]	!MAIN[25][10]
CELL.SINGLE_H[4]	CELL.SINGLE_H_E[4]	!MAIN[31][9]
CELL.SINGLE_H[4]	CELL.SINGLE_V[4]	!MAIN[34][9]
CELL.SINGLE_H[4]	CELL.SINGLE_V_S[4]	!MAIN[30][9]
CELL.SINGLE_H[5]	CELL.SINGLE_H_E[5]	!MAIN[30][8]
CELL.SINGLE_H[5]	CELL.SINGLE_V[5]	!MAIN[31][7]
CELL.SINGLE_H[5]	CELL.SINGLE_V_S[5]	!MAIN[32][8]
CELL.SINGLE_H[6]	CELL.SINGLE_H_E[6]	!MAIN[30][10]
CELL.SINGLE_H[6]	CELL.SINGLE_V[6]	!MAIN[31][11]
CELL.SINGLE_H[6]	CELL.SINGLE_V_S[6]	!MAIN[31][10]
CELL.SINGLE_H[7]	CELL.SINGLE_H_E[7]	!MAIN[33][12]
CELL.SINGLE_H[7]	CELL.SINGLE_V[7]	!MAIN[30][12]
CELL.SINGLE_H[7]	CELL.SINGLE_V_S[7]	!MAIN[32][11]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V[0]	!MAIN[21][8]
CELL.SINGLE_H_E[0]	CELL.SINGLE_V_S[0]	!MAIN[23][8]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V[1]	!MAIN[25][9]
CELL.SINGLE_H_E[1]	CELL.SINGLE_V_S[1]	!MAIN[26][8]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V[2]	!MAIN[26][12]
CELL.SINGLE_H_E[2]	CELL.SINGLE_V_S[2]	!MAIN[27][12]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V[3]	!MAIN[27][10]
CELL.SINGLE_H_E[3]	CELL.SINGLE_V_S[3]	!MAIN[28][10]
CELL.SINGLE_H_E[4]	CELL.SINGLE_V[4]	!MAIN[34][11]
CELL.SINGLE_H_E[4]	CELL.SINGLE_V_S[4]	!MAIN[32][9]
CELL.SINGLE_H_E[5]	CELL.SINGLE_V[5]	!MAIN[31][8]
CELL.SINGLE_H_E[5]	CELL.SINGLE_V_S[5]	!MAIN[33][8]
CELL.SINGLE_H_E[6]	CELL.SINGLE_V[6]	!MAIN[29][10]
CELL.SINGLE_H_E[6]	CELL.SINGLE_V_S[6]	!MAIN[32][10]
CELL.SINGLE_H_E[7]	CELL.SINGLE_V[7]	!MAIN[32][12]
CELL.SINGLE_H_E[7]	CELL.SINGLE_V_S[7]	!MAIN[34][12]
CELL.SINGLE_V[0]	CELL.SINGLE_V_S[0]	!MAIN[24][9]
CELL.SINGLE_V[0]	CELL.DOUBLE_IO_S1[0]	!MAIN[19][2]
CELL.SINGLE_V[1]	CELL.SINGLE_V_S[1]	!MAIN[26][7]
CELL.SINGLE_V[1]	CELL.DOUBLE_IO_S0[0]	!MAIN[22][2]
CELL.SINGLE_V[1]	CELL.DOUBLE_IO_S2[0]	!MAIN[24][2]
CELL.SINGLE_V[2]	CELL.SINGLE_V_S[2]	!MAIN[25][12]
CELL.SINGLE_V[2]	CELL.DOUBLE_IO_S1[1]	!MAIN[25][3]
CELL.SINGLE_V[3]	CELL.SINGLE_V_S[3]	!MAIN[22][10]
CELL.SINGLE_V[3]	CELL.DOUBLE_IO_S0[1]	!MAIN[27][2]
CELL.SINGLE_V[3]	CELL.DOUBLE_IO_S2[1]	!MAIN[26][1]
CELL.SINGLE_V[4]	CELL.SINGLE_V_S[4]	!MAIN[33][9]
CELL.SINGLE_V[4]	CELL.DOUBLE_IO_S1[2]	!MAIN[28][2]
CELL.SINGLE_V[5]	CELL.SINGLE_V_S[5]	!MAIN[34][8]
CELL.SINGLE_V[5]	CELL.DOUBLE_IO_S0[2]	!MAIN[30][2]
CELL.SINGLE_V[5]	CELL.DOUBLE_IO_S2[2]	!MAIN[29][1]
CELL.SINGLE_V[6]	CELL.SINGLE_V_S[6]	!MAIN[33][10]
CELL.SINGLE_V[6]	CELL.DOUBLE_IO_S1[3]	!MAIN[31][3]
CELL.SINGLE_V[7]	CELL.SINGLE_V_S[7]	!MAIN[31][12]
CELL.SINGLE_V[7]	CELL.DOUBLE_IO_S0[3]	!MAIN[32][1]
CELL.SINGLE_V[7]	CELL.DOUBLE_IO_S2[3]	!MAIN[32][2]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_H2[0]	!MAIN[24][12]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_V0[0]	!MAIN[22][12]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_V2[0]	!MAIN[23][12]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_H2[1]	!MAIN[28][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_V0[1]	!MAIN[27][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_V2[1]	!MAIN[28][7]
CELL.DOUBLE_H2[0]	CELL.DOUBLE_V0[0]	!MAIN[24][10]
CELL.DOUBLE_H2[0]	CELL.DOUBLE_V2[0]	!MAIN[24][11]
CELL.DOUBLE_H2[1]	CELL.DOUBLE_V0[1]	!MAIN[28][8]
CELL.DOUBLE_H2[1]	CELL.DOUBLE_V2[1]	!MAIN[29][8]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_V2[0]	!MAIN[22][11]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_S0[1]	!MAIN[26][2]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_S1[1]	!MAIN[24][3]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_S2[1]	!MAIN[27][1]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_V2[1]	!MAIN[29][7]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_S0[2]	!MAIN[28][1]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_S1[2]	!MAIN[29][2]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_S2[2]	!MAIN[30][1]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_S0[0]	!MAIN[21][2]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_S1[0]	!MAIN[20][2]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_S2[0]	!MAIN[25][2]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_S0[3]	!MAIN[31][2]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_S1[3]	!MAIN[31][1]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_S2[3]	!MAIN[33][2]
CELL.DOUBLE_IO_S0[0]	CELL.DOUBLE_IO_S2[0]	!MAIN[23][2]
CELL.DOUBLE_IO_S0[1]	CELL.DOUBLE_IO_S2[1]	!MAIN[25][1]
CELL.DOUBLE_IO_S0[2]	CELL.DOUBLE_IO_S2[2]	!MAIN[30][3]
CELL.DOUBLE_IO_S0[3]	CELL.DOUBLE_IO_S2[3]	!MAIN[32][3]

xc4000h IO_S1_W switchbox INT muxes DBUF_IO_H[0]
Bits				Destination
MAIN[7][2]	MAIN[8][2]	MAIN[7][1]	MAIN[8][1]	CELL.DBUF_IO_H[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_S0[0]
0	1	0	1	CELL.DOUBLE_IO_S0[2]
0	1	1	0	CELL.DOUBLE_IO_S0[3]
1	1	1	1	CELL.DOUBLE_IO_S0[1]

xc4000h IO_S1_W switchbox INT muxes DBUF_IO_H[1]
Bits				Destination
MAIN[33][3]	MAIN[34][3]	MAIN[35][3]	MAIN[33][1]	CELL.DBUF_IO_H[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_S2[1]
0	1	0	1	CELL.DOUBLE_IO_S2[2]
0	1	1	0	CELL.DOUBLE_IO_S2[3]
1	1	1	1	CELL.DOUBLE_IO_S2[0]

xc4000h IO_S1_W switchbox INT muxes LONG_V[0]
Bits				Destination
MAIN[26][5]	MAIN[27][5]	MAIN[29][5]	MAIN[28][5]	CELL.LONG_V[0]
				Source
0	0	0	1	CELL.LONG_IO_H[0]
0	0	1	0	CELL.DEC_H[0]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_S1_W switchbox INT muxes LONG_V[1]
Bits				Destination
MAIN[35][5]	MAIN[33][5]	MAIN[34][6]	MAIN[34][5]	CELL.LONG_V[1]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_S1_W switchbox INT muxes LONG_V[2]
Bits				Destination
MAIN[31][5]	MAIN[30][5]	MAIN[32][5]	MAIN[33][6]	CELL.LONG_V[2]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_S1_W switchbox INT muxes LONG_V[3]
Bits				Destination
MAIN[6][5]	MAIN[6][6]	MAIN[7][6]	MAIN[7][5]	CELL.LONG_V[3]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_S1_W switchbox INT muxes LONG_V[4]
Bits				Destination
MAIN[5][5]	MAIN[1][6]	MAIN[2][6]	MAIN[2][5]	CELL.LONG_V[4]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_S1_W switchbox INT muxes LONG_V[5]
Bits				Destination
MAIN[8][5]	MAIN[8][6]	MAIN[9][5]	MAIN[9][6]	CELL.LONG_V[5]
				Source
0	0	0	1	CELL.LONG_IO_H[3]
0	0	1	0	CELL.DEC_H[3]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_S1_W switchbox INT muxes LONG_IO_H[0]
Bits		Destination
MAIN[4][6]	MAIN[16][4]	CELL.LONG_IO_H[0]
		Source
0	0	CELL.LONG_V[0]
0	1	CELL.SINGLE_V[1]
1	1	off

xc4000h IO_S1_W switchbox INT muxes LONG_IO_H[1]
Bits				Destination
MAIN[23][3]	MAIN[15][3]	MAIN[18][4]	MAIN[16][3]	CELL.LONG_IO_H[1]
				Source
0	0	0	1	CELL.LONG_V[1]
0	0	1	0	CELL.LONG_V[3]
0	1	1	1	CELL.SINGLE_V[2]
1	1	1	1	off

xc4000h IO_S1_W switchbox INT muxes LONG_IO_H[2]
Bits				Destination
MAIN[22][3]	MAIN[20][4]	MAIN[21][4]	MAIN[22][4]	CELL.LONG_IO_H[2]
				Source
0	0	0	1	CELL.LONG_V[2]
0	0	1	0	CELL.LONG_V[4]
0	1	1	1	CELL.SINGLE_V[5]
1	1	1	1	off

xc4000h IO_S1_W switchbox INT muxes LONG_IO_H[3]
Bits		Destination
MAIN[4][5]	MAIN[23][4]	CELL.LONG_IO_H[3]
		Source
0	0	CELL.LONG_V[5]
0	1	CELL.SINGLE_V[6]
1	1	off

xc4000h IO_S1_W switchbox INT muxes IMUX_CLB_F2
Bits								Destination
MAIN[10][12]	MAIN[10][10]	MAIN[11][9]	MAIN[11][11]	MAIN[11][12]	MAIN[12][11]	MAIN[12][10]	MAIN[12][9]	CELL.IMUX_CLB_F2
								Source
0	0	1	1	0	0	1	1	CELL.SINGLE_H[5]
0	0	1	1	0	1	0	1	CELL.LONG_H[5]
0	0	1	1	0	1	1	0	CELL.DOUBLE_H1[1]
0	0	1	1	1	1	1	1	CELL.SINGLE_H[0]
0	1	0	1	0	0	1	1	CELL.SINGLE_H[4]
0	1	0	1	0	1	0	1	CELL.DOUBLE_H0[1]
0	1	0	1	0	1	1	0	CELL.LONG_H[4]
0	1	0	1	1	1	1	1	CELL.SINGLE_H[1]
0	1	1	0	0	0	1	1	CELL.SINGLE_H[6]
0	1	1	0	0	1	0	1	CELL_N.LONG_H[2]
0	1	1	0	0	1	1	0	CELL_N.LONG_H[0]
0	1	1	0	1	1	1	1	CELL.SINGLE_H[3]
1	1	1	1	0	0	1	1	CELL.DOUBLE_H0[0]
1	1	1	1	0	1	0	1	CELL.SINGLE_H[7]
1	1	1	1	0	1	1	0	CELL.DOUBLE_H1[0]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[2]

xc4000h IO_S1_W switchbox INT muxes IMUX_CLB_F4
Bits								Destination
MAIN[9][10]	MAIN[9][11]	MAIN[8][9]	MAIN[8][10]	MAIN[10][9]	MAIN[8][12]	MAIN[9][12]	MAIN[10][11]	CELL.IMUX_CLB_F4
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_H[0]
0	0	0	1	1	0	1	1	CELL.DOUBLE_H1[0]
0	0	0	1	1	1	0	1	CELL_N.LONG_H[0]
0	0	1	1	1	1	1	1	CELL.SINGLE_H[1]
0	1	0	0	0	1	1	1	CELL.LONG_H[5]
0	1	0	0	1	1	1	0	CELL.LONG_H[3]
0	1	0	1	0	0	1	1	CELL.SINGLE_H[2]
0	1	0	1	0	1	0	1	CELL.SINGLE_H[3]
0	1	0	1	1	0	1	0	CELL.SINGLE_H[7]
0	1	0	1	1	1	0	0	CELL_N.LONG_H[1]
0	1	1	1	0	1	1	1	CELL.DOUBLE_H1[1]
0	1	1	1	1	1	1	0	CELL.DOUBLE_H0[1]
1	1	0	0	1	1	1	1	CELL.SINGLE_H[5]
1	1	0	1	1	0	1	1	CELL.DOUBLE_H0[0]
1	1	0	1	1	1	0	1	CELL.SINGLE_H[6]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[4]

xc4000h IO_S1_W switchbox INT muxes IMUX_CLB_G2
Bits									Destination
MAIN[2][10]	MAIN[3][10]	MAIN[3][12]	MAIN[2][9]	MAIN[3][11]	MAIN[2][11]	MAIN[2][12]	MAIN[3][9]	MAIN[4][11]	CELL.IMUX_CLB_G2
									Source
0	0	0	1	1	1	1	1	1	CELL.SPECIAL_CLB_COUT0
0	0	1	0	0	1	1	1	1	CELL.LONG_H[4]
0	0	1	0	1	1	1	0	1	CELL.SINGLE_H[4]
0	0	1	0	1	1	1	1	0	CELL.LONG_H[5]
0	0	1	1	0	0	1	1	1	CELL.SINGLE_H[2]
0	0	1	1	0	1	0	1	1	CELL.SINGLE_H[3]
0	0	1	1	1	0	1	0	1	CELL.SINGLE_H[7]
0	0	1	1	1	0	1	1	0	CELL.DOUBLE_H0[0]
0	0	1	1	1	1	0	0	1	CELL_N.LONG_H[2]
0	0	1	1	1	1	0	1	0	CELL.SINGLE_H[6]
0	1	1	0	1	1	1	1	1	CELL.SINGLE_H[1]
0	1	1	1	1	0	1	1	1	CELL_N.LONG_H[0]
0	1	1	1	1	1	0	1	1	CELL.DOUBLE_H1[0]
1	0	1	1	0	1	1	1	1	CELL.DOUBLE_H1[1]
1	0	1	1	1	1	1	0	1	CELL.SINGLE_H[5]
1	0	1	1	1	1	1	1	0	CELL.DOUBLE_H0[1]
1	1	1	1	1	1	1	1	1	CELL.SINGLE_H[0]

xc4000h IO_S1_W switchbox INT muxes IMUX_CLB_G4
Bits								Destination
MAIN[5][12]	MAIN[4][12]	MAIN[6][11]	MAIN[4][9]	MAIN[4][10]	MAIN[5][10]	MAIN[5][11]	MAIN[5][9]	CELL.IMUX_CLB_G4
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_H[0]
0	0	0	1	0	1	1	1	CELL.SINGLE_H[1]
0	0	0	1	1	1	0	1	CELL_N.LONG_H[0]
0	0	1	0	1	0	1	1	CELL.DOUBLE_H1[1]
0	0	1	0	1	1	1	0	CELL.LONG_H[3]
0	0	1	1	0	0	1	1	CELL.LONG_H[5]
0	0	1	1	0	1	1	0	CELL.DOUBLE_H0[1]
0	0	1	1	1	0	0	1	CELL.SINGLE_H[3]
0	0	1	1	1	1	0	0	CELL.SINGLE_H[6]
0	1	0	1	1	1	1	1	CELL.DOUBLE_H1[0]
0	1	1	1	1	0	1	1	CELL.SINGLE_H[2]
0	1	1	1	1	1	1	0	CELL.DOUBLE_H0[0]
1	0	1	0	1	1	1	1	CELL.SINGLE_H[5]
1	0	1	1	0	1	1	1	CELL.SINGLE_H[4]
1	0	1	1	1	1	0	1	CELL_N.LONG_H[1]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[7]

xc4000h IO_S1_W switchbox INT muxes IMUX_CLB_C2
Bits								Destination
MAIN[0][10]	MAIN[0][9]	MAIN[1][10]	MAIN[1][12]	MAIN[0][11]	MAIN[0][12]	MAIN[1][9]	MAIN[1][11]	CELL.IMUX_CLB_C2
								Source
0	0	0	0	1	1	1	1	CELL.LONG_H[4]
0	0	0	1	1	1	0	1	CELL.SINGLE_H[5]
0	0	0	1	1	1	1	0	CELL.LONG_H[3]
0	0	1	1	1	1	1	1	CELL.SINGLE_H[0]
0	1	0	0	0	1	1	1	CELL.SINGLE_H[2]
0	1	0	0	1	0	1	1	CELL.SINGLE_H[3]
0	1	0	1	0	1	0	1	CELL.SINGLE_H[7]
0	1	0	1	0	1	1	0	CELL.DOUBLE_H0[0]
0	1	0	1	1	0	0	1	CELL_N.LONG_H[1]
0	1	0	1	1	0	1	0	CELL.SINGLE_H[6]
0	1	1	1	0	1	1	1	CELL.DOUBLE_H1[0]
0	1	1	1	1	0	1	1	CELL_N.LONG_H[2]
1	1	0	0	1	1	1	1	CELL.DOUBLE_H1[1]
1	1	0	1	1	1	0	1	CELL.SINGLE_H[4]
1	1	0	1	1	1	1	0	CELL.DOUBLE_H0[1]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[1]

xc4000h IO_S1_W switchbox INT muxes IMUX_CLB_C4
Bits								Destination
MAIN[7][10]	MAIN[8][11]	MAIN[6][10]	MAIN[6][9]	MAIN[7][12]	MAIN[7][11]	MAIN[6][12]	MAIN[7][9]	CELL.IMUX_CLB_C4
								Source
0	0	0	0	1	1	1	1	CELL.SINGLE_H[1]
0	0	0	1	1	0	1	1	CELL.DOUBLE_H0[0]
0	0	0	1	1	1	0	1	CELL.SINGLE_H[6]
0	0	1	1	1	1	1	1	CELL.SINGLE_H[0]
0	1	0	0	0	1	1	1	CELL.LONG_H[4]
0	1	0	0	1	1	1	0	CELL.LONG_H[3]
0	1	0	1	0	0	1	1	CELL.SINGLE_H[2]
0	1	0	1	0	1	0	1	CELL.SINGLE_H[3]
0	1	0	1	1	0	1	0	CELL.DOUBLE_H1[0]
0	1	0	1	1	1	0	0	CELL_N.LONG_H[1]
0	1	1	1	0	1	1	1	CELL.DOUBLE_H1[1]
0	1	1	1	1	1	1	0	CELL.DOUBLE_H0[1]
1	1	0	0	1	1	1	1	CELL.SINGLE_H[4]
1	1	0	1	1	0	1	1	CELL.SINGLE_H[7]
1	1	0	1	1	1	0	1	CELL_N.LONG_H[2]
1	1	1	1	1	1	1	1	CELL.SINGLE_H[5]

xc4000h IO_S1_W switchbox INT muxes IMUX_IO_O1[0]
Bits						Destination
MAIN[26][4]	MAIN[26][3]	MAIN[28][4]	MAIN[27][3]	MAIN[28][3]	MAIN[27][4]	CELL.IMUX_IO_O1[0]
						Source
0	0	0	1	1	1	CELL.DEC_H[2]
0	0	1	1	1	1	CELL.DOUBLE_V0[0]
0	1	0	0	1	1	CELL.DEC_H[0]
0	1	0	1	0	1	CELL.DEC_H[3]
0	1	0	1	1	0	CELL.LONG_V[5]
0	1	1	0	1	1	CELL.LONG_V[3]
0	1	1	1	0	1	CELL.LONG_V[4]
0	1	1	1	1	0	CELL.DEC_H[1]
1	1	0	1	1	1	CELL.DOUBLE_V1[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_S1_W switchbox INT muxes IMUX_IO_O1[1]
Bits						Destination
MAIN[0][4]	MAIN[2][4]	MAIN[2][3]	MAIN[1][4]	MAIN[1][3]	MAIN[0][3]	CELL.IMUX_IO_O1[1]
						Source
0	0	0	1	1	1	CELL.DEC_H[0]
0	0	1	0	1	1	CELL.DEC_H[2]
0	0	1	1	0	1	CELL.DEC_H[3]
0	0	1	1	1	0	CELL_E.LONG_V[2]
0	1	0	1	1	1	CELL_E.LONG_V[1]
0	1	1	0	1	1	CELL.DEC_H[1]
0	1	1	1	0	1	CELL_E.LONG_V[0]
0	1	1	1	1	0	CELL_E.DOUBLE_V1[0]
1	0	1	1	1	1	CELL_E.DOUBLE_V0[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_S1_W switchbox INT muxes IMUX_IO_OK[0]
Bits								Destination
MAIN[23][5]	MAIN[29][6]	MAIN[28][6]	MAIN[27][6]	MAIN[24][6]	MAIN[23][6]	MAIN[25][6]	MAIN[26][6]	CELL.IMUX_IO_OK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_V[3]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[2]

xc4000h IO_S1_W switchbox INT muxes IMUX_IO_OK[1]
Bits								Destination
MAIN[10][5]	MAIN[12][6]	MAIN[13][6]	MAIN[11][6]	MAIN[10][6]	MAIN[13][5]	MAIN[12][5]	MAIN[11][5]	CELL.IMUX_IO_OK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_E.SINGLE_V[2]
0	1	1	1	1	1	0	1	CELL_E.SINGLE_V[3]
0	1	1	1	1	1	1	0	CELL_E.SINGLE_V[5]
1	1	1	1	1	1	1	1	CELL_E.SINGLE_V[4]

xc4000h IO_S1_W switchbox INT muxes IMUX_IO_IK[0]
Bits								Destination
MAIN[18][5]	MAIN[19][5]	MAIN[20][5]	MAIN[21][5]	MAIN[19][6]	MAIN[18][6]	MAIN[20][6]	MAIN[21][6]	CELL.IMUX_IO_IK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_V[2]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[3]

xc4000h IO_S1_W switchbox INT muxes IMUX_IO_IK[1]
Bits								Destination
MAIN[14][5]	MAIN[16][6]	MAIN[17][6]	MAIN[15][6]	MAIN[14][6]	MAIN[17][5]	MAIN[16][5]	MAIN[15][5]	CELL.IMUX_IO_IK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_E.SINGLE_V[2]
0	1	1	1	1	1	0	1	CELL_E.SINGLE_V[3]
0	1	1	1	1	1	1	0	CELL_E.SINGLE_V[4]
1	1	1	1	1	1	1	1	CELL_E.SINGLE_V[5]

xc4000h IO_S1_W switchbox INT muxes IMUX_IO_T[0]
Bits								Destination
MAIN[5][2]	MAIN[3][2]	MAIN[6][0]	MAIN[6][1]	MAIN[6][2]	MAIN[4][2]	MAIN[5][1]	MAIN[4][1]	CELL.IMUX_IO_T[0]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	1	1	0	1	CELL.DEC_H[1]
0	0	1	0	1	1	1	0	CELL.GCLK[0]
0	0	1	1	0	0	1	1	CELL.LONG_IO_H[3]
0	0	1	1	0	1	0	1	CELL.LONG_IO_H[0]
0	0	1	1	0	1	1	0	CELL.LONG_IO_H[2]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_S0[1]
0	1	1	1	0	1	1	1	CELL.DOUBLE_IO_S1[0]
1	0	1	1	1	0	1	1	CELL.DOUBLE_IO_S1[1]
1	0	1	1	1	1	0	1	CELL.LONG_IO_H[1]
1	0	1	1	1	1	1	0	CELL.DEC_H[0]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_S0[0]

xc4000h IO_S1_W switchbox INT muxes IMUX_IO_T[1]
Bits								Destination
MAIN[0][1]	MAIN[1][2]	MAIN[11][2]	MAIN[2][1]	MAIN[2][2]	MAIN[3][1]	MAIN[1][1]	MAIN[0][2]	CELL.IMUX_IO_T[1]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	0	1	1	1	CELL.LONG_IO_H[0]
0	0	1	0	1	0	1	1	CELL.GCLK[0]
0	0	1	1	0	1	0	1	CELL.LONG_IO_H[3]
0	0	1	1	0	1	1	0	CELL.LONG_IO_H[2]
0	0	1	1	1	0	0	1	CELL.DEC_H[0]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_S0[0]
0	1	1	1	1	1	0	1	CELL.LONG_IO_H[1]
0	1	1	1	1	1	1	0	CELL.DEC_H[1]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_S0[1]
1	0	1	1	1	0	1	1	CELL.DOUBLE_IO_S1[1]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_S1[0]

xc4000h IO_S1_W switchbox INT muxes IMUX_HIO_O[0]
Bits	Destination
MAIN[26][0]	CELL.IMUX_HIO_O[0]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_F4

xc4000h IO_S1_W switchbox INT muxes IMUX_HIO_O[1]
Bits	Destination
MAIN[21][0]	CELL.IMUX_HIO_O[1]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_F4

xc4000h IO_S1_W switchbox INT muxes IMUX_HIO_O[2]
Bits	Destination
MAIN[12][0]	CELL.IMUX_HIO_O[2]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_G4

xc4000h IO_S1_W switchbox INT muxes IMUX_HIO_O[3]
Bits	Destination
MAIN[8][0]	CELL.IMUX_HIO_O[3]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_G4

xc4000h IO_S1_W switchbox INT muxes IMUX_HIO_T[0]
Bits	Destination
MAIN[28][0]	CELL.IMUX_HIO_T[0]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_OK[0]

xc4000h IO_S1_W switchbox INT muxes IMUX_HIO_T[1]
Bits	Destination
MAIN[21][1]	CELL.IMUX_HIO_T[1]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_IK[0]

xc4000h IO_S1_W switchbox INT muxes IMUX_HIO_T[2]
Bits	Destination
MAIN[14][0]	CELL.IMUX_HIO_T[2]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_IK[1]

xc4000h IO_S1_W switchbox INT muxes IMUX_HIO_T[3]
Bits	Destination
MAIN[5][0]	CELL.IMUX_HIO_T[3]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_OK[1]

xc4000h IO_S1_W switchbox INT muxes OUT_IO_SN_I1[0]
Bits	Destination
MAIN[20][1]	CELL.OUT_IO_SN_I1[0]
	Source
0	CELL.OUT_HIO_I[1]
1	CELL.OUT_HIO_I[0]

xc4000h IO_S1_W switchbox INT muxes OUT_IO_SN_I1[1]
Bits	Destination
MAIN[15][0]	CELL.OUT_IO_SN_I1[1]
	Source
0	CELL.OUT_HIO_I[2]
1	CELL.OUT_HIO_I[3]

xc4000h IO_S1_W switchbox INT muxes OUT_IO_SN_I2[0]
Bits	Destination
MAIN[31][0]	CELL.OUT_IO_SN_I2[0]
	Source
0	CELL.OUT_HIO_I[0]
1	CELL.OUT_HIO_I[1]

xc4000h IO_S1_W switchbox INT muxes OUT_IO_SN_I2[1]
Bits	Destination
MAIN[3][0]	CELL.OUT_IO_SN_I2[1]
	Source
0	CELL.OUT_HIO_I[3]
1	CELL.OUT_HIO_I[2]

Bels HIO

xc4000h IO_S1_W bel HIO pins
Pin	Direction	HIO[0]	HIO[1]	HIO[2]	HIO[3]
O	in	CELL.IMUX_HIO_O[0] invert by !MAIN[27][0]	CELL.IMUX_HIO_O[1] invert by !MAIN[22][0]	CELL.IMUX_HIO_O[2] invert by !MAIN[13][0]	CELL.IMUX_HIO_O[3] invert by !MAIN[7][0]
T	in	CELL.IMUX_HIO_T[0] invert by !MAIN[29][0]	CELL.IMUX_HIO_T[1] invert by !MAIN[20][0]	CELL.IMUX_HIO_T[2] invert by !MAIN[14][1]	CELL.IMUX_HIO_T[3] invert by !MAIN[4][0]
I	out	CELL.OUT_HIO_I[0]	CELL.OUT_HIO_I[1]	CELL.OUT_HIO_I[2]	CELL.OUT_HIO_I[3]
CLKIN	out	CELL.OUT_IO_CLKIN	-	-	-

xc4000h IO_S1_W bel HIO attribute bits
Attribute	HIO[0]	HIO[1]	HIO[2]	HIO[3]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
ISTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OSTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OMODE	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]
I_INV	!MAIN[32][0]	!MAIN[19][0]	!MAIN[16][0]	!MAIN[2][0]
READBACK_I bit 0	!MAIN[18][2]	!MAIN[18][3]	!MAIN[16][2]	!MAIN[17][3]

xc4000h IO_S1_W enum IO_PULL
HIO[0].PULL	MAIN[24][0]	MAIN[25][0]
HIO[1].PULL	MAIN[24][1]	MAIN[22][1]
HIO[2].PULL	MAIN[11][1]	MAIN[13][1]
HIO[3].PULL	MAIN[10][0]	MAIN[9][0]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

xc4000h IO_S1_W enum IO_STD
HIO[0].ISTD	MAIN[33][0]
HIO[1].ISTD	MAIN[18][0]
HIO[2].ISTD	MAIN[15][1]
HIO[3].ISTD	MAIN[1][0]
CMOS	0
TTL	1

xc4000h IO_S1_W enum IO_STD
HIO[0].OSTD	MAIN[34][0]
HIO[1].OSTD	MAIN[18][1]
HIO[2].OSTD	MAIN[16][1]
HIO[3].OSTD	MAIN[0][0]
CMOS	1
TTL	0

xc4000h IO_S1_W enum HIO_OMODE
HIO[0].OMODE	MAIN[23][0]
HIO[1].OMODE	MAIN[23][1]
HIO[2].OMODE	MAIN[12][1]
HIO[3].OMODE	MAIN[11][0]
CAP	1
RES	0

Bels DEC

xc4000h IO_S1_W bel DEC pins
Pin	Direction	DEC[0]	DEC[1]	DEC[2]
I	in	CELL.OUT_IO_SN_I1[0]	CELL.IMUX_CLB_C4	CELL.OUT_IO_SN_I1[1]
O1	bidir	CELL.DEC_H[0]	CELL.DEC_H[0]	CELL.DEC_H[0]
O2	bidir	CELL.DEC_H[1]	CELL.DEC_H[1]	CELL.DEC_H[1]
O3	bidir	CELL.DEC_H[2]	CELL.DEC_H[2]	CELL.DEC_H[2]
O4	bidir	CELL.DEC_H[3]	CELL.DEC_H[3]	CELL.DEC_H[3]

xc4000h IO_S1_W bel DEC attribute bits
Attribute	DEC[0]	DEC[1]	DEC[2]
O1_P	!MAIN[14][3]	!MAIN[12][4]	MAIN[13][3]
O1_N	MAIN[14][4]	MAIN[12][3]	!MAIN[13][4]
O2_P	!MAIN[9][3]	!MAIN[11][4]	MAIN[10][3]
O2_N	MAIN[9][4]	MAIN[11][3]	!MAIN[10][4]
O3_P	!MAIN[3][3]	!MAIN[5][4]	MAIN[4][3]
O3_N	MAIN[3][4]	MAIN[5][3]	!MAIN[4][4]
O4_P	!MAIN[8][3]	!MAIN[6][4]	MAIN[7][3]
O4_N	MAIN[8][4]	MAIN[6][3]	!MAIN[7][4]

Bel wires

xc4000h IO_S1_W bel wires
Wire	Pins
CELL.DEC_H[0]	DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_H[1]	DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.DEC_H[2]	DEC[0].O3, DEC[1].O3, DEC[2].O3
CELL.DEC_H[3]	DEC[0].O4, DEC[1].O4, DEC[2].O4
CELL.IMUX_CLB_C4	DEC[1].I
CELL.IMUX_HIO_O[0]	HIO[0].O
CELL.IMUX_HIO_O[1]	HIO[1].O
CELL.IMUX_HIO_O[2]	HIO[2].O
CELL.IMUX_HIO_O[3]	HIO[3].O
CELL.IMUX_HIO_T[0]	HIO[0].T
CELL.IMUX_HIO_T[1]	HIO[1].T
CELL.IMUX_HIO_T[2]	HIO[2].T
CELL.IMUX_HIO_T[3]	HIO[3].T
CELL.OUT_IO_SN_I1[0]	DEC[0].I
CELL.OUT_IO_SN_I1[1]	DEC[2].I
CELL.OUT_HIO_I[0]	HIO[0].I
CELL.OUT_HIO_I[1]	HIO[1].I
CELL.OUT_HIO_I[2]	HIO[2].I
CELL.OUT_HIO_I[3]	HIO[3].I
CELL.OUT_IO_CLKIN	HIO[0].CLKIN

Bitstream

xc4000h IO_S1_W rect MAIN
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B12	INT: !pass CELL.SINGLE_H_E[2] ← CELL.LONG_V[1]	INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_H_E[7]	INT: !bipass CELL.SINGLE_H_E[7] = CELL.SINGLE_V[7]	INT: !bipass CELL.SINGLE_V[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V[7]	INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_V[5]	-	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H_E[2] = CELL.SINGLE_V[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_H2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_V0[0]	INT: !pass CELL.SINGLE_V[7] ← CELL.TIE_0	-	INT: !buffer CELL.LONG_V[2] ← CELL.SINGLE_H_E[3]	INT: !buffer CELL.LONG_H[5] ← CELL.SINGLE_V[6]	-	-	INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_CLB_X_S	INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_CLB_X_S	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_CLB_X_S	INT: !pass CELL.SINGLE_H[7] ← CELL.TIE_0	INT: mux CELL.IMUX_CLB_F2 bit 3	INT: mux CELL.IMUX_CLB_F2 bit 7	INT: mux CELL.IMUX_CLB_F4 bit 1	INT: mux CELL.IMUX_CLB_F4 bit 2	INT: mux CELL.IMUX_CLB_C4 bit 3	INT: mux CELL.IMUX_CLB_C4 bit 1	INT: mux CELL.IMUX_CLB_G4 bit 7	INT: mux CELL.IMUX_CLB_G4 bit 6	INT: mux CELL.IMUX_CLB_G2 bit 6	INT: mux CELL.IMUX_CLB_G2 bit 2	INT: mux CELL.IMUX_CLB_C2 bit 4	INT: mux CELL.IMUX_CLB_C2 bit 2
B11	-	INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V[4]	INT: !buffer CELL.LONG_V[1] ← CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[7] = CELL.SINGLE_V_S[7]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V[6]	INT: !buffer CELL.LONG_V[5] ← CELL.SINGLE_H[6]	-	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V_S[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_H_E[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.SINGLE_V[2]	-	INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V2[0]	-	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_V2[0]	-	-	-	-	-	-	-	-	-	INT: mux CELL.IMUX_CLB_F2 bit 2	INT: mux CELL.IMUX_CLB_F2 bit 4	INT: mux CELL.IMUX_CLB_F4 bit 0	INT: mux CELL.IMUX_CLB_F4 bit 6	INT: mux CELL.IMUX_CLB_C4 bit 6	INT: mux CELL.IMUX_CLB_C4 bit 2	INT: mux CELL.IMUX_CLB_G4 bit 5	INT: mux CELL.IMUX_CLB_G4 bit 1	INT: mux CELL.IMUX_CLB_G2 bit 0	INT: mux CELL.IMUX_CLB_G2 bit 4	INT: mux CELL.IMUX_CLB_G2 bit 3	INT: mux CELL.IMUX_CLB_C2 bit 0	INT: mux CELL.IMUX_CLB_C2 bit 3
B10	INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_H[5]	-	INT: !bipass CELL.SINGLE_V[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_V_S[6]	INT: !bipass CELL.SINGLE_H[6] = CELL.SINGLE_H_E[6]	INT: !bipass CELL.SINGLE_H_E[6] = CELL.SINGLE_V[6]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.SINGLE_H_E[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_H_E[3]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V_S[3]	INT: !bipass CELL.DOUBLE_H2[0] = CELL.DOUBLE_V0[0]	INT: !bipass CELL.SINGLE_H[3] = CELL.SINGLE_V[3]	INT: !bipass CELL.SINGLE_V[3] = CELL.SINGLE_V_S[3]	INT: !pass CELL.SINGLE_V[4] ← CELL.LONG_H[3]	-	-	-	-	-	INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_CLB_XQ_S	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_CLB_XQ_S	INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_CLB_XQ_S	INT: mux CELL.IMUX_CLB_F2 bit 1	INT: !pass CELL.SINGLE_H[3] ← CELL.TIE_0	INT: mux CELL.IMUX_CLB_F2 bit 6	INT: mux CELL.IMUX_CLB_F4 bit 7	INT: mux CELL.IMUX_CLB_F4 bit 4	INT: mux CELL.IMUX_CLB_C4 bit 7	INT: mux CELL.IMUX_CLB_C4 bit 5	INT: mux CELL.IMUX_CLB_G4 bit 2	INT: mux CELL.IMUX_CLB_G4 bit 3	INT: mux CELL.IMUX_CLB_G2 bit 7	INT: mux CELL.IMUX_CLB_G2 bit 8	INT: mux CELL.IMUX_CLB_C2 bit 5	INT: mux CELL.IMUX_CLB_C2 bit 7
B9	-	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V[4]	INT: !bipass CELL.SINGLE_V[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H_E[4] = CELL.SINGLE_V_S[4]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_H_E[4]	INT: !bipass CELL.SINGLE_H[4] = CELL.SINGLE_V_S[4]	INT: !pass CELL.SINGLE_H_E[3] ← CELL.LONG_V[2]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_H2[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V0[1]	-	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_V[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_H_E[0]	-	INT: !pass CELL.SINGLE_V[0] ← CELL.TIE_0	INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_IO_SN_I2[1]	INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_SN_I2[1]	INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_IO_SN_I2[1]	-	INT: !pass CELL.SINGLE_H[6] ← CELL.TIE_0	INT: mux CELL.IMUX_CLB_F2 bit 0	INT: mux CELL.IMUX_CLB_F2 bit 5	INT: mux CELL.IMUX_CLB_F4 bit 3	-	INT: mux CELL.IMUX_CLB_F4 bit 5	INT: mux CELL.IMUX_CLB_C4 bit 0	INT: mux CELL.IMUX_CLB_C4 bit 4	INT: mux CELL.IMUX_CLB_G4 bit 0	INT: mux CELL.IMUX_CLB_G4 bit 4	INT: mux CELL.IMUX_CLB_G2 bit 1	INT: mux CELL.IMUX_CLB_G2 bit 5	INT: mux CELL.IMUX_CLB_C2 bit 1	INT: mux CELL.IMUX_CLB_C2 bit 6
B8	INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_H[4]	INT: !bipass CELL.SINGLE_V[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V_S[5]	INT: !bipass CELL.SINGLE_H_E[5] = CELL.SINGLE_V[5]	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_H_E[5]	INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V2[1]	INT: !bipass CELL.DOUBLE_H2[1] = CELL.DOUBLE_V0[1]	INT: !pass CELL.SINGLE_H_E[1] ← CELL.LONG_V[0]	INT: !bipass CELL.SINGLE_H_E[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_H_E[1]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V[1]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V[0]	INT: !bipass CELL.SINGLE_H_E[0] = CELL.SINGLE_V[0]	-	-	-	-	-	-	INT: !buffer CELL.LONG_H[4] ← CELL.SINGLE_V[5]	INT: !buffer CELL.LONG_V[0] ← CELL.SINGLE_H_E[1]	INT: !buffer CELL.LONG_V[4] ← CELL.SINGLE_H[5]	-	-	INT: !buffer CELL.LONG_V[3] ← CELL.SINGLE_H[4]	-	INT: !pass CELL.SINGLE_H[0] ← CELL.TIE_0	-	-	-	-	-	-	-
B7	-	-	-	-	INT: !bipass CELL.SINGLE_H[5] = CELL.SINGLE_V[5]	INT: !pass CELL.SINGLE_H[4] ← CELL.LONG_V[3]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_V2[1]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_V2[1]	-	INT: !bipass CELL.SINGLE_V[1] = CELL.SINGLE_V_S[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.SINGLE_V_S[0]	INT: !bipass CELL.SINGLE_H[1] = CELL.SINGLE_V_S[1]	INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_V[4]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.LONG_V[1] bit 1	INT: mux CELL.LONG_V[2] bit 0	INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1	INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0]	INT: mux CELL.IMUX_IO_OK[0] bit 6	INT: mux CELL.IMUX_IO_OK[0] bit 5	INT: mux CELL.IMUX_IO_OK[0] bit 4	INT: mux CELL.IMUX_IO_OK[0] bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 1	INT: mux CELL.IMUX_IO_OK[0] bit 3	INT: mux CELL.IMUX_IO_OK[0] bit 2	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0]	INT: mux CELL.IMUX_IO_IK[0] bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 1	INT: mux CELL.IMUX_IO_IK[0] bit 3	INT: mux CELL.IMUX_IO_IK[0] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 5	INT: mux CELL.IMUX_IO_IK[1] bit 6	INT: mux CELL.IMUX_IO_IK[1] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 3	INT: mux CELL.IMUX_IO_OK[1] bit 5	INT: mux CELL.IMUX_IO_OK[1] bit 6	INT: mux CELL.IMUX_IO_OK[1] bit 4	INT: mux CELL.IMUX_IO_OK[1] bit 3	INT: mux CELL.LONG_V[5] bit 0	INT: mux CELL.LONG_V[5] bit 2	INT: mux CELL.LONG_V[3] bit 1	INT: mux CELL.LONG_V[3] bit 2	-	INT: mux CELL.LONG_IO_H[0] bit 1	-	INT: mux CELL.LONG_V[4] bit 1	INT: mux CELL.LONG_V[4] bit 2	-
B5	INT: mux CELL.LONG_V[1] bit 3	INT: mux CELL.LONG_V[1] bit 0	INT: mux CELL.LONG_V[1] bit 2	INT: mux CELL.LONG_V[2] bit 1	INT: mux CELL.LONG_V[2] bit 3	INT: mux CELL.LONG_V[2] bit 2	INT: mux CELL.LONG_V[0] bit 1	INT: mux CELL.LONG_V[0] bit 0	INT: mux CELL.LONG_V[0] bit 2	INT: mux CELL.LONG_V[0] bit 3	INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_IO_SN_I1[0]	INT: !buffer CELL.LONG_H[3] ← CELL.SINGLE_V[4]	INT: mux CELL.IMUX_IO_OK[0] bit 7	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.IMUX_IO_IK[0] bit 4	INT: mux CELL.IMUX_IO_IK[0] bit 5	INT: mux CELL.IMUX_IO_IK[0] bit 6	INT: mux CELL.IMUX_IO_IK[0] bit 7	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 0	INT: mux CELL.IMUX_IO_IK[1] bit 7	INT: mux CELL.IMUX_IO_OK[1] bit 2	INT: mux CELL.IMUX_IO_OK[1] bit 1	INT: mux CELL.IMUX_IO_OK[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 7	INT: mux CELL.LONG_V[5] bit 1	INT: mux CELL.LONG_V[5] bit 3	INT: mux CELL.LONG_V[3] bit 0	INT: mux CELL.LONG_V[3] bit 3	INT: mux CELL.LONG_V[4] bit 3	INT: mux CELL.LONG_IO_H[3] bit 1	-	INT: mux CELL.LONG_V[4] bit 0	-	-
B4	INT: !pass CELL.SINGLE_V[4] ← CELL.DEC_H[1]	INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_IO_H[3]	INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_IO_H[2]	INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.SINGLE_V[7] ← CELL.DEC_H[0]	INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[2]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1	INT: mux CELL.IMUX_IO_O1[0] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 5	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0]	-	INT: mux CELL.LONG_IO_H[3] bit 0	INT: mux CELL.LONG_IO_H[2] bit 0	INT: mux CELL.LONG_IO_H[2] bit 1	INT: mux CELL.LONG_IO_H[2] bit 2	INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[3]	INT: mux CELL.LONG_IO_H[1] bit 1	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[1]	INT: mux CELL.LONG_IO_H[0] bit 0	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[0]	DEC[0]: O1_N	DEC[2]: ! O1_N	DEC[1]: ! O1_P	DEC[1]: ! O2_P	DEC[2]: ! O2_N	DEC[0]: O2_N	DEC[0]: O4_N	DEC[2]: ! O4_N	DEC[1]: ! O4_P	DEC[1]: ! O3_P	DEC[2]: ! O3_N	DEC[0]: O3_N	INT: mux CELL.IMUX_IO_O1[1] bit 4	INT: mux CELL.IMUX_IO_O1[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 5
B3	INT: mux CELL.DBUF_IO_H[1] bit 1	INT: mux CELL.DBUF_IO_H[1] bit 2	INT: mux CELL.DBUF_IO_H[1] bit 3	INT: !bipass CELL.DOUBLE_IO_S0[3] = CELL.DOUBLE_IO_S2[3]	INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_S1[3]	INT: !bipass CELL.DOUBLE_IO_S0[2] = CELL.DOUBLE_IO_S2[2]	-	INT: mux CELL.IMUX_IO_O1[0] bit 1	INT: mux CELL.IMUX_IO_O1[0] bit 2	INT: mux CELL.IMUX_IO_O1[0] bit 4	INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_S1[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S1[1]	INT: mux CELL.LONG_IO_H[1] bit 3	INT: mux CELL.LONG_IO_H[2] bit 3	INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0]	-	HIO[1]: ! READBACK_I bit 0	HIO[3]: ! READBACK_I bit 0	INT: mux CELL.LONG_IO_H[1] bit 0	INT: mux CELL.LONG_IO_H[1] bit 2	DEC[0]: ! O1_P	DEC[2]: O1_P	DEC[1]: O1_N	DEC[1]: O2_N	DEC[2]: O2_P	DEC[0]: ! O2_P	DEC[0]: ! O4_P	DEC[2]: O4_P	DEC[1]: O4_N	DEC[1]: O3_N	DEC[2]: O3_P	DEC[0]: ! O3_P	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.IMUX_IO_O1[1] bit 0
B2	INT: !pass CELL.DOUBLE_IO_S2[0] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_S2[1] ← CELL.DBUF_IO_H[0]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S2[3]	INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_S2[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S0[3]	INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_S0[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S1[2]	INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_S1[2]	INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S0[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S0[1]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S2[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S2[0]	INT: !bipass CELL.DOUBLE_IO_S0[0] = CELL.DOUBLE_IO_S2[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_S0[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S0[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_S1[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_S1[0]	HIO[0]: ! READBACK_I bit 0	-	HIO[2]: ! READBACK_I bit 0	-	-	-	-	INT: mux CELL.IMUX_IO_T[1] bit 5	INT: !pass CELL.DOUBLE_IO_S0[0] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_S0[1] ← CELL.DBUF_IO_H[1]	INT: mux CELL.DBUF_IO_H[0] bit 2	INT: mux CELL.DBUF_IO_H[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 7	INT: mux CELL.IMUX_IO_T[0] bit 2	INT: mux CELL.IMUX_IO_T[0] bit 6	INT: mux CELL.IMUX_IO_T[1] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 6	INT: mux CELL.IMUX_IO_T[1] bit 0
B1	INT: !pass CELL.DOUBLE_IO_S2[3] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_S2[2] ← CELL.DBUF_IO_H[0]	INT: mux CELL.DBUF_IO_H[1] bit 0	INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_S0[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_S1[3]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S2[2]	INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_S2[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_S0[2]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_S2[1]	INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_S2[1]	INT: !bipass CELL.DOUBLE_IO_S0[1] = CELL.DOUBLE_IO_S2[1]	HIO[1]: PULL bit 1	HIO[1]: OMODE bit 0	HIO[1]: PULL bit 0	INT: mux CELL.IMUX_HIO_T[1] bit 0	INT: mux CELL.OUT_IO_SN_I1[0] bit 0	-	HIO[1]: OSTD bit 0	-	HIO[2]: OSTD bit 0	HIO[2]: ISTD bit 0	HIO[2]: !invert T	HIO[2]: PULL bit 0	HIO[2]: OMODE bit 0	HIO[2]: PULL bit 1	INT: !pass CELL.DOUBLE_IO_S0[3] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_S0[2] ← CELL.DBUF_IO_H[1]	INT: mux CELL.DBUF_IO_H[0] bit 0	INT: mux CELL.DBUF_IO_H[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 4	INT: mux CELL.IMUX_IO_T[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 0	INT: mux CELL.IMUX_IO_T[1] bit 2	INT: mux CELL.IMUX_IO_T[1] bit 4	INT: mux CELL.IMUX_IO_T[1] bit 1	INT: mux CELL.IMUX_IO_T[1] bit 7
B0	-	HIO[0]: OSTD bit 0	HIO[0]: ISTD bit 0	HIO[0]: ! I_INV	INT: mux CELL.OUT_IO_SN_I2[0] bit 0	-	HIO[0]: !invert T	INT: mux CELL.IMUX_HIO_T[0] bit 0	HIO[0]: !invert O	INT: mux CELL.IMUX_HIO_O[0] bit 0	HIO[0]: PULL bit 0	HIO[0]: PULL bit 1	HIO[0]: OMODE bit 0	HIO[1]: !invert O	INT: mux CELL.IMUX_HIO_O[1] bit 0	HIO[1]: !invert T	HIO[1]: ! I_INV	HIO[1]: ISTD bit 0	-	HIO[2]: ! I_INV	INT: mux CELL.OUT_IO_SN_I1[1] bit 0	INT: mux CELL.IMUX_HIO_T[2] bit 0	HIO[2]: !invert O	INT: mux CELL.IMUX_HIO_O[2] bit 0	HIO[3]: OMODE bit 0	HIO[3]: PULL bit 1	HIO[3]: PULL bit 0	INT: mux CELL.IMUX_HIO_O[3] bit 0	HIO[3]: !invert O	INT: mux CELL.IMUX_IO_T[0] bit 5	INT: mux CELL.IMUX_HIO_T[3] bit 0	HIO[3]: !invert T	INT: mux CELL.OUT_IO_SN_I2[1] bit 0	HIO[3]: ! I_INV	HIO[3]: ISTD bit 0	HIO[3]: OSTD bit 0

xc4000h IO_S1_W rect MAIN_E
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile IO_N0

Cells: 3

Switchbox INT

xc4000h IO_N0 switchbox INT programmable buffers
Destination	Source	Bit
CELL.LONG_H[0]	CELL.SINGLE_V[1]	!MAIN_S[21][8]
CELL.LONG_H[1]	CELL.SINGLE_V[2]	!MAIN_S[25][8]
CELL.LONG_H[2]	CELL.SINGLE_V[3]	!MAIN[24][1]

xc4000h IO_N0 switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_V[0]	CELL.DEC_H[0]	!MAIN[19][2]
CELL.SINGLE_V[0]	CELL.OUT_IO_SN_I2_E1	!MAIN[22][1]
CELL.SINGLE_V[1]	CELL.LONG_H[0]	!MAIN_S[23][8]
CELL.SINGLE_V[1]	CELL.LONG_IO_H[0]	!MAIN[15][2]
CELL.SINGLE_V[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[22][0]
CELL.SINGLE_V[2]	CELL.LONG_H[1]	!MAIN_S[29][8]
CELL.SINGLE_V[2]	CELL.LONG_IO_H[1]	!MAIN[17][2]
CELL.SINGLE_V[2]	CELL.OUT_IO_SN_I1[0]	!MAIN[25][2]
CELL.SINGLE_V[3]	CELL.LONG_H[2]	!MAIN_S[28][9]
CELL.SINGLE_V[3]	CELL.DEC_H[1]	!MAIN[30][2]
CELL.SINGLE_V[3]	CELL.OUT_IO_SN_I1_E1	!MAIN[29][2]
CELL.SINGLE_V[4]	CELL.DEC_H[2]	!MAIN[35][2]
CELL.SINGLE_V[4]	CELL.OUT_IO_SN_I2_E1	!MAIN[35][0]
CELL.SINGLE_V[5]	CELL.LONG_IO_H[2]	!MAIN[33][2]
CELL.SINGLE_V[5]	CELL.OUT_IO_SN_I2[0]	!MAIN[32][0]
CELL.SINGLE_V[6]	CELL.LONG_IO_H[3]	!MAIN[34][2]
CELL.SINGLE_V[6]	CELL.OUT_IO_SN_I1[0]	!MAIN[25][1]
CELL.SINGLE_V[7]	CELL.DEC_H[3]	!MAIN[31][2]
CELL.SINGLE_V[7]	CELL.OUT_IO_SN_I1_E1	!MAIN[32][2]
CELL.DOUBLE_V0[0]	CELL.OUT_IO_SN_I1_E1	!MAIN[21][3]
CELL.DOUBLE_V0[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[30][0]
CELL.DOUBLE_V1[0]	CELL.OUT_IO_SN_I1[0]	!MAIN[20][3]
CELL.DOUBLE_V1[1]	CELL.OUT_IO_SN_I2_E1	!MAIN[31][0]
CELL.DOUBLE_IO_N0[0]	CELL.DBUF_IO_H[0]	!MAIN[35][4]
CELL.DOUBLE_IO_N0[1]	CELL.DBUF_IO_H[0]	!MAIN[34][4]
CELL.DOUBLE_IO_N0[2]	CELL.DBUF_IO_H[0]	!MAIN[34][5]
CELL.DOUBLE_IO_N0[3]	CELL.DBUF_IO_H[0]	!MAIN[35][5]
CELL.DOUBLE_IO_N2[0]	CELL.DBUF_IO_H[1]	!MAIN[10][4]
CELL.DOUBLE_IO_N2[1]	CELL.DBUF_IO_H[1]	!MAIN[9][4]
CELL.DOUBLE_IO_N2[2]	CELL.DBUF_IO_H[1]	!MAIN[9][5]
CELL.DOUBLE_IO_N2[3]	CELL.DBUF_IO_H[1]	!MAIN[10][5]

xc4000h IO_N0 switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_V[0]	CELL.DOUBLE_IO_N0[0]	!MAIN[24][4]
CELL.SINGLE_V[0]	CELL.DOUBLE_IO_N2[0]	!MAIN[22][4]
CELL.SINGLE_V[1]	CELL.DOUBLE_IO_N1[0]	!MAIN[19][4]
CELL.SINGLE_V[2]	CELL.DOUBLE_IO_N0[1]	!MAIN[26][5]
CELL.SINGLE_V[2]	CELL.DOUBLE_IO_N2[1]	!MAIN[27][4]
CELL.SINGLE_V[3]	CELL.DOUBLE_IO_N1[1]	!MAIN[25][3]
CELL.SINGLE_V[4]	CELL.DOUBLE_IO_N0[2]	!MAIN[29][5]
CELL.SINGLE_V[4]	CELL.DOUBLE_IO_N2[2]	!MAIN[30][4]
CELL.SINGLE_V[5]	CELL.DOUBLE_IO_N1[2]	!MAIN[28][4]
CELL.SINGLE_V[6]	CELL.DOUBLE_IO_N0[3]	!MAIN[32][4]
CELL.SINGLE_V[6]	CELL.DOUBLE_IO_N2[3]	!MAIN[32][5]
CELL.SINGLE_V[7]	CELL.DOUBLE_IO_N1[3]	!MAIN[31][3]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_N0[1]	!MAIN[27][5]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_N1[1]	!MAIN[24][3]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_N2[1]	!MAIN[26][4]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_N0[2]	!MAIN[30][5]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_N1[2]	!MAIN[29][4]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_N2[2]	!MAIN[28][5]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_N0[0]	!MAIN[25][4]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_N1[0]	!MAIN[20][4]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_N2[0]	!MAIN[21][4]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_N0[3]	!MAIN[33][4]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_N1[3]	!MAIN[31][5]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_N2[3]	!MAIN[31][4]
CELL.DOUBLE_IO_N0[0]	CELL.DOUBLE_IO_N2[0]	!MAIN[23][4]
CELL.DOUBLE_IO_N0[1]	CELL.DOUBLE_IO_N2[1]	!MAIN[25][5]
CELL.DOUBLE_IO_N0[2]	CELL.DOUBLE_IO_N2[2]	!MAIN[30][3]
CELL.DOUBLE_IO_N0[3]	CELL.DOUBLE_IO_N2[3]	!MAIN[32][3]

xc4000h IO_N0 switchbox INT muxes DBUF_IO_H[0]
Bits				Destination
MAIN[7][4]	MAIN[8][4]	MAIN[7][5]	MAIN[8][5]	CELL.DBUF_IO_H[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_N2[0]
0	1	0	1	CELL.DOUBLE_IO_N2[2]
0	1	1	0	CELL.DOUBLE_IO_N2[3]
1	1	1	1	CELL.DOUBLE_IO_N2[1]

xc4000h IO_N0 switchbox INT muxes DBUF_IO_H[1]
Bits				Destination
MAIN[33][3]	MAIN[34][3]	MAIN[35][3]	MAIN[33][5]	CELL.DBUF_IO_H[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_N0[1]
0	1	0	1	CELL.DOUBLE_IO_N0[2]
0	1	1	0	CELL.DOUBLE_IO_N0[3]
1	1	1	1	CELL.DOUBLE_IO_N0[0]

xc4000h IO_N0 switchbox INT muxes LONG_V[0]
Bits				Destination
MAIN[26][1]	MAIN[27][1]	MAIN[29][1]	MAIN[28][1]	CELL.LONG_V[0]
				Source
0	0	0	1	CELL.LONG_IO_H[0]
0	0	1	0	CELL.DEC_H[3]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_N0 switchbox INT muxes LONG_V[1]
Bits				Destination
MAIN[35][1]	MAIN[33][1]	MAIN[34][0]	MAIN[34][1]	CELL.LONG_V[1]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_N0 switchbox INT muxes LONG_V[2]
Bits				Destination
MAIN[31][1]	MAIN[30][1]	MAIN[32][1]	MAIN[33][0]	CELL.LONG_V[2]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_N0 switchbox INT muxes LONG_V[3]
Bits				Destination
MAIN[6][1]	MAIN[6][0]	MAIN[7][0]	MAIN[7][1]	CELL.LONG_V[3]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_N0 switchbox INT muxes LONG_V[4]
Bits				Destination
MAIN[5][1]	MAIN[1][0]	MAIN[2][0]	MAIN[2][1]	CELL.LONG_V[4]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_N0 switchbox INT muxes LONG_V[5]
Bits				Destination
MAIN[8][1]	MAIN[8][0]	MAIN[9][1]	MAIN[9][0]	CELL.LONG_V[5]
				Source
0	0	0	1	CELL.LONG_IO_H[3]
0	0	1	0	CELL.DEC_H[0]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_N0 switchbox INT muxes LONG_IO_H[0]
Bits		Destination
MAIN[4][0]	MAIN[16][2]	CELL.LONG_IO_H[0]
		Source
0	0	CELL.LONG_V[0]
0	1	CELL.SINGLE_V[1]
1	1	off

xc4000h IO_N0 switchbox INT muxes LONG_IO_H[1]
Bits				Destination
MAIN[23][3]	MAIN[15][3]	MAIN[18][2]	MAIN[16][3]	CELL.LONG_IO_H[1]
				Source
0	0	0	1	CELL.LONG_V[1]
0	0	1	0	CELL.LONG_V[3]
0	1	1	1	CELL.SINGLE_V[2]
1	1	1	1	off

xc4000h IO_N0 switchbox INT muxes LONG_IO_H[2]
Bits				Destination
MAIN[22][3]	MAIN[20][2]	MAIN[21][2]	MAIN[22][2]	CELL.LONG_IO_H[2]
				Source
0	0	0	1	CELL.LONG_V[2]
0	0	1	0	CELL.LONG_V[4]
0	1	1	1	CELL.SINGLE_V[5]
1	1	1	1	off

xc4000h IO_N0 switchbox INT muxes LONG_IO_H[3]
Bits		Destination
MAIN[4][1]	MAIN[23][2]	CELL.LONG_IO_H[3]
		Source
0	0	CELL.LONG_V[5]
0	1	CELL.SINGLE_V[6]
1	1	off

xc4000h IO_N0 switchbox INT muxes IMUX_IO_O1[0]
Bits						Destination
MAIN[26][2]	MAIN[26][3]	MAIN[28][2]	MAIN[27][3]	MAIN[28][3]	MAIN[27][2]	CELL.IMUX_IO_O1[0]
						Source
0	0	0	1	1	1	CELL.DEC_H[1]
0	0	1	1	1	1	CELL.DOUBLE_V0[0]
0	1	0	0	1	1	CELL.DEC_H[3]
0	1	0	1	0	1	CELL.DEC_H[0]
0	1	0	1	1	0	CELL.LONG_V[5]
0	1	1	0	1	1	CELL.LONG_V[3]
0	1	1	1	0	1	CELL.LONG_V[4]
0	1	1	1	1	0	CELL.DEC_H[2]
1	1	0	1	1	1	CELL.DOUBLE_V1[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_N0 switchbox INT muxes IMUX_IO_O1[1]
Bits						Destination
MAIN[0][2]	MAIN[2][2]	MAIN[1][3]	MAIN[1][2]	MAIN[2][3]	MAIN[0][3]	CELL.IMUX_IO_O1[1]
						Source
0	0	0	1	1	1	CELL.DEC_H[0]
0	0	1	0	1	1	CELL.DEC_H[1]
0	0	1	1	0	1	CELL.DEC_H[3]
0	0	1	1	1	0	CELL_E.LONG_V[2]
0	1	0	1	1	1	CELL_E.LONG_V[0]
0	1	1	0	1	1	CELL.DEC_H[2]
0	1	1	1	0	1	CELL_E.LONG_V[1]
0	1	1	1	1	0	CELL_E.DOUBLE_V1[0]
1	0	1	1	1	1	CELL_E.DOUBLE_V0[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_N0 switchbox INT muxes IMUX_IO_OK[0]
Bits								Destination
MAIN[23][1]	MAIN[29][0]	MAIN[28][0]	MAIN[27][0]	MAIN[24][0]	MAIN[23][0]	MAIN[25][0]	MAIN[26][0]	CELL.IMUX_IO_OK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_V[3]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[2]

xc4000h IO_N0 switchbox INT muxes IMUX_IO_OK[1]
Bits								Destination
MAIN[10][1]	MAIN[12][0]	MAIN[13][0]	MAIN[11][0]	MAIN[10][0]	MAIN[13][1]	MAIN[12][1]	MAIN[11][1]	CELL.IMUX_IO_OK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_E.SINGLE_V[2]
0	1	1	1	1	1	0	1	CELL_E.SINGLE_V[3]
0	1	1	1	1	1	1	0	CELL_E.SINGLE_V[5]
1	1	1	1	1	1	1	1	CELL_E.SINGLE_V[4]

xc4000h IO_N0 switchbox INT muxes IMUX_IO_IK[0]
Bits								Destination
MAIN[18][1]	MAIN[19][1]	MAIN[20][1]	MAIN[21][1]	MAIN[19][0]	MAIN[18][0]	MAIN[20][0]	MAIN[21][0]	CELL.IMUX_IO_IK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_V[2]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[3]

xc4000h IO_N0 switchbox INT muxes IMUX_IO_IK[1]
Bits								Destination
MAIN[14][1]	MAIN[16][0]	MAIN[17][0]	MAIN[15][0]	MAIN[14][0]	MAIN[17][1]	MAIN[16][1]	MAIN[15][1]	CELL.IMUX_IO_IK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_E.SINGLE_V[2]
0	1	1	1	1	1	0	1	CELL_E.SINGLE_V[3]
0	1	1	1	1	1	1	0	CELL_E.SINGLE_V[4]
1	1	1	1	1	1	1	1	CELL_E.SINGLE_V[5]

xc4000h IO_N0 switchbox INT muxes IMUX_IO_T[0]
Bits								Destination
MAIN[5][4]	MAIN[3][4]	MAIN[6][6]	MAIN[6][4]	MAIN[4][4]	MAIN[6][5]	MAIN[5][5]	MAIN[4][5]	CELL.IMUX_IO_T[0]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	0	1	1	1	CELL.LONG_IO_H[3]
0	0	1	0	1	1	0	1	CELL.LONG_IO_H[0]
0	0	1	0	1	1	1	0	CELL.LONG_IO_H[2]
0	0	1	1	1	0	0	1	CELL.DEC_H[2]
0	0	1	1	1	0	1	0	CELL.GCLK[0]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_N1[0]
0	1	1	1	1	0	1	1	CELL.DOUBLE_IO_N2[1]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_N1[1]
1	0	1	1	1	1	0	1	CELL.LONG_IO_H[1]
1	0	1	1	1	1	1	0	CELL.DEC_H[3]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_N2[0]

xc4000h IO_N0 switchbox INT muxes IMUX_IO_T[1]
Bits								Destination
MAIN[1][4]	MAIN[0][5]	MAIN[11][4]	MAIN[3][5]	MAIN[2][5]	MAIN[2][4]	MAIN[1][5]	MAIN[0][4]	CELL.IMUX_IO_T[1]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	0	1	1	1	CELL.GCLK[0]
0	0	1	0	1	1	0	1	CELL.DEC_H[3]
0	0	1	1	0	0	1	1	CELL.LONG_IO_H[0]
0	0	1	1	1	0	0	1	CELL.LONG_IO_H[3]
0	0	1	1	1	0	1	0	CELL.LONG_IO_H[2]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_N1[1]
0	1	1	1	1	0	1	1	CELL.DOUBLE_IO_N2[1]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_N2[0]
1	0	1	1	1	1	0	1	CELL.LONG_IO_H[1]
1	0	1	1	1	1	1	0	CELL.DEC_H[2]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_N1[0]

xc4000h IO_N0 switchbox INT muxes IMUX_HIO_O[0]
Bits	Destination
MAIN[26][6]	CELL.IMUX_HIO_O[0]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_F2_N

xc4000h IO_N0 switchbox INT muxes IMUX_HIO_O[1]
Bits	Destination
MAIN[21][6]	CELL.IMUX_HIO_O[1]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_F2_N

xc4000h IO_N0 switchbox INT muxes IMUX_HIO_O[2]
Bits	Destination
MAIN[12][6]	CELL.IMUX_HIO_O[2]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_G2_N

xc4000h IO_N0 switchbox INT muxes IMUX_HIO_O[3]
Bits	Destination
MAIN[8][6]	CELL.IMUX_HIO_O[3]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_G2_N

xc4000h IO_N0 switchbox INT muxes IMUX_HIO_T[0]
Bits	Destination
MAIN[28][6]	CELL.IMUX_HIO_T[0]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_OK[0]

xc4000h IO_N0 switchbox INT muxes IMUX_HIO_T[1]
Bits	Destination
MAIN[21][5]	CELL.IMUX_HIO_T[1]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_IK[0]

xc4000h IO_N0 switchbox INT muxes IMUX_HIO_T[2]
Bits	Destination
MAIN[14][6]	CELL.IMUX_HIO_T[2]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_IK[1]

xc4000h IO_N0 switchbox INT muxes IMUX_HIO_T[3]
Bits	Destination
MAIN[5][6]	CELL.IMUX_HIO_T[3]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_OK[1]

xc4000h IO_N0 switchbox INT muxes OUT_IO_SN_I1[0]
Bits	Destination
MAIN[20][5]	CELL.OUT_IO_SN_I1[0]
	Source
0	CELL.OUT_HIO_I[1]
1	CELL.OUT_HIO_I[0]

xc4000h IO_N0 switchbox INT muxes OUT_IO_SN_I1[1]
Bits	Destination
MAIN[15][6]	CELL.OUT_IO_SN_I1[1]
	Source
0	CELL.OUT_HIO_I[2]
1	CELL.OUT_HIO_I[3]

xc4000h IO_N0 switchbox INT muxes OUT_IO_SN_I2[0]
Bits	Destination
MAIN[31][6]	CELL.OUT_IO_SN_I2[0]
	Source
0	CELL.OUT_HIO_I[0]
1	CELL.OUT_HIO_I[1]

xc4000h IO_N0 switchbox INT muxes OUT_IO_SN_I2[1]
Bits	Destination
MAIN[3][6]	CELL.OUT_IO_SN_I2[1]
	Source
0	CELL.OUT_HIO_I[3]
1	CELL.OUT_HIO_I[2]

Bels HIO

xc4000h IO_N0 bel HIO pins
Pin	Direction	HIO[0]	HIO[1]	HIO[2]	HIO[3]
O	in	CELL.IMUX_HIO_O[0] invert by !MAIN[27][6]	CELL.IMUX_HIO_O[1] invert by !MAIN[22][6]	CELL.IMUX_HIO_O[2] invert by !MAIN[13][6]	CELL.IMUX_HIO_O[3] invert by !MAIN[7][6]
T	in	CELL.IMUX_HIO_T[0] invert by !MAIN[29][6]	CELL.IMUX_HIO_T[1] invert by !MAIN[20][6]	CELL.IMUX_HIO_T[2] invert by !MAIN[14][5]	CELL.IMUX_HIO_T[3] invert by !MAIN[4][6]
I	out	CELL.OUT_HIO_I[0]	CELL.OUT_HIO_I[1]	CELL.OUT_HIO_I[2]	CELL.OUT_HIO_I[3]

xc4000h IO_N0 bel HIO attribute bits
Attribute	HIO[0]	HIO[1]	HIO[2]	HIO[3]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
ISTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OSTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OMODE	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]
I_INV	!MAIN[32][6]	!MAIN[19][6]	!MAIN[16][6]	!MAIN[2][6]
READBACK_I bit 0	!MAIN[18][4]	!MAIN[18][3]	!MAIN[16][4]	!MAIN[17][3]

xc4000h IO_N0 enum IO_PULL
HIO[0].PULL	MAIN[24][6]	MAIN[25][6]
HIO[1].PULL	MAIN[24][5]	MAIN[22][5]
HIO[2].PULL	MAIN[11][5]	MAIN[13][5]
HIO[3].PULL	MAIN[10][6]	MAIN[9][6]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

xc4000h IO_N0 enum IO_STD
HIO[0].ISTD	MAIN[33][6]
HIO[1].ISTD	MAIN[18][6]
HIO[2].ISTD	MAIN[15][5]
HIO[3].ISTD	MAIN[1][6]
CMOS	0
TTL	1

xc4000h IO_N0 enum IO_STD
HIO[0].OSTD	MAIN[34][6]
HIO[1].OSTD	MAIN[18][5]
HIO[2].OSTD	MAIN[16][5]
HIO[3].OSTD	MAIN[0][6]
CMOS	1
TTL	0

xc4000h IO_N0 enum HIO_OMODE
HIO[0].OMODE	MAIN[23][6]
HIO[1].OMODE	MAIN[23][5]
HIO[2].OMODE	MAIN[12][5]
HIO[3].OMODE	MAIN[11][6]
CAP	1
RES	0

Bels DEC

xc4000h IO_N0 bel DEC pins
Pin	Direction	DEC[0]	DEC[1]	DEC[2]
I	in	CELL.OUT_IO_SN_I1[0]	CELL.IMUX_CLB_C2_N	CELL.OUT_IO_SN_I1[1]
O1	bidir	CELL.DEC_H[0]	CELL.DEC_H[0]	CELL.DEC_H[0]
O2	bidir	CELL.DEC_H[1]	CELL.DEC_H[1]	CELL.DEC_H[1]
O3	bidir	CELL.DEC_H[2]	CELL.DEC_H[2]	CELL.DEC_H[2]
O4	bidir	CELL.DEC_H[3]	CELL.DEC_H[3]	CELL.DEC_H[3]

xc4000h IO_N0 bel DEC attribute bits
Attribute	DEC[0]	DEC[1]	DEC[2]
O1_P	!MAIN[8][3]	!MAIN[6][2]	MAIN[7][3]
O1_N	MAIN[8][2]	MAIN[6][3]	!MAIN[7][2]
O2_P	!MAIN[3][3]	!MAIN[5][2]	MAIN[4][3]
O2_N	MAIN[3][2]	MAIN[5][3]	!MAIN[4][2]
O3_P	!MAIN[9][3]	!MAIN[11][2]	MAIN[10][3]
O3_N	MAIN[9][2]	MAIN[11][3]	!MAIN[10][2]
O4_P	!MAIN[14][3]	!MAIN[12][2]	MAIN[13][3]
O4_N	MAIN[14][2]	MAIN[12][3]	!MAIN[13][2]

Bel wires

xc4000h IO_N0 bel wires
Wire	Pins
CELL.DEC_H[0]	DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_H[1]	DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.DEC_H[2]	DEC[0].O3, DEC[1].O3, DEC[2].O3
CELL.DEC_H[3]	DEC[0].O4, DEC[1].O4, DEC[2].O4
CELL.IMUX_CLB_C2_N	DEC[1].I
CELL.IMUX_HIO_O[0]	HIO[0].O
CELL.IMUX_HIO_O[1]	HIO[1].O
CELL.IMUX_HIO_O[2]	HIO[2].O
CELL.IMUX_HIO_O[3]	HIO[3].O
CELL.IMUX_HIO_T[0]	HIO[0].T
CELL.IMUX_HIO_T[1]	HIO[1].T
CELL.IMUX_HIO_T[2]	HIO[2].T
CELL.IMUX_HIO_T[3]	HIO[3].T
CELL.OUT_IO_SN_I1[0]	DEC[0].I
CELL.OUT_IO_SN_I1[1]	DEC[2].I
CELL.OUT_HIO_I[0]	HIO[0].I
CELL.OUT_HIO_I[1]	HIO[1].I
CELL.OUT_HIO_I[2]	HIO[2].I
CELL.OUT_HIO_I[3]	HIO[3].I

Bitstream

xc4000h IO_N0 rect MAIN
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B6	-	HIO[0]: OSTD bit 0	HIO[0]: ISTD bit 0	HIO[0]: ! I_INV	INT: mux CELL.OUT_IO_SN_I2[0] bit 0	-	HIO[0]: !invert T	INT: mux CELL.IMUX_HIO_T[0] bit 0	HIO[0]: !invert O	INT: mux CELL.IMUX_HIO_O[0] bit 0	HIO[0]: PULL bit 0	HIO[0]: PULL bit 1	HIO[0]: OMODE bit 0	HIO[1]: !invert O	INT: mux CELL.IMUX_HIO_O[1] bit 0	HIO[1]: !invert T	HIO[1]: ! I_INV	HIO[1]: ISTD bit 0	-	HIO[2]: ! I_INV	INT: mux CELL.OUT_IO_SN_I1[1] bit 0	INT: mux CELL.IMUX_HIO_T[2] bit 0	HIO[2]: !invert O	INT: mux CELL.IMUX_HIO_O[2] bit 0	HIO[3]: OMODE bit 0	HIO[3]: PULL bit 1	HIO[3]: PULL bit 0	INT: mux CELL.IMUX_HIO_O[3] bit 0	HIO[3]: !invert O	INT: mux CELL.IMUX_IO_T[0] bit 5	INT: mux CELL.IMUX_HIO_T[3] bit 0	HIO[3]: !invert T	INT: mux CELL.OUT_IO_SN_I2[1] bit 0	HIO[3]: ! I_INV	HIO[3]: ISTD bit 0	HIO[3]: OSTD bit 0
B5	INT: !pass CELL.DOUBLE_IO_N0[3] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_N0[2] ← CELL.DBUF_IO_H[0]	INT: mux CELL.DBUF_IO_H[1] bit 0	INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_N2[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N1[3]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N0[2]	INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_N0[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N2[2]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N0[1]	INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N0[1]	INT: !bipass CELL.DOUBLE_IO_N0[1] = CELL.DOUBLE_IO_N2[1]	HIO[1]: PULL bit 1	HIO[1]: OMODE bit 0	HIO[1]: PULL bit 0	INT: mux CELL.IMUX_HIO_T[1] bit 0	INT: mux CELL.OUT_IO_SN_I1[0] bit 0	-	HIO[1]: OSTD bit 0	-	HIO[2]: OSTD bit 0	HIO[2]: ISTD bit 0	HIO[2]: !invert T	HIO[2]: PULL bit 0	HIO[2]: OMODE bit 0	HIO[2]: PULL bit 1	INT: !pass CELL.DOUBLE_IO_N2[3] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_N2[2] ← CELL.DBUF_IO_H[1]	INT: mux CELL.DBUF_IO_H[0] bit 0	INT: mux CELL.DBUF_IO_H[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 2	INT: mux CELL.IMUX_IO_T[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 0	INT: mux CELL.IMUX_IO_T[1] bit 4	INT: mux CELL.IMUX_IO_T[1] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 1	INT: mux CELL.IMUX_IO_T[1] bit 6
B4	INT: !pass CELL.DOUBLE_IO_N0[0] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_N0[1] ← CELL.DBUF_IO_H[0]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N0[3]	INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_N0[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N2[3]	INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_N2[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N1[2]	INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_N1[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N2[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N2[1]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N0[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N0[0]	INT: !bipass CELL.DOUBLE_IO_N0[0] = CELL.DOUBLE_IO_N2[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N2[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N2[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N1[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N1[0]	HIO[0]: ! READBACK_I bit 0	-	HIO[2]: ! READBACK_I bit 0	-	-	-	-	INT: mux CELL.IMUX_IO_T[1] bit 5	INT: !pass CELL.DOUBLE_IO_N2[0] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_N2[1] ← CELL.DBUF_IO_H[1]	INT: mux CELL.DBUF_IO_H[0] bit 2	INT: mux CELL.DBUF_IO_H[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 4	INT: mux CELL.IMUX_IO_T[0] bit 7	INT: mux CELL.IMUX_IO_T[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 6	INT: mux CELL.IMUX_IO_T[1] bit 2	INT: mux CELL.IMUX_IO_T[1] bit 7	INT: mux CELL.IMUX_IO_T[1] bit 0
B3	INT: mux CELL.DBUF_IO_H[1] bit 1	INT: mux CELL.DBUF_IO_H[1] bit 2	INT: mux CELL.DBUF_IO_H[1] bit 3	INT: !bipass CELL.DOUBLE_IO_N0[3] = CELL.DOUBLE_IO_N2[3]	INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_N1[3]	INT: !bipass CELL.DOUBLE_IO_N0[2] = CELL.DOUBLE_IO_N2[2]	-	INT: mux CELL.IMUX_IO_O1[0] bit 1	INT: mux CELL.IMUX_IO_O1[0] bit 2	INT: mux CELL.IMUX_IO_O1[0] bit 4	INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N1[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N1[1]	INT: mux CELL.LONG_IO_H[1] bit 3	INT: mux CELL.LONG_IO_H[2] bit 3	INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0]	-	HIO[1]: ! READBACK_I bit 0	HIO[3]: ! READBACK_I bit 0	INT: mux CELL.LONG_IO_H[1] bit 0	INT: mux CELL.LONG_IO_H[1] bit 2	DEC[0]: ! O4_P	DEC[2]: O4_P	DEC[1]: O4_N	DEC[1]: O3_N	DEC[2]: O3_P	DEC[0]: ! O3_P	DEC[0]: ! O1_P	DEC[2]: O1_P	DEC[1]: O1_N	DEC[1]: O2_N	DEC[2]: O2_P	DEC[0]: ! O2_P	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 0
B2	INT: !pass CELL.SINGLE_V[4] ← CELL.DEC_H[2]	INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_IO_H[3]	INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_IO_H[2]	INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.SINGLE_V[7] ← CELL.DEC_H[3]	INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[1]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1	INT: mux CELL.IMUX_IO_O1[0] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 5	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0]	-	INT: mux CELL.LONG_IO_H[3] bit 0	INT: mux CELL.LONG_IO_H[2] bit 0	INT: mux CELL.LONG_IO_H[2] bit 1	INT: mux CELL.LONG_IO_H[2] bit 2	INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[0]	INT: mux CELL.LONG_IO_H[1] bit 1	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[1]	INT: mux CELL.LONG_IO_H[0] bit 0	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[0]	DEC[0]: O4_N	DEC[2]: ! O4_N	DEC[1]: ! O4_P	DEC[1]: ! O3_P	DEC[2]: ! O3_N	DEC[0]: O3_N	DEC[0]: O1_N	DEC[2]: ! O1_N	DEC[1]: ! O1_P	DEC[1]: ! O2_P	DEC[2]: ! O2_N	DEC[0]: O2_N	INT: mux CELL.IMUX_IO_O1[1] bit 4	INT: mux CELL.IMUX_IO_O1[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 5
B1	INT: mux CELL.LONG_V[1] bit 3	INT: mux CELL.LONG_V[1] bit 0	INT: mux CELL.LONG_V[1] bit 2	INT: mux CELL.LONG_V[2] bit 1	INT: mux CELL.LONG_V[2] bit 3	INT: mux CELL.LONG_V[2] bit 2	INT: mux CELL.LONG_V[0] bit 1	INT: mux CELL.LONG_V[0] bit 0	INT: mux CELL.LONG_V[0] bit 2	INT: mux CELL.LONG_V[0] bit 3	INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_IO_SN_I1[0]	INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[3]	INT: mux CELL.IMUX_IO_OK[0] bit 7	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.IMUX_IO_IK[0] bit 4	INT: mux CELL.IMUX_IO_IK[0] bit 5	INT: mux CELL.IMUX_IO_IK[0] bit 6	INT: mux CELL.IMUX_IO_IK[0] bit 7	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 0	INT: mux CELL.IMUX_IO_IK[1] bit 7	INT: mux CELL.IMUX_IO_OK[1] bit 2	INT: mux CELL.IMUX_IO_OK[1] bit 1	INT: mux CELL.IMUX_IO_OK[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 7	INT: mux CELL.LONG_V[5] bit 1	INT: mux CELL.LONG_V[5] bit 3	INT: mux CELL.LONG_V[3] bit 0	INT: mux CELL.LONG_V[3] bit 3	INT: mux CELL.LONG_V[4] bit 3	INT: mux CELL.LONG_IO_H[3] bit 1	-	INT: mux CELL.LONG_V[4] bit 0	-	-
B0	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.LONG_V[1] bit 1	INT: mux CELL.LONG_V[2] bit 0	INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1	INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0]	INT: mux CELL.IMUX_IO_OK[0] bit 6	INT: mux CELL.IMUX_IO_OK[0] bit 5	INT: mux CELL.IMUX_IO_OK[0] bit 4	INT: mux CELL.IMUX_IO_OK[0] bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 1	INT: mux CELL.IMUX_IO_OK[0] bit 3	INT: mux CELL.IMUX_IO_OK[0] bit 2	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0]	INT: mux CELL.IMUX_IO_IK[0] bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 1	INT: mux CELL.IMUX_IO_IK[0] bit 3	INT: mux CELL.IMUX_IO_IK[0] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 5	INT: mux CELL.IMUX_IO_IK[1] bit 6	INT: mux CELL.IMUX_IO_IK[1] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 3	INT: mux CELL.IMUX_IO_OK[1] bit 5	INT: mux CELL.IMUX_IO_OK[1] bit 6	INT: mux CELL.IMUX_IO_OK[1] bit 4	INT: mux CELL.IMUX_IO_OK[1] bit 3	INT: mux CELL.LONG_V[5] bit 0	INT: mux CELL.LONG_V[5] bit 2	INT: mux CELL.LONG_V[3] bit 1	INT: mux CELL.LONG_V[3] bit 2	-	INT: mux CELL.LONG_IO_H[0] bit 1	-	INT: mux CELL.LONG_V[4] bit 1	INT: mux CELL.LONG_V[4] bit 2	-

xc4000h IO_N0 rect MAIN_S
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	-	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1]	-	-	-	INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2]	-	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0]	-	INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

xc4000h IO_N0 rect MAIN_E
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

xc4000h IO_N0 rect MAIN_W
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile IO_N0_E

Cells: 3

Switchbox INT

xc4000h IO_N0_E switchbox INT programmable buffers
Destination	Source	Bit
CELL.LONG_H[0]	CELL.SINGLE_V[1]	!MAIN_S[21][8]
CELL.LONG_H[1]	CELL.SINGLE_V[2]	!MAIN_S[25][8]
CELL.LONG_H[2]	CELL.SINGLE_V[3]	!MAIN[24][1]

xc4000h IO_N0_E switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_V[0]	CELL.DEC_H[0]	!MAIN[19][2]
CELL.SINGLE_V[0]	CELL.OUT_IO_SN_I2_E1	!MAIN[22][1]
CELL.SINGLE_V[1]	CELL.LONG_H[0]	!MAIN_S[23][8]
CELL.SINGLE_V[1]	CELL.LONG_IO_H[0]	!MAIN[15][2]
CELL.SINGLE_V[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[22][0]
CELL.SINGLE_V[2]	CELL.LONG_H[1]	!MAIN_S[29][8]
CELL.SINGLE_V[2]	CELL.LONG_IO_H[1]	!MAIN[17][2]
CELL.SINGLE_V[2]	CELL.OUT_IO_SN_I1[0]	!MAIN[25][2]
CELL.SINGLE_V[3]	CELL.LONG_H[2]	!MAIN_S[28][9]
CELL.SINGLE_V[3]	CELL.DEC_H[1]	!MAIN[30][2]
CELL.SINGLE_V[3]	CELL.OUT_IO_SN_I1_E1	!MAIN[29][2]
CELL.SINGLE_V[4]	CELL.DEC_H[2]	!MAIN[35][2]
CELL.SINGLE_V[4]	CELL.OUT_IO_SN_I2_E1	!MAIN[35][0]
CELL.SINGLE_V[5]	CELL.LONG_IO_H[2]	!MAIN[33][2]
CELL.SINGLE_V[5]	CELL.OUT_IO_SN_I2[0]	!MAIN[32][0]
CELL.SINGLE_V[6]	CELL.LONG_IO_H[3]	!MAIN[34][2]
CELL.SINGLE_V[6]	CELL.OUT_IO_SN_I1[0]	!MAIN[25][1]
CELL.SINGLE_V[7]	CELL.DEC_H[3]	!MAIN[31][2]
CELL.SINGLE_V[7]	CELL.OUT_IO_SN_I1_E1	!MAIN[32][2]
CELL.DOUBLE_V0[0]	CELL.OUT_IO_SN_I1_E1	!MAIN[21][3]
CELL.DOUBLE_V0[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[30][0]
CELL.DOUBLE_V1[0]	CELL.OUT_IO_SN_I1[0]	!MAIN[20][3]
CELL.DOUBLE_V1[1]	CELL.OUT_IO_SN_I2_E1	!MAIN[31][0]
CELL.DOUBLE_IO_N0[0]	CELL.DBUF_IO_H[0]	!MAIN[35][4]
CELL.DOUBLE_IO_N0[1]	CELL.DBUF_IO_H[0]	!MAIN[34][4]
CELL.DOUBLE_IO_N0[2]	CELL.DBUF_IO_H[0]	!MAIN[34][5]
CELL.DOUBLE_IO_N0[3]	CELL.DBUF_IO_H[0]	!MAIN[35][5]
CELL.DOUBLE_IO_N2[0]	CELL.DBUF_IO_H[1]	!MAIN[10][4]
CELL.DOUBLE_IO_N2[1]	CELL.DBUF_IO_H[1]	!MAIN[9][4]
CELL.DOUBLE_IO_N2[2]	CELL.DBUF_IO_H[1]	!MAIN[9][5]
CELL.DOUBLE_IO_N2[3]	CELL.DBUF_IO_H[1]	!MAIN[10][5]

xc4000h IO_N0_E switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_V[0]	CELL.DOUBLE_IO_N0[0]	!MAIN[24][4]
CELL.SINGLE_V[0]	CELL.DOUBLE_IO_N2[0]	!MAIN[22][4]
CELL.SINGLE_V[1]	CELL.DOUBLE_IO_N1[0]	!MAIN[19][4]
CELL.SINGLE_V[2]	CELL.DOUBLE_IO_N0[1]	!MAIN[26][5]
CELL.SINGLE_V[2]	CELL.DOUBLE_IO_N2[1]	!MAIN[27][4]
CELL.SINGLE_V[3]	CELL.DOUBLE_IO_N1[1]	!MAIN[25][3]
CELL.SINGLE_V[4]	CELL.DOUBLE_IO_N0[2]	!MAIN[29][5]
CELL.SINGLE_V[4]	CELL.DOUBLE_IO_N2[2]	!MAIN[30][4]
CELL.SINGLE_V[5]	CELL.DOUBLE_IO_N1[2]	!MAIN[28][4]
CELL.SINGLE_V[6]	CELL.DOUBLE_IO_N0[3]	!MAIN[32][4]
CELL.SINGLE_V[6]	CELL.DOUBLE_IO_N2[3]	!MAIN[32][5]
CELL.SINGLE_V[7]	CELL.DOUBLE_IO_N1[3]	!MAIN[31][3]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_N0[1]	!MAIN[27][5]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_N1[1]	!MAIN[24][3]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_N2[1]	!MAIN[26][4]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_N0[2]	!MAIN[30][5]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_N1[2]	!MAIN[29][4]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_N2[2]	!MAIN[28][5]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_N0[0]	!MAIN[25][4]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_N1[0]	!MAIN[20][4]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_N2[0]	!MAIN[21][4]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_N0[3]	!MAIN[33][4]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_N1[3]	!MAIN[31][5]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_N2[3]	!MAIN[31][4]
CELL.DOUBLE_IO_N0[0]	CELL.DOUBLE_IO_N2[0]	!MAIN[23][4]
CELL.DOUBLE_IO_N0[1]	CELL.DOUBLE_IO_N2[1]	!MAIN[25][5]
CELL.DOUBLE_IO_N0[2]	CELL.DOUBLE_IO_N2[2]	!MAIN[30][3]
CELL.DOUBLE_IO_N0[3]	CELL.DOUBLE_IO_N2[3]	!MAIN[32][3]

xc4000h IO_N0_E switchbox INT muxes DBUF_IO_H[0]
Bits				Destination
MAIN[7][4]	MAIN[8][4]	MAIN[7][5]	MAIN[8][5]	CELL.DBUF_IO_H[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_N2[0]
0	1	0	1	CELL.DOUBLE_IO_N2[2]
0	1	1	0	CELL.DOUBLE_IO_N2[3]
1	1	1	1	CELL.DOUBLE_IO_N2[1]

xc4000h IO_N0_E switchbox INT muxes DBUF_IO_H[1]
Bits				Destination
MAIN[33][3]	MAIN[34][3]	MAIN[35][3]	MAIN[33][5]	CELL.DBUF_IO_H[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_N0[1]
0	1	0	1	CELL.DOUBLE_IO_N0[2]
0	1	1	0	CELL.DOUBLE_IO_N0[3]
1	1	1	1	CELL.DOUBLE_IO_N0[0]

xc4000h IO_N0_E switchbox INT muxes LONG_V[0]
Bits				Destination
MAIN[26][1]	MAIN[27][1]	MAIN[29][1]	MAIN[28][1]	CELL.LONG_V[0]
				Source
0	0	0	1	CELL.LONG_IO_H[0]
0	0	1	0	CELL.DEC_H[3]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_N0_E switchbox INT muxes LONG_V[1]
Bits				Destination
MAIN[35][1]	MAIN[33][1]	MAIN[34][0]	MAIN[34][1]	CELL.LONG_V[1]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_N0_E switchbox INT muxes LONG_V[2]
Bits				Destination
MAIN[31][1]	MAIN[30][1]	MAIN[32][1]	MAIN[33][0]	CELL.LONG_V[2]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_N0_E switchbox INT muxes LONG_V[3]
Bits				Destination
MAIN[6][1]	MAIN[6][0]	MAIN[7][0]	MAIN[7][1]	CELL.LONG_V[3]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_N0_E switchbox INT muxes LONG_V[4]
Bits				Destination
MAIN[5][1]	MAIN[1][0]	MAIN[2][0]	MAIN[2][1]	CELL.LONG_V[4]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_N0_E switchbox INT muxes LONG_V[5]
Bits				Destination
MAIN[8][1]	MAIN[8][0]	MAIN[9][1]	MAIN[9][0]	CELL.LONG_V[5]
				Source
0	0	0	1	CELL.LONG_IO_H[3]
0	0	1	0	CELL.DEC_H[0]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_N0_E switchbox INT muxes LONG_IO_H[0]
Bits		Destination
MAIN[4][0]	MAIN[16][2]	CELL.LONG_IO_H[0]
		Source
0	0	CELL.LONG_V[0]
0	1	CELL.SINGLE_V[1]
1	1	off

xc4000h IO_N0_E switchbox INT muxes LONG_IO_H[1]
Bits				Destination
MAIN[23][3]	MAIN[15][3]	MAIN[18][2]	MAIN[16][3]	CELL.LONG_IO_H[1]
				Source
0	0	0	1	CELL.LONG_V[1]
0	0	1	0	CELL.LONG_V[3]
0	1	1	1	CELL.SINGLE_V[2]
1	1	1	1	off

xc4000h IO_N0_E switchbox INT muxes LONG_IO_H[2]
Bits				Destination
MAIN[22][3]	MAIN[20][2]	MAIN[21][2]	MAIN[22][2]	CELL.LONG_IO_H[2]
				Source
0	0	0	1	CELL.LONG_V[2]
0	0	1	0	CELL.LONG_V[4]
0	1	1	1	CELL.SINGLE_V[5]
1	1	1	1	off

xc4000h IO_N0_E switchbox INT muxes LONG_IO_H[3]
Bits		Destination
MAIN[4][1]	MAIN[23][2]	CELL.LONG_IO_H[3]
		Source
0	0	CELL.LONG_V[5]
0	1	CELL.SINGLE_V[6]
1	1	off

xc4000h IO_N0_E switchbox INT muxes IMUX_IO_O1[0]
Bits						Destination
MAIN[26][2]	MAIN[26][3]	MAIN[28][2]	MAIN[27][3]	MAIN[28][3]	MAIN[27][2]	CELL.IMUX_IO_O1[0]
						Source
0	0	0	1	1	1	CELL.DEC_H[1]
0	0	1	1	1	1	CELL.DOUBLE_V0[0]
0	1	0	0	1	1	CELL.DEC_H[3]
0	1	0	1	0	1	CELL.DEC_H[0]
0	1	0	1	1	0	CELL.LONG_V[5]
0	1	1	0	1	1	CELL.LONG_V[3]
0	1	1	1	0	1	CELL.LONG_V[4]
0	1	1	1	1	0	CELL.DEC_H[2]
1	1	0	1	1	1	CELL.DOUBLE_V1[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_N0_E switchbox INT muxes IMUX_IO_O1[1]
Bits						Destination
MAIN[0][2]	MAIN[2][2]	MAIN[1][3]	MAIN[1][2]	MAIN[2][3]	MAIN[0][3]	CELL.IMUX_IO_O1[1]
						Source
0	0	0	1	1	1	CELL.DEC_H[0]
0	0	1	0	1	1	CELL.DEC_H[1]
0	0	1	1	0	1	CELL.DEC_H[3]
0	0	1	1	1	0	CELL_E.LONG_V[2]
0	1	0	1	1	1	CELL_E.LONG_V[0]
0	1	1	0	1	1	CELL.DEC_H[2]
0	1	1	1	0	1	CELL_E.LONG_V[1]
0	1	1	1	1	0	CELL_E.DOUBLE_V1[0]
1	0	1	1	1	1	CELL_E.DOUBLE_V0[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_N0_E switchbox INT muxes IMUX_IO_OK[0]
Bits								Destination
MAIN[23][1]	MAIN[29][0]	MAIN[28][0]	MAIN[27][0]	MAIN[24][0]	MAIN[23][0]	MAIN[25][0]	MAIN[26][0]	CELL.IMUX_IO_OK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_V[3]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[2]

xc4000h IO_N0_E switchbox INT muxes IMUX_IO_OK[1]
Bits								Destination
MAIN[10][1]	MAIN[12][0]	MAIN[13][0]	MAIN[11][0]	MAIN[10][0]	MAIN[13][1]	MAIN[12][1]	MAIN[11][1]	CELL.IMUX_IO_OK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_E.SINGLE_V[2]
0	1	1	1	1	1	0	1	CELL_E.SINGLE_V[3]
0	1	1	1	1	1	1	0	CELL_E.SINGLE_V[5]
1	1	1	1	1	1	1	1	CELL_E.SINGLE_V[4]

xc4000h IO_N0_E switchbox INT muxes IMUX_IO_IK[0]
Bits								Destination
MAIN[18][1]	MAIN[19][1]	MAIN[20][1]	MAIN[21][1]	MAIN[19][0]	MAIN[18][0]	MAIN[20][0]	MAIN[21][0]	CELL.IMUX_IO_IK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_V[2]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[3]

xc4000h IO_N0_E switchbox INT muxes IMUX_IO_IK[1]
Bits								Destination
MAIN[14][1]	MAIN[16][0]	MAIN[17][0]	MAIN[15][0]	MAIN[14][0]	MAIN[17][1]	MAIN[16][1]	MAIN[15][1]	CELL.IMUX_IO_IK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_E.SINGLE_V[2]
0	1	1	1	1	1	0	1	CELL_E.SINGLE_V[3]
0	1	1	1	1	1	1	0	CELL_E.SINGLE_V[4]
1	1	1	1	1	1	1	1	CELL_E.SINGLE_V[5]

xc4000h IO_N0_E switchbox INT muxes IMUX_IO_T[0]
Bits								Destination
MAIN[5][4]	MAIN[3][4]	MAIN[6][6]	MAIN[6][4]	MAIN[4][4]	MAIN[6][5]	MAIN[5][5]	MAIN[4][5]	CELL.IMUX_IO_T[0]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	0	1	1	1	CELL.LONG_IO_H[3]
0	0	1	0	1	1	0	1	CELL.LONG_IO_H[0]
0	0	1	0	1	1	1	0	CELL.LONG_IO_H[2]
0	0	1	1	1	0	0	1	CELL.DEC_H[2]
0	0	1	1	1	0	1	0	CELL.GCLK[0]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_N1[0]
0	1	1	1	1	0	1	1	CELL.DOUBLE_IO_N2[1]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_N1[1]
1	0	1	1	1	1	0	1	CELL.LONG_IO_H[1]
1	0	1	1	1	1	1	0	CELL.DEC_H[3]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_N2[0]

xc4000h IO_N0_E switchbox INT muxes IMUX_IO_T[1]
Bits								Destination
MAIN[1][4]	MAIN[0][5]	MAIN[11][4]	MAIN[3][5]	MAIN[2][5]	MAIN[2][4]	MAIN[1][5]	MAIN[0][4]	CELL.IMUX_IO_T[1]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	0	1	1	1	CELL.GCLK[0]
0	0	1	0	1	1	0	1	CELL.DEC_H[3]
0	0	1	1	0	0	1	1	CELL.LONG_IO_H[0]
0	0	1	1	1	0	0	1	CELL.LONG_IO_H[3]
0	0	1	1	1	0	1	0	CELL.LONG_IO_H[2]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_N1[1]
0	1	1	1	1	0	1	1	CELL.DOUBLE_IO_N2[1]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_N2[0]
1	0	1	1	1	1	0	1	CELL.LONG_IO_H[1]
1	0	1	1	1	1	1	0	CELL.DEC_H[2]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_N1[0]

xc4000h IO_N0_E switchbox INT muxes IMUX_HIO_O[0]
Bits	Destination
MAIN[26][6]	CELL.IMUX_HIO_O[0]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_F2_N

xc4000h IO_N0_E switchbox INT muxes IMUX_HIO_O[1]
Bits	Destination
MAIN[21][6]	CELL.IMUX_HIO_O[1]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_F2_N

xc4000h IO_N0_E switchbox INT muxes IMUX_HIO_O[2]
Bits	Destination
MAIN[12][6]	CELL.IMUX_HIO_O[2]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_G2_N

xc4000h IO_N0_E switchbox INT muxes IMUX_HIO_O[3]
Bits	Destination
MAIN[8][6]	CELL.IMUX_HIO_O[3]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_G2_N

xc4000h IO_N0_E switchbox INT muxes IMUX_HIO_T[0]
Bits	Destination
MAIN[28][6]	CELL.IMUX_HIO_T[0]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_OK[0]

xc4000h IO_N0_E switchbox INT muxes IMUX_HIO_T[1]
Bits	Destination
MAIN[21][5]	CELL.IMUX_HIO_T[1]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_IK[0]

xc4000h IO_N0_E switchbox INT muxes IMUX_HIO_T[2]
Bits	Destination
MAIN[14][6]	CELL.IMUX_HIO_T[2]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_IK[1]

xc4000h IO_N0_E switchbox INT muxes IMUX_HIO_T[3]
Bits	Destination
MAIN[5][6]	CELL.IMUX_HIO_T[3]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_OK[1]

xc4000h IO_N0_E switchbox INT muxes OUT_IO_SN_I1[0]
Bits	Destination
MAIN[20][5]	CELL.OUT_IO_SN_I1[0]
	Source
0	CELL.OUT_HIO_I[1]
1	CELL.OUT_HIO_I[0]

xc4000h IO_N0_E switchbox INT muxes OUT_IO_SN_I1[1]
Bits	Destination
MAIN[15][6]	CELL.OUT_IO_SN_I1[1]
	Source
0	CELL.OUT_HIO_I[2]
1	CELL.OUT_HIO_I[3]

xc4000h IO_N0_E switchbox INT muxes OUT_IO_SN_I2[0]
Bits	Destination
MAIN[31][6]	CELL.OUT_IO_SN_I2[0]
	Source
0	CELL.OUT_HIO_I[0]
1	CELL.OUT_HIO_I[1]

xc4000h IO_N0_E switchbox INT muxes OUT_IO_SN_I2[1]
Bits	Destination
MAIN[3][6]	CELL.OUT_IO_SN_I2[1]
	Source
0	CELL.OUT_HIO_I[3]
1	CELL.OUT_HIO_I[2]

Bels HIO

xc4000h IO_N0_E bel HIO pins
Pin	Direction	HIO[0]	HIO[1]	HIO[2]	HIO[3]
O	in	CELL.IMUX_HIO_O[0] invert by !MAIN[27][6]	CELL.IMUX_HIO_O[1] invert by !MAIN[22][6]	CELL.IMUX_HIO_O[2] invert by !MAIN[13][6]	CELL.IMUX_HIO_O[3] invert by !MAIN[7][6]
T	in	CELL.IMUX_HIO_T[0] invert by !MAIN[29][6]	CELL.IMUX_HIO_T[1] invert by !MAIN[20][6]	CELL.IMUX_HIO_T[2] invert by !MAIN[14][5]	CELL.IMUX_HIO_T[3] invert by !MAIN[4][6]
I	out	CELL.OUT_HIO_I[0]	CELL.OUT_HIO_I[1]	CELL.OUT_HIO_I[2]	CELL.OUT_HIO_I[3]
CLKIN	out	-	-	CELL.OUT_IO_CLKIN	-

xc4000h IO_N0_E bel HIO attribute bits
Attribute	HIO[0]	HIO[1]	HIO[2]	HIO[3]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
ISTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OSTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OMODE	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]
I_INV	!MAIN[32][6]	!MAIN[19][6]	!MAIN[16][6]	!MAIN[2][6]
READBACK_I bit 0	!MAIN[18][4]	!MAIN[18][3]	!MAIN[16][4]	!MAIN[17][3]

xc4000h IO_N0_E enum IO_PULL
HIO[0].PULL	MAIN[24][6]	MAIN[25][6]
HIO[1].PULL	MAIN[24][5]	MAIN[22][5]
HIO[2].PULL	MAIN[11][5]	MAIN[13][5]
HIO[3].PULL	MAIN[10][6]	MAIN[9][6]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

xc4000h IO_N0_E enum IO_STD
HIO[0].ISTD	MAIN[33][6]
HIO[1].ISTD	MAIN[18][6]
HIO[2].ISTD	MAIN[15][5]
HIO[3].ISTD	MAIN[1][6]
CMOS	0
TTL	1

xc4000h IO_N0_E enum IO_STD
HIO[0].OSTD	MAIN[34][6]
HIO[1].OSTD	MAIN[18][5]
HIO[2].OSTD	MAIN[16][5]
HIO[3].OSTD	MAIN[0][6]
CMOS	1
TTL	0

xc4000h IO_N0_E enum HIO_OMODE
HIO[0].OMODE	MAIN[23][6]
HIO[1].OMODE	MAIN[23][5]
HIO[2].OMODE	MAIN[12][5]
HIO[3].OMODE	MAIN[11][6]
CAP	1
RES	0

Bels DEC

xc4000h IO_N0_E bel DEC pins
Pin	Direction	DEC[0]	DEC[1]	DEC[2]
I	in	CELL.OUT_IO_SN_I1[0]	CELL.IMUX_CLB_C2_N	CELL.OUT_IO_SN_I1[1]
O1	bidir	CELL.DEC_H[0]	CELL.DEC_H[0]	CELL.DEC_H[0]
O2	bidir	CELL.DEC_H[1]	CELL.DEC_H[1]	CELL.DEC_H[1]
O3	bidir	CELL.DEC_H[2]	CELL.DEC_H[2]	CELL.DEC_H[2]
O4	bidir	CELL.DEC_H[3]	CELL.DEC_H[3]	CELL.DEC_H[3]

xc4000h IO_N0_E bel DEC attribute bits
Attribute	DEC[0]	DEC[1]	DEC[2]
O1_P	!MAIN[8][3]	!MAIN[6][2]	MAIN[7][3]
O1_N	MAIN[8][2]	MAIN[6][3]	!MAIN[7][2]
O2_P	!MAIN[3][3]	!MAIN[5][2]	MAIN[4][3]
O2_N	MAIN[3][2]	MAIN[5][3]	!MAIN[4][2]
O3_P	!MAIN[9][3]	!MAIN[11][2]	MAIN[10][3]
O3_N	MAIN[9][2]	MAIN[11][3]	!MAIN[10][2]
O4_P	!MAIN[14][3]	!MAIN[12][2]	MAIN[13][3]
O4_N	MAIN[14][2]	MAIN[12][3]	!MAIN[13][2]

Bel wires

xc4000h IO_N0_E bel wires
Wire	Pins
CELL.DEC_H[0]	DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_H[1]	DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.DEC_H[2]	DEC[0].O3, DEC[1].O3, DEC[2].O3
CELL.DEC_H[3]	DEC[0].O4, DEC[1].O4, DEC[2].O4
CELL.IMUX_CLB_C2_N	DEC[1].I
CELL.IMUX_HIO_O[0]	HIO[0].O
CELL.IMUX_HIO_O[1]	HIO[1].O
CELL.IMUX_HIO_O[2]	HIO[2].O
CELL.IMUX_HIO_O[3]	HIO[3].O
CELL.IMUX_HIO_T[0]	HIO[0].T
CELL.IMUX_HIO_T[1]	HIO[1].T
CELL.IMUX_HIO_T[2]	HIO[2].T
CELL.IMUX_HIO_T[3]	HIO[3].T
CELL.OUT_IO_SN_I1[0]	DEC[0].I
CELL.OUT_IO_SN_I1[1]	DEC[2].I
CELL.OUT_HIO_I[0]	HIO[0].I
CELL.OUT_HIO_I[1]	HIO[1].I
CELL.OUT_HIO_I[2]	HIO[2].I
CELL.OUT_HIO_I[3]	HIO[3].I
CELL.OUT_IO_CLKIN	HIO[2].CLKIN

Bitstream

xc4000h IO_N0_E rect MAIN
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B6	-	HIO[0]: OSTD bit 0	HIO[0]: ISTD bit 0	HIO[0]: ! I_INV	INT: mux CELL.OUT_IO_SN_I2[0] bit 0	-	HIO[0]: !invert T	INT: mux CELL.IMUX_HIO_T[0] bit 0	HIO[0]: !invert O	INT: mux CELL.IMUX_HIO_O[0] bit 0	HIO[0]: PULL bit 0	HIO[0]: PULL bit 1	HIO[0]: OMODE bit 0	HIO[1]: !invert O	INT: mux CELL.IMUX_HIO_O[1] bit 0	HIO[1]: !invert T	HIO[1]: ! I_INV	HIO[1]: ISTD bit 0	-	HIO[2]: ! I_INV	INT: mux CELL.OUT_IO_SN_I1[1] bit 0	INT: mux CELL.IMUX_HIO_T[2] bit 0	HIO[2]: !invert O	INT: mux CELL.IMUX_HIO_O[2] bit 0	HIO[3]: OMODE bit 0	HIO[3]: PULL bit 1	HIO[3]: PULL bit 0	INT: mux CELL.IMUX_HIO_O[3] bit 0	HIO[3]: !invert O	INT: mux CELL.IMUX_IO_T[0] bit 5	INT: mux CELL.IMUX_HIO_T[3] bit 0	HIO[3]: !invert T	INT: mux CELL.OUT_IO_SN_I2[1] bit 0	HIO[3]: ! I_INV	HIO[3]: ISTD bit 0	HIO[3]: OSTD bit 0
B5	INT: !pass CELL.DOUBLE_IO_N0[3] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_N0[2] ← CELL.DBUF_IO_H[0]	INT: mux CELL.DBUF_IO_H[1] bit 0	INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_N2[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N1[3]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N0[2]	INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_N0[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N2[2]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N0[1]	INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N0[1]	INT: !bipass CELL.DOUBLE_IO_N0[1] = CELL.DOUBLE_IO_N2[1]	HIO[1]: PULL bit 1	HIO[1]: OMODE bit 0	HIO[1]: PULL bit 0	INT: mux CELL.IMUX_HIO_T[1] bit 0	INT: mux CELL.OUT_IO_SN_I1[0] bit 0	-	HIO[1]: OSTD bit 0	-	HIO[2]: OSTD bit 0	HIO[2]: ISTD bit 0	HIO[2]: !invert T	HIO[2]: PULL bit 0	HIO[2]: OMODE bit 0	HIO[2]: PULL bit 1	INT: !pass CELL.DOUBLE_IO_N2[3] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_N2[2] ← CELL.DBUF_IO_H[1]	INT: mux CELL.DBUF_IO_H[0] bit 0	INT: mux CELL.DBUF_IO_H[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 2	INT: mux CELL.IMUX_IO_T[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 0	INT: mux CELL.IMUX_IO_T[1] bit 4	INT: mux CELL.IMUX_IO_T[1] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 1	INT: mux CELL.IMUX_IO_T[1] bit 6
B4	INT: !pass CELL.DOUBLE_IO_N0[0] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_N0[1] ← CELL.DBUF_IO_H[0]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N0[3]	INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_N0[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N2[3]	INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_N2[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N1[2]	INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_N1[2]	INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N2[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N2[1]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N0[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N0[0]	INT: !bipass CELL.DOUBLE_IO_N0[0] = CELL.DOUBLE_IO_N2[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N2[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N2[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N1[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N1[0]	HIO[0]: ! READBACK_I bit 0	-	HIO[2]: ! READBACK_I bit 0	-	-	-	-	INT: mux CELL.IMUX_IO_T[1] bit 5	INT: !pass CELL.DOUBLE_IO_N2[0] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_N2[1] ← CELL.DBUF_IO_H[1]	INT: mux CELL.DBUF_IO_H[0] bit 2	INT: mux CELL.DBUF_IO_H[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 4	INT: mux CELL.IMUX_IO_T[0] bit 7	INT: mux CELL.IMUX_IO_T[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 6	INT: mux CELL.IMUX_IO_T[1] bit 2	INT: mux CELL.IMUX_IO_T[1] bit 7	INT: mux CELL.IMUX_IO_T[1] bit 0
B3	INT: mux CELL.DBUF_IO_H[1] bit 1	INT: mux CELL.DBUF_IO_H[1] bit 2	INT: mux CELL.DBUF_IO_H[1] bit 3	INT: !bipass CELL.DOUBLE_IO_N0[3] = CELL.DOUBLE_IO_N2[3]	INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_N1[3]	INT: !bipass CELL.DOUBLE_IO_N0[2] = CELL.DOUBLE_IO_N2[2]	-	INT: mux CELL.IMUX_IO_O1[0] bit 1	INT: mux CELL.IMUX_IO_O1[0] bit 2	INT: mux CELL.IMUX_IO_O1[0] bit 4	INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N1[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N1[1]	INT: mux CELL.LONG_IO_H[1] bit 3	INT: mux CELL.LONG_IO_H[2] bit 3	INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0]	-	HIO[1]: ! READBACK_I bit 0	HIO[3]: ! READBACK_I bit 0	INT: mux CELL.LONG_IO_H[1] bit 0	INT: mux CELL.LONG_IO_H[1] bit 2	DEC[0]: ! O4_P	DEC[2]: O4_P	DEC[1]: O4_N	DEC[1]: O3_N	DEC[2]: O3_P	DEC[0]: ! O3_P	DEC[0]: ! O1_P	DEC[2]: O1_P	DEC[1]: O1_N	DEC[1]: O2_N	DEC[2]: O2_P	DEC[0]: ! O2_P	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 0
B2	INT: !pass CELL.SINGLE_V[4] ← CELL.DEC_H[2]	INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_IO_H[3]	INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_IO_H[2]	INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.SINGLE_V[7] ← CELL.DEC_H[3]	INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[1]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1	INT: mux CELL.IMUX_IO_O1[0] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 5	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0]	-	INT: mux CELL.LONG_IO_H[3] bit 0	INT: mux CELL.LONG_IO_H[2] bit 0	INT: mux CELL.LONG_IO_H[2] bit 1	INT: mux CELL.LONG_IO_H[2] bit 2	INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[0]	INT: mux CELL.LONG_IO_H[1] bit 1	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[1]	INT: mux CELL.LONG_IO_H[0] bit 0	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[0]	DEC[0]: O4_N	DEC[2]: ! O4_N	DEC[1]: ! O4_P	DEC[1]: ! O3_P	DEC[2]: ! O3_N	DEC[0]: O3_N	DEC[0]: O1_N	DEC[2]: ! O1_N	DEC[1]: ! O1_P	DEC[1]: ! O2_P	DEC[2]: ! O2_N	DEC[0]: O2_N	INT: mux CELL.IMUX_IO_O1[1] bit 4	INT: mux CELL.IMUX_IO_O1[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 5
B1	INT: mux CELL.LONG_V[1] bit 3	INT: mux CELL.LONG_V[1] bit 0	INT: mux CELL.LONG_V[1] bit 2	INT: mux CELL.LONG_V[2] bit 1	INT: mux CELL.LONG_V[2] bit 3	INT: mux CELL.LONG_V[2] bit 2	INT: mux CELL.LONG_V[0] bit 1	INT: mux CELL.LONG_V[0] bit 0	INT: mux CELL.LONG_V[0] bit 2	INT: mux CELL.LONG_V[0] bit 3	INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_IO_SN_I1[0]	INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[3]	INT: mux CELL.IMUX_IO_OK[0] bit 7	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.IMUX_IO_IK[0] bit 4	INT: mux CELL.IMUX_IO_IK[0] bit 5	INT: mux CELL.IMUX_IO_IK[0] bit 6	INT: mux CELL.IMUX_IO_IK[0] bit 7	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 0	INT: mux CELL.IMUX_IO_IK[1] bit 7	INT: mux CELL.IMUX_IO_OK[1] bit 2	INT: mux CELL.IMUX_IO_OK[1] bit 1	INT: mux CELL.IMUX_IO_OK[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 7	INT: mux CELL.LONG_V[5] bit 1	INT: mux CELL.LONG_V[5] bit 3	INT: mux CELL.LONG_V[3] bit 0	INT: mux CELL.LONG_V[3] bit 3	INT: mux CELL.LONG_V[4] bit 3	INT: mux CELL.LONG_IO_H[3] bit 1	-	INT: mux CELL.LONG_V[4] bit 0	-	-
B0	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.LONG_V[1] bit 1	INT: mux CELL.LONG_V[2] bit 0	INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1	INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0]	INT: mux CELL.IMUX_IO_OK[0] bit 6	INT: mux CELL.IMUX_IO_OK[0] bit 5	INT: mux CELL.IMUX_IO_OK[0] bit 4	INT: mux CELL.IMUX_IO_OK[0] bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 1	INT: mux CELL.IMUX_IO_OK[0] bit 3	INT: mux CELL.IMUX_IO_OK[0] bit 2	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0]	INT: mux CELL.IMUX_IO_IK[0] bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 1	INT: mux CELL.IMUX_IO_IK[0] bit 3	INT: mux CELL.IMUX_IO_IK[0] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 5	INT: mux CELL.IMUX_IO_IK[1] bit 6	INT: mux CELL.IMUX_IO_IK[1] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 3	INT: mux CELL.IMUX_IO_OK[1] bit 5	INT: mux CELL.IMUX_IO_OK[1] bit 6	INT: mux CELL.IMUX_IO_OK[1] bit 4	INT: mux CELL.IMUX_IO_OK[1] bit 3	INT: mux CELL.LONG_V[5] bit 0	INT: mux CELL.LONG_V[5] bit 2	INT: mux CELL.LONG_V[3] bit 1	INT: mux CELL.LONG_V[3] bit 2	-	INT: mux CELL.LONG_IO_H[0] bit 1	-	INT: mux CELL.LONG_V[4] bit 1	INT: mux CELL.LONG_V[4] bit 2	-

xc4000h IO_N0_E rect MAIN_S
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	-	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1]	-	-	-	INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2]	-	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0]	-	INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

xc4000h IO_N0_E rect MAIN_E
Bit	Frame
Bit	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

xc4000h IO_N0_E rect MAIN_W
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile IO_N1

Cells: 3

Switchbox INT

xc4000h IO_N1 switchbox INT programmable buffers
Destination	Source	Bit
CELL.LONG_H[0]	CELL.SINGLE_V[1]	!MAIN_S[21][8]
CELL.LONG_H[1]	CELL.SINGLE_V[2]	!MAIN_S[25][8]
CELL.LONG_H[2]	CELL.SINGLE_V[3]	!MAIN[24][1]

xc4000h IO_N1 switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_V[0]	CELL.DEC_H[0]	!MAIN[19][2]
CELL.SINGLE_V[0]	CELL.OUT_IO_SN_I2_E1	!MAIN[22][1]
CELL.SINGLE_V[1]	CELL.LONG_H[0]	!MAIN_S[23][8]
CELL.SINGLE_V[1]	CELL.LONG_IO_H[0]	!MAIN[15][2]
CELL.SINGLE_V[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[22][0]
CELL.SINGLE_V[2]	CELL.LONG_H[1]	!MAIN_S[29][8]
CELL.SINGLE_V[2]	CELL.LONG_IO_H[1]	!MAIN[17][2]
CELL.SINGLE_V[2]	CELL.OUT_IO_SN_I1[0]	!MAIN[25][2]
CELL.SINGLE_V[3]	CELL.LONG_H[2]	!MAIN_S[28][9]
CELL.SINGLE_V[3]	CELL.DEC_H[1]	!MAIN[30][2]
CELL.SINGLE_V[3]	CELL.OUT_IO_SN_I1_E1	!MAIN[29][2]
CELL.SINGLE_V[4]	CELL.DEC_H[2]	!MAIN[35][2]
CELL.SINGLE_V[4]	CELL.OUT_IO_SN_I2_E1	!MAIN[35][0]
CELL.SINGLE_V[5]	CELL.LONG_IO_H[2]	!MAIN[33][2]
CELL.SINGLE_V[5]	CELL.OUT_IO_SN_I2[0]	!MAIN[32][0]
CELL.SINGLE_V[6]	CELL.LONG_IO_H[3]	!MAIN[34][2]
CELL.SINGLE_V[6]	CELL.OUT_IO_SN_I1[0]	!MAIN[25][1]
CELL.SINGLE_V[7]	CELL.DEC_H[3]	!MAIN[31][2]
CELL.SINGLE_V[7]	CELL.OUT_IO_SN_I1_E1	!MAIN[32][2]
CELL.DOUBLE_V0[0]	CELL.OUT_IO_SN_I1_E1	!MAIN[21][3]
CELL.DOUBLE_V0[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[30][0]
CELL.DOUBLE_V1[0]	CELL.OUT_IO_SN_I1[0]	!MAIN[20][3]
CELL.DOUBLE_V1[1]	CELL.OUT_IO_SN_I2_E1	!MAIN[31][0]
CELL.DOUBLE_IO_N0[0]	CELL.DBUF_IO_H[0]	!MAIN[35][4]
CELL.DOUBLE_IO_N0[1]	CELL.DBUF_IO_H[0]	!MAIN[34][4]
CELL.DOUBLE_IO_N0[2]	CELL.DBUF_IO_H[0]	!MAIN[34][5]
CELL.DOUBLE_IO_N0[3]	CELL.DBUF_IO_H[0]	!MAIN[35][5]
CELL.DOUBLE_IO_N2[0]	CELL.DBUF_IO_H[1]	!MAIN[10][4]
CELL.DOUBLE_IO_N2[1]	CELL.DBUF_IO_H[1]	!MAIN[9][4]
CELL.DOUBLE_IO_N2[2]	CELL.DBUF_IO_H[1]	!MAIN[9][5]
CELL.DOUBLE_IO_N2[3]	CELL.DBUF_IO_H[1]	!MAIN[10][5]

xc4000h IO_N1 switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_V[0]	CELL.DOUBLE_IO_N1[0]	!MAIN[19][4]
CELL.SINGLE_V[1]	CELL.DOUBLE_IO_N0[0]	!MAIN[24][4]
CELL.SINGLE_V[1]	CELL.DOUBLE_IO_N2[0]	!MAIN[22][4]
CELL.SINGLE_V[2]	CELL.DOUBLE_IO_N1[1]	!MAIN[25][3]
CELL.SINGLE_V[3]	CELL.DOUBLE_IO_N0[1]	!MAIN[26][5]
CELL.SINGLE_V[3]	CELL.DOUBLE_IO_N2[1]	!MAIN[27][4]
CELL.SINGLE_V[4]	CELL.DOUBLE_IO_N1[2]	!MAIN[28][4]
CELL.SINGLE_V[5]	CELL.DOUBLE_IO_N0[2]	!MAIN[29][5]
CELL.SINGLE_V[5]	CELL.DOUBLE_IO_N2[2]	!MAIN[30][4]
CELL.SINGLE_V[6]	CELL.DOUBLE_IO_N1[3]	!MAIN[31][3]
CELL.SINGLE_V[7]	CELL.DOUBLE_IO_N0[3]	!MAIN[32][4]
CELL.SINGLE_V[7]	CELL.DOUBLE_IO_N2[3]	!MAIN[32][5]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_N0[1]	!MAIN[27][5]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_N1[1]	!MAIN[24][3]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_N2[1]	!MAIN[26][4]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_N0[2]	!MAIN[30][5]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_N1[2]	!MAIN[29][4]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_N2[2]	!MAIN[28][5]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_N0[0]	!MAIN[25][4]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_N1[0]	!MAIN[20][4]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_N2[0]	!MAIN[21][4]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_N0[3]	!MAIN[33][4]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_N1[3]	!MAIN[31][5]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_N2[3]	!MAIN[31][4]
CELL.DOUBLE_IO_N0[0]	CELL.DOUBLE_IO_N2[0]	!MAIN[23][4]
CELL.DOUBLE_IO_N0[1]	CELL.DOUBLE_IO_N2[1]	!MAIN[25][5]
CELL.DOUBLE_IO_N0[2]	CELL.DOUBLE_IO_N2[2]	!MAIN[30][3]
CELL.DOUBLE_IO_N0[3]	CELL.DOUBLE_IO_N2[3]	!MAIN[32][3]

xc4000h IO_N1 switchbox INT muxes DBUF_IO_H[0]
Bits				Destination
MAIN[7][4]	MAIN[8][4]	MAIN[7][5]	MAIN[8][5]	CELL.DBUF_IO_H[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_N2[0]
0	1	0	1	CELL.DOUBLE_IO_N2[2]
0	1	1	0	CELL.DOUBLE_IO_N2[3]
1	1	1	1	CELL.DOUBLE_IO_N2[1]

xc4000h IO_N1 switchbox INT muxes DBUF_IO_H[1]
Bits				Destination
MAIN[33][3]	MAIN[34][3]	MAIN[35][3]	MAIN[33][5]	CELL.DBUF_IO_H[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_N0[1]
0	1	0	1	CELL.DOUBLE_IO_N0[2]
0	1	1	0	CELL.DOUBLE_IO_N0[3]
1	1	1	1	CELL.DOUBLE_IO_N0[0]

xc4000h IO_N1 switchbox INT muxes LONG_V[0]
Bits				Destination
MAIN[26][1]	MAIN[27][1]	MAIN[29][1]	MAIN[28][1]	CELL.LONG_V[0]
				Source
0	0	0	1	CELL.LONG_IO_H[0]
0	0	1	0	CELL.DEC_H[3]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_N1 switchbox INT muxes LONG_V[1]
Bits				Destination
MAIN[35][1]	MAIN[33][1]	MAIN[34][0]	MAIN[34][1]	CELL.LONG_V[1]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_N1 switchbox INT muxes LONG_V[2]
Bits				Destination
MAIN[31][1]	MAIN[30][1]	MAIN[32][1]	MAIN[33][0]	CELL.LONG_V[2]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_N1 switchbox INT muxes LONG_V[3]
Bits				Destination
MAIN[6][1]	MAIN[6][0]	MAIN[7][0]	MAIN[7][1]	CELL.LONG_V[3]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_N1 switchbox INT muxes LONG_V[4]
Bits				Destination
MAIN[5][1]	MAIN[1][0]	MAIN[2][0]	MAIN[2][1]	CELL.LONG_V[4]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_N1 switchbox INT muxes LONG_V[5]
Bits				Destination
MAIN[8][1]	MAIN[8][0]	MAIN[9][1]	MAIN[9][0]	CELL.LONG_V[5]
				Source
0	0	0	1	CELL.LONG_IO_H[3]
0	0	1	0	CELL.DEC_H[0]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_N1 switchbox INT muxes LONG_IO_H[0]
Bits		Destination
MAIN[4][0]	MAIN[16][2]	CELL.LONG_IO_H[0]
		Source
0	0	CELL.LONG_V[0]
0	1	CELL.SINGLE_V[1]
1	1	off

xc4000h IO_N1 switchbox INT muxes LONG_IO_H[1]
Bits				Destination
MAIN[23][3]	MAIN[15][3]	MAIN[18][2]	MAIN[16][3]	CELL.LONG_IO_H[1]
				Source
0	0	0	1	CELL.LONG_V[1]
0	0	1	0	CELL.LONG_V[3]
0	1	1	1	CELL.SINGLE_V[2]
1	1	1	1	off

xc4000h IO_N1 switchbox INT muxes LONG_IO_H[2]
Bits				Destination
MAIN[22][3]	MAIN[20][2]	MAIN[21][2]	MAIN[22][2]	CELL.LONG_IO_H[2]
				Source
0	0	0	1	CELL.LONG_V[2]
0	0	1	0	CELL.LONG_V[4]
0	1	1	1	CELL.SINGLE_V[5]
1	1	1	1	off

xc4000h IO_N1 switchbox INT muxes LONG_IO_H[3]
Bits		Destination
MAIN[4][1]	MAIN[23][2]	CELL.LONG_IO_H[3]
		Source
0	0	CELL.LONG_V[5]
0	1	CELL.SINGLE_V[6]
1	1	off

xc4000h IO_N1 switchbox INT muxes IMUX_IO_O1[0]
Bits						Destination
MAIN[26][2]	MAIN[26][3]	MAIN[28][2]	MAIN[27][3]	MAIN[28][3]	MAIN[27][2]	CELL.IMUX_IO_O1[0]
						Source
0	0	0	1	1	1	CELL.DEC_H[1]
0	0	1	1	1	1	CELL.DOUBLE_V0[0]
0	1	0	0	1	1	CELL.DEC_H[3]
0	1	0	1	0	1	CELL.DEC_H[0]
0	1	0	1	1	0	CELL.LONG_V[5]
0	1	1	0	1	1	CELL.LONG_V[3]
0	1	1	1	0	1	CELL.LONG_V[4]
0	1	1	1	1	0	CELL.DEC_H[2]
1	1	0	1	1	1	CELL.DOUBLE_V1[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_N1 switchbox INT muxes IMUX_IO_O1[1]
Bits						Destination
MAIN[0][2]	MAIN[2][2]	MAIN[1][3]	MAIN[1][2]	MAIN[2][3]	MAIN[0][3]	CELL.IMUX_IO_O1[1]
						Source
0	0	0	1	1	1	CELL.DEC_H[0]
0	0	1	0	1	1	CELL.DEC_H[1]
0	0	1	1	0	1	CELL.DEC_H[3]
0	0	1	1	1	0	CELL_E.LONG_V[2]
0	1	0	1	1	1	CELL_E.LONG_V[0]
0	1	1	0	1	1	CELL.DEC_H[2]
0	1	1	1	0	1	CELL_E.LONG_V[1]
0	1	1	1	1	0	CELL_E.DOUBLE_V1[0]
1	0	1	1	1	1	CELL_E.DOUBLE_V0[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_N1 switchbox INT muxes IMUX_IO_OK[0]
Bits								Destination
MAIN[23][1]	MAIN[29][0]	MAIN[28][0]	MAIN[27][0]	MAIN[24][0]	MAIN[23][0]	MAIN[25][0]	MAIN[26][0]	CELL.IMUX_IO_OK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_V[3]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[2]

xc4000h IO_N1 switchbox INT muxes IMUX_IO_OK[1]
Bits								Destination
MAIN[10][1]	MAIN[12][0]	MAIN[13][0]	MAIN[11][0]	MAIN[10][0]	MAIN[13][1]	MAIN[12][1]	MAIN[11][1]	CELL.IMUX_IO_OK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_E.SINGLE_V[2]
0	1	1	1	1	1	0	1	CELL_E.SINGLE_V[3]
0	1	1	1	1	1	1	0	CELL_E.SINGLE_V[5]
1	1	1	1	1	1	1	1	CELL_E.SINGLE_V[4]

xc4000h IO_N1 switchbox INT muxes IMUX_IO_IK[0]
Bits								Destination
MAIN[18][1]	MAIN[19][1]	MAIN[20][1]	MAIN[21][1]	MAIN[19][0]	MAIN[18][0]	MAIN[20][0]	MAIN[21][0]	CELL.IMUX_IO_IK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_V[2]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[3]

xc4000h IO_N1 switchbox INT muxes IMUX_IO_IK[1]
Bits								Destination
MAIN[14][1]	MAIN[16][0]	MAIN[17][0]	MAIN[15][0]	MAIN[14][0]	MAIN[17][1]	MAIN[16][1]	MAIN[15][1]	CELL.IMUX_IO_IK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_E.SINGLE_V[2]
0	1	1	1	1	1	0	1	CELL_E.SINGLE_V[3]
0	1	1	1	1	1	1	0	CELL_E.SINGLE_V[4]
1	1	1	1	1	1	1	1	CELL_E.SINGLE_V[5]

xc4000h IO_N1 switchbox INT muxes IMUX_IO_T[0]
Bits								Destination
MAIN[5][4]	MAIN[3][4]	MAIN[6][6]	MAIN[6][4]	MAIN[4][4]	MAIN[6][5]	MAIN[5][5]	MAIN[4][5]	CELL.IMUX_IO_T[0]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	0	1	1	1	CELL.LONG_IO_H[3]
0	0	1	0	1	1	0	1	CELL.LONG_IO_H[0]
0	0	1	0	1	1	1	0	CELL.LONG_IO_H[2]
0	0	1	1	1	0	0	1	CELL.DEC_H[2]
0	0	1	1	1	0	1	0	CELL.GCLK[0]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_N1[0]
0	1	1	1	1	0	1	1	CELL.DOUBLE_IO_N2[1]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_N1[1]
1	0	1	1	1	1	0	1	CELL.LONG_IO_H[1]
1	0	1	1	1	1	1	0	CELL.DEC_H[3]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_N2[0]

xc4000h IO_N1 switchbox INT muxes IMUX_IO_T[1]
Bits								Destination
MAIN[1][4]	MAIN[0][5]	MAIN[11][4]	MAIN[3][5]	MAIN[2][5]	MAIN[2][4]	MAIN[1][5]	MAIN[0][4]	CELL.IMUX_IO_T[1]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	0	1	1	1	CELL.GCLK[0]
0	0	1	0	1	1	0	1	CELL.DEC_H[3]
0	0	1	1	0	0	1	1	CELL.LONG_IO_H[0]
0	0	1	1	1	0	0	1	CELL.LONG_IO_H[3]
0	0	1	1	1	0	1	0	CELL.LONG_IO_H[2]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_N1[1]
0	1	1	1	1	0	1	1	CELL.DOUBLE_IO_N2[1]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_N2[0]
1	0	1	1	1	1	0	1	CELL.LONG_IO_H[1]
1	0	1	1	1	1	1	0	CELL.DEC_H[2]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_N1[0]

xc4000h IO_N1 switchbox INT muxes IMUX_HIO_O[0]
Bits	Destination
MAIN[26][6]	CELL.IMUX_HIO_O[0]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_F2_N

xc4000h IO_N1 switchbox INT muxes IMUX_HIO_O[1]
Bits	Destination
MAIN[21][6]	CELL.IMUX_HIO_O[1]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_F2_N

xc4000h IO_N1 switchbox INT muxes IMUX_HIO_O[2]
Bits	Destination
MAIN[12][6]	CELL.IMUX_HIO_O[2]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_G2_N

xc4000h IO_N1 switchbox INT muxes IMUX_HIO_O[3]
Bits	Destination
MAIN[8][6]	CELL.IMUX_HIO_O[3]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_G2_N

xc4000h IO_N1 switchbox INT muxes IMUX_HIO_T[0]
Bits	Destination
MAIN[28][6]	CELL.IMUX_HIO_T[0]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_OK[0]

xc4000h IO_N1 switchbox INT muxes IMUX_HIO_T[1]
Bits	Destination
MAIN[21][5]	CELL.IMUX_HIO_T[1]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_IK[0]

xc4000h IO_N1 switchbox INT muxes IMUX_HIO_T[2]
Bits	Destination
MAIN[14][6]	CELL.IMUX_HIO_T[2]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_IK[1]

xc4000h IO_N1 switchbox INT muxes IMUX_HIO_T[3]
Bits	Destination
MAIN[5][6]	CELL.IMUX_HIO_T[3]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_OK[1]

xc4000h IO_N1 switchbox INT muxes OUT_IO_SN_I1[0]
Bits	Destination
MAIN[20][5]	CELL.OUT_IO_SN_I1[0]
	Source
0	CELL.OUT_HIO_I[1]
1	CELL.OUT_HIO_I[0]

xc4000h IO_N1 switchbox INT muxes OUT_IO_SN_I1[1]
Bits	Destination
MAIN[15][6]	CELL.OUT_IO_SN_I1[1]
	Source
0	CELL.OUT_HIO_I[2]
1	CELL.OUT_HIO_I[3]

xc4000h IO_N1 switchbox INT muxes OUT_IO_SN_I2[0]
Bits	Destination
MAIN[31][6]	CELL.OUT_IO_SN_I2[0]
	Source
0	CELL.OUT_HIO_I[0]
1	CELL.OUT_HIO_I[1]

xc4000h IO_N1 switchbox INT muxes OUT_IO_SN_I2[1]
Bits	Destination
MAIN[3][6]	CELL.OUT_IO_SN_I2[1]
	Source
0	CELL.OUT_HIO_I[3]
1	CELL.OUT_HIO_I[2]

Bels HIO

xc4000h IO_N1 bel HIO pins
Pin	Direction	HIO[0]	HIO[1]	HIO[2]	HIO[3]
O	in	CELL.IMUX_HIO_O[0] invert by !MAIN[27][6]	CELL.IMUX_HIO_O[1] invert by !MAIN[22][6]	CELL.IMUX_HIO_O[2] invert by !MAIN[13][6]	CELL.IMUX_HIO_O[3] invert by !MAIN[7][6]
T	in	CELL.IMUX_HIO_T[0] invert by !MAIN[29][6]	CELL.IMUX_HIO_T[1] invert by !MAIN[20][6]	CELL.IMUX_HIO_T[2] invert by !MAIN[14][5]	CELL.IMUX_HIO_T[3] invert by !MAIN[4][6]
I	out	CELL.OUT_HIO_I[0]	CELL.OUT_HIO_I[1]	CELL.OUT_HIO_I[2]	CELL.OUT_HIO_I[3]

xc4000h IO_N1 bel HIO attribute bits
Attribute	HIO[0]	HIO[1]	HIO[2]	HIO[3]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
ISTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OSTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OMODE	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]
I_INV	!MAIN[32][6]	!MAIN[19][6]	!MAIN[16][6]	!MAIN[2][6]
READBACK_I bit 0	!MAIN[18][4]	!MAIN[18][3]	!MAIN[16][4]	!MAIN[17][3]

xc4000h IO_N1 enum IO_PULL
HIO[0].PULL	MAIN[24][6]	MAIN[25][6]
HIO[1].PULL	MAIN[24][5]	MAIN[22][5]
HIO[2].PULL	MAIN[11][5]	MAIN[13][5]
HIO[3].PULL	MAIN[10][6]	MAIN[9][6]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

xc4000h IO_N1 enum IO_STD
HIO[0].ISTD	MAIN[33][6]
HIO[1].ISTD	MAIN[18][6]
HIO[2].ISTD	MAIN[15][5]
HIO[3].ISTD	MAIN[1][6]
CMOS	0
TTL	1

xc4000h IO_N1 enum IO_STD
HIO[0].OSTD	MAIN[34][6]
HIO[1].OSTD	MAIN[18][5]
HIO[2].OSTD	MAIN[16][5]
HIO[3].OSTD	MAIN[0][6]
CMOS	1
TTL	0

xc4000h IO_N1 enum HIO_OMODE
HIO[0].OMODE	MAIN[23][6]
HIO[1].OMODE	MAIN[23][5]
HIO[2].OMODE	MAIN[12][5]
HIO[3].OMODE	MAIN[11][6]
CAP	1
RES	0

Bels DEC

xc4000h IO_N1 bel DEC pins
Pin	Direction	DEC[0]	DEC[1]	DEC[2]
I	in	CELL.OUT_IO_SN_I1[0]	CELL.IMUX_CLB_C2_N	CELL.OUT_IO_SN_I1[1]
O1	bidir	CELL.DEC_H[0]	CELL.DEC_H[0]	CELL.DEC_H[0]
O2	bidir	CELL.DEC_H[1]	CELL.DEC_H[1]	CELL.DEC_H[1]
O3	bidir	CELL.DEC_H[2]	CELL.DEC_H[2]	CELL.DEC_H[2]
O4	bidir	CELL.DEC_H[3]	CELL.DEC_H[3]	CELL.DEC_H[3]

xc4000h IO_N1 bel DEC attribute bits
Attribute	DEC[0]	DEC[1]	DEC[2]
O1_P	!MAIN[8][3]	!MAIN[6][2]	MAIN[7][3]
O1_N	MAIN[8][2]	MAIN[6][3]	!MAIN[7][2]
O2_P	!MAIN[3][3]	!MAIN[5][2]	MAIN[4][3]
O2_N	MAIN[3][2]	MAIN[5][3]	!MAIN[4][2]
O3_P	!MAIN[9][3]	!MAIN[11][2]	MAIN[10][3]
O3_N	MAIN[9][2]	MAIN[11][3]	!MAIN[10][2]
O4_P	!MAIN[14][3]	!MAIN[12][2]	MAIN[13][3]
O4_N	MAIN[14][2]	MAIN[12][3]	!MAIN[13][2]

Bel wires

xc4000h IO_N1 bel wires
Wire	Pins
CELL.DEC_H[0]	DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_H[1]	DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.DEC_H[2]	DEC[0].O3, DEC[1].O3, DEC[2].O3
CELL.DEC_H[3]	DEC[0].O4, DEC[1].O4, DEC[2].O4
CELL.IMUX_CLB_C2_N	DEC[1].I
CELL.IMUX_HIO_O[0]	HIO[0].O
CELL.IMUX_HIO_O[1]	HIO[1].O
CELL.IMUX_HIO_O[2]	HIO[2].O
CELL.IMUX_HIO_O[3]	HIO[3].O
CELL.IMUX_HIO_T[0]	HIO[0].T
CELL.IMUX_HIO_T[1]	HIO[1].T
CELL.IMUX_HIO_T[2]	HIO[2].T
CELL.IMUX_HIO_T[3]	HIO[3].T
CELL.OUT_IO_SN_I1[0]	DEC[0].I
CELL.OUT_IO_SN_I1[1]	DEC[2].I
CELL.OUT_HIO_I[0]	HIO[0].I
CELL.OUT_HIO_I[1]	HIO[1].I
CELL.OUT_HIO_I[2]	HIO[2].I
CELL.OUT_HIO_I[3]	HIO[3].I

Bitstream

xc4000h IO_N1 rect MAIN
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B6	-	HIO[0]: OSTD bit 0	HIO[0]: ISTD bit 0	HIO[0]: ! I_INV	INT: mux CELL.OUT_IO_SN_I2[0] bit 0	-	HIO[0]: !invert T	INT: mux CELL.IMUX_HIO_T[0] bit 0	HIO[0]: !invert O	INT: mux CELL.IMUX_HIO_O[0] bit 0	HIO[0]: PULL bit 0	HIO[0]: PULL bit 1	HIO[0]: OMODE bit 0	HIO[1]: !invert O	INT: mux CELL.IMUX_HIO_O[1] bit 0	HIO[1]: !invert T	HIO[1]: ! I_INV	HIO[1]: ISTD bit 0	-	HIO[2]: ! I_INV	INT: mux CELL.OUT_IO_SN_I1[1] bit 0	INT: mux CELL.IMUX_HIO_T[2] bit 0	HIO[2]: !invert O	INT: mux CELL.IMUX_HIO_O[2] bit 0	HIO[3]: OMODE bit 0	HIO[3]: PULL bit 1	HIO[3]: PULL bit 0	INT: mux CELL.IMUX_HIO_O[3] bit 0	HIO[3]: !invert O	INT: mux CELL.IMUX_IO_T[0] bit 5	INT: mux CELL.IMUX_HIO_T[3] bit 0	HIO[3]: !invert T	INT: mux CELL.OUT_IO_SN_I2[1] bit 0	HIO[3]: ! I_INV	HIO[3]: ISTD bit 0	HIO[3]: OSTD bit 0
B5	INT: !pass CELL.DOUBLE_IO_N0[3] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_N0[2] ← CELL.DBUF_IO_H[0]	INT: mux CELL.DBUF_IO_H[1] bit 0	INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_N2[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N1[3]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N0[2]	INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_N0[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N2[2]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N0[1]	INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N0[1]	INT: !bipass CELL.DOUBLE_IO_N0[1] = CELL.DOUBLE_IO_N2[1]	HIO[1]: PULL bit 1	HIO[1]: OMODE bit 0	HIO[1]: PULL bit 0	INT: mux CELL.IMUX_HIO_T[1] bit 0	INT: mux CELL.OUT_IO_SN_I1[0] bit 0	-	HIO[1]: OSTD bit 0	-	HIO[2]: OSTD bit 0	HIO[2]: ISTD bit 0	HIO[2]: !invert T	HIO[2]: PULL bit 0	HIO[2]: OMODE bit 0	HIO[2]: PULL bit 1	INT: !pass CELL.DOUBLE_IO_N2[3] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_N2[2] ← CELL.DBUF_IO_H[1]	INT: mux CELL.DBUF_IO_H[0] bit 0	INT: mux CELL.DBUF_IO_H[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 2	INT: mux CELL.IMUX_IO_T[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 0	INT: mux CELL.IMUX_IO_T[1] bit 4	INT: mux CELL.IMUX_IO_T[1] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 1	INT: mux CELL.IMUX_IO_T[1] bit 6
B4	INT: !pass CELL.DOUBLE_IO_N0[0] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_N0[1] ← CELL.DBUF_IO_H[0]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N0[3]	INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_N0[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N2[3]	INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_N2[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N1[2]	INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_N1[2]	INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N2[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N2[1]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N0[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N0[0]	INT: !bipass CELL.DOUBLE_IO_N0[0] = CELL.DOUBLE_IO_N2[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N2[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N2[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N1[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N1[0]	HIO[0]: ! READBACK_I bit 0	-	HIO[2]: ! READBACK_I bit 0	-	-	-	-	INT: mux CELL.IMUX_IO_T[1] bit 5	INT: !pass CELL.DOUBLE_IO_N2[0] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_N2[1] ← CELL.DBUF_IO_H[1]	INT: mux CELL.DBUF_IO_H[0] bit 2	INT: mux CELL.DBUF_IO_H[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 4	INT: mux CELL.IMUX_IO_T[0] bit 7	INT: mux CELL.IMUX_IO_T[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 6	INT: mux CELL.IMUX_IO_T[1] bit 2	INT: mux CELL.IMUX_IO_T[1] bit 7	INT: mux CELL.IMUX_IO_T[1] bit 0
B3	INT: mux CELL.DBUF_IO_H[1] bit 1	INT: mux CELL.DBUF_IO_H[1] bit 2	INT: mux CELL.DBUF_IO_H[1] bit 3	INT: !bipass CELL.DOUBLE_IO_N0[3] = CELL.DOUBLE_IO_N2[3]	INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_N1[3]	INT: !bipass CELL.DOUBLE_IO_N0[2] = CELL.DOUBLE_IO_N2[2]	-	INT: mux CELL.IMUX_IO_O1[0] bit 1	INT: mux CELL.IMUX_IO_O1[0] bit 2	INT: mux CELL.IMUX_IO_O1[0] bit 4	INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N1[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N1[1]	INT: mux CELL.LONG_IO_H[1] bit 3	INT: mux CELL.LONG_IO_H[2] bit 3	INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0]	-	HIO[1]: ! READBACK_I bit 0	HIO[3]: ! READBACK_I bit 0	INT: mux CELL.LONG_IO_H[1] bit 0	INT: mux CELL.LONG_IO_H[1] bit 2	DEC[0]: ! O4_P	DEC[2]: O4_P	DEC[1]: O4_N	DEC[1]: O3_N	DEC[2]: O3_P	DEC[0]: ! O3_P	DEC[0]: ! O1_P	DEC[2]: O1_P	DEC[1]: O1_N	DEC[1]: O2_N	DEC[2]: O2_P	DEC[0]: ! O2_P	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 0
B2	INT: !pass CELL.SINGLE_V[4] ← CELL.DEC_H[2]	INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_IO_H[3]	INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_IO_H[2]	INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.SINGLE_V[7] ← CELL.DEC_H[3]	INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[1]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1	INT: mux CELL.IMUX_IO_O1[0] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 5	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0]	-	INT: mux CELL.LONG_IO_H[3] bit 0	INT: mux CELL.LONG_IO_H[2] bit 0	INT: mux CELL.LONG_IO_H[2] bit 1	INT: mux CELL.LONG_IO_H[2] bit 2	INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[0]	INT: mux CELL.LONG_IO_H[1] bit 1	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[1]	INT: mux CELL.LONG_IO_H[0] bit 0	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[0]	DEC[0]: O4_N	DEC[2]: ! O4_N	DEC[1]: ! O4_P	DEC[1]: ! O3_P	DEC[2]: ! O3_N	DEC[0]: O3_N	DEC[0]: O1_N	DEC[2]: ! O1_N	DEC[1]: ! O1_P	DEC[1]: ! O2_P	DEC[2]: ! O2_N	DEC[0]: O2_N	INT: mux CELL.IMUX_IO_O1[1] bit 4	INT: mux CELL.IMUX_IO_O1[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 5
B1	INT: mux CELL.LONG_V[1] bit 3	INT: mux CELL.LONG_V[1] bit 0	INT: mux CELL.LONG_V[1] bit 2	INT: mux CELL.LONG_V[2] bit 1	INT: mux CELL.LONG_V[2] bit 3	INT: mux CELL.LONG_V[2] bit 2	INT: mux CELL.LONG_V[0] bit 1	INT: mux CELL.LONG_V[0] bit 0	INT: mux CELL.LONG_V[0] bit 2	INT: mux CELL.LONG_V[0] bit 3	INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_IO_SN_I1[0]	INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[3]	INT: mux CELL.IMUX_IO_OK[0] bit 7	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.IMUX_IO_IK[0] bit 4	INT: mux CELL.IMUX_IO_IK[0] bit 5	INT: mux CELL.IMUX_IO_IK[0] bit 6	INT: mux CELL.IMUX_IO_IK[0] bit 7	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 0	INT: mux CELL.IMUX_IO_IK[1] bit 7	INT: mux CELL.IMUX_IO_OK[1] bit 2	INT: mux CELL.IMUX_IO_OK[1] bit 1	INT: mux CELL.IMUX_IO_OK[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 7	INT: mux CELL.LONG_V[5] bit 1	INT: mux CELL.LONG_V[5] bit 3	INT: mux CELL.LONG_V[3] bit 0	INT: mux CELL.LONG_V[3] bit 3	INT: mux CELL.LONG_V[4] bit 3	INT: mux CELL.LONG_IO_H[3] bit 1	-	INT: mux CELL.LONG_V[4] bit 0	-	-
B0	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.LONG_V[1] bit 1	INT: mux CELL.LONG_V[2] bit 0	INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1	INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0]	INT: mux CELL.IMUX_IO_OK[0] bit 6	INT: mux CELL.IMUX_IO_OK[0] bit 5	INT: mux CELL.IMUX_IO_OK[0] bit 4	INT: mux CELL.IMUX_IO_OK[0] bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 1	INT: mux CELL.IMUX_IO_OK[0] bit 3	INT: mux CELL.IMUX_IO_OK[0] bit 2	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0]	INT: mux CELL.IMUX_IO_IK[0] bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 1	INT: mux CELL.IMUX_IO_IK[0] bit 3	INT: mux CELL.IMUX_IO_IK[0] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 5	INT: mux CELL.IMUX_IO_IK[1] bit 6	INT: mux CELL.IMUX_IO_IK[1] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 3	INT: mux CELL.IMUX_IO_OK[1] bit 5	INT: mux CELL.IMUX_IO_OK[1] bit 6	INT: mux CELL.IMUX_IO_OK[1] bit 4	INT: mux CELL.IMUX_IO_OK[1] bit 3	INT: mux CELL.LONG_V[5] bit 0	INT: mux CELL.LONG_V[5] bit 2	INT: mux CELL.LONG_V[3] bit 1	INT: mux CELL.LONG_V[3] bit 2	-	INT: mux CELL.LONG_IO_H[0] bit 1	-	INT: mux CELL.LONG_V[4] bit 1	INT: mux CELL.LONG_V[4] bit 2	-

xc4000h IO_N1 rect MAIN_S
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	-	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1]	-	-	-	INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2]	-	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0]	-	INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

xc4000h IO_N1 rect MAIN_E
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

xc4000h IO_N1 rect MAIN_W
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile IO_N1_W

Cells: 3

Switchbox INT

xc4000h IO_N1_W switchbox INT programmable buffers
Destination	Source	Bit
CELL.LONG_H[0]	CELL.SINGLE_V[1]	!MAIN_S[21][8]
CELL.LONG_H[1]	CELL.SINGLE_V[2]	!MAIN_S[25][8]
CELL.LONG_H[2]	CELL.SINGLE_V[3]	!MAIN[24][1]

xc4000h IO_N1_W switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_V[0]	CELL.DEC_H[0]	!MAIN[19][2]
CELL.SINGLE_V[0]	CELL.OUT_IO_SN_I2_E1	!MAIN[22][1]
CELL.SINGLE_V[1]	CELL.LONG_H[0]	!MAIN_S[23][8]
CELL.SINGLE_V[1]	CELL.LONG_IO_H[0]	!MAIN[15][2]
CELL.SINGLE_V[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[22][0]
CELL.SINGLE_V[2]	CELL.LONG_H[1]	!MAIN_S[29][8]
CELL.SINGLE_V[2]	CELL.LONG_IO_H[1]	!MAIN[17][2]
CELL.SINGLE_V[2]	CELL.OUT_IO_SN_I1[0]	!MAIN[25][2]
CELL.SINGLE_V[3]	CELL.LONG_H[2]	!MAIN_S[28][9]
CELL.SINGLE_V[3]	CELL.DEC_H[1]	!MAIN[30][2]
CELL.SINGLE_V[3]	CELL.OUT_IO_SN_I1_E1	!MAIN[29][2]
CELL.SINGLE_V[4]	CELL.DEC_H[2]	!MAIN[35][2]
CELL.SINGLE_V[4]	CELL.OUT_IO_SN_I2_E1	!MAIN[35][0]
CELL.SINGLE_V[5]	CELL.LONG_IO_H[2]	!MAIN[33][2]
CELL.SINGLE_V[5]	CELL.OUT_IO_SN_I2[0]	!MAIN[32][0]
CELL.SINGLE_V[6]	CELL.LONG_IO_H[3]	!MAIN[34][2]
CELL.SINGLE_V[6]	CELL.OUT_IO_SN_I1[0]	!MAIN[25][1]
CELL.SINGLE_V[7]	CELL.DEC_H[3]	!MAIN[31][2]
CELL.SINGLE_V[7]	CELL.OUT_IO_SN_I1_E1	!MAIN[32][2]
CELL.DOUBLE_V0[0]	CELL.OUT_IO_SN_I1_E1	!MAIN[21][3]
CELL.DOUBLE_V0[1]	CELL.OUT_IO_SN_I2[0]	!MAIN[30][0]
CELL.DOUBLE_V1[0]	CELL.OUT_IO_SN_I1[0]	!MAIN[20][3]
CELL.DOUBLE_V1[1]	CELL.OUT_IO_SN_I2_E1	!MAIN[31][0]
CELL.DOUBLE_IO_N0[0]	CELL.DBUF_IO_H[0]	!MAIN[35][4]
CELL.DOUBLE_IO_N0[1]	CELL.DBUF_IO_H[0]	!MAIN[34][4]
CELL.DOUBLE_IO_N0[2]	CELL.DBUF_IO_H[0]	!MAIN[34][5]
CELL.DOUBLE_IO_N0[3]	CELL.DBUF_IO_H[0]	!MAIN[35][5]
CELL.DOUBLE_IO_N2[0]	CELL.DBUF_IO_H[1]	!MAIN[10][4]
CELL.DOUBLE_IO_N2[1]	CELL.DBUF_IO_H[1]	!MAIN[9][4]
CELL.DOUBLE_IO_N2[2]	CELL.DBUF_IO_H[1]	!MAIN[9][5]
CELL.DOUBLE_IO_N2[3]	CELL.DBUF_IO_H[1]	!MAIN[10][5]

xc4000h IO_N1_W switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_V[0]	CELL.DOUBLE_IO_N1[0]	!MAIN[19][4]
CELL.SINGLE_V[1]	CELL.DOUBLE_IO_N0[0]	!MAIN[24][4]
CELL.SINGLE_V[1]	CELL.DOUBLE_IO_N2[0]	!MAIN[22][4]
CELL.SINGLE_V[2]	CELL.DOUBLE_IO_N1[1]	!MAIN[25][3]
CELL.SINGLE_V[3]	CELL.DOUBLE_IO_N0[1]	!MAIN[26][5]
CELL.SINGLE_V[3]	CELL.DOUBLE_IO_N2[1]	!MAIN[27][4]
CELL.SINGLE_V[4]	CELL.DOUBLE_IO_N1[2]	!MAIN[28][4]
CELL.SINGLE_V[5]	CELL.DOUBLE_IO_N0[2]	!MAIN[29][5]
CELL.SINGLE_V[5]	CELL.DOUBLE_IO_N2[2]	!MAIN[30][4]
CELL.SINGLE_V[6]	CELL.DOUBLE_IO_N1[3]	!MAIN[31][3]
CELL.SINGLE_V[7]	CELL.DOUBLE_IO_N0[3]	!MAIN[32][4]
CELL.SINGLE_V[7]	CELL.DOUBLE_IO_N2[3]	!MAIN[32][5]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_N0[1]	!MAIN[27][5]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_N1[1]	!MAIN[24][3]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_N2[1]	!MAIN[26][4]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_N0[2]	!MAIN[30][5]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_N1[2]	!MAIN[29][4]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_N2[2]	!MAIN[28][5]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_N0[0]	!MAIN[25][4]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_N1[0]	!MAIN[20][4]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_N2[0]	!MAIN[21][4]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_N0[3]	!MAIN[33][4]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_N1[3]	!MAIN[31][5]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_N2[3]	!MAIN[31][4]
CELL.DOUBLE_IO_N0[0]	CELL.DOUBLE_IO_N2[0]	!MAIN[23][4]
CELL.DOUBLE_IO_N0[1]	CELL.DOUBLE_IO_N2[1]	!MAIN[25][5]
CELL.DOUBLE_IO_N0[2]	CELL.DOUBLE_IO_N2[2]	!MAIN[30][3]
CELL.DOUBLE_IO_N0[3]	CELL.DOUBLE_IO_N2[3]	!MAIN[32][3]

xc4000h IO_N1_W switchbox INT muxes DBUF_IO_H[0]
Bits				Destination
MAIN[7][4]	MAIN[8][4]	MAIN[7][5]	MAIN[8][5]	CELL.DBUF_IO_H[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_N2[0]
0	1	0	1	CELL.DOUBLE_IO_N2[2]
0	1	1	0	CELL.DOUBLE_IO_N2[3]
1	1	1	1	CELL.DOUBLE_IO_N2[1]

xc4000h IO_N1_W switchbox INT muxes DBUF_IO_H[1]
Bits				Destination
MAIN[33][3]	MAIN[34][3]	MAIN[35][3]	MAIN[33][5]	CELL.DBUF_IO_H[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_N0[1]
0	1	0	1	CELL.DOUBLE_IO_N0[2]
0	1	1	0	CELL.DOUBLE_IO_N0[3]
1	1	1	1	CELL.DOUBLE_IO_N0[0]

xc4000h IO_N1_W switchbox INT muxes LONG_V[0]
Bits				Destination
MAIN[26][1]	MAIN[27][1]	MAIN[29][1]	MAIN[28][1]	CELL.LONG_V[0]
				Source
0	0	0	1	CELL.LONG_IO_H[0]
0	0	1	0	CELL.DEC_H[3]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_N1_W switchbox INT muxes LONG_V[1]
Bits				Destination
MAIN[35][1]	MAIN[33][1]	MAIN[34][0]	MAIN[34][1]	CELL.LONG_V[1]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_N1_W switchbox INT muxes LONG_V[2]
Bits				Destination
MAIN[31][1]	MAIN[30][1]	MAIN[32][1]	MAIN[33][0]	CELL.LONG_V[2]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000h IO_N1_W switchbox INT muxes LONG_V[3]
Bits				Destination
MAIN[6][1]	MAIN[6][0]	MAIN[7][0]	MAIN[7][1]	CELL.LONG_V[3]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_N1_W switchbox INT muxes LONG_V[4]
Bits				Destination
MAIN[5][1]	MAIN[1][0]	MAIN[2][0]	MAIN[2][1]	CELL.LONG_V[4]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_N1_W switchbox INT muxes LONG_V[5]
Bits				Destination
MAIN[8][1]	MAIN[8][0]	MAIN[9][1]	MAIN[9][0]	CELL.LONG_V[5]
				Source
0	0	0	1	CELL.LONG_IO_H[3]
0	0	1	0	CELL.DEC_H[0]
0	1	1	1	CELL.OUT_IO_SN_I2[0]
1	1	1	1	off

xc4000h IO_N1_W switchbox INT muxes LONG_IO_H[0]
Bits		Destination
MAIN[4][0]	MAIN[16][2]	CELL.LONG_IO_H[0]
		Source
0	0	CELL.LONG_V[0]
0	1	CELL.SINGLE_V[1]
1	1	off

xc4000h IO_N1_W switchbox INT muxes LONG_IO_H[1]
Bits				Destination
MAIN[23][3]	MAIN[15][3]	MAIN[18][2]	MAIN[16][3]	CELL.LONG_IO_H[1]
				Source
0	0	0	1	CELL.LONG_V[1]
0	0	1	0	CELL.LONG_V[3]
0	1	1	1	CELL.SINGLE_V[2]
1	1	1	1	off

xc4000h IO_N1_W switchbox INT muxes LONG_IO_H[2]
Bits				Destination
MAIN[22][3]	MAIN[20][2]	MAIN[21][2]	MAIN[22][2]	CELL.LONG_IO_H[2]
				Source
0	0	0	1	CELL.LONG_V[2]
0	0	1	0	CELL.LONG_V[4]
0	1	1	1	CELL.SINGLE_V[5]
1	1	1	1	off

xc4000h IO_N1_W switchbox INT muxes LONG_IO_H[3]
Bits		Destination
MAIN[4][1]	MAIN[23][2]	CELL.LONG_IO_H[3]
		Source
0	0	CELL.LONG_V[5]
0	1	CELL.SINGLE_V[6]
1	1	off

xc4000h IO_N1_W switchbox INT muxes IMUX_IO_O1[0]
Bits						Destination
MAIN[26][2]	MAIN[26][3]	MAIN[28][2]	MAIN[27][3]	MAIN[28][3]	MAIN[27][2]	CELL.IMUX_IO_O1[0]
						Source
0	0	0	1	1	1	CELL.DEC_H[1]
0	0	1	1	1	1	CELL.DOUBLE_V0[0]
0	1	0	0	1	1	CELL.DEC_H[3]
0	1	0	1	0	1	CELL.DEC_H[0]
0	1	0	1	1	0	CELL.LONG_V[5]
0	1	1	0	1	1	CELL.LONG_V[3]
0	1	1	1	0	1	CELL.LONG_V[4]
0	1	1	1	1	0	CELL.DEC_H[2]
1	1	0	1	1	1	CELL.DOUBLE_V1[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_N1_W switchbox INT muxes IMUX_IO_O1[1]
Bits						Destination
MAIN[0][2]	MAIN[2][2]	MAIN[1][3]	MAIN[1][2]	MAIN[2][3]	MAIN[0][3]	CELL.IMUX_IO_O1[1]
						Source
0	0	0	1	1	1	CELL.DEC_H[0]
0	0	1	0	1	1	CELL.DEC_H[1]
0	0	1	1	0	1	CELL.DEC_H[3]
0	0	1	1	1	0	CELL_E.LONG_V[2]
0	1	0	1	1	1	CELL_E.LONG_V[0]
0	1	1	0	1	1	CELL.DEC_H[2]
0	1	1	1	0	1	CELL_E.LONG_V[1]
0	1	1	1	1	0	CELL_E.DOUBLE_V1[0]
1	0	1	1	1	1	CELL_E.DOUBLE_V0[1]
1	1	1	1	1	1	CELL.TIE_0

xc4000h IO_N1_W switchbox INT muxes IMUX_IO_OK[0]
Bits								Destination
MAIN[23][1]	MAIN[29][0]	MAIN[28][0]	MAIN[27][0]	MAIN[24][0]	MAIN[23][0]	MAIN[25][0]	MAIN[26][0]	CELL.IMUX_IO_OK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_V[3]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[2]

xc4000h IO_N1_W switchbox INT muxes IMUX_IO_OK[1]
Bits								Destination
MAIN[10][1]	MAIN[12][0]	MAIN[13][0]	MAIN[11][0]	MAIN[10][0]	MAIN[13][1]	MAIN[12][1]	MAIN[11][1]	CELL.IMUX_IO_OK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_E.SINGLE_V[2]
0	1	1	1	1	1	0	1	CELL_E.SINGLE_V[3]
0	1	1	1	1	1	1	0	CELL_E.SINGLE_V[5]
1	1	1	1	1	1	1	1	CELL_E.SINGLE_V[4]

xc4000h IO_N1_W switchbox INT muxes IMUX_IO_IK[0]
Bits								Destination
MAIN[18][1]	MAIN[19][1]	MAIN[20][1]	MAIN[21][1]	MAIN[19][0]	MAIN[18][0]	MAIN[20][0]	MAIN[21][0]	CELL.IMUX_IO_IK[0]
								Source
0	0	1	1	1	1	1	1	CELL.SINGLE_V[2]
0	1	0	1	1	1	1	1	CELL.SINGLE_V[4]
0	1	1	0	1	1	1	1	CELL.SINGLE_V[5]
0	1	1	1	0	1	1	1	CELL.GCLK[0]
0	1	1	1	1	0	1	1	CELL.GCLK[1]
0	1	1	1	1	1	0	1	CELL.GCLK[2]
0	1	1	1	1	1	1	0	CELL.GCLK[3]
1	1	1	1	1	1	1	1	CELL.SINGLE_V[3]

xc4000h IO_N1_W switchbox INT muxes IMUX_IO_IK[1]
Bits								Destination
MAIN[14][1]	MAIN[16][0]	MAIN[17][0]	MAIN[15][0]	MAIN[14][0]	MAIN[17][1]	MAIN[16][1]	MAIN[15][1]	CELL.IMUX_IO_IK[1]
								Source
0	0	1	1	1	1	1	1	CELL.GCLK[0]
0	1	0	1	1	1	1	1	CELL.GCLK[1]
0	1	1	0	1	1	1	1	CELL.GCLK[2]
0	1	1	1	0	1	1	1	CELL.GCLK[3]
0	1	1	1	1	0	1	1	CELL_E.SINGLE_V[2]
0	1	1	1	1	1	0	1	CELL_E.SINGLE_V[3]
0	1	1	1	1	1	1	0	CELL_E.SINGLE_V[4]
1	1	1	1	1	1	1	1	CELL_E.SINGLE_V[5]

xc4000h IO_N1_W switchbox INT muxes IMUX_IO_T[0]
Bits								Destination
MAIN[5][4]	MAIN[3][4]	MAIN[6][6]	MAIN[6][4]	MAIN[4][4]	MAIN[6][5]	MAIN[5][5]	MAIN[4][5]	CELL.IMUX_IO_T[0]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	0	1	1	1	CELL.LONG_IO_H[3]
0	0	1	0	1	1	0	1	CELL.LONG_IO_H[0]
0	0	1	0	1	1	1	0	CELL.LONG_IO_H[2]
0	0	1	1	1	0	0	1	CELL.DEC_H[2]
0	0	1	1	1	0	1	0	CELL.GCLK[0]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_N1[0]
0	1	1	1	1	0	1	1	CELL.DOUBLE_IO_N2[1]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_N1[1]
1	0	1	1	1	1	0	1	CELL.LONG_IO_H[1]
1	0	1	1	1	1	1	0	CELL.DEC_H[3]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_N2[0]

xc4000h IO_N1_W switchbox INT muxes IMUX_IO_T[1]
Bits								Destination
MAIN[1][4]	MAIN[0][5]	MAIN[11][4]	MAIN[3][5]	MAIN[2][5]	MAIN[2][4]	MAIN[1][5]	MAIN[0][4]	CELL.IMUX_IO_T[1]
								Source
0	0	0	1	1	1	1	1	CELL.TIE_0
0	0	1	0	0	1	1	1	CELL.GCLK[0]
0	0	1	0	1	1	0	1	CELL.DEC_H[3]
0	0	1	1	0	0	1	1	CELL.LONG_IO_H[0]
0	0	1	1	1	0	0	1	CELL.LONG_IO_H[3]
0	0	1	1	1	0	1	0	CELL.LONG_IO_H[2]
0	1	1	0	1	1	1	1	CELL.DOUBLE_IO_N1[1]
0	1	1	1	1	0	1	1	CELL.DOUBLE_IO_N2[1]
1	0	1	1	0	1	1	1	CELL.DOUBLE_IO_N2[0]
1	0	1	1	1	1	0	1	CELL.LONG_IO_H[1]
1	0	1	1	1	1	1	0	CELL.DEC_H[2]
1	1	1	1	1	1	1	1	CELL.DOUBLE_IO_N1[0]

xc4000h IO_N1_W switchbox INT muxes IMUX_HIO_O[0]
Bits	Destination
MAIN[26][6]	CELL.IMUX_HIO_O[0]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_F2_N

xc4000h IO_N1_W switchbox INT muxes IMUX_HIO_O[1]
Bits	Destination
MAIN[21][6]	CELL.IMUX_HIO_O[1]
	Source
0	CELL.IMUX_IO_O1[0]
1	CELL.IMUX_CLB_F2_N

xc4000h IO_N1_W switchbox INT muxes IMUX_HIO_O[2]
Bits	Destination
MAIN[12][6]	CELL.IMUX_HIO_O[2]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_G2_N

xc4000h IO_N1_W switchbox INT muxes IMUX_HIO_O[3]
Bits	Destination
MAIN[8][6]	CELL.IMUX_HIO_O[3]
	Source
0	CELL.IMUX_IO_O1[1]
1	CELL.IMUX_CLB_G2_N

xc4000h IO_N1_W switchbox INT muxes IMUX_HIO_T[0]
Bits	Destination
MAIN[28][6]	CELL.IMUX_HIO_T[0]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_OK[0]

xc4000h IO_N1_W switchbox INT muxes IMUX_HIO_T[1]
Bits	Destination
MAIN[21][5]	CELL.IMUX_HIO_T[1]
	Source
0	CELL.IMUX_IO_T[0]
1	CELL.IMUX_IO_IK[0]

xc4000h IO_N1_W switchbox INT muxes IMUX_HIO_T[2]
Bits	Destination
MAIN[14][6]	CELL.IMUX_HIO_T[2]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_IK[1]

xc4000h IO_N1_W switchbox INT muxes IMUX_HIO_T[3]
Bits	Destination
MAIN[5][6]	CELL.IMUX_HIO_T[3]
	Source
0	CELL.IMUX_IO_T[1]
1	CELL.IMUX_IO_OK[1]

xc4000h IO_N1_W switchbox INT muxes OUT_IO_SN_I1[0]
Bits	Destination
MAIN[20][5]	CELL.OUT_IO_SN_I1[0]
	Source
0	CELL.OUT_HIO_I[1]
1	CELL.OUT_HIO_I[0]

xc4000h IO_N1_W switchbox INT muxes OUT_IO_SN_I1[1]
Bits	Destination
MAIN[15][6]	CELL.OUT_IO_SN_I1[1]
	Source
0	CELL.OUT_HIO_I[2]
1	CELL.OUT_HIO_I[3]

xc4000h IO_N1_W switchbox INT muxes OUT_IO_SN_I2[0]
Bits	Destination
MAIN[31][6]	CELL.OUT_IO_SN_I2[0]
	Source
0	CELL.OUT_HIO_I[0]
1	CELL.OUT_HIO_I[1]

xc4000h IO_N1_W switchbox INT muxes OUT_IO_SN_I2[1]
Bits	Destination
MAIN[3][6]	CELL.OUT_IO_SN_I2[1]
	Source
0	CELL.OUT_HIO_I[3]
1	CELL.OUT_HIO_I[2]

Bels HIO

xc4000h IO_N1_W bel HIO pins
Pin	Direction	HIO[0]	HIO[1]	HIO[2]	HIO[3]
O	in	CELL.IMUX_HIO_O[0] invert by !MAIN[27][6]	CELL.IMUX_HIO_O[1] invert by !MAIN[22][6]	CELL.IMUX_HIO_O[2] invert by !MAIN[13][6]	CELL.IMUX_HIO_O[3] invert by !MAIN[7][6]
T	in	CELL.IMUX_HIO_T[0] invert by !MAIN[29][6]	CELL.IMUX_HIO_T[1] invert by !MAIN[20][6]	CELL.IMUX_HIO_T[2] invert by !MAIN[14][5]	CELL.IMUX_HIO_T[3] invert by !MAIN[4][6]
I	out	CELL.OUT_HIO_I[0]	CELL.OUT_HIO_I[1]	CELL.OUT_HIO_I[2]	CELL.OUT_HIO_I[3]
CLKIN	out	CELL.OUT_IO_CLKIN	-	-	-

xc4000h IO_N1_W bel HIO attribute bits
Attribute	HIO[0]	HIO[1]	HIO[2]	HIO[3]
PULL	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]	[enum: IO_PULL]
ISTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OSTD	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]	[enum: IO_STD]
OMODE	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]	[enum: HIO_OMODE]
I_INV	!MAIN[32][6]	!MAIN[19][6]	!MAIN[16][6]	!MAIN[2][6]
READBACK_I bit 0	!MAIN[18][4]	!MAIN[18][3]	!MAIN[16][4]	!MAIN[17][3]

xc4000h IO_N1_W enum IO_PULL
HIO[0].PULL	MAIN[24][6]	MAIN[25][6]
HIO[1].PULL	MAIN[24][5]	MAIN[22][5]
HIO[2].PULL	MAIN[11][5]	MAIN[13][5]
HIO[3].PULL	MAIN[10][6]	MAIN[9][6]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

xc4000h IO_N1_W enum IO_STD
HIO[0].ISTD	MAIN[33][6]
HIO[1].ISTD	MAIN[18][6]
HIO[2].ISTD	MAIN[15][5]
HIO[3].ISTD	MAIN[1][6]
CMOS	0
TTL	1

xc4000h IO_N1_W enum IO_STD
HIO[0].OSTD	MAIN[34][6]
HIO[1].OSTD	MAIN[18][5]
HIO[2].OSTD	MAIN[16][5]
HIO[3].OSTD	MAIN[0][6]
CMOS	1
TTL	0

xc4000h IO_N1_W enum HIO_OMODE
HIO[0].OMODE	MAIN[23][6]
HIO[1].OMODE	MAIN[23][5]
HIO[2].OMODE	MAIN[12][5]
HIO[3].OMODE	MAIN[11][6]
CAP	1
RES	0

Bels DEC

xc4000h IO_N1_W bel DEC pins
Pin	Direction	DEC[0]	DEC[1]	DEC[2]
I	in	CELL.OUT_IO_SN_I1[0]	CELL.IMUX_CLB_C2_N	CELL.OUT_IO_SN_I1[1]
O1	bidir	CELL.DEC_H[0]	CELL.DEC_H[0]	CELL.DEC_H[0]
O2	bidir	CELL.DEC_H[1]	CELL.DEC_H[1]	CELL.DEC_H[1]
O3	bidir	CELL.DEC_H[2]	CELL.DEC_H[2]	CELL.DEC_H[2]
O4	bidir	CELL.DEC_H[3]	CELL.DEC_H[3]	CELL.DEC_H[3]

xc4000h IO_N1_W bel DEC attribute bits
Attribute	DEC[0]	DEC[1]	DEC[2]
O1_P	!MAIN[8][3]	!MAIN[6][2]	MAIN[7][3]
O1_N	MAIN[8][2]	MAIN[6][3]	!MAIN[7][2]
O2_P	!MAIN[3][3]	!MAIN[5][2]	MAIN[4][3]
O2_N	MAIN[3][2]	MAIN[5][3]	!MAIN[4][2]
O3_P	!MAIN[9][3]	!MAIN[11][2]	MAIN[10][3]
O3_N	MAIN[9][2]	MAIN[11][3]	!MAIN[10][2]
O4_P	!MAIN[14][3]	!MAIN[12][2]	MAIN[13][3]
O4_N	MAIN[14][2]	MAIN[12][3]	!MAIN[13][2]

Bel wires

xc4000h IO_N1_W bel wires
Wire	Pins
CELL.DEC_H[0]	DEC[0].O1, DEC[1].O1, DEC[2].O1
CELL.DEC_H[1]	DEC[0].O2, DEC[1].O2, DEC[2].O2
CELL.DEC_H[2]	DEC[0].O3, DEC[1].O3, DEC[2].O3
CELL.DEC_H[3]	DEC[0].O4, DEC[1].O4, DEC[2].O4
CELL.IMUX_CLB_C2_N	DEC[1].I
CELL.IMUX_HIO_O[0]	HIO[0].O
CELL.IMUX_HIO_O[1]	HIO[1].O
CELL.IMUX_HIO_O[2]	HIO[2].O
CELL.IMUX_HIO_O[3]	HIO[3].O
CELL.IMUX_HIO_T[0]	HIO[0].T
CELL.IMUX_HIO_T[1]	HIO[1].T
CELL.IMUX_HIO_T[2]	HIO[2].T
CELL.IMUX_HIO_T[3]	HIO[3].T
CELL.OUT_IO_SN_I1[0]	DEC[0].I
CELL.OUT_IO_SN_I1[1]	DEC[2].I
CELL.OUT_HIO_I[0]	HIO[0].I
CELL.OUT_HIO_I[1]	HIO[1].I
CELL.OUT_HIO_I[2]	HIO[2].I
CELL.OUT_HIO_I[3]	HIO[3].I
CELL.OUT_IO_CLKIN	HIO[0].CLKIN

Bitstream

xc4000h IO_N1_W rect MAIN
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B6	-	HIO[0]: OSTD bit 0	HIO[0]: ISTD bit 0	HIO[0]: ! I_INV	INT: mux CELL.OUT_IO_SN_I2[0] bit 0	-	HIO[0]: !invert T	INT: mux CELL.IMUX_HIO_T[0] bit 0	HIO[0]: !invert O	INT: mux CELL.IMUX_HIO_O[0] bit 0	HIO[0]: PULL bit 0	HIO[0]: PULL bit 1	HIO[0]: OMODE bit 0	HIO[1]: !invert O	INT: mux CELL.IMUX_HIO_O[1] bit 0	HIO[1]: !invert T	HIO[1]: ! I_INV	HIO[1]: ISTD bit 0	-	HIO[2]: ! I_INV	INT: mux CELL.OUT_IO_SN_I1[1] bit 0	INT: mux CELL.IMUX_HIO_T[2] bit 0	HIO[2]: !invert O	INT: mux CELL.IMUX_HIO_O[2] bit 0	HIO[3]: OMODE bit 0	HIO[3]: PULL bit 1	HIO[3]: PULL bit 0	INT: mux CELL.IMUX_HIO_O[3] bit 0	HIO[3]: !invert O	INT: mux CELL.IMUX_IO_T[0] bit 5	INT: mux CELL.IMUX_HIO_T[3] bit 0	HIO[3]: !invert T	INT: mux CELL.OUT_IO_SN_I2[1] bit 0	HIO[3]: ! I_INV	HIO[3]: ISTD bit 0	HIO[3]: OSTD bit 0
B5	INT: !pass CELL.DOUBLE_IO_N0[3] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_N0[2] ← CELL.DBUF_IO_H[0]	INT: mux CELL.DBUF_IO_H[1] bit 0	INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_N2[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N1[3]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N0[2]	INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_N0[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N2[2]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N0[1]	INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N0[1]	INT: !bipass CELL.DOUBLE_IO_N0[1] = CELL.DOUBLE_IO_N2[1]	HIO[1]: PULL bit 1	HIO[1]: OMODE bit 0	HIO[1]: PULL bit 0	INT: mux CELL.IMUX_HIO_T[1] bit 0	INT: mux CELL.OUT_IO_SN_I1[0] bit 0	-	HIO[1]: OSTD bit 0	-	HIO[2]: OSTD bit 0	HIO[2]: ISTD bit 0	HIO[2]: !invert T	HIO[2]: PULL bit 0	HIO[2]: OMODE bit 0	HIO[2]: PULL bit 1	INT: !pass CELL.DOUBLE_IO_N2[3] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_N2[2] ← CELL.DBUF_IO_H[1]	INT: mux CELL.DBUF_IO_H[0] bit 0	INT: mux CELL.DBUF_IO_H[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 2	INT: mux CELL.IMUX_IO_T[0] bit 1	INT: mux CELL.IMUX_IO_T[0] bit 0	INT: mux CELL.IMUX_IO_T[1] bit 4	INT: mux CELL.IMUX_IO_T[1] bit 3	INT: mux CELL.IMUX_IO_T[1] bit 1	INT: mux CELL.IMUX_IO_T[1] bit 6
B4	INT: !pass CELL.DOUBLE_IO_N0[0] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_N0[1] ← CELL.DBUF_IO_H[0]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N0[3]	INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_N0[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N2[3]	INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_N2[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N1[2]	INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_N1[2]	INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N2[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N2[1]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N0[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N0[0]	INT: !bipass CELL.DOUBLE_IO_N0[0] = CELL.DOUBLE_IO_N2[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N2[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N2[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N1[0]	INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_N1[0]	HIO[0]: ! READBACK_I bit 0	-	HIO[2]: ! READBACK_I bit 0	-	-	-	-	INT: mux CELL.IMUX_IO_T[1] bit 5	INT: !pass CELL.DOUBLE_IO_N2[0] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_N2[1] ← CELL.DBUF_IO_H[1]	INT: mux CELL.DBUF_IO_H[0] bit 2	INT: mux CELL.DBUF_IO_H[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 4	INT: mux CELL.IMUX_IO_T[0] bit 7	INT: mux CELL.IMUX_IO_T[0] bit 3	INT: mux CELL.IMUX_IO_T[0] bit 6	INT: mux CELL.IMUX_IO_T[1] bit 2	INT: mux CELL.IMUX_IO_T[1] bit 7	INT: mux CELL.IMUX_IO_T[1] bit 0
B3	INT: mux CELL.DBUF_IO_H[1] bit 1	INT: mux CELL.DBUF_IO_H[1] bit 2	INT: mux CELL.DBUF_IO_H[1] bit 3	INT: !bipass CELL.DOUBLE_IO_N0[3] = CELL.DOUBLE_IO_N2[3]	INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_N1[3]	INT: !bipass CELL.DOUBLE_IO_N0[2] = CELL.DOUBLE_IO_N2[2]	-	INT: mux CELL.IMUX_IO_O1[0] bit 1	INT: mux CELL.IMUX_IO_O1[0] bit 2	INT: mux CELL.IMUX_IO_O1[0] bit 4	INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_N1[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N1[1]	INT: mux CELL.LONG_IO_H[1] bit 3	INT: mux CELL.LONG_IO_H[2] bit 3	INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_IO_SN_I1[0]	-	HIO[1]: ! READBACK_I bit 0	HIO[3]: ! READBACK_I bit 0	INT: mux CELL.LONG_IO_H[1] bit 0	INT: mux CELL.LONG_IO_H[1] bit 2	DEC[0]: ! O4_P	DEC[2]: O4_P	DEC[1]: O4_N	DEC[1]: O3_N	DEC[2]: O3_P	DEC[0]: ! O3_P	DEC[0]: ! O1_P	DEC[2]: O1_P	DEC[1]: O1_N	DEC[1]: O2_N	DEC[2]: O2_P	DEC[0]: ! O2_P	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 0
B2	INT: !pass CELL.SINGLE_V[4] ← CELL.DEC_H[2]	INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_IO_H[3]	INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_IO_H[2]	INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.SINGLE_V[7] ← CELL.DEC_H[3]	INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[1]	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1	INT: mux CELL.IMUX_IO_O1[0] bit 3	INT: mux CELL.IMUX_IO_O1[0] bit 0	INT: mux CELL.IMUX_IO_O1[0] bit 5	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_IO_SN_I1[0]	-	INT: mux CELL.LONG_IO_H[3] bit 0	INT: mux CELL.LONG_IO_H[2] bit 0	INT: mux CELL.LONG_IO_H[2] bit 1	INT: mux CELL.LONG_IO_H[2] bit 2	INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[0]	INT: mux CELL.LONG_IO_H[1] bit 1	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[1]	INT: mux CELL.LONG_IO_H[0] bit 0	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[0]	DEC[0]: O4_N	DEC[2]: ! O4_N	DEC[1]: ! O4_P	DEC[1]: ! O3_P	DEC[2]: ! O3_N	DEC[0]: O3_N	DEC[0]: O1_N	DEC[2]: ! O1_N	DEC[1]: ! O1_P	DEC[1]: ! O2_P	DEC[2]: ! O2_N	DEC[0]: O2_N	INT: mux CELL.IMUX_IO_O1[1] bit 4	INT: mux CELL.IMUX_IO_O1[1] bit 2	INT: mux CELL.IMUX_IO_O1[1] bit 5
B1	INT: mux CELL.LONG_V[1] bit 3	INT: mux CELL.LONG_V[1] bit 0	INT: mux CELL.LONG_V[1] bit 2	INT: mux CELL.LONG_V[2] bit 1	INT: mux CELL.LONG_V[2] bit 3	INT: mux CELL.LONG_V[2] bit 2	INT: mux CELL.LONG_V[0] bit 1	INT: mux CELL.LONG_V[0] bit 0	INT: mux CELL.LONG_V[0] bit 2	INT: mux CELL.LONG_V[0] bit 3	INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_IO_SN_I1[0]	INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[3]	INT: mux CELL.IMUX_IO_OK[0] bit 7	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.IMUX_IO_IK[0] bit 4	INT: mux CELL.IMUX_IO_IK[0] bit 5	INT: mux CELL.IMUX_IO_IK[0] bit 6	INT: mux CELL.IMUX_IO_IK[0] bit 7	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 0	INT: mux CELL.IMUX_IO_IK[1] bit 7	INT: mux CELL.IMUX_IO_OK[1] bit 2	INT: mux CELL.IMUX_IO_OK[1] bit 1	INT: mux CELL.IMUX_IO_OK[1] bit 0	INT: mux CELL.IMUX_IO_OK[1] bit 7	INT: mux CELL.LONG_V[5] bit 1	INT: mux CELL.LONG_V[5] bit 3	INT: mux CELL.LONG_V[3] bit 0	INT: mux CELL.LONG_V[3] bit 3	INT: mux CELL.LONG_V[4] bit 3	INT: mux CELL.LONG_IO_H[3] bit 1	-	INT: mux CELL.LONG_V[4] bit 0	-	-
B0	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.LONG_V[1] bit 1	INT: mux CELL.LONG_V[2] bit 0	INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_IO_SN_I2[0]	INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1	INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_IO_SN_I2[0]	INT: mux CELL.IMUX_IO_OK[0] bit 6	INT: mux CELL.IMUX_IO_OK[0] bit 5	INT: mux CELL.IMUX_IO_OK[0] bit 4	INT: mux CELL.IMUX_IO_OK[0] bit 0	INT: mux CELL.IMUX_IO_OK[0] bit 1	INT: mux CELL.IMUX_IO_OK[0] bit 3	INT: mux CELL.IMUX_IO_OK[0] bit 2	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_IO_SN_I2[0]	INT: mux CELL.IMUX_IO_IK[0] bit 0	INT: mux CELL.IMUX_IO_IK[0] bit 1	INT: mux CELL.IMUX_IO_IK[0] bit 3	INT: mux CELL.IMUX_IO_IK[0] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 5	INT: mux CELL.IMUX_IO_IK[1] bit 6	INT: mux CELL.IMUX_IO_IK[1] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 3	INT: mux CELL.IMUX_IO_OK[1] bit 5	INT: mux CELL.IMUX_IO_OK[1] bit 6	INT: mux CELL.IMUX_IO_OK[1] bit 4	INT: mux CELL.IMUX_IO_OK[1] bit 3	INT: mux CELL.LONG_V[5] bit 0	INT: mux CELL.LONG_V[5] bit 2	INT: mux CELL.LONG_V[3] bit 1	INT: mux CELL.LONG_V[3] bit 2	-	INT: mux CELL.LONG_IO_H[0] bit 1	-	INT: mux CELL.LONG_V[4] bit 1	INT: mux CELL.LONG_V[4] bit 2	-

xc4000h IO_N1_W rect MAIN_S
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B9	-	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1]	-	-	-	INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2]	-	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0]	-	INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

xc4000h IO_N1_W rect MAIN_E
Bit	Frame
Bit	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

xc4000h IO_N1_W rect MAIN_W
Bit	Frame
Bit	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

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