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Corners

Tile CNR.BL

Cells: 2

Switchbox INT

xc4000h CNR.BL switchbox INT
DestinationSourceKind
TCELL0_SINGLE.H0TCELL0_DEC.V3pass transistor
TCELL0_OUT.LR.IOB1.I2.Spass transistor
TCELL0_IO.DOUBLE.0.S.0bidirectional pass transistor
TCELL0_IO.DOUBLE.0.W.2bidirectional pass transistor
TCELL0_SINGLE.H1TCELL0_LONG.IO.V0pass transistor
TCELL0_OUT.RDBK.DATApass transistor
TCELL0_IO.DOUBLE.0.W.1bidirectional pass transistor
TCELL0_SINGLE.H2TCELL0_LONG.IO.V1pass transistor
TCELL0_OUT.MD0.Ipass transistor
TCELL0_IO.DOUBLE.1.S.0bidirectional pass transistor
TCELL0_IO.DOUBLE.1.W.2bidirectional pass transistor
TCELL0_SINGLE.H3TCELL0_DEC.V2pass transistor
TCELL0_OUT.LR.IOB1.I1.Spass transistor
TCELL0_IO.DOUBLE.1.W.1bidirectional pass transistor
TCELL0_SINGLE.H4TCELL0_DEC.V1pass transistor
TCELL0_OUT.LR.IOB1.I2.Spass transistor
TCELL0_IO.DOUBLE.2.S.0bidirectional pass transistor
TCELL0_IO.DOUBLE.2.W.2bidirectional pass transistor
TCELL0_SINGLE.H5TCELL0_LONG.IO.V2pass transistor
TCELL0_OUT.RDBK.DATApass transistor
TCELL0_IO.DOUBLE.2.W.1bidirectional pass transistor
TCELL0_SINGLE.H6TCELL0_LONG.IO.V3pass transistor
TCELL0_OUT.MD0.Ipass transistor
TCELL0_IO.DOUBLE.3.S.0bidirectional pass transistor
TCELL0_IO.DOUBLE.3.W.2bidirectional pass transistor
TCELL0_SINGLE.H7TCELL0_DEC.V0pass transistor
TCELL0_OUT.LR.IOB1.I1.Spass transistor
TCELL0_IO.DOUBLE.3.W.1bidirectional pass transistor
TCELL0_DOUBLE.H0.0TCELL0_OUT.LR.IOB1.I1.Spass transistor
TCELL0_IO.DOUBLE.0.S.0bidirectional pass transistor
TCELL0_IO.DOUBLE.0.W.1bidirectional pass transistor
TCELL0_IO.DOUBLE.0.W.2bidirectional pass transistor
TCELL0_DOUBLE.H0.1TCELL0_OUT.MD0.Ipass transistor
TCELL0_IO.DOUBLE.1.S.0bidirectional pass transistor
TCELL0_IO.DOUBLE.1.W.1bidirectional pass transistor
TCELL0_IO.DOUBLE.1.W.2bidirectional pass transistor
TCELL0_DOUBLE.H1.0TCELL0_OUT.RDBK.DATApass transistor
TCELL0_IO.DOUBLE.3.S.0bidirectional pass transistor
TCELL0_IO.DOUBLE.3.W.1bidirectional pass transistor
TCELL0_IO.DOUBLE.3.W.2bidirectional pass transistor
TCELL0_DOUBLE.H1.1TCELL0_OUT.LR.IOB1.I2.Spass transistor
TCELL0_IO.DOUBLE.2.S.0bidirectional pass transistor
TCELL0_IO.DOUBLE.2.W.1bidirectional pass transistor
TCELL0_IO.DOUBLE.2.W.2bidirectional pass transistor
TCELL0_IO.DOUBLE.0.S.0TCELL0_IO.DBUF.V1pass transistor
TCELL0_SINGLE.H0bidirectional pass transistor
TCELL0_DOUBLE.H0.0bidirectional pass transistor
TCELL0_IO.DOUBLE.0.W.2bidirectional pass transistor
TCELL0_IO.DOUBLE.0.W.1TCELL0_SINGLE.H1bidirectional pass transistor
TCELL0_DOUBLE.H0.0bidirectional pass transistor
TCELL0_IO.DOUBLE.0.W.2TCELL0_IO.DBUF.V0pass transistor
TCELL0_SINGLE.H0bidirectional pass transistor
TCELL0_DOUBLE.H0.0bidirectional pass transistor
TCELL0_IO.DOUBLE.0.S.0bidirectional pass transistor
TCELL0_IO.DOUBLE.1.S.0TCELL0_IO.DBUF.V1pass transistor
TCELL0_SINGLE.H2bidirectional pass transistor
TCELL0_DOUBLE.H0.1bidirectional pass transistor
TCELL0_IO.DOUBLE.1.W.2bidirectional pass transistor
TCELL0_IO.DOUBLE.1.W.1TCELL0_SINGLE.H3bidirectional pass transistor
TCELL0_DOUBLE.H0.1bidirectional pass transistor
TCELL0_IO.DOUBLE.1.W.2TCELL0_IO.DBUF.V0pass transistor
TCELL0_SINGLE.H2bidirectional pass transistor
TCELL0_DOUBLE.H0.1bidirectional pass transistor
TCELL0_IO.DOUBLE.1.S.0bidirectional pass transistor
TCELL0_IO.DOUBLE.2.S.0TCELL0_IO.DBUF.V1pass transistor
TCELL0_SINGLE.H4bidirectional pass transistor
TCELL0_DOUBLE.H1.1bidirectional pass transistor
TCELL0_IO.DOUBLE.2.W.2bidirectional pass transistor
TCELL0_IO.DOUBLE.2.W.1TCELL0_SINGLE.H5bidirectional pass transistor
TCELL0_DOUBLE.H1.1bidirectional pass transistor
TCELL0_IO.DOUBLE.2.W.2TCELL0_IO.DBUF.V0pass transistor
TCELL0_SINGLE.H4bidirectional pass transistor
TCELL0_DOUBLE.H1.1bidirectional pass transistor
TCELL0_IO.DOUBLE.2.S.0bidirectional pass transistor
TCELL0_IO.DOUBLE.3.S.0TCELL0_IO.DBUF.V1pass transistor
TCELL0_SINGLE.H6bidirectional pass transistor
TCELL0_DOUBLE.H1.0bidirectional pass transistor
TCELL0_IO.DOUBLE.3.W.2bidirectional pass transistor
TCELL0_IO.DOUBLE.3.W.1TCELL0_SINGLE.H7bidirectional pass transistor
TCELL0_DOUBLE.H1.0bidirectional pass transistor
TCELL0_IO.DOUBLE.3.W.2TCELL0_IO.DBUF.V0pass transistor
TCELL0_SINGLE.H6bidirectional pass transistor
TCELL0_DOUBLE.H1.0bidirectional pass transistor
TCELL0_IO.DOUBLE.3.S.0bidirectional pass transistor
TCELL0_IO.DBUF.V0TCELL0_IO.DOUBLE.0.S.0mux
TCELL0_IO.DOUBLE.1.S.0mux
TCELL0_IO.DOUBLE.2.S.0mux
TCELL0_IO.DOUBLE.3.S.0mux
TCELL0_IO.DBUF.V1TCELL0_IO.DOUBLE.0.W.2mux
TCELL0_IO.DOUBLE.1.W.2mux
TCELL0_IO.DOUBLE.2.W.2mux
TCELL0_IO.DOUBLE.3.W.2mux
TCELL0_LONG.H3TCELL0_LONG.IO.V1mux
TCELL0_DEC.V1mux
TCELL0_LONG.H4TCELL0_LONG.IO.V2mux
TCELL0_DEC.V2mux
TCELL0_OUT.RDBK.DATAmux
TCELL0_LONG.H5TCELL0_LONG.IO.V3mux
TCELL0_DEC.V3mux
TCELL0_OUT.RDBK.DATAmux
TCELL0_LONG.IO.H0TCELL0_LONG.IO.V0mux
TCELL0_LONG.IO.V2mux
TCELL0_LONG.IO.H1TCELL0_LONG.IO.V1mux
TCELL0_LONG.IO.V3mux
TCELL0_LONG.IO.H2TCELL0_LONG.IO.V0mux
TCELL0_LONG.IO.V2mux
TCELL0_LONG.IO.H3TCELL0_LONG.IO.V1mux
TCELL0_LONG.IO.V3mux
TCELL0_LONG.IO.V0TCELL0_SINGLE.H1mux
TCELL0_LONG.IO.H0mux
TCELL0_LONG.IO.H2mux
TCELL0_LONG.IO.V1TCELL0_SINGLE.H2mux
TCELL0_LONG.H3mux
TCELL0_LONG.IO.H1mux
TCELL0_LONG.IO.H3mux
TCELL0_LONG.IO.V2TCELL0_SINGLE.H5mux
TCELL0_LONG.H4mux
TCELL0_LONG.IO.H0mux
TCELL0_LONG.IO.H2mux
TCELL0_LONG.IO.V3TCELL0_SINGLE.H6mux
TCELL0_LONG.H5mux
TCELL0_LONG.IO.H1mux
TCELL0_LONG.IO.H3mux
TCELL0_IMUX.IOB1.O1TCELL0_SINGLE.H2mux
TCELL0_SINGLE.H3mux
TCELL0_SINGLE.H4mux
TCELL0_SINGLE.H5mux
TCELL1_DOUBLE.V0.1mux
TCELL1_DOUBLE.V1.0mux
TCELL1_LONG.V0mux
TCELL1_LONG.V1mux
TCELL1_LONG.V2mux
TCELL0_IMUX.IOB1.IKTCELL0_DOUBLE.H0.0mux
TCELL0_DOUBLE.H1.1mux
TCELL0_LONG.H3mux
TCELL0_LONG.H4mux
TCELL0_LONG.H5mux
TCELL1_SINGLE.V2mux
TCELL1_SINGLE.V3mux
TCELL1_SINGLE.V4mux
TCELL1_SINGLE.V5mux
TCELL0_IMUX.BUFG.HTCELL0_OUT.IOB.CLKIN.Wmux
TCELL0_IMUX.BUFG.VTCELL0_IO.DOUBLE.0.S.0mux
TCELL0_IO.DOUBLE.0.W.1mux
TCELL0_IO.DOUBLE.1.S.0mux
TCELL0_IO.DOUBLE.1.W.1mux
TCELL0_IO.DOUBLE.2.S.0mux
TCELL0_IO.DOUBLE.2.W.1mux
TCELL0_IO.DOUBLE.3.S.0mux
TCELL0_IO.DOUBLE.3.W.1mux
TCELL0_OUT.IOB.CLKIN.Smux
TCELL0_IMUX.RDBK.TRIGTCELL0_SINGLE.H2mux
TCELL0_SINGLE.H3mux
TCELL0_SINGLE.H4mux
TCELL0_SINGLE.H5mux

Bel PULLUP_DEC0_H

xc4000h CNR.BL bel PULLUP_DEC0_H
PinDirectionWires
OoutputTCELL0:DEC.H0

Bel PULLUP_DEC1_H

xc4000h CNR.BL bel PULLUP_DEC1_H
PinDirectionWires
OoutputTCELL0:DEC.H1

Bel PULLUP_DEC2_H

xc4000h CNR.BL bel PULLUP_DEC2_H
PinDirectionWires
OoutputTCELL0:DEC.H2

Bel PULLUP_DEC3_H

xc4000h CNR.BL bel PULLUP_DEC3_H
PinDirectionWires
OoutputTCELL0:DEC.H3

Bel PULLUP_DEC0_V

xc4000h CNR.BL bel PULLUP_DEC0_V
PinDirectionWires
OoutputTCELL0:DEC.V0

Bel PULLUP_DEC1_V

xc4000h CNR.BL bel PULLUP_DEC1_V
PinDirectionWires
OoutputTCELL0:DEC.V1

Bel PULLUP_DEC2_V

xc4000h CNR.BL bel PULLUP_DEC2_V
PinDirectionWires
OoutputTCELL0:DEC.V2

Bel PULLUP_DEC3_V

xc4000h CNR.BL bel PULLUP_DEC3_V
PinDirectionWires
OoutputTCELL0:DEC.V3

Bel BUFGLS_H

xc4000h CNR.BL bel BUFGLS_H
PinDirectionWires
IinputTCELL0:IMUX.BUFG.H

Bel BUFGLS_V

xc4000h CNR.BL bel BUFGLS_V
PinDirectionWires
IinputTCELL0:IMUX.BUFG.V

Bel CIN

xc4000h CNR.BL bel CIN
PinDirectionWires

Bel MD0

xc4000h CNR.BL bel MD0
PinDirectionWires
IoutputTCELL0:OUT.MD0.I

Bel MD1

xc4000h CNR.BL bel MD1
PinDirectionWires
OinputTCELL0:IMUX.IOB1.O1
TinputTCELL0:IMUX.IOB1.IK

Bel MD2

xc4000h CNR.BL bel MD2
PinDirectionWires
IoutputTCELL0:OUT.BT.IOB1.I1

Bel RDBK

xc4000h CNR.BL bel RDBK
PinDirectionWires
DATAoutputTCELL0:OUT.RDBK.DATA
RIPoutputTCELL0:OUT.BT.IOB1.I2
TRIGinputTCELL0:IMUX.RDBK.TRIG

Bel wires

xc4000h CNR.BL bel wires
WirePins
TCELL0:DEC.H0PULLUP_DEC0_H.O
TCELL0:DEC.H1PULLUP_DEC1_H.O
TCELL0:DEC.H2PULLUP_DEC2_H.O
TCELL0:DEC.H3PULLUP_DEC3_H.O
TCELL0:DEC.V0PULLUP_DEC0_V.O
TCELL0:DEC.V1PULLUP_DEC1_V.O
TCELL0:DEC.V2PULLUP_DEC2_V.O
TCELL0:DEC.V3PULLUP_DEC3_V.O
TCELL0:IMUX.IOB1.O1MD1.O
TCELL0:IMUX.IOB1.IKMD1.T
TCELL0:IMUX.BUFG.HBUFGLS_H.I
TCELL0:IMUX.BUFG.VBUFGLS_V.I
TCELL0:IMUX.RDBK.TRIGRDBK.TRIG
TCELL0:OUT.BT.IOB1.I1MD2.I
TCELL0:OUT.BT.IOB1.I2RDBK.RIP
TCELL0:OUT.MD0.IMD0.I
TCELL0:OUT.RDBK.DATARDBK.DATA

Bitstream

xc4000h CNR.BL bittile 0
BitFrame
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
12 - - - - - - - - - ~INT:PASS.SINGLE.H3.0.DEC.V2 ~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.0 ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.S.0 ~INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.W.1 ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.1 ~INT:BIPASS.IO.DOUBLE.1.S.0.IO.DOUBLE.1.W.2 ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.2 ~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.W.2 ~INT:PASS.SINGLE.H7.0.DEC.V0 - ~INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.S.0 ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.S.0 ~INT:BIPASS.SINGLE.H7.IO.DOUBLE.3.W.1 ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.W.1 ~INT:BIPASS.IO.DOUBLE.3.S.0.IO.DOUBLE.3.W.2 ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.W.2 ~INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.W.2
11 MD1:PULL[1] MD1:PULL[0] ~PULLUP_DEC3_V:ENABLE ~PULLUP_DEC1_V:ENABLE ~PULLUP_DEC0_V:ENABLE ~PULLUP_DEC2_V:ENABLE - - INT:MUX.IO.DBUF.V1[2] INT:MUX.IO.DBUF.V1[1] INT:MUX.IO.DBUF.V1[0] INT:MUX.IO.DBUF.V1[3] - - - ~INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S ~INT:PASS.IO.DOUBLE.1.W.2.0.IO.DBUF.V0 - - - ~INT:PASS.DOUBLE.H0.1.0.OUT.MD0.I ~INT:PASS.SINGLE.H6.0.LONG.IO.V3 - - ~INT:PASS.SINGLE.H6.0.OUT.MD0.I ~INT:PASS.SINGLE.H7.0.OUT.LR.IOB1.I1.S
10 - ~MD1:ENABLE.T ~MD1:ENABLE.O - - - - - - - INT:MUX.LONG.H3[0] - - ~INT:PASS.SINGLE.H2.0.LONG.IO.V1 - INT:MUX.LONG.H5[3] INT:MUX.LONG.H5[0] ~INT:PASS.IO.DOUBLE.3.W.2.0.IO.DBUF.V0 - INT:MUX.LONG.H5[1] - ~INT:PASS.SINGLE.H2.0.OUT.MD0.I INT:MUX.LONG.H4[1] ~INT:PASS.DOUBLE.H0.0.0.OUT.LR.IOB1.I1.S INT:MUX.LONG.H4[0] -
9 - - - - - - - - - - - - INT:MUX.LONG.H3[1] - - ~INT:PASS.IO.DOUBLE.1.S.0.0.IO.DBUF.V1 - ~INT:PASS.IO.DOUBLE.2.W.2.0.IO.DBUF.V0 - ~INT:PASS.IO.DOUBLE.0.W.2.0.IO.DBUF.V0 INT:MUX.LONG.H5[2] - ~INT:PASS.IO.DOUBLE.3.S.0.0.IO.DBUF.V1 ~INT:PASS.DOUBLE.H1.0.0.OUT.RDBK.DATA INT:MUX.LONG.H4[3] INT:MUX.LONG.H4[2]
8 - - - - - - - - - - - ~INT:PASS.SINGLE.H4.0.DEC.V1 ~INT:PASS.IO.DOUBLE.2.S.0.0.IO.DBUF.V1 ~INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.S.0 ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.S.0 ~INT:PASS.IO.DOUBLE.0.S.0.0.IO.DBUF.V1 ~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.0 ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.S.0 - ~INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.W.1 ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.1 - ~INT:BIPASS.IO.DOUBLE.0.S.0.IO.DOUBLE.0.W.2 ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.2 - ~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.W.2
7 - - - - - - - - - - - - ~INT:BIPASS.SINGLE.H5.IO.DOUBLE.2.W.1 ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.W.1 ~INT:BIPASS.IO.DOUBLE.2.S.0.IO.DOUBLE.2.W.2 ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.W.2 ~INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.W.2 ~INT:PASS.SINGLE.H0.0.DEC.V3 - ~INT:PASS.SINGLE.H5.0.LONG.IO.V2 ~INT:PASS.SINGLE.H5.0.OUT.RDBK.DATA ~INT:PASS.SINGLE.H1.0.OUT.RDBK.DATA ~INT:PASS.SINGLE.H1.0.LONG.IO.V0 ~INT:PASS.DOUBLE.H1.1.0.OUT.LR.IOB1.I2.S ~INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S ~INT:PASS.SINGLE.H4.0.OUT.LR.IOB1.I2.S
6 - - - - - - - - - - - - - INT:MUX.IO.DBUF.V0[1] INT:MUX.IO.DBUF.V0[0] INT:MUX.IO.DBUF.V0[2] INT:MUX.IO.DBUF.V0[3] - - - - - - INT:MUX.IMUX.IOB1.IK[5] INT:MUX.IMUX.IOB1.IK[1] INT:MUX.IMUX.IOB1.IK[4]
5 - - - - - - - - - - - - - - - - - - - - INT:MUX.LONG.IO.V3[4] INT:MUX.LONG.IO.V2[4] INT:MUX.IMUX.IOB1.IK[0] INT:MUX.IMUX.IOB1.IK[2] INT:MUX.IMUX.IOB1.IK[3] -
4 - - ~RDBK:ENABLE INT:MUX.LONG.IO.V0[3] INT:MUX.LONG.IO.V0[1] INT:MUX.LONG.IO.V0[0] INT:MUX.LONG.IO.V0[2] INT:MUX.IMUX.RDBK.TRIG[0] INT:MUX.IMUX.RDBK.TRIG[1] INT:MUX.LONG.IO.V1[0] INT:MUX.LONG.IO.V1[2] INT:MUX.LONG.IO.V1[1] INT:MUX.LONG.IO.V1[4] INT:MUX.LONG.IO.V1[3] INT:MUX.LONG.IO.V3[0] INT:MUX.LONG.IO.V3[2] INT:MUX.LONG.IO.V3[1] INT:MUX.LONG.IO.V3[3] INT:MUX.IMUX.IOB1.O1[0] INT:MUX.IMUX.IOB1.O1[1] INT:MUX.IMUX.IOB1.O1[3] INT:MUX.IMUX.IOB1.O1[5] INT:MUX.LONG.IO.V2[0] INT:MUX.LONG.IO.V2[2] INT:MUX.LONG.IO.V2[1] INT:MUX.LONG.IO.V2[3]
3 - - - INT:MUX.IMUX.BUFG.H[0] INT:MUX.LONG.IO.H1[0] - INT:MUX.LONG.IO.H1[1] - INT:MUX.LONG.IO.H3[1] INT:MUX.LONG.IO.H3[0] ~MISC:READ_ABORT INT:MUX.LONG.IO.H0[0] ~MISC:READ_CAPTURE INT:MUX.LONG.IO.H0[1] - INT:MUX.LONG.IO.H2[1] INT:MUX.LONG.IO.H2[0] - ~MISC:TM_BOT INT:MUX.IMUX.RDBK.TRIG[2] INT:MUX.IMUX.RDBK.TRIG[3] INT:MUX.IMUX.IOB1.O1[2] ~PULLUP_DEC3_H:ENABLE ~PULLUP_DEC2_H:ENABLE ~PULLUP_DEC1_H:ENABLE ~PULLUP_DEC0_H:ENABLE
2 - - - - - - - - - - - - - - - - - - - - - INT:MUX.IMUX.IOB1.O1[4] INT:MUX.IMUX.BUFG.V[0] INT:MUX.IMUX.BUFG.V[6] INT:MUX.IMUX.BUFG.V[3] INT:MUX.IMUX.BUFG.V[4]
1 - - - - - - - - - - - - - - - - - - - - - - - INT:MUX.IMUX.BUFG.V[5] INT:MUX.IMUX.BUFG.V[2] INT:MUX.IMUX.BUFG.V[1]
0 - - - - - - - - - - - - - - - - - - - - - - - - - -
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.S.0 0.8.8
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.1 0.5.8
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.0.W.2 0.2.8
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.S.0 0.14.12
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.1 0.12.12
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.1.W.2 0.10.12
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.S.0 0.5.12
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.W.1 0.3.12
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.3.W.2 0.1.12
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.S.0 0.11.8
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.W.1 0.12.7
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.2.W.2 0.10.7
INT:BIPASS.IO.DOUBLE.0.S.0.IO.DOUBLE.0.W.2 0.3.8
INT:BIPASS.IO.DOUBLE.1.S.0.IO.DOUBLE.1.W.2 0.11.12
INT:BIPASS.IO.DOUBLE.2.S.0.IO.DOUBLE.2.W.2 0.11.7
INT:BIPASS.IO.DOUBLE.3.S.0.IO.DOUBLE.3.W.2 0.2.12
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.0 0.9.8
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.W.2 0.0.8
INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.W.1 0.6.8
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.0 0.15.12
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.W.2 0.9.12
INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.W.1 0.13.12
INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.S.0 0.12.8
INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.W.2 0.9.7
INT:BIPASS.SINGLE.H5.IO.DOUBLE.2.W.1 0.13.7
INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.S.0 0.6.12
INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.W.2 0.0.12
INT:BIPASS.SINGLE.H7.IO.DOUBLE.3.W.1 0.4.12
INT:PASS.DOUBLE.H0.0.0.OUT.LR.IOB1.I1.S 0.2.10
INT:PASS.DOUBLE.H0.1.0.OUT.MD0.I 0.5.11
INT:PASS.DOUBLE.H1.0.0.OUT.RDBK.DATA 0.2.9
INT:PASS.DOUBLE.H1.1.0.OUT.LR.IOB1.I2.S 0.2.7
INT:PASS.IO.DOUBLE.0.S.0.0.IO.DBUF.V1 0.10.8
INT:PASS.IO.DOUBLE.0.W.2.0.IO.DBUF.V0 0.6.9
INT:PASS.IO.DOUBLE.1.S.0.0.IO.DBUF.V1 0.10.9
INT:PASS.IO.DOUBLE.1.W.2.0.IO.DBUF.V0 0.9.11
INT:PASS.IO.DOUBLE.2.S.0.0.IO.DBUF.V1 0.13.8
INT:PASS.IO.DOUBLE.2.W.2.0.IO.DBUF.V0 0.8.9
INT:PASS.IO.DOUBLE.3.S.0.0.IO.DBUF.V1 0.3.9
INT:PASS.IO.DOUBLE.3.W.2.0.IO.DBUF.V0 0.8.10
INT:PASS.SINGLE.H0.0.DEC.V3 0.8.7
INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S 0.1.7
INT:PASS.SINGLE.H1.0.LONG.IO.V0 0.3.7
INT:PASS.SINGLE.H1.0.OUT.RDBK.DATA 0.4.7
INT:PASS.SINGLE.H2.0.LONG.IO.V1 0.12.10
INT:PASS.SINGLE.H2.0.OUT.MD0.I 0.4.10
INT:PASS.SINGLE.H3.0.DEC.V2 0.16.12
INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S 0.10.11
INT:PASS.SINGLE.H4.0.DEC.V1 0.14.8
INT:PASS.SINGLE.H4.0.OUT.LR.IOB1.I2.S 0.0.7
INT:PASS.SINGLE.H5.0.LONG.IO.V2 0.6.7
INT:PASS.SINGLE.H5.0.OUT.RDBK.DATA 0.5.7
INT:PASS.SINGLE.H6.0.LONG.IO.V3 0.4.11
INT:PASS.SINGLE.H6.0.OUT.MD0.I 0.1.11
INT:PASS.SINGLE.H7.0.DEC.V0 0.8.12
INT:PASS.SINGLE.H7.0.OUT.LR.IOB1.I1.S 0.0.11
MD1:ENABLE.O 0.23.10
MD1:ENABLE.T 0.24.10
MISC:READ_ABORT 0.15.3
MISC:READ_CAPTURE 0.13.3
MISC:TM_BOT 0.7.3
PULLUP_DEC0_H:ENABLE 0.0.3
PULLUP_DEC0_V:ENABLE 0.21.11
PULLUP_DEC1_H:ENABLE 0.1.3
PULLUP_DEC1_V:ENABLE 0.22.11
PULLUP_DEC2_H:ENABLE 0.2.3
PULLUP_DEC2_V:ENABLE 0.20.11
PULLUP_DEC3_H:ENABLE 0.3.3
PULLUP_DEC3_V:ENABLE 0.23.11
RDBK:ENABLE 0.23.4
inverted ~[0]
INT:MUX.IMUX.BUFG.H 0.22.3
0.OUT.IOB.CLKIN.W 0
NONE 1
INT:MUX.IMUX.BUFG.V 0.2.2 0.2.1 0.0.2 0.1.2 0.1.1 0.0.1 0.3.2
0.IO.DOUBLE.0.S.0 0 0 0 0 1 1 1
0.IO.DOUBLE.1.S.0 0 0 0 1 0 1 1
0.IO.DOUBLE.2.S.0 0 0 0 1 1 0 1
0.IO.DOUBLE.0.W.1 0 0 1 1 1 1 1
0.IO.DOUBLE.2.W.1 0 1 0 0 1 1 1
0.IO.DOUBLE.3.S.0 0 1 0 1 0 1 1
0.IO.DOUBLE.3.W.1 0 1 0 1 1 0 1
0.IO.DOUBLE.1.W.1 0 1 1 1 1 1 1
0.OUT.IOB.CLKIN.S 1 1 0 1 1 1 0
NONE 1 1 0 1 1 1 1
INT:MUX.IMUX.IOB1.IK 0.2.6 0.0.6 0.1.5 0.2.5 0.1.6 0.3.5
0.LONG.H3 0 0 0 1 1 1
0.LONG.H4 0 0 1 0 1 1
0.LONG.H5 0 0 1 1 0 1
0.DOUBLE.H0.0 0 1 1 1 1 1
1.SINGLE.V2 1 0 0 1 1 1
1.SINGLE.V3 1 0 1 0 1 1
1.SINGLE.V4 1 0 1 1 0 1
1.SINGLE.V5 1 0 1 1 1 0
0.DOUBLE.H1.1 1 1 1 1 1 1
INT:MUX.IMUX.IOB1.O1 0.4.4 0.4.2 0.5.4 0.4.3 0.6.4 0.7.4
1.LONG.V0 0 0 1 1 1 0
0.SINGLE.H2 0 0 1 1 1 1
1.LONG.V1 0 1 0 1 1 0
0.SINGLE.H3 0 1 0 1 1 1
1.LONG.V2 0 1 1 0 1 0
0.SINGLE.H4 0 1 1 0 1 1
0.SINGLE.H5 0 1 1 1 0 1
1.DOUBLE.V1.0 1 1 1 1 1 0
1.DOUBLE.V0.1 1 1 1 1 1 1
INT:MUX.IMUX.RDBK.TRIG 0.5.3 0.6.3 0.17.4 0.18.4
0.SINGLE.H3 0 0 1 1
0.SINGLE.H4 0 1 0 1
0.SINGLE.H5 0 1 1 0
0.SINGLE.H2 1 1 1 1
INT:MUX.IO.DBUF.V0 0.9.6 0.10.6 0.12.6 0.11.6
0.IO.DOUBLE.1.S.0 0 0 1 1
0.IO.DOUBLE.2.S.0 0 1 0 1
0.IO.DOUBLE.3.S.0 0 1 1 0
0.IO.DOUBLE.0.S.0 1 1 1 1
INT:MUX.IO.DBUF.V1 0.14.11 0.17.11 0.16.11 0.15.11
0.IO.DOUBLE.0.W.2 0 0 1 1
0.IO.DOUBLE.1.W.2 0 1 0 1
0.IO.DOUBLE.3.W.2 0 1 1 0
0.IO.DOUBLE.2.W.2 1 1 1 1
INT:MUX.LONG.H3 0.13.9 0.15.10
0.DEC.V1 0 0
0.LONG.IO.V1 0 1
NONE 1 1
INT:MUX.LONG.H4 0.1.9 0.0.9 0.3.10 0.1.10
0.LONG.IO.V2 0 0 0 1
0.DEC.V2 0 0 1 0
0.OUT.RDBK.DATA 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.H5 0.10.10 0.5.9 0.6.10 0.9.10
0.LONG.IO.V3 0 0 0 1
0.DEC.V3 0 0 1 0
0.OUT.RDBK.DATA 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.H0 0.12.3 0.14.3
0.LONG.IO.V2 0 0
0.LONG.IO.V0 0 1
NONE 1 1
INT:MUX.LONG.IO.H1 0.19.3 0.21.3
0.LONG.IO.V3 0 0
0.LONG.IO.V1 0 1
NONE 1 1
INT:MUX.LONG.IO.H2 0.10.3 0.9.3
0.LONG.IO.V0 0 0
0.LONG.IO.V2 0 1
NONE 1 1
INT:MUX.LONG.IO.H3 0.17.3 0.16.3
0.LONG.IO.V1 0 0
0.LONG.IO.V3 0 1
NONE 1 1
INT:MUX.LONG.IO.V0 0.22.4 0.19.4 0.21.4 0.20.4
0.LONG.IO.H0 0 0 0 1
0.LONG.IO.H2 0 0 1 0
0.SINGLE.H1 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.V1 0.13.4 0.12.4 0.15.4 0.14.4 0.16.4
0.LONG.H3 0 0 0 1 1
0.LONG.IO.H1 0 0 1 0 1
0.LONG.IO.H3 0 0 1 1 0
0.SINGLE.H2 0 1 1 1 1
NONE 1 1 1 1 1
INT:MUX.LONG.IO.V2 0.4.5 0.0.4 0.2.4 0.1.4 0.3.4
0.LONG.H4 0 0 0 1 1
0.LONG.IO.H0 0 0 1 0 1
0.LONG.IO.H2 0 0 1 1 0
0.SINGLE.H5 0 1 1 1 1
NONE 1 1 1 1 1
INT:MUX.LONG.IO.V3 0.5.5 0.8.4 0.10.4 0.9.4 0.11.4
0.LONG.H5 0 0 0 1 1
0.LONG.IO.H1 0 0 1 0 1
0.LONG.IO.H3 0 0 1 1 0
0.SINGLE.H6 0 1 1 1 1
NONE 1 1 1 1 1
MD1:PULL 0.25.11 0.24.11
PULLUP 0 1
PULLDOWN 1 0
PULLNONE 1 1

Tile CNR.TL

Cells: 4

Switchbox INT

xc4000h CNR.TL switchbox INT
DestinationSourceKind
TCELL0_LONG.H0TCELL0_LONG.IO.V0mux
TCELL0_DEC.V0mux
TCELL0_OUT.LR.IOB1.I2mux
TCELL0_LONG.H1TCELL0_LONG.IO.V1mux
TCELL0_DEC.V1mux
TCELL0_OUT.LR.IOB1.I2mux
TCELL0_LONG.H2TCELL0_LONG.IO.V2mux
TCELL0_DEC.V2mux
TCELL0_LONG.IO.H0TCELL0_LONG.IO.V0mux
TCELL0_LONG.IO.V2mux
TCELL0_LONG.IO.H1TCELL0_LONG.IO.V1mux
TCELL0_LONG.IO.V3mux
TCELL0_LONG.IO.H2TCELL0_LONG.IO.V0mux
TCELL0_LONG.IO.V2mux
TCELL0_LONG.IO.H3TCELL0_LONG.IO.V1mux
TCELL0_LONG.IO.V3mux
TCELL0_LONG.IO.V0TCELL0_LONG.H0mux
TCELL0_LONG.IO.H0mux
TCELL0_LONG.IO.H2mux
TCELL0_LONG.IO.V1TCELL0_LONG.H1mux
TCELL0_LONG.IO.H1mux
TCELL0_LONG.IO.H3mux
TCELL0_LONG.IO.V2TCELL0_LONG.H2mux
TCELL0_LONG.IO.H0mux
TCELL0_LONG.IO.H2mux
TCELL0_LONG.IO.V3TCELL0_LONG.IO.H1mux
TCELL0_LONG.IO.H3mux
TCELL0_IMUX.BUFG.HTCELL0_IO.DOUBLE.0.W.0mux
TCELL0_IO.DOUBLE.0.W.1mux
TCELL0_IO.DOUBLE.1.W.0mux
TCELL0_IO.DOUBLE.1.W.1mux
TCELL0_IO.DOUBLE.2.W.0mux
TCELL0_IO.DOUBLE.2.W.1mux
TCELL0_IO.DOUBLE.3.W.0mux
TCELL0_IO.DOUBLE.3.W.1mux
TCELL0_OUT.IOB.CLKIN.Wmux
TCELL0_IMUX.BUFG.VTCELL0_OUT.IOB.CLKIN.Nmux
TCELL0_IMUX.BSCAN.TDO1TCELL1_DOUBLE.V0.1mux
TCELL1_DOUBLE.V1.0mux
TCELL1_LONG.V0mux
TCELL1_LONG.V1mux
TCELL1_LONG.V2mux
TCELL2_SINGLE.H2mux
TCELL2_SINGLE.H3mux
TCELL2_SINGLE.H4mux
TCELL2_SINGLE.H5mux
TCELL0_IMUX.BSCAN.TDO2TCELL0_LONG.H0mux
TCELL0_LONG.H1mux
TCELL0_LONG.H2mux
TCELL1_SINGLE.V2mux
TCELL1_SINGLE.V3mux
TCELL1_SINGLE.V4mux
TCELL1_SINGLE.V5mux
TCELL2_DOUBLE.H0.1mux
TCELL2_DOUBLE.H1.0mux

Bel PULLUP_DEC0_H

xc4000h CNR.TL bel PULLUP_DEC0_H
PinDirectionWires
OoutputTCELL0:DEC.H0

Bel PULLUP_DEC1_H

xc4000h CNR.TL bel PULLUP_DEC1_H
PinDirectionWires
OoutputTCELL0:DEC.H1

Bel PULLUP_DEC2_H

xc4000h CNR.TL bel PULLUP_DEC2_H
PinDirectionWires
OoutputTCELL0:DEC.H2

Bel PULLUP_DEC3_H

xc4000h CNR.TL bel PULLUP_DEC3_H
PinDirectionWires
OoutputTCELL0:DEC.H3

Bel PULLUP_DEC0_V

xc4000h CNR.TL bel PULLUP_DEC0_V
PinDirectionWires
OoutputTCELL0:DEC.V0

Bel PULLUP_DEC1_V

xc4000h CNR.TL bel PULLUP_DEC1_V
PinDirectionWires
OoutputTCELL0:DEC.V1

Bel PULLUP_DEC2_V

xc4000h CNR.TL bel PULLUP_DEC2_V
PinDirectionWires
OoutputTCELL0:DEC.V2

Bel PULLUP_DEC3_V

xc4000h CNR.TL bel PULLUP_DEC3_V
PinDirectionWires
OoutputTCELL0:DEC.V3

Bel BUFGLS_H

xc4000h CNR.TL bel BUFGLS_H
PinDirectionWires
IinputTCELL0:IMUX.BUFG.H

Bel BUFGLS_V

xc4000h CNR.TL bel BUFGLS_V
PinDirectionWires
IinputTCELL0:IMUX.BUFG.V

Bel CIN

xc4000h CNR.TL bel CIN
PinDirectionWires

Bel BSCAN

xc4000h CNR.TL bel BSCAN
PinDirectionWires
DRCKoutputTCELL0:OUT.BT.IOB1.I2
IDLEoutputTCELL0:OUT.LR.IOB1.I2
SEL1outputTCELL0:OUT.LR.IOB1.I1
SEL2outputTCELL0:OUT.BT.IOB1.I1
TDO1inputTCELL0:IMUX.BSCAN.TDO1
TDO2inputTCELL0:IMUX.BSCAN.TDO2

Bel wires

xc4000h CNR.TL bel wires
WirePins
TCELL0:DEC.H0PULLUP_DEC0_H.O
TCELL0:DEC.H1PULLUP_DEC1_H.O
TCELL0:DEC.H2PULLUP_DEC2_H.O
TCELL0:DEC.H3PULLUP_DEC3_H.O
TCELL0:DEC.V0PULLUP_DEC0_V.O
TCELL0:DEC.V1PULLUP_DEC1_V.O
TCELL0:DEC.V2PULLUP_DEC2_V.O
TCELL0:DEC.V3PULLUP_DEC3_V.O
TCELL0:IMUX.BUFG.HBUFGLS_H.I
TCELL0:IMUX.BUFG.VBUFGLS_V.I
TCELL0:IMUX.BSCAN.TDO1BSCAN.TDO1
TCELL0:IMUX.BSCAN.TDO2BSCAN.TDO2
TCELL0:OUT.BT.IOB1.I1BSCAN.SEL2
TCELL0:OUT.BT.IOB1.I2BSCAN.DRCK
TCELL0:OUT.LR.IOB1.I1BSCAN.SEL1
TCELL0:OUT.LR.IOB1.I2BSCAN.IDLE

Bitstream

xc4000h CNR.TL bittile 0
BitFrame
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
6 - - - - - - - - - - - - - - - - - - MISC:INPUT[0] INT:MUX.IMUX.BUFG.H[4]
5 - - - - - - - - - - - - - - - - - - INT:MUX.IMUX.BUFG.H[5] INT:MUX.IMUX.BUFG.H[1]
4 - - - - - - - - - - - - - ~MISC:TM_TOP INT:MUX.LONG.IO.H1[1] INT:MUX.IMUX.BUFG.H[0] INT:MUX.IMUX.BUFG.H[6] INT:MUX.IMUX.BUFG.H[2] INT:MUX.IMUX.BUFG.H[3] INT:MUX.LONG.IO.H3[1]
3 - - - - BSCAN:ENABLE INT:MUX.LONG.IO.V3[1] INT:MUX.LONG.IO.V3[0] ~MISC:TM_LEFT INT:MUX.LONG.IO.V1[0] INT:MUX.LONG.IO.V1[1] INT:MUX.LONG.IO.V1[2] - INT:MUX.LONG.IO.V1[3] ~PULLUP_DEC0_H:ENABLE INT:MUX.LONG.IO.H1[0] ~PULLUP_DEC1_H:ENABLE INT:MUX.LONG.IO.H3[0] INT:MUX.IMUX.BSCAN.TDO1[1] INT:MUX.IMUX.BSCAN.TDO1[5] INT:MUX.IMUX.BSCAN.TDO1[4]
2 - INT:MUX.LONG.H1[3] INT:MUX.LONG.H1[1] INT:MUX.LONG.H1[0] INT:MUX.LONG.H1[2] INT:MUX.LONG.H0[0] INT:MUX.LONG.H0[1] INT:MUX.LONG.H0[2] INT:MUX.LONG.H0[3] - - - - INT:MUX.LONG.IO.V0[3] ~PULLUP_DEC3_H:ENABLE ~PULLUP_DEC2_H:ENABLE INT:MUX.IMUX.BSCAN.TDO1[0] INT:MUX.IMUX.BSCAN.TDO1[3] INT:MUX.IMUX.BSCAN.TDO1[2] INT:MUX.LONG.IO.H0[1]
1 INT:MUX.IMUX.BUFG.V[0] INT:MUX.LONG.H2[1] INT:MUX.LONG.H2[0] - INT:MUX.LONG.IO.V2[3] INT:MUX.LONG.IO.V2[1] INT:MUX.LONG.IO.V2[0] INT:MUX.LONG.IO.V2[2] INT:MUX.LONG.IO.V0[0] INT:MUX.LONG.IO.V0[1] INT:MUX.LONG.IO.V0[2] - - INT:MUX.LONG.IO.H2[1] INT:MUX.LONG.IO.H2[0] - INT:MUX.LONG.IO.H0[0] INT:MUX.IMUX.BSCAN.TDO2[4] INT:MUX.IMUX.BSCAN.TDO2[3] INT:MUX.IMUX.BSCAN.TDO2[0]
0 - - - - ~PULLUP_DEC3_V:ENABLE - - - - ~PULLUP_DEC1_V:ENABLE ~PULLUP_DEC2_V:ENABLE ~PULLUP_DEC0_V:ENABLE - - - - - INT:MUX.IMUX.BSCAN.TDO2[2] INT:MUX.IMUX.BSCAN.TDO2[1] INT:MUX.IMUX.BSCAN.TDO2[5]
BSCAN:ENABLE 0.15.3
non-inverted [0]
INT:MUX.IMUX.BSCAN.TDO1 0.1.3 0.0.3 0.2.2 0.1.2 0.2.3 0.3.2
1.LONG.V0 0 0 0 1 1 1
1.LONG.V1 0 0 1 0 1 1
1.LONG.V2 0 0 1 1 0 1
1.DOUBLE.V1.0 0 1 1 1 1 1
2.SINGLE.H2 1 0 0 1 1 1
2.SINGLE.H3 1 0 1 0 1 1
2.SINGLE.H4 1 0 1 1 0 1
2.SINGLE.H5 1 0 1 1 1 0
1.DOUBLE.V0.1 1 1 1 1 1 1
INT:MUX.IMUX.BSCAN.TDO2 0.0.0 0.2.1 0.1.1 0.2.0 0.1.0 0.0.1
0.LONG.H0 0 0 0 1 1 1
0.LONG.H1 0 0 1 0 1 1
0.LONG.H2 0 0 1 1 0 1
1.SINGLE.V2 0 1 0 1 1 1
1.SINGLE.V3 0 1 1 0 1 1
1.SINGLE.V4 0 1 1 1 0 1
1.SINGLE.V5 0 1 1 1 1 0
2.DOUBLE.H1.0 1 0 1 1 1 1
2.DOUBLE.H0.1 1 1 1 1 1 1
INT:MUX.IMUX.BUFG.H 0.3.4 0.1.5 0.0.6 0.1.4 0.2.4 0.0.5 0.4.4
0.IO.DOUBLE.0.W.0 0 0 0 0 1 1 1
0.IO.DOUBLE.1.W.0 0 0 0 1 0 1 1
0.IO.DOUBLE.2.W.0 0 0 0 1 1 0 1
0.IO.DOUBLE.0.W.1 0 0 1 1 1 1 1
0.IO.DOUBLE.2.W.1 0 1 0 0 1 1 1
0.IO.DOUBLE.3.W.0 0 1 0 1 0 1 1
0.IO.DOUBLE.3.W.1 0 1 0 1 1 0 1
0.IO.DOUBLE.1.W.1 0 1 1 1 1 1 1
0.OUT.IOB.CLKIN.W 1 1 0 1 1 1 0
NONE 1 1 0 1 1 1 1
INT:MUX.IMUX.BUFG.V 0.19.1
0.OUT.IOB.CLKIN.N 0
NONE 1
INT:MUX.LONG.H0 0.11.2 0.12.2 0.13.2 0.14.2
0.LONG.IO.V0 0 0 0 1
0.DEC.V0 0 0 1 0
0.OUT.LR.IOB1.I2 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.H1 0.18.2 0.15.2 0.17.2 0.16.2
0.LONG.IO.V1 0 0 0 1
0.DEC.V1 0 0 1 0
0.OUT.LR.IOB1.I2 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.H2 0.18.1 0.17.1
0.LONG.IO.V2 0 0
0.DEC.V2 0 1
NONE 1 1
INT:MUX.LONG.IO.H0 0.0.2 0.3.1
0.LONG.IO.V2 0 0
0.LONG.IO.V0 0 1
NONE 1 1
INT:MUX.LONG.IO.H1 0.5.4 0.5.3
0.LONG.IO.V3 0 0
0.LONG.IO.V1 0 1
NONE 1 1
INT:MUX.LONG.IO.H2 0.6.1 0.5.1
0.LONG.IO.V0 0 0
0.LONG.IO.V2 0 1
NONE 1 1
INT:MUX.LONG.IO.H3 0.0.4 0.3.3
0.LONG.IO.V1 0 0
0.LONG.IO.V3 0 1
NONE 1 1
INT:MUX.LONG.IO.V0 0.6.2 0.9.1 0.10.1 0.11.1
0.LONG.H0 0 0 0 1
0.LONG.IO.H2 0 0 1 0
0.LONG.IO.H0 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.V1 0.7.3 0.9.3 0.10.3 0.11.3
0.LONG.H1 0 0 0 1
0.LONG.IO.H3 0 0 1 0
0.LONG.IO.H1 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.V2 0.15.1 0.12.1 0.14.1 0.13.1
0.LONG.H2 0 0 0 1
0.LONG.IO.H0 0 0 1 0
0.LONG.IO.H2 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.V3 0.14.3 0.13.3
0.LONG.IO.H1 0 0
0.LONG.IO.H3 0 1
NONE 1 1
MISC:INPUT 0.1.6
CMOS 0
TTL 1
MISC:TM_LEFT 0.12.3
MISC:TM_TOP 0.6.4
PULLUP_DEC0_H:ENABLE 0.6.3
PULLUP_DEC0_V:ENABLE 0.8.0
PULLUP_DEC1_H:ENABLE 0.4.3
PULLUP_DEC1_V:ENABLE 0.10.0
PULLUP_DEC2_H:ENABLE 0.4.2
PULLUP_DEC2_V:ENABLE 0.9.0
PULLUP_DEC3_H:ENABLE 0.5.2
PULLUP_DEC3_V:ENABLE 0.15.0
inverted ~[0]

Tile CNR.BR

Cells: 1

Switchbox INT

xc4000h CNR.BR switchbox INT
DestinationSourceKind
SINGLE.H0DEC.V0pass transistor
OUT.LR.IOB1.I2.Spass transistor
SINGLE.H0.Ebidirectional pass transistor
SINGLE.V0bidirectional pass transistor
SINGLE.V0.Sbidirectional pass transistor
IO.DOUBLE.0.E.0bidirectional pass transistor
IO.DOUBLE.0.S.1bidirectional pass transistor
SINGLE.H0.ESINGLE.H0bidirectional pass transistor
SINGLE.V0bidirectional pass transistor
SINGLE.V0.Sbidirectional pass transistor
SINGLE.H1LONG.IO.V0pass transistor
OUT.STARTUP.Q3pass transistor
SINGLE.H1.Ebidirectional pass transistor
SINGLE.V1bidirectional pass transistor
SINGLE.V1.Sbidirectional pass transistor
IO.DOUBLE.0.E.1bidirectional pass transistor
SINGLE.H1.ELONG.V0pass transistor
SINGLE.H1bidirectional pass transistor
SINGLE.V1bidirectional pass transistor
SINGLE.V1.Sbidirectional pass transistor
SINGLE.H2LONG.IO.V1pass transistor
OUT.STARTUP.Q1Q4pass transistor
SINGLE.H2.Ebidirectional pass transistor
SINGLE.V2bidirectional pass transistor
SINGLE.V2.Sbidirectional pass transistor
IO.DOUBLE.1.E.0bidirectional pass transistor
IO.DOUBLE.1.S.1bidirectional pass transistor
SINGLE.H2.ELONG.V1pass transistor
SINGLE.H2bidirectional pass transistor
SINGLE.V2bidirectional pass transistor
SINGLE.V2.Sbidirectional pass transistor
SINGLE.H3DEC.V1pass transistor
OUT.LR.IOB1.I1.Spass transistor
SINGLE.H3.Ebidirectional pass transistor
SINGLE.V3bidirectional pass transistor
SINGLE.V3.Sbidirectional pass transistor
IO.DOUBLE.1.E.1bidirectional pass transistor
SINGLE.H3.ELONG.V2pass transistor
SINGLE.H3bidirectional pass transistor
SINGLE.V3bidirectional pass transistor
SINGLE.V3.Sbidirectional pass transistor
SINGLE.H4LONG.V3pass transistor
DEC.V2pass transistor
OUT.LR.IOB1.I2.Spass transistor
SINGLE.H4.Ebidirectional pass transistor
SINGLE.V4bidirectional pass transistor
SINGLE.V4.Sbidirectional pass transistor
IO.DOUBLE.2.E.0bidirectional pass transistor
IO.DOUBLE.2.S.1bidirectional pass transistor
SINGLE.H4.ESINGLE.H4bidirectional pass transistor
SINGLE.V4bidirectional pass transistor
SINGLE.V4.Sbidirectional pass transistor
SINGLE.H5LONG.V4pass transistor
LONG.IO.V2pass transistor
OUT.STARTUP.Q3pass transistor
SINGLE.H5.Ebidirectional pass transistor
SINGLE.V5bidirectional pass transistor
SINGLE.V5.Sbidirectional pass transistor
IO.DOUBLE.2.E.1bidirectional pass transistor
SINGLE.H5.ESINGLE.H5bidirectional pass transistor
SINGLE.V5bidirectional pass transistor
SINGLE.V5.Sbidirectional pass transistor
SINGLE.H6LONG.V5pass transistor
LONG.IO.V3pass transistor
OUT.STARTUP.Q1Q4pass transistor
SINGLE.H6.Ebidirectional pass transistor
SINGLE.V6bidirectional pass transistor
SINGLE.V6.Sbidirectional pass transistor
IO.DOUBLE.3.E.0bidirectional pass transistor
IO.DOUBLE.3.S.1bidirectional pass transistor
SINGLE.H6.ESINGLE.H6bidirectional pass transistor
SINGLE.V6bidirectional pass transistor
SINGLE.V6.Sbidirectional pass transistor
SINGLE.H7DEC.V3pass transistor
OUT.LR.IOB1.I1.Spass transistor
SINGLE.H7.Ebidirectional pass transistor
SINGLE.V7bidirectional pass transistor
SINGLE.V7.Sbidirectional pass transistor
IO.DOUBLE.3.E.1bidirectional pass transistor
SINGLE.H7.ESINGLE.H7bidirectional pass transistor
SINGLE.V7bidirectional pass transistor
SINGLE.V7.Sbidirectional pass transistor
SINGLE.V0GNDpass transistor
DEC.H3pass transistor
OUT.BT.IOB1.I2.Epass transistor
SINGLE.H0bidirectional pass transistor
SINGLE.H0.Ebidirectional pass transistor
SINGLE.V0.Sbidirectional pass transistor
IO.DOUBLE.0.S.1bidirectional pass transistor
SINGLE.V0.SSINGLE.H0bidirectional pass transistor
SINGLE.H0.Ebidirectional pass transistor
SINGLE.V0bidirectional pass transistor
SINGLE.V1LONG.IO.H0pass transistor
OUT.STARTUP.DONEINpass transistor
SINGLE.H1bidirectional pass transistor
SINGLE.H1.Ebidirectional pass transistor
SINGLE.V1.Sbidirectional pass transistor
IO.DOUBLE.0.E.1bidirectional pass transistor
IO.DOUBLE.0.S.2bidirectional pass transistor
SINGLE.V1.SSINGLE.H1bidirectional pass transistor
SINGLE.H1.Ebidirectional pass transistor
SINGLE.V1bidirectional pass transistor
SINGLE.V2LONG.IO.H1pass transistor
OUT.STARTUP.Q2pass transistor
SINGLE.H2bidirectional pass transistor
SINGLE.H2.Ebidirectional pass transistor
SINGLE.V2.Sbidirectional pass transistor
IO.DOUBLE.1.S.1bidirectional pass transistor
SINGLE.V2.SSINGLE.H2bidirectional pass transistor
SINGLE.H2.Ebidirectional pass transistor
SINGLE.V2bidirectional pass transistor
SINGLE.V3DEC.H2pass transistor
OUT.BT.IOB1.I1.Epass transistor
SINGLE.H3bidirectional pass transistor
SINGLE.H3.Ebidirectional pass transistor
SINGLE.V3.Sbidirectional pass transistor
IO.DOUBLE.1.E.1bidirectional pass transistor
IO.DOUBLE.1.S.2bidirectional pass transistor
SINGLE.V3.SSINGLE.H3bidirectional pass transistor
SINGLE.H3.Ebidirectional pass transistor
SINGLE.V3bidirectional pass transistor
SINGLE.V4LONG.H3pass transistor
DEC.H1pass transistor
OUT.BT.IOB1.I2.Epass transistor
SINGLE.H4bidirectional pass transistor
SINGLE.H4.Ebidirectional pass transistor
SINGLE.V4.Sbidirectional pass transistor
IO.DOUBLE.2.S.1bidirectional pass transistor
SINGLE.V4.SSINGLE.H4bidirectional pass transistor
SINGLE.H4.Ebidirectional pass transistor
SINGLE.V4bidirectional pass transistor
SINGLE.V5LONG.H4pass transistor
LONG.IO.H2pass transistor
OUT.STARTUP.DONEINpass transistor
SINGLE.H5bidirectional pass transistor
SINGLE.H5.Ebidirectional pass transistor
SINGLE.V5.Sbidirectional pass transistor
IO.DOUBLE.2.E.1bidirectional pass transistor
IO.DOUBLE.2.S.2bidirectional pass transistor
SINGLE.V5.SSINGLE.H5bidirectional pass transistor
SINGLE.H5.Ebidirectional pass transistor
SINGLE.V5bidirectional pass transistor
SINGLE.V6LONG.H5pass transistor
LONG.IO.H3pass transistor
OUT.STARTUP.Q2pass transistor
SINGLE.H6bidirectional pass transistor
SINGLE.H6.Ebidirectional pass transistor
SINGLE.V6.Sbidirectional pass transistor
IO.DOUBLE.3.S.1bidirectional pass transistor
SINGLE.V6.SSINGLE.H6bidirectional pass transistor
SINGLE.H6.Ebidirectional pass transistor
SINGLE.V6bidirectional pass transistor
SINGLE.V7GNDpass transistor
DEC.H0pass transistor
OUT.BT.IOB1.I1.Epass transistor
SINGLE.H7bidirectional pass transistor
SINGLE.H7.Ebidirectional pass transistor
SINGLE.V7.Sbidirectional pass transistor
IO.DOUBLE.3.E.1bidirectional pass transistor
IO.DOUBLE.3.S.2bidirectional pass transistor
SINGLE.V7.SSINGLE.H7bidirectional pass transistor
SINGLE.H7.Ebidirectional pass transistor
SINGLE.V7bidirectional pass transistor
DOUBLE.H0.0OUT.STARTUP.Q1Q4pass transistor
DOUBLE.H0.2bidirectional pass transistor
DOUBLE.V0.0bidirectional pass transistor
DOUBLE.V0.2bidirectional pass transistor
IO.DOUBLE.1.E.0bidirectional pass transistor
IO.DOUBLE.1.E.1bidirectional pass transistor
IO.DOUBLE.1.S.1bidirectional pass transistor
DOUBLE.H0.1OUT.LR.IOB1.I1.Spass transistor
IO.DOUBLE.0.E.0bidirectional pass transistor
IO.DOUBLE.0.E.1bidirectional pass transistor
IO.DOUBLE.0.S.1bidirectional pass transistor
DOUBLE.H0.2DOUBLE.H0.0bidirectional pass transistor
DOUBLE.V0.0bidirectional pass transistor
DOUBLE.V0.2bidirectional pass transistor
DOUBLE.H1.0OUT.LR.IOB1.I2.Spass transistor
DOUBLE.H1.2bidirectional pass transistor
DOUBLE.V1.0bidirectional pass transistor
DOUBLE.V1.2bidirectional pass transistor
IO.DOUBLE.2.E.0bidirectional pass transistor
IO.DOUBLE.2.E.1bidirectional pass transistor
IO.DOUBLE.2.S.1bidirectional pass transistor
DOUBLE.H1.1OUT.STARTUP.Q3pass transistor
IO.DOUBLE.3.E.0bidirectional pass transistor
IO.DOUBLE.3.E.1bidirectional pass transistor
IO.DOUBLE.3.S.1bidirectional pass transistor
DOUBLE.H1.2DOUBLE.H1.0bidirectional pass transistor
DOUBLE.V1.0bidirectional pass transistor
DOUBLE.V1.2bidirectional pass transistor
DOUBLE.V0.0OUT.BT.IOB1.I1.Epass transistor
DOUBLE.H0.0bidirectional pass transistor
DOUBLE.H0.2bidirectional pass transistor
DOUBLE.V0.2bidirectional pass transistor
IO.DOUBLE.1.E.1bidirectional pass transistor
IO.DOUBLE.1.S.1bidirectional pass transistor
IO.DOUBLE.1.S.2bidirectional pass transistor
DOUBLE.V0.1OUT.STARTUP.Q2pass transistor
IO.DOUBLE.0.E.1bidirectional pass transistor
IO.DOUBLE.0.S.1bidirectional pass transistor
IO.DOUBLE.0.S.2bidirectional pass transistor
DOUBLE.V0.2DOUBLE.H0.0bidirectional pass transistor
DOUBLE.H0.2bidirectional pass transistor
DOUBLE.V0.0bidirectional pass transistor
DOUBLE.V1.0OUT.STARTUP.DONEINpass transistor
DOUBLE.H1.0bidirectional pass transistor
DOUBLE.H1.2bidirectional pass transistor
DOUBLE.V1.2bidirectional pass transistor
IO.DOUBLE.2.E.1bidirectional pass transistor
IO.DOUBLE.2.S.1bidirectional pass transistor
IO.DOUBLE.2.S.2bidirectional pass transistor
DOUBLE.V1.1OUT.BT.IOB1.I2.Epass transistor
IO.DOUBLE.3.E.1bidirectional pass transistor
IO.DOUBLE.3.S.1bidirectional pass transistor
IO.DOUBLE.3.S.2bidirectional pass transistor
DOUBLE.V1.2DOUBLE.H1.0bidirectional pass transistor
DOUBLE.H1.2bidirectional pass transistor
DOUBLE.V1.0bidirectional pass transistor
IO.DOUBLE.0.E.0IO.DBUF.V0pass transistor
SINGLE.H0bidirectional pass transistor
DOUBLE.H0.1bidirectional pass transistor
IO.DOUBLE.0.S.1bidirectional pass transistor
IO.DOUBLE.0.E.1IO.DBUF.H1pass transistor
SINGLE.H1bidirectional pass transistor
SINGLE.V1bidirectional pass transistor
DOUBLE.H0.1bidirectional pass transistor
DOUBLE.V0.1bidirectional pass transistor
IO.DOUBLE.0.S.2bidirectional pass transistor
IO.DOUBLE.0.S.1IO.DBUF.V1pass transistor
SINGLE.H0bidirectional pass transistor
SINGLE.V0bidirectional pass transistor
DOUBLE.H0.1bidirectional pass transistor
DOUBLE.V0.1bidirectional pass transistor
IO.DOUBLE.0.E.0bidirectional pass transistor
IO.DOUBLE.0.S.2IO.DBUF.H0pass transistor
SINGLE.V1bidirectional pass transistor
DOUBLE.V0.1bidirectional pass transistor
IO.DOUBLE.0.E.1bidirectional pass transistor
IO.DOUBLE.1.E.0IO.DBUF.V0pass transistor
SINGLE.H2bidirectional pass transistor
DOUBLE.H0.0bidirectional pass transistor
IO.DOUBLE.1.S.1bidirectional pass transistor
IO.DOUBLE.1.E.1IO.DBUF.H1pass transistor
SINGLE.H3bidirectional pass transistor
SINGLE.V3bidirectional pass transistor
DOUBLE.H0.0bidirectional pass transistor
DOUBLE.V0.0bidirectional pass transistor
IO.DOUBLE.1.S.2bidirectional pass transistor
IO.DOUBLE.1.S.1IO.DBUF.V1pass transistor
SINGLE.H2bidirectional pass transistor
SINGLE.V2bidirectional pass transistor
DOUBLE.H0.0bidirectional pass transistor
DOUBLE.V0.0bidirectional pass transistor
IO.DOUBLE.1.E.0bidirectional pass transistor
IO.DOUBLE.1.S.2IO.DBUF.H0pass transistor
SINGLE.V3bidirectional pass transistor
DOUBLE.V0.0bidirectional pass transistor
IO.DOUBLE.1.E.1bidirectional pass transistor
IO.DOUBLE.2.E.0IO.DBUF.V0pass transistor
SINGLE.H4bidirectional pass transistor
DOUBLE.H1.0bidirectional pass transistor
IO.DOUBLE.2.S.1bidirectional pass transistor
IO.DOUBLE.2.E.1IO.DBUF.H1pass transistor
SINGLE.H5bidirectional pass transistor
SINGLE.V5bidirectional pass transistor
DOUBLE.H1.0bidirectional pass transistor
DOUBLE.V1.0bidirectional pass transistor
IO.DOUBLE.2.S.2bidirectional pass transistor
IO.DOUBLE.2.S.1IO.DBUF.V1pass transistor
SINGLE.H4bidirectional pass transistor
SINGLE.V4bidirectional pass transistor
DOUBLE.H1.0bidirectional pass transistor
DOUBLE.V1.0bidirectional pass transistor
IO.DOUBLE.2.E.0bidirectional pass transistor
IO.DOUBLE.2.S.2IO.DBUF.H0pass transistor
SINGLE.V5bidirectional pass transistor
DOUBLE.V1.0bidirectional pass transistor
IO.DOUBLE.2.E.1bidirectional pass transistor
IO.DOUBLE.3.E.0IO.DBUF.V0pass transistor
SINGLE.H6bidirectional pass transistor
DOUBLE.H1.1bidirectional pass transistor
IO.DOUBLE.3.S.1bidirectional pass transistor
IO.DOUBLE.3.E.1IO.DBUF.H1pass transistor
SINGLE.H7bidirectional pass transistor
SINGLE.V7bidirectional pass transistor
DOUBLE.H1.1bidirectional pass transistor
DOUBLE.V1.1bidirectional pass transistor
IO.DOUBLE.3.S.2bidirectional pass transistor
IO.DOUBLE.3.S.1IO.DBUF.V1pass transistor
SINGLE.H6bidirectional pass transistor
SINGLE.V6bidirectional pass transistor
DOUBLE.H1.1bidirectional pass transistor
DOUBLE.V1.1bidirectional pass transistor
IO.DOUBLE.3.E.0bidirectional pass transistor
IO.DOUBLE.3.S.2IO.DBUF.H0pass transistor
SINGLE.V7bidirectional pass transistor
DOUBLE.V1.1bidirectional pass transistor
IO.DOUBLE.3.E.1bidirectional pass transistor
IO.DBUF.H0IO.DOUBLE.0.E.1mux
IO.DOUBLE.1.E.1mux
IO.DOUBLE.2.E.1mux
IO.DOUBLE.3.E.1mux
IO.DBUF.H1IO.DOUBLE.0.S.2mux
IO.DOUBLE.1.S.2mux
IO.DOUBLE.2.S.2mux
IO.DOUBLE.3.S.2mux
IO.DBUF.V0IO.DOUBLE.0.S.1mux
IO.DOUBLE.1.S.1mux
IO.DOUBLE.2.S.1mux
IO.DOUBLE.3.S.1mux
IO.DBUF.V1IO.DOUBLE.0.E.0mux
IO.DOUBLE.1.E.0mux
IO.DOUBLE.2.E.0mux
IO.DOUBLE.3.E.0mux
LONG.H3LONG.IO.V1mux
DEC.V2mux
SINGLE.V4buffer
LONG.H4LONG.IO.V2mux
DEC.V1mux
OUT.STARTUP.Q3mux
SINGLE.V5buffer
LONG.H5LONG.IO.V3mux
DEC.V0mux
OUT.STARTUP.Q3mux
SINGLE.V6buffer
LONG.V0LONG.IO.H0mux
DEC.H0mux
OUT.BT.IOB1.I2.Emux
SINGLE.H1.Ebuffer
LONG.V1LONG.IO.H1mux
DEC.H1mux
OUT.BT.IOB1.I2.Emux
SINGLE.H2.Ebuffer
LONG.V2LONG.IO.H2mux
DEC.H2mux
OUT.BT.IOB1.I2.Emux
SINGLE.H3.Ebuffer
LONG.V3LONG.IO.H1mux
DEC.H1mux
OUT.STARTUP.DONEINmux
SINGLE.H4buffer
LONG.V4LONG.IO.H2mux
DEC.H2mux
OUT.STARTUP.DONEINmux
SINGLE.H5buffer
LONG.V5LONG.IO.H3mux
DEC.H3mux
OUT.STARTUP.DONEINmux
SINGLE.H6buffer
LONG.IO.H0SINGLE.V1mux
LONG.V0mux
LONG.IO.V0mux
LONG.IO.V2mux
LONG.IO.H1SINGLE.V2mux
LONG.V1mux
LONG.V3mux
LONG.IO.V1mux
LONG.IO.V3mux
LONG.IO.H2SINGLE.V5mux
LONG.V2mux
LONG.V4mux
LONG.IO.V0mux
LONG.IO.V2mux
LONG.IO.H3SINGLE.V6mux
LONG.V5mux
LONG.IO.V1mux
LONG.IO.V3mux
LONG.IO.V0SINGLE.H1mux
LONG.IO.H0mux
LONG.IO.H2mux
LONG.IO.V1SINGLE.H2mux
LONG.H3mux
LONG.IO.H1mux
LONG.IO.H3mux
LONG.IO.V2SINGLE.H5mux
LONG.H4mux
LONG.IO.H0mux
LONG.IO.H2mux
LONG.IO.V3SINGLE.H6mux
LONG.H5mux
LONG.IO.H1mux
LONG.IO.H3mux
IMUX.STARTUP.CLKSINGLE.V2mux
SINGLE.V3mux
SINGLE.V4mux
SINGLE.V5mux
IMUX.STARTUP.GSRSINGLE.H2mux
SINGLE.H3mux
SINGLE.H4mux
SINGLE.H5mux
DOUBLE.V0.0mux
DOUBLE.V1.1mux
LONG.V3mux
LONG.V4mux
LONG.V5mux
IMUX.STARTUP.GTSSINGLE.V2mux
SINGLE.V3mux
SINGLE.V4mux
SINGLE.V5mux
DOUBLE.H0.1mux
DOUBLE.H1.0mux
LONG.H3mux
LONG.H4mux
LONG.H5mux
IMUX.READCLK.ISINGLE.H2mux
SINGLE.H3mux
SINGLE.H4mux
SINGLE.H5mux
IMUX.BUFG.HIO.DOUBLE.0.E.1mux
IO.DOUBLE.0.S.1mux
IO.DOUBLE.1.E.1mux
IO.DOUBLE.1.S.1mux
IO.DOUBLE.2.E.1mux
IO.DOUBLE.2.S.1mux
IO.DOUBLE.3.E.1mux
IO.DOUBLE.3.S.1mux
OUT.IOB.CLKIN.Emux
IMUX.BUFG.VOUT.IOB.CLKIN.Smux

Bel PULLUP_DEC0_H

xc4000h CNR.BR bel PULLUP_DEC0_H
PinDirectionWires
OoutputDEC.H0

Bel PULLUP_DEC1_H

xc4000h CNR.BR bel PULLUP_DEC1_H
PinDirectionWires
OoutputDEC.H1

Bel PULLUP_DEC2_H

xc4000h CNR.BR bel PULLUP_DEC2_H
PinDirectionWires
OoutputDEC.H2

Bel PULLUP_DEC3_H

xc4000h CNR.BR bel PULLUP_DEC3_H
PinDirectionWires
OoutputDEC.H3

Bel PULLUP_DEC0_V

xc4000h CNR.BR bel PULLUP_DEC0_V
PinDirectionWires
OoutputDEC.V0

Bel PULLUP_DEC1_V

xc4000h CNR.BR bel PULLUP_DEC1_V
PinDirectionWires
OoutputDEC.V1

Bel PULLUP_DEC2_V

xc4000h CNR.BR bel PULLUP_DEC2_V
PinDirectionWires
OoutputDEC.V2

Bel PULLUP_DEC3_V

xc4000h CNR.BR bel PULLUP_DEC3_V
PinDirectionWires
OoutputDEC.V3

Bel BUFGLS_H

xc4000h CNR.BR bel BUFGLS_H
PinDirectionWires
IinputIMUX.BUFG.H

Bel BUFGLS_V

xc4000h CNR.BR bel BUFGLS_V
PinDirectionWires
IinputIMUX.BUFG.V

Bel COUT

xc4000h CNR.BR bel COUT
PinDirectionWires

Bel STARTUP

xc4000h CNR.BR bel STARTUP
PinDirectionWires
CLKinputIMUX.STARTUP.CLK
DONEINoutputOUT.STARTUP.DONEIN
GSRinputIMUX.STARTUP.GSR
GTSinputIMUX.STARTUP.GTS
Q1Q4outputOUT.STARTUP.Q1Q4
Q2outputOUT.STARTUP.Q2
Q3outputOUT.STARTUP.Q3

Bel READCLK

xc4000h CNR.BR bel READCLK
PinDirectionWires
IinputIMUX.READCLK.I

Bel wires

xc4000h CNR.BR bel wires
WirePins
DEC.H0PULLUP_DEC0_H.O
DEC.H1PULLUP_DEC1_H.O
DEC.H2PULLUP_DEC2_H.O
DEC.H3PULLUP_DEC3_H.O
DEC.V0PULLUP_DEC0_V.O
DEC.V1PULLUP_DEC1_V.O
DEC.V2PULLUP_DEC2_V.O
DEC.V3PULLUP_DEC3_V.O
IMUX.STARTUP.CLKSTARTUP.CLK
IMUX.STARTUP.GSRSTARTUP.GSR
IMUX.STARTUP.GTSSTARTUP.GTS
IMUX.READCLK.IREADCLK.I
IMUX.BUFG.HBUFGLS_H.I
IMUX.BUFG.VBUFGLS_V.I
OUT.STARTUP.DONEINSTARTUP.DONEIN
OUT.STARTUP.Q1Q4STARTUP.Q1Q4
OUT.STARTUP.Q2STARTUP.Q2
OUT.STARTUP.Q3STARTUP.Q3

Bitstream

xc4000h CNR.BR bittile 0
BitFrame
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
12 ~INT:PASS.SINGLE.H2.E.0.LONG.V1 ~INT:BIPASS.SINGLE.H7.E.SINGLE.V7.S ~INT:BIPASS.SINGLE.H7.SINGLE.H7.E ~INT:BIPASS.SINGLE.H7.E.SINGLE.V7 ~INT:BIPASS.SINGLE.V7.SINGLE.V7.S ~INT:BIPASS.SINGLE.H7.SINGLE.V7 ~INT:PASS.SINGLE.H6.0.LONG.V5 - ~INT:BIPASS.SINGLE.H2.E.SINGLE.V2.S ~INT:BIPASS.SINGLE.H2.E.SINGLE.V2 ~INT:BIPASS.SINGLE.V2.SINGLE.V2.S ~INT:BIPASS.DOUBLE.H0.0.DOUBLE.H0.2 ~INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.2 ~INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.0 ~INT:PASS.SINGLE.V7.0.GND - ~INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.E.0 ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.E.0 ~INT:BIPASS.SINGLE.H7.IO.DOUBLE.3.E.1 ~INT:BIPASS.IO.DOUBLE.3.E.0.IO.DOUBLE.3.S.1 ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.E.1 ~INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.S.1 ~INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.S.1 ~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.1 ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.S.1 ~INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.E.1 INT:MUX.IO.DBUF.V1[0] INT:MUX.IO.DBUF.V1[2] INT:MUX.IO.DBUF.V1[1] ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.1 ~INT:BIPASS.IO.DOUBLE.0.E.0.IO.DOUBLE.0.S.1 INT:MUX.IO.DBUF.V1[3] ~INT:PASS.SINGLE.H2.0.LONG.IO.V1 INT:MUX.IO.DBUF.V0[1] INT:MUX.IO.DBUF.V0[0] INT:MUX.IO.DBUF.V0[2] ~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.E.0 ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.0 ~INT:BIPASS.IO.DOUBLE.1.E.0.IO.DOUBLE.1.S.1 ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.S.1 ~INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.1
11 - ~INT:BIPASS.SINGLE.H4.E.SINGLE.V4 ~INT:BUF.LONG.V1.0.SINGLE.H2.E ~INT:BIPASS.SINGLE.H7.SINGLE.V7.S ~INT:BIPASS.SINGLE.H6.SINGLE.V6 ~INT:BUF.LONG.V5.0.SINGLE.H6 - ~INT:BIPASS.SINGLE.H2.SINGLE.V2.S ~INT:BIPASS.SINGLE.H2.SINGLE.H2.E ~INT:BIPASS.SINGLE.H2.SINGLE.V2 - ~INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.2 - ~INT:BIPASS.DOUBLE.V0.0.DOUBLE.V0.2 - - - - - - - - - - - - - - - - - - - - - - - - - - -
10 ~INT:PASS.SINGLE.V6.0.LONG.H5 - ~INT:BIPASS.SINGLE.V6.SINGLE.V6.S ~INT:BIPASS.SINGLE.H6.E.SINGLE.V6.S ~INT:BIPASS.SINGLE.H6.SINGLE.V6.S ~INT:BIPASS.SINGLE.H6.SINGLE.H6.E ~INT:BIPASS.SINGLE.H6.E.SINGLE.V6 ~INT:BIPASS.SINGLE.H3.E.SINGLE.V3.S ~INT:BIPASS.SINGLE.H3.E.SINGLE.V3 ~INT:BIPASS.SINGLE.H3.SINGLE.H3.E ~INT:BIPASS.SINGLE.H3.SINGLE.V3.S ~INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.0 ~INT:BIPASS.SINGLE.H3.SINGLE.V3 ~INT:BIPASS.SINGLE.V3.SINGLE.V3.S ~INT:PASS.SINGLE.V4.0.LONG.H3 - - - - - - - - - - - - - - - - - ~INT:PASS.SINGLE.H6.0.OUT.STARTUP.Q1Q4 ~INT:PASS.DOUBLE.H0.0.0.OUT.STARTUP.Q1Q4 ~INT:PASS.SINGLE.H2.0.OUT.STARTUP.Q1Q4 ~INT:PASS.SINGLE.H3.0.DEC.V1 INT:MUX.IO.DBUF.V0[3] ~INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.E.0 ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.E.0 ~INT:BIPASS.IO.DOUBLE.2.E.0.IO.DOUBLE.2.S.1 OSC:MUX.OUT0[2]
9 - ~INT:BIPASS.SINGLE.H4.SINGLE.V4 ~INT:BIPASS.SINGLE.V4.SINGLE.V4.S ~INT:BIPASS.SINGLE.H4.E.SINGLE.V4.S ~INT:BIPASS.SINGLE.H4.SINGLE.H4.E ~INT:BIPASS.SINGLE.H4.SINGLE.V4.S ~INT:PASS.SINGLE.H3.E.0.LONG.V2 ~INT:BIPASS.DOUBLE.H1.0.DOUBLE.H1.2 ~INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.0 - ~INT:BIPASS.SINGLE.H1.E.SINGLE.V1 ~INT:BIPASS.SINGLE.V0.SINGLE.V0.S ~INT:BIPASS.SINGLE.H0.SINGLE.H0.E - ~INT:PASS.SINGLE.V0.0.GND ~INT:PASS.DOUBLE.H1.0.0.OUT.LR.IOB1.I2.S ~INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S ~INT:PASS.SINGLE.H4.0.OUT.LR.IOB1.I2.S ~INT:PASS.SINGLE.H5.0.OUT.STARTUP.Q3 ~INT:PASS.DOUBLE.H1.1.0.OUT.STARTUP.Q3 ~INT:PASS.SINGLE.H1.0.OUT.STARTUP.Q3 ~INT:BUF.LONG.V2.0.SINGLE.H3.E ~INT:BUF.LONG.H5.0.SINGLE.V6 - ~INT:PASS.SINGLE.H1.0.LONG.IO.V0 ~INT:PASS.SINGLE.H6.0.LONG.IO.V3 ~INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.0 ~INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.E.0 ~INT:PASS.IO.DOUBLE.3.E.0.0.IO.DBUF.V0 ~INT:PASS.IO.DOUBLE.2.E.0.0.IO.DBUF.V0 ~INT:PASS.IO.DOUBLE.0.S.1.0.IO.DBUF.V1 ~INT:PASS.IO.DOUBLE.2.S.1.0.IO.DBUF.V1 ~INT:PASS.IO.DOUBLE.3.S.1.0.IO.DBUF.V1 ~INT:PASS.IO.DOUBLE.1.S.1.0.IO.DBUF.V1 ~INT:PASS.SINGLE.H7.0.OUT.LR.IOB1.I1.S ~INT:PASS.SINGLE.H7.0.DEC.V3 ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.E.1 ~INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.1 ~INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.S.1 ~INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.S.1 OSC:MUX.OUT1[2]
8 ~INT:PASS.SINGLE.V5.0.LONG.H4 ~INT:BIPASS.SINGLE.V5.SINGLE.V5.S ~INT:BIPASS.SINGLE.H5.E.SINGLE.V5.S ~INT:BIPASS.SINGLE.H5.SINGLE.V5.S ~INT:BIPASS.SINGLE.H5.E.SINGLE.V5 ~INT:BIPASS.SINGLE.H5.SINGLE.H5.E ~INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.2 ~INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.0 ~INT:PASS.SINGLE.H1.E.0.LONG.V0 ~INT:BIPASS.SINGLE.H1.E.SINGLE.V1.S ~INT:BIPASS.SINGLE.H1.SINGLE.H1.E ~INT:BIPASS.SINGLE.H1.SINGLE.V1 ~INT:BIPASS.SINGLE.H0.E.SINGLE.V0.S ~INT:BIPASS.SINGLE.H0.SINGLE.V0 ~INT:BIPASS.SINGLE.H0.E.SINGLE.V0 - - - - - - ~INT:BUF.LONG.H4.0.SINGLE.V5 - ~INT:BUF.LONG.V0.0.SINGLE.H1.E ~INT:BUF.LONG.V4.0.SINGLE.H5 ~INT:BUF.LONG.V3.0.SINGLE.H4 ~INT:PASS.IO.DOUBLE.0.E.0.0.IO.DBUF.V0 ~INT:PASS.IO.DOUBLE.1.E.0.0.IO.DBUF.V0 ~INT:PASS.DOUBLE.H0.1.0.OUT.LR.IOB1.I1.S ~INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S ~INT:PASS.SINGLE.H0.0.DEC.V0 ~INT:PASS.SINGLE.H5.0.LONG.IO.V2 ~INT:PASS.SINGLE.H4.0.DEC.V2 INT:MUX.IMUX.READCLK.I[2] INT:MUX.IMUX.READCLK.I[1] INT:MUX.IMUX.READCLK.I[0] INT:MUX.IMUX.READCLK.I[3] ~INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.E.1 ~INT:BIPASS.SINGLE.H5.IO.DOUBLE.2.E.1 OSC:MUX.OUT0[1] OSC:MUX.OUT1[1]
7 INT:MUX.IMUX.STARTUP.CLK[0] INT:MUX.IMUX.STARTUP.CLK[1] INT:MUX.IMUX.STARTUP.CLK[2] INT:MUX.IMUX.STARTUP.CLK[3] ~INT:BIPASS.SINGLE.H5.SINGLE.V5 ~INT:PASS.SINGLE.H4.0.LONG.V3 ~INT:BIPASS.DOUBLE.V1.0.DOUBLE.V1.2 ~INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.2 - ~INT:BIPASS.SINGLE.V1.SINGLE.V1.S ~INT:BIPASS.SINGLE.H0.SINGLE.V0.S ~INT:BIPASS.SINGLE.H1.SINGLE.V1.S ~INT:PASS.SINGLE.H5.0.LONG.V4 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 ~INT:PASS.SINGLE.V4.0.OUT.BT.IOB1.I2.E ~INT:PASS.SINGLE.V4.0.DEC.H1 ~INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E INT:MUX.LONG.V1[2] ~INT:PASS.SINGLE.V3.0.DEC.H2 INT:MUX.LONG.V3[1] INT:MUX.LONG.V3[2] INT:MUX.IMUX.STARTUP.GSR[3] INT:MUX.IMUX.STARTUP.GSR[0] INT:MUX.IMUX.STARTUP.GSR[2] INT:MUX.IMUX.STARTUP.GSR[1] INT:MUX.IMUX.STARTUP.GSR[5] INT:MUX.IMUX.STARTUP.GSR[4] ~INT:PASS.SINGLE.V1.0.OUT.STARTUP.DONEIN INT:MUX.LONG.V2[0] INT:MUX.LONG.V2[2] ~INT:BUF.LONG.H3.0.SINGLE.V4 - INT:MUX.LONG.H3[0] INT:MUX.LONG.H5[1] INT:MUX.IMUX.BUFG.H[2] INT:MUX.IMUX.BUFG.H[4] INT:MUX.IMUX.BUFG.H[3] INT:MUX.IMUX.BUFG.H[5] INT:MUX.IMUX.BUFG.H[6] INT:MUX.IMUX.BUFG.H[0] - ~INT:PASS.DOUBLE.V0.1.0.OUT.STARTUP.Q2 ~INT:PASS.SINGLE.V2.0.OUT.STARTUP.Q2 ~INT:PASS.SINGLE.V6.0.OUT.STARTUP.Q2 INT:MUX.LONG.H4[3] INT:MUX.LONG.H4[1] - INT:MUX.LONG.H4[0] INT:MUX.LONG.H4[2] - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - INT:MUX.LONG.V1[0] INT:MUX.LONG.V1[3] INT:MUX.LONG.V1[1] INT:MUX.LONG.V3[0] INT:MUX.LONG.V3[3] INT:MUX.IMUX.STARTUP.GTS[1] INT:MUX.IMUX.STARTUP.GTS[2] INT:MUX.IMUX.STARTUP.GTS[3] INT:MUX.IMUX.STARTUP.GTS[4] INT:MUX.IMUX.STARTUP.GTS[5] INT:MUX.IMUX.STARTUP.GTS[0] INT:MUX.LONG.V2[3] INT:MUX.LONG.V2[1] ~INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E INT:MUX.LONG.V4[3] INT:MUX.LONG.V4[0] INT:MUX.LONG.V4[1] INT:MUX.LONG.V4[2] INT:MUX.LONG.H3[1] INT:MUX.LONG.H5[0] INT:MUX.LONG.H5[2] INT:MUX.LONG.H5[3] INT:MUX.IMUX.BUFG.H[1] INT:MUX.LONG.IO.V2[2] INT:MUX.LONG.IO.V0[2] INT:MUX.LONG.IO.V2[1] INT:MUX.LONG.IO.V2[0] ~PULLUP_DEC3_V:ENABLE ~PULLUP_DEC1_V:ENABLE ~INT:PASS.SINGLE.V6.0.LONG.IO.H3 ~PULLUP_DEC2_V:ENABLE ~PULLUP_DEC0_V:ENABLE INT:MUX.LONG.IO.V1[2] INT:MUX.LONG.IO.V1[0] INT:MUX.LONG.IO.V1[1] INT:MUX.LONG.IO.V2[3] INT:MUX.LONG.IO.V3[3] - OSC:MUX.OUT0[0] OSC:MUX.OUT1[0]
3 - ~PULLUP_DEC3_H:ENABLE ~PULLUP_DEC2_H:ENABLE ~PULLUP_DEC1_H:ENABLE ~INT:PASS.SINGLE.V7.0.OUT.BT.IOB1.I1.E INT:MUX.LONG.V5[3] ~INT:PASS.SINGLE.V7.0.DEC.H0 INT:MUX.LONG.V5[1] INT:MUX.LONG.V5[0] INT:MUX.LONG.V5[2] ~INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E ~INT:PASS.DOUBLE.V1.0.0.OUT.STARTUP.DONEIN ~INT:PASS.SINGLE.V5.0.LONG.IO.H2 ~INT:PASS.SINGLE.V5.0.OUT.STARTUP.DONEIN INT:MUX.LONG.IO.H3[2] INT:MUX.LONG.V0[0] INT:MUX.LONG.V0[1] INT:MUX.LONG.IO.V2[4] INT:MUX.LONG.V0[2] INT:MUX.LONG.IO.V0[3] INT:MUX.LONG.V0[3] ~INT:PASS.SINGLE.V2.0.LONG.IO.H1 ~INT:PASS.SINGLE.V1.0.LONG.IO.H0 INT:MUX.LONG.IO.V3[4] INT:MUX.LONG.IO.V0[0] INT:MUX.LONG.IO.V0[1] ~INT:PASS.SINGLE.V0.0.DEC.H3 ~INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E INT:MUX.LONG.IO.V3[0] INT:MUX.IO.DBUF.H0[2] INT:MUX.LONG.IO.V1[4] INT:MUX.IO.DBUF.H0[0] INT:MUX.IO.DBUF.H0[1] INT:MUX.IO.DBUF.H0[3] INT:MUX.LONG.IO.V3[2] INT:MUX.LONG.IO.V1[3] INT:MUX.LONG.IO.V3[1] OSC:MUX.OUT1[3] - OSC:MUX.OUT0[3] OSC:ENABLE
2 - ~PULLUP_DEC0_H:ENABLE INT:MUX.LONG.IO.H2[3] INT:MUX.LONG.IO.H2[2] INT:MUX.LONG.IO.H2[5] INT:MUX.LONG.IO.H3[3] INT:MUX.LONG.IO.H2[4] INT:MUX.LONG.IO.H1[5] INT:MUX.LONG.IO.H1[3] INT:MUX.LONG.IO.H1[2] INT:MUX.LONG.IO.H1[4] INT:MUX.LONG.IO.H0[3] INT:MUX.LONG.IO.H0[2] ~INT:BIPASS.IO.DOUBLE.1.E.1.IO.DOUBLE.1.S.2 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.1 ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.1 ~INT:BIPASS.IO.DOUBLE.0.E.1.IO.DOUBLE.0.S.2 INT:MUX.LONG.IO.H0[1] INT:MUX.LONG.IO.H0[0] - INT:MUX.LONG.IO.H2[0] INT:MUX.LONG.IO.H2[1] STARTUP:OUTPUTS_ACTIVE[1] STARTUP:OUTPUTS_ACTIVE[0] STARTUP:GSR_INACTIVE[0] STARTUP:GSR_INACTIVE[1] INT:MUX.LONG.IO.H1[1] INT:MUX.LONG.IO.H1[0] STARTUP:DONE_ACTIVE[1] INT:MUX.LONG.IO.H3[0] INT:MUX.LONG.IO.H3[1] - - - - - - - - - -
1 - INT:MUX.IO.DBUF.H1[2] INT:MUX.IO.DBUF.H1[3] ~INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.S.2 ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.S.2 ~INT:BIPASS.IO.DOUBLE.3.E.1.IO.DOUBLE.3.S.2 ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.S.1 ~INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.S.2 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.S.2 ~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.S.2 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.2 ~INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.S.1 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1 ~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.S.2 ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.2 ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1 ~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.1 ~INT:PASS.IO.DOUBLE.0.E.1.0.IO.DBUF.H1 ~INT:PASS.IO.DOUBLE.2.E.1.0.IO.DBUF.H1 ~INT:PASS.IO.DOUBLE.1.E.1.0.IO.DBUF.H1 INT:MUX.IMUX.BUFG.V[0] - - - - - - - - - - - - - - - - - - - ~STARTUP:CRC
0 - INT:MUX.IO.DBUF.H1[0] INT:MUX.IO.DBUF.H1[1] ~INT:BIPASS.SINGLE.V6.IO.DOUBLE.3.S.1 ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.1 ~INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.E.1 ~INT:PASS.IO.DOUBLE.3.S.2.0.IO.DBUF.H0 ~INT:PASS.IO.DOUBLE.2.S.2.0.IO.DBUF.H0 ~INT:PASS.IO.DOUBLE.1.S.2.0.IO.DBUF.H0 ~INT:PASS.IO.DOUBLE.0.S.2.0.IO.DBUF.H0 ~INT:BIPASS.IO.DOUBLE.2.E.1.IO.DOUBLE.2.S.2 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.S.1 ~INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.E.1 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.1 ~INT:BIPASS.SINGLE.V4.IO.DOUBLE.2.S.1 ~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.1 ~INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.S.1 ~INT:PASS.IO.DOUBLE.3.E.1.0.IO.DBUF.H1 - - - - - - - - - - STARTUP:DONE_ACTIVE[0] ~STARTUP:SYNC_TO_DONE STARTUP:STARTUP_CLK[0] ~STARTUP:INV.GSR ~STARTUP:ENABLE.GSR ~STARTUP:INV.GTS DONE:PULL[0] ~STARTUP:ENABLE.GTS ~MISC:TCTEST - - - STARTUP:CONFIG_RATE[0]
DONE:PULL 0.6.0
PULLUP 0
PULLNONE 1
INT:BIPASS.DOUBLE.H0.0.DOUBLE.H0.2 0.29.12
INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.0 0.27.12
INT:BIPASS.DOUBLE.H0.0.DOUBLE.V0.2 0.28.12
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.0 0.3.12
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.E.1 0.3.9
INT:BIPASS.DOUBLE.H0.0.IO.DOUBLE.1.S.1 0.1.12
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.0 0.14.9
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.E.1 0.11.12
INT:BIPASS.DOUBLE.H0.1.IO.DOUBLE.0.S.1 0.16.12
INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.0 0.29.10
INT:BIPASS.DOUBLE.H0.2.DOUBLE.V0.2 0.29.11
INT:BIPASS.DOUBLE.H1.0.DOUBLE.H1.2 0.33.9
INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.0 0.32.9
INT:BIPASS.DOUBLE.H1.0.DOUBLE.V1.2 0.33.7
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.E.0 0.2.10
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.E.1 0.4.9
INT:BIPASS.DOUBLE.H1.0.IO.DOUBLE.2.S.1 0.2.9
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.E.0 0.23.12
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.E.1 0.20.12
INT:BIPASS.DOUBLE.H1.1.IO.DOUBLE.3.S.1 0.19.12
INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.0 0.33.8
INT:BIPASS.DOUBLE.H1.2.DOUBLE.V1.2 0.34.8
INT:BIPASS.DOUBLE.V0.0.DOUBLE.V0.2 0.27.11
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1 0.28.1
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.1 0.26.2
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.S.2 0.30.1
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1 0.25.1
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.1 0.25.2
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.S.2 0.26.1
INT:BIPASS.DOUBLE.V1.0.DOUBLE.V1.2 0.34.7
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.1 0.27.0
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.S.1 0.29.0
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.S.2 0.32.1
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.1 0.36.0
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.S.1 0.34.1
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.S.2 0.36.1
INT:BIPASS.IO.DOUBLE.0.E.0.IO.DOUBLE.0.S.1 0.10.12
INT:BIPASS.IO.DOUBLE.0.E.1.IO.DOUBLE.0.S.2 0.24.2
INT:BIPASS.IO.DOUBLE.1.E.0.IO.DOUBLE.1.S.1 0.2.12
INT:BIPASS.IO.DOUBLE.1.E.1.IO.DOUBLE.1.S.2 0.27.2
INT:BIPASS.IO.DOUBLE.2.E.0.IO.DOUBLE.2.S.1 0.1.10
INT:BIPASS.IO.DOUBLE.2.E.1.IO.DOUBLE.2.S.2 0.30.0
INT:BIPASS.IO.DOUBLE.3.E.0.IO.DOUBLE.3.S.1 0.21.12
INT:BIPASS.IO.DOUBLE.3.E.1.IO.DOUBLE.3.S.2 0.35.1
INT:BIPASS.SINGLE.H0.E.SINGLE.V0 0.26.8
INT:BIPASS.SINGLE.H0.E.SINGLE.V0.S 0.28.8
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.E.0 0.13.9
INT:BIPASS.SINGLE.H0.IO.DOUBLE.0.S.1 0.17.12
INT:BIPASS.SINGLE.H0.SINGLE.H0.E 0.28.9
INT:BIPASS.SINGLE.H0.SINGLE.V0 0.27.8
INT:BIPASS.SINGLE.H0.SINGLE.V0.S 0.30.7
INT:BIPASS.SINGLE.H1.E.SINGLE.V1 0.30.9
INT:BIPASS.SINGLE.H1.E.SINGLE.V1.S 0.31.8
INT:BIPASS.SINGLE.H1.IO.DOUBLE.0.E.1 0.15.12
INT:BIPASS.SINGLE.H1.SINGLE.H1.E 0.30.8
INT:BIPASS.SINGLE.H1.SINGLE.V1 0.29.8
INT:BIPASS.SINGLE.H1.SINGLE.V1.S 0.29.7
INT:BIPASS.SINGLE.H2.E.SINGLE.V2 0.31.12
INT:BIPASS.SINGLE.H2.E.SINGLE.V2.S 0.32.12
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.E.0 0.4.12
INT:BIPASS.SINGLE.H2.IO.DOUBLE.1.S.1 0.0.12
INT:BIPASS.SINGLE.H2.SINGLE.H2.E 0.32.11
INT:BIPASS.SINGLE.H2.SINGLE.V2 0.31.11
INT:BIPASS.SINGLE.H2.SINGLE.V2.S 0.33.11
INT:BIPASS.SINGLE.H3.E.SINGLE.V3 0.32.10
INT:BIPASS.SINGLE.H3.E.SINGLE.V3.S 0.33.10
INT:BIPASS.SINGLE.H3.IO.DOUBLE.1.E.1 0.3.8
INT:BIPASS.SINGLE.H3.SINGLE.H3.E 0.31.10
INT:BIPASS.SINGLE.H3.SINGLE.V3 0.28.10
INT:BIPASS.SINGLE.H3.SINGLE.V3.S 0.30.10
INT:BIPASS.SINGLE.H4.E.SINGLE.V4 0.39.11
INT:BIPASS.SINGLE.H4.E.SINGLE.V4.S 0.37.9
INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.E.0 0.3.10
INT:BIPASS.SINGLE.H4.IO.DOUBLE.2.S.1 0.1.9
INT:BIPASS.SINGLE.H4.SINGLE.H4.E 0.36.9
INT:BIPASS.SINGLE.H4.SINGLE.V4 0.39.9
INT:BIPASS.SINGLE.H4.SINGLE.V4.S 0.35.9
INT:BIPASS.SINGLE.H5.E.SINGLE.V5 0.36.8
INT:BIPASS.SINGLE.H5.E.SINGLE.V5.S 0.38.8
INT:BIPASS.SINGLE.H5.IO.DOUBLE.2.E.1 0.2.8
INT:BIPASS.SINGLE.H5.SINGLE.H5.E 0.35.8
INT:BIPASS.SINGLE.H5.SINGLE.V5 0.36.7
INT:BIPASS.SINGLE.H5.SINGLE.V5.S 0.37.8
INT:BIPASS.SINGLE.H6.E.SINGLE.V6 0.34.10
INT:BIPASS.SINGLE.H6.E.SINGLE.V6.S 0.37.10
INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.E.0 0.24.12
INT:BIPASS.SINGLE.H6.IO.DOUBLE.3.S.1 0.18.12
INT:BIPASS.SINGLE.H6.SINGLE.H6.E 0.35.10
INT:BIPASS.SINGLE.H6.SINGLE.V6 0.36.11
INT:BIPASS.SINGLE.H6.SINGLE.V6.S 0.36.10
INT:BIPASS.SINGLE.H7.E.SINGLE.V7 0.37.12
INT:BIPASS.SINGLE.H7.E.SINGLE.V7.S 0.39.12
INT:BIPASS.SINGLE.H7.IO.DOUBLE.3.E.1 0.22.12
INT:BIPASS.SINGLE.H7.SINGLE.H7.E 0.38.12
INT:BIPASS.SINGLE.H7.SINGLE.V7 0.35.12
INT:BIPASS.SINGLE.H7.SINGLE.V7.S 0.37.11
INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.S.1 0.24.0
INT:BIPASS.SINGLE.V0.SINGLE.V0.S 0.29.9
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.1 0.24.1
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.S.2 0.27.1
INT:BIPASS.SINGLE.V1.SINGLE.V1.S 0.31.7
INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.S.1 0.29.1
INT:BIPASS.SINGLE.V2.SINGLE.V2.S 0.30.12
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.1 0.25.0
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.S.2 0.31.1
INT:BIPASS.SINGLE.V3.SINGLE.V3.S 0.27.10
INT:BIPASS.SINGLE.V4.IO.DOUBLE.2.S.1 0.26.0
INT:BIPASS.SINGLE.V4.SINGLE.V4.S 0.38.9
INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.E.1 0.28.0
INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.S.2 0.33.1
INT:BIPASS.SINGLE.V5.SINGLE.V5.S 0.39.8
INT:BIPASS.SINGLE.V6.IO.DOUBLE.3.S.1 0.37.0
INT:BIPASS.SINGLE.V6.SINGLE.V6.S 0.38.10
INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.E.1 0.35.0
INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.S.2 0.37.1
INT:BIPASS.SINGLE.V7.SINGLE.V7.S 0.36.12
INT:BUF.LONG.H3.0.SINGLE.V4 0.24.6
INT:BUF.LONG.H4.0.SINGLE.V5 0.19.8
INT:BUF.LONG.H5.0.SINGLE.V6 0.18.9
INT:BUF.LONG.V0.0.SINGLE.H1.E 0.17.8
INT:BUF.LONG.V1.0.SINGLE.H2.E 0.38.11
INT:BUF.LONG.V2.0.SINGLE.H3.E 0.19.9
INT:BUF.LONG.V3.0.SINGLE.H4 0.15.8
INT:BUF.LONG.V4.0.SINGLE.H5 0.16.8
INT:BUF.LONG.V5.0.SINGLE.H6 0.35.11
INT:PASS.DOUBLE.H0.0.0.OUT.STARTUP.Q1Q4 0.7.10
INT:PASS.DOUBLE.H0.1.0.OUT.LR.IOB1.I1.S 0.12.8
INT:PASS.DOUBLE.H1.0.0.OUT.LR.IOB1.I2.S 0.25.9
INT:PASS.DOUBLE.H1.1.0.OUT.STARTUP.Q3 0.21.9
INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E 0.13.3
INT:PASS.DOUBLE.V0.1.0.OUT.STARTUP.Q2 0.13.6
INT:PASS.DOUBLE.V1.0.0.OUT.STARTUP.DONEIN 0.29.3
INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E 0.38.6
INT:PASS.IO.DOUBLE.0.E.0.0.IO.DBUF.V0 0.14.8
INT:PASS.IO.DOUBLE.0.E.1.0.IO.DBUF.H1 0.23.1
INT:PASS.IO.DOUBLE.0.S.1.0.IO.DBUF.V1 0.10.9
INT:PASS.IO.DOUBLE.0.S.2.0.IO.DBUF.H0 0.31.0
INT:PASS.IO.DOUBLE.1.E.0.0.IO.DBUF.V0 0.13.8
INT:PASS.IO.DOUBLE.1.E.1.0.IO.DBUF.H1 0.21.1
INT:PASS.IO.DOUBLE.1.S.1.0.IO.DBUF.V1 0.7.9
INT:PASS.IO.DOUBLE.1.S.2.0.IO.DBUF.H0 0.32.0
INT:PASS.IO.DOUBLE.2.E.0.0.IO.DBUF.V0 0.11.9
INT:PASS.IO.DOUBLE.2.E.1.0.IO.DBUF.H1 0.22.1
INT:PASS.IO.DOUBLE.2.S.1.0.IO.DBUF.V1 0.9.9
INT:PASS.IO.DOUBLE.2.S.2.0.IO.DBUF.H0 0.33.0
INT:PASS.IO.DOUBLE.3.E.0.0.IO.DBUF.V0 0.12.9
INT:PASS.IO.DOUBLE.3.E.1.0.IO.DBUF.H1 0.23.0
INT:PASS.IO.DOUBLE.3.S.1.0.IO.DBUF.V1 0.8.9
INT:PASS.IO.DOUBLE.3.S.2.0.IO.DBUF.H0 0.34.0
INT:PASS.SINGLE.H0.0.DEC.V0 0.10.8
INT:PASS.SINGLE.H0.0.OUT.LR.IOB1.I2.S 0.24.9
INT:PASS.SINGLE.H1.0.LONG.IO.V0 0.16.9
INT:PASS.SINGLE.H1.0.OUT.STARTUP.Q3 0.20.9
INT:PASS.SINGLE.H1.E.0.LONG.V0 0.32.8
INT:PASS.SINGLE.H2.0.LONG.IO.V1 0.8.12
INT:PASS.SINGLE.H2.0.OUT.STARTUP.Q1Q4 0.6.10
INT:PASS.SINGLE.H2.E.0.LONG.V1 0.40.12
INT:PASS.SINGLE.H3.0.DEC.V1 0.5.10
INT:PASS.SINGLE.H3.0.OUT.LR.IOB1.I1.S 0.11.8
INT:PASS.SINGLE.H3.E.0.LONG.V2 0.34.9
INT:PASS.SINGLE.H4.0.DEC.V2 0.8.8
INT:PASS.SINGLE.H4.0.LONG.V3 0.35.7
INT:PASS.SINGLE.H4.0.OUT.LR.IOB1.I2.S 0.23.9
INT:PASS.SINGLE.H5.0.LONG.IO.V2 0.9.8
INT:PASS.SINGLE.H5.0.LONG.V4 0.28.7
INT:PASS.SINGLE.H5.0.OUT.STARTUP.Q3 0.22.9
INT:PASS.SINGLE.H6.0.LONG.IO.V3 0.15.9
INT:PASS.SINGLE.H6.0.LONG.V5 0.34.12
INT:PASS.SINGLE.H6.0.OUT.STARTUP.Q1Q4 0.8.10
INT:PASS.SINGLE.H7.0.DEC.V3 0.5.9
INT:PASS.SINGLE.H7.0.OUT.LR.IOB1.I1.S 0.6.9
INT:PASS.SINGLE.V0.0.DEC.H3 0.14.3
INT:PASS.SINGLE.V0.0.GND 0.26.9
INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E 0.26.4
INT:PASS.SINGLE.V1.0.LONG.IO.H0 0.18.3
INT:PASS.SINGLE.V1.0.OUT.STARTUP.DONEIN 0.27.6
INT:PASS.SINGLE.V2.0.LONG.IO.H1 0.19.3
INT:PASS.SINGLE.V2.0.OUT.STARTUP.Q2 0.12.6
INT:PASS.SINGLE.V3.0.DEC.H2 0.36.6
INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E 0.30.3
INT:PASS.SINGLE.V4.0.DEC.H1 0.39.6
INT:PASS.SINGLE.V4.0.LONG.H3 0.26.10
INT:PASS.SINGLE.V4.0.OUT.BT.IOB1.I2.E 0.40.6
INT:PASS.SINGLE.V5.0.LONG.H4 0.40.8
INT:PASS.SINGLE.V5.0.LONG.IO.H2 0.28.3
INT:PASS.SINGLE.V5.0.OUT.STARTUP.DONEIN 0.27.3
INT:PASS.SINGLE.V6.0.LONG.H5 0.40.10
INT:PASS.SINGLE.V6.0.LONG.IO.H3 0.10.4
INT:PASS.SINGLE.V6.0.OUT.STARTUP.Q2 0.11.6
INT:PASS.SINGLE.V7.0.DEC.H0 0.34.3
INT:PASS.SINGLE.V7.0.GND 0.26.12
INT:PASS.SINGLE.V7.0.OUT.BT.IOB1.I1.E 0.36.3
MISC:TCTEST 0.4.0
PULLUP_DEC0_H:ENABLE 0.39.2
PULLUP_DEC0_V:ENABLE 0.8.4
PULLUP_DEC1_H:ENABLE 0.37.3
PULLUP_DEC1_V:ENABLE 0.11.4
PULLUP_DEC2_H:ENABLE 0.38.3
PULLUP_DEC2_V:ENABLE 0.9.4
PULLUP_DEC3_H:ENABLE 0.39.3
PULLUP_DEC3_V:ENABLE 0.12.4
STARTUP:CRC 0.0.1
STARTUP:ENABLE.GSR 0.8.0
STARTUP:ENABLE.GTS 0.5.0
STARTUP:INV.GSR 0.9.0
STARTUP:INV.GTS 0.7.0
STARTUP:SYNC_TO_DONE 0.11.0
inverted ~[0]
INT:MUX.IMUX.BUFG.H 0.16.6 0.17.6 0.19.6 0.18.6 0.20.6 0.17.4 0.15.6
0.IO.DOUBLE.3.E.1 0 0 0 1 1 0 1
0.IO.DOUBLE.0.E.1 0 0 0 1 1 1 1
0.IO.DOUBLE.2.S.1 0 0 1 0 1 0 1
0.IO.DOUBLE.0.S.1 0 0 1 0 1 1 1
0.IO.DOUBLE.3.S.1 0 0 1 1 0 0 1
0.IO.DOUBLE.1.E.1 0 0 1 1 0 1 1
0.IO.DOUBLE.1.S.1 0 1 1 1 1 0 1
0.IO.DOUBLE.2.E.1 0 1 1 1 1 1 1
0.OUT.IOB.CLKIN.E 1 0 1 1 1 1 0
NONE 1 0 1 1 1 1 1
INT:MUX.IMUX.BUFG.V 0.20.1
0.OUT.IOB.CLKIN.S 0
NONE 1
INT:MUX.IMUX.READCLK.I 0.4.8 0.7.8 0.6.8 0.5.8
0.SINGLE.H2 0 0 1 1
0.SINGLE.H3 0 1 0 1
0.SINGLE.H4 0 1 1 0
0.SINGLE.H5 1 1 1 1
INT:MUX.IMUX.STARTUP.CLK 0.37.7 0.38.7 0.39.7 0.40.7
0.SINGLE.V3 0 0 1 1
0.SINGLE.V4 0 1 0 1
0.SINGLE.V5 0 1 1 0
0.SINGLE.V2 1 1 1 1
INT:MUX.IMUX.STARTUP.GSR 0.29.6 0.28.6 0.33.6 0.31.6 0.30.6 0.32.6
0.SINGLE.H2 0 0 0 1 1 1
0.SINGLE.H3 0 0 1 0 1 1
0.LONG.V4 0 0 1 1 1 0
0.LONG.V5 0 1 0 1 1 1
0.DOUBLE.V1.1 0 1 1 0 1 1
0.SINGLE.H4 0 1 1 1 0 1
0.LONG.V3 0 1 1 1 1 0
0.DOUBLE.V0.0 1 0 1 1 1 1
0.SINGLE.H5 1 1 1 1 1 1
INT:MUX.IMUX.STARTUP.GTS 0.30.4 0.31.4 0.32.4 0.33.4 0.34.4 0.29.4
0.LONG.H3 0 0 1 1 1 0
0.SINGLE.V2 0 0 1 1 1 1
0.SINGLE.V3 0 1 0 1 1 1
0.LONG.H5 0 1 1 0 1 0
0.SINGLE.V4 0 1 1 0 1 1
0.LONG.H4 0 1 1 1 0 0
0.SINGLE.V5 0 1 1 1 0 1
0.DOUBLE.H1.0 1 1 1 1 1 0
0.DOUBLE.H0.1 1 1 1 1 1 1
INT:MUX.IO.DBUF.H0 0.7.3 0.11.3 0.8.3 0.9.3
0.IO.DOUBLE.0.E.1 0 0 1 1
0.IO.DOUBLE.2.E.1 0 1 0 1
0.IO.DOUBLE.3.E.1 0 1 1 0
0.IO.DOUBLE.1.E.1 1 1 1 1
INT:MUX.IO.DBUF.H1 0.38.1 0.39.1 0.38.0 0.39.0
0.IO.DOUBLE.1.S.2 0 0 1 1
0.IO.DOUBLE.2.S.2 0 1 0 1
0.IO.DOUBLE.3.S.2 0 1 1 0
0.IO.DOUBLE.0.S.2 1 1 1 1
INT:MUX.IO.DBUF.V0 0.4.10 0.5.12 0.7.12 0.6.12
0.IO.DOUBLE.1.S.1 0 0 1 1
0.IO.DOUBLE.2.S.1 0 1 0 1
0.IO.DOUBLE.3.S.1 0 1 1 0
0.IO.DOUBLE.0.S.1 1 1 1 1
INT:MUX.IO.DBUF.V1 0.9.12 0.13.12 0.12.12 0.14.12
0.IO.DOUBLE.0.E.0 0 0 1 1
0.IO.DOUBLE.1.E.0 0 1 0 1
0.IO.DOUBLE.3.E.0 0 1 1 0
0.IO.DOUBLE.2.E.0 1 1 1 1
INT:MUX.LONG.H3 0.21.4 0.22.6
0.LONG.IO.V1 0 0
0.DEC.V2 0 1
NONE 1 1
INT:MUX.LONG.H4 0.10.6 0.6.6 0.9.6 0.7.6
0.LONG.IO.V2 0 0 0 1
0.DEC.V1 0 0 1 0
0.OUT.STARTUP.Q3 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.H5 0.18.4 0.19.4 0.21.6 0.20.4
0.LONG.IO.V3 0 0 0 1
0.DEC.V0 0 0 1 0
0.OUT.STARTUP.Q3 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.H0 0.29.2 0.28.2 0.23.2 0.22.2
0.LONG.V0 0 0 1 1
0.SINGLE.V1 0 1 1 1
0.LONG.IO.V2 1 1 0 0
0.LONG.IO.V0 1 1 0 1
NONE 1 1 1 1
INT:MUX.LONG.IO.H1 0.33.2 0.30.2 0.32.2 0.31.2 0.14.2 0.13.2
0.LONG.V1 0 0 0 1 1 1
0.LONG.V3 0 0 1 0 1 1
0.SINGLE.V2 0 1 1 1 1 1
0.LONG.IO.V3 1 1 1 1 0 0
0.LONG.IO.V1 1 1 1 1 0 1
NONE 1 1 1 1 1 1
INT:MUX.LONG.IO.H2 0.36.2 0.34.2 0.38.2 0.37.2 0.19.2 0.20.2
0.LONG.V2 0 0 0 1 1 1
0.LONG.V4 0 0 1 0 1 1
0.SINGLE.V5 0 1 1 1 1 1
0.LONG.IO.V0 1 1 1 1 0 0
0.LONG.IO.V2 1 1 1 1 0 1
NONE 1 1 1 1 1 1
INT:MUX.LONG.IO.H3 0.35.2 0.26.3 0.10.2 0.11.2
0.LONG.V5 0 0 1 1
0.SINGLE.V6 0 1 1 1
0.LONG.IO.V1 1 1 0 0
0.LONG.IO.V3 1 1 0 1
NONE 1 1 1 1
INT:MUX.LONG.IO.V0 0.21.3 0.15.4 0.15.3 0.16.3
0.LONG.IO.H0 0 0 0 1
0.LONG.IO.H2 0 0 1 0
0.SINGLE.H1 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.V1 0.10.3 0.5.3 0.7.4 0.5.4 0.6.4
0.LONG.H3 0 0 0 1 1
0.LONG.IO.H1 0 0 1 0 1
0.LONG.IO.H3 0 0 1 1 0
0.SINGLE.H2 0 1 1 1 1
NONE 1 1 1 1 1
INT:MUX.LONG.IO.V2 0.23.3 0.4.4 0.16.4 0.14.4 0.13.4
0.LONG.H4 0 0 0 1 1
0.LONG.IO.H0 0 0 1 0 1
0.LONG.IO.H2 0 0 1 1 0
0.SINGLE.H5 0 1 1 1 1
NONE 1 1 1 1 1
INT:MUX.LONG.IO.V3 0.17.3 0.3.4 0.6.3 0.4.3 0.12.3
0.LONG.H5 0 0 0 1 1
0.LONG.IO.H1 0 0 1 0 1
0.LONG.IO.H3 0 0 1 1 0
0.SINGLE.H6 0 1 1 1 1
NONE 1 1 1 1 1
INT:MUX.LONG.V0 0.20.3 0.22.3 0.24.3 0.25.3
0.LONG.IO.H0 0 0 0 1
0.DEC.H0 0 0 1 0
0.OUT.BT.IOB1.I2.E 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V1 0.38.4 0.37.6 0.37.4 0.39.4
0.LONG.IO.H1 0 0 0 1
0.DEC.H1 0 0 1 0
0.OUT.BT.IOB1.I2.E 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V2 0.28.4 0.25.6 0.27.4 0.26.6
0.LONG.IO.H2 0 0 0 1
0.DEC.H2 0 0 1 0
0.OUT.BT.IOB1.I2.E 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V3 0.35.4 0.34.6 0.35.6 0.36.4
0.LONG.IO.H1 0 0 0 1
0.DEC.H1 0 0 1 0
0.OUT.STARTUP.DONEIN 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V4 0.25.4 0.22.4 0.23.4 0.24.4
0.LONG.IO.H2 0 0 0 1
0.DEC.H2 0 0 1 0
0.OUT.STARTUP.DONEIN 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V5 0.35.3 0.31.3 0.33.3 0.32.3
0.LONG.IO.H3 0 0 0 1
0.DEC.H3 0 0 1 0
0.OUT.STARTUP.DONEIN 0 1 1 1
NONE 1 1 1 1
OSC:ENABLE 0.0.3
non-inverted [0]
OSC:MUX.OUT0 0.1.3 0.0.10 0.1.8 0.1.4
OSC:MUX.OUT1 0.3.3 0.0.9 0.0.8 0.0.4
F500K 0 0 1 1
F16K 0 1 0 1
F490 0 1 1 0
F15 1 1 1 1
STARTUP:CONFIG_RATE 0.0.0
FAST 0
SLOW 1
STARTUP:DONE_ACTIVE 0.12.2 0.12.0
Q2 0 0
Q3 0 1
Q1Q4 1 0
Q0 1 1
STARTUP:GSR_INACTIVE 0.15.2 0.16.2
DONE_IN 0 0
Q3 0 1
Q1Q4 1 0
Q2 1 1
STARTUP:OUTPUTS_ACTIVE 0.18.2 0.17.2
Q3 0 0
DONE_IN 0 1
Q2 1 0
Q1Q4 1 1
STARTUP:STARTUP_CLK 0.10.0
CCLK 0
USERCLK 1

Tile CNR.TR

Cells: 2

Switchbox INT

xc4000h CNR.TR switchbox INT
DestinationSourceKind
TCELL0_SINGLE.V0TCELL0_DEC.H0pass transistor
TCELL0_OUT.BT.IOB1.I2.Epass transistor
TCELL0_IO.DOUBLE.0.E.1bidirectional pass transistor
TCELL0_SINGLE.V1TCELL0_LONG.H0pass transistor
TCELL0_LONG.IO.H0pass transistor
TCELL0_OUT.OSC.MUX1pass transistor
TCELL0_IO.DOUBLE.0.N.0bidirectional pass transistor
TCELL0_IO.DOUBLE.0.E.2bidirectional pass transistor
TCELL0_SINGLE.V2TCELL0_LONG.H1pass transistor
TCELL0_LONG.IO.H1pass transistor
TCELL0_OUT.UPDATE.Opass transistor
TCELL0_IO.DOUBLE.1.E.1bidirectional pass transistor
TCELL0_SINGLE.V3TCELL0_LONG.H2pass transistor
TCELL0_DEC.H1pass transistor
TCELL0_OUT.BT.IOB1.I1.Epass transistor
TCELL0_IO.DOUBLE.1.N.0bidirectional pass transistor
TCELL0_IO.DOUBLE.1.E.2bidirectional pass transistor
TCELL0_SINGLE.V4TCELL0_DEC.H2pass transistor
TCELL0_OUT.BT.IOB1.I2.Epass transistor
TCELL0_IO.DOUBLE.2.E.1bidirectional pass transistor
TCELL0_SINGLE.V5TCELL0_LONG.IO.H2pass transistor
TCELL0_OUT.OSC.MUX1pass transistor
TCELL0_IO.DOUBLE.2.N.0bidirectional pass transistor
TCELL0_IO.DOUBLE.2.E.2bidirectional pass transistor
TCELL0_SINGLE.V6TCELL0_LONG.IO.H3pass transistor
TCELL0_OUT.UPDATE.Opass transistor
TCELL0_IO.DOUBLE.3.E.1bidirectional pass transistor
TCELL0_SINGLE.V7TCELL0_DEC.H3pass transistor
TCELL0_OUT.BT.IOB1.I1.Epass transistor
TCELL0_IO.DOUBLE.3.N.0bidirectional pass transistor
TCELL0_IO.DOUBLE.3.E.2bidirectional pass transistor
TCELL0_DOUBLE.V0.0TCELL0_OUT.BT.IOB1.I1.Epass transistor
TCELL0_IO.DOUBLE.1.N.0bidirectional pass transistor
TCELL0_IO.DOUBLE.1.E.1bidirectional pass transistor
TCELL0_IO.DOUBLE.1.E.2bidirectional pass transistor
TCELL0_DOUBLE.V0.1TCELL0_OUT.UPDATE.Opass transistor
TCELL0_IO.DOUBLE.0.N.0bidirectional pass transistor
TCELL0_IO.DOUBLE.0.E.1bidirectional pass transistor
TCELL0_IO.DOUBLE.0.E.2bidirectional pass transistor
TCELL0_DOUBLE.V1.0TCELL0_OUT.OSC.MUX1pass transistor
TCELL0_IO.DOUBLE.2.N.0bidirectional pass transistor
TCELL0_IO.DOUBLE.2.E.1bidirectional pass transistor
TCELL0_IO.DOUBLE.2.E.2bidirectional pass transistor
TCELL0_DOUBLE.V1.1TCELL0_OUT.BT.IOB1.I2.Epass transistor
TCELL0_IO.DOUBLE.3.N.0bidirectional pass transistor
TCELL0_IO.DOUBLE.3.E.1bidirectional pass transistor
TCELL0_IO.DOUBLE.3.E.2bidirectional pass transistor
TCELL0_IO.DOUBLE.0.N.0TCELL0_IO.DBUF.H0pass transistor
TCELL0_SINGLE.V1bidirectional pass transistor
TCELL0_DOUBLE.V0.1bidirectional pass transistor
TCELL0_IO.DOUBLE.0.E.2bidirectional pass transistor
TCELL0_IO.DOUBLE.0.E.1TCELL0_SINGLE.V0bidirectional pass transistor
TCELL0_DOUBLE.V0.1bidirectional pass transistor
TCELL0_IO.DOUBLE.0.E.2TCELL0_IO.DBUF.H1pass transistor
TCELL0_SINGLE.V1bidirectional pass transistor
TCELL0_DOUBLE.V0.1bidirectional pass transistor
TCELL0_IO.DOUBLE.0.N.0bidirectional pass transistor
TCELL0_IO.DOUBLE.1.N.0TCELL0_IO.DBUF.H0pass transistor
TCELL0_SINGLE.V3bidirectional pass transistor
TCELL0_DOUBLE.V0.0bidirectional pass transistor
TCELL0_IO.DOUBLE.1.E.2bidirectional pass transistor
TCELL0_IO.DOUBLE.1.E.1TCELL0_SINGLE.V2bidirectional pass transistor
TCELL0_DOUBLE.V0.0bidirectional pass transistor
TCELL0_IO.DOUBLE.1.E.2TCELL0_IO.DBUF.H1pass transistor
TCELL0_SINGLE.V3bidirectional pass transistor
TCELL0_DOUBLE.V0.0bidirectional pass transistor
TCELL0_IO.DOUBLE.1.N.0bidirectional pass transistor
TCELL0_IO.DOUBLE.2.N.0TCELL0_IO.DBUF.H0pass transistor
TCELL0_SINGLE.V5bidirectional pass transistor
TCELL0_DOUBLE.V1.0bidirectional pass transistor
TCELL0_IO.DOUBLE.2.E.2bidirectional pass transistor
TCELL0_IO.DOUBLE.2.E.1TCELL0_SINGLE.V4bidirectional pass transistor
TCELL0_DOUBLE.V1.0bidirectional pass transistor
TCELL0_IO.DOUBLE.2.E.2TCELL0_IO.DBUF.H1pass transistor
TCELL0_SINGLE.V5bidirectional pass transistor
TCELL0_DOUBLE.V1.0bidirectional pass transistor
TCELL0_IO.DOUBLE.2.N.0bidirectional pass transistor
TCELL0_IO.DOUBLE.3.N.0TCELL0_IO.DBUF.H0pass transistor
TCELL0_SINGLE.V7bidirectional pass transistor
TCELL0_DOUBLE.V1.1bidirectional pass transistor
TCELL0_IO.DOUBLE.3.E.2bidirectional pass transistor
TCELL0_IO.DOUBLE.3.E.1TCELL0_SINGLE.V6bidirectional pass transistor
TCELL0_DOUBLE.V1.1bidirectional pass transistor
TCELL0_IO.DOUBLE.3.E.2TCELL0_IO.DBUF.H1pass transistor
TCELL0_SINGLE.V7bidirectional pass transistor
TCELL0_DOUBLE.V1.1bidirectional pass transistor
TCELL0_IO.DOUBLE.3.N.0bidirectional pass transistor
TCELL0_IO.DBUF.H0TCELL0_IO.DOUBLE.0.E.2mux
TCELL0_IO.DOUBLE.1.E.2mux
TCELL0_IO.DOUBLE.2.E.2mux
TCELL0_IO.DOUBLE.3.E.2mux
TCELL0_IO.DBUF.H1TCELL0_IO.DOUBLE.0.N.0mux
TCELL0_IO.DOUBLE.1.N.0mux
TCELL0_IO.DOUBLE.2.N.0mux
TCELL0_IO.DOUBLE.3.N.0mux
TCELL0_LONG.H0TCELL0_LONG.IO.V0mux
TCELL0_DEC.V3mux
TCELL0_OUT.LR.IOB1.I2mux
TCELL0_SINGLE.V1buffer
TCELL0_LONG.H1TCELL0_LONG.IO.V1mux
TCELL0_DEC.V2mux
TCELL0_OUT.LR.IOB1.I2mux
TCELL0_SINGLE.V2buffer
TCELL0_LONG.H2TCELL0_LONG.IO.V2mux
TCELL0_DEC.V1mux
TCELL0_SINGLE.V3buffer
TCELL0_LONG.V0TCELL0_LONG.IO.H0mux
TCELL0_DEC.H3mux
TCELL0_OUT.BT.IOB1.I2.Emux
TCELL0_LONG.V1TCELL0_LONG.IO.H1mux
TCELL0_DEC.H2mux
TCELL0_OUT.BT.IOB1.I2.Emux
TCELL0_LONG.V2TCELL0_LONG.IO.H2mux
TCELL0_DEC.H1mux
TCELL0_OUT.BT.IOB1.I2.Emux
TCELL0_LONG.V3TCELL0_LONG.IO.H1mux
TCELL0_DEC.H2mux
TCELL0_OUT.OSC.MUX1mux
TCELL0_LONG.V4TCELL0_LONG.IO.H2mux
TCELL0_DEC.H1mux
TCELL0_OUT.OSC.MUX1mux
TCELL0_LONG.V5TCELL0_LONG.IO.H3mux
TCELL0_DEC.H0mux
TCELL0_OUT.OSC.MUX1mux
TCELL0_LONG.IO.H0TCELL0_SINGLE.V1mux
TCELL0_LONG.V0mux
TCELL0_LONG.IO.V0mux
TCELL0_LONG.IO.V2mux
TCELL0_LONG.IO.H1TCELL0_SINGLE.V2mux
TCELL0_LONG.V1mux
TCELL0_LONG.V3mux
TCELL0_LONG.IO.V1mux
TCELL0_LONG.IO.V3mux
TCELL0_LONG.IO.H2TCELL0_SINGLE.V5mux
TCELL0_LONG.V2mux
TCELL0_LONG.V4mux
TCELL0_LONG.IO.V0mux
TCELL0_LONG.IO.V2mux
TCELL0_LONG.IO.H3TCELL0_SINGLE.V6mux
TCELL0_LONG.V5mux
TCELL0_LONG.IO.V1mux
TCELL0_LONG.IO.V3mux
TCELL0_LONG.IO.V0TCELL0_LONG.H0mux
TCELL0_LONG.IO.H0mux
TCELL0_LONG.IO.H2mux
TCELL0_LONG.IO.V1TCELL0_LONG.H1mux
TCELL0_LONG.IO.H1mux
TCELL0_LONG.IO.H3mux
TCELL0_LONG.IO.V2TCELL0_LONG.H2mux
TCELL0_LONG.IO.H0mux
TCELL0_LONG.IO.H2mux
TCELL0_LONG.IO.V3TCELL0_LONG.IO.H1mux
TCELL0_LONG.IO.H3mux
TCELL0_IMUX.BUFG.HTCELL0_OUT.IOB.CLKIN.Emux
TCELL0_IMUX.BUFG.VTCELL0_IO.DOUBLE.0.E.1mux
TCELL0_IO.DOUBLE.0.E.2mux
TCELL0_IO.DOUBLE.1.E.1mux
TCELL0_IO.DOUBLE.1.E.2mux
TCELL0_IO.DOUBLE.2.E.1mux
TCELL0_IO.DOUBLE.2.E.2mux
TCELL0_IO.DOUBLE.3.E.1mux
TCELL0_IO.DOUBLE.3.E.2mux
TCELL0_OUT.IOB.CLKIN.Nmux
TCELL0_IMUX.TDO.OTCELL0_SINGLE.V2mux
TCELL0_SINGLE.V3mux
TCELL0_SINGLE.V4mux
TCELL0_SINGLE.V5mux
TCELL0_LONG.H0mux
TCELL0_LONG.H1mux
TCELL0_LONG.H2mux
TCELL1_DOUBLE.H0.0mux
TCELL1_DOUBLE.H1.1mux
TCELL0_IMUX.TDO.TTCELL0_DOUBLE.V0.0mux
TCELL0_DOUBLE.V1.1mux
TCELL0_LONG.V3mux
TCELL0_LONG.V4mux
TCELL0_LONG.V5mux
TCELL1_SINGLE.H2mux
TCELL1_SINGLE.H3mux
TCELL1_SINGLE.H4mux
TCELL1_SINGLE.H5mux

Bel PULLUP_DEC0_H

xc4000h CNR.TR bel PULLUP_DEC0_H
PinDirectionWires
OoutputTCELL0:DEC.H0

Bel PULLUP_DEC1_H

xc4000h CNR.TR bel PULLUP_DEC1_H
PinDirectionWires
OoutputTCELL0:DEC.H1

Bel PULLUP_DEC2_H

xc4000h CNR.TR bel PULLUP_DEC2_H
PinDirectionWires
OoutputTCELL0:DEC.H2

Bel PULLUP_DEC3_H

xc4000h CNR.TR bel PULLUP_DEC3_H
PinDirectionWires
OoutputTCELL0:DEC.H3

Bel PULLUP_DEC0_V

xc4000h CNR.TR bel PULLUP_DEC0_V
PinDirectionWires
OoutputTCELL0:DEC.V0

Bel PULLUP_DEC1_V

xc4000h CNR.TR bel PULLUP_DEC1_V
PinDirectionWires
OoutputTCELL0:DEC.V1

Bel PULLUP_DEC2_V

xc4000h CNR.TR bel PULLUP_DEC2_V
PinDirectionWires
OoutputTCELL0:DEC.V2

Bel PULLUP_DEC3_V

xc4000h CNR.TR bel PULLUP_DEC3_V
PinDirectionWires
OoutputTCELL0:DEC.V3

Bel BUFGLS_H

xc4000h CNR.TR bel BUFGLS_H
PinDirectionWires
IinputTCELL0:IMUX.BUFG.H

Bel BUFGLS_V

xc4000h CNR.TR bel BUFGLS_V
PinDirectionWires
IinputTCELL0:IMUX.BUFG.V

Bel COUT

xc4000h CNR.TR bel COUT
PinDirectionWires

Bel UPDATE

xc4000h CNR.TR bel UPDATE
PinDirectionWires
OoutputTCELL0:OUT.UPDATE.O

Bel OSC

xc4000h CNR.TR bel OSC
PinDirectionWires
F8MoutputTCELL0:OUT.LR.IOB1.I1
OUT0outputTCELL0:OUT.LR.IOB1.I2
OUT1outputTCELL0:OUT.OSC.MUX1

Bel TDO

xc4000h CNR.TR bel TDO
PinDirectionWires
OinputTCELL0:IMUX.TDO.O
TinputTCELL0:IMUX.TDO.T

Bel wires

xc4000h CNR.TR bel wires
WirePins
TCELL0:DEC.H0PULLUP_DEC0_H.O
TCELL0:DEC.H1PULLUP_DEC1_H.O
TCELL0:DEC.H2PULLUP_DEC2_H.O
TCELL0:DEC.H3PULLUP_DEC3_H.O
TCELL0:DEC.V0PULLUP_DEC0_V.O
TCELL0:DEC.V1PULLUP_DEC1_V.O
TCELL0:DEC.V2PULLUP_DEC2_V.O
TCELL0:DEC.V3PULLUP_DEC3_V.O
TCELL0:IMUX.BUFG.HBUFGLS_H.I
TCELL0:IMUX.BUFG.VBUFGLS_V.I
TCELL0:IMUX.TDO.OTDO.O
TCELL0:IMUX.TDO.TTDO.T
TCELL0:OUT.LR.IOB1.I1OSC.F8M
TCELL0:OUT.LR.IOB1.I2OSC.OUT0
TCELL0:OUT.OSC.MUX1OSC.OUT1
TCELL0:OUT.UPDATE.OUPDATE.O

Bitstream

xc4000h CNR.TR bittile 0
BitFrame
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
6 - INT:MUX.IO.DBUF.H1[0] INT:MUX.IO.DBUF.H1[1] ~INT:BIPASS.SINGLE.V6.IO.DOUBLE.3.E.1 ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.2 ~INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.E.2 ~INT:PASS.IO.DOUBLE.3.N.0.0.IO.DBUF.H0 ~INT:PASS.IO.DOUBLE.2.N.0.0.IO.DBUF.H0 ~INT:PASS.IO.DOUBLE.1.N.0.0.IO.DBUF.H0 ~INT:PASS.IO.DOUBLE.0.N.0.0.IO.DBUF.H0 ~INT:BIPASS.IO.DOUBLE.2.N.0.IO.DOUBLE.2.E.2 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.1 ~INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.E.2 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.2 ~INT:BIPASS.SINGLE.V4.IO.DOUBLE.2.E.1 ~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.2 ~INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.E.1 ~INT:PASS.IO.DOUBLE.3.E.2.0.IO.DBUF.H1 - - - - - - - - - - - - - - - - - - - - - - -
5 - INT:MUX.IO.DBUF.H1[2] INT:MUX.IO.DBUF.H1[3] ~INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.N.0 ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.N.0 ~INT:BIPASS.IO.DOUBLE.3.N.0.IO.DOUBLE.3.E.2 ~INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.1 ~INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.N.0 ~INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.N.0 ~INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.N.0 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.N.0 ~INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.E.1 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.2 ~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.N.0 ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.N.0 ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.2 ~INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.2 ~INT:PASS.IO.DOUBLE.0.E.2.0.IO.DBUF.H1 ~INT:PASS.IO.DOUBLE.2.E.2.0.IO.DBUF.H1 ~INT:PASS.IO.DOUBLE.1.E.2.0.IO.DBUF.H1 INT:MUX.IMUX.BUFG.H[0] - - - - - - - - - - - - - - - - - - - -
4 - ~PULLUP_DEC3_H:ENABLE INT:MUX.LONG.IO.H2[3] INT:MUX.LONG.IO.H2[2] INT:MUX.LONG.IO.H2[5] INT:MUX.LONG.IO.H3[3] INT:MUX.LONG.IO.H2[4] INT:MUX.LONG.IO.H1[5] INT:MUX.LONG.IO.H1[3] INT:MUX.LONG.IO.H1[2] INT:MUX.LONG.IO.H1[4] INT:MUX.LONG.IO.H0[3] INT:MUX.LONG.IO.H0[2] ~INT:BIPASS.IO.DOUBLE.1.N.0.IO.DOUBLE.1.E.2 ~INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1 ~INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1 ~INT:BIPASS.IO.DOUBLE.0.N.0.IO.DOUBLE.0.E.2 INT:MUX.LONG.IO.H0[1] INT:MUX.LONG.IO.H0[0] - INT:MUX.LONG.IO.H2[0] INT:MUX.LONG.IO.H2[1] TDO:PULL[1] BSCAN:ENABLE TDO:PULL[0] ~MISC:TAC INT:MUX.LONG.IO.H1[1] INT:MUX.LONG.IO.H1[0] READCLK:READ_CLK[0] INT:MUX.LONG.IO.H3[0] INT:MUX.LONG.IO.H3[1] - ~TDO:ENABLE.O ~TDO:ENABLE.T - - - - - - -
3 - ~PULLUP_DEC0_H:ENABLE ~PULLUP_DEC1_H:ENABLE ~PULLUP_DEC2_H:ENABLE ~INT:PASS.SINGLE.V7.0.OUT.BT.IOB1.I1.E INT:MUX.LONG.V5[3] ~INT:PASS.SINGLE.V7.0.DEC.H3 INT:MUX.LONG.V5[1] INT:MUX.LONG.V5[0] INT:MUX.LONG.V5[2] ~INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E ~INT:PASS.DOUBLE.V1.0.0.OUT.OSC.MUX1 ~INT:PASS.SINGLE.V5.0.LONG.IO.H2 ~INT:PASS.SINGLE.V5.0.OUT.OSC.MUX1 INT:MUX.LONG.IO.H3[2] INT:MUX.LONG.V0[0] INT:MUX.LONG.V0[1] INT:MUX.LONG.IO.V2[3] INT:MUX.LONG.V0[2] INT:MUX.LONG.IO.V0[3] INT:MUX.LONG.V0[3] ~INT:PASS.SINGLE.V2.0.LONG.IO.H1 ~INT:PASS.SINGLE.V1.0.LONG.IO.H0 INT:MUX.LONG.IO.V3[1] INT:MUX.LONG.IO.V0[0] INT:MUX.LONG.IO.V0[2] ~INT:PASS.SINGLE.V0.0.DEC.H0 ~INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E INT:MUX.LONG.IO.V3[0] INT:MUX.IO.DBUF.H0[2] INT:MUX.LONG.IO.V1[3] INT:MUX.IO.DBUF.H0[0] INT:MUX.IO.DBUF.H0[1] INT:MUX.IO.DBUF.H0[3] - - - - - - -
2 - INT:MUX.LONG.V1[0] INT:MUX.LONG.V1[3] INT:MUX.LONG.V1[1] INT:MUX.LONG.V3[0] INT:MUX.LONG.V3[3] INT:MUX.IMUX.TDO.O[1] INT:MUX.IMUX.TDO.O[2] INT:MUX.IMUX.TDO.O[3] INT:MUX.IMUX.TDO.O[4] INT:MUX.IMUX.TDO.O[5] INT:MUX.IMUX.TDO.O[0] INT:MUX.LONG.V2[3] INT:MUX.LONG.V2[1] ~INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E INT:MUX.LONG.V4[3] INT:MUX.LONG.V4[0] INT:MUX.LONG.V4[1] INT:MUX.LONG.V4[2] INT:MUX.LONG.H2[1] INT:MUX.LONG.H0[0] INT:MUX.LONG.H0[2] INT:MUX.LONG.H0[3] INT:MUX.IMUX.BUFG.V[2] INT:MUX.LONG.IO.V2[1] INT:MUX.LONG.IO.V0[1] INT:MUX.LONG.IO.V2[0] INT:MUX.LONG.IO.V2[2] ~PULLUP_DEC3_V:ENABLE ~PULLUP_DEC1_V:ENABLE ~INT:PASS.SINGLE.V6.0.LONG.IO.H3 ~PULLUP_DEC2_V:ENABLE ~PULLUP_DEC0_V:ENABLE INT:MUX.LONG.IO.V1[1] INT:MUX.LONG.IO.V1[0] INT:MUX.LONG.IO.V1[2] - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 ~INT:PASS.SINGLE.V4.0.OUT.BT.IOB1.I2.E ~INT:PASS.SINGLE.V4.0.DEC.H2 ~INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E INT:MUX.LONG.V1[2] ~INT:PASS.SINGLE.V3.0.DEC.H1 INT:MUX.LONG.V3[1] INT:MUX.LONG.V3[2] INT:MUX.IMUX.TDO.T[1] INT:MUX.IMUX.TDO.T[2] INT:MUX.IMUX.TDO.T[3] INT:MUX.IMUX.TDO.T[0] INT:MUX.IMUX.TDO.T[4] INT:MUX.IMUX.TDO.T[5] ~INT:PASS.SINGLE.V1.0.OUT.OSC.MUX1 INT:MUX.LONG.V2[0] INT:MUX.LONG.V2[2] ~INT:BUF.LONG.H2.0.SINGLE.V3 - INT:MUX.LONG.H2[0] INT:MUX.LONG.H0[1] INT:MUX.IMUX.BUFG.V[1] INT:MUX.IMUX.BUFG.V[3] INT:MUX.IMUX.BUFG.V[4] INT:MUX.IMUX.BUFG.V[5] INT:MUX.IMUX.BUFG.V[6] INT:MUX.IMUX.BUFG.V[0] ~MISC:TM_RIGHT ~INT:PASS.DOUBLE.V0.1.0.OUT.UPDATE.O ~INT:PASS.SINGLE.V2.0.OUT.UPDATE.O ~INT:PASS.SINGLE.V6.0.OUT.UPDATE.O INT:MUX.LONG.H1[3] INT:MUX.LONG.H1[1] - INT:MUX.LONG.H1[0] INT:MUX.LONG.H1[2] - - - - - -
xc4000h CNR.TR bittile 1
BitFrame
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
9 - ~INT:PASS.SINGLE.V3.0.LONG.H2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 ~INT:PASS.SINGLE.V2.0.LONG.H1 - - - ~INT:BUF.LONG.H1.0.SINGLE.V2 - ~INT:PASS.SINGLE.V1.0.LONG.H0 - ~INT:BUF.LONG.H0.0.SINGLE.V1 - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BSCAN:ENABLE 0.17.4
non-inverted [0]
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.1 0.26.4
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.E.2 0.28.5
INT:BIPASS.DOUBLE.V0.0.IO.DOUBLE.1.N.0 0.30.5
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.1 0.25.4
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.E.2 0.25.5
INT:BIPASS.DOUBLE.V0.1.IO.DOUBLE.0.N.0 0.26.5
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.1 0.29.6
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.E.2 0.27.6
INT:BIPASS.DOUBLE.V1.0.IO.DOUBLE.2.N.0 0.32.5
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.1 0.34.5
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.E.2 0.36.6
INT:BIPASS.DOUBLE.V1.1.IO.DOUBLE.3.N.0 0.36.5
INT:BIPASS.IO.DOUBLE.0.N.0.IO.DOUBLE.0.E.2 0.24.4
INT:BIPASS.IO.DOUBLE.1.N.0.IO.DOUBLE.1.E.2 0.27.4
INT:BIPASS.IO.DOUBLE.2.N.0.IO.DOUBLE.2.E.2 0.30.6
INT:BIPASS.IO.DOUBLE.3.N.0.IO.DOUBLE.3.E.2 0.35.5
INT:BIPASS.SINGLE.V0.IO.DOUBLE.0.E.1 0.24.6
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.E.2 0.24.5
INT:BIPASS.SINGLE.V1.IO.DOUBLE.0.N.0 0.27.5
INT:BIPASS.SINGLE.V2.IO.DOUBLE.1.E.1 0.29.5
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.E.2 0.25.6
INT:BIPASS.SINGLE.V3.IO.DOUBLE.1.N.0 0.31.5
INT:BIPASS.SINGLE.V4.IO.DOUBLE.2.E.1 0.26.6
INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.E.2 0.28.6
INT:BIPASS.SINGLE.V5.IO.DOUBLE.2.N.0 0.33.5
INT:BIPASS.SINGLE.V6.IO.DOUBLE.3.E.1 0.37.6
INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.E.2 0.35.6
INT:BIPASS.SINGLE.V7.IO.DOUBLE.3.N.0 0.37.5
INT:BUF.LONG.H0.0.SINGLE.V1 1.26.8
INT:BUF.LONG.H1.0.SINGLE.V2 1.30.8
INT:BUF.LONG.H2.0.SINGLE.V3 0.24.0
INT:PASS.DOUBLE.V0.0.0.OUT.BT.IOB1.I1.E 0.13.3
INT:PASS.DOUBLE.V0.1.0.OUT.UPDATE.O 0.13.0
INT:PASS.DOUBLE.V1.0.0.OUT.OSC.MUX1 0.29.3
INT:PASS.DOUBLE.V1.1.0.OUT.BT.IOB1.I2.E 0.38.0
INT:PASS.IO.DOUBLE.0.E.2.0.IO.DBUF.H1 0.23.5
INT:PASS.IO.DOUBLE.0.N.0.0.IO.DBUF.H0 0.31.6
INT:PASS.IO.DOUBLE.1.E.2.0.IO.DBUF.H1 0.21.5
INT:PASS.IO.DOUBLE.1.N.0.0.IO.DBUF.H0 0.32.6
INT:PASS.IO.DOUBLE.2.E.2.0.IO.DBUF.H1 0.22.5
INT:PASS.IO.DOUBLE.2.N.0.0.IO.DBUF.H0 0.33.6
INT:PASS.IO.DOUBLE.3.E.2.0.IO.DBUF.H1 0.23.6
INT:PASS.IO.DOUBLE.3.N.0.0.IO.DBUF.H0 0.34.6
INT:PASS.SINGLE.V0.0.DEC.H0 0.14.3
INT:PASS.SINGLE.V0.0.OUT.BT.IOB1.I2.E 0.26.2
INT:PASS.SINGLE.V1.0.LONG.H0 1.28.8
INT:PASS.SINGLE.V1.0.LONG.IO.H0 0.18.3
INT:PASS.SINGLE.V1.0.OUT.OSC.MUX1 0.27.0
INT:PASS.SINGLE.V2.0.LONG.H1 1.34.8
INT:PASS.SINGLE.V2.0.LONG.IO.H1 0.19.3
INT:PASS.SINGLE.V2.0.OUT.UPDATE.O 0.12.0
INT:PASS.SINGLE.V3.0.DEC.H1 0.36.0
INT:PASS.SINGLE.V3.0.LONG.H2 1.33.9
INT:PASS.SINGLE.V3.0.OUT.BT.IOB1.I1.E 0.30.3
INT:PASS.SINGLE.V4.0.DEC.H2 0.39.0
INT:PASS.SINGLE.V4.0.OUT.BT.IOB1.I2.E 0.40.0
INT:PASS.SINGLE.V5.0.LONG.IO.H2 0.28.3
INT:PASS.SINGLE.V5.0.OUT.OSC.MUX1 0.27.3
INT:PASS.SINGLE.V6.0.LONG.IO.H3 0.10.2
INT:PASS.SINGLE.V6.0.OUT.UPDATE.O 0.11.0
INT:PASS.SINGLE.V7.0.DEC.H3 0.34.3
INT:PASS.SINGLE.V7.0.OUT.BT.IOB1.I1.E 0.36.3
MISC:TAC 0.15.4
MISC:TM_RIGHT 0.14.0
PULLUP_DEC0_H:ENABLE 0.39.3
PULLUP_DEC0_V:ENABLE 0.8.2
PULLUP_DEC1_H:ENABLE 0.38.3
PULLUP_DEC1_V:ENABLE 0.11.2
PULLUP_DEC2_H:ENABLE 0.37.3
PULLUP_DEC2_V:ENABLE 0.9.2
PULLUP_DEC3_H:ENABLE 0.39.4
PULLUP_DEC3_V:ENABLE 0.12.2
TDO:ENABLE.O 0.8.4
TDO:ENABLE.T 0.7.4
inverted ~[0]
INT:MUX.IMUX.BUFG.H 0.20.5
0.OUT.IOB.CLKIN.E 0
NONE 1
INT:MUX.IMUX.BUFG.V 0.16.0 0.17.0 0.18.0 0.19.0 0.17.2 0.20.0 0.15.0
0.IO.DOUBLE.2.E.1 0 0 0 1 0 1 1
0.IO.DOUBLE.0.E.1 0 0 0 1 1 1 1
0.IO.DOUBLE.3.E.2 0 0 1 0 0 1 1
0.IO.DOUBLE.0.E.2 0 0 1 0 1 1 1
0.IO.DOUBLE.3.E.1 0 0 1 1 0 0 1
0.IO.DOUBLE.1.E.2 0 0 1 1 1 0 1
0.IO.DOUBLE.1.E.1 0 1 1 1 0 1 1
0.IO.DOUBLE.2.E.2 0 1 1 1 1 1 1
0.OUT.IOB.CLKIN.N 1 0 1 1 1 1 0
NONE 1 0 1 1 1 1 1
INT:MUX.IMUX.TDO.O 0.30.2 0.31.2 0.32.2 0.33.2 0.34.2 0.29.2
0.LONG.H0 0 0 1 1 1 0
0.SINGLE.V2 0 0 1 1 1 1
0.SINGLE.V3 0 1 0 1 1 1
0.LONG.H1 0 1 1 0 1 0
0.SINGLE.V4 0 1 1 0 1 1
0.LONG.H2 0 1 1 1 0 0
0.SINGLE.V5 0 1 1 1 0 1
1.DOUBLE.H1.1 1 1 1 1 1 0
1.DOUBLE.H0.0 1 1 1 1 1 1
INT:MUX.IMUX.TDO.T 0.28.0 0.29.0 0.31.0 0.32.0 0.33.0 0.30.0
1.SINGLE.H3 0 0 0 1 1 1
0.LONG.V4 0 0 1 0 1 1
1.SINGLE.H2 0 0 1 1 0 1
0.DOUBLE.V0.0 0 1 1 1 1 1
0.DOUBLE.V1.1 1 0 0 1 1 1
0.LONG.V3 1 0 1 0 1 1
0.LONG.V5 1 0 1 1 0 1
1.SINGLE.H4 1 0 1 1 1 0
1.SINGLE.H5 1 1 1 1 1 1
INT:MUX.IO.DBUF.H0 0.7.3 0.11.3 0.8.3 0.9.3
0.IO.DOUBLE.0.E.2 0 0 1 1
0.IO.DOUBLE.2.E.2 0 1 0 1
0.IO.DOUBLE.3.E.2 0 1 1 0
0.IO.DOUBLE.1.E.2 1 1 1 1
INT:MUX.IO.DBUF.H1 0.38.5 0.39.5 0.38.6 0.39.6
0.IO.DOUBLE.1.N.0 0 0 1 1
0.IO.DOUBLE.2.N.0 0 1 0 1
0.IO.DOUBLE.3.N.0 0 1 1 0
0.IO.DOUBLE.0.N.0 1 1 1 1
INT:MUX.LONG.H0 0.18.2 0.19.2 0.21.0 0.20.2
0.LONG.IO.V0 0 0 0 1
0.DEC.V3 0 0 1 0
0.OUT.LR.IOB1.I2 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.H1 0.10.0 0.6.0 0.9.0 0.7.0
0.LONG.IO.V1 0 0 0 1
0.DEC.V2 0 0 1 0
0.OUT.LR.IOB1.I2 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.H2 0.21.2 0.22.0
0.LONG.IO.V2 0 0
0.DEC.V1 0 1
NONE 1 1
INT:MUX.LONG.IO.H0 0.29.4 0.28.4 0.23.4 0.22.4
0.LONG.V0 0 0 1 1
0.SINGLE.V1 0 1 1 1
0.LONG.IO.V2 1 1 0 0
0.LONG.IO.V0 1 1 0 1
NONE 1 1 1 1
INT:MUX.LONG.IO.H1 0.33.4 0.30.4 0.32.4 0.31.4 0.14.4 0.13.4
0.LONG.V1 0 0 0 1 1 1
0.LONG.V3 0 0 1 0 1 1
0.SINGLE.V2 0 1 1 1 1 1
0.LONG.IO.V3 1 1 1 1 0 0
0.LONG.IO.V1 1 1 1 1 0 1
NONE 1 1 1 1 1 1
INT:MUX.LONG.IO.H2 0.36.4 0.34.4 0.38.4 0.37.4 0.19.4 0.20.4
0.LONG.V2 0 0 0 1 1 1
0.LONG.V4 0 0 1 0 1 1
0.SINGLE.V5 0 1 1 1 1 1
0.LONG.IO.V0 1 1 1 1 0 0
0.LONG.IO.V2 1 1 1 1 0 1
NONE 1 1 1 1 1 1
INT:MUX.LONG.IO.H3 0.35.4 0.26.3 0.10.4 0.11.4
0.LONG.V5 0 0 1 1
0.SINGLE.V6 0 1 1 1
0.LONG.IO.V1 1 1 0 0
0.LONG.IO.V3 1 1 0 1
NONE 1 1 1 1
INT:MUX.LONG.IO.V0 0.21.3 0.15.3 0.15.2 0.16.3
0.LONG.H0 0 0 0 1
0.LONG.IO.H2 0 0 1 0
0.LONG.IO.H0 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.V1 0.10.3 0.5.2 0.7.2 0.6.2
0.LONG.H1 0 0 0 1
0.LONG.IO.H3 0 0 1 0
0.LONG.IO.H1 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.V2 0.23.3 0.13.2 0.16.2 0.14.2
0.LONG.H2 0 0 0 1
0.LONG.IO.H0 0 0 1 0
0.LONG.IO.H2 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.IO.V3 0.17.3 0.12.3
0.LONG.IO.H1 0 0
0.LONG.IO.H3 0 1
NONE 1 1
INT:MUX.LONG.V0 0.20.3 0.22.3 0.24.3 0.25.3
0.LONG.IO.H0 0 0 0 1
0.DEC.H3 0 0 1 0
0.OUT.BT.IOB1.I2.E 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V1 0.38.2 0.37.0 0.37.2 0.39.2
0.LONG.IO.H1 0 0 0 1
0.DEC.H2 0 0 1 0
0.OUT.BT.IOB1.I2.E 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V2 0.28.2 0.25.0 0.27.2 0.26.0
0.LONG.IO.H2 0 0 0 1
0.DEC.H1 0 0 1 0
0.OUT.BT.IOB1.I2.E 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V3 0.35.2 0.34.0 0.35.0 0.36.2
0.LONG.IO.H1 0 0 0 1
0.DEC.H2 0 0 1 0
0.OUT.OSC.MUX1 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V4 0.25.2 0.22.2 0.23.2 0.24.2
0.LONG.IO.H2 0 0 0 1
0.DEC.H1 0 0 1 0
0.OUT.OSC.MUX1 0 1 1 1
NONE 1 1 1 1
INT:MUX.LONG.V5 0.35.3 0.31.3 0.33.3 0.32.3
0.LONG.IO.H3 0 0 0 1
0.DEC.H0 0 0 1 0
0.OUT.OSC.MUX1 0 1 1 1
NONE 1 1 1 1
READCLK:READ_CLK 0.12.4
RDBK 0
CCLK 1
TDO:PULL 0.18.4 0.16.4
PULLUP 0 1
PULLDOWN 1 0
PULLNONE 1 1