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Splitters

Tile LLH.CLB

Cells: 2

Bel LLH

Switchbox LLH

xc4000h LLH.CLB switchbox LLH
DestinationSourceKind
TCELL0_LONG.H0TCELL1_LONG.H0bidirectional pass transistor
TCELL0_LONG.H1TCELL1_LONG.H1bidirectional pass transistor
TCELL0_LONG.H2TCELL1_LONG.H2bidirectional pass transistor
TCELL0_LONG.H3TCELL1_LONG.H3bidirectional pass transistor
TCELL0_LONG.H4TCELL1_LONG.H4bidirectional pass transistor
TCELL0_LONG.H5TCELL1_LONG.H5bidirectional pass transistor
TCELL1_LONG.H0TCELL0_LONG.H0bidirectional pass transistor
TCELL1_LONG.H1TCELL0_LONG.H1bidirectional pass transistor
TCELL1_LONG.H2TCELL0_LONG.H2bidirectional pass transistor
TCELL1_LONG.H3TCELL0_LONG.H3bidirectional pass transistor
TCELL1_LONG.H4TCELL0_LONG.H4bidirectional pass transistor
TCELL1_LONG.H5TCELL0_LONG.H5bidirectional pass transistor

Bitstream

xc4000h LLH.CLB bittile 0
BitFrame
0
5 ~LLH:BIPASS.0.LONG.H4.1.LONG.H4
4 ~LLH:BIPASS.0.LONG.H3.1.LONG.H3
3 ~LLH:BIPASS.0.LONG.H5.1.LONG.H5
2 -
1 -
0 -
xc4000h LLH.CLB bittile 1
BitFrame
0
8 ~LLH:BIPASS.0.LONG.H0.1.LONG.H0
7 ~LLH:BIPASS.0.LONG.H1.1.LONG.H1
6 ~LLH:BIPASS.0.LONG.H2.1.LONG.H2
5 -
4 -
3 -
2 -
1 -
0 -
LLH:BIPASS.0.LONG.H0.1.LONG.H0 1.0.8
LLH:BIPASS.0.LONG.H1.1.LONG.H1 1.0.7
LLH:BIPASS.0.LONG.H2.1.LONG.H2 1.0.6
LLH:BIPASS.0.LONG.H3.1.LONG.H3 0.0.4
LLH:BIPASS.0.LONG.H4.1.LONG.H4 0.0.5
LLH:BIPASS.0.LONG.H5.1.LONG.H5 0.0.3
inverted ~[0]

Tile LLH.CLB.B

Cells: 2

Bel LLH

Switchbox LLH

xc4000h LLH.CLB.B switchbox LLH
DestinationSourceKind
TCELL0_LONG.H0TCELL1_LONG.H0bidirectional pass transistor
TCELL0_LONG.H1TCELL1_LONG.H1bidirectional pass transistor
TCELL0_LONG.H2TCELL1_LONG.H2bidirectional pass transistor
TCELL0_LONG.H3TCELL1_LONG.H3bidirectional pass transistor
TCELL0_LONG.H4TCELL1_LONG.H4bidirectional pass transistor
TCELL0_LONG.H5TCELL1_LONG.H5bidirectional pass transistor
TCELL1_LONG.H0TCELL0_LONG.H0bidirectional pass transistor
TCELL1_LONG.H1TCELL0_LONG.H1bidirectional pass transistor
TCELL1_LONG.H2TCELL0_LONG.H2bidirectional pass transistor
TCELL1_LONG.H3TCELL0_LONG.H3bidirectional pass transistor
TCELL1_LONG.H4TCELL0_LONG.H4bidirectional pass transistor
TCELL1_LONG.H5TCELL0_LONG.H5bidirectional pass transistor

Bitstream

xc4000h LLH.CLB.B bittile 0
BitFrame
0
5 ~LLH:BIPASS.0.LONG.H4.1.LONG.H4
4 ~LLH:BIPASS.0.LONG.H3.1.LONG.H3
3 ~LLH:BIPASS.0.LONG.H5.1.LONG.H5
2 -
1 -
0 ~LLH:BIPASS.0.LONG.H2.1.LONG.H2
xc4000h LLH.CLB.B bittile 1
BitFrame
0
12 ~LLH:BIPASS.0.LONG.H1.1.LONG.H1
11 ~LLH:BIPASS.0.LONG.H0.1.LONG.H0
10 -
9 -
8 -
7 -
6 -
5 -
4 -
3 -
2 -
1 -
0 -
LLH:BIPASS.0.LONG.H0.1.LONG.H0 1.0.11
LLH:BIPASS.0.LONG.H1.1.LONG.H1 1.0.12
LLH:BIPASS.0.LONG.H2.1.LONG.H2 0.0.0
LLH:BIPASS.0.LONG.H3.1.LONG.H3 0.0.4
LLH:BIPASS.0.LONG.H4.1.LONG.H4 0.0.5
LLH:BIPASS.0.LONG.H5.1.LONG.H5 0.0.3
inverted ~[0]

Tile LLH.IO.B

Cells: 2

Bel LLH

Switchbox LLH

xc4000h LLH.IO.B switchbox LLH
DestinationSourceKind
TCELL0_LONG.H3TCELL1_LONG.H3bidirectional pass transistor
TCELL0_LONG.H4TCELL1_LONG.H4bidirectional pass transistor
TCELL0_LONG.H5TCELL1_LONG.H5bidirectional pass transistor
TCELL0_LONG.IO.H0TCELL1_LONG.IO.H0bidirectional pass transistor
TCELL0_LONG.IO.H1TCELL1_LONG.IO.H1bidirectional pass transistor
TCELL0_LONG.IO.H2TCELL1_LONG.IO.H2bidirectional pass transistor
TCELL0_LONG.IO.H3TCELL1_LONG.IO.H3bidirectional pass transistor
TCELL0_DEC.H0TCELL1_DEC.H0bidirectional pass transistor
TCELL0_DEC.H1TCELL1_DEC.H1bidirectional pass transistor
TCELL0_DEC.H2TCELL1_DEC.H2bidirectional pass transistor
TCELL0_DEC.H3TCELL1_DEC.H3bidirectional pass transistor
TCELL1_LONG.H3TCELL0_LONG.H3bidirectional pass transistor
TCELL1_LONG.H4TCELL0_LONG.H4bidirectional pass transistor
TCELL1_LONG.H5TCELL0_LONG.H5bidirectional pass transistor
TCELL1_LONG.IO.H0TCELL0_LONG.IO.H0bidirectional pass transistor
TCELL1_LONG.IO.H1TCELL0_LONG.IO.H1bidirectional pass transistor
TCELL1_LONG.IO.H2TCELL0_LONG.IO.H2bidirectional pass transistor
TCELL1_LONG.IO.H3TCELL0_LONG.IO.H3bidirectional pass transistor
TCELL1_DEC.H0TCELL0_DEC.H0bidirectional pass transistor
TCELL1_DEC.H1TCELL0_DEC.H1bidirectional pass transistor
TCELL1_DEC.H2TCELL0_DEC.H2bidirectional pass transistor
TCELL1_DEC.H3TCELL0_DEC.H3bidirectional pass transistor

Bitstream

xc4000h LLH.IO.B bittile 0
BitFrame
0
10 ~LLH:BIPASS.0.LONG.H3.1.LONG.H3
9 ~LLH:BIPASS.0.LONG.H4.1.LONG.H4
8 ~LLH:BIPASS.0.LONG.H5.1.LONG.H5
7 ~LLH:BIPASS.0.DEC.H3.1.DEC.H3
6 ~LLH:BIPASS.0.DEC.H1.1.DEC.H1
5 ~LLH:BIPASS.0.DEC.H2.1.DEC.H2
4 ~LLH:BIPASS.0.DEC.H0.1.DEC.H0
3 ~LLH:BIPASS.0.LONG.IO.H3.1.LONG.IO.H3
2 ~LLH:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0
1 ~LLH:BIPASS.0.LONG.IO.H2.1.LONG.IO.H2
0 ~LLH:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1
LLH:BIPASS.0.DEC.H0.1.DEC.H0 0.0.4
LLH:BIPASS.0.DEC.H1.1.DEC.H1 0.0.6
LLH:BIPASS.0.DEC.H2.1.DEC.H2 0.0.5
LLH:BIPASS.0.DEC.H3.1.DEC.H3 0.0.7
LLH:BIPASS.0.LONG.H3.1.LONG.H3 0.0.10
LLH:BIPASS.0.LONG.H4.1.LONG.H4 0.0.9
LLH:BIPASS.0.LONG.H5.1.LONG.H5 0.0.8
LLH:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0 0.0.2
LLH:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1 0.0.0
LLH:BIPASS.0.LONG.IO.H2.1.LONG.IO.H2 0.0.1
LLH:BIPASS.0.LONG.IO.H3.1.LONG.IO.H3 0.0.3
inverted ~[0]

Tile LLH.IO.T

Cells: 2

Bel LLH

Switchbox LLH

xc4000h LLH.IO.T switchbox LLH
DestinationSourceKind
TCELL0_LONG.H0TCELL1_LONG.H0bidirectional pass transistor
TCELL0_LONG.H1TCELL1_LONG.H1bidirectional pass transistor
TCELL0_LONG.H2TCELL1_LONG.H2bidirectional pass transistor
TCELL0_LONG.IO.H0TCELL1_LONG.IO.H0bidirectional pass transistor
TCELL0_LONG.IO.H1TCELL1_LONG.IO.H1bidirectional pass transistor
TCELL0_LONG.IO.H2TCELL1_LONG.IO.H2bidirectional pass transistor
TCELL0_LONG.IO.H3TCELL1_LONG.IO.H3bidirectional pass transistor
TCELL0_DEC.H0TCELL1_DEC.H0bidirectional pass transistor
TCELL0_DEC.H1TCELL1_DEC.H1bidirectional pass transistor
TCELL0_DEC.H2TCELL1_DEC.H2bidirectional pass transistor
TCELL0_DEC.H3TCELL1_DEC.H3bidirectional pass transistor
TCELL1_LONG.H0TCELL0_LONG.H0bidirectional pass transistor
TCELL1_LONG.H1TCELL0_LONG.H1bidirectional pass transistor
TCELL1_LONG.H2TCELL0_LONG.H2bidirectional pass transistor
TCELL1_LONG.IO.H0TCELL0_LONG.IO.H0bidirectional pass transistor
TCELL1_LONG.IO.H1TCELL0_LONG.IO.H1bidirectional pass transistor
TCELL1_LONG.IO.H2TCELL0_LONG.IO.H2bidirectional pass transistor
TCELL1_LONG.IO.H3TCELL0_LONG.IO.H3bidirectional pass transistor
TCELL1_DEC.H0TCELL0_DEC.H0bidirectional pass transistor
TCELL1_DEC.H1TCELL0_DEC.H1bidirectional pass transistor
TCELL1_DEC.H2TCELL0_DEC.H2bidirectional pass transistor
TCELL1_DEC.H3TCELL0_DEC.H3bidirectional pass transistor

Bitstream

xc4000h LLH.IO.T bittile 0
BitFrame
0
6 ~LLH:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1
5 ~LLH:BIPASS.0.LONG.IO.H2.1.LONG.IO.H2
4 ~LLH:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0
3 ~LLH:BIPASS.0.LONG.IO.H3.1.LONG.IO.H3
2 ~LLH:BIPASS.0.DEC.H3.1.DEC.H3
1 ~LLH:BIPASS.0.DEC.H1.1.DEC.H1
0 ~LLH:BIPASS.0.DEC.H2.1.DEC.H2
xc4000h LLH.IO.T bittile 1
BitFrame
0
9 ~LLH:BIPASS.0.DEC.H0.1.DEC.H0
8 ~LLH:BIPASS.0.LONG.H0.1.LONG.H0
7 ~LLH:BIPASS.0.LONG.H1.1.LONG.H1
6 ~LLH:BIPASS.0.LONG.H2.1.LONG.H2
5 -
4 -
3 -
2 -
1 -
0 -
LLH:BIPASS.0.DEC.H0.1.DEC.H0 1.0.9
LLH:BIPASS.0.DEC.H1.1.DEC.H1 0.0.1
LLH:BIPASS.0.DEC.H2.1.DEC.H2 0.0.0
LLH:BIPASS.0.DEC.H3.1.DEC.H3 0.0.2
LLH:BIPASS.0.LONG.H0.1.LONG.H0 1.0.8
LLH:BIPASS.0.LONG.H1.1.LONG.H1 1.0.7
LLH:BIPASS.0.LONG.H2.1.LONG.H2 1.0.6
LLH:BIPASS.0.LONG.IO.H0.1.LONG.IO.H0 0.0.4
LLH:BIPASS.0.LONG.IO.H1.1.LONG.IO.H1 0.0.6
LLH:BIPASS.0.LONG.IO.H2.1.LONG.IO.H2 0.0.5
LLH:BIPASS.0.LONG.IO.H3.1.LONG.IO.H3 0.0.3
inverted ~[0]

Tile LLV.CLB

Cells: 2

Bel LLV

Switchbox LLV

xc4000h LLV.CLB switchbox LLV
DestinationSourceKind
TCELL0_LONG.V0TCELL1_LONG.V0bidirectional pass transistor
TCELL0_LONG.V1TCELL1_LONG.V1bidirectional pass transistor
TCELL0_LONG.V2TCELL1_LONG.V2bidirectional pass transistor
TCELL0_LONG.V3TCELL1_LONG.V3bidirectional pass transistor
TCELL0_LONG.V4TCELL1_LONG.V4bidirectional pass transistor
TCELL0_LONG.V5TCELL1_LONG.V5bidirectional pass transistor
TCELL1_LONG.V0TCELL0_LONG.V0bidirectional pass transistor
TCELL1_LONG.V1TCELL0_LONG.V1bidirectional pass transistor
TCELL1_LONG.V2TCELL0_LONG.V2bidirectional pass transistor
TCELL1_LONG.V3TCELL0_LONG.V3bidirectional pass transistor
TCELL1_LONG.V4TCELL0_LONG.V4bidirectional pass transistor
TCELL1_LONG.V5TCELL0_LONG.V5bidirectional pass transistor

Bel CLKH

xc4000h LLV.CLB bel CLKH
PinDirectionWires
O0outputTCELL0:GCLK0
O1outputTCELL0:GCLK1
O2outputTCELL0:GCLK2
O3outputTCELL0:GCLK3

Bel wires

xc4000h LLV.CLB bel wires
WirePins
TCELL0:GCLK0CLKH.O0
TCELL0:GCLK1CLKH.O1
TCELL0:GCLK2CLKH.O2
TCELL0:GCLK3CLKH.O3

Bitstream

xc4000h LLV.CLB bittile 0
BitFrame
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 ~LLV:BIPASS.0.LONG.V5.1.LONG.V5 ~LLV:BIPASS.0.LONG.V1.1.LONG.V1 ~LLV:BIPASS.0.LONG.V2.1.LONG.V2 CLKH:MUX.O2[4] CLKH:MUX.O2[2] CLKH:MUX.O2[0] CLKH:MUX.O2[1] CLKH:MUX.O2[3] ~LLV:BIPASS.0.LONG.V3.1.LONG.V3 ~LLV:BIPASS.0.LONG.V0.1.LONG.V0 ~LLV:BIPASS.0.LONG.V4.1.LONG.V4 CLKH:MUX.O0[4] CLKH:MUX.O0[2] CLKH:MUX.O0[0] CLKH:MUX.O0[1] CLKH:MUX.O0[3] CLKH:MUX.O3[3] CLKH:MUX.O3[1] - CLKH:MUX.O3[0] CLKH:MUX.O3[2] CLKH:MUX.O3[4] CLKH:MUX.O1[4] CLKH:MUX.O1[2] CLKH:MUX.O1[0] CLKH:MUX.O1[1] CLKH:MUX.O1[3] - - - -
CLKH:MUX.O0 0.19.0 0.15.0 0.18.0 0.16.0 0.17.0
I.UL.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
GND 1 1 1 1 1
CLKH:MUX.O1 0.8.0 0.4.0 0.7.0 0.5.0 0.6.0
I.LL.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
GND 1 1 1 1 1
CLKH:MUX.O2 0.27.0 0.23.0 0.26.0 0.24.0 0.25.0
I.LR.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
GND 1 1 1 1 1
CLKH:MUX.O3 0.9.0 0.14.0 0.10.0 0.13.0 0.11.0
I.UR.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
GND 1 1 1 1 1
LLV:BIPASS.0.LONG.V0.1.LONG.V0 0.21.0
LLV:BIPASS.0.LONG.V1.1.LONG.V1 0.29.0
LLV:BIPASS.0.LONG.V2.1.LONG.V2 0.28.0
LLV:BIPASS.0.LONG.V3.1.LONG.V3 0.22.0
LLV:BIPASS.0.LONG.V4.1.LONG.V4 0.20.0
LLV:BIPASS.0.LONG.V5.1.LONG.V5 0.30.0
inverted ~[0]

Tile LLV.IO.L

Cells: 2

Bel LLV

Switchbox LLV

xc4000h LLV.IO.L switchbox LLV
DestinationSourceKind
TCELL0_LONG.IO.V0TCELL1_LONG.IO.V0bidirectional pass transistor
TCELL0_LONG.IO.V1TCELL1_LONG.IO.V1bidirectional pass transistor
TCELL0_LONG.IO.V2TCELL1_LONG.IO.V2bidirectional pass transistor
TCELL0_LONG.IO.V3TCELL1_LONG.IO.V3bidirectional pass transistor
TCELL0_DEC.V0TCELL1_DEC.V0bidirectional pass transistor
TCELL0_DEC.V1TCELL1_DEC.V1bidirectional pass transistor
TCELL0_DEC.V2TCELL1_DEC.V2bidirectional pass transistor
TCELL0_DEC.V3TCELL1_DEC.V3bidirectional pass transistor
TCELL1_LONG.IO.V0TCELL0_LONG.IO.V0bidirectional pass transistor
TCELL1_LONG.IO.V1TCELL0_LONG.IO.V1bidirectional pass transistor
TCELL1_LONG.IO.V2TCELL0_LONG.IO.V2bidirectional pass transistor
TCELL1_LONG.IO.V3TCELL0_LONG.IO.V3bidirectional pass transistor
TCELL1_DEC.V0TCELL0_DEC.V0bidirectional pass transistor
TCELL1_DEC.V1TCELL0_DEC.V1bidirectional pass transistor
TCELL1_DEC.V2TCELL0_DEC.V2bidirectional pass transistor
TCELL1_DEC.V3TCELL0_DEC.V3bidirectional pass transistor

Bel CLKH

xc4000h LLV.IO.L bel CLKH
PinDirectionWires
O0outputTCELL0:GCLK0
O1outputTCELL0:GCLK1
O2outputTCELL0:GCLK2
O3outputTCELL0:GCLK3

Bel wires

xc4000h LLV.IO.L bel wires
WirePins
TCELL0:GCLK0CLKH.O0
TCELL0:GCLK1CLKH.O1
TCELL0:GCLK2CLKH.O2
TCELL0:GCLK3CLKH.O3

Bitstream

xc4000h LLV.IO.L bittile 0
BitFrame
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 CLKH:MUX.O3[4] CLKH:MUX.O3[2] CLKH:MUX.O3[0] CLKH:MUX.O3[1] CLKH:MUX.O3[3] ~LLV:BIPASS.0.DEC.V3.1.DEC.V3 CLKH:MUX.O1[4] CLKH:MUX.O1[2] CLKH:MUX.O1[0] CLKH:MUX.O1[1] CLKH:MUX.O1[3] ~LLV:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1 ~LLV:BIPASS.0.DEC.V2.1.DEC.V2 ~LLV:BIPASS.0.DEC.V1.1.DEC.V1 CLKH:MUX.O0[4] CLKH:MUX.O0[2] CLKH:MUX.O0[0] CLKH:MUX.O0[1] ~LLV:BIPASS.0.DEC.V0.1.DEC.V0 CLKH:MUX.O0[3] - ~LLV:BIPASS.0.LONG.IO.V2.1.LONG.IO.V2 ~LLV:BIPASS.0.LONG.IO.V3.1.LONG.IO.V3 ~LLV:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0 - CLKH:MUX.O2[4]
xc4000h LLV.IO.L bittile 1
BitFrame
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 CLKH:MUX.O2[2] CLKH:MUX.O2[0] CLKH:MUX.O2[1] CLKH:MUX.O2[3] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
CLKH:MUX.O0 0.11.0 0.6.0 0.10.0 0.8.0 0.9.0
I.UL.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
GND 1 1 1 1 1
CLKH:MUX.O1 0.19.0 0.15.0 0.18.0 0.16.0 0.17.0
I.LL.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
GND 1 1 1 1 1
CLKH:MUX.O2 0.0.0 1.31.0 1.34.0 1.32.0 1.33.0
I.LR.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
GND 1 1 1 1 1
CLKH:MUX.O3 0.25.0 0.21.0 0.24.0 0.22.0 0.23.0
I.UR.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
GND 1 1 1 1 1
LLV:BIPASS.0.DEC.V0.1.DEC.V0 0.7.0
LLV:BIPASS.0.DEC.V1.1.DEC.V1 0.12.0
LLV:BIPASS.0.DEC.V2.1.DEC.V2 0.13.0
LLV:BIPASS.0.DEC.V3.1.DEC.V3 0.20.0
LLV:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0 0.2.0
LLV:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1 0.14.0
LLV:BIPASS.0.LONG.IO.V2.1.LONG.IO.V2 0.4.0
LLV:BIPASS.0.LONG.IO.V3.1.LONG.IO.V3 0.3.0
inverted ~[0]

Tile LLV.IO.R

Cells: 2

Bel LLV

Switchbox LLV

xc4000h LLV.IO.R switchbox LLV
DestinationSourceKind
TCELL0_LONG.V0TCELL1_LONG.V0bidirectional pass transistor
TCELL0_LONG.V1TCELL1_LONG.V1bidirectional pass transistor
TCELL0_LONG.V2TCELL1_LONG.V2bidirectional pass transistor
TCELL0_LONG.V3TCELL1_LONG.V3bidirectional pass transistor
TCELL0_LONG.V4TCELL1_LONG.V4bidirectional pass transistor
TCELL0_LONG.V5TCELL1_LONG.V5bidirectional pass transistor
TCELL0_LONG.IO.V0TCELL1_LONG.IO.V0bidirectional pass transistor
TCELL0_LONG.IO.V1TCELL1_LONG.IO.V1bidirectional pass transistor
TCELL0_LONG.IO.V2TCELL1_LONG.IO.V2bidirectional pass transistor
TCELL0_LONG.IO.V3TCELL1_LONG.IO.V3bidirectional pass transistor
TCELL0_DEC.V0TCELL1_DEC.V0bidirectional pass transistor
TCELL0_DEC.V1TCELL1_DEC.V1bidirectional pass transistor
TCELL0_DEC.V2TCELL1_DEC.V2bidirectional pass transistor
TCELL0_DEC.V3TCELL1_DEC.V3bidirectional pass transistor
TCELL1_LONG.V0TCELL0_LONG.V0bidirectional pass transistor
TCELL1_LONG.V1TCELL0_LONG.V1bidirectional pass transistor
TCELL1_LONG.V2TCELL0_LONG.V2bidirectional pass transistor
TCELL1_LONG.V3TCELL0_LONG.V3bidirectional pass transistor
TCELL1_LONG.V4TCELL0_LONG.V4bidirectional pass transistor
TCELL1_LONG.V5TCELL0_LONG.V5bidirectional pass transistor
TCELL1_LONG.IO.V0TCELL0_LONG.IO.V0bidirectional pass transistor
TCELL1_LONG.IO.V1TCELL0_LONG.IO.V1bidirectional pass transistor
TCELL1_LONG.IO.V2TCELL0_LONG.IO.V2bidirectional pass transistor
TCELL1_LONG.IO.V3TCELL0_LONG.IO.V3bidirectional pass transistor
TCELL1_DEC.V0TCELL0_DEC.V0bidirectional pass transistor
TCELL1_DEC.V1TCELL0_DEC.V1bidirectional pass transistor
TCELL1_DEC.V2TCELL0_DEC.V2bidirectional pass transistor
TCELL1_DEC.V3TCELL0_DEC.V3bidirectional pass transistor

Bel CLKH

xc4000h LLV.IO.R bel CLKH
PinDirectionWires
O0outputTCELL0:GCLK0
O1outputTCELL0:GCLK1
O2outputTCELL0:GCLK2
O3outputTCELL0:GCLK3

Bel wires

xc4000h LLV.IO.R bel wires
WirePins
TCELL0:GCLK0CLKH.O0
TCELL0:GCLK1CLKH.O1
TCELL0:GCLK2CLKH.O2
TCELL0:GCLK3CLKH.O3

Bitstream

xc4000h LLV.IO.R bittile 0
BitFrame
35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 ~LLV:BIPASS.0.LONG.V5.1.LONG.V5 ~LLV:BIPASS.0.LONG.V1.1.LONG.V1 ~LLV:BIPASS.0.LONG.V2.1.LONG.V2 CLKH:MUX.O2[4] CLKH:MUX.O2[2] CLKH:MUX.O2[0] CLKH:MUX.O2[1] CLKH:MUX.O2[3] ~LLV:BIPASS.0.LONG.V3.1.LONG.V3 ~LLV:BIPASS.0.LONG.V0.1.LONG.V0 ~MISC:TLC ~LLV:BIPASS.0.LONG.V4.1.LONG.V4 ~LLV:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0 ~LLV:BIPASS.0.LONG.IO.V3.1.LONG.IO.V3 ~LLV:BIPASS.0.LONG.IO.V2.1.LONG.IO.V2 - CLKH:MUX.O0[3] ~LLV:BIPASS.0.DEC.V3.1.DEC.V3 CLKH:MUX.O0[1] CLKH:MUX.O0[0] CLKH:MUX.O0[2] CLKH:MUX.O0[4] ~LLV:BIPASS.0.DEC.V2.1.DEC.V2 ~LLV:BIPASS.0.DEC.V1.1.DEC.V1 ~LLV:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1 CLKH:MUX.O1[3] CLKH:MUX.O1[1] CLKH:MUX.O1[0] CLKH:MUX.O1[2] CLKH:MUX.O1[4] ~LLV:BIPASS.0.DEC.V0.1.DEC.V0 CLKH:MUX.O3[3] CLKH:MUX.O3[1] CLKH:MUX.O3[0] CLKH:MUX.O3[2] CLKH:MUX.O3[4]
CLKH:MUX.O0 0.14.0 0.19.0 0.15.0 0.17.0 0.16.0
I.UL.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
GND 1 1 1 1 1
CLKH:MUX.O1 0.6.0 0.10.0 0.7.0 0.9.0 0.8.0
I.LL.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
GND 1 1 1 1 1
CLKH:MUX.O2 0.32.0 0.28.0 0.31.0 0.29.0 0.30.0
I.LR.V 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
GND 1 1 1 1 1
CLKH:MUX.O3 0.0.0 0.4.0 0.1.0 0.3.0 0.2.0
I.UR.H 0 1 1 1 1
I.LL.V 1 0 1 1 1
I.UL.H 1 1 0 1 1
I.LR.H 1 1 1 0 1
I.UR.V 1 1 1 1 0
GND 1 1 1 1 1
LLV:BIPASS.0.DEC.V0.1.DEC.V0 0.5.0
LLV:BIPASS.0.DEC.V1.1.DEC.V1 0.12.0
LLV:BIPASS.0.DEC.V2.1.DEC.V2 0.13.0
LLV:BIPASS.0.DEC.V3.1.DEC.V3 0.18.0
LLV:BIPASS.0.LONG.IO.V0.1.LONG.IO.V0 0.23.0
LLV:BIPASS.0.LONG.IO.V1.1.LONG.IO.V1 0.11.0
LLV:BIPASS.0.LONG.IO.V2.1.LONG.IO.V2 0.21.0
LLV:BIPASS.0.LONG.IO.V3.1.LONG.IO.V3 0.22.0
LLV:BIPASS.0.LONG.V0.1.LONG.V0 0.26.0
LLV:BIPASS.0.LONG.V1.1.LONG.V1 0.34.0
LLV:BIPASS.0.LONG.V2.1.LONG.V2 0.33.0
LLV:BIPASS.0.LONG.V3.1.LONG.V3 0.27.0
LLV:BIPASS.0.LONG.V4.1.LONG.V4 0.24.0
LLV:BIPASS.0.LONG.V5.1.LONG.V5 0.35.0
MISC:TLC 0.25.0
inverted ~[0]