Corners

Tile CNR_SW

Cells: 2

Switchbox INT

xc4000xv CNR_SW switchbox INT permanent buffers
Destination	Source
CELL.BUFGE_H	CELL.OUT_BUFGE_H
CELL.BUFGE_V[0]	CELL.OUT_BUFGE_V

xc4000xv CNR_SW switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_H[0]	CELL.DEC_V[3]	!MAIN[9][8]
CELL.SINGLE_H[0]	CELL.OUT_IO_WE_I2_S1	!MAIN[2][8]
CELL.SINGLE_H[1]	CELL.LONG_IO_V[0]	!MAIN[4][8]
CELL.SINGLE_H[1]	CELL.OUT_RDBK_DATA	!MAIN[5][8]
CELL.SINGLE_H[2]	CELL.LONG_IO_V[1]	!MAIN[19][12]
CELL.SINGLE_H[2]	CELL.OUT_MD0_I	!MAIN[5][11]
CELL.SINGLE_H[3]	CELL.DEC_V[2]	!MAIN[17][13]
CELL.SINGLE_H[3]	CELL.OUT_IO_WE_I1_S1	!MAIN[11][12]
CELL.SINGLE_H[4]	CELL.DEC_V[1]	!MAIN[15][9]
CELL.SINGLE_H[4]	CELL.OUT_IO_WE_I2_S1	!MAIN[1][8]
CELL.SINGLE_H[5]	CELL.LONG_IO_V[2]	!MAIN[7][8]
CELL.SINGLE_H[5]	CELL.OUT_RDBK_DATA	!MAIN[6][8]
CELL.SINGLE_H[6]	CELL.LONG_IO_V[3]	!MAIN[4][12]
CELL.SINGLE_H[6]	CELL.OUT_MD0_I	!MAIN[2][12]
CELL.SINGLE_H[7]	CELL.DEC_V[0]	!MAIN[9][13]
CELL.SINGLE_H[7]	CELL.OUT_IO_WE_I1_S1	!MAIN[1][12]
CELL.DOUBLE_H0[0]	CELL.OUT_IO_WE_I1_S1	!MAIN[3][11]
CELL.DOUBLE_H0[1]	CELL.OUT_RDBK_DATA	!MAIN[3][10]
CELL.DOUBLE_H1[0]	CELL.OUT_MD0_I	!MAIN[5][12]
CELL.DOUBLE_H1[1]	CELL.OUT_IO_WE_I2_S1	!MAIN[3][8]
CELL.DOUBLE_IO_S0[0]	CELL.DBUF_IO_V[1]	!MAIN[11][9]
CELL.DOUBLE_IO_S0[1]	CELL.DBUF_IO_V[1]	!MAIN[11][10]
CELL.DOUBLE_IO_S0[2]	CELL.DBUF_IO_V[1]	!MAIN[14][9]
CELL.DOUBLE_IO_S0[3]	CELL.DBUF_IO_V[1]	!MAIN[4][10]
CELL.DOUBLE_IO_W2[0]	CELL.DBUF_IO_V[0]	!MAIN[7][10]
CELL.DOUBLE_IO_W2[1]	CELL.DBUF_IO_V[0]	!MAIN[10][12]
CELL.DOUBLE_IO_W2[2]	CELL.DBUF_IO_V[0]	!MAIN[9][10]
CELL.DOUBLE_IO_W2[3]	CELL.DBUF_IO_V[0]	!MAIN[9][11]
CELL.QUAD_H0[1]	CELL.OUT_IO_WE_I1_S1	!MAIN[11][14]
CELL.QUAD_H0[2]	CELL.OUT_IO_WE_I2_S1	!MAIN[2][14]
CELL.QUAD_H2[0]	CELL.DEC_V[0]	!MAIN[8][15]
CELL.QUAD_H2[1]	CELL.DEC_V[1]	!MAIN[6][15]
CELL.QUAD_H2[2]	CELL.DEC_V[2]	!MAIN[10][15]
CELL.QUAD_H3[0]	CELL.OUT_IO_WE_I2_S1	!MAIN[1][14]
CELL.QUAD_H3[2]	CELL.OUT_IO_WE_I1_S1	!MAIN[9][14]

xc4000xv CNR_SW switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_H[0]	CELL.DOUBLE_IO_S0[0]	!MAIN[10][9]
CELL.SINGLE_H[0]	CELL.DOUBLE_IO_W2[0]	!MAIN[1][9]
CELL.SINGLE_H[1]	CELL.DOUBLE_IO_W1[0]	!MAIN[7][9]
CELL.SINGLE_H[2]	CELL.DOUBLE_IO_S0[1]	!MAIN[16][13]
CELL.SINGLE_H[2]	CELL.DOUBLE_IO_W2[1]	!MAIN[10][13]
CELL.SINGLE_H[3]	CELL.DOUBLE_IO_W1[1]	!MAIN[14][13]
CELL.SINGLE_H[4]	CELL.DOUBLE_IO_S0[2]	!MAIN[13][9]
CELL.SINGLE_H[4]	CELL.DOUBLE_IO_W2[2]	!MAIN[10][8]
CELL.SINGLE_H[5]	CELL.DOUBLE_IO_W1[2]	!MAIN[14][8]
CELL.SINGLE_H[6]	CELL.DOUBLE_IO_S0[3]	!MAIN[7][13]
CELL.SINGLE_H[6]	CELL.DOUBLE_IO_W2[3]	!MAIN[1][13]
CELL.SINGLE_H[7]	CELL.DOUBLE_IO_W1[3]	!MAIN[5][13]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_S0[0]	!MAIN[9][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_W1[0]	!MAIN[6][9]
CELL.DOUBLE_H0[0]	CELL.DOUBLE_IO_W2[0]	!MAIN[3][9]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_S0[3]	!MAIN[6][13]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_W1[3]	!MAIN[4][13]
CELL.DOUBLE_H0[1]	CELL.DOUBLE_IO_W2[3]	!MAIN[2][13]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_S0[1]	!MAIN[15][13]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_W1[1]	!MAIN[13][13]
CELL.DOUBLE_H1[0]	CELL.DOUBLE_IO_W2[1]	!MAIN[11][13]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_S0[2]	!MAIN[12][9]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_W1[2]	!MAIN[13][8]
CELL.DOUBLE_H1[1]	CELL.DOUBLE_IO_W2[2]	!MAIN[11][8]
CELL.DOUBLE_IO_S0[0]	CELL.DOUBLE_IO_W2[0]	!MAIN[4][9]
CELL.DOUBLE_IO_S0[1]	CELL.DOUBLE_IO_W2[1]	!MAIN[12][13]
CELL.DOUBLE_IO_S0[2]	CELL.DOUBLE_IO_W2[2]	!MAIN[12][8]
CELL.DOUBLE_IO_S0[3]	CELL.DOUBLE_IO_W2[3]	!MAIN[3][13]
CELL.DOUBLE_IO_W1[0]	CELL.QUAD_H1[0]	!MAIN[3][15]
CELL.DOUBLE_IO_W1[1]	CELL.QUAD_H2[1]	!MAIN[7][15]
CELL.DOUBLE_IO_W1[2]	CELL.QUAD_H2[2]	!MAIN[11][15]
CELL.DOUBLE_IO_W1[3]	CELL.QUAD_H0[2]	!MAIN[3][14]
CELL.DOUBLE_IO_W2[0]	CELL.QUAD_H2[0]	!MAIN[9][15]
CELL.DOUBLE_IO_W2[1]	CELL.QUAD_H0[0]	!MAIN[8][14]
CELL.DOUBLE_IO_W2[2]	CELL.QUAD_H1[1]	!MAIN[5][15]
CELL.DOUBLE_IO_W2[3]	CELL.QUAD_H1[2]	!MAIN[4][15]
CELL.QUAD_H3[0]	CELL.LONG_IO_V[3]	!MAIN[5][14]
CELL.QUAD_H3[1]	CELL.LONG_IO_V[2]	!MAIN[2][15]
CELL.QUAD_H3[2]	CELL.LONG_IO_V[1]	!MAIN[10][14]

xc4000xv CNR_SW switchbox INT muxes DBUF_IO_V[0]
Bits				Destination
MAIN[10][7]	MAIN[11][7]	MAIN[13][7]	MAIN[12][7]	CELL.DBUF_IO_V[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_S0[1]
0	1	0	1	CELL.DOUBLE_IO_S0[2]
0	1	1	0	CELL.DOUBLE_IO_S0[3]
1	1	1	1	CELL.DOUBLE_IO_S0[0]

xc4000xv CNR_SW switchbox INT muxes DBUF_IO_V[1]
Bits				Destination
MAIN[16][11]	MAIN[18][12]	MAIN[17][12]	MAIN[16][12]	CELL.DBUF_IO_V[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_W2[0]
0	1	0	1	CELL.DOUBLE_IO_W2[1]
0	1	1	0	CELL.DOUBLE_IO_W2[3]
1	1	1	1	CELL.DOUBLE_IO_W2[2]

xc4000xv CNR_SW switchbox INT muxes LONG_H[3]
Bits		Destination
MAIN[14][10]	MAIN[19][11]	CELL.LONG_H[3]
		Source
0	0	CELL.DEC_V[1]
0	1	CELL.LONG_IO_V[1]
1	1	off

xc4000xv CNR_SW switchbox INT muxes LONG_H[4]
Bits				Destination
MAIN[2][10]	MAIN[1][10]	MAIN[4][11]	MAIN[2][11]	CELL.LONG_H[4]
				Source
0	0	0	1	CELL.LONG_IO_V[2]
0	0	1	0	CELL.DEC_V[2]
0	1	1	1	CELL.OUT_RDBK_DATA
1	1	1	1	off

xc4000xv CNR_SW switchbox INT muxes LONG_H[5]
Bits				Destination
MAIN[11][11]	MAIN[6][10]	MAIN[7][11]	MAIN[10][11]	CELL.LONG_H[5]
				Source
0	0	0	1	CELL.LONG_IO_V[3]
0	0	1	0	CELL.DEC_V[3]
0	1	1	1	CELL.OUT_RDBK_DATA
1	1	1	1	off

xc4000xv CNR_SW switchbox INT muxes LONG_IO_H[0]
Bits		Destination
MAIN[13][4]	MAIN[15][4]	CELL.LONG_IO_H[0]
		Source
0	0	CELL.LONG_IO_V[2]
0	1	CELL.LONG_IO_V[0]
1	1	off

xc4000xv CNR_SW switchbox INT muxes LONG_IO_H[1]
Bits		Destination
MAIN[20][4]	MAIN[22][4]	CELL.LONG_IO_H[1]
		Source
0	0	CELL.LONG_IO_V[3]
0	1	CELL.LONG_IO_V[1]
1	1	off

xc4000xv CNR_SW switchbox INT muxes LONG_IO_H[2]
Bits		Destination
MAIN[11][4]	MAIN[10][4]	CELL.LONG_IO_H[2]
		Source
0	0	CELL.LONG_IO_V[0]
0	1	CELL.LONG_IO_V[2]
1	1	off

xc4000xv CNR_SW switchbox INT muxes LONG_IO_H[3]
Bits		Destination
MAIN[18][4]	MAIN[17][4]	CELL.LONG_IO_H[3]
		Source
0	0	CELL.LONG_IO_V[1]
0	1	CELL.LONG_IO_V[3]
1	1	off

xc4000xv CNR_SW switchbox INT muxes LONG_IO_V[0]
Bits				Destination
MAIN[23][5]	MAIN[20][5]	MAIN[22][5]	MAIN[21][5]	CELL.LONG_IO_V[0]
				Source
0	0	0	1	CELL.LONG_IO_H[0]
0	0	1	0	CELL.LONG_IO_H[2]
0	1	1	1	CELL.SINGLE_H[1]
1	1	1	1	off

xc4000xv CNR_SW switchbox INT muxes LONG_IO_V[1]
Bits					Destination
MAIN[14][5]	MAIN[13][5]	MAIN[16][5]	MAIN[15][5]	MAIN[17][5]	CELL.LONG_IO_V[1]
					Source
0	0	0	1	1	CELL.LONG_H[3]
0	0	1	0	1	CELL.LONG_IO_H[1]
0	0	1	1	0	CELL.LONG_IO_H[3]
0	1	1	1	1	CELL.SINGLE_H[2]
1	1	1	1	1	off

xc4000xv CNR_SW switchbox INT muxes LONG_IO_V[2]
Bits					Destination
MAIN[5][6]	MAIN[1][5]	MAIN[3][5]	MAIN[2][5]	MAIN[4][5]	CELL.LONG_IO_V[2]
					Source
0	0	0	1	1	CELL.LONG_H[4]
0	0	1	0	1	CELL.LONG_IO_H[0]
0	0	1	1	0	CELL.LONG_IO_H[2]
0	1	1	1	1	CELL.SINGLE_H[5]
1	1	1	1	1	off

xc4000xv CNR_SW switchbox INT muxes LONG_IO_V[3]
Bits					Destination
MAIN[6][6]	MAIN[9][5]	MAIN[11][5]	MAIN[10][5]	MAIN[12][5]	CELL.LONG_IO_V[3]
					Source
0	0	0	1	1	CELL.LONG_H[5]
0	0	1	0	1	CELL.LONG_IO_H[1]
0	0	1	1	0	CELL.LONG_IO_H[3]
0	1	1	1	1	CELL.SINGLE_H[6]
1	1	1	1	1	off

xc4000xv CNR_SW switchbox INT muxes ECLK_V
Bits							Destination
MAIN[15][14]	MAIN[20][14]	MAIN[21][14]	MAIN[22][14]	MAIN[13][14]	MAIN[24][14]	MAIN[25][14]	CELL.ECLK_V
							Source
0	0	1	1	0	0	1	CELL.LONG_IO_H[0]
0	0	1	1	1	1	1	CELL.SINGLE_H[2]
0	1	0	1	0	0	1	CELL.LONG_IO_H[1]
0	1	0	1	1	1	1	CELL.SINGLE_H[3]
0	1	1	0	0	0	1	CELL.LONG_IO_H[3]
0	1	1	0	1	1	1	CELL.SINGLE_H[4]
0	1	1	1	0	1	0	CELL.OUT_BUFGE_H
1	1	1	1	0	0	1	CELL.DOUBLE_IO_W2[3]
1	1	1	1	1	1	1	CELL.SINGLE_H[5]

xc4000xv CNR_SW switchbox INT muxes IMUX_CLB_F2
Bits		Destination
MAIN[16][14]	MAIN[16][15]	CELL.IMUX_CLB_F2
		Source
0	0	CELL_N.LONG_V[7]
0	1	CELL_N.LONG_V[8]
1	0	CELL_N.LONG_V[9]
1	1	CELL_N.GCLK[7]

xc4000xv CNR_SW switchbox INT muxes IMUX_CLB_G2
Bits		Destination
MAIN[14][15]	MAIN[14][14]	CELL.IMUX_CLB_G2
		Source
0	0	CELL_N.LONG_V[6]
0	1	CELL_N.LONG_V[8]
1	0	CELL_N.GCLK[7]
1	1	CELL_N.LONG_V[9]

xc4000xv CNR_SW switchbox INT muxes IMUX_CLB_C2
Bits					Destination
MAIN[18][14]	MAIN[17][14]	MAIN[18][15]	MAIN[19][14]	MAIN[17][15]	CELL.IMUX_CLB_C2
					Source
0	1	1	1	1	CELL_N.LONG_V[1]
1	0	1	1	1	CELL_N.LONG_V[5]
1	1	0	1	1	CELL_N.LONG_V[7]
1	1	1	0	1	CELL_N.LONG_V[8]
1	1	1	1	0	CELL_N.GCLK[6]
1	1	1	1	1	off

xc4000xv CNR_SW switchbox INT muxes IMUX_IO_O1[1]
Bits						Destination
MAIN[5][5]	MAIN[5][3]	MAIN[6][5]	MAIN[5][4]	MAIN[7][5]	MAIN[8][5]	CELL.IMUX_IO_O1[1]
						Source
0	0	1	1	1	0	CELL_N.LONG_V[0]
0	0	1	1	1	1	CELL.SINGLE_H[2]
0	1	0	1	1	0	CELL_N.LONG_V[1]
0	1	0	1	1	1	CELL.SINGLE_H[3]
0	1	1	0	1	0	CELL_N.LONG_V[2]
0	1	1	0	1	1	CELL.SINGLE_H[4]
0	1	1	1	0	1	CELL.SINGLE_H[5]
1	1	1	1	1	0	CELL_N.DOUBLE_V0[1]
1	1	1	1	1	1	CELL_N.DOUBLE_V1[0]

xc4000xv CNR_SW switchbox INT muxes IMUX_IO_IK[1]
Bits						Destination
MAIN[3][7]	MAIN[1][7]	MAIN[2][6]	MAIN[3][6]	MAIN[2][7]	MAIN[4][6]	CELL.IMUX_IO_IK[1]
						Source
0	0	0	1	1	1	CELL.LONG_H[3]
0	0	1	0	1	1	CELL.LONG_H[4]
0	0	1	1	0	1	CELL.LONG_H[5]
0	1	1	1	1	1	CELL.DOUBLE_H0[0]
1	0	0	1	1	1	CELL_N.SINGLE_V[2]
1	0	1	0	1	1	CELL_N.SINGLE_V[3]
1	0	1	1	0	1	CELL_N.SINGLE_V[4]
1	0	1	1	1	0	CELL_N.SINGLE_V[5]
1	1	1	1	1	1	CELL.DOUBLE_H1[1]

xc4000xv CNR_SW switchbox INT muxes IMUX_BUFG_H
Bits							Destination
MAIN[1][3]	MAIN[3][3]	MAIN[3][2]	MAIN[2][3]	MAIN[2][2]	MAIN[1][2]	MAIN[4][3]	CELL.IMUX_BUFG_H
							Source
0	0	0	0	1	1	1	CELL.DOUBLE_IO_S0[0]
0	0	0	1	0	1	1	CELL.DOUBLE_IO_S0[1]
0	0	0	1	1	0	1	CELL.DOUBLE_IO_S0[2]
0	0	1	0	1	1	1	CELL.DOUBLE_IO_W1[2]
0	0	1	1	0	1	1	CELL.DOUBLE_IO_S0[3]
0	0	1	1	1	0	1	CELL.DOUBLE_IO_W1[3]
0	1	1	1	1	1	0	CELL.OUT_IO_CLKIN_W
0	1	1	1	1	1	1	off
1	0	0	1	1	1	1	CELL.DOUBLE_IO_W1[0]
1	0	1	1	1	1	1	CELL.DOUBLE_IO_W1[1]

xc4000xv CNR_SW switchbox INT muxes IMUX_BUFG_V
Bits						Destination
MAIN[7][3]	MAIN[21][4]	MAIN[9][4]	MAIN[19][4]	MAIN[12][4]	MAIN[23][4]	CELL.IMUX_BUFG_V
						Source
0	0	0	1	1	1	CELL.OCTAL_IO_S[0]
0	0	1	0	1	1	CELL.LONG_IO_H[0]
0	0	1	1	0	1	CELL.LONG_IO_V[0]
0	1	1	1	1	0	CELL.OUT_IO_CLKIN_S
0	1	1	1	1	1	off
1	0	1	1	1	1	CELL.OCTAL_IO_S[7]

xc4000xv CNR_SW switchbox INT muxes IMUX_RDBK_TRIG
Bits				Destination
MAIN[6][4]	MAIN[7][4]	MAIN[18][5]	MAIN[19][5]	CELL.IMUX_RDBK_TRIG
				Source
0	0	1	1	CELL.SINGLE_H[3]
0	1	0	1	CELL.SINGLE_H[4]
0	1	1	0	CELL.SINGLE_H[5]
1	1	1	1	CELL.SINGLE_H[2]

Bels PULLUP

xc4000xv CNR_SW bel PULLUP pins
Pin	Direction	PULLUP_DEC_H[0]	PULLUP_DEC_H[1]	PULLUP_DEC_H[2]	PULLUP_DEC_H[3]	PULLUP_DEC_V[0]	PULLUP_DEC_V[1]	PULLUP_DEC_V[2]	PULLUP_DEC_V[3]
O	bidir	CELL.DEC_H[0]	CELL.DEC_H[1]	CELL.DEC_H[2]	CELL.DEC_H[3]	CELL.DEC_V[0]	CELL.DEC_V[1]	CELL.DEC_V[2]	CELL.DEC_V[3]

xc4000xv CNR_SW bel PULLUP attribute bits
Attribute	PULLUP_DEC_H[0]	PULLUP_DEC_H[1]	PULLUP_DEC_H[2]	PULLUP_DEC_H[3]	PULLUP_DEC_V[0]	PULLUP_DEC_V[1]	PULLUP_DEC_V[2]	PULLUP_DEC_V[3]
ENABLE	!MAIN[1][4]	!MAIN[2][4]	!MAIN[3][4]	!MAIN[4][4]	!MAIN[22][12]	!MAIN[23][12]	!MAIN[21][12]	!MAIN[24][12]

Bels BUFG

xc4000xv CNR_SW bel BUFG pins
Pin	Direction	BUFG_H	BUFG_V
I	in	CELL.IMUX_BUFG_H	CELL.IMUX_BUFG_V
O	out	CELL.BUFGLS[2]	CELL.BUFGLS[1]
O_BUFGE	out	CELL.OUT_BUFGE_H	CELL.OUT_BUFGE_V

xc4000xv CNR_SW bel BUFG attribute bits
Attribute	BUFG_H	BUFG_V
CLK_EN	!MAIN[7][2]	!MAIN[8][3]
ALT_PAD	!MAIN[6][2]	!MAIN[8][2]

Bels IBUF

xc4000xv CNR_SW bel IBUF pins
Pin	Direction	MD0	MD2
I	out	CELL.OUT_MD0_I	CELL.OUT_IO_SN_I1[1]

xc4000xv CNR_SW bel IBUF attribute bits
Attribute	MD0	MD2
PULL	[enum: IO_PULL]	[enum: IO_PULL]

xc4000xv CNR_SW enum IO_PULL
MD0.PULL	MAIN[25][4]	MAIN[24][4]
MD2.PULL	MAIN[5][2]	MAIN[4][2]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

Bels MD1

xc4000xv CNR_SW bel MD1 pins
Pin	Direction	MD1
O	in	CELL.IMUX_IO_O1[1]
T	in	CELL.IMUX_IO_IK[1]

xc4000xv CNR_SW bel MD1 attribute bits
Attribute	MD1
PULL	[enum: IO_PULL]
T_ENABLE	!MAIN[25][11]
O_ENABLE	!MAIN[24][11]

xc4000xv CNR_SW enum IO_PULL
MD1.PULL	MAIN[26][12]	MAIN[25][12]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

Bels RDBK

xc4000xv CNR_SW bel RDBK pins
Pin	Direction	RDBK
TRIG	in	CELL.IMUX_RDBK_TRIG
DATA	out	CELL.OUT_RDBK_DATA
RIP	out	CELL.OUT_IO_SN_I2[1]

xc4000xv CNR_SW bel RDBK attribute bits
Attribute	RDBK
ENABLE	!MAIN[24][5]
READ_ABORT	!MAIN[16][4]
READ_CAPTURE	!MAIN[14][4]

Bels MISC_SW

xc4000xv CNR_SW bel MISC_SW pins
Pin	Direction	MISC_SW

xc4000xv CNR_SW bel MISC_SW attribute bits
Attribute	MISC_SW
TM_BOT	!MAIN[8][4]
IO_5V_TOLERANT	MAIN[6][3]

Bel wires

xc4000xv CNR_SW bel wires
Wire	Pins
CELL.DEC_H[0]	PULLUP_DEC_H[0].O
CELL.DEC_H[1]	PULLUP_DEC_H[1].O
CELL.DEC_H[2]	PULLUP_DEC_H[2].O
CELL.DEC_H[3]	PULLUP_DEC_H[3].O
CELL.DEC_V[0]	PULLUP_DEC_V[0].O
CELL.DEC_V[1]	PULLUP_DEC_V[1].O
CELL.DEC_V[2]	PULLUP_DEC_V[2].O
CELL.DEC_V[3]	PULLUP_DEC_V[3].O
CELL.BUFGLS[1]	BUFG_V.O
CELL.BUFGLS[2]	BUFG_H.O
CELL.IMUX_IO_O1[1]	MD1.O
CELL.IMUX_IO_IK[1]	MD1.T
CELL.IMUX_BUFG_H	BUFG_H.I
CELL.IMUX_BUFG_V	BUFG_V.I
CELL.IMUX_RDBK_TRIG	RDBK.TRIG
CELL.OUT_IO_SN_I1[1]	MD2.I
CELL.OUT_IO_SN_I2[1]	RDBK.RIP
CELL.OUT_MD0_I	MD0.I
CELL.OUT_RDBK_DATA	RDBK.DATA
CELL.OUT_BUFGE_H	BUFG_H.O_BUFGE
CELL.OUT_BUFGE_V	BUFG_V.O_BUFGE

Bitstream

xc4000xv CNR_SW rect MAIN
Bit	Frame
Bit	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	INT: mux CELL.IMUX_CLB_C2 bit 2	INT: mux CELL.IMUX_CLB_C2 bit 0	INT: mux CELL.IMUX_CLB_F2 bit 0	-	INT: mux CELL.IMUX_CLB_G2 bit 1	-	-	INT: !bipass CELL.DOUBLE_IO_W1[2] = CELL.QUAD_H2[2]	INT: !pass CELL.QUAD_H2[2] ← CELL.DEC_V[2]	INT: !bipass CELL.DOUBLE_IO_W2[0] = CELL.QUAD_H2[0]	INT: !pass CELL.QUAD_H2[0] ← CELL.DEC_V[0]	INT: !bipass CELL.DOUBLE_IO_W1[1] = CELL.QUAD_H2[1]	INT: !pass CELL.QUAD_H2[1] ← CELL.DEC_V[1]	INT: !bipass CELL.DOUBLE_IO_W2[2] = CELL.QUAD_H1[1]	INT: !bipass CELL.DOUBLE_IO_W2[3] = CELL.QUAD_H1[2]	INT: !bipass CELL.DOUBLE_IO_W1[0] = CELL.QUAD_H1[0]	INT: !bipass CELL.QUAD_H3[1] = CELL.LONG_IO_V[2]	-	-
B14	-	INT: mux CELL.ECLK_V bit 0	INT: mux CELL.ECLK_V bit 1	-	INT: mux CELL.ECLK_V bit 3	INT: mux CELL.ECLK_V bit 4	INT: mux CELL.ECLK_V bit 5	INT: mux CELL.IMUX_CLB_C2 bit 1	INT: mux CELL.IMUX_CLB_C2 bit 4	INT: mux CELL.IMUX_CLB_C2 bit 3	INT: mux CELL.IMUX_CLB_F2 bit 1	INT: mux CELL.ECLK_V bit 6	INT: mux CELL.IMUX_CLB_G2 bit 0	INT: mux CELL.ECLK_V bit 2	-	INT: !pass CELL.QUAD_H0[1] ← CELL.OUT_IO_WE_I1_S1	INT: !bipass CELL.QUAD_H3[2] = CELL.LONG_IO_V[1]	INT: !pass CELL.QUAD_H3[2] ← CELL.OUT_IO_WE_I1_S1	INT: !bipass CELL.DOUBLE_IO_W2[1] = CELL.QUAD_H0[0]	-	-	INT: !bipass CELL.QUAD_H3[0] = CELL.LONG_IO_V[3]	-	INT: !bipass CELL.DOUBLE_IO_W1[3] = CELL.QUAD_H0[2]	INT: !pass CELL.QUAD_H0[2] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.QUAD_H3[0] ← CELL.OUT_IO_WE_I2_S1	-
B13	-	-	-	-	-	-	-	-	-	INT: !pass CELL.SINGLE_H[3] ← CELL.DEC_V[2]	INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_S0[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_S0[1]	INT: !bipass CELL.SINGLE_H[3] = CELL.DOUBLE_IO_W1[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W1[1]	INT: !bipass CELL.DOUBLE_IO_S0[1] = CELL.DOUBLE_IO_W2[1]	INT: !bipass CELL.DOUBLE_H1[0] = CELL.DOUBLE_IO_W2[1]	INT: !bipass CELL.SINGLE_H[2] = CELL.DOUBLE_IO_W2[1]	INT: !pass CELL.SINGLE_H[7] ← CELL.DEC_V[0]	-	INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_S0[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_S0[3]	INT: !bipass CELL.SINGLE_H[7] = CELL.DOUBLE_IO_W1[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W1[3]	INT: !bipass CELL.DOUBLE_IO_S0[3] = CELL.DOUBLE_IO_W2[3]	INT: !bipass CELL.DOUBLE_H0[1] = CELL.DOUBLE_IO_W2[3]	INT: !bipass CELL.SINGLE_H[6] = CELL.DOUBLE_IO_W2[3]	-
B12	MD1: PULL bit 1	MD1: PULL bit 0	PULLUP_DEC_V[3]: ! ENABLE	PULLUP_DEC_V[1]: ! ENABLE	PULLUP_DEC_V[0]: ! ENABLE	PULLUP_DEC_V[2]: ! ENABLE	-	INT: !pass CELL.SINGLE_H[2] ← CELL.LONG_IO_V[1]	INT: mux CELL.DBUF_IO_V[1] bit 2	INT: mux CELL.DBUF_IO_V[1] bit 1	INT: mux CELL.DBUF_IO_V[1] bit 0	-	-	-	-	INT: !pass CELL.SINGLE_H[3] ← CELL.OUT_IO_WE_I1_S1	INT: !pass CELL.DOUBLE_IO_W2[1] ← CELL.DBUF_IO_V[0]	-	-	-	-	INT: !pass CELL.DOUBLE_H1[0] ← CELL.OUT_MD0_I	INT: !pass CELL.SINGLE_H[6] ← CELL.LONG_IO_V[3]	-	INT: !pass CELL.SINGLE_H[6] ← CELL.OUT_MD0_I	INT: !pass CELL.SINGLE_H[7] ← CELL.OUT_IO_WE_I1_S1	-
B11	-	MD1: ! T_ENABLE	MD1: ! O_ENABLE	-	-	-	-	INT: mux CELL.LONG_H[3] bit 0	-	-	INT: mux CELL.DBUF_IO_V[1] bit 3	-	-	-	-	INT: mux CELL.LONG_H[5] bit 3	INT: mux CELL.LONG_H[5] bit 0	INT: !pass CELL.DOUBLE_IO_W2[3] ← CELL.DBUF_IO_V[0]	-	INT: mux CELL.LONG_H[5] bit 1	-	INT: !pass CELL.SINGLE_H[2] ← CELL.OUT_MD0_I	INT: mux CELL.LONG_H[4] bit 1	INT: !pass CELL.DOUBLE_H0[0] ← CELL.OUT_IO_WE_I1_S1	INT: mux CELL.LONG_H[4] bit 0	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	INT: mux CELL.LONG_H[3] bit 1	-	-	INT: !pass CELL.DOUBLE_IO_S0[1] ← CELL.DBUF_IO_V[1]	-	INT: !pass CELL.DOUBLE_IO_W2[2] ← CELL.DBUF_IO_V[0]	-	INT: !pass CELL.DOUBLE_IO_W2[0] ← CELL.DBUF_IO_V[0]	INT: mux CELL.LONG_H[5] bit 2	-	INT: !pass CELL.DOUBLE_IO_S0[3] ← CELL.DBUF_IO_V[1]	INT: !pass CELL.DOUBLE_H0[1] ← CELL.OUT_RDBK_DATA	INT: mux CELL.LONG_H[4] bit 3	INT: mux CELL.LONG_H[4] bit 2	-
B9	-	-	-	-	-	-	-	-	-	-	-	INT: !pass CELL.SINGLE_H[4] ← CELL.DEC_V[1]	INT: !pass CELL.DOUBLE_IO_S0[2] ← CELL.DBUF_IO_V[1]	INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_S0[2]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_S0[2]	INT: !pass CELL.DOUBLE_IO_S0[0] ← CELL.DBUF_IO_V[1]	INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_S0[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_S0[0]	-	INT: !bipass CELL.SINGLE_H[1] = CELL.DOUBLE_IO_W1[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W1[0]	-	INT: !bipass CELL.DOUBLE_IO_S0[0] = CELL.DOUBLE_IO_W2[0]	INT: !bipass CELL.DOUBLE_H0[0] = CELL.DOUBLE_IO_W2[0]	-	INT: !bipass CELL.SINGLE_H[0] = CELL.DOUBLE_IO_W2[0]	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	INT: !bipass CELL.SINGLE_H[5] = CELL.DOUBLE_IO_W1[2]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W1[2]	INT: !bipass CELL.DOUBLE_IO_S0[2] = CELL.DOUBLE_IO_W2[2]	INT: !bipass CELL.DOUBLE_H1[1] = CELL.DOUBLE_IO_W2[2]	INT: !bipass CELL.SINGLE_H[4] = CELL.DOUBLE_IO_W2[2]	INT: !pass CELL.SINGLE_H[0] ← CELL.DEC_V[3]	-	INT: !pass CELL.SINGLE_H[5] ← CELL.LONG_IO_V[2]	INT: !pass CELL.SINGLE_H[5] ← CELL.OUT_RDBK_DATA	INT: !pass CELL.SINGLE_H[1] ← CELL.OUT_RDBK_DATA	INT: !pass CELL.SINGLE_H[1] ← CELL.LONG_IO_V[0]	INT: !pass CELL.DOUBLE_H1[1] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[0] ← CELL.OUT_IO_WE_I2_S1	INT: !pass CELL.SINGLE_H[4] ← CELL.OUT_IO_WE_I2_S1	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	INT: mux CELL.DBUF_IO_V[0] bit 1	INT: mux CELL.DBUF_IO_V[0] bit 0	INT: mux CELL.DBUF_IO_V[0] bit 2	INT: mux CELL.DBUF_IO_V[0] bit 3	-	-	-	-	-	-	INT: mux CELL.IMUX_IO_IK[1] bit 5	INT: mux CELL.IMUX_IO_IK[1] bit 1	INT: mux CELL.IMUX_IO_IK[1] bit 4	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INT: mux CELL.LONG_IO_V[3] bit 4	INT: mux CELL.LONG_IO_V[2] bit 4	INT: mux CELL.IMUX_IO_IK[1] bit 0	INT: mux CELL.IMUX_IO_IK[1] bit 2	INT: mux CELL.IMUX_IO_IK[1] bit 3	-	-
B5	-	-	RDBK: ! ENABLE	INT: mux CELL.LONG_IO_V[0] bit 3	INT: mux CELL.LONG_IO_V[0] bit 1	INT: mux CELL.LONG_IO_V[0] bit 0	INT: mux CELL.LONG_IO_V[0] bit 2	INT: mux CELL.IMUX_RDBK_TRIG bit 0	INT: mux CELL.IMUX_RDBK_TRIG bit 1	INT: mux CELL.LONG_IO_V[1] bit 0	INT: mux CELL.LONG_IO_V[1] bit 2	INT: mux CELL.LONG_IO_V[1] bit 1	INT: mux CELL.LONG_IO_V[1] bit 4	INT: mux CELL.LONG_IO_V[1] bit 3	INT: mux CELL.LONG_IO_V[3] bit 0	INT: mux CELL.LONG_IO_V[3] bit 2	INT: mux CELL.LONG_IO_V[3] bit 1	INT: mux CELL.LONG_IO_V[3] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 0	INT: mux CELL.IMUX_IO_O1[1] bit 1	INT: mux CELL.IMUX_IO_O1[1] bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 5	INT: mux CELL.LONG_IO_V[2] bit 0	INT: mux CELL.LONG_IO_V[2] bit 2	INT: mux CELL.LONG_IO_V[2] bit 1	INT: mux CELL.LONG_IO_V[2] bit 3	-
B4	-	MD0: PULL bit 1	MD0: PULL bit 0	INT: mux CELL.IMUX_BUFG_V bit 0	INT: mux CELL.LONG_IO_H[1] bit 0	INT: mux CELL.IMUX_BUFG_V bit 4	INT: mux CELL.LONG_IO_H[1] bit 1	INT: mux CELL.IMUX_BUFG_V bit 2	INT: mux CELL.LONG_IO_H[3] bit 1	INT: mux CELL.LONG_IO_H[3] bit 0	RDBK: ! READ_ABORT	INT: mux CELL.LONG_IO_H[0] bit 0	RDBK: ! READ_CAPTURE	INT: mux CELL.LONG_IO_H[0] bit 1	INT: mux CELL.IMUX_BUFG_V bit 1	INT: mux CELL.LONG_IO_H[2] bit 1	INT: mux CELL.LONG_IO_H[2] bit 0	INT: mux CELL.IMUX_BUFG_V bit 3	MISC_SW: ! TM_BOT	INT: mux CELL.IMUX_RDBK_TRIG bit 2	INT: mux CELL.IMUX_RDBK_TRIG bit 3	INT: mux CELL.IMUX_IO_O1[1] bit 2	PULLUP_DEC_H[3]: ! ENABLE	PULLUP_DEC_H[2]: ! ENABLE	PULLUP_DEC_H[1]: ! ENABLE	PULLUP_DEC_H[0]: ! ENABLE	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFG_V: ! CLK_EN	INT: mux CELL.IMUX_BUFG_V bit 5	MISC_SW: IO_5V_TOLERANT	INT: mux CELL.IMUX_IO_O1[1] bit 4	INT: mux CELL.IMUX_BUFG_H bit 0	INT: mux CELL.IMUX_BUFG_H bit 5	INT: mux CELL.IMUX_BUFG_H bit 3	INT: mux CELL.IMUX_BUFG_H bit 6	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFG_V: ! ALT_PAD	BUFG_H: ! CLK_EN	BUFG_H: ! ALT_PAD	MD2: PULL bit 1	MD2: PULL bit 0	INT: mux CELL.IMUX_BUFG_H bit 4	INT: mux CELL.IMUX_BUFG_H bit 2	INT: mux CELL.IMUX_BUFG_H bit 1	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile CNR_NW

Cells: 4

Switchbox INT

xc4000xv CNR_NW switchbox INT permanent buffers
Destination	Source
CELL.BUFGE_H	CELL.OUT_BUFGE_H
CELL.BUFGE_V[1]	CELL.OUT_BUFGE_V

xc4000xv CNR_NW switchbox INT muxes LONG_H[0]
Bits				Destination
MAIN[12][4]	MAIN[13][4]	MAIN[14][4]	MAIN[15][4]	CELL.LONG_H[0]
				Source
0	0	0	1	CELL.LONG_IO_V[0]
0	0	1	0	CELL.DEC_V[0]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000xv CNR_NW switchbox INT muxes LONG_H[1]
Bits				Destination
MAIN[19][4]	MAIN[16][4]	MAIN[18][4]	MAIN[17][4]	CELL.LONG_H[1]
				Source
0	0	0	1	CELL.LONG_IO_V[1]
0	0	1	0	CELL.DEC_V[1]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000xv CNR_NW switchbox INT muxes LONG_H[2]
Bits		Destination
MAIN[19][3]	MAIN[18][3]	CELL.LONG_H[2]
		Source
0	0	CELL.LONG_IO_V[2]
0	1	CELL.DEC_V[2]
1	1	off

xc4000xv CNR_NW switchbox INT muxes LONG_IO_H[0]
Bits		Destination
MAIN[1][4]	MAIN[4][3]	CELL.LONG_IO_H[0]
		Source
0	0	CELL.LONG_IO_V[2]
0	1	CELL.LONG_IO_V[0]
1	1	off

xc4000xv CNR_NW switchbox INT muxes LONG_IO_H[1]
Bits		Destination
MAIN[6][6]	MAIN[6][5]	CELL.LONG_IO_H[1]
		Source
0	0	CELL.LONG_IO_V[3]
0	1	CELL.LONG_IO_V[1]
1	1	off

xc4000xv CNR_NW switchbox INT muxes LONG_IO_H[2]
Bits		Destination
MAIN[7][3]	MAIN[6][3]	CELL.LONG_IO_H[2]
		Source
0	0	CELL.LONG_IO_V[0]
0	1	CELL.LONG_IO_V[2]
1	1	off

xc4000xv CNR_NW switchbox INT muxes LONG_IO_H[3]
Bits		Destination
MAIN[1][6]	MAIN[4][5]	CELL.LONG_IO_H[3]
		Source
0	0	CELL.LONG_IO_V[1]
0	1	CELL.LONG_IO_V[3]
1	1	off

xc4000xv CNR_NW switchbox INT muxes LONG_IO_V[0]
Bits				Destination
MAIN[10][3]	MAIN[7][4]	MAIN[11][3]	MAIN[12][3]	CELL.LONG_IO_V[0]
				Source
0	0	0	1	CELL.LONG_H[0]
0	0	1	0	CELL.LONG_IO_H[2]
0	1	1	1	CELL.LONG_IO_H[0]
1	1	1	1	off

xc4000xv CNR_NW switchbox INT muxes LONG_IO_V[1]
Bits				Destination
MAIN[8][5]	MAIN[10][5]	MAIN[11][5]	MAIN[12][5]	CELL.LONG_IO_V[1]
				Source
0	0	0	1	CELL.LONG_H[1]
0	0	1	0	CELL.LONG_IO_H[3]
0	1	1	1	CELL.LONG_IO_H[1]
1	1	1	1	off

xc4000xv CNR_NW switchbox INT muxes LONG_IO_V[2]
Bits				Destination
MAIN[16][3]	MAIN[13][3]	MAIN[15][3]	MAIN[14][3]	CELL.LONG_IO_V[2]
				Source
0	0	0	1	CELL.LONG_H[2]
0	0	1	0	CELL.LONG_IO_H[0]
0	1	1	1	CELL.LONG_IO_H[2]
1	1	1	1	off

xc4000xv CNR_NW switchbox INT muxes LONG_IO_V[3]
Bits		Destination
MAIN[15][5]	MAIN[14][5]	CELL.LONG_IO_V[3]
		Source
0	0	CELL.LONG_IO_H[1]
0	1	CELL.LONG_IO_H[3]
1	1	off

xc4000xv CNR_NW switchbox INT muxes IMUX_BUFG_H
Bits							Destination
MAIN[1][8]	MAIN[4][6]	MAIN[2][7]	MAIN[2][6]	MAIN[3][6]	MAIN[1][7]	MAIN[5][6]	CELL.IMUX_BUFG_H
							Source
0	0	0	0	1	1	1	CELL.DOUBLE_IO_N1[0]
0	0	0	1	0	1	1	CELL.DOUBLE_IO_N1[1]
0	0	0	1	1	0	1	CELL.DOUBLE_IO_N1[2]
0	0	1	0	1	1	1	CELL.DOUBLE_IO_N2[2]
0	0	1	1	0	1	1	CELL.DOUBLE_IO_N1[3]
0	0	1	1	1	0	1	CELL.DOUBLE_IO_N2[3]
0	1	1	1	1	1	0	CELL.OUT_IO_CLKIN_W
0	1	1	1	1	1	1	off
1	0	0	1	1	1	1	CELL.DOUBLE_IO_N2[0]
1	0	1	1	1	1	1	CELL.DOUBLE_IO_N2[1]

xc4000xv CNR_NW switchbox INT muxes IMUX_BUFG_V
Bits						Destination
MAIN[19][2]	MAIN[23][2]	MAIN[22][2]	MAIN[21][2]	MAIN[20][2]	MAIN[20][3]	CELL.IMUX_BUFG_V
						Source
0	0	0	1	1	1	CELL.OCTAL_IO_W[0]
0	0	1	0	1	1	CELL.OCTAL_IO_W[7]
0	0	1	1	0	1	CELL.LONG_IO_V[0]
0	1	1	1	1	0	CELL.OUT_IO_CLKIN_N
0	1	1	1	1	1	off
1	0	1	1	1	1	CELL.LONG_IO_H[0]

xc4000xv CNR_NW switchbox INT muxes IMUX_BSCAN_TDO1
Bits						Destination
MAIN[2][5]	MAIN[1][5]	MAIN[3][4]	MAIN[2][4]	MAIN[3][5]	MAIN[4][4]	CELL.IMUX_BSCAN_TDO1
						Source
0	0	0	1	1	1	CELL_E.LONG_V[0]
0	0	1	0	1	1	CELL_E.LONG_V[1]
0	0	1	1	0	1	CELL_E.LONG_V[2]
0	1	1	1	1	1	CELL_E.DOUBLE_V0[1]
1	0	0	1	1	1	CELL_S.SINGLE_H[2]
1	0	1	0	1	1	CELL_S.SINGLE_H[3]
1	0	1	1	0	1	CELL_S.SINGLE_H[4]
1	0	1	1	1	0	CELL_S.SINGLE_H[5]
1	1	1	1	1	1	CELL_E.DOUBLE_V1[0]

xc4000xv CNR_NW switchbox INT muxes IMUX_BSCAN_TDO2
Bits						Destination
MAIN[1][2]	MAIN[3][3]	MAIN[2][3]	MAIN[3][2]	MAIN[2][2]	MAIN[1][3]	CELL.IMUX_BSCAN_TDO2
						Source
0	0	0	1	1	1	CELL.LONG_H[0]
0	0	1	0	1	1	CELL.LONG_H[1]
0	0	1	1	0	1	CELL.LONG_H[2]
0	1	0	1	1	1	CELL_E.SINGLE_V[2]
0	1	1	0	1	1	CELL_E.SINGLE_V[3]
0	1	1	1	0	1	CELL_E.SINGLE_V[4]
0	1	1	1	1	0	CELL_E.SINGLE_V[5]
1	0	1	1	1	1	CELL_S.DOUBLE_H0[1]
1	1	1	1	1	1	CELL_S.DOUBLE_H1[0]

Bels PULLUP

xc4000xv CNR_NW bel PULLUP pins
Pin	Direction	PULLUP_DEC_H[0]	PULLUP_DEC_H[1]	PULLUP_DEC_H[2]	PULLUP_DEC_H[3]	PULLUP_DEC_V[0]	PULLUP_DEC_V[1]	PULLUP_DEC_V[2]	PULLUP_DEC_V[3]
O	bidir	CELL.DEC_H[0]	CELL.DEC_H[1]	CELL.DEC_H[2]	CELL.DEC_H[3]	CELL.DEC_V[0]	CELL.DEC_V[1]	CELL.DEC_V[2]	CELL.DEC_V[3]

xc4000xv CNR_NW bel PULLUP attribute bits
Attribute	PULLUP_DEC_H[0]	PULLUP_DEC_H[1]	PULLUP_DEC_H[2]	PULLUP_DEC_H[3]	PULLUP_DEC_V[0]	PULLUP_DEC_V[1]	PULLUP_DEC_V[2]	PULLUP_DEC_V[3]
ENABLE	!MAIN[7][5]	!MAIN[5][5]	!MAIN[5][4]	!MAIN[6][4]	!MAIN[9][2]	!MAIN[11][2]	!MAIN[10][2]	!MAIN[16][2]

Bels BUFG

xc4000xv CNR_NW bel BUFG pins
Pin	Direction	BUFG_H	BUFG_V
I	in	CELL.IMUX_BUFG_H	CELL.IMUX_BUFG_V
O	out	CELL.BUFGLS[7]	CELL.BUFGLS[0]
O_BUFGE	out	CELL.OUT_BUFGE_H	CELL.OUT_BUFGE_V

xc4000xv CNR_NW bel BUFG attribute bits
Attribute	BUFG_H	BUFG_V
CLK_EN	!MAIN[4][8]	!MAIN[17][2]
ALT_PAD	!MAIN[5][8]	!MAIN[18][5]

Bels BSCAN

xc4000xv CNR_NW bel BSCAN pins
Pin	Direction	BSCAN
TDO1	in	CELL.IMUX_BSCAN_TDO1
TDO2	in	CELL.IMUX_BSCAN_TDO2
DRCK	out	CELL.OUT_IO_SN_I2[1]
IDLE	out	CELL.OUT_IO_WE_I2[1]
SEL1	out	CELL.OUT_IO_WE_I1[1]
SEL2	out	CELL.OUT_IO_SN_I1[1]

xc4000xv CNR_NW bel BSCAN attribute bits
Attribute	BSCAN
ENABLE	MAIN[16][5]
CONFIG	MAIN[25][8]

Bels MISC_NW

xc4000xv CNR_NW bel MISC_NW pins
Pin	Direction	MISC_NW

xc4000xv CNR_NW bel MISC_NW attribute bits
Attribute	MISC_NW
IO_ISTD	[enum: IO_STD]
IO_OSTD	[enum: IO_STD]
TM_LEFT	!MAIN[13][5]
TM_TOP	!MAIN[7][6]
_3V	!MAIN[3][8]

xc4000xv CNR_NW enum IO_STD
MISC_NW.IO_ISTD	MAIN[2][8]
MISC_NW.IO_OSTD	MAIN[20][4]
CMOS	0
TTL	1

Bel wires

xc4000xv CNR_NW bel wires
Wire	Pins
CELL.DEC_H[0]	PULLUP_DEC_H[0].O
CELL.DEC_H[1]	PULLUP_DEC_H[1].O
CELL.DEC_H[2]	PULLUP_DEC_H[2].O
CELL.DEC_H[3]	PULLUP_DEC_H[3].O
CELL.DEC_V[0]	PULLUP_DEC_V[0].O
CELL.DEC_V[1]	PULLUP_DEC_V[1].O
CELL.DEC_V[2]	PULLUP_DEC_V[2].O
CELL.DEC_V[3]	PULLUP_DEC_V[3].O
CELL.BUFGLS[0]	BUFG_V.O
CELL.BUFGLS[7]	BUFG_H.O
CELL.IMUX_BUFG_H	BUFG_H.I
CELL.IMUX_BUFG_V	BUFG_V.I
CELL.IMUX_BSCAN_TDO1	BSCAN.TDO1
CELL.IMUX_BSCAN_TDO2	BSCAN.TDO2
CELL.OUT_IO_SN_I1[1]	BSCAN.SEL2
CELL.OUT_IO_SN_I2[1]	BSCAN.DRCK
CELL.OUT_IO_WE_I1[1]	BSCAN.SEL1
CELL.OUT_IO_WE_I2[1]	BSCAN.IDLE
CELL.OUT_BUFGE_H	BUFG_H.O_BUFGE
CELL.OUT_BUFGE_V	BUFG_V.O_BUFGE

Bitstream

xc4000xv CNR_NW rect MAIN
Bit	Frame
Bit	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B8	-	BSCAN: CONFIG	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFG_H: ! ALT_PAD	BUFG_H: ! CLK_EN	MISC_NW: ! _3V	MISC_NW: IO_ISTD bit 0	INT: mux CELL.IMUX_BUFG_H bit 6	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INT: mux CELL.IMUX_BUFG_H bit 4	INT: mux CELL.IMUX_BUFG_H bit 1	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	MISC_NW: ! TM_TOP	INT: mux CELL.LONG_IO_H[1] bit 1	INT: mux CELL.IMUX_BUFG_H bit 0	INT: mux CELL.IMUX_BUFG_H bit 5	INT: mux CELL.IMUX_BUFG_H bit 2	INT: mux CELL.IMUX_BUFG_H bit 3	INT: mux CELL.LONG_IO_H[3] bit 1	-
B5	-	-	-	-	-	-	-	-	BUFG_V: ! ALT_PAD	-	BSCAN: ENABLE	INT: mux CELL.LONG_IO_V[3] bit 1	INT: mux CELL.LONG_IO_V[3] bit 0	MISC_NW: ! TM_LEFT	INT: mux CELL.LONG_IO_V[1] bit 0	INT: mux CELL.LONG_IO_V[1] bit 1	INT: mux CELL.LONG_IO_V[1] bit 2	-	INT: mux CELL.LONG_IO_V[1] bit 3	PULLUP_DEC_H[0]: ! ENABLE	INT: mux CELL.LONG_IO_H[1] bit 0	PULLUP_DEC_H[1]: ! ENABLE	INT: mux CELL.LONG_IO_H[3] bit 0	INT: mux CELL.IMUX_BSCAN_TDO1 bit 1	INT: mux CELL.IMUX_BSCAN_TDO1 bit 5	INT: mux CELL.IMUX_BSCAN_TDO1 bit 4	-
B4	-	-	-	-	-	-	MISC_NW: IO_OSTD bit 0	INT: mux CELL.LONG_H[1] bit 3	INT: mux CELL.LONG_H[1] bit 1	INT: mux CELL.LONG_H[1] bit 0	INT: mux CELL.LONG_H[1] bit 2	INT: mux CELL.LONG_H[0] bit 0	INT: mux CELL.LONG_H[0] bit 1	INT: mux CELL.LONG_H[0] bit 2	INT: mux CELL.LONG_H[0] bit 3	-	-	-	-	INT: mux CELL.LONG_IO_V[0] bit 2	PULLUP_DEC_H[3]: ! ENABLE	PULLUP_DEC_H[2]: ! ENABLE	INT: mux CELL.IMUX_BSCAN_TDO1 bit 0	INT: mux CELL.IMUX_BSCAN_TDO1 bit 3	INT: mux CELL.IMUX_BSCAN_TDO1 bit 2	INT: mux CELL.LONG_IO_H[0] bit 1	-
B3	-	-	-	-	-	-	INT: mux CELL.IMUX_BUFG_V bit 0	INT: mux CELL.LONG_H[2] bit 1	INT: mux CELL.LONG_H[2] bit 0	-	INT: mux CELL.LONG_IO_V[2] bit 3	INT: mux CELL.LONG_IO_V[2] bit 1	INT: mux CELL.LONG_IO_V[2] bit 0	INT: mux CELL.LONG_IO_V[2] bit 2	INT: mux CELL.LONG_IO_V[0] bit 0	INT: mux CELL.LONG_IO_V[0] bit 1	INT: mux CELL.LONG_IO_V[0] bit 3	-	-	INT: mux CELL.LONG_IO_H[2] bit 1	INT: mux CELL.LONG_IO_H[2] bit 0	-	INT: mux CELL.LONG_IO_H[0] bit 0	INT: mux CELL.IMUX_BSCAN_TDO2 bit 4	INT: mux CELL.IMUX_BSCAN_TDO2 bit 3	INT: mux CELL.IMUX_BSCAN_TDO2 bit 0	-
B2	-	-	-	INT: mux CELL.IMUX_BUFG_V bit 4	INT: mux CELL.IMUX_BUFG_V bit 3	INT: mux CELL.IMUX_BUFG_V bit 2	INT: mux CELL.IMUX_BUFG_V bit 1	INT: mux CELL.IMUX_BUFG_V bit 5	-	BUFG_V: ! CLK_EN	PULLUP_DEC_V[3]: ! ENABLE	-	-	-	-	PULLUP_DEC_V[1]: ! ENABLE	PULLUP_DEC_V[2]: ! ENABLE	PULLUP_DEC_V[0]: ! ENABLE	-	-	-	-	-	INT: mux CELL.IMUX_BSCAN_TDO2 bit 2	INT: mux CELL.IMUX_BSCAN_TDO2 bit 1	INT: mux CELL.IMUX_BSCAN_TDO2 bit 5	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tile CNR_SE

Cells: 1

Switchbox INT

xc4000xv CNR_SE switchbox INT permanent buffers
Destination	Source
BUFGE_H	OUT_BUFGE_H
BUFGE_V[0]	OUT_BUFGE_V

xc4000xv CNR_SE switchbox INT programmable buffers
Destination	Source	Bit
LONG_H[3]	SINGLE_V[4]	!MAIN[24][6]
LONG_H[4]	SINGLE_V[5]	!MAIN[19][9]
LONG_H[5]	SINGLE_V[6]	!MAIN[18][10]
LONG_V[0]	SINGLE_H_E[1]	!MAIN[18][9]
LONG_V[1]	SINGLE_H_E[2]	!MAIN[39][12]
LONG_V[2]	SINGLE_H_E[3]	!MAIN[19][10]
LONG_V[3]	SINGLE_H[4]	!MAIN[15][9]
LONG_V[4]	SINGLE_H[5]	!MAIN[17][9]
LONG_V[5]	SINGLE_H[6]	!MAIN[36][12]
LONG_V[6]	SINGLE_H_E[0]	!MAIN[44][11]
LONG_V[7]	SINGLE_H_E[3]	!MAIN[43][11]
LONG_V[8]	SINGLE_H_E[4]	!MAIN[49][11]
LONG_V[9]	SINGLE_H_E[7]	!MAIN[50][11]

xc4000xv CNR_SE switchbox INT pass gates
Destination	Source	Bit
SINGLE_H[0]	DEC_V[0]	!MAIN[10][9]
SINGLE_H[0]	OUT_IO_WE_I2_S1	!MAIN[24][10]
SINGLE_H[1]	LONG_IO_V[0]	!MAIN[16][10]
SINGLE_H[1]	OUT_STARTUP_Q3	!MAIN[20][10]
SINGLE_H[2]	LONG_IO_V[1]	!MAIN[16][9]
SINGLE_H[2]	OUT_STARTUP_Q1Q4	!MAIN[5][11]
SINGLE_H[3]	DEC_V[1]	!MAIN[8][13]
SINGLE_H[3]	OUT_IO_WE_I1_S1	!MAIN[11][9]
SINGLE_H[4]	LONG_V[3]	!MAIN[36][8]
SINGLE_H[4]	DEC_V[2]	!MAIN[8][9]
SINGLE_H[4]	OUT_IO_WE_I2_S1	!MAIN[23][10]
SINGLE_H[5]	LONG_V[4]	!MAIN[29][8]
SINGLE_H[5]	LONG_IO_V[2]	!MAIN[9][9]
SINGLE_H[5]	OUT_STARTUP_Q3	!MAIN[22][10]
SINGLE_H[6]	LONG_V[5]	!MAIN[35][13]
SINGLE_H[6]	LONG_IO_V[3]	!MAIN[15][10]
SINGLE_H[6]	OUT_STARTUP_Q1Q4	!MAIN[7][11]
SINGLE_H[7]	DEC_V[3]	!MAIN[5][10]
SINGLE_H[7]	OUT_IO_WE_I1_S1	!MAIN[6][10]
SINGLE_H_E[0]	LONG_V[6]	!MAIN[47][11]
SINGLE_H_E[1]	LONG_V[0]	!MAIN[33][9]
SINGLE_H_E[2]	LONG_V[1]	!MAIN[41][13]
SINGLE_H_E[3]	LONG_V[2]	!MAIN[35][10]
SINGLE_H_E[3]	LONG_V[7]	!MAIN[42][11]
SINGLE_H_E[4]	LONG_V[8]	!MAIN[48][8]
SINGLE_H_E[7]	LONG_V[9]	!MAIN[49][8]
SINGLE_V[0]	TIE_0	!MAIN[27][10]
SINGLE_V[0]	DEC_H[3]	!MAIN[14][4]
SINGLE_V[0]	OUT_IO_SN_I2_E1	!MAIN[27][5]
SINGLE_V[1]	LONG_IO_H[0]	!MAIN[18][4]
SINGLE_V[1]	OUT_STARTUP_DONEIN	!MAIN[28][6]
SINGLE_V[2]	LONG_IO_H[1]	!MAIN[19][4]
SINGLE_V[2]	OUT_STARTUP_Q2	!MAIN[12][6]
SINGLE_V[3]	DEC_H[2]	!MAIN[37][6]
SINGLE_V[3]	OUT_IO_SN_I1_E1	!MAIN[31][4]
SINGLE_V[4]	LONG_H[3]	!MAIN[27][11]
SINGLE_V[4]	DEC_H[1]	!MAIN[40][6]
SINGLE_V[4]	OUT_IO_SN_I2_E1	!MAIN[41][6]
SINGLE_V[5]	LONG_H[4]	!MAIN[41][9]
SINGLE_V[5]	LONG_IO_H[2]	!MAIN[29][4]
SINGLE_V[5]	OUT_STARTUP_DONEIN	!MAIN[28][4]
SINGLE_V[6]	LONG_H[5]	!MAIN[41][11]
SINGLE_V[6]	LONG_IO_H[3]	!MAIN[10][5]
SINGLE_V[6]	OUT_STARTUP_Q2	!MAIN[11][6]
SINGLE_V[7]	TIE_0	!MAIN[27][13]
SINGLE_V[7]	DEC_H[0]	!MAIN[35][4]
SINGLE_V[7]	OUT_IO_SN_I1_E1	!MAIN[37][4]
DOUBLE_H0[0]	OUT_STARTUP_Q1Q4	!MAIN[6][11]
DOUBLE_H0[1]	OUT_IO_WE_I2_S1	!MAIN[25][10]
DOUBLE_H1[0]	OUT_IO_WE_I1_S1	!MAIN[12][9]
DOUBLE_H1[1]	OUT_STARTUP_Q3	!MAIN[21][10]
DOUBLE_V0[0]	OUT_IO_SN_I1_E1	!MAIN[13][4]
DOUBLE_V0[1]	OUT_STARTUP_DONEIN	!MAIN[30][4]
DOUBLE_V1[0]	OUT_STARTUP_Q2	!MAIN[13][6]
DOUBLE_V1[1]	OUT_IO_SN_I2_E1	!MAIN[39][6]
DOUBLE_IO_S1[0]	DBUF_IO_V[1]	!MAIN[10][10]
DOUBLE_IO_S1[0]	GCLK[4]	!MAIN[44][2]
DOUBLE_IO_S1[1]	DBUF_IO_V[1]	!MAIN[7][10]
DOUBLE_IO_S1[1]	LONG_V[8]	!MAIN[49][3]
DOUBLE_IO_S1[2]	DBUF_IO_V[1]	!MAIN[9][10]
DOUBLE_IO_S1[2]	LONG_V[7]	!MAIN[50][0]
DOUBLE_IO_S1[3]	DBUF_IO_V[1]	!MAIN[8][10]
DOUBLE_IO_S1[3]	GCLK[7]	!MAIN[42][2]
DOUBLE_IO_S2[0]	DBUF_IO_H[0]	!MAIN[32][1]
DOUBLE_IO_S2[0]	LONG_V[9]	!MAIN[50][2]
DOUBLE_IO_S2[1]	DBUF_IO_H[0]	!MAIN[33][1]
DOUBLE_IO_S2[1]	GCLK[5]	!MAIN[43][2]
DOUBLE_IO_S2[2]	DBUF_IO_H[0]	!MAIN[34][1]
DOUBLE_IO_S2[2]	GCLK[6]	!MAIN[42][0]
DOUBLE_IO_S2[3]	DBUF_IO_H[0]	!MAIN[35][1]
DOUBLE_IO_S2[3]	LONG_V[6]	!MAIN[48][2]
DOUBLE_IO_E0[0]	DBUF_IO_V[0]	!MAIN[14][9]
DOUBLE_IO_E0[1]	DBUF_IO_V[0]	!MAIN[13][9]
DOUBLE_IO_E0[2]	DBUF_IO_V[0]	!MAIN[11][10]
DOUBLE_IO_E0[3]	DBUF_IO_V[0]	!MAIN[12][10]
DOUBLE_IO_E1[0]	DBUF_IO_H[1]	!MAIN[23][2]
DOUBLE_IO_E1[1]	DBUF_IO_H[1]	!MAIN[21][2]
DOUBLE_IO_E1[2]	DBUF_IO_H[1]	!MAIN[22][2]
DOUBLE_IO_E1[3]	DBUF_IO_H[1]	!MAIN[23][1]
QUAD_H0[0]	QBUF[0]	!MAIN[45][14]
QUAD_H0[1]	QBUF[1]	!MAIN[42][13]
QUAD_H0[1]	OUT_IO_WE_I1_S1	!MAIN[17][15]
QUAD_H0[2]	QBUF[2]	!MAIN[51][14]
QUAD_H0[2]	OUT_IO_WE_I2_S1	!MAIN[21][14]
QUAD_H1[0]	DEC_V[3]	!MAIN[5][14]
QUAD_H1[1]	DEC_V[2]	!MAIN[5][15]
QUAD_H1[2]	DEC_V[1]	!MAIN[16][14]
QUAD_H3[0]	OUT_IO_WE_I2_S1	!MAIN[19][14]
QUAD_H3[2]	OUT_IO_WE_I1_S1	!MAIN[16][15]
QUAD_H4[0]	QBUF[0]	!MAIN[44][14]
QUAD_H4[1]	QBUF[1]	!MAIN[44][13]
QUAD_H4[2]	QBUF[2]	!MAIN[50][14]
QUAD_V0[0]	QBUF[0]	!MAIN[46][14]
QUAD_V0[1]	QBUF[1]	!MAIN[42][14]
QUAD_V0[1]	OUT_IO_SN_I1_E1	!MAIN[43][0]
QUAD_V0[2]	QBUF[2]	!MAIN[51][15]
QUAD_V0[2]	OUT_IO_SN_I2_E1	!MAIN[42][5]
QUAD_V3[0]	DEC_H[2]	!MAIN[46][0]
QUAD_V3[0]	OUT_IO_SN_I2_E1	!MAIN[44][5]
QUAD_V3[1]	DEC_H[1]	!MAIN[45][2]
QUAD_V3[2]	DEC_H[0]	!MAIN[50][5]
QUAD_V3[2]	OUT_IO_SN_I1_E1	!MAIN[49][4]
QUAD_V4[0]	QBUF[0]	!MAIN[43][14]
QUAD_V4[1]	QBUF[1]	!MAIN[43][13]
QUAD_V4[2]	QBUF[2]	!MAIN[49][14]

xc4000xv CNR_SE switchbox INT bidirectional pass gates
Side A	Side B	Bit
SINGLE_H[0]	SINGLE_H_E[0]	!MAIN[29][10]
SINGLE_H[0]	SINGLE_V[0]	!MAIN[28][9]
SINGLE_H[0]	SINGLE_V_S[0]	!MAIN[31][8]
SINGLE_H[0]	DOUBLE_IO_S1[0]	!MAIN[17][13]
SINGLE_H[0]	DOUBLE_IO_E0[0]	!MAIN[13][10]
SINGLE_H[1]	SINGLE_H_E[1]	!MAIN[31][9]
SINGLE_H[1]	SINGLE_V[1]	!MAIN[30][9]
SINGLE_H[1]	SINGLE_V_S[1]	!MAIN[30][8]
SINGLE_H[1]	DOUBLE_IO_E1[0]	!MAIN[15][13]
SINGLE_H[2]	SINGLE_H_E[2]	!MAIN[33][12]
SINGLE_H[2]	SINGLE_V[2]	!MAIN[32][12]
SINGLE_H[2]	SINGLE_V_S[2]	!MAIN[34][12]
SINGLE_H[2]	DOUBLE_IO_S1[1]	!MAIN[0][13]
SINGLE_H[2]	DOUBLE_IO_E0[1]	!MAIN[4][13]
SINGLE_H[3]	SINGLE_H_E[3]	!MAIN[32][11]
SINGLE_H[3]	SINGLE_V[3]	!MAIN[29][11]
SINGLE_H[3]	SINGLE_V_S[3]	!MAIN[31][11]
SINGLE_H[3]	DOUBLE_IO_E1[1]	!MAIN[3][9]
SINGLE_H[4]	SINGLE_H_E[4]	!MAIN[37][10]
SINGLE_H[4]	SINGLE_V[4]	!MAIN[40][10]
SINGLE_H[4]	SINGLE_V_S[4]	!MAIN[36][10]
SINGLE_H[4]	DOUBLE_IO_S1[2]	!MAIN[1][10]
SINGLE_H[4]	DOUBLE_IO_E0[2]	!MAIN[3][11]
SINGLE_H[5]	SINGLE_H_E[5]	!MAIN[36][9]
SINGLE_H[5]	SINGLE_V[5]	!MAIN[37][8]
SINGLE_H[5]	SINGLE_V_S[5]	!MAIN[38][9]
SINGLE_H[5]	DOUBLE_IO_E1[2]	!MAIN[2][9]
SINGLE_H[6]	SINGLE_H_E[6]	!MAIN[36][11]
SINGLE_H[6]	SINGLE_V[6]	!MAIN[37][12]
SINGLE_H[6]	SINGLE_V_S[6]	!MAIN[37][11]
SINGLE_H[6]	DOUBLE_IO_S1[3]	!MAIN[18][13]
SINGLE_H[6]	DOUBLE_IO_E0[3]	!MAIN[24][13]
SINGLE_H[7]	SINGLE_H_E[7]	!MAIN[39][13]
SINGLE_H[7]	SINGLE_V[7]	!MAIN[36][13]
SINGLE_H[7]	SINGLE_V_S[7]	!MAIN[38][12]
SINGLE_H[7]	DOUBLE_IO_E1[3]	!MAIN[22][13]
SINGLE_H_E[0]	SINGLE_V[0]	!MAIN[27][9]
SINGLE_H_E[0]	SINGLE_V_S[0]	!MAIN[29][9]
SINGLE_H_E[0]	QUAD_V1[0]	!MAIN[48][11]
SINGLE_H_E[1]	SINGLE_V[1]	!MAIN[31][10]
SINGLE_H_E[1]	SINGLE_V_S[1]	!MAIN[32][9]
SINGLE_H_E[1]	QUAD_V3[0]	!MAIN[46][11]
SINGLE_H_E[2]	SINGLE_V[2]	!MAIN[32][13]
SINGLE_H_E[2]	SINGLE_V_S[2]	!MAIN[33][13]
SINGLE_H_E[2]	QUAD_V2[0]	!MAIN[42][12]
SINGLE_H_E[3]	SINGLE_V[3]	!MAIN[33][11]
SINGLE_H_E[3]	SINGLE_V_S[3]	!MAIN[34][11]
SINGLE_H_E[3]	QUAD_V0[1]	!MAIN[50][12]
SINGLE_H_E[4]	SINGLE_V[4]	!MAIN[40][12]
SINGLE_H_E[4]	SINGLE_V_S[4]	!MAIN[38][10]
SINGLE_H_E[4]	QUAD_V0[2]	!MAIN[45][11]
SINGLE_H_E[5]	SINGLE_V[5]	!MAIN[37][9]
SINGLE_H_E[5]	SINGLE_V_S[5]	!MAIN[39][9]
SINGLE_H_E[5]	QUAD_V1[1]	!MAIN[47][12]
SINGLE_H_E[6]	SINGLE_V[6]	!MAIN[35][11]
SINGLE_H_E[6]	SINGLE_V_S[6]	!MAIN[38][11]
SINGLE_H_E[6]	QUAD_V3[2]	!MAIN[48][12]
SINGLE_H_E[7]	SINGLE_V[7]	!MAIN[38][13]
SINGLE_H_E[7]	SINGLE_V_S[7]	!MAIN[40][13]
SINGLE_H_E[7]	QUAD_V2[2]	!MAIN[43][12]
SINGLE_V[0]	SINGLE_V_S[0]	!MAIN[30][10]
SINGLE_V[0]	DOUBLE_IO_S1[0]	!MAIN[24][1]
SINGLE_V[1]	SINGLE_V_S[1]	!MAIN[32][8]
SINGLE_V[1]	DOUBLE_IO_S2[0]	!MAIN[28][2]
SINGLE_V[1]	DOUBLE_IO_E1[0]	!MAIN[24][2]
SINGLE_V[2]	SINGLE_V_S[2]	!MAIN[31][13]
SINGLE_V[2]	DOUBLE_IO_S1[1]	!MAIN[30][2]
SINGLE_V[3]	SINGLE_V_S[3]	!MAIN[28][11]
SINGLE_V[3]	DOUBLE_IO_S2[1]	!MAIN[32][2]
SINGLE_V[3]	DOUBLE_IO_E1[1]	!MAIN[25][1]
SINGLE_V[4]	SINGLE_V_S[4]	!MAIN[39][10]
SINGLE_V[4]	DOUBLE_IO_S1[2]	!MAIN[27][1]
SINGLE_V[5]	SINGLE_V_S[5]	!MAIN[40][9]
SINGLE_V[5]	DOUBLE_IO_S2[2]	!MAIN[34][2]
SINGLE_V[5]	DOUBLE_IO_E1[2]	!MAIN[29][1]
SINGLE_V[6]	SINGLE_V_S[6]	!MAIN[39][11]
SINGLE_V[6]	DOUBLE_IO_S1[3]	!MAIN[38][1]
SINGLE_V[7]	SINGLE_V_S[7]	!MAIN[37][13]
SINGLE_V[7]	DOUBLE_IO_S2[3]	!MAIN[38][2]
SINGLE_V[7]	DOUBLE_IO_E1[3]	!MAIN[36][1]
SINGLE_V_S[0]	QUAD_H2[0]	!MAIN[34][15]
SINGLE_V_S[1]	QUAD_H0[0]	!MAIN[35][14]
SINGLE_V_S[2]	QUAD_H2[1]	!MAIN[35][15]
SINGLE_V_S[3]	QUAD_H1[1]	!MAIN[36][14]
SINGLE_V_S[4]	QUAD_H0[1]	!MAIN[38][15]
SINGLE_V_S[5]	QUAD_H3[2]	!MAIN[39][14]
SINGLE_V_S[6]	QUAD_H2[2]	!MAIN[37][15]
SINGLE_V_S[7]	QUAD_H1[2]	!MAIN[37][14]
DOUBLE_H0[0]	DOUBLE_H2[0]	!MAIN[30][13]
DOUBLE_H0[0]	DOUBLE_V0[0]	!MAIN[28][13]
DOUBLE_H0[0]	DOUBLE_V2[0]	!MAIN[29][13]
DOUBLE_H0[0]	DOUBLE_IO_S1[1]	!MAIN[1][13]
DOUBLE_H0[0]	DOUBLE_IO_E0[1]	!MAIN[3][13]
DOUBLE_H0[0]	DOUBLE_IO_E1[1]	!MAIN[3][10]
DOUBLE_H0[1]	DOUBLE_H2[1]	!MAIN[34][10]
DOUBLE_H0[1]	DOUBLE_V0[1]	!MAIN[33][10]
DOUBLE_H0[1]	DOUBLE_V2[1]	!MAIN[34][8]
DOUBLE_H0[1]	DOUBLE_IO_S1[2]	!MAIN[2][10]
DOUBLE_H0[1]	DOUBLE_IO_E0[2]	!MAIN[2][11]
DOUBLE_H0[1]	DOUBLE_IO_E1[2]	!MAIN[4][10]
DOUBLE_H1[0]	DOUBLE_IO_S1[0]	!MAIN[16][13]
DOUBLE_H1[0]	DOUBLE_IO_E0[0]	!MAIN[14][10]
DOUBLE_H1[0]	DOUBLE_IO_E1[0]	!MAIN[11][13]
DOUBLE_H1[1]	DOUBLE_IO_S1[3]	!MAIN[19][13]
DOUBLE_H1[1]	DOUBLE_IO_E0[3]	!MAIN[23][13]
DOUBLE_H1[1]	DOUBLE_IO_E1[3]	!MAIN[20][13]
DOUBLE_H1[1]	QUAD_V3[1]	!MAIN[45][12]
DOUBLE_H2[0]	DOUBLE_V0[0]	!MAIN[30][11]
DOUBLE_H2[0]	DOUBLE_V2[0]	!MAIN[30][12]
DOUBLE_H2[0]	QUAD_V0[0]	!MAIN[44][12]
DOUBLE_H2[1]	DOUBLE_V0[1]	!MAIN[34][9]
DOUBLE_H2[1]	DOUBLE_V2[1]	!MAIN[35][9]
DOUBLE_V0[0]	DOUBLE_V2[0]	!MAIN[28][12]
DOUBLE_V0[0]	DOUBLE_IO_S1[1]	!MAIN[27][3]
DOUBLE_V0[0]	DOUBLE_IO_S2[1]	!MAIN[31][2]
DOUBLE_V0[0]	DOUBLE_IO_E1[1]	!MAIN[29][2]
DOUBLE_V0[1]	DOUBLE_V2[1]	!MAIN[35][8]
DOUBLE_V0[1]	DOUBLE_IO_S1[2]	!MAIN[30][1]
DOUBLE_V0[1]	DOUBLE_IO_S2[2]	!MAIN[33][2]
DOUBLE_V0[1]	DOUBLE_IO_E1[2]	!MAIN[28][1]
DOUBLE_V1[0]	DOUBLE_IO_S1[0]	!MAIN[25][3]
DOUBLE_V1[0]	DOUBLE_IO_S2[0]	!MAIN[27][2]
DOUBLE_V1[0]	DOUBLE_IO_E1[0]	!MAIN[25][2]
DOUBLE_V1[1]	DOUBLE_IO_S1[3]	!MAIN[35][2]
DOUBLE_V1[1]	DOUBLE_IO_S2[3]	!MAIN[37][2]
DOUBLE_V1[1]	DOUBLE_IO_E1[3]	!MAIN[37][1]
DOUBLE_V1[1]	QUAD_H0[2]	!MAIN[38][14]
DOUBLE_V2[0]	QUAD_H3[0]	!MAIN[34][14]
DOUBLE_IO_S1[0]	DOUBLE_IO_E0[0]	!MAIN[10][13]
DOUBLE_IO_S1[0]	QUAD_V2[0]	!MAIN[46][1]
DOUBLE_IO_S1[1]	DOUBLE_IO_E0[1]	!MAIN[2][13]
DOUBLE_IO_S1[1]	QUAD_V1[1]	!MAIN[47][2]
DOUBLE_IO_S1[2]	DOUBLE_IO_E0[2]	!MAIN[1][11]
DOUBLE_IO_S1[2]	QUAD_V3[1]	!MAIN[45][1]
DOUBLE_IO_S1[3]	DOUBLE_IO_E0[3]	!MAIN[21][13]
DOUBLE_IO_S1[3]	QUAD_V2[2]	!MAIN[43][1]
DOUBLE_IO_S2[0]	DOUBLE_IO_E1[0]	!MAIN[24][3]
DOUBLE_IO_S2[0]	QUAD_V1[0]	!MAIN[46][2]
DOUBLE_IO_S2[1]	DOUBLE_IO_E1[1]	!MAIN[28][3]
DOUBLE_IO_S2[1]	QUAD_V3[0]	!MAIN[51][2]
DOUBLE_IO_S2[2]	DOUBLE_IO_E1[2]	!MAIN[31][1]
DOUBLE_IO_S2[2]	QUAD_V2[1]	!MAIN[44][0]
DOUBLE_IO_S2[3]	DOUBLE_IO_E1[3]	!MAIN[36][2]
DOUBLE_IO_S2[3]	QUAD_V1[2]	!MAIN[44][1]
DOUBLE_IO_E0[0]	QUAD_H3[0]	!MAIN[18][14]
DOUBLE_IO_E0[1]	QUAD_H1[0]	!MAIN[4][14]
DOUBLE_IO_E0[2]	QUAD_H1[1]	!MAIN[4][15]
DOUBLE_IO_E0[3]	QUAD_H2[2]	!MAIN[19][15]
DOUBLE_IO_E1[0]	QUAD_H2[0]	!MAIN[23][15]
DOUBLE_IO_E1[1]	QUAD_H2[1]	!MAIN[21][15]
DOUBLE_IO_E1[2]	QUAD_H3[2]	!MAIN[2][15]
DOUBLE_IO_E1[3]	QUAD_H1[2]	!MAIN[17][14]
QUAD_H0[0]	QUAD_H4[0]	!MAIN[43][15]
QUAD_H0[0]	QUAD_V0[0]	!MAIN[44][15]
QUAD_H0[0]	QUAD_V4[0]	!MAIN[40][15]
QUAD_H0[0]	LONG_IO_V[3]	!MAIN[2][14]
QUAD_H0[1]	QUAD_H4[1]	!MAIN[49][12]
QUAD_H0[1]	QUAD_V0[1]	!MAIN[47][13]
QUAD_H0[1]	QUAD_V4[1]	!MAIN[48][13]
QUAD_H0[1]	LONG_IO_V[2]	!MAIN[18][15]
QUAD_H0[2]	QUAD_H4[2]	!MAIN[49][15]
QUAD_H0[2]	QUAD_V0[2]	!MAIN[50][15]
QUAD_H0[2]	QUAD_V4[2]	!MAIN[46][15]
QUAD_H0[2]	LONG_IO_V[1]	!MAIN[20][14]
QUAD_H4[0]	QUAD_V0[0]	!MAIN[42][15]
QUAD_H4[0]	QUAD_V4[0]	!MAIN[41][15]
QUAD_H4[1]	QUAD_V0[1]	!MAIN[50][13]
QUAD_H4[1]	QUAD_V4[1]	!MAIN[51][13]
QUAD_H4[2]	QUAD_V0[2]	!MAIN[48][15]
QUAD_H4[2]	QUAD_V4[2]	!MAIN[47][15]
QUAD_V0[0]	QUAD_V4[0]	!MAIN[39][15]
QUAD_V0[0]	LONG_IO_H[0]	!MAIN[50][3]
QUAD_V0[1]	QUAD_V4[1]	!MAIN[49][13]
QUAD_V0[1]	LONG_IO_H[1]	!MAIN[51][4]
QUAD_V0[2]	QUAD_V4[2]	!MAIN[45][15]
QUAD_V0[2]	LONG_IO_H[3]	!MAIN[50][4]

xc4000xv CNR_SE switchbox INT muxes DBUF_IO_H[0]
Bits				Destination
MAIN[7][4]	MAIN[11][4]	MAIN[8][4]	MAIN[9][4]	DBUF_IO_H[0]
				Source
0	0	1	1	DOUBLE_IO_E1[0]
0	1	0	1	DOUBLE_IO_E1[2]
0	1	1	0	DOUBLE_IO_E1[3]
1	1	1	1	DOUBLE_IO_E1[1]

xc4000xv CNR_SE switchbox INT muxes DBUF_IO_H[1]
Bits				Destination
MAIN[39][2]	MAIN[40][2]	MAIN[39][1]	MAIN[40][1]	DBUF_IO_H[1]
				Source
0	0	1	1	DOUBLE_IO_S2[1]
0	1	0	1	DOUBLE_IO_S2[2]
0	1	1	0	DOUBLE_IO_S2[3]
1	1	1	1	DOUBLE_IO_S2[0]

xc4000xv CNR_SE switchbox INT muxes DBUF_IO_V[0]
Bits				Destination
MAIN[4][11]	MAIN[5][13]	MAIN[7][13]	MAIN[6][13]	DBUF_IO_V[0]
				Source
0	0	1	1	DOUBLE_IO_S1[1]
0	1	0	1	DOUBLE_IO_S1[2]
0	1	1	0	DOUBLE_IO_S1[3]
1	1	1	1	DOUBLE_IO_S1[0]

xc4000xv CNR_SE switchbox INT muxes DBUF_IO_V[1]
Bits				Destination
MAIN[9][13]	MAIN[13][13]	MAIN[12][13]	MAIN[14][13]	DBUF_IO_V[1]
				Source
0	0	1	1	DOUBLE_IO_E0[0]
0	1	0	1	DOUBLE_IO_E0[1]
0	1	1	0	DOUBLE_IO_E0[3]
1	1	1	1	DOUBLE_IO_E0[2]

xc4000xv CNR_SE switchbox INT muxes QBUF[0]
Bits		Destination
MAIN[40][14]	MAIN[41][14]	QBUF[0]
		Source
0	0	QUAD_V4[0]
0	1	QUAD_V0[0]
1	0	QUAD_H0[0]
1	1	QUAD_H4[0]

xc4000xv CNR_SE switchbox INT muxes QBUF[1]
Bits		Destination
MAIN[45][13]	MAIN[46][13]	QBUF[1]
		Source
0	0	QUAD_V4[1]
0	1	QUAD_V0[1]
1	0	QUAD_H0[1]
1	1	QUAD_H4[1]

xc4000xv CNR_SE switchbox INT muxes QBUF[2]
Bits		Destination
MAIN[47][14]	MAIN[48][14]	QBUF[2]
		Source
0	0	QUAD_V4[2]
0	1	QUAD_V0[2]
1	0	QUAD_H0[2]
1	1	QUAD_H4[2]

xc4000xv CNR_SE switchbox INT muxes LONG_H[3]
Bits		Destination
MAIN[21][5]	MAIN[22][6]	LONG_H[3]
		Source
0	0	LONG_IO_V[1]
0	1	DEC_V[2]
1	1	off

xc4000xv CNR_SE switchbox INT muxes LONG_H[4]
Bits				Destination
MAIN[10][6]	MAIN[6][6]	MAIN[9][6]	MAIN[7][6]	LONG_H[4]
				Source
0	0	0	1	LONG_IO_V[2]
0	0	1	0	DEC_V[1]
0	1	1	1	OUT_STARTUP_Q3
1	1	1	1	off

xc4000xv CNR_SE switchbox INT muxes LONG_H[5]
Bits				Destination
MAIN[18][5]	MAIN[19][5]	MAIN[21][6]	MAIN[20][5]	LONG_H[5]
				Source
0	0	0	1	LONG_IO_V[3]
0	0	1	0	DEC_V[0]
0	1	1	1	OUT_STARTUP_Q3
1	1	1	1	off

xc4000xv CNR_SE switchbox INT muxes LONG_V[0]
Bits				Destination
MAIN[20][4]	MAIN[22][4]	MAIN[24][4]	MAIN[25][4]	LONG_V[0]
				Source
0	0	0	1	LONG_IO_H[0]
0	0	1	0	DEC_H[0]
0	1	1	1	OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000xv CNR_SE switchbox INT muxes LONG_V[1]
Bits				Destination
MAIN[39][5]	MAIN[38][6]	MAIN[38][5]	MAIN[40][5]	LONG_V[1]
				Source
0	0	0	1	LONG_IO_H[1]
0	0	1	0	DEC_H[1]
0	1	1	1	OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000xv CNR_SE switchbox INT muxes LONG_V[2]
Bits				Destination
MAIN[29][5]	MAIN[25][6]	MAIN[28][5]	MAIN[27][6]	LONG_V[2]
				Source
0	0	0	1	LONG_IO_H[2]
0	0	1	0	DEC_H[2]
0	1	1	1	OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000xv CNR_SE switchbox INT muxes LONG_V[3]
Bits				Destination
MAIN[36][5]	MAIN[35][6]	MAIN[36][6]	MAIN[37][5]	LONG_V[3]
				Source
0	0	0	1	LONG_IO_H[1]
0	0	1	0	DEC_H[1]
0	1	1	1	OUT_STARTUP_DONEIN
1	1	1	1	off

xc4000xv CNR_SE switchbox INT muxes LONG_V[4]
Bits				Destination
MAIN[25][5]	MAIN[22][5]	MAIN[23][5]	MAIN[24][5]	LONG_V[4]
				Source
0	0	0	1	LONG_IO_H[2]
0	0	1	0	DEC_H[2]
0	1	1	1	OUT_STARTUP_DONEIN
1	1	1	1	off

xc4000xv CNR_SE switchbox INT muxes LONG_V[5]
Bits				Destination
MAIN[36][4]	MAIN[32][4]	MAIN[34][4]	MAIN[33][4]	LONG_V[5]
				Source
0	0	0	1	LONG_IO_H[3]
0	0	1	0	DEC_H[3]
0	1	1	1	OUT_STARTUP_DONEIN
1	1	1	1	off

xc4000xv CNR_SE switchbox INT muxes LONG_V[6]
Bits	Destination
MAIN[47][5]	LONG_V[6]
	Source
0	LONG_IO_H[0]
1	off

xc4000xv CNR_SE switchbox INT muxes LONG_V[7]
Bits	Destination
MAIN[46][5]	LONG_V[7]
	Source
0	LONG_IO_H[1]
1	off

xc4000xv CNR_SE switchbox INT muxes LONG_V[8]
Bits	Destination
MAIN[47][6]	LONG_V[8]
	Source
0	LONG_IO_H[2]
1	off

xc4000xv CNR_SE switchbox INT muxes LONG_V[9]
Bits	Destination
MAIN[43][6]	LONG_V[9]
	Source
0	LONG_IO_H[3]
1	off

xc4000xv CNR_SE switchbox INT muxes LONG_IO_H[0]
Bits						Destination
MAIN[30][3]	MAIN[29][3]	MAIN[48][5]	MAIN[49][5]	MAIN[23][3]	MAIN[22][3]	LONG_IO_H[0]
						Source
0	0	1	1	1	1	LONG_V[0]
0	1	1	1	1	1	SINGLE_V[1]
1	1	0	0	1	1	LONG_V[6]
1	1	0	1	1	1	GCLK[4]
1	1	1	1	0	0	LONG_IO_V[2]
1	1	1	1	0	1	LONG_IO_V[0]
1	1	1	1	1	1	off

xc4000xv CNR_SE switchbox INT muxes LONG_IO_H[1]
Bits								Destination
MAIN[34][3]	MAIN[31][3]	MAIN[33][3]	MAIN[32][3]	MAIN[45][5]	MAIN[43][5]	MAIN[14][3]	MAIN[13][3]	LONG_IO_H[1]
								Source
0	0	0	1	1	1	1	1	LONG_V[1]
0	0	1	0	1	1	1	1	LONG_V[3]
0	1	1	1	1	1	1	1	SINGLE_V[2]
1	1	1	1	0	0	1	1	LONG_V[7]
1	1	1	1	0	1	1	1	GCLK[5]
1	1	1	1	1	1	0	0	LONG_IO_V[3]
1	1	1	1	1	1	0	1	LONG_IO_V[1]
1	1	1	1	1	1	1	1	off

xc4000xv CNR_SE switchbox INT muxes LONG_IO_H[2]
Bits								Destination
MAIN[37][3]	MAIN[35][3]	MAIN[39][3]	MAIN[38][3]	MAIN[48][6]	MAIN[49][6]	MAIN[19][3]	MAIN[20][3]	LONG_IO_H[2]
								Source
0	0	0	1	1	1	1	1	LONG_V[2]
0	0	1	0	1	1	1	1	LONG_V[4]
0	1	1	1	1	1	1	1	SINGLE_V[5]
1	1	1	1	0	0	1	1	LONG_V[8]
1	1	1	1	0	1	1	1	GCLK[6]
1	1	1	1	1	1	0	0	LONG_IO_V[0]
1	1	1	1	1	1	0	1	LONG_IO_V[2]
1	1	1	1	1	1	1	1	off

xc4000xv CNR_SE switchbox INT muxes LONG_IO_H[3]
Bits						Destination
MAIN[36][3]	MAIN[27][4]	MAIN[44][6]	MAIN[42][6]	MAIN[10][3]	MAIN[11][3]	LONG_IO_H[3]
						Source
0	0	1	1	1	1	LONG_V[5]
0	1	1	1	1	1	SINGLE_V[6]
1	1	0	0	1	1	LONG_V[9]
1	1	0	1	1	1	GCLK[7]
1	1	1	1	0	0	LONG_IO_V[1]
1	1	1	1	0	1	LONG_IO_V[3]
1	1	1	1	1	1	off

xc4000xv CNR_SE switchbox INT muxes LONG_IO_V[0]
Bits				Destination
MAIN[21][4]	MAIN[15][5]	MAIN[15][4]	MAIN[16][4]	LONG_IO_V[0]
				Source
0	0	0	1	LONG_IO_H[0]
0	0	1	0	LONG_IO_H[2]
0	1	1	1	SINGLE_H[1]
1	1	1	1	off

xc4000xv CNR_SE switchbox INT muxes LONG_IO_V[1]
Bits					Destination
MAIN[10][4]	MAIN[5][4]	MAIN[7][5]	MAIN[5][5]	MAIN[6][5]	LONG_IO_V[1]
					Source
0	0	0	1	1	LONG_H[3]
0	0	1	0	1	LONG_IO_H[1]
0	0	1	1	0	LONG_IO_H[3]
0	1	1	1	1	SINGLE_H[2]
1	1	1	1	1	off

xc4000xv CNR_SE switchbox INT muxes LONG_IO_V[2]
Bits					Destination
MAIN[23][4]	MAIN[4][5]	MAIN[16][5]	MAIN[14][5]	MAIN[13][5]	LONG_IO_V[2]
					Source
0	0	0	1	1	LONG_H[4]
0	0	1	0	1	LONG_IO_H[0]
0	0	1	1	0	LONG_IO_H[2]
0	1	1	1	1	SINGLE_H[5]
1	1	1	1	1	off

xc4000xv CNR_SE switchbox INT muxes LONG_IO_V[3]
Bits					Destination
MAIN[17][4]	MAIN[3][5]	MAIN[6][4]	MAIN[4][4]	MAIN[12][4]	LONG_IO_V[3]
					Source
0	0	0	1	1	LONG_H[5]
0	0	1	0	1	LONG_IO_H[1]
0	0	1	1	0	LONG_IO_H[3]
0	1	1	1	1	SINGLE_H[6]
1	1	1	1	1	off

xc4000xv CNR_SE switchbox INT muxes VCLK
Bits							Destination
MAIN[47][0]	MAIN[48][1]	MAIN[49][1]	MAIN[50][1]	MAIN[47][1]	MAIN[49][2]	MAIN[51][1]	VCLK
							Source
0	0	0	0	1	1	1	off
0	0	0	1	1	1	0	OUT_IO_SN_I1_E1
0	0	1	1	1	1	1	DOUBLE_IO_S1[1]
0	1	0	0	0	1	1	QUAD_V0[0]
0	1	0	0	1	0	1	LONG_IO_H[0]
0	1	0	1	0	1	0	LONG_IO_H[3]
0	1	0	1	1	0	0	LONG_IO_H[1]
0	1	1	1	0	1	1	DOUBLE_IO_S1[2]
0	1	1	1	1	0	1	DOUBLE_IO_S2[0]
1	1	0	0	1	1	1	ECLK_H
1	1	0	1	1	1	0	BUFGE_H
1	1	1	1	1	1	1	DOUBLE_IO_S2[3]

xc4000xv CNR_SE switchbox INT muxes ECLK_H
Bits							Destination
MAIN[42][3]	MAIN[43][3]	MAIN[44][3]	MAIN[45][4]	MAIN[42][4]	MAIN[44][4]	MAIN[43][4]	ECLK_H
							Source
0	0	1	1	0	0	1	LONG_IO_H[1]
0	0	1	1	0	1	0	GCLK[5]
0	0	1	1	1	1	1	SINGLE_V[3]
0	1	0	1	0	0	1	OUT_BUFGE_V
0	1	0	1	0	1	0	GCLK[6]
0	1	0	1	1	1	1	SINGLE_V[4]
0	1	1	0	0	0	1	LONG_IO_H[3]
0	1	1	0	0	1	0	GCLK[7]
0	1	1	0	1	1	1	SINGLE_V[5]
1	1	1	1	0	0	1	LONG_IO_H[0]
1	1	1	1	0	1	0	GCLK[4]
1	1	1	1	1	1	1	SINGLE_V[2]

xc4000xv CNR_SE switchbox INT muxes ECLK_V
Bits							Destination
MAIN[7][14]	MAIN[11][14]	MAIN[10][14]	MAIN[9][14]	MAIN[8][14]	MAIN[12][14]	MAIN[14][14]	ECLK_V
							Source
0	0	1	1	0	0	1	LONG_IO_H[3]
0	0	1	1	1	1	1	SINGLE_H[2]
0	1	0	1	0	0	1	LONG_IO_H[1]
0	1	0	1	1	1	1	SINGLE_H[3]
0	1	1	0	0	0	1	LONG_IO_H[0]
0	1	1	0	1	1	1	SINGLE_H[4]
0	1	1	1	0	1	0	OUT_BUFGE_H
1	1	1	1	0	0	1	DOUBLE_IO_E1[3]
1	1	1	1	1	1	1	SINGLE_H[5]

xc4000xv CNR_SE switchbox INT muxes IMUX_CLB_F4
Bits		Destination
MAIN[15][14]	MAIN[15][15]	IMUX_CLB_F4
		Source
0	1	LONG_V[7]
1	0	LONG_V[9]
1	1	GCLK[4]

xc4000xv CNR_SE switchbox INT muxes IMUX_CLB_G4
Bits		Destination
MAIN[13][15]	MAIN[13][14]	IMUX_CLB_G4
		Source
0	1	LONG_V[9]
1	0	GCLK[4]
1	1	LONG_V[6]

xc4000xv CNR_SE switchbox INT muxes IMUX_CLB_C4
Bits					Destination
MAIN[25][14]	MAIN[24][14]	MAIN[25][15]	MAIN[23][14]	MAIN[24][15]	IMUX_CLB_C4
					Source
0	1	1	1	1	LONG_V[0]
1	0	1	1	1	LONG_V[4]
1	1	0	1	1	LONG_V[6]
1	1	1	0	1	LONG_V[8]
1	1	1	1	0	GCLK[5]
1	1	1	1	1	off

xc4000xv CNR_SE switchbox INT muxes IMUX_STARTUP_CLK
Bits				Destination
MAIN[38][8]	MAIN[39][8]	MAIN[40][8]	MAIN[41][8]	IMUX_STARTUP_CLK
				Source
0	0	1	1	SINGLE_V[3]
0	1	0	1	SINGLE_V[4]
0	1	1	0	SINGLE_V[5]
1	1	1	1	SINGLE_V[2]

xc4000xv CNR_SE switchbox INT muxes IMUX_STARTUP_GSR
Bits						Destination
MAIN[30][6]	MAIN[29][6]	MAIN[34][6]	MAIN[32][6]	MAIN[31][6]	MAIN[33][6]	IMUX_STARTUP_GSR
						Source
0	0	0	1	1	1	SINGLE_H[2]
0	0	1	0	1	1	SINGLE_H[3]
0	0	1	1	1	0	LONG_V[4]
0	1	0	1	1	1	LONG_V[5]
0	1	1	0	1	1	DOUBLE_V1[1]
0	1	1	1	0	1	SINGLE_H[4]
0	1	1	1	1	0	LONG_V[3]
1	0	1	1	1	1	DOUBLE_V0[0]
1	1	1	1	1	1	SINGLE_H[5]

xc4000xv CNR_SE switchbox INT muxes IMUX_STARTUP_GTS
Bits						Destination
MAIN[31][5]	MAIN[32][5]	MAIN[33][5]	MAIN[34][5]	MAIN[35][5]	MAIN[30][5]	IMUX_STARTUP_GTS
						Source
0	0	1	1	1	0	LONG_H[3]
0	0	1	1	1	1	SINGLE_V[2]
0	1	0	1	1	1	SINGLE_V[3]
0	1	1	0	1	0	LONG_H[5]
0	1	1	0	1	1	SINGLE_V[4]
0	1	1	1	0	0	LONG_H[4]
0	1	1	1	0	1	SINGLE_V[5]
1	1	1	1	1	0	DOUBLE_H0[1]
1	1	1	1	1	1	DOUBLE_H1[0]

xc4000xv CNR_SE switchbox INT muxes IMUX_READCLK_I
Bits				Destination
MAIN[4][9]	MAIN[7][9]	MAIN[6][9]	MAIN[5][9]	IMUX_READCLK_I
				Source
0	0	1	1	SINGLE_H[2]
0	1	0	1	SINGLE_H[3]
0	1	1	0	SINGLE_H[4]
1	1	1	1	SINGLE_H[5]

xc4000xv CNR_SE switchbox INT muxes IMUX_BUFG_H
Bits							Destination
MAIN[21][3]	MAIN[22][1]	MAIN[26][1]	MAIN[21][1]	MAIN[26][3]	MAIN[26][2]	MAIN[20][2]	IMUX_BUFG_H
							Source
0	0	0	0	1	1	1	DOUBLE_IO_S1[2]
0	0	0	1	1	1	1	DOUBLE_IO_S1[0]
0	0	1	0	0	1	1	DOUBLE_IO_S1[3]
0	0	1	0	1	0	1	DOUBLE_IO_E1[3]
0	0	1	1	0	1	1	DOUBLE_IO_E1[1]
0	0	1	1	1	0	1	DOUBLE_IO_E1[0]
0	1	1	1	1	1	0	OUT_IO_CLKIN_E
0	1	1	1	1	1	1	off
1	0	1	0	1	1	1	DOUBLE_IO_S1[1]
1	0	1	1	1	1	1	DOUBLE_IO_E1[2]

xc4000xv CNR_SE switchbox INT muxes IMUX_BUFG_V
Bits						Destination
MAIN[17][6]	MAIN[16][6]	MAIN[18][6]	MAIN[20][6]	MAIN[19][6]	MAIN[15][6]	IMUX_BUFG_V
						Source
0	0	0	1	1	1	OCTAL_IO_E[7]
0	0	1	0	1	1	LONG_IO_H[0]
0	0	1	1	0	1	LONG_IO_V[0]
0	1	1	1	1	0	OUT_IO_CLKIN_S
0	1	1	1	1	1	off
1	0	1	1	1	1	OCTAL_IO_E[0]

Bels PULLUP

xc4000xv CNR_SE bel PULLUP pins
Pin	Direction	PULLUP_DEC_H[0]	PULLUP_DEC_H[1]	PULLUP_DEC_H[2]	PULLUP_DEC_H[3]	PULLUP_DEC_V[0]	PULLUP_DEC_V[1]	PULLUP_DEC_V[2]	PULLUP_DEC_V[3]
O	bidir	DEC_H[0]	DEC_H[1]	DEC_H[2]	DEC_H[3]	DEC_V[0]	DEC_V[1]	DEC_V[2]	DEC_V[3]

xc4000xv CNR_SE bel PULLUP attribute bits
Attribute	PULLUP_DEC_H[0]	PULLUP_DEC_H[1]	PULLUP_DEC_H[2]	PULLUP_DEC_H[3]	PULLUP_DEC_V[0]	PULLUP_DEC_V[1]	PULLUP_DEC_V[2]	PULLUP_DEC_V[3]
ENABLE	!MAIN[40][3]	!MAIN[38][4]	!MAIN[39][4]	!MAIN[40][4]	!MAIN[8][5]	!MAIN[11][5]	!MAIN[9][5]	!MAIN[12][5]

Bels BUFG

xc4000xv CNR_SE bel BUFG pins
Pin	Direction	BUFG_H	BUFG_V
I	in	IMUX_BUFG_H	IMUX_BUFG_V
O	out	BUFGLS[3]	BUFGLS[4]
O_BUFGE	out	OUT_BUFGE_H	OUT_BUFGE_V

xc4000xv CNR_SE bel BUFG attribute bits
Attribute	BUFG_H	BUFG_V
CLK_EN	!MAIN[2][1]	!MAIN[8][6]
ALT_PAD	!MAIN[15][1]	!MAIN[0][3]

Bels STARTUP

xc4000xv CNR_SE bel STARTUP pins
Pin	Direction	STARTUP
CLK	in	IMUX_STARTUP_CLK
GSR	in	IMUX_STARTUP_GSR invert by !MAIN[9][1]
GTS	in	IMUX_STARTUP_GTS invert by !MAIN[7][1]
DONEIN	out	OUT_STARTUP_DONEIN
Q1Q4	out	OUT_STARTUP_Q1Q4
Q2	out	OUT_STARTUP_Q2
Q3	out	OUT_STARTUP_Q3

xc4000xv CNR_SE bel STARTUP attribute bits
Attribute	STARTUP
GSR_ENABLE	!MAIN[8][1]
GTS_ENABLE	!MAIN[5][1]
CONFIG_RATE	[enum: CONFIG_RATE]
CRC	!MAIN[0][1]
DONE_TIMING	[enum: DONE_TIMING]
GTS_TIMING	[enum: GTS_GSR_TIMING]
GSR_TIMING	[enum: GTS_GSR_TIMING]
SYNC_TO_DONE	!MAIN[11][1]
MUX_CLK	[enum: STARTUP_MUX_CLK]
EXPRESS_MODE	!MAIN[7][3]

xc4000xv CNR_SE enum CONFIG_RATE
STARTUP.CONFIG_RATE	MAIN[0][0]
SLOW	1
FAST	0

xc4000xv CNR_SE enum DONE_TIMING
STARTUP.DONE_TIMING	MAIN[12][1]	MAIN[12][3]
Q0	1	1
Q1Q4	0	1
Q2	0	0
Q3	1	0

xc4000xv CNR_SE enum GTS_GSR_TIMING
STARTUP.GTS_TIMING	MAIN[17][3]	MAIN[18][3]
Q1Q4	1	1
Q2	0	1
Q3	0	0
DONE_IN	1	0

xc4000xv CNR_SE enum GTS_GSR_TIMING
STARTUP.GSR_TIMING	MAIN[16][3]	MAIN[15][3]
Q1Q4	0	1
Q2	1	1
Q3	1	0
DONE_IN	0	0

xc4000xv CNR_SE enum STARTUP_MUX_CLK
STARTUP.MUX_CLK	MAIN[10][1]
CCLK	0
USERCLK	1

Bels READCLK

xc4000xv CNR_SE bel READCLK pins
Pin	Direction	READCLK
I	in	IMUX_READCLK_I

Bels MISC_SE

xc4000xv CNR_SE bel MISC_SE pins
Pin	Direction	MISC_SE

xc4000xv CNR_SE bel MISC_SE attribute bits
Attribute	MISC_SE
DONE_PULLUP	!MAIN[6][1]
OSC_ENABLE	MAIN[0][4]
OSC_MUX_OUT0	[enum: OSC_MUX_OUT]
OSC_MUX_OUT1	[enum: OSC_MUX_OUT]
TCTEST	!MAIN[4][1]
TM_OSC	!MAIN[13][1]
OSC_CLK	[enum: OSC_CLK]
FIX_DISCHARGE	!MAIN[1][3]

xc4000xv CNR_SE enum OSC_MUX_OUT
MISC_SE.OSC_MUX_OUT0	MAIN[1][4]	MAIN[0][11]	MAIN[1][9]	MAIN[1][5]
MISC_SE.OSC_MUX_OUT1	MAIN[3][4]	MAIN[0][10]	MAIN[0][9]	MAIN[0][5]
F500K	0	0	1	1
F16K	0	1	0	1
F490	0	1	1	0
F15	1	1	1	1

xc4000xv CNR_SE enum OSC_CLK
MISC_SE.OSC_CLK	MAIN[14][1]
CCLK	1
EXTCLK	0

Bel wires

xc4000xv CNR_SE bel wires
Wire	Pins
DEC_H[0]	PULLUP_DEC_H[0].O
DEC_H[1]	PULLUP_DEC_H[1].O
DEC_H[2]	PULLUP_DEC_H[2].O
DEC_H[3]	PULLUP_DEC_H[3].O
DEC_V[0]	PULLUP_DEC_V[0].O
DEC_V[1]	PULLUP_DEC_V[1].O
DEC_V[2]	PULLUP_DEC_V[2].O
DEC_V[3]	PULLUP_DEC_V[3].O
BUFGLS[3]	BUFG_H.O
BUFGLS[4]	BUFG_V.O
IMUX_STARTUP_CLK	STARTUP.CLK
IMUX_STARTUP_GSR	STARTUP.GSR
IMUX_STARTUP_GTS	STARTUP.GTS
IMUX_READCLK_I	READCLK.I
IMUX_BUFG_H	BUFG_H.I
IMUX_BUFG_V	BUFG_V.I
OUT_STARTUP_DONEIN	STARTUP.DONEIN
OUT_STARTUP_Q1Q4	STARTUP.Q1Q4
OUT_STARTUP_Q2	STARTUP.Q2
OUT_STARTUP_Q3	STARTUP.Q3
OUT_BUFGE_H	BUFG_H.O_BUFGE
OUT_BUFGE_V	BUFG_V.O_BUFGE

Bitstream

xc4000xv CNR_SE rect MAIN
Bit	Frame
Bit	F51	F50	F49	F48	F47	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	INT: !pass QUAD_V0[2] ← QBUF[2]	INT: !bipass QUAD_H0[2] = QUAD_V0[2]	INT: !bipass QUAD_H0[2] = QUAD_H4[2]	INT: !bipass QUAD_H4[2] = QUAD_V0[2]	INT: !bipass QUAD_H4[2] = QUAD_V4[2]	INT: !bipass QUAD_H0[2] = QUAD_V4[2]	INT: !bipass QUAD_V0[2] = QUAD_V4[2]	INT: !bipass QUAD_H0[0] = QUAD_V0[0]	INT: !bipass QUAD_H0[0] = QUAD_H4[0]	INT: !bipass QUAD_H4[0] = QUAD_V0[0]	INT: !bipass QUAD_H4[0] = QUAD_V4[0]	INT: !bipass QUAD_H0[0] = QUAD_V4[0]	INT: !bipass QUAD_V0[0] = QUAD_V4[0]	INT: !bipass SINGLE_V_S[4] = QUAD_H0[1]	INT: !bipass SINGLE_V_S[6] = QUAD_H2[2]	-	INT: !bipass SINGLE_V_S[2] = QUAD_H2[1]	INT: !bipass SINGLE_V_S[0] = QUAD_H2[0]	-	-	-	-	-	-	-	-	INT: mux IMUX_CLB_C4 bit 2	INT: mux IMUX_CLB_C4 bit 0	INT: !bipass DOUBLE_IO_E1[0] = QUAD_H2[0]	-	INT: !bipass DOUBLE_IO_E1[1] = QUAD_H2[1]	-	INT: !bipass DOUBLE_IO_E0[3] = QUAD_H2[2]	INT: !bipass QUAD_H0[1] = LONG_IO_V[2]	INT: !pass QUAD_H0[1] ← OUT_IO_WE_I1_S1	INT: !pass QUAD_H3[2] ← OUT_IO_WE_I1_S1	INT: mux IMUX_CLB_F4 bit 0	-	INT: mux IMUX_CLB_G4 bit 1	-	-	-	-	-	-	-	INT: !pass QUAD_H1[1] ← DEC_V[2]	INT: !bipass DOUBLE_IO_E0[2] = QUAD_H1[1]	-	INT: !bipass DOUBLE_IO_E1[2] = QUAD_H3[2]	-	-
B14	INT: !pass QUAD_H0[2] ← QBUF[2]	INT: !pass QUAD_H4[2] ← QBUF[2]	INT: !pass QUAD_V4[2] ← QBUF[2]	INT: mux QBUF[2] bit 0	INT: mux QBUF[2] bit 1	INT: !pass QUAD_V0[0] ← QBUF[0]	INT: !pass QUAD_H0[0] ← QBUF[0]	INT: !pass QUAD_H4[0] ← QBUF[0]	INT: !pass QUAD_V4[0] ← QBUF[0]	INT: !pass QUAD_V0[1] ← QBUF[1]	INT: mux QBUF[0] bit 0	INT: mux QBUF[0] bit 1	INT: !bipass SINGLE_V_S[5] = QUAD_H3[2]	INT: !bipass DOUBLE_V1[1] = QUAD_H0[2]	INT: !bipass SINGLE_V_S[7] = QUAD_H1[2]	INT: !bipass SINGLE_V_S[3] = QUAD_H1[1]	INT: !bipass SINGLE_V_S[1] = QUAD_H0[0]	INT: !bipass DOUBLE_V2[0] = QUAD_H3[0]	-	-	-	-	-	-	-	-	INT: mux IMUX_CLB_C4 bit 4	INT: mux IMUX_CLB_C4 bit 3	INT: mux IMUX_CLB_C4 bit 1	-	INT: !pass QUAD_H0[2] ← OUT_IO_WE_I2_S1	INT: !bipass QUAD_H0[2] = LONG_IO_V[1]	INT: !pass QUAD_H3[0] ← OUT_IO_WE_I2_S1	INT: !bipass DOUBLE_IO_E0[0] = QUAD_H3[0]	INT: !bipass DOUBLE_IO_E1[3] = QUAD_H1[2]	INT: !pass QUAD_H1[2] ← DEC_V[1]	INT: mux IMUX_CLB_F4 bit 1	INT: mux ECLK_V bit 0	INT: mux IMUX_CLB_G4 bit 0	INT: mux ECLK_V bit 1	INT: mux ECLK_V bit 5	INT: mux ECLK_V bit 4	INT: mux ECLK_V bit 3	INT: mux ECLK_V bit 2	INT: mux ECLK_V bit 6	-	INT: !pass QUAD_H1[0] ← DEC_V[3]	INT: !bipass DOUBLE_IO_E0[1] = QUAD_H1[0]	-	INT: !bipass QUAD_H0[0] = LONG_IO_V[3]	-	-
B13	INT: !bipass QUAD_H4[1] = QUAD_V4[1]	INT: !bipass QUAD_H4[1] = QUAD_V0[1]	INT: !bipass QUAD_V0[1] = QUAD_V4[1]	INT: !bipass QUAD_H0[1] = QUAD_V4[1]	INT: !bipass QUAD_H0[1] = QUAD_V0[1]	INT: mux QBUF[1] bit 0	INT: mux QBUF[1] bit 1	INT: !pass QUAD_H4[1] ← QBUF[1]	INT: !pass QUAD_V4[1] ← QBUF[1]	INT: !pass QUAD_H0[1] ← QBUF[1]	INT: !pass SINGLE_H_E[2] ← LONG_V[1]	INT: !bipass SINGLE_H_E[7] = SINGLE_V_S[7]	INT: !bipass SINGLE_H[7] = SINGLE_H_E[7]	INT: !bipass SINGLE_H_E[7] = SINGLE_V[7]	INT: !bipass SINGLE_V[7] = SINGLE_V_S[7]	INT: !bipass SINGLE_H[7] = SINGLE_V[7]	INT: !pass SINGLE_H[6] ← LONG_V[5]	-	INT: !bipass SINGLE_H_E[2] = SINGLE_V_S[2]	INT: !bipass SINGLE_H_E[2] = SINGLE_V[2]	INT: !bipass SINGLE_V[2] = SINGLE_V_S[2]	INT: !bipass DOUBLE_H0[0] = DOUBLE_H2[0]	INT: !bipass DOUBLE_H0[0] = DOUBLE_V2[0]	INT: !bipass DOUBLE_H0[0] = DOUBLE_V0[0]	INT: !pass SINGLE_V[7] ← TIE_0	-	-	INT: !bipass SINGLE_H[6] = DOUBLE_IO_E0[3]	INT: !bipass DOUBLE_H1[1] = DOUBLE_IO_E0[3]	INT: !bipass SINGLE_H[7] = DOUBLE_IO_E1[3]	INT: !bipass DOUBLE_IO_S1[3] = DOUBLE_IO_E0[3]	INT: !bipass DOUBLE_H1[1] = DOUBLE_IO_E1[3]	INT: !bipass DOUBLE_H1[1] = DOUBLE_IO_S1[3]	INT: !bipass SINGLE_H[6] = DOUBLE_IO_S1[3]	INT: !bipass SINGLE_H[0] = DOUBLE_IO_S1[0]	INT: !bipass DOUBLE_H1[0] = DOUBLE_IO_S1[0]	INT: !bipass SINGLE_H[1] = DOUBLE_IO_E1[0]	INT: mux DBUF_IO_V[1] bit 0	INT: mux DBUF_IO_V[1] bit 2	INT: mux DBUF_IO_V[1] bit 1	INT: !bipass DOUBLE_H1[0] = DOUBLE_IO_E1[0]	INT: !bipass DOUBLE_IO_S1[0] = DOUBLE_IO_E0[0]	INT: mux DBUF_IO_V[1] bit 3	INT: !pass SINGLE_H[3] ← DEC_V[1]	INT: mux DBUF_IO_V[0] bit 1	INT: mux DBUF_IO_V[0] bit 0	INT: mux DBUF_IO_V[0] bit 2	INT: !bipass SINGLE_H[2] = DOUBLE_IO_E0[1]	INT: !bipass DOUBLE_H0[0] = DOUBLE_IO_E0[1]	INT: !bipass DOUBLE_IO_S1[1] = DOUBLE_IO_E0[1]	INT: !bipass DOUBLE_H0[0] = DOUBLE_IO_S1[1]	INT: !bipass SINGLE_H[2] = DOUBLE_IO_S1[1]
B12	-	INT: !bipass SINGLE_H_E[3] = QUAD_V0[1]	INT: !bipass QUAD_H0[1] = QUAD_H4[1]	INT: !bipass SINGLE_H_E[6] = QUAD_V3[2]	INT: !bipass SINGLE_H_E[5] = QUAD_V1[1]	-	INT: !bipass DOUBLE_H1[1] = QUAD_V3[1]	INT: !bipass DOUBLE_H2[0] = QUAD_V0[0]	INT: !bipass SINGLE_H_E[7] = QUAD_V2[2]	INT: !bipass SINGLE_H_E[2] = QUAD_V2[0]	-	INT: !bipass SINGLE_H_E[4] = SINGLE_V[4]	INT: !buffer LONG_V[1] ← SINGLE_H_E[2]	INT: !bipass SINGLE_H[7] = SINGLE_V_S[7]	INT: !bipass SINGLE_H[6] = SINGLE_V[6]	INT: !buffer LONG_V[5] ← SINGLE_H[6]	-	INT: !bipass SINGLE_H[2] = SINGLE_V_S[2]	INT: !bipass SINGLE_H[2] = SINGLE_H_E[2]	INT: !bipass SINGLE_H[2] = SINGLE_V[2]	-	INT: !bipass DOUBLE_H2[0] = DOUBLE_V2[0]	-	INT: !bipass DOUBLE_V0[0] = DOUBLE_V2[0]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	INT: !buffer LONG_V[9] ← SINGLE_H_E[7]	INT: !buffer LONG_V[8] ← SINGLE_H_E[4]	INT: !bipass SINGLE_H_E[0] = QUAD_V1[0]	INT: !pass SINGLE_H_E[0] ← LONG_V[6]	INT: !bipass SINGLE_H_E[1] = QUAD_V3[0]	INT: !bipass SINGLE_H_E[4] = QUAD_V0[2]	INT: !buffer LONG_V[6] ← SINGLE_H_E[0]	INT: !buffer LONG_V[7] ← SINGLE_H_E[3]	INT: !pass SINGLE_H_E[3] ← LONG_V[7]	INT: !pass SINGLE_V[6] ← LONG_H[5]	-	INT: !bipass SINGLE_V[6] = SINGLE_V_S[6]	INT: !bipass SINGLE_H_E[6] = SINGLE_V_S[6]	INT: !bipass SINGLE_H[6] = SINGLE_V_S[6]	INT: !bipass SINGLE_H[6] = SINGLE_H_E[6]	INT: !bipass SINGLE_H_E[6] = SINGLE_V[6]	INT: !bipass SINGLE_H_E[3] = SINGLE_V_S[3]	INT: !bipass SINGLE_H_E[3] = SINGLE_V[3]	INT: !bipass SINGLE_H[3] = SINGLE_H_E[3]	INT: !bipass SINGLE_H[3] = SINGLE_V_S[3]	INT: !bipass DOUBLE_H2[0] = DOUBLE_V0[0]	INT: !bipass SINGLE_H[3] = SINGLE_V[3]	INT: !bipass SINGLE_V[3] = SINGLE_V_S[3]	INT: !pass SINGLE_V[4] ← LONG_H[3]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INT: !pass SINGLE_H[6] ← OUT_STARTUP_Q1Q4	INT: !pass DOUBLE_H0[0] ← OUT_STARTUP_Q1Q4	INT: !pass SINGLE_H[2] ← OUT_STARTUP_Q1Q4	INT: mux DBUF_IO_V[0] bit 3	INT: !bipass SINGLE_H[4] = DOUBLE_IO_E0[2]	INT: !bipass DOUBLE_H0[1] = DOUBLE_IO_E0[2]	INT: !bipass DOUBLE_IO_S1[2] = DOUBLE_IO_E0[2]	MISC_SE: OSC_MUX_OUT0 bit 2
B10	-	-	-	-	-	-	-	-	-	-	-	INT: !bipass SINGLE_H[4] = SINGLE_V[4]	INT: !bipass SINGLE_V[4] = SINGLE_V_S[4]	INT: !bipass SINGLE_H_E[4] = SINGLE_V_S[4]	INT: !bipass SINGLE_H[4] = SINGLE_H_E[4]	INT: !bipass SINGLE_H[4] = SINGLE_V_S[4]	INT: !pass SINGLE_H_E[3] ← LONG_V[2]	INT: !bipass DOUBLE_H0[1] = DOUBLE_H2[1]	INT: !bipass DOUBLE_H0[1] = DOUBLE_V0[1]	-	INT: !bipass SINGLE_H_E[1] = SINGLE_V[1]	INT: !bipass SINGLE_V[0] = SINGLE_V_S[0]	INT: !bipass SINGLE_H[0] = SINGLE_H_E[0]	-	INT: !pass SINGLE_V[0] ← TIE_0	-	INT: !pass DOUBLE_H0[1] ← OUT_IO_WE_I2_S1	INT: !pass SINGLE_H[0] ← OUT_IO_WE_I2_S1	INT: !pass SINGLE_H[4] ← OUT_IO_WE_I2_S1	INT: !pass SINGLE_H[5] ← OUT_STARTUP_Q3	INT: !pass DOUBLE_H1[1] ← OUT_STARTUP_Q3	INT: !pass SINGLE_H[1] ← OUT_STARTUP_Q3	INT: !buffer LONG_V[2] ← SINGLE_H_E[3]	INT: !buffer LONG_H[5] ← SINGLE_V[6]	-	INT: !pass SINGLE_H[1] ← LONG_IO_V[0]	INT: !pass SINGLE_H[6] ← LONG_IO_V[3]	INT: !bipass DOUBLE_H1[0] = DOUBLE_IO_E0[0]	INT: !bipass SINGLE_H[0] = DOUBLE_IO_E0[0]	INT: !pass DOUBLE_IO_E0[3] ← DBUF_IO_V[0]	INT: !pass DOUBLE_IO_E0[2] ← DBUF_IO_V[0]	INT: !pass DOUBLE_IO_S1[0] ← DBUF_IO_V[1]	INT: !pass DOUBLE_IO_S1[2] ← DBUF_IO_V[1]	INT: !pass DOUBLE_IO_S1[3] ← DBUF_IO_V[1]	INT: !pass DOUBLE_IO_S1[1] ← DBUF_IO_V[1]	INT: !pass SINGLE_H[7] ← OUT_IO_WE_I1_S1	INT: !pass SINGLE_H[7] ← DEC_V[3]	INT: !bipass DOUBLE_H0[1] = DOUBLE_IO_E1[2]	INT: !bipass DOUBLE_H0[0] = DOUBLE_IO_E1[1]	INT: !bipass DOUBLE_H0[1] = DOUBLE_IO_S1[2]	INT: !bipass SINGLE_H[4] = DOUBLE_IO_S1[2]	MISC_SE: OSC_MUX_OUT1 bit 2
B9	-	-	-	-	-	-	-	-	-	-	INT: !pass SINGLE_V[5] ← LONG_H[4]	INT: !bipass SINGLE_V[5] = SINGLE_V_S[5]	INT: !bipass SINGLE_H_E[5] = SINGLE_V_S[5]	INT: !bipass SINGLE_H[5] = SINGLE_V_S[5]	INT: !bipass SINGLE_H_E[5] = SINGLE_V[5]	INT: !bipass SINGLE_H[5] = SINGLE_H_E[5]	INT: !bipass DOUBLE_H2[1] = DOUBLE_V2[1]	INT: !bipass DOUBLE_H2[1] = DOUBLE_V0[1]	INT: !pass SINGLE_H_E[1] ← LONG_V[0]	INT: !bipass SINGLE_H_E[1] = SINGLE_V_S[1]	INT: !bipass SINGLE_H[1] = SINGLE_H_E[1]	INT: !bipass SINGLE_H[1] = SINGLE_V[1]	INT: !bipass SINGLE_H_E[0] = SINGLE_V_S[0]	INT: !bipass SINGLE_H[0] = SINGLE_V[0]	INT: !bipass SINGLE_H_E[0] = SINGLE_V[0]	-	-	-	-	-	-	-	INT: !buffer LONG_H[4] ← SINGLE_V[5]	INT: !buffer LONG_V[0] ← SINGLE_H_E[1]	INT: !buffer LONG_V[4] ← SINGLE_H[5]	INT: !pass SINGLE_H[2] ← LONG_IO_V[1]	INT: !buffer LONG_V[3] ← SINGLE_H[4]	INT: !pass DOUBLE_IO_E0[0] ← DBUF_IO_V[0]	INT: !pass DOUBLE_IO_E0[1] ← DBUF_IO_V[0]	INT: !pass DOUBLE_H1[0] ← OUT_IO_WE_I1_S1	INT: !pass SINGLE_H[3] ← OUT_IO_WE_I1_S1	INT: !pass SINGLE_H[0] ← DEC_V[0]	INT: !pass SINGLE_H[5] ← LONG_IO_V[2]	INT: !pass SINGLE_H[4] ← DEC_V[2]	INT: mux IMUX_READCLK_I bit 2	INT: mux IMUX_READCLK_I bit 1	INT: mux IMUX_READCLK_I bit 0	INT: mux IMUX_READCLK_I bit 3	INT: !bipass SINGLE_H[3] = DOUBLE_IO_E1[1]	INT: !bipass SINGLE_H[5] = DOUBLE_IO_E1[2]	MISC_SE: OSC_MUX_OUT0 bit 1	MISC_SE: OSC_MUX_OUT1 bit 1
B8	-	-	INT: !pass SINGLE_H_E[7] ← LONG_V[9]	INT: !pass SINGLE_H_E[4] ← LONG_V[8]	-	-	-	-	-	-	INT: mux IMUX_STARTUP_CLK bit 0	INT: mux IMUX_STARTUP_CLK bit 1	INT: mux IMUX_STARTUP_CLK bit 2	INT: mux IMUX_STARTUP_CLK bit 3	INT: !bipass SINGLE_H[5] = SINGLE_V[5]	INT: !pass SINGLE_H[4] ← LONG_V[3]	INT: !bipass DOUBLE_V0[1] = DOUBLE_V2[1]	INT: !bipass DOUBLE_H0[1] = DOUBLE_V2[1]	-	INT: !bipass SINGLE_V[1] = SINGLE_V_S[1]	INT: !bipass SINGLE_H[0] = SINGLE_V_S[0]	INT: !bipass SINGLE_H[1] = SINGLE_V_S[1]	INT: !pass SINGLE_H[5] ← LONG_V[4]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	INT: mux LONG_IO_H[2] bit 2	INT: mux LONG_IO_H[2] bit 3	INT: mux LONG_V[8] bit 0	-	-	INT: mux LONG_IO_H[3] bit 3	INT: mux LONG_V[9] bit 0	INT: mux LONG_IO_H[3] bit 2	INT: !pass SINGLE_V[4] ← OUT_IO_SN_I2_E1	INT: !pass SINGLE_V[4] ← DEC_H[1]	INT: !pass DOUBLE_V1[1] ← OUT_IO_SN_I2_E1	INT: mux LONG_V[1] bit 2	INT: !pass SINGLE_V[3] ← DEC_H[2]	INT: mux LONG_V[3] bit 1	INT: mux LONG_V[3] bit 2	INT: mux IMUX_STARTUP_GSR bit 3	INT: mux IMUX_STARTUP_GSR bit 0	INT: mux IMUX_STARTUP_GSR bit 2	INT: mux IMUX_STARTUP_GSR bit 1	INT: mux IMUX_STARTUP_GSR bit 5	INT: mux IMUX_STARTUP_GSR bit 4	INT: !pass SINGLE_V[1] ← OUT_STARTUP_DONEIN	INT: mux LONG_V[2] bit 0	-	INT: mux LONG_V[2] bit 2	INT: !buffer LONG_H[3] ← SINGLE_V[4]	-	INT: mux LONG_H[3] bit 0	INT: mux LONG_H[5] bit 1	INT: mux IMUX_BUFG_V bit 2	INT: mux IMUX_BUFG_V bit 1	INT: mux IMUX_BUFG_V bit 3	INT: mux IMUX_BUFG_V bit 5	INT: mux IMUX_BUFG_V bit 4	INT: mux IMUX_BUFG_V bit 0	-	INT: !pass DOUBLE_V1[0] ← OUT_STARTUP_Q2	INT: !pass SINGLE_V[2] ← OUT_STARTUP_Q2	INT: !pass SINGLE_V[6] ← OUT_STARTUP_Q2	INT: mux LONG_H[4] bit 3	INT: mux LONG_H[4] bit 1	BUFG_V: ! CLK_EN	INT: mux LONG_H[4] bit 0	INT: mux LONG_H[4] bit 2	-	-	-	-	-	-
B5	-	INT: !pass QUAD_V3[2] ← DEC_H[0]	INT: mux LONG_IO_H[0] bit 2	INT: mux LONG_IO_H[0] bit 3	INT: mux LONG_V[6] bit 0	INT: mux LONG_V[7] bit 0	INT: mux LONG_IO_H[1] bit 3	INT: !pass QUAD_V3[0] ← OUT_IO_SN_I2_E1	INT: mux LONG_IO_H[1] bit 2	INT: !pass QUAD_V0[2] ← OUT_IO_SN_I2_E1	-	INT: mux LONG_V[1] bit 0	INT: mux LONG_V[1] bit 3	INT: mux LONG_V[1] bit 1	INT: mux LONG_V[3] bit 0	INT: mux LONG_V[3] bit 3	INT: mux IMUX_STARTUP_GTS bit 1	INT: mux IMUX_STARTUP_GTS bit 2	INT: mux IMUX_STARTUP_GTS bit 3	INT: mux IMUX_STARTUP_GTS bit 4	INT: mux IMUX_STARTUP_GTS bit 5	INT: mux IMUX_STARTUP_GTS bit 0	INT: mux LONG_V[2] bit 3	INT: mux LONG_V[2] bit 1	INT: !pass SINGLE_V[0] ← OUT_IO_SN_I2_E1	-	INT: mux LONG_V[4] bit 3	INT: mux LONG_V[4] bit 0	INT: mux LONG_V[4] bit 1	INT: mux LONG_V[4] bit 2	INT: mux LONG_H[3] bit 1	INT: mux LONG_H[5] bit 0	INT: mux LONG_H[5] bit 2	INT: mux LONG_H[5] bit 3	-	INT: mux LONG_IO_V[2] bit 2	INT: mux LONG_IO_V[0] bit 2	INT: mux LONG_IO_V[2] bit 1	INT: mux LONG_IO_V[2] bit 0	PULLUP_DEC_V[3]: ! ENABLE	PULLUP_DEC_V[1]: ! ENABLE	INT: !pass SINGLE_V[6] ← LONG_IO_H[3]	PULLUP_DEC_V[2]: ! ENABLE	PULLUP_DEC_V[0]: ! ENABLE	INT: mux LONG_IO_V[1] bit 2	INT: mux LONG_IO_V[1] bit 0	INT: mux LONG_IO_V[1] bit 1	INT: mux LONG_IO_V[2] bit 3	INT: mux LONG_IO_V[3] bit 3	-	MISC_SE: OSC_MUX_OUT0 bit 0	MISC_SE: OSC_MUX_OUT1 bit 0
B4	INT: !bipass QUAD_V0[1] = LONG_IO_H[1]	INT: !bipass QUAD_V0[2] = LONG_IO_H[3]	INT: !pass QUAD_V3[2] ← OUT_IO_SN_I1_E1	-	-	-	INT: mux ECLK_H bit 3	INT: mux ECLK_H bit 1	INT: mux ECLK_H bit 0	INT: mux ECLK_H bit 2	-	PULLUP_DEC_H[3]: ! ENABLE	PULLUP_DEC_H[2]: ! ENABLE	PULLUP_DEC_H[1]: ! ENABLE	INT: !pass SINGLE_V[7] ← OUT_IO_SN_I1_E1	INT: mux LONG_V[5] bit 3	INT: !pass SINGLE_V[7] ← DEC_H[0]	INT: mux LONG_V[5] bit 1	INT: mux LONG_V[5] bit 0	INT: mux LONG_V[5] bit 2	INT: !pass SINGLE_V[3] ← OUT_IO_SN_I1_E1	INT: !pass DOUBLE_V0[1] ← OUT_STARTUP_DONEIN	INT: !pass SINGLE_V[5] ← LONG_IO_H[2]	INT: !pass SINGLE_V[5] ← OUT_STARTUP_DONEIN	INT: mux LONG_IO_H[3] bit 4	-	INT: mux LONG_V[0] bit 0	INT: mux LONG_V[0] bit 1	INT: mux LONG_IO_V[2] bit 4	INT: mux LONG_V[0] bit 2	INT: mux LONG_IO_V[0] bit 3	INT: mux LONG_V[0] bit 3	INT: !pass SINGLE_V[2] ← LONG_IO_H[1]	INT: !pass SINGLE_V[1] ← LONG_IO_H[0]	INT: mux LONG_IO_V[3] bit 4	INT: mux LONG_IO_V[0] bit 0	INT: mux LONG_IO_V[0] bit 1	INT: !pass SINGLE_V[0] ← DEC_H[3]	INT: !pass DOUBLE_V0[0] ← OUT_IO_SN_I1_E1	INT: mux LONG_IO_V[3] bit 0	INT: mux DBUF_IO_H[0] bit 2	INT: mux LONG_IO_V[1] bit 4	INT: mux DBUF_IO_H[0] bit 0	INT: mux DBUF_IO_H[0] bit 1	INT: mux DBUF_IO_H[0] bit 3	INT: mux LONG_IO_V[3] bit 2	INT: mux LONG_IO_V[1] bit 3	INT: mux LONG_IO_V[3] bit 1	MISC_SE: OSC_MUX_OUT1 bit 3	-	MISC_SE: OSC_MUX_OUT0 bit 3	MISC_SE: OSC_ENABLE
B3	-	INT: !bipass QUAD_V0[0] = LONG_IO_H[0]	INT: !pass DOUBLE_IO_S1[1] ← LONG_V[8]	-	-	-	-	INT: mux ECLK_H bit 4	INT: mux ECLK_H bit 5	INT: mux ECLK_H bit 6	-	PULLUP_DEC_H[0]: ! ENABLE	INT: mux LONG_IO_H[2] bit 5	INT: mux LONG_IO_H[2] bit 4	INT: mux LONG_IO_H[2] bit 7	INT: mux LONG_IO_H[3] bit 5	INT: mux LONG_IO_H[2] bit 6	INT: mux LONG_IO_H[1] bit 7	INT: mux LONG_IO_H[1] bit 5	INT: mux LONG_IO_H[1] bit 4	INT: mux LONG_IO_H[1] bit 6	INT: mux LONG_IO_H[0] bit 5	INT: mux LONG_IO_H[0] bit 4	INT: !bipass DOUBLE_IO_S2[1] = DOUBLE_IO_E1[1]	INT: !bipass DOUBLE_V0[0] = DOUBLE_IO_S1[1]	INT: mux IMUX_BUFG_H bit 2	INT: !bipass DOUBLE_V1[0] = DOUBLE_IO_S1[0]	INT: !bipass DOUBLE_IO_S2[0] = DOUBLE_IO_E1[0]	INT: mux LONG_IO_H[0] bit 1	INT: mux LONG_IO_H[0] bit 0	INT: mux IMUX_BUFG_H bit 6	INT: mux LONG_IO_H[2] bit 0	INT: mux LONG_IO_H[2] bit 1	STARTUP: GTS_TIMING bit 0	STARTUP: GTS_TIMING bit 1	STARTUP: GSR_TIMING bit 1	STARTUP: GSR_TIMING bit 0	INT: mux LONG_IO_H[1] bit 1	INT: mux LONG_IO_H[1] bit 0	STARTUP: DONE_TIMING bit 0	INT: mux LONG_IO_H[3] bit 0	INT: mux LONG_IO_H[3] bit 1	-	-	STARTUP: ! EXPRESS_MODE	-	-	-	-	-	MISC_SE: ! FIX_DISCHARGE	BUFG_V: ! ALT_PAD
B2	INT: !bipass DOUBLE_IO_S2[1] = QUAD_V3[0]	INT: !pass DOUBLE_IO_S2[0] ← LONG_V[9]	INT: mux VCLK bit 1	INT: !pass DOUBLE_IO_S2[3] ← LONG_V[6]	INT: !bipass DOUBLE_IO_S1[1] = QUAD_V1[1]	INT: !bipass DOUBLE_IO_S2[0] = QUAD_V1[0]	INT: !pass QUAD_V3[1] ← DEC_H[1]	INT: !pass DOUBLE_IO_S1[0] ← GCLK[4]	INT: !pass DOUBLE_IO_S2[1] ← GCLK[5]	INT: !pass DOUBLE_IO_S1[3] ← GCLK[7]	-	INT: mux DBUF_IO_H[1] bit 2	INT: mux DBUF_IO_H[1] bit 3	INT: !bipass SINGLE_V[7] = DOUBLE_IO_S2[3]	INT: !bipass DOUBLE_V1[1] = DOUBLE_IO_S2[3]	INT: !bipass DOUBLE_IO_S2[3] = DOUBLE_IO_E1[3]	INT: !bipass DOUBLE_V1[1] = DOUBLE_IO_S1[3]	INT: !bipass SINGLE_V[5] = DOUBLE_IO_S2[2]	INT: !bipass DOUBLE_V0[1] = DOUBLE_IO_S2[2]	INT: !bipass SINGLE_V[3] = DOUBLE_IO_S2[1]	INT: !bipass DOUBLE_V0[0] = DOUBLE_IO_S2[1]	INT: !bipass SINGLE_V[2] = DOUBLE_IO_S1[1]	INT: !bipass DOUBLE_V0[0] = DOUBLE_IO_E1[1]	INT: !bipass SINGLE_V[1] = DOUBLE_IO_S2[0]	INT: !bipass DOUBLE_V1[0] = DOUBLE_IO_S2[0]	INT: mux IMUX_BUFG_H bit 1	INT: !bipass DOUBLE_V1[0] = DOUBLE_IO_E1[0]	INT: !bipass SINGLE_V[1] = DOUBLE_IO_E1[0]	INT: !pass DOUBLE_IO_E1[0] ← DBUF_IO_H[1]	INT: !pass DOUBLE_IO_E1[2] ← DBUF_IO_H[1]	INT: !pass DOUBLE_IO_E1[1] ← DBUF_IO_H[1]	INT: mux IMUX_BUFG_H bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	INT: mux VCLK bit 0	INT: mux VCLK bit 3	INT: mux VCLK bit 4	INT: mux VCLK bit 5	INT: mux VCLK bit 2	INT: !bipass DOUBLE_IO_S1[0] = QUAD_V2[0]	INT: !bipass DOUBLE_IO_S1[2] = QUAD_V3[1]	INT: !bipass DOUBLE_IO_S2[3] = QUAD_V1[2]	INT: !bipass DOUBLE_IO_S1[3] = QUAD_V2[2]	-	-	INT: mux DBUF_IO_H[1] bit 0	INT: mux DBUF_IO_H[1] bit 1	INT: !bipass SINGLE_V[6] = DOUBLE_IO_S1[3]	INT: !bipass DOUBLE_V1[1] = DOUBLE_IO_E1[3]	INT: !bipass SINGLE_V[7] = DOUBLE_IO_E1[3]	INT: !pass DOUBLE_IO_S2[3] ← DBUF_IO_H[0]	INT: !pass DOUBLE_IO_S2[2] ← DBUF_IO_H[0]	INT: !pass DOUBLE_IO_S2[1] ← DBUF_IO_H[0]	INT: !pass DOUBLE_IO_S2[0] ← DBUF_IO_H[0]	INT: !bipass DOUBLE_IO_S2[2] = DOUBLE_IO_E1[2]	INT: !bipass DOUBLE_V0[1] = DOUBLE_IO_S1[2]	INT: !bipass SINGLE_V[5] = DOUBLE_IO_E1[2]	INT: !bipass DOUBLE_V0[1] = DOUBLE_IO_E1[2]	INT: !bipass SINGLE_V[4] = DOUBLE_IO_S1[2]	INT: mux IMUX_BUFG_H bit 4	INT: !bipass SINGLE_V[3] = DOUBLE_IO_E1[1]	INT: !bipass SINGLE_V[0] = DOUBLE_IO_S1[0]	INT: !pass DOUBLE_IO_E1[3] ← DBUF_IO_H[1]	INT: mux IMUX_BUFG_H bit 5	INT: mux IMUX_BUFG_H bit 3	-	-	-	-	-	BUFG_H: ! ALT_PAD	MISC_SE: OSC_CLK bit 0	MISC_SE: ! TM_OSC	STARTUP: DONE_TIMING bit 1	STARTUP: ! SYNC_TO_DONE	STARTUP: MUX_CLK bit 0	STARTUP: !invert GSR	STARTUP: ! GSR_ENABLE	STARTUP: !invert GTS	MISC_SE: ! DONE_PULLUP	STARTUP: ! GTS_ENABLE	MISC_SE: ! TCTEST	-	BUFG_H: ! CLK_EN	-	STARTUP: ! CRC
B0	-	INT: !pass DOUBLE_IO_S1[2] ← LONG_V[7]	-	-	INT: mux VCLK bit 6	INT: !pass QUAD_V3[0] ← DEC_H[2]	-	INT: !bipass DOUBLE_IO_S2[2] = QUAD_V2[1]	INT: !pass QUAD_V0[1] ← OUT_IO_SN_I1_E1	INT: !pass DOUBLE_IO_S2[2] ← GCLK[6]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	STARTUP: CONFIG_RATE bit 0

Tile CNR_NE

Cells: 2

Switchbox INT

xc4000xv CNR_NE switchbox INT permanent buffers
Destination	Source
CELL.BUFGE_H	CELL.OUT_BUFGE_H
CELL.BUFGE_V[1]	CELL.OUT_BUFGE_V

xc4000xv CNR_NE switchbox INT programmable buffers
Destination	Source	Bit
CELL.LONG_H[0]	CELL.SINGLE_V[1]	!MAIN_S[27][8]
CELL.LONG_H[1]	CELL.SINGLE_V[2]	!MAIN_S[31][8]
CELL.LONG_H[2]	CELL.SINGLE_V[3]	!MAIN[24][2]

xc4000xv CNR_NE switchbox INT pass gates
Destination	Source	Bit
CELL.SINGLE_V[0]	CELL.DEC_H[0]	!MAIN[14][4]
CELL.SINGLE_V[0]	CELL.OUT_IO_SN_I2_E1	!MAIN[27][3]
CELL.SINGLE_V[1]	CELL.LONG_H[0]	!MAIN_S[29][8]
CELL.SINGLE_V[1]	CELL.LONG_IO_H[0]	!MAIN[18][4]
CELL.SINGLE_V[1]	CELL.OUT_OSC_MUX1	!MAIN[28][2]
CELL.SINGLE_V[2]	CELL.LONG_H[1]	!MAIN_S[35][8]
CELL.SINGLE_V[2]	CELL.LONG_IO_H[1]	!MAIN[19][4]
CELL.SINGLE_V[2]	CELL.OUT_UPDATE_O	!MAIN[12][2]
CELL.SINGLE_V[3]	CELL.LONG_H[2]	!MAIN_S[34][9]
CELL.SINGLE_V[3]	CELL.DEC_H[1]	!MAIN[37][2]
CELL.SINGLE_V[3]	CELL.OUT_IO_SN_I1_E1	!MAIN[31][4]
CELL.SINGLE_V[4]	CELL.DEC_H[2]	!MAIN[40][2]
CELL.SINGLE_V[4]	CELL.OUT_IO_SN_I2_E1	!MAIN[41][2]
CELL.SINGLE_V[5]	CELL.LONG_IO_H[2]	!MAIN[29][4]
CELL.SINGLE_V[5]	CELL.OUT_OSC_MUX1	!MAIN[28][4]
CELL.SINGLE_V[6]	CELL.LONG_IO_H[3]	!MAIN[10][3]
CELL.SINGLE_V[6]	CELL.OUT_UPDATE_O	!MAIN[11][2]
CELL.SINGLE_V[7]	CELL.DEC_H[3]	!MAIN[35][4]
CELL.SINGLE_V[7]	CELL.OUT_IO_SN_I1_E1	!MAIN[37][4]
CELL.DOUBLE_V0[0]	CELL.OUT_IO_SN_I1_E1	!MAIN[13][4]
CELL.DOUBLE_V0[1]	CELL.OUT_OSC_MUX1	!MAIN[30][4]
CELL.DOUBLE_V1[0]	CELL.OUT_UPDATE_O	!MAIN[13][2]
CELL.DOUBLE_V1[1]	CELL.OUT_IO_SN_I2_E1	!MAIN[39][2]
CELL.DOUBLE_IO_E1[0]	CELL.GCLK[4]	!MAIN[44][6]
CELL.DOUBLE_IO_E1[1]	CELL.LONG_V[8]	!MAIN[49][5]
CELL.DOUBLE_IO_E1[2]	CELL.LONG_V[7]	!MAIN[50][8]
CELL.DOUBLE_IO_E1[3]	CELL.GCLK[7]	!MAIN[42][6]
CELL.DOUBLE_IO_E2[0]	CELL.DBUF_IO_H[1]	!MAIN[23][6]
CELL.DOUBLE_IO_E2[1]	CELL.DBUF_IO_H[1]	!MAIN[21][6]
CELL.DOUBLE_IO_E2[2]	CELL.DBUF_IO_H[1]	!MAIN[22][6]
CELL.DOUBLE_IO_E2[3]	CELL.DBUF_IO_H[1]	!MAIN[23][7]
CELL.DOUBLE_IO_N0[0]	CELL.DBUF_IO_H[0]	!MAIN[32][7]
CELL.DOUBLE_IO_N0[0]	CELL.LONG_V[9]	!MAIN[50][6]
CELL.DOUBLE_IO_N0[1]	CELL.DBUF_IO_H[0]	!MAIN[33][7]
CELL.DOUBLE_IO_N0[1]	CELL.GCLK[5]	!MAIN[43][6]
CELL.DOUBLE_IO_N0[2]	CELL.DBUF_IO_H[0]	!MAIN[34][7]
CELL.DOUBLE_IO_N0[2]	CELL.GCLK[6]	!MAIN[42][8]
CELL.DOUBLE_IO_N0[3]	CELL.DBUF_IO_H[0]	!MAIN[35][7]
CELL.DOUBLE_IO_N0[3]	CELL.LONG_V[6]	!MAIN[48][6]
CELL.QUAD_V0[1]	CELL.OUT_IO_SN_I1_E1	!MAIN[43][8]
CELL.QUAD_V0[2]	CELL.OUT_IO_SN_I2_E1	!MAIN[42][3]
CELL.QUAD_V2[0]	CELL.DEC_H[1]	!MAIN[46][8]
CELL.QUAD_V2[0]	CELL.OUT_COUT_E	!MAIN[50][3]
CELL.QUAD_V2[1]	CELL.DEC_H[2]	!MAIN[45][6]
CELL.QUAD_V2[2]	CELL.DEC_H[3]	!MAIN[51][3]
CELL.QUAD_V3[0]	CELL.OUT_IO_SN_I2_E1	!MAIN[44][3]
CELL.QUAD_V3[2]	CELL.OUT_IO_SN_I1_E1	!MAIN[49][4]

xc4000xv CNR_NE switchbox INT bidirectional pass gates
Side A	Side B	Bit
CELL.SINGLE_V[0]	CELL.DOUBLE_IO_E1[0]	!MAIN[24][7]
CELL.SINGLE_V[1]	CELL.DOUBLE_IO_E2[0]	!MAIN[24][6]
CELL.SINGLE_V[1]	CELL.DOUBLE_IO_N0[0]	!MAIN[28][6]
CELL.SINGLE_V[2]	CELL.DOUBLE_IO_E1[1]	!MAIN[30][6]
CELL.SINGLE_V[3]	CELL.DOUBLE_IO_E2[1]	!MAIN[25][7]
CELL.SINGLE_V[3]	CELL.DOUBLE_IO_N0[1]	!MAIN[32][6]
CELL.SINGLE_V[4]	CELL.DOUBLE_IO_E1[2]	!MAIN[27][7]
CELL.SINGLE_V[5]	CELL.DOUBLE_IO_E2[2]	!MAIN[29][7]
CELL.SINGLE_V[5]	CELL.DOUBLE_IO_N0[2]	!MAIN[34][6]
CELL.SINGLE_V[6]	CELL.DOUBLE_IO_E1[3]	!MAIN[38][7]
CELL.SINGLE_V[7]	CELL.DOUBLE_IO_E2[3]	!MAIN[36][7]
CELL.SINGLE_V[7]	CELL.DOUBLE_IO_N0[3]	!MAIN[38][6]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_E1[1]	!MAIN[27][5]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_E2[1]	!MAIN[29][6]
CELL.DOUBLE_V0[0]	CELL.DOUBLE_IO_N0[1]	!MAIN[31][6]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_E1[2]	!MAIN[30][7]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_E2[2]	!MAIN[28][7]
CELL.DOUBLE_V0[1]	CELL.DOUBLE_IO_N0[2]	!MAIN[33][6]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_E1[0]	!MAIN[25][5]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_E2[0]	!MAIN[25][6]
CELL.DOUBLE_V1[0]	CELL.DOUBLE_IO_N0[0]	!MAIN[27][6]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_E1[3]	!MAIN[35][6]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_E2[3]	!MAIN[37][7]
CELL.DOUBLE_V1[1]	CELL.DOUBLE_IO_N0[3]	!MAIN[37][6]
CELL.DOUBLE_IO_E1[0]	CELL.QUAD_V2[0]	!MAIN[46][7]
CELL.DOUBLE_IO_E1[1]	CELL.QUAD_V1[1]	!MAIN[47][6]
CELL.DOUBLE_IO_E1[2]	CELL.QUAD_V0[1]	!MAIN[45][7]
CELL.DOUBLE_IO_E1[3]	CELL.QUAD_V0[2]	!MAIN[43][7]
CELL.DOUBLE_IO_E2[0]	CELL.DOUBLE_IO_N0[0]	!MAIN[24][5]
CELL.DOUBLE_IO_E2[1]	CELL.DOUBLE_IO_N0[1]	!MAIN[28][5]
CELL.DOUBLE_IO_E2[2]	CELL.DOUBLE_IO_N0[2]	!MAIN[31][7]
CELL.DOUBLE_IO_E2[3]	CELL.DOUBLE_IO_N0[3]	!MAIN[36][6]
CELL.DOUBLE_IO_N0[0]	CELL.QUAD_V1[0]	!MAIN[46][6]
CELL.DOUBLE_IO_N0[1]	CELL.QUAD_V0[0]	!MAIN[51][6]
CELL.DOUBLE_IO_N0[2]	CELL.QUAD_V2[1]	!MAIN[44][8]
CELL.DOUBLE_IO_N0[3]	CELL.QUAD_V1[2]	!MAIN[44][7]
CELL.QUAD_V3[0]	CELL.LONG_IO_H[0]	!MAIN[50][5]
CELL.QUAD_V3[1]	CELL.LONG_IO_H[1]	!MAIN[51][4]
CELL.QUAD_V3[2]	CELL.LONG_IO_H[3]	!MAIN[50][4]

xc4000xv CNR_NE switchbox INT muxes DBUF_IO_H[0]
Bits				Destination
MAIN[7][4]	MAIN[11][4]	MAIN[8][4]	MAIN[9][4]	CELL.DBUF_IO_H[0]
				Source
0	0	1	1	CELL.DOUBLE_IO_E2[0]
0	1	0	1	CELL.DOUBLE_IO_E2[2]
0	1	1	0	CELL.DOUBLE_IO_E2[3]
1	1	1	1	CELL.DOUBLE_IO_E2[1]

xc4000xv CNR_NE switchbox INT muxes DBUF_IO_H[1]
Bits				Destination
MAIN[39][6]	MAIN[40][6]	MAIN[39][7]	MAIN[40][7]	CELL.DBUF_IO_H[1]
				Source
0	0	1	1	CELL.DOUBLE_IO_N0[1]
0	1	0	1	CELL.DOUBLE_IO_N0[2]
0	1	1	0	CELL.DOUBLE_IO_N0[3]
1	1	1	1	CELL.DOUBLE_IO_N0[0]

xc4000xv CNR_NE switchbox INT muxes LONG_H[0]
Bits				Destination
MAIN[18][3]	MAIN[19][3]	MAIN[21][2]	MAIN[20][3]	CELL.LONG_H[0]
				Source
0	0	0	1	CELL.LONG_IO_V[0]
0	0	1	0	CELL.DEC_V[3]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000xv CNR_NE switchbox INT muxes LONG_H[1]
Bits				Destination
MAIN[10][2]	MAIN[6][2]	MAIN[9][2]	MAIN[7][2]	CELL.LONG_H[1]
				Source
0	0	0	1	CELL.LONG_IO_V[1]
0	0	1	0	CELL.DEC_V[2]
0	1	1	1	CELL.OUT_IO_WE_I2[1]
1	1	1	1	off

xc4000xv CNR_NE switchbox INT muxes LONG_H[2]
Bits		Destination
MAIN[21][3]	MAIN[22][2]	CELL.LONG_H[2]
		Source
0	0	CELL.LONG_IO_V[2]
0	1	CELL.DEC_V[1]
1	1	off

xc4000xv CNR_NE switchbox INT muxes LONG_V[0]
Bits				Destination
MAIN[20][4]	MAIN[22][4]	MAIN[24][4]	MAIN[25][4]	CELL.LONG_V[0]
				Source
0	0	0	1	CELL.LONG_IO_H[0]
0	0	1	0	CELL.DEC_H[3]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000xv CNR_NE switchbox INT muxes LONG_V[1]
Bits				Destination
MAIN[39][3]	MAIN[38][2]	MAIN[38][3]	MAIN[40][3]	CELL.LONG_V[1]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000xv CNR_NE switchbox INT muxes LONG_V[2]
Bits				Destination
MAIN[29][3]	MAIN[25][2]	MAIN[28][3]	MAIN[27][2]	CELL.LONG_V[2]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_IO_SN_I2_E1
1	1	1	1	off

xc4000xv CNR_NE switchbox INT muxes LONG_V[3]
Bits				Destination
MAIN[36][3]	MAIN[35][2]	MAIN[36][2]	MAIN[37][3]	CELL.LONG_V[3]
				Source
0	0	0	1	CELL.LONG_IO_H[1]
0	0	1	0	CELL.DEC_H[2]
0	1	1	1	CELL.OUT_OSC_MUX1
1	1	1	1	off

xc4000xv CNR_NE switchbox INT muxes LONG_V[4]
Bits				Destination
MAIN[25][3]	MAIN[22][3]	MAIN[23][3]	MAIN[24][3]	CELL.LONG_V[4]
				Source
0	0	0	1	CELL.LONG_IO_H[2]
0	0	1	0	CELL.DEC_H[1]
0	1	1	1	CELL.OUT_OSC_MUX1
1	1	1	1	off

xc4000xv CNR_NE switchbox INT muxes LONG_V[5]
Bits				Destination
MAIN[36][4]	MAIN[32][4]	MAIN[34][4]	MAIN[33][4]	CELL.LONG_V[5]
				Source
0	0	0	1	CELL.LONG_IO_H[3]
0	0	1	0	CELL.DEC_H[0]
0	1	1	1	CELL.OUT_OSC_MUX1
1	1	1	1	off

xc4000xv CNR_NE switchbox INT muxes LONG_V[6]
Bits	Destination
MAIN[47][3]	CELL.LONG_V[6]
	Source
0	CELL.LONG_IO_H[0]
1	off

xc4000xv CNR_NE switchbox INT muxes LONG_V[7]
Bits	Destination
MAIN[46][3]	CELL.LONG_V[7]
	Source
0	CELL.LONG_IO_H[1]
1	off

xc4000xv CNR_NE switchbox INT muxes LONG_V[8]
Bits	Destination
MAIN[47][2]	CELL.LONG_V[8]
	Source
0	CELL.LONG_IO_H[2]
1	off

xc4000xv CNR_NE switchbox INT muxes LONG_V[9]
Bits	Destination
MAIN[43][2]	CELL.LONG_V[9]
	Source
0	CELL.LONG_IO_H[3]
1	off

xc4000xv CNR_NE switchbox INT muxes LONG_IO_H[0]
Bits						Destination
MAIN[30][5]	MAIN[29][5]	MAIN[48][3]	MAIN[49][3]	MAIN[23][5]	MAIN[22][5]	CELL.LONG_IO_H[0]
						Source
0	0	1	1	1	1	CELL.LONG_V[0]
0	1	1	1	1	1	CELL.SINGLE_V[1]
1	1	0	0	1	1	CELL.LONG_V[6]
1	1	0	1	1	1	CELL.GCLK[4]
1	1	1	1	0	0	CELL.LONG_IO_V[2]
1	1	1	1	0	1	CELL.LONG_IO_V[0]
1	1	1	1	1	1	off

xc4000xv CNR_NE switchbox INT muxes LONG_IO_H[1]
Bits								Destination
MAIN[34][5]	MAIN[31][5]	MAIN[33][5]	MAIN[32][5]	MAIN[45][3]	MAIN[43][3]	MAIN[14][5]	MAIN[13][5]	CELL.LONG_IO_H[1]
								Source
0	0	0	1	1	1	1	1	CELL.LONG_V[1]
0	0	1	0	1	1	1	1	CELL.LONG_V[3]
0	1	1	1	1	1	1	1	CELL.SINGLE_V[2]
1	1	1	1	0	0	1	1	CELL.LONG_V[7]
1	1	1	1	0	1	1	1	CELL.GCLK[5]
1	1	1	1	1	1	0	0	CELL.LONG_IO_V[3]
1	1	1	1	1	1	0	1	CELL.LONG_IO_V[1]
1	1	1	1	1	1	1	1	off

xc4000xv CNR_NE switchbox INT muxes LONG_IO_H[2]
Bits								Destination
MAIN[37][5]	MAIN[35][5]	MAIN[39][5]	MAIN[38][5]	MAIN[48][2]	MAIN[49][2]	MAIN[19][5]	MAIN[20][5]	CELL.LONG_IO_H[2]
								Source
0	0	0	1	1	1	1	1	CELL.LONG_V[2]
0	0	1	0	1	1	1	1	CELL.LONG_V[4]
0	1	1	1	1	1	1	1	CELL.SINGLE_V[5]
1	1	1	1	0	0	1	1	CELL.LONG_V[8]
1	1	1	1	0	1	1	1	CELL.GCLK[6]
1	1	1	1	1	1	0	0	CELL.LONG_IO_V[0]
1	1	1	1	1	1	0	1	CELL.LONG_IO_V[2]
1	1	1	1	1	1	1	1	off

xc4000xv CNR_NE switchbox INT muxes LONG_IO_H[3]
Bits						Destination
MAIN[36][5]	MAIN[27][4]	MAIN[44][2]	MAIN[42][2]	MAIN[10][5]	MAIN[11][5]	CELL.LONG_IO_H[3]
						Source
0	0	1	1	1	1	CELL.LONG_V[5]
0	1	1	1	1	1	CELL.SINGLE_V[6]
1	1	0	0	1	1	CELL.LONG_V[9]
1	1	0	1	1	1	CELL.GCLK[7]
1	1	1	1	0	0	CELL.LONG_IO_V[1]
1	1	1	1	0	1	CELL.LONG_IO_V[3]
1	1	1	1	1	1	off

xc4000xv CNR_NE switchbox INT muxes LONG_IO_V[0]
Bits				Destination
MAIN[21][4]	MAIN[15][4]	MAIN[15][3]	MAIN[16][4]	CELL.LONG_IO_V[0]
				Source
0	0	0	1	CELL.LONG_H[0]
0	0	1	0	CELL.LONG_IO_H[2]
0	1	1	1	CELL.LONG_IO_H[0]
1	1	1	1	off

xc4000xv CNR_NE switchbox INT muxes LONG_IO_V[1]
Bits				Destination
MAIN[10][4]	MAIN[5][3]	MAIN[7][3]	MAIN[6][3]	CELL.LONG_IO_V[1]
				Source
0	0	0	1	CELL.LONG_H[1]
0	0	1	0	CELL.LONG_IO_H[3]
0	1	1	1	CELL.LONG_IO_H[1]
1	1	1	1	off

xc4000xv CNR_NE switchbox INT muxes LONG_IO_V[2]
Bits				Destination
MAIN[23][4]	MAIN[13][3]	MAIN[16][3]	MAIN[14][3]	CELL.LONG_IO_V[2]
				Source
0	0	0	1	CELL.LONG_H[2]
0	0	1	0	CELL.LONG_IO_H[0]
0	1	1	1	CELL.LONG_IO_H[2]
1	1	1	1	off

xc4000xv CNR_NE switchbox INT muxes LONG_IO_V[3]
Bits		Destination
MAIN[17][4]	MAIN[12][4]	CELL.LONG_IO_V[3]
		Source
0	0	CELL.LONG_IO_H[1]
0	1	CELL.LONG_IO_H[3]
1	1	off

xc4000xv CNR_NE switchbox INT muxes VCLK
Bits							Destination
MAIN[47][8]	MAIN[48][7]	MAIN[49][7]	MAIN[50][7]	MAIN[47][7]	MAIN[49][6]	MAIN[51][7]	CELL.VCLK
							Source
0	0	0	0	1	1	1	off
0	0	0	1	1	1	0	CELL.OUT_IO_SN_I1_E1
0	0	1	1	1	1	1	CELL.DOUBLE_IO_E1[1]
0	1	0	0	0	1	1	CELL.OUT_COUT_E
0	1	0	0	1	0	1	CELL.LONG_IO_H[0]
0	1	0	1	0	1	0	CELL.LONG_IO_H[3]
0	1	0	1	1	0	0	CELL.LONG_IO_H[1]
0	1	1	1	0	1	1	CELL.DOUBLE_IO_E1[2]
0	1	1	1	1	0	1	CELL.DOUBLE_IO_N0[0]
1	1	0	0	1	1	1	CELL.ECLK_H
1	1	0	1	1	1	0	CELL.BUFGE_H
1	1	1	1	1	1	1	CELL.DOUBLE_IO_N0[3]

xc4000xv CNR_NE switchbox INT muxes ECLK_H
Bits							Destination
MAIN[42][5]	MAIN[43][5]	MAIN[44][5]	MAIN[45][4]	MAIN[42][4]	MAIN[44][4]	MAIN[43][4]	CELL.ECLK_H
							Source
0	0	1	1	0	0	1	CELL.LONG_IO_H[1]
0	0	1	1	0	1	0	CELL.GCLK[5]
0	0	1	1	1	1	1	CELL.SINGLE_V[3]
0	1	0	1	0	0	1	CELL.OUT_BUFGE_V
0	1	0	1	0	1	0	CELL.GCLK[6]
0	1	0	1	1	1	1	CELL.SINGLE_V[4]
0	1	1	0	0	0	1	CELL.LONG_IO_H[3]
0	1	1	0	0	1	0	CELL.GCLK[7]
0	1	1	0	1	1	1	CELL.SINGLE_V[5]
1	1	1	1	0	0	1	CELL.LONG_IO_H[0]
1	1	1	1	0	1	0	CELL.GCLK[4]
1	1	1	1	1	1	1	CELL.SINGLE_V[2]

xc4000xv CNR_NE switchbox INT muxes IMUX_BUFG_H
Bits							Destination
MAIN[21][5]	MAIN[22][7]	MAIN[26][7]	MAIN[21][7]	MAIN[26][5]	MAIN[26][6]	MAIN[20][6]	CELL.IMUX_BUFG_H
							Source
0	0	0	0	1	1	1	CELL.DOUBLE_IO_E1[2]
0	0	0	1	1	1	1	CELL.DOUBLE_IO_E1[0]
0	0	1	0	0	1	1	CELL.DOUBLE_IO_E1[3]
0	0	1	0	1	0	1	CELL.DOUBLE_IO_E2[3]
0	0	1	1	0	1	1	CELL.DOUBLE_IO_E2[1]
0	0	1	1	1	0	1	CELL.DOUBLE_IO_E2[0]
0	1	1	1	1	1	0	CELL.OUT_IO_CLKIN_E
0	1	1	1	1	1	1	off
1	0	1	0	1	1	1	CELL.DOUBLE_IO_E1[1]
1	0	1	1	1	1	1	CELL.DOUBLE_IO_E2[2]

xc4000xv CNR_NE switchbox INT muxes IMUX_BUFG_V
Bits						Destination
MAIN[17][2]	MAIN[16][2]	MAIN[18][2]	MAIN[20][2]	MAIN[19][2]	MAIN[15][2]	CELL.IMUX_BUFG_V
						Source
0	0	0	1	1	1	CELL.OCTAL_IO_N[7]
0	0	1	0	1	1	CELL.LONG_IO_H[0]
0	0	1	1	0	1	CELL.LONG_IO_V[0]
0	1	1	1	1	0	CELL.OUT_IO_CLKIN_N
0	1	1	1	1	1	off
1	0	1	1	1	1	CELL.OCTAL_IO_N[0]

xc4000xv CNR_NE switchbox INT muxes IMUX_TDO_O
Bits						Destination
MAIN[31][3]	MAIN[32][3]	MAIN[33][3]	MAIN[34][3]	MAIN[35][3]	MAIN[30][3]	CELL.IMUX_TDO_O
						Source
0	0	1	1	1	0	CELL.LONG_H[0]
0	0	1	1	1	1	CELL.SINGLE_V[2]
0	1	0	1	1	1	CELL.SINGLE_V[3]
0	1	1	0	1	0	CELL.LONG_H[1]
0	1	1	0	1	1	CELL.SINGLE_V[4]
0	1	1	1	0	0	CELL.LONG_H[2]
0	1	1	1	0	1	CELL.SINGLE_V[5]
1	1	1	1	1	0	CELL_S.DOUBLE_H1[1]
1	1	1	1	1	1	CELL_S.DOUBLE_H0[0]

xc4000xv CNR_NE switchbox INT muxes IMUX_TDO_T
Bits						Destination
MAIN[29][2]	MAIN[30][2]	MAIN[32][2]	MAIN[33][2]	MAIN[34][2]	MAIN[31][2]	CELL.IMUX_TDO_T
						Source
0	0	0	1	1	1	CELL_S.SINGLE_H[3]
0	0	1	0	1	1	CELL.LONG_V[4]
0	0	1	1	0	1	CELL_S.SINGLE_H[2]
0	1	1	1	1	1	CELL.DOUBLE_V0[0]
1	0	0	1	1	1	CELL.DOUBLE_V1[1]
1	0	1	0	1	1	CELL.LONG_V[3]
1	0	1	1	0	1	CELL.LONG_V[5]
1	0	1	1	1	0	CELL_S.SINGLE_H[4]
1	1	1	1	1	1	CELL_S.SINGLE_H[5]

Bels PULLUP

xc4000xv CNR_NE bel PULLUP pins
Pin	Direction	PULLUP_DEC_H[0]	PULLUP_DEC_H[1]	PULLUP_DEC_H[2]	PULLUP_DEC_H[3]	PULLUP_DEC_V[0]	PULLUP_DEC_V[1]	PULLUP_DEC_V[2]	PULLUP_DEC_V[3]
O	bidir	CELL.DEC_H[0]	CELL.DEC_H[1]	CELL.DEC_H[2]	CELL.DEC_H[3]	CELL.DEC_V[0]	CELL.DEC_V[1]	CELL.DEC_V[2]	CELL.DEC_V[3]

xc4000xv CNR_NE bel PULLUP attribute bits
Attribute	PULLUP_DEC_H[0]	PULLUP_DEC_H[1]	PULLUP_DEC_H[2]	PULLUP_DEC_H[3]	PULLUP_DEC_V[0]	PULLUP_DEC_V[1]	PULLUP_DEC_V[2]	PULLUP_DEC_V[3]
ENABLE	!MAIN[40][4]	!MAIN[39][4]	!MAIN[38][4]	!MAIN[40][5]	!MAIN[8][3]	!MAIN[11][3]	!MAIN[9][3]	!MAIN[12][3]

Bels BUFG

xc4000xv CNR_NE bel BUFG pins
Pin	Direction	BUFG_H	BUFG_V
I	in	CELL.IMUX_BUFG_H	CELL.IMUX_BUFG_V
O	out	CELL.BUFGLS[6]	CELL.BUFGLS[5]
O_BUFGE	out	CELL.OUT_BUFGE_H	CELL.OUT_BUFGE_V

xc4000xv CNR_NE bel BUFG attribute bits
Attribute	BUFG_H	BUFG_V
CLK_EN	!MAIN[2][8]	!MAIN[8][2]
ALT_PAD	!MAIN[49][8]	!MAIN[51][8]

Bels UPDATE

xc4000xv CNR_NE bel UPDATE pins
Pin	Direction	UPDATE
O	out	CELL.OUT_UPDATE_O

Bels OSC

xc4000xv CNR_NE bel OSC pins
Pin	Direction	OSC
F8M	out	CELL.OUT_IO_WE_I1[1]
OUT0	out	CELL.OUT_IO_WE_I2[1]
OUT1	out	CELL.OUT_OSC_MUX1

Bels TDO

xc4000xv CNR_NE bel TDO pins
Pin	Direction	TDO
O	in	CELL.IMUX_TDO_O
T	in	CELL.IMUX_TDO_T

xc4000xv CNR_NE bel TDO attribute bits
Attribute	TDO
PULL	[enum: IO_PULL]
BSCAN_ENABLE	MAIN[17][5]
BSCAN_STATUS	!MAIN[3][8]
T_ENABLE	!MAIN[7][5]
O_ENABLE	!MAIN[8][5]

xc4000xv CNR_NE enum IO_PULL
TDO.PULL	MAIN[18][5]	MAIN[16][5]
NONE	1	1
PULLUP	0	1
PULLDOWN	1	0

Bels MISC_NE

xc4000xv CNR_NE bel MISC_NE pins
Pin	Direction	MISC_NE

xc4000xv CNR_NE bel MISC_NE attribute bits
Attribute	MISC_NE
TM_RIGHT	!MAIN[14][2]
TAC	!MAIN[15][5]
READCLK	[enum: RDBK_MUX_CLK]
ADDRESS_LINES	[enum: ADDRESS_LINES]

xc4000xv CNR_NE enum RDBK_MUX_CLK
MISC_NE.READCLK	MAIN[12][5]
CCLK	1
RDBK	0

xc4000xv CNR_NE enum ADDRESS_LINES
MISC_NE.ADDRESS_LINES	MAIN[1][8]
_18	1
_22	0

Bel wires

xc4000xv CNR_NE bel wires
Wire	Pins
CELL.DEC_H[0]	PULLUP_DEC_H[0].O
CELL.DEC_H[1]	PULLUP_DEC_H[1].O
CELL.DEC_H[2]	PULLUP_DEC_H[2].O
CELL.DEC_H[3]	PULLUP_DEC_H[3].O
CELL.DEC_V[0]	PULLUP_DEC_V[0].O
CELL.DEC_V[1]	PULLUP_DEC_V[1].O
CELL.DEC_V[2]	PULLUP_DEC_V[2].O
CELL.DEC_V[3]	PULLUP_DEC_V[3].O
CELL.BUFGLS[5]	BUFG_V.O
CELL.BUFGLS[6]	BUFG_H.O
CELL.IMUX_BUFG_H	BUFG_H.I
CELL.IMUX_BUFG_V	BUFG_V.I
CELL.IMUX_TDO_O	TDO.O
CELL.IMUX_TDO_T	TDO.T
CELL.OUT_IO_WE_I1[1]	OSC.F8M
CELL.OUT_IO_WE_I2[1]	OSC.OUT0
CELL.OUT_OSC_MUX1	OSC.OUT1
CELL.OUT_UPDATE_O	UPDATE.O
CELL.OUT_BUFGE_H	BUFG_H.O_BUFGE
CELL.OUT_BUFGE_V	BUFG_V.O_BUFGE

Bitstream

xc4000xv CNR_NE rect MAIN
Bit	Frame
Bit	F51	F50	F49	F48	F47	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B8	BUFG_V: ! ALT_PAD	INT: !pass CELL.DOUBLE_IO_E1[2] ← CELL.LONG_V[7]	BUFG_H: ! ALT_PAD	-	INT: mux CELL.VCLK bit 6	INT: !pass CELL.QUAD_V2[0] ← CELL.DEC_H[1]	-	INT: !bipass CELL.DOUBLE_IO_N0[2] = CELL.QUAD_V2[1]	INT: !pass CELL.QUAD_V0[1] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.DOUBLE_IO_N0[2] ← CELL.GCLK[6]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	TDO: ! BSCAN_STATUS	BUFG_H: ! CLK_EN	MISC_NE: ADDRESS_LINES bit 0	-
B7	INT: mux CELL.VCLK bit 0	INT: mux CELL.VCLK bit 3	INT: mux CELL.VCLK bit 4	INT: mux CELL.VCLK bit 5	INT: mux CELL.VCLK bit 2	INT: !bipass CELL.DOUBLE_IO_E1[0] = CELL.QUAD_V2[0]	INT: !bipass CELL.DOUBLE_IO_E1[2] = CELL.QUAD_V0[1]	INT: !bipass CELL.DOUBLE_IO_N0[3] = CELL.QUAD_V1[2]	INT: !bipass CELL.DOUBLE_IO_E1[3] = CELL.QUAD_V0[2]	-	-	INT: mux CELL.DBUF_IO_H[1] bit 0	INT: mux CELL.DBUF_IO_H[1] bit 1	INT: !bipass CELL.SINGLE_V[6] = CELL.DOUBLE_IO_E1[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_E2[3]	INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_E2[3]	INT: !pass CELL.DOUBLE_IO_N0[3] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_N0[2] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_N0[1] ← CELL.DBUF_IO_H[0]	INT: !pass CELL.DOUBLE_IO_N0[0] ← CELL.DBUF_IO_H[0]	INT: !bipass CELL.DOUBLE_IO_E2[2] = CELL.DOUBLE_IO_N0[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_E1[2]	INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_E2[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_E2[2]	INT: !bipass CELL.SINGLE_V[4] = CELL.DOUBLE_IO_E1[2]	INT: mux CELL.IMUX_BUFG_H bit 4	INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_E2[1]	INT: !bipass CELL.SINGLE_V[0] = CELL.DOUBLE_IO_E1[0]	INT: !pass CELL.DOUBLE_IO_E2[3] ← CELL.DBUF_IO_H[1]	INT: mux CELL.IMUX_BUFG_H bit 5	INT: mux CELL.IMUX_BUFG_H bit 3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	INT: !bipass CELL.DOUBLE_IO_N0[1] = CELL.QUAD_V0[0]	INT: !pass CELL.DOUBLE_IO_N0[0] ← CELL.LONG_V[9]	INT: mux CELL.VCLK bit 1	INT: !pass CELL.DOUBLE_IO_N0[3] ← CELL.LONG_V[6]	INT: !bipass CELL.DOUBLE_IO_E1[1] = CELL.QUAD_V1[1]	INT: !bipass CELL.DOUBLE_IO_N0[0] = CELL.QUAD_V1[0]	INT: !pass CELL.QUAD_V2[1] ← CELL.DEC_H[2]	INT: !pass CELL.DOUBLE_IO_E1[0] ← CELL.GCLK[4]	INT: !pass CELL.DOUBLE_IO_N0[1] ← CELL.GCLK[5]	INT: !pass CELL.DOUBLE_IO_E1[3] ← CELL.GCLK[7]	-	INT: mux CELL.DBUF_IO_H[1] bit 2	INT: mux CELL.DBUF_IO_H[1] bit 3	INT: !bipass CELL.SINGLE_V[7] = CELL.DOUBLE_IO_N0[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_N0[3]	INT: !bipass CELL.DOUBLE_IO_E2[3] = CELL.DOUBLE_IO_N0[3]	INT: !bipass CELL.DOUBLE_V1[1] = CELL.DOUBLE_IO_E1[3]	INT: !bipass CELL.SINGLE_V[5] = CELL.DOUBLE_IO_N0[2]	INT: !bipass CELL.DOUBLE_V0[1] = CELL.DOUBLE_IO_N0[2]	INT: !bipass CELL.SINGLE_V[3] = CELL.DOUBLE_IO_N0[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_N0[1]	INT: !bipass CELL.SINGLE_V[2] = CELL.DOUBLE_IO_E1[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_E2[1]	INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_N0[0]	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_N0[0]	INT: mux CELL.IMUX_BUFG_H bit 1	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_E2[0]	INT: !bipass CELL.SINGLE_V[1] = CELL.DOUBLE_IO_E2[0]	INT: !pass CELL.DOUBLE_IO_E2[0] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_E2[2] ← CELL.DBUF_IO_H[1]	INT: !pass CELL.DOUBLE_IO_E2[1] ← CELL.DBUF_IO_H[1]	INT: mux CELL.IMUX_BUFG_H bit 0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	INT: !bipass CELL.QUAD_V3[0] = CELL.LONG_IO_H[0]	INT: !pass CELL.DOUBLE_IO_E1[1] ← CELL.LONG_V[8]	-	-	-	-	INT: mux CELL.ECLK_H bit 4	INT: mux CELL.ECLK_H bit 5	INT: mux CELL.ECLK_H bit 6	-	PULLUP_DEC_H[3]: ! ENABLE	INT: mux CELL.LONG_IO_H[2] bit 5	INT: mux CELL.LONG_IO_H[2] bit 4	INT: mux CELL.LONG_IO_H[2] bit 7	INT: mux CELL.LONG_IO_H[3] bit 5	INT: mux CELL.LONG_IO_H[2] bit 6	INT: mux CELL.LONG_IO_H[1] bit 7	INT: mux CELL.LONG_IO_H[1] bit 5	INT: mux CELL.LONG_IO_H[1] bit 4	INT: mux CELL.LONG_IO_H[1] bit 6	INT: mux CELL.LONG_IO_H[0] bit 5	INT: mux CELL.LONG_IO_H[0] bit 4	INT: !bipass CELL.DOUBLE_IO_E2[1] = CELL.DOUBLE_IO_N0[1]	INT: !bipass CELL.DOUBLE_V0[0] = CELL.DOUBLE_IO_E1[1]	INT: mux CELL.IMUX_BUFG_H bit 2	INT: !bipass CELL.DOUBLE_V1[0] = CELL.DOUBLE_IO_E1[0]	INT: !bipass CELL.DOUBLE_IO_E2[0] = CELL.DOUBLE_IO_N0[0]	INT: mux CELL.LONG_IO_H[0] bit 1	INT: mux CELL.LONG_IO_H[0] bit 0	INT: mux CELL.IMUX_BUFG_H bit 6	INT: mux CELL.LONG_IO_H[2] bit 0	INT: mux CELL.LONG_IO_H[2] bit 1	TDO: PULL bit 1	TDO: BSCAN_ENABLE	TDO: PULL bit 0	MISC_NE: ! TAC	INT: mux CELL.LONG_IO_H[1] bit 1	INT: mux CELL.LONG_IO_H[1] bit 0	MISC_NE: READCLK bit 0	INT: mux CELL.LONG_IO_H[3] bit 0	INT: mux CELL.LONG_IO_H[3] bit 1	-	TDO: ! O_ENABLE	TDO: ! T_ENABLE	-	-	-	-	-	-	-
B4	INT: !bipass CELL.QUAD_V3[1] = CELL.LONG_IO_H[1]	INT: !bipass CELL.QUAD_V3[2] = CELL.LONG_IO_H[3]	INT: !pass CELL.QUAD_V3[2] ← CELL.OUT_IO_SN_I1_E1	-	-	-	INT: mux CELL.ECLK_H bit 3	INT: mux CELL.ECLK_H bit 1	INT: mux CELL.ECLK_H bit 0	INT: mux CELL.ECLK_H bit 2	-	PULLUP_DEC_H[0]: ! ENABLE	PULLUP_DEC_H[1]: ! ENABLE	PULLUP_DEC_H[2]: ! ENABLE	INT: !pass CELL.SINGLE_V[7] ← CELL.OUT_IO_SN_I1_E1	INT: mux CELL.LONG_V[5] bit 3	INT: !pass CELL.SINGLE_V[7] ← CELL.DEC_H[3]	INT: mux CELL.LONG_V[5] bit 1	INT: mux CELL.LONG_V[5] bit 0	INT: mux CELL.LONG_V[5] bit 2	INT: !pass CELL.SINGLE_V[3] ← CELL.OUT_IO_SN_I1_E1	INT: !pass CELL.DOUBLE_V0[1] ← CELL.OUT_OSC_MUX1	INT: !pass CELL.SINGLE_V[5] ← CELL.LONG_IO_H[2]	INT: !pass CELL.SINGLE_V[5] ← CELL.OUT_OSC_MUX1	INT: mux CELL.LONG_IO_H[3] bit 4	-	INT: mux CELL.LONG_V[0] bit 0	INT: mux CELL.LONG_V[0] bit 1	INT: mux CELL.LONG_IO_V[2] bit 3	INT: mux CELL.LONG_V[0] bit 2	INT: mux CELL.LONG_IO_V[0] bit 3	INT: mux CELL.LONG_V[0] bit 3	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_IO_H[1]	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_IO_H[0]	INT: mux CELL.LONG_IO_V[3] bit 1	INT: mux CELL.LONG_IO_V[0] bit 0	INT: mux CELL.LONG_IO_V[0] bit 2	INT: !pass CELL.SINGLE_V[0] ← CELL.DEC_H[0]	INT: !pass CELL.DOUBLE_V0[0] ← CELL.OUT_IO_SN_I1_E1	INT: mux CELL.LONG_IO_V[3] bit 0	INT: mux CELL.DBUF_IO_H[0] bit 2	INT: mux CELL.LONG_IO_V[1] bit 3	INT: mux CELL.DBUF_IO_H[0] bit 0	INT: mux CELL.DBUF_IO_H[0] bit 1	INT: mux CELL.DBUF_IO_H[0] bit 3	-	-	-	-	-	-	-
B3	INT: !pass CELL.QUAD_V2[2] ← CELL.DEC_H[3]	INT: !pass CELL.QUAD_V2[0] ← CELL.OUT_COUT_E	INT: mux CELL.LONG_IO_H[0] bit 2	INT: mux CELL.LONG_IO_H[0] bit 3	INT: mux CELL.LONG_V[6] bit 0	INT: mux CELL.LONG_V[7] bit 0	INT: mux CELL.LONG_IO_H[1] bit 3	INT: !pass CELL.QUAD_V3[0] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.LONG_IO_H[1] bit 2	INT: !pass CELL.QUAD_V0[2] ← CELL.OUT_IO_SN_I2_E1	-	INT: mux CELL.LONG_V[1] bit 0	INT: mux CELL.LONG_V[1] bit 3	INT: mux CELL.LONG_V[1] bit 1	INT: mux CELL.LONG_V[3] bit 0	INT: mux CELL.LONG_V[3] bit 3	INT: mux CELL.IMUX_TDO_O bit 1	INT: mux CELL.IMUX_TDO_O bit 2	INT: mux CELL.IMUX_TDO_O bit 3	INT: mux CELL.IMUX_TDO_O bit 4	INT: mux CELL.IMUX_TDO_O bit 5	INT: mux CELL.IMUX_TDO_O bit 0	INT: mux CELL.LONG_V[2] bit 3	INT: mux CELL.LONG_V[2] bit 1	INT: !pass CELL.SINGLE_V[0] ← CELL.OUT_IO_SN_I2_E1	-	INT: mux CELL.LONG_V[4] bit 3	INT: mux CELL.LONG_V[4] bit 0	INT: mux CELL.LONG_V[4] bit 1	INT: mux CELL.LONG_V[4] bit 2	INT: mux CELL.LONG_H[2] bit 1	INT: mux CELL.LONG_H[0] bit 0	INT: mux CELL.LONG_H[0] bit 2	INT: mux CELL.LONG_H[0] bit 3	-	INT: mux CELL.LONG_IO_V[2] bit 1	INT: mux CELL.LONG_IO_V[0] bit 1	INT: mux CELL.LONG_IO_V[2] bit 0	INT: mux CELL.LONG_IO_V[2] bit 2	PULLUP_DEC_V[3]: ! ENABLE	PULLUP_DEC_V[1]: ! ENABLE	INT: !pass CELL.SINGLE_V[6] ← CELL.LONG_IO_H[3]	PULLUP_DEC_V[2]: ! ENABLE	PULLUP_DEC_V[0]: ! ENABLE	INT: mux CELL.LONG_IO_V[1] bit 1	INT: mux CELL.LONG_IO_V[1] bit 0	INT: mux CELL.LONG_IO_V[1] bit 2	-	-	-	-	-
B2	-	-	INT: mux CELL.LONG_IO_H[2] bit 2	INT: mux CELL.LONG_IO_H[2] bit 3	INT: mux CELL.LONG_V[8] bit 0	-	-	INT: mux CELL.LONG_IO_H[3] bit 3	INT: mux CELL.LONG_V[9] bit 0	INT: mux CELL.LONG_IO_H[3] bit 2	INT: !pass CELL.SINGLE_V[4] ← CELL.OUT_IO_SN_I2_E1	INT: !pass CELL.SINGLE_V[4] ← CELL.DEC_H[2]	INT: !pass CELL.DOUBLE_V1[1] ← CELL.OUT_IO_SN_I2_E1	INT: mux CELL.LONG_V[1] bit 2	INT: !pass CELL.SINGLE_V[3] ← CELL.DEC_H[1]	INT: mux CELL.LONG_V[3] bit 1	INT: mux CELL.LONG_V[3] bit 2	INT: mux CELL.IMUX_TDO_T bit 1	INT: mux CELL.IMUX_TDO_T bit 2	INT: mux CELL.IMUX_TDO_T bit 3	INT: mux CELL.IMUX_TDO_T bit 0	INT: mux CELL.IMUX_TDO_T bit 4	INT: mux CELL.IMUX_TDO_T bit 5	INT: !pass CELL.SINGLE_V[1] ← CELL.OUT_OSC_MUX1	INT: mux CELL.LONG_V[2] bit 0	-	INT: mux CELL.LONG_V[2] bit 2	INT: !buffer CELL.LONG_H[2] ← CELL.SINGLE_V[3]	-	INT: mux CELL.LONG_H[2] bit 0	INT: mux CELL.LONG_H[0] bit 1	INT: mux CELL.IMUX_BUFG_V bit 2	INT: mux CELL.IMUX_BUFG_V bit 1	INT: mux CELL.IMUX_BUFG_V bit 3	INT: mux CELL.IMUX_BUFG_V bit 5	INT: mux CELL.IMUX_BUFG_V bit 4	INT: mux CELL.IMUX_BUFG_V bit 0	MISC_NE: ! TM_RIGHT	INT: !pass CELL.DOUBLE_V1[0] ← CELL.OUT_UPDATE_O	INT: !pass CELL.SINGLE_V[2] ← CELL.OUT_UPDATE_O	INT: !pass CELL.SINGLE_V[6] ← CELL.OUT_UPDATE_O	INT: mux CELL.LONG_H[1] bit 3	INT: mux CELL.LONG_H[1] bit 1	BUFG_V: ! CLK_EN	INT: mux CELL.LONG_H[1] bit 0	INT: mux CELL.LONG_H[1] bit 2	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

xc4000xv CNR_NE rect MAIN_S
Bit	Frame
Bit	F51	F50	F49	F48	F47	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[3] ← CELL.LONG_H[2]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	INT: !pass CELL.SINGLE_V[2] ← CELL.LONG_H[1]	-	-	-	INT: !buffer CELL.LONG_H[1] ← CELL.SINGLE_V[2]	-	INT: !pass CELL.SINGLE_V[1] ← CELL.LONG_H[0]	-	INT: !buffer CELL.LONG_H[0] ← CELL.SINGLE_V[1]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

xc4000xv CNR_NE rect MAIN_W
Bit	Frame
Bit	F46	F45	F44	F43	F42	F41	F40	F39	F38	F37	F36	F35	F34	F33	F32	F31	F30	F29	F28	F27	F26	F25	F24	F23	F22	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

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