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Splitters

Tile LLHC.CLB

Cells: 2 IRIs: 0

Muxes

xc4000xv LLHC.CLB muxes
DestinationSources
TCELL0:LONG.H0TCELL1:LONG.H0
TCELL0:LONG.H1TCELL1:LONG.H1
TCELL0:LONG.H4TCELL1:LONG.H4
TCELL0:LONG.H5TCELL1:LONG.H5
TCELL1:LONG.H0TCELL0:LONG.H0
TCELL1:LONG.H1TCELL0:LONG.H1
TCELL1:LONG.H4TCELL0:LONG.H4
TCELL1:LONG.H5TCELL0:LONG.H5

Bel PULLUP_TBUF0_W

xc4000xv LLHC.CLB bel PULLUP_TBUF0_W
PinDirectionWires
OoutputTCELL0:LONG.H2

Bel PULLUP_TBUF1_W

xc4000xv LLHC.CLB bel PULLUP_TBUF1_W
PinDirectionWires
OoutputTCELL0:LONG.H3

Bel PULLUP_TBUF0_E

xc4000xv LLHC.CLB bel PULLUP_TBUF0_E
PinDirectionWires
OoutputTCELL1:LONG.H2

Bel PULLUP_TBUF1_E

xc4000xv LLHC.CLB bel PULLUP_TBUF1_E
PinDirectionWires
OoutputTCELL1:LONG.H3

Bel TBUF_SPLITTER0

xc4000xv LLHC.CLB bel TBUF_SPLITTER0
PinDirectionWires
Lin-outTCELL0:LONG.H2
Rin-outTCELL1:LONG.H2

Bel TBUF_SPLITTER1

xc4000xv LLHC.CLB bel TBUF_SPLITTER1
PinDirectionWires
Lin-outTCELL0:LONG.H3
Rin-outTCELL1:LONG.H3

Bel wires

xc4000xv LLHC.CLB bel wires
WirePins
TCELL0:LONG.H2PULLUP_TBUF0_W.O, TBUF_SPLITTER0.L
TCELL0:LONG.H3PULLUP_TBUF1_W.O, TBUF_SPLITTER1.L
TCELL1:LONG.H2PULLUP_TBUF0_E.O, TBUF_SPLITTER0.R
TCELL1:LONG.H3PULLUP_TBUF1_E.O, TBUF_SPLITTER1.R

Bitstream

INT:BUF.0.LONG.H0.1.LONG.H0 1.0.6
INT:BUF.0.LONG.H1.1.LONG.H1 1.0.4
INT:BUF.0.LONG.H4.1.LONG.H4 0.0.1
INT:BUF.0.LONG.H5.1.LONG.H5 0.0.3
INT:BUF.1.LONG.H0.0.LONG.H0 1.0.5
INT:BUF.1.LONG.H1.0.LONG.H1 1.0.7
INT:BUF.1.LONG.H4.0.LONG.H4 0.0.0
INT:BUF.1.LONG.H5.0.LONG.H5 0.0.2
PULLUP_TBUF0_E:ENABLE 1.0.9
PULLUP_TBUF0_W:ENABLE 1.1.4
PULLUP_TBUF1_E:ENABLE 0.1.7
PULLUP_TBUF1_W:ENABLE 0.1.10
TBUF_SPLITTER0:BUF_E 1.1.8
TBUF_SPLITTER0:BUF_W 1.1.9
TBUF_SPLITTER0:PASS 1.1.6
TBUF_SPLITTER1:BUF_E 0.0.10
TBUF_SPLITTER1:BUF_W 0.0.11
TBUF_SPLITTER1:PASS 0.1.5
inverted ~[0]

Tile LLHC.CLB.B

Cells: 2 IRIs: 0

Muxes

xc4000xv LLHC.CLB.B muxes
DestinationSources
TCELL0:LONG.H0TCELL1:LONG.H0
TCELL0:LONG.H1TCELL1:LONG.H1
TCELL0:LONG.H4TCELL1:LONG.H4
TCELL0:LONG.H5TCELL1:LONG.H5
TCELL1:LONG.H0TCELL0:LONG.H0
TCELL1:LONG.H1TCELL0:LONG.H1
TCELL1:LONG.H4TCELL0:LONG.H4
TCELL1:LONG.H5TCELL0:LONG.H5

Bel PULLUP_TBUF0_W

xc4000xv LLHC.CLB.B bel PULLUP_TBUF0_W
PinDirectionWires
OoutputTCELL0:LONG.H2

Bel PULLUP_TBUF1_W

xc4000xv LLHC.CLB.B bel PULLUP_TBUF1_W
PinDirectionWires
OoutputTCELL0:LONG.H3

Bel PULLUP_TBUF0_E

xc4000xv LLHC.CLB.B bel PULLUP_TBUF0_E
PinDirectionWires
OoutputTCELL1:LONG.H2

Bel PULLUP_TBUF1_E

xc4000xv LLHC.CLB.B bel PULLUP_TBUF1_E
PinDirectionWires
OoutputTCELL1:LONG.H3

Bel TBUF_SPLITTER0

xc4000xv LLHC.CLB.B bel TBUF_SPLITTER0
PinDirectionWires
Lin-outTCELL0:LONG.H2
Rin-outTCELL1:LONG.H2

Bel TBUF_SPLITTER1

xc4000xv LLHC.CLB.B bel TBUF_SPLITTER1
PinDirectionWires
Lin-outTCELL0:LONG.H3
Rin-outTCELL1:LONG.H3

Bel wires

xc4000xv LLHC.CLB.B bel wires
WirePins
TCELL0:LONG.H2PULLUP_TBUF0_W.O, TBUF_SPLITTER0.L
TCELL0:LONG.H3PULLUP_TBUF1_W.O, TBUF_SPLITTER1.L
TCELL1:LONG.H2PULLUP_TBUF0_E.O, TBUF_SPLITTER0.R
TCELL1:LONG.H3PULLUP_TBUF1_E.O, TBUF_SPLITTER1.R

Bitstream

xc4000xv LLHC.CLB.B bittile 1
BitFrame
1 0
15 ~INT:BUF.1.LONG.H0.0.LONG.H0 ~INT:BUF.0.LONG.H0.1.LONG.H0
14 ~INT:BUF.1.LONG.H1.0.LONG.H1 ~TBUF_SPLITTER0:PASS
13 - ~INT:BUF.0.LONG.H1.1.LONG.H1
12 - ~PULLUP_TBUF0_E:ENABLE
11 ~TBUF_SPLITTER0:BUF_E ~TBUF_SPLITTER0:BUF_W
10 - -
9 - -
8 - -
7 - -
6 - -
5 - -
4 - -
3 - -
2 - -
1 - -
0 - -
xc4000xv LLHC.CLB.B bittile 2
BitFrame
0
12 ~PULLUP_TBUF0_W:ENABLE
11 -
10 -
9 -
8 -
7 -
6 -
5 -
4 -
3 -
2 -
1 -
0 -
INT:BUF.0.LONG.H0.1.LONG.H0 1.0.15
INT:BUF.0.LONG.H1.1.LONG.H1 1.0.13
INT:BUF.0.LONG.H4.1.LONG.H4 0.0.1
INT:BUF.0.LONG.H5.1.LONG.H5 0.0.3
INT:BUF.1.LONG.H0.0.LONG.H0 1.1.15
INT:BUF.1.LONG.H1.0.LONG.H1 1.1.14
INT:BUF.1.LONG.H4.0.LONG.H4 0.0.0
INT:BUF.1.LONG.H5.0.LONG.H5 0.0.2
PULLUP_TBUF0_E:ENABLE 1.0.12
PULLUP_TBUF0_W:ENABLE 2.0.12
PULLUP_TBUF1_E:ENABLE 0.1.7
PULLUP_TBUF1_W:ENABLE 0.1.10
TBUF_SPLITTER0:BUF_E 1.1.11
TBUF_SPLITTER0:BUF_W 1.0.11
TBUF_SPLITTER0:PASS 1.0.14
TBUF_SPLITTER1:BUF_E 0.0.10
TBUF_SPLITTER1:BUF_W 0.0.11
TBUF_SPLITTER1:PASS 0.1.5
inverted ~[0]

Tile LLHC.IO.B

Cells: 2 IRIs: 0

Muxes

xc4000xv LLHC.IO.B muxes
DestinationSources
TCELL0:LONG.H3TCELL1:LONG.H3
TCELL0:LONG.H4TCELL1:LONG.H4
TCELL0:LONG.H5TCELL1:LONG.H5
TCELL0:LONG.IO.H0TCELL1:LONG.IO.H0
TCELL0:LONG.IO.H1TCELL1:LONG.IO.H1
TCELL0:LONG.IO.H2TCELL1:LONG.IO.H2
TCELL0:LONG.IO.H3TCELL1:LONG.IO.H3
TCELL0:DEC.H0TCELL1:DEC.H0
TCELL0:DEC.H1TCELL1:DEC.H1
TCELL0:DEC.H2TCELL1:DEC.H2
TCELL0:DEC.H3TCELL1:DEC.H3
TCELL1:LONG.H3TCELL0:LONG.H3
TCELL1:LONG.H4TCELL0:LONG.H4
TCELL1:LONG.H5TCELL0:LONG.H5
TCELL1:LONG.IO.H0TCELL0:LONG.IO.H0
TCELL1:LONG.IO.H1TCELL0:LONG.IO.H1
TCELL1:LONG.IO.H2TCELL0:LONG.IO.H2
TCELL1:LONG.IO.H3TCELL0:LONG.IO.H3
TCELL1:DEC.H0TCELL0:DEC.H0
TCELL1:DEC.H1TCELL0:DEC.H1
TCELL1:DEC.H2TCELL0:DEC.H2
TCELL1:DEC.H3TCELL0:DEC.H3

Bel PULLUP_DEC0_W

xc4000xv LLHC.IO.B bel PULLUP_DEC0_W
PinDirectionWires
OoutputTCELL0:DEC.H0

Bel PULLUP_DEC1_W

xc4000xv LLHC.IO.B bel PULLUP_DEC1_W
PinDirectionWires
OoutputTCELL0:DEC.H1

Bel PULLUP_DEC2_W

xc4000xv LLHC.IO.B bel PULLUP_DEC2_W
PinDirectionWires
OoutputTCELL0:DEC.H2

Bel PULLUP_DEC3_W

xc4000xv LLHC.IO.B bel PULLUP_DEC3_W
PinDirectionWires
OoutputTCELL0:DEC.H3

Bel PULLUP_DEC0_E

xc4000xv LLHC.IO.B bel PULLUP_DEC0_E
PinDirectionWires
OoutputTCELL1:DEC.H0

Bel PULLUP_DEC1_E

xc4000xv LLHC.IO.B bel PULLUP_DEC1_E
PinDirectionWires
OoutputTCELL1:DEC.H1

Bel PULLUP_DEC2_E

xc4000xv LLHC.IO.B bel PULLUP_DEC2_E
PinDirectionWires
OoutputTCELL1:DEC.H2

Bel PULLUP_DEC3_E

xc4000xv LLHC.IO.B bel PULLUP_DEC3_E
PinDirectionWires
OoutputTCELL1:DEC.H3

Bel wires

xc4000xv LLHC.IO.B bel wires
WirePins
TCELL0:DEC.H0PULLUP_DEC0_W.O
TCELL0:DEC.H1PULLUP_DEC1_W.O
TCELL0:DEC.H2PULLUP_DEC2_W.O
TCELL0:DEC.H3PULLUP_DEC3_W.O
TCELL1:DEC.H0PULLUP_DEC0_E.O
TCELL1:DEC.H1PULLUP_DEC1_E.O
TCELL1:DEC.H2PULLUP_DEC2_E.O
TCELL1:DEC.H3PULLUP_DEC3_E.O

Bitstream

INT:BIPASS.0.DEC.H0.1.DEC.H0 1.0.10
INT:BIPASS.0.DEC.H1.1.DEC.H1 0.0.10
INT:BIPASS.0.DEC.H2.1.DEC.H2 0.0.4
INT:BIPASS.0.DEC.H3.1.DEC.H3 0.1.4
INT:BUF.0.LONG.H3.1.LONG.H3 0.0.8
INT:BUF.0.LONG.H4.1.LONG.H4 0.0.5
INT:BUF.0.LONG.H5.1.LONG.H5 0.0.3
INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0 0.0.7
INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1 1.0.4
INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2 1.0.2
INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3 0.0.0
INT:BUF.1.LONG.H3.0.LONG.H3 0.1.9
INT:BUF.1.LONG.H4.0.LONG.H4 0.1.5
INT:BUF.1.LONG.H5.0.LONG.H5 0.1.3
INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0 0.1.6
INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1 0.1.7
INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2 0.1.2
INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3 0.1.1
PULLUP_DEC0_E:ENABLE 1.0.14
PULLUP_DEC0_W:ENABLE 1.0.13
PULLUP_DEC1_E:ENABLE 0.1.13
PULLUP_DEC1_W:ENABLE 1.0.15
PULLUP_DEC2_E:ENABLE 0.1.10
PULLUP_DEC2_W:ENABLE 0.1.12
PULLUP_DEC3_E:ENABLE 0.0.1
PULLUP_DEC3_W:ENABLE 0.1.0
inverted ~[0]

Tile LLHC.IO.T

Cells: 2 IRIs: 0

Muxes

xc4000xv LLHC.IO.T muxes
DestinationSources
TCELL0:LONG.H0TCELL1:LONG.H0
TCELL0:LONG.H1TCELL1:LONG.H1
TCELL0:LONG.H2TCELL1:LONG.H2
TCELL0:LONG.IO.H0TCELL1:LONG.IO.H0
TCELL0:LONG.IO.H1TCELL1:LONG.IO.H1
TCELL0:LONG.IO.H2TCELL1:LONG.IO.H2
TCELL0:LONG.IO.H3TCELL1:LONG.IO.H3
TCELL0:DEC.H0TCELL1:DEC.H0
TCELL0:DEC.H1TCELL1:DEC.H1
TCELL0:DEC.H2TCELL1:DEC.H2
TCELL0:DEC.H3TCELL1:DEC.H3
TCELL1:LONG.H0TCELL0:LONG.H0
TCELL1:LONG.H1TCELL0:LONG.H1
TCELL1:LONG.H2TCELL0:LONG.H2
TCELL1:LONG.IO.H0TCELL0:LONG.IO.H0
TCELL1:LONG.IO.H1TCELL0:LONG.IO.H1
TCELL1:LONG.IO.H2TCELL0:LONG.IO.H2
TCELL1:LONG.IO.H3TCELL0:LONG.IO.H3
TCELL1:DEC.H0TCELL0:DEC.H0
TCELL1:DEC.H1TCELL0:DEC.H1
TCELL1:DEC.H2TCELL0:DEC.H2
TCELL1:DEC.H3TCELL0:DEC.H3

Bel PULLUP_DEC0_W

xc4000xv LLHC.IO.T bel PULLUP_DEC0_W
PinDirectionWires
OoutputTCELL0:DEC.H0

Bel PULLUP_DEC1_W

xc4000xv LLHC.IO.T bel PULLUP_DEC1_W
PinDirectionWires
OoutputTCELL0:DEC.H1

Bel PULLUP_DEC2_W

xc4000xv LLHC.IO.T bel PULLUP_DEC2_W
PinDirectionWires
OoutputTCELL0:DEC.H2

Bel PULLUP_DEC3_W

xc4000xv LLHC.IO.T bel PULLUP_DEC3_W
PinDirectionWires
OoutputTCELL0:DEC.H3

Bel PULLUP_DEC0_E

xc4000xv LLHC.IO.T bel PULLUP_DEC0_E
PinDirectionWires
OoutputTCELL1:DEC.H0

Bel PULLUP_DEC1_E

xc4000xv LLHC.IO.T bel PULLUP_DEC1_E
PinDirectionWires
OoutputTCELL1:DEC.H1

Bel PULLUP_DEC2_E

xc4000xv LLHC.IO.T bel PULLUP_DEC2_E
PinDirectionWires
OoutputTCELL1:DEC.H2

Bel PULLUP_DEC3_E

xc4000xv LLHC.IO.T bel PULLUP_DEC3_E
PinDirectionWires
OoutputTCELL1:DEC.H3

Bel wires

xc4000xv LLHC.IO.T bel wires
WirePins
TCELL0:DEC.H0PULLUP_DEC0_W.O
TCELL0:DEC.H1PULLUP_DEC1_W.O
TCELL0:DEC.H2PULLUP_DEC2_W.O
TCELL0:DEC.H3PULLUP_DEC3_W.O
TCELL1:DEC.H0PULLUP_DEC0_E.O
TCELL1:DEC.H1PULLUP_DEC1_E.O
TCELL1:DEC.H2PULLUP_DEC2_E.O
TCELL1:DEC.H3PULLUP_DEC3_E.O

Bitstream

INT:BIPASS.0.DEC.H0.1.DEC.H0 2.0.4
INT:BIPASS.0.DEC.H1.1.DEC.H1 2.0.6
INT:BIPASS.0.DEC.H2.1.DEC.H2 2.0.8
INT:BIPASS.0.DEC.H3.1.DEC.H3 2.0.3
INT:BUF.0.LONG.H0.1.LONG.H0 1.0.6
INT:BUF.0.LONG.H1.1.LONG.H1 1.0.4
INT:BUF.0.LONG.H2.1.LONG.H2 1.1.9
INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0 2.0.1
INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1 0.1.2
INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2 0.1.5
INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3 0.1.6
INT:BUF.1.LONG.H0.0.LONG.H0 1.0.5
INT:BUF.1.LONG.H1.0.LONG.H1 1.0.7
INT:BUF.1.LONG.H2.0.LONG.H2 1.1.8
INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0 2.0.2
INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1 0.0.2
INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2 0.0.5
INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3 0.0.6
PULLUP_DEC0_E:ENABLE 0.1.3
PULLUP_DEC0_W:ENABLE 0.0.3
PULLUP_DEC1_E:ENABLE 0.1.7
PULLUP_DEC1_W:ENABLE 0.0.7
PULLUP_DEC2_E:ENABLE 0.0.4
PULLUP_DEC2_W:ENABLE 0.1.4
PULLUP_DEC3_E:ENABLE 0.0.1
PULLUP_DEC3_W:ENABLE 0.1.1
inverted ~[0]

Tile LLHQ.CLB

Cells: 2 IRIs: 0

Muxes

xc4000xv LLHQ.CLB muxes
DestinationSources
TCELL0:LONG.H0TCELL1:LONG.H0
TCELL0:LONG.H1TCELL1:LONG.H1
TCELL0:LONG.H4TCELL1:LONG.H4
TCELL0:LONG.H5TCELL1:LONG.H5
TCELL1:LONG.H0TCELL0:LONG.H0
TCELL1:LONG.H1TCELL0:LONG.H1
TCELL1:LONG.H4TCELL0:LONG.H4
TCELL1:LONG.H5TCELL0:LONG.H5

Bel PULLUP_TBUF0_W

xc4000xv LLHQ.CLB bel PULLUP_TBUF0_W
PinDirectionWires
OoutputTCELL0:LONG.H2

Bel PULLUP_TBUF1_W

xc4000xv LLHQ.CLB bel PULLUP_TBUF1_W
PinDirectionWires
OoutputTCELL0:LONG.H3

Bel PULLUP_TBUF0_E

xc4000xv LLHQ.CLB bel PULLUP_TBUF0_E
PinDirectionWires
OoutputTCELL0:LONG.H2

Bel PULLUP_TBUF1_E

xc4000xv LLHQ.CLB bel PULLUP_TBUF1_E
PinDirectionWires
OoutputTCELL0:LONG.H3

Bel wires

xc4000xv LLHQ.CLB bel wires
WirePins
TCELL0:LONG.H2PULLUP_TBUF0_W.O, PULLUP_TBUF0_E.O
TCELL0:LONG.H3PULLUP_TBUF1_W.O, PULLUP_TBUF1_E.O

Bitstream

INT:BUF.0.LONG.H0.1.LONG.H0 1.0.10
INT:BUF.0.LONG.H1.1.LONG.H1 1.0.8
INT:BUF.0.LONG.H4.1.LONG.H4 0.0.3
INT:BUF.0.LONG.H5.1.LONG.H5 0.0.0
INT:BUF.1.LONG.H0.0.LONG.H0 1.0.11
INT:BUF.1.LONG.H1.0.LONG.H1 1.0.9
INT:BUF.1.LONG.H4.0.LONG.H4 0.0.2
INT:BUF.1.LONG.H5.0.LONG.H5 0.0.1
PULLUP_TBUF0_E:ENABLE 1.0.7
PULLUP_TBUF0_W:ENABLE 1.0.6
PULLUP_TBUF1_E:ENABLE 0.0.5
PULLUP_TBUF1_W:ENABLE 0.0.4
inverted ~[0]

Tile LLHQ.CLB.B

Cells: 2 IRIs: 0

Muxes

xc4000xv LLHQ.CLB.B muxes
DestinationSources
TCELL0:LONG.H0TCELL1:LONG.H0
TCELL0:LONG.H1TCELL1:LONG.H1
TCELL0:LONG.H4TCELL1:LONG.H4
TCELL0:LONG.H5TCELL1:LONG.H5
TCELL1:LONG.H0TCELL0:LONG.H0
TCELL1:LONG.H1TCELL0:LONG.H1
TCELL1:LONG.H4TCELL0:LONG.H4
TCELL1:LONG.H5TCELL0:LONG.H5

Bel PULLUP_TBUF0_W

xc4000xv LLHQ.CLB.B bel PULLUP_TBUF0_W
PinDirectionWires
OoutputTCELL0:LONG.H2

Bel PULLUP_TBUF1_W

xc4000xv LLHQ.CLB.B bel PULLUP_TBUF1_W
PinDirectionWires
OoutputTCELL0:LONG.H3

Bel PULLUP_TBUF0_E

xc4000xv LLHQ.CLB.B bel PULLUP_TBUF0_E
PinDirectionWires
OoutputTCELL0:LONG.H2

Bel PULLUP_TBUF1_E

xc4000xv LLHQ.CLB.B bel PULLUP_TBUF1_E
PinDirectionWires
OoutputTCELL0:LONG.H3

Bel wires

xc4000xv LLHQ.CLB.B bel wires
WirePins
TCELL0:LONG.H2PULLUP_TBUF0_W.O, PULLUP_TBUF0_E.O
TCELL0:LONG.H3PULLUP_TBUF1_W.O, PULLUP_TBUF1_E.O

Bitstream

xc4000xv LLHQ.CLB.B bittile 1
BitFrame
xc4000xv LLHQ.CLB.B bittile 2
BitFrame
0
15 ~PULLUP_TBUF0_E:ENABLE
14 ~PULLUP_TBUF0_W:ENABLE
13 ~INT:BUF.0.LONG.H0.1.LONG.H0
12 ~INT:BUF.1.LONG.H0.0.LONG.H0
11 ~INT:BUF.0.LONG.H1.1.LONG.H1
10 ~INT:BUF.1.LONG.H1.0.LONG.H1
9 -
8 -
7 -
6 -
5 -
4 -
3 -
2 -
1 -
0 -
INT:BUF.0.LONG.H0.1.LONG.H0 2.0.13
INT:BUF.0.LONG.H1.1.LONG.H1 2.0.11
INT:BUF.0.LONG.H4.1.LONG.H4 0.0.3
INT:BUF.0.LONG.H5.1.LONG.H5 0.0.0
INT:BUF.1.LONG.H0.0.LONG.H0 2.0.12
INT:BUF.1.LONG.H1.0.LONG.H1 2.0.10
INT:BUF.1.LONG.H4.0.LONG.H4 0.0.2
INT:BUF.1.LONG.H5.0.LONG.H5 0.0.1
PULLUP_TBUF0_E:ENABLE 2.0.15
PULLUP_TBUF0_W:ENABLE 2.0.14
PULLUP_TBUF1_E:ENABLE 0.0.5
PULLUP_TBUF1_W:ENABLE 0.0.4
inverted ~[0]

Tile LLHQ.CLB.T

Cells: 2 IRIs: 0

Muxes

xc4000xv LLHQ.CLB.T muxes
DestinationSources
TCELL0:LONG.H0TCELL1:LONG.H0
TCELL0:LONG.H1TCELL1:LONG.H1
TCELL0:LONG.H4TCELL1:LONG.H4
TCELL0:LONG.H5TCELL1:LONG.H5
TCELL1:LONG.H0TCELL0:LONG.H0
TCELL1:LONG.H1TCELL0:LONG.H1
TCELL1:LONG.H4TCELL0:LONG.H4
TCELL1:LONG.H5TCELL0:LONG.H5

Bel PULLUP_TBUF0_W

xc4000xv LLHQ.CLB.T bel PULLUP_TBUF0_W
PinDirectionWires
OoutputTCELL0:LONG.H2

Bel PULLUP_TBUF1_W

xc4000xv LLHQ.CLB.T bel PULLUP_TBUF1_W
PinDirectionWires
OoutputTCELL0:LONG.H3

Bel PULLUP_TBUF0_E

xc4000xv LLHQ.CLB.T bel PULLUP_TBUF0_E
PinDirectionWires
OoutputTCELL0:LONG.H2

Bel PULLUP_TBUF1_E

xc4000xv LLHQ.CLB.T bel PULLUP_TBUF1_E
PinDirectionWires
OoutputTCELL0:LONG.H3

Bel wires

xc4000xv LLHQ.CLB.T bel wires
WirePins
TCELL0:LONG.H2PULLUP_TBUF0_W.O, PULLUP_TBUF0_E.O
TCELL0:LONG.H3PULLUP_TBUF1_W.O, PULLUP_TBUF1_E.O

Bitstream

INT:BUF.0.LONG.H0.1.LONG.H0 1.0.10
INT:BUF.0.LONG.H1.1.LONG.H1 1.0.8
INT:BUF.0.LONG.H4.1.LONG.H4 0.0.3
INT:BUF.0.LONG.H5.1.LONG.H5 0.0.0
INT:BUF.1.LONG.H0.0.LONG.H0 1.0.11
INT:BUF.1.LONG.H1.0.LONG.H1 1.0.9
INT:BUF.1.LONG.H4.0.LONG.H4 0.0.2
INT:BUF.1.LONG.H5.0.LONG.H5 0.0.1
PULLUP_TBUF0_E:ENABLE 1.0.7
PULLUP_TBUF0_W:ENABLE 1.0.6
PULLUP_TBUF1_E:ENABLE 0.0.5
PULLUP_TBUF1_W:ENABLE 0.0.4
inverted ~[0]

Tile LLHQ.IO.B

Cells: 2 IRIs: 0

Muxes

xc4000xv LLHQ.IO.B muxes
DestinationSources
TCELL0:LONG.H3TCELL1:LONG.H3
TCELL0:LONG.H4TCELL1:LONG.H4
TCELL0:LONG.H5TCELL1:LONG.H5
TCELL0:LONG.IO.H0TCELL1:LONG.IO.H0
TCELL0:LONG.IO.H1TCELL1:LONG.IO.H1
TCELL0:LONG.IO.H2TCELL1:LONG.IO.H2
TCELL0:LONG.IO.H3TCELL1:LONG.IO.H3
TCELL1:LONG.H3TCELL0:LONG.H3
TCELL1:LONG.H4TCELL0:LONG.H4
TCELL1:LONG.H5TCELL0:LONG.H5
TCELL1:LONG.IO.H0TCELL0:LONG.IO.H0
TCELL1:LONG.IO.H1TCELL0:LONG.IO.H1
TCELL1:LONG.IO.H2TCELL0:LONG.IO.H2
TCELL1:LONG.IO.H3TCELL0:LONG.IO.H3

Bitstream

INT:BUF.0.LONG.H3.1.LONG.H3 0.0.11
INT:BUF.0.LONG.H4.1.LONG.H4 1.0.6
INT:BUF.0.LONG.H5.1.LONG.H5 0.0.6
INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0 1.0.4
INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1 0.0.4
INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2 1.0.0
INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3 0.0.0
INT:BUF.1.LONG.H3.0.LONG.H3 0.0.10
INT:BUF.1.LONG.H4.0.LONG.H4 1.0.7
INT:BUF.1.LONG.H5.0.LONG.H5 0.0.7
INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0 1.0.5
INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1 0.0.5
INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2 1.0.1
INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3 0.0.1
inverted ~[0]

Tile LLHQ.IO.T

Cells: 2 IRIs: 0

Muxes

xc4000xv LLHQ.IO.T muxes
DestinationSources
TCELL0:LONG.H0TCELL1:LONG.H0
TCELL0:LONG.H1TCELL1:LONG.H1
TCELL0:LONG.H2TCELL1:LONG.H2
TCELL0:LONG.IO.H0TCELL1:LONG.IO.H0
TCELL0:LONG.IO.H1TCELL1:LONG.IO.H1
TCELL0:LONG.IO.H2TCELL1:LONG.IO.H2
TCELL0:LONG.IO.H3TCELL1:LONG.IO.H3
TCELL1:LONG.H0TCELL0:LONG.H0
TCELL1:LONG.H1TCELL0:LONG.H1
TCELL1:LONG.H2TCELL0:LONG.H2
TCELL1:LONG.IO.H0TCELL0:LONG.IO.H0
TCELL1:LONG.IO.H1TCELL0:LONG.IO.H1
TCELL1:LONG.IO.H2TCELL0:LONG.IO.H2
TCELL1:LONG.IO.H3TCELL0:LONG.IO.H3

Bitstream

INT:BUF.0.LONG.H0.1.LONG.H0 1.0.10
INT:BUF.0.LONG.H1.1.LONG.H1 1.0.8
INT:BUF.0.LONG.H2.1.LONG.H2 1.0.6
INT:BUF.0.LONG.IO.H0.1.LONG.IO.H0 0.0.2
INT:BUF.0.LONG.IO.H1.1.LONG.IO.H1 0.0.4
INT:BUF.0.LONG.IO.H2.1.LONG.IO.H2 0.0.6
INT:BUF.0.LONG.IO.H3.1.LONG.IO.H3 0.0.8
INT:BUF.1.LONG.H0.0.LONG.H0 1.0.11
INT:BUF.1.LONG.H1.0.LONG.H1 1.0.9
INT:BUF.1.LONG.H2.0.LONG.H2 1.0.7
INT:BUF.1.LONG.IO.H0.0.LONG.IO.H0 0.0.1
INT:BUF.1.LONG.IO.H1.0.LONG.IO.H1 0.0.3
INT:BUF.1.LONG.IO.H2.0.LONG.IO.H2 0.0.5
INT:BUF.1.LONG.IO.H3.0.LONG.IO.H3 0.0.7
inverted ~[0]

Tile LLVC.CLB

Cells: 2 IRIs: 0

Muxes

xc4000xv LLVC.CLB muxes
DestinationSources
TCELL0:LONG.V0TCELL1:LONG.V0
TCELL0:LONG.V1TCELL1:LONG.V1
TCELL0:LONG.V2TCELL1:LONG.V2
TCELL0:LONG.V3TCELL1:LONG.V3
TCELL0:LONG.V4TCELL1:LONG.V4
TCELL0:LONG.V5TCELL1:LONG.V5
TCELL0:LONG.V6TCELL1:LONG.V6
TCELL0:LONG.V7TCELL1:LONG.V7
TCELL0:LONG.V8TCELL1:LONG.V8
TCELL0:LONG.V9TCELL1:LONG.V9
TCELL0:VCLKTCELL0:QUAD.V0.4, TCELL1:SINGLE.V0, TCELL1:SINGLE.V1, TCELL1:SINGLE.V2, TCELL1:SINGLE.V4, TCELL1:SINGLE.V5, TCELL1:QUAD.V2.0, TCELL1:LONG.V0, TCELL1:LONG.V4, TCELL1:LONG.V6, TCELL1:GCLK2, TCELL1:GCLK5
TCELL1:LONG.V0TCELL0:LONG.V0
TCELL1:LONG.V1TCELL0:LONG.V1
TCELL1:LONG.V2TCELL0:LONG.V2
TCELL1:LONG.V3TCELL0:LONG.V3
TCELL1:LONG.V4TCELL0:LONG.V4
TCELL1:LONG.V5TCELL0:LONG.V5
TCELL1:LONG.V6TCELL0:LONG.V6
TCELL1:LONG.V7TCELL0:LONG.V7
TCELL1:LONG.V8TCELL0:LONG.V8
TCELL1:LONG.V9TCELL0:LONG.V9
TCELL1:VCLKTCELL0:QUAD.V1.4, TCELL0:LONG.V1, TCELL0:LONG.V5, TCELL0:LONG.V8, TCELL0:GCLK1, TCELL0:GCLK4, TCELL1:SINGLE.V0, TCELL1:SINGLE.V1, TCELL1:SINGLE.V4, TCELL1:SINGLE.V5, TCELL1:SINGLE.V6, TCELL1:QUAD.V0.0

Bitstream

INT:BUF.0.LONG.V0.1.LONG.V0 0.26.1
INT:BUF.0.LONG.V1.1.LONG.V1 0.28.1
INT:BUF.0.LONG.V2.1.LONG.V2 0.22.1
INT:BUF.0.LONG.V3.1.LONG.V3 0.41.1
INT:BUF.0.LONG.V4.1.LONG.V4 0.24.1
INT:BUF.0.LONG.V5.1.LONG.V5 0.43.1
INT:BUF.0.LONG.V6.1.LONG.V6 0.45.1
INT:BUF.0.LONG.V7.1.LONG.V7 0.38.1
INT:BUF.0.LONG.V8.1.LONG.V8 0.34.1
INT:BUF.0.LONG.V9.1.LONG.V9 0.33.1
INT:BUF.1.LONG.V0.0.LONG.V0 0.25.1
INT:BUF.1.LONG.V1.0.LONG.V1 0.27.1
INT:BUF.1.LONG.V2.0.LONG.V2 0.23.1
INT:BUF.1.LONG.V3.0.LONG.V3 0.40.1
INT:BUF.1.LONG.V4.0.LONG.V4 0.30.1
INT:BUF.1.LONG.V5.0.LONG.V5 0.42.1
INT:BUF.1.LONG.V6.0.LONG.V6 0.44.1
INT:BUF.1.LONG.V7.0.LONG.V7 0.39.1
INT:BUF.1.LONG.V8.0.LONG.V8 0.35.1
INT:BUF.1.LONG.V9.0.LONG.V9 0.32.1
inverted ~[0]
INT:MUX.0.VCLK 0.5.0 0.6.0 0.15.0 0.35.0 0.14.0 0.8.0 0.7.0
0.QUAD.V0.4 0 0 0 0 1 1 1
1.LONG.V0 0 0 0 1 0 1 1
1.QUAD.V2.0 0 0 1 0 1 0 1
1.LONG.V6 0 0 1 0 1 1 0
1.SINGLE.V1 0 0 1 1 0 0 1
1.SINGLE.V2 0 0 1 1 0 1 0
1.GCLK5 0 1 1 0 1 1 1
1.SINGLE.V4 0 1 1 1 0 1 1
1.SINGLE.V5 1 0 0 1 1 1 1
1.LONG.V4 1 0 1 1 1 0 1
1.GCLK2 1 0 1 1 1 1 0
1.SINGLE.V0 1 1 1 1 1 1 1
INT:MUX.1.VCLK 0.19.0 0.18.0 0.23.0 0.34.0 0.29.0 0.28.0 0.22.0
0.QUAD.V1.4 0 0 0 0 1 1 1
1.SINGLE.V1 0 0 0 1 0 1 1
1.QUAD.V0.0 0 0 1 0 1 0 1
0.LONG.V8 0 0 1 0 1 1 0
0.LONG.V1 0 0 1 1 0 0 1
1.SINGLE.V4 0 0 1 1 0 1 0
0.LONG.V5 0 1 0 1 1 1 1
1.SINGLE.V6 0 1 1 1 1 0 1
0.GCLK1 0 1 1 1 1 1 0
0.GCLK4 1 0 1 0 1 1 1
1.SINGLE.V5 1 0 1 1 0 1 1
1.SINGLE.V0 1 1 1 1 1 1 1

Tile LLVC.IO.L

Cells: 2 IRIs: 0

Muxes

xc4000xv LLVC.IO.L muxes
DestinationSources
TCELL0:LONG.IO.V0TCELL1:LONG.IO.V0
TCELL0:LONG.IO.V1TCELL1:LONG.IO.V1
TCELL0:LONG.IO.V2TCELL1:LONG.IO.V2
TCELL0:LONG.IO.V3TCELL1:LONG.IO.V3
TCELL0:DEC.V0TCELL1:DEC.V0
TCELL0:DEC.V1TCELL1:DEC.V1
TCELL0:DEC.V2TCELL1:DEC.V2
TCELL0:DEC.V3TCELL1:DEC.V3
TCELL1:LONG.IO.V0TCELL0:LONG.IO.V0
TCELL1:LONG.IO.V1TCELL0:LONG.IO.V1
TCELL1:LONG.IO.V2TCELL0:LONG.IO.V2
TCELL1:LONG.IO.V3TCELL0:LONG.IO.V3
TCELL1:DEC.V0TCELL0:DEC.V0
TCELL1:DEC.V1TCELL0:DEC.V1
TCELL1:DEC.V2TCELL0:DEC.V2
TCELL1:DEC.V3TCELL0:DEC.V3

Bel PULLUP_DEC0_S

xc4000xv LLVC.IO.L bel PULLUP_DEC0_S
PinDirectionWires
OoutputTCELL0:DEC.V0

Bel PULLUP_DEC1_S

xc4000xv LLVC.IO.L bel PULLUP_DEC1_S
PinDirectionWires
OoutputTCELL0:DEC.V1

Bel PULLUP_DEC2_S

xc4000xv LLVC.IO.L bel PULLUP_DEC2_S
PinDirectionWires
OoutputTCELL0:DEC.V2

Bel PULLUP_DEC3_S

xc4000xv LLVC.IO.L bel PULLUP_DEC3_S
PinDirectionWires
OoutputTCELL0:DEC.V3

Bel PULLUP_DEC0_N

xc4000xv LLVC.IO.L bel PULLUP_DEC0_N
PinDirectionWires
OoutputTCELL1:DEC.V0

Bel PULLUP_DEC1_N

xc4000xv LLVC.IO.L bel PULLUP_DEC1_N
PinDirectionWires
OoutputTCELL1:DEC.V1

Bel PULLUP_DEC2_N

xc4000xv LLVC.IO.L bel PULLUP_DEC2_N
PinDirectionWires
OoutputTCELL1:DEC.V2

Bel PULLUP_DEC3_N

xc4000xv LLVC.IO.L bel PULLUP_DEC3_N
PinDirectionWires
OoutputTCELL1:DEC.V3

Bel wires

xc4000xv LLVC.IO.L bel wires
WirePins
TCELL0:DEC.V0PULLUP_DEC0_S.O
TCELL0:DEC.V1PULLUP_DEC1_S.O
TCELL0:DEC.V2PULLUP_DEC2_S.O
TCELL0:DEC.V3PULLUP_DEC3_S.O
TCELL1:DEC.V0PULLUP_DEC0_N.O
TCELL1:DEC.V1PULLUP_DEC1_N.O
TCELL1:DEC.V2PULLUP_DEC2_N.O
TCELL1:DEC.V3PULLUP_DEC3_N.O

Bitstream

INT:BIPASS.0.DEC.V0.1.DEC.V0 0.17.1
INT:BIPASS.0.DEC.V1.1.DEC.V1 0.25.1
INT:BIPASS.0.DEC.V2.1.DEC.V2 0.16.1
INT:BIPASS.0.DEC.V3.1.DEC.V3 0.24.1
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 0.10.1
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 0.13.1
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 0.6.1
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 0.5.1
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 0.11.1
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 0.12.1
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 0.7.1
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 0.4.1
PULLUP_DEC0_N:ENABLE 0.15.1
PULLUP_DEC0_S:ENABLE 0.14.1
PULLUP_DEC1_N:ENABLE 0.21.1
PULLUP_DEC1_S:ENABLE 0.20.1
PULLUP_DEC2_N:ENABLE 0.18.1
PULLUP_DEC2_S:ENABLE 0.19.1
PULLUP_DEC3_N:ENABLE 0.22.1
PULLUP_DEC3_S:ENABLE 0.23.1
inverted ~[0]

Tile LLVC.IO.R

Cells: 2 IRIs: 0

Muxes

xc4000xv LLVC.IO.R muxes
DestinationSources
TCELL0:LONG.V0TCELL1:LONG.V0
TCELL0:LONG.V1TCELL1:LONG.V1
TCELL0:LONG.V2TCELL1:LONG.V2
TCELL0:LONG.V3TCELL1:LONG.V3
TCELL0:LONG.V4TCELL1:LONG.V4
TCELL0:LONG.V5TCELL1:LONG.V5
TCELL0:LONG.V6TCELL1:LONG.V6
TCELL0:LONG.V7TCELL1:LONG.V7
TCELL0:LONG.V8TCELL1:LONG.V8
TCELL0:LONG.V9TCELL1:LONG.V9
TCELL0:LONG.IO.V0TCELL1:LONG.IO.V0
TCELL0:LONG.IO.V1TCELL1:LONG.IO.V1
TCELL0:LONG.IO.V2TCELL1:LONG.IO.V2
TCELL0:LONG.IO.V3TCELL1:LONG.IO.V3
TCELL0:DEC.V0TCELL1:DEC.V0
TCELL0:DEC.V1TCELL1:DEC.V1
TCELL0:DEC.V2TCELL1:DEC.V2
TCELL0:DEC.V3TCELL1:DEC.V3
TCELL0:VCLKTCELL0:QUAD.V0.4, TCELL1:SINGLE.V0, TCELL1:SINGLE.V1, TCELL1:SINGLE.V2, TCELL1:SINGLE.V4, TCELL1:SINGLE.V5, TCELL1:QUAD.V2.0, TCELL1:LONG.V0, TCELL1:LONG.V4, TCELL1:LONG.V6, TCELL1:GCLK2, TCELL1:GCLK5
TCELL1:LONG.V0TCELL0:LONG.V0
TCELL1:LONG.V1TCELL0:LONG.V1
TCELL1:LONG.V2TCELL0:LONG.V2
TCELL1:LONG.V3TCELL0:LONG.V3
TCELL1:LONG.V4TCELL0:LONG.V4
TCELL1:LONG.V5TCELL0:LONG.V5
TCELL1:LONG.V6TCELL0:LONG.V6
TCELL1:LONG.V7TCELL0:LONG.V7
TCELL1:LONG.V8TCELL0:LONG.V8
TCELL1:LONG.V9TCELL0:LONG.V9
TCELL1:LONG.IO.V0TCELL0:LONG.IO.V0
TCELL1:LONG.IO.V1TCELL0:LONG.IO.V1
TCELL1:LONG.IO.V2TCELL0:LONG.IO.V2
TCELL1:LONG.IO.V3TCELL0:LONG.IO.V3
TCELL1:DEC.V0TCELL0:DEC.V0
TCELL1:DEC.V1TCELL0:DEC.V1
TCELL1:DEC.V2TCELL0:DEC.V2
TCELL1:DEC.V3TCELL0:DEC.V3
TCELL1:VCLKTCELL0:QUAD.V1.4, TCELL0:LONG.V1, TCELL0:LONG.V5, TCELL0:LONG.V8, TCELL0:GCLK1, TCELL0:GCLK4, TCELL1:SINGLE.V0, TCELL1:SINGLE.V1, TCELL1:SINGLE.V4, TCELL1:SINGLE.V5, TCELL1:SINGLE.V6, TCELL1:QUAD.V0.0

Bel PULLUP_DEC0_S

xc4000xv LLVC.IO.R bel PULLUP_DEC0_S
PinDirectionWires
OoutputTCELL0:DEC.V0

Bel PULLUP_DEC1_S

xc4000xv LLVC.IO.R bel PULLUP_DEC1_S
PinDirectionWires
OoutputTCELL0:DEC.V1

Bel PULLUP_DEC2_S

xc4000xv LLVC.IO.R bel PULLUP_DEC2_S
PinDirectionWires
OoutputTCELL0:DEC.V2

Bel PULLUP_DEC3_S

xc4000xv LLVC.IO.R bel PULLUP_DEC3_S
PinDirectionWires
OoutputTCELL0:DEC.V3

Bel PULLUP_DEC0_N

xc4000xv LLVC.IO.R bel PULLUP_DEC0_N
PinDirectionWires
OoutputTCELL1:DEC.V0

Bel PULLUP_DEC1_N

xc4000xv LLVC.IO.R bel PULLUP_DEC1_N
PinDirectionWires
OoutputTCELL1:DEC.V1

Bel PULLUP_DEC2_N

xc4000xv LLVC.IO.R bel PULLUP_DEC2_N
PinDirectionWires
OoutputTCELL1:DEC.V2

Bel PULLUP_DEC3_N

xc4000xv LLVC.IO.R bel PULLUP_DEC3_N
PinDirectionWires
OoutputTCELL1:DEC.V3

Bel wires

xc4000xv LLVC.IO.R bel wires
WirePins
TCELL0:DEC.V0PULLUP_DEC0_S.O
TCELL0:DEC.V1PULLUP_DEC1_S.O
TCELL0:DEC.V2PULLUP_DEC2_S.O
TCELL0:DEC.V3PULLUP_DEC3_S.O
TCELL1:DEC.V0PULLUP_DEC0_N.O
TCELL1:DEC.V1PULLUP_DEC1_N.O
TCELL1:DEC.V2PULLUP_DEC2_N.O
TCELL1:DEC.V3PULLUP_DEC3_N.O

Bitstream

xc4000xv LLVC.IO.R bittile 0
BitFrame
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 ~INT:BUF.0.LONG.V6.1.LONG.V6 ~INT:BUF.1.LONG.V6.0.LONG.V6 - - - - ~INT:BUF.1.LONG.V7.0.LONG.V7 ~INT:BUF.0.LONG.V7.1.LONG.V7 - - ~INT:BUF.1.LONG.V8.0.LONG.V8 ~INT:BUF.0.LONG.V8.1.LONG.V8 ~INT:BUF.0.LONG.V9.1.LONG.V9 ~INT:BUF.1.LONG.V9.0.LONG.V9 - ~INT:BIPASS.0.DEC.V3.1.DEC.V3 ~INT:BUF.0.LONG.V1.1.LONG.V1 ~PULLUP_DEC3_S:ENABLE ~INT:BUF.1.LONG.V1.0.LONG.V1 ~PULLUP_DEC3_N:ENABLE ~INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 ~INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 ~INT:BUF.1.LONG.V2.0.LONG.V2 ~INT:BUF.0.LONG.V2.1.LONG.V2 ~INT:BUF.0.LONG.V4.1.LONG.V4 ~INT:BUF.1.LONG.V4.0.LONG.V4 ~INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 ~INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 - - ~INT:BUF.0.LONG.V3.1.LONG.V3 ~INT:BUF.1.LONG.V3.0.LONG.V3 ~INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 ~INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 ~INT:BUF.0.LONG.V0.1.LONG.V0 ~INT:BUF.1.LONG.V0.0.LONG.V0 ~INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 ~INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 ~PULLUP_DEC1_S:ENABLE ~PULLUP_DEC1_N:ENABLE ~INT:BUF.1.LONG.V5.0.LONG.V5 ~INT:BUF.0.LONG.V5.1.LONG.V5 - ~PULLUP_DEC0_N:ENABLE ~PULLUP_DEC2_N:ENABLE ~PULLUP_DEC2_S:ENABLE ~PULLUP_DEC0_S:ENABLE - - - -
0 - - - - - - - - - - INT:MUX.0.VCLK[3] INT:MUX.1.VCLK[3] - - - - INT:MUX.1.VCLK[2] INT:MUX.1.VCLK[1] - - - - INT:MUX.1.VCLK[4] INT:MUX.1.VCLK[0] - - INT:MUX.1.VCLK[6] INT:MUX.1.VCLK[5] - - INT:MUX.0.VCLK[4] INT:MUX.0.VCLK[2] - - - - - - INT:MUX.0.VCLK[1] INT:MUX.0.VCLK[0] INT:MUX.0.VCLK[5] INT:MUX.0.VCLK[6] - ~INT:BIPASS.0.DEC.V1.1.DEC.V1 - ~INT:BIPASS.0.DEC.V2.1.DEC.V2 ~INT:BIPASS.0.DEC.V0.1.DEC.V0 - ~MISC:TLC - -
INT:BIPASS.0.DEC.V0.1.DEC.V0 0.4.0
INT:BIPASS.0.DEC.V1.1.DEC.V1 0.7.0
INT:BIPASS.0.DEC.V2.1.DEC.V2 0.5.0
INT:BIPASS.0.DEC.V3.1.DEC.V3 0.35.1
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 0.30.1
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 0.13.1
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 0.23.1
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 0.18.1
INT:BUF.0.LONG.V0.1.LONG.V0 0.16.1
INT:BUF.0.LONG.V1.1.LONG.V1 0.34.1
INT:BUF.0.LONG.V2.1.LONG.V2 0.27.1
INT:BUF.0.LONG.V3.1.LONG.V3 0.20.1
INT:BUF.0.LONG.V4.1.LONG.V4 0.26.1
INT:BUF.0.LONG.V5.1.LONG.V5 0.9.1
INT:BUF.0.LONG.V6.1.LONG.V6 0.50.1
INT:BUF.0.LONG.V7.1.LONG.V7 0.43.1
INT:BUF.0.LONG.V8.1.LONG.V8 0.39.1
INT:BUF.0.LONG.V9.1.LONG.V9 0.38.1
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 0.29.1
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 0.14.1
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 0.24.1
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 0.17.1
INT:BUF.1.LONG.V0.0.LONG.V0 0.15.1
INT:BUF.1.LONG.V1.0.LONG.V1 0.32.1
INT:BUF.1.LONG.V2.0.LONG.V2 0.28.1
INT:BUF.1.LONG.V3.0.LONG.V3 0.19.1
INT:BUF.1.LONG.V4.0.LONG.V4 0.25.1
INT:BUF.1.LONG.V5.0.LONG.V5 0.10.1
INT:BUF.1.LONG.V6.0.LONG.V6 0.49.1
INT:BUF.1.LONG.V7.0.LONG.V7 0.44.1
INT:BUF.1.LONG.V8.0.LONG.V8 0.40.1
INT:BUF.1.LONG.V9.0.LONG.V9 0.37.1
MISC:TLC 0.2.0
PULLUP_DEC0_N:ENABLE 0.7.1
PULLUP_DEC0_S:ENABLE 0.4.1
PULLUP_DEC1_N:ENABLE 0.11.1
PULLUP_DEC1_S:ENABLE 0.12.1
PULLUP_DEC2_N:ENABLE 0.6.1
PULLUP_DEC2_S:ENABLE 0.5.1
PULLUP_DEC3_N:ENABLE 0.31.1
PULLUP_DEC3_S:ENABLE 0.33.1
inverted ~[0]
INT:MUX.0.VCLK 0.9.0 0.10.0 0.20.0 0.40.0 0.19.0 0.12.0 0.11.0
0.QUAD.V0.4 0 0 0 0 1 1 1
1.LONG.V0 0 0 0 1 0 1 1
1.QUAD.V2.0 0 0 1 0 1 0 1
1.LONG.V6 0 0 1 0 1 1 0
1.SINGLE.V1 0 0 1 1 0 0 1
1.SINGLE.V2 0 0 1 1 0 1 0
1.GCLK5 0 1 1 0 1 1 1
1.SINGLE.V4 0 1 1 1 0 1 1
1.SINGLE.V5 1 0 0 1 1 1 1
1.LONG.V4 1 0 1 1 1 0 1
1.GCLK2 1 0 1 1 1 1 0
1.SINGLE.V0 1 1 1 1 1 1 1
INT:MUX.1.VCLK 0.24.0 0.23.0 0.28.0 0.39.0 0.34.0 0.33.0 0.27.0
0.QUAD.V1.4 0 0 0 0 1 1 1
1.SINGLE.V1 0 0 0 1 0 1 1
1.QUAD.V0.0 0 0 1 0 1 0 1
0.LONG.V8 0 0 1 0 1 1 0
0.LONG.V1 0 0 1 1 0 0 1
1.SINGLE.V4 0 0 1 1 0 1 0
0.LONG.V5 0 1 0 1 1 1 1
1.SINGLE.V6 0 1 1 1 1 0 1
0.GCLK1 0 1 1 1 1 1 0
0.GCLK4 1 0 1 0 1 1 1
1.SINGLE.V5 1 0 1 1 0 1 1
1.SINGLE.V0 1 1 1 1 1 1 1

Tile LLVQ.CLB

Cells: 2 IRIs: 0

Muxes

xc4000xv LLVQ.CLB muxes
DestinationSources
TCELL0:QUAD.V1.4TCELL0:VCLK
TCELL0:QUAD.V2.4TCELL1:VCLK
TCELL0:LONG.V0TCELL1:LONG.V0
TCELL0:LONG.V1TCELL1:LONG.V1
TCELL0:LONG.V2TCELL1:LONG.V2
TCELL0:LONG.V3TCELL1:LONG.V3
TCELL0:LONG.V4TCELL1:LONG.V4
TCELL0:LONG.V5TCELL1:LONG.V5
TCELL0:LONG.V6TCELL1:LONG.V6
TCELL0:LONG.V7TCELL1:LONG.V7.EXCL
TCELL0:LONG.V8TCELL1:LONG.V8
TCELL0:LONG.V9TCELL1:LONG.V9.EXCL
TCELL0:GCLK0TCELL0:QUAD.V0.3, TCELL0:VCLK, TCELL1:SINGLE.V0, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK1TCELL0:QUAD.V0.4, TCELL0:VCLK, TCELL1:SINGLE.V1, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK2TCELL0:VCLK, TCELL1:SINGLE.V2, TCELL1:QUAD.V0.0, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK3TCELL0:QUAD.V1.4, TCELL0:VCLK, TCELL1:SINGLE.V3, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK4TCELL0:VCLK, TCELL1:SINGLE.V4, TCELL1:QUAD.V1.0, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK5TCELL0:QUAD.V2.3, TCELL0:VCLK, TCELL1:SINGLE.V5, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK6TCELL0:QUAD.V2.4, TCELL0:VCLK, TCELL1:SINGLE.V6, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK7TCELL0:VCLK, TCELL1:SINGLE.V7, TCELL1:QUAD.V2.0, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL1:SINGLE.V0TCELL0:VCLK
TCELL1:SINGLE.V1TCELL1:VCLK
TCELL1:SINGLE.V2TCELL0:VCLK
TCELL1:SINGLE.V3TCELL1:VCLK
TCELL1:SINGLE.V4TCELL0:VCLK
TCELL1:SINGLE.V5TCELL1:VCLK
TCELL1:SINGLE.V6TCELL0:VCLK
TCELL1:SINGLE.V7TCELL1:VCLK
TCELL1:QUAD.V0.0TCELL1:VCLK
TCELL1:QUAD.V2.0TCELL0:VCLK
TCELL1:LONG.V0TCELL0:LONG.V0
TCELL1:LONG.V1TCELL0:LONG.V1
TCELL1:LONG.V2TCELL0:LONG.V2
TCELL1:LONG.V3TCELL0:LONG.V3
TCELL1:LONG.V4TCELL0:LONG.V4
TCELL1:LONG.V5TCELL0:LONG.V5
TCELL1:LONG.V6TCELL0:LONG.V6
TCELL1:LONG.V7TCELL1:LONG.V7.EXCL
TCELL1:LONG.V7.EXCLTCELL0:LONG.V7, TCELL0:VCLK, TCELL1:LONG.V7
TCELL1:LONG.V8TCELL0:LONG.V8
TCELL1:LONG.V9TCELL1:LONG.V9.EXCL
TCELL1:LONG.V9.EXCLTCELL0:LONG.V9, TCELL1:LONG.V9, TCELL1:VCLK

Bitstream

xc4000xv LLVQ.CLB bittile 0
BitFrame
46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 ~INT:BUF.0.LONG.V6.1.LONG.V6 ~INT:BUF.0.LONG.V7.1.LONG.V7 ~INT:PASS.1.QUAD.V0.0.1.VCLK INT:MUX.1.LONG.V7[0] ~INT:BUF.0.LONG.V8.1.LONG.V8 INT:MUX.0.GCLK4[3] INT:MUX.0.GCLK4[4] INT:MUX.0.GCLK4[6] INT:MUX.0.GCLK4[0] ~INT:BUF.1.LONG.V9.0.LONG.V9 INT:MUX.0.LONG.V9[0] INT:MUX.0.GCLK5[5] INT:MUX.0.GCLK5[3] INT:MUX.0.GCLK5[6] INT:MUX.0.GCLK5[0] ~INT:BUF.0.LONG.V2.1.LONG.V2 INT:MUX.0.GCLK0[5] INT:MUX.0.GCLK0[3] INT:MUX.0.GCLK0[6] INT:MUX.0.GCLK0[0] ~INT:PASS.1.SINGLE.V1.1.VCLK ~INT:BUF.0.LONG.V4.1.LONG.V4 INT:MUX.0.GCLK6[5] INT:MUX.0.GCLK6[3] INT:MUX.0.GCLK6[6] INT:MUX.0.GCLK6[0] ~INT:BUF.0.LONG.V1.1.LONG.V1 INT:MUX.0.GCLK7[3] INT:MUX.0.GCLK7[4] INT:MUX.0.GCLK7[6] INT:MUX.0.GCLK7[0] ~INT:BUF.0.LONG.V5.1.LONG.V5 - INT:MUX.0.GCLK2[3] INT:MUX.0.GCLK2[4] INT:MUX.0.GCLK2[6] INT:MUX.0.GCLK2[0] ~INT:BUF.0.LONG.V3.1.LONG.V3 INT:MUX.0.GCLK3[5] INT:MUX.0.GCLK3[3] INT:MUX.0.GCLK3[6] INT:MUX.0.GCLK3[0] ~INT:BUF.0.LONG.V0.1.LONG.V0 INT:MUX.0.GCLK1[5] INT:MUX.0.GCLK1[3] INT:MUX.0.GCLK1[6] INT:MUX.0.GCLK1[0]
0 ~INT:BUF.1.LONG.V6.0.LONG.V6 INT:MUX.1.LONG.V7[1] ~INT:BUF.1.LONG.V8.0.LONG.V8 ~INT:PASS.0.QUAD.V1.4.0.VCLK ~INT:PASS.0.QUAD.V2.4.1.VCLK INT:MUX.0.GCLK4[5] INT:MUX.0.GCLK4[2] INT:MUX.0.GCLK4[1] ~INT:PASS.1.SINGLE.V4.0.VCLK ~INT:PASS.1.SINGLE.V6.0.VCLK INT:MUX.0.LONG.V9[1] INT:MUX.0.GCLK5[4] INT:MUX.0.GCLK5[2] INT:MUX.0.GCLK5[1] ~INT:PASS.1.SINGLE.V7.1.VCLK ~INT:BUF.1.LONG.V2.0.LONG.V2 INT:MUX.0.GCLK0[4] INT:MUX.0.GCLK0[2] ~INT:PASS.1.SINGLE.V5.1.VCLK ~INT:PASS.1.SINGLE.V3.1.VCLK INT:MUX.0.GCLK0[1] ~INT:BUF.1.LONG.V4.0.LONG.V4 INT:MUX.0.GCLK6[4] INT:MUX.0.GCLK6[2] ~INT:PASS.1.QUAD.V2.0.0.VCLK INT:MUX.0.GCLK6[1] ~INT:BUF.1.LONG.V1.0.LONG.V1 INT:MUX.0.GCLK7[5] INT:MUX.0.GCLK7[2] ~INT:PASS.1.SINGLE.V0.0.VCLK INT:MUX.0.GCLK7[1] ~INT:BUF.1.LONG.V5.0.LONG.V5 ~INT:PASS.1.SINGLE.V2.0.VCLK INT:MUX.0.GCLK2[5] INT:MUX.0.GCLK2[2] - INT:MUX.0.GCLK2[1] ~INT:BUF.1.LONG.V3.0.LONG.V3 INT:MUX.0.GCLK3[4] INT:MUX.0.GCLK3[2] - INT:MUX.0.GCLK3[1] ~INT:BUF.1.LONG.V0.0.LONG.V0 INT:MUX.0.GCLK1[4] INT:MUX.0.GCLK1[2] - INT:MUX.0.GCLK1[1]
INT:BUF.0.LONG.V0.1.LONG.V0 0.4.1
INT:BUF.0.LONG.V1.1.LONG.V1 0.20.1
INT:BUF.0.LONG.V2.1.LONG.V2 0.31.1
INT:BUF.0.LONG.V3.1.LONG.V3 0.9.1
INT:BUF.0.LONG.V4.1.LONG.V4 0.25.1
INT:BUF.0.LONG.V5.1.LONG.V5 0.15.1
INT:BUF.0.LONG.V6.1.LONG.V6 0.46.1
INT:BUF.0.LONG.V7.1.LONG.V7 0.45.1
INT:BUF.0.LONG.V8.1.LONG.V8 0.42.1
INT:BUF.1.LONG.V0.0.LONG.V0 0.4.0
INT:BUF.1.LONG.V1.0.LONG.V1 0.20.0
INT:BUF.1.LONG.V2.0.LONG.V2 0.31.0
INT:BUF.1.LONG.V3.0.LONG.V3 0.9.0
INT:BUF.1.LONG.V4.0.LONG.V4 0.25.0
INT:BUF.1.LONG.V5.0.LONG.V5 0.15.0
INT:BUF.1.LONG.V6.0.LONG.V6 0.46.0
INT:BUF.1.LONG.V8.0.LONG.V8 0.44.0
INT:BUF.1.LONG.V9.0.LONG.V9 0.37.1
INT:PASS.0.QUAD.V1.4.0.VCLK 0.43.0
INT:PASS.0.QUAD.V2.4.1.VCLK 0.42.0
INT:PASS.1.QUAD.V0.0.1.VCLK 0.44.1
INT:PASS.1.QUAD.V2.0.0.VCLK 0.22.0
INT:PASS.1.SINGLE.V0.0.VCLK 0.17.0
INT:PASS.1.SINGLE.V1.1.VCLK 0.26.1
INT:PASS.1.SINGLE.V2.0.VCLK 0.14.0
INT:PASS.1.SINGLE.V3.1.VCLK 0.27.0
INT:PASS.1.SINGLE.V4.0.VCLK 0.38.0
INT:PASS.1.SINGLE.V5.1.VCLK 0.28.0
INT:PASS.1.SINGLE.V6.0.VCLK 0.37.0
INT:PASS.1.SINGLE.V7.1.VCLK 0.32.0
inverted ~[0]
INT:MUX.0.GCLK0 0.28.1 0.30.1 0.30.0 0.29.1 0.29.0 0.26.0 0.27.1
0.QUAD.V0.3 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V0 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK1 0.1.1 0.3.1 0.3.0 0.2.1 0.2.0 0.0.0 0.0.1
0.QUAD.V0.4 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V1 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK2 0.11.1 0.13.0 0.12.1 0.13.1 0.12.0 0.10.0 0.10.1
0.VCLK 0 0 1 1 1 1 1
1.SINGLE.V2 0 1 0 1 1 1 1
1.QUAD.V0.0 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H2 1 0 1 1 1 0 1
1.BUFGLS.H3 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H4 1 1 1 0 1 0 1
1.BUFGLS.H5 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK3 0.6.1 0.8.1 0.8.0 0.7.1 0.7.0 0.5.0 0.5.1
0.QUAD.V1.4 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V3 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK4 0.39.1 0.41.0 0.40.1 0.41.1 0.40.0 0.39.0 0.38.1
0.VCLK 0 0 1 1 1 1 1
1.SINGLE.V4 0 1 0 1 1 1 1
1.QUAD.V1.0 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H2 1 0 1 1 1 0 1
1.BUFGLS.H3 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H4 1 1 1 0 1 0 1
1.BUFGLS.H5 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK5 0.33.1 0.35.1 0.35.0 0.34.1 0.34.0 0.33.0 0.32.1
0.QUAD.V2.3 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V5 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK6 0.22.1 0.24.1 0.24.0 0.23.1 0.23.0 0.21.0 0.21.1
0.QUAD.V2.4 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V6 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK7 0.17.1 0.19.0 0.18.1 0.19.1 0.18.0 0.16.0 0.16.1
0.VCLK 0 0 1 1 1 1 1
1.SINGLE.V7 0 1 0 1 1 1 1
1.QUAD.V2.0 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H2 1 0 1 1 1 0 1
1.BUFGLS.H3 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H4 1 1 1 0 1 0 1
1.BUFGLS.H5 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.LONG.V9 0.36.0 0.36.1
1.LONG.V9 0 0
1.VCLK 0 1
NONE 1 1
INT:MUX.1.LONG.V7 0.45.0 0.43.1
0.LONG.V7 0 0
0.VCLK 0 1
NONE 1 1

Tile LLVQ.IO.L.B

Cells: 2 IRIs: 0

Muxes

xc4000xv LLVQ.IO.L.B muxes
DestinationSources
TCELL0:IO.DOUBLE.0.W.1TCELL0:ECLK.V
TCELL0:IO.DOUBLE.1.W.1TCELL0:ECLK.V
TCELL0:IO.DOUBLE.1.W.2TCELL0:ECLK.V
TCELL0:IO.DOUBLE.2.W.1TCELL0:ECLK.V
TCELL0:IO.DOUBLE.3.W.2TCELL0:ECLK.V
TCELL0:LONG.IO.V0TCELL1:LONG.IO.V0
TCELL0:LONG.IO.V1TCELL1:LONG.IO.V1
TCELL0:LONG.IO.V2TCELL1:LONG.IO.V2
TCELL0:LONG.IO.V3TCELL1:LONG.IO.V3
TCELL0:GCLK0TCELL0:IO.DOUBLE.0.W.1, TCELL0:IO.DOUBLE.2.W.1, TCELL0:BUFGE.V1, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7, TCELL1:OUT.BUFF
TCELL0:GCLK1TCELL0:IO.DOUBLE.0.W.2, TCELL0:IO.DOUBLE.2.W.2, TCELL0:ECLK.V, TCELL0:BUFGE.V0, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK2TCELL0:IO.DOUBLE.1.W.1, TCELL0:IO.DOUBLE.3.W.1, TCELL0:ECLK.V, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7, TCELL1:OUT.BUFF
TCELL0:GCLK3TCELL0:IO.DOUBLE.1.W.2, TCELL0:IO.DOUBLE.3.W.2, TCELL0:BUFGE.V0, TCELL0:BUFGE.V1, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL1:LONG.IO.V0TCELL0:LONG.IO.V0
TCELL1:LONG.IO.V1TCELL0:LONG.IO.V1
TCELL1:LONG.IO.V2TCELL0:LONG.IO.V2
TCELL1:LONG.IO.V3TCELL0:LONG.IO.V3

Bel BUFF

xc4000xv LLVQ.IO.L.B bel BUFF
PinDirectionWires
OoutputTCELL1:OUT.BUFF

Bel wires

xc4000xv LLVQ.IO.L.B bel wires
WirePins
TCELL1:OUT.BUFFBUFF.O

Bitstream

INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 0.7.1
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 0.9.1
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 0.5.1
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 0.8.1
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 0.7.0
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 0.9.0
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 0.5.0
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 0.8.0
INT:PASS.0.IO.DOUBLE.0.W.1.0.ECLK.V 0.15.0
INT:PASS.0.IO.DOUBLE.1.W.1.0.ECLK.V 0.11.0
INT:PASS.0.IO.DOUBLE.1.W.2.0.ECLK.V 0.19.0
INT:PASS.0.IO.DOUBLE.2.W.1.0.ECLK.V 0.6.1
INT:PASS.0.IO.DOUBLE.3.W.2.0.ECLK.V 0.23.0
inverted ~[0]
INT:MUX.0.GCLK0 0.16.1 0.18.1 0.17.1 0.18.0 0.17.0 0.16.0 0.15.1
0.IO.DOUBLE.0.W.1 0 0 1 1 1 1 1
0.IO.DOUBLE.2.W.1 0 1 0 1 1 1 1
0.BUFGE.V1 0 1 1 0 1 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
1.OUT.BUFF 1 1 1 1 1 1 1
INT:MUX.0.GCLK1 0.24.1 0.26.1 0.25.1 0.26.0 0.25.0 0.24.0 0.23.1
0.IO.DOUBLE.0.W.2 0 0 1 1 1 1 1
0.IO.DOUBLE.2.W.2 0 1 0 1 1 1 1
0.ECLK.V 0 1 1 0 1 1 1
0.BUFGE.V0 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK2 0.12.1 0.13.1 0.14.1 0.14.0 0.13.0 0.12.0 0.11.1
0.IO.DOUBLE.1.W.1 0 0 1 1 1 1 1
0.IO.DOUBLE.3.W.1 0 1 0 1 1 1 1
0.ECLK.V 0 1 1 0 1 1 1
1.BUFGLS.H6 1 0 1 1 1 0 1
1.BUFGLS.H7 1 0 1 1 1 1 0
1.BUFGLS.H4 1 1 0 1 1 0 1
1.BUFGLS.H5 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
1.OUT.BUFF 1 1 1 1 1 1 1
INT:MUX.0.GCLK3 0.20.1 0.21.1 0.22.1 0.21.0 0.22.0 0.20.0 0.19.1
0.IO.DOUBLE.1.W.2 0 0 1 1 1 1 1
0.IO.DOUBLE.3.W.2 0 1 0 1 1 1 1
0.BUFGE.V0 0 1 1 0 1 1 1
0.BUFGE.V1 0 1 1 1 0 1 1
1.BUFGLS.H6 1 0 1 1 1 0 1
1.BUFGLS.H7 1 0 1 1 1 1 0
1.BUFGLS.H4 1 1 0 1 1 0 1
1.BUFGLS.H5 1 1 0 1 1 1 0
1.BUFGLS.H0 1 1 1 0 1 0 1
1.BUFGLS.H1 1 1 1 0 1 1 0
1.BUFGLS.H2 1 1 1 1 0 0 1
1.BUFGLS.H3 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1

Tile LLVQ.IO.L.T

Cells: 2 IRIs: 0

Muxes

xc4000xv LLVQ.IO.L.T muxes
DestinationSources
TCELL0:IO.DOUBLE.0.W.1TCELL1:ECLK.V
TCELL0:IO.DOUBLE.1.W.1TCELL1:ECLK.V
TCELL0:IO.DOUBLE.1.W.2TCELL1:ECLK.V
TCELL0:IO.DOUBLE.2.W.1TCELL1:ECLK.V
TCELL0:IO.DOUBLE.3.W.2TCELL1:ECLK.V
TCELL0:LONG.IO.V0TCELL1:LONG.IO.V0
TCELL0:LONG.IO.V1TCELL1:LONG.IO.V1
TCELL0:LONG.IO.V2TCELL1:LONG.IO.V2
TCELL0:LONG.IO.V3TCELL1:LONG.IO.V3
TCELL0:GCLK0TCELL0:IO.DOUBLE.0.W.1, TCELL0:IO.DOUBLE.2.W.1, TCELL0:BUFGE.V0, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7, TCELL1:OUT.BUFF
TCELL0:GCLK1TCELL0:IO.DOUBLE.0.W.2, TCELL0:IO.DOUBLE.2.W.2, TCELL0:BUFGE.V1, TCELL1:ECLK.V, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK2TCELL0:IO.DOUBLE.1.W.1, TCELL0:IO.DOUBLE.3.W.1, TCELL1:ECLK.V, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7, TCELL1:OUT.BUFF
TCELL0:GCLK3TCELL0:IO.DOUBLE.1.W.2, TCELL0:IO.DOUBLE.3.W.2, TCELL0:BUFGE.V0, TCELL0:BUFGE.V1, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL1:LONG.IO.V0TCELL0:LONG.IO.V0
TCELL1:LONG.IO.V1TCELL0:LONG.IO.V1
TCELL1:LONG.IO.V2TCELL0:LONG.IO.V2
TCELL1:LONG.IO.V3TCELL0:LONG.IO.V3

Bel BUFF

xc4000xv LLVQ.IO.L.T bel BUFF
PinDirectionWires
OoutputTCELL1:OUT.BUFF

Bel wires

xc4000xv LLVQ.IO.L.T bel wires
WirePins
TCELL1:OUT.BUFFBUFF.O

Bitstream

INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 0.7.1
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 0.9.1
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 0.5.1
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 0.8.1
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 0.7.0
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 0.9.0
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 0.5.0
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 0.8.0
INT:PASS.0.IO.DOUBLE.0.W.1.1.ECLK.V 0.15.0
INT:PASS.0.IO.DOUBLE.1.W.1.1.ECLK.V 0.11.0
INT:PASS.0.IO.DOUBLE.1.W.2.1.ECLK.V 0.19.0
INT:PASS.0.IO.DOUBLE.2.W.1.1.ECLK.V 0.6.1
INT:PASS.0.IO.DOUBLE.3.W.2.1.ECLK.V 0.23.0
inverted ~[0]
INT:MUX.0.GCLK0 0.16.1 0.18.1 0.17.1 0.18.0 0.17.0 0.16.0 0.15.1
0.IO.DOUBLE.0.W.1 0 0 1 1 1 1 1
0.IO.DOUBLE.2.W.1 0 1 0 1 1 1 1
0.BUFGE.V0 0 1 1 0 1 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
1.OUT.BUFF 1 1 1 1 1 1 1
INT:MUX.0.GCLK1 0.24.1 0.26.1 0.25.1 0.25.0 0.26.0 0.24.0 0.23.1
0.IO.DOUBLE.0.W.2 0 0 1 1 1 1 1
0.IO.DOUBLE.2.W.2 0 1 0 1 1 1 1
0.BUFGE.V1 0 1 1 0 1 1 1
1.ECLK.V 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H0 1 1 1 0 1 0 1
1.BUFGLS.H1 1 1 1 0 1 1 0
1.BUFGLS.H2 1 1 1 1 0 0 1
1.BUFGLS.H3 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK2 0.12.1 0.13.1 0.14.1 0.14.0 0.13.0 0.12.0 0.11.1
0.IO.DOUBLE.1.W.1 0 0 1 1 1 1 1
0.IO.DOUBLE.3.W.1 0 1 0 1 1 1 1
1.ECLK.V 0 1 1 0 1 1 1
1.BUFGLS.H6 1 0 1 1 1 0 1
1.BUFGLS.H7 1 0 1 1 1 1 0
1.BUFGLS.H4 1 1 0 1 1 0 1
1.BUFGLS.H5 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
1.OUT.BUFF 1 1 1 1 1 1 1
INT:MUX.0.GCLK3 0.20.1 0.21.1 0.22.1 0.22.0 0.21.0 0.20.0 0.19.1
0.IO.DOUBLE.1.W.2 0 0 1 1 1 1 1
0.IO.DOUBLE.3.W.2 0 1 0 1 1 1 1
0.BUFGE.V0 0 1 1 0 1 1 1
0.BUFGE.V1 0 1 1 1 0 1 1
1.BUFGLS.H6 1 0 1 1 1 0 1
1.BUFGLS.H7 1 0 1 1 1 1 0
1.BUFGLS.H4 1 1 0 1 1 0 1
1.BUFGLS.H5 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1

Tile LLVQ.IO.R.B

Cells: 2 IRIs: 0

Muxes

xc4000xv LLVQ.IO.R.B muxes
DestinationSources
TCELL0:IO.DOUBLE.0.E.1TCELL0:ECLK.V
TCELL0:IO.DOUBLE.1.E.0TCELL0:ECLK.V
TCELL0:IO.DOUBLE.1.E.1TCELL0:ECLK.V
TCELL0:IO.DOUBLE.2.E.1TCELL0:ECLK.V
TCELL0:IO.DOUBLE.3.E.0TCELL0:ECLK.V
TCELL0:QUAD.V1.4TCELL0:VCLK
TCELL0:QUAD.V2.4TCELL1:VCLK
TCELL0:LONG.V0TCELL1:LONG.V0
TCELL0:LONG.V1TCELL1:LONG.V1
TCELL0:LONG.V2TCELL1:LONG.V2
TCELL0:LONG.V3TCELL1:LONG.V3
TCELL0:LONG.V4TCELL1:LONG.V4
TCELL0:LONG.V5TCELL1:LONG.V5
TCELL0:LONG.V6TCELL1:LONG.V6
TCELL0:LONG.V7TCELL1:LONG.V7.EXCL
TCELL0:LONG.V8TCELL1:LONG.V8
TCELL0:LONG.V9TCELL1:LONG.V9.EXCL
TCELL0:LONG.IO.V0TCELL1:LONG.IO.V0
TCELL0:LONG.IO.V1TCELL1:LONG.IO.V1
TCELL0:LONG.IO.V2TCELL1:LONG.IO.V2
TCELL0:LONG.IO.V3TCELL1:LONG.IO.V3
TCELL0:GCLK0TCELL0:IO.DOUBLE.0.E.1, TCELL0:IO.DOUBLE.2.E.1, TCELL0:BUFGE.V1, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7, TCELL1:OUT.BUFF
TCELL0:GCLK1TCELL0:IO.DOUBLE.0.E.0, TCELL0:IO.DOUBLE.2.E.0, TCELL0:ECLK.V, TCELL0:BUFGE.V0, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK2TCELL0:IO.DOUBLE.1.E.1, TCELL0:IO.DOUBLE.3.E.1, TCELL0:ECLK.V, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7, TCELL1:OUT.BUFF
TCELL0:GCLK3TCELL0:IO.DOUBLE.1.E.0, TCELL0:IO.DOUBLE.3.E.0, TCELL0:BUFGE.V0, TCELL0:BUFGE.V1, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK4TCELL0:VCLK, TCELL1:SINGLE.V4, TCELL1:QUAD.V1.0, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK5TCELL0:QUAD.V2.3, TCELL0:VCLK, TCELL1:SINGLE.V5, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK6TCELL0:QUAD.V2.4, TCELL0:VCLK, TCELL1:SINGLE.V6, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK7TCELL0:VCLK, TCELL1:SINGLE.V7, TCELL1:QUAD.V2.0, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL1:SINGLE.V0TCELL0:VCLK
TCELL1:SINGLE.V1TCELL1:VCLK
TCELL1:SINGLE.V2TCELL0:VCLK
TCELL1:SINGLE.V3TCELL1:VCLK
TCELL1:SINGLE.V4TCELL0:VCLK
TCELL1:SINGLE.V5TCELL1:VCLK
TCELL1:SINGLE.V6TCELL0:VCLK
TCELL1:SINGLE.V7TCELL1:VCLK
TCELL1:QUAD.V0.0TCELL1:VCLK
TCELL1:QUAD.V2.0TCELL0:VCLK
TCELL1:LONG.V0TCELL0:LONG.V0
TCELL1:LONG.V1TCELL0:LONG.V1
TCELL1:LONG.V2TCELL0:LONG.V2
TCELL1:LONG.V3TCELL0:LONG.V3
TCELL1:LONG.V4TCELL0:LONG.V4
TCELL1:LONG.V5TCELL0:LONG.V5
TCELL1:LONG.V6TCELL0:LONG.V6
TCELL1:LONG.V7TCELL1:LONG.V7.EXCL
TCELL1:LONG.V7.EXCLTCELL0:LONG.V7, TCELL0:VCLK, TCELL1:LONG.V7
TCELL1:LONG.V8TCELL0:LONG.V8
TCELL1:LONG.V9TCELL1:LONG.V9.EXCL
TCELL1:LONG.V9.EXCLTCELL0:LONG.V9, TCELL1:LONG.V9, TCELL1:VCLK
TCELL1:LONG.IO.V0TCELL0:LONG.IO.V0
TCELL1:LONG.IO.V1TCELL0:LONG.IO.V1
TCELL1:LONG.IO.V2TCELL0:LONG.IO.V2
TCELL1:LONG.IO.V3TCELL0:LONG.IO.V3

Bel BUFF

xc4000xv LLVQ.IO.R.B bel BUFF
PinDirectionWires
OoutputTCELL1:OUT.BUFF

Bel wires

xc4000xv LLVQ.IO.R.B bel wires
WirePins
TCELL1:OUT.BUFFBUFF.O

Bitstream

xc4000xv LLVQ.IO.R.B bittile 0
BitFrame
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 INT:MUX.0.GCLK4[3] INT:MUX.0.GCLK4[4] INT:MUX.0.GCLK4[6] INT:MUX.0.GCLK4[0] INT:MUX.0.GCLK5[5] INT:MUX.0.GCLK5[3] INT:MUX.0.GCLK5[6] INT:MUX.0.GCLK5[0] INT:MUX.0.GCLK6[5] INT:MUX.0.GCLK6[3] INT:MUX.0.GCLK6[6] INT:MUX.0.GCLK6[0] INT:MUX.0.GCLK7[3] INT:MUX.0.GCLK7[4] INT:MUX.0.GCLK7[6] INT:MUX.0.GCLK7[0] ~INT:BUF.0.LONG.V5.1.LONG.V5 ~INT:BUF.0.LONG.V3.1.LONG.V3 ~INT:BUF.0.LONG.V2.1.LONG.V2 ~INT:PASS.1.QUAD.V2.0.0.VCLK ~INT:BUF.0.LONG.V0.1.LONG.V0 ~INT:PASS.0.QUAD.V1.4.0.VCLK ~INT:BUF.0.LONG.V4.1.LONG.V4 ~INT:PASS.1.SINGLE.V3.1.VCLK ~INT:BUF.0.LONG.V1.1.LONG.V1 ~INT:BUF.0.LONG.V6.1.LONG.V6 ~INT:BUF.0.LONG.V7.1.LONG.V7 INT:MUX.1.LONG.V7[0] ~INT:BUF.0.LONG.V8.1.LONG.V8 ~INT:BUF.1.LONG.V9.0.LONG.V9 INT:MUX.0.LONG.V9[0] ~INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 ~INT:PASS.0.IO.DOUBLE.3.E.0.0.ECLK.V ~INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 ~INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 ~INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 INT:MUX.0.GCLK2[4] INT:MUX.0.GCLK2[5] INT:MUX.0.GCLK2[6] INT:MUX.0.GCLK2[0] INT:MUX.0.GCLK0[5] INT:MUX.0.GCLK0[4] INT:MUX.0.GCLK0[6] INT:MUX.0.GCLK0[0] INT:MUX.0.GCLK1[5] INT:MUX.0.GCLK1[4] INT:MUX.0.GCLK1[6] INT:MUX.0.GCLK1[0] INT:MUX.0.GCLK3[4] INT:MUX.0.GCLK3[5] INT:MUX.0.GCLK3[6] INT:MUX.0.GCLK3[0]
0 INT:MUX.0.GCLK4[5] INT:MUX.0.GCLK4[2] INT:MUX.0.GCLK4[1] ~INT:PASS.1.SINGLE.V4.0.VCLK INT:MUX.0.GCLK5[4] INT:MUX.0.GCLK5[2] ~INT:PASS.1.SINGLE.V5.1.VCLK INT:MUX.0.GCLK5[1] INT:MUX.0.GCLK6[4] INT:MUX.0.GCLK6[2] ~INT:PASS.1.SINGLE.V6.0.VCLK INT:MUX.0.GCLK6[1] INT:MUX.0.GCLK7[5] INT:MUX.0.GCLK7[2] INT:MUX.0.GCLK7[1] ~INT:PASS.1.SINGLE.V7.1.VCLK ~INT:BUF.1.LONG.V5.0.LONG.V5 ~INT:BUF.1.LONG.V3.0.LONG.V3 ~INT:BUF.1.LONG.V2.0.LONG.V2 ~INT:PASS.0.QUAD.V2.4.1.VCLK ~INT:BUF.1.LONG.V0.0.LONG.V0 ~INT:PASS.1.QUAD.V0.0.1.VCLK ~INT:BUF.1.LONG.V4.0.LONG.V4 ~INT:PASS.1.SINGLE.V2.0.VCLK ~INT:BUF.1.LONG.V1.0.LONG.V1 ~INT:BUF.1.LONG.V6.0.LONG.V6 INT:MUX.1.LONG.V7[1] ~INT:PASS.1.SINGLE.V0.0.VCLK ~INT:BUF.1.LONG.V8.0.LONG.V8 INT:MUX.0.LONG.V9[1] ~INT:PASS.1.SINGLE.V1.1.VCLK ~INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 ~INT:PASS.0.IO.DOUBLE.0.E.1.0.ECLK.V ~INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 ~INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 ~INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 INT:MUX.0.GCLK2[3] INT:MUX.0.GCLK2[2] - INT:MUX.0.GCLK2[1] INT:MUX.0.GCLK0[3] INT:MUX.0.GCLK0[2] ~INT:PASS.0.IO.DOUBLE.1.E.0.0.ECLK.V INT:MUX.0.GCLK0[1] INT:MUX.0.GCLK1[3] INT:MUX.0.GCLK1[2] ~INT:PASS.0.IO.DOUBLE.1.E.1.0.ECLK.V INT:MUX.0.GCLK1[1] INT:MUX.0.GCLK3[2] INT:MUX.0.GCLK3[3] ~INT:PASS.0.IO.DOUBLE.2.E.1.0.ECLK.V INT:MUX.0.GCLK3[1]
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 0.20.1
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 0.16.1
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 0.18.1
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 0.17.1
INT:BUF.0.LONG.V0.1.LONG.V0 0.31.1
INT:BUF.0.LONG.V1.1.LONG.V1 0.27.1
INT:BUF.0.LONG.V2.1.LONG.V2 0.33.1
INT:BUF.0.LONG.V3.1.LONG.V3 0.34.1
INT:BUF.0.LONG.V4.1.LONG.V4 0.29.1
INT:BUF.0.LONG.V5.1.LONG.V5 0.35.1
INT:BUF.0.LONG.V6.1.LONG.V6 0.26.1
INT:BUF.0.LONG.V7.1.LONG.V7 0.25.1
INT:BUF.0.LONG.V8.1.LONG.V8 0.23.1
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 0.20.0
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 0.16.0
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 0.18.0
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 0.17.0
INT:BUF.1.LONG.V0.0.LONG.V0 0.31.0
INT:BUF.1.LONG.V1.0.LONG.V1 0.27.0
INT:BUF.1.LONG.V2.0.LONG.V2 0.33.0
INT:BUF.1.LONG.V3.0.LONG.V3 0.34.0
INT:BUF.1.LONG.V4.0.LONG.V4 0.29.0
INT:BUF.1.LONG.V5.0.LONG.V5 0.35.0
INT:BUF.1.LONG.V6.0.LONG.V6 0.26.0
INT:BUF.1.LONG.V8.0.LONG.V8 0.23.0
INT:BUF.1.LONG.V9.0.LONG.V9 0.22.1
INT:PASS.0.IO.DOUBLE.0.E.1.0.ECLK.V 0.19.0
INT:PASS.0.IO.DOUBLE.1.E.0.0.ECLK.V 0.9.0
INT:PASS.0.IO.DOUBLE.1.E.1.0.ECLK.V 0.5.0
INT:PASS.0.IO.DOUBLE.2.E.1.0.ECLK.V 0.1.0
INT:PASS.0.IO.DOUBLE.3.E.0.0.ECLK.V 0.19.1
INT:PASS.0.QUAD.V1.4.0.VCLK 0.30.1
INT:PASS.0.QUAD.V2.4.1.VCLK 0.32.0
INT:PASS.1.QUAD.V0.0.1.VCLK 0.30.0
INT:PASS.1.QUAD.V2.0.0.VCLK 0.32.1
INT:PASS.1.SINGLE.V0.0.VCLK 0.24.0
INT:PASS.1.SINGLE.V1.1.VCLK 0.21.0
INT:PASS.1.SINGLE.V2.0.VCLK 0.28.0
INT:PASS.1.SINGLE.V3.1.VCLK 0.28.1
INT:PASS.1.SINGLE.V4.0.VCLK 0.48.0
INT:PASS.1.SINGLE.V5.1.VCLK 0.45.0
INT:PASS.1.SINGLE.V6.0.VCLK 0.41.0
INT:PASS.1.SINGLE.V7.1.VCLK 0.36.0
inverted ~[0]
INT:MUX.0.GCLK0 0.9.1 0.11.1 0.10.1 0.11.0 0.10.0 0.8.0 0.8.1
0.IO.DOUBLE.0.E.1 0 0 1 1 1 1 1
0.IO.DOUBLE.2.E.1 0 1 0 1 1 1 1
0.BUFGE.V1 0 1 1 0 1 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
1.OUT.BUFF 1 1 1 1 1 1 1
INT:MUX.0.GCLK1 0.5.1 0.7.1 0.6.1 0.7.0 0.6.0 0.4.0 0.4.1
0.IO.DOUBLE.0.E.0 0 0 1 1 1 1 1
0.IO.DOUBLE.2.E.0 0 1 0 1 1 1 1
0.ECLK.V 0 1 1 0 1 1 1
0.BUFGE.V0 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK2 0.13.1 0.14.1 0.15.1 0.15.0 0.14.0 0.12.0 0.12.1
0.IO.DOUBLE.1.E.1 0 0 1 1 1 1 1
0.IO.DOUBLE.3.E.1 0 1 0 1 1 1 1
0.ECLK.V 0 1 1 0 1 1 1
1.BUFGLS.H6 1 0 1 1 1 0 1
1.BUFGLS.H7 1 0 1 1 1 1 0
1.BUFGLS.H4 1 1 0 1 1 0 1
1.BUFGLS.H5 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
1.OUT.BUFF 1 1 1 1 1 1 1
INT:MUX.0.GCLK3 0.1.1 0.2.1 0.3.1 0.2.0 0.3.0 0.0.0 0.0.1
0.IO.DOUBLE.1.E.0 0 0 1 1 1 1 1
0.IO.DOUBLE.3.E.0 0 1 0 1 1 1 1
0.BUFGE.V0 0 1 1 0 1 1 1
0.BUFGE.V1 0 1 1 1 0 1 1
1.BUFGLS.H6 1 0 1 1 1 0 1
1.BUFGLS.H7 1 0 1 1 1 1 0
1.BUFGLS.H4 1 1 0 1 1 0 1
1.BUFGLS.H5 1 1 0 1 1 1 0
1.BUFGLS.H0 1 1 1 0 1 0 1
1.BUFGLS.H1 1 1 1 0 1 1 0
1.BUFGLS.H2 1 1 1 1 0 0 1
1.BUFGLS.H3 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK4 0.49.1 0.51.0 0.50.1 0.51.1 0.50.0 0.49.0 0.48.1
0.VCLK 0 0 1 1 1 1 1
1.SINGLE.V4 0 1 0 1 1 1 1
1.QUAD.V1.0 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H2 1 0 1 1 1 0 1
1.BUFGLS.H3 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H4 1 1 1 0 1 0 1
1.BUFGLS.H5 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK5 0.45.1 0.47.1 0.47.0 0.46.1 0.46.0 0.44.0 0.44.1
0.QUAD.V2.3 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V5 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK6 0.41.1 0.43.1 0.43.0 0.42.1 0.42.0 0.40.0 0.40.1
0.QUAD.V2.4 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V6 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK7 0.37.1 0.39.0 0.38.1 0.39.1 0.38.0 0.37.0 0.36.1
0.VCLK 0 0 1 1 1 1 1
1.SINGLE.V7 0 1 0 1 1 1 1
1.QUAD.V2.0 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H2 1 0 1 1 1 0 1
1.BUFGLS.H3 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H4 1 1 1 0 1 0 1
1.BUFGLS.H5 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.LONG.V9 0.22.0 0.21.1
1.LONG.V9 0 0
1.VCLK 0 1
NONE 1 1
INT:MUX.1.LONG.V7 0.25.0 0.24.1
0.LONG.V7 0 0
0.VCLK 0 1
NONE 1 1

Tile LLVQ.IO.R.T

Cells: 2 IRIs: 0

Muxes

xc4000xv LLVQ.IO.R.T muxes
DestinationSources
TCELL0:IO.DOUBLE.0.E.1TCELL1:ECLK.V
TCELL0:IO.DOUBLE.1.E.0TCELL1:ECLK.V
TCELL0:IO.DOUBLE.1.E.1TCELL1:ECLK.V
TCELL0:IO.DOUBLE.2.E.1TCELL1:ECLK.V
TCELL0:IO.DOUBLE.3.E.0TCELL1:ECLK.V
TCELL0:QUAD.V1.4TCELL0:VCLK
TCELL0:QUAD.V2.4TCELL1:VCLK
TCELL0:LONG.V0TCELL1:LONG.V0
TCELL0:LONG.V1TCELL1:LONG.V1
TCELL0:LONG.V2TCELL1:LONG.V2
TCELL0:LONG.V3TCELL1:LONG.V3
TCELL0:LONG.V4TCELL1:LONG.V4
TCELL0:LONG.V5TCELL1:LONG.V5
TCELL0:LONG.V6TCELL1:LONG.V6
TCELL0:LONG.V7TCELL1:LONG.V7.EXCL
TCELL0:LONG.V8TCELL1:LONG.V8
TCELL0:LONG.V9TCELL1:LONG.V9.EXCL
TCELL0:LONG.IO.V0TCELL1:LONG.IO.V0
TCELL0:LONG.IO.V1TCELL1:LONG.IO.V1
TCELL0:LONG.IO.V2TCELL1:LONG.IO.V2
TCELL0:LONG.IO.V3TCELL1:LONG.IO.V3
TCELL0:GCLK0TCELL0:IO.DOUBLE.0.E.1, TCELL0:IO.DOUBLE.2.E.1, TCELL0:BUFGE.V0, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7, TCELL1:OUT.BUFF
TCELL0:GCLK1TCELL0:IO.DOUBLE.0.E.0, TCELL0:IO.DOUBLE.2.E.0, TCELL0:BUFGE.V1, TCELL1:ECLK.V, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK2TCELL0:IO.DOUBLE.1.E.1, TCELL0:IO.DOUBLE.3.E.1, TCELL1:ECLK.V, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7, TCELL1:OUT.BUFF
TCELL0:GCLK3TCELL0:IO.DOUBLE.1.E.0, TCELL0:IO.DOUBLE.3.E.0, TCELL0:BUFGE.V0, TCELL0:BUFGE.V1, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK4TCELL0:VCLK, TCELL1:SINGLE.V4, TCELL1:QUAD.V1.0, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK5TCELL0:QUAD.V2.3, TCELL0:VCLK, TCELL1:SINGLE.V5, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK6TCELL0:QUAD.V2.4, TCELL0:VCLK, TCELL1:SINGLE.V6, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL0:GCLK7TCELL0:VCLK, TCELL1:SINGLE.V7, TCELL1:QUAD.V2.0, TCELL1:VCLK, TCELL1:BUFGLS.H0, TCELL1:BUFGLS.H1, TCELL1:BUFGLS.H2, TCELL1:BUFGLS.H3, TCELL1:BUFGLS.H4, TCELL1:BUFGLS.H5, TCELL1:BUFGLS.H6, TCELL1:BUFGLS.H7
TCELL1:SINGLE.V0TCELL0:VCLK
TCELL1:SINGLE.V1TCELL1:VCLK
TCELL1:SINGLE.V2TCELL0:VCLK
TCELL1:SINGLE.V3TCELL1:VCLK
TCELL1:SINGLE.V4TCELL0:VCLK
TCELL1:SINGLE.V5TCELL1:VCLK
TCELL1:SINGLE.V6TCELL0:VCLK
TCELL1:SINGLE.V7TCELL1:VCLK
TCELL1:QUAD.V0.0TCELL1:VCLK
TCELL1:QUAD.V2.0TCELL0:VCLK
TCELL1:LONG.V0TCELL0:LONG.V0
TCELL1:LONG.V1TCELL0:LONG.V1
TCELL1:LONG.V2TCELL0:LONG.V2
TCELL1:LONG.V3TCELL0:LONG.V3
TCELL1:LONG.V4TCELL0:LONG.V4
TCELL1:LONG.V5TCELL0:LONG.V5
TCELL1:LONG.V6TCELL0:LONG.V6
TCELL1:LONG.V7TCELL1:LONG.V7.EXCL
TCELL1:LONG.V7.EXCLTCELL0:LONG.V7, TCELL0:VCLK, TCELL1:LONG.V7
TCELL1:LONG.V8TCELL0:LONG.V8
TCELL1:LONG.V9TCELL1:LONG.V9.EXCL
TCELL1:LONG.V9.EXCLTCELL0:LONG.V9, TCELL1:LONG.V9, TCELL1:VCLK
TCELL1:LONG.IO.V0TCELL0:LONG.IO.V0
TCELL1:LONG.IO.V1TCELL0:LONG.IO.V1
TCELL1:LONG.IO.V2TCELL0:LONG.IO.V2
TCELL1:LONG.IO.V3TCELL0:LONG.IO.V3

Bel BUFF

xc4000xv LLVQ.IO.R.T bel BUFF
PinDirectionWires
OoutputTCELL1:OUT.BUFF

Bel wires

xc4000xv LLVQ.IO.R.T bel wires
WirePins
TCELL1:OUT.BUFFBUFF.O

Bitstream

xc4000xv LLVQ.IO.R.T bittile 0
BitFrame
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 INT:MUX.0.GCLK4[3] INT:MUX.0.GCLK4[4] INT:MUX.0.GCLK4[6] INT:MUX.0.GCLK4[0] INT:MUX.0.GCLK5[5] INT:MUX.0.GCLK5[3] INT:MUX.0.GCLK5[6] INT:MUX.0.GCLK5[0] INT:MUX.0.GCLK6[5] INT:MUX.0.GCLK6[3] INT:MUX.0.GCLK6[6] INT:MUX.0.GCLK6[0] INT:MUX.0.GCLK7[3] INT:MUX.0.GCLK7[4] INT:MUX.0.GCLK7[6] INT:MUX.0.GCLK7[0] ~INT:BUF.0.LONG.V5.1.LONG.V5 ~INT:BUF.0.LONG.V3.1.LONG.V3 ~INT:BUF.0.LONG.V2.1.LONG.V2 ~INT:PASS.1.QUAD.V2.0.0.VCLK ~INT:BUF.0.LONG.V0.1.LONG.V0 ~INT:PASS.0.QUAD.V1.4.0.VCLK ~INT:BUF.0.LONG.V4.1.LONG.V4 ~INT:PASS.1.SINGLE.V3.1.VCLK ~INT:BUF.0.LONG.V1.1.LONG.V1 ~INT:BUF.0.LONG.V6.1.LONG.V6 ~INT:BUF.0.LONG.V7.1.LONG.V7 INT:MUX.1.LONG.V7[0] ~INT:BUF.0.LONG.V8.1.LONG.V8 ~INT:BUF.1.LONG.V9.0.LONG.V9 INT:MUX.0.LONG.V9[0] ~INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 ~INT:PASS.0.IO.DOUBLE.3.E.0.1.ECLK.V ~INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 ~INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 ~INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 INT:MUX.0.GCLK2[4] INT:MUX.0.GCLK2[5] INT:MUX.0.GCLK2[6] INT:MUX.0.GCLK2[0] INT:MUX.0.GCLK0[5] INT:MUX.0.GCLK0[4] INT:MUX.0.GCLK0[6] INT:MUX.0.GCLK0[0] INT:MUX.0.GCLK1[5] INT:MUX.0.GCLK1[4] INT:MUX.0.GCLK1[6] INT:MUX.0.GCLK1[0] INT:MUX.0.GCLK3[4] INT:MUX.0.GCLK3[5] INT:MUX.0.GCLK3[6] INT:MUX.0.GCLK3[0]
0 INT:MUX.0.GCLK4[5] INT:MUX.0.GCLK4[2] INT:MUX.0.GCLK4[1] ~INT:PASS.1.SINGLE.V4.0.VCLK INT:MUX.0.GCLK5[4] INT:MUX.0.GCLK5[2] ~INT:PASS.1.SINGLE.V5.1.VCLK INT:MUX.0.GCLK5[1] INT:MUX.0.GCLK6[4] INT:MUX.0.GCLK6[2] ~INT:PASS.1.SINGLE.V6.0.VCLK INT:MUX.0.GCLK6[1] INT:MUX.0.GCLK7[5] INT:MUX.0.GCLK7[2] INT:MUX.0.GCLK7[1] ~INT:PASS.1.SINGLE.V7.1.VCLK ~INT:BUF.1.LONG.V5.0.LONG.V5 ~INT:BUF.1.LONG.V3.0.LONG.V3 ~INT:BUF.1.LONG.V2.0.LONG.V2 ~INT:PASS.0.QUAD.V2.4.1.VCLK ~INT:BUF.1.LONG.V0.0.LONG.V0 ~INT:PASS.1.QUAD.V0.0.1.VCLK ~INT:BUF.1.LONG.V4.0.LONG.V4 ~INT:PASS.1.SINGLE.V2.0.VCLK ~INT:BUF.1.LONG.V1.0.LONG.V1 ~INT:BUF.1.LONG.V6.0.LONG.V6 INT:MUX.1.LONG.V7[1] ~INT:PASS.1.SINGLE.V0.0.VCLK ~INT:BUF.1.LONG.V8.0.LONG.V8 INT:MUX.0.LONG.V9[1] ~INT:PASS.1.SINGLE.V1.1.VCLK ~INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 ~INT:PASS.0.IO.DOUBLE.0.E.1.1.ECLK.V ~INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 ~INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 ~INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 INT:MUX.0.GCLK2[3] INT:MUX.0.GCLK2[2] - INT:MUX.0.GCLK2[1] INT:MUX.0.GCLK0[3] INT:MUX.0.GCLK0[2] ~INT:PASS.0.IO.DOUBLE.1.E.0.1.ECLK.V INT:MUX.0.GCLK0[1] INT:MUX.0.GCLK1[2] INT:MUX.0.GCLK1[3] ~INT:PASS.0.IO.DOUBLE.1.E.1.1.ECLK.V INT:MUX.0.GCLK1[1] INT:MUX.0.GCLK3[3] INT:MUX.0.GCLK3[2] ~INT:PASS.0.IO.DOUBLE.2.E.1.1.ECLK.V INT:MUX.0.GCLK3[1]
INT:BUF.0.LONG.IO.V0.1.LONG.IO.V0 0.20.1
INT:BUF.0.LONG.IO.V1.1.LONG.IO.V1 0.16.1
INT:BUF.0.LONG.IO.V2.1.LONG.IO.V2 0.18.1
INT:BUF.0.LONG.IO.V3.1.LONG.IO.V3 0.17.1
INT:BUF.0.LONG.V0.1.LONG.V0 0.31.1
INT:BUF.0.LONG.V1.1.LONG.V1 0.27.1
INT:BUF.0.LONG.V2.1.LONG.V2 0.33.1
INT:BUF.0.LONG.V3.1.LONG.V3 0.34.1
INT:BUF.0.LONG.V4.1.LONG.V4 0.29.1
INT:BUF.0.LONG.V5.1.LONG.V5 0.35.1
INT:BUF.0.LONG.V6.1.LONG.V6 0.26.1
INT:BUF.0.LONG.V7.1.LONG.V7 0.25.1
INT:BUF.0.LONG.V8.1.LONG.V8 0.23.1
INT:BUF.1.LONG.IO.V0.0.LONG.IO.V0 0.20.0
INT:BUF.1.LONG.IO.V1.0.LONG.IO.V1 0.16.0
INT:BUF.1.LONG.IO.V2.0.LONG.IO.V2 0.18.0
INT:BUF.1.LONG.IO.V3.0.LONG.IO.V3 0.17.0
INT:BUF.1.LONG.V0.0.LONG.V0 0.31.0
INT:BUF.1.LONG.V1.0.LONG.V1 0.27.0
INT:BUF.1.LONG.V2.0.LONG.V2 0.33.0
INT:BUF.1.LONG.V3.0.LONG.V3 0.34.0
INT:BUF.1.LONG.V4.0.LONG.V4 0.29.0
INT:BUF.1.LONG.V5.0.LONG.V5 0.35.0
INT:BUF.1.LONG.V6.0.LONG.V6 0.26.0
INT:BUF.1.LONG.V8.0.LONG.V8 0.23.0
INT:BUF.1.LONG.V9.0.LONG.V9 0.22.1
INT:PASS.0.IO.DOUBLE.0.E.1.1.ECLK.V 0.19.0
INT:PASS.0.IO.DOUBLE.1.E.0.1.ECLK.V 0.9.0
INT:PASS.0.IO.DOUBLE.1.E.1.1.ECLK.V 0.5.0
INT:PASS.0.IO.DOUBLE.2.E.1.1.ECLK.V 0.1.0
INT:PASS.0.IO.DOUBLE.3.E.0.1.ECLK.V 0.19.1
INT:PASS.0.QUAD.V1.4.0.VCLK 0.30.1
INT:PASS.0.QUAD.V2.4.1.VCLK 0.32.0
INT:PASS.1.QUAD.V0.0.1.VCLK 0.30.0
INT:PASS.1.QUAD.V2.0.0.VCLK 0.32.1
INT:PASS.1.SINGLE.V0.0.VCLK 0.24.0
INT:PASS.1.SINGLE.V1.1.VCLK 0.21.0
INT:PASS.1.SINGLE.V2.0.VCLK 0.28.0
INT:PASS.1.SINGLE.V3.1.VCLK 0.28.1
INT:PASS.1.SINGLE.V4.0.VCLK 0.48.0
INT:PASS.1.SINGLE.V5.1.VCLK 0.45.0
INT:PASS.1.SINGLE.V6.0.VCLK 0.41.0
INT:PASS.1.SINGLE.V7.1.VCLK 0.36.0
inverted ~[0]
INT:MUX.0.GCLK0 0.9.1 0.11.1 0.10.1 0.11.0 0.10.0 0.8.0 0.8.1
0.IO.DOUBLE.0.E.1 0 0 1 1 1 1 1
0.IO.DOUBLE.2.E.1 0 1 0 1 1 1 1
0.BUFGE.V0 0 1 1 0 1 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
1.OUT.BUFF 1 1 1 1 1 1 1
INT:MUX.0.GCLK1 0.5.1 0.7.1 0.6.1 0.6.0 0.7.0 0.4.0 0.4.1
0.IO.DOUBLE.0.E.0 0 0 1 1 1 1 1
0.IO.DOUBLE.2.E.0 0 1 0 1 1 1 1
0.BUFGE.V1 0 1 1 0 1 1 1
1.ECLK.V 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H0 1 1 1 0 1 0 1
1.BUFGLS.H1 1 1 1 0 1 1 0
1.BUFGLS.H2 1 1 1 1 0 0 1
1.BUFGLS.H3 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK2 0.13.1 0.14.1 0.15.1 0.15.0 0.14.0 0.12.0 0.12.1
0.IO.DOUBLE.1.E.1 0 0 1 1 1 1 1
0.IO.DOUBLE.3.E.1 0 1 0 1 1 1 1
1.ECLK.V 0 1 1 0 1 1 1
1.BUFGLS.H6 1 0 1 1 1 0 1
1.BUFGLS.H7 1 0 1 1 1 1 0
1.BUFGLS.H4 1 1 0 1 1 0 1
1.BUFGLS.H5 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
1.OUT.BUFF 1 1 1 1 1 1 1
INT:MUX.0.GCLK3 0.1.1 0.2.1 0.3.1 0.3.0 0.2.0 0.0.0 0.0.1
0.IO.DOUBLE.1.E.0 0 0 1 1 1 1 1
0.IO.DOUBLE.3.E.0 0 1 0 1 1 1 1
0.BUFGE.V0 0 1 1 0 1 1 1
0.BUFGE.V1 0 1 1 1 0 1 1
1.BUFGLS.H6 1 0 1 1 1 0 1
1.BUFGLS.H7 1 0 1 1 1 1 0
1.BUFGLS.H4 1 1 0 1 1 0 1
1.BUFGLS.H5 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK4 0.49.1 0.51.0 0.50.1 0.51.1 0.50.0 0.49.0 0.48.1
0.VCLK 0 0 1 1 1 1 1
1.SINGLE.V4 0 1 0 1 1 1 1
1.QUAD.V1.0 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H2 1 0 1 1 1 0 1
1.BUFGLS.H3 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H4 1 1 1 0 1 0 1
1.BUFGLS.H5 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK5 0.45.1 0.47.1 0.47.0 0.46.1 0.46.0 0.44.0 0.44.1
0.QUAD.V2.3 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V5 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK6 0.41.1 0.43.1 0.43.0 0.42.1 0.42.0 0.40.0 0.40.1
0.QUAD.V2.4 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V6 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.GCLK7 0.37.1 0.39.0 0.38.1 0.39.1 0.38.0 0.37.0 0.36.1
0.VCLK 0 0 1 1 1 1 1
1.SINGLE.V7 0 1 0 1 1 1 1
1.QUAD.V2.0 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H2 1 0 1 1 1 0 1
1.BUFGLS.H3 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H4 1 1 1 0 1 0 1
1.BUFGLS.H5 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
INT:MUX.0.LONG.V9 0.22.0 0.21.1
1.LONG.V9 0 0
1.VCLK 0 1
NONE 1 1
INT:MUX.1.LONG.V7 0.25.0 0.24.1
0.LONG.V7 0 0
0.VCLK 0 1
NONE 1 1

Tile CLKQ

Cells: 2 IRIs: 0

Bel CLKQ

xc4000xv CLKQ bel CLKQ
PinDirectionWires
O.LL.H.LoutputTCELL0:BUFGLS.H2
O.LL.H.RoutputTCELL1:BUFGLS.H2
O.LL.V.LoutputTCELL0:BUFGLS.H1
O.LL.V.RoutputTCELL1:BUFGLS.H1
O.LR.H.LoutputTCELL0:BUFGLS.H3
O.LR.H.RoutputTCELL1:BUFGLS.H3
O.LR.V.LoutputTCELL0:BUFGLS.H4
O.LR.V.RoutputTCELL1:BUFGLS.H4
O.UL.H.LoutputTCELL0:BUFGLS.H7
O.UL.H.RoutputTCELL1:BUFGLS.H7
O.UL.V.LoutputTCELL0:BUFGLS.H0
O.UL.V.RoutputTCELL1:BUFGLS.H0
O.UR.H.LoutputTCELL0:BUFGLS.H6
O.UR.H.RoutputTCELL1:BUFGLS.H6
O.UR.V.LoutputTCELL0:BUFGLS.H5
O.UR.V.RoutputTCELL1:BUFGLS.H5

Bel wires

xc4000xv CLKQ bel wires
WirePins
TCELL0:BUFGLS.H0CLKQ.O.UL.V.L
TCELL0:BUFGLS.H1CLKQ.O.LL.V.L
TCELL0:BUFGLS.H2CLKQ.O.LL.H.L
TCELL0:BUFGLS.H3CLKQ.O.LR.H.L
TCELL0:BUFGLS.H4CLKQ.O.LR.V.L
TCELL0:BUFGLS.H5CLKQ.O.UR.V.L
TCELL0:BUFGLS.H6CLKQ.O.UR.H.L
TCELL0:BUFGLS.H7CLKQ.O.UL.H.L
TCELL1:BUFGLS.H0CLKQ.O.UL.V.R
TCELL1:BUFGLS.H1CLKQ.O.LL.V.R
TCELL1:BUFGLS.H2CLKQ.O.LL.H.R
TCELL1:BUFGLS.H3CLKQ.O.LR.H.R
TCELL1:BUFGLS.H4CLKQ.O.LR.V.R
TCELL1:BUFGLS.H5CLKQ.O.UR.V.R
TCELL1:BUFGLS.H6CLKQ.O.UR.H.R
TCELL1:BUFGLS.H7CLKQ.O.UL.H.R