Keyboard shortcuts

Press ← or → to navigate between chapters

Press ? to show this help

Press Esc to hide this help

Splitters

Tile LLHC.CLB

Cells: 2

Bel PULLUP_TBUF0_W

xc4000xv LLHC.CLB bel PULLUP_TBUF0_W
PinDirectionWires
OoutputCELL0.LONG.H2

Bel PULLUP_TBUF1_W

xc4000xv LLHC.CLB bel PULLUP_TBUF1_W
PinDirectionWires
OoutputCELL0.LONG.H3

Bel PULLUP_TBUF0_E

xc4000xv LLHC.CLB bel PULLUP_TBUF0_E
PinDirectionWires
OoutputCELL1.LONG.H2

Bel PULLUP_TBUF1_E

xc4000xv LLHC.CLB bel PULLUP_TBUF1_E
PinDirectionWires
OoutputCELL1.LONG.H3

Bel TBUF_SPLITTER0

xc4000xv LLHC.CLB bel TBUF_SPLITTER0
PinDirectionWires
Lin-outCELL0.LONG.H2
Rin-outCELL1.LONG.H2

Bel TBUF_SPLITTER1

xc4000xv LLHC.CLB bel TBUF_SPLITTER1
PinDirectionWires
Lin-outCELL0.LONG.H3
Rin-outCELL1.LONG.H3

Switchbox LLH

xc4000xv LLHC.CLB switchbox LLH
DestinationSourceKind
CELL0.LONG.H0CELL1.LONG.H0buffer
CELL0.LONG.H1CELL1.LONG.H1buffer
CELL0.LONG.H4CELL1.LONG.H4buffer
CELL0.LONG.H5CELL1.LONG.H5buffer
CELL1.LONG.H0CELL0.LONG.H0buffer
CELL1.LONG.H1CELL0.LONG.H1buffer
CELL1.LONG.H4CELL0.LONG.H4buffer
CELL1.LONG.H5CELL0.LONG.H5buffer

Bel wires

xc4000xv LLHC.CLB bel wires
WirePins
CELL0.LONG.H2PULLUP_TBUF0_W.O, TBUF_SPLITTER0.L
CELL0.LONG.H3PULLUP_TBUF1_W.O, TBUF_SPLITTER1.L
CELL1.LONG.H2PULLUP_TBUF0_E.O, TBUF_SPLITTER0.R
CELL1.LONG.H3PULLUP_TBUF1_E.O, TBUF_SPLITTER1.R

Bitstream

xc4000xv LLHC.CLB rect R0
BitFrame
F1 F0
B11 - ~TBUF_SPLITTER1:BUF_W
B10 ~PULLUP_TBUF1_W:ENABLE ~TBUF_SPLITTER1:BUF_E
B9 - -
B8 - -
B7 ~PULLUP_TBUF1_E:ENABLE -
B6 - -
B5 ~TBUF_SPLITTER1:PASS -
B4 - -
B3 - ~LLH:BUF.0.LONG.H5.1.LONG.H5
B2 - ~LLH:BUF.1.LONG.H5.0.LONG.H5
B1 - ~LLH:BUF.0.LONG.H4.1.LONG.H4
B0 - ~LLH:BUF.1.LONG.H4.0.LONG.H4
xc4000xv LLHC.CLB rect R1
BitFrame
F1 F0
B9 ~TBUF_SPLITTER0:BUF_W ~PULLUP_TBUF0_E:ENABLE
B8 ~TBUF_SPLITTER0:BUF_E -
B7 - ~LLH:BUF.1.LONG.H1.0.LONG.H1
B6 ~TBUF_SPLITTER0:PASS ~LLH:BUF.0.LONG.H0.1.LONG.H0
B5 - ~LLH:BUF.1.LONG.H0.0.LONG.H0
B4 ~PULLUP_TBUF0_W:ENABLE ~LLH:BUF.0.LONG.H1.1.LONG.H1
B3 - -
B2 - -
B1 - -
B0 - -
LLH:BUF.0.LONG.H0.1.LONG.H0 1.F0.B6
LLH:BUF.0.LONG.H1.1.LONG.H1 1.F0.B4
LLH:BUF.0.LONG.H4.1.LONG.H4 0.F0.B1
LLH:BUF.0.LONG.H5.1.LONG.H5 0.F0.B3
LLH:BUF.1.LONG.H0.0.LONG.H0 1.F0.B5
LLH:BUF.1.LONG.H1.0.LONG.H1 1.F0.B7
LLH:BUF.1.LONG.H4.0.LONG.H4 0.F0.B0
LLH:BUF.1.LONG.H5.0.LONG.H5 0.F0.B2
PULLUP_TBUF0_E:ENABLE 1.F0.B9
PULLUP_TBUF0_W:ENABLE 1.F1.B4
PULLUP_TBUF1_E:ENABLE 0.F1.B7
PULLUP_TBUF1_W:ENABLE 0.F1.B10
TBUF_SPLITTER0:BUF_E 1.F1.B8
TBUF_SPLITTER0:BUF_W 1.F1.B9
TBUF_SPLITTER0:PASS 1.F1.B6
TBUF_SPLITTER1:BUF_E 0.F0.B10
TBUF_SPLITTER1:BUF_W 0.F0.B11
TBUF_SPLITTER1:PASS 0.F1.B5
inverted ~[0]

Tile LLHC.CLB.B

Cells: 2

Bel PULLUP_TBUF0_W

xc4000xv LLHC.CLB.B bel PULLUP_TBUF0_W
PinDirectionWires
OoutputCELL0.LONG.H2

Bel PULLUP_TBUF1_W

xc4000xv LLHC.CLB.B bel PULLUP_TBUF1_W
PinDirectionWires
OoutputCELL0.LONG.H3

Bel PULLUP_TBUF0_E

xc4000xv LLHC.CLB.B bel PULLUP_TBUF0_E
PinDirectionWires
OoutputCELL1.LONG.H2

Bel PULLUP_TBUF1_E

xc4000xv LLHC.CLB.B bel PULLUP_TBUF1_E
PinDirectionWires
OoutputCELL1.LONG.H3

Bel TBUF_SPLITTER0

xc4000xv LLHC.CLB.B bel TBUF_SPLITTER0
PinDirectionWires
Lin-outCELL0.LONG.H2
Rin-outCELL1.LONG.H2

Bel TBUF_SPLITTER1

xc4000xv LLHC.CLB.B bel TBUF_SPLITTER1
PinDirectionWires
Lin-outCELL0.LONG.H3
Rin-outCELL1.LONG.H3

Switchbox LLH

xc4000xv LLHC.CLB.B switchbox LLH
DestinationSourceKind
CELL0.LONG.H0CELL1.LONG.H0buffer
CELL0.LONG.H1CELL1.LONG.H1buffer
CELL0.LONG.H4CELL1.LONG.H4buffer
CELL0.LONG.H5CELL1.LONG.H5buffer
CELL1.LONG.H0CELL0.LONG.H0buffer
CELL1.LONG.H1CELL0.LONG.H1buffer
CELL1.LONG.H4CELL0.LONG.H4buffer
CELL1.LONG.H5CELL0.LONG.H5buffer

Bel wires

xc4000xv LLHC.CLB.B bel wires
WirePins
CELL0.LONG.H2PULLUP_TBUF0_W.O, TBUF_SPLITTER0.L
CELL0.LONG.H3PULLUP_TBUF1_W.O, TBUF_SPLITTER1.L
CELL1.LONG.H2PULLUP_TBUF0_E.O, TBUF_SPLITTER0.R
CELL1.LONG.H3PULLUP_TBUF1_E.O, TBUF_SPLITTER1.R

Bitstream

xc4000xv LLHC.CLB.B rect R0
BitFrame
F1 F0
B11 - ~TBUF_SPLITTER1:BUF_W
B10 ~PULLUP_TBUF1_W:ENABLE ~TBUF_SPLITTER1:BUF_E
B9 - -
B8 - -
B7 ~PULLUP_TBUF1_E:ENABLE -
B6 - -
B5 ~TBUF_SPLITTER1:PASS -
B4 - -
B3 - ~LLH:BUF.0.LONG.H5.1.LONG.H5
B2 - ~LLH:BUF.1.LONG.H5.0.LONG.H5
B1 - ~LLH:BUF.0.LONG.H4.1.LONG.H4
B0 - ~LLH:BUF.1.LONG.H4.0.LONG.H4
xc4000xv LLHC.CLB.B rect R1
BitFrame
F1 F0
B15 ~LLH:BUF.1.LONG.H0.0.LONG.H0 ~LLH:BUF.0.LONG.H0.1.LONG.H0
B14 ~LLH:BUF.1.LONG.H1.0.LONG.H1 ~TBUF_SPLITTER0:PASS
B13 - ~LLH:BUF.0.LONG.H1.1.LONG.H1
B12 - ~PULLUP_TBUF0_E:ENABLE
B11 ~TBUF_SPLITTER0:BUF_E ~TBUF_SPLITTER0:BUF_W
B10 - -
B9 - -
B8 - -
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - -
B0 - -
xc4000xv LLHC.CLB.B rect R2
BitFrame
F0
B12 ~PULLUP_TBUF0_W:ENABLE
B11 -
B10 -
B9 -
B8 -
B7 -
B6 -
B5 -
B4 -
B3 -
B2 -
B1 -
B0 -
LLH:BUF.0.LONG.H0.1.LONG.H0 1.F0.B15
LLH:BUF.0.LONG.H1.1.LONG.H1 1.F0.B13
LLH:BUF.0.LONG.H4.1.LONG.H4 0.F0.B1
LLH:BUF.0.LONG.H5.1.LONG.H5 0.F0.B3
LLH:BUF.1.LONG.H0.0.LONG.H0 1.F1.B15
LLH:BUF.1.LONG.H1.0.LONG.H1 1.F1.B14
LLH:BUF.1.LONG.H4.0.LONG.H4 0.F0.B0
LLH:BUF.1.LONG.H5.0.LONG.H5 0.F0.B2
PULLUP_TBUF0_E:ENABLE 1.F0.B12
PULLUP_TBUF0_W:ENABLE 2.F0.B12
PULLUP_TBUF1_E:ENABLE 0.F1.B7
PULLUP_TBUF1_W:ENABLE 0.F1.B10
TBUF_SPLITTER0:BUF_E 1.F1.B11
TBUF_SPLITTER0:BUF_W 1.F0.B11
TBUF_SPLITTER0:PASS 1.F0.B14
TBUF_SPLITTER1:BUF_E 0.F0.B10
TBUF_SPLITTER1:BUF_W 0.F0.B11
TBUF_SPLITTER1:PASS 0.F1.B5
inverted ~[0]

Tile LLHC.IO.B

Cells: 2

Bel PULLUP_DEC0_W

xc4000xv LLHC.IO.B bel PULLUP_DEC0_W
PinDirectionWires
OoutputCELL0.DEC.H0

Bel PULLUP_DEC1_W

xc4000xv LLHC.IO.B bel PULLUP_DEC1_W
PinDirectionWires
OoutputCELL0.DEC.H1

Bel PULLUP_DEC2_W

xc4000xv LLHC.IO.B bel PULLUP_DEC2_W
PinDirectionWires
OoutputCELL0.DEC.H2

Bel PULLUP_DEC3_W

xc4000xv LLHC.IO.B bel PULLUP_DEC3_W
PinDirectionWires
OoutputCELL0.DEC.H3

Bel PULLUP_DEC0_E

xc4000xv LLHC.IO.B bel PULLUP_DEC0_E
PinDirectionWires
OoutputCELL1.DEC.H0

Bel PULLUP_DEC1_E

xc4000xv LLHC.IO.B bel PULLUP_DEC1_E
PinDirectionWires
OoutputCELL1.DEC.H1

Bel PULLUP_DEC2_E

xc4000xv LLHC.IO.B bel PULLUP_DEC2_E
PinDirectionWires
OoutputCELL1.DEC.H2

Bel PULLUP_DEC3_E

xc4000xv LLHC.IO.B bel PULLUP_DEC3_E
PinDirectionWires
OoutputCELL1.DEC.H3

Switchbox LLH

xc4000xv LLHC.IO.B switchbox LLH
DestinationSourceKind
CELL0.LONG.H3CELL1.LONG.H3buffer
CELL0.LONG.H4CELL1.LONG.H4buffer
CELL0.LONG.H5CELL1.LONG.H5buffer
CELL0.LONG.IO.H0CELL1.LONG.IO.H0buffer
CELL0.LONG.IO.H1CELL1.LONG.IO.H1buffer
CELL0.LONG.IO.H2CELL1.LONG.IO.H2buffer
CELL0.LONG.IO.H3CELL1.LONG.IO.H3buffer
CELL0.DEC.H0CELL1.DEC.H0bidirectional pass transistor
CELL0.DEC.H1CELL1.DEC.H1bidirectional pass transistor
CELL0.DEC.H2CELL1.DEC.H2bidirectional pass transistor
CELL0.DEC.H3CELL1.DEC.H3bidirectional pass transistor
CELL1.LONG.H3CELL0.LONG.H3buffer
CELL1.LONG.H4CELL0.LONG.H4buffer
CELL1.LONG.H5CELL0.LONG.H5buffer
CELL1.LONG.IO.H0CELL0.LONG.IO.H0buffer
CELL1.LONG.IO.H1CELL0.LONG.IO.H1buffer
CELL1.LONG.IO.H2CELL0.LONG.IO.H2buffer
CELL1.LONG.IO.H3CELL0.LONG.IO.H3buffer
CELL1.DEC.H0CELL0.DEC.H0bidirectional pass transistor
CELL1.DEC.H1CELL0.DEC.H1bidirectional pass transistor
CELL1.DEC.H2CELL0.DEC.H2bidirectional pass transistor
CELL1.DEC.H3CELL0.DEC.H3bidirectional pass transistor

Bel wires

xc4000xv LLHC.IO.B bel wires
WirePins
CELL0.DEC.H0PULLUP_DEC0_W.O
CELL0.DEC.H1PULLUP_DEC1_W.O
CELL0.DEC.H2PULLUP_DEC2_W.O
CELL0.DEC.H3PULLUP_DEC3_W.O
CELL1.DEC.H0PULLUP_DEC0_E.O
CELL1.DEC.H1PULLUP_DEC1_E.O
CELL1.DEC.H2PULLUP_DEC2_E.O
CELL1.DEC.H3PULLUP_DEC3_E.O

Bitstream

xc4000xv LLHC.IO.B rect R0
BitFrame
F1 F0
B13 ~PULLUP_DEC1_E:ENABLE -
B12 ~PULLUP_DEC2_W:ENABLE -
B11 - -
B10 ~PULLUP_DEC2_E:ENABLE ~LLH:BIPASS.0.DEC.H1.1.DEC.H1
B9 ~LLH:BUF.1.LONG.H3.0.LONG.H3 -
B8 - ~LLH:BUF.0.LONG.H3.1.LONG.H3
B7 ~LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1 ~LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0
B6 ~LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0 -
B5 ~LLH:BUF.1.LONG.H4.0.LONG.H4 ~LLH:BUF.0.LONG.H4.1.LONG.H4
B4 ~LLH:BIPASS.0.DEC.H3.1.DEC.H3 ~LLH:BIPASS.0.DEC.H2.1.DEC.H2
B3 ~LLH:BUF.1.LONG.H5.0.LONG.H5 ~LLH:BUF.0.LONG.H5.1.LONG.H5
B2 ~LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2 -
B1 ~LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3 ~PULLUP_DEC3_E:ENABLE
B0 ~PULLUP_DEC3_W:ENABLE ~LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3
xc4000xv LLHC.IO.B rect R1
BitFrame
F0
B15 ~PULLUP_DEC1_W:ENABLE
B14 ~PULLUP_DEC0_E:ENABLE
B13 ~PULLUP_DEC0_W:ENABLE
B12 -
B11 -
B10 ~LLH:BIPASS.0.DEC.H0.1.DEC.H0
B9 -
B8 -
B7 -
B6 -
B5 -
B4 ~LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1
B3 -
B2 ~LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2
B1 -
B0 -
LLH:BIPASS.0.DEC.H0.1.DEC.H0 1.F0.B10
LLH:BIPASS.0.DEC.H1.1.DEC.H1 0.F0.B10
LLH:BIPASS.0.DEC.H2.1.DEC.H2 0.F0.B4
LLH:BIPASS.0.DEC.H3.1.DEC.H3 0.F1.B4
LLH:BUF.0.LONG.H3.1.LONG.H3 0.F0.B8
LLH:BUF.0.LONG.H4.1.LONG.H4 0.F0.B5
LLH:BUF.0.LONG.H5.1.LONG.H5 0.F0.B3
LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0 0.F0.B7
LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1 1.F0.B4
LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2 1.F0.B2
LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3 0.F0.B0
LLH:BUF.1.LONG.H3.0.LONG.H3 0.F1.B9
LLH:BUF.1.LONG.H4.0.LONG.H4 0.F1.B5
LLH:BUF.1.LONG.H5.0.LONG.H5 0.F1.B3
LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0 0.F1.B6
LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1 0.F1.B7
LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2 0.F1.B2
LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3 0.F1.B1
PULLUP_DEC0_E:ENABLE 1.F0.B14
PULLUP_DEC0_W:ENABLE 1.F0.B13
PULLUP_DEC1_E:ENABLE 0.F1.B13
PULLUP_DEC1_W:ENABLE 1.F0.B15
PULLUP_DEC2_E:ENABLE 0.F1.B10
PULLUP_DEC2_W:ENABLE 0.F1.B12
PULLUP_DEC3_E:ENABLE 0.F0.B1
PULLUP_DEC3_W:ENABLE 0.F1.B0
inverted ~[0]

Tile LLHC.IO.T

Cells: 2

Bel PULLUP_DEC0_W

xc4000xv LLHC.IO.T bel PULLUP_DEC0_W
PinDirectionWires
OoutputCELL0.DEC.H0

Bel PULLUP_DEC1_W

xc4000xv LLHC.IO.T bel PULLUP_DEC1_W
PinDirectionWires
OoutputCELL0.DEC.H1

Bel PULLUP_DEC2_W

xc4000xv LLHC.IO.T bel PULLUP_DEC2_W
PinDirectionWires
OoutputCELL0.DEC.H2

Bel PULLUP_DEC3_W

xc4000xv LLHC.IO.T bel PULLUP_DEC3_W
PinDirectionWires
OoutputCELL0.DEC.H3

Bel PULLUP_DEC0_E

xc4000xv LLHC.IO.T bel PULLUP_DEC0_E
PinDirectionWires
OoutputCELL1.DEC.H0

Bel PULLUP_DEC1_E

xc4000xv LLHC.IO.T bel PULLUP_DEC1_E
PinDirectionWires
OoutputCELL1.DEC.H1

Bel PULLUP_DEC2_E

xc4000xv LLHC.IO.T bel PULLUP_DEC2_E
PinDirectionWires
OoutputCELL1.DEC.H2

Bel PULLUP_DEC3_E

xc4000xv LLHC.IO.T bel PULLUP_DEC3_E
PinDirectionWires
OoutputCELL1.DEC.H3

Switchbox LLH

xc4000xv LLHC.IO.T switchbox LLH
DestinationSourceKind
CELL0.LONG.H0CELL1.LONG.H0buffer
CELL0.LONG.H1CELL1.LONG.H1buffer
CELL0.LONG.H2CELL1.LONG.H2buffer
CELL0.LONG.IO.H0CELL1.LONG.IO.H0buffer
CELL0.LONG.IO.H1CELL1.LONG.IO.H1buffer
CELL0.LONG.IO.H2CELL1.LONG.IO.H2buffer
CELL0.LONG.IO.H3CELL1.LONG.IO.H3buffer
CELL0.DEC.H0CELL1.DEC.H0bidirectional pass transistor
CELL0.DEC.H1CELL1.DEC.H1bidirectional pass transistor
CELL0.DEC.H2CELL1.DEC.H2bidirectional pass transistor
CELL0.DEC.H3CELL1.DEC.H3bidirectional pass transistor
CELL1.LONG.H0CELL0.LONG.H0buffer
CELL1.LONG.H1CELL0.LONG.H1buffer
CELL1.LONG.H2CELL0.LONG.H2buffer
CELL1.LONG.IO.H0CELL0.LONG.IO.H0buffer
CELL1.LONG.IO.H1CELL0.LONG.IO.H1buffer
CELL1.LONG.IO.H2CELL0.LONG.IO.H2buffer
CELL1.LONG.IO.H3CELL0.LONG.IO.H3buffer
CELL1.DEC.H0CELL0.DEC.H0bidirectional pass transistor
CELL1.DEC.H1CELL0.DEC.H1bidirectional pass transistor
CELL1.DEC.H2CELL0.DEC.H2bidirectional pass transistor
CELL1.DEC.H3CELL0.DEC.H3bidirectional pass transistor

Bel wires

xc4000xv LLHC.IO.T bel wires
WirePins
CELL0.DEC.H0PULLUP_DEC0_W.O
CELL0.DEC.H1PULLUP_DEC1_W.O
CELL0.DEC.H2PULLUP_DEC2_W.O
CELL0.DEC.H3PULLUP_DEC3_W.O
CELL1.DEC.H0PULLUP_DEC0_E.O
CELL1.DEC.H1PULLUP_DEC1_E.O
CELL1.DEC.H2PULLUP_DEC2_E.O
CELL1.DEC.H3PULLUP_DEC3_E.O

Bitstream

xc4000xv LLHC.IO.T rect R0
BitFrame
F1 F0
B7 ~PULLUP_DEC1_E:ENABLE ~PULLUP_DEC1_W:ENABLE
B6 ~LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3 ~LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3
B5 ~LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2 ~LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2
B4 ~PULLUP_DEC2_W:ENABLE ~PULLUP_DEC2_E:ENABLE
B3 ~PULLUP_DEC0_E:ENABLE ~PULLUP_DEC0_W:ENABLE
B2 ~LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1 ~LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1
B1 ~PULLUP_DEC3_W:ENABLE ~PULLUP_DEC3_E:ENABLE
B0 - -
xc4000xv LLHC.IO.T rect R1
BitFrame
F1 F0
B9 ~LLH:BUF.0.LONG.H2.1.LONG.H2 -
B8 ~LLH:BUF.1.LONG.H2.0.LONG.H2 -
B7 - ~LLH:BUF.1.LONG.H1.0.LONG.H1
B6 - ~LLH:BUF.0.LONG.H0.1.LONG.H0
B5 - ~LLH:BUF.1.LONG.H0.0.LONG.H0
B4 - ~LLH:BUF.0.LONG.H1.1.LONG.H1
B3 - -
B2 - -
B1 - -
B0 - -
xc4000xv LLHC.IO.T rect R2
BitFrame
F0
B8 ~LLH:BIPASS.0.DEC.H2.1.DEC.H2
B7 -
B6 ~LLH:BIPASS.0.DEC.H1.1.DEC.H1
B5 -
B4 ~LLH:BIPASS.0.DEC.H0.1.DEC.H0
B3 ~LLH:BIPASS.0.DEC.H3.1.DEC.H3
B2 ~LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0
B1 ~LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0
B0 -
LLH:BIPASS.0.DEC.H0.1.DEC.H0 2.F0.B4
LLH:BIPASS.0.DEC.H1.1.DEC.H1 2.F0.B6
LLH:BIPASS.0.DEC.H2.1.DEC.H2 2.F0.B8
LLH:BIPASS.0.DEC.H3.1.DEC.H3 2.F0.B3
LLH:BUF.0.LONG.H0.1.LONG.H0 1.F0.B6
LLH:BUF.0.LONG.H1.1.LONG.H1 1.F0.B4
LLH:BUF.0.LONG.H2.1.LONG.H2 1.F1.B9
LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0 2.F0.B1
LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1 0.F1.B2
LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2 0.F1.B5
LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3 0.F1.B6
LLH:BUF.1.LONG.H0.0.LONG.H0 1.F0.B5
LLH:BUF.1.LONG.H1.0.LONG.H1 1.F0.B7
LLH:BUF.1.LONG.H2.0.LONG.H2 1.F1.B8
LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0 2.F0.B2
LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1 0.F0.B2
LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2 0.F0.B5
LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3 0.F0.B6
PULLUP_DEC0_E:ENABLE 0.F1.B3
PULLUP_DEC0_W:ENABLE 0.F0.B3
PULLUP_DEC1_E:ENABLE 0.F1.B7
PULLUP_DEC1_W:ENABLE 0.F0.B7
PULLUP_DEC2_E:ENABLE 0.F0.B4
PULLUP_DEC2_W:ENABLE 0.F1.B4
PULLUP_DEC3_E:ENABLE 0.F0.B1
PULLUP_DEC3_W:ENABLE 0.F1.B1
inverted ~[0]

Tile LLHQ.CLB

Cells: 2

Bel PULLUP_TBUF0_W

xc4000xv LLHQ.CLB bel PULLUP_TBUF0_W
PinDirectionWires
OoutputCELL0.LONG.H2

Bel PULLUP_TBUF1_W

xc4000xv LLHQ.CLB bel PULLUP_TBUF1_W
PinDirectionWires
OoutputCELL0.LONG.H3

Bel PULLUP_TBUF0_E

xc4000xv LLHQ.CLB bel PULLUP_TBUF0_E
PinDirectionWires
OoutputCELL0.LONG.H2

Bel PULLUP_TBUF1_E

xc4000xv LLHQ.CLB bel PULLUP_TBUF1_E
PinDirectionWires
OoutputCELL0.LONG.H3

Switchbox LLH

xc4000xv LLHQ.CLB switchbox LLH
DestinationSourceKind
CELL0.LONG.H0CELL1.LONG.H0buffer
CELL0.LONG.H1CELL1.LONG.H1buffer
CELL0.LONG.H4CELL1.LONG.H4buffer
CELL0.LONG.H5CELL1.LONG.H5buffer
CELL1.LONG.H0CELL0.LONG.H0buffer
CELL1.LONG.H1CELL0.LONG.H1buffer
CELL1.LONG.H4CELL0.LONG.H4buffer
CELL1.LONG.H5CELL0.LONG.H5buffer

Bel wires

xc4000xv LLHQ.CLB bel wires
WirePins
CELL0.LONG.H2PULLUP_TBUF0_W.O, PULLUP_TBUF0_E.O
CELL0.LONG.H3PULLUP_TBUF1_W.O, PULLUP_TBUF1_E.O

Bitstream

xc4000xv LLHQ.CLB rect R0
BitFrame
F0
B5 ~PULLUP_TBUF1_E:ENABLE
B4 ~PULLUP_TBUF1_W:ENABLE
B3 ~LLH:BUF.0.LONG.H4.1.LONG.H4
B2 ~LLH:BUF.1.LONG.H4.0.LONG.H4
B1 ~LLH:BUF.1.LONG.H5.0.LONG.H5
B0 ~LLH:BUF.0.LONG.H5.1.LONG.H5
xc4000xv LLHQ.CLB rect R1
BitFrame
F0
B11 ~LLH:BUF.1.LONG.H0.0.LONG.H0
B10 ~LLH:BUF.0.LONG.H0.1.LONG.H0
B9 ~LLH:BUF.1.LONG.H1.0.LONG.H1
B8 ~LLH:BUF.0.LONG.H1.1.LONG.H1
B7 ~PULLUP_TBUF0_E:ENABLE
B6 ~PULLUP_TBUF0_W:ENABLE
B5 -
B4 -
B3 -
B2 -
B1 -
B0 -
LLH:BUF.0.LONG.H0.1.LONG.H0 1.F0.B10
LLH:BUF.0.LONG.H1.1.LONG.H1 1.F0.B8
LLH:BUF.0.LONG.H4.1.LONG.H4 0.F0.B3
LLH:BUF.0.LONG.H5.1.LONG.H5 0.F0.B0
LLH:BUF.1.LONG.H0.0.LONG.H0 1.F0.B11
LLH:BUF.1.LONG.H1.0.LONG.H1 1.F0.B9
LLH:BUF.1.LONG.H4.0.LONG.H4 0.F0.B2
LLH:BUF.1.LONG.H5.0.LONG.H5 0.F0.B1
PULLUP_TBUF0_E:ENABLE 1.F0.B7
PULLUP_TBUF0_W:ENABLE 1.F0.B6
PULLUP_TBUF1_E:ENABLE 0.F0.B5
PULLUP_TBUF1_W:ENABLE 0.F0.B4
inverted ~[0]

Tile LLHQ.CLB.B

Cells: 2

Bel PULLUP_TBUF0_W

xc4000xv LLHQ.CLB.B bel PULLUP_TBUF0_W
PinDirectionWires
OoutputCELL0.LONG.H2

Bel PULLUP_TBUF1_W

xc4000xv LLHQ.CLB.B bel PULLUP_TBUF1_W
PinDirectionWires
OoutputCELL0.LONG.H3

Bel PULLUP_TBUF0_E

xc4000xv LLHQ.CLB.B bel PULLUP_TBUF0_E
PinDirectionWires
OoutputCELL0.LONG.H2

Bel PULLUP_TBUF1_E

xc4000xv LLHQ.CLB.B bel PULLUP_TBUF1_E
PinDirectionWires
OoutputCELL0.LONG.H3

Switchbox LLH

xc4000xv LLHQ.CLB.B switchbox LLH
DestinationSourceKind
CELL0.LONG.H0CELL1.LONG.H0buffer
CELL0.LONG.H1CELL1.LONG.H1buffer
CELL0.LONG.H4CELL1.LONG.H4buffer
CELL0.LONG.H5CELL1.LONG.H5buffer
CELL1.LONG.H0CELL0.LONG.H0buffer
CELL1.LONG.H1CELL0.LONG.H1buffer
CELL1.LONG.H4CELL0.LONG.H4buffer
CELL1.LONG.H5CELL0.LONG.H5buffer

Bel wires

xc4000xv LLHQ.CLB.B bel wires
WirePins
CELL0.LONG.H2PULLUP_TBUF0_W.O, PULLUP_TBUF0_E.O
CELL0.LONG.H3PULLUP_TBUF1_W.O, PULLUP_TBUF1_E.O

Bitstream

xc4000xv LLHQ.CLB.B rect R0
BitFrame
F0
B5 ~PULLUP_TBUF1_E:ENABLE
B4 ~PULLUP_TBUF1_W:ENABLE
B3 ~LLH:BUF.0.LONG.H4.1.LONG.H4
B2 ~LLH:BUF.1.LONG.H4.0.LONG.H4
B1 ~LLH:BUF.1.LONG.H5.0.LONG.H5
B0 ~LLH:BUF.0.LONG.H5.1.LONG.H5
xc4000xv LLHQ.CLB.B rect R1
BitFrame
xc4000xv LLHQ.CLB.B rect R2
BitFrame
F0
B15 ~PULLUP_TBUF0_E:ENABLE
B14 ~PULLUP_TBUF0_W:ENABLE
B13 ~LLH:BUF.0.LONG.H0.1.LONG.H0
B12 ~LLH:BUF.1.LONG.H0.0.LONG.H0
B11 ~LLH:BUF.0.LONG.H1.1.LONG.H1
B10 ~LLH:BUF.1.LONG.H1.0.LONG.H1
B9 -
B8 -
B7 -
B6 -
B5 -
B4 -
B3 -
B2 -
B1 -
B0 -
LLH:BUF.0.LONG.H0.1.LONG.H0 2.F0.B13
LLH:BUF.0.LONG.H1.1.LONG.H1 2.F0.B11
LLH:BUF.0.LONG.H4.1.LONG.H4 0.F0.B3
LLH:BUF.0.LONG.H5.1.LONG.H5 0.F0.B0
LLH:BUF.1.LONG.H0.0.LONG.H0 2.F0.B12
LLH:BUF.1.LONG.H1.0.LONG.H1 2.F0.B10
LLH:BUF.1.LONG.H4.0.LONG.H4 0.F0.B2
LLH:BUF.1.LONG.H5.0.LONG.H5 0.F0.B1
PULLUP_TBUF0_E:ENABLE 2.F0.B15
PULLUP_TBUF0_W:ENABLE 2.F0.B14
PULLUP_TBUF1_E:ENABLE 0.F0.B5
PULLUP_TBUF1_W:ENABLE 0.F0.B4
inverted ~[0]

Tile LLHQ.CLB.T

Cells: 2

Bel PULLUP_TBUF0_W

xc4000xv LLHQ.CLB.T bel PULLUP_TBUF0_W
PinDirectionWires
OoutputCELL0.LONG.H2

Bel PULLUP_TBUF1_W

xc4000xv LLHQ.CLB.T bel PULLUP_TBUF1_W
PinDirectionWires
OoutputCELL0.LONG.H3

Bel PULLUP_TBUF0_E

xc4000xv LLHQ.CLB.T bel PULLUP_TBUF0_E
PinDirectionWires
OoutputCELL0.LONG.H2

Bel PULLUP_TBUF1_E

xc4000xv LLHQ.CLB.T bel PULLUP_TBUF1_E
PinDirectionWires
OoutputCELL0.LONG.H3

Switchbox LLH

xc4000xv LLHQ.CLB.T switchbox LLH
DestinationSourceKind
CELL0.LONG.H0CELL1.LONG.H0buffer
CELL0.LONG.H1CELL1.LONG.H1buffer
CELL0.LONG.H4CELL1.LONG.H4buffer
CELL0.LONG.H5CELL1.LONG.H5buffer
CELL1.LONG.H0CELL0.LONG.H0buffer
CELL1.LONG.H1CELL0.LONG.H1buffer
CELL1.LONG.H4CELL0.LONG.H4buffer
CELL1.LONG.H5CELL0.LONG.H5buffer

Bel wires

xc4000xv LLHQ.CLB.T bel wires
WirePins
CELL0.LONG.H2PULLUP_TBUF0_W.O, PULLUP_TBUF0_E.O
CELL0.LONG.H3PULLUP_TBUF1_W.O, PULLUP_TBUF1_E.O

Bitstream

xc4000xv LLHQ.CLB.T rect R0
BitFrame
F0
B5 ~PULLUP_TBUF1_E:ENABLE
B4 ~PULLUP_TBUF1_W:ENABLE
B3 ~LLH:BUF.0.LONG.H4.1.LONG.H4
B2 ~LLH:BUF.1.LONG.H4.0.LONG.H4
B1 ~LLH:BUF.1.LONG.H5.0.LONG.H5
B0 ~LLH:BUF.0.LONG.H5.1.LONG.H5
xc4000xv LLHQ.CLB.T rect R1
BitFrame
F0
B11 ~LLH:BUF.1.LONG.H0.0.LONG.H0
B10 ~LLH:BUF.0.LONG.H0.1.LONG.H0
B9 ~LLH:BUF.1.LONG.H1.0.LONG.H1
B8 ~LLH:BUF.0.LONG.H1.1.LONG.H1
B7 ~PULLUP_TBUF0_E:ENABLE
B6 ~PULLUP_TBUF0_W:ENABLE
B5 -
B4 -
B3 -
B2 -
B1 -
B0 -
LLH:BUF.0.LONG.H0.1.LONG.H0 1.F0.B10
LLH:BUF.0.LONG.H1.1.LONG.H1 1.F0.B8
LLH:BUF.0.LONG.H4.1.LONG.H4 0.F0.B3
LLH:BUF.0.LONG.H5.1.LONG.H5 0.F0.B0
LLH:BUF.1.LONG.H0.0.LONG.H0 1.F0.B11
LLH:BUF.1.LONG.H1.0.LONG.H1 1.F0.B9
LLH:BUF.1.LONG.H4.0.LONG.H4 0.F0.B2
LLH:BUF.1.LONG.H5.0.LONG.H5 0.F0.B1
PULLUP_TBUF0_E:ENABLE 1.F0.B7
PULLUP_TBUF0_W:ENABLE 1.F0.B6
PULLUP_TBUF1_E:ENABLE 0.F0.B5
PULLUP_TBUF1_W:ENABLE 0.F0.B4
inverted ~[0]

Tile LLHQ.IO.B

Cells: 2

Switchbox LLH

xc4000xv LLHQ.IO.B switchbox LLH
DestinationSourceKind
CELL0.LONG.H3CELL1.LONG.H3buffer
CELL0.LONG.H4CELL1.LONG.H4buffer
CELL0.LONG.H5CELL1.LONG.H5buffer
CELL0.LONG.IO.H0CELL1.LONG.IO.H0buffer
CELL0.LONG.IO.H1CELL1.LONG.IO.H1buffer
CELL0.LONG.IO.H2CELL1.LONG.IO.H2buffer
CELL0.LONG.IO.H3CELL1.LONG.IO.H3buffer
CELL1.LONG.H3CELL0.LONG.H3buffer
CELL1.LONG.H4CELL0.LONG.H4buffer
CELL1.LONG.H5CELL0.LONG.H5buffer
CELL1.LONG.IO.H0CELL0.LONG.IO.H0buffer
CELL1.LONG.IO.H1CELL0.LONG.IO.H1buffer
CELL1.LONG.IO.H2CELL0.LONG.IO.H2buffer
CELL1.LONG.IO.H3CELL0.LONG.IO.H3buffer

Bitstream

xc4000xv LLHQ.IO.B rect R0
BitFrame
F0
B11 ~LLH:BUF.0.LONG.H3.1.LONG.H3
B10 ~LLH:BUF.1.LONG.H3.0.LONG.H3
B9 -
B8 -
B7 ~LLH:BUF.1.LONG.H5.0.LONG.H5
B6 ~LLH:BUF.0.LONG.H5.1.LONG.H5
B5 ~LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1
B4 ~LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1
B3 -
B2 -
B1 ~LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3
B0 ~LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3
xc4000xv LLHQ.IO.B rect R1
BitFrame
F0
B7 ~LLH:BUF.1.LONG.H4.0.LONG.H4
B6 ~LLH:BUF.0.LONG.H4.1.LONG.H4
B5 ~LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0
B4 ~LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0
B3 -
B2 -
B1 ~LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2
B0 ~LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2
LLH:BUF.0.LONG.H3.1.LONG.H3 0.F0.B11
LLH:BUF.0.LONG.H4.1.LONG.H4 1.F0.B6
LLH:BUF.0.LONG.H5.1.LONG.H5 0.F0.B6
LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0 1.F0.B4
LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1 0.F0.B4
LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2 1.F0.B0
LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3 0.F0.B0
LLH:BUF.1.LONG.H3.0.LONG.H3 0.F0.B10
LLH:BUF.1.LONG.H4.0.LONG.H4 1.F0.B7
LLH:BUF.1.LONG.H5.0.LONG.H5 0.F0.B7
LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0 1.F0.B5
LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1 0.F0.B5
LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2 1.F0.B1
LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3 0.F0.B1
inverted ~[0]

Tile LLHQ.IO.T

Cells: 2

Switchbox LLH

xc4000xv LLHQ.IO.T switchbox LLH
DestinationSourceKind
CELL0.LONG.H0CELL1.LONG.H0buffer
CELL0.LONG.H1CELL1.LONG.H1buffer
CELL0.LONG.H2CELL1.LONG.H2buffer
CELL0.LONG.IO.H0CELL1.LONG.IO.H0buffer
CELL0.LONG.IO.H1CELL1.LONG.IO.H1buffer
CELL0.LONG.IO.H2CELL1.LONG.IO.H2buffer
CELL0.LONG.IO.H3CELL1.LONG.IO.H3buffer
CELL1.LONG.H0CELL0.LONG.H0buffer
CELL1.LONG.H1CELL0.LONG.H1buffer
CELL1.LONG.H2CELL0.LONG.H2buffer
CELL1.LONG.IO.H0CELL0.LONG.IO.H0buffer
CELL1.LONG.IO.H1CELL0.LONG.IO.H1buffer
CELL1.LONG.IO.H2CELL0.LONG.IO.H2buffer
CELL1.LONG.IO.H3CELL0.LONG.IO.H3buffer

Bitstream

xc4000xv LLHQ.IO.T rect R0
BitFrame
F0
B8 ~LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3
B7 ~LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3
B6 ~LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2
B5 ~LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2
B4 ~LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1
B3 ~LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1
B2 ~LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0
B1 ~LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0
B0 -
xc4000xv LLHQ.IO.T rect R1
BitFrame
F0
B11 ~LLH:BUF.1.LONG.H0.0.LONG.H0
B10 ~LLH:BUF.0.LONG.H0.1.LONG.H0
B9 ~LLH:BUF.1.LONG.H1.0.LONG.H1
B8 ~LLH:BUF.0.LONG.H1.1.LONG.H1
B7 ~LLH:BUF.1.LONG.H2.0.LONG.H2
B6 ~LLH:BUF.0.LONG.H2.1.LONG.H2
B5 -
B4 -
B3 -
B2 -
B1 -
B0 -
LLH:BUF.0.LONG.H0.1.LONG.H0 1.F0.B10
LLH:BUF.0.LONG.H1.1.LONG.H1 1.F0.B8
LLH:BUF.0.LONG.H2.1.LONG.H2 1.F0.B6
LLH:BUF.0.LONG.IO.H0.1.LONG.IO.H0 0.F0.B2
LLH:BUF.0.LONG.IO.H1.1.LONG.IO.H1 0.F0.B4
LLH:BUF.0.LONG.IO.H2.1.LONG.IO.H2 0.F0.B6
LLH:BUF.0.LONG.IO.H3.1.LONG.IO.H3 0.F0.B8
LLH:BUF.1.LONG.H0.0.LONG.H0 1.F0.B11
LLH:BUF.1.LONG.H1.0.LONG.H1 1.F0.B9
LLH:BUF.1.LONG.H2.0.LONG.H2 1.F0.B7
LLH:BUF.1.LONG.IO.H0.0.LONG.IO.H0 0.F0.B1
LLH:BUF.1.LONG.IO.H1.0.LONG.IO.H1 0.F0.B3
LLH:BUF.1.LONG.IO.H2.0.LONG.IO.H2 0.F0.B5
LLH:BUF.1.LONG.IO.H3.0.LONG.IO.H3 0.F0.B7
inverted ~[0]

Tile LLVC.CLB

Cells: 2

Switchbox LLV

xc4000xv LLVC.CLB switchbox LLV
DestinationSourceKind
CELL0.LONG.V0CELL1.LONG.V0buffer
CELL0.LONG.V1CELL1.LONG.V1buffer
CELL0.LONG.V2CELL1.LONG.V2buffer
CELL0.LONG.V3CELL1.LONG.V3buffer
CELL0.LONG.V4CELL1.LONG.V4buffer
CELL0.LONG.V5CELL1.LONG.V5buffer
CELL0.LONG.V6CELL1.LONG.V6buffer
CELL0.LONG.V7CELL1.LONG.V7buffer
CELL0.LONG.V8CELL1.LONG.V8buffer
CELL0.LONG.V9CELL1.LONG.V9buffer
CELL0.VCLKCELL0.QUAD.V0.4mux
CELL1.SINGLE.V0mux
CELL1.SINGLE.V1mux
CELL1.SINGLE.V2mux
CELL1.SINGLE.V4mux
CELL1.SINGLE.V5mux
CELL1.QUAD.V2.0mux
CELL1.LONG.V0mux
CELL1.LONG.V4mux
CELL1.LONG.V6mux
CELL1.GCLK2mux
CELL1.GCLK5mux
CELL1.LONG.V0CELL0.LONG.V0buffer
CELL1.LONG.V1CELL0.LONG.V1buffer
CELL1.LONG.V2CELL0.LONG.V2buffer
CELL1.LONG.V3CELL0.LONG.V3buffer
CELL1.LONG.V4CELL0.LONG.V4buffer
CELL1.LONG.V5CELL0.LONG.V5buffer
CELL1.LONG.V6CELL0.LONG.V6buffer
CELL1.LONG.V7CELL0.LONG.V7buffer
CELL1.LONG.V8CELL0.LONG.V8buffer
CELL1.LONG.V9CELL0.LONG.V9buffer
CELL1.VCLKCELL0.QUAD.V1.4mux
CELL0.LONG.V1mux
CELL0.LONG.V5mux
CELL0.LONG.V8mux
CELL0.GCLK1mux
CELL0.GCLK4mux
CELL1.SINGLE.V0mux
CELL1.SINGLE.V1mux
CELL1.SINGLE.V4mux
CELL1.SINGLE.V5mux
CELL1.SINGLE.V6mux
CELL1.QUAD.V0.0mux

Bitstream

xc4000xv LLVC.CLB rect R0
BitFrame
F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B1 ~LLV:BUF.0.LONG.V6.1.LONG.V6 ~LLV:BUF.1.LONG.V6.0.LONG.V6 ~LLV:BUF.0.LONG.V5.1.LONG.V5 ~LLV:BUF.1.LONG.V5.0.LONG.V5 ~LLV:BUF.0.LONG.V3.1.LONG.V3 ~LLV:BUF.1.LONG.V3.0.LONG.V3 ~LLV:BUF.1.LONG.V7.0.LONG.V7 ~LLV:BUF.0.LONG.V7.1.LONG.V7 - - ~LLV:BUF.1.LONG.V8.0.LONG.V8 ~LLV:BUF.0.LONG.V8.1.LONG.V8 ~LLV:BUF.0.LONG.V9.1.LONG.V9 ~LLV:BUF.1.LONG.V9.0.LONG.V9 - ~LLV:BUF.1.LONG.V4.0.LONG.V4 - ~LLV:BUF.0.LONG.V1.1.LONG.V1 ~LLV:BUF.1.LONG.V1.0.LONG.V1 ~LLV:BUF.0.LONG.V0.1.LONG.V0 ~LLV:BUF.1.LONG.V0.0.LONG.V0 ~LLV:BUF.0.LONG.V4.1.LONG.V4 ~LLV:BUF.1.LONG.V2.0.LONG.V2 ~LLV:BUF.0.LONG.V2.1.LONG.V2 - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - LLV:MUX.0.VCLK[3] LLV:MUX.1.VCLK[3] - - - - LLV:MUX.1.VCLK[2] LLV:MUX.1.VCLK[1] - - - - LLV:MUX.1.VCLK[4] LLV:MUX.1.VCLK[0] - - LLV:MUX.1.VCLK[6] LLV:MUX.1.VCLK[5] - - LLV:MUX.0.VCLK[4] LLV:MUX.0.VCLK[2] - - - - - LLV:MUX.0.VCLK[1] LLV:MUX.0.VCLK[0] LLV:MUX.0.VCLK[5] LLV:MUX.0.VCLK[6] - - - - -
LLV:BUF.0.LONG.V0.1.LONG.V0 0.F26.B1
LLV:BUF.0.LONG.V1.1.LONG.V1 0.F28.B1
LLV:BUF.0.LONG.V2.1.LONG.V2 0.F22.B1
LLV:BUF.0.LONG.V3.1.LONG.V3 0.F41.B1
LLV:BUF.0.LONG.V4.1.LONG.V4 0.F24.B1
LLV:BUF.0.LONG.V5.1.LONG.V5 0.F43.B1
LLV:BUF.0.LONG.V6.1.LONG.V6 0.F45.B1
LLV:BUF.0.LONG.V7.1.LONG.V7 0.F38.B1
LLV:BUF.0.LONG.V8.1.LONG.V8 0.F34.B1
LLV:BUF.0.LONG.V9.1.LONG.V9 0.F33.B1
LLV:BUF.1.LONG.V0.0.LONG.V0 0.F25.B1
LLV:BUF.1.LONG.V1.0.LONG.V1 0.F27.B1
LLV:BUF.1.LONG.V2.0.LONG.V2 0.F23.B1
LLV:BUF.1.LONG.V3.0.LONG.V3 0.F40.B1
LLV:BUF.1.LONG.V4.0.LONG.V4 0.F30.B1
LLV:BUF.1.LONG.V5.0.LONG.V5 0.F42.B1
LLV:BUF.1.LONG.V6.0.LONG.V6 0.F44.B1
LLV:BUF.1.LONG.V7.0.LONG.V7 0.F39.B1
LLV:BUF.1.LONG.V8.0.LONG.V8 0.F35.B1
LLV:BUF.1.LONG.V9.0.LONG.V9 0.F32.B1
inverted ~[0]
LLV:MUX.0.VCLK 0.F5.B0 0.F6.B0 0.F15.B0 0.F35.B0 0.F14.B0 0.F8.B0 0.F7.B0
0.QUAD.V0.4 0 0 0 0 1 1 1
1.LONG.V0 0 0 0 1 0 1 1
1.QUAD.V2.0 0 0 1 0 1 0 1
1.LONG.V6 0 0 1 0 1 1 0
1.SINGLE.V1 0 0 1 1 0 0 1
1.SINGLE.V2 0 0 1 1 0 1 0
1.GCLK5 0 1 1 0 1 1 1
1.SINGLE.V4 0 1 1 1 0 1 1
1.SINGLE.V5 1 0 0 1 1 1 1
1.LONG.V4 1 0 1 1 1 0 1
1.GCLK2 1 0 1 1 1 1 0
1.SINGLE.V0 1 1 1 1 1 1 1
LLV:MUX.1.VCLK 0.F19.B0 0.F18.B0 0.F23.B0 0.F34.B0 0.F29.B0 0.F28.B0 0.F22.B0
0.QUAD.V1.4 0 0 0 0 1 1 1
1.SINGLE.V1 0 0 0 1 0 1 1
1.QUAD.V0.0 0 0 1 0 1 0 1
0.LONG.V8 0 0 1 0 1 1 0
0.LONG.V1 0 0 1 1 0 0 1
1.SINGLE.V4 0 0 1 1 0 1 0
0.LONG.V5 0 1 0 1 1 1 1
1.SINGLE.V6 0 1 1 1 1 0 1
0.GCLK1 0 1 1 1 1 1 0
0.GCLK4 1 0 1 0 1 1 1
1.SINGLE.V5 1 0 1 1 0 1 1
1.SINGLE.V0 1 1 1 1 1 1 1

Tile LLVC.IO.L

Cells: 2

Bel PULLUP_DEC0_S

xc4000xv LLVC.IO.L bel PULLUP_DEC0_S
PinDirectionWires
OoutputCELL0.DEC.V0

Bel PULLUP_DEC1_S

xc4000xv LLVC.IO.L bel PULLUP_DEC1_S
PinDirectionWires
OoutputCELL0.DEC.V1

Bel PULLUP_DEC2_S

xc4000xv LLVC.IO.L bel PULLUP_DEC2_S
PinDirectionWires
OoutputCELL0.DEC.V2

Bel PULLUP_DEC3_S

xc4000xv LLVC.IO.L bel PULLUP_DEC3_S
PinDirectionWires
OoutputCELL0.DEC.V3

Bel PULLUP_DEC0_N

xc4000xv LLVC.IO.L bel PULLUP_DEC0_N
PinDirectionWires
OoutputCELL1.DEC.V0

Bel PULLUP_DEC1_N

xc4000xv LLVC.IO.L bel PULLUP_DEC1_N
PinDirectionWires
OoutputCELL1.DEC.V1

Bel PULLUP_DEC2_N

xc4000xv LLVC.IO.L bel PULLUP_DEC2_N
PinDirectionWires
OoutputCELL1.DEC.V2

Bel PULLUP_DEC3_N

xc4000xv LLVC.IO.L bel PULLUP_DEC3_N
PinDirectionWires
OoutputCELL1.DEC.V3

Switchbox LLV

xc4000xv LLVC.IO.L switchbox LLV
DestinationSourceKind
CELL0.LONG.IO.V0CELL1.LONG.IO.V0buffer
CELL0.LONG.IO.V1CELL1.LONG.IO.V1buffer
CELL0.LONG.IO.V2CELL1.LONG.IO.V2buffer
CELL0.LONG.IO.V3CELL1.LONG.IO.V3buffer
CELL0.DEC.V0CELL1.DEC.V0bidirectional pass transistor
CELL0.DEC.V1CELL1.DEC.V1bidirectional pass transistor
CELL0.DEC.V2CELL1.DEC.V2bidirectional pass transistor
CELL0.DEC.V3CELL1.DEC.V3bidirectional pass transistor
CELL1.LONG.IO.V0CELL0.LONG.IO.V0buffer
CELL1.LONG.IO.V1CELL0.LONG.IO.V1buffer
CELL1.LONG.IO.V2CELL0.LONG.IO.V2buffer
CELL1.LONG.IO.V3CELL0.LONG.IO.V3buffer
CELL1.DEC.V0CELL0.DEC.V0bidirectional pass transistor
CELL1.DEC.V1CELL0.DEC.V1bidirectional pass transistor
CELL1.DEC.V2CELL0.DEC.V2bidirectional pass transistor
CELL1.DEC.V3CELL0.DEC.V3bidirectional pass transistor

Bel wires

xc4000xv LLVC.IO.L bel wires
WirePins
CELL0.DEC.V0PULLUP_DEC0_S.O
CELL0.DEC.V1PULLUP_DEC1_S.O
CELL0.DEC.V2PULLUP_DEC2_S.O
CELL0.DEC.V3PULLUP_DEC3_S.O
CELL1.DEC.V0PULLUP_DEC0_N.O
CELL1.DEC.V1PULLUP_DEC1_N.O
CELL1.DEC.V2PULLUP_DEC2_N.O
CELL1.DEC.V3PULLUP_DEC3_N.O

Bitstream

xc4000xv LLVC.IO.L rect R0
BitFrame
F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B1 ~LLV:BIPASS.0.DEC.V1.1.DEC.V1 ~LLV:BIPASS.0.DEC.V3.1.DEC.V3 ~PULLUP_DEC3_S:ENABLE ~PULLUP_DEC3_N:ENABLE ~PULLUP_DEC1_N:ENABLE ~PULLUP_DEC1_S:ENABLE ~PULLUP_DEC2_S:ENABLE ~PULLUP_DEC2_N:ENABLE ~LLV:BIPASS.0.DEC.V0.1.DEC.V0 ~LLV:BIPASS.0.DEC.V2.1.DEC.V2 ~PULLUP_DEC0_N:ENABLE ~PULLUP_DEC0_S:ENABLE ~LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1 ~LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1 ~LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0 ~LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0 - - ~LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2 ~LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2 ~LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3 ~LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3 - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - -
LLV:BIPASS.0.DEC.V0.1.DEC.V0 0.F17.B1
LLV:BIPASS.0.DEC.V1.1.DEC.V1 0.F25.B1
LLV:BIPASS.0.DEC.V2.1.DEC.V2 0.F16.B1
LLV:BIPASS.0.DEC.V3.1.DEC.V3 0.F24.B1
LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0 0.F10.B1
LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1 0.F13.B1
LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2 0.F6.B1
LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3 0.F5.B1
LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0 0.F11.B1
LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1 0.F12.B1
LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2 0.F7.B1
LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3 0.F4.B1
PULLUP_DEC0_N:ENABLE 0.F15.B1
PULLUP_DEC0_S:ENABLE 0.F14.B1
PULLUP_DEC1_N:ENABLE 0.F21.B1
PULLUP_DEC1_S:ENABLE 0.F20.B1
PULLUP_DEC2_N:ENABLE 0.F18.B1
PULLUP_DEC2_S:ENABLE 0.F19.B1
PULLUP_DEC3_N:ENABLE 0.F22.B1
PULLUP_DEC3_S:ENABLE 0.F23.B1
inverted ~[0]

Tile LLVC.IO.R

Cells: 2

Bel PULLUP_DEC0_S

xc4000xv LLVC.IO.R bel PULLUP_DEC0_S
PinDirectionWires
OoutputCELL0.DEC.V0

Bel PULLUP_DEC1_S

xc4000xv LLVC.IO.R bel PULLUP_DEC1_S
PinDirectionWires
OoutputCELL0.DEC.V1

Bel PULLUP_DEC2_S

xc4000xv LLVC.IO.R bel PULLUP_DEC2_S
PinDirectionWires
OoutputCELL0.DEC.V2

Bel PULLUP_DEC3_S

xc4000xv LLVC.IO.R bel PULLUP_DEC3_S
PinDirectionWires
OoutputCELL0.DEC.V3

Bel PULLUP_DEC0_N

xc4000xv LLVC.IO.R bel PULLUP_DEC0_N
PinDirectionWires
OoutputCELL1.DEC.V0

Bel PULLUP_DEC1_N

xc4000xv LLVC.IO.R bel PULLUP_DEC1_N
PinDirectionWires
OoutputCELL1.DEC.V1

Bel PULLUP_DEC2_N

xc4000xv LLVC.IO.R bel PULLUP_DEC2_N
PinDirectionWires
OoutputCELL1.DEC.V2

Bel PULLUP_DEC3_N

xc4000xv LLVC.IO.R bel PULLUP_DEC3_N
PinDirectionWires
OoutputCELL1.DEC.V3

Switchbox LLV

xc4000xv LLVC.IO.R switchbox LLV
DestinationSourceKind
CELL0.LONG.V0CELL1.LONG.V0buffer
CELL0.LONG.V1CELL1.LONG.V1buffer
CELL0.LONG.V2CELL1.LONG.V2buffer
CELL0.LONG.V3CELL1.LONG.V3buffer
CELL0.LONG.V4CELL1.LONG.V4buffer
CELL0.LONG.V5CELL1.LONG.V5buffer
CELL0.LONG.V6CELL1.LONG.V6buffer
CELL0.LONG.V7CELL1.LONG.V7buffer
CELL0.LONG.V8CELL1.LONG.V8buffer
CELL0.LONG.V9CELL1.LONG.V9buffer
CELL0.LONG.IO.V0CELL1.LONG.IO.V0buffer
CELL0.LONG.IO.V1CELL1.LONG.IO.V1buffer
CELL0.LONG.IO.V2CELL1.LONG.IO.V2buffer
CELL0.LONG.IO.V3CELL1.LONG.IO.V3buffer
CELL0.DEC.V0CELL1.DEC.V0bidirectional pass transistor
CELL0.DEC.V1CELL1.DEC.V1bidirectional pass transistor
CELL0.DEC.V2CELL1.DEC.V2bidirectional pass transistor
CELL0.DEC.V3CELL1.DEC.V3bidirectional pass transistor
CELL0.VCLKCELL0.QUAD.V0.4mux
CELL1.SINGLE.V0mux
CELL1.SINGLE.V1mux
CELL1.SINGLE.V2mux
CELL1.SINGLE.V4mux
CELL1.SINGLE.V5mux
CELL1.QUAD.V2.0mux
CELL1.LONG.V0mux
CELL1.LONG.V4mux
CELL1.LONG.V6mux
CELL1.GCLK2mux
CELL1.GCLK5mux
CELL1.LONG.V0CELL0.LONG.V0buffer
CELL1.LONG.V1CELL0.LONG.V1buffer
CELL1.LONG.V2CELL0.LONG.V2buffer
CELL1.LONG.V3CELL0.LONG.V3buffer
CELL1.LONG.V4CELL0.LONG.V4buffer
CELL1.LONG.V5CELL0.LONG.V5buffer
CELL1.LONG.V6CELL0.LONG.V6buffer
CELL1.LONG.V7CELL0.LONG.V7buffer
CELL1.LONG.V8CELL0.LONG.V8buffer
CELL1.LONG.V9CELL0.LONG.V9buffer
CELL1.LONG.IO.V0CELL0.LONG.IO.V0buffer
CELL1.LONG.IO.V1CELL0.LONG.IO.V1buffer
CELL1.LONG.IO.V2CELL0.LONG.IO.V2buffer
CELL1.LONG.IO.V3CELL0.LONG.IO.V3buffer
CELL1.DEC.V0CELL0.DEC.V0bidirectional pass transistor
CELL1.DEC.V1CELL0.DEC.V1bidirectional pass transistor
CELL1.DEC.V2CELL0.DEC.V2bidirectional pass transistor
CELL1.DEC.V3CELL0.DEC.V3bidirectional pass transistor
CELL1.VCLKCELL0.QUAD.V1.4mux
CELL0.LONG.V1mux
CELL0.LONG.V5mux
CELL0.LONG.V8mux
CELL0.GCLK1mux
CELL0.GCLK4mux
CELL1.SINGLE.V0mux
CELL1.SINGLE.V1mux
CELL1.SINGLE.V4mux
CELL1.SINGLE.V5mux
CELL1.SINGLE.V6mux
CELL1.QUAD.V0.0mux

Bel wires

xc4000xv LLVC.IO.R bel wires
WirePins
CELL0.DEC.V0PULLUP_DEC0_S.O
CELL0.DEC.V1PULLUP_DEC1_S.O
CELL0.DEC.V2PULLUP_DEC2_S.O
CELL0.DEC.V3PULLUP_DEC3_S.O
CELL1.DEC.V0PULLUP_DEC0_N.O
CELL1.DEC.V1PULLUP_DEC1_N.O
CELL1.DEC.V2PULLUP_DEC2_N.O
CELL1.DEC.V3PULLUP_DEC3_N.O

Bitstream

xc4000xv LLVC.IO.R rect R0
BitFrame
F50 F49 F48 F47 F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B1 ~LLV:BUF.0.LONG.V6.1.LONG.V6 ~LLV:BUF.1.LONG.V6.0.LONG.V6 - - - - ~LLV:BUF.1.LONG.V7.0.LONG.V7 ~LLV:BUF.0.LONG.V7.1.LONG.V7 - - ~LLV:BUF.1.LONG.V8.0.LONG.V8 ~LLV:BUF.0.LONG.V8.1.LONG.V8 ~LLV:BUF.0.LONG.V9.1.LONG.V9 ~LLV:BUF.1.LONG.V9.0.LONG.V9 - ~LLV:BIPASS.0.DEC.V3.1.DEC.V3 ~LLV:BUF.0.LONG.V1.1.LONG.V1 ~PULLUP_DEC3_S:ENABLE ~LLV:BUF.1.LONG.V1.0.LONG.V1 ~PULLUP_DEC3_N:ENABLE ~LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0 ~LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0 ~LLV:BUF.1.LONG.V2.0.LONG.V2 ~LLV:BUF.0.LONG.V2.1.LONG.V2 ~LLV:BUF.0.LONG.V4.1.LONG.V4 ~LLV:BUF.1.LONG.V4.0.LONG.V4 ~LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2 ~LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2 - - ~LLV:BUF.0.LONG.V3.1.LONG.V3 ~LLV:BUF.1.LONG.V3.0.LONG.V3 ~LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3 ~LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3 ~LLV:BUF.0.LONG.V0.1.LONG.V0 ~LLV:BUF.1.LONG.V0.0.LONG.V0 ~LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1 ~LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1 ~PULLUP_DEC1_S:ENABLE ~PULLUP_DEC1_N:ENABLE ~LLV:BUF.1.LONG.V5.0.LONG.V5 ~LLV:BUF.0.LONG.V5.1.LONG.V5 - ~PULLUP_DEC0_N:ENABLE ~PULLUP_DEC2_N:ENABLE ~PULLUP_DEC2_S:ENABLE ~PULLUP_DEC0_S:ENABLE - - - -
B0 - - - - - - - - - - LLV:MUX.0.VCLK[3] LLV:MUX.1.VCLK[3] - - - - LLV:MUX.1.VCLK[2] LLV:MUX.1.VCLK[1] - - - - LLV:MUX.1.VCLK[4] LLV:MUX.1.VCLK[0] - - LLV:MUX.1.VCLK[6] LLV:MUX.1.VCLK[5] - - LLV:MUX.0.VCLK[4] LLV:MUX.0.VCLK[2] - - - - - - LLV:MUX.0.VCLK[1] LLV:MUX.0.VCLK[0] LLV:MUX.0.VCLK[5] LLV:MUX.0.VCLK[6] - ~LLV:BIPASS.0.DEC.V1.1.DEC.V1 - ~LLV:BIPASS.0.DEC.V2.1.DEC.V2 ~LLV:BIPASS.0.DEC.V0.1.DEC.V0 - ~MISC:TLC - -
LLV:BIPASS.0.DEC.V0.1.DEC.V0 0.F4.B0
LLV:BIPASS.0.DEC.V1.1.DEC.V1 0.F7.B0
LLV:BIPASS.0.DEC.V2.1.DEC.V2 0.F5.B0
LLV:BIPASS.0.DEC.V3.1.DEC.V3 0.F35.B1
LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0 0.F30.B1
LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1 0.F13.B1
LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2 0.F23.B1
LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3 0.F18.B1
LLV:BUF.0.LONG.V0.1.LONG.V0 0.F16.B1
LLV:BUF.0.LONG.V1.1.LONG.V1 0.F34.B1
LLV:BUF.0.LONG.V2.1.LONG.V2 0.F27.B1
LLV:BUF.0.LONG.V3.1.LONG.V3 0.F20.B1
LLV:BUF.0.LONG.V4.1.LONG.V4 0.F26.B1
LLV:BUF.0.LONG.V5.1.LONG.V5 0.F9.B1
LLV:BUF.0.LONG.V6.1.LONG.V6 0.F50.B1
LLV:BUF.0.LONG.V7.1.LONG.V7 0.F43.B1
LLV:BUF.0.LONG.V8.1.LONG.V8 0.F39.B1
LLV:BUF.0.LONG.V9.1.LONG.V9 0.F38.B1
LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0 0.F29.B1
LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1 0.F14.B1
LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2 0.F24.B1
LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3 0.F17.B1
LLV:BUF.1.LONG.V0.0.LONG.V0 0.F15.B1
LLV:BUF.1.LONG.V1.0.LONG.V1 0.F32.B1
LLV:BUF.1.LONG.V2.0.LONG.V2 0.F28.B1
LLV:BUF.1.LONG.V3.0.LONG.V3 0.F19.B1
LLV:BUF.1.LONG.V4.0.LONG.V4 0.F25.B1
LLV:BUF.1.LONG.V5.0.LONG.V5 0.F10.B1
LLV:BUF.1.LONG.V6.0.LONG.V6 0.F49.B1
LLV:BUF.1.LONG.V7.0.LONG.V7 0.F44.B1
LLV:BUF.1.LONG.V8.0.LONG.V8 0.F40.B1
LLV:BUF.1.LONG.V9.0.LONG.V9 0.F37.B1
MISC:TLC 0.F2.B0
PULLUP_DEC0_N:ENABLE 0.F7.B1
PULLUP_DEC0_S:ENABLE 0.F4.B1
PULLUP_DEC1_N:ENABLE 0.F11.B1
PULLUP_DEC1_S:ENABLE 0.F12.B1
PULLUP_DEC2_N:ENABLE 0.F6.B1
PULLUP_DEC2_S:ENABLE 0.F5.B1
PULLUP_DEC3_N:ENABLE 0.F31.B1
PULLUP_DEC3_S:ENABLE 0.F33.B1
inverted ~[0]
LLV:MUX.0.VCLK 0.F9.B0 0.F10.B0 0.F20.B0 0.F40.B0 0.F19.B0 0.F12.B0 0.F11.B0
0.QUAD.V0.4 0 0 0 0 1 1 1
1.LONG.V0 0 0 0 1 0 1 1
1.QUAD.V2.0 0 0 1 0 1 0 1
1.LONG.V6 0 0 1 0 1 1 0
1.SINGLE.V1 0 0 1 1 0 0 1
1.SINGLE.V2 0 0 1 1 0 1 0
1.GCLK5 0 1 1 0 1 1 1
1.SINGLE.V4 0 1 1 1 0 1 1
1.SINGLE.V5 1 0 0 1 1 1 1
1.LONG.V4 1 0 1 1 1 0 1
1.GCLK2 1 0 1 1 1 1 0
1.SINGLE.V0 1 1 1 1 1 1 1
LLV:MUX.1.VCLK 0.F24.B0 0.F23.B0 0.F28.B0 0.F39.B0 0.F34.B0 0.F33.B0 0.F27.B0
0.QUAD.V1.4 0 0 0 0 1 1 1
1.SINGLE.V1 0 0 0 1 0 1 1
1.QUAD.V0.0 0 0 1 0 1 0 1
0.LONG.V8 0 0 1 0 1 1 0
0.LONG.V1 0 0 1 1 0 0 1
1.SINGLE.V4 0 0 1 1 0 1 0
0.LONG.V5 0 1 0 1 1 1 1
1.SINGLE.V6 0 1 1 1 1 0 1
0.GCLK1 0 1 1 1 1 1 0
0.GCLK4 1 0 1 0 1 1 1
1.SINGLE.V5 1 0 1 1 0 1 1
1.SINGLE.V0 1 1 1 1 1 1 1

Tile LLVQ.CLB

Cells: 2

Switchbox LLV

xc4000xv LLVQ.CLB switchbox LLV
DestinationSourceKind
CELL0.QUAD.V1.4CELL0.VCLKpass transistor
CELL0.QUAD.V2.4CELL1.VCLKpass transistor
CELL0.LONG.V0CELL1.LONG.V0buffer
CELL0.LONG.V1CELL1.LONG.V1buffer
CELL0.LONG.V2CELL1.LONG.V2buffer
CELL0.LONG.V3CELL1.LONG.V3buffer
CELL0.LONG.V4CELL1.LONG.V4buffer
CELL0.LONG.V5CELL1.LONG.V5buffer
CELL0.LONG.V6CELL1.LONG.V6buffer
CELL0.LONG.V7CELL1.LONG.V7.EXCLmux
CELL0.LONG.V8CELL1.LONG.V8buffer
CELL0.LONG.V9CELL1.LONG.V9.EXCLmux
CELL0.GCLK0CELL0.QUAD.V0.3mux
CELL0.VCLKmux
CELL1.SINGLE.V0mux
CELL1.VCLKmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK1CELL0.QUAD.V0.4mux
CELL0.VCLKmux
CELL1.SINGLE.V1mux
CELL1.VCLKmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK2CELL0.VCLKmux
CELL1.SINGLE.V2mux
CELL1.QUAD.V0.0mux
CELL1.VCLKmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK3CELL0.QUAD.V1.4mux
CELL0.VCLKmux
CELL1.SINGLE.V3mux
CELL1.VCLKmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK4CELL0.VCLKmux
CELL1.SINGLE.V4mux
CELL1.QUAD.V1.0mux
CELL1.VCLKmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK5CELL0.QUAD.V2.3mux
CELL0.VCLKmux
CELL1.SINGLE.V5mux
CELL1.VCLKmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK6CELL0.QUAD.V2.4mux
CELL0.VCLKmux
CELL1.SINGLE.V6mux
CELL1.VCLKmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK7CELL0.VCLKmux
CELL1.SINGLE.V7mux
CELL1.QUAD.V2.0mux
CELL1.VCLKmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL1.SINGLE.V0CELL0.VCLKpass transistor
CELL1.SINGLE.V1CELL1.VCLKpass transistor
CELL1.SINGLE.V2CELL0.VCLKpass transistor
CELL1.SINGLE.V3CELL1.VCLKpass transistor
CELL1.SINGLE.V4CELL0.VCLKpass transistor
CELL1.SINGLE.V5CELL1.VCLKpass transistor
CELL1.SINGLE.V6CELL0.VCLKpass transistor
CELL1.SINGLE.V7CELL1.VCLKpass transistor
CELL1.QUAD.V0.0CELL1.VCLKpass transistor
CELL1.QUAD.V2.0CELL0.VCLKpass transistor
CELL1.LONG.V0CELL0.LONG.V0buffer
CELL1.LONG.V1CELL0.LONG.V1buffer
CELL1.LONG.V2CELL0.LONG.V2buffer
CELL1.LONG.V3CELL0.LONG.V3buffer
CELL1.LONG.V4CELL0.LONG.V4buffer
CELL1.LONG.V5CELL0.LONG.V5buffer
CELL1.LONG.V6CELL0.LONG.V6buffer
CELL1.LONG.V7CELL1.LONG.V7.EXCLmux
CELL1.LONG.V7.EXCLCELL0.LONG.V7mux
CELL0.VCLKmux
CELL1.LONG.V7mux
CELL1.LONG.V8CELL0.LONG.V8buffer
CELL1.LONG.V9CELL1.LONG.V9.EXCLmux
CELL1.LONG.V9.EXCLCELL0.LONG.V9mux
CELL1.LONG.V9mux
CELL1.VCLKmux

Bitstream

xc4000xv LLVQ.CLB rect R0
BitFrame
F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B1 ~LLV:BUF.0.LONG.V6.1.LONG.V6 ~LLV:BUF.0.LONG.V7.1.LONG.V7 ~LLV:PASS.1.QUAD.V0.0.1.VCLK LLV:MUX.1.LONG.V7[0] ~LLV:BUF.0.LONG.V8.1.LONG.V8 LLV:MUX.0.GCLK4[3] LLV:MUX.0.GCLK4[4] LLV:MUX.0.GCLK4[6] LLV:MUX.0.GCLK4[0] ~LLV:BUF.1.LONG.V9.0.LONG.V9 LLV:MUX.0.LONG.V9[0] LLV:MUX.0.GCLK5[5] LLV:MUX.0.GCLK5[3] LLV:MUX.0.GCLK5[6] LLV:MUX.0.GCLK5[0] ~LLV:BUF.0.LONG.V2.1.LONG.V2 LLV:MUX.0.GCLK0[5] LLV:MUX.0.GCLK0[3] LLV:MUX.0.GCLK0[6] LLV:MUX.0.GCLK0[0] ~LLV:PASS.1.SINGLE.V1.1.VCLK ~LLV:BUF.0.LONG.V4.1.LONG.V4 LLV:MUX.0.GCLK6[5] LLV:MUX.0.GCLK6[3] LLV:MUX.0.GCLK6[6] LLV:MUX.0.GCLK6[0] ~LLV:BUF.0.LONG.V1.1.LONG.V1 LLV:MUX.0.GCLK7[3] LLV:MUX.0.GCLK7[4] LLV:MUX.0.GCLK7[6] LLV:MUX.0.GCLK7[0] ~LLV:BUF.0.LONG.V5.1.LONG.V5 - LLV:MUX.0.GCLK2[3] LLV:MUX.0.GCLK2[4] LLV:MUX.0.GCLK2[6] LLV:MUX.0.GCLK2[0] ~LLV:BUF.0.LONG.V3.1.LONG.V3 LLV:MUX.0.GCLK3[5] LLV:MUX.0.GCLK3[3] LLV:MUX.0.GCLK3[6] LLV:MUX.0.GCLK3[0] ~LLV:BUF.0.LONG.V0.1.LONG.V0 LLV:MUX.0.GCLK1[5] LLV:MUX.0.GCLK1[3] LLV:MUX.0.GCLK1[6] LLV:MUX.0.GCLK1[0]
B0 ~LLV:BUF.1.LONG.V6.0.LONG.V6 LLV:MUX.1.LONG.V7[1] ~LLV:BUF.1.LONG.V8.0.LONG.V8 ~LLV:PASS.0.QUAD.V1.4.0.VCLK ~LLV:PASS.0.QUAD.V2.4.1.VCLK LLV:MUX.0.GCLK4[5] LLV:MUX.0.GCLK4[2] LLV:MUX.0.GCLK4[1] ~LLV:PASS.1.SINGLE.V4.0.VCLK ~LLV:PASS.1.SINGLE.V6.0.VCLK LLV:MUX.0.LONG.V9[1] LLV:MUX.0.GCLK5[4] LLV:MUX.0.GCLK5[2] LLV:MUX.0.GCLK5[1] ~LLV:PASS.1.SINGLE.V7.1.VCLK ~LLV:BUF.1.LONG.V2.0.LONG.V2 LLV:MUX.0.GCLK0[4] LLV:MUX.0.GCLK0[2] ~LLV:PASS.1.SINGLE.V5.1.VCLK ~LLV:PASS.1.SINGLE.V3.1.VCLK LLV:MUX.0.GCLK0[1] ~LLV:BUF.1.LONG.V4.0.LONG.V4 LLV:MUX.0.GCLK6[4] LLV:MUX.0.GCLK6[2] ~LLV:PASS.1.QUAD.V2.0.0.VCLK LLV:MUX.0.GCLK6[1] ~LLV:BUF.1.LONG.V1.0.LONG.V1 LLV:MUX.0.GCLK7[5] LLV:MUX.0.GCLK7[2] ~LLV:PASS.1.SINGLE.V0.0.VCLK LLV:MUX.0.GCLK7[1] ~LLV:BUF.1.LONG.V5.0.LONG.V5 ~LLV:PASS.1.SINGLE.V2.0.VCLK LLV:MUX.0.GCLK2[5] LLV:MUX.0.GCLK2[2] - LLV:MUX.0.GCLK2[1] ~LLV:BUF.1.LONG.V3.0.LONG.V3 LLV:MUX.0.GCLK3[4] LLV:MUX.0.GCLK3[2] - LLV:MUX.0.GCLK3[1] ~LLV:BUF.1.LONG.V0.0.LONG.V0 LLV:MUX.0.GCLK1[4] LLV:MUX.0.GCLK1[2] - LLV:MUX.0.GCLK1[1]
LLV:BUF.0.LONG.V0.1.LONG.V0 0.F4.B1
LLV:BUF.0.LONG.V1.1.LONG.V1 0.F20.B1
LLV:BUF.0.LONG.V2.1.LONG.V2 0.F31.B1
LLV:BUF.0.LONG.V3.1.LONG.V3 0.F9.B1
LLV:BUF.0.LONG.V4.1.LONG.V4 0.F25.B1
LLV:BUF.0.LONG.V5.1.LONG.V5 0.F15.B1
LLV:BUF.0.LONG.V6.1.LONG.V6 0.F46.B1
LLV:BUF.0.LONG.V7.1.LONG.V7 0.F45.B1
LLV:BUF.0.LONG.V8.1.LONG.V8 0.F42.B1
LLV:BUF.1.LONG.V0.0.LONG.V0 0.F4.B0
LLV:BUF.1.LONG.V1.0.LONG.V1 0.F20.B0
LLV:BUF.1.LONG.V2.0.LONG.V2 0.F31.B0
LLV:BUF.1.LONG.V3.0.LONG.V3 0.F9.B0
LLV:BUF.1.LONG.V4.0.LONG.V4 0.F25.B0
LLV:BUF.1.LONG.V5.0.LONG.V5 0.F15.B0
LLV:BUF.1.LONG.V6.0.LONG.V6 0.F46.B0
LLV:BUF.1.LONG.V8.0.LONG.V8 0.F44.B0
LLV:BUF.1.LONG.V9.0.LONG.V9 0.F37.B1
LLV:PASS.0.QUAD.V1.4.0.VCLK 0.F43.B0
LLV:PASS.0.QUAD.V2.4.1.VCLK 0.F42.B0
LLV:PASS.1.QUAD.V0.0.1.VCLK 0.F44.B1
LLV:PASS.1.QUAD.V2.0.0.VCLK 0.F22.B0
LLV:PASS.1.SINGLE.V0.0.VCLK 0.F17.B0
LLV:PASS.1.SINGLE.V1.1.VCLK 0.F26.B1
LLV:PASS.1.SINGLE.V2.0.VCLK 0.F14.B0
LLV:PASS.1.SINGLE.V3.1.VCLK 0.F27.B0
LLV:PASS.1.SINGLE.V4.0.VCLK 0.F38.B0
LLV:PASS.1.SINGLE.V5.1.VCLK 0.F28.B0
LLV:PASS.1.SINGLE.V6.0.VCLK 0.F37.B0
LLV:PASS.1.SINGLE.V7.1.VCLK 0.F32.B0
inverted ~[0]
LLV:MUX.0.GCLK0 0.F28.B1 0.F30.B1 0.F30.B0 0.F29.B1 0.F29.B0 0.F26.B0 0.F27.B1
0.QUAD.V0.3 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V0 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK1 0.F1.B1 0.F3.B1 0.F3.B0 0.F2.B1 0.F2.B0 0.F0.B0 0.F0.B1
0.QUAD.V0.4 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V1 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK2 0.F11.B1 0.F13.B0 0.F12.B1 0.F13.B1 0.F12.B0 0.F10.B0 0.F10.B1
0.VCLK 0 0 1 1 1 1 1
1.SINGLE.V2 0 1 0 1 1 1 1
1.QUAD.V0.0 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H2 1 0 1 1 1 0 1
1.BUFGLS.H3 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H4 1 1 1 0 1 0 1
1.BUFGLS.H5 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK3 0.F6.B1 0.F8.B1 0.F8.B0 0.F7.B1 0.F7.B0 0.F5.B0 0.F5.B1
0.QUAD.V1.4 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V3 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK4 0.F39.B1 0.F41.B0 0.F40.B1 0.F41.B1 0.F40.B0 0.F39.B0 0.F38.B1
0.VCLK 0 0 1 1 1 1 1
1.SINGLE.V4 0 1 0 1 1 1 1
1.QUAD.V1.0 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H2 1 0 1 1 1 0 1
1.BUFGLS.H3 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H4 1 1 1 0 1 0 1
1.BUFGLS.H5 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK5 0.F33.B1 0.F35.B1 0.F35.B0 0.F34.B1 0.F34.B0 0.F33.B0 0.F32.B1
0.QUAD.V2.3 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V5 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK6 0.F22.B1 0.F24.B1 0.F24.B0 0.F23.B1 0.F23.B0 0.F21.B0 0.F21.B1
0.QUAD.V2.4 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V6 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK7 0.F17.B1 0.F19.B0 0.F18.B1 0.F19.B1 0.F18.B0 0.F16.B0 0.F16.B1
0.VCLK 0 0 1 1 1 1 1
1.SINGLE.V7 0 1 0 1 1 1 1
1.QUAD.V2.0 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H2 1 0 1 1 1 0 1
1.BUFGLS.H3 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H4 1 1 1 0 1 0 1
1.BUFGLS.H5 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.LONG.V9 0.F36.B0 0.F36.B1
1.LONG.V9 0 0
1.VCLK 0 1
NONE 1 1
LLV:MUX.1.LONG.V7 0.F45.B0 0.F43.B1
0.LONG.V7 0 0
0.VCLK 0 1
NONE 1 1

Tile LLVQ.IO.L.B

Cells: 2

Bel BUFF

xc4000xv LLVQ.IO.L.B bel BUFF
PinDirectionWires
OoutputCELL1.OUT.BUFF

Switchbox LLV

xc4000xv LLVQ.IO.L.B switchbox LLV
DestinationSourceKind
CELL0.IO.DOUBLE.0.W.1CELL0.ECLK.Vpass transistor
CELL0.IO.DOUBLE.1.W.1CELL0.ECLK.Vpass transistor
CELL0.IO.DOUBLE.1.W.2CELL0.ECLK.Vpass transistor
CELL0.IO.DOUBLE.2.W.1CELL0.ECLK.Vpass transistor
CELL0.IO.DOUBLE.3.W.2CELL0.ECLK.Vpass transistor
CELL0.LONG.IO.V0CELL1.LONG.IO.V0buffer
CELL0.LONG.IO.V1CELL1.LONG.IO.V1buffer
CELL0.LONG.IO.V2CELL1.LONG.IO.V2buffer
CELL0.LONG.IO.V3CELL1.LONG.IO.V3buffer
CELL0.GCLK0CELL0.IO.DOUBLE.0.W.1mux
CELL0.IO.DOUBLE.2.W.1mux
CELL0.BUFGE.V1mux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL1.OUT.BUFFmux
CELL0.GCLK1CELL0.IO.DOUBLE.0.W.2mux
CELL0.IO.DOUBLE.2.W.2mux
CELL0.ECLK.Vmux
CELL0.BUFGE.V0mux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK2CELL0.IO.DOUBLE.1.W.1mux
CELL0.IO.DOUBLE.3.W.1mux
CELL0.ECLK.Vmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL1.OUT.BUFFmux
CELL0.GCLK3CELL0.IO.DOUBLE.1.W.2mux
CELL0.IO.DOUBLE.3.W.2mux
CELL0.BUFGE.V0mux
CELL0.BUFGE.V1mux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL1.LONG.IO.V0CELL0.LONG.IO.V0buffer
CELL1.LONG.IO.V1CELL0.LONG.IO.V1buffer
CELL1.LONG.IO.V2CELL0.LONG.IO.V2buffer
CELL1.LONG.IO.V3CELL0.LONG.IO.V3buffer

Bel wires

xc4000xv LLVQ.IO.L.B bel wires
WirePins
CELL1.OUT.BUFFBUFF.O

Bitstream

xc4000xv LLVQ.IO.L.B rect R0
BitFrame
F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B1 LLV:MUX.0.GCLK1[5] LLV:MUX.0.GCLK1[4] LLV:MUX.0.GCLK1[6] LLV:MUX.0.GCLK1[0] LLV:MUX.0.GCLK3[4] LLV:MUX.0.GCLK3[5] LLV:MUX.0.GCLK3[6] LLV:MUX.0.GCLK3[0] LLV:MUX.0.GCLK0[5] LLV:MUX.0.GCLK0[4] LLV:MUX.0.GCLK0[6] LLV:MUX.0.GCLK0[0] LLV:MUX.0.GCLK2[4] LLV:MUX.0.GCLK2[5] LLV:MUX.0.GCLK2[6] LLV:MUX.0.GCLK2[0] - ~LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1 ~LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3 ~LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0 ~LLV:PASS.0.IO.DOUBLE.2.W.1.0.ECLK.V ~LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2 - - - - -
B0 LLV:MUX.0.GCLK1[3] LLV:MUX.0.GCLK1[2] LLV:MUX.0.GCLK1[1] ~LLV:PASS.0.IO.DOUBLE.3.W.2.0.ECLK.V LLV:MUX.0.GCLK3[2] LLV:MUX.0.GCLK3[3] LLV:MUX.0.GCLK3[1] ~LLV:PASS.0.IO.DOUBLE.1.W.2.0.ECLK.V LLV:MUX.0.GCLK0[3] LLV:MUX.0.GCLK0[2] LLV:MUX.0.GCLK0[1] ~LLV:PASS.0.IO.DOUBLE.0.W.1.0.ECLK.V LLV:MUX.0.GCLK2[3] LLV:MUX.0.GCLK2[2] LLV:MUX.0.GCLK2[1] ~LLV:PASS.0.IO.DOUBLE.1.W.1.0.ECLK.V - ~LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1 ~LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3 ~LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0 - ~LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2 - - - - -
LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0 0.F7.B1
LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1 0.F9.B1
LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2 0.F5.B1
LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3 0.F8.B1
LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0 0.F7.B0
LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1 0.F9.B0
LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2 0.F5.B0
LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3 0.F8.B0
LLV:PASS.0.IO.DOUBLE.0.W.1.0.ECLK.V 0.F15.B0
LLV:PASS.0.IO.DOUBLE.1.W.1.0.ECLK.V 0.F11.B0
LLV:PASS.0.IO.DOUBLE.1.W.2.0.ECLK.V 0.F19.B0
LLV:PASS.0.IO.DOUBLE.2.W.1.0.ECLK.V 0.F6.B1
LLV:PASS.0.IO.DOUBLE.3.W.2.0.ECLK.V 0.F23.B0
inverted ~[0]
LLV:MUX.0.GCLK0 0.F16.B1 0.F18.B1 0.F17.B1 0.F18.B0 0.F17.B0 0.F16.B0 0.F15.B1
0.IO.DOUBLE.0.W.1 0 0 1 1 1 1 1
0.IO.DOUBLE.2.W.1 0 1 0 1 1 1 1
0.BUFGE.V1 0 1 1 0 1 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
1.OUT.BUFF 1 1 1 1 1 1 1
LLV:MUX.0.GCLK1 0.F24.B1 0.F26.B1 0.F25.B1 0.F26.B0 0.F25.B0 0.F24.B0 0.F23.B1
0.IO.DOUBLE.0.W.2 0 0 1 1 1 1 1
0.IO.DOUBLE.2.W.2 0 1 0 1 1 1 1
0.ECLK.V 0 1 1 0 1 1 1
0.BUFGE.V0 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK2 0.F12.B1 0.F13.B1 0.F14.B1 0.F14.B0 0.F13.B0 0.F12.B0 0.F11.B1
0.IO.DOUBLE.1.W.1 0 0 1 1 1 1 1
0.IO.DOUBLE.3.W.1 0 1 0 1 1 1 1
0.ECLK.V 0 1 1 0 1 1 1
1.BUFGLS.H6 1 0 1 1 1 0 1
1.BUFGLS.H7 1 0 1 1 1 1 0
1.BUFGLS.H4 1 1 0 1 1 0 1
1.BUFGLS.H5 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
1.OUT.BUFF 1 1 1 1 1 1 1
LLV:MUX.0.GCLK3 0.F20.B1 0.F21.B1 0.F22.B1 0.F21.B0 0.F22.B0 0.F20.B0 0.F19.B1
0.IO.DOUBLE.1.W.2 0 0 1 1 1 1 1
0.IO.DOUBLE.3.W.2 0 1 0 1 1 1 1
0.BUFGE.V0 0 1 1 0 1 1 1
0.BUFGE.V1 0 1 1 1 0 1 1
1.BUFGLS.H6 1 0 1 1 1 0 1
1.BUFGLS.H7 1 0 1 1 1 1 0
1.BUFGLS.H4 1 1 0 1 1 0 1
1.BUFGLS.H5 1 1 0 1 1 1 0
1.BUFGLS.H0 1 1 1 0 1 0 1
1.BUFGLS.H1 1 1 1 0 1 1 0
1.BUFGLS.H2 1 1 1 1 0 0 1
1.BUFGLS.H3 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1

Tile LLVQ.IO.L.T

Cells: 2

Bel BUFF

xc4000xv LLVQ.IO.L.T bel BUFF
PinDirectionWires
OoutputCELL1.OUT.BUFF

Switchbox LLV

xc4000xv LLVQ.IO.L.T switchbox LLV
DestinationSourceKind
CELL0.IO.DOUBLE.0.W.1CELL1.ECLK.Vpass transistor
CELL0.IO.DOUBLE.1.W.1CELL1.ECLK.Vpass transistor
CELL0.IO.DOUBLE.1.W.2CELL1.ECLK.Vpass transistor
CELL0.IO.DOUBLE.2.W.1CELL1.ECLK.Vpass transistor
CELL0.IO.DOUBLE.3.W.2CELL1.ECLK.Vpass transistor
CELL0.LONG.IO.V0CELL1.LONG.IO.V0buffer
CELL0.LONG.IO.V1CELL1.LONG.IO.V1buffer
CELL0.LONG.IO.V2CELL1.LONG.IO.V2buffer
CELL0.LONG.IO.V3CELL1.LONG.IO.V3buffer
CELL0.GCLK0CELL0.IO.DOUBLE.0.W.1mux
CELL0.IO.DOUBLE.2.W.1mux
CELL0.BUFGE.V0mux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL1.OUT.BUFFmux
CELL0.GCLK1CELL0.IO.DOUBLE.0.W.2mux
CELL0.IO.DOUBLE.2.W.2mux
CELL0.BUFGE.V1mux
CELL1.ECLK.Vmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK2CELL0.IO.DOUBLE.1.W.1mux
CELL0.IO.DOUBLE.3.W.1mux
CELL1.ECLK.Vmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL1.OUT.BUFFmux
CELL0.GCLK3CELL0.IO.DOUBLE.1.W.2mux
CELL0.IO.DOUBLE.3.W.2mux
CELL0.BUFGE.V0mux
CELL0.BUFGE.V1mux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL1.LONG.IO.V0CELL0.LONG.IO.V0buffer
CELL1.LONG.IO.V1CELL0.LONG.IO.V1buffer
CELL1.LONG.IO.V2CELL0.LONG.IO.V2buffer
CELL1.LONG.IO.V3CELL0.LONG.IO.V3buffer

Bel wires

xc4000xv LLVQ.IO.L.T bel wires
WirePins
CELL1.OUT.BUFFBUFF.O

Bitstream

xc4000xv LLVQ.IO.L.T rect R0
BitFrame
F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B1 LLV:MUX.0.GCLK1[5] LLV:MUX.0.GCLK1[4] LLV:MUX.0.GCLK1[6] LLV:MUX.0.GCLK1[0] LLV:MUX.0.GCLK3[4] LLV:MUX.0.GCLK3[5] LLV:MUX.0.GCLK3[6] LLV:MUX.0.GCLK3[0] LLV:MUX.0.GCLK0[5] LLV:MUX.0.GCLK0[4] LLV:MUX.0.GCLK0[6] LLV:MUX.0.GCLK0[0] LLV:MUX.0.GCLK2[4] LLV:MUX.0.GCLK2[5] LLV:MUX.0.GCLK2[6] LLV:MUX.0.GCLK2[0] - ~LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1 ~LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3 ~LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0 ~LLV:PASS.0.IO.DOUBLE.2.W.1.1.ECLK.V ~LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2 - - - - -
B0 LLV:MUX.0.GCLK1[2] LLV:MUX.0.GCLK1[3] LLV:MUX.0.GCLK1[1] ~LLV:PASS.0.IO.DOUBLE.3.W.2.1.ECLK.V LLV:MUX.0.GCLK3[3] LLV:MUX.0.GCLK3[2] LLV:MUX.0.GCLK3[1] ~LLV:PASS.0.IO.DOUBLE.1.W.2.1.ECLK.V LLV:MUX.0.GCLK0[3] LLV:MUX.0.GCLK0[2] LLV:MUX.0.GCLK0[1] ~LLV:PASS.0.IO.DOUBLE.0.W.1.1.ECLK.V LLV:MUX.0.GCLK2[3] LLV:MUX.0.GCLK2[2] LLV:MUX.0.GCLK2[1] ~LLV:PASS.0.IO.DOUBLE.1.W.1.1.ECLK.V - ~LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1 ~LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3 ~LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0 - ~LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2 - - - - -
LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0 0.F7.B1
LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1 0.F9.B1
LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2 0.F5.B1
LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3 0.F8.B1
LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0 0.F7.B0
LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1 0.F9.B0
LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2 0.F5.B0
LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3 0.F8.B0
LLV:PASS.0.IO.DOUBLE.0.W.1.1.ECLK.V 0.F15.B0
LLV:PASS.0.IO.DOUBLE.1.W.1.1.ECLK.V 0.F11.B0
LLV:PASS.0.IO.DOUBLE.1.W.2.1.ECLK.V 0.F19.B0
LLV:PASS.0.IO.DOUBLE.2.W.1.1.ECLK.V 0.F6.B1
LLV:PASS.0.IO.DOUBLE.3.W.2.1.ECLK.V 0.F23.B0
inverted ~[0]
LLV:MUX.0.GCLK0 0.F16.B1 0.F18.B1 0.F17.B1 0.F18.B0 0.F17.B0 0.F16.B0 0.F15.B1
0.IO.DOUBLE.0.W.1 0 0 1 1 1 1 1
0.IO.DOUBLE.2.W.1 0 1 0 1 1 1 1
0.BUFGE.V0 0 1 1 0 1 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
1.OUT.BUFF 1 1 1 1 1 1 1
LLV:MUX.0.GCLK1 0.F24.B1 0.F26.B1 0.F25.B1 0.F25.B0 0.F26.B0 0.F24.B0 0.F23.B1
0.IO.DOUBLE.0.W.2 0 0 1 1 1 1 1
0.IO.DOUBLE.2.W.2 0 1 0 1 1 1 1
0.BUFGE.V1 0 1 1 0 1 1 1
1.ECLK.V 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H0 1 1 1 0 1 0 1
1.BUFGLS.H1 1 1 1 0 1 1 0
1.BUFGLS.H2 1 1 1 1 0 0 1
1.BUFGLS.H3 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK2 0.F12.B1 0.F13.B1 0.F14.B1 0.F14.B0 0.F13.B0 0.F12.B0 0.F11.B1
0.IO.DOUBLE.1.W.1 0 0 1 1 1 1 1
0.IO.DOUBLE.3.W.1 0 1 0 1 1 1 1
1.ECLK.V 0 1 1 0 1 1 1
1.BUFGLS.H6 1 0 1 1 1 0 1
1.BUFGLS.H7 1 0 1 1 1 1 0
1.BUFGLS.H4 1 1 0 1 1 0 1
1.BUFGLS.H5 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
1.OUT.BUFF 1 1 1 1 1 1 1
LLV:MUX.0.GCLK3 0.F20.B1 0.F21.B1 0.F22.B1 0.F22.B0 0.F21.B0 0.F20.B0 0.F19.B1
0.IO.DOUBLE.1.W.2 0 0 1 1 1 1 1
0.IO.DOUBLE.3.W.2 0 1 0 1 1 1 1
0.BUFGE.V0 0 1 1 0 1 1 1
0.BUFGE.V1 0 1 1 1 0 1 1
1.BUFGLS.H6 1 0 1 1 1 0 1
1.BUFGLS.H7 1 0 1 1 1 1 0
1.BUFGLS.H4 1 1 0 1 1 0 1
1.BUFGLS.H5 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1

Tile LLVQ.IO.R.B

Cells: 2

Bel BUFF

xc4000xv LLVQ.IO.R.B bel BUFF
PinDirectionWires
OoutputCELL1.OUT.BUFF

Switchbox LLV

xc4000xv LLVQ.IO.R.B switchbox LLV
DestinationSourceKind
CELL0.IO.DOUBLE.0.E.1CELL0.ECLK.Vpass transistor
CELL0.IO.DOUBLE.1.E.0CELL0.ECLK.Vpass transistor
CELL0.IO.DOUBLE.1.E.1CELL0.ECLK.Vpass transistor
CELL0.IO.DOUBLE.2.E.1CELL0.ECLK.Vpass transistor
CELL0.IO.DOUBLE.3.E.0CELL0.ECLK.Vpass transistor
CELL0.QUAD.V1.4CELL0.VCLKpass transistor
CELL0.QUAD.V2.4CELL1.VCLKpass transistor
CELL0.LONG.V0CELL1.LONG.V0buffer
CELL0.LONG.V1CELL1.LONG.V1buffer
CELL0.LONG.V2CELL1.LONG.V2buffer
CELL0.LONG.V3CELL1.LONG.V3buffer
CELL0.LONG.V4CELL1.LONG.V4buffer
CELL0.LONG.V5CELL1.LONG.V5buffer
CELL0.LONG.V6CELL1.LONG.V6buffer
CELL0.LONG.V7CELL1.LONG.V7.EXCLmux
CELL0.LONG.V8CELL1.LONG.V8buffer
CELL0.LONG.V9CELL1.LONG.V9.EXCLmux
CELL0.LONG.IO.V0CELL1.LONG.IO.V0buffer
CELL0.LONG.IO.V1CELL1.LONG.IO.V1buffer
CELL0.LONG.IO.V2CELL1.LONG.IO.V2buffer
CELL0.LONG.IO.V3CELL1.LONG.IO.V3buffer
CELL0.GCLK0CELL0.IO.DOUBLE.0.E.1mux
CELL0.IO.DOUBLE.2.E.1mux
CELL0.BUFGE.V1mux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL1.OUT.BUFFmux
CELL0.GCLK1CELL0.IO.DOUBLE.0.E.0mux
CELL0.IO.DOUBLE.2.E.0mux
CELL0.ECLK.Vmux
CELL0.BUFGE.V0mux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK2CELL0.IO.DOUBLE.1.E.1mux
CELL0.IO.DOUBLE.3.E.1mux
CELL0.ECLK.Vmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL1.OUT.BUFFmux
CELL0.GCLK3CELL0.IO.DOUBLE.1.E.0mux
CELL0.IO.DOUBLE.3.E.0mux
CELL0.BUFGE.V0mux
CELL0.BUFGE.V1mux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK4CELL0.VCLKmux
CELL1.SINGLE.V4mux
CELL1.QUAD.V1.0mux
CELL1.VCLKmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK5CELL0.QUAD.V2.3mux
CELL0.VCLKmux
CELL1.SINGLE.V5mux
CELL1.VCLKmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK6CELL0.QUAD.V2.4mux
CELL0.VCLKmux
CELL1.SINGLE.V6mux
CELL1.VCLKmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK7CELL0.VCLKmux
CELL1.SINGLE.V7mux
CELL1.QUAD.V2.0mux
CELL1.VCLKmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL1.SINGLE.V0CELL0.VCLKpass transistor
CELL1.SINGLE.V1CELL1.VCLKpass transistor
CELL1.SINGLE.V2CELL0.VCLKpass transistor
CELL1.SINGLE.V3CELL1.VCLKpass transistor
CELL1.SINGLE.V4CELL0.VCLKpass transistor
CELL1.SINGLE.V5CELL1.VCLKpass transistor
CELL1.SINGLE.V6CELL0.VCLKpass transistor
CELL1.SINGLE.V7CELL1.VCLKpass transistor
CELL1.QUAD.V0.0CELL1.VCLKpass transistor
CELL1.QUAD.V2.0CELL0.VCLKpass transistor
CELL1.LONG.V0CELL0.LONG.V0buffer
CELL1.LONG.V1CELL0.LONG.V1buffer
CELL1.LONG.V2CELL0.LONG.V2buffer
CELL1.LONG.V3CELL0.LONG.V3buffer
CELL1.LONG.V4CELL0.LONG.V4buffer
CELL1.LONG.V5CELL0.LONG.V5buffer
CELL1.LONG.V6CELL0.LONG.V6buffer
CELL1.LONG.V7CELL1.LONG.V7.EXCLmux
CELL1.LONG.V7.EXCLCELL0.LONG.V7mux
CELL0.VCLKmux
CELL1.LONG.V7mux
CELL1.LONG.V8CELL0.LONG.V8buffer
CELL1.LONG.V9CELL1.LONG.V9.EXCLmux
CELL1.LONG.V9.EXCLCELL0.LONG.V9mux
CELL1.LONG.V9mux
CELL1.VCLKmux
CELL1.LONG.IO.V0CELL0.LONG.IO.V0buffer
CELL1.LONG.IO.V1CELL0.LONG.IO.V1buffer
CELL1.LONG.IO.V2CELL0.LONG.IO.V2buffer
CELL1.LONG.IO.V3CELL0.LONG.IO.V3buffer

Bel wires

xc4000xv LLVQ.IO.R.B bel wires
WirePins
CELL1.OUT.BUFFBUFF.O

Bitstream

xc4000xv LLVQ.IO.R.B rect R0
BitFrame
F51 F50 F49 F48 F47 F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B1 LLV:MUX.0.GCLK4[3] LLV:MUX.0.GCLK4[4] LLV:MUX.0.GCLK4[6] LLV:MUX.0.GCLK4[0] LLV:MUX.0.GCLK5[5] LLV:MUX.0.GCLK5[3] LLV:MUX.0.GCLK5[6] LLV:MUX.0.GCLK5[0] LLV:MUX.0.GCLK6[5] LLV:MUX.0.GCLK6[3] LLV:MUX.0.GCLK6[6] LLV:MUX.0.GCLK6[0] LLV:MUX.0.GCLK7[3] LLV:MUX.0.GCLK7[4] LLV:MUX.0.GCLK7[6] LLV:MUX.0.GCLK7[0] ~LLV:BUF.0.LONG.V5.1.LONG.V5 ~LLV:BUF.0.LONG.V3.1.LONG.V3 ~LLV:BUF.0.LONG.V2.1.LONG.V2 ~LLV:PASS.1.QUAD.V2.0.0.VCLK ~LLV:BUF.0.LONG.V0.1.LONG.V0 ~LLV:PASS.0.QUAD.V1.4.0.VCLK ~LLV:BUF.0.LONG.V4.1.LONG.V4 ~LLV:PASS.1.SINGLE.V3.1.VCLK ~LLV:BUF.0.LONG.V1.1.LONG.V1 ~LLV:BUF.0.LONG.V6.1.LONG.V6 ~LLV:BUF.0.LONG.V7.1.LONG.V7 LLV:MUX.1.LONG.V7[0] ~LLV:BUF.0.LONG.V8.1.LONG.V8 ~LLV:BUF.1.LONG.V9.0.LONG.V9 LLV:MUX.0.LONG.V9[0] ~LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0 ~LLV:PASS.0.IO.DOUBLE.3.E.0.0.ECLK.V ~LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2 ~LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3 ~LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1 LLV:MUX.0.GCLK2[4] LLV:MUX.0.GCLK2[5] LLV:MUX.0.GCLK2[6] LLV:MUX.0.GCLK2[0] LLV:MUX.0.GCLK0[5] LLV:MUX.0.GCLK0[4] LLV:MUX.0.GCLK0[6] LLV:MUX.0.GCLK0[0] LLV:MUX.0.GCLK1[5] LLV:MUX.0.GCLK1[4] LLV:MUX.0.GCLK1[6] LLV:MUX.0.GCLK1[0] LLV:MUX.0.GCLK3[4] LLV:MUX.0.GCLK3[5] LLV:MUX.0.GCLK3[6] LLV:MUX.0.GCLK3[0]
B0 LLV:MUX.0.GCLK4[5] LLV:MUX.0.GCLK4[2] LLV:MUX.0.GCLK4[1] ~LLV:PASS.1.SINGLE.V4.0.VCLK LLV:MUX.0.GCLK5[4] LLV:MUX.0.GCLK5[2] ~LLV:PASS.1.SINGLE.V5.1.VCLK LLV:MUX.0.GCLK5[1] LLV:MUX.0.GCLK6[4] LLV:MUX.0.GCLK6[2] ~LLV:PASS.1.SINGLE.V6.0.VCLK LLV:MUX.0.GCLK6[1] LLV:MUX.0.GCLK7[5] LLV:MUX.0.GCLK7[2] LLV:MUX.0.GCLK7[1] ~LLV:PASS.1.SINGLE.V7.1.VCLK ~LLV:BUF.1.LONG.V5.0.LONG.V5 ~LLV:BUF.1.LONG.V3.0.LONG.V3 ~LLV:BUF.1.LONG.V2.0.LONG.V2 ~LLV:PASS.0.QUAD.V2.4.1.VCLK ~LLV:BUF.1.LONG.V0.0.LONG.V0 ~LLV:PASS.1.QUAD.V0.0.1.VCLK ~LLV:BUF.1.LONG.V4.0.LONG.V4 ~LLV:PASS.1.SINGLE.V2.0.VCLK ~LLV:BUF.1.LONG.V1.0.LONG.V1 ~LLV:BUF.1.LONG.V6.0.LONG.V6 LLV:MUX.1.LONG.V7[1] ~LLV:PASS.1.SINGLE.V0.0.VCLK ~LLV:BUF.1.LONG.V8.0.LONG.V8 LLV:MUX.0.LONG.V9[1] ~LLV:PASS.1.SINGLE.V1.1.VCLK ~LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0 ~LLV:PASS.0.IO.DOUBLE.0.E.1.0.ECLK.V ~LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2 ~LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3 ~LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1 LLV:MUX.0.GCLK2[3] LLV:MUX.0.GCLK2[2] - LLV:MUX.0.GCLK2[1] LLV:MUX.0.GCLK0[3] LLV:MUX.0.GCLK0[2] ~LLV:PASS.0.IO.DOUBLE.1.E.0.0.ECLK.V LLV:MUX.0.GCLK0[1] LLV:MUX.0.GCLK1[3] LLV:MUX.0.GCLK1[2] ~LLV:PASS.0.IO.DOUBLE.1.E.1.0.ECLK.V LLV:MUX.0.GCLK1[1] LLV:MUX.0.GCLK3[2] LLV:MUX.0.GCLK3[3] ~LLV:PASS.0.IO.DOUBLE.2.E.1.0.ECLK.V LLV:MUX.0.GCLK3[1]
LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0 0.F20.B1
LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1 0.F16.B1
LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2 0.F18.B1
LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3 0.F17.B1
LLV:BUF.0.LONG.V0.1.LONG.V0 0.F31.B1
LLV:BUF.0.LONG.V1.1.LONG.V1 0.F27.B1
LLV:BUF.0.LONG.V2.1.LONG.V2 0.F33.B1
LLV:BUF.0.LONG.V3.1.LONG.V3 0.F34.B1
LLV:BUF.0.LONG.V4.1.LONG.V4 0.F29.B1
LLV:BUF.0.LONG.V5.1.LONG.V5 0.F35.B1
LLV:BUF.0.LONG.V6.1.LONG.V6 0.F26.B1
LLV:BUF.0.LONG.V7.1.LONG.V7 0.F25.B1
LLV:BUF.0.LONG.V8.1.LONG.V8 0.F23.B1
LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0 0.F20.B0
LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1 0.F16.B0
LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2 0.F18.B0
LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3 0.F17.B0
LLV:BUF.1.LONG.V0.0.LONG.V0 0.F31.B0
LLV:BUF.1.LONG.V1.0.LONG.V1 0.F27.B0
LLV:BUF.1.LONG.V2.0.LONG.V2 0.F33.B0
LLV:BUF.1.LONG.V3.0.LONG.V3 0.F34.B0
LLV:BUF.1.LONG.V4.0.LONG.V4 0.F29.B0
LLV:BUF.1.LONG.V5.0.LONG.V5 0.F35.B0
LLV:BUF.1.LONG.V6.0.LONG.V6 0.F26.B0
LLV:BUF.1.LONG.V8.0.LONG.V8 0.F23.B0
LLV:BUF.1.LONG.V9.0.LONG.V9 0.F22.B1
LLV:PASS.0.IO.DOUBLE.0.E.1.0.ECLK.V 0.F19.B0
LLV:PASS.0.IO.DOUBLE.1.E.0.0.ECLK.V 0.F9.B0
LLV:PASS.0.IO.DOUBLE.1.E.1.0.ECLK.V 0.F5.B0
LLV:PASS.0.IO.DOUBLE.2.E.1.0.ECLK.V 0.F1.B0
LLV:PASS.0.IO.DOUBLE.3.E.0.0.ECLK.V 0.F19.B1
LLV:PASS.0.QUAD.V1.4.0.VCLK 0.F30.B1
LLV:PASS.0.QUAD.V2.4.1.VCLK 0.F32.B0
LLV:PASS.1.QUAD.V0.0.1.VCLK 0.F30.B0
LLV:PASS.1.QUAD.V2.0.0.VCLK 0.F32.B1
LLV:PASS.1.SINGLE.V0.0.VCLK 0.F24.B0
LLV:PASS.1.SINGLE.V1.1.VCLK 0.F21.B0
LLV:PASS.1.SINGLE.V2.0.VCLK 0.F28.B0
LLV:PASS.1.SINGLE.V3.1.VCLK 0.F28.B1
LLV:PASS.1.SINGLE.V4.0.VCLK 0.F48.B0
LLV:PASS.1.SINGLE.V5.1.VCLK 0.F45.B0
LLV:PASS.1.SINGLE.V6.0.VCLK 0.F41.B0
LLV:PASS.1.SINGLE.V7.1.VCLK 0.F36.B0
inverted ~[0]
LLV:MUX.0.GCLK0 0.F9.B1 0.F11.B1 0.F10.B1 0.F11.B0 0.F10.B0 0.F8.B0 0.F8.B1
0.IO.DOUBLE.0.E.1 0 0 1 1 1 1 1
0.IO.DOUBLE.2.E.1 0 1 0 1 1 1 1
0.BUFGE.V1 0 1 1 0 1 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
1.OUT.BUFF 1 1 1 1 1 1 1
LLV:MUX.0.GCLK1 0.F5.B1 0.F7.B1 0.F6.B1 0.F7.B0 0.F6.B0 0.F4.B0 0.F4.B1
0.IO.DOUBLE.0.E.0 0 0 1 1 1 1 1
0.IO.DOUBLE.2.E.0 0 1 0 1 1 1 1
0.ECLK.V 0 1 1 0 1 1 1
0.BUFGE.V0 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK2 0.F13.B1 0.F14.B1 0.F15.B1 0.F15.B0 0.F14.B0 0.F12.B0 0.F12.B1
0.IO.DOUBLE.1.E.1 0 0 1 1 1 1 1
0.IO.DOUBLE.3.E.1 0 1 0 1 1 1 1
0.ECLK.V 0 1 1 0 1 1 1
1.BUFGLS.H6 1 0 1 1 1 0 1
1.BUFGLS.H7 1 0 1 1 1 1 0
1.BUFGLS.H4 1 1 0 1 1 0 1
1.BUFGLS.H5 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
1.OUT.BUFF 1 1 1 1 1 1 1
LLV:MUX.0.GCLK3 0.F1.B1 0.F2.B1 0.F3.B1 0.F2.B0 0.F3.B0 0.F0.B0 0.F0.B1
0.IO.DOUBLE.1.E.0 0 0 1 1 1 1 1
0.IO.DOUBLE.3.E.0 0 1 0 1 1 1 1
0.BUFGE.V0 0 1 1 0 1 1 1
0.BUFGE.V1 0 1 1 1 0 1 1
1.BUFGLS.H6 1 0 1 1 1 0 1
1.BUFGLS.H7 1 0 1 1 1 1 0
1.BUFGLS.H4 1 1 0 1 1 0 1
1.BUFGLS.H5 1 1 0 1 1 1 0
1.BUFGLS.H0 1 1 1 0 1 0 1
1.BUFGLS.H1 1 1 1 0 1 1 0
1.BUFGLS.H2 1 1 1 1 0 0 1
1.BUFGLS.H3 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK4 0.F49.B1 0.F51.B0 0.F50.B1 0.F51.B1 0.F50.B0 0.F49.B0 0.F48.B1
0.VCLK 0 0 1 1 1 1 1
1.SINGLE.V4 0 1 0 1 1 1 1
1.QUAD.V1.0 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H2 1 0 1 1 1 0 1
1.BUFGLS.H3 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H4 1 1 1 0 1 0 1
1.BUFGLS.H5 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK5 0.F45.B1 0.F47.B1 0.F47.B0 0.F46.B1 0.F46.B0 0.F44.B0 0.F44.B1
0.QUAD.V2.3 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V5 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK6 0.F41.B1 0.F43.B1 0.F43.B0 0.F42.B1 0.F42.B0 0.F40.B0 0.F40.B1
0.QUAD.V2.4 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V6 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK7 0.F37.B1 0.F39.B0 0.F38.B1 0.F39.B1 0.F38.B0 0.F37.B0 0.F36.B1
0.VCLK 0 0 1 1 1 1 1
1.SINGLE.V7 0 1 0 1 1 1 1
1.QUAD.V2.0 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H2 1 0 1 1 1 0 1
1.BUFGLS.H3 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H4 1 1 1 0 1 0 1
1.BUFGLS.H5 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.LONG.V9 0.F22.B0 0.F21.B1
1.LONG.V9 0 0
1.VCLK 0 1
NONE 1 1
LLV:MUX.1.LONG.V7 0.F25.B0 0.F24.B1
0.LONG.V7 0 0
0.VCLK 0 1
NONE 1 1

Tile LLVQ.IO.R.T

Cells: 2

Bel BUFF

xc4000xv LLVQ.IO.R.T bel BUFF
PinDirectionWires
OoutputCELL1.OUT.BUFF

Switchbox LLV

xc4000xv LLVQ.IO.R.T switchbox LLV
DestinationSourceKind
CELL0.IO.DOUBLE.0.E.1CELL1.ECLK.Vpass transistor
CELL0.IO.DOUBLE.1.E.0CELL1.ECLK.Vpass transistor
CELL0.IO.DOUBLE.1.E.1CELL1.ECLK.Vpass transistor
CELL0.IO.DOUBLE.2.E.1CELL1.ECLK.Vpass transistor
CELL0.IO.DOUBLE.3.E.0CELL1.ECLK.Vpass transistor
CELL0.QUAD.V1.4CELL0.VCLKpass transistor
CELL0.QUAD.V2.4CELL1.VCLKpass transistor
CELL0.LONG.V0CELL1.LONG.V0buffer
CELL0.LONG.V1CELL1.LONG.V1buffer
CELL0.LONG.V2CELL1.LONG.V2buffer
CELL0.LONG.V3CELL1.LONG.V3buffer
CELL0.LONG.V4CELL1.LONG.V4buffer
CELL0.LONG.V5CELL1.LONG.V5buffer
CELL0.LONG.V6CELL1.LONG.V6buffer
CELL0.LONG.V7CELL1.LONG.V7.EXCLmux
CELL0.LONG.V8CELL1.LONG.V8buffer
CELL0.LONG.V9CELL1.LONG.V9.EXCLmux
CELL0.LONG.IO.V0CELL1.LONG.IO.V0buffer
CELL0.LONG.IO.V1CELL1.LONG.IO.V1buffer
CELL0.LONG.IO.V2CELL1.LONG.IO.V2buffer
CELL0.LONG.IO.V3CELL1.LONG.IO.V3buffer
CELL0.GCLK0CELL0.IO.DOUBLE.0.E.1mux
CELL0.IO.DOUBLE.2.E.1mux
CELL0.BUFGE.V0mux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL1.OUT.BUFFmux
CELL0.GCLK1CELL0.IO.DOUBLE.0.E.0mux
CELL0.IO.DOUBLE.2.E.0mux
CELL0.BUFGE.V1mux
CELL1.ECLK.Vmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK2CELL0.IO.DOUBLE.1.E.1mux
CELL0.IO.DOUBLE.3.E.1mux
CELL1.ECLK.Vmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL1.OUT.BUFFmux
CELL0.GCLK3CELL0.IO.DOUBLE.1.E.0mux
CELL0.IO.DOUBLE.3.E.0mux
CELL0.BUFGE.V0mux
CELL0.BUFGE.V1mux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK4CELL0.VCLKmux
CELL1.SINGLE.V4mux
CELL1.QUAD.V1.0mux
CELL1.VCLKmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK5CELL0.QUAD.V2.3mux
CELL0.VCLKmux
CELL1.SINGLE.V5mux
CELL1.VCLKmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK6CELL0.QUAD.V2.4mux
CELL0.VCLKmux
CELL1.SINGLE.V6mux
CELL1.VCLKmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL0.GCLK7CELL0.VCLKmux
CELL1.SINGLE.V7mux
CELL1.QUAD.V2.0mux
CELL1.VCLKmux
CELL1.BUFGLS.H0mux
CELL1.BUFGLS.H1mux
CELL1.BUFGLS.H2mux
CELL1.BUFGLS.H3mux
CELL1.BUFGLS.H4mux
CELL1.BUFGLS.H5mux
CELL1.BUFGLS.H6mux
CELL1.BUFGLS.H7mux
CELL1.SINGLE.V0CELL0.VCLKpass transistor
CELL1.SINGLE.V1CELL1.VCLKpass transistor
CELL1.SINGLE.V2CELL0.VCLKpass transistor
CELL1.SINGLE.V3CELL1.VCLKpass transistor
CELL1.SINGLE.V4CELL0.VCLKpass transistor
CELL1.SINGLE.V5CELL1.VCLKpass transistor
CELL1.SINGLE.V6CELL0.VCLKpass transistor
CELL1.SINGLE.V7CELL1.VCLKpass transistor
CELL1.QUAD.V0.0CELL1.VCLKpass transistor
CELL1.QUAD.V2.0CELL0.VCLKpass transistor
CELL1.LONG.V0CELL0.LONG.V0buffer
CELL1.LONG.V1CELL0.LONG.V1buffer
CELL1.LONG.V2CELL0.LONG.V2buffer
CELL1.LONG.V3CELL0.LONG.V3buffer
CELL1.LONG.V4CELL0.LONG.V4buffer
CELL1.LONG.V5CELL0.LONG.V5buffer
CELL1.LONG.V6CELL0.LONG.V6buffer
CELL1.LONG.V7CELL1.LONG.V7.EXCLmux
CELL1.LONG.V7.EXCLCELL0.LONG.V7mux
CELL0.VCLKmux
CELL1.LONG.V7mux
CELL1.LONG.V8CELL0.LONG.V8buffer
CELL1.LONG.V9CELL1.LONG.V9.EXCLmux
CELL1.LONG.V9.EXCLCELL0.LONG.V9mux
CELL1.LONG.V9mux
CELL1.VCLKmux
CELL1.LONG.IO.V0CELL0.LONG.IO.V0buffer
CELL1.LONG.IO.V1CELL0.LONG.IO.V1buffer
CELL1.LONG.IO.V2CELL0.LONG.IO.V2buffer
CELL1.LONG.IO.V3CELL0.LONG.IO.V3buffer

Bel wires

xc4000xv LLVQ.IO.R.T bel wires
WirePins
CELL1.OUT.BUFFBUFF.O

Bitstream

xc4000xv LLVQ.IO.R.T rect R0
BitFrame
F51 F50 F49 F48 F47 F46 F45 F44 F43 F42 F41 F40 F39 F38 F37 F36 F35 F34 F33 F32 F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B1 LLV:MUX.0.GCLK4[3] LLV:MUX.0.GCLK4[4] LLV:MUX.0.GCLK4[6] LLV:MUX.0.GCLK4[0] LLV:MUX.0.GCLK5[5] LLV:MUX.0.GCLK5[3] LLV:MUX.0.GCLK5[6] LLV:MUX.0.GCLK5[0] LLV:MUX.0.GCLK6[5] LLV:MUX.0.GCLK6[3] LLV:MUX.0.GCLK6[6] LLV:MUX.0.GCLK6[0] LLV:MUX.0.GCLK7[3] LLV:MUX.0.GCLK7[4] LLV:MUX.0.GCLK7[6] LLV:MUX.0.GCLK7[0] ~LLV:BUF.0.LONG.V5.1.LONG.V5 ~LLV:BUF.0.LONG.V3.1.LONG.V3 ~LLV:BUF.0.LONG.V2.1.LONG.V2 ~LLV:PASS.1.QUAD.V2.0.0.VCLK ~LLV:BUF.0.LONG.V0.1.LONG.V0 ~LLV:PASS.0.QUAD.V1.4.0.VCLK ~LLV:BUF.0.LONG.V4.1.LONG.V4 ~LLV:PASS.1.SINGLE.V3.1.VCLK ~LLV:BUF.0.LONG.V1.1.LONG.V1 ~LLV:BUF.0.LONG.V6.1.LONG.V6 ~LLV:BUF.0.LONG.V7.1.LONG.V7 LLV:MUX.1.LONG.V7[0] ~LLV:BUF.0.LONG.V8.1.LONG.V8 ~LLV:BUF.1.LONG.V9.0.LONG.V9 LLV:MUX.0.LONG.V9[0] ~LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0 ~LLV:PASS.0.IO.DOUBLE.3.E.0.1.ECLK.V ~LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2 ~LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3 ~LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1 LLV:MUX.0.GCLK2[4] LLV:MUX.0.GCLK2[5] LLV:MUX.0.GCLK2[6] LLV:MUX.0.GCLK2[0] LLV:MUX.0.GCLK0[5] LLV:MUX.0.GCLK0[4] LLV:MUX.0.GCLK0[6] LLV:MUX.0.GCLK0[0] LLV:MUX.0.GCLK1[5] LLV:MUX.0.GCLK1[4] LLV:MUX.0.GCLK1[6] LLV:MUX.0.GCLK1[0] LLV:MUX.0.GCLK3[4] LLV:MUX.0.GCLK3[5] LLV:MUX.0.GCLK3[6] LLV:MUX.0.GCLK3[0]
B0 LLV:MUX.0.GCLK4[5] LLV:MUX.0.GCLK4[2] LLV:MUX.0.GCLK4[1] ~LLV:PASS.1.SINGLE.V4.0.VCLK LLV:MUX.0.GCLK5[4] LLV:MUX.0.GCLK5[2] ~LLV:PASS.1.SINGLE.V5.1.VCLK LLV:MUX.0.GCLK5[1] LLV:MUX.0.GCLK6[4] LLV:MUX.0.GCLK6[2] ~LLV:PASS.1.SINGLE.V6.0.VCLK LLV:MUX.0.GCLK6[1] LLV:MUX.0.GCLK7[5] LLV:MUX.0.GCLK7[2] LLV:MUX.0.GCLK7[1] ~LLV:PASS.1.SINGLE.V7.1.VCLK ~LLV:BUF.1.LONG.V5.0.LONG.V5 ~LLV:BUF.1.LONG.V3.0.LONG.V3 ~LLV:BUF.1.LONG.V2.0.LONG.V2 ~LLV:PASS.0.QUAD.V2.4.1.VCLK ~LLV:BUF.1.LONG.V0.0.LONG.V0 ~LLV:PASS.1.QUAD.V0.0.1.VCLK ~LLV:BUF.1.LONG.V4.0.LONG.V4 ~LLV:PASS.1.SINGLE.V2.0.VCLK ~LLV:BUF.1.LONG.V1.0.LONG.V1 ~LLV:BUF.1.LONG.V6.0.LONG.V6 LLV:MUX.1.LONG.V7[1] ~LLV:PASS.1.SINGLE.V0.0.VCLK ~LLV:BUF.1.LONG.V8.0.LONG.V8 LLV:MUX.0.LONG.V9[1] ~LLV:PASS.1.SINGLE.V1.1.VCLK ~LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0 ~LLV:PASS.0.IO.DOUBLE.0.E.1.1.ECLK.V ~LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2 ~LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3 ~LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1 LLV:MUX.0.GCLK2[3] LLV:MUX.0.GCLK2[2] - LLV:MUX.0.GCLK2[1] LLV:MUX.0.GCLK0[3] LLV:MUX.0.GCLK0[2] ~LLV:PASS.0.IO.DOUBLE.1.E.0.1.ECLK.V LLV:MUX.0.GCLK0[1] LLV:MUX.0.GCLK1[2] LLV:MUX.0.GCLK1[3] ~LLV:PASS.0.IO.DOUBLE.1.E.1.1.ECLK.V LLV:MUX.0.GCLK1[1] LLV:MUX.0.GCLK3[3] LLV:MUX.0.GCLK3[2] ~LLV:PASS.0.IO.DOUBLE.2.E.1.1.ECLK.V LLV:MUX.0.GCLK3[1]
LLV:BUF.0.LONG.IO.V0.1.LONG.IO.V0 0.F20.B1
LLV:BUF.0.LONG.IO.V1.1.LONG.IO.V1 0.F16.B1
LLV:BUF.0.LONG.IO.V2.1.LONG.IO.V2 0.F18.B1
LLV:BUF.0.LONG.IO.V3.1.LONG.IO.V3 0.F17.B1
LLV:BUF.0.LONG.V0.1.LONG.V0 0.F31.B1
LLV:BUF.0.LONG.V1.1.LONG.V1 0.F27.B1
LLV:BUF.0.LONG.V2.1.LONG.V2 0.F33.B1
LLV:BUF.0.LONG.V3.1.LONG.V3 0.F34.B1
LLV:BUF.0.LONG.V4.1.LONG.V4 0.F29.B1
LLV:BUF.0.LONG.V5.1.LONG.V5 0.F35.B1
LLV:BUF.0.LONG.V6.1.LONG.V6 0.F26.B1
LLV:BUF.0.LONG.V7.1.LONG.V7 0.F25.B1
LLV:BUF.0.LONG.V8.1.LONG.V8 0.F23.B1
LLV:BUF.1.LONG.IO.V0.0.LONG.IO.V0 0.F20.B0
LLV:BUF.1.LONG.IO.V1.0.LONG.IO.V1 0.F16.B0
LLV:BUF.1.LONG.IO.V2.0.LONG.IO.V2 0.F18.B0
LLV:BUF.1.LONG.IO.V3.0.LONG.IO.V3 0.F17.B0
LLV:BUF.1.LONG.V0.0.LONG.V0 0.F31.B0
LLV:BUF.1.LONG.V1.0.LONG.V1 0.F27.B0
LLV:BUF.1.LONG.V2.0.LONG.V2 0.F33.B0
LLV:BUF.1.LONG.V3.0.LONG.V3 0.F34.B0
LLV:BUF.1.LONG.V4.0.LONG.V4 0.F29.B0
LLV:BUF.1.LONG.V5.0.LONG.V5 0.F35.B0
LLV:BUF.1.LONG.V6.0.LONG.V6 0.F26.B0
LLV:BUF.1.LONG.V8.0.LONG.V8 0.F23.B0
LLV:BUF.1.LONG.V9.0.LONG.V9 0.F22.B1
LLV:PASS.0.IO.DOUBLE.0.E.1.1.ECLK.V 0.F19.B0
LLV:PASS.0.IO.DOUBLE.1.E.0.1.ECLK.V 0.F9.B0
LLV:PASS.0.IO.DOUBLE.1.E.1.1.ECLK.V 0.F5.B0
LLV:PASS.0.IO.DOUBLE.2.E.1.1.ECLK.V 0.F1.B0
LLV:PASS.0.IO.DOUBLE.3.E.0.1.ECLK.V 0.F19.B1
LLV:PASS.0.QUAD.V1.4.0.VCLK 0.F30.B1
LLV:PASS.0.QUAD.V2.4.1.VCLK 0.F32.B0
LLV:PASS.1.QUAD.V0.0.1.VCLK 0.F30.B0
LLV:PASS.1.QUAD.V2.0.0.VCLK 0.F32.B1
LLV:PASS.1.SINGLE.V0.0.VCLK 0.F24.B0
LLV:PASS.1.SINGLE.V1.1.VCLK 0.F21.B0
LLV:PASS.1.SINGLE.V2.0.VCLK 0.F28.B0
LLV:PASS.1.SINGLE.V3.1.VCLK 0.F28.B1
LLV:PASS.1.SINGLE.V4.0.VCLK 0.F48.B0
LLV:PASS.1.SINGLE.V5.1.VCLK 0.F45.B0
LLV:PASS.1.SINGLE.V6.0.VCLK 0.F41.B0
LLV:PASS.1.SINGLE.V7.1.VCLK 0.F36.B0
inverted ~[0]
LLV:MUX.0.GCLK0 0.F9.B1 0.F11.B1 0.F10.B1 0.F11.B0 0.F10.B0 0.F8.B0 0.F8.B1
0.IO.DOUBLE.0.E.1 0 0 1 1 1 1 1
0.IO.DOUBLE.2.E.1 0 1 0 1 1 1 1
0.BUFGE.V0 0 1 1 0 1 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
1.OUT.BUFF 1 1 1 1 1 1 1
LLV:MUX.0.GCLK1 0.F5.B1 0.F7.B1 0.F6.B1 0.F6.B0 0.F7.B0 0.F4.B0 0.F4.B1
0.IO.DOUBLE.0.E.0 0 0 1 1 1 1 1
0.IO.DOUBLE.2.E.0 0 1 0 1 1 1 1
0.BUFGE.V1 0 1 1 0 1 1 1
1.ECLK.V 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H0 1 1 1 0 1 0 1
1.BUFGLS.H1 1 1 1 0 1 1 0
1.BUFGLS.H2 1 1 1 1 0 0 1
1.BUFGLS.H3 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK2 0.F13.B1 0.F14.B1 0.F15.B1 0.F15.B0 0.F14.B0 0.F12.B0 0.F12.B1
0.IO.DOUBLE.1.E.1 0 0 1 1 1 1 1
0.IO.DOUBLE.3.E.1 0 1 0 1 1 1 1
1.ECLK.V 0 1 1 0 1 1 1
1.BUFGLS.H6 1 0 1 1 1 0 1
1.BUFGLS.H7 1 0 1 1 1 1 0
1.BUFGLS.H4 1 1 0 1 1 0 1
1.BUFGLS.H5 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
1.OUT.BUFF 1 1 1 1 1 1 1
LLV:MUX.0.GCLK3 0.F1.B1 0.F2.B1 0.F3.B1 0.F3.B0 0.F2.B0 0.F0.B0 0.F0.B1
0.IO.DOUBLE.1.E.0 0 0 1 1 1 1 1
0.IO.DOUBLE.3.E.0 0 1 0 1 1 1 1
0.BUFGE.V0 0 1 1 0 1 1 1
0.BUFGE.V1 0 1 1 1 0 1 1
1.BUFGLS.H6 1 0 1 1 1 0 1
1.BUFGLS.H7 1 0 1 1 1 1 0
1.BUFGLS.H4 1 1 0 1 1 0 1
1.BUFGLS.H5 1 1 0 1 1 1 0
1.BUFGLS.H2 1 1 1 0 1 0 1
1.BUFGLS.H3 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK4 0.F49.B1 0.F51.B0 0.F50.B1 0.F51.B1 0.F50.B0 0.F49.B0 0.F48.B1
0.VCLK 0 0 1 1 1 1 1
1.SINGLE.V4 0 1 0 1 1 1 1
1.QUAD.V1.0 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H2 1 0 1 1 1 0 1
1.BUFGLS.H3 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H4 1 1 1 0 1 0 1
1.BUFGLS.H5 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK5 0.F45.B1 0.F47.B1 0.F47.B0 0.F46.B1 0.F46.B0 0.F44.B0 0.F44.B1
0.QUAD.V2.3 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V5 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK6 0.F41.B1 0.F43.B1 0.F43.B0 0.F42.B1 0.F42.B0 0.F40.B0 0.F40.B1
0.QUAD.V2.4 0 0 1 1 1 1 1
0.VCLK 0 1 0 1 1 1 1
1.SINGLE.V6 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H4 1 0 1 1 1 0 1
1.BUFGLS.H5 1 0 1 1 1 1 0
1.BUFGLS.H2 1 1 0 1 1 0 1
1.BUFGLS.H3 1 1 0 1 1 1 0
1.BUFGLS.H6 1 1 1 0 1 0 1
1.BUFGLS.H7 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.GCLK7 0.F37.B1 0.F39.B0 0.F38.B1 0.F39.B1 0.F38.B0 0.F37.B0 0.F36.B1
0.VCLK 0 0 1 1 1 1 1
1.SINGLE.V7 0 1 0 1 1 1 1
1.QUAD.V2.0 0 1 1 0 1 1 1
1.VCLK 0 1 1 1 0 1 1
1.BUFGLS.H2 1 0 1 1 1 0 1
1.BUFGLS.H3 1 0 1 1 1 1 0
1.BUFGLS.H6 1 1 0 1 1 0 1
1.BUFGLS.H7 1 1 0 1 1 1 0
1.BUFGLS.H4 1 1 1 0 1 0 1
1.BUFGLS.H5 1 1 1 0 1 1 0
1.BUFGLS.H0 1 1 1 1 0 0 1
1.BUFGLS.H1 1 1 1 1 0 1 0
NONE 1 1 1 1 1 1 1
LLV:MUX.0.LONG.V9 0.F22.B0 0.F21.B1
1.LONG.V9 0 0
1.VCLK 0 1
NONE 1 1
LLV:MUX.1.LONG.V7 0.F25.B0 0.F24.B1
0.LONG.V7 0 0
0.VCLK 0 1
NONE 1 1

Tile CLKQ

Cells: 2

Bel CLKQ

xc4000xv CLKQ bel CLKQ
PinDirectionWires
O.LL.H.LoutputCELL0.BUFGLS.H2
O.LL.H.RoutputCELL1.BUFGLS.H2
O.LL.V.LoutputCELL0.BUFGLS.H1
O.LL.V.RoutputCELL1.BUFGLS.H1
O.LR.H.LoutputCELL0.BUFGLS.H3
O.LR.H.RoutputCELL1.BUFGLS.H3
O.LR.V.LoutputCELL0.BUFGLS.H4
O.LR.V.RoutputCELL1.BUFGLS.H4
O.UL.H.LoutputCELL0.BUFGLS.H7
O.UL.H.RoutputCELL1.BUFGLS.H7
O.UL.V.LoutputCELL0.BUFGLS.H0
O.UL.V.RoutputCELL1.BUFGLS.H0
O.UR.H.LoutputCELL0.BUFGLS.H6
O.UR.H.RoutputCELL1.BUFGLS.H6
O.UR.V.LoutputCELL0.BUFGLS.H5
O.UR.V.RoutputCELL1.BUFGLS.H5

Bel wires

xc4000xv CLKQ bel wires
WirePins
CELL0.BUFGLS.H0CLKQ.O.UL.V.L
CELL0.BUFGLS.H1CLKQ.O.LL.V.L
CELL0.BUFGLS.H2CLKQ.O.LL.H.L
CELL0.BUFGLS.H3CLKQ.O.LR.H.L
CELL0.BUFGLS.H4CLKQ.O.LR.V.L
CELL0.BUFGLS.H5CLKQ.O.UR.V.L
CELL0.BUFGLS.H6CLKQ.O.UR.H.L
CELL0.BUFGLS.H7CLKQ.O.UL.H.L
CELL1.BUFGLS.H0CLKQ.O.UL.V.R
CELL1.BUFGLS.H1CLKQ.O.LL.V.R
CELL1.BUFGLS.H2CLKQ.O.LL.H.R
CELL1.BUFGLS.H3CLKQ.O.LR.H.R
CELL1.BUFGLS.H4CLKQ.O.LR.V.R
CELL1.BUFGLS.H5CLKQ.O.UR.V.R
CELL1.BUFGLS.H6CLKQ.O.UR.H.R
CELL1.BUFGLS.H7CLKQ.O.UL.H.R