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Splitters

Tile CLKL

Cells: 2 IRIs: 0

Muxes

xc5200 CLKL muxes
DestinationSources
TCELL0:LONG.V0TCELL1:LONG.V0
TCELL0:LONG.V1TCELL1:LONG.V1
TCELL0:LONG.V2TCELL1:LONG.V2
TCELL0:LONG.V3TCELL1:LONG.V3
TCELL0:LONG.V4TCELL1:LONG.V4
TCELL0:LONG.V5TCELL1:LONG.V5
TCELL0:LONG.V6TCELL1:LONG.V6
TCELL0:LONG.V7TCELL1:LONG.V7
TCELL1:LONG.V0TCELL0:LONG.V0
TCELL1:LONG.V1TCELL0:LONG.V1
TCELL1:LONG.V2TCELL0:LONG.V2
TCELL1:LONG.V3TCELL0:LONG.V3
TCELL1:LONG.V4TCELL0:LONG.V4
TCELL1:LONG.V5TCELL0:LONG.V5
TCELL1:LONG.V6TCELL0:LONG.V6
TCELL1:LONG.V7TCELL0:LONG.V7

Bitstream

xc5200 CLKL bittile 0
BitFrame
6 5 4 3 2 1 0
3 ~INT:BIPASS.0.LONG.V7.1.LONG.V7 ~INT:BIPASS.0.LONG.V3.1.LONG.V3 ~INT:BIPASS.0.LONG.V4.1.LONG.V4 ~INT:BIPASS.0.LONG.V0.1.LONG.V0 ~INT:BIPASS.0.LONG.V1.1.LONG.V1 ~INT:BIPASS.0.LONG.V6.1.LONG.V6 ~INT:BIPASS.0.LONG.V5.1.LONG.V5
2 - - - - - - -
1 - - - - - - -
0 - - - - - - -
xc5200 CLKL bittile 1
BitFrame
6 5 4 3 2 1 0
0 INT:BIPASS.0.LONG.V2.1.LONG.V2 - - - - - -
INT:BIPASS.0.LONG.V0.1.LONG.V0 0.3.3
INT:BIPASS.0.LONG.V1.1.LONG.V1 0.2.3
INT:BIPASS.0.LONG.V3.1.LONG.V3 0.5.3
INT:BIPASS.0.LONG.V4.1.LONG.V4 0.4.3
INT:BIPASS.0.LONG.V5.1.LONG.V5 0.0.3
INT:BIPASS.0.LONG.V6.1.LONG.V6 0.1.3
INT:BIPASS.0.LONG.V7.1.LONG.V7 0.6.3
inverted ~[0]
INT:BIPASS.0.LONG.V2.1.LONG.V2 1.6.0
non-inverted [0]

Tile CLKH

Cells: 2 IRIs: 0

Muxes

xc5200 CLKH muxes
DestinationSources
TCELL0:LONG.V0TCELL1:LONG.V0
TCELL0:LONG.V1TCELL1:LONG.V1
TCELL0:LONG.V2TCELL1:LONG.V2
TCELL0:LONG.V3TCELL1:LONG.V3
TCELL0:LONG.V4TCELL1:LONG.V4
TCELL0:LONG.V5TCELL1:LONG.V5
TCELL0:LONG.V6TCELL1:LONG.V6
TCELL0:LONG.V7TCELL1:LONG.V7
TCELL1:LONG.V0TCELL0:LONG.V0
TCELL1:LONG.V1TCELL0:LONG.V1
TCELL1:LONG.V2TCELL0:LONG.V2
TCELL1:LONG.V3TCELL0:LONG.V3
TCELL1:LONG.V4TCELL0:LONG.V4
TCELL1:LONG.V5TCELL0:LONG.V5
TCELL1:LONG.V6TCELL0:LONG.V6
TCELL1:LONG.V7TCELL0:LONG.V7

Bitstream

xc5200 CLKH bittile 0
BitFrame
10 9 8 7 6 5 4 3 2 1 0
3 ~INT:BIPASS.0.LONG.V0.1.LONG.V0 ~INT:BIPASS.0.LONG.V1.1.LONG.V1 ~INT:BIPASS.0.LONG.V2.1.LONG.V2 ~INT:BIPASS.0.LONG.V3.1.LONG.V3 ~INT:BIPASS.0.LONG.V4.1.LONG.V4 ~INT:BIPASS.0.LONG.V5.1.LONG.V5 ~INT:BIPASS.0.LONG.V6.1.LONG.V6 ~INT:BIPASS.0.LONG.V7.1.LONG.V7 - - -
2 - - - - - - - - - - -
1 - - - - - - - - - - -
0 - - - - - - - - - - -
INT:BIPASS.0.LONG.V0.1.LONG.V0 0.10.3
INT:BIPASS.0.LONG.V1.1.LONG.V1 0.9.3
INT:BIPASS.0.LONG.V2.1.LONG.V2 0.8.3
INT:BIPASS.0.LONG.V3.1.LONG.V3 0.7.3
INT:BIPASS.0.LONG.V4.1.LONG.V4 0.6.3
INT:BIPASS.0.LONG.V5.1.LONG.V5 0.5.3
INT:BIPASS.0.LONG.V6.1.LONG.V6 0.4.3
INT:BIPASS.0.LONG.V7.1.LONG.V7 0.3.3
inverted ~[0]

Tile CLKR

Cells: 2 IRIs: 0

Muxes

xc5200 CLKR muxes
DestinationSources
TCELL0:LONG.V0TCELL1:LONG.V0
TCELL0:LONG.V1TCELL1:LONG.V1
TCELL0:LONG.V2TCELL1:LONG.V2
TCELL0:LONG.V3TCELL1:LONG.V3
TCELL0:LONG.V4TCELL1:LONG.V4
TCELL0:LONG.V5TCELL1:LONG.V5
TCELL0:LONG.V6TCELL1:LONG.V6
TCELL0:LONG.V7TCELL1:LONG.V7
TCELL1:LONG.V0TCELL0:LONG.V0
TCELL1:LONG.V1TCELL0:LONG.V1
TCELL1:LONG.V2TCELL0:LONG.V2
TCELL1:LONG.V3TCELL0:LONG.V3
TCELL1:LONG.V4TCELL0:LONG.V4
TCELL1:LONG.V5TCELL0:LONG.V5
TCELL1:LONG.V6TCELL0:LONG.V6
TCELL1:LONG.V7TCELL0:LONG.V7

Bitstream

xc5200 CLKR bittile 0
BitFrame
6 5 4 3 2 1 0
3 ~INT:BIPASS.0.LONG.V5.1.LONG.V5 ~INT:BIPASS.0.LONG.V6.1.LONG.V6 ~INT:BIPASS.0.LONG.V1.1.LONG.V1 ~INT:BIPASS.0.LONG.V0.1.LONG.V0 ~INT:BIPASS.0.LONG.V4.1.LONG.V4 ~INT:BIPASS.0.LONG.V3.1.LONG.V3 ~INT:BIPASS.0.LONG.V7.1.LONG.V7
2 - - - - - - -
1 - - - - - - -
0 - - - - - - -
xc5200 CLKR bittile 1
BitFrame
0
0 INT:BIPASS.0.LONG.V2.1.LONG.V2
INT:BIPASS.0.LONG.V0.1.LONG.V0 0.3.3
INT:BIPASS.0.LONG.V1.1.LONG.V1 0.4.3
INT:BIPASS.0.LONG.V3.1.LONG.V3 0.1.3
INT:BIPASS.0.LONG.V4.1.LONG.V4 0.2.3
INT:BIPASS.0.LONG.V5.1.LONG.V5 0.6.3
INT:BIPASS.0.LONG.V6.1.LONG.V6 0.5.3
INT:BIPASS.0.LONG.V7.1.LONG.V7 0.0.3
inverted ~[0]
INT:BIPASS.0.LONG.V2.1.LONG.V2 1.0.0
non-inverted [0]

Tile CLKB

Cells: 2 IRIs: 0

Muxes

xc5200 CLKB muxes
DestinationSources
TCELL0:LONG.H0TCELL1:LONG.H0
TCELL0:LONG.H1TCELL1:LONG.H1
TCELL0:LONG.H2TCELL1:LONG.H2
TCELL0:LONG.H3TCELL1:LONG.H3
TCELL0:LONG.H4TCELL1:LONG.H4
TCELL0:LONG.H5TCELL1:LONG.H5
TCELL0:LONG.H6TCELL1:LONG.H6
TCELL0:LONG.H7TCELL1:LONG.H7
TCELL1:LONG.H0TCELL0:LONG.H0
TCELL1:LONG.H1TCELL0:LONG.H1
TCELL1:LONG.H2TCELL0:LONG.H2
TCELL1:LONG.H3TCELL0:LONG.H3
TCELL1:LONG.H4TCELL0:LONG.H4
TCELL1:LONG.H5TCELL0:LONG.H5
TCELL1:LONG.H6TCELL0:LONG.H6
TCELL1:LONG.H7TCELL0:LONG.H7

Bitstream

xc5200 CLKB bittile 0
BitFrame
0
27 ~INT:BIPASS.0.LONG.H7.1.LONG.H7
26 -
25 -
24 -
23 -
22 -
21 ~INT:BIPASS.0.LONG.H6.1.LONG.H6
20 -
19 ~INT:BIPASS.0.LONG.H5.1.LONG.H5
18 -
17 -
16 -
15 -
14 -
13 ~INT:BIPASS.0.LONG.H4.1.LONG.H4
12 ~INT:BIPASS.0.LONG.H3.1.LONG.H3
11 -
10 -
9 -
8 -
7 -
6 ~INT:BIPASS.0.LONG.H2.1.LONG.H2
5 -
4 ~INT:BIPASS.0.LONG.H1.1.LONG.H1
3 -
2 -
1 -
0 ~INT:BIPASS.0.LONG.H0.1.LONG.H0
INT:BIPASS.0.LONG.H0.1.LONG.H0 0.0.0
INT:BIPASS.0.LONG.H1.1.LONG.H1 0.0.4
INT:BIPASS.0.LONG.H2.1.LONG.H2 0.0.6
INT:BIPASS.0.LONG.H3.1.LONG.H3 0.0.12
INT:BIPASS.0.LONG.H4.1.LONG.H4 0.0.13
INT:BIPASS.0.LONG.H5.1.LONG.H5 0.0.19
INT:BIPASS.0.LONG.H6.1.LONG.H6 0.0.21
INT:BIPASS.0.LONG.H7.1.LONG.H7 0.0.27
inverted ~[0]

Tile CLKV

Cells: 2 IRIs: 0

Muxes

xc5200 CLKV muxes
DestinationSources
TCELL0:LONG.H0TCELL1:LONG.H0
TCELL0:LONG.H1TCELL1:LONG.H1
TCELL0:LONG.H2TCELL1:LONG.H2
TCELL0:LONG.H3TCELL1:LONG.H3
TCELL0:LONG.H4TCELL1:LONG.H4
TCELL0:LONG.H5TCELL1:LONG.H5
TCELL0:LONG.H6TCELL1:LONG.H6
TCELL0:LONG.H7TCELL1:LONG.H7
TCELL1:LONG.H0TCELL0:LONG.H0
TCELL1:LONG.H1TCELL0:LONG.H1
TCELL1:LONG.H2TCELL0:LONG.H2
TCELL1:LONG.H3TCELL0:LONG.H3
TCELL1:LONG.H4TCELL0:LONG.H4
TCELL1:LONG.H5TCELL0:LONG.H5
TCELL1:LONG.H6TCELL0:LONG.H6
TCELL1:LONG.H7TCELL0:LONG.H7

Bitstream

xc5200 CLKV bittile 0
BitFrame
0
33 ~INT:BIPASS.0.LONG.H7.1.LONG.H7
32 -
31 -
30 -
29 -
28 -
27 ~INT:BIPASS.0.LONG.H3.1.LONG.H3
26 -
25 -
24 ~INT:BIPASS.0.LONG.H2.1.LONG.H2
23 -
22 -
21 -
20 -
19 ~INT:BIPASS.0.LONG.H6.1.LONG.H6
18 -
17 -
16 ~INT:BIPASS.0.LONG.H1.1.LONG.H1
15 -
14 -
13 -
12 -
11 -
10 ~INT:BIPASS.0.LONG.H5.1.LONG.H5
9 -
8 ~INT:BIPASS.0.LONG.H0.1.LONG.H0
7 -
6 -
5 -
4 -
3 ~INT:BIPASS.0.LONG.H4.1.LONG.H4
2 -
1 -
0 -
INT:BIPASS.0.LONG.H0.1.LONG.H0 0.0.8
INT:BIPASS.0.LONG.H1.1.LONG.H1 0.0.16
INT:BIPASS.0.LONG.H2.1.LONG.H2 0.0.24
INT:BIPASS.0.LONG.H3.1.LONG.H3 0.0.27
INT:BIPASS.0.LONG.H4.1.LONG.H4 0.0.3
INT:BIPASS.0.LONG.H5.1.LONG.H5 0.0.10
INT:BIPASS.0.LONG.H6.1.LONG.H6 0.0.19
INT:BIPASS.0.LONG.H7.1.LONG.H7 0.0.33
inverted ~[0]

Tile CLKT

Cells: 2 IRIs: 0

Muxes

xc5200 CLKT muxes
DestinationSources
TCELL0:LONG.H0TCELL1:LONG.H0
TCELL0:LONG.H1TCELL1:LONG.H1
TCELL0:LONG.H2TCELL1:LONG.H2
TCELL0:LONG.H3TCELL1:LONG.H3
TCELL0:LONG.H4TCELL1:LONG.H4
TCELL0:LONG.H5TCELL1:LONG.H5
TCELL0:LONG.H6TCELL1:LONG.H6
TCELL0:LONG.H7TCELL1:LONG.H7
TCELL1:LONG.H0TCELL0:LONG.H0
TCELL1:LONG.H1TCELL0:LONG.H1
TCELL1:LONG.H2TCELL0:LONG.H2
TCELL1:LONG.H3TCELL0:LONG.H3
TCELL1:LONG.H4TCELL0:LONG.H4
TCELL1:LONG.H5TCELL0:LONG.H5
TCELL1:LONG.H6TCELL0:LONG.H6
TCELL1:LONG.H7TCELL0:LONG.H7

Bitstream

xc5200 CLKT bittile 0
BitFrame
0
27 ~INT:BIPASS.0.LONG.H1.1.LONG.H1
26 -
25 -
24 ~INT:BIPASS.0.LONG.H2.1.LONG.H2
23 -
22 -
21 ~INT:BIPASS.0.LONG.H4.1.LONG.H4
20 -
19 -
18 -
17 -
16 ~INT:BIPASS.0.LONG.H0.1.LONG.H0
15 -
14 ~INT:BIPASS.0.LONG.H5.1.LONG.H5
13 -
12 -
11 -
10 -
9 -
8 ~INT:BIPASS.0.LONG.H3.1.LONG.H3
7 -
6 ~INT:BIPASS.0.LONG.H6.1.LONG.H6
5 -
4 -
3 -
2 -
1 -
0 ~INT:BIPASS.0.LONG.H7.1.LONG.H7
INT:BIPASS.0.LONG.H0.1.LONG.H0 0.0.16
INT:BIPASS.0.LONG.H1.1.LONG.H1 0.0.27
INT:BIPASS.0.LONG.H2.1.LONG.H2 0.0.24
INT:BIPASS.0.LONG.H3.1.LONG.H3 0.0.8
INT:BIPASS.0.LONG.H4.1.LONG.H4 0.0.21
INT:BIPASS.0.LONG.H5.1.LONG.H5 0.0.14
INT:BIPASS.0.LONG.H6.1.LONG.H6 0.0.6
INT:BIPASS.0.LONG.H7.1.LONG.H7 0.0.0
inverted ~[0]