Keyboard shortcuts

Press ← or → to navigate between chapters

Press ? to show this help

Press Esc to hide this help

Corners

Tile CNR.BL

Cells: 1

Switchbox INT

xc5200 CNR.BL switchbox INT
DestinationSourceKind
IO.SINGLE.L.N0OUT.RDBK.RIPpass transistor
IO.SINGLE.L.N1OUT.RDBK.RIPpass transistor
IO.SINGLE.L.N2OUT.RDBK.RIPpass transistor
IO.SINGLE.L.N3OUT.RDBK.RIPpass transistor
IO.SINGLE.L.N4OUT.RDBK.DATApass transistor
IO.SINGLE.L.N5OUT.RDBK.DATApass transistor
IO.SINGLE.L.N6OUT.RDBK.DATApass transistor
IO.SINGLE.L.N7OUT.RDBK.DATApass transistor
LONG.H0OUT.RDBK.RIPpass transistor
LONG.V0bidirectional pass transistor
LONG.H1OUT.RDBK.RIPpass transistor
LONG.V1bidirectional pass transistor
LONG.H2OUT.RDBK.RIPpass transistor
LONG.V2bidirectional pass transistor
LONG.H3OUT.RDBK.RIPpass transistor
LONG.V3bidirectional pass transistor
LONG.H4OUT.RDBK.DATApass transistor
LONG.V4bidirectional pass transistor
LONG.H5OUT.RDBK.DATApass transistor
LONG.V5bidirectional pass transistor
LONG.H6OUT.RDBK.DATApass transistor
LONG.V6bidirectional pass transistor
LONG.H7OUT.RDBK.DATApass transistor
LONG.V7bidirectional pass transistor
LONG.V0LONG.H0bidirectional pass transistor
LONG.V1LONG.H1bidirectional pass transistor
LONG.V2LONG.H2bidirectional pass transistor
LONG.V3LONG.H3bidirectional pass transistor
LONG.V4LONG.H4bidirectional pass transistor
LONG.V5LONG.H5bidirectional pass transistor
LONG.V6LONG.H6bidirectional pass transistor
LONG.V7LONG.H7bidirectional pass transistor
IMUX.RDBK.RCLKIO.SINGLE.L.N0mux
IO.SINGLE.L.N1mux
IO.SINGLE.L.N2mux
IO.SINGLE.L.N3mux
LONG.H0mux
LONG.H1mux
LONG.H2mux
LONG.H3mux
IMUX.RDBK.TRIGGNDmux
IO.SINGLE.L.N4mux
IO.SINGLE.L.N5mux
IO.SINGLE.L.N6mux
LONG.H4mux
LONG.H5mux
LONG.H6mux
LONG.H7mux
IMUX.BUFGGNDmux
IO.SINGLE.L.N0mux
IO.SINGLE.L.N1mux
IO.SINGLE.L.N2mux
IO.SINGLE.L.N3mux
LONG.V4mux
LONG.V5mux
LONG.V6mux
LONG.V7mux
OUT.CLKIOBmux

Bel BUFG

xc5200 CNR.BL bel BUFG
PinDirectionWires
IinputIMUX.BUFG
OoutputGLOBAL.BL

Bel CLKIOB

xc5200 CNR.BL bel CLKIOB
PinDirectionWires
OUToutputOUT.CLKIOB

Bel RDBK

xc5200 CNR.BL bel RDBK
PinDirectionWires
CKinputIMUX.RDBK.RCLK
DATAoutputOUT.RDBK.DATA
RIPoutputOUT.RDBK.RIP
TRIGinputIMUX.RDBK.TRIG

Bel wires

xc5200 CNR.BL bel wires
WirePins
GLOBAL.BLBUFG.O
OUT.CLKIOBCLKIOB.OUT
OUT.RDBK.RIPRDBK.RIP
OUT.RDBK.DATARDBK.DATA
IMUX.RDBK.RCLKRDBK.CK
IMUX.RDBK.TRIGRDBK.TRIG
IMUX.BUFGBUFG.I

Bitstream

xc5200 CNR.BL bittile 0
BitFrame
6 5 4 3 2 1 0
27 INT:MUX.IMUX.BUFG[5] INT:MUX.IMUX.BUFG[8] - - INT:MUX.IMUX.RDBK.TRIG[2] INT:MUX.IMUX.RDBK.TRIG[1] ~INT:PASS.IO.SINGLE.L.N7.OUT.RDBK.DATA
26 INT:MUX.IMUX.BUFG[6] INT:MUX.IMUX.BUFG[7] - - INT:MUX.IMUX.RDBK.TRIG[0] ~INT:PASS.IO.SINGLE.L.N6.OUT.RDBK.DATA ~INT:PASS.LONG.H6.OUT.RDBK.DATA
25 - - - - INT:MUX.IMUX.RDBK.RCLK[1] - -
24 - - - - INT:MUX.IMUX.RDBK.RCLK[2] ~INT:PASS.LONG.H7.OUT.RDBK.DATA ~INT:PASS.IO.SINGLE.L.N5.OUT.RDBK.DATA
23 - - - - INT:MUX.IMUX.RDBK.RCLK[0] ~INT:PASS.IO.SINGLE.L.N4.OUT.RDBK.DATA -
22 - - - - - ~INT:PASS.LONG.H5.OUT.RDBK.DATA ~INT:PASS.LONG.H4.OUT.RDBK.DATA
21 - - - - - - -
20 - - - - - ~INT:PASS.IO.SINGLE.L.N2.OUT.RDBK.RIP ~INT:PASS.IO.SINGLE.L.N3.OUT.RDBK.RIP
19 - - - - - - -
18 - - - - INT:MUX.IMUX.BUFG[4] ~INT:PASS.LONG.H3.OUT.RDBK.RIP ~INT:PASS.LONG.H2.OUT.RDBK.RIP
17 - - - - INT:MUX.IMUX.BUFG[3] - -
16 - - - - INT:MUX.IMUX.BUFG[2] ~INT:PASS.IO.SINGLE.L.N0.OUT.RDBK.RIP ~INT:PASS.IO.SINGLE.L.N1.OUT.RDBK.RIP
15 - - - - INT:MUX.IMUX.BUFG[1] ~INT:PASS.LONG.H1.OUT.RDBK.RIP -
14 - - - - INT:MUX.IMUX.BUFG[0] ~INT:BIPASS.LONG.H2.LONG.V2 ~INT:PASS.LONG.H0.OUT.RDBK.RIP
13 - - - - - ~INT:BIPASS.LONG.H1.LONG.V1 -
12 - - - - - - -
11 - - - - - ~INT:BIPASS.LONG.H0.LONG.V0 ~INT:BIPASS.LONG.H4.LONG.V4
10 - - - - - - ~INT:BIPASS.LONG.H3.LONG.V3
9 - - - - - ~INT:BIPASS.LONG.H5.LONG.V5 -
8 - - - - - ~INT:BIPASS.LONG.H7.LONG.V7 ~INT:BIPASS.LONG.H6.LONG.V6
7 - - - - - - -
6 - - - - - RDBK:READ_CLK[0] -
5 - - - - - - -
4 - - - - ~MISC:READ_CAPTURE ~MISC:READ_ABORT MISC:SCAN_TEST[2]
3 - - - - MISC:SCAN_TEST[0] - -
2 - - - - MISC:SCAN_TEST[1] - -
1 - - - - - - -
0 - - - - - - -
INT:BIPASS.LONG.H0.LONG.V0 0.1.11
INT:BIPASS.LONG.H1.LONG.V1 0.1.13
INT:BIPASS.LONG.H2.LONG.V2 0.1.14
INT:BIPASS.LONG.H3.LONG.V3 0.0.10
INT:BIPASS.LONG.H4.LONG.V4 0.0.11
INT:BIPASS.LONG.H5.LONG.V5 0.1.9
INT:BIPASS.LONG.H6.LONG.V6 0.0.8
INT:BIPASS.LONG.H7.LONG.V7 0.1.8
INT:PASS.IO.SINGLE.L.N0.OUT.RDBK.RIP 0.1.16
INT:PASS.IO.SINGLE.L.N1.OUT.RDBK.RIP 0.0.16
INT:PASS.IO.SINGLE.L.N2.OUT.RDBK.RIP 0.1.20
INT:PASS.IO.SINGLE.L.N3.OUT.RDBK.RIP 0.0.20
INT:PASS.IO.SINGLE.L.N4.OUT.RDBK.DATA 0.1.23
INT:PASS.IO.SINGLE.L.N5.OUT.RDBK.DATA 0.0.24
INT:PASS.IO.SINGLE.L.N6.OUT.RDBK.DATA 0.1.26
INT:PASS.IO.SINGLE.L.N7.OUT.RDBK.DATA 0.0.27
INT:PASS.LONG.H0.OUT.RDBK.RIP 0.0.14
INT:PASS.LONG.H1.OUT.RDBK.RIP 0.1.15
INT:PASS.LONG.H2.OUT.RDBK.RIP 0.0.18
INT:PASS.LONG.H3.OUT.RDBK.RIP 0.1.18
INT:PASS.LONG.H4.OUT.RDBK.DATA 0.0.22
INT:PASS.LONG.H5.OUT.RDBK.DATA 0.1.22
INT:PASS.LONG.H6.OUT.RDBK.DATA 0.0.26
INT:PASS.LONG.H7.OUT.RDBK.DATA 0.1.24
MISC:READ_ABORT 0.1.4
MISC:READ_CAPTURE 0.2.4
inverted ~[0]
INT:MUX.IMUX.BUFG 0.5.27 0.5.26 0.6.26 0.6.27 0.2.18 0.2.17 0.2.16 0.2.15 0.2.14
IO.SINGLE.L.N0 0 1 1 1 1 1 1 1 1
IO.SINGLE.L.N1 1 0 1 1 1 1 1 1 1
IO.SINGLE.L.N2 1 1 0 1 1 1 1 1 1
IO.SINGLE.L.N3 1 1 1 0 1 1 1 1 1
LONG.V4 1 1 1 1 0 1 1 1 1
LONG.V5 1 1 1 1 1 0 1 1 1
LONG.V6 1 1 1 1 1 1 0 1 1
LONG.V7 1 1 1 1 1 1 1 0 1
OUT.CLKIOB 1 1 1 1 1 1 1 1 0
GND 1 1 1 1 1 1 1 1 1
INT:MUX.IMUX.RDBK.RCLK 0.2.24 0.2.25 0.2.23
LONG.H1 0 0 0
IO.SINGLE.L.N1 0 0 1
LONG.H0 0 1 0
IO.SINGLE.L.N0 0 1 1
LONG.H3 1 0 0
IO.SINGLE.L.N2 1 0 1
LONG.H2 1 1 0
IO.SINGLE.L.N3 1 1 1
INT:MUX.IMUX.RDBK.TRIG 0.2.27 0.1.27 0.2.26
LONG.H4 0 0 0
IO.SINGLE.L.N4 0 0 1
LONG.H5 0 1 0
IO.SINGLE.L.N5 0 1 1
LONG.H6 1 0 0
IO.SINGLE.L.N6 1 0 1
LONG.H7 1 1 0
GND 1 1 1
MISC:SCAN_TEST 0.0.4 0.2.2 0.2.3
ENABLE 0 1 1
ENLL 1 0 1
NE7 1 1 0
DISABLE 1 1 1
RDBK:READ_CLK 0.1.6
RDBK 0
CCLK 1

Tile CNR.BR

Cells: 1

Switchbox INT

xc5200 CNR.BR switchbox INT
DestinationSourceKind
IO.SINGLE.B.W0OUT.STARTUP.DONEINpass transistor
IO.SINGLE.B.W1OUT.STARTUP.DONEINpass transistor
IO.SINGLE.B.W2OUT.STARTUP.Q3pass transistor
IO.SINGLE.B.W3OUT.STARTUP.Q3pass transistor
IO.SINGLE.B.W4OUT.STARTUP.Q2pass transistor
IO.SINGLE.B.W5OUT.STARTUP.Q2pass transistor
IO.SINGLE.B.W6OUT.STARTUP.Q1Q4pass transistor
IO.SINGLE.B.W7OUT.STARTUP.Q1Q4pass transistor
LONG.H0LONG.V0bidirectional pass transistor
LONG.H1LONG.V1bidirectional pass transistor
LONG.H2LONG.V2bidirectional pass transistor
LONG.H3LONG.V3bidirectional pass transistor
LONG.H4LONG.V4bidirectional pass transistor
LONG.H5LONG.V5bidirectional pass transistor
LONG.H6LONG.V6bidirectional pass transistor
LONG.H7LONG.V7bidirectional pass transistor
LONG.V0OUT.STARTUP.DONEINpass transistor
LONG.H0bidirectional pass transistor
LONG.V1OUT.STARTUP.DONEINpass transistor
LONG.H1bidirectional pass transistor
LONG.V2OUT.STARTUP.Q3pass transistor
LONG.H2bidirectional pass transistor
LONG.V3OUT.STARTUP.Q3pass transistor
LONG.H3bidirectional pass transistor
LONG.V4OUT.STARTUP.Q2pass transistor
LONG.H4bidirectional pass transistor
LONG.V5OUT.STARTUP.Q2pass transistor
LONG.H5bidirectional pass transistor
LONG.V6OUT.STARTUP.Q1Q4pass transistor
LONG.H6bidirectional pass transistor
LONG.V7OUT.STARTUP.Q1Q4pass transistor
LONG.H7bidirectional pass transistor
IMUX.STARTUP.SCLKLONG.V0mux
LONG.V1mux
LONG.V2mux
LONG.V3mux
LONG.V4mux
LONG.V5mux
LONG.V6mux
LONG.V7mux
IMUX.STARTUP.GRSTIO.SINGLE.B.W4mux
IO.SINGLE.B.W5mux
IO.SINGLE.B.W6mux
IO.SINGLE.B.W7mux
LONG.V4mux
LONG.V5mux
LONG.V6mux
LONG.V7mux
IMUX.STARTUP.GTSIO.SINGLE.B.W0mux
IO.SINGLE.B.W1mux
IO.SINGLE.B.W2mux
IO.SINGLE.B.W3mux
LONG.V0mux
LONG.V1mux
LONG.V2mux
LONG.V3mux
IMUX.BUFGGNDmux
IO.SINGLE.B.W0mux
IO.SINGLE.B.W1mux
IO.SINGLE.B.W2mux
IO.SINGLE.B.W3mux
LONG.H4mux
LONG.H5mux
LONG.H6mux
LONG.H7mux
OUT.CLKIOBmux

Bel BUFG

xc5200 CNR.BR bel BUFG
PinDirectionWires
IinputIMUX.BUFG
OoutputGLOBAL.BR

Bel CLKIOB

xc5200 CNR.BR bel CLKIOB
PinDirectionWires
OUToutputOUT.CLKIOB

Bel STARTUP

xc5200 CNR.BR bel STARTUP
PinDirectionWires
CLKinputIMUX.STARTUP.SCLK
DONEINoutputOUT.STARTUP.DONEIN
GRinputIMUX.STARTUP.GRST
GTSinputIMUX.STARTUP.GTS
Q1Q4outputOUT.STARTUP.Q1Q4
Q2outputOUT.STARTUP.Q2
Q3outputOUT.STARTUP.Q3

Bel wires

xc5200 CNR.BR bel wires
WirePins
GLOBAL.BRBUFG.O
OUT.CLKIOBCLKIOB.OUT
OUT.STARTUP.DONEINSTARTUP.DONEIN
OUT.STARTUP.Q1Q4STARTUP.Q1Q4
OUT.STARTUP.Q2STARTUP.Q2
OUT.STARTUP.Q3STARTUP.Q3
IMUX.STARTUP.SCLKSTARTUP.CLK
IMUX.STARTUP.GRSTSTARTUP.GR
IMUX.STARTUP.GTSSTARTUP.GTS
IMUX.BUFGBUFG.I

Bitstream

xc5200 CNR.BR bittile 0
BitFrame
6 5 4 3 2 1 0
27 ~INT:PASS.IO.SINGLE.B.W7.OUT.STARTUP.Q1Q4 ~INT:PASS.IO.SINGLE.B.W6.OUT.STARTUP.Q1Q4 INT:MUX.IMUX.STARTUP.GTS[0] ~INT:BIPASS.LONG.H7.LONG.V7 - INT:MUX.IMUX.STARTUP.SCLK[2] ~MISC:TCTEST
26 ~INT:PASS.LONG.V7.OUT.STARTUP.Q1Q4 ~INT:PASS.LONG.V6.OUT.STARTUP.Q1Q4 INT:MUX.IMUX.STARTUP.GTS[1] ~INT:BIPASS.LONG.H6.LONG.V6 - INT:MUX.IMUX.STARTUP.SCLK[1] STARTUP:STARTUP_CLK[0]
25 ~INT:PASS.IO.SINGLE.B.W5.OUT.STARTUP.Q2 ~INT:PASS.IO.SINGLE.B.W4.OUT.STARTUP.Q2 INT:MUX.IMUX.STARTUP.GTS[2] - - INT:MUX.IMUX.STARTUP.SCLK[0] ~STARTUP:ENABLE.GR
24 ~INT:PASS.LONG.V5.OUT.STARTUP.Q2 ~INT:PASS.LONG.V4.OUT.STARTUP.Q2 INT:MUX.IMUX.STARTUP.GRST[0] ~INT:BIPASS.LONG.H5.LONG.V5 - - STARTUP:DONE_ACTIVE[0]
23 ~INT:PASS.IO.SINGLE.B.W3.OUT.STARTUP.Q3 ~INT:PASS.IO.SINGLE.B.W2.OUT.STARTUP.Q3 INT:MUX.IMUX.STARTUP.GRST[1] - - INT:MUX.IMUX.BUFG[0] STARTUP:DONE_ACTIVE[1]
22 ~INT:PASS.LONG.V3.OUT.STARTUP.Q3 ~INT:PASS.LONG.V2.OUT.STARTUP.Q3 INT:MUX.IMUX.STARTUP.GRST[2] ~INT:BIPASS.LONG.H4.LONG.V4 - INT:MUX.IMUX.BUFG[1] ~STARTUP:INV.GTS
21 ~INT:PASS.IO.SINGLE.B.W1.OUT.STARTUP.DONEIN ~INT:PASS.IO.SINGLE.B.W0.OUT.STARTUP.DONEIN - - - INT:MUX.IMUX.BUFG[2] ~STARTUP:ENABLE.GTS
20 ~INT:PASS.LONG.V1.OUT.STARTUP.DONEIN ~INT:PASS.LONG.V0.OUT.STARTUP.DONEIN - ~INT:BIPASS.LONG.H3.LONG.V3 - INT:MUX.IMUX.BUFG[3] ~STARTUP:INV.GR
19 OSC:OSC1[1] OSC:OSC2[1] OSC:CMUX[0] - - INT:MUX.IMUX.BUFG[4] STARTUP:GSR_INACTIVE[1]
18 OSC:OSC1[0] OSC:OSC2[0] OSC:OSC2[2] ~INT:BIPASS.LONG.H2.LONG.V2 - STARTUP:OUTPUTS_ACTIVE[0] STARTUP:GSR_INACTIVE[0]
17 - - - - - ~STARTUP:SYNC_TO_DONE STARTUP:OUTPUTS_ACTIVE[1]
16 - - - ~INT:BIPASS.LONG.H1.LONG.V1 - INT:MUX.IMUX.BUFG[6] PROG:PULL[0]
15 - - - - - INT:MUX.IMUX.BUFG[7] DONE:PULL[0]
14 - - - ~INT:BIPASS.LONG.H0.LONG.V0 - INT:MUX.IMUX.BUFG[8] INT:MUX.IMUX.BUFG[5]
13 - - - - - - -
12 - - - - - - -
11 - - - - - - -
10 - - - - - - -
9 - - - - - - -
8 - - - - - - -
7 - - - - - - -
6 - - - - - - -
5 - - - - - - -
4 - - - - - - -
3 - - - - - - -
2 - - - - - - STARTUP:CONFIG_RATE[0]
1 - - - - - - STARTUP:CONFIG_RATE[1]
0 - - - - - - STARTUP:CRC
DONE:PULL 0.0.15
PROG:PULL 0.0.16
PULLNONE 0
PULLUP 1
INT:BIPASS.LONG.H0.LONG.V0 0.3.14
INT:BIPASS.LONG.H1.LONG.V1 0.3.16
INT:BIPASS.LONG.H2.LONG.V2 0.3.18
INT:BIPASS.LONG.H3.LONG.V3 0.3.20
INT:BIPASS.LONG.H4.LONG.V4 0.3.22
INT:BIPASS.LONG.H5.LONG.V5 0.3.24
INT:BIPASS.LONG.H6.LONG.V6 0.3.26
INT:BIPASS.LONG.H7.LONG.V7 0.3.27
INT:PASS.IO.SINGLE.B.W0.OUT.STARTUP.DONEIN 0.5.21
INT:PASS.IO.SINGLE.B.W1.OUT.STARTUP.DONEIN 0.6.21
INT:PASS.IO.SINGLE.B.W2.OUT.STARTUP.Q3 0.5.23
INT:PASS.IO.SINGLE.B.W3.OUT.STARTUP.Q3 0.6.23
INT:PASS.IO.SINGLE.B.W4.OUT.STARTUP.Q2 0.5.25
INT:PASS.IO.SINGLE.B.W5.OUT.STARTUP.Q2 0.6.25
INT:PASS.IO.SINGLE.B.W6.OUT.STARTUP.Q1Q4 0.5.27
INT:PASS.IO.SINGLE.B.W7.OUT.STARTUP.Q1Q4 0.6.27
INT:PASS.LONG.V0.OUT.STARTUP.DONEIN 0.5.20
INT:PASS.LONG.V1.OUT.STARTUP.DONEIN 0.6.20
INT:PASS.LONG.V2.OUT.STARTUP.Q3 0.5.22
INT:PASS.LONG.V3.OUT.STARTUP.Q3 0.6.22
INT:PASS.LONG.V4.OUT.STARTUP.Q2 0.5.24
INT:PASS.LONG.V5.OUT.STARTUP.Q2 0.6.24
INT:PASS.LONG.V6.OUT.STARTUP.Q1Q4 0.5.26
INT:PASS.LONG.V7.OUT.STARTUP.Q1Q4 0.6.26
MISC:TCTEST 0.0.27
STARTUP:ENABLE.GR 0.0.25
STARTUP:ENABLE.GTS 0.0.21
STARTUP:INV.GR 0.0.20
STARTUP:INV.GTS 0.0.22
STARTUP:SYNC_TO_DONE 0.1.17
inverted ~[0]
INT:MUX.IMUX.BUFG 0.1.14 0.1.15 0.1.16 0.0.14 0.1.19 0.1.20 0.1.21 0.1.22 0.1.23
IO.SINGLE.B.W0 0 1 1 1 1 1 1 1 1
IO.SINGLE.B.W1 1 0 1 1 1 1 1 1 1
IO.SINGLE.B.W2 1 1 0 1 1 1 1 1 1
IO.SINGLE.B.W3 1 1 1 0 1 1 1 1 1
LONG.H4 1 1 1 1 0 1 1 1 1
LONG.H5 1 1 1 1 1 0 1 1 1
LONG.H6 1 1 1 1 1 1 0 1 1
LONG.H7 1 1 1 1 1 1 1 0 1
OUT.CLKIOB 1 1 1 1 1 1 1 1 0
GND 1 1 1 1 1 1 1 1 1
INT:MUX.IMUX.STARTUP.GRST 0.4.22 0.4.23 0.4.24
IO.SINGLE.B.W4 0 0 0
IO.SINGLE.B.W5 0 0 1
IO.SINGLE.B.W6 0 1 0
IO.SINGLE.B.W7 0 1 1
LONG.V4 1 0 0
LONG.V5 1 0 1
LONG.V6 1 1 0
LONG.V7 1 1 1
INT:MUX.IMUX.STARTUP.GTS 0.4.25 0.4.26 0.4.27
LONG.V3 0 0 0
IO.SINGLE.B.W3 0 0 1
LONG.V1 0 1 0
IO.SINGLE.B.W1 0 1 1
LONG.V2 1 0 0
IO.SINGLE.B.W2 1 0 1
LONG.V0 1 1 0
IO.SINGLE.B.W0 1 1 1
INT:MUX.IMUX.STARTUP.SCLK 0.1.27 0.1.26 0.1.25
LONG.V0 0 0 0
LONG.V1 0 0 1
LONG.V2 0 1 0
LONG.V3 0 1 1
LONG.V4 1 0 0
LONG.V5 1 0 1
LONG.V6 1 1 0
LONG.V7 1 1 1
OSC:CMUX 0.4.19
CCLK 0
USERCLK 1
OSC:OSC1 0.6.19 0.6.18
D8 0 0
D4 0 1
D6 1 0
D2 1 1
OSC:OSC2 0.4.18 0.5.19 0.5.18
D7 0 0 0
D3 0 0 1
D5 0 1 0
D1 0 1 1
D16 1 0 0
D12 1 0 1
D14 1 1 0
D10 1 1 1
STARTUP:CONFIG_RATE 0.0.1 0.0.2
SLOW 0 0
MED 0 1
FAST 1 0
STARTUP:CRC 0.0.0
non-inverted [0]
STARTUP:DONE_ACTIVE 0.0.23 0.0.24
Q1Q4 0 0
Q2 0 1
Q3 1 0
Q0 1 1
STARTUP:GSR_INACTIVE 0.0.19 0.0.18
DONE_IN 0 0
Q3 0 1
Q1Q4 1 0
Q2 1 1
STARTUP:OUTPUTS_ACTIVE 0.0.17 0.1.18
DONE_IN 0 0
Q3 0 1
Q2 1 0
Q1Q4 1 1
STARTUP:STARTUP_CLK 0.0.26
USERCLK 0
CCLK 1

Tile CNR.TL

Cells: 1

Switchbox INT

xc5200 CNR.TL switchbox INT
DestinationSourceKind
IO.SINGLE.T.E0OUT.BSCAN.DRCKpass transistor
OUT.BSCAN.SEL2pass transistor
IO.SINGLE.T.E1OUT.BSCAN.DRCKpass transistor
OUT.BSCAN.SEL2pass transistor
IO.SINGLE.T.E2OUT.BSCAN.SEL1pass transistor
OUT.BSCAN.SHIFTpass transistor
IO.SINGLE.T.E3OUT.BSCAN.SEL1pass transistor
OUT.BSCAN.SHIFTpass transistor
IO.SINGLE.T.E4OUT.BSCAN.UPDATEpass transistor
IO.SINGLE.T.E5OUT.BSCAN.UPDATEpass transistor
IO.SINGLE.T.E6OUT.BSCAN.IDLEpass transistor
OUT.BSCAN.RESETpass transistor
IO.SINGLE.T.E7OUT.BSCAN.IDLEpass transistor
OUT.BSCAN.RESETpass transistor
LONG.H0LONG.V0bidirectional pass transistor
LONG.H1LONG.V1bidirectional pass transistor
LONG.H2LONG.V2bidirectional pass transistor
LONG.H3LONG.V3bidirectional pass transistor
LONG.H4LONG.V4bidirectional pass transistor
LONG.H5LONG.V5bidirectional pass transistor
LONG.H6LONG.V6bidirectional pass transistor
LONG.H7LONG.V7bidirectional pass transistor
LONG.V0OUT.BSCAN.DRCKpass transistor
OUT.BSCAN.SEL2pass transistor
LONG.H0bidirectional pass transistor
LONG.V1OUT.BSCAN.DRCKpass transistor
OUT.BSCAN.SEL2pass transistor
LONG.H1bidirectional pass transistor
LONG.V2OUT.BSCAN.SEL1pass transistor
OUT.BSCAN.SHIFTpass transistor
LONG.H2bidirectional pass transistor
LONG.V3OUT.BSCAN.SEL1pass transistor
OUT.BSCAN.SHIFTpass transistor
LONG.H3bidirectional pass transistor
LONG.V4OUT.BSCAN.UPDATEpass transistor
LONG.H4bidirectional pass transistor
LONG.V5OUT.BSCAN.UPDATEpass transistor
LONG.H5bidirectional pass transistor
LONG.V6OUT.BSCAN.IDLEpass transistor
OUT.BSCAN.RESETpass transistor
LONG.H6bidirectional pass transistor
LONG.V7OUT.BSCAN.IDLEpass transistor
OUT.BSCAN.RESETpass transistor
LONG.H7bidirectional pass transistor
IMUX.BSCAN.TDO1IO.SINGLE.T.E6mux
IO.SINGLE.T.E7mux
LONG.V6mux
LONG.V7mux
IMUX.BSCAN.TDO2IO.SINGLE.T.E4mux
IO.SINGLE.T.E5mux
LONG.V4mux
LONG.V5mux
IMUX.BUFGGNDmux
IO.SINGLE.T.E0mux
IO.SINGLE.T.E1mux
IO.SINGLE.T.E2mux
IO.SINGLE.T.E3mux
LONG.H4mux
LONG.H5mux
LONG.H6mux
LONG.H7mux
OUT.CLKIOBmux

Bel BUFG

xc5200 CNR.TL bel BUFG
PinDirectionWires
IinputIMUX.BUFG
OoutputGLOBAL.TL

Bel CLKIOB

xc5200 CNR.TL bel CLKIOB
PinDirectionWires
OUToutputOUT.CLKIOB

Bel BSCAN

xc5200 CNR.TL bel BSCAN
PinDirectionWires
DRCKoutputOUT.BSCAN.DRCK
IDLEoutputOUT.BSCAN.IDLE
RESEToutputOUT.BSCAN.RESET
SEL1outputOUT.BSCAN.SEL1
SEL2outputOUT.BSCAN.SEL2
SHIFToutputOUT.BSCAN.SHIFT
TDO1inputIMUX.BSCAN.TDO1
TDO2inputIMUX.BSCAN.TDO2
UPDATEoutputOUT.BSCAN.UPDATE

Bel wires

xc5200 CNR.TL bel wires
WirePins
GLOBAL.TLBUFG.O
OUT.CLKIOBCLKIOB.OUT
OUT.BSCAN.DRCKBSCAN.DRCK
OUT.BSCAN.IDLEBSCAN.IDLE
OUT.BSCAN.RESETBSCAN.RESET
OUT.BSCAN.SEL1BSCAN.SEL1
OUT.BSCAN.SEL2BSCAN.SEL2
OUT.BSCAN.SHIFTBSCAN.SHIFT
OUT.BSCAN.UPDATEBSCAN.UPDATE
IMUX.BSCAN.TDO1BSCAN.TDO1
IMUX.BSCAN.TDO2BSCAN.TDO2
IMUX.BUFGBUFG.I

Bitstream

xc5200 CNR.TL bittile 0
BitFrame
5 4 3 2 1 0
15 INT:MUX.IMUX.BUFG[5] - ~MISC:BS_READBACK - - -
14 - - - - - -
13 INT:MUX.IMUX.BUFG[6] - ~INT:BIPASS.LONG.H0.LONG.V0 - - -
12 INT:MUX.IMUX.BUFG[7] - - - - -
11 INT:MUX.IMUX.BUFG[8] - ~INT:BIPASS.LONG.H1.LONG.V1 - - -
10 MISC:INPUT[0] - - - - -
9 ~MISC:BS_RECONFIG - ~INT:BIPASS.LONG.H2.LONG.V2 ~INT:PASS.LONG.V2.OUT.BSCAN.SEL1 - ~BSCAN:ENABLE
8 INT:MUX.IMUX.BUFG[1] - - ~INT:PASS.LONG.V2.OUT.BSCAN.SHIFT ~INT:PASS.LONG.V0.OUT.BSCAN.SEL2 ~INT:PASS.LONG.V0.OUT.BSCAN.DRCK
7 INT:MUX.IMUX.BUFG[2] - ~INT:BIPASS.LONG.H3.LONG.V3 ~INT:PASS.LONG.V3.OUT.BSCAN.SHIFT ~INT:PASS.IO.SINGLE.T.E0.OUT.BSCAN.DRCK ~INT:PASS.IO.SINGLE.T.E0.OUT.BSCAN.SEL2
6 INT:MUX.IMUX.BUFG[3] - - ~INT:PASS.LONG.V3.OUT.BSCAN.SEL1 ~INT:PASS.IO.SINGLE.T.E1.OUT.BSCAN.SEL2 ~INT:PASS.IO.SINGLE.T.E1.OUT.BSCAN.DRCK
5 INT:MUX.IMUX.BUFG[4] - ~INT:BIPASS.LONG.H4.LONG.V4 ~INT:PASS.LONG.V4.OUT.BSCAN.UPDATE ~INT:PASS.LONG.V1.OUT.BSCAN.DRCK ~INT:PASS.LONG.V1.OUT.BSCAN.SEL2
4 INT:MUX.IMUX.BUFG[0] - - ~INT:PASS.LONG.V5.OUT.BSCAN.UPDATE ~INT:PASS.IO.SINGLE.T.E2.OUT.BSCAN.SHIFT ~INT:PASS.IO.SINGLE.T.E2.OUT.BSCAN.SEL1
3 INT:MUX.IMUX.BSCAN.TDO2[1] - ~INT:BIPASS.LONG.H5.LONG.V5 ~INT:PASS.LONG.V6.OUT.BSCAN.IDLE ~INT:PASS.IO.SINGLE.T.E3.OUT.BSCAN.SEL1 ~INT:PASS.IO.SINGLE.T.E3.OUT.BSCAN.SHIFT
2 INT:MUX.IMUX.BSCAN.TDO2[0] - - ~INT:PASS.LONG.V6.OUT.BSCAN.RESET ~INT:PASS.IO.SINGLE.T.E4.OUT.BSCAN.UPDATE ~INT:PASS.IO.SINGLE.T.E5.OUT.BSCAN.UPDATE
1 INT:MUX.IMUX.BSCAN.TDO1[1] - ~INT:BIPASS.LONG.H6.LONG.V6 ~INT:PASS.LONG.V7.OUT.BSCAN.RESET ~INT:PASS.IO.SINGLE.T.E6.OUT.BSCAN.RESET ~INT:PASS.IO.SINGLE.T.E6.OUT.BSCAN.IDLE
0 INT:MUX.IMUX.BSCAN.TDO1[0] - ~INT:BIPASS.LONG.H7.LONG.V7 ~INT:PASS.LONG.V7.OUT.BSCAN.IDLE ~INT:PASS.IO.SINGLE.T.E7.OUT.BSCAN.IDLE ~INT:PASS.IO.SINGLE.T.E7.OUT.BSCAN.RESET
BSCAN:ENABLE 0.0.9
INT:BIPASS.LONG.H0.LONG.V0 0.3.13
INT:BIPASS.LONG.H1.LONG.V1 0.3.11
INT:BIPASS.LONG.H2.LONG.V2 0.3.9
INT:BIPASS.LONG.H3.LONG.V3 0.3.7
INT:BIPASS.LONG.H4.LONG.V4 0.3.5
INT:BIPASS.LONG.H5.LONG.V5 0.3.3
INT:BIPASS.LONG.H6.LONG.V6 0.3.1
INT:BIPASS.LONG.H7.LONG.V7 0.3.0
INT:PASS.IO.SINGLE.T.E0.OUT.BSCAN.DRCK 0.1.7
INT:PASS.IO.SINGLE.T.E0.OUT.BSCAN.SEL2 0.0.7
INT:PASS.IO.SINGLE.T.E1.OUT.BSCAN.DRCK 0.0.6
INT:PASS.IO.SINGLE.T.E1.OUT.BSCAN.SEL2 0.1.6
INT:PASS.IO.SINGLE.T.E2.OUT.BSCAN.SEL1 0.0.4
INT:PASS.IO.SINGLE.T.E2.OUT.BSCAN.SHIFT 0.1.4
INT:PASS.IO.SINGLE.T.E3.OUT.BSCAN.SEL1 0.1.3
INT:PASS.IO.SINGLE.T.E3.OUT.BSCAN.SHIFT 0.0.3
INT:PASS.IO.SINGLE.T.E4.OUT.BSCAN.UPDATE 0.1.2
INT:PASS.IO.SINGLE.T.E5.OUT.BSCAN.UPDATE 0.0.2
INT:PASS.IO.SINGLE.T.E6.OUT.BSCAN.IDLE 0.0.1
INT:PASS.IO.SINGLE.T.E6.OUT.BSCAN.RESET 0.1.1
INT:PASS.IO.SINGLE.T.E7.OUT.BSCAN.IDLE 0.1.0
INT:PASS.IO.SINGLE.T.E7.OUT.BSCAN.RESET 0.0.0
INT:PASS.LONG.V0.OUT.BSCAN.DRCK 0.0.8
INT:PASS.LONG.V0.OUT.BSCAN.SEL2 0.1.8
INT:PASS.LONG.V1.OUT.BSCAN.DRCK 0.1.5
INT:PASS.LONG.V1.OUT.BSCAN.SEL2 0.0.5
INT:PASS.LONG.V2.OUT.BSCAN.SEL1 0.2.9
INT:PASS.LONG.V2.OUT.BSCAN.SHIFT 0.2.8
INT:PASS.LONG.V3.OUT.BSCAN.SEL1 0.2.6
INT:PASS.LONG.V3.OUT.BSCAN.SHIFT 0.2.7
INT:PASS.LONG.V4.OUT.BSCAN.UPDATE 0.2.5
INT:PASS.LONG.V5.OUT.BSCAN.UPDATE 0.2.4
INT:PASS.LONG.V6.OUT.BSCAN.IDLE 0.2.3
INT:PASS.LONG.V6.OUT.BSCAN.RESET 0.2.2
INT:PASS.LONG.V7.OUT.BSCAN.IDLE 0.2.0
INT:PASS.LONG.V7.OUT.BSCAN.RESET 0.2.1
MISC:BS_READBACK 0.3.15
MISC:BS_RECONFIG 0.5.9
inverted ~[0]
INT:MUX.IMUX.BSCAN.TDO1 0.5.1 0.5.0
IO.SINGLE.T.E7 0 0
IO.SINGLE.T.E6 0 1
LONG.V7 1 0
LONG.V6 1 1
INT:MUX.IMUX.BSCAN.TDO2 0.5.3 0.5.2
IO.SINGLE.T.E5 0 0
IO.SINGLE.T.E4 0 1
LONG.V5 1 0
LONG.V4 1 1
INT:MUX.IMUX.BUFG 0.5.11 0.5.12 0.5.13 0.5.15 0.5.5 0.5.6 0.5.7 0.5.8 0.5.4
IO.SINGLE.T.E0 0 1 1 1 1 1 1 1 1
IO.SINGLE.T.E1 1 0 1 1 1 1 1 1 1
IO.SINGLE.T.E2 1 1 0 1 1 1 1 1 1
IO.SINGLE.T.E3 1 1 1 0 1 1 1 1 1
LONG.H4 1 1 1 1 0 1 1 1 1
LONG.H5 1 1 1 1 1 0 1 1 1
LONG.H6 1 1 1 1 1 1 0 1 1
LONG.H7 1 1 1 1 1 1 1 0 1
OUT.CLKIOB 1 1 1 1 1 1 1 1 0
GND 1 1 1 1 1 1 1 1 1
MISC:INPUT 0.5.10
CMOS 0
TTL 1

Tile CNR.TR

Cells: 1

Switchbox INT

xc5200 CNR.TR switchbox INT
DestinationSourceKind
IO.SINGLE.R.S2OUT.BSUPDpass transistor
IO.SINGLE.R.S3OUT.BSUPDpass transistor
IO.SINGLE.R.S4OUT.OSC.OSC1pass transistor
IO.SINGLE.R.S5OUT.OSC.OSC1pass transistor
IO.SINGLE.R.S6OUT.OSC.OSC2pass transistor
IO.SINGLE.R.S7OUT.OSC.OSC2pass transistor
LONG.H0LONG.V0bidirectional pass transistor
LONG.H1LONG.V1bidirectional pass transistor
LONG.H2OUT.BSUPDpass transistor
LONG.V2bidirectional pass transistor
LONG.H3OUT.BSUPDpass transistor
LONG.V3bidirectional pass transistor
LONG.H4OUT.OSC.OSC1pass transistor
LONG.V4bidirectional pass transistor
LONG.H5OUT.OSC.OSC1pass transistor
LONG.V5bidirectional pass transistor
LONG.H6OUT.OSC.OSC2pass transistor
LONG.V6bidirectional pass transistor
LONG.H7OUT.OSC.OSC2pass transistor
LONG.V7bidirectional pass transistor
LONG.V0LONG.H0bidirectional pass transistor
LONG.V1LONG.H1bidirectional pass transistor
LONG.V2LONG.H2bidirectional pass transistor
LONG.V3LONG.H3bidirectional pass transistor
LONG.V4LONG.H4bidirectional pass transistor
LONG.V5LONG.H5bidirectional pass transistor
LONG.V6LONG.H6bidirectional pass transistor
LONG.V7LONG.H7bidirectional pass transistor
IMUX.OSC.OCLKGNDmux
IO.SINGLE.R.S0mux
IO.SINGLE.R.S1mux
IO.SINGLE.R.S2mux
IO.SINGLE.R.S3mux
LONG.H0mux
LONG.H1mux
LONG.H2mux
LONG.H3mux
IMUX.BYPOSC.PUMPIO.SINGLE.R.S4mux
IO.SINGLE.R.S5mux
LONG.H4mux
LONG.V3mux
IMUX.BUFGGNDmux
IO.SINGLE.R.S0mux
IO.SINGLE.R.S1mux
IO.SINGLE.R.S2mux
IO.SINGLE.R.S3mux
LONG.V4mux
LONG.V5mux
LONG.V6mux
LONG.V7mux
OUT.CLKIOBmux

Bel BUFG

xc5200 CNR.TR bel BUFG
PinDirectionWires
IinputIMUX.BUFG
OoutputGLOBAL.TR

Bel CLKIOB

xc5200 CNR.TR bel CLKIOB
PinDirectionWires
OUToutputOUT.CLKIOB

Bel OSC

xc5200 CNR.TR bel OSC
PinDirectionWires
CinputIMUX.OSC.OCLK
OSC1outputOUT.OSC.OSC1
OSC2outputOUT.OSC.OSC2

Bel BYPOSC

xc5200 CNR.TR bel BYPOSC
PinDirectionWires
IinputIMUX.BYPOSC.PUMP

Bel BSUPD

xc5200 CNR.TR bel BSUPD
PinDirectionWires
OoutputOUT.BSUPD

Bel wires

xc5200 CNR.TR bel wires
WirePins
GLOBAL.TRBUFG.O
OUT.CLKIOBCLKIOB.OUT
OUT.BSUPDBSUPD.O
OUT.OSC.OSC1OSC.OSC1
OUT.OSC.OSC2OSC.OSC2
IMUX.OSC.OCLKOSC.C
IMUX.BYPOSC.PUMPBYPOSC.I
IMUX.BUFGBUFG.I

Bitstream

xc5200 CNR.TR bittile 0
BitFrame
6 5 4 3 2 1 0
11 - - - INT:MUX.IMUX.BUFG[7] - INT:MUX.IMUX.BUFG[6] ~MISC:TLC
10 - - - INT:MUX.IMUX.BUFG[8] - INT:MUX.IMUX.BUFG[5] ~MISC:TAC
9 - - - - - - -
8 - - - - - - -
7 - - ~INT:PASS.IO.SINGLE.R.S2.OUT.BSUPD - - ~INT:BIPASS.LONG.H0.LONG.V0 -
6 INT:MUX.IMUX.OSC.OCLK[0] - ~INT:PASS.IO.SINGLE.R.S3.OUT.BSUPD - - ~INT:BIPASS.LONG.H1.LONG.V1 -
5 INT:MUX.IMUX.OSC.OCLK[4] INT:MUX.IMUX.BYPOSC.PUMP[2] ~INT:PASS.LONG.H2.OUT.BSUPD - - ~INT:BIPASS.LONG.H2.LONG.V2 -
4 INT:MUX.IMUX.OSC.OCLK[3] INT:MUX.IMUX.BYPOSC.PUMP[3] ~INT:PASS.LONG.H3.OUT.BSUPD INT:MUX.IMUX.BUFG[0] - ~INT:BIPASS.LONG.H3.LONG.V3 -
3 INT:MUX.IMUX.OSC.OCLK[2] INT:MUX.IMUX.BYPOSC.PUMP[0] ~INT:PASS.LONG.H4.OUT.OSC.OSC1 INT:MUX.IMUX.BUFG[4] - ~INT:BIPASS.LONG.H4.LONG.V4 -
2 INT:MUX.IMUX.OSC.OCLK[1] INT:MUX.IMUX.BYPOSC.PUMP[1] ~INT:PASS.LONG.H5.OUT.OSC.OSC1 INT:MUX.IMUX.BUFG[3] - ~INT:BIPASS.LONG.H5.LONG.V5 -
1 ~INT:PASS.IO.SINGLE.R.S4.OUT.OSC.OSC1 ~INT:PASS.IO.SINGLE.R.S5.OUT.OSC.OSC1 ~INT:PASS.LONG.H6.OUT.OSC.OSC2 INT:MUX.IMUX.BUFG[2] - ~INT:BIPASS.LONG.H6.LONG.V6 -
0 ~INT:PASS.IO.SINGLE.R.S7.OUT.OSC.OSC2 ~INT:PASS.IO.SINGLE.R.S6.OUT.OSC.OSC2 ~INT:PASS.LONG.H7.OUT.OSC.OSC2 INT:MUX.IMUX.BUFG[1] - ~INT:BIPASS.LONG.H7.LONG.V7 -
INT:BIPASS.LONG.H0.LONG.V0 0.1.7
INT:BIPASS.LONG.H1.LONG.V1 0.1.6
INT:BIPASS.LONG.H2.LONG.V2 0.1.5
INT:BIPASS.LONG.H3.LONG.V3 0.1.4
INT:BIPASS.LONG.H4.LONG.V4 0.1.3
INT:BIPASS.LONG.H5.LONG.V5 0.1.2
INT:BIPASS.LONG.H6.LONG.V6 0.1.1
INT:BIPASS.LONG.H7.LONG.V7 0.1.0
INT:PASS.IO.SINGLE.R.S2.OUT.BSUPD 0.4.7
INT:PASS.IO.SINGLE.R.S3.OUT.BSUPD 0.4.6
INT:PASS.IO.SINGLE.R.S4.OUT.OSC.OSC1 0.6.1
INT:PASS.IO.SINGLE.R.S5.OUT.OSC.OSC1 0.5.1
INT:PASS.IO.SINGLE.R.S6.OUT.OSC.OSC2 0.5.0
INT:PASS.IO.SINGLE.R.S7.OUT.OSC.OSC2 0.6.0
INT:PASS.LONG.H2.OUT.BSUPD 0.4.5
INT:PASS.LONG.H3.OUT.BSUPD 0.4.4
INT:PASS.LONG.H4.OUT.OSC.OSC1 0.4.3
INT:PASS.LONG.H5.OUT.OSC.OSC1 0.4.2
INT:PASS.LONG.H6.OUT.OSC.OSC2 0.4.1
INT:PASS.LONG.H7.OUT.OSC.OSC2 0.4.0
MISC:TAC 0.0.10
MISC:TLC 0.0.11
inverted ~[0]
INT:MUX.IMUX.BUFG 0.3.10 0.3.11 0.1.11 0.1.10 0.3.3 0.3.2 0.3.1 0.3.0 0.3.4
IO.SINGLE.R.S0 0 1 1 1 1 1 1 1 1
IO.SINGLE.R.S1 1 0 1 1 1 1 1 1 1
IO.SINGLE.R.S2 1 1 0 1 1 1 1 1 1
IO.SINGLE.R.S3 1 1 1 0 1 1 1 1 1
LONG.V4 1 1 1 1 0 1 1 1 1
LONG.V5 1 1 1 1 1 0 1 1 1
LONG.V6 1 1 1 1 1 1 0 1 1
LONG.V7 1 1 1 1 1 1 1 0 1
OUT.CLKIOB 1 1 1 1 1 1 1 1 0
GND 1 1 1 1 1 1 1 1 1
INT:MUX.IMUX.BYPOSC.PUMP 0.5.4 0.5.5 0.5.2 0.5.3
IO.SINGLE.R.S4 0 1 1 1
IO.SINGLE.R.S5 1 0 1 1
LONG.H4 1 1 0 1
LONG.V3 1 1 1 0
NONE 1 1 1 1
INT:MUX.IMUX.OSC.OCLK 0.6.5 0.6.4 0.6.3 0.6.2 0.6.6
LONG.H0 0 1 1 1 0
IO.SINGLE.R.S0 0 1 1 1 1
LONG.H1 1 0 1 1 0
IO.SINGLE.R.S1 1 0 1 1 1
LONG.H2 1 1 0 1 0
IO.SINGLE.R.S2 1 1 0 1 1
LONG.H3 1 1 1 0 0
IO.SINGLE.R.S3 1 1 1 0 1
GND 1 1 1 1 1