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Corners

Tile CNR_SW

Cells: 1

Switchbox INT

xc5200 CNR_SW switchbox INT pass gates
DestinationSourceBit
SINGLE_IO_W_N[0]OUT_RDBK_RIP!MAIN[1][16]
SINGLE_IO_W_N[1]OUT_RDBK_RIP!MAIN[0][16]
SINGLE_IO_W_N[2]OUT_RDBK_RIP!MAIN[1][20]
SINGLE_IO_W_N[3]OUT_RDBK_RIP!MAIN[0][20]
SINGLE_IO_W_N[4]OUT_RDBK_DATA!MAIN[1][23]
SINGLE_IO_W_N[5]OUT_RDBK_DATA!MAIN[0][24]
SINGLE_IO_W_N[6]OUT_RDBK_DATA!MAIN[1][26]
SINGLE_IO_W_N[7]OUT_RDBK_DATA!MAIN[0][27]
LONG_H[0]OUT_RDBK_RIP!MAIN[0][14]
LONG_H[1]OUT_RDBK_RIP!MAIN[1][15]
LONG_H[2]OUT_RDBK_RIP!MAIN[0][18]
LONG_H[3]OUT_RDBK_RIP!MAIN[1][18]
LONG_H[4]OUT_RDBK_DATA!MAIN[0][22]
LONG_H[5]OUT_RDBK_DATA!MAIN[1][22]
LONG_H[6]OUT_RDBK_DATA!MAIN[0][26]
LONG_H[7]OUT_RDBK_DATA!MAIN[1][24]
xc5200 CNR_SW switchbox INT bidirectional pass gates
Side ASide BBit
LONG_H[0]LONG_V[0]!MAIN[1][11]
LONG_H[1]LONG_V[1]!MAIN[1][13]
LONG_H[2]LONG_V[2]!MAIN[1][14]
LONG_H[3]LONG_V[3]!MAIN[0][10]
LONG_H[4]LONG_V[4]!MAIN[0][11]
LONG_H[5]LONG_V[5]!MAIN[1][9]
LONG_H[6]LONG_V[6]!MAIN[0][8]
LONG_H[7]LONG_V[7]!MAIN[1][8]
xc5200 CNR_SW switchbox INT muxes IMUX_RDBK_RCLK
BitsDestination
MAIN[2][24]MAIN[2][25]MAIN[2][23]IMUX_RDBK_RCLK
Source
000LONG_H[1]
001SINGLE_IO_W_N[1]
010LONG_H[0]
011SINGLE_IO_W_N[0]
100LONG_H[3]
101SINGLE_IO_W_N[2]
110LONG_H[2]
111SINGLE_IO_W_N[3]
xc5200 CNR_SW switchbox INT muxes IMUX_RDBK_TRIG
BitsDestination
MAIN[2][27]MAIN[1][27]MAIN[2][26]IMUX_RDBK_TRIG
Source
000LONG_H[4]
001SINGLE_IO_W_N[4]
010LONG_H[5]
011SINGLE_IO_W_N[5]
100LONG_H[6]
101SINGLE_IO_W_N[6]
110LONG_H[7]
111TIE_0
xc5200 CNR_SW switchbox INT muxes IMUX_BUFG
BitsDestination
MAIN[5][27]MAIN[5][26]MAIN[6][26]MAIN[6][27]MAIN[2][18]MAIN[2][17]MAIN[2][16]MAIN[2][15]MAIN[2][14]IMUX_BUFG
Source
011111111SINGLE_IO_W_N[0]
101111111SINGLE_IO_W_N[1]
110111111SINGLE_IO_W_N[2]
111011111SINGLE_IO_W_N[3]
111101111LONG_V[4]
111110111LONG_V[5]
111111011LONG_V[6]
111111101LONG_V[7]
111111110OUT_CLKIOB
111111111TIE_0

Switchbox BUFG

xc5200 CNR_SW switchbox BUFG permanent buffers
DestinationSource
GCLK_SWIMUX_BUFG

Bels CLKIOB

xc5200 CNR_SW bel CLKIOB pins
PinDirectionCLKIOB
OUToutOUT_CLKIOB

Bels RDBK

xc5200 CNR_SW bel RDBK pins
PinDirectionRDBK
CKinIMUX_RDBK_RCLK
TRIGinIMUX_RDBK_TRIG
DATAoutOUT_RDBK_DATA
RIPoutOUT_RDBK_RIP
xc5200 CNR_SW bel RDBK attribute bits
AttributeRDBK
MUX_CLK[enum: RDBK_MUX_CLK]
READ_ABORT!MAIN[1][4]
READ_CAPTURE!MAIN[2][4]
xc5200 CNR_SW enum RDBK_MUX_CLK
RDBK.MUX_CLKMAIN[1][6]
CCLK1
RDBK0

Bels MISC_SW

xc5200 CNR_SW bel MISC_SW pins
PinDirectionMISC_SW
xc5200 CNR_SW bel MISC_SW attribute bits
AttributeMISC_SW
SCAN_TEST[enum: SCAN_TEST]
xc5200 CNR_SW enum SCAN_TEST
MISC_SW.SCAN_TESTMAIN[0][4]MAIN[2][2]MAIN[2][3]
DISABLE111
ENABLE011
ENLL101
NE7110

Bel wires

xc5200 CNR_SW bel wires
WirePins
OUT_CLKIOBCLKIOB.OUT
OUT_RDBK_RIPRDBK.RIP
OUT_RDBK_DATARDBK.DATA
IMUX_RDBK_RCLKRDBK.CK
IMUX_RDBK_TRIGRDBK.TRIG

Bitstream

xc5200 CNR_SW rect MAIN
BitFrame
F6 F5 F4 F3 F2 F1 F0
B27 INT: mux IMUX_BUFG bit 5 INT: mux IMUX_BUFG bit 8 - - INT: mux IMUX_RDBK_TRIG bit 2 INT: mux IMUX_RDBK_TRIG bit 1 INT: !pass SINGLE_IO_W_N[7] ← OUT_RDBK_DATA
B26 INT: mux IMUX_BUFG bit 6 INT: mux IMUX_BUFG bit 7 - - INT: mux IMUX_RDBK_TRIG bit 0 INT: !pass SINGLE_IO_W_N[6] ← OUT_RDBK_DATA INT: !pass LONG_H[6] ← OUT_RDBK_DATA
B25 - - - - INT: mux IMUX_RDBK_RCLK bit 1 - -
B24 - - - - INT: mux IMUX_RDBK_RCLK bit 2 INT: !pass LONG_H[7] ← OUT_RDBK_DATA INT: !pass SINGLE_IO_W_N[5] ← OUT_RDBK_DATA
B23 - - - - INT: mux IMUX_RDBK_RCLK bit 0 INT: !pass SINGLE_IO_W_N[4] ← OUT_RDBK_DATA -
B22 - - - - - INT: !pass LONG_H[5] ← OUT_RDBK_DATA INT: !pass LONG_H[4] ← OUT_RDBK_DATA
B21 - - - - - - -
B20 - - - - - INT: !pass SINGLE_IO_W_N[2] ← OUT_RDBK_RIP INT: !pass SINGLE_IO_W_N[3] ← OUT_RDBK_RIP
B19 - - - - - - -
B18 - - - - INT: mux IMUX_BUFG bit 4 INT: !pass LONG_H[3] ← OUT_RDBK_RIP INT: !pass LONG_H[2] ← OUT_RDBK_RIP
B17 - - - - INT: mux IMUX_BUFG bit 3 - -
B16 - - - - INT: mux IMUX_BUFG bit 2 INT: !pass SINGLE_IO_W_N[0] ← OUT_RDBK_RIP INT: !pass SINGLE_IO_W_N[1] ← OUT_RDBK_RIP
B15 - - - - INT: mux IMUX_BUFG bit 1 INT: !pass LONG_H[1] ← OUT_RDBK_RIP -
B14 - - - - INT: mux IMUX_BUFG bit 0 INT: !bipass LONG_H[2] = LONG_V[2] INT: !pass LONG_H[0] ← OUT_RDBK_RIP
B13 - - - - - INT: !bipass LONG_H[1] = LONG_V[1] -
B12 - - - - - - -
B11 - - - - - INT: !bipass LONG_H[0] = LONG_V[0] INT: !bipass LONG_H[4] = LONG_V[4]
B10 - - - - - - INT: !bipass LONG_H[3] = LONG_V[3]
B9 - - - - - INT: !bipass LONG_H[5] = LONG_V[5] -
B8 - - - - - INT: !bipass LONG_H[7] = LONG_V[7] INT: !bipass LONG_H[6] = LONG_V[6]
B7 - - - - - - -
B6 - - - - - RDBK: MUX_CLK bit 0 -
B5 - - - - - - -
B4 - - - - RDBK: ! READ_CAPTURE RDBK: ! READ_ABORT MISC_SW: SCAN_TEST bit 2
B3 - - - - MISC_SW: SCAN_TEST bit 0 - -
B2 - - - - MISC_SW: SCAN_TEST bit 1 - -
B1 - - - - - - -
B0 - - - - - - -

Tile CNR_SE

Cells: 1

Switchbox INT

xc5200 CNR_SE switchbox INT pass gates
DestinationSourceBit
SINGLE_IO_S_W[0]OUT_STARTUP_DONEIN!MAIN[5][21]
SINGLE_IO_S_W[1]OUT_STARTUP_DONEIN!MAIN[6][21]
SINGLE_IO_S_W[2]OUT_STARTUP_Q3!MAIN[5][23]
SINGLE_IO_S_W[3]OUT_STARTUP_Q3!MAIN[6][23]
SINGLE_IO_S_W[4]OUT_STARTUP_Q2!MAIN[5][25]
SINGLE_IO_S_W[5]OUT_STARTUP_Q2!MAIN[6][25]
SINGLE_IO_S_W[6]OUT_STARTUP_Q1Q4!MAIN[5][27]
SINGLE_IO_S_W[7]OUT_STARTUP_Q1Q4!MAIN[6][27]
LONG_V[0]OUT_STARTUP_DONEIN!MAIN[5][20]
LONG_V[1]OUT_STARTUP_DONEIN!MAIN[6][20]
LONG_V[2]OUT_STARTUP_Q3!MAIN[5][22]
LONG_V[3]OUT_STARTUP_Q3!MAIN[6][22]
LONG_V[4]OUT_STARTUP_Q2!MAIN[5][24]
LONG_V[5]OUT_STARTUP_Q2!MAIN[6][24]
LONG_V[6]OUT_STARTUP_Q1Q4!MAIN[5][26]
LONG_V[7]OUT_STARTUP_Q1Q4!MAIN[6][26]
xc5200 CNR_SE switchbox INT bidirectional pass gates
Side ASide BBit
LONG_H[0]LONG_V[0]!MAIN[3][14]
LONG_H[1]LONG_V[1]!MAIN[3][16]
LONG_H[2]LONG_V[2]!MAIN[3][18]
LONG_H[3]LONG_V[3]!MAIN[3][20]
LONG_H[4]LONG_V[4]!MAIN[3][22]
LONG_H[5]LONG_V[5]!MAIN[3][24]
LONG_H[6]LONG_V[6]!MAIN[3][26]
LONG_H[7]LONG_V[7]!MAIN[3][27]
xc5200 CNR_SE switchbox INT muxes IMUX_STARTUP_SCLK
BitsDestination
MAIN[1][27]MAIN[1][26]MAIN[1][25]IMUX_STARTUP_SCLK
Source
000LONG_V[0]
001LONG_V[1]
010LONG_V[2]
011LONG_V[3]
100LONG_V[4]
101LONG_V[5]
110LONG_V[6]
111LONG_V[7]
xc5200 CNR_SE switchbox INT muxes IMUX_STARTUP_GRST
BitsDestination
MAIN[4][22]MAIN[4][23]MAIN[4][24]IMUX_STARTUP_GRST
Source
000SINGLE_IO_S_W[4]
001SINGLE_IO_S_W[5]
010SINGLE_IO_S_W[6]
011SINGLE_IO_S_W[7]
100LONG_V[4]
101LONG_V[5]
110LONG_V[6]
111LONG_V[7]
xc5200 CNR_SE switchbox INT muxes IMUX_STARTUP_GTS
BitsDestination
MAIN[4][25]MAIN[4][26]MAIN[4][27]IMUX_STARTUP_GTS
Source
000LONG_V[3]
001SINGLE_IO_S_W[3]
010LONG_V[1]
011SINGLE_IO_S_W[1]
100LONG_V[2]
101SINGLE_IO_S_W[2]
110LONG_V[0]
111SINGLE_IO_S_W[0]
xc5200 CNR_SE switchbox INT muxes IMUX_BUFG
BitsDestination
MAIN[1][14]MAIN[1][15]MAIN[1][16]MAIN[0][14]MAIN[1][19]MAIN[1][20]MAIN[1][21]MAIN[1][22]MAIN[1][23]IMUX_BUFG
Source
011111111SINGLE_IO_S_W[0]
101111111SINGLE_IO_S_W[1]
110111111SINGLE_IO_S_W[2]
111011111SINGLE_IO_S_W[3]
111101111LONG_H[4]
111110111LONG_H[5]
111111011LONG_H[6]
111111101LONG_H[7]
111111110OUT_CLKIOB
111111111TIE_0

Switchbox BUFG

xc5200 CNR_SE switchbox BUFG permanent buffers
DestinationSource
GCLK_SEIMUX_BUFG

Bels CLKIOB

xc5200 CNR_SE bel CLKIOB pins
PinDirectionCLKIOB
OUToutOUT_CLKIOB

Bels STARTUP

xc5200 CNR_SE bel STARTUP pins
PinDirectionSTARTUP
CLKinIMUX_STARTUP_SCLK
GRinIMUX_STARTUP_GRST invert by !MAIN[0][20]
GTSinIMUX_STARTUP_GTS invert by !MAIN[0][22]
DONEINoutOUT_STARTUP_DONEIN
Q1Q4outOUT_STARTUP_Q1Q4
Q2outOUT_STARTUP_Q2
Q3outOUT_STARTUP_Q3
xc5200 CNR_SE bel STARTUP attribute bits
AttributeSTARTUP
GR_ENABLE!MAIN[0][25]
GTS_ENABLE!MAIN[0][21]
CONFIG_RATE[enum: CONFIG_RATE]
CRCMAIN[0][0]
DONE_TIMING[enum: DONE_TIMING]
GTS_TIMING[enum: GTS_GSR_TIMING]
GSR_TIMING[enum: GTS_GSR_TIMING]
SYNC_TO_DONE!MAIN[1][17]
MUX_CLK[enum: STARTUP_MUX_CLK]
xc5200 CNR_SE enum CONFIG_RATE
STARTUP.CONFIG_RATEMAIN[0][1]MAIN[0][2]
SLOW00
MED01
FAST10
xc5200 CNR_SE enum DONE_TIMING
STARTUP.DONE_TIMINGMAIN[0][23]MAIN[0][24]
Q011
Q1Q400
Q201
Q310
xc5200 CNR_SE enum GTS_GSR_TIMING
STARTUP.GTS_TIMINGMAIN[1][18]MAIN[0][17]
Q1Q411
Q201
Q310
DONE_IN00
xc5200 CNR_SE enum GTS_GSR_TIMING
STARTUP.GSR_TIMINGMAIN[0][18]MAIN[0][19]
Q1Q401
Q211
Q310
DONE_IN00
xc5200 CNR_SE enum STARTUP_MUX_CLK
STARTUP.MUX_CLKMAIN[0][26]
CCLK1
USERCLK0

Bels OSC_SE

xc5200 CNR_SE bel OSC_SE pins
PinDirectionOSC_SE
xc5200 CNR_SE bel OSC_SE attribute bits
AttributeOSC_SE
OSC1_DIV[enum: OSC1_DIV]
OSC2_DIV[enum: OSC2_DIV]
MUX_CLK[enum: OSC_MUX_CLK]
xc5200 CNR_SE enum OSC1_DIV
OSC_SE.OSC1_DIVMAIN[6][19]MAIN[6][18]
D211
D401
D610
D800
xc5200 CNR_SE enum OSC2_DIV
OSC_SE.OSC2_DIVMAIN[4][18]MAIN[5][19]MAIN[5][18]
D1011
D3001
D5010
D7000
D10111
D12101
D14110
D16100
xc5200 CNR_SE enum OSC_MUX_CLK
OSC_SE.MUX_CLKMAIN[4][19]
CCLK0
USERCLK1

Bels MISC_SE

xc5200 CNR_SE bel MISC_SE pins
PinDirectionMISC_SE
xc5200 CNR_SE bel MISC_SE attribute bits
AttributeMISC_SE
DONE_PULLUPMAIN[0][15]
PROG_PULLUPMAIN[0][16]
TCTEST!MAIN[0][27]

Bel wires

xc5200 CNR_SE bel wires
WirePins
OUT_CLKIOBCLKIOB.OUT
OUT_STARTUP_DONEINSTARTUP.DONEIN
OUT_STARTUP_Q1Q4STARTUP.Q1Q4
OUT_STARTUP_Q2STARTUP.Q2
OUT_STARTUP_Q3STARTUP.Q3
IMUX_STARTUP_SCLKSTARTUP.CLK
IMUX_STARTUP_GRSTSTARTUP.GR
IMUX_STARTUP_GTSSTARTUP.GTS

Bitstream

xc5200 CNR_SE rect MAIN
BitFrame
F7 F6 F5 F4 F3 F2 F1 F0
B27 - INT: !pass SINGLE_IO_S_W[7] ← OUT_STARTUP_Q1Q4 INT: !pass SINGLE_IO_S_W[6] ← OUT_STARTUP_Q1Q4 INT: mux IMUX_STARTUP_GTS bit 0 INT: !bipass LONG_H[7] = LONG_V[7] - INT: mux IMUX_STARTUP_SCLK bit 2 MISC_SE: ! TCTEST
B26 - INT: !pass LONG_V[7] ← OUT_STARTUP_Q1Q4 INT: !pass LONG_V[6] ← OUT_STARTUP_Q1Q4 INT: mux IMUX_STARTUP_GTS bit 1 INT: !bipass LONG_H[6] = LONG_V[6] - INT: mux IMUX_STARTUP_SCLK bit 1 STARTUP: MUX_CLK bit 0
B25 - INT: !pass SINGLE_IO_S_W[5] ← OUT_STARTUP_Q2 INT: !pass SINGLE_IO_S_W[4] ← OUT_STARTUP_Q2 INT: mux IMUX_STARTUP_GTS bit 2 - - INT: mux IMUX_STARTUP_SCLK bit 0 STARTUP: ! GR_ENABLE
B24 - INT: !pass LONG_V[5] ← OUT_STARTUP_Q2 INT: !pass LONG_V[4] ← OUT_STARTUP_Q2 INT: mux IMUX_STARTUP_GRST bit 0 INT: !bipass LONG_H[5] = LONG_V[5] - - STARTUP: DONE_TIMING bit 0
B23 - INT: !pass SINGLE_IO_S_W[3] ← OUT_STARTUP_Q3 INT: !pass SINGLE_IO_S_W[2] ← OUT_STARTUP_Q3 INT: mux IMUX_STARTUP_GRST bit 1 - - INT: mux IMUX_BUFG bit 0 STARTUP: DONE_TIMING bit 1
B22 - INT: !pass LONG_V[3] ← OUT_STARTUP_Q3 INT: !pass LONG_V[2] ← OUT_STARTUP_Q3 INT: mux IMUX_STARTUP_GRST bit 2 INT: !bipass LONG_H[4] = LONG_V[4] - INT: mux IMUX_BUFG bit 1 STARTUP: !invert GTS
B21 - INT: !pass SINGLE_IO_S_W[1] ← OUT_STARTUP_DONEIN INT: !pass SINGLE_IO_S_W[0] ← OUT_STARTUP_DONEIN - - - INT: mux IMUX_BUFG bit 2 STARTUP: ! GTS_ENABLE
B20 - INT: !pass LONG_V[1] ← OUT_STARTUP_DONEIN INT: !pass LONG_V[0] ← OUT_STARTUP_DONEIN - INT: !bipass LONG_H[3] = LONG_V[3] - INT: mux IMUX_BUFG bit 3 STARTUP: !invert GR
B19 - OSC_SE: OSC1_DIV bit 1 OSC_SE: OSC2_DIV bit 1 OSC_SE: MUX_CLK bit 0 - - INT: mux IMUX_BUFG bit 4 STARTUP: GSR_TIMING bit 0
B18 - OSC_SE: OSC1_DIV bit 0 OSC_SE: OSC2_DIV bit 0 OSC_SE: OSC2_DIV bit 2 INT: !bipass LONG_H[2] = LONG_V[2] - STARTUP: GTS_TIMING bit 1 STARTUP: GSR_TIMING bit 1
B17 - - - - - - STARTUP: ! SYNC_TO_DONE STARTUP: GTS_TIMING bit 0
B16 - - - - INT: !bipass LONG_H[1] = LONG_V[1] - INT: mux IMUX_BUFG bit 6 MISC_SE: PROG_PULLUP
B15 - - - - - - INT: mux IMUX_BUFG bit 7 MISC_SE: DONE_PULLUP
B14 - - - - INT: !bipass LONG_H[0] = LONG_V[0] - INT: mux IMUX_BUFG bit 8 INT: mux IMUX_BUFG bit 5
B13 - - - - - - - -
B12 - - - - - - - -
B11 - - - - - - - -
B10 - - - - - - - -
B9 - - - - - - - -
B8 - - - - - - - -
B7 - - - - - - - -
B6 - - - - - - - -
B5 - - - - - - - -
B4 - - - - - - - -
B3 - - - - - - - -
B2 - - - - - - - STARTUP: CONFIG_RATE bit 0
B1 - - - - - - - STARTUP: CONFIG_RATE bit 1
B0 - - - - - - - STARTUP: CRC

Tile CNR_NW

Cells: 1

Switchbox INT

xc5200 CNR_NW switchbox INT pass gates
DestinationSourceBit
SINGLE_IO_N_E[0]OUT_BSCAN_DRCK!MAIN[1][7]
SINGLE_IO_N_E[0]OUT_BSCAN_SEL2!MAIN[0][7]
SINGLE_IO_N_E[1]OUT_BSCAN_DRCK!MAIN[0][6]
SINGLE_IO_N_E[1]OUT_BSCAN_SEL2!MAIN[1][6]
SINGLE_IO_N_E[2]OUT_BSCAN_SEL1!MAIN[0][4]
SINGLE_IO_N_E[2]OUT_BSCAN_SHIFT!MAIN[1][4]
SINGLE_IO_N_E[3]OUT_BSCAN_SEL1!MAIN[1][3]
SINGLE_IO_N_E[3]OUT_BSCAN_SHIFT!MAIN[0][3]
SINGLE_IO_N_E[4]OUT_BSCAN_UPDATE!MAIN[1][2]
SINGLE_IO_N_E[5]OUT_BSCAN_UPDATE!MAIN[0][2]
SINGLE_IO_N_E[6]OUT_BSCAN_IDLE!MAIN[0][1]
SINGLE_IO_N_E[6]OUT_BSCAN_RESET!MAIN[1][1]
SINGLE_IO_N_E[7]OUT_BSCAN_IDLE!MAIN[1][0]
SINGLE_IO_N_E[7]OUT_BSCAN_RESET!MAIN[0][0]
LONG_V[0]OUT_BSCAN_DRCK!MAIN[0][8]
LONG_V[0]OUT_BSCAN_SEL2!MAIN[1][8]
LONG_V[1]OUT_BSCAN_DRCK!MAIN[1][5]
LONG_V[1]OUT_BSCAN_SEL2!MAIN[0][5]
LONG_V[2]OUT_BSCAN_SEL1!MAIN[2][9]
LONG_V[2]OUT_BSCAN_SHIFT!MAIN[2][8]
LONG_V[3]OUT_BSCAN_SEL1!MAIN[2][6]
LONG_V[3]OUT_BSCAN_SHIFT!MAIN[2][7]
LONG_V[4]OUT_BSCAN_UPDATE!MAIN[2][5]
LONG_V[5]OUT_BSCAN_UPDATE!MAIN[2][4]
LONG_V[6]OUT_BSCAN_IDLE!MAIN[2][3]
LONG_V[6]OUT_BSCAN_RESET!MAIN[2][2]
LONG_V[7]OUT_BSCAN_IDLE!MAIN[2][0]
LONG_V[7]OUT_BSCAN_RESET!MAIN[2][1]
xc5200 CNR_NW switchbox INT bidirectional pass gates
Side ASide BBit
LONG_H[0]LONG_V[0]!MAIN[3][13]
LONG_H[1]LONG_V[1]!MAIN[3][11]
LONG_H[2]LONG_V[2]!MAIN[3][9]
LONG_H[3]LONG_V[3]!MAIN[3][7]
LONG_H[4]LONG_V[4]!MAIN[3][5]
LONG_H[5]LONG_V[5]!MAIN[3][3]
LONG_H[6]LONG_V[6]!MAIN[3][1]
LONG_H[7]LONG_V[7]!MAIN[3][0]
xc5200 CNR_NW switchbox INT muxes IMUX_BSCAN_TDO1
BitsDestination
MAIN[5][1]MAIN[5][0]IMUX_BSCAN_TDO1
Source
00SINGLE_IO_N_E[7]
01SINGLE_IO_N_E[6]
10LONG_V[7]
11LONG_V[6]
xc5200 CNR_NW switchbox INT muxes IMUX_BSCAN_TDO2
BitsDestination
MAIN[5][3]MAIN[5][2]IMUX_BSCAN_TDO2
Source
00SINGLE_IO_N_E[5]
01SINGLE_IO_N_E[4]
10LONG_V[5]
11LONG_V[4]
xc5200 CNR_NW switchbox INT muxes IMUX_BUFG
BitsDestination
MAIN[5][11]MAIN[5][12]MAIN[5][13]MAIN[5][15]MAIN[5][5]MAIN[5][6]MAIN[5][7]MAIN[5][8]MAIN[5][4]IMUX_BUFG
Source
011111111SINGLE_IO_N_E[0]
101111111SINGLE_IO_N_E[1]
110111111SINGLE_IO_N_E[2]
111011111SINGLE_IO_N_E[3]
111101111LONG_H[4]
111110111LONG_H[5]
111111011LONG_H[6]
111111101LONG_H[7]
111111110OUT_CLKIOB
111111111TIE_0

Switchbox BUFG

xc5200 CNR_NW switchbox BUFG permanent buffers
DestinationSource
GCLK_NWIMUX_BUFG

Bels CLKIOB

xc5200 CNR_NW bel CLKIOB pins
PinDirectionCLKIOB
OUToutOUT_CLKIOB

Bels BSCAN

xc5200 CNR_NW bel BSCAN pins
PinDirectionBSCAN
TDO1inIMUX_BSCAN_TDO1
TDO2inIMUX_BSCAN_TDO2
DRCKoutOUT_BSCAN_DRCK
IDLEoutOUT_BSCAN_IDLE
RESEToutOUT_BSCAN_RESET
SEL1outOUT_BSCAN_SEL1
SEL2outOUT_BSCAN_SEL2
SHIFToutOUT_BSCAN_SHIFT
UPDATEoutOUT_BSCAN_UPDATE
xc5200 CNR_NW bel BSCAN attribute bits
AttributeBSCAN
ENABLE!MAIN[0][9]
RECONFIG!MAIN[5][9]
READBACK!MAIN[3][15]

Bels MISC_NW

xc5200 CNR_NW bel MISC_NW pins
PinDirectionMISC_NW
xc5200 CNR_NW bel MISC_NW attribute bits
AttributeMISC_NW
IO_INPUT_MODE[enum: IO_INPUT_MODE]
xc5200 CNR_NW enum IO_INPUT_MODE
MISC_NW.IO_INPUT_MODEMAIN[5][10]
TTL1
CMOS0

Bel wires

xc5200 CNR_NW bel wires
WirePins
OUT_CLKIOBCLKIOB.OUT
OUT_BSCAN_DRCKBSCAN.DRCK
OUT_BSCAN_IDLEBSCAN.IDLE
OUT_BSCAN_RESETBSCAN.RESET
OUT_BSCAN_SEL1BSCAN.SEL1
OUT_BSCAN_SEL2BSCAN.SEL2
OUT_BSCAN_SHIFTBSCAN.SHIFT
OUT_BSCAN_UPDATEBSCAN.UPDATE
IMUX_BSCAN_TDO1BSCAN.TDO1
IMUX_BSCAN_TDO2BSCAN.TDO2

Bitstream

xc5200 CNR_NW rect MAIN
BitFrame
F6 F5 F4 F3 F2 F1 F0
B27 - - - - - - -
B26 - - - - - - -
B25 - - - - - - -
B24 - - - - - - -
B23 - - - - - - -
B22 - - - - - - -
B21 - - - - - - -
B20 - - - - - - -
B19 - - - - - - -
B18 - - - - - - -
B17 - - - - - - -
B16 - - - - - - -
B15 - INT: mux IMUX_BUFG bit 5 - BSCAN: ! READBACK - - -
B14 - - - - - - -
B13 - INT: mux IMUX_BUFG bit 6 - INT: !bipass LONG_H[0] = LONG_V[0] - - -
B12 - INT: mux IMUX_BUFG bit 7 - - - - -
B11 - INT: mux IMUX_BUFG bit 8 - INT: !bipass LONG_H[1] = LONG_V[1] - - -
B10 - MISC_NW: IO_INPUT_MODE bit 0 - - - - -
B9 - BSCAN: ! RECONFIG - INT: !bipass LONG_H[2] = LONG_V[2] INT: !pass LONG_V[2] ← OUT_BSCAN_SEL1 - BSCAN: ! ENABLE
B8 - INT: mux IMUX_BUFG bit 1 - - INT: !pass LONG_V[2] ← OUT_BSCAN_SHIFT INT: !pass LONG_V[0] ← OUT_BSCAN_SEL2 INT: !pass LONG_V[0] ← OUT_BSCAN_DRCK
B7 - INT: mux IMUX_BUFG bit 2 - INT: !bipass LONG_H[3] = LONG_V[3] INT: !pass LONG_V[3] ← OUT_BSCAN_SHIFT INT: !pass SINGLE_IO_N_E[0] ← OUT_BSCAN_DRCK INT: !pass SINGLE_IO_N_E[0] ← OUT_BSCAN_SEL2
B6 - INT: mux IMUX_BUFG bit 3 - - INT: !pass LONG_V[3] ← OUT_BSCAN_SEL1 INT: !pass SINGLE_IO_N_E[1] ← OUT_BSCAN_SEL2 INT: !pass SINGLE_IO_N_E[1] ← OUT_BSCAN_DRCK
B5 - INT: mux IMUX_BUFG bit 4 - INT: !bipass LONG_H[4] = LONG_V[4] INT: !pass LONG_V[4] ← OUT_BSCAN_UPDATE INT: !pass LONG_V[1] ← OUT_BSCAN_DRCK INT: !pass LONG_V[1] ← OUT_BSCAN_SEL2
B4 - INT: mux IMUX_BUFG bit 0 - - INT: !pass LONG_V[5] ← OUT_BSCAN_UPDATE INT: !pass SINGLE_IO_N_E[2] ← OUT_BSCAN_SHIFT INT: !pass SINGLE_IO_N_E[2] ← OUT_BSCAN_SEL1
B3 - INT: mux IMUX_BSCAN_TDO2 bit 1 - INT: !bipass LONG_H[5] = LONG_V[5] INT: !pass LONG_V[6] ← OUT_BSCAN_IDLE INT: !pass SINGLE_IO_N_E[3] ← OUT_BSCAN_SEL1 INT: !pass SINGLE_IO_N_E[3] ← OUT_BSCAN_SHIFT
B2 - INT: mux IMUX_BSCAN_TDO2 bit 0 - - INT: !pass LONG_V[6] ← OUT_BSCAN_RESET INT: !pass SINGLE_IO_N_E[4] ← OUT_BSCAN_UPDATE INT: !pass SINGLE_IO_N_E[5] ← OUT_BSCAN_UPDATE
B1 - INT: mux IMUX_BSCAN_TDO1 bit 1 - INT: !bipass LONG_H[6] = LONG_V[6] INT: !pass LONG_V[7] ← OUT_BSCAN_RESET INT: !pass SINGLE_IO_N_E[6] ← OUT_BSCAN_RESET INT: !pass SINGLE_IO_N_E[6] ← OUT_BSCAN_IDLE
B0 - INT: mux IMUX_BSCAN_TDO1 bit 0 - INT: !bipass LONG_H[7] = LONG_V[7] INT: !pass LONG_V[7] ← OUT_BSCAN_IDLE INT: !pass SINGLE_IO_N_E[7] ← OUT_BSCAN_IDLE INT: !pass SINGLE_IO_N_E[7] ← OUT_BSCAN_RESET

Tile CNR_NE

Cells: 1

Switchbox INT

xc5200 CNR_NE switchbox INT pass gates
DestinationSourceBit
SINGLE_IO_E_S[2]OUT_BSUPD!MAIN[4][7]
SINGLE_IO_E_S[3]OUT_BSUPD!MAIN[4][6]
SINGLE_IO_E_S[4]OUT_OSC_OSC1!MAIN[6][1]
SINGLE_IO_E_S[5]OUT_OSC_OSC1!MAIN[5][1]
SINGLE_IO_E_S[6]OUT_OSC_OSC2!MAIN[5][0]
SINGLE_IO_E_S[7]OUT_OSC_OSC2!MAIN[6][0]
LONG_H[2]OUT_BSUPD!MAIN[4][5]
LONG_H[3]OUT_BSUPD!MAIN[4][4]
LONG_H[4]OUT_OSC_OSC1!MAIN[4][3]
LONG_H[5]OUT_OSC_OSC1!MAIN[4][2]
LONG_H[6]OUT_OSC_OSC2!MAIN[4][1]
LONG_H[7]OUT_OSC_OSC2!MAIN[4][0]
xc5200 CNR_NE switchbox INT bidirectional pass gates
Side ASide BBit
LONG_H[0]LONG_V[0]!MAIN[1][7]
LONG_H[1]LONG_V[1]!MAIN[1][6]
LONG_H[2]LONG_V[2]!MAIN[1][5]
LONG_H[3]LONG_V[3]!MAIN[1][4]
LONG_H[4]LONG_V[4]!MAIN[1][3]
LONG_H[5]LONG_V[5]!MAIN[1][2]
LONG_H[6]LONG_V[6]!MAIN[1][1]
LONG_H[7]LONG_V[7]!MAIN[1][0]
xc5200 CNR_NE switchbox INT muxes IMUX_OSC_OCLK
BitsDestination
MAIN[6][5]MAIN[6][4]MAIN[6][3]MAIN[6][2]MAIN[6][6]IMUX_OSC_OCLK
Source
01110LONG_H[0]
01111SINGLE_IO_E_S[0]
10110LONG_H[1]
10111SINGLE_IO_E_S[1]
11010LONG_H[2]
11011SINGLE_IO_E_S[2]
11100LONG_H[3]
11101SINGLE_IO_E_S[3]
11111TIE_0
xc5200 CNR_NE switchbox INT muxes IMUX_BYPOSC_PUMP
BitsDestination
MAIN[5][4]MAIN[5][5]MAIN[5][2]MAIN[5][3]IMUX_BYPOSC_PUMP
Source
0111SINGLE_IO_E_S[4]
1011SINGLE_IO_E_S[5]
1101LONG_H[4]
1110LONG_V[3]
1111off
xc5200 CNR_NE switchbox INT muxes IMUX_BUFG
BitsDestination
MAIN[3][10]MAIN[3][11]MAIN[1][11]MAIN[1][10]MAIN[3][3]MAIN[3][2]MAIN[3][1]MAIN[3][0]MAIN[3][4]IMUX_BUFG
Source
011111111SINGLE_IO_E_S[0]
101111111SINGLE_IO_E_S[1]
110111111SINGLE_IO_E_S[2]
111011111SINGLE_IO_E_S[3]
111101111LONG_V[4]
111110111LONG_V[5]
111111011LONG_V[6]
111111101LONG_V[7]
111111110OUT_CLKIOB
111111111TIE_0

Switchbox BUFG

xc5200 CNR_NE switchbox BUFG permanent buffers
DestinationSource
GCLK_NEIMUX_BUFG

Bels CLKIOB

xc5200 CNR_NE bel CLKIOB pins
PinDirectionCLKIOB
OUToutOUT_CLKIOB

Bels OSC_NE

xc5200 CNR_NE bel OSC_NE pins
PinDirectionOSC_NE
CinIMUX_OSC_OCLK
OSC1outOUT_OSC_OSC1
OSC2outOUT_OSC_OSC2

Bels BYPOSC

xc5200 CNR_NE bel BYPOSC pins
PinDirectionBYPOSC
IinIMUX_BYPOSC_PUMP

Bels BSUPD

xc5200 CNR_NE bel BSUPD pins
PinDirectionBSUPD
OoutOUT_BSUPD

Bels MISC_NE

xc5200 CNR_NE bel MISC_NE pins
PinDirectionMISC_NE
xc5200 CNR_NE bel MISC_NE attribute bits
AttributeMISC_NE
TAC!MAIN[0][10]
TLC!MAIN[0][11]

Bel wires

xc5200 CNR_NE bel wires
WirePins
OUT_CLKIOBCLKIOB.OUT
OUT_BSUPDBSUPD.O
OUT_OSC_OSC1OSC_NE.OSC1
OUT_OSC_OSC2OSC_NE.OSC2
IMUX_OSC_OCLKOSC_NE.C
IMUX_BYPOSC_PUMPBYPOSC.I

Bitstream

xc5200 CNR_NE rect MAIN
BitFrame
F7 F6 F5 F4 F3 F2 F1 F0
B27 - - - - - - - -
B26 - - - - - - - -
B25 - - - - - - - -
B24 - - - - - - - -
B23 - - - - - - - -
B22 - - - - - - - -
B21 - - - - - - - -
B20 - - - - - - - -
B19 - - - - - - - -
B18 - - - - - - - -
B17 - - - - - - - -
B16 - - - - - - - -
B15 - - - - - - - -
B14 - - - - - - - -
B13 - - - - - - - -
B12 - - - - - - - -
B11 - - - - INT: mux IMUX_BUFG bit 7 - INT: mux IMUX_BUFG bit 6 MISC_NE: ! TLC
B10 - - - - INT: mux IMUX_BUFG bit 8 - INT: mux IMUX_BUFG bit 5 MISC_NE: ! TAC
B9 - - - - - - - -
B8 - - - - - - - -
B7 - - - INT: !pass SINGLE_IO_E_S[2] ← OUT_BSUPD - - INT: !bipass LONG_H[0] = LONG_V[0] -
B6 - INT: mux IMUX_OSC_OCLK bit 0 - INT: !pass SINGLE_IO_E_S[3] ← OUT_BSUPD - - INT: !bipass LONG_H[1] = LONG_V[1] -
B5 - INT: mux IMUX_OSC_OCLK bit 4 INT: mux IMUX_BYPOSC_PUMP bit 2 INT: !pass LONG_H[2] ← OUT_BSUPD - - INT: !bipass LONG_H[2] = LONG_V[2] -
B4 - INT: mux IMUX_OSC_OCLK bit 3 INT: mux IMUX_BYPOSC_PUMP bit 3 INT: !pass LONG_H[3] ← OUT_BSUPD INT: mux IMUX_BUFG bit 0 - INT: !bipass LONG_H[3] = LONG_V[3] -
B3 - INT: mux IMUX_OSC_OCLK bit 2 INT: mux IMUX_BYPOSC_PUMP bit 0 INT: !pass LONG_H[4] ← OUT_OSC_OSC1 INT: mux IMUX_BUFG bit 4 - INT: !bipass LONG_H[4] = LONG_V[4] -
B2 - INT: mux IMUX_OSC_OCLK bit 1 INT: mux IMUX_BYPOSC_PUMP bit 1 INT: !pass LONG_H[5] ← OUT_OSC_OSC1 INT: mux IMUX_BUFG bit 3 - INT: !bipass LONG_H[5] = LONG_V[5] -
B1 - INT: !pass SINGLE_IO_E_S[4] ← OUT_OSC_OSC1 INT: !pass SINGLE_IO_E_S[5] ← OUT_OSC_OSC1 INT: !pass LONG_H[6] ← OUT_OSC_OSC2 INT: mux IMUX_BUFG bit 2 - INT: !bipass LONG_H[6] = LONG_V[6] -
B0 - INT: !pass SINGLE_IO_E_S[7] ← OUT_OSC_OSC2 INT: !pass SINGLE_IO_E_S[6] ← OUT_OSC_OSC2 INT: !pass LONG_H[7] ← OUT_OSC_OSC2 INT: mux IMUX_BUFG bit 1 - INT: !bipass LONG_H[7] = LONG_V[7] -