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Block RAM

Tile EBR

Cells: 2

Bel EBR0

xp EBR bel EBR0
PinDirectionWires
ADA0inputTCELL0:IMUX_D7
ADA1inputTCELL0:IMUX_A6
ADA10inputTCELL1:IMUX_D0
ADA11inputTCELL1:IMUX_B1
ADA12inputTCELL1:IMUX_C0
ADA2inputTCELL1:IMUX_A6
ADA3inputTCELL1:IMUX_D7
ADA4inputTCELL1:IMUX_C7
ADA5inputTCELL1:IMUX_B7
ADA6inputTCELL1:IMUX_A7
ADA7inputTCELL1:IMUX_D6
ADA8inputTCELL1:IMUX_C6
ADA9inputTCELL1:IMUX_A1
ADB0inputTCELL0:IMUX_D3
ADB1inputTCELL0:IMUX_C2
ADB10inputTCELL0:IMUX_B6
ADB11inputTCELL0:IMUX_B4
ADB12inputTCELL0:IMUX_A4
ADB2inputTCELL1:IMUX_C3
ADB3inputTCELL1:IMUX_B5
ADB4inputTCELL1:IMUX_A5
ADB5inputTCELL1:IMUX_D3
ADB6inputTCELL1:IMUX_C4
ADB7inputTCELL1:IMUX_B3
ADB8inputTCELL1:IMUX_A3
ADB9inputTCELL0:IMUX_C7
CEAinputTCELL1:IMUX_CE1
CEBinputTCELL0:IMUX_CE1
CLKAinputTCELL1:IMUX_CLK1
CLKBinputTCELL1:IMUX_CLK0
CSA0inputTCELL1:IMUX_M2
CSA1inputTCELL0:IMUX_M4
CSA2inputTCELL0:IMUX_M6
CSB0inputTCELL1:IMUX_M6
CSB1inputTCELL1:IMUX_M4
CSB2inputTCELL0:IMUX_M2
DIA0inputTCELL1:IMUX_B6
DIA1inputTCELL1:IMUX_D5
DIA10inputTCELL1:IMUX_D4
DIA11inputTCELL1:IMUX_B4
DIA12inputTCELL1:IMUX_A4
DIA13inputTCELL0:IMUX_C5
DIA14inputTCELL0:IMUX_A5
DIA15inputTCELL0:IMUX_D4
DIA16inputTCELL0:IMUX_B5
DIA17inputTCELL0:IMUX_C4
DIA2inputTCELL1:IMUX_D2
DIA3inputTCELL1:IMUX_C2
DIA4inputTCELL1:IMUX_A0
DIA5inputTCELL0:IMUX_B7
DIA6inputTCELL0:IMUX_A7
DIA7inputTCELL0:IMUX_D6
DIA8inputTCELL0:IMUX_C6
DIA9inputTCELL1:IMUX_C5
DIB0inputTCELL0:IMUX_C3
DIB1inputTCELL0:IMUX_B3
DIB10inputTCELL1:IMUX_B2
DIB11inputTCELL1:IMUX_D1
DIB12inputTCELL1:IMUX_C1
DIB13inputTCELL0:IMUX_D1
DIB14inputTCELL0:IMUX_C1
DIB15inputTCELL0:IMUX_B1
DIB16inputTCELL0:IMUX_A1
DIB17inputTCELL0:IMUX_D0
DIB2inputTCELL0:IMUX_A3
DIB3inputTCELL0:IMUX_D2
DIB4inputTCELL0:IMUX_B2
DIB5inputTCELL0:IMUX_A2
DIB6inputTCELL0:IMUX_C0
DIB7inputTCELL0:IMUX_B0
DIB8inputTCELL0:IMUX_A0
DIB9inputTCELL1:IMUX_A2
DOA0outputTCELL1:OUT_Q4
DOA1outputTCELL1:OUT_F4
DOA10outputTCELL1:OUT_F7
DOA11outputTCELL1:OUT_Q6
DOA12outputTCELL1:OUT_F6
DOA13outputTCELL0:OUT_Q7
DOA14outputTCELL0:OUT_F7
DOA15outputTCELL0:OUT_Q6
DOA16outputTCELL0:OUT_F6
DOA17outputTCELL0:OUT_Q5
DOA2outputTCELL1:OUT_F5
DOA3outputTCELL1:OUT_Q5
DOA4outputTCELL0:OUT_F5
DOA5outputTCELL0:OUT_Q4
DOA6outputTCELL0:OUT_F4
DOA7outputTCELL0:OUT_OFX3
DOA8outputTCELL0:OUT_Q3
DOA9outputTCELL1:OUT_Q7
DOB0outputTCELL1:OUT_Q1
DOB1outputTCELL1:OUT_F1
DOB10outputTCELL1:OUT_Q3
DOB11outputTCELL1:OUT_Q2
DOB12outputTCELL1:OUT_F2
DOB13outputTCELL0:OUT_F3
DOB14outputTCELL0:OUT_OFX2
DOB15outputTCELL0:OUT_Q2
DOB16outputTCELL0:OUT_F2
DOB17outputTCELL0:OUT_OFX1
DOB2outputTCELL1:OUT_F0
DOB3outputTCELL1:OUT_Q0
DOB4outputTCELL0:OUT_Q1
DOB5outputTCELL0:OUT_F1
DOB6outputTCELL0:OUT_OFX0
DOB7outputTCELL0:OUT_Q0
DOB8outputTCELL0:OUT_F0
DOB9outputTCELL1:OUT_F3
MORCLKAinputTCELL0:IMUX_CLK1
MORCLKBinputTCELL0:IMUX_CLK0
RSTAinputTCELL1:IMUX_LSR3
RSTBinputTCELL0:IMUX_LSR3
WEAinputTCELL1:IMUX_M0
WEBinputTCELL0:IMUX_M0

Bel wires

xp EBR bel wires
WirePins
TCELL0:IMUX_A0EBR0.DIB8
TCELL0:IMUX_A1EBR0.DIB16
TCELL0:IMUX_A2EBR0.DIB5
TCELL0:IMUX_A3EBR0.DIB2
TCELL0:IMUX_A4EBR0.ADB12
TCELL0:IMUX_A5EBR0.DIA14
TCELL0:IMUX_A6EBR0.ADA1
TCELL0:IMUX_A7EBR0.DIA6
TCELL0:IMUX_B0EBR0.DIB7
TCELL0:IMUX_B1EBR0.DIB15
TCELL0:IMUX_B2EBR0.DIB4
TCELL0:IMUX_B3EBR0.DIB1
TCELL0:IMUX_B4EBR0.ADB11
TCELL0:IMUX_B5EBR0.DIA16
TCELL0:IMUX_B6EBR0.ADB10
TCELL0:IMUX_B7EBR0.DIA5
TCELL0:IMUX_C0EBR0.DIB6
TCELL0:IMUX_C1EBR0.DIB14
TCELL0:IMUX_C2EBR0.ADB1
TCELL0:IMUX_C3EBR0.DIB0
TCELL0:IMUX_C4EBR0.DIA17
TCELL0:IMUX_C5EBR0.DIA13
TCELL0:IMUX_C6EBR0.DIA8
TCELL0:IMUX_C7EBR0.ADB9
TCELL0:IMUX_D0EBR0.DIB17
TCELL0:IMUX_D1EBR0.DIB13
TCELL0:IMUX_D2EBR0.DIB3
TCELL0:IMUX_D3EBR0.ADB0
TCELL0:IMUX_D4EBR0.DIA15
TCELL0:IMUX_D6EBR0.DIA7
TCELL0:IMUX_D7EBR0.ADA0
TCELL0:IMUX_M0EBR0.WEB
TCELL0:IMUX_M2EBR0.CSB2
TCELL0:IMUX_M4EBR0.CSA1
TCELL0:IMUX_M6EBR0.CSA2
TCELL0:IMUX_CLK0EBR0.MORCLKB
TCELL0:IMUX_CLK1EBR0.MORCLKA
TCELL0:IMUX_LSR3EBR0.RSTB
TCELL0:IMUX_CE1EBR0.CEB
TCELL0:OUT_F0EBR0.DOB8
TCELL0:OUT_F1EBR0.DOB5
TCELL0:OUT_F2EBR0.DOB16
TCELL0:OUT_F3EBR0.DOB13
TCELL0:OUT_F4EBR0.DOA6
TCELL0:OUT_F5EBR0.DOA4
TCELL0:OUT_F6EBR0.DOA16
TCELL0:OUT_F7EBR0.DOA14
TCELL0:OUT_Q0EBR0.DOB7
TCELL0:OUT_Q1EBR0.DOB4
TCELL0:OUT_Q2EBR0.DOB15
TCELL0:OUT_Q3EBR0.DOA8
TCELL0:OUT_Q4EBR0.DOA5
TCELL0:OUT_Q5EBR0.DOA17
TCELL0:OUT_Q6EBR0.DOA15
TCELL0:OUT_Q7EBR0.DOA13
TCELL0:OUT_OFX0EBR0.DOB6
TCELL0:OUT_OFX1EBR0.DOB17
TCELL0:OUT_OFX2EBR0.DOB14
TCELL0:OUT_OFX3EBR0.DOA7
TCELL1:IMUX_A0EBR0.DIA4
TCELL1:IMUX_A1EBR0.ADA9
TCELL1:IMUX_A2EBR0.DIB9
TCELL1:IMUX_A3EBR0.ADB8
TCELL1:IMUX_A4EBR0.DIA12
TCELL1:IMUX_A5EBR0.ADB4
TCELL1:IMUX_A6EBR0.ADA2
TCELL1:IMUX_A7EBR0.ADA6
TCELL1:IMUX_B1EBR0.ADA11
TCELL1:IMUX_B2EBR0.DIB10
TCELL1:IMUX_B3EBR0.ADB7
TCELL1:IMUX_B4EBR0.DIA11
TCELL1:IMUX_B5EBR0.ADB3
TCELL1:IMUX_B6EBR0.DIA0
TCELL1:IMUX_B7EBR0.ADA5
TCELL1:IMUX_C0EBR0.ADA12
TCELL1:IMUX_C1EBR0.DIB12
TCELL1:IMUX_C2EBR0.DIA3
TCELL1:IMUX_C3EBR0.ADB2
TCELL1:IMUX_C4EBR0.ADB6
TCELL1:IMUX_C5EBR0.DIA9
TCELL1:IMUX_C6EBR0.ADA8
TCELL1:IMUX_C7EBR0.ADA4
TCELL1:IMUX_D0EBR0.ADA10
TCELL1:IMUX_D1EBR0.DIB11
TCELL1:IMUX_D2EBR0.DIA2
TCELL1:IMUX_D3EBR0.ADB5
TCELL1:IMUX_D4EBR0.DIA10
TCELL1:IMUX_D5EBR0.DIA1
TCELL1:IMUX_D6EBR0.ADA7
TCELL1:IMUX_D7EBR0.ADA3
TCELL1:IMUX_M0EBR0.WEA
TCELL1:IMUX_M2EBR0.CSA0
TCELL1:IMUX_M4EBR0.CSB1
TCELL1:IMUX_M6EBR0.CSB0
TCELL1:IMUX_CLK0EBR0.CLKB
TCELL1:IMUX_CLK1EBR0.CLKA
TCELL1:IMUX_LSR3EBR0.RSTA
TCELL1:IMUX_CE1EBR0.CEA
TCELL1:OUT_F0EBR0.DOB2
TCELL1:OUT_F1EBR0.DOB1
TCELL1:OUT_F2EBR0.DOB12
TCELL1:OUT_F3EBR0.DOB9
TCELL1:OUT_F4EBR0.DOA1
TCELL1:OUT_F5EBR0.DOA2
TCELL1:OUT_F6EBR0.DOA12
TCELL1:OUT_F7EBR0.DOA10
TCELL1:OUT_Q0EBR0.DOB3
TCELL1:OUT_Q1EBR0.DOB0
TCELL1:OUT_Q2EBR0.DOB11
TCELL1:OUT_Q3EBR0.DOB10
TCELL1:OUT_Q4EBR0.DOA0
TCELL1:OUT_Q5EBR0.DOA3
TCELL1:OUT_Q6EBR0.DOA11
TCELL1:OUT_Q7EBR0.DOA9