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Clock interconnect

Tile CLK_ROOT_2PLL_A

Cells: 28

Bel DCS_SW0

xp CLK_ROOT_2PLL_A bel DCS_SW0
PinDirectionWires
OUTinputCELL0.PCLK2
SELinputCELL5.IMUX_C5

Bel DCS_SW1

xp CLK_ROOT_2PLL_A bel DCS_SW1
PinDirectionWires
OUTinputCELL0.PCLK3
SELinputCELL4.IMUX_C5

Bel DCS_SE0

xp CLK_ROOT_2PLL_A bel DCS_SE0
PinDirectionWires
OUTinputCELL1.PCLK2
SELinputCELL6.IMUX_C5

Bel DCS_SE1

xp CLK_ROOT_2PLL_A bel DCS_SE1
PinDirectionWires
OUTinputCELL1.PCLK3
SELinputCELL7.IMUX_C5

Bel DCS_NW0

xp CLK_ROOT_2PLL_A bel DCS_NW0
PinDirectionWires
OUTinputCELL2.PCLK2
SELinputCELL5.IMUX_B5

Bel DCS_NW1

xp CLK_ROOT_2PLL_A bel DCS_NW1
PinDirectionWires
OUTinputCELL2.PCLK3
SELinputCELL4.IMUX_B5

Bel DCS_NE0

xp CLK_ROOT_2PLL_A bel DCS_NE0
PinDirectionWires
OUTinputCELL3.PCLK2
SELinputCELL6.IMUX_B5

Bel DCS_NE1

xp CLK_ROOT_2PLL_A bel DCS_NE1
PinDirectionWires
OUTinputCELL3.PCLK3
SELinputCELL7.IMUX_B5

Bel CLK_ROOT

xp CLK_ROOT_2PLL_A bel CLK_ROOT
PinDirectionWires
PCLK0_NEinputCELL3.PCLK0
PCLK0_NWinputCELL2.PCLK0
PCLK0_SEinputCELL1.PCLK0
PCLK0_SWinputCELL0.PCLK0
PCLK1_NEinputCELL3.PCLK1
PCLK1_NWinputCELL2.PCLK1
PCLK1_SEinputCELL1.PCLK1
PCLK1_SWinputCELL0.PCLK1
PCLK_IN_EinputCELL9.IMUX_B5
PCLK_IN_NinputCELL11.IMUX_B5
PCLK_IN_SinputCELL10.IMUX_B5
PCLK_IN_WinputCELL8.IMUX_B5
SCLK0_NEinputCELL3.SCLK0
SCLK0_NWinputCELL2.SCLK0
SCLK0_SEinputCELL1.SCLK0
SCLK0_SWinputCELL0.SCLK0
SCLK1_NEinputCELL3.SCLK1
SCLK1_NWinputCELL2.SCLK1
SCLK1_SEinputCELL1.SCLK1
SCLK1_SWinputCELL0.SCLK1
SCLK2_NEinputCELL3.SCLK2
SCLK2_NWinputCELL2.SCLK2
SCLK2_SEinputCELL1.SCLK2
SCLK2_SWinputCELL0.SCLK2
SCLK3_NEinputCELL3.SCLK3
SCLK3_NWinputCELL2.SCLK3
SCLK3_SEinputCELL1.SCLK3
SCLK3_SWinputCELL0.SCLK3
SCLK_IN_E0inputCELL16.IMUX_B5
SCLK_IN_E1inputCELL17.IMUX_B5
SCLK_IN_E2inputCELL18.IMUX_D5
SCLK_IN_E3inputCELL19.IMUX_B0
SCLK_IN_N0inputCELL24.IMUX_B5
SCLK_IN_N1inputCELL25.IMUX_B5
SCLK_IN_N2inputCELL26.IMUX_D5
SCLK_IN_N3inputCELL27.IMUX_B0
SCLK_IN_S0inputCELL20.IMUX_B5
SCLK_IN_S1inputCELL21.IMUX_B5
SCLK_IN_S2inputCELL22.IMUX_D5
SCLK_IN_S3inputCELL23.IMUX_B0
SCLK_IN_W0inputCELL12.IMUX_B5
SCLK_IN_W1inputCELL13.IMUX_B5
SCLK_IN_W2inputCELL14.IMUX_D5
SCLK_IN_W3inputCELL15.IMUX_B0

Bel wires

xp CLK_ROOT_2PLL_A bel wires
WirePins
CELL0.PCLK0CLK_ROOT.PCLK0_SW
CELL0.PCLK1CLK_ROOT.PCLK1_SW
CELL0.PCLK2DCS_SW0.OUT
CELL0.PCLK3DCS_SW1.OUT
CELL0.SCLK0CLK_ROOT.SCLK0_SW
CELL0.SCLK1CLK_ROOT.SCLK1_SW
CELL0.SCLK2CLK_ROOT.SCLK2_SW
CELL0.SCLK3CLK_ROOT.SCLK3_SW
CELL1.PCLK0CLK_ROOT.PCLK0_SE
CELL1.PCLK1CLK_ROOT.PCLK1_SE
CELL1.PCLK2DCS_SE0.OUT
CELL1.PCLK3DCS_SE1.OUT
CELL1.SCLK0CLK_ROOT.SCLK0_SE
CELL1.SCLK1CLK_ROOT.SCLK1_SE
CELL1.SCLK2CLK_ROOT.SCLK2_SE
CELL1.SCLK3CLK_ROOT.SCLK3_SE
CELL2.PCLK0CLK_ROOT.PCLK0_NW
CELL2.PCLK1CLK_ROOT.PCLK1_NW
CELL2.PCLK2DCS_NW0.OUT
CELL2.PCLK3DCS_NW1.OUT
CELL2.SCLK0CLK_ROOT.SCLK0_NW
CELL2.SCLK1CLK_ROOT.SCLK1_NW
CELL2.SCLK2CLK_ROOT.SCLK2_NW
CELL2.SCLK3CLK_ROOT.SCLK3_NW
CELL3.PCLK0CLK_ROOT.PCLK0_NE
CELL3.PCLK1CLK_ROOT.PCLK1_NE
CELL3.PCLK2DCS_NE0.OUT
CELL3.PCLK3DCS_NE1.OUT
CELL3.SCLK0CLK_ROOT.SCLK0_NE
CELL3.SCLK1CLK_ROOT.SCLK1_NE
CELL3.SCLK2CLK_ROOT.SCLK2_NE
CELL3.SCLK3CLK_ROOT.SCLK3_NE
CELL4.IMUX_B5DCS_NW1.SEL
CELL4.IMUX_C5DCS_SW1.SEL
CELL5.IMUX_B5DCS_NW0.SEL
CELL5.IMUX_C5DCS_SW0.SEL
CELL6.IMUX_B5DCS_NE0.SEL
CELL6.IMUX_C5DCS_SE0.SEL
CELL7.IMUX_B5DCS_NE1.SEL
CELL7.IMUX_C5DCS_SE1.SEL
CELL8.IMUX_B5CLK_ROOT.PCLK_IN_W
CELL9.IMUX_B5CLK_ROOT.PCLK_IN_E
CELL10.IMUX_B5CLK_ROOT.PCLK_IN_S
CELL11.IMUX_B5CLK_ROOT.PCLK_IN_N
CELL12.IMUX_B5CLK_ROOT.SCLK_IN_W0
CELL13.IMUX_B5CLK_ROOT.SCLK_IN_W1
CELL14.IMUX_D5CLK_ROOT.SCLK_IN_W2
CELL15.IMUX_B0CLK_ROOT.SCLK_IN_W3
CELL16.IMUX_B5CLK_ROOT.SCLK_IN_E0
CELL17.IMUX_B5CLK_ROOT.SCLK_IN_E1
CELL18.IMUX_D5CLK_ROOT.SCLK_IN_E2
CELL19.IMUX_B0CLK_ROOT.SCLK_IN_E3
CELL20.IMUX_B5CLK_ROOT.SCLK_IN_S0
CELL21.IMUX_B5CLK_ROOT.SCLK_IN_S1
CELL22.IMUX_D5CLK_ROOT.SCLK_IN_S2
CELL23.IMUX_B0CLK_ROOT.SCLK_IN_S3
CELL24.IMUX_B5CLK_ROOT.SCLK_IN_N0
CELL25.IMUX_B5CLK_ROOT.SCLK_IN_N1
CELL26.IMUX_D5CLK_ROOT.SCLK_IN_N2
CELL27.IMUX_B0CLK_ROOT.SCLK_IN_N3

Tile CLK_ROOT_2PLL_B

Cells: 28

Bel DCS_SW0

xp CLK_ROOT_2PLL_B bel DCS_SW0
PinDirectionWires
OUTinputCELL0.PCLK2
SELinputCELL5.IMUX_C5

Bel DCS_SW1

xp CLK_ROOT_2PLL_B bel DCS_SW1
PinDirectionWires
OUTinputCELL0.PCLK3
SELinputCELL4.IMUX_C5

Bel DCS_SE0

xp CLK_ROOT_2PLL_B bel DCS_SE0
PinDirectionWires
OUTinputCELL1.PCLK2
SELinputCELL6.IMUX_C5

Bel DCS_SE1

xp CLK_ROOT_2PLL_B bel DCS_SE1
PinDirectionWires
OUTinputCELL1.PCLK3
SELinputCELL7.IMUX_C5

Bel DCS_NW0

xp CLK_ROOT_2PLL_B bel DCS_NW0
PinDirectionWires
OUTinputCELL2.PCLK2
SELinputCELL5.IMUX_B5

Bel DCS_NW1

xp CLK_ROOT_2PLL_B bel DCS_NW1
PinDirectionWires
OUTinputCELL2.PCLK3
SELinputCELL4.IMUX_B5

Bel DCS_NE0

xp CLK_ROOT_2PLL_B bel DCS_NE0
PinDirectionWires
OUTinputCELL3.PCLK2
SELinputCELL6.IMUX_B5

Bel DCS_NE1

xp CLK_ROOT_2PLL_B bel DCS_NE1
PinDirectionWires
OUTinputCELL3.PCLK3
SELinputCELL7.IMUX_B5

Bel CLK_ROOT

xp CLK_ROOT_2PLL_B bel CLK_ROOT
PinDirectionWires
PCLK0_NEinputCELL3.PCLK0
PCLK0_NWinputCELL2.PCLK0
PCLK0_SEinputCELL1.PCLK0
PCLK0_SWinputCELL0.PCLK0
PCLK1_NEinputCELL3.PCLK1
PCLK1_NWinputCELL2.PCLK1
PCLK1_SEinputCELL1.PCLK1
PCLK1_SWinputCELL0.PCLK1
PCLK_IN_EinputCELL9.IMUX_B5
PCLK_IN_NinputCELL11.IMUX_B5
PCLK_IN_SinputCELL10.IMUX_B5
PCLK_IN_WinputCELL8.IMUX_B5
SCLK0_NEinputCELL3.SCLK0
SCLK0_NWinputCELL2.SCLK0
SCLK0_SEinputCELL1.SCLK0
SCLK0_SWinputCELL0.SCLK0
SCLK1_NEinputCELL3.SCLK1
SCLK1_NWinputCELL2.SCLK1
SCLK1_SEinputCELL1.SCLK1
SCLK1_SWinputCELL0.SCLK1
SCLK2_NEinputCELL3.SCLK2
SCLK2_NWinputCELL2.SCLK2
SCLK2_SEinputCELL1.SCLK2
SCLK2_SWinputCELL0.SCLK2
SCLK3_NEinputCELL3.SCLK3
SCLK3_NWinputCELL2.SCLK3
SCLK3_SEinputCELL1.SCLK3
SCLK3_SWinputCELL0.SCLK3
SCLK_IN_E0inputCELL16.IMUX_B5
SCLK_IN_E1inputCELL17.IMUX_B5
SCLK_IN_E2inputCELL18.IMUX_B0
SCLK_IN_E3inputCELL19.IMUX_B0
SCLK_IN_N0inputCELL24.IMUX_B5
SCLK_IN_N1inputCELL25.IMUX_B5
SCLK_IN_N2inputCELL26.IMUX_D5
SCLK_IN_N3inputCELL27.IMUX_B0
SCLK_IN_S0inputCELL20.IMUX_B5
SCLK_IN_S1inputCELL21.IMUX_B5
SCLK_IN_S2inputCELL22.IMUX_B0
SCLK_IN_S3inputCELL23.IMUX_D5
SCLK_IN_W0inputCELL12.IMUX_B5
SCLK_IN_W1inputCELL13.IMUX_B5
SCLK_IN_W2inputCELL14.IMUX_D5
SCLK_IN_W3inputCELL15.IMUX_D5

Bel wires

xp CLK_ROOT_2PLL_B bel wires
WirePins
CELL0.PCLK0CLK_ROOT.PCLK0_SW
CELL0.PCLK1CLK_ROOT.PCLK1_SW
CELL0.PCLK2DCS_SW0.OUT
CELL0.PCLK3DCS_SW1.OUT
CELL0.SCLK0CLK_ROOT.SCLK0_SW
CELL0.SCLK1CLK_ROOT.SCLK1_SW
CELL0.SCLK2CLK_ROOT.SCLK2_SW
CELL0.SCLK3CLK_ROOT.SCLK3_SW
CELL1.PCLK0CLK_ROOT.PCLK0_SE
CELL1.PCLK1CLK_ROOT.PCLK1_SE
CELL1.PCLK2DCS_SE0.OUT
CELL1.PCLK3DCS_SE1.OUT
CELL1.SCLK0CLK_ROOT.SCLK0_SE
CELL1.SCLK1CLK_ROOT.SCLK1_SE
CELL1.SCLK2CLK_ROOT.SCLK2_SE
CELL1.SCLK3CLK_ROOT.SCLK3_SE
CELL2.PCLK0CLK_ROOT.PCLK0_NW
CELL2.PCLK1CLK_ROOT.PCLK1_NW
CELL2.PCLK2DCS_NW0.OUT
CELL2.PCLK3DCS_NW1.OUT
CELL2.SCLK0CLK_ROOT.SCLK0_NW
CELL2.SCLK1CLK_ROOT.SCLK1_NW
CELL2.SCLK2CLK_ROOT.SCLK2_NW
CELL2.SCLK3CLK_ROOT.SCLK3_NW
CELL3.PCLK0CLK_ROOT.PCLK0_NE
CELL3.PCLK1CLK_ROOT.PCLK1_NE
CELL3.PCLK2DCS_NE0.OUT
CELL3.PCLK3DCS_NE1.OUT
CELL3.SCLK0CLK_ROOT.SCLK0_NE
CELL3.SCLK1CLK_ROOT.SCLK1_NE
CELL3.SCLK2CLK_ROOT.SCLK2_NE
CELL3.SCLK3CLK_ROOT.SCLK3_NE
CELL4.IMUX_B5DCS_NW1.SEL
CELL4.IMUX_C5DCS_SW1.SEL
CELL5.IMUX_B5DCS_NW0.SEL
CELL5.IMUX_C5DCS_SW0.SEL
CELL6.IMUX_B5DCS_NE0.SEL
CELL6.IMUX_C5DCS_SE0.SEL
CELL7.IMUX_B5DCS_NE1.SEL
CELL7.IMUX_C5DCS_SE1.SEL
CELL8.IMUX_B5CLK_ROOT.PCLK_IN_W
CELL9.IMUX_B5CLK_ROOT.PCLK_IN_E
CELL10.IMUX_B5CLK_ROOT.PCLK_IN_S
CELL11.IMUX_B5CLK_ROOT.PCLK_IN_N
CELL12.IMUX_B5CLK_ROOT.SCLK_IN_W0
CELL13.IMUX_B5CLK_ROOT.SCLK_IN_W1
CELL14.IMUX_D5CLK_ROOT.SCLK_IN_W2
CELL15.IMUX_D5CLK_ROOT.SCLK_IN_W3
CELL16.IMUX_B5CLK_ROOT.SCLK_IN_E0
CELL17.IMUX_B5CLK_ROOT.SCLK_IN_E1
CELL18.IMUX_B0CLK_ROOT.SCLK_IN_E2
CELL19.IMUX_B0CLK_ROOT.SCLK_IN_E3
CELL20.IMUX_B5CLK_ROOT.SCLK_IN_S0
CELL21.IMUX_B5CLK_ROOT.SCLK_IN_S1
CELL22.IMUX_B0CLK_ROOT.SCLK_IN_S2
CELL23.IMUX_D5CLK_ROOT.SCLK_IN_S3
CELL24.IMUX_B5CLK_ROOT.SCLK_IN_N0
CELL25.IMUX_B5CLK_ROOT.SCLK_IN_N1
CELL26.IMUX_D5CLK_ROOT.SCLK_IN_N2
CELL27.IMUX_B0CLK_ROOT.SCLK_IN_N3

Tile CLK_ROOT_4PLL

Cells: 32

Bel DCS_SW0

xp CLK_ROOT_4PLL bel DCS_SW0
PinDirectionWires
OUTinputCELL0.PCLK2
SELinputCELL5.IMUX_B5

Bel DCS_SW1

xp CLK_ROOT_4PLL bel DCS_SW1
PinDirectionWires
OUTinputCELL0.PCLK3
SELinputCELL4.IMUX_B5

Bel DCS_SE0

xp CLK_ROOT_4PLL bel DCS_SE0
PinDirectionWires
OUTinputCELL1.PCLK2
SELinputCELL6.IMUX_B5

Bel DCS_SE1

xp CLK_ROOT_4PLL bel DCS_SE1
PinDirectionWires
OUTinputCELL1.PCLK3
SELinputCELL7.IMUX_B5

Bel DCS_NW0

xp CLK_ROOT_4PLL bel DCS_NW0
PinDirectionWires
OUTinputCELL2.PCLK2
SELinputCELL9.IMUX_B5

Bel DCS_NW1

xp CLK_ROOT_4PLL bel DCS_NW1
PinDirectionWires
OUTinputCELL2.PCLK3
SELinputCELL8.IMUX_B5

Bel DCS_NE0

xp CLK_ROOT_4PLL bel DCS_NE0
PinDirectionWires
OUTinputCELL3.PCLK2
SELinputCELL10.IMUX_B5

Bel DCS_NE1

xp CLK_ROOT_4PLL bel DCS_NE1
PinDirectionWires
OUTinputCELL3.PCLK3
SELinputCELL11.IMUX_B5

Bel CLK_ROOT

xp CLK_ROOT_4PLL bel CLK_ROOT
PinDirectionWires
PCLK0_NEinputCELL3.PCLK0
PCLK0_NWinputCELL2.PCLK0
PCLK0_SEinputCELL1.PCLK0
PCLK0_SWinputCELL0.PCLK0
PCLK1_NEinputCELL3.PCLK1
PCLK1_NWinputCELL2.PCLK1
PCLK1_SEinputCELL1.PCLK1
PCLK1_SWinputCELL0.PCLK1
PCLK_IN_EinputCELL13.IMUX_B5
PCLK_IN_NinputCELL15.IMUX_B5
PCLK_IN_SinputCELL14.IMUX_B5
PCLK_IN_WinputCELL12.IMUX_B5
SCLK0_NEinputCELL3.SCLK0
SCLK0_NWinputCELL2.SCLK0
SCLK0_SEinputCELL1.SCLK0
SCLK0_SWinputCELL0.SCLK0
SCLK1_NEinputCELL3.SCLK1
SCLK1_NWinputCELL2.SCLK1
SCLK1_SEinputCELL1.SCLK1
SCLK1_SWinputCELL0.SCLK1
SCLK2_NEinputCELL3.SCLK2
SCLK2_NWinputCELL2.SCLK2
SCLK2_SEinputCELL1.SCLK2
SCLK2_SWinputCELL0.SCLK2
SCLK3_NEinputCELL3.SCLK3
SCLK3_NWinputCELL2.SCLK3
SCLK3_SEinputCELL1.SCLK3
SCLK3_SWinputCELL0.SCLK3
SCLK_IN_E0inputCELL20.IMUX_B5
SCLK_IN_E1inputCELL21.IMUX_B5
SCLK_IN_E2inputCELL22.IMUX_B0
SCLK_IN_E3inputCELL23.IMUX_B0
SCLK_IN_N0inputCELL28.IMUX_B5
SCLK_IN_N1inputCELL29.IMUX_B5
SCLK_IN_N2inputCELL30.IMUX_B0
SCLK_IN_N3inputCELL31.IMUX_D5
SCLK_IN_S0inputCELL24.IMUX_B5
SCLK_IN_S1inputCELL25.IMUX_B5
SCLK_IN_S2inputCELL26.IMUX_B0
SCLK_IN_S3inputCELL27.IMUX_D5
SCLK_IN_W0inputCELL16.IMUX_B5
SCLK_IN_W1inputCELL17.IMUX_B5
SCLK_IN_W2inputCELL18.IMUX_D5
SCLK_IN_W3inputCELL19.IMUX_D5

Bel wires

xp CLK_ROOT_4PLL bel wires
WirePins
CELL0.PCLK0CLK_ROOT.PCLK0_SW
CELL0.PCLK1CLK_ROOT.PCLK1_SW
CELL0.PCLK2DCS_SW0.OUT
CELL0.PCLK3DCS_SW1.OUT
CELL0.SCLK0CLK_ROOT.SCLK0_SW
CELL0.SCLK1CLK_ROOT.SCLK1_SW
CELL0.SCLK2CLK_ROOT.SCLK2_SW
CELL0.SCLK3CLK_ROOT.SCLK3_SW
CELL1.PCLK0CLK_ROOT.PCLK0_SE
CELL1.PCLK1CLK_ROOT.PCLK1_SE
CELL1.PCLK2DCS_SE0.OUT
CELL1.PCLK3DCS_SE1.OUT
CELL1.SCLK0CLK_ROOT.SCLK0_SE
CELL1.SCLK1CLK_ROOT.SCLK1_SE
CELL1.SCLK2CLK_ROOT.SCLK2_SE
CELL1.SCLK3CLK_ROOT.SCLK3_SE
CELL2.PCLK0CLK_ROOT.PCLK0_NW
CELL2.PCLK1CLK_ROOT.PCLK1_NW
CELL2.PCLK2DCS_NW0.OUT
CELL2.PCLK3DCS_NW1.OUT
CELL2.SCLK0CLK_ROOT.SCLK0_NW
CELL2.SCLK1CLK_ROOT.SCLK1_NW
CELL2.SCLK2CLK_ROOT.SCLK2_NW
CELL2.SCLK3CLK_ROOT.SCLK3_NW
CELL3.PCLK0CLK_ROOT.PCLK0_NE
CELL3.PCLK1CLK_ROOT.PCLK1_NE
CELL3.PCLK2DCS_NE0.OUT
CELL3.PCLK3DCS_NE1.OUT
CELL3.SCLK0CLK_ROOT.SCLK0_NE
CELL3.SCLK1CLK_ROOT.SCLK1_NE
CELL3.SCLK2CLK_ROOT.SCLK2_NE
CELL3.SCLK3CLK_ROOT.SCLK3_NE
CELL4.IMUX_B5DCS_SW1.SEL
CELL5.IMUX_B5DCS_SW0.SEL
CELL6.IMUX_B5DCS_SE0.SEL
CELL7.IMUX_B5DCS_SE1.SEL
CELL8.IMUX_B5DCS_NW1.SEL
CELL9.IMUX_B5DCS_NW0.SEL
CELL10.IMUX_B5DCS_NE0.SEL
CELL11.IMUX_B5DCS_NE1.SEL
CELL12.IMUX_B5CLK_ROOT.PCLK_IN_W
CELL13.IMUX_B5CLK_ROOT.PCLK_IN_E
CELL14.IMUX_B5CLK_ROOT.PCLK_IN_S
CELL15.IMUX_B5CLK_ROOT.PCLK_IN_N
CELL16.IMUX_B5CLK_ROOT.SCLK_IN_W0
CELL17.IMUX_B5CLK_ROOT.SCLK_IN_W1
CELL18.IMUX_D5CLK_ROOT.SCLK_IN_W2
CELL19.IMUX_D5CLK_ROOT.SCLK_IN_W3
CELL20.IMUX_B5CLK_ROOT.SCLK_IN_E0
CELL21.IMUX_B5CLK_ROOT.SCLK_IN_E1
CELL22.IMUX_B0CLK_ROOT.SCLK_IN_E2
CELL23.IMUX_B0CLK_ROOT.SCLK_IN_E3
CELL24.IMUX_B5CLK_ROOT.SCLK_IN_S0
CELL25.IMUX_B5CLK_ROOT.SCLK_IN_S1
CELL26.IMUX_B0CLK_ROOT.SCLK_IN_S2
CELL27.IMUX_D5CLK_ROOT.SCLK_IN_S3
CELL28.IMUX_B5CLK_ROOT.SCLK_IN_N0
CELL29.IMUX_B5CLK_ROOT.SCLK_IN_N1
CELL30.IMUX_B0CLK_ROOT.SCLK_IN_N2
CELL31.IMUX_D5CLK_ROOT.SCLK_IN_N3