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Clock interconnect

Tile CLK_S

Cells: 6

Bel DLLDEL0

crosslink CLK_S bel DLLDEL0
PinDirectionWires
CFLAGoutputTCELL0:OUT_Q7
DIRECTIONinputTCELL0:IMUX_D6
LOADNinputTCELL0:IMUX_B6
MOVEinputTCELL0:IMUX_C6

Bel DLLDEL1

crosslink CLK_S bel DLLDEL1
PinDirectionWires
CFLAGoutputTCELL1:OUT_Q7
DIRECTIONinputTCELL1:IMUX_D6
LOADNinputTCELL1:IMUX_B6
MOVEinputTCELL1:IMUX_C6

Bel DLLDEL2

crosslink CLK_S bel DLLDEL2
PinDirectionWires
CFLAGoutputTCELL2:OUT_Q7
DIRECTIONinputTCELL2:IMUX_D6
LOADNinputTCELL2:IMUX_B6
MOVEinputTCELL2:IMUX_C6

Bel DLLDEL3

crosslink CLK_S bel DLLDEL3
PinDirectionWires
CFLAGoutputTCELL3:OUT_Q7
DIRECTIONinputTCELL3:IMUX_D6
LOADNinputTCELL3:IMUX_B6
MOVEinputTCELL3:IMUX_C6

Bel CLKDIV0

crosslink CLK_S bel CLKDIV0
PinDirectionWires
ALIGNWDinputTCELL1:IMUX_A3
CDIVXoutputTCELL1:OUT_F2
RSTinputTCELL1:IMUX_LSR0

Bel CLKDIV1

crosslink CLK_S bel CLKDIV1
PinDirectionWires
ALIGNWDinputTCELL1:IMUX_B3
CDIVXoutputTCELL1:OUT_F3
RSTinputTCELL1:IMUX_LSR1

Bel CLKDIV2

crosslink CLK_S bel CLKDIV2
PinDirectionWires
ALIGNWDinputTCELL1:IMUX_C2
CDIVXoutputTCELL2:OUT_F2
RSTinputTCELL2:IMUX_LSR0

Bel CLKDIV3

crosslink CLK_S bel CLKDIV3
PinDirectionWires
ALIGNWDinputTCELL1:IMUX_D2
CDIVXoutputTCELL2:OUT_F3
RSTinputTCELL2:IMUX_LSR1

Bel DCC0

crosslink CLK_S bel DCC0
PinDirectionWires
CEinputTCELL2:IMUX_A0

Bel DCC1

crosslink CLK_S bel DCC1
PinDirectionWires
CEinputTCELL2:IMUX_A1

Bel DCC2

crosslink CLK_S bel DCC2
PinDirectionWires
CEinputTCELL2:IMUX_A2

Bel DCC3

crosslink CLK_S bel DCC3
PinDirectionWires
CEinputTCELL2:IMUX_A3

Bel DCC4

crosslink CLK_S bel DCC4
PinDirectionWires
CEinputTCELL2:IMUX_A4

Bel DCC5

crosslink CLK_S bel DCC5
PinDirectionWires
CEinputTCELL2:IMUX_A5

Bel DCC6

crosslink CLK_S bel DCC6
PinDirectionWires
CEinputTCELL2:IMUX_A6

Bel DCC7

crosslink CLK_S bel DCC7
PinDirectionWires
CEinputTCELL2:IMUX_A7

Bel CLK_EDGE

crosslink CLK_S bel CLK_EDGE
PinDirectionWires
INT_IN_0inputTCELL4:IMUX_D7
INT_IN_1inputTCELL5:IMUX_D7

Bel CLKTEST

crosslink CLK_S bel CLKTEST
PinDirectionWires
TESTIN0inputTCELL2:IMUX_B0
TESTIN1inputTCELL2:IMUX_B1
TESTIN2inputTCELL2:IMUX_B2

Bel ECLKSYNC0

crosslink CLK_S bel ECLKSYNC0
PinDirectionWires
ECLKoutputTCELL1:OUT_F0
ECLKIinputTCELL1:IMUX_CLK0
STOPinputTCELL1:IMUX_A0

Bel ECLKSYNC1

crosslink CLK_S bel ECLKSYNC1
PinDirectionWires
ECLKoutputTCELL1:OUT_F1
ECLKIinputTCELL1:IMUX_CLK0
STOPinputTCELL1:IMUX_B0

Bel ECLKSYNC2

crosslink CLK_S bel ECLKSYNC2
PinDirectionWires
ECLKoutputTCELL2:OUT_F0
ECLKIinputTCELL1:IMUX_CLK1
STOPinputTCELL1:IMUX_C0

Bel ECLKSYNC3

crosslink CLK_S bel ECLKSYNC3
PinDirectionWires
ECLKoutputTCELL2:OUT_F1
ECLKIinputTCELL1:IMUX_CLK1
STOPinputTCELL1:IMUX_D0

Bel CLKTEST_ECLK

crosslink CLK_S bel CLKTEST_ECLK
PinDirectionWires
TESTIN0inputTCELL1:IMUX_A4
TESTIN1inputTCELL1:IMUX_B4
TESTIN2inputTCELL1:IMUX_C4
TESTIN3inputTCELL1:IMUX_A5
TESTIN4inputTCELL1:IMUX_B5
TESTIN5inputTCELL1:IMUX_C5

Bel wires

crosslink CLK_S bel wires
WirePins
TCELL0:IMUX_B6DLLDEL0.LOADN
TCELL0:IMUX_C6DLLDEL0.MOVE
TCELL0:IMUX_D6DLLDEL0.DIRECTION
TCELL0:OUT_Q7DLLDEL0.CFLAG
TCELL1:IMUX_A0ECLKSYNC0.STOP
TCELL1:IMUX_A3CLKDIV0.ALIGNWD
TCELL1:IMUX_A4CLKTEST_ECLK.TESTIN0
TCELL1:IMUX_A5CLKTEST_ECLK.TESTIN3
TCELL1:IMUX_B0ECLKSYNC1.STOP
TCELL1:IMUX_B3CLKDIV1.ALIGNWD
TCELL1:IMUX_B4CLKTEST_ECLK.TESTIN1
TCELL1:IMUX_B5CLKTEST_ECLK.TESTIN4
TCELL1:IMUX_B6DLLDEL1.LOADN
TCELL1:IMUX_C0ECLKSYNC2.STOP
TCELL1:IMUX_C2CLKDIV2.ALIGNWD
TCELL1:IMUX_C4CLKTEST_ECLK.TESTIN2
TCELL1:IMUX_C5CLKTEST_ECLK.TESTIN5
TCELL1:IMUX_C6DLLDEL1.MOVE
TCELL1:IMUX_D0ECLKSYNC3.STOP
TCELL1:IMUX_D2CLKDIV3.ALIGNWD
TCELL1:IMUX_D6DLLDEL1.DIRECTION
TCELL1:IMUX_CLK0ECLKSYNC0.ECLKI, ECLKSYNC1.ECLKI
TCELL1:IMUX_CLK1ECLKSYNC2.ECLKI, ECLKSYNC3.ECLKI
TCELL1:IMUX_LSR0CLKDIV0.RST
TCELL1:IMUX_LSR1CLKDIV1.RST
TCELL1:OUT_F0ECLKSYNC0.ECLK
TCELL1:OUT_F1ECLKSYNC1.ECLK
TCELL1:OUT_F2CLKDIV0.CDIVX
TCELL1:OUT_F3CLKDIV1.CDIVX
TCELL1:OUT_Q7DLLDEL1.CFLAG
TCELL2:IMUX_A0DCC0.CE
TCELL2:IMUX_A1DCC1.CE
TCELL2:IMUX_A2DCC2.CE
TCELL2:IMUX_A3DCC3.CE
TCELL2:IMUX_A4DCC4.CE
TCELL2:IMUX_A5DCC5.CE
TCELL2:IMUX_A6DCC6.CE
TCELL2:IMUX_A7DCC7.CE
TCELL2:IMUX_B0CLKTEST.TESTIN0
TCELL2:IMUX_B1CLKTEST.TESTIN1
TCELL2:IMUX_B2CLKTEST.TESTIN2
TCELL2:IMUX_B6DLLDEL2.LOADN
TCELL2:IMUX_C6DLLDEL2.MOVE
TCELL2:IMUX_D6DLLDEL2.DIRECTION
TCELL2:IMUX_LSR0CLKDIV2.RST
TCELL2:IMUX_LSR1CLKDIV3.RST
TCELL2:OUT_F0ECLKSYNC2.ECLK
TCELL2:OUT_F1ECLKSYNC3.ECLK
TCELL2:OUT_F2CLKDIV2.CDIVX
TCELL2:OUT_F3CLKDIV3.CDIVX
TCELL2:OUT_Q7DLLDEL2.CFLAG
TCELL3:IMUX_B6DLLDEL3.LOADN
TCELL3:IMUX_C6DLLDEL3.MOVE
TCELL3:IMUX_D6DLLDEL3.DIRECTION
TCELL3:OUT_Q7DLLDEL3.CFLAG
TCELL4:IMUX_D7CLK_EDGE.INT_IN_0
TCELL5:IMUX_D7CLK_EDGE.INT_IN_1

Tile CLK_N

Cells: 2

Bel DCC0

crosslink CLK_N bel DCC0
PinDirectionWires
CEinputTCELL1:IMUX_A0

Bel DCC1

crosslink CLK_N bel DCC1
PinDirectionWires
CEinputTCELL1:IMUX_A1

Bel DCC2

crosslink CLK_N bel DCC2
PinDirectionWires
CEinputTCELL1:IMUX_A2

Bel DCC3

crosslink CLK_N bel DCC3
PinDirectionWires
CEinputTCELL1:IMUX_A3

Bel DCC4

crosslink CLK_N bel DCC4
PinDirectionWires
CEinputTCELL1:IMUX_A4

Bel DCC5

crosslink CLK_N bel DCC5
PinDirectionWires
CEinputTCELL1:IMUX_A5

Bel CLK_EDGE

crosslink CLK_N bel CLK_EDGE
PinDirectionWires
INT_IN_0inputTCELL0:IMUX_D7
INT_IN_1inputTCELL1:IMUX_D7

Bel CLKTEST

crosslink CLK_N bel CLKTEST
PinDirectionWires
TESTIN0inputTCELL1:IMUX_B4
TESTIN1inputTCELL1:IMUX_D5
TESTIN2inputTCELL1:IMUX_B6

Bel wires

crosslink CLK_N bel wires
WirePins
TCELL0:IMUX_D7CLK_EDGE.INT_IN_0
TCELL1:IMUX_A0DCC0.CE
TCELL1:IMUX_A1DCC1.CE
TCELL1:IMUX_A2DCC2.CE
TCELL1:IMUX_A3DCC3.CE
TCELL1:IMUX_A4DCC4.CE
TCELL1:IMUX_A5DCC5.CE
TCELL1:IMUX_B4CLKTEST.TESTIN0
TCELL1:IMUX_B6CLKTEST.TESTIN2
TCELL1:IMUX_D5CLKTEST.TESTIN1
TCELL1:IMUX_D7CLK_EDGE.INT_IN_1

Tile CLK_ROOT

Cells: 1

Bel DCS0

crosslink CLK_ROOT bel DCS0
PinDirectionWires
MODESELinputIMUX_A2
SEL0inputIMUX_A0
SEL1inputIMUX_A1

Bel CLK_ROOT

crosslink CLK_ROOT bel CLK_ROOT
PinDirectionWires
PCLK0outputPCLK0
PCLK1outputPCLK1
PCLK2outputPCLK2
PCLK3outputPCLK3
PCLK4outputPCLK4
PCLK5outputPCLK5
PCLK6outputPCLK6
PCLK7outputPCLK7

Bel CLKTEST

crosslink CLK_ROOT bel CLKTEST
PinDirectionWires
TESTIN0inputIMUX_B0
TESTIN1inputIMUX_B1
TESTIN2inputIMUX_B2
TESTIN3inputIMUX_B3

Bel wires

crosslink CLK_ROOT bel wires
WirePins
PCLK0CLK_ROOT.PCLK0
PCLK1CLK_ROOT.PCLK1
PCLK2CLK_ROOT.PCLK2
PCLK3CLK_ROOT.PCLK3
PCLK4CLK_ROOT.PCLK4
PCLK5CLK_ROOT.PCLK5
PCLK6CLK_ROOT.PCLK6
PCLK7CLK_ROOT.PCLK7
IMUX_A0DCS0.SEL0
IMUX_A1DCS0.SEL1
IMUX_A2DCS0.MODESEL
IMUX_B0CLKTEST.TESTIN0
IMUX_B1CLKTEST.TESTIN1
IMUX_B2CLKTEST.TESTIN2
IMUX_B3CLKTEST.TESTIN3