Cells: 2
crosslink PLL bel PLL0
| Pin | Direction | Wires |
|---|
| CLKFB | input | TCELL1:IMUX_CLK0 |
| CLKOP | output | TCELL1:OUT_F0 |
| CLKOS | output | TCELL1:OUT_F1 |
| CLKOS2 | output | TCELL1:OUT_F2 |
| CLKOS3 | output | TCELL1:OUT_F3 |
| ENCLKOP | input | TCELL1:IMUX_B6 |
| ENCLKOS | input | TCELL1:IMUX_A4 |
| ENCLKOS2 | input | TCELL1:IMUX_A2 |
| ENCLKOS3 | input | TCELL1:IMUX_A0 |
| INTLOCK | output | TCELL1:OUT_F5 |
| LOCK | output | TCELL1:OUT_F6 |
| PFDDN | output | TCELL1:OUT_Q7 |
| PFDUP | output | TCELL1:OUT_Q6 |
| PHASEDIR | input | TCELL1:IMUX_C4 |
| PHASELOADREG | input | TCELL1:IMUX_C2 |
| PHASESEL0 | input | TCELL1:IMUX_B0 |
| PHASESEL1 | input | TCELL1:IMUX_B4 |
| PHASESTEP | input | TCELL1:IMUX_C0 |
| PLLWAKESYNC | input | TCELL1:IMUX_D6 |
| REFCLK | output | TCELL1:OUT_F4 |
| RST | input | TCELL1:IMUX_C6 |
| USRSTDBY | input | TCELL1:IMUX_LSR0 |
crosslink PLL bel PLLREFCS0
| Pin | Direction | Wires |
|---|
| CLK0 | input | TCELL0:IMUX_CLK0 |
| CLK1 | input | TCELL0:IMUX_CLK1 |
| SEL | input | TCELL1:IMUX_A6 |
crosslink PLL bel wires
| Wire | Pins |
|---|
| TCELL0:IMUX_CLK0 | PLLREFCS0.CLK0 |
| TCELL0:IMUX_CLK1 | PLLREFCS0.CLK1 |
| TCELL1:IMUX_A0 | PLL0.ENCLKOS3 |
| TCELL1:IMUX_A2 | PLL0.ENCLKOS2 |
| TCELL1:IMUX_A4 | PLL0.ENCLKOS |
| TCELL1:IMUX_A6 | PLLREFCS0.SEL |
| TCELL1:IMUX_B0 | PLL0.PHASESEL0 |
| TCELL1:IMUX_B4 | PLL0.PHASESEL1 |
| TCELL1:IMUX_B6 | PLL0.ENCLKOP |
| TCELL1:IMUX_C0 | PLL0.PHASESTEP |
| TCELL1:IMUX_C2 | PLL0.PHASELOADREG |
| TCELL1:IMUX_C4 | PLL0.PHASEDIR |
| TCELL1:IMUX_C6 | PLL0.RST |
| TCELL1:IMUX_D6 | PLL0.PLLWAKESYNC |
| TCELL1:IMUX_CLK0 | PLL0.CLKFB |
| TCELL1:IMUX_LSR0 | PLL0.USRSTDBY |
| TCELL1:OUT_F0 | PLL0.CLKOP |
| TCELL1:OUT_F1 | PLL0.CLKOS |
| TCELL1:OUT_F2 | PLL0.CLKOS2 |
| TCELL1:OUT_F3 | PLL0.CLKOS3 |
| TCELL1:OUT_F4 | PLL0.REFCLK |
| TCELL1:OUT_F5 | PLL0.INTLOCK |
| TCELL1:OUT_F6 | PLL0.LOCK |
| TCELL1:OUT_Q6 | PLL0.PFDUP |
| TCELL1:OUT_Q7 | PLL0.PFDDN |