Keyboard shortcuts

Press ← or → to navigate between chapters

Press ? to show this help

Press Esc to hide this help

Phase-Locked Loops

Tile PLL

Cells: 2

Bel PLL0

crosslink PLL bel PLL0
PinDirectionWires
CLKFBinputCELL1.IMUX_CLK0
CLKOPoutputCELL1.OUT_F0
CLKOSoutputCELL1.OUT_F1
CLKOS2outputCELL1.OUT_F2
CLKOS3outputCELL1.OUT_F3
ENCLKOPinputCELL1.IMUX_B6
ENCLKOSinputCELL1.IMUX_A4
ENCLKOS2inputCELL1.IMUX_A2
ENCLKOS3inputCELL1.IMUX_A0
INTLOCKoutputCELL1.OUT_F5
LOCKoutputCELL1.OUT_F6
PFDDNoutputCELL1.OUT_Q7
PFDUPoutputCELL1.OUT_Q6
PHASEDIRinputCELL1.IMUX_C4
PHASELOADREGinputCELL1.IMUX_C2
PHASESEL0inputCELL1.IMUX_B0
PHASESEL1inputCELL1.IMUX_B4
PHASESTEPinputCELL1.IMUX_C0
PLLWAKESYNCinputCELL1.IMUX_D6
REFCLKoutputCELL1.OUT_F4
RSTinputCELL1.IMUX_C6
USRSTDBYinputCELL1.IMUX_LSR0

Bel PLLREFCS0

crosslink PLL bel PLLREFCS0
PinDirectionWires
CLK0inputCELL0.IMUX_CLK0
CLK1inputCELL0.IMUX_CLK1
SELinputCELL1.IMUX_A6

Bel wires

crosslink PLL bel wires
WirePins
CELL0.IMUX_CLK0PLLREFCS0.CLK0
CELL0.IMUX_CLK1PLLREFCS0.CLK1
CELL1.IMUX_A0PLL0.ENCLKOS3
CELL1.IMUX_A2PLL0.ENCLKOS2
CELL1.IMUX_A4PLL0.ENCLKOS
CELL1.IMUX_A6PLLREFCS0.SEL
CELL1.IMUX_B0PLL0.PHASESEL0
CELL1.IMUX_B4PLL0.PHASESEL1
CELL1.IMUX_B6PLL0.ENCLKOP
CELL1.IMUX_C0PLL0.PHASESTEP
CELL1.IMUX_C2PLL0.PHASELOADREG
CELL1.IMUX_C4PLL0.PHASEDIR
CELL1.IMUX_C6PLL0.RST
CELL1.IMUX_D6PLL0.PLLWAKESYNC
CELL1.IMUX_CLK0PLL0.CLKFB
CELL1.IMUX_LSR0PLL0.USRSTDBY
CELL1.OUT_F0PLL0.CLKOP
CELL1.OUT_F1PLL0.CLKOS
CELL1.OUT_F2PLL0.CLKOS2
CELL1.OUT_F3PLL0.CLKOS3
CELL1.OUT_F4PLL0.REFCLK
CELL1.OUT_F5PLL0.INTLOCK
CELL1.OUT_F6PLL0.LOCK
CELL1.OUT_Q6PLL0.PFDUP
CELL1.OUT_Q7PLL0.PFDDN