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Phase-Locked Loops

Tile PLL_SW

Cells: 4

Bel PLL0

ecp4 PLL_SW bel PLL0
PinDirectionWires
CLKFB2inputCELL3.IMUX_CLK1_DELAY
CLKOPoutputCELL3.OUT_F0
CLKOSoutputCELL3.OUT_F2
CLKOS2outputCELL3.OUT_F4
CLKOS3outputCELL3.OUT_F6
ENCLKOPinputCELL3.IMUX_D2
ENCLKOSinputCELL3.IMUX_A3
ENCLKOS2inputCELL3.IMUX_B3
ENCLKOS3inputCELL3.IMUX_C3
INTLOCKoutputCELL3.OUT_Q4
LOCKoutputCELL3.OUT_Q2
PHASEDIRinputCELL3.IMUX_D4
PHASELOADREGinputCELL3.IMUX_D3
PHASESEL0inputCELL3.IMUX_B4
PHASESEL1inputCELL3.IMUX_A4
PHASESRCSTAToutputCELL3.OUT_Q6
PHASESTEPinputCELL3.IMUX_C4
PLLWAKESYNCinputCELL3.IMUX_C2
REFCLKoutputCELL3.OUT_Q0
RSTinputCELL3.IMUX_B1
SMIADinputCELL2.IMUX_A4
SMICLKinputCELL2.IMUX_CLK1_DELAY
SMIRDinputCELL2.IMUX_B4
SMIRDATAoutputCELL2.OUT_F0
SMIRSTNinputCELL2.IMUX_A5
SMIWDATAinputCELL2.IMUX_D4
SMIWRinputCELL2.IMUX_C4
STDBYinputCELL3.IMUX_LSR0

Bel PLL1

ecp4 PLL_SW bel PLL1
PinDirectionWires
CLKFB2inputCELL1.IMUX_CLK1_DELAY
CLKOPoutputCELL1.OUT_F0
CLKOSoutputCELL1.OUT_F2
CLKOS2outputCELL1.OUT_F4
CLKOS3outputCELL1.OUT_F6
ENCLKOPinputCELL1.IMUX_D2
ENCLKOSinputCELL1.IMUX_A3
ENCLKOS2inputCELL1.IMUX_B3
ENCLKOS3inputCELL1.IMUX_C3
INTLOCKoutputCELL1.OUT_Q4
LOCKoutputCELL1.OUT_Q2
PHASEDIRinputCELL1.IMUX_D4
PHASELOADREGinputCELL1.IMUX_D3
PHASESEL0inputCELL1.IMUX_B4
PHASESEL1inputCELL1.IMUX_A4
PHASESRCSTAToutputCELL1.OUT_Q6
PHASESTEPinputCELL1.IMUX_C4
PLLWAKESYNCinputCELL1.IMUX_C2
REFCLKoutputCELL1.OUT_Q0
RSTinputCELL1.IMUX_B1
SMIADinputCELL0.IMUX_A4
SMICLKinputCELL0.IMUX_CLK1_DELAY
SMIRDinputCELL0.IMUX_B4
SMIRDATAoutputCELL0.OUT_F0
SMIRSTNinputCELL0.IMUX_A5
SMIWDATAinputCELL0.IMUX_D4
SMIWRinputCELL0.IMUX_C4
STDBYinputCELL1.IMUX_LSR0

Bel PLLREFCS0

ecp4 PLL_SW bel PLLREFCS0
PinDirectionWires
REFCLK0_2inputCELL3.IMUX_A0
REFCLK0_3inputCELL3.IMUX_CLK0_DELAY
REFCLK1_2inputCELL2.IMUX_A0
REFCLK1_3inputCELL2.IMUX_CLK0_DELAY
SELinputCELL3.IMUX_B2

Bel PLLREFCS1

ecp4 PLL_SW bel PLLREFCS1
PinDirectionWires
REFCLK0_2inputCELL1.IMUX_A0
REFCLK0_3inputCELL1.IMUX_CLK0_DELAY
REFCLK1_2inputCELL0.IMUX_A0
REFCLK1_3inputCELL0.IMUX_CLK0_DELAY
SELinputCELL1.IMUX_B2

Bel wires

ecp4 PLL_SW bel wires
WirePins
CELL0.IMUX_A0PLLREFCS1.REFCLK1_2
CELL0.IMUX_A4PLL1.SMIAD
CELL0.IMUX_A5PLL1.SMIRSTN
CELL0.IMUX_B4PLL1.SMIRD
CELL0.IMUX_C4PLL1.SMIWR
CELL0.IMUX_D4PLL1.SMIWDATA
CELL0.IMUX_CLK0_DELAYPLLREFCS1.REFCLK1_3
CELL0.IMUX_CLK1_DELAYPLL1.SMICLK
CELL0.OUT_F0PLL1.SMIRDATA
CELL1.IMUX_A0PLLREFCS1.REFCLK0_2
CELL1.IMUX_A3PLL1.ENCLKOS
CELL1.IMUX_A4PLL1.PHASESEL1
CELL1.IMUX_B1PLL1.RST
CELL1.IMUX_B2PLLREFCS1.SEL
CELL1.IMUX_B3PLL1.ENCLKOS2
CELL1.IMUX_B4PLL1.PHASESEL0
CELL1.IMUX_C2PLL1.PLLWAKESYNC
CELL1.IMUX_C3PLL1.ENCLKOS3
CELL1.IMUX_C4PLL1.PHASESTEP
CELL1.IMUX_D2PLL1.ENCLKOP
CELL1.IMUX_D3PLL1.PHASELOADREG
CELL1.IMUX_D4PLL1.PHASEDIR
CELL1.IMUX_LSR0PLL1.STDBY
CELL1.IMUX_CLK0_DELAYPLLREFCS1.REFCLK0_3
CELL1.IMUX_CLK1_DELAYPLL1.CLKFB2
CELL1.OUT_F0PLL1.CLKOP
CELL1.OUT_F2PLL1.CLKOS
CELL1.OUT_F4PLL1.CLKOS2
CELL1.OUT_F6PLL1.CLKOS3
CELL1.OUT_Q0PLL1.REFCLK
CELL1.OUT_Q2PLL1.LOCK
CELL1.OUT_Q4PLL1.INTLOCK
CELL1.OUT_Q6PLL1.PHASESRCSTAT
CELL2.IMUX_A0PLLREFCS0.REFCLK1_2
CELL2.IMUX_A4PLL0.SMIAD
CELL2.IMUX_A5PLL0.SMIRSTN
CELL2.IMUX_B4PLL0.SMIRD
CELL2.IMUX_C4PLL0.SMIWR
CELL2.IMUX_D4PLL0.SMIWDATA
CELL2.IMUX_CLK0_DELAYPLLREFCS0.REFCLK1_3
CELL2.IMUX_CLK1_DELAYPLL0.SMICLK
CELL2.OUT_F0PLL0.SMIRDATA
CELL3.IMUX_A0PLLREFCS0.REFCLK0_2
CELL3.IMUX_A3PLL0.ENCLKOS
CELL3.IMUX_A4PLL0.PHASESEL1
CELL3.IMUX_B1PLL0.RST
CELL3.IMUX_B2PLLREFCS0.SEL
CELL3.IMUX_B3PLL0.ENCLKOS2
CELL3.IMUX_B4PLL0.PHASESEL0
CELL3.IMUX_C2PLL0.PLLWAKESYNC
CELL3.IMUX_C3PLL0.ENCLKOS3
CELL3.IMUX_C4PLL0.PHASESTEP
CELL3.IMUX_D2PLL0.ENCLKOP
CELL3.IMUX_D3PLL0.PHASELOADREG
CELL3.IMUX_D4PLL0.PHASEDIR
CELL3.IMUX_LSR0PLL0.STDBY
CELL3.IMUX_CLK0_DELAYPLLREFCS0.REFCLK0_3
CELL3.IMUX_CLK1_DELAYPLL0.CLKFB2
CELL3.OUT_F0PLL0.CLKOP
CELL3.OUT_F2PLL0.CLKOS
CELL3.OUT_F4PLL0.CLKOS2
CELL3.OUT_F6PLL0.CLKOS3
CELL3.OUT_Q0PLL0.REFCLK
CELL3.OUT_Q2PLL0.LOCK
CELL3.OUT_Q4PLL0.INTLOCK
CELL3.OUT_Q6PLL0.PHASESRCSTAT

Tile PLL_SE

Cells: 4

Bel PLL0

ecp4 PLL_SE bel PLL0
PinDirectionWires
CLKFB2inputCELL3.IMUX_CLK1_DELAY
CLKOPoutputCELL3.OUT_F0
CLKOSoutputCELL3.OUT_F2
CLKOS2outputCELL3.OUT_F4
CLKOS3outputCELL3.OUT_F6
ENCLKOPinputCELL3.IMUX_D2
ENCLKOSinputCELL3.IMUX_A3
ENCLKOS2inputCELL3.IMUX_B3
ENCLKOS3inputCELL3.IMUX_C3
INTLOCKoutputCELL3.OUT_Q4
LOCKoutputCELL3.OUT_Q2
PHASEDIRinputCELL3.IMUX_D4
PHASELOADREGinputCELL3.IMUX_D3
PHASESEL0inputCELL3.IMUX_B4
PHASESEL1inputCELL3.IMUX_A4
PHASESRCSTAToutputCELL3.OUT_Q6
PHASESTEPinputCELL3.IMUX_C4
PLLWAKESYNCinputCELL3.IMUX_C2
REFCLKoutputCELL3.OUT_Q0
RSTinputCELL3.IMUX_B1
SMIADinputCELL2.IMUX_A4
SMICLKinputCELL2.IMUX_CLK1_DELAY
SMIRDinputCELL2.IMUX_B4
SMIRDATAoutputCELL2.OUT_F0
SMIRSTNinputCELL2.IMUX_A5
SMIWDATAinputCELL2.IMUX_D4
SMIWRinputCELL2.IMUX_C4
STDBYinputCELL3.IMUX_LSR0

Bel PLL1

ecp4 PLL_SE bel PLL1
PinDirectionWires
CLKFB2inputCELL0.IMUX_CLK1_DELAY
CLKOPoutputCELL0.OUT_F0
CLKOSoutputCELL0.OUT_F2
CLKOS2outputCELL0.OUT_F4
CLKOS3outputCELL0.OUT_F6
ENCLKOPinputCELL0.IMUX_D2
ENCLKOSinputCELL0.IMUX_A3
ENCLKOS2inputCELL0.IMUX_B3
ENCLKOS3inputCELL0.IMUX_C3
INTLOCKoutputCELL0.OUT_Q4
LOCKoutputCELL0.OUT_Q2
PHASEDIRinputCELL0.IMUX_D4
PHASELOADREGinputCELL0.IMUX_D3
PHASESEL0inputCELL0.IMUX_B4
PHASESEL1inputCELL0.IMUX_A4
PHASESRCSTAToutputCELL0.OUT_Q6
PHASESTEPinputCELL0.IMUX_C4
PLLWAKESYNCinputCELL0.IMUX_C2
REFCLKoutputCELL0.OUT_Q0
RSTinputCELL0.IMUX_B1
SMIADinputCELL1.IMUX_A4
SMICLKinputCELL1.IMUX_CLK1_DELAY
SMIRDinputCELL1.IMUX_B4
SMIRDATAoutputCELL1.OUT_F0
SMIRSTNinputCELL1.IMUX_A5
SMIWDATAinputCELL1.IMUX_D4
SMIWRinputCELL1.IMUX_C4
STDBYinputCELL0.IMUX_LSR0

Bel PLLREFCS0

ecp4 PLL_SE bel PLLREFCS0
PinDirectionWires
REFCLK0_2inputCELL3.IMUX_A0
REFCLK0_3inputCELL3.IMUX_CLK0_DELAY
REFCLK1_2inputCELL2.IMUX_A0
REFCLK1_3inputCELL2.IMUX_CLK0_DELAY
SELinputCELL3.IMUX_B2

Bel PLLREFCS1

ecp4 PLL_SE bel PLLREFCS1
PinDirectionWires
REFCLK0_2inputCELL0.IMUX_A0
REFCLK0_3inputCELL0.IMUX_CLK0_DELAY
REFCLK1_2inputCELL1.IMUX_A0
REFCLK1_3inputCELL1.IMUX_CLK0_DELAY
SELinputCELL0.IMUX_B2

Bel wires

ecp4 PLL_SE bel wires
WirePins
CELL0.IMUX_A0PLLREFCS1.REFCLK0_2
CELL0.IMUX_A3PLL1.ENCLKOS
CELL0.IMUX_A4PLL1.PHASESEL1
CELL0.IMUX_B1PLL1.RST
CELL0.IMUX_B2PLLREFCS1.SEL
CELL0.IMUX_B3PLL1.ENCLKOS2
CELL0.IMUX_B4PLL1.PHASESEL0
CELL0.IMUX_C2PLL1.PLLWAKESYNC
CELL0.IMUX_C3PLL1.ENCLKOS3
CELL0.IMUX_C4PLL1.PHASESTEP
CELL0.IMUX_D2PLL1.ENCLKOP
CELL0.IMUX_D3PLL1.PHASELOADREG
CELL0.IMUX_D4PLL1.PHASEDIR
CELL0.IMUX_LSR0PLL1.STDBY
CELL0.IMUX_CLK0_DELAYPLLREFCS1.REFCLK0_3
CELL0.IMUX_CLK1_DELAYPLL1.CLKFB2
CELL0.OUT_F0PLL1.CLKOP
CELL0.OUT_F2PLL1.CLKOS
CELL0.OUT_F4PLL1.CLKOS2
CELL0.OUT_F6PLL1.CLKOS3
CELL0.OUT_Q0PLL1.REFCLK
CELL0.OUT_Q2PLL1.LOCK
CELL0.OUT_Q4PLL1.INTLOCK
CELL0.OUT_Q6PLL1.PHASESRCSTAT
CELL1.IMUX_A0PLLREFCS1.REFCLK1_2
CELL1.IMUX_A4PLL1.SMIAD
CELL1.IMUX_A5PLL1.SMIRSTN
CELL1.IMUX_B4PLL1.SMIRD
CELL1.IMUX_C4PLL1.SMIWR
CELL1.IMUX_D4PLL1.SMIWDATA
CELL1.IMUX_CLK0_DELAYPLLREFCS1.REFCLK1_3
CELL1.IMUX_CLK1_DELAYPLL1.SMICLK
CELL1.OUT_F0PLL1.SMIRDATA
CELL2.IMUX_A0PLLREFCS0.REFCLK1_2
CELL2.IMUX_A4PLL0.SMIAD
CELL2.IMUX_A5PLL0.SMIRSTN
CELL2.IMUX_B4PLL0.SMIRD
CELL2.IMUX_C4PLL0.SMIWR
CELL2.IMUX_D4PLL0.SMIWDATA
CELL2.IMUX_CLK0_DELAYPLLREFCS0.REFCLK1_3
CELL2.IMUX_CLK1_DELAYPLL0.SMICLK
CELL2.OUT_F0PLL0.SMIRDATA
CELL3.IMUX_A0PLLREFCS0.REFCLK0_2
CELL3.IMUX_A3PLL0.ENCLKOS
CELL3.IMUX_A4PLL0.PHASESEL1
CELL3.IMUX_B1PLL0.RST
CELL3.IMUX_B2PLLREFCS0.SEL
CELL3.IMUX_B3PLL0.ENCLKOS2
CELL3.IMUX_B4PLL0.PHASESEL0
CELL3.IMUX_C2PLL0.PLLWAKESYNC
CELL3.IMUX_C3PLL0.ENCLKOS3
CELL3.IMUX_C4PLL0.PHASESTEP
CELL3.IMUX_D2PLL0.ENCLKOP
CELL3.IMUX_D3PLL0.PHASELOADREG
CELL3.IMUX_D4PLL0.PHASEDIR
CELL3.IMUX_LSR0PLL0.STDBY
CELL3.IMUX_CLK0_DELAYPLLREFCS0.REFCLK0_3
CELL3.IMUX_CLK1_DELAYPLL0.CLKFB2
CELL3.OUT_F0PLL0.CLKOP
CELL3.OUT_F2PLL0.CLKOS
CELL3.OUT_F4PLL0.CLKOS2
CELL3.OUT_F6PLL0.CLKOS3
CELL3.OUT_Q0PLL0.REFCLK
CELL3.OUT_Q2PLL0.LOCK
CELL3.OUT_Q4PLL0.INTLOCK
CELL3.OUT_Q6PLL0.PHASESRCSTAT

Tile PLL_NW

Cells: 4

Bel PLL0

ecp4 PLL_NW bel PLL0
PinDirectionWires
CLKFB2inputCELL3.IMUX_CLK1_DELAY
CLKOPoutputCELL3.OUT_F0
CLKOSoutputCELL3.OUT_F2
CLKOS2outputCELL3.OUT_F4
CLKOS3outputCELL3.OUT_F6
ENCLKOPinputCELL3.IMUX_D2
ENCLKOSinputCELL3.IMUX_A3
ENCLKOS2inputCELL3.IMUX_B3
ENCLKOS3inputCELL3.IMUX_C3
INTLOCKoutputCELL3.OUT_Q4
LOCKoutputCELL3.OUT_Q2
PHASEDIRinputCELL3.IMUX_D4
PHASELOADREGinputCELL3.IMUX_D3
PHASESEL0inputCELL3.IMUX_B4
PHASESEL1inputCELL3.IMUX_A4
PHASESRCSTAToutputCELL3.OUT_Q6
PHASESTEPinputCELL3.IMUX_C4
PLLWAKESYNCinputCELL3.IMUX_C2
REFCLKoutputCELL3.OUT_Q0
RSTinputCELL3.IMUX_B1
SMIADinputCELL2.IMUX_A4
SMICLKinputCELL2.IMUX_CLK1_DELAY
SMIRDinputCELL2.IMUX_B4
SMIRDATAoutputCELL2.OUT_F0
SMIRSTNinputCELL2.IMUX_A5
SMIWDATAinputCELL2.IMUX_D4
SMIWRinputCELL2.IMUX_C4
STDBYinputCELL3.IMUX_LSR0

Bel PLL1

ecp4 PLL_NW bel PLL1
PinDirectionWires
CLKFB2inputCELL1.IMUX_CLK1_DELAY
CLKOPoutputCELL1.OUT_F0
CLKOSoutputCELL1.OUT_F2
CLKOS2outputCELL1.OUT_F4
CLKOS3outputCELL1.OUT_F6
ENCLKOPinputCELL1.IMUX_D2
ENCLKOSinputCELL1.IMUX_A3
ENCLKOS2inputCELL1.IMUX_B3
ENCLKOS3inputCELL1.IMUX_C3
INTLOCKoutputCELL1.OUT_Q4
LOCKoutputCELL1.OUT_Q2
PHASEDIRinputCELL1.IMUX_D4
PHASELOADREGinputCELL1.IMUX_D3
PHASESEL0inputCELL1.IMUX_B4
PHASESEL1inputCELL1.IMUX_A4
PHASESRCSTAToutputCELL1.OUT_Q6
PHASESTEPinputCELL1.IMUX_C4
PLLWAKESYNCinputCELL1.IMUX_C2
REFCLKoutputCELL1.OUT_Q0
RSTinputCELL1.IMUX_B1
SMIADinputCELL0.IMUX_A4
SMICLKinputCELL0.IMUX_CLK1_DELAY
SMIRDinputCELL0.IMUX_B4
SMIRDATAoutputCELL0.OUT_F0
SMIRSTNinputCELL0.IMUX_A5
SMIWDATAinputCELL0.IMUX_D4
SMIWRinputCELL0.IMUX_C4
STDBYinputCELL1.IMUX_LSR0

Bel PLLREFCS0

ecp4 PLL_NW bel PLLREFCS0
PinDirectionWires
REFCLK0_2inputCELL3.IMUX_A0
REFCLK0_3inputCELL3.IMUX_CLK0_DELAY
REFCLK1_2inputCELL2.IMUX_A0
REFCLK1_3inputCELL2.IMUX_CLK0_DELAY
SELinputCELL3.IMUX_B2

Bel PLLREFCS1

ecp4 PLL_NW bel PLLREFCS1
PinDirectionWires
REFCLK0_2inputCELL1.IMUX_A0
REFCLK0_3inputCELL1.IMUX_CLK0_DELAY
REFCLK1_2inputCELL0.IMUX_A0
REFCLK1_3inputCELL0.IMUX_CLK0_DELAY
SELinputCELL1.IMUX_B2

Bel wires

ecp4 PLL_NW bel wires
WirePins
CELL0.IMUX_A0PLLREFCS1.REFCLK1_2
CELL0.IMUX_A4PLL1.SMIAD
CELL0.IMUX_A5PLL1.SMIRSTN
CELL0.IMUX_B4PLL1.SMIRD
CELL0.IMUX_C4PLL1.SMIWR
CELL0.IMUX_D4PLL1.SMIWDATA
CELL0.IMUX_CLK0_DELAYPLLREFCS1.REFCLK1_3
CELL0.IMUX_CLK1_DELAYPLL1.SMICLK
CELL0.OUT_F0PLL1.SMIRDATA
CELL1.IMUX_A0PLLREFCS1.REFCLK0_2
CELL1.IMUX_A3PLL1.ENCLKOS
CELL1.IMUX_A4PLL1.PHASESEL1
CELL1.IMUX_B1PLL1.RST
CELL1.IMUX_B2PLLREFCS1.SEL
CELL1.IMUX_B3PLL1.ENCLKOS2
CELL1.IMUX_B4PLL1.PHASESEL0
CELL1.IMUX_C2PLL1.PLLWAKESYNC
CELL1.IMUX_C3PLL1.ENCLKOS3
CELL1.IMUX_C4PLL1.PHASESTEP
CELL1.IMUX_D2PLL1.ENCLKOP
CELL1.IMUX_D3PLL1.PHASELOADREG
CELL1.IMUX_D4PLL1.PHASEDIR
CELL1.IMUX_LSR0PLL1.STDBY
CELL1.IMUX_CLK0_DELAYPLLREFCS1.REFCLK0_3
CELL1.IMUX_CLK1_DELAYPLL1.CLKFB2
CELL1.OUT_F0PLL1.CLKOP
CELL1.OUT_F2PLL1.CLKOS
CELL1.OUT_F4PLL1.CLKOS2
CELL1.OUT_F6PLL1.CLKOS3
CELL1.OUT_Q0PLL1.REFCLK
CELL1.OUT_Q2PLL1.LOCK
CELL1.OUT_Q4PLL1.INTLOCK
CELL1.OUT_Q6PLL1.PHASESRCSTAT
CELL2.IMUX_A0PLLREFCS0.REFCLK1_2
CELL2.IMUX_A4PLL0.SMIAD
CELL2.IMUX_A5PLL0.SMIRSTN
CELL2.IMUX_B4PLL0.SMIRD
CELL2.IMUX_C4PLL0.SMIWR
CELL2.IMUX_D4PLL0.SMIWDATA
CELL2.IMUX_CLK0_DELAYPLLREFCS0.REFCLK1_3
CELL2.IMUX_CLK1_DELAYPLL0.SMICLK
CELL2.OUT_F0PLL0.SMIRDATA
CELL3.IMUX_A0PLLREFCS0.REFCLK0_2
CELL3.IMUX_A3PLL0.ENCLKOS
CELL3.IMUX_A4PLL0.PHASESEL1
CELL3.IMUX_B1PLL0.RST
CELL3.IMUX_B2PLLREFCS0.SEL
CELL3.IMUX_B3PLL0.ENCLKOS2
CELL3.IMUX_B4PLL0.PHASESEL0
CELL3.IMUX_C2PLL0.PLLWAKESYNC
CELL3.IMUX_C3PLL0.ENCLKOS3
CELL3.IMUX_C4PLL0.PHASESTEP
CELL3.IMUX_D2PLL0.ENCLKOP
CELL3.IMUX_D3PLL0.PHASELOADREG
CELL3.IMUX_D4PLL0.PHASEDIR
CELL3.IMUX_LSR0PLL0.STDBY
CELL3.IMUX_CLK0_DELAYPLLREFCS0.REFCLK0_3
CELL3.IMUX_CLK1_DELAYPLL0.CLKFB2
CELL3.OUT_F0PLL0.CLKOP
CELL3.OUT_F2PLL0.CLKOS
CELL3.OUT_F4PLL0.CLKOS2
CELL3.OUT_F6PLL0.CLKOS3
CELL3.OUT_Q0PLL0.REFCLK
CELL3.OUT_Q2PLL0.LOCK
CELL3.OUT_Q4PLL0.INTLOCK
CELL3.OUT_Q6PLL0.PHASESRCSTAT

Tile PLL_NE

Cells: 4

Bel PLL0

ecp4 PLL_NE bel PLL0
PinDirectionWires
CLKFB2inputCELL3.IMUX_CLK1_DELAY
CLKOPoutputCELL3.OUT_F0
CLKOSoutputCELL3.OUT_F2
CLKOS2outputCELL3.OUT_F4
CLKOS3outputCELL3.OUT_F6
ENCLKOPinputCELL3.IMUX_D2
ENCLKOSinputCELL3.IMUX_A3
ENCLKOS2inputCELL3.IMUX_B3
ENCLKOS3inputCELL3.IMUX_C3
INTLOCKoutputCELL3.OUT_Q4
LOCKoutputCELL3.OUT_Q2
PHASEDIRinputCELL3.IMUX_D4
PHASELOADREGinputCELL3.IMUX_D3
PHASESEL0inputCELL3.IMUX_B4
PHASESEL1inputCELL3.IMUX_A4
PHASESRCSTAToutputCELL3.OUT_Q6
PHASESTEPinputCELL3.IMUX_C4
PLLWAKESYNCinputCELL3.IMUX_C2
REFCLKoutputCELL3.OUT_Q0
RSTinputCELL3.IMUX_B1
SMIADinputCELL2.IMUX_A4
SMICLKinputCELL2.IMUX_CLK1_DELAY
SMIRDinputCELL2.IMUX_B4
SMIRDATAoutputCELL2.OUT_F0
SMIRSTNinputCELL2.IMUX_A5
SMIWDATAinputCELL2.IMUX_D4
SMIWRinputCELL2.IMUX_C4
STDBYinputCELL3.IMUX_LSR0

Bel PLL1

ecp4 PLL_NE bel PLL1
PinDirectionWires
CLKFB2inputCELL1.IMUX_CLK1_DELAY
CLKOPoutputCELL1.OUT_F0
CLKOSoutputCELL1.OUT_F2
CLKOS2outputCELL1.OUT_F4
CLKOS3outputCELL1.OUT_F6
ENCLKOPinputCELL1.IMUX_D2
ENCLKOSinputCELL1.IMUX_A3
ENCLKOS2inputCELL1.IMUX_B3
ENCLKOS3inputCELL1.IMUX_C3
INTLOCKoutputCELL1.OUT_Q4
LOCKoutputCELL1.OUT_Q2
PHASEDIRinputCELL1.IMUX_D4
PHASELOADREGinputCELL1.IMUX_D3
PHASESEL0inputCELL1.IMUX_B4
PHASESEL1inputCELL1.IMUX_A4
PHASESRCSTAToutputCELL1.OUT_Q6
PHASESTEPinputCELL1.IMUX_C4
PLLWAKESYNCinputCELL1.IMUX_C2
REFCLKoutputCELL1.OUT_Q0
RSTinputCELL1.IMUX_B1
SMIADinputCELL0.IMUX_A4
SMICLKinputCELL0.IMUX_CLK1_DELAY
SMIRDinputCELL0.IMUX_B4
SMIRDATAoutputCELL0.OUT_F0
SMIRSTNinputCELL0.IMUX_A5
SMIWDATAinputCELL0.IMUX_D4
SMIWRinputCELL0.IMUX_C4
STDBYinputCELL1.IMUX_LSR0

Bel PLLREFCS0

ecp4 PLL_NE bel PLLREFCS0
PinDirectionWires
REFCLK0_2inputCELL3.IMUX_A0
REFCLK0_3inputCELL3.IMUX_CLK0_DELAY
REFCLK1_2inputCELL2.IMUX_A0
REFCLK1_3inputCELL2.IMUX_CLK0_DELAY
SELinputCELL3.IMUX_B2

Bel PLLREFCS1

ecp4 PLL_NE bel PLLREFCS1
PinDirectionWires
REFCLK0_2inputCELL1.IMUX_A0
REFCLK0_3inputCELL1.IMUX_CLK0_DELAY
REFCLK1_2inputCELL0.IMUX_A0
REFCLK1_3inputCELL0.IMUX_CLK0_DELAY
SELinputCELL1.IMUX_B2

Bel wires

ecp4 PLL_NE bel wires
WirePins
CELL0.IMUX_A0PLLREFCS1.REFCLK1_2
CELL0.IMUX_A4PLL1.SMIAD
CELL0.IMUX_A5PLL1.SMIRSTN
CELL0.IMUX_B4PLL1.SMIRD
CELL0.IMUX_C4PLL1.SMIWR
CELL0.IMUX_D4PLL1.SMIWDATA
CELL0.IMUX_CLK0_DELAYPLLREFCS1.REFCLK1_3
CELL0.IMUX_CLK1_DELAYPLL1.SMICLK
CELL0.OUT_F0PLL1.SMIRDATA
CELL1.IMUX_A0PLLREFCS1.REFCLK0_2
CELL1.IMUX_A3PLL1.ENCLKOS
CELL1.IMUX_A4PLL1.PHASESEL1
CELL1.IMUX_B1PLL1.RST
CELL1.IMUX_B2PLLREFCS1.SEL
CELL1.IMUX_B3PLL1.ENCLKOS2
CELL1.IMUX_B4PLL1.PHASESEL0
CELL1.IMUX_C2PLL1.PLLWAKESYNC
CELL1.IMUX_C3PLL1.ENCLKOS3
CELL1.IMUX_C4PLL1.PHASESTEP
CELL1.IMUX_D2PLL1.ENCLKOP
CELL1.IMUX_D3PLL1.PHASELOADREG
CELL1.IMUX_D4PLL1.PHASEDIR
CELL1.IMUX_LSR0PLL1.STDBY
CELL1.IMUX_CLK0_DELAYPLLREFCS1.REFCLK0_3
CELL1.IMUX_CLK1_DELAYPLL1.CLKFB2
CELL1.OUT_F0PLL1.CLKOP
CELL1.OUT_F2PLL1.CLKOS
CELL1.OUT_F4PLL1.CLKOS2
CELL1.OUT_F6PLL1.CLKOS3
CELL1.OUT_Q0PLL1.REFCLK
CELL1.OUT_Q2PLL1.LOCK
CELL1.OUT_Q4PLL1.INTLOCK
CELL1.OUT_Q6PLL1.PHASESRCSTAT
CELL2.IMUX_A0PLLREFCS0.REFCLK1_2
CELL2.IMUX_A4PLL0.SMIAD
CELL2.IMUX_A5PLL0.SMIRSTN
CELL2.IMUX_B4PLL0.SMIRD
CELL2.IMUX_C4PLL0.SMIWR
CELL2.IMUX_D4PLL0.SMIWDATA
CELL2.IMUX_CLK0_DELAYPLLREFCS0.REFCLK1_3
CELL2.IMUX_CLK1_DELAYPLL0.SMICLK
CELL2.OUT_F0PLL0.SMIRDATA
CELL3.IMUX_A0PLLREFCS0.REFCLK0_2
CELL3.IMUX_A3PLL0.ENCLKOS
CELL3.IMUX_A4PLL0.PHASESEL1
CELL3.IMUX_B1PLL0.RST
CELL3.IMUX_B2PLLREFCS0.SEL
CELL3.IMUX_B3PLL0.ENCLKOS2
CELL3.IMUX_B4PLL0.PHASESEL0
CELL3.IMUX_C2PLL0.PLLWAKESYNC
CELL3.IMUX_C3PLL0.ENCLKOS3
CELL3.IMUX_C4PLL0.PHASESTEP
CELL3.IMUX_D2PLL0.ENCLKOP
CELL3.IMUX_D3PLL0.PHASELOADREG
CELL3.IMUX_D4PLL0.PHASEDIR
CELL3.IMUX_LSR0PLL0.STDBY
CELL3.IMUX_CLK0_DELAYPLLREFCS0.REFCLK0_3
CELL3.IMUX_CLK1_DELAYPLL0.CLKFB2
CELL3.OUT_F0PLL0.CLKOP
CELL3.OUT_F2PLL0.CLKOS
CELL3.OUT_F4PLL0.CLKOS2
CELL3.OUT_F6PLL0.CLKOS3
CELL3.OUT_Q0PLL0.REFCLK
CELL3.OUT_Q2PLL0.LOCK
CELL3.OUT_Q4PLL0.INTLOCK
CELL3.OUT_Q6PLL0.PHASESRCSTAT