SERDES
Tile SERDES
Cells: 12
Bel SERDES
| Pin | Direction | Wires |
|---|---|---|
| CH0_FFC_CDR_EN_BITSLIP | input | TCELL1:IMUX_A1 |
| CH0_FFC_DIV11_MODE_RX | input | TCELL1:IMUX_C0 |
| CH0_FFC_DIV11_MODE_TX | input | TCELL0:IMUX_D2 |
| CH0_FFC_EI_EN | input | TCELL0:IMUX_B5 |
| CH0_FFC_ENABLE_CGALIGN | input | TCELL0:IMUX_C0 |
| CH0_FFC_FB_LOOPBACK | input | TCELL0:IMUX_C2 |
| CH0_FFC_LANE_RX_RST | input | TCELL1:IMUX_A5 |
| CH0_FFC_LANE_TX_RST | input | TCELL0:IMUX_C4 |
| CH0_FFC_LDR_CORE2TX_EN | input | TCELL0:IMUX_A5 |
| CH0_FFC_PCIE_CT | input | TCELL0:IMUX_D4 |
| CH0_FFC_PCIE_DET_EN | input | TCELL0:IMUX_B3 |
| CH0_FFC_PFIFO_CLR | input | TCELL1:IMUX_C4 |
| CH0_FFC_RATE_MODE_RX | input | TCELL0:IMUX_A7 |
| CH0_FFC_RATE_MODE_TX | input | TCELL0:IMUX_D6 |
| CH0_FFC_RRST | input | TCELL1:IMUX_A3 |
| CH0_FFC_RXPWDNB | input | TCELL0:IMUX_A1 |
| CH0_FFC_RX_GEAR_MODE | input | TCELL2:IMUX_A5 |
| CH0_FFC_SB_INV_RX | input | TCELL1:IMUX_C2 |
| CH0_FFC_SB_PFIFO_LP | input | TCELL0:IMUX_A3 |
| CH0_FFC_SIGNAL_DETECT | input | TCELL1:IMUX_A7 |
| CH0_FFC_TXPWDNB | input | TCELL0:IMUX_B1 |
| CH0_FFC_TX_GEAR_MODE | input | TCELL0:IMUX_C6 |
| CH0_FFS_CC_OVERRUN | output | TCELL1:OUT_Q0 |
| CH0_FFS_CC_UNDERRUN | output | TCELL4:OUT_Q4 |
| CH0_FFS_LS_SYNC_STATUS | output | TCELL2:OUT_Q1 |
| CH0_FFS_PCIE_CON | output | TCELL0:OUT_F2 |
| CH0_FFS_PCIE_DONE | output | TCELL0:OUT_F1 |
| CH0_FFS_RLOL | output | TCELL1:OUT_Q1 |
| CH0_FFS_RLOS | output | TCELL2:OUT_Q0 |
| CH0_FFS_RXFBFIFO_ERROR | output | TCELL4:OUT_Q5 |
| CH0_FFS_SKP_ADDED | output | TCELL0:OUT_F7 |
| CH0_FFS_SKP_DELETED | output | TCELL0:OUT_Q4 |
| CH0_FFS_TXFBFIFO_ERROR | output | TCELL0:OUT_F4 |
| CH0_FF_EBRD_CLK | input | TCELL0:IMUX_CLK0 |
| CH0_FF_RXI_CLK | input | TCELL3:IMUX_CLK0 |
| CH0_FF_RX_D_0 | output | TCELL1:OUT_F0 |
| CH0_FF_RX_D_1 | output | TCELL1:OUT_F1 |
| CH0_FF_RX_D_10 | output | TCELL2:OUT_F2 |
| CH0_FF_RX_D_11 | output | TCELL2:OUT_F3 |
| CH0_FF_RX_D_12 | output | TCELL2:OUT_F4 |
| CH0_FF_RX_D_13 | output | TCELL2:OUT_F5 |
| CH0_FF_RX_D_14 | output | TCELL2:OUT_F6 |
| CH0_FF_RX_D_15 | output | TCELL2:OUT_F7 |
| CH0_FF_RX_D_16 | output | TCELL3:OUT_F0 |
| CH0_FF_RX_D_17 | output | TCELL3:OUT_F1 |
| CH0_FF_RX_D_18 | output | TCELL3:OUT_F2 |
| CH0_FF_RX_D_19 | output | TCELL3:OUT_F3 |
| CH0_FF_RX_D_2 | output | TCELL1:OUT_F2 |
| CH0_FF_RX_D_20 | output | TCELL3:OUT_F4 |
| CH0_FF_RX_D_21 | output | TCELL3:OUT_F5 |
| CH0_FF_RX_D_22 | output | TCELL3:OUT_F6 |
| CH0_FF_RX_D_23 | output | TCELL3:OUT_F7 |
| CH0_FF_RX_D_3 | output | TCELL1:OUT_F3 |
| CH0_FF_RX_D_4 | output | TCELL1:OUT_F4 |
| CH0_FF_RX_D_5 | output | TCELL1:OUT_F5 |
| CH0_FF_RX_D_6 | output | TCELL1:OUT_F6 |
| CH0_FF_RX_D_7 | output | TCELL1:OUT_F7 |
| CH0_FF_RX_D_8 | output | TCELL2:OUT_F0 |
| CH0_FF_RX_D_9 | output | TCELL2:OUT_F1 |
| CH0_FF_RX_F_CLK | output | TCELL3:OUT_Q0 |
| CH0_FF_RX_H_CLK | output | TCELL3:OUT_Q1 |
| CH0_FF_TXI_CLK | input | TCELL0:IMUX_CLK1 |
| CH0_FF_TX_D_0 | input | TCELL1:IMUX_D0 |
| CH0_FF_TX_D_1 | input | TCELL1:IMUX_B1 |
| CH0_FF_TX_D_10 | input | TCELL2:IMUX_D2 |
| CH0_FF_TX_D_11 | input | TCELL2:IMUX_B3 |
| CH0_FF_TX_D_12 | input | TCELL2:IMUX_D4 |
| CH0_FF_TX_D_13 | input | TCELL2:IMUX_B5 |
| CH0_FF_TX_D_14 | input | TCELL2:IMUX_D6 |
| CH0_FF_TX_D_15 | input | TCELL2:IMUX_B7 |
| CH0_FF_TX_D_16 | input | TCELL3:IMUX_D0 |
| CH0_FF_TX_D_17 | input | TCELL3:IMUX_B1 |
| CH0_FF_TX_D_18 | input | TCELL3:IMUX_D2 |
| CH0_FF_TX_D_19 | input | TCELL3:IMUX_B3 |
| CH0_FF_TX_D_2 | input | TCELL1:IMUX_D2 |
| CH0_FF_TX_D_20 | input | TCELL3:IMUX_D4 |
| CH0_FF_TX_D_21 | input | TCELL3:IMUX_B5 |
| CH0_FF_TX_D_22 | input | TCELL3:IMUX_D6 |
| CH0_FF_TX_D_23 | input | TCELL3:IMUX_B7 |
| CH0_FF_TX_D_3 | input | TCELL1:IMUX_B3 |
| CH0_FF_TX_D_4 | input | TCELL1:IMUX_D4 |
| CH0_FF_TX_D_5 | input | TCELL1:IMUX_B5 |
| CH0_FF_TX_D_6 | input | TCELL1:IMUX_D6 |
| CH0_FF_TX_D_7 | input | TCELL1:IMUX_B7 |
| CH0_FF_TX_D_8 | input | TCELL2:IMUX_D0 |
| CH0_FF_TX_D_9 | input | TCELL2:IMUX_B1 |
| CH0_FF_TX_F_CLK | output | TCELL0:OUT_Q1 |
| CH0_FF_TX_H_CLK | output | TCELL0:OUT_Q0 |
| CH0_LDR_CORE2TX | input | TCELL0:IMUX_B7 |
| CH0_LDR_RX2CORE | output | TCELL0:OUT_F6 |
| CH0_RX_REFCLK | input | TCELL4:IMUX_CLK0 |
| CH0_SCIEN | input | TCELL2:IMUX_C6 |
| CH0_SCISEL | input | TCELL2:IMUX_A7 |
| CH1_FFC_CDR_EN_BITSLIP | input | TCELL5:IMUX_A3 |
| CH1_FFC_DIV11_MODE_RX | input | TCELL6:IMUX_D0 |
| CH1_FFC_DIV11_MODE_TX | input | TCELL7:IMUX_D6 |
| CH1_FFC_EI_EN | input | TCELL7:IMUX_B3 |
| CH1_FFC_ENABLE_CGALIGN | input | TCELL6:IMUX_B7 |
| CH1_FFC_FB_LOOPBACK | input | TCELL6:IMUX_B5 |
| CH1_FFC_LANE_RX_RST | input | TCELL6:IMUX_D2 |
| CH1_FFC_LANE_TX_RST | input | TCELL7:IMUX_D0 |
| CH1_FFC_LDR_CORE2TX_EN | input | TCELL6:IMUX_A7 |
| CH1_FFC_PCIE_CT | input | TCELL7:IMUX_D4 |
| CH1_FFC_PCIE_DET_EN | input | TCELL7:IMUX_B5 |
| CH1_FFC_PFIFO_CLR | input | TCELL6:IMUX_B3 |
| CH1_FFC_RATE_MODE_RX | input | TCELL6:IMUX_C4 |
| CH1_FFC_RATE_MODE_TX | input | TCELL7:IMUX_D2 |
| CH1_FFC_RRST | input | TCELL6:IMUX_C0 |
| CH1_FFC_RXPWDNB | input | TCELL6:IMUX_D6 |
| CH1_FFC_RX_GEAR_MODE | input | TCELL5:IMUX_A1 |
| CH1_FFC_SB_INV_RX | input | TCELL5:IMUX_C2 |
| CH1_FFC_SB_PFIFO_LP | input | TCELL6:IMUX_D4 |
| CH1_FFC_SIGNAL_DETECT | input | TCELL6:IMUX_B1 |
| CH1_FFC_TXPWDNB | input | TCELL7:IMUX_B7 |
| CH1_FFC_TX_GEAR_MODE | input | TCELL6:IMUX_C6 |
| CH1_FFS_CC_OVERRUN | output | TCELL7:OUT_F6 |
| CH1_FFS_CC_UNDERRUN | output | TCELL7:OUT_F2 |
| CH1_FFS_LS_SYNC_STATUS | output | TCELL7:OUT_F3 |
| CH1_FFS_PCIE_CON | output | TCELL11:OUT_F3 |
| CH1_FFS_PCIE_DONE | output | TCELL11:OUT_F4 |
| CH1_FFS_RLOL | output | TCELL7:OUT_F5 |
| CH1_FFS_RLOS | output | TCELL7:OUT_F4 |
| CH1_FFS_RXFBFIFO_ERROR | output | TCELL7:OUT_F1 |
| CH1_FFS_SKP_ADDED | output | TCELL10:OUT_Q1 |
| CH1_FFS_SKP_DELETED | output | TCELL10:OUT_Q0 |
| CH1_FFS_TXFBFIFO_ERROR | output | TCELL11:OUT_F2 |
| CH1_FF_EBRD_CLK | input | TCELL7:IMUX_CLK0 |
| CH1_FF_RXI_CLK | input | TCELL6:IMUX_CLK0 |
| CH1_FF_RX_D_0 | output | TCELL8:OUT_F0 |
| CH1_FF_RX_D_1 | output | TCELL8:OUT_F1 |
| CH1_FF_RX_D_10 | output | TCELL9:OUT_F2 |
| CH1_FF_RX_D_11 | output | TCELL9:OUT_F3 |
| CH1_FF_RX_D_12 | output | TCELL9:OUT_F4 |
| CH1_FF_RX_D_13 | output | TCELL9:OUT_F5 |
| CH1_FF_RX_D_14 | output | TCELL9:OUT_F6 |
| CH1_FF_RX_D_15 | output | TCELL9:OUT_F7 |
| CH1_FF_RX_D_16 | output | TCELL10:OUT_F0 |
| CH1_FF_RX_D_17 | output | TCELL10:OUT_F1 |
| CH1_FF_RX_D_18 | output | TCELL10:OUT_F2 |
| CH1_FF_RX_D_19 | output | TCELL10:OUT_F3 |
| CH1_FF_RX_D_2 | output | TCELL8:OUT_F2 |
| CH1_FF_RX_D_20 | output | TCELL10:OUT_F4 |
| CH1_FF_RX_D_21 | output | TCELL10:OUT_F5 |
| CH1_FF_RX_D_22 | output | TCELL10:OUT_F6 |
| CH1_FF_RX_D_23 | output | TCELL10:OUT_F7 |
| CH1_FF_RX_D_3 | output | TCELL8:OUT_F3 |
| CH1_FF_RX_D_4 | output | TCELL8:OUT_F4 |
| CH1_FF_RX_D_5 | output | TCELL8:OUT_F5 |
| CH1_FF_RX_D_6 | output | TCELL8:OUT_F6 |
| CH1_FF_RX_D_7 | output | TCELL8:OUT_F7 |
| CH1_FF_RX_D_8 | output | TCELL9:OUT_F0 |
| CH1_FF_RX_D_9 | output | TCELL9:OUT_F1 |
| CH1_FF_RX_F_CLK | output | TCELL6:OUT_Q0 |
| CH1_FF_RX_H_CLK | output | TCELL6:OUT_Q1 |
| CH1_FF_TXI_CLK | input | TCELL7:IMUX_CLK1 |
| CH1_FF_TX_D_0 | input | TCELL8:IMUX_D0 |
| CH1_FF_TX_D_1 | input | TCELL8:IMUX_B1 |
| CH1_FF_TX_D_10 | input | TCELL9:IMUX_D2 |
| CH1_FF_TX_D_11 | input | TCELL9:IMUX_B3 |
| CH1_FF_TX_D_12 | input | TCELL9:IMUX_D4 |
| CH1_FF_TX_D_13 | input | TCELL9:IMUX_B5 |
| CH1_FF_TX_D_14 | input | TCELL9:IMUX_D6 |
| CH1_FF_TX_D_15 | input | TCELL9:IMUX_B7 |
| CH1_FF_TX_D_16 | input | TCELL10:IMUX_D0 |
| CH1_FF_TX_D_17 | input | TCELL10:IMUX_B1 |
| CH1_FF_TX_D_18 | input | TCELL10:IMUX_D2 |
| CH1_FF_TX_D_19 | input | TCELL10:IMUX_B3 |
| CH1_FF_TX_D_2 | input | TCELL8:IMUX_D2 |
| CH1_FF_TX_D_20 | input | TCELL10:IMUX_D4 |
| CH1_FF_TX_D_21 | input | TCELL10:IMUX_B5 |
| CH1_FF_TX_D_22 | input | TCELL10:IMUX_D6 |
| CH1_FF_TX_D_23 | input | TCELL10:IMUX_B7 |
| CH1_FF_TX_D_3 | input | TCELL8:IMUX_B3 |
| CH1_FF_TX_D_4 | input | TCELL8:IMUX_D4 |
| CH1_FF_TX_D_5 | input | TCELL8:IMUX_B5 |
| CH1_FF_TX_D_6 | input | TCELL8:IMUX_D6 |
| CH1_FF_TX_D_7 | input | TCELL8:IMUX_B7 |
| CH1_FF_TX_D_8 | input | TCELL9:IMUX_D0 |
| CH1_FF_TX_D_9 | input | TCELL9:IMUX_B1 |
| CH1_FF_TX_F_CLK | output | TCELL7:OUT_Q0 |
| CH1_FF_TX_H_CLK | output | TCELL7:OUT_Q1 |
| CH1_LDR_CORE2TX | input | TCELL7:IMUX_B1 |
| CH1_LDR_RX2CORE | output | TCELL11:OUT_F0 |
| CH1_RX_REFCLK | input | TCELL6:IMUX_CLK1 |
| CH1_SCIEN | input | TCELL3:IMUX_C2 |
| CH1_SCISEL | input | TCELL3:IMUX_A3 |
| D_CIN0 | input | TCELL5:IMUX_D2 |
| D_CIN1 | input | TCELL5:IMUX_B3 |
| D_CIN10 | input | TCELL5:IMUX_B1 |
| D_CIN11 | input | TCELL5:IMUX_D0 |
| D_CIN2 | input | TCELL5:IMUX_D4 |
| D_CIN3 | input | TCELL5:IMUX_B5 |
| D_CIN4 | input | TCELL5:IMUX_D6 |
| D_CIN5 | input | TCELL5:IMUX_B7 |
| D_CIN6 | input | TCELL5:IMUX_C4 |
| D_CIN7 | input | TCELL5:IMUX_A5 |
| D_CIN8 | input | TCELL5:IMUX_C6 |
| D_CIN9 | input | TCELL5:IMUX_A7 |
| D_COUT0 | output | TCELL5:OUT_F5 |
| D_COUT1 | output | TCELL11:OUT_F6 |
| D_COUT10 | output | TCELL4:OUT_F7 |
| D_COUT11 | output | TCELL5:OUT_F0 |
| D_COUT12 | output | TCELL5:OUT_F1 |
| D_COUT13 | output | TCELL5:OUT_F2 |
| D_COUT14 | output | TCELL5:OUT_F3 |
| D_COUT15 | output | TCELL5:OUT_F4 |
| D_COUT16 | output | TCELL4:OUT_F2 |
| D_COUT17 | output | TCELL4:OUT_Q0 |
| D_COUT18 | output | TCELL4:OUT_Q1 |
| D_COUT19 | output | TCELL4:OUT_F1 |
| D_COUT2 | output | TCELL5:OUT_F6 |
| D_COUT3 | output | TCELL5:OUT_F7 |
| D_COUT4 | output | TCELL5:OUT_Q0 |
| D_COUT5 | output | TCELL5:OUT_Q1 |
| D_COUT6 | output | TCELL4:OUT_F3 |
| D_COUT7 | output | TCELL4:OUT_F4 |
| D_COUT8 | output | TCELL4:OUT_F5 |
| D_COUT9 | output | TCELL4:OUT_F6 |
| D_CYAWSTN | input | TCELL3:IMUX_C0 |
| D_FFC_DUAL_RST | input | TCELL4:IMUX_C2 |
| D_FFC_MACROPDB | input | TCELL11:IMUX_D2 |
| D_FFC_MACRO_RST | input | TCELL11:IMUX_B1 |
| D_FFC_SYNC_TOGGLE | input | TCELL11:IMUX_B5 |
| D_FFC_TRST | input | TCELL11:IMUX_B3 |
| D_FFS_PLOL | output | TCELL11:OUT_Q0 |
| D_REFCLKI | input | TCELL11:IMUX_CLK0 |
| D_SCAN_ENABLE | input | TCELL4:IMUX_A7 |
| D_SCAN_IN_0 | input | TCELL11:IMUX_D0 |
| D_SCAN_IN_1 | input | TCELL6:IMUX_A5 |
| D_SCAN_IN_2 | input | TCELL5:IMUX_C0 |
| D_SCAN_IN_3 | input | TCELL2:IMUX_C4 |
| D_SCAN_IN_4 | input | TCELL1:IMUX_C6 |
| D_SCAN_IN_5 | input | TCELL0:IMUX_D0 |
| D_SCAN_IN_6 | input | TCELL3:IMUX_C6 |
| D_SCAN_IN_7 | input | TCELL3:IMUX_A7 |
| D_SCAN_MODE | input | TCELL4:IMUX_C0 |
| D_SCAN_OUT_0 | output | TCELL11:OUT_F7 |
| D_SCAN_OUT_1 | output | TCELL0:OUT_F0 |
| D_SCAN_OUT_2 | output | TCELL0:OUT_F3 |
| D_SCAN_OUT_3 | output | TCELL11:OUT_F5 |
| D_SCAN_OUT_4 | output | TCELL7:OUT_F7 |
| D_SCAN_OUT_5 | output | TCELL0:OUT_F5 |
| D_SCAN_OUT_6 | output | TCELL5:OUT_Q4 |
| D_SCAN_OUT_7 | output | TCELL11:OUT_F1 |
| D_SCAN_RESET | input | TCELL4:IMUX_A1 |
| D_SCIADDR0 | input | TCELL2:IMUX_C0 |
| D_SCIADDR1 | input | TCELL2:IMUX_A1 |
| D_SCIADDR2 | input | TCELL2:IMUX_C2 |
| D_SCIADDR3 | input | TCELL2:IMUX_A3 |
| D_SCIADDR4 | input | TCELL3:IMUX_C4 |
| D_SCIADDR5 | input | TCELL3:IMUX_A5 |
| D_SCIENAUX | input | TCELL4:IMUX_A5 |
| D_SCIINT | output | TCELL5:OUT_Q5 |
| D_SCIRD | input | TCELL4:IMUX_C6 |
| D_SCIRDATA0 | output | TCELL6:OUT_F0 |
| D_SCIRDATA1 | output | TCELL6:OUT_F1 |
| D_SCIRDATA2 | output | TCELL6:OUT_F2 |
| D_SCIRDATA3 | output | TCELL6:OUT_F3 |
| D_SCIRDATA4 | output | TCELL6:OUT_F4 |
| D_SCIRDATA5 | output | TCELL6:OUT_F5 |
| D_SCIRDATA6 | output | TCELL6:OUT_F6 |
| D_SCIRDATA7 | output | TCELL6:OUT_F7 |
| D_SCISELAUX | input | TCELL4:IMUX_C4 |
| D_SCIWDATA0 | input | TCELL4:IMUX_D0 |
| D_SCIWDATA1 | input | TCELL4:IMUX_B1 |
| D_SCIWDATA2 | input | TCELL4:IMUX_D2 |
| D_SCIWDATA3 | input | TCELL4:IMUX_B3 |
| D_SCIWDATA4 | input | TCELL4:IMUX_D4 |
| D_SCIWDATA5 | input | TCELL4:IMUX_B5 |
| D_SCIWDATA6 | input | TCELL4:IMUX_D6 |
| D_SCIWDATA7 | input | TCELL4:IMUX_B7 |
| D_SCIWSTN | input | TCELL3:IMUX_A1 |
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:IMUX_A1 | SERDES.CH0_FFC_RXPWDNB |
| TCELL0:IMUX_A3 | SERDES.CH0_FFC_SB_PFIFO_LP |
| TCELL0:IMUX_A5 | SERDES.CH0_FFC_LDR_CORE2TX_EN |
| TCELL0:IMUX_A7 | SERDES.CH0_FFC_RATE_MODE_RX |
| TCELL0:IMUX_B1 | SERDES.CH0_FFC_TXPWDNB |
| TCELL0:IMUX_B3 | SERDES.CH0_FFC_PCIE_DET_EN |
| TCELL0:IMUX_B5 | SERDES.CH0_FFC_EI_EN |
| TCELL0:IMUX_B7 | SERDES.CH0_LDR_CORE2TX |
| TCELL0:IMUX_C0 | SERDES.CH0_FFC_ENABLE_CGALIGN |
| TCELL0:IMUX_C2 | SERDES.CH0_FFC_FB_LOOPBACK |
| TCELL0:IMUX_C4 | SERDES.CH0_FFC_LANE_TX_RST |
| TCELL0:IMUX_C6 | SERDES.CH0_FFC_TX_GEAR_MODE |
| TCELL0:IMUX_D0 | SERDES.D_SCAN_IN_5 |
| TCELL0:IMUX_D2 | SERDES.CH0_FFC_DIV11_MODE_TX |
| TCELL0:IMUX_D4 | SERDES.CH0_FFC_PCIE_CT |
| TCELL0:IMUX_D6 | SERDES.CH0_FFC_RATE_MODE_TX |
| TCELL0:IMUX_CLK0 | SERDES.CH0_FF_EBRD_CLK |
| TCELL0:IMUX_CLK1 | SERDES.CH0_FF_TXI_CLK |
| TCELL0:OUT_F0 | SERDES.D_SCAN_OUT_1 |
| TCELL0:OUT_F1 | SERDES.CH0_FFS_PCIE_DONE |
| TCELL0:OUT_F2 | SERDES.CH0_FFS_PCIE_CON |
| TCELL0:OUT_F3 | SERDES.D_SCAN_OUT_2 |
| TCELL0:OUT_F4 | SERDES.CH0_FFS_TXFBFIFO_ERROR |
| TCELL0:OUT_F5 | SERDES.D_SCAN_OUT_5 |
| TCELL0:OUT_F6 | SERDES.CH0_LDR_RX2CORE |
| TCELL0:OUT_F7 | SERDES.CH0_FFS_SKP_ADDED |
| TCELL0:OUT_Q0 | SERDES.CH0_FF_TX_H_CLK |
| TCELL0:OUT_Q1 | SERDES.CH0_FF_TX_F_CLK |
| TCELL0:OUT_Q4 | SERDES.CH0_FFS_SKP_DELETED |
| TCELL1:IMUX_A1 | SERDES.CH0_FFC_CDR_EN_BITSLIP |
| TCELL1:IMUX_A3 | SERDES.CH0_FFC_RRST |
| TCELL1:IMUX_A5 | SERDES.CH0_FFC_LANE_RX_RST |
| TCELL1:IMUX_A7 | SERDES.CH0_FFC_SIGNAL_DETECT |
| TCELL1:IMUX_B1 | SERDES.CH0_FF_TX_D_1 |
| TCELL1:IMUX_B3 | SERDES.CH0_FF_TX_D_3 |
| TCELL1:IMUX_B5 | SERDES.CH0_FF_TX_D_5 |
| TCELL1:IMUX_B7 | SERDES.CH0_FF_TX_D_7 |
| TCELL1:IMUX_C0 | SERDES.CH0_FFC_DIV11_MODE_RX |
| TCELL1:IMUX_C2 | SERDES.CH0_FFC_SB_INV_RX |
| TCELL1:IMUX_C4 | SERDES.CH0_FFC_PFIFO_CLR |
| TCELL1:IMUX_C6 | SERDES.D_SCAN_IN_4 |
| TCELL1:IMUX_D0 | SERDES.CH0_FF_TX_D_0 |
| TCELL1:IMUX_D2 | SERDES.CH0_FF_TX_D_2 |
| TCELL1:IMUX_D4 | SERDES.CH0_FF_TX_D_4 |
| TCELL1:IMUX_D6 | SERDES.CH0_FF_TX_D_6 |
| TCELL1:OUT_F0 | SERDES.CH0_FF_RX_D_0 |
| TCELL1:OUT_F1 | SERDES.CH0_FF_RX_D_1 |
| TCELL1:OUT_F2 | SERDES.CH0_FF_RX_D_2 |
| TCELL1:OUT_F3 | SERDES.CH0_FF_RX_D_3 |
| TCELL1:OUT_F4 | SERDES.CH0_FF_RX_D_4 |
| TCELL1:OUT_F5 | SERDES.CH0_FF_RX_D_5 |
| TCELL1:OUT_F6 | SERDES.CH0_FF_RX_D_6 |
| TCELL1:OUT_F7 | SERDES.CH0_FF_RX_D_7 |
| TCELL1:OUT_Q0 | SERDES.CH0_FFS_CC_OVERRUN |
| TCELL1:OUT_Q1 | SERDES.CH0_FFS_RLOL |
| TCELL2:IMUX_A1 | SERDES.D_SCIADDR1 |
| TCELL2:IMUX_A3 | SERDES.D_SCIADDR3 |
| TCELL2:IMUX_A5 | SERDES.CH0_FFC_RX_GEAR_MODE |
| TCELL2:IMUX_A7 | SERDES.CH0_SCISEL |
| TCELL2:IMUX_B1 | SERDES.CH0_FF_TX_D_9 |
| TCELL2:IMUX_B3 | SERDES.CH0_FF_TX_D_11 |
| TCELL2:IMUX_B5 | SERDES.CH0_FF_TX_D_13 |
| TCELL2:IMUX_B7 | SERDES.CH0_FF_TX_D_15 |
| TCELL2:IMUX_C0 | SERDES.D_SCIADDR0 |
| TCELL2:IMUX_C2 | SERDES.D_SCIADDR2 |
| TCELL2:IMUX_C4 | SERDES.D_SCAN_IN_3 |
| TCELL2:IMUX_C6 | SERDES.CH0_SCIEN |
| TCELL2:IMUX_D0 | SERDES.CH0_FF_TX_D_8 |
| TCELL2:IMUX_D2 | SERDES.CH0_FF_TX_D_10 |
| TCELL2:IMUX_D4 | SERDES.CH0_FF_TX_D_12 |
| TCELL2:IMUX_D6 | SERDES.CH0_FF_TX_D_14 |
| TCELL2:OUT_F0 | SERDES.CH0_FF_RX_D_8 |
| TCELL2:OUT_F1 | SERDES.CH0_FF_RX_D_9 |
| TCELL2:OUT_F2 | SERDES.CH0_FF_RX_D_10 |
| TCELL2:OUT_F3 | SERDES.CH0_FF_RX_D_11 |
| TCELL2:OUT_F4 | SERDES.CH0_FF_RX_D_12 |
| TCELL2:OUT_F5 | SERDES.CH0_FF_RX_D_13 |
| TCELL2:OUT_F6 | SERDES.CH0_FF_RX_D_14 |
| TCELL2:OUT_F7 | SERDES.CH0_FF_RX_D_15 |
| TCELL2:OUT_Q0 | SERDES.CH0_FFS_RLOS |
| TCELL2:OUT_Q1 | SERDES.CH0_FFS_LS_SYNC_STATUS |
| TCELL3:IMUX_A1 | SERDES.D_SCIWSTN |
| TCELL3:IMUX_A3 | SERDES.CH1_SCISEL |
| TCELL3:IMUX_A5 | SERDES.D_SCIADDR5 |
| TCELL3:IMUX_A7 | SERDES.D_SCAN_IN_7 |
| TCELL3:IMUX_B1 | SERDES.CH0_FF_TX_D_17 |
| TCELL3:IMUX_B3 | SERDES.CH0_FF_TX_D_19 |
| TCELL3:IMUX_B5 | SERDES.CH0_FF_TX_D_21 |
| TCELL3:IMUX_B7 | SERDES.CH0_FF_TX_D_23 |
| TCELL3:IMUX_C0 | SERDES.D_CYAWSTN |
| TCELL3:IMUX_C2 | SERDES.CH1_SCIEN |
| TCELL3:IMUX_C4 | SERDES.D_SCIADDR4 |
| TCELL3:IMUX_C6 | SERDES.D_SCAN_IN_6 |
| TCELL3:IMUX_D0 | SERDES.CH0_FF_TX_D_16 |
| TCELL3:IMUX_D2 | SERDES.CH0_FF_TX_D_18 |
| TCELL3:IMUX_D4 | SERDES.CH0_FF_TX_D_20 |
| TCELL3:IMUX_D6 | SERDES.CH0_FF_TX_D_22 |
| TCELL3:IMUX_CLK0 | SERDES.CH0_FF_RXI_CLK |
| TCELL3:OUT_F0 | SERDES.CH0_FF_RX_D_16 |
| TCELL3:OUT_F1 | SERDES.CH0_FF_RX_D_17 |
| TCELL3:OUT_F2 | SERDES.CH0_FF_RX_D_18 |
| TCELL3:OUT_F3 | SERDES.CH0_FF_RX_D_19 |
| TCELL3:OUT_F4 | SERDES.CH0_FF_RX_D_20 |
| TCELL3:OUT_F5 | SERDES.CH0_FF_RX_D_21 |
| TCELL3:OUT_F6 | SERDES.CH0_FF_RX_D_22 |
| TCELL3:OUT_F7 | SERDES.CH0_FF_RX_D_23 |
| TCELL3:OUT_Q0 | SERDES.CH0_FF_RX_F_CLK |
| TCELL3:OUT_Q1 | SERDES.CH0_FF_RX_H_CLK |
| TCELL4:IMUX_A1 | SERDES.D_SCAN_RESET |
| TCELL4:IMUX_A5 | SERDES.D_SCIENAUX |
| TCELL4:IMUX_A7 | SERDES.D_SCAN_ENABLE |
| TCELL4:IMUX_B1 | SERDES.D_SCIWDATA1 |
| TCELL4:IMUX_B3 | SERDES.D_SCIWDATA3 |
| TCELL4:IMUX_B5 | SERDES.D_SCIWDATA5 |
| TCELL4:IMUX_B7 | SERDES.D_SCIWDATA7 |
| TCELL4:IMUX_C0 | SERDES.D_SCAN_MODE |
| TCELL4:IMUX_C2 | SERDES.D_FFC_DUAL_RST |
| TCELL4:IMUX_C4 | SERDES.D_SCISELAUX |
| TCELL4:IMUX_C6 | SERDES.D_SCIRD |
| TCELL4:IMUX_D0 | SERDES.D_SCIWDATA0 |
| TCELL4:IMUX_D2 | SERDES.D_SCIWDATA2 |
| TCELL4:IMUX_D4 | SERDES.D_SCIWDATA4 |
| TCELL4:IMUX_D6 | SERDES.D_SCIWDATA6 |
| TCELL4:IMUX_CLK0 | SERDES.CH0_RX_REFCLK |
| TCELL4:OUT_F1 | SERDES.D_COUT19 |
| TCELL4:OUT_F2 | SERDES.D_COUT16 |
| TCELL4:OUT_F3 | SERDES.D_COUT6 |
| TCELL4:OUT_F4 | SERDES.D_COUT7 |
| TCELL4:OUT_F5 | SERDES.D_COUT8 |
| TCELL4:OUT_F6 | SERDES.D_COUT9 |
| TCELL4:OUT_F7 | SERDES.D_COUT10 |
| TCELL4:OUT_Q0 | SERDES.D_COUT17 |
| TCELL4:OUT_Q1 | SERDES.D_COUT18 |
| TCELL4:OUT_Q4 | SERDES.CH0_FFS_CC_UNDERRUN |
| TCELL4:OUT_Q5 | SERDES.CH0_FFS_RXFBFIFO_ERROR |
| TCELL5:IMUX_A1 | SERDES.CH1_FFC_RX_GEAR_MODE |
| TCELL5:IMUX_A3 | SERDES.CH1_FFC_CDR_EN_BITSLIP |
| TCELL5:IMUX_A5 | SERDES.D_CIN7 |
| TCELL5:IMUX_A7 | SERDES.D_CIN9 |
| TCELL5:IMUX_B1 | SERDES.D_CIN10 |
| TCELL5:IMUX_B3 | SERDES.D_CIN1 |
| TCELL5:IMUX_B5 | SERDES.D_CIN3 |
| TCELL5:IMUX_B7 | SERDES.D_CIN5 |
| TCELL5:IMUX_C0 | SERDES.D_SCAN_IN_2 |
| TCELL5:IMUX_C2 | SERDES.CH1_FFC_SB_INV_RX |
| TCELL5:IMUX_C4 | SERDES.D_CIN6 |
| TCELL5:IMUX_C6 | SERDES.D_CIN8 |
| TCELL5:IMUX_D0 | SERDES.D_CIN11 |
| TCELL5:IMUX_D2 | SERDES.D_CIN0 |
| TCELL5:IMUX_D4 | SERDES.D_CIN2 |
| TCELL5:IMUX_D6 | SERDES.D_CIN4 |
| TCELL5:OUT_F0 | SERDES.D_COUT11 |
| TCELL5:OUT_F1 | SERDES.D_COUT12 |
| TCELL5:OUT_F2 | SERDES.D_COUT13 |
| TCELL5:OUT_F3 | SERDES.D_COUT14 |
| TCELL5:OUT_F4 | SERDES.D_COUT15 |
| TCELL5:OUT_F5 | SERDES.D_COUT0 |
| TCELL5:OUT_F6 | SERDES.D_COUT2 |
| TCELL5:OUT_F7 | SERDES.D_COUT3 |
| TCELL5:OUT_Q0 | SERDES.D_COUT4 |
| TCELL5:OUT_Q1 | SERDES.D_COUT5 |
| TCELL5:OUT_Q4 | SERDES.D_SCAN_OUT_6 |
| TCELL5:OUT_Q5 | SERDES.D_SCIINT |
| TCELL6:IMUX_A5 | SERDES.D_SCAN_IN_1 |
| TCELL6:IMUX_A7 | SERDES.CH1_FFC_LDR_CORE2TX_EN |
| TCELL6:IMUX_B1 | SERDES.CH1_FFC_SIGNAL_DETECT |
| TCELL6:IMUX_B3 | SERDES.CH1_FFC_PFIFO_CLR |
| TCELL6:IMUX_B5 | SERDES.CH1_FFC_FB_LOOPBACK |
| TCELL6:IMUX_B7 | SERDES.CH1_FFC_ENABLE_CGALIGN |
| TCELL6:IMUX_C0 | SERDES.CH1_FFC_RRST |
| TCELL6:IMUX_C4 | SERDES.CH1_FFC_RATE_MODE_RX |
| TCELL6:IMUX_C6 | SERDES.CH1_FFC_TX_GEAR_MODE |
| TCELL6:IMUX_D0 | SERDES.CH1_FFC_DIV11_MODE_RX |
| TCELL6:IMUX_D2 | SERDES.CH1_FFC_LANE_RX_RST |
| TCELL6:IMUX_D4 | SERDES.CH1_FFC_SB_PFIFO_LP |
| TCELL6:IMUX_D6 | SERDES.CH1_FFC_RXPWDNB |
| TCELL6:IMUX_CLK0 | SERDES.CH1_FF_RXI_CLK |
| TCELL6:IMUX_CLK1 | SERDES.CH1_RX_REFCLK |
| TCELL6:OUT_F0 | SERDES.D_SCIRDATA0 |
| TCELL6:OUT_F1 | SERDES.D_SCIRDATA1 |
| TCELL6:OUT_F2 | SERDES.D_SCIRDATA2 |
| TCELL6:OUT_F3 | SERDES.D_SCIRDATA3 |
| TCELL6:OUT_F4 | SERDES.D_SCIRDATA4 |
| TCELL6:OUT_F5 | SERDES.D_SCIRDATA5 |
| TCELL6:OUT_F6 | SERDES.D_SCIRDATA6 |
| TCELL6:OUT_F7 | SERDES.D_SCIRDATA7 |
| TCELL6:OUT_Q0 | SERDES.CH1_FF_RX_F_CLK |
| TCELL6:OUT_Q1 | SERDES.CH1_FF_RX_H_CLK |
| TCELL7:IMUX_B1 | SERDES.CH1_LDR_CORE2TX |
| TCELL7:IMUX_B3 | SERDES.CH1_FFC_EI_EN |
| TCELL7:IMUX_B5 | SERDES.CH1_FFC_PCIE_DET_EN |
| TCELL7:IMUX_B7 | SERDES.CH1_FFC_TXPWDNB |
| TCELL7:IMUX_D0 | SERDES.CH1_FFC_LANE_TX_RST |
| TCELL7:IMUX_D2 | SERDES.CH1_FFC_RATE_MODE_TX |
| TCELL7:IMUX_D4 | SERDES.CH1_FFC_PCIE_CT |
| TCELL7:IMUX_D6 | SERDES.CH1_FFC_DIV11_MODE_TX |
| TCELL7:IMUX_CLK0 | SERDES.CH1_FF_EBRD_CLK |
| TCELL7:IMUX_CLK1 | SERDES.CH1_FF_TXI_CLK |
| TCELL7:OUT_F1 | SERDES.CH1_FFS_RXFBFIFO_ERROR |
| TCELL7:OUT_F2 | SERDES.CH1_FFS_CC_UNDERRUN |
| TCELL7:OUT_F3 | SERDES.CH1_FFS_LS_SYNC_STATUS |
| TCELL7:OUT_F4 | SERDES.CH1_FFS_RLOS |
| TCELL7:OUT_F5 | SERDES.CH1_FFS_RLOL |
| TCELL7:OUT_F6 | SERDES.CH1_FFS_CC_OVERRUN |
| TCELL7:OUT_F7 | SERDES.D_SCAN_OUT_4 |
| TCELL7:OUT_Q0 | SERDES.CH1_FF_TX_F_CLK |
| TCELL7:OUT_Q1 | SERDES.CH1_FF_TX_H_CLK |
| TCELL8:IMUX_B1 | SERDES.CH1_FF_TX_D_1 |
| TCELL8:IMUX_B3 | SERDES.CH1_FF_TX_D_3 |
| TCELL8:IMUX_B5 | SERDES.CH1_FF_TX_D_5 |
| TCELL8:IMUX_B7 | SERDES.CH1_FF_TX_D_7 |
| TCELL8:IMUX_D0 | SERDES.CH1_FF_TX_D_0 |
| TCELL8:IMUX_D2 | SERDES.CH1_FF_TX_D_2 |
| TCELL8:IMUX_D4 | SERDES.CH1_FF_TX_D_4 |
| TCELL8:IMUX_D6 | SERDES.CH1_FF_TX_D_6 |
| TCELL8:OUT_F0 | SERDES.CH1_FF_RX_D_0 |
| TCELL8:OUT_F1 | SERDES.CH1_FF_RX_D_1 |
| TCELL8:OUT_F2 | SERDES.CH1_FF_RX_D_2 |
| TCELL8:OUT_F3 | SERDES.CH1_FF_RX_D_3 |
| TCELL8:OUT_F4 | SERDES.CH1_FF_RX_D_4 |
| TCELL8:OUT_F5 | SERDES.CH1_FF_RX_D_5 |
| TCELL8:OUT_F6 | SERDES.CH1_FF_RX_D_6 |
| TCELL8:OUT_F7 | SERDES.CH1_FF_RX_D_7 |
| TCELL9:IMUX_B1 | SERDES.CH1_FF_TX_D_9 |
| TCELL9:IMUX_B3 | SERDES.CH1_FF_TX_D_11 |
| TCELL9:IMUX_B5 | SERDES.CH1_FF_TX_D_13 |
| TCELL9:IMUX_B7 | SERDES.CH1_FF_TX_D_15 |
| TCELL9:IMUX_D0 | SERDES.CH1_FF_TX_D_8 |
| TCELL9:IMUX_D2 | SERDES.CH1_FF_TX_D_10 |
| TCELL9:IMUX_D4 | SERDES.CH1_FF_TX_D_12 |
| TCELL9:IMUX_D6 | SERDES.CH1_FF_TX_D_14 |
| TCELL9:OUT_F0 | SERDES.CH1_FF_RX_D_8 |
| TCELL9:OUT_F1 | SERDES.CH1_FF_RX_D_9 |
| TCELL9:OUT_F2 | SERDES.CH1_FF_RX_D_10 |
| TCELL9:OUT_F3 | SERDES.CH1_FF_RX_D_11 |
| TCELL9:OUT_F4 | SERDES.CH1_FF_RX_D_12 |
| TCELL9:OUT_F5 | SERDES.CH1_FF_RX_D_13 |
| TCELL9:OUT_F6 | SERDES.CH1_FF_RX_D_14 |
| TCELL9:OUT_F7 | SERDES.CH1_FF_RX_D_15 |
| TCELL10:IMUX_B1 | SERDES.CH1_FF_TX_D_17 |
| TCELL10:IMUX_B3 | SERDES.CH1_FF_TX_D_19 |
| TCELL10:IMUX_B5 | SERDES.CH1_FF_TX_D_21 |
| TCELL10:IMUX_B7 | SERDES.CH1_FF_TX_D_23 |
| TCELL10:IMUX_D0 | SERDES.CH1_FF_TX_D_16 |
| TCELL10:IMUX_D2 | SERDES.CH1_FF_TX_D_18 |
| TCELL10:IMUX_D4 | SERDES.CH1_FF_TX_D_20 |
| TCELL10:IMUX_D6 | SERDES.CH1_FF_TX_D_22 |
| TCELL10:OUT_F0 | SERDES.CH1_FF_RX_D_16 |
| TCELL10:OUT_F1 | SERDES.CH1_FF_RX_D_17 |
| TCELL10:OUT_F2 | SERDES.CH1_FF_RX_D_18 |
| TCELL10:OUT_F3 | SERDES.CH1_FF_RX_D_19 |
| TCELL10:OUT_F4 | SERDES.CH1_FF_RX_D_20 |
| TCELL10:OUT_F5 | SERDES.CH1_FF_RX_D_21 |
| TCELL10:OUT_F6 | SERDES.CH1_FF_RX_D_22 |
| TCELL10:OUT_F7 | SERDES.CH1_FF_RX_D_23 |
| TCELL10:OUT_Q0 | SERDES.CH1_FFS_SKP_DELETED |
| TCELL10:OUT_Q1 | SERDES.CH1_FFS_SKP_ADDED |
| TCELL11:IMUX_B1 | SERDES.D_FFC_MACRO_RST |
| TCELL11:IMUX_B3 | SERDES.D_FFC_TRST |
| TCELL11:IMUX_B5 | SERDES.D_FFC_SYNC_TOGGLE |
| TCELL11:IMUX_D0 | SERDES.D_SCAN_IN_0 |
| TCELL11:IMUX_D2 | SERDES.D_FFC_MACROPDB |
| TCELL11:IMUX_CLK0 | SERDES.D_REFCLKI |
| TCELL11:OUT_F0 | SERDES.CH1_LDR_RX2CORE |
| TCELL11:OUT_F1 | SERDES.D_SCAN_OUT_7 |
| TCELL11:OUT_F2 | SERDES.CH1_FFS_TXFBFIFO_ERROR |
| TCELL11:OUT_F3 | SERDES.CH1_FFS_PCIE_CON |
| TCELL11:OUT_F4 | SERDES.CH1_FFS_PCIE_DONE |
| TCELL11:OUT_F5 | SERDES.D_SCAN_OUT_3 |
| TCELL11:OUT_F6 | SERDES.D_COUT1 |
| TCELL11:OUT_F7 | SERDES.D_SCAN_OUT_0 |
| TCELL11:OUT_Q0 | SERDES.D_FFS_PLOL |