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North-west

TODO: document

Tile UL.FC

Cells: 1 IRIs: 0

Bel PMV

fpgacore UL.FC bel PMV
PinDirectionWires
A0inputIMUX.DATA0
A1inputIMUX.DATA1
A2inputIMUX.DATA2
A3inputIMUX.DATA3
A4inputIMUX.DATA4
A5inputIMUX.DATA5
ENinputIMUX.DATA6
OoutputOUT.FAN0

Bel MISR

fpgacore UL.FC bel MISR
PinDirectionWires
CLKinputIMUX.CLK3

Bel wires

fpgacore UL.FC bel wires
WirePins
IMUX.CLK3MISR.CLK
IMUX.DATA0PMV.A0
IMUX.DATA1PMV.A1
IMUX.DATA2PMV.A2
IMUX.DATA3PMV.A3
IMUX.DATA4PMV.A4
IMUX.DATA5PMV.A5
IMUX.DATA6PMV.EN
OUT.FAN0PMV.O

Bitstream

fpgacore UL.FC bittile 0
BitFrame
0 1
32 - MISC:TEST_LL
31 - -
30 - -
29 - -
28 - -
27 - -
26 - -
25 - -
24 - -
23 - -
22 - -
21 - -
20 - -
19 - -
18 - -
17 - -
16 - -
15 - -
14 - -
13 - -
12 - -
11 - -
10 - -
9 - -
8 - -
7 - -
6 - -
5 - -
4 - -
3 - -
2 - -
1 MISC:MISR_CLOCK -
0 MISC:MISR_RESET -
MISC:MISR_CLOCK 0.0.1
MISC:MISR_RESET 0.0.0
MISC:TEST_LL 0.1.32
non-inverted [0]