TODO: document
Cells: 1
fpgacore LR.FC bel STARTUP
| Pin | Direction | Wires | 
| CLK | input | IMUX.CLK0 | 
| GSR | input | IMUX.SR0 | 
| GTS | input | IMUX.SR3 | 
 
fpgacore LR.FC bel CAPTURE
| Pin | Direction | Wires | 
| CAP | input | IMUX.SR1 | 
| CLK | input | IMUX.CLK2 | 
 
fpgacore LR.FC bel ICAP
| Pin | Direction | Wires | 
| BUSY | output | OUT.SEC8 | 
| CE | input | IMUX.CE2 | 
| CLK | input | IMUX.CLK1 | 
| I0 | input | IMUX.DATA0 | 
| I1 | input | IMUX.DATA1 | 
| I2 | input | IMUX.DATA2 | 
| I3 | input | IMUX.DATA3 | 
| I4 | input | IMUX.DATA4 | 
| I5 | input | IMUX.DATA5 | 
| I6 | input | IMUX.DATA6 | 
| I7 | input | IMUX.DATA7 | 
| O0 | output | OUT.FAN0 | 
| O1 | output | OUT.FAN1 | 
| O2 | output | OUT.FAN2 | 
| O3 | output | OUT.FAN3 | 
| O4 | output | OUT.FAN4 | 
| O5 | output | OUT.FAN5 | 
| O6 | output | OUT.FAN6 | 
| O7 | output | OUT.FAN7 | 
| WRITE | input | IMUX.CE1 | 
 
fpgacore LR.FC bel MISR
| Pin | Direction | Wires | 
| CLK | input | IMUX.CLK3 | 
 
fpgacore LR.FC bel wires
| Wire | Pins | 
| IMUX.SR0 | STARTUP.GSR | 
| IMUX.SR1 | CAPTURE.CAP | 
| IMUX.SR3 | STARTUP.GTS | 
| IMUX.CLK0 | STARTUP.CLK | 
| IMUX.CLK1 | ICAP.CLK | 
| IMUX.CLK2 | CAPTURE.CLK | 
| IMUX.CLK3 | MISR.CLK | 
| IMUX.CE1 | ICAP.WRITE | 
| IMUX.CE2 | ICAP.CE | 
| IMUX.DATA0 | ICAP.I0 | 
| IMUX.DATA1 | ICAP.I1 | 
| IMUX.DATA2 | ICAP.I2 | 
| IMUX.DATA3 | ICAP.I3 | 
| IMUX.DATA4 | ICAP.I4 | 
| IMUX.DATA5 | ICAP.I5 | 
| IMUX.DATA6 | ICAP.I6 | 
| IMUX.DATA7 | ICAP.I7 | 
| OUT.FAN0 | ICAP.O0 | 
| OUT.FAN1 | ICAP.O1 | 
| OUT.FAN2 | ICAP.O2 | 
| OUT.FAN3 | ICAP.O3 | 
| OUT.FAN4 | ICAP.O4 | 
| OUT.FAN5 | ICAP.O5 | 
| OUT.FAN6 | ICAP.O6 | 
| OUT.FAN7 | ICAP.O7 | 
| OUT.SEC8 | ICAP.BUSY | 
 
| ICAP:ENABLE | 
0.1.3 | 
| MISC:MISR_CLOCK | 
0.0.1 | 
| MISC:MISR_RESET | 
0.0.0 | 
| STARTUP:GSR_SYNC | 
0.1.0 | 
| STARTUP:GTS_GSR_ENABLE | 
0.1.4 | 
| STARTUP:GTS_SYNC | 
0.1.1 | 
| 
non-inverted
 | 
[0] | 
 
| MISC:ABUFF | 
0.0.43 | 
0.0.42 | 
0.0.41 | 
0.0.40 | 
| 
non-inverted
 | 
[3] | 
[2] | 
[1] | 
[0] |