Input / Output
Tile IO_W2
Cells: 1
Bel IO0
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE0 |
CLK | input | IMUX_CLK0 |
DI | output | OUT_Q0 |
IN | output | OUT_F0 |
IP | output | OUT_F4 |
LSR | input | IMUX_LSR0 |
ONEG | input | IMUX_B0 |
OPOS | input | IMUX_A0 |
TS | input | IMUX_C0 |
Bel IO1
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE1 |
CLK | input | IMUX_CLK1 |
DI | output | OUT_Q1 |
IN | output | OUT_F1 |
IP | output | OUT_F5 |
LSR | input | IMUX_LSR1 |
ONEG | input | IMUX_B1 |
OPOS | input | IMUX_A1 |
TS | input | IMUX_C1 |
Bel wires
Wire | Pins |
---|---|
IMUX_A0 | IO0.OPOS |
IMUX_A1 | IO1.OPOS |
IMUX_B0 | IO0.ONEG |
IMUX_B1 | IO1.ONEG |
IMUX_C0 | IO0.TS |
IMUX_C1 | IO1.TS |
IMUX_CLK0 | IO0.CLK |
IMUX_CLK1 | IO1.CLK |
IMUX_LSR0 | IO0.LSR |
IMUX_LSR1 | IO1.LSR |
IMUX_CE0 | IO0.CE |
IMUX_CE1 | IO1.CE |
OUT_F0 | IO0.IN |
OUT_F1 | IO1.IN |
OUT_F4 | IO0.IP |
OUT_F5 | IO1.IP |
OUT_Q0 | IO0.DI |
OUT_Q1 | IO1.DI |
Tile IO_W4
Cells: 1
Bel IO0
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE0 |
CLK | input | IMUX_CLK0 |
DI | output | OUT_Q0 |
IN | output | OUT_F0 |
IP | output | OUT_F4 |
LSR | input | IMUX_LSR0 |
ONEG | input | IMUX_B0 |
OPOS | input | IMUX_A0 |
TS | input | IMUX_C0 |
Bel IO1
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE1 |
CLK | input | IMUX_CLK1 |
DI | output | OUT_Q1 |
IN | output | OUT_F1 |
IP | output | OUT_F5 |
LSR | input | IMUX_LSR1 |
ONEG | input | IMUX_B1 |
OPOS | input | IMUX_A1 |
TS | input | IMUX_C1 |
Bel IO2
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE2 |
CLK | input | IMUX_CLK2 |
DI | output | OUT_Q2 |
IN | output | OUT_F2 |
IP | output | OUT_F6 |
LSR | input | IMUX_LSR2 |
ONEG | input | IMUX_B2 |
OPOS | input | IMUX_A2 |
TS | input | IMUX_C2 |
Bel IO3
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE3 |
CLK | input | IMUX_CLK3 |
DI | output | OUT_Q3 |
IN | output | OUT_F3 |
IP | output | OUT_F7 |
LSR | input | IMUX_LSR3 |
ONEG | input | IMUX_B3 |
OPOS | input | IMUX_A3 |
TS | input | IMUX_C3 |
Bel wires
Wire | Pins |
---|---|
IMUX_A0 | IO0.OPOS |
IMUX_A1 | IO1.OPOS |
IMUX_A2 | IO2.OPOS |
IMUX_A3 | IO3.OPOS |
IMUX_B0 | IO0.ONEG |
IMUX_B1 | IO1.ONEG |
IMUX_B2 | IO2.ONEG |
IMUX_B3 | IO3.ONEG |
IMUX_C0 | IO0.TS |
IMUX_C1 | IO1.TS |
IMUX_C2 | IO2.TS |
IMUX_C3 | IO3.TS |
IMUX_CLK0 | IO0.CLK |
IMUX_CLK1 | IO1.CLK |
IMUX_CLK2 | IO2.CLK |
IMUX_CLK3 | IO3.CLK |
IMUX_LSR0 | IO0.LSR |
IMUX_LSR1 | IO1.LSR |
IMUX_LSR2 | IO2.LSR |
IMUX_LSR3 | IO3.LSR |
IMUX_CE0 | IO0.CE |
IMUX_CE1 | IO1.CE |
IMUX_CE2 | IO2.CE |
IMUX_CE3 | IO3.CE |
OUT_F0 | IO0.IN |
OUT_F1 | IO1.IN |
OUT_F2 | IO2.IN |
OUT_F3 | IO3.IN |
OUT_F4 | IO0.IP |
OUT_F5 | IO1.IP |
OUT_F6 | IO2.IP |
OUT_F7 | IO3.IP |
OUT_Q0 | IO0.DI |
OUT_Q1 | IO1.DI |
OUT_Q2 | IO2.DI |
OUT_Q3 | IO3.DI |
Tile IO_W4_I3C
Cells: 1
Bel IO0
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE0 |
CLK | input | IMUX_CLK0 |
DI | output | OUT_Q0 |
IN | output | OUT_F0 |
IP | output | OUT_F4 |
LSR | input | IMUX_LSR0 |
ONEG | input | IMUX_B0 |
OPOS | input | IMUX_A0 |
PULLUPEN | input | IMUX_C4 |
RESEN | input | IMUX_A4 |
TS | input | IMUX_C0 |
Bel IO1
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE1 |
CLK | input | IMUX_CLK1 |
DI | output | OUT_Q1 |
IN | output | OUT_F1 |
IP | output | OUT_F5 |
LSR | input | IMUX_LSR1 |
ONEG | input | IMUX_B1 |
OPOS | input | IMUX_A1 |
PULLUPEN | input | IMUX_D4 |
RESEN | input | IMUX_B4 |
TS | input | IMUX_C1 |
Bel IO2
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE2 |
CLK | input | IMUX_CLK2 |
DI | output | OUT_Q2 |
IN | output | OUT_F2 |
IP | output | OUT_F6 |
LSR | input | IMUX_LSR2 |
ONEG | input | IMUX_B2 |
OPOS | input | IMUX_A2 |
TS | input | IMUX_C2 |
Bel IO3
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE3 |
CLK | input | IMUX_CLK3 |
DI | output | OUT_Q3 |
IN | output | OUT_F3 |
IP | output | OUT_F7 |
LSR | input | IMUX_LSR3 |
ONEG | input | IMUX_B3 |
OPOS | input | IMUX_A3 |
TS | input | IMUX_C3 |
Bel wires
Wire | Pins |
---|---|
IMUX_A0 | IO0.OPOS |
IMUX_A1 | IO1.OPOS |
IMUX_A2 | IO2.OPOS |
IMUX_A3 | IO3.OPOS |
IMUX_A4 | IO0.RESEN |
IMUX_B0 | IO0.ONEG |
IMUX_B1 | IO1.ONEG |
IMUX_B2 | IO2.ONEG |
IMUX_B3 | IO3.ONEG |
IMUX_B4 | IO1.RESEN |
IMUX_C0 | IO0.TS |
IMUX_C1 | IO1.TS |
IMUX_C2 | IO2.TS |
IMUX_C3 | IO3.TS |
IMUX_C4 | IO0.PULLUPEN |
IMUX_D4 | IO1.PULLUPEN |
IMUX_CLK0 | IO0.CLK |
IMUX_CLK1 | IO1.CLK |
IMUX_CLK2 | IO2.CLK |
IMUX_CLK3 | IO3.CLK |
IMUX_LSR0 | IO0.LSR |
IMUX_LSR1 | IO1.LSR |
IMUX_LSR2 | IO2.LSR |
IMUX_LSR3 | IO3.LSR |
IMUX_CE0 | IO0.CE |
IMUX_CE1 | IO1.CE |
IMUX_CE2 | IO2.CE |
IMUX_CE3 | IO3.CE |
OUT_F0 | IO0.IN |
OUT_F1 | IO1.IN |
OUT_F2 | IO2.IN |
OUT_F3 | IO3.IN |
OUT_F4 | IO0.IP |
OUT_F5 | IO1.IP |
OUT_F6 | IO2.IP |
OUT_F7 | IO3.IP |
OUT_Q0 | IO0.DI |
OUT_Q1 | IO1.DI |
OUT_Q2 | IO2.DI |
OUT_Q3 | IO3.DI |
Tile IO_E2
Cells: 1
Bel IO0
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE0 |
CLK | input | IMUX_CLK0 |
DI | output | OUT_Q0 |
IN | output | OUT_F0 |
IP | output | OUT_F4 |
LSR | input | IMUX_LSR0 |
ONEG | input | IMUX_B0 |
OPOS | input | IMUX_A0 |
TS | input | IMUX_C0 |
Bel IO1
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE1 |
CLK | input | IMUX_CLK1 |
DI | output | OUT_Q1 |
IN | output | OUT_F1 |
IP | output | OUT_F5 |
LSR | input | IMUX_LSR1 |
ONEG | input | IMUX_B1 |
OPOS | input | IMUX_A1 |
TS | input | IMUX_C1 |
Bel wires
Wire | Pins |
---|---|
IMUX_A0 | IO0.OPOS |
IMUX_A1 | IO1.OPOS |
IMUX_B0 | IO0.ONEG |
IMUX_B1 | IO1.ONEG |
IMUX_C0 | IO0.TS |
IMUX_C1 | IO1.TS |
IMUX_CLK0 | IO0.CLK |
IMUX_CLK1 | IO1.CLK |
IMUX_LSR0 | IO0.LSR |
IMUX_LSR1 | IO1.LSR |
IMUX_CE0 | IO0.CE |
IMUX_CE1 | IO1.CE |
OUT_F0 | IO0.IN |
OUT_F1 | IO1.IN |
OUT_F4 | IO0.IP |
OUT_F5 | IO1.IP |
OUT_Q0 | IO0.DI |
OUT_Q1 | IO1.DI |
Tile IO_E4
Cells: 1
Bel IO0
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE0 |
CLK | input | IMUX_CLK0 |
DI | output | OUT_Q0 |
IN | output | OUT_F0 |
IP | output | OUT_F4 |
LSR | input | IMUX_LSR0 |
ONEG | input | IMUX_B0 |
OPOS | input | IMUX_A0 |
TS | input | IMUX_C0 |
Bel IO1
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE1 |
CLK | input | IMUX_CLK1 |
DI | output | OUT_Q1 |
IN | output | OUT_F1 |
IP | output | OUT_F5 |
LSR | input | IMUX_LSR1 |
ONEG | input | IMUX_B1 |
OPOS | input | IMUX_A1 |
TS | input | IMUX_C1 |
Bel IO2
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE2 |
CLK | input | IMUX_CLK2 |
DI | output | OUT_Q2 |
IN | output | OUT_F2 |
IP | output | OUT_F6 |
LSR | input | IMUX_LSR2 |
ONEG | input | IMUX_B2 |
OPOS | input | IMUX_A2 |
TS | input | IMUX_C2 |
Bel IO3
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE3 |
CLK | input | IMUX_CLK3 |
DI | output | OUT_Q3 |
IN | output | OUT_F3 |
IP | output | OUT_F7 |
LSR | input | IMUX_LSR3 |
ONEG | input | IMUX_B3 |
OPOS | input | IMUX_A3 |
TS | input | IMUX_C3 |
Bel wires
Wire | Pins |
---|---|
IMUX_A0 | IO0.OPOS |
IMUX_A1 | IO1.OPOS |
IMUX_A2 | IO2.OPOS |
IMUX_A3 | IO3.OPOS |
IMUX_B0 | IO0.ONEG |
IMUX_B1 | IO1.ONEG |
IMUX_B2 | IO2.ONEG |
IMUX_B3 | IO3.ONEG |
IMUX_C0 | IO0.TS |
IMUX_C1 | IO1.TS |
IMUX_C2 | IO2.TS |
IMUX_C3 | IO3.TS |
IMUX_CLK0 | IO0.CLK |
IMUX_CLK1 | IO1.CLK |
IMUX_CLK2 | IO2.CLK |
IMUX_CLK3 | IO3.CLK |
IMUX_LSR0 | IO0.LSR |
IMUX_LSR1 | IO1.LSR |
IMUX_LSR2 | IO2.LSR |
IMUX_LSR3 | IO3.LSR |
IMUX_CE0 | IO0.CE |
IMUX_CE1 | IO1.CE |
IMUX_CE2 | IO2.CE |
IMUX_CE3 | IO3.CE |
OUT_F0 | IO0.IN |
OUT_F1 | IO1.IN |
OUT_F2 | IO2.IN |
OUT_F3 | IO3.IN |
OUT_F4 | IO0.IP |
OUT_F5 | IO1.IP |
OUT_F6 | IO2.IP |
OUT_F7 | IO3.IP |
OUT_Q0 | IO0.DI |
OUT_Q1 | IO1.DI |
OUT_Q2 | IO2.DI |
OUT_Q3 | IO3.DI |
Tile SIO_S2
Cells: 1
Bel IO0
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE0 |
CLK | input | IMUX_CLK0 |
DI | output | OUT_Q0 |
IN | output | OUT_F0 |
IP | output | OUT_F4 |
LSR | input | IMUX_LSR0 |
ONEG | input | IMUX_B0 |
OPOS | input | IMUX_A0 |
TS | input | IMUX_C0 |
Bel IO1
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE1 |
CLK | input | IMUX_CLK1 |
DI | output | OUT_Q1 |
IN | output | OUT_F1 |
IP | output | OUT_F5 |
LSR | input | IMUX_LSR1 |
ONEG | input | IMUX_B1 |
OPOS | input | IMUX_A1 |
TS | input | IMUX_C1 |
Bel wires
Wire | Pins |
---|---|
IMUX_A0 | IO0.OPOS |
IMUX_A1 | IO1.OPOS |
IMUX_B0 | IO0.ONEG |
IMUX_B1 | IO1.ONEG |
IMUX_C0 | IO0.TS |
IMUX_C1 | IO1.TS |
IMUX_CLK0 | IO0.CLK |
IMUX_CLK1 | IO1.CLK |
IMUX_LSR0 | IO0.LSR |
IMUX_LSR1 | IO1.LSR |
IMUX_CE0 | IO0.CE |
IMUX_CE1 | IO1.CE |
OUT_F0 | IO0.IN |
OUT_F1 | IO1.IN |
OUT_F4 | IO0.IP |
OUT_F5 | IO1.IP |
OUT_Q0 | IO0.DI |
OUT_Q1 | IO1.DI |
Tile SIO_S4
Cells: 1
Bel IO0
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE0 |
CLK | input | IMUX_CLK0 |
DI | output | OUT_Q0 |
IN | output | OUT_F0 |
IP | output | OUT_F4 |
LSR | input | IMUX_LSR0 |
ONEG | input | IMUX_B0 |
OPOS | input | IMUX_A0 |
TS | input | IMUX_C0 |
Bel IO1
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE1 |
CLK | input | IMUX_CLK1 |
DI | output | OUT_Q1 |
IN | output | OUT_F1 |
IP | output | OUT_F5 |
LSR | input | IMUX_LSR1 |
ONEG | input | IMUX_B1 |
OPOS | input | IMUX_A1 |
TS | input | IMUX_C1 |
Bel IO2
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE2 |
CLK | input | IMUX_CLK2 |
DI | output | OUT_Q2 |
IN | output | OUT_F2 |
IP | output | OUT_F6 |
LSR | input | IMUX_LSR2 |
ONEG | input | IMUX_B2 |
OPOS | input | IMUX_A2 |
TS | input | IMUX_C2 |
Bel IO3
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE3 |
CLK | input | IMUX_CLK3 |
DI | output | OUT_Q3 |
IN | output | OUT_F3 |
IP | output | OUT_F7 |
LSR | input | IMUX_LSR3 |
ONEG | input | IMUX_B3 |
OPOS | input | IMUX_A3 |
TS | input | IMUX_C3 |
Bel wires
Wire | Pins |
---|---|
IMUX_A0 | IO0.OPOS |
IMUX_A1 | IO1.OPOS |
IMUX_A2 | IO2.OPOS |
IMUX_A3 | IO3.OPOS |
IMUX_B0 | IO0.ONEG |
IMUX_B1 | IO1.ONEG |
IMUX_B2 | IO2.ONEG |
IMUX_B3 | IO3.ONEG |
IMUX_C0 | IO0.TS |
IMUX_C1 | IO1.TS |
IMUX_C2 | IO2.TS |
IMUX_C3 | IO3.TS |
IMUX_CLK0 | IO0.CLK |
IMUX_CLK1 | IO1.CLK |
IMUX_CLK2 | IO2.CLK |
IMUX_CLK3 | IO3.CLK |
IMUX_LSR0 | IO0.LSR |
IMUX_LSR1 | IO1.LSR |
IMUX_LSR2 | IO2.LSR |
IMUX_LSR3 | IO3.LSR |
IMUX_CE0 | IO0.CE |
IMUX_CE1 | IO1.CE |
IMUX_CE2 | IO2.CE |
IMUX_CE3 | IO3.CE |
OUT_F0 | IO0.IN |
OUT_F1 | IO1.IN |
OUT_F2 | IO2.IN |
OUT_F3 | IO3.IN |
OUT_F4 | IO0.IP |
OUT_F5 | IO1.IP |
OUT_F6 | IO2.IP |
OUT_F7 | IO3.IP |
OUT_Q0 | IO0.DI |
OUT_Q1 | IO1.DI |
OUT_Q2 | IO2.DI |
OUT_Q3 | IO3.DI |
Tile IO_S4
Cells: 1
Bel IO0
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE0 |
CLK | input | IMUX_CLK0 |
DEL0 | input | IMUX_D2 |
DEL1 | input | IMUX_D3 |
DEL2 | input | IMUX_A4 |
DEL3 | input | IMUX_B4 |
DEL4 | input | IMUX_C4 |
DI | output | OUT_Q0 |
IN | output | OUT_F0 |
IP | output | OUT_F4 |
LSR | input | IMUX_LSR0 |
ONEG | input | IMUX_B0 |
OPOS | input | IMUX_A0 |
RXD0 | output | OUT_F4 |
RXD1 | output | OUT_F0 |
RXD2 | output | OUT_F5 |
RXD3 | output | OUT_F1 |
RXDA0 | output | OUT_Q4 |
RXDA1 | output | OUT_Q5 |
RXDA2 | output | OUT_Q6 |
RXDA3 | output | OUT_Q7 |
RXDA4 | output | OUT_F4 |
RXDA5 | output | OUT_F0 |
RXDA6 | output | OUT_F5 |
RXDA7 | output | OUT_F1 |
SLIP | input | IMUX_D0 |
TS | input | IMUX_C0 |
Bel IO1
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE1 |
CLK | input | IMUX_CLK1 |
DI | output | OUT_Q1 |
IN | output | OUT_F1 |
IP | output | OUT_F5 |
LSR | input | IMUX_LSR1 |
ONEG | input | IMUX_B1 |
OPOS | input | IMUX_A1 |
TS | input | IMUX_C1 |
Bel IO2
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE2 |
CLK | input | IMUX_CLK2 |
DEL0 | input | IMUX_D4 |
DEL1 | input | IMUX_A5 |
DEL2 | input | IMUX_B5 |
DEL3 | input | IMUX_C5 |
DEL4 | input | IMUX_D5 |
DI | output | OUT_Q2 |
IN | output | OUT_F2 |
IP | output | OUT_F6 |
LSR | input | IMUX_LSR2 |
ONEG | input | IMUX_B2 |
OPOS | input | IMUX_A2 |
RXD0 | output | OUT_Q4 |
RXD1 | output | OUT_Q5 |
RXD2 | output | OUT_Q6 |
RXD3 | output | OUT_Q7 |
SLIP | input | IMUX_D1 |
TS | input | IMUX_C2 |
Bel IO3
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE3 |
CLK | input | IMUX_CLK3 |
DI | output | OUT_Q3 |
IN | output | OUT_F3 |
IP | output | OUT_F7 |
LSR | input | IMUX_LSR3 |
ONEG | input | IMUX_B3 |
OPOS | input | IMUX_A3 |
TS | input | IMUX_C3 |
Bel wires
Wire | Pins |
---|---|
IMUX_A0 | IO0.OPOS |
IMUX_A1 | IO1.OPOS |
IMUX_A2 | IO2.OPOS |
IMUX_A3 | IO3.OPOS |
IMUX_A4 | IO0.DEL2 |
IMUX_A5 | IO2.DEL1 |
IMUX_B0 | IO0.ONEG |
IMUX_B1 | IO1.ONEG |
IMUX_B2 | IO2.ONEG |
IMUX_B3 | IO3.ONEG |
IMUX_B4 | IO0.DEL3 |
IMUX_B5 | IO2.DEL2 |
IMUX_C0 | IO0.TS |
IMUX_C1 | IO1.TS |
IMUX_C2 | IO2.TS |
IMUX_C3 | IO3.TS |
IMUX_C4 | IO0.DEL4 |
IMUX_C5 | IO2.DEL3 |
IMUX_D0 | IO0.SLIP |
IMUX_D1 | IO2.SLIP |
IMUX_D2 | IO0.DEL0 |
IMUX_D3 | IO0.DEL1 |
IMUX_D4 | IO2.DEL0 |
IMUX_D5 | IO2.DEL4 |
IMUX_CLK0 | IO0.CLK |
IMUX_CLK1 | IO1.CLK |
IMUX_CLK2 | IO2.CLK |
IMUX_CLK3 | IO3.CLK |
IMUX_LSR0 | IO0.LSR |
IMUX_LSR1 | IO1.LSR |
IMUX_LSR2 | IO2.LSR |
IMUX_LSR3 | IO3.LSR |
IMUX_CE0 | IO0.CE |
IMUX_CE1 | IO1.CE |
IMUX_CE2 | IO2.CE |
IMUX_CE3 | IO3.CE |
OUT_F0 | IO0.IN, IO0.RXD1, IO0.RXDA5 |
OUT_F1 | IO0.RXD3, IO0.RXDA7, IO1.IN |
OUT_F2 | IO2.IN |
OUT_F3 | IO3.IN |
OUT_F4 | IO0.IP, IO0.RXD0, IO0.RXDA4 |
OUT_F5 | IO0.RXD2, IO0.RXDA6, IO1.IP |
OUT_F6 | IO2.IP |
OUT_F7 | IO3.IP |
OUT_Q0 | IO0.DI |
OUT_Q1 | IO1.DI |
OUT_Q2 | IO2.DI |
OUT_Q3 | IO3.DI |
OUT_Q4 | IO0.RXDA0, IO2.RXD0 |
OUT_Q5 | IO0.RXDA1, IO2.RXD1 |
OUT_Q6 | IO0.RXDA2, IO2.RXD2 |
OUT_Q7 | IO0.RXDA3, IO2.RXD3 |
Tile SIO_N2
Cells: 1
Bel IO0
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE0 |
CLK | input | IMUX_CLK0 |
DI | output | OUT_Q0 |
IN | output | OUT_F0 |
IP | output | OUT_F4 |
LSR | input | IMUX_LSR0 |
ONEG | input | IMUX_B0 |
OPOS | input | IMUX_A0 |
TS | input | IMUX_C0 |
Bel IO1
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE1 |
CLK | input | IMUX_CLK1 |
DI | output | OUT_Q1 |
IN | output | OUT_F1 |
IP | output | OUT_F5 |
LSR | input | IMUX_LSR1 |
ONEG | input | IMUX_B1 |
OPOS | input | IMUX_A1 |
TS | input | IMUX_C1 |
Bel wires
Wire | Pins |
---|---|
IMUX_A0 | IO0.OPOS |
IMUX_A1 | IO1.OPOS |
IMUX_B0 | IO0.ONEG |
IMUX_B1 | IO1.ONEG |
IMUX_C0 | IO0.TS |
IMUX_C1 | IO1.TS |
IMUX_CLK0 | IO0.CLK |
IMUX_CLK1 | IO1.CLK |
IMUX_LSR0 | IO0.LSR |
IMUX_LSR1 | IO1.LSR |
IMUX_CE0 | IO0.CE |
IMUX_CE1 | IO1.CE |
OUT_F0 | IO0.IN |
OUT_F1 | IO1.IN |
OUT_F4 | IO0.IP |
OUT_F5 | IO1.IP |
OUT_Q0 | IO0.DI |
OUT_Q1 | IO1.DI |
Tile SIO_N4
Cells: 1
Bel IO0
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE0 |
CLK | input | IMUX_CLK0 |
DI | output | OUT_Q0 |
IN | output | OUT_F0 |
IP | output | OUT_F4 |
LSR | input | IMUX_LSR0 |
ONEG | input | IMUX_B0 |
OPOS | input | IMUX_A0 |
TS | input | IMUX_C0 |
Bel IO1
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE1 |
CLK | input | IMUX_CLK1 |
DI | output | OUT_Q1 |
IN | output | OUT_F1 |
IP | output | OUT_F5 |
LSR | input | IMUX_LSR1 |
ONEG | input | IMUX_B1 |
OPOS | input | IMUX_A1 |
TS | input | IMUX_C1 |
Bel IO2
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE2 |
CLK | input | IMUX_CLK2 |
DI | output | OUT_Q2 |
IN | output | OUT_F2 |
IP | output | OUT_F6 |
LSR | input | IMUX_LSR2 |
ONEG | input | IMUX_B2 |
OPOS | input | IMUX_A2 |
TS | input | IMUX_C2 |
Bel IO3
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE3 |
CLK | input | IMUX_CLK3 |
DI | output | OUT_Q3 |
IN | output | OUT_F3 |
IP | output | OUT_F7 |
LSR | input | IMUX_LSR3 |
ONEG | input | IMUX_B3 |
OPOS | input | IMUX_A3 |
TS | input | IMUX_C3 |
Bel wires
Wire | Pins |
---|---|
IMUX_A0 | IO0.OPOS |
IMUX_A1 | IO1.OPOS |
IMUX_A2 | IO2.OPOS |
IMUX_A3 | IO3.OPOS |
IMUX_B0 | IO0.ONEG |
IMUX_B1 | IO1.ONEG |
IMUX_B2 | IO2.ONEG |
IMUX_B3 | IO3.ONEG |
IMUX_C0 | IO0.TS |
IMUX_C1 | IO1.TS |
IMUX_C2 | IO2.TS |
IMUX_C3 | IO3.TS |
IMUX_CLK0 | IO0.CLK |
IMUX_CLK1 | IO1.CLK |
IMUX_CLK2 | IO2.CLK |
IMUX_CLK3 | IO3.CLK |
IMUX_LSR0 | IO0.LSR |
IMUX_LSR1 | IO1.LSR |
IMUX_LSR2 | IO2.LSR |
IMUX_LSR3 | IO3.LSR |
IMUX_CE0 | IO0.CE |
IMUX_CE1 | IO1.CE |
IMUX_CE2 | IO2.CE |
IMUX_CE3 | IO3.CE |
OUT_F0 | IO0.IN |
OUT_F1 | IO1.IN |
OUT_F2 | IO2.IN |
OUT_F3 | IO3.IN |
OUT_F4 | IO0.IP |
OUT_F5 | IO1.IP |
OUT_F6 | IO2.IP |
OUT_F7 | IO3.IP |
OUT_Q0 | IO0.DI |
OUT_Q1 | IO1.DI |
OUT_Q2 | IO2.DI |
OUT_Q3 | IO3.DI |
Tile IO_N4
Cells: 1
Bel IO0
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE0 |
CLK | input | IMUX_CLK0 |
DI | output | OUT_Q0 |
IN | output | OUT_F0 |
IP | output | OUT_F4 |
LSR | input | IMUX_LSR0 |
ONEG | input | IMUX_B0 |
OPOS | input | IMUX_A0 |
TS | input | IMUX_C0 |
TXD0 | input | IMUX_A0 |
TXD1 | input | IMUX_B0 |
TXD2 | input | IMUX_A1 |
TXD3 | input | IMUX_B1 |
TXD4 | input | IMUX_D0 |
TXD5 | input | IMUX_D1 |
TXD6 | input | IMUX_D2 |
TXD7 | input | IMUX_D3 |
Bel IO1
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE1 |
CLK | input | IMUX_CLK1 |
DI | output | OUT_Q1 |
IN | output | OUT_F1 |
IP | output | OUT_F5 |
LSR | input | IMUX_LSR1 |
ONEG | input | IMUX_B1 |
OPOS | input | IMUX_A1 |
TS | input | IMUX_C1 |
Bel IO2
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE2 |
CLK | input | IMUX_CLK2 |
DI | output | OUT_Q2 |
IN | output | OUT_F2 |
IP | output | OUT_F6 |
LSR | input | IMUX_LSR2 |
ONEG | input | IMUX_B2 |
OPOS | input | IMUX_A2 |
TS | input | IMUX_C2 |
TXD0 | input | IMUX_D0 |
TXD1 | input | IMUX_D1 |
TXD2 | input | IMUX_D2 |
TXD3 | input | IMUX_D3 |
Bel IO3
Pin | Direction | Wires |
---|---|---|
CE | input | IMUX_CE3 |
CLK | input | IMUX_CLK3 |
DI | output | OUT_Q3 |
IN | output | OUT_F3 |
IP | output | OUT_F7 |
LSR | input | IMUX_LSR3 |
ONEG | input | IMUX_B3 |
OPOS | input | IMUX_A3 |
TS | input | IMUX_C3 |
Bel wires
Wire | Pins |
---|---|
IMUX_A0 | IO0.OPOS, IO0.TXD0 |
IMUX_A1 | IO0.TXD2, IO1.OPOS |
IMUX_A2 | IO2.OPOS |
IMUX_A3 | IO3.OPOS |
IMUX_B0 | IO0.ONEG, IO0.TXD1 |
IMUX_B1 | IO0.TXD3, IO1.ONEG |
IMUX_B2 | IO2.ONEG |
IMUX_B3 | IO3.ONEG |
IMUX_C0 | IO0.TS |
IMUX_C1 | IO1.TS |
IMUX_C2 | IO2.TS |
IMUX_C3 | IO3.TS |
IMUX_D0 | IO0.TXD4, IO2.TXD0 |
IMUX_D1 | IO0.TXD5, IO2.TXD1 |
IMUX_D2 | IO0.TXD6, IO2.TXD2 |
IMUX_D3 | IO0.TXD7, IO2.TXD3 |
IMUX_CLK0 | IO0.CLK |
IMUX_CLK1 | IO1.CLK |
IMUX_CLK2 | IO2.CLK |
IMUX_CLK3 | IO3.CLK |
IMUX_LSR0 | IO0.LSR |
IMUX_LSR1 | IO1.LSR |
IMUX_LSR2 | IO2.LSR |
IMUX_LSR3 | IO3.LSR |
IMUX_CE0 | IO0.CE |
IMUX_CE1 | IO1.CE |
IMUX_CE2 | IO2.CE |
IMUX_CE3 | IO3.CE |
OUT_F0 | IO0.IN |
OUT_F1 | IO1.IN |
OUT_F2 | IO2.IN |
OUT_F3 | IO3.IN |
OUT_F4 | IO0.IP |
OUT_F5 | IO1.IP |
OUT_F6 | IO2.IP |
OUT_F7 | IO3.IP |
OUT_Q0 | IO0.DI |
OUT_Q1 | IO1.DI |
OUT_Q2 | IO2.DI |
OUT_Q3 | IO3.DI |
Tile DQSDLL_S
Cells: 1
Bel DQSDLL
Pin | Direction | Wires |
---|---|---|
CLK | input | IMUX_CLK0 |
FREEZE | input | IMUX_B0 |
LOCK | output | OUT_F0 |
RST | input | IMUX_LSR0 |
UDDCNTLN | input | IMUX_A0 |
Bel DQSDLLTEST
Pin | Direction | Wires |
---|---|---|
DIVOSC | output | OUT_F1 |
SDOUT0 | output | OUT_Q0 |
SDOUT1 | output | OUT_Q1 |
SDOUT2 | output | OUT_Q2 |
SDOUT3 | output | OUT_Q3 |
SDOUT4 | output | OUT_Q4 |
SDOUT5 | output | OUT_Q5 |
SDOUT6 | output | OUT_Q6 |
Bel wires
Wire | Pins |
---|---|
IMUX_A0 | DQSDLL.UDDCNTLN |
IMUX_B0 | DQSDLL.FREEZE |
IMUX_CLK0 | DQSDLL.CLK |
IMUX_LSR0 | DQSDLL.RST |
OUT_F0 | DQSDLL.LOCK |
OUT_F1 | DQSDLLTEST.DIVOSC |
OUT_Q0 | DQSDLLTEST.SDOUT0 |
OUT_Q1 | DQSDLLTEST.SDOUT1 |
OUT_Q2 | DQSDLLTEST.SDOUT2 |
OUT_Q3 | DQSDLLTEST.SDOUT3 |
OUT_Q4 | DQSDLLTEST.SDOUT4 |
OUT_Q5 | DQSDLLTEST.SDOUT5 |
OUT_Q6 | DQSDLLTEST.SDOUT6 |
Tile DQSDLL_N
Cells: 1
Bel DQSDLL
Pin | Direction | Wires |
---|---|---|
CLK | input | IMUX_CLK0 |
FREEZE | input | IMUX_B0 |
LOCK | output | OUT_F0 |
RST | input | IMUX_LSR0 |
UDDCNTLN | input | IMUX_A0 |
Bel DQSDLLTEST
Pin | Direction | Wires |
---|---|---|
DIVOSC | output | OUT_F1 |
SDOUT0 | output | OUT_Q0 |
SDOUT1 | output | OUT_Q1 |
SDOUT2 | output | OUT_Q2 |
SDOUT3 | output | OUT_Q3 |
SDOUT4 | output | OUT_Q4 |
SDOUT5 | output | OUT_Q5 |
SDOUT6 | output | OUT_Q6 |
Bel wires
Wire | Pins |
---|---|
IMUX_A0 | DQSDLL.UDDCNTLN |
IMUX_B0 | DQSDLL.FREEZE |
IMUX_CLK0 | DQSDLL.CLK |
IMUX_LSR0 | DQSDLL.RST |
OUT_F0 | DQSDLL.LOCK |
OUT_F1 | DQSDLLTEST.DIVOSC |
OUT_Q0 | DQSDLLTEST.SDOUT0 |
OUT_Q1 | DQSDLLTEST.SDOUT1 |
OUT_Q2 | DQSDLLTEST.SDOUT2 |
OUT_Q3 | DQSDLLTEST.SDOUT3 |
OUT_Q4 | DQSDLLTEST.SDOUT4 |
OUT_Q5 | DQSDLLTEST.SDOUT5 |
OUT_Q6 | DQSDLLTEST.SDOUT6 |
Tile BC
Cells: 1
Bel BCPG
Pin | Direction | Wires |
---|---|---|
PGENI | input | IMUX_D5 |
Bel BCINRD
Pin | Direction | Wires |
---|---|---|
INRDENI | input | IMUX_C5 |
Bel wires
Wire | Pins |
---|---|
IMUX_C5 | BCINRD.INRDENI |
IMUX_D5 | BCPG.PGENI |
Tile BC_N
Cells: 1
Bel BCPG
Pin | Direction | Wires |
---|---|---|
PGENI | input | IMUX_D5 |
Bel BCINRD
Pin | Direction | Wires |
---|---|---|
INRDENI | input | IMUX_C5 |
Bel BCLVDSO
Pin | Direction | Wires |
---|---|---|
LVDSENI | input | IMUX_B5 |
Bel wires
Wire | Pins |
---|---|
IMUX_B5 | BCLVDSO.LVDSENI |
IMUX_C5 | BCINRD.INRDENI |
IMUX_D5 | BCPG.PGENI |
Tile BCSR_W
Cells: 1
Bel BCPG
Pin | Direction | Wires |
---|---|---|
PGENI | input | IMUX_D5 |
Bel BCINRD
Pin | Direction | Wires |
---|---|---|
INRDENI | input | IMUX_C5 |
Bel BCSLEWRATE
Pin | Direction | Wires |
---|---|---|
SLEWRATEENI | input | IMUX_D0 |
Bel wires
Wire | Pins |
---|---|
IMUX_C5 | BCINRD.INRDENI |
IMUX_D0 | BCSLEWRATE.SLEWRATEENI |
IMUX_D5 | BCPG.PGENI |
Tile BCSR_E
Cells: 2
Bel BCPG
Pin | Direction | Wires |
---|---|---|
PGENI | input | TCELL0:IMUX_D5 |
Bel BCINRD
Pin | Direction | Wires |
---|---|---|
INRDENI | input | TCELL0:IMUX_C5 |
Bel BCSLEWRATE
Pin | Direction | Wires |
---|---|---|
SLEWRATEENI | input | TCELL1:IMUX_D0 |
Bel wires
Wire | Pins |
---|---|
TCELL0:IMUX_C5 | BCINRD.INRDENI |
TCELL0:IMUX_D5 | BCPG.PGENI |
TCELL1:IMUX_D0 | BCSLEWRATE.SLEWRATEENI |
Tile BCSR_S
Cells: 1
Bel BCPG
Pin | Direction | Wires |
---|---|---|
PGENI | input | IMUX_D5 |
Bel BCINRD
Pin | Direction | Wires |
---|---|---|
INRDENI | input | IMUX_C5 |
Bel BCSLEWRATE
Pin | Direction | Wires |
---|---|---|
SLEWRATEENI | input | IMUX_A5 |
Bel wires
Wire | Pins |
---|---|
IMUX_A5 | BCSLEWRATE.SLEWRATEENI |
IMUX_C5 | BCINRD.INRDENI |
IMUX_D5 | BCPG.PGENI |
Tile BCSR_N
Cells: 1
Bel BCPG
Pin | Direction | Wires |
---|---|---|
PGENI | input | IMUX_D5 |
Bel BCINRD
Pin | Direction | Wires |
---|---|---|
INRDENI | input | IMUX_C5 |
Bel BCLVDSO
Pin | Direction | Wires |
---|---|---|
LVDSENI | input | IMUX_B5 |
Bel BCSLEWRATE
Pin | Direction | Wires |
---|---|---|
SLEWRATEENI | input | IMUX_A5 |
Bel wires
Wire | Pins |
---|---|
IMUX_A5 | BCSLEWRATE.SLEWRATEENI |
IMUX_B5 | BCLVDSO.LVDSENI |
IMUX_C5 | BCINRD.INRDENI |
IMUX_D5 | BCPG.PGENI |