Cells: 3
siliconblue WARMBOOT bel WARMBOOT
Pin | Direction | Wires |
BOOT | input | TCELL0:IMUX.IO.EXTRA |
S0 | input | TCELL1:IMUX.IO.EXTRA |
S1 | input | TCELL2:IMUX.IO.EXTRA |
siliconblue WARMBOOT bel wires
Wire | Pins |
TCELL0:IMUX.IO.EXTRA | WARMBOOT.BOOT |
TCELL1:IMUX.IO.EXTRA | WARMBOOT.S0 |
TCELL2:IMUX.IO.EXTRA | WARMBOOT.S1 |
Cells: 1
siliconblue WARMBOOT_T01 bel WARMBOOT
Pin | Direction | Wires |
BOOT | input | IMUX.LC3.I1 |
S0 | input | IMUX.LC4.I1 |
S1 | input | IMUX.LC5.I1 |
siliconblue WARMBOOT_T01 bel wires
Wire | Pins |
IMUX.LC3.I1 | WARMBOOT.BOOT |
IMUX.LC4.I1 | WARMBOOT.S0 |
IMUX.LC5.I1 | WARMBOOT.S1 |
Cells: 1
siliconblue SMCCLK_T04 bel SMCCLK
Pin | Direction | Wires |
CLK | output | OUT.LC5 |
siliconblue SMCCLK_T04 bel wires
Wire | Pins |
OUT.LC5 | SMCCLK.CLK |
Cells: 1
siliconblue SMCCLK_T05 bel SMCCLK
Pin | Direction | Wires |
CLK | output | OUT.LC1 |
siliconblue SMCCLK_T05 bel wires
Wire | Pins |
OUT.LC1 | SMCCLK.CLK |
Cells: 1
siliconblue SMCCLK_T01 bel SMCCLK
Pin | Direction | Wires |
CLK | output | OUT.LC2 |
siliconblue SMCCLK_T01 bel wires
Wire | Pins |
OUT.LC2 | SMCCLK.CLK |