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Led drivers

Tile LED_DRV_CUR_T04

Cells: 2

Bel LED_DRV_CUR

siliconblue LED_DRV_CUR_T04 bel LED_DRV_CUR
PinDirectionWires
ENinputTCELL1:IMUX.LC6.I3
TRIM0inputTCELL0:IMUX.LC0.I3
TRIM1inputTCELL0:IMUX.LC1.I3
TRIM2inputTCELL0:IMUX.LC2.I3
TRIM3inputTCELL0:IMUX.LC3.I3
TRIM4inputTCELL0:IMUX.LC4.I3
TRIM5inputTCELL0:IMUX.LC5.I3
TRIM6inputTCELL0:IMUX.LC6.I3
TRIM7inputTCELL0:IMUX.LC7.I3
TRIM8inputTCELL0:IMUX.LC0.I1
TRIM9inputTCELL0:IMUX.LC1.I1

Bel wires

siliconblue LED_DRV_CUR_T04 bel wires
WirePins
TCELL0:IMUX.LC0.I1LED_DRV_CUR.TRIM8
TCELL0:IMUX.LC0.I3LED_DRV_CUR.TRIM0
TCELL0:IMUX.LC1.I1LED_DRV_CUR.TRIM9
TCELL0:IMUX.LC1.I3LED_DRV_CUR.TRIM1
TCELL0:IMUX.LC2.I3LED_DRV_CUR.TRIM2
TCELL0:IMUX.LC3.I3LED_DRV_CUR.TRIM3
TCELL0:IMUX.LC4.I3LED_DRV_CUR.TRIM4
TCELL0:IMUX.LC5.I3LED_DRV_CUR.TRIM5
TCELL0:IMUX.LC6.I3LED_DRV_CUR.TRIM6
TCELL0:IMUX.LC7.I3LED_DRV_CUR.TRIM7
TCELL1:IMUX.LC6.I3LED_DRV_CUR.EN

Bitstream

siliconblue LED_DRV_CUR_T04 bittile 0
FrameBit
siliconblue LED_DRV_CUR_T04 bittile 1
FrameBit
0 1 2 3 4 5 6 7
0 - - - - - - - -
1 - - - - - - - -
2 - - - - - - - -
3 - - - - - - - -
4 - - - - - - - LED_DRV_CUR:ENABLE
LED_DRV_CUR:ENABLE 1.4.7
non-inverted [0]

Tile LED_DRV_CUR_T05

Cells: 2

Bel LED_DRV_CUR

siliconblue LED_DRV_CUR_T05 bel LED_DRV_CUR
PinDirectionWires
ENinputTCELL1:IMUX.LC6.I3
TRIM0inputTCELL0:IMUX.LC0.I3
TRIM1inputTCELL0:IMUX.LC1.I3
TRIM2inputTCELL0:IMUX.LC2.I3
TRIM3inputTCELL0:IMUX.LC3.I3
TRIM4inputTCELL0:IMUX.LC4.I3
TRIM5inputTCELL0:IMUX.LC5.I3
TRIM6inputTCELL0:IMUX.LC6.I3
TRIM7inputTCELL0:IMUX.LC7.I3
TRIM8inputTCELL0:IMUX.LC0.I1
TRIM9inputTCELL0:IMUX.LC1.I1

Bel wires

siliconblue LED_DRV_CUR_T05 bel wires
WirePins
TCELL0:IMUX.LC0.I1LED_DRV_CUR.TRIM8
TCELL0:IMUX.LC0.I3LED_DRV_CUR.TRIM0
TCELL0:IMUX.LC1.I1LED_DRV_CUR.TRIM9
TCELL0:IMUX.LC1.I3LED_DRV_CUR.TRIM1
TCELL0:IMUX.LC2.I3LED_DRV_CUR.TRIM2
TCELL0:IMUX.LC3.I3LED_DRV_CUR.TRIM3
TCELL0:IMUX.LC4.I3LED_DRV_CUR.TRIM4
TCELL0:IMUX.LC5.I3LED_DRV_CUR.TRIM5
TCELL0:IMUX.LC6.I3LED_DRV_CUR.TRIM6
TCELL0:IMUX.LC7.I3LED_DRV_CUR.TRIM7
TCELL1:IMUX.LC6.I3LED_DRV_CUR.EN

Tile LED_DRV_CUR_T01

Cells: 1

Bel LED_DRV_CUR

siliconblue LED_DRV_CUR_T01 bel LED_DRV_CUR
PinDirectionWires
ENinputIMUX.LC0.I1
TRIM0inputIMUX.LC1.I1
TRIM1inputIMUX.LC2.I1
TRIM2inputIMUX.LC3.I1
TRIM3inputIMUX.LC4.I1
TRIM4inputIMUX.LC5.I1
TRIM5inputIMUX.LC6.I1
TRIM6inputIMUX.LC7.I1
TRIM7inputIMUX.LC0.I0
TRIM8inputIMUX.LC1.I0
TRIM9inputIMUX.LC2.I0

Bel wires

siliconblue LED_DRV_CUR_T01 bel wires
WirePins
IMUX.LC0.I0LED_DRV_CUR.TRIM7
IMUX.LC0.I1LED_DRV_CUR.EN
IMUX.LC1.I0LED_DRV_CUR.TRIM8
IMUX.LC1.I1LED_DRV_CUR.TRIM0
IMUX.LC2.I0LED_DRV_CUR.TRIM9
IMUX.LC2.I1LED_DRV_CUR.TRIM1
IMUX.LC3.I1LED_DRV_CUR.TRIM2
IMUX.LC4.I1LED_DRV_CUR.TRIM3
IMUX.LC5.I1LED_DRV_CUR.TRIM4
IMUX.LC6.I1LED_DRV_CUR.TRIM5
IMUX.LC7.I1LED_DRV_CUR.TRIM6

Tile RGB_DRV

Cells: 3

Bel RGB_DRV

siliconblue RGB_DRV bel RGB_DRV
PinDirectionWires
RGB0PWMinputTCELL2:IMUX.LC2.I1
RGB1PWMinputTCELL2:IMUX.LC3.I1
RGB2PWMinputTCELL2:IMUX.LC4.I1
RGBLEDENinputTCELL2:IMUX.LC1.I1

Bel wires

siliconblue RGB_DRV bel wires
WirePins
TCELL2:IMUX.LC1.I1RGB_DRV.RGBLEDEN
TCELL2:IMUX.LC2.I1RGB_DRV.RGB0PWM
TCELL2:IMUX.LC3.I1RGB_DRV.RGB1PWM
TCELL2:IMUX.LC4.I1RGB_DRV.RGB2PWM

Bitstream

siliconblue RGB_DRV bittile 0
FrameBit
0 1 2 3 4 5 6 7
0 - - - - - - - -
1 - - - - - - - -
2 - - - - - - - -
3 - - - - - - - -
4 - - - - - - - RGB_DRV:ENABLE
5 - - - - - - - -
6 - - - - - - - RGB_DRV:RGB0_CURRENT[1]
7 - - - - - - - RGB_DRV:RGB0_CURRENT[0]
siliconblue RGB_DRV bittile 1
FrameBit
0 1 2 3 4 5 6 7
0 - - - - - - - RGB_DRV:RGB0_CURRENT[3]
1 - - - - - - - RGB_DRV:RGB0_CURRENT[2]
2 - - - - - - - RGB_DRV:RGB0_CURRENT[5]
3 - - - - - - - RGB_DRV:RGB0_CURRENT[4]
4 - - - - - - - RGB_DRV:RGB1_CURRENT[1]
5 - - - - - - - RGB_DRV:RGB1_CURRENT[0]
6 - - - - - - - RGB_DRV:RGB1_CURRENT[3]
7 - - - - - - - RGB_DRV:RGB1_CURRENT[2]
siliconblue RGB_DRV bittile 2
FrameBit
0 1 2 3 4 5 6 7
0 - - - - - - - RGB_DRV:RGB1_CURRENT[5]
1 - - - - - - - RGB_DRV:RGB1_CURRENT[4]
2 - - - - - - - RGB_DRV:RGB2_CURRENT[1]
3 - - - - - - - RGB_DRV:RGB2_CURRENT[0]
4 - - - - - - - RGB_DRV:RGB2_CURRENT[3]
5 - - - - - - - RGB_DRV:RGB2_CURRENT[2]
6 - - - - - - - RGB_DRV:RGB2_CURRENT[5]
7 - - - - - - - RGB_DRV:RGB2_CURRENT[4]
RGB_DRV:ENABLE 0.4.7
non-inverted [0]
RGB_DRV:RGB0_CURRENT 1.2.7 1.3.7 1.0.7 1.1.7 0.6.7 0.7.7
RGB_DRV:RGB1_CURRENT 2.0.7 2.1.7 1.6.7 1.7.7 1.4.7 1.5.7
RGB_DRV:RGB2_CURRENT 2.6.7 2.7.7 2.4.7 2.5.7 2.2.7 2.3.7
non-inverted [5] [4] [3] [2] [1] [0]

Tile LEDD_IP

Cells: 2

Bel LEDD_IP

siliconblue LEDD_IP bel LEDD_IP
PinDirectionWires
LEDDADDR0inputTCELL0:IMUX.LC4.I0
LEDDADDR1inputTCELL0:IMUX.LC5.I0
LEDDADDR2inputTCELL0:IMUX.LC6.I0
LEDDADDR3inputTCELL0:IMUX.LC7.I0
LEDDCLKinputTCELL0:IMUX.LC3.I0
LEDDCSinputTCELL0:IMUX.LC2.I0
LEDDDAT0inputTCELL0:IMUX.LC2.I1
LEDDDAT1inputTCELL0:IMUX.LC3.I1
LEDDDAT2inputTCELL0:IMUX.LC4.I1
LEDDDAT3inputTCELL0:IMUX.LC5.I1
LEDDDAT4inputTCELL0:IMUX.LC6.I1
LEDDDAT5inputTCELL0:IMUX.LC7.I1
LEDDDAT6inputTCELL0:IMUX.LC0.I0
LEDDDAT7inputTCELL0:IMUX.LC1.I0
LEDDDENinputTCELL0:IMUX.LC1.I1
LEDDEXEinputTCELL0:IMUX.LC0.I1
LEDDONoutputTCELL1:OUT.LC0
PWMOUT0outputTCELL0:OUT.LC4
PWMOUT1outputTCELL0:OUT.LC5
PWMOUT2outputTCELL0:OUT.LC6

Bel wires

siliconblue LEDD_IP bel wires
WirePins
TCELL0:IMUX.LC0.I0LEDD_IP.LEDDDAT6
TCELL0:IMUX.LC0.I1LEDD_IP.LEDDEXE
TCELL0:IMUX.LC1.I0LEDD_IP.LEDDDAT7
TCELL0:IMUX.LC1.I1LEDD_IP.LEDDDEN
TCELL0:IMUX.LC2.I0LEDD_IP.LEDDCS
TCELL0:IMUX.LC2.I1LEDD_IP.LEDDDAT0
TCELL0:IMUX.LC3.I0LEDD_IP.LEDDCLK
TCELL0:IMUX.LC3.I1LEDD_IP.LEDDDAT1
TCELL0:IMUX.LC4.I0LEDD_IP.LEDDADDR0
TCELL0:IMUX.LC4.I1LEDD_IP.LEDDDAT2
TCELL0:IMUX.LC5.I0LEDD_IP.LEDDADDR1
TCELL0:IMUX.LC5.I1LEDD_IP.LEDDDAT3
TCELL0:IMUX.LC6.I0LEDD_IP.LEDDADDR2
TCELL0:IMUX.LC6.I1LEDD_IP.LEDDDAT4
TCELL0:IMUX.LC7.I0LEDD_IP.LEDDADDR3
TCELL0:IMUX.LC7.I1LEDD_IP.LEDDDAT5
TCELL0:OUT.LC4LEDD_IP.PWMOUT0
TCELL0:OUT.LC5LEDD_IP.PWMOUT1
TCELL0:OUT.LC6LEDD_IP.PWMOUT2
TCELL1:OUT.LC0LEDD_IP.LEDDON

Tile IR_DRV

Cells: 3

Bel IR_DRV

siliconblue IR_DRV bel IR_DRV
PinDirectionWires
IRLEDENinputTCELL0:IMUX.LC7.I0
IRPWMinputTCELL0:IMUX.LC6.I0

Bel wires

siliconblue IR_DRV bel wires
WirePins
TCELL0:IMUX.LC6.I0IR_DRV.IRPWM
TCELL0:IMUX.LC7.I0IR_DRV.IRLEDEN

Bitstream

siliconblue IR_DRV bittile 0
FrameBit
siliconblue IR_DRV bittile 1
FrameBit
0 1 2 3 4 5 6 7
0 - - - - - - - -
1 - - - - - - - -
2 - - - - - - - -
3 - - - - - - - -
4 - - - - - - - -
5 - - - - - - - IR_DRV:ENABLE
6 - - - - - - - IR_DRV:IR_CURRENT[1]
7 - - - - - - - IR_DRV:IR_CURRENT[0]
siliconblue IR_DRV bittile 2
FrameBit
0 1 2 3 4 5 6 7
0 - - - - - - - IR_DRV:IR_CURRENT[3]
1 - - - - - - - IR_DRV:IR_CURRENT[2]
2 - - - - - - - IR_DRV:IR_CURRENT[5]
3 - - - - - - - IR_DRV:IR_CURRENT[4]
4 - - - - - - - IR_DRV:IR_CURRENT[7]
5 - - - - - - - IR_DRV:IR_CURRENT[6]
6 - - - - - - - IR_DRV:IR_CURRENT[9]
7 - - - - - - - IR_DRV:IR_CURRENT[8]
IR_DRV:ENABLE 1.5.7
non-inverted [0]
IR_DRV:IR_CURRENT 2.6.7 2.7.7 2.4.7 2.5.7 2.2.7 2.3.7 2.0.7 2.1.7 1.6.7 1.7.7
non-inverted [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

Tile RGBA_DRV_T05

Cells: 3

Bel RGBA_DRV

siliconblue RGBA_DRV_T05 bel RGBA_DRV
PinDirectionWires
RGB0PWMinputTCELL2:IMUX.LC2.I1
RGB1PWMinputTCELL2:IMUX.LC3.I1
RGB2PWMinputTCELL2:IMUX.LC4.I1
RGBLEDENinputTCELL2:IMUX.LC1.I1

Bel wires

siliconblue RGBA_DRV_T05 bel wires
WirePins
TCELL2:IMUX.LC1.I1RGBA_DRV.RGBLEDEN
TCELL2:IMUX.LC2.I1RGBA_DRV.RGB0PWM
TCELL2:IMUX.LC3.I1RGBA_DRV.RGB1PWM
TCELL2:IMUX.LC4.I1RGBA_DRV.RGB2PWM

Bitstream

siliconblue RGBA_DRV_T05 bittile 0
FrameBit
0 1 2 3 4 5 6 7
0 - - - - - - - -
1 - - - - - - - -
2 - - - - - - - -
3 - - - - - - - -
4 - - - - - - - RGBA_DRV:ENABLE
5 - - - - - - - RGBA_DRV:CURRENT_MODE
6 - - - - - - - RGBA_DRV:RGB0_CURRENT[1]
7 - - - - - - - RGBA_DRV:RGB0_CURRENT[0]
siliconblue RGBA_DRV_T05 bittile 1
FrameBit
0 1 2 3 4 5 6 7
0 - - - - - - - RGBA_DRV:RGB0_CURRENT[3]
1 - - - - - - - RGBA_DRV:RGB0_CURRENT[2]
2 - - - - - - - RGBA_DRV:RGB0_CURRENT[5]
3 - - - - - - - RGBA_DRV:RGB0_CURRENT[4]
4 - - - - - - - RGBA_DRV:RGB1_CURRENT[1]
5 - - - - - - - RGBA_DRV:RGB1_CURRENT[0]
6 - - - - - - - RGBA_DRV:RGB1_CURRENT[3]
7 - - - - - - - RGBA_DRV:RGB1_CURRENT[2]
siliconblue RGBA_DRV_T05 bittile 2
FrameBit
0 1 2 3 4 5 6 7
0 - - - - - - - RGBA_DRV:RGB1_CURRENT[5]
1 - - - - - - - RGBA_DRV:RGB1_CURRENT[4]
2 - - - - - - - RGBA_DRV:RGB2_CURRENT[1]
3 - - - - - - - RGBA_DRV:RGB2_CURRENT[0]
4 - - - - - - - RGBA_DRV:RGB2_CURRENT[3]
5 - - - - - - - RGBA_DRV:RGB2_CURRENT[2]
6 - - - - - - - RGBA_DRV:RGB2_CURRENT[5]
7 - - - - - - - RGBA_DRV:RGB2_CURRENT[4]
RGBA_DRV:CURRENT_MODE 0.5.7
RGBA_DRV:ENABLE 0.4.7
non-inverted [0]
RGBA_DRV:RGB0_CURRENT 1.2.7 1.3.7 1.0.7 1.1.7 0.6.7 0.7.7
RGBA_DRV:RGB1_CURRENT 2.0.7 2.1.7 1.6.7 1.7.7 1.4.7 1.5.7
RGBA_DRV:RGB2_CURRENT 2.6.7 2.7.7 2.4.7 2.5.7 2.2.7 2.3.7
non-inverted [5] [4] [3] [2] [1] [0]

Tile RGBA_DRV_T01

Cells: 4

Bel RGBA_DRV

siliconblue RGBA_DRV_T01 bel RGBA_DRV
PinDirectionWires
RGB0PWMinputTCELL3:IMUX.LC5.I0
RGB1PWMinputTCELL3:IMUX.LC6.I0
RGB2PWMinputTCELL3:IMUX.LC7.I0
RGBLEDENinputTCELL1:IMUX.LC1.I1

Bel wires

siliconblue RGBA_DRV_T01 bel wires
WirePins
TCELL1:IMUX.LC1.I1RGBA_DRV.RGBLEDEN
TCELL3:IMUX.LC5.I0RGBA_DRV.RGB0PWM
TCELL3:IMUX.LC6.I0RGBA_DRV.RGB1PWM
TCELL3:IMUX.LC7.I0RGBA_DRV.RGB2PWM

Bitstream

siliconblue RGBA_DRV_T01 bittile 0
FrameBit
0 1 2 3 4 5 6 7
0 - - - - - - - RGBA_DRV:RGB0_CURRENT[0]
1 - - - - - - - RGBA_DRV:ENABLE
2 - - - - - - - RGBA_DRV:RGB0_CURRENT[2]
3 - - - - - - - RGBA_DRV:RGB0_CURRENT[1]
4 - - - - - - - RGBA_DRV:RGB0_CURRENT[4]
5 - - - - - - - RGBA_DRV:RGB0_CURRENT[3]
6 - - - - - - - RGBA_DRV:RGB1_CURRENT[0]
7 - - - - - - - RGBA_DRV:RGB0_CURRENT[5]
siliconblue RGBA_DRV_T01 bittile 1
FrameBit
0 1 2 3 4 5 6 7
0 - - - - - - - RGBA_DRV:RGB1_CURRENT[2]
1 - - - - - - - RGBA_DRV:RGB1_CURRENT[1]
2 - - - - - - - RGBA_DRV:RGB1_CURRENT[4]
3 - - - - - - - RGBA_DRV:RGB1_CURRENT[3]
4 - - - - - - - RGBA_DRV:RGB2_CURRENT[0]
5 - - - - - - - RGBA_DRV:RGB1_CURRENT[5]
6 - - - - - - - RGBA_DRV:RGB2_CURRENT[2]
7 - - - - - - - RGBA_DRV:RGB2_CURRENT[1]
siliconblue RGBA_DRV_T01 bittile 2
FrameBit
0 1 2 3 4 5 6 7
0 - - - - - - - RGBA_DRV:RGB2_CURRENT[4]
1 - - - - - - - RGBA_DRV:RGB2_CURRENT[3]
2 - - - - - - - RGBA_DRV:CURRENT_MODE
3 - - - - - - - RGBA_DRV:RGB2_CURRENT[5]
RGBA_DRV:CURRENT_MODE 2.2.7
RGBA_DRV:ENABLE 0.1.7
non-inverted [0]
RGBA_DRV:RGB0_CURRENT 0.7.7 0.4.7 0.5.7 0.2.7 0.3.7 0.0.7
RGBA_DRV:RGB1_CURRENT 1.5.7 1.2.7 1.3.7 1.0.7 1.1.7 0.6.7
RGBA_DRV:RGB2_CURRENT 2.3.7 2.0.7 2.1.7 1.6.7 1.7.7 1.4.7
non-inverted [5] [4] [3] [2] [1] [0]

Tile LEDDA_IP_T05

Cells: 2

Bel LEDDA_IP

siliconblue LEDDA_IP_T05 bel LEDDA_IP
PinDirectionWires
LEDDADDR0inputTCELL0:IMUX.LC4.I0
LEDDADDR1inputTCELL0:IMUX.LC5.I0
LEDDADDR2inputTCELL0:IMUX.LC6.I0
LEDDADDR3inputTCELL0:IMUX.LC7.I0
LEDDCLKinputTCELL1:IMUX.CLK.OPTINV
LEDDCSinputTCELL0:IMUX.LC2.I0
LEDDDAT0inputTCELL0:IMUX.LC2.I1
LEDDDAT1inputTCELL0:IMUX.LC3.I1
LEDDDAT2inputTCELL0:IMUX.LC4.I1
LEDDDAT3inputTCELL0:IMUX.LC5.I1
LEDDDAT4inputTCELL0:IMUX.LC6.I1
LEDDDAT5inputTCELL0:IMUX.LC7.I1
LEDDDAT6inputTCELL0:IMUX.LC0.I0
LEDDDAT7inputTCELL0:IMUX.LC1.I0
LEDDDENinputTCELL0:IMUX.LC1.I1
LEDDEXEinputTCELL0:IMUX.LC0.I1
LEDDONoutputTCELL1:OUT.LC0
PWMOUT0outputTCELL0:OUT.LC4
PWMOUT1outputTCELL0:OUT.LC5
PWMOUT2outputTCELL0:OUT.LC6

Bel wires

siliconblue LEDDA_IP_T05 bel wires
WirePins
TCELL0:IMUX.LC0.I0LEDDA_IP.LEDDDAT6
TCELL0:IMUX.LC0.I1LEDDA_IP.LEDDEXE
TCELL0:IMUX.LC1.I0LEDDA_IP.LEDDDAT7
TCELL0:IMUX.LC1.I1LEDDA_IP.LEDDDEN
TCELL0:IMUX.LC2.I0LEDDA_IP.LEDDCS
TCELL0:IMUX.LC2.I1LEDDA_IP.LEDDDAT0
TCELL0:IMUX.LC3.I1LEDDA_IP.LEDDDAT1
TCELL0:IMUX.LC4.I0LEDDA_IP.LEDDADDR0
TCELL0:IMUX.LC4.I1LEDDA_IP.LEDDDAT2
TCELL0:IMUX.LC5.I0LEDDA_IP.LEDDADDR1
TCELL0:IMUX.LC5.I1LEDDA_IP.LEDDDAT3
TCELL0:IMUX.LC6.I0LEDDA_IP.LEDDADDR2
TCELL0:IMUX.LC6.I1LEDDA_IP.LEDDDAT4
TCELL0:IMUX.LC7.I0LEDDA_IP.LEDDADDR3
TCELL0:IMUX.LC7.I1LEDDA_IP.LEDDDAT5
TCELL0:OUT.LC4LEDDA_IP.PWMOUT0
TCELL0:OUT.LC5LEDDA_IP.PWMOUT1
TCELL0:OUT.LC6LEDDA_IP.PWMOUT2
TCELL1:IMUX.CLK.OPTINVLEDDA_IP.LEDDCLK
TCELL1:OUT.LC0LEDDA_IP.LEDDON

Tile LEDDA_IP_T01

Cells: 4

Bel LEDDA_IP

siliconblue LEDDA_IP_T01 bel LEDDA_IP
PinDirectionWires
LEDDADDR0inputTCELL0:IMUX.LC6.I0
LEDDADDR1inputTCELL0:IMUX.LC7.I0
LEDDADDR2inputTCELL1:IMUX.LC0.I3
LEDDADDR3inputTCELL1:IMUX.LC1.I3
LEDDCLKinputTCELL3:IMUX.CLK.OPTINV
LEDDCSinputTCELL0:IMUX.LC4.I0
LEDDDAT0inputTCELL0:IMUX.LC4.I1
LEDDDAT1inputTCELL0:IMUX.LC5.I1
LEDDDAT2inputTCELL0:IMUX.LC6.I1
LEDDDAT3inputTCELL0:IMUX.LC7.I1
LEDDDAT4inputTCELL0:IMUX.LC0.I0
LEDDDAT5inputTCELL0:IMUX.LC1.I0
LEDDDAT6inputTCELL0:IMUX.LC2.I0
LEDDDAT7inputTCELL0:IMUX.LC3.I0
LEDDDENinputTCELL0:IMUX.LC3.I1
LEDDEXEinputTCELL0:IMUX.LC2.I1
LEDDONoutputTCELL2:OUT.LC2
PWMOUT0outputTCELL2:OUT.LC3
PWMOUT1outputTCELL2:OUT.LC4
PWMOUT2outputTCELL2:OUT.LC5

Bel wires

siliconblue LEDDA_IP_T01 bel wires
WirePins
TCELL0:IMUX.LC0.I0LEDDA_IP.LEDDDAT4
TCELL0:IMUX.LC1.I0LEDDA_IP.LEDDDAT5
TCELL0:IMUX.LC2.I0LEDDA_IP.LEDDDAT6
TCELL0:IMUX.LC2.I1LEDDA_IP.LEDDEXE
TCELL0:IMUX.LC3.I0LEDDA_IP.LEDDDAT7
TCELL0:IMUX.LC3.I1LEDDA_IP.LEDDDEN
TCELL0:IMUX.LC4.I0LEDDA_IP.LEDDCS
TCELL0:IMUX.LC4.I1LEDDA_IP.LEDDDAT0
TCELL0:IMUX.LC5.I1LEDDA_IP.LEDDDAT1
TCELL0:IMUX.LC6.I0LEDDA_IP.LEDDADDR0
TCELL0:IMUX.LC6.I1LEDDA_IP.LEDDDAT2
TCELL0:IMUX.LC7.I0LEDDA_IP.LEDDADDR1
TCELL0:IMUX.LC7.I1LEDDA_IP.LEDDDAT3
TCELL1:IMUX.LC0.I3LEDDA_IP.LEDDADDR2
TCELL1:IMUX.LC1.I3LEDDA_IP.LEDDADDR3
TCELL2:OUT.LC2LEDDA_IP.LEDDON
TCELL2:OUT.LC3LEDDA_IP.PWMOUT0
TCELL2:OUT.LC4LEDDA_IP.PWMOUT1
TCELL2:OUT.LC5LEDDA_IP.PWMOUT2
TCELL3:IMUX.CLK.OPTINVLEDDA_IP.LEDDCLK

Tile IR500_DRV

Cells: 4

Bel IR400_DRV

siliconblue IR500_DRV bel IR400_DRV
PinDirectionWires
IRLEDENinputTCELL1:IMUX.LC4.I0
IRPWMinputTCELL3:IMUX.LC7.I0

Bel BARCODE_DRV

siliconblue IR500_DRV bel BARCODE_DRV
PinDirectionWires
BARCODEENinputTCELL1:IMUX.LC3.I0
BARCODEPWMinputTCELL3:IMUX.LC6.I0

Bel wires

siliconblue IR500_DRV bel wires
WirePins
TCELL1:IMUX.LC3.I0BARCODE_DRV.BARCODEEN
TCELL1:IMUX.LC4.I0IR400_DRV.IRLEDEN
TCELL3:IMUX.LC6.I0BARCODE_DRV.BARCODEPWM
TCELL3:IMUX.LC7.I0IR400_DRV.IRPWM

Bitstream

siliconblue IR500_DRV bittile 0
FrameBit
0 1 2 3 4 5 6 7
0 - - - - - - - RGBA_DRV:ENABLE
1 - - - - - - - IR400_DRV:ENABLE
2 - - - - - - - BARCODE_DRV:BARCODE_CURRENT[1]
3 - - - - - - - BARCODE_DRV:BARCODE_CURRENT[0]
4 - - - - - - - BARCODE_DRV:BARCODE_CURRENT[3]
5 - - - - - - - BARCODE_DRV:BARCODE_CURRENT[2]
6 - - - - - - - IR400_DRV:IR400_CURRENT[1]
7 - - - - - - - IR400_DRV:IR400_CURRENT[0]
siliconblue IR500_DRV bittile 1
FrameBit
0 1 2 3 4 5 6 7
0 - - - - - - - IR400_DRV:IR400_CURRENT[3]
1 - - - - - - - IR400_DRV:IR400_CURRENT[2]
2 - - - - - - - IR400_DRV:IR400_CURRENT[5]
3 - - - - - - - IR400_DRV:IR400_CURRENT[4]
4 - - - - - - - IR400_DRV:IR400_CURRENT[7]
5 - - - - - - - IR400_DRV:IR400_CURRENT[6]
6 - - - - - - - BARCODE_DRV:ENABLE
7 - - - - - - - IR500_DRV:CURRENT_MODE
siliconblue IR500_DRV bittile 2
FrameBit
0 1 2 3 4 5 6 7
0 - - - - - - - -
1 - - - - - - - IR500_DRV:ENABLE
BARCODE_DRV:BARCODE_CURRENT 0.4.7 0.5.7 0.2.7 0.3.7
non-inverted [3] [2] [1] [0]
BARCODE_DRV:ENABLE 1.6.7
IR400_DRV:ENABLE 0.1.7
IR500_DRV:CURRENT_MODE 1.7.7
IR500_DRV:ENABLE 2.1.7
RGBA_DRV:ENABLE 0.0.7
non-inverted [0]
IR400_DRV:IR400_CURRENT 1.4.7 1.5.7 1.2.7 1.3.7 1.0.7 1.1.7 0.6.7 0.7.7
non-inverted [7] [6] [5] [4] [3] [2] [1] [0]

Tile IR_IP

Cells: 4

Bel IR_IP

siliconblue IR_IP bel IR_IP
PinDirectionWires
ADRI0inputTCELL1:IMUX.LC2.I3
ADRI1inputTCELL1:IMUX.LC3.I3
ADRI2inputTCELL1:IMUX.LC4.I3
ADRI3inputTCELL1:IMUX.LC5.I3
BUSYoutputTCELL1:OUT.LC3
CLKIinputTCELL3:IMUX.CLK.OPTINV
CSIinputTCELL1:IMUX.LC0.I1
DENIinputTCELL1:IMUX.LC7.I3
DRDYoutputTCELL1:OUT.LC4
ERRoutputTCELL1:OUT.LC5
EXEinputTCELL1:IMUX.LC2.I1
IRINinputTCELL0:IMUX.LC0.I0
IROUToutputTCELL2:OUT.LC6
LEARNinputTCELL0:IMUX.LC1.I0
RDATA0outputTCELL1:OUT.LC6
RDATA1outputTCELL1:OUT.LC7
RDATA2outputTCELL2:OUT.LC0
RDATA3outputTCELL2:OUT.LC1
RDATA4outputTCELL2:OUT.LC2
RDATA5outputTCELL2:OUT.LC3
RDATA6outputTCELL2:OUT.LC4
RDATA7outputTCELL2:OUT.LC5
WDATA0inputTCELL0:IMUX.LC2.I0
WDATA1inputTCELL0:IMUX.LC3.I0
WDATA2inputTCELL0:IMUX.LC4.I0
WDATA3inputTCELL0:IMUX.LC5.I0
WDATA4inputTCELL0:IMUX.LC6.I0
WDATA5inputTCELL0:IMUX.LC7.I0
WDATA6inputTCELL1:IMUX.LC0.I3
WDATA7inputTCELL1:IMUX.LC1.I3
WEIinputTCELL1:IMUX.LC6.I3

Bel wires

siliconblue IR_IP bel wires
WirePins
TCELL0:IMUX.LC0.I0IR_IP.IRIN
TCELL0:IMUX.LC1.I0IR_IP.LEARN
TCELL0:IMUX.LC2.I0IR_IP.WDATA0
TCELL0:IMUX.LC3.I0IR_IP.WDATA1
TCELL0:IMUX.LC4.I0IR_IP.WDATA2
TCELL0:IMUX.LC5.I0IR_IP.WDATA3
TCELL0:IMUX.LC6.I0IR_IP.WDATA4
TCELL0:IMUX.LC7.I0IR_IP.WDATA5
TCELL1:IMUX.LC0.I1IR_IP.CSI
TCELL1:IMUX.LC0.I3IR_IP.WDATA6
TCELL1:IMUX.LC1.I3IR_IP.WDATA7
TCELL1:IMUX.LC2.I1IR_IP.EXE
TCELL1:IMUX.LC2.I3IR_IP.ADRI0
TCELL1:IMUX.LC3.I3IR_IP.ADRI1
TCELL1:IMUX.LC4.I3IR_IP.ADRI2
TCELL1:IMUX.LC5.I3IR_IP.ADRI3
TCELL1:IMUX.LC6.I3IR_IP.WEI
TCELL1:IMUX.LC7.I3IR_IP.DENI
TCELL1:OUT.LC3IR_IP.BUSY
TCELL1:OUT.LC4IR_IP.DRDY
TCELL1:OUT.LC5IR_IP.ERR
TCELL1:OUT.LC6IR_IP.RDATA0
TCELL1:OUT.LC7IR_IP.RDATA1
TCELL2:OUT.LC0IR_IP.RDATA2
TCELL2:OUT.LC1IR_IP.RDATA3
TCELL2:OUT.LC2IR_IP.RDATA4
TCELL2:OUT.LC3IR_IP.RDATA5
TCELL2:OUT.LC4IR_IP.RDATA6
TCELL2:OUT.LC5IR_IP.RDATA7
TCELL2:OUT.LC6IR_IP.IROUT
TCELL3:IMUX.CLK.OPTINVIR_IP.CLKI