Led drivers
Tile LED_DRV_CUR_T04
Cells: 2 IRIs: 0
Bel LED_DRV_CUR
Pin | Direction | Wires |
---|---|---|
EN | input | TCELL1:IMUX.LC6.I3 |
TRIM0 | input | TCELL0:IMUX.LC0.I3 |
TRIM1 | input | TCELL0:IMUX.LC1.I3 |
TRIM2 | input | TCELL0:IMUX.LC2.I3 |
TRIM3 | input | TCELL0:IMUX.LC3.I3 |
TRIM4 | input | TCELL0:IMUX.LC4.I3 |
TRIM5 | input | TCELL0:IMUX.LC5.I3 |
TRIM6 | input | TCELL0:IMUX.LC6.I3 |
TRIM7 | input | TCELL0:IMUX.LC7.I3 |
TRIM8 | input | TCELL0:IMUX.LC0.I1 |
TRIM9 | input | TCELL0:IMUX.LC1.I1 |
Bel wires
Wire | Pins |
---|---|
TCELL0:IMUX.LC0.I1 | LED_DRV_CUR.TRIM8 |
TCELL0:IMUX.LC0.I3 | LED_DRV_CUR.TRIM0 |
TCELL0:IMUX.LC1.I1 | LED_DRV_CUR.TRIM9 |
TCELL0:IMUX.LC1.I3 | LED_DRV_CUR.TRIM1 |
TCELL0:IMUX.LC2.I3 | LED_DRV_CUR.TRIM2 |
TCELL0:IMUX.LC3.I3 | LED_DRV_CUR.TRIM3 |
TCELL0:IMUX.LC4.I3 | LED_DRV_CUR.TRIM4 |
TCELL0:IMUX.LC5.I3 | LED_DRV_CUR.TRIM5 |
TCELL0:IMUX.LC6.I3 | LED_DRV_CUR.TRIM6 |
TCELL0:IMUX.LC7.I3 | LED_DRV_CUR.TRIM7 |
TCELL1:IMUX.LC6.I3 | LED_DRV_CUR.EN |
Bitstream
Frame | Bit |
---|
Frame | Bit | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
0 | - | - | - | - | - | - | - | - |
1 | - | - | - | - | - | - | - | - |
2 | - | - | - | - | - | - | - | - |
3 | - | - | - | - | - | - | - | - |
4 | - | - | - | - | - | - | - | LED_DRV_CUR:ENABLE |
LED_DRV_CUR:ENABLE | 1.4.7 |
---|---|
non-inverted | [0] |
Tile LED_DRV_CUR_T05
Cells: 2 IRIs: 0
Bel LED_DRV_CUR
Pin | Direction | Wires |
---|---|---|
EN | input | TCELL1:IMUX.LC6.I3 |
TRIM0 | input | TCELL0:IMUX.LC0.I3 |
TRIM1 | input | TCELL0:IMUX.LC1.I3 |
TRIM2 | input | TCELL0:IMUX.LC2.I3 |
TRIM3 | input | TCELL0:IMUX.LC3.I3 |
TRIM4 | input | TCELL0:IMUX.LC4.I3 |
TRIM5 | input | TCELL0:IMUX.LC5.I3 |
TRIM6 | input | TCELL0:IMUX.LC6.I3 |
TRIM7 | input | TCELL0:IMUX.LC7.I3 |
TRIM8 | input | TCELL0:IMUX.LC0.I1 |
TRIM9 | input | TCELL0:IMUX.LC1.I1 |
Bel wires
Wire | Pins |
---|---|
TCELL0:IMUX.LC0.I1 | LED_DRV_CUR.TRIM8 |
TCELL0:IMUX.LC0.I3 | LED_DRV_CUR.TRIM0 |
TCELL0:IMUX.LC1.I1 | LED_DRV_CUR.TRIM9 |
TCELL0:IMUX.LC1.I3 | LED_DRV_CUR.TRIM1 |
TCELL0:IMUX.LC2.I3 | LED_DRV_CUR.TRIM2 |
TCELL0:IMUX.LC3.I3 | LED_DRV_CUR.TRIM3 |
TCELL0:IMUX.LC4.I3 | LED_DRV_CUR.TRIM4 |
TCELL0:IMUX.LC5.I3 | LED_DRV_CUR.TRIM5 |
TCELL0:IMUX.LC6.I3 | LED_DRV_CUR.TRIM6 |
TCELL0:IMUX.LC7.I3 | LED_DRV_CUR.TRIM7 |
TCELL1:IMUX.LC6.I3 | LED_DRV_CUR.EN |
Tile LED_DRV_CUR_T01
Cells: 1 IRIs: 0
Bel LED_DRV_CUR
Pin | Direction | Wires |
---|---|---|
EN | input | IMUX.LC0.I1 |
TRIM0 | input | IMUX.LC1.I1 |
TRIM1 | input | IMUX.LC2.I1 |
TRIM2 | input | IMUX.LC3.I1 |
TRIM3 | input | IMUX.LC4.I1 |
TRIM4 | input | IMUX.LC5.I1 |
TRIM5 | input | IMUX.LC6.I1 |
TRIM6 | input | IMUX.LC7.I1 |
TRIM7 | input | IMUX.LC0.I0 |
TRIM8 | input | IMUX.LC1.I0 |
TRIM9 | input | IMUX.LC2.I0 |
Bel wires
Wire | Pins |
---|---|
IMUX.LC0.I0 | LED_DRV_CUR.TRIM7 |
IMUX.LC0.I1 | LED_DRV_CUR.EN |
IMUX.LC1.I0 | LED_DRV_CUR.TRIM8 |
IMUX.LC1.I1 | LED_DRV_CUR.TRIM0 |
IMUX.LC2.I0 | LED_DRV_CUR.TRIM9 |
IMUX.LC2.I1 | LED_DRV_CUR.TRIM1 |
IMUX.LC3.I1 | LED_DRV_CUR.TRIM2 |
IMUX.LC4.I1 | LED_DRV_CUR.TRIM3 |
IMUX.LC5.I1 | LED_DRV_CUR.TRIM4 |
IMUX.LC6.I1 | LED_DRV_CUR.TRIM5 |
IMUX.LC7.I1 | LED_DRV_CUR.TRIM6 |
Tile RGB_DRV
Cells: 3 IRIs: 0
Bel RGB_DRV
Pin | Direction | Wires |
---|---|---|
RGB0PWM | input | TCELL2:IMUX.LC2.I1 |
RGB1PWM | input | TCELL2:IMUX.LC3.I1 |
RGB2PWM | input | TCELL2:IMUX.LC4.I1 |
RGBLEDEN | input | TCELL2:IMUX.LC1.I1 |
Bel wires
Wire | Pins |
---|---|
TCELL2:IMUX.LC1.I1 | RGB_DRV.RGBLEDEN |
TCELL2:IMUX.LC2.I1 | RGB_DRV.RGB0PWM |
TCELL2:IMUX.LC3.I1 | RGB_DRV.RGB1PWM |
TCELL2:IMUX.LC4.I1 | RGB_DRV.RGB2PWM |
Bitstream
Frame | Bit | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
0 | - | - | - | - | - | - | - | - |
1 | - | - | - | - | - | - | - | - |
2 | - | - | - | - | - | - | - | - |
3 | - | - | - | - | - | - | - | - |
4 | - | - | - | - | - | - | - | RGB_DRV:ENABLE |
5 | - | - | - | - | - | - | - | - |
6 | - | - | - | - | - | - | - | RGB_DRV:RGB0_CURRENT[1] |
7 | - | - | - | - | - | - | - | RGB_DRV:RGB0_CURRENT[0] |
Frame | Bit | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
0 | - | - | - | - | - | - | - | RGB_DRV:RGB0_CURRENT[3] |
1 | - | - | - | - | - | - | - | RGB_DRV:RGB0_CURRENT[2] |
2 | - | - | - | - | - | - | - | RGB_DRV:RGB0_CURRENT[5] |
3 | - | - | - | - | - | - | - | RGB_DRV:RGB0_CURRENT[4] |
4 | - | - | - | - | - | - | - | RGB_DRV:RGB1_CURRENT[1] |
5 | - | - | - | - | - | - | - | RGB_DRV:RGB1_CURRENT[0] |
6 | - | - | - | - | - | - | - | RGB_DRV:RGB1_CURRENT[3] |
7 | - | - | - | - | - | - | - | RGB_DRV:RGB1_CURRENT[2] |
Frame | Bit | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
0 | - | - | - | - | - | - | - | RGB_DRV:RGB1_CURRENT[5] |
1 | - | - | - | - | - | - | - | RGB_DRV:RGB1_CURRENT[4] |
2 | - | - | - | - | - | - | - | RGB_DRV:RGB2_CURRENT[1] |
3 | - | - | - | - | - | - | - | RGB_DRV:RGB2_CURRENT[0] |
4 | - | - | - | - | - | - | - | RGB_DRV:RGB2_CURRENT[3] |
5 | - | - | - | - | - | - | - | RGB_DRV:RGB2_CURRENT[2] |
6 | - | - | - | - | - | - | - | RGB_DRV:RGB2_CURRENT[5] |
7 | - | - | - | - | - | - | - | RGB_DRV:RGB2_CURRENT[4] |
RGB_DRV:ENABLE | 0.4.7 |
---|---|
non-inverted | [0] |
RGB_DRV:RGB0_CURRENT | 1.2.7 | 1.3.7 | 1.0.7 | 1.1.7 | 0.6.7 | 0.7.7 |
---|---|---|---|---|---|---|
RGB_DRV:RGB1_CURRENT | 2.0.7 | 2.1.7 | 1.6.7 | 1.7.7 | 1.4.7 | 1.5.7 |
RGB_DRV:RGB2_CURRENT | 2.6.7 | 2.7.7 | 2.4.7 | 2.5.7 | 2.2.7 | 2.3.7 |
non-inverted | [5] | [4] | [3] | [2] | [1] | [0] |
Tile LEDD_IP
Cells: 2 IRIs: 0
Bel LEDD_IP
Pin | Direction | Wires |
---|---|---|
LEDDADDR0 | input | TCELL0:IMUX.LC4.I0 |
LEDDADDR1 | input | TCELL0:IMUX.LC5.I0 |
LEDDADDR2 | input | TCELL0:IMUX.LC6.I0 |
LEDDADDR3 | input | TCELL0:IMUX.LC7.I0 |
LEDDCLK | input | TCELL0:IMUX.LC3.I0 |
LEDDCS | input | TCELL0:IMUX.LC2.I0 |
LEDDDAT0 | input | TCELL0:IMUX.LC2.I1 |
LEDDDAT1 | input | TCELL0:IMUX.LC3.I1 |
LEDDDAT2 | input | TCELL0:IMUX.LC4.I1 |
LEDDDAT3 | input | TCELL0:IMUX.LC5.I1 |
LEDDDAT4 | input | TCELL0:IMUX.LC6.I1 |
LEDDDAT5 | input | TCELL0:IMUX.LC7.I1 |
LEDDDAT6 | input | TCELL0:IMUX.LC0.I0 |
LEDDDAT7 | input | TCELL0:IMUX.LC1.I0 |
LEDDDEN | input | TCELL0:IMUX.LC1.I1 |
LEDDEXE | input | TCELL0:IMUX.LC0.I1 |
LEDDON | output | TCELL1:OUT.LC0 |
PWMOUT0 | output | TCELL0:OUT.LC4 |
PWMOUT1 | output | TCELL0:OUT.LC5 |
PWMOUT2 | output | TCELL0:OUT.LC6 |
Bel wires
Wire | Pins |
---|---|
TCELL0:IMUX.LC0.I0 | LEDD_IP.LEDDDAT6 |
TCELL0:IMUX.LC0.I1 | LEDD_IP.LEDDEXE |
TCELL0:IMUX.LC1.I0 | LEDD_IP.LEDDDAT7 |
TCELL0:IMUX.LC1.I1 | LEDD_IP.LEDDDEN |
TCELL0:IMUX.LC2.I0 | LEDD_IP.LEDDCS |
TCELL0:IMUX.LC2.I1 | LEDD_IP.LEDDDAT0 |
TCELL0:IMUX.LC3.I0 | LEDD_IP.LEDDCLK |
TCELL0:IMUX.LC3.I1 | LEDD_IP.LEDDDAT1 |
TCELL0:IMUX.LC4.I0 | LEDD_IP.LEDDADDR0 |
TCELL0:IMUX.LC4.I1 | LEDD_IP.LEDDDAT2 |
TCELL0:IMUX.LC5.I0 | LEDD_IP.LEDDADDR1 |
TCELL0:IMUX.LC5.I1 | LEDD_IP.LEDDDAT3 |
TCELL0:IMUX.LC6.I0 | LEDD_IP.LEDDADDR2 |
TCELL0:IMUX.LC6.I1 | LEDD_IP.LEDDDAT4 |
TCELL0:IMUX.LC7.I0 | LEDD_IP.LEDDADDR3 |
TCELL0:IMUX.LC7.I1 | LEDD_IP.LEDDDAT5 |
TCELL0:OUT.LC4 | LEDD_IP.PWMOUT0 |
TCELL0:OUT.LC5 | LEDD_IP.PWMOUT1 |
TCELL0:OUT.LC6 | LEDD_IP.PWMOUT2 |
TCELL1:OUT.LC0 | LEDD_IP.LEDDON |
Tile IR_DRV
Cells: 3 IRIs: 0
Bel IR_DRV
Pin | Direction | Wires |
---|---|---|
IRLEDEN | input | TCELL0:IMUX.LC7.I0 |
IRPWM | input | TCELL0:IMUX.LC6.I0 |
Bel wires
Wire | Pins |
---|---|
TCELL0:IMUX.LC6.I0 | IR_DRV.IRPWM |
TCELL0:IMUX.LC7.I0 | IR_DRV.IRLEDEN |
Bitstream
Frame | Bit |
---|
Frame | Bit | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
0 | - | - | - | - | - | - | - | - |
1 | - | - | - | - | - | - | - | - |
2 | - | - | - | - | - | - | - | - |
3 | - | - | - | - | - | - | - | - |
4 | - | - | - | - | - | - | - | - |
5 | - | - | - | - | - | - | - | IR_DRV:ENABLE |
6 | - | - | - | - | - | - | - | IR_DRV:IR_CURRENT[1] |
7 | - | - | - | - | - | - | - | IR_DRV:IR_CURRENT[0] |
Frame | Bit | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
0 | - | - | - | - | - | - | - | IR_DRV:IR_CURRENT[3] |
1 | - | - | - | - | - | - | - | IR_DRV:IR_CURRENT[2] |
2 | - | - | - | - | - | - | - | IR_DRV:IR_CURRENT[5] |
3 | - | - | - | - | - | - | - | IR_DRV:IR_CURRENT[4] |
4 | - | - | - | - | - | - | - | IR_DRV:IR_CURRENT[7] |
5 | - | - | - | - | - | - | - | IR_DRV:IR_CURRENT[6] |
6 | - | - | - | - | - | - | - | IR_DRV:IR_CURRENT[9] |
7 | - | - | - | - | - | - | - | IR_DRV:IR_CURRENT[8] |
IR_DRV:ENABLE | 1.5.7 |
---|---|
non-inverted | [0] |
IR_DRV:IR_CURRENT | 2.6.7 | 2.7.7 | 2.4.7 | 2.5.7 | 2.2.7 | 2.3.7 | 2.0.7 | 2.1.7 | 1.6.7 | 1.7.7 |
---|---|---|---|---|---|---|---|---|---|---|
non-inverted | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
Tile RGBA_DRV_T05
Cells: 3 IRIs: 0
Bel RGBA_DRV
Pin | Direction | Wires |
---|---|---|
RGB0PWM | input | TCELL2:IMUX.LC2.I1 |
RGB1PWM | input | TCELL2:IMUX.LC3.I1 |
RGB2PWM | input | TCELL2:IMUX.LC4.I1 |
RGBLEDEN | input | TCELL2:IMUX.LC1.I1 |
Bel wires
Wire | Pins |
---|---|
TCELL2:IMUX.LC1.I1 | RGBA_DRV.RGBLEDEN |
TCELL2:IMUX.LC2.I1 | RGBA_DRV.RGB0PWM |
TCELL2:IMUX.LC3.I1 | RGBA_DRV.RGB1PWM |
TCELL2:IMUX.LC4.I1 | RGBA_DRV.RGB2PWM |
Bitstream
Frame | Bit | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
0 | - | - | - | - | - | - | - | - |
1 | - | - | - | - | - | - | - | - |
2 | - | - | - | - | - | - | - | - |
3 | - | - | - | - | - | - | - | - |
4 | - | - | - | - | - | - | - | RGBA_DRV:ENABLE |
5 | - | - | - | - | - | - | - | RGBA_DRV:CURRENT_MODE |
6 | - | - | - | - | - | - | - | RGBA_DRV:RGB0_CURRENT[1] |
7 | - | - | - | - | - | - | - | RGBA_DRV:RGB0_CURRENT[0] |
Frame | Bit | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
0 | - | - | - | - | - | - | - | RGBA_DRV:RGB0_CURRENT[3] |
1 | - | - | - | - | - | - | - | RGBA_DRV:RGB0_CURRENT[2] |
2 | - | - | - | - | - | - | - | RGBA_DRV:RGB0_CURRENT[5] |
3 | - | - | - | - | - | - | - | RGBA_DRV:RGB0_CURRENT[4] |
4 | - | - | - | - | - | - | - | RGBA_DRV:RGB1_CURRENT[1] |
5 | - | - | - | - | - | - | - | RGBA_DRV:RGB1_CURRENT[0] |
6 | - | - | - | - | - | - | - | RGBA_DRV:RGB1_CURRENT[3] |
7 | - | - | - | - | - | - | - | RGBA_DRV:RGB1_CURRENT[2] |
Frame | Bit | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
0 | - | - | - | - | - | - | - | RGBA_DRV:RGB1_CURRENT[5] |
1 | - | - | - | - | - | - | - | RGBA_DRV:RGB1_CURRENT[4] |
2 | - | - | - | - | - | - | - | RGBA_DRV:RGB2_CURRENT[1] |
3 | - | - | - | - | - | - | - | RGBA_DRV:RGB2_CURRENT[0] |
4 | - | - | - | - | - | - | - | RGBA_DRV:RGB2_CURRENT[3] |
5 | - | - | - | - | - | - | - | RGBA_DRV:RGB2_CURRENT[2] |
6 | - | - | - | - | - | - | - | RGBA_DRV:RGB2_CURRENT[5] |
7 | - | - | - | - | - | - | - | RGBA_DRV:RGB2_CURRENT[4] |
RGBA_DRV:CURRENT_MODE | 0.5.7 |
---|---|
RGBA_DRV:ENABLE | 0.4.7 |
non-inverted | [0] |
RGBA_DRV:RGB0_CURRENT | 1.2.7 | 1.3.7 | 1.0.7 | 1.1.7 | 0.6.7 | 0.7.7 |
---|---|---|---|---|---|---|
RGBA_DRV:RGB1_CURRENT | 2.0.7 | 2.1.7 | 1.6.7 | 1.7.7 | 1.4.7 | 1.5.7 |
RGBA_DRV:RGB2_CURRENT | 2.6.7 | 2.7.7 | 2.4.7 | 2.5.7 | 2.2.7 | 2.3.7 |
non-inverted | [5] | [4] | [3] | [2] | [1] | [0] |
Tile RGBA_DRV_T01
Cells: 4 IRIs: 0
Bel RGBA_DRV
Pin | Direction | Wires |
---|---|---|
RGB0PWM | input | TCELL3:IMUX.LC5.I0 |
RGB1PWM | input | TCELL3:IMUX.LC6.I0 |
RGB2PWM | input | TCELL3:IMUX.LC7.I0 |
RGBLEDEN | input | TCELL1:IMUX.LC1.I1 |
Bel wires
Wire | Pins |
---|---|
TCELL1:IMUX.LC1.I1 | RGBA_DRV.RGBLEDEN |
TCELL3:IMUX.LC5.I0 | RGBA_DRV.RGB0PWM |
TCELL3:IMUX.LC6.I0 | RGBA_DRV.RGB1PWM |
TCELL3:IMUX.LC7.I0 | RGBA_DRV.RGB2PWM |
Bitstream
Frame | Bit | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
0 | - | - | - | - | - | - | - | RGBA_DRV:RGB0_CURRENT[0] |
1 | - | - | - | - | - | - | - | RGBA_DRV:ENABLE |
2 | - | - | - | - | - | - | - | RGBA_DRV:RGB0_CURRENT[2] |
3 | - | - | - | - | - | - | - | RGBA_DRV:RGB0_CURRENT[1] |
4 | - | - | - | - | - | - | - | RGBA_DRV:RGB0_CURRENT[4] |
5 | - | - | - | - | - | - | - | RGBA_DRV:RGB0_CURRENT[3] |
6 | - | - | - | - | - | - | - | RGBA_DRV:RGB1_CURRENT[0] |
7 | - | - | - | - | - | - | - | RGBA_DRV:RGB0_CURRENT[5] |
Frame | Bit | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
0 | - | - | - | - | - | - | - | RGBA_DRV:RGB1_CURRENT[2] |
1 | - | - | - | - | - | - | - | RGBA_DRV:RGB1_CURRENT[1] |
2 | - | - | - | - | - | - | - | RGBA_DRV:RGB1_CURRENT[4] |
3 | - | - | - | - | - | - | - | RGBA_DRV:RGB1_CURRENT[3] |
4 | - | - | - | - | - | - | - | RGBA_DRV:RGB2_CURRENT[0] |
5 | - | - | - | - | - | - | - | RGBA_DRV:RGB1_CURRENT[5] |
6 | - | - | - | - | - | - | - | RGBA_DRV:RGB2_CURRENT[2] |
7 | - | - | - | - | - | - | - | RGBA_DRV:RGB2_CURRENT[1] |
Frame | Bit | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
0 | - | - | - | - | - | - | - | RGBA_DRV:RGB2_CURRENT[4] |
1 | - | - | - | - | - | - | - | RGBA_DRV:RGB2_CURRENT[3] |
2 | - | - | - | - | - | - | - | RGBA_DRV:CURRENT_MODE |
3 | - | - | - | - | - | - | - | RGBA_DRV:RGB2_CURRENT[5] |
RGBA_DRV:CURRENT_MODE | 2.2.7 |
---|---|
RGBA_DRV:ENABLE | 0.1.7 |
non-inverted | [0] |
RGBA_DRV:RGB0_CURRENT | 0.7.7 | 0.4.7 | 0.5.7 | 0.2.7 | 0.3.7 | 0.0.7 |
---|---|---|---|---|---|---|
RGBA_DRV:RGB1_CURRENT | 1.5.7 | 1.2.7 | 1.3.7 | 1.0.7 | 1.1.7 | 0.6.7 |
RGBA_DRV:RGB2_CURRENT | 2.3.7 | 2.0.7 | 2.1.7 | 1.6.7 | 1.7.7 | 1.4.7 |
non-inverted | [5] | [4] | [3] | [2] | [1] | [0] |
Tile LEDDA_IP_T05
Cells: 2 IRIs: 0
Bel LEDDA_IP
Pin | Direction | Wires |
---|---|---|
LEDDADDR0 | input | TCELL0:IMUX.LC4.I0 |
LEDDADDR1 | input | TCELL0:IMUX.LC5.I0 |
LEDDADDR2 | input | TCELL0:IMUX.LC6.I0 |
LEDDADDR3 | input | TCELL0:IMUX.LC7.I0 |
LEDDCLK | input | TCELL1:IMUX.CLK |
LEDDCS | input | TCELL0:IMUX.LC2.I0 |
LEDDDAT0 | input | TCELL0:IMUX.LC2.I1 |
LEDDDAT1 | input | TCELL0:IMUX.LC3.I1 |
LEDDDAT2 | input | TCELL0:IMUX.LC4.I1 |
LEDDDAT3 | input | TCELL0:IMUX.LC5.I1 |
LEDDDAT4 | input | TCELL0:IMUX.LC6.I1 |
LEDDDAT5 | input | TCELL0:IMUX.LC7.I1 |
LEDDDAT6 | input | TCELL0:IMUX.LC0.I0 |
LEDDDAT7 | input | TCELL0:IMUX.LC1.I0 |
LEDDDEN | input | TCELL0:IMUX.LC1.I1 |
LEDDEXE | input | TCELL0:IMUX.LC0.I1 |
LEDDON | output | TCELL1:OUT.LC0 |
PWMOUT0 | output | TCELL0:OUT.LC4 |
PWMOUT1 | output | TCELL0:OUT.LC5 |
PWMOUT2 | output | TCELL0:OUT.LC6 |
Bel wires
Wire | Pins |
---|---|
TCELL0:IMUX.LC0.I0 | LEDDA_IP.LEDDDAT6 |
TCELL0:IMUX.LC0.I1 | LEDDA_IP.LEDDEXE |
TCELL0:IMUX.LC1.I0 | LEDDA_IP.LEDDDAT7 |
TCELL0:IMUX.LC1.I1 | LEDDA_IP.LEDDDEN |
TCELL0:IMUX.LC2.I0 | LEDDA_IP.LEDDCS |
TCELL0:IMUX.LC2.I1 | LEDDA_IP.LEDDDAT0 |
TCELL0:IMUX.LC3.I1 | LEDDA_IP.LEDDDAT1 |
TCELL0:IMUX.LC4.I0 | LEDDA_IP.LEDDADDR0 |
TCELL0:IMUX.LC4.I1 | LEDDA_IP.LEDDDAT2 |
TCELL0:IMUX.LC5.I0 | LEDDA_IP.LEDDADDR1 |
TCELL0:IMUX.LC5.I1 | LEDDA_IP.LEDDDAT3 |
TCELL0:IMUX.LC6.I0 | LEDDA_IP.LEDDADDR2 |
TCELL0:IMUX.LC6.I1 | LEDDA_IP.LEDDDAT4 |
TCELL0:IMUX.LC7.I0 | LEDDA_IP.LEDDADDR3 |
TCELL0:IMUX.LC7.I1 | LEDDA_IP.LEDDDAT5 |
TCELL0:OUT.LC4 | LEDDA_IP.PWMOUT0 |
TCELL0:OUT.LC5 | LEDDA_IP.PWMOUT1 |
TCELL0:OUT.LC6 | LEDDA_IP.PWMOUT2 |
TCELL1:IMUX.CLK | LEDDA_IP.LEDDCLK |
TCELL1:OUT.LC0 | LEDDA_IP.LEDDON |
Tile LEDDA_IP_T01
Cells: 4 IRIs: 0
Bel LEDDA_IP
Pin | Direction | Wires |
---|---|---|
LEDDADDR0 | input | TCELL0:IMUX.LC6.I0 |
LEDDADDR1 | input | TCELL0:IMUX.LC7.I0 |
LEDDADDR2 | input | TCELL1:IMUX.LC0.I3 |
LEDDADDR3 | input | TCELL1:IMUX.LC1.I3 |
LEDDCLK | input | TCELL3:IMUX.CLK |
LEDDCS | input | TCELL0:IMUX.LC4.I0 |
LEDDDAT0 | input | TCELL0:IMUX.LC4.I1 |
LEDDDAT1 | input | TCELL0:IMUX.LC5.I1 |
LEDDDAT2 | input | TCELL0:IMUX.LC6.I1 |
LEDDDAT3 | input | TCELL0:IMUX.LC7.I1 |
LEDDDAT4 | input | TCELL0:IMUX.LC0.I0 |
LEDDDAT5 | input | TCELL0:IMUX.LC1.I0 |
LEDDDAT6 | input | TCELL0:IMUX.LC2.I0 |
LEDDDAT7 | input | TCELL0:IMUX.LC3.I0 |
LEDDDEN | input | TCELL0:IMUX.LC3.I1 |
LEDDEXE | input | TCELL0:IMUX.LC2.I1 |
LEDDON | output | TCELL2:OUT.LC2 |
PWMOUT0 | output | TCELL2:OUT.LC3 |
PWMOUT1 | output | TCELL2:OUT.LC4 |
PWMOUT2 | output | TCELL2:OUT.LC5 |
Bel wires
Wire | Pins |
---|---|
TCELL0:IMUX.LC0.I0 | LEDDA_IP.LEDDDAT4 |
TCELL0:IMUX.LC1.I0 | LEDDA_IP.LEDDDAT5 |
TCELL0:IMUX.LC2.I0 | LEDDA_IP.LEDDDAT6 |
TCELL0:IMUX.LC2.I1 | LEDDA_IP.LEDDEXE |
TCELL0:IMUX.LC3.I0 | LEDDA_IP.LEDDDAT7 |
TCELL0:IMUX.LC3.I1 | LEDDA_IP.LEDDDEN |
TCELL0:IMUX.LC4.I0 | LEDDA_IP.LEDDCS |
TCELL0:IMUX.LC4.I1 | LEDDA_IP.LEDDDAT0 |
TCELL0:IMUX.LC5.I1 | LEDDA_IP.LEDDDAT1 |
TCELL0:IMUX.LC6.I0 | LEDDA_IP.LEDDADDR0 |
TCELL0:IMUX.LC6.I1 | LEDDA_IP.LEDDDAT2 |
TCELL0:IMUX.LC7.I0 | LEDDA_IP.LEDDADDR1 |
TCELL0:IMUX.LC7.I1 | LEDDA_IP.LEDDDAT3 |
TCELL1:IMUX.LC0.I3 | LEDDA_IP.LEDDADDR2 |
TCELL1:IMUX.LC1.I3 | LEDDA_IP.LEDDADDR3 |
TCELL2:OUT.LC2 | LEDDA_IP.LEDDON |
TCELL2:OUT.LC3 | LEDDA_IP.PWMOUT0 |
TCELL2:OUT.LC4 | LEDDA_IP.PWMOUT1 |
TCELL2:OUT.LC5 | LEDDA_IP.PWMOUT2 |
TCELL3:IMUX.CLK | LEDDA_IP.LEDDCLK |
Tile IR500_DRV
Cells: 4 IRIs: 0
Bel IR400_DRV
Pin | Direction | Wires |
---|---|---|
IRLEDEN | input | TCELL1:IMUX.LC4.I0 |
IRPWM | input | TCELL3:IMUX.LC7.I0 |
Bel BARCODE_DRV
Pin | Direction | Wires |
---|---|---|
BARCODEEN | input | TCELL1:IMUX.LC3.I0 |
BARCODEPWM | input | TCELL3:IMUX.LC6.I0 |
Bel wires
Wire | Pins |
---|---|
TCELL1:IMUX.LC3.I0 | BARCODE_DRV.BARCODEEN |
TCELL1:IMUX.LC4.I0 | IR400_DRV.IRLEDEN |
TCELL3:IMUX.LC6.I0 | BARCODE_DRV.BARCODEPWM |
TCELL3:IMUX.LC7.I0 | IR400_DRV.IRPWM |
Bitstream
Frame | Bit | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
0 | - | - | - | - | - | - | - | RGBA_DRV:ENABLE |
1 | - | - | - | - | - | - | - | IR400_DRV:ENABLE |
2 | - | - | - | - | - | - | - | BARCODE_DRV:BARCODE_CURRENT[1] |
3 | - | - | - | - | - | - | - | BARCODE_DRV:BARCODE_CURRENT[0] |
4 | - | - | - | - | - | - | - | BARCODE_DRV:BARCODE_CURRENT[3] |
5 | - | - | - | - | - | - | - | BARCODE_DRV:BARCODE_CURRENT[2] |
6 | - | - | - | - | - | - | - | IR400_DRV:IR400_CURRENT[1] |
7 | - | - | - | - | - | - | - | IR400_DRV:IR400_CURRENT[0] |
Frame | Bit | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
0 | - | - | - | - | - | - | - | IR400_DRV:IR400_CURRENT[3] |
1 | - | - | - | - | - | - | - | IR400_DRV:IR400_CURRENT[2] |
2 | - | - | - | - | - | - | - | IR400_DRV:IR400_CURRENT[5] |
3 | - | - | - | - | - | - | - | IR400_DRV:IR400_CURRENT[4] |
4 | - | - | - | - | - | - | - | IR400_DRV:IR400_CURRENT[7] |
5 | - | - | - | - | - | - | - | IR400_DRV:IR400_CURRENT[6] |
6 | - | - | - | - | - | - | - | BARCODE_DRV:ENABLE |
7 | - | - | - | - | - | - | - | IR500_DRV:CURRENT_MODE |
Frame | Bit | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
0 | - | - | - | - | - | - | - | - |
1 | - | - | - | - | - | - | - | IR500_DRV:ENABLE |
BARCODE_DRV:BARCODE_CURRENT | 0.4.7 | 0.5.7 | 0.2.7 | 0.3.7 |
---|---|---|---|---|
non-inverted | [3] | [2] | [1] | [0] |
BARCODE_DRV:ENABLE | 1.6.7 |
---|---|
IR400_DRV:ENABLE | 0.1.7 |
IR500_DRV:CURRENT_MODE | 1.7.7 |
IR500_DRV:ENABLE | 2.1.7 |
RGBA_DRV:ENABLE | 0.0.7 |
non-inverted | [0] |
IR400_DRV:IR400_CURRENT | 1.4.7 | 1.5.7 | 1.2.7 | 1.3.7 | 1.0.7 | 1.1.7 | 0.6.7 | 0.7.7 |
---|---|---|---|---|---|---|---|---|
non-inverted | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
Tile IR_IP
Cells: 4 IRIs: 0
Bel IR_IP
Pin | Direction | Wires |
---|---|---|
ADRI0 | input | TCELL1:IMUX.LC2.I3 |
ADRI1 | input | TCELL1:IMUX.LC3.I3 |
ADRI2 | input | TCELL1:IMUX.LC4.I3 |
ADRI3 | input | TCELL1:IMUX.LC5.I3 |
BUSY | output | TCELL1:OUT.LC3 |
CLKI | input | TCELL3:IMUX.CLK |
CSI | input | TCELL1:IMUX.LC0.I1 |
DENI | input | TCELL1:IMUX.LC7.I3 |
DRDY | output | TCELL1:OUT.LC4 |
ERR | output | TCELL1:OUT.LC5 |
EXE | input | TCELL1:IMUX.LC2.I1 |
IRIN | input | TCELL0:IMUX.LC0.I0 |
IROUT | output | TCELL2:OUT.LC6 |
LEARN | input | TCELL0:IMUX.LC1.I0 |
RDATA0 | output | TCELL1:OUT.LC6 |
RDATA1 | output | TCELL1:OUT.LC7 |
RDATA2 | output | TCELL2:OUT.LC0 |
RDATA3 | output | TCELL2:OUT.LC1 |
RDATA4 | output | TCELL2:OUT.LC2 |
RDATA5 | output | TCELL2:OUT.LC3 |
RDATA6 | output | TCELL2:OUT.LC4 |
RDATA7 | output | TCELL2:OUT.LC5 |
WDATA0 | input | TCELL0:IMUX.LC2.I0 |
WDATA1 | input | TCELL0:IMUX.LC3.I0 |
WDATA2 | input | TCELL0:IMUX.LC4.I0 |
WDATA3 | input | TCELL0:IMUX.LC5.I0 |
WDATA4 | input | TCELL0:IMUX.LC6.I0 |
WDATA5 | input | TCELL0:IMUX.LC7.I0 |
WDATA6 | input | TCELL1:IMUX.LC0.I3 |
WDATA7 | input | TCELL1:IMUX.LC1.I3 |
WEI | input | TCELL1:IMUX.LC6.I3 |
Bel wires
Wire | Pins |
---|---|
TCELL0:IMUX.LC0.I0 | IR_IP.IRIN |
TCELL0:IMUX.LC1.I0 | IR_IP.LEARN |
TCELL0:IMUX.LC2.I0 | IR_IP.WDATA0 |
TCELL0:IMUX.LC3.I0 | IR_IP.WDATA1 |
TCELL0:IMUX.LC4.I0 | IR_IP.WDATA2 |
TCELL0:IMUX.LC5.I0 | IR_IP.WDATA3 |
TCELL0:IMUX.LC6.I0 | IR_IP.WDATA4 |
TCELL0:IMUX.LC7.I0 | IR_IP.WDATA5 |
TCELL1:IMUX.LC0.I1 | IR_IP.CSI |
TCELL1:IMUX.LC0.I3 | IR_IP.WDATA6 |
TCELL1:IMUX.LC1.I3 | IR_IP.WDATA7 |
TCELL1:IMUX.LC2.I1 | IR_IP.EXE |
TCELL1:IMUX.LC2.I3 | IR_IP.ADRI0 |
TCELL1:IMUX.LC3.I3 | IR_IP.ADRI1 |
TCELL1:IMUX.LC4.I3 | IR_IP.ADRI2 |
TCELL1:IMUX.LC5.I3 | IR_IP.ADRI3 |
TCELL1:IMUX.LC6.I3 | IR_IP.WEI |
TCELL1:IMUX.LC7.I3 | IR_IP.DENI |
TCELL1:OUT.LC3 | IR_IP.BUSY |
TCELL1:OUT.LC4 | IR_IP.DRDY |
TCELL1:OUT.LC5 | IR_IP.ERR |
TCELL1:OUT.LC6 | IR_IP.RDATA0 |
TCELL1:OUT.LC7 | IR_IP.RDATA1 |
TCELL2:OUT.LC0 | IR_IP.RDATA2 |
TCELL2:OUT.LC1 | IR_IP.RDATA3 |
TCELL2:OUT.LC2 | IR_IP.RDATA4 |
TCELL2:OUT.LC3 | IR_IP.RDATA5 |
TCELL2:OUT.LC4 | IR_IP.RDATA6 |
TCELL2:OUT.LC5 | IR_IP.RDATA7 |
TCELL2:OUT.LC6 | IR_IP.IROUT |
TCELL3:IMUX.CLK | IR_IP.CLKI |