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TODO: document

CNR_SE_S3

This tile is used on Spartan 3.

Tile CNR_SE_S3

Cells: 1

Bel DCI[0]

spartan3 CNR_SE_S3 bel DCI[0]
PinDirectionWires
ADDRESS0outputOUT_SEC[0]
ADDRESS1outputOUT_SEC[1]
ADDRESS2outputOUT_SEC[2]
DATAoutputOUT_SEC[3]
DCI_CLKinputIMUX_DATA[23]
DCI_DONEoutputOUT_SEC[4]
DCI_RESETinputIMUX_DATA[22]
HI_LO_NinputIMUX_DATA[21]
HI_LO_PinputIMUX_DATA[20]
IOUPDATEoutputOUT_SEC[8]
N_OR_PoutputOUT_SEC[5]
SCLKoutputOUT_SEC[6]
UPDATEoutputOUT_SEC[7]

Bel DCI[1]

spartan3 CNR_SE_S3 bel DCI[1]
PinDirectionWires
ADDRESS0outputOUT_SEC[0]
ADDRESS1outputOUT_SEC[1]
ADDRESS2outputOUT_SEC[2]
DATAoutputOUT_SEC[3]
DCI_CLKinputIMUX_DATA[15]
DCI_DONEoutputOUT_SEC[4]
DCI_RESETinputIMUX_DATA[14]
HI_LO_NinputIMUX_DATA[13]
HI_LO_PinputIMUX_DATA[12]
IOUPDATEoutputOUT_SEC[8]
N_OR_PoutputOUT_SEC[5]
SCLKoutputOUT_SEC[6]
UPDATEoutputOUT_SEC[7]

Bel DCIRESET[0]

spartan3 CNR_SE_S3 bel DCIRESET[0]
PinDirectionWires
RSTinputIMUX_DATA[19]

Bel DCIRESET[1]

spartan3 CNR_SE_S3 bel DCIRESET[1]
PinDirectionWires
RSTinputIMUX_DATA[11]

Bel STARTUP

spartan3 CNR_SE_S3 bel STARTUP
PinDirectionWires
CLKinputIMUX_CLK[0]
GSRinputIMUX_SR[0]
GTSinputIMUX_SR[3]

Bel CAPTURE

spartan3 CNR_SE_S3 bel CAPTURE
PinDirectionWires
CAPinputIMUX_SR[1]
CLKinputIMUX_CLK[2]

Bel ICAP

spartan3 CNR_SE_S3 bel ICAP
PinDirectionWires
BUSYoutputOUT_SEC[8]
CEinputIMUX_CE[2]
CLKinputIMUX_CLK[1]
I0inputIMUX_DATA[0]
I1inputIMUX_DATA[1]
I2inputIMUX_DATA[2]
I3inputIMUX_DATA[3]
I4inputIMUX_DATA[4]
I5inputIMUX_DATA[5]
I6inputIMUX_DATA[6]
I7inputIMUX_DATA[7]
O0outputOUT_FAN[0]
O1outputOUT_FAN[1]
O2outputOUT_FAN[2]
O3outputOUT_FAN[3]
O4outputOUT_FAN[4]
O5outputOUT_FAN[5]
O6outputOUT_FAN[6]
O7outputOUT_FAN[7]
WRITEinputIMUX_CE[1]

Bel wires

spartan3 CNR_SE_S3 bel wires
WirePins
IMUX_CLK[0]STARTUP.CLK
IMUX_CLK[1]ICAP.CLK
IMUX_CLK[2]CAPTURE.CLK
IMUX_SR[0]STARTUP.GSR
IMUX_SR[1]CAPTURE.CAP
IMUX_SR[3]STARTUP.GTS
IMUX_CE[1]ICAP.WRITE
IMUX_CE[2]ICAP.CE
IMUX_DATA[0]ICAP.I0
IMUX_DATA[1]ICAP.I1
IMUX_DATA[2]ICAP.I2
IMUX_DATA[3]ICAP.I3
IMUX_DATA[4]ICAP.I4
IMUX_DATA[5]ICAP.I5
IMUX_DATA[6]ICAP.I6
IMUX_DATA[7]ICAP.I7
IMUX_DATA[11]DCIRESET[1].RST
IMUX_DATA[12]DCI[1].HI_LO_P
IMUX_DATA[13]DCI[1].HI_LO_N
IMUX_DATA[14]DCI[1].DCI_RESET
IMUX_DATA[15]DCI[1].DCI_CLK
IMUX_DATA[19]DCIRESET[0].RST
IMUX_DATA[20]DCI[0].HI_LO_P
IMUX_DATA[21]DCI[0].HI_LO_N
IMUX_DATA[22]DCI[0].DCI_RESET
IMUX_DATA[23]DCI[0].DCI_CLK
OUT_FAN[0]ICAP.O0
OUT_FAN[1]ICAP.O1
OUT_FAN[2]ICAP.O2
OUT_FAN[3]ICAP.O3
OUT_FAN[4]ICAP.O4
OUT_FAN[5]ICAP.O5
OUT_FAN[6]ICAP.O6
OUT_FAN[7]ICAP.O7
OUT_SEC[0]DCI[0].ADDRESS0, DCI[1].ADDRESS0
OUT_SEC[1]DCI[0].ADDRESS1, DCI[1].ADDRESS1
OUT_SEC[2]DCI[0].ADDRESS2, DCI[1].ADDRESS2
OUT_SEC[3]DCI[0].DATA, DCI[1].DATA
OUT_SEC[4]DCI[0].DCI_DONE, DCI[1].DCI_DONE
OUT_SEC[5]DCI[0].N_OR_P, DCI[1].N_OR_P
OUT_SEC[6]DCI[0].SCLK, DCI[1].SCLK
OUT_SEC[7]DCI[0].UPDATE, DCI[1].UPDATE
OUT_SEC[8]DCI[0].IOUPDATE, DCI[1].IOUPDATE, ICAP.BUSY

Bitstream

spartan3 CNR_SE_S3 rect TERM_H
BitFrame
F0 F1
B63 - -
B62 - -
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 - -
B42 - -
B41 - -
B40 - -
B39 - -
B38 - -
B37 - -
B36 - -
B35 - -
B34 - -
B33 - -
B32 - -
B31 - -
B30 - -
B29 - -
B28 - -
B27 - -
B26 - -
B25 - -
B24 - -
B23 - -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - -
B12 - -
B11 - -
B10 - -
B9 - -
B8 - -
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - -
B0 - -
### Bitstream
spartan3 CNR_SE_S3 rect R0
BitFrame
F0 F1
B63 DCIRESET[0]:ENABLE DCIRESET[1]:ENABLE
B62 DCI[0]:TEST_ENABLE DCI[1]:TEST_ENABLE
B61 DCI[0]:FORCE_DONE_HIGH DCI[1]:FORCE_DONE_HIGH
B60 - -
B59 DCI[0]:PMASK_TERM_SPLIT[3] DCI[1]:PMASK_TERM_SPLIT[3]
B58 DCI[0]:PMASK_TERM_SPLIT[2] DCI[1]:PMASK_TERM_SPLIT[2]
B57 DCI[0]:PMASK_TERM_SPLIT[1] DCI[1]:PMASK_TERM_SPLIT[1]
B56 DCI[0]:PMASK_TERM_SPLIT[0] DCI[1]:PMASK_TERM_SPLIT[0]
B55 - -
B54 DCI[0]:PMASK_TERM_VCC[3] DCI[1]:PMASK_TERM_VCC[3]
B53 DCI[0]:PMASK_TERM_VCC[2] DCI[1]:PMASK_TERM_VCC[2]
B52 DCI[0]:PMASK_TERM_VCC[1] DCI[1]:PMASK_TERM_VCC[1]
B51 DCI[0]:PMASK_TERM_VCC[0] DCI[1]:PMASK_TERM_VCC[0]
B50 MISC:DCI_TEST_MUX[0] -
B49 DCI[0]:NMASK_TERM_SPLIT[3] DCI[1]:NMASK_TERM_SPLIT[3]
B48 DCI[0]:NMASK_TERM_SPLIT[2] DCI[1]:NMASK_TERM_SPLIT[2]
B47 DCI[0]:NMASK_TERM_SPLIT[1] DCI[1]:NMASK_TERM_SPLIT[1]
B46 DCI[0]:NMASK_TERM_SPLIT[0] DCI[1]:NMASK_TERM_SPLIT[0]
B45 DCI[0]:QUIET DCI[1]:QUIET
B44 DCI[0]:ENABLE DCI[1]:ENABLE
B43 - DCI[1]:LVDSBIAS[2]
B42 - DCI[1]:LVDSBIAS[3]
B41 - DCI[1]:LVDSBIAS[4]
B40 - DCI[1]:LVDSBIAS[5]
B39 - DCI[1]:LVDSBIAS[6]
B38 - DCI[1]:LVDSBIAS[7]
B37 - DCI[1]:LVDSBIAS[8]
B36 - DCI[1]:LVDSBIAS[9]
B35 - DCI[1]:LVDSBIAS[10]
B34 - DCI[1]:LVDSBIAS[11]
B33 - DCI[1]:LVDSBIAS[12]
B32 - DCI[0]:LVDSBIAS[2]
B31 - DCI[0]:LVDSBIAS[3]
B30 - DCI[0]:LVDSBIAS[4]
B29 - DCI[0]:LVDSBIAS[5]
B28 - DCI[0]:LVDSBIAS[6]
B27 - DCI[0]:LVDSBIAS[7]
B26 - DCI[0]:LVDSBIAS[8]
B25 - DCI[0]:LVDSBIAS[9]
B24 - DCI[0]:LVDSBIAS[10]
B23 - DCI[0]:LVDSBIAS[11]
B22 - DCI[0]:LVDSBIAS[12]
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - MISC:CCLKPIN[0]
B14 - MISC:DONEPIN[0]
B13 - MISC:DCM_ENABLE
B12 - DCI[1]:LVDSBIAS[0]
B11 - DCI[1]:LVDSBIAS[1]
B10 - DCI[0]:LVDSBIAS[0]
B9 - DCI[0]:LVDSBIAS[1]
B8 - -
B7 - -
B6 - -
B5 - -
B4 - STARTUP:GTS_GSR_ENABLE
B3 - ICAP:ENABLE
B2 - -
B1 - STARTUP:GTS_SYNC
B0 - STARTUP:GSR_SYNC
DCIRESET[0]:ENABLE 0.F0.B63
DCIRESET[1]:ENABLE 0.F1.B63
DCI[0]:ENABLE 0.F0.B44
DCI[0]:FORCE_DONE_HIGH 0.F0.B61
DCI[0]:QUIET 0.F0.B45
DCI[0]:TEST_ENABLE 0.F0.B62
DCI[1]:ENABLE 0.F1.B44
DCI[1]:FORCE_DONE_HIGH 0.F1.B61
DCI[1]:QUIET 0.F1.B45
DCI[1]:TEST_ENABLE 0.F1.B62
ICAP:ENABLE 0.F1.B3
MISC:DCM_ENABLE 0.F1.B13
STARTUP:GSR_SYNC 0.F1.B0
STARTUP:GTS_GSR_ENABLE 0.F1.B4
STARTUP:GTS_SYNC 0.F1.B1
non-inverted [0]
DCI[0]:LVDSBIAS 0.F1.B22 0.F1.B23 0.F1.B24 0.F1.B25 0.F1.B26 0.F1.B27 0.F1.B28 0.F1.B29 0.F1.B30 0.F1.B31 0.F1.B32 0.F1.B9 0.F1.B10
DCI[1]:LVDSBIAS 0.F1.B33 0.F1.B34 0.F1.B35 0.F1.B36 0.F1.B37 0.F1.B38 0.F1.B39 0.F1.B40 0.F1.B41 0.F1.B42 0.F1.B43 0.F1.B11 0.F1.B12
non-inverted [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
DCI[0]:NMASK_TERM_SPLIT 0.F0.B49 0.F0.B48 0.F0.B47 0.F0.B46
DCI[0]:PMASK_TERM_SPLIT 0.F0.B59 0.F0.B58 0.F0.B57 0.F0.B56
DCI[0]:PMASK_TERM_VCC 0.F0.B54 0.F0.B53 0.F0.B52 0.F0.B51
DCI[1]:NMASK_TERM_SPLIT 0.F1.B49 0.F1.B48 0.F1.B47 0.F1.B46
DCI[1]:PMASK_TERM_SPLIT 0.F1.B59 0.F1.B58 0.F1.B57 0.F1.B56
DCI[1]:PMASK_TERM_VCC 0.F1.B54 0.F1.B53 0.F1.B52 0.F1.B51
non-inverted [3] [2] [1] [0]
MISC:CCLKPIN 0.F1.B15
MISC:DONEPIN 0.F1.B14
PULLUP 0
PULLNONE 1
MISC:DCI_TEST_MUX 0.F0.B50
DCI0 0
DCI1 1

CNR_SE_FC

This tile is used on FPGAcore.

Tile CNR_SE_FC

Cells: 1

Bel STARTUP

spartan3 CNR_SE_FC bel STARTUP
PinDirectionWires
CLKinputIMUX_CLK[0]
GSRinputIMUX_SR[0]
GTSinputIMUX_SR[3]

Bel CAPTURE

spartan3 CNR_SE_FC bel CAPTURE
PinDirectionWires
CAPinputIMUX_SR[1]
CLKinputIMUX_CLK[2]

Bel ICAP

spartan3 CNR_SE_FC bel ICAP
PinDirectionWires
BUSYoutputOUT_SEC[8]
CEinputIMUX_CE[2]
CLKinputIMUX_CLK[1]
I0inputIMUX_DATA[0]
I1inputIMUX_DATA[1]
I2inputIMUX_DATA[2]
I3inputIMUX_DATA[3]
I4inputIMUX_DATA[4]
I5inputIMUX_DATA[5]
I6inputIMUX_DATA[6]
I7inputIMUX_DATA[7]
O0outputOUT_FAN[0]
O1outputOUT_FAN[1]
O2outputOUT_FAN[2]
O3outputOUT_FAN[3]
O4outputOUT_FAN[4]
O5outputOUT_FAN[5]
O6outputOUT_FAN[6]
O7outputOUT_FAN[7]
WRITEinputIMUX_CE[1]

Bel MISR

spartan3 CNR_SE_FC bel MISR
PinDirectionWires
CLKinputIMUX_CLK[3]

Bel wires

spartan3 CNR_SE_FC bel wires
WirePins
IMUX_CLK[0]STARTUP.CLK
IMUX_CLK[1]ICAP.CLK
IMUX_CLK[2]CAPTURE.CLK
IMUX_CLK[3]MISR.CLK
IMUX_SR[0]STARTUP.GSR
IMUX_SR[1]CAPTURE.CAP
IMUX_SR[3]STARTUP.GTS
IMUX_CE[1]ICAP.WRITE
IMUX_CE[2]ICAP.CE
IMUX_DATA[0]ICAP.I0
IMUX_DATA[1]ICAP.I1
IMUX_DATA[2]ICAP.I2
IMUX_DATA[3]ICAP.I3
IMUX_DATA[4]ICAP.I4
IMUX_DATA[5]ICAP.I5
IMUX_DATA[6]ICAP.I6
IMUX_DATA[7]ICAP.I7
OUT_FAN[0]ICAP.O0
OUT_FAN[1]ICAP.O1
OUT_FAN[2]ICAP.O2
OUT_FAN[3]ICAP.O3
OUT_FAN[4]ICAP.O4
OUT_FAN[5]ICAP.O5
OUT_FAN[6]ICAP.O6
OUT_FAN[7]ICAP.O7
OUT_SEC[8]ICAP.BUSY

Bitstream

spartan3 CNR_SE_FC rect TERM_H
BitFrame
F0 F1
B63 - -
B62 - -
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 - -
B42 - -
B41 - -
B40 - -
B39 - -
B38 - -
B37 - -
B36 - -
B35 - -
B34 - -
B33 - -
B32 - -
B31 - -
B30 - -
B29 - -
B28 - -
B27 - -
B26 - -
B25 - -
B24 - -
B23 - -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - -
B12 - -
B11 - -
B10 - -
B9 - -
B8 - -
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - -
B0 - -
### Bitstream
spartan3 CNR_SE_FC rect R0
BitFrame
F0 F1
B43 MISC:ABUFF[3] -
B42 MISC:ABUFF[2] -
B41 MISC:ABUFF[1] -
B40 MISC:ABUFF[0] -
B39 - -
B38 - -
B37 - -
B36 - -
B35 - -
B34 - -
B33 - -
B32 - -
B31 - -
B30 - -
B29 - -
B28 - -
B27 - -
B26 - -
B25 - -
B24 - -
B23 - -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - -
B12 - -
B11 - -
B10 - -
B9 - -
B8 - -
B7 - -
B6 - -
B5 - -
B4 - STARTUP:GTS_GSR_ENABLE
B3 - ICAP:ENABLE
B2 - -
B1 MISC:MISR_CLOCK STARTUP:GTS_SYNC
B0 MISC:MISR_RESET STARTUP:GSR_SYNC
ICAP:ENABLE 0.F1.B3
MISC:MISR_CLOCK 0.F0.B1
MISC:MISR_RESET 0.F0.B0
STARTUP:GSR_SYNC 0.F1.B0
STARTUP:GTS_GSR_ENABLE 0.F1.B4
STARTUP:GTS_SYNC 0.F1.B1
non-inverted [0]
MISC:ABUFF 0.F0.B43 0.F0.B42 0.F0.B41 0.F0.B40
non-inverted [3] [2] [1] [0]

CNR_SE_S3E

This tile is used on Spartan 3E.

Tile CNR_SE_S3E

Cells: 1

Bel STARTUP

spartan3 CNR_SE_S3E bel STARTUP
PinDirectionWires
CLKinputIMUX_CLK[0]
GSRinputIMUX_SR[0]
GTSinputIMUX_SR[3]
MBTinputIMUX_CE[0]

Bel CAPTURE

spartan3 CNR_SE_S3E bel CAPTURE
PinDirectionWires
CAPinputIMUX_SR[1]
CLKinputIMUX_CLK[2]

Bel ICAP

spartan3 CNR_SE_S3E bel ICAP
PinDirectionWires
BUSYoutputOUT_SEC[8]
CEinputIMUX_CE[2]
CLKinputIMUX_CLK[1]
I0inputIMUX_DATA[0]
I1inputIMUX_DATA[1]
I2inputIMUX_DATA[2]
I3inputIMUX_DATA[3]
I4inputIMUX_DATA[4]
I5inputIMUX_DATA[5]
I6inputIMUX_DATA[6]
I7inputIMUX_DATA[7]
O0outputOUT_FAN[0]
O1outputOUT_FAN[1]
O2outputOUT_FAN[2]
O3outputOUT_FAN[3]
O4outputOUT_FAN[4]
O5outputOUT_FAN[5]
O6outputOUT_FAN[6]
O7outputOUT_FAN[7]
WRITEinputIMUX_CE[1]

Bel wires

spartan3 CNR_SE_S3E bel wires
WirePins
IMUX_CLK[0]STARTUP.CLK
IMUX_CLK[1]ICAP.CLK
IMUX_CLK[2]CAPTURE.CLK
IMUX_SR[0]STARTUP.GSR
IMUX_SR[1]CAPTURE.CAP
IMUX_SR[3]STARTUP.GTS
IMUX_CE[0]STARTUP.MBT
IMUX_CE[1]ICAP.WRITE
IMUX_CE[2]ICAP.CE
IMUX_DATA[0]ICAP.I0
IMUX_DATA[1]ICAP.I1
IMUX_DATA[2]ICAP.I2
IMUX_DATA[3]ICAP.I3
IMUX_DATA[4]ICAP.I4
IMUX_DATA[5]ICAP.I5
IMUX_DATA[6]ICAP.I6
IMUX_DATA[7]ICAP.I7
OUT_FAN[0]ICAP.O0
OUT_FAN[1]ICAP.O1
OUT_FAN[2]ICAP.O2
OUT_FAN[3]ICAP.O3
OUT_FAN[4]ICAP.O4
OUT_FAN[5]ICAP.O5
OUT_FAN[6]ICAP.O6
OUT_FAN[7]ICAP.O7
OUT_SEC[8]ICAP.BUSY

Bitstream

spartan3 CNR_SE_S3E rect TERM_H
BitFrame
F0 F1
B63 - -
B62 - -
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 - -
B42 - -
B41 - -
B40 - -
B39 - -
B38 - -
B37 - -
B36 - -
B35 - -
B34 - -
B33 - -
B32 - -
B31 - -
B30 - -
B29 - -
B28 - -
B27 - -
B26 - -
B25 - -
B24 - -
B23 - -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - -
B12 - -
B11 - -
B10 - -
B9 - -
B8 - -
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - -
B0 - -
### Bitstream
spartan3 CNR_SE_S3E rect R0
BitFrame
F0 F1
B36 - BANK:LVDSBIAS_0[2]
B35 - BANK:LVDSBIAS_0[3]
B34 - BANK:LVDSBIAS_0[4]
B33 - BANK:LVDSBIAS_1[5]
B32 - BANK:LVDSBIAS_1[6]
B31 - BANK:LVDSBIAS_1[7]
B30 - BANK:LVDSBIAS_1[8]
B29 - BANK:LVDSBIAS_1[9]
B28 - BANK:LVDSBIAS_1[10]
B27 - BANK:LVDSBIAS_0[5]
B26 - BANK:LVDSBIAS_0[6]
B25 - BANK:LVDSBIAS_0[7]
B24 - BANK:LVDSBIAS_0[8]
B23 - BANK:LVDSBIAS_0[9]
B22 - BANK:LVDSBIAS_0[10]
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - MISC:CCLKPIN[0]
B14 - MISC:DONEPIN[0]
B13 - BANK:LVDSBIAS_1[0]
B12 - BANK:LVDSBIAS_0[0]
B11 - BANK:LVDSBIAS_1[1]
B10 - BANK:LVDSBIAS_1[2]
B9 - BANK:LVDSBIAS_1[3]
B8 - BANK:LVDSBIAS_1[4]
B7 - BANK:LVDSBIAS_0[1]
B6 - -
B5 - -
B4 - STARTUP:GTS_GSR_ENABLE
B3 - -
B2 - -
B1 - STARTUP:GTS_SYNC
B0 - STARTUP:GSR_SYNC
BANK:LVDSBIAS_0 0.F1.B22 0.F1.B23 0.F1.B24 0.F1.B25 0.F1.B26 0.F1.B27 0.F1.B34 0.F1.B35 0.F1.B36 0.F1.B7 0.F1.B12
BANK:LVDSBIAS_1 0.F1.B28 0.F1.B29 0.F1.B30 0.F1.B31 0.F1.B32 0.F1.B33 0.F1.B8 0.F1.B9 0.F1.B10 0.F1.B11 0.F1.B13
non-inverted [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
MISC:CCLKPIN 0.F1.B15
MISC:DONEPIN 0.F1.B14
PULLUP 0
PULLNONE 1
STARTUP:GSR_SYNC 0.F1.B0
STARTUP:GTS_GSR_ENABLE 0.F1.B4
STARTUP:GTS_SYNC 0.F1.B1
non-inverted [0]

CNR_SE_S3A

This tile is used on Spartan 3A.

Tile CNR_SE_S3A

Cells: 1

Bel STARTUP

spartan3 CNR_SE_S3A bel STARTUP
PinDirectionWires
CLKinputIMUX_CLK[0]
GSRinputIMUX_SR[0]
GTSinputIMUX_CE[3]

Bel CAPTURE

spartan3 CNR_SE_S3A bel CAPTURE
PinDirectionWires
CAPinputIMUX_SR[1]
CLKinputIMUX_CLK[2]

Bel ICAP

spartan3 CNR_SE_S3A bel ICAP
PinDirectionWires
BUSYoutputOUT_SEC[0]
CEinputIMUX_CE[2]
CLKinputIMUX_CLK[1]
I0inputIMUX_DATA[0]
I1inputIMUX_DATA[1]
I2inputIMUX_DATA[2]
I3inputIMUX_DATA[3]
I4inputIMUX_DATA[4]
I5inputIMUX_DATA[5]
I6inputIMUX_DATA[6]
I7inputIMUX_DATA[7]
O0outputOUT_FAN[0]
O1outputOUT_FAN[1]
O2outputOUT_FAN[2]
O3outputOUT_FAN[3]
O4outputOUT_FAN[4]
O5outputOUT_FAN[5]
O6outputOUT_FAN[6]
O7outputOUT_FAN[7]
WRITEinputIMUX_CE[1]

Bel SPI_ACCESS

spartan3 CNR_SE_S3A bel SPI_ACCESS
PinDirectionWires
CLKinputIMUX_CLK[3]
CSBinputIMUX_CE[0]
MISOoutputOUT_SEC[14]
MOSIinputIMUX_SR[2]

Bel wires

spartan3 CNR_SE_S3A bel wires
WirePins
IMUX_CLK[0]STARTUP.CLK
IMUX_CLK[1]ICAP.CLK
IMUX_CLK[2]CAPTURE.CLK
IMUX_CLK[3]SPI_ACCESS.CLK
IMUX_SR[0]STARTUP.GSR
IMUX_SR[1]CAPTURE.CAP
IMUX_SR[2]SPI_ACCESS.MOSI
IMUX_CE[0]SPI_ACCESS.CSB
IMUX_CE[1]ICAP.WRITE
IMUX_CE[2]ICAP.CE
IMUX_CE[3]STARTUP.GTS
IMUX_DATA[0]ICAP.I0
IMUX_DATA[1]ICAP.I1
IMUX_DATA[2]ICAP.I2
IMUX_DATA[3]ICAP.I3
IMUX_DATA[4]ICAP.I4
IMUX_DATA[5]ICAP.I5
IMUX_DATA[6]ICAP.I6
IMUX_DATA[7]ICAP.I7
OUT_FAN[0]ICAP.O0
OUT_FAN[1]ICAP.O1
OUT_FAN[2]ICAP.O2
OUT_FAN[3]ICAP.O3
OUT_FAN[4]ICAP.O4
OUT_FAN[5]ICAP.O5
OUT_FAN[6]ICAP.O6
OUT_FAN[7]ICAP.O7
OUT_SEC[0]ICAP.BUSY
OUT_SEC[14]SPI_ACCESS.MISO

Bitstream

spartan3 CNR_SE_S3A rect TERM_H
BitFrame
F0 F1
B63 - -
B62 - -
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 - -
B42 - -
B41 - -
B40 - -
B39 - -
B38 - -
B37 - -
B36 - -
B35 - -
B34 - -
B33 - -
B32 - -
B31 - -
B30 - -
B29 - -
B28 - -
B27 - -
B26 - -
B25 - -
B24 - -
B23 - -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - -
B12 - -
B11 - -
B10 - -
B9 - -
B8 - -
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - -
B0 - -
### Bitstream
spartan3 CNR_SE_S3A rect R0
BitFrame
F0 F1
B6 - MISC:DONEPIN[0]
B5 - -
B4 - STARTUP:GTS_GSR_ENABLE
B3 - SPI_ACCESS:ENABLE
B2 - -
B1 - STARTUP:GTS_SYNC
B0 - STARTUP:GSR_SYNC
MISC:DONEPIN 0.F1.B6
PULLUP 0
PULLNONE 1
SPI_ACCESS:ENABLE 0.F1.B3
STARTUP:GSR_SYNC 0.F1.B0
STARTUP:GTS_GSR_ENABLE 0.F1.B4
STARTUP:GTS_SYNC 0.F1.B1
non-inverted [0]