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South-east

TODO: document

CNR_SE_S3

This tile is used on Spartan 3.

Tile CNR_SE_S3

Cells: 1

Bels DCI

spartan3 CNR_SE_S3 bel DCI pins
PinDirectionDCI[0]DCI[1]
DCI_CLKinIMUX_DATA[23]IMUX_DATA[15]
DCI_RESETinIMUX_DATA[22]IMUX_DATA[14]
HI_LO_PinIMUX_DATA[20]IMUX_DATA[12]
HI_LO_NinIMUX_DATA[21]IMUX_DATA[13]
SCLKoutOUT_SEC[6]OUT_SEC[6]
ADDRESS[0]outOUT_SEC[0]OUT_SEC[0]
ADDRESS[1]outOUT_SEC[1]OUT_SEC[1]
ADDRESS[2]outOUT_SEC[2]OUT_SEC[2]
DATAoutOUT_SEC[3]OUT_SEC[3]
N_OR_PoutOUT_SEC[5]OUT_SEC[5]
UPDATEoutOUT_SEC[7]OUT_SEC[7]
IOUPDATEoutOUT_SEC[8]OUT_SEC[8]
DCI_DONEoutOUT_SEC[4]OUT_SEC[4]
spartan3 CNR_SE_S3 bel DCI attribute bits
AttributeDCI[0]DCI[1]
ENABLETERM_H[0][44]TERM_H[1][44]
TEST_ENABLETERM_H[0][62]TERM_H[1][62]
FORCE_DONE_HIGHTERM_H[0][61]TERM_H[1][61]
S3_PMASK_TERM_SPLIT bit 0TERM_H[0][56]TERM_H[1][56]
S3_PMASK_TERM_SPLIT bit 1TERM_H[0][57]TERM_H[1][57]
S3_PMASK_TERM_SPLIT bit 2TERM_H[0][58]TERM_H[1][58]
S3_PMASK_TERM_SPLIT bit 3TERM_H[0][59]TERM_H[1][59]
S3_NMASK_TERM_SPLIT bit 0TERM_H[0][46]TERM_H[1][46]
S3_NMASK_TERM_SPLIT bit 1TERM_H[0][47]TERM_H[1][47]
S3_NMASK_TERM_SPLIT bit 2TERM_H[0][48]TERM_H[1][48]
S3_NMASK_TERM_SPLIT bit 3TERM_H[0][49]TERM_H[1][49]
S3_PMASK_TERM_VCC bit 0TERM_H[0][51]TERM_H[1][51]
S3_PMASK_TERM_VCC bit 1TERM_H[0][52]TERM_H[1][52]
S3_PMASK_TERM_VCC bit 2TERM_H[0][53]TERM_H[1][53]
S3_PMASK_TERM_VCC bit 3TERM_H[0][54]TERM_H[1][54]
S3_LVDSBIAS bit 0TERM_H[1][22]TERM_H[1][33]
S3_LVDSBIAS bit 1TERM_H[1][23]TERM_H[1][34]
S3_LVDSBIAS bit 2TERM_H[1][24]TERM_H[1][35]
S3_LVDSBIAS bit 3TERM_H[1][25]TERM_H[1][36]
S3_LVDSBIAS bit 4TERM_H[1][26]TERM_H[1][37]
S3_LVDSBIAS bit 5TERM_H[1][27]TERM_H[1][38]
S3_LVDSBIAS bit 6TERM_H[1][28]TERM_H[1][39]
S3_LVDSBIAS bit 7TERM_H[1][29]TERM_H[1][40]
S3_LVDSBIAS bit 8TERM_H[1][30]TERM_H[1][41]
S3_LVDSBIAS bit 9TERM_H[1][31]TERM_H[1][42]
S3_LVDSBIAS bit 10TERM_H[1][32]TERM_H[1][43]
S3_LVDSBIAS bit 11TERM_H[1][9]TERM_H[1][11]
S3_LVDSBIAS bit 12TERM_H[1][10]TERM_H[1][12]
QUIETTERM_H[0][45]TERM_H[1][45]

Bels DCIRESET

spartan3 CNR_SE_S3 bel DCIRESET pins
PinDirectionDCIRESET[0]DCIRESET[1]
RSTinIMUX_DATA[19]IMUX_DATA[11]
spartan3 CNR_SE_S3 bel DCIRESET attribute bits
AttributeDCIRESET[0]DCIRESET[1]
ENABLETERM_H[0][63]TERM_H[1][63]

Bels STARTUP

spartan3 CNR_SE_S3 bel STARTUP pins
PinDirectionSTARTUP
CLKinIMUX_CLK_OPTINV[0]
GSRinIMUX_SR_OPTINV[0]
GTSinIMUX_SR_OPTINV[3]
spartan3 CNR_SE_S3 bel STARTUP attribute bits
AttributeSTARTUP
USER_GTS_GSR_ENABLETERM_H[1][4]
GTS_SYNCTERM_H[1][1]
GSR_SYNCTERM_H[1][0]

Bels CAPTURE

spartan3 CNR_SE_S3 bel CAPTURE pins
PinDirectionCAPTURE
CLKinIMUX_CLK_OPTINV[2]
CAPinIMUX_SR_OPTINV[1]

Bels ICAP

spartan3 CNR_SE_S3 bel ICAP pins
PinDirectionICAP
CLKinIMUX_CLK_OPTINV[1]
CEin~IMUX_CE_OPTINV[2]
WRITEin~IMUX_CE_OPTINV[1]
I[0]inIMUX_DATA[0]
I[1]inIMUX_DATA[1]
I[2]inIMUX_DATA[2]
I[3]inIMUX_DATA[3]
I[4]inIMUX_DATA[4]
I[5]inIMUX_DATA[5]
I[6]inIMUX_DATA[6]
I[7]inIMUX_DATA[7]
BUSYoutOUT_SEC[8]
O[0]outOUT_FAN[0]
O[1]outOUT_FAN[1]
O[2]outOUT_FAN[2]
O[3]outOUT_FAN[3]
O[4]outOUT_FAN[4]
O[5]outOUT_FAN[5]
O[6]outOUT_FAN[6]
O[7]outOUT_FAN[7]
spartan3 CNR_SE_S3 bel ICAP attribute bits
AttributeICAP
ENABLETERM_H[1][3]

Bels MISC_CNR_S3

spartan3 CNR_SE_S3 bel MISC_CNR_S3 pins
PinDirectionMISC_CNR_S3
spartan3 CNR_SE_S3 bel MISC_CNR_S3 attribute bits
AttributeMISC_CNR_S3
MUX_DCI_TEST bit 0TERM_H[0][50]
DCM_ENABLETERM_H[1][13]

Bels MISC_SE

spartan3 CNR_SE_S3 bel MISC_SE pins
PinDirectionMISC_SE
spartan3 CNR_SE_S3 bel MISC_SE attribute bits
AttributeMISC_SE
CCLK_PULL[enum: IOB_PULL]
DONE_PULL[enum: IOB_PULL]
spartan3 CNR_SE_S3 enum IOB_PULL
MISC_SE.CCLK_PULLTERM_H[1][15]
MISC_SE.DONE_PULLTERM_H[1][14]
NONE1
PULLUP0

Bel wires

spartan3 CNR_SE_S3 bel wires
WirePins
IMUX_CLK_OPTINV[0]STARTUP.CLK
IMUX_CLK_OPTINV[1]ICAP.CLK
IMUX_CLK_OPTINV[2]CAPTURE.CLK
IMUX_SR_OPTINV[0]STARTUP.GSR
IMUX_SR_OPTINV[1]CAPTURE.CAP
IMUX_SR_OPTINV[3]STARTUP.GTS
IMUX_CE_OPTINV[1]ICAP.WRITE
IMUX_CE_OPTINV[2]ICAP.CE
IMUX_DATA[0]ICAP.I[0]
IMUX_DATA[1]ICAP.I[1]
IMUX_DATA[2]ICAP.I[2]
IMUX_DATA[3]ICAP.I[3]
IMUX_DATA[4]ICAP.I[4]
IMUX_DATA[5]ICAP.I[5]
IMUX_DATA[6]ICAP.I[6]
IMUX_DATA[7]ICAP.I[7]
IMUX_DATA[11]DCIRESET[1].RST
IMUX_DATA[12]DCI[1].HI_LO_P
IMUX_DATA[13]DCI[1].HI_LO_N
IMUX_DATA[14]DCI[1].DCI_RESET
IMUX_DATA[15]DCI[1].DCI_CLK
IMUX_DATA[19]DCIRESET[0].RST
IMUX_DATA[20]DCI[0].HI_LO_P
IMUX_DATA[21]DCI[0].HI_LO_N
IMUX_DATA[22]DCI[0].DCI_RESET
IMUX_DATA[23]DCI[0].DCI_CLK
OUT_FAN[0]ICAP.O[0]
OUT_FAN[1]ICAP.O[1]
OUT_FAN[2]ICAP.O[2]
OUT_FAN[3]ICAP.O[3]
OUT_FAN[4]ICAP.O[4]
OUT_FAN[5]ICAP.O[5]
OUT_FAN[6]ICAP.O[6]
OUT_FAN[7]ICAP.O[7]
OUT_SEC[0]DCI[0].ADDRESS[0], DCI[1].ADDRESS[0]
OUT_SEC[1]DCI[0].ADDRESS[1], DCI[1].ADDRESS[1]
OUT_SEC[2]DCI[0].ADDRESS[2], DCI[1].ADDRESS[2]
OUT_SEC[3]DCI[0].DATA, DCI[1].DATA
OUT_SEC[4]DCI[0].DCI_DONE, DCI[1].DCI_DONE
OUT_SEC[5]DCI[0].N_OR_P, DCI[1].N_OR_P
OUT_SEC[6]DCI[0].SCLK, DCI[1].SCLK
OUT_SEC[7]DCI[0].UPDATE, DCI[1].UPDATE
OUT_SEC[8]DCI[0].IOUPDATE, DCI[1].IOUPDATE, ICAP.BUSY

Bitstream

spartan3 CNR_SE_S3 rect TERM_H
BitFrame
F1 F0
B63 DCIRESET[1]: ENABLE DCIRESET[0]: ENABLE
B62 DCI[1]: TEST_ENABLE DCI[0]: TEST_ENABLE
B61 DCI[1]: FORCE_DONE_HIGH DCI[0]: FORCE_DONE_HIGH
B60 - -
B59 DCI[1]: S3_PMASK_TERM_SPLIT bit 3 DCI[0]: S3_PMASK_TERM_SPLIT bit 3
B58 DCI[1]: S3_PMASK_TERM_SPLIT bit 2 DCI[0]: S3_PMASK_TERM_SPLIT bit 2
B57 DCI[1]: S3_PMASK_TERM_SPLIT bit 1 DCI[0]: S3_PMASK_TERM_SPLIT bit 1
B56 DCI[1]: S3_PMASK_TERM_SPLIT bit 0 DCI[0]: S3_PMASK_TERM_SPLIT bit 0
B55 - -
B54 DCI[1]: S3_PMASK_TERM_VCC bit 3 DCI[0]: S3_PMASK_TERM_VCC bit 3
B53 DCI[1]: S3_PMASK_TERM_VCC bit 2 DCI[0]: S3_PMASK_TERM_VCC bit 2
B52 DCI[1]: S3_PMASK_TERM_VCC bit 1 DCI[0]: S3_PMASK_TERM_VCC bit 1
B51 DCI[1]: S3_PMASK_TERM_VCC bit 0 DCI[0]: S3_PMASK_TERM_VCC bit 0
B50 - MISC_CNR_S3: MUX_DCI_TEST bit 0
B49 DCI[1]: S3_NMASK_TERM_SPLIT bit 3 DCI[0]: S3_NMASK_TERM_SPLIT bit 3
B48 DCI[1]: S3_NMASK_TERM_SPLIT bit 2 DCI[0]: S3_NMASK_TERM_SPLIT bit 2
B47 DCI[1]: S3_NMASK_TERM_SPLIT bit 1 DCI[0]: S3_NMASK_TERM_SPLIT bit 1
B46 DCI[1]: S3_NMASK_TERM_SPLIT bit 0 DCI[0]: S3_NMASK_TERM_SPLIT bit 0
B45 DCI[1]: QUIET DCI[0]: QUIET
B44 DCI[1]: ENABLE DCI[0]: ENABLE
B43 DCI[1]: S3_LVDSBIAS bit 10 -
B42 DCI[1]: S3_LVDSBIAS bit 9 -
B41 DCI[1]: S3_LVDSBIAS bit 8 -
B40 DCI[1]: S3_LVDSBIAS bit 7 -
B39 DCI[1]: S3_LVDSBIAS bit 6 -
B38 DCI[1]: S3_LVDSBIAS bit 5 -
B37 DCI[1]: S3_LVDSBIAS bit 4 -
B36 DCI[1]: S3_LVDSBIAS bit 3 -
B35 DCI[1]: S3_LVDSBIAS bit 2 -
B34 DCI[1]: S3_LVDSBIAS bit 1 -
B33 DCI[1]: S3_LVDSBIAS bit 0 -
B32 DCI[0]: S3_LVDSBIAS bit 10 -
B31 DCI[0]: S3_LVDSBIAS bit 9 -
B30 DCI[0]: S3_LVDSBIAS bit 8 -
B29 DCI[0]: S3_LVDSBIAS bit 7 -
B28 DCI[0]: S3_LVDSBIAS bit 6 -
B27 DCI[0]: S3_LVDSBIAS bit 5 -
B26 DCI[0]: S3_LVDSBIAS bit 4 -
B25 DCI[0]: S3_LVDSBIAS bit 3 -
B24 DCI[0]: S3_LVDSBIAS bit 2 -
B23 DCI[0]: S3_LVDSBIAS bit 1 -
B22 DCI[0]: S3_LVDSBIAS bit 0 -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 MISC_SE: CCLK_PULL bit 0 -
B14 MISC_SE: DONE_PULL bit 0 -
B13 MISC_CNR_S3: DCM_ENABLE -
B12 DCI[1]: S3_LVDSBIAS bit 12 -
B11 DCI[1]: S3_LVDSBIAS bit 11 -
B10 DCI[0]: S3_LVDSBIAS bit 12 -
B9 DCI[0]: S3_LVDSBIAS bit 11 -
B8 - -
B7 - -
B6 - -
B5 - -
B4 STARTUP: USER_GTS_GSR_ENABLE -
B3 ICAP: ENABLE -
B2 - -
B1 STARTUP: GTS_SYNC -
B0 STARTUP: GSR_SYNC -

CNR_SE_FC

This tile is used on FPGAcore.

Tile CNR_SE_FC

Cells: 1

Bels STARTUP

spartan3 CNR_SE_FC bel STARTUP pins
PinDirectionSTARTUP
CLKinIMUX_CLK_OPTINV[0]
GSRinIMUX_SR_OPTINV[0]
GTSinIMUX_SR_OPTINV[3]
spartan3 CNR_SE_FC bel STARTUP attribute bits
AttributeSTARTUP
USER_GTS_GSR_ENABLETERM_H[1][4]
GTS_SYNCTERM_H[1][1]
GSR_SYNCTERM_H[1][0]

Bels CAPTURE

spartan3 CNR_SE_FC bel CAPTURE pins
PinDirectionCAPTURE
CLKinIMUX_CLK_OPTINV[2]
CAPinIMUX_SR_OPTINV[1]

Bels ICAP

spartan3 CNR_SE_FC bel ICAP pins
PinDirectionICAP
CLKinIMUX_CLK_OPTINV[1]
CEin~IMUX_CE_OPTINV[2]
WRITEin~IMUX_CE_OPTINV[1]
I[0]inIMUX_DATA[0]
I[1]inIMUX_DATA[1]
I[2]inIMUX_DATA[2]
I[3]inIMUX_DATA[3]
I[4]inIMUX_DATA[4]
I[5]inIMUX_DATA[5]
I[6]inIMUX_DATA[6]
I[7]inIMUX_DATA[7]
BUSYoutOUT_SEC[8]
O[0]outOUT_FAN[0]
O[1]outOUT_FAN[1]
O[2]outOUT_FAN[2]
O[3]outOUT_FAN[3]
O[4]outOUT_FAN[4]
O[5]outOUT_FAN[5]
O[6]outOUT_FAN[6]
O[7]outOUT_FAN[7]
spartan3 CNR_SE_FC bel ICAP attribute bits
AttributeICAP
ENABLETERM_H[1][3]

Bels MISR_FC

spartan3 CNR_SE_FC bel MISR_FC pins
PinDirectionMISR_FC
CLKinIMUX_CLK_OPTINV[3]
spartan3 CNR_SE_FC bel MISR_FC attribute bits
AttributeMISR_FC
MISR_CLOCKTERM_H[0][1]
MISR_RESETTERM_H[0][0]

Bels MISC_SE

spartan3 CNR_SE_FC bel MISC_SE pins
PinDirectionMISC_SE
spartan3 CNR_SE_FC bel MISC_SE attribute bits
AttributeMISC_SE
ABUFF bit 0TERM_H[0][40]
ABUFF bit 1TERM_H[0][41]
ABUFF bit 2TERM_H[0][42]
ABUFF bit 3TERM_H[0][43]

Bel wires

spartan3 CNR_SE_FC bel wires
WirePins
IMUX_CLK_OPTINV[0]STARTUP.CLK
IMUX_CLK_OPTINV[1]ICAP.CLK
IMUX_CLK_OPTINV[2]CAPTURE.CLK
IMUX_CLK_OPTINV[3]MISR_FC.CLK
IMUX_SR_OPTINV[0]STARTUP.GSR
IMUX_SR_OPTINV[1]CAPTURE.CAP
IMUX_SR_OPTINV[3]STARTUP.GTS
IMUX_CE_OPTINV[1]ICAP.WRITE
IMUX_CE_OPTINV[2]ICAP.CE
IMUX_DATA[0]ICAP.I[0]
IMUX_DATA[1]ICAP.I[1]
IMUX_DATA[2]ICAP.I[2]
IMUX_DATA[3]ICAP.I[3]
IMUX_DATA[4]ICAP.I[4]
IMUX_DATA[5]ICAP.I[5]
IMUX_DATA[6]ICAP.I[6]
IMUX_DATA[7]ICAP.I[7]
OUT_FAN[0]ICAP.O[0]
OUT_FAN[1]ICAP.O[1]
OUT_FAN[2]ICAP.O[2]
OUT_FAN[3]ICAP.O[3]
OUT_FAN[4]ICAP.O[4]
OUT_FAN[5]ICAP.O[5]
OUT_FAN[6]ICAP.O[6]
OUT_FAN[7]ICAP.O[7]
OUT_SEC[8]ICAP.BUSY

Bitstream

spartan3 CNR_SE_FC rect TERM_H
BitFrame
F1 F0
B63 - -
B62 - -
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 - MISC_SE: ABUFF bit 3
B42 - MISC_SE: ABUFF bit 2
B41 - MISC_SE: ABUFF bit 1
B40 - MISC_SE: ABUFF bit 0
B39 - -
B38 - -
B37 - -
B36 - -
B35 - -
B34 - -
B33 - -
B32 - -
B31 - -
B30 - -
B29 - -
B28 - -
B27 - -
B26 - -
B25 - -
B24 - -
B23 - -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - -
B12 - -
B11 - -
B10 - -
B9 - -
B8 - -
B7 - -
B6 - -
B5 - -
B4 STARTUP: USER_GTS_GSR_ENABLE -
B3 ICAP: ENABLE -
B2 - -
B1 STARTUP: GTS_SYNC MISR_FC: MISR_CLOCK
B0 STARTUP: GSR_SYNC MISR_FC: MISR_RESET

CNR_SE_S3E

This tile is used on Spartan 3E.

Tile CNR_SE_S3E

Cells: 1

Bels STARTUP

spartan3 CNR_SE_S3E bel STARTUP pins
PinDirectionSTARTUP
CLKinIMUX_CLK_OPTINV[0]
GSRinIMUX_SR_OPTINV[0]
GTSinIMUX_SR_OPTINV[3]
MBTinIMUX_CE_OPTINV[0]
spartan3 CNR_SE_S3E bel STARTUP attribute bits
AttributeSTARTUP
USER_GTS_GSR_ENABLETERM_H[1][4]
GTS_SYNCTERM_H[1][1]
GSR_SYNCTERM_H[1][0]

Bels CAPTURE

spartan3 CNR_SE_S3E bel CAPTURE pins
PinDirectionCAPTURE
CLKinIMUX_CLK_OPTINV[2]
CAPinIMUX_SR_OPTINV[1]

Bels ICAP

spartan3 CNR_SE_S3E bel ICAP pins
PinDirectionICAP
CLKinIMUX_CLK_OPTINV[1]
CEin~IMUX_CE_OPTINV[2]
WRITEin~IMUX_CE_OPTINV[1]
I[0]inIMUX_DATA[0]
I[1]inIMUX_DATA[1]
I[2]inIMUX_DATA[2]
I[3]inIMUX_DATA[3]
I[4]inIMUX_DATA[4]
I[5]inIMUX_DATA[5]
I[6]inIMUX_DATA[6]
I[7]inIMUX_DATA[7]
BUSYoutOUT_SEC[8]
O[0]outOUT_FAN[0]
O[1]outOUT_FAN[1]
O[2]outOUT_FAN[2]
O[3]outOUT_FAN[3]
O[4]outOUT_FAN[4]
O[5]outOUT_FAN[5]
O[6]outOUT_FAN[6]
O[7]outOUT_FAN[7]
spartan3 CNR_SE_S3E bel ICAP attribute bits
AttributeICAP

Bels MISC_SE

spartan3 CNR_SE_S3E bel MISC_SE pins
PinDirectionMISC_SE
spartan3 CNR_SE_S3E bel MISC_SE attribute bits
AttributeMISC_SE
CCLK_PULL[enum: IOB_PULL]
DONE_PULL[enum: IOB_PULL]
spartan3 CNR_SE_S3E enum IOB_PULL
MISC_SE.CCLK_PULLTERM_H[1][15]
MISC_SE.DONE_PULLTERM_H[1][14]
NONE1
PULLUP0

Bels BANK

spartan3 CNR_SE_S3E bel BANK pins
PinDirectionBANK
spartan3 CNR_SE_S3E bel BANK attribute bits
AttributeBANK
S3E_LVDSBIAS[0] bit 0TERM_H[1][12]
S3E_LVDSBIAS[0] bit 1TERM_H[1][7]
S3E_LVDSBIAS[0] bit 2TERM_H[1][36]
S3E_LVDSBIAS[0] bit 3TERM_H[1][35]
S3E_LVDSBIAS[0] bit 4TERM_H[1][34]
S3E_LVDSBIAS[0] bit 5TERM_H[1][27]
S3E_LVDSBIAS[0] bit 6TERM_H[1][26]
S3E_LVDSBIAS[0] bit 7TERM_H[1][25]
S3E_LVDSBIAS[0] bit 8TERM_H[1][24]
S3E_LVDSBIAS[0] bit 9TERM_H[1][23]
S3E_LVDSBIAS[0] bit 10TERM_H[1][22]
S3E_LVDSBIAS[1] bit 0TERM_H[1][13]
S3E_LVDSBIAS[1] bit 1TERM_H[1][11]
S3E_LVDSBIAS[1] bit 2TERM_H[1][10]
S3E_LVDSBIAS[1] bit 3TERM_H[1][9]
S3E_LVDSBIAS[1] bit 4TERM_H[1][8]
S3E_LVDSBIAS[1] bit 5TERM_H[1][33]
S3E_LVDSBIAS[1] bit 6TERM_H[1][32]
S3E_LVDSBIAS[1] bit 7TERM_H[1][31]
S3E_LVDSBIAS[1] bit 8TERM_H[1][30]
S3E_LVDSBIAS[1] bit 9TERM_H[1][29]
S3E_LVDSBIAS[1] bit 10TERM_H[1][28]

Bel wires

spartan3 CNR_SE_S3E bel wires
WirePins
IMUX_CLK_OPTINV[0]STARTUP.CLK
IMUX_CLK_OPTINV[1]ICAP.CLK
IMUX_CLK_OPTINV[2]CAPTURE.CLK
IMUX_SR_OPTINV[0]STARTUP.GSR
IMUX_SR_OPTINV[1]CAPTURE.CAP
IMUX_SR_OPTINV[3]STARTUP.GTS
IMUX_CE_OPTINV[0]STARTUP.MBT
IMUX_CE_OPTINV[1]ICAP.WRITE
IMUX_CE_OPTINV[2]ICAP.CE
IMUX_DATA[0]ICAP.I[0]
IMUX_DATA[1]ICAP.I[1]
IMUX_DATA[2]ICAP.I[2]
IMUX_DATA[3]ICAP.I[3]
IMUX_DATA[4]ICAP.I[4]
IMUX_DATA[5]ICAP.I[5]
IMUX_DATA[6]ICAP.I[6]
IMUX_DATA[7]ICAP.I[7]
OUT_FAN[0]ICAP.O[0]
OUT_FAN[1]ICAP.O[1]
OUT_FAN[2]ICAP.O[2]
OUT_FAN[3]ICAP.O[3]
OUT_FAN[4]ICAP.O[4]
OUT_FAN[5]ICAP.O[5]
OUT_FAN[6]ICAP.O[6]
OUT_FAN[7]ICAP.O[7]
OUT_SEC[8]ICAP.BUSY

Bitstream

spartan3 CNR_SE_S3E rect TERM_H
BitFrame
F1 F0
B63 - -
B62 - -
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 - -
B42 - -
B41 - -
B40 - -
B39 - -
B38 - -
B37 - -
B36 BANK: S3E_LVDSBIAS[0] bit 2 -
B35 BANK: S3E_LVDSBIAS[0] bit 3 -
B34 BANK: S3E_LVDSBIAS[0] bit 4 -
B33 BANK: S3E_LVDSBIAS[1] bit 5 -
B32 BANK: S3E_LVDSBIAS[1] bit 6 -
B31 BANK: S3E_LVDSBIAS[1] bit 7 -
B30 BANK: S3E_LVDSBIAS[1] bit 8 -
B29 BANK: S3E_LVDSBIAS[1] bit 9 -
B28 BANK: S3E_LVDSBIAS[1] bit 10 -
B27 BANK: S3E_LVDSBIAS[0] bit 5 -
B26 BANK: S3E_LVDSBIAS[0] bit 6 -
B25 BANK: S3E_LVDSBIAS[0] bit 7 -
B24 BANK: S3E_LVDSBIAS[0] bit 8 -
B23 BANK: S3E_LVDSBIAS[0] bit 9 -
B22 BANK: S3E_LVDSBIAS[0] bit 10 -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 MISC_SE: CCLK_PULL bit 0 -
B14 MISC_SE: DONE_PULL bit 0 -
B13 BANK: S3E_LVDSBIAS[1] bit 0 -
B12 BANK: S3E_LVDSBIAS[0] bit 0 -
B11 BANK: S3E_LVDSBIAS[1] bit 1 -
B10 BANK: S3E_LVDSBIAS[1] bit 2 -
B9 BANK: S3E_LVDSBIAS[1] bit 3 -
B8 BANK: S3E_LVDSBIAS[1] bit 4 -
B7 BANK: S3E_LVDSBIAS[0] bit 1 -
B6 - -
B5 - -
B4 STARTUP: USER_GTS_GSR_ENABLE -
B3 - -
B2 - -
B1 STARTUP: GTS_SYNC -
B0 STARTUP: GSR_SYNC -

CNR_SE_S3A

This tile is used on Spartan 3A.

Tile CNR_SE_S3A

Cells: 1

Bels STARTUP

spartan3 CNR_SE_S3A bel STARTUP pins
PinDirectionSTARTUP
CLKinIMUX_CLK_OPTINV[0]
GSRinIMUX_SR_OPTINV[0]
GTSinIMUX_CE_OPTINV[3]
spartan3 CNR_SE_S3A bel STARTUP attribute bits
AttributeSTARTUP
USER_GTS_GSR_ENABLETERM_H[1][4]
GTS_SYNCTERM_H[1][1]
GSR_SYNCTERM_H[1][0]

Bels CAPTURE

spartan3 CNR_SE_S3A bel CAPTURE pins
PinDirectionCAPTURE
CLKinIMUX_CLK_OPTINV[2]
CAPinIMUX_SR_OPTINV[1]

Bels ICAP

spartan3 CNR_SE_S3A bel ICAP pins
PinDirectionICAP
CLKinIMUX_CLK_OPTINV[1]
CEin~IMUX_CE_OPTINV[2]
WRITEin~IMUX_CE_OPTINV[1]
I[0]inIMUX_DATA[0]
I[1]inIMUX_DATA[1]
I[2]inIMUX_DATA[2]
I[3]inIMUX_DATA[3]
I[4]inIMUX_DATA[4]
I[5]inIMUX_DATA[5]
I[6]inIMUX_DATA[6]
I[7]inIMUX_DATA[7]
BUSYoutOUT_SEC[0]
O[0]outOUT_FAN[0]
O[1]outOUT_FAN[1]
O[2]outOUT_FAN[2]
O[3]outOUT_FAN[3]
O[4]outOUT_FAN[4]
O[5]outOUT_FAN[5]
O[6]outOUT_FAN[6]
O[7]outOUT_FAN[7]
spartan3 CNR_SE_S3A bel ICAP attribute bits
AttributeICAP

Bels SPI_ACCESS

spartan3 CNR_SE_S3A bel SPI_ACCESS pins
PinDirectionSPI_ACCESS
CLKinIMUX_CLK_OPTINV[3]
CSBin~IMUX_CE_OPTINV[0]
MOSIinIMUX_SR_OPTINV[2]
MISOoutOUT_SEC[14]
spartan3 CNR_SE_S3A bel SPI_ACCESS attribute bits
AttributeSPI_ACCESS
ENABLETERM_H[1][3]

Bels MISC_SE

spartan3 CNR_SE_S3A bel MISC_SE pins
PinDirectionMISC_SE
spartan3 CNR_SE_S3A bel MISC_SE attribute bits
AttributeMISC_SE
DONE_PULL[enum: IOB_PULL]
spartan3 CNR_SE_S3A enum IOB_PULL
MISC_SE.DONE_PULLTERM_H[1][6]
NONE1
PULLUP0

Bel wires

spartan3 CNR_SE_S3A bel wires
WirePins
IMUX_CLK_OPTINV[0]STARTUP.CLK
IMUX_CLK_OPTINV[1]ICAP.CLK
IMUX_CLK_OPTINV[2]CAPTURE.CLK
IMUX_CLK_OPTINV[3]SPI_ACCESS.CLK
IMUX_SR_OPTINV[0]STARTUP.GSR
IMUX_SR_OPTINV[1]CAPTURE.CAP
IMUX_SR_OPTINV[2]SPI_ACCESS.MOSI
IMUX_CE_OPTINV[0]SPI_ACCESS.CSB
IMUX_CE_OPTINV[1]ICAP.WRITE
IMUX_CE_OPTINV[2]ICAP.CE
IMUX_CE_OPTINV[3]STARTUP.GTS
IMUX_DATA[0]ICAP.I[0]
IMUX_DATA[1]ICAP.I[1]
IMUX_DATA[2]ICAP.I[2]
IMUX_DATA[3]ICAP.I[3]
IMUX_DATA[4]ICAP.I[4]
IMUX_DATA[5]ICAP.I[5]
IMUX_DATA[6]ICAP.I[6]
IMUX_DATA[7]ICAP.I[7]
OUT_FAN[0]ICAP.O[0]
OUT_FAN[1]ICAP.O[1]
OUT_FAN[2]ICAP.O[2]
OUT_FAN[3]ICAP.O[3]
OUT_FAN[4]ICAP.O[4]
OUT_FAN[5]ICAP.O[5]
OUT_FAN[6]ICAP.O[6]
OUT_FAN[7]ICAP.O[7]
OUT_SEC[0]ICAP.BUSY
OUT_SEC[14]SPI_ACCESS.MISO

Bitstream

spartan3 CNR_SE_S3A rect TERM_H
BitFrame
F1 F0
B63 - -
B62 - -
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 - -
B42 - -
B41 - -
B40 - -
B39 - -
B38 - -
B37 - -
B36 - -
B35 - -
B34 - -
B33 - -
B32 - -
B31 - -
B30 - -
B29 - -
B28 - -
B27 - -
B26 - -
B25 - -
B24 - -
B23 - -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - -
B12 - -
B11 - -
B10 - -
B9 - -
B8 - -
B7 - -
B6 MISC_SE: DONE_PULL bit 0 -
B5 - -
B4 STARTUP: USER_GTS_GSR_ENABLE -
B3 SPI_ACCESS: ENABLE -
B2 - -
B1 STARTUP: GTS_SYNC -
B0 STARTUP: GSR_SYNC -