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TODO: document

LR.S3

This tile is used on Spartan 3.

Tile LR.S3

Cells: 1 IRIs: 0

Bel DCI0

spartan3 LR.S3 bel DCI0
PinDirectionWires
ADDRESS0outputOUT.SEC0
ADDRESS1outputOUT.SEC1
ADDRESS2outputOUT.SEC2
DATAoutputOUT.SEC3
DCI_CLKinputIMUX.DATA23
DCI_DONEoutputOUT.SEC4
DCI_RESETinputIMUX.DATA22
HI_LO_NinputIMUX.DATA21
HI_LO_PinputIMUX.DATA20
IOUPDATEoutputOUT.SEC8
N_OR_PoutputOUT.SEC5
SCLKoutputOUT.SEC6
UPDATEoutputOUT.SEC7

Bel DCI1

spartan3 LR.S3 bel DCI1
PinDirectionWires
ADDRESS0outputOUT.SEC0
ADDRESS1outputOUT.SEC1
ADDRESS2outputOUT.SEC2
DATAoutputOUT.SEC3
DCI_CLKinputIMUX.DATA15
DCI_DONEoutputOUT.SEC4
DCI_RESETinputIMUX.DATA14
HI_LO_NinputIMUX.DATA13
HI_LO_PinputIMUX.DATA12
IOUPDATEoutputOUT.SEC8
N_OR_PoutputOUT.SEC5
SCLKoutputOUT.SEC6
UPDATEoutputOUT.SEC7

Bel DCIRESET0

spartan3 LR.S3 bel DCIRESET0
PinDirectionWires
RSTinputIMUX.DATA19

Bel DCIRESET1

spartan3 LR.S3 bel DCIRESET1
PinDirectionWires
RSTinputIMUX.DATA11

Bel STARTUP

spartan3 LR.S3 bel STARTUP
PinDirectionWires
CLKinputIMUX.CLK0
GSRinputIMUX.SR0
GTSinputIMUX.SR3

Bel CAPTURE

spartan3 LR.S3 bel CAPTURE
PinDirectionWires
CAPinputIMUX.SR1
CLKinputIMUX.CLK2

Bel ICAP

spartan3 LR.S3 bel ICAP
PinDirectionWires
BUSYoutputOUT.SEC8
CEinputIMUX.CE2
CLKinputIMUX.CLK1
I0inputIMUX.DATA0
I1inputIMUX.DATA1
I2inputIMUX.DATA2
I3inputIMUX.DATA3
I4inputIMUX.DATA4
I5inputIMUX.DATA5
I6inputIMUX.DATA6
I7inputIMUX.DATA7
O0outputOUT.FAN0
O1outputOUT.FAN1
O2outputOUT.FAN2
O3outputOUT.FAN3
O4outputOUT.FAN4
O5outputOUT.FAN5
O6outputOUT.FAN6
O7outputOUT.FAN7
WRITEinputIMUX.CE1

Bel wires

spartan3 LR.S3 bel wires
WirePins
IMUX.SR0STARTUP.GSR
IMUX.SR1CAPTURE.CAP
IMUX.SR3STARTUP.GTS
IMUX.CLK0STARTUP.CLK
IMUX.CLK1ICAP.CLK
IMUX.CLK2CAPTURE.CLK
IMUX.CE1ICAP.WRITE
IMUX.CE2ICAP.CE
IMUX.DATA0ICAP.I0
IMUX.DATA1ICAP.I1
IMUX.DATA2ICAP.I2
IMUX.DATA3ICAP.I3
IMUX.DATA4ICAP.I4
IMUX.DATA5ICAP.I5
IMUX.DATA6ICAP.I6
IMUX.DATA7ICAP.I7
IMUX.DATA11DCIRESET1.RST
IMUX.DATA12DCI1.HI_LO_P
IMUX.DATA13DCI1.HI_LO_N
IMUX.DATA14DCI1.DCI_RESET
IMUX.DATA15DCI1.DCI_CLK
IMUX.DATA19DCIRESET0.RST
IMUX.DATA20DCI0.HI_LO_P
IMUX.DATA21DCI0.HI_LO_N
IMUX.DATA22DCI0.DCI_RESET
IMUX.DATA23DCI0.DCI_CLK
OUT.FAN0ICAP.O0
OUT.FAN1ICAP.O1
OUT.FAN2ICAP.O2
OUT.FAN3ICAP.O3
OUT.FAN4ICAP.O4
OUT.FAN5ICAP.O5
OUT.FAN6ICAP.O6
OUT.FAN7ICAP.O7
OUT.SEC0DCI0.ADDRESS0, DCI1.ADDRESS0
OUT.SEC1DCI0.ADDRESS1, DCI1.ADDRESS1
OUT.SEC2DCI0.ADDRESS2, DCI1.ADDRESS2
OUT.SEC3DCI0.DATA, DCI1.DATA
OUT.SEC4DCI0.DCI_DONE, DCI1.DCI_DONE
OUT.SEC5DCI0.N_OR_P, DCI1.N_OR_P
OUT.SEC6DCI0.SCLK, DCI1.SCLK
OUT.SEC7DCI0.UPDATE, DCI1.UPDATE
OUT.SEC8DCI0.IOUPDATE, DCI1.IOUPDATE, ICAP.BUSY

Bitstream

spartan3 LR.S3 bittile 0
BitFrame
0 1
63 DCIRESET0:ENABLE DCIRESET1:ENABLE
62 DCI0:TEST_ENABLE DCI1:TEST_ENABLE
61 DCI0:FORCE_DONE_HIGH DCI1:FORCE_DONE_HIGH
60 - -
59 DCI0:PMASK_TERM_SPLIT[3] DCI1:PMASK_TERM_SPLIT[3]
58 DCI0:PMASK_TERM_SPLIT[2] DCI1:PMASK_TERM_SPLIT[2]
57 DCI0:PMASK_TERM_SPLIT[1] DCI1:PMASK_TERM_SPLIT[1]
56 DCI0:PMASK_TERM_SPLIT[0] DCI1:PMASK_TERM_SPLIT[0]
55 - -
54 DCI0:PMASK_TERM_VCC[3] DCI1:PMASK_TERM_VCC[3]
53 DCI0:PMASK_TERM_VCC[2] DCI1:PMASK_TERM_VCC[2]
52 DCI0:PMASK_TERM_VCC[1] DCI1:PMASK_TERM_VCC[1]
51 DCI0:PMASK_TERM_VCC[0] DCI1:PMASK_TERM_VCC[0]
50 MISC:DCI_TEST_MUX[0] -
49 DCI0:NMASK_TERM_SPLIT[3] DCI1:NMASK_TERM_SPLIT[3]
48 DCI0:NMASK_TERM_SPLIT[2] DCI1:NMASK_TERM_SPLIT[2]
47 DCI0:NMASK_TERM_SPLIT[1] DCI1:NMASK_TERM_SPLIT[1]
46 DCI0:NMASK_TERM_SPLIT[0] DCI1:NMASK_TERM_SPLIT[0]
45 DCI0:QUIET DCI1:QUIET
44 DCI0:ENABLE DCI1:ENABLE
43 - DCI1:LVDSBIAS[2]
42 - DCI1:LVDSBIAS[3]
41 - DCI1:LVDSBIAS[4]
40 - DCI1:LVDSBIAS[5]
39 - DCI1:LVDSBIAS[6]
38 - DCI1:LVDSBIAS[7]
37 - DCI1:LVDSBIAS[8]
36 - DCI1:LVDSBIAS[9]
35 - DCI1:LVDSBIAS[10]
34 - DCI1:LVDSBIAS[11]
33 - DCI1:LVDSBIAS[12]
32 - DCI0:LVDSBIAS[2]
31 - DCI0:LVDSBIAS[3]
30 - DCI0:LVDSBIAS[4]
29 - DCI0:LVDSBIAS[5]
28 - DCI0:LVDSBIAS[6]
27 - DCI0:LVDSBIAS[7]
26 - DCI0:LVDSBIAS[8]
25 - DCI0:LVDSBIAS[9]
24 - DCI0:LVDSBIAS[10]
23 - DCI0:LVDSBIAS[11]
22 - DCI0:LVDSBIAS[12]
21 - -
20 - -
19 - -
18 - -
17 - -
16 - -
15 - MISC:CCLKPIN[0]
14 - MISC:DONEPIN[0]
13 - MISC:DCM_ENABLE
12 - DCI1:LVDSBIAS[0]
11 - DCI1:LVDSBIAS[1]
10 - DCI0:LVDSBIAS[0]
9 - DCI0:LVDSBIAS[1]
8 - -
7 - -
6 - -
5 - -
4 - STARTUP:GTS_GSR_ENABLE
3 - ICAP:ENABLE
2 - -
1 - STARTUP:GTS_SYNC
0 - STARTUP:GSR_SYNC
DCI0:ENABLE 0.0.44
DCI0:FORCE_DONE_HIGH 0.0.61
DCI0:QUIET 0.0.45
DCI0:TEST_ENABLE 0.0.62
DCI1:ENABLE 0.1.44
DCI1:FORCE_DONE_HIGH 0.1.61
DCI1:QUIET 0.1.45
DCI1:TEST_ENABLE 0.1.62
DCIRESET0:ENABLE 0.0.63
DCIRESET1:ENABLE 0.1.63
ICAP:ENABLE 0.1.3
MISC:DCM_ENABLE 0.1.13
STARTUP:GSR_SYNC 0.1.0
STARTUP:GTS_GSR_ENABLE 0.1.4
STARTUP:GTS_SYNC 0.1.1
non-inverted [0]
DCI0:LVDSBIAS 0.1.22 0.1.23 0.1.24 0.1.25 0.1.26 0.1.27 0.1.28 0.1.29 0.1.30 0.1.31 0.1.32 0.1.9 0.1.10
DCI1:LVDSBIAS 0.1.33 0.1.34 0.1.35 0.1.36 0.1.37 0.1.38 0.1.39 0.1.40 0.1.41 0.1.42 0.1.43 0.1.11 0.1.12
non-inverted [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
DCI0:NMASK_TERM_SPLIT 0.0.49 0.0.48 0.0.47 0.0.46
DCI0:PMASK_TERM_SPLIT 0.0.59 0.0.58 0.0.57 0.0.56
DCI0:PMASK_TERM_VCC 0.0.54 0.0.53 0.0.52 0.0.51
DCI1:NMASK_TERM_SPLIT 0.1.49 0.1.48 0.1.47 0.1.46
DCI1:PMASK_TERM_SPLIT 0.1.59 0.1.58 0.1.57 0.1.56
DCI1:PMASK_TERM_VCC 0.1.54 0.1.53 0.1.52 0.1.51
non-inverted [3] [2] [1] [0]
MISC:CCLKPIN 0.1.15
MISC:DONEPIN 0.1.14
PULLUP 0
PULLNONE 1
MISC:DCI_TEST_MUX 0.0.50
DCI0 0
DCI1 1

LR.S3E

This tile is used on Spartan 3E.

Tile LR.S3E

Cells: 1 IRIs: 0

Bel STARTUP

spartan3 LR.S3E bel STARTUP
PinDirectionWires
CLKinputIMUX.CLK0
GSRinputIMUX.SR0
GTSinputIMUX.SR3
MBTinputIMUX.CE0

Bel CAPTURE

spartan3 LR.S3E bel CAPTURE
PinDirectionWires
CAPinputIMUX.SR1
CLKinputIMUX.CLK2

Bel ICAP

spartan3 LR.S3E bel ICAP
PinDirectionWires
BUSYoutputOUT.SEC8
CEinputIMUX.CE2
CLKinputIMUX.CLK1
I0inputIMUX.DATA0
I1inputIMUX.DATA1
I2inputIMUX.DATA2
I3inputIMUX.DATA3
I4inputIMUX.DATA4
I5inputIMUX.DATA5
I6inputIMUX.DATA6
I7inputIMUX.DATA7
O0outputOUT.FAN0
O1outputOUT.FAN1
O2outputOUT.FAN2
O3outputOUT.FAN3
O4outputOUT.FAN4
O5outputOUT.FAN5
O6outputOUT.FAN6
O7outputOUT.FAN7
WRITEinputIMUX.CE1

Bel wires

spartan3 LR.S3E bel wires
WirePins
IMUX.SR0STARTUP.GSR
IMUX.SR1CAPTURE.CAP
IMUX.SR3STARTUP.GTS
IMUX.CLK0STARTUP.CLK
IMUX.CLK1ICAP.CLK
IMUX.CLK2CAPTURE.CLK
IMUX.CE0STARTUP.MBT
IMUX.CE1ICAP.WRITE
IMUX.CE2ICAP.CE
IMUX.DATA0ICAP.I0
IMUX.DATA1ICAP.I1
IMUX.DATA2ICAP.I2
IMUX.DATA3ICAP.I3
IMUX.DATA4ICAP.I4
IMUX.DATA5ICAP.I5
IMUX.DATA6ICAP.I6
IMUX.DATA7ICAP.I7
OUT.FAN0ICAP.O0
OUT.FAN1ICAP.O1
OUT.FAN2ICAP.O2
OUT.FAN3ICAP.O3
OUT.FAN4ICAP.O4
OUT.FAN5ICAP.O5
OUT.FAN6ICAP.O6
OUT.FAN7ICAP.O7
OUT.SEC8ICAP.BUSY

Bitstream

spartan3 LR.S3E bittile 0
BitFrame
0 1
36 - BANK:LVDSBIAS_0[2]
35 - BANK:LVDSBIAS_0[3]
34 - BANK:LVDSBIAS_0[4]
33 - BANK:LVDSBIAS_1[5]
32 - BANK:LVDSBIAS_1[6]
31 - BANK:LVDSBIAS_1[7]
30 - BANK:LVDSBIAS_1[8]
29 - BANK:LVDSBIAS_1[9]
28 - BANK:LVDSBIAS_1[10]
27 - BANK:LVDSBIAS_0[5]
26 - BANK:LVDSBIAS_0[6]
25 - BANK:LVDSBIAS_0[7]
24 - BANK:LVDSBIAS_0[8]
23 - BANK:LVDSBIAS_0[9]
22 - BANK:LVDSBIAS_0[10]
21 - -
20 - -
19 - -
18 - -
17 - -
16 - -
15 - MISC:CCLKPIN[0]
14 - MISC:DONEPIN[0]
13 - BANK:LVDSBIAS_1[0]
12 - BANK:LVDSBIAS_0[0]
11 - BANK:LVDSBIAS_1[1]
10 - BANK:LVDSBIAS_1[2]
9 - BANK:LVDSBIAS_1[3]
8 - BANK:LVDSBIAS_1[4]
7 - BANK:LVDSBIAS_0[1]
6 - -
5 - -
4 - STARTUP:GTS_GSR_ENABLE
3 - -
2 - -
1 - STARTUP:GTS_SYNC
0 - STARTUP:GSR_SYNC
BANK:LVDSBIAS_0 0.1.22 0.1.23 0.1.24 0.1.25 0.1.26 0.1.27 0.1.34 0.1.35 0.1.36 0.1.7 0.1.12
BANK:LVDSBIAS_1 0.1.28 0.1.29 0.1.30 0.1.31 0.1.32 0.1.33 0.1.8 0.1.9 0.1.10 0.1.11 0.1.13
non-inverted [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
MISC:CCLKPIN 0.1.15
MISC:DONEPIN 0.1.14
PULLUP 0
PULLNONE 1
STARTUP:GSR_SYNC 0.1.0
STARTUP:GTS_GSR_ENABLE 0.1.4
STARTUP:GTS_SYNC 0.1.1
non-inverted [0]

LR.S3A

This tile is used on Spartan 3A.

Tile LR.S3A

Cells: 1 IRIs: 0

Bel STARTUP

spartan3 LR.S3A bel STARTUP
PinDirectionWires
CLKinputIMUX.CLK0
GSRinputIMUX.SR0
GTSinputIMUX.CE3

Bel CAPTURE

spartan3 LR.S3A bel CAPTURE
PinDirectionWires
CAPinputIMUX.SR1
CLKinputIMUX.CLK2

Bel ICAP

spartan3 LR.S3A bel ICAP
PinDirectionWires
BUSYoutputOUT.SEC0
CEinputIMUX.CE2
CLKinputIMUX.CLK1
I0inputIMUX.DATA0
I1inputIMUX.DATA1
I2inputIMUX.DATA2
I3inputIMUX.DATA3
I4inputIMUX.DATA4
I5inputIMUX.DATA5
I6inputIMUX.DATA6
I7inputIMUX.DATA7
O0outputOUT.FAN0
O1outputOUT.FAN1
O2outputOUT.FAN2
O3outputOUT.FAN3
O4outputOUT.FAN4
O5outputOUT.FAN5
O6outputOUT.FAN6
O7outputOUT.FAN7
WRITEinputIMUX.CE1

Bel SPI_ACCESS

spartan3 LR.S3A bel SPI_ACCESS
PinDirectionWires
CLKinputIMUX.CLK3
CSBinputIMUX.CE0
MISOoutputOUT.SEC14
MOSIinputIMUX.SR2

Bel wires

spartan3 LR.S3A bel wires
WirePins
IMUX.SR0STARTUP.GSR
IMUX.SR1CAPTURE.CAP
IMUX.SR2SPI_ACCESS.MOSI
IMUX.CLK0STARTUP.CLK
IMUX.CLK1ICAP.CLK
IMUX.CLK2CAPTURE.CLK
IMUX.CLK3SPI_ACCESS.CLK
IMUX.CE0SPI_ACCESS.CSB
IMUX.CE1ICAP.WRITE
IMUX.CE2ICAP.CE
IMUX.CE3STARTUP.GTS
IMUX.DATA0ICAP.I0
IMUX.DATA1ICAP.I1
IMUX.DATA2ICAP.I2
IMUX.DATA3ICAP.I3
IMUX.DATA4ICAP.I4
IMUX.DATA5ICAP.I5
IMUX.DATA6ICAP.I6
IMUX.DATA7ICAP.I7
OUT.FAN0ICAP.O0
OUT.FAN1ICAP.O1
OUT.FAN2ICAP.O2
OUT.FAN3ICAP.O3
OUT.FAN4ICAP.O4
OUT.FAN5ICAP.O5
OUT.FAN6ICAP.O6
OUT.FAN7ICAP.O7
OUT.SEC0ICAP.BUSY
OUT.SEC14SPI_ACCESS.MISO

Bitstream

spartan3 LR.S3A bittile 0
BitFrame
0 1
6 - MISC:DONEPIN[0]
5 - -
4 - STARTUP:GTS_GSR_ENABLE
3 - SPI_ACCESS:ENABLE
2 - -
1 - STARTUP:GTS_SYNC
0 - STARTUP:GSR_SYNC
MISC:DONEPIN 0.1.6
PULLUP 0
PULLNONE 1
SPI_ACCESS:ENABLE 0.1.3
STARTUP:GSR_SYNC 0.1.0
STARTUP:GTS_GSR_ENABLE 0.1.4
STARTUP:GTS_SYNC 0.1.1
non-inverted [0]