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Digital Clock Managers (Spartan 3)

TODO: reverse, document

Tile DCM_S3

Cells: 1

Bels DCM

spartan3 DCM_S3 bel DCM pins
PinDirectionDCM
CLKINinIMUX_CLK_OPTINV[2]
CLKFBinIMUX_CLK_OPTINV[3]
RSTinIMUX_DATA[19] invert by !MAIN[3][20]
PSCLKinIMUX_CLK_OPTINV[1]
PSENinIMUX_DATA[17] invert by !MAIN[3][12]
PSINCDECinIMUX_DATA[18] invert by !MAIN[3][56]
STSADRS[0]inIMUX_DATA[27] invert by !MAIN[3][24]
STSADRS[1]inIMUX_DATA[20] invert by !MAIN[3][4]
STSADRS[2]inIMUX_DATA[21] invert by !MAIN[3][51]
STSADRS[3]inIMUX_DATA[22] invert by !MAIN[3][15]
STSADRS[4]inIMUX_DATA[23] invert by !MAIN[3][63]
FREEZEDLLinIMUX_DATA[25] invert by !MAIN[3][11]
FREEZEDFSinIMUX_DATA[26] invert by !MAIN[3][57]
DSSENinIMUX_DATA[16]
CTLMODEinIMUX_DATA[24] invert by !MAIN[3][44]
CTLGOinIMUX_DATA[31] invert by !MAIN[3][62]
CTLOSC1inIMUX_DATA[30] invert by !MAIN[3][13]
CTLOSC2inIMUX_DATA[29] invert by !MAIN[3][52]
CTLSEL[0]inIMUX_DATA[2] invert by !MAIN[3][53]
CTLSEL[1]inIMUX_DATA[3] invert by !MAIN[3][19]
CTLSEL[2]inIMUX_DATA[28] invert by !MAIN[3][5]
CLK0outOUT_FAN[3]
CLK90outOUT_FAN[2]
CLK180outOUT_FAN[1]
CLK270outOUT_FAN[0]
CLK2XoutOUT_FAN[7]
CLK2X180outOUT_FAN[6]
CLKDVoutOUT_SEC[3]
CLKFXoutOUT_FAN[5]
CLKFX180outOUT_FAN[4]
CONCURoutOUT_SEC[1]
LOCKEDoutOUT_SEC[2]
PSDONEoutOUT_SEC[0]
STATUS[0]outOUT_SEC[8]
STATUS[1]outOUT_SEC[9]
STATUS[2]outOUT_SEC[10]
STATUS[3]outOUT_SEC[11]
STATUS[4]outOUT_SEC[4]
STATUS[5]outOUT_SEC[5]
STATUS[6]outOUT_SEC[6]
STATUS[7]outOUT_SEC[7]
spartan3 DCM_S3 bel DCM attribute bits
AttributeDCM
OUT_CLK0_ENABLEMAIN[3][36]
OUT_CLK90_ENABLEMAIN[3][35]
OUT_CLK180_ENABLEMAIN[3][34]
OUT_CLK270_ENABLEMAIN[3][33]
OUT_CLK2X_ENABLEMAIN[3][32]
OUT_CLK2X180_ENABLEMAIN[3][31]
OUT_CLKDV_ENABLEMAIN[3][30]
OUT_CLKFX_ENABLEMAIN[3][28]
OUT_CLKFX180_ENABLEMAIN[3][29]
OUT_CONCUR_ENABLEMAIN[3][27]
CLKDV_COUNT_MAX bit 0MAIN[1][4]
CLKDV_COUNT_MAX bit 1MAIN[1][5]
CLKDV_COUNT_MAX bit 2MAIN[1][6]
CLKDV_COUNT_MAX bit 3MAIN[1][7]
CLKDV_COUNT_FALL bit 0MAIN[1][8]
CLKDV_COUNT_FALL bit 1MAIN[1][9]
CLKDV_COUNT_FALL bit 2MAIN[1][10]
CLKDV_COUNT_FALL bit 3MAIN[1][11]
CLKDV_COUNT_FALL_2 bit 0MAIN[1][12]
CLKDV_COUNT_FALL_2 bit 1MAIN[1][13]
CLKDV_COUNT_FALL_2 bit 2MAIN[1][14]
CLKDV_COUNT_FALL_2 bit 3MAIN[1][15]
CLKDV_PHASE_RISE bit 0MAIN[3][2]
CLKDV_PHASE_RISE bit 1MAIN[2][1]
CLKDV_PHASE_FALL bit 0MAIN[2][2]
CLKDV_PHASE_FALL bit 1MAIN[2][3]
CLKDV_MODE[enum: DCM_CLKDV_MODE]
DESKEW_ADJUST bit 0MAIN[2][33]
DESKEW_ADJUST bit 1MAIN[2][34]
DESKEW_ADJUST bit 2MAIN[2][35]
DESKEW_ADJUST bit 3MAIN[2][36]
CLKIN_IOBMAIN[2][37]
CLKFB_IOBMAIN[2][38]
CLKIN_DIVIDE_BY_2MAIN[2][32]
CLK_FEEDBACK_2XMAIN[2][7]
DLL_ENABLEMAIN[1][33]
DLL_FREQUENCY_MODE[enum: DCM_FREQUENCY_MODE]
DFS_ENABLEMAIN[1][32]
DFS_FEEDBACKMAIN[2][59]
DFS_FREQUENCY_MODE[enum: DCM_FREQUENCY_MODE]
PHASE_SHIFT bit 0MAIN[1][38]
PHASE_SHIFT bit 1MAIN[1][39]
PHASE_SHIFT bit 2MAIN[1][40]
PHASE_SHIFT bit 3MAIN[1][41]
PHASE_SHIFT bit 4MAIN[1][42]
PHASE_SHIFT bit 5MAIN[1][43]
PHASE_SHIFT bit 6MAIN[1][44]
PHASE_SHIFT bit 7MAIN[1][45]
PHASE_SHIFT_NEGATIVEMAIN[1][37]
PS_ENABLEMAIN[1][35]
STARTUP_WAITMAIN[3][26]
V2_REG_COM bit 0MAIN[2][16]
V2_REG_COM bit 1MAIN[2][17]
V2_REG_COM bit 2MAIN[2][18]
V2_REG_COM bit 3MAIN[2][19]
V2_REG_COM bit 4MAIN[2][20]
V2_REG_COM bit 5MAIN[2][21]
V2_REG_COM bit 6MAIN[2][22]
V2_REG_COM bit 7MAIN[2][23]
V2_REG_COM bit 8MAIN[2][24]
V2_REG_COM bit 9MAIN[2][25]
V2_REG_COM bit 10MAIN[2][26]
V2_REG_COM bit 11MAIN[2][27]
V2_REG_COM bit 12MAIN[2][28]
V2_REG_COM bit 13MAIN[2][29]
V2_REG_COM bit 14MAIN[2][30]
V2_REG_COM bit 15MAIN[2][31]
V2_REG_COM bit 16MAIN[2][32]
V2_REG_COM bit 17MAIN[2][33]
V2_REG_COM bit 18MAIN[2][34]
V2_REG_COM bit 19MAIN[2][35]
V2_REG_COM bit 20MAIN[2][36]
V2_REG_COM bit 21MAIN[2][37]
V2_REG_COM bit 22MAIN[2][38]
V2_REG_COM bit 23MAIN[2][39]
V2_REG_COM bit 24MAIN[2][40]
V2_REG_COM bit 25MAIN[2][41]
V2_REG_COM bit 26MAIN[2][42]
V2_REG_COM bit 27MAIN[2][43]
V2_REG_COM bit 28MAIN[2][44]
V2_REG_COM bit 29MAIN[2][45]
V2_REG_COM bit 30MAIN[2][46]
V2_REG_COM bit 31MAIN[2][47]
V2_REG_DFS bit 0MAIN[1][48]
V2_REG_DFS bit 1MAIN[1][49]
V2_REG_DFS bit 2MAIN[1][50]
V2_REG_DFS bit 3MAIN[1][51]
V2_REG_DFS bit 4MAIN[1][52]
V2_REG_DFS bit 5MAIN[1][53]
V2_REG_DFS bit 6MAIN[1][54]
V2_REG_DFS bit 7MAIN[1][55]
V2_REG_DFS bit 8MAIN[1][56]
V2_REG_DFS bit 9MAIN[1][57]
V2_REG_DFS bit 10MAIN[1][58]
V2_REG_DFS bit 11MAIN[1][59]
V2_REG_DFS bit 12MAIN[1][60]
V2_REG_DFS bit 13MAIN[1][61]
V2_REG_DFS bit 14MAIN[1][62]
V2_REG_DFS bit 15MAIN[3][59]
V2_REG_DFS bit 16MAIN[2][48]
V2_REG_DFS bit 17MAIN[2][49]
V2_REG_DFS bit 18MAIN[2][50]
V2_REG_DFS bit 19MAIN[2][51]
V2_REG_DFS bit 20MAIN[2][52]
V2_REG_DFS bit 21MAIN[2][53]
V2_REG_DFS bit 22MAIN[2][54]
V2_REG_DFS bit 23MAIN[2][55]
V2_REG_DFS bit 24MAIN[2][56]
V2_REG_DFS bit 25MAIN[2][57]
V2_REG_DFS bit 26MAIN[2][58]
V2_REG_DFS bit 27MAIN[2][59]
V2_REG_DFS bit 28MAIN[2][60]
V2_REG_DFS bit 29MAIN[2][61]
V2_REG_DFS bit 30MAIN[2][62]
V2_REG_DFS bit 31MAIN[3][60]
V2_REG_DLLC bit 0MAIN[3][1]
V2_REG_DLLC bit 1MAIN[1][1]
V2_REG_DLLC bit 2MAIN[1][2]
V2_REG_DLLC bit 3MAIN[1][3]
V2_REG_DLLC bit 4MAIN[1][4]
V2_REG_DLLC bit 5MAIN[1][5]
V2_REG_DLLC bit 6MAIN[1][6]
V2_REG_DLLC bit 7MAIN[1][7]
V2_REG_DLLC bit 8MAIN[1][8]
V2_REG_DLLC bit 9MAIN[1][9]
V2_REG_DLLC bit 10MAIN[1][10]
V2_REG_DLLC bit 11MAIN[1][11]
V2_REG_DLLC bit 12MAIN[1][12]
V2_REG_DLLC bit 13MAIN[1][13]
V2_REG_DLLC bit 14MAIN[1][14]
V2_REG_DLLC bit 15MAIN[1][15]
V2_REG_DLLC bit 16MAIN[3][2]
V2_REG_DLLC bit 17MAIN[2][1]
V2_REG_DLLC bit 18MAIN[2][2]
V2_REG_DLLC bit 19MAIN[2][3]
V2_REG_DLLC bit 20MAIN[2][4]
V2_REG_DLLC bit 21MAIN[2][5]
V2_REG_DLLC bit 22MAIN[2][6]
V2_REG_DLLC bit 23MAIN[2][7]
V2_REG_DLLC bit 24MAIN[2][8]
V2_REG_DLLC bit 25MAIN[2][9]
V2_REG_DLLC bit 26MAIN[2][10]
V2_REG_DLLC bit 27MAIN[2][11]
V2_REG_DLLC bit 28MAIN[2][12]
V2_REG_DLLC bit 29MAIN[2][13]
V2_REG_DLLC bit 30MAIN[2][14]
V2_REG_DLLC bit 31MAIN[2][15]
V2_REG_DLLS bit 0MAIN[1][16]
V2_REG_DLLS bit 1MAIN[1][17]
V2_REG_DLLS bit 2MAIN[1][18]
V2_REG_DLLS bit 3MAIN[1][19]
V2_REG_DLLS bit 4MAIN[1][20]
V2_REG_DLLS bit 5MAIN[1][21]
V2_REG_DLLS bit 6MAIN[1][22]
V2_REG_DLLS bit 7MAIN[1][23]
V2_REG_DLLS bit 8MAIN[1][24]
V2_REG_DLLS bit 9MAIN[1][25]
V2_REG_DLLS bit 10MAIN[1][26]
V2_REG_DLLS bit 11MAIN[1][27]
V2_REG_DLLS bit 12MAIN[1][28]
V2_REG_DLLS bit 13MAIN[1][29]
V2_REG_DLLS bit 14MAIN[1][30]
V2_REG_DLLS bit 15MAIN[1][31]
V2_REG_DLLS bit 16MAIN[1][32]
V2_REG_DLLS bit 17MAIN[1][33]
V2_REG_DLLS bit 18MAIN[1][34]
V2_REG_DLLS bit 19MAIN[1][35]
V2_REG_DLLS bit 20MAIN[1][36]
V2_REG_DLLS bit 21MAIN[1][37]
V2_REG_DLLS bit 22MAIN[1][38]
V2_REG_DLLS bit 23MAIN[1][39]
V2_REG_DLLS bit 24MAIN[1][40]
V2_REG_DLLS bit 25MAIN[1][41]
V2_REG_DLLS bit 26MAIN[1][42]
V2_REG_DLLS bit 27MAIN[1][43]
V2_REG_DLLS bit 28MAIN[1][44]
V2_REG_DLLS bit 29MAIN[1][45]
V2_REG_DLLS bit 30MAIN[1][46]
V2_REG_DLLS bit 31MAIN[1][47]
S3_REG_MISC bit 0MAIN[3][37]
S3_REG_MISC bit 1MAIN[3][36]
S3_REG_MISC bit 2MAIN[3][35]
S3_REG_MISC bit 3MAIN[3][34]
S3_REG_MISC bit 4MAIN[3][33]
S3_REG_MISC bit 5MAIN[3][32]
S3_REG_MISC bit 6MAIN[3][31]
S3_REG_MISC bit 7MAIN[3][30]
S3_REG_MISC bit 8MAIN[3][29]
S3_REG_MISC bit 9MAIN[3][28]
S3_REG_MISC bit 10MAIN[3][27]
S3_REG_MISC bit 11MAIN[3][26]
V2_CLKFX_MULTIPLY bit 0MAIN[1][60]
V2_CLKFX_MULTIPLY bit 1MAIN[1][61]
V2_CLKFX_MULTIPLY bit 2MAIN[1][62]
V2_CLKFX_MULTIPLY bit 3MAIN[3][59]
V2_CLKFX_MULTIPLY bit 4MAIN[2][48]
V2_CLKFX_MULTIPLY bit 5MAIN[2][49]
V2_CLKFX_MULTIPLY bit 6MAIN[2][50]
V2_CLKFX_MULTIPLY bit 7MAIN[2][51]
V2_CLKFX_MULTIPLY bit 8MAIN[2][52]
V2_CLKFX_MULTIPLY bit 9MAIN[2][53]
V2_CLKFX_MULTIPLY bit 10MAIN[2][54]
V2_CLKFX_MULTIPLY bit 11MAIN[2][55]
V2_CLKFX_DIVIDE bit 0MAIN[1][48]
V2_CLKFX_DIVIDE bit 1MAIN[1][49]
V2_CLKFX_DIVIDE bit 2MAIN[1][50]
V2_CLKFX_DIVIDE bit 3MAIN[1][51]
V2_CLKFX_DIVIDE bit 4MAIN[1][52]
V2_CLKFX_DIVIDE bit 5MAIN[1][53]
V2_CLKFX_DIVIDE bit 6MAIN[1][54]
V2_CLKFX_DIVIDE bit 7MAIN[1][55]
V2_CLKFX_DIVIDE bit 8MAIN[1][56]
V2_CLKFX_DIVIDE bit 9MAIN[1][57]
V2_CLKFX_DIVIDE bit 10MAIN[1][58]
V2_CLKFX_DIVIDE bit 11MAIN[1][59]
V2_DUTY_CYCLE_CORRECTION bit 0MAIN[1][1]
V2_DUTY_CYCLE_CORRECTION bit 1MAIN[1][2]
V2_DUTY_CYCLE_CORRECTION bit 2MAIN[1][3]
V2_DUTY_CYCLE_CORRECTION bit 3MAIN[3][1]
CLKFB_ENABLEMAIN[1][34]
STATUS1_ENABLEMAIN[2][12]
STATUS7_ENABLEMAIN[2][11]
PL_CENTEREDMAIN[3][60]
PS_CENTEREDMAIN[2][9]
PS_MODE[enum: DCM_PS_MODE]
SEL_PL_DLY bit 0MAIN[2][61]
SEL_PL_DLY bit 1MAIN[2][62]
COIN_WINDOW bit 0MAIN[2][45]
COIN_WINDOW bit 1MAIN[2][46]
NON_STOPMAIN[2][47]
EN_OSC_COARSEMAIN[0][44]
FACTORY_JF1 bit 0MAIN[1][24]
FACTORY_JF1 bit 1MAIN[1][25]
FACTORY_JF1 bit 2MAIN[1][26]
FACTORY_JF1 bit 3MAIN[1][27]
FACTORY_JF1 bit 4MAIN[1][28]
FACTORY_JF1 bit 5MAIN[1][29]
FACTORY_JF1 bit 6MAIN[1][30]
FACTORY_JF1 bit 7MAIN[1][31]
FACTORY_JF2 bit 0MAIN[1][16]
FACTORY_JF2 bit 1MAIN[1][17]
FACTORY_JF2 bit 2MAIN[1][18]
FACTORY_JF2 bit 3MAIN[1][19]
FACTORY_JF2 bit 4MAIN[1][20]
FACTORY_JF2 bit 5MAIN[1][21]
FACTORY_JF2 bit 6MAIN[1][22]
FACTORY_JF2 bit 7MAIN[1][23]
TEST_OSC[enum: DCM_TEST_OSC]
ZD2_BY1MAIN[0][39]
V2_VBG_SEL bit 0MAIN[2][40]
V2_VBG_SEL bit 1MAIN[2][41]
V2_VBG_SEL bit 2MAIN[2][42]
V2_VBG_PD bit 0MAIN[2][43]
V2_VBG_PD bit 1MAIN[2][44]
ZD1_BY1MAIN[0][38]
RESET_PS_SELMAIN[0][37]
CFG_DLL_LP bit 0MAIN[0][25]
CFG_DLL_LP bit 1MAIN[0][26]
CFG_DLL_LP bit 2MAIN[0][27]
CFG_DLL_PS bit 0MAIN[0][28]
CFG_DLL_PS bit 1MAIN[0][29]
CFG_DLL_PS bit 2MAIN[0][30]
CFG_DLL_PS bit 3MAIN[0][31]
CFG_DLL_PS bit 4MAIN[0][32]
CFG_DLL_PS bit 5MAIN[0][33]
CFG_DLL_PS bit 6MAIN[0][34]
CFG_DLL_PS bit 7MAIN[0][35]
CFG_DLL_PS bit 8MAIN[0][36]
S3_EN_DUMMY_OSCMAIN[0][40]
EN_OLD_OSCCTLMAIN[0][16]
EN_PWCTLMAIN[0][20]
EN_RELRST_BMAIN[0][17]
EXTENDED_FLUSH_TIMEMAIN[0][43]
EXTENDED_HALT_TIMEMAIN[0][42]
EXTENDED_RUN_TIMEMAIN[0][41]
INVERT_ZD1_CUSTOMMAIN[0][14]
LPON_B_DFS bit 0MAIN[0][18]
LPON_B_DFS bit 1MAIN[0][19]
M1D1MAIN[0][23]
MIS1MAIN[0][22]
SEL_HSYNC_B bit 0MAIN[0][24]
SEL_HSYNC_B bit 1MAIN[0][21]
SPLY_IDC bit 0MAIN[0][45]
SPLY_IDC bit 1MAIN[0][46]
TRIM_LP_BMAIN[0][15]
VREG_PROBE bit 0MAIN[3][55]
VREG_PROBE bit 1MAIN[3][54]
VREG_PROBE bit 2MAIN[3][47]
VREG_PROBE bit 3MAIN[3][46]
VREG_PROBE bit 4MAIN[3][14]
spartan3 DCM_S3 enum DCM_CLKDV_MODE
DCM.CLKDV_MODEMAIN[2][4]
HALF0
INT1
spartan3 DCM_S3 enum DCM_FREQUENCY_MODE
DCM.DLL_FREQUENCY_MODEMAIN[2][8]
DCM.DFS_FREQUENCY_MODEMAIN[2][60]
LOW0
HIGH1
spartan3 DCM_S3 enum DCM_PS_MODE
DCM.PS_MODEMAIN[2][10]
CLKIN1
CLKFB0
spartan3 DCM_S3 enum DCM_TEST_OSC
DCM.TEST_OSCMAIN[2][6]MAIN[2][5]
_9000
_18001
_27010
_36011

Bel wires

spartan3 DCM_S3 bel wires
WirePins
IMUX_CLK_OPTINV[1]DCM.PSCLK
IMUX_CLK_OPTINV[2]DCM.CLKIN
IMUX_CLK_OPTINV[3]DCM.CLKFB
IMUX_DATA[2]DCM.CTLSEL[0]
IMUX_DATA[3]DCM.CTLSEL[1]
IMUX_DATA[16]DCM.DSSEN
IMUX_DATA[17]DCM.PSEN
IMUX_DATA[18]DCM.PSINCDEC
IMUX_DATA[19]DCM.RST
IMUX_DATA[20]DCM.STSADRS[1]
IMUX_DATA[21]DCM.STSADRS[2]
IMUX_DATA[22]DCM.STSADRS[3]
IMUX_DATA[23]DCM.STSADRS[4]
IMUX_DATA[24]DCM.CTLMODE
IMUX_DATA[25]DCM.FREEZEDLL
IMUX_DATA[26]DCM.FREEZEDFS
IMUX_DATA[27]DCM.STSADRS[0]
IMUX_DATA[28]DCM.CTLSEL[2]
IMUX_DATA[29]DCM.CTLOSC2
IMUX_DATA[30]DCM.CTLOSC1
IMUX_DATA[31]DCM.CTLGO
OUT_FAN[0]DCM.CLK270
OUT_FAN[1]DCM.CLK180
OUT_FAN[2]DCM.CLK90
OUT_FAN[3]DCM.CLK0
OUT_FAN[4]DCM.CLKFX180
OUT_FAN[5]DCM.CLKFX
OUT_FAN[6]DCM.CLK2X180
OUT_FAN[7]DCM.CLK2X
OUT_SEC[0]DCM.PSDONE
OUT_SEC[1]DCM.CONCUR
OUT_SEC[2]DCM.LOCKED
OUT_SEC[3]DCM.CLKDV
OUT_SEC[4]DCM.STATUS[4]
OUT_SEC[5]DCM.STATUS[5]
OUT_SEC[6]DCM.STATUS[6]
OUT_SEC[7]DCM.STATUS[7]
OUT_SEC[8]DCM.STATUS[0]
OUT_SEC[9]DCM.STATUS[1]
OUT_SEC[10]DCM.STATUS[2]
OUT_SEC[11]DCM.STATUS[3]

Bitstream

spartan3 DCM_S3 rect MAIN
BitFrame
F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B63 - - - - - - - - - - - - - - - DCM: !invert STSADRS[4] - - -
B62 - - - - - - - - - - - - - - - DCM: !invert CTLGO DCM: V2_REG_DFS bit 30 DCM: SEL_PL_DLY bit 1 DCM: V2_REG_DFS bit 14 DCM: V2_CLKFX_MULTIPLY bit 2 -
B61 - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 29 DCM: SEL_PL_DLY bit 0 DCM: V2_REG_DFS bit 13 DCM: V2_CLKFX_MULTIPLY bit 1 -
B60 - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 31 DCM: PL_CENTERED DCM: V2_REG_DFS bit 28 DCM: DFS_FREQUENCY_MODE bit 0 DCM: V2_REG_DFS bit 12 DCM: V2_CLKFX_MULTIPLY bit 0 -
B59 - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 15 DCM: V2_CLKFX_MULTIPLY bit 3 DCM: DFS_FEEDBACK DCM: V2_REG_DFS bit 27 DCM: V2_REG_DFS bit 11 DCM: V2_CLKFX_DIVIDE bit 11 -
B58 - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 26 DCM: V2_REG_DFS bit 10 DCM: V2_CLKFX_DIVIDE bit 10 -
B57 - - - - - - - - - - - - - - - DCM: !invert FREEZEDFS DCM: V2_REG_DFS bit 25 DCM: V2_REG_DFS bit 9 DCM: V2_CLKFX_DIVIDE bit 9 -
B56 - - - - - - - - - - - - - - - DCM: !invert PSINCDEC DCM: V2_REG_DFS bit 24 DCM: V2_REG_DFS bit 8 DCM: V2_CLKFX_DIVIDE bit 8 -
B55 - - - - - - - - - - - - - - - DCM: VREG_PROBE bit 0 DCM: V2_REG_DFS bit 23 DCM: V2_CLKFX_MULTIPLY bit 11 DCM: V2_REG_DFS bit 7 DCM: V2_CLKFX_DIVIDE bit 7 -
B54 - - - - - - - - - - - - - - - DCM: VREG_PROBE bit 1 DCM: V2_REG_DFS bit 22 DCM: V2_CLKFX_MULTIPLY bit 10 DCM: V2_REG_DFS bit 6 DCM: V2_CLKFX_DIVIDE bit 6 -
B53 - - - - - - - - - - - - - - - DCM: !invert CTLSEL[0] DCM: V2_REG_DFS bit 21 DCM: V2_CLKFX_MULTIPLY bit 9 DCM: V2_REG_DFS bit 5 DCM: V2_CLKFX_DIVIDE bit 5 -
B52 - - - - - - - - - - - - - - - DCM: !invert CTLOSC2 DCM: V2_REG_DFS bit 20 DCM: V2_CLKFX_MULTIPLY bit 8 DCM: V2_REG_DFS bit 4 DCM: V2_CLKFX_DIVIDE bit 4 -
B51 - - - - - - - - - - - - - - - DCM: !invert STSADRS[2] DCM: V2_REG_DFS bit 19 DCM: V2_CLKFX_MULTIPLY bit 7 DCM: V2_REG_DFS bit 3 DCM: V2_CLKFX_DIVIDE bit 3 -
B50 - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 18 DCM: V2_CLKFX_MULTIPLY bit 6 DCM: V2_REG_DFS bit 2 DCM: V2_CLKFX_DIVIDE bit 2 -
B49 - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 17 DCM: V2_CLKFX_MULTIPLY bit 5 DCM: V2_REG_DFS bit 1 DCM: V2_CLKFX_DIVIDE bit 1 -
B48 - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 16 DCM: V2_CLKFX_MULTIPLY bit 4 DCM: V2_REG_DFS bit 0 DCM: V2_CLKFX_DIVIDE bit 0 -
B47 - - - - - - - - - - - - - - - DCM: VREG_PROBE bit 2 DCM: V2_REG_COM bit 31 DCM: NON_STOP DCM: V2_REG_DLLS bit 31 -
B46 - - - - - - - - - - - - - - - DCM: VREG_PROBE bit 3 DCM: V2_REG_COM bit 30 DCM: COIN_WINDOW bit 1 DCM: V2_REG_DLLS bit 30 DCM: SPLY_IDC bit 1
B45 - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 29 DCM: COIN_WINDOW bit 0 DCM: PHASE_SHIFT bit 7 DCM: V2_REG_DLLS bit 29 DCM: SPLY_IDC bit 0
B44 - - - - - - - - - - - - - - - DCM: !invert CTLMODE DCM: V2_REG_COM bit 28 DCM: V2_VBG_PD bit 1 DCM: PHASE_SHIFT bit 6 DCM: V2_REG_DLLS bit 28 DCM: EN_OSC_COARSE
B43 - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 27 DCM: V2_VBG_PD bit 0 DCM: PHASE_SHIFT bit 5 DCM: V2_REG_DLLS bit 27 DCM: EXTENDED_FLUSH_TIME
B42 - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 26 DCM: V2_VBG_SEL bit 2 DCM: PHASE_SHIFT bit 4 DCM: V2_REG_DLLS bit 26 DCM: EXTENDED_HALT_TIME
B41 - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 25 DCM: V2_VBG_SEL bit 1 DCM: PHASE_SHIFT bit 3 DCM: V2_REG_DLLS bit 25 DCM: EXTENDED_RUN_TIME
B40 - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 24 DCM: V2_VBG_SEL bit 0 DCM: PHASE_SHIFT bit 2 DCM: V2_REG_DLLS bit 24 DCM: S3_EN_DUMMY_OSC
B39 - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 23 DCM: PHASE_SHIFT bit 1 DCM: V2_REG_DLLS bit 23 DCM: ZD2_BY1
B38 - - - - - - - - - - - - - - - - DCM: CLKFB_IOB DCM: V2_REG_COM bit 22 DCM: PHASE_SHIFT bit 0 DCM: V2_REG_DLLS bit 22 DCM: ZD1_BY1
B37 - - - - - - - - - - - - - - - DCM: S3_REG_MISC bit 0 DCM: CLKIN_IOB DCM: V2_REG_COM bit 21 DCM: PHASE_SHIFT_NEGATIVE DCM: V2_REG_DLLS bit 21 DCM: RESET_PS_SEL
B36 - - - - - - - - - - - - - - - DCM: OUT_CLK0_ENABLE DCM: S3_REG_MISC bit 1 DCM: DESKEW_ADJUST bit 3 DCM: V2_REG_COM bit 20 DCM: V2_REG_DLLS bit 20 DCM: CFG_DLL_PS bit 8
B35 - - - - - - - - - - - - - - - DCM: OUT_CLK90_ENABLE DCM: S3_REG_MISC bit 2 DCM: DESKEW_ADJUST bit 2 DCM: V2_REG_COM bit 19 DCM: PS_ENABLE DCM: V2_REG_DLLS bit 19 DCM: CFG_DLL_PS bit 7
B34 - - - - - - - - - - - - - - - DCM: OUT_CLK180_ENABLE DCM: S3_REG_MISC bit 3 DCM: DESKEW_ADJUST bit 1 DCM: V2_REG_COM bit 18 DCM: V2_REG_DLLS bit 18 DCM: CLKFB_ENABLE DCM: CFG_DLL_PS bit 6
B33 - - - - - - - - - - - - - - - DCM: OUT_CLK270_ENABLE DCM: S3_REG_MISC bit 4 DCM: DESKEW_ADJUST bit 0 DCM: V2_REG_COM bit 17 DCM: DLL_ENABLE DCM: V2_REG_DLLS bit 17 DCM: CFG_DLL_PS bit 5
B32 - - - - - - - - - - - - - - - DCM: OUT_CLK2X_ENABLE DCM: S3_REG_MISC bit 5 DCM: CLKIN_DIVIDE_BY_2 DCM: V2_REG_COM bit 16 DCM: DFS_ENABLE DCM: V2_REG_DLLS bit 16 DCM: CFG_DLL_PS bit 4
B31 - - - - - - - - - - - - - - - DCM: OUT_CLK2X180_ENABLE DCM: S3_REG_MISC bit 6 DCM: V2_REG_COM bit 15 DCM: V2_REG_DLLS bit 15 DCM: FACTORY_JF1 bit 7 DCM: CFG_DLL_PS bit 3
B30 - - - - - - - - - - - - - - - DCM: OUT_CLKDV_ENABLE DCM: S3_REG_MISC bit 7 DCM: V2_REG_COM bit 14 DCM: V2_REG_DLLS bit 14 DCM: FACTORY_JF1 bit 6 DCM: CFG_DLL_PS bit 2
B29 - - - - - - - - - - - - - - - DCM: OUT_CLKFX180_ENABLE DCM: S3_REG_MISC bit 8 DCM: V2_REG_COM bit 13 DCM: V2_REG_DLLS bit 13 DCM: FACTORY_JF1 bit 5 DCM: CFG_DLL_PS bit 1
B28 - - - - - - - - - - - - - - - DCM: OUT_CLKFX_ENABLE DCM: S3_REG_MISC bit 9 DCM: V2_REG_COM bit 12 DCM: V2_REG_DLLS bit 12 DCM: FACTORY_JF1 bit 4 DCM: CFG_DLL_PS bit 0
B27 - - - - - - - - - - - - - - - DCM: OUT_CONCUR_ENABLE DCM: S3_REG_MISC bit 10 DCM: V2_REG_COM bit 11 DCM: V2_REG_DLLS bit 11 DCM: FACTORY_JF1 bit 3 DCM: CFG_DLL_LP bit 2
B26 - - - - - - - - - - - - - - - DCM: STARTUP_WAIT DCM: S3_REG_MISC bit 11 DCM: V2_REG_COM bit 10 DCM: V2_REG_DLLS bit 10 DCM: FACTORY_JF1 bit 2 DCM: CFG_DLL_LP bit 1
B25 - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 9 DCM: V2_REG_DLLS bit 9 DCM: FACTORY_JF1 bit 1 DCM: CFG_DLL_LP bit 0
B24 - - - - - - - - - - - - - - - DCM: !invert STSADRS[0] DCM: V2_REG_COM bit 8 DCM: V2_REG_DLLS bit 8 DCM: FACTORY_JF1 bit 0 DCM: SEL_HSYNC_B bit 0
B23 - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 7 DCM: V2_REG_DLLS bit 7 DCM: FACTORY_JF2 bit 7 DCM: M1D1
B22 - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 6 DCM: V2_REG_DLLS bit 6 DCM: FACTORY_JF2 bit 6 DCM: MIS1
B21 - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 5 DCM: V2_REG_DLLS bit 5 DCM: FACTORY_JF2 bit 5 DCM: SEL_HSYNC_B bit 1
B20 - - - - - - - - - - - - - - - DCM: !invert RST DCM: V2_REG_COM bit 4 DCM: V2_REG_DLLS bit 4 DCM: FACTORY_JF2 bit 4 DCM: EN_PWCTL
B19 - - - - - - - - - - - - - - - DCM: !invert CTLSEL[1] DCM: V2_REG_COM bit 3 DCM: V2_REG_DLLS bit 3 DCM: FACTORY_JF2 bit 3 DCM: LPON_B_DFS bit 1
B18 - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 2 DCM: V2_REG_DLLS bit 2 DCM: FACTORY_JF2 bit 2 DCM: LPON_B_DFS bit 0
B17 - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 1 DCM: V2_REG_DLLS bit 1 DCM: FACTORY_JF2 bit 1 DCM: EN_RELRST_B
B16 - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 0 DCM: V2_REG_DLLS bit 0 DCM: FACTORY_JF2 bit 0 DCM: EN_OLD_OSCCTL
B15 - - - - - - - - - - - - - - - DCM: !invert STSADRS[3] DCM: V2_REG_DLLC bit 31 DCM: CLKDV_COUNT_FALL_2 bit 3 DCM: V2_REG_DLLC bit 15 DCM: TRIM_LP_B
B14 - - - - - - - - - - - - - - - DCM: VREG_PROBE bit 4 DCM: V2_REG_DLLC bit 30 DCM: CLKDV_COUNT_FALL_2 bit 2 DCM: V2_REG_DLLC bit 14 DCM: INVERT_ZD1_CUSTOM
B13 - - - - - - - - - - - - - - - DCM: !invert CTLOSC1 DCM: V2_REG_DLLC bit 29 DCM: CLKDV_COUNT_FALL_2 bit 1 DCM: V2_REG_DLLC bit 13 -
B12 - - - - - - - - - - - - - - - DCM: !invert PSEN DCM: V2_REG_DLLC bit 28 DCM: STATUS1_ENABLE DCM: CLKDV_COUNT_FALL_2 bit 0 DCM: V2_REG_DLLC bit 12 -
B11 - - - - - - - - - - - - - - - DCM: !invert FREEZEDLL DCM: V2_REG_DLLC bit 27 DCM: STATUS7_ENABLE DCM: CLKDV_COUNT_FALL bit 3 DCM: V2_REG_DLLC bit 11 -
B10 - - - - - - - - - - - - - - - - DCM: V2_REG_DLLC bit 26 DCM: PS_MODE bit 0 DCM: CLKDV_COUNT_FALL bit 2 DCM: V2_REG_DLLC bit 10 -
B9 - - - - - - - - - - - - - - - - DCM: V2_REG_DLLC bit 25 DCM: PS_CENTERED DCM: CLKDV_COUNT_FALL bit 1 DCM: V2_REG_DLLC bit 9 -
B8 - - - - - - - - - - - - - - - - DCM: V2_REG_DLLC bit 24 DCM: DLL_FREQUENCY_MODE bit 0 DCM: CLKDV_COUNT_FALL bit 0 DCM: V2_REG_DLLC bit 8 -
B7 - - - - - - - - - - - - - - - - DCM: CLK_FEEDBACK_2X DCM: V2_REG_DLLC bit 23 DCM: CLKDV_COUNT_MAX bit 3 DCM: V2_REG_DLLC bit 7 -
B6 - - - - - - - - - - - - - - - - DCM: V2_REG_DLLC bit 22 DCM: TEST_OSC bit 1 DCM: CLKDV_COUNT_MAX bit 2 DCM: V2_REG_DLLC bit 6 -
B5 - - - - - - - - - - - - - - - DCM: !invert CTLSEL[2] DCM: V2_REG_DLLC bit 21 DCM: TEST_OSC bit 0 DCM: CLKDV_COUNT_MAX bit 1 DCM: V2_REG_DLLC bit 5 -
B4 - - - - - - - - - - - - - - - DCM: !invert STSADRS[1] DCM: V2_REG_DLLC bit 20 DCM: CLKDV_MODE bit 0 DCM: CLKDV_COUNT_MAX bit 0 DCM: V2_REG_DLLC bit 4 -
B3 - - - - - - - - - - - - - - - - DCM: CLKDV_PHASE_FALL bit 1 DCM: V2_REG_DLLC bit 19 DCM: V2_REG_DLLC bit 3 DCM: V2_DUTY_CYCLE_CORRECTION bit 2 -
B2 - - - - - - - - - - - - - - - DCM: CLKDV_PHASE_RISE bit 0 DCM: V2_REG_DLLC bit 16 DCM: CLKDV_PHASE_FALL bit 0 DCM: V2_REG_DLLC bit 18 DCM: V2_REG_DLLC bit 2 DCM: V2_DUTY_CYCLE_CORRECTION bit 1 -
B1 - - - - - - - - - - - - - - - DCM: V2_REG_DLLC bit 0 DCM: V2_DUTY_CYCLE_CORRECTION bit 3 DCM: CLKDV_PHASE_RISE bit 1 DCM: V2_REG_DLLC bit 17 DCM: V2_REG_DLLC bit 1 DCM: V2_DUTY_CYCLE_CORRECTION bit 0 -
B0 - - - - - - - - - - - - - - - - - - -

Tile DCMCONN_S

Cells: 1

Switchbox DCMCONN

spartan3 DCMCONN_S switchbox DCMCONN
DestinationSourceKind
DCM_BUS[0]OMUX[0]fixed buffer
DCM_BUS[1]OMUX[3]fixed buffer
DCM_BUS[2]OMUX[4]fixed buffer
DCM_BUS[3]OMUX[5]fixed buffer

Tile DCMCONN_N

Cells: 1

Switchbox DCMCONN

spartan3 DCMCONN_N switchbox DCMCONN
DestinationSourceKind
DCM_BUS[0]OMUX[10]fixed buffer
DCM_BUS[1]OMUX[11]fixed buffer
DCM_BUS[2]OMUX[12]fixed buffer
DCM_BUS[3]OMUX[15]fixed buffer

Device data

Device data dcm-data

spartan3 device data dcm-data
Device DCM_DESKEW_ADJUST DCM_V2_VBG_PD DCM_V2_VBG_SEL
xc3s50 0b0111 0b10 0b100
xa3s50 0b0111 0b10 0b100
xc3s200 0b0111 0b10 0b100
xa3s200 0b0111 0b10 0b100
xc3s400 0b0111 0b10 0b100
xa3s400 0b0111 0b10 0b100
xc3s1000 0b1000 0b10 0b100
xa3s1000 0b1000 0b10 0b100
xc3s1000l 0b1000 0b10 0b100
xc3s1500 0b1000 0b10 0b100
xa3s1500 0b1000 0b10 0b100
xc3s1500l 0b1000 0b10 0b100
xc3s2000 0b1000 0b10 0b100
xc3s4000 0b1000 0b10 0b100
xc3s4000l 0b1000 0b10 0b100
xc3s5000 0b1000 0b10 0b100
xcexf10 - - -
xcexf20 - - -
xcexf40 - - -
xc3s100e 0b0110 - -
xa3s100e 0b0110 - -
xc3s250e 0b0111 - -
xa3s250e 0b0111 - -
xc3s500e 0b0110 - -
xa3s500e 0b0110 - -
xc3s1200e 0b0111 - -
xa3s1200e 0b0111 - -
xc3s1600e 0b0111 - -
xa3s1600e 0b0111 - -
xc3s50a 0b1011 - -
xc3s50an 0b1011 - -
xc3s200a 0b1011 - -
xa3s200a 0b1011 - -
xc3s200an 0b1011 - -
xc3s400a 0b1011 - -
xa3s400a 0b1011 - -
xc3s400an 0b1011 - -
xc3s700a 0b1011 - -
xa3s700a 0b1011 - -
xc3s700an 0b1011 - -
xc3s1400a 0b1011 - -
xa3s1400a 0b1011 - -
xc3s1400an 0b1011 - -
xc3sd1800a 0b1011 - -
xa3sd1800a 0b1011 - -
xc3sd3400a 0b1011 - -
xa3sd3400a 0b1011 - -