63 |
- |
- |
- |
~DCM:INV.STSADRS4
|
62 |
- |
DCM:CLKFX_MULTIPLY[2]
DCM:DFS[14]
|
DCM:DFS[30]
DCM:SEL_PL_DLY[1]
|
~DCM:INV.CTLGO
|
61 |
- |
DCM:CLKFX_MULTIPLY[1]
DCM:DFS[13]
|
DCM:DFS[29]
DCM:SEL_PL_DLY[0]
|
- |
60 |
- |
DCM:CLKFX_MULTIPLY[0]
DCM:DFS[12]
|
DCM:DFS[28]
DCM:DFS_FREQUENCY_MODE[0]
|
DCM:DFS[31]
DCM:PL_CENTERED
|
59 |
- |
DCM:CLKFX_DIVIDE[11]
DCM:DFS[11]
|
DCM:DFS[27]
DCM:DFS_FEEDBACK
|
DCM:CLKFX_MULTIPLY[3]
DCM:DFS[15]
|
58 |
- |
DCM:CLKFX_DIVIDE[10]
DCM:DFS[10]
|
DCM:DFS[26]
|
- |
57 |
- |
DCM:CLKFX_DIVIDE[9]
DCM:DFS[9]
|
DCM:DFS[25]
|
~DCM:INV.FREEZEDFS
|
56 |
- |
DCM:CLKFX_DIVIDE[8]
DCM:DFS[8]
|
DCM:DFS[24]
|
~DCM:INV.PSINCDEC
|
55 |
- |
DCM:CLKFX_DIVIDE[7]
DCM:DFS[7]
|
DCM:CLKFX_MULTIPLY[11]
DCM:DFS[23]
|
DCM:VREG_PROBE[0]
|
54 |
- |
DCM:CLKFX_DIVIDE[6]
DCM:DFS[6]
|
DCM:CLKFX_MULTIPLY[10]
DCM:DFS[22]
|
DCM:VREG_PROBE[1]
|
53 |
- |
DCM:CLKFX_DIVIDE[5]
DCM:DFS[5]
|
DCM:CLKFX_MULTIPLY[9]
DCM:DFS[21]
|
~DCM:INV.CTLSEL0
|
52 |
- |
DCM:CLKFX_DIVIDE[4]
DCM:DFS[4]
|
DCM:CLKFX_MULTIPLY[8]
DCM:DFS[20]
|
~DCM:INV.CTLOSC2
|
51 |
- |
DCM:CLKFX_DIVIDE[3]
DCM:DFS[3]
|
DCM:CLKFX_MULTIPLY[7]
DCM:DFS[19]
|
~DCM:INV.STSADRS2
|
50 |
- |
DCM:CLKFX_DIVIDE[2]
DCM:DFS[2]
|
DCM:CLKFX_MULTIPLY[6]
DCM:DFS[18]
|
- |
49 |
- |
DCM:CLKFX_DIVIDE[1]
DCM:DFS[1]
|
DCM:CLKFX_MULTIPLY[5]
DCM:DFS[17]
|
- |
48 |
- |
DCM:CLKFX_DIVIDE[0]
DCM:DFS[0]
|
DCM:CLKFX_MULTIPLY[4]
DCM:DFS[16]
|
- |
47 |
- |
DCM:DLLS[31]
|
DCM:COM[31]
DCM:NON_STOP
|
DCM:VREG_PROBE[2]
|
46 |
DCM:SPLY_IDC[1]
|
DCM:DLLS[30]
|
DCM:COIN_WINDOW[1]
DCM:COM[30]
|
DCM:VREG_PROBE[3]
|
45 |
DCM:SPLY_IDC[0]
|
DCM:DLLS[29]
DCM:PHASE_SHIFT[7]
|
DCM:COIN_WINDOW[0]
DCM:COM[29]
|
- |
44 |
DCM:EN_OSC_COARSE
|
DCM:DLLS[28]
DCM:PHASE_SHIFT[6]
|
DCM:COM[28]
DCM:VBG_PD[1]
|
~DCM:INV.CTLMODE
|
43 |
DCM:EXTENDED_FLUSH_TIME
|
DCM:DLLS[27]
DCM:PHASE_SHIFT[5]
|
DCM:COM[27]
DCM:VBG_PD[0]
|
- |
42 |
DCM:EXTENDED_HALT_TIME
|
DCM:DLLS[26]
DCM:PHASE_SHIFT[4]
|
DCM:COM[26]
DCM:VBG_SEL[2]
|
- |
41 |
DCM:EXTENDED_RUN_TIME
|
DCM:DLLS[25]
DCM:PHASE_SHIFT[3]
|
DCM:COM[25]
DCM:VBG_SEL[1]
|
- |
40 |
DCM:EN_DUMMY_OSC
|
DCM:DLLS[24]
DCM:PHASE_SHIFT[2]
|
DCM:COM[24]
DCM:VBG_SEL[0]
|
- |
39 |
DCM:ZD2_BY1
|
DCM:DLLS[23]
DCM:PHASE_SHIFT[1]
|
DCM:COM[23]
|
- |
38 |
DCM:ZD1_BY1
|
DCM:DLLS[22]
DCM:PHASE_SHIFT[0]
|
DCM:CLKFB_IOB
DCM:COM[22]
|
- |
37 |
DCM:RESET_PS_SEL
|
DCM:DLLS[21]
DCM:PHASE_SHIFT_NEGATIVE
|
DCM:CLKIN_IOB
DCM:COM[21]
|
DCM:MISC[0]
|
36 |
DCM:CFG_DLL_PS[8]
|
DCM:DLLS[20]
|
DCM:COM[20]
DCM:DESKEW_ADJUST[3]
|
DCM:ENABLE.CLK0
DCM:MISC[1]
|
35 |
DCM:CFG_DLL_PS[7]
|
DCM:DLLS[19]
DCM:PS_ENABLE
|
DCM:COM[19]
DCM:DESKEW_ADJUST[2]
|
DCM:ENABLE.CLK90
DCM:MISC[2]
|
34 |
DCM:CFG_DLL_PS[6]
|
DCM:DLLS[18]
DCM:ENABLE.CLKFB
|
DCM:COM[18]
DCM:DESKEW_ADJUST[1]
|
DCM:ENABLE.CLK180
DCM:MISC[3]
|
33 |
DCM:CFG_DLL_PS[5]
|
DCM:DLLS[17]
DCM:DLL_ENABLE
|
DCM:COM[17]
DCM:DESKEW_ADJUST[0]
|
DCM:ENABLE.CLK270
DCM:MISC[4]
|
32 |
DCM:CFG_DLL_PS[4]
|
DCM:DFS_ENABLE
DCM:DLLS[16]
|
DCM:CLKIN_DIVIDE_BY_2
DCM:COM[16]
|
DCM:ENABLE.CLK2X
DCM:MISC[5]
|
31 |
DCM:CFG_DLL_PS[3]
|
DCM:DLLS[15]
DCM:FACTORY_JF1[7]
|
DCM:COM[15]
|
DCM:ENABLE.CLK2X180
DCM:MISC[6]
|
30 |
DCM:CFG_DLL_PS[2]
|
DCM:DLLS[14]
DCM:FACTORY_JF1[6]
|
DCM:COM[14]
|
DCM:ENABLE.CLKDV
DCM:MISC[7]
|
29 |
DCM:CFG_DLL_PS[1]
|
DCM:DLLS[13]
DCM:FACTORY_JF1[5]
|
DCM:COM[13]
|
DCM:ENABLE.CLKFX180
DCM:MISC[8]
|
28 |
DCM:CFG_DLL_PS[0]
|
DCM:DLLS[12]
DCM:FACTORY_JF1[4]
|
DCM:COM[12]
|
DCM:ENABLE.CLKFX
DCM:MISC[9]
|
27 |
DCM:CFG_DLL_LP[2]
|
DCM:DLLS[11]
DCM:FACTORY_JF1[3]
|
DCM:COM[11]
|
DCM:ENABLE.CONCUR
DCM:MISC[10]
|
26 |
DCM:CFG_DLL_LP[1]
|
DCM:DLLS[10]
DCM:FACTORY_JF1[2]
|
DCM:COM[10]
|
DCM:MISC[11]
DCM:STARTUP_WAIT
|
25 |
DCM:CFG_DLL_LP[0]
|
DCM:DLLS[9]
DCM:FACTORY_JF1[1]
|
DCM:COM[9]
|
- |
24 |
DCM:SEL_HSYNC_B[0]
|
DCM:DLLS[8]
DCM:FACTORY_JF1[0]
|
DCM:COM[8]
|
~DCM:INV.STSADRS0
|
23 |
DCM:M1D1
|
DCM:DLLS[7]
DCM:FACTORY_JF2[7]
|
DCM:COM[7]
|
- |
22 |
DCM:MIS1
|
DCM:DLLS[6]
DCM:FACTORY_JF2[6]
|
DCM:COM[6]
|
- |
21 |
DCM:SEL_HSYNC_B[1]
|
DCM:DLLS[5]
DCM:FACTORY_JF2[5]
|
DCM:COM[5]
|
- |
20 |
DCM:EN_PWCTL
|
DCM:DLLS[4]
DCM:FACTORY_JF2[4]
|
DCM:COM[4]
|
~DCM:INV.RST
|
19 |
DCM:LPON_B_DFS[1]
|
DCM:DLLS[3]
DCM:FACTORY_JF2[3]
|
DCM:COM[3]
|
~DCM:INV.CTLSEL1
|
18 |
DCM:LPON_B_DFS[0]
|
DCM:DLLS[2]
DCM:FACTORY_JF2[2]
|
DCM:COM[2]
|
- |
17 |
DCM:EN_RELRST_B
|
DCM:DLLS[1]
DCM:FACTORY_JF2[1]
|
DCM:COM[1]
|
- |
16 |
DCM:EN_OLD_OSCCTL
|
DCM:DLLS[0]
DCM:FACTORY_JF2[0]
|
DCM:COM[0]
|
- |
15 |
DCM:TRIM_LP_B
|
DCM:CLKDV_COUNT_FALL_2[3]
DCM:DLLC[15]
|
DCM:DLLC[31]
|
~DCM:INV.STSADRS3
|
14 |
DCM:INVERT_ZD1_CUSTOM
|
DCM:CLKDV_COUNT_FALL_2[2]
DCM:DLLC[14]
|
DCM:DLLC[30]
|
DCM:VREG_PROBE[4]
|
13 |
- |
DCM:CLKDV_COUNT_FALL_2[1]
DCM:DLLC[13]
|
DCM:DLLC[29]
|
~DCM:INV.CTLOSC1
|
12 |
- |
DCM:CLKDV_COUNT_FALL_2[0]
DCM:DLLC[12]
|
DCM:DLLC[28]
DCM:STATUS1
|
~DCM:INV.PSEN
|
11 |
- |
DCM:CLKDV_COUNT_FALL[3]
DCM:DLLC[11]
|
DCM:DLLC[27]
DCM:STATUS7
|
~DCM:INV.FREEZEDLL
|
10 |
- |
DCM:CLKDV_COUNT_FALL[2]
DCM:DLLC[10]
|
DCM:DLLC[26]
DCM:PS_MODE[0]
|
- |
9 |
- |
DCM:CLKDV_COUNT_FALL[1]
DCM:DLLC[9]
|
DCM:DLLC[25]
DCM:PS_CENTERED
|
- |
8 |
- |
DCM:CLKDV_COUNT_FALL[0]
DCM:DLLC[8]
|
DCM:DLLC[24]
DCM:DLL_FREQUENCY_MODE[0]
|
- |
7 |
- |
DCM:CLKDV_COUNT_MAX[3]
DCM:DLLC[7]
|
DCM:CLK_FEEDBACK[0]
DCM:DLLC[23]
|
- |
6 |
- |
DCM:CLKDV_COUNT_MAX[2]
DCM:DLLC[6]
|
DCM:DLLC[22]
DCM:TEST_OSC[1]
|
- |
5 |
- |
DCM:CLKDV_COUNT_MAX[1]
DCM:DLLC[5]
|
DCM:DLLC[21]
DCM:TEST_OSC[0]
|
~DCM:INV.CTLSEL2
|
4 |
- |
DCM:CLKDV_COUNT_MAX[0]
DCM:DLLC[4]
|
DCM:CLKDV_MODE[0]
DCM:DLLC[20]
|
~DCM:INV.STSADRS1
|
3 |
- |
DCM:DLLC[3]
DCM:DUTY_CYCLE_CORRECTION[2]
|
DCM:CLKDV_PHASE_FALL[1]
DCM:DLLC[19]
|
- |
2 |
- |
DCM:DLLC[2]
DCM:DUTY_CYCLE_CORRECTION[1]
|
DCM:CLKDV_PHASE_FALL[0]
DCM:DLLC[18]
|
DCM:CLKDV_PHASE_RISE[0]
DCM:DLLC[16]
|
1 |
- |
DCM:DLLC[1]
DCM:DUTY_CYCLE_CORRECTION[0]
|
DCM:CLKDV_PHASE_RISE[1]
DCM:DLLC[17]
|
DCM:DLLC[0]
DCM:DUTY_CYCLE_CORRECTION[3]
|
0 |
- |
- |
- |
- |