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Digital Clock Managers (Spartan 3)

TODO: reverse, document

DCM.S3

spartan3 DCM.S3 bittile 0
BitFrame
0 1 2 3
63 - - - ~DCM:INV.STSADRS4
62 - DCM:CLKFX_MULTIPLY[2] DCM:DFS[14] DCM:DFS[30] DCM:SEL_PL_DLY[1] ~DCM:INV.CTLGO
61 - DCM:CLKFX_MULTIPLY[1] DCM:DFS[13] DCM:DFS[29] DCM:SEL_PL_DLY[0] -
60 - DCM:CLKFX_MULTIPLY[0] DCM:DFS[12] DCM:DFS[28] DCM:DFS_FREQUENCY_MODE[0] DCM:DFS[31] DCM:PL_CENTERED
59 - DCM:CLKFX_DIVIDE[11] DCM:DFS[11] DCM:DFS[27] DCM:DFS_FEEDBACK DCM:CLKFX_MULTIPLY[3] DCM:DFS[15]
58 - DCM:CLKFX_DIVIDE[10] DCM:DFS[10] DCM:DFS[26] -
57 - DCM:CLKFX_DIVIDE[9] DCM:DFS[9] DCM:DFS[25] ~DCM:INV.FREEZEDFS
56 - DCM:CLKFX_DIVIDE[8] DCM:DFS[8] DCM:DFS[24] ~DCM:INV.PSINCDEC
55 - DCM:CLKFX_DIVIDE[7] DCM:DFS[7] DCM:CLKFX_MULTIPLY[11] DCM:DFS[23] DCM:VREG_PROBE[0]
54 - DCM:CLKFX_DIVIDE[6] DCM:DFS[6] DCM:CLKFX_MULTIPLY[10] DCM:DFS[22] DCM:VREG_PROBE[1]
53 - DCM:CLKFX_DIVIDE[5] DCM:DFS[5] DCM:CLKFX_MULTIPLY[9] DCM:DFS[21] ~DCM:INV.CTLSEL0
52 - DCM:CLKFX_DIVIDE[4] DCM:DFS[4] DCM:CLKFX_MULTIPLY[8] DCM:DFS[20] ~DCM:INV.CTLOSC2
51 - DCM:CLKFX_DIVIDE[3] DCM:DFS[3] DCM:CLKFX_MULTIPLY[7] DCM:DFS[19] ~DCM:INV.STSADRS2
50 - DCM:CLKFX_DIVIDE[2] DCM:DFS[2] DCM:CLKFX_MULTIPLY[6] DCM:DFS[18] -
49 - DCM:CLKFX_DIVIDE[1] DCM:DFS[1] DCM:CLKFX_MULTIPLY[5] DCM:DFS[17] -
48 - DCM:CLKFX_DIVIDE[0] DCM:DFS[0] DCM:CLKFX_MULTIPLY[4] DCM:DFS[16] -
47 - DCM:DLLS[31] DCM:COM[31] DCM:NON_STOP DCM:VREG_PROBE[2]
46 DCM:SPLY_IDC[1] DCM:DLLS[30] DCM:COIN_WINDOW[1] DCM:COM[30] DCM:VREG_PROBE[3]
45 DCM:SPLY_IDC[0] DCM:DLLS[29] DCM:PHASE_SHIFT[7] DCM:COIN_WINDOW[0] DCM:COM[29] -
44 DCM:EN_OSC_COARSE DCM:DLLS[28] DCM:PHASE_SHIFT[6] DCM:COM[28] DCM:VBG_PD[1] ~DCM:INV.CTLMODE
43 DCM:EXTENDED_FLUSH_TIME DCM:DLLS[27] DCM:PHASE_SHIFT[5] DCM:COM[27] DCM:VBG_PD[0] -
42 DCM:EXTENDED_HALT_TIME DCM:DLLS[26] DCM:PHASE_SHIFT[4] DCM:COM[26] DCM:VBG_SEL[2] -
41 DCM:EXTENDED_RUN_TIME DCM:DLLS[25] DCM:PHASE_SHIFT[3] DCM:COM[25] DCM:VBG_SEL[1] -
40 DCM:EN_DUMMY_OSC DCM:DLLS[24] DCM:PHASE_SHIFT[2] DCM:COM[24] DCM:VBG_SEL[0] -
39 DCM:ZD2_BY1 DCM:DLLS[23] DCM:PHASE_SHIFT[1] DCM:COM[23] -
38 DCM:ZD1_BY1 DCM:DLLS[22] DCM:PHASE_SHIFT[0] DCM:CLKFB_IOB DCM:COM[22] -
37 DCM:RESET_PS_SEL DCM:DLLS[21] DCM:PHASE_SHIFT_NEGATIVE DCM:CLKIN_IOB DCM:COM[21] DCM:MISC[0]
36 DCM:CFG_DLL_PS[8] DCM:DLLS[20] DCM:COM[20] DCM:DESKEW_ADJUST[3] DCM:ENABLE.CLK0 DCM:MISC[1]
35 DCM:CFG_DLL_PS[7] DCM:DLLS[19] DCM:PS_ENABLE DCM:COM[19] DCM:DESKEW_ADJUST[2] DCM:ENABLE.CLK90 DCM:MISC[2]
34 DCM:CFG_DLL_PS[6] DCM:DLLS[18] DCM:ENABLE.CLKFB DCM:COM[18] DCM:DESKEW_ADJUST[1] DCM:ENABLE.CLK180 DCM:MISC[3]
33 DCM:CFG_DLL_PS[5] DCM:DLLS[17] DCM:DLL_ENABLE DCM:COM[17] DCM:DESKEW_ADJUST[0] DCM:ENABLE.CLK270 DCM:MISC[4]
32 DCM:CFG_DLL_PS[4] DCM:DFS_ENABLE DCM:DLLS[16] DCM:CLKIN_DIVIDE_BY_2 DCM:COM[16] DCM:ENABLE.CLK2X DCM:MISC[5]
31 DCM:CFG_DLL_PS[3] DCM:DLLS[15] DCM:FACTORY_JF1[7] DCM:COM[15] DCM:ENABLE.CLK2X180 DCM:MISC[6]
30 DCM:CFG_DLL_PS[2] DCM:DLLS[14] DCM:FACTORY_JF1[6] DCM:COM[14] DCM:ENABLE.CLKDV DCM:MISC[7]
29 DCM:CFG_DLL_PS[1] DCM:DLLS[13] DCM:FACTORY_JF1[5] DCM:COM[13] DCM:ENABLE.CLKFX180 DCM:MISC[8]
28 DCM:CFG_DLL_PS[0] DCM:DLLS[12] DCM:FACTORY_JF1[4] DCM:COM[12] DCM:ENABLE.CLKFX DCM:MISC[9]
27 DCM:CFG_DLL_LP[2] DCM:DLLS[11] DCM:FACTORY_JF1[3] DCM:COM[11] DCM:ENABLE.CONCUR DCM:MISC[10]
26 DCM:CFG_DLL_LP[1] DCM:DLLS[10] DCM:FACTORY_JF1[2] DCM:COM[10] DCM:MISC[11] DCM:STARTUP_WAIT
25 DCM:CFG_DLL_LP[0] DCM:DLLS[9] DCM:FACTORY_JF1[1] DCM:COM[9] -
24 DCM:SEL_HSYNC_B[0] DCM:DLLS[8] DCM:FACTORY_JF1[0] DCM:COM[8] ~DCM:INV.STSADRS0
23 DCM:M1D1 DCM:DLLS[7] DCM:FACTORY_JF2[7] DCM:COM[7] -
22 DCM:MIS1 DCM:DLLS[6] DCM:FACTORY_JF2[6] DCM:COM[6] -
21 DCM:SEL_HSYNC_B[1] DCM:DLLS[5] DCM:FACTORY_JF2[5] DCM:COM[5] -
20 DCM:EN_PWCTL DCM:DLLS[4] DCM:FACTORY_JF2[4] DCM:COM[4] ~DCM:INV.RST
19 DCM:LPON_B_DFS[1] DCM:DLLS[3] DCM:FACTORY_JF2[3] DCM:COM[3] ~DCM:INV.CTLSEL1
18 DCM:LPON_B_DFS[0] DCM:DLLS[2] DCM:FACTORY_JF2[2] DCM:COM[2] -
17 DCM:EN_RELRST_B DCM:DLLS[1] DCM:FACTORY_JF2[1] DCM:COM[1] -
16 DCM:EN_OLD_OSCCTL DCM:DLLS[0] DCM:FACTORY_JF2[0] DCM:COM[0] -
15 DCM:TRIM_LP_B DCM:CLKDV_COUNT_FALL_2[3] DCM:DLLC[15] DCM:DLLC[31] ~DCM:INV.STSADRS3
14 DCM:INVERT_ZD1_CUSTOM DCM:CLKDV_COUNT_FALL_2[2] DCM:DLLC[14] DCM:DLLC[30] DCM:VREG_PROBE[4]
13 - DCM:CLKDV_COUNT_FALL_2[1] DCM:DLLC[13] DCM:DLLC[29] ~DCM:INV.CTLOSC1
12 - DCM:CLKDV_COUNT_FALL_2[0] DCM:DLLC[12] DCM:DLLC[28] DCM:STATUS1 ~DCM:INV.PSEN
11 - DCM:CLKDV_COUNT_FALL[3] DCM:DLLC[11] DCM:DLLC[27] DCM:STATUS7 ~DCM:INV.FREEZEDLL
10 - DCM:CLKDV_COUNT_FALL[2] DCM:DLLC[10] DCM:DLLC[26] DCM:PS_MODE[0] -
9 - DCM:CLKDV_COUNT_FALL[1] DCM:DLLC[9] DCM:DLLC[25] DCM:PS_CENTERED -
8 - DCM:CLKDV_COUNT_FALL[0] DCM:DLLC[8] DCM:DLLC[24] DCM:DLL_FREQUENCY_MODE[0] -
7 - DCM:CLKDV_COUNT_MAX[3] DCM:DLLC[7] DCM:CLK_FEEDBACK[0] DCM:DLLC[23] -
6 - DCM:CLKDV_COUNT_MAX[2] DCM:DLLC[6] DCM:DLLC[22] DCM:TEST_OSC[1] -
5 - DCM:CLKDV_COUNT_MAX[1] DCM:DLLC[5] DCM:DLLC[21] DCM:TEST_OSC[0] ~DCM:INV.CTLSEL2
4 - DCM:CLKDV_COUNT_MAX[0] DCM:DLLC[4] DCM:CLKDV_MODE[0] DCM:DLLC[20] ~DCM:INV.STSADRS1
3 - DCM:DLLC[3] DCM:DUTY_CYCLE_CORRECTION[2] DCM:CLKDV_PHASE_FALL[1] DCM:DLLC[19] -
2 - DCM:DLLC[2] DCM:DUTY_CYCLE_CORRECTION[1] DCM:CLKDV_PHASE_FALL[0] DCM:DLLC[18] DCM:CLKDV_PHASE_RISE[0] DCM:DLLC[16]
1 - DCM:DLLC[1] DCM:DUTY_CYCLE_CORRECTION[0] DCM:CLKDV_PHASE_RISE[1] DCM:DLLC[17] DCM:DLLC[0] DCM:DUTY_CYCLE_CORRECTION[3]
0 - - - -
DCM:CFG_DLL_LP 0.0.27 0.0.26 0.0.25
DCM:VBG_SEL 0.2.42 0.2.41 0.2.40
non-inverted [2] [1] [0]
DCM:CFG_DLL_PS 0.0.36 0.0.35 0.0.34 0.0.33 0.0.32 0.0.31 0.0.30 0.0.29 0.0.28
non-inverted [8] [7] [6] [5] [4] [3] [2] [1] [0]
DCM:CLKDV_COUNT_FALL 0.1.11 0.1.10 0.1.9 0.1.8
DCM:CLKDV_COUNT_FALL_2 0.1.15 0.1.14 0.1.13 0.1.12
DCM:CLKDV_COUNT_MAX 0.1.7 0.1.6 0.1.5 0.1.4
DCM:DESKEW_ADJUST 0.2.36 0.2.35 0.2.34 0.2.33
DCM:DUTY_CYCLE_CORRECTION 0.3.1 0.1.3 0.1.2 0.1.1
non-inverted [3] [2] [1] [0]
DCM:CLKDV_MODE 0.2.4
HALF 0
INT 1
DCM:CLKDV_PHASE_FALL 0.2.3 0.2.2
DCM:CLKDV_PHASE_RISE 0.2.1 0.3.2
DCM:LPON_B_DFS 0.0.19 0.0.18
DCM:SEL_HSYNC_B 0.0.21 0.0.24
DCM:SPLY_IDC 0.0.46 0.0.45
DCM:VBG_PD 0.2.44 0.2.43
non-inverted [1] [0]
DCM:CLKFB_IOB 0.2.38
DCM:CLKIN_DIVIDE_BY_2 0.2.32
DCM:CLKIN_IOB 0.2.37
DCM:DFS_ENABLE 0.1.32
DCM:DFS_FEEDBACK 0.2.59
DCM:DLL_ENABLE 0.1.33
DCM:ENABLE.CLK0 0.3.36
DCM:ENABLE.CLK180 0.3.34
DCM:ENABLE.CLK270 0.3.33
DCM:ENABLE.CLK2X 0.3.32
DCM:ENABLE.CLK2X180 0.3.31
DCM:ENABLE.CLK90 0.3.35
DCM:ENABLE.CLKDV 0.3.30
DCM:ENABLE.CLKFB 0.1.34
DCM:ENABLE.CLKFX 0.3.28
DCM:ENABLE.CLKFX180 0.3.29
DCM:ENABLE.CONCUR 0.3.27
DCM:EN_DUMMY_OSC 0.0.40
DCM:EN_OLD_OSCCTL 0.0.16
DCM:EN_OSC_COARSE 0.0.44
DCM:EN_PWCTL 0.0.20
DCM:EN_RELRST_B 0.0.17
DCM:EXTENDED_FLUSH_TIME 0.0.43
DCM:EXTENDED_HALT_TIME 0.0.42
DCM:EXTENDED_RUN_TIME 0.0.41
DCM:INVERT_ZD1_CUSTOM 0.0.14
DCM:M1D1 0.0.23
DCM:MIS1 0.0.22
DCM:NON_STOP 0.2.47
DCM:PHASE_SHIFT_NEGATIVE 0.1.37
DCM:PL_CENTERED 0.3.60
DCM:PS_CENTERED 0.2.9
DCM:PS_ENABLE 0.1.35
DCM:RESET_PS_SEL 0.0.37
DCM:STARTUP_WAIT 0.3.26
DCM:STATUS1 0.2.12
DCM:STATUS7 0.2.11
DCM:TRIM_LP_B 0.0.15
DCM:ZD1_BY1 0.0.38
DCM:ZD2_BY1 0.0.39
non-inverted [0]
DCM:CLKFX_DIVIDE 0.1.59 0.1.58 0.1.57 0.1.56 0.1.55 0.1.54 0.1.53 0.1.52 0.1.51 0.1.50 0.1.49 0.1.48
DCM:CLKFX_MULTIPLY 0.2.55 0.2.54 0.2.53 0.2.52 0.2.51 0.2.50 0.2.49 0.2.48 0.3.59 0.1.62 0.1.61 0.1.60
DCM:MISC 0.3.26 0.3.27 0.3.28 0.3.29 0.3.30 0.3.31 0.3.32 0.3.33 0.3.34 0.3.35 0.3.36 0.3.37
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
DCM:CLK_FEEDBACK 0.2.7
1X 0
2X 1
DCM:COIN_WINDOW 0.2.46 0.2.45
DCM:SEL_PL_DLY 0.2.62 0.2.61
0 0 0
1 0 1
2 1 0
3 1 1
DCM:COM 0.2.47 0.2.46 0.2.45 0.2.44 0.2.43 0.2.42 0.2.41 0.2.40 0.2.39 0.2.38 0.2.37 0.2.36 0.2.35 0.2.34 0.2.33 0.2.32 0.2.31 0.2.30 0.2.29 0.2.28 0.2.27 0.2.26 0.2.25 0.2.24 0.2.23 0.2.22 0.2.21 0.2.20 0.2.19 0.2.18 0.2.17 0.2.16
DCM:DFS 0.3.60 0.2.62 0.2.61 0.2.60 0.2.59 0.2.58 0.2.57 0.2.56 0.2.55 0.2.54 0.2.53 0.2.52 0.2.51 0.2.50 0.2.49 0.2.48 0.3.59 0.1.62 0.1.61 0.1.60 0.1.59 0.1.58 0.1.57 0.1.56 0.1.55 0.1.54 0.1.53 0.1.52 0.1.51 0.1.50 0.1.49 0.1.48
DCM:DLLC 0.2.15 0.2.14 0.2.13 0.2.12 0.2.11 0.2.10 0.2.9 0.2.8 0.2.7 0.2.6 0.2.5 0.2.4 0.2.3 0.2.2 0.2.1 0.3.2 0.1.15 0.1.14 0.1.13 0.1.12 0.1.11 0.1.10 0.1.9 0.1.8 0.1.7 0.1.6 0.1.5 0.1.4 0.1.3 0.1.2 0.1.1 0.3.1
DCM:DLLS 0.1.47 0.1.46 0.1.45 0.1.44 0.1.43 0.1.42 0.1.41 0.1.40 0.1.39 0.1.38 0.1.37 0.1.36 0.1.35 0.1.34 0.1.33 0.1.32 0.1.31 0.1.30 0.1.29 0.1.28 0.1.27 0.1.26 0.1.25 0.1.24 0.1.23 0.1.22 0.1.21 0.1.20 0.1.19 0.1.18 0.1.17 0.1.16
non-inverted [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
DCM:DFS_FREQUENCY_MODE 0.2.60
DCM:DLL_FREQUENCY_MODE 0.2.8
LOW 0
HIGH 1
DCM:FACTORY_JF1 0.1.31 0.1.30 0.1.29 0.1.28 0.1.27 0.1.26 0.1.25 0.1.24
DCM:FACTORY_JF2 0.1.23 0.1.22 0.1.21 0.1.20 0.1.19 0.1.18 0.1.17 0.1.16
DCM:PHASE_SHIFT 0.1.45 0.1.44 0.1.43 0.1.42 0.1.41 0.1.40 0.1.39 0.1.38
non-inverted [7] [6] [5] [4] [3] [2] [1] [0]
DCM:INV.CTLGO 0.3.62
DCM:INV.CTLMODE 0.3.44
DCM:INV.CTLOSC1 0.3.13
DCM:INV.CTLOSC2 0.3.52
DCM:INV.CTLSEL0 0.3.53
DCM:INV.CTLSEL1 0.3.19
DCM:INV.CTLSEL2 0.3.5
DCM:INV.FREEZEDFS 0.3.57
DCM:INV.FREEZEDLL 0.3.11
DCM:INV.PSEN 0.3.12
DCM:INV.PSINCDEC 0.3.56
DCM:INV.RST 0.3.20
DCM:INV.STSADRS0 0.3.24
DCM:INV.STSADRS1 0.3.4
DCM:INV.STSADRS2 0.3.51
DCM:INV.STSADRS3 0.3.15
DCM:INV.STSADRS4 0.3.63
inverted ~[0]
DCM:PS_MODE 0.2.10
CLKFB 0
CLKIN 1
DCM:TEST_OSC 0.2.6 0.2.5
90 0 0
180 0 1
270 1 0
360 1 1
DCM:VREG_PROBE 0.3.14 0.3.46 0.3.47 0.3.54 0.3.55
non-inverted [4] [3] [2] [1] [0]

Device data

Device DCM:DESKEW_ADJUST DCM:VBG_PD DCM:VBG_SEL
[3] [2] [1] [0] [1] [0] [2] [1] [0]
xc3s50 0 1 1 1 1 0 1 0 0
xa3s50 0 1 1 1 1 0 1 0 0
xc3s200 0 1 1 1 1 0 1 0 0
xa3s200 0 1 1 1 1 0 1 0 0
xc3s400 0 1 1 1 1 0 1 0 0
xa3s400 0 1 1 1 1 0 1 0 0
xc3s1000 1 0 0 0 1 0 1 0 0
xa3s1000 1 0 0 0 1 0 1 0 0
xc3s1000l 1 0 0 0 1 0 1 0 0
xc3s1500 1 0 0 0 1 0 1 0 0
xa3s1500 1 0 0 0 1 0 1 0 0
xc3s1500l 1 0 0 0 1 0 1 0 0
xc3s2000 1 0 0 0 1 0 1 0 0
xc3s4000 1 0 0 0 1 0 1 0 0
xc3s4000l 1 0 0 0 1 0 1 0 0
xc3s5000 1 0 0 0 1 0 1 0 0
xc3s100e 0 1 1 0 - - - - -
xa3s100e 0 1 1 0 - - - - -
xc3s250e 0 1 1 1 - - - - -
xa3s250e 0 1 1 1 - - - - -
xc3s500e 0 1 1 0 - - - - -
xa3s500e 0 1 1 0 - - - - -
xc3s1200e 0 1 1 1 - - - - -
xa3s1200e 0 1 1 1 - - - - -
xc3s1600e 0 1 1 1 - - - - -
xa3s1600e 0 1 1 1 - - - - -
xc3s50a 1 0 1 1 - - - - -
xc3s50an 1 0 1 1 - - - - -
xc3s200a 1 0 1 1 - - - - -
xa3s200a 1 0 1 1 - - - - -
xc3s200an 1 0 1 1 - - - - -
xc3s400a 1 0 1 1 - - - - -
xa3s400a 1 0 1 1 - - - - -
xc3s400an 1 0 1 1 - - - - -
xc3s700a 1 0 1 1 - - - - -
xa3s700a 1 0 1 1 - - - - -
xc3s700an 1 0 1 1 - - - - -
xc3s1400a 1 0 1 1 - - - - -
xa3s1400a 1 0 1 1 - - - - -
xc3s1400an 1 0 1 1 - - - - -
xc3sd1800a 1 0 1 1 - - - - -
xa3sd1800a 1 0 1 1 - - - - -
xc3sd3400a 1 0 1 1 - - - - -
xa3sd3400a 1 0 1 1 - - - - -