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Clock row buffers

Tile HCLK_ROW

Cells: 2

Switchbox HCLK_ROW

spartan6 HCLK_ROW switchbox HCLK_ROW muxes HCLK_ROW[0]
BitsDestination
MAIN[0][32]MAIN[0][48]W.HCLK_ROW[0]
MAIN[0][0]MAIN[0][16]E.HCLK_ROW[0]
Source
00off
01W.GCLK[0]
10W.CMT_OUT[0]
spartan6 HCLK_ROW switchbox HCLK_ROW muxes HCLK_ROW[1]
BitsDestination
MAIN[1][33]MAIN[1][49]W.HCLK_ROW[1]
MAIN[1][1]MAIN[1][17]E.HCLK_ROW[1]
Source
00off
01W.GCLK[1]
10W.CMT_OUT[1]
spartan6 HCLK_ROW switchbox HCLK_ROW muxes HCLK_ROW[2]
BitsDestination
MAIN[2][34]MAIN[2][50]W.HCLK_ROW[2]
MAIN[2][2]MAIN[2][18]E.HCLK_ROW[2]
Source
00off
01W.GCLK[2]
10W.CMT_OUT[2]
spartan6 HCLK_ROW switchbox HCLK_ROW muxes HCLK_ROW[3]
BitsDestination
MAIN[0][35]MAIN[0][51]W.HCLK_ROW[3]
MAIN[0][3]MAIN[0][19]E.HCLK_ROW[3]
Source
00off
01W.GCLK[3]
10W.CMT_OUT[3]
spartan6 HCLK_ROW switchbox HCLK_ROW muxes HCLK_ROW[4]
BitsDestination
MAIN[1][36]MAIN[1][52]W.HCLK_ROW[4]
MAIN[1][4]MAIN[1][20]E.HCLK_ROW[4]
Source
00off
01W.GCLK[4]
10W.CMT_OUT[4]
spartan6 HCLK_ROW switchbox HCLK_ROW muxes HCLK_ROW[5]
BitsDestination
MAIN[2][37]MAIN[2][53]W.HCLK_ROW[5]
MAIN[2][5]MAIN[2][21]E.HCLK_ROW[5]
Source
00off
01W.GCLK[5]
10W.CMT_OUT[5]
spartan6 HCLK_ROW switchbox HCLK_ROW muxes HCLK_ROW[6]
BitsDestination
MAIN[0][38]MAIN[0][54]W.HCLK_ROW[6]
MAIN[0][6]MAIN[0][22]E.HCLK_ROW[6]
Source
00off
01W.GCLK[6]
10W.CMT_OUT[6]
spartan6 HCLK_ROW switchbox HCLK_ROW muxes HCLK_ROW[7]
BitsDestination
MAIN[1][39]MAIN[1][55]W.HCLK_ROW[7]
MAIN[1][7]MAIN[1][23]E.HCLK_ROW[7]
Source
00off
01W.GCLK[7]
10W.CMT_OUT[7]
spartan6 HCLK_ROW switchbox HCLK_ROW muxes HCLK_ROW[8]
BitsDestination
MAIN[2][40]MAIN[2][56]W.HCLK_ROW[8]
MAIN[2][8]MAIN[2][24]E.HCLK_ROW[8]
Source
00off
01W.GCLK[8]
10W.CMT_OUT[8]
spartan6 HCLK_ROW switchbox HCLK_ROW muxes HCLK_ROW[9]
BitsDestination
MAIN[0][41]MAIN[0][57]W.HCLK_ROW[9]
MAIN[0][9]MAIN[0][25]E.HCLK_ROW[9]
Source
00off
01W.GCLK[9]
10W.CMT_OUT[9]
spartan6 HCLK_ROW switchbox HCLK_ROW muxes HCLK_ROW[10]
BitsDestination
MAIN[1][42]MAIN[1][58]W.HCLK_ROW[10]
MAIN[1][10]MAIN[1][26]E.HCLK_ROW[10]
Source
00off
01W.GCLK[10]
10W.CMT_OUT[10]
spartan6 HCLK_ROW switchbox HCLK_ROW muxes HCLK_ROW[11]
BitsDestination
MAIN[2][43]MAIN[2][59]W.HCLK_ROW[11]
MAIN[2][11]MAIN[2][27]E.HCLK_ROW[11]
Source
00off
01W.GCLK[11]
10W.CMT_OUT[11]
spartan6 HCLK_ROW switchbox HCLK_ROW muxes HCLK_ROW[12]
BitsDestination
MAIN[0][44]MAIN[0][60]W.HCLK_ROW[12]
MAIN[0][12]MAIN[0][28]E.HCLK_ROW[12]
Source
00off
01W.GCLK[12]
10W.CMT_OUT[12]
spartan6 HCLK_ROW switchbox HCLK_ROW muxes HCLK_ROW[13]
BitsDestination
MAIN[1][45]MAIN[1][61]W.HCLK_ROW[13]
MAIN[1][13]MAIN[1][29]E.HCLK_ROW[13]
Source
00off
01W.GCLK[13]
10W.CMT_OUT[13]
spartan6 HCLK_ROW switchbox HCLK_ROW muxes HCLK_ROW[14]
BitsDestination
MAIN[2][46]MAIN[2][62]W.HCLK_ROW[14]
MAIN[2][14]MAIN[2][30]E.HCLK_ROW[14]
Source
00off
01W.GCLK[14]
10W.CMT_OUT[14]
spartan6 HCLK_ROW switchbox HCLK_ROW muxes HCLK_ROW[15]
BitsDestination
MAIN[0][47]MAIN[0][63]W.HCLK_ROW[15]
MAIN[0][15]MAIN[0][31]E.HCLK_ROW[15]
Source
00off
01W.GCLK[15]
10W.CMT_OUT[15]

Bitstream

spartan6 HCLK_ROW rect MAIN
BitFrame
F0 F1 F2 F3
B63 HCLK_ROW: mux W.HCLK_ROW[15] bit 0 - - -
B62 - - HCLK_ROW: mux W.HCLK_ROW[14] bit 0 -
B61 - HCLK_ROW: mux W.HCLK_ROW[13] bit 0 - -
B60 HCLK_ROW: mux W.HCLK_ROW[12] bit 0 - - -
B59 - - HCLK_ROW: mux W.HCLK_ROW[11] bit 0 -
B58 - HCLK_ROW: mux W.HCLK_ROW[10] bit 0 - -
B57 HCLK_ROW: mux W.HCLK_ROW[9] bit 0 - - -
B56 - - HCLK_ROW: mux W.HCLK_ROW[8] bit 0 -
B55 - HCLK_ROW: mux W.HCLK_ROW[7] bit 0 - -
B54 HCLK_ROW: mux W.HCLK_ROW[6] bit 0 - - -
B53 - - HCLK_ROW: mux W.HCLK_ROW[5] bit 0 -
B52 - HCLK_ROW: mux W.HCLK_ROW[4] bit 0 - -
B51 HCLK_ROW: mux W.HCLK_ROW[3] bit 0 - - -
B50 - - HCLK_ROW: mux W.HCLK_ROW[2] bit 0 -
B49 - HCLK_ROW: mux W.HCLK_ROW[1] bit 0 - -
B48 HCLK_ROW: mux W.HCLK_ROW[0] bit 0 - - -
B47 HCLK_ROW: mux W.HCLK_ROW[15] bit 1 - - -
B46 - - HCLK_ROW: mux W.HCLK_ROW[14] bit 1 -
B45 - HCLK_ROW: mux W.HCLK_ROW[13] bit 1 - -
B44 HCLK_ROW: mux W.HCLK_ROW[12] bit 1 - - -
B43 - - HCLK_ROW: mux W.HCLK_ROW[11] bit 1 -
B42 - HCLK_ROW: mux W.HCLK_ROW[10] bit 1 - -
B41 HCLK_ROW: mux W.HCLK_ROW[9] bit 1 - - -
B40 - - HCLK_ROW: mux W.HCLK_ROW[8] bit 1 -
B39 - HCLK_ROW: mux W.HCLK_ROW[7] bit 1 - -
B38 HCLK_ROW: mux W.HCLK_ROW[6] bit 1 - - -
B37 - - HCLK_ROW: mux W.HCLK_ROW[5] bit 1 -
B36 - HCLK_ROW: mux W.HCLK_ROW[4] bit 1 - -
B35 HCLK_ROW: mux W.HCLK_ROW[3] bit 1 - - -
B34 - - HCLK_ROW: mux W.HCLK_ROW[2] bit 1 -
B33 - HCLK_ROW: mux W.HCLK_ROW[1] bit 1 - -
B32 HCLK_ROW: mux W.HCLK_ROW[0] bit 1 - - -
B31 HCLK_ROW: mux E.HCLK_ROW[15] bit 0 - - -
B30 - - HCLK_ROW: mux E.HCLK_ROW[14] bit 0 -
B29 - HCLK_ROW: mux E.HCLK_ROW[13] bit 0 - -
B28 HCLK_ROW: mux E.HCLK_ROW[12] bit 0 - - -
B27 - - HCLK_ROW: mux E.HCLK_ROW[11] bit 0 -
B26 - HCLK_ROW: mux E.HCLK_ROW[10] bit 0 - -
B25 HCLK_ROW: mux E.HCLK_ROW[9] bit 0 - - -
B24 - - HCLK_ROW: mux E.HCLK_ROW[8] bit 0 -
B23 - HCLK_ROW: mux E.HCLK_ROW[7] bit 0 - -
B22 HCLK_ROW: mux E.HCLK_ROW[6] bit 0 - - -
B21 - - HCLK_ROW: mux E.HCLK_ROW[5] bit 0 -
B20 - HCLK_ROW: mux E.HCLK_ROW[4] bit 0 - -
B19 HCLK_ROW: mux E.HCLK_ROW[3] bit 0 - - -
B18 - - HCLK_ROW: mux E.HCLK_ROW[2] bit 0 -
B17 - HCLK_ROW: mux E.HCLK_ROW[1] bit 0 - -
B16 HCLK_ROW: mux E.HCLK_ROW[0] bit 0 - - -
B15 HCLK_ROW: mux E.HCLK_ROW[15] bit 1 - - -
B14 - - HCLK_ROW: mux E.HCLK_ROW[14] bit 1 -
B13 - HCLK_ROW: mux E.HCLK_ROW[13] bit 1 - -
B12 HCLK_ROW: mux E.HCLK_ROW[12] bit 1 - - -
B11 - - HCLK_ROW: mux E.HCLK_ROW[11] bit 1 -
B10 - HCLK_ROW: mux E.HCLK_ROW[10] bit 1 - -
B9 HCLK_ROW: mux E.HCLK_ROW[9] bit 1 - - -
B8 - - HCLK_ROW: mux E.HCLK_ROW[8] bit 1 -
B7 - HCLK_ROW: mux E.HCLK_ROW[7] bit 1 - -
B6 HCLK_ROW: mux E.HCLK_ROW[6] bit 1 - - -
B5 - - HCLK_ROW: mux E.HCLK_ROW[5] bit 1 -
B4 - HCLK_ROW: mux E.HCLK_ROW[4] bit 1 - -
B3 HCLK_ROW: mux E.HCLK_ROW[3] bit 1 - - -
B2 - - HCLK_ROW: mux E.HCLK_ROW[2] bit 1 -
B1 - HCLK_ROW: mux E.HCLK_ROW[1] bit 1 - -
B0 HCLK_ROW: mux E.HCLK_ROW[0] bit 1 - - -