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Clock spine buffers

Tile DCM_BUFPLL_BUF_S

Cells: 0 IRIs: 0

Bel DCM_BUFPLL_BUF_S

spartan6 DCM_BUFPLL_BUF_S bel DCM_BUFPLL_BUF_S
PinDirectionWires

Bitstream

spartan6 DCM_BUFPLL_BUF_S bittile 0
BitFrame
0 1 2 3
7 - - - DCM_BUFPLL_BUF_S:CLKC_CLKOUT1
6 - - - DCM_BUFPLL_BUF_S:CLKC_CLKOUT0
5 - - - DCM_BUFPLL_BUF_S:PLL1_CLKOUT1
4 - - - DCM_BUFPLL_BUF_S:PLL1_CLKOUT0
3 - - - -
2 - - - -
1 - - - DCM_BUFPLL_BUF_S:PLL0_CLKOUT1
0 - - - DCM_BUFPLL_BUF_S:PLL0_CLKOUT0
DCM_BUFPLL_BUF_S:CLKC_CLKOUT0 0.3.6
DCM_BUFPLL_BUF_S:CLKC_CLKOUT1 0.3.7
DCM_BUFPLL_BUF_S:PLL0_CLKOUT0 0.3.0
DCM_BUFPLL_BUF_S:PLL0_CLKOUT1 0.3.1
DCM_BUFPLL_BUF_S:PLL1_CLKOUT0 0.3.4
DCM_BUFPLL_BUF_S:PLL1_CLKOUT1 0.3.5
non-inverted [0]

Tile DCM_BUFPLL_BUF_S_MID

Cells: 0 IRIs: 0

Bel DCM_BUFPLL_BUF_S_MID

spartan6 DCM_BUFPLL_BUF_S_MID bel DCM_BUFPLL_BUF_S_MID
PinDirectionWires

Bitstream

spartan6 DCM_BUFPLL_BUF_S_MID bittile 0
BitFrame
0 1 2 3
7 - - - DCM_BUFPLL_BUF_S_MID:CLKC_CLKOUT1
6 - - - DCM_BUFPLL_BUF_S_MID:CLKC_CLKOUT0
5 - - - DCM_BUFPLL_BUF_S_MID:PLL1_CLKOUT1
4 - - - DCM_BUFPLL_BUF_S_MID:PLL1_CLKOUT0
3 - - - -
2 - - - -
1 - - - DCM_BUFPLL_BUF_S_MID:PLL0_CLKOUT1
0 - - - DCM_BUFPLL_BUF_S_MID:PLL0_CLKOUT0
DCM_BUFPLL_BUF_S_MID:CLKC_CLKOUT0 0.3.6
DCM_BUFPLL_BUF_S_MID:CLKC_CLKOUT1 0.3.7
DCM_BUFPLL_BUF_S_MID:PLL0_CLKOUT0 0.3.0
DCM_BUFPLL_BUF_S_MID:PLL0_CLKOUT1 0.3.1
DCM_BUFPLL_BUF_S_MID:PLL1_CLKOUT0 0.3.4
DCM_BUFPLL_BUF_S_MID:PLL1_CLKOUT1 0.3.5
non-inverted [0]

Tile DCM_BUFPLL_BUF_N

Cells: 0 IRIs: 0

Bel DCM_BUFPLL_BUF_N

spartan6 DCM_BUFPLL_BUF_N bel DCM_BUFPLL_BUF_N
PinDirectionWires

Bitstream

spartan6 DCM_BUFPLL_BUF_N bittile 0
BitFrame
0 1 2 3
7 - - - DCM_BUFPLL_BUF_N:CLKC_CLKOUT1
6 - - - DCM_BUFPLL_BUF_N:CLKC_CLKOUT0
5 - - - DCM_BUFPLL_BUF_N:PLL1_CLKOUT1
4 - - - DCM_BUFPLL_BUF_N:PLL1_CLKOUT0
3 - - - -
2 - - - -
1 - - - DCM_BUFPLL_BUF_N:PLL0_CLKOUT1
0 - - - DCM_BUFPLL_BUF_N:PLL0_CLKOUT0
DCM_BUFPLL_BUF_N:CLKC_CLKOUT0 0.3.6
DCM_BUFPLL_BUF_N:CLKC_CLKOUT1 0.3.7
DCM_BUFPLL_BUF_N:PLL0_CLKOUT0 0.3.0
DCM_BUFPLL_BUF_N:PLL0_CLKOUT1 0.3.1
DCM_BUFPLL_BUF_N:PLL1_CLKOUT0 0.3.4
DCM_BUFPLL_BUF_N:PLL1_CLKOUT1 0.3.5
non-inverted [0]

Tile DCM_BUFPLL_BUF_N_MID

Cells: 0 IRIs: 0

Bel DCM_BUFPLL_BUF_N_MID

spartan6 DCM_BUFPLL_BUF_N_MID bel DCM_BUFPLL_BUF_N_MID
PinDirectionWires

Bitstream

spartan6 DCM_BUFPLL_BUF_N_MID bittile 0
BitFrame
0 1 2 3
7 - - - DCM_BUFPLL_BUF_N_MID:CLKC_CLKOUT1
6 - - - DCM_BUFPLL_BUF_N_MID:CLKC_CLKOUT0
5 - - - DCM_BUFPLL_BUF_N_MID:PLL1_CLKOUT1
4 - - - DCM_BUFPLL_BUF_N_MID:PLL1_CLKOUT0
3 - - - -
2 - - - -
1 - - - DCM_BUFPLL_BUF_N_MID:PLL0_CLKOUT1
0 - - - DCM_BUFPLL_BUF_N_MID:PLL0_CLKOUT0
DCM_BUFPLL_BUF_N_MID:CLKC_CLKOUT0 0.3.6
DCM_BUFPLL_BUF_N_MID:CLKC_CLKOUT1 0.3.7
DCM_BUFPLL_BUF_N_MID:PLL0_CLKOUT0 0.3.0
DCM_BUFPLL_BUF_N_MID:PLL0_CLKOUT1 0.3.1
DCM_BUFPLL_BUF_N_MID:PLL1_CLKOUT0 0.3.4
DCM_BUFPLL_BUF_N_MID:PLL1_CLKOUT1 0.3.5
non-inverted [0]

Tile PLL_BUFPLL_OUT0

Cells: 0 IRIs: 0

Bel PLL_BUFPLL

spartan6 PLL_BUFPLL_OUT0 bel PLL_BUFPLL
PinDirectionWires

Bitstream

spartan6 PLL_BUFPLL_OUT0 bittile 0
BitFrame
0 1 2 3
7 - - - PLL_BUFPLL:PLL1_CLKOUT1
6 - - - PLL_BUFPLL:PLL1_CLKOUT0
5 - - - PLL_BUFPLL:CLKC_CLKOUT1
4 - - - PLL_BUFPLL:CLKC_CLKOUT0
3 - - - PLL_BUFPLL:PLL0_CLKOUT1_D
2 - - - PLL_BUFPLL:PLL0_CLKOUT1_U
1 - - - PLL_BUFPLL:PLL0_CLKOUT0_D
0 - - - PLL_BUFPLL:PLL0_CLKOUT0_U
PLL_BUFPLL:CLKC_CLKOUT0 0.3.4
PLL_BUFPLL:CLKC_CLKOUT1 0.3.5
PLL_BUFPLL:PLL0_CLKOUT0_D 0.3.1
PLL_BUFPLL:PLL0_CLKOUT0_U 0.3.0
PLL_BUFPLL:PLL0_CLKOUT1_D 0.3.3
PLL_BUFPLL:PLL0_CLKOUT1_U 0.3.2
PLL_BUFPLL:PLL1_CLKOUT0 0.3.6
PLL_BUFPLL:PLL1_CLKOUT1 0.3.7
non-inverted [0]

Tile PLL_BUFPLL_OUT1

Cells: 0 IRIs: 0

Bel PLL_BUFPLL

spartan6 PLL_BUFPLL_OUT1 bel PLL_BUFPLL
PinDirectionWires

Bitstream

spartan6 PLL_BUFPLL_OUT1 bittile 0
BitFrame
0 1 2 3
7 - - - PLL_BUFPLL:PLL1_CLKOUT1_D
6 - - - PLL_BUFPLL:PLL1_CLKOUT1_U
5 - - - PLL_BUFPLL:CLKC_CLKOUT1
4 - - - PLL_BUFPLL:CLKC_CLKOUT0
3 - - - PLL_BUFPLL:PLL1_CLKOUT0_D
2 - - - PLL_BUFPLL:PLL1_CLKOUT0_U
1 - - - PLL_BUFPLL:PLL0_CLKOUT1
0 - - - PLL_BUFPLL:PLL0_CLKOUT0
PLL_BUFPLL:CLKC_CLKOUT0 0.3.4
PLL_BUFPLL:CLKC_CLKOUT1 0.3.5
PLL_BUFPLL:PLL0_CLKOUT0 0.3.0
PLL_BUFPLL:PLL0_CLKOUT1 0.3.1
PLL_BUFPLL:PLL1_CLKOUT0_D 0.3.3
PLL_BUFPLL:PLL1_CLKOUT0_U 0.3.2
PLL_BUFPLL:PLL1_CLKOUT1_D 0.3.7
PLL_BUFPLL:PLL1_CLKOUT1_U 0.3.6
non-inverted [0]

Tile PLL_BUFPLL_B

Cells: 0 IRIs: 0

Bitstream

spartan6 PLL_BUFPLL_B bittile 0
BitFrame
0 1 2 3
7 - - - PLL_BUFPLL:PLL1_CLKOUT1
6 - - - PLL_BUFPLL:PLL1_CLKOUT0
5 - - - PLL_BUFPLL:CLKC_CLKOUT1
4 - - - PLL_BUFPLL:CLKC_CLKOUT0
3 - - - PLL_BUFPLL:PLL0_CLKOUT1
2 - - - -
1 - - - PLL_BUFPLL:PLL0_CLKOUT0
0 - - - -
PLL_BUFPLL:CLKC_CLKOUT0 0.3.4
PLL_BUFPLL:CLKC_CLKOUT1 0.3.5
PLL_BUFPLL:PLL0_CLKOUT0 0.3.1
PLL_BUFPLL:PLL0_CLKOUT1 0.3.3
PLL_BUFPLL:PLL1_CLKOUT0 0.3.6
PLL_BUFPLL:PLL1_CLKOUT1 0.3.7
non-inverted [0]

Tile PLL_BUFPLL_T

Cells: 0 IRIs: 0

Bitstream

spartan6 PLL_BUFPLL_T bittile 0
BitFrame
0 1 2 3
7 - - - PLL_BUFPLL:PLL1_CLKOUT1
6 - - - PLL_BUFPLL:PLL1_CLKOUT0
5 - - - PLL_BUFPLL:CLKC_CLKOUT1
4 - - - PLL_BUFPLL:CLKC_CLKOUT0
3 - - - -
2 - - - PLL_BUFPLL:PLL0_CLKOUT1
1 - - - -
0 - - - PLL_BUFPLL:PLL0_CLKOUT0
PLL_BUFPLL:CLKC_CLKOUT0 0.3.4
PLL_BUFPLL:CLKC_CLKOUT1 0.3.5
PLL_BUFPLL:PLL0_CLKOUT0 0.3.0
PLL_BUFPLL:PLL0_CLKOUT1 0.3.2
PLL_BUFPLL:PLL1_CLKOUT0 0.3.6
PLL_BUFPLL:PLL1_CLKOUT1 0.3.7
non-inverted [0]

Tile HCLK_H_MIDBUF

Cells: 0 IRIs: 0

Bel HCLK_H_MIDBUF

spartan6 HCLK_H_MIDBUF bel HCLK_H_MIDBUF
PinDirectionWires

Tile HCLK_V_MIDBUF

Cells: 0 IRIs: 0

Bel HCLK_V_MIDBUF

spartan6 HCLK_V_MIDBUF bel HCLK_V_MIDBUF
PinDirectionWires

Tile CKPIN_H_MIDBUF

Cells: 0 IRIs: 0

Bel CKPIN_H_MIDBUF

spartan6 CKPIN_H_MIDBUF bel CKPIN_H_MIDBUF
PinDirectionWires

Tile CKPIN_V_MIDBUF

Cells: 0 IRIs: 0

Bel CKPIN_V_MIDBUF

spartan6 CKPIN_V_MIDBUF bel CKPIN_V_MIDBUF
PinDirectionWires