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Input/Output

Tile IOI_WE

Cells: 1

Switchbox IOI_INT

spartan6 IOI_WE switchbox IOI_INT programmable inverters
DestinationSourceBit
IOI_IOCLK_OPTINV[0]IOI_IOCLK[0]MAIN[23][38]
IOI_IOCLK_OPTINV[1]IOI_IOCLK[1]MAIN[24][38]
IOI_IOCLK_OPTINV[2]IOI_IOCLK[2]MAIN[23][39]
IOI_IOCLK_OPTINV[3]IOI_IOCLK[3]MAIN[23][25]
IOI_IOCLK_OPTINV[4]IOI_IOCLK[4]MAIN[24][25]
IOI_IOCLK_OPTINV[5]IOI_IOCLK[5]MAIN[23][24]
spartan6 IOI_WE switchbox IOI_INT muxes IOI_IOCLK[0]
BitsDestination
MAIN[23][36]MAIN[23][32]MAIN[23][33]MAIN[23][35]MAIN[23][37]IOI_IOCLK[0]
Source
00000off
00001IMUX_GFAN[1]
00010IMUX_CLK[1]
00100IOCLK[0]
01000IOCLK[2]
10000PLLCLK[0]
spartan6 IOI_WE switchbox IOI_INT muxes IOI_IOCLK[1]
BitsDestination
MAIN[24][36]MAIN[24][32]MAIN[24][33]MAIN[24][37]MAIN[24][35]IOI_IOCLK[1]
Source
00000off
00001IMUX_GFAN[1]
00010IMUX_CLK[1]
00100IOCLK[1]
01000IOCLK[3]
10000PLLCLK[1]
spartan6 IOI_WE switchbox IOI_INT muxes IOI_IOCLK[2]
BitsDestination
MAIN[24][40]MAIN[24][39]IOI_IOCLK[2]
Source
00off
01PLLCLK[0]
10PLLCLK[1]
spartan6 IOI_WE switchbox IOI_INT muxes IOI_IOCLK[3]
BitsDestination
MAIN[23][27]MAIN[23][31]MAIN[23][30]MAIN[23][28]MAIN[23][26]IOI_IOCLK[3]
Source
00000off
00001IMUX_GFAN[0]
00010IMUX_CLK[0]
00100IOCLK[0]
01000IOCLK[2]
10000PLLCLK[0]
spartan6 IOI_WE switchbox IOI_INT muxes IOI_IOCLK[4]
BitsDestination
MAIN[24][27]MAIN[24][31]MAIN[24][30]MAIN[24][26]MAIN[24][28]IOI_IOCLK[4]
Source
00000off
00001IMUX_GFAN[0]
00010IMUX_CLK[0]
00100IOCLK[1]
01000IOCLK[3]
10000PLLCLK[1]
spartan6 IOI_WE switchbox IOI_INT muxes IOI_IOCLK[5]
BitsDestination
MAIN[24][23]MAIN[24][24]IOI_IOCLK[5]
Source
00off
01PLLCLK[0]
10PLLCLK[1]
spartan6 IOI_WE switchbox IOI_INT muxes IOI_IOCE[0]
BitsDestination
MAIN[23][53]MAIN[23][52]MAIN[23][50]IOI_IOCE[0]
Source
000off
001IOCE[0]
010IOCE[2]
100PLLCE[0]
spartan6 IOI_WE switchbox IOI_INT muxes IOI_IOCE[1]
BitsDestination
MAIN[24][53]MAIN[24][52]MAIN[24][51]IOI_IOCE[1]
Source
000off
001IOCE[1]
010IOCE[3]
100PLLCE[1]
spartan6 IOI_WE switchbox IOI_INT muxes IOI_IOCE[2]
BitsDestination
MAIN[23][10]MAIN[23][11]MAIN[23][13]IOI_IOCE[2]
Source
000off
001IOCE[0]
010IOCE[2]
100PLLCE[0]
spartan6 IOI_WE switchbox IOI_INT muxes IOI_IOCE[3]
BitsDestination
MAIN[24][10]MAIN[24][11]MAIN[24][12]IOI_IOCE[3]
Source
000off
001IOCE[1]
010IOCE[3]
100PLLCE[1]
spartan6 IOI_WE switchbox IOI_INT muxes IOI_ICLK[0]
BitsDestination
MAIN[23][48]MAIN[23][49]MAIN[24][46]MAIN[24][47]IOI_ICLK[0]
Source
0000off
0001IOI_IOCLK[0]
0010IOI_IOCLK[1]
0100IOI_IOCLK[2]
1000OUT_DDR_IOCLK[0]
spartan6 IOI_WE switchbox IOI_INT muxes IOI_ICLK[1]
BitsDestination
MAIN[23][15]MAIN[23][14]MAIN[24][17]MAIN[24][16]IOI_ICLK[1]
Source
0000off
0001IOI_IOCLK[3]
0010IOI_IOCLK[4]
0100IOI_IOCLK[5]
1000OUT_DDR_IOCLK[1]
spartan6 IOI_WE switchbox IOI_INT muxes IOI_OCLK[0]
BitsDestination
MAIN[24][49]MAIN[24][50]MAIN[24][45]MAIN[24][48]IOI_OCLK[0]
Source
0000off
0001IOI_IOCLK[0]
0010IOI_IOCLK[1]
0100IOI_IOCLK[2]
1000OUT_DDR_IOCLK[0]
spartan6 IOI_WE switchbox IOI_INT muxes IOI_OCLK[1]
BitsDestination
MAIN[24][14]MAIN[24][13]MAIN[24][18]MAIN[24][15]IOI_OCLK[1]
Source
0000off
0001IOI_IOCLK[3]
0010IOI_IOCLK[4]
0100IOI_IOCLK[5]
1000OUT_DDR_IOCLK[1]
spartan6 IOI_WE switchbox IOI_INT muxes IMUX_ILOGIC_IOCE[0]
BitsDestination
MAIN[23][60]MAIN[23][62]MAIN[23][61]IMUX_ILOGIC_IOCE[0]
Source
000off
001IOI_IOCE[0]
010IOI_IOCE[1]
100OUT_DDR_IOCE[0]
spartan6 IOI_WE switchbox IOI_INT muxes IMUX_ILOGIC_IOCE[1]
BitsDestination
MAIN[23][3]MAIN[23][1]MAIN[23][2]IMUX_ILOGIC_IOCE[1]
Source
000off
001IOI_IOCE[2]
010IOI_IOCE[3]
100OUT_DDR_IOCE[1]
spartan6 IOI_WE switchbox IOI_INT muxes IMUX_OLOGIC_IOCE[0]
BitsDestination
MAIN[24][59]MAIN[24][61]MAIN[24][60]IMUX_OLOGIC_IOCE[0]
Source
000off
001IOI_IOCE[0]
010IOI_IOCE[1]
100OUT_DDR_IOCE[0]
spartan6 IOI_WE switchbox IOI_INT muxes IMUX_OLOGIC_IOCE[1]
BitsDestination
MAIN[24][4]MAIN[24][2]MAIN[24][3]IMUX_OLOGIC_IOCE[1]
Source
000off
001IOI_IOCE[2]
010IOI_IOCE[3]
100OUT_DDR_IOCE[1]
spartan6 IOI_WE switchbox IOI_INT muxes IMUX_ILOGIC_CLK[0]
BitsDestination
MAIN[29][41]MAIN[29][40]IMUX_ILOGIC_CLK[0]
Source
00off
01IOI_ICLK[0]
10IOI_ICLK[1]
spartan6 IOI_WE switchbox IOI_INT muxes IMUX_ILOGIC_CLK[1]
BitsDestination
MAIN[29][43]MAIN[29][42]IMUX_ILOGIC_CLK[1]
Source
00off
01IOI_ICLK[0]
10IOI_ICLK[1]
spartan6 IOI_WE switchbox IOI_INT muxes IMUX_OLOGIC_CLK[0]
BitsDestination
MAIN[29][37]MAIN[29][36]IMUX_OLOGIC_CLK[0]
Source
00off
01IOI_OCLK[0]
10IOI_OCLK[1]
spartan6 IOI_WE switchbox IOI_INT muxes IMUX_OLOGIC_CLK[1]
BitsDestination
MAIN[29][39]MAIN[29][38]IMUX_OLOGIC_CLK[1]
Source
00off
01IOI_OCLK[0]
10IOI_OCLK[1]
spartan6 IOI_WE switchbox IOI_INT muxes IMUX_IODELAY_IOCLK[0]
BitsDestination
MAIN[29][3]IMUX_IODELAY_IOCLK[0]
Source
0IMUX_ILOGIC_CLK[0]
1IMUX_OLOGIC_CLK[0]
spartan6 IOI_WE switchbox IOI_INT muxes IMUX_IODELAY_IOCLK[1]
BitsDestination
MAIN[29][1]IMUX_IODELAY_IOCLK[1]
Source
0IMUX_ILOGIC_CLK[1]
1IMUX_OLOGIC_CLK[1]

Bels IOI_DDR

spartan6 IOI_WE bel IOI_DDR pins
PinDirectionIOI_DDR[0]IOI_DDR[1]
CLK0inIOI_IOCLK[0]IOI_IOCLK[3]
CLK1inIOI_IOCLK[1]IOI_IOCLK[4]
CLKoutOUT_DDR_IOCLK[0]OUT_DDR_IOCLK[1]
IOCEoutOUT_DDR_IOCE[0]OUT_DDR_IOCE[1]
spartan6 IOI_WE bel IOI_DDR attribute bits
AttributeIOI_DDR[0]IOI_DDR[1]
ENABLE bit 0MAIN[23][40]MAIN[23][22]
ENABLE bit 1MAIN[23][41]MAIN[23][23]
ALIGNMENT[enum: IOI_DDR_ALIGNMENT][enum: IOI_DDR_ALIGNMENT]
spartan6 IOI_WE enum IOI_DDR_ALIGNMENT
IOI_DDR[0].ALIGNMENTMAIN[23][54]MAIN[23][55]
IOI_DDR[1].ALIGNMENTMAIN[23][9]MAIN[23][8]
NONE00
CLK001
CLK110

Bels ILOGIC

spartan6 IOI_WE bel ILOGIC pins
PinDirectionILOGIC[0]ILOGIC[1]
CLKinIMUX_ILOGIC_CLK[0]IMUX_ILOGIC_CLK[1]
IOCEinIMUX_ILOGIC_IOCE[0]IMUX_ILOGIC_IOCE[1]
CLKDIVinIMUX_CLK[1]IMUX_CLK[0]
SRinIMUX_LOGICIN[20]IMUX_LOGICIN[36]
REVinIMUX_LOGICIN[59]IMUX_LOGICIN[37]
CE0inIMUX_LOGICIN[62]IMUX_LOGICIN[38]
BITSLIPinIMUX_LOGICIN[19]IMUX_LOGICIN[57]
FABRICOUToutOUT_BEL[7]OUT_BEL[0]
Q1outOUT_BEL[8]OUT_BEL[1]
Q2outOUT_BEL[9]OUT_BEL[2]
Q3outOUT_BEL[10]OUT_BEL[3]
Q4outOUT_BEL[11]OUT_BEL[4]
INCDECout-OUT_BEL[5]
VALIDout-OUT_BEL[6]
DFBoutOUT_CLKPAD_DFB[0]OUT_CLKPAD_DFB[1]
CFB0outOUT_CLKPAD_CFB0[0]OUT_CLKPAD_CFB0[1]
CFB1outOUT_CLKPAD_CFB1[0]OUT_CLKPAD_CFB1[1]
spartan6 IOI_WE bel ILOGIC attribute bits
AttributeILOGIC[0]ILOGIC[1]
ENABLEMAIN[29][32]MAIN[29][35]
DDRMAIN[22][40]MAIN[22][60]
IOCE_ENABLEMAIN[29][26]MAIN[29][24]
FFI_INIT bit 0MAIN[22][38]MAIN[22][41]
FFI_SRVAL bit 0MAIN[22][37]MAIN[22][55]
FFI_LATCHMAIN[22][33]MAIN[22][63]
FFI_SR_ENABLEMAIN[22][39]MAIN[22][42]
FFI_SR_SYNC!MAIN[22][32]!MAIN[22][62]
FFI_REV_ENABLEMAIN[22][35]MAIN[22][59]
FFI_CE_ENABLE!MAIN[22][31]!MAIN[22][57]
FFI_DELAY_ENABLE!MAIN[28][55]!MAIN[28][8]
I_DELAY_ENABLE!MAIN[23][57]!MAIN[23][6]
MUX_TSBYPASS[enum: ILOGIC_MUX_TSBYPASS][enum: ILOGIC_MUX_TSBYPASS]
MUX_D[enum: ILOGIC_MUX_D]-
MUX_SR[enum: ILOGIC_MUX_SR][enum: ILOGIC_MUX_SR]
DATA_WIDTH_START[enum: ILOGIC_DATA_WIDTH][enum: ILOGIC_DATA_WIDTH]
DATA_WIDTH_RELOAD[enum: ILOGIC_DATA_WIDTH][enum: ILOGIC_DATA_WIDTH]
BITSLIP_ENABLEMAIN[29][22]MAIN[29][17]
CASCADE_ENABLEMAIN[22][34]MAIN[29][16]
MUX_Q1[enum: ILOGIC_MUX_Q][enum: ILOGIC_MUX_Q]
MUX_Q2[enum: ILOGIC_MUX_Q][enum: ILOGIC_MUX_Q]
MUX_Q3[enum: ILOGIC_MUX_Q][enum: ILOGIC_MUX_Q]
MUX_Q4[enum: ILOGIC_MUX_Q][enum: ILOGIC_MUX_Q]
ROW1_CLK_ENABLEMAIN[22][45]MAIN[22][50]
ROW2_CLK_ENABLEMAIN[22][44]MAIN[22][51]
ROW3_CLK_ENABLEMAIN[22][46]MAIN[22][49]
ROW4_CLK_ENABLEMAIN[22][47]MAIN[22][48]
spartan6 IOI_WE enum ILOGIC_MUX_TSBYPASS
ILOGIC[0].MUX_TSBYPASSMAIN[23][58]
ILOGIC[1].MUX_TSBYPASSMAIN[23][5]
GND0
T1
spartan6 IOI_WE enum ILOGIC_MUX_D
ILOGIC[0].MUX_DMAIN[24][43]MAIN[24][42]
IOB_I00
OTHER_IOB_I11
spartan6 IOI_WE enum ILOGIC_MUX_SR
ILOGIC[0].MUX_SRMAIN[22][36]
ILOGIC[1].MUX_SRMAIN[22][58]
INT1
OLOGIC_SR0
spartan6 IOI_WE enum ILOGIC_DATA_WIDTH
ILOGIC[0].DATA_WIDTH_STARTMAIN[29][23]MAIN[29][21]
_200
_301
_410
spartan6 IOI_WE enum ILOGIC_DATA_WIDTH
ILOGIC[1].DATA_WIDTH_STARTMAIN[29][18]MAIN[29][19]MAIN[29][20]
_2000
_3001
_4010
_5011
_6100
_7101
_8110
spartan6 IOI_WE enum ILOGIC_DATA_WIDTH
ILOGIC[0].DATA_WIDTH_RELOADMAIN[27][39]MAIN[27][38]
_111
_210
_301
_400
spartan6 IOI_WE enum ILOGIC_DATA_WIDTH
ILOGIC[1].DATA_WIDTH_RELOADMAIN[27][37]MAIN[27][36]MAIN[27][18]
_1111
_2110
_3101
_4100
_5011
_6010
_7001
_8000
spartan6 IOI_WE enum ILOGIC_MUX_Q
ILOGIC[0].MUX_Q1MAIN[27][46]MAIN[27][47]
ILOGIC[1].MUX_Q1MAIN[27][49]MAIN[27][48]
ILOGIC[0].MUX_Q2MAIN[27][45]MAIN[27][44]
ILOGIC[1].MUX_Q2MAIN[27][50]MAIN[27][51]
ILOGIC[0].MUX_Q3MAIN[27][42]MAIN[27][43]
ILOGIC[1].MUX_Q3MAIN[27][53]MAIN[27][52]
ILOGIC[0].MUX_Q4MAIN[27][41]MAIN[27][40]
ILOGIC[1].MUX_Q4MAIN[27][54]MAIN[27][55]
NETWORKING01
NETWORKING_PIPELINED10
RETIMED11
SHIFT_REGISTER00

Bels OLOGIC

spartan6 IOI_WE bel OLOGIC pins
PinDirectionOLOGIC[0]OLOGIC[1]
CLKinIMUX_OLOGIC_CLK[0]IMUX_OLOGIC_CLK[1]
IOCEinIMUX_OLOGIC_IOCE[0]IMUX_OLOGIC_IOCE[1]
CLKDIVinIMUX_CLK[1]IMUX_CLK[0]
SRinIMUX_SR[1]IMUX_SR[0]
REVinIMUX_LOGICIN[14]IMUX_LOGICIN[29]
OCEinIMUX_LOGICIN[39]IMUX_LOGICIN[30]
TCEinIMUX_LOGICIN[9]IMUX_LOGICIN[23]
D1inIMUX_LOGICIN[15]IMUX_LOGICIN[31]
D2inIMUX_LOGICIN[16]IMUX_LOGICIN[32]
D3inIMUX_LOGICIN[17]IMUX_LOGICIN[44]
D4inIMUX_LOGICIN[48]IMUX_LOGICIN[34]
T1inIMUX_LOGICIN[45]IMUX_LOGICIN[24]
T2inIMUX_LOGICIN[42]IMUX_LOGICIN[25]
T3inIMUX_LOGICIN[12]IMUX_LOGICIN[26]
T4inIMUX_LOGICIN[54]IMUX_LOGICIN[27]
TRAINinIMUX_LOGICIN[28]IMUX_LOGICIN[8]
spartan6 IOI_WE bel OLOGIC attribute bits
AttributeOLOGIC[0]OLOGIC[1]
ENABLEMAIN[29][28]MAIN[29][31]
IOCE_ENABLEMAIN[29][27]MAIN[29][25]
DDR_OPPOSITE_EDGEMAIN[27][14]MAIN[27][29]
FFO_INIT bit 0MAIN[22][9]MAIN[22][25]
FFO_SRVAL bit 0MAIN[22][8]MAIN[22][24]
FFO_LATCHMAIN[22][13]MAIN[22][29]
FFO_RANK1_BYPASSMAIN[27][15]MAIN[27][34]
FFO_RANK1_CLK_ENABLEMAIN[27][9]MAIN[27][25]
FFO_RANK2_CLK_ENABLEMAIN[27][8]MAIN[27][24]
FFO_SR_SYNC!MAIN[22][10]!MAIN[22][26]
FFO_SR_ENABLEMAIN[22][12]MAIN[22][28]
FFO_REV_ENABLEMAIN[22][11]MAIN[22][27]
FFO_CE_ENABLEMAIN[27][11]MAIN[27][27]
FFO_CE_OR_DDRMAIN[27][10]MAIN[27][26]
FFT_INIT bit 0MAIN[22][6]MAIN[22][22]
FFT_SRVAL bit 0MAIN[22][7]MAIN[22][23]
FFT_LATCHMAIN[22][2]MAIN[22][18]
FFT_RANK1_BYPASSMAIN[27][1]MAIN[27][19]
FFT_RANK1_CLK_ENABLEMAIN[27][6]MAIN[27][22]
FFT_RANK2_CLK_ENABLEMAIN[27][7]MAIN[27][23]
FFT_SR_SYNC!MAIN[22][5]!MAIN[22][21]
FFT_SR_ENABLEMAIN[22][3]MAIN[22][19]
FFT_REV_ENABLEMAIN[22][4]MAIN[22][20]
FFT_CE_ENABLEMAIN[27][4]MAIN[27][20]
FFT_CE_OR_DDRMAIN[27][5]MAIN[27][21]
MUX_IN_O[enum: OLOGIC_MUX_IN][enum: OLOGIC_MUX_IN]
MUX_IN_T[enum: OLOGIC_MUX_IN][enum: OLOGIC_MUX_IN]
MUX_OCE[enum: OLOGIC_MUX_OCE][enum: OLOGIC_MUX_OCE]
MUX_SR[enum: OLOGIC_MUX_SR][enum: OLOGIC_MUX_SR]
MUX_REV[enum: OLOGIC_MUX_REV][enum: OLOGIC_MUX_REV]
MUX_TRAIN[enum: OLOGIC_MUX_TRAIN][enum: OLOGIC_MUX_TRAIN]
MUX_O[enum: OLOGIC_MUX_O][enum: OLOGIC_MUX_O]
MUX_T[enum: OLOGIC_MUX_T][enum: OLOGIC_MUX_T]
CASCADE_ENABLEMAIN[29][46]MAIN[22][30]
OUTPUT_MODE[enum: OLOGIC_OUTPUT_MODE]-
TRAIN_PATTERN bit 0MAIN[27][16]MAIN[27][33]
TRAIN_PATTERN bit 1MAIN[27][17]MAIN[27][32]
TRAIN_PATTERN bit 2MAIN[27][13]MAIN[27][31]
TRAIN_PATTERN bit 3MAIN[27][3]MAIN[27][30]
MISR_ENABLE_CLKMAIN[29][13]MAIN[29][14]
MISR_ENABLE_DATAMAIN[29][12]MAIN[29][15]
MISR_RESETMAIN[29][10]MAIN[29][11]
spartan6 IOI_WE enum OLOGIC_MUX_IN
OLOGIC[0].MUX_IN_OMAIN[27][12]
OLOGIC[1].MUX_IN_OMAIN[27][35]
OLOGIC[0].MUX_IN_TMAIN[27][2]
OLOGIC[1].MUX_IN_TMAIN[27][28]
INT0
MCB1
spartan6 IOI_WE enum OLOGIC_MUX_OCE
OLOGIC[0].MUX_OCEMAIN[28][43]
OLOGIC[1].MUX_OCEMAIN[28][20]
INT0
PCI_CE1
spartan6 IOI_WE enum OLOGIC_MUX_SR
OLOGIC[0].MUX_SRMAIN[22][1]
OLOGIC[1].MUX_SRMAIN[22][15]
GND0
INT1
spartan6 IOI_WE enum OLOGIC_MUX_REV
OLOGIC[0].MUX_REVMAIN[22][0]
OLOGIC[1].MUX_REVMAIN[22][14]
GND0
INT1
spartan6 IOI_WE enum OLOGIC_MUX_TRAIN
OLOGIC[0].MUX_TRAINMAIN[29][47]MAIN[29][45]
OLOGIC[1].MUX_TRAINMAIN[29][48]MAIN[29][44]
GND00
INT01
MCB10
spartan6 IOI_WE enum OLOGIC_MUX_O
OLOGIC[0].MUX_OMAIN[28][49]
OLOGIC[1].MUX_OMAIN[28][14]
D11
FFO0
spartan6 IOI_WE enum OLOGIC_MUX_T
OLOGIC[0].MUX_TMAIN[28][41]
OLOGIC[1].MUX_TMAIN[28][22]
T11
FFT0
spartan6 IOI_WE enum OLOGIC_OUTPUT_MODE
OLOGIC[0].OUTPUT_MODEMAIN[27][0]
SINGLE_ENDED0
DIFFERENTIAL1

Bels IODELAY

spartan6 IOI_WE bel IODELAY pins
PinDirectionIODELAY[0]IODELAY[1]
IOCLKinIMUX_IODELAY_IOCLK[0]IMUX_IODELAY_IOCLK[1]
RSTinIMUX_LOGICIN[41]IMUX_LOGICIN[55]
CALinIMUX_LOGICIN[3]IMUX_LOGICIN[2]
CEinIMUX_LOGICIN[5]IMUX_LOGICIN[47]
CINinIMUX_LOGICIN[52]IMUX_LOGICIN[1]
CLKinIMUX_CLK[1]IMUX_CLK[0]
INCinIMUX_LOGICIN[7]IMUX_LOGICIN[58]
BUSYoutOUT_BEL[15]OUT_BEL[14]
LOADoutOUT_BEL[17]OUT_BEL[16]
RCLKoutOUT_BEL[13]OUT_BEL[12]
DQSOUTPout-OUT_CLKPAD_DQSP
DQSOUTNout-OUT_CLKPAD_DQSN
spartan6 IOI_WE bel IODELAY attribute bits
AttributeIODELAY[0]IODELAY[1]
MODE[enum: IODELAY_MODE][enum: IODELAY_MODE]
COUNTER_WRAPAROUND[enum: IOLOGIC_COUNTER_WRAPAROUND][enum: IOLOGIC_COUNTER_WRAPAROUND]
DELAYCHAIN_OSCMAIN[24][56]MAIN[24][7]
DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB bit 0MAIN[26][44]MAIN[26][9]
DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB bit 1MAIN[26][54]MAIN[26][19]
DELAY_SRC[enum: IODELAY_DELAY_SRC][enum: IODELAY_DELAY_SRC]
DIFF_PHASE_DETECTORMAIN[26][55]MAIN[26][20]
CIN_ENABLE bit 0MAIN[24][41]MAIN[24][5]
CIN_ENABLE bit 1MAIN[24][57]MAIN[24][6]
CIN_ENABLE bit 2MAIN[24][58]MAIN[24][22]
ODATAIN_ENABLEMAIN[23][59]MAIN[23][4]
IDELAY_FIXEDMAIN[22][52]MAIN[22][16]
IDELAY_FROM_HALF_MAXMAIN[28][44]MAIN[28][19]
IDELAY_MODE[enum: IODELAY_IDELAY_MODE][enum: IODELAY_IDELAY_MODE]
IODELAY_CHANGE[enum: IODELAY_CHANGE][enum: IODELAY_CHANGE]
LUMPED_DELAYMAIN[28][52]MAIN[28][11]
LUMPED_DELAY_SELECTMAIN[28][54]MAIN[28][9]
PLUS1MAIN[28][45]-
TEST_GLITCH_FILTERMAIN[23][45]MAIN[23][18]
TEST_PCOUNTERMAIN[26][49]MAIN[26][0]
TEST_NCOUNTERMAIN[26][51]MAIN[26][12]
EVENT_SEL bit 0-MAIN[28][18]
EVENT_SEL bit 1-MAIN[28][16]
CAL_DELAY_MAX bit 0MAIN[28][63]MAIN[28][0]
CAL_DELAY_MAX bit 1MAIN[28][62]MAIN[28][1]
CAL_DELAY_MAX bit 2MAIN[28][61]MAIN[28][2]
CAL_DELAY_MAX bit 3MAIN[28][60]MAIN[28][3]
CAL_DELAY_MAX bit 4MAIN[28][59]MAIN[28][4]
CAL_DELAY_MAX bit 5MAIN[28][58]MAIN[28][5]
CAL_DELAY_MAX bit 6MAIN[28][57]MAIN[28][6]
CAL_DELAY_MAX bit 7MAIN[28][56]MAIN[28][7]
IDELAY_VALUE_P bit 0MAIN[25][46]MAIN[25][17]
IDELAY_VALUE_P bit 1MAIN[25][44]MAIN[25][19]
IDELAY_VALUE_P bit 2MAIN[25][42]MAIN[25][21]
IDELAY_VALUE_P bit 3MAIN[25][40]MAIN[25][23]
IDELAY_VALUE_P bit 4MAIN[25][39]MAIN[25][24]
IDELAY_VALUE_P bit 5MAIN[25][37]MAIN[25][26]
IDELAY_VALUE_P bit 6MAIN[25][35]MAIN[25][28]
IDELAY_VALUE_P bit 7MAIN[25][33]MAIN[25][30]
IDELAY_VALUE_N bit 0MAIN[25][49]MAIN[25][14]
IDELAY_VALUE_N bit 1MAIN[25][51]MAIN[25][12]
IDELAY_VALUE_N bit 2MAIN[25][53]MAIN[25][10]
IDELAY_VALUE_N bit 3MAIN[25][55]MAIN[25][8]
IDELAY_VALUE_N bit 4MAIN[25][56]MAIN[25][7]
IDELAY_VALUE_N bit 5MAIN[25][58]MAIN[25][5]
IDELAY_VALUE_N bit 6MAIN[25][60]MAIN[25][3]
IDELAY_VALUE_N bit 7MAIN[25][62]MAIN[25][1]
ODELAY_VALUE_P bit 0MAIN[25][47]MAIN[25][16]
ODELAY_VALUE_P bit 1MAIN[25][45]MAIN[25][18]
ODELAY_VALUE_P bit 2MAIN[25][43]MAIN[25][20]
ODELAY_VALUE_P bit 3MAIN[25][41]MAIN[25][22]
ODELAY_VALUE_P bit 4MAIN[25][38]MAIN[25][25]
ODELAY_VALUE_P bit 5MAIN[25][36]MAIN[25][27]
ODELAY_VALUE_P bit 6MAIN[25][34]MAIN[25][29]
ODELAY_VALUE_P bit 7MAIN[25][32]MAIN[25][31]
ODELAY_VALUE_N bit 0MAIN[25][48]MAIN[25][15]
ODELAY_VALUE_N bit 1MAIN[25][50]MAIN[25][13]
ODELAY_VALUE_N bit 2MAIN[25][52]MAIN[25][11]
ODELAY_VALUE_N bit 3MAIN[25][54]MAIN[25][9]
ODELAY_VALUE_N bit 4MAIN[25][57]MAIN[25][6]
ODELAY_VALUE_N bit 5MAIN[25][59]MAIN[25][4]
ODELAY_VALUE_N bit 6MAIN[25][61]MAIN[25][2]
ODELAY_VALUE_N bit 7MAIN[25][63]MAIN[25][0]
DRP_ADDR bit 0MAIN[28][39]MAIN[28][24]
DRP_ADDR bit 1MAIN[28][38]MAIN[28][25]
DRP_ADDR bit 2MAIN[28][37]MAIN[28][26]
DRP_ADDR bit 3MAIN[28][36]MAIN[28][27]
DRP_ADDR bit 4MAIN[28][32]MAIN[28][31]
DRP06 bit 0MAIN[28][45]MAIN[28][18]
DRP06 bit 1MAIN[28][47]MAIN[28][16]
DRP06 bit 2MAIN[28][50]MAIN[28][13]
DRP06 bit 3MAIN[28][53]MAIN[28][10]
DRP06 bit 4MAIN[28][55]MAIN[28][8]
DRP06 bit 5MAIN[28][49]MAIN[28][14]
DRP06 bit 6MAIN[28][41]MAIN[28][22]
DRP06 bit 7MAIN[28][43]MAIN[28][20]
DRP07 bit 0MAIN[28][44]MAIN[28][19]
DRP07 bit 1MAIN[28][46]MAIN[28][17]
DRP07 bit 2MAIN[28][51]MAIN[28][12]
DRP07 bit 3MAIN[28][52]MAIN[28][11]
DRP07 bit 4MAIN[28][54]MAIN[28][9]
DRP07 bit 5MAIN[28][48]MAIN[28][15]
DRP07 bit 6MAIN[28][40]MAIN[28][23]
DRP07 bit 7MAIN[28][42]MAIN[28][21]
spartan6 IOI_WE enum IODELAY_MODE
IODELAY[0].MODEMAIN[24][55]MAIN[23][56]MAIN[23][44]MAIN[23][42]
IODELAY[1].MODEMAIN[24][8]MAIN[23][7]MAIN[23][21]MAIN[23][19]
IODRP20000
IODELAY20011
IODRP2_MCB1100
spartan6 IOI_WE enum IOLOGIC_COUNTER_WRAPAROUND
IODELAY[0].COUNTER_WRAPAROUNDMAIN[28][46]
IODELAY[1].COUNTER_WRAPAROUNDMAIN[28][17]
WRAPAROUND0
STAY_AT_LIMIT1
spartan6 IOI_WE enum IODELAY_DELAY_SRC
IODELAY[0].DELAY_SRCMAIN[28][53]MAIN[28][50]
IODELAY[1].DELAY_SRCMAIN[28][10]MAIN[28][13]
IO00
ODATAIN01
IDATAIN11
spartan6 IOI_WE enum IODELAY_IDELAY_MODE
IODELAY[0].IDELAY_MODEMAIN[24][54]MAIN[24][44]
IODELAY[1].IDELAY_MODEMAIN[24][19]MAIN[24][9]
NORMAL00
PCI11
spartan6 IOI_WE enum IODELAY_CHANGE
IODELAY[0].IODELAY_CHANGEMAIN[28][51]
IODELAY[1].IODELAY_CHANGEMAIN[28][12]
CHANGE_ON_CLOCK0
CHANGE_ON_DATA1

Bels MISC_IOI

spartan6 IOI_WE bel MISC_IOI pins
PinDirectionMISC_IOI
spartan6 IOI_WE bel MISC_IOI attribute bits
AttributeMISC_IOI
MEM_PLL_DIV_ENMAIN[26][57]
MEM_PLL_POL_SEL[enum: MCB_MEM_PLL_POL_SEL]
DRP_ENABLEMAIN[26][28]
DRP_FROM_MCBMAIN[26][46]
ENFFSCAN_DRP bit 0MAIN[26][43]
ENFFSCAN_DRP bit 1MAIN[29][9]
DRP_MCB_ADDRESS bit 0MAIN[26][24]
DRP_MCB_ADDRESS bit 1MAIN[26][26]
DRP_MCB_ADDRESS bit 2MAIN[26][39]
DRP_MCB_ADDRESS bit 3MAIN[26][47]
DIFF_PHASE_DETECTORMAIN[27][63]
spartan6 IOI_WE enum MCB_MEM_PLL_POL_SEL
MISC_IOI.MEM_PLL_POL_SELMAIN[26][56]
INVERTED0
NOTINVERTED1

Bel wires

spartan6 IOI_WE bel wires
WirePins
IMUX_CLK[0]ILOGIC[1].CLKDIV, OLOGIC[1].CLKDIV, IODELAY[1].CLK
IMUX_CLK[1]ILOGIC[0].CLKDIV, OLOGIC[0].CLKDIV, IODELAY[0].CLK
IMUX_SR[0]OLOGIC[1].SR
IMUX_SR[1]OLOGIC[0].SR
IMUX_LOGICIN[1]IODELAY[1].CIN
IMUX_LOGICIN[2]IODELAY[1].CAL
IMUX_LOGICIN[3]IODELAY[0].CAL
IMUX_LOGICIN[5]IODELAY[0].CE
IMUX_LOGICIN[7]IODELAY[0].INC
IMUX_LOGICIN[8]OLOGIC[1].TRAIN
IMUX_LOGICIN[9]OLOGIC[0].TCE
IMUX_LOGICIN[12]OLOGIC[0].T3
IMUX_LOGICIN[14]OLOGIC[0].REV
IMUX_LOGICIN[15]OLOGIC[0].D1
IMUX_LOGICIN[16]OLOGIC[0].D2
IMUX_LOGICIN[17]OLOGIC[0].D3
IMUX_LOGICIN[19]ILOGIC[0].BITSLIP
IMUX_LOGICIN[20]ILOGIC[0].SR
IMUX_LOGICIN[23]OLOGIC[1].TCE
IMUX_LOGICIN[24]OLOGIC[1].T1
IMUX_LOGICIN[25]OLOGIC[1].T2
IMUX_LOGICIN[26]OLOGIC[1].T3
IMUX_LOGICIN[27]OLOGIC[1].T4
IMUX_LOGICIN[28]OLOGIC[0].TRAIN
IMUX_LOGICIN[29]OLOGIC[1].REV
IMUX_LOGICIN[30]OLOGIC[1].OCE
IMUX_LOGICIN[31]OLOGIC[1].D1
IMUX_LOGICIN[32]OLOGIC[1].D2
IMUX_LOGICIN[34]OLOGIC[1].D4
IMUX_LOGICIN[36]ILOGIC[1].SR
IMUX_LOGICIN[37]ILOGIC[1].REV
IMUX_LOGICIN[38]ILOGIC[1].CE0
IMUX_LOGICIN[39]OLOGIC[0].OCE
IMUX_LOGICIN[41]IODELAY[0].RST
IMUX_LOGICIN[42]OLOGIC[0].T2
IMUX_LOGICIN[44]OLOGIC[1].D3
IMUX_LOGICIN[45]OLOGIC[0].T1
IMUX_LOGICIN[47]IODELAY[1].CE
IMUX_LOGICIN[48]OLOGIC[0].D4
IMUX_LOGICIN[52]IODELAY[0].CIN
IMUX_LOGICIN[54]OLOGIC[0].T4
IMUX_LOGICIN[55]IODELAY[1].RST
IMUX_LOGICIN[57]ILOGIC[1].BITSLIP
IMUX_LOGICIN[58]IODELAY[1].INC
IMUX_LOGICIN[59]ILOGIC[0].REV
IMUX_LOGICIN[62]ILOGIC[0].CE0
OUT_BEL[0]ILOGIC[1].FABRICOUT
OUT_BEL[1]ILOGIC[1].Q1
OUT_BEL[2]ILOGIC[1].Q2
OUT_BEL[3]ILOGIC[1].Q3
OUT_BEL[4]ILOGIC[1].Q4
OUT_BEL[5]ILOGIC[1].INCDEC
OUT_BEL[6]ILOGIC[1].VALID
OUT_BEL[7]ILOGIC[0].FABRICOUT
OUT_BEL[8]ILOGIC[0].Q1
OUT_BEL[9]ILOGIC[0].Q2
OUT_BEL[10]ILOGIC[0].Q3
OUT_BEL[11]ILOGIC[0].Q4
OUT_BEL[12]IODELAY[1].RCLK
OUT_BEL[13]IODELAY[0].RCLK
OUT_BEL[14]IODELAY[1].BUSY
OUT_BEL[15]IODELAY[0].BUSY
OUT_BEL[16]IODELAY[1].LOAD
OUT_BEL[17]IODELAY[0].LOAD
OUT_CLKPAD_DFB[0]ILOGIC[0].DFB
OUT_CLKPAD_DFB[1]ILOGIC[1].DFB
OUT_CLKPAD_CFB0[0]ILOGIC[0].CFB0
OUT_CLKPAD_CFB0[1]ILOGIC[1].CFB0
OUT_CLKPAD_CFB1[0]ILOGIC[0].CFB1
OUT_CLKPAD_CFB1[1]ILOGIC[1].CFB1
OUT_CLKPAD_DQSPIODELAY[1].DQSOUTP
OUT_CLKPAD_DQSNIODELAY[1].DQSOUTN
IOI_IOCLK[0]IOI_DDR[0].CLK0
IOI_IOCLK[1]IOI_DDR[0].CLK1
IOI_IOCLK[3]IOI_DDR[1].CLK0
IOI_IOCLK[4]IOI_DDR[1].CLK1
OUT_DDR_IOCLK[0]IOI_DDR[0].CLK
OUT_DDR_IOCLK[1]IOI_DDR[1].CLK
OUT_DDR_IOCE[0]IOI_DDR[0].IOCE
OUT_DDR_IOCE[1]IOI_DDR[1].IOCE
IMUX_ILOGIC_CLK[0]ILOGIC[0].CLK
IMUX_ILOGIC_CLK[1]ILOGIC[1].CLK
IMUX_OLOGIC_CLK[0]OLOGIC[0].CLK
IMUX_OLOGIC_CLK[1]OLOGIC[1].CLK
IMUX_IODELAY_IOCLK[0]IODELAY[0].IOCLK
IMUX_IODELAY_IOCLK[1]IODELAY[1].IOCLK
IMUX_ILOGIC_IOCE[0]ILOGIC[0].IOCE
IMUX_ILOGIC_IOCE[1]ILOGIC[1].IOCE
IMUX_OLOGIC_IOCE[0]OLOGIC[0].IOCE
IMUX_OLOGIC_IOCE[1]OLOGIC[1].IOCE

Bitstream

spartan6 IOI_WE rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: FFI_LATCH - - IODELAY[0]: ODELAY_VALUE_N bit 7 - MISC_IOI: DIFF_PHASE_DETECTOR IODELAY[0]: CAL_DELAY_MAX bit 0 -
B62 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! FFI_SR_SYNC IOI_INT: mux IMUX_ILOGIC_IOCE[0] bit 1 - IODELAY[0]: IDELAY_VALUE_N bit 7 - - IODELAY[0]: CAL_DELAY_MAX bit 1 -
B61 - - - - - - - - - - - - - - - - - - - - - - - IOI_INT: mux IMUX_ILOGIC_IOCE[0] bit 0 IOI_INT: mux IMUX_OLOGIC_IOCE[0] bit 1 IODELAY[0]: ODELAY_VALUE_N bit 6 - - IODELAY[0]: CAL_DELAY_MAX bit 2 -
B60 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: DDR IOI_INT: mux IMUX_ILOGIC_IOCE[0] bit 2 IOI_INT: mux IMUX_OLOGIC_IOCE[0] bit 0 IODELAY[0]: IDELAY_VALUE_N bit 6 - - IODELAY[0]: CAL_DELAY_MAX bit 3 -
B59 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: FFI_REV_ENABLE IODELAY[0]: ODATAIN_ENABLE IOI_INT: mux IMUX_OLOGIC_IOCE[0] bit 2 IODELAY[0]: ODELAY_VALUE_N bit 5 - - IODELAY[0]: CAL_DELAY_MAX bit 4 -
B58 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: MUX_SR bit 0 ILOGIC[0]: MUX_TSBYPASS bit 0 IODELAY[0]: CIN_ENABLE bit 2 IODELAY[0]: IDELAY_VALUE_N bit 5 - - IODELAY[0]: CAL_DELAY_MAX bit 5 -
B57 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! FFI_CE_ENABLE ILOGIC[0]: ! I_DELAY_ENABLE IODELAY[0]: CIN_ENABLE bit 1 IODELAY[0]: ODELAY_VALUE_N bit 4 MISC_IOI: MEM_PLL_DIV_EN - IODELAY[0]: CAL_DELAY_MAX bit 6 -
B56 - - - - - - - - - - - - - - - - - - - - - - - IODELAY[0]: MODE bit 2 IODELAY[0]: DELAYCHAIN_OSC IODELAY[0]: IDELAY_VALUE_N bit 4 MISC_IOI: MEM_PLL_POL_SEL bit 0 - IODELAY[0]: CAL_DELAY_MAX bit 7 -
B55 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: FFI_SRVAL bit 0 IOI_DDR[0]: ALIGNMENT bit 0 IODELAY[0]: MODE bit 3 IODELAY[0]: IDELAY_VALUE_N bit 3 IODELAY[0]: DIFF_PHASE_DETECTOR ILOGIC[1]: MUX_Q4 bit 0 ILOGIC[0]: ! FFI_DELAY_ENABLE IODELAY[0]: DRP06 bit 4 -
B54 - - - - - - - - - - - - - - - - - - - - - - - IOI_DDR[0]: ALIGNMENT bit 1 IODELAY[0]: IDELAY_MODE bit 1 IODELAY[0]: ODELAY_VALUE_N bit 3 IODELAY[0]: DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB bit 1 ILOGIC[1]: MUX_Q4 bit 1 IODELAY[0]: LUMPED_DELAY_SELECT IODELAY[0]: DRP07 bit 4 -
B53 - - - - - - - - - - - - - - - - - - - - - - - IOI_INT: mux IOI_IOCE[0] bit 2 IOI_INT: mux IOI_IOCE[1] bit 2 IODELAY[0]: IDELAY_VALUE_N bit 2 - ILOGIC[1]: MUX_Q3 bit 1 IODELAY[0]: DRP06 bit 3 IODELAY[0]: DELAY_SRC bit 1 -
B52 - - - - - - - - - - - - - - - - - - - - - - IODELAY[0]: IDELAY_FIXED IOI_INT: mux IOI_IOCE[0] bit 1 IOI_INT: mux IOI_IOCE[1] bit 1 IODELAY[0]: ODELAY_VALUE_N bit 2 - ILOGIC[1]: MUX_Q3 bit 0 IODELAY[0]: LUMPED_DELAY IODELAY[0]: DRP07 bit 3 -
B51 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ROW2_CLK_ENABLE - IOI_INT: mux IOI_IOCE[1] bit 0 IODELAY[0]: IDELAY_VALUE_N bit 1 IODELAY[0]: TEST_NCOUNTER ILOGIC[1]: MUX_Q2 bit 0 IODELAY[0]: DRP07 bit 2 IODELAY[0]: IODELAY_CHANGE bit 0 -
B50 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ROW1_CLK_ENABLE IOI_INT: mux IOI_IOCE[0] bit 0 IOI_INT: mux IOI_OCLK[0] bit 2 IODELAY[0]: ODELAY_VALUE_N bit 1 - ILOGIC[1]: MUX_Q2 bit 1 IODELAY[0]: DRP06 bit 2 IODELAY[0]: DELAY_SRC bit 0 -
B49 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ROW3_CLK_ENABLE IOI_INT: mux IOI_ICLK[0] bit 2 IOI_INT: mux IOI_OCLK[0] bit 3 IODELAY[0]: IDELAY_VALUE_N bit 0 IODELAY[0]: TEST_PCOUNTER ILOGIC[1]: MUX_Q1 bit 1 OLOGIC[0]: MUX_O bit 0 IODELAY[0]: DRP06 bit 5 -
B48 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ROW4_CLK_ENABLE IOI_INT: mux IOI_ICLK[0] bit 3 IOI_INT: mux IOI_OCLK[0] bit 0 IODELAY[0]: ODELAY_VALUE_N bit 0 - ILOGIC[1]: MUX_Q1 bit 0 IODELAY[0]: DRP07 bit 5 OLOGIC[1]: MUX_TRAIN bit 1
B47 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ROW4_CLK_ENABLE - IOI_INT: mux IOI_ICLK[0] bit 0 IODELAY[0]: ODELAY_VALUE_P bit 0 MISC_IOI: DRP_MCB_ADDRESS bit 3 ILOGIC[0]: MUX_Q1 bit 0 IODELAY[0]: DRP06 bit 1 OLOGIC[0]: MUX_TRAIN bit 1
B46 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ROW3_CLK_ENABLE - IOI_INT: mux IOI_ICLK[0] bit 1 IODELAY[0]: IDELAY_VALUE_P bit 0 MISC_IOI: DRP_FROM_MCB ILOGIC[0]: MUX_Q1 bit 1 IODELAY[0]: DRP07 bit 1 IODELAY[0]: COUNTER_WRAPAROUND bit 0 OLOGIC[0]: CASCADE_ENABLE
B45 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ROW1_CLK_ENABLE IODELAY[0]: TEST_GLITCH_FILTER IOI_INT: mux IOI_OCLK[0] bit 1 IODELAY[0]: ODELAY_VALUE_P bit 1 - ILOGIC[0]: MUX_Q2 bit 1 IODELAY[0]: PLUS1 IODELAY[0]: DRP06 bit 0 OLOGIC[0]: MUX_TRAIN bit 0
B44 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ROW2_CLK_ENABLE IODELAY[0]: MODE bit 1 IODELAY[0]: IDELAY_MODE bit 0 IODELAY[0]: IDELAY_VALUE_P bit 1 IODELAY[0]: DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB bit 0 ILOGIC[0]: MUX_Q2 bit 0 IODELAY[0]: IDELAY_FROM_HALF_MAX IODELAY[0]: DRP07 bit 0 OLOGIC[1]: MUX_TRAIN bit 0
B43 - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: MUX_D bit 1 IODELAY[0]: ODELAY_VALUE_P bit 2 MISC_IOI: ENFFSCAN_DRP bit 0 ILOGIC[0]: MUX_Q3 bit 0 OLOGIC[0]: MUX_OCE bit 0 IODELAY[0]: DRP06 bit 7 IOI_INT: mux IMUX_ILOGIC_CLK[1] bit 1
B42 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: FFI_SR_ENABLE IODELAY[0]: MODE bit 0 ILOGIC[0]: MUX_D bit 0 IODELAY[0]: IDELAY_VALUE_P bit 2 - ILOGIC[0]: MUX_Q3 bit 1 IODELAY[0]: DRP07 bit 7 IOI_INT: mux IMUX_ILOGIC_CLK[1] bit 0
B41 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: FFI_INIT bit 0 IOI_DDR[0]: ENABLE bit 1 IODELAY[0]: CIN_ENABLE bit 0 IODELAY[0]: ODELAY_VALUE_P bit 3 - ILOGIC[0]: MUX_Q4 bit 1 OLOGIC[0]: MUX_T bit 0 IODELAY[0]: DRP06 bit 6 IOI_INT: mux IMUX_ILOGIC_CLK[0] bit 1
B40 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: DDR IOI_DDR[0]: ENABLE bit 0 IOI_INT: mux IOI_IOCLK[2] bit 1 IODELAY[0]: IDELAY_VALUE_P bit 3 - ILOGIC[0]: MUX_Q4 bit 0 IODELAY[0]: DRP07 bit 6 IOI_INT: mux IMUX_ILOGIC_CLK[0] bit 0
B39 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: FFI_SR_ENABLE IOI_INT: invert IOI_IOCLK_OPTINV[2] ← IOI_IOCLK[2] IOI_INT: mux IOI_IOCLK[2] bit 0 IODELAY[0]: IDELAY_VALUE_P bit 4 MISC_IOI: DRP_MCB_ADDRESS bit 2 ILOGIC[0]: DATA_WIDTH_RELOAD bit 1 IODELAY[0]: DRP_ADDR bit 0 IOI_INT: mux IMUX_OLOGIC_CLK[1] bit 1
B38 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: FFI_INIT bit 0 IOI_INT: invert IOI_IOCLK_OPTINV[0] ← IOI_IOCLK[0] IOI_INT: invert IOI_IOCLK_OPTINV[1] ← IOI_IOCLK[1] IODELAY[0]: ODELAY_VALUE_P bit 4 - ILOGIC[0]: DATA_WIDTH_RELOAD bit 0 IODELAY[0]: DRP_ADDR bit 1 IOI_INT: mux IMUX_OLOGIC_CLK[1] bit 0
B37 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: FFI_SRVAL bit 0 IOI_INT: mux IOI_IOCLK[0] bit 0 IOI_INT: mux IOI_IOCLK[1] bit 1 IODELAY[0]: IDELAY_VALUE_P bit 5 - ILOGIC[1]: DATA_WIDTH_RELOAD bit 2 IODELAY[0]: DRP_ADDR bit 2 IOI_INT: mux IMUX_OLOGIC_CLK[0] bit 1
B36 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: MUX_SR bit 0 IOI_INT: mux IOI_IOCLK[0] bit 4 IOI_INT: mux IOI_IOCLK[1] bit 4 IODELAY[0]: ODELAY_VALUE_P bit 5 - ILOGIC[1]: DATA_WIDTH_RELOAD bit 1 IODELAY[0]: DRP_ADDR bit 3 IOI_INT: mux IMUX_OLOGIC_CLK[0] bit 0
B35 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: FFI_REV_ENABLE IOI_INT: mux IOI_IOCLK[0] bit 1 IOI_INT: mux IOI_IOCLK[1] bit 0 IODELAY[0]: IDELAY_VALUE_P bit 6 - OLOGIC[1]: MUX_IN_O bit 0 - ILOGIC[1]: ENABLE
B34 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: CASCADE_ENABLE - - IODELAY[0]: ODELAY_VALUE_P bit 6 - OLOGIC[1]: FFO_RANK1_BYPASS - -
B33 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: FFI_LATCH IOI_INT: mux IOI_IOCLK[0] bit 2 IOI_INT: mux IOI_IOCLK[1] bit 2 IODELAY[0]: IDELAY_VALUE_P bit 7 - OLOGIC[1]: TRAIN_PATTERN bit 0 - -
B32 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! FFI_SR_SYNC IOI_INT: mux IOI_IOCLK[0] bit 3 IOI_INT: mux IOI_IOCLK[1] bit 3 IODELAY[0]: ODELAY_VALUE_P bit 7 - OLOGIC[1]: TRAIN_PATTERN bit 1 IODELAY[0]: DRP_ADDR bit 4 ILOGIC[0]: ENABLE
B31 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! FFI_CE_ENABLE IOI_INT: mux IOI_IOCLK[3] bit 3 IOI_INT: mux IOI_IOCLK[4] bit 3 IODELAY[1]: ODELAY_VALUE_P bit 7 - OLOGIC[1]: TRAIN_PATTERN bit 2 IODELAY[1]: DRP_ADDR bit 4 OLOGIC[1]: ENABLE
B30 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: CASCADE_ENABLE IOI_INT: mux IOI_IOCLK[3] bit 2 IOI_INT: mux IOI_IOCLK[4] bit 2 IODELAY[1]: IDELAY_VALUE_P bit 7 - OLOGIC[1]: TRAIN_PATTERN bit 3 - -
B29 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFO_LATCH - - IODELAY[1]: ODELAY_VALUE_P bit 6 - OLOGIC[1]: DDR_OPPOSITE_EDGE - -
B28 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFO_SR_ENABLE IOI_INT: mux IOI_IOCLK[3] bit 1 IOI_INT: mux IOI_IOCLK[4] bit 0 IODELAY[1]: IDELAY_VALUE_P bit 6 MISC_IOI: DRP_ENABLE OLOGIC[1]: MUX_IN_T bit 0 - OLOGIC[0]: ENABLE
B27 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFO_REV_ENABLE IOI_INT: mux IOI_IOCLK[3] bit 4 IOI_INT: mux IOI_IOCLK[4] bit 4 IODELAY[1]: ODELAY_VALUE_P bit 5 - OLOGIC[1]: FFO_CE_ENABLE IODELAY[1]: DRP_ADDR bit 3 OLOGIC[0]: IOCE_ENABLE
B26 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: ! FFO_SR_SYNC IOI_INT: mux IOI_IOCLK[3] bit 0 IOI_INT: mux IOI_IOCLK[4] bit 1 IODELAY[1]: IDELAY_VALUE_P bit 5 MISC_IOI: DRP_MCB_ADDRESS bit 1 OLOGIC[1]: FFO_CE_OR_DDR IODELAY[1]: DRP_ADDR bit 2 ILOGIC[0]: IOCE_ENABLE
B25 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFO_INIT bit 0 IOI_INT: invert IOI_IOCLK_OPTINV[3] ← IOI_IOCLK[3] IOI_INT: invert IOI_IOCLK_OPTINV[4] ← IOI_IOCLK[4] IODELAY[1]: ODELAY_VALUE_P bit 4 - OLOGIC[1]: FFO_RANK1_CLK_ENABLE IODELAY[1]: DRP_ADDR bit 1 OLOGIC[1]: IOCE_ENABLE
B24 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFO_SRVAL bit 0 IOI_INT: invert IOI_IOCLK_OPTINV[5] ← IOI_IOCLK[5] IOI_INT: mux IOI_IOCLK[5] bit 0 IODELAY[1]: IDELAY_VALUE_P bit 4 MISC_IOI: DRP_MCB_ADDRESS bit 0 OLOGIC[1]: FFO_RANK2_CLK_ENABLE IODELAY[1]: DRP_ADDR bit 0 ILOGIC[1]: IOCE_ENABLE
B23 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFT_SRVAL bit 0 IOI_DDR[1]: ENABLE bit 1 IOI_INT: mux IOI_IOCLK[5] bit 1 IODELAY[1]: IDELAY_VALUE_P bit 3 - OLOGIC[1]: FFT_RANK2_CLK_ENABLE IODELAY[1]: DRP07 bit 6 ILOGIC[0]: DATA_WIDTH_START bit 1
B22 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFT_INIT bit 0 IOI_DDR[1]: ENABLE bit 0 IODELAY[1]: CIN_ENABLE bit 2 IODELAY[1]: ODELAY_VALUE_P bit 3 - OLOGIC[1]: FFT_RANK1_CLK_ENABLE OLOGIC[1]: MUX_T bit 0 IODELAY[1]: DRP06 bit 6 ILOGIC[0]: BITSLIP_ENABLE
B21 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: ! FFT_SR_SYNC IODELAY[1]: MODE bit 1 - IODELAY[1]: IDELAY_VALUE_P bit 2 - OLOGIC[1]: FFT_CE_OR_DDR IODELAY[1]: DRP07 bit 7 ILOGIC[0]: DATA_WIDTH_START bit 0
B20 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFT_REV_ENABLE - - IODELAY[1]: ODELAY_VALUE_P bit 2 IODELAY[1]: DIFF_PHASE_DETECTOR OLOGIC[1]: FFT_CE_ENABLE OLOGIC[1]: MUX_OCE bit 0 IODELAY[1]: DRP06 bit 7 ILOGIC[1]: DATA_WIDTH_START bit 0
B19 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFT_SR_ENABLE IODELAY[1]: MODE bit 0 IODELAY[1]: IDELAY_MODE bit 1 IODELAY[1]: IDELAY_VALUE_P bit 1 IODELAY[1]: DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB bit 1 OLOGIC[1]: FFT_RANK1_BYPASS IODELAY[1]: IDELAY_FROM_HALF_MAX IODELAY[1]: DRP07 bit 0 ILOGIC[1]: DATA_WIDTH_START bit 1
B18 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFT_LATCH IODELAY[1]: TEST_GLITCH_FILTER IOI_INT: mux IOI_OCLK[1] bit 1 IODELAY[1]: ODELAY_VALUE_P bit 1 - ILOGIC[1]: DATA_WIDTH_RELOAD bit 0 IODELAY[1]: EVENT_SEL bit 0 IODELAY[1]: DRP06 bit 0 ILOGIC[1]: DATA_WIDTH_START bit 2
B17 - - - - - - - - - - - - - - - - - - - - - - - - IOI_INT: mux IOI_ICLK[1] bit 1 IODELAY[1]: IDELAY_VALUE_P bit 0 - OLOGIC[0]: TRAIN_PATTERN bit 1 IODELAY[1]: DRP07 bit 1 IODELAY[1]: COUNTER_WRAPAROUND bit 0 ILOGIC[1]: BITSLIP_ENABLE
B16 - - - - - - - - - - - - - - - - - - - - - - IODELAY[1]: IDELAY_FIXED - IOI_INT: mux IOI_ICLK[1] bit 0 IODELAY[1]: ODELAY_VALUE_P bit 0 - OLOGIC[0]: TRAIN_PATTERN bit 0 IODELAY[1]: EVENT_SEL bit 1 IODELAY[1]: DRP06 bit 1 ILOGIC[1]: CASCADE_ENABLE
B15 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: MUX_SR bit 0 IOI_INT: mux IOI_ICLK[1] bit 3 IOI_INT: mux IOI_OCLK[1] bit 0 IODELAY[1]: ODELAY_VALUE_N bit 0 - OLOGIC[0]: FFO_RANK1_BYPASS IODELAY[1]: DRP07 bit 5 OLOGIC[1]: MISR_ENABLE_DATA
B14 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: MUX_REV bit 0 IOI_INT: mux IOI_ICLK[1] bit 2 IOI_INT: mux IOI_OCLK[1] bit 3 IODELAY[1]: IDELAY_VALUE_N bit 0 - OLOGIC[0]: DDR_OPPOSITE_EDGE OLOGIC[1]: MUX_O bit 0 IODELAY[1]: DRP06 bit 5 OLOGIC[1]: MISR_ENABLE_CLK
B13 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFO_LATCH IOI_INT: mux IOI_IOCE[2] bit 0 IOI_INT: mux IOI_OCLK[1] bit 2 IODELAY[1]: ODELAY_VALUE_N bit 1 - OLOGIC[0]: TRAIN_PATTERN bit 2 IODELAY[1]: DRP06 bit 2 IODELAY[1]: DELAY_SRC bit 0 OLOGIC[0]: MISR_ENABLE_CLK
B12 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFO_SR_ENABLE - IOI_INT: mux IOI_IOCE[3] bit 0 IODELAY[1]: IDELAY_VALUE_N bit 1 IODELAY[1]: TEST_NCOUNTER OLOGIC[0]: MUX_IN_O bit 0 IODELAY[1]: DRP07 bit 2 IODELAY[1]: IODELAY_CHANGE bit 0 OLOGIC[0]: MISR_ENABLE_DATA
B11 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFO_REV_ENABLE IOI_INT: mux IOI_IOCE[2] bit 1 IOI_INT: mux IOI_IOCE[3] bit 1 IODELAY[1]: ODELAY_VALUE_N bit 2 - OLOGIC[0]: FFO_CE_ENABLE IODELAY[1]: LUMPED_DELAY IODELAY[1]: DRP07 bit 3 OLOGIC[1]: MISR_RESET
B10 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFO_SR_SYNC IOI_INT: mux IOI_IOCE[2] bit 2 IOI_INT: mux IOI_IOCE[3] bit 2 IODELAY[1]: IDELAY_VALUE_N bit 2 - OLOGIC[0]: FFO_CE_OR_DDR IODELAY[1]: DRP06 bit 3 IODELAY[1]: DELAY_SRC bit 1 OLOGIC[0]: MISR_RESET
B9 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFO_INIT bit 0 IOI_DDR[1]: ALIGNMENT bit 1 IODELAY[1]: IDELAY_MODE bit 0 IODELAY[1]: ODELAY_VALUE_N bit 3 IODELAY[1]: DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB bit 0 OLOGIC[0]: FFO_RANK1_CLK_ENABLE IODELAY[1]: LUMPED_DELAY_SELECT IODELAY[1]: DRP07 bit 4 MISC_IOI: ENFFSCAN_DRP bit 1
B8 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFO_SRVAL bit 0 IOI_DDR[1]: ALIGNMENT bit 0 IODELAY[1]: MODE bit 3 IODELAY[1]: IDELAY_VALUE_N bit 3 - OLOGIC[0]: FFO_RANK2_CLK_ENABLE ILOGIC[1]: ! FFI_DELAY_ENABLE IODELAY[1]: DRP06 bit 4 -
B7 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFT_SRVAL bit 0 IODELAY[1]: MODE bit 2 IODELAY[1]: DELAYCHAIN_OSC IODELAY[1]: IDELAY_VALUE_N bit 4 - OLOGIC[0]: FFT_RANK2_CLK_ENABLE IODELAY[1]: CAL_DELAY_MAX bit 7 -
B6 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFT_INIT bit 0 ILOGIC[1]: ! I_DELAY_ENABLE IODELAY[1]: CIN_ENABLE bit 1 IODELAY[1]: ODELAY_VALUE_N bit 4 - OLOGIC[0]: FFT_RANK1_CLK_ENABLE IODELAY[1]: CAL_DELAY_MAX bit 6 -
B5 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFT_SR_SYNC ILOGIC[1]: MUX_TSBYPASS bit 0 IODELAY[1]: CIN_ENABLE bit 0 IODELAY[1]: IDELAY_VALUE_N bit 5 - OLOGIC[0]: FFT_CE_OR_DDR IODELAY[1]: CAL_DELAY_MAX bit 5 -
B4 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFT_REV_ENABLE IODELAY[1]: ODATAIN_ENABLE IOI_INT: mux IMUX_OLOGIC_IOCE[1] bit 2 IODELAY[1]: ODELAY_VALUE_N bit 5 - OLOGIC[0]: FFT_CE_ENABLE IODELAY[1]: CAL_DELAY_MAX bit 4 -
B3 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFT_SR_ENABLE IOI_INT: mux IMUX_ILOGIC_IOCE[1] bit 2 IOI_INT: mux IMUX_OLOGIC_IOCE[1] bit 0 IODELAY[1]: IDELAY_VALUE_N bit 6 - OLOGIC[0]: TRAIN_PATTERN bit 3 IODELAY[1]: CAL_DELAY_MAX bit 3 IOI_INT: mux IMUX_IODELAY_IOCLK[0] bit 0
B2 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFT_LATCH IOI_INT: mux IMUX_ILOGIC_IOCE[1] bit 0 IOI_INT: mux IMUX_OLOGIC_IOCE[1] bit 1 IODELAY[1]: ODELAY_VALUE_N bit 6 - OLOGIC[0]: MUX_IN_T bit 0 IODELAY[1]: CAL_DELAY_MAX bit 2 -
B1 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MUX_SR bit 0 IOI_INT: mux IMUX_ILOGIC_IOCE[1] bit 1 - IODELAY[1]: IDELAY_VALUE_N bit 7 - OLOGIC[0]: FFT_RANK1_BYPASS IODELAY[1]: CAL_DELAY_MAX bit 1 IOI_INT: mux IMUX_IODELAY_IOCLK[1] bit 0
B0 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MUX_REV bit 0 - - IODELAY[1]: ODELAY_VALUE_N bit 7 IODELAY[1]: TEST_PCOUNTER OLOGIC[0]: OUTPUT_MODE bit 0 IODELAY[1]: CAL_DELAY_MAX bit 0 -

Tile IOI_SN

Cells: 1

Switchbox IOI_INT

spartan6 IOI_SN switchbox IOI_INT programmable inverters
DestinationSourceBit
IOI_IOCLK_OPTINV[0]IOI_IOCLK[0]MAIN[29][38]
IOI_IOCLK_OPTINV[1]IOI_IOCLK[1]MAIN[23][38]
IOI_IOCLK_OPTINV[2]IOI_IOCLK[2]MAIN[29][39]
IOI_IOCLK_OPTINV[3]IOI_IOCLK[3]MAIN[29][25]
IOI_IOCLK_OPTINV[4]IOI_IOCLK[4]MAIN[23][25]
IOI_IOCLK_OPTINV[5]IOI_IOCLK[5]MAIN[29][24]
spartan6 IOI_SN switchbox IOI_INT muxes IOI_IOCLK[0]
BitsDestination
MAIN[29][36]MAIN[29][32]MAIN[29][33]MAIN[29][35]MAIN[29][37]IOI_IOCLK[0]
Source
00000off
00001IMUX_GFAN[1]
00010IMUX_CLK[1]
00100IOCLK[0]
01000IOCLK[2]
10000PLLCLK[0]
spartan6 IOI_SN switchbox IOI_INT muxes IOI_IOCLK[1]
BitsDestination
MAIN[23][36]MAIN[23][32]MAIN[23][33]MAIN[23][37]MAIN[23][35]IOI_IOCLK[1]
Source
00000off
00001IMUX_GFAN[1]
00010IMUX_CLK[1]
00100IOCLK[1]
01000IOCLK[3]
10000PLLCLK[1]
spartan6 IOI_SN switchbox IOI_INT muxes IOI_IOCLK[2]
BitsDestination
MAIN[23][40]MAIN[23][39]IOI_IOCLK[2]
Source
00off
01PLLCLK[0]
10PLLCLK[1]
spartan6 IOI_SN switchbox IOI_INT muxes IOI_IOCLK[3]
BitsDestination
MAIN[29][27]MAIN[29][31]MAIN[29][30]MAIN[29][28]MAIN[29][26]IOI_IOCLK[3]
Source
00000off
00001IMUX_GFAN[0]
00010IMUX_CLK[0]
00100IOCLK[0]
01000IOCLK[2]
10000PLLCLK[0]
spartan6 IOI_SN switchbox IOI_INT muxes IOI_IOCLK[4]
BitsDestination
MAIN[23][27]MAIN[23][31]MAIN[23][30]MAIN[23][26]MAIN[23][28]IOI_IOCLK[4]
Source
00000off
00001IMUX_GFAN[0]
00010IMUX_CLK[0]
00100IOCLK[1]
01000IOCLK[3]
10000PLLCLK[1]
spartan6 IOI_SN switchbox IOI_INT muxes IOI_IOCLK[5]
BitsDestination
MAIN[23][23]MAIN[23][24]IOI_IOCLK[5]
Source
00off
01PLLCLK[0]
10PLLCLK[1]
spartan6 IOI_SN switchbox IOI_INT muxes IOI_IOCE[0]
BitsDestination
MAIN[29][53]MAIN[29][52]MAIN[29][50]IOI_IOCE[0]
Source
000off
001IOCE[0]
010IOCE[2]
100PLLCE[0]
spartan6 IOI_SN switchbox IOI_INT muxes IOI_IOCE[1]
BitsDestination
MAIN[23][53]MAIN[23][52]MAIN[23][51]IOI_IOCE[1]
Source
000off
001IOCE[1]
010IOCE[3]
100PLLCE[1]
spartan6 IOI_SN switchbox IOI_INT muxes IOI_IOCE[2]
BitsDestination
MAIN[29][10]MAIN[29][11]MAIN[29][13]IOI_IOCE[2]
Source
000off
001IOCE[0]
010IOCE[2]
100PLLCE[0]
spartan6 IOI_SN switchbox IOI_INT muxes IOI_IOCE[3]
BitsDestination
MAIN[23][10]MAIN[23][11]MAIN[23][12]IOI_IOCE[3]
Source
000off
001IOCE[1]
010IOCE[3]
100PLLCE[1]
spartan6 IOI_SN switchbox IOI_INT muxes IOI_ICLK[0]
BitsDestination
MAIN[29][48]MAIN[29][49]MAIN[23][46]MAIN[23][47]IOI_ICLK[0]
Source
0000off
0001IOI_IOCLK[0]
0010IOI_IOCLK[1]
0100IOI_IOCLK[2]
1000OUT_DDR_IOCLK[0]
spartan6 IOI_SN switchbox IOI_INT muxes IOI_ICLK[1]
BitsDestination
MAIN[29][15]MAIN[29][14]MAIN[23][17]MAIN[23][16]IOI_ICLK[1]
Source
0000off
0001IOI_IOCLK[3]
0010IOI_IOCLK[4]
0100IOI_IOCLK[5]
1000OUT_DDR_IOCLK[1]
spartan6 IOI_SN switchbox IOI_INT muxes IOI_OCLK[0]
BitsDestination
MAIN[23][49]MAIN[23][50]MAIN[23][45]MAIN[23][48]IOI_OCLK[0]
Source
0000off
0001IOI_IOCLK[0]
0010IOI_IOCLK[1]
0100IOI_IOCLK[2]
1000OUT_DDR_IOCLK[0]
spartan6 IOI_SN switchbox IOI_INT muxes IOI_OCLK[1]
BitsDestination
MAIN[23][14]MAIN[23][13]MAIN[23][18]MAIN[23][15]IOI_OCLK[1]
Source
0000off
0001IOI_IOCLK[3]
0010IOI_IOCLK[4]
0100IOI_IOCLK[5]
1000OUT_DDR_IOCLK[1]
spartan6 IOI_SN switchbox IOI_INT muxes IMUX_ILOGIC_IOCE[0]
BitsDestination
MAIN[29][60]MAIN[29][62]MAIN[29][61]IMUX_ILOGIC_IOCE[0]
Source
000off
001IOI_IOCE[0]
010IOI_IOCE[1]
100OUT_DDR_IOCE[0]
spartan6 IOI_SN switchbox IOI_INT muxes IMUX_ILOGIC_IOCE[1]
BitsDestination
MAIN[29][3]MAIN[29][1]MAIN[29][2]IMUX_ILOGIC_IOCE[1]
Source
000off
001IOI_IOCE[2]
010IOI_IOCE[3]
100OUT_DDR_IOCE[1]
spartan6 IOI_SN switchbox IOI_INT muxes IMUX_OLOGIC_IOCE[0]
BitsDestination
MAIN[23][59]MAIN[23][61]MAIN[23][60]IMUX_OLOGIC_IOCE[0]
Source
000off
001IOI_IOCE[0]
010IOI_IOCE[1]
100OUT_DDR_IOCE[0]
spartan6 IOI_SN switchbox IOI_INT muxes IMUX_OLOGIC_IOCE[1]
BitsDestination
MAIN[23][4]MAIN[23][2]MAIN[23][3]IMUX_OLOGIC_IOCE[1]
Source
000off
001IOI_IOCE[2]
010IOI_IOCE[3]
100OUT_DDR_IOCE[1]
spartan6 IOI_SN switchbox IOI_INT muxes IMUX_ILOGIC_CLK[0]
BitsDestination
MAIN[26][41]MAIN[26][40]IMUX_ILOGIC_CLK[0]
Source
00off
01IOI_ICLK[0]
10IOI_ICLK[1]
spartan6 IOI_SN switchbox IOI_INT muxes IMUX_ILOGIC_CLK[1]
BitsDestination
MAIN[26][43]MAIN[26][42]IMUX_ILOGIC_CLK[1]
Source
00off
01IOI_ICLK[0]
10IOI_ICLK[1]
spartan6 IOI_SN switchbox IOI_INT muxes IMUX_OLOGIC_CLK[0]
BitsDestination
MAIN[26][37]MAIN[26][36]IMUX_OLOGIC_CLK[0]
Source
00off
01IOI_OCLK[0]
10IOI_OCLK[1]
spartan6 IOI_SN switchbox IOI_INT muxes IMUX_OLOGIC_CLK[1]
BitsDestination
MAIN[26][39]MAIN[26][38]IMUX_OLOGIC_CLK[1]
Source
00off
01IOI_OCLK[0]
10IOI_OCLK[1]
spartan6 IOI_SN switchbox IOI_INT muxes IMUX_IODELAY_IOCLK[0]
BitsDestination
MAIN[26][3]IMUX_IODELAY_IOCLK[0]
Source
0IMUX_ILOGIC_CLK[0]
1IMUX_OLOGIC_CLK[0]
spartan6 IOI_SN switchbox IOI_INT muxes IMUX_IODELAY_IOCLK[1]
BitsDestination
MAIN[26][1]IMUX_IODELAY_IOCLK[1]
Source
0IMUX_ILOGIC_CLK[1]
1IMUX_OLOGIC_CLK[1]

Bels IOI_DDR

spartan6 IOI_SN bel IOI_DDR pins
PinDirectionIOI_DDR[0]IOI_DDR[1]
CLK0inIOI_IOCLK[0]IOI_IOCLK[3]
CLK1inIOI_IOCLK[1]IOI_IOCLK[4]
CLKoutOUT_DDR_IOCLK[0]OUT_DDR_IOCLK[1]
IOCEoutOUT_DDR_IOCE[0]OUT_DDR_IOCE[1]
spartan6 IOI_SN bel IOI_DDR attribute bits
AttributeIOI_DDR[0]IOI_DDR[1]
ENABLE bit 0MAIN[29][40]MAIN[29][22]
ENABLE bit 1MAIN[29][41]MAIN[29][23]
ALIGNMENT[enum: IOI_DDR_ALIGNMENT][enum: IOI_DDR_ALIGNMENT]
spartan6 IOI_SN enum IOI_DDR_ALIGNMENT
IOI_DDR[0].ALIGNMENTMAIN[29][54]MAIN[29][55]
IOI_DDR[1].ALIGNMENTMAIN[29][9]MAIN[29][8]
NONE00
CLK001
CLK110

Bels ILOGIC

spartan6 IOI_SN bel ILOGIC pins
PinDirectionILOGIC[0]ILOGIC[1]
CLKinIMUX_ILOGIC_CLK[0]IMUX_ILOGIC_CLK[1]
IOCEinIMUX_ILOGIC_IOCE[0]IMUX_ILOGIC_IOCE[1]
CLKDIVinIMUX_CLK[1]IMUX_CLK[0]
SRinIMUX_LOGICIN[20]IMUX_LOGICIN[36]
REVinIMUX_LOGICIN[59]IMUX_LOGICIN[37]
CE0inIMUX_LOGICIN[62]IMUX_LOGICIN[38]
BITSLIPinIMUX_LOGICIN[19]IMUX_LOGICIN[57]
FABRICOUToutOUT_BEL[7]OUT_BEL[0]
Q1outOUT_BEL[8]OUT_BEL[1]
Q2outOUT_BEL[9]OUT_BEL[2]
Q3outOUT_BEL[10]OUT_BEL[3]
Q4outOUT_BEL[11]OUT_BEL[4]
INCDECout-OUT_BEL[5]
VALIDout-OUT_BEL[6]
DFBoutOUT_CLKPAD_DFB[0]OUT_CLKPAD_DFB[1]
CFB0outOUT_CLKPAD_CFB0[0]OUT_CLKPAD_CFB0[1]
CFB1outOUT_CLKPAD_CFB1[0]OUT_CLKPAD_CFB1[1]
spartan6 IOI_SN bel ILOGIC attribute bits
AttributeILOGIC[0]ILOGIC[1]
ENABLEMAIN[26][32]MAIN[26][35]
DDRMAIN[22][40]MAIN[22][60]
IOCE_ENABLEMAIN[26][26]MAIN[26][24]
FFI_INIT bit 0MAIN[22][38]MAIN[22][41]
FFI_SRVAL bit 0MAIN[22][37]MAIN[22][55]
FFI_LATCHMAIN[22][33]MAIN[22][63]
FFI_SR_ENABLEMAIN[22][39]MAIN[22][42]
FFI_SR_SYNC!MAIN[22][32]!MAIN[22][62]
FFI_REV_ENABLEMAIN[22][35]MAIN[22][59]
FFI_CE_ENABLE!MAIN[22][31]!MAIN[22][57]
FFI_DELAY_ENABLE!MAIN[28][55]!MAIN[28][8]
I_DELAY_ENABLE!MAIN[29][57]!MAIN[29][6]
MUX_TSBYPASS[enum: ILOGIC_MUX_TSBYPASS][enum: ILOGIC_MUX_TSBYPASS]
MUX_D[enum: ILOGIC_MUX_D]-
MUX_SR[enum: ILOGIC_MUX_SR][enum: ILOGIC_MUX_SR]
DATA_WIDTH_START[enum: ILOGIC_DATA_WIDTH][enum: ILOGIC_DATA_WIDTH]
DATA_WIDTH_RELOAD[enum: ILOGIC_DATA_WIDTH][enum: ILOGIC_DATA_WIDTH]
BITSLIP_ENABLEMAIN[26][22]MAIN[26][17]
CASCADE_ENABLEMAIN[22][34]MAIN[26][16]
MUX_Q1[enum: ILOGIC_MUX_Q][enum: ILOGIC_MUX_Q]
MUX_Q2[enum: ILOGIC_MUX_Q][enum: ILOGIC_MUX_Q]
MUX_Q3[enum: ILOGIC_MUX_Q][enum: ILOGIC_MUX_Q]
MUX_Q4[enum: ILOGIC_MUX_Q][enum: ILOGIC_MUX_Q]
ROW1_CLK_ENABLEMAIN[22][45]MAIN[22][50]
ROW2_CLK_ENABLEMAIN[22][44]MAIN[22][51]
ROW3_CLK_ENABLEMAIN[22][46]MAIN[22][49]
ROW4_CLK_ENABLEMAIN[22][47]MAIN[22][48]
spartan6 IOI_SN enum ILOGIC_MUX_TSBYPASS
ILOGIC[0].MUX_TSBYPASSMAIN[29][58]
ILOGIC[1].MUX_TSBYPASSMAIN[29][5]
GND0
T1
spartan6 IOI_SN enum ILOGIC_MUX_D
ILOGIC[0].MUX_DMAIN[23][43]MAIN[23][42]
IOB_I00
OTHER_IOB_I11
spartan6 IOI_SN enum ILOGIC_MUX_SR
ILOGIC[0].MUX_SRMAIN[22][36]
ILOGIC[1].MUX_SRMAIN[22][58]
INT1
OLOGIC_SR0
spartan6 IOI_SN enum ILOGIC_DATA_WIDTH
ILOGIC[0].DATA_WIDTH_STARTMAIN[26][23]MAIN[26][21]
_200
_301
_410
spartan6 IOI_SN enum ILOGIC_DATA_WIDTH
ILOGIC[1].DATA_WIDTH_STARTMAIN[26][18]MAIN[26][19]MAIN[26][20]
_2000
_3001
_4010
_5011
_6100
_7101
_8110
spartan6 IOI_SN enum ILOGIC_DATA_WIDTH
ILOGIC[0].DATA_WIDTH_RELOADMAIN[27][39]MAIN[27][38]
_111
_210
_301
_400
spartan6 IOI_SN enum ILOGIC_DATA_WIDTH
ILOGIC[1].DATA_WIDTH_RELOADMAIN[27][37]MAIN[27][36]MAIN[27][18]
_1111
_2110
_3101
_4100
_5011
_6010
_7001
_8000
spartan6 IOI_SN enum ILOGIC_MUX_Q
ILOGIC[0].MUX_Q1MAIN[27][46]MAIN[27][47]
ILOGIC[1].MUX_Q1MAIN[27][49]MAIN[27][48]
ILOGIC[0].MUX_Q2MAIN[27][45]MAIN[27][44]
ILOGIC[1].MUX_Q2MAIN[27][50]MAIN[27][51]
ILOGIC[0].MUX_Q3MAIN[27][42]MAIN[27][43]
ILOGIC[1].MUX_Q3MAIN[27][53]MAIN[27][52]
ILOGIC[0].MUX_Q4MAIN[27][41]MAIN[27][40]
ILOGIC[1].MUX_Q4MAIN[27][54]MAIN[27][55]
NETWORKING01
NETWORKING_PIPELINED10
RETIMED11
SHIFT_REGISTER00

Bels OLOGIC

spartan6 IOI_SN bel OLOGIC pins
PinDirectionOLOGIC[0]OLOGIC[1]
CLKinIMUX_OLOGIC_CLK[0]IMUX_OLOGIC_CLK[1]
IOCEinIMUX_OLOGIC_IOCE[0]IMUX_OLOGIC_IOCE[1]
CLKDIVinIMUX_CLK[1]IMUX_CLK[0]
SRinIMUX_SR[1]IMUX_SR[0]
REVinIMUX_LOGICIN[14]IMUX_LOGICIN[29]
OCEinIMUX_LOGICIN[39]IMUX_LOGICIN[30]
TCEinIMUX_LOGICIN[9]IMUX_LOGICIN[23]
D1inIMUX_LOGICIN[15]IMUX_LOGICIN[31]
D2inIMUX_LOGICIN[16]IMUX_LOGICIN[32]
D3inIMUX_LOGICIN[17]IMUX_LOGICIN[44]
D4inIMUX_LOGICIN[48]IMUX_LOGICIN[34]
T1inIMUX_LOGICIN[45]IMUX_LOGICIN[24]
T2inIMUX_LOGICIN[42]IMUX_LOGICIN[25]
T3inIMUX_LOGICIN[12]IMUX_LOGICIN[26]
T4inIMUX_LOGICIN[54]IMUX_LOGICIN[27]
TRAINinIMUX_LOGICIN[28]IMUX_LOGICIN[8]
spartan6 IOI_SN bel OLOGIC attribute bits
AttributeOLOGIC[0]OLOGIC[1]
ENABLEMAIN[26][28]MAIN[26][31]
IOCE_ENABLEMAIN[26][27]MAIN[26][25]
DDR_OPPOSITE_EDGEMAIN[27][14]MAIN[27][29]
FFO_INIT bit 0MAIN[22][9]MAIN[22][25]
FFO_SRVAL bit 0MAIN[22][8]MAIN[22][24]
FFO_LATCHMAIN[22][13]MAIN[22][29]
FFO_RANK1_BYPASSMAIN[27][15]MAIN[27][34]
FFO_RANK1_CLK_ENABLEMAIN[27][9]MAIN[27][25]
FFO_RANK2_CLK_ENABLEMAIN[27][8]MAIN[27][24]
FFO_SR_SYNC!MAIN[22][10]!MAIN[22][26]
FFO_SR_ENABLEMAIN[22][12]MAIN[22][28]
FFO_REV_ENABLEMAIN[22][11]MAIN[22][27]
FFO_CE_ENABLEMAIN[27][11]MAIN[27][27]
FFO_CE_OR_DDRMAIN[27][10]MAIN[27][26]
FFT_INIT bit 0MAIN[22][6]MAIN[22][22]
FFT_SRVAL bit 0MAIN[22][7]MAIN[22][23]
FFT_LATCHMAIN[22][2]MAIN[22][18]
FFT_RANK1_BYPASSMAIN[27][1]MAIN[27][19]
FFT_RANK1_CLK_ENABLEMAIN[27][6]MAIN[27][22]
FFT_RANK2_CLK_ENABLEMAIN[27][7]MAIN[27][23]
FFT_SR_SYNC!MAIN[22][5]!MAIN[22][21]
FFT_SR_ENABLEMAIN[22][3]MAIN[22][19]
FFT_REV_ENABLEMAIN[22][4]MAIN[22][20]
FFT_CE_ENABLEMAIN[27][4]MAIN[27][20]
FFT_CE_OR_DDRMAIN[27][5]MAIN[27][21]
MUX_IN_O[enum: OLOGIC_MUX_IN][enum: OLOGIC_MUX_IN]
MUX_IN_T[enum: OLOGIC_MUX_IN][enum: OLOGIC_MUX_IN]
MUX_OCE[enum: OLOGIC_MUX_OCE][enum: OLOGIC_MUX_OCE]
MUX_SR[enum: OLOGIC_MUX_SR][enum: OLOGIC_MUX_SR]
MUX_REV[enum: OLOGIC_MUX_REV][enum: OLOGIC_MUX_REV]
MUX_TRAIN[enum: OLOGIC_MUX_TRAIN][enum: OLOGIC_MUX_TRAIN]
MUX_O[enum: OLOGIC_MUX_O][enum: OLOGIC_MUX_O]
MUX_T[enum: OLOGIC_MUX_T][enum: OLOGIC_MUX_T]
CASCADE_ENABLEMAIN[26][46]MAIN[22][30]
OUTPUT_MODE[enum: OLOGIC_OUTPUT_MODE]-
TRAIN_PATTERN bit 0MAIN[27][16]MAIN[27][33]
TRAIN_PATTERN bit 1MAIN[27][17]MAIN[27][32]
TRAIN_PATTERN bit 2MAIN[27][13]MAIN[27][31]
TRAIN_PATTERN bit 3MAIN[27][3]MAIN[27][30]
MISR_ENABLE_CLKMAIN[26][13]MAIN[26][14]
MISR_ENABLE_DATAMAIN[26][12]MAIN[26][15]
MISR_RESETMAIN[26][10]MAIN[26][11]
spartan6 IOI_SN enum OLOGIC_MUX_IN
OLOGIC[0].MUX_IN_OMAIN[27][12]
OLOGIC[1].MUX_IN_OMAIN[27][35]
OLOGIC[0].MUX_IN_TMAIN[27][2]
OLOGIC[1].MUX_IN_TMAIN[27][28]
INT0
MCB1
spartan6 IOI_SN enum OLOGIC_MUX_OCE
OLOGIC[0].MUX_OCEMAIN[28][43]
OLOGIC[1].MUX_OCEMAIN[28][20]
INT0
PCI_CE1
spartan6 IOI_SN enum OLOGIC_MUX_SR
OLOGIC[0].MUX_SRMAIN[22][1]
OLOGIC[1].MUX_SRMAIN[22][15]
GND0
INT1
spartan6 IOI_SN enum OLOGIC_MUX_REV
OLOGIC[0].MUX_REVMAIN[22][0]
OLOGIC[1].MUX_REVMAIN[22][14]
GND0
INT1
spartan6 IOI_SN enum OLOGIC_MUX_TRAIN
OLOGIC[0].MUX_TRAINMAIN[26][47]MAIN[26][45]
OLOGIC[1].MUX_TRAINMAIN[26][48]MAIN[26][44]
GND00
INT01
MCB10
spartan6 IOI_SN enum OLOGIC_MUX_O
OLOGIC[0].MUX_OMAIN[28][49]
OLOGIC[1].MUX_OMAIN[28][14]
D11
FFO0
spartan6 IOI_SN enum OLOGIC_MUX_T
OLOGIC[0].MUX_TMAIN[28][41]
OLOGIC[1].MUX_TMAIN[28][22]
T11
FFT0
spartan6 IOI_SN enum OLOGIC_OUTPUT_MODE
OLOGIC[0].OUTPUT_MODEMAIN[27][0]
SINGLE_ENDED0
DIFFERENTIAL1

Bels IODELAY

spartan6 IOI_SN bel IODELAY pins
PinDirectionIODELAY[0]IODELAY[1]
IOCLKinIMUX_IODELAY_IOCLK[0]IMUX_IODELAY_IOCLK[1]
RSTinIMUX_LOGICIN[41]IMUX_LOGICIN[55]
CALinIMUX_LOGICIN[3]IMUX_LOGICIN[2]
CEinIMUX_LOGICIN[5]IMUX_LOGICIN[47]
CINinIMUX_LOGICIN[52]IMUX_LOGICIN[1]
CLKinIMUX_CLK[1]IMUX_CLK[0]
INCinIMUX_LOGICIN[7]IMUX_LOGICIN[58]
BUSYoutOUT_BEL[15]OUT_BEL[14]
LOADoutOUT_BEL[17]OUT_BEL[16]
RCLKoutOUT_BEL[13]OUT_BEL[12]
DQSOUTPout-OUT_CLKPAD_DQSP
DQSOUTNout-OUT_CLKPAD_DQSN
spartan6 IOI_SN bel IODELAY attribute bits
AttributeIODELAY[0]IODELAY[1]
MODE[enum: IODELAY_MODE][enum: IODELAY_MODE]
COUNTER_WRAPAROUND[enum: IOLOGIC_COUNTER_WRAPAROUND][enum: IOLOGIC_COUNTER_WRAPAROUND]
DELAYCHAIN_OSCMAIN[23][56]MAIN[23][7]
DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB bit 0MAIN[25][44]MAIN[25][9]
DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB bit 1MAIN[25][54]MAIN[25][19]
DELAY_SRC[enum: IODELAY_DELAY_SRC][enum: IODELAY_DELAY_SRC]
DIFF_PHASE_DETECTORMAIN[25][55]MAIN[25][20]
CIN_ENABLE bit 0MAIN[23][41]MAIN[23][5]
CIN_ENABLE bit 1MAIN[23][57]MAIN[23][6]
CIN_ENABLE bit 2MAIN[23][58]MAIN[23][22]
ODATAIN_ENABLEMAIN[29][59]MAIN[29][4]
IDELAY_FIXEDMAIN[22][52]MAIN[22][16]
IDELAY_FROM_HALF_MAXMAIN[28][44]MAIN[28][19]
IDELAY_MODE[enum: IODELAY_IDELAY_MODE][enum: IODELAY_IDELAY_MODE]
IODELAY_CHANGE[enum: IODELAY_CHANGE][enum: IODELAY_CHANGE]
LUMPED_DELAYMAIN[28][52]MAIN[28][11]
LUMPED_DELAY_SELECTMAIN[28][54]MAIN[28][9]
PLUS1MAIN[28][45]-
TEST_GLITCH_FILTERMAIN[29][45]MAIN[29][18]
TEST_PCOUNTERMAIN[25][49]MAIN[25][0]
TEST_NCOUNTERMAIN[25][51]MAIN[25][12]
EVENT_SEL bit 0-MAIN[28][18]
EVENT_SEL bit 1-MAIN[28][16]
CAL_DELAY_MAX bit 0MAIN[28][63]MAIN[28][0]
CAL_DELAY_MAX bit 1MAIN[28][62]MAIN[28][1]
CAL_DELAY_MAX bit 2MAIN[28][61]MAIN[28][2]
CAL_DELAY_MAX bit 3MAIN[28][60]MAIN[28][3]
CAL_DELAY_MAX bit 4MAIN[28][59]MAIN[28][4]
CAL_DELAY_MAX bit 5MAIN[28][58]MAIN[28][5]
CAL_DELAY_MAX bit 6MAIN[28][57]MAIN[28][6]
CAL_DELAY_MAX bit 7MAIN[28][56]MAIN[28][7]
IDELAY_VALUE_P bit 0MAIN[24][46]MAIN[24][17]
IDELAY_VALUE_P bit 1MAIN[24][44]MAIN[24][19]
IDELAY_VALUE_P bit 2MAIN[24][42]MAIN[24][21]
IDELAY_VALUE_P bit 3MAIN[24][40]MAIN[24][23]
IDELAY_VALUE_P bit 4MAIN[24][39]MAIN[24][24]
IDELAY_VALUE_P bit 5MAIN[24][37]MAIN[24][26]
IDELAY_VALUE_P bit 6MAIN[24][35]MAIN[24][28]
IDELAY_VALUE_P bit 7MAIN[24][33]MAIN[24][30]
IDELAY_VALUE_N bit 0MAIN[24][49]MAIN[24][14]
IDELAY_VALUE_N bit 1MAIN[24][51]MAIN[24][12]
IDELAY_VALUE_N bit 2MAIN[24][53]MAIN[24][10]
IDELAY_VALUE_N bit 3MAIN[24][55]MAIN[24][8]
IDELAY_VALUE_N bit 4MAIN[24][56]MAIN[24][7]
IDELAY_VALUE_N bit 5MAIN[24][58]MAIN[24][5]
IDELAY_VALUE_N bit 6MAIN[24][60]MAIN[24][3]
IDELAY_VALUE_N bit 7MAIN[24][62]MAIN[24][1]
ODELAY_VALUE_P bit 0MAIN[24][47]MAIN[24][16]
ODELAY_VALUE_P bit 1MAIN[24][45]MAIN[24][18]
ODELAY_VALUE_P bit 2MAIN[24][43]MAIN[24][20]
ODELAY_VALUE_P bit 3MAIN[24][41]MAIN[24][22]
ODELAY_VALUE_P bit 4MAIN[24][38]MAIN[24][25]
ODELAY_VALUE_P bit 5MAIN[24][36]MAIN[24][27]
ODELAY_VALUE_P bit 6MAIN[24][34]MAIN[24][29]
ODELAY_VALUE_P bit 7MAIN[24][32]MAIN[24][31]
ODELAY_VALUE_N bit 0MAIN[24][48]MAIN[24][15]
ODELAY_VALUE_N bit 1MAIN[24][50]MAIN[24][13]
ODELAY_VALUE_N bit 2MAIN[24][52]MAIN[24][11]
ODELAY_VALUE_N bit 3MAIN[24][54]MAIN[24][9]
ODELAY_VALUE_N bit 4MAIN[24][57]MAIN[24][6]
ODELAY_VALUE_N bit 5MAIN[24][59]MAIN[24][4]
ODELAY_VALUE_N bit 6MAIN[24][61]MAIN[24][2]
ODELAY_VALUE_N bit 7MAIN[24][63]MAIN[24][0]
DRP_ADDR bit 0MAIN[28][39]MAIN[28][24]
DRP_ADDR bit 1MAIN[28][38]MAIN[28][25]
DRP_ADDR bit 2MAIN[28][37]MAIN[28][26]
DRP_ADDR bit 3MAIN[28][36]MAIN[28][27]
DRP_ADDR bit 4MAIN[28][32]MAIN[28][31]
DRP06 bit 0MAIN[28][45]MAIN[28][18]
DRP06 bit 1MAIN[28][47]MAIN[28][16]
DRP06 bit 2MAIN[28][50]MAIN[28][13]
DRP06 bit 3MAIN[28][53]MAIN[28][10]
DRP06 bit 4MAIN[28][55]MAIN[28][8]
DRP06 bit 5MAIN[28][49]MAIN[28][14]
DRP06 bit 6MAIN[28][41]MAIN[28][22]
DRP06 bit 7MAIN[28][43]MAIN[28][20]
DRP07 bit 0MAIN[28][44]MAIN[28][19]
DRP07 bit 1MAIN[28][46]MAIN[28][17]
DRP07 bit 2MAIN[28][51]MAIN[28][12]
DRP07 bit 3MAIN[28][52]MAIN[28][11]
DRP07 bit 4MAIN[28][54]MAIN[28][9]
DRP07 bit 5MAIN[28][48]MAIN[28][15]
DRP07 bit 6MAIN[28][40]MAIN[28][23]
DRP07 bit 7MAIN[28][42]MAIN[28][21]
spartan6 IOI_SN enum IODELAY_MODE
IODELAY[0].MODEMAIN[29][56]MAIN[23][55]MAIN[29][44]MAIN[29][42]
IODELAY[1].MODEMAIN[29][7]MAIN[23][8]MAIN[29][21]MAIN[29][19]
IODRP20000
IODELAY20011
IODRP2_MCB1100
spartan6 IOI_SN enum IOLOGIC_COUNTER_WRAPAROUND
IODELAY[0].COUNTER_WRAPAROUNDMAIN[28][46]
IODELAY[1].COUNTER_WRAPAROUNDMAIN[28][17]
WRAPAROUND0
STAY_AT_LIMIT1
spartan6 IOI_SN enum IODELAY_DELAY_SRC
IODELAY[0].DELAY_SRCMAIN[28][53]MAIN[28][50]
IODELAY[1].DELAY_SRCMAIN[28][10]MAIN[28][13]
IO00
ODATAIN01
IDATAIN11
spartan6 IOI_SN enum IODELAY_IDELAY_MODE
IODELAY[0].IDELAY_MODEMAIN[23][54]MAIN[23][44]
IODELAY[1].IDELAY_MODEMAIN[23][19]MAIN[23][9]
NORMAL00
PCI11
spartan6 IOI_SN enum IODELAY_CHANGE
IODELAY[0].IODELAY_CHANGEMAIN[28][51]
IODELAY[1].IODELAY_CHANGEMAIN[28][12]
CHANGE_ON_CLOCK0
CHANGE_ON_DATA1

Bels MISC_IOI

spartan6 IOI_SN bel MISC_IOI pins
PinDirectionMISC_IOI
spartan6 IOI_SN bel MISC_IOI attribute bits
AttributeMISC_IOI
MEM_PLL_DIV_ENMAIN[25][56]
MEM_PLL_POL_SEL[enum: MCB_MEM_PLL_POL_SEL]
DRP_ENABLEMAIN[25][28]
DRP_FROM_MCBMAIN[25][46]
ENFFSCAN_DRP bit 0MAIN[25][43]
ENFFSCAN_DRP bit 1MAIN[26][9]
DRP_MCB_ADDRESS bit 0MAIN[25][24]
DRP_MCB_ADDRESS bit 1MAIN[25][26]
DRP_MCB_ADDRESS bit 2MAIN[25][39]
DRP_MCB_ADDRESS bit 3MAIN[25][47]
DIFF_PHASE_DETECTORMAIN[27][63]
spartan6 IOI_SN enum MCB_MEM_PLL_POL_SEL
MISC_IOI.MEM_PLL_POL_SELMAIN[25][57]
INVERTED0
NOTINVERTED1

Bel wires

spartan6 IOI_SN bel wires
WirePins
IMUX_CLK[0]ILOGIC[1].CLKDIV, OLOGIC[1].CLKDIV, IODELAY[1].CLK
IMUX_CLK[1]ILOGIC[0].CLKDIV, OLOGIC[0].CLKDIV, IODELAY[0].CLK
IMUX_SR[0]OLOGIC[1].SR
IMUX_SR[1]OLOGIC[0].SR
IMUX_LOGICIN[1]IODELAY[1].CIN
IMUX_LOGICIN[2]IODELAY[1].CAL
IMUX_LOGICIN[3]IODELAY[0].CAL
IMUX_LOGICIN[5]IODELAY[0].CE
IMUX_LOGICIN[7]IODELAY[0].INC
IMUX_LOGICIN[8]OLOGIC[1].TRAIN
IMUX_LOGICIN[9]OLOGIC[0].TCE
IMUX_LOGICIN[12]OLOGIC[0].T3
IMUX_LOGICIN[14]OLOGIC[0].REV
IMUX_LOGICIN[15]OLOGIC[0].D1
IMUX_LOGICIN[16]OLOGIC[0].D2
IMUX_LOGICIN[17]OLOGIC[0].D3
IMUX_LOGICIN[19]ILOGIC[0].BITSLIP
IMUX_LOGICIN[20]ILOGIC[0].SR
IMUX_LOGICIN[23]OLOGIC[1].TCE
IMUX_LOGICIN[24]OLOGIC[1].T1
IMUX_LOGICIN[25]OLOGIC[1].T2
IMUX_LOGICIN[26]OLOGIC[1].T3
IMUX_LOGICIN[27]OLOGIC[1].T4
IMUX_LOGICIN[28]OLOGIC[0].TRAIN
IMUX_LOGICIN[29]OLOGIC[1].REV
IMUX_LOGICIN[30]OLOGIC[1].OCE
IMUX_LOGICIN[31]OLOGIC[1].D1
IMUX_LOGICIN[32]OLOGIC[1].D2
IMUX_LOGICIN[34]OLOGIC[1].D4
IMUX_LOGICIN[36]ILOGIC[1].SR
IMUX_LOGICIN[37]ILOGIC[1].REV
IMUX_LOGICIN[38]ILOGIC[1].CE0
IMUX_LOGICIN[39]OLOGIC[0].OCE
IMUX_LOGICIN[41]IODELAY[0].RST
IMUX_LOGICIN[42]OLOGIC[0].T2
IMUX_LOGICIN[44]OLOGIC[1].D3
IMUX_LOGICIN[45]OLOGIC[0].T1
IMUX_LOGICIN[47]IODELAY[1].CE
IMUX_LOGICIN[48]OLOGIC[0].D4
IMUX_LOGICIN[52]IODELAY[0].CIN
IMUX_LOGICIN[54]OLOGIC[0].T4
IMUX_LOGICIN[55]IODELAY[1].RST
IMUX_LOGICIN[57]ILOGIC[1].BITSLIP
IMUX_LOGICIN[58]IODELAY[1].INC
IMUX_LOGICIN[59]ILOGIC[0].REV
IMUX_LOGICIN[62]ILOGIC[0].CE0
OUT_BEL[0]ILOGIC[1].FABRICOUT
OUT_BEL[1]ILOGIC[1].Q1
OUT_BEL[2]ILOGIC[1].Q2
OUT_BEL[3]ILOGIC[1].Q3
OUT_BEL[4]ILOGIC[1].Q4
OUT_BEL[5]ILOGIC[1].INCDEC
OUT_BEL[6]ILOGIC[1].VALID
OUT_BEL[7]ILOGIC[0].FABRICOUT
OUT_BEL[8]ILOGIC[0].Q1
OUT_BEL[9]ILOGIC[0].Q2
OUT_BEL[10]ILOGIC[0].Q3
OUT_BEL[11]ILOGIC[0].Q4
OUT_BEL[12]IODELAY[1].RCLK
OUT_BEL[13]IODELAY[0].RCLK
OUT_BEL[14]IODELAY[1].BUSY
OUT_BEL[15]IODELAY[0].BUSY
OUT_BEL[16]IODELAY[1].LOAD
OUT_BEL[17]IODELAY[0].LOAD
OUT_CLKPAD_DFB[0]ILOGIC[0].DFB
OUT_CLKPAD_DFB[1]ILOGIC[1].DFB
OUT_CLKPAD_CFB0[0]ILOGIC[0].CFB0
OUT_CLKPAD_CFB0[1]ILOGIC[1].CFB0
OUT_CLKPAD_CFB1[0]ILOGIC[0].CFB1
OUT_CLKPAD_CFB1[1]ILOGIC[1].CFB1
OUT_CLKPAD_DQSPIODELAY[1].DQSOUTP
OUT_CLKPAD_DQSNIODELAY[1].DQSOUTN
IOI_IOCLK[0]IOI_DDR[0].CLK0
IOI_IOCLK[1]IOI_DDR[0].CLK1
IOI_IOCLK[3]IOI_DDR[1].CLK0
IOI_IOCLK[4]IOI_DDR[1].CLK1
OUT_DDR_IOCLK[0]IOI_DDR[0].CLK
OUT_DDR_IOCLK[1]IOI_DDR[1].CLK
OUT_DDR_IOCE[0]IOI_DDR[0].IOCE
OUT_DDR_IOCE[1]IOI_DDR[1].IOCE
IMUX_ILOGIC_CLK[0]ILOGIC[0].CLK
IMUX_ILOGIC_CLK[1]ILOGIC[1].CLK
IMUX_OLOGIC_CLK[0]OLOGIC[0].CLK
IMUX_OLOGIC_CLK[1]OLOGIC[1].CLK
IMUX_IODELAY_IOCLK[0]IODELAY[0].IOCLK
IMUX_IODELAY_IOCLK[1]IODELAY[1].IOCLK
IMUX_ILOGIC_IOCE[0]ILOGIC[0].IOCE
IMUX_ILOGIC_IOCE[1]ILOGIC[1].IOCE
IMUX_OLOGIC_IOCE[0]OLOGIC[0].IOCE
IMUX_OLOGIC_IOCE[1]OLOGIC[1].IOCE

Bitstream

spartan6 IOI_SN rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: FFI_LATCH - IODELAY[0]: ODELAY_VALUE_N bit 7 - - MISC_IOI: DIFF_PHASE_DETECTOR IODELAY[0]: CAL_DELAY_MAX bit 0 -
B62 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! FFI_SR_SYNC - IODELAY[0]: IDELAY_VALUE_N bit 7 - - - IODELAY[0]: CAL_DELAY_MAX bit 1 IOI_INT: mux IMUX_ILOGIC_IOCE[0] bit 1
B61 - - - - - - - - - - - - - - - - - - - - - - - IOI_INT: mux IMUX_OLOGIC_IOCE[0] bit 1 IODELAY[0]: ODELAY_VALUE_N bit 6 - - - IODELAY[0]: CAL_DELAY_MAX bit 2 IOI_INT: mux IMUX_ILOGIC_IOCE[0] bit 0
B60 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: DDR IOI_INT: mux IMUX_OLOGIC_IOCE[0] bit 0 IODELAY[0]: IDELAY_VALUE_N bit 6 - - - IODELAY[0]: CAL_DELAY_MAX bit 3 IOI_INT: mux IMUX_ILOGIC_IOCE[0] bit 2
B59 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: FFI_REV_ENABLE IOI_INT: mux IMUX_OLOGIC_IOCE[0] bit 2 IODELAY[0]: ODELAY_VALUE_N bit 5 - - - IODELAY[0]: CAL_DELAY_MAX bit 4 IODELAY[0]: ODATAIN_ENABLE
B58 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: MUX_SR bit 0 IODELAY[0]: CIN_ENABLE bit 2 IODELAY[0]: IDELAY_VALUE_N bit 5 - - - IODELAY[0]: CAL_DELAY_MAX bit 5 ILOGIC[0]: MUX_TSBYPASS bit 0
B57 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! FFI_CE_ENABLE IODELAY[0]: CIN_ENABLE bit 1 IODELAY[0]: ODELAY_VALUE_N bit 4 MISC_IOI: MEM_PLL_POL_SEL bit 0 - - IODELAY[0]: CAL_DELAY_MAX bit 6 ILOGIC[0]: ! I_DELAY_ENABLE
B56 - - - - - - - - - - - - - - - - - - - - - - - IODELAY[0]: DELAYCHAIN_OSC IODELAY[0]: IDELAY_VALUE_N bit 4 MISC_IOI: MEM_PLL_DIV_EN - - IODELAY[0]: CAL_DELAY_MAX bit 7 IODELAY[0]: MODE bit 3
B55 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: FFI_SRVAL bit 0 IODELAY[0]: MODE bit 2 IODELAY[0]: IDELAY_VALUE_N bit 3 IODELAY[0]: DIFF_PHASE_DETECTOR - ILOGIC[1]: MUX_Q4 bit 0 ILOGIC[0]: ! FFI_DELAY_ENABLE IODELAY[0]: DRP06 bit 4 IOI_DDR[0]: ALIGNMENT bit 0
B54 - - - - - - - - - - - - - - - - - - - - - - - IODELAY[0]: IDELAY_MODE bit 1 IODELAY[0]: ODELAY_VALUE_N bit 3 IODELAY[0]: DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB bit 1 - ILOGIC[1]: MUX_Q4 bit 1 IODELAY[0]: LUMPED_DELAY_SELECT IODELAY[0]: DRP07 bit 4 IOI_DDR[0]: ALIGNMENT bit 1
B53 - - - - - - - - - - - - - - - - - - - - - - - IOI_INT: mux IOI_IOCE[1] bit 2 IODELAY[0]: IDELAY_VALUE_N bit 2 - - ILOGIC[1]: MUX_Q3 bit 1 IODELAY[0]: DRP06 bit 3 IODELAY[0]: DELAY_SRC bit 1 IOI_INT: mux IOI_IOCE[0] bit 2
B52 - - - - - - - - - - - - - - - - - - - - - - IODELAY[0]: IDELAY_FIXED IOI_INT: mux IOI_IOCE[1] bit 1 IODELAY[0]: ODELAY_VALUE_N bit 2 - - ILOGIC[1]: MUX_Q3 bit 0 IODELAY[0]: LUMPED_DELAY IODELAY[0]: DRP07 bit 3 IOI_INT: mux IOI_IOCE[0] bit 1
B51 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ROW2_CLK_ENABLE IOI_INT: mux IOI_IOCE[1] bit 0 IODELAY[0]: IDELAY_VALUE_N bit 1 IODELAY[0]: TEST_NCOUNTER - ILOGIC[1]: MUX_Q2 bit 0 IODELAY[0]: DRP07 bit 2 IODELAY[0]: IODELAY_CHANGE bit 0 -
B50 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ROW1_CLK_ENABLE IOI_INT: mux IOI_OCLK[0] bit 2 IODELAY[0]: ODELAY_VALUE_N bit 1 - - ILOGIC[1]: MUX_Q2 bit 1 IODELAY[0]: DRP06 bit 2 IODELAY[0]: DELAY_SRC bit 0 IOI_INT: mux IOI_IOCE[0] bit 0
B49 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ROW3_CLK_ENABLE IOI_INT: mux IOI_OCLK[0] bit 3 IODELAY[0]: IDELAY_VALUE_N bit 0 IODELAY[0]: TEST_PCOUNTER - ILOGIC[1]: MUX_Q1 bit 1 OLOGIC[0]: MUX_O bit 0 IODELAY[0]: DRP06 bit 5 IOI_INT: mux IOI_ICLK[0] bit 2
B48 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ROW4_CLK_ENABLE IOI_INT: mux IOI_OCLK[0] bit 0 IODELAY[0]: ODELAY_VALUE_N bit 0 - OLOGIC[1]: MUX_TRAIN bit 1 ILOGIC[1]: MUX_Q1 bit 0 IODELAY[0]: DRP07 bit 5 IOI_INT: mux IOI_ICLK[0] bit 3
B47 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ROW4_CLK_ENABLE IOI_INT: mux IOI_ICLK[0] bit 0 IODELAY[0]: ODELAY_VALUE_P bit 0 MISC_IOI: DRP_MCB_ADDRESS bit 3 OLOGIC[0]: MUX_TRAIN bit 1 ILOGIC[0]: MUX_Q1 bit 0 IODELAY[0]: DRP06 bit 1 -
B46 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ROW3_CLK_ENABLE IOI_INT: mux IOI_ICLK[0] bit 1 IODELAY[0]: IDELAY_VALUE_P bit 0 MISC_IOI: DRP_FROM_MCB OLOGIC[0]: CASCADE_ENABLE ILOGIC[0]: MUX_Q1 bit 1 IODELAY[0]: DRP07 bit 1 IODELAY[0]: COUNTER_WRAPAROUND bit 0 -
B45 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ROW1_CLK_ENABLE IOI_INT: mux IOI_OCLK[0] bit 1 IODELAY[0]: ODELAY_VALUE_P bit 1 - OLOGIC[0]: MUX_TRAIN bit 0 ILOGIC[0]: MUX_Q2 bit 1 IODELAY[0]: PLUS1 IODELAY[0]: DRP06 bit 0 IODELAY[0]: TEST_GLITCH_FILTER
B44 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ROW2_CLK_ENABLE IODELAY[0]: IDELAY_MODE bit 0 IODELAY[0]: IDELAY_VALUE_P bit 1 IODELAY[0]: DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB bit 0 OLOGIC[1]: MUX_TRAIN bit 0 ILOGIC[0]: MUX_Q2 bit 0 IODELAY[0]: IDELAY_FROM_HALF_MAX IODELAY[0]: DRP07 bit 0 IODELAY[0]: MODE bit 1
B43 - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: MUX_D bit 1 IODELAY[0]: ODELAY_VALUE_P bit 2 MISC_IOI: ENFFSCAN_DRP bit 0 IOI_INT: mux IMUX_ILOGIC_CLK[1] bit 1 ILOGIC[0]: MUX_Q3 bit 0 OLOGIC[0]: MUX_OCE bit 0 IODELAY[0]: DRP06 bit 7 -
B42 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: FFI_SR_ENABLE ILOGIC[0]: MUX_D bit 0 IODELAY[0]: IDELAY_VALUE_P bit 2 - IOI_INT: mux IMUX_ILOGIC_CLK[1] bit 0 ILOGIC[0]: MUX_Q3 bit 1 IODELAY[0]: DRP07 bit 7 IODELAY[0]: MODE bit 0
B41 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: FFI_INIT bit 0 IODELAY[0]: CIN_ENABLE bit 0 IODELAY[0]: ODELAY_VALUE_P bit 3 - IOI_INT: mux IMUX_ILOGIC_CLK[0] bit 1 ILOGIC[0]: MUX_Q4 bit 1 OLOGIC[0]: MUX_T bit 0 IODELAY[0]: DRP06 bit 6 IOI_DDR[0]: ENABLE bit 1
B40 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: DDR IOI_INT: mux IOI_IOCLK[2] bit 1 IODELAY[0]: IDELAY_VALUE_P bit 3 - IOI_INT: mux IMUX_ILOGIC_CLK[0] bit 0 ILOGIC[0]: MUX_Q4 bit 0 IODELAY[0]: DRP07 bit 6 IOI_DDR[0]: ENABLE bit 0
B39 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: FFI_SR_ENABLE IOI_INT: mux IOI_IOCLK[2] bit 0 IODELAY[0]: IDELAY_VALUE_P bit 4 MISC_IOI: DRP_MCB_ADDRESS bit 2 IOI_INT: mux IMUX_OLOGIC_CLK[1] bit 1 ILOGIC[0]: DATA_WIDTH_RELOAD bit 1 IODELAY[0]: DRP_ADDR bit 0 IOI_INT: invert IOI_IOCLK_OPTINV[2] ← IOI_IOCLK[2]
B38 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: FFI_INIT bit 0 IOI_INT: invert IOI_IOCLK_OPTINV[1] ← IOI_IOCLK[1] IODELAY[0]: ODELAY_VALUE_P bit 4 - IOI_INT: mux IMUX_OLOGIC_CLK[1] bit 0 ILOGIC[0]: DATA_WIDTH_RELOAD bit 0 IODELAY[0]: DRP_ADDR bit 1 IOI_INT: invert IOI_IOCLK_OPTINV[0] ← IOI_IOCLK[0]
B37 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: FFI_SRVAL bit 0 IOI_INT: mux IOI_IOCLK[1] bit 1 IODELAY[0]: IDELAY_VALUE_P bit 5 - IOI_INT: mux IMUX_OLOGIC_CLK[0] bit 1 ILOGIC[1]: DATA_WIDTH_RELOAD bit 2 IODELAY[0]: DRP_ADDR bit 2 IOI_INT: mux IOI_IOCLK[0] bit 0
B36 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: MUX_SR bit 0 IOI_INT: mux IOI_IOCLK[1] bit 4 IODELAY[0]: ODELAY_VALUE_P bit 5 - IOI_INT: mux IMUX_OLOGIC_CLK[0] bit 0 ILOGIC[1]: DATA_WIDTH_RELOAD bit 1 IODELAY[0]: DRP_ADDR bit 3 IOI_INT: mux IOI_IOCLK[0] bit 4
B35 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: FFI_REV_ENABLE IOI_INT: mux IOI_IOCLK[1] bit 0 IODELAY[0]: IDELAY_VALUE_P bit 6 - ILOGIC[1]: ENABLE OLOGIC[1]: MUX_IN_O bit 0 - IOI_INT: mux IOI_IOCLK[0] bit 1
B34 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: CASCADE_ENABLE - IODELAY[0]: ODELAY_VALUE_P bit 6 - - OLOGIC[1]: FFO_RANK1_BYPASS - -
B33 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: FFI_LATCH IOI_INT: mux IOI_IOCLK[1] bit 2 IODELAY[0]: IDELAY_VALUE_P bit 7 - - OLOGIC[1]: TRAIN_PATTERN bit 0 - IOI_INT: mux IOI_IOCLK[0] bit 2
B32 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! FFI_SR_SYNC IOI_INT: mux IOI_IOCLK[1] bit 3 IODELAY[0]: ODELAY_VALUE_P bit 7 - ILOGIC[0]: ENABLE OLOGIC[1]: TRAIN_PATTERN bit 1 IODELAY[0]: DRP_ADDR bit 4 IOI_INT: mux IOI_IOCLK[0] bit 3
B31 - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! FFI_CE_ENABLE IOI_INT: mux IOI_IOCLK[4] bit 3 IODELAY[1]: ODELAY_VALUE_P bit 7 - OLOGIC[1]: ENABLE OLOGIC[1]: TRAIN_PATTERN bit 2 IODELAY[1]: DRP_ADDR bit 4 IOI_INT: mux IOI_IOCLK[3] bit 3
B30 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: CASCADE_ENABLE IOI_INT: mux IOI_IOCLK[4] bit 2 IODELAY[1]: IDELAY_VALUE_P bit 7 - - OLOGIC[1]: TRAIN_PATTERN bit 3 - IOI_INT: mux IOI_IOCLK[3] bit 2
B29 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFO_LATCH - IODELAY[1]: ODELAY_VALUE_P bit 6 - - OLOGIC[1]: DDR_OPPOSITE_EDGE - -
B28 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFO_SR_ENABLE IOI_INT: mux IOI_IOCLK[4] bit 0 IODELAY[1]: IDELAY_VALUE_P bit 6 MISC_IOI: DRP_ENABLE OLOGIC[0]: ENABLE OLOGIC[1]: MUX_IN_T bit 0 - IOI_INT: mux IOI_IOCLK[3] bit 1
B27 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFO_REV_ENABLE IOI_INT: mux IOI_IOCLK[4] bit 4 IODELAY[1]: ODELAY_VALUE_P bit 5 - OLOGIC[0]: IOCE_ENABLE OLOGIC[1]: FFO_CE_ENABLE IODELAY[1]: DRP_ADDR bit 3 IOI_INT: mux IOI_IOCLK[3] bit 4
B26 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: ! FFO_SR_SYNC IOI_INT: mux IOI_IOCLK[4] bit 1 IODELAY[1]: IDELAY_VALUE_P bit 5 MISC_IOI: DRP_MCB_ADDRESS bit 1 ILOGIC[0]: IOCE_ENABLE OLOGIC[1]: FFO_CE_OR_DDR IODELAY[1]: DRP_ADDR bit 2 IOI_INT: mux IOI_IOCLK[3] bit 0
B25 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFO_INIT bit 0 IOI_INT: invert IOI_IOCLK_OPTINV[4] ← IOI_IOCLK[4] IODELAY[1]: ODELAY_VALUE_P bit 4 - OLOGIC[1]: IOCE_ENABLE OLOGIC[1]: FFO_RANK1_CLK_ENABLE IODELAY[1]: DRP_ADDR bit 1 IOI_INT: invert IOI_IOCLK_OPTINV[3] ← IOI_IOCLK[3]
B24 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFO_SRVAL bit 0 IOI_INT: mux IOI_IOCLK[5] bit 0 IODELAY[1]: IDELAY_VALUE_P bit 4 MISC_IOI: DRP_MCB_ADDRESS bit 0 ILOGIC[1]: IOCE_ENABLE OLOGIC[1]: FFO_RANK2_CLK_ENABLE IODELAY[1]: DRP_ADDR bit 0 IOI_INT: invert IOI_IOCLK_OPTINV[5] ← IOI_IOCLK[5]
B23 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFT_SRVAL bit 0 IOI_INT: mux IOI_IOCLK[5] bit 1 IODELAY[1]: IDELAY_VALUE_P bit 3 - ILOGIC[0]: DATA_WIDTH_START bit 1 OLOGIC[1]: FFT_RANK2_CLK_ENABLE IODELAY[1]: DRP07 bit 6 IOI_DDR[1]: ENABLE bit 1
B22 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFT_INIT bit 0 IODELAY[1]: CIN_ENABLE bit 2 IODELAY[1]: ODELAY_VALUE_P bit 3 - ILOGIC[0]: BITSLIP_ENABLE OLOGIC[1]: FFT_RANK1_CLK_ENABLE OLOGIC[1]: MUX_T bit 0 IODELAY[1]: DRP06 bit 6 IOI_DDR[1]: ENABLE bit 0
B21 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: ! FFT_SR_SYNC - IODELAY[1]: IDELAY_VALUE_P bit 2 - ILOGIC[0]: DATA_WIDTH_START bit 0 OLOGIC[1]: FFT_CE_OR_DDR IODELAY[1]: DRP07 bit 7 IODELAY[1]: MODE bit 1
B20 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFT_REV_ENABLE - IODELAY[1]: ODELAY_VALUE_P bit 2 IODELAY[1]: DIFF_PHASE_DETECTOR ILOGIC[1]: DATA_WIDTH_START bit 0 OLOGIC[1]: FFT_CE_ENABLE OLOGIC[1]: MUX_OCE bit 0 IODELAY[1]: DRP06 bit 7 -
B19 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFT_SR_ENABLE IODELAY[1]: IDELAY_MODE bit 1 IODELAY[1]: IDELAY_VALUE_P bit 1 IODELAY[1]: DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB bit 1 ILOGIC[1]: DATA_WIDTH_START bit 1 OLOGIC[1]: FFT_RANK1_BYPASS IODELAY[1]: IDELAY_FROM_HALF_MAX IODELAY[1]: DRP07 bit 0 IODELAY[1]: MODE bit 0
B18 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: FFT_LATCH IOI_INT: mux IOI_OCLK[1] bit 1 IODELAY[1]: ODELAY_VALUE_P bit 1 - ILOGIC[1]: DATA_WIDTH_START bit 2 ILOGIC[1]: DATA_WIDTH_RELOAD bit 0 IODELAY[1]: EVENT_SEL bit 0 IODELAY[1]: DRP06 bit 0 IODELAY[1]: TEST_GLITCH_FILTER
B17 - - - - - - - - - - - - - - - - - - - - - - - IOI_INT: mux IOI_ICLK[1] bit 1 IODELAY[1]: IDELAY_VALUE_P bit 0 - ILOGIC[1]: BITSLIP_ENABLE OLOGIC[0]: TRAIN_PATTERN bit 1 IODELAY[1]: DRP07 bit 1 IODELAY[1]: COUNTER_WRAPAROUND bit 0 -
B16 - - - - - - - - - - - - - - - - - - - - - - IODELAY[1]: IDELAY_FIXED IOI_INT: mux IOI_ICLK[1] bit 0 IODELAY[1]: ODELAY_VALUE_P bit 0 - ILOGIC[1]: CASCADE_ENABLE OLOGIC[0]: TRAIN_PATTERN bit 0 IODELAY[1]: EVENT_SEL bit 1 IODELAY[1]: DRP06 bit 1 -
B15 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: MUX_SR bit 0 IOI_INT: mux IOI_OCLK[1] bit 0 IODELAY[1]: ODELAY_VALUE_N bit 0 - OLOGIC[1]: MISR_ENABLE_DATA OLOGIC[0]: FFO_RANK1_BYPASS IODELAY[1]: DRP07 bit 5 IOI_INT: mux IOI_ICLK[1] bit 3
B14 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: MUX_REV bit 0 IOI_INT: mux IOI_OCLK[1] bit 3 IODELAY[1]: IDELAY_VALUE_N bit 0 - OLOGIC[1]: MISR_ENABLE_CLK OLOGIC[0]: DDR_OPPOSITE_EDGE OLOGIC[1]: MUX_O bit 0 IODELAY[1]: DRP06 bit 5 IOI_INT: mux IOI_ICLK[1] bit 2
B13 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFO_LATCH IOI_INT: mux IOI_OCLK[1] bit 2 IODELAY[1]: ODELAY_VALUE_N bit 1 - OLOGIC[0]: MISR_ENABLE_CLK OLOGIC[0]: TRAIN_PATTERN bit 2 IODELAY[1]: DRP06 bit 2 IODELAY[1]: DELAY_SRC bit 0 IOI_INT: mux IOI_IOCE[2] bit 0
B12 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFO_SR_ENABLE IOI_INT: mux IOI_IOCE[3] bit 0 IODELAY[1]: IDELAY_VALUE_N bit 1 IODELAY[1]: TEST_NCOUNTER OLOGIC[0]: MISR_ENABLE_DATA OLOGIC[0]: MUX_IN_O bit 0 IODELAY[1]: DRP07 bit 2 IODELAY[1]: IODELAY_CHANGE bit 0 -
B11 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFO_REV_ENABLE IOI_INT: mux IOI_IOCE[3] bit 1 IODELAY[1]: ODELAY_VALUE_N bit 2 - OLOGIC[1]: MISR_RESET OLOGIC[0]: FFO_CE_ENABLE IODELAY[1]: LUMPED_DELAY IODELAY[1]: DRP07 bit 3 IOI_INT: mux IOI_IOCE[2] bit 1
B10 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFO_SR_SYNC IOI_INT: mux IOI_IOCE[3] bit 2 IODELAY[1]: IDELAY_VALUE_N bit 2 - OLOGIC[0]: MISR_RESET OLOGIC[0]: FFO_CE_OR_DDR IODELAY[1]: DRP06 bit 3 IODELAY[1]: DELAY_SRC bit 1 IOI_INT: mux IOI_IOCE[2] bit 2
B9 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFO_INIT bit 0 IODELAY[1]: IDELAY_MODE bit 0 IODELAY[1]: ODELAY_VALUE_N bit 3 IODELAY[1]: DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB bit 0 MISC_IOI: ENFFSCAN_DRP bit 1 OLOGIC[0]: FFO_RANK1_CLK_ENABLE IODELAY[1]: LUMPED_DELAY_SELECT IODELAY[1]: DRP07 bit 4 IOI_DDR[1]: ALIGNMENT bit 1
B8 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFO_SRVAL bit 0 IODELAY[1]: MODE bit 2 IODELAY[1]: IDELAY_VALUE_N bit 3 - - OLOGIC[0]: FFO_RANK2_CLK_ENABLE ILOGIC[1]: ! FFI_DELAY_ENABLE IODELAY[1]: DRP06 bit 4 IOI_DDR[1]: ALIGNMENT bit 0
B7 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFT_SRVAL bit 0 IODELAY[1]: DELAYCHAIN_OSC IODELAY[1]: IDELAY_VALUE_N bit 4 - - OLOGIC[0]: FFT_RANK2_CLK_ENABLE IODELAY[1]: CAL_DELAY_MAX bit 7 IODELAY[1]: MODE bit 3
B6 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFT_INIT bit 0 IODELAY[1]: CIN_ENABLE bit 1 IODELAY[1]: ODELAY_VALUE_N bit 4 - - OLOGIC[0]: FFT_RANK1_CLK_ENABLE IODELAY[1]: CAL_DELAY_MAX bit 6 ILOGIC[1]: ! I_DELAY_ENABLE
B5 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFT_SR_SYNC IODELAY[1]: CIN_ENABLE bit 0 IODELAY[1]: IDELAY_VALUE_N bit 5 - - OLOGIC[0]: FFT_CE_OR_DDR IODELAY[1]: CAL_DELAY_MAX bit 5 ILOGIC[1]: MUX_TSBYPASS bit 0
B4 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFT_REV_ENABLE IOI_INT: mux IMUX_OLOGIC_IOCE[1] bit 2 IODELAY[1]: ODELAY_VALUE_N bit 5 - - OLOGIC[0]: FFT_CE_ENABLE IODELAY[1]: CAL_DELAY_MAX bit 4 IODELAY[1]: ODATAIN_ENABLE
B3 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFT_SR_ENABLE IOI_INT: mux IMUX_OLOGIC_IOCE[1] bit 0 IODELAY[1]: IDELAY_VALUE_N bit 6 - IOI_INT: mux IMUX_IODELAY_IOCLK[0] bit 0 OLOGIC[0]: TRAIN_PATTERN bit 3 IODELAY[1]: CAL_DELAY_MAX bit 3 IOI_INT: mux IMUX_ILOGIC_IOCE[1] bit 2
B2 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: FFT_LATCH IOI_INT: mux IMUX_OLOGIC_IOCE[1] bit 1 IODELAY[1]: ODELAY_VALUE_N bit 6 - - OLOGIC[0]: MUX_IN_T bit 0 IODELAY[1]: CAL_DELAY_MAX bit 2 IOI_INT: mux IMUX_ILOGIC_IOCE[1] bit 0
B1 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MUX_SR bit 0 - IODELAY[1]: IDELAY_VALUE_N bit 7 - IOI_INT: mux IMUX_IODELAY_IOCLK[1] bit 0 OLOGIC[0]: FFT_RANK1_BYPASS IODELAY[1]: CAL_DELAY_MAX bit 1 IOI_INT: mux IMUX_ILOGIC_IOCE[1] bit 1
B0 - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MUX_REV bit 0 - IODELAY[1]: ODELAY_VALUE_N bit 7 IODELAY[1]: TEST_PCOUNTER - OLOGIC[0]: OUTPUT_MODE bit 0 IODELAY[1]: CAL_DELAY_MAX bit 0 -

Tile IOB

Cells: 1

Bels IOB

spartan6 IOB bel IOB pins
PinDirectionIOB[0]IOB[1]
IoutOUT_CLKPAD_I[0]OUT_CLKPAD_I[1]
spartan6 IOB bel IOB attribute bits
AttributeIOB[0]IOB[1]
PDRIVE bit 0!MAIN[0][0]!MAIN[0][64]
PDRIVE bit 1!MAIN[0][1]!MAIN[0][65]
PDRIVE bit 2MAIN[0][2]MAIN[0][66]
PDRIVE bit 3!MAIN[0][3]!MAIN[0][67]
PDRIVE bit 4MAIN[0][4]MAIN[0][68]
PDRIVE bit 5MAIN[0][5]MAIN[0][69]
PTERM bit 0MAIN[0][8]MAIN[0][72]
PTERM bit 1MAIN[0][9]MAIN[0][73]
PTERM bit 2MAIN[0][10]MAIN[0][74]
PTERM bit 3MAIN[0][11]MAIN[0][75]
PTERM bit 4MAIN[0][12]MAIN[0][76]
PTERM bit 5MAIN[0][13]MAIN[0][77]
NDRIVE bit 0MAIN[0][16]MAIN[0][80]
NDRIVE bit 1MAIN[0][17]MAIN[0][81]
NDRIVE bit 2!MAIN[0][18]!MAIN[0][82]
NDRIVE bit 3MAIN[0][19]MAIN[0][83]
NDRIVE bit 4MAIN[0][20]MAIN[0][84]
NDRIVE bit 5!MAIN[0][21]!MAIN[0][85]
NDRIVE bit 6MAIN[0][22]MAIN[0][86]
NTERM bit 0MAIN[0][24]MAIN[0][88]
NTERM bit 1MAIN[0][25]MAIN[0][89]
NTERM bit 2MAIN[0][26]MAIN[0][90]
NTERM bit 3MAIN[0][27]MAIN[0][91]
NTERM bit 4MAIN[0][28]MAIN[0][92]
NTERM bit 5MAIN[0][29]MAIN[0][93]
NTERM bit 6MAIN[0][30]MAIN[0][94]
TMLMAIN[0][15]MAIN[0][79]
PSLEW bit 0MAIN[0][32]MAIN[0][96]
PSLEW bit 1MAIN[0][33]MAIN[0][97]
PSLEW bit 2!MAIN[0][34]!MAIN[0][98]
PSLEW bit 3MAIN[0][35]MAIN[0][99]
NSLEW bit 0MAIN[0][36]MAIN[0][100]
NSLEW bit 1MAIN[0][37]MAIN[0][101]
NSLEW bit 2!MAIN[0][38]!MAIN[0][102]
NSLEW bit 3MAIN[0][39]MAIN[0][103]
DIFF_TERMMAIN[0][40]-
DIFF_OUTPUT_ENABLE-MAIN[0][104]
LVDS_GROUP bit 0-MAIN[0][105]
DIFF_MODE-[enum: IOB_DIFF_MODE]
PRE_EMPHASISMAIN[0][45]MAIN[0][109]
OUTPUT_LOW_VOLTAGEMAIN[0][46]MAIN[0][110]
PCI_CLAMPMAIN[0][47]MAIN[0][111]
PULL[enum: IOB_PULL][enum: IOB_PULL]
SUSPEND[enum: IOB_SUSPEND][enum: IOB_SUSPEND]
IBUF_MODE[enum: IOB_IBUF_MODE][enum: IOB_IBUF_MODE]
VREF_HVMAIN[0][59]MAIN[0][123]
PCI_INPUTMAIN[0][60]MAIN[0][124]
I_INVMAIN[0][61]MAIN[0][125]
VREFMAIN[0][62]-
OUTPUT_ENABLEMAIN[0][63]MAIN[0][127]
spartan6 IOB enum IOB_DIFF_MODE
IOB[1].DIFF_MODEMAIN[0][107]MAIN[0][106]
NONE00
LVDS01
TMDS10
spartan6 IOB enum IOB_PULL
IOB[0].PULLMAIN[0][50]MAIN[0][49]MAIN[0][48]
IOB[1].PULLMAIN[0][114]MAIN[0][113]MAIN[0][112]
NONE001
PULLUP011
PULLDOWN000
KEEPER101
spartan6 IOB enum IOB_SUSPEND
IOB[0].SUSPENDMAIN[0][55]MAIN[0][54]MAIN[0][53]MAIN[0][52]MAIN[0][51]
IOB[1].SUSPENDMAIN[0][119]MAIN[0][118]MAIN[0][117]MAIN[0][116]MAIN[0][115]
_3STATE00000
DRIVE_LAST_VALUE00001
_3STATE_PULLDOWN00010
_3STATE_PULLUP00100
_3STATE_KEEPER01000
_3STATE_OCT_ON10000
spartan6 IOB enum IOB_IBUF_MODE
IOB[0].IBUF_MODEMAIN[0][58]MAIN[0][57]MAIN[0][56]
IOB[1].IBUF_MODEMAIN[0][122]MAIN[0][121]MAIN[0][120]
NONE000
LOOPBACK_T001
LOOPBACK_O010
CMOS_VCCINT011
CMOS_VCCO100
VREF101
DIFF110
CMOS_VCCAUX111

Bel wires

spartan6 IOB bel wires
WirePins
OUT_CLKPAD_I[0]IOB[0].I
OUT_CLKPAD_I[1]IOB[1].I

Bitstream

spartan6 IOB rect MAIN
BitFrame
F0
B0 IOB[0]: ! PDRIVE bit 0
B1 IOB[0]: ! PDRIVE bit 1
B2 IOB[0]: PDRIVE bit 2
B3 IOB[0]: ! PDRIVE bit 3
B4 IOB[0]: PDRIVE bit 4
B5 IOB[0]: PDRIVE bit 5
B6 -
B7 -
B8 IOB[0]: PTERM bit 0
B9 IOB[0]: PTERM bit 1
B10 IOB[0]: PTERM bit 2
B11 IOB[0]: PTERM bit 3
B12 IOB[0]: PTERM bit 4
B13 IOB[0]: PTERM bit 5
B14 -
B15 IOB[0]: TML
B16 IOB[0]: NDRIVE bit 0
B17 IOB[0]: NDRIVE bit 1
B18 IOB[0]: ! NDRIVE bit 2
B19 IOB[0]: NDRIVE bit 3
B20 IOB[0]: NDRIVE bit 4
B21 IOB[0]: ! NDRIVE bit 5
B22 IOB[0]: NDRIVE bit 6
B23 -
B24 IOB[0]: NTERM bit 0
B25 IOB[0]: NTERM bit 1
B26 IOB[0]: NTERM bit 2
B27 IOB[0]: NTERM bit 3
B28 IOB[0]: NTERM bit 4
B29 IOB[0]: NTERM bit 5
B30 IOB[0]: NTERM bit 6
B31 -
B32 IOB[0]: PSLEW bit 0
B33 IOB[0]: PSLEW bit 1
B34 IOB[0]: ! PSLEW bit 2
B35 IOB[0]: PSLEW bit 3
B36 IOB[0]: NSLEW bit 0
B37 IOB[0]: NSLEW bit 1
B38 IOB[0]: ! NSLEW bit 2
B39 IOB[0]: NSLEW bit 3
B40 IOB[0]: DIFF_TERM
B41 -
B42 -
B43 -
B44 -
B45 IOB[0]: PRE_EMPHASIS
B46 IOB[0]: OUTPUT_LOW_VOLTAGE
B47 IOB[0]: PCI_CLAMP
B48 IOB[0]: PULL bit 0
B49 IOB[0]: PULL bit 1
B50 IOB[0]: PULL bit 2
B51 IOB[0]: SUSPEND bit 0
B52 IOB[0]: SUSPEND bit 1
B53 IOB[0]: SUSPEND bit 2
B54 IOB[0]: SUSPEND bit 3
B55 IOB[0]: SUSPEND bit 4
B56 IOB[0]: IBUF_MODE bit 0
B57 IOB[0]: IBUF_MODE bit 1
B58 IOB[0]: IBUF_MODE bit 2
B59 IOB[0]: VREF_HV
B60 IOB[0]: PCI_INPUT
B61 IOB[0]: I_INV
B62 IOB[0]: VREF
B63 IOB[0]: OUTPUT_ENABLE
B64 IOB[1]: ! PDRIVE bit 0
B65 IOB[1]: ! PDRIVE bit 1
B66 IOB[1]: PDRIVE bit 2
B67 IOB[1]: ! PDRIVE bit 3
B68 IOB[1]: PDRIVE bit 4
B69 IOB[1]: PDRIVE bit 5
B70 -
B71 -
B72 IOB[1]: PTERM bit 0
B73 IOB[1]: PTERM bit 1
B74 IOB[1]: PTERM bit 2
B75 IOB[1]: PTERM bit 3
B76 IOB[1]: PTERM bit 4
B77 IOB[1]: PTERM bit 5
B78 -
B79 IOB[1]: TML
B80 IOB[1]: NDRIVE bit 0
B81 IOB[1]: NDRIVE bit 1
B82 IOB[1]: ! NDRIVE bit 2
B83 IOB[1]: NDRIVE bit 3
B84 IOB[1]: NDRIVE bit 4
B85 IOB[1]: ! NDRIVE bit 5
B86 IOB[1]: NDRIVE bit 6
B87 -
B88 IOB[1]: NTERM bit 0
B89 IOB[1]: NTERM bit 1
B90 IOB[1]: NTERM bit 2
B91 IOB[1]: NTERM bit 3
B92 IOB[1]: NTERM bit 4
B93 IOB[1]: NTERM bit 5
B94 IOB[1]: NTERM bit 6
B95 -
B96 IOB[1]: PSLEW bit 0
B97 IOB[1]: PSLEW bit 1
B98 IOB[1]: ! PSLEW bit 2
B99 IOB[1]: PSLEW bit 3
B100 IOB[1]: NSLEW bit 0
B101 IOB[1]: NSLEW bit 1
B102 IOB[1]: ! NSLEW bit 2
B103 IOB[1]: NSLEW bit 3
B104 IOB[1]: DIFF_OUTPUT_ENABLE
B105 IOB[1]: LVDS_GROUP bit 0
B106 IOB[1]: DIFF_MODE bit 0
B107 IOB[1]: DIFF_MODE bit 1
B108 -
B109 IOB[1]: PRE_EMPHASIS
B110 IOB[1]: OUTPUT_LOW_VOLTAGE
B111 IOB[1]: PCI_CLAMP
B112 IOB[1]: PULL bit 0
B113 IOB[1]: PULL bit 1
B114 IOB[1]: PULL bit 2
B115 IOB[1]: SUSPEND bit 0
B116 IOB[1]: SUSPEND bit 1
B117 IOB[1]: SUSPEND bit 2
B118 IOB[1]: SUSPEND bit 3
B119 IOB[1]: SUSPEND bit 4
B120 IOB[1]: IBUF_MODE bit 0
B121 IOB[1]: IBUF_MODE bit 1
B122 IOB[1]: IBUF_MODE bit 2
B123 IOB[1]: VREF_HV
B124 IOB[1]: PCI_INPUT
B125 IOB[1]: I_INV
B126 -
B127 IOB[1]: OUTPUT_ENABLE

Tables

Table IOB_DATA

spartan6 table IOB_DATA
Row PDRIVE NDRIVE_2V5 NDRIVE_3V3 PSLEW NSLEW
OFF 0b000000 0b0000000 0b0000000 0b0000 0b0000
IN_TERM - - - 0b0100 0b0100
SLEW_SLOW - - - 0b0100 0b0100
SLEW_FAST - - - 0b1000 0b1000
SLEW_QUIETIO - - - 0b0010 0b0010
LVCMOS12_2 0b001001 0b0001001 0b0000111 - -
LVCMOS12_4 0b010010 0b0010010 0b0001110 - -
LVCMOS12_6 0b011010 0b0011011 0b0010101 - -
LVCMOS12_8 0b100011 0b0100100 0b0011100 - -
LVCMOS12_12 0b110100 0b0110101 0b0101010 - -
LVCMOS15_2 0b000110 0b0001010 0b0001000 - -
LVCMOS15_4 0b001100 0b0010100 0b0010000 - -
LVCMOS15_6 0b010010 0b0011110 0b0011000 - -
LVCMOS15_8 0b011000 0b0101000 0b0100000 - -
LVCMOS15_12 0b100100 0b0111100 0b0101111 - -
LVCMOS15_16 0b101111 0b1001111 0b0111111 - -
LVCMOS18_2 0b000100 0b0001001 0b0000111 - -
LVCMOS18_4 0b001000 0b0010001 0b0001101 - -
LVCMOS18_6 0b001100 0b0011001 0b0010011 - -
LVCMOS18_8 0b010000 0b0100001 0b0011001 - -
LVCMOS18_12 0b010111 0b0110001 0b0100110 - -
LVCMOS18_16 0b011111 0b1000001 0b0110010 - -
LVCMOS18_24 0b101110 0b1100001 0b1001011 - -
LVCMOS25_2 0b000011 0b0001001 0b0000111 - -
LVCMOS25_4 0b000110 0b0010010 0b0001110 - -
LVCMOS25_6 0b001001 0b0011011 0b0010101 - -
LVCMOS25_8 0b001011 0b0100100 0b0011100 - -
LVCMOS25_12 0b010001 0b0110101 0b0101010 - -
LVCMOS25_16 0b010110 0b1000111 0b0111000 - -
LVCMOS25_24 0b100001 0b1101010 0b1010011 - -
LVCMOS33_2 0b000011 0b0001001 0b0000111 - -
LVCMOS33_4 0b000101 0b0010010 0b0001110 - -
LVCMOS33_6 0b000111 0b0011011 0b0010101 - -
LVCMOS33_8 0b001001 0b0100100 0b0011100 - -
LVCMOS33_12 0b001101 0b0110101 0b0101010 - -
LVCMOS33_16 0b010010 0b1000111 0b0111000 - -
LVCMOS33_24 0b011010 0b1101010 0b1010011 - -
LVTTL_2 0b000010 0b0001001 0b0000111 - -
LVTTL_4 0b000100 0b0010010 0b0001110 - -
LVTTL_6 0b000101 0b0011011 0b0010101 - -
LVTTL_8 0b000111 0b0100100 0b0011100 - -
LVTTL_12 0b001010 0b0110101 0b0101010 - -
LVTTL_16 0b001101 0b1000111 0b0111000 - -
LVTTL_24 0b010011 0b1101010 0b1010011 - -
MOBILE_DDR 0b010000 0b0011011 0b0010100 0b1000 0b1000
SDIO 0b001001 0b0100100 0b0011100 0b0100 0b0100
I2C 0b000000 0b0010000 0b0001000 0b0100 0b0100
SMBUS 0b000000 0b0010010 0b0001110 0b0100 0b0100
PCI33_3 0b011001 - 0b1010000 0b0001 0b0001
PCI66_3 0b011001 - 0b1010000 0b0001 0b0001
DIFF_MOBILE_DDR 0b001000 0b0010001 0b0001101 0b1000 0b1000
BLVDS_25 0b011111 0b1111111 0b1111111 0b1000 0b1000
DISPLAY_PORT 0b001000 0b0111000 0b0011100 0b1000 0b1000
TML_33 0b000110 - 0b0000000 0b0100 0b0100
HSTL_I 0b010110 0b0100100 0b0011100 0b1000 0b1000
HSTL_II 0b101011 0b1000111 0b0111000 0b1000 0b1000
HSTL_III 0b010110 0b1101010 0b1010011 0b1000 0b1000
HSTL_I_18 0b010110 0b0110001 0b0100110 0b1000 0b1000
HSTL_II_18 0b101100 0b1100010 0b1001100 0b1000 0b1000
HSTL_III_18 0b010110 0b1111111 0b1101000 0b1000 0b1000
SSTL15_II 0b101101 0b1010000 0b1000000 0b1111 0b1111
SSTL18_I 0b001110 0b0011110 0b0011000 0b1000 0b1000
SSTL18_II 0b100101 0b1010011 0b1000010 0b1000 0b1000
SSTL2_I 0b001001 0b0011100 0b0010110 0b1000 0b1000
SSTL2_II 0b011001 0b1001111 0b0111110 0b1000 0b1000
SSTL3_I 0b000101 0b0011000 0b0010010 0b1000 0b1000
SSTL3_II 0b001010 0b0111100 0b0101110 0b1000 0b1000
UNTUNED_25_1V2 0b100010 0b0100100 0b0011111 - -
UNTUNED_25_1V5 0b011010 0b0100101 0b0011111 - -
UNTUNED_25_1V8 0b010101 0b0100110 0b0100000 - -
UNTUNED_25_2V5 0b010000 0b0101001 0b0100010 - -
UNTUNED_25_3V3 0b001101 0b0101101 0b0100100 - -
UNTUNED_50_1V2 0b010001 0b0010010 0b0001111 - -
UNTUNED_50_1V5 0b001101 0b0010010 0b0001111 - -
UNTUNED_50_1V8 0b001010 0b0010011 0b0010000 - -
UNTUNED_50_2V5 0b001000 0b0010100 0b0010001 - -
UNTUNED_50_3V3 0b000110 0b0010110 0b0010010 - -
UNTUNED_75_1V2 0b001011 0b0001100 0b0001010 - -
UNTUNED_75_1V5 0b001000 0b0001100 0b0001010 - -
UNTUNED_75_1V8 0b000111 0b0001100 0b0001010 - -
UNTUNED_75_2V5 0b000101 0b0001101 0b0001011 - -
UNTUNED_75_3V3 0b000100 0b0001111 0b0001100 - -

Table IOB_TERM

spartan6 table IOB_TERM
Row PTERM_2V5 PTERM_3V3 NTERM_2V5 NTERM_3V3
OFF 0b000000 0b000000 0b0000000 0b0000000
TML_33 - 0b000110 - 0b0000000
UNTUNED_SPLIT_25_1V2 0b101011 0b101000 0b0011111 0b0011010
UNTUNED_SPLIT_25_1V5 0b100000 0b011101 0b0100100 0b0011011
UNTUNED_SPLIT_25_1V8 0b011011 0b011000 0b0101011 0b0011101
UNTUNED_SPLIT_25_2V5 0b011000 0b010100 0b1000000 0b0101001
UNTUNED_SPLIT_25_3V3 0b011000 0b010100 0b1011011 0b0111010
UNTUNED_SPLIT_50_1V2 0b010101 0b010100 0b0001111 0b0001100
UNTUNED_SPLIT_50_1V5 0b010000 0b001111 0b0010010 0b0001101
UNTUNED_SPLIT_50_1V8 0b001110 0b001100 0b0010101 0b0001110
UNTUNED_SPLIT_50_2V5 0b001100 0b001010 0b0100000 0b0010011
UNTUNED_SPLIT_50_3V3 0b001100 0b001010 0b0101110 0b0011100
UNTUNED_SPLIT_75_1V2 0b001110 0b001110 0b0001010 0b0001001
UNTUNED_SPLIT_75_1V5 0b001010 0b001001 0b0001011 0b0001001
UNTUNED_SPLIT_75_1V8 0b001001 0b001000 0b0001110 0b0001010
UNTUNED_SPLIT_75_2V5 0b001000 0b000111 0b0010100 0b0001101
UNTUNED_SPLIT_75_3V3 0b001000 0b000111 0b0011110 0b0010011

Table LVDSBIAS

spartan6 table LVDSBIAS
Row LVDSBIAS
OFF 0b000000000000
LVDS_25 0b100010111001
LVDS_33 0b100010111001
MINI_LVDS_25 0b011111010001
MINI_LVDS_33 0b011111010001
RSDS_25 0b100010010101
RSDS_33 0b100010010101
PPDS_25 0b010000110111
PPDS_33 0b010000110111
TMDS_33 0b101001100101
TML_33 0b101001111111