Input/Output

Tile IOI_WE

Cells: 1

Bel ILOGIC[0]

spartan6 IOI_WE bel ILOGIC[0]
Pin	Direction	Wires
BITSLIP	input	IMUX_LOGICIN[19]
CE0	input	IMUX_LOGICIN[62]
CLKDIV	input	IMUX_CLK[1]
FABRICOUT	output	OUT_TMIN[7]
Q1	output	OUT_TMIN[8]
Q2	output	OUT_TMIN[9]
Q3	output	OUT_TMIN[10]
Q4	output	OUT_TMIN[11]
REV	input	IMUX_LOGICIN[59]
SR_INT	input	IMUX_LOGICIN[20]

Bel ILOGIC[1]

spartan6 IOI_WE bel ILOGIC[1]
Pin	Direction	Wires
BITSLIP	input	IMUX_LOGICIN[57]
CE0	input	IMUX_LOGICIN[38]
CLKDIV	input	IMUX_CLK[0]
FABRICOUT	output	OUT_TMIN[0]
INCDEC	output	OUT_TMIN[5]
Q1	output	OUT_TMIN[1]
Q2	output	OUT_TMIN[2]
Q3	output	OUT_TMIN[3]
Q4	output	OUT_TMIN[4]
REV	input	IMUX_LOGICIN[37]
SR_INT	input	IMUX_LOGICIN[36]
VALID	output	OUT_TMIN[6]

Bel OLOGIC[0]

spartan6 IOI_WE bel OLOGIC[0]
Pin	Direction	Wires
CLKDIV	input	IMUX_CLK[1]
D1	input	IMUX_LOGICIN[15]
D2	input	IMUX_LOGICIN[16]
D3	input	IMUX_LOGICIN[17]
D4	input	IMUX_LOGICIN[48]
OCE	input	IMUX_LOGICIN[39]
REV	input	IMUX_LOGICIN[14]
SR	input	IMUX_SR[1]
T1	input	IMUX_LOGICIN[45]
T2	input	IMUX_LOGICIN[42]
T3	input	IMUX_LOGICIN[12]
T4	input	IMUX_LOGICIN[54]
TCE	input	IMUX_LOGICIN[9]
TRAIN	input	IMUX_LOGICIN[28]

Bel OLOGIC[1]

spartan6 IOI_WE bel OLOGIC[1]
Pin	Direction	Wires
CLKDIV	input	IMUX_CLK[0]
D1	input	IMUX_LOGICIN[31]
D2	input	IMUX_LOGICIN[32]
D3	input	IMUX_LOGICIN[44]
D4	input	IMUX_LOGICIN[34]
OCE	input	IMUX_LOGICIN[30]
REV	input	IMUX_LOGICIN[29]
SR	input	IMUX_SR[0]
T1	input	IMUX_LOGICIN[24]
T2	input	IMUX_LOGICIN[25]
T3	input	IMUX_LOGICIN[26]
T4	input	IMUX_LOGICIN[27]
TCE	input	IMUX_LOGICIN[23]
TRAIN	input	IMUX_LOGICIN[8]

Bel IODELAY[0]

spartan6 IOI_WE bel IODELAY[0]
Pin	Direction	Wires
BUSY	output	OUT_TMIN[15]
CAL	input	IMUX_LOGICIN[3]
CE	input	IMUX_LOGICIN[5]
CIN	input	IMUX_LOGICIN[52]
CLK	input	IMUX_CLK[1]
INC	input	IMUX_LOGICIN[7]
LOAD	output	OUT_TMIN[17]
RCLK	output	OUT_TMIN[13]
RST	input	IMUX_LOGICIN[41]

Bel IODELAY[1]

spartan6 IOI_WE bel IODELAY[1]
Pin	Direction	Wires
BUSY	output	OUT_TMIN[14]
CAL	input	IMUX_LOGICIN[2]
CE	input	IMUX_LOGICIN[47]
CIN	input	IMUX_LOGICIN[1]
CLK	input	IMUX_CLK[0]
INC	input	IMUX_LOGICIN[58]
LOAD	output	OUT_TMIN[16]
RCLK	output	OUT_TMIN[12]
RST	input	IMUX_LOGICIN[55]

Bel IOICLK[0]

spartan6 IOI_WE bel IOICLK[0]
Pin	Direction	Wires
CKINT0	input	IMUX_CLK[1]
CKINT1	input	IMUX_GFAN[1]

Bel IOICLK[1]

spartan6 IOI_WE bel IOICLK[1]
Pin	Direction	Wires
CKINT0	input	IMUX_CLK[0]
CKINT1	input	IMUX_GFAN[0]

Bel IOI

spartan6 IOI_WE bel IOI
Pin	Direction	Wires

Bel TIEOFF_IOI

spartan6 IOI_WE bel TIEOFF_IOI
Pin	Direction	Wires

Bel wires

spartan6 IOI_WE bel wires
Wire	Pins
IMUX_GFAN[0]	IOICLK[1].CKINT1
IMUX_GFAN[1]	IOICLK[0].CKINT1
IMUX_CLK[0]	ILOGIC[1].CLKDIV, OLOGIC[1].CLKDIV, IODELAY[1].CLK, IOICLK[1].CKINT0
IMUX_CLK[1]	ILOGIC[0].CLKDIV, OLOGIC[0].CLKDIV, IODELAY[0].CLK, IOICLK[0].CKINT0
IMUX_SR[0]	OLOGIC[1].SR
IMUX_SR[1]	OLOGIC[0].SR
IMUX_LOGICIN[1]	IODELAY[1].CIN
IMUX_LOGICIN[2]	IODELAY[1].CAL
IMUX_LOGICIN[3]	IODELAY[0].CAL
IMUX_LOGICIN[5]	IODELAY[0].CE
IMUX_LOGICIN[7]	IODELAY[0].INC
IMUX_LOGICIN[8]	OLOGIC[1].TRAIN
IMUX_LOGICIN[9]	OLOGIC[0].TCE
IMUX_LOGICIN[12]	OLOGIC[0].T3
IMUX_LOGICIN[14]	OLOGIC[0].REV
IMUX_LOGICIN[15]	OLOGIC[0].D1
IMUX_LOGICIN[16]	OLOGIC[0].D2
IMUX_LOGICIN[17]	OLOGIC[0].D3
IMUX_LOGICIN[19]	ILOGIC[0].BITSLIP
IMUX_LOGICIN[20]	ILOGIC[0].SR_INT
IMUX_LOGICIN[23]	OLOGIC[1].TCE
IMUX_LOGICIN[24]	OLOGIC[1].T1
IMUX_LOGICIN[25]	OLOGIC[1].T2
IMUX_LOGICIN[26]	OLOGIC[1].T3
IMUX_LOGICIN[27]	OLOGIC[1].T4
IMUX_LOGICIN[28]	OLOGIC[0].TRAIN
IMUX_LOGICIN[29]	OLOGIC[1].REV
IMUX_LOGICIN[30]	OLOGIC[1].OCE
IMUX_LOGICIN[31]	OLOGIC[1].D1
IMUX_LOGICIN[32]	OLOGIC[1].D2
IMUX_LOGICIN[34]	OLOGIC[1].D4
IMUX_LOGICIN[36]	ILOGIC[1].SR_INT
IMUX_LOGICIN[37]	ILOGIC[1].REV
IMUX_LOGICIN[38]	ILOGIC[1].CE0
IMUX_LOGICIN[39]	OLOGIC[0].OCE
IMUX_LOGICIN[41]	IODELAY[0].RST
IMUX_LOGICIN[42]	OLOGIC[0].T2
IMUX_LOGICIN[44]	OLOGIC[1].D3
IMUX_LOGICIN[45]	OLOGIC[0].T1
IMUX_LOGICIN[47]	IODELAY[1].CE
IMUX_LOGICIN[48]	OLOGIC[0].D4
IMUX_LOGICIN[52]	IODELAY[0].CIN
IMUX_LOGICIN[54]	OLOGIC[0].T4
IMUX_LOGICIN[55]	IODELAY[1].RST
IMUX_LOGICIN[57]	ILOGIC[1].BITSLIP
IMUX_LOGICIN[58]	IODELAY[1].INC
IMUX_LOGICIN[59]	ILOGIC[0].REV
IMUX_LOGICIN[62]	ILOGIC[0].CE0
OUT_TMIN[0]	ILOGIC[1].FABRICOUT
OUT_TMIN[1]	ILOGIC[1].Q1
OUT_TMIN[2]	ILOGIC[1].Q2
OUT_TMIN[3]	ILOGIC[1].Q3
OUT_TMIN[4]	ILOGIC[1].Q4
OUT_TMIN[5]	ILOGIC[1].INCDEC
OUT_TMIN[6]	ILOGIC[1].VALID
OUT_TMIN[7]	ILOGIC[0].FABRICOUT
OUT_TMIN[8]	ILOGIC[0].Q1
OUT_TMIN[9]	ILOGIC[0].Q2
OUT_TMIN[10]	ILOGIC[0].Q3
OUT_TMIN[11]	ILOGIC[0].Q4
OUT_TMIN[12]	IODELAY[1].RCLK
OUT_TMIN[13]	IODELAY[0].RCLK
OUT_TMIN[14]	IODELAY[1].BUSY
OUT_TMIN[15]	IODELAY[0].BUSY
OUT_TMIN[16]	IODELAY[1].LOAD
OUT_TMIN[17]	IODELAY[0].LOAD

Bitstream

spartan6 IOI_WE rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

### Bitstream

spartan6 IOI_WE rect R0
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:IFF_LATCH	-	-	IODELAY[0]:ODELAY_VALUE_N[7]	-	IODELAY_COMMON:DIFF_PHASE_DETECTOR	IODELAY[0]:CAL_DELAY_MAX[0]	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC[1]:IFF_SR_SYNC	IOICLK[0]:MUX.ICE[1]	-	IODELAY[0]:IDELAY_VALUE_N[7]	-	-	IODELAY[0]:CAL_DELAY_MAX[1]	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IOICLK[0]:MUX.ICE[0]	IOICLK[0]:MUX.OCE[1]	IODELAY[0]:ODELAY_VALUE_N[6]	-	-	IODELAY[0]:CAL_DELAY_MAX[2]	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:DDR	IOICLK[0]:MUX.ICE[2]	IOICLK[0]:MUX.OCE[0]	IODELAY[0]:IDELAY_VALUE_N[6]	-	-	IODELAY[0]:CAL_DELAY_MAX[3]	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:IFF_REV_USED	IODELAY[0]:ENABLE.ODATAIN	IOICLK[0]:MUX.OCE[2]	IODELAY[0]:ODELAY_VALUE_N[5]	-	-	IODELAY[0]:CAL_DELAY_MAX[4]	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:MUX.SR[0]	ILOGIC[0]:TSBYPASS_MUX[0]	IODELAY[0]:ENABLE.CIN[2]	IODELAY[0]:IDELAY_VALUE_N[5]	-	-	IODELAY[0]:CAL_DELAY_MAX[5]	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC[1]:IFF_CE_ENABLE	~ILOGIC[0]:I_DELAY_ENABLE	IODELAY[0]:ENABLE.CIN[1]	IODELAY[0]:ODELAY_VALUE_N[4]	IOI:MEM_PLL_DIV_EN	-	IODELAY[0]:CAL_DELAY_MAX[6]	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IODELAY[0]:MODE[2]	IODELAY[0]:DELAYCHAIN_OSC	IODELAY[0]:IDELAY_VALUE_N[4]	IOI:MEM_PLL_POL_SEL[0]	-	IODELAY[0]:CAL_DELAY_MAX[7]	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:IFF_SRVAL	IOICLK[0]:DDR_ALIGNMENT[0]	IODELAY[0]:MODE[3]	IODELAY[0]:IDELAY_VALUE_N[3]	IODELAY[0]:DIFF_PHASE_DETECTOR	ILOGIC[1]:MUX.Q4[0]	~ILOGIC[0]:IFF_DELAY_ENABLE IODELAY[0]:DRP06[4]	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IOICLK[0]:DDR_ALIGNMENT[1]	IODELAY[0]:IDELAY_MODE[1]	IODELAY[0]:ODELAY_VALUE_N[3]	IODELAY[0]:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB[1]	ILOGIC[1]:MUX.Q4[1]	IODELAY[0]:DRP07[4] IODELAY[0]:LUMPED_DELAY_SELECT	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IOICLK[0]:MUX.CE0[2]	IOICLK[0]:MUX.CE1[2]	IODELAY[0]:IDELAY_VALUE_N[2]	-	ILOGIC[1]:MUX.Q3[1]	IODELAY[0]:DELAY_SRC[1] IODELAY[0]:DRP06[3]	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IODELAY[0]:IDELAY_FIXED	IOICLK[0]:MUX.CE0[1]	IOICLK[0]:MUX.CE1[1]	IODELAY[0]:ODELAY_VALUE_N[2]	-	ILOGIC[1]:MUX.Q3[0]	IODELAY[0]:DRP07[3] IODELAY[0]:LUMPED_DELAY	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:ROW2_CLK_ENABLE	-	IOICLK[0]:MUX.CE1[0]	IODELAY[0]:IDELAY_VALUE_N[1]	IODELAY[0]:TEST_NCOUNTER	ILOGIC[1]:MUX.Q2[0]	IODELAY[0]:DRP07[2] IODELAY[0]:IODELAY_CHANGE[0]	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:ROW1_CLK_ENABLE	IOICLK[0]:MUX.CE0[0]	IOICLK[0]:MUX.OCLK[2]	IODELAY[0]:ODELAY_VALUE_N[1]	-	ILOGIC[1]:MUX.Q2[1]	IODELAY[0]:DELAY_SRC[0] IODELAY[0]:DRP06[2]	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:ROW3_CLK_ENABLE	IOICLK[0]:MUX.ICLK[2]	IOICLK[0]:MUX.OCLK[3]	IODELAY[0]:IDELAY_VALUE_N[0]	IODELAY[0]:TEST_PCOUNTER	ILOGIC[1]:MUX.Q1[1]	IODELAY[0]:DRP06[5] OLOGIC[0]:OMUX[0]	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:ROW4_CLK_ENABLE	IOICLK[0]:MUX.ICLK[3]	IOICLK[0]:MUX.OCLK[0]	IODELAY[0]:ODELAY_VALUE_N[0]	-	ILOGIC[1]:MUX.Q1[0]	IODELAY[0]:DRP07[5]	OLOGIC[1]:MUX.TRAIN[1]
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:ROW4_CLK_ENABLE	-	IOICLK[0]:MUX.ICLK[0]	IODELAY[0]:ODELAY_VALUE_P[0]	IODELAY_COMMON:MCB_ADDRESS[3]	ILOGIC[0]:MUX.Q1[0]	IODELAY[0]:DRP06[1]	OLOGIC[0]:MUX.TRAIN[1]
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:ROW3_CLK_ENABLE	-	IOICLK[0]:MUX.ICLK[1]	IODELAY[0]:IDELAY_VALUE_P[0]	IODELAY_COMMON:DRP_FROM_MCB	ILOGIC[0]:MUX.Q1[1]	IODELAY[0]:COUNTER_WRAPAROUND[0] IODELAY[0]:DRP07[1]	OLOGIC[0]:CASCADE_ENABLE
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:ROW1_CLK_ENABLE	IODELAY[0]:TEST_GLITCH_FILTER	IOICLK[0]:MUX.OCLK[1]	IODELAY[0]:ODELAY_VALUE_P[1]	-	ILOGIC[0]:MUX.Q2[1]	IODELAY[0]:DRP06[0] IODELAY[0]:PLUS1	OLOGIC[0]:MUX.TRAIN[0]
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:ROW2_CLK_ENABLE	IODELAY[0]:MODE[1]	IODELAY[0]:IDELAY_MODE[0]	IODELAY[0]:IDELAY_VALUE_P[1]	IODELAY[0]:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB[0]	ILOGIC[0]:MUX.Q2[0]	IODELAY[0]:DRP07[0] IODELAY[0]:IDELAY_FROM_HALF_MAX	OLOGIC[1]:MUX.TRAIN[0]
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:MUX.D[1]	IODELAY[0]:ODELAY_VALUE_P[2]	IODELAY_COMMON:ENFFSCAN_DRP[0]	ILOGIC[0]:MUX.Q3[0]	IODELAY[0]:DRP06[7] OLOGIC[0]:MUX.OCE[0]	ILOGIC[1]:MUX.CLK[1]
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:IFF_SR_USED	IODELAY[0]:MODE[0]	ILOGIC[0]:MUX.D[0]	IODELAY[0]:IDELAY_VALUE_P[2]	-	ILOGIC[0]:MUX.Q3[1]	IODELAY[0]:DRP07[7]	ILOGIC[1]:MUX.CLK[0]
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:IFF_INIT	IOICLK[0]:DDR_ENABLE[1]	IODELAY[0]:ENABLE.CIN[0]	IODELAY[0]:ODELAY_VALUE_P[3]	-	ILOGIC[0]:MUX.Q4[1]	IODELAY[0]:DRP06[6] OLOGIC[0]:TMUX[0]	ILOGIC[0]:MUX.CLK[1]
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:DDR	IOICLK[0]:DDR_ENABLE[0]	IOICLK[0]:MUX.CLK2[1]	IODELAY[0]:IDELAY_VALUE_P[3]	-	ILOGIC[0]:MUX.Q4[0]	IODELAY[0]:DRP07[6]	ILOGIC[0]:MUX.CLK[0]
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:IFF_SR_USED	IOICLK[0]:INV.CLK2	IOICLK[0]:MUX.CLK2[0]	IODELAY[0]:IDELAY_VALUE_P[4]	IODELAY_COMMON:MCB_ADDRESS[2]	ILOGIC[0]:DATA_WIDTH_RELOAD[1]	IODELAY[0]:DRP_ADDR[0]	OLOGIC[1]:MUX.CLK[1]
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:IFF_INIT	IOICLK[0]:INV.CLK0	IOICLK[0]:INV.CLK1	IODELAY[0]:ODELAY_VALUE_P[4]	-	ILOGIC[0]:DATA_WIDTH_RELOAD[0]	IODELAY[0]:DRP_ADDR[1]	OLOGIC[1]:MUX.CLK[0]
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:IFF_SRVAL	IOICLK[0]:MUX.CLK0[4]	IOICLK[0]:MUX.CLK1[3]	IODELAY[0]:IDELAY_VALUE_P[5]	-	ILOGIC[1]:DATA_WIDTH_RELOAD[2]	IODELAY[0]:DRP_ADDR[2]	OLOGIC[0]:MUX.CLK[1]
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:MUX.SR[0]	IOICLK[0]:MUX.CLK0[2]	IOICLK[0]:MUX.CLK1[2]	IODELAY[0]:ODELAY_VALUE_P[5]	-	ILOGIC[1]:DATA_WIDTH_RELOAD[1]	IODELAY[0]:DRP_ADDR[3]	OLOGIC[0]:MUX.CLK[0]
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:IFF_REV_USED	IOICLK[0]:MUX.CLK0[3]	IOICLK[0]:MUX.CLK1[4]	IODELAY[0]:IDELAY_VALUE_P[6]	-	OLOGIC[1]:MUX.D[0]	-	ILOGIC[1]:ENABLE
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:CASCADE_ENABLE	-	-	IODELAY[0]:ODELAY_VALUE_P[6]	-	OLOGIC[1]:OFF_RANK1_BYPASS	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:IFF_LATCH	IOICLK[0]:MUX.CLK0[0]	IOICLK[0]:MUX.CLK1[0]	IODELAY[0]:IDELAY_VALUE_P[7]	-	OLOGIC[1]:TRAIN_PATTERN[0]	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC[0]:IFF_SR_SYNC	IOICLK[0]:MUX.CLK0[1]	IOICLK[0]:MUX.CLK1[1]	IODELAY[0]:ODELAY_VALUE_P[7]	-	OLOGIC[1]:TRAIN_PATTERN[1]	IODELAY[0]:DRP_ADDR[4]	ILOGIC[0]:ENABLE
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC[0]:IFF_CE_ENABLE	IOICLK[1]:MUX.CLK0[1]	IOICLK[1]:MUX.CLK1[1]	IODELAY[1]:ODELAY_VALUE_P[7]	-	OLOGIC[1]:TRAIN_PATTERN[2]	IODELAY[1]:DRP_ADDR[4]	OLOGIC[1]:ENABLE
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:CASCADE_ENABLE	IOICLK[1]:MUX.CLK0[0]	IOICLK[1]:MUX.CLK1[0]	IODELAY[1]:IDELAY_VALUE_P[7]	-	OLOGIC[1]:TRAIN_PATTERN[3]	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:OFF_LATCH	-	-	IODELAY[1]:ODELAY_VALUE_P[6]	-	OLOGIC[1]:DDR_OPPOSITE_EDGE	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:OFF_SR_ENABLE	IOICLK[1]:MUX.CLK0[3]	IOICLK[1]:MUX.CLK1[4]	IODELAY[1]:IDELAY_VALUE_P[6]	IODELAY_COMMON:DRP_ENABLE	OLOGIC[1]:MUX.T[0]	-	OLOGIC[0]:ENABLE
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:OFF_REV_ENABLE	IOICLK[1]:MUX.CLK0[2]	IOICLK[1]:MUX.CLK1[2]	IODELAY[1]:ODELAY_VALUE_P[5]	-	OLOGIC[1]:OFF_CE_ENABLE	IODELAY[1]:DRP_ADDR[3]	OLOGIC[0]:ENABLE.IOCE
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~OLOGIC[1]:OFF_SR_SYNC	IOICLK[1]:MUX.CLK0[4]	IOICLK[1]:MUX.CLK1[3]	IODELAY[1]:IDELAY_VALUE_P[5]	IODELAY_COMMON:MCB_ADDRESS[1]	OLOGIC[1]:OFF_CE_OR_DDR	IODELAY[1]:DRP_ADDR[2]	ILOGIC[0]:ENABLE.IOCE
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:OFF_INIT	IOICLK[1]:INV.CLK0	IOICLK[1]:INV.CLK1	IODELAY[1]:ODELAY_VALUE_P[4]	-	OLOGIC[1]:OFF_RANK1_CLK_ENABLE	IODELAY[1]:DRP_ADDR[1]	OLOGIC[1]:ENABLE.IOCE
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:OFF_SRVAL	IOICLK[1]:INV.CLK2	IOICLK[1]:MUX.CLK2[0]	IODELAY[1]:IDELAY_VALUE_P[4]	IODELAY_COMMON:MCB_ADDRESS[0]	OLOGIC[1]:OFF_RANK2_CLK_ENABLE	IODELAY[1]:DRP_ADDR[0]	ILOGIC[1]:ENABLE.IOCE
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:TFF_SRVAL	IOICLK[1]:DDR_ENABLE[1]	IOICLK[1]:MUX.CLK2[1]	IODELAY[1]:IDELAY_VALUE_P[3]	-	OLOGIC[1]:TFF_RANK2_CLK_ENABLE	IODELAY[1]:DRP07[6]	ILOGIC[0]:DATA_WIDTH_START[1]
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:TFF_INIT	IOICLK[1]:DDR_ENABLE[0]	IODELAY[1]:ENABLE.CIN[2]	IODELAY[1]:ODELAY_VALUE_P[3]	-	OLOGIC[1]:TFF_RANK1_CLK_ENABLE	IODELAY[1]:DRP06[6] OLOGIC[1]:TMUX[0]	ILOGIC[0]:BITSLIP_ENABLE
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~OLOGIC[1]:TFF_SR_SYNC	IODELAY[1]:MODE[1]	-	IODELAY[1]:IDELAY_VALUE_P[2]	-	OLOGIC[1]:TFF_CE_OR_DDR	IODELAY[1]:DRP07[7]	ILOGIC[0]:DATA_WIDTH_START[0]
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:TFF_REV_ENABLE	-	-	IODELAY[1]:ODELAY_VALUE_P[2]	IODELAY[1]:DIFF_PHASE_DETECTOR	OLOGIC[1]:TFF_CE_ENABLE	IODELAY[1]:DRP06[7] OLOGIC[1]:MUX.OCE[0]	ILOGIC[1]:DATA_WIDTH_START[0]
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:TFF_SR_ENABLE	IODELAY[1]:MODE[0]	IODELAY[1]:IDELAY_MODE[1]	IODELAY[1]:IDELAY_VALUE_P[1]	IODELAY[1]:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB[1]	OLOGIC[1]:TFF_RANK1_BYPASS	IODELAY[1]:DRP07[0] IODELAY[1]:IDELAY_FROM_HALF_MAX	ILOGIC[1]:DATA_WIDTH_START[1]
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:TFF_LATCH	IODELAY[1]:TEST_GLITCH_FILTER	IOICLK[1]:MUX.OCLK[1]	IODELAY[1]:ODELAY_VALUE_P[1]	-	ILOGIC[1]:DATA_WIDTH_RELOAD[0]	IODELAY[1]:DRP06[0] IODELAY[1]:EVENT_SEL[0]	ILOGIC[1]:DATA_WIDTH_START[2]
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IOICLK[1]:MUX.ICLK[1]	IODELAY[1]:IDELAY_VALUE_P[0]	-	OLOGIC[0]:TRAIN_PATTERN[1]	IODELAY[1]:COUNTER_WRAPAROUND[0] IODELAY[1]:DRP07[1]	ILOGIC[1]:BITSLIP_ENABLE
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IODELAY[1]:IDELAY_FIXED	-	IOICLK[1]:MUX.ICLK[0]	IODELAY[1]:ODELAY_VALUE_P[0]	-	OLOGIC[0]:TRAIN_PATTERN[0]	IODELAY[1]:DRP06[1] IODELAY[1]:EVENT_SEL[1]	ILOGIC[1]:CASCADE_ENABLE
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:MUX.SR[0]	IOICLK[1]:MUX.ICLK[3]	IOICLK[1]:MUX.OCLK[0]	IODELAY[1]:ODELAY_VALUE_N[0]	-	OLOGIC[0]:OFF_RANK1_BYPASS	IODELAY[1]:DRP07[5]	OLOGIC[1]:MISR_ENABLE_DATA
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:MUX.REV[0]	IOICLK[1]:MUX.ICLK[2]	IOICLK[1]:MUX.OCLK[3]	IODELAY[1]:IDELAY_VALUE_N[0]	-	OLOGIC[0]:DDR_OPPOSITE_EDGE	IODELAY[1]:DRP06[5] OLOGIC[1]:OMUX[0]	OLOGIC[1]:MISR_ENABLE_CLK
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:OFF_LATCH	IOICLK[1]:MUX.CE0[0]	IOICLK[1]:MUX.OCLK[2]	IODELAY[1]:ODELAY_VALUE_N[1]	-	OLOGIC[0]:TRAIN_PATTERN[2]	IODELAY[1]:DELAY_SRC[0] IODELAY[1]:DRP06[2]	OLOGIC[0]:MISR_ENABLE_CLK
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:OFF_SR_ENABLE	-	IOICLK[1]:MUX.CE1[0]	IODELAY[1]:IDELAY_VALUE_N[1]	IODELAY[1]:TEST_NCOUNTER	OLOGIC[0]:MUX.D[0]	IODELAY[1]:DRP07[2] IODELAY[1]:IODELAY_CHANGE[0]	OLOGIC[0]:MISR_ENABLE_DATA
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:OFF_REV_ENABLE	IOICLK[1]:MUX.CE0[1]	IOICLK[1]:MUX.CE1[1]	IODELAY[1]:ODELAY_VALUE_N[2]	-	OLOGIC[0]:OFF_CE_ENABLE	IODELAY[1]:DRP07[3] IODELAY[1]:LUMPED_DELAY	OLOGIC[1]:MISR_RESET
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~OLOGIC[0]:OFF_SR_SYNC	IOICLK[1]:MUX.CE0[2]	IOICLK[1]:MUX.CE1[2]	IODELAY[1]:IDELAY_VALUE_N[2]	-	OLOGIC[0]:OFF_CE_OR_DDR	IODELAY[1]:DELAY_SRC[1] IODELAY[1]:DRP06[3]	OLOGIC[0]:MISR_RESET
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:OFF_INIT	IOICLK[1]:DDR_ALIGNMENT[1]	IODELAY[1]:IDELAY_MODE[0]	IODELAY[1]:ODELAY_VALUE_N[3]	IODELAY[1]:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB[0]	OLOGIC[0]:OFF_RANK1_CLK_ENABLE	IODELAY[1]:DRP07[4] IODELAY[1]:LUMPED_DELAY_SELECT	IODELAY_COMMON:ENFFSCAN_DRP[1]
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:OFF_SRVAL	IOICLK[1]:DDR_ALIGNMENT[0]	IODELAY[1]:MODE[3]	IODELAY[1]:IDELAY_VALUE_N[3]	-	OLOGIC[0]:OFF_RANK2_CLK_ENABLE	~ILOGIC[1]:IFF_DELAY_ENABLE IODELAY[1]:DRP06[4]	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:TFF_SRVAL	IODELAY[1]:MODE[2]	IODELAY[1]:DELAYCHAIN_OSC	IODELAY[1]:IDELAY_VALUE_N[4]	-	OLOGIC[0]:TFF_RANK2_CLK_ENABLE	IODELAY[1]:CAL_DELAY_MAX[7]	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:TFF_INIT	~ILOGIC[1]:I_DELAY_ENABLE	IODELAY[1]:ENABLE.CIN[1]	IODELAY[1]:ODELAY_VALUE_N[4]	-	OLOGIC[0]:TFF_RANK1_CLK_ENABLE	IODELAY[1]:CAL_DELAY_MAX[6]	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~OLOGIC[0]:TFF_SR_SYNC	ILOGIC[1]:TSBYPASS_MUX[0]	IODELAY[1]:ENABLE.CIN[0]	IODELAY[1]:IDELAY_VALUE_N[5]	-	OLOGIC[0]:TFF_CE_OR_DDR	IODELAY[1]:CAL_DELAY_MAX[5]	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:TFF_REV_ENABLE	IODELAY[1]:ENABLE.ODATAIN	IOICLK[1]:MUX.OCE[2]	IODELAY[1]:ODELAY_VALUE_N[5]	-	OLOGIC[0]:TFF_CE_ENABLE	IODELAY[1]:CAL_DELAY_MAX[4]	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:TFF_SR_ENABLE	IOICLK[1]:MUX.ICE[2]	IOICLK[1]:MUX.OCE[0]	IODELAY[1]:IDELAY_VALUE_N[6]	-	OLOGIC[0]:TRAIN_PATTERN[3]	IODELAY[1]:CAL_DELAY_MAX[3]	IODELAY[0]:MUX.IOCLK[0]
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:TFF_LATCH	IOICLK[1]:MUX.ICE[0]	IOICLK[1]:MUX.OCE[1]	IODELAY[1]:ODELAY_VALUE_N[6]	-	OLOGIC[0]:MUX.T[0]	IODELAY[1]:CAL_DELAY_MAX[2]	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:MUX.SR[0]	IOICLK[1]:MUX.ICE[1]	-	IODELAY[1]:IDELAY_VALUE_N[7]	-	OLOGIC[0]:TFF_RANK1_BYPASS	IODELAY[1]:CAL_DELAY_MAX[1]	IODELAY[1]:MUX.IOCLK[0]
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:MUX.REV[0]	-	-	IODELAY[1]:ODELAY_VALUE_N[7]	IODELAY[1]:TEST_PCOUNTER	OLOGIC[0]:OUTPUT_MODE[0]	IODELAY[1]:CAL_DELAY_MAX[0]	-

ILOGIC[0]:BITSLIP_ENABLE	0.F29.B22
ILOGIC[0]:CASCADE_ENABLE	0.F22.B34
ILOGIC[0]:DDR	0.F22.B40
ILOGIC[0]:ENABLE	0.F29.B32
ILOGIC[0]:ENABLE.IOCE	0.F29.B26
ILOGIC[0]:IFF_INIT	0.F22.B38
ILOGIC[0]:IFF_LATCH	0.F22.B33
ILOGIC[0]:IFF_REV_USED	0.F22.B35
ILOGIC[0]:IFF_SRVAL	0.F22.B37
ILOGIC[0]:IFF_SR_USED	0.F22.B39
ILOGIC[0]:ROW1_CLK_ENABLE	0.F22.B45
ILOGIC[0]:ROW2_CLK_ENABLE	0.F22.B44
ILOGIC[0]:ROW3_CLK_ENABLE	0.F22.B46
ILOGIC[0]:ROW4_CLK_ENABLE	0.F22.B47
ILOGIC[1]:BITSLIP_ENABLE	0.F29.B17
ILOGIC[1]:CASCADE_ENABLE	0.F29.B16
ILOGIC[1]:DDR	0.F22.B60
ILOGIC[1]:ENABLE	0.F29.B35
ILOGIC[1]:ENABLE.IOCE	0.F29.B24
ILOGIC[1]:IFF_INIT	0.F22.B41
ILOGIC[1]:IFF_LATCH	0.F22.B63
ILOGIC[1]:IFF_REV_USED	0.F22.B59
ILOGIC[1]:IFF_SRVAL	0.F22.B55
ILOGIC[1]:IFF_SR_USED	0.F22.B42
ILOGIC[1]:ROW1_CLK_ENABLE	0.F22.B50
ILOGIC[1]:ROW2_CLK_ENABLE	0.F22.B51
ILOGIC[1]:ROW3_CLK_ENABLE	0.F22.B49
ILOGIC[1]:ROW4_CLK_ENABLE	0.F22.B48
IODELAY[0]:DELAYCHAIN_OSC	0.F24.B56
IODELAY[0]:DIFF_PHASE_DETECTOR	0.F26.B55
IODELAY[0]:ENABLE.ODATAIN	0.F23.B59
IODELAY[0]:IDELAY_FIXED	0.F22.B52
IODELAY[0]:IDELAY_FROM_HALF_MAX	0.F28.B44
IODELAY[0]:LUMPED_DELAY	0.F28.B52
IODELAY[0]:LUMPED_DELAY_SELECT	0.F28.B54
IODELAY[0]:PLUS1	0.F28.B45
IODELAY[0]:TEST_GLITCH_FILTER	0.F23.B45
IODELAY[0]:TEST_NCOUNTER	0.F26.B51
IODELAY[0]:TEST_PCOUNTER	0.F26.B49
IODELAY[1]:DELAYCHAIN_OSC	0.F24.B7
IODELAY[1]:DIFF_PHASE_DETECTOR	0.F26.B20
IODELAY[1]:ENABLE.ODATAIN	0.F23.B4
IODELAY[1]:IDELAY_FIXED	0.F22.B16
IODELAY[1]:IDELAY_FROM_HALF_MAX	0.F28.B19
IODELAY[1]:LUMPED_DELAY	0.F28.B11
IODELAY[1]:LUMPED_DELAY_SELECT	0.F28.B9
IODELAY[1]:TEST_GLITCH_FILTER	0.F23.B18
IODELAY[1]:TEST_NCOUNTER	0.F26.B12
IODELAY[1]:TEST_PCOUNTER	0.F26.B0
IODELAY_COMMON:DIFF_PHASE_DETECTOR	0.F27.B63
IODELAY_COMMON:DRP_ENABLE	0.F26.B28
IODELAY_COMMON:DRP_FROM_MCB	0.F26.B46
IOI:MEM_PLL_DIV_EN	0.F26.B57
IOICLK[0]:INV.CLK0	0.F23.B38
IOICLK[0]:INV.CLK1	0.F24.B38
IOICLK[0]:INV.CLK2	0.F23.B39
IOICLK[1]:INV.CLK0	0.F23.B25
IOICLK[1]:INV.CLK1	0.F24.B25
IOICLK[1]:INV.CLK2	0.F23.B24
OLOGIC[0]:CASCADE_ENABLE	0.F29.B46
OLOGIC[0]:DDR_OPPOSITE_EDGE	0.F27.B14
OLOGIC[0]:ENABLE	0.F29.B28
OLOGIC[0]:ENABLE.IOCE	0.F29.B27
OLOGIC[0]:MISR_ENABLE_CLK	0.F29.B13
OLOGIC[0]:MISR_ENABLE_DATA	0.F29.B12
OLOGIC[0]:MISR_RESET	0.F29.B10
OLOGIC[0]:OFF_CE_ENABLE	0.F27.B11
OLOGIC[0]:OFF_CE_OR_DDR	0.F27.B10
OLOGIC[0]:OFF_INIT	0.F22.B9
OLOGIC[0]:OFF_LATCH	0.F22.B13
OLOGIC[0]:OFF_RANK1_BYPASS	0.F27.B15
OLOGIC[0]:OFF_RANK1_CLK_ENABLE	0.F27.B9
OLOGIC[0]:OFF_RANK2_CLK_ENABLE	0.F27.B8
OLOGIC[0]:OFF_REV_ENABLE	0.F22.B11
OLOGIC[0]:OFF_SRVAL	0.F22.B8
OLOGIC[0]:OFF_SR_ENABLE	0.F22.B12
OLOGIC[0]:TFF_CE_ENABLE	0.F27.B4
OLOGIC[0]:TFF_CE_OR_DDR	0.F27.B5
OLOGIC[0]:TFF_INIT	0.F22.B6
OLOGIC[0]:TFF_LATCH	0.F22.B2
OLOGIC[0]:TFF_RANK1_BYPASS	0.F27.B1
OLOGIC[0]:TFF_RANK1_CLK_ENABLE	0.F27.B6
OLOGIC[0]:TFF_RANK2_CLK_ENABLE	0.F27.B7
OLOGIC[0]:TFF_REV_ENABLE	0.F22.B4
OLOGIC[0]:TFF_SRVAL	0.F22.B7
OLOGIC[0]:TFF_SR_ENABLE	0.F22.B3
OLOGIC[1]:CASCADE_ENABLE	0.F22.B30
OLOGIC[1]:DDR_OPPOSITE_EDGE	0.F27.B29
OLOGIC[1]:ENABLE	0.F29.B31
OLOGIC[1]:ENABLE.IOCE	0.F29.B25
OLOGIC[1]:MISR_ENABLE_CLK	0.F29.B14
OLOGIC[1]:MISR_ENABLE_DATA	0.F29.B15
OLOGIC[1]:MISR_RESET	0.F29.B11
OLOGIC[1]:OFF_CE_ENABLE	0.F27.B27
OLOGIC[1]:OFF_CE_OR_DDR	0.F27.B26
OLOGIC[1]:OFF_INIT	0.F22.B25
OLOGIC[1]:OFF_LATCH	0.F22.B29
OLOGIC[1]:OFF_RANK1_BYPASS	0.F27.B34
OLOGIC[1]:OFF_RANK1_CLK_ENABLE	0.F27.B25
OLOGIC[1]:OFF_RANK2_CLK_ENABLE	0.F27.B24
OLOGIC[1]:OFF_REV_ENABLE	0.F22.B27
OLOGIC[1]:OFF_SRVAL	0.F22.B24
OLOGIC[1]:OFF_SR_ENABLE	0.F22.B28
OLOGIC[1]:TFF_CE_ENABLE	0.F27.B20
OLOGIC[1]:TFF_CE_OR_DDR	0.F27.B21
OLOGIC[1]:TFF_INIT	0.F22.B22
OLOGIC[1]:TFF_LATCH	0.F22.B18
OLOGIC[1]:TFF_RANK1_BYPASS	0.F27.B19
OLOGIC[1]:TFF_RANK1_CLK_ENABLE	0.F27.B22
OLOGIC[1]:TFF_RANK2_CLK_ENABLE	0.F27.B23
OLOGIC[1]:TFF_REV_ENABLE	0.F22.B20
OLOGIC[1]:TFF_SRVAL	0.F22.B23
OLOGIC[1]:TFF_SR_ENABLE	0.F22.B19
non-inverted	[0]

ILOGIC[0]:DATA_WIDTH_RELOAD	0.F27.B39	0.F27.B38
4	0	0
3	0	1
2	1	0
1	1	1

ILOGIC[0]:DATA_WIDTH_START	0.F29.B23	0.F29.B21
2	0	0
3	0	1
4	1	0

ILOGIC[0]:IFF_CE_ENABLE	0.F22.B31
ILOGIC[0]:IFF_DELAY_ENABLE	0.F28.B55
ILOGIC[0]:IFF_SR_SYNC	0.F22.B32
ILOGIC[0]:I_DELAY_ENABLE	0.F23.B57
ILOGIC[1]:IFF_CE_ENABLE	0.F22.B57
ILOGIC[1]:IFF_DELAY_ENABLE	0.F28.B8
ILOGIC[1]:IFF_SR_SYNC	0.F22.B62
ILOGIC[1]:I_DELAY_ENABLE	0.F23.B6
OLOGIC[0]:OFF_SR_SYNC	0.F22.B10
OLOGIC[0]:TFF_SR_SYNC	0.F22.B5
OLOGIC[1]:OFF_SR_SYNC	0.F22.B26
OLOGIC[1]:TFF_SR_SYNC	0.F22.B21
inverted	~[0]

ILOGIC[0]:MUX.CLK	0.F29.B41	0.F29.B40
ILOGIC[1]:MUX.CLK	0.F29.B43	0.F29.B42
NONE	0	0
ICLK0	0	1
ICLK1	1	0

ILOGIC[0]:MUX.D	0.F24.B43	0.F24.B42
IOB_I	0	0
OTHER_IOB_I	1	1

ILOGIC[0]:MUX.Q1	0.F27.B46	0.F27.B47
ILOGIC[0]:MUX.Q2	0.F27.B45	0.F27.B44
ILOGIC[0]:MUX.Q3	0.F27.B42	0.F27.B43
ILOGIC[0]:MUX.Q4	0.F27.B41	0.F27.B40
ILOGIC[1]:MUX.Q1	0.F27.B49	0.F27.B48
ILOGIC[1]:MUX.Q2	0.F27.B50	0.F27.B51
ILOGIC[1]:MUX.Q3	0.F27.B53	0.F27.B52
ILOGIC[1]:MUX.Q4	0.F27.B54	0.F27.B55
SHIFT_REGISTER	0	0
NETWORKING	0	1
NETWORKING_PIPELINED	1	0
RETIMED	1	1

ILOGIC[0]:MUX.SR	0.F22.B36
ILOGIC[1]:MUX.SR	0.F22.B58
OLOGIC_SR	0
INT	1

ILOGIC[0]:TSBYPASS_MUX	0.F23.B58
ILOGIC[1]:TSBYPASS_MUX	0.F23.B5
GND	0
T	1

ILOGIC[1]:DATA_WIDTH_RELOAD	0.F27.B37	0.F27.B36	0.F27.B18
8	0	0	0
7	0	0	1
6	0	1	0
5	0	1	1
4	1	0	0
3	1	0	1
2	1	1	0
1	1	1	1

ILOGIC[1]:DATA_WIDTH_START	0.F29.B18	0.F29.B19	0.F29.B20
2	0	0	0
3	0	0	1
4	0	1	0
5	0	1	1
6	1	0	0
7	1	0	1
8	1	1	0

IODELAY[0]:CAL_DELAY_MAX	0.F28.B56	0.F28.B57	0.F28.B58	0.F28.B59	0.F28.B60	0.F28.B61	0.F28.B62	0.F28.B63
IODELAY[0]:DRP06	0.F28.B43	0.F28.B41	0.F28.B49	0.F28.B55	0.F28.B53	0.F28.B50	0.F28.B47	0.F28.B45
IODELAY[0]:DRP07	0.F28.B42	0.F28.B40	0.F28.B48	0.F28.B54	0.F28.B52	0.F28.B51	0.F28.B46	0.F28.B44
IODELAY[0]:IDELAY_VALUE_N	0.F25.B62	0.F25.B60	0.F25.B58	0.F25.B56	0.F25.B55	0.F25.B53	0.F25.B51	0.F25.B49
IODELAY[0]:IDELAY_VALUE_P	0.F25.B33	0.F25.B35	0.F25.B37	0.F25.B39	0.F25.B40	0.F25.B42	0.F25.B44	0.F25.B46
IODELAY[0]:ODELAY_VALUE_N	0.F25.B63	0.F25.B61	0.F25.B59	0.F25.B57	0.F25.B54	0.F25.B52	0.F25.B50	0.F25.B48
IODELAY[0]:ODELAY_VALUE_P	0.F25.B32	0.F25.B34	0.F25.B36	0.F25.B38	0.F25.B41	0.F25.B43	0.F25.B45	0.F25.B47
IODELAY[1]:CAL_DELAY_MAX	0.F28.B7	0.F28.B6	0.F28.B5	0.F28.B4	0.F28.B3	0.F28.B2	0.F28.B1	0.F28.B0
IODELAY[1]:DRP06	0.F28.B20	0.F28.B22	0.F28.B14	0.F28.B8	0.F28.B10	0.F28.B13	0.F28.B16	0.F28.B18
IODELAY[1]:DRP07	0.F28.B21	0.F28.B23	0.F28.B15	0.F28.B9	0.F28.B11	0.F28.B12	0.F28.B17	0.F28.B19
IODELAY[1]:IDELAY_VALUE_N	0.F25.B1	0.F25.B3	0.F25.B5	0.F25.B7	0.F25.B8	0.F25.B10	0.F25.B12	0.F25.B14
IODELAY[1]:IDELAY_VALUE_P	0.F25.B30	0.F25.B28	0.F25.B26	0.F25.B24	0.F25.B23	0.F25.B21	0.F25.B19	0.F25.B17
IODELAY[1]:ODELAY_VALUE_N	0.F25.B0	0.F25.B2	0.F25.B4	0.F25.B6	0.F25.B9	0.F25.B11	0.F25.B13	0.F25.B15
IODELAY[1]:ODELAY_VALUE_P	0.F25.B31	0.F25.B29	0.F25.B27	0.F25.B25	0.F25.B22	0.F25.B20	0.F25.B18	0.F25.B16
non-inverted	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

IODELAY[0]:COUNTER_WRAPAROUND	0.F28.B46
IODELAY[1]:COUNTER_WRAPAROUND	0.F28.B17
WRAPAROUND	0
STAY_AT_LIMIT	1

IODELAY[0]:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB	0.F26.B54	0.F26.B44
IODELAY[1]:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB	0.F26.B19	0.F26.B9
IODELAY[1]:EVENT_SEL	0.F28.B16	0.F28.B18
IODELAY_COMMON:ENFFSCAN_DRP	0.F29.B9	0.F26.B43
IOICLK[0]:DDR_ENABLE	0.F23.B41	0.F23.B40
IOICLK[1]:DDR_ENABLE	0.F23.B23	0.F23.B22
non-inverted	[1]	[0]

IODELAY[0]:DELAY_SRC	0.F28.B53	0.F28.B50
IODELAY[1]:DELAY_SRC	0.F28.B10	0.F28.B13
IO	0	0
ODATAIN	0	1
IDATAIN	1	1

IODELAY[0]:DRP_ADDR	0.F28.B32	0.F28.B36	0.F28.B37	0.F28.B38	0.F28.B39
IODELAY[1]:DRP_ADDR	0.F28.B31	0.F28.B27	0.F28.B26	0.F28.B25	0.F28.B24
non-inverted	[4]	[3]	[2]	[1]	[0]

IODELAY[0]:ENABLE.CIN	0.F24.B58	0.F24.B57	0.F24.B41
IODELAY[1]:ENABLE.CIN	0.F24.B22	0.F24.B6	0.F24.B5
non-inverted	[2]	[1]	[0]

IODELAY[0]:IDELAY_MODE	0.F24.B54	0.F24.B44
IODELAY[1]:IDELAY_MODE	0.F24.B19	0.F24.B9
NORMAL	0	0
PCI	1	1

IODELAY[0]:IODELAY_CHANGE	0.F28.B51
IODELAY[1]:IODELAY_CHANGE	0.F28.B12
CHANGE_ON_CLOCK	0
CHANGE_ON_DATA	1

IODELAY[0]:MODE	0.F24.B55	0.F23.B56	0.F23.B44	0.F23.B42
IODELAY[1]:MODE	0.F24.B8	0.F23.B7	0.F23.B21	0.F23.B19
IODRP2	0	0	0	0
IODELAY2	0	0	1	1
IODRP2_MCB	1	1	0	0

IODELAY[0]:MUX.IOCLK	0.F29.B3
IODELAY[1]:MUX.IOCLK	0.F29.B1
ILOGIC_CLK	0
OLOGIC_CLK	1

IODELAY_COMMON:MCB_ADDRESS	0.F26.B47	0.F26.B39	0.F26.B26	0.F26.B24
OLOGIC[0]:TRAIN_PATTERN	0.F27.B3	0.F27.B13	0.F27.B17	0.F27.B16
OLOGIC[1]:TRAIN_PATTERN	0.F27.B30	0.F27.B31	0.F27.B32	0.F27.B33
non-inverted	[3]	[2]	[1]	[0]

IOI:MEM_PLL_POL_SEL	0.F26.B56
INVERTED	0
NOTINVERTED	1

IOICLK[0]:DDR_ALIGNMENT	0.F23.B54	0.F23.B55
IOICLK[1]:DDR_ALIGNMENT	0.F23.B9	0.F23.B8
NONE	0	0
CLK0	0	1
CLK1	1	0

IOICLK[0]:MUX.CE0	0.F23.B53	0.F23.B52	0.F23.B50
IOICLK[1]:MUX.CE0	0.F23.B10	0.F23.B11	0.F23.B13
NONE	0	0	0
IOCE0	0	0	1
IOCE2	0	1	0
PLLCE0	1	0	0

IOICLK[0]:MUX.CE1	0.F24.B53	0.F24.B52	0.F24.B51
IOICLK[1]:MUX.CE1	0.F24.B10	0.F24.B11	0.F24.B12
NONE	0	0	0
IOCE1	0	0	1
IOCE3	0	1	0
PLLCE1	1	0	0

IOICLK[0]:MUX.CLK0	0.F23.B37	0.F23.B35	0.F23.B36	0.F23.B32	0.F23.B33
IOICLK[1]:MUX.CLK0	0.F23.B26	0.F23.B28	0.F23.B27	0.F23.B31	0.F23.B30
NONE	0	0	0	0	0
IOCLK0	0	0	0	0	1
IOCLK2	0	0	0	1	0
PLLCLK0	0	0	1	0	0
CKINT0	0	1	0	0	0
CKINT1	1	0	0	0	0

IOICLK[0]:MUX.CLK1	0.F24.B35	0.F24.B37	0.F24.B36	0.F24.B32	0.F24.B33
IOICLK[1]:MUX.CLK1	0.F24.B28	0.F24.B26	0.F24.B27	0.F24.B31	0.F24.B30
NONE	0	0	0	0	0
IOCLK1	0	0	0	0	1
IOCLK3	0	0	0	1	0
PLLCLK1	0	0	1	0	0
CKINT0	0	1	0	0	0
CKINT1	1	0	0	0	0

IOICLK[0]:MUX.CLK2	0.F24.B40	0.F24.B39
IOICLK[1]:MUX.CLK2	0.F24.B23	0.F24.B24
NONE	0	0
PLLCLK0	0	1
PLLCLK1	1	0

IOICLK[0]:MUX.ICE	0.F23.B60	0.F23.B62	0.F23.B61
IOICLK[0]:MUX.OCE	0.F24.B59	0.F24.B61	0.F24.B60
IOICLK[1]:MUX.ICE	0.F23.B3	0.F23.B1	0.F23.B2
IOICLK[1]:MUX.OCE	0.F24.B4	0.F24.B2	0.F24.B3
NONE	0	0	0
CE0	0	0	1
CE1	0	1	0
DDR	1	0	0

IOICLK[0]:MUX.ICLK	0.F23.B48	0.F23.B49	0.F24.B46	0.F24.B47
IOICLK[0]:MUX.OCLK	0.F24.B49	0.F24.B50	0.F24.B45	0.F24.B48
IOICLK[1]:MUX.ICLK	0.F23.B15	0.F23.B14	0.F24.B17	0.F24.B16
IOICLK[1]:MUX.OCLK	0.F24.B14	0.F24.B13	0.F24.B18	0.F24.B15
NONE	0	0	0	0
CLK0	0	0	0	1
CLK1	0	0	1	0
CLK2	0	1	0	0
DDR	1	0	0	0

OLOGIC[0]:MUX.CLK	0.F29.B37	0.F29.B36
OLOGIC[1]:MUX.CLK	0.F29.B39	0.F29.B38
NONE	0	0
OCLK0	0	1
OCLK1	1	0

OLOGIC[0]:MUX.D	0.F27.B12
OLOGIC[0]:MUX.T	0.F27.B2
OLOGIC[1]:MUX.D	0.F27.B35
OLOGIC[1]:MUX.T	0.F27.B28
INT	0
MCB	1

OLOGIC[0]:MUX.OCE	0.F28.B43
OLOGIC[1]:MUX.OCE	0.F28.B20
INT	0
PCI_CE	1

OLOGIC[0]:MUX.REV	0.F22.B0
OLOGIC[0]:MUX.SR	0.F22.B1
OLOGIC[1]:MUX.REV	0.F22.B14
OLOGIC[1]:MUX.SR	0.F22.B15
GND	0
INT	1

OLOGIC[0]:MUX.TRAIN	0.F29.B47	0.F29.B45
OLOGIC[1]:MUX.TRAIN	0.F29.B48	0.F29.B44
GND	0	0
INT	0	1
MCB	1	0

OLOGIC[0]:OMUX	0.F28.B49
OLOGIC[1]:OMUX	0.F28.B14
OUTFF	0
D1	1

OLOGIC[0]:OUTPUT_MODE	0.F27.B0
SINGLE_ENDED	0
DIFFERENTIAL	1

OLOGIC[0]:TMUX	0.F28.B41
OLOGIC[1]:TMUX	0.F28.B22
TFF	0
T1	1

Tile IOI_SN

Cells: 1

Bel ILOGIC[0]

spartan6 IOI_SN bel ILOGIC[0]
Pin	Direction	Wires
BITSLIP	input	IMUX_LOGICIN[19]
CE0	input	IMUX_LOGICIN[62]
CLKDIV	input	IMUX_CLK[1]
FABRICOUT	output	OUT_TMIN[7]
Q1	output	OUT_TMIN[8]
Q2	output	OUT_TMIN[9]
Q3	output	OUT_TMIN[10]
Q4	output	OUT_TMIN[11]
REV	input	IMUX_LOGICIN[59]
SR_INT	input	IMUX_LOGICIN[20]

Bel ILOGIC[1]

spartan6 IOI_SN bel ILOGIC[1]
Pin	Direction	Wires
BITSLIP	input	IMUX_LOGICIN[57]
CE0	input	IMUX_LOGICIN[38]
CLKDIV	input	IMUX_CLK[0]
FABRICOUT	output	OUT_TMIN[0]
INCDEC	output	OUT_TMIN[5]
Q1	output	OUT_TMIN[1]
Q2	output	OUT_TMIN[2]
Q3	output	OUT_TMIN[3]
Q4	output	OUT_TMIN[4]
REV	input	IMUX_LOGICIN[37]
SR_INT	input	IMUX_LOGICIN[36]
VALID	output	OUT_TMIN[6]

Bel OLOGIC[0]

spartan6 IOI_SN bel OLOGIC[0]
Pin	Direction	Wires
CLKDIV	input	IMUX_CLK[1]
D1	input	IMUX_LOGICIN[15]
D2	input	IMUX_LOGICIN[16]
D3	input	IMUX_LOGICIN[17]
D4	input	IMUX_LOGICIN[48]
OCE	input	IMUX_LOGICIN[39]
REV	input	IMUX_LOGICIN[14]
SR	input	IMUX_SR[1]
T1	input	IMUX_LOGICIN[45]
T2	input	IMUX_LOGICIN[42]
T3	input	IMUX_LOGICIN[12]
T4	input	IMUX_LOGICIN[54]
TCE	input	IMUX_LOGICIN[9]
TRAIN	input	IMUX_LOGICIN[28]

Bel OLOGIC[1]

spartan6 IOI_SN bel OLOGIC[1]
Pin	Direction	Wires
CLKDIV	input	IMUX_CLK[0]
D1	input	IMUX_LOGICIN[31]
D2	input	IMUX_LOGICIN[32]
D3	input	IMUX_LOGICIN[44]
D4	input	IMUX_LOGICIN[34]
OCE	input	IMUX_LOGICIN[30]
REV	input	IMUX_LOGICIN[29]
SR	input	IMUX_SR[0]
T1	input	IMUX_LOGICIN[24]
T2	input	IMUX_LOGICIN[25]
T3	input	IMUX_LOGICIN[26]
T4	input	IMUX_LOGICIN[27]
TCE	input	IMUX_LOGICIN[23]
TRAIN	input	IMUX_LOGICIN[8]

Bel IODELAY[0]

spartan6 IOI_SN bel IODELAY[0]
Pin	Direction	Wires
BUSY	output	OUT_TMIN[15]
CAL	input	IMUX_LOGICIN[3]
CE	input	IMUX_LOGICIN[5]
CIN	input	IMUX_LOGICIN[52]
CLK	input	IMUX_CLK[1]
INC	input	IMUX_LOGICIN[7]
LOAD	output	OUT_TMIN[17]
RCLK	output	OUT_TMIN[13]
RST	input	IMUX_LOGICIN[41]

Bel IODELAY[1]

spartan6 IOI_SN bel IODELAY[1]
Pin	Direction	Wires
BUSY	output	OUT_TMIN[14]
CAL	input	IMUX_LOGICIN[2]
CE	input	IMUX_LOGICIN[47]
CIN	input	IMUX_LOGICIN[1]
CLK	input	IMUX_CLK[0]
INC	input	IMUX_LOGICIN[58]
LOAD	output	OUT_TMIN[16]
RCLK	output	OUT_TMIN[12]
RST	input	IMUX_LOGICIN[55]

Bel IOICLK[0]

spartan6 IOI_SN bel IOICLK[0]
Pin	Direction	Wires
CKINT0	input	IMUX_CLK[1]
CKINT1	input	IMUX_GFAN[1]

Bel IOICLK[1]

spartan6 IOI_SN bel IOICLK[1]
Pin	Direction	Wires
CKINT0	input	IMUX_CLK[0]
CKINT1	input	IMUX_GFAN[0]

Bel IOI

spartan6 IOI_SN bel IOI
Pin	Direction	Wires

Bel TIEOFF_IOI

spartan6 IOI_SN bel TIEOFF_IOI
Pin	Direction	Wires

Bel wires

spartan6 IOI_SN bel wires
Wire	Pins
IMUX_GFAN[0]	IOICLK[1].CKINT1
IMUX_GFAN[1]	IOICLK[0].CKINT1
IMUX_CLK[0]	ILOGIC[1].CLKDIV, OLOGIC[1].CLKDIV, IODELAY[1].CLK, IOICLK[1].CKINT0
IMUX_CLK[1]	ILOGIC[0].CLKDIV, OLOGIC[0].CLKDIV, IODELAY[0].CLK, IOICLK[0].CKINT0
IMUX_SR[0]	OLOGIC[1].SR
IMUX_SR[1]	OLOGIC[0].SR
IMUX_LOGICIN[1]	IODELAY[1].CIN
IMUX_LOGICIN[2]	IODELAY[1].CAL
IMUX_LOGICIN[3]	IODELAY[0].CAL
IMUX_LOGICIN[5]	IODELAY[0].CE
IMUX_LOGICIN[7]	IODELAY[0].INC
IMUX_LOGICIN[8]	OLOGIC[1].TRAIN
IMUX_LOGICIN[9]	OLOGIC[0].TCE
IMUX_LOGICIN[12]	OLOGIC[0].T3
IMUX_LOGICIN[14]	OLOGIC[0].REV
IMUX_LOGICIN[15]	OLOGIC[0].D1
IMUX_LOGICIN[16]	OLOGIC[0].D2
IMUX_LOGICIN[17]	OLOGIC[0].D3
IMUX_LOGICIN[19]	ILOGIC[0].BITSLIP
IMUX_LOGICIN[20]	ILOGIC[0].SR_INT
IMUX_LOGICIN[23]	OLOGIC[1].TCE
IMUX_LOGICIN[24]	OLOGIC[1].T1
IMUX_LOGICIN[25]	OLOGIC[1].T2
IMUX_LOGICIN[26]	OLOGIC[1].T3
IMUX_LOGICIN[27]	OLOGIC[1].T4
IMUX_LOGICIN[28]	OLOGIC[0].TRAIN
IMUX_LOGICIN[29]	OLOGIC[1].REV
IMUX_LOGICIN[30]	OLOGIC[1].OCE
IMUX_LOGICIN[31]	OLOGIC[1].D1
IMUX_LOGICIN[32]	OLOGIC[1].D2
IMUX_LOGICIN[34]	OLOGIC[1].D4
IMUX_LOGICIN[36]	ILOGIC[1].SR_INT
IMUX_LOGICIN[37]	ILOGIC[1].REV
IMUX_LOGICIN[38]	ILOGIC[1].CE0
IMUX_LOGICIN[39]	OLOGIC[0].OCE
IMUX_LOGICIN[41]	IODELAY[0].RST
IMUX_LOGICIN[42]	OLOGIC[0].T2
IMUX_LOGICIN[44]	OLOGIC[1].D3
IMUX_LOGICIN[45]	OLOGIC[0].T1
IMUX_LOGICIN[47]	IODELAY[1].CE
IMUX_LOGICIN[48]	OLOGIC[0].D4
IMUX_LOGICIN[52]	IODELAY[0].CIN
IMUX_LOGICIN[54]	OLOGIC[0].T4
IMUX_LOGICIN[55]	IODELAY[1].RST
IMUX_LOGICIN[57]	ILOGIC[1].BITSLIP
IMUX_LOGICIN[58]	IODELAY[1].INC
IMUX_LOGICIN[59]	ILOGIC[0].REV
IMUX_LOGICIN[62]	ILOGIC[0].CE0
OUT_TMIN[0]	ILOGIC[1].FABRICOUT
OUT_TMIN[1]	ILOGIC[1].Q1
OUT_TMIN[2]	ILOGIC[1].Q2
OUT_TMIN[3]	ILOGIC[1].Q3
OUT_TMIN[4]	ILOGIC[1].Q4
OUT_TMIN[5]	ILOGIC[1].INCDEC
OUT_TMIN[6]	ILOGIC[1].VALID
OUT_TMIN[7]	ILOGIC[0].FABRICOUT
OUT_TMIN[8]	ILOGIC[0].Q1
OUT_TMIN[9]	ILOGIC[0].Q2
OUT_TMIN[10]	ILOGIC[0].Q3
OUT_TMIN[11]	ILOGIC[0].Q4
OUT_TMIN[12]	IODELAY[1].RCLK
OUT_TMIN[13]	IODELAY[0].RCLK
OUT_TMIN[14]	IODELAY[1].BUSY
OUT_TMIN[15]	IODELAY[0].BUSY
OUT_TMIN[16]	IODELAY[1].LOAD
OUT_TMIN[17]	IODELAY[0].LOAD

Bitstream

spartan6 IOI_SN rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

### Bitstream

spartan6 IOI_SN rect R0
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:IFF_LATCH	-	IODELAY[0]:ODELAY_VALUE_N[7]	-	-	IODELAY_COMMON:DIFF_PHASE_DETECTOR	IODELAY[0]:CAL_DELAY_MAX[0]	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC[1]:IFF_SR_SYNC	-	IODELAY[0]:IDELAY_VALUE_N[7]	-	-	-	IODELAY[0]:CAL_DELAY_MAX[1]	IOICLK[0]:MUX.ICE[1]
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IOICLK[0]:MUX.OCE[1]	IODELAY[0]:ODELAY_VALUE_N[6]	-	-	-	IODELAY[0]:CAL_DELAY_MAX[2]	IOICLK[0]:MUX.ICE[0]
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:DDR	IOICLK[0]:MUX.OCE[0]	IODELAY[0]:IDELAY_VALUE_N[6]	-	-	-	IODELAY[0]:CAL_DELAY_MAX[3]	IOICLK[0]:MUX.ICE[2]
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:IFF_REV_USED	IOICLK[0]:MUX.OCE[2]	IODELAY[0]:ODELAY_VALUE_N[5]	-	-	-	IODELAY[0]:CAL_DELAY_MAX[4]	IODELAY[0]:ENABLE.ODATAIN
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:MUX.SR[0]	IODELAY[0]:ENABLE.CIN[2]	IODELAY[0]:IDELAY_VALUE_N[5]	-	-	-	IODELAY[0]:CAL_DELAY_MAX[5]	ILOGIC[0]:TSBYPASS_MUX[0]
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC[1]:IFF_CE_ENABLE	IODELAY[0]:ENABLE.CIN[1]	IODELAY[0]:ODELAY_VALUE_N[4]	IOI:MEM_PLL_POL_SEL[0]	-	-	IODELAY[0]:CAL_DELAY_MAX[6]	~ILOGIC[0]:I_DELAY_ENABLE
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IODELAY[0]:DELAYCHAIN_OSC	IODELAY[0]:IDELAY_VALUE_N[4]	IOI:MEM_PLL_DIV_EN	-	-	IODELAY[0]:CAL_DELAY_MAX[7]	IODELAY[0]:MODE[3]
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:IFF_SRVAL	IODELAY[0]:MODE[2]	IODELAY[0]:IDELAY_VALUE_N[3]	IODELAY[0]:DIFF_PHASE_DETECTOR	-	ILOGIC[1]:MUX.Q4[0]	~ILOGIC[0]:IFF_DELAY_ENABLE IODELAY[0]:DRP06[4]	IOICLK[0]:DDR_ALIGNMENT[0]
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IODELAY[0]:IDELAY_MODE[1]	IODELAY[0]:ODELAY_VALUE_N[3]	IODELAY[0]:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB[1]	-	ILOGIC[1]:MUX.Q4[1]	IODELAY[0]:DRP07[4] IODELAY[0]:LUMPED_DELAY_SELECT	IOICLK[0]:DDR_ALIGNMENT[1]
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IOICLK[0]:MUX.CE1[2]	IODELAY[0]:IDELAY_VALUE_N[2]	-	-	ILOGIC[1]:MUX.Q3[1]	IODELAY[0]:DELAY_SRC[1] IODELAY[0]:DRP06[3]	IOICLK[0]:MUX.CE0[2]
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IODELAY[0]:IDELAY_FIXED	IOICLK[0]:MUX.CE1[1]	IODELAY[0]:ODELAY_VALUE_N[2]	-	-	ILOGIC[1]:MUX.Q3[0]	IODELAY[0]:DRP07[3] IODELAY[0]:LUMPED_DELAY	IOICLK[0]:MUX.CE0[1]
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:ROW2_CLK_ENABLE	IOICLK[0]:MUX.CE1[0]	IODELAY[0]:IDELAY_VALUE_N[1]	IODELAY[0]:TEST_NCOUNTER	-	ILOGIC[1]:MUX.Q2[0]	IODELAY[0]:DRP07[2] IODELAY[0]:IODELAY_CHANGE[0]	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:ROW1_CLK_ENABLE	IOICLK[0]:MUX.OCLK[2]	IODELAY[0]:ODELAY_VALUE_N[1]	-	-	ILOGIC[1]:MUX.Q2[1]	IODELAY[0]:DELAY_SRC[0] IODELAY[0]:DRP06[2]	IOICLK[0]:MUX.CE0[0]
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:ROW3_CLK_ENABLE	IOICLK[0]:MUX.OCLK[3]	IODELAY[0]:IDELAY_VALUE_N[0]	IODELAY[0]:TEST_PCOUNTER	-	ILOGIC[1]:MUX.Q1[1]	IODELAY[0]:DRP06[5] OLOGIC[0]:OMUX[0]	IOICLK[0]:MUX.ICLK[2]
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:ROW4_CLK_ENABLE	IOICLK[0]:MUX.OCLK[0]	IODELAY[0]:ODELAY_VALUE_N[0]	-	OLOGIC[1]:MUX.TRAIN[1]	ILOGIC[1]:MUX.Q1[0]	IODELAY[0]:DRP07[5]	IOICLK[0]:MUX.ICLK[3]
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:ROW4_CLK_ENABLE	IOICLK[0]:MUX.ICLK[0]	IODELAY[0]:ODELAY_VALUE_P[0]	IODELAY_COMMON:MCB_ADDRESS[3]	OLOGIC[0]:MUX.TRAIN[1]	ILOGIC[0]:MUX.Q1[0]	IODELAY[0]:DRP06[1]	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:ROW3_CLK_ENABLE	IOICLK[0]:MUX.ICLK[1]	IODELAY[0]:IDELAY_VALUE_P[0]	IODELAY_COMMON:DRP_FROM_MCB	OLOGIC[0]:CASCADE_ENABLE	ILOGIC[0]:MUX.Q1[1]	IODELAY[0]:COUNTER_WRAPAROUND[0] IODELAY[0]:DRP07[1]	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:ROW1_CLK_ENABLE	IOICLK[0]:MUX.OCLK[1]	IODELAY[0]:ODELAY_VALUE_P[1]	-	OLOGIC[0]:MUX.TRAIN[0]	ILOGIC[0]:MUX.Q2[1]	IODELAY[0]:DRP06[0] IODELAY[0]:PLUS1	IODELAY[0]:TEST_GLITCH_FILTER
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:ROW2_CLK_ENABLE	IODELAY[0]:IDELAY_MODE[0]	IODELAY[0]:IDELAY_VALUE_P[1]	IODELAY[0]:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB[0]	OLOGIC[1]:MUX.TRAIN[0]	ILOGIC[0]:MUX.Q2[0]	IODELAY[0]:DRP07[0] IODELAY[0]:IDELAY_FROM_HALF_MAX	IODELAY[0]:MODE[1]
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:MUX.D[1]	IODELAY[0]:ODELAY_VALUE_P[2]	IODELAY_COMMON:ENFFSCAN_DRP[0]	ILOGIC[1]:MUX.CLK[1]	ILOGIC[0]:MUX.Q3[0]	IODELAY[0]:DRP06[7] OLOGIC[0]:MUX.OCE[0]	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:IFF_SR_USED	ILOGIC[0]:MUX.D[0]	IODELAY[0]:IDELAY_VALUE_P[2]	-	ILOGIC[1]:MUX.CLK[0]	ILOGIC[0]:MUX.Q3[1]	IODELAY[0]:DRP07[7]	IODELAY[0]:MODE[0]
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]:IFF_INIT	IODELAY[0]:ENABLE.CIN[0]	IODELAY[0]:ODELAY_VALUE_P[3]	-	ILOGIC[0]:MUX.CLK[1]	ILOGIC[0]:MUX.Q4[1]	IODELAY[0]:DRP06[6] OLOGIC[0]:TMUX[0]	IOICLK[0]:DDR_ENABLE[1]
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:DDR	IOICLK[0]:MUX.CLK2[1]	IODELAY[0]:IDELAY_VALUE_P[3]	-	ILOGIC[0]:MUX.CLK[0]	ILOGIC[0]:MUX.Q4[0]	IODELAY[0]:DRP07[6]	IOICLK[0]:DDR_ENABLE[0]
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:IFF_SR_USED	IOICLK[0]:MUX.CLK2[0]	IODELAY[0]:IDELAY_VALUE_P[4]	IODELAY_COMMON:MCB_ADDRESS[2]	OLOGIC[1]:MUX.CLK[1]	ILOGIC[0]:DATA_WIDTH_RELOAD[1]	IODELAY[0]:DRP_ADDR[0]	IOICLK[0]:INV.CLK2
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:IFF_INIT	IOICLK[0]:INV.CLK1	IODELAY[0]:ODELAY_VALUE_P[4]	-	OLOGIC[1]:MUX.CLK[0]	ILOGIC[0]:DATA_WIDTH_RELOAD[0]	IODELAY[0]:DRP_ADDR[1]	IOICLK[0]:INV.CLK0
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:IFF_SRVAL	IOICLK[0]:MUX.CLK1[3]	IODELAY[0]:IDELAY_VALUE_P[5]	-	OLOGIC[0]:MUX.CLK[1]	ILOGIC[1]:DATA_WIDTH_RELOAD[2]	IODELAY[0]:DRP_ADDR[2]	IOICLK[0]:MUX.CLK0[4]
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:MUX.SR[0]	IOICLK[0]:MUX.CLK1[2]	IODELAY[0]:ODELAY_VALUE_P[5]	-	OLOGIC[0]:MUX.CLK[0]	ILOGIC[1]:DATA_WIDTH_RELOAD[1]	IODELAY[0]:DRP_ADDR[3]	IOICLK[0]:MUX.CLK0[2]
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:IFF_REV_USED	IOICLK[0]:MUX.CLK1[4]	IODELAY[0]:IDELAY_VALUE_P[6]	-	ILOGIC[1]:ENABLE	OLOGIC[1]:MUX.D[0]	-	IOICLK[0]:MUX.CLK0[3]
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:CASCADE_ENABLE	-	IODELAY[0]:ODELAY_VALUE_P[6]	-	-	OLOGIC[1]:OFF_RANK1_BYPASS	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]:IFF_LATCH	IOICLK[0]:MUX.CLK1[0]	IODELAY[0]:IDELAY_VALUE_P[7]	-	-	OLOGIC[1]:TRAIN_PATTERN[0]	-	IOICLK[0]:MUX.CLK0[0]
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC[0]:IFF_SR_SYNC	IOICLK[0]:MUX.CLK1[1]	IODELAY[0]:ODELAY_VALUE_P[7]	-	ILOGIC[0]:ENABLE	OLOGIC[1]:TRAIN_PATTERN[1]	IODELAY[0]:DRP_ADDR[4]	IOICLK[0]:MUX.CLK0[1]
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~ILOGIC[0]:IFF_CE_ENABLE	IOICLK[1]:MUX.CLK1[1]	IODELAY[1]:ODELAY_VALUE_P[7]	-	OLOGIC[1]:ENABLE	OLOGIC[1]:TRAIN_PATTERN[2]	IODELAY[1]:DRP_ADDR[4]	IOICLK[1]:MUX.CLK0[1]
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:CASCADE_ENABLE	IOICLK[1]:MUX.CLK1[0]	IODELAY[1]:IDELAY_VALUE_P[7]	-	-	OLOGIC[1]:TRAIN_PATTERN[3]	-	IOICLK[1]:MUX.CLK0[0]
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:OFF_LATCH	-	IODELAY[1]:ODELAY_VALUE_P[6]	-	-	OLOGIC[1]:DDR_OPPOSITE_EDGE	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:OFF_SR_ENABLE	IOICLK[1]:MUX.CLK1[4]	IODELAY[1]:IDELAY_VALUE_P[6]	IODELAY_COMMON:DRP_ENABLE	OLOGIC[0]:ENABLE	OLOGIC[1]:MUX.T[0]	-	IOICLK[1]:MUX.CLK0[3]
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:OFF_REV_ENABLE	IOICLK[1]:MUX.CLK1[2]	IODELAY[1]:ODELAY_VALUE_P[5]	-	OLOGIC[0]:ENABLE.IOCE	OLOGIC[1]:OFF_CE_ENABLE	IODELAY[1]:DRP_ADDR[3]	IOICLK[1]:MUX.CLK0[2]
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~OLOGIC[1]:OFF_SR_SYNC	IOICLK[1]:MUX.CLK1[3]	IODELAY[1]:IDELAY_VALUE_P[5]	IODELAY_COMMON:MCB_ADDRESS[1]	ILOGIC[0]:ENABLE.IOCE	OLOGIC[1]:OFF_CE_OR_DDR	IODELAY[1]:DRP_ADDR[2]	IOICLK[1]:MUX.CLK0[4]
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:OFF_INIT	IOICLK[1]:INV.CLK1	IODELAY[1]:ODELAY_VALUE_P[4]	-	OLOGIC[1]:ENABLE.IOCE	OLOGIC[1]:OFF_RANK1_CLK_ENABLE	IODELAY[1]:DRP_ADDR[1]	IOICLK[1]:INV.CLK0
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:OFF_SRVAL	IOICLK[1]:MUX.CLK2[0]	IODELAY[1]:IDELAY_VALUE_P[4]	IODELAY_COMMON:MCB_ADDRESS[0]	ILOGIC[1]:ENABLE.IOCE	OLOGIC[1]:OFF_RANK2_CLK_ENABLE	IODELAY[1]:DRP_ADDR[0]	IOICLK[1]:INV.CLK2
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:TFF_SRVAL	IOICLK[1]:MUX.CLK2[1]	IODELAY[1]:IDELAY_VALUE_P[3]	-	ILOGIC[0]:DATA_WIDTH_START[1]	OLOGIC[1]:TFF_RANK2_CLK_ENABLE	IODELAY[1]:DRP07[6]	IOICLK[1]:DDR_ENABLE[1]
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:TFF_INIT	IODELAY[1]:ENABLE.CIN[2]	IODELAY[1]:ODELAY_VALUE_P[3]	-	ILOGIC[0]:BITSLIP_ENABLE	OLOGIC[1]:TFF_RANK1_CLK_ENABLE	IODELAY[1]:DRP06[6] OLOGIC[1]:TMUX[0]	IOICLK[1]:DDR_ENABLE[0]
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~OLOGIC[1]:TFF_SR_SYNC	-	IODELAY[1]:IDELAY_VALUE_P[2]	-	ILOGIC[0]:DATA_WIDTH_START[0]	OLOGIC[1]:TFF_CE_OR_DDR	IODELAY[1]:DRP07[7]	IODELAY[1]:MODE[1]
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:TFF_REV_ENABLE	-	IODELAY[1]:ODELAY_VALUE_P[2]	IODELAY[1]:DIFF_PHASE_DETECTOR	ILOGIC[1]:DATA_WIDTH_START[0]	OLOGIC[1]:TFF_CE_ENABLE	IODELAY[1]:DRP06[7] OLOGIC[1]:MUX.OCE[0]	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:TFF_SR_ENABLE	IODELAY[1]:IDELAY_MODE[1]	IODELAY[1]:IDELAY_VALUE_P[1]	IODELAY[1]:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB[1]	ILOGIC[1]:DATA_WIDTH_START[1]	OLOGIC[1]:TFF_RANK1_BYPASS	IODELAY[1]:DRP07[0] IODELAY[1]:IDELAY_FROM_HALF_MAX	IODELAY[1]:MODE[0]
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:TFF_LATCH	IOICLK[1]:MUX.OCLK[1]	IODELAY[1]:ODELAY_VALUE_P[1]	-	ILOGIC[1]:DATA_WIDTH_START[2]	ILOGIC[1]:DATA_WIDTH_RELOAD[0]	IODELAY[1]:DRP06[0] IODELAY[1]:EVENT_SEL[0]	IODELAY[1]:TEST_GLITCH_FILTER
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IOICLK[1]:MUX.ICLK[1]	IODELAY[1]:IDELAY_VALUE_P[0]	-	ILOGIC[1]:BITSLIP_ENABLE	OLOGIC[0]:TRAIN_PATTERN[1]	IODELAY[1]:COUNTER_WRAPAROUND[0] IODELAY[1]:DRP07[1]	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	IODELAY[1]:IDELAY_FIXED	IOICLK[1]:MUX.ICLK[0]	IODELAY[1]:ODELAY_VALUE_P[0]	-	ILOGIC[1]:CASCADE_ENABLE	OLOGIC[0]:TRAIN_PATTERN[0]	IODELAY[1]:DRP06[1] IODELAY[1]:EVENT_SEL[1]	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:MUX.SR[0]	IOICLK[1]:MUX.OCLK[0]	IODELAY[1]:ODELAY_VALUE_N[0]	-	OLOGIC[1]:MISR_ENABLE_DATA	OLOGIC[0]:OFF_RANK1_BYPASS	IODELAY[1]:DRP07[5]	IOICLK[1]:MUX.ICLK[3]
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]:MUX.REV[0]	IOICLK[1]:MUX.OCLK[3]	IODELAY[1]:IDELAY_VALUE_N[0]	-	OLOGIC[1]:MISR_ENABLE_CLK	OLOGIC[0]:DDR_OPPOSITE_EDGE	IODELAY[1]:DRP06[5] OLOGIC[1]:OMUX[0]	IOICLK[1]:MUX.ICLK[2]
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:OFF_LATCH	IOICLK[1]:MUX.OCLK[2]	IODELAY[1]:ODELAY_VALUE_N[1]	-	OLOGIC[0]:MISR_ENABLE_CLK	OLOGIC[0]:TRAIN_PATTERN[2]	IODELAY[1]:DELAY_SRC[0] IODELAY[1]:DRP06[2]	IOICLK[1]:MUX.CE0[0]
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:OFF_SR_ENABLE	IOICLK[1]:MUX.CE1[0]	IODELAY[1]:IDELAY_VALUE_N[1]	IODELAY[1]:TEST_NCOUNTER	OLOGIC[0]:MISR_ENABLE_DATA	OLOGIC[0]:MUX.D[0]	IODELAY[1]:DRP07[2] IODELAY[1]:IODELAY_CHANGE[0]	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:OFF_REV_ENABLE	IOICLK[1]:MUX.CE1[1]	IODELAY[1]:ODELAY_VALUE_N[2]	-	OLOGIC[1]:MISR_RESET	OLOGIC[0]:OFF_CE_ENABLE	IODELAY[1]:DRP07[3] IODELAY[1]:LUMPED_DELAY	IOICLK[1]:MUX.CE0[1]
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~OLOGIC[0]:OFF_SR_SYNC	IOICLK[1]:MUX.CE1[2]	IODELAY[1]:IDELAY_VALUE_N[2]	-	OLOGIC[0]:MISR_RESET	OLOGIC[0]:OFF_CE_OR_DDR	IODELAY[1]:DELAY_SRC[1] IODELAY[1]:DRP06[3]	IOICLK[1]:MUX.CE0[2]
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:OFF_INIT	IODELAY[1]:IDELAY_MODE[0]	IODELAY[1]:ODELAY_VALUE_N[3]	IODELAY[1]:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB[0]	IODELAY_COMMON:ENFFSCAN_DRP[1]	OLOGIC[0]:OFF_RANK1_CLK_ENABLE	IODELAY[1]:DRP07[4] IODELAY[1]:LUMPED_DELAY_SELECT	IOICLK[1]:DDR_ALIGNMENT[1]
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:OFF_SRVAL	IODELAY[1]:MODE[2]	IODELAY[1]:IDELAY_VALUE_N[3]	-	-	OLOGIC[0]:OFF_RANK2_CLK_ENABLE	~ILOGIC[1]:IFF_DELAY_ENABLE IODELAY[1]:DRP06[4]	IOICLK[1]:DDR_ALIGNMENT[0]
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:TFF_SRVAL	IODELAY[1]:DELAYCHAIN_OSC	IODELAY[1]:IDELAY_VALUE_N[4]	-	-	OLOGIC[0]:TFF_RANK2_CLK_ENABLE	IODELAY[1]:CAL_DELAY_MAX[7]	IODELAY[1]:MODE[3]
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:TFF_INIT	IODELAY[1]:ENABLE.CIN[1]	IODELAY[1]:ODELAY_VALUE_N[4]	-	-	OLOGIC[0]:TFF_RANK1_CLK_ENABLE	IODELAY[1]:CAL_DELAY_MAX[6]	~ILOGIC[1]:I_DELAY_ENABLE
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~OLOGIC[0]:TFF_SR_SYNC	IODELAY[1]:ENABLE.CIN[0]	IODELAY[1]:IDELAY_VALUE_N[5]	-	-	OLOGIC[0]:TFF_CE_OR_DDR	IODELAY[1]:CAL_DELAY_MAX[5]	ILOGIC[1]:TSBYPASS_MUX[0]
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:TFF_REV_ENABLE	IOICLK[1]:MUX.OCE[2]	IODELAY[1]:ODELAY_VALUE_N[5]	-	-	OLOGIC[0]:TFF_CE_ENABLE	IODELAY[1]:CAL_DELAY_MAX[4]	IODELAY[1]:ENABLE.ODATAIN
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:TFF_SR_ENABLE	IOICLK[1]:MUX.OCE[0]	IODELAY[1]:IDELAY_VALUE_N[6]	-	IODELAY[0]:MUX.IOCLK[0]	OLOGIC[0]:TRAIN_PATTERN[3]	IODELAY[1]:CAL_DELAY_MAX[3]	IOICLK[1]:MUX.ICE[2]
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:TFF_LATCH	IOICLK[1]:MUX.OCE[1]	IODELAY[1]:ODELAY_VALUE_N[6]	-	-	OLOGIC[0]:MUX.T[0]	IODELAY[1]:CAL_DELAY_MAX[2]	IOICLK[1]:MUX.ICE[0]
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:MUX.SR[0]	-	IODELAY[1]:IDELAY_VALUE_N[7]	-	IODELAY[1]:MUX.IOCLK[0]	OLOGIC[0]:TFF_RANK1_BYPASS	IODELAY[1]:CAL_DELAY_MAX[1]	IOICLK[1]:MUX.ICE[1]
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]:MUX.REV[0]	-	IODELAY[1]:ODELAY_VALUE_N[7]	IODELAY[1]:TEST_PCOUNTER	-	OLOGIC[0]:OUTPUT_MODE[0]	IODELAY[1]:CAL_DELAY_MAX[0]	-

ILOGIC[0]:BITSLIP_ENABLE	0.F26.B22
ILOGIC[0]:CASCADE_ENABLE	0.F22.B34
ILOGIC[0]:DDR	0.F22.B40
ILOGIC[0]:ENABLE	0.F26.B32
ILOGIC[0]:ENABLE.IOCE	0.F26.B26
ILOGIC[0]:IFF_INIT	0.F22.B38
ILOGIC[0]:IFF_LATCH	0.F22.B33
ILOGIC[0]:IFF_REV_USED	0.F22.B35
ILOGIC[0]:IFF_SRVAL	0.F22.B37
ILOGIC[0]:IFF_SR_USED	0.F22.B39
ILOGIC[0]:ROW1_CLK_ENABLE	0.F22.B45
ILOGIC[0]:ROW2_CLK_ENABLE	0.F22.B44
ILOGIC[0]:ROW3_CLK_ENABLE	0.F22.B46
ILOGIC[0]:ROW4_CLK_ENABLE	0.F22.B47
ILOGIC[1]:BITSLIP_ENABLE	0.F26.B17
ILOGIC[1]:CASCADE_ENABLE	0.F26.B16
ILOGIC[1]:DDR	0.F22.B60
ILOGIC[1]:ENABLE	0.F26.B35
ILOGIC[1]:ENABLE.IOCE	0.F26.B24
ILOGIC[1]:IFF_INIT	0.F22.B41
ILOGIC[1]:IFF_LATCH	0.F22.B63
ILOGIC[1]:IFF_REV_USED	0.F22.B59
ILOGIC[1]:IFF_SRVAL	0.F22.B55
ILOGIC[1]:IFF_SR_USED	0.F22.B42
ILOGIC[1]:ROW1_CLK_ENABLE	0.F22.B50
ILOGIC[1]:ROW2_CLK_ENABLE	0.F22.B51
ILOGIC[1]:ROW3_CLK_ENABLE	0.F22.B49
ILOGIC[1]:ROW4_CLK_ENABLE	0.F22.B48
IODELAY[0]:DELAYCHAIN_OSC	0.F23.B56
IODELAY[0]:DIFF_PHASE_DETECTOR	0.F25.B55
IODELAY[0]:ENABLE.ODATAIN	0.F29.B59
IODELAY[0]:IDELAY_FIXED	0.F22.B52
IODELAY[0]:IDELAY_FROM_HALF_MAX	0.F28.B44
IODELAY[0]:LUMPED_DELAY	0.F28.B52
IODELAY[0]:LUMPED_DELAY_SELECT	0.F28.B54
IODELAY[0]:PLUS1	0.F28.B45
IODELAY[0]:TEST_GLITCH_FILTER	0.F29.B45
IODELAY[0]:TEST_NCOUNTER	0.F25.B51
IODELAY[0]:TEST_PCOUNTER	0.F25.B49
IODELAY[1]:DELAYCHAIN_OSC	0.F23.B7
IODELAY[1]:DIFF_PHASE_DETECTOR	0.F25.B20
IODELAY[1]:ENABLE.ODATAIN	0.F29.B4
IODELAY[1]:IDELAY_FIXED	0.F22.B16
IODELAY[1]:IDELAY_FROM_HALF_MAX	0.F28.B19
IODELAY[1]:LUMPED_DELAY	0.F28.B11
IODELAY[1]:LUMPED_DELAY_SELECT	0.F28.B9
IODELAY[1]:TEST_GLITCH_FILTER	0.F29.B18
IODELAY[1]:TEST_NCOUNTER	0.F25.B12
IODELAY[1]:TEST_PCOUNTER	0.F25.B0
IODELAY_COMMON:DIFF_PHASE_DETECTOR	0.F27.B63
IODELAY_COMMON:DRP_ENABLE	0.F25.B28
IODELAY_COMMON:DRP_FROM_MCB	0.F25.B46
IOI:MEM_PLL_DIV_EN	0.F25.B56
IOICLK[0]:INV.CLK0	0.F29.B38
IOICLK[0]:INV.CLK1	0.F23.B38
IOICLK[0]:INV.CLK2	0.F29.B39
IOICLK[1]:INV.CLK0	0.F29.B25
IOICLK[1]:INV.CLK1	0.F23.B25
IOICLK[1]:INV.CLK2	0.F29.B24
OLOGIC[0]:CASCADE_ENABLE	0.F26.B46
OLOGIC[0]:DDR_OPPOSITE_EDGE	0.F27.B14
OLOGIC[0]:ENABLE	0.F26.B28
OLOGIC[0]:ENABLE.IOCE	0.F26.B27
OLOGIC[0]:MISR_ENABLE_CLK	0.F26.B13
OLOGIC[0]:MISR_ENABLE_DATA	0.F26.B12
OLOGIC[0]:MISR_RESET	0.F26.B10
OLOGIC[0]:OFF_CE_ENABLE	0.F27.B11
OLOGIC[0]:OFF_CE_OR_DDR	0.F27.B10
OLOGIC[0]:OFF_INIT	0.F22.B9
OLOGIC[0]:OFF_LATCH	0.F22.B13
OLOGIC[0]:OFF_RANK1_BYPASS	0.F27.B15
OLOGIC[0]:OFF_RANK1_CLK_ENABLE	0.F27.B9
OLOGIC[0]:OFF_RANK2_CLK_ENABLE	0.F27.B8
OLOGIC[0]:OFF_REV_ENABLE	0.F22.B11
OLOGIC[0]:OFF_SRVAL	0.F22.B8
OLOGIC[0]:OFF_SR_ENABLE	0.F22.B12
OLOGIC[0]:TFF_CE_ENABLE	0.F27.B4
OLOGIC[0]:TFF_CE_OR_DDR	0.F27.B5
OLOGIC[0]:TFF_INIT	0.F22.B6
OLOGIC[0]:TFF_LATCH	0.F22.B2
OLOGIC[0]:TFF_RANK1_BYPASS	0.F27.B1
OLOGIC[0]:TFF_RANK1_CLK_ENABLE	0.F27.B6
OLOGIC[0]:TFF_RANK2_CLK_ENABLE	0.F27.B7
OLOGIC[0]:TFF_REV_ENABLE	0.F22.B4
OLOGIC[0]:TFF_SRVAL	0.F22.B7
OLOGIC[0]:TFF_SR_ENABLE	0.F22.B3
OLOGIC[1]:CASCADE_ENABLE	0.F22.B30
OLOGIC[1]:DDR_OPPOSITE_EDGE	0.F27.B29
OLOGIC[1]:ENABLE	0.F26.B31
OLOGIC[1]:ENABLE.IOCE	0.F26.B25
OLOGIC[1]:MISR_ENABLE_CLK	0.F26.B14
OLOGIC[1]:MISR_ENABLE_DATA	0.F26.B15
OLOGIC[1]:MISR_RESET	0.F26.B11
OLOGIC[1]:OFF_CE_ENABLE	0.F27.B27
OLOGIC[1]:OFF_CE_OR_DDR	0.F27.B26
OLOGIC[1]:OFF_INIT	0.F22.B25
OLOGIC[1]:OFF_LATCH	0.F22.B29
OLOGIC[1]:OFF_RANK1_BYPASS	0.F27.B34
OLOGIC[1]:OFF_RANK1_CLK_ENABLE	0.F27.B25
OLOGIC[1]:OFF_RANK2_CLK_ENABLE	0.F27.B24
OLOGIC[1]:OFF_REV_ENABLE	0.F22.B27
OLOGIC[1]:OFF_SRVAL	0.F22.B24
OLOGIC[1]:OFF_SR_ENABLE	0.F22.B28
OLOGIC[1]:TFF_CE_ENABLE	0.F27.B20
OLOGIC[1]:TFF_CE_OR_DDR	0.F27.B21
OLOGIC[1]:TFF_INIT	0.F22.B22
OLOGIC[1]:TFF_LATCH	0.F22.B18
OLOGIC[1]:TFF_RANK1_BYPASS	0.F27.B19
OLOGIC[1]:TFF_RANK1_CLK_ENABLE	0.F27.B22
OLOGIC[1]:TFF_RANK2_CLK_ENABLE	0.F27.B23
OLOGIC[1]:TFF_REV_ENABLE	0.F22.B20
OLOGIC[1]:TFF_SRVAL	0.F22.B23
OLOGIC[1]:TFF_SR_ENABLE	0.F22.B19
non-inverted	[0]

ILOGIC[0]:DATA_WIDTH_RELOAD	0.F27.B39	0.F27.B38
4	0	0
3	0	1
2	1	0
1	1	1

ILOGIC[0]:DATA_WIDTH_START	0.F26.B23	0.F26.B21
2	0	0
3	0	1
4	1	0

ILOGIC[0]:IFF_CE_ENABLE	0.F22.B31
ILOGIC[0]:IFF_DELAY_ENABLE	0.F28.B55
ILOGIC[0]:IFF_SR_SYNC	0.F22.B32
ILOGIC[0]:I_DELAY_ENABLE	0.F29.B57
ILOGIC[1]:IFF_CE_ENABLE	0.F22.B57
ILOGIC[1]:IFF_DELAY_ENABLE	0.F28.B8
ILOGIC[1]:IFF_SR_SYNC	0.F22.B62
ILOGIC[1]:I_DELAY_ENABLE	0.F29.B6
OLOGIC[0]:OFF_SR_SYNC	0.F22.B10
OLOGIC[0]:TFF_SR_SYNC	0.F22.B5
OLOGIC[1]:OFF_SR_SYNC	0.F22.B26
OLOGIC[1]:TFF_SR_SYNC	0.F22.B21
inverted	~[0]

ILOGIC[0]:MUX.CLK	0.F26.B41	0.F26.B40
ILOGIC[1]:MUX.CLK	0.F26.B43	0.F26.B42
NONE	0	0
ICLK0	0	1
ICLK1	1	0

ILOGIC[0]:MUX.D	0.F23.B43	0.F23.B42
IOB_I	0	0
OTHER_IOB_I	1	1

ILOGIC[0]:MUX.Q1	0.F27.B46	0.F27.B47
ILOGIC[0]:MUX.Q2	0.F27.B45	0.F27.B44
ILOGIC[0]:MUX.Q3	0.F27.B42	0.F27.B43
ILOGIC[0]:MUX.Q4	0.F27.B41	0.F27.B40
ILOGIC[1]:MUX.Q1	0.F27.B49	0.F27.B48
ILOGIC[1]:MUX.Q2	0.F27.B50	0.F27.B51
ILOGIC[1]:MUX.Q3	0.F27.B53	0.F27.B52
ILOGIC[1]:MUX.Q4	0.F27.B54	0.F27.B55
SHIFT_REGISTER	0	0
NETWORKING	0	1
NETWORKING_PIPELINED	1	0
RETIMED	1	1

ILOGIC[0]:MUX.SR	0.F22.B36
ILOGIC[1]:MUX.SR	0.F22.B58
OLOGIC_SR	0
INT	1

ILOGIC[0]:TSBYPASS_MUX	0.F29.B58
ILOGIC[1]:TSBYPASS_MUX	0.F29.B5
GND	0
T	1

ILOGIC[1]:DATA_WIDTH_RELOAD	0.F27.B37	0.F27.B36	0.F27.B18
8	0	0	0
7	0	0	1
6	0	1	0
5	0	1	1
4	1	0	0
3	1	0	1
2	1	1	0
1	1	1	1

ILOGIC[1]:DATA_WIDTH_START	0.F26.B18	0.F26.B19	0.F26.B20
2	0	0	0
3	0	0	1
4	0	1	0
5	0	1	1
6	1	0	0
7	1	0	1
8	1	1	0

IODELAY[0]:CAL_DELAY_MAX	0.F28.B56	0.F28.B57	0.F28.B58	0.F28.B59	0.F28.B60	0.F28.B61	0.F28.B62	0.F28.B63
IODELAY[0]:DRP06	0.F28.B43	0.F28.B41	0.F28.B49	0.F28.B55	0.F28.B53	0.F28.B50	0.F28.B47	0.F28.B45
IODELAY[0]:DRP07	0.F28.B42	0.F28.B40	0.F28.B48	0.F28.B54	0.F28.B52	0.F28.B51	0.F28.B46	0.F28.B44
IODELAY[0]:IDELAY_VALUE_N	0.F24.B62	0.F24.B60	0.F24.B58	0.F24.B56	0.F24.B55	0.F24.B53	0.F24.B51	0.F24.B49
IODELAY[0]:IDELAY_VALUE_P	0.F24.B33	0.F24.B35	0.F24.B37	0.F24.B39	0.F24.B40	0.F24.B42	0.F24.B44	0.F24.B46
IODELAY[0]:ODELAY_VALUE_N	0.F24.B63	0.F24.B61	0.F24.B59	0.F24.B57	0.F24.B54	0.F24.B52	0.F24.B50	0.F24.B48
IODELAY[0]:ODELAY_VALUE_P	0.F24.B32	0.F24.B34	0.F24.B36	0.F24.B38	0.F24.B41	0.F24.B43	0.F24.B45	0.F24.B47
IODELAY[1]:CAL_DELAY_MAX	0.F28.B7	0.F28.B6	0.F28.B5	0.F28.B4	0.F28.B3	0.F28.B2	0.F28.B1	0.F28.B0
IODELAY[1]:DRP06	0.F28.B20	0.F28.B22	0.F28.B14	0.F28.B8	0.F28.B10	0.F28.B13	0.F28.B16	0.F28.B18
IODELAY[1]:DRP07	0.F28.B21	0.F28.B23	0.F28.B15	0.F28.B9	0.F28.B11	0.F28.B12	0.F28.B17	0.F28.B19
IODELAY[1]:IDELAY_VALUE_N	0.F24.B1	0.F24.B3	0.F24.B5	0.F24.B7	0.F24.B8	0.F24.B10	0.F24.B12	0.F24.B14
IODELAY[1]:IDELAY_VALUE_P	0.F24.B30	0.F24.B28	0.F24.B26	0.F24.B24	0.F24.B23	0.F24.B21	0.F24.B19	0.F24.B17
IODELAY[1]:ODELAY_VALUE_N	0.F24.B0	0.F24.B2	0.F24.B4	0.F24.B6	0.F24.B9	0.F24.B11	0.F24.B13	0.F24.B15
IODELAY[1]:ODELAY_VALUE_P	0.F24.B31	0.F24.B29	0.F24.B27	0.F24.B25	0.F24.B22	0.F24.B20	0.F24.B18	0.F24.B16
non-inverted	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

IODELAY[0]:COUNTER_WRAPAROUND	0.F28.B46
IODELAY[1]:COUNTER_WRAPAROUND	0.F28.B17
WRAPAROUND	0
STAY_AT_LIMIT	1

IODELAY[0]:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB	0.F25.B54	0.F25.B44
IODELAY[1]:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB	0.F25.B19	0.F25.B9
IODELAY[1]:EVENT_SEL	0.F28.B16	0.F28.B18
IODELAY_COMMON:ENFFSCAN_DRP	0.F26.B9	0.F25.B43
IOICLK[0]:DDR_ENABLE	0.F29.B41	0.F29.B40
IOICLK[1]:DDR_ENABLE	0.F29.B23	0.F29.B22
non-inverted	[1]	[0]

IODELAY[0]:DELAY_SRC	0.F28.B53	0.F28.B50
IODELAY[1]:DELAY_SRC	0.F28.B10	0.F28.B13
IO	0	0
ODATAIN	0	1
IDATAIN	1	1

IODELAY[0]:DRP_ADDR	0.F28.B32	0.F28.B36	0.F28.B37	0.F28.B38	0.F28.B39
IODELAY[1]:DRP_ADDR	0.F28.B31	0.F28.B27	0.F28.B26	0.F28.B25	0.F28.B24
non-inverted	[4]	[3]	[2]	[1]	[0]

IODELAY[0]:ENABLE.CIN	0.F23.B58	0.F23.B57	0.F23.B41
IODELAY[1]:ENABLE.CIN	0.F23.B22	0.F23.B6	0.F23.B5
non-inverted	[2]	[1]	[0]

IODELAY[0]:IDELAY_MODE	0.F23.B54	0.F23.B44
IODELAY[1]:IDELAY_MODE	0.F23.B19	0.F23.B9
NORMAL	0	0
PCI	1	1

IODELAY[0]:IODELAY_CHANGE	0.F28.B51
IODELAY[1]:IODELAY_CHANGE	0.F28.B12
CHANGE_ON_CLOCK	0
CHANGE_ON_DATA	1

IODELAY[0]:MODE	0.F29.B56	0.F23.B55	0.F29.B44	0.F29.B42
IODELAY[1]:MODE	0.F29.B7	0.F23.B8	0.F29.B21	0.F29.B19
IODRP2	0	0	0	0
IODELAY2	0	0	1	1
IODRP2_MCB	1	1	0	0

IODELAY[0]:MUX.IOCLK	0.F26.B3
IODELAY[1]:MUX.IOCLK	0.F26.B1
ILOGIC_CLK	0
OLOGIC_CLK	1

IODELAY_COMMON:MCB_ADDRESS	0.F25.B47	0.F25.B39	0.F25.B26	0.F25.B24
OLOGIC[0]:TRAIN_PATTERN	0.F27.B3	0.F27.B13	0.F27.B17	0.F27.B16
OLOGIC[1]:TRAIN_PATTERN	0.F27.B30	0.F27.B31	0.F27.B32	0.F27.B33
non-inverted	[3]	[2]	[1]	[0]

IOI:MEM_PLL_POL_SEL	0.F25.B57
INVERTED	0
NOTINVERTED	1

IOICLK[0]:DDR_ALIGNMENT	0.F29.B54	0.F29.B55
IOICLK[1]:DDR_ALIGNMENT	0.F29.B9	0.F29.B8
NONE	0	0
CLK0	0	1
CLK1	1	0

IOICLK[0]:MUX.CE0	0.F29.B53	0.F29.B52	0.F29.B50
IOICLK[1]:MUX.CE0	0.F29.B10	0.F29.B11	0.F29.B13
NONE	0	0	0
IOCE0	0	0	1
IOCE2	0	1	0
PLLCE0	1	0	0

IOICLK[0]:MUX.CE1	0.F23.B53	0.F23.B52	0.F23.B51
IOICLK[1]:MUX.CE1	0.F23.B10	0.F23.B11	0.F23.B12
NONE	0	0	0
IOCE1	0	0	1
IOCE3	0	1	0
PLLCE1	1	0	0

IOICLK[0]:MUX.CLK0	0.F29.B37	0.F29.B35	0.F29.B36	0.F29.B32	0.F29.B33
IOICLK[1]:MUX.CLK0	0.F29.B26	0.F29.B28	0.F29.B27	0.F29.B31	0.F29.B30
NONE	0	0	0	0	0
IOCLK0	0	0	0	0	1
IOCLK2	0	0	0	1	0
PLLCLK0	0	0	1	0	0
CKINT0	0	1	0	0	0
CKINT1	1	0	0	0	0

IOICLK[0]:MUX.CLK1	0.F23.B35	0.F23.B37	0.F23.B36	0.F23.B32	0.F23.B33
IOICLK[1]:MUX.CLK1	0.F23.B28	0.F23.B26	0.F23.B27	0.F23.B31	0.F23.B30
NONE	0	0	0	0	0
IOCLK1	0	0	0	0	1
IOCLK3	0	0	0	1	0
PLLCLK1	0	0	1	0	0
CKINT0	0	1	0	0	0
CKINT1	1	0	0	0	0

IOICLK[0]:MUX.CLK2	0.F23.B40	0.F23.B39
IOICLK[1]:MUX.CLK2	0.F23.B23	0.F23.B24
NONE	0	0
PLLCLK0	0	1
PLLCLK1	1	0

IOICLK[0]:MUX.ICE	0.F29.B60	0.F29.B62	0.F29.B61
IOICLK[0]:MUX.OCE	0.F23.B59	0.F23.B61	0.F23.B60
IOICLK[1]:MUX.ICE	0.F29.B3	0.F29.B1	0.F29.B2
IOICLK[1]:MUX.OCE	0.F23.B4	0.F23.B2	0.F23.B3
NONE	0	0	0
CE0	0	0	1
CE1	0	1	0
DDR	1	0	0

IOICLK[0]:MUX.ICLK	0.F29.B48	0.F29.B49	0.F23.B46	0.F23.B47
IOICLK[0]:MUX.OCLK	0.F23.B49	0.F23.B50	0.F23.B45	0.F23.B48
IOICLK[1]:MUX.ICLK	0.F29.B15	0.F29.B14	0.F23.B17	0.F23.B16
IOICLK[1]:MUX.OCLK	0.F23.B14	0.F23.B13	0.F23.B18	0.F23.B15
NONE	0	0	0	0
CLK0	0	0	0	1
CLK1	0	0	1	0
CLK2	0	1	0	0
DDR	1	0	0	0

OLOGIC[0]:MUX.CLK	0.F26.B37	0.F26.B36
OLOGIC[1]:MUX.CLK	0.F26.B39	0.F26.B38
NONE	0	0
OCLK0	0	1
OCLK1	1	0

OLOGIC[0]:MUX.D	0.F27.B12
OLOGIC[0]:MUX.T	0.F27.B2
OLOGIC[1]:MUX.D	0.F27.B35
OLOGIC[1]:MUX.T	0.F27.B28
INT	0
MCB	1

OLOGIC[0]:MUX.OCE	0.F28.B43
OLOGIC[1]:MUX.OCE	0.F28.B20
INT	0
PCI_CE	1

OLOGIC[0]:MUX.REV	0.F22.B0
OLOGIC[0]:MUX.SR	0.F22.B1
OLOGIC[1]:MUX.REV	0.F22.B14
OLOGIC[1]:MUX.SR	0.F22.B15
GND	0
INT	1

OLOGIC[0]:MUX.TRAIN	0.F26.B47	0.F26.B45
OLOGIC[1]:MUX.TRAIN	0.F26.B48	0.F26.B44
GND	0	0
INT	0	1
MCB	1	0

OLOGIC[0]:OMUX	0.F28.B49
OLOGIC[1]:OMUX	0.F28.B14
OUTFF	0
D1	1

OLOGIC[0]:OUTPUT_MODE	0.F27.B0
SINGLE_ENDED	0
DIFFERENTIAL	1

OLOGIC[0]:TMUX	0.F28.B41
OLOGIC[1]:TMUX	0.F28.B22
TFF	0
T1	1

Tile IOB

Cells: 0

Bel IOB[0]

spartan6 IOB bel IOB[0]
Pin	Direction	Wires

Bel IOB[1]

spartan6 IOB bel IOB[1]
Pin	Direction	Wires

Bitstream

spartan6 IOB rect MAIN
Bit	Frame
Bit	F0
B0	-
B1	-
B2	-
B3	-
B4	-
B5	-
B6	-
B7	-
B8	-
B9	-
B10	-
B11	-
B12	-
B13	-
B14	-
B15	-
B16	-
B17	-
B18	-
B19	-
B20	-
B21	-
B22	-
B23	-
B24	-
B25	-
B26	-
B27	-
B28	-
B29	-
B30	-
B31	-
B32	-
B33	-
B34	-
B35	-
B36	-
B37	-
B38	-
B39	-
B40	-
B41	-
B42	-
B43	-
B44	-
B45	-
B46	-
B47	-
B48	-
B49	-
B50	-
B51	-
B52	-
B53	-
B54	-
B55	-
B56	-
B57	-
B58	-
B59	-
B60	-
B61	-
B62	-
B63	-
B64	-
B65	-
B66	-
B67	-
B68	-
B69	-
B70	-
B71	-
B72	-
B73	-
B74	-
B75	-
B76	-
B77	-
B78	-
B79	-
B80	-
B81	-
B82	-
B83	-
B84	-
B85	-
B86	-
B87	-
B88	-
B89	-
B90	-
B91	-
B92	-
B93	-
B94	-
B95	-
B96	-
B97	-
B98	-
B99	-
B100	-
B101	-
B102	-
B103	-
B104	-
B105	-
B106	-
B107	-
B108	-
B109	-
B110	-
B111	-
B112	-
B113	-
B114	-
B115	-
B116	-
B117	-
B118	-
B119	-
B120	-
B121	-
B122	-
B123	-
B124	-
B125	-
B126	-
B127	-

### Bitstream

spartan6 IOB rect R0
Bit	Frame
Bit	F0
B127	IOB[1]:OUTPUT_ENABLE
B126	-
B125	IOB[1]:INV.I
B124	IOB[1]:PCI_INPUT
B123	IOB[1]:VREF_HV
B122	IOB[1]:IBUF_MODE[2]
B121	IOB[1]:IBUF_MODE[1]
B120	IOB[1]:IBUF_MODE[0]
B119	IOB[1]:SUSPEND[4]
B118	IOB[1]:SUSPEND[3]
B117	IOB[1]:SUSPEND[2]
B116	IOB[1]:SUSPEND[1]
B115	IOB[1]:SUSPEND[0]
B114	IOB[1]:PULLTYPE[2]
B113	IOB[1]:PULLTYPE[1]
B112	IOB[1]:PULLTYPE[0]
B111	IOB[1]:PCI_CLAMP
B110	IOB[1]:OUTPUT_LOW_VOLTAGE
B109	IOB[1]:PRE_EMPHASIS
B108	-
B107	IOB[1]:DIFF_MODE[1]
B106	IOB[1]:DIFF_MODE[0]
B105	IOB[1]:LVDS_GROUP
B104	IOB[1]:DIFF_OUTPUT_ENABLE
B103	IOB[1]:NSLEW[3]
B102	~IOB[1]:NSLEW[2]
B101	IOB[1]:NSLEW[1]
B100	IOB[1]:NSLEW[0]
B99	IOB[1]:PSLEW[3]
B98	~IOB[1]:PSLEW[2]
B97	IOB[1]:PSLEW[1]
B96	IOB[1]:PSLEW[0]
B95	-
B94	IOB[1]:NTERM[6]
B93	IOB[1]:NTERM[5]
B92	IOB[1]:NTERM[4]
B91	IOB[1]:NTERM[3]
B90	IOB[1]:NTERM[2]
B89	IOB[1]:NTERM[1]
B88	IOB[1]:NTERM[0]
B87	-
B86	IOB[1]:NDRIVE[6]
B85	~IOB[1]:NDRIVE[5]
B84	IOB[1]:NDRIVE[4]
B83	IOB[1]:NDRIVE[3]
B82	~IOB[1]:NDRIVE[2]
B81	IOB[1]:NDRIVE[1]
B80	IOB[1]:NDRIVE[0]
B79	IOB[1]:TML
B78	-
B77	IOB[1]:PTERM[5]
B76	IOB[1]:PTERM[4]
B75	IOB[1]:PTERM[3]
B74	IOB[1]:PTERM[2]
B73	IOB[1]:PTERM[1]
B72	IOB[1]:PTERM[0]
B71	-
B70	-
B69	IOB[1]:PDRIVE[5]
B68	IOB[1]:PDRIVE[4]
B67	~IOB[1]:PDRIVE[3]
B66	IOB[1]:PDRIVE[2]
B65	~IOB[1]:PDRIVE[1]
B64	~IOB[1]:PDRIVE[0]
B63	IOB[0]:OUTPUT_ENABLE
B62	IOB[0]:VREF
B61	IOB[0]:INV.I
B60	IOB[0]:PCI_INPUT
B59	IOB[0]:VREF_HV
B58	IOB[0]:IBUF_MODE[2]
B57	IOB[0]:IBUF_MODE[1]
B56	IOB[0]:IBUF_MODE[0]
B55	IOB[0]:SUSPEND[4]
B54	IOB[0]:SUSPEND[3]
B53	IOB[0]:SUSPEND[2]
B52	IOB[0]:SUSPEND[1]
B51	IOB[0]:SUSPEND[0]
B50	IOB[0]:PULLTYPE[2]
B49	IOB[0]:PULLTYPE[1]
B48	IOB[0]:PULLTYPE[0]
B47	IOB[0]:PCI_CLAMP
B46	IOB[0]:OUTPUT_LOW_VOLTAGE
B45	IOB[0]:PRE_EMPHASIS
B44	-
B43	-
B42	-
B41	-
B40	IOB[0]:DIFF_TERM
B39	IOB[0]:NSLEW[3]
B38	~IOB[0]:NSLEW[2]
B37	IOB[0]:NSLEW[1]
B36	IOB[0]:NSLEW[0]
B35	IOB[0]:PSLEW[3]
B34	~IOB[0]:PSLEW[2]
B33	IOB[0]:PSLEW[1]
B32	IOB[0]:PSLEW[0]
B31	-
B30	IOB[0]:NTERM[6]
B29	IOB[0]:NTERM[5]
B28	IOB[0]:NTERM[4]
B27	IOB[0]:NTERM[3]
B26	IOB[0]:NTERM[2]
B25	IOB[0]:NTERM[1]
B24	IOB[0]:NTERM[0]
B23	-
B22	IOB[0]:NDRIVE[6]
B21	~IOB[0]:NDRIVE[5]
B20	IOB[0]:NDRIVE[4]
B19	IOB[0]:NDRIVE[3]
B18	~IOB[0]:NDRIVE[2]
B17	IOB[0]:NDRIVE[1]
B16	IOB[0]:NDRIVE[0]
B15	IOB[0]:TML
B14	-
B13	IOB[0]:PTERM[5]
B12	IOB[0]:PTERM[4]
B11	IOB[0]:PTERM[3]
B10	IOB[0]:PTERM[2]
B9	IOB[0]:PTERM[1]
B8	IOB[0]:PTERM[0]
B7	-
B6	-
B5	IOB[0]:PDRIVE[5]
B4	IOB[0]:PDRIVE[4]
B3	~IOB[0]:PDRIVE[3]
B2	IOB[0]:PDRIVE[2]
B1	~IOB[0]:PDRIVE[1]
B0	~IOB[0]:PDRIVE[0]

IOB[0]:DIFF_TERM	0.F0.B40
IOB[0]:INV.I	0.F0.B61
IOB[0]:OUTPUT_ENABLE	0.F0.B63
IOB[0]:OUTPUT_LOW_VOLTAGE	0.F0.B46
IOB[0]:PCI_CLAMP	0.F0.B47
IOB[0]:PCI_INPUT	0.F0.B60
IOB[0]:PRE_EMPHASIS	0.F0.B45
IOB[0]:TML	0.F0.B15
IOB[0]:VREF	0.F0.B62
IOB[0]:VREF_HV	0.F0.B59
IOB[1]:DIFF_OUTPUT_ENABLE	0.F0.B104
IOB[1]:INV.I	0.F0.B125
IOB[1]:LVDS_GROUP	0.F0.B105
IOB[1]:OUTPUT_ENABLE	0.F0.B127
IOB[1]:OUTPUT_LOW_VOLTAGE	0.F0.B110
IOB[1]:PCI_CLAMP	0.F0.B111
IOB[1]:PCI_INPUT	0.F0.B124
IOB[1]:PRE_EMPHASIS	0.F0.B109
IOB[1]:TML	0.F0.B79
IOB[1]:VREF_HV	0.F0.B123
non-inverted	[0]

IOB[0]:IBUF_MODE	0.F0.B58	0.F0.B57	0.F0.B56
IOB[1]:IBUF_MODE	0.F0.B122	0.F0.B121	0.F0.B120
NONE	0	0	0
BYPASS_T	0	0	1
BYPASS_O	0	1	0
CMOS_VCCINT	0	1	1
CMOS_VCCO	1	0	0
VREF	1	0	1
DIFF	1	1	0
CMOS_VCCAUX	1	1	1

IOB[0]:NDRIVE	0.F0.B22	0.F0.B21	0.F0.B20	0.F0.B19	0.F0.B18	0.F0.B17	0.F0.B16
IOB[1]:NDRIVE	0.F0.B86	0.F0.B85	0.F0.B84	0.F0.B83	0.F0.B82	0.F0.B81	0.F0.B80
mixed inversion	[6]	~[5]	[4]	[3]	~[2]	[1]	[0]

IOB[0]:NSLEW	0.F0.B39	0.F0.B38	0.F0.B37	0.F0.B36
IOB[0]:PSLEW	0.F0.B35	0.F0.B34	0.F0.B33	0.F0.B32
IOB[1]:NSLEW	0.F0.B103	0.F0.B102	0.F0.B101	0.F0.B100
IOB[1]:PSLEW	0.F0.B99	0.F0.B98	0.F0.B97	0.F0.B96
mixed inversion	[3]	~[2]	[1]	[0]

IOB[0]:NTERM	0.F0.B30	0.F0.B29	0.F0.B28	0.F0.B27	0.F0.B26	0.F0.B25	0.F0.B24
IOB[1]:NTERM	0.F0.B94	0.F0.B93	0.F0.B92	0.F0.B91	0.F0.B90	0.F0.B89	0.F0.B88
non-inverted	[6]	[5]	[4]	[3]	[2]	[1]	[0]

IOB[0]:PDRIVE	0.F0.B5	0.F0.B4	0.F0.B3	0.F0.B2	0.F0.B1	0.F0.B0
IOB[1]:PDRIVE	0.F0.B69	0.F0.B68	0.F0.B67	0.F0.B66	0.F0.B65	0.F0.B64
mixed inversion	[5]	[4]	~[3]	[2]	~[1]	~[0]

IOB[0]:PTERM	0.F0.B13	0.F0.B12	0.F0.B11	0.F0.B10	0.F0.B9	0.F0.B8
IOB[1]:PTERM	0.F0.B77	0.F0.B76	0.F0.B75	0.F0.B74	0.F0.B73	0.F0.B72
non-inverted	[5]	[4]	[3]	[2]	[1]	[0]

IOB[0]:PULLTYPE	0.F0.B50	0.F0.B49	0.F0.B48
IOB[1]:PULLTYPE	0.F0.B114	0.F0.B113	0.F0.B112
PULLDOWN	0	0	0
NONE	0	0	1
PULLUP	0	1	1
KEEPER	1	0	1

IOB[0]:SUSPEND	0.F0.B55	0.F0.B54	0.F0.B53	0.F0.B52	0.F0.B51
IOB[1]:SUSPEND	0.F0.B119	0.F0.B118	0.F0.B117	0.F0.B116	0.F0.B115
3STATE	0	0	0	0	0
DRIVE_LAST_VALUE	0	0	0	0	1
3STATE_PULLDOWN	0	0	0	1	0
3STATE_PULLUP	0	0	1	0	0
3STATE_KEEPER	0	1	0	0	0
3STATE_OCT_ON	1	0	0	0	0

IOB[1]:DIFF_MODE	0.F0.B107	0.F0.B106
NONE	0	0
LVDS	0	1
TMDS	1	0

Tile IOI_CLK_WE

Cells: 0

Bel IOI_CLK_WE

spartan6 IOI_CLK_WE bel IOI_CLK_WE
Pin	Direction	Wires

Bel IOI_CLK_WE_TERM

spartan6 IOI_CLK_WE bel IOI_CLK_WE_TERM
Pin	Direction	Wires

Tile IOI_CLK_SN

Cells: 0

Bel IOI_CLK_SN

spartan6 IOI_CLK_SN bel IOI_CLK_SN
Pin	Direction	Wires

Tile CLKPIN_BUF

Cells: 0

Bel CLKPIN_BUF

spartan6 CLKPIN_BUF bel CLKPIN_BUF
Pin	Direction	Wires

Tables

Name	IOSTD:PDRIVE						IOSTD:NDRIVE
Name	[5]	[4]	[3]	[2]	[1]	[0]	[6]	[5]	[4]	[3]	[2]	[1]	[0]
BLVDS_25.2.5	0	1	1	1	1	1	1	1	1	1	1	1	1
BLVDS_25.3.3	0	1	1	1	1	1	1	1	1	1	1	1	1
DIFF_MOBILE_DDR.2.5	0	0	1	0	0	0	0	0	1	0	0	0	1
DIFF_MOBILE_DDR.3.3	0	0	1	0	0	0	0	0	0	1	1	0	1
DISPLAY_PORT.2.5	0	0	1	0	0	0	0	1	1	1	0	0	0
DISPLAY_PORT.3.3	0	0	1	0	0	0	0	0	1	1	1	0	0
HSTL_I.2.5	0	1	0	1	1	0	0	1	0	0	1	0	0
HSTL_I.3.3	0	1	0	1	1	0	0	0	1	1	1	0	0
HSTL_II.2.5	1	0	1	0	1	1	1	0	0	0	1	1	1
HSTL_II.3.3	1	0	1	0	1	1	0	1	1	1	0	0	0
HSTL_III.2.5	0	1	0	1	1	0	1	1	0	1	0	1	0
HSTL_III.3.3	0	1	0	1	1	0	1	0	1	0	0	1	1
HSTL_III_18.2.5	0	1	0	1	1	0	1	1	1	1	1	1	1
HSTL_III_18.3.3	0	1	0	1	1	0	1	1	0	1	0	0	0
HSTL_II_18.2.5	1	0	1	1	0	0	1	1	0	0	0	1	0
HSTL_II_18.3.3	1	0	1	1	0	0	1	0	0	1	1	0	0
HSTL_I_18.2.5	0	1	0	1	1	0	0	1	1	0	0	0	1
HSTL_I_18.3.3	0	1	0	1	1	0	0	1	0	0	1	1	0
I2C.2.5	0	0	0	0	0	0	0	0	1	0	0	0	0
I2C.3.3	0	0	0	0	0	0	0	0	0	1	0	0	0
LVCMOS12.12.2.5	1	1	0	1	0	0	0	1	1	0	1	0	1
LVCMOS12.12.3.3	1	1	0	1	0	0	0	1	0	1	0	1	0
LVCMOS12.2.2.5	0	0	1	0	0	1	0	0	0	1	0	0	1
LVCMOS12.2.3.3	0	0	1	0	0	1	0	0	0	0	1	1	1
LVCMOS12.4.2.5	0	1	0	0	1	0	0	0	1	0	0	1	0
LVCMOS12.4.3.3	0	1	0	0	1	0	0	0	0	1	1	1	0
LVCMOS12.6.2.5	0	1	1	0	1	0	0	0	1	1	0	1	1
LVCMOS12.6.3.3	0	1	1	0	1	0	0	0	1	0	1	0	1
LVCMOS12.8.2.5	1	0	0	0	1	1	0	1	0	0	1	0	0
LVCMOS12.8.3.3	1	0	0	0	1	1	0	0	1	1	1	0	0
LVCMOS12_JEDEC.12.2.5	1	1	0	1	0	0	0	1	1	0	1	0	1
LVCMOS12_JEDEC.12.3.3	1	1	0	1	0	0	0	1	0	1	0	1	0
LVCMOS12_JEDEC.2.2.5	0	0	1	0	0	1	0	0	0	1	0	0	1
LVCMOS12_JEDEC.2.3.3	0	0	1	0	0	1	0	0	0	0	1	1	1
LVCMOS12_JEDEC.4.2.5	0	1	0	0	1	0	0	0	1	0	0	1	0
LVCMOS12_JEDEC.4.3.3	0	1	0	0	1	0	0	0	0	1	1	1	0
LVCMOS12_JEDEC.6.2.5	0	1	1	0	1	0	0	0	1	1	0	1	1
LVCMOS12_JEDEC.6.3.3	0	1	1	0	1	0	0	0	1	0	1	0	1
LVCMOS12_JEDEC.8.2.5	1	0	0	0	1	1	0	1	0	0	1	0	0
LVCMOS12_JEDEC.8.3.3	1	0	0	0	1	1	0	0	1	1	1	0	0
LVCMOS15.12.2.5	1	0	0	1	0	0	0	1	1	1	1	0	0
LVCMOS15.12.3.3	1	0	0	1	0	0	0	1	0	1	1	1	1
LVCMOS15.16.2.5	1	0	1	1	1	1	1	0	0	1	1	1	1
LVCMOS15.16.3.3	1	0	1	1	1	1	0	1	1	1	1	1	1
LVCMOS15.2.2.5	0	0	0	1	1	0	0	0	0	1	0	1	0
LVCMOS15.2.3.3	0	0	0	1	1	0	0	0	0	1	0	0	0
LVCMOS15.4.2.5	0	0	1	1	0	0	0	0	1	0	1	0	0
LVCMOS15.4.3.3	0	0	1	1	0	0	0	0	1	0	0	0	0
LVCMOS15.6.2.5	0	1	0	0	1	0	0	0	1	1	1	1	0
LVCMOS15.6.3.3	0	1	0	0	1	0	0	0	1	1	0	0	0
LVCMOS15.8.2.5	0	1	1	0	0	0	0	1	0	1	0	0	0
LVCMOS15.8.3.3	0	1	1	0	0	0	0	1	0	0	0	0	0
LVCMOS15_JEDEC.12.2.5	1	0	0	1	0	0	0	1	1	1	1	0	0
LVCMOS15_JEDEC.12.3.3	1	0	0	1	0	0	0	1	0	1	1	1	1
LVCMOS15_JEDEC.16.2.5	1	0	1	1	1	1	1	0	0	1	1	1	1
LVCMOS15_JEDEC.16.3.3	1	0	1	1	1	1	0	1	1	1	1	1	1
LVCMOS15_JEDEC.2.2.5	0	0	0	1	1	0	0	0	0	1	0	1	0
LVCMOS15_JEDEC.2.3.3	0	0	0	1	1	0	0	0	0	1	0	0	0
LVCMOS15_JEDEC.4.2.5	0	0	1	1	0	0	0	0	1	0	1	0	0
LVCMOS15_JEDEC.4.3.3	0	0	1	1	0	0	0	0	1	0	0	0	0
LVCMOS15_JEDEC.6.2.5	0	1	0	0	1	0	0	0	1	1	1	1	0
LVCMOS15_JEDEC.6.3.3	0	1	0	0	1	0	0	0	1	1	0	0	0
LVCMOS15_JEDEC.8.2.5	0	1	1	0	0	0	0	1	0	1	0	0	0
LVCMOS15_JEDEC.8.3.3	0	1	1	0	0	0	0	1	0	0	0	0	0
LVCMOS18.12.2.5	0	1	0	1	1	1	0	1	1	0	0	0	1
LVCMOS18.12.3.3	0	1	0	1	1	1	0	1	0	0	1	1	0
LVCMOS18.16.2.5	0	1	1	1	1	1	1	0	0	0	0	0	1
LVCMOS18.16.3.3	0	1	1	1	1	1	0	1	1	0	0	1	0
LVCMOS18.2.2.5	0	0	0	1	0	0	0	0	0	1	0	0	1
LVCMOS18.2.3.3	0	0	0	1	0	0	0	0	0	0	1	1	1
LVCMOS18.24.2.5	1	0	1	1	1	0	1	1	0	0	0	0	1
LVCMOS18.24.3.3	1	0	1	1	1	0	1	0	0	1	0	1	1
LVCMOS18.4.2.5	0	0	1	0	0	0	0	0	1	0	0	0	1
LVCMOS18.4.3.3	0	0	1	0	0	0	0	0	0	1	1	0	1
LVCMOS18.6.2.5	0	0	1	1	0	0	0	0	1	1	0	0	1
LVCMOS18.6.3.3	0	0	1	1	0	0	0	0	1	0	0	1	1
LVCMOS18.8.2.5	0	1	0	0	0	0	0	1	0	0	0	0	1
LVCMOS18.8.3.3	0	1	0	0	0	0	0	0	1	1	0	0	1
LVCMOS18_JEDEC.12.2.5	0	1	0	1	1	1	0	1	1	0	0	0	1
LVCMOS18_JEDEC.12.3.3	0	1	0	1	1	1	0	1	0	0	1	1	0
LVCMOS18_JEDEC.16.2.5	0	1	1	1	1	1	1	0	0	0	0	0	1
LVCMOS18_JEDEC.16.3.3	0	1	1	1	1	1	0	1	1	0	0	1	0
LVCMOS18_JEDEC.2.2.5	0	0	0	1	0	0	0	0	0	1	0	0	1
LVCMOS18_JEDEC.2.3.3	0	0	0	1	0	0	0	0	0	0	1	1	1
LVCMOS18_JEDEC.24.2.5	1	0	1	1	1	0	1	1	0	0	0	0	1
LVCMOS18_JEDEC.24.3.3	1	0	1	1	1	0	1	0	0	1	0	1	1
LVCMOS18_JEDEC.4.2.5	0	0	1	0	0	0	0	0	1	0	0	0	1
LVCMOS18_JEDEC.4.3.3	0	0	1	0	0	0	0	0	0	1	1	0	1
LVCMOS18_JEDEC.6.2.5	0	0	1	1	0	0	0	0	1	1	0	0	1
LVCMOS18_JEDEC.6.3.3	0	0	1	1	0	0	0	0	1	0	0	1	1
LVCMOS18_JEDEC.8.2.5	0	1	0	0	0	0	0	1	0	0	0	0	1
LVCMOS18_JEDEC.8.3.3	0	1	0	0	0	0	0	0	1	1	0	0	1
LVCMOS25.12.2.5	0	1	0	0	0	1	0	1	1	0	1	0	1
LVCMOS25.12.3.3	0	1	0	0	0	1	0	1	0	1	0	1	0
LVCMOS25.16.2.5	0	1	0	1	1	0	1	0	0	0	1	1	1
LVCMOS25.16.3.3	0	1	0	1	1	0	0	1	1	1	0	0	0
LVCMOS25.2.2.5	0	0	0	0	1	1	0	0	0	1	0	0	1
LVCMOS25.2.3.3	0	0	0	0	1	1	0	0	0	0	1	1	1
LVCMOS25.24.2.5	1	0	0	0	0	1	1	1	0	1	0	1	0
LVCMOS25.24.3.3	1	0	0	0	0	1	1	0	1	0	0	1	1
LVCMOS25.4.2.5	0	0	0	1	1	0	0	0	1	0	0	1	0
LVCMOS25.4.3.3	0	0	0	1	1	0	0	0	0	1	1	1	0
LVCMOS25.6.2.5	0	0	1	0	0	1	0	0	1	1	0	1	1
LVCMOS25.6.3.3	0	0	1	0	0	1	0	0	1	0	1	0	1
LVCMOS25.8.2.5	0	0	1	0	1	1	0	1	0	0	1	0	0
LVCMOS25.8.3.3	0	0	1	0	1	1	0	0	1	1	1	0	0
LVCMOS33.12.2.5	0	0	1	1	0	1	0	1	1	0	1	0	1
LVCMOS33.12.3.3	0	0	1	1	0	1	0	1	0	1	0	1	0
LVCMOS33.16.2.5	0	1	0	0	1	0	1	0	0	0	1	1	1
LVCMOS33.16.3.3	0	1	0	0	1	0	0	1	1	1	0	0	0
LVCMOS33.2.2.5	0	0	0	0	1	1	0	0	0	1	0	0	1
LVCMOS33.2.3.3	0	0	0	0	1	1	0	0	0	0	1	1	1
LVCMOS33.24.2.5	0	1	1	0	1	0	1	1	0	1	0	1	0
LVCMOS33.24.3.3	0	1	1	0	1	0	1	0	1	0	0	1	1
LVCMOS33.4.2.5	0	0	0	1	0	1	0	0	1	0	0	1	0
LVCMOS33.4.3.3	0	0	0	1	0	1	0	0	0	1	1	1	0
LVCMOS33.6.2.5	0	0	0	1	1	1	0	0	1	1	0	1	1
LVCMOS33.6.3.3	0	0	0	1	1	1	0	0	1	0	1	0	1
LVCMOS33.8.2.5	0	0	1	0	0	1	0	1	0	0	1	0	0
LVCMOS33.8.3.3	0	0	1	0	0	1	0	0	1	1	1	0	0
LVTTL.12.2.5	0	0	1	0	1	0	0	1	1	0	1	0	1
LVTTL.12.3.3	0	0	1	0	1	0	0	1	0	1	0	1	0
LVTTL.16.2.5	0	0	1	1	0	1	1	0	0	0	1	1	1
LVTTL.16.3.3	0	0	1	1	0	1	0	1	1	1	0	0	0
LVTTL.2.2.5	0	0	0	0	1	0	0	0	0	1	0	0	1
LVTTL.2.3.3	0	0	0	0	1	0	0	0	0	0	1	1	1
LVTTL.24.2.5	0	1	0	0	1	1	1	1	0	1	0	1	0
LVTTL.24.3.3	0	1	0	0	1	1	1	0	1	0	0	1	1
LVTTL.4.2.5	0	0	0	1	0	0	0	0	1	0	0	1	0
LVTTL.4.3.3	0	0	0	1	0	0	0	0	0	1	1	1	0
LVTTL.6.2.5	0	0	0	1	0	1	0	0	1	1	0	1	1
LVTTL.6.3.3	0	0	0	1	0	1	0	0	1	0	1	0	1
LVTTL.8.2.5	0	0	0	1	1	1	0	1	0	0	1	0	0
LVTTL.8.3.3	0	0	0	1	1	1	0	0	1	1	1	0	0
MOBILE_DDR.2.5	0	1	0	0	0	0	0	0	1	1	0	1	1
MOBILE_DDR.3.3	0	1	0	0	0	0	0	0	1	0	1	0	0
OFF	0	0	0	0	0	0	0	0	0	0	0	0	0
PCI33_3.3.3	0	1	1	0	0	1	1	0	1	0	0	0	0
PCI66_3.3.3	0	1	1	0	0	1	1	0	1	0	0	0	0
SDIO.2.5	0	0	1	0	0	1	0	1	0	0	1	0	0
SDIO.3.3	0	0	1	0	0	1	0	0	1	1	1	0	0
SMBUS.2.5	0	0	0	0	0	0	0	0	1	0	0	1	0
SMBUS.3.3	0	0	0	0	0	0	0	0	0	1	1	1	0
SSTL15_II.2.5	1	0	1	1	0	1	1	0	1	0	0	0	0
SSTL15_II.3.3	1	0	1	1	0	1	1	0	0	0	0	0	0
SSTL18_I.2.5	0	0	1	1	1	0	0	0	1	1	1	1	0
SSTL18_I.3.3	0	0	1	1	1	0	0	0	1	1	0	0	0
SSTL18_II.2.5	1	0	0	1	0	1	1	0	1	0	0	1	1
SSTL18_II.3.3	1	0	0	1	0	1	1	0	0	0	0	1	0
SSTL2_I.2.5	0	0	1	0	0	1	0	0	1	1	1	0	0
SSTL2_I.3.3	0	0	1	0	0	1	0	0	1	0	1	1	0
SSTL2_II.2.5	0	1	1	0	0	1	1	0	0	1	1	1	1
SSTL2_II.3.3	0	1	1	0	0	1	0	1	1	1	1	1	0
SSTL3_I.2.5	0	0	0	1	0	1	0	0	1	1	0	0	0
SSTL3_I.3.3	0	0	0	1	0	1	0	0	1	0	0	1	0
SSTL3_II.2.5	0	0	1	0	1	0	0	1	1	1	1	0	0
SSTL3_II.3.3	0	0	1	0	1	0	0	1	0	1	1	1	0
TML_33.3.3	0	0	0	1	1	0	0	0	0	0	0	0	0
UNTUNED_25.1200.2.5	1	0	0	0	1	0	0	1	0	0	1	0	0
UNTUNED_25.1200.3.3	1	0	0	0	1	0	0	0	1	1	1	1	1
UNTUNED_25.1500.2.5	0	1	1	0	1	0	0	1	0	0	1	0	1
UNTUNED_25.1500.3.3	0	1	1	0	1	0	0	0	1	1	1	1	1
UNTUNED_25.1800.2.5	0	1	0	1	0	1	0	1	0	0	1	1	0
UNTUNED_25.1800.3.3	0	1	0	1	0	1	0	1	0	0	0	0	0
UNTUNED_25.2500.2.5	0	1	0	0	0	0	0	1	0	1	0	0	1
UNTUNED_25.2500.3.3	0	1	0	0	0	0	0	1	0	0	0	1	0
UNTUNED_25.3300.2.5	0	0	1	1	0	1	0	1	0	1	1	0	1
UNTUNED_25.3300.3.3	0	0	1	1	0	1	0	1	0	0	1	0	0
UNTUNED_50.1200.2.5	0	1	0	0	0	1	0	0	1	0	0	1	0
UNTUNED_50.1200.3.3	0	1	0	0	0	1	0	0	0	1	1	1	1
UNTUNED_50.1500.2.5	0	0	1	1	0	1	0	0	1	0	0	1	0
UNTUNED_50.1500.3.3	0	0	1	1	0	1	0	0	0	1	1	1	1
UNTUNED_50.1800.2.5	0	0	1	0	1	0	0	0	1	0	0	1	1
UNTUNED_50.1800.3.3	0	0	1	0	1	0	0	0	1	0	0	0	0
UNTUNED_50.2500.2.5	0	0	1	0	0	0	0	0	1	0	1	0	0
UNTUNED_50.2500.3.3	0	0	1	0	0	0	0	0	1	0	0	0	1
UNTUNED_50.3300.2.5	0	0	0	1	1	0	0	0	1	0	1	1	0
UNTUNED_50.3300.3.3	0	0	0	1	1	0	0	0	1	0	0	1	0
UNTUNED_75.1200.2.5	0	0	1	0	1	1	0	0	0	1	1	0	0
UNTUNED_75.1200.3.3	0	0	1	0	1	1	0	0	0	1	0	1	0
UNTUNED_75.1500.2.5	0	0	1	0	0	0	0	0	0	1	1	0	0
UNTUNED_75.1500.3.3	0	0	1	0	0	0	0	0	0	1	0	1	0
UNTUNED_75.1800.2.5	0	0	0	1	1	1	0	0	0	1	1	0	0
UNTUNED_75.1800.3.3	0	0	0	1	1	1	0	0	0	1	0	1	0
UNTUNED_75.2500.2.5	0	0	0	1	0	1	0	0	0	1	1	0	1
UNTUNED_75.2500.3.3	0	0	0	1	0	1	0	0	0	1	0	1	1
UNTUNED_75.3300.2.5	0	0	0	1	0	0	0	0	0	1	1	1	1
UNTUNED_75.3300.3.3	0	0	0	1	0	0	0	0	0	1	1	0	0

Name	IOSTD:PTERM						IOSTD:NTERM
Name	[5]	[4]	[3]	[2]	[1]	[0]	[6]	[5]	[4]	[3]	[2]	[1]	[0]
OFF	0	0	0	0	0	0	0	0	0	0	0	0	0
TML_33.3.3	0	0	0	1	1	0	0	0	0	0	0	0	0
UNTUNED_SPLIT_25.1200.2.5	1	0	1	0	1	1	0	0	1	1	1	1	1
UNTUNED_SPLIT_25.1200.3.3	1	0	1	0	0	0	0	0	1	1	0	1	0
UNTUNED_SPLIT_25.1500.2.5	1	0	0	0	0	0	0	1	0	0	1	0	0
UNTUNED_SPLIT_25.1500.3.3	0	1	1	1	0	1	0	0	1	1	0	1	1
UNTUNED_SPLIT_25.1800.2.5	0	1	1	0	1	1	0	1	0	1	0	1	1
UNTUNED_SPLIT_25.1800.3.3	0	1	1	0	0	0	0	0	1	1	1	0	1
UNTUNED_SPLIT_25.2500.2.5	0	1	1	0	0	0	1	0	0	0	0	0	0
UNTUNED_SPLIT_25.2500.3.3	0	1	0	1	0	0	0	1	0	1	0	0	1
UNTUNED_SPLIT_25.3300.2.5	0	1	1	0	0	0	1	0	1	1	0	1	1
UNTUNED_SPLIT_25.3300.3.3	0	1	0	1	0	0	0	1	1	1	0	1	0
UNTUNED_SPLIT_50.1200.2.5	0	1	0	1	0	1	0	0	0	1	1	1	1
UNTUNED_SPLIT_50.1200.3.3	0	1	0	1	0	0	0	0	0	1	1	0	0
UNTUNED_SPLIT_50.1500.2.5	0	1	0	0	0	0	0	0	1	0	0	1	0
UNTUNED_SPLIT_50.1500.3.3	0	0	1	1	1	1	0	0	0	1	1	0	1
UNTUNED_SPLIT_50.1800.2.5	0	0	1	1	1	0	0	0	1	0	1	0	1
UNTUNED_SPLIT_50.1800.3.3	0	0	1	1	0	0	0	0	0	1	1	1	0
UNTUNED_SPLIT_50.2500.2.5	0	0	1	1	0	0	0	1	0	0	0	0	0
UNTUNED_SPLIT_50.2500.3.3	0	0	1	0	1	0	0	0	1	0	0	1	1
UNTUNED_SPLIT_50.3300.2.5	0	0	1	1	0	0	0	1	0	1	1	1	0
UNTUNED_SPLIT_50.3300.3.3	0	0	1	0	1	0	0	0	1	1	1	0	0
UNTUNED_SPLIT_75.1200.2.5	0	0	1	1	1	0	0	0	0	1	0	1	0
UNTUNED_SPLIT_75.1200.3.3	0	0	1	1	1	0	0	0	0	1	0	0	1
UNTUNED_SPLIT_75.1500.2.5	0	0	1	0	1	0	0	0	0	1	0	1	1
UNTUNED_SPLIT_75.1500.3.3	0	0	1	0	0	1	0	0	0	1	0	0	1
UNTUNED_SPLIT_75.1800.2.5	0	0	1	0	0	1	0	0	0	1	1	1	0
UNTUNED_SPLIT_75.1800.3.3	0	0	1	0	0	0	0	0	0	1	0	1	0
UNTUNED_SPLIT_75.2500.2.5	0	0	1	0	0	0	0	0	1	0	1	0	0
UNTUNED_SPLIT_75.2500.3.3	0	0	0	1	1	1	0	0	0	1	1	0	1
UNTUNED_SPLIT_75.3300.2.5	0	0	1	0	0	0	0	0	1	1	1	1	0
UNTUNED_SPLIT_75.3300.3.3	0	0	0	1	1	1	0	0	1	0	0	1	1

Name	IOSTD:PSLEW				IOSTD:NSLEW
Name	[3]	[2]	[1]	[0]	[3]	[2]	[1]	[0]
BLVDS_25	1	0	0	0	1	0	0	0
DIFF_MOBILE_DDR	1	0	0	0	1	0	0	0
DISPLAY_PORT	1	0	0	0	1	0	0	0
HSTL_I	1	0	0	0	1	0	0	0
HSTL_II	1	0	0	0	1	0	0	0
HSTL_III	1	0	0	0	1	0	0	0
HSTL_III_18	1	0	0	0	1	0	0	0
HSTL_II_18	1	0	0	0	1	0	0	0
HSTL_I_18	1	0	0	0	1	0	0	0
I2C	0	1	0	0	0	1	0	0
IN_TERM	0	1	0	0	0	1	0	0
LVCMOS12.FAST	1	0	0	0	1	0	0	0
LVCMOS12.QUIETIO	0	0	1	0	0	0	1	0
LVCMOS12.SLOW	0	1	0	0	0	1	0	0
LVCMOS12_JEDEC.FAST	1	0	0	0	1	0	0	0
LVCMOS12_JEDEC.QUIETIO	0	0	1	0	0	0	1	0
LVCMOS12_JEDEC.SLOW	0	1	0	0	0	1	0	0
LVCMOS15.FAST	1	0	0	0	1	0	0	0
LVCMOS15.QUIETIO	0	0	1	0	0	0	1	0
LVCMOS15.SLOW	0	1	0	0	0	1	0	0
LVCMOS15_JEDEC.FAST	1	0	0	0	1	0	0	0
LVCMOS15_JEDEC.QUIETIO	0	0	1	0	0	0	1	0
LVCMOS15_JEDEC.SLOW	0	1	0	0	0	1	0	0
LVCMOS18.FAST	1	0	0	0	1	0	0	0
LVCMOS18.QUIETIO	0	0	1	0	0	0	1	0
LVCMOS18.SLOW	0	1	0	0	0	1	0	0
LVCMOS18_JEDEC.FAST	1	0	0	0	1	0	0	0
LVCMOS18_JEDEC.QUIETIO	0	0	1	0	0	0	1	0
LVCMOS18_JEDEC.SLOW	0	1	0	0	0	1	0	0
LVCMOS25.FAST	1	0	0	0	1	0	0	0
LVCMOS25.QUIETIO	0	0	1	0	0	0	1	0
LVCMOS25.SLOW	0	1	0	0	0	1	0	0
LVCMOS33.FAST	1	0	0	0	1	0	0	0
LVCMOS33.QUIETIO	0	0	1	0	0	0	1	0
LVCMOS33.SLOW	0	1	0	0	0	1	0	0
LVTTL.FAST	1	0	0	0	1	0	0	0
LVTTL.QUIETIO	0	0	1	0	0	0	1	0
LVTTL.SLOW	0	1	0	0	0	1	0	0
MOBILE_DDR	1	0	0	0	1	0	0	0
OFF	0	0	0	0	0	0	0	0
PCI33_3	0	0	0	1	0	0	0	1
PCI66_3	0	0	0	1	0	0	0	1
SDIO	0	1	0	0	0	1	0	0
SMBUS	0	1	0	0	0	1	0	0
SSTL15_II	1	1	1	1	1	1	1	1
SSTL18_I	1	0	0	0	1	0	0	0
SSTL18_II	1	0	0	0	1	0	0	0
SSTL2_I	1	0	0	0	1	0	0	0
SSTL2_II	1	0	0	0	1	0	0	0
SSTL3_I	1	0	0	0	1	0	0	0
SSTL3_II	1	0	0	0	1	0	0	0
TML_33	0	1	0	0	0	1	0	0

Name	IOSTD:LVDSBIAS
Name	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]
LVDS_25	1	0	0	0	1	0	1	1	1	0	0	1
LVDS_33	1	0	0	0	1	0	1	1	1	0	0	1
MINI_LVDS_25	0	1	1	1	1	1	0	1	0	0	0	1
MINI_LVDS_33	0	1	1	1	1	1	0	1	0	0	0	1
PPDS_25	0	1	0	0	0	0	1	1	0	1	1	1
PPDS_33	0	1	0	0	0	0	1	1	0	1	1	1
RSDS_25	1	0	0	0	1	0	0	1	0	1	0	1
RSDS_33	1	0	0	0	1	0	0	1	0	1	0	1
TMDS_33	1	0	1	0	0	1	1	0	0	1	0	1
TML_33	1	0	1	0	0	1	1	1	1	1	1	1

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