Keyboard shortcuts

Press ← or → to navigate between chapters

Press ? to show this help

Press Esc to hide this help

Input/Output

Bitstream — IOI.LR

spartan6 IOI.LR bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
63 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IFF_LATCH - - IODELAY0:ODELAY_VALUE_N[7] - IODELAY_COMMON:DIFF_PHASE_DETECTOR IODELAY0:CAL_DELAY_MAX[0] -
62 - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF_SR_SYNC IOICLK0:MUX.ICE[1] - IODELAY0:IDELAY_VALUE_N[7] - - IODELAY0:CAL_DELAY_MAX[1] -
61 - - - - - - - - - - - - - - - - - - - - - - - IOICLK0:MUX.ICE[0] IOICLK0:MUX.OCE[1] IODELAY0:ODELAY_VALUE_N[6] - - IODELAY0:CAL_DELAY_MAX[2] -
60 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DDR IOICLK0:MUX.ICE[2] IOICLK0:MUX.OCE[0] IODELAY0:IDELAY_VALUE_N[6] - - IODELAY0:CAL_DELAY_MAX[3] -
59 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IFF_REV_USED IODELAY0:ENABLE.ODATAIN IOICLK0:MUX.OCE[2] IODELAY0:ODELAY_VALUE_N[5] - - IODELAY0:CAL_DELAY_MAX[4] -
58 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.SR[0] ILOGIC0:TSBYPASS_MUX[0] IODELAY0:ENABLE.CIN[2] IODELAY0:IDELAY_VALUE_N[5] - - IODELAY0:CAL_DELAY_MAX[5] -
57 - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF_CE_ENABLE ~ILOGIC0:I_DELAY_ENABLE IODELAY0:ENABLE.CIN[1] IODELAY0:ODELAY_VALUE_N[4] IOI:MEM_PLL_DIV_EN - IODELAY0:CAL_DELAY_MAX[6] -
56 - - - - - - - - - - - - - - - - - - - - - - - IODELAY0:MODE[2] IODELAY0:DELAYCHAIN_OSC IODELAY0:IDELAY_VALUE_N[4] IOI:MEM_PLL_POL_SEL[0] - IODELAY0:CAL_DELAY_MAX[7] -
55 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IFF_SRVAL IOICLK0:DDR_ALIGNMENT[0] IODELAY0:MODE[3] IODELAY0:IDELAY_VALUE_N[3] IODELAY0:DIFF_PHASE_DETECTOR ILOGIC1:MUX.Q4[0] ~ILOGIC0:IFF_DELAY_ENABLE IODELAY0:DRP06[4] -
54 - - - - - - - - - - - - - - - - - - - - - - - IOICLK0:DDR_ALIGNMENT[1] IODELAY0:IDELAY_MODE[1] IODELAY0:ODELAY_VALUE_N[3] IODELAY0:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB[1] ILOGIC1:MUX.Q4[1] IODELAY0:DRP07[4] IODELAY0:LUMPED_DELAY_SELECT -
53 - - - - - - - - - - - - - - - - - - - - - - - IOICLK0:MUX.CE0[2] IOICLK0:MUX.CE1[2] IODELAY0:IDELAY_VALUE_N[2] - ILOGIC1:MUX.Q3[1] IODELAY0:DELAY_SRC[1] IODELAY0:DRP06[3] -
52 - - - - - - - - - - - - - - - - - - - - - - IODELAY0:IDELAY_FIXED IOICLK0:MUX.CE0[1] IOICLK0:MUX.CE1[1] IODELAY0:ODELAY_VALUE_N[2] - ILOGIC1:MUX.Q3[0] IODELAY0:DRP07[3] IODELAY0:LUMPED_DELAY -
51 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:ROW2_CLK_ENABLE - IOICLK0:MUX.CE1[0] IODELAY0:IDELAY_VALUE_N[1] IODELAY0:TEST_NCOUNTER ILOGIC1:MUX.Q2[0] IODELAY0:DRP07[2] IODELAY0:IODELAY_CHANGE[0] -
50 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:ROW1_CLK_ENABLE IOICLK0:MUX.CE0[0] IOICLK0:MUX.OCLK[2] IODELAY0:ODELAY_VALUE_N[1] - ILOGIC1:MUX.Q2[1] IODELAY0:DELAY_SRC[0] IODELAY0:DRP06[2] -
49 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:ROW3_CLK_ENABLE IOICLK0:MUX.ICLK[2] IOICLK0:MUX.OCLK[3] IODELAY0:IDELAY_VALUE_N[0] IODELAY0:TEST_PCOUNTER ILOGIC1:MUX.Q1[1] IODELAY0:DRP06[5] OLOGIC0:OMUX[0] -
48 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:ROW4_CLK_ENABLE IOICLK0:MUX.ICLK[3] IOICLK0:MUX.OCLK[0] IODELAY0:ODELAY_VALUE_N[0] - ILOGIC1:MUX.Q1[0] IODELAY0:DRP07[5] OLOGIC1:MUX.TRAIN[1]
47 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:ROW4_CLK_ENABLE - IOICLK0:MUX.ICLK[0] IODELAY0:ODELAY_VALUE_P[0] IODELAY_COMMON:MCB_ADDRESS[3] ILOGIC0:MUX.Q1[0] IODELAY0:DRP06[1] OLOGIC0:MUX.TRAIN[1]
46 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:ROW3_CLK_ENABLE - IOICLK0:MUX.ICLK[1] IODELAY0:IDELAY_VALUE_P[0] IODELAY_COMMON:DRP_FROM_MCB ILOGIC0:MUX.Q1[1] IODELAY0:COUNTER_WRAPAROUND[0] IODELAY0:DRP07[1] OLOGIC0:CASCADE_ENABLE
45 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:ROW1_CLK_ENABLE IODELAY0:TEST_GLITCH_FILTER IOICLK0:MUX.OCLK[1] IODELAY0:ODELAY_VALUE_P[1] - ILOGIC0:MUX.Q2[1] IODELAY0:DRP06[0] IODELAY0:PLUS1 OLOGIC0:MUX.TRAIN[0]
44 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:ROW2_CLK_ENABLE IODELAY0:MODE[1] IODELAY0:IDELAY_MODE[0] IODELAY0:IDELAY_VALUE_P[1] IODELAY0:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB[0] ILOGIC0:MUX.Q2[0] IODELAY0:DRP07[0] IODELAY0:IDELAY_FROM_HALF_MAX OLOGIC1:MUX.TRAIN[0]
43 - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.D[1] IODELAY0:ODELAY_VALUE_P[2] IODELAY_COMMON:ENFFSCAN_DRP[0] ILOGIC0:MUX.Q3[0] IODELAY0:DRP06[7] OLOGIC0:MUX.OCE[0] ILOGIC1:MUX.CLK[1]
42 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IFF_SR_USED IODELAY0:MODE[0] ILOGIC0:MUX.D[0] IODELAY0:IDELAY_VALUE_P[2] - ILOGIC0:MUX.Q3[1] IODELAY0:DRP07[7] ILOGIC1:MUX.CLK[0]
41 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IFF_INIT IOICLK0:DDR_ENABLE[1] IODELAY0:ENABLE.CIN[0] IODELAY0:ODELAY_VALUE_P[3] - ILOGIC0:MUX.Q4[1] IODELAY0:DRP06[6] OLOGIC0:TMUX[0] ILOGIC0:MUX.CLK[1]
40 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DDR IOICLK0:DDR_ENABLE[0] IOICLK0:MUX.CLK2[1] IODELAY0:IDELAY_VALUE_P[3] - ILOGIC0:MUX.Q4[0] IODELAY0:DRP07[6] ILOGIC0:MUX.CLK[0]
39 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_SR_USED IOICLK0:INV.CLK2 IOICLK0:MUX.CLK2[0] IODELAY0:IDELAY_VALUE_P[4] IODELAY_COMMON:MCB_ADDRESS[2] ILOGIC0:DATA_WIDTH_RELOAD[1] IODELAY0:DRP_ADDR[0] OLOGIC1:MUX.CLK[1]
38 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_INIT IOICLK0:INV.CLK0 IOICLK0:INV.CLK1 IODELAY0:ODELAY_VALUE_P[4] - ILOGIC0:DATA_WIDTH_RELOAD[0] IODELAY0:DRP_ADDR[1] OLOGIC1:MUX.CLK[0]
37 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_SRVAL IOICLK0:MUX.CLK0[4] IOICLK0:MUX.CLK1[3] IODELAY0:IDELAY_VALUE_P[5] - ILOGIC1:DATA_WIDTH_RELOAD[2] IODELAY0:DRP_ADDR[2] OLOGIC0:MUX.CLK[1]
36 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.SR[0] IOICLK0:MUX.CLK0[2] IOICLK0:MUX.CLK1[2] IODELAY0:ODELAY_VALUE_P[5] - ILOGIC1:DATA_WIDTH_RELOAD[1] IODELAY0:DRP_ADDR[3] OLOGIC0:MUX.CLK[0]
35 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_REV_USED IOICLK0:MUX.CLK0[3] IOICLK0:MUX.CLK1[4] IODELAY0:IDELAY_VALUE_P[6] - OLOGIC1:MUX.D[0] - ILOGIC1:ENABLE
34 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:CASCADE_ENABLE - - IODELAY0:ODELAY_VALUE_P[6] - OLOGIC1:OFF_RANK1_BYPASS - -
33 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_LATCH IOICLK0:MUX.CLK0[0] IOICLK0:MUX.CLK1[0] IODELAY0:IDELAY_VALUE_P[7] - OLOGIC1:TRAIN_PATTERN[0] - -
32 - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF_SR_SYNC IOICLK0:MUX.CLK0[1] IOICLK0:MUX.CLK1[1] IODELAY0:ODELAY_VALUE_P[7] - OLOGIC1:TRAIN_PATTERN[1] IODELAY0:DRP_ADDR[4] ILOGIC0:ENABLE
31 - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF_CE_ENABLE IOICLK1:MUX.CLK0[1] IOICLK1:MUX.CLK1[1] IODELAY1:ODELAY_VALUE_P[7] - OLOGIC1:TRAIN_PATTERN[2] IODELAY1:DRP_ADDR[4] OLOGIC1:ENABLE
30 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:CASCADE_ENABLE IOICLK1:MUX.CLK0[0] IOICLK1:MUX.CLK1[0] IODELAY1:IDELAY_VALUE_P[7] - OLOGIC1:TRAIN_PATTERN[3] - -
29 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:OFF_LATCH - - IODELAY1:ODELAY_VALUE_P[6] - OLOGIC1:DDR_OPPOSITE_EDGE - -
28 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:OFF_SR_ENABLE IOICLK1:MUX.CLK0[3] IOICLK1:MUX.CLK1[4] IODELAY1:IDELAY_VALUE_P[6] IODELAY_COMMON:DRP_ENABLE OLOGIC1:MUX.T[0] - OLOGIC0:ENABLE
27 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:OFF_REV_ENABLE IOICLK1:MUX.CLK0[2] IOICLK1:MUX.CLK1[2] IODELAY1:ODELAY_VALUE_P[5] - OLOGIC1:OFF_CE_ENABLE IODELAY1:DRP_ADDR[3] OLOGIC0:ENABLE.IOCE
26 - - - - - - - - - - - - - - - - - - - - - - ~OLOGIC1:OFF_SR_SYNC IOICLK1:MUX.CLK0[4] IOICLK1:MUX.CLK1[3] IODELAY1:IDELAY_VALUE_P[5] IODELAY_COMMON:MCB_ADDRESS[1] OLOGIC1:OFF_CE_OR_DDR IODELAY1:DRP_ADDR[2] ILOGIC0:ENABLE.IOCE
25 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:OFF_INIT IOICLK1:INV.CLK0 IOICLK1:INV.CLK1 IODELAY1:ODELAY_VALUE_P[4] - OLOGIC1:OFF_RANK1_CLK_ENABLE IODELAY1:DRP_ADDR[1] OLOGIC1:ENABLE.IOCE
24 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:OFF_SRVAL IOICLK1:INV.CLK2 IOICLK1:MUX.CLK2[0] IODELAY1:IDELAY_VALUE_P[4] IODELAY_COMMON:MCB_ADDRESS[0] OLOGIC1:OFF_RANK2_CLK_ENABLE IODELAY1:DRP_ADDR[0] ILOGIC1:ENABLE.IOCE
23 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:TFF_SRVAL IOICLK1:DDR_ENABLE[1] IOICLK1:MUX.CLK2[1] IODELAY1:IDELAY_VALUE_P[3] - OLOGIC1:TFF_RANK2_CLK_ENABLE IODELAY1:DRP07[6] ILOGIC0:DATA_WIDTH_START[1]
22 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:TFF_INIT IOICLK1:DDR_ENABLE[0] IODELAY1:ENABLE.CIN[2] IODELAY1:ODELAY_VALUE_P[3] - OLOGIC1:TFF_RANK1_CLK_ENABLE IODELAY1:DRP06[6] OLOGIC1:TMUX[0] ILOGIC0:BITSLIP_ENABLE
21 - - - - - - - - - - - - - - - - - - - - - - ~OLOGIC1:TFF_SR_SYNC IODELAY1:MODE[1] - IODELAY1:IDELAY_VALUE_P[2] - OLOGIC1:TFF_CE_OR_DDR IODELAY1:DRP07[7] ILOGIC0:DATA_WIDTH_START[0]
20 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:TFF_REV_ENABLE - - IODELAY1:ODELAY_VALUE_P[2] IODELAY1:DIFF_PHASE_DETECTOR OLOGIC1:TFF_CE_ENABLE IODELAY1:DRP06[7] OLOGIC1:MUX.OCE[0] ILOGIC1:DATA_WIDTH_START[0]
19 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:TFF_SR_ENABLE IODELAY1:MODE[0] IODELAY1:IDELAY_MODE[1] IODELAY1:IDELAY_VALUE_P[1] IODELAY1:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB[1] OLOGIC1:TFF_RANK1_BYPASS IODELAY1:DRP07[0] IODELAY1:IDELAY_FROM_HALF_MAX ILOGIC1:DATA_WIDTH_START[1]
18 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:TFF_LATCH IODELAY1:TEST_GLITCH_FILTER IOICLK1:MUX.OCLK[1] IODELAY1:ODELAY_VALUE_P[1] - ILOGIC1:DATA_WIDTH_RELOAD[0] IODELAY1:DRP06[0] IODELAY1:EVENT_SEL[0] ILOGIC1:DATA_WIDTH_START[2]
17 - - - - - - - - - - - - - - - - - - - - - - - - IOICLK1:MUX.ICLK[1] IODELAY1:IDELAY_VALUE_P[0] - OLOGIC0:TRAIN_PATTERN[1] IODELAY1:COUNTER_WRAPAROUND[0] IODELAY1:DRP07[1] ILOGIC1:BITSLIP_ENABLE
16 - - - - - - - - - - - - - - - - - - - - - - IODELAY1:IDELAY_FIXED - IOICLK1:MUX.ICLK[0] IODELAY1:ODELAY_VALUE_P[0] - OLOGIC0:TRAIN_PATTERN[0] IODELAY1:DRP06[1] IODELAY1:EVENT_SEL[1] ILOGIC1:CASCADE_ENABLE
15 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.SR[0] IOICLK1:MUX.ICLK[3] IOICLK1:MUX.OCLK[0] IODELAY1:ODELAY_VALUE_N[0] - OLOGIC0:OFF_RANK1_BYPASS IODELAY1:DRP07[5] OLOGIC1:MISR_ENABLE_DATA
14 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.REV[0] IOICLK1:MUX.ICLK[2] IOICLK1:MUX.OCLK[3] IODELAY1:IDELAY_VALUE_N[0] - OLOGIC0:DDR_OPPOSITE_EDGE IODELAY1:DRP06[5] OLOGIC1:OMUX[0] OLOGIC1:MISR_ENABLE_CLK
13 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:OFF_LATCH IOICLK1:MUX.CE0[0] IOICLK1:MUX.OCLK[2] IODELAY1:ODELAY_VALUE_N[1] - OLOGIC0:TRAIN_PATTERN[2] IODELAY1:DELAY_SRC[0] IODELAY1:DRP06[2] OLOGIC0:MISR_ENABLE_CLK
12 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:OFF_SR_ENABLE - IOICLK1:MUX.CE1[0] IODELAY1:IDELAY_VALUE_N[1] IODELAY1:TEST_NCOUNTER OLOGIC0:MUX.D[0] IODELAY1:DRP07[2] IODELAY1:IODELAY_CHANGE[0] OLOGIC0:MISR_ENABLE_DATA
11 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:OFF_REV_ENABLE IOICLK1:MUX.CE0[1] IOICLK1:MUX.CE1[1] IODELAY1:ODELAY_VALUE_N[2] - OLOGIC0:OFF_CE_ENABLE IODELAY1:DRP07[3] IODELAY1:LUMPED_DELAY OLOGIC1:MISR_RESET
10 - - - - - - - - - - - - - - - - - - - - - - ~OLOGIC0:OFF_SR_SYNC IOICLK1:MUX.CE0[2] IOICLK1:MUX.CE1[2] IODELAY1:IDELAY_VALUE_N[2] - OLOGIC0:OFF_CE_OR_DDR IODELAY1:DELAY_SRC[1] IODELAY1:DRP06[3] OLOGIC0:MISR_RESET
9 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:OFF_INIT IOICLK1:DDR_ALIGNMENT[1] IODELAY1:IDELAY_MODE[0] IODELAY1:ODELAY_VALUE_N[3] IODELAY1:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB[0] OLOGIC0:OFF_RANK1_CLK_ENABLE IODELAY1:DRP07[4] IODELAY1:LUMPED_DELAY_SELECT IODELAY_COMMON:ENFFSCAN_DRP[1]
8 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:OFF_SRVAL IOICLK1:DDR_ALIGNMENT[0] IODELAY1:MODE[3] IODELAY1:IDELAY_VALUE_N[3] - OLOGIC0:OFF_RANK2_CLK_ENABLE ~ILOGIC1:IFF_DELAY_ENABLE IODELAY1:DRP06[4] -
7 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TFF_SRVAL IODELAY1:MODE[2] IODELAY1:DELAYCHAIN_OSC IODELAY1:IDELAY_VALUE_N[4] - OLOGIC0:TFF_RANK2_CLK_ENABLE IODELAY1:CAL_DELAY_MAX[7] -
6 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TFF_INIT ~ILOGIC1:I_DELAY_ENABLE IODELAY1:ENABLE.CIN[1] IODELAY1:ODELAY_VALUE_N[4] - OLOGIC0:TFF_RANK1_CLK_ENABLE IODELAY1:CAL_DELAY_MAX[6] -
5 - - - - - - - - - - - - - - - - - - - - - - ~OLOGIC0:TFF_SR_SYNC ILOGIC1:TSBYPASS_MUX[0] IODELAY1:ENABLE.CIN[0] IODELAY1:IDELAY_VALUE_N[5] - OLOGIC0:TFF_CE_OR_DDR IODELAY1:CAL_DELAY_MAX[5] -
4 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TFF_REV_ENABLE IODELAY1:ENABLE.ODATAIN IOICLK1:MUX.OCE[2] IODELAY1:ODELAY_VALUE_N[5] - OLOGIC0:TFF_CE_ENABLE IODELAY1:CAL_DELAY_MAX[4] -
3 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TFF_SR_ENABLE IOICLK1:MUX.ICE[2] IOICLK1:MUX.OCE[0] IODELAY1:IDELAY_VALUE_N[6] - OLOGIC0:TRAIN_PATTERN[3] IODELAY1:CAL_DELAY_MAX[3] IODELAY0:MUX.IOCLK[0]
2 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TFF_LATCH IOICLK1:MUX.ICE[0] IOICLK1:MUX.OCE[1] IODELAY1:ODELAY_VALUE_N[6] - OLOGIC0:MUX.T[0] IODELAY1:CAL_DELAY_MAX[2] -
1 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.SR[0] IOICLK1:MUX.ICE[1] - IODELAY1:IDELAY_VALUE_N[7] - OLOGIC0:TFF_RANK1_BYPASS IODELAY1:CAL_DELAY_MAX[1] IODELAY1:MUX.IOCLK[0]
0 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.REV[0] - - IODELAY1:ODELAY_VALUE_N[7] IODELAY1:TEST_PCOUNTER OLOGIC0:OUTPUT_MODE[0] IODELAY1:CAL_DELAY_MAX[0] -
ILOGIC0:BITSLIP_ENABLE 0.29.22
ILOGIC0:CASCADE_ENABLE 0.22.34
ILOGIC0:DDR 0.22.40
ILOGIC0:ENABLE 0.29.32
ILOGIC0:ENABLE.IOCE 0.29.26
ILOGIC0:IFF_INIT 0.22.38
ILOGIC0:IFF_LATCH 0.22.33
ILOGIC0:IFF_REV_USED 0.22.35
ILOGIC0:IFF_SRVAL 0.22.37
ILOGIC0:IFF_SR_USED 0.22.39
ILOGIC0:ROW1_CLK_ENABLE 0.22.45
ILOGIC0:ROW2_CLK_ENABLE 0.22.44
ILOGIC0:ROW3_CLK_ENABLE 0.22.46
ILOGIC0:ROW4_CLK_ENABLE 0.22.47
ILOGIC1:BITSLIP_ENABLE 0.29.17
ILOGIC1:CASCADE_ENABLE 0.29.16
ILOGIC1:DDR 0.22.60
ILOGIC1:ENABLE 0.29.35
ILOGIC1:ENABLE.IOCE 0.29.24
ILOGIC1:IFF_INIT 0.22.41
ILOGIC1:IFF_LATCH 0.22.63
ILOGIC1:IFF_REV_USED 0.22.59
ILOGIC1:IFF_SRVAL 0.22.55
ILOGIC1:IFF_SR_USED 0.22.42
ILOGIC1:ROW1_CLK_ENABLE 0.22.50
ILOGIC1:ROW2_CLK_ENABLE 0.22.51
ILOGIC1:ROW3_CLK_ENABLE 0.22.49
ILOGIC1:ROW4_CLK_ENABLE 0.22.48
IODELAY0:DELAYCHAIN_OSC 0.24.56
IODELAY0:DIFF_PHASE_DETECTOR 0.26.55
IODELAY0:ENABLE.ODATAIN 0.23.59
IODELAY0:IDELAY_FIXED 0.22.52
IODELAY0:IDELAY_FROM_HALF_MAX 0.28.44
IODELAY0:LUMPED_DELAY 0.28.52
IODELAY0:LUMPED_DELAY_SELECT 0.28.54
IODELAY0:PLUS1 0.28.45
IODELAY0:TEST_GLITCH_FILTER 0.23.45
IODELAY0:TEST_NCOUNTER 0.26.51
IODELAY0:TEST_PCOUNTER 0.26.49
IODELAY1:DELAYCHAIN_OSC 0.24.7
IODELAY1:DIFF_PHASE_DETECTOR 0.26.20
IODELAY1:ENABLE.ODATAIN 0.23.4
IODELAY1:IDELAY_FIXED 0.22.16
IODELAY1:IDELAY_FROM_HALF_MAX 0.28.19
IODELAY1:LUMPED_DELAY 0.28.11
IODELAY1:LUMPED_DELAY_SELECT 0.28.9
IODELAY1:TEST_GLITCH_FILTER 0.23.18
IODELAY1:TEST_NCOUNTER 0.26.12
IODELAY1:TEST_PCOUNTER 0.26.0
IODELAY_COMMON:DIFF_PHASE_DETECTOR 0.27.63
IODELAY_COMMON:DRP_ENABLE 0.26.28
IODELAY_COMMON:DRP_FROM_MCB 0.26.46
IOI:MEM_PLL_DIV_EN 0.26.57
IOICLK0:INV.CLK0 0.23.38
IOICLK0:INV.CLK1 0.24.38
IOICLK0:INV.CLK2 0.23.39
IOICLK1:INV.CLK0 0.23.25
IOICLK1:INV.CLK1 0.24.25
IOICLK1:INV.CLK2 0.23.24
OLOGIC0:CASCADE_ENABLE 0.29.46
OLOGIC0:DDR_OPPOSITE_EDGE 0.27.14
OLOGIC0:ENABLE 0.29.28
OLOGIC0:ENABLE.IOCE 0.29.27
OLOGIC0:MISR_ENABLE_CLK 0.29.13
OLOGIC0:MISR_ENABLE_DATA 0.29.12
OLOGIC0:MISR_RESET 0.29.10
OLOGIC0:OFF_CE_ENABLE 0.27.11
OLOGIC0:OFF_CE_OR_DDR 0.27.10
OLOGIC0:OFF_INIT 0.22.9
OLOGIC0:OFF_LATCH 0.22.13
OLOGIC0:OFF_RANK1_BYPASS 0.27.15
OLOGIC0:OFF_RANK1_CLK_ENABLE 0.27.9
OLOGIC0:OFF_RANK2_CLK_ENABLE 0.27.8
OLOGIC0:OFF_REV_ENABLE 0.22.11
OLOGIC0:OFF_SRVAL 0.22.8
OLOGIC0:OFF_SR_ENABLE 0.22.12
OLOGIC0:TFF_CE_ENABLE 0.27.4
OLOGIC0:TFF_CE_OR_DDR 0.27.5
OLOGIC0:TFF_INIT 0.22.6
OLOGIC0:TFF_LATCH 0.22.2
OLOGIC0:TFF_RANK1_BYPASS 0.27.1
OLOGIC0:TFF_RANK1_CLK_ENABLE 0.27.6
OLOGIC0:TFF_RANK2_CLK_ENABLE 0.27.7
OLOGIC0:TFF_REV_ENABLE 0.22.4
OLOGIC0:TFF_SRVAL 0.22.7
OLOGIC0:TFF_SR_ENABLE 0.22.3
OLOGIC1:CASCADE_ENABLE 0.22.30
OLOGIC1:DDR_OPPOSITE_EDGE 0.27.29
OLOGIC1:ENABLE 0.29.31
OLOGIC1:ENABLE.IOCE 0.29.25
OLOGIC1:MISR_ENABLE_CLK 0.29.14
OLOGIC1:MISR_ENABLE_DATA 0.29.15
OLOGIC1:MISR_RESET 0.29.11
OLOGIC1:OFF_CE_ENABLE 0.27.27
OLOGIC1:OFF_CE_OR_DDR 0.27.26
OLOGIC1:OFF_INIT 0.22.25
OLOGIC1:OFF_LATCH 0.22.29
OLOGIC1:OFF_RANK1_BYPASS 0.27.34
OLOGIC1:OFF_RANK1_CLK_ENABLE 0.27.25
OLOGIC1:OFF_RANK2_CLK_ENABLE 0.27.24
OLOGIC1:OFF_REV_ENABLE 0.22.27
OLOGIC1:OFF_SRVAL 0.22.24
OLOGIC1:OFF_SR_ENABLE 0.22.28
OLOGIC1:TFF_CE_ENABLE 0.27.20
OLOGIC1:TFF_CE_OR_DDR 0.27.21
OLOGIC1:TFF_INIT 0.22.22
OLOGIC1:TFF_LATCH 0.22.18
OLOGIC1:TFF_RANK1_BYPASS 0.27.19
OLOGIC1:TFF_RANK1_CLK_ENABLE 0.27.22
OLOGIC1:TFF_RANK2_CLK_ENABLE 0.27.23
OLOGIC1:TFF_REV_ENABLE 0.22.20
OLOGIC1:TFF_SRVAL 0.22.23
OLOGIC1:TFF_SR_ENABLE 0.22.19
non-inverted [0]
ILOGIC0:DATA_WIDTH_RELOAD 0.27.39 0.27.38
4 0 0
3 0 1
2 1 0
1 1 1
ILOGIC0:DATA_WIDTH_START 0.29.23 0.29.21
2 0 0
3 0 1
4 1 0
ILOGIC0:IFF_CE_ENABLE 0.22.31
ILOGIC0:IFF_DELAY_ENABLE 0.28.55
ILOGIC0:IFF_SR_SYNC 0.22.32
ILOGIC0:I_DELAY_ENABLE 0.23.57
ILOGIC1:IFF_CE_ENABLE 0.22.57
ILOGIC1:IFF_DELAY_ENABLE 0.28.8
ILOGIC1:IFF_SR_SYNC 0.22.62
ILOGIC1:I_DELAY_ENABLE 0.23.6
OLOGIC0:OFF_SR_SYNC 0.22.10
OLOGIC0:TFF_SR_SYNC 0.22.5
OLOGIC1:OFF_SR_SYNC 0.22.26
OLOGIC1:TFF_SR_SYNC 0.22.21
inverted ~[0]
ILOGIC0:MUX.CLK 0.29.41 0.29.40
ILOGIC1:MUX.CLK 0.29.43 0.29.42
NONE 0 0
ICLK0 0 1
ICLK1 1 0
ILOGIC0:MUX.D 0.24.43 0.24.42
IOB_I 0 0
OTHER_IOB_I 1 1
ILOGIC0:MUX.Q1 0.27.46 0.27.47
ILOGIC0:MUX.Q2 0.27.45 0.27.44
ILOGIC0:MUX.Q3 0.27.42 0.27.43
ILOGIC0:MUX.Q4 0.27.41 0.27.40
ILOGIC1:MUX.Q1 0.27.49 0.27.48
ILOGIC1:MUX.Q2 0.27.50 0.27.51
ILOGIC1:MUX.Q3 0.27.53 0.27.52
ILOGIC1:MUX.Q4 0.27.54 0.27.55
SHIFT_REGISTER 0 0
NETWORKING 0 1
NETWORKING_PIPELINED 1 0
RETIMED 1 1
ILOGIC0:MUX.SR 0.22.36
ILOGIC1:MUX.SR 0.22.58
OLOGIC_SR 0
INT 1
ILOGIC0:TSBYPASS_MUX 0.23.58
ILOGIC1:TSBYPASS_MUX 0.23.5
GND 0
T 1
ILOGIC1:DATA_WIDTH_RELOAD 0.27.37 0.27.36 0.27.18
8 0 0 0
7 0 0 1
6 0 1 0
5 0 1 1
4 1 0 0
3 1 0 1
2 1 1 0
1 1 1 1
ILOGIC1:DATA_WIDTH_START 0.29.18 0.29.19 0.29.20
2 0 0 0
3 0 0 1
4 0 1 0
5 0 1 1
6 1 0 0
7 1 0 1
8 1 1 0
IODELAY0:CAL_DELAY_MAX 0.28.56 0.28.57 0.28.58 0.28.59 0.28.60 0.28.61 0.28.62 0.28.63
IODELAY0:DRP06 0.28.43 0.28.41 0.28.49 0.28.55 0.28.53 0.28.50 0.28.47 0.28.45
IODELAY0:DRP07 0.28.42 0.28.40 0.28.48 0.28.54 0.28.52 0.28.51 0.28.46 0.28.44
IODELAY0:IDELAY_VALUE_N 0.25.62 0.25.60 0.25.58 0.25.56 0.25.55 0.25.53 0.25.51 0.25.49
IODELAY0:IDELAY_VALUE_P 0.25.33 0.25.35 0.25.37 0.25.39 0.25.40 0.25.42 0.25.44 0.25.46
IODELAY0:ODELAY_VALUE_N 0.25.63 0.25.61 0.25.59 0.25.57 0.25.54 0.25.52 0.25.50 0.25.48
IODELAY0:ODELAY_VALUE_P 0.25.32 0.25.34 0.25.36 0.25.38 0.25.41 0.25.43 0.25.45 0.25.47
IODELAY1:CAL_DELAY_MAX 0.28.7 0.28.6 0.28.5 0.28.4 0.28.3 0.28.2 0.28.1 0.28.0
IODELAY1:DRP06 0.28.20 0.28.22 0.28.14 0.28.8 0.28.10 0.28.13 0.28.16 0.28.18
IODELAY1:DRP07 0.28.21 0.28.23 0.28.15 0.28.9 0.28.11 0.28.12 0.28.17 0.28.19
IODELAY1:IDELAY_VALUE_N 0.25.1 0.25.3 0.25.5 0.25.7 0.25.8 0.25.10 0.25.12 0.25.14
IODELAY1:IDELAY_VALUE_P 0.25.30 0.25.28 0.25.26 0.25.24 0.25.23 0.25.21 0.25.19 0.25.17
IODELAY1:ODELAY_VALUE_N 0.25.0 0.25.2 0.25.4 0.25.6 0.25.9 0.25.11 0.25.13 0.25.15
IODELAY1:ODELAY_VALUE_P 0.25.31 0.25.29 0.25.27 0.25.25 0.25.22 0.25.20 0.25.18 0.25.16
non-inverted [7] [6] [5] [4] [3] [2] [1] [0]
IODELAY0:COUNTER_WRAPAROUND 0.28.46
IODELAY1:COUNTER_WRAPAROUND 0.28.17
WRAPAROUND 0
STAY_AT_LIMIT 1
IODELAY0:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB 0.26.54 0.26.44
IODELAY1:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB 0.26.19 0.26.9
IODELAY1:EVENT_SEL 0.28.16 0.28.18
IODELAY_COMMON:ENFFSCAN_DRP 0.29.9 0.26.43
IOICLK0:DDR_ENABLE 0.23.41 0.23.40
IOICLK1:DDR_ENABLE 0.23.23 0.23.22
non-inverted [1] [0]
IODELAY0:DELAY_SRC 0.28.53 0.28.50
IODELAY1:DELAY_SRC 0.28.10 0.28.13
IO 0 0
ODATAIN 0 1
IDATAIN 1 1
IODELAY0:DRP_ADDR 0.28.32 0.28.36 0.28.37 0.28.38 0.28.39
IODELAY1:DRP_ADDR 0.28.31 0.28.27 0.28.26 0.28.25 0.28.24
non-inverted [4] [3] [2] [1] [0]
IODELAY0:ENABLE.CIN 0.24.58 0.24.57 0.24.41
IODELAY1:ENABLE.CIN 0.24.22 0.24.6 0.24.5
non-inverted [2] [1] [0]
IODELAY0:IDELAY_MODE 0.24.54 0.24.44
IODELAY1:IDELAY_MODE 0.24.19 0.24.9
NORMAL 0 0
PCI 1 1
IODELAY0:IODELAY_CHANGE 0.28.51
IODELAY1:IODELAY_CHANGE 0.28.12
CHANGE_ON_CLOCK 0
CHANGE_ON_DATA 1
IODELAY0:MODE 0.24.55 0.23.56 0.23.44 0.23.42
IODELAY1:MODE 0.24.8 0.23.7 0.23.21 0.23.19
IODRP2 0 0 0 0
IODELAY2 0 0 1 1
IODRP2_MCB 1 1 0 0
IODELAY0:MUX.IOCLK 0.29.3
IODELAY1:MUX.IOCLK 0.29.1
ILOGIC_CLK 0
OLOGIC_CLK 1
IODELAY_COMMON:MCB_ADDRESS 0.26.47 0.26.39 0.26.26 0.26.24
OLOGIC0:TRAIN_PATTERN 0.27.3 0.27.13 0.27.17 0.27.16
OLOGIC1:TRAIN_PATTERN 0.27.30 0.27.31 0.27.32 0.27.33
non-inverted [3] [2] [1] [0]
IOI:MEM_PLL_POL_SEL 0.26.56
INVERTED 0
NOTINVERTED 1
IOICLK0:DDR_ALIGNMENT 0.23.54 0.23.55
IOICLK1:DDR_ALIGNMENT 0.23.9 0.23.8
NONE 0 0
CLK0 0 1
CLK1 1 0
IOICLK0:MUX.CE0 0.23.53 0.23.52 0.23.50
IOICLK1:MUX.CE0 0.23.10 0.23.11 0.23.13
NONE 0 0 0
IOCE0 0 0 1
IOCE2 0 1 0
PLLCE0 1 0 0
IOICLK0:MUX.CE1 0.24.53 0.24.52 0.24.51
IOICLK1:MUX.CE1 0.24.10 0.24.11 0.24.12
NONE 0 0 0
IOCE1 0 0 1
IOCE3 0 1 0
PLLCE1 1 0 0
IOICLK0:MUX.CLK0 0.23.37 0.23.35 0.23.36 0.23.32 0.23.33
IOICLK1:MUX.CLK0 0.23.26 0.23.28 0.23.27 0.23.31 0.23.30
NONE 0 0 0 0 0
IOCLK0 0 0 0 0 1
IOCLK2 0 0 0 1 0
PLLCLK0 0 0 1 0 0
CKINT0 0 1 0 0 0
CKINT1 1 0 0 0 0
IOICLK0:MUX.CLK1 0.24.35 0.24.37 0.24.36 0.24.32 0.24.33
IOICLK1:MUX.CLK1 0.24.28 0.24.26 0.24.27 0.24.31 0.24.30
NONE 0 0 0 0 0
IOCLK1 0 0 0 0 1
IOCLK3 0 0 0 1 0
PLLCLK1 0 0 1 0 0
CKINT0 0 1 0 0 0
CKINT1 1 0 0 0 0
IOICLK0:MUX.CLK2 0.24.40 0.24.39
IOICLK1:MUX.CLK2 0.24.23 0.24.24
NONE 0 0
PLLCLK0 0 1
PLLCLK1 1 0
IOICLK0:MUX.ICE 0.23.60 0.23.62 0.23.61
IOICLK0:MUX.OCE 0.24.59 0.24.61 0.24.60
IOICLK1:MUX.ICE 0.23.3 0.23.1 0.23.2
IOICLK1:MUX.OCE 0.24.4 0.24.2 0.24.3
NONE 0 0 0
CE0 0 0 1
CE1 0 1 0
DDR 1 0 0
IOICLK0:MUX.ICLK 0.23.48 0.23.49 0.24.46 0.24.47
IOICLK0:MUX.OCLK 0.24.49 0.24.50 0.24.45 0.24.48
IOICLK1:MUX.ICLK 0.23.15 0.23.14 0.24.17 0.24.16
IOICLK1:MUX.OCLK 0.24.14 0.24.13 0.24.18 0.24.15
NONE 0 0 0 0
CLK0 0 0 0 1
CLK1 0 0 1 0
CLK2 0 1 0 0
DDR 1 0 0 0
OLOGIC0:MUX.CLK 0.29.37 0.29.36
OLOGIC1:MUX.CLK 0.29.39 0.29.38
NONE 0 0
OCLK0 0 1
OCLK1 1 0
OLOGIC0:MUX.D 0.27.12
OLOGIC0:MUX.T 0.27.2
OLOGIC1:MUX.D 0.27.35
OLOGIC1:MUX.T 0.27.28
INT 0
MCB 1
OLOGIC0:MUX.OCE 0.28.43
OLOGIC1:MUX.OCE 0.28.20
INT 0
PCI_CE 1
OLOGIC0:MUX.REV 0.22.0
OLOGIC0:MUX.SR 0.22.1
OLOGIC1:MUX.REV 0.22.14
OLOGIC1:MUX.SR 0.22.15
GND 0
INT 1
OLOGIC0:MUX.TRAIN 0.29.47 0.29.45
OLOGIC1:MUX.TRAIN 0.29.48 0.29.44
GND 0 0
INT 0 1
MCB 1 0
OLOGIC0:OMUX 0.28.49
OLOGIC1:OMUX 0.28.14
OUTFF 0
D1 1
OLOGIC0:OUTPUT_MODE 0.27.0
SINGLE_ENDED 0
DIFFERENTIAL 1
OLOGIC0:TMUX 0.28.41
OLOGIC1:TMUX 0.28.22
TFF 0
T1 1

Bitstream — IOI.BT

spartan6 IOI.BT bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
63 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IFF_LATCH - IODELAY0:ODELAY_VALUE_N[7] - - IODELAY_COMMON:DIFF_PHASE_DETECTOR IODELAY0:CAL_DELAY_MAX[0] -
62 - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF_SR_SYNC - IODELAY0:IDELAY_VALUE_N[7] - - - IODELAY0:CAL_DELAY_MAX[1] IOICLK0:MUX.ICE[1]
61 - - - - - - - - - - - - - - - - - - - - - - - IOICLK0:MUX.OCE[1] IODELAY0:ODELAY_VALUE_N[6] - - - IODELAY0:CAL_DELAY_MAX[2] IOICLK0:MUX.ICE[0]
60 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DDR IOICLK0:MUX.OCE[0] IODELAY0:IDELAY_VALUE_N[6] - - - IODELAY0:CAL_DELAY_MAX[3] IOICLK0:MUX.ICE[2]
59 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IFF_REV_USED IOICLK0:MUX.OCE[2] IODELAY0:ODELAY_VALUE_N[5] - - - IODELAY0:CAL_DELAY_MAX[4] IODELAY0:ENABLE.ODATAIN
58 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:MUX.SR[0] IODELAY0:ENABLE.CIN[2] IODELAY0:IDELAY_VALUE_N[5] - - - IODELAY0:CAL_DELAY_MAX[5] ILOGIC0:TSBYPASS_MUX[0]
57 - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF_CE_ENABLE IODELAY0:ENABLE.CIN[1] IODELAY0:ODELAY_VALUE_N[4] IOI:MEM_PLL_POL_SEL[0] - - IODELAY0:CAL_DELAY_MAX[6] ~ILOGIC0:I_DELAY_ENABLE
56 - - - - - - - - - - - - - - - - - - - - - - - IODELAY0:DELAYCHAIN_OSC IODELAY0:IDELAY_VALUE_N[4] IOI:MEM_PLL_DIV_EN - - IODELAY0:CAL_DELAY_MAX[7] IODELAY0:MODE[3]
55 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IFF_SRVAL IODELAY0:MODE[2] IODELAY0:IDELAY_VALUE_N[3] IODELAY0:DIFF_PHASE_DETECTOR - ILOGIC1:MUX.Q4[0] ~ILOGIC0:IFF_DELAY_ENABLE IODELAY0:DRP06[4] IOICLK0:DDR_ALIGNMENT[0]
54 - - - - - - - - - - - - - - - - - - - - - - - IODELAY0:IDELAY_MODE[1] IODELAY0:ODELAY_VALUE_N[3] IODELAY0:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB[1] - ILOGIC1:MUX.Q4[1] IODELAY0:DRP07[4] IODELAY0:LUMPED_DELAY_SELECT IOICLK0:DDR_ALIGNMENT[1]
53 - - - - - - - - - - - - - - - - - - - - - - - IOICLK0:MUX.CE1[2] IODELAY0:IDELAY_VALUE_N[2] - - ILOGIC1:MUX.Q3[1] IODELAY0:DELAY_SRC[1] IODELAY0:DRP06[3] IOICLK0:MUX.CE0[2]
52 - - - - - - - - - - - - - - - - - - - - - - IODELAY0:IDELAY_FIXED IOICLK0:MUX.CE1[1] IODELAY0:ODELAY_VALUE_N[2] - - ILOGIC1:MUX.Q3[0] IODELAY0:DRP07[3] IODELAY0:LUMPED_DELAY IOICLK0:MUX.CE0[1]
51 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:ROW2_CLK_ENABLE IOICLK0:MUX.CE1[0] IODELAY0:IDELAY_VALUE_N[1] IODELAY0:TEST_NCOUNTER - ILOGIC1:MUX.Q2[0] IODELAY0:DRP07[2] IODELAY0:IODELAY_CHANGE[0] -
50 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:ROW1_CLK_ENABLE IOICLK0:MUX.OCLK[2] IODELAY0:ODELAY_VALUE_N[1] - - ILOGIC1:MUX.Q2[1] IODELAY0:DELAY_SRC[0] IODELAY0:DRP06[2] IOICLK0:MUX.CE0[0]
49 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:ROW3_CLK_ENABLE IOICLK0:MUX.OCLK[3] IODELAY0:IDELAY_VALUE_N[0] IODELAY0:TEST_PCOUNTER - ILOGIC1:MUX.Q1[1] IODELAY0:DRP06[5] OLOGIC0:OMUX[0] IOICLK0:MUX.ICLK[2]
48 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:ROW4_CLK_ENABLE IOICLK0:MUX.OCLK[0] IODELAY0:ODELAY_VALUE_N[0] - OLOGIC1:MUX.TRAIN[1] ILOGIC1:MUX.Q1[0] IODELAY0:DRP07[5] IOICLK0:MUX.ICLK[3]
47 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:ROW4_CLK_ENABLE IOICLK0:MUX.ICLK[0] IODELAY0:ODELAY_VALUE_P[0] IODELAY_COMMON:MCB_ADDRESS[3] OLOGIC0:MUX.TRAIN[1] ILOGIC0:MUX.Q1[0] IODELAY0:DRP06[1] -
46 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:ROW3_CLK_ENABLE IOICLK0:MUX.ICLK[1] IODELAY0:IDELAY_VALUE_P[0] IODELAY_COMMON:DRP_FROM_MCB OLOGIC0:CASCADE_ENABLE ILOGIC0:MUX.Q1[1] IODELAY0:COUNTER_WRAPAROUND[0] IODELAY0:DRP07[1] -
45 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:ROW1_CLK_ENABLE IOICLK0:MUX.OCLK[1] IODELAY0:ODELAY_VALUE_P[1] - OLOGIC0:MUX.TRAIN[0] ILOGIC0:MUX.Q2[1] IODELAY0:DRP06[0] IODELAY0:PLUS1 IODELAY0:TEST_GLITCH_FILTER
44 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:ROW2_CLK_ENABLE IODELAY0:IDELAY_MODE[0] IODELAY0:IDELAY_VALUE_P[1] IODELAY0:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB[0] OLOGIC1:MUX.TRAIN[0] ILOGIC0:MUX.Q2[0] IODELAY0:DRP07[0] IODELAY0:IDELAY_FROM_HALF_MAX IODELAY0:MODE[1]
43 - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.D[1] IODELAY0:ODELAY_VALUE_P[2] IODELAY_COMMON:ENFFSCAN_DRP[0] ILOGIC1:MUX.CLK[1] ILOGIC0:MUX.Q3[0] IODELAY0:DRP06[7] OLOGIC0:MUX.OCE[0] -
42 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IFF_SR_USED ILOGIC0:MUX.D[0] IODELAY0:IDELAY_VALUE_P[2] - ILOGIC1:MUX.CLK[0] ILOGIC0:MUX.Q3[1] IODELAY0:DRP07[7] IODELAY0:MODE[0]
41 - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IFF_INIT IODELAY0:ENABLE.CIN[0] IODELAY0:ODELAY_VALUE_P[3] - ILOGIC0:MUX.CLK[1] ILOGIC0:MUX.Q4[1] IODELAY0:DRP06[6] OLOGIC0:TMUX[0] IOICLK0:DDR_ENABLE[1]
40 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DDR IOICLK0:MUX.CLK2[1] IODELAY0:IDELAY_VALUE_P[3] - ILOGIC0:MUX.CLK[0] ILOGIC0:MUX.Q4[0] IODELAY0:DRP07[6] IOICLK0:DDR_ENABLE[0]
39 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_SR_USED IOICLK0:MUX.CLK2[0] IODELAY0:IDELAY_VALUE_P[4] IODELAY_COMMON:MCB_ADDRESS[2] OLOGIC1:MUX.CLK[1] ILOGIC0:DATA_WIDTH_RELOAD[1] IODELAY0:DRP_ADDR[0] IOICLK0:INV.CLK2
38 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_INIT IOICLK0:INV.CLK1 IODELAY0:ODELAY_VALUE_P[4] - OLOGIC1:MUX.CLK[0] ILOGIC0:DATA_WIDTH_RELOAD[0] IODELAY0:DRP_ADDR[1] IOICLK0:INV.CLK0
37 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_SRVAL IOICLK0:MUX.CLK1[3] IODELAY0:IDELAY_VALUE_P[5] - OLOGIC0:MUX.CLK[1] ILOGIC1:DATA_WIDTH_RELOAD[2] IODELAY0:DRP_ADDR[2] IOICLK0:MUX.CLK0[4]
36 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:MUX.SR[0] IOICLK0:MUX.CLK1[2] IODELAY0:ODELAY_VALUE_P[5] - OLOGIC0:MUX.CLK[0] ILOGIC1:DATA_WIDTH_RELOAD[1] IODELAY0:DRP_ADDR[3] IOICLK0:MUX.CLK0[2]
35 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_REV_USED IOICLK0:MUX.CLK1[4] IODELAY0:IDELAY_VALUE_P[6] - ILOGIC1:ENABLE OLOGIC1:MUX.D[0] - IOICLK0:MUX.CLK0[3]
34 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:CASCADE_ENABLE - IODELAY0:ODELAY_VALUE_P[6] - - OLOGIC1:OFF_RANK1_BYPASS - -
33 - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_LATCH IOICLK0:MUX.CLK1[0] IODELAY0:IDELAY_VALUE_P[7] - - OLOGIC1:TRAIN_PATTERN[0] - IOICLK0:MUX.CLK0[0]
32 - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF_SR_SYNC IOICLK0:MUX.CLK1[1] IODELAY0:ODELAY_VALUE_P[7] - ILOGIC0:ENABLE OLOGIC1:TRAIN_PATTERN[1] IODELAY0:DRP_ADDR[4] IOICLK0:MUX.CLK0[1]
31 - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF_CE_ENABLE IOICLK1:MUX.CLK1[1] IODELAY1:ODELAY_VALUE_P[7] - OLOGIC1:ENABLE OLOGIC1:TRAIN_PATTERN[2] IODELAY1:DRP_ADDR[4] IOICLK1:MUX.CLK0[1]
30 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:CASCADE_ENABLE IOICLK1:MUX.CLK1[0] IODELAY1:IDELAY_VALUE_P[7] - - OLOGIC1:TRAIN_PATTERN[3] - IOICLK1:MUX.CLK0[0]
29 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:OFF_LATCH - IODELAY1:ODELAY_VALUE_P[6] - - OLOGIC1:DDR_OPPOSITE_EDGE - -
28 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:OFF_SR_ENABLE IOICLK1:MUX.CLK1[4] IODELAY1:IDELAY_VALUE_P[6] IODELAY_COMMON:DRP_ENABLE OLOGIC0:ENABLE OLOGIC1:MUX.T[0] - IOICLK1:MUX.CLK0[3]
27 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:OFF_REV_ENABLE IOICLK1:MUX.CLK1[2] IODELAY1:ODELAY_VALUE_P[5] - OLOGIC0:ENABLE.IOCE OLOGIC1:OFF_CE_ENABLE IODELAY1:DRP_ADDR[3] IOICLK1:MUX.CLK0[2]
26 - - - - - - - - - - - - - - - - - - - - - - ~OLOGIC1:OFF_SR_SYNC IOICLK1:MUX.CLK1[3] IODELAY1:IDELAY_VALUE_P[5] IODELAY_COMMON:MCB_ADDRESS[1] ILOGIC0:ENABLE.IOCE OLOGIC1:OFF_CE_OR_DDR IODELAY1:DRP_ADDR[2] IOICLK1:MUX.CLK0[4]
25 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:OFF_INIT IOICLK1:INV.CLK1 IODELAY1:ODELAY_VALUE_P[4] - OLOGIC1:ENABLE.IOCE OLOGIC1:OFF_RANK1_CLK_ENABLE IODELAY1:DRP_ADDR[1] IOICLK1:INV.CLK0
24 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:OFF_SRVAL IOICLK1:MUX.CLK2[0] IODELAY1:IDELAY_VALUE_P[4] IODELAY_COMMON:MCB_ADDRESS[0] ILOGIC1:ENABLE.IOCE OLOGIC1:OFF_RANK2_CLK_ENABLE IODELAY1:DRP_ADDR[0] IOICLK1:INV.CLK2
23 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:TFF_SRVAL IOICLK1:MUX.CLK2[1] IODELAY1:IDELAY_VALUE_P[3] - ILOGIC0:DATA_WIDTH_START[1] OLOGIC1:TFF_RANK2_CLK_ENABLE IODELAY1:DRP07[6] IOICLK1:DDR_ENABLE[1]
22 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:TFF_INIT IODELAY1:ENABLE.CIN[2] IODELAY1:ODELAY_VALUE_P[3] - ILOGIC0:BITSLIP_ENABLE OLOGIC1:TFF_RANK1_CLK_ENABLE IODELAY1:DRP06[6] OLOGIC1:TMUX[0] IOICLK1:DDR_ENABLE[0]
21 - - - - - - - - - - - - - - - - - - - - - - ~OLOGIC1:TFF_SR_SYNC - IODELAY1:IDELAY_VALUE_P[2] - ILOGIC0:DATA_WIDTH_START[0] OLOGIC1:TFF_CE_OR_DDR IODELAY1:DRP07[7] IODELAY1:MODE[1]
20 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:TFF_REV_ENABLE - IODELAY1:ODELAY_VALUE_P[2] IODELAY1:DIFF_PHASE_DETECTOR ILOGIC1:DATA_WIDTH_START[0] OLOGIC1:TFF_CE_ENABLE IODELAY1:DRP06[7] OLOGIC1:MUX.OCE[0] -
19 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:TFF_SR_ENABLE IODELAY1:IDELAY_MODE[1] IODELAY1:IDELAY_VALUE_P[1] IODELAY1:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB[1] ILOGIC1:DATA_WIDTH_START[1] OLOGIC1:TFF_RANK1_BYPASS IODELAY1:DRP07[0] IODELAY1:IDELAY_FROM_HALF_MAX IODELAY1:MODE[0]
18 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:TFF_LATCH IOICLK1:MUX.OCLK[1] IODELAY1:ODELAY_VALUE_P[1] - ILOGIC1:DATA_WIDTH_START[2] ILOGIC1:DATA_WIDTH_RELOAD[0] IODELAY1:DRP06[0] IODELAY1:EVENT_SEL[0] IODELAY1:TEST_GLITCH_FILTER
17 - - - - - - - - - - - - - - - - - - - - - - - IOICLK1:MUX.ICLK[1] IODELAY1:IDELAY_VALUE_P[0] - ILOGIC1:BITSLIP_ENABLE OLOGIC0:TRAIN_PATTERN[1] IODELAY1:COUNTER_WRAPAROUND[0] IODELAY1:DRP07[1] -
16 - - - - - - - - - - - - - - - - - - - - - - IODELAY1:IDELAY_FIXED IOICLK1:MUX.ICLK[0] IODELAY1:ODELAY_VALUE_P[0] - ILOGIC1:CASCADE_ENABLE OLOGIC0:TRAIN_PATTERN[0] IODELAY1:DRP06[1] IODELAY1:EVENT_SEL[1] -
15 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.SR[0] IOICLK1:MUX.OCLK[0] IODELAY1:ODELAY_VALUE_N[0] - OLOGIC1:MISR_ENABLE_DATA OLOGIC0:OFF_RANK1_BYPASS IODELAY1:DRP07[5] IOICLK1:MUX.ICLK[3]
14 - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MUX.REV[0] IOICLK1:MUX.OCLK[3] IODELAY1:IDELAY_VALUE_N[0] - OLOGIC1:MISR_ENABLE_CLK OLOGIC0:DDR_OPPOSITE_EDGE IODELAY1:DRP06[5] OLOGIC1:OMUX[0] IOICLK1:MUX.ICLK[2]
13 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:OFF_LATCH IOICLK1:MUX.OCLK[2] IODELAY1:ODELAY_VALUE_N[1] - OLOGIC0:MISR_ENABLE_CLK OLOGIC0:TRAIN_PATTERN[2] IODELAY1:DELAY_SRC[0] IODELAY1:DRP06[2] IOICLK1:MUX.CE0[0]
12 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:OFF_SR_ENABLE IOICLK1:MUX.CE1[0] IODELAY1:IDELAY_VALUE_N[1] IODELAY1:TEST_NCOUNTER OLOGIC0:MISR_ENABLE_DATA OLOGIC0:MUX.D[0] IODELAY1:DRP07[2] IODELAY1:IODELAY_CHANGE[0] -
11 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:OFF_REV_ENABLE IOICLK1:MUX.CE1[1] IODELAY1:ODELAY_VALUE_N[2] - OLOGIC1:MISR_RESET OLOGIC0:OFF_CE_ENABLE IODELAY1:DRP07[3] IODELAY1:LUMPED_DELAY IOICLK1:MUX.CE0[1]
10 - - - - - - - - - - - - - - - - - - - - - - ~OLOGIC0:OFF_SR_SYNC IOICLK1:MUX.CE1[2] IODELAY1:IDELAY_VALUE_N[2] - OLOGIC0:MISR_RESET OLOGIC0:OFF_CE_OR_DDR IODELAY1:DELAY_SRC[1] IODELAY1:DRP06[3] IOICLK1:MUX.CE0[2]
9 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:OFF_INIT IODELAY1:IDELAY_MODE[0] IODELAY1:ODELAY_VALUE_N[3] IODELAY1:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB[0] IODELAY_COMMON:ENFFSCAN_DRP[1] OLOGIC0:OFF_RANK1_CLK_ENABLE IODELAY1:DRP07[4] IODELAY1:LUMPED_DELAY_SELECT IOICLK1:DDR_ALIGNMENT[1]
8 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:OFF_SRVAL IODELAY1:MODE[2] IODELAY1:IDELAY_VALUE_N[3] - - OLOGIC0:OFF_RANK2_CLK_ENABLE ~ILOGIC1:IFF_DELAY_ENABLE IODELAY1:DRP06[4] IOICLK1:DDR_ALIGNMENT[0]
7 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TFF_SRVAL IODELAY1:DELAYCHAIN_OSC IODELAY1:IDELAY_VALUE_N[4] - - OLOGIC0:TFF_RANK2_CLK_ENABLE IODELAY1:CAL_DELAY_MAX[7] IODELAY1:MODE[3]
6 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TFF_INIT IODELAY1:ENABLE.CIN[1] IODELAY1:ODELAY_VALUE_N[4] - - OLOGIC0:TFF_RANK1_CLK_ENABLE IODELAY1:CAL_DELAY_MAX[6] ~ILOGIC1:I_DELAY_ENABLE
5 - - - - - - - - - - - - - - - - - - - - - - ~OLOGIC0:TFF_SR_SYNC IODELAY1:ENABLE.CIN[0] IODELAY1:IDELAY_VALUE_N[5] - - OLOGIC0:TFF_CE_OR_DDR IODELAY1:CAL_DELAY_MAX[5] ILOGIC1:TSBYPASS_MUX[0]
4 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TFF_REV_ENABLE IOICLK1:MUX.OCE[2] IODELAY1:ODELAY_VALUE_N[5] - - OLOGIC0:TFF_CE_ENABLE IODELAY1:CAL_DELAY_MAX[4] IODELAY1:ENABLE.ODATAIN
3 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TFF_SR_ENABLE IOICLK1:MUX.OCE[0] IODELAY1:IDELAY_VALUE_N[6] - IODELAY0:MUX.IOCLK[0] OLOGIC0:TRAIN_PATTERN[3] IODELAY1:CAL_DELAY_MAX[3] IOICLK1:MUX.ICE[2]
2 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:TFF_LATCH IOICLK1:MUX.OCE[1] IODELAY1:ODELAY_VALUE_N[6] - - OLOGIC0:MUX.T[0] IODELAY1:CAL_DELAY_MAX[2] IOICLK1:MUX.ICE[0]
1 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.SR[0] - IODELAY1:IDELAY_VALUE_N[7] - IODELAY1:MUX.IOCLK[0] OLOGIC0:TFF_RANK1_BYPASS IODELAY1:CAL_DELAY_MAX[1] IOICLK1:MUX.ICE[1]
0 - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MUX.REV[0] - IODELAY1:ODELAY_VALUE_N[7] IODELAY1:TEST_PCOUNTER - OLOGIC0:OUTPUT_MODE[0] IODELAY1:CAL_DELAY_MAX[0] -
ILOGIC0:BITSLIP_ENABLE 0.26.22
ILOGIC0:CASCADE_ENABLE 0.22.34
ILOGIC0:DDR 0.22.40
ILOGIC0:ENABLE 0.26.32
ILOGIC0:ENABLE.IOCE 0.26.26
ILOGIC0:IFF_INIT 0.22.38
ILOGIC0:IFF_LATCH 0.22.33
ILOGIC0:IFF_REV_USED 0.22.35
ILOGIC0:IFF_SRVAL 0.22.37
ILOGIC0:IFF_SR_USED 0.22.39
ILOGIC0:ROW1_CLK_ENABLE 0.22.45
ILOGIC0:ROW2_CLK_ENABLE 0.22.44
ILOGIC0:ROW3_CLK_ENABLE 0.22.46
ILOGIC0:ROW4_CLK_ENABLE 0.22.47
ILOGIC1:BITSLIP_ENABLE 0.26.17
ILOGIC1:CASCADE_ENABLE 0.26.16
ILOGIC1:DDR 0.22.60
ILOGIC1:ENABLE 0.26.35
ILOGIC1:ENABLE.IOCE 0.26.24
ILOGIC1:IFF_INIT 0.22.41
ILOGIC1:IFF_LATCH 0.22.63
ILOGIC1:IFF_REV_USED 0.22.59
ILOGIC1:IFF_SRVAL 0.22.55
ILOGIC1:IFF_SR_USED 0.22.42
ILOGIC1:ROW1_CLK_ENABLE 0.22.50
ILOGIC1:ROW2_CLK_ENABLE 0.22.51
ILOGIC1:ROW3_CLK_ENABLE 0.22.49
ILOGIC1:ROW4_CLK_ENABLE 0.22.48
IODELAY0:DELAYCHAIN_OSC 0.23.56
IODELAY0:DIFF_PHASE_DETECTOR 0.25.55
IODELAY0:ENABLE.ODATAIN 0.29.59
IODELAY0:IDELAY_FIXED 0.22.52
IODELAY0:IDELAY_FROM_HALF_MAX 0.28.44
IODELAY0:LUMPED_DELAY 0.28.52
IODELAY0:LUMPED_DELAY_SELECT 0.28.54
IODELAY0:PLUS1 0.28.45
IODELAY0:TEST_GLITCH_FILTER 0.29.45
IODELAY0:TEST_NCOUNTER 0.25.51
IODELAY0:TEST_PCOUNTER 0.25.49
IODELAY1:DELAYCHAIN_OSC 0.23.7
IODELAY1:DIFF_PHASE_DETECTOR 0.25.20
IODELAY1:ENABLE.ODATAIN 0.29.4
IODELAY1:IDELAY_FIXED 0.22.16
IODELAY1:IDELAY_FROM_HALF_MAX 0.28.19
IODELAY1:LUMPED_DELAY 0.28.11
IODELAY1:LUMPED_DELAY_SELECT 0.28.9
IODELAY1:TEST_GLITCH_FILTER 0.29.18
IODELAY1:TEST_NCOUNTER 0.25.12
IODELAY1:TEST_PCOUNTER 0.25.0
IODELAY_COMMON:DIFF_PHASE_DETECTOR 0.27.63
IODELAY_COMMON:DRP_ENABLE 0.25.28
IODELAY_COMMON:DRP_FROM_MCB 0.25.46
IOI:MEM_PLL_DIV_EN 0.25.56
IOICLK0:INV.CLK0 0.29.38
IOICLK0:INV.CLK1 0.23.38
IOICLK0:INV.CLK2 0.29.39
IOICLK1:INV.CLK0 0.29.25
IOICLK1:INV.CLK1 0.23.25
IOICLK1:INV.CLK2 0.29.24
OLOGIC0:CASCADE_ENABLE 0.26.46
OLOGIC0:DDR_OPPOSITE_EDGE 0.27.14
OLOGIC0:ENABLE 0.26.28
OLOGIC0:ENABLE.IOCE 0.26.27
OLOGIC0:MISR_ENABLE_CLK 0.26.13
OLOGIC0:MISR_ENABLE_DATA 0.26.12
OLOGIC0:MISR_RESET 0.26.10
OLOGIC0:OFF_CE_ENABLE 0.27.11
OLOGIC0:OFF_CE_OR_DDR 0.27.10
OLOGIC0:OFF_INIT 0.22.9
OLOGIC0:OFF_LATCH 0.22.13
OLOGIC0:OFF_RANK1_BYPASS 0.27.15
OLOGIC0:OFF_RANK1_CLK_ENABLE 0.27.9
OLOGIC0:OFF_RANK2_CLK_ENABLE 0.27.8
OLOGIC0:OFF_REV_ENABLE 0.22.11
OLOGIC0:OFF_SRVAL 0.22.8
OLOGIC0:OFF_SR_ENABLE 0.22.12
OLOGIC0:TFF_CE_ENABLE 0.27.4
OLOGIC0:TFF_CE_OR_DDR 0.27.5
OLOGIC0:TFF_INIT 0.22.6
OLOGIC0:TFF_LATCH 0.22.2
OLOGIC0:TFF_RANK1_BYPASS 0.27.1
OLOGIC0:TFF_RANK1_CLK_ENABLE 0.27.6
OLOGIC0:TFF_RANK2_CLK_ENABLE 0.27.7
OLOGIC0:TFF_REV_ENABLE 0.22.4
OLOGIC0:TFF_SRVAL 0.22.7
OLOGIC0:TFF_SR_ENABLE 0.22.3
OLOGIC1:CASCADE_ENABLE 0.22.30
OLOGIC1:DDR_OPPOSITE_EDGE 0.27.29
OLOGIC1:ENABLE 0.26.31
OLOGIC1:ENABLE.IOCE 0.26.25
OLOGIC1:MISR_ENABLE_CLK 0.26.14
OLOGIC1:MISR_ENABLE_DATA 0.26.15
OLOGIC1:MISR_RESET 0.26.11
OLOGIC1:OFF_CE_ENABLE 0.27.27
OLOGIC1:OFF_CE_OR_DDR 0.27.26
OLOGIC1:OFF_INIT 0.22.25
OLOGIC1:OFF_LATCH 0.22.29
OLOGIC1:OFF_RANK1_BYPASS 0.27.34
OLOGIC1:OFF_RANK1_CLK_ENABLE 0.27.25
OLOGIC1:OFF_RANK2_CLK_ENABLE 0.27.24
OLOGIC1:OFF_REV_ENABLE 0.22.27
OLOGIC1:OFF_SRVAL 0.22.24
OLOGIC1:OFF_SR_ENABLE 0.22.28
OLOGIC1:TFF_CE_ENABLE 0.27.20
OLOGIC1:TFF_CE_OR_DDR 0.27.21
OLOGIC1:TFF_INIT 0.22.22
OLOGIC1:TFF_LATCH 0.22.18
OLOGIC1:TFF_RANK1_BYPASS 0.27.19
OLOGIC1:TFF_RANK1_CLK_ENABLE 0.27.22
OLOGIC1:TFF_RANK2_CLK_ENABLE 0.27.23
OLOGIC1:TFF_REV_ENABLE 0.22.20
OLOGIC1:TFF_SRVAL 0.22.23
OLOGIC1:TFF_SR_ENABLE 0.22.19
non-inverted [0]
ILOGIC0:DATA_WIDTH_RELOAD 0.27.39 0.27.38
4 0 0
3 0 1
2 1 0
1 1 1
ILOGIC0:DATA_WIDTH_START 0.26.23 0.26.21
2 0 0
3 0 1
4 1 0
ILOGIC0:IFF_CE_ENABLE 0.22.31
ILOGIC0:IFF_DELAY_ENABLE 0.28.55
ILOGIC0:IFF_SR_SYNC 0.22.32
ILOGIC0:I_DELAY_ENABLE 0.29.57
ILOGIC1:IFF_CE_ENABLE 0.22.57
ILOGIC1:IFF_DELAY_ENABLE 0.28.8
ILOGIC1:IFF_SR_SYNC 0.22.62
ILOGIC1:I_DELAY_ENABLE 0.29.6
OLOGIC0:OFF_SR_SYNC 0.22.10
OLOGIC0:TFF_SR_SYNC 0.22.5
OLOGIC1:OFF_SR_SYNC 0.22.26
OLOGIC1:TFF_SR_SYNC 0.22.21
inverted ~[0]
ILOGIC0:MUX.CLK 0.26.41 0.26.40
ILOGIC1:MUX.CLK 0.26.43 0.26.42
NONE 0 0
ICLK0 0 1
ICLK1 1 0
ILOGIC0:MUX.D 0.23.43 0.23.42
IOB_I 0 0
OTHER_IOB_I 1 1
ILOGIC0:MUX.Q1 0.27.46 0.27.47
ILOGIC0:MUX.Q2 0.27.45 0.27.44
ILOGIC0:MUX.Q3 0.27.42 0.27.43
ILOGIC0:MUX.Q4 0.27.41 0.27.40
ILOGIC1:MUX.Q1 0.27.49 0.27.48
ILOGIC1:MUX.Q2 0.27.50 0.27.51
ILOGIC1:MUX.Q3 0.27.53 0.27.52
ILOGIC1:MUX.Q4 0.27.54 0.27.55
SHIFT_REGISTER 0 0
NETWORKING 0 1
NETWORKING_PIPELINED 1 0
RETIMED 1 1
ILOGIC0:MUX.SR 0.22.36
ILOGIC1:MUX.SR 0.22.58
OLOGIC_SR 0
INT 1
ILOGIC0:TSBYPASS_MUX 0.29.58
ILOGIC1:TSBYPASS_MUX 0.29.5
GND 0
T 1
ILOGIC1:DATA_WIDTH_RELOAD 0.27.37 0.27.36 0.27.18
8 0 0 0
7 0 0 1
6 0 1 0
5 0 1 1
4 1 0 0
3 1 0 1
2 1 1 0
1 1 1 1
ILOGIC1:DATA_WIDTH_START 0.26.18 0.26.19 0.26.20
2 0 0 0
3 0 0 1
4 0 1 0
5 0 1 1
6 1 0 0
7 1 0 1
8 1 1 0
IODELAY0:CAL_DELAY_MAX 0.28.56 0.28.57 0.28.58 0.28.59 0.28.60 0.28.61 0.28.62 0.28.63
IODELAY0:DRP06 0.28.43 0.28.41 0.28.49 0.28.55 0.28.53 0.28.50 0.28.47 0.28.45
IODELAY0:DRP07 0.28.42 0.28.40 0.28.48 0.28.54 0.28.52 0.28.51 0.28.46 0.28.44
IODELAY0:IDELAY_VALUE_N 0.24.62 0.24.60 0.24.58 0.24.56 0.24.55 0.24.53 0.24.51 0.24.49
IODELAY0:IDELAY_VALUE_P 0.24.33 0.24.35 0.24.37 0.24.39 0.24.40 0.24.42 0.24.44 0.24.46
IODELAY0:ODELAY_VALUE_N 0.24.63 0.24.61 0.24.59 0.24.57 0.24.54 0.24.52 0.24.50 0.24.48
IODELAY0:ODELAY_VALUE_P 0.24.32 0.24.34 0.24.36 0.24.38 0.24.41 0.24.43 0.24.45 0.24.47
IODELAY1:CAL_DELAY_MAX 0.28.7 0.28.6 0.28.5 0.28.4 0.28.3 0.28.2 0.28.1 0.28.0
IODELAY1:DRP06 0.28.20 0.28.22 0.28.14 0.28.8 0.28.10 0.28.13 0.28.16 0.28.18
IODELAY1:DRP07 0.28.21 0.28.23 0.28.15 0.28.9 0.28.11 0.28.12 0.28.17 0.28.19
IODELAY1:IDELAY_VALUE_N 0.24.1 0.24.3 0.24.5 0.24.7 0.24.8 0.24.10 0.24.12 0.24.14
IODELAY1:IDELAY_VALUE_P 0.24.30 0.24.28 0.24.26 0.24.24 0.24.23 0.24.21 0.24.19 0.24.17
IODELAY1:ODELAY_VALUE_N 0.24.0 0.24.2 0.24.4 0.24.6 0.24.9 0.24.11 0.24.13 0.24.15
IODELAY1:ODELAY_VALUE_P 0.24.31 0.24.29 0.24.27 0.24.25 0.24.22 0.24.20 0.24.18 0.24.16
non-inverted [7] [6] [5] [4] [3] [2] [1] [0]
IODELAY0:COUNTER_WRAPAROUND 0.28.46
IODELAY1:COUNTER_WRAPAROUND 0.28.17
WRAPAROUND 0
STAY_AT_LIMIT 1
IODELAY0:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB 0.25.54 0.25.44
IODELAY1:DELAYCHAIN_OSC_OR_ODATAIN_LP_OR_IDRP2_MCB 0.25.19 0.25.9
IODELAY1:EVENT_SEL 0.28.16 0.28.18
IODELAY_COMMON:ENFFSCAN_DRP 0.26.9 0.25.43
IOICLK0:DDR_ENABLE 0.29.41 0.29.40
IOICLK1:DDR_ENABLE 0.29.23 0.29.22
non-inverted [1] [0]
IODELAY0:DELAY_SRC 0.28.53 0.28.50
IODELAY1:DELAY_SRC 0.28.10 0.28.13
IO 0 0
ODATAIN 0 1
IDATAIN 1 1
IODELAY0:DRP_ADDR 0.28.32 0.28.36 0.28.37 0.28.38 0.28.39
IODELAY1:DRP_ADDR 0.28.31 0.28.27 0.28.26 0.28.25 0.28.24
non-inverted [4] [3] [2] [1] [0]
IODELAY0:ENABLE.CIN 0.23.58 0.23.57 0.23.41
IODELAY1:ENABLE.CIN 0.23.22 0.23.6 0.23.5
non-inverted [2] [1] [0]
IODELAY0:IDELAY_MODE 0.23.54 0.23.44
IODELAY1:IDELAY_MODE 0.23.19 0.23.9
NORMAL 0 0
PCI 1 1
IODELAY0:IODELAY_CHANGE 0.28.51
IODELAY1:IODELAY_CHANGE 0.28.12
CHANGE_ON_CLOCK 0
CHANGE_ON_DATA 1
IODELAY0:MODE 0.29.56 0.23.55 0.29.44 0.29.42
IODELAY1:MODE 0.29.7 0.23.8 0.29.21 0.29.19
IODRP2 0 0 0 0
IODELAY2 0 0 1 1
IODRP2_MCB 1 1 0 0
IODELAY0:MUX.IOCLK 0.26.3
IODELAY1:MUX.IOCLK 0.26.1
ILOGIC_CLK 0
OLOGIC_CLK 1
IODELAY_COMMON:MCB_ADDRESS 0.25.47 0.25.39 0.25.26 0.25.24
OLOGIC0:TRAIN_PATTERN 0.27.3 0.27.13 0.27.17 0.27.16
OLOGIC1:TRAIN_PATTERN 0.27.30 0.27.31 0.27.32 0.27.33
non-inverted [3] [2] [1] [0]
IOI:MEM_PLL_POL_SEL 0.25.57
INVERTED 0
NOTINVERTED 1
IOICLK0:DDR_ALIGNMENT 0.29.54 0.29.55
IOICLK1:DDR_ALIGNMENT 0.29.9 0.29.8
NONE 0 0
CLK0 0 1
CLK1 1 0
IOICLK0:MUX.CE0 0.29.53 0.29.52 0.29.50
IOICLK1:MUX.CE0 0.29.10 0.29.11 0.29.13
NONE 0 0 0
IOCE0 0 0 1
IOCE2 0 1 0
PLLCE0 1 0 0
IOICLK0:MUX.CE1 0.23.53 0.23.52 0.23.51
IOICLK1:MUX.CE1 0.23.10 0.23.11 0.23.12
NONE 0 0 0
IOCE1 0 0 1
IOCE3 0 1 0
PLLCE1 1 0 0
IOICLK0:MUX.CLK0 0.29.37 0.29.35 0.29.36 0.29.32 0.29.33
IOICLK1:MUX.CLK0 0.29.26 0.29.28 0.29.27 0.29.31 0.29.30
NONE 0 0 0 0 0
IOCLK0 0 0 0 0 1
IOCLK2 0 0 0 1 0
PLLCLK0 0 0 1 0 0
CKINT0 0 1 0 0 0
CKINT1 1 0 0 0 0
IOICLK0:MUX.CLK1 0.23.35 0.23.37 0.23.36 0.23.32 0.23.33
IOICLK1:MUX.CLK1 0.23.28 0.23.26 0.23.27 0.23.31 0.23.30
NONE 0 0 0 0 0
IOCLK1 0 0 0 0 1
IOCLK3 0 0 0 1 0
PLLCLK1 0 0 1 0 0
CKINT0 0 1 0 0 0
CKINT1 1 0 0 0 0
IOICLK0:MUX.CLK2 0.23.40 0.23.39
IOICLK1:MUX.CLK2 0.23.23 0.23.24
NONE 0 0
PLLCLK0 0 1
PLLCLK1 1 0
IOICLK0:MUX.ICE 0.29.60 0.29.62 0.29.61
IOICLK0:MUX.OCE 0.23.59 0.23.61 0.23.60
IOICLK1:MUX.ICE 0.29.3 0.29.1 0.29.2
IOICLK1:MUX.OCE 0.23.4 0.23.2 0.23.3
NONE 0 0 0
CE0 0 0 1
CE1 0 1 0
DDR 1 0 0
IOICLK0:MUX.ICLK 0.29.48 0.29.49 0.23.46 0.23.47
IOICLK0:MUX.OCLK 0.23.49 0.23.50 0.23.45 0.23.48
IOICLK1:MUX.ICLK 0.29.15 0.29.14 0.23.17 0.23.16
IOICLK1:MUX.OCLK 0.23.14 0.23.13 0.23.18 0.23.15
NONE 0 0 0 0
CLK0 0 0 0 1
CLK1 0 0 1 0
CLK2 0 1 0 0
DDR 1 0 0 0
OLOGIC0:MUX.CLK 0.26.37 0.26.36
OLOGIC1:MUX.CLK 0.26.39 0.26.38
NONE 0 0
OCLK0 0 1
OCLK1 1 0
OLOGIC0:MUX.D 0.27.12
OLOGIC0:MUX.T 0.27.2
OLOGIC1:MUX.D 0.27.35
OLOGIC1:MUX.T 0.27.28
INT 0
MCB 1
OLOGIC0:MUX.OCE 0.28.43
OLOGIC1:MUX.OCE 0.28.20
INT 0
PCI_CE 1
OLOGIC0:MUX.REV 0.22.0
OLOGIC0:MUX.SR 0.22.1
OLOGIC1:MUX.REV 0.22.14
OLOGIC1:MUX.SR 0.22.15
GND 0
INT 1
OLOGIC0:MUX.TRAIN 0.26.47 0.26.45
OLOGIC1:MUX.TRAIN 0.26.48 0.26.44
GND 0 0
INT 0 1
MCB 1 0
OLOGIC0:OMUX 0.28.49
OLOGIC1:OMUX 0.28.14
OUTFF 0
D1 1
OLOGIC0:OUTPUT_MODE 0.27.0
SINGLE_ENDED 0
DIFFERENTIAL 1
OLOGIC0:TMUX 0.28.41
OLOGIC1:TMUX 0.28.22
TFF 0
T1 1

Bitstream — IOB

spartan6 IOB bittile 0
BitFrame
0
127 IOB1:OUTPUT_ENABLE
126 -
125 IOB1:INV.I
124 IOB1:PCI_INPUT
123 IOB1:VREF_HV
122 IOB1:IBUF_MODE[2]
121 IOB1:IBUF_MODE[1]
120 IOB1:IBUF_MODE[0]
119 IOB1:SUSPEND[4]
118 IOB1:SUSPEND[3]
117 IOB1:SUSPEND[2]
116 IOB1:SUSPEND[1]
115 IOB1:SUSPEND[0]
114 IOB1:PULLTYPE[2]
113 IOB1:PULLTYPE[1]
112 IOB1:PULLTYPE[0]
111 IOB1:PCI_CLAMP
110 IOB1:OUTPUT_LOW_VOLTAGE
109 IOB1:PRE_EMPHASIS
108 -
107 IOB1:DIFF_MODE[1]
106 IOB1:DIFF_MODE[0]
105 IOB1:LVDS_GROUP
104 IOB1:DIFF_OUTPUT_ENABLE
103 IOB1:NSLEW[3]
102 ~IOB1:NSLEW[2]
101 IOB1:NSLEW[1]
100 IOB1:NSLEW[0]
99 IOB1:PSLEW[3]
98 ~IOB1:PSLEW[2]
97 IOB1:PSLEW[1]
96 IOB1:PSLEW[0]
95 -
94 IOB1:NTERM[6]
93 IOB1:NTERM[5]
92 IOB1:NTERM[4]
91 IOB1:NTERM[3]
90 IOB1:NTERM[2]
89 IOB1:NTERM[1]
88 IOB1:NTERM[0]
87 -
86 IOB1:NDRIVE[6]
85 ~IOB1:NDRIVE[5]
84 IOB1:NDRIVE[4]
83 IOB1:NDRIVE[3]
82 ~IOB1:NDRIVE[2]
81 IOB1:NDRIVE[1]
80 IOB1:NDRIVE[0]
79 IOB1:TML
78 -
77 IOB1:PTERM[5]
76 IOB1:PTERM[4]
75 IOB1:PTERM[3]
74 IOB1:PTERM[2]
73 IOB1:PTERM[1]
72 IOB1:PTERM[0]
71 -
70 -
69 IOB1:PDRIVE[5]
68 IOB1:PDRIVE[4]
67 ~IOB1:PDRIVE[3]
66 IOB1:PDRIVE[2]
65 ~IOB1:PDRIVE[1]
64 ~IOB1:PDRIVE[0]
63 IOB0:OUTPUT_ENABLE
62 IOB0:VREF
61 IOB0:INV.I
60 IOB0:PCI_INPUT
59 IOB0:VREF_HV
58 IOB0:IBUF_MODE[2]
57 IOB0:IBUF_MODE[1]
56 IOB0:IBUF_MODE[0]
55 IOB0:SUSPEND[4]
54 IOB0:SUSPEND[3]
53 IOB0:SUSPEND[2]
52 IOB0:SUSPEND[1]
51 IOB0:SUSPEND[0]
50 IOB0:PULLTYPE[2]
49 IOB0:PULLTYPE[1]
48 IOB0:PULLTYPE[0]
47 IOB0:PCI_CLAMP
46 IOB0:OUTPUT_LOW_VOLTAGE
45 IOB0:PRE_EMPHASIS
44 -
43 -
42 -
41 -
40 IOB0:DIFF_TERM
39 IOB0:NSLEW[3]
38 ~IOB0:NSLEW[2]
37 IOB0:NSLEW[1]
36 IOB0:NSLEW[0]
35 IOB0:PSLEW[3]
34 ~IOB0:PSLEW[2]
33 IOB0:PSLEW[1]
32 IOB0:PSLEW[0]
31 -
30 IOB0:NTERM[6]
29 IOB0:NTERM[5]
28 IOB0:NTERM[4]
27 IOB0:NTERM[3]
26 IOB0:NTERM[2]
25 IOB0:NTERM[1]
24 IOB0:NTERM[0]
23 -
22 IOB0:NDRIVE[6]
21 ~IOB0:NDRIVE[5]
20 IOB0:NDRIVE[4]
19 IOB0:NDRIVE[3]
18 ~IOB0:NDRIVE[2]
17 IOB0:NDRIVE[1]
16 IOB0:NDRIVE[0]
15 IOB0:TML
14 -
13 IOB0:PTERM[5]
12 IOB0:PTERM[4]
11 IOB0:PTERM[3]
10 IOB0:PTERM[2]
9 IOB0:PTERM[1]
8 IOB0:PTERM[0]
7 -
6 -
5 IOB0:PDRIVE[5]
4 IOB0:PDRIVE[4]
3 ~IOB0:PDRIVE[3]
2 IOB0:PDRIVE[2]
1 ~IOB0:PDRIVE[1]
0 ~IOB0:PDRIVE[0]
IOB0:DIFF_TERM 0.0.40
IOB0:INV.I 0.0.61
IOB0:OUTPUT_ENABLE 0.0.63
IOB0:OUTPUT_LOW_VOLTAGE 0.0.46
IOB0:PCI_CLAMP 0.0.47
IOB0:PCI_INPUT 0.0.60
IOB0:PRE_EMPHASIS 0.0.45
IOB0:TML 0.0.15
IOB0:VREF 0.0.62
IOB0:VREF_HV 0.0.59
IOB1:DIFF_OUTPUT_ENABLE 0.0.104
IOB1:INV.I 0.0.125
IOB1:LVDS_GROUP 0.0.105
IOB1:OUTPUT_ENABLE 0.0.127
IOB1:OUTPUT_LOW_VOLTAGE 0.0.110
IOB1:PCI_CLAMP 0.0.111
IOB1:PCI_INPUT 0.0.124
IOB1:PRE_EMPHASIS 0.0.109
IOB1:TML 0.0.79
IOB1:VREF_HV 0.0.123
non-inverted [0]
IOB0:IBUF_MODE 0.0.58 0.0.57 0.0.56
IOB1:IBUF_MODE 0.0.122 0.0.121 0.0.120
NONE 0 0 0
BYPASS_T 0 0 1
BYPASS_O 0 1 0
CMOS_VCCINT 0 1 1
CMOS_VCCO 1 0 0
VREF 1 0 1
DIFF 1 1 0
CMOS_VCCAUX 1 1 1
IOB0:NDRIVE 0.0.22 0.0.21 0.0.20 0.0.19 0.0.18 0.0.17 0.0.16
IOB1:NDRIVE 0.0.86 0.0.85 0.0.84 0.0.83 0.0.82 0.0.81 0.0.80
mixed inversion [6] ~[5] [4] [3] ~[2] [1] [0]
IOB0:NSLEW 0.0.39 0.0.38 0.0.37 0.0.36
IOB0:PSLEW 0.0.35 0.0.34 0.0.33 0.0.32
IOB1:NSLEW 0.0.103 0.0.102 0.0.101 0.0.100
IOB1:PSLEW 0.0.99 0.0.98 0.0.97 0.0.96
mixed inversion [3] ~[2] [1] [0]
IOB0:NTERM 0.0.30 0.0.29 0.0.28 0.0.27 0.0.26 0.0.25 0.0.24
IOB1:NTERM 0.0.94 0.0.93 0.0.92 0.0.91 0.0.90 0.0.89 0.0.88
non-inverted [6] [5] [4] [3] [2] [1] [0]
IOB0:PDRIVE 0.0.5 0.0.4 0.0.3 0.0.2 0.0.1 0.0.0
IOB1:PDRIVE 0.0.69 0.0.68 0.0.67 0.0.66 0.0.65 0.0.64
mixed inversion [5] [4] ~[3] [2] ~[1] ~[0]
IOB0:PTERM 0.0.13 0.0.12 0.0.11 0.0.10 0.0.9 0.0.8
IOB1:PTERM 0.0.77 0.0.76 0.0.75 0.0.74 0.0.73 0.0.72
non-inverted [5] [4] [3] [2] [1] [0]
IOB0:PULLTYPE 0.0.50 0.0.49 0.0.48
IOB1:PULLTYPE 0.0.114 0.0.113 0.0.112
PULLDOWN 0 0 0
NONE 0 0 1
PULLUP 0 1 1
KEEPER 1 0 1
IOB0:SUSPEND 0.0.55 0.0.54 0.0.53 0.0.52 0.0.51
IOB1:SUSPEND 0.0.119 0.0.118 0.0.117 0.0.116 0.0.115
3STATE 0 0 0 0 0
DRIVE_LAST_VALUE 0 0 0 0 1
3STATE_PULLDOWN 0 0 0 1 0
3STATE_PULLUP 0 0 1 0 0
3STATE_KEEPER 0 1 0 0 0
3STATE_OCT_ON 1 0 0 0 0
IOB1:DIFF_MODE 0.0.107 0.0.106
NONE 0 0
LVDS 0 1
TMDS 1 0

Tables

Name IOSTD:PDRIVE IOSTD:NDRIVE
[5] [4] [3] [2] [1] [0] [6] [5] [4] [3] [2] [1] [0]
BLVDS_25.2.5 0 1 1 1 1 1 1 1 1 1 1 1 1
BLVDS_25.3.3 0 1 1 1 1 1 1 1 1 1 1 1 1
DIFF_MOBILE_DDR.2.5 0 0 1 0 0 0 0 0 1 0 0 0 1
DIFF_MOBILE_DDR.3.3 0 0 1 0 0 0 0 0 0 1 1 0 1
DISPLAY_PORT.2.5 0 0 1 0 0 0 0 1 1 1 0 0 0
DISPLAY_PORT.3.3 0 0 1 0 0 0 0 0 1 1 1 0 0
HSTL_I.2.5 0 1 0 1 1 0 0 1 0 0 1 0 0
HSTL_I.3.3 0 1 0 1 1 0 0 0 1 1 1 0 0
HSTL_II.2.5 1 0 1 0 1 1 1 0 0 0 1 1 1
HSTL_II.3.3 1 0 1 0 1 1 0 1 1 1 0 0 0
HSTL_III.2.5 0 1 0 1 1 0 1 1 0 1 0 1 0
HSTL_III.3.3 0 1 0 1 1 0 1 0 1 0 0 1 1
HSTL_III_18.2.5 0 1 0 1 1 0 1 1 1 1 1 1 1
HSTL_III_18.3.3 0 1 0 1 1 0 1 1 0 1 0 0 0
HSTL_II_18.2.5 1 0 1 1 0 0 1 1 0 0 0 1 0
HSTL_II_18.3.3 1 0 1 1 0 0 1 0 0 1 1 0 0
HSTL_I_18.2.5 0 1 0 1 1 0 0 1 1 0 0 0 1
HSTL_I_18.3.3 0 1 0 1 1 0 0 1 0 0 1 1 0
I2C.2.5 0 0 0 0 0 0 0 0 1 0 0 0 0
I2C.3.3 0 0 0 0 0 0 0 0 0 1 0 0 0
LVCMOS12.12.2.5 1 1 0 1 0 0 0 1 1 0 1 0 1
LVCMOS12.12.3.3 1 1 0 1 0 0 0 1 0 1 0 1 0
LVCMOS12.2.2.5 0 0 1 0 0 1 0 0 0 1 0 0 1
LVCMOS12.2.3.3 0 0 1 0 0 1 0 0 0 0 1 1 1
LVCMOS12.4.2.5 0 1 0 0 1 0 0 0 1 0 0 1 0
LVCMOS12.4.3.3 0 1 0 0 1 0 0 0 0 1 1 1 0
LVCMOS12.6.2.5 0 1 1 0 1 0 0 0 1 1 0 1 1
LVCMOS12.6.3.3 0 1 1 0 1 0 0 0 1 0 1 0 1
LVCMOS12.8.2.5 1 0 0 0 1 1 0 1 0 0 1 0 0
LVCMOS12.8.3.3 1 0 0 0 1 1 0 0 1 1 1 0 0
LVCMOS12_JEDEC.12.2.5 1 1 0 1 0 0 0 1 1 0 1 0 1
LVCMOS12_JEDEC.12.3.3 1 1 0 1 0 0 0 1 0 1 0 1 0
LVCMOS12_JEDEC.2.2.5 0 0 1 0 0 1 0 0 0 1 0 0 1
LVCMOS12_JEDEC.2.3.3 0 0 1 0 0 1 0 0 0 0 1 1 1
LVCMOS12_JEDEC.4.2.5 0 1 0 0 1 0 0 0 1 0 0 1 0
LVCMOS12_JEDEC.4.3.3 0 1 0 0 1 0 0 0 0 1 1 1 0
LVCMOS12_JEDEC.6.2.5 0 1 1 0 1 0 0 0 1 1 0 1 1
LVCMOS12_JEDEC.6.3.3 0 1 1 0 1 0 0 0 1 0 1 0 1
LVCMOS12_JEDEC.8.2.5 1 0 0 0 1 1 0 1 0 0 1 0 0
LVCMOS12_JEDEC.8.3.3 1 0 0 0 1 1 0 0 1 1 1 0 0
LVCMOS15.12.2.5 1 0 0 1 0 0 0 1 1 1 1 0 0
LVCMOS15.12.3.3 1 0 0 1 0 0 0 1 0 1 1 1 1
LVCMOS15.16.2.5 1 0 1 1 1 1 1 0 0 1 1 1 1
LVCMOS15.16.3.3 1 0 1 1 1 1 0 1 1 1 1 1 1
LVCMOS15.2.2.5 0 0 0 1 1 0 0 0 0 1 0 1 0
LVCMOS15.2.3.3 0 0 0 1 1 0 0 0 0 1 0 0 0
LVCMOS15.4.2.5 0 0 1 1 0 0 0 0 1 0 1 0 0
LVCMOS15.4.3.3 0 0 1 1 0 0 0 0 1 0 0 0 0
LVCMOS15.6.2.5 0 1 0 0 1 0 0 0 1 1 1 1 0
LVCMOS15.6.3.3 0 1 0 0 1 0 0 0 1 1 0 0 0
LVCMOS15.8.2.5 0 1 1 0 0 0 0 1 0 1 0 0 0
LVCMOS15.8.3.3 0 1 1 0 0 0 0 1 0 0 0 0 0
LVCMOS15_JEDEC.12.2.5 1 0 0 1 0 0 0 1 1 1 1 0 0
LVCMOS15_JEDEC.12.3.3 1 0 0 1 0 0 0 1 0 1 1 1 1
LVCMOS15_JEDEC.16.2.5 1 0 1 1 1 1 1 0 0 1 1 1 1
LVCMOS15_JEDEC.16.3.3 1 0 1 1 1 1 0 1 1 1 1 1 1
LVCMOS15_JEDEC.2.2.5 0 0 0 1 1 0 0 0 0 1 0 1 0
LVCMOS15_JEDEC.2.3.3 0 0 0 1 1 0 0 0 0 1 0 0 0
LVCMOS15_JEDEC.4.2.5 0 0 1 1 0 0 0 0 1 0 1 0 0
LVCMOS15_JEDEC.4.3.3 0 0 1 1 0 0 0 0 1 0 0 0 0
LVCMOS15_JEDEC.6.2.5 0 1 0 0 1 0 0 0 1 1 1 1 0
LVCMOS15_JEDEC.6.3.3 0 1 0 0 1 0 0 0 1 1 0 0 0
LVCMOS15_JEDEC.8.2.5 0 1 1 0 0 0 0 1 0 1 0 0 0
LVCMOS15_JEDEC.8.3.3 0 1 1 0 0 0 0 1 0 0 0 0 0
LVCMOS18.12.2.5 0 1 0 1 1 1 0 1 1 0 0 0 1
LVCMOS18.12.3.3 0 1 0 1 1 1 0 1 0 0 1 1 0
LVCMOS18.16.2.5 0 1 1 1 1 1 1 0 0 0 0 0 1
LVCMOS18.16.3.3 0 1 1 1 1 1 0 1 1 0 0 1 0
LVCMOS18.2.2.5 0 0 0 1 0 0 0 0 0 1 0 0 1
LVCMOS18.2.3.3 0 0 0 1 0 0 0 0 0 0 1 1 1
LVCMOS18.24.2.5 1 0 1 1 1 0 1 1 0 0 0 0 1
LVCMOS18.24.3.3 1 0 1 1 1 0 1 0 0 1 0 1 1
LVCMOS18.4.2.5 0 0 1 0 0 0 0 0 1 0 0 0 1
LVCMOS18.4.3.3 0 0 1 0 0 0 0 0 0 1 1 0 1
LVCMOS18.6.2.5 0 0 1 1 0 0 0 0 1 1 0 0 1
LVCMOS18.6.3.3 0 0 1 1 0 0 0 0 1 0 0 1 1
LVCMOS18.8.2.5 0 1 0 0 0 0 0 1 0 0 0 0 1
LVCMOS18.8.3.3 0 1 0 0 0 0 0 0 1 1 0 0 1
LVCMOS18_JEDEC.12.2.5 0 1 0 1 1 1 0 1 1 0 0 0 1
LVCMOS18_JEDEC.12.3.3 0 1 0 1 1 1 0 1 0 0 1 1 0
LVCMOS18_JEDEC.16.2.5 0 1 1 1 1 1 1 0 0 0 0 0 1
LVCMOS18_JEDEC.16.3.3 0 1 1 1 1 1 0 1 1 0 0 1 0
LVCMOS18_JEDEC.2.2.5 0 0 0 1 0 0 0 0 0 1 0 0 1
LVCMOS18_JEDEC.2.3.3 0 0 0 1 0 0 0 0 0 0 1 1 1
LVCMOS18_JEDEC.24.2.5 1 0 1 1 1 0 1 1 0 0 0 0 1
LVCMOS18_JEDEC.24.3.3 1 0 1 1 1 0 1 0 0 1 0 1 1
LVCMOS18_JEDEC.4.2.5 0 0 1 0 0 0 0 0 1 0 0 0 1
LVCMOS18_JEDEC.4.3.3 0 0 1 0 0 0 0 0 0 1 1 0 1
LVCMOS18_JEDEC.6.2.5 0 0 1 1 0 0 0 0 1 1 0 0 1
LVCMOS18_JEDEC.6.3.3 0 0 1 1 0 0 0 0 1 0 0 1 1
LVCMOS18_JEDEC.8.2.5 0 1 0 0 0 0 0 1 0 0 0 0 1
LVCMOS18_JEDEC.8.3.3 0 1 0 0 0 0 0 0 1 1 0 0 1
LVCMOS25.12.2.5 0 1 0 0 0 1 0 1 1 0 1 0 1
LVCMOS25.12.3.3 0 1 0 0 0 1 0 1 0 1 0 1 0
LVCMOS25.16.2.5 0 1 0 1 1 0 1 0 0 0 1 1 1
LVCMOS25.16.3.3 0 1 0 1 1 0 0 1 1 1 0 0 0
LVCMOS25.2.2.5 0 0 0 0 1 1 0 0 0 1 0 0 1
LVCMOS25.2.3.3 0 0 0 0 1 1 0 0 0 0 1 1 1
LVCMOS25.24.2.5 1 0 0 0 0 1 1 1 0 1 0 1 0
LVCMOS25.24.3.3 1 0 0 0 0 1 1 0 1 0 0 1 1
LVCMOS25.4.2.5 0 0 0 1 1 0 0 0 1 0 0 1 0
LVCMOS25.4.3.3 0 0 0 1 1 0 0 0 0 1 1 1 0
LVCMOS25.6.2.5 0 0 1 0 0 1 0 0 1 1 0 1 1
LVCMOS25.6.3.3 0 0 1 0 0 1 0 0 1 0 1 0 1
LVCMOS25.8.2.5 0 0 1 0 1 1 0 1 0 0 1 0 0
LVCMOS25.8.3.3 0 0 1 0 1 1 0 0 1 1 1 0 0
LVCMOS33.12.2.5 0 0 1 1 0 1 0 1 1 0 1 0 1
LVCMOS33.12.3.3 0 0 1 1 0 1 0 1 0 1 0 1 0
LVCMOS33.16.2.5 0 1 0 0 1 0 1 0 0 0 1 1 1
LVCMOS33.16.3.3 0 1 0 0 1 0 0 1 1 1 0 0 0
LVCMOS33.2.2.5 0 0 0 0 1 1 0 0 0 1 0 0 1
LVCMOS33.2.3.3 0 0 0 0 1 1 0 0 0 0 1 1 1
LVCMOS33.24.2.5 0 1 1 0 1 0 1 1 0 1 0 1 0
LVCMOS33.24.3.3 0 1 1 0 1 0 1 0 1 0 0 1 1
LVCMOS33.4.2.5 0 0 0 1 0 1 0 0 1 0 0 1 0
LVCMOS33.4.3.3 0 0 0 1 0 1 0 0 0 1 1 1 0
LVCMOS33.6.2.5 0 0 0 1 1 1 0 0 1 1 0 1 1
LVCMOS33.6.3.3 0 0 0 1 1 1 0 0 1 0 1 0 1
LVCMOS33.8.2.5 0 0 1 0 0 1 0 1 0 0 1 0 0
LVCMOS33.8.3.3 0 0 1 0 0 1 0 0 1 1 1 0 0
LVTTL.12.2.5 0 0 1 0 1 0 0 1 1 0 1 0 1
LVTTL.12.3.3 0 0 1 0 1 0 0 1 0 1 0 1 0
LVTTL.16.2.5 0 0 1 1 0 1 1 0 0 0 1 1 1
LVTTL.16.3.3 0 0 1 1 0 1 0 1 1 1 0 0 0
LVTTL.2.2.5 0 0 0 0 1 0 0 0 0 1 0 0 1
LVTTL.2.3.3 0 0 0 0 1 0 0 0 0 0 1 1 1
LVTTL.24.2.5 0 1 0 0 1 1 1 1 0 1 0 1 0
LVTTL.24.3.3 0 1 0 0 1 1 1 0 1 0 0 1 1
LVTTL.4.2.5 0 0 0 1 0 0 0 0 1 0 0 1 0
LVTTL.4.3.3 0 0 0 1 0 0 0 0 0 1 1 1 0
LVTTL.6.2.5 0 0 0 1 0 1 0 0 1 1 0 1 1
LVTTL.6.3.3 0 0 0 1 0 1 0 0 1 0 1 0 1
LVTTL.8.2.5 0 0 0 1 1 1 0 1 0 0 1 0 0
LVTTL.8.3.3 0 0 0 1 1 1 0 0 1 1 1 0 0
MOBILE_DDR.2.5 0 1 0 0 0 0 0 0 1 1 0 1 1
MOBILE_DDR.3.3 0 1 0 0 0 0 0 0 1 0 1 0 0
OFF 0 0 0 0 0 0 0 0 0 0 0 0 0
PCI33_3.3.3 0 1 1 0 0 1 1 0 1 0 0 0 0
PCI66_3.3.3 0 1 1 0 0 1 1 0 1 0 0 0 0
SDIO.2.5 0 0 1 0 0 1 0 1 0 0 1 0 0
SDIO.3.3 0 0 1 0 0 1 0 0 1 1 1 0 0
SMBUS.2.5 0 0 0 0 0 0 0 0 1 0 0 1 0
SMBUS.3.3 0 0 0 0 0 0 0 0 0 1 1 1 0
SSTL15_II.2.5 1 0 1 1 0 1 1 0 1 0 0 0 0
SSTL15_II.3.3 1 0 1 1 0 1 1 0 0 0 0 0 0
SSTL18_I.2.5 0 0 1 1 1 0 0 0 1 1 1 1 0
SSTL18_I.3.3 0 0 1 1 1 0 0 0 1 1 0 0 0
SSTL18_II.2.5 1 0 0 1 0 1 1 0 1 0 0 1 1
SSTL18_II.3.3 1 0 0 1 0 1 1 0 0 0 0 1 0
SSTL2_I.2.5 0 0 1 0 0 1 0 0 1 1 1 0 0
SSTL2_I.3.3 0 0 1 0 0 1 0 0 1 0 1 1 0
SSTL2_II.2.5 0 1 1 0 0 1 1 0 0 1 1 1 1
SSTL2_II.3.3 0 1 1 0 0 1 0 1 1 1 1 1 0
SSTL3_I.2.5 0 0 0 1 0 1 0 0 1 1 0 0 0
SSTL3_I.3.3 0 0 0 1 0 1 0 0 1 0 0 1 0
SSTL3_II.2.5 0 0 1 0 1 0 0 1 1 1 1 0 0
SSTL3_II.3.3 0 0 1 0 1 0 0 1 0 1 1 1 0
TML_33.3.3 0 0 0 1 1 0 0 0 0 0 0 0 0
UNTUNED_25.1200.2.5 1 0 0 0 1 0 0 1 0 0 1 0 0
UNTUNED_25.1200.3.3 1 0 0 0 1 0 0 0 1 1 1 1 1
UNTUNED_25.1500.2.5 0 1 1 0 1 0 0 1 0 0 1 0 1
UNTUNED_25.1500.3.3 0 1 1 0 1 0 0 0 1 1 1 1 1
UNTUNED_25.1800.2.5 0 1 0 1 0 1 0 1 0 0 1 1 0
UNTUNED_25.1800.3.3 0 1 0 1 0 1 0 1 0 0 0 0 0
UNTUNED_25.2500.2.5 0 1 0 0 0 0 0 1 0 1 0 0 1
UNTUNED_25.2500.3.3 0 1 0 0 0 0 0 1 0 0 0 1 0
UNTUNED_25.3300.2.5 0 0 1 1 0 1 0 1 0 1 1 0 1
UNTUNED_25.3300.3.3 0 0 1 1 0 1 0 1 0 0 1 0 0
UNTUNED_50.1200.2.5 0 1 0 0 0 1 0 0 1 0 0 1 0
UNTUNED_50.1200.3.3 0 1 0 0 0 1 0 0 0 1 1 1 1
UNTUNED_50.1500.2.5 0 0 1 1 0 1 0 0 1 0 0 1 0
UNTUNED_50.1500.3.3 0 0 1 1 0 1 0 0 0 1 1 1 1
UNTUNED_50.1800.2.5 0 0 1 0 1 0 0 0 1 0 0 1 1
UNTUNED_50.1800.3.3 0 0 1 0 1 0 0 0 1 0 0 0 0
UNTUNED_50.2500.2.5 0 0 1 0 0 0 0 0 1 0 1 0 0
UNTUNED_50.2500.3.3 0 0 1 0 0 0 0 0 1 0 0 0 1
UNTUNED_50.3300.2.5 0 0 0 1 1 0 0 0 1 0 1 1 0
UNTUNED_50.3300.3.3 0 0 0 1 1 0 0 0 1 0 0 1 0
UNTUNED_75.1200.2.5 0 0 1 0 1 1 0 0 0 1 1 0 0
UNTUNED_75.1200.3.3 0 0 1 0 1 1 0 0 0 1 0 1 0
UNTUNED_75.1500.2.5 0 0 1 0 0 0 0 0 0 1 1 0 0
UNTUNED_75.1500.3.3 0 0 1 0 0 0 0 0 0 1 0 1 0
UNTUNED_75.1800.2.5 0 0 0 1 1 1 0 0 0 1 1 0 0
UNTUNED_75.1800.3.3 0 0 0 1 1 1 0 0 0 1 0 1 0
UNTUNED_75.2500.2.5 0 0 0 1 0 1 0 0 0 1 1 0 1
UNTUNED_75.2500.3.3 0 0 0 1 0 1 0 0 0 1 0 1 1
UNTUNED_75.3300.2.5 0 0 0 1 0 0 0 0 0 1 1 1 1
UNTUNED_75.3300.3.3 0 0 0 1 0 0 0 0 0 1 1 0 0
Name IOSTD:PTERM IOSTD:NTERM
[5] [4] [3] [2] [1] [0] [6] [5] [4] [3] [2] [1] [0]
OFF 0 0 0 0 0 0 0 0 0 0 0 0 0
TML_33.3.3 0 0 0 1 1 0 0 0 0 0 0 0 0
UNTUNED_SPLIT_25.1200.2.5 1 0 1 0 1 1 0 0 1 1 1 1 1
UNTUNED_SPLIT_25.1200.3.3 1 0 1 0 0 0 0 0 1 1 0 1 0
UNTUNED_SPLIT_25.1500.2.5 1 0 0 0 0 0 0 1 0 0 1 0 0
UNTUNED_SPLIT_25.1500.3.3 0 1 1 1 0 1 0 0 1 1 0 1 1
UNTUNED_SPLIT_25.1800.2.5 0 1 1 0 1 1 0 1 0 1 0 1 1
UNTUNED_SPLIT_25.1800.3.3 0 1 1 0 0 0 0 0 1 1 1 0 1
UNTUNED_SPLIT_25.2500.2.5 0 1 1 0 0 0 1 0 0 0 0 0 0
UNTUNED_SPLIT_25.2500.3.3 0 1 0 1 0 0 0 1 0 1 0 0 1
UNTUNED_SPLIT_25.3300.2.5 0 1 1 0 0 0 1 0 1 1 0 1 1
UNTUNED_SPLIT_25.3300.3.3 0 1 0 1 0 0 0 1 1 1 0 1 0
UNTUNED_SPLIT_50.1200.2.5 0 1 0 1 0 1 0 0 0 1 1 1 1
UNTUNED_SPLIT_50.1200.3.3 0 1 0 1 0 0 0 0 0 1 1 0 0
UNTUNED_SPLIT_50.1500.2.5 0 1 0 0 0 0 0 0 1 0 0 1 0
UNTUNED_SPLIT_50.1500.3.3 0 0 1 1 1 1 0 0 0 1 1 0 1
UNTUNED_SPLIT_50.1800.2.5 0 0 1 1 1 0 0 0 1 0 1 0 1
UNTUNED_SPLIT_50.1800.3.3 0 0 1 1 0 0 0 0 0 1 1 1 0
UNTUNED_SPLIT_50.2500.2.5 0 0 1 1 0 0 0 1 0 0 0 0 0
UNTUNED_SPLIT_50.2500.3.3 0 0 1 0 1 0 0 0 1 0 0 1 1
UNTUNED_SPLIT_50.3300.2.5 0 0 1 1 0 0 0 1 0 1 1 1 0
UNTUNED_SPLIT_50.3300.3.3 0 0 1 0 1 0 0 0 1 1 1 0 0
UNTUNED_SPLIT_75.1200.2.5 0 0 1 1 1 0 0 0 0 1 0 1 0
UNTUNED_SPLIT_75.1200.3.3 0 0 1 1 1 0 0 0 0 1 0 0 1
UNTUNED_SPLIT_75.1500.2.5 0 0 1 0 1 0 0 0 0 1 0 1 1
UNTUNED_SPLIT_75.1500.3.3 0 0 1 0 0 1 0 0 0 1 0 0 1
UNTUNED_SPLIT_75.1800.2.5 0 0 1 0 0 1 0 0 0 1 1 1 0
UNTUNED_SPLIT_75.1800.3.3 0 0 1 0 0 0 0 0 0 1 0 1 0
UNTUNED_SPLIT_75.2500.2.5 0 0 1 0 0 0 0 0 1 0 1 0 0
UNTUNED_SPLIT_75.2500.3.3 0 0 0 1 1 1 0 0 0 1 1 0 1
UNTUNED_SPLIT_75.3300.2.5 0 0 1 0 0 0 0 0 1 1 1 1 0
UNTUNED_SPLIT_75.3300.3.3 0 0 0 1 1 1 0 0 1 0 0 1 1
Name IOSTD:PSLEW IOSTD:NSLEW
[3] [2] [1] [0] [3] [2] [1] [0]
BLVDS_25 1 0 0 0 1 0 0 0
DIFF_MOBILE_DDR 1 0 0 0 1 0 0 0
DISPLAY_PORT 1 0 0 0 1 0 0 0
HSTL_I 1 0 0 0 1 0 0 0
HSTL_II 1 0 0 0 1 0 0 0
HSTL_III 1 0 0 0 1 0 0 0
HSTL_III_18 1 0 0 0 1 0 0 0
HSTL_II_18 1 0 0 0 1 0 0 0
HSTL_I_18 1 0 0 0 1 0 0 0
I2C 0 1 0 0 0 1 0 0
IN_TERM 0 1 0 0 0 1 0 0
LVCMOS12.FAST 1 0 0 0 1 0 0 0
LVCMOS12.QUIETIO 0 0 1 0 0 0 1 0
LVCMOS12.SLOW 0 1 0 0 0 1 0 0
LVCMOS12_JEDEC.FAST 1 0 0 0 1 0 0 0
LVCMOS12_JEDEC.QUIETIO 0 0 1 0 0 0 1 0
LVCMOS12_JEDEC.SLOW 0 1 0 0 0 1 0 0
LVCMOS15.FAST 1 0 0 0 1 0 0 0
LVCMOS15.QUIETIO 0 0 1 0 0 0 1 0
LVCMOS15.SLOW 0 1 0 0 0 1 0 0
LVCMOS15_JEDEC.FAST 1 0 0 0 1 0 0 0
LVCMOS15_JEDEC.QUIETIO 0 0 1 0 0 0 1 0
LVCMOS15_JEDEC.SLOW 0 1 0 0 0 1 0 0
LVCMOS18.FAST 1 0 0 0 1 0 0 0
LVCMOS18.QUIETIO 0 0 1 0 0 0 1 0
LVCMOS18.SLOW 0 1 0 0 0 1 0 0
LVCMOS18_JEDEC.FAST 1 0 0 0 1 0 0 0
LVCMOS18_JEDEC.QUIETIO 0 0 1 0 0 0 1 0
LVCMOS18_JEDEC.SLOW 0 1 0 0 0 1 0 0
LVCMOS25.FAST 1 0 0 0 1 0 0 0
LVCMOS25.QUIETIO 0 0 1 0 0 0 1 0
LVCMOS25.SLOW 0 1 0 0 0 1 0 0
LVCMOS33.FAST 1 0 0 0 1 0 0 0
LVCMOS33.QUIETIO 0 0 1 0 0 0 1 0
LVCMOS33.SLOW 0 1 0 0 0 1 0 0
LVTTL.FAST 1 0 0 0 1 0 0 0
LVTTL.QUIETIO 0 0 1 0 0 0 1 0
LVTTL.SLOW 0 1 0 0 0 1 0 0
MOBILE_DDR 1 0 0 0 1 0 0 0
OFF 0 0 0 0 0 0 0 0
PCI33_3 0 0 0 1 0 0 0 1
PCI66_3 0 0 0 1 0 0 0 1
SDIO 0 1 0 0 0 1 0 0
SMBUS 0 1 0 0 0 1 0 0
SSTL15_II 1 1 1 1 1 1 1 1
SSTL18_I 1 0 0 0 1 0 0 0
SSTL18_II 1 0 0 0 1 0 0 0
SSTL2_I 1 0 0 0 1 0 0 0
SSTL2_II 1 0 0 0 1 0 0 0
SSTL3_I 1 0 0 0 1 0 0 0
SSTL3_II 1 0 0 0 1 0 0 0
TML_33 0 1 0 0 0 1 0 0
Name IOSTD:LVDSBIAS
[11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
LVDS_25 1 0 0 0 1 0 1 1 1 0 0 1
LVDS_33 1 0 0 0 1 0 1 1 1 0 0 1
MINI_LVDS_25 0 1 1 1 1 1 0 1 0 0 0 1
MINI_LVDS_33 0 1 1 1 1 1 0 1 0 0 0 1
PPDS_25 0 1 0 0 0 0 1 1 0 1 1 1
PPDS_33 0 1 0 0 0 0 1 1 0 1 1 1
RSDS_25 1 0 0 0 1 0 0 1 0 1 0 1
RSDS_33 1 0 0 0 1 0 0 1 0 1 0 1
TMDS_33 1 0 1 0 0 1 1 0 0 1 0 1
TML_33 1 0 1 0 0 1 1 1 1 1 1 1