Hard PCI logic
Tile PCILOGICSE
Cells: 1
Bel PCILOGICSE
| Pin | Direction | Wires | 
|---|---|---|
| I1 | input | IMUX.LOGICIN24 | 
| I2 | input | IMUX.LOGICIN7 | 
| I3 | input | IMUX.LOGICIN5 | 
Bel wires
| Wire | Pins | 
|---|---|
| IMUX.LOGICIN5 | PCILOGICSE.I3 | 
| IMUX.LOGICIN7 | PCILOGICSE.I2 | 
| IMUX.LOGICIN24 | PCILOGICSE.I1 | 
Bitstream
| Bit | Frame | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCILOGICSE:ENABLE | 
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCILOGICSE:PCI_CE_DELAY[4] | 
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCILOGICSE:PCI_CE_DELAY[3] | 
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCILOGICSE:PCI_CE_DELAY[2] | 
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCILOGICSE:PCI_CE_DELAY[1] | 
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PCILOGICSE:PCI_CE_DELAY[0] | 
| PCILOGICSE:ENABLE | 0.22.5 | 
|---|---|
| non-inverted | [0] | 
| PCILOGICSE:PCI_CE_DELAY | 0.22.4 | 0.22.3 | 0.22.2 | 0.22.1 | 0.22.0 | 
|---|---|---|---|---|---|
| TAP31 | 0 | 0 | 0 | 0 | 1 | 
| TAP30 | 0 | 0 | 0 | 1 | 0 | 
| TAP29 | 0 | 0 | 0 | 1 | 1 | 
| TAP28 | 0 | 0 | 1 | 0 | 0 | 
| TAP27 | 0 | 0 | 1 | 0 | 1 | 
| TAP26 | 0 | 0 | 1 | 1 | 0 | 
| TAP25 | 0 | 0 | 1 | 1 | 1 | 
| TAP24 | 0 | 1 | 0 | 0 | 0 | 
| TAP23 | 0 | 1 | 0 | 0 | 1 | 
| TAP22 | 0 | 1 | 0 | 1 | 0 | 
| TAP21 | 0 | 1 | 0 | 1 | 1 | 
| TAP20 | 0 | 1 | 1 | 0 | 0 | 
| TAP19 | 0 | 1 | 1 | 0 | 1 | 
| TAP18 | 0 | 1 | 1 | 1 | 0 | 
| TAP17 | 0 | 1 | 1 | 1 | 1 | 
| TAP16 | 1 | 0 | 0 | 0 | 0 | 
| TAP15 | 1 | 0 | 0 | 0 | 1 | 
| TAP14 | 1 | 0 | 0 | 1 | 0 | 
| TAP13 | 1 | 0 | 0 | 1 | 1 | 
| TAP12 | 1 | 0 | 1 | 0 | 0 | 
| TAP11 | 1 | 0 | 1 | 0 | 1 | 
| TAP10 | 1 | 0 | 1 | 1 | 0 | 
| TAP9 | 1 | 0 | 1 | 1 | 1 | 
| TAP8 | 1 | 1 | 0 | 0 | 0 | 
| TAP7 | 1 | 1 | 0 | 0 | 1 | 
| TAP6 | 1 | 1 | 0 | 1 | 0 | 
| TAP5 | 1 | 1 | 0 | 1 | 1 | 
| TAP4 | 1 | 1 | 1 | 0 | 0 | 
| TAP3 | 1 | 1 | 1 | 0 | 1 | 
| TAP2 | 1 | 1 | 1 | 1 | 0 | 
Tile PCI_CE_TRUNK_BUF
Cells: 0
Bel PCI_CE_TRUNK_BUF
| Pin | Direction | Wires | 
|---|
Tile PCI_CE_SPLIT
Cells: 0
Bel PCI_CE_SPLIT
| Pin | Direction | Wires | 
|---|
Tile PCI_CE_H_BUF
Cells: 0
Bel PCI_CE_H_BUF
| Pin | Direction | Wires | 
|---|
Tile PCI_CE_V_BUF
Cells: 0
Bel PCI_CE_V_BUF
| Pin | Direction | Wires | 
|---|
PCI_CE_DELAY
| Device | PCI_CE_DELAY | 
|---|---|
| xc6slx9 | TAP6 | 
| xa6slx9 | TAP6 | 
| xc6slx9l | TAP6 | 
| xc6slx4 | TAP6 | 
| xa6slx4 | TAP6 | 
| xc6slx4l | TAP6 | 
| xc6slx16 | TAP6 | 
| xa6slx16 | TAP6 | 
| xc6slx16l | TAP6 | 
| xc6slx25t | TAP6 | 
| xa6slx25t | TAP6 | 
| xc6slx25 | TAP6 | 
| xa6slx25 | TAP6 | 
| xc6slx25l | TAP6 | 
| xc6slx45t | TAP6 | 
| xa6slx45t | TAP6 | 
| xc6slx45 | TAP6 | 
| xa6slx45 | TAP6 | 
| xc6slx45l | TAP6 | 
| xc6slx75t | TAP9 | 
| xa6slx75t | TAP9 | 
| xq6slx75t | TAP9 | 
| xc6slx75 | TAP9 | 
| xa6slx75 | TAP9 | 
| xq6slx75 | TAP9 | 
| xc6slx75l | TAP9 | 
| xq6slx75l | TAP9 | 
| xc6slx100t | TAP9 | 
| xc6slx100 | TAP9 | 
| xa6slx100 | TAP9 | 
| xc6slx100l | TAP9 | 
| xc6slx150t | TAP9 | 
| xq6slx150t | TAP9 | 
| xc6slx150 | TAP9 | 
| xq6slx150 | TAP9 | 
| xc6slx150l | TAP9 | 
| xq6slx150l | TAP9 |