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Memory Controller Block

TODO: document

Tile MCB

Cells: 28 IRIs: 0

Bel MCB

spartan6 MCB bel MCB
PinDirectionWires
P0ARBENinputTCELL11:IMUX.LOGICIN29
P0CMDBA0inputTCELL10:IMUX.LOGICIN7
P0CMDBA1inputTCELL10:IMUX.LOGICIN36
P0CMDBA2inputTCELL10:IMUX.LOGICIN16
P0CMDBL0inputTCELL10:IMUX.LOGICIN57
P0CMDBL1inputTCELL10:IMUX.LOGICIN44
P0CMDBL2inputTCELL10:IMUX.LOGICIN4
P0CMDBL3inputTCELL10:IMUX.LOGICIN55
P0CMDBL4inputTCELL10:IMUX.LOGICIN26
P0CMDBL5inputTCELL10:IMUX.LOGICIN30
P0CMDCA0inputTCELL11:IMUX.LOGICIN7
P0CMDCA1inputTCELL11:IMUX.LOGICIN36
P0CMDCA10inputTCELL11:IMUX.LOGICIN4
P0CMDCA11inputTCELL11:IMUX.LOGICIN55
P0CMDCA2inputTCELL11:IMUX.LOGICIN12
P0CMDCA3inputTCELL11:IMUX.LOGICIN47
P0CMDCA4inputTCELL11:IMUX.LOGICIN45
P0CMDCA5inputTCELL11:IMUX.LOGICIN17
P0CMDCA6inputTCELL11:IMUX.LOGICIN23
P0CMDCA7inputTCELL11:IMUX.LOGICIN25
P0CMDCA8inputTCELL11:IMUX.LOGICIN57
P0CMDCA9inputTCELL11:IMUX.LOGICIN44
P0CMDCLKinputTCELL11:IMUX.CLK1
P0CMDEMPTYoutputTCELL11:OUT6
P0CMDENinputTCELL10:IMUX.LOGICIN47
P0CMDFULLoutputTCELL11:OUT3
P0CMDINSTR0inputTCELL10:IMUX.LOGICIN20
P0CMDINSTR1inputTCELL10:IMUX.LOGICIN17
P0CMDINSTR2inputTCELL10:IMUX.LOGICIN34
P0CMDRA0inputTCELL11:IMUX.LOGICIN26
P0CMDRA1inputTCELL11:IMUX.LOGICIN30
P0CMDRA10inputTCELL11:IMUX.LOGICIN14
P0CMDRA11inputTCELL11:IMUX.LOGICIN37
P0CMDRA12inputTCELL11:IMUX.LOGICIN31
P0CMDRA13inputTCELL10:IMUX.LOGICIN24
P0CMDRA14inputTCELL10:IMUX.LOGICIN15
P0CMDRA2inputTCELL11:IMUX.LOGICIN10
P0CMDRA3inputTCELL11:IMUX.LOGICIN3
P0CMDRA4inputTCELL11:IMUX.LOGICIN1
P0CMDRA5inputTCELL11:IMUX.LOGICIN28
P0CMDRA6inputTCELL11:IMUX.LOGICIN27
P0CMDRA7inputTCELL11:IMUX.LOGICIN32
P0CMDRA8inputTCELL11:IMUX.LOGICIN59
P0CMDRA9inputTCELL11:IMUX.LOGICIN2
P0RDCLKinputTCELL13:IMUX.CLK1
P0RDCOUNT0outputTCELL13:OUT12
P0RDCOUNT1outputTCELL13:OUT19
P0RDCOUNT2outputTCELL13:OUT14
P0RDCOUNT3outputTCELL13:OUT2
P0RDCOUNT4outputTCELL12:OUT9
P0RDCOUNT5outputTCELL12:OUT11
P0RDCOUNT6outputTCELL12:OUT23
P0RDDATA0outputTCELL12:OUT2
P0RDDATA1outputTCELL12:OUT14
P0RDDATA10outputTCELL12:OUT15
P0RDDATA11outputTCELL12:OUT3
P0RDDATA12outputTCELL12:OUT8
P0RDDATA13outputTCELL12:OUT1
P0RDDATA14outputTCELL12:OUT18
P0RDDATA15outputTCELL12:OUT20
P0RDDATA16outputTCELL12:OUT13
P0RDDATA17outputTCELL12:OUT6
P0RDDATA18outputTCELL13:OUT10
P0RDDATA19outputTCELL13:OUT17
P0RDDATA2outputTCELL12:OUT19
P0RDDATA20outputTCELL13:OUT22
P0RDDATA21outputTCELL13:OUT15
P0RDDATA22outputTCELL13:OUT3
P0RDDATA23outputTCELL13:OUT8
P0RDDATA24outputTCELL13:OUT1
P0RDDATA25outputTCELL13:OUT18
P0RDDATA26outputTCELL13:OUT20
P0RDDATA27outputTCELL13:OUT13
P0RDDATA28outputTCELL13:OUT6
P0RDDATA29outputTCELL13:OUT4
P0RDDATA3outputTCELL12:OUT7
P0RDDATA30outputTCELL13:OUT16
P0RDDATA31outputTCELL13:OUT21
P0RDDATA4outputTCELL12:OUT12
P0RDDATA5outputTCELL12:OUT0
P0RDDATA6outputTCELL12:OUT5
P0RDDATA7outputTCELL12:OUT10
P0RDDATA8outputTCELL12:OUT17
P0RDDATA9outputTCELL12:OUT22
P0RDEMPTYoutputTCELL13:OUT0
P0RDENinputTCELL13:IMUX.LOGICIN7
P0RDERRORoutputTCELL13:OUT7
P0RDFULLoutputTCELL12:OUT4
P0RDOVERFLOWoutputTCELL12:OUT16
P0RTSTENBinputTCELL12:IMUX.LOGICIN9
P0RTSTMODEB0inputTCELL12:IMUX.LOGICIN32
P0RTSTMODEB1inputTCELL12:IMUX.LOGICIN29
P0RTSTMODEB2inputTCELL12:IMUX.LOGICIN1
P0RTSTMODEB3inputTCELL12:IMUX.LOGICIN19
P0RTSTPINENBinputTCELL12:IMUX.LOGICIN59
P0RTSTUDMPoutputTCELL12:OUT21
P0RTSTUNDERRUNoutputTCELL13:OUT5
P0RTSTWRDATA0inputTCELL12:IMUX.LOGICIN15
P0RTSTWRDATA1inputTCELL12:IMUX.LOGICIN42
P0RTSTWRDATA10inputTCELL12:IMUX.LOGICIN25
P0RTSTWRDATA11inputTCELL12:IMUX.LOGICIN57
P0RTSTWRDATA12inputTCELL12:IMUX.LOGICIN44
P0RTSTWRDATA13inputTCELL12:IMUX.LOGICIN4
P0RTSTWRDATA14inputTCELL12:IMUX.LOGICIN55
P0RTSTWRDATA15inputTCELL12:IMUX.LOGICIN26
P0RTSTWRDATA16inputTCELL12:IMUX.LOGICIN30
P0RTSTWRDATA17inputTCELL12:IMUX.LOGICIN10
P0RTSTWRDATA18inputTCELL13:IMUX.LOGICIN57
P0RTSTWRDATA19inputTCELL13:IMUX.LOGICIN44
P0RTSTWRDATA2inputTCELL12:IMUX.LOGICIN7
P0RTSTWRDATA20inputTCELL13:IMUX.LOGICIN4
P0RTSTWRDATA21inputTCELL13:IMUX.LOGICIN55
P0RTSTWRDATA22inputTCELL13:IMUX.LOGICIN26
P0RTSTWRDATA23inputTCELL13:IMUX.LOGICIN30
P0RTSTWRDATA24inputTCELL13:IMUX.LOGICIN41
P0RTSTWRDATA25inputTCELL13:IMUX.LOGICIN10
P0RTSTWRDATA26inputTCELL13:IMUX.LOGICIN3
P0RTSTWRDATA27inputTCELL13:IMUX.LOGICIN1
P0RTSTWRDATA28inputTCELL13:IMUX.LOGICIN19
P0RTSTWRDATA29inputTCELL13:IMUX.LOGICIN27
P0RTSTWRDATA3inputTCELL12:IMUX.LOGICIN12
P0RTSTWRDATA30inputTCELL13:IMUX.LOGICIN29
P0RTSTWRDATA31inputTCELL13:IMUX.LOGICIN32
P0RTSTWRDATA4inputTCELL12:IMUX.LOGICIN62
P0RTSTWRDATA5inputTCELL12:IMUX.LOGICIN20
P0RTSTWRDATA6inputTCELL12:IMUX.LOGICIN38
P0RTSTWRDATA7inputTCELL12:IMUX.LOGICIN17
P0RTSTWRDATA8inputTCELL12:IMUX.LOGICIN23
P0RTSTWRDATA9inputTCELL12:IMUX.LOGICIN48
P0RTSTWRMASK0inputTCELL13:IMUX.LOGICIN52
P0RTSTWRMASK1inputTCELL13:IMUX.LOGICIN2
P0RTSTWRMASK2inputTCELL13:IMUX.LOGICIN14
P0RTSTWRMASK3inputTCELL13:IMUX.LOGICIN37
P0RWRMASK0inputTCELL15:IMUX.LOGICIN52
P0RWRMASK1inputTCELL15:IMUX.LOGICIN2
P0RWRMASK2inputTCELL15:IMUX.LOGICIN14
P0RWRMASK3inputTCELL15:IMUX.LOGICIN37
P0WRCLKinputTCELL15:IMUX.CLK1
P0WRCOUNT0outputTCELL15:OUT12
P0WRCOUNT1outputTCELL15:OUT19
P0WRCOUNT2outputTCELL15:OUT14
P0WRCOUNT3outputTCELL15:OUT2
P0WRCOUNT4outputTCELL14:OUT9
P0WRCOUNT5outputTCELL14:OUT11
P0WRCOUNT6outputTCELL14:OUT23
P0WRDATA0inputTCELL14:IMUX.LOGICIN15
P0WRDATA1inputTCELL14:IMUX.LOGICIN42
P0WRDATA10inputTCELL14:IMUX.LOGICIN25
P0WRDATA11inputTCELL14:IMUX.LOGICIN57
P0WRDATA12inputTCELL14:IMUX.LOGICIN44
P0WRDATA13inputTCELL14:IMUX.LOGICIN4
P0WRDATA14inputTCELL14:IMUX.LOGICIN55
P0WRDATA15inputTCELL14:IMUX.LOGICIN26
P0WRDATA16inputTCELL14:IMUX.LOGICIN30
P0WRDATA17inputTCELL14:IMUX.LOGICIN10
P0WRDATA18inputTCELL15:IMUX.LOGICIN57
P0WRDATA19inputTCELL15:IMUX.LOGICIN44
P0WRDATA2inputTCELL14:IMUX.LOGICIN7
P0WRDATA20inputTCELL15:IMUX.LOGICIN4
P0WRDATA21inputTCELL15:IMUX.LOGICIN55
P0WRDATA22inputTCELL15:IMUX.LOGICIN26
P0WRDATA23inputTCELL15:IMUX.LOGICIN30
P0WRDATA24inputTCELL15:IMUX.LOGICIN41
P0WRDATA25inputTCELL15:IMUX.LOGICIN10
P0WRDATA26inputTCELL15:IMUX.LOGICIN3
P0WRDATA27inputTCELL15:IMUX.LOGICIN1
P0WRDATA28inputTCELL15:IMUX.LOGICIN19
P0WRDATA29inputTCELL15:IMUX.LOGICIN27
P0WRDATA3inputTCELL14:IMUX.LOGICIN12
P0WRDATA30inputTCELL15:IMUX.LOGICIN29
P0WRDATA31inputTCELL15:IMUX.LOGICIN32
P0WRDATA4inputTCELL14:IMUX.LOGICIN62
P0WRDATA5inputTCELL14:IMUX.LOGICIN20
P0WRDATA6inputTCELL14:IMUX.LOGICIN38
P0WRDATA7inputTCELL14:IMUX.LOGICIN17
P0WRDATA8inputTCELL14:IMUX.LOGICIN23
P0WRDATA9inputTCELL14:IMUX.LOGICIN48
P0WREMPTYoutputTCELL15:OUT0
P0WRENinputTCELL15:IMUX.LOGICIN7
P0WRERRORoutputTCELL15:OUT7
P0WRFULLoutputTCELL14:OUT4
P0WRUNDERRUNoutputTCELL15:OUT5
P0WTSTDATA0outputTCELL14:OUT2
P0WTSTDATA1outputTCELL14:OUT14
P0WTSTDATA10outputTCELL14:OUT15
P0WTSTDATA11outputTCELL14:OUT3
P0WTSTDATA12outputTCELL14:OUT8
P0WTSTDATA13outputTCELL14:OUT1
P0WTSTDATA14outputTCELL14:OUT18
P0WTSTDATA15outputTCELL14:OUT20
P0WTSTDATA16outputTCELL14:OUT13
P0WTSTDATA17outputTCELL14:OUT6
P0WTSTDATA18outputTCELL15:OUT10
P0WTSTDATA19outputTCELL15:OUT17
P0WTSTDATA2outputTCELL14:OUT19
P0WTSTDATA20outputTCELL15:OUT22
P0WTSTDATA21outputTCELL15:OUT15
P0WTSTDATA22outputTCELL15:OUT3
P0WTSTDATA23outputTCELL15:OUT8
P0WTSTDATA24outputTCELL15:OUT1
P0WTSTDATA25outputTCELL15:OUT18
P0WTSTDATA26outputTCELL15:OUT20
P0WTSTDATA27outputTCELL15:OUT13
P0WTSTDATA28outputTCELL15:OUT6
P0WTSTDATA29outputTCELL15:OUT4
P0WTSTDATA3outputTCELL14:OUT7
P0WTSTDATA30outputTCELL15:OUT16
P0WTSTDATA31outputTCELL15:OUT21
P0WTSTDATA4outputTCELL14:OUT12
P0WTSTDATA5outputTCELL14:OUT0
P0WTSTDATA6outputTCELL14:OUT5
P0WTSTDATA7outputTCELL14:OUT10
P0WTSTDATA8outputTCELL14:OUT17
P0WTSTDATA9outputTCELL14:OUT22
P0WTSTENBinputTCELL14:IMUX.LOGICIN9
P0WTSTLDMPoutputTCELL14:OUT21
P0WTSTMODEB0inputTCELL14:IMUX.LOGICIN32
P0WTSTMODEB1inputTCELL14:IMUX.LOGICIN29
P0WTSTMODEB2inputTCELL14:IMUX.LOGICIN1
P0WTSTMODEB3inputTCELL14:IMUX.LOGICIN19
P0WTSTOVERFLOWoutputTCELL14:OUT16
P0WTSTPINENBinputTCELL14:IMUX.LOGICIN59
P1ARBENinputTCELL9:IMUX.LOGICIN29
P1CMDBA0inputTCELL8:IMUX.LOGICIN7
P1CMDBA1inputTCELL8:IMUX.LOGICIN36
P1CMDBA2inputTCELL8:IMUX.LOGICIN16
P1CMDBL0inputTCELL8:IMUX.LOGICIN57
P1CMDBL1inputTCELL8:IMUX.LOGICIN44
P1CMDBL2inputTCELL8:IMUX.LOGICIN4
P1CMDBL3inputTCELL8:IMUX.LOGICIN55
P1CMDBL4inputTCELL8:IMUX.LOGICIN26
P1CMDBL5inputTCELL8:IMUX.LOGICIN30
P1CMDCA0inputTCELL9:IMUX.LOGICIN7
P1CMDCA1inputTCELL9:IMUX.LOGICIN36
P1CMDCA10inputTCELL9:IMUX.LOGICIN4
P1CMDCA11inputTCELL9:IMUX.LOGICIN55
P1CMDCA2inputTCELL9:IMUX.LOGICIN12
P1CMDCA3inputTCELL9:IMUX.LOGICIN47
P1CMDCA4inputTCELL9:IMUX.LOGICIN45
P1CMDCA5inputTCELL9:IMUX.LOGICIN17
P1CMDCA6inputTCELL9:IMUX.LOGICIN23
P1CMDCA7inputTCELL9:IMUX.LOGICIN25
P1CMDCA8inputTCELL9:IMUX.LOGICIN57
P1CMDCA9inputTCELL9:IMUX.LOGICIN44
P1CMDCLKinputTCELL9:IMUX.CLK1
P1CMDEMPTYoutputTCELL9:OUT6
P1CMDENinputTCELL8:IMUX.LOGICIN47
P1CMDFULLoutputTCELL9:OUT3
P1CMDINSTR0inputTCELL8:IMUX.LOGICIN20
P1CMDINSTR1inputTCELL8:IMUX.LOGICIN17
P1CMDINSTR2inputTCELL8:IMUX.LOGICIN34
P1CMDRA0inputTCELL9:IMUX.LOGICIN26
P1CMDRA1inputTCELL9:IMUX.LOGICIN30
P1CMDRA10inputTCELL9:IMUX.LOGICIN14
P1CMDRA11inputTCELL9:IMUX.LOGICIN37
P1CMDRA12inputTCELL9:IMUX.LOGICIN31
P1CMDRA13inputTCELL8:IMUX.LOGICIN24
P1CMDRA14inputTCELL8:IMUX.LOGICIN15
P1CMDRA2inputTCELL9:IMUX.LOGICIN10
P1CMDRA3inputTCELL9:IMUX.LOGICIN3
P1CMDRA4inputTCELL9:IMUX.LOGICIN1
P1CMDRA5inputTCELL9:IMUX.LOGICIN28
P1CMDRA6inputTCELL9:IMUX.LOGICIN27
P1CMDRA7inputTCELL9:IMUX.LOGICIN32
P1CMDRA8inputTCELL9:IMUX.LOGICIN59
P1CMDRA9inputTCELL9:IMUX.LOGICIN2
P1RDCLKinputTCELL17:IMUX.CLK1
P1RDCOUNT0outputTCELL17:OUT12
P1RDCOUNT1outputTCELL17:OUT19
P1RDCOUNT2outputTCELL17:OUT14
P1RDCOUNT3outputTCELL17:OUT2
P1RDCOUNT4outputTCELL16:OUT9
P1RDCOUNT5outputTCELL16:OUT11
P1RDCOUNT6outputTCELL16:OUT23
P1RDDATA0outputTCELL16:OUT2
P1RDDATA1outputTCELL16:OUT14
P1RDDATA10outputTCELL16:OUT15
P1RDDATA11outputTCELL16:OUT3
P1RDDATA12outputTCELL16:OUT8
P1RDDATA13outputTCELL16:OUT1
P1RDDATA14outputTCELL16:OUT18
P1RDDATA15outputTCELL16:OUT20
P1RDDATA16outputTCELL16:OUT13
P1RDDATA17outputTCELL16:OUT6
P1RDDATA18outputTCELL17:OUT10
P1RDDATA19outputTCELL17:OUT17
P1RDDATA2outputTCELL16:OUT19
P1RDDATA20outputTCELL17:OUT22
P1RDDATA21outputTCELL17:OUT15
P1RDDATA22outputTCELL17:OUT3
P1RDDATA23outputTCELL17:OUT8
P1RDDATA24outputTCELL17:OUT1
P1RDDATA25outputTCELL17:OUT18
P1RDDATA26outputTCELL17:OUT20
P1RDDATA27outputTCELL17:OUT13
P1RDDATA28outputTCELL17:OUT6
P1RDDATA29outputTCELL17:OUT4
P1RDDATA3outputTCELL16:OUT7
P1RDDATA30outputTCELL17:OUT16
P1RDDATA31outputTCELL17:OUT21
P1RDDATA4outputTCELL16:OUT12
P1RDDATA5outputTCELL16:OUT0
P1RDDATA6outputTCELL16:OUT5
P1RDDATA7outputTCELL16:OUT10
P1RDDATA8outputTCELL16:OUT17
P1RDDATA9outputTCELL16:OUT22
P1RDEMPTYoutputTCELL17:OUT0
P1RDENinputTCELL17:IMUX.LOGICIN7
P1RDERRORoutputTCELL17:OUT7
P1RDFULLoutputTCELL16:OUT4
P1RDOVERFLOWoutputTCELL16:OUT16
P1RTSTENBinputTCELL16:IMUX.LOGICIN9
P1RTSTMODEB0inputTCELL16:IMUX.LOGICIN32
P1RTSTMODEB1inputTCELL16:IMUX.LOGICIN29
P1RTSTMODEB2inputTCELL16:IMUX.LOGICIN1
P1RTSTMODEB3inputTCELL16:IMUX.LOGICIN19
P1RTSTPINENBinputTCELL16:IMUX.LOGICIN59
P1RTSTUDMNoutputTCELL16:OUT21
P1RTSTUNDERRUNoutputTCELL17:OUT5
P1RTSTWRDATA0inputTCELL16:IMUX.LOGICIN15
P1RTSTWRDATA1inputTCELL16:IMUX.LOGICIN42
P1RTSTWRDATA10inputTCELL16:IMUX.LOGICIN25
P1RTSTWRDATA11inputTCELL16:IMUX.LOGICIN57
P1RTSTWRDATA12inputTCELL16:IMUX.LOGICIN44
P1RTSTWRDATA13inputTCELL16:IMUX.LOGICIN4
P1RTSTWRDATA14inputTCELL16:IMUX.LOGICIN55
P1RTSTWRDATA15inputTCELL16:IMUX.LOGICIN26
P1RTSTWRDATA16inputTCELL16:IMUX.LOGICIN30
P1RTSTWRDATA17inputTCELL16:IMUX.LOGICIN10
P1RTSTWRDATA18inputTCELL17:IMUX.LOGICIN57
P1RTSTWRDATA19inputTCELL17:IMUX.LOGICIN44
P1RTSTWRDATA2inputTCELL16:IMUX.LOGICIN7
P1RTSTWRDATA20inputTCELL17:IMUX.LOGICIN4
P1RTSTWRDATA21inputTCELL17:IMUX.LOGICIN55
P1RTSTWRDATA22inputTCELL17:IMUX.LOGICIN26
P1RTSTWRDATA23inputTCELL17:IMUX.LOGICIN30
P1RTSTWRDATA24inputTCELL17:IMUX.LOGICIN41
P1RTSTWRDATA25inputTCELL17:IMUX.LOGICIN10
P1RTSTWRDATA26inputTCELL17:IMUX.LOGICIN3
P1RTSTWRDATA27inputTCELL17:IMUX.LOGICIN1
P1RTSTWRDATA28inputTCELL17:IMUX.LOGICIN19
P1RTSTWRDATA29inputTCELL17:IMUX.LOGICIN27
P1RTSTWRDATA3inputTCELL16:IMUX.LOGICIN12
P1RTSTWRDATA30inputTCELL17:IMUX.LOGICIN29
P1RTSTWRDATA31inputTCELL17:IMUX.LOGICIN32
P1RTSTWRDATA4inputTCELL16:IMUX.LOGICIN62
P1RTSTWRDATA5inputTCELL16:IMUX.LOGICIN20
P1RTSTWRDATA6inputTCELL16:IMUX.LOGICIN38
P1RTSTWRDATA7inputTCELL16:IMUX.LOGICIN17
P1RTSTWRDATA8inputTCELL16:IMUX.LOGICIN23
P1RTSTWRDATA9inputTCELL16:IMUX.LOGICIN48
P1RTSTWRMASK0inputTCELL17:IMUX.LOGICIN52
P1RTSTWRMASK1inputTCELL17:IMUX.LOGICIN2
P1RTSTWRMASK2inputTCELL17:IMUX.LOGICIN14
P1RTSTWRMASK3inputTCELL17:IMUX.LOGICIN37
P1RWRMASK0inputTCELL19:IMUX.LOGICIN52
P1RWRMASK1inputTCELL19:IMUX.LOGICIN2
P1RWRMASK2inputTCELL19:IMUX.LOGICIN14
P1RWRMASK3inputTCELL19:IMUX.LOGICIN37
P1WRCLKinputTCELL19:IMUX.CLK1
P1WRCOUNT0outputTCELL19:OUT12
P1WRCOUNT1outputTCELL19:OUT19
P1WRCOUNT2outputTCELL19:OUT14
P1WRCOUNT3outputTCELL19:OUT2
P1WRCOUNT4outputTCELL18:OUT9
P1WRCOUNT5outputTCELL18:OUT11
P1WRCOUNT6outputTCELL18:OUT23
P1WRDATA0inputTCELL18:IMUX.LOGICIN15
P1WRDATA1inputTCELL18:IMUX.LOGICIN42
P1WRDATA10inputTCELL18:IMUX.LOGICIN25
P1WRDATA11inputTCELL18:IMUX.LOGICIN57
P1WRDATA12inputTCELL18:IMUX.LOGICIN44
P1WRDATA13inputTCELL18:IMUX.LOGICIN4
P1WRDATA14inputTCELL18:IMUX.LOGICIN55
P1WRDATA15inputTCELL18:IMUX.LOGICIN26
P1WRDATA16inputTCELL18:IMUX.LOGICIN30
P1WRDATA17inputTCELL18:IMUX.LOGICIN10
P1WRDATA18inputTCELL19:IMUX.LOGICIN57
P1WRDATA19inputTCELL19:IMUX.LOGICIN44
P1WRDATA2inputTCELL18:IMUX.LOGICIN7
P1WRDATA20inputTCELL19:IMUX.LOGICIN4
P1WRDATA21inputTCELL19:IMUX.LOGICIN55
P1WRDATA22inputTCELL19:IMUX.LOGICIN26
P1WRDATA23inputTCELL19:IMUX.LOGICIN30
P1WRDATA24inputTCELL19:IMUX.LOGICIN41
P1WRDATA25inputTCELL19:IMUX.LOGICIN10
P1WRDATA26inputTCELL19:IMUX.LOGICIN3
P1WRDATA27inputTCELL19:IMUX.LOGICIN1
P1WRDATA28inputTCELL19:IMUX.LOGICIN19
P1WRDATA29inputTCELL19:IMUX.LOGICIN27
P1WRDATA3inputTCELL18:IMUX.LOGICIN12
P1WRDATA30inputTCELL19:IMUX.LOGICIN29
P1WRDATA31inputTCELL19:IMUX.LOGICIN32
P1WRDATA4inputTCELL18:IMUX.LOGICIN62
P1WRDATA5inputTCELL18:IMUX.LOGICIN20
P1WRDATA6inputTCELL18:IMUX.LOGICIN38
P1WRDATA7inputTCELL18:IMUX.LOGICIN17
P1WRDATA8inputTCELL18:IMUX.LOGICIN23
P1WRDATA9inputTCELL18:IMUX.LOGICIN48
P1WREMPTYoutputTCELL19:OUT0
P1WRENinputTCELL19:IMUX.LOGICIN7
P1WRERRORoutputTCELL19:OUT7
P1WRFULLoutputTCELL18:OUT4
P1WRUNDERRUNoutputTCELL19:OUT5
P1WTSTDATA0outputTCELL18:OUT2
P1WTSTDATA1outputTCELL18:OUT14
P1WTSTDATA10outputTCELL18:OUT15
P1WTSTDATA11outputTCELL18:OUT3
P1WTSTDATA12outputTCELL18:OUT8
P1WTSTDATA13outputTCELL18:OUT1
P1WTSTDATA14outputTCELL18:OUT18
P1WTSTDATA15outputTCELL18:OUT20
P1WTSTDATA16outputTCELL18:OUT13
P1WTSTDATA17outputTCELL18:OUT6
P1WTSTDATA18outputTCELL19:OUT10
P1WTSTDATA19outputTCELL19:OUT17
P1WTSTDATA2outputTCELL18:OUT19
P1WTSTDATA20outputTCELL19:OUT22
P1WTSTDATA21outputTCELL19:OUT15
P1WTSTDATA22outputTCELL19:OUT3
P1WTSTDATA23outputTCELL19:OUT8
P1WTSTDATA24outputTCELL19:OUT1
P1WTSTDATA25outputTCELL19:OUT18
P1WTSTDATA26outputTCELL19:OUT20
P1WTSTDATA27outputTCELL19:OUT13
P1WTSTDATA28outputTCELL19:OUT6
P1WTSTDATA29outputTCELL19:OUT4
P1WTSTDATA3outputTCELL18:OUT7
P1WTSTDATA30outputTCELL19:OUT16
P1WTSTDATA31outputTCELL19:OUT21
P1WTSTDATA4outputTCELL18:OUT12
P1WTSTDATA5outputTCELL18:OUT0
P1WTSTDATA6outputTCELL18:OUT5
P1WTSTDATA7outputTCELL18:OUT10
P1WTSTDATA8outputTCELL18:OUT17
P1WTSTDATA9outputTCELL18:OUT22
P1WTSTENBinputTCELL18:IMUX.LOGICIN9
P1WTSTLDMNoutputTCELL18:OUT21
P1WTSTMODEB0inputTCELL18:IMUX.LOGICIN32
P1WTSTMODEB1inputTCELL18:IMUX.LOGICIN29
P1WTSTMODEB2inputTCELL18:IMUX.LOGICIN1
P1WTSTMODEB3inputTCELL18:IMUX.LOGICIN19
P1WTSTOVERFLOWoutputTCELL18:OUT16
P1WTSTPINENBinputTCELL18:IMUX.LOGICIN59
P2ARBENinputTCELL7:IMUX.LOGICIN29
P2CLKinputTCELL21:IMUX.CLK1
P2CMDBA0inputTCELL6:IMUX.LOGICIN7
P2CMDBA1inputTCELL6:IMUX.LOGICIN36
P2CMDBA2inputTCELL6:IMUX.LOGICIN16
P2CMDBL0inputTCELL6:IMUX.LOGICIN57
P2CMDBL1inputTCELL6:IMUX.LOGICIN44
P2CMDBL2inputTCELL6:IMUX.LOGICIN4
P2CMDBL3inputTCELL6:IMUX.LOGICIN55
P2CMDBL4inputTCELL6:IMUX.LOGICIN26
P2CMDBL5inputTCELL6:IMUX.LOGICIN30
P2CMDCA0inputTCELL7:IMUX.LOGICIN7
P2CMDCA1inputTCELL7:IMUX.LOGICIN36
P2CMDCA10inputTCELL7:IMUX.LOGICIN4
P2CMDCA11inputTCELL7:IMUX.LOGICIN55
P2CMDCA2inputTCELL7:IMUX.LOGICIN12
P2CMDCA3inputTCELL7:IMUX.LOGICIN47
P2CMDCA4inputTCELL7:IMUX.LOGICIN45
P2CMDCA5inputTCELL7:IMUX.LOGICIN17
P2CMDCA6inputTCELL7:IMUX.LOGICIN23
P2CMDCA7inputTCELL7:IMUX.LOGICIN25
P2CMDCA8inputTCELL7:IMUX.LOGICIN57
P2CMDCA9inputTCELL7:IMUX.LOGICIN44
P2CMDCLKinputTCELL7:IMUX.CLK1
P2CMDEMPTYoutputTCELL7:OUT6
P2CMDENinputTCELL6:IMUX.LOGICIN47
P2CMDFULLoutputTCELL7:OUT3
P2CMDINSTR0inputTCELL6:IMUX.LOGICIN20
P2CMDINSTR1inputTCELL6:IMUX.LOGICIN17
P2CMDINSTR2inputTCELL6:IMUX.LOGICIN34
P2CMDRA0inputTCELL7:IMUX.LOGICIN26
P2CMDRA1inputTCELL7:IMUX.LOGICIN30
P2CMDRA10inputTCELL7:IMUX.LOGICIN14
P2CMDRA11inputTCELL7:IMUX.LOGICIN37
P2CMDRA12inputTCELL7:IMUX.LOGICIN31
P2CMDRA13inputTCELL6:IMUX.LOGICIN24
P2CMDRA14inputTCELL6:IMUX.LOGICIN15
P2CMDRA2inputTCELL7:IMUX.LOGICIN10
P2CMDRA3inputTCELL7:IMUX.LOGICIN3
P2CMDRA4inputTCELL7:IMUX.LOGICIN1
P2CMDRA5inputTCELL7:IMUX.LOGICIN28
P2CMDRA6inputTCELL7:IMUX.LOGICIN27
P2CMDRA7inputTCELL7:IMUX.LOGICIN32
P2CMDRA8inputTCELL7:IMUX.LOGICIN59
P2CMDRA9inputTCELL7:IMUX.LOGICIN2
P2COUNT0outputTCELL21:OUT12
P2COUNT1outputTCELL21:OUT19
P2COUNT2outputTCELL21:OUT14
P2COUNT3outputTCELL21:OUT2
P2COUNT4outputTCELL20:OUT9
P2COUNT5outputTCELL20:OUT11
P2COUNT6outputTCELL20:OUT23
P2EMPTYoutputTCELL21:OUT0
P2ENinputTCELL21:IMUX.LOGICIN7
P2ERRORoutputTCELL21:OUT7
P2FULLoutputTCELL20:OUT4
P2RDDATA0outputTCELL20:OUT2
P2RDDATA1outputTCELL20:OUT14
P2RDDATA10outputTCELL20:OUT15
P2RDDATA11outputTCELL20:OUT3
P2RDDATA12outputTCELL20:OUT8
P2RDDATA13outputTCELL20:OUT1
P2RDDATA14outputTCELL20:OUT18
P2RDDATA15outputTCELL20:OUT20
P2RDDATA16outputTCELL20:OUT13
P2RDDATA17outputTCELL20:OUT6
P2RDDATA18outputTCELL21:OUT10
P2RDDATA19outputTCELL21:OUT17
P2RDDATA2outputTCELL20:OUT19
P2RDDATA20outputTCELL21:OUT22
P2RDDATA21outputTCELL21:OUT15
P2RDDATA22outputTCELL21:OUT3
P2RDDATA23outputTCELL21:OUT8
P2RDDATA24outputTCELL21:OUT1
P2RDDATA25outputTCELL21:OUT18
P2RDDATA26outputTCELL21:OUT20
P2RDDATA27outputTCELL21:OUT13
P2RDDATA28outputTCELL21:OUT6
P2RDDATA29outputTCELL21:OUT4
P2RDDATA3outputTCELL20:OUT7
P2RDDATA30outputTCELL21:OUT16
P2RDDATA31outputTCELL21:OUT21
P2RDDATA4outputTCELL20:OUT12
P2RDDATA5outputTCELL20:OUT0
P2RDDATA6outputTCELL20:OUT5
P2RDDATA7outputTCELL20:OUT10
P2RDDATA8outputTCELL20:OUT17
P2RDDATA9outputTCELL20:OUT22
P2RDOVERFLOWoutputTCELL20:OUT16
P2TSTENBinputTCELL20:IMUX.LOGICIN9
P2TSTMODEB0inputTCELL20:IMUX.LOGICIN32
P2TSTMODEB1inputTCELL20:IMUX.LOGICIN29
P2TSTMODEB2inputTCELL20:IMUX.LOGICIN1
P2TSTMODEB3inputTCELL20:IMUX.LOGICIN19
P2TSTPINENBinputTCELL20:IMUX.LOGICIN59
P2TSTUDMPoutputTCELL20:OUT21
P2WRDATA0inputTCELL20:IMUX.LOGICIN15
P2WRDATA1inputTCELL20:IMUX.LOGICIN42
P2WRDATA10inputTCELL20:IMUX.LOGICIN25
P2WRDATA11inputTCELL20:IMUX.LOGICIN57
P2WRDATA12inputTCELL20:IMUX.LOGICIN44
P2WRDATA13inputTCELL20:IMUX.LOGICIN4
P2WRDATA14inputTCELL20:IMUX.LOGICIN55
P2WRDATA15inputTCELL20:IMUX.LOGICIN26
P2WRDATA16inputTCELL20:IMUX.LOGICIN30
P2WRDATA17inputTCELL20:IMUX.LOGICIN10
P2WRDATA18inputTCELL21:IMUX.LOGICIN57
P2WRDATA19inputTCELL21:IMUX.LOGICIN44
P2WRDATA2inputTCELL20:IMUX.LOGICIN7
P2WRDATA20inputTCELL21:IMUX.LOGICIN4
P2WRDATA21inputTCELL21:IMUX.LOGICIN55
P2WRDATA22inputTCELL21:IMUX.LOGICIN26
P2WRDATA23inputTCELL21:IMUX.LOGICIN30
P2WRDATA24inputTCELL21:IMUX.LOGICIN41
P2WRDATA25inputTCELL21:IMUX.LOGICIN10
P2WRDATA26inputTCELL21:IMUX.LOGICIN3
P2WRDATA27inputTCELL21:IMUX.LOGICIN1
P2WRDATA28inputTCELL21:IMUX.LOGICIN19
P2WRDATA29inputTCELL21:IMUX.LOGICIN27
P2WRDATA3inputTCELL20:IMUX.LOGICIN12
P2WRDATA30inputTCELL21:IMUX.LOGICIN29
P2WRDATA31inputTCELL21:IMUX.LOGICIN32
P2WRDATA4inputTCELL20:IMUX.LOGICIN62
P2WRDATA5inputTCELL20:IMUX.LOGICIN20
P2WRDATA6inputTCELL20:IMUX.LOGICIN38
P2WRDATA7inputTCELL20:IMUX.LOGICIN17
P2WRDATA8inputTCELL20:IMUX.LOGICIN23
P2WRDATA9inputTCELL20:IMUX.LOGICIN48
P2WRMASK0inputTCELL21:IMUX.LOGICIN52
P2WRMASK1inputTCELL21:IMUX.LOGICIN2
P2WRMASK2inputTCELL21:IMUX.LOGICIN14
P2WRMASK3inputTCELL21:IMUX.LOGICIN37
P2WRUNDERRUNoutputTCELL21:OUT5
P3ARBENinputTCELL5:IMUX.LOGICIN29
P3CLKinputTCELL23:IMUX.CLK1
P3CMDBA0inputTCELL4:IMUX.LOGICIN7
P3CMDBA1inputTCELL4:IMUX.LOGICIN36
P3CMDBA2inputTCELL4:IMUX.LOGICIN16
P3CMDBL0inputTCELL4:IMUX.LOGICIN57
P3CMDBL1inputTCELL4:IMUX.LOGICIN44
P3CMDBL2inputTCELL4:IMUX.LOGICIN4
P3CMDBL3inputTCELL4:IMUX.LOGICIN55
P3CMDBL4inputTCELL4:IMUX.LOGICIN26
P3CMDBL5inputTCELL4:IMUX.LOGICIN30
P3CMDCA0inputTCELL5:IMUX.LOGICIN7
P3CMDCA1inputTCELL5:IMUX.LOGICIN36
P3CMDCA10inputTCELL5:IMUX.LOGICIN4
P3CMDCA11inputTCELL5:IMUX.LOGICIN55
P3CMDCA2inputTCELL5:IMUX.LOGICIN12
P3CMDCA3inputTCELL5:IMUX.LOGICIN47
P3CMDCA4inputTCELL5:IMUX.LOGICIN45
P3CMDCA5inputTCELL5:IMUX.LOGICIN17
P3CMDCA6inputTCELL5:IMUX.LOGICIN23
P3CMDCA7inputTCELL5:IMUX.LOGICIN25
P3CMDCA8inputTCELL5:IMUX.LOGICIN57
P3CMDCA9inputTCELL5:IMUX.LOGICIN44
P3CMDCLKinputTCELL5:IMUX.CLK1
P3CMDEMPTYoutputTCELL5:OUT6
P3CMDENinputTCELL4:IMUX.LOGICIN47
P3CMDFULLoutputTCELL5:OUT3
P3CMDINSTR0inputTCELL4:IMUX.LOGICIN20
P3CMDINSTR1inputTCELL4:IMUX.LOGICIN17
P3CMDINSTR2inputTCELL4:IMUX.LOGICIN34
P3CMDRA0inputTCELL5:IMUX.LOGICIN26
P3CMDRA1inputTCELL5:IMUX.LOGICIN30
P3CMDRA10inputTCELL5:IMUX.LOGICIN14
P3CMDRA11inputTCELL5:IMUX.LOGICIN37
P3CMDRA12inputTCELL5:IMUX.LOGICIN31
P3CMDRA13inputTCELL4:IMUX.LOGICIN24
P3CMDRA14inputTCELL4:IMUX.LOGICIN15
P3CMDRA2inputTCELL5:IMUX.LOGICIN10
P3CMDRA3inputTCELL5:IMUX.LOGICIN3
P3CMDRA4inputTCELL5:IMUX.LOGICIN1
P3CMDRA5inputTCELL5:IMUX.LOGICIN28
P3CMDRA6inputTCELL5:IMUX.LOGICIN27
P3CMDRA7inputTCELL5:IMUX.LOGICIN32
P3CMDRA8inputTCELL5:IMUX.LOGICIN59
P3CMDRA9inputTCELL5:IMUX.LOGICIN2
P3COUNT0outputTCELL23:OUT12
P3COUNT1outputTCELL23:OUT19
P3COUNT2outputTCELL23:OUT14
P3COUNT3outputTCELL23:OUT2
P3COUNT4outputTCELL22:OUT9
P3COUNT5outputTCELL22:OUT11
P3COUNT6outputTCELL22:OUT23
P3EMPTYoutputTCELL23:OUT0
P3ENinputTCELL23:IMUX.LOGICIN7
P3ERRORoutputTCELL23:OUT7
P3FULLoutputTCELL22:OUT4
P3RDDATA0outputTCELL22:OUT2
P3RDDATA1outputTCELL22:OUT14
P3RDDATA10outputTCELL22:OUT15
P3RDDATA11outputTCELL22:OUT3
P3RDDATA12outputTCELL22:OUT8
P3RDDATA13outputTCELL22:OUT1
P3RDDATA14outputTCELL22:OUT18
P3RDDATA15outputTCELL22:OUT20
P3RDDATA16outputTCELL22:OUT13
P3RDDATA17outputTCELL22:OUT6
P3RDDATA18outputTCELL23:OUT10
P3RDDATA19outputTCELL23:OUT17
P3RDDATA2outputTCELL22:OUT19
P3RDDATA20outputTCELL23:OUT22
P3RDDATA21outputTCELL23:OUT15
P3RDDATA22outputTCELL23:OUT3
P3RDDATA23outputTCELL23:OUT8
P3RDDATA24outputTCELL23:OUT1
P3RDDATA25outputTCELL23:OUT18
P3RDDATA26outputTCELL23:OUT20
P3RDDATA27outputTCELL23:OUT13
P3RDDATA28outputTCELL23:OUT6
P3RDDATA29outputTCELL23:OUT4
P3RDDATA3outputTCELL22:OUT7
P3RDDATA30outputTCELL23:OUT16
P3RDDATA31outputTCELL23:OUT21
P3RDDATA4outputTCELL22:OUT12
P3RDDATA5outputTCELL22:OUT0
P3RDDATA6outputTCELL22:OUT5
P3RDDATA7outputTCELL22:OUT10
P3RDDATA8outputTCELL22:OUT17
P3RDDATA9outputTCELL22:OUT22
P3RDOVERFLOWoutputTCELL22:OUT16
P3TSTENBinputTCELL22:IMUX.LOGICIN9
P3TSTLDMPoutputTCELL22:OUT21
P3TSTMODEB0inputTCELL22:IMUX.LOGICIN32
P3TSTMODEB1inputTCELL22:IMUX.LOGICIN29
P3TSTMODEB2inputTCELL22:IMUX.LOGICIN1
P3TSTMODEB3inputTCELL22:IMUX.LOGICIN19
P3TSTPINENBinputTCELL22:IMUX.LOGICIN59
P3WRDATA0inputTCELL22:IMUX.LOGICIN15
P3WRDATA1inputTCELL22:IMUX.LOGICIN42
P3WRDATA10inputTCELL22:IMUX.LOGICIN25
P3WRDATA11inputTCELL22:IMUX.LOGICIN57
P3WRDATA12inputTCELL22:IMUX.LOGICIN44
P3WRDATA13inputTCELL22:IMUX.LOGICIN4
P3WRDATA14inputTCELL22:IMUX.LOGICIN55
P3WRDATA15inputTCELL22:IMUX.LOGICIN26
P3WRDATA16inputTCELL22:IMUX.LOGICIN30
P3WRDATA17inputTCELL22:IMUX.LOGICIN10
P3WRDATA18inputTCELL23:IMUX.LOGICIN57
P3WRDATA19inputTCELL23:IMUX.LOGICIN44
P3WRDATA2inputTCELL22:IMUX.LOGICIN7
P3WRDATA20inputTCELL23:IMUX.LOGICIN4
P3WRDATA21inputTCELL23:IMUX.LOGICIN55
P3WRDATA22inputTCELL23:IMUX.LOGICIN26
P3WRDATA23inputTCELL23:IMUX.LOGICIN30
P3WRDATA24inputTCELL23:IMUX.LOGICIN41
P3WRDATA25inputTCELL23:IMUX.LOGICIN10
P3WRDATA26inputTCELL23:IMUX.LOGICIN3
P3WRDATA27inputTCELL23:IMUX.LOGICIN1
P3WRDATA28inputTCELL23:IMUX.LOGICIN19
P3WRDATA29inputTCELL23:IMUX.LOGICIN27
P3WRDATA3inputTCELL22:IMUX.LOGICIN12
P3WRDATA30inputTCELL23:IMUX.LOGICIN29
P3WRDATA31inputTCELL23:IMUX.LOGICIN32
P3WRDATA4inputTCELL22:IMUX.LOGICIN62
P3WRDATA5inputTCELL22:IMUX.LOGICIN20
P3WRDATA6inputTCELL22:IMUX.LOGICIN38
P3WRDATA7inputTCELL22:IMUX.LOGICIN17
P3WRDATA8inputTCELL22:IMUX.LOGICIN23
P3WRDATA9inputTCELL22:IMUX.LOGICIN48
P3WRMASK0inputTCELL23:IMUX.LOGICIN52
P3WRMASK1inputTCELL23:IMUX.LOGICIN2
P3WRMASK2inputTCELL23:IMUX.LOGICIN14
P3WRMASK3inputTCELL23:IMUX.LOGICIN37
P3WRUNDERRUNoutputTCELL23:OUT5
P4ARBENinputTCELL3:IMUX.LOGICIN29
P4CLKinputTCELL25:IMUX.CLK1
P4CMDBA0inputTCELL2:IMUX.LOGICIN7
P4CMDBA1inputTCELL2:IMUX.LOGICIN36
P4CMDBA2inputTCELL2:IMUX.LOGICIN16
P4CMDBL0inputTCELL2:IMUX.LOGICIN57
P4CMDBL1inputTCELL2:IMUX.LOGICIN44
P4CMDBL2inputTCELL2:IMUX.LOGICIN4
P4CMDBL3inputTCELL2:IMUX.LOGICIN55
P4CMDBL4inputTCELL2:IMUX.LOGICIN26
P4CMDBL5inputTCELL2:IMUX.LOGICIN30
P4CMDCA0inputTCELL3:IMUX.LOGICIN7
P4CMDCA1inputTCELL3:IMUX.LOGICIN36
P4CMDCA10inputTCELL3:IMUX.LOGICIN4
P4CMDCA11inputTCELL3:IMUX.LOGICIN55
P4CMDCA2inputTCELL3:IMUX.LOGICIN12
P4CMDCA3inputTCELL3:IMUX.LOGICIN47
P4CMDCA4inputTCELL3:IMUX.LOGICIN45
P4CMDCA5inputTCELL3:IMUX.LOGICIN17
P4CMDCA6inputTCELL3:IMUX.LOGICIN23
P4CMDCA7inputTCELL3:IMUX.LOGICIN25
P4CMDCA8inputTCELL3:IMUX.LOGICIN57
P4CMDCA9inputTCELL3:IMUX.LOGICIN44
P4CMDCLKinputTCELL3:IMUX.CLK1
P4CMDEMPTYoutputTCELL3:OUT6
P4CMDENinputTCELL2:IMUX.LOGICIN47
P4CMDFULLoutputTCELL3:OUT3
P4CMDINSTR0inputTCELL2:IMUX.LOGICIN20
P4CMDINSTR1inputTCELL2:IMUX.LOGICIN17
P4CMDINSTR2inputTCELL2:IMUX.LOGICIN34
P4CMDRA0inputTCELL3:IMUX.LOGICIN26
P4CMDRA1inputTCELL3:IMUX.LOGICIN30
P4CMDRA10inputTCELL3:IMUX.LOGICIN14
P4CMDRA11inputTCELL3:IMUX.LOGICIN37
P4CMDRA12inputTCELL3:IMUX.LOGICIN31
P4CMDRA13inputTCELL2:IMUX.LOGICIN24
P4CMDRA14inputTCELL2:IMUX.LOGICIN15
P4CMDRA2inputTCELL3:IMUX.LOGICIN10
P4CMDRA3inputTCELL3:IMUX.LOGICIN3
P4CMDRA4inputTCELL3:IMUX.LOGICIN1
P4CMDRA5inputTCELL3:IMUX.LOGICIN28
P4CMDRA6inputTCELL3:IMUX.LOGICIN27
P4CMDRA7inputTCELL3:IMUX.LOGICIN32
P4CMDRA8inputTCELL3:IMUX.LOGICIN59
P4CMDRA9inputTCELL3:IMUX.LOGICIN2
P4COUNT0outputTCELL25:OUT12
P4COUNT1outputTCELL25:OUT19
P4COUNT2outputTCELL25:OUT14
P4COUNT3outputTCELL25:OUT2
P4COUNT4outputTCELL24:OUT9
P4COUNT5outputTCELL24:OUT11
P4COUNT6outputTCELL24:OUT23
P4EMPTYoutputTCELL25:OUT0
P4ENinputTCELL25:IMUX.LOGICIN7
P4ERRORoutputTCELL25:OUT7
P4FULLoutputTCELL24:OUT4
P4RDDATA0outputTCELL24:OUT2
P4RDDATA1outputTCELL24:OUT14
P4RDDATA10outputTCELL24:OUT15
P4RDDATA11outputTCELL24:OUT3
P4RDDATA12outputTCELL24:OUT8
P4RDDATA13outputTCELL24:OUT1
P4RDDATA14outputTCELL24:OUT18
P4RDDATA15outputTCELL24:OUT20
P4RDDATA16outputTCELL24:OUT13
P4RDDATA17outputTCELL24:OUT6
P4RDDATA18outputTCELL25:OUT10
P4RDDATA19outputTCELL25:OUT17
P4RDDATA2outputTCELL24:OUT19
P4RDDATA20outputTCELL25:OUT22
P4RDDATA21outputTCELL25:OUT15
P4RDDATA22outputTCELL25:OUT3
P4RDDATA23outputTCELL25:OUT8
P4RDDATA24outputTCELL25:OUT1
P4RDDATA25outputTCELL25:OUT18
P4RDDATA26outputTCELL25:OUT20
P4RDDATA27outputTCELL25:OUT13
P4RDDATA28outputTCELL25:OUT6
P4RDDATA29outputTCELL25:OUT4
P4RDDATA3outputTCELL24:OUT7
P4RDDATA30outputTCELL25:OUT16
P4RDDATA31outputTCELL25:OUT21
P4RDDATA4outputTCELL24:OUT12
P4RDDATA5outputTCELL24:OUT0
P4RDDATA6outputTCELL24:OUT5
P4RDDATA7outputTCELL24:OUT10
P4RDDATA8outputTCELL24:OUT17
P4RDDATA9outputTCELL24:OUT22
P4RDOVERFLOWoutputTCELL24:OUT16
P4TSTENBinputTCELL24:IMUX.LOGICIN9
P4TSTMODEB0inputTCELL24:IMUX.LOGICIN32
P4TSTMODEB1inputTCELL24:IMUX.LOGICIN29
P4TSTMODEB2inputTCELL24:IMUX.LOGICIN1
P4TSTMODEB3inputTCELL24:IMUX.LOGICIN19
P4TSTPINENBinputTCELL24:IMUX.LOGICIN59
P4TSTUDMNoutputTCELL24:OUT21
P4WRDATA0inputTCELL24:IMUX.LOGICIN15
P4WRDATA1inputTCELL24:IMUX.LOGICIN42
P4WRDATA10inputTCELL24:IMUX.LOGICIN25
P4WRDATA11inputTCELL24:IMUX.LOGICIN57
P4WRDATA12inputTCELL24:IMUX.LOGICIN44
P4WRDATA13inputTCELL24:IMUX.LOGICIN4
P4WRDATA14inputTCELL24:IMUX.LOGICIN55
P4WRDATA15inputTCELL24:IMUX.LOGICIN26
P4WRDATA16inputTCELL24:IMUX.LOGICIN30
P4WRDATA17inputTCELL24:IMUX.LOGICIN10
P4WRDATA18inputTCELL25:IMUX.LOGICIN57
P4WRDATA19inputTCELL25:IMUX.LOGICIN44
P4WRDATA2inputTCELL24:IMUX.LOGICIN7
P4WRDATA20inputTCELL25:IMUX.LOGICIN4
P4WRDATA21inputTCELL25:IMUX.LOGICIN55
P4WRDATA22inputTCELL25:IMUX.LOGICIN26
P4WRDATA23inputTCELL25:IMUX.LOGICIN30
P4WRDATA24inputTCELL25:IMUX.LOGICIN41
P4WRDATA25inputTCELL25:IMUX.LOGICIN10
P4WRDATA26inputTCELL25:IMUX.LOGICIN3
P4WRDATA27inputTCELL25:IMUX.LOGICIN1
P4WRDATA28inputTCELL25:IMUX.LOGICIN19
P4WRDATA29inputTCELL25:IMUX.LOGICIN27
P4WRDATA3inputTCELL24:IMUX.LOGICIN12
P4WRDATA30inputTCELL25:IMUX.LOGICIN29
P4WRDATA31inputTCELL25:IMUX.LOGICIN32
P4WRDATA4inputTCELL24:IMUX.LOGICIN62
P4WRDATA5inputTCELL24:IMUX.LOGICIN20
P4WRDATA6inputTCELL24:IMUX.LOGICIN38
P4WRDATA7inputTCELL24:IMUX.LOGICIN17
P4WRDATA8inputTCELL24:IMUX.LOGICIN23
P4WRDATA9inputTCELL24:IMUX.LOGICIN48
P4WRMASK0inputTCELL25:IMUX.LOGICIN52
P4WRMASK1inputTCELL25:IMUX.LOGICIN2
P4WRMASK2inputTCELL25:IMUX.LOGICIN14
P4WRMASK3inputTCELL25:IMUX.LOGICIN37
P4WRUNDERRUNoutputTCELL25:OUT5
P5ARBENinputTCELL1:IMUX.LOGICIN29
P5CLKinputTCELL27:IMUX.CLK1
P5CMDBA0inputTCELL0:IMUX.LOGICIN7
P5CMDBA1inputTCELL0:IMUX.LOGICIN36
P5CMDBA2inputTCELL0:IMUX.LOGICIN16
P5CMDBL0inputTCELL0:IMUX.LOGICIN57
P5CMDBL1inputTCELL0:IMUX.LOGICIN44
P5CMDBL2inputTCELL0:IMUX.LOGICIN4
P5CMDBL3inputTCELL0:IMUX.LOGICIN55
P5CMDBL4inputTCELL0:IMUX.LOGICIN26
P5CMDBL5inputTCELL0:IMUX.LOGICIN30
P5CMDCA0inputTCELL1:IMUX.LOGICIN7
P5CMDCA1inputTCELL1:IMUX.LOGICIN36
P5CMDCA10inputTCELL1:IMUX.LOGICIN4
P5CMDCA11inputTCELL1:IMUX.LOGICIN55
P5CMDCA2inputTCELL1:IMUX.LOGICIN12
P5CMDCA3inputTCELL1:IMUX.LOGICIN47
P5CMDCA4inputTCELL1:IMUX.LOGICIN45
P5CMDCA5inputTCELL1:IMUX.LOGICIN17
P5CMDCA6inputTCELL1:IMUX.LOGICIN23
P5CMDCA7inputTCELL1:IMUX.LOGICIN25
P5CMDCA8inputTCELL1:IMUX.LOGICIN57
P5CMDCA9inputTCELL1:IMUX.LOGICIN44
P5CMDCLKinputTCELL1:IMUX.CLK1
P5CMDEMPTYoutputTCELL1:OUT6
P5CMDENinputTCELL0:IMUX.LOGICIN47
P5CMDFULLoutputTCELL1:OUT3
P5CMDINSTR0inputTCELL0:IMUX.LOGICIN20
P5CMDINSTR1inputTCELL0:IMUX.LOGICIN17
P5CMDINSTR2inputTCELL0:IMUX.LOGICIN34
P5CMDRA0inputTCELL1:IMUX.LOGICIN26
P5CMDRA1inputTCELL1:IMUX.LOGICIN30
P5CMDRA10inputTCELL1:IMUX.LOGICIN14
P5CMDRA11inputTCELL1:IMUX.LOGICIN37
P5CMDRA12inputTCELL1:IMUX.LOGICIN31
P5CMDRA13inputTCELL0:IMUX.LOGICIN24
P5CMDRA14inputTCELL0:IMUX.LOGICIN15
P5CMDRA2inputTCELL1:IMUX.LOGICIN10
P5CMDRA3inputTCELL1:IMUX.LOGICIN3
P5CMDRA4inputTCELL1:IMUX.LOGICIN1
P5CMDRA5inputTCELL1:IMUX.LOGICIN28
P5CMDRA6inputTCELL1:IMUX.LOGICIN27
P5CMDRA7inputTCELL1:IMUX.LOGICIN32
P5CMDRA8inputTCELL1:IMUX.LOGICIN59
P5CMDRA9inputTCELL1:IMUX.LOGICIN2
P5COUNT0outputTCELL27:OUT12
P5COUNT1outputTCELL27:OUT19
P5COUNT2outputTCELL27:OUT14
P5COUNT3outputTCELL27:OUT2
P5COUNT4outputTCELL26:OUT9
P5COUNT5outputTCELL26:OUT11
P5COUNT6outputTCELL26:OUT23
P5EMPTYoutputTCELL27:OUT0
P5ENinputTCELL27:IMUX.LOGICIN7
P5ERRORoutputTCELL27:OUT7
P5FULLoutputTCELL26:OUT4
P5RDDATA0outputTCELL26:OUT2
P5RDDATA1outputTCELL26:OUT14
P5RDDATA10outputTCELL26:OUT15
P5RDDATA11outputTCELL26:OUT3
P5RDDATA12outputTCELL26:OUT8
P5RDDATA13outputTCELL26:OUT1
P5RDDATA14outputTCELL26:OUT18
P5RDDATA15outputTCELL26:OUT20
P5RDDATA16outputTCELL26:OUT13
P5RDDATA17outputTCELL26:OUT6
P5RDDATA18outputTCELL27:OUT10
P5RDDATA19outputTCELL27:OUT17
P5RDDATA2outputTCELL26:OUT19
P5RDDATA20outputTCELL27:OUT22
P5RDDATA21outputTCELL27:OUT15
P5RDDATA22outputTCELL27:OUT3
P5RDDATA23outputTCELL27:OUT8
P5RDDATA24outputTCELL27:OUT1
P5RDDATA25outputTCELL27:OUT18
P5RDDATA26outputTCELL27:OUT20
P5RDDATA27outputTCELL27:OUT13
P5RDDATA28outputTCELL27:OUT6
P5RDDATA29outputTCELL27:OUT4
P5RDDATA3outputTCELL26:OUT7
P5RDDATA30outputTCELL27:OUT16
P5RDDATA31outputTCELL27:OUT21
P5RDDATA4outputTCELL26:OUT12
P5RDDATA5outputTCELL26:OUT0
P5RDDATA6outputTCELL26:OUT5
P5RDDATA7outputTCELL26:OUT10
P5RDDATA8outputTCELL26:OUT17
P5RDDATA9outputTCELL26:OUT22
P5RDOVERFLOWoutputTCELL26:OUT16
P5TSTENBinputTCELL26:IMUX.LOGICIN9
P5TSTLDMNoutputTCELL26:OUT21
P5TSTMODEB0inputTCELL26:IMUX.LOGICIN32
P5TSTMODEB1inputTCELL26:IMUX.LOGICIN29
P5TSTMODEB2inputTCELL26:IMUX.LOGICIN1
P5TSTMODEB3inputTCELL26:IMUX.LOGICIN19
P5TSTPINENBinputTCELL26:IMUX.LOGICIN59
P5WRDATA0inputTCELL26:IMUX.LOGICIN15
P5WRDATA1inputTCELL26:IMUX.LOGICIN42
P5WRDATA10inputTCELL26:IMUX.LOGICIN25
P5WRDATA11inputTCELL26:IMUX.LOGICIN57
P5WRDATA12inputTCELL26:IMUX.LOGICIN44
P5WRDATA13inputTCELL26:IMUX.LOGICIN4
P5WRDATA14inputTCELL26:IMUX.LOGICIN55
P5WRDATA15inputTCELL26:IMUX.LOGICIN26
P5WRDATA16inputTCELL26:IMUX.LOGICIN30
P5WRDATA17inputTCELL26:IMUX.LOGICIN10
P5WRDATA18inputTCELL27:IMUX.LOGICIN57
P5WRDATA19inputTCELL27:IMUX.LOGICIN44
P5WRDATA2inputTCELL26:IMUX.LOGICIN7
P5WRDATA20inputTCELL27:IMUX.LOGICIN4
P5WRDATA21inputTCELL27:IMUX.LOGICIN55
P5WRDATA22inputTCELL27:IMUX.LOGICIN26
P5WRDATA23inputTCELL27:IMUX.LOGICIN30
P5WRDATA24inputTCELL27:IMUX.LOGICIN41
P5WRDATA25inputTCELL27:IMUX.LOGICIN10
P5WRDATA26inputTCELL27:IMUX.LOGICIN3
P5WRDATA27inputTCELL27:IMUX.LOGICIN1
P5WRDATA28inputTCELL27:IMUX.LOGICIN19
P5WRDATA29inputTCELL27:IMUX.LOGICIN27
P5WRDATA3inputTCELL26:IMUX.LOGICIN12
P5WRDATA30inputTCELL27:IMUX.LOGICIN29
P5WRDATA31inputTCELL27:IMUX.LOGICIN32
P5WRDATA4inputTCELL26:IMUX.LOGICIN62
P5WRDATA5inputTCELL26:IMUX.LOGICIN20
P5WRDATA6inputTCELL26:IMUX.LOGICIN38
P5WRDATA7inputTCELL26:IMUX.LOGICIN17
P5WRDATA8inputTCELL26:IMUX.LOGICIN23
P5WRDATA9inputTCELL26:IMUX.LOGICIN48
P5WRMASK0inputTCELL27:IMUX.LOGICIN52
P5WRMASK1inputTCELL27:IMUX.LOGICIN2
P5WRMASK2inputTCELL27:IMUX.LOGICIN14
P5WRMASK3inputTCELL27:IMUX.LOGICIN37
P5WRUNDERRUNoutputTCELL27:OUT5
PLLLOCKinputTCELL11:IMUX.LOGICIN24
RECALinputTCELL8:IMUX.LOGICIN14
SELFREFRESHENTERinputTCELL8:IMUX.LOGICIN37
SELFREFRESHMODEoutputTCELL8:OUT11
STATUS0outputTCELL4:OUT2
STATUS1outputTCELL4:OUT19
STATUS10outputTCELL4:OUT16
STATUS11outputTCELL4:OUT23
STATUS12outputTCELL4:OUT11
STATUS13outputTCELL3:OUT2
STATUS14outputTCELL3:OUT19
STATUS15outputTCELL3:OUT7
STATUS16outputTCELL3:OUT12
STATUS17outputTCELL3:OUT5
STATUS18outputTCELL3:OUT10
STATUS19outputTCELL3:OUT17
STATUS2outputTCELL4:OUT7
STATUS20outputTCELL3:OUT22
STATUS21outputTCELL3:OUT15
STATUS22outputTCELL3:OUT13
STATUS23outputTCELL3:OUT16
STATUS24outputTCELL3:OUT23
STATUS25outputTCELL3:OUT11
STATUS26outputTCELL2:OUT2
STATUS27outputTCELL2:OUT19
STATUS28outputTCELL2:OUT7
STATUS29outputTCELL2:OUT12
STATUS3outputTCELL4:OUT12
STATUS30outputTCELL2:OUT5
STATUS31outputTCELL2:OUT10
STATUS4outputTCELL4:OUT5
STATUS5outputTCELL4:OUT10
STATUS6outputTCELL4:OUT17
STATUS7outputTCELL4:OUT22
STATUS8outputTCELL4:OUT15
STATUS9outputTCELL4:OUT13
SYSRSTinputTCELL11:IMUX.SR0
TSTCMDOUT0outputTCELL7:OUT2
TSTCMDOUT1outputTCELL7:OUT19
TSTCMDOUT10outputTCELL7:OUT16
TSTCMDOUT11outputTCELL7:OUT23
TSTCMDOUT12outputTCELL7:OUT11
TSTCMDOUT13outputTCELL6:OUT2
TSTCMDOUT14outputTCELL6:OUT19
TSTCMDOUT15outputTCELL6:OUT7
TSTCMDOUT16outputTCELL6:OUT12
TSTCMDOUT17outputTCELL6:OUT5
TSTCMDOUT18outputTCELL6:OUT10
TSTCMDOUT19outputTCELL6:OUT17
TSTCMDOUT2outputTCELL7:OUT7
TSTCMDOUT20outputTCELL6:OUT22
TSTCMDOUT21outputTCELL6:OUT15
TSTCMDOUT22outputTCELL6:OUT13
TSTCMDOUT23outputTCELL6:OUT16
TSTCMDOUT24outputTCELL6:OUT23
TSTCMDOUT25outputTCELL6:OUT11
TSTCMDOUT26outputTCELL5:OUT2
TSTCMDOUT27outputTCELL5:OUT19
TSTCMDOUT28outputTCELL5:OUT7
TSTCMDOUT29outputTCELL5:OUT12
TSTCMDOUT3outputTCELL7:OUT12
TSTCMDOUT30outputTCELL5:OUT5
TSTCMDOUT31outputTCELL5:OUT10
TSTCMDOUT32outputTCELL5:OUT17
TSTCMDOUT33outputTCELL5:OUT22
TSTCMDOUT34outputTCELL5:OUT15
TSTCMDOUT35outputTCELL5:OUT13
TSTCMDOUT36outputTCELL5:OUT16
TSTCMDOUT37outputTCELL5:OUT23
TSTCMDOUT38outputTCELL5:OUT11
TSTCMDOUT4outputTCELL7:OUT5
TSTCMDOUT5outputTCELL7:OUT10
TSTCMDOUT6outputTCELL7:OUT17
TSTCMDOUT7outputTCELL7:OUT22
TSTCMDOUT8outputTCELL7:OUT15
TSTCMDOUT9outputTCELL7:OUT13
TSTCMDTESTENBinputTCELL6:IMUX.LOGICIN3
TSTINB0inputTCELL4:IMUX.LOGICIN48
TSTINB1inputTCELL4:IMUX.LOGICIN58
TSTINB10inputTCELL3:IMUX.LOGICIN19
TSTINB11inputTCELL3:IMUX.LOGICIN41
TSTINB12inputTCELL3:IMUX.LOGICIN52
TSTINB13inputTCELL3:IMUX.LOGICIN9
TSTINB14inputTCELL3:IMUX.LOGICIN39
TSTINB15inputTCELL3:IMUX.LOGICIN8
TSTINB2inputTCELL4:IMUX.LOGICIN19
TSTINB3inputTCELL4:IMUX.LOGICIN41
TSTINB4inputTCELL4:IMUX.LOGICIN52
TSTINB5inputTCELL4:IMUX.LOGICIN9
TSTINB6inputTCELL4:IMUX.LOGICIN39
TSTINB7inputTCELL4:IMUX.LOGICIN8
TSTINB8inputTCELL3:IMUX.LOGICIN48
TSTINB9inputTCELL3:IMUX.LOGICIN58
TSTSCANCLKinputTCELL0:IMUX.LOGICIN10
TSTSCANENBinputTCELL0:IMUX.LOGICIN3
TSTSCANINinputTCELL0:IMUX.LOGICIN14
TSTSCANMODEinputTCELL0:IMUX.LOGICIN37
TSTSCANOUToutputTCELL0:OUT11
TSTSCANRSTinputTCELL0:IMUX.LOGICIN59
TSTSCANSETinputTCELL0:IMUX.LOGICIN9
TSTSEL0inputTCELL6:IMUX.LOGICIN10
TSTSEL1inputTCELL6:IMUX.LOGICIN58
TSTSEL2inputTCELL6:IMUX.LOGICIN19
TSTSEL3inputTCELL6:IMUX.LOGICIN32
TSTSEL4inputTCELL6:IMUX.LOGICIN9
TSTSEL5inputTCELL6:IMUX.LOGICIN2
TSTSEL6inputTCELL6:IMUX.LOGICIN14
TSTSEL7inputTCELL6:IMUX.LOGICIN31
UIADDinputTCELL10:IMUX.LOGICIN3
UIADDR0inputTCELL10:IMUX.LOGICIN1
UIADDR1inputTCELL10:IMUX.LOGICIN19
UIADDR2inputTCELL10:IMUX.LOGICIN27
UIADDR3inputTCELL10:IMUX.LOGICIN29
UIADDR4inputTCELL10:IMUX.LOGICIN59
UIBROADCASTinputTCELL10:IMUX.LOGICIN14
UICLKinputTCELL10:IMUX.CLK0
UICMDinputTCELL8:IMUX.LOGICIN27
UICMDENinputTCELL8:IMUX.LOGICIN9
UICMDINinputTCELL8:IMUX.LOGICIN52
UICSinputTCELL10:IMUX.LOGICIN10
UIDONECALinputTCELL8:IMUX.LOGICIN2
UIDQCOUNT0inputTCELL8:IMUX.LOGICIN10
UIDQCOUNT1inputTCELL8:IMUX.LOGICIN3
UIDQCOUNT2inputTCELL8:IMUX.LOGICIN1
UIDQCOUNT3inputTCELL8:IMUX.LOGICIN19
UIDQLOWERDECinputTCELL2:IMUX.LOGICIN41
UIDQLOWERINCinputTCELL8:IMUX.LOGICIN31
UIDQUPPERDECinputTCELL2:IMUX.LOGICIN27
UIDQUPPERINCinputTCELL2:IMUX.LOGICIN3
UIDRPUPDATEinputTCELL10:IMUX.LOGICIN37
UILDQSDECinputTCELL8:IMUX.LOGICIN29
UILDQSINCinputTCELL8:IMUX.LOGICIN59
UIREADinputTCELL10:IMUX.LOGICIN2
UISDIinputTCELL10:IMUX.LOGICIN9
UIUDQSDECinputTCELL2:IMUX.LOGICIN14
UIUDQSINCinputTCELL2:IMUX.LOGICIN32
UOCALSTARToutputTCELL10:OUT2
UOCMDREADYINoutputTCELL10:OUT7
UODATA0outputTCELL9:OUT7
UODATA1outputTCELL9:OUT0
UODATA2outputTCELL9:OUT10
UODATA3outputTCELL9:OUT22
UODATA4outputTCELL9:OUT8
UODATA5outputTCELL9:OUT20
UODATA6outputTCELL9:OUT16
UODATA7outputTCELL9:OUT11
UODATAVALIDoutputTCELL10:OUT22
UODONECALoutputTCELL10:OUT5
UOREFRSHFLAGoutputTCELL8:OUT19
UOSDOoutputTCELL10:OUT16

Bel MCB_TIE_CLK

spartan6 MCB bel MCB_TIE_CLK
PinDirectionWires

Bel MCB_TIE_DQS0

spartan6 MCB bel MCB_TIE_DQS0
PinDirectionWires

Bel MCB_TIE_DQS1

spartan6 MCB bel MCB_TIE_DQS1
PinDirectionWires

Bel TIEOFF_CLK

spartan6 MCB bel TIEOFF_CLK
PinDirectionWires

Bel TIEOFF_DQS0

spartan6 MCB bel TIEOFF_DQS0
PinDirectionWires

Bel TIEOFF_DQS1

spartan6 MCB bel TIEOFF_DQS1
PinDirectionWires

Bel wires

spartan6 MCB bel wires
WirePins
TCELL0:IMUX.LOGICIN3MCB.TSTSCANENB
TCELL0:IMUX.LOGICIN4MCB.P5CMDBL2
TCELL0:IMUX.LOGICIN7MCB.P5CMDBA0
TCELL0:IMUX.LOGICIN9MCB.TSTSCANSET
TCELL0:IMUX.LOGICIN10MCB.TSTSCANCLK
TCELL0:IMUX.LOGICIN14MCB.TSTSCANIN
TCELL0:IMUX.LOGICIN15MCB.P5CMDRA14
TCELL0:IMUX.LOGICIN16MCB.P5CMDBA2
TCELL0:IMUX.LOGICIN17MCB.P5CMDINSTR1
TCELL0:IMUX.LOGICIN20MCB.P5CMDINSTR0
TCELL0:IMUX.LOGICIN24MCB.P5CMDRA13
TCELL0:IMUX.LOGICIN26MCB.P5CMDBL4
TCELL0:IMUX.LOGICIN30MCB.P5CMDBL5
TCELL0:IMUX.LOGICIN34MCB.P5CMDINSTR2
TCELL0:IMUX.LOGICIN36MCB.P5CMDBA1
TCELL0:IMUX.LOGICIN37MCB.TSTSCANMODE
TCELL0:IMUX.LOGICIN44MCB.P5CMDBL1
TCELL0:IMUX.LOGICIN47MCB.P5CMDEN
TCELL0:IMUX.LOGICIN55MCB.P5CMDBL3
TCELL0:IMUX.LOGICIN57MCB.P5CMDBL0
TCELL0:IMUX.LOGICIN59MCB.TSTSCANRST
TCELL0:OUT11MCB.TSTSCANOUT
TCELL1:IMUX.CLK1MCB.P5CMDCLK
TCELL1:IMUX.LOGICIN1MCB.P5CMDRA4
TCELL1:IMUX.LOGICIN2MCB.P5CMDRA9
TCELL1:IMUX.LOGICIN3MCB.P5CMDRA3
TCELL1:IMUX.LOGICIN4MCB.P5CMDCA10
TCELL1:IMUX.LOGICIN7MCB.P5CMDCA0
TCELL1:IMUX.LOGICIN10MCB.P5CMDRA2
TCELL1:IMUX.LOGICIN12MCB.P5CMDCA2
TCELL1:IMUX.LOGICIN14MCB.P5CMDRA10
TCELL1:IMUX.LOGICIN17MCB.P5CMDCA5
TCELL1:IMUX.LOGICIN23MCB.P5CMDCA6
TCELL1:IMUX.LOGICIN25MCB.P5CMDCA7
TCELL1:IMUX.LOGICIN26MCB.P5CMDRA0
TCELL1:IMUX.LOGICIN27MCB.P5CMDRA6
TCELL1:IMUX.LOGICIN28MCB.P5CMDRA5
TCELL1:IMUX.LOGICIN29MCB.P5ARBEN
TCELL1:IMUX.LOGICIN30MCB.P5CMDRA1
TCELL1:IMUX.LOGICIN31MCB.P5CMDRA12
TCELL1:IMUX.LOGICIN32MCB.P5CMDRA7
TCELL1:IMUX.LOGICIN36MCB.P5CMDCA1
TCELL1:IMUX.LOGICIN37MCB.P5CMDRA11
TCELL1:IMUX.LOGICIN44MCB.P5CMDCA9
TCELL1:IMUX.LOGICIN45MCB.P5CMDCA4
TCELL1:IMUX.LOGICIN47MCB.P5CMDCA3
TCELL1:IMUX.LOGICIN55MCB.P5CMDCA11
TCELL1:IMUX.LOGICIN57MCB.P5CMDCA8
TCELL1:IMUX.LOGICIN59MCB.P5CMDRA8
TCELL1:OUT3MCB.P5CMDFULL
TCELL1:OUT6MCB.P5CMDEMPTY
TCELL2:IMUX.LOGICIN3MCB.UIDQUPPERINC
TCELL2:IMUX.LOGICIN4MCB.P4CMDBL2
TCELL2:IMUX.LOGICIN7MCB.P4CMDBA0
TCELL2:IMUX.LOGICIN14MCB.UIUDQSDEC
TCELL2:IMUX.LOGICIN15MCB.P4CMDRA14
TCELL2:IMUX.LOGICIN16MCB.P4CMDBA2
TCELL2:IMUX.LOGICIN17MCB.P4CMDINSTR1
TCELL2:IMUX.LOGICIN20MCB.P4CMDINSTR0
TCELL2:IMUX.LOGICIN24MCB.P4CMDRA13
TCELL2:IMUX.LOGICIN26MCB.P4CMDBL4
TCELL2:IMUX.LOGICIN27MCB.UIDQUPPERDEC
TCELL2:IMUX.LOGICIN30MCB.P4CMDBL5
TCELL2:IMUX.LOGICIN32MCB.UIUDQSINC
TCELL2:IMUX.LOGICIN34MCB.P4CMDINSTR2
TCELL2:IMUX.LOGICIN36MCB.P4CMDBA1
TCELL2:IMUX.LOGICIN41MCB.UIDQLOWERDEC
TCELL2:IMUX.LOGICIN44MCB.P4CMDBL1
TCELL2:IMUX.LOGICIN47MCB.P4CMDEN
TCELL2:IMUX.LOGICIN55MCB.P4CMDBL3
TCELL2:IMUX.LOGICIN57MCB.P4CMDBL0
TCELL2:OUT2MCB.STATUS26
TCELL2:OUT5MCB.STATUS30
TCELL2:OUT7MCB.STATUS28
TCELL2:OUT10MCB.STATUS31
TCELL2:OUT12MCB.STATUS29
TCELL2:OUT19MCB.STATUS27
TCELL3:IMUX.CLK1MCB.P4CMDCLK
TCELL3:IMUX.LOGICIN1MCB.P4CMDRA4
TCELL3:IMUX.LOGICIN2MCB.P4CMDRA9
TCELL3:IMUX.LOGICIN3MCB.P4CMDRA3
TCELL3:IMUX.LOGICIN4MCB.P4CMDCA10
TCELL3:IMUX.LOGICIN7MCB.P4CMDCA0
TCELL3:IMUX.LOGICIN8MCB.TSTINB15
TCELL3:IMUX.LOGICIN9MCB.TSTINB13
TCELL3:IMUX.LOGICIN10MCB.P4CMDRA2
TCELL3:IMUX.LOGICIN12MCB.P4CMDCA2
TCELL3:IMUX.LOGICIN14MCB.P4CMDRA10
TCELL3:IMUX.LOGICIN17MCB.P4CMDCA5
TCELL3:IMUX.LOGICIN19MCB.TSTINB10
TCELL3:IMUX.LOGICIN23MCB.P4CMDCA6
TCELL3:IMUX.LOGICIN25MCB.P4CMDCA7
TCELL3:IMUX.LOGICIN26MCB.P4CMDRA0
TCELL3:IMUX.LOGICIN27MCB.P4CMDRA6
TCELL3:IMUX.LOGICIN28MCB.P4CMDRA5
TCELL3:IMUX.LOGICIN29MCB.P4ARBEN
TCELL3:IMUX.LOGICIN30MCB.P4CMDRA1
TCELL3:IMUX.LOGICIN31MCB.P4CMDRA12
TCELL3:IMUX.LOGICIN32MCB.P4CMDRA7
TCELL3:IMUX.LOGICIN36MCB.P4CMDCA1
TCELL3:IMUX.LOGICIN37MCB.P4CMDRA11
TCELL3:IMUX.LOGICIN39MCB.TSTINB14
TCELL3:IMUX.LOGICIN41MCB.TSTINB11
TCELL3:IMUX.LOGICIN44MCB.P4CMDCA9
TCELL3:IMUX.LOGICIN45MCB.P4CMDCA4
TCELL3:IMUX.LOGICIN47MCB.P4CMDCA3
TCELL3:IMUX.LOGICIN48MCB.TSTINB8
TCELL3:IMUX.LOGICIN52MCB.TSTINB12
TCELL3:IMUX.LOGICIN55MCB.P4CMDCA11
TCELL3:IMUX.LOGICIN57MCB.P4CMDCA8
TCELL3:IMUX.LOGICIN58MCB.TSTINB9
TCELL3:IMUX.LOGICIN59MCB.P4CMDRA8
TCELL3:OUT2MCB.STATUS13
TCELL3:OUT3MCB.P4CMDFULL
TCELL3:OUT5MCB.STATUS17
TCELL3:OUT6MCB.P4CMDEMPTY
TCELL3:OUT7MCB.STATUS15
TCELL3:OUT10MCB.STATUS18
TCELL3:OUT11MCB.STATUS25
TCELL3:OUT12MCB.STATUS16
TCELL3:OUT13MCB.STATUS22
TCELL3:OUT15MCB.STATUS21
TCELL3:OUT16MCB.STATUS23
TCELL3:OUT17MCB.STATUS19
TCELL3:OUT19MCB.STATUS14
TCELL3:OUT22MCB.STATUS20
TCELL3:OUT23MCB.STATUS24
TCELL4:IMUX.LOGICIN4MCB.P3CMDBL2
TCELL4:IMUX.LOGICIN7MCB.P3CMDBA0
TCELL4:IMUX.LOGICIN8MCB.TSTINB7
TCELL4:IMUX.LOGICIN9MCB.TSTINB5
TCELL4:IMUX.LOGICIN15MCB.P3CMDRA14
TCELL4:IMUX.LOGICIN16MCB.P3CMDBA2
TCELL4:IMUX.LOGICIN17MCB.P3CMDINSTR1
TCELL4:IMUX.LOGICIN19MCB.TSTINB2
TCELL4:IMUX.LOGICIN20MCB.P3CMDINSTR0
TCELL4:IMUX.LOGICIN24MCB.P3CMDRA13
TCELL4:IMUX.LOGICIN26MCB.P3CMDBL4
TCELL4:IMUX.LOGICIN30MCB.P3CMDBL5
TCELL4:IMUX.LOGICIN34MCB.P3CMDINSTR2
TCELL4:IMUX.LOGICIN36MCB.P3CMDBA1
TCELL4:IMUX.LOGICIN39MCB.TSTINB6
TCELL4:IMUX.LOGICIN41MCB.TSTINB3
TCELL4:IMUX.LOGICIN44MCB.P3CMDBL1
TCELL4:IMUX.LOGICIN47MCB.P3CMDEN
TCELL4:IMUX.LOGICIN48MCB.TSTINB0
TCELL4:IMUX.LOGICIN52MCB.TSTINB4
TCELL4:IMUX.LOGICIN55MCB.P3CMDBL3
TCELL4:IMUX.LOGICIN57MCB.P3CMDBL0
TCELL4:IMUX.LOGICIN58MCB.TSTINB1
TCELL4:OUT2MCB.STATUS0
TCELL4:OUT5MCB.STATUS4
TCELL4:OUT7MCB.STATUS2
TCELL4:OUT10MCB.STATUS5
TCELL4:OUT11MCB.STATUS12
TCELL4:OUT12MCB.STATUS3
TCELL4:OUT13MCB.STATUS9
TCELL4:OUT15MCB.STATUS8
TCELL4:OUT16MCB.STATUS10
TCELL4:OUT17MCB.STATUS6
TCELL4:OUT19MCB.STATUS1
TCELL4:OUT22MCB.STATUS7
TCELL4:OUT23MCB.STATUS11
TCELL5:IMUX.CLK1MCB.P3CMDCLK
TCELL5:IMUX.LOGICIN1MCB.P3CMDRA4
TCELL5:IMUX.LOGICIN2MCB.P3CMDRA9
TCELL5:IMUX.LOGICIN3MCB.P3CMDRA3
TCELL5:IMUX.LOGICIN4MCB.P3CMDCA10
TCELL5:IMUX.LOGICIN7MCB.P3CMDCA0
TCELL5:IMUX.LOGICIN10MCB.P3CMDRA2
TCELL5:IMUX.LOGICIN12MCB.P3CMDCA2
TCELL5:IMUX.LOGICIN14MCB.P3CMDRA10
TCELL5:IMUX.LOGICIN17MCB.P3CMDCA5
TCELL5:IMUX.LOGICIN23MCB.P3CMDCA6
TCELL5:IMUX.LOGICIN25MCB.P3CMDCA7
TCELL5:IMUX.LOGICIN26MCB.P3CMDRA0
TCELL5:IMUX.LOGICIN27MCB.P3CMDRA6
TCELL5:IMUX.LOGICIN28MCB.P3CMDRA5
TCELL5:IMUX.LOGICIN29MCB.P3ARBEN
TCELL5:IMUX.LOGICIN30MCB.P3CMDRA1
TCELL5:IMUX.LOGICIN31MCB.P3CMDRA12
TCELL5:IMUX.LOGICIN32MCB.P3CMDRA7
TCELL5:IMUX.LOGICIN36MCB.P3CMDCA1
TCELL5:IMUX.LOGICIN37MCB.P3CMDRA11
TCELL5:IMUX.LOGICIN44MCB.P3CMDCA9
TCELL5:IMUX.LOGICIN45MCB.P3CMDCA4
TCELL5:IMUX.LOGICIN47MCB.P3CMDCA3
TCELL5:IMUX.LOGICIN55MCB.P3CMDCA11
TCELL5:IMUX.LOGICIN57MCB.P3CMDCA8
TCELL5:IMUX.LOGICIN59MCB.P3CMDRA8
TCELL5:OUT2MCB.TSTCMDOUT26
TCELL5:OUT3MCB.P3CMDFULL
TCELL5:OUT5MCB.TSTCMDOUT30
TCELL5:OUT6MCB.P3CMDEMPTY
TCELL5:OUT7MCB.TSTCMDOUT28
TCELL5:OUT10MCB.TSTCMDOUT31
TCELL5:OUT11MCB.TSTCMDOUT38
TCELL5:OUT12MCB.TSTCMDOUT29
TCELL5:OUT13MCB.TSTCMDOUT35
TCELL5:OUT15MCB.TSTCMDOUT34
TCELL5:OUT16MCB.TSTCMDOUT36
TCELL5:OUT17MCB.TSTCMDOUT32
TCELL5:OUT19MCB.TSTCMDOUT27
TCELL5:OUT22MCB.TSTCMDOUT33
TCELL5:OUT23MCB.TSTCMDOUT37
TCELL6:IMUX.LOGICIN2MCB.TSTSEL5
TCELL6:IMUX.LOGICIN3MCB.TSTCMDTESTENB
TCELL6:IMUX.LOGICIN4MCB.P2CMDBL2
TCELL6:IMUX.LOGICIN7MCB.P2CMDBA0
TCELL6:IMUX.LOGICIN9MCB.TSTSEL4
TCELL6:IMUX.LOGICIN10MCB.TSTSEL0
TCELL6:IMUX.LOGICIN14MCB.TSTSEL6
TCELL6:IMUX.LOGICIN15MCB.P2CMDRA14
TCELL6:IMUX.LOGICIN16MCB.P2CMDBA2
TCELL6:IMUX.LOGICIN17MCB.P2CMDINSTR1
TCELL6:IMUX.LOGICIN19MCB.TSTSEL2
TCELL6:IMUX.LOGICIN20MCB.P2CMDINSTR0
TCELL6:IMUX.LOGICIN24MCB.P2CMDRA13
TCELL6:IMUX.LOGICIN26MCB.P2CMDBL4
TCELL6:IMUX.LOGICIN30MCB.P2CMDBL5
TCELL6:IMUX.LOGICIN31MCB.TSTSEL7
TCELL6:IMUX.LOGICIN32MCB.TSTSEL3
TCELL6:IMUX.LOGICIN34MCB.P2CMDINSTR2
TCELL6:IMUX.LOGICIN36MCB.P2CMDBA1
TCELL6:IMUX.LOGICIN44MCB.P2CMDBL1
TCELL6:IMUX.LOGICIN47MCB.P2CMDEN
TCELL6:IMUX.LOGICIN55MCB.P2CMDBL3
TCELL6:IMUX.LOGICIN57MCB.P2CMDBL0
TCELL6:IMUX.LOGICIN58MCB.TSTSEL1
TCELL6:OUT2MCB.TSTCMDOUT13
TCELL6:OUT5MCB.TSTCMDOUT17
TCELL6:OUT7MCB.TSTCMDOUT15
TCELL6:OUT10MCB.TSTCMDOUT18
TCELL6:OUT11MCB.TSTCMDOUT25
TCELL6:OUT12MCB.TSTCMDOUT16
TCELL6:OUT13MCB.TSTCMDOUT22
TCELL6:OUT15MCB.TSTCMDOUT21
TCELL6:OUT16MCB.TSTCMDOUT23
TCELL6:OUT17MCB.TSTCMDOUT19
TCELL6:OUT19MCB.TSTCMDOUT14
TCELL6:OUT22MCB.TSTCMDOUT20
TCELL6:OUT23MCB.TSTCMDOUT24
TCELL7:IMUX.CLK1MCB.P2CMDCLK
TCELL7:IMUX.LOGICIN1MCB.P2CMDRA4
TCELL7:IMUX.LOGICIN2MCB.P2CMDRA9
TCELL7:IMUX.LOGICIN3MCB.P2CMDRA3
TCELL7:IMUX.LOGICIN4MCB.P2CMDCA10
TCELL7:IMUX.LOGICIN7MCB.P2CMDCA0
TCELL7:IMUX.LOGICIN10MCB.P2CMDRA2
TCELL7:IMUX.LOGICIN12MCB.P2CMDCA2
TCELL7:IMUX.LOGICIN14MCB.P2CMDRA10
TCELL7:IMUX.LOGICIN17MCB.P2CMDCA5
TCELL7:IMUX.LOGICIN23MCB.P2CMDCA6
TCELL7:IMUX.LOGICIN25MCB.P2CMDCA7
TCELL7:IMUX.LOGICIN26MCB.P2CMDRA0
TCELL7:IMUX.LOGICIN27MCB.P2CMDRA6
TCELL7:IMUX.LOGICIN28MCB.P2CMDRA5
TCELL7:IMUX.LOGICIN29MCB.P2ARBEN
TCELL7:IMUX.LOGICIN30MCB.P2CMDRA1
TCELL7:IMUX.LOGICIN31MCB.P2CMDRA12
TCELL7:IMUX.LOGICIN32MCB.P2CMDRA7
TCELL7:IMUX.LOGICIN36MCB.P2CMDCA1
TCELL7:IMUX.LOGICIN37MCB.P2CMDRA11
TCELL7:IMUX.LOGICIN44MCB.P2CMDCA9
TCELL7:IMUX.LOGICIN45MCB.P2CMDCA4
TCELL7:IMUX.LOGICIN47MCB.P2CMDCA3
TCELL7:IMUX.LOGICIN55MCB.P2CMDCA11
TCELL7:IMUX.LOGICIN57MCB.P2CMDCA8
TCELL7:IMUX.LOGICIN59MCB.P2CMDRA8
TCELL7:OUT2MCB.TSTCMDOUT0
TCELL7:OUT3MCB.P2CMDFULL
TCELL7:OUT5MCB.TSTCMDOUT4
TCELL7:OUT6MCB.P2CMDEMPTY
TCELL7:OUT7MCB.TSTCMDOUT2
TCELL7:OUT10MCB.TSTCMDOUT5
TCELL7:OUT11MCB.TSTCMDOUT12
TCELL7:OUT12MCB.TSTCMDOUT3
TCELL7:OUT13MCB.TSTCMDOUT9
TCELL7:OUT15MCB.TSTCMDOUT8
TCELL7:OUT16MCB.TSTCMDOUT10
TCELL7:OUT17MCB.TSTCMDOUT6
TCELL7:OUT19MCB.TSTCMDOUT1
TCELL7:OUT22MCB.TSTCMDOUT7
TCELL7:OUT23MCB.TSTCMDOUT11
TCELL8:IMUX.LOGICIN1MCB.UIDQCOUNT2
TCELL8:IMUX.LOGICIN2MCB.UIDONECAL
TCELL8:IMUX.LOGICIN3MCB.UIDQCOUNT1
TCELL8:IMUX.LOGICIN4MCB.P1CMDBL2
TCELL8:IMUX.LOGICIN7MCB.P1CMDBA0
TCELL8:IMUX.LOGICIN9MCB.UICMDEN
TCELL8:IMUX.LOGICIN10MCB.UIDQCOUNT0
TCELL8:IMUX.LOGICIN14MCB.RECAL
TCELL8:IMUX.LOGICIN15MCB.P1CMDRA14
TCELL8:IMUX.LOGICIN16MCB.P1CMDBA2
TCELL8:IMUX.LOGICIN17MCB.P1CMDINSTR1
TCELL8:IMUX.LOGICIN19MCB.UIDQCOUNT3
TCELL8:IMUX.LOGICIN20MCB.P1CMDINSTR0
TCELL8:IMUX.LOGICIN24MCB.P1CMDRA13
TCELL8:IMUX.LOGICIN26MCB.P1CMDBL4
TCELL8:IMUX.LOGICIN27MCB.UICMD
TCELL8:IMUX.LOGICIN29MCB.UILDQSDEC
TCELL8:IMUX.LOGICIN30MCB.P1CMDBL5
TCELL8:IMUX.LOGICIN31MCB.UIDQLOWERINC
TCELL8:IMUX.LOGICIN34MCB.P1CMDINSTR2
TCELL8:IMUX.LOGICIN36MCB.P1CMDBA1
TCELL8:IMUX.LOGICIN37MCB.SELFREFRESHENTER
TCELL8:IMUX.LOGICIN44MCB.P1CMDBL1
TCELL8:IMUX.LOGICIN47MCB.P1CMDEN
TCELL8:IMUX.LOGICIN52MCB.UICMDIN
TCELL8:IMUX.LOGICIN55MCB.P1CMDBL3
TCELL8:IMUX.LOGICIN57MCB.P1CMDBL0
TCELL8:IMUX.LOGICIN59MCB.UILDQSINC
TCELL8:OUT11MCB.SELFREFRESHMODE
TCELL8:OUT19MCB.UOREFRSHFLAG
TCELL9:IMUX.CLK1MCB.P1CMDCLK
TCELL9:IMUX.LOGICIN1MCB.P1CMDRA4
TCELL9:IMUX.LOGICIN2MCB.P1CMDRA9
TCELL9:IMUX.LOGICIN3MCB.P1CMDRA3
TCELL9:IMUX.LOGICIN4MCB.P1CMDCA10
TCELL9:IMUX.LOGICIN7MCB.P1CMDCA0
TCELL9:IMUX.LOGICIN10MCB.P1CMDRA2
TCELL9:IMUX.LOGICIN12MCB.P1CMDCA2
TCELL9:IMUX.LOGICIN14MCB.P1CMDRA10
TCELL9:IMUX.LOGICIN17MCB.P1CMDCA5
TCELL9:IMUX.LOGICIN23MCB.P1CMDCA6
TCELL9:IMUX.LOGICIN25MCB.P1CMDCA7
TCELL9:IMUX.LOGICIN26MCB.P1CMDRA0
TCELL9:IMUX.LOGICIN27MCB.P1CMDRA6
TCELL9:IMUX.LOGICIN28MCB.P1CMDRA5
TCELL9:IMUX.LOGICIN29MCB.P1ARBEN
TCELL9:IMUX.LOGICIN30MCB.P1CMDRA1
TCELL9:IMUX.LOGICIN31MCB.P1CMDRA12
TCELL9:IMUX.LOGICIN32MCB.P1CMDRA7
TCELL9:IMUX.LOGICIN36MCB.P1CMDCA1
TCELL9:IMUX.LOGICIN37MCB.P1CMDRA11
TCELL9:IMUX.LOGICIN44MCB.P1CMDCA9
TCELL9:IMUX.LOGICIN45MCB.P1CMDCA4
TCELL9:IMUX.LOGICIN47MCB.P1CMDCA3
TCELL9:IMUX.LOGICIN55MCB.P1CMDCA11
TCELL9:IMUX.LOGICIN57MCB.P1CMDCA8
TCELL9:IMUX.LOGICIN59MCB.P1CMDRA8
TCELL9:OUT0MCB.UODATA1
TCELL9:OUT3MCB.P1CMDFULL
TCELL9:OUT6MCB.P1CMDEMPTY
TCELL9:OUT7MCB.UODATA0
TCELL9:OUT8MCB.UODATA4
TCELL9:OUT10MCB.UODATA2
TCELL9:OUT11MCB.UODATA7
TCELL9:OUT16MCB.UODATA6
TCELL9:OUT20MCB.UODATA5
TCELL9:OUT22MCB.UODATA3
TCELL10:IMUX.CLK0MCB.UICLK
TCELL10:IMUX.LOGICIN1MCB.UIADDR0
TCELL10:IMUX.LOGICIN2MCB.UIREAD
TCELL10:IMUX.LOGICIN3MCB.UIADD
TCELL10:IMUX.LOGICIN4MCB.P0CMDBL2
TCELL10:IMUX.LOGICIN7MCB.P0CMDBA0
TCELL10:IMUX.LOGICIN9MCB.UISDI
TCELL10:IMUX.LOGICIN10MCB.UICS
TCELL10:IMUX.LOGICIN14MCB.UIBROADCAST
TCELL10:IMUX.LOGICIN15MCB.P0CMDRA14
TCELL10:IMUX.LOGICIN16MCB.P0CMDBA2
TCELL10:IMUX.LOGICIN17MCB.P0CMDINSTR1
TCELL10:IMUX.LOGICIN19MCB.UIADDR1
TCELL10:IMUX.LOGICIN20MCB.P0CMDINSTR0
TCELL10:IMUX.LOGICIN24MCB.P0CMDRA13
TCELL10:IMUX.LOGICIN26MCB.P0CMDBL4
TCELL10:IMUX.LOGICIN27MCB.UIADDR2
TCELL10:IMUX.LOGICIN29MCB.UIADDR3
TCELL10:IMUX.LOGICIN30MCB.P0CMDBL5
TCELL10:IMUX.LOGICIN34MCB.P0CMDINSTR2
TCELL10:IMUX.LOGICIN36MCB.P0CMDBA1
TCELL10:IMUX.LOGICIN37MCB.UIDRPUPDATE
TCELL10:IMUX.LOGICIN44MCB.P0CMDBL1
TCELL10:IMUX.LOGICIN47MCB.P0CMDEN
TCELL10:IMUX.LOGICIN55MCB.P0CMDBL3
TCELL10:IMUX.LOGICIN57MCB.P0CMDBL0
TCELL10:IMUX.LOGICIN59MCB.UIADDR4
TCELL10:OUT2MCB.UOCALSTART
TCELL10:OUT5MCB.UODONECAL
TCELL10:OUT7MCB.UOCMDREADYIN
TCELL10:OUT16MCB.UOSDO
TCELL10:OUT22MCB.UODATAVALID
TCELL11:IMUX.CLK1MCB.P0CMDCLK
TCELL11:IMUX.SR0MCB.SYSRST
TCELL11:IMUX.LOGICIN1MCB.P0CMDRA4
TCELL11:IMUX.LOGICIN2MCB.P0CMDRA9
TCELL11:IMUX.LOGICIN3MCB.P0CMDRA3
TCELL11:IMUX.LOGICIN4MCB.P0CMDCA10
TCELL11:IMUX.LOGICIN7MCB.P0CMDCA0
TCELL11:IMUX.LOGICIN10MCB.P0CMDRA2
TCELL11:IMUX.LOGICIN12MCB.P0CMDCA2
TCELL11:IMUX.LOGICIN14MCB.P0CMDRA10
TCELL11:IMUX.LOGICIN17MCB.P0CMDCA5
TCELL11:IMUX.LOGICIN23MCB.P0CMDCA6
TCELL11:IMUX.LOGICIN24MCB.PLLLOCK
TCELL11:IMUX.LOGICIN25MCB.P0CMDCA7
TCELL11:IMUX.LOGICIN26MCB.P0CMDRA0
TCELL11:IMUX.LOGICIN27MCB.P0CMDRA6
TCELL11:IMUX.LOGICIN28MCB.P0CMDRA5
TCELL11:IMUX.LOGICIN29MCB.P0ARBEN
TCELL11:IMUX.LOGICIN30MCB.P0CMDRA1
TCELL11:IMUX.LOGICIN31MCB.P0CMDRA12
TCELL11:IMUX.LOGICIN32MCB.P0CMDRA7
TCELL11:IMUX.LOGICIN36MCB.P0CMDCA1
TCELL11:IMUX.LOGICIN37MCB.P0CMDRA11
TCELL11:IMUX.LOGICIN44MCB.P0CMDCA9
TCELL11:IMUX.LOGICIN45MCB.P0CMDCA4
TCELL11:IMUX.LOGICIN47MCB.P0CMDCA3
TCELL11:IMUX.LOGICIN55MCB.P0CMDCA11
TCELL11:IMUX.LOGICIN57MCB.P0CMDCA8
TCELL11:IMUX.LOGICIN59MCB.P0CMDRA8
TCELL11:OUT3MCB.P0CMDFULL
TCELL11:OUT6MCB.P0CMDEMPTY
TCELL12:IMUX.LOGICIN1MCB.P0RTSTMODEB2
TCELL12:IMUX.LOGICIN4MCB.P0RTSTWRDATA13
TCELL12:IMUX.LOGICIN7MCB.P0RTSTWRDATA2
TCELL12:IMUX.LOGICIN9MCB.P0RTSTENB
TCELL12:IMUX.LOGICIN10MCB.P0RTSTWRDATA17
TCELL12:IMUX.LOGICIN12MCB.P0RTSTWRDATA3
TCELL12:IMUX.LOGICIN15MCB.P0RTSTWRDATA0
TCELL12:IMUX.LOGICIN17MCB.P0RTSTWRDATA7
TCELL12:IMUX.LOGICIN19MCB.P0RTSTMODEB3
TCELL12:IMUX.LOGICIN20MCB.P0RTSTWRDATA5
TCELL12:IMUX.LOGICIN23MCB.P0RTSTWRDATA8
TCELL12:IMUX.LOGICIN25MCB.P0RTSTWRDATA10
TCELL12:IMUX.LOGICIN26MCB.P0RTSTWRDATA15
TCELL12:IMUX.LOGICIN29MCB.P0RTSTMODEB1
TCELL12:IMUX.LOGICIN30MCB.P0RTSTWRDATA16
TCELL12:IMUX.LOGICIN32MCB.P0RTSTMODEB0
TCELL12:IMUX.LOGICIN38MCB.P0RTSTWRDATA6
TCELL12:IMUX.LOGICIN42MCB.P0RTSTWRDATA1
TCELL12:IMUX.LOGICIN44MCB.P0RTSTWRDATA12
TCELL12:IMUX.LOGICIN48MCB.P0RTSTWRDATA9
TCELL12:IMUX.LOGICIN55MCB.P0RTSTWRDATA14
TCELL12:IMUX.LOGICIN57MCB.P0RTSTWRDATA11
TCELL12:IMUX.LOGICIN59MCB.P0RTSTPINENB
TCELL12:IMUX.LOGICIN62MCB.P0RTSTWRDATA4
TCELL12:OUT0MCB.P0RDDATA5
TCELL12:OUT1MCB.P0RDDATA13
TCELL12:OUT2MCB.P0RDDATA0
TCELL12:OUT3MCB.P0RDDATA11
TCELL12:OUT4MCB.P0RDFULL
TCELL12:OUT5MCB.P0RDDATA6
TCELL12:OUT6MCB.P0RDDATA17
TCELL12:OUT7MCB.P0RDDATA3
TCELL12:OUT8MCB.P0RDDATA12
TCELL12:OUT9MCB.P0RDCOUNT4
TCELL12:OUT10MCB.P0RDDATA7
TCELL12:OUT11MCB.P0RDCOUNT5
TCELL12:OUT12MCB.P0RDDATA4
TCELL12:OUT13MCB.P0RDDATA16
TCELL12:OUT14MCB.P0RDDATA1
TCELL12:OUT15MCB.P0RDDATA10
TCELL12:OUT16MCB.P0RDOVERFLOW
TCELL12:OUT17MCB.P0RDDATA8
TCELL12:OUT18MCB.P0RDDATA14
TCELL12:OUT19MCB.P0RDDATA2
TCELL12:OUT20MCB.P0RDDATA15
TCELL12:OUT21MCB.P0RTSTUDMP
TCELL12:OUT22MCB.P0RDDATA9
TCELL12:OUT23MCB.P0RDCOUNT6
TCELL13:IMUX.CLK1MCB.P0RDCLK
TCELL13:IMUX.LOGICIN1MCB.P0RTSTWRDATA27
TCELL13:IMUX.LOGICIN2MCB.P0RTSTWRMASK1
TCELL13:IMUX.LOGICIN3MCB.P0RTSTWRDATA26
TCELL13:IMUX.LOGICIN4MCB.P0RTSTWRDATA20
TCELL13:IMUX.LOGICIN7MCB.P0RDEN
TCELL13:IMUX.LOGICIN10MCB.P0RTSTWRDATA25
TCELL13:IMUX.LOGICIN14MCB.P0RTSTWRMASK2
TCELL13:IMUX.LOGICIN19MCB.P0RTSTWRDATA28
TCELL13:IMUX.LOGICIN26MCB.P0RTSTWRDATA22
TCELL13:IMUX.LOGICIN27MCB.P0RTSTWRDATA29
TCELL13:IMUX.LOGICIN29MCB.P0RTSTWRDATA30
TCELL13:IMUX.LOGICIN30MCB.P0RTSTWRDATA23
TCELL13:IMUX.LOGICIN32MCB.P0RTSTWRDATA31
TCELL13:IMUX.LOGICIN37MCB.P0RTSTWRMASK3
TCELL13:IMUX.LOGICIN41MCB.P0RTSTWRDATA24
TCELL13:IMUX.LOGICIN44MCB.P0RTSTWRDATA19
TCELL13:IMUX.LOGICIN52MCB.P0RTSTWRMASK0
TCELL13:IMUX.LOGICIN55MCB.P0RTSTWRDATA21
TCELL13:IMUX.LOGICIN57MCB.P0RTSTWRDATA18
TCELL13:OUT0MCB.P0RDEMPTY
TCELL13:OUT1MCB.P0RDDATA24
TCELL13:OUT2MCB.P0RDCOUNT3
TCELL13:OUT3MCB.P0RDDATA22
TCELL13:OUT4MCB.P0RDDATA29
TCELL13:OUT5MCB.P0RTSTUNDERRUN
TCELL13:OUT6MCB.P0RDDATA28
TCELL13:OUT7MCB.P0RDERROR
TCELL13:OUT8MCB.P0RDDATA23
TCELL13:OUT10MCB.P0RDDATA18
TCELL13:OUT12MCB.P0RDCOUNT0
TCELL13:OUT13MCB.P0RDDATA27
TCELL13:OUT14MCB.P0RDCOUNT2
TCELL13:OUT15MCB.P0RDDATA21
TCELL13:OUT16MCB.P0RDDATA30
TCELL13:OUT17MCB.P0RDDATA19
TCELL13:OUT18MCB.P0RDDATA25
TCELL13:OUT19MCB.P0RDCOUNT1
TCELL13:OUT20MCB.P0RDDATA26
TCELL13:OUT21MCB.P0RDDATA31
TCELL13:OUT22MCB.P0RDDATA20
TCELL14:IMUX.LOGICIN1MCB.P0WTSTMODEB2
TCELL14:IMUX.LOGICIN4MCB.P0WRDATA13
TCELL14:IMUX.LOGICIN7MCB.P0WRDATA2
TCELL14:IMUX.LOGICIN9MCB.P0WTSTENB
TCELL14:IMUX.LOGICIN10MCB.P0WRDATA17
TCELL14:IMUX.LOGICIN12MCB.P0WRDATA3
TCELL14:IMUX.LOGICIN15MCB.P0WRDATA0
TCELL14:IMUX.LOGICIN17MCB.P0WRDATA7
TCELL14:IMUX.LOGICIN19MCB.P0WTSTMODEB3
TCELL14:IMUX.LOGICIN20MCB.P0WRDATA5
TCELL14:IMUX.LOGICIN23MCB.P0WRDATA8
TCELL14:IMUX.LOGICIN25MCB.P0WRDATA10
TCELL14:IMUX.LOGICIN26MCB.P0WRDATA15
TCELL14:IMUX.LOGICIN29MCB.P0WTSTMODEB1
TCELL14:IMUX.LOGICIN30MCB.P0WRDATA16
TCELL14:IMUX.LOGICIN32MCB.P0WTSTMODEB0
TCELL14:IMUX.LOGICIN38MCB.P0WRDATA6
TCELL14:IMUX.LOGICIN42MCB.P0WRDATA1
TCELL14:IMUX.LOGICIN44MCB.P0WRDATA12
TCELL14:IMUX.LOGICIN48MCB.P0WRDATA9
TCELL14:IMUX.LOGICIN55MCB.P0WRDATA14
TCELL14:IMUX.LOGICIN57MCB.P0WRDATA11
TCELL14:IMUX.LOGICIN59MCB.P0WTSTPINENB
TCELL14:IMUX.LOGICIN62MCB.P0WRDATA4
TCELL14:OUT0MCB.P0WTSTDATA5
TCELL14:OUT1MCB.P0WTSTDATA13
TCELL14:OUT2MCB.P0WTSTDATA0
TCELL14:OUT3MCB.P0WTSTDATA11
TCELL14:OUT4MCB.P0WRFULL
TCELL14:OUT5MCB.P0WTSTDATA6
TCELL14:OUT6MCB.P0WTSTDATA17
TCELL14:OUT7MCB.P0WTSTDATA3
TCELL14:OUT8MCB.P0WTSTDATA12
TCELL14:OUT9MCB.P0WRCOUNT4
TCELL14:OUT10MCB.P0WTSTDATA7
TCELL14:OUT11MCB.P0WRCOUNT5
TCELL14:OUT12MCB.P0WTSTDATA4
TCELL14:OUT13MCB.P0WTSTDATA16
TCELL14:OUT14MCB.P0WTSTDATA1
TCELL14:OUT15MCB.P0WTSTDATA10
TCELL14:OUT16MCB.P0WTSTOVERFLOW
TCELL14:OUT17MCB.P0WTSTDATA8
TCELL14:OUT18MCB.P0WTSTDATA14
TCELL14:OUT19MCB.P0WTSTDATA2
TCELL14:OUT20MCB.P0WTSTDATA15
TCELL14:OUT21MCB.P0WTSTLDMP
TCELL14:OUT22MCB.P0WTSTDATA9
TCELL14:OUT23MCB.P0WRCOUNT6
TCELL15:IMUX.CLK1MCB.P0WRCLK
TCELL15:IMUX.LOGICIN1MCB.P0WRDATA27
TCELL15:IMUX.LOGICIN2MCB.P0RWRMASK1
TCELL15:IMUX.LOGICIN3MCB.P0WRDATA26
TCELL15:IMUX.LOGICIN4MCB.P0WRDATA20
TCELL15:IMUX.LOGICIN7MCB.P0WREN
TCELL15:IMUX.LOGICIN10MCB.P0WRDATA25
TCELL15:IMUX.LOGICIN14MCB.P0RWRMASK2
TCELL15:IMUX.LOGICIN19MCB.P0WRDATA28
TCELL15:IMUX.LOGICIN26MCB.P0WRDATA22
TCELL15:IMUX.LOGICIN27MCB.P0WRDATA29
TCELL15:IMUX.LOGICIN29MCB.P0WRDATA30
TCELL15:IMUX.LOGICIN30MCB.P0WRDATA23
TCELL15:IMUX.LOGICIN32MCB.P0WRDATA31
TCELL15:IMUX.LOGICIN37MCB.P0RWRMASK3
TCELL15:IMUX.LOGICIN41MCB.P0WRDATA24
TCELL15:IMUX.LOGICIN44MCB.P0WRDATA19
TCELL15:IMUX.LOGICIN52MCB.P0RWRMASK0
TCELL15:IMUX.LOGICIN55MCB.P0WRDATA21
TCELL15:IMUX.LOGICIN57MCB.P0WRDATA18
TCELL15:OUT0MCB.P0WREMPTY
TCELL15:OUT1MCB.P0WTSTDATA24
TCELL15:OUT2MCB.P0WRCOUNT3
TCELL15:OUT3MCB.P0WTSTDATA22
TCELL15:OUT4MCB.P0WTSTDATA29
TCELL15:OUT5MCB.P0WRUNDERRUN
TCELL15:OUT6MCB.P0WTSTDATA28
TCELL15:OUT7MCB.P0WRERROR
TCELL15:OUT8MCB.P0WTSTDATA23
TCELL15:OUT10MCB.P0WTSTDATA18
TCELL15:OUT12MCB.P0WRCOUNT0
TCELL15:OUT13MCB.P0WTSTDATA27
TCELL15:OUT14MCB.P0WRCOUNT2
TCELL15:OUT15MCB.P0WTSTDATA21
TCELL15:OUT16MCB.P0WTSTDATA30
TCELL15:OUT17MCB.P0WTSTDATA19
TCELL15:OUT18MCB.P0WTSTDATA25
TCELL15:OUT19MCB.P0WRCOUNT1
TCELL15:OUT20MCB.P0WTSTDATA26
TCELL15:OUT21MCB.P0WTSTDATA31
TCELL15:OUT22MCB.P0WTSTDATA20
TCELL16:IMUX.LOGICIN1MCB.P1RTSTMODEB2
TCELL16:IMUX.LOGICIN4MCB.P1RTSTWRDATA13
TCELL16:IMUX.LOGICIN7MCB.P1RTSTWRDATA2
TCELL16:IMUX.LOGICIN9MCB.P1RTSTENB
TCELL16:IMUX.LOGICIN10MCB.P1RTSTWRDATA17
TCELL16:IMUX.LOGICIN12MCB.P1RTSTWRDATA3
TCELL16:IMUX.LOGICIN15MCB.P1RTSTWRDATA0
TCELL16:IMUX.LOGICIN17MCB.P1RTSTWRDATA7
TCELL16:IMUX.LOGICIN19MCB.P1RTSTMODEB3
TCELL16:IMUX.LOGICIN20MCB.P1RTSTWRDATA5
TCELL16:IMUX.LOGICIN23MCB.P1RTSTWRDATA8
TCELL16:IMUX.LOGICIN25MCB.P1RTSTWRDATA10
TCELL16:IMUX.LOGICIN26MCB.P1RTSTWRDATA15
TCELL16:IMUX.LOGICIN29MCB.P1RTSTMODEB1
TCELL16:IMUX.LOGICIN30MCB.P1RTSTWRDATA16
TCELL16:IMUX.LOGICIN32MCB.P1RTSTMODEB0
TCELL16:IMUX.LOGICIN38MCB.P1RTSTWRDATA6
TCELL16:IMUX.LOGICIN42MCB.P1RTSTWRDATA1
TCELL16:IMUX.LOGICIN44MCB.P1RTSTWRDATA12
TCELL16:IMUX.LOGICIN48MCB.P1RTSTWRDATA9
TCELL16:IMUX.LOGICIN55MCB.P1RTSTWRDATA14
TCELL16:IMUX.LOGICIN57MCB.P1RTSTWRDATA11
TCELL16:IMUX.LOGICIN59MCB.P1RTSTPINENB
TCELL16:IMUX.LOGICIN62MCB.P1RTSTWRDATA4
TCELL16:OUT0MCB.P1RDDATA5
TCELL16:OUT1MCB.P1RDDATA13
TCELL16:OUT2MCB.P1RDDATA0
TCELL16:OUT3MCB.P1RDDATA11
TCELL16:OUT4MCB.P1RDFULL
TCELL16:OUT5MCB.P1RDDATA6
TCELL16:OUT6MCB.P1RDDATA17
TCELL16:OUT7MCB.P1RDDATA3
TCELL16:OUT8MCB.P1RDDATA12
TCELL16:OUT9MCB.P1RDCOUNT4
TCELL16:OUT10MCB.P1RDDATA7
TCELL16:OUT11MCB.P1RDCOUNT5
TCELL16:OUT12MCB.P1RDDATA4
TCELL16:OUT13MCB.P1RDDATA16
TCELL16:OUT14MCB.P1RDDATA1
TCELL16:OUT15MCB.P1RDDATA10
TCELL16:OUT16MCB.P1RDOVERFLOW
TCELL16:OUT17MCB.P1RDDATA8
TCELL16:OUT18MCB.P1RDDATA14
TCELL16:OUT19MCB.P1RDDATA2
TCELL16:OUT20MCB.P1RDDATA15
TCELL16:OUT21MCB.P1RTSTUDMN
TCELL16:OUT22MCB.P1RDDATA9
TCELL16:OUT23MCB.P1RDCOUNT6
TCELL17:IMUX.CLK1MCB.P1RDCLK
TCELL17:IMUX.LOGICIN1MCB.P1RTSTWRDATA27
TCELL17:IMUX.LOGICIN2MCB.P1RTSTWRMASK1
TCELL17:IMUX.LOGICIN3MCB.P1RTSTWRDATA26
TCELL17:IMUX.LOGICIN4MCB.P1RTSTWRDATA20
TCELL17:IMUX.LOGICIN7MCB.P1RDEN
TCELL17:IMUX.LOGICIN10MCB.P1RTSTWRDATA25
TCELL17:IMUX.LOGICIN14MCB.P1RTSTWRMASK2
TCELL17:IMUX.LOGICIN19MCB.P1RTSTWRDATA28
TCELL17:IMUX.LOGICIN26MCB.P1RTSTWRDATA22
TCELL17:IMUX.LOGICIN27MCB.P1RTSTWRDATA29
TCELL17:IMUX.LOGICIN29MCB.P1RTSTWRDATA30
TCELL17:IMUX.LOGICIN30MCB.P1RTSTWRDATA23
TCELL17:IMUX.LOGICIN32MCB.P1RTSTWRDATA31
TCELL17:IMUX.LOGICIN37MCB.P1RTSTWRMASK3
TCELL17:IMUX.LOGICIN41MCB.P1RTSTWRDATA24
TCELL17:IMUX.LOGICIN44MCB.P1RTSTWRDATA19
TCELL17:IMUX.LOGICIN52MCB.P1RTSTWRMASK0
TCELL17:IMUX.LOGICIN55MCB.P1RTSTWRDATA21
TCELL17:IMUX.LOGICIN57MCB.P1RTSTWRDATA18
TCELL17:OUT0MCB.P1RDEMPTY
TCELL17:OUT1MCB.P1RDDATA24
TCELL17:OUT2MCB.P1RDCOUNT3
TCELL17:OUT3MCB.P1RDDATA22
TCELL17:OUT4MCB.P1RDDATA29
TCELL17:OUT5MCB.P1RTSTUNDERRUN
TCELL17:OUT6MCB.P1RDDATA28
TCELL17:OUT7MCB.P1RDERROR
TCELL17:OUT8MCB.P1RDDATA23
TCELL17:OUT10MCB.P1RDDATA18
TCELL17:OUT12MCB.P1RDCOUNT0
TCELL17:OUT13MCB.P1RDDATA27
TCELL17:OUT14MCB.P1RDCOUNT2
TCELL17:OUT15MCB.P1RDDATA21
TCELL17:OUT16MCB.P1RDDATA30
TCELL17:OUT17MCB.P1RDDATA19
TCELL17:OUT18MCB.P1RDDATA25
TCELL17:OUT19MCB.P1RDCOUNT1
TCELL17:OUT20MCB.P1RDDATA26
TCELL17:OUT21MCB.P1RDDATA31
TCELL17:OUT22MCB.P1RDDATA20
TCELL18:IMUX.LOGICIN1MCB.P1WTSTMODEB2
TCELL18:IMUX.LOGICIN4MCB.P1WRDATA13
TCELL18:IMUX.LOGICIN7MCB.P1WRDATA2
TCELL18:IMUX.LOGICIN9MCB.P1WTSTENB
TCELL18:IMUX.LOGICIN10MCB.P1WRDATA17
TCELL18:IMUX.LOGICIN12MCB.P1WRDATA3
TCELL18:IMUX.LOGICIN15MCB.P1WRDATA0
TCELL18:IMUX.LOGICIN17MCB.P1WRDATA7
TCELL18:IMUX.LOGICIN19MCB.P1WTSTMODEB3
TCELL18:IMUX.LOGICIN20MCB.P1WRDATA5
TCELL18:IMUX.LOGICIN23MCB.P1WRDATA8
TCELL18:IMUX.LOGICIN25MCB.P1WRDATA10
TCELL18:IMUX.LOGICIN26MCB.P1WRDATA15
TCELL18:IMUX.LOGICIN29MCB.P1WTSTMODEB1
TCELL18:IMUX.LOGICIN30MCB.P1WRDATA16
TCELL18:IMUX.LOGICIN32MCB.P1WTSTMODEB0
TCELL18:IMUX.LOGICIN38MCB.P1WRDATA6
TCELL18:IMUX.LOGICIN42MCB.P1WRDATA1
TCELL18:IMUX.LOGICIN44MCB.P1WRDATA12
TCELL18:IMUX.LOGICIN48MCB.P1WRDATA9
TCELL18:IMUX.LOGICIN55MCB.P1WRDATA14
TCELL18:IMUX.LOGICIN57MCB.P1WRDATA11
TCELL18:IMUX.LOGICIN59MCB.P1WTSTPINENB
TCELL18:IMUX.LOGICIN62MCB.P1WRDATA4
TCELL18:OUT0MCB.P1WTSTDATA5
TCELL18:OUT1MCB.P1WTSTDATA13
TCELL18:OUT2MCB.P1WTSTDATA0
TCELL18:OUT3MCB.P1WTSTDATA11
TCELL18:OUT4MCB.P1WRFULL
TCELL18:OUT5MCB.P1WTSTDATA6
TCELL18:OUT6MCB.P1WTSTDATA17
TCELL18:OUT7MCB.P1WTSTDATA3
TCELL18:OUT8MCB.P1WTSTDATA12
TCELL18:OUT9MCB.P1WRCOUNT4
TCELL18:OUT10MCB.P1WTSTDATA7
TCELL18:OUT11MCB.P1WRCOUNT5
TCELL18:OUT12MCB.P1WTSTDATA4
TCELL18:OUT13MCB.P1WTSTDATA16
TCELL18:OUT14MCB.P1WTSTDATA1
TCELL18:OUT15MCB.P1WTSTDATA10
TCELL18:OUT16MCB.P1WTSTOVERFLOW
TCELL18:OUT17MCB.P1WTSTDATA8
TCELL18:OUT18MCB.P1WTSTDATA14
TCELL18:OUT19MCB.P1WTSTDATA2
TCELL18:OUT20MCB.P1WTSTDATA15
TCELL18:OUT21MCB.P1WTSTLDMN
TCELL18:OUT22MCB.P1WTSTDATA9
TCELL18:OUT23MCB.P1WRCOUNT6
TCELL19:IMUX.CLK1MCB.P1WRCLK
TCELL19:IMUX.LOGICIN1MCB.P1WRDATA27
TCELL19:IMUX.LOGICIN2MCB.P1RWRMASK1
TCELL19:IMUX.LOGICIN3MCB.P1WRDATA26
TCELL19:IMUX.LOGICIN4MCB.P1WRDATA20
TCELL19:IMUX.LOGICIN7MCB.P1WREN
TCELL19:IMUX.LOGICIN10MCB.P1WRDATA25
TCELL19:IMUX.LOGICIN14MCB.P1RWRMASK2
TCELL19:IMUX.LOGICIN19MCB.P1WRDATA28
TCELL19:IMUX.LOGICIN26MCB.P1WRDATA22
TCELL19:IMUX.LOGICIN27MCB.P1WRDATA29
TCELL19:IMUX.LOGICIN29MCB.P1WRDATA30
TCELL19:IMUX.LOGICIN30MCB.P1WRDATA23
TCELL19:IMUX.LOGICIN32MCB.P1WRDATA31
TCELL19:IMUX.LOGICIN37MCB.P1RWRMASK3
TCELL19:IMUX.LOGICIN41MCB.P1WRDATA24
TCELL19:IMUX.LOGICIN44MCB.P1WRDATA19
TCELL19:IMUX.LOGICIN52MCB.P1RWRMASK0
TCELL19:IMUX.LOGICIN55MCB.P1WRDATA21
TCELL19:IMUX.LOGICIN57MCB.P1WRDATA18
TCELL19:OUT0MCB.P1WREMPTY
TCELL19:OUT1MCB.P1WTSTDATA24
TCELL19:OUT2MCB.P1WRCOUNT3
TCELL19:OUT3MCB.P1WTSTDATA22
TCELL19:OUT4MCB.P1WTSTDATA29
TCELL19:OUT5MCB.P1WRUNDERRUN
TCELL19:OUT6MCB.P1WTSTDATA28
TCELL19:OUT7MCB.P1WRERROR
TCELL19:OUT8MCB.P1WTSTDATA23
TCELL19:OUT10MCB.P1WTSTDATA18
TCELL19:OUT12MCB.P1WRCOUNT0
TCELL19:OUT13MCB.P1WTSTDATA27
TCELL19:OUT14MCB.P1WRCOUNT2
TCELL19:OUT15MCB.P1WTSTDATA21
TCELL19:OUT16MCB.P1WTSTDATA30
TCELL19:OUT17MCB.P1WTSTDATA19
TCELL19:OUT18MCB.P1WTSTDATA25
TCELL19:OUT19MCB.P1WRCOUNT1
TCELL19:OUT20MCB.P1WTSTDATA26
TCELL19:OUT21MCB.P1WTSTDATA31
TCELL19:OUT22MCB.P1WTSTDATA20
TCELL20:IMUX.LOGICIN1MCB.P2TSTMODEB2
TCELL20:IMUX.LOGICIN4MCB.P2WRDATA13
TCELL20:IMUX.LOGICIN7MCB.P2WRDATA2
TCELL20:IMUX.LOGICIN9MCB.P2TSTENB
TCELL20:IMUX.LOGICIN10MCB.P2WRDATA17
TCELL20:IMUX.LOGICIN12MCB.P2WRDATA3
TCELL20:IMUX.LOGICIN15MCB.P2WRDATA0
TCELL20:IMUX.LOGICIN17MCB.P2WRDATA7
TCELL20:IMUX.LOGICIN19MCB.P2TSTMODEB3
TCELL20:IMUX.LOGICIN20MCB.P2WRDATA5
TCELL20:IMUX.LOGICIN23MCB.P2WRDATA8
TCELL20:IMUX.LOGICIN25MCB.P2WRDATA10
TCELL20:IMUX.LOGICIN26MCB.P2WRDATA15
TCELL20:IMUX.LOGICIN29MCB.P2TSTMODEB1
TCELL20:IMUX.LOGICIN30MCB.P2WRDATA16
TCELL20:IMUX.LOGICIN32MCB.P2TSTMODEB0
TCELL20:IMUX.LOGICIN38MCB.P2WRDATA6
TCELL20:IMUX.LOGICIN42MCB.P2WRDATA1
TCELL20:IMUX.LOGICIN44MCB.P2WRDATA12
TCELL20:IMUX.LOGICIN48MCB.P2WRDATA9
TCELL20:IMUX.LOGICIN55MCB.P2WRDATA14
TCELL20:IMUX.LOGICIN57MCB.P2WRDATA11
TCELL20:IMUX.LOGICIN59MCB.P2TSTPINENB
TCELL20:IMUX.LOGICIN62MCB.P2WRDATA4
TCELL20:OUT0MCB.P2RDDATA5
TCELL20:OUT1MCB.P2RDDATA13
TCELL20:OUT2MCB.P2RDDATA0
TCELL20:OUT3MCB.P2RDDATA11
TCELL20:OUT4MCB.P2FULL
TCELL20:OUT5MCB.P2RDDATA6
TCELL20:OUT6MCB.P2RDDATA17
TCELL20:OUT7MCB.P2RDDATA3
TCELL20:OUT8MCB.P2RDDATA12
TCELL20:OUT9MCB.P2COUNT4
TCELL20:OUT10MCB.P2RDDATA7
TCELL20:OUT11MCB.P2COUNT5
TCELL20:OUT12MCB.P2RDDATA4
TCELL20:OUT13MCB.P2RDDATA16
TCELL20:OUT14MCB.P2RDDATA1
TCELL20:OUT15MCB.P2RDDATA10
TCELL20:OUT16MCB.P2RDOVERFLOW
TCELL20:OUT17MCB.P2RDDATA8
TCELL20:OUT18MCB.P2RDDATA14
TCELL20:OUT19MCB.P2RDDATA2
TCELL20:OUT20MCB.P2RDDATA15
TCELL20:OUT21MCB.P2TSTUDMP
TCELL20:OUT22MCB.P2RDDATA9
TCELL20:OUT23MCB.P2COUNT6
TCELL21:IMUX.CLK1MCB.P2CLK
TCELL21:IMUX.LOGICIN1MCB.P2WRDATA27
TCELL21:IMUX.LOGICIN2MCB.P2WRMASK1
TCELL21:IMUX.LOGICIN3MCB.P2WRDATA26
TCELL21:IMUX.LOGICIN4MCB.P2WRDATA20
TCELL21:IMUX.LOGICIN7MCB.P2EN
TCELL21:IMUX.LOGICIN10MCB.P2WRDATA25
TCELL21:IMUX.LOGICIN14MCB.P2WRMASK2
TCELL21:IMUX.LOGICIN19MCB.P2WRDATA28
TCELL21:IMUX.LOGICIN26MCB.P2WRDATA22
TCELL21:IMUX.LOGICIN27MCB.P2WRDATA29
TCELL21:IMUX.LOGICIN29MCB.P2WRDATA30
TCELL21:IMUX.LOGICIN30MCB.P2WRDATA23
TCELL21:IMUX.LOGICIN32MCB.P2WRDATA31
TCELL21:IMUX.LOGICIN37MCB.P2WRMASK3
TCELL21:IMUX.LOGICIN41MCB.P2WRDATA24
TCELL21:IMUX.LOGICIN44MCB.P2WRDATA19
TCELL21:IMUX.LOGICIN52MCB.P2WRMASK0
TCELL21:IMUX.LOGICIN55MCB.P2WRDATA21
TCELL21:IMUX.LOGICIN57MCB.P2WRDATA18
TCELL21:OUT0MCB.P2EMPTY
TCELL21:OUT1MCB.P2RDDATA24
TCELL21:OUT2MCB.P2COUNT3
TCELL21:OUT3MCB.P2RDDATA22
TCELL21:OUT4MCB.P2RDDATA29
TCELL21:OUT5MCB.P2WRUNDERRUN
TCELL21:OUT6MCB.P2RDDATA28
TCELL21:OUT7MCB.P2ERROR
TCELL21:OUT8MCB.P2RDDATA23
TCELL21:OUT10MCB.P2RDDATA18
TCELL21:OUT12MCB.P2COUNT0
TCELL21:OUT13MCB.P2RDDATA27
TCELL21:OUT14MCB.P2COUNT2
TCELL21:OUT15MCB.P2RDDATA21
TCELL21:OUT16MCB.P2RDDATA30
TCELL21:OUT17MCB.P2RDDATA19
TCELL21:OUT18MCB.P2RDDATA25
TCELL21:OUT19MCB.P2COUNT1
TCELL21:OUT20MCB.P2RDDATA26
TCELL21:OUT21MCB.P2RDDATA31
TCELL21:OUT22MCB.P2RDDATA20
TCELL22:IMUX.LOGICIN1MCB.P3TSTMODEB2
TCELL22:IMUX.LOGICIN4MCB.P3WRDATA13
TCELL22:IMUX.LOGICIN7MCB.P3WRDATA2
TCELL22:IMUX.LOGICIN9MCB.P3TSTENB
TCELL22:IMUX.LOGICIN10MCB.P3WRDATA17
TCELL22:IMUX.LOGICIN12MCB.P3WRDATA3
TCELL22:IMUX.LOGICIN15MCB.P3WRDATA0
TCELL22:IMUX.LOGICIN17MCB.P3WRDATA7
TCELL22:IMUX.LOGICIN19MCB.P3TSTMODEB3
TCELL22:IMUX.LOGICIN20MCB.P3WRDATA5
TCELL22:IMUX.LOGICIN23MCB.P3WRDATA8
TCELL22:IMUX.LOGICIN25MCB.P3WRDATA10
TCELL22:IMUX.LOGICIN26MCB.P3WRDATA15
TCELL22:IMUX.LOGICIN29MCB.P3TSTMODEB1
TCELL22:IMUX.LOGICIN30MCB.P3WRDATA16
TCELL22:IMUX.LOGICIN32MCB.P3TSTMODEB0
TCELL22:IMUX.LOGICIN38MCB.P3WRDATA6
TCELL22:IMUX.LOGICIN42MCB.P3WRDATA1
TCELL22:IMUX.LOGICIN44MCB.P3WRDATA12
TCELL22:IMUX.LOGICIN48MCB.P3WRDATA9
TCELL22:IMUX.LOGICIN55MCB.P3WRDATA14
TCELL22:IMUX.LOGICIN57MCB.P3WRDATA11
TCELL22:IMUX.LOGICIN59MCB.P3TSTPINENB
TCELL22:IMUX.LOGICIN62MCB.P3WRDATA4
TCELL22:OUT0MCB.P3RDDATA5
TCELL22:OUT1MCB.P3RDDATA13
TCELL22:OUT2MCB.P3RDDATA0
TCELL22:OUT3MCB.P3RDDATA11
TCELL22:OUT4MCB.P3FULL
TCELL22:OUT5MCB.P3RDDATA6
TCELL22:OUT6MCB.P3RDDATA17
TCELL22:OUT7MCB.P3RDDATA3
TCELL22:OUT8MCB.P3RDDATA12
TCELL22:OUT9MCB.P3COUNT4
TCELL22:OUT10MCB.P3RDDATA7
TCELL22:OUT11MCB.P3COUNT5
TCELL22:OUT12MCB.P3RDDATA4
TCELL22:OUT13MCB.P3RDDATA16
TCELL22:OUT14MCB.P3RDDATA1
TCELL22:OUT15MCB.P3RDDATA10
TCELL22:OUT16MCB.P3RDOVERFLOW
TCELL22:OUT17MCB.P3RDDATA8
TCELL22:OUT18MCB.P3RDDATA14
TCELL22:OUT19MCB.P3RDDATA2
TCELL22:OUT20MCB.P3RDDATA15
TCELL22:OUT21MCB.P3TSTLDMP
TCELL22:OUT22MCB.P3RDDATA9
TCELL22:OUT23MCB.P3COUNT6
TCELL23:IMUX.CLK1MCB.P3CLK
TCELL23:IMUX.LOGICIN1MCB.P3WRDATA27
TCELL23:IMUX.LOGICIN2MCB.P3WRMASK1
TCELL23:IMUX.LOGICIN3MCB.P3WRDATA26
TCELL23:IMUX.LOGICIN4MCB.P3WRDATA20
TCELL23:IMUX.LOGICIN7MCB.P3EN
TCELL23:IMUX.LOGICIN10MCB.P3WRDATA25
TCELL23:IMUX.LOGICIN14MCB.P3WRMASK2
TCELL23:IMUX.LOGICIN19MCB.P3WRDATA28
TCELL23:IMUX.LOGICIN26MCB.P3WRDATA22
TCELL23:IMUX.LOGICIN27MCB.P3WRDATA29
TCELL23:IMUX.LOGICIN29MCB.P3WRDATA30
TCELL23:IMUX.LOGICIN30MCB.P3WRDATA23
TCELL23:IMUX.LOGICIN32MCB.P3WRDATA31
TCELL23:IMUX.LOGICIN37MCB.P3WRMASK3
TCELL23:IMUX.LOGICIN41MCB.P3WRDATA24
TCELL23:IMUX.LOGICIN44MCB.P3WRDATA19
TCELL23:IMUX.LOGICIN52MCB.P3WRMASK0
TCELL23:IMUX.LOGICIN55MCB.P3WRDATA21
TCELL23:IMUX.LOGICIN57MCB.P3WRDATA18
TCELL23:OUT0MCB.P3EMPTY
TCELL23:OUT1MCB.P3RDDATA24
TCELL23:OUT2MCB.P3COUNT3
TCELL23:OUT3MCB.P3RDDATA22
TCELL23:OUT4MCB.P3RDDATA29
TCELL23:OUT5MCB.P3WRUNDERRUN
TCELL23:OUT6MCB.P3RDDATA28
TCELL23:OUT7MCB.P3ERROR
TCELL23:OUT8MCB.P3RDDATA23
TCELL23:OUT10MCB.P3RDDATA18
TCELL23:OUT12MCB.P3COUNT0
TCELL23:OUT13MCB.P3RDDATA27
TCELL23:OUT14MCB.P3COUNT2
TCELL23:OUT15MCB.P3RDDATA21
TCELL23:OUT16MCB.P3RDDATA30
TCELL23:OUT17MCB.P3RDDATA19
TCELL23:OUT18MCB.P3RDDATA25
TCELL23:OUT19MCB.P3COUNT1
TCELL23:OUT20MCB.P3RDDATA26
TCELL23:OUT21MCB.P3RDDATA31
TCELL23:OUT22MCB.P3RDDATA20
TCELL24:IMUX.LOGICIN1MCB.P4TSTMODEB2
TCELL24:IMUX.LOGICIN4MCB.P4WRDATA13
TCELL24:IMUX.LOGICIN7MCB.P4WRDATA2
TCELL24:IMUX.LOGICIN9MCB.P4TSTENB
TCELL24:IMUX.LOGICIN10MCB.P4WRDATA17
TCELL24:IMUX.LOGICIN12MCB.P4WRDATA3
TCELL24:IMUX.LOGICIN15MCB.P4WRDATA0
TCELL24:IMUX.LOGICIN17MCB.P4WRDATA7
TCELL24:IMUX.LOGICIN19MCB.P4TSTMODEB3
TCELL24:IMUX.LOGICIN20MCB.P4WRDATA5
TCELL24:IMUX.LOGICIN23MCB.P4WRDATA8
TCELL24:IMUX.LOGICIN25MCB.P4WRDATA10
TCELL24:IMUX.LOGICIN26MCB.P4WRDATA15
TCELL24:IMUX.LOGICIN29MCB.P4TSTMODEB1
TCELL24:IMUX.LOGICIN30MCB.P4WRDATA16
TCELL24:IMUX.LOGICIN32MCB.P4TSTMODEB0
TCELL24:IMUX.LOGICIN38MCB.P4WRDATA6
TCELL24:IMUX.LOGICIN42MCB.P4WRDATA1
TCELL24:IMUX.LOGICIN44MCB.P4WRDATA12
TCELL24:IMUX.LOGICIN48MCB.P4WRDATA9
TCELL24:IMUX.LOGICIN55MCB.P4WRDATA14
TCELL24:IMUX.LOGICIN57MCB.P4WRDATA11
TCELL24:IMUX.LOGICIN59MCB.P4TSTPINENB
TCELL24:IMUX.LOGICIN62MCB.P4WRDATA4
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TCELL24:OUT6MCB.P4RDDATA17
TCELL24:OUT7MCB.P4RDDATA3
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TCELL25:IMUX.CLK1MCB.P4CLK
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TCELL26:IMUX.LOGICIN1MCB.P5TSTMODEB2
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16 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_7[16]
15 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_7[15]
14 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_7[14]
13 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_7[13]
12 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_7[12]
11 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_7[11]
10 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_7[10]
9 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_7[9]
8 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_7[8]
7 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_7[7]
6 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_7[6]
5 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_7[5]
4 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_7[4]
3 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_7[3]
2 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_7[2]
1 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_7[1]
0 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_7[0]
spartan6 MCB bittile 5
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
33 - - - - - - - - - - - - - - - - - - - - - - MCB:INV.P3CMDEN
32 - - - - - - - - - - - - - - - - - - - - - - ~MCB:INV.P3CMDCLK
31 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR2[13]
30 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR2[12]
29 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR2[11]
28 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR2[10] MCB:MEM_DDR3_DYN_WRT_ODT[1]
27 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR2[9] MCB:MEM_DDR3_DYN_WRT_ODT[0]
26 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR2[8]
25 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR2[7] MCB:MEM_DDR2_3_HIGH_TEMP_SR[0]
24 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR2[6] MCB:MEM_DDR3_AUTO_SR[0]
23 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR2[5]
22 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR2[4] MCB:MEM_DDR3_CAS_WR_LATENCY[1]
21 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR2[3] MCB:MEM_DDR3_CAS_WR_LATENCY[0]
20 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR2[2] MCB:MEM_DDR2_3_PA_SR[2]
19 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR2[1] MCB:MEM_DDR2_3_PA_SR[1]
18 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR2[0] MCB:MEM_DDR2_3_PA_SR[0]
17 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[17]
16 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[16]
15 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[15]
14 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[14]
13 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[13]
12 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[12]
11 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[11]
10 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[10]
9 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[9]
8 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[8]
7 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[7]
6 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[6]
5 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[5]
4 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[4]
3 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[3]
2 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[2]
1 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[1]
0 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_6[0]
spartan6 MCB bittile 6
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
31 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR1[13]
30 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR1[12]
29 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR1[11]
28 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR1[10] MCB:MEM_DDR2_DIFF_DQS_EN[0]
27 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR1[9] MCB:MEM_DDR3_RTT[2]
26 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR1[8]
25 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR1[7] MCB:MEM_MDDR_ODS[2]
24 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR1[6] MCB:MEM_DDR2_RTT[1] MCB:MEM_DDR3_RTT[0] MCB:MEM_MDDR_ODS[0]
23 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR1[5] MCB:MEM_DDR2_ADD_LATENCY[2] MCB:MEM_MDDR_ODS[1]
22 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR1[4] MCB:MEM_DDR2_ADD_LATENCY[1] MCB:MEM_DDR3_ADD_LATENCY[1] MCB:MEM_MOBILE_TC_SR[1]
21 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR1[3] MCB:MEM_DDR2_ADD_LATENCY[0] MCB:MEM_DDR3_ADD_LATENCY[0] MCB:MEM_MOBILE_TC_SR[0]
20 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR1[2] MCB:MEM_DDR2_RTT[0] MCB:MEM_DDR3_RTT[1]
19 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR1[1] MCB:MEM_DDR1_2_ODS[0] MCB:MEM_DDR3_ODS[0]
18 - - - - - - - - - - - - - - - - - - - - - - MCB:EMR1[0] MCB:MEM_MOBILE_PA_SR[0]
17 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[17]
16 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[16]
15 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[15]
14 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[14]
13 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[13]
12 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[12]
11 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[11]
10 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[10]
9 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[9]
8 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[8]
7 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[7]
6 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[6]
5 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[5]
4 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[4]
3 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[3]
2 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[2]
1 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[1]
0 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_5[0]
spartan6 MCB bittile 7
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
33 - - - - - - - - - - - - - - - - - - - - - - MCB:INV.P2CMDEN
32 - - - - - - - - - - - - - - - - - - - - - - ~MCB:INV.P2CMDCLK
31 - - - - - - - - - - - - - - - - - - - - - - MCB:MR[13]
30 - - - - - - - - - - - - - - - - - - - - - - MCB:MR[12]
29 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_DDR2_WRT_RECOVERY[2] MCB:MEM_DDR3_WRT_RECOVERY[2] MCB:MR[11]
28 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_DDR2_WRT_RECOVERY[1] MCB:MEM_DDR3_WRT_RECOVERY[1] MCB:MR[10]
27 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_DDR2_WRT_RECOVERY[0] MCB:MEM_DDR3_WRT_RECOVERY[0] MCB:MR[9]
26 - - - - - - - - - - - - - - - - - - - - - - MCB:MR[8]
25 - - - - - - - - - - - - - - - - - - - - - - MCB:MR[7]
24 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_CAS_LATENCY[2] MCB:MEM_DDR3_CAS_LATENCY[2] MCB:MR[6]
23 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_CAS_LATENCY[1] MCB:MEM_DDR3_CAS_LATENCY[1] MCB:MR[5]
22 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_CAS_LATENCY[0] MCB:MEM_DDR3_CAS_LATENCY[0] MCB:MR[4]
21 - - - - - - - - - - - - - - - - - - - - - - MCB:MR[3]
20 - - - - - - - - - - - - - - - - - - - - - - MCB:MR[2]
19 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_DDR_DDR2_MDDR_BURST_LEN[0] MCB:MR[1]
18 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_DDR_DDR2_MDDR_BURST_LEN[1] MCB:MR[0]
17 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[17]
16 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[16]
15 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[15]
14 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[14]
13 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[13]
12 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[12]
11 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[11]
10 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[10]
9 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[9]
8 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[8]
7 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[7]
6 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[6]
5 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[5]
4 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[4]
3 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[3]
2 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[2]
1 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[1]
0 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_4[0]
spartan6 MCB bittile 8
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
32 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_ADDR_ORDER[0]
31 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_CA_SIZE[1]
30 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_CA_SIZE[0]
29 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RA_SIZE[1]
28 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RA_SIZE[0]
27 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_BA_SIZE[0]
26 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_NUM_TIME_SLOTS[0]
25 - - - - - - - - - - - - - - - - - - - - - - -
24 - - - - - - - - - - - - - - - - - - - - - - -
23 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_PLL_DIV_EN
22 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_PLL_POL_SEL[0]
21 - - - - - - - - - - - - - - - - - - - - - - -
20 - - - - - - - - - - - - - - - - - - - - - - -
19 - - - - - - - - - - - - - - - - - - - - - - -
18 - - - - - - - - - - - - - - - - - - - - - - -
17 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[17]
16 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[16]
15 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[15]
14 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[14]
13 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[13]
12 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[12]
11 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[11]
10 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[10]
9 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[9]
8 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[8]
7 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[7]
6 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[6]
5 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[5]
4 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[4]
3 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[3]
2 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[2]
1 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[1]
0 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_3[0]
spartan6 MCB bittile 9
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
40 - - - - - - - - - - - - - - - - - - - - - - MCB:INV.P1CMDEN
39 - - - - - - - - - - - - - - - - - - - - - - ~MCB:INV.P1CMDCLK
38 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_WTR_VAL[2]
37 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_WTR_VAL[1]
36 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_WTR_VAL[0]
35 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RTP_VAL[2]
34 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RTP_VAL[1]
33 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RTP_VAL[0]
32 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_WR_VAL[2]
31 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_WR_VAL[1]
30 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_WR_VAL[0]
29 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RP_VAL[3]
28 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RP_VAL[2]
27 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RP_VAL[1]
26 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RP_VAL[0]
25 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RFC_VAL[7]
24 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RFC_VAL[6]
23 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RFC_VAL[5]
22 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RFC_VAL[4]
21 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RFC_VAL[3]
20 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RFC_VAL[2]
19 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RFC_VAL[1]
18 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RFC_VAL[0]
17 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[17]
16 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[16]
15 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[15]
14 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[14]
13 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[13]
12 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[12]
11 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[11]
10 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[10]
9 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[9]
8 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[8]
7 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[7]
6 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[6]
5 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[5]
4 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[4]
3 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[3]
2 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[2]
1 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[1]
0 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_2[0]
spartan6 MCB bittile 10
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
38 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_REFI_VAL[11]
37 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_REFI_VAL[10]
36 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_REFI_VAL[9]
35 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_REFI_VAL[8]
34 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_REFI_VAL[7]
33 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_REFI_VAL[6]
32 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_REFI_VAL[5]
31 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_REFI_VAL[4]
30 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_REFI_VAL[3]
29 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_REFI_VAL[2]
28 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_REFI_VAL[1]
27 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_REFI_VAL[0]
26 - - - - - - - - - - - - - - - - - - - - - - -
25 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RCD_VAL[2]
24 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RCD_VAL[1]
23 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RCD_VAL[0]
22 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RAS_VAL[4]
21 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RAS_VAL[3]
20 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RAS_VAL[2]
19 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_RAS_VAL[1]
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15 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_1[15]
14 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_1[14]
13 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_1[13]
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10 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_1[10]
9 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_1[9]
8 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_1[8]
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6 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_1[6]
5 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_1[5]
4 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_1[4]
3 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_1[3]
2 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_1[2]
1 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_1[1]
0 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_1[0]
spartan6 MCB bittile 11
BitFrame
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29 - - - - - - - - - - - - - - - - - - - - - - -
28 - - - - - - - - - - - - - - - - - - - - - - -
27 - - - - - - - - - - - - - - - - - - - - - - MCB:PORT_CONFIG[2]
26 - - - - - - - - - - - - - - - - - - - - - - MCB:PORT_CONFIG[1]
25 - - - - - - - - - - - - - - - - - - - - - - MCB:PORT_CONFIG[0]
24 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_BURST_LEN[0]
23 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_BURST_LEN[1]
22 - - - - - - - - - - - - - - - - - - - - - - -
21 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_TYPE[0]
20 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_TYPE[1]
19 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_WIDTH[1]
18 - - - - - - - - - - - - - - - - - - - - - - MCB:MEM_WIDTH[0]
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16 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_0[16]
15 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_0[15]
14 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_0[14]
13 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_0[13]
12 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_0[12]
11 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_0[11]
10 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_0[10]
9 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_0[9]
8 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_0[8]
7 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_0[7]
6 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_0[6]
5 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_0[5]
4 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_0[4]
3 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_0[3]
2 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_0[2]
1 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_0[1]
0 - - - - - - - - - - - - - - - - - - - - - - MCB:ARB_TIME_SLOT_0[0]
spartan6 MCB bittile 12
BitFrame
spartan6 MCB bittile 13
BitFrame
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8 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI0R.MEM_PLL_POL_SEL[0]
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6 - - - - - - - - - - - - - - - - - - - - - - - - - ~MCB:INV.P0RDEN
5 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI0R.MEM_PLL_DIV_EN
4 - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI0R.MEM_WIDTH[1]
1 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI0R.MEM_WIDTH[0]
0 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI0R_PORT_CONFIG[0]
spartan6 MCB bittile 14
BitFrame
spartan6 MCB bittile 15
BitFrame
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8 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI0W.MEM_PLL_POL_SEL[0]
7 - - - - - - - - - - - - - - - - - - - - - - - - - ~MCB:INV.P0WRCLK
6 - - - - - - - - - - - - - - - - - - - - - - - - - ~MCB:INV.P0WREN
5 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI0W.MEM_PLL_DIV_EN
4 - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI0W.MEM_WIDTH[1]
1 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI0W.MEM_WIDTH[0]
0 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI0W_PORT_CONFIG[0]
spartan6 MCB bittile 16
BitFrame
spartan6 MCB bittile 17
BitFrame
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8 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI1R.MEM_PLL_POL_SEL[0]
7 - - - - - - - - - - - - - - - - - - - - - - - - - ~MCB:INV.P1RDCLK
6 - - - - - - - - - - - - - - - - - - - - - - - - - ~MCB:INV.P1RDEN
5 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI1R.MEM_PLL_DIV_EN
4 - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI1R.MEM_WIDTH[1]
1 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI1R.MEM_WIDTH[0]
0 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI1R_PORT_CONFIG[0]
spartan6 MCB bittile 18
BitFrame
spartan6 MCB bittile 19
BitFrame
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8 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI1W.MEM_PLL_POL_SEL[0]
7 - - - - - - - - - - - - - - - - - - - - - - - - - ~MCB:INV.P1WRCLK
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5 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI1W.MEM_PLL_DIV_EN
4 - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI1W.MEM_WIDTH[1]
1 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI1W.MEM_WIDTH[0]
0 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI1W_PORT_CONFIG[0]
spartan6 MCB bittile 20
BitFrame
spartan6 MCB bittile 21
BitFrame
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8 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI0.MEM_PLL_POL_SEL[0]
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6 - - - - - - - - - - - - - - - - - - - - - - - - - ~MCB:INV.P2EN
5 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI0.MEM_PLL_DIV_EN
4 - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI0.MEM_WIDTH[1]
1 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI0.MEM_WIDTH[0]
0 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI2_PORT_CONFIG[0]
spartan6 MCB bittile 22
BitFrame
spartan6 MCB bittile 23
BitFrame
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8 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI1.MEM_PLL_POL_SEL[0]
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5 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI1.MEM_PLL_DIV_EN
4 - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI1.MEM_WIDTH[1]
1 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI1.MEM_WIDTH[0]
0 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI3_PORT_CONFIG[0]
spartan6 MCB bittile 24
BitFrame
spartan6 MCB bittile 25
BitFrame
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8 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI2.MEM_PLL_POL_SEL[0]
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5 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI2.MEM_PLL_DIV_EN
4 - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI2.MEM_WIDTH[1]
1 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI2.MEM_WIDTH[0]
0 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI4_PORT_CONFIG[0]
spartan6 MCB bittile 26
BitFrame
spartan6 MCB bittile 27
BitFrame
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8 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI3.MEM_PLL_POL_SEL[0]
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5 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI3.MEM_PLL_DIV_EN
4 - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI3.MEM_WIDTH[1]
1 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI3.MEM_WIDTH[0]
0 - - - - - - - - - - - - - - - - - - - - - - - - - MCB:MUI5_PORT_CONFIG[0]
MCB:ARB_NUM_TIME_SLOTS 8.22.26
10 0
12 1
MCB:ARB_TIME_SLOT_0 11.22.17 11.22.16 11.22.15 11.22.14 11.22.13 11.22.12 11.22.11 11.22.10 11.22.9 11.22.8 11.22.7 11.22.6 11.22.5 11.22.4 11.22.3 11.22.2 11.22.1 11.22.0
MCB:ARB_TIME_SLOT_1 10.22.17 10.22.16 10.22.15 10.22.14 10.22.13 10.22.12 10.22.11 10.22.10 10.22.9 10.22.8 10.22.7 10.22.6 10.22.5 10.22.4 10.22.3 10.22.2 10.22.1 10.22.0
MCB:ARB_TIME_SLOT_10 1.22.17 1.22.16 1.22.15 1.22.14 1.22.13 1.22.12 1.22.11 1.22.10 1.22.9 1.22.8 1.22.7 1.22.6 1.22.5 1.22.4 1.22.3 1.22.2 1.22.1 1.22.0
MCB:ARB_TIME_SLOT_11 0.22.17 0.22.16 0.22.15 0.22.14 0.22.13 0.22.12 0.22.11 0.22.10 0.22.9 0.22.8 0.22.7 0.22.6 0.22.5 0.22.4 0.22.3 0.22.2 0.22.1 0.22.0
MCB:ARB_TIME_SLOT_2 9.22.17 9.22.16 9.22.15 9.22.14 9.22.13 9.22.12 9.22.11 9.22.10 9.22.9 9.22.8 9.22.7 9.22.6 9.22.5 9.22.4 9.22.3 9.22.2 9.22.1 9.22.0
MCB:ARB_TIME_SLOT_3 8.22.17 8.22.16 8.22.15 8.22.14 8.22.13 8.22.12 8.22.11 8.22.10 8.22.9 8.22.8 8.22.7 8.22.6 8.22.5 8.22.4 8.22.3 8.22.2 8.22.1 8.22.0
MCB:ARB_TIME_SLOT_4 7.22.17 7.22.16 7.22.15 7.22.14 7.22.13 7.22.12 7.22.11 7.22.10 7.22.9 7.22.8 7.22.7 7.22.6 7.22.5 7.22.4 7.22.3 7.22.2 7.22.1 7.22.0
MCB:ARB_TIME_SLOT_5 6.22.17 6.22.16 6.22.15 6.22.14 6.22.13 6.22.12 6.22.11 6.22.10 6.22.9 6.22.8 6.22.7 6.22.6 6.22.5 6.22.4 6.22.3 6.22.2 6.22.1 6.22.0
MCB:ARB_TIME_SLOT_6 5.22.17 5.22.16 5.22.15 5.22.14 5.22.13 5.22.12 5.22.11 5.22.10 5.22.9 5.22.8 5.22.7 5.22.6 5.22.5 5.22.4 5.22.3 5.22.2 5.22.1 5.22.0
MCB:ARB_TIME_SLOT_7 4.22.17 4.22.16 4.22.15 4.22.14 4.22.13 4.22.12 4.22.11 4.22.10 4.22.9 4.22.8 4.22.7 4.22.6 4.22.5 4.22.4 4.22.3 4.22.2 4.22.1 4.22.0
MCB:ARB_TIME_SLOT_8 3.22.17 3.22.16 3.22.15 3.22.14 3.22.13 3.22.12 3.22.11 3.22.10 3.22.9 3.22.8 3.22.7 3.22.6 3.22.5 3.22.4 3.22.3 3.22.2 3.22.1 3.22.0
MCB:ARB_TIME_SLOT_9 2.22.17 2.22.16 2.22.15 2.22.14 2.22.13 2.22.12 2.22.11 2.22.10 2.22.9 2.22.8 2.22.7 2.22.6 2.22.5 2.22.4 2.22.3 2.22.2 2.22.1 2.22.0
non-inverted [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
MCB:CAL_BA 3.22.22 3.22.21 3.22.20
MCB:MEM_RCD_VAL 10.22.25 10.22.24 10.22.23
MCB:MEM_RTP_VAL 9.22.35 9.22.34 9.22.33
MCB:MEM_WR_VAL 9.22.32 9.22.31 9.22.30
MCB:MEM_WTR_VAL 9.22.38 9.22.37 9.22.36
non-inverted [2] [1] [0]
MCB:CAL_BYPASS 3.22.19
MCB:INV.P0CMDEN 11.22.31
MCB:INV.P1CMDEN 9.22.40
MCB:INV.P2CMDEN 7.22.33
MCB:INV.P3CMDEN 5.22.33
MCB:INV.P4CMDEN 3.22.24
MCB:INV.P5CMDEN 1.22.31
MCB:MEM_PLL_DIV_EN 8.22.23
MCB:MUI0.MEM_PLL_DIV_EN 21.25.5
MCB:MUI0R.MEM_PLL_DIV_EN 13.25.5
MCB:MUI0W.MEM_PLL_DIV_EN 15.25.5
MCB:MUI1.MEM_PLL_DIV_EN 23.25.5
MCB:MUI1R.MEM_PLL_DIV_EN 17.25.5
MCB:MUI1W.MEM_PLL_DIV_EN 19.25.5
MCB:MUI2.MEM_PLL_DIV_EN 25.25.5
MCB:MUI3.MEM_PLL_DIV_EN 27.25.5
non-inverted [0]
MCB:CAL_CA 1.22.29 1.22.28 1.22.27 1.22.26 1.22.25 1.22.24 1.22.23 1.22.22 1.22.21 1.22.20 1.22.19 1.22.18
MCB:MEM_REFI_VAL 10.22.38 10.22.37 10.22.36 10.22.35 10.22.34 10.22.33 10.22.32 10.22.31 10.22.30 10.22.29 10.22.28 10.22.27
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
MCB:CAL_CALIBRATION_MODE 0.22.21
CALIBRATION 0
NOCALIBRATION 1
MCB:CAL_CLK_DIV 0.22.19 0.22.18
1 0 0
2 0 1
4 1 0
8 1 1
MCB:CAL_DELAY 0.22.23 0.22.22
QUARTER 0 0
HALF 0 1
THREEQUARTER 1 0
FULL 1 1
MCB:CAL_RA 2.22.32 2.22.31 2.22.30 2.22.29 2.22.28 2.22.27 2.22.26 2.22.25 2.22.24 2.22.23 2.22.22 2.22.21 2.22.20 2.22.19 2.22.18
non-inverted [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
MCB:EMR1 6.22.31 6.22.30 6.22.29 6.22.28 6.22.27 6.22.26 6.22.25 6.22.24 6.22.23 6.22.22 6.22.21 6.22.20 6.22.19 6.22.18
MCB:EMR2 5.22.31 5.22.30 5.22.29 5.22.28 5.22.27 5.22.26 5.22.25 5.22.24 5.22.23 5.22.22 5.22.21 5.22.20 5.22.19 5.22.18
MCB:EMR3 4.22.31 4.22.30 4.22.29 4.22.28 4.22.27 4.22.26 4.22.25 4.22.24 4.22.23 4.22.22 4.22.21 4.22.20 4.22.19 4.22.18
MCB:MR 7.22.31 7.22.30 7.22.29 7.22.28 7.22.27 7.22.26 7.22.25 7.22.24 7.22.23 7.22.22 7.22.21 7.22.20 7.22.19 7.22.18
non-inverted [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
MCB:INV.P0CMDCLK 11.22.30
MCB:INV.P0RDCLK 13.25.7
MCB:INV.P0RDEN 13.25.6
MCB:INV.P0WRCLK 15.25.7
MCB:INV.P0WREN 15.25.6
MCB:INV.P1CMDCLK 9.22.39
MCB:INV.P1RDCLK 17.25.7
MCB:INV.P1RDEN 17.25.6
MCB:INV.P1WRCLK 19.25.7
MCB:INV.P1WREN 19.25.6
MCB:INV.P2CLK 21.25.7
MCB:INV.P2CMDCLK 7.22.32
MCB:INV.P2EN 21.25.6
MCB:INV.P3CLK 23.25.7
MCB:INV.P3CMDCLK 5.22.32
MCB:INV.P3EN 23.25.6
MCB:INV.P4CLK 25.25.7
MCB:INV.P4CMDCLK 3.22.23
MCB:INV.P4EN 25.25.6
MCB:INV.P5CLK 27.25.7
MCB:INV.P5CMDCLK 1.22.30
MCB:INV.P5EN 27.25.6
inverted ~[0]
MCB:MEM_ADDR_ORDER 8.22.32
BANK_ROW_COLUMN 0
ROW_BANK_COLUMN 1
MCB:MEM_BA_SIZE 8.22.27
2 0
3 1
MCB:MEM_BURST_LEN 11.22.23 11.22.24
MCB:MEM_DDR_DDR2_MDDR_BURST_LEN 7.22.18 7.22.19
4 0 1
8 1 1
MCB:MEM_CAS_LATENCY 7.22.24 7.22.23 7.22.22
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
MCB:MEM_CA_SIZE 8.22.31 8.22.30
9 0 0
10 0 1
11 1 0
12 1 1
MCB:MEM_DDR1_2_ODS 6.22.19
FULL 0
REDUCED 1
MCB:MEM_DDR2_3_HIGH_TEMP_SR 5.22.25
NORMAL 0
EXTENDED 1
MCB:MEM_DDR2_3_PA_SR 5.22.20 5.22.19 5.22.18
FULL 0 0 0
HALF1 0 0 1
QUARTER1 0 1 0
EIGHTH1 0 1 1
THREEQUARTER 1 0 0
HALF2 1 0 1
QUARTER2 1 1 0
EIGHTH2 1 1 1
MCB:MEM_DDR2_ADD_LATENCY 6.22.23 6.22.22 6.22.21
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
MCB:MEM_DDR2_DIFF_DQS_EN 6.22.28
YES 0
NO 1
MCB:MEM_DDR2_RTT 6.22.24 6.22.20
NONE 0 0
75OHMS 0 1
150OHMS 1 0
50OHMS 1 1
MCB:MEM_DDR2_WRT_RECOVERY 7.22.29 7.22.28 7.22.27
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
MCB:MEM_DDR3_ADD_LATENCY 6.22.22 6.22.21
NONE 0 0
CL1 0 1
CL2 1 0
MCB:MEM_DDR3_AUTO_SR 5.22.24
MANUAL 0
ENABLED 1
MCB:MEM_DDR3_CAS_LATENCY 7.22.24 7.22.23 7.22.22
5 0 0 1
6 0 1 0
7 0 1 1
8 1 0 0
9 1 0 1
10 1 1 0
MCB:MEM_DDR3_CAS_WR_LATENCY 5.22.22 5.22.21
5 0 0
6 0 1
7 1 0
8 1 1
MCB:MEM_DDR3_DYN_WRT_ODT 5.22.28 5.22.27
NONE 0 0
DIV2 0 1
DIV4 1 0
MCB:MEM_DDR3_ODS 6.22.19
DIV6 0
DIV7 1
MCB:MEM_DDR3_RTT 6.22.27 6.22.20 6.22.24
NONE 0 0 0
DIV2 0 0 1
DIV4 0 1 0
DIV6 0 1 1
DIV8 1 0 0
DIV12 1 1 0
MCB:MEM_DDR3_WRT_RECOVERY 7.22.29 7.22.28 7.22.27
5 0 0 1
6 0 1 0
7 0 1 1
8 1 0 0
10 1 0 1
12 1 1 0
MCB:MEM_MDDR_ODS 6.22.25 6.22.23 6.22.24
FULL 0 0 0
QUARTER 0 0 1
HALF 0 1 0
THREEQUARTERS 1 0 0
MCB:MEM_MOBILE_PA_SR 6.22.18
FULL 0
HALF 1
MCB:MEM_MOBILE_TC_SR 6.22.22 6.22.21
0 0 0
1 0 1
2 1 0
3 1 1
MCB:MEM_PLL_POL_SEL 8.22.22
MCB:MUI0.MEM_PLL_POL_SEL 21.25.8
MCB:MUI0R.MEM_PLL_POL_SEL 13.25.8
MCB:MUI0W.MEM_PLL_POL_SEL 15.25.8
MCB:MUI1.MEM_PLL_POL_SEL 23.25.8
MCB:MUI1R.MEM_PLL_POL_SEL 17.25.8
MCB:MUI1W.MEM_PLL_POL_SEL 19.25.8
MCB:MUI2.MEM_PLL_POL_SEL 25.25.8
MCB:MUI3.MEM_PLL_POL_SEL 27.25.8
INVERTED 0
NOTINVERTED 1
MCB:MEM_RAS_VAL 10.22.22 10.22.21 10.22.20 10.22.19 10.22.18
non-inverted [4] [3] [2] [1] [0]
MCB:MEM_RA_SIZE 8.22.29 8.22.28
12 0 0
13 0 1
14 1 0
15 1 1
MCB:MEM_RFC_VAL 9.22.25 9.22.24 9.22.23 9.22.22 9.22.21 9.22.20 9.22.19 9.22.18
non-inverted [7] [6] [5] [4] [3] [2] [1] [0]
MCB:MEM_RP_VAL 9.22.29 9.22.28 9.22.27 9.22.26
non-inverted [3] [2] [1] [0]
MCB:MEM_TYPE 11.22.20 11.22.21
DDR3 0 0
DDR 0 1
DDR2 1 0
MDDR 1 1
MCB:MEM_WIDTH 11.22.19 11.22.18
MCB:MUI0.MEM_WIDTH 21.25.2 21.25.1
MCB:MUI0R.MEM_WIDTH 13.25.2 13.25.1
MCB:MUI0W.MEM_WIDTH 15.25.2 15.25.1
MCB:MUI1.MEM_WIDTH 23.25.2 23.25.1
MCB:MUI1R.MEM_WIDTH 17.25.2 17.25.1
MCB:MUI1W.MEM_WIDTH 19.25.2 19.25.1
MCB:MUI2.MEM_WIDTH 25.25.2 25.25.1
MCB:MUI3.MEM_WIDTH 27.25.2 27.25.1
4 0 1
8 1 0
16 1 1
MCB:MUI0R_PORT_CONFIG 13.25.0
MCB:MUI0W_PORT_CONFIG 15.25.0
MCB:MUI1R_PORT_CONFIG 17.25.0
MCB:MUI1W_PORT_CONFIG 19.25.0
MCB:MUI2_PORT_CONFIG 21.25.0
MCB:MUI3_PORT_CONFIG 23.25.0
MCB:MUI4_PORT_CONFIG 25.25.0
MCB:MUI5_PORT_CONFIG 27.25.0
WRITE 0
READ 1
MCB:PORT_CONFIG 11.22.27 11.22.26 11.22.25
B32_B32_X32_X32_X32_X32 0 0 0
B32_B32_B32_B32 0 0 1
B64_B32_B32 0 1 0
B64_B64 0 1 1
B128 1 0 0