Memory Controller Block
TODO: document
Tile MCB
Cells: 28
Bel MCB
| Pin | Direction | Wires |
|---|---|---|
| P0ARBEN | input | TCELL11:IMUX.LOGICIN29 |
| P0CMDBA0 | input | TCELL10:IMUX.LOGICIN7 |
| P0CMDBA1 | input | TCELL10:IMUX.LOGICIN36 |
| P0CMDBA2 | input | TCELL10:IMUX.LOGICIN16 |
| P0CMDBL0 | input | TCELL10:IMUX.LOGICIN57 |
| P0CMDBL1 | input | TCELL10:IMUX.LOGICIN44 |
| P0CMDBL2 | input | TCELL10:IMUX.LOGICIN4 |
| P0CMDBL3 | input | TCELL10:IMUX.LOGICIN55 |
| P0CMDBL4 | input | TCELL10:IMUX.LOGICIN26 |
| P0CMDBL5 | input | TCELL10:IMUX.LOGICIN30 |
| P0CMDCA0 | input | TCELL11:IMUX.LOGICIN7 |
| P0CMDCA1 | input | TCELL11:IMUX.LOGICIN36 |
| P0CMDCA10 | input | TCELL11:IMUX.LOGICIN4 |
| P0CMDCA11 | input | TCELL11:IMUX.LOGICIN55 |
| P0CMDCA2 | input | TCELL11:IMUX.LOGICIN12 |
| P0CMDCA3 | input | TCELL11:IMUX.LOGICIN47 |
| P0CMDCA4 | input | TCELL11:IMUX.LOGICIN45 |
| P0CMDCA5 | input | TCELL11:IMUX.LOGICIN17 |
| P0CMDCA6 | input | TCELL11:IMUX.LOGICIN23 |
| P0CMDCA7 | input | TCELL11:IMUX.LOGICIN25 |
| P0CMDCA8 | input | TCELL11:IMUX.LOGICIN57 |
| P0CMDCA9 | input | TCELL11:IMUX.LOGICIN44 |
| P0CMDCLK | input | TCELL11:IMUX.CLK1 |
| P0CMDEMPTY | output | TCELL11:OUT6.TMIN |
| P0CMDEN | input | TCELL10:IMUX.LOGICIN47 |
| P0CMDFULL | output | TCELL11:OUT3.TMIN |
| P0CMDINSTR0 | input | TCELL10:IMUX.LOGICIN20 |
| P0CMDINSTR1 | input | TCELL10:IMUX.LOGICIN17 |
| P0CMDINSTR2 | input | TCELL10:IMUX.LOGICIN34 |
| P0CMDRA0 | input | TCELL11:IMUX.LOGICIN26 |
| P0CMDRA1 | input | TCELL11:IMUX.LOGICIN30 |
| P0CMDRA10 | input | TCELL11:IMUX.LOGICIN14 |
| P0CMDRA11 | input | TCELL11:IMUX.LOGICIN37 |
| P0CMDRA12 | input | TCELL11:IMUX.LOGICIN31 |
| P0CMDRA13 | input | TCELL10:IMUX.LOGICIN24 |
| P0CMDRA14 | input | TCELL10:IMUX.LOGICIN15 |
| P0CMDRA2 | input | TCELL11:IMUX.LOGICIN10 |
| P0CMDRA3 | input | TCELL11:IMUX.LOGICIN3 |
| P0CMDRA4 | input | TCELL11:IMUX.LOGICIN1 |
| P0CMDRA5 | input | TCELL11:IMUX.LOGICIN28 |
| P0CMDRA6 | input | TCELL11:IMUX.LOGICIN27 |
| P0CMDRA7 | input | TCELL11:IMUX.LOGICIN32 |
| P0CMDRA8 | input | TCELL11:IMUX.LOGICIN59 |
| P0CMDRA9 | input | TCELL11:IMUX.LOGICIN2 |
| P0RDCLK | input | TCELL13:IMUX.CLK1 |
| P0RDCOUNT0 | output | TCELL13:OUT12.TMIN |
| P0RDCOUNT1 | output | TCELL13:OUT19.TMIN |
| P0RDCOUNT2 | output | TCELL13:OUT14.TMIN |
| P0RDCOUNT3 | output | TCELL13:OUT2.TMIN |
| P0RDCOUNT4 | output | TCELL12:OUT9.TMIN |
| P0RDCOUNT5 | output | TCELL12:OUT11.TMIN |
| P0RDCOUNT6 | output | TCELL12:OUT23.TMIN |
| P0RDDATA0 | output | TCELL12:OUT2.TMIN |
| P0RDDATA1 | output | TCELL12:OUT14.TMIN |
| P0RDDATA10 | output | TCELL12:OUT15.TMIN |
| P0RDDATA11 | output | TCELL12:OUT3.TMIN |
| P0RDDATA12 | output | TCELL12:OUT8.TMIN |
| P0RDDATA13 | output | TCELL12:OUT1.TMIN |
| P0RDDATA14 | output | TCELL12:OUT18.TMIN |
| P0RDDATA15 | output | TCELL12:OUT20.TMIN |
| P0RDDATA16 | output | TCELL12:OUT13.TMIN |
| P0RDDATA17 | output | TCELL12:OUT6.TMIN |
| P0RDDATA18 | output | TCELL13:OUT10.TMIN |
| P0RDDATA19 | output | TCELL13:OUT17.TMIN |
| P0RDDATA2 | output | TCELL12:OUT19.TMIN |
| P0RDDATA20 | output | TCELL13:OUT22.TMIN |
| P0RDDATA21 | output | TCELL13:OUT15.TMIN |
| P0RDDATA22 | output | TCELL13:OUT3.TMIN |
| P0RDDATA23 | output | TCELL13:OUT8.TMIN |
| P0RDDATA24 | output | TCELL13:OUT1.TMIN |
| P0RDDATA25 | output | TCELL13:OUT18.TMIN |
| P0RDDATA26 | output | TCELL13:OUT20.TMIN |
| P0RDDATA27 | output | TCELL13:OUT13.TMIN |
| P0RDDATA28 | output | TCELL13:OUT6.TMIN |
| P0RDDATA29 | output | TCELL13:OUT4.TMIN |
| P0RDDATA3 | output | TCELL12:OUT7.TMIN |
| P0RDDATA30 | output | TCELL13:OUT16.TMIN |
| P0RDDATA31 | output | TCELL13:OUT21.TMIN |
| P0RDDATA4 | output | TCELL12:OUT12.TMIN |
| P0RDDATA5 | output | TCELL12:OUT0.TMIN |
| P0RDDATA6 | output | TCELL12:OUT5.TMIN |
| P0RDDATA7 | output | TCELL12:OUT10.TMIN |
| P0RDDATA8 | output | TCELL12:OUT17.TMIN |
| P0RDDATA9 | output | TCELL12:OUT22.TMIN |
| P0RDEMPTY | output | TCELL13:OUT0.TMIN |
| P0RDEN | input | TCELL13:IMUX.LOGICIN7 |
| P0RDERROR | output | TCELL13:OUT7.TMIN |
| P0RDFULL | output | TCELL12:OUT4.TMIN |
| P0RDOVERFLOW | output | TCELL12:OUT16.TMIN |
| P0RTSTENB | input | TCELL12:IMUX.LOGICIN9 |
| P0RTSTMODEB0 | input | TCELL12:IMUX.LOGICIN32 |
| P0RTSTMODEB1 | input | TCELL12:IMUX.LOGICIN29 |
| P0RTSTMODEB2 | input | TCELL12:IMUX.LOGICIN1 |
| P0RTSTMODEB3 | input | TCELL12:IMUX.LOGICIN19 |
| P0RTSTPINENB | input | TCELL12:IMUX.LOGICIN59 |
| P0RTSTUDMP | output | TCELL12:OUT21.TMIN |
| P0RTSTUNDERRUN | output | TCELL13:OUT5.TMIN |
| P0RTSTWRDATA0 | input | TCELL12:IMUX.LOGICIN15 |
| P0RTSTWRDATA1 | input | TCELL12:IMUX.LOGICIN42 |
| P0RTSTWRDATA10 | input | TCELL12:IMUX.LOGICIN25 |
| P0RTSTWRDATA11 | input | TCELL12:IMUX.LOGICIN57 |
| P0RTSTWRDATA12 | input | TCELL12:IMUX.LOGICIN44 |
| P0RTSTWRDATA13 | input | TCELL12:IMUX.LOGICIN4 |
| P0RTSTWRDATA14 | input | TCELL12:IMUX.LOGICIN55 |
| P0RTSTWRDATA15 | input | TCELL12:IMUX.LOGICIN26 |
| P0RTSTWRDATA16 | input | TCELL12:IMUX.LOGICIN30 |
| P0RTSTWRDATA17 | input | TCELL12:IMUX.LOGICIN10 |
| P0RTSTWRDATA18 | input | TCELL13:IMUX.LOGICIN57 |
| P0RTSTWRDATA19 | input | TCELL13:IMUX.LOGICIN44 |
| P0RTSTWRDATA2 | input | TCELL12:IMUX.LOGICIN7 |
| P0RTSTWRDATA20 | input | TCELL13:IMUX.LOGICIN4 |
| P0RTSTWRDATA21 | input | TCELL13:IMUX.LOGICIN55 |
| P0RTSTWRDATA22 | input | TCELL13:IMUX.LOGICIN26 |
| P0RTSTWRDATA23 | input | TCELL13:IMUX.LOGICIN30 |
| P0RTSTWRDATA24 | input | TCELL13:IMUX.LOGICIN41 |
| P0RTSTWRDATA25 | input | TCELL13:IMUX.LOGICIN10 |
| P0RTSTWRDATA26 | input | TCELL13:IMUX.LOGICIN3 |
| P0RTSTWRDATA27 | input | TCELL13:IMUX.LOGICIN1 |
| P0RTSTWRDATA28 | input | TCELL13:IMUX.LOGICIN19 |
| P0RTSTWRDATA29 | input | TCELL13:IMUX.LOGICIN27 |
| P0RTSTWRDATA3 | input | TCELL12:IMUX.LOGICIN12 |
| P0RTSTWRDATA30 | input | TCELL13:IMUX.LOGICIN29 |
| P0RTSTWRDATA31 | input | TCELL13:IMUX.LOGICIN32 |
| P0RTSTWRDATA4 | input | TCELL12:IMUX.LOGICIN62 |
| P0RTSTWRDATA5 | input | TCELL12:IMUX.LOGICIN20 |
| P0RTSTWRDATA6 | input | TCELL12:IMUX.LOGICIN38 |
| P0RTSTWRDATA7 | input | TCELL12:IMUX.LOGICIN17 |
| P0RTSTWRDATA8 | input | TCELL12:IMUX.LOGICIN23 |
| P0RTSTWRDATA9 | input | TCELL12:IMUX.LOGICIN48 |
| P0RTSTWRMASK0 | input | TCELL13:IMUX.LOGICIN52 |
| P0RTSTWRMASK1 | input | TCELL13:IMUX.LOGICIN2 |
| P0RTSTWRMASK2 | input | TCELL13:IMUX.LOGICIN14 |
| P0RTSTWRMASK3 | input | TCELL13:IMUX.LOGICIN37 |
| P0RWRMASK0 | input | TCELL15:IMUX.LOGICIN52 |
| P0RWRMASK1 | input | TCELL15:IMUX.LOGICIN2 |
| P0RWRMASK2 | input | TCELL15:IMUX.LOGICIN14 |
| P0RWRMASK3 | input | TCELL15:IMUX.LOGICIN37 |
| P0WRCLK | input | TCELL15:IMUX.CLK1 |
| P0WRCOUNT0 | output | TCELL15:OUT12.TMIN |
| P0WRCOUNT1 | output | TCELL15:OUT19.TMIN |
| P0WRCOUNT2 | output | TCELL15:OUT14.TMIN |
| P0WRCOUNT3 | output | TCELL15:OUT2.TMIN |
| P0WRCOUNT4 | output | TCELL14:OUT9.TMIN |
| P0WRCOUNT5 | output | TCELL14:OUT11.TMIN |
| P0WRCOUNT6 | output | TCELL14:OUT23.TMIN |
| P0WRDATA0 | input | TCELL14:IMUX.LOGICIN15 |
| P0WRDATA1 | input | TCELL14:IMUX.LOGICIN42 |
| P0WRDATA10 | input | TCELL14:IMUX.LOGICIN25 |
| P0WRDATA11 | input | TCELL14:IMUX.LOGICIN57 |
| P0WRDATA12 | input | TCELL14:IMUX.LOGICIN44 |
| P0WRDATA13 | input | TCELL14:IMUX.LOGICIN4 |
| P0WRDATA14 | input | TCELL14:IMUX.LOGICIN55 |
| P0WRDATA15 | input | TCELL14:IMUX.LOGICIN26 |
| P0WRDATA16 | input | TCELL14:IMUX.LOGICIN30 |
| P0WRDATA17 | input | TCELL14:IMUX.LOGICIN10 |
| P0WRDATA18 | input | TCELL15:IMUX.LOGICIN57 |
| P0WRDATA19 | input | TCELL15:IMUX.LOGICIN44 |
| P0WRDATA2 | input | TCELL14:IMUX.LOGICIN7 |
| P0WRDATA20 | input | TCELL15:IMUX.LOGICIN4 |
| P0WRDATA21 | input | TCELL15:IMUX.LOGICIN55 |
| P0WRDATA22 | input | TCELL15:IMUX.LOGICIN26 |
| P0WRDATA23 | input | TCELL15:IMUX.LOGICIN30 |
| P0WRDATA24 | input | TCELL15:IMUX.LOGICIN41 |
| P0WRDATA25 | input | TCELL15:IMUX.LOGICIN10 |
| P0WRDATA26 | input | TCELL15:IMUX.LOGICIN3 |
| P0WRDATA27 | input | TCELL15:IMUX.LOGICIN1 |
| P0WRDATA28 | input | TCELL15:IMUX.LOGICIN19 |
| P0WRDATA29 | input | TCELL15:IMUX.LOGICIN27 |
| P0WRDATA3 | input | TCELL14:IMUX.LOGICIN12 |
| P0WRDATA30 | input | TCELL15:IMUX.LOGICIN29 |
| P0WRDATA31 | input | TCELL15:IMUX.LOGICIN32 |
| P0WRDATA4 | input | TCELL14:IMUX.LOGICIN62 |
| P0WRDATA5 | input | TCELL14:IMUX.LOGICIN20 |
| P0WRDATA6 | input | TCELL14:IMUX.LOGICIN38 |
| P0WRDATA7 | input | TCELL14:IMUX.LOGICIN17 |
| P0WRDATA8 | input | TCELL14:IMUX.LOGICIN23 |
| P0WRDATA9 | input | TCELL14:IMUX.LOGICIN48 |
| P0WREMPTY | output | TCELL15:OUT0.TMIN |
| P0WREN | input | TCELL15:IMUX.LOGICIN7 |
| P0WRERROR | output | TCELL15:OUT7.TMIN |
| P0WRFULL | output | TCELL14:OUT4.TMIN |
| P0WRUNDERRUN | output | TCELL15:OUT5.TMIN |
| P0WTSTDATA0 | output | TCELL14:OUT2.TMIN |
| P0WTSTDATA1 | output | TCELL14:OUT14.TMIN |
| P0WTSTDATA10 | output | TCELL14:OUT15.TMIN |
| P0WTSTDATA11 | output | TCELL14:OUT3.TMIN |
| P0WTSTDATA12 | output | TCELL14:OUT8.TMIN |
| P0WTSTDATA13 | output | TCELL14:OUT1.TMIN |
| P0WTSTDATA14 | output | TCELL14:OUT18.TMIN |
| P0WTSTDATA15 | output | TCELL14:OUT20.TMIN |
| P0WTSTDATA16 | output | TCELL14:OUT13.TMIN |
| P0WTSTDATA17 | output | TCELL14:OUT6.TMIN |
| P0WTSTDATA18 | output | TCELL15:OUT10.TMIN |
| P0WTSTDATA19 | output | TCELL15:OUT17.TMIN |
| P0WTSTDATA2 | output | TCELL14:OUT19.TMIN |
| P0WTSTDATA20 | output | TCELL15:OUT22.TMIN |
| P0WTSTDATA21 | output | TCELL15:OUT15.TMIN |
| P0WTSTDATA22 | output | TCELL15:OUT3.TMIN |
| P0WTSTDATA23 | output | TCELL15:OUT8.TMIN |
| P0WTSTDATA24 | output | TCELL15:OUT1.TMIN |
| P0WTSTDATA25 | output | TCELL15:OUT18.TMIN |
| P0WTSTDATA26 | output | TCELL15:OUT20.TMIN |
| P0WTSTDATA27 | output | TCELL15:OUT13.TMIN |
| P0WTSTDATA28 | output | TCELL15:OUT6.TMIN |
| P0WTSTDATA29 | output | TCELL15:OUT4.TMIN |
| P0WTSTDATA3 | output | TCELL14:OUT7.TMIN |
| P0WTSTDATA30 | output | TCELL15:OUT16.TMIN |
| P0WTSTDATA31 | output | TCELL15:OUT21.TMIN |
| P0WTSTDATA4 | output | TCELL14:OUT12.TMIN |
| P0WTSTDATA5 | output | TCELL14:OUT0.TMIN |
| P0WTSTDATA6 | output | TCELL14:OUT5.TMIN |
| P0WTSTDATA7 | output | TCELL14:OUT10.TMIN |
| P0WTSTDATA8 | output | TCELL14:OUT17.TMIN |
| P0WTSTDATA9 | output | TCELL14:OUT22.TMIN |
| P0WTSTENB | input | TCELL14:IMUX.LOGICIN9 |
| P0WTSTLDMP | output | TCELL14:OUT21.TMIN |
| P0WTSTMODEB0 | input | TCELL14:IMUX.LOGICIN32 |
| P0WTSTMODEB1 | input | TCELL14:IMUX.LOGICIN29 |
| P0WTSTMODEB2 | input | TCELL14:IMUX.LOGICIN1 |
| P0WTSTMODEB3 | input | TCELL14:IMUX.LOGICIN19 |
| P0WTSTOVERFLOW | output | TCELL14:OUT16.TMIN |
| P0WTSTPINENB | input | TCELL14:IMUX.LOGICIN59 |
| P1ARBEN | input | TCELL9:IMUX.LOGICIN29 |
| P1CMDBA0 | input | TCELL8:IMUX.LOGICIN7 |
| P1CMDBA1 | input | TCELL8:IMUX.LOGICIN36 |
| P1CMDBA2 | input | TCELL8:IMUX.LOGICIN16 |
| P1CMDBL0 | input | TCELL8:IMUX.LOGICIN57 |
| P1CMDBL1 | input | TCELL8:IMUX.LOGICIN44 |
| P1CMDBL2 | input | TCELL8:IMUX.LOGICIN4 |
| P1CMDBL3 | input | TCELL8:IMUX.LOGICIN55 |
| P1CMDBL4 | input | TCELL8:IMUX.LOGICIN26 |
| P1CMDBL5 | input | TCELL8:IMUX.LOGICIN30 |
| P1CMDCA0 | input | TCELL9:IMUX.LOGICIN7 |
| P1CMDCA1 | input | TCELL9:IMUX.LOGICIN36 |
| P1CMDCA10 | input | TCELL9:IMUX.LOGICIN4 |
| P1CMDCA11 | input | TCELL9:IMUX.LOGICIN55 |
| P1CMDCA2 | input | TCELL9:IMUX.LOGICIN12 |
| P1CMDCA3 | input | TCELL9:IMUX.LOGICIN47 |
| P1CMDCA4 | input | TCELL9:IMUX.LOGICIN45 |
| P1CMDCA5 | input | TCELL9:IMUX.LOGICIN17 |
| P1CMDCA6 | input | TCELL9:IMUX.LOGICIN23 |
| P1CMDCA7 | input | TCELL9:IMUX.LOGICIN25 |
| P1CMDCA8 | input | TCELL9:IMUX.LOGICIN57 |
| P1CMDCA9 | input | TCELL9:IMUX.LOGICIN44 |
| P1CMDCLK | input | TCELL9:IMUX.CLK1 |
| P1CMDEMPTY | output | TCELL9:OUT6.TMIN |
| P1CMDEN | input | TCELL8:IMUX.LOGICIN47 |
| P1CMDFULL | output | TCELL9:OUT3.TMIN |
| P1CMDINSTR0 | input | TCELL8:IMUX.LOGICIN20 |
| P1CMDINSTR1 | input | TCELL8:IMUX.LOGICIN17 |
| P1CMDINSTR2 | input | TCELL8:IMUX.LOGICIN34 |
| P1CMDRA0 | input | TCELL9:IMUX.LOGICIN26 |
| P1CMDRA1 | input | TCELL9:IMUX.LOGICIN30 |
| P1CMDRA10 | input | TCELL9:IMUX.LOGICIN14 |
| P1CMDRA11 | input | TCELL9:IMUX.LOGICIN37 |
| P1CMDRA12 | input | TCELL9:IMUX.LOGICIN31 |
| P1CMDRA13 | input | TCELL8:IMUX.LOGICIN24 |
| P1CMDRA14 | input | TCELL8:IMUX.LOGICIN15 |
| P1CMDRA2 | input | TCELL9:IMUX.LOGICIN10 |
| P1CMDRA3 | input | TCELL9:IMUX.LOGICIN3 |
| P1CMDRA4 | input | TCELL9:IMUX.LOGICIN1 |
| P1CMDRA5 | input | TCELL9:IMUX.LOGICIN28 |
| P1CMDRA6 | input | TCELL9:IMUX.LOGICIN27 |
| P1CMDRA7 | input | TCELL9:IMUX.LOGICIN32 |
| P1CMDRA8 | input | TCELL9:IMUX.LOGICIN59 |
| P1CMDRA9 | input | TCELL9:IMUX.LOGICIN2 |
| P1RDCLK | input | TCELL17:IMUX.CLK1 |
| P1RDCOUNT0 | output | TCELL17:OUT12.TMIN |
| P1RDCOUNT1 | output | TCELL17:OUT19.TMIN |
| P1RDCOUNT2 | output | TCELL17:OUT14.TMIN |
| P1RDCOUNT3 | output | TCELL17:OUT2.TMIN |
| P1RDCOUNT4 | output | TCELL16:OUT9.TMIN |
| P1RDCOUNT5 | output | TCELL16:OUT11.TMIN |
| P1RDCOUNT6 | output | TCELL16:OUT23.TMIN |
| P1RDDATA0 | output | TCELL16:OUT2.TMIN |
| P1RDDATA1 | output | TCELL16:OUT14.TMIN |
| P1RDDATA10 | output | TCELL16:OUT15.TMIN |
| P1RDDATA11 | output | TCELL16:OUT3.TMIN |
| P1RDDATA12 | output | TCELL16:OUT8.TMIN |
| P1RDDATA13 | output | TCELL16:OUT1.TMIN |
| P1RDDATA14 | output | TCELL16:OUT18.TMIN |
| P1RDDATA15 | output | TCELL16:OUT20.TMIN |
| P1RDDATA16 | output | TCELL16:OUT13.TMIN |
| P1RDDATA17 | output | TCELL16:OUT6.TMIN |
| P1RDDATA18 | output | TCELL17:OUT10.TMIN |
| P1RDDATA19 | output | TCELL17:OUT17.TMIN |
| P1RDDATA2 | output | TCELL16:OUT19.TMIN |
| P1RDDATA20 | output | TCELL17:OUT22.TMIN |
| P1RDDATA21 | output | TCELL17:OUT15.TMIN |
| P1RDDATA22 | output | TCELL17:OUT3.TMIN |
| P1RDDATA23 | output | TCELL17:OUT8.TMIN |
| P1RDDATA24 | output | TCELL17:OUT1.TMIN |
| P1RDDATA25 | output | TCELL17:OUT18.TMIN |
| P1RDDATA26 | output | TCELL17:OUT20.TMIN |
| P1RDDATA27 | output | TCELL17:OUT13.TMIN |
| P1RDDATA28 | output | TCELL17:OUT6.TMIN |
| P1RDDATA29 | output | TCELL17:OUT4.TMIN |
| P1RDDATA3 | output | TCELL16:OUT7.TMIN |
| P1RDDATA30 | output | TCELL17:OUT16.TMIN |
| P1RDDATA31 | output | TCELL17:OUT21.TMIN |
| P1RDDATA4 | output | TCELL16:OUT12.TMIN |
| P1RDDATA5 | output | TCELL16:OUT0.TMIN |
| P1RDDATA6 | output | TCELL16:OUT5.TMIN |
| P1RDDATA7 | output | TCELL16:OUT10.TMIN |
| P1RDDATA8 | output | TCELL16:OUT17.TMIN |
| P1RDDATA9 | output | TCELL16:OUT22.TMIN |
| P1RDEMPTY | output | TCELL17:OUT0.TMIN |
| P1RDEN | input | TCELL17:IMUX.LOGICIN7 |
| P1RDERROR | output | TCELL17:OUT7.TMIN |
| P1RDFULL | output | TCELL16:OUT4.TMIN |
| P1RDOVERFLOW | output | TCELL16:OUT16.TMIN |
| P1RTSTENB | input | TCELL16:IMUX.LOGICIN9 |
| P1RTSTMODEB0 | input | TCELL16:IMUX.LOGICIN32 |
| P1RTSTMODEB1 | input | TCELL16:IMUX.LOGICIN29 |
| P1RTSTMODEB2 | input | TCELL16:IMUX.LOGICIN1 |
| P1RTSTMODEB3 | input | TCELL16:IMUX.LOGICIN19 |
| P1RTSTPINENB | input | TCELL16:IMUX.LOGICIN59 |
| P1RTSTUDMN | output | TCELL16:OUT21.TMIN |
| P1RTSTUNDERRUN | output | TCELL17:OUT5.TMIN |
| P1RTSTWRDATA0 | input | TCELL16:IMUX.LOGICIN15 |
| P1RTSTWRDATA1 | input | TCELL16:IMUX.LOGICIN42 |
| P1RTSTWRDATA10 | input | TCELL16:IMUX.LOGICIN25 |
| P1RTSTWRDATA11 | input | TCELL16:IMUX.LOGICIN57 |
| P1RTSTWRDATA12 | input | TCELL16:IMUX.LOGICIN44 |
| P1RTSTWRDATA13 | input | TCELL16:IMUX.LOGICIN4 |
| P1RTSTWRDATA14 | input | TCELL16:IMUX.LOGICIN55 |
| P1RTSTWRDATA15 | input | TCELL16:IMUX.LOGICIN26 |
| P1RTSTWRDATA16 | input | TCELL16:IMUX.LOGICIN30 |
| P1RTSTWRDATA17 | input | TCELL16:IMUX.LOGICIN10 |
| P1RTSTWRDATA18 | input | TCELL17:IMUX.LOGICIN57 |
| P1RTSTWRDATA19 | input | TCELL17:IMUX.LOGICIN44 |
| P1RTSTWRDATA2 | input | TCELL16:IMUX.LOGICIN7 |
| P1RTSTWRDATA20 | input | TCELL17:IMUX.LOGICIN4 |
| P1RTSTWRDATA21 | input | TCELL17:IMUX.LOGICIN55 |
| P1RTSTWRDATA22 | input | TCELL17:IMUX.LOGICIN26 |
| P1RTSTWRDATA23 | input | TCELL17:IMUX.LOGICIN30 |
| P1RTSTWRDATA24 | input | TCELL17:IMUX.LOGICIN41 |
| P1RTSTWRDATA25 | input | TCELL17:IMUX.LOGICIN10 |
| P1RTSTWRDATA26 | input | TCELL17:IMUX.LOGICIN3 |
| P1RTSTWRDATA27 | input | TCELL17:IMUX.LOGICIN1 |
| P1RTSTWRDATA28 | input | TCELL17:IMUX.LOGICIN19 |
| P1RTSTWRDATA29 | input | TCELL17:IMUX.LOGICIN27 |
| P1RTSTWRDATA3 | input | TCELL16:IMUX.LOGICIN12 |
| P1RTSTWRDATA30 | input | TCELL17:IMUX.LOGICIN29 |
| P1RTSTWRDATA31 | input | TCELL17:IMUX.LOGICIN32 |
| P1RTSTWRDATA4 | input | TCELL16:IMUX.LOGICIN62 |
| P1RTSTWRDATA5 | input | TCELL16:IMUX.LOGICIN20 |
| P1RTSTWRDATA6 | input | TCELL16:IMUX.LOGICIN38 |
| P1RTSTWRDATA7 | input | TCELL16:IMUX.LOGICIN17 |
| P1RTSTWRDATA8 | input | TCELL16:IMUX.LOGICIN23 |
| P1RTSTWRDATA9 | input | TCELL16:IMUX.LOGICIN48 |
| P1RTSTWRMASK0 | input | TCELL17:IMUX.LOGICIN52 |
| P1RTSTWRMASK1 | input | TCELL17:IMUX.LOGICIN2 |
| P1RTSTWRMASK2 | input | TCELL17:IMUX.LOGICIN14 |
| P1RTSTWRMASK3 | input | TCELL17:IMUX.LOGICIN37 |
| P1RWRMASK0 | input | TCELL19:IMUX.LOGICIN52 |
| P1RWRMASK1 | input | TCELL19:IMUX.LOGICIN2 |
| P1RWRMASK2 | input | TCELL19:IMUX.LOGICIN14 |
| P1RWRMASK3 | input | TCELL19:IMUX.LOGICIN37 |
| P1WRCLK | input | TCELL19:IMUX.CLK1 |
| P1WRCOUNT0 | output | TCELL19:OUT12.TMIN |
| P1WRCOUNT1 | output | TCELL19:OUT19.TMIN |
| P1WRCOUNT2 | output | TCELL19:OUT14.TMIN |
| P1WRCOUNT3 | output | TCELL19:OUT2.TMIN |
| P1WRCOUNT4 | output | TCELL18:OUT9.TMIN |
| P1WRCOUNT5 | output | TCELL18:OUT11.TMIN |
| P1WRCOUNT6 | output | TCELL18:OUT23.TMIN |
| P1WRDATA0 | input | TCELL18:IMUX.LOGICIN15 |
| P1WRDATA1 | input | TCELL18:IMUX.LOGICIN42 |
| P1WRDATA10 | input | TCELL18:IMUX.LOGICIN25 |
| P1WRDATA11 | input | TCELL18:IMUX.LOGICIN57 |
| P1WRDATA12 | input | TCELL18:IMUX.LOGICIN44 |
| P1WRDATA13 | input | TCELL18:IMUX.LOGICIN4 |
| P1WRDATA14 | input | TCELL18:IMUX.LOGICIN55 |
| P1WRDATA15 | input | TCELL18:IMUX.LOGICIN26 |
| P1WRDATA16 | input | TCELL18:IMUX.LOGICIN30 |
| P1WRDATA17 | input | TCELL18:IMUX.LOGICIN10 |
| P1WRDATA18 | input | TCELL19:IMUX.LOGICIN57 |
| P1WRDATA19 | input | TCELL19:IMUX.LOGICIN44 |
| P1WRDATA2 | input | TCELL18:IMUX.LOGICIN7 |
| P1WRDATA20 | input | TCELL19:IMUX.LOGICIN4 |
| P1WRDATA21 | input | TCELL19:IMUX.LOGICIN55 |
| P1WRDATA22 | input | TCELL19:IMUX.LOGICIN26 |
| P1WRDATA23 | input | TCELL19:IMUX.LOGICIN30 |
| P1WRDATA24 | input | TCELL19:IMUX.LOGICIN41 |
| P1WRDATA25 | input | TCELL19:IMUX.LOGICIN10 |
| P1WRDATA26 | input | TCELL19:IMUX.LOGICIN3 |
| P1WRDATA27 | input | TCELL19:IMUX.LOGICIN1 |
| P1WRDATA28 | input | TCELL19:IMUX.LOGICIN19 |
| P1WRDATA29 | input | TCELL19:IMUX.LOGICIN27 |
| P1WRDATA3 | input | TCELL18:IMUX.LOGICIN12 |
| P1WRDATA30 | input | TCELL19:IMUX.LOGICIN29 |
| P1WRDATA31 | input | TCELL19:IMUX.LOGICIN32 |
| P1WRDATA4 | input | TCELL18:IMUX.LOGICIN62 |
| P1WRDATA5 | input | TCELL18:IMUX.LOGICIN20 |
| P1WRDATA6 | input | TCELL18:IMUX.LOGICIN38 |
| P1WRDATA7 | input | TCELL18:IMUX.LOGICIN17 |
| P1WRDATA8 | input | TCELL18:IMUX.LOGICIN23 |
| P1WRDATA9 | input | TCELL18:IMUX.LOGICIN48 |
| P1WREMPTY | output | TCELL19:OUT0.TMIN |
| P1WREN | input | TCELL19:IMUX.LOGICIN7 |
| P1WRERROR | output | TCELL19:OUT7.TMIN |
| P1WRFULL | output | TCELL18:OUT4.TMIN |
| P1WRUNDERRUN | output | TCELL19:OUT5.TMIN |
| P1WTSTDATA0 | output | TCELL18:OUT2.TMIN |
| P1WTSTDATA1 | output | TCELL18:OUT14.TMIN |
| P1WTSTDATA10 | output | TCELL18:OUT15.TMIN |
| P1WTSTDATA11 | output | TCELL18:OUT3.TMIN |
| P1WTSTDATA12 | output | TCELL18:OUT8.TMIN |
| P1WTSTDATA13 | output | TCELL18:OUT1.TMIN |
| P1WTSTDATA14 | output | TCELL18:OUT18.TMIN |
| P1WTSTDATA15 | output | TCELL18:OUT20.TMIN |
| P1WTSTDATA16 | output | TCELL18:OUT13.TMIN |
| P1WTSTDATA17 | output | TCELL18:OUT6.TMIN |
| P1WTSTDATA18 | output | TCELL19:OUT10.TMIN |
| P1WTSTDATA19 | output | TCELL19:OUT17.TMIN |
| P1WTSTDATA2 | output | TCELL18:OUT19.TMIN |
| P1WTSTDATA20 | output | TCELL19:OUT22.TMIN |
| P1WTSTDATA21 | output | TCELL19:OUT15.TMIN |
| P1WTSTDATA22 | output | TCELL19:OUT3.TMIN |
| P1WTSTDATA23 | output | TCELL19:OUT8.TMIN |
| P1WTSTDATA24 | output | TCELL19:OUT1.TMIN |
| P1WTSTDATA25 | output | TCELL19:OUT18.TMIN |
| P1WTSTDATA26 | output | TCELL19:OUT20.TMIN |
| P1WTSTDATA27 | output | TCELL19:OUT13.TMIN |
| P1WTSTDATA28 | output | TCELL19:OUT6.TMIN |
| P1WTSTDATA29 | output | TCELL19:OUT4.TMIN |
| P1WTSTDATA3 | output | TCELL18:OUT7.TMIN |
| P1WTSTDATA30 | output | TCELL19:OUT16.TMIN |
| P1WTSTDATA31 | output | TCELL19:OUT21.TMIN |
| P1WTSTDATA4 | output | TCELL18:OUT12.TMIN |
| P1WTSTDATA5 | output | TCELL18:OUT0.TMIN |
| P1WTSTDATA6 | output | TCELL18:OUT5.TMIN |
| P1WTSTDATA7 | output | TCELL18:OUT10.TMIN |
| P1WTSTDATA8 | output | TCELL18:OUT17.TMIN |
| P1WTSTDATA9 | output | TCELL18:OUT22.TMIN |
| P1WTSTENB | input | TCELL18:IMUX.LOGICIN9 |
| P1WTSTLDMN | output | TCELL18:OUT21.TMIN |
| P1WTSTMODEB0 | input | TCELL18:IMUX.LOGICIN32 |
| P1WTSTMODEB1 | input | TCELL18:IMUX.LOGICIN29 |
| P1WTSTMODEB2 | input | TCELL18:IMUX.LOGICIN1 |
| P1WTSTMODEB3 | input | TCELL18:IMUX.LOGICIN19 |
| P1WTSTOVERFLOW | output | TCELL18:OUT16.TMIN |
| P1WTSTPINENB | input | TCELL18:IMUX.LOGICIN59 |
| P2ARBEN | input | TCELL7:IMUX.LOGICIN29 |
| P2CLK | input | TCELL21:IMUX.CLK1 |
| P2CMDBA0 | input | TCELL6:IMUX.LOGICIN7 |
| P2CMDBA1 | input | TCELL6:IMUX.LOGICIN36 |
| P2CMDBA2 | input | TCELL6:IMUX.LOGICIN16 |
| P2CMDBL0 | input | TCELL6:IMUX.LOGICIN57 |
| P2CMDBL1 | input | TCELL6:IMUX.LOGICIN44 |
| P2CMDBL2 | input | TCELL6:IMUX.LOGICIN4 |
| P2CMDBL3 | input | TCELL6:IMUX.LOGICIN55 |
| P2CMDBL4 | input | TCELL6:IMUX.LOGICIN26 |
| P2CMDBL5 | input | TCELL6:IMUX.LOGICIN30 |
| P2CMDCA0 | input | TCELL7:IMUX.LOGICIN7 |
| P2CMDCA1 | input | TCELL7:IMUX.LOGICIN36 |
| P2CMDCA10 | input | TCELL7:IMUX.LOGICIN4 |
| P2CMDCA11 | input | TCELL7:IMUX.LOGICIN55 |
| P2CMDCA2 | input | TCELL7:IMUX.LOGICIN12 |
| P2CMDCA3 | input | TCELL7:IMUX.LOGICIN47 |
| P2CMDCA4 | input | TCELL7:IMUX.LOGICIN45 |
| P2CMDCA5 | input | TCELL7:IMUX.LOGICIN17 |
| P2CMDCA6 | input | TCELL7:IMUX.LOGICIN23 |
| P2CMDCA7 | input | TCELL7:IMUX.LOGICIN25 |
| P2CMDCA8 | input | TCELL7:IMUX.LOGICIN57 |
| P2CMDCA9 | input | TCELL7:IMUX.LOGICIN44 |
| P2CMDCLK | input | TCELL7:IMUX.CLK1 |
| P2CMDEMPTY | output | TCELL7:OUT6.TMIN |
| P2CMDEN | input | TCELL6:IMUX.LOGICIN47 |
| P2CMDFULL | output | TCELL7:OUT3.TMIN |
| P2CMDINSTR0 | input | TCELL6:IMUX.LOGICIN20 |
| P2CMDINSTR1 | input | TCELL6:IMUX.LOGICIN17 |
| P2CMDINSTR2 | input | TCELL6:IMUX.LOGICIN34 |
| P2CMDRA0 | input | TCELL7:IMUX.LOGICIN26 |
| P2CMDRA1 | input | TCELL7:IMUX.LOGICIN30 |
| P2CMDRA10 | input | TCELL7:IMUX.LOGICIN14 |
| P2CMDRA11 | input | TCELL7:IMUX.LOGICIN37 |
| P2CMDRA12 | input | TCELL7:IMUX.LOGICIN31 |
| P2CMDRA13 | input | TCELL6:IMUX.LOGICIN24 |
| P2CMDRA14 | input | TCELL6:IMUX.LOGICIN15 |
| P2CMDRA2 | input | TCELL7:IMUX.LOGICIN10 |
| P2CMDRA3 | input | TCELL7:IMUX.LOGICIN3 |
| P2CMDRA4 | input | TCELL7:IMUX.LOGICIN1 |
| P2CMDRA5 | input | TCELL7:IMUX.LOGICIN28 |
| P2CMDRA6 | input | TCELL7:IMUX.LOGICIN27 |
| P2CMDRA7 | input | TCELL7:IMUX.LOGICIN32 |
| P2CMDRA8 | input | TCELL7:IMUX.LOGICIN59 |
| P2CMDRA9 | input | TCELL7:IMUX.LOGICIN2 |
| P2COUNT0 | output | TCELL21:OUT12.TMIN |
| P2COUNT1 | output | TCELL21:OUT19.TMIN |
| P2COUNT2 | output | TCELL21:OUT14.TMIN |
| P2COUNT3 | output | TCELL21:OUT2.TMIN |
| P2COUNT4 | output | TCELL20:OUT9.TMIN |
| P2COUNT5 | output | TCELL20:OUT11.TMIN |
| P2COUNT6 | output | TCELL20:OUT23.TMIN |
| P2EMPTY | output | TCELL21:OUT0.TMIN |
| P2EN | input | TCELL21:IMUX.LOGICIN7 |
| P2ERROR | output | TCELL21:OUT7.TMIN |
| P2FULL | output | TCELL20:OUT4.TMIN |
| P2RDDATA0 | output | TCELL20:OUT2.TMIN |
| P2RDDATA1 | output | TCELL20:OUT14.TMIN |
| P2RDDATA10 | output | TCELL20:OUT15.TMIN |
| P2RDDATA11 | output | TCELL20:OUT3.TMIN |
| P2RDDATA12 | output | TCELL20:OUT8.TMIN |
| P2RDDATA13 | output | TCELL20:OUT1.TMIN |
| P2RDDATA14 | output | TCELL20:OUT18.TMIN |
| P2RDDATA15 | output | TCELL20:OUT20.TMIN |
| P2RDDATA16 | output | TCELL20:OUT13.TMIN |
| P2RDDATA17 | output | TCELL20:OUT6.TMIN |
| P2RDDATA18 | output | TCELL21:OUT10.TMIN |
| P2RDDATA19 | output | TCELL21:OUT17.TMIN |
| P2RDDATA2 | output | TCELL20:OUT19.TMIN |
| P2RDDATA20 | output | TCELL21:OUT22.TMIN |
| P2RDDATA21 | output | TCELL21:OUT15.TMIN |
| P2RDDATA22 | output | TCELL21:OUT3.TMIN |
| P2RDDATA23 | output | TCELL21:OUT8.TMIN |
| P2RDDATA24 | output | TCELL21:OUT1.TMIN |
| P2RDDATA25 | output | TCELL21:OUT18.TMIN |
| P2RDDATA26 | output | TCELL21:OUT20.TMIN |
| P2RDDATA27 | output | TCELL21:OUT13.TMIN |
| P2RDDATA28 | output | TCELL21:OUT6.TMIN |
| P2RDDATA29 | output | TCELL21:OUT4.TMIN |
| P2RDDATA3 | output | TCELL20:OUT7.TMIN |
| P2RDDATA30 | output | TCELL21:OUT16.TMIN |
| P2RDDATA31 | output | TCELL21:OUT21.TMIN |
| P2RDDATA4 | output | TCELL20:OUT12.TMIN |
| P2RDDATA5 | output | TCELL20:OUT0.TMIN |
| P2RDDATA6 | output | TCELL20:OUT5.TMIN |
| P2RDDATA7 | output | TCELL20:OUT10.TMIN |
| P2RDDATA8 | output | TCELL20:OUT17.TMIN |
| P2RDDATA9 | output | TCELL20:OUT22.TMIN |
| P2RDOVERFLOW | output | TCELL20:OUT16.TMIN |
| P2TSTENB | input | TCELL20:IMUX.LOGICIN9 |
| P2TSTMODEB0 | input | TCELL20:IMUX.LOGICIN32 |
| P2TSTMODEB1 | input | TCELL20:IMUX.LOGICIN29 |
| P2TSTMODEB2 | input | TCELL20:IMUX.LOGICIN1 |
| P2TSTMODEB3 | input | TCELL20:IMUX.LOGICIN19 |
| P2TSTPINENB | input | TCELL20:IMUX.LOGICIN59 |
| P2TSTUDMP | output | TCELL20:OUT21.TMIN |
| P2WRDATA0 | input | TCELL20:IMUX.LOGICIN15 |
| P2WRDATA1 | input | TCELL20:IMUX.LOGICIN42 |
| P2WRDATA10 | input | TCELL20:IMUX.LOGICIN25 |
| P2WRDATA11 | input | TCELL20:IMUX.LOGICIN57 |
| P2WRDATA12 | input | TCELL20:IMUX.LOGICIN44 |
| P2WRDATA13 | input | TCELL20:IMUX.LOGICIN4 |
| P2WRDATA14 | input | TCELL20:IMUX.LOGICIN55 |
| P2WRDATA15 | input | TCELL20:IMUX.LOGICIN26 |
| P2WRDATA16 | input | TCELL20:IMUX.LOGICIN30 |
| P2WRDATA17 | input | TCELL20:IMUX.LOGICIN10 |
| P2WRDATA18 | input | TCELL21:IMUX.LOGICIN57 |
| P2WRDATA19 | input | TCELL21:IMUX.LOGICIN44 |
| P2WRDATA2 | input | TCELL20:IMUX.LOGICIN7 |
| P2WRDATA20 | input | TCELL21:IMUX.LOGICIN4 |
| P2WRDATA21 | input | TCELL21:IMUX.LOGICIN55 |
| P2WRDATA22 | input | TCELL21:IMUX.LOGICIN26 |
| P2WRDATA23 | input | TCELL21:IMUX.LOGICIN30 |
| P2WRDATA24 | input | TCELL21:IMUX.LOGICIN41 |
| P2WRDATA25 | input | TCELL21:IMUX.LOGICIN10 |
| P2WRDATA26 | input | TCELL21:IMUX.LOGICIN3 |
| P2WRDATA27 | input | TCELL21:IMUX.LOGICIN1 |
| P2WRDATA28 | input | TCELL21:IMUX.LOGICIN19 |
| P2WRDATA29 | input | TCELL21:IMUX.LOGICIN27 |
| P2WRDATA3 | input | TCELL20:IMUX.LOGICIN12 |
| P2WRDATA30 | input | TCELL21:IMUX.LOGICIN29 |
| P2WRDATA31 | input | TCELL21:IMUX.LOGICIN32 |
| P2WRDATA4 | input | TCELL20:IMUX.LOGICIN62 |
| P2WRDATA5 | input | TCELL20:IMUX.LOGICIN20 |
| P2WRDATA6 | input | TCELL20:IMUX.LOGICIN38 |
| P2WRDATA7 | input | TCELL20:IMUX.LOGICIN17 |
| P2WRDATA8 | input | TCELL20:IMUX.LOGICIN23 |
| P2WRDATA9 | input | TCELL20:IMUX.LOGICIN48 |
| P2WRMASK0 | input | TCELL21:IMUX.LOGICIN52 |
| P2WRMASK1 | input | TCELL21:IMUX.LOGICIN2 |
| P2WRMASK2 | input | TCELL21:IMUX.LOGICIN14 |
| P2WRMASK3 | input | TCELL21:IMUX.LOGICIN37 |
| P2WRUNDERRUN | output | TCELL21:OUT5.TMIN |
| P3ARBEN | input | TCELL5:IMUX.LOGICIN29 |
| P3CLK | input | TCELL23:IMUX.CLK1 |
| P3CMDBA0 | input | TCELL4:IMUX.LOGICIN7 |
| P3CMDBA1 | input | TCELL4:IMUX.LOGICIN36 |
| P3CMDBA2 | input | TCELL4:IMUX.LOGICIN16 |
| P3CMDBL0 | input | TCELL4:IMUX.LOGICIN57 |
| P3CMDBL1 | input | TCELL4:IMUX.LOGICIN44 |
| P3CMDBL2 | input | TCELL4:IMUX.LOGICIN4 |
| P3CMDBL3 | input | TCELL4:IMUX.LOGICIN55 |
| P3CMDBL4 | input | TCELL4:IMUX.LOGICIN26 |
| P3CMDBL5 | input | TCELL4:IMUX.LOGICIN30 |
| P3CMDCA0 | input | TCELL5:IMUX.LOGICIN7 |
| P3CMDCA1 | input | TCELL5:IMUX.LOGICIN36 |
| P3CMDCA10 | input | TCELL5:IMUX.LOGICIN4 |
| P3CMDCA11 | input | TCELL5:IMUX.LOGICIN55 |
| P3CMDCA2 | input | TCELL5:IMUX.LOGICIN12 |
| P3CMDCA3 | input | TCELL5:IMUX.LOGICIN47 |
| P3CMDCA4 | input | TCELL5:IMUX.LOGICIN45 |
| P3CMDCA5 | input | TCELL5:IMUX.LOGICIN17 |
| P3CMDCA6 | input | TCELL5:IMUX.LOGICIN23 |
| P3CMDCA7 | input | TCELL5:IMUX.LOGICIN25 |
| P3CMDCA8 | input | TCELL5:IMUX.LOGICIN57 |
| P3CMDCA9 | input | TCELL5:IMUX.LOGICIN44 |
| P3CMDCLK | input | TCELL5:IMUX.CLK1 |
| P3CMDEMPTY | output | TCELL5:OUT6.TMIN |
| P3CMDEN | input | TCELL4:IMUX.LOGICIN47 |
| P3CMDFULL | output | TCELL5:OUT3.TMIN |
| P3CMDINSTR0 | input | TCELL4:IMUX.LOGICIN20 |
| P3CMDINSTR1 | input | TCELL4:IMUX.LOGICIN17 |
| P3CMDINSTR2 | input | TCELL4:IMUX.LOGICIN34 |
| P3CMDRA0 | input | TCELL5:IMUX.LOGICIN26 |
| P3CMDRA1 | input | TCELL5:IMUX.LOGICIN30 |
| P3CMDRA10 | input | TCELL5:IMUX.LOGICIN14 |
| P3CMDRA11 | input | TCELL5:IMUX.LOGICIN37 |
| P3CMDRA12 | input | TCELL5:IMUX.LOGICIN31 |
| P3CMDRA13 | input | TCELL4:IMUX.LOGICIN24 |
| P3CMDRA14 | input | TCELL4:IMUX.LOGICIN15 |
| P3CMDRA2 | input | TCELL5:IMUX.LOGICIN10 |
| P3CMDRA3 | input | TCELL5:IMUX.LOGICIN3 |
| P3CMDRA4 | input | TCELL5:IMUX.LOGICIN1 |
| P3CMDRA5 | input | TCELL5:IMUX.LOGICIN28 |
| P3CMDRA6 | input | TCELL5:IMUX.LOGICIN27 |
| P3CMDRA7 | input | TCELL5:IMUX.LOGICIN32 |
| P3CMDRA8 | input | TCELL5:IMUX.LOGICIN59 |
| P3CMDRA9 | input | TCELL5:IMUX.LOGICIN2 |
| P3COUNT0 | output | TCELL23:OUT12.TMIN |
| P3COUNT1 | output | TCELL23:OUT19.TMIN |
| P3COUNT2 | output | TCELL23:OUT14.TMIN |
| P3COUNT3 | output | TCELL23:OUT2.TMIN |
| P3COUNT4 | output | TCELL22:OUT9.TMIN |
| P3COUNT5 | output | TCELL22:OUT11.TMIN |
| P3COUNT6 | output | TCELL22:OUT23.TMIN |
| P3EMPTY | output | TCELL23:OUT0.TMIN |
| P3EN | input | TCELL23:IMUX.LOGICIN7 |
| P3ERROR | output | TCELL23:OUT7.TMIN |
| P3FULL | output | TCELL22:OUT4.TMIN |
| P3RDDATA0 | output | TCELL22:OUT2.TMIN |
| P3RDDATA1 | output | TCELL22:OUT14.TMIN |
| P3RDDATA10 | output | TCELL22:OUT15.TMIN |
| P3RDDATA11 | output | TCELL22:OUT3.TMIN |
| P3RDDATA12 | output | TCELL22:OUT8.TMIN |
| P3RDDATA13 | output | TCELL22:OUT1.TMIN |
| P3RDDATA14 | output | TCELL22:OUT18.TMIN |
| P3RDDATA15 | output | TCELL22:OUT20.TMIN |
| P3RDDATA16 | output | TCELL22:OUT13.TMIN |
| P3RDDATA17 | output | TCELL22:OUT6.TMIN |
| P3RDDATA18 | output | TCELL23:OUT10.TMIN |
| P3RDDATA19 | output | TCELL23:OUT17.TMIN |
| P3RDDATA2 | output | TCELL22:OUT19.TMIN |
| P3RDDATA20 | output | TCELL23:OUT22.TMIN |
| P3RDDATA21 | output | TCELL23:OUT15.TMIN |
| P3RDDATA22 | output | TCELL23:OUT3.TMIN |
| P3RDDATA23 | output | TCELL23:OUT8.TMIN |
| P3RDDATA24 | output | TCELL23:OUT1.TMIN |
| P3RDDATA25 | output | TCELL23:OUT18.TMIN |
| P3RDDATA26 | output | TCELL23:OUT20.TMIN |
| P3RDDATA27 | output | TCELL23:OUT13.TMIN |
| P3RDDATA28 | output | TCELL23:OUT6.TMIN |
| P3RDDATA29 | output | TCELL23:OUT4.TMIN |
| P3RDDATA3 | output | TCELL22:OUT7.TMIN |
| P3RDDATA30 | output | TCELL23:OUT16.TMIN |
| P3RDDATA31 | output | TCELL23:OUT21.TMIN |
| P3RDDATA4 | output | TCELL22:OUT12.TMIN |
| P3RDDATA5 | output | TCELL22:OUT0.TMIN |
| P3RDDATA6 | output | TCELL22:OUT5.TMIN |
| P3RDDATA7 | output | TCELL22:OUT10.TMIN |
| P3RDDATA8 | output | TCELL22:OUT17.TMIN |
| P3RDDATA9 | output | TCELL22:OUT22.TMIN |
| P3RDOVERFLOW | output | TCELL22:OUT16.TMIN |
| P3TSTENB | input | TCELL22:IMUX.LOGICIN9 |
| P3TSTLDMP | output | TCELL22:OUT21.TMIN |
| P3TSTMODEB0 | input | TCELL22:IMUX.LOGICIN32 |
| P3TSTMODEB1 | input | TCELL22:IMUX.LOGICIN29 |
| P3TSTMODEB2 | input | TCELL22:IMUX.LOGICIN1 |
| P3TSTMODEB3 | input | TCELL22:IMUX.LOGICIN19 |
| P3TSTPINENB | input | TCELL22:IMUX.LOGICIN59 |
| P3WRDATA0 | input | TCELL22:IMUX.LOGICIN15 |
| P3WRDATA1 | input | TCELL22:IMUX.LOGICIN42 |
| P3WRDATA10 | input | TCELL22:IMUX.LOGICIN25 |
| P3WRDATA11 | input | TCELL22:IMUX.LOGICIN57 |
| P3WRDATA12 | input | TCELL22:IMUX.LOGICIN44 |
| P3WRDATA13 | input | TCELL22:IMUX.LOGICIN4 |
| P3WRDATA14 | input | TCELL22:IMUX.LOGICIN55 |
| P3WRDATA15 | input | TCELL22:IMUX.LOGICIN26 |
| P3WRDATA16 | input | TCELL22:IMUX.LOGICIN30 |
| P3WRDATA17 | input | TCELL22:IMUX.LOGICIN10 |
| P3WRDATA18 | input | TCELL23:IMUX.LOGICIN57 |
| P3WRDATA19 | input | TCELL23:IMUX.LOGICIN44 |
| P3WRDATA2 | input | TCELL22:IMUX.LOGICIN7 |
| P3WRDATA20 | input | TCELL23:IMUX.LOGICIN4 |
| P3WRDATA21 | input | TCELL23:IMUX.LOGICIN55 |
| P3WRDATA22 | input | TCELL23:IMUX.LOGICIN26 |
| P3WRDATA23 | input | TCELL23:IMUX.LOGICIN30 |
| P3WRDATA24 | input | TCELL23:IMUX.LOGICIN41 |
| P3WRDATA25 | input | TCELL23:IMUX.LOGICIN10 |
| P3WRDATA26 | input | TCELL23:IMUX.LOGICIN3 |
| P3WRDATA27 | input | TCELL23:IMUX.LOGICIN1 |
| P3WRDATA28 | input | TCELL23:IMUX.LOGICIN19 |
| P3WRDATA29 | input | TCELL23:IMUX.LOGICIN27 |
| P3WRDATA3 | input | TCELL22:IMUX.LOGICIN12 |
| P3WRDATA30 | input | TCELL23:IMUX.LOGICIN29 |
| P3WRDATA31 | input | TCELL23:IMUX.LOGICIN32 |
| P3WRDATA4 | input | TCELL22:IMUX.LOGICIN62 |
| P3WRDATA5 | input | TCELL22:IMUX.LOGICIN20 |
| P3WRDATA6 | input | TCELL22:IMUX.LOGICIN38 |
| P3WRDATA7 | input | TCELL22:IMUX.LOGICIN17 |
| P3WRDATA8 | input | TCELL22:IMUX.LOGICIN23 |
| P3WRDATA9 | input | TCELL22:IMUX.LOGICIN48 |
| P3WRMASK0 | input | TCELL23:IMUX.LOGICIN52 |
| P3WRMASK1 | input | TCELL23:IMUX.LOGICIN2 |
| P3WRMASK2 | input | TCELL23:IMUX.LOGICIN14 |
| P3WRMASK3 | input | TCELL23:IMUX.LOGICIN37 |
| P3WRUNDERRUN | output | TCELL23:OUT5.TMIN |
| P4ARBEN | input | TCELL3:IMUX.LOGICIN29 |
| P4CLK | input | TCELL25:IMUX.CLK1 |
| P4CMDBA0 | input | TCELL2:IMUX.LOGICIN7 |
| P4CMDBA1 | input | TCELL2:IMUX.LOGICIN36 |
| P4CMDBA2 | input | TCELL2:IMUX.LOGICIN16 |
| P4CMDBL0 | input | TCELL2:IMUX.LOGICIN57 |
| P4CMDBL1 | input | TCELL2:IMUX.LOGICIN44 |
| P4CMDBL2 | input | TCELL2:IMUX.LOGICIN4 |
| P4CMDBL3 | input | TCELL2:IMUX.LOGICIN55 |
| P4CMDBL4 | input | TCELL2:IMUX.LOGICIN26 |
| P4CMDBL5 | input | TCELL2:IMUX.LOGICIN30 |
| P4CMDCA0 | input | TCELL3:IMUX.LOGICIN7 |
| P4CMDCA1 | input | TCELL3:IMUX.LOGICIN36 |
| P4CMDCA10 | input | TCELL3:IMUX.LOGICIN4 |
| P4CMDCA11 | input | TCELL3:IMUX.LOGICIN55 |
| P4CMDCA2 | input | TCELL3:IMUX.LOGICIN12 |
| P4CMDCA3 | input | TCELL3:IMUX.LOGICIN47 |
| P4CMDCA4 | input | TCELL3:IMUX.LOGICIN45 |
| P4CMDCA5 | input | TCELL3:IMUX.LOGICIN17 |
| P4CMDCA6 | input | TCELL3:IMUX.LOGICIN23 |
| P4CMDCA7 | input | TCELL3:IMUX.LOGICIN25 |
| P4CMDCA8 | input | TCELL3:IMUX.LOGICIN57 |
| P4CMDCA9 | input | TCELL3:IMUX.LOGICIN44 |
| P4CMDCLK | input | TCELL3:IMUX.CLK1 |
| P4CMDEMPTY | output | TCELL3:OUT6.TMIN |
| P4CMDEN | input | TCELL2:IMUX.LOGICIN47 |
| P4CMDFULL | output | TCELL3:OUT3.TMIN |
| P4CMDINSTR0 | input | TCELL2:IMUX.LOGICIN20 |
| P4CMDINSTR1 | input | TCELL2:IMUX.LOGICIN17 |
| P4CMDINSTR2 | input | TCELL2:IMUX.LOGICIN34 |
| P4CMDRA0 | input | TCELL3:IMUX.LOGICIN26 |
| P4CMDRA1 | input | TCELL3:IMUX.LOGICIN30 |
| P4CMDRA10 | input | TCELL3:IMUX.LOGICIN14 |
| P4CMDRA11 | input | TCELL3:IMUX.LOGICIN37 |
| P4CMDRA12 | input | TCELL3:IMUX.LOGICIN31 |
| P4CMDRA13 | input | TCELL2:IMUX.LOGICIN24 |
| P4CMDRA14 | input | TCELL2:IMUX.LOGICIN15 |
| P4CMDRA2 | input | TCELL3:IMUX.LOGICIN10 |
| P4CMDRA3 | input | TCELL3:IMUX.LOGICIN3 |
| P4CMDRA4 | input | TCELL3:IMUX.LOGICIN1 |
| P4CMDRA5 | input | TCELL3:IMUX.LOGICIN28 |
| P4CMDRA6 | input | TCELL3:IMUX.LOGICIN27 |
| P4CMDRA7 | input | TCELL3:IMUX.LOGICIN32 |
| P4CMDRA8 | input | TCELL3:IMUX.LOGICIN59 |
| P4CMDRA9 | input | TCELL3:IMUX.LOGICIN2 |
| P4COUNT0 | output | TCELL25:OUT12.TMIN |
| P4COUNT1 | output | TCELL25:OUT19.TMIN |
| P4COUNT2 | output | TCELL25:OUT14.TMIN |
| P4COUNT3 | output | TCELL25:OUT2.TMIN |
| P4COUNT4 | output | TCELL24:OUT9.TMIN |
| P4COUNT5 | output | TCELL24:OUT11.TMIN |
| P4COUNT6 | output | TCELL24:OUT23.TMIN |
| P4EMPTY | output | TCELL25:OUT0.TMIN |
| P4EN | input | TCELL25:IMUX.LOGICIN7 |
| P4ERROR | output | TCELL25:OUT7.TMIN |
| P4FULL | output | TCELL24:OUT4.TMIN |
| P4RDDATA0 | output | TCELL24:OUT2.TMIN |
| P4RDDATA1 | output | TCELL24:OUT14.TMIN |
| P4RDDATA10 | output | TCELL24:OUT15.TMIN |
| P4RDDATA11 | output | TCELL24:OUT3.TMIN |
| P4RDDATA12 | output | TCELL24:OUT8.TMIN |
| P4RDDATA13 | output | TCELL24:OUT1.TMIN |
| P4RDDATA14 | output | TCELL24:OUT18.TMIN |
| P4RDDATA15 | output | TCELL24:OUT20.TMIN |
| P4RDDATA16 | output | TCELL24:OUT13.TMIN |
| P4RDDATA17 | output | TCELL24:OUT6.TMIN |
| P4RDDATA18 | output | TCELL25:OUT10.TMIN |
| P4RDDATA19 | output | TCELL25:OUT17.TMIN |
| P4RDDATA2 | output | TCELL24:OUT19.TMIN |
| P4RDDATA20 | output | TCELL25:OUT22.TMIN |
| P4RDDATA21 | output | TCELL25:OUT15.TMIN |
| P4RDDATA22 | output | TCELL25:OUT3.TMIN |
| P4RDDATA23 | output | TCELL25:OUT8.TMIN |
| P4RDDATA24 | output | TCELL25:OUT1.TMIN |
| P4RDDATA25 | output | TCELL25:OUT18.TMIN |
| P4RDDATA26 | output | TCELL25:OUT20.TMIN |
| P4RDDATA27 | output | TCELL25:OUT13.TMIN |
| P4RDDATA28 | output | TCELL25:OUT6.TMIN |
| P4RDDATA29 | output | TCELL25:OUT4.TMIN |
| P4RDDATA3 | output | TCELL24:OUT7.TMIN |
| P4RDDATA30 | output | TCELL25:OUT16.TMIN |
| P4RDDATA31 | output | TCELL25:OUT21.TMIN |
| P4RDDATA4 | output | TCELL24:OUT12.TMIN |
| P4RDDATA5 | output | TCELL24:OUT0.TMIN |
| P4RDDATA6 | output | TCELL24:OUT5.TMIN |
| P4RDDATA7 | output | TCELL24:OUT10.TMIN |
| P4RDDATA8 | output | TCELL24:OUT17.TMIN |
| P4RDDATA9 | output | TCELL24:OUT22.TMIN |
| P4RDOVERFLOW | output | TCELL24:OUT16.TMIN |
| P4TSTENB | input | TCELL24:IMUX.LOGICIN9 |
| P4TSTMODEB0 | input | TCELL24:IMUX.LOGICIN32 |
| P4TSTMODEB1 | input | TCELL24:IMUX.LOGICIN29 |
| P4TSTMODEB2 | input | TCELL24:IMUX.LOGICIN1 |
| P4TSTMODEB3 | input | TCELL24:IMUX.LOGICIN19 |
| P4TSTPINENB | input | TCELL24:IMUX.LOGICIN59 |
| P4TSTUDMN | output | TCELL24:OUT21.TMIN |
| P4WRDATA0 | input | TCELL24:IMUX.LOGICIN15 |
| P4WRDATA1 | input | TCELL24:IMUX.LOGICIN42 |
| P4WRDATA10 | input | TCELL24:IMUX.LOGICIN25 |
| P4WRDATA11 | input | TCELL24:IMUX.LOGICIN57 |
| P4WRDATA12 | input | TCELL24:IMUX.LOGICIN44 |
| P4WRDATA13 | input | TCELL24:IMUX.LOGICIN4 |
| P4WRDATA14 | input | TCELL24:IMUX.LOGICIN55 |
| P4WRDATA15 | input | TCELL24:IMUX.LOGICIN26 |
| P4WRDATA16 | input | TCELL24:IMUX.LOGICIN30 |
| P4WRDATA17 | input | TCELL24:IMUX.LOGICIN10 |
| P4WRDATA18 | input | TCELL25:IMUX.LOGICIN57 |
| P4WRDATA19 | input | TCELL25:IMUX.LOGICIN44 |
| P4WRDATA2 | input | TCELL24:IMUX.LOGICIN7 |
| P4WRDATA20 | input | TCELL25:IMUX.LOGICIN4 |
| P4WRDATA21 | input | TCELL25:IMUX.LOGICIN55 |
| P4WRDATA22 | input | TCELL25:IMUX.LOGICIN26 |
| P4WRDATA23 | input | TCELL25:IMUX.LOGICIN30 |
| P4WRDATA24 | input | TCELL25:IMUX.LOGICIN41 |
| P4WRDATA25 | input | TCELL25:IMUX.LOGICIN10 |
| P4WRDATA26 | input | TCELL25:IMUX.LOGICIN3 |
| P4WRDATA27 | input | TCELL25:IMUX.LOGICIN1 |
| P4WRDATA28 | input | TCELL25:IMUX.LOGICIN19 |
| P4WRDATA29 | input | TCELL25:IMUX.LOGICIN27 |
| P4WRDATA3 | input | TCELL24:IMUX.LOGICIN12 |
| P4WRDATA30 | input | TCELL25:IMUX.LOGICIN29 |
| P4WRDATA31 | input | TCELL25:IMUX.LOGICIN32 |
| P4WRDATA4 | input | TCELL24:IMUX.LOGICIN62 |
| P4WRDATA5 | input | TCELL24:IMUX.LOGICIN20 |
| P4WRDATA6 | input | TCELL24:IMUX.LOGICIN38 |
| P4WRDATA7 | input | TCELL24:IMUX.LOGICIN17 |
| P4WRDATA8 | input | TCELL24:IMUX.LOGICIN23 |
| P4WRDATA9 | input | TCELL24:IMUX.LOGICIN48 |
| P4WRMASK0 | input | TCELL25:IMUX.LOGICIN52 |
| P4WRMASK1 | input | TCELL25:IMUX.LOGICIN2 |
| P4WRMASK2 | input | TCELL25:IMUX.LOGICIN14 |
| P4WRMASK3 | input | TCELL25:IMUX.LOGICIN37 |
| P4WRUNDERRUN | output | TCELL25:OUT5.TMIN |
| P5ARBEN | input | TCELL1:IMUX.LOGICIN29 |
| P5CLK | input | TCELL27:IMUX.CLK1 |
| P5CMDBA0 | input | TCELL0:IMUX.LOGICIN7 |
| P5CMDBA1 | input | TCELL0:IMUX.LOGICIN36 |
| P5CMDBA2 | input | TCELL0:IMUX.LOGICIN16 |
| P5CMDBL0 | input | TCELL0:IMUX.LOGICIN57 |
| P5CMDBL1 | input | TCELL0:IMUX.LOGICIN44 |
| P5CMDBL2 | input | TCELL0:IMUX.LOGICIN4 |
| P5CMDBL3 | input | TCELL0:IMUX.LOGICIN55 |
| P5CMDBL4 | input | TCELL0:IMUX.LOGICIN26 |
| P5CMDBL5 | input | TCELL0:IMUX.LOGICIN30 |
| P5CMDCA0 | input | TCELL1:IMUX.LOGICIN7 |
| P5CMDCA1 | input | TCELL1:IMUX.LOGICIN36 |
| P5CMDCA10 | input | TCELL1:IMUX.LOGICIN4 |
| P5CMDCA11 | input | TCELL1:IMUX.LOGICIN55 |
| P5CMDCA2 | input | TCELL1:IMUX.LOGICIN12 |
| P5CMDCA3 | input | TCELL1:IMUX.LOGICIN47 |
| P5CMDCA4 | input | TCELL1:IMUX.LOGICIN45 |
| P5CMDCA5 | input | TCELL1:IMUX.LOGICIN17 |
| P5CMDCA6 | input | TCELL1:IMUX.LOGICIN23 |
| P5CMDCA7 | input | TCELL1:IMUX.LOGICIN25 |
| P5CMDCA8 | input | TCELL1:IMUX.LOGICIN57 |
| P5CMDCA9 | input | TCELL1:IMUX.LOGICIN44 |
| P5CMDCLK | input | TCELL1:IMUX.CLK1 |
| P5CMDEMPTY | output | TCELL1:OUT6.TMIN |
| P5CMDEN | input | TCELL0:IMUX.LOGICIN47 |
| P5CMDFULL | output | TCELL1:OUT3.TMIN |
| P5CMDINSTR0 | input | TCELL0:IMUX.LOGICIN20 |
| P5CMDINSTR1 | input | TCELL0:IMUX.LOGICIN17 |
| P5CMDINSTR2 | input | TCELL0:IMUX.LOGICIN34 |
| P5CMDRA0 | input | TCELL1:IMUX.LOGICIN26 |
| P5CMDRA1 | input | TCELL1:IMUX.LOGICIN30 |
| P5CMDRA10 | input | TCELL1:IMUX.LOGICIN14 |
| P5CMDRA11 | input | TCELL1:IMUX.LOGICIN37 |
| P5CMDRA12 | input | TCELL1:IMUX.LOGICIN31 |
| P5CMDRA13 | input | TCELL0:IMUX.LOGICIN24 |
| P5CMDRA14 | input | TCELL0:IMUX.LOGICIN15 |
| P5CMDRA2 | input | TCELL1:IMUX.LOGICIN10 |
| P5CMDRA3 | input | TCELL1:IMUX.LOGICIN3 |
| P5CMDRA4 | input | TCELL1:IMUX.LOGICIN1 |
| P5CMDRA5 | input | TCELL1:IMUX.LOGICIN28 |
| P5CMDRA6 | input | TCELL1:IMUX.LOGICIN27 |
| P5CMDRA7 | input | TCELL1:IMUX.LOGICIN32 |
| P5CMDRA8 | input | TCELL1:IMUX.LOGICIN59 |
| P5CMDRA9 | input | TCELL1:IMUX.LOGICIN2 |
| P5COUNT0 | output | TCELL27:OUT12.TMIN |
| P5COUNT1 | output | TCELL27:OUT19.TMIN |
| P5COUNT2 | output | TCELL27:OUT14.TMIN |
| P5COUNT3 | output | TCELL27:OUT2.TMIN |
| P5COUNT4 | output | TCELL26:OUT9.TMIN |
| P5COUNT5 | output | TCELL26:OUT11.TMIN |
| P5COUNT6 | output | TCELL26:OUT23.TMIN |
| P5EMPTY | output | TCELL27:OUT0.TMIN |
| P5EN | input | TCELL27:IMUX.LOGICIN7 |
| P5ERROR | output | TCELL27:OUT7.TMIN |
| P5FULL | output | TCELL26:OUT4.TMIN |
| P5RDDATA0 | output | TCELL26:OUT2.TMIN |
| P5RDDATA1 | output | TCELL26:OUT14.TMIN |
| P5RDDATA10 | output | TCELL26:OUT15.TMIN |
| P5RDDATA11 | output | TCELL26:OUT3.TMIN |
| P5RDDATA12 | output | TCELL26:OUT8.TMIN |
| P5RDDATA13 | output | TCELL26:OUT1.TMIN |
| P5RDDATA14 | output | TCELL26:OUT18.TMIN |
| P5RDDATA15 | output | TCELL26:OUT20.TMIN |
| P5RDDATA16 | output | TCELL26:OUT13.TMIN |
| P5RDDATA17 | output | TCELL26:OUT6.TMIN |
| P5RDDATA18 | output | TCELL27:OUT10.TMIN |
| P5RDDATA19 | output | TCELL27:OUT17.TMIN |
| P5RDDATA2 | output | TCELL26:OUT19.TMIN |
| P5RDDATA20 | output | TCELL27:OUT22.TMIN |
| P5RDDATA21 | output | TCELL27:OUT15.TMIN |
| P5RDDATA22 | output | TCELL27:OUT3.TMIN |
| P5RDDATA23 | output | TCELL27:OUT8.TMIN |
| P5RDDATA24 | output | TCELL27:OUT1.TMIN |
| P5RDDATA25 | output | TCELL27:OUT18.TMIN |
| P5RDDATA26 | output | TCELL27:OUT20.TMIN |
| P5RDDATA27 | output | TCELL27:OUT13.TMIN |
| P5RDDATA28 | output | TCELL27:OUT6.TMIN |
| P5RDDATA29 | output | TCELL27:OUT4.TMIN |
| P5RDDATA3 | output | TCELL26:OUT7.TMIN |
| P5RDDATA30 | output | TCELL27:OUT16.TMIN |
| P5RDDATA31 | output | TCELL27:OUT21.TMIN |
| P5RDDATA4 | output | TCELL26:OUT12.TMIN |
| P5RDDATA5 | output | TCELL26:OUT0.TMIN |
| P5RDDATA6 | output | TCELL26:OUT5.TMIN |
| P5RDDATA7 | output | TCELL26:OUT10.TMIN |
| P5RDDATA8 | output | TCELL26:OUT17.TMIN |
| P5RDDATA9 | output | TCELL26:OUT22.TMIN |
| P5RDOVERFLOW | output | TCELL26:OUT16.TMIN |
| P5TSTENB | input | TCELL26:IMUX.LOGICIN9 |
| P5TSTLDMN | output | TCELL26:OUT21.TMIN |
| P5TSTMODEB0 | input | TCELL26:IMUX.LOGICIN32 |
| P5TSTMODEB1 | input | TCELL26:IMUX.LOGICIN29 |
| P5TSTMODEB2 | input | TCELL26:IMUX.LOGICIN1 |
| P5TSTMODEB3 | input | TCELL26:IMUX.LOGICIN19 |
| P5TSTPINENB | input | TCELL26:IMUX.LOGICIN59 |
| P5WRDATA0 | input | TCELL26:IMUX.LOGICIN15 |
| P5WRDATA1 | input | TCELL26:IMUX.LOGICIN42 |
| P5WRDATA10 | input | TCELL26:IMUX.LOGICIN25 |
| P5WRDATA11 | input | TCELL26:IMUX.LOGICIN57 |
| P5WRDATA12 | input | TCELL26:IMUX.LOGICIN44 |
| P5WRDATA13 | input | TCELL26:IMUX.LOGICIN4 |
| P5WRDATA14 | input | TCELL26:IMUX.LOGICIN55 |
| P5WRDATA15 | input | TCELL26:IMUX.LOGICIN26 |
| P5WRDATA16 | input | TCELL26:IMUX.LOGICIN30 |
| P5WRDATA17 | input | TCELL26:IMUX.LOGICIN10 |
| P5WRDATA18 | input | TCELL27:IMUX.LOGICIN57 |
| P5WRDATA19 | input | TCELL27:IMUX.LOGICIN44 |
| P5WRDATA2 | input | TCELL26:IMUX.LOGICIN7 |
| P5WRDATA20 | input | TCELL27:IMUX.LOGICIN4 |
| P5WRDATA21 | input | TCELL27:IMUX.LOGICIN55 |
| P5WRDATA22 | input | TCELL27:IMUX.LOGICIN26 |
| P5WRDATA23 | input | TCELL27:IMUX.LOGICIN30 |
| P5WRDATA24 | input | TCELL27:IMUX.LOGICIN41 |
| P5WRDATA25 | input | TCELL27:IMUX.LOGICIN10 |
| P5WRDATA26 | input | TCELL27:IMUX.LOGICIN3 |
| P5WRDATA27 | input | TCELL27:IMUX.LOGICIN1 |
| P5WRDATA28 | input | TCELL27:IMUX.LOGICIN19 |
| P5WRDATA29 | input | TCELL27:IMUX.LOGICIN27 |
| P5WRDATA3 | input | TCELL26:IMUX.LOGICIN12 |
| P5WRDATA30 | input | TCELL27:IMUX.LOGICIN29 |
| P5WRDATA31 | input | TCELL27:IMUX.LOGICIN32 |
| P5WRDATA4 | input | TCELL26:IMUX.LOGICIN62 |
| P5WRDATA5 | input | TCELL26:IMUX.LOGICIN20 |
| P5WRDATA6 | input | TCELL26:IMUX.LOGICIN38 |
| P5WRDATA7 | input | TCELL26:IMUX.LOGICIN17 |
| P5WRDATA8 | input | TCELL26:IMUX.LOGICIN23 |
| P5WRDATA9 | input | TCELL26:IMUX.LOGICIN48 |
| P5WRMASK0 | input | TCELL27:IMUX.LOGICIN52 |
| P5WRMASK1 | input | TCELL27:IMUX.LOGICIN2 |
| P5WRMASK2 | input | TCELL27:IMUX.LOGICIN14 |
| P5WRMASK3 | input | TCELL27:IMUX.LOGICIN37 |
| P5WRUNDERRUN | output | TCELL27:OUT5.TMIN |
| PLLLOCK | input | TCELL11:IMUX.LOGICIN24 |
| RECAL | input | TCELL8:IMUX.LOGICIN14 |
| SELFREFRESHENTER | input | TCELL8:IMUX.LOGICIN37 |
| SELFREFRESHMODE | output | TCELL8:OUT11.TMIN |
| STATUS0 | output | TCELL4:OUT2.TMIN |
| STATUS1 | output | TCELL4:OUT19.TMIN |
| STATUS10 | output | TCELL4:OUT16.TMIN |
| STATUS11 | output | TCELL4:OUT23.TMIN |
| STATUS12 | output | TCELL4:OUT11.TMIN |
| STATUS13 | output | TCELL3:OUT2.TMIN |
| STATUS14 | output | TCELL3:OUT19.TMIN |
| STATUS15 | output | TCELL3:OUT7.TMIN |
| STATUS16 | output | TCELL3:OUT12.TMIN |
| STATUS17 | output | TCELL3:OUT5.TMIN |
| STATUS18 | output | TCELL3:OUT10.TMIN |
| STATUS19 | output | TCELL3:OUT17.TMIN |
| STATUS2 | output | TCELL4:OUT7.TMIN |
| STATUS20 | output | TCELL3:OUT22.TMIN |
| STATUS21 | output | TCELL3:OUT15.TMIN |
| STATUS22 | output | TCELL3:OUT13.TMIN |
| STATUS23 | output | TCELL3:OUT16.TMIN |
| STATUS24 | output | TCELL3:OUT23.TMIN |
| STATUS25 | output | TCELL3:OUT11.TMIN |
| STATUS26 | output | TCELL2:OUT2.TMIN |
| STATUS27 | output | TCELL2:OUT19.TMIN |
| STATUS28 | output | TCELL2:OUT7.TMIN |
| STATUS29 | output | TCELL2:OUT12.TMIN |
| STATUS3 | output | TCELL4:OUT12.TMIN |
| STATUS30 | output | TCELL2:OUT5.TMIN |
| STATUS31 | output | TCELL2:OUT10.TMIN |
| STATUS4 | output | TCELL4:OUT5.TMIN |
| STATUS5 | output | TCELL4:OUT10.TMIN |
| STATUS6 | output | TCELL4:OUT17.TMIN |
| STATUS7 | output | TCELL4:OUT22.TMIN |
| STATUS8 | output | TCELL4:OUT15.TMIN |
| STATUS9 | output | TCELL4:OUT13.TMIN |
| SYSRST | input | TCELL11:IMUX.SR0 |
| TSTCMDOUT0 | output | TCELL7:OUT2.TMIN |
| TSTCMDOUT1 | output | TCELL7:OUT19.TMIN |
| TSTCMDOUT10 | output | TCELL7:OUT16.TMIN |
| TSTCMDOUT11 | output | TCELL7:OUT23.TMIN |
| TSTCMDOUT12 | output | TCELL7:OUT11.TMIN |
| TSTCMDOUT13 | output | TCELL6:OUT2.TMIN |
| TSTCMDOUT14 | output | TCELL6:OUT19.TMIN |
| TSTCMDOUT15 | output | TCELL6:OUT7.TMIN |
| TSTCMDOUT16 | output | TCELL6:OUT12.TMIN |
| TSTCMDOUT17 | output | TCELL6:OUT5.TMIN |
| TSTCMDOUT18 | output | TCELL6:OUT10.TMIN |
| TSTCMDOUT19 | output | TCELL6:OUT17.TMIN |
| TSTCMDOUT2 | output | TCELL7:OUT7.TMIN |
| TSTCMDOUT20 | output | TCELL6:OUT22.TMIN |
| TSTCMDOUT21 | output | TCELL6:OUT15.TMIN |
| TSTCMDOUT22 | output | TCELL6:OUT13.TMIN |
| TSTCMDOUT23 | output | TCELL6:OUT16.TMIN |
| TSTCMDOUT24 | output | TCELL6:OUT23.TMIN |
| TSTCMDOUT25 | output | TCELL6:OUT11.TMIN |
| TSTCMDOUT26 | output | TCELL5:OUT2.TMIN |
| TSTCMDOUT27 | output | TCELL5:OUT19.TMIN |
| TSTCMDOUT28 | output | TCELL5:OUT7.TMIN |
| TSTCMDOUT29 | output | TCELL5:OUT12.TMIN |
| TSTCMDOUT3 | output | TCELL7:OUT12.TMIN |
| TSTCMDOUT30 | output | TCELL5:OUT5.TMIN |
| TSTCMDOUT31 | output | TCELL5:OUT10.TMIN |
| TSTCMDOUT32 | output | TCELL5:OUT17.TMIN |
| TSTCMDOUT33 | output | TCELL5:OUT22.TMIN |
| TSTCMDOUT34 | output | TCELL5:OUT15.TMIN |
| TSTCMDOUT35 | output | TCELL5:OUT13.TMIN |
| TSTCMDOUT36 | output | TCELL5:OUT16.TMIN |
| TSTCMDOUT37 | output | TCELL5:OUT23.TMIN |
| TSTCMDOUT38 | output | TCELL5:OUT11.TMIN |
| TSTCMDOUT4 | output | TCELL7:OUT5.TMIN |
| TSTCMDOUT5 | output | TCELL7:OUT10.TMIN |
| TSTCMDOUT6 | output | TCELL7:OUT17.TMIN |
| TSTCMDOUT7 | output | TCELL7:OUT22.TMIN |
| TSTCMDOUT8 | output | TCELL7:OUT15.TMIN |
| TSTCMDOUT9 | output | TCELL7:OUT13.TMIN |
| TSTCMDTESTENB | input | TCELL6:IMUX.LOGICIN3 |
| TSTINB0 | input | TCELL4:IMUX.LOGICIN48 |
| TSTINB1 | input | TCELL4:IMUX.LOGICIN58 |
| TSTINB10 | input | TCELL3:IMUX.LOGICIN19 |
| TSTINB11 | input | TCELL3:IMUX.LOGICIN41 |
| TSTINB12 | input | TCELL3:IMUX.LOGICIN52 |
| TSTINB13 | input | TCELL3:IMUX.LOGICIN9 |
| TSTINB14 | input | TCELL3:IMUX.LOGICIN39 |
| TSTINB15 | input | TCELL3:IMUX.LOGICIN8 |
| TSTINB2 | input | TCELL4:IMUX.LOGICIN19 |
| TSTINB3 | input | TCELL4:IMUX.LOGICIN41 |
| TSTINB4 | input | TCELL4:IMUX.LOGICIN52 |
| TSTINB5 | input | TCELL4:IMUX.LOGICIN9 |
| TSTINB6 | input | TCELL4:IMUX.LOGICIN39 |
| TSTINB7 | input | TCELL4:IMUX.LOGICIN8 |
| TSTINB8 | input | TCELL3:IMUX.LOGICIN48 |
| TSTINB9 | input | TCELL3:IMUX.LOGICIN58 |
| TSTSCANCLK | input | TCELL0:IMUX.LOGICIN10 |
| TSTSCANENB | input | TCELL0:IMUX.LOGICIN3 |
| TSTSCANIN | input | TCELL0:IMUX.LOGICIN14 |
| TSTSCANMODE | input | TCELL0:IMUX.LOGICIN37 |
| TSTSCANOUT | output | TCELL0:OUT11.TMIN |
| TSTSCANRST | input | TCELL0:IMUX.LOGICIN59 |
| TSTSCANSET | input | TCELL0:IMUX.LOGICIN9 |
| TSTSEL0 | input | TCELL6:IMUX.LOGICIN10 |
| TSTSEL1 | input | TCELL6:IMUX.LOGICIN58 |
| TSTSEL2 | input | TCELL6:IMUX.LOGICIN19 |
| TSTSEL3 | input | TCELL6:IMUX.LOGICIN32 |
| TSTSEL4 | input | TCELL6:IMUX.LOGICIN9 |
| TSTSEL5 | input | TCELL6:IMUX.LOGICIN2 |
| TSTSEL6 | input | TCELL6:IMUX.LOGICIN14 |
| TSTSEL7 | input | TCELL6:IMUX.LOGICIN31 |
| UIADD | input | TCELL10:IMUX.LOGICIN3 |
| UIADDR0 | input | TCELL10:IMUX.LOGICIN1 |
| UIADDR1 | input | TCELL10:IMUX.LOGICIN19 |
| UIADDR2 | input | TCELL10:IMUX.LOGICIN27 |
| UIADDR3 | input | TCELL10:IMUX.LOGICIN29 |
| UIADDR4 | input | TCELL10:IMUX.LOGICIN59 |
| UIBROADCAST | input | TCELL10:IMUX.LOGICIN14 |
| UICLK | input | TCELL10:IMUX.CLK0 |
| UICMD | input | TCELL8:IMUX.LOGICIN27 |
| UICMDEN | input | TCELL8:IMUX.LOGICIN9 |
| UICMDIN | input | TCELL8:IMUX.LOGICIN52 |
| UICS | input | TCELL10:IMUX.LOGICIN10 |
| UIDONECAL | input | TCELL8:IMUX.LOGICIN2 |
| UIDQCOUNT0 | input | TCELL8:IMUX.LOGICIN10 |
| UIDQCOUNT1 | input | TCELL8:IMUX.LOGICIN3 |
| UIDQCOUNT2 | input | TCELL8:IMUX.LOGICIN1 |
| UIDQCOUNT3 | input | TCELL8:IMUX.LOGICIN19 |
| UIDQLOWERDEC | input | TCELL2:IMUX.LOGICIN41 |
| UIDQLOWERINC | input | TCELL8:IMUX.LOGICIN31 |
| UIDQUPPERDEC | input | TCELL2:IMUX.LOGICIN27 |
| UIDQUPPERINC | input | TCELL2:IMUX.LOGICIN3 |
| UIDRPUPDATE | input | TCELL10:IMUX.LOGICIN37 |
| UILDQSDEC | input | TCELL8:IMUX.LOGICIN29 |
| UILDQSINC | input | TCELL8:IMUX.LOGICIN59 |
| UIREAD | input | TCELL10:IMUX.LOGICIN2 |
| UISDI | input | TCELL10:IMUX.LOGICIN9 |
| UIUDQSDEC | input | TCELL2:IMUX.LOGICIN14 |
| UIUDQSINC | input | TCELL2:IMUX.LOGICIN32 |
| UOCALSTART | output | TCELL10:OUT2.TMIN |
| UOCMDREADYIN | output | TCELL10:OUT7.TMIN |
| UODATA0 | output | TCELL9:OUT7.TMIN |
| UODATA1 | output | TCELL9:OUT0.TMIN |
| UODATA2 | output | TCELL9:OUT10.TMIN |
| UODATA3 | output | TCELL9:OUT22.TMIN |
| UODATA4 | output | TCELL9:OUT8.TMIN |
| UODATA5 | output | TCELL9:OUT20.TMIN |
| UODATA6 | output | TCELL9:OUT16.TMIN |
| UODATA7 | output | TCELL9:OUT11.TMIN |
| UODATAVALID | output | TCELL10:OUT22.TMIN |
| UODONECAL | output | TCELL10:OUT5.TMIN |
| UOREFRSHFLAG | output | TCELL8:OUT19.TMIN |
| UOSDO | output | TCELL10:OUT16.TMIN |
Bel MCB_TIE_CLK
| Pin | Direction | Wires |
|---|
Bel MCB_TIE_DQS0
| Pin | Direction | Wires |
|---|
Bel MCB_TIE_DQS1
| Pin | Direction | Wires |
|---|
Bel TIEOFF_CLK
| Pin | Direction | Wires |
|---|
Bel TIEOFF_DQS0
| Pin | Direction | Wires |
|---|
Bel TIEOFF_DQS1
| Pin | Direction | Wires |
|---|
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:IMUX.LOGICIN3 | MCB.TSTSCANENB |
| TCELL0:IMUX.LOGICIN4 | MCB.P5CMDBL2 |
| TCELL0:IMUX.LOGICIN7 | MCB.P5CMDBA0 |
| TCELL0:IMUX.LOGICIN9 | MCB.TSTSCANSET |
| TCELL0:IMUX.LOGICIN10 | MCB.TSTSCANCLK |
| TCELL0:IMUX.LOGICIN14 | MCB.TSTSCANIN |
| TCELL0:IMUX.LOGICIN15 | MCB.P5CMDRA14 |
| TCELL0:IMUX.LOGICIN16 | MCB.P5CMDBA2 |
| TCELL0:IMUX.LOGICIN17 | MCB.P5CMDINSTR1 |
| TCELL0:IMUX.LOGICIN20 | MCB.P5CMDINSTR0 |
| TCELL0:IMUX.LOGICIN24 | MCB.P5CMDRA13 |
| TCELL0:IMUX.LOGICIN26 | MCB.P5CMDBL4 |
| TCELL0:IMUX.LOGICIN30 | MCB.P5CMDBL5 |
| TCELL0:IMUX.LOGICIN34 | MCB.P5CMDINSTR2 |
| TCELL0:IMUX.LOGICIN36 | MCB.P5CMDBA1 |
| TCELL0:IMUX.LOGICIN37 | MCB.TSTSCANMODE |
| TCELL0:IMUX.LOGICIN44 | MCB.P5CMDBL1 |
| TCELL0:IMUX.LOGICIN47 | MCB.P5CMDEN |
| TCELL0:IMUX.LOGICIN55 | MCB.P5CMDBL3 |
| TCELL0:IMUX.LOGICIN57 | MCB.P5CMDBL0 |
| TCELL0:IMUX.LOGICIN59 | MCB.TSTSCANRST |
| TCELL0:OUT11.TMIN | MCB.TSTSCANOUT |
| TCELL1:IMUX.CLK1 | MCB.P5CMDCLK |
| TCELL1:IMUX.LOGICIN1 | MCB.P5CMDRA4 |
| TCELL1:IMUX.LOGICIN2 | MCB.P5CMDRA9 |
| TCELL1:IMUX.LOGICIN3 | MCB.P5CMDRA3 |
| TCELL1:IMUX.LOGICIN4 | MCB.P5CMDCA10 |
| TCELL1:IMUX.LOGICIN7 | MCB.P5CMDCA0 |
| TCELL1:IMUX.LOGICIN10 | MCB.P5CMDRA2 |
| TCELL1:IMUX.LOGICIN12 | MCB.P5CMDCA2 |
| TCELL1:IMUX.LOGICIN14 | MCB.P5CMDRA10 |
| TCELL1:IMUX.LOGICIN17 | MCB.P5CMDCA5 |
| TCELL1:IMUX.LOGICIN23 | MCB.P5CMDCA6 |
| TCELL1:IMUX.LOGICIN25 | MCB.P5CMDCA7 |
| TCELL1:IMUX.LOGICIN26 | MCB.P5CMDRA0 |
| TCELL1:IMUX.LOGICIN27 | MCB.P5CMDRA6 |
| TCELL1:IMUX.LOGICIN28 | MCB.P5CMDRA5 |
| TCELL1:IMUX.LOGICIN29 | MCB.P5ARBEN |
| TCELL1:IMUX.LOGICIN30 | MCB.P5CMDRA1 |
| TCELL1:IMUX.LOGICIN31 | MCB.P5CMDRA12 |
| TCELL1:IMUX.LOGICIN32 | MCB.P5CMDRA7 |
| TCELL1:IMUX.LOGICIN36 | MCB.P5CMDCA1 |
| TCELL1:IMUX.LOGICIN37 | MCB.P5CMDRA11 |
| TCELL1:IMUX.LOGICIN44 | MCB.P5CMDCA9 |
| TCELL1:IMUX.LOGICIN45 | MCB.P5CMDCA4 |
| TCELL1:IMUX.LOGICIN47 | MCB.P5CMDCA3 |
| TCELL1:IMUX.LOGICIN55 | MCB.P5CMDCA11 |
| TCELL1:IMUX.LOGICIN57 | MCB.P5CMDCA8 |
| TCELL1:IMUX.LOGICIN59 | MCB.P5CMDRA8 |
| TCELL1:OUT3.TMIN | MCB.P5CMDFULL |
| TCELL1:OUT6.TMIN | MCB.P5CMDEMPTY |
| TCELL2:IMUX.LOGICIN3 | MCB.UIDQUPPERINC |
| TCELL2:IMUX.LOGICIN4 | MCB.P4CMDBL2 |
| TCELL2:IMUX.LOGICIN7 | MCB.P4CMDBA0 |
| TCELL2:IMUX.LOGICIN14 | MCB.UIUDQSDEC |
| TCELL2:IMUX.LOGICIN15 | MCB.P4CMDRA14 |
| TCELL2:IMUX.LOGICIN16 | MCB.P4CMDBA2 |
| TCELL2:IMUX.LOGICIN17 | MCB.P4CMDINSTR1 |
| TCELL2:IMUX.LOGICIN20 | MCB.P4CMDINSTR0 |
| TCELL2:IMUX.LOGICIN24 | MCB.P4CMDRA13 |
| TCELL2:IMUX.LOGICIN26 | MCB.P4CMDBL4 |
| TCELL2:IMUX.LOGICIN27 | MCB.UIDQUPPERDEC |
| TCELL2:IMUX.LOGICIN30 | MCB.P4CMDBL5 |
| TCELL2:IMUX.LOGICIN32 | MCB.UIUDQSINC |
| TCELL2:IMUX.LOGICIN34 | MCB.P4CMDINSTR2 |
| TCELL2:IMUX.LOGICIN36 | MCB.P4CMDBA1 |
| TCELL2:IMUX.LOGICIN41 | MCB.UIDQLOWERDEC |
| TCELL2:IMUX.LOGICIN44 | MCB.P4CMDBL1 |
| TCELL2:IMUX.LOGICIN47 | MCB.P4CMDEN |
| TCELL2:IMUX.LOGICIN55 | MCB.P4CMDBL3 |
| TCELL2:IMUX.LOGICIN57 | MCB.P4CMDBL0 |
| TCELL2:OUT2.TMIN | MCB.STATUS26 |
| TCELL2:OUT5.TMIN | MCB.STATUS30 |
| TCELL2:OUT7.TMIN | MCB.STATUS28 |
| TCELL2:OUT10.TMIN | MCB.STATUS31 |
| TCELL2:OUT12.TMIN | MCB.STATUS29 |
| TCELL2:OUT19.TMIN | MCB.STATUS27 |
| TCELL3:IMUX.CLK1 | MCB.P4CMDCLK |
| TCELL3:IMUX.LOGICIN1 | MCB.P4CMDRA4 |
| TCELL3:IMUX.LOGICIN2 | MCB.P4CMDRA9 |
| TCELL3:IMUX.LOGICIN3 | MCB.P4CMDRA3 |
| TCELL3:IMUX.LOGICIN4 | MCB.P4CMDCA10 |
| TCELL3:IMUX.LOGICIN7 | MCB.P4CMDCA0 |
| TCELL3:IMUX.LOGICIN8 | MCB.TSTINB15 |
| TCELL3:IMUX.LOGICIN9 | MCB.TSTINB13 |
| TCELL3:IMUX.LOGICIN10 | MCB.P4CMDRA2 |
| TCELL3:IMUX.LOGICIN12 | MCB.P4CMDCA2 |
| TCELL3:IMUX.LOGICIN14 | MCB.P4CMDRA10 |
| TCELL3:IMUX.LOGICIN17 | MCB.P4CMDCA5 |
| TCELL3:IMUX.LOGICIN19 | MCB.TSTINB10 |
| TCELL3:IMUX.LOGICIN23 | MCB.P4CMDCA6 |
| TCELL3:IMUX.LOGICIN25 | MCB.P4CMDCA7 |
| TCELL3:IMUX.LOGICIN26 | MCB.P4CMDRA0 |
| TCELL3:IMUX.LOGICIN27 | MCB.P4CMDRA6 |
| TCELL3:IMUX.LOGICIN28 | MCB.P4CMDRA5 |
| TCELL3:IMUX.LOGICIN29 | MCB.P4ARBEN |
| TCELL3:IMUX.LOGICIN30 | MCB.P4CMDRA1 |
| TCELL3:IMUX.LOGICIN31 | MCB.P4CMDRA12 |
| TCELL3:IMUX.LOGICIN32 | MCB.P4CMDRA7 |
| TCELL3:IMUX.LOGICIN36 | MCB.P4CMDCA1 |
| TCELL3:IMUX.LOGICIN37 | MCB.P4CMDRA11 |
| TCELL3:IMUX.LOGICIN39 | MCB.TSTINB14 |
| TCELL3:IMUX.LOGICIN41 | MCB.TSTINB11 |
| TCELL3:IMUX.LOGICIN44 | MCB.P4CMDCA9 |
| TCELL3:IMUX.LOGICIN45 | MCB.P4CMDCA4 |
| TCELL3:IMUX.LOGICIN47 | MCB.P4CMDCA3 |
| TCELL3:IMUX.LOGICIN48 | MCB.TSTINB8 |
| TCELL3:IMUX.LOGICIN52 | MCB.TSTINB12 |
| TCELL3:IMUX.LOGICIN55 | MCB.P4CMDCA11 |
| TCELL3:IMUX.LOGICIN57 | MCB.P4CMDCA8 |
| TCELL3:IMUX.LOGICIN58 | MCB.TSTINB9 |
| TCELL3:IMUX.LOGICIN59 | MCB.P4CMDRA8 |
| TCELL3:OUT2.TMIN | MCB.STATUS13 |
| TCELL3:OUT3.TMIN | MCB.P4CMDFULL |
| TCELL3:OUT5.TMIN | MCB.STATUS17 |
| TCELL3:OUT6.TMIN | MCB.P4CMDEMPTY |
| TCELL3:OUT7.TMIN | MCB.STATUS15 |
| TCELL3:OUT10.TMIN | MCB.STATUS18 |
| TCELL3:OUT11.TMIN | MCB.STATUS25 |
| TCELL3:OUT12.TMIN | MCB.STATUS16 |
| TCELL3:OUT13.TMIN | MCB.STATUS22 |
| TCELL3:OUT15.TMIN | MCB.STATUS21 |
| TCELL3:OUT16.TMIN | MCB.STATUS23 |
| TCELL3:OUT17.TMIN | MCB.STATUS19 |
| TCELL3:OUT19.TMIN | MCB.STATUS14 |
| TCELL3:OUT22.TMIN | MCB.STATUS20 |
| TCELL3:OUT23.TMIN | MCB.STATUS24 |
| TCELL4:IMUX.LOGICIN4 | MCB.P3CMDBL2 |
| TCELL4:IMUX.LOGICIN7 | MCB.P3CMDBA0 |
| TCELL4:IMUX.LOGICIN8 | MCB.TSTINB7 |
| TCELL4:IMUX.LOGICIN9 | MCB.TSTINB5 |
| TCELL4:IMUX.LOGICIN15 | MCB.P3CMDRA14 |
| TCELL4:IMUX.LOGICIN16 | MCB.P3CMDBA2 |
| TCELL4:IMUX.LOGICIN17 | MCB.P3CMDINSTR1 |
| TCELL4:IMUX.LOGICIN19 | MCB.TSTINB2 |
| TCELL4:IMUX.LOGICIN20 | MCB.P3CMDINSTR0 |
| TCELL4:IMUX.LOGICIN24 | MCB.P3CMDRA13 |
| TCELL4:IMUX.LOGICIN26 | MCB.P3CMDBL4 |
| TCELL4:IMUX.LOGICIN30 | MCB.P3CMDBL5 |
| TCELL4:IMUX.LOGICIN34 | MCB.P3CMDINSTR2 |
| TCELL4:IMUX.LOGICIN36 | MCB.P3CMDBA1 |
| TCELL4:IMUX.LOGICIN39 | MCB.TSTINB6 |
| TCELL4:IMUX.LOGICIN41 | MCB.TSTINB3 |
| TCELL4:IMUX.LOGICIN44 | MCB.P3CMDBL1 |
| TCELL4:IMUX.LOGICIN47 | MCB.P3CMDEN |
| TCELL4:IMUX.LOGICIN48 | MCB.TSTINB0 |
| TCELL4:IMUX.LOGICIN52 | MCB.TSTINB4 |
| TCELL4:IMUX.LOGICIN55 | MCB.P3CMDBL3 |
| TCELL4:IMUX.LOGICIN57 | MCB.P3CMDBL0 |
| TCELL4:IMUX.LOGICIN58 | MCB.TSTINB1 |
| TCELL4:OUT2.TMIN | MCB.STATUS0 |
| TCELL4:OUT5.TMIN | MCB.STATUS4 |
| TCELL4:OUT7.TMIN | MCB.STATUS2 |
| TCELL4:OUT10.TMIN | MCB.STATUS5 |
| TCELL4:OUT11.TMIN | MCB.STATUS12 |
| TCELL4:OUT12.TMIN | MCB.STATUS3 |
| TCELL4:OUT13.TMIN | MCB.STATUS9 |
| TCELL4:OUT15.TMIN | MCB.STATUS8 |
| TCELL4:OUT16.TMIN | MCB.STATUS10 |
| TCELL4:OUT17.TMIN | MCB.STATUS6 |
| TCELL4:OUT19.TMIN | MCB.STATUS1 |
| TCELL4:OUT22.TMIN | MCB.STATUS7 |
| TCELL4:OUT23.TMIN | MCB.STATUS11 |
| TCELL5:IMUX.CLK1 | MCB.P3CMDCLK |
| TCELL5:IMUX.LOGICIN1 | MCB.P3CMDRA4 |
| TCELL5:IMUX.LOGICIN2 | MCB.P3CMDRA9 |
| TCELL5:IMUX.LOGICIN3 | MCB.P3CMDRA3 |
| TCELL5:IMUX.LOGICIN4 | MCB.P3CMDCA10 |
| TCELL5:IMUX.LOGICIN7 | MCB.P3CMDCA0 |
| TCELL5:IMUX.LOGICIN10 | MCB.P3CMDRA2 |
| TCELL5:IMUX.LOGICIN12 | MCB.P3CMDCA2 |
| TCELL5:IMUX.LOGICIN14 | MCB.P3CMDRA10 |
| TCELL5:IMUX.LOGICIN17 | MCB.P3CMDCA5 |
| TCELL5:IMUX.LOGICIN23 | MCB.P3CMDCA6 |
| TCELL5:IMUX.LOGICIN25 | MCB.P3CMDCA7 |
| TCELL5:IMUX.LOGICIN26 | MCB.P3CMDRA0 |
| TCELL5:IMUX.LOGICIN27 | MCB.P3CMDRA6 |
| TCELL5:IMUX.LOGICIN28 | MCB.P3CMDRA5 |
| TCELL5:IMUX.LOGICIN29 | MCB.P3ARBEN |
| TCELL5:IMUX.LOGICIN30 | MCB.P3CMDRA1 |
| TCELL5:IMUX.LOGICIN31 | MCB.P3CMDRA12 |
| TCELL5:IMUX.LOGICIN32 | MCB.P3CMDRA7 |
| TCELL5:IMUX.LOGICIN36 | MCB.P3CMDCA1 |
| TCELL5:IMUX.LOGICIN37 | MCB.P3CMDRA11 |
| TCELL5:IMUX.LOGICIN44 | MCB.P3CMDCA9 |
| TCELL5:IMUX.LOGICIN45 | MCB.P3CMDCA4 |
| TCELL5:IMUX.LOGICIN47 | MCB.P3CMDCA3 |
| TCELL5:IMUX.LOGICIN55 | MCB.P3CMDCA11 |
| TCELL5:IMUX.LOGICIN57 | MCB.P3CMDCA8 |
| TCELL5:IMUX.LOGICIN59 | MCB.P3CMDRA8 |
| TCELL5:OUT2.TMIN | MCB.TSTCMDOUT26 |
| TCELL5:OUT3.TMIN | MCB.P3CMDFULL |
| TCELL5:OUT5.TMIN | MCB.TSTCMDOUT30 |
| TCELL5:OUT6.TMIN | MCB.P3CMDEMPTY |
| TCELL5:OUT7.TMIN | MCB.TSTCMDOUT28 |
| TCELL5:OUT10.TMIN | MCB.TSTCMDOUT31 |
| TCELL5:OUT11.TMIN | MCB.TSTCMDOUT38 |
| TCELL5:OUT12.TMIN | MCB.TSTCMDOUT29 |
| TCELL5:OUT13.TMIN | MCB.TSTCMDOUT35 |
| TCELL5:OUT15.TMIN | MCB.TSTCMDOUT34 |
| TCELL5:OUT16.TMIN | MCB.TSTCMDOUT36 |
| TCELL5:OUT17.TMIN | MCB.TSTCMDOUT32 |
| TCELL5:OUT19.TMIN | MCB.TSTCMDOUT27 |
| TCELL5:OUT22.TMIN | MCB.TSTCMDOUT33 |
| TCELL5:OUT23.TMIN | MCB.TSTCMDOUT37 |
| TCELL6:IMUX.LOGICIN2 | MCB.TSTSEL5 |
| TCELL6:IMUX.LOGICIN3 | MCB.TSTCMDTESTENB |
| TCELL6:IMUX.LOGICIN4 | MCB.P2CMDBL2 |
| TCELL6:IMUX.LOGICIN7 | MCB.P2CMDBA0 |
| TCELL6:IMUX.LOGICIN9 | MCB.TSTSEL4 |
| TCELL6:IMUX.LOGICIN10 | MCB.TSTSEL0 |
| TCELL6:IMUX.LOGICIN14 | MCB.TSTSEL6 |
| TCELL6:IMUX.LOGICIN15 | MCB.P2CMDRA14 |
| TCELL6:IMUX.LOGICIN16 | MCB.P2CMDBA2 |
| TCELL6:IMUX.LOGICIN17 | MCB.P2CMDINSTR1 |
| TCELL6:IMUX.LOGICIN19 | MCB.TSTSEL2 |
| TCELL6:IMUX.LOGICIN20 | MCB.P2CMDINSTR0 |
| TCELL6:IMUX.LOGICIN24 | MCB.P2CMDRA13 |
| TCELL6:IMUX.LOGICIN26 | MCB.P2CMDBL4 |
| TCELL6:IMUX.LOGICIN30 | MCB.P2CMDBL5 |
| TCELL6:IMUX.LOGICIN31 | MCB.TSTSEL7 |
| TCELL6:IMUX.LOGICIN32 | MCB.TSTSEL3 |
| TCELL6:IMUX.LOGICIN34 | MCB.P2CMDINSTR2 |
| TCELL6:IMUX.LOGICIN36 | MCB.P2CMDBA1 |
| TCELL6:IMUX.LOGICIN44 | MCB.P2CMDBL1 |
| TCELL6:IMUX.LOGICIN47 | MCB.P2CMDEN |
| TCELL6:IMUX.LOGICIN55 | MCB.P2CMDBL3 |
| TCELL6:IMUX.LOGICIN57 | MCB.P2CMDBL0 |
| TCELL6:IMUX.LOGICIN58 | MCB.TSTSEL1 |
| TCELL6:OUT2.TMIN | MCB.TSTCMDOUT13 |
| TCELL6:OUT5.TMIN | MCB.TSTCMDOUT17 |
| TCELL6:OUT7.TMIN | MCB.TSTCMDOUT15 |
| TCELL6:OUT10.TMIN | MCB.TSTCMDOUT18 |
| TCELL6:OUT11.TMIN | MCB.TSTCMDOUT25 |
| TCELL6:OUT12.TMIN | MCB.TSTCMDOUT16 |
| TCELL6:OUT13.TMIN | MCB.TSTCMDOUT22 |
| TCELL6:OUT15.TMIN | MCB.TSTCMDOUT21 |
| TCELL6:OUT16.TMIN | MCB.TSTCMDOUT23 |
| TCELL6:OUT17.TMIN | MCB.TSTCMDOUT19 |
| TCELL6:OUT19.TMIN | MCB.TSTCMDOUT14 |
| TCELL6:OUT22.TMIN | MCB.TSTCMDOUT20 |
| TCELL6:OUT23.TMIN | MCB.TSTCMDOUT24 |
| TCELL7:IMUX.CLK1 | MCB.P2CMDCLK |
| TCELL7:IMUX.LOGICIN1 | MCB.P2CMDRA4 |
| TCELL7:IMUX.LOGICIN2 | MCB.P2CMDRA9 |
| TCELL7:IMUX.LOGICIN3 | MCB.P2CMDRA3 |
| TCELL7:IMUX.LOGICIN4 | MCB.P2CMDCA10 |
| TCELL7:IMUX.LOGICIN7 | MCB.P2CMDCA0 |
| TCELL7:IMUX.LOGICIN10 | MCB.P2CMDRA2 |
| TCELL7:IMUX.LOGICIN12 | MCB.P2CMDCA2 |
| TCELL7:IMUX.LOGICIN14 | MCB.P2CMDRA10 |
| TCELL7:IMUX.LOGICIN17 | MCB.P2CMDCA5 |
| TCELL7:IMUX.LOGICIN23 | MCB.P2CMDCA6 |
| TCELL7:IMUX.LOGICIN25 | MCB.P2CMDCA7 |
| TCELL7:IMUX.LOGICIN26 | MCB.P2CMDRA0 |
| TCELL7:IMUX.LOGICIN27 | MCB.P2CMDRA6 |
| TCELL7:IMUX.LOGICIN28 | MCB.P2CMDRA5 |
| TCELL7:IMUX.LOGICIN29 | MCB.P2ARBEN |
| TCELL7:IMUX.LOGICIN30 | MCB.P2CMDRA1 |
| TCELL7:IMUX.LOGICIN31 | MCB.P2CMDRA12 |
| TCELL7:IMUX.LOGICIN32 | MCB.P2CMDRA7 |
| TCELL7:IMUX.LOGICIN36 | MCB.P2CMDCA1 |
| TCELL7:IMUX.LOGICIN37 | MCB.P2CMDRA11 |
| TCELL7:IMUX.LOGICIN44 | MCB.P2CMDCA9 |
| TCELL7:IMUX.LOGICIN45 | MCB.P2CMDCA4 |
| TCELL7:IMUX.LOGICIN47 | MCB.P2CMDCA3 |
| TCELL7:IMUX.LOGICIN55 | MCB.P2CMDCA11 |
| TCELL7:IMUX.LOGICIN57 | MCB.P2CMDCA8 |
| TCELL7:IMUX.LOGICIN59 | MCB.P2CMDRA8 |
| TCELL7:OUT2.TMIN | MCB.TSTCMDOUT0 |
| TCELL7:OUT3.TMIN | MCB.P2CMDFULL |
| TCELL7:OUT5.TMIN | MCB.TSTCMDOUT4 |
| TCELL7:OUT6.TMIN | MCB.P2CMDEMPTY |
| TCELL7:OUT7.TMIN | MCB.TSTCMDOUT2 |
| TCELL7:OUT10.TMIN | MCB.TSTCMDOUT5 |
| TCELL7:OUT11.TMIN | MCB.TSTCMDOUT12 |
| TCELL7:OUT12.TMIN | MCB.TSTCMDOUT3 |
| TCELL7:OUT13.TMIN | MCB.TSTCMDOUT9 |
| TCELL7:OUT15.TMIN | MCB.TSTCMDOUT8 |
| TCELL7:OUT16.TMIN | MCB.TSTCMDOUT10 |
| TCELL7:OUT17.TMIN | MCB.TSTCMDOUT6 |
| TCELL7:OUT19.TMIN | MCB.TSTCMDOUT1 |
| TCELL7:OUT22.TMIN | MCB.TSTCMDOUT7 |
| TCELL7:OUT23.TMIN | MCB.TSTCMDOUT11 |
| TCELL8:IMUX.LOGICIN1 | MCB.UIDQCOUNT2 |
| TCELL8:IMUX.LOGICIN2 | MCB.UIDONECAL |
| TCELL8:IMUX.LOGICIN3 | MCB.UIDQCOUNT1 |
| TCELL8:IMUX.LOGICIN4 | MCB.P1CMDBL2 |
| TCELL8:IMUX.LOGICIN7 | MCB.P1CMDBA0 |
| TCELL8:IMUX.LOGICIN9 | MCB.UICMDEN |
| TCELL8:IMUX.LOGICIN10 | MCB.UIDQCOUNT0 |
| TCELL8:IMUX.LOGICIN14 | MCB.RECAL |
| TCELL8:IMUX.LOGICIN15 | MCB.P1CMDRA14 |
| TCELL8:IMUX.LOGICIN16 | MCB.P1CMDBA2 |
| TCELL8:IMUX.LOGICIN17 | MCB.P1CMDINSTR1 |
| TCELL8:IMUX.LOGICIN19 | MCB.UIDQCOUNT3 |
| TCELL8:IMUX.LOGICIN20 | MCB.P1CMDINSTR0 |
| TCELL8:IMUX.LOGICIN24 | MCB.P1CMDRA13 |
| TCELL8:IMUX.LOGICIN26 | MCB.P1CMDBL4 |
| TCELL8:IMUX.LOGICIN27 | MCB.UICMD |
| TCELL8:IMUX.LOGICIN29 | MCB.UILDQSDEC |
| TCELL8:IMUX.LOGICIN30 | MCB.P1CMDBL5 |
| TCELL8:IMUX.LOGICIN31 | MCB.UIDQLOWERINC |
| TCELL8:IMUX.LOGICIN34 | MCB.P1CMDINSTR2 |
| TCELL8:IMUX.LOGICIN36 | MCB.P1CMDBA1 |
| TCELL8:IMUX.LOGICIN37 | MCB.SELFREFRESHENTER |
| TCELL8:IMUX.LOGICIN44 | MCB.P1CMDBL1 |
| TCELL8:IMUX.LOGICIN47 | MCB.P1CMDEN |
| TCELL8:IMUX.LOGICIN52 | MCB.UICMDIN |
| TCELL8:IMUX.LOGICIN55 | MCB.P1CMDBL3 |
| TCELL8:IMUX.LOGICIN57 | MCB.P1CMDBL0 |
| TCELL8:IMUX.LOGICIN59 | MCB.UILDQSINC |
| TCELL8:OUT11.TMIN | MCB.SELFREFRESHMODE |
| TCELL8:OUT19.TMIN | MCB.UOREFRSHFLAG |
| TCELL9:IMUX.CLK1 | MCB.P1CMDCLK |
| TCELL9:IMUX.LOGICIN1 | MCB.P1CMDRA4 |
| TCELL9:IMUX.LOGICIN2 | MCB.P1CMDRA9 |
| TCELL9:IMUX.LOGICIN3 | MCB.P1CMDRA3 |
| TCELL9:IMUX.LOGICIN4 | MCB.P1CMDCA10 |
| TCELL9:IMUX.LOGICIN7 | MCB.P1CMDCA0 |
| TCELL9:IMUX.LOGICIN10 | MCB.P1CMDRA2 |
| TCELL9:IMUX.LOGICIN12 | MCB.P1CMDCA2 |
| TCELL9:IMUX.LOGICIN14 | MCB.P1CMDRA10 |
| TCELL9:IMUX.LOGICIN17 | MCB.P1CMDCA5 |
| TCELL9:IMUX.LOGICIN23 | MCB.P1CMDCA6 |
| TCELL9:IMUX.LOGICIN25 | MCB.P1CMDCA7 |
| TCELL9:IMUX.LOGICIN26 | MCB.P1CMDRA0 |
| TCELL9:IMUX.LOGICIN27 | MCB.P1CMDRA6 |
| TCELL9:IMUX.LOGICIN28 | MCB.P1CMDRA5 |
| TCELL9:IMUX.LOGICIN29 | MCB.P1ARBEN |
| TCELL9:IMUX.LOGICIN30 | MCB.P1CMDRA1 |
| TCELL9:IMUX.LOGICIN31 | MCB.P1CMDRA12 |
| TCELL9:IMUX.LOGICIN32 | MCB.P1CMDRA7 |
| TCELL9:IMUX.LOGICIN36 | MCB.P1CMDCA1 |
| TCELL9:IMUX.LOGICIN37 | MCB.P1CMDRA11 |
| TCELL9:IMUX.LOGICIN44 | MCB.P1CMDCA9 |
| TCELL9:IMUX.LOGICIN45 | MCB.P1CMDCA4 |
| TCELL9:IMUX.LOGICIN47 | MCB.P1CMDCA3 |
| TCELL9:IMUX.LOGICIN55 | MCB.P1CMDCA11 |
| TCELL9:IMUX.LOGICIN57 | MCB.P1CMDCA8 |
| TCELL9:IMUX.LOGICIN59 | MCB.P1CMDRA8 |
| TCELL9:OUT0.TMIN | MCB.UODATA1 |
| TCELL9:OUT3.TMIN | MCB.P1CMDFULL |
| TCELL9:OUT6.TMIN | MCB.P1CMDEMPTY |
| TCELL9:OUT7.TMIN | MCB.UODATA0 |
| TCELL9:OUT8.TMIN | MCB.UODATA4 |
| TCELL9:OUT10.TMIN | MCB.UODATA2 |
| TCELL9:OUT11.TMIN | MCB.UODATA7 |
| TCELL9:OUT16.TMIN | MCB.UODATA6 |
| TCELL9:OUT20.TMIN | MCB.UODATA5 |
| TCELL9:OUT22.TMIN | MCB.UODATA3 |
| TCELL10:IMUX.CLK0 | MCB.UICLK |
| TCELL10:IMUX.LOGICIN1 | MCB.UIADDR0 |
| TCELL10:IMUX.LOGICIN2 | MCB.UIREAD |
| TCELL10:IMUX.LOGICIN3 | MCB.UIADD |
| TCELL10:IMUX.LOGICIN4 | MCB.P0CMDBL2 |
| TCELL10:IMUX.LOGICIN7 | MCB.P0CMDBA0 |
| TCELL10:IMUX.LOGICIN9 | MCB.UISDI |
| TCELL10:IMUX.LOGICIN10 | MCB.UICS |
| TCELL10:IMUX.LOGICIN14 | MCB.UIBROADCAST |
| TCELL10:IMUX.LOGICIN15 | MCB.P0CMDRA14 |
| TCELL10:IMUX.LOGICIN16 | MCB.P0CMDBA2 |
| TCELL10:IMUX.LOGICIN17 | MCB.P0CMDINSTR1 |
| TCELL10:IMUX.LOGICIN19 | MCB.UIADDR1 |
| TCELL10:IMUX.LOGICIN20 | MCB.P0CMDINSTR0 |
| TCELL10:IMUX.LOGICIN24 | MCB.P0CMDRA13 |
| TCELL10:IMUX.LOGICIN26 | MCB.P0CMDBL4 |
| TCELL10:IMUX.LOGICIN27 | MCB.UIADDR2 |
| TCELL10:IMUX.LOGICIN29 | MCB.UIADDR3 |
| TCELL10:IMUX.LOGICIN30 | MCB.P0CMDBL5 |
| TCELL10:IMUX.LOGICIN34 | MCB.P0CMDINSTR2 |
| TCELL10:IMUX.LOGICIN36 | MCB.P0CMDBA1 |
| TCELL10:IMUX.LOGICIN37 | MCB.UIDRPUPDATE |
| TCELL10:IMUX.LOGICIN44 | MCB.P0CMDBL1 |
| TCELL10:IMUX.LOGICIN47 | MCB.P0CMDEN |
| TCELL10:IMUX.LOGICIN55 | MCB.P0CMDBL3 |
| TCELL10:IMUX.LOGICIN57 | MCB.P0CMDBL0 |
| TCELL10:IMUX.LOGICIN59 | MCB.UIADDR4 |
| TCELL10:OUT2.TMIN | MCB.UOCALSTART |
| TCELL10:OUT5.TMIN | MCB.UODONECAL |
| TCELL10:OUT7.TMIN | MCB.UOCMDREADYIN |
| TCELL10:OUT16.TMIN | MCB.UOSDO |
| TCELL10:OUT22.TMIN | MCB.UODATAVALID |
| TCELL11:IMUX.CLK1 | MCB.P0CMDCLK |
| TCELL11:IMUX.SR0 | MCB.SYSRST |
| TCELL11:IMUX.LOGICIN1 | MCB.P0CMDRA4 |
| TCELL11:IMUX.LOGICIN2 | MCB.P0CMDRA9 |
| TCELL11:IMUX.LOGICIN3 | MCB.P0CMDRA3 |
| TCELL11:IMUX.LOGICIN4 | MCB.P0CMDCA10 |
| TCELL11:IMUX.LOGICIN7 | MCB.P0CMDCA0 |
| TCELL11:IMUX.LOGICIN10 | MCB.P0CMDRA2 |
| TCELL11:IMUX.LOGICIN12 | MCB.P0CMDCA2 |
| TCELL11:IMUX.LOGICIN14 | MCB.P0CMDRA10 |
| TCELL11:IMUX.LOGICIN17 | MCB.P0CMDCA5 |
| TCELL11:IMUX.LOGICIN23 | MCB.P0CMDCA6 |
| TCELL11:IMUX.LOGICIN24 | MCB.PLLLOCK |
| TCELL11:IMUX.LOGICIN25 | MCB.P0CMDCA7 |
| TCELL11:IMUX.LOGICIN26 | MCB.P0CMDRA0 |
| TCELL11:IMUX.LOGICIN27 | MCB.P0CMDRA6 |
| TCELL11:IMUX.LOGICIN28 | MCB.P0CMDRA5 |
| TCELL11:IMUX.LOGICIN29 | MCB.P0ARBEN |
| TCELL11:IMUX.LOGICIN30 | MCB.P0CMDRA1 |
| TCELL11:IMUX.LOGICIN31 | MCB.P0CMDRA12 |
| TCELL11:IMUX.LOGICIN32 | MCB.P0CMDRA7 |
| TCELL11:IMUX.LOGICIN36 | MCB.P0CMDCA1 |
| TCELL11:IMUX.LOGICIN37 | MCB.P0CMDRA11 |
| TCELL11:IMUX.LOGICIN44 | MCB.P0CMDCA9 |
| TCELL11:IMUX.LOGICIN45 | MCB.P0CMDCA4 |
| TCELL11:IMUX.LOGICIN47 | MCB.P0CMDCA3 |
| TCELL11:IMUX.LOGICIN55 | MCB.P0CMDCA11 |
| TCELL11:IMUX.LOGICIN57 | MCB.P0CMDCA8 |
| TCELL11:IMUX.LOGICIN59 | MCB.P0CMDRA8 |
| TCELL11:OUT3.TMIN | MCB.P0CMDFULL |
| TCELL11:OUT6.TMIN | MCB.P0CMDEMPTY |
| TCELL12:IMUX.LOGICIN1 | MCB.P0RTSTMODEB2 |
| TCELL12:IMUX.LOGICIN4 | MCB.P0RTSTWRDATA13 |
| TCELL12:IMUX.LOGICIN7 | MCB.P0RTSTWRDATA2 |
| TCELL12:IMUX.LOGICIN9 | MCB.P0RTSTENB |
| TCELL12:IMUX.LOGICIN10 | MCB.P0RTSTWRDATA17 |
| TCELL12:IMUX.LOGICIN12 | MCB.P0RTSTWRDATA3 |
| TCELL12:IMUX.LOGICIN15 | MCB.P0RTSTWRDATA0 |
| TCELL12:IMUX.LOGICIN17 | MCB.P0RTSTWRDATA7 |
| TCELL12:IMUX.LOGICIN19 | MCB.P0RTSTMODEB3 |
| TCELL12:IMUX.LOGICIN20 | MCB.P0RTSTWRDATA5 |
| TCELL12:IMUX.LOGICIN23 | MCB.P0RTSTWRDATA8 |
| TCELL12:IMUX.LOGICIN25 | MCB.P0RTSTWRDATA10 |
| TCELL12:IMUX.LOGICIN26 | MCB.P0RTSTWRDATA15 |
| TCELL12:IMUX.LOGICIN29 | MCB.P0RTSTMODEB1 |
| TCELL12:IMUX.LOGICIN30 | MCB.P0RTSTWRDATA16 |
| TCELL12:IMUX.LOGICIN32 | MCB.P0RTSTMODEB0 |
| TCELL12:IMUX.LOGICIN38 | MCB.P0RTSTWRDATA6 |
| TCELL12:IMUX.LOGICIN42 | MCB.P0RTSTWRDATA1 |
| TCELL12:IMUX.LOGICIN44 | MCB.P0RTSTWRDATA12 |
| TCELL12:IMUX.LOGICIN48 | MCB.P0RTSTWRDATA9 |
| TCELL12:IMUX.LOGICIN55 | MCB.P0RTSTWRDATA14 |
| TCELL12:IMUX.LOGICIN57 | MCB.P0RTSTWRDATA11 |
| TCELL12:IMUX.LOGICIN59 | MCB.P0RTSTPINENB |
| TCELL12:IMUX.LOGICIN62 | MCB.P0RTSTWRDATA4 |
| TCELL12:OUT0.TMIN | MCB.P0RDDATA5 |
| TCELL12:OUT1.TMIN | MCB.P0RDDATA13 |
| TCELL12:OUT2.TMIN | MCB.P0RDDATA0 |
| TCELL12:OUT3.TMIN | MCB.P0RDDATA11 |
| TCELL12:OUT4.TMIN | MCB.P0RDFULL |
| TCELL12:OUT5.TMIN | MCB.P0RDDATA6 |
| TCELL12:OUT6.TMIN | MCB.P0RDDATA17 |
| TCELL12:OUT7.TMIN | MCB.P0RDDATA3 |
| TCELL12:OUT8.TMIN | MCB.P0RDDATA12 |
| TCELL12:OUT9.TMIN | MCB.P0RDCOUNT4 |
| TCELL12:OUT10.TMIN | MCB.P0RDDATA7 |
| TCELL12:OUT11.TMIN | MCB.P0RDCOUNT5 |
| TCELL12:OUT12.TMIN | MCB.P0RDDATA4 |
| TCELL12:OUT13.TMIN | MCB.P0RDDATA16 |
| TCELL12:OUT14.TMIN | MCB.P0RDDATA1 |
| TCELL12:OUT15.TMIN | MCB.P0RDDATA10 |
| TCELL12:OUT16.TMIN | MCB.P0RDOVERFLOW |
| TCELL12:OUT17.TMIN | MCB.P0RDDATA8 |
| TCELL12:OUT18.TMIN | MCB.P0RDDATA14 |
| TCELL12:OUT19.TMIN | MCB.P0RDDATA2 |
| TCELL12:OUT20.TMIN | MCB.P0RDDATA15 |
| TCELL12:OUT21.TMIN | MCB.P0RTSTUDMP |
| TCELL12:OUT22.TMIN | MCB.P0RDDATA9 |
| TCELL12:OUT23.TMIN | MCB.P0RDCOUNT6 |
| TCELL13:IMUX.CLK1 | MCB.P0RDCLK |
| TCELL13:IMUX.LOGICIN1 | MCB.P0RTSTWRDATA27 |
| TCELL13:IMUX.LOGICIN2 | MCB.P0RTSTWRMASK1 |
| TCELL13:IMUX.LOGICIN3 | MCB.P0RTSTWRDATA26 |
| TCELL13:IMUX.LOGICIN4 | MCB.P0RTSTWRDATA20 |
| TCELL13:IMUX.LOGICIN7 | MCB.P0RDEN |
| TCELL13:IMUX.LOGICIN10 | MCB.P0RTSTWRDATA25 |
| TCELL13:IMUX.LOGICIN14 | MCB.P0RTSTWRMASK2 |
| TCELL13:IMUX.LOGICIN19 | MCB.P0RTSTWRDATA28 |
| TCELL13:IMUX.LOGICIN26 | MCB.P0RTSTWRDATA22 |
| TCELL13:IMUX.LOGICIN27 | MCB.P0RTSTWRDATA29 |
| TCELL13:IMUX.LOGICIN29 | MCB.P0RTSTWRDATA30 |
| TCELL13:IMUX.LOGICIN30 | MCB.P0RTSTWRDATA23 |
| TCELL13:IMUX.LOGICIN32 | MCB.P0RTSTWRDATA31 |
| TCELL13:IMUX.LOGICIN37 | MCB.P0RTSTWRMASK3 |
| TCELL13:IMUX.LOGICIN41 | MCB.P0RTSTWRDATA24 |
| TCELL13:IMUX.LOGICIN44 | MCB.P0RTSTWRDATA19 |
| TCELL13:IMUX.LOGICIN52 | MCB.P0RTSTWRMASK0 |
| TCELL13:IMUX.LOGICIN55 | MCB.P0RTSTWRDATA21 |
| TCELL13:IMUX.LOGICIN57 | MCB.P0RTSTWRDATA18 |
| TCELL13:OUT0.TMIN | MCB.P0RDEMPTY |
| TCELL13:OUT1.TMIN | MCB.P0RDDATA24 |
| TCELL13:OUT2.TMIN | MCB.P0RDCOUNT3 |
| TCELL13:OUT3.TMIN | MCB.P0RDDATA22 |
| TCELL13:OUT4.TMIN | MCB.P0RDDATA29 |
| TCELL13:OUT5.TMIN | MCB.P0RTSTUNDERRUN |
| TCELL13:OUT6.TMIN | MCB.P0RDDATA28 |
| TCELL13:OUT7.TMIN | MCB.P0RDERROR |
| TCELL13:OUT8.TMIN | MCB.P0RDDATA23 |
| TCELL13:OUT10.TMIN | MCB.P0RDDATA18 |
| TCELL13:OUT12.TMIN | MCB.P0RDCOUNT0 |
| TCELL13:OUT13.TMIN | MCB.P0RDDATA27 |
| TCELL13:OUT14.TMIN | MCB.P0RDCOUNT2 |
| TCELL13:OUT15.TMIN | MCB.P0RDDATA21 |
| TCELL13:OUT16.TMIN | MCB.P0RDDATA30 |
| TCELL13:OUT17.TMIN | MCB.P0RDDATA19 |
| TCELL13:OUT18.TMIN | MCB.P0RDDATA25 |
| TCELL13:OUT19.TMIN | MCB.P0RDCOUNT1 |
| TCELL13:OUT20.TMIN | MCB.P0RDDATA26 |
| TCELL13:OUT21.TMIN | MCB.P0RDDATA31 |
| TCELL13:OUT22.TMIN | MCB.P0RDDATA20 |
| TCELL14:IMUX.LOGICIN1 | MCB.P0WTSTMODEB2 |
| TCELL14:IMUX.LOGICIN4 | MCB.P0WRDATA13 |
| TCELL14:IMUX.LOGICIN7 | MCB.P0WRDATA2 |
| TCELL14:IMUX.LOGICIN9 | MCB.P0WTSTENB |
| TCELL14:IMUX.LOGICIN10 | MCB.P0WRDATA17 |
| TCELL14:IMUX.LOGICIN12 | MCB.P0WRDATA3 |
| TCELL14:IMUX.LOGICIN15 | MCB.P0WRDATA0 |
| TCELL14:IMUX.LOGICIN17 | MCB.P0WRDATA7 |
| TCELL14:IMUX.LOGICIN19 | MCB.P0WTSTMODEB3 |
| TCELL14:IMUX.LOGICIN20 | MCB.P0WRDATA5 |
| TCELL14:IMUX.LOGICIN23 | MCB.P0WRDATA8 |
| TCELL14:IMUX.LOGICIN25 | MCB.P0WRDATA10 |
| TCELL14:IMUX.LOGICIN26 | MCB.P0WRDATA15 |
| TCELL14:IMUX.LOGICIN29 | MCB.P0WTSTMODEB1 |
| TCELL14:IMUX.LOGICIN30 | MCB.P0WRDATA16 |
| TCELL14:IMUX.LOGICIN32 | MCB.P0WTSTMODEB0 |
| TCELL14:IMUX.LOGICIN38 | MCB.P0WRDATA6 |
| TCELL14:IMUX.LOGICIN42 | MCB.P0WRDATA1 |
| TCELL14:IMUX.LOGICIN44 | MCB.P0WRDATA12 |
| TCELL14:IMUX.LOGICIN48 | MCB.P0WRDATA9 |
| TCELL14:IMUX.LOGICIN55 | MCB.P0WRDATA14 |
| TCELL14:IMUX.LOGICIN57 | MCB.P0WRDATA11 |
| TCELL14:IMUX.LOGICIN59 | MCB.P0WTSTPINENB |
| TCELL14:IMUX.LOGICIN62 | MCB.P0WRDATA4 |
| TCELL14:OUT0.TMIN | MCB.P0WTSTDATA5 |
| TCELL14:OUT1.TMIN | MCB.P0WTSTDATA13 |
| TCELL14:OUT2.TMIN | MCB.P0WTSTDATA0 |
| TCELL14:OUT3.TMIN | MCB.P0WTSTDATA11 |
| TCELL14:OUT4.TMIN | MCB.P0WRFULL |
| TCELL14:OUT5.TMIN | MCB.P0WTSTDATA6 |
| TCELL14:OUT6.TMIN | MCB.P0WTSTDATA17 |
| TCELL14:OUT7.TMIN | MCB.P0WTSTDATA3 |
| TCELL14:OUT8.TMIN | MCB.P0WTSTDATA12 |
| TCELL14:OUT9.TMIN | MCB.P0WRCOUNT4 |
| TCELL14:OUT10.TMIN | MCB.P0WTSTDATA7 |
| TCELL14:OUT11.TMIN | MCB.P0WRCOUNT5 |
| TCELL14:OUT12.TMIN | MCB.P0WTSTDATA4 |
| TCELL14:OUT13.TMIN | MCB.P0WTSTDATA16 |
| TCELL14:OUT14.TMIN | MCB.P0WTSTDATA1 |
| TCELL14:OUT15.TMIN | MCB.P0WTSTDATA10 |
| TCELL14:OUT16.TMIN | MCB.P0WTSTOVERFLOW |
| TCELL14:OUT17.TMIN | MCB.P0WTSTDATA8 |
| TCELL14:OUT18.TMIN | MCB.P0WTSTDATA14 |
| TCELL14:OUT19.TMIN | MCB.P0WTSTDATA2 |
| TCELL14:OUT20.TMIN | MCB.P0WTSTDATA15 |
| TCELL14:OUT21.TMIN | MCB.P0WTSTLDMP |
| TCELL14:OUT22.TMIN | MCB.P0WTSTDATA9 |
| TCELL14:OUT23.TMIN | MCB.P0WRCOUNT6 |
| TCELL15:IMUX.CLK1 | MCB.P0WRCLK |
| TCELL15:IMUX.LOGICIN1 | MCB.P0WRDATA27 |
| TCELL15:IMUX.LOGICIN2 | MCB.P0RWRMASK1 |
| TCELL15:IMUX.LOGICIN3 | MCB.P0WRDATA26 |
| TCELL15:IMUX.LOGICIN4 | MCB.P0WRDATA20 |
| TCELL15:IMUX.LOGICIN7 | MCB.P0WREN |
| TCELL15:IMUX.LOGICIN10 | MCB.P0WRDATA25 |
| TCELL15:IMUX.LOGICIN14 | MCB.P0RWRMASK2 |
| TCELL15:IMUX.LOGICIN19 | MCB.P0WRDATA28 |
| TCELL15:IMUX.LOGICIN26 | MCB.P0WRDATA22 |
| TCELL15:IMUX.LOGICIN27 | MCB.P0WRDATA29 |
| TCELL15:IMUX.LOGICIN29 | MCB.P0WRDATA30 |
| TCELL15:IMUX.LOGICIN30 | MCB.P0WRDATA23 |
| TCELL15:IMUX.LOGICIN32 | MCB.P0WRDATA31 |
| TCELL15:IMUX.LOGICIN37 | MCB.P0RWRMASK3 |
| TCELL15:IMUX.LOGICIN41 | MCB.P0WRDATA24 |
| TCELL15:IMUX.LOGICIN44 | MCB.P0WRDATA19 |
| TCELL15:IMUX.LOGICIN52 | MCB.P0RWRMASK0 |
| TCELL15:IMUX.LOGICIN55 | MCB.P0WRDATA21 |
| TCELL15:IMUX.LOGICIN57 | MCB.P0WRDATA18 |
| TCELL15:OUT0.TMIN | MCB.P0WREMPTY |
| TCELL15:OUT1.TMIN | MCB.P0WTSTDATA24 |
| TCELL15:OUT2.TMIN | MCB.P0WRCOUNT3 |
| TCELL15:OUT3.TMIN | MCB.P0WTSTDATA22 |
| TCELL15:OUT4.TMIN | MCB.P0WTSTDATA29 |
| TCELL15:OUT5.TMIN | MCB.P0WRUNDERRUN |
| TCELL15:OUT6.TMIN | MCB.P0WTSTDATA28 |
| TCELL15:OUT7.TMIN | MCB.P0WRERROR |
| TCELL15:OUT8.TMIN | MCB.P0WTSTDATA23 |
| TCELL15:OUT10.TMIN | MCB.P0WTSTDATA18 |
| TCELL15:OUT12.TMIN | MCB.P0WRCOUNT0 |
| TCELL15:OUT13.TMIN | MCB.P0WTSTDATA27 |
| TCELL15:OUT14.TMIN | MCB.P0WRCOUNT2 |
| TCELL15:OUT15.TMIN | MCB.P0WTSTDATA21 |
| TCELL15:OUT16.TMIN | MCB.P0WTSTDATA30 |
| TCELL15:OUT17.TMIN | MCB.P0WTSTDATA19 |
| TCELL15:OUT18.TMIN | MCB.P0WTSTDATA25 |
| TCELL15:OUT19.TMIN | MCB.P0WRCOUNT1 |
| TCELL15:OUT20.TMIN | MCB.P0WTSTDATA26 |
| TCELL15:OUT21.TMIN | MCB.P0WTSTDATA31 |
| TCELL15:OUT22.TMIN | MCB.P0WTSTDATA20 |
| TCELL16:IMUX.LOGICIN1 | MCB.P1RTSTMODEB2 |
| TCELL16:IMUX.LOGICIN4 | MCB.P1RTSTWRDATA13 |
| TCELL16:IMUX.LOGICIN7 | MCB.P1RTSTWRDATA2 |
| TCELL16:IMUX.LOGICIN9 | MCB.P1RTSTENB |
| TCELL16:IMUX.LOGICIN10 | MCB.P1RTSTWRDATA17 |
| TCELL16:IMUX.LOGICIN12 | MCB.P1RTSTWRDATA3 |
| TCELL16:IMUX.LOGICIN15 | MCB.P1RTSTWRDATA0 |
| TCELL16:IMUX.LOGICIN17 | MCB.P1RTSTWRDATA7 |
| TCELL16:IMUX.LOGICIN19 | MCB.P1RTSTMODEB3 |
| TCELL16:IMUX.LOGICIN20 | MCB.P1RTSTWRDATA5 |
| TCELL16:IMUX.LOGICIN23 | MCB.P1RTSTWRDATA8 |
| TCELL16:IMUX.LOGICIN25 | MCB.P1RTSTWRDATA10 |
| TCELL16:IMUX.LOGICIN26 | MCB.P1RTSTWRDATA15 |
| TCELL16:IMUX.LOGICIN29 | MCB.P1RTSTMODEB1 |
| TCELL16:IMUX.LOGICIN30 | MCB.P1RTSTWRDATA16 |
| TCELL16:IMUX.LOGICIN32 | MCB.P1RTSTMODEB0 |
| TCELL16:IMUX.LOGICIN38 | MCB.P1RTSTWRDATA6 |
| TCELL16:IMUX.LOGICIN42 | MCB.P1RTSTWRDATA1 |
| TCELL16:IMUX.LOGICIN44 | MCB.P1RTSTWRDATA12 |
| TCELL16:IMUX.LOGICIN48 | MCB.P1RTSTWRDATA9 |
| TCELL16:IMUX.LOGICIN55 | MCB.P1RTSTWRDATA14 |
| TCELL16:IMUX.LOGICIN57 | MCB.P1RTSTWRDATA11 |
| TCELL16:IMUX.LOGICIN59 | MCB.P1RTSTPINENB |
| TCELL16:IMUX.LOGICIN62 | MCB.P1RTSTWRDATA4 |
| TCELL16:OUT0.TMIN | MCB.P1RDDATA5 |
| TCELL16:OUT1.TMIN | MCB.P1RDDATA13 |
| TCELL16:OUT2.TMIN | MCB.P1RDDATA0 |
| TCELL16:OUT3.TMIN | MCB.P1RDDATA11 |
| TCELL16:OUT4.TMIN | MCB.P1RDFULL |
| TCELL16:OUT5.TMIN | MCB.P1RDDATA6 |
| TCELL16:OUT6.TMIN | MCB.P1RDDATA17 |
| TCELL16:OUT7.TMIN | MCB.P1RDDATA3 |
| TCELL16:OUT8.TMIN | MCB.P1RDDATA12 |
| TCELL16:OUT9.TMIN | MCB.P1RDCOUNT4 |
| TCELL16:OUT10.TMIN | MCB.P1RDDATA7 |
| TCELL16:OUT11.TMIN | MCB.P1RDCOUNT5 |
| TCELL16:OUT12.TMIN | MCB.P1RDDATA4 |
| TCELL16:OUT13.TMIN | MCB.P1RDDATA16 |
| TCELL16:OUT14.TMIN | MCB.P1RDDATA1 |
| TCELL16:OUT15.TMIN | MCB.P1RDDATA10 |
| TCELL16:OUT16.TMIN | MCB.P1RDOVERFLOW |
| TCELL16:OUT17.TMIN | MCB.P1RDDATA8 |
| TCELL16:OUT18.TMIN | MCB.P1RDDATA14 |
| TCELL16:OUT19.TMIN | MCB.P1RDDATA2 |
| TCELL16:OUT20.TMIN | MCB.P1RDDATA15 |
| TCELL16:OUT21.TMIN | MCB.P1RTSTUDMN |
| TCELL16:OUT22.TMIN | MCB.P1RDDATA9 |
| TCELL16:OUT23.TMIN | MCB.P1RDCOUNT6 |
| TCELL17:IMUX.CLK1 | MCB.P1RDCLK |
| TCELL17:IMUX.LOGICIN1 | MCB.P1RTSTWRDATA27 |
| TCELL17:IMUX.LOGICIN2 | MCB.P1RTSTWRMASK1 |
| TCELL17:IMUX.LOGICIN3 | MCB.P1RTSTWRDATA26 |
| TCELL17:IMUX.LOGICIN4 | MCB.P1RTSTWRDATA20 |
| TCELL17:IMUX.LOGICIN7 | MCB.P1RDEN |
| TCELL17:IMUX.LOGICIN10 | MCB.P1RTSTWRDATA25 |
| TCELL17:IMUX.LOGICIN14 | MCB.P1RTSTWRMASK2 |
| TCELL17:IMUX.LOGICIN19 | MCB.P1RTSTWRDATA28 |
| TCELL17:IMUX.LOGICIN26 | MCB.P1RTSTWRDATA22 |
| TCELL17:IMUX.LOGICIN27 | MCB.P1RTSTWRDATA29 |
| TCELL17:IMUX.LOGICIN29 | MCB.P1RTSTWRDATA30 |
| TCELL17:IMUX.LOGICIN30 | MCB.P1RTSTWRDATA23 |
| TCELL17:IMUX.LOGICIN32 | MCB.P1RTSTWRDATA31 |
| TCELL17:IMUX.LOGICIN37 | MCB.P1RTSTWRMASK3 |
| TCELL17:IMUX.LOGICIN41 | MCB.P1RTSTWRDATA24 |
| TCELL17:IMUX.LOGICIN44 | MCB.P1RTSTWRDATA19 |
| TCELL17:IMUX.LOGICIN52 | MCB.P1RTSTWRMASK0 |
| TCELL17:IMUX.LOGICIN55 | MCB.P1RTSTWRDATA21 |
| TCELL17:IMUX.LOGICIN57 | MCB.P1RTSTWRDATA18 |
| TCELL17:OUT0.TMIN | MCB.P1RDEMPTY |
| TCELL17:OUT1.TMIN | MCB.P1RDDATA24 |
| TCELL17:OUT2.TMIN | MCB.P1RDCOUNT3 |
| TCELL17:OUT3.TMIN | MCB.P1RDDATA22 |
| TCELL17:OUT4.TMIN | MCB.P1RDDATA29 |
| TCELL17:OUT5.TMIN | MCB.P1RTSTUNDERRUN |
| TCELL17:OUT6.TMIN | MCB.P1RDDATA28 |
| TCELL17:OUT7.TMIN | MCB.P1RDERROR |
| TCELL17:OUT8.TMIN | MCB.P1RDDATA23 |
| TCELL17:OUT10.TMIN | MCB.P1RDDATA18 |
| TCELL17:OUT12.TMIN | MCB.P1RDCOUNT0 |
| TCELL17:OUT13.TMIN | MCB.P1RDDATA27 |
| TCELL17:OUT14.TMIN | MCB.P1RDCOUNT2 |
| TCELL17:OUT15.TMIN | MCB.P1RDDATA21 |
| TCELL17:OUT16.TMIN | MCB.P1RDDATA30 |
| TCELL17:OUT17.TMIN | MCB.P1RDDATA19 |
| TCELL17:OUT18.TMIN | MCB.P1RDDATA25 |
| TCELL17:OUT19.TMIN | MCB.P1RDCOUNT1 |
| TCELL17:OUT20.TMIN | MCB.P1RDDATA26 |
| TCELL17:OUT21.TMIN | MCB.P1RDDATA31 |
| TCELL17:OUT22.TMIN | MCB.P1RDDATA20 |
| TCELL18:IMUX.LOGICIN1 | MCB.P1WTSTMODEB2 |
| TCELL18:IMUX.LOGICIN4 | MCB.P1WRDATA13 |
| TCELL18:IMUX.LOGICIN7 | MCB.P1WRDATA2 |
| TCELL18:IMUX.LOGICIN9 | MCB.P1WTSTENB |
| TCELL18:IMUX.LOGICIN10 | MCB.P1WRDATA17 |
| TCELL18:IMUX.LOGICIN12 | MCB.P1WRDATA3 |
| TCELL18:IMUX.LOGICIN15 | MCB.P1WRDATA0 |
| TCELL18:IMUX.LOGICIN17 | MCB.P1WRDATA7 |
| TCELL18:IMUX.LOGICIN19 | MCB.P1WTSTMODEB3 |
| TCELL18:IMUX.LOGICIN20 | MCB.P1WRDATA5 |
| TCELL18:IMUX.LOGICIN23 | MCB.P1WRDATA8 |
| TCELL18:IMUX.LOGICIN25 | MCB.P1WRDATA10 |
| TCELL18:IMUX.LOGICIN26 | MCB.P1WRDATA15 |
| TCELL18:IMUX.LOGICIN29 | MCB.P1WTSTMODEB1 |
| TCELL18:IMUX.LOGICIN30 | MCB.P1WRDATA16 |
| TCELL18:IMUX.LOGICIN32 | MCB.P1WTSTMODEB0 |
| TCELL18:IMUX.LOGICIN38 | MCB.P1WRDATA6 |
| TCELL18:IMUX.LOGICIN42 | MCB.P1WRDATA1 |
| TCELL18:IMUX.LOGICIN44 | MCB.P1WRDATA12 |
| TCELL18:IMUX.LOGICIN48 | MCB.P1WRDATA9 |
| TCELL18:IMUX.LOGICIN55 | MCB.P1WRDATA14 |
| TCELL18:IMUX.LOGICIN57 | MCB.P1WRDATA11 |
| TCELL18:IMUX.LOGICIN59 | MCB.P1WTSTPINENB |
| TCELL18:IMUX.LOGICIN62 | MCB.P1WRDATA4 |
| TCELL18:OUT0.TMIN | MCB.P1WTSTDATA5 |
| TCELL18:OUT1.TMIN | MCB.P1WTSTDATA13 |
| TCELL18:OUT2.TMIN | MCB.P1WTSTDATA0 |
| TCELL18:OUT3.TMIN | MCB.P1WTSTDATA11 |
| TCELL18:OUT4.TMIN | MCB.P1WRFULL |
| TCELL18:OUT5.TMIN | MCB.P1WTSTDATA6 |
| TCELL18:OUT6.TMIN | MCB.P1WTSTDATA17 |
| TCELL18:OUT7.TMIN | MCB.P1WTSTDATA3 |
| TCELL18:OUT8.TMIN | MCB.P1WTSTDATA12 |
| TCELL18:OUT9.TMIN | MCB.P1WRCOUNT4 |
| TCELL18:OUT10.TMIN | MCB.P1WTSTDATA7 |
| TCELL18:OUT11.TMIN | MCB.P1WRCOUNT5 |
| TCELL18:OUT12.TMIN | MCB.P1WTSTDATA4 |
| TCELL18:OUT13.TMIN | MCB.P1WTSTDATA16 |
| TCELL18:OUT14.TMIN | MCB.P1WTSTDATA1 |
| TCELL18:OUT15.TMIN | MCB.P1WTSTDATA10 |
| TCELL18:OUT16.TMIN | MCB.P1WTSTOVERFLOW |
| TCELL18:OUT17.TMIN | MCB.P1WTSTDATA8 |
| TCELL18:OUT18.TMIN | MCB.P1WTSTDATA14 |
| TCELL18:OUT19.TMIN | MCB.P1WTSTDATA2 |
| TCELL18:OUT20.TMIN | MCB.P1WTSTDATA15 |
| TCELL18:OUT21.TMIN | MCB.P1WTSTLDMN |
| TCELL18:OUT22.TMIN | MCB.P1WTSTDATA9 |
| TCELL18:OUT23.TMIN | MCB.P1WRCOUNT6 |
| TCELL19:IMUX.CLK1 | MCB.P1WRCLK |
| TCELL19:IMUX.LOGICIN1 | MCB.P1WRDATA27 |
| TCELL19:IMUX.LOGICIN2 | MCB.P1RWRMASK1 |
| TCELL19:IMUX.LOGICIN3 | MCB.P1WRDATA26 |
| TCELL19:IMUX.LOGICIN4 | MCB.P1WRDATA20 |
| TCELL19:IMUX.LOGICIN7 | MCB.P1WREN |
| TCELL19:IMUX.LOGICIN10 | MCB.P1WRDATA25 |
| TCELL19:IMUX.LOGICIN14 | MCB.P1RWRMASK2 |
| TCELL19:IMUX.LOGICIN19 | MCB.P1WRDATA28 |
| TCELL19:IMUX.LOGICIN26 | MCB.P1WRDATA22 |
| TCELL19:IMUX.LOGICIN27 | MCB.P1WRDATA29 |
| TCELL19:IMUX.LOGICIN29 | MCB.P1WRDATA30 |
| TCELL19:IMUX.LOGICIN30 | MCB.P1WRDATA23 |
| TCELL19:IMUX.LOGICIN32 | MCB.P1WRDATA31 |
| TCELL19:IMUX.LOGICIN37 | MCB.P1RWRMASK3 |
| TCELL19:IMUX.LOGICIN41 | MCB.P1WRDATA24 |
| TCELL19:IMUX.LOGICIN44 | MCB.P1WRDATA19 |
| TCELL19:IMUX.LOGICIN52 | MCB.P1RWRMASK0 |
| TCELL19:IMUX.LOGICIN55 | MCB.P1WRDATA21 |
| TCELL19:IMUX.LOGICIN57 | MCB.P1WRDATA18 |
| TCELL19:OUT0.TMIN | MCB.P1WREMPTY |
| TCELL19:OUT1.TMIN | MCB.P1WTSTDATA24 |
| TCELL19:OUT2.TMIN | MCB.P1WRCOUNT3 |
| TCELL19:OUT3.TMIN | MCB.P1WTSTDATA22 |
| TCELL19:OUT4.TMIN | MCB.P1WTSTDATA29 |
| TCELL19:OUT5.TMIN | MCB.P1WRUNDERRUN |
| TCELL19:OUT6.TMIN | MCB.P1WTSTDATA28 |
| TCELL19:OUT7.TMIN | MCB.P1WRERROR |
| TCELL19:OUT8.TMIN | MCB.P1WTSTDATA23 |
| TCELL19:OUT10.TMIN | MCB.P1WTSTDATA18 |
| TCELL19:OUT12.TMIN | MCB.P1WRCOUNT0 |
| TCELL19:OUT13.TMIN | MCB.P1WTSTDATA27 |
| TCELL19:OUT14.TMIN | MCB.P1WRCOUNT2 |
| TCELL19:OUT15.TMIN | MCB.P1WTSTDATA21 |
| TCELL19:OUT16.TMIN | MCB.P1WTSTDATA30 |
| TCELL19:OUT17.TMIN | MCB.P1WTSTDATA19 |
| TCELL19:OUT18.TMIN | MCB.P1WTSTDATA25 |
| TCELL19:OUT19.TMIN | MCB.P1WRCOUNT1 |
| TCELL19:OUT20.TMIN | MCB.P1WTSTDATA26 |
| TCELL19:OUT21.TMIN | MCB.P1WTSTDATA31 |
| TCELL19:OUT22.TMIN | MCB.P1WTSTDATA20 |
| TCELL20:IMUX.LOGICIN1 | MCB.P2TSTMODEB2 |
| TCELL20:IMUX.LOGICIN4 | MCB.P2WRDATA13 |
| TCELL20:IMUX.LOGICIN7 | MCB.P2WRDATA2 |
| TCELL20:IMUX.LOGICIN9 | MCB.P2TSTENB |
| TCELL20:IMUX.LOGICIN10 | MCB.P2WRDATA17 |
| TCELL20:IMUX.LOGICIN12 | MCB.P2WRDATA3 |
| TCELL20:IMUX.LOGICIN15 | MCB.P2WRDATA0 |
| TCELL20:IMUX.LOGICIN17 | MCB.P2WRDATA7 |
| TCELL20:IMUX.LOGICIN19 | MCB.P2TSTMODEB3 |
| TCELL20:IMUX.LOGICIN20 | MCB.P2WRDATA5 |
| TCELL20:IMUX.LOGICIN23 | MCB.P2WRDATA8 |
| TCELL20:IMUX.LOGICIN25 | MCB.P2WRDATA10 |
| TCELL20:IMUX.LOGICIN26 | MCB.P2WRDATA15 |
| TCELL20:IMUX.LOGICIN29 | MCB.P2TSTMODEB1 |
| TCELL20:IMUX.LOGICIN30 | MCB.P2WRDATA16 |
| TCELL20:IMUX.LOGICIN32 | MCB.P2TSTMODEB0 |
| TCELL20:IMUX.LOGICIN38 | MCB.P2WRDATA6 |
| TCELL20:IMUX.LOGICIN42 | MCB.P2WRDATA1 |
| TCELL20:IMUX.LOGICIN44 | MCB.P2WRDATA12 |
| TCELL20:IMUX.LOGICIN48 | MCB.P2WRDATA9 |
| TCELL20:IMUX.LOGICIN55 | MCB.P2WRDATA14 |
| TCELL20:IMUX.LOGICIN57 | MCB.P2WRDATA11 |
| TCELL20:IMUX.LOGICIN59 | MCB.P2TSTPINENB |
| TCELL20:IMUX.LOGICIN62 | MCB.P2WRDATA4 |
| TCELL20:OUT0.TMIN | MCB.P2RDDATA5 |
| TCELL20:OUT1.TMIN | MCB.P2RDDATA13 |
| TCELL20:OUT2.TMIN | MCB.P2RDDATA0 |
| TCELL20:OUT3.TMIN | MCB.P2RDDATA11 |
| TCELL20:OUT4.TMIN | MCB.P2FULL |
| TCELL20:OUT5.TMIN | MCB.P2RDDATA6 |
| TCELL20:OUT6.TMIN | MCB.P2RDDATA17 |
| TCELL20:OUT7.TMIN | MCB.P2RDDATA3 |
| TCELL20:OUT8.TMIN | MCB.P2RDDATA12 |
| TCELL20:OUT9.TMIN | MCB.P2COUNT4 |
| TCELL20:OUT10.TMIN | MCB.P2RDDATA7 |
| TCELL20:OUT11.TMIN | MCB.P2COUNT5 |
| TCELL20:OUT12.TMIN | MCB.P2RDDATA4 |
| TCELL20:OUT13.TMIN | MCB.P2RDDATA16 |
| TCELL20:OUT14.TMIN | MCB.P2RDDATA1 |
| TCELL20:OUT15.TMIN | MCB.P2RDDATA10 |
| TCELL20:OUT16.TMIN | MCB.P2RDOVERFLOW |
| TCELL20:OUT17.TMIN | MCB.P2RDDATA8 |
| TCELL20:OUT18.TMIN | MCB.P2RDDATA14 |
| TCELL20:OUT19.TMIN | MCB.P2RDDATA2 |
| TCELL20:OUT20.TMIN | MCB.P2RDDATA15 |
| TCELL20:OUT21.TMIN | MCB.P2TSTUDMP |
| TCELL20:OUT22.TMIN | MCB.P2RDDATA9 |
| TCELL20:OUT23.TMIN | MCB.P2COUNT6 |
| TCELL21:IMUX.CLK1 | MCB.P2CLK |
| TCELL21:IMUX.LOGICIN1 | MCB.P2WRDATA27 |
| TCELL21:IMUX.LOGICIN2 | MCB.P2WRMASK1 |
| TCELL21:IMUX.LOGICIN3 | MCB.P2WRDATA26 |
| TCELL21:IMUX.LOGICIN4 | MCB.P2WRDATA20 |
| TCELL21:IMUX.LOGICIN7 | MCB.P2EN |
| TCELL21:IMUX.LOGICIN10 | MCB.P2WRDATA25 |
| TCELL21:IMUX.LOGICIN14 | MCB.P2WRMASK2 |
| TCELL21:IMUX.LOGICIN19 | MCB.P2WRDATA28 |
| TCELL21:IMUX.LOGICIN26 | MCB.P2WRDATA22 |
| TCELL21:IMUX.LOGICIN27 | MCB.P2WRDATA29 |
| TCELL21:IMUX.LOGICIN29 | MCB.P2WRDATA30 |
| TCELL21:IMUX.LOGICIN30 | MCB.P2WRDATA23 |
| TCELL21:IMUX.LOGICIN32 | MCB.P2WRDATA31 |
| TCELL21:IMUX.LOGICIN37 | MCB.P2WRMASK3 |
| TCELL21:IMUX.LOGICIN41 | MCB.P2WRDATA24 |
| TCELL21:IMUX.LOGICIN44 | MCB.P2WRDATA19 |
| TCELL21:IMUX.LOGICIN52 | MCB.P2WRMASK0 |
| TCELL21:IMUX.LOGICIN55 | MCB.P2WRDATA21 |
| TCELL21:IMUX.LOGICIN57 | MCB.P2WRDATA18 |
| TCELL21:OUT0.TMIN | MCB.P2EMPTY |
| TCELL21:OUT1.TMIN | MCB.P2RDDATA24 |
| TCELL21:OUT2.TMIN | MCB.P2COUNT3 |
| TCELL21:OUT3.TMIN | MCB.P2RDDATA22 |
| TCELL21:OUT4.TMIN | MCB.P2RDDATA29 |
| TCELL21:OUT5.TMIN | MCB.P2WRUNDERRUN |
| TCELL21:OUT6.TMIN | MCB.P2RDDATA28 |
| TCELL21:OUT7.TMIN | MCB.P2ERROR |
| TCELL21:OUT8.TMIN | MCB.P2RDDATA23 |
| TCELL21:OUT10.TMIN | MCB.P2RDDATA18 |
| TCELL21:OUT12.TMIN | MCB.P2COUNT0 |
| TCELL21:OUT13.TMIN | MCB.P2RDDATA27 |
| TCELL21:OUT14.TMIN | MCB.P2COUNT2 |
| TCELL21:OUT15.TMIN | MCB.P2RDDATA21 |
| TCELL21:OUT16.TMIN | MCB.P2RDDATA30 |
| TCELL21:OUT17.TMIN | MCB.P2RDDATA19 |
| TCELL21:OUT18.TMIN | MCB.P2RDDATA25 |
| TCELL21:OUT19.TMIN | MCB.P2COUNT1 |
| TCELL21:OUT20.TMIN | MCB.P2RDDATA26 |
| TCELL21:OUT21.TMIN | MCB.P2RDDATA31 |
| TCELL21:OUT22.TMIN | MCB.P2RDDATA20 |
| TCELL22:IMUX.LOGICIN1 | MCB.P3TSTMODEB2 |
| TCELL22:IMUX.LOGICIN4 | MCB.P3WRDATA13 |
| TCELL22:IMUX.LOGICIN7 | MCB.P3WRDATA2 |
| TCELL22:IMUX.LOGICIN9 | MCB.P3TSTENB |
| TCELL22:IMUX.LOGICIN10 | MCB.P3WRDATA17 |
| TCELL22:IMUX.LOGICIN12 | MCB.P3WRDATA3 |
| TCELL22:IMUX.LOGICIN15 | MCB.P3WRDATA0 |
| TCELL22:IMUX.LOGICIN17 | MCB.P3WRDATA7 |
| TCELL22:IMUX.LOGICIN19 | MCB.P3TSTMODEB3 |
| TCELL22:IMUX.LOGICIN20 | MCB.P3WRDATA5 |
| TCELL22:IMUX.LOGICIN23 | MCB.P3WRDATA8 |
| TCELL22:IMUX.LOGICIN25 | MCB.P3WRDATA10 |
| TCELL22:IMUX.LOGICIN26 | MCB.P3WRDATA15 |
| TCELL22:IMUX.LOGICIN29 | MCB.P3TSTMODEB1 |
| TCELL22:IMUX.LOGICIN30 | MCB.P3WRDATA16 |
| TCELL22:IMUX.LOGICIN32 | MCB.P3TSTMODEB0 |
| TCELL22:IMUX.LOGICIN38 | MCB.P3WRDATA6 |
| TCELL22:IMUX.LOGICIN42 | MCB.P3WRDATA1 |
| TCELL22:IMUX.LOGICIN44 | MCB.P3WRDATA12 |
| TCELL22:IMUX.LOGICIN48 | MCB.P3WRDATA9 |
| TCELL22:IMUX.LOGICIN55 | MCB.P3WRDATA14 |
| TCELL22:IMUX.LOGICIN57 | MCB.P3WRDATA11 |
| TCELL22:IMUX.LOGICIN59 | MCB.P3TSTPINENB |
| TCELL22:IMUX.LOGICIN62 | MCB.P3WRDATA4 |
| TCELL22:OUT0.TMIN | MCB.P3RDDATA5 |
| TCELL22:OUT1.TMIN | MCB.P3RDDATA13 |
| TCELL22:OUT2.TMIN | MCB.P3RDDATA0 |
| TCELL22:OUT3.TMIN | MCB.P3RDDATA11 |
| TCELL22:OUT4.TMIN | MCB.P3FULL |
| TCELL22:OUT5.TMIN | MCB.P3RDDATA6 |
| TCELL22:OUT6.TMIN | MCB.P3RDDATA17 |
| TCELL22:OUT7.TMIN | MCB.P3RDDATA3 |
| TCELL22:OUT8.TMIN | MCB.P3RDDATA12 |
| TCELL22:OUT9.TMIN | MCB.P3COUNT4 |
| TCELL22:OUT10.TMIN | MCB.P3RDDATA7 |
| TCELL22:OUT11.TMIN | MCB.P3COUNT5 |
| TCELL22:OUT12.TMIN | MCB.P3RDDATA4 |
| TCELL22:OUT13.TMIN | MCB.P3RDDATA16 |
| TCELL22:OUT14.TMIN | MCB.P3RDDATA1 |
| TCELL22:OUT15.TMIN | MCB.P3RDDATA10 |
| TCELL22:OUT16.TMIN | MCB.P3RDOVERFLOW |
| TCELL22:OUT17.TMIN | MCB.P3RDDATA8 |
| TCELL22:OUT18.TMIN | MCB.P3RDDATA14 |
| TCELL22:OUT19.TMIN | MCB.P3RDDATA2 |
| TCELL22:OUT20.TMIN | MCB.P3RDDATA15 |
| TCELL22:OUT21.TMIN | MCB.P3TSTLDMP |
| TCELL22:OUT22.TMIN | MCB.P3RDDATA9 |
| TCELL22:OUT23.TMIN | MCB.P3COUNT6 |
| TCELL23:IMUX.CLK1 | MCB.P3CLK |
| TCELL23:IMUX.LOGICIN1 | MCB.P3WRDATA27 |
| TCELL23:IMUX.LOGICIN2 | MCB.P3WRMASK1 |
| TCELL23:IMUX.LOGICIN3 | MCB.P3WRDATA26 |
| TCELL23:IMUX.LOGICIN4 | MCB.P3WRDATA20 |
| TCELL23:IMUX.LOGICIN7 | MCB.P3EN |
| TCELL23:IMUX.LOGICIN10 | MCB.P3WRDATA25 |
| TCELL23:IMUX.LOGICIN14 | MCB.P3WRMASK2 |
| TCELL23:IMUX.LOGICIN19 | MCB.P3WRDATA28 |
| TCELL23:IMUX.LOGICIN26 | MCB.P3WRDATA22 |
| TCELL23:IMUX.LOGICIN27 | MCB.P3WRDATA29 |
| TCELL23:IMUX.LOGICIN29 | MCB.P3WRDATA30 |
| TCELL23:IMUX.LOGICIN30 | MCB.P3WRDATA23 |
| TCELL23:IMUX.LOGICIN32 | MCB.P3WRDATA31 |
| TCELL23:IMUX.LOGICIN37 | MCB.P3WRMASK3 |
| TCELL23:IMUX.LOGICIN41 | MCB.P3WRDATA24 |
| TCELL23:IMUX.LOGICIN44 | MCB.P3WRDATA19 |
| TCELL23:IMUX.LOGICIN52 | MCB.P3WRMASK0 |
| TCELL23:IMUX.LOGICIN55 | MCB.P3WRDATA21 |
| TCELL23:IMUX.LOGICIN57 | MCB.P3WRDATA18 |
| TCELL23:OUT0.TMIN | MCB.P3EMPTY |
| TCELL23:OUT1.TMIN | MCB.P3RDDATA24 |
| TCELL23:OUT2.TMIN | MCB.P3COUNT3 |
| TCELL23:OUT3.TMIN | MCB.P3RDDATA22 |
| TCELL23:OUT4.TMIN | MCB.P3RDDATA29 |
| TCELL23:OUT5.TMIN | MCB.P3WRUNDERRUN |
| TCELL23:OUT6.TMIN | MCB.P3RDDATA28 |
| TCELL23:OUT7.TMIN | MCB.P3ERROR |
| TCELL23:OUT8.TMIN | MCB.P3RDDATA23 |
| TCELL23:OUT10.TMIN | MCB.P3RDDATA18 |
| TCELL23:OUT12.TMIN | MCB.P3COUNT0 |
| TCELL23:OUT13.TMIN | MCB.P3RDDATA27 |
| TCELL23:OUT14.TMIN | MCB.P3COUNT2 |
| TCELL23:OUT15.TMIN | MCB.P3RDDATA21 |
| TCELL23:OUT16.TMIN | MCB.P3RDDATA30 |
| TCELL23:OUT17.TMIN | MCB.P3RDDATA19 |
| TCELL23:OUT18.TMIN | MCB.P3RDDATA25 |
| TCELL23:OUT19.TMIN | MCB.P3COUNT1 |
| TCELL23:OUT20.TMIN | MCB.P3RDDATA26 |
| TCELL23:OUT21.TMIN | MCB.P3RDDATA31 |
| TCELL23:OUT22.TMIN | MCB.P3RDDATA20 |
| TCELL24:IMUX.LOGICIN1 | MCB.P4TSTMODEB2 |
| TCELL24:IMUX.LOGICIN4 | MCB.P4WRDATA13 |
| TCELL24:IMUX.LOGICIN7 | MCB.P4WRDATA2 |
| TCELL24:IMUX.LOGICIN9 | MCB.P4TSTENB |
| TCELL24:IMUX.LOGICIN10 | MCB.P4WRDATA17 |
| TCELL24:IMUX.LOGICIN12 | MCB.P4WRDATA3 |
| TCELL24:IMUX.LOGICIN15 | MCB.P4WRDATA0 |
| TCELL24:IMUX.LOGICIN17 | MCB.P4WRDATA7 |
| TCELL24:IMUX.LOGICIN19 | MCB.P4TSTMODEB3 |
| TCELL24:IMUX.LOGICIN20 | MCB.P4WRDATA5 |
| TCELL24:IMUX.LOGICIN23 | MCB.P4WRDATA8 |
| TCELL24:IMUX.LOGICIN25 | MCB.P4WRDATA10 |
| TCELL24:IMUX.LOGICIN26 | MCB.P4WRDATA15 |
| TCELL24:IMUX.LOGICIN29 | MCB.P4TSTMODEB1 |
| TCELL24:IMUX.LOGICIN30 | MCB.P4WRDATA16 |
| TCELL24:IMUX.LOGICIN32 | MCB.P4TSTMODEB0 |
| TCELL24:IMUX.LOGICIN38 | MCB.P4WRDATA6 |
| TCELL24:IMUX.LOGICIN42 | MCB.P4WRDATA1 |
| TCELL24:IMUX.LOGICIN44 | MCB.P4WRDATA12 |
| TCELL24:IMUX.LOGICIN48 | MCB.P4WRDATA9 |
| TCELL24:IMUX.LOGICIN55 | MCB.P4WRDATA14 |
| TCELL24:IMUX.LOGICIN57 | MCB.P4WRDATA11 |
| TCELL24:IMUX.LOGICIN59 | MCB.P4TSTPINENB |
| TCELL24:IMUX.LOGICIN62 | MCB.P4WRDATA4 |
| TCELL24:OUT0.TMIN | MCB.P4RDDATA5 |
| TCELL24:OUT1.TMIN | MCB.P4RDDATA13 |
| TCELL24:OUT2.TMIN | MCB.P4RDDATA0 |
| TCELL24:OUT3.TMIN | MCB.P4RDDATA11 |
| TCELL24:OUT4.TMIN | MCB.P4FULL |
| TCELL24:OUT5.TMIN | MCB.P4RDDATA6 |
| TCELL24:OUT6.TMIN | MCB.P4RDDATA17 |
| TCELL24:OUT7.TMIN | MCB.P4RDDATA3 |
| TCELL24:OUT8.TMIN | MCB.P4RDDATA12 |
| TCELL24:OUT9.TMIN | MCB.P4COUNT4 |
| TCELL24:OUT10.TMIN | MCB.P4RDDATA7 |
| TCELL24:OUT11.TMIN | MCB.P4COUNT5 |
| TCELL24:OUT12.TMIN | MCB.P4RDDATA4 |
| TCELL24:OUT13.TMIN | MCB.P4RDDATA16 |
| TCELL24:OUT14.TMIN | MCB.P4RDDATA1 |
| TCELL24:OUT15.TMIN | MCB.P4RDDATA10 |
| TCELL24:OUT16.TMIN | MCB.P4RDOVERFLOW |
| TCELL24:OUT17.TMIN | MCB.P4RDDATA8 |
| TCELL24:OUT18.TMIN | MCB.P4RDDATA14 |
| TCELL24:OUT19.TMIN | MCB.P4RDDATA2 |
| TCELL24:OUT20.TMIN | MCB.P4RDDATA15 |
| TCELL24:OUT21.TMIN | MCB.P4TSTUDMN |
| TCELL24:OUT22.TMIN | MCB.P4RDDATA9 |
| TCELL24:OUT23.TMIN | MCB.P4COUNT6 |
| TCELL25:IMUX.CLK1 | MCB.P4CLK |
| TCELL25:IMUX.LOGICIN1 | MCB.P4WRDATA27 |
| TCELL25:IMUX.LOGICIN2 | MCB.P4WRMASK1 |
| TCELL25:IMUX.LOGICIN3 | MCB.P4WRDATA26 |
| TCELL25:IMUX.LOGICIN4 | MCB.P4WRDATA20 |
| TCELL25:IMUX.LOGICIN7 | MCB.P4EN |
| TCELL25:IMUX.LOGICIN10 | MCB.P4WRDATA25 |
| TCELL25:IMUX.LOGICIN14 | MCB.P4WRMASK2 |
| TCELL25:IMUX.LOGICIN19 | MCB.P4WRDATA28 |
| TCELL25:IMUX.LOGICIN26 | MCB.P4WRDATA22 |
| TCELL25:IMUX.LOGICIN27 | MCB.P4WRDATA29 |
| TCELL25:IMUX.LOGICIN29 | MCB.P4WRDATA30 |
| TCELL25:IMUX.LOGICIN30 | MCB.P4WRDATA23 |
| TCELL25:IMUX.LOGICIN32 | MCB.P4WRDATA31 |
| TCELL25:IMUX.LOGICIN37 | MCB.P4WRMASK3 |
| TCELL25:IMUX.LOGICIN41 | MCB.P4WRDATA24 |
| TCELL25:IMUX.LOGICIN44 | MCB.P4WRDATA19 |
| TCELL25:IMUX.LOGICIN52 | MCB.P4WRMASK0 |
| TCELL25:IMUX.LOGICIN55 | MCB.P4WRDATA21 |
| TCELL25:IMUX.LOGICIN57 | MCB.P4WRDATA18 |
| TCELL25:OUT0.TMIN | MCB.P4EMPTY |
| TCELL25:OUT1.TMIN | MCB.P4RDDATA24 |
| TCELL25:OUT2.TMIN | MCB.P4COUNT3 |
| TCELL25:OUT3.TMIN | MCB.P4RDDATA22 |
| TCELL25:OUT4.TMIN | MCB.P4RDDATA29 |
| TCELL25:OUT5.TMIN | MCB.P4WRUNDERRUN |
| TCELL25:OUT6.TMIN | MCB.P4RDDATA28 |
| TCELL25:OUT7.TMIN | MCB.P4ERROR |
| TCELL25:OUT8.TMIN | MCB.P4RDDATA23 |
| TCELL25:OUT10.TMIN | MCB.P4RDDATA18 |
| TCELL25:OUT12.TMIN | MCB.P4COUNT0 |
| TCELL25:OUT13.TMIN | MCB.P4RDDATA27 |
| TCELL25:OUT14.TMIN | MCB.P4COUNT2 |
| TCELL25:OUT15.TMIN | MCB.P4RDDATA21 |
| TCELL25:OUT16.TMIN | MCB.P4RDDATA30 |
| TCELL25:OUT17.TMIN | MCB.P4RDDATA19 |
| TCELL25:OUT18.TMIN | MCB.P4RDDATA25 |
| TCELL25:OUT19.TMIN | MCB.P4COUNT1 |
| TCELL25:OUT20.TMIN | MCB.P4RDDATA26 |
| TCELL25:OUT21.TMIN | MCB.P4RDDATA31 |
| TCELL25:OUT22.TMIN | MCB.P4RDDATA20 |
| TCELL26:IMUX.LOGICIN1 | MCB.P5TSTMODEB2 |
| TCELL26:IMUX.LOGICIN4 | MCB.P5WRDATA13 |
| TCELL26:IMUX.LOGICIN7 | MCB.P5WRDATA2 |
| TCELL26:IMUX.LOGICIN9 | MCB.P5TSTENB |
| TCELL26:IMUX.LOGICIN10 | MCB.P5WRDATA17 |
| TCELL26:IMUX.LOGICIN12 | MCB.P5WRDATA3 |
| TCELL26:IMUX.LOGICIN15 | MCB.P5WRDATA0 |
| TCELL26:IMUX.LOGICIN17 | MCB.P5WRDATA7 |
| TCELL26:IMUX.LOGICIN19 | MCB.P5TSTMODEB3 |
| TCELL26:IMUX.LOGICIN20 | MCB.P5WRDATA5 |
| TCELL26:IMUX.LOGICIN23 | MCB.P5WRDATA8 |
| TCELL26:IMUX.LOGICIN25 | MCB.P5WRDATA10 |
| TCELL26:IMUX.LOGICIN26 | MCB.P5WRDATA15 |
| TCELL26:IMUX.LOGICIN29 | MCB.P5TSTMODEB1 |
| TCELL26:IMUX.LOGICIN30 | MCB.P5WRDATA16 |
| TCELL26:IMUX.LOGICIN32 | MCB.P5TSTMODEB0 |
| TCELL26:IMUX.LOGICIN38 | MCB.P5WRDATA6 |
| TCELL26:IMUX.LOGICIN42 | MCB.P5WRDATA1 |
| TCELL26:IMUX.LOGICIN44 | MCB.P5WRDATA12 |
| TCELL26:IMUX.LOGICIN48 | MCB.P5WRDATA9 |
| TCELL26:IMUX.LOGICIN55 | MCB.P5WRDATA14 |
| TCELL26:IMUX.LOGICIN57 | MCB.P5WRDATA11 |
| TCELL26:IMUX.LOGICIN59 | MCB.P5TSTPINENB |
| TCELL26:IMUX.LOGICIN62 | MCB.P5WRDATA4 |
| TCELL26:OUT0.TMIN | MCB.P5RDDATA5 |
| TCELL26:OUT1.TMIN | MCB.P5RDDATA13 |
| TCELL26:OUT2.TMIN | MCB.P5RDDATA0 |
| TCELL26:OUT3.TMIN | MCB.P5RDDATA11 |
| TCELL26:OUT4.TMIN | MCB.P5FULL |
| TCELL26:OUT5.TMIN | MCB.P5RDDATA6 |
| TCELL26:OUT6.TMIN | MCB.P5RDDATA17 |
| TCELL26:OUT7.TMIN | MCB.P5RDDATA3 |
| TCELL26:OUT8.TMIN | MCB.P5RDDATA12 |
| TCELL26:OUT9.TMIN | MCB.P5COUNT4 |
| TCELL26:OUT10.TMIN | MCB.P5RDDATA7 |
| TCELL26:OUT11.TMIN | MCB.P5COUNT5 |
| TCELL26:OUT12.TMIN | MCB.P5RDDATA4 |
| TCELL26:OUT13.TMIN | MCB.P5RDDATA16 |
| TCELL26:OUT14.TMIN | MCB.P5RDDATA1 |
| TCELL26:OUT15.TMIN | MCB.P5RDDATA10 |
| TCELL26:OUT16.TMIN | MCB.P5RDOVERFLOW |
| TCELL26:OUT17.TMIN | MCB.P5RDDATA8 |
| TCELL26:OUT18.TMIN | MCB.P5RDDATA14 |
| TCELL26:OUT19.TMIN | MCB.P5RDDATA2 |
| TCELL26:OUT20.TMIN | MCB.P5RDDATA15 |
| TCELL26:OUT21.TMIN | MCB.P5TSTLDMN |
| TCELL26:OUT22.TMIN | MCB.P5RDDATA9 |
| TCELL26:OUT23.TMIN | MCB.P5COUNT6 |
| TCELL27:IMUX.CLK1 | MCB.P5CLK |
| TCELL27:IMUX.LOGICIN1 | MCB.P5WRDATA27 |
| TCELL27:IMUX.LOGICIN2 | MCB.P5WRMASK1 |
| TCELL27:IMUX.LOGICIN3 | MCB.P5WRDATA26 |
| TCELL27:IMUX.LOGICIN4 | MCB.P5WRDATA20 |
| TCELL27:IMUX.LOGICIN7 | MCB.P5EN |
| TCELL27:IMUX.LOGICIN10 | MCB.P5WRDATA25 |
| TCELL27:IMUX.LOGICIN14 | MCB.P5WRMASK2 |
| TCELL27:IMUX.LOGICIN19 | MCB.P5WRDATA28 |
| TCELL27:IMUX.LOGICIN26 | MCB.P5WRDATA22 |
| TCELL27:IMUX.LOGICIN27 | MCB.P5WRDATA29 |
| TCELL27:IMUX.LOGICIN29 | MCB.P5WRDATA30 |
| TCELL27:IMUX.LOGICIN30 | MCB.P5WRDATA23 |
| TCELL27:IMUX.LOGICIN32 | MCB.P5WRDATA31 |
| TCELL27:IMUX.LOGICIN37 | MCB.P5WRMASK3 |
| TCELL27:IMUX.LOGICIN41 | MCB.P5WRDATA24 |
| TCELL27:IMUX.LOGICIN44 | MCB.P5WRDATA19 |
| TCELL27:IMUX.LOGICIN52 | MCB.P5WRMASK0 |
| TCELL27:IMUX.LOGICIN55 | MCB.P5WRDATA21 |
| TCELL27:IMUX.LOGICIN57 | MCB.P5WRDATA18 |
| TCELL27:OUT0.TMIN | MCB.P5EMPTY |
| TCELL27:OUT1.TMIN | MCB.P5RDDATA24 |
| TCELL27:OUT2.TMIN | MCB.P5COUNT3 |
| TCELL27:OUT3.TMIN | MCB.P5RDDATA22 |
| TCELL27:OUT4.TMIN | MCB.P5RDDATA29 |
| TCELL27:OUT5.TMIN | MCB.P5WRUNDERRUN |
| TCELL27:OUT6.TMIN | MCB.P5RDDATA28 |
| TCELL27:OUT7.TMIN | MCB.P5ERROR |
| TCELL27:OUT8.TMIN | MCB.P5RDDATA23 |
| TCELL27:OUT10.TMIN | MCB.P5RDDATA18 |
| TCELL27:OUT12.TMIN | MCB.P5COUNT0 |
| TCELL27:OUT13.TMIN | MCB.P5RDDATA27 |
| TCELL27:OUT14.TMIN | MCB.P5COUNT2 |
| TCELL27:OUT15.TMIN | MCB.P5RDDATA21 |
| TCELL27:OUT16.TMIN | MCB.P5RDDATA30 |
| TCELL27:OUT17.TMIN | MCB.P5RDDATA19 |
| TCELL27:OUT18.TMIN | MCB.P5RDDATA25 |
| TCELL27:OUT19.TMIN | MCB.P5COUNT1 |
| TCELL27:OUT20.TMIN | MCB.P5RDDATA26 |
| TCELL27:OUT21.TMIN | MCB.P5RDDATA31 |
| TCELL27:OUT22.TMIN | MCB.P5RDDATA20 |
Bitstream
| Bit | Frame | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_DELAY[1] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_DELAY[0] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_CALIBRATION_MODE[0] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_CLK_DIV[1] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_CLK_DIV[0] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[17] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[16] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[14] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[13] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[12] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[11] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[10] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[9] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[8] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[7] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[6] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[5] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[4] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[3] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[2] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[1] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_11[0] |
| Bit | Frame | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:INV.P5CMDEN |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P5CMDCLK |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_CA[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_CA[10] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_CA[9] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_CA[8] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_CA[7] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_CA[6] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_CA[5] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_CA[4] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_CA[3] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_CA[2] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_CA[1] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_CA[0] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[17] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[16] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[14] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[13] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[12] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[11] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[10] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[9] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[8] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[7] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[6] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[5] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[4] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[3] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[2] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[1] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_10[0] |
| Bit | Frame | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_RA[14] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_RA[13] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_RA[12] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_RA[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_RA[10] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_RA[9] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_RA[8] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_RA[7] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_RA[6] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_RA[5] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_RA[4] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_RA[3] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_RA[2] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_RA[1] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_RA[0] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[17] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[16] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[14] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[13] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[12] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[11] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[10] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[9] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[8] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[7] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[6] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[5] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[4] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[3] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[2] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[1] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_9[0] |
| Bit | Frame | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:INV.P4CMDEN |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P4CMDCLK |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_BA[2] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_BA[1] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_BA[0] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:CAL_BYPASS |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[17] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[16] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[14] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[13] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[12] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[11] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[10] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[9] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[8] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[7] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[6] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[5] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[4] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[3] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[2] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[1] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_8[0] |
| Bit | Frame | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR3[13] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR3[12] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR3[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR3[10] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR3[9] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR3[8] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR3[7] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR3[6] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR3[5] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR3[4] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR3[3] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR3[2] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR3[1] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR3[0] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[17] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[16] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[14] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[13] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[12] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[11] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[10] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[9] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[8] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[7] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[6] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[5] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[4] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[3] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[2] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[1] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_7[0] |
| Bit | Frame | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:INV.P3CMDEN |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P3CMDCLK |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR2[13] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR2[12] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR2[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR2[10] MCB:MEM_DDR3_DYN_WRT_ODT[1] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR2[9] MCB:MEM_DDR3_DYN_WRT_ODT[0] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR2[8] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR2[7] MCB:MEM_DDR2_3_HIGH_TEMP_SR[0] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR2[6] MCB:MEM_DDR3_AUTO_SR[0] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR2[5] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR2[4] MCB:MEM_DDR3_CAS_WR_LATENCY[1] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR2[3] MCB:MEM_DDR3_CAS_WR_LATENCY[0] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR2[2] MCB:MEM_DDR2_3_PA_SR[2] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR2[1] MCB:MEM_DDR2_3_PA_SR[1] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR2[0] MCB:MEM_DDR2_3_PA_SR[0] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[17] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[16] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[14] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[13] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[12] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[11] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[10] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[9] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[8] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[7] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[6] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[5] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[4] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[3] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[2] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[1] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_6[0] |
| Bit | Frame | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR1[13] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR1[12] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR1[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR1[10] MCB:MEM_DDR2_DIFF_DQS_EN[0] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR1[9] MCB:MEM_DDR3_RTT[2] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR1[8] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR1[7] MCB:MEM_MDDR_ODS[2] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR1[6] MCB:MEM_DDR2_RTT[1] MCB:MEM_DDR3_RTT[0] MCB:MEM_MDDR_ODS[0] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR1[5] MCB:MEM_DDR2_ADD_LATENCY[2] MCB:MEM_MDDR_ODS[1] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR1[4] MCB:MEM_DDR2_ADD_LATENCY[1] MCB:MEM_DDR3_ADD_LATENCY[1] MCB:MEM_MOBILE_TC_SR[1] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR1[3] MCB:MEM_DDR2_ADD_LATENCY[0] MCB:MEM_DDR3_ADD_LATENCY[0] MCB:MEM_MOBILE_TC_SR[0] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR1[2] MCB:MEM_DDR2_RTT[0] MCB:MEM_DDR3_RTT[1] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR1[1] MCB:MEM_DDR1_2_ODS[0] MCB:MEM_DDR3_ODS[0] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:EMR1[0] MCB:MEM_MOBILE_PA_SR[0] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[17] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[16] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[14] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[13] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[12] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[11] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[10] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[9] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[8] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[7] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[6] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[5] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[4] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[3] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[2] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[1] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_5[0] |
| Bit | Frame | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:INV.P2CMDEN |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P2CMDCLK |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MR[13] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MR[12] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_DDR2_WRT_RECOVERY[2] MCB:MEM_DDR3_WRT_RECOVERY[2] MCB:MR[11] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_DDR2_WRT_RECOVERY[1] MCB:MEM_DDR3_WRT_RECOVERY[1] MCB:MR[10] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_DDR2_WRT_RECOVERY[0] MCB:MEM_DDR3_WRT_RECOVERY[0] MCB:MR[9] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MR[8] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MR[7] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_CAS_LATENCY[2] MCB:MEM_DDR3_CAS_LATENCY[2] MCB:MR[6] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_CAS_LATENCY[1] MCB:MEM_DDR3_CAS_LATENCY[1] MCB:MR[5] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_CAS_LATENCY[0] MCB:MEM_DDR3_CAS_LATENCY[0] MCB:MR[4] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MR[3] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MR[2] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_DDR_DDR2_MDDR_BURST_LEN[0] MCB:MR[1] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_DDR_DDR2_MDDR_BURST_LEN[1] MCB:MR[0] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[17] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[16] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[14] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[13] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[12] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[11] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[10] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[9] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[8] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[7] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[6] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[5] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[4] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[3] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[2] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[1] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_4[0] |
| Bit | Frame | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_ADDR_ORDER[0] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_CA_SIZE[1] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_CA_SIZE[0] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RA_SIZE[1] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RA_SIZE[0] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_BA_SIZE[0] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_NUM_TIME_SLOTS[0] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_PLL_DIV_EN |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_PLL_POL_SEL[0] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[17] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[16] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[14] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[13] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[12] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[11] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[10] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[9] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[8] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[7] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[6] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[5] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[4] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[3] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[2] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[1] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_3[0] |
| Bit | Frame | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | |
| 40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:INV.P1CMDEN |
| 39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P1CMDCLK |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_WTR_VAL[2] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_WTR_VAL[1] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_WTR_VAL[0] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RTP_VAL[2] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RTP_VAL[1] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RTP_VAL[0] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_WR_VAL[2] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_WR_VAL[1] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_WR_VAL[0] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RP_VAL[3] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RP_VAL[2] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RP_VAL[1] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RP_VAL[0] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RFC_VAL[7] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RFC_VAL[6] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RFC_VAL[5] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RFC_VAL[4] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RFC_VAL[3] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RFC_VAL[2] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RFC_VAL[1] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RFC_VAL[0] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[17] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[16] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[14] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[13] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[12] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[11] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[10] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[9] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[8] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[7] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[6] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[5] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[4] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[3] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[2] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[1] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_2[0] |
| Bit | Frame | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | |
| 38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_REFI_VAL[11] |
| 37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_REFI_VAL[10] |
| 36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_REFI_VAL[9] |
| 35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_REFI_VAL[8] |
| 34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_REFI_VAL[7] |
| 33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_REFI_VAL[6] |
| 32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_REFI_VAL[5] |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_REFI_VAL[4] |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_REFI_VAL[3] |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_REFI_VAL[2] |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_REFI_VAL[1] |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_REFI_VAL[0] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RCD_VAL[2] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RCD_VAL[1] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RCD_VAL[0] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RAS_VAL[4] |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RAS_VAL[3] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RAS_VAL[2] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RAS_VAL[1] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_RAS_VAL[0] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[17] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[16] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[14] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[13] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[12] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[11] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[10] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[9] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[8] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[7] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[6] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[5] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[4] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[3] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[2] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[1] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_1[0] |
| Bit | Frame | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | |
| 31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:INV.P0CMDEN |
| 30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P0CMDCLK |
| 29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:PORT_CONFIG[2] |
| 26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:PORT_CONFIG[1] |
| 25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:PORT_CONFIG[0] |
| 24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_BURST_LEN[0] |
| 23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_BURST_LEN[1] |
| 22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_TYPE[0] |
| 20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_TYPE[1] |
| 19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_WIDTH[1] |
| 18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MEM_WIDTH[0] |
| 17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[17] |
| 16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[16] |
| 15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[15] |
| 14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[14] |
| 13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[13] |
| 12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[12] |
| 11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[11] |
| 10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[10] |
| 9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[9] |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[8] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[7] |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[6] |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[5] |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[4] |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[3] |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[2] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[1] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:ARB_TIME_SLOT_0[0] |
| Bit | Frame |
|---|
| Bit | Frame | |||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI0R.MEM_PLL_POL_SEL[0] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P0RDCLK |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P0RDEN |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI0R.MEM_PLL_DIV_EN |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI0R.MEM_WIDTH[1] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI0R.MEM_WIDTH[0] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI0R_PORT_CONFIG[0] |
| Bit | Frame |
|---|
| Bit | Frame | |||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI0W.MEM_PLL_POL_SEL[0] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P0WRCLK |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P0WREN |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI0W.MEM_PLL_DIV_EN |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI0W.MEM_WIDTH[1] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI0W.MEM_WIDTH[0] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI0W_PORT_CONFIG[0] |
| Bit | Frame |
|---|
| Bit | Frame | |||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI1R.MEM_PLL_POL_SEL[0] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P1RDCLK |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P1RDEN |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI1R.MEM_PLL_DIV_EN |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI1R.MEM_WIDTH[1] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI1R.MEM_WIDTH[0] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI1R_PORT_CONFIG[0] |
| Bit | Frame |
|---|
| Bit | Frame | |||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI1W.MEM_PLL_POL_SEL[0] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P1WRCLK |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P1WREN |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI1W.MEM_PLL_DIV_EN |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI1W.MEM_WIDTH[1] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI1W.MEM_WIDTH[0] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI1W_PORT_CONFIG[0] |
| Bit | Frame |
|---|
| Bit | Frame | |||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI0.MEM_PLL_POL_SEL[0] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P2CLK |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P2EN |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI0.MEM_PLL_DIV_EN |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI0.MEM_WIDTH[1] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI0.MEM_WIDTH[0] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI2_PORT_CONFIG[0] |
| Bit | Frame |
|---|
| Bit | Frame | |||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI1.MEM_PLL_POL_SEL[0] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P3CLK |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P3EN |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI1.MEM_PLL_DIV_EN |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI1.MEM_WIDTH[1] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI1.MEM_WIDTH[0] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI3_PORT_CONFIG[0] |
| Bit | Frame |
|---|
| Bit | Frame | |||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI2.MEM_PLL_POL_SEL[0] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P4CLK |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P4EN |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI2.MEM_PLL_DIV_EN |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI2.MEM_WIDTH[1] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI2.MEM_WIDTH[0] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI4_PORT_CONFIG[0] |
| Bit | Frame |
|---|
| Bit | Frame | |||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | |
| 8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI3.MEM_PLL_POL_SEL[0] |
| 7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P5CLK |
| 6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~MCB:INV.P5EN |
| 5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI3.MEM_PLL_DIV_EN |
| 4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| 2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI3.MEM_WIDTH[1] |
| 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI3.MEM_WIDTH[0] |
| 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | MCB:MUI5_PORT_CONFIG[0] |
| MCB:ARB_NUM_TIME_SLOTS | 8.22.26 |
|---|---|
| 10 | 0 |
| 12 | 1 |
| MCB:ARB_TIME_SLOT_0 | 11.22.17 | 11.22.16 | 11.22.15 | 11.22.14 | 11.22.13 | 11.22.12 | 11.22.11 | 11.22.10 | 11.22.9 | 11.22.8 | 11.22.7 | 11.22.6 | 11.22.5 | 11.22.4 | 11.22.3 | 11.22.2 | 11.22.1 | 11.22.0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCB:ARB_TIME_SLOT_1 | 10.22.17 | 10.22.16 | 10.22.15 | 10.22.14 | 10.22.13 | 10.22.12 | 10.22.11 | 10.22.10 | 10.22.9 | 10.22.8 | 10.22.7 | 10.22.6 | 10.22.5 | 10.22.4 | 10.22.3 | 10.22.2 | 10.22.1 | 10.22.0 |
| MCB:ARB_TIME_SLOT_10 | 1.22.17 | 1.22.16 | 1.22.15 | 1.22.14 | 1.22.13 | 1.22.12 | 1.22.11 | 1.22.10 | 1.22.9 | 1.22.8 | 1.22.7 | 1.22.6 | 1.22.5 | 1.22.4 | 1.22.3 | 1.22.2 | 1.22.1 | 1.22.0 |
| MCB:ARB_TIME_SLOT_11 | 0.22.17 | 0.22.16 | 0.22.15 | 0.22.14 | 0.22.13 | 0.22.12 | 0.22.11 | 0.22.10 | 0.22.9 | 0.22.8 | 0.22.7 | 0.22.6 | 0.22.5 | 0.22.4 | 0.22.3 | 0.22.2 | 0.22.1 | 0.22.0 |
| MCB:ARB_TIME_SLOT_2 | 9.22.17 | 9.22.16 | 9.22.15 | 9.22.14 | 9.22.13 | 9.22.12 | 9.22.11 | 9.22.10 | 9.22.9 | 9.22.8 | 9.22.7 | 9.22.6 | 9.22.5 | 9.22.4 | 9.22.3 | 9.22.2 | 9.22.1 | 9.22.0 |
| MCB:ARB_TIME_SLOT_3 | 8.22.17 | 8.22.16 | 8.22.15 | 8.22.14 | 8.22.13 | 8.22.12 | 8.22.11 | 8.22.10 | 8.22.9 | 8.22.8 | 8.22.7 | 8.22.6 | 8.22.5 | 8.22.4 | 8.22.3 | 8.22.2 | 8.22.1 | 8.22.0 |
| MCB:ARB_TIME_SLOT_4 | 7.22.17 | 7.22.16 | 7.22.15 | 7.22.14 | 7.22.13 | 7.22.12 | 7.22.11 | 7.22.10 | 7.22.9 | 7.22.8 | 7.22.7 | 7.22.6 | 7.22.5 | 7.22.4 | 7.22.3 | 7.22.2 | 7.22.1 | 7.22.0 |
| MCB:ARB_TIME_SLOT_5 | 6.22.17 | 6.22.16 | 6.22.15 | 6.22.14 | 6.22.13 | 6.22.12 | 6.22.11 | 6.22.10 | 6.22.9 | 6.22.8 | 6.22.7 | 6.22.6 | 6.22.5 | 6.22.4 | 6.22.3 | 6.22.2 | 6.22.1 | 6.22.0 |
| MCB:ARB_TIME_SLOT_6 | 5.22.17 | 5.22.16 | 5.22.15 | 5.22.14 | 5.22.13 | 5.22.12 | 5.22.11 | 5.22.10 | 5.22.9 | 5.22.8 | 5.22.7 | 5.22.6 | 5.22.5 | 5.22.4 | 5.22.3 | 5.22.2 | 5.22.1 | 5.22.0 |
| MCB:ARB_TIME_SLOT_7 | 4.22.17 | 4.22.16 | 4.22.15 | 4.22.14 | 4.22.13 | 4.22.12 | 4.22.11 | 4.22.10 | 4.22.9 | 4.22.8 | 4.22.7 | 4.22.6 | 4.22.5 | 4.22.4 | 4.22.3 | 4.22.2 | 4.22.1 | 4.22.0 |
| MCB:ARB_TIME_SLOT_8 | 3.22.17 | 3.22.16 | 3.22.15 | 3.22.14 | 3.22.13 | 3.22.12 | 3.22.11 | 3.22.10 | 3.22.9 | 3.22.8 | 3.22.7 | 3.22.6 | 3.22.5 | 3.22.4 | 3.22.3 | 3.22.2 | 3.22.1 | 3.22.0 |
| MCB:ARB_TIME_SLOT_9 | 2.22.17 | 2.22.16 | 2.22.15 | 2.22.14 | 2.22.13 | 2.22.12 | 2.22.11 | 2.22.10 | 2.22.9 | 2.22.8 | 2.22.7 | 2.22.6 | 2.22.5 | 2.22.4 | 2.22.3 | 2.22.2 | 2.22.1 | 2.22.0 |
| non-inverted | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| MCB:CAL_BA | 3.22.22 | 3.22.21 | 3.22.20 |
|---|---|---|---|
| MCB:MEM_RCD_VAL | 10.22.25 | 10.22.24 | 10.22.23 |
| MCB:MEM_RTP_VAL | 9.22.35 | 9.22.34 | 9.22.33 |
| MCB:MEM_WR_VAL | 9.22.32 | 9.22.31 | 9.22.30 |
| MCB:MEM_WTR_VAL | 9.22.38 | 9.22.37 | 9.22.36 |
| non-inverted | [2] | [1] | [0] |
| MCB:CAL_BYPASS | 3.22.19 |
|---|---|
| MCB:INV.P0CMDEN | 11.22.31 |
| MCB:INV.P1CMDEN | 9.22.40 |
| MCB:INV.P2CMDEN | 7.22.33 |
| MCB:INV.P3CMDEN | 5.22.33 |
| MCB:INV.P4CMDEN | 3.22.24 |
| MCB:INV.P5CMDEN | 1.22.31 |
| MCB:MEM_PLL_DIV_EN | 8.22.23 |
| MCB:MUI0.MEM_PLL_DIV_EN | 21.25.5 |
| MCB:MUI0R.MEM_PLL_DIV_EN | 13.25.5 |
| MCB:MUI0W.MEM_PLL_DIV_EN | 15.25.5 |
| MCB:MUI1.MEM_PLL_DIV_EN | 23.25.5 |
| MCB:MUI1R.MEM_PLL_DIV_EN | 17.25.5 |
| MCB:MUI1W.MEM_PLL_DIV_EN | 19.25.5 |
| MCB:MUI2.MEM_PLL_DIV_EN | 25.25.5 |
| MCB:MUI3.MEM_PLL_DIV_EN | 27.25.5 |
| non-inverted | [0] |
| MCB:CAL_CA | 1.22.29 | 1.22.28 | 1.22.27 | 1.22.26 | 1.22.25 | 1.22.24 | 1.22.23 | 1.22.22 | 1.22.21 | 1.22.20 | 1.22.19 | 1.22.18 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCB:MEM_REFI_VAL | 10.22.38 | 10.22.37 | 10.22.36 | 10.22.35 | 10.22.34 | 10.22.33 | 10.22.32 | 10.22.31 | 10.22.30 | 10.22.29 | 10.22.28 | 10.22.27 |
| non-inverted | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| MCB:CAL_CALIBRATION_MODE | 0.22.21 |
|---|---|
| CALIBRATION | 0 |
| NOCALIBRATION | 1 |
| MCB:CAL_CLK_DIV | 0.22.19 | 0.22.18 |
|---|---|---|
| 1 | 0 | 0 |
| 2 | 0 | 1 |
| 4 | 1 | 0 |
| 8 | 1 | 1 |
| MCB:CAL_DELAY | 0.22.23 | 0.22.22 |
|---|---|---|
| QUARTER | 0 | 0 |
| HALF | 0 | 1 |
| THREEQUARTER | 1 | 0 |
| FULL | 1 | 1 |
| MCB:CAL_RA | 2.22.32 | 2.22.31 | 2.22.30 | 2.22.29 | 2.22.28 | 2.22.27 | 2.22.26 | 2.22.25 | 2.22.24 | 2.22.23 | 2.22.22 | 2.22.21 | 2.22.20 | 2.22.19 | 2.22.18 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| non-inverted | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| MCB:EMR1 | 6.22.31 | 6.22.30 | 6.22.29 | 6.22.28 | 6.22.27 | 6.22.26 | 6.22.25 | 6.22.24 | 6.22.23 | 6.22.22 | 6.22.21 | 6.22.20 | 6.22.19 | 6.22.18 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCB:EMR2 | 5.22.31 | 5.22.30 | 5.22.29 | 5.22.28 | 5.22.27 | 5.22.26 | 5.22.25 | 5.22.24 | 5.22.23 | 5.22.22 | 5.22.21 | 5.22.20 | 5.22.19 | 5.22.18 |
| MCB:EMR3 | 4.22.31 | 4.22.30 | 4.22.29 | 4.22.28 | 4.22.27 | 4.22.26 | 4.22.25 | 4.22.24 | 4.22.23 | 4.22.22 | 4.22.21 | 4.22.20 | 4.22.19 | 4.22.18 |
| MCB:MR | 7.22.31 | 7.22.30 | 7.22.29 | 7.22.28 | 7.22.27 | 7.22.26 | 7.22.25 | 7.22.24 | 7.22.23 | 7.22.22 | 7.22.21 | 7.22.20 | 7.22.19 | 7.22.18 |
| non-inverted | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| MCB:INV.P0CMDCLK | 11.22.30 |
|---|---|
| MCB:INV.P0RDCLK | 13.25.7 |
| MCB:INV.P0RDEN | 13.25.6 |
| MCB:INV.P0WRCLK | 15.25.7 |
| MCB:INV.P0WREN | 15.25.6 |
| MCB:INV.P1CMDCLK | 9.22.39 |
| MCB:INV.P1RDCLK | 17.25.7 |
| MCB:INV.P1RDEN | 17.25.6 |
| MCB:INV.P1WRCLK | 19.25.7 |
| MCB:INV.P1WREN | 19.25.6 |
| MCB:INV.P2CLK | 21.25.7 |
| MCB:INV.P2CMDCLK | 7.22.32 |
| MCB:INV.P2EN | 21.25.6 |
| MCB:INV.P3CLK | 23.25.7 |
| MCB:INV.P3CMDCLK | 5.22.32 |
| MCB:INV.P3EN | 23.25.6 |
| MCB:INV.P4CLK | 25.25.7 |
| MCB:INV.P4CMDCLK | 3.22.23 |
| MCB:INV.P4EN | 25.25.6 |
| MCB:INV.P5CLK | 27.25.7 |
| MCB:INV.P5CMDCLK | 1.22.30 |
| MCB:INV.P5EN | 27.25.6 |
| inverted | ~[0] |
| MCB:MEM_ADDR_ORDER | 8.22.32 |
|---|---|
| BANK_ROW_COLUMN | 0 |
| ROW_BANK_COLUMN | 1 |
| MCB:MEM_BA_SIZE | 8.22.27 |
|---|---|
| 2 | 0 |
| 3 | 1 |
| MCB:MEM_BURST_LEN | 11.22.23 | 11.22.24 |
|---|---|---|
| MCB:MEM_DDR_DDR2_MDDR_BURST_LEN | 7.22.18 | 7.22.19 |
| 4 | 0 | 1 |
| 8 | 1 | 1 |
| MCB:MEM_CAS_LATENCY | 7.22.24 | 7.22.23 | 7.22.22 |
|---|---|---|---|
| 1 | 0 | 0 | 1 |
| 2 | 0 | 1 | 0 |
| 3 | 0 | 1 | 1 |
| 4 | 1 | 0 | 0 |
| 5 | 1 | 0 | 1 |
| 6 | 1 | 1 | 0 |
| MCB:MEM_CA_SIZE | 8.22.31 | 8.22.30 |
|---|---|---|
| 9 | 0 | 0 |
| 10 | 0 | 1 |
| 11 | 1 | 0 |
| 12 | 1 | 1 |
| MCB:MEM_DDR1_2_ODS | 6.22.19 |
|---|---|
| FULL | 0 |
| REDUCED | 1 |
| MCB:MEM_DDR2_3_HIGH_TEMP_SR | 5.22.25 |
|---|---|
| NORMAL | 0 |
| EXTENDED | 1 |
| MCB:MEM_DDR2_3_PA_SR | 5.22.20 | 5.22.19 | 5.22.18 |
|---|---|---|---|
| FULL | 0 | 0 | 0 |
| HALF1 | 0 | 0 | 1 |
| QUARTER1 | 0 | 1 | 0 |
| EIGHTH1 | 0 | 1 | 1 |
| THREEQUARTER | 1 | 0 | 0 |
| HALF2 | 1 | 0 | 1 |
| QUARTER2 | 1 | 1 | 0 |
| EIGHTH2 | 1 | 1 | 1 |
| MCB:MEM_DDR2_ADD_LATENCY | 6.22.23 | 6.22.22 | 6.22.21 |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 |
| 2 | 0 | 1 | 0 |
| 3 | 0 | 1 | 1 |
| 4 | 1 | 0 | 0 |
| 5 | 1 | 0 | 1 |
| MCB:MEM_DDR2_DIFF_DQS_EN | 6.22.28 |
|---|---|
| YES | 0 |
| NO | 1 |
| MCB:MEM_DDR2_RTT | 6.22.24 | 6.22.20 |
|---|---|---|
| NONE | 0 | 0 |
| 75OHMS | 0 | 1 |
| 150OHMS | 1 | 0 |
| 50OHMS | 1 | 1 |
| MCB:MEM_DDR2_WRT_RECOVERY | 7.22.29 | 7.22.28 | 7.22.27 |
|---|---|---|---|
| 2 | 0 | 0 | 1 |
| 3 | 0 | 1 | 0 |
| 4 | 0 | 1 | 1 |
| 5 | 1 | 0 | 0 |
| 6 | 1 | 0 | 1 |
| MCB:MEM_DDR3_ADD_LATENCY | 6.22.22 | 6.22.21 |
|---|---|---|
| NONE | 0 | 0 |
| CL1 | 0 | 1 |
| CL2 | 1 | 0 |
| MCB:MEM_DDR3_AUTO_SR | 5.22.24 |
|---|---|
| MANUAL | 0 |
| ENABLED | 1 |
| MCB:MEM_DDR3_CAS_LATENCY | 7.22.24 | 7.22.23 | 7.22.22 |
|---|---|---|---|
| 5 | 0 | 0 | 1 |
| 6 | 0 | 1 | 0 |
| 7 | 0 | 1 | 1 |
| 8 | 1 | 0 | 0 |
| 9 | 1 | 0 | 1 |
| 10 | 1 | 1 | 0 |
| MCB:MEM_DDR3_CAS_WR_LATENCY | 5.22.22 | 5.22.21 |
|---|---|---|
| 5 | 0 | 0 |
| 6 | 0 | 1 |
| 7 | 1 | 0 |
| 8 | 1 | 1 |
| MCB:MEM_DDR3_DYN_WRT_ODT | 5.22.28 | 5.22.27 |
|---|---|---|
| NONE | 0 | 0 |
| DIV2 | 0 | 1 |
| DIV4 | 1 | 0 |
| MCB:MEM_DDR3_ODS | 6.22.19 |
|---|---|
| DIV6 | 0 |
| DIV7 | 1 |
| MCB:MEM_DDR3_RTT | 6.22.27 | 6.22.20 | 6.22.24 |
|---|---|---|---|
| NONE | 0 | 0 | 0 |
| DIV2 | 0 | 0 | 1 |
| DIV4 | 0 | 1 | 0 |
| DIV6 | 0 | 1 | 1 |
| DIV8 | 1 | 0 | 0 |
| DIV12 | 1 | 1 | 0 |
| MCB:MEM_DDR3_WRT_RECOVERY | 7.22.29 | 7.22.28 | 7.22.27 |
|---|---|---|---|
| 5 | 0 | 0 | 1 |
| 6 | 0 | 1 | 0 |
| 7 | 0 | 1 | 1 |
| 8 | 1 | 0 | 0 |
| 10 | 1 | 0 | 1 |
| 12 | 1 | 1 | 0 |
| MCB:MEM_MDDR_ODS | 6.22.25 | 6.22.23 | 6.22.24 |
|---|---|---|---|
| FULL | 0 | 0 | 0 |
| QUARTER | 0 | 0 | 1 |
| HALF | 0 | 1 | 0 |
| THREEQUARTERS | 1 | 0 | 0 |
| MCB:MEM_MOBILE_PA_SR | 6.22.18 |
|---|---|
| FULL | 0 |
| HALF | 1 |
| MCB:MEM_MOBILE_TC_SR | 6.22.22 | 6.22.21 |
|---|---|---|
| 0 | 0 | 0 |
| 1 | 0 | 1 |
| 2 | 1 | 0 |
| 3 | 1 | 1 |
| MCB:MEM_PLL_POL_SEL | 8.22.22 |
|---|---|
| MCB:MUI0.MEM_PLL_POL_SEL | 21.25.8 |
| MCB:MUI0R.MEM_PLL_POL_SEL | 13.25.8 |
| MCB:MUI0W.MEM_PLL_POL_SEL | 15.25.8 |
| MCB:MUI1.MEM_PLL_POL_SEL | 23.25.8 |
| MCB:MUI1R.MEM_PLL_POL_SEL | 17.25.8 |
| MCB:MUI1W.MEM_PLL_POL_SEL | 19.25.8 |
| MCB:MUI2.MEM_PLL_POL_SEL | 25.25.8 |
| MCB:MUI3.MEM_PLL_POL_SEL | 27.25.8 |
| INVERTED | 0 |
| NOTINVERTED | 1 |
| MCB:MEM_RAS_VAL | 10.22.22 | 10.22.21 | 10.22.20 | 10.22.19 | 10.22.18 |
|---|---|---|---|---|---|
| non-inverted | [4] | [3] | [2] | [1] | [0] |
| MCB:MEM_RA_SIZE | 8.22.29 | 8.22.28 |
|---|---|---|
| 12 | 0 | 0 |
| 13 | 0 | 1 |
| 14 | 1 | 0 |
| 15 | 1 | 1 |
| MCB:MEM_RFC_VAL | 9.22.25 | 9.22.24 | 9.22.23 | 9.22.22 | 9.22.21 | 9.22.20 | 9.22.19 | 9.22.18 |
|---|---|---|---|---|---|---|---|---|
| non-inverted | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| MCB:MEM_RP_VAL | 9.22.29 | 9.22.28 | 9.22.27 | 9.22.26 |
|---|---|---|---|---|
| non-inverted | [3] | [2] | [1] | [0] |
| MCB:MEM_TYPE | 11.22.20 | 11.22.21 |
|---|---|---|
| DDR3 | 0 | 0 |
| DDR | 0 | 1 |
| DDR2 | 1 | 0 |
| MDDR | 1 | 1 |
| MCB:MEM_WIDTH | 11.22.19 | 11.22.18 |
|---|---|---|
| MCB:MUI0.MEM_WIDTH | 21.25.2 | 21.25.1 |
| MCB:MUI0R.MEM_WIDTH | 13.25.2 | 13.25.1 |
| MCB:MUI0W.MEM_WIDTH | 15.25.2 | 15.25.1 |
| MCB:MUI1.MEM_WIDTH | 23.25.2 | 23.25.1 |
| MCB:MUI1R.MEM_WIDTH | 17.25.2 | 17.25.1 |
| MCB:MUI1W.MEM_WIDTH | 19.25.2 | 19.25.1 |
| MCB:MUI2.MEM_WIDTH | 25.25.2 | 25.25.1 |
| MCB:MUI3.MEM_WIDTH | 27.25.2 | 27.25.1 |
| 4 | 0 | 1 |
| 8 | 1 | 0 |
| 16 | 1 | 1 |
| MCB:MUI0R_PORT_CONFIG | 13.25.0 |
|---|---|
| MCB:MUI0W_PORT_CONFIG | 15.25.0 |
| MCB:MUI1R_PORT_CONFIG | 17.25.0 |
| MCB:MUI1W_PORT_CONFIG | 19.25.0 |
| MCB:MUI2_PORT_CONFIG | 21.25.0 |
| MCB:MUI3_PORT_CONFIG | 23.25.0 |
| MCB:MUI4_PORT_CONFIG | 25.25.0 |
| MCB:MUI5_PORT_CONFIG | 27.25.0 |
| WRITE | 0 |
| READ | 1 |
| MCB:PORT_CONFIG | 11.22.27 | 11.22.26 | 11.22.25 |
|---|---|---|---|
| B32_B32_X32_X32_X32_X32 | 0 | 0 | 0 |
| B32_B32_B32_B32 | 0 | 0 | 1 |
| B64_B32_B32 | 0 | 1 | 0 |
| B64_B64 | 0 | 1 | 1 |
| B128 | 1 | 0 | 0 |