Global buffers

TODO: document

Bitstream

The CLK_S* tiles use two bitstream tiles:

tile 0: 4×80 tile located in the clock spine column, in the bits corresponding to the bottom interconnect row
tile 1: 4×16 tile located in the clock spine column, in the bits corresponding to the low special area (used for bottom IOB tiles and clock rows in normal columns)

The CLK_N* tiles use two bitstream tiles:

tile 0: 4×80 tile located in the clock spine column, in the bits corresponding to the top interconnect row
tile 1: 4×16 tile located in the clock spine column, in the bits corresponding to the high special area (used for top IOB tiles and clock rows in normal columns)

Each tile comes in three variants:

*_V2: used on Virtex 2 devices
*_V2P: used on Virtex 2 Pro devices with GT transceivers
*_V2PX: used on Virtex 2 Pro X devices with GT10 transceivers

Tile CLK_S_V2

Cells: 2

Switchbox CLK_INT

virtex2 CLK_S_V2 switchbox CLK_INT muxes OMUX_N10
Bits	Destination
CELL[0].OMUX_N10
CELL[1].OMUX_N10
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_S_V2 switchbox CLK_INT muxes OMUX_N11
Bits	Destination
CELL[0].OMUX_N11
CELL[1].OMUX_N11
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_S_V2 switchbox CLK_INT muxes OMUX_N12
Bits	Destination
CELL[0].OMUX_N12
CELL[1].OMUX_N12
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_S_V2 switchbox CLK_INT muxes OMUX_N15
Bits	Destination
CELL[0].OMUX_N15
CELL[1].OMUX_N15
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_S_V2 switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[0]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_S_V2 switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[1]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_S_V2 switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[2]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_S_V2 switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[3]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_S_V2 switchbox CLK_INT muxes IMUX_BUFG_CLK[4]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[4]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_S_V2 switchbox CLK_INT muxes IMUX_BUFG_CLK[5]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[5]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_S_V2 switchbox CLK_INT muxes IMUX_BUFG_CLK[6]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[6]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_S_V2 switchbox CLK_INT muxes IMUX_BUFG_CLK[7]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[7]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_S_V2 switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[0]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_S_V2 switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[1]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_S_V2 switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[2]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_S_V2 switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[3]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_S_V2 switchbox CLK_INT muxes IMUX_BUFG_SEL[4]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[4]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_S_V2 switchbox CLK_INT muxes IMUX_BUFG_SEL[5]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[5]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_S_V2 switchbox CLK_INT muxes IMUX_BUFG_SEL[6]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[6]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_S_V2 switchbox CLK_INT muxes IMUX_BUFG_SEL[7]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[7]
	Source
CELL[1].DBL_W0[9]

Bel BUFGMUX[0]

virtex2 CLK_S_V2 bel BUFGMUX[0]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[0]
O	output	CELL[0].OUT_BUFG[0]
S	input	CELL[0].IMUX_BUFG_SEL[0]

Bel BUFGMUX[1]

virtex2 CLK_S_V2 bel BUFGMUX[1]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[1]
O	output	CELL[0].OUT_BUFG[1]
S	input	CELL[0].IMUX_BUFG_SEL[1]

Bel BUFGMUX[2]

virtex2 CLK_S_V2 bel BUFGMUX[2]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[2]
O	output	CELL[0].OUT_BUFG[2]
S	input	CELL[0].IMUX_BUFG_SEL[2]

Bel BUFGMUX[3]

virtex2 CLK_S_V2 bel BUFGMUX[3]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[3]
O	output	CELL[0].OUT_BUFG[3]
S	input	CELL[0].IMUX_BUFG_SEL[3]

Bel BUFGMUX[4]

virtex2 CLK_S_V2 bel BUFGMUX[4]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[4]
O	output	CELL[0].OUT_BUFG[4]
S	input	CELL[0].IMUX_BUFG_SEL[4]

Bel BUFGMUX[5]

virtex2 CLK_S_V2 bel BUFGMUX[5]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[5]
O	output	CELL[0].OUT_BUFG[5]
S	input	CELL[0].IMUX_BUFG_SEL[5]

Bel BUFGMUX[6]

virtex2 CLK_S_V2 bel BUFGMUX[6]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[6]
O	output	CELL[0].OUT_BUFG[6]
S	input	CELL[0].IMUX_BUFG_SEL[6]

Bel BUFGMUX[7]

virtex2 CLK_S_V2 bel BUFGMUX[7]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[7]
O	output	CELL[0].OUT_BUFG[7]
S	input	CELL[0].IMUX_BUFG_SEL[7]

Bel GLOBALSIG_S[0]

virtex2 CLK_S_V2 bel GLOBALSIG_S[0]
Pin	Direction	Wires

Bel GLOBALSIG_S[1]

virtex2 CLK_S_V2 bel GLOBALSIG_S[1]
Pin	Direction	Wires

Bel wires

virtex2 CLK_S_V2 bel wires
Wire	Pins
CELL[0].IMUX_BUFG_CLK[0]	BUFGMUX[0].CLK
CELL[0].IMUX_BUFG_CLK[1]	BUFGMUX[1].CLK
CELL[0].IMUX_BUFG_CLK[2]	BUFGMUX[2].CLK
CELL[0].IMUX_BUFG_CLK[3]	BUFGMUX[3].CLK
CELL[0].IMUX_BUFG_CLK[4]	BUFGMUX[4].CLK
CELL[0].IMUX_BUFG_CLK[5]	BUFGMUX[5].CLK
CELL[0].IMUX_BUFG_CLK[6]	BUFGMUX[6].CLK
CELL[0].IMUX_BUFG_CLK[7]	BUFGMUX[7].CLK
CELL[0].IMUX_BUFG_SEL[0]	BUFGMUX[0].S
CELL[0].IMUX_BUFG_SEL[1]	BUFGMUX[1].S
CELL[0].IMUX_BUFG_SEL[2]	BUFGMUX[2].S
CELL[0].IMUX_BUFG_SEL[3]	BUFGMUX[3].S
CELL[0].IMUX_BUFG_SEL[4]	BUFGMUX[4].S
CELL[0].IMUX_BUFG_SEL[5]	BUFGMUX[5].S
CELL[0].IMUX_BUFG_SEL[6]	BUFGMUX[6].S
CELL[0].IMUX_BUFG_SEL[7]	BUFGMUX[7].S
CELL[0].OUT_BUFG[0]	BUFGMUX[0].O
CELL[0].OUT_BUFG[1]	BUFGMUX[1].O
CELL[0].OUT_BUFG[2]	BUFGMUX[2].O
CELL[0].OUT_BUFG[3]	BUFGMUX[3].O
CELL[0].OUT_BUFG[4]	BUFGMUX[4].O
CELL[0].OUT_BUFG[5]	BUFGMUX[5].O
CELL[0].OUT_BUFG[6]	BUFGMUX[6].O
CELL[0].OUT_BUFG[7]	BUFGMUX[7].O

Bitstream

virtex2 CLK_S_V2 rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3
B79	-	-	-	-
B78	-	-	-	-
B77	-	-	-	-
B76	-	-	-	-
B75	-	-	-	-
B74	-	-	-	-
B73	-	-	-	-
B72	-	-	-	-
B71	-	-	-	-
B70	-	-	-	-
B69	-	-	-	-
B68	-	-	-	-
B67	-	-	-	-
B66	-	-	-	-
B65	-	-	-	-
B64	-	-	-	-
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex2 CLK_S_V2 rect TERM
Bit	Frame
Bit	F0	F1	F2	F3
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

### Bitstream

virtex2 CLK_S_V2 rect R0
Bit	Frame
Bit	F0	F1	F2	F3
B76	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][5]
B75	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][0]
B74	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][1]
B73	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][2]
B72	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][3]
B71	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][4]
B70	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[3]	~CLK_INT:INV.0.IMUX_BUFG_SEL[7]	-
B69	-	-	-	-
B68	-	-	-	-
B67	-	-	-	-
B66	-	-	-	-
B65	-	-	-	-
B64	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][5]
B63	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][0]
B62	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][1]
B61	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][2]
B60	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][3]
B59	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][4]
B58	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[2]	~CLK_INT:INV.0.IMUX_BUFG_SEL[6]	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][5]
B51	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][0]
B50	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][1]
B49	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][2]
B48	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][3]
B47	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][4]
B46	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[1]	~CLK_INT:INV.0.IMUX_BUFG_SEL[5]	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][5]
B39	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][0]
B38	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][1]
B37	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][2]
B36	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][3]
B35	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][4]
B34	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[0]	~CLK_INT:INV.0.IMUX_BUFG_SEL[4]	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	CLK_INT:MUX.1.OMUX_N10[4]	CLK_INT:MUX.1.OMUX_N11[0]	CLK_INT:MUX.0.OMUX_N11[0]	CLK_INT:MUX.0.OMUX_N10[4]
B27	CLK_INT:MUX.1.OMUX_N10[0]	CLK_INT:MUX.1.OMUX_N11[1]	CLK_INT:MUX.0.OMUX_N11[1]	CLK_INT:MUX.0.OMUX_N10[0]
B26	CLK_INT:MUX.1.OMUX_N10[1]	CLK_INT:MUX.1.OMUX_N11[2]	CLK_INT:MUX.0.OMUX_N11[2]	CLK_INT:MUX.0.OMUX_N10[1]
B25	CLK_INT:MUX.1.OMUX_N10[2]	CLK_INT:MUX.1.OMUX_N11[3]	CLK_INT:MUX.0.OMUX_N11[3]	CLK_INT:MUX.0.OMUX_N10[2]
B24	CLK_INT:MUX.1.OMUX_N10[3]	CLK_INT:MUX.1.OMUX_N11[4]	CLK_INT:MUX.0.OMUX_N11[4]	CLK_INT:MUX.0.OMUX_N10[3]
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	CLK_INT:MUX.1.OMUX_N12[4]	CLK_INT:MUX.1.OMUX_N15[0]	CLK_INT:MUX.0.OMUX_N15[0]	CLK_INT:MUX.0.OMUX_N12[4]
B17	CLK_INT:MUX.1.OMUX_N12[0]	CLK_INT:MUX.1.OMUX_N15[1]	CLK_INT:MUX.0.OMUX_N15[1]	CLK_INT:MUX.0.OMUX_N12[0]
B16	CLK_INT:MUX.1.OMUX_N12[1]	CLK_INT:MUX.1.OMUX_N15[2]	CLK_INT:MUX.0.OMUX_N15[2]	CLK_INT:MUX.0.OMUX_N12[1]
B15	CLK_INT:MUX.1.OMUX_N12[2]	CLK_INT:MUX.1.OMUX_N15[3]	CLK_INT:MUX.0.OMUX_N15[3]	CLK_INT:MUX.0.OMUX_N12[2]
B14	CLK_INT:MUX.1.OMUX_N12[3]	CLK_INT:MUX.1.OMUX_N15[4]	CLK_INT:MUX.0.OMUX_N15[4]	CLK_INT:MUX.0.OMUX_N12[3]
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	BUFGMUX[0]:MUX.CLK[0]	-	-	BUFGMUX[4]:MUX.CLK[0]
B9	BUFGMUX[0]:MUX.CLK[3]	-	-	BUFGMUX[4]:MUX.CLK[3]
B8	BUFGMUX[0]:MUX.CLK[2]	-	-	BUFGMUX[4]:MUX.CLK[2]
B7	BUFGMUX[0]:MUX.CLK[1]	-	-	BUFGMUX[4]:MUX.CLK[1]
B6	BUFGMUX[0]:DISABLE_ATTR[0]	-	-	BUFGMUX[4]:DISABLE_ATTR[0]
B5	BUFGMUX[1]:DISABLE_ATTR[0]	-	-	BUFGMUX[5]:DISABLE_ATTR[0]
B4	BUFGMUX[1]:MUX.CLK[1]	-	-	BUFGMUX[5]:MUX.CLK[1]
B3	BUFGMUX[1]:MUX.CLK[2]	-	-	BUFGMUX[5]:MUX.CLK[2]
B2	BUFGMUX[1]:MUX.CLK[3]	-	-	BUFGMUX[5]:MUX.CLK[3]
B1	BUFGMUX[1]:MUX.CLK[0]	-	-	BUFGMUX[5]:MUX.CLK[0]
B0	BUFGMUX[2]:MUX.CLK[0]	-	-	BUFGMUX[6]:MUX.CLK[0]

virtex2 CLK_S_V2 rect R1
Bit	Frame
Bit	F0	F1	F2	F3
B15	BUFGMUX[2]:MUX.CLK[3]	-	-	BUFGMUX[6]:MUX.CLK[3]
B14	BUFGMUX[2]:MUX.CLK[2]	-	-	BUFGMUX[6]:MUX.CLK[2]
B13	BUFGMUX[2]:MUX.CLK[1]	-	-	BUFGMUX[6]:MUX.CLK[1]
B12	BUFGMUX[2]:DISABLE_ATTR[0]	-	-	BUFGMUX[6]:DISABLE_ATTR[0]
B11	BUFGMUX[3]:DISABLE_ATTR[0]	-	-	BUFGMUX[7]:DISABLE_ATTR[0]
B10	BUFGMUX[3]:MUX.CLK[1]	-	-	BUFGMUX[7]:MUX.CLK[1]
B9	BUFGMUX[3]:MUX.CLK[2]	-	-	BUFGMUX[7]:MUX.CLK[2]
B8	BUFGMUX[3]:MUX.CLK[3]	-	-	BUFGMUX[7]:MUX.CLK[3]
B7	BUFGMUX[3]:MUX.CLK[0]	-	-	BUFGMUX[7]:MUX.CLK[0]
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

BUFGMUX[0]:DISABLE_ATTR	0.F0.B6
BUFGMUX[1]:DISABLE_ATTR	0.F0.B5
BUFGMUX[2]:DISABLE_ATTR	1.F0.B12
BUFGMUX[3]:DISABLE_ATTR	1.F0.B11
BUFGMUX[4]:DISABLE_ATTR	0.F3.B6
BUFGMUX[5]:DISABLE_ATTR	0.F3.B5
BUFGMUX[6]:DISABLE_ATTR	1.F3.B12
BUFGMUX[7]:DISABLE_ATTR	1.F3.B11
LOW	0
HIGH	1

BUFGMUX[0]:MUX.CLK	0.F0.B9	0.F0.B8	0.F0.B7	0.F0.B10
BUFGMUX[1]:MUX.CLK	0.F0.B2	0.F0.B3	0.F0.B4	0.F0.B1
BUFGMUX[2]:MUX.CLK	1.F0.B15	1.F0.B14	1.F0.B13	0.F0.B0
BUFGMUX[3]:MUX.CLK	1.F0.B8	1.F0.B9	1.F0.B10	1.F0.B7
BUFGMUX[4]:MUX.CLK	0.F3.B9	0.F3.B8	0.F3.B7	0.F3.B10
BUFGMUX[5]:MUX.CLK	0.F3.B2	0.F3.B3	0.F3.B4	0.F3.B1
BUFGMUX[6]:MUX.CLK	1.F3.B15	1.F3.B14	1.F3.B13	0.F3.B0
BUFGMUX[7]:MUX.CLK	1.F3.B8	1.F3.B9	1.F3.B10	1.F3.B7
INT	0	0	0	1
CKI	0	0	1	0
DCM_OUT_L	0	1	0	0
DCM_OUT_R	1	0	0	0

CLK_INT:INV.0.IMUX_BUFG_SEL[0]	0.F1.B34
CLK_INT:INV.0.IMUX_BUFG_SEL[1]	0.F1.B46
CLK_INT:INV.0.IMUX_BUFG_SEL[2]	0.F1.B58
CLK_INT:INV.0.IMUX_BUFG_SEL[3]	0.F1.B70
CLK_INT:INV.0.IMUX_BUFG_SEL[4]	0.F2.B34
CLK_INT:INV.0.IMUX_BUFG_SEL[5]	0.F2.B46
CLK_INT:INV.0.IMUX_BUFG_SEL[6]	0.F2.B58
CLK_INT:INV.0.IMUX_BUFG_SEL[7]	0.F2.B70
inverted	~[0]

CLK_INT:MUX.0.IMUX_BUFG_CLK[0]	0.F0.B40	0.F0.B35	0.F0.B36	0.F0.B37	0.F0.B38	0.F0.B39
CLK_INT:MUX.0.IMUX_BUFG_CLK[4]	0.F3.B40	0.F3.B35	0.F3.B36	0.F3.B37	0.F3.B38	0.F3.B39
CLK_INT:MUX.0.IMUX_BUFG_SEL[0]	0.F1.B35	0.F1.B36	0.F1.B37	0.F1.B38	0.F1.B39	0.F1.B40
CLK_INT:MUX.0.IMUX_BUFG_SEL[4]	0.F2.B35	0.F2.B36	0.F2.B37	0.F2.B38	0.F2.B39	0.F2.B40
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[0]	0	0	0	0	0	1
0.DBL_W2[1]	0	0	0	0	1	0
0.DBL_W2[2]	0	0	0	1	0	0
1.DBL_W0[0]	0	0	1	0	0	0
1.DBL_W0[1]	0	1	0	0	0	0
0.DBL_E0[0]	1	0	0	0	0	1
0.DBL_E0[1]	1	0	0	0	1	0
0.DBL_E0[2]	1	0	0	1	0	0
0.DBL_E1[0]	1	0	1	0	0	0
0.DBL_E1[1]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[1]	0.F0.B52	0.F0.B47	0.F0.B48	0.F0.B49	0.F0.B50	0.F0.B51
CLK_INT:MUX.0.IMUX_BUFG_CLK[5]	0.F3.B52	0.F3.B47	0.F3.B48	0.F3.B49	0.F3.B50	0.F3.B51
CLK_INT:MUX.0.IMUX_BUFG_SEL[1]	0.F1.B47	0.F1.B48	0.F1.B49	0.F1.B50	0.F1.B51	0.F1.B52
CLK_INT:MUX.0.IMUX_BUFG_SEL[5]	0.F2.B47	0.F2.B48	0.F2.B49	0.F2.B50	0.F2.B51	0.F2.B52
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[3]	0	0	0	0	0	1
0.DBL_W2[4]	0	0	0	0	1	0
1.DBL_W0[2]	0	0	0	1	0	0
1.DBL_W0[3]	0	0	1	0	0	0
1.DBL_W0[4]	0	1	0	0	0	0
0.DBL_E0[3]	1	0	0	0	0	1
0.DBL_E0[4]	1	0	0	0	1	0
0.DBL_E1[2]	1	0	0	1	0	0
0.DBL_E1[3]	1	0	1	0	0	0
0.DBL_E1[4]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[2]	0.F0.B64	0.F0.B59	0.F0.B60	0.F0.B61	0.F0.B62	0.F0.B63
CLK_INT:MUX.0.IMUX_BUFG_CLK[6]	0.F3.B64	0.F3.B59	0.F3.B60	0.F3.B61	0.F3.B62	0.F3.B63
CLK_INT:MUX.0.IMUX_BUFG_SEL[2]	0.F1.B59	0.F1.B60	0.F1.B61	0.F1.B62	0.F1.B63	0.F1.B64
CLK_INT:MUX.0.IMUX_BUFG_SEL[6]	0.F2.B59	0.F2.B60	0.F2.B61	0.F2.B62	0.F2.B63	0.F2.B64
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[5]	0	0	0	0	0	1
0.DBL_W2[6]	0	0	0	0	1	0
0.DBL_W2[7]	0	0	0	1	0	0
1.DBL_W0[5]	0	0	1	0	0	0
1.DBL_W0[6]	0	1	0	0	0	0
0.DBL_E0[5]	1	0	0	0	0	1
0.DBL_E0[6]	1	0	0	0	1	0
0.DBL_E0[7]	1	0	0	1	0	0
0.DBL_E1[5]	1	0	1	0	0	0
0.DBL_E1[6]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[3]	0.F0.B76	0.F0.B71	0.F0.B72	0.F0.B73	0.F0.B74	0.F0.B75
CLK_INT:MUX.0.IMUX_BUFG_CLK[7]	0.F3.B76	0.F3.B71	0.F3.B72	0.F3.B73	0.F3.B74	0.F3.B75
CLK_INT:MUX.0.IMUX_BUFG_SEL[3]	0.F1.B71	0.F1.B72	0.F1.B73	0.F1.B74	0.F1.B75	0.F1.B76
CLK_INT:MUX.0.IMUX_BUFG_SEL[7]	0.F2.B71	0.F2.B72	0.F2.B73	0.F2.B74	0.F2.B75	0.F2.B76
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[8]	0	0	0	0	0	1
0.DBL_W2[9]	0	0	0	0	1	0
1.DBL_W0[7]	0	0	0	1	0	0
1.DBL_W0[8]	0	0	1	0	0	0
1.DBL_W0[9]	0	1	0	0	0	0
0.DBL_E0[8]	1	0	0	0	0	1
0.DBL_E0[9]	1	0	0	0	1	0
0.DBL_E1[7]	1	0	0	1	0	0
0.DBL_E1[8]	1	0	1	0	0	0
0.DBL_E1[9]	1	1	0	0	0	0

CLK_INT:MUX.0.OMUX_N10	0.F3.B28	0.F3.B24	0.F3.B25	0.F3.B26	0.F3.B27
CLK_INT:MUX.0.OMUX_N11	0.F2.B24	0.F2.B25	0.F2.B26	0.F2.B27	0.F2.B28
CLK_INT:MUX.0.OMUX_N12	0.F3.B18	0.F3.B14	0.F3.B15	0.F3.B16	0.F3.B17
CLK_INT:MUX.0.OMUX_N15	0.F2.B14	0.F2.B15	0.F2.B16	0.F2.B17	0.F2.B18
NONE	0	0	0	0	0
0.OUT_BUFG[0]	0	0	0	0	1
0.OUT_BUFG[1]	0	0	0	1	0
0.OUT_BUFG[2]	0	0	1	0	0
0.OUT_BUFG[3]	0	1	0	0	0
0.OUT_BUFG[4]	1	0	0	0	1
0.OUT_BUFG[5]	1	0	0	1	0
0.OUT_BUFG[6]	1	0	1	0	0
0.OUT_BUFG[7]	1	1	0	0	0

CLK_INT:MUX.1.OMUX_N10	0.F0.B28	0.F0.B24	0.F0.B25	0.F0.B26	0.F0.B27
CLK_INT:MUX.1.OMUX_N11	0.F1.B24	0.F1.B25	0.F1.B26	0.F1.B27	0.F1.B28
CLK_INT:MUX.1.OMUX_N12	0.F0.B18	0.F0.B14	0.F0.B15	0.F0.B16	0.F0.B17
CLK_INT:MUX.1.OMUX_N15	0.F1.B14	0.F1.B15	0.F1.B16	0.F1.B17	0.F1.B18
NONE	0	0	0	0	0
0.OUT_BUFG[4]	0	0	0	0	1
0.OUT_BUFG[5]	0	0	0	1	0
0.OUT_BUFG[6]	0	0	1	0	0
0.OUT_BUFG[7]	0	1	0	0	0
0.OUT_BUFG[0]	1	0	0	0	1
0.OUT_BUFG[1]	1	0	0	1	0
0.OUT_BUFG[2]	1	0	1	0	0
0.OUT_BUFG[3]	1	1	0	0	0

Tile CLK_S_V2P

Cells: 2

Switchbox CLK_INT

virtex2 CLK_S_V2P switchbox CLK_INT muxes OMUX_N10
Bits	Destination
CELL[0].OMUX_N10
CELL[1].OMUX_N10
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_S_V2P switchbox CLK_INT muxes OMUX_N11
Bits	Destination
CELL[0].OMUX_N11
CELL[1].OMUX_N11
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_S_V2P switchbox CLK_INT muxes OMUX_N12
Bits	Destination
CELL[0].OMUX_N12
CELL[1].OMUX_N12
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_S_V2P switchbox CLK_INT muxes OMUX_N15
Bits	Destination
CELL[0].OMUX_N15
CELL[1].OMUX_N15
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_S_V2P switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[0]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_S_V2P switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[1]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_S_V2P switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[2]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_S_V2P switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[3]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_S_V2P switchbox CLK_INT muxes IMUX_BUFG_CLK[4]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[4]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_S_V2P switchbox CLK_INT muxes IMUX_BUFG_CLK[5]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[5]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_S_V2P switchbox CLK_INT muxes IMUX_BUFG_CLK[6]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[6]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_S_V2P switchbox CLK_INT muxes IMUX_BUFG_CLK[7]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[7]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_S_V2P switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[0]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_S_V2P switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[1]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_S_V2P switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[2]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_S_V2P switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[3]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_S_V2P switchbox CLK_INT muxes IMUX_BUFG_SEL[4]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[4]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_S_V2P switchbox CLK_INT muxes IMUX_BUFG_SEL[5]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[5]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_S_V2P switchbox CLK_INT muxes IMUX_BUFG_SEL[6]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[6]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_S_V2P switchbox CLK_INT muxes IMUX_BUFG_SEL[7]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[7]
	Source
CELL[1].DBL_W0[9]

Bel BUFGMUX[0]

virtex2 CLK_S_V2P bel BUFGMUX[0]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[0]
O	output	CELL[0].OUT_BUFG[0]
S	input	CELL[0].IMUX_BUFG_SEL[0]

Bel BUFGMUX[1]

virtex2 CLK_S_V2P bel BUFGMUX[1]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[1]
O	output	CELL[0].OUT_BUFG[1]
S	input	CELL[0].IMUX_BUFG_SEL[1]

Bel BUFGMUX[2]

virtex2 CLK_S_V2P bel BUFGMUX[2]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[2]
O	output	CELL[0].OUT_BUFG[2]
S	input	CELL[0].IMUX_BUFG_SEL[2]

Bel BUFGMUX[3]

virtex2 CLK_S_V2P bel BUFGMUX[3]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[3]
O	output	CELL[0].OUT_BUFG[3]
S	input	CELL[0].IMUX_BUFG_SEL[3]

Bel BUFGMUX[4]

virtex2 CLK_S_V2P bel BUFGMUX[4]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[4]
O	output	CELL[0].OUT_BUFG[4]
S	input	CELL[0].IMUX_BUFG_SEL[4]

Bel BUFGMUX[5]

virtex2 CLK_S_V2P bel BUFGMUX[5]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[5]
O	output	CELL[0].OUT_BUFG[5]
S	input	CELL[0].IMUX_BUFG_SEL[5]

Bel BUFGMUX[6]

virtex2 CLK_S_V2P bel BUFGMUX[6]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[6]
O	output	CELL[0].OUT_BUFG[6]
S	input	CELL[0].IMUX_BUFG_SEL[6]

Bel BUFGMUX[7]

virtex2 CLK_S_V2P bel BUFGMUX[7]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[7]
O	output	CELL[0].OUT_BUFG[7]
S	input	CELL[0].IMUX_BUFG_SEL[7]

Bel GLOBALSIG_S[0]

virtex2 CLK_S_V2P bel GLOBALSIG_S[0]
Pin	Direction	Wires

Bel GLOBALSIG_S[1]

virtex2 CLK_S_V2P bel GLOBALSIG_S[1]
Pin	Direction	Wires

Bel BREFCLK

virtex2 CLK_S_V2P bel BREFCLK
Pin	Direction	Wires

Bel wires

virtex2 CLK_S_V2P bel wires
Wire	Pins
CELL[0].IMUX_BUFG_CLK[0]	BUFGMUX[0].CLK
CELL[0].IMUX_BUFG_CLK[1]	BUFGMUX[1].CLK
CELL[0].IMUX_BUFG_CLK[2]	BUFGMUX[2].CLK
CELL[0].IMUX_BUFG_CLK[3]	BUFGMUX[3].CLK
CELL[0].IMUX_BUFG_CLK[4]	BUFGMUX[4].CLK
CELL[0].IMUX_BUFG_CLK[5]	BUFGMUX[5].CLK
CELL[0].IMUX_BUFG_CLK[6]	BUFGMUX[6].CLK
CELL[0].IMUX_BUFG_CLK[7]	BUFGMUX[7].CLK
CELL[0].IMUX_BUFG_SEL[0]	BUFGMUX[0].S
CELL[0].IMUX_BUFG_SEL[1]	BUFGMUX[1].S
CELL[0].IMUX_BUFG_SEL[2]	BUFGMUX[2].S
CELL[0].IMUX_BUFG_SEL[3]	BUFGMUX[3].S
CELL[0].IMUX_BUFG_SEL[4]	BUFGMUX[4].S
CELL[0].IMUX_BUFG_SEL[5]	BUFGMUX[5].S
CELL[0].IMUX_BUFG_SEL[6]	BUFGMUX[6].S
CELL[0].IMUX_BUFG_SEL[7]	BUFGMUX[7].S
CELL[0].OUT_BUFG[0]	BUFGMUX[0].O
CELL[0].OUT_BUFG[1]	BUFGMUX[1].O
CELL[0].OUT_BUFG[2]	BUFGMUX[2].O
CELL[0].OUT_BUFG[3]	BUFGMUX[3].O
CELL[0].OUT_BUFG[4]	BUFGMUX[4].O
CELL[0].OUT_BUFG[5]	BUFGMUX[5].O
CELL[0].OUT_BUFG[6]	BUFGMUX[6].O
CELL[0].OUT_BUFG[7]	BUFGMUX[7].O

Bitstream

virtex2 CLK_S_V2P rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3
B79	-	-	-	-
B78	-	-	-	-
B77	-	-	-	-
B76	-	-	-	-
B75	-	-	-	-
B74	-	-	-	-
B73	-	-	-	-
B72	-	-	-	-
B71	-	-	-	-
B70	-	-	-	-
B69	-	-	-	-
B68	-	-	-	-
B67	-	-	-	-
B66	-	-	-	-
B65	-	-	-	-
B64	-	-	-	-
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex2 CLK_S_V2P rect TERM
Bit	Frame
Bit	F0	F1	F2	F3
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

### Bitstream

virtex2 CLK_S_V2P rect R0
Bit	Frame
Bit	F0	F1	F2	F3
B76	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][5]
B75	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][0]
B74	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][1]
B73	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][2]
B72	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][3]
B71	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][4]
B70	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[3]	~CLK_INT:INV.0.IMUX_BUFG_SEL[7]	-
B69	-	-	-	-
B68	-	-	-	-
B67	-	-	-	-
B66	-	-	-	-
B65	-	-	-	-
B64	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][5]
B63	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][0]
B62	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][1]
B61	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][2]
B60	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][3]
B59	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][4]
B58	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[2]	~CLK_INT:INV.0.IMUX_BUFG_SEL[6]	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][5]
B51	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][0]
B50	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][1]
B49	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][2]
B48	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][3]
B47	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][4]
B46	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[1]	~CLK_INT:INV.0.IMUX_BUFG_SEL[5]	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][5]
B39	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][0]
B38	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][1]
B37	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][2]
B36	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][3]
B35	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][4]
B34	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[0]	~CLK_INT:INV.0.IMUX_BUFG_SEL[4]	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	CLK_INT:MUX.1.OMUX_N10[4]	CLK_INT:MUX.1.OMUX_N11[0]	CLK_INT:MUX.0.OMUX_N11[0]	CLK_INT:MUX.0.OMUX_N10[4]
B27	CLK_INT:MUX.1.OMUX_N10[0]	CLK_INT:MUX.1.OMUX_N11[1]	CLK_INT:MUX.0.OMUX_N11[1]	CLK_INT:MUX.0.OMUX_N10[0]
B26	CLK_INT:MUX.1.OMUX_N10[1]	CLK_INT:MUX.1.OMUX_N11[2]	CLK_INT:MUX.0.OMUX_N11[2]	CLK_INT:MUX.0.OMUX_N10[1]
B25	CLK_INT:MUX.1.OMUX_N10[2]	CLK_INT:MUX.1.OMUX_N11[3]	CLK_INT:MUX.0.OMUX_N11[3]	CLK_INT:MUX.0.OMUX_N10[2]
B24	CLK_INT:MUX.1.OMUX_N10[3]	CLK_INT:MUX.1.OMUX_N11[4]	CLK_INT:MUX.0.OMUX_N11[4]	CLK_INT:MUX.0.OMUX_N10[3]
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	CLK_INT:MUX.1.OMUX_N12[4]	CLK_INT:MUX.1.OMUX_N15[0]	CLK_INT:MUX.0.OMUX_N15[0]	CLK_INT:MUX.0.OMUX_N12[4]
B17	CLK_INT:MUX.1.OMUX_N12[0]	CLK_INT:MUX.1.OMUX_N15[1]	CLK_INT:MUX.0.OMUX_N15[1]	CLK_INT:MUX.0.OMUX_N12[0]
B16	CLK_INT:MUX.1.OMUX_N12[1]	CLK_INT:MUX.1.OMUX_N15[2]	CLK_INT:MUX.0.OMUX_N15[2]	CLK_INT:MUX.0.OMUX_N12[1]
B15	CLK_INT:MUX.1.OMUX_N12[2]	CLK_INT:MUX.1.OMUX_N15[3]	CLK_INT:MUX.0.OMUX_N15[3]	CLK_INT:MUX.0.OMUX_N12[2]
B14	CLK_INT:MUX.1.OMUX_N12[3]	CLK_INT:MUX.1.OMUX_N15[4]	CLK_INT:MUX.0.OMUX_N15[4]	CLK_INT:MUX.0.OMUX_N12[3]
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	BUFGMUX[0]:MUX.CLK[0]	-	-	BUFGMUX[4]:MUX.CLK[0]
B9	BUFGMUX[0]:MUX.CLK[3]	-	-	BUFGMUX[4]:MUX.CLK[3]
B8	BUFGMUX[0]:MUX.CLK[2]	-	-	BUFGMUX[4]:MUX.CLK[2]
B7	BUFGMUX[0]:MUX.CLK[1]	-	-	BUFGMUX[4]:MUX.CLK[1]
B6	BUFGMUX[0]:DISABLE_ATTR[0]	-	-	BUFGMUX[4]:DISABLE_ATTR[0]
B5	BUFGMUX[1]:DISABLE_ATTR[0]	-	-	BUFGMUX[5]:DISABLE_ATTR[0]
B4	BUFGMUX[1]:MUX.CLK[1]	-	-	BUFGMUX[5]:MUX.CLK[1]
B3	BUFGMUX[1]:MUX.CLK[2]	-	-	BUFGMUX[5]:MUX.CLK[2]
B2	BUFGMUX[1]:MUX.CLK[3]	-	-	BUFGMUX[5]:MUX.CLK[3]
B1	BUFGMUX[1]:MUX.CLK[0]	-	-	BUFGMUX[5]:MUX.CLK[0]
B0	BUFGMUX[2]:MUX.CLK[0]	-	-	BUFGMUX[6]:MUX.CLK[0]

virtex2 CLK_S_V2P rect R1
Bit	Frame
Bit	F0	F1	F2	F3
B15	BUFGMUX[2]:MUX.CLK[3]	-	-	BUFGMUX[6]:MUX.CLK[3]
B14	BUFGMUX[2]:MUX.CLK[2]	-	-	BUFGMUX[6]:MUX.CLK[2]
B13	BUFGMUX[2]:MUX.CLK[1]	-	-	BUFGMUX[6]:MUX.CLK[1]
B12	BUFGMUX[2]:DISABLE_ATTR[0]	-	-	BUFGMUX[6]:DISABLE_ATTR[0]
B11	BUFGMUX[3]:DISABLE_ATTR[0]	-	-	BUFGMUX[7]:DISABLE_ATTR[0]
B10	BUFGMUX[3]:MUX.CLK[1]	-	-	BUFGMUX[7]:MUX.CLK[1]
B9	BUFGMUX[3]:MUX.CLK[2]	-	-	BUFGMUX[7]:MUX.CLK[2]
B8	BUFGMUX[3]:MUX.CLK[3]	-	-	BUFGMUX[7]:MUX.CLK[3]
B7	BUFGMUX[3]:MUX.CLK[0]	-	-	BUFGMUX[7]:MUX.CLK[0]
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

BUFGMUX[0]:DISABLE_ATTR	0.F0.B6
BUFGMUX[1]:DISABLE_ATTR	0.F0.B5
BUFGMUX[2]:DISABLE_ATTR	1.F0.B12
BUFGMUX[3]:DISABLE_ATTR	1.F0.B11
BUFGMUX[4]:DISABLE_ATTR	0.F3.B6
BUFGMUX[5]:DISABLE_ATTR	0.F3.B5
BUFGMUX[6]:DISABLE_ATTR	1.F3.B12
BUFGMUX[7]:DISABLE_ATTR	1.F3.B11
LOW	0
HIGH	1

BUFGMUX[0]:MUX.CLK	0.F0.B9	0.F0.B8	0.F0.B7	0.F0.B10
BUFGMUX[1]:MUX.CLK	0.F0.B2	0.F0.B3	0.F0.B4	0.F0.B1
BUFGMUX[2]:MUX.CLK	1.F0.B15	1.F0.B14	1.F0.B13	0.F0.B0
BUFGMUX[3]:MUX.CLK	1.F0.B8	1.F0.B9	1.F0.B10	1.F0.B7
BUFGMUX[4]:MUX.CLK	0.F3.B9	0.F3.B8	0.F3.B7	0.F3.B10
BUFGMUX[5]:MUX.CLK	0.F3.B2	0.F3.B3	0.F3.B4	0.F3.B1
BUFGMUX[6]:MUX.CLK	1.F3.B15	1.F3.B14	1.F3.B13	0.F3.B0
BUFGMUX[7]:MUX.CLK	1.F3.B8	1.F3.B9	1.F3.B10	1.F3.B7
INT	0	0	0	1
CKI	0	0	1	0
DCM_OUT_L	0	1	0	0
DCM_OUT_R	1	0	0	0

CLK_INT:INV.0.IMUX_BUFG_SEL[0]	0.F1.B34
CLK_INT:INV.0.IMUX_BUFG_SEL[1]	0.F1.B46
CLK_INT:INV.0.IMUX_BUFG_SEL[2]	0.F1.B58
CLK_INT:INV.0.IMUX_BUFG_SEL[3]	0.F1.B70
CLK_INT:INV.0.IMUX_BUFG_SEL[4]	0.F2.B34
CLK_INT:INV.0.IMUX_BUFG_SEL[5]	0.F2.B46
CLK_INT:INV.0.IMUX_BUFG_SEL[6]	0.F2.B58
CLK_INT:INV.0.IMUX_BUFG_SEL[7]	0.F2.B70
inverted	~[0]

CLK_INT:MUX.0.IMUX_BUFG_CLK[0]	0.F0.B40	0.F0.B35	0.F0.B36	0.F0.B37	0.F0.B38	0.F0.B39
CLK_INT:MUX.0.IMUX_BUFG_CLK[4]	0.F3.B40	0.F3.B35	0.F3.B36	0.F3.B37	0.F3.B38	0.F3.B39
CLK_INT:MUX.0.IMUX_BUFG_SEL[0]	0.F1.B35	0.F1.B36	0.F1.B37	0.F1.B38	0.F1.B39	0.F1.B40
CLK_INT:MUX.0.IMUX_BUFG_SEL[4]	0.F2.B35	0.F2.B36	0.F2.B37	0.F2.B38	0.F2.B39	0.F2.B40
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[0]	0	0	0	0	0	1
0.DBL_W2[1]	0	0	0	0	1	0
0.DBL_W2[2]	0	0	0	1	0	0
1.DBL_W0[0]	0	0	1	0	0	0
1.DBL_W0[1]	0	1	0	0	0	0
0.DBL_E0[0]	1	0	0	0	0	1
0.DBL_E0[1]	1	0	0	0	1	0
0.DBL_E0[2]	1	0	0	1	0	0
0.DBL_E1[0]	1	0	1	0	0	0
0.DBL_E1[1]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[1]	0.F0.B52	0.F0.B47	0.F0.B48	0.F0.B49	0.F0.B50	0.F0.B51
CLK_INT:MUX.0.IMUX_BUFG_CLK[5]	0.F3.B52	0.F3.B47	0.F3.B48	0.F3.B49	0.F3.B50	0.F3.B51
CLK_INT:MUX.0.IMUX_BUFG_SEL[1]	0.F1.B47	0.F1.B48	0.F1.B49	0.F1.B50	0.F1.B51	0.F1.B52
CLK_INT:MUX.0.IMUX_BUFG_SEL[5]	0.F2.B47	0.F2.B48	0.F2.B49	0.F2.B50	0.F2.B51	0.F2.B52
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[3]	0	0	0	0	0	1
0.DBL_W2[4]	0	0	0	0	1	0
1.DBL_W0[2]	0	0	0	1	0	0
1.DBL_W0[3]	0	0	1	0	0	0
1.DBL_W0[4]	0	1	0	0	0	0
0.DBL_E0[3]	1	0	0	0	0	1
0.DBL_E0[4]	1	0	0	0	1	0
0.DBL_E1[2]	1	0	0	1	0	0
0.DBL_E1[3]	1	0	1	0	0	0
0.DBL_E1[4]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[2]	0.F0.B64	0.F0.B59	0.F0.B60	0.F0.B61	0.F0.B62	0.F0.B63
CLK_INT:MUX.0.IMUX_BUFG_CLK[6]	0.F3.B64	0.F3.B59	0.F3.B60	0.F3.B61	0.F3.B62	0.F3.B63
CLK_INT:MUX.0.IMUX_BUFG_SEL[2]	0.F1.B59	0.F1.B60	0.F1.B61	0.F1.B62	0.F1.B63	0.F1.B64
CLK_INT:MUX.0.IMUX_BUFG_SEL[6]	0.F2.B59	0.F2.B60	0.F2.B61	0.F2.B62	0.F2.B63	0.F2.B64
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[5]	0	0	0	0	0	1
0.DBL_W2[6]	0	0	0	0	1	0
0.DBL_W2[7]	0	0	0	1	0	0
1.DBL_W0[5]	0	0	1	0	0	0
1.DBL_W0[6]	0	1	0	0	0	0
0.DBL_E0[5]	1	0	0	0	0	1
0.DBL_E0[6]	1	0	0	0	1	0
0.DBL_E0[7]	1	0	0	1	0	0
0.DBL_E1[5]	1	0	1	0	0	0
0.DBL_E1[6]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[3]	0.F0.B76	0.F0.B71	0.F0.B72	0.F0.B73	0.F0.B74	0.F0.B75
CLK_INT:MUX.0.IMUX_BUFG_CLK[7]	0.F3.B76	0.F3.B71	0.F3.B72	0.F3.B73	0.F3.B74	0.F3.B75
CLK_INT:MUX.0.IMUX_BUFG_SEL[3]	0.F1.B71	0.F1.B72	0.F1.B73	0.F1.B74	0.F1.B75	0.F1.B76
CLK_INT:MUX.0.IMUX_BUFG_SEL[7]	0.F2.B71	0.F2.B72	0.F2.B73	0.F2.B74	0.F2.B75	0.F2.B76
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[8]	0	0	0	0	0	1
0.DBL_W2[9]	0	0	0	0	1	0
1.DBL_W0[7]	0	0	0	1	0	0
1.DBL_W0[8]	0	0	1	0	0	0
1.DBL_W0[9]	0	1	0	0	0	0
0.DBL_E0[8]	1	0	0	0	0	1
0.DBL_E0[9]	1	0	0	0	1	0
0.DBL_E1[7]	1	0	0	1	0	0
0.DBL_E1[8]	1	0	1	0	0	0
0.DBL_E1[9]	1	1	0	0	0	0

CLK_INT:MUX.0.OMUX_N10	0.F3.B28	0.F3.B24	0.F3.B25	0.F3.B26	0.F3.B27
CLK_INT:MUX.0.OMUX_N11	0.F2.B24	0.F2.B25	0.F2.B26	0.F2.B27	0.F2.B28
CLK_INT:MUX.0.OMUX_N12	0.F3.B18	0.F3.B14	0.F3.B15	0.F3.B16	0.F3.B17
CLK_INT:MUX.0.OMUX_N15	0.F2.B14	0.F2.B15	0.F2.B16	0.F2.B17	0.F2.B18
NONE	0	0	0	0	0
0.OUT_BUFG[0]	0	0	0	0	1
0.OUT_BUFG[1]	0	0	0	1	0
0.OUT_BUFG[2]	0	0	1	0	0
0.OUT_BUFG[3]	0	1	0	0	0
0.OUT_BUFG[4]	1	0	0	0	1
0.OUT_BUFG[5]	1	0	0	1	0
0.OUT_BUFG[6]	1	0	1	0	0
0.OUT_BUFG[7]	1	1	0	0	0

CLK_INT:MUX.1.OMUX_N10	0.F0.B28	0.F0.B24	0.F0.B25	0.F0.B26	0.F0.B27
CLK_INT:MUX.1.OMUX_N11	0.F1.B24	0.F1.B25	0.F1.B26	0.F1.B27	0.F1.B28
CLK_INT:MUX.1.OMUX_N12	0.F0.B18	0.F0.B14	0.F0.B15	0.F0.B16	0.F0.B17
CLK_INT:MUX.1.OMUX_N15	0.F1.B14	0.F1.B15	0.F1.B16	0.F1.B17	0.F1.B18
NONE	0	0	0	0	0
0.OUT_BUFG[4]	0	0	0	0	1
0.OUT_BUFG[5]	0	0	0	1	0
0.OUT_BUFG[6]	0	0	1	0	0
0.OUT_BUFG[7]	0	1	0	0	0
0.OUT_BUFG[0]	1	0	0	0	1
0.OUT_BUFG[1]	1	0	0	1	0
0.OUT_BUFG[2]	1	0	1	0	0
0.OUT_BUFG[3]	1	1	0	0	0

Tile CLK_S_V2PX

Cells: 2

Switchbox CLK_INT

virtex2 CLK_S_V2PX switchbox CLK_INT muxes OMUX_N10
Bits	Destination
CELL[0].OMUX_N10
CELL[1].OMUX_N10
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes OMUX_N11
Bits	Destination
CELL[0].OMUX_N11
CELL[1].OMUX_N11
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes OMUX_N12
Bits	Destination
CELL[0].OMUX_N12
CELL[1].OMUX_N12
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes OMUX_N15
Bits	Destination
CELL[0].OMUX_N15
CELL[1].OMUX_N15
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[0]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[1]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[2]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[3]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes IMUX_BUFG_CLK[4]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[4]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes IMUX_BUFG_CLK[5]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[5]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes IMUX_BUFG_CLK[6]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[6]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes IMUX_BUFG_CLK[7]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[7]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[0]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[1]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[2]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[3]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes IMUX_BUFG_SEL[4]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[4]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes IMUX_BUFG_SEL[5]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[5]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes IMUX_BUFG_SEL[6]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[6]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_S_V2PX switchbox CLK_INT muxes IMUX_BUFG_SEL[7]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[7]
	Source
CELL[1].DBL_W0[9]

Bel BUFGMUX[0]

virtex2 CLK_S_V2PX bel BUFGMUX[0]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[0]
O	output	CELL[0].OUT_BUFG[0]
S	input	CELL[0].IMUX_BUFG_SEL[0]

Bel BUFGMUX[1]

virtex2 CLK_S_V2PX bel BUFGMUX[1]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[1]
O	output	CELL[0].OUT_BUFG[1]
S	input	CELL[0].IMUX_BUFG_SEL[1]

Bel BUFGMUX[2]

virtex2 CLK_S_V2PX bel BUFGMUX[2]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[2]
O	output	CELL[0].OUT_BUFG[2]
S	input	CELL[0].IMUX_BUFG_SEL[2]

Bel BUFGMUX[3]

virtex2 CLK_S_V2PX bel BUFGMUX[3]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[3]
O	output	CELL[0].OUT_BUFG[3]
S	input	CELL[0].IMUX_BUFG_SEL[3]

Bel BUFGMUX[4]

virtex2 CLK_S_V2PX bel BUFGMUX[4]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[4]
O	output	CELL[0].OUT_BUFG[4]
S	input	CELL[0].IMUX_BUFG_SEL[4]

Bel BUFGMUX[5]

virtex2 CLK_S_V2PX bel BUFGMUX[5]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[5]
O	output	CELL[0].OUT_BUFG[5]
S	input	CELL[0].IMUX_BUFG_SEL[5]

Bel BUFGMUX[6]

virtex2 CLK_S_V2PX bel BUFGMUX[6]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[6]
O	output	CELL[0].OUT_BUFG[6]
S	input	CELL[0].IMUX_BUFG_SEL[6]

Bel BUFGMUX[7]

virtex2 CLK_S_V2PX bel BUFGMUX[7]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[7]
O	output	CELL[0].OUT_BUFG[7]
S	input	CELL[0].IMUX_BUFG_SEL[7]

Bel GLOBALSIG_S[0]

virtex2 CLK_S_V2PX bel GLOBALSIG_S[0]
Pin	Direction	Wires

Bel GLOBALSIG_S[1]

virtex2 CLK_S_V2PX bel GLOBALSIG_S[1]
Pin	Direction	Wires

Bel wires

virtex2 CLK_S_V2PX bel wires
Wire	Pins
CELL[0].IMUX_BUFG_CLK[0]	BUFGMUX[0].CLK
CELL[0].IMUX_BUFG_CLK[1]	BUFGMUX[1].CLK
CELL[0].IMUX_BUFG_CLK[2]	BUFGMUX[2].CLK
CELL[0].IMUX_BUFG_CLK[3]	BUFGMUX[3].CLK
CELL[0].IMUX_BUFG_CLK[4]	BUFGMUX[4].CLK
CELL[0].IMUX_BUFG_CLK[5]	BUFGMUX[5].CLK
CELL[0].IMUX_BUFG_CLK[6]	BUFGMUX[6].CLK
CELL[0].IMUX_BUFG_CLK[7]	BUFGMUX[7].CLK
CELL[0].IMUX_BUFG_SEL[0]	BUFGMUX[0].S
CELL[0].IMUX_BUFG_SEL[1]	BUFGMUX[1].S
CELL[0].IMUX_BUFG_SEL[2]	BUFGMUX[2].S
CELL[0].IMUX_BUFG_SEL[3]	BUFGMUX[3].S
CELL[0].IMUX_BUFG_SEL[4]	BUFGMUX[4].S
CELL[0].IMUX_BUFG_SEL[5]	BUFGMUX[5].S
CELL[0].IMUX_BUFG_SEL[6]	BUFGMUX[6].S
CELL[0].IMUX_BUFG_SEL[7]	BUFGMUX[7].S
CELL[0].OUT_BUFG[0]	BUFGMUX[0].O
CELL[0].OUT_BUFG[1]	BUFGMUX[1].O
CELL[0].OUT_BUFG[2]	BUFGMUX[2].O
CELL[0].OUT_BUFG[3]	BUFGMUX[3].O
CELL[0].OUT_BUFG[4]	BUFGMUX[4].O
CELL[0].OUT_BUFG[5]	BUFGMUX[5].O
CELL[0].OUT_BUFG[6]	BUFGMUX[6].O
CELL[0].OUT_BUFG[7]	BUFGMUX[7].O

Bitstream

virtex2 CLK_S_V2PX rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3
B79	-	-	-	-
B78	-	-	-	-
B77	-	-	-	-
B76	-	-	-	-
B75	-	-	-	-
B74	-	-	-	-
B73	-	-	-	-
B72	-	-	-	-
B71	-	-	-	-
B70	-	-	-	-
B69	-	-	-	-
B68	-	-	-	-
B67	-	-	-	-
B66	-	-	-	-
B65	-	-	-	-
B64	-	-	-	-
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex2 CLK_S_V2PX rect TERM
Bit	Frame
Bit	F0	F1	F2	F3
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

### Bitstream

virtex2 CLK_S_V2PX rect R0
Bit	Frame
Bit	F0	F1	F2	F3
B76	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][5]
B75	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][0]
B74	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][1]
B73	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][2]
B72	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][3]
B71	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][4]
B70	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[3]	~CLK_INT:INV.0.IMUX_BUFG_SEL[7]	-
B69	-	-	-	-
B68	-	-	-	-
B67	-	-	-	-
B66	-	-	-	-
B65	-	-	-	-
B64	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][5]
B63	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][0]
B62	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][1]
B61	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][2]
B60	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][3]
B59	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][4]
B58	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[2]	~CLK_INT:INV.0.IMUX_BUFG_SEL[6]	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][5]
B51	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][0]
B50	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][1]
B49	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][2]
B48	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][3]
B47	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][4]
B46	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[1]	~CLK_INT:INV.0.IMUX_BUFG_SEL[5]	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][5]
B39	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][0]
B38	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][1]
B37	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][2]
B36	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][3]
B35	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][4]
B34	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[0]	~CLK_INT:INV.0.IMUX_BUFG_SEL[4]	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	CLK_INT:MUX.1.OMUX_N10[4]	CLK_INT:MUX.1.OMUX_N11[0]	CLK_INT:MUX.0.OMUX_N11[0]	CLK_INT:MUX.0.OMUX_N10[4]
B27	CLK_INT:MUX.1.OMUX_N10[0]	CLK_INT:MUX.1.OMUX_N11[1]	CLK_INT:MUX.0.OMUX_N11[1]	CLK_INT:MUX.0.OMUX_N10[0]
B26	CLK_INT:MUX.1.OMUX_N10[1]	CLK_INT:MUX.1.OMUX_N11[2]	CLK_INT:MUX.0.OMUX_N11[2]	CLK_INT:MUX.0.OMUX_N10[1]
B25	CLK_INT:MUX.1.OMUX_N10[2]	CLK_INT:MUX.1.OMUX_N11[3]	CLK_INT:MUX.0.OMUX_N11[3]	CLK_INT:MUX.0.OMUX_N10[2]
B24	CLK_INT:MUX.1.OMUX_N10[3]	CLK_INT:MUX.1.OMUX_N11[4]	CLK_INT:MUX.0.OMUX_N11[4]	CLK_INT:MUX.0.OMUX_N10[3]
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	CLK_INT:MUX.1.OMUX_N12[4]	CLK_INT:MUX.1.OMUX_N15[0]	CLK_INT:MUX.0.OMUX_N15[0]	CLK_INT:MUX.0.OMUX_N12[4]
B17	CLK_INT:MUX.1.OMUX_N12[0]	CLK_INT:MUX.1.OMUX_N15[1]	CLK_INT:MUX.0.OMUX_N15[1]	CLK_INT:MUX.0.OMUX_N12[0]
B16	CLK_INT:MUX.1.OMUX_N12[1]	CLK_INT:MUX.1.OMUX_N15[2]	CLK_INT:MUX.0.OMUX_N15[2]	CLK_INT:MUX.0.OMUX_N12[1]
B15	CLK_INT:MUX.1.OMUX_N12[2]	CLK_INT:MUX.1.OMUX_N15[3]	CLK_INT:MUX.0.OMUX_N15[3]	CLK_INT:MUX.0.OMUX_N12[2]
B14	CLK_INT:MUX.1.OMUX_N12[3]	CLK_INT:MUX.1.OMUX_N15[4]	CLK_INT:MUX.0.OMUX_N15[4]	CLK_INT:MUX.0.OMUX_N12[3]
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	BUFGMUX[0]:MUX.CLK[0]	-	-	BUFGMUX[4]:MUX.CLK[0]
B9	BUFGMUX[0]:MUX.CLK[3]	-	-	BUFGMUX[4]:MUX.CLK[3]
B8	BUFGMUX[0]:MUX.CLK[2]	-	-	BUFGMUX[4]:MUX.CLK[2]
B7	BUFGMUX[0]:MUX.CLK[1]	-	-	BUFGMUX[4]:MUX.CLK[1]
B6	BUFGMUX[0]:DISABLE_ATTR[0]	-	-	BUFGMUX[4]:DISABLE_ATTR[0]
B5	BUFGMUX[1]:DISABLE_ATTR[0]	-	-	BUFGMUX[5]:DISABLE_ATTR[0]
B4	BUFGMUX[1]:MUX.CLK[1]	-	-	BUFGMUX[5]:MUX.CLK[1]
B3	BUFGMUX[1]:MUX.CLK[2]	-	-	BUFGMUX[5]:MUX.CLK[2]
B2	BUFGMUX[1]:MUX.CLK[3]	-	-	BUFGMUX[5]:MUX.CLK[3]
B1	BUFGMUX[1]:MUX.CLK[0]	-	-	BUFGMUX[5]:MUX.CLK[0]
B0	BUFGMUX[2]:MUX.CLK[0]	-	-	BUFGMUX[6]:MUX.CLK[0]

virtex2 CLK_S_V2PX rect R1
Bit	Frame
Bit	F0	F1	F2	F3
B15	BUFGMUX[2]:MUX.CLK[3]	-	-	BUFGMUX[6]:MUX.CLK[3]
B14	BUFGMUX[2]:MUX.CLK[2]	-	-	BUFGMUX[6]:MUX.CLK[2]
B13	BUFGMUX[2]:MUX.CLK[1]	-	-	BUFGMUX[6]:MUX.CLK[1]
B12	BUFGMUX[2]:DISABLE_ATTR[0]	-	-	BUFGMUX[6]:DISABLE_ATTR[0]
B11	BUFGMUX[3]:DISABLE_ATTR[0]	-	-	BUFGMUX[7]:DISABLE_ATTR[0]
B10	BUFGMUX[3]:MUX.CLK[1]	-	-	BUFGMUX[7]:MUX.CLK[1]
B9	BUFGMUX[3]:MUX.CLK[2]	-	-	BUFGMUX[7]:MUX.CLK[2]
B8	BUFGMUX[3]:MUX.CLK[3]	-	-	BUFGMUX[7]:MUX.CLK[3]
B7	BUFGMUX[3]:MUX.CLK[0]	-	-	BUFGMUX[7]:MUX.CLK[0]
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

BUFGMUX[0]:DISABLE_ATTR	0.F0.B6
BUFGMUX[1]:DISABLE_ATTR	0.F0.B5
BUFGMUX[2]:DISABLE_ATTR	1.F0.B12
BUFGMUX[3]:DISABLE_ATTR	1.F0.B11
BUFGMUX[4]:DISABLE_ATTR	0.F3.B6
BUFGMUX[5]:DISABLE_ATTR	0.F3.B5
BUFGMUX[6]:DISABLE_ATTR	1.F3.B12
BUFGMUX[7]:DISABLE_ATTR	1.F3.B11
LOW	0
HIGH	1

BUFGMUX[0]:MUX.CLK	0.F0.B9	0.F0.B8	0.F0.B7	0.F0.B10
BUFGMUX[1]:MUX.CLK	0.F0.B2	0.F0.B3	0.F0.B4	0.F0.B1
BUFGMUX[2]:MUX.CLK	1.F0.B15	1.F0.B14	1.F0.B13	0.F0.B0
BUFGMUX[3]:MUX.CLK	1.F0.B8	1.F0.B9	1.F0.B10	1.F0.B7
BUFGMUX[4]:MUX.CLK	0.F3.B9	0.F3.B8	0.F3.B7	0.F3.B10
BUFGMUX[5]:MUX.CLK	0.F3.B2	0.F3.B3	0.F3.B4	0.F3.B1
BUFGMUX[6]:MUX.CLK	1.F3.B15	1.F3.B14	1.F3.B13	0.F3.B0
BUFGMUX[7]:MUX.CLK	1.F3.B8	1.F3.B9	1.F3.B10	1.F3.B7
INT	0	0	0	1
CKI	0	0	1	0
DCM_OUT_L	0	1	0	0
DCM_OUT_R	1	0	0	0

CLK_INT:INV.0.IMUX_BUFG_SEL[0]	0.F1.B34
CLK_INT:INV.0.IMUX_BUFG_SEL[1]	0.F1.B46
CLK_INT:INV.0.IMUX_BUFG_SEL[2]	0.F1.B58
CLK_INT:INV.0.IMUX_BUFG_SEL[3]	0.F1.B70
CLK_INT:INV.0.IMUX_BUFG_SEL[4]	0.F2.B34
CLK_INT:INV.0.IMUX_BUFG_SEL[5]	0.F2.B46
CLK_INT:INV.0.IMUX_BUFG_SEL[6]	0.F2.B58
CLK_INT:INV.0.IMUX_BUFG_SEL[7]	0.F2.B70
inverted	~[0]

CLK_INT:MUX.0.IMUX_BUFG_CLK[0]	0.F0.B40	0.F0.B35	0.F0.B36	0.F0.B37	0.F0.B38	0.F0.B39
CLK_INT:MUX.0.IMUX_BUFG_CLK[4]	0.F3.B40	0.F3.B35	0.F3.B36	0.F3.B37	0.F3.B38	0.F3.B39
CLK_INT:MUX.0.IMUX_BUFG_SEL[0]	0.F1.B35	0.F1.B36	0.F1.B37	0.F1.B38	0.F1.B39	0.F1.B40
CLK_INT:MUX.0.IMUX_BUFG_SEL[4]	0.F2.B35	0.F2.B36	0.F2.B37	0.F2.B38	0.F2.B39	0.F2.B40
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[0]	0	0	0	0	0	1
0.DBL_W2[1]	0	0	0	0	1	0
0.DBL_W2[2]	0	0	0	1	0	0
1.DBL_W0[0]	0	0	1	0	0	0
1.DBL_W0[1]	0	1	0	0	0	0
0.DBL_E0[0]	1	0	0	0	0	1
0.DBL_E0[1]	1	0	0	0	1	0
0.DBL_E0[2]	1	0	0	1	0	0
0.DBL_E1[0]	1	0	1	0	0	0
0.DBL_E1[1]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[1]	0.F0.B52	0.F0.B47	0.F0.B48	0.F0.B49	0.F0.B50	0.F0.B51
CLK_INT:MUX.0.IMUX_BUFG_CLK[5]	0.F3.B52	0.F3.B47	0.F3.B48	0.F3.B49	0.F3.B50	0.F3.B51
CLK_INT:MUX.0.IMUX_BUFG_SEL[1]	0.F1.B47	0.F1.B48	0.F1.B49	0.F1.B50	0.F1.B51	0.F1.B52
CLK_INT:MUX.0.IMUX_BUFG_SEL[5]	0.F2.B47	0.F2.B48	0.F2.B49	0.F2.B50	0.F2.B51	0.F2.B52
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[3]	0	0	0	0	0	1
0.DBL_W2[4]	0	0	0	0	1	0
1.DBL_W0[2]	0	0	0	1	0	0
1.DBL_W0[3]	0	0	1	0	0	0
1.DBL_W0[4]	0	1	0	0	0	0
0.DBL_E0[3]	1	0	0	0	0	1
0.DBL_E0[4]	1	0	0	0	1	0
0.DBL_E1[2]	1	0	0	1	0	0
0.DBL_E1[3]	1	0	1	0	0	0
0.DBL_E1[4]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[2]	0.F0.B64	0.F0.B59	0.F0.B60	0.F0.B61	0.F0.B62	0.F0.B63
CLK_INT:MUX.0.IMUX_BUFG_CLK[6]	0.F3.B64	0.F3.B59	0.F3.B60	0.F3.B61	0.F3.B62	0.F3.B63
CLK_INT:MUX.0.IMUX_BUFG_SEL[2]	0.F1.B59	0.F1.B60	0.F1.B61	0.F1.B62	0.F1.B63	0.F1.B64
CLK_INT:MUX.0.IMUX_BUFG_SEL[6]	0.F2.B59	0.F2.B60	0.F2.B61	0.F2.B62	0.F2.B63	0.F2.B64
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[5]	0	0	0	0	0	1
0.DBL_W2[6]	0	0	0	0	1	0
0.DBL_W2[7]	0	0	0	1	0	0
1.DBL_W0[5]	0	0	1	0	0	0
1.DBL_W0[6]	0	1	0	0	0	0
0.DBL_E0[5]	1	0	0	0	0	1
0.DBL_E0[6]	1	0	0	0	1	0
0.DBL_E0[7]	1	0	0	1	0	0
0.DBL_E1[5]	1	0	1	0	0	0
0.DBL_E1[6]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[3]	0.F0.B76	0.F0.B71	0.F0.B72	0.F0.B73	0.F0.B74	0.F0.B75
CLK_INT:MUX.0.IMUX_BUFG_CLK[7]	0.F3.B76	0.F3.B71	0.F3.B72	0.F3.B73	0.F3.B74	0.F3.B75
CLK_INT:MUX.0.IMUX_BUFG_SEL[3]	0.F1.B71	0.F1.B72	0.F1.B73	0.F1.B74	0.F1.B75	0.F1.B76
CLK_INT:MUX.0.IMUX_BUFG_SEL[7]	0.F2.B71	0.F2.B72	0.F2.B73	0.F2.B74	0.F2.B75	0.F2.B76
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[8]	0	0	0	0	0	1
0.DBL_W2[9]	0	0	0	0	1	0
1.DBL_W0[7]	0	0	0	1	0	0
1.DBL_W0[8]	0	0	1	0	0	0
1.DBL_W0[9]	0	1	0	0	0	0
0.DBL_E0[8]	1	0	0	0	0	1
0.DBL_E0[9]	1	0	0	0	1	0
0.DBL_E1[7]	1	0	0	1	0	0
0.DBL_E1[8]	1	0	1	0	0	0
0.DBL_E1[9]	1	1	0	0	0	0

CLK_INT:MUX.0.OMUX_N10	0.F3.B28	0.F3.B24	0.F3.B25	0.F3.B26	0.F3.B27
CLK_INT:MUX.0.OMUX_N11	0.F2.B24	0.F2.B25	0.F2.B26	0.F2.B27	0.F2.B28
CLK_INT:MUX.0.OMUX_N12	0.F3.B18	0.F3.B14	0.F3.B15	0.F3.B16	0.F3.B17
CLK_INT:MUX.0.OMUX_N15	0.F2.B14	0.F2.B15	0.F2.B16	0.F2.B17	0.F2.B18
NONE	0	0	0	0	0
0.OUT_BUFG[0]	0	0	0	0	1
0.OUT_BUFG[1]	0	0	0	1	0
0.OUT_BUFG[2]	0	0	1	0	0
0.OUT_BUFG[3]	0	1	0	0	0
0.OUT_BUFG[4]	1	0	0	0	1
0.OUT_BUFG[5]	1	0	0	1	0
0.OUT_BUFG[6]	1	0	1	0	0
0.OUT_BUFG[7]	1	1	0	0	0

CLK_INT:MUX.1.OMUX_N10	0.F0.B28	0.F0.B24	0.F0.B25	0.F0.B26	0.F0.B27
CLK_INT:MUX.1.OMUX_N11	0.F1.B24	0.F1.B25	0.F1.B26	0.F1.B27	0.F1.B28
CLK_INT:MUX.1.OMUX_N12	0.F0.B18	0.F0.B14	0.F0.B15	0.F0.B16	0.F0.B17
CLK_INT:MUX.1.OMUX_N15	0.F1.B14	0.F1.B15	0.F1.B16	0.F1.B17	0.F1.B18
NONE	0	0	0	0	0
0.OUT_BUFG[4]	0	0	0	0	1
0.OUT_BUFG[5]	0	0	0	1	0
0.OUT_BUFG[6]	0	0	1	0	0
0.OUT_BUFG[7]	0	1	0	0	0
0.OUT_BUFG[0]	1	0	0	0	1
0.OUT_BUFG[1]	1	0	0	1	0
0.OUT_BUFG[2]	1	0	1	0	0
0.OUT_BUFG[3]	1	1	0	0	0

Tile CLK_N_V2

Cells: 2

Switchbox CLK_INT

virtex2 CLK_N_V2 switchbox CLK_INT muxes OMUX_S0
Bits	Destination
CELL[0].OMUX_S0
CELL[1].OMUX_S0
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_N_V2 switchbox CLK_INT muxes OMUX_S3
Bits	Destination
CELL[0].OMUX_S3
CELL[1].OMUX_S3
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_N_V2 switchbox CLK_INT muxes OMUX_S4
Bits	Destination
CELL[0].OMUX_S4
CELL[1].OMUX_S4
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_N_V2 switchbox CLK_INT muxes OMUX_S5
Bits	Destination
CELL[0].OMUX_S5
CELL[1].OMUX_S5
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_N_V2 switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[0]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_N_V2 switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[1]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_N_V2 switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[2]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_N_V2 switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[3]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_N_V2 switchbox CLK_INT muxes IMUX_BUFG_CLK[4]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[4]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_N_V2 switchbox CLK_INT muxes IMUX_BUFG_CLK[5]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[5]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_N_V2 switchbox CLK_INT muxes IMUX_BUFG_CLK[6]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[6]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_N_V2 switchbox CLK_INT muxes IMUX_BUFG_CLK[7]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[7]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_N_V2 switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[0]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_N_V2 switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[1]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_N_V2 switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[2]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_N_V2 switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[3]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_N_V2 switchbox CLK_INT muxes IMUX_BUFG_SEL[4]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[4]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_N_V2 switchbox CLK_INT muxes IMUX_BUFG_SEL[5]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[5]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_N_V2 switchbox CLK_INT muxes IMUX_BUFG_SEL[6]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[6]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_N_V2 switchbox CLK_INT muxes IMUX_BUFG_SEL[7]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[7]
	Source
CELL[1].DBL_W0[9]

Bel BUFGMUX[0]

virtex2 CLK_N_V2 bel BUFGMUX[0]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[0]
O	output	CELL[0].OUT_BUFG[0]
S	input	CELL[0].IMUX_BUFG_SEL[0]

Bel BUFGMUX[1]

virtex2 CLK_N_V2 bel BUFGMUX[1]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[1]
O	output	CELL[0].OUT_BUFG[1]
S	input	CELL[0].IMUX_BUFG_SEL[1]

Bel BUFGMUX[2]

virtex2 CLK_N_V2 bel BUFGMUX[2]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[2]
O	output	CELL[0].OUT_BUFG[2]
S	input	CELL[0].IMUX_BUFG_SEL[2]

Bel BUFGMUX[3]

virtex2 CLK_N_V2 bel BUFGMUX[3]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[3]
O	output	CELL[0].OUT_BUFG[3]
S	input	CELL[0].IMUX_BUFG_SEL[3]

Bel BUFGMUX[4]

virtex2 CLK_N_V2 bel BUFGMUX[4]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[4]
O	output	CELL[0].OUT_BUFG[4]
S	input	CELL[0].IMUX_BUFG_SEL[4]

Bel BUFGMUX[5]

virtex2 CLK_N_V2 bel BUFGMUX[5]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[5]
O	output	CELL[0].OUT_BUFG[5]
S	input	CELL[0].IMUX_BUFG_SEL[5]

Bel BUFGMUX[6]

virtex2 CLK_N_V2 bel BUFGMUX[6]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[6]
O	output	CELL[0].OUT_BUFG[6]
S	input	CELL[0].IMUX_BUFG_SEL[6]

Bel BUFGMUX[7]

virtex2 CLK_N_V2 bel BUFGMUX[7]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[7]
O	output	CELL[0].OUT_BUFG[7]
S	input	CELL[0].IMUX_BUFG_SEL[7]

Bel GLOBALSIG_N[0]

virtex2 CLK_N_V2 bel GLOBALSIG_N[0]
Pin	Direction	Wires

Bel GLOBALSIG_N[1]

virtex2 CLK_N_V2 bel GLOBALSIG_N[1]
Pin	Direction	Wires

Bel wires

virtex2 CLK_N_V2 bel wires
Wire	Pins
CELL[0].IMUX_BUFG_CLK[0]	BUFGMUX[0].CLK
CELL[0].IMUX_BUFG_CLK[1]	BUFGMUX[1].CLK
CELL[0].IMUX_BUFG_CLK[2]	BUFGMUX[2].CLK
CELL[0].IMUX_BUFG_CLK[3]	BUFGMUX[3].CLK
CELL[0].IMUX_BUFG_CLK[4]	BUFGMUX[4].CLK
CELL[0].IMUX_BUFG_CLK[5]	BUFGMUX[5].CLK
CELL[0].IMUX_BUFG_CLK[6]	BUFGMUX[6].CLK
CELL[0].IMUX_BUFG_CLK[7]	BUFGMUX[7].CLK
CELL[0].IMUX_BUFG_SEL[0]	BUFGMUX[0].S
CELL[0].IMUX_BUFG_SEL[1]	BUFGMUX[1].S
CELL[0].IMUX_BUFG_SEL[2]	BUFGMUX[2].S
CELL[0].IMUX_BUFG_SEL[3]	BUFGMUX[3].S
CELL[0].IMUX_BUFG_SEL[4]	BUFGMUX[4].S
CELL[0].IMUX_BUFG_SEL[5]	BUFGMUX[5].S
CELL[0].IMUX_BUFG_SEL[6]	BUFGMUX[6].S
CELL[0].IMUX_BUFG_SEL[7]	BUFGMUX[7].S
CELL[0].OUT_BUFG[0]	BUFGMUX[0].O
CELL[0].OUT_BUFG[1]	BUFGMUX[1].O
CELL[0].OUT_BUFG[2]	BUFGMUX[2].O
CELL[0].OUT_BUFG[3]	BUFGMUX[3].O
CELL[0].OUT_BUFG[4]	BUFGMUX[4].O
CELL[0].OUT_BUFG[5]	BUFGMUX[5].O
CELL[0].OUT_BUFG[6]	BUFGMUX[6].O
CELL[0].OUT_BUFG[7]	BUFGMUX[7].O

Bitstream

virtex2 CLK_N_V2 rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3
B79	-	-	-	-
B78	-	-	-	-
B77	-	-	-	-
B76	-	-	-	-
B75	-	-	-	-
B74	-	-	-	-
B73	-	-	-	-
B72	-	-	-	-
B71	-	-	-	-
B70	-	-	-	-
B69	-	-	-	-
B68	-	-	-	-
B67	-	-	-	-
B66	-	-	-	-
B65	-	-	-	-
B64	-	-	-	-
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex2 CLK_N_V2 rect TERM
Bit	Frame
Bit	F0	F1	F2	F3
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

### Bitstream

virtex2 CLK_N_V2 rect R0
Bit	Frame
Bit	F0	F1	F2	F3
B79	BUFGMUX[2]:MUX.CLK[3]	-	-	BUFGMUX[6]:MUX.CLK[3]
B78	BUFGMUX[2]:MUX.CLK[0]	-	-	BUFGMUX[6]:MUX.CLK[0]
B77	BUFGMUX[1]:MUX.CLK[0]	-	-	BUFGMUX[5]:MUX.CLK[0]
B76	BUFGMUX[1]:MUX.CLK[3]	-	-	BUFGMUX[5]:MUX.CLK[3]
B75	BUFGMUX[1]:MUX.CLK[2]	-	-	BUFGMUX[5]:MUX.CLK[2]
B74	BUFGMUX[1]:MUX.CLK[1]	-	-	BUFGMUX[5]:MUX.CLK[1]
B73	BUFGMUX[1]:DISABLE_ATTR[0]	-	-	BUFGMUX[5]:DISABLE_ATTR[0]
B72	BUFGMUX[0]:DISABLE_ATTR[0]	-	-	BUFGMUX[4]:DISABLE_ATTR[0]
B71	BUFGMUX[0]:MUX.CLK[1]	-	-	BUFGMUX[4]:MUX.CLK[1]
B70	BUFGMUX[0]:MUX.CLK[2]	-	-	BUFGMUX[4]:MUX.CLK[2]
B69	BUFGMUX[0]:MUX.CLK[3]	-	-	BUFGMUX[4]:MUX.CLK[3]
B68	BUFGMUX[0]:MUX.CLK[0]	-	-	BUFGMUX[4]:MUX.CLK[0]
B67	-	-	-	-
B66	-	-	-	-
B65	-	-	-	-
B64	CLK_INT:MUX.1.OMUX_S4[3]	CLK_INT:MUX.1.OMUX_S5[4]	CLK_INT:MUX.0.OMUX_S5[4]	CLK_INT:MUX.0.OMUX_S4[3]
B63	CLK_INT:MUX.1.OMUX_S4[2]	CLK_INT:MUX.1.OMUX_S5[3]	CLK_INT:MUX.0.OMUX_S5[3]	CLK_INT:MUX.0.OMUX_S4[2]
B62	CLK_INT:MUX.1.OMUX_S4[1]	CLK_INT:MUX.1.OMUX_S5[2]	CLK_INT:MUX.0.OMUX_S5[2]	CLK_INT:MUX.0.OMUX_S4[1]
B61	CLK_INT:MUX.1.OMUX_S4[0]	CLK_INT:MUX.1.OMUX_S5[1]	CLK_INT:MUX.0.OMUX_S5[1]	CLK_INT:MUX.0.OMUX_S4[0]
B60	CLK_INT:MUX.1.OMUX_S4[4]	CLK_INT:MUX.1.OMUX_S5[0]	CLK_INT:MUX.0.OMUX_S5[0]	CLK_INT:MUX.0.OMUX_S4[4]
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	CLK_INT:MUX.1.OMUX_S0[3]	CLK_INT:MUX.1.OMUX_S3[4]	CLK_INT:MUX.0.OMUX_S3[4]	CLK_INT:MUX.0.OMUX_S0[3]
B53	CLK_INT:MUX.1.OMUX_S0[2]	CLK_INT:MUX.1.OMUX_S3[3]	CLK_INT:MUX.0.OMUX_S3[3]	CLK_INT:MUX.0.OMUX_S0[2]
B52	CLK_INT:MUX.1.OMUX_S0[1]	CLK_INT:MUX.1.OMUX_S3[2]	CLK_INT:MUX.0.OMUX_S3[2]	CLK_INT:MUX.0.OMUX_S0[1]
B51	CLK_INT:MUX.1.OMUX_S0[0]	CLK_INT:MUX.1.OMUX_S3[1]	CLK_INT:MUX.0.OMUX_S3[1]	CLK_INT:MUX.0.OMUX_S0[0]
B50	CLK_INT:MUX.1.OMUX_S0[4]	CLK_INT:MUX.1.OMUX_S3[0]	CLK_INT:MUX.0.OMUX_S3[0]	CLK_INT:MUX.0.OMUX_S0[4]
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[3]	~CLK_INT:INV.0.IMUX_BUFG_SEL[7]	-
B43	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][4]
B42	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][3]
B41	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][2]
B40	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][1]
B39	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][0]
B38	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][5]
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[2]	~CLK_INT:INV.0.IMUX_BUFG_SEL[6]	-
B31	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][4]
B30	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][3]
B29	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][2]
B28	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][1]
B27	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][0]
B26	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][5]
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[1]	~CLK_INT:INV.0.IMUX_BUFG_SEL[5]	-
B19	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][4]
B18	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][3]
B17	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][2]
B16	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][1]
B15	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][0]
B14	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][5]
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[0]	~CLK_INT:INV.0.IMUX_BUFG_SEL[4]	-
B7	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][4]
B6	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][3]
B5	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][2]
B4	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][1]
B3	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][0]
B2	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][5]
B1	-	-	-	-
B0	-	-	-	-

virtex2 CLK_N_V2 rect R1
Bit	Frame
Bit	F0	F1	F2	F3
B7	BUFGMUX[3]:MUX.CLK[0]	-	-	BUFGMUX[7]:MUX.CLK[0]
B6	BUFGMUX[3]:MUX.CLK[3]	-	-	BUFGMUX[7]:MUX.CLK[3]
B5	BUFGMUX[3]:MUX.CLK[2]	-	-	BUFGMUX[7]:MUX.CLK[2]
B4	BUFGMUX[3]:MUX.CLK[1]	-	-	BUFGMUX[7]:MUX.CLK[1]
B3	BUFGMUX[3]:DISABLE_ATTR[0]	-	-	BUFGMUX[7]:DISABLE_ATTR[0]
B2	BUFGMUX[2]:DISABLE_ATTR[0]	-	-	BUFGMUX[6]:DISABLE_ATTR[0]
B1	BUFGMUX[2]:MUX.CLK[1]	-	-	BUFGMUX[6]:MUX.CLK[1]
B0	BUFGMUX[2]:MUX.CLK[2]	-	-	BUFGMUX[6]:MUX.CLK[2]

BUFGMUX[0]:DISABLE_ATTR	0.F0.B72
BUFGMUX[1]:DISABLE_ATTR	0.F0.B73
BUFGMUX[2]:DISABLE_ATTR	1.F0.B2
BUFGMUX[3]:DISABLE_ATTR	1.F0.B3
BUFGMUX[4]:DISABLE_ATTR	0.F3.B72
BUFGMUX[5]:DISABLE_ATTR	0.F3.B73
BUFGMUX[6]:DISABLE_ATTR	1.F3.B2
BUFGMUX[7]:DISABLE_ATTR	1.F3.B3
LOW	0
HIGH	1

BUFGMUX[0]:MUX.CLK	0.F0.B69	0.F0.B70	0.F0.B71	0.F0.B68
BUFGMUX[1]:MUX.CLK	0.F0.B76	0.F0.B75	0.F0.B74	0.F0.B77
BUFGMUX[2]:MUX.CLK	0.F0.B79	1.F0.B0	1.F0.B1	0.F0.B78
BUFGMUX[3]:MUX.CLK	1.F0.B6	1.F0.B5	1.F0.B4	1.F0.B7
BUFGMUX[4]:MUX.CLK	0.F3.B69	0.F3.B70	0.F3.B71	0.F3.B68
BUFGMUX[5]:MUX.CLK	0.F3.B76	0.F3.B75	0.F3.B74	0.F3.B77
BUFGMUX[6]:MUX.CLK	0.F3.B79	1.F3.B0	1.F3.B1	0.F3.B78
BUFGMUX[7]:MUX.CLK	1.F3.B6	1.F3.B5	1.F3.B4	1.F3.B7
INT	0	0	0	1
CKI	0	0	1	0
DCM_OUT_L	0	1	0	0
DCM_OUT_R	1	0	0	0

CLK_INT:INV.0.IMUX_BUFG_SEL[0]	0.F1.B8
CLK_INT:INV.0.IMUX_BUFG_SEL[1]	0.F1.B20
CLK_INT:INV.0.IMUX_BUFG_SEL[2]	0.F1.B32
CLK_INT:INV.0.IMUX_BUFG_SEL[3]	0.F1.B44
CLK_INT:INV.0.IMUX_BUFG_SEL[4]	0.F2.B8
CLK_INT:INV.0.IMUX_BUFG_SEL[5]	0.F2.B20
CLK_INT:INV.0.IMUX_BUFG_SEL[6]	0.F2.B32
CLK_INT:INV.0.IMUX_BUFG_SEL[7]	0.F2.B44
inverted	~[0]

CLK_INT:MUX.0.IMUX_BUFG_CLK[0]	0.F0.B2	0.F0.B7	0.F0.B6	0.F0.B5	0.F0.B4	0.F0.B3
CLK_INT:MUX.0.IMUX_BUFG_CLK[4]	0.F3.B2	0.F3.B7	0.F3.B6	0.F3.B5	0.F3.B4	0.F3.B3
CLK_INT:MUX.0.IMUX_BUFG_SEL[0]	0.F1.B7	0.F1.B6	0.F1.B5	0.F1.B4	0.F1.B3	0.F1.B2
CLK_INT:MUX.0.IMUX_BUFG_SEL[4]	0.F2.B7	0.F2.B6	0.F2.B5	0.F2.B4	0.F2.B3	0.F2.B2
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[0]	0	0	0	0	0	1
0.DBL_W2[1]	0	0	0	0	1	0
0.DBL_W2[2]	0	0	0	1	0	0
1.DBL_W0[0]	0	0	1	0	0	0
1.DBL_W0[1]	0	1	0	0	0	0
0.DBL_E0[0]	1	0	0	0	0	1
0.DBL_E0[1]	1	0	0	0	1	0
0.DBL_E0[2]	1	0	0	1	0	0
0.DBL_E1[0]	1	0	1	0	0	0
0.DBL_E1[1]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[1]	0.F0.B14	0.F0.B19	0.F0.B18	0.F0.B17	0.F0.B16	0.F0.B15
CLK_INT:MUX.0.IMUX_BUFG_CLK[5]	0.F3.B14	0.F3.B19	0.F3.B18	0.F3.B17	0.F3.B16	0.F3.B15
CLK_INT:MUX.0.IMUX_BUFG_SEL[1]	0.F1.B19	0.F1.B18	0.F1.B17	0.F1.B16	0.F1.B15	0.F1.B14
CLK_INT:MUX.0.IMUX_BUFG_SEL[5]	0.F2.B19	0.F2.B18	0.F2.B17	0.F2.B16	0.F2.B15	0.F2.B14
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[3]	0	0	0	0	0	1
0.DBL_W2[4]	0	0	0	0	1	0
1.DBL_W0[2]	0	0	0	1	0	0
1.DBL_W0[3]	0	0	1	0	0	0
1.DBL_W0[4]	0	1	0	0	0	0
0.DBL_E0[3]	1	0	0	0	0	1
0.DBL_E0[4]	1	0	0	0	1	0
0.DBL_E1[2]	1	0	0	1	0	0
0.DBL_E1[3]	1	0	1	0	0	0
0.DBL_E1[4]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[2]	0.F0.B26	0.F0.B31	0.F0.B30	0.F0.B29	0.F0.B28	0.F0.B27
CLK_INT:MUX.0.IMUX_BUFG_CLK[6]	0.F3.B26	0.F3.B31	0.F3.B30	0.F3.B29	0.F3.B28	0.F3.B27
CLK_INT:MUX.0.IMUX_BUFG_SEL[2]	0.F1.B31	0.F1.B30	0.F1.B29	0.F1.B28	0.F1.B27	0.F1.B26
CLK_INT:MUX.0.IMUX_BUFG_SEL[6]	0.F2.B31	0.F2.B30	0.F2.B29	0.F2.B28	0.F2.B27	0.F2.B26
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[5]	0	0	0	0	0	1
0.DBL_W2[6]	0	0	0	0	1	0
0.DBL_W2[7]	0	0	0	1	0	0
1.DBL_W0[5]	0	0	1	0	0	0
1.DBL_W0[6]	0	1	0	0	0	0
0.DBL_E0[5]	1	0	0	0	0	1
0.DBL_E0[6]	1	0	0	0	1	0
0.DBL_E0[7]	1	0	0	1	0	0
0.DBL_E1[5]	1	0	1	0	0	0
0.DBL_E1[6]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[3]	0.F0.B38	0.F0.B43	0.F0.B42	0.F0.B41	0.F0.B40	0.F0.B39
CLK_INT:MUX.0.IMUX_BUFG_CLK[7]	0.F3.B38	0.F3.B43	0.F3.B42	0.F3.B41	0.F3.B40	0.F3.B39
CLK_INT:MUX.0.IMUX_BUFG_SEL[3]	0.F1.B43	0.F1.B42	0.F1.B41	0.F1.B40	0.F1.B39	0.F1.B38
CLK_INT:MUX.0.IMUX_BUFG_SEL[7]	0.F2.B43	0.F2.B42	0.F2.B41	0.F2.B40	0.F2.B39	0.F2.B38
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[8]	0	0	0	0	0	1
0.DBL_W2[9]	0	0	0	0	1	0
1.DBL_W0[7]	0	0	0	1	0	0
1.DBL_W0[8]	0	0	1	0	0	0
1.DBL_W0[9]	0	1	0	0	0	0
0.DBL_E0[8]	1	0	0	0	0	1
0.DBL_E0[9]	1	0	0	0	1	0
0.DBL_E1[7]	1	0	0	1	0	0
0.DBL_E1[8]	1	0	1	0	0	0
0.DBL_E1[9]	1	1	0	0	0	0

CLK_INT:MUX.0.OMUX_S0	0.F3.B50	0.F3.B54	0.F3.B53	0.F3.B52	0.F3.B51
CLK_INT:MUX.0.OMUX_S3	0.F2.B54	0.F2.B53	0.F2.B52	0.F2.B51	0.F2.B50
CLK_INT:MUX.0.OMUX_S4	0.F3.B60	0.F3.B64	0.F3.B63	0.F3.B62	0.F3.B61
CLK_INT:MUX.0.OMUX_S5	0.F2.B64	0.F2.B63	0.F2.B62	0.F2.B61	0.F2.B60
NONE	0	0	0	0	0
0.OUT_BUFG[0]	0	0	0	0	1
0.OUT_BUFG[1]	0	0	0	1	0
0.OUT_BUFG[2]	0	0	1	0	0
0.OUT_BUFG[3]	0	1	0	0	0
0.OUT_BUFG[4]	1	0	0	0	1
0.OUT_BUFG[5]	1	0	0	1	0
0.OUT_BUFG[6]	1	0	1	0	0
0.OUT_BUFG[7]	1	1	0	0	0

CLK_INT:MUX.1.OMUX_S0	0.F0.B50	0.F0.B54	0.F0.B53	0.F0.B52	0.F0.B51
CLK_INT:MUX.1.OMUX_S3	0.F1.B54	0.F1.B53	0.F1.B52	0.F1.B51	0.F1.B50
CLK_INT:MUX.1.OMUX_S4	0.F0.B60	0.F0.B64	0.F0.B63	0.F0.B62	0.F0.B61
CLK_INT:MUX.1.OMUX_S5	0.F1.B64	0.F1.B63	0.F1.B62	0.F1.B61	0.F1.B60
NONE	0	0	0	0	0
0.OUT_BUFG[4]	0	0	0	0	1
0.OUT_BUFG[5]	0	0	0	1	0
0.OUT_BUFG[6]	0	0	1	0	0
0.OUT_BUFG[7]	0	1	0	0	0
0.OUT_BUFG[0]	1	0	0	0	1
0.OUT_BUFG[1]	1	0	0	1	0
0.OUT_BUFG[2]	1	0	1	0	0
0.OUT_BUFG[3]	1	1	0	0	0

Tile CLK_N_V2P

Cells: 2

Switchbox CLK_INT

virtex2 CLK_N_V2P switchbox CLK_INT muxes OMUX_S0
Bits	Destination
CELL[0].OMUX_S0
CELL[1].OMUX_S0
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_N_V2P switchbox CLK_INT muxes OMUX_S3
Bits	Destination
CELL[0].OMUX_S3
CELL[1].OMUX_S3
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_N_V2P switchbox CLK_INT muxes OMUX_S4
Bits	Destination
CELL[0].OMUX_S4
CELL[1].OMUX_S4
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_N_V2P switchbox CLK_INT muxes OMUX_S5
Bits	Destination
CELL[0].OMUX_S5
CELL[1].OMUX_S5
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_N_V2P switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[0]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_N_V2P switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[1]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_N_V2P switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[2]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_N_V2P switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[3]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_N_V2P switchbox CLK_INT muxes IMUX_BUFG_CLK[4]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[4]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_N_V2P switchbox CLK_INT muxes IMUX_BUFG_CLK[5]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[5]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_N_V2P switchbox CLK_INT muxes IMUX_BUFG_CLK[6]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[6]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_N_V2P switchbox CLK_INT muxes IMUX_BUFG_CLK[7]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[7]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_N_V2P switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[0]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_N_V2P switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[1]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_N_V2P switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[2]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_N_V2P switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[3]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_N_V2P switchbox CLK_INT muxes IMUX_BUFG_SEL[4]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[4]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_N_V2P switchbox CLK_INT muxes IMUX_BUFG_SEL[5]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[5]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_N_V2P switchbox CLK_INT muxes IMUX_BUFG_SEL[6]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[6]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_N_V2P switchbox CLK_INT muxes IMUX_BUFG_SEL[7]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[7]
	Source
CELL[1].DBL_W0[9]

Bel BUFGMUX[0]

virtex2 CLK_N_V2P bel BUFGMUX[0]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[0]
O	output	CELL[0].OUT_BUFG[0]
S	input	CELL[0].IMUX_BUFG_SEL[0]

Bel BUFGMUX[1]

virtex2 CLK_N_V2P bel BUFGMUX[1]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[1]
O	output	CELL[0].OUT_BUFG[1]
S	input	CELL[0].IMUX_BUFG_SEL[1]

Bel BUFGMUX[2]

virtex2 CLK_N_V2P bel BUFGMUX[2]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[2]
O	output	CELL[0].OUT_BUFG[2]
S	input	CELL[0].IMUX_BUFG_SEL[2]

Bel BUFGMUX[3]

virtex2 CLK_N_V2P bel BUFGMUX[3]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[3]
O	output	CELL[0].OUT_BUFG[3]
S	input	CELL[0].IMUX_BUFG_SEL[3]

Bel BUFGMUX[4]

virtex2 CLK_N_V2P bel BUFGMUX[4]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[4]
O	output	CELL[0].OUT_BUFG[4]
S	input	CELL[0].IMUX_BUFG_SEL[4]

Bel BUFGMUX[5]

virtex2 CLK_N_V2P bel BUFGMUX[5]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[5]
O	output	CELL[0].OUT_BUFG[5]
S	input	CELL[0].IMUX_BUFG_SEL[5]

Bel BUFGMUX[6]

virtex2 CLK_N_V2P bel BUFGMUX[6]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[6]
O	output	CELL[0].OUT_BUFG[6]
S	input	CELL[0].IMUX_BUFG_SEL[6]

Bel BUFGMUX[7]

virtex2 CLK_N_V2P bel BUFGMUX[7]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[7]
O	output	CELL[0].OUT_BUFG[7]
S	input	CELL[0].IMUX_BUFG_SEL[7]

Bel GLOBALSIG_N[0]

virtex2 CLK_N_V2P bel GLOBALSIG_N[0]
Pin	Direction	Wires

Bel GLOBALSIG_N[1]

virtex2 CLK_N_V2P bel GLOBALSIG_N[1]
Pin	Direction	Wires

Bel BREFCLK

virtex2 CLK_N_V2P bel BREFCLK
Pin	Direction	Wires

Bel wires

virtex2 CLK_N_V2P bel wires
Wire	Pins
CELL[0].IMUX_BUFG_CLK[0]	BUFGMUX[0].CLK
CELL[0].IMUX_BUFG_CLK[1]	BUFGMUX[1].CLK
CELL[0].IMUX_BUFG_CLK[2]	BUFGMUX[2].CLK
CELL[0].IMUX_BUFG_CLK[3]	BUFGMUX[3].CLK
CELL[0].IMUX_BUFG_CLK[4]	BUFGMUX[4].CLK
CELL[0].IMUX_BUFG_CLK[5]	BUFGMUX[5].CLK
CELL[0].IMUX_BUFG_CLK[6]	BUFGMUX[6].CLK
CELL[0].IMUX_BUFG_CLK[7]	BUFGMUX[7].CLK
CELL[0].IMUX_BUFG_SEL[0]	BUFGMUX[0].S
CELL[0].IMUX_BUFG_SEL[1]	BUFGMUX[1].S
CELL[0].IMUX_BUFG_SEL[2]	BUFGMUX[2].S
CELL[0].IMUX_BUFG_SEL[3]	BUFGMUX[3].S
CELL[0].IMUX_BUFG_SEL[4]	BUFGMUX[4].S
CELL[0].IMUX_BUFG_SEL[5]	BUFGMUX[5].S
CELL[0].IMUX_BUFG_SEL[6]	BUFGMUX[6].S
CELL[0].IMUX_BUFG_SEL[7]	BUFGMUX[7].S
CELL[0].OUT_BUFG[0]	BUFGMUX[0].O
CELL[0].OUT_BUFG[1]	BUFGMUX[1].O
CELL[0].OUT_BUFG[2]	BUFGMUX[2].O
CELL[0].OUT_BUFG[3]	BUFGMUX[3].O
CELL[0].OUT_BUFG[4]	BUFGMUX[4].O
CELL[0].OUT_BUFG[5]	BUFGMUX[5].O
CELL[0].OUT_BUFG[6]	BUFGMUX[6].O
CELL[0].OUT_BUFG[7]	BUFGMUX[7].O

Bitstream

virtex2 CLK_N_V2P rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3
B79	-	-	-	-
B78	-	-	-	-
B77	-	-	-	-
B76	-	-	-	-
B75	-	-	-	-
B74	-	-	-	-
B73	-	-	-	-
B72	-	-	-	-
B71	-	-	-	-
B70	-	-	-	-
B69	-	-	-	-
B68	-	-	-	-
B67	-	-	-	-
B66	-	-	-	-
B65	-	-	-	-
B64	-	-	-	-
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex2 CLK_N_V2P rect TERM
Bit	Frame
Bit	F0	F1	F2	F3
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

### Bitstream

virtex2 CLK_N_V2P rect R0
Bit	Frame
Bit	F0	F1	F2	F3
B79	BUFGMUX[2]:MUX.CLK[3]	-	-	BUFGMUX[6]:MUX.CLK[3]
B78	BUFGMUX[2]:MUX.CLK[0]	-	-	BUFGMUX[6]:MUX.CLK[0]
B77	BUFGMUX[1]:MUX.CLK[0]	-	-	BUFGMUX[5]:MUX.CLK[0]
B76	BUFGMUX[1]:MUX.CLK[3]	-	-	BUFGMUX[5]:MUX.CLK[3]
B75	BUFGMUX[1]:MUX.CLK[2]	-	-	BUFGMUX[5]:MUX.CLK[2]
B74	BUFGMUX[1]:MUX.CLK[1]	-	-	BUFGMUX[5]:MUX.CLK[1]
B73	BUFGMUX[1]:DISABLE_ATTR[0]	-	-	BUFGMUX[5]:DISABLE_ATTR[0]
B72	BUFGMUX[0]:DISABLE_ATTR[0]	-	-	BUFGMUX[4]:DISABLE_ATTR[0]
B71	BUFGMUX[0]:MUX.CLK[1]	-	-	BUFGMUX[4]:MUX.CLK[1]
B70	BUFGMUX[0]:MUX.CLK[2]	-	-	BUFGMUX[4]:MUX.CLK[2]
B69	BUFGMUX[0]:MUX.CLK[3]	-	-	BUFGMUX[4]:MUX.CLK[3]
B68	BUFGMUX[0]:MUX.CLK[0]	-	-	BUFGMUX[4]:MUX.CLK[0]
B67	-	-	-	-
B66	-	-	-	-
B65	-	-	-	-
B64	CLK_INT:MUX.1.OMUX_S4[3]	CLK_INT:MUX.1.OMUX_S5[4]	CLK_INT:MUX.0.OMUX_S5[4]	CLK_INT:MUX.0.OMUX_S4[3]
B63	CLK_INT:MUX.1.OMUX_S4[2]	CLK_INT:MUX.1.OMUX_S5[3]	CLK_INT:MUX.0.OMUX_S5[3]	CLK_INT:MUX.0.OMUX_S4[2]
B62	CLK_INT:MUX.1.OMUX_S4[1]	CLK_INT:MUX.1.OMUX_S5[2]	CLK_INT:MUX.0.OMUX_S5[2]	CLK_INT:MUX.0.OMUX_S4[1]
B61	CLK_INT:MUX.1.OMUX_S4[0]	CLK_INT:MUX.1.OMUX_S5[1]	CLK_INT:MUX.0.OMUX_S5[1]	CLK_INT:MUX.0.OMUX_S4[0]
B60	CLK_INT:MUX.1.OMUX_S4[4]	CLK_INT:MUX.1.OMUX_S5[0]	CLK_INT:MUX.0.OMUX_S5[0]	CLK_INT:MUX.0.OMUX_S4[4]
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	CLK_INT:MUX.1.OMUX_S0[3]	CLK_INT:MUX.1.OMUX_S3[4]	CLK_INT:MUX.0.OMUX_S3[4]	CLK_INT:MUX.0.OMUX_S0[3]
B53	CLK_INT:MUX.1.OMUX_S0[2]	CLK_INT:MUX.1.OMUX_S3[3]	CLK_INT:MUX.0.OMUX_S3[3]	CLK_INT:MUX.0.OMUX_S0[2]
B52	CLK_INT:MUX.1.OMUX_S0[1]	CLK_INT:MUX.1.OMUX_S3[2]	CLK_INT:MUX.0.OMUX_S3[2]	CLK_INT:MUX.0.OMUX_S0[1]
B51	CLK_INT:MUX.1.OMUX_S0[0]	CLK_INT:MUX.1.OMUX_S3[1]	CLK_INT:MUX.0.OMUX_S3[1]	CLK_INT:MUX.0.OMUX_S0[0]
B50	CLK_INT:MUX.1.OMUX_S0[4]	CLK_INT:MUX.1.OMUX_S3[0]	CLK_INT:MUX.0.OMUX_S3[0]	CLK_INT:MUX.0.OMUX_S0[4]
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[3]	~CLK_INT:INV.0.IMUX_BUFG_SEL[7]	-
B43	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][4]
B42	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][3]
B41	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][2]
B40	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][1]
B39	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][0]
B38	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][5]
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[2]	~CLK_INT:INV.0.IMUX_BUFG_SEL[6]	-
B31	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][4]
B30	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][3]
B29	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][2]
B28	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][1]
B27	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][0]
B26	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][5]
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[1]	~CLK_INT:INV.0.IMUX_BUFG_SEL[5]	-
B19	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][4]
B18	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][3]
B17	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][2]
B16	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][1]
B15	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][0]
B14	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][5]
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[0]	~CLK_INT:INV.0.IMUX_BUFG_SEL[4]	-
B7	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][4]
B6	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][3]
B5	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][2]
B4	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][1]
B3	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][0]
B2	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][5]
B1	-	-	-	-
B0	-	-	-	-

virtex2 CLK_N_V2P rect R1
Bit	Frame
Bit	F0	F1	F2	F3
B7	BUFGMUX[3]:MUX.CLK[0]	-	-	BUFGMUX[7]:MUX.CLK[0]
B6	BUFGMUX[3]:MUX.CLK[3]	-	-	BUFGMUX[7]:MUX.CLK[3]
B5	BUFGMUX[3]:MUX.CLK[2]	-	-	BUFGMUX[7]:MUX.CLK[2]
B4	BUFGMUX[3]:MUX.CLK[1]	-	-	BUFGMUX[7]:MUX.CLK[1]
B3	BUFGMUX[3]:DISABLE_ATTR[0]	-	-	BUFGMUX[7]:DISABLE_ATTR[0]
B2	BUFGMUX[2]:DISABLE_ATTR[0]	-	-	BUFGMUX[6]:DISABLE_ATTR[0]
B1	BUFGMUX[2]:MUX.CLK[1]	-	-	BUFGMUX[6]:MUX.CLK[1]
B0	BUFGMUX[2]:MUX.CLK[2]	-	-	BUFGMUX[6]:MUX.CLK[2]

BUFGMUX[0]:DISABLE_ATTR	0.F0.B72
BUFGMUX[1]:DISABLE_ATTR	0.F0.B73
BUFGMUX[2]:DISABLE_ATTR	1.F0.B2
BUFGMUX[3]:DISABLE_ATTR	1.F0.B3
BUFGMUX[4]:DISABLE_ATTR	0.F3.B72
BUFGMUX[5]:DISABLE_ATTR	0.F3.B73
BUFGMUX[6]:DISABLE_ATTR	1.F3.B2
BUFGMUX[7]:DISABLE_ATTR	1.F3.B3
LOW	0
HIGH	1

BUFGMUX[0]:MUX.CLK	0.F0.B69	0.F0.B70	0.F0.B71	0.F0.B68
BUFGMUX[1]:MUX.CLK	0.F0.B76	0.F0.B75	0.F0.B74	0.F0.B77
BUFGMUX[2]:MUX.CLK	0.F0.B79	1.F0.B0	1.F0.B1	0.F0.B78
BUFGMUX[3]:MUX.CLK	1.F0.B6	1.F0.B5	1.F0.B4	1.F0.B7
BUFGMUX[4]:MUX.CLK	0.F3.B69	0.F3.B70	0.F3.B71	0.F3.B68
BUFGMUX[5]:MUX.CLK	0.F3.B76	0.F3.B75	0.F3.B74	0.F3.B77
BUFGMUX[6]:MUX.CLK	0.F3.B79	1.F3.B0	1.F3.B1	0.F3.B78
BUFGMUX[7]:MUX.CLK	1.F3.B6	1.F3.B5	1.F3.B4	1.F3.B7
INT	0	0	0	1
CKI	0	0	1	0
DCM_OUT_L	0	1	0	0
DCM_OUT_R	1	0	0	0

CLK_INT:INV.0.IMUX_BUFG_SEL[0]	0.F1.B8
CLK_INT:INV.0.IMUX_BUFG_SEL[1]	0.F1.B20
CLK_INT:INV.0.IMUX_BUFG_SEL[2]	0.F1.B32
CLK_INT:INV.0.IMUX_BUFG_SEL[3]	0.F1.B44
CLK_INT:INV.0.IMUX_BUFG_SEL[4]	0.F2.B8
CLK_INT:INV.0.IMUX_BUFG_SEL[5]	0.F2.B20
CLK_INT:INV.0.IMUX_BUFG_SEL[6]	0.F2.B32
CLK_INT:INV.0.IMUX_BUFG_SEL[7]	0.F2.B44
inverted	~[0]

CLK_INT:MUX.0.IMUX_BUFG_CLK[0]	0.F0.B2	0.F0.B7	0.F0.B6	0.F0.B5	0.F0.B4	0.F0.B3
CLK_INT:MUX.0.IMUX_BUFG_CLK[4]	0.F3.B2	0.F3.B7	0.F3.B6	0.F3.B5	0.F3.B4	0.F3.B3
CLK_INT:MUX.0.IMUX_BUFG_SEL[0]	0.F1.B7	0.F1.B6	0.F1.B5	0.F1.B4	0.F1.B3	0.F1.B2
CLK_INT:MUX.0.IMUX_BUFG_SEL[4]	0.F2.B7	0.F2.B6	0.F2.B5	0.F2.B4	0.F2.B3	0.F2.B2
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[0]	0	0	0	0	0	1
0.DBL_W2[1]	0	0	0	0	1	0
0.DBL_W2[2]	0	0	0	1	0	0
1.DBL_W0[0]	0	0	1	0	0	0
1.DBL_W0[1]	0	1	0	0	0	0
0.DBL_E0[0]	1	0	0	0	0	1
0.DBL_E0[1]	1	0	0	0	1	0
0.DBL_E0[2]	1	0	0	1	0	0
0.DBL_E1[0]	1	0	1	0	0	0
0.DBL_E1[1]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[1]	0.F0.B14	0.F0.B19	0.F0.B18	0.F0.B17	0.F0.B16	0.F0.B15
CLK_INT:MUX.0.IMUX_BUFG_CLK[5]	0.F3.B14	0.F3.B19	0.F3.B18	0.F3.B17	0.F3.B16	0.F3.B15
CLK_INT:MUX.0.IMUX_BUFG_SEL[1]	0.F1.B19	0.F1.B18	0.F1.B17	0.F1.B16	0.F1.B15	0.F1.B14
CLK_INT:MUX.0.IMUX_BUFG_SEL[5]	0.F2.B19	0.F2.B18	0.F2.B17	0.F2.B16	0.F2.B15	0.F2.B14
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[3]	0	0	0	0	0	1
0.DBL_W2[4]	0	0	0	0	1	0
1.DBL_W0[2]	0	0	0	1	0	0
1.DBL_W0[3]	0	0	1	0	0	0
1.DBL_W0[4]	0	1	0	0	0	0
0.DBL_E0[3]	1	0	0	0	0	1
0.DBL_E0[4]	1	0	0	0	1	0
0.DBL_E1[2]	1	0	0	1	0	0
0.DBL_E1[3]	1	0	1	0	0	0
0.DBL_E1[4]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[2]	0.F0.B26	0.F0.B31	0.F0.B30	0.F0.B29	0.F0.B28	0.F0.B27
CLK_INT:MUX.0.IMUX_BUFG_CLK[6]	0.F3.B26	0.F3.B31	0.F3.B30	0.F3.B29	0.F3.B28	0.F3.B27
CLK_INT:MUX.0.IMUX_BUFG_SEL[2]	0.F1.B31	0.F1.B30	0.F1.B29	0.F1.B28	0.F1.B27	0.F1.B26
CLK_INT:MUX.0.IMUX_BUFG_SEL[6]	0.F2.B31	0.F2.B30	0.F2.B29	0.F2.B28	0.F2.B27	0.F2.B26
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[5]	0	0	0	0	0	1
0.DBL_W2[6]	0	0	0	0	1	0
0.DBL_W2[7]	0	0	0	1	0	0
1.DBL_W0[5]	0	0	1	0	0	0
1.DBL_W0[6]	0	1	0	0	0	0
0.DBL_E0[5]	1	0	0	0	0	1
0.DBL_E0[6]	1	0	0	0	1	0
0.DBL_E0[7]	1	0	0	1	0	0
0.DBL_E1[5]	1	0	1	0	0	0
0.DBL_E1[6]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[3]	0.F0.B38	0.F0.B43	0.F0.B42	0.F0.B41	0.F0.B40	0.F0.B39
CLK_INT:MUX.0.IMUX_BUFG_CLK[7]	0.F3.B38	0.F3.B43	0.F3.B42	0.F3.B41	0.F3.B40	0.F3.B39
CLK_INT:MUX.0.IMUX_BUFG_SEL[3]	0.F1.B43	0.F1.B42	0.F1.B41	0.F1.B40	0.F1.B39	0.F1.B38
CLK_INT:MUX.0.IMUX_BUFG_SEL[7]	0.F2.B43	0.F2.B42	0.F2.B41	0.F2.B40	0.F2.B39	0.F2.B38
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[8]	0	0	0	0	0	1
0.DBL_W2[9]	0	0	0	0	1	0
1.DBL_W0[7]	0	0	0	1	0	0
1.DBL_W0[8]	0	0	1	0	0	0
1.DBL_W0[9]	0	1	0	0	0	0
0.DBL_E0[8]	1	0	0	0	0	1
0.DBL_E0[9]	1	0	0	0	1	0
0.DBL_E1[7]	1	0	0	1	0	0
0.DBL_E1[8]	1	0	1	0	0	0
0.DBL_E1[9]	1	1	0	0	0	0

CLK_INT:MUX.0.OMUX_S0	0.F3.B50	0.F3.B54	0.F3.B53	0.F3.B52	0.F3.B51
CLK_INT:MUX.0.OMUX_S3	0.F2.B54	0.F2.B53	0.F2.B52	0.F2.B51	0.F2.B50
CLK_INT:MUX.0.OMUX_S4	0.F3.B60	0.F3.B64	0.F3.B63	0.F3.B62	0.F3.B61
CLK_INT:MUX.0.OMUX_S5	0.F2.B64	0.F2.B63	0.F2.B62	0.F2.B61	0.F2.B60
NONE	0	0	0	0	0
0.OUT_BUFG[0]	0	0	0	0	1
0.OUT_BUFG[1]	0	0	0	1	0
0.OUT_BUFG[2]	0	0	1	0	0
0.OUT_BUFG[3]	0	1	0	0	0
0.OUT_BUFG[4]	1	0	0	0	1
0.OUT_BUFG[5]	1	0	0	1	0
0.OUT_BUFG[6]	1	0	1	0	0
0.OUT_BUFG[7]	1	1	0	0	0

CLK_INT:MUX.1.OMUX_S0	0.F0.B50	0.F0.B54	0.F0.B53	0.F0.B52	0.F0.B51
CLK_INT:MUX.1.OMUX_S3	0.F1.B54	0.F1.B53	0.F1.B52	0.F1.B51	0.F1.B50
CLK_INT:MUX.1.OMUX_S4	0.F0.B60	0.F0.B64	0.F0.B63	0.F0.B62	0.F0.B61
CLK_INT:MUX.1.OMUX_S5	0.F1.B64	0.F1.B63	0.F1.B62	0.F1.B61	0.F1.B60
NONE	0	0	0	0	0
0.OUT_BUFG[4]	0	0	0	0	1
0.OUT_BUFG[5]	0	0	0	1	0
0.OUT_BUFG[6]	0	0	1	0	0
0.OUT_BUFG[7]	0	1	0	0	0
0.OUT_BUFG[0]	1	0	0	0	1
0.OUT_BUFG[1]	1	0	0	1	0
0.OUT_BUFG[2]	1	0	1	0	0
0.OUT_BUFG[3]	1	1	0	0	0

Tile CLK_N_V2PX

Cells: 2

Switchbox CLK_INT

virtex2 CLK_N_V2PX switchbox CLK_INT muxes OMUX_S0
Bits	Destination
CELL[0].OMUX_S0
CELL[1].OMUX_S0
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes OMUX_S3
Bits	Destination
CELL[0].OMUX_S3
CELL[1].OMUX_S3
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes OMUX_S4
Bits	Destination
CELL[0].OMUX_S4
CELL[1].OMUX_S4
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes OMUX_S5
Bits	Destination
CELL[0].OMUX_S5
CELL[1].OMUX_S5
	Source
CELL[0].OUT_BUFG[7]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[0]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[1]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[2]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[3]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes IMUX_BUFG_CLK[4]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[4]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes IMUX_BUFG_CLK[5]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[5]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes IMUX_BUFG_CLK[6]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[6]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes IMUX_BUFG_CLK[7]
Bits	Destination
CELL[0].IMUX_BUFG_CLK[7]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[0]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[1]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[2]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[3]
	Source
CELL[1].DBL_W0[9]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes IMUX_BUFG_SEL[4]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[4]
	Source
CELL[1].DBL_W0[1]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes IMUX_BUFG_SEL[5]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[5]
	Source
CELL[1].DBL_W0[4]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes IMUX_BUFG_SEL[6]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[6]
	Source
CELL[1].DBL_W0[6]

virtex2 CLK_N_V2PX switchbox CLK_INT muxes IMUX_BUFG_SEL[7]
Bits	Destination
CELL[0].IMUX_BUFG_SEL[7]
	Source
CELL[1].DBL_W0[9]

Bel BUFGMUX[0]

virtex2 CLK_N_V2PX bel BUFGMUX[0]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[0]
O	output	CELL[0].OUT_BUFG[0]
S	input	CELL[0].IMUX_BUFG_SEL[0]

Bel BUFGMUX[1]

virtex2 CLK_N_V2PX bel BUFGMUX[1]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[1]
O	output	CELL[0].OUT_BUFG[1]
S	input	CELL[0].IMUX_BUFG_SEL[1]

Bel BUFGMUX[2]

virtex2 CLK_N_V2PX bel BUFGMUX[2]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[2]
O	output	CELL[0].OUT_BUFG[2]
S	input	CELL[0].IMUX_BUFG_SEL[2]

Bel BUFGMUX[3]

virtex2 CLK_N_V2PX bel BUFGMUX[3]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[3]
O	output	CELL[0].OUT_BUFG[3]
S	input	CELL[0].IMUX_BUFG_SEL[3]

Bel BUFGMUX[4]

virtex2 CLK_N_V2PX bel BUFGMUX[4]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[4]
O	output	CELL[0].OUT_BUFG[4]
S	input	CELL[0].IMUX_BUFG_SEL[4]

Bel BUFGMUX[5]

virtex2 CLK_N_V2PX bel BUFGMUX[5]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[5]
O	output	CELL[0].OUT_BUFG[5]
S	input	CELL[0].IMUX_BUFG_SEL[5]

Bel BUFGMUX[6]

virtex2 CLK_N_V2PX bel BUFGMUX[6]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[6]
O	output	CELL[0].OUT_BUFG[6]
S	input	CELL[0].IMUX_BUFG_SEL[6]

Bel BUFGMUX[7]

virtex2 CLK_N_V2PX bel BUFGMUX[7]
Pin	Direction	Wires
CLK	input	CELL[0].IMUX_BUFG_CLK[7]
O	output	CELL[0].OUT_BUFG[7]
S	input	CELL[0].IMUX_BUFG_SEL[7]

Bel GLOBALSIG_N[0]

virtex2 CLK_N_V2PX bel GLOBALSIG_N[0]
Pin	Direction	Wires

Bel GLOBALSIG_N[1]

virtex2 CLK_N_V2PX bel GLOBALSIG_N[1]
Pin	Direction	Wires

Bel wires

virtex2 CLK_N_V2PX bel wires
Wire	Pins
CELL[0].IMUX_BUFG_CLK[0]	BUFGMUX[0].CLK
CELL[0].IMUX_BUFG_CLK[1]	BUFGMUX[1].CLK
CELL[0].IMUX_BUFG_CLK[2]	BUFGMUX[2].CLK
CELL[0].IMUX_BUFG_CLK[3]	BUFGMUX[3].CLK
CELL[0].IMUX_BUFG_CLK[4]	BUFGMUX[4].CLK
CELL[0].IMUX_BUFG_CLK[5]	BUFGMUX[5].CLK
CELL[0].IMUX_BUFG_CLK[6]	BUFGMUX[6].CLK
CELL[0].IMUX_BUFG_CLK[7]	BUFGMUX[7].CLK
CELL[0].IMUX_BUFG_SEL[0]	BUFGMUX[0].S
CELL[0].IMUX_BUFG_SEL[1]	BUFGMUX[1].S
CELL[0].IMUX_BUFG_SEL[2]	BUFGMUX[2].S
CELL[0].IMUX_BUFG_SEL[3]	BUFGMUX[3].S
CELL[0].IMUX_BUFG_SEL[4]	BUFGMUX[4].S
CELL[0].IMUX_BUFG_SEL[5]	BUFGMUX[5].S
CELL[0].IMUX_BUFG_SEL[6]	BUFGMUX[6].S
CELL[0].IMUX_BUFG_SEL[7]	BUFGMUX[7].S
CELL[0].OUT_BUFG[0]	BUFGMUX[0].O
CELL[0].OUT_BUFG[1]	BUFGMUX[1].O
CELL[0].OUT_BUFG[2]	BUFGMUX[2].O
CELL[0].OUT_BUFG[3]	BUFGMUX[3].O
CELL[0].OUT_BUFG[4]	BUFGMUX[4].O
CELL[0].OUT_BUFG[5]	BUFGMUX[5].O
CELL[0].OUT_BUFG[6]	BUFGMUX[6].O
CELL[0].OUT_BUFG[7]	BUFGMUX[7].O

Bitstream

virtex2 CLK_N_V2PX rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3
B79	-	-	-	-
B78	-	-	-	-
B77	-	-	-	-
B76	-	-	-	-
B75	-	-	-	-
B74	-	-	-	-
B73	-	-	-	-
B72	-	-	-	-
B71	-	-	-	-
B70	-	-	-	-
B69	-	-	-	-
B68	-	-	-	-
B67	-	-	-	-
B66	-	-	-	-
B65	-	-	-	-
B64	-	-	-	-
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex2 CLK_N_V2PX rect TERM
Bit	Frame
Bit	F0	F1	F2	F3
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

### Bitstream

virtex2 CLK_N_V2PX rect R0
Bit	Frame
Bit	F0	F1	F2	F3
B79	BUFGMUX[2]:MUX.CLK[3]	-	-	BUFGMUX[6]:MUX.CLK[3]
B78	BUFGMUX[2]:MUX.CLK[0]	-	-	BUFGMUX[6]:MUX.CLK[0]
B77	BUFGMUX[1]:MUX.CLK[0]	-	-	BUFGMUX[5]:MUX.CLK[0]
B76	BUFGMUX[1]:MUX.CLK[3]	-	-	BUFGMUX[5]:MUX.CLK[3]
B75	BUFGMUX[1]:MUX.CLK[2]	-	-	BUFGMUX[5]:MUX.CLK[2]
B74	BUFGMUX[1]:MUX.CLK[1]	-	-	BUFGMUX[5]:MUX.CLK[1]
B73	BUFGMUX[1]:DISABLE_ATTR[0]	-	-	BUFGMUX[5]:DISABLE_ATTR[0]
B72	BUFGMUX[0]:DISABLE_ATTR[0]	-	-	BUFGMUX[4]:DISABLE_ATTR[0]
B71	BUFGMUX[0]:MUX.CLK[1]	-	-	BUFGMUX[4]:MUX.CLK[1]
B70	BUFGMUX[0]:MUX.CLK[2]	-	-	BUFGMUX[4]:MUX.CLK[2]
B69	BUFGMUX[0]:MUX.CLK[3]	-	-	BUFGMUX[4]:MUX.CLK[3]
B68	BUFGMUX[0]:MUX.CLK[0]	-	-	BUFGMUX[4]:MUX.CLK[0]
B67	-	-	-	-
B66	-	-	-	-
B65	-	-	-	-
B64	CLK_INT:MUX.1.OMUX_S4[3]	CLK_INT:MUX.1.OMUX_S5[4]	CLK_INT:MUX.0.OMUX_S5[4]	CLK_INT:MUX.0.OMUX_S4[3]
B63	CLK_INT:MUX.1.OMUX_S4[2]	CLK_INT:MUX.1.OMUX_S5[3]	CLK_INT:MUX.0.OMUX_S5[3]	CLK_INT:MUX.0.OMUX_S4[2]
B62	CLK_INT:MUX.1.OMUX_S4[1]	CLK_INT:MUX.1.OMUX_S5[2]	CLK_INT:MUX.0.OMUX_S5[2]	CLK_INT:MUX.0.OMUX_S4[1]
B61	CLK_INT:MUX.1.OMUX_S4[0]	CLK_INT:MUX.1.OMUX_S5[1]	CLK_INT:MUX.0.OMUX_S5[1]	CLK_INT:MUX.0.OMUX_S4[0]
B60	CLK_INT:MUX.1.OMUX_S4[4]	CLK_INT:MUX.1.OMUX_S5[0]	CLK_INT:MUX.0.OMUX_S5[0]	CLK_INT:MUX.0.OMUX_S4[4]
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	CLK_INT:MUX.1.OMUX_S0[3]	CLK_INT:MUX.1.OMUX_S3[4]	CLK_INT:MUX.0.OMUX_S3[4]	CLK_INT:MUX.0.OMUX_S0[3]
B53	CLK_INT:MUX.1.OMUX_S0[2]	CLK_INT:MUX.1.OMUX_S3[3]	CLK_INT:MUX.0.OMUX_S3[3]	CLK_INT:MUX.0.OMUX_S0[2]
B52	CLK_INT:MUX.1.OMUX_S0[1]	CLK_INT:MUX.1.OMUX_S3[2]	CLK_INT:MUX.0.OMUX_S3[2]	CLK_INT:MUX.0.OMUX_S0[1]
B51	CLK_INT:MUX.1.OMUX_S0[0]	CLK_INT:MUX.1.OMUX_S3[1]	CLK_INT:MUX.0.OMUX_S3[1]	CLK_INT:MUX.0.OMUX_S0[0]
B50	CLK_INT:MUX.1.OMUX_S0[4]	CLK_INT:MUX.1.OMUX_S3[0]	CLK_INT:MUX.0.OMUX_S3[0]	CLK_INT:MUX.0.OMUX_S0[4]
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[3]	~CLK_INT:INV.0.IMUX_BUFG_SEL[7]	-
B43	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][4]
B42	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][3]
B41	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][2]
B40	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][1]
B39	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][0]
B38	CLK_INT:MUX.0.IMUX_BUFG_CLK[3][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[3][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[7][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[7][5]
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[2]	~CLK_INT:INV.0.IMUX_BUFG_SEL[6]	-
B31	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][4]
B30	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][3]
B29	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][2]
B28	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][1]
B27	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][0]
B26	CLK_INT:MUX.0.IMUX_BUFG_CLK[2][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[2][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[6][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[6][5]
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[1]	~CLK_INT:INV.0.IMUX_BUFG_SEL[5]	-
B19	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][4]
B18	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][3]
B17	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][2]
B16	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][1]
B15	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][0]
B14	CLK_INT:MUX.0.IMUX_BUFG_CLK[1][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[1][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[5][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[5][5]
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	~CLK_INT:INV.0.IMUX_BUFG_SEL[0]	~CLK_INT:INV.0.IMUX_BUFG_SEL[4]	-
B7	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][5]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][4]
B6	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][4]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][4]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][3]
B5	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][3]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][3]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][2]
B4	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][2]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][2]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][1]
B3	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][1]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][1]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][0]
B2	CLK_INT:MUX.0.IMUX_BUFG_CLK[0][5]	CLK_INT:MUX.0.IMUX_BUFG_SEL[0][0]	CLK_INT:MUX.0.IMUX_BUFG_SEL[4][0]	CLK_INT:MUX.0.IMUX_BUFG_CLK[4][5]
B1	-	-	-	-
B0	-	-	-	-

virtex2 CLK_N_V2PX rect R1
Bit	Frame
Bit	F0	F1	F2	F3
B7	BUFGMUX[3]:MUX.CLK[0]	-	-	BUFGMUX[7]:MUX.CLK[0]
B6	BUFGMUX[3]:MUX.CLK[3]	-	-	BUFGMUX[7]:MUX.CLK[3]
B5	BUFGMUX[3]:MUX.CLK[2]	-	-	BUFGMUX[7]:MUX.CLK[2]
B4	BUFGMUX[3]:MUX.CLK[1]	-	-	BUFGMUX[7]:MUX.CLK[1]
B3	BUFGMUX[3]:DISABLE_ATTR[0]	-	-	BUFGMUX[7]:DISABLE_ATTR[0]
B2	BUFGMUX[2]:DISABLE_ATTR[0]	-	-	BUFGMUX[6]:DISABLE_ATTR[0]
B1	BUFGMUX[2]:MUX.CLK[1]	-	-	BUFGMUX[6]:MUX.CLK[1]
B0	BUFGMUX[2]:MUX.CLK[2]	-	-	BUFGMUX[6]:MUX.CLK[2]

BUFGMUX[0]:DISABLE_ATTR	0.F0.B72
BUFGMUX[1]:DISABLE_ATTR	0.F0.B73
BUFGMUX[2]:DISABLE_ATTR	1.F0.B2
BUFGMUX[3]:DISABLE_ATTR	1.F0.B3
BUFGMUX[4]:DISABLE_ATTR	0.F3.B72
BUFGMUX[5]:DISABLE_ATTR	0.F3.B73
BUFGMUX[6]:DISABLE_ATTR	1.F3.B2
BUFGMUX[7]:DISABLE_ATTR	1.F3.B3
LOW	0
HIGH	1

BUFGMUX[0]:MUX.CLK	0.F0.B69	0.F0.B70	0.F0.B71	0.F0.B68
BUFGMUX[1]:MUX.CLK	0.F0.B76	0.F0.B75	0.F0.B74	0.F0.B77
BUFGMUX[2]:MUX.CLK	0.F0.B79	1.F0.B0	1.F0.B1	0.F0.B78
BUFGMUX[3]:MUX.CLK	1.F0.B6	1.F0.B5	1.F0.B4	1.F0.B7
BUFGMUX[4]:MUX.CLK	0.F3.B69	0.F3.B70	0.F3.B71	0.F3.B68
BUFGMUX[5]:MUX.CLK	0.F3.B76	0.F3.B75	0.F3.B74	0.F3.B77
BUFGMUX[6]:MUX.CLK	0.F3.B79	1.F3.B0	1.F3.B1	0.F3.B78
BUFGMUX[7]:MUX.CLK	1.F3.B6	1.F3.B5	1.F3.B4	1.F3.B7
INT	0	0	0	1
CKI	0	0	1	0
DCM_OUT_L	0	1	0	0
DCM_OUT_R	1	0	0	0

CLK_INT:INV.0.IMUX_BUFG_SEL[0]	0.F1.B8
CLK_INT:INV.0.IMUX_BUFG_SEL[1]	0.F1.B20
CLK_INT:INV.0.IMUX_BUFG_SEL[2]	0.F1.B32
CLK_INT:INV.0.IMUX_BUFG_SEL[3]	0.F1.B44
CLK_INT:INV.0.IMUX_BUFG_SEL[4]	0.F2.B8
CLK_INT:INV.0.IMUX_BUFG_SEL[5]	0.F2.B20
CLK_INT:INV.0.IMUX_BUFG_SEL[6]	0.F2.B32
CLK_INT:INV.0.IMUX_BUFG_SEL[7]	0.F2.B44
inverted	~[0]

CLK_INT:MUX.0.IMUX_BUFG_CLK[0]	0.F0.B2	0.F0.B7	0.F0.B6	0.F0.B5	0.F0.B4	0.F0.B3
CLK_INT:MUX.0.IMUX_BUFG_CLK[4]	0.F3.B2	0.F3.B7	0.F3.B6	0.F3.B5	0.F3.B4	0.F3.B3
CLK_INT:MUX.0.IMUX_BUFG_SEL[0]	0.F1.B7	0.F1.B6	0.F1.B5	0.F1.B4	0.F1.B3	0.F1.B2
CLK_INT:MUX.0.IMUX_BUFG_SEL[4]	0.F2.B7	0.F2.B6	0.F2.B5	0.F2.B4	0.F2.B3	0.F2.B2
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[0]	0	0	0	0	0	1
0.DBL_W2[1]	0	0	0	0	1	0
0.DBL_W2[2]	0	0	0	1	0	0
1.DBL_W0[0]	0	0	1	0	0	0
1.DBL_W0[1]	0	1	0	0	0	0
0.DBL_E0[0]	1	0	0	0	0	1
0.DBL_E0[1]	1	0	0	0	1	0
0.DBL_E0[2]	1	0	0	1	0	0
0.DBL_E1[0]	1	0	1	0	0	0
0.DBL_E1[1]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[1]	0.F0.B14	0.F0.B19	0.F0.B18	0.F0.B17	0.F0.B16	0.F0.B15
CLK_INT:MUX.0.IMUX_BUFG_CLK[5]	0.F3.B14	0.F3.B19	0.F3.B18	0.F3.B17	0.F3.B16	0.F3.B15
CLK_INT:MUX.0.IMUX_BUFG_SEL[1]	0.F1.B19	0.F1.B18	0.F1.B17	0.F1.B16	0.F1.B15	0.F1.B14
CLK_INT:MUX.0.IMUX_BUFG_SEL[5]	0.F2.B19	0.F2.B18	0.F2.B17	0.F2.B16	0.F2.B15	0.F2.B14
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[3]	0	0	0	0	0	1
0.DBL_W2[4]	0	0	0	0	1	0
1.DBL_W0[2]	0	0	0	1	0	0
1.DBL_W0[3]	0	0	1	0	0	0
1.DBL_W0[4]	0	1	0	0	0	0
0.DBL_E0[3]	1	0	0	0	0	1
0.DBL_E0[4]	1	0	0	0	1	0
0.DBL_E1[2]	1	0	0	1	0	0
0.DBL_E1[3]	1	0	1	0	0	0
0.DBL_E1[4]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[2]	0.F0.B26	0.F0.B31	0.F0.B30	0.F0.B29	0.F0.B28	0.F0.B27
CLK_INT:MUX.0.IMUX_BUFG_CLK[6]	0.F3.B26	0.F3.B31	0.F3.B30	0.F3.B29	0.F3.B28	0.F3.B27
CLK_INT:MUX.0.IMUX_BUFG_SEL[2]	0.F1.B31	0.F1.B30	0.F1.B29	0.F1.B28	0.F1.B27	0.F1.B26
CLK_INT:MUX.0.IMUX_BUFG_SEL[6]	0.F2.B31	0.F2.B30	0.F2.B29	0.F2.B28	0.F2.B27	0.F2.B26
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[5]	0	0	0	0	0	1
0.DBL_W2[6]	0	0	0	0	1	0
0.DBL_W2[7]	0	0	0	1	0	0
1.DBL_W0[5]	0	0	1	0	0	0
1.DBL_W0[6]	0	1	0	0	0	0
0.DBL_E0[5]	1	0	0	0	0	1
0.DBL_E0[6]	1	0	0	0	1	0
0.DBL_E0[7]	1	0	0	1	0	0
0.DBL_E1[5]	1	0	1	0	0	0
0.DBL_E1[6]	1	1	0	0	0	0

CLK_INT:MUX.0.IMUX_BUFG_CLK[3]	0.F0.B38	0.F0.B43	0.F0.B42	0.F0.B41	0.F0.B40	0.F0.B39
CLK_INT:MUX.0.IMUX_BUFG_CLK[7]	0.F3.B38	0.F3.B43	0.F3.B42	0.F3.B41	0.F3.B40	0.F3.B39
CLK_INT:MUX.0.IMUX_BUFG_SEL[3]	0.F1.B43	0.F1.B42	0.F1.B41	0.F1.B40	0.F1.B39	0.F1.B38
CLK_INT:MUX.0.IMUX_BUFG_SEL[7]	0.F2.B43	0.F2.B42	0.F2.B41	0.F2.B40	0.F2.B39	0.F2.B38
0.PULLUP	0	0	0	0	0	0
0.DBL_W2[8]	0	0	0	0	0	1
0.DBL_W2[9]	0	0	0	0	1	0
1.DBL_W0[7]	0	0	0	1	0	0
1.DBL_W0[8]	0	0	1	0	0	0
1.DBL_W0[9]	0	1	0	0	0	0
0.DBL_E0[8]	1	0	0	0	0	1
0.DBL_E0[9]	1	0	0	0	1	0
0.DBL_E1[7]	1	0	0	1	0	0
0.DBL_E1[8]	1	0	1	0	0	0
0.DBL_E1[9]	1	1	0	0	0	0

CLK_INT:MUX.0.OMUX_S0	0.F3.B50	0.F3.B54	0.F3.B53	0.F3.B52	0.F3.B51
CLK_INT:MUX.0.OMUX_S3	0.F2.B54	0.F2.B53	0.F2.B52	0.F2.B51	0.F2.B50
CLK_INT:MUX.0.OMUX_S4	0.F3.B60	0.F3.B64	0.F3.B63	0.F3.B62	0.F3.B61
CLK_INT:MUX.0.OMUX_S5	0.F2.B64	0.F2.B63	0.F2.B62	0.F2.B61	0.F2.B60
NONE	0	0	0	0	0
0.OUT_BUFG[0]	0	0	0	0	1
0.OUT_BUFG[1]	0	0	0	1	0
0.OUT_BUFG[2]	0	0	1	0	0
0.OUT_BUFG[3]	0	1	0	0	0
0.OUT_BUFG[4]	1	0	0	0	1
0.OUT_BUFG[5]	1	0	0	1	0
0.OUT_BUFG[6]	1	0	1	0	0
0.OUT_BUFG[7]	1	1	0	0	0

CLK_INT:MUX.1.OMUX_S0	0.F0.B50	0.F0.B54	0.F0.B53	0.F0.B52	0.F0.B51
CLK_INT:MUX.1.OMUX_S3	0.F1.B54	0.F1.B53	0.F1.B52	0.F1.B51	0.F1.B50
CLK_INT:MUX.1.OMUX_S4	0.F0.B60	0.F0.B64	0.F0.B63	0.F0.B62	0.F0.B61
CLK_INT:MUX.1.OMUX_S5	0.F1.B64	0.F1.B63	0.F1.B62	0.F1.B61	0.F1.B60
NONE	0	0	0	0	0
0.OUT_BUFG[4]	0	0	0	0	1
0.OUT_BUFG[5]	0	0	0	1	0
0.OUT_BUFG[6]	0	0	1	0	0
0.OUT_BUFG[7]	0	1	0	0	0
0.OUT_BUFG[0]	1	0	0	0	1
0.OUT_BUFG[1]	1	0	0	1	0
0.OUT_BUFG[2]	1	0	1	0	0
0.OUT_BUFG[3]	1	1	0	0	0

Tile CLKC

Cells: 0

Bel CLKC

virtex2 CLKC bel CLKC
Pin	Direction	Wires

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