Global buffers

TODO: document

Bitstream

The CLK_S tile uses two bitstream tiles:

tile 0: 4×80 tile located in the clock spine column, in the bits corresponding to the bottom interconnect row
tile 1: 4×16 tile located in the clock spine column, in the bits corresponding to the low special area (used for bottom IOB tiles and clock rows in normal columns)

The CLK_N tile uses two bitstream tiles:

tile 0: 4×80 tile located in the clock spine column, in the bits corresponding to the top interconnect row
tile 1: 4×16 tile located in the clock spine column, in the bits corresponding to the high special area (used for top IOB tiles and clock rows in normal columns)

Tile CLK_S

Cells: 2

Switchbox CLK_INT

virtex2 CLK_S switchbox CLK_INT permanent buffers
Destination	Source
CELL[0].DCM_CLKPAD[0]	CELL[0].OUT_CLKPAD[0]
CELL[0].DCM_CLKPAD[1]	CELL[0].OUT_CLKPAD[1]
CELL[0].DCM_CLKPAD[2]	CELL[0].OUT_CLKPAD[2]
CELL[0].DCM_CLKPAD[3]	CELL[0].OUT_CLKPAD[3]
CELL[0].DCM_CLKPAD[4]	CELL[1].OUT_CLKPAD[0]
CELL[0].DCM_CLKPAD[5]	CELL[1].OUT_CLKPAD[1]
CELL[0].DCM_CLKPAD[6]	CELL[1].OUT_CLKPAD[2]
CELL[0].DCM_CLKPAD[7]	CELL[1].OUT_CLKPAD[3]
CELL[1].DCM_CLKPAD[0]	CELL[1].OUT_CLKPAD[0]
CELL[1].DCM_CLKPAD[1]	CELL[1].OUT_CLKPAD[1]
CELL[1].DCM_CLKPAD[2]	CELL[1].OUT_CLKPAD[2]
CELL[1].DCM_CLKPAD[3]	CELL[1].OUT_CLKPAD[3]
CELL[1].DCM_CLKPAD[4]	CELL[0].OUT_CLKPAD[0]
CELL[1].DCM_CLKPAD[5]	CELL[0].OUT_CLKPAD[1]
CELL[1].DCM_CLKPAD[6]	CELL[0].OUT_CLKPAD[2]
CELL[1].DCM_CLKPAD[7]	CELL[0].OUT_CLKPAD[3]

virtex2 CLK_S switchbox CLK_INT muxes OMUX_N10
Bits					Destination
MAIN[3][28]	MAIN[3][24]	MAIN[3][25]	MAIN[3][26]	MAIN[3][27]	CELL[0].OMUX_N10	-
MAIN[0][28]	MAIN[0][24]	MAIN[0][25]	MAIN[0][26]	MAIN[0][27]	-	CELL[1].OMUX_N10
					Source
0	0	0	0	0	off	off
0	0	0	0	1	CELL[1].GCLK_S[0]	CELL[1].GCLK_S[4]
0	0	0	1	0	CELL[1].GCLK_S[1]	CELL[1].GCLK_S[5]
0	0	1	0	0	CELL[1].GCLK_S[2]	CELL[1].GCLK_S[6]
0	1	0	0	0	CELL[1].GCLK_S[3]	CELL[1].GCLK_S[7]
1	0	0	0	1	CELL[1].GCLK_S[4]	CELL[1].GCLK_S[0]
1	0	0	1	0	CELL[1].GCLK_S[5]	CELL[1].GCLK_S[1]
1	0	1	0	0	CELL[1].GCLK_S[6]	CELL[1].GCLK_S[2]
1	1	0	0	0	CELL[1].GCLK_S[7]	CELL[1].GCLK_S[3]

virtex2 CLK_S switchbox CLK_INT muxes OMUX_N11
Bits					Destination
MAIN[2][24]	MAIN[2][25]	MAIN[2][26]	MAIN[2][27]	MAIN[2][28]	CELL[0].OMUX_N11	-
MAIN[1][24]	MAIN[1][25]	MAIN[1][26]	MAIN[1][27]	MAIN[1][28]	-	CELL[1].OMUX_N11
					Source
0	0	0	0	0	off	off
0	0	0	0	1	CELL[1].GCLK_S[0]	CELL[1].GCLK_S[4]
0	0	0	1	0	CELL[1].GCLK_S[1]	CELL[1].GCLK_S[5]
0	0	1	0	0	CELL[1].GCLK_S[2]	CELL[1].GCLK_S[6]
0	1	0	0	0	CELL[1].GCLK_S[3]	CELL[1].GCLK_S[7]
1	0	0	0	1	CELL[1].GCLK_S[4]	CELL[1].GCLK_S[0]
1	0	0	1	0	CELL[1].GCLK_S[5]	CELL[1].GCLK_S[1]
1	0	1	0	0	CELL[1].GCLK_S[6]	CELL[1].GCLK_S[2]
1	1	0	0	0	CELL[1].GCLK_S[7]	CELL[1].GCLK_S[3]

virtex2 CLK_S switchbox CLK_INT muxes OMUX_N12
Bits					Destination
MAIN[3][18]	MAIN[3][14]	MAIN[3][15]	MAIN[3][16]	MAIN[3][17]	CELL[0].OMUX_N12	-
MAIN[0][18]	MAIN[0][14]	MAIN[0][15]	MAIN[0][16]	MAIN[0][17]	-	CELL[1].OMUX_N12
					Source
0	0	0	0	0	off	off
0	0	0	0	1	CELL[1].GCLK_S[0]	CELL[1].GCLK_S[4]
0	0	0	1	0	CELL[1].GCLK_S[1]	CELL[1].GCLK_S[5]
0	0	1	0	0	CELL[1].GCLK_S[2]	CELL[1].GCLK_S[6]
0	1	0	0	0	CELL[1].GCLK_S[3]	CELL[1].GCLK_S[7]
1	0	0	0	1	CELL[1].GCLK_S[4]	CELL[1].GCLK_S[0]
1	0	0	1	0	CELL[1].GCLK_S[5]	CELL[1].GCLK_S[1]
1	0	1	0	0	CELL[1].GCLK_S[6]	CELL[1].GCLK_S[2]
1	1	0	0	0	CELL[1].GCLK_S[7]	CELL[1].GCLK_S[3]

virtex2 CLK_S switchbox CLK_INT muxes OMUX_N15
Bits					Destination
MAIN[2][14]	MAIN[2][15]	MAIN[2][16]	MAIN[2][17]	MAIN[2][18]	CELL[0].OMUX_N15	-
MAIN[1][14]	MAIN[1][15]	MAIN[1][16]	MAIN[1][17]	MAIN[1][18]	-	CELL[1].OMUX_N15
					Source
0	0	0	0	0	off	off
0	0	0	0	1	CELL[1].GCLK_S[0]	CELL[1].GCLK_S[4]
0	0	0	1	0	CELL[1].GCLK_S[1]	CELL[1].GCLK_S[5]
0	0	1	0	0	CELL[1].GCLK_S[2]	CELL[1].GCLK_S[6]
0	1	0	0	0	CELL[1].GCLK_S[3]	CELL[1].GCLK_S[7]
1	0	0	0	1	CELL[1].GCLK_S[4]	CELL[1].GCLK_S[0]
1	0	0	1	0	CELL[1].GCLK_S[5]	CELL[1].GCLK_S[1]
1	0	1	0	0	CELL[1].GCLK_S[6]	CELL[1].GCLK_S[2]
1	1	0	0	0	CELL[1].GCLK_S[7]	CELL[1].GCLK_S[3]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[0]
Bits						Destination
MAIN[0][40]	MAIN[0][35]	MAIN[0][36]	MAIN[0][37]	MAIN[0][38]	MAIN[0][39]	CELL[1].IMUX_BUFG_CLK_INT[0]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[0]
0	0	0	0	1	0	CELL[0].DBL_W2[1]
0	0	0	1	0	0	CELL[0].DBL_W2[2]
0	0	1	0	0	0	CELL[1].DBL_W0[0]
0	1	0	0	0	0	CELL[1].DBL_W0[1]
1	0	0	0	0	1	CELL[0].DBL_E0[0]
1	0	0	0	1	0	CELL[0].DBL_E0[1]
1	0	0	1	0	0	CELL[0].DBL_E0[2]
1	0	1	0	0	0	CELL[0].DBL_E1[0]
1	1	0	0	0	0	CELL[0].DBL_E1[1]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[1]
Bits						Destination
MAIN[0][52]	MAIN[0][47]	MAIN[0][48]	MAIN[0][49]	MAIN[0][50]	MAIN[0][51]	CELL[1].IMUX_BUFG_CLK_INT[1]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[3]
0	0	0	0	1	0	CELL[0].DBL_W2[4]
0	0	0	1	0	0	CELL[1].DBL_W0[2]
0	0	1	0	0	0	CELL[1].DBL_W0[3]
0	1	0	0	0	0	CELL[1].DBL_W0[4]
1	0	0	0	0	1	CELL[0].DBL_E0[3]
1	0	0	0	1	0	CELL[0].DBL_E0[4]
1	0	0	1	0	0	CELL[0].DBL_E1[2]
1	0	1	0	0	0	CELL[0].DBL_E1[3]
1	1	0	0	0	0	CELL[0].DBL_E1[4]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[2]
Bits						Destination
MAIN[0][64]	MAIN[0][59]	MAIN[0][60]	MAIN[0][61]	MAIN[0][62]	MAIN[0][63]	CELL[1].IMUX_BUFG_CLK_INT[2]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[5]
0	0	0	0	1	0	CELL[0].DBL_W2[6]
0	0	0	1	0	0	CELL[0].DBL_W2[7]
0	0	1	0	0	0	CELL[1].DBL_W0[5]
0	1	0	0	0	0	CELL[1].DBL_W0[6]
1	0	0	0	0	1	CELL[0].DBL_E0[5]
1	0	0	0	1	0	CELL[0].DBL_E0[6]
1	0	0	1	0	0	CELL[0].DBL_E0[7]
1	0	1	0	0	0	CELL[0].DBL_E1[5]
1	1	0	0	0	0	CELL[0].DBL_E1[6]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[3]
Bits						Destination
MAIN[0][76]	MAIN[0][71]	MAIN[0][72]	MAIN[0][73]	MAIN[0][74]	MAIN[0][75]	CELL[1].IMUX_BUFG_CLK_INT[3]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[8]
0	0	0	0	1	0	CELL[0].DBL_W2[9]
0	0	0	1	0	0	CELL[1].DBL_W0[7]
0	0	1	0	0	0	CELL[1].DBL_W0[8]
0	1	0	0	0	0	CELL[1].DBL_W0[9]
1	0	0	0	0	1	CELL[0].DBL_E0[8]
1	0	0	0	1	0	CELL[0].DBL_E0[9]
1	0	0	1	0	0	CELL[0].DBL_E1[7]
1	0	1	0	0	0	CELL[0].DBL_E1[8]
1	1	0	0	0	0	CELL[0].DBL_E1[9]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[4]
Bits						Destination
MAIN[3][40]	MAIN[3][35]	MAIN[3][36]	MAIN[3][37]	MAIN[3][38]	MAIN[3][39]	CELL[1].IMUX_BUFG_CLK_INT[4]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[0]
0	0	0	0	1	0	CELL[0].DBL_W2[1]
0	0	0	1	0	0	CELL[0].DBL_W2[2]
0	0	1	0	0	0	CELL[1].DBL_W0[0]
0	1	0	0	0	0	CELL[1].DBL_W0[1]
1	0	0	0	0	1	CELL[0].DBL_E0[0]
1	0	0	0	1	0	CELL[0].DBL_E0[1]
1	0	0	1	0	0	CELL[0].DBL_E0[2]
1	0	1	0	0	0	CELL[0].DBL_E1[0]
1	1	0	0	0	0	CELL[0].DBL_E1[1]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[5]
Bits						Destination
MAIN[3][52]	MAIN[3][47]	MAIN[3][48]	MAIN[3][49]	MAIN[3][50]	MAIN[3][51]	CELL[1].IMUX_BUFG_CLK_INT[5]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[3]
0	0	0	0	1	0	CELL[0].DBL_W2[4]
0	0	0	1	0	0	CELL[1].DBL_W0[2]
0	0	1	0	0	0	CELL[1].DBL_W0[3]
0	1	0	0	0	0	CELL[1].DBL_W0[4]
1	0	0	0	0	1	CELL[0].DBL_E0[3]
1	0	0	0	1	0	CELL[0].DBL_E0[4]
1	0	0	1	0	0	CELL[0].DBL_E1[2]
1	0	1	0	0	0	CELL[0].DBL_E1[3]
1	1	0	0	0	0	CELL[0].DBL_E1[4]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[6]
Bits						Destination
MAIN[3][64]	MAIN[3][59]	MAIN[3][60]	MAIN[3][61]	MAIN[3][62]	MAIN[3][63]	CELL[1].IMUX_BUFG_CLK_INT[6]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[5]
0	0	0	0	1	0	CELL[0].DBL_W2[6]
0	0	0	1	0	0	CELL[0].DBL_W2[7]
0	0	1	0	0	0	CELL[1].DBL_W0[5]
0	1	0	0	0	0	CELL[1].DBL_W0[6]
1	0	0	0	0	1	CELL[0].DBL_E0[5]
1	0	0	0	1	0	CELL[0].DBL_E0[6]
1	0	0	1	0	0	CELL[0].DBL_E0[7]
1	0	1	0	0	0	CELL[0].DBL_E1[5]
1	1	0	0	0	0	CELL[0].DBL_E1[6]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[7]
Bits						Destination
MAIN[3][76]	MAIN[3][71]	MAIN[3][72]	MAIN[3][73]	MAIN[3][74]	MAIN[3][75]	CELL[1].IMUX_BUFG_CLK_INT[7]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[8]
0	0	0	0	1	0	CELL[0].DBL_W2[9]
0	0	0	1	0	0	CELL[1].DBL_W0[7]
0	0	1	0	0	0	CELL[1].DBL_W0[8]
0	1	0	0	0	0	CELL[1].DBL_W0[9]
1	0	0	0	0	1	CELL[0].DBL_E0[8]
1	0	0	0	1	0	CELL[0].DBL_E0[9]
1	0	0	1	0	0	CELL[0].DBL_E1[7]
1	0	1	0	0	0	CELL[0].DBL_E1[8]
1	1	0	0	0	0	CELL[0].DBL_E1[9]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits				Destination
MAIN[0][10]	MAIN[0][9]	MAIN[0][7]	MAIN[0][8]	CELL[1].IMUX_BUFG_CLK[0]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].DCM_BUS[0]
0	0	1	0	CELL[1].OUT_CLKPAD[0]
0	1	0	0	CELL[1].DCM_BUS[0]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[0]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits				Destination
MAIN[0][1]	MAIN[0][2]	MAIN[0][4]	MAIN[0][3]	CELL[1].IMUX_BUFG_CLK[1]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].DCM_BUS[1]
0	0	1	0	CELL[1].OUT_CLKPAD[1]
0	1	0	0	CELL[1].DCM_BUS[1]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[1]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits				Destination
MAIN[0][0]	TERM[0][15]	TERM[0][13]	TERM[0][14]	CELL[1].IMUX_BUFG_CLK[2]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].DCM_BUS[2]
0	0	1	0	CELL[1].OUT_CLKPAD[2]
0	1	0	0	CELL[1].DCM_BUS[2]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[2]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits				Destination
TERM[0][7]	TERM[0][8]	TERM[0][10]	TERM[0][9]	CELL[1].IMUX_BUFG_CLK[3]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].DCM_BUS[3]
0	0	1	0	CELL[1].OUT_CLKPAD[3]
0	1	0	0	CELL[1].DCM_BUS[3]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[3]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_CLK[4]
Bits				Destination
MAIN[3][10]	MAIN[3][9]	MAIN[3][8]	MAIN[3][7]	CELL[1].IMUX_BUFG_CLK[4]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].OUT_CLKPAD[0]
0	0	1	0	CELL[0].DCM_BUS[4]
0	1	0	0	CELL[1].DCM_BUS[4]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[4]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_CLK[5]
Bits				Destination
MAIN[3][1]	MAIN[3][2]	MAIN[3][3]	MAIN[3][4]	CELL[1].IMUX_BUFG_CLK[5]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].OUT_CLKPAD[1]
0	0	1	0	CELL[0].DCM_BUS[5]
0	1	0	0	CELL[1].DCM_BUS[5]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[5]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_CLK[6]
Bits				Destination
MAIN[3][0]	TERM[3][15]	TERM[3][14]	TERM[3][13]	CELL[1].IMUX_BUFG_CLK[6]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].OUT_CLKPAD[2]
0	0	1	0	CELL[0].DCM_BUS[6]
0	1	0	0	CELL[1].DCM_BUS[6]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[6]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_CLK[7]
Bits				Destination
TERM[3][7]	TERM[3][8]	TERM[3][9]	TERM[3][10]	CELL[1].IMUX_BUFG_CLK[7]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].OUT_CLKPAD[3]
0	0	1	0	CELL[0].DCM_BUS[7]
0	1	0	0	CELL[1].DCM_BUS[7]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[7]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits						Destination
MAIN[1][35]	MAIN[1][36]	MAIN[1][37]	MAIN[1][38]	MAIN[1][39]	MAIN[1][40]	CELL[1].IMUX_BUFG_SEL[0]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[0]
0	0	0	0	1	0	CELL[0].DBL_W2[1]
0	0	0	1	0	0	CELL[0].DBL_W2[2]
0	0	1	0	0	0	CELL[1].DBL_W0[0]
0	1	0	0	0	0	CELL[1].DBL_W0[1]
1	0	0	0	0	1	CELL[0].DBL_E0[0]
1	0	0	0	1	0	CELL[0].DBL_E0[1]
1	0	0	1	0	0	CELL[0].DBL_E0[2]
1	0	1	0	0	0	CELL[0].DBL_E1[0]
1	1	0	0	0	0	CELL[0].DBL_E1[1]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits						Destination
MAIN[1][47]	MAIN[1][48]	MAIN[1][49]	MAIN[1][50]	MAIN[1][51]	MAIN[1][52]	CELL[1].IMUX_BUFG_SEL[1]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[3]
0	0	0	0	1	0	CELL[0].DBL_W2[4]
0	0	0	1	0	0	CELL[1].DBL_W0[2]
0	0	1	0	0	0	CELL[1].DBL_W0[3]
0	1	0	0	0	0	CELL[1].DBL_W0[4]
1	0	0	0	0	1	CELL[0].DBL_E0[3]
1	0	0	0	1	0	CELL[0].DBL_E0[4]
1	0	0	1	0	0	CELL[0].DBL_E1[2]
1	0	1	0	0	0	CELL[0].DBL_E1[3]
1	1	0	0	0	0	CELL[0].DBL_E1[4]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits						Destination
MAIN[1][59]	MAIN[1][60]	MAIN[1][61]	MAIN[1][62]	MAIN[1][63]	MAIN[1][64]	CELL[1].IMUX_BUFG_SEL[2]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[5]
0	0	0	0	1	0	CELL[0].DBL_W2[6]
0	0	0	1	0	0	CELL[0].DBL_W2[7]
0	0	1	0	0	0	CELL[1].DBL_W0[5]
0	1	0	0	0	0	CELL[1].DBL_W0[6]
1	0	0	0	0	1	CELL[0].DBL_E0[5]
1	0	0	0	1	0	CELL[0].DBL_E0[6]
1	0	0	1	0	0	CELL[0].DBL_E0[7]
1	0	1	0	0	0	CELL[0].DBL_E1[5]
1	1	0	0	0	0	CELL[0].DBL_E1[6]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits						Destination
MAIN[1][71]	MAIN[1][72]	MAIN[1][73]	MAIN[1][74]	MAIN[1][75]	MAIN[1][76]	CELL[1].IMUX_BUFG_SEL[3]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[8]
0	0	0	0	1	0	CELL[0].DBL_W2[9]
0	0	0	1	0	0	CELL[1].DBL_W0[7]
0	0	1	0	0	0	CELL[1].DBL_W0[8]
0	1	0	0	0	0	CELL[1].DBL_W0[9]
1	0	0	0	0	1	CELL[0].DBL_E0[8]
1	0	0	0	1	0	CELL[0].DBL_E0[9]
1	0	0	1	0	0	CELL[0].DBL_E1[7]
1	0	1	0	0	0	CELL[0].DBL_E1[8]
1	1	0	0	0	0	CELL[0].DBL_E1[9]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_SEL[4]
Bits						Destination
MAIN[2][35]	MAIN[2][36]	MAIN[2][37]	MAIN[2][38]	MAIN[2][39]	MAIN[2][40]	CELL[1].IMUX_BUFG_SEL[4]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[0]
0	0	0	0	1	0	CELL[0].DBL_W2[1]
0	0	0	1	0	0	CELL[0].DBL_W2[2]
0	0	1	0	0	0	CELL[1].DBL_W0[0]
0	1	0	0	0	0	CELL[1].DBL_W0[1]
1	0	0	0	0	1	CELL[0].DBL_E0[0]
1	0	0	0	1	0	CELL[0].DBL_E0[1]
1	0	0	1	0	0	CELL[0].DBL_E0[2]
1	0	1	0	0	0	CELL[0].DBL_E1[0]
1	1	0	0	0	0	CELL[0].DBL_E1[1]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_SEL[5]
Bits						Destination
MAIN[2][47]	MAIN[2][48]	MAIN[2][49]	MAIN[2][50]	MAIN[2][51]	MAIN[2][52]	CELL[1].IMUX_BUFG_SEL[5]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[3]
0	0	0	0	1	0	CELL[0].DBL_W2[4]
0	0	0	1	0	0	CELL[1].DBL_W0[2]
0	0	1	0	0	0	CELL[1].DBL_W0[3]
0	1	0	0	0	0	CELL[1].DBL_W0[4]
1	0	0	0	0	1	CELL[0].DBL_E0[3]
1	0	0	0	1	0	CELL[0].DBL_E0[4]
1	0	0	1	0	0	CELL[0].DBL_E1[2]
1	0	1	0	0	0	CELL[0].DBL_E1[3]
1	1	0	0	0	0	CELL[0].DBL_E1[4]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_SEL[6]
Bits						Destination
MAIN[2][59]	MAIN[2][60]	MAIN[2][61]	MAIN[2][62]	MAIN[2][63]	MAIN[2][64]	CELL[1].IMUX_BUFG_SEL[6]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[5]
0	0	0	0	1	0	CELL[0].DBL_W2[6]
0	0	0	1	0	0	CELL[0].DBL_W2[7]
0	0	1	0	0	0	CELL[1].DBL_W0[5]
0	1	0	0	0	0	CELL[1].DBL_W0[6]
1	0	0	0	0	1	CELL[0].DBL_E0[5]
1	0	0	0	1	0	CELL[0].DBL_E0[6]
1	0	0	1	0	0	CELL[0].DBL_E0[7]
1	0	1	0	0	0	CELL[0].DBL_E1[5]
1	1	0	0	0	0	CELL[0].DBL_E1[6]

virtex2 CLK_S switchbox CLK_INT muxes IMUX_BUFG_SEL[7]
Bits						Destination
MAIN[2][71]	MAIN[2][72]	MAIN[2][73]	MAIN[2][74]	MAIN[2][75]	MAIN[2][76]	CELL[1].IMUX_BUFG_SEL[7]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[8]
0	0	0	0	1	0	CELL[0].DBL_W2[9]
0	0	0	1	0	0	CELL[1].DBL_W0[7]
0	0	1	0	0	0	CELL[1].DBL_W0[8]
0	1	0	0	0	0	CELL[1].DBL_W0[9]
1	0	0	0	0	1	CELL[0].DBL_E0[8]
1	0	0	0	1	0	CELL[0].DBL_E0[9]
1	0	0	1	0	0	CELL[0].DBL_E1[7]
1	0	1	0	0	0	CELL[0].DBL_E1[8]
1	1	0	0	0	0	CELL[0].DBL_E1[9]

Bels BUFGMUX

virtex2 CLK_S bel BUFGMUX pins
Pin	Direction	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]	BUFGMUX[4]	BUFGMUX[5]	BUFGMUX[6]	BUFGMUX[7]
I0	in	CELL[1].IMUX_BUFG_CLK[0]	CELL[1].IMUX_BUFG_CLK[1]	CELL[1].IMUX_BUFG_CLK[2]	CELL[1].IMUX_BUFG_CLK[3]	CELL[1].IMUX_BUFG_CLK[4]	CELL[1].IMUX_BUFG_CLK[5]	CELL[1].IMUX_BUFG_CLK[6]	CELL[1].IMUX_BUFG_CLK[7]
I1	in	CELL[1].IMUX_BUFG_CLK[1]	CELL[1].IMUX_BUFG_CLK[0]	CELL[1].IMUX_BUFG_CLK[3]	CELL[1].IMUX_BUFG_CLK[2]	CELL[1].IMUX_BUFG_CLK[5]	CELL[1].IMUX_BUFG_CLK[4]	CELL[1].IMUX_BUFG_CLK[7]	CELL[1].IMUX_BUFG_CLK[6]
S	in	CELL[1].IMUX_BUFG_SEL[0] invert by !MAIN[1][34]	CELL[1].IMUX_BUFG_SEL[1] invert by !MAIN[1][46]	CELL[1].IMUX_BUFG_SEL[2] invert by !MAIN[1][58]	CELL[1].IMUX_BUFG_SEL[3] invert by !MAIN[1][70]	CELL[1].IMUX_BUFG_SEL[4] invert by !MAIN[2][34]	CELL[1].IMUX_BUFG_SEL[5] invert by !MAIN[2][46]	CELL[1].IMUX_BUFG_SEL[6] invert by !MAIN[2][58]	CELL[1].IMUX_BUFG_SEL[7] invert by !MAIN[2][70]
O	out	CELL[1].GCLK_S[0]	CELL[1].GCLK_S[1]	CELL[1].GCLK_S[2]	CELL[1].GCLK_S[3]	CELL[1].GCLK_S[4]	CELL[1].GCLK_S[5]	CELL[1].GCLK_S[6]	CELL[1].GCLK_S[7]

virtex2 CLK_S bel BUFGMUX attribute bits
Attribute	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]	BUFGMUX[4]	BUFGMUX[5]	BUFGMUX[6]	BUFGMUX[7]
INIT_OUT bit 0	MAIN[0][6]	MAIN[0][5]	TERM[0][12]	TERM[0][11]	MAIN[3][6]	MAIN[3][5]	TERM[3][12]	TERM[3][11]

Bels GLOBALSIG_BUFG

virtex2 CLK_S bel GLOBALSIG_BUFG pins
Pin	Direction	GLOBALSIG_BUFG[0]	GLOBALSIG_BUFG[1]

virtex2 CLK_S bel GLOBALSIG_BUFG attribute bits
Attribute	GLOBALSIG_BUFG[0]	GLOBALSIG_BUFG[1]
GWE_ENABLE	!TERM[0][6]	!TERM[3][6]

Bel wires

virtex2 CLK_S bel wires
Wire	Pins
CELL[1].GCLK_S[0]	BUFGMUX[0].O
CELL[1].GCLK_S[1]	BUFGMUX[1].O
CELL[1].GCLK_S[2]	BUFGMUX[2].O
CELL[1].GCLK_S[3]	BUFGMUX[3].O
CELL[1].GCLK_S[4]	BUFGMUX[4].O
CELL[1].GCLK_S[5]	BUFGMUX[5].O
CELL[1].GCLK_S[6]	BUFGMUX[6].O
CELL[1].GCLK_S[7]	BUFGMUX[7].O
CELL[1].IMUX_BUFG_CLK[0]	BUFGMUX[0].I0, BUFGMUX[1].I1
CELL[1].IMUX_BUFG_CLK[1]	BUFGMUX[1].I0, BUFGMUX[0].I1
CELL[1].IMUX_BUFG_CLK[2]	BUFGMUX[2].I0, BUFGMUX[3].I1
CELL[1].IMUX_BUFG_CLK[3]	BUFGMUX[3].I0, BUFGMUX[2].I1
CELL[1].IMUX_BUFG_CLK[4]	BUFGMUX[4].I0, BUFGMUX[5].I1
CELL[1].IMUX_BUFG_CLK[5]	BUFGMUX[5].I0, BUFGMUX[4].I1
CELL[1].IMUX_BUFG_CLK[6]	BUFGMUX[6].I0, BUFGMUX[7].I1
CELL[1].IMUX_BUFG_CLK[7]	BUFGMUX[7].I0, BUFGMUX[6].I1
CELL[1].IMUX_BUFG_SEL[0]	BUFGMUX[0].S
CELL[1].IMUX_BUFG_SEL[1]	BUFGMUX[1].S
CELL[1].IMUX_BUFG_SEL[2]	BUFGMUX[2].S
CELL[1].IMUX_BUFG_SEL[3]	BUFGMUX[3].S
CELL[1].IMUX_BUFG_SEL[4]	BUFGMUX[4].S
CELL[1].IMUX_BUFG_SEL[5]	BUFGMUX[5].S
CELL[1].IMUX_BUFG_SEL[6]	BUFGMUX[6].S
CELL[1].IMUX_BUFG_SEL[7]	BUFGMUX[7].S

Bitstream

virtex2 CLK_S rect MAIN
Bit	Frame
Bit	F3	F2	F1	F0
B79	-	-	-	-
B78	-	-	-	-
B77	-	-	-	-
B76	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[7] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[7] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 5
B75	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[7] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[7] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 0
B74	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[7] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[7] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 1
B73	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[7] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[7] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 2
B72	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[7] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[7] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 3
B71	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[7] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[7] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 4
B70	-	BUFGMUX[7]: !invert S	BUFGMUX[3]: !invert S	-
B69	-	-	-	-
B68	-	-	-	-
B67	-	-	-	-
B66	-	-	-	-
B65	-	-	-	-
B64	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[6] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[6] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 5
B63	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[6] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[6] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 0
B62	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[6] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[6] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 1
B61	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[6] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[6] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 2
B60	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[6] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[6] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 3
B59	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[6] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[6] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 4
B58	-	BUFGMUX[6]: !invert S	BUFGMUX[2]: !invert S	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[5] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[5] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 5
B51	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[5] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[5] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 0
B50	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[5] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[5] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 1
B49	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[5] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[5] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 2
B48	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[5] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[5] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 3
B47	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[5] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[5] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 4
B46	-	BUFGMUX[5]: !invert S	BUFGMUX[1]: !invert S	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[4] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[4] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 5
B39	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[4] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[4] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 0
B38	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[4] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[4] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 1
B37	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[4] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[4] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 2
B36	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[4] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[4] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 3
B35	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[4] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[4] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 4
B34	-	BUFGMUX[4]: !invert S	BUFGMUX[0]: !invert S	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	CLK_INT: mux CELL[0].OMUX_N10 bit 4	CLK_INT: mux CELL[0].OMUX_N11 bit 0	CLK_INT: mux CELL[1].OMUX_N11 bit 0	CLK_INT: mux CELL[1].OMUX_N10 bit 4
B27	CLK_INT: mux CELL[0].OMUX_N10 bit 0	CLK_INT: mux CELL[0].OMUX_N11 bit 1	CLK_INT: mux CELL[1].OMUX_N11 bit 1	CLK_INT: mux CELL[1].OMUX_N10 bit 0
B26	CLK_INT: mux CELL[0].OMUX_N10 bit 1	CLK_INT: mux CELL[0].OMUX_N11 bit 2	CLK_INT: mux CELL[1].OMUX_N11 bit 2	CLK_INT: mux CELL[1].OMUX_N10 bit 1
B25	CLK_INT: mux CELL[0].OMUX_N10 bit 2	CLK_INT: mux CELL[0].OMUX_N11 bit 3	CLK_INT: mux CELL[1].OMUX_N11 bit 3	CLK_INT: mux CELL[1].OMUX_N10 bit 2
B24	CLK_INT: mux CELL[0].OMUX_N10 bit 3	CLK_INT: mux CELL[0].OMUX_N11 bit 4	CLK_INT: mux CELL[1].OMUX_N11 bit 4	CLK_INT: mux CELL[1].OMUX_N10 bit 3
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	CLK_INT: mux CELL[0].OMUX_N12 bit 4	CLK_INT: mux CELL[0].OMUX_N15 bit 0	CLK_INT: mux CELL[1].OMUX_N15 bit 0	CLK_INT: mux CELL[1].OMUX_N12 bit 4
B17	CLK_INT: mux CELL[0].OMUX_N12 bit 0	CLK_INT: mux CELL[0].OMUX_N15 bit 1	CLK_INT: mux CELL[1].OMUX_N15 bit 1	CLK_INT: mux CELL[1].OMUX_N12 bit 0
B16	CLK_INT: mux CELL[0].OMUX_N12 bit 1	CLK_INT: mux CELL[0].OMUX_N15 bit 2	CLK_INT: mux CELL[1].OMUX_N15 bit 2	CLK_INT: mux CELL[1].OMUX_N12 bit 1
B15	CLK_INT: mux CELL[0].OMUX_N12 bit 2	CLK_INT: mux CELL[0].OMUX_N15 bit 3	CLK_INT: mux CELL[1].OMUX_N15 bit 3	CLK_INT: mux CELL[1].OMUX_N12 bit 2
B14	CLK_INT: mux CELL[0].OMUX_N12 bit 3	CLK_INT: mux CELL[0].OMUX_N15 bit 4	CLK_INT: mux CELL[1].OMUX_N15 bit 4	CLK_INT: mux CELL[1].OMUX_N12 bit 3
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[4] bit 3	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 3
B9	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[4] bit 2	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 2
B8	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[4] bit 1	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 0
B7	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[4] bit 0	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 1
B6	BUFGMUX[4]: INIT_OUT bit 0	-	-	BUFGMUX[0]: INIT_OUT bit 0
B5	BUFGMUX[5]: INIT_OUT bit 0	-	-	BUFGMUX[1]: INIT_OUT bit 0
B4	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[5] bit 0	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 1
B3	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[5] bit 1	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 0
B2	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[5] bit 2	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 2
B1	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[5] bit 3	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 3
B0	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[6] bit 3	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 3

virtex2 CLK_S rect TERM
Bit	Frame
Bit	F3	F2	F1	F0
B15	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[6] bit 2	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 2
B14	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[6] bit 1	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 0
B13	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[6] bit 0	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 1
B12	BUFGMUX[6]: INIT_OUT bit 0	-	-	BUFGMUX[2]: INIT_OUT bit 0
B11	BUFGMUX[7]: INIT_OUT bit 0	-	-	BUFGMUX[3]: INIT_OUT bit 0
B10	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[7] bit 0	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 1
B9	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[7] bit 1	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 0
B8	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[7] bit 2	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 2
B7	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[7] bit 3	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 3
B6	GLOBALSIG_BUFG[1]: ! GWE_ENABLE	-	-	GLOBALSIG_BUFG[0]: ! GWE_ENABLE
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

Tile CLK_N

Cells: 2

Switchbox CLK_INT

virtex2 CLK_N switchbox CLK_INT permanent buffers
Destination	Source
CELL[0].DCM_CLKPAD[0]	CELL[0].OUT_CLKPAD[0]
CELL[0].DCM_CLKPAD[1]	CELL[0].OUT_CLKPAD[1]
CELL[0].DCM_CLKPAD[2]	CELL[0].OUT_CLKPAD[2]
CELL[0].DCM_CLKPAD[3]	CELL[0].OUT_CLKPAD[3]
CELL[0].DCM_CLKPAD[4]	CELL[1].OUT_CLKPAD[0]
CELL[0].DCM_CLKPAD[5]	CELL[1].OUT_CLKPAD[1]
CELL[0].DCM_CLKPAD[6]	CELL[1].OUT_CLKPAD[2]
CELL[0].DCM_CLKPAD[7]	CELL[1].OUT_CLKPAD[3]
CELL[1].DCM_CLKPAD[0]	CELL[1].OUT_CLKPAD[0]
CELL[1].DCM_CLKPAD[1]	CELL[1].OUT_CLKPAD[1]
CELL[1].DCM_CLKPAD[2]	CELL[1].OUT_CLKPAD[2]
CELL[1].DCM_CLKPAD[3]	CELL[1].OUT_CLKPAD[3]
CELL[1].DCM_CLKPAD[4]	CELL[0].OUT_CLKPAD[0]
CELL[1].DCM_CLKPAD[5]	CELL[0].OUT_CLKPAD[1]
CELL[1].DCM_CLKPAD[6]	CELL[0].OUT_CLKPAD[2]
CELL[1].DCM_CLKPAD[7]	CELL[0].OUT_CLKPAD[3]

virtex2 CLK_N switchbox CLK_INT muxes OMUX_S0
Bits					Destination
MAIN[3][50]	MAIN[3][54]	MAIN[3][53]	MAIN[3][52]	MAIN[3][51]	CELL[0].OMUX_S0	-
MAIN[0][50]	MAIN[0][54]	MAIN[0][53]	MAIN[0][52]	MAIN[0][51]	-	CELL[1].OMUX_S0
					Source
0	0	0	0	0	off	off
0	0	0	0	1	CELL[1].GCLK_N[0]	CELL[1].GCLK_N[4]
0	0	0	1	0	CELL[1].GCLK_N[1]	CELL[1].GCLK_N[5]
0	0	1	0	0	CELL[1].GCLK_N[2]	CELL[1].GCLK_N[6]
0	1	0	0	0	CELL[1].GCLK_N[3]	CELL[1].GCLK_N[7]
1	0	0	0	1	CELL[1].GCLK_N[4]	CELL[1].GCLK_N[0]
1	0	0	1	0	CELL[1].GCLK_N[5]	CELL[1].GCLK_N[1]
1	0	1	0	0	CELL[1].GCLK_N[6]	CELL[1].GCLK_N[2]
1	1	0	0	0	CELL[1].GCLK_N[7]	CELL[1].GCLK_N[3]

virtex2 CLK_N switchbox CLK_INT muxes OMUX_S3
Bits					Destination
MAIN[2][54]	MAIN[2][53]	MAIN[2][52]	MAIN[2][51]	MAIN[2][50]	CELL[0].OMUX_S3	-
MAIN[1][54]	MAIN[1][53]	MAIN[1][52]	MAIN[1][51]	MAIN[1][50]	-	CELL[1].OMUX_S3
					Source
0	0	0	0	0	off	off
0	0	0	0	1	CELL[1].GCLK_N[0]	CELL[1].GCLK_N[4]
0	0	0	1	0	CELL[1].GCLK_N[1]	CELL[1].GCLK_N[5]
0	0	1	0	0	CELL[1].GCLK_N[2]	CELL[1].GCLK_N[6]
0	1	0	0	0	CELL[1].GCLK_N[3]	CELL[1].GCLK_N[7]
1	0	0	0	1	CELL[1].GCLK_N[4]	CELL[1].GCLK_N[0]
1	0	0	1	0	CELL[1].GCLK_N[5]	CELL[1].GCLK_N[1]
1	0	1	0	0	CELL[1].GCLK_N[6]	CELL[1].GCLK_N[2]
1	1	0	0	0	CELL[1].GCLK_N[7]	CELL[1].GCLK_N[3]

virtex2 CLK_N switchbox CLK_INT muxes OMUX_S4
Bits					Destination
MAIN[3][60]	MAIN[3][64]	MAIN[3][63]	MAIN[3][62]	MAIN[3][61]	CELL[0].OMUX_S4	-
MAIN[0][60]	MAIN[0][64]	MAIN[0][63]	MAIN[0][62]	MAIN[0][61]	-	CELL[1].OMUX_S4
					Source
0	0	0	0	0	off	off
0	0	0	0	1	CELL[1].GCLK_N[0]	CELL[1].GCLK_N[4]
0	0	0	1	0	CELL[1].GCLK_N[1]	CELL[1].GCLK_N[5]
0	0	1	0	0	CELL[1].GCLK_N[2]	CELL[1].GCLK_N[6]
0	1	0	0	0	CELL[1].GCLK_N[3]	CELL[1].GCLK_N[7]
1	0	0	0	1	CELL[1].GCLK_N[4]	CELL[1].GCLK_N[0]
1	0	0	1	0	CELL[1].GCLK_N[5]	CELL[1].GCLK_N[1]
1	0	1	0	0	CELL[1].GCLK_N[6]	CELL[1].GCLK_N[2]
1	1	0	0	0	CELL[1].GCLK_N[7]	CELL[1].GCLK_N[3]

virtex2 CLK_N switchbox CLK_INT muxes OMUX_S5
Bits					Destination
MAIN[2][64]	MAIN[2][63]	MAIN[2][62]	MAIN[2][61]	MAIN[2][60]	CELL[0].OMUX_S5	-
MAIN[1][64]	MAIN[1][63]	MAIN[1][62]	MAIN[1][61]	MAIN[1][60]	-	CELL[1].OMUX_S5
					Source
0	0	0	0	0	off	off
0	0	0	0	1	CELL[1].GCLK_N[0]	CELL[1].GCLK_N[4]
0	0	0	1	0	CELL[1].GCLK_N[1]	CELL[1].GCLK_N[5]
0	0	1	0	0	CELL[1].GCLK_N[2]	CELL[1].GCLK_N[6]
0	1	0	0	0	CELL[1].GCLK_N[3]	CELL[1].GCLK_N[7]
1	0	0	0	1	CELL[1].GCLK_N[4]	CELL[1].GCLK_N[0]
1	0	0	1	0	CELL[1].GCLK_N[5]	CELL[1].GCLK_N[1]
1	0	1	0	0	CELL[1].GCLK_N[6]	CELL[1].GCLK_N[2]
1	1	0	0	0	CELL[1].GCLK_N[7]	CELL[1].GCLK_N[3]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[0]
Bits						Destination
MAIN[0][2]	MAIN[0][7]	MAIN[0][6]	MAIN[0][5]	MAIN[0][4]	MAIN[0][3]	CELL[1].IMUX_BUFG_CLK_INT[0]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[0]
0	0	0	0	1	0	CELL[0].DBL_W2[1]
0	0	0	1	0	0	CELL[0].DBL_W2[2]
0	0	1	0	0	0	CELL[1].DBL_W0[0]
0	1	0	0	0	0	CELL[1].DBL_W0[1]
1	0	0	0	0	1	CELL[0].DBL_E0[0]
1	0	0	0	1	0	CELL[0].DBL_E0[1]
1	0	0	1	0	0	CELL[0].DBL_E0[2]
1	0	1	0	0	0	CELL[0].DBL_E1[0]
1	1	0	0	0	0	CELL[0].DBL_E1[1]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[1]
Bits						Destination
MAIN[0][14]	MAIN[0][19]	MAIN[0][18]	MAIN[0][17]	MAIN[0][16]	MAIN[0][15]	CELL[1].IMUX_BUFG_CLK_INT[1]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[3]
0	0	0	0	1	0	CELL[0].DBL_W2[4]
0	0	0	1	0	0	CELL[1].DBL_W0[2]
0	0	1	0	0	0	CELL[1].DBL_W0[3]
0	1	0	0	0	0	CELL[1].DBL_W0[4]
1	0	0	0	0	1	CELL[0].DBL_E0[3]
1	0	0	0	1	0	CELL[0].DBL_E0[4]
1	0	0	1	0	0	CELL[0].DBL_E1[2]
1	0	1	0	0	0	CELL[0].DBL_E1[3]
1	1	0	0	0	0	CELL[0].DBL_E1[4]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[2]
Bits						Destination
MAIN[0][26]	MAIN[0][31]	MAIN[0][30]	MAIN[0][29]	MAIN[0][28]	MAIN[0][27]	CELL[1].IMUX_BUFG_CLK_INT[2]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[5]
0	0	0	0	1	0	CELL[0].DBL_W2[6]
0	0	0	1	0	0	CELL[0].DBL_W2[7]
0	0	1	0	0	0	CELL[1].DBL_W0[5]
0	1	0	0	0	0	CELL[1].DBL_W0[6]
1	0	0	0	0	1	CELL[0].DBL_E0[5]
1	0	0	0	1	0	CELL[0].DBL_E0[6]
1	0	0	1	0	0	CELL[0].DBL_E0[7]
1	0	1	0	0	0	CELL[0].DBL_E1[5]
1	1	0	0	0	0	CELL[0].DBL_E1[6]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[3]
Bits						Destination
MAIN[0][38]	MAIN[0][43]	MAIN[0][42]	MAIN[0][41]	MAIN[0][40]	MAIN[0][39]	CELL[1].IMUX_BUFG_CLK_INT[3]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[8]
0	0	0	0	1	0	CELL[0].DBL_W2[9]
0	0	0	1	0	0	CELL[1].DBL_W0[7]
0	0	1	0	0	0	CELL[1].DBL_W0[8]
0	1	0	0	0	0	CELL[1].DBL_W0[9]
1	0	0	0	0	1	CELL[0].DBL_E0[8]
1	0	0	0	1	0	CELL[0].DBL_E0[9]
1	0	0	1	0	0	CELL[0].DBL_E1[7]
1	0	1	0	0	0	CELL[0].DBL_E1[8]
1	1	0	0	0	0	CELL[0].DBL_E1[9]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[4]
Bits						Destination
MAIN[3][2]	MAIN[3][7]	MAIN[3][6]	MAIN[3][5]	MAIN[3][4]	MAIN[3][3]	CELL[1].IMUX_BUFG_CLK_INT[4]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[0]
0	0	0	0	1	0	CELL[0].DBL_W2[1]
0	0	0	1	0	0	CELL[0].DBL_W2[2]
0	0	1	0	0	0	CELL[1].DBL_W0[0]
0	1	0	0	0	0	CELL[1].DBL_W0[1]
1	0	0	0	0	1	CELL[0].DBL_E0[0]
1	0	0	0	1	0	CELL[0].DBL_E0[1]
1	0	0	1	0	0	CELL[0].DBL_E0[2]
1	0	1	0	0	0	CELL[0].DBL_E1[0]
1	1	0	0	0	0	CELL[0].DBL_E1[1]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[5]
Bits						Destination
MAIN[3][14]	MAIN[3][19]	MAIN[3][18]	MAIN[3][17]	MAIN[3][16]	MAIN[3][15]	CELL[1].IMUX_BUFG_CLK_INT[5]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[3]
0	0	0	0	1	0	CELL[0].DBL_W2[4]
0	0	0	1	0	0	CELL[1].DBL_W0[2]
0	0	1	0	0	0	CELL[1].DBL_W0[3]
0	1	0	0	0	0	CELL[1].DBL_W0[4]
1	0	0	0	0	1	CELL[0].DBL_E0[3]
1	0	0	0	1	0	CELL[0].DBL_E0[4]
1	0	0	1	0	0	CELL[0].DBL_E1[2]
1	0	1	0	0	0	CELL[0].DBL_E1[3]
1	1	0	0	0	0	CELL[0].DBL_E1[4]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[6]
Bits						Destination
MAIN[3][26]	MAIN[3][31]	MAIN[3][30]	MAIN[3][29]	MAIN[3][28]	MAIN[3][27]	CELL[1].IMUX_BUFG_CLK_INT[6]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[5]
0	0	0	0	1	0	CELL[0].DBL_W2[6]
0	0	0	1	0	0	CELL[0].DBL_W2[7]
0	0	1	0	0	0	CELL[1].DBL_W0[5]
0	1	0	0	0	0	CELL[1].DBL_W0[6]
1	0	0	0	0	1	CELL[0].DBL_E0[5]
1	0	0	0	1	0	CELL[0].DBL_E0[6]
1	0	0	1	0	0	CELL[0].DBL_E0[7]
1	0	1	0	0	0	CELL[0].DBL_E1[5]
1	1	0	0	0	0	CELL[0].DBL_E1[6]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_CLK_INT[7]
Bits						Destination
MAIN[3][38]	MAIN[3][43]	MAIN[3][42]	MAIN[3][41]	MAIN[3][40]	MAIN[3][39]	CELL[1].IMUX_BUFG_CLK_INT[7]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[8]
0	0	0	0	1	0	CELL[0].DBL_W2[9]
0	0	0	1	0	0	CELL[1].DBL_W0[7]
0	0	1	0	0	0	CELL[1].DBL_W0[8]
0	1	0	0	0	0	CELL[1].DBL_W0[9]
1	0	0	0	0	1	CELL[0].DBL_E0[8]
1	0	0	0	1	0	CELL[0].DBL_E0[9]
1	0	0	1	0	0	CELL[0].DBL_E1[7]
1	0	1	0	0	0	CELL[0].DBL_E1[8]
1	1	0	0	0	0	CELL[0].DBL_E1[9]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_CLK[0]
Bits				Destination
MAIN[0][68]	MAIN[0][69]	MAIN[0][71]	MAIN[0][70]	CELL[1].IMUX_BUFG_CLK[0]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].DCM_BUS[0]
0	0	1	0	CELL[1].OUT_CLKPAD[0]
0	1	0	0	CELL[1].DCM_BUS[0]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[0]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_CLK[1]
Bits				Destination
MAIN[0][77]	MAIN[0][76]	MAIN[0][74]	MAIN[0][75]	CELL[1].IMUX_BUFG_CLK[1]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].DCM_BUS[1]
0	0	1	0	CELL[1].OUT_CLKPAD[1]
0	1	0	0	CELL[1].DCM_BUS[1]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[1]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_CLK[2]
Bits				Destination
MAIN[0][78]	MAIN[0][79]	TERM[0][1]	TERM[0][0]	CELL[1].IMUX_BUFG_CLK[2]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].DCM_BUS[2]
0	0	1	0	CELL[1].OUT_CLKPAD[2]
0	1	0	0	CELL[1].DCM_BUS[2]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[2]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_CLK[3]
Bits				Destination
TERM[0][7]	TERM[0][6]	TERM[0][4]	TERM[0][5]	CELL[1].IMUX_BUFG_CLK[3]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].DCM_BUS[3]
0	0	1	0	CELL[1].OUT_CLKPAD[3]
0	1	0	0	CELL[1].DCM_BUS[3]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[3]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_CLK[4]
Bits				Destination
MAIN[3][68]	MAIN[3][69]	MAIN[3][70]	MAIN[3][71]	CELL[1].IMUX_BUFG_CLK[4]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].OUT_CLKPAD[0]
0	0	1	0	CELL[0].DCM_BUS[4]
0	1	0	0	CELL[1].DCM_BUS[4]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[4]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_CLK[5]
Bits				Destination
MAIN[3][77]	MAIN[3][76]	MAIN[3][75]	MAIN[3][74]	CELL[1].IMUX_BUFG_CLK[5]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].OUT_CLKPAD[1]
0	0	1	0	CELL[0].DCM_BUS[5]
0	1	0	0	CELL[1].DCM_BUS[5]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[5]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_CLK[6]
Bits				Destination
MAIN[3][78]	MAIN[3][79]	TERM[3][0]	TERM[3][1]	CELL[1].IMUX_BUFG_CLK[6]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].OUT_CLKPAD[2]
0	0	1	0	CELL[0].DCM_BUS[6]
0	1	0	0	CELL[1].DCM_BUS[6]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[6]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_CLK[7]
Bits				Destination
TERM[3][7]	TERM[3][6]	TERM[3][5]	TERM[3][4]	CELL[1].IMUX_BUFG_CLK[7]
				Source
0	0	0	0	off
0	0	0	1	CELL[0].OUT_CLKPAD[3]
0	0	1	0	CELL[0].DCM_BUS[7]
0	1	0	0	CELL[1].DCM_BUS[7]
1	0	0	0	CELL[1].IMUX_BUFG_CLK_INT[7]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_SEL[0]
Bits						Destination
MAIN[1][7]	MAIN[1][6]	MAIN[1][5]	MAIN[1][4]	MAIN[1][3]	MAIN[1][2]	CELL[1].IMUX_BUFG_SEL[0]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[0]
0	0	0	0	1	0	CELL[0].DBL_W2[1]
0	0	0	1	0	0	CELL[0].DBL_W2[2]
0	0	1	0	0	0	CELL[1].DBL_W0[0]
0	1	0	0	0	0	CELL[1].DBL_W0[1]
1	0	0	0	0	1	CELL[0].DBL_E0[0]
1	0	0	0	1	0	CELL[0].DBL_E0[1]
1	0	0	1	0	0	CELL[0].DBL_E0[2]
1	0	1	0	0	0	CELL[0].DBL_E1[0]
1	1	0	0	0	0	CELL[0].DBL_E1[1]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_SEL[1]
Bits						Destination
MAIN[1][19]	MAIN[1][18]	MAIN[1][17]	MAIN[1][16]	MAIN[1][15]	MAIN[1][14]	CELL[1].IMUX_BUFG_SEL[1]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[3]
0	0	0	0	1	0	CELL[0].DBL_W2[4]
0	0	0	1	0	0	CELL[1].DBL_W0[2]
0	0	1	0	0	0	CELL[1].DBL_W0[3]
0	1	0	0	0	0	CELL[1].DBL_W0[4]
1	0	0	0	0	1	CELL[0].DBL_E0[3]
1	0	0	0	1	0	CELL[0].DBL_E0[4]
1	0	0	1	0	0	CELL[0].DBL_E1[2]
1	0	1	0	0	0	CELL[0].DBL_E1[3]
1	1	0	0	0	0	CELL[0].DBL_E1[4]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_SEL[2]
Bits						Destination
MAIN[1][31]	MAIN[1][30]	MAIN[1][29]	MAIN[1][28]	MAIN[1][27]	MAIN[1][26]	CELL[1].IMUX_BUFG_SEL[2]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[5]
0	0	0	0	1	0	CELL[0].DBL_W2[6]
0	0	0	1	0	0	CELL[0].DBL_W2[7]
0	0	1	0	0	0	CELL[1].DBL_W0[5]
0	1	0	0	0	0	CELL[1].DBL_W0[6]
1	0	0	0	0	1	CELL[0].DBL_E0[5]
1	0	0	0	1	0	CELL[0].DBL_E0[6]
1	0	0	1	0	0	CELL[0].DBL_E0[7]
1	0	1	0	0	0	CELL[0].DBL_E1[5]
1	1	0	0	0	0	CELL[0].DBL_E1[6]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_SEL[3]
Bits						Destination
MAIN[1][43]	MAIN[1][42]	MAIN[1][41]	MAIN[1][40]	MAIN[1][39]	MAIN[1][38]	CELL[1].IMUX_BUFG_SEL[3]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[8]
0	0	0	0	1	0	CELL[0].DBL_W2[9]
0	0	0	1	0	0	CELL[1].DBL_W0[7]
0	0	1	0	0	0	CELL[1].DBL_W0[8]
0	1	0	0	0	0	CELL[1].DBL_W0[9]
1	0	0	0	0	1	CELL[0].DBL_E0[8]
1	0	0	0	1	0	CELL[0].DBL_E0[9]
1	0	0	1	0	0	CELL[0].DBL_E1[7]
1	0	1	0	0	0	CELL[0].DBL_E1[8]
1	1	0	0	0	0	CELL[0].DBL_E1[9]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_SEL[4]
Bits						Destination
MAIN[2][7]	MAIN[2][6]	MAIN[2][5]	MAIN[2][4]	MAIN[2][3]	MAIN[2][2]	CELL[1].IMUX_BUFG_SEL[4]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[0]
0	0	0	0	1	0	CELL[0].DBL_W2[1]
0	0	0	1	0	0	CELL[0].DBL_W2[2]
0	0	1	0	0	0	CELL[1].DBL_W0[0]
0	1	0	0	0	0	CELL[1].DBL_W0[1]
1	0	0	0	0	1	CELL[0].DBL_E0[0]
1	0	0	0	1	0	CELL[0].DBL_E0[1]
1	0	0	1	0	0	CELL[0].DBL_E0[2]
1	0	1	0	0	0	CELL[0].DBL_E1[0]
1	1	0	0	0	0	CELL[0].DBL_E1[1]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_SEL[5]
Bits						Destination
MAIN[2][19]	MAIN[2][18]	MAIN[2][17]	MAIN[2][16]	MAIN[2][15]	MAIN[2][14]	CELL[1].IMUX_BUFG_SEL[5]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[3]
0	0	0	0	1	0	CELL[0].DBL_W2[4]
0	0	0	1	0	0	CELL[1].DBL_W0[2]
0	0	1	0	0	0	CELL[1].DBL_W0[3]
0	1	0	0	0	0	CELL[1].DBL_W0[4]
1	0	0	0	0	1	CELL[0].DBL_E0[3]
1	0	0	0	1	0	CELL[0].DBL_E0[4]
1	0	0	1	0	0	CELL[0].DBL_E1[2]
1	0	1	0	0	0	CELL[0].DBL_E1[3]
1	1	0	0	0	0	CELL[0].DBL_E1[4]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_SEL[6]
Bits						Destination
MAIN[2][31]	MAIN[2][30]	MAIN[2][29]	MAIN[2][28]	MAIN[2][27]	MAIN[2][26]	CELL[1].IMUX_BUFG_SEL[6]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[5]
0	0	0	0	1	0	CELL[0].DBL_W2[6]
0	0	0	1	0	0	CELL[0].DBL_W2[7]
0	0	1	0	0	0	CELL[1].DBL_W0[5]
0	1	0	0	0	0	CELL[1].DBL_W0[6]
1	0	0	0	0	1	CELL[0].DBL_E0[5]
1	0	0	0	1	0	CELL[0].DBL_E0[6]
1	0	0	1	0	0	CELL[0].DBL_E0[7]
1	0	1	0	0	0	CELL[0].DBL_E1[5]
1	1	0	0	0	0	CELL[0].DBL_E1[6]

virtex2 CLK_N switchbox CLK_INT muxes IMUX_BUFG_SEL[7]
Bits						Destination
MAIN[2][43]	MAIN[2][42]	MAIN[2][41]	MAIN[2][40]	MAIN[2][39]	MAIN[2][38]	CELL[1].IMUX_BUFG_SEL[7]
						Source
0	0	0	0	0	0	CELL[0].PULLUP
0	0	0	0	0	1	CELL[0].DBL_W2[8]
0	0	0	0	1	0	CELL[0].DBL_W2[9]
0	0	0	1	0	0	CELL[1].DBL_W0[7]
0	0	1	0	0	0	CELL[1].DBL_W0[8]
0	1	0	0	0	0	CELL[1].DBL_W0[9]
1	0	0	0	0	1	CELL[0].DBL_E0[8]
1	0	0	0	1	0	CELL[0].DBL_E0[9]
1	0	0	1	0	0	CELL[0].DBL_E1[7]
1	0	1	0	0	0	CELL[0].DBL_E1[8]
1	1	0	0	0	0	CELL[0].DBL_E1[9]

Bels BUFGMUX

virtex2 CLK_N bel BUFGMUX pins
Pin	Direction	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]	BUFGMUX[4]	BUFGMUX[5]	BUFGMUX[6]	BUFGMUX[7]
I0	in	CELL[1].IMUX_BUFG_CLK[0]	CELL[1].IMUX_BUFG_CLK[1]	CELL[1].IMUX_BUFG_CLK[2]	CELL[1].IMUX_BUFG_CLK[3]	CELL[1].IMUX_BUFG_CLK[4]	CELL[1].IMUX_BUFG_CLK[5]	CELL[1].IMUX_BUFG_CLK[6]	CELL[1].IMUX_BUFG_CLK[7]
I1	in	CELL[1].IMUX_BUFG_CLK[1]	CELL[1].IMUX_BUFG_CLK[0]	CELL[1].IMUX_BUFG_CLK[3]	CELL[1].IMUX_BUFG_CLK[2]	CELL[1].IMUX_BUFG_CLK[5]	CELL[1].IMUX_BUFG_CLK[4]	CELL[1].IMUX_BUFG_CLK[7]	CELL[1].IMUX_BUFG_CLK[6]
S	in	CELL[1].IMUX_BUFG_SEL[0] invert by !MAIN[1][8]	CELL[1].IMUX_BUFG_SEL[1] invert by !MAIN[1][20]	CELL[1].IMUX_BUFG_SEL[2] invert by !MAIN[1][32]	CELL[1].IMUX_BUFG_SEL[3] invert by !MAIN[1][44]	CELL[1].IMUX_BUFG_SEL[4] invert by !MAIN[2][8]	CELL[1].IMUX_BUFG_SEL[5] invert by !MAIN[2][20]	CELL[1].IMUX_BUFG_SEL[6] invert by !MAIN[2][32]	CELL[1].IMUX_BUFG_SEL[7] invert by !MAIN[2][44]
O	out	CELL[1].GCLK_N[0]	CELL[1].GCLK_N[1]	CELL[1].GCLK_N[2]	CELL[1].GCLK_N[3]	CELL[1].GCLK_N[4]	CELL[1].GCLK_N[5]	CELL[1].GCLK_N[6]	CELL[1].GCLK_N[7]

virtex2 CLK_N bel BUFGMUX attribute bits
Attribute	BUFGMUX[0]	BUFGMUX[1]	BUFGMUX[2]	BUFGMUX[3]	BUFGMUX[4]	BUFGMUX[5]	BUFGMUX[6]	BUFGMUX[7]
INIT_OUT bit 0	MAIN[0][72]	MAIN[0][73]	TERM[0][2]	TERM[0][3]	MAIN[3][72]	MAIN[3][73]	TERM[3][2]	TERM[3][3]

Bels GLOBALSIG_BUFG

virtex2 CLK_N bel GLOBALSIG_BUFG pins
Pin	Direction	GLOBALSIG_BUFG[0]	GLOBALSIG_BUFG[1]

virtex2 CLK_N bel GLOBALSIG_BUFG attribute bits
Attribute	GLOBALSIG_BUFG[0]	GLOBALSIG_BUFG[1]
GWE_ENABLE	!TERM[0][8]	!TERM[3][8]

Bel wires

virtex2 CLK_N bel wires
Wire	Pins
CELL[1].GCLK_N[0]	BUFGMUX[0].O
CELL[1].GCLK_N[1]	BUFGMUX[1].O
CELL[1].GCLK_N[2]	BUFGMUX[2].O
CELL[1].GCLK_N[3]	BUFGMUX[3].O
CELL[1].GCLK_N[4]	BUFGMUX[4].O
CELL[1].GCLK_N[5]	BUFGMUX[5].O
CELL[1].GCLK_N[6]	BUFGMUX[6].O
CELL[1].GCLK_N[7]	BUFGMUX[7].O
CELL[1].IMUX_BUFG_CLK[0]	BUFGMUX[0].I0, BUFGMUX[1].I1
CELL[1].IMUX_BUFG_CLK[1]	BUFGMUX[1].I0, BUFGMUX[0].I1
CELL[1].IMUX_BUFG_CLK[2]	BUFGMUX[2].I0, BUFGMUX[3].I1
CELL[1].IMUX_BUFG_CLK[3]	BUFGMUX[3].I0, BUFGMUX[2].I1
CELL[1].IMUX_BUFG_CLK[4]	BUFGMUX[4].I0, BUFGMUX[5].I1
CELL[1].IMUX_BUFG_CLK[5]	BUFGMUX[5].I0, BUFGMUX[4].I1
CELL[1].IMUX_BUFG_CLK[6]	BUFGMUX[6].I0, BUFGMUX[7].I1
CELL[1].IMUX_BUFG_CLK[7]	BUFGMUX[7].I0, BUFGMUX[6].I1
CELL[1].IMUX_BUFG_SEL[0]	BUFGMUX[0].S
CELL[1].IMUX_BUFG_SEL[1]	BUFGMUX[1].S
CELL[1].IMUX_BUFG_SEL[2]	BUFGMUX[2].S
CELL[1].IMUX_BUFG_SEL[3]	BUFGMUX[3].S
CELL[1].IMUX_BUFG_SEL[4]	BUFGMUX[4].S
CELL[1].IMUX_BUFG_SEL[5]	BUFGMUX[5].S
CELL[1].IMUX_BUFG_SEL[6]	BUFGMUX[6].S
CELL[1].IMUX_BUFG_SEL[7]	BUFGMUX[7].S

Bitstream

virtex2 CLK_N rect MAIN
Bit	Frame
Bit	F3	F2	F1	F0
B79	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[6] bit 2	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 2
B78	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[6] bit 3	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 3
B77	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[5] bit 3	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 3
B76	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[5] bit 2	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 2
B75	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[5] bit 1	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 0
B74	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[5] bit 0	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[1] bit 1
B73	BUFGMUX[5]: INIT_OUT bit 0	-	-	BUFGMUX[1]: INIT_OUT bit 0
B72	BUFGMUX[4]: INIT_OUT bit 0	-	-	BUFGMUX[0]: INIT_OUT bit 0
B71	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[4] bit 0	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 1
B70	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[4] bit 1	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 0
B69	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[4] bit 2	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 2
B68	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[4] bit 3	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[0] bit 3
B67	-	-	-	-
B66	-	-	-	-
B65	-	-	-	-
B64	CLK_INT: mux CELL[0].OMUX_S4 bit 3	CLK_INT: mux CELL[0].OMUX_S5 bit 4	CLK_INT: mux CELL[1].OMUX_S5 bit 4	CLK_INT: mux CELL[1].OMUX_S4 bit 3
B63	CLK_INT: mux CELL[0].OMUX_S4 bit 2	CLK_INT: mux CELL[0].OMUX_S5 bit 3	CLK_INT: mux CELL[1].OMUX_S5 bit 3	CLK_INT: mux CELL[1].OMUX_S4 bit 2
B62	CLK_INT: mux CELL[0].OMUX_S4 bit 1	CLK_INT: mux CELL[0].OMUX_S5 bit 2	CLK_INT: mux CELL[1].OMUX_S5 bit 2	CLK_INT: mux CELL[1].OMUX_S4 bit 1
B61	CLK_INT: mux CELL[0].OMUX_S4 bit 0	CLK_INT: mux CELL[0].OMUX_S5 bit 1	CLK_INT: mux CELL[1].OMUX_S5 bit 1	CLK_INT: mux CELL[1].OMUX_S4 bit 0
B60	CLK_INT: mux CELL[0].OMUX_S4 bit 4	CLK_INT: mux CELL[0].OMUX_S5 bit 0	CLK_INT: mux CELL[1].OMUX_S5 bit 0	CLK_INT: mux CELL[1].OMUX_S4 bit 4
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	CLK_INT: mux CELL[0].OMUX_S0 bit 3	CLK_INT: mux CELL[0].OMUX_S3 bit 4	CLK_INT: mux CELL[1].OMUX_S3 bit 4	CLK_INT: mux CELL[1].OMUX_S0 bit 3
B53	CLK_INT: mux CELL[0].OMUX_S0 bit 2	CLK_INT: mux CELL[0].OMUX_S3 bit 3	CLK_INT: mux CELL[1].OMUX_S3 bit 3	CLK_INT: mux CELL[1].OMUX_S0 bit 2
B52	CLK_INT: mux CELL[0].OMUX_S0 bit 1	CLK_INT: mux CELL[0].OMUX_S3 bit 2	CLK_INT: mux CELL[1].OMUX_S3 bit 2	CLK_INT: mux CELL[1].OMUX_S0 bit 1
B51	CLK_INT: mux CELL[0].OMUX_S0 bit 0	CLK_INT: mux CELL[0].OMUX_S3 bit 1	CLK_INT: mux CELL[1].OMUX_S3 bit 1	CLK_INT: mux CELL[1].OMUX_S0 bit 0
B50	CLK_INT: mux CELL[0].OMUX_S0 bit 4	CLK_INT: mux CELL[0].OMUX_S3 bit 0	CLK_INT: mux CELL[1].OMUX_S3 bit 0	CLK_INT: mux CELL[1].OMUX_S0 bit 4
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	BUFGMUX[7]: !invert S	BUFGMUX[3]: !invert S	-
B43	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[7] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[7] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 4
B42	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[7] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[7] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 3
B41	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[7] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[7] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 2
B40	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[7] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[7] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 1
B39	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[7] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[7] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 0
B38	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[7] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[7] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[3] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[3] bit 5
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	BUFGMUX[6]: !invert S	BUFGMUX[2]: !invert S	-
B31	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[6] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[6] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 4
B30	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[6] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[6] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 3
B29	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[6] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[6] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 2
B28	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[6] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[6] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 1
B27	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[6] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[6] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 0
B26	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[6] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[6] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[2] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[2] bit 5
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	BUFGMUX[5]: !invert S	BUFGMUX[1]: !invert S	-
B19	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[5] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[5] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 4
B18	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[5] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[5] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 3
B17	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[5] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[5] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 2
B16	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[5] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[5] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 1
B15	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[5] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[5] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 0
B14	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[5] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[5] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[1] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[1] bit 5
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	BUFGMUX[4]: !invert S	BUFGMUX[0]: !invert S	-
B7	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[4] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[4] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 4
B6	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[4] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[4] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 4	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 3
B5	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[4] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[4] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 3	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 2
B4	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[4] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[4] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 2	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 1
B3	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[4] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[4] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 1	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 0
B2	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[4] bit 5	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[4] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_SEL[0] bit 0	CLK_INT: mux CELL[1].IMUX_BUFG_CLK_INT[0] bit 5
B1	-	-	-	-
B0	-	-	-	-

virtex2 CLK_N rect TERM
Bit	Frame
Bit	F3	F2	F1	F0
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	GLOBALSIG_BUFG[1]: ! GWE_ENABLE	-	-	GLOBALSIG_BUFG[0]: ! GWE_ENABLE
B7	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[7] bit 3	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 3
B6	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[7] bit 2	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 2
B5	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[7] bit 1	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 0
B4	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[7] bit 0	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[3] bit 1
B3	BUFGMUX[7]: INIT_OUT bit 0	-	-	BUFGMUX[3]: INIT_OUT bit 0
B2	BUFGMUX[6]: INIT_OUT bit 0	-	-	BUFGMUX[2]: INIT_OUT bit 0
B1	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[6] bit 0	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 1
B0	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[6] bit 1	-	-	CLK_INT: mux CELL[1].IMUX_BUFG_CLK[2] bit 0

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