Digital Clock Managers
TODO: reverse, document
DCM.V2
Bit | Frame | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
11 | - | - | - | - | - | - | - | DCM:EN_DUMMY_OSC[2] |
10 | - | - | - | - | - | - | - | DCM:ZD2_BY1 |
9 | - | - | - | - | - | - | DCM:EN_OSC_COARSE | DCM:EN_DUMMY_OSC_OR_NON_STOP |
8 | - | - | - | - | - | - | - | - |
7 | - | - | - | - | - | - | - | DCM:EN_DUMMY_OSC[1] |
6 | - | - | - | - | - | - | - | DCM:EN_DUMMY_OSC[0] |
5 | - | - | - | - | - | - | - | - |
4 | - | - | - | - | - | - | - | - |
3 | - | - | - | - | - | - | - | - |
2 | - | - | - | - | - | - | - | - |
1 | - | - | - | - | - | - | - | - |
0 | - | - | - | - | - | - | - | - |
DCM:CLKDV_COUNT_FALL | 0.0.43 | 0.0.42 | 0.0.41 | 0.0.40 |
---|---|---|---|---|
DCM:CLKDV_COUNT_FALL_2 | 0.0.47 | 0.0.46 | 0.0.45 | 0.0.44 |
DCM:CLKDV_COUNT_MAX | 0.0.39 | 0.0.38 | 0.0.37 | 0.0.36 |
DCM:DESKEW_ADJUST | 0.3.4 | 0.3.3 | 0.3.2 | 0.3.1 |
DCM:DUTY_CYCLE_CORRECTION | 0.0.35 | 0.0.34 | 0.0.33 | 0.0.32 |
non-inverted | [3] | [2] | [1] | [0] |
DCM:CLKDV_MODE | 0.0.52 |
---|---|
HALF | 0 |
INT | 1 |
DCM:CLKDV_PHASE_FALL | 0.0.51 | 0.0.50 |
---|---|---|
DCM:CLKDV_PHASE_RISE | 0.0.49 | 0.0.48 |
DCM:VBG_PD | 0.3.12 | 0.3.11 |
non-inverted | [1] | [0] |
DCM:CLKFB_IOB | 0.3.6 |
---|---|
DCM:CLKIN_DIVIDE_BY_2 | 0.3.0 |
DCM:CLKIN_IOB | 0.3.5 |
DCM:DFS_ENABLE | 0.0.16 |
DCM:DFS_FEEDBACK | 0.3.43 |
DCM:DLL_ENABLE | 0.0.17 |
DCM:DSS_ENABLE | 0.0.20 |
DCM:ENABLE.CLK0 | 0.3.49 |
DCM:ENABLE.CLK180 | 0.3.51 |
DCM:ENABLE.CLK270 | 0.3.52 |
DCM:ENABLE.CLK2X | 0.3.53 |
DCM:ENABLE.CLK2X180 | 0.3.54 |
DCM:ENABLE.CLK90 | 0.3.50 |
DCM:ENABLE.CLKDV | 0.3.55 |
DCM:ENABLE.CLKFB | 0.0.18 |
DCM:ENABLE.CLKFX | 0.3.57 |
DCM:ENABLE.CLKFX180 | 0.3.56 |
DCM:ENABLE.CONCUR | 0.3.58 |
DCM:EN_DUMMY_OSC_OR_NON_STOP | 1.7.9 |
DCM:EN_OSC_COARSE | 1.6.9 |
DCM:NON_STOP | 0.3.15 |
DCM:PHASE_SHIFT_NEGATIVE | 0.0.21 |
DCM:PL_CENTERED | 0.3.47 |
DCM:PS_CENTERED | 0.0.57 |
DCM:PS_ENABLE | 0.0.19 |
DCM:STARTUP_WAIT | 0.3.59 |
DCM:STATUS1 | 0.0.60 |
DCM:STATUS7 | 0.0.59 |
DCM:TEST_ENABLE | 0.3.79 |
DCM:ZD2_BY1 | 1.7.10 |
non-inverted | [0] |
DCM:CLKFX_DIVIDE | 0.3.27 | 0.3.26 | 0.3.25 | 0.3.24 | 0.3.23 | 0.3.22 | 0.3.21 | 0.3.20 | 0.3.19 | 0.3.18 | 0.3.17 | 0.3.16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|
DCM:CLKFX_MULTIPLY | 0.3.39 | 0.3.38 | 0.3.37 | 0.3.36 | 0.3.35 | 0.3.34 | 0.3.33 | 0.3.32 | 0.3.31 | 0.3.30 | 0.3.29 | 0.3.28 |
non-inverted | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
DCM:CLK_FEEDBACK | 0.0.55 |
---|---|
1X | 0 |
2X | 1 |
DCM:COIN_WINDOW | 0.3.14 | 0.3.13 |
---|---|---|
DCM:SEL_PL_DLY | 0.3.46 | 0.3.45 |
0 | 0 | 0 |
1 | 0 | 1 |
2 | 1 | 0 |
3 | 1 | 1 |
DCM:COM | 0.3.15 | 0.3.14 | 0.3.13 | 0.3.12 | 0.3.11 | 0.3.10 | 0.3.9 | 0.3.8 | 0.3.7 | 0.3.6 | 0.3.5 | 0.3.4 | 0.3.3 | 0.3.2 | 0.3.1 | 0.3.0 | 0.0.79 | 0.0.78 | 0.0.77 | 0.0.76 | 0.0.75 | 0.0.74 | 0.0.73 | 0.0.72 | 0.0.71 | 0.0.70 | 0.0.69 | 0.0.68 | 0.0.67 | 0.0.66 | 0.0.65 | 0.0.64 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DCM:DFS | 0.3.47 | 0.3.46 | 0.3.45 | 0.3.44 | 0.3.43 | 0.3.42 | 0.3.41 | 0.3.40 | 0.3.39 | 0.3.38 | 0.3.37 | 0.3.36 | 0.3.35 | 0.3.34 | 0.3.33 | 0.3.32 | 0.3.31 | 0.3.30 | 0.3.29 | 0.3.28 | 0.3.27 | 0.3.26 | 0.3.25 | 0.3.24 | 0.3.23 | 0.3.22 | 0.3.21 | 0.3.20 | 0.3.19 | 0.3.18 | 0.3.17 | 0.3.16 |
DCM:DLLC | 0.0.63 | 0.0.62 | 0.0.61 | 0.0.60 | 0.0.59 | 0.0.58 | 0.0.57 | 0.0.56 | 0.0.55 | 0.0.54 | 0.0.53 | 0.0.52 | 0.0.51 | 0.0.50 | 0.0.49 | 0.0.48 | 0.0.47 | 0.0.46 | 0.0.45 | 0.0.44 | 0.0.43 | 0.0.42 | 0.0.41 | 0.0.40 | 0.0.39 | 0.0.38 | 0.0.37 | 0.0.36 | 0.0.35 | 0.0.34 | 0.0.33 | 0.0.32 |
DCM:DLLS | 0.0.31 | 0.0.30 | 0.0.29 | 0.0.28 | 0.0.27 | 0.0.26 | 0.0.25 | 0.0.24 | 0.0.23 | 0.0.22 | 0.0.21 | 0.0.20 | 0.0.19 | 0.0.18 | 0.0.17 | 0.0.16 | 0.0.15 | 0.0.14 | 0.0.13 | 0.0.12 | 0.0.11 | 0.0.10 | 0.0.9 | 0.0.8 | 0.0.7 | 0.0.6 | 0.0.5 | 0.0.4 | 0.0.3 | 0.0.2 | 0.0.1 | 0.0.0 |
DCM:MISC | 0.3.79 | 0.3.78 | 0.3.77 | 0.3.76 | 0.3.75 | 0.3.74 | 0.3.73 | 0.3.72 | 0.3.71 | 0.3.70 | 0.3.69 | 0.3.68 | 0.3.67 | 0.3.66 | 0.3.65 | 0.3.64 | 0.3.63 | 0.3.62 | 0.3.61 | 0.3.60 | 0.3.59 | 0.3.58 | 0.3.57 | 0.3.56 | 0.3.55 | 0.3.54 | 0.3.53 | 0.3.52 | 0.3.51 | 0.3.50 | 0.3.49 | 0.3.48 |
non-inverted | [31] | [30] | [29] | [28] | [27] | [26] | [25] | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
DCM:DFS_FREQUENCY_MODE | 0.3.44 |
---|---|
DCM:DLL_FREQUENCY_MODE | 0.0.56 |
LOW | 0 |
HIGH | 1 |
DCM:DSS_MODE | 0.0.31 | 0.0.30 |
---|---|---|
SPREAD_2 | 0 | 0 |
SPREAD_4 | 0 | 1 |
SPREAD_6 | 1 | 0 |
SPREAD_8 | 1 | 1 |
DCM:EN_DUMMY_OSC | 1.7.11 | 1.7.7 | 1.7.6 |
---|---|---|---|
DCM:VBG_SEL | 0.3.10 | 0.3.9 | 0.3.8 |
non-inverted | [2] | [1] | [0] |
DCM:FACTORY_JF1 | 0.0.15 | 0.0.14 | 0.0.13 | 0.0.12 | 0.0.11 | 0.0.10 | 0.0.9 | 0.0.8 |
---|---|---|---|---|---|---|---|---|
DCM:FACTORY_JF2 | 0.0.7 | 0.0.6 | 0.0.5 | 0.0.4 | 0.0.3 | 0.0.2 | 0.0.1 | 0.0.0 |
DCM:PHASE_SHIFT | 0.0.29 | 0.0.28 | 0.0.27 | 0.0.26 | 0.0.25 | 0.0.24 | 0.0.23 | 0.0.22 |
non-inverted | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
DCM:INV.CTLGO | 0.3.71 |
---|---|
DCM:INV.CTLMODE | 0.3.72 |
DCM:INV.CTLOSC1 | 0.3.70 |
DCM:INV.CTLOSC2 | 0.3.69 |
DCM:INV.CTLSEL0 | 0.3.66 |
DCM:INV.CTLSEL1 | 0.3.67 |
DCM:INV.CTLSEL2 | 0.3.68 |
DCM:INV.DSSEN | 0.3.61 |
DCM:INV.FREEZEDFS | 0.3.74 |
DCM:INV.FREEZEDLL | 0.3.73 |
DCM:INV.PSEN | 0.3.63 |
DCM:INV.PSINCDEC | 0.3.64 |
DCM:INV.RST | 0.3.65 |
DCM:INV.STSADRS0 | 0.3.75 |
DCM:INV.STSADRS1 | 0.3.76 |
DCM:INV.STSADRS2 | 0.3.77 |
DCM:INV.STSADRS3 | 0.3.78 |
inverted | ~[0] |
DCM:PS_MODE | 0.0.58 |
---|---|
CLKFB | 0 |
CLKIN | 1 |
DCM:TEST_OSC | 0.0.54 | 0.0.53 |
---|---|---|
90 | 0 | 0 |
180 | 0 | 1 |
270 | 1 | 0 |
360 | 1 | 1 |
DCM.V2P
Bit | Frame | |||||||
---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
11 | - | - | - | - | - | - | - | DCM:EN_DUMMY_OSC[2] |
10 | - | - | - | - | DCM:RESET_PS_SEL | - | - | DCM:ZD2_BY1 |
9 | - | - | - | - | - | - | DCM:EN_OSC_COARSE | DCM:EN_DUMMY_OSC_OR_NON_STOP |
8 | - | - | - | - | - | - | - | DCM:ZD1_BY1 |
7 | - | - | - | - | - | - | - | DCM:EN_DUMMY_OSC[1] |
6 | - | - | - | - | - | - | - | DCM:EN_DUMMY_OSC[0] |
5 | - | - | - | - | - | - | - | - |
4 | - | - | - | - | - | - | - | - |
3 | - | - | - | - | - | - | - | - |
2 | - | - | - | - | - | - | - | - |
1 | - | - | - | - | - | - | - | - |
0 | - | - | - | - | - | - | - | - |
DCM:CLKDV_COUNT_FALL | 0.0.43 | 0.0.42 | 0.0.41 | 0.0.40 |
---|---|---|---|---|
DCM:CLKDV_COUNT_FALL_2 | 0.0.47 | 0.0.46 | 0.0.45 | 0.0.44 |
DCM:CLKDV_COUNT_MAX | 0.0.39 | 0.0.38 | 0.0.37 | 0.0.36 |
DCM:DESKEW_ADJUST | 0.3.4 | 0.3.3 | 0.3.2 | 0.3.1 |
DCM:DUTY_CYCLE_CORRECTION | 0.0.35 | 0.0.34 | 0.0.33 | 0.0.32 |
non-inverted | [3] | [2] | [1] | [0] |
DCM:CLKDV_MODE | 0.0.52 |
---|---|
HALF | 0 |
INT | 1 |
DCM:CLKDV_PHASE_FALL | 0.0.51 | 0.0.50 |
---|---|---|
DCM:CLKDV_PHASE_RISE | 0.0.49 | 0.0.48 |
DCM:VBG_PD | 0.3.12 | 0.3.11 |
non-inverted | [1] | [0] |
DCM:CLKFB_IOB | 0.3.6 |
---|---|
DCM:CLKIN_DIVIDE_BY_2 | 0.3.0 |
DCM:CLKIN_IOB | 0.3.5 |
DCM:DFS_ENABLE | 0.0.16 |
DCM:DFS_FEEDBACK | 0.3.43 |
DCM:DLL_ENABLE | 0.0.17 |
DCM:DSS_ENABLE | 0.0.20 |
DCM:ENABLE.CLK0 | 0.3.49 |
DCM:ENABLE.CLK180 | 0.3.51 |
DCM:ENABLE.CLK270 | 0.3.52 |
DCM:ENABLE.CLK2X | 0.3.53 |
DCM:ENABLE.CLK2X180 | 0.3.54 |
DCM:ENABLE.CLK90 | 0.3.50 |
DCM:ENABLE.CLKDV | 0.3.55 |
DCM:ENABLE.CLKFB | 0.0.18 |
DCM:ENABLE.CLKFX | 0.3.57 |
DCM:ENABLE.CLKFX180 | 0.3.56 |
DCM:ENABLE.CONCUR | 0.3.58 |
DCM:EN_DUMMY_OSC_OR_NON_STOP | 1.7.9 |
DCM:EN_OSC_COARSE | 1.6.9 |
DCM:NON_STOP | 0.3.15 |
DCM:PHASE_SHIFT_NEGATIVE | 0.0.21 |
DCM:PL_CENTERED | 0.3.47 |
DCM:PS_CENTERED | 0.0.57 |
DCM:PS_ENABLE | 0.0.19 |
DCM:RESET_PS_SEL | 1.4.10 |
DCM:STARTUP_WAIT | 0.3.59 |
DCM:STATUS1 | 0.0.60 |
DCM:STATUS7 | 0.0.59 |
DCM:TEST_ENABLE | 0.3.79 |
DCM:ZD1_BY1 | 1.7.8 |
DCM:ZD2_BY1 | 1.7.10 |
non-inverted | [0] |
DCM:CLKFX_DIVIDE | 0.3.27 | 0.3.26 | 0.3.25 | 0.3.24 | 0.3.23 | 0.3.22 | 0.3.21 | 0.3.20 | 0.3.19 | 0.3.18 | 0.3.17 | 0.3.16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|
DCM:CLKFX_MULTIPLY | 0.3.39 | 0.3.38 | 0.3.37 | 0.3.36 | 0.3.35 | 0.3.34 | 0.3.33 | 0.3.32 | 0.3.31 | 0.3.30 | 0.3.29 | 0.3.28 |
non-inverted | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
DCM:CLK_FEEDBACK | 0.0.55 |
---|---|
1X | 0 |
2X | 1 |
DCM:COIN_WINDOW | 0.3.14 | 0.3.13 |
---|---|---|
DCM:SEL_PL_DLY | 0.3.46 | 0.3.45 |
0 | 0 | 0 |
1 | 0 | 1 |
2 | 1 | 0 |
3 | 1 | 1 |
DCM:COM | 0.3.15 | 0.3.14 | 0.3.13 | 0.3.12 | 0.3.11 | 0.3.10 | 0.3.9 | 0.3.8 | 0.3.7 | 0.3.6 | 0.3.5 | 0.3.4 | 0.3.3 | 0.3.2 | 0.3.1 | 0.3.0 | 0.0.79 | 0.0.78 | 0.0.77 | 0.0.76 | 0.0.75 | 0.0.74 | 0.0.73 | 0.0.72 | 0.0.71 | 0.0.70 | 0.0.69 | 0.0.68 | 0.0.67 | 0.0.66 | 0.0.65 | 0.0.64 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DCM:DFS | 0.3.47 | 0.3.46 | 0.3.45 | 0.3.44 | 0.3.43 | 0.3.42 | 0.3.41 | 0.3.40 | 0.3.39 | 0.3.38 | 0.3.37 | 0.3.36 | 0.3.35 | 0.3.34 | 0.3.33 | 0.3.32 | 0.3.31 | 0.3.30 | 0.3.29 | 0.3.28 | 0.3.27 | 0.3.26 | 0.3.25 | 0.3.24 | 0.3.23 | 0.3.22 | 0.3.21 | 0.3.20 | 0.3.19 | 0.3.18 | 0.3.17 | 0.3.16 |
DCM:DLLC | 0.0.63 | 0.0.62 | 0.0.61 | 0.0.60 | 0.0.59 | 0.0.58 | 0.0.57 | 0.0.56 | 0.0.55 | 0.0.54 | 0.0.53 | 0.0.52 | 0.0.51 | 0.0.50 | 0.0.49 | 0.0.48 | 0.0.47 | 0.0.46 | 0.0.45 | 0.0.44 | 0.0.43 | 0.0.42 | 0.0.41 | 0.0.40 | 0.0.39 | 0.0.38 | 0.0.37 | 0.0.36 | 0.0.35 | 0.0.34 | 0.0.33 | 0.0.32 |
DCM:DLLS | 0.0.31 | 0.0.30 | 0.0.29 | 0.0.28 | 0.0.27 | 0.0.26 | 0.0.25 | 0.0.24 | 0.0.23 | 0.0.22 | 0.0.21 | 0.0.20 | 0.0.19 | 0.0.18 | 0.0.17 | 0.0.16 | 0.0.15 | 0.0.14 | 0.0.13 | 0.0.12 | 0.0.11 | 0.0.10 | 0.0.9 | 0.0.8 | 0.0.7 | 0.0.6 | 0.0.5 | 0.0.4 | 0.0.3 | 0.0.2 | 0.0.1 | 0.0.0 |
DCM:MISC | 0.3.79 | 0.3.78 | 0.3.77 | 0.3.76 | 0.3.75 | 0.3.74 | 0.3.73 | 0.3.72 | 0.3.71 | 0.3.70 | 0.3.69 | 0.3.68 | 0.3.67 | 0.3.66 | 0.3.65 | 0.3.64 | 0.3.63 | 0.3.62 | 0.3.61 | 0.3.60 | 0.3.59 | 0.3.58 | 0.3.57 | 0.3.56 | 0.3.55 | 0.3.54 | 0.3.53 | 0.3.52 | 0.3.51 | 0.3.50 | 0.3.49 | 0.3.48 |
non-inverted | [31] | [30] | [29] | [28] | [27] | [26] | [25] | [24] | [23] | [22] | [21] | [20] | [19] | [18] | [17] | [16] | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
DCM:DFS_FREQUENCY_MODE | 0.3.44 |
---|---|
DCM:DLL_FREQUENCY_MODE | 0.0.56 |
LOW | 0 |
HIGH | 1 |
DCM:DSS_MODE | 0.0.31 | 0.0.30 |
---|---|---|
SPREAD_2 | 0 | 0 |
SPREAD_4 | 0 | 1 |
SPREAD_6 | 1 | 0 |
SPREAD_8 | 1 | 1 |
DCM:EN_DUMMY_OSC | 1.7.11 | 1.7.7 | 1.7.6 |
---|---|---|---|
DCM:VBG_SEL | 0.3.10 | 0.3.9 | 0.3.8 |
non-inverted | [2] | [1] | [0] |
DCM:FACTORY_JF1 | 0.0.15 | 0.0.14 | 0.0.13 | 0.0.12 | 0.0.11 | 0.0.10 | 0.0.9 | 0.0.8 |
---|---|---|---|---|---|---|---|---|
DCM:FACTORY_JF2 | 0.0.7 | 0.0.6 | 0.0.5 | 0.0.4 | 0.0.3 | 0.0.2 | 0.0.1 | 0.0.0 |
DCM:PHASE_SHIFT | 0.0.29 | 0.0.28 | 0.0.27 | 0.0.26 | 0.0.25 | 0.0.24 | 0.0.23 | 0.0.22 |
non-inverted | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
DCM:INV.CTLGO | 0.3.71 |
---|---|
DCM:INV.CTLMODE | 0.3.72 |
DCM:INV.CTLOSC1 | 0.3.70 |
DCM:INV.CTLOSC2 | 0.3.69 |
DCM:INV.CTLSEL0 | 0.3.66 |
DCM:INV.CTLSEL1 | 0.3.67 |
DCM:INV.CTLSEL2 | 0.3.68 |
DCM:INV.DSSEN | 0.3.61 |
DCM:INV.FREEZEDFS | 0.3.74 |
DCM:INV.FREEZEDLL | 0.3.73 |
DCM:INV.PSEN | 0.3.63 |
DCM:INV.PSINCDEC | 0.3.64 |
DCM:INV.RST | 0.3.65 |
DCM:INV.STSADRS0 | 0.3.75 |
DCM:INV.STSADRS1 | 0.3.76 |
DCM:INV.STSADRS2 | 0.3.77 |
DCM:INV.STSADRS3 | 0.3.78 |
DCM:INV.STSADRS4 | 0.3.60 |
inverted | ~[0] |
DCM:PS_MODE | 0.0.58 |
---|---|
CLKFB | 0 |
CLKIN | 1 |
DCM:TEST_OSC | 0.0.54 | 0.0.53 |
---|---|---|
90 | 0 | 0 |
180 | 0 | 1 |
270 | 1 | 0 |
360 | 1 | 1 |
Device data
Device | DCM:DESKEW_ADJUST | DCM:VBG_PD | DCM:VBG_SEL | ||||||
---|---|---|---|---|---|---|---|---|---|
[3] | [2] | [1] | [0] | [1] | [0] | [2] | [1] | [0] | |
xc2v40 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
xc2v80 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 |
xc2v250 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 |
xc2v500 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 |
xc2v1000 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
xq2v1000 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
xqr2v1000 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
xc2v1500 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
xc2v2000 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
xc2v3000 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
xq2v3000 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
xqr2v3000 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
xc2v4000 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
xc2v6000 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
xq2v6000 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
xqr2v6000 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
xc2v8000 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 |
xc2vp2 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 |
xc2vp4 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 |
xc2vp7 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 |
xc2vp20 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 |
xc2vp30 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
xc2vp40 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
xq2vp40 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
xc2vp50 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
xc2vp70 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
xq2vp70 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
xc2vp100 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
xc2vpx20 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 |
xc2vpx70 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |