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Digital Clock Managers

TODO: reverse, document

Tile DCM_V2

Cells: 1

Bels DCM

virtex2 DCM_V2 bel DCM pins
PinDirectionDCM
CLKINinIMUX_DCM_CLK_OPTINV[1]
CLKFBinIMUX_DCM_CLK_OPTINV[0]
RSTinIMUX_G3_DATA[0] invert by !MAIN[3][65]
PSCLKinIMUX_DCM_CLK_OPTINV[2]
PSENinIMUX_G1_DATA[0] invert by !MAIN[3][63]
PSINCDECinIMUX_G2_DATA[0] invert by !MAIN[3][64]
STSADRS[0]inIMUX_G3_DATA[1] invert by !MAIN[3][75]
STSADRS[1]inIMUX_G3_DATA[2] invert by !MAIN[3][76]
STSADRS[2]inIMUX_G3_DATA[3] invert by !MAIN[3][77]
STSADRS[3]inIMUX_G3_DATA[4] invert by !MAIN[3][78]
FREEZEDLLinIMUX_G2_DATA[2] invert by !MAIN[3][73]
FREEZEDFSinIMUX_G2_DATA[3] invert by !MAIN[3][74]
DSSENinIMUX_G0_DATA[0] invert by !MAIN[3][61]
CTLMODEinIMUX_G2_DATA[1] invert by !MAIN[3][72]
CTLGOinIMUX_G1_DATA[3] invert by !MAIN[3][71]
CTLOSC1inIMUX_G1_DATA[2] invert by !MAIN[3][70]
CTLOSC2inIMUX_G1_DATA[1] invert by !MAIN[3][69]
CTLSEL[0]inIMUX_G0_DATA[1] invert by !MAIN[3][66]
CTLSEL[1]inIMUX_G0_DATA[2] invert by !MAIN[3][67]
CTLSEL[2]inIMUX_G0_DATA[3] invert by !MAIN[3][68]
CLK0outOUT_SEC[10]
CLK90outOUT_SEC[9]
CLK180outOUT_SEC[8]
CLK270outOUT_SEC[7]
CLK2XoutOUT_SEC[6]
CLK2X180outOUT_SEC[5]
CLKDVoutOUT_SEC[4]
CLKFXoutOUT_SEC[3]
CLKFX180outOUT_SEC[2]
CONCURoutOUT_SEC[11]
LOCKEDoutOUT_SEC[13]
PSDONEoutOUT_SEC[12]
STATUS[0]outOUT_HALF0[14]
STATUS[1]outOUT_HALF0[15]
STATUS[2]outOUT_HALF0[16]
STATUS[3]outOUT_HALF0[17]
STATUS[4]outOUT_HALF1[14]
STATUS[5]outOUT_HALF1[15]
STATUS[6]outOUT_HALF1[16]
STATUS[7]outOUT_HALF1[17]
virtex2 DCM_V2 bel DCM attribute bits
AttributeDCM
OUT_CLK0_ENABLEMAIN[3][49]
OUT_CLK90_ENABLEMAIN[3][50]
OUT_CLK180_ENABLEMAIN[3][51]
OUT_CLK270_ENABLEMAIN[3][52]
OUT_CLK2X_ENABLEMAIN[3][53]
OUT_CLK2X180_ENABLEMAIN[3][54]
OUT_CLKDV_ENABLEMAIN[3][55]
OUT_CLKFX_ENABLEMAIN[3][57]
OUT_CLKFX180_ENABLEMAIN[3][56]
OUT_CONCUR_ENABLEMAIN[3][58]
CLKDV_COUNT_MAX bit 0MAIN[0][36]
CLKDV_COUNT_MAX bit 1MAIN[0][37]
CLKDV_COUNT_MAX bit 2MAIN[0][38]
CLKDV_COUNT_MAX bit 3MAIN[0][39]
CLKDV_COUNT_FALL bit 0MAIN[0][40]
CLKDV_COUNT_FALL bit 1MAIN[0][41]
CLKDV_COUNT_FALL bit 2MAIN[0][42]
CLKDV_COUNT_FALL bit 3MAIN[0][43]
CLKDV_COUNT_FALL_2 bit 0MAIN[0][44]
CLKDV_COUNT_FALL_2 bit 1MAIN[0][45]
CLKDV_COUNT_FALL_2 bit 2MAIN[0][46]
CLKDV_COUNT_FALL_2 bit 3MAIN[0][47]
CLKDV_PHASE_RISE bit 0MAIN[0][48]
CLKDV_PHASE_RISE bit 1MAIN[0][49]
CLKDV_PHASE_FALL bit 0MAIN[0][50]
CLKDV_PHASE_FALL bit 1MAIN[0][51]
CLKDV_MODE[enum: DCM_CLKDV_MODE]
DESKEW_ADJUST bit 0MAIN[3][1]
DESKEW_ADJUST bit 1MAIN[3][2]
DESKEW_ADJUST bit 2MAIN[3][3]
DESKEW_ADJUST bit 3MAIN[3][4]
CLKIN_IOBMAIN[3][5]
CLKFB_IOBMAIN[3][6]
CLKIN_DIVIDE_BY_2MAIN[3][0]
CLK_FEEDBACK_2XMAIN[0][55]
DLL_ENABLEMAIN[0][17]
DLL_FREQUENCY_MODE[enum: DCM_FREQUENCY_MODE]
DFS_ENABLEMAIN[0][16]
DFS_FEEDBACKMAIN[3][43]
DFS_FREQUENCY_MODE[enum: DCM_FREQUENCY_MODE]
PHASE_SHIFT bit 0MAIN[0][22]
PHASE_SHIFT bit 1MAIN[0][23]
PHASE_SHIFT bit 2MAIN[0][24]
PHASE_SHIFT bit 3MAIN[0][25]
PHASE_SHIFT bit 4MAIN[0][26]
PHASE_SHIFT bit 5MAIN[0][27]
PHASE_SHIFT bit 6MAIN[0][28]
PHASE_SHIFT bit 7MAIN[0][29]
PHASE_SHIFT_NEGATIVEMAIN[0][21]
PS_ENABLEMAIN[0][19]
STARTUP_WAITMAIN[3][59]
V2_REG_COM bit 0MAIN[0][64]
V2_REG_COM bit 1MAIN[0][65]
V2_REG_COM bit 2MAIN[0][66]
V2_REG_COM bit 3MAIN[0][67]
V2_REG_COM bit 4MAIN[0][68]
V2_REG_COM bit 5MAIN[0][69]
V2_REG_COM bit 6MAIN[0][70]
V2_REG_COM bit 7MAIN[0][71]
V2_REG_COM bit 8MAIN[0][72]
V2_REG_COM bit 9MAIN[0][73]
V2_REG_COM bit 10MAIN[0][74]
V2_REG_COM bit 11MAIN[0][75]
V2_REG_COM bit 12MAIN[0][76]
V2_REG_COM bit 13MAIN[0][77]
V2_REG_COM bit 14MAIN[0][78]
V2_REG_COM bit 15MAIN[0][79]
V2_REG_COM bit 16MAIN[3][0]
V2_REG_COM bit 17MAIN[3][1]
V2_REG_COM bit 18MAIN[3][2]
V2_REG_COM bit 19MAIN[3][3]
V2_REG_COM bit 20MAIN[3][4]
V2_REG_COM bit 21MAIN[3][5]
V2_REG_COM bit 22MAIN[3][6]
V2_REG_COM bit 23MAIN[3][7]
V2_REG_COM bit 24MAIN[3][8]
V2_REG_COM bit 25MAIN[3][9]
V2_REG_COM bit 26MAIN[3][10]
V2_REG_COM bit 27MAIN[3][11]
V2_REG_COM bit 28MAIN[3][12]
V2_REG_COM bit 29MAIN[3][13]
V2_REG_COM bit 30MAIN[3][14]
V2_REG_COM bit 31MAIN[3][15]
V2_REG_DFS bit 0MAIN[3][16]
V2_REG_DFS bit 1MAIN[3][17]
V2_REG_DFS bit 2MAIN[3][18]
V2_REG_DFS bit 3MAIN[3][19]
V2_REG_DFS bit 4MAIN[3][20]
V2_REG_DFS bit 5MAIN[3][21]
V2_REG_DFS bit 6MAIN[3][22]
V2_REG_DFS bit 7MAIN[3][23]
V2_REG_DFS bit 8MAIN[3][24]
V2_REG_DFS bit 9MAIN[3][25]
V2_REG_DFS bit 10MAIN[3][26]
V2_REG_DFS bit 11MAIN[3][27]
V2_REG_DFS bit 12MAIN[3][28]
V2_REG_DFS bit 13MAIN[3][29]
V2_REG_DFS bit 14MAIN[3][30]
V2_REG_DFS bit 15MAIN[3][31]
V2_REG_DFS bit 16MAIN[3][32]
V2_REG_DFS bit 17MAIN[3][33]
V2_REG_DFS bit 18MAIN[3][34]
V2_REG_DFS bit 19MAIN[3][35]
V2_REG_DFS bit 20MAIN[3][36]
V2_REG_DFS bit 21MAIN[3][37]
V2_REG_DFS bit 22MAIN[3][38]
V2_REG_DFS bit 23MAIN[3][39]
V2_REG_DFS bit 24MAIN[3][40]
V2_REG_DFS bit 25MAIN[3][41]
V2_REG_DFS bit 26MAIN[3][42]
V2_REG_DFS bit 27MAIN[3][43]
V2_REG_DFS bit 28MAIN[3][44]
V2_REG_DFS bit 29MAIN[3][45]
V2_REG_DFS bit 30MAIN[3][46]
V2_REG_DFS bit 31MAIN[3][47]
V2_REG_DLLC bit 0MAIN[0][32]
V2_REG_DLLC bit 1MAIN[0][33]
V2_REG_DLLC bit 2MAIN[0][34]
V2_REG_DLLC bit 3MAIN[0][35]
V2_REG_DLLC bit 4MAIN[0][36]
V2_REG_DLLC bit 5MAIN[0][37]
V2_REG_DLLC bit 6MAIN[0][38]
V2_REG_DLLC bit 7MAIN[0][39]
V2_REG_DLLC bit 8MAIN[0][40]
V2_REG_DLLC bit 9MAIN[0][41]
V2_REG_DLLC bit 10MAIN[0][42]
V2_REG_DLLC bit 11MAIN[0][43]
V2_REG_DLLC bit 12MAIN[0][44]
V2_REG_DLLC bit 13MAIN[0][45]
V2_REG_DLLC bit 14MAIN[0][46]
V2_REG_DLLC bit 15MAIN[0][47]
V2_REG_DLLC bit 16MAIN[0][48]
V2_REG_DLLC bit 17MAIN[0][49]
V2_REG_DLLC bit 18MAIN[0][50]
V2_REG_DLLC bit 19MAIN[0][51]
V2_REG_DLLC bit 20MAIN[0][52]
V2_REG_DLLC bit 21MAIN[0][53]
V2_REG_DLLC bit 22MAIN[0][54]
V2_REG_DLLC bit 23MAIN[0][55]
V2_REG_DLLC bit 24MAIN[0][56]
V2_REG_DLLC bit 25MAIN[0][57]
V2_REG_DLLC bit 26MAIN[0][58]
V2_REG_DLLC bit 27MAIN[0][59]
V2_REG_DLLC bit 28MAIN[0][60]
V2_REG_DLLC bit 29MAIN[0][61]
V2_REG_DLLC bit 30MAIN[0][62]
V2_REG_DLLC bit 31MAIN[0][63]
V2_REG_DLLS bit 0MAIN[0][0]
V2_REG_DLLS bit 1MAIN[0][1]
V2_REG_DLLS bit 2MAIN[0][2]
V2_REG_DLLS bit 3MAIN[0][3]
V2_REG_DLLS bit 4MAIN[0][4]
V2_REG_DLLS bit 5MAIN[0][5]
V2_REG_DLLS bit 6MAIN[0][6]
V2_REG_DLLS bit 7MAIN[0][7]
V2_REG_DLLS bit 8MAIN[0][8]
V2_REG_DLLS bit 9MAIN[0][9]
V2_REG_DLLS bit 10MAIN[0][10]
V2_REG_DLLS bit 11MAIN[0][11]
V2_REG_DLLS bit 12MAIN[0][12]
V2_REG_DLLS bit 13MAIN[0][13]
V2_REG_DLLS bit 14MAIN[0][14]
V2_REG_DLLS bit 15MAIN[0][15]
V2_REG_DLLS bit 16MAIN[0][16]
V2_REG_DLLS bit 17MAIN[0][17]
V2_REG_DLLS bit 18MAIN[0][18]
V2_REG_DLLS bit 19MAIN[0][19]
V2_REG_DLLS bit 20MAIN[0][20]
V2_REG_DLLS bit 21MAIN[0][21]
V2_REG_DLLS bit 22MAIN[0][22]
V2_REG_DLLS bit 23MAIN[0][23]
V2_REG_DLLS bit 24MAIN[0][24]
V2_REG_DLLS bit 25MAIN[0][25]
V2_REG_DLLS bit 26MAIN[0][26]
V2_REG_DLLS bit 27MAIN[0][27]
V2_REG_DLLS bit 28MAIN[0][28]
V2_REG_DLLS bit 29MAIN[0][29]
V2_REG_DLLS bit 30MAIN[0][30]
V2_REG_DLLS bit 31MAIN[0][31]
V2_REG_MISC bit 0MAIN[3][48]
V2_REG_MISC bit 1MAIN[3][49]
V2_REG_MISC bit 2MAIN[3][50]
V2_REG_MISC bit 3MAIN[3][51]
V2_REG_MISC bit 4MAIN[3][52]
V2_REG_MISC bit 5MAIN[3][53]
V2_REG_MISC bit 6MAIN[3][54]
V2_REG_MISC bit 7MAIN[3][55]
V2_REG_MISC bit 8MAIN[3][56]
V2_REG_MISC bit 9MAIN[3][57]
V2_REG_MISC bit 10MAIN[3][58]
V2_REG_MISC bit 11MAIN[3][59]
V2_REG_MISC bit 12MAIN[3][60]
V2_REG_MISC bit 13MAIN[3][61]
V2_REG_MISC bit 14MAIN[3][62]
V2_REG_MISC bit 15MAIN[3][63]
V2_REG_MISC bit 16MAIN[3][64]
V2_REG_MISC bit 17MAIN[3][65]
V2_REG_MISC bit 18MAIN[3][66]
V2_REG_MISC bit 19MAIN[3][67]
V2_REG_MISC bit 20MAIN[3][68]
V2_REG_MISC bit 21MAIN[3][69]
V2_REG_MISC bit 22MAIN[3][70]
V2_REG_MISC bit 23MAIN[3][71]
V2_REG_MISC bit 24MAIN[3][72]
V2_REG_MISC bit 25MAIN[3][73]
V2_REG_MISC bit 26MAIN[3][74]
V2_REG_MISC bit 27MAIN[3][75]
V2_REG_MISC bit 28MAIN[3][76]
V2_REG_MISC bit 29MAIN[3][77]
V2_REG_MISC bit 30MAIN[3][78]
V2_REG_MISC bit 31MAIN[3][79]
V2_CLKFX_MULTIPLY bit 0MAIN[3][28]
V2_CLKFX_MULTIPLY bit 1MAIN[3][29]
V2_CLKFX_MULTIPLY bit 2MAIN[3][30]
V2_CLKFX_MULTIPLY bit 3MAIN[3][31]
V2_CLKFX_MULTIPLY bit 4MAIN[3][32]
V2_CLKFX_MULTIPLY bit 5MAIN[3][33]
V2_CLKFX_MULTIPLY bit 6MAIN[3][34]
V2_CLKFX_MULTIPLY bit 7MAIN[3][35]
V2_CLKFX_MULTIPLY bit 8MAIN[3][36]
V2_CLKFX_MULTIPLY bit 9MAIN[3][37]
V2_CLKFX_MULTIPLY bit 10MAIN[3][38]
V2_CLKFX_MULTIPLY bit 11MAIN[3][39]
V2_CLKFX_DIVIDE bit 0MAIN[3][16]
V2_CLKFX_DIVIDE bit 1MAIN[3][17]
V2_CLKFX_DIVIDE bit 2MAIN[3][18]
V2_CLKFX_DIVIDE bit 3MAIN[3][19]
V2_CLKFX_DIVIDE bit 4MAIN[3][20]
V2_CLKFX_DIVIDE bit 5MAIN[3][21]
V2_CLKFX_DIVIDE bit 6MAIN[3][22]
V2_CLKFX_DIVIDE bit 7MAIN[3][23]
V2_CLKFX_DIVIDE bit 8MAIN[3][24]
V2_CLKFX_DIVIDE bit 9MAIN[3][25]
V2_CLKFX_DIVIDE bit 10MAIN[3][26]
V2_CLKFX_DIVIDE bit 11MAIN[3][27]
V2_DUTY_CYCLE_CORRECTION bit 0MAIN[0][32]
V2_DUTY_CYCLE_CORRECTION bit 1MAIN[0][33]
V2_DUTY_CYCLE_CORRECTION bit 2MAIN[0][34]
V2_DUTY_CYCLE_CORRECTION bit 3MAIN[0][35]
DSS_ENABLEMAIN[0][20]
DSS_MODE[enum: DCM_DSS_MODE]
CLKFB_ENABLEMAIN[0][18]
STATUS1_ENABLEMAIN[0][60]
STATUS7_ENABLEMAIN[0][59]
PL_CENTEREDMAIN[3][47]
PS_CENTEREDMAIN[0][57]
PS_MODE[enum: DCM_PS_MODE]
SEL_PL_DLY bit 0MAIN[3][45]
SEL_PL_DLY bit 1MAIN[3][46]
COIN_WINDOW bit 0MAIN[3][13]
COIN_WINDOW bit 1MAIN[3][14]
NON_STOPMAIN[3][15]
V2_EN_DUMMY_OSC bit 0TERM[7][6]
V2_EN_DUMMY_OSC bit 1TERM[7][7]
V2_EN_DUMMY_OSC bit 2TERM[7][11]
EN_DUMMY_OSC_OR_NON_STOPTERM[7][9]
EN_OSC_COARSETERM[6][9]
FACTORY_JF1 bit 0MAIN[0][8]
FACTORY_JF1 bit 1MAIN[0][9]
FACTORY_JF1 bit 2MAIN[0][10]
FACTORY_JF1 bit 3MAIN[0][11]
FACTORY_JF1 bit 4MAIN[0][12]
FACTORY_JF1 bit 5MAIN[0][13]
FACTORY_JF1 bit 6MAIN[0][14]
FACTORY_JF1 bit 7MAIN[0][15]
FACTORY_JF2 bit 0MAIN[0][0]
FACTORY_JF2 bit 1MAIN[0][1]
FACTORY_JF2 bit 2MAIN[0][2]
FACTORY_JF2 bit 3MAIN[0][3]
FACTORY_JF2 bit 4MAIN[0][4]
FACTORY_JF2 bit 5MAIN[0][5]
FACTORY_JF2 bit 6MAIN[0][6]
FACTORY_JF2 bit 7MAIN[0][7]
TEST_ENABLEMAIN[3][79]
TEST_OSC[enum: DCM_TEST_OSC]
ZD2_BY1TERM[7][10]
V2_VBG_SEL bit 0MAIN[3][8]
V2_VBG_SEL bit 1MAIN[3][9]
V2_VBG_SEL bit 2MAIN[3][10]
V2_VBG_PD bit 0MAIN[3][11]
V2_VBG_PD bit 1MAIN[3][12]
virtex2 DCM_V2 enum DCM_CLKDV_MODE
DCM.CLKDV_MODEMAIN[0][52]
HALF0
INT1
virtex2 DCM_V2 enum DCM_FREQUENCY_MODE
DCM.DLL_FREQUENCY_MODEMAIN[0][56]
DCM.DFS_FREQUENCY_MODEMAIN[3][44]
LOW0
HIGH1
virtex2 DCM_V2 enum DCM_DSS_MODE
DCM.DSS_MODEMAIN[0][31]MAIN[0][30]
SPREAD_200
SPREAD_401
SPREAD_610
SPREAD_811
virtex2 DCM_V2 enum DCM_PS_MODE
DCM.PS_MODEMAIN[0][58]
CLKIN1
CLKFB0
virtex2 DCM_V2 enum DCM_TEST_OSC
DCM.TEST_OSCMAIN[0][54]MAIN[0][53]
_9000
_18001
_27010
_36011

Bel wires

virtex2 DCM_V2 bel wires
WirePins
IMUX_DCM_CLK_OPTINV[0]DCM.CLKFB
IMUX_DCM_CLK_OPTINV[1]DCM.CLKIN
IMUX_DCM_CLK_OPTINV[2]DCM.PSCLK
IMUX_G0_DATA[0]DCM.DSSEN
IMUX_G0_DATA[1]DCM.CTLSEL[0]
IMUX_G0_DATA[2]DCM.CTLSEL[1]
IMUX_G0_DATA[3]DCM.CTLSEL[2]
IMUX_G1_DATA[0]DCM.PSEN
IMUX_G1_DATA[1]DCM.CTLOSC2
IMUX_G1_DATA[2]DCM.CTLOSC1
IMUX_G1_DATA[3]DCM.CTLGO
IMUX_G2_DATA[0]DCM.PSINCDEC
IMUX_G2_DATA[1]DCM.CTLMODE
IMUX_G2_DATA[2]DCM.FREEZEDLL
IMUX_G2_DATA[3]DCM.FREEZEDFS
IMUX_G3_DATA[0]DCM.RST
IMUX_G3_DATA[1]DCM.STSADRS[0]
IMUX_G3_DATA[2]DCM.STSADRS[1]
IMUX_G3_DATA[3]DCM.STSADRS[2]
IMUX_G3_DATA[4]DCM.STSADRS[3]
OUT_SEC[2]DCM.CLKFX180
OUT_SEC[3]DCM.CLKFX
OUT_SEC[4]DCM.CLKDV
OUT_SEC[5]DCM.CLK2X180
OUT_SEC[6]DCM.CLK2X
OUT_SEC[7]DCM.CLK270
OUT_SEC[8]DCM.CLK180
OUT_SEC[9]DCM.CLK90
OUT_SEC[10]DCM.CLK0
OUT_SEC[11]DCM.CONCUR
OUT_SEC[12]DCM.PSDONE
OUT_SEC[13]DCM.LOCKED
OUT_HALF0[14]DCM.STATUS[0]
OUT_HALF0[15]DCM.STATUS[1]
OUT_HALF0[16]DCM.STATUS[2]
OUT_HALF0[17]DCM.STATUS[3]
OUT_HALF1[14]DCM.STATUS[4]
OUT_HALF1[15]DCM.STATUS[5]
OUT_HALF1[16]DCM.STATUS[6]
OUT_HALF1[17]DCM.STATUS[7]

Bitstream

virtex2 DCM_V2 rect MAIN
BitFrame
F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B79 - - - - - - - - - - - - - - - - - - DCM: V2_REG_MISC bit 31 DCM: TEST_ENABLE - - DCM: V2_REG_COM bit 15
B78 - - - - - - - - - - - - - - - - - - DCM: !invert STSADRS[3] DCM: V2_REG_MISC bit 30 - - DCM: V2_REG_COM bit 14
B77 - - - - - - - - - - - - - - - - - - DCM: !invert STSADRS[2] DCM: V2_REG_MISC bit 29 - - DCM: V2_REG_COM bit 13
B76 - - - - - - - - - - - - - - - - - - DCM: !invert STSADRS[1] DCM: V2_REG_MISC bit 28 - - DCM: V2_REG_COM bit 12
B75 - - - - - - - - - - - - - - - - - - DCM: !invert STSADRS[0] DCM: V2_REG_MISC bit 27 - - DCM: V2_REG_COM bit 11
B74 - - - - - - - - - - - - - - - - - - DCM: !invert FREEZEDFS DCM: V2_REG_MISC bit 26 - - DCM: V2_REG_COM bit 10
B73 - - - - - - - - - - - - - - - - - - DCM: !invert FREEZEDLL DCM: V2_REG_MISC bit 25 - - DCM: V2_REG_COM bit 9
B72 - - - - - - - - - - - - - - - - - - DCM: !invert CTLMODE DCM: V2_REG_MISC bit 24 - - DCM: V2_REG_COM bit 8
B71 - - - - - - - - - - - - - - - - - - DCM: !invert CTLGO DCM: V2_REG_MISC bit 23 - - DCM: V2_REG_COM bit 7
B70 - - - - - - - - - - - - - - - - - - DCM: !invert CTLOSC1 DCM: V2_REG_MISC bit 22 - - DCM: V2_REG_COM bit 6
B69 - - - - - - - - - - - - - - - - - - DCM: !invert CTLOSC2 DCM: V2_REG_MISC bit 21 - - DCM: V2_REG_COM bit 5
B68 - - - - - - - - - - - - - - - - - - DCM: !invert CTLSEL[2] DCM: V2_REG_MISC bit 20 - - DCM: V2_REG_COM bit 4
B67 - - - - - - - - - - - - - - - - - - DCM: !invert CTLSEL[1] DCM: V2_REG_MISC bit 19 - - DCM: V2_REG_COM bit 3
B66 - - - - - - - - - - - - - - - - - - DCM: !invert CTLSEL[0] DCM: V2_REG_MISC bit 18 - - DCM: V2_REG_COM bit 2
B65 - - - - - - - - - - - - - - - - - - DCM: !invert RST DCM: V2_REG_MISC bit 17 - - DCM: V2_REG_COM bit 1
B64 - - - - - - - - - - - - - - - - - - DCM: !invert PSINCDEC DCM: V2_REG_MISC bit 16 - - DCM: V2_REG_COM bit 0
B63 - - - - - - - - - - - - - - - - - - DCM: !invert PSEN DCM: V2_REG_MISC bit 15 - - DCM: V2_REG_DLLC bit 31
B62 - - - - - - - - - - - - - - - - - - DCM: V2_REG_MISC bit 14 - - DCM: V2_REG_DLLC bit 30
B61 - - - - - - - - - - - - - - - - - - DCM: !invert DSSEN DCM: V2_REG_MISC bit 13 - - DCM: V2_REG_DLLC bit 29
B60 - - - - - - - - - - - - - - - - - - DCM: V2_REG_MISC bit 12 - - DCM: V2_REG_DLLC bit 28 DCM: STATUS1_ENABLE
B59 - - - - - - - - - - - - - - - - - - DCM: STARTUP_WAIT DCM: V2_REG_MISC bit 11 - - DCM: V2_REG_DLLC bit 27 DCM: STATUS7_ENABLE
B58 - - - - - - - - - - - - - - - - - - DCM: OUT_CONCUR_ENABLE DCM: V2_REG_MISC bit 10 - - DCM: V2_REG_DLLC bit 26 DCM: PS_MODE bit 0
B57 - - - - - - - - - - - - - - - - - - DCM: OUT_CLKFX_ENABLE DCM: V2_REG_MISC bit 9 - - DCM: V2_REG_DLLC bit 25 DCM: PS_CENTERED
B56 - - - - - - - - - - - - - - - - - - DCM: OUT_CLKFX180_ENABLE DCM: V2_REG_MISC bit 8 - - DCM: V2_REG_DLLC bit 24 DCM: DLL_FREQUENCY_MODE bit 0
B55 - - - - - - - - - - - - - - - - - - DCM: OUT_CLKDV_ENABLE DCM: V2_REG_MISC bit 7 - - DCM: CLK_FEEDBACK_2X DCM: V2_REG_DLLC bit 23
B54 - - - - - - - - - - - - - - - - - - DCM: OUT_CLK2X180_ENABLE DCM: V2_REG_MISC bit 6 - - DCM: V2_REG_DLLC bit 22 DCM: TEST_OSC bit 1
B53 - - - - - - - - - - - - - - - - - - DCM: OUT_CLK2X_ENABLE DCM: V2_REG_MISC bit 5 - - DCM: V2_REG_DLLC bit 21 DCM: TEST_OSC bit 0
B52 - - - - - - - - - - - - - - - - - - DCM: OUT_CLK270_ENABLE DCM: V2_REG_MISC bit 4 - - DCM: V2_REG_DLLC bit 20 DCM: CLKDV_MODE bit 0
B51 - - - - - - - - - - - - - - - - - - DCM: OUT_CLK180_ENABLE DCM: V2_REG_MISC bit 3 - - DCM: CLKDV_PHASE_FALL bit 1 DCM: V2_REG_DLLC bit 19
B50 - - - - - - - - - - - - - - - - - - DCM: OUT_CLK90_ENABLE DCM: V2_REG_MISC bit 2 - - DCM: CLKDV_PHASE_FALL bit 0 DCM: V2_REG_DLLC bit 18
B49 - - - - - - - - - - - - - - - - - - DCM: OUT_CLK0_ENABLE DCM: V2_REG_MISC bit 1 - - DCM: CLKDV_PHASE_RISE bit 1 DCM: V2_REG_DLLC bit 17
B48 - - - - - - - - - - - - - - - - - - DCM: V2_REG_MISC bit 0 - - DCM: CLKDV_PHASE_RISE bit 0 DCM: V2_REG_DLLC bit 16
B47 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 31 DCM: PL_CENTERED - - DCM: CLKDV_COUNT_FALL_2 bit 3 DCM: V2_REG_DLLC bit 15
B46 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 30 DCM: SEL_PL_DLY bit 1 - - DCM: CLKDV_COUNT_FALL_2 bit 2 DCM: V2_REG_DLLC bit 14
B45 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 29 DCM: SEL_PL_DLY bit 0 - - DCM: CLKDV_COUNT_FALL_2 bit 1 DCM: V2_REG_DLLC bit 13
B44 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 28 DCM: DFS_FREQUENCY_MODE bit 0 - - DCM: CLKDV_COUNT_FALL_2 bit 0 DCM: V2_REG_DLLC bit 12
B43 - - - - - - - - - - - - - - - - - - DCM: DFS_FEEDBACK DCM: V2_REG_DFS bit 27 - - DCM: CLKDV_COUNT_FALL bit 3 DCM: V2_REG_DLLC bit 11
B42 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 26 - - DCM: CLKDV_COUNT_FALL bit 2 DCM: V2_REG_DLLC bit 10
B41 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 25 - - DCM: CLKDV_COUNT_FALL bit 1 DCM: V2_REG_DLLC bit 9
B40 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 24 - - DCM: CLKDV_COUNT_FALL bit 0 DCM: V2_REG_DLLC bit 8
B39 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 23 DCM: V2_CLKFX_MULTIPLY bit 11 - - DCM: CLKDV_COUNT_MAX bit 3 DCM: V2_REG_DLLC bit 7
B38 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 22 DCM: V2_CLKFX_MULTIPLY bit 10 - - DCM: CLKDV_COUNT_MAX bit 2 DCM: V2_REG_DLLC bit 6
B37 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 21 DCM: V2_CLKFX_MULTIPLY bit 9 - - DCM: CLKDV_COUNT_MAX bit 1 DCM: V2_REG_DLLC bit 5
B36 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 20 DCM: V2_CLKFX_MULTIPLY bit 8 - - DCM: CLKDV_COUNT_MAX bit 0 DCM: V2_REG_DLLC bit 4
B35 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 19 DCM: V2_CLKFX_MULTIPLY bit 7 - - DCM: V2_REG_DLLC bit 3 DCM: V2_DUTY_CYCLE_CORRECTION bit 3
B34 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 18 DCM: V2_CLKFX_MULTIPLY bit 6 - - DCM: V2_REG_DLLC bit 2 DCM: V2_DUTY_CYCLE_CORRECTION bit 2
B33 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 17 DCM: V2_CLKFX_MULTIPLY bit 5 - - DCM: V2_REG_DLLC bit 1 DCM: V2_DUTY_CYCLE_CORRECTION bit 1
B32 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 16 DCM: V2_CLKFX_MULTIPLY bit 4 - - DCM: V2_REG_DLLC bit 0 DCM: V2_DUTY_CYCLE_CORRECTION bit 0
B31 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 15 DCM: V2_CLKFX_MULTIPLY bit 3 - - DCM: V2_REG_DLLS bit 31 DCM: DSS_MODE bit 1
B30 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 14 DCM: V2_CLKFX_MULTIPLY bit 2 - - DCM: V2_REG_DLLS bit 30 DCM: DSS_MODE bit 0
B29 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 13 DCM: V2_CLKFX_MULTIPLY bit 1 - - DCM: PHASE_SHIFT bit 7 DCM: V2_REG_DLLS bit 29
B28 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 12 DCM: V2_CLKFX_MULTIPLY bit 0 - - DCM: PHASE_SHIFT bit 6 DCM: V2_REG_DLLS bit 28
B27 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 11 DCM: V2_CLKFX_DIVIDE bit 11 - - DCM: PHASE_SHIFT bit 5 DCM: V2_REG_DLLS bit 27
B26 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 10 DCM: V2_CLKFX_DIVIDE bit 10 - - DCM: PHASE_SHIFT bit 4 DCM: V2_REG_DLLS bit 26
B25 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 9 DCM: V2_CLKFX_DIVIDE bit 9 - - DCM: PHASE_SHIFT bit 3 DCM: V2_REG_DLLS bit 25
B24 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 8 DCM: V2_CLKFX_DIVIDE bit 8 - - DCM: PHASE_SHIFT bit 2 DCM: V2_REG_DLLS bit 24
B23 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 7 DCM: V2_CLKFX_DIVIDE bit 7 - - DCM: PHASE_SHIFT bit 1 DCM: V2_REG_DLLS bit 23
B22 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 6 DCM: V2_CLKFX_DIVIDE bit 6 - - DCM: PHASE_SHIFT bit 0 DCM: V2_REG_DLLS bit 22
B21 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 5 DCM: V2_CLKFX_DIVIDE bit 5 - - DCM: PHASE_SHIFT_NEGATIVE DCM: V2_REG_DLLS bit 21
B20 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 4 DCM: V2_CLKFX_DIVIDE bit 4 - - DCM: V2_REG_DLLS bit 20 DCM: DSS_ENABLE
B19 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 3 DCM: V2_CLKFX_DIVIDE bit 3 - - DCM: PS_ENABLE DCM: V2_REG_DLLS bit 19
B18 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 2 DCM: V2_CLKFX_DIVIDE bit 2 - - DCM: V2_REG_DLLS bit 18 DCM: CLKFB_ENABLE
B17 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 1 DCM: V2_CLKFX_DIVIDE bit 1 - - DCM: DLL_ENABLE DCM: V2_REG_DLLS bit 17
B16 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 0 DCM: V2_CLKFX_DIVIDE bit 0 - - DCM: DFS_ENABLE DCM: V2_REG_DLLS bit 16
B15 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 31 DCM: NON_STOP - - DCM: V2_REG_DLLS bit 15 DCM: FACTORY_JF1 bit 7
B14 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 30 DCM: COIN_WINDOW bit 1 - - DCM: V2_REG_DLLS bit 14 DCM: FACTORY_JF1 bit 6
B13 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 29 DCM: COIN_WINDOW bit 0 - - DCM: V2_REG_DLLS bit 13 DCM: FACTORY_JF1 bit 5
B12 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 28 DCM: V2_VBG_PD bit 1 - - DCM: V2_REG_DLLS bit 12 DCM: FACTORY_JF1 bit 4
B11 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 27 DCM: V2_VBG_PD bit 0 - - DCM: V2_REG_DLLS bit 11 DCM: FACTORY_JF1 bit 3
B10 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 26 DCM: V2_VBG_SEL bit 2 - - DCM: V2_REG_DLLS bit 10 DCM: FACTORY_JF1 bit 2
B9 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 25 DCM: V2_VBG_SEL bit 1 - - DCM: V2_REG_DLLS bit 9 DCM: FACTORY_JF1 bit 1
B8 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 24 DCM: V2_VBG_SEL bit 0 - - DCM: V2_REG_DLLS bit 8 DCM: FACTORY_JF1 bit 0
B7 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 23 - - DCM: V2_REG_DLLS bit 7 DCM: FACTORY_JF2 bit 7
B6 - - - - - - - - - - - - - - - - - - DCM: CLKFB_IOB DCM: V2_REG_COM bit 22 - - DCM: V2_REG_DLLS bit 6 DCM: FACTORY_JF2 bit 6
B5 - - - - - - - - - - - - - - - - - - DCM: CLKIN_IOB DCM: V2_REG_COM bit 21 - - DCM: V2_REG_DLLS bit 5 DCM: FACTORY_JF2 bit 5
B4 - - - - - - - - - - - - - - - - - - DCM: DESKEW_ADJUST bit 3 DCM: V2_REG_COM bit 20 - - DCM: V2_REG_DLLS bit 4 DCM: FACTORY_JF2 bit 4
B3 - - - - - - - - - - - - - - - - - - DCM: DESKEW_ADJUST bit 2 DCM: V2_REG_COM bit 19 - - DCM: V2_REG_DLLS bit 3 DCM: FACTORY_JF2 bit 3
B2 - - - - - - - - - - - - - - - - - - DCM: DESKEW_ADJUST bit 1 DCM: V2_REG_COM bit 18 - - DCM: V2_REG_DLLS bit 2 DCM: FACTORY_JF2 bit 2
B1 - - - - - - - - - - - - - - - - - - DCM: DESKEW_ADJUST bit 0 DCM: V2_REG_COM bit 17 - - DCM: V2_REG_DLLS bit 1 DCM: FACTORY_JF2 bit 1
B0 - - - - - - - - - - - - - - - - - - DCM: CLKIN_DIVIDE_BY_2 DCM: V2_REG_COM bit 16 - - DCM: V2_REG_DLLS bit 0 DCM: FACTORY_JF2 bit 0
virtex2 DCM_V2 rect TERM
BitFrame
F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - DCM: V2_EN_DUMMY_OSC bit 2 - - - - - - -
B10 - - - - - - - - - - - - - - DCM: ZD2_BY1 - - - - - - -
B9 - - - - - - - - - - - - - - DCM: EN_DUMMY_OSC_OR_NON_STOP DCM: EN_OSC_COARSE - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - DCM: V2_EN_DUMMY_OSC bit 1 - - - - - - -
B6 - - - - - - - - - - - - - - DCM: V2_EN_DUMMY_OSC bit 0 - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - -

Tile DCM_V2P

Cells: 1

Bels DCM

virtex2 DCM_V2P bel DCM pins
PinDirectionDCM
CLKINinIMUX_DCM_CLK_OPTINV[1]
CLKFBinIMUX_DCM_CLK_OPTINV[0]
RSTinIMUX_G3_DATA[0] invert by !MAIN[3][65]
PSCLKinIMUX_DCM_CLK_OPTINV[2]
PSENinIMUX_G1_DATA[0] invert by !MAIN[3][63]
PSINCDECinIMUX_G2_DATA[0] invert by !MAIN[3][64]
STSADRS[0]inIMUX_G3_DATA[1] invert by !MAIN[3][75]
STSADRS[1]inIMUX_G3_DATA[2] invert by !MAIN[3][76]
STSADRS[2]inIMUX_G3_DATA[3] invert by !MAIN[3][77]
STSADRS[3]inIMUX_G3_DATA[4] invert by !MAIN[3][78]
STSADRS[4]inIMUX_G3_DATA[5] invert by !MAIN[3][60]
FREEZEDLLinIMUX_G2_DATA[2] invert by !MAIN[3][73]
FREEZEDFSinIMUX_G2_DATA[3] invert by !MAIN[3][74]
DSSENinIMUX_G0_DATA[0] invert by !MAIN[3][61]
CTLMODEinIMUX_G2_DATA[1] invert by !MAIN[3][72]
CTLGOinIMUX_G1_DATA[3] invert by !MAIN[3][71]
CTLOSC1inIMUX_G1_DATA[2] invert by !MAIN[3][70]
CTLOSC2inIMUX_G1_DATA[1] invert by !MAIN[3][69]
CTLSEL[0]inIMUX_G0_DATA[1] invert by !MAIN[3][66]
CTLSEL[1]inIMUX_G0_DATA[2] invert by !MAIN[3][67]
CTLSEL[2]inIMUX_G0_DATA[3] invert by !MAIN[3][68]
CLK0outOUT_SEC[10]
CLK90outOUT_SEC[9]
CLK180outOUT_SEC[8]
CLK270outOUT_SEC[7]
CLK2XoutOUT_SEC[6]
CLK2X180outOUT_SEC[5]
CLKDVoutOUT_SEC[4]
CLKFXoutOUT_SEC[3]
CLKFX180outOUT_SEC[2]
CONCURoutOUT_SEC[11]
LOCKEDoutOUT_SEC[13]
PSDONEoutOUT_SEC[12]
STATUS[0]outOUT_HALF0[14]
STATUS[1]outOUT_HALF0[15]
STATUS[2]outOUT_HALF0[16]
STATUS[3]outOUT_HALF0[17]
STATUS[4]outOUT_HALF1[14]
STATUS[5]outOUT_HALF1[15]
STATUS[6]outOUT_HALF1[16]
STATUS[7]outOUT_HALF1[17]
virtex2 DCM_V2P bel DCM attribute bits
AttributeDCM
OUT_CLK0_ENABLEMAIN[3][49]
OUT_CLK90_ENABLEMAIN[3][50]
OUT_CLK180_ENABLEMAIN[3][51]
OUT_CLK270_ENABLEMAIN[3][52]
OUT_CLK2X_ENABLEMAIN[3][53]
OUT_CLK2X180_ENABLEMAIN[3][54]
OUT_CLKDV_ENABLEMAIN[3][55]
OUT_CLKFX_ENABLEMAIN[3][57]
OUT_CLKFX180_ENABLEMAIN[3][56]
OUT_CONCUR_ENABLEMAIN[3][58]
CLKDV_COUNT_MAX bit 0MAIN[0][36]
CLKDV_COUNT_MAX bit 1MAIN[0][37]
CLKDV_COUNT_MAX bit 2MAIN[0][38]
CLKDV_COUNT_MAX bit 3MAIN[0][39]
CLKDV_COUNT_FALL bit 0MAIN[0][40]
CLKDV_COUNT_FALL bit 1MAIN[0][41]
CLKDV_COUNT_FALL bit 2MAIN[0][42]
CLKDV_COUNT_FALL bit 3MAIN[0][43]
CLKDV_COUNT_FALL_2 bit 0MAIN[0][44]
CLKDV_COUNT_FALL_2 bit 1MAIN[0][45]
CLKDV_COUNT_FALL_2 bit 2MAIN[0][46]
CLKDV_COUNT_FALL_2 bit 3MAIN[0][47]
CLKDV_PHASE_RISE bit 0MAIN[0][48]
CLKDV_PHASE_RISE bit 1MAIN[0][49]
CLKDV_PHASE_FALL bit 0MAIN[0][50]
CLKDV_PHASE_FALL bit 1MAIN[0][51]
CLKDV_MODE[enum: DCM_CLKDV_MODE]
DESKEW_ADJUST bit 0MAIN[3][1]
DESKEW_ADJUST bit 1MAIN[3][2]
DESKEW_ADJUST bit 2MAIN[3][3]
DESKEW_ADJUST bit 3MAIN[3][4]
CLKIN_IOBMAIN[3][5]
CLKFB_IOBMAIN[3][6]
CLKIN_DIVIDE_BY_2MAIN[3][0]
CLK_FEEDBACK_2XMAIN[0][55]
DLL_ENABLEMAIN[0][17]
DLL_FREQUENCY_MODE[enum: DCM_FREQUENCY_MODE]
DFS_ENABLEMAIN[0][16]
DFS_FEEDBACKMAIN[3][43]
DFS_FREQUENCY_MODE[enum: DCM_FREQUENCY_MODE]
PHASE_SHIFT bit 0MAIN[0][22]
PHASE_SHIFT bit 1MAIN[0][23]
PHASE_SHIFT bit 2MAIN[0][24]
PHASE_SHIFT bit 3MAIN[0][25]
PHASE_SHIFT bit 4MAIN[0][26]
PHASE_SHIFT bit 5MAIN[0][27]
PHASE_SHIFT bit 6MAIN[0][28]
PHASE_SHIFT bit 7MAIN[0][29]
PHASE_SHIFT_NEGATIVEMAIN[0][21]
PS_ENABLEMAIN[0][19]
STARTUP_WAITMAIN[3][59]
V2_REG_COM bit 0MAIN[0][64]
V2_REG_COM bit 1MAIN[0][65]
V2_REG_COM bit 2MAIN[0][66]
V2_REG_COM bit 3MAIN[0][67]
V2_REG_COM bit 4MAIN[0][68]
V2_REG_COM bit 5MAIN[0][69]
V2_REG_COM bit 6MAIN[0][70]
V2_REG_COM bit 7MAIN[0][71]
V2_REG_COM bit 8MAIN[0][72]
V2_REG_COM bit 9MAIN[0][73]
V2_REG_COM bit 10MAIN[0][74]
V2_REG_COM bit 11MAIN[0][75]
V2_REG_COM bit 12MAIN[0][76]
V2_REG_COM bit 13MAIN[0][77]
V2_REG_COM bit 14MAIN[0][78]
V2_REG_COM bit 15MAIN[0][79]
V2_REG_COM bit 16MAIN[3][0]
V2_REG_COM bit 17MAIN[3][1]
V2_REG_COM bit 18MAIN[3][2]
V2_REG_COM bit 19MAIN[3][3]
V2_REG_COM bit 20MAIN[3][4]
V2_REG_COM bit 21MAIN[3][5]
V2_REG_COM bit 22MAIN[3][6]
V2_REG_COM bit 23MAIN[3][7]
V2_REG_COM bit 24MAIN[3][8]
V2_REG_COM bit 25MAIN[3][9]
V2_REG_COM bit 26MAIN[3][10]
V2_REG_COM bit 27MAIN[3][11]
V2_REG_COM bit 28MAIN[3][12]
V2_REG_COM bit 29MAIN[3][13]
V2_REG_COM bit 30MAIN[3][14]
V2_REG_COM bit 31MAIN[3][15]
V2_REG_DFS bit 0MAIN[3][16]
V2_REG_DFS bit 1MAIN[3][17]
V2_REG_DFS bit 2MAIN[3][18]
V2_REG_DFS bit 3MAIN[3][19]
V2_REG_DFS bit 4MAIN[3][20]
V2_REG_DFS bit 5MAIN[3][21]
V2_REG_DFS bit 6MAIN[3][22]
V2_REG_DFS bit 7MAIN[3][23]
V2_REG_DFS bit 8MAIN[3][24]
V2_REG_DFS bit 9MAIN[3][25]
V2_REG_DFS bit 10MAIN[3][26]
V2_REG_DFS bit 11MAIN[3][27]
V2_REG_DFS bit 12MAIN[3][28]
V2_REG_DFS bit 13MAIN[3][29]
V2_REG_DFS bit 14MAIN[3][30]
V2_REG_DFS bit 15MAIN[3][31]
V2_REG_DFS bit 16MAIN[3][32]
V2_REG_DFS bit 17MAIN[3][33]
V2_REG_DFS bit 18MAIN[3][34]
V2_REG_DFS bit 19MAIN[3][35]
V2_REG_DFS bit 20MAIN[3][36]
V2_REG_DFS bit 21MAIN[3][37]
V2_REG_DFS bit 22MAIN[3][38]
V2_REG_DFS bit 23MAIN[3][39]
V2_REG_DFS bit 24MAIN[3][40]
V2_REG_DFS bit 25MAIN[3][41]
V2_REG_DFS bit 26MAIN[3][42]
V2_REG_DFS bit 27MAIN[3][43]
V2_REG_DFS bit 28MAIN[3][44]
V2_REG_DFS bit 29MAIN[3][45]
V2_REG_DFS bit 30MAIN[3][46]
V2_REG_DFS bit 31MAIN[3][47]
V2_REG_DLLC bit 0MAIN[0][32]
V2_REG_DLLC bit 1MAIN[0][33]
V2_REG_DLLC bit 2MAIN[0][34]
V2_REG_DLLC bit 3MAIN[0][35]
V2_REG_DLLC bit 4MAIN[0][36]
V2_REG_DLLC bit 5MAIN[0][37]
V2_REG_DLLC bit 6MAIN[0][38]
V2_REG_DLLC bit 7MAIN[0][39]
V2_REG_DLLC bit 8MAIN[0][40]
V2_REG_DLLC bit 9MAIN[0][41]
V2_REG_DLLC bit 10MAIN[0][42]
V2_REG_DLLC bit 11MAIN[0][43]
V2_REG_DLLC bit 12MAIN[0][44]
V2_REG_DLLC bit 13MAIN[0][45]
V2_REG_DLLC bit 14MAIN[0][46]
V2_REG_DLLC bit 15MAIN[0][47]
V2_REG_DLLC bit 16MAIN[0][48]
V2_REG_DLLC bit 17MAIN[0][49]
V2_REG_DLLC bit 18MAIN[0][50]
V2_REG_DLLC bit 19MAIN[0][51]
V2_REG_DLLC bit 20MAIN[0][52]
V2_REG_DLLC bit 21MAIN[0][53]
V2_REG_DLLC bit 22MAIN[0][54]
V2_REG_DLLC bit 23MAIN[0][55]
V2_REG_DLLC bit 24MAIN[0][56]
V2_REG_DLLC bit 25MAIN[0][57]
V2_REG_DLLC bit 26MAIN[0][58]
V2_REG_DLLC bit 27MAIN[0][59]
V2_REG_DLLC bit 28MAIN[0][60]
V2_REG_DLLC bit 29MAIN[0][61]
V2_REG_DLLC bit 30MAIN[0][62]
V2_REG_DLLC bit 31MAIN[0][63]
V2_REG_DLLS bit 0MAIN[0][0]
V2_REG_DLLS bit 1MAIN[0][1]
V2_REG_DLLS bit 2MAIN[0][2]
V2_REG_DLLS bit 3MAIN[0][3]
V2_REG_DLLS bit 4MAIN[0][4]
V2_REG_DLLS bit 5MAIN[0][5]
V2_REG_DLLS bit 6MAIN[0][6]
V2_REG_DLLS bit 7MAIN[0][7]
V2_REG_DLLS bit 8MAIN[0][8]
V2_REG_DLLS bit 9MAIN[0][9]
V2_REG_DLLS bit 10MAIN[0][10]
V2_REG_DLLS bit 11MAIN[0][11]
V2_REG_DLLS bit 12MAIN[0][12]
V2_REG_DLLS bit 13MAIN[0][13]
V2_REG_DLLS bit 14MAIN[0][14]
V2_REG_DLLS bit 15MAIN[0][15]
V2_REG_DLLS bit 16MAIN[0][16]
V2_REG_DLLS bit 17MAIN[0][17]
V2_REG_DLLS bit 18MAIN[0][18]
V2_REG_DLLS bit 19MAIN[0][19]
V2_REG_DLLS bit 20MAIN[0][20]
V2_REG_DLLS bit 21MAIN[0][21]
V2_REG_DLLS bit 22MAIN[0][22]
V2_REG_DLLS bit 23MAIN[0][23]
V2_REG_DLLS bit 24MAIN[0][24]
V2_REG_DLLS bit 25MAIN[0][25]
V2_REG_DLLS bit 26MAIN[0][26]
V2_REG_DLLS bit 27MAIN[0][27]
V2_REG_DLLS bit 28MAIN[0][28]
V2_REG_DLLS bit 29MAIN[0][29]
V2_REG_DLLS bit 30MAIN[0][30]
V2_REG_DLLS bit 31MAIN[0][31]
V2_REG_MISC bit 0MAIN[3][48]
V2_REG_MISC bit 1MAIN[3][49]
V2_REG_MISC bit 2MAIN[3][50]
V2_REG_MISC bit 3MAIN[3][51]
V2_REG_MISC bit 4MAIN[3][52]
V2_REG_MISC bit 5MAIN[3][53]
V2_REG_MISC bit 6MAIN[3][54]
V2_REG_MISC bit 7MAIN[3][55]
V2_REG_MISC bit 8MAIN[3][56]
V2_REG_MISC bit 9MAIN[3][57]
V2_REG_MISC bit 10MAIN[3][58]
V2_REG_MISC bit 11MAIN[3][59]
V2_REG_MISC bit 12MAIN[3][60]
V2_REG_MISC bit 13MAIN[3][61]
V2_REG_MISC bit 14MAIN[3][62]
V2_REG_MISC bit 15MAIN[3][63]
V2_REG_MISC bit 16MAIN[3][64]
V2_REG_MISC bit 17MAIN[3][65]
V2_REG_MISC bit 18MAIN[3][66]
V2_REG_MISC bit 19MAIN[3][67]
V2_REG_MISC bit 20MAIN[3][68]
V2_REG_MISC bit 21MAIN[3][69]
V2_REG_MISC bit 22MAIN[3][70]
V2_REG_MISC bit 23MAIN[3][71]
V2_REG_MISC bit 24MAIN[3][72]
V2_REG_MISC bit 25MAIN[3][73]
V2_REG_MISC bit 26MAIN[3][74]
V2_REG_MISC bit 27MAIN[3][75]
V2_REG_MISC bit 28MAIN[3][76]
V2_REG_MISC bit 29MAIN[3][77]
V2_REG_MISC bit 30MAIN[3][78]
V2_REG_MISC bit 31MAIN[3][79]
V2_CLKFX_MULTIPLY bit 0MAIN[3][28]
V2_CLKFX_MULTIPLY bit 1MAIN[3][29]
V2_CLKFX_MULTIPLY bit 2MAIN[3][30]
V2_CLKFX_MULTIPLY bit 3MAIN[3][31]
V2_CLKFX_MULTIPLY bit 4MAIN[3][32]
V2_CLKFX_MULTIPLY bit 5MAIN[3][33]
V2_CLKFX_MULTIPLY bit 6MAIN[3][34]
V2_CLKFX_MULTIPLY bit 7MAIN[3][35]
V2_CLKFX_MULTIPLY bit 8MAIN[3][36]
V2_CLKFX_MULTIPLY bit 9MAIN[3][37]
V2_CLKFX_MULTIPLY bit 10MAIN[3][38]
V2_CLKFX_MULTIPLY bit 11MAIN[3][39]
V2_CLKFX_DIVIDE bit 0MAIN[3][16]
V2_CLKFX_DIVIDE bit 1MAIN[3][17]
V2_CLKFX_DIVIDE bit 2MAIN[3][18]
V2_CLKFX_DIVIDE bit 3MAIN[3][19]
V2_CLKFX_DIVIDE bit 4MAIN[3][20]
V2_CLKFX_DIVIDE bit 5MAIN[3][21]
V2_CLKFX_DIVIDE bit 6MAIN[3][22]
V2_CLKFX_DIVIDE bit 7MAIN[3][23]
V2_CLKFX_DIVIDE bit 8MAIN[3][24]
V2_CLKFX_DIVIDE bit 9MAIN[3][25]
V2_CLKFX_DIVIDE bit 10MAIN[3][26]
V2_CLKFX_DIVIDE bit 11MAIN[3][27]
V2_DUTY_CYCLE_CORRECTION bit 0MAIN[0][32]
V2_DUTY_CYCLE_CORRECTION bit 1MAIN[0][33]
V2_DUTY_CYCLE_CORRECTION bit 2MAIN[0][34]
V2_DUTY_CYCLE_CORRECTION bit 3MAIN[0][35]
DSS_ENABLEMAIN[0][20]
DSS_MODE[enum: DCM_DSS_MODE]
CLKFB_ENABLEMAIN[0][18]
STATUS1_ENABLEMAIN[0][60]
STATUS7_ENABLEMAIN[0][59]
PL_CENTEREDMAIN[3][47]
PS_CENTEREDMAIN[0][57]
PS_MODE[enum: DCM_PS_MODE]
SEL_PL_DLY bit 0MAIN[3][45]
SEL_PL_DLY bit 1MAIN[3][46]
COIN_WINDOW bit 0MAIN[3][13]
COIN_WINDOW bit 1MAIN[3][14]
NON_STOPMAIN[3][15]
V2_EN_DUMMY_OSC bit 0TERM[7][6]
V2_EN_DUMMY_OSC bit 1TERM[7][7]
V2_EN_DUMMY_OSC bit 2TERM[7][11]
EN_DUMMY_OSC_OR_NON_STOPTERM[7][9]
EN_OSC_COARSETERM[6][9]
FACTORY_JF1 bit 0MAIN[0][8]
FACTORY_JF1 bit 1MAIN[0][9]
FACTORY_JF1 bit 2MAIN[0][10]
FACTORY_JF1 bit 3MAIN[0][11]
FACTORY_JF1 bit 4MAIN[0][12]
FACTORY_JF1 bit 5MAIN[0][13]
FACTORY_JF1 bit 6MAIN[0][14]
FACTORY_JF1 bit 7MAIN[0][15]
FACTORY_JF2 bit 0MAIN[0][0]
FACTORY_JF2 bit 1MAIN[0][1]
FACTORY_JF2 bit 2MAIN[0][2]
FACTORY_JF2 bit 3MAIN[0][3]
FACTORY_JF2 bit 4MAIN[0][4]
FACTORY_JF2 bit 5MAIN[0][5]
FACTORY_JF2 bit 6MAIN[0][6]
FACTORY_JF2 bit 7MAIN[0][7]
TEST_ENABLEMAIN[3][79]
TEST_OSC[enum: DCM_TEST_OSC]
ZD2_BY1TERM[7][10]
V2_VBG_SEL bit 0MAIN[3][8]
V2_VBG_SEL bit 1MAIN[3][9]
V2_VBG_SEL bit 2MAIN[3][10]
V2_VBG_PD bit 0MAIN[3][11]
V2_VBG_PD bit 1MAIN[3][12]
ZD1_BY1TERM[7][8]
RESET_PS_SELTERM[4][10]
virtex2 DCM_V2P enum DCM_CLKDV_MODE
DCM.CLKDV_MODEMAIN[0][52]
HALF0
INT1
virtex2 DCM_V2P enum DCM_FREQUENCY_MODE
DCM.DLL_FREQUENCY_MODEMAIN[0][56]
DCM.DFS_FREQUENCY_MODEMAIN[3][44]
LOW0
HIGH1
virtex2 DCM_V2P enum DCM_DSS_MODE
DCM.DSS_MODEMAIN[0][31]MAIN[0][30]
SPREAD_200
SPREAD_401
SPREAD_610
SPREAD_811
virtex2 DCM_V2P enum DCM_PS_MODE
DCM.PS_MODEMAIN[0][58]
CLKIN1
CLKFB0
virtex2 DCM_V2P enum DCM_TEST_OSC
DCM.TEST_OSCMAIN[0][54]MAIN[0][53]
_9000
_18001
_27010
_36011

Bel wires

virtex2 DCM_V2P bel wires
WirePins
IMUX_DCM_CLK_OPTINV[0]DCM.CLKFB
IMUX_DCM_CLK_OPTINV[1]DCM.CLKIN
IMUX_DCM_CLK_OPTINV[2]DCM.PSCLK
IMUX_G0_DATA[0]DCM.DSSEN
IMUX_G0_DATA[1]DCM.CTLSEL[0]
IMUX_G0_DATA[2]DCM.CTLSEL[1]
IMUX_G0_DATA[3]DCM.CTLSEL[2]
IMUX_G1_DATA[0]DCM.PSEN
IMUX_G1_DATA[1]DCM.CTLOSC2
IMUX_G1_DATA[2]DCM.CTLOSC1
IMUX_G1_DATA[3]DCM.CTLGO
IMUX_G2_DATA[0]DCM.PSINCDEC
IMUX_G2_DATA[1]DCM.CTLMODE
IMUX_G2_DATA[2]DCM.FREEZEDLL
IMUX_G2_DATA[3]DCM.FREEZEDFS
IMUX_G3_DATA[0]DCM.RST
IMUX_G3_DATA[1]DCM.STSADRS[0]
IMUX_G3_DATA[2]DCM.STSADRS[1]
IMUX_G3_DATA[3]DCM.STSADRS[2]
IMUX_G3_DATA[4]DCM.STSADRS[3]
IMUX_G3_DATA[5]DCM.STSADRS[4]
OUT_SEC[2]DCM.CLKFX180
OUT_SEC[3]DCM.CLKFX
OUT_SEC[4]DCM.CLKDV
OUT_SEC[5]DCM.CLK2X180
OUT_SEC[6]DCM.CLK2X
OUT_SEC[7]DCM.CLK270
OUT_SEC[8]DCM.CLK180
OUT_SEC[9]DCM.CLK90
OUT_SEC[10]DCM.CLK0
OUT_SEC[11]DCM.CONCUR
OUT_SEC[12]DCM.PSDONE
OUT_SEC[13]DCM.LOCKED
OUT_HALF0[14]DCM.STATUS[0]
OUT_HALF0[15]DCM.STATUS[1]
OUT_HALF0[16]DCM.STATUS[2]
OUT_HALF0[17]DCM.STATUS[3]
OUT_HALF1[14]DCM.STATUS[4]
OUT_HALF1[15]DCM.STATUS[5]
OUT_HALF1[16]DCM.STATUS[6]
OUT_HALF1[17]DCM.STATUS[7]

Bitstream

virtex2 DCM_V2P rect MAIN
BitFrame
F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B79 - - - - - - - - - - - - - - - - - - DCM: V2_REG_MISC bit 31 DCM: TEST_ENABLE - - DCM: V2_REG_COM bit 15
B78 - - - - - - - - - - - - - - - - - - DCM: !invert STSADRS[3] DCM: V2_REG_MISC bit 30 - - DCM: V2_REG_COM bit 14
B77 - - - - - - - - - - - - - - - - - - DCM: !invert STSADRS[2] DCM: V2_REG_MISC bit 29 - - DCM: V2_REG_COM bit 13
B76 - - - - - - - - - - - - - - - - - - DCM: !invert STSADRS[1] DCM: V2_REG_MISC bit 28 - - DCM: V2_REG_COM bit 12
B75 - - - - - - - - - - - - - - - - - - DCM: !invert STSADRS[0] DCM: V2_REG_MISC bit 27 - - DCM: V2_REG_COM bit 11
B74 - - - - - - - - - - - - - - - - - - DCM: !invert FREEZEDFS DCM: V2_REG_MISC bit 26 - - DCM: V2_REG_COM bit 10
B73 - - - - - - - - - - - - - - - - - - DCM: !invert FREEZEDLL DCM: V2_REG_MISC bit 25 - - DCM: V2_REG_COM bit 9
B72 - - - - - - - - - - - - - - - - - - DCM: !invert CTLMODE DCM: V2_REG_MISC bit 24 - - DCM: V2_REG_COM bit 8
B71 - - - - - - - - - - - - - - - - - - DCM: !invert CTLGO DCM: V2_REG_MISC bit 23 - - DCM: V2_REG_COM bit 7
B70 - - - - - - - - - - - - - - - - - - DCM: !invert CTLOSC1 DCM: V2_REG_MISC bit 22 - - DCM: V2_REG_COM bit 6
B69 - - - - - - - - - - - - - - - - - - DCM: !invert CTLOSC2 DCM: V2_REG_MISC bit 21 - - DCM: V2_REG_COM bit 5
B68 - - - - - - - - - - - - - - - - - - DCM: !invert CTLSEL[2] DCM: V2_REG_MISC bit 20 - - DCM: V2_REG_COM bit 4
B67 - - - - - - - - - - - - - - - - - - DCM: !invert CTLSEL[1] DCM: V2_REG_MISC bit 19 - - DCM: V2_REG_COM bit 3
B66 - - - - - - - - - - - - - - - - - - DCM: !invert CTLSEL[0] DCM: V2_REG_MISC bit 18 - - DCM: V2_REG_COM bit 2
B65 - - - - - - - - - - - - - - - - - - DCM: !invert RST DCM: V2_REG_MISC bit 17 - - DCM: V2_REG_COM bit 1
B64 - - - - - - - - - - - - - - - - - - DCM: !invert PSINCDEC DCM: V2_REG_MISC bit 16 - - DCM: V2_REG_COM bit 0
B63 - - - - - - - - - - - - - - - - - - DCM: !invert PSEN DCM: V2_REG_MISC bit 15 - - DCM: V2_REG_DLLC bit 31
B62 - - - - - - - - - - - - - - - - - - DCM: V2_REG_MISC bit 14 - - DCM: V2_REG_DLLC bit 30
B61 - - - - - - - - - - - - - - - - - - DCM: !invert DSSEN DCM: V2_REG_MISC bit 13 - - DCM: V2_REG_DLLC bit 29
B60 - - - - - - - - - - - - - - - - - - DCM: !invert STSADRS[4] DCM: V2_REG_MISC bit 12 - - DCM: V2_REG_DLLC bit 28 DCM: STATUS1_ENABLE
B59 - - - - - - - - - - - - - - - - - - DCM: STARTUP_WAIT DCM: V2_REG_MISC bit 11 - - DCM: V2_REG_DLLC bit 27 DCM: STATUS7_ENABLE
B58 - - - - - - - - - - - - - - - - - - DCM: OUT_CONCUR_ENABLE DCM: V2_REG_MISC bit 10 - - DCM: V2_REG_DLLC bit 26 DCM: PS_MODE bit 0
B57 - - - - - - - - - - - - - - - - - - DCM: OUT_CLKFX_ENABLE DCM: V2_REG_MISC bit 9 - - DCM: V2_REG_DLLC bit 25 DCM: PS_CENTERED
B56 - - - - - - - - - - - - - - - - - - DCM: OUT_CLKFX180_ENABLE DCM: V2_REG_MISC bit 8 - - DCM: V2_REG_DLLC bit 24 DCM: DLL_FREQUENCY_MODE bit 0
B55 - - - - - - - - - - - - - - - - - - DCM: OUT_CLKDV_ENABLE DCM: V2_REG_MISC bit 7 - - DCM: CLK_FEEDBACK_2X DCM: V2_REG_DLLC bit 23
B54 - - - - - - - - - - - - - - - - - - DCM: OUT_CLK2X180_ENABLE DCM: V2_REG_MISC bit 6 - - DCM: V2_REG_DLLC bit 22 DCM: TEST_OSC bit 1
B53 - - - - - - - - - - - - - - - - - - DCM: OUT_CLK2X_ENABLE DCM: V2_REG_MISC bit 5 - - DCM: V2_REG_DLLC bit 21 DCM: TEST_OSC bit 0
B52 - - - - - - - - - - - - - - - - - - DCM: OUT_CLK270_ENABLE DCM: V2_REG_MISC bit 4 - - DCM: V2_REG_DLLC bit 20 DCM: CLKDV_MODE bit 0
B51 - - - - - - - - - - - - - - - - - - DCM: OUT_CLK180_ENABLE DCM: V2_REG_MISC bit 3 - - DCM: CLKDV_PHASE_FALL bit 1 DCM: V2_REG_DLLC bit 19
B50 - - - - - - - - - - - - - - - - - - DCM: OUT_CLK90_ENABLE DCM: V2_REG_MISC bit 2 - - DCM: CLKDV_PHASE_FALL bit 0 DCM: V2_REG_DLLC bit 18
B49 - - - - - - - - - - - - - - - - - - DCM: OUT_CLK0_ENABLE DCM: V2_REG_MISC bit 1 - - DCM: CLKDV_PHASE_RISE bit 1 DCM: V2_REG_DLLC bit 17
B48 - - - - - - - - - - - - - - - - - - DCM: V2_REG_MISC bit 0 - - DCM: CLKDV_PHASE_RISE bit 0 DCM: V2_REG_DLLC bit 16
B47 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 31 DCM: PL_CENTERED - - DCM: CLKDV_COUNT_FALL_2 bit 3 DCM: V2_REG_DLLC bit 15
B46 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 30 DCM: SEL_PL_DLY bit 1 - - DCM: CLKDV_COUNT_FALL_2 bit 2 DCM: V2_REG_DLLC bit 14
B45 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 29 DCM: SEL_PL_DLY bit 0 - - DCM: CLKDV_COUNT_FALL_2 bit 1 DCM: V2_REG_DLLC bit 13
B44 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 28 DCM: DFS_FREQUENCY_MODE bit 0 - - DCM: CLKDV_COUNT_FALL_2 bit 0 DCM: V2_REG_DLLC bit 12
B43 - - - - - - - - - - - - - - - - - - DCM: DFS_FEEDBACK DCM: V2_REG_DFS bit 27 - - DCM: CLKDV_COUNT_FALL bit 3 DCM: V2_REG_DLLC bit 11
B42 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 26 - - DCM: CLKDV_COUNT_FALL bit 2 DCM: V2_REG_DLLC bit 10
B41 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 25 - - DCM: CLKDV_COUNT_FALL bit 1 DCM: V2_REG_DLLC bit 9
B40 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 24 - - DCM: CLKDV_COUNT_FALL bit 0 DCM: V2_REG_DLLC bit 8
B39 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 23 DCM: V2_CLKFX_MULTIPLY bit 11 - - DCM: CLKDV_COUNT_MAX bit 3 DCM: V2_REG_DLLC bit 7
B38 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 22 DCM: V2_CLKFX_MULTIPLY bit 10 - - DCM: CLKDV_COUNT_MAX bit 2 DCM: V2_REG_DLLC bit 6
B37 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 21 DCM: V2_CLKFX_MULTIPLY bit 9 - - DCM: CLKDV_COUNT_MAX bit 1 DCM: V2_REG_DLLC bit 5
B36 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 20 DCM: V2_CLKFX_MULTIPLY bit 8 - - DCM: CLKDV_COUNT_MAX bit 0 DCM: V2_REG_DLLC bit 4
B35 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 19 DCM: V2_CLKFX_MULTIPLY bit 7 - - DCM: V2_REG_DLLC bit 3 DCM: V2_DUTY_CYCLE_CORRECTION bit 3
B34 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 18 DCM: V2_CLKFX_MULTIPLY bit 6 - - DCM: V2_REG_DLLC bit 2 DCM: V2_DUTY_CYCLE_CORRECTION bit 2
B33 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 17 DCM: V2_CLKFX_MULTIPLY bit 5 - - DCM: V2_REG_DLLC bit 1 DCM: V2_DUTY_CYCLE_CORRECTION bit 1
B32 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 16 DCM: V2_CLKFX_MULTIPLY bit 4 - - DCM: V2_REG_DLLC bit 0 DCM: V2_DUTY_CYCLE_CORRECTION bit 0
B31 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 15 DCM: V2_CLKFX_MULTIPLY bit 3 - - DCM: V2_REG_DLLS bit 31 DCM: DSS_MODE bit 1
B30 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 14 DCM: V2_CLKFX_MULTIPLY bit 2 - - DCM: V2_REG_DLLS bit 30 DCM: DSS_MODE bit 0
B29 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 13 DCM: V2_CLKFX_MULTIPLY bit 1 - - DCM: PHASE_SHIFT bit 7 DCM: V2_REG_DLLS bit 29
B28 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 12 DCM: V2_CLKFX_MULTIPLY bit 0 - - DCM: PHASE_SHIFT bit 6 DCM: V2_REG_DLLS bit 28
B27 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 11 DCM: V2_CLKFX_DIVIDE bit 11 - - DCM: PHASE_SHIFT bit 5 DCM: V2_REG_DLLS bit 27
B26 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 10 DCM: V2_CLKFX_DIVIDE bit 10 - - DCM: PHASE_SHIFT bit 4 DCM: V2_REG_DLLS bit 26
B25 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 9 DCM: V2_CLKFX_DIVIDE bit 9 - - DCM: PHASE_SHIFT bit 3 DCM: V2_REG_DLLS bit 25
B24 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 8 DCM: V2_CLKFX_DIVIDE bit 8 - - DCM: PHASE_SHIFT bit 2 DCM: V2_REG_DLLS bit 24
B23 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 7 DCM: V2_CLKFX_DIVIDE bit 7 - - DCM: PHASE_SHIFT bit 1 DCM: V2_REG_DLLS bit 23
B22 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 6 DCM: V2_CLKFX_DIVIDE bit 6 - - DCM: PHASE_SHIFT bit 0 DCM: V2_REG_DLLS bit 22
B21 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 5 DCM: V2_CLKFX_DIVIDE bit 5 - - DCM: PHASE_SHIFT_NEGATIVE DCM: V2_REG_DLLS bit 21
B20 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 4 DCM: V2_CLKFX_DIVIDE bit 4 - - DCM: V2_REG_DLLS bit 20 DCM: DSS_ENABLE
B19 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 3 DCM: V2_CLKFX_DIVIDE bit 3 - - DCM: PS_ENABLE DCM: V2_REG_DLLS bit 19
B18 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 2 DCM: V2_CLKFX_DIVIDE bit 2 - - DCM: V2_REG_DLLS bit 18 DCM: CLKFB_ENABLE
B17 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 1 DCM: V2_CLKFX_DIVIDE bit 1 - - DCM: DLL_ENABLE DCM: V2_REG_DLLS bit 17
B16 - - - - - - - - - - - - - - - - - - DCM: V2_REG_DFS bit 0 DCM: V2_CLKFX_DIVIDE bit 0 - - DCM: DFS_ENABLE DCM: V2_REG_DLLS bit 16
B15 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 31 DCM: NON_STOP - - DCM: V2_REG_DLLS bit 15 DCM: FACTORY_JF1 bit 7
B14 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 30 DCM: COIN_WINDOW bit 1 - - DCM: V2_REG_DLLS bit 14 DCM: FACTORY_JF1 bit 6
B13 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 29 DCM: COIN_WINDOW bit 0 - - DCM: V2_REG_DLLS bit 13 DCM: FACTORY_JF1 bit 5
B12 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 28 DCM: V2_VBG_PD bit 1 - - DCM: V2_REG_DLLS bit 12 DCM: FACTORY_JF1 bit 4
B11 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 27 DCM: V2_VBG_PD bit 0 - - DCM: V2_REG_DLLS bit 11 DCM: FACTORY_JF1 bit 3
B10 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 26 DCM: V2_VBG_SEL bit 2 - - DCM: V2_REG_DLLS bit 10 DCM: FACTORY_JF1 bit 2
B9 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 25 DCM: V2_VBG_SEL bit 1 - - DCM: V2_REG_DLLS bit 9 DCM: FACTORY_JF1 bit 1
B8 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 24 DCM: V2_VBG_SEL bit 0 - - DCM: V2_REG_DLLS bit 8 DCM: FACTORY_JF1 bit 0
B7 - - - - - - - - - - - - - - - - - - DCM: V2_REG_COM bit 23 - - DCM: V2_REG_DLLS bit 7 DCM: FACTORY_JF2 bit 7
B6 - - - - - - - - - - - - - - - - - - DCM: CLKFB_IOB DCM: V2_REG_COM bit 22 - - DCM: V2_REG_DLLS bit 6 DCM: FACTORY_JF2 bit 6
B5 - - - - - - - - - - - - - - - - - - DCM: CLKIN_IOB DCM: V2_REG_COM bit 21 - - DCM: V2_REG_DLLS bit 5 DCM: FACTORY_JF2 bit 5
B4 - - - - - - - - - - - - - - - - - - DCM: DESKEW_ADJUST bit 3 DCM: V2_REG_COM bit 20 - - DCM: V2_REG_DLLS bit 4 DCM: FACTORY_JF2 bit 4
B3 - - - - - - - - - - - - - - - - - - DCM: DESKEW_ADJUST bit 2 DCM: V2_REG_COM bit 19 - - DCM: V2_REG_DLLS bit 3 DCM: FACTORY_JF2 bit 3
B2 - - - - - - - - - - - - - - - - - - DCM: DESKEW_ADJUST bit 1 DCM: V2_REG_COM bit 18 - - DCM: V2_REG_DLLS bit 2 DCM: FACTORY_JF2 bit 2
B1 - - - - - - - - - - - - - - - - - - DCM: DESKEW_ADJUST bit 0 DCM: V2_REG_COM bit 17 - - DCM: V2_REG_DLLS bit 1 DCM: FACTORY_JF2 bit 1
B0 - - - - - - - - - - - - - - - - - - DCM: CLKIN_DIVIDE_BY_2 DCM: V2_REG_COM bit 16 - - DCM: V2_REG_DLLS bit 0 DCM: FACTORY_JF2 bit 0
virtex2 DCM_V2P rect TERM
BitFrame
F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - - - - - - - DCM: V2_EN_DUMMY_OSC bit 2 - - - - - - -
B10 - - - - - - - - - - - - - - DCM: ZD2_BY1 - - DCM: RESET_PS_SEL - - - -
B9 - - - - - - - - - - - - - - DCM: EN_DUMMY_OSC_OR_NON_STOP DCM: EN_OSC_COARSE - - - - - -
B8 - - - - - - - - - - - - - - DCM: ZD1_BY1 - - - - - - -
B7 - - - - - - - - - - - - - - DCM: V2_EN_DUMMY_OSC bit 1 - - - - - - -
B6 - - - - - - - - - - - - - - DCM: V2_EN_DUMMY_OSC bit 0 - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - -

Device data

Device data dcm-data

virtex2 device data dcm-data
Device DCM_DESKEW_ADJUST DCM_V2_VBG_PD DCM_V2_VBG_SEL
xc2v40 0b1011 0b01 0b101
xc2v80 0b1011 0b01 0b100
xc2v250 0b1011 0b01 0b100
xc2v500 0b1011 0b01 0b100
xc2v1000 0b1011 0b01 0b101
xq2v1000 0b1011 0b01 0b101
xqr2v1000 0b1011 0b01 0b101
xc2v1500 0b1011 0b01 0b101
xc2v2000 0b1011 0b01 0b101
xc2v3000 0b1100 0b01 0b101
xq2v3000 0b1100 0b01 0b101
xqr2v3000 0b1100 0b01 0b101
xc2v4000 0b1100 0b01 0b101
xc2v6000 0b1100 0b01 0b101
xq2v6000 0b1100 0b01 0b101
xqr2v6000 0b1100 0b01 0b101
xc2v8000 0b1101 0b01 0b101
xc2vp2 0b0110 0b01 0b101
xc2vp4 0b0110 0b01 0b101
xc2vp7 0b0110 0b01 0b101
xc2vp20 0b0110 0b01 0b101
xc2vp30 0b0111 0b01 0b101
xc2vp40 0b0111 0b01 0b101
xq2vp40 0b0111 0b01 0b101
xc2vp50 0b0111 0b01 0b101
xc2vp70 0b0111 0b01 0b101
xq2vp70 0b0111 0b01 0b101
xc2vp100 0b0111 0b01 0b101
xc2vpx20 0b0110 0b01 0b101
xc2vpx70 0b0111 0b01 0b101