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PowerPC 405

TODO: reverse, document

Tile PPC_W

Cells: 48

Bel PPC405

virtex2 PPC_W bel PPC405
PinDirectionWires
APUC405DCDAPUOPinputCELL_W[0].IMUX_G0_DATA[0]
APUC405DCDCRENinputCELL_W[0].IMUX_G1_DATA[0]
APUC405DCDFORCEALGNinputCELL_W[0].IMUX_G2_DATA[0]
APUC405DCDFORCEBESTEERINGinputCELL_W[0].IMUX_G3_DATA[0]
APUC405DCDFPUOPinputCELL_W[1].IMUX_G0_DATA[0]
APUC405DCDGPRWRITEinputCELL_W[1].IMUX_G1_DATA[0]
APUC405DCDLDSTBYTEinputCELL_W[1].IMUX_G2_DATA[0]
APUC405DCDLDSTDWinputCELL_W[1].IMUX_G3_DATA[0]
APUC405DCDLDSTHWinputCELL_W[2].IMUX_G0_DATA[0]
APUC405DCDLDSTQWinputCELL_W[2].IMUX_G1_DATA[0]
APUC405DCDLDSTWDinputCELL_W[2].IMUX_G2_DATA[0]
APUC405DCDLOADinputCELL_W[2].IMUX_G3_DATA[0]
APUC405DCDPRIVOPinputCELL_W[3].IMUX_G0_DATA[0]
APUC405DCDRAENinputCELL_W[3].IMUX_G1_DATA[0]
APUC405DCDRBENinputCELL_W[3].IMUX_G2_DATA[0]
APUC405DCDSTOREinputCELL_W[3].IMUX_G3_DATA[0]
APUC405DCDTRAPBEinputCELL_W[4].IMUX_G0_DATA[0]
APUC405DCDTRAPLEinputCELL_W[4].IMUX_G1_DATA[0]
APUC405DCDUPDATEinputCELL_W[5].IMUX_G0_DATA[0]
APUC405DCDVALIDOPinputCELL_W[5].IMUX_G1_DATA[0]
APUC405DCDXERCAENinputCELL_W[6].IMUX_G0_DATA[0]
APUC405DCDXEROVENinputCELL_W[6].IMUX_G1_DATA[0]
APUC405EXCEPTIONinputCELL_W[7].IMUX_G0_DATA[0]
APUC405EXEBLOCKINGMCOinputCELL_W[7].IMUX_G1_DATA[0]
APUC405EXEBUSYinputCELL_W[8].IMUX_G0_DATA[0]
APUC405EXECR0inputCELL_W[8].IMUX_G1_DATA[0]
APUC405EXECR1inputCELL_W[8].IMUX_G2_DATA[0]
APUC405EXECR2inputCELL_W[9].IMUX_G0_DATA[0]
APUC405EXECR3inputCELL_W[9].IMUX_G1_DATA[0]
APUC405EXECRFIELD0inputCELL_W[9].IMUX_G2_DATA[0]
APUC405EXECRFIELD1inputCELL_W[9].IMUX_G3_DATA[0]
APUC405EXECRFIELD2inputCELL_W[10].IMUX_G0_DATA[0]
APUC405EXELDDEPENDinputCELL_W[10].IMUX_G1_DATA[0]
APUC405EXENONBLOCKINGMCOinputCELL_W[10].IMUX_G2_DATA[0]
APUC405EXERESULT0inputCELL_W[10].IMUX_G3_DATA[0]
APUC405EXERESULT1inputCELL_W[11].IMUX_G0_DATA[0]
APUC405EXERESULT10inputCELL_W[13].IMUX_G1_DATA[0]
APUC405EXERESULT11inputCELL_W[13].IMUX_G2_DATA[0]
APUC405EXERESULT12inputCELL_W[13].IMUX_G3_DATA[0]
APUC405EXERESULT13inputCELL_W[14].IMUX_G0_DATA[0]
APUC405EXERESULT14inputCELL_W[14].IMUX_G1_DATA[0]
APUC405EXERESULT15inputCELL_W[14].IMUX_G2_DATA[0]
APUC405EXERESULT16inputCELL_W[14].IMUX_G3_DATA[0]
APUC405EXERESULT17inputCELL_W[15].IMUX_G0_DATA[0]
APUC405EXERESULT18inputCELL_W[15].IMUX_G1_DATA[0]
APUC405EXERESULT19inputCELL_W[15].IMUX_G2_DATA[0]
APUC405EXERESULT2inputCELL_W[11].IMUX_G1_DATA[0]
APUC405EXERESULT20inputCELL_W[15].IMUX_G3_DATA[0]
APUC405EXERESULT21inputCELL_W[0].IMUX_G0_DATA[1]
APUC405EXERESULT22inputCELL_W[0].IMUX_G1_DATA[1]
APUC405EXERESULT23inputCELL_W[1].IMUX_G0_DATA[1]
APUC405EXERESULT24inputCELL_W[1].IMUX_G1_DATA[1]
APUC405EXERESULT25inputCELL_W[2].IMUX_G0_DATA[1]
APUC405EXERESULT26inputCELL_W[2].IMUX_G1_DATA[1]
APUC405EXERESULT27inputCELL_W[3].IMUX_G0_DATA[1]
APUC405EXERESULT28inputCELL_W[3].IMUX_G1_DATA[1]
APUC405EXERESULT29inputCELL_W[4].IMUX_G2_DATA[0]
APUC405EXERESULT3inputCELL_W[11].IMUX_G2_DATA[0]
APUC405EXERESULT30inputCELL_W[4].IMUX_G3_DATA[0]
APUC405EXERESULT31inputCELL_W[5].IMUX_G2_DATA[0]
APUC405EXERESULT4inputCELL_W[11].IMUX_G3_DATA[0]
APUC405EXERESULT5inputCELL_W[12].IMUX_G0_DATA[0]
APUC405EXERESULT6inputCELL_W[12].IMUX_G1_DATA[0]
APUC405EXERESULT7inputCELL_W[12].IMUX_G2_DATA[0]
APUC405EXERESULT8inputCELL_W[12].IMUX_G3_DATA[0]
APUC405EXERESULT9inputCELL_W[13].IMUX_G0_DATA[0]
APUC405EXEXERCAinputCELL_W[5].IMUX_G3_DATA[0]
APUC405EXEXEROVinputCELL_W[6].IMUX_G2_DATA[0]
APUC405FPUEXCEPTIONinputCELL_W[6].IMUX_G3_DATA[0]
APUC405LWBLDDEPENDinputCELL_W[7].IMUX_G2_DATA[0]
APUC405SLEEPREQinputCELL_W[7].IMUX_G3_DATA[0]
APUC405WBLDDEPENDinputCELL_W[8].IMUX_G3_DATA[0]
BRAMDSOCMCLKinputCELL_N[3].IMUX_CLK[0]
BRAMDSOCMRDDACKinputCELL_N[2].IMUX_G3_DATA[0]
BRAMDSOCMRDDBUS0inputCELL_N[0].IMUX_G0_DATA[0]
BRAMDSOCMRDDBUS1inputCELL_N[0].IMUX_G1_DATA[0]
BRAMDSOCMRDDBUS10inputCELL_N[0].IMUX_G2_DATA[2]
BRAMDSOCMRDDBUS11inputCELL_N[0].IMUX_G3_DATA[2]
BRAMDSOCMRDDBUS12inputCELL_N[0].IMUX_G0_DATA[3]
BRAMDSOCMRDDBUS13inputCELL_N[0].IMUX_G1_DATA[3]
BRAMDSOCMRDDBUS14inputCELL_N[0].IMUX_G2_DATA[3]
BRAMDSOCMRDDBUS15inputCELL_N[0].IMUX_G3_DATA[3]
BRAMDSOCMRDDBUS16inputCELL_N[7].IMUX_G0_DATA[0]
BRAMDSOCMRDDBUS17inputCELL_N[7].IMUX_G1_DATA[0]
BRAMDSOCMRDDBUS18inputCELL_N[7].IMUX_G2_DATA[0]
BRAMDSOCMRDDBUS19inputCELL_N[7].IMUX_G3_DATA[0]
BRAMDSOCMRDDBUS2inputCELL_N[0].IMUX_G2_DATA[0]
BRAMDSOCMRDDBUS20inputCELL_N[7].IMUX_G0_DATA[1]
BRAMDSOCMRDDBUS21inputCELL_N[7].IMUX_G1_DATA[1]
BRAMDSOCMRDDBUS22inputCELL_N[7].IMUX_G2_DATA[1]
BRAMDSOCMRDDBUS23inputCELL_N[7].IMUX_G3_DATA[1]
BRAMDSOCMRDDBUS24inputCELL_N[7].IMUX_G0_DATA[2]
BRAMDSOCMRDDBUS25inputCELL_N[7].IMUX_G1_DATA[2]
BRAMDSOCMRDDBUS26inputCELL_N[7].IMUX_G2_DATA[2]
BRAMDSOCMRDDBUS27inputCELL_N[7].IMUX_G3_DATA[2]
BRAMDSOCMRDDBUS28inputCELL_N[7].IMUX_G0_DATA[3]
BRAMDSOCMRDDBUS29inputCELL_N[7].IMUX_G1_DATA[3]
BRAMDSOCMRDDBUS3inputCELL_N[0].IMUX_G3_DATA[0]
BRAMDSOCMRDDBUS30inputCELL_N[7].IMUX_G2_DATA[3]
BRAMDSOCMRDDBUS31inputCELL_N[7].IMUX_G3_DATA[3]
BRAMDSOCMRDDBUS4inputCELL_N[0].IMUX_G0_DATA[1]
BRAMDSOCMRDDBUS5inputCELL_N[0].IMUX_G1_DATA[1]
BRAMDSOCMRDDBUS6inputCELL_N[0].IMUX_G2_DATA[1]
BRAMDSOCMRDDBUS7inputCELL_N[0].IMUX_G3_DATA[1]
BRAMDSOCMRDDBUS8inputCELL_N[0].IMUX_G0_DATA[2]
BRAMDSOCMRDDBUS9inputCELL_N[0].IMUX_G1_DATA[2]
BRAMISOCMCLKinputCELL_S[4].IMUX_CLK[0]
BRAMISOCMRDDACKinputCELL_S[4].IMUX_G0_DATA[0]
BRAMISOCMRDDBUS0inputCELL_S[0].IMUX_G0_DATA[0]
BRAMISOCMRDDBUS1inputCELL_S[0].IMUX_G1_DATA[0]
BRAMISOCMRDDBUS10inputCELL_S[0].IMUX_G2_DATA[2]
BRAMISOCMRDDBUS11inputCELL_S[0].IMUX_G3_DATA[2]
BRAMISOCMRDDBUS12inputCELL_S[0].IMUX_G0_DATA[3]
BRAMISOCMRDDBUS13inputCELL_S[0].IMUX_G1_DATA[3]
BRAMISOCMRDDBUS14inputCELL_S[0].IMUX_G2_DATA[3]
BRAMISOCMRDDBUS15inputCELL_S[0].IMUX_G3_DATA[3]
BRAMISOCMRDDBUS16inputCELL_S[1].IMUX_G0_DATA[0]
BRAMISOCMRDDBUS17inputCELL_S[1].IMUX_G1_DATA[0]
BRAMISOCMRDDBUS18inputCELL_S[1].IMUX_G2_DATA[0]
BRAMISOCMRDDBUS19inputCELL_S[1].IMUX_G3_DATA[0]
BRAMISOCMRDDBUS2inputCELL_S[0].IMUX_G2_DATA[0]
BRAMISOCMRDDBUS20inputCELL_S[1].IMUX_G0_DATA[1]
BRAMISOCMRDDBUS21inputCELL_S[1].IMUX_G1_DATA[1]
BRAMISOCMRDDBUS22inputCELL_S[1].IMUX_G2_DATA[1]
BRAMISOCMRDDBUS23inputCELL_S[1].IMUX_G3_DATA[1]
BRAMISOCMRDDBUS24inputCELL_S[1].IMUX_G0_DATA[2]
BRAMISOCMRDDBUS25inputCELL_S[1].IMUX_G1_DATA[2]
BRAMISOCMRDDBUS26inputCELL_S[1].IMUX_G2_DATA[2]
BRAMISOCMRDDBUS27inputCELL_S[1].IMUX_G3_DATA[2]
BRAMISOCMRDDBUS28inputCELL_S[1].IMUX_G0_DATA[3]
BRAMISOCMRDDBUS29inputCELL_S[1].IMUX_G1_DATA[3]
BRAMISOCMRDDBUS3inputCELL_S[0].IMUX_G3_DATA[0]
BRAMISOCMRDDBUS30inputCELL_S[1].IMUX_G2_DATA[3]
BRAMISOCMRDDBUS31inputCELL_S[1].IMUX_G3_DATA[3]
BRAMISOCMRDDBUS32inputCELL_S[6].IMUX_G0_DATA[0]
BRAMISOCMRDDBUS33inputCELL_S[6].IMUX_G1_DATA[0]
BRAMISOCMRDDBUS34inputCELL_S[6].IMUX_G2_DATA[0]
BRAMISOCMRDDBUS35inputCELL_S[6].IMUX_G3_DATA[0]
BRAMISOCMRDDBUS36inputCELL_S[6].IMUX_G0_DATA[1]
BRAMISOCMRDDBUS37inputCELL_S[6].IMUX_G1_DATA[1]
BRAMISOCMRDDBUS38inputCELL_S[6].IMUX_G2_DATA[1]
BRAMISOCMRDDBUS39inputCELL_S[6].IMUX_G3_DATA[1]
BRAMISOCMRDDBUS4inputCELL_S[0].IMUX_G0_DATA[1]
BRAMISOCMRDDBUS40inputCELL_S[6].IMUX_G0_DATA[2]
BRAMISOCMRDDBUS41inputCELL_S[6].IMUX_G1_DATA[2]
BRAMISOCMRDDBUS42inputCELL_S[6].IMUX_G2_DATA[2]
BRAMISOCMRDDBUS43inputCELL_S[6].IMUX_G3_DATA[2]
BRAMISOCMRDDBUS44inputCELL_S[6].IMUX_G0_DATA[3]
BRAMISOCMRDDBUS45inputCELL_S[6].IMUX_G1_DATA[3]
BRAMISOCMRDDBUS46inputCELL_S[6].IMUX_G2_DATA[3]
BRAMISOCMRDDBUS47inputCELL_S[6].IMUX_G3_DATA[3]
BRAMISOCMRDDBUS48inputCELL_S[7].IMUX_G0_DATA[0]
BRAMISOCMRDDBUS49inputCELL_S[7].IMUX_G1_DATA[0]
BRAMISOCMRDDBUS5inputCELL_S[0].IMUX_G1_DATA[1]
BRAMISOCMRDDBUS50inputCELL_S[7].IMUX_G2_DATA[0]
BRAMISOCMRDDBUS51inputCELL_S[7].IMUX_G3_DATA[0]
BRAMISOCMRDDBUS52inputCELL_S[7].IMUX_G0_DATA[1]
BRAMISOCMRDDBUS53inputCELL_S[7].IMUX_G1_DATA[1]
BRAMISOCMRDDBUS54inputCELL_S[7].IMUX_G2_DATA[1]
BRAMISOCMRDDBUS55inputCELL_S[7].IMUX_G3_DATA[1]
BRAMISOCMRDDBUS56inputCELL_S[7].IMUX_G0_DATA[2]
BRAMISOCMRDDBUS57inputCELL_S[7].IMUX_G1_DATA[2]
BRAMISOCMRDDBUS58inputCELL_S[7].IMUX_G2_DATA[2]
BRAMISOCMRDDBUS59inputCELL_S[7].IMUX_G3_DATA[2]
BRAMISOCMRDDBUS6inputCELL_S[0].IMUX_G2_DATA[1]
BRAMISOCMRDDBUS60inputCELL_S[7].IMUX_G0_DATA[3]
BRAMISOCMRDDBUS61inputCELL_S[7].IMUX_G1_DATA[3]
BRAMISOCMRDDBUS62inputCELL_S[7].IMUX_G2_DATA[3]
BRAMISOCMRDDBUS63inputCELL_S[7].IMUX_G3_DATA[3]
BRAMISOCMRDDBUS7inputCELL_S[0].IMUX_G3_DATA[1]
BRAMISOCMRDDBUS8inputCELL_S[0].IMUX_G0_DATA[2]
BRAMISOCMRDDBUS9inputCELL_S[0].IMUX_G1_DATA[2]
C405APUDCDFULLoutputCELL_W[0].OUT_FAN_TMIN[0]
C405APUDCDHOLDoutputCELL_W[0].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION0outputCELL_W[0].OUT_FAN_TMIN[2]
C405APUDCDINSTRUCTION1outputCELL_W[0].OUT_FAN_TMIN[3]
C405APUDCDINSTRUCTION10outputCELL_W[3].OUT_FAN_TMIN[0]
C405APUDCDINSTRUCTION11outputCELL_W[3].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION12outputCELL_W[3].OUT_FAN_TMIN[2]
C405APUDCDINSTRUCTION13outputCELL_W[3].OUT_FAN_TMIN[3]
C405APUDCDINSTRUCTION14outputCELL_W[4].OUT_FAN_TMIN[0]
C405APUDCDINSTRUCTION15outputCELL_W[4].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION16outputCELL_W[4].OUT_FAN_TMIN[2]
C405APUDCDINSTRUCTION17outputCELL_W[4].OUT_FAN_TMIN[3]
C405APUDCDINSTRUCTION18outputCELL_W[5].OUT_FAN_TMIN[0]
C405APUDCDINSTRUCTION19outputCELL_W[5].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION2outputCELL_W[1].OUT_FAN_TMIN[0]
C405APUDCDINSTRUCTION20outputCELL_W[5].OUT_FAN_TMIN[2]
C405APUDCDINSTRUCTION21outputCELL_W[5].OUT_FAN_TMIN[3]
C405APUDCDINSTRUCTION22outputCELL_W[6].OUT_FAN_TMIN[0]
C405APUDCDINSTRUCTION23outputCELL_W[6].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION24outputCELL_W[6].OUT_FAN_TMIN[2]
C405APUDCDINSTRUCTION25outputCELL_W[6].OUT_FAN_TMIN[3]
C405APUDCDINSTRUCTION26outputCELL_W[7].OUT_FAN_TMIN[0]
C405APUDCDINSTRUCTION27outputCELL_W[7].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION28outputCELL_W[7].OUT_FAN_TMIN[2]
C405APUDCDINSTRUCTION29outputCELL_W[7].OUT_FAN_TMIN[3]
C405APUDCDINSTRUCTION3outputCELL_W[1].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION30outputCELL_W[8].OUT_FAN_TMIN[0]
C405APUDCDINSTRUCTION31outputCELL_W[8].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION4outputCELL_W[1].OUT_FAN_TMIN[2]
C405APUDCDINSTRUCTION5outputCELL_W[1].OUT_FAN_TMIN[3]
C405APUDCDINSTRUCTION6outputCELL_W[2].OUT_FAN_TMIN[0]
C405APUDCDINSTRUCTION7outputCELL_W[2].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION8outputCELL_W[2].OUT_FAN_TMIN[2]
C405APUDCDINSTRUCTION9outputCELL_W[2].OUT_FAN_TMIN[3]
C405APUEXEFLUSHoutputCELL_W[8].OUT_FAN_TMIN[2]
C405APUEXEHOLDoutputCELL_W[8].OUT_FAN_TMIN[3]
C405APUEXELOADDBUS0outputCELL_W[9].OUT_FAN_TMIN[0]
C405APUEXELOADDBUS1outputCELL_W[9].OUT_FAN_TMIN[1]
C405APUEXELOADDBUS10outputCELL_W[11].OUT_FAN_TMIN[2]
C405APUEXELOADDBUS11outputCELL_W[11].OUT_FAN_TMIN[3]
C405APUEXELOADDBUS12outputCELL_W[12].OUT_FAN_TMIN[0]
C405APUEXELOADDBUS13outputCELL_W[12].OUT_FAN_TMIN[1]
C405APUEXELOADDBUS14outputCELL_W[12].OUT_FAN_TMIN[2]
C405APUEXELOADDBUS15outputCELL_W[12].OUT_FAN_TMIN[3]
C405APUEXELOADDBUS16outputCELL_W[13].OUT_FAN_TMIN[0]
C405APUEXELOADDBUS17outputCELL_W[13].OUT_FAN_TMIN[1]
C405APUEXELOADDBUS18outputCELL_W[13].OUT_FAN_TMIN[2]
C405APUEXELOADDBUS19outputCELL_W[13].OUT_FAN_TMIN[3]
C405APUEXELOADDBUS2outputCELL_W[9].OUT_FAN_TMIN[2]
C405APUEXELOADDBUS20outputCELL_W[14].OUT_FAN_TMIN[0]
C405APUEXELOADDBUS21outputCELL_W[14].OUT_FAN_TMIN[1]
C405APUEXELOADDBUS22outputCELL_W[14].OUT_FAN_TMIN[2]
C405APUEXELOADDBUS23outputCELL_W[14].OUT_FAN_TMIN[3]
C405APUEXELOADDBUS24outputCELL_W[15].OUT_FAN_TMIN[0]
C405APUEXELOADDBUS25outputCELL_W[15].OUT_FAN_TMIN[1]
C405APUEXELOADDBUS26outputCELL_W[15].OUT_FAN_TMIN[2]
C405APUEXELOADDBUS27outputCELL_W[15].OUT_FAN_TMIN[3]
C405APUEXELOADDBUS28outputCELL_W[0].OUT_FAN_TMIN[4]
C405APUEXELOADDBUS29outputCELL_W[0].OUT_FAN_TMIN[5]
C405APUEXELOADDBUS3outputCELL_W[9].OUT_FAN_TMIN[3]
C405APUEXELOADDBUS30outputCELL_W[1].OUT_FAN_TMIN[4]
C405APUEXELOADDBUS31outputCELL_W[1].OUT_FAN_TMIN[5]
C405APUEXELOADDBUS4outputCELL_W[10].OUT_FAN_TMIN[0]
C405APUEXELOADDBUS5outputCELL_W[10].OUT_FAN_TMIN[1]
C405APUEXELOADDBUS6outputCELL_W[10].OUT_FAN_TMIN[2]
C405APUEXELOADDBUS7outputCELL_W[10].OUT_FAN_TMIN[3]
C405APUEXELOADDBUS8outputCELL_W[11].OUT_FAN_TMIN[0]
C405APUEXELOADDBUS9outputCELL_W[11].OUT_FAN_TMIN[1]
C405APUEXELOADDVALIDoutputCELL_W[2].OUT_FAN_TMIN[4]
C405APUEXERADATA0outputCELL_W[2].OUT_FAN_TMIN[5]
C405APUEXERADATA1outputCELL_W[3].OUT_FAN_TMIN[4]
C405APUEXERADATA10outputCELL_W[7].OUT_FAN_TMIN[5]
C405APUEXERADATA11outputCELL_W[8].OUT_FAN_TMIN[4]
C405APUEXERADATA12outputCELL_W[8].OUT_FAN_TMIN[5]
C405APUEXERADATA13outputCELL_W[9].OUT_FAN_TMIN[4]
C405APUEXERADATA14outputCELL_W[9].OUT_FAN_TMIN[5]
C405APUEXERADATA15outputCELL_W[10].OUT_FAN_TMIN[4]
C405APUEXERADATA16outputCELL_W[10].OUT_FAN_TMIN[5]
C405APUEXERADATA17outputCELL_W[11].OUT_FAN_TMIN[4]
C405APUEXERADATA18outputCELL_W[11].OUT_FAN_TMIN[5]
C405APUEXERADATA19outputCELL_W[12].OUT_FAN_TMIN[4]
C405APUEXERADATA2outputCELL_W[3].OUT_FAN_TMIN[5]
C405APUEXERADATA20outputCELL_W[12].OUT_FAN_TMIN[5]
C405APUEXERADATA21outputCELL_W[13].OUT_FAN_TMIN[4]
C405APUEXERADATA22outputCELL_W[13].OUT_FAN_TMIN[5]
C405APUEXERADATA23outputCELL_W[14].OUT_FAN_TMIN[4]
C405APUEXERADATA24outputCELL_W[14].OUT_FAN_TMIN[5]
C405APUEXERADATA25outputCELL_W[15].OUT_FAN_TMIN[4]
C405APUEXERADATA26outputCELL_W[15].OUT_FAN_TMIN[5]
C405APUEXERADATA27outputCELL_W[0].OUT_FAN_TMIN[6]
C405APUEXERADATA28outputCELL_W[0].OUT_FAN_TMIN[7]
C405APUEXERADATA29outputCELL_W[1].OUT_FAN_TMIN[6]
C405APUEXERADATA3outputCELL_W[4].OUT_FAN_TMIN[4]
C405APUEXERADATA30outputCELL_W[1].OUT_FAN_TMIN[7]
C405APUEXERADATA31outputCELL_W[2].OUT_FAN_TMIN[6]
C405APUEXERADATA4outputCELL_W[4].OUT_FAN_TMIN[5]
C405APUEXERADATA5outputCELL_W[5].OUT_FAN_TMIN[4]
C405APUEXERADATA6outputCELL_W[5].OUT_FAN_TMIN[5]
C405APUEXERADATA7outputCELL_W[6].OUT_FAN_TMIN[4]
C405APUEXERADATA8outputCELL_W[6].OUT_FAN_TMIN[5]
C405APUEXERADATA9outputCELL_W[7].OUT_FAN_TMIN[4]
C405APUEXERBDATA0outputCELL_W[2].OUT_FAN_TMIN[7]
C405APUEXERBDATA1outputCELL_W[3].OUT_FAN_TMIN[6]
C405APUEXERBDATA10outputCELL_W[7].OUT_FAN_TMIN[7]
C405APUEXERBDATA11outputCELL_W[8].OUT_FAN_TMIN[6]
C405APUEXERBDATA12outputCELL_W[8].OUT_FAN_TMIN[7]
C405APUEXERBDATA13outputCELL_W[9].OUT_FAN_TMIN[6]
C405APUEXERBDATA14outputCELL_W[9].OUT_FAN_TMIN[7]
C405APUEXERBDATA15outputCELL_W[10].OUT_FAN_TMIN[6]
C405APUEXERBDATA16outputCELL_W[10].OUT_FAN_TMIN[7]
C405APUEXERBDATA17outputCELL_W[11].OUT_FAN_TMIN[6]
C405APUEXERBDATA18outputCELL_W[11].OUT_FAN_TMIN[7]
C405APUEXERBDATA19outputCELL_W[12].OUT_FAN_TMIN[6]
C405APUEXERBDATA2outputCELL_W[3].OUT_FAN_TMIN[7]
C405APUEXERBDATA20outputCELL_W[12].OUT_FAN_TMIN[7]
C405APUEXERBDATA21outputCELL_W[13].OUT_FAN_TMIN[6]
C405APUEXERBDATA22outputCELL_W[13].OUT_FAN_TMIN[7]
C405APUEXERBDATA23outputCELL_W[14].OUT_FAN_TMIN[6]
C405APUEXERBDATA24outputCELL_W[14].OUT_FAN_TMIN[7]
C405APUEXERBDATA25outputCELL_W[15].OUT_FAN_TMIN[6]
C405APUEXERBDATA26outputCELL_W[15].OUT_FAN_TMIN[7]
C405APUEXERBDATA27outputCELL_W[0].OUT_SEC_TMIN[15]
C405APUEXERBDATA28outputCELL_W[0].OUT_SEC_TMIN[14]
C405APUEXERBDATA29outputCELL_W[1].OUT_SEC_TMIN[15]
C405APUEXERBDATA3outputCELL_W[4].OUT_FAN_TMIN[6]
C405APUEXERBDATA30outputCELL_W[1].OUT_SEC_TMIN[14]
C405APUEXERBDATA31outputCELL_W[2].OUT_SEC_TMIN[15]
C405APUEXERBDATA4outputCELL_W[4].OUT_FAN_TMIN[7]
C405APUEXERBDATA5outputCELL_W[5].OUT_FAN_TMIN[6]
C405APUEXERBDATA6outputCELL_W[5].OUT_FAN_TMIN[7]
C405APUEXERBDATA7outputCELL_W[6].OUT_FAN_TMIN[6]
C405APUEXERBDATA8outputCELL_W[6].OUT_FAN_TMIN[7]
C405APUEXERBDATA9outputCELL_W[7].OUT_FAN_TMIN[6]
C405APUEXEWDCNT0outputCELL_W[2].OUT_SEC_TMIN[14]
C405APUEXEWDCNT1outputCELL_W[3].OUT_SEC_TMIN[15]
C405APUMSRFE0outputCELL_W[3].OUT_SEC_TMIN[14]
C405APUMSRFE1outputCELL_W[4].OUT_SEC_TMIN[15]
C405APUWBBYTEEN0outputCELL_W[4].OUT_SEC_TMIN[14]
C405APUWBBYTEEN1outputCELL_W[5].OUT_SEC_TMIN[15]
C405APUWBBYTEEN2outputCELL_W[5].OUT_SEC_TMIN[14]
C405APUWBBYTEEN3outputCELL_W[6].OUT_SEC_TMIN[15]
C405APUWBENDIANoutputCELL_W[6].OUT_SEC_TMIN[14]
C405APUWBFLUSHoutputCELL_W[7].OUT_SEC_TMIN[15]
C405APUWBHOLDoutputCELL_W[7].OUT_SEC_TMIN[14]
C405APUXERCAoutputCELL_W[8].OUT_SEC_TMIN[15]
C405CPMCORESLEEPREQoutputCELL_E[14].OUT_FAN_TMIN[5]
C405CPMMSRCEoutputCELL_E[15].OUT_FAN_TMIN[4]
C405CPMMSREEoutputCELL_E[15].OUT_FAN_TMIN[5]
C405CPMTIMERIRQoutputCELL_E[0].OUT_FAN_TMIN[6]
C405CPMTIMERRESETREQoutputCELL_E[0].OUT_FAN_TMIN[7]
C405DBGLOADDATAONAPUDBUSoutputCELL_E[14].OUT_FAN_TMIN[7]
C405DBGMSRWEoutputCELL_E[15].OUT_FAN_TMIN[6]
C405DBGSTOPACKoutputCELL_E[15].OUT_FAN_TMIN[7]
C405DBGWBCOMPLETEoutputCELL_E[0].OUT_SEC_TMIN[15]
C405DBGWBFULLoutputCELL_E[0].OUT_SEC_TMIN[14]
C405DBGWBIAR0outputCELL_E[1].OUT_SEC_TMIN[14]
C405DBGWBIAR1outputCELL_E[13].OUT_SEC_TMIN[15]
C405DBGWBIAR10outputCELL_E[14].OUT_SEC_TMIN[13]
C405DBGWBIAR11outputCELL_E[2].OUT_FAN_TMIN[6]
C405DBGWBIAR12outputCELL_E[2].OUT_FAN_TMIN[7]
C405DBGWBIAR13outputCELL_E[3].OUT_SEC_TMIN[15]
C405DBGWBIAR14outputCELL_E[3].OUT_SEC_TMIN[14]
C405DBGWBIAR15outputCELL_E[3].OUT_SEC_TMIN[13]
C405DBGWBIAR16outputCELL_E[3].OUT_SEC_TMIN[12]
C405DBGWBIAR17outputCELL_E[4].OUT_SEC_TMIN[13]
C405DBGWBIAR18outputCELL_E[4].OUT_SEC_TMIN[12]
C405DBGWBIAR19outputCELL_E[12].OUT_FAN_TMIN[7]
C405DBGWBIAR2outputCELL_E[13].OUT_SEC_TMIN[14]
C405DBGWBIAR20outputCELL_E[15].OUT_SEC_TMIN[13]
C405DBGWBIAR21outputCELL_E[0].OUT_SEC_TMIN[12]
C405DBGWBIAR22outputCELL_E[1].OUT_SEC_TMIN[12]
C405DBGWBIAR23outputCELL_E[13].OUT_SEC_TMIN[12]
C405DBGWBIAR24outputCELL_E[14].OUT_SEC_TMIN[12]
C405DBGWBIAR25outputCELL_E[15].OUT_SEC_TMIN[12]
C405DBGWBIAR26outputCELL_E[0].OUT_SEC_TMIN[11]
C405DBGWBIAR27outputCELL_E[1].OUT_SEC_TMIN[11]
C405DBGWBIAR28outputCELL_E[2].OUT_SEC_TMIN[11]
C405DBGWBIAR29outputCELL_E[3].OUT_SEC_TMIN[11]
C405DBGWBIAR3outputCELL_E[14].OUT_SEC_TMIN[15]
C405DBGWBIAR4outputCELL_E[14].OUT_SEC_TMIN[14]
C405DBGWBIAR5outputCELL_E[15].OUT_SEC_TMIN[15]
C405DBGWBIAR6outputCELL_E[15].OUT_SEC_TMIN[14]
C405DBGWBIAR7outputCELL_E[0].OUT_SEC_TMIN[13]
C405DBGWBIAR8outputCELL_E[1].OUT_SEC_TMIN[13]
C405DBGWBIAR9outputCELL_E[13].OUT_SEC_TMIN[13]
C405DCRABUS0outputCELL_W[8].OUT_SEC_TMIN[14]
C405DCRABUS1outputCELL_W[9].OUT_SEC_TMIN[15]
C405DCRABUS2outputCELL_W[9].OUT_SEC_TMIN[14]
C405DCRABUS3outputCELL_W[10].OUT_SEC_TMIN[15]
C405DCRABUS4outputCELL_W[10].OUT_SEC_TMIN[14]
C405DCRABUS5outputCELL_W[11].OUT_SEC_TMIN[15]
C405DCRABUS6outputCELL_W[11].OUT_SEC_TMIN[14]
C405DCRABUS7outputCELL_W[12].OUT_SEC_TMIN[15]
C405DCRABUS8outputCELL_W[12].OUT_SEC_TMIN[14]
C405DCRABUS9outputCELL_W[13].OUT_SEC_TMIN[15]
C405DCRDBUSOUT0outputCELL_W[13].OUT_SEC_TMIN[14]
C405DCRDBUSOUT1outputCELL_W[14].OUT_SEC_TMIN[15]
C405DCRDBUSOUT10outputCELL_W[5].OUT_SEC_TMIN[13]
C405DCRDBUSOUT11outputCELL_W[6].OUT_SEC_TMIN[13]
C405DCRDBUSOUT12outputCELL_W[7].OUT_SEC_TMIN[13]
C405DCRDBUSOUT13outputCELL_W[8].OUT_SEC_TMIN[13]
C405DCRDBUSOUT14outputCELL_W[9].OUT_SEC_TMIN[13]
C405DCRDBUSOUT15outputCELL_W[10].OUT_SEC_TMIN[13]
C405DCRDBUSOUT16outputCELL_W[11].OUT_SEC_TMIN[13]
C405DCRDBUSOUT17outputCELL_W[12].OUT_SEC_TMIN[13]
C405DCRDBUSOUT18outputCELL_W[13].OUT_SEC_TMIN[13]
C405DCRDBUSOUT19outputCELL_W[14].OUT_SEC_TMIN[13]
C405DCRDBUSOUT2outputCELL_W[14].OUT_SEC_TMIN[14]
C405DCRDBUSOUT20outputCELL_W[15].OUT_SEC_TMIN[13]
C405DCRDBUSOUT21outputCELL_W[0].OUT_SEC_TMIN[12]
C405DCRDBUSOUT22outputCELL_W[1].OUT_SEC_TMIN[12]
C405DCRDBUSOUT23outputCELL_W[2].OUT_SEC_TMIN[12]
C405DCRDBUSOUT24outputCELL_W[3].OUT_SEC_TMIN[12]
C405DCRDBUSOUT25outputCELL_W[4].OUT_SEC_TMIN[12]
C405DCRDBUSOUT26outputCELL_W[5].OUT_SEC_TMIN[12]
C405DCRDBUSOUT27outputCELL_W[6].OUT_SEC_TMIN[12]
C405DCRDBUSOUT28outputCELL_W[7].OUT_SEC_TMIN[12]
C405DCRDBUSOUT29outputCELL_W[8].OUT_SEC_TMIN[12]
C405DCRDBUSOUT3outputCELL_W[15].OUT_SEC_TMIN[15]
C405DCRDBUSOUT30outputCELL_W[9].OUT_SEC_TMIN[12]
C405DCRDBUSOUT31outputCELL_W[10].OUT_SEC_TMIN[12]
C405DCRDBUSOUT4outputCELL_W[15].OUT_SEC_TMIN[14]
C405DCRDBUSOUT5outputCELL_W[0].OUT_SEC_TMIN[13]
C405DCRDBUSOUT6outputCELL_W[1].OUT_SEC_TMIN[13]
C405DCRDBUSOUT7outputCELL_W[2].OUT_SEC_TMIN[13]
C405DCRDBUSOUT8outputCELL_W[3].OUT_SEC_TMIN[13]
C405DCRDBUSOUT9outputCELL_W[4].OUT_SEC_TMIN[13]
C405DCRREADoutputCELL_W[11].OUT_SEC_TMIN[12]
C405DCRWRITEoutputCELL_W[12].OUT_SEC_TMIN[12]
C405DSOCMCACHEABLEoutputCELL_S[0].OUT_TEST[6]
C405DSOCMGUARDEDoutputCELL_S[1].OUT_TEST[0]
C405DSOCMSTRINGMULTIPLEoutputCELL_S[1].OUT_TEST[2]
C405DSOCMU0ATTRoutputCELL_S[2].OUT_TEST[2]
C405ISOCMCACHEABLEoutputCELL_S[7].OUT_SEC_TMIN[10]
C405ISOCMCONTEXTSYNCoutputCELL_S[7].OUT_SEC_TMIN[9]
C405ISOCMU0ATTRoutputCELL_S[0].OUT_TEST[4]
C405JTGCAPTUREDRoutputCELL_N[4].OUT_SEC_TMIN[14]
C405JTGEXTESToutputCELL_N[7].OUT_SEC_TMIN[15]
C405JTGPGMOUToutputCELL_N[7].OUT_SEC_TMIN[14]
C405JTGSHIFTDRoutputCELL_N[0].OUT_SEC_TMIN[13]
C405JTGTDOoutputCELL_N[1].OUT_SEC_TMIN[13]
C405JTGTDOENoutputCELL_N[2].OUT_SEC_TMIN[13]
C405JTGUPDATEDRoutputCELL_N[3].OUT_SEC_TMIN[13]
C405LSSDDIAGABISTDONEoutputCELL_S[1].OUT_SEC_TMIN[9]
C405LSSDDIAGOUToutputCELL_S[1].OUT_SEC_TMIN[8]
C405LSSDSCANOUT0outputCELL_S[2].OUT_SEC_TMIN[8]
C405LSSDSCANOUT1outputCELL_S[2].OUT_TEST[0]
C405LSSDSCANOUT2outputCELL_S[3].OUT_SEC_TMIN[11]
C405LSSDSCANOUT3outputCELL_S[3].OUT_SEC_TMIN[10]
C405LSSDSCANOUT4outputCELL_S[4].OUT_SEC_TMIN[11]
C405LSSDSCANOUT5outputCELL_S[4].OUT_SEC_TMIN[10]
C405LSSDSCANOUT6outputCELL_S[5].OUT_SEC_TMIN[11]
C405LSSDSCANOUT7outputCELL_S[5].OUT_SEC_TMIN[10]
C405LSSDSCANOUT8outputCELL_S[6].OUT_TEST[0]
C405LSSDSCANOUT9outputCELL_S[6].OUT_TEST[2]
C405PLBDCUABORToutputCELL_E[1].OUT_FAN_TMIN[7]
C405PLBDCUABUS0outputCELL_E[11].OUT_FAN_TMIN[4]
C405PLBDCUABUS1outputCELL_E[11].OUT_FAN_TMIN[5]
C405PLBDCUABUS10outputCELL_E[9].OUT_FAN_TMIN[6]
C405PLBDCUABUS11outputCELL_E[9].OUT_FAN_TMIN[7]
C405PLBDCUABUS12outputCELL_E[8].OUT_FAN_TMIN[4]
C405PLBDCUABUS13outputCELL_E[8].OUT_FAN_TMIN[5]
C405PLBDCUABUS14outputCELL_E[8].OUT_FAN_TMIN[6]
C405PLBDCUABUS15outputCELL_E[8].OUT_FAN_TMIN[7]
C405PLBDCUABUS16outputCELL_E[7].OUT_FAN_TMIN[4]
C405PLBDCUABUS17outputCELL_E[7].OUT_FAN_TMIN[5]
C405PLBDCUABUS18outputCELL_E[7].OUT_FAN_TMIN[6]
C405PLBDCUABUS19outputCELL_E[7].OUT_FAN_TMIN[7]
C405PLBDCUABUS2outputCELL_E[11].OUT_FAN_TMIN[6]
C405PLBDCUABUS20outputCELL_E[6].OUT_FAN_TMIN[4]
C405PLBDCUABUS21outputCELL_E[6].OUT_FAN_TMIN[5]
C405PLBDCUABUS22outputCELL_E[6].OUT_FAN_TMIN[6]
C405PLBDCUABUS23outputCELL_E[6].OUT_FAN_TMIN[7]
C405PLBDCUABUS24outputCELL_E[5].OUT_FAN_TMIN[4]
C405PLBDCUABUS25outputCELL_E[5].OUT_FAN_TMIN[5]
C405PLBDCUABUS26outputCELL_E[5].OUT_FAN_TMIN[6]
C405PLBDCUABUS27outputCELL_E[5].OUT_FAN_TMIN[7]
C405PLBDCUABUS28outputCELL_E[4].OUT_FAN_TMIN[4]
C405PLBDCUABUS29outputCELL_E[4].OUT_FAN_TMIN[5]
C405PLBDCUABUS3outputCELL_E[11].OUT_FAN_TMIN[7]
C405PLBDCUABUS30outputCELL_E[4].OUT_FAN_TMIN[6]
C405PLBDCUABUS31outputCELL_E[4].OUT_FAN_TMIN[7]
C405PLBDCUABUS4outputCELL_E[10].OUT_FAN_TMIN[4]
C405PLBDCUABUS5outputCELL_E[10].OUT_FAN_TMIN[5]
C405PLBDCUABUS6outputCELL_E[10].OUT_FAN_TMIN[6]
C405PLBDCUABUS7outputCELL_E[10].OUT_FAN_TMIN[7]
C405PLBDCUABUS8outputCELL_E[9].OUT_FAN_TMIN[4]
C405PLBDCUABUS9outputCELL_E[9].OUT_FAN_TMIN[5]
C405PLBDCUBE0outputCELL_E[13].OUT_FAN_TMIN[4]
C405PLBDCUBE1outputCELL_E[13].OUT_FAN_TMIN[5]
C405PLBDCUBE2outputCELL_E[13].OUT_FAN_TMIN[6]
C405PLBDCUBE3outputCELL_E[13].OUT_FAN_TMIN[7]
C405PLBDCUBE4outputCELL_E[3].OUT_FAN_TMIN[4]
C405PLBDCUBE5outputCELL_E[3].OUT_FAN_TMIN[5]
C405PLBDCUBE6outputCELL_E[3].OUT_FAN_TMIN[6]
C405PLBDCUBE7outputCELL_E[3].OUT_FAN_TMIN[7]
C405PLBDCUCACHEABLEoutputCELL_E[12].OUT_FAN_TMIN[6]
C405PLBDCUGUARDEDoutputCELL_E[2].OUT_FAN_TMIN[4]
C405PLBDCUPRIORITY0outputCELL_E[1].OUT_FAN_TMIN[5]
C405PLBDCUPRIORITY1outputCELL_E[1].OUT_FAN_TMIN[6]
C405PLBDCUREQUESToutputCELL_E[1].OUT_FAN_TMIN[4]
C405PLBDCURNWoutputCELL_E[1].OUT_SEC_TMIN[15]
C405PLBDCUSIZE2outputCELL_E[12].OUT_FAN_TMIN[4]
C405PLBDCUU0ATTRoutputCELL_E[12].OUT_FAN_TMIN[5]
C405PLBDCUWRDBUS0outputCELL_E[15].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS1outputCELL_E[15].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS10outputCELL_E[13].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS11outputCELL_E[13].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS12outputCELL_E[12].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS13outputCELL_E[12].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS14outputCELL_E[12].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS15outputCELL_E[12].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS16outputCELL_E[11].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS17outputCELL_E[11].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS18outputCELL_E[11].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS19outputCELL_E[11].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS2outputCELL_E[15].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS20outputCELL_E[10].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS21outputCELL_E[10].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS22outputCELL_E[10].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS23outputCELL_E[10].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS24outputCELL_E[9].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS25outputCELL_E[9].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS26outputCELL_E[9].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS27outputCELL_E[9].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS28outputCELL_E[8].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS29outputCELL_E[8].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS3outputCELL_E[15].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS30outputCELL_E[8].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS31outputCELL_E[8].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS32outputCELL_E[7].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS33outputCELL_E[7].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS34outputCELL_E[7].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS35outputCELL_E[7].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS36outputCELL_E[6].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS37outputCELL_E[6].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS38outputCELL_E[6].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS39outputCELL_E[6].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS4outputCELL_E[14].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS40outputCELL_E[5].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS41outputCELL_E[5].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS42outputCELL_E[5].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS43outputCELL_E[5].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS44outputCELL_E[4].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS45outputCELL_E[4].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS46outputCELL_E[4].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS47outputCELL_E[4].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS48outputCELL_E[3].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS49outputCELL_E[3].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS5outputCELL_E[14].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS50outputCELL_E[3].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS51outputCELL_E[3].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS52outputCELL_E[2].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS53outputCELL_E[2].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS54outputCELL_E[2].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS55outputCELL_E[2].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS56outputCELL_E[1].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS57outputCELL_E[1].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS58outputCELL_E[1].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS59outputCELL_E[1].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS6outputCELL_E[14].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS60outputCELL_E[0].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS61outputCELL_E[0].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS62outputCELL_E[0].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS63outputCELL_E[0].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS7outputCELL_E[14].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS8outputCELL_E[13].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS9outputCELL_E[13].OUT_FAN_TMIN[1]
C405PLBDCUWRITETHRUoutputCELL_E[2].OUT_FAN_TMIN[5]
C405PLBICUABORToutputCELL_E[2].OUT_SEC_TMIN[12]
C405PLBICUABUS0outputCELL_E[11].OUT_SEC_TMIN[15]
C405PLBICUABUS1outputCELL_E[11].OUT_SEC_TMIN[14]
C405PLBICUABUS10outputCELL_E[9].OUT_SEC_TMIN[13]
C405PLBICUABUS11outputCELL_E[9].OUT_SEC_TMIN[12]
C405PLBICUABUS12outputCELL_E[8].OUT_SEC_TMIN[15]
C405PLBICUABUS13outputCELL_E[8].OUT_SEC_TMIN[14]
C405PLBICUABUS14outputCELL_E[8].OUT_SEC_TMIN[13]
C405PLBICUABUS15outputCELL_E[8].OUT_SEC_TMIN[12]
C405PLBICUABUS16outputCELL_E[7].OUT_SEC_TMIN[15]
C405PLBICUABUS17outputCELL_E[7].OUT_SEC_TMIN[14]
C405PLBICUABUS18outputCELL_E[7].OUT_SEC_TMIN[13]
C405PLBICUABUS19outputCELL_E[7].OUT_SEC_TMIN[12]
C405PLBICUABUS2outputCELL_E[11].OUT_SEC_TMIN[13]
C405PLBICUABUS20outputCELL_E[6].OUT_SEC_TMIN[15]
C405PLBICUABUS21outputCELL_E[6].OUT_SEC_TMIN[14]
C405PLBICUABUS22outputCELL_E[6].OUT_SEC_TMIN[13]
C405PLBICUABUS23outputCELL_E[6].OUT_SEC_TMIN[12]
C405PLBICUABUS24outputCELL_E[5].OUT_SEC_TMIN[15]
C405PLBICUABUS25outputCELL_E[5].OUT_SEC_TMIN[14]
C405PLBICUABUS26outputCELL_E[5].OUT_SEC_TMIN[13]
C405PLBICUABUS27outputCELL_E[5].OUT_SEC_TMIN[12]
C405PLBICUABUS28outputCELL_E[4].OUT_SEC_TMIN[15]
C405PLBICUABUS29outputCELL_E[4].OUT_SEC_TMIN[14]
C405PLBICUABUS3outputCELL_E[11].OUT_SEC_TMIN[12]
C405PLBICUABUS4outputCELL_E[10].OUT_SEC_TMIN[15]
C405PLBICUABUS5outputCELL_E[10].OUT_SEC_TMIN[14]
C405PLBICUABUS6outputCELL_E[10].OUT_SEC_TMIN[13]
C405PLBICUABUS7outputCELL_E[10].OUT_SEC_TMIN[12]
C405PLBICUABUS8outputCELL_E[9].OUT_SEC_TMIN[15]
C405PLBICUABUS9outputCELL_E[9].OUT_SEC_TMIN[14]
C405PLBICUCACHEABLEoutputCELL_E[12].OUT_SEC_TMIN[12]
C405PLBICUPRIORITY0outputCELL_E[2].OUT_SEC_TMIN[14]
C405PLBICUPRIORITY1outputCELL_E[2].OUT_SEC_TMIN[13]
C405PLBICUREQUESToutputCELL_E[2].OUT_SEC_TMIN[15]
C405PLBICUSIZE2outputCELL_E[12].OUT_SEC_TMIN[15]
C405PLBICUSIZE3outputCELL_E[12].OUT_SEC_TMIN[14]
C405PLBICUU0ATTRoutputCELL_E[12].OUT_SEC_TMIN[13]
C405RSTCHIPRESETREQoutputCELL_E[0].OUT_FAN_TMIN[4]
C405RSTCORERESETREQoutputCELL_E[0].OUT_FAN_TMIN[5]
C405RSTSYSRESETREQoutputCELL_E[14].OUT_FAN_TMIN[4]
C405TRCCYCLEoutputCELL_N[7].OUT_FAN_TMIN[0]
C405TRCEVENEXECUTIONSTATUS0outputCELL_N[7].OUT_FAN_TMIN[1]
C405TRCEVENEXECUTIONSTATUS1outputCELL_N[7].OUT_FAN_TMIN[2]
C405TRCODDEXECUTIONSTATUS0outputCELL_N[7].OUT_FAN_TMIN[3]
C405TRCODDEXECUTIONSTATUS1outputCELL_N[0].OUT_FAN_TMIN[4]
C405TRCTRACESTATUS0outputCELL_N[0].OUT_FAN_TMIN[5]
C405TRCTRACESTATUS1outputCELL_N[7].OUT_FAN_TMIN[4]
C405TRCTRACESTATUS2outputCELL_N[7].OUT_FAN_TMIN[5]
C405TRCTRACESTATUS3outputCELL_N[0].OUT_FAN_TMIN[6]
C405TRCTRIGGEREVENTOUToutputCELL_N[0].OUT_FAN_TMIN[7]
C405TRCTRIGGEREVENTTYPE0outputCELL_N[7].OUT_FAN_TMIN[6]
C405TRCTRIGGEREVENTTYPE1outputCELL_N[7].OUT_FAN_TMIN[7]
C405TRCTRIGGEREVENTTYPE10outputCELL_N[4].OUT_SEC_TMIN[15]
C405TRCTRIGGEREVENTTYPE2outputCELL_N[0].OUT_SEC_TMIN[15]
C405TRCTRIGGEREVENTTYPE3outputCELL_N[0].OUT_SEC_TMIN[14]
C405TRCTRIGGEREVENTTYPE4outputCELL_N[1].OUT_SEC_TMIN[15]
C405TRCTRIGGEREVENTTYPE5outputCELL_N[1].OUT_SEC_TMIN[14]
C405TRCTRIGGEREVENTTYPE6outputCELL_N[2].OUT_SEC_TMIN[15]
C405TRCTRIGGEREVENTTYPE7outputCELL_N[2].OUT_SEC_TMIN[14]
C405TRCTRIGGEREVENTTYPE8outputCELL_N[3].OUT_SEC_TMIN[15]
C405TRCTRIGGEREVENTTYPE9outputCELL_N[3].OUT_SEC_TMIN[14]
C405XXXMACHINECHECKoutputCELL_E[14].OUT_FAN_TMIN[6]
CPMC405CLOCKinputCELL_E[9].IMUX_CLK[0]
CPMC405CORECLKINACTIVEinputCELL_E[5].IMUX_G1_DATA[2]
CPMC405CPUCLKENinputCELL_E[1].IMUX_CE[0]
CPMC405JTAGCLKENinputCELL_E[3].IMUX_CE[0]
CPMC405TIMERCLKENinputCELL_E[2].IMUX_CE[0]
CPMC405TIMERTICKinputCELL_E[3].IMUX_CLK[0]
DBGC405DEBUGHALTinputCELL_E[1].IMUX_G0_DATA[2]
DBGC405EXTBUSHOLDACKinputCELL_E[4].IMUX_G0_DATA[2]
DBGC405UNCONDDEBUGEVENTinputCELL_E[2].IMUX_G0_DATA[2]
DCRC405ACKinputCELL_W[8].IMUX_G0_DATA[1]
DCRC405DBUSIN0inputCELL_W[9].IMUX_G0_DATA[1]
DCRC405DBUSIN1inputCELL_W[9].IMUX_G1_DATA[1]
DCRC405DBUSIN10inputCELL_W[14].IMUX_G0_DATA[1]
DCRC405DBUSIN11inputCELL_W[14].IMUX_G1_DATA[1]
DCRC405DBUSIN12inputCELL_W[15].IMUX_G0_DATA[1]
DCRC405DBUSIN13inputCELL_W[15].IMUX_G1_DATA[1]
DCRC405DBUSIN14inputCELL_W[0].IMUX_G2_DATA[1]
DCRC405DBUSIN15inputCELL_W[0].IMUX_G3_DATA[1]
DCRC405DBUSIN16inputCELL_W[1].IMUX_G2_DATA[1]
DCRC405DBUSIN17inputCELL_W[1].IMUX_G3_DATA[1]
DCRC405DBUSIN18inputCELL_W[2].IMUX_G2_DATA[1]
DCRC405DBUSIN19inputCELL_W[2].IMUX_G3_DATA[1]
DCRC405DBUSIN2inputCELL_W[10].IMUX_G0_DATA[1]
DCRC405DBUSIN20inputCELL_W[3].IMUX_G2_DATA[1]
DCRC405DBUSIN21inputCELL_W[3].IMUX_G3_DATA[1]
DCRC405DBUSIN22inputCELL_W[4].IMUX_G0_DATA[1]
DCRC405DBUSIN23inputCELL_W[4].IMUX_G1_DATA[1]
DCRC405DBUSIN24inputCELL_W[5].IMUX_G0_DATA[1]
DCRC405DBUSIN25inputCELL_W[5].IMUX_G1_DATA[1]
DCRC405DBUSIN26inputCELL_W[6].IMUX_G0_DATA[1]
DCRC405DBUSIN27inputCELL_W[6].IMUX_G1_DATA[1]
DCRC405DBUSIN28inputCELL_W[7].IMUX_G0_DATA[1]
DCRC405DBUSIN29inputCELL_W[7].IMUX_G1_DATA[1]
DCRC405DBUSIN3inputCELL_W[10].IMUX_G1_DATA[1]
DCRC405DBUSIN30inputCELL_W[8].IMUX_G1_DATA[1]
DCRC405DBUSIN31inputCELL_W[8].IMUX_G2_DATA[1]
DCRC405DBUSIN4inputCELL_W[11].IMUX_G0_DATA[1]
DCRC405DBUSIN5inputCELL_W[11].IMUX_G1_DATA[1]
DCRC405DBUSIN6inputCELL_W[12].IMUX_G0_DATA[1]
DCRC405DBUSIN7inputCELL_W[12].IMUX_G1_DATA[1]
DCRC405DBUSIN8inputCELL_W[13].IMUX_G0_DATA[1]
DCRC405DBUSIN9inputCELL_W[13].IMUX_G1_DATA[1]
DSARCVALUE0inputCELL_N[5].IMUX_TI[0]
DSARCVALUE1inputCELL_N[5].IMUX_TI[1]
DSARCVALUE2inputCELL_N[5].IMUX_TS[0]
DSARCVALUE3inputCELL_N[5].IMUX_TS[1]
DSARCVALUE4inputCELL_N[6].IMUX_TI[0]
DSARCVALUE5inputCELL_N[6].IMUX_TI[1]
DSARCVALUE6inputCELL_N[6].IMUX_TS[0]
DSARCVALUE7inputCELL_N[6].IMUX_TS[1]
DSCNTLVALUE0inputCELL_N[1].IMUX_TI[0]
DSCNTLVALUE1inputCELL_N[1].IMUX_TI[1]
DSCNTLVALUE2inputCELL_N[1].IMUX_TS[0]
DSCNTLVALUE3inputCELL_N[1].IMUX_TS[1]
DSCNTLVALUE4inputCELL_N[2].IMUX_TI[1]
DSCNTLVALUE5inputCELL_N[2].IMUX_TS[0]
DSCNTLVALUE6inputCELL_N[2].IMUX_TS[1]
DSCNTLVALUE7inputCELL_N[4].IMUX_TS[1]
DSOCMBRAMABUS10outputCELL_N[5].OUT_FAN_TMIN[2]
DSOCMBRAMABUS11outputCELL_N[5].OUT_FAN_TMIN[3]
DSOCMBRAMABUS12outputCELL_N[5].OUT_FAN_TMIN[4]
DSOCMBRAMABUS13outputCELL_N[5].OUT_FAN_TMIN[5]
DSOCMBRAMABUS14outputCELL_N[5].OUT_FAN_TMIN[6]
DSOCMBRAMABUS15outputCELL_N[5].OUT_FAN_TMIN[7]
DSOCMBRAMABUS16outputCELL_N[0].IMUX_BRAM_ADDRA_N3[0], CELL_N[5].OUT_SEC_TMIN[15], CELL_N[7].IMUX_BRAM_ADDRA_N3[0]
DSOCMBRAMABUS17outputCELL_N[0].IMUX_BRAM_ADDRA_N3[1], CELL_N[5].OUT_SEC_TMIN[14], CELL_N[7].IMUX_BRAM_ADDRA_N3[1]
DSOCMBRAMABUS18outputCELL_N[0].IMUX_BRAM_ADDRA_N3[2], CELL_N[5].OUT_SEC_TMIN[13], CELL_N[7].IMUX_BRAM_ADDRA_N3[2]
DSOCMBRAMABUS19outputCELL_N[0].IMUX_BRAM_ADDRA_N3[3], CELL_N[5].OUT_SEC_TMIN[12], CELL_N[7].IMUX_BRAM_ADDRA_N3[3]
DSOCMBRAMABUS20outputCELL_N[0].IMUX_BRAM_ADDRA_N2[0], CELL_N[6].OUT_FAN_TMIN[0], CELL_N[7].IMUX_BRAM_ADDRA_N2[0]
DSOCMBRAMABUS21outputCELL_N[0].IMUX_BRAM_ADDRA_N2[1], CELL_N[6].OUT_FAN_TMIN[1], CELL_N[7].IMUX_BRAM_ADDRA_N2[1]
DSOCMBRAMABUS22outputCELL_N[0].IMUX_BRAM_ADDRA_N2[2], CELL_N[6].OUT_FAN_TMIN[2], CELL_N[7].IMUX_BRAM_ADDRA_N2[2]
DSOCMBRAMABUS23outputCELL_N[0].IMUX_BRAM_ADDRA_N2[3], CELL_N[6].OUT_FAN_TMIN[3], CELL_N[7].IMUX_BRAM_ADDRA_N2[3]
DSOCMBRAMABUS24outputCELL_N[0].IMUX_BRAM_ADDRA_N1[0], CELL_N[6].OUT_FAN_TMIN[4], CELL_N[7].IMUX_BRAM_ADDRA_N1[0]
DSOCMBRAMABUS25outputCELL_N[0].IMUX_BRAM_ADDRA_N1[1], CELL_N[6].OUT_FAN_TMIN[5], CELL_N[7].IMUX_BRAM_ADDRA_N1[1]
DSOCMBRAMABUS26outputCELL_N[0].IMUX_BRAM_ADDRA_N1[2], CELL_N[6].OUT_FAN_TMIN[6], CELL_N[7].IMUX_BRAM_ADDRA_N1[2]
DSOCMBRAMABUS27outputCELL_N[0].IMUX_BRAM_ADDRA_N1[3], CELL_N[6].OUT_FAN_TMIN[7], CELL_N[7].IMUX_BRAM_ADDRA_N1[3]
DSOCMBRAMABUS28outputCELL_N[0].IMUX_BRAM_ADDRA[0], CELL_N[6].OUT_SEC_TMIN[15], CELL_N[7].IMUX_BRAM_ADDRA[0]
DSOCMBRAMABUS29outputCELL_N[0].IMUX_BRAM_ADDRA[1], CELL_N[6].OUT_SEC_TMIN[14], CELL_N[7].IMUX_BRAM_ADDRA[1]
DSOCMBRAMABUS8outputCELL_N[5].OUT_FAN_TMIN[0]
DSOCMBRAMABUS9outputCELL_N[5].OUT_FAN_TMIN[1]
DSOCMBRAMBYTEWRITE0outputCELL_N[0].OUT_FAN_TMIN[0]
DSOCMBRAMBYTEWRITE1outputCELL_N[0].OUT_FAN_TMIN[1]
DSOCMBRAMBYTEWRITE2outputCELL_N[0].OUT_FAN_TMIN[2]
DSOCMBRAMBYTEWRITE3outputCELL_N[0].OUT_FAN_TMIN[3]
DSOCMBRAMENoutputCELL_N[6].OUT_SEC_TMIN[13]
DSOCMBRAMWRDBUS0outputCELL_N[1].OUT_FAN_TMIN[0]
DSOCMBRAMWRDBUS1outputCELL_N[1].OUT_FAN_TMIN[1]
DSOCMBRAMWRDBUS10outputCELL_N[2].OUT_FAN_TMIN[2]
DSOCMBRAMWRDBUS11outputCELL_N[2].OUT_FAN_TMIN[3]
DSOCMBRAMWRDBUS12outputCELL_N[2].OUT_FAN_TMIN[4]
DSOCMBRAMWRDBUS13outputCELL_N[2].OUT_FAN_TMIN[5]
DSOCMBRAMWRDBUS14outputCELL_N[2].OUT_FAN_TMIN[6]
DSOCMBRAMWRDBUS15outputCELL_N[2].OUT_FAN_TMIN[7]
DSOCMBRAMWRDBUS16outputCELL_N[3].OUT_FAN_TMIN[0]
DSOCMBRAMWRDBUS17outputCELL_N[3].OUT_FAN_TMIN[1]
DSOCMBRAMWRDBUS18outputCELL_N[3].OUT_FAN_TMIN[2]
DSOCMBRAMWRDBUS19outputCELL_N[3].OUT_FAN_TMIN[3]
DSOCMBRAMWRDBUS2outputCELL_N[1].OUT_FAN_TMIN[2]
DSOCMBRAMWRDBUS20outputCELL_N[3].OUT_FAN_TMIN[4]
DSOCMBRAMWRDBUS21outputCELL_N[3].OUT_FAN_TMIN[5]
DSOCMBRAMWRDBUS22outputCELL_N[3].OUT_FAN_TMIN[6]
DSOCMBRAMWRDBUS23outputCELL_N[3].OUT_FAN_TMIN[7]
DSOCMBRAMWRDBUS24outputCELL_N[4].OUT_FAN_TMIN[0]
DSOCMBRAMWRDBUS25outputCELL_N[4].OUT_FAN_TMIN[1]
DSOCMBRAMWRDBUS26outputCELL_N[4].OUT_FAN_TMIN[2]
DSOCMBRAMWRDBUS27outputCELL_N[4].OUT_FAN_TMIN[3]
DSOCMBRAMWRDBUS28outputCELL_N[4].OUT_FAN_TMIN[4]
DSOCMBRAMWRDBUS29outputCELL_N[4].OUT_FAN_TMIN[5]
DSOCMBRAMWRDBUS3outputCELL_N[1].OUT_FAN_TMIN[3]
DSOCMBRAMWRDBUS30outputCELL_N[4].OUT_FAN_TMIN[6]
DSOCMBRAMWRDBUS31outputCELL_N[4].OUT_FAN_TMIN[7]
DSOCMBRAMWRDBUS4outputCELL_N[1].OUT_FAN_TMIN[4]
DSOCMBRAMWRDBUS5outputCELL_N[1].OUT_FAN_TMIN[5]
DSOCMBRAMWRDBUS6outputCELL_N[1].OUT_FAN_TMIN[6]
DSOCMBRAMWRDBUS7outputCELL_N[1].OUT_FAN_TMIN[7]
DSOCMBRAMWRDBUS8outputCELL_N[2].OUT_FAN_TMIN[0]
DSOCMBRAMWRDBUS9outputCELL_N[2].OUT_FAN_TMIN[1]
DSOCMBUSYoutputCELL_N[6].OUT_SEC_TMIN[12]
DSOCMRDADDRVALIDoutputCELL_N[4].OUT_SEC_TMIN[13]
EICC405CRITINPUTIRQinputCELL_E[10].IMUX_G0_DATA[2]
EICC405EXTINPUTIRQinputCELL_E[15].IMUX_G0_DATA[2]
ISARCVALUE0inputCELL_S[4].IMUX_TI[0]
ISARCVALUE1inputCELL_S[4].IMUX_TI[1]
ISARCVALUE2inputCELL_S[4].IMUX_TS[0]
ISARCVALUE3inputCELL_S[4].IMUX_TS[1]
ISARCVALUE4inputCELL_S[5].IMUX_TI[0]
ISARCVALUE5inputCELL_S[5].IMUX_TI[1]
ISARCVALUE6inputCELL_S[5].IMUX_TS[0]
ISARCVALUE7inputCELL_S[5].IMUX_TS[1]
ISCNTLVALUE0inputCELL_S[2].IMUX_SR[0]
ISCNTLVALUE1inputCELL_S[2].IMUX_SR[1]
ISCNTLVALUE2inputCELL_S[3].IMUX_SR[0]
ISCNTLVALUE3inputCELL_S[3].IMUX_SR[1]
ISCNTLVALUE4inputCELL_S[5].IMUX_G0_DATA[0]
ISCNTLVALUE5inputCELL_S[5].IMUX_G1_DATA[0]
ISCNTLVALUE6inputCELL_S[2].IMUX_G0_DATA[0]
ISCNTLVALUE7inputCELL_S[2].IMUX_G1_DATA[0]
ISOCMBRAMENoutputCELL_S[2].OUT_SEC_TMIN[13]
ISOCMBRAMEVENWRITEENoutputCELL_S[2].OUT_SEC_TMIN[14]
ISOCMBRAMODDWRITEENoutputCELL_S[2].OUT_SEC_TMIN[15]
ISOCMBRAMRDABUS10outputCELL_S[6].OUT_FAN_TMIN[2]
ISOCMBRAMRDABUS11outputCELL_S[6].OUT_FAN_TMIN[3]
ISOCMBRAMRDABUS12outputCELL_S[6].OUT_FAN_TMIN[4]
ISOCMBRAMRDABUS13outputCELL_S[6].OUT_FAN_TMIN[5]
ISOCMBRAMRDABUS14outputCELL_S[6].OUT_FAN_TMIN[6]
ISOCMBRAMRDABUS15outputCELL_S[0].IMUX_BRAM_ADDRB[0], CELL_S[6].OUT_FAN_TMIN[7], CELL_S[7].IMUX_BRAM_ADDRB[0]
ISOCMBRAMRDABUS16outputCELL_S[0].IMUX_BRAM_ADDRB[1], CELL_S[6].OUT_SEC_TMIN[15], CELL_S[7].IMUX_BRAM_ADDRB[1]
ISOCMBRAMRDABUS17outputCELL_S[0].IMUX_BRAM_ADDRB[2], CELL_S[6].OUT_SEC_TMIN[14], CELL_S[7].IMUX_BRAM_ADDRB[2]
ISOCMBRAMRDABUS18outputCELL_S[0].IMUX_BRAM_ADDRB[3], CELL_S[6].OUT_SEC_TMIN[13], CELL_S[7].IMUX_BRAM_ADDRB[3]
ISOCMBRAMRDABUS19outputCELL_S[0].IMUX_BRAM_ADDRB_S1[0], CELL_S[6].OUT_SEC_TMIN[12], CELL_S[7].IMUX_BRAM_ADDRB_S1[0]
ISOCMBRAMRDABUS20outputCELL_S[0].IMUX_BRAM_ADDRB_S1[1], CELL_S[7].IMUX_BRAM_ADDRB_S1[1], CELL_S[7].OUT_FAN_TMIN[0]
ISOCMBRAMRDABUS21outputCELL_S[0].IMUX_BRAM_ADDRB_S1[2], CELL_S[7].IMUX_BRAM_ADDRB_S1[2], CELL_S[7].OUT_FAN_TMIN[1]
ISOCMBRAMRDABUS22outputCELL_S[0].IMUX_BRAM_ADDRB_S1[3], CELL_S[7].IMUX_BRAM_ADDRB_S1[3], CELL_S[7].OUT_FAN_TMIN[2]
ISOCMBRAMRDABUS23outputCELL_S[0].IMUX_BRAM_ADDRB_S2[0], CELL_S[7].IMUX_BRAM_ADDRB_S2[0], CELL_S[7].OUT_FAN_TMIN[3]
ISOCMBRAMRDABUS24outputCELL_S[0].IMUX_BRAM_ADDRB_S2[1], CELL_S[7].IMUX_BRAM_ADDRB_S2[1], CELL_S[7].OUT_FAN_TMIN[4]
ISOCMBRAMRDABUS25outputCELL_S[0].IMUX_BRAM_ADDRB_S2[2], CELL_S[7].IMUX_BRAM_ADDRB_S2[2], CELL_S[7].OUT_FAN_TMIN[5]
ISOCMBRAMRDABUS26outputCELL_S[0].IMUX_BRAM_ADDRB_S2[3], CELL_S[7].IMUX_BRAM_ADDRB_S2[3], CELL_S[7].OUT_FAN_TMIN[6]
ISOCMBRAMRDABUS27outputCELL_S[0].IMUX_BRAM_ADDRB_S3[0], CELL_S[7].IMUX_BRAM_ADDRB_S3[0], CELL_S[7].OUT_FAN_TMIN[7]
ISOCMBRAMRDABUS28outputCELL_S[0].IMUX_BRAM_ADDRB_S3[1], CELL_S[7].IMUX_BRAM_ADDRB_S3[1], CELL_S[7].OUT_SEC_TMIN[15]
ISOCMBRAMRDABUS8outputCELL_S[6].OUT_FAN_TMIN[0]
ISOCMBRAMRDABUS9outputCELL_S[6].OUT_FAN_TMIN[1]
ISOCMBRAMWRABUS10outputCELL_S[0].OUT_FAN_TMIN[2]
ISOCMBRAMWRABUS11outputCELL_S[0].OUT_FAN_TMIN[3]
ISOCMBRAMWRABUS12outputCELL_S[0].OUT_FAN_TMIN[4]
ISOCMBRAMWRABUS13outputCELL_S[0].OUT_FAN_TMIN[5]
ISOCMBRAMWRABUS14outputCELL_S[0].OUT_FAN_TMIN[6]
ISOCMBRAMWRABUS15outputCELL_S[0].IMUX_BRAM_ADDRA[0], CELL_S[0].OUT_FAN_TMIN[7], CELL_S[7].IMUX_BRAM_ADDRA[0]
ISOCMBRAMWRABUS16outputCELL_S[0].IMUX_BRAM_ADDRA[1], CELL_S[0].OUT_SEC_TMIN[15], CELL_S[7].IMUX_BRAM_ADDRA[1]
ISOCMBRAMWRABUS17outputCELL_S[0].IMUX_BRAM_ADDRA[2], CELL_S[0].OUT_SEC_TMIN[14], CELL_S[7].IMUX_BRAM_ADDRA[2]
ISOCMBRAMWRABUS18outputCELL_S[0].IMUX_BRAM_ADDRA[3], CELL_S[0].OUT_SEC_TMIN[13], CELL_S[7].IMUX_BRAM_ADDRA[3]
ISOCMBRAMWRABUS19outputCELL_S[0].IMUX_BRAM_ADDRA_S1[0], CELL_S[0].OUT_SEC_TMIN[12], CELL_S[7].IMUX_BRAM_ADDRA_S1[0]
ISOCMBRAMWRABUS20outputCELL_S[0].IMUX_BRAM_ADDRA_S1[1], CELL_S[1].OUT_FAN_TMIN[0], CELL_S[7].IMUX_BRAM_ADDRA_S1[1]
ISOCMBRAMWRABUS21outputCELL_S[0].IMUX_BRAM_ADDRA_S1[2], CELL_S[1].OUT_FAN_TMIN[1], CELL_S[7].IMUX_BRAM_ADDRA_S1[2]
ISOCMBRAMWRABUS22outputCELL_S[0].IMUX_BRAM_ADDRA_S1[3], CELL_S[1].OUT_FAN_TMIN[2], CELL_S[7].IMUX_BRAM_ADDRA_S1[3]
ISOCMBRAMWRABUS23outputCELL_S[0].IMUX_BRAM_ADDRA_S2[0], CELL_S[1].OUT_FAN_TMIN[3], CELL_S[7].IMUX_BRAM_ADDRA_S2[0]
ISOCMBRAMWRABUS24outputCELL_S[0].IMUX_BRAM_ADDRA_S2[1], CELL_S[1].OUT_FAN_TMIN[4], CELL_S[7].IMUX_BRAM_ADDRA_S2[1]
ISOCMBRAMWRABUS25outputCELL_S[0].IMUX_BRAM_ADDRA_S2[2], CELL_S[1].OUT_FAN_TMIN[5], CELL_S[7].IMUX_BRAM_ADDRA_S2[2]
ISOCMBRAMWRABUS26outputCELL_S[0].IMUX_BRAM_ADDRA_S2[3], CELL_S[1].OUT_FAN_TMIN[6], CELL_S[7].IMUX_BRAM_ADDRA_S2[3]
ISOCMBRAMWRABUS27outputCELL_S[0].IMUX_BRAM_ADDRA_S3[0], CELL_S[1].OUT_FAN_TMIN[7], CELL_S[7].IMUX_BRAM_ADDRA_S3[0]
ISOCMBRAMWRABUS28outputCELL_S[0].IMUX_BRAM_ADDRA_S3[1], CELL_S[1].OUT_SEC_TMIN[15], CELL_S[7].IMUX_BRAM_ADDRA_S3[1]
ISOCMBRAMWRABUS8outputCELL_S[0].OUT_FAN_TMIN[0]
ISOCMBRAMWRABUS9outputCELL_S[0].OUT_FAN_TMIN[1]
ISOCMBRAMWRDBUS0outputCELL_S[2].OUT_FAN_TMIN[0]
ISOCMBRAMWRDBUS1outputCELL_S[2].OUT_FAN_TMIN[1]
ISOCMBRAMWRDBUS10outputCELL_S[3].OUT_FAN_TMIN[2]
ISOCMBRAMWRDBUS11outputCELL_S[3].OUT_FAN_TMIN[3]
ISOCMBRAMWRDBUS12outputCELL_S[3].OUT_FAN_TMIN[4]
ISOCMBRAMWRDBUS13outputCELL_S[3].OUT_FAN_TMIN[5]
ISOCMBRAMWRDBUS14outputCELL_S[3].OUT_FAN_TMIN[6]
ISOCMBRAMWRDBUS15outputCELL_S[3].OUT_FAN_TMIN[7]
ISOCMBRAMWRDBUS16outputCELL_S[4].OUT_FAN_TMIN[0]
ISOCMBRAMWRDBUS17outputCELL_S[4].OUT_FAN_TMIN[1]
ISOCMBRAMWRDBUS18outputCELL_S[4].OUT_FAN_TMIN[2]
ISOCMBRAMWRDBUS19outputCELL_S[4].OUT_FAN_TMIN[3]
ISOCMBRAMWRDBUS2outputCELL_S[2].OUT_FAN_TMIN[2]
ISOCMBRAMWRDBUS20outputCELL_S[4].OUT_FAN_TMIN[4]
ISOCMBRAMWRDBUS21outputCELL_S[4].OUT_FAN_TMIN[5]
ISOCMBRAMWRDBUS22outputCELL_S[4].OUT_FAN_TMIN[6]
ISOCMBRAMWRDBUS23outputCELL_S[4].OUT_FAN_TMIN[7]
ISOCMBRAMWRDBUS24outputCELL_S[5].OUT_FAN_TMIN[0]
ISOCMBRAMWRDBUS25outputCELL_S[5].OUT_FAN_TMIN[1]
ISOCMBRAMWRDBUS26outputCELL_S[5].OUT_FAN_TMIN[2]
ISOCMBRAMWRDBUS27outputCELL_S[5].OUT_FAN_TMIN[3]
ISOCMBRAMWRDBUS28outputCELL_S[5].OUT_FAN_TMIN[4]
ISOCMBRAMWRDBUS29outputCELL_S[5].OUT_FAN_TMIN[5]
ISOCMBRAMWRDBUS3outputCELL_S[2].OUT_FAN_TMIN[3]
ISOCMBRAMWRDBUS30outputCELL_S[5].OUT_FAN_TMIN[6]
ISOCMBRAMWRDBUS31outputCELL_S[5].OUT_FAN_TMIN[7]
ISOCMBRAMWRDBUS4outputCELL_S[2].OUT_FAN_TMIN[4]
ISOCMBRAMWRDBUS5outputCELL_S[2].OUT_FAN_TMIN[5]
ISOCMBRAMWRDBUS6outputCELL_S[2].OUT_FAN_TMIN[6]
ISOCMBRAMWRDBUS7outputCELL_S[2].OUT_FAN_TMIN[7]
ISOCMBRAMWRDBUS8outputCELL_S[3].OUT_FAN_TMIN[0]
ISOCMBRAMWRDBUS9outputCELL_S[3].OUT_FAN_TMIN[1]
ISOCMRDADDRVALIDoutputCELL_S[1].OUT_SEC_TMIN[14]
JTGC405BNDSCANTDOinputCELL_N[2].IMUX_G1_DATA[0]
JTGC405TCKinputCELL_N[1].IMUX_CLK[0]
JTGC405TDIinputCELL_N[1].IMUX_G1_DATA[0]
JTGC405TMSinputCELL_N[1].IMUX_G2_DATA[0]
JTGC405TRSTNEGinputCELL_E[12].IMUX_G2_DATA[2]
LSSDC405ACLKinputCELL_S[7].IMUX_G1_DATA[5]
LSSDC405ARRAYCCLKNEGinputCELL_S[0].IMUX_G2_DATA[5]
LSSDC405BCLKinputCELL_S[0].IMUX_G3_DATA[5]
LSSDC405BISTCCLKinputCELL_S[1].IMUX_G2_DATA[5]
LSSDC405CNTLPOINTinputCELL_S[1].IMUX_G3_DATA[5]
LSSDC405SCANGATEinputCELL_S[2].IMUX_G0_DATA[2]
LSSDC405SCANIN0inputCELL_S[4].IMUX_G3_DATA[1]
LSSDC405SCANIN1inputCELL_S[4].IMUX_G0_DATA[2]
LSSDC405SCANIN2inputCELL_S[5].IMUX_G0_DATA[2]
LSSDC405SCANIN3inputCELL_S[5].IMUX_G1_DATA[2]
LSSDC405SCANIN4inputCELL_S[6].IMUX_G2_DATA[5]
LSSDC405SCANIN5inputCELL_S[6].IMUX_G3_DATA[5]
LSSDC405SCANIN6inputCELL_S[7].IMUX_G2_DATA[5]
LSSDC405SCANIN7inputCELL_S[7].IMUX_G3_DATA[5]
LSSDC405SCANIN8inputCELL_S[0].IMUX_G0_DATA[6]
LSSDC405SCANIN9inputCELL_S[0].IMUX_G1_DATA[6]
LSSDC405TESTEVSinputCELL_S[2].IMUX_G1_DATA[2]
LSSDC405TESTM1inputCELL_S[3].IMUX_G2_DATA[1]
LSSDC405TESTM3inputCELL_S[3].IMUX_G3_DATA[1]
MCBCPUCLKENinputCELL_E[4].IMUX_TI[0]
MCBJTAGENinputCELL_E[5].IMUX_TI[0]
MCBTIMERENinputCELL_E[6].IMUX_TI[0]
MCPPCRSTinputCELL_E[14].IMUX_TI[0]
PLBC405DCUADDRACKinputCELL_E[7].IMUX_G0_DATA[2]
PLBC405DCUBUSYinputCELL_E[7].IMUX_G2_DATA[2]
PLBC405DCUERRinputCELL_E[7].IMUX_G3_DATA[2]
PLBC405DCURDDACKinputCELL_E[6].IMUX_G3_DATA[2]
PLBC405DCURDDBUS0inputCELL_E[15].IMUX_G0_DATA[0]
PLBC405DCURDDBUS1inputCELL_E[15].IMUX_G1_DATA[0]
PLBC405DCURDDBUS10inputCELL_E[13].IMUX_G2_DATA[0]
PLBC405DCURDDBUS11inputCELL_E[13].IMUX_G3_DATA[0]
PLBC405DCURDDBUS12inputCELL_E[12].IMUX_G0_DATA[0]
PLBC405DCURDDBUS13inputCELL_E[12].IMUX_G1_DATA[0]
PLBC405DCURDDBUS14inputCELL_E[12].IMUX_G2_DATA[0]
PLBC405DCURDDBUS15inputCELL_E[12].IMUX_G3_DATA[0]
PLBC405DCURDDBUS16inputCELL_E[11].IMUX_G0_DATA[0]
PLBC405DCURDDBUS17inputCELL_E[11].IMUX_G1_DATA[0]
PLBC405DCURDDBUS18inputCELL_E[11].IMUX_G2_DATA[0]
PLBC405DCURDDBUS19inputCELL_E[11].IMUX_G3_DATA[0]
PLBC405DCURDDBUS2inputCELL_E[15].IMUX_G2_DATA[0]
PLBC405DCURDDBUS20inputCELL_E[10].IMUX_G0_DATA[0]
PLBC405DCURDDBUS21inputCELL_E[10].IMUX_G1_DATA[0]
PLBC405DCURDDBUS22inputCELL_E[10].IMUX_G2_DATA[0]
PLBC405DCURDDBUS23inputCELL_E[10].IMUX_G3_DATA[0]
PLBC405DCURDDBUS24inputCELL_E[9].IMUX_G0_DATA[0]
PLBC405DCURDDBUS25inputCELL_E[9].IMUX_G1_DATA[0]
PLBC405DCURDDBUS26inputCELL_E[9].IMUX_G2_DATA[0]
PLBC405DCURDDBUS27inputCELL_E[9].IMUX_G3_DATA[0]
PLBC405DCURDDBUS28inputCELL_E[8].IMUX_G0_DATA[0]
PLBC405DCURDDBUS29inputCELL_E[8].IMUX_G1_DATA[0]
PLBC405DCURDDBUS3inputCELL_E[15].IMUX_G3_DATA[0]
PLBC405DCURDDBUS30inputCELL_E[8].IMUX_G2_DATA[0]
PLBC405DCURDDBUS31inputCELL_E[8].IMUX_G3_DATA[0]
PLBC405DCURDDBUS32inputCELL_E[7].IMUX_G0_DATA[0]
PLBC405DCURDDBUS33inputCELL_E[7].IMUX_G1_DATA[0]
PLBC405DCURDDBUS34inputCELL_E[7].IMUX_G2_DATA[0]
PLBC405DCURDDBUS35inputCELL_E[7].IMUX_G3_DATA[0]
PLBC405DCURDDBUS36inputCELL_E[6].IMUX_G0_DATA[0]
PLBC405DCURDDBUS37inputCELL_E[6].IMUX_G1_DATA[0]
PLBC405DCURDDBUS38inputCELL_E[6].IMUX_G2_DATA[0]
PLBC405DCURDDBUS39inputCELL_E[6].IMUX_G3_DATA[0]
PLBC405DCURDDBUS4inputCELL_E[14].IMUX_G0_DATA[0]
PLBC405DCURDDBUS40inputCELL_E[5].IMUX_G0_DATA[0]
PLBC405DCURDDBUS41inputCELL_E[5].IMUX_G1_DATA[0]
PLBC405DCURDDBUS42inputCELL_E[5].IMUX_G2_DATA[0]
PLBC405DCURDDBUS43inputCELL_E[5].IMUX_G3_DATA[0]
PLBC405DCURDDBUS44inputCELL_E[4].IMUX_G0_DATA[0]
PLBC405DCURDDBUS45inputCELL_E[4].IMUX_G1_DATA[0]
PLBC405DCURDDBUS46inputCELL_E[4].IMUX_G2_DATA[0]
PLBC405DCURDDBUS47inputCELL_E[4].IMUX_G3_DATA[0]
PLBC405DCURDDBUS48inputCELL_E[3].IMUX_G0_DATA[0]
PLBC405DCURDDBUS49inputCELL_E[3].IMUX_G1_DATA[0]
PLBC405DCURDDBUS5inputCELL_E[14].IMUX_G1_DATA[0]
PLBC405DCURDDBUS50inputCELL_E[3].IMUX_G2_DATA[0]
PLBC405DCURDDBUS51inputCELL_E[3].IMUX_G3_DATA[0]
PLBC405DCURDDBUS52inputCELL_E[2].IMUX_G0_DATA[0]
PLBC405DCURDDBUS53inputCELL_E[2].IMUX_G1_DATA[0]
PLBC405DCURDDBUS54inputCELL_E[2].IMUX_G2_DATA[0]
PLBC405DCURDDBUS55inputCELL_E[2].IMUX_G3_DATA[0]
PLBC405DCURDDBUS56inputCELL_E[1].IMUX_G0_DATA[0]
PLBC405DCURDDBUS57inputCELL_E[1].IMUX_G1_DATA[0]
PLBC405DCURDDBUS58inputCELL_E[1].IMUX_G2_DATA[0]
PLBC405DCURDDBUS59inputCELL_E[1].IMUX_G3_DATA[0]
PLBC405DCURDDBUS6inputCELL_E[14].IMUX_G2_DATA[0]
PLBC405DCURDDBUS60inputCELL_E[0].IMUX_G0_DATA[0]
PLBC405DCURDDBUS61inputCELL_E[0].IMUX_G1_DATA[0]
PLBC405DCURDDBUS62inputCELL_E[0].IMUX_G2_DATA[0]
PLBC405DCURDDBUS63inputCELL_E[0].IMUX_G3_DATA[0]
PLBC405DCURDDBUS7inputCELL_E[14].IMUX_G3_DATA[0]
PLBC405DCURDDBUS8inputCELL_E[13].IMUX_G0_DATA[0]
PLBC405DCURDDBUS9inputCELL_E[13].IMUX_G1_DATA[0]
PLBC405DCURDWDADDR1inputCELL_E[6].IMUX_G0_DATA[2]
PLBC405DCURDWDADDR2inputCELL_E[6].IMUX_G1_DATA[2]
PLBC405DCURDWDADDR3inputCELL_E[6].IMUX_G2_DATA[2]
PLBC405DCUSSIZE1inputCELL_E[7].IMUX_G1_DATA[2]
PLBC405DCUWRDACKinputCELL_E[5].IMUX_G0_DATA[2]
PLBC405ICUADDRACKinputCELL_E[8].IMUX_G0_DATA[2]
PLBC405ICUBUSYinputCELL_E[8].IMUX_G2_DATA[2]
PLBC405ICUERRinputCELL_E[8].IMUX_G3_DATA[2]
PLBC405ICURDDACKinputCELL_E[9].IMUX_G3_DATA[2]
PLBC405ICURDDBUS0inputCELL_E[15].IMUX_G0_DATA[1]
PLBC405ICURDDBUS1inputCELL_E[15].IMUX_G1_DATA[1]
PLBC405ICURDDBUS10inputCELL_E[13].IMUX_G2_DATA[1]
PLBC405ICURDDBUS11inputCELL_E[13].IMUX_G3_DATA[1]
PLBC405ICURDDBUS12inputCELL_E[12].IMUX_G0_DATA[1]
PLBC405ICURDDBUS13inputCELL_E[12].IMUX_G1_DATA[1]
PLBC405ICURDDBUS14inputCELL_E[12].IMUX_G2_DATA[1]
PLBC405ICURDDBUS15inputCELL_E[12].IMUX_G3_DATA[1]
PLBC405ICURDDBUS16inputCELL_E[11].IMUX_G0_DATA[1]
PLBC405ICURDDBUS17inputCELL_E[11].IMUX_G1_DATA[1]
PLBC405ICURDDBUS18inputCELL_E[11].IMUX_G2_DATA[1]
PLBC405ICURDDBUS19inputCELL_E[11].IMUX_G3_DATA[1]
PLBC405ICURDDBUS2inputCELL_E[15].IMUX_G2_DATA[1]
PLBC405ICURDDBUS20inputCELL_E[10].IMUX_G0_DATA[1]
PLBC405ICURDDBUS21inputCELL_E[10].IMUX_G1_DATA[1]
PLBC405ICURDDBUS22inputCELL_E[10].IMUX_G2_DATA[1]
PLBC405ICURDDBUS23inputCELL_E[10].IMUX_G3_DATA[1]
PLBC405ICURDDBUS24inputCELL_E[9].IMUX_G0_DATA[1]
PLBC405ICURDDBUS25inputCELL_E[9].IMUX_G1_DATA[1]
PLBC405ICURDDBUS26inputCELL_E[9].IMUX_G2_DATA[1]
PLBC405ICURDDBUS27inputCELL_E[9].IMUX_G3_DATA[1]
PLBC405ICURDDBUS28inputCELL_E[8].IMUX_G0_DATA[1]
PLBC405ICURDDBUS29inputCELL_E[8].IMUX_G1_DATA[1]
PLBC405ICURDDBUS3inputCELL_E[15].IMUX_G3_DATA[1]
PLBC405ICURDDBUS30inputCELL_E[8].IMUX_G2_DATA[1]
PLBC405ICURDDBUS31inputCELL_E[8].IMUX_G3_DATA[1]
PLBC405ICURDDBUS32inputCELL_E[7].IMUX_G0_DATA[1]
PLBC405ICURDDBUS33inputCELL_E[7].IMUX_G1_DATA[1]
PLBC405ICURDDBUS34inputCELL_E[7].IMUX_G2_DATA[1]
PLBC405ICURDDBUS35inputCELL_E[7].IMUX_G3_DATA[1]
PLBC405ICURDDBUS36inputCELL_E[6].IMUX_G0_DATA[1]
PLBC405ICURDDBUS37inputCELL_E[6].IMUX_G1_DATA[1]
PLBC405ICURDDBUS38inputCELL_E[6].IMUX_G2_DATA[1]
PLBC405ICURDDBUS39inputCELL_E[6].IMUX_G3_DATA[1]
PLBC405ICURDDBUS4inputCELL_E[14].IMUX_G0_DATA[1]
PLBC405ICURDDBUS40inputCELL_E[5].IMUX_G0_DATA[1]
PLBC405ICURDDBUS41inputCELL_E[5].IMUX_G1_DATA[1]
PLBC405ICURDDBUS42inputCELL_E[5].IMUX_G2_DATA[1]
PLBC405ICURDDBUS43inputCELL_E[5].IMUX_G3_DATA[1]
PLBC405ICURDDBUS44inputCELL_E[4].IMUX_G0_DATA[1]
PLBC405ICURDDBUS45inputCELL_E[4].IMUX_G1_DATA[1]
PLBC405ICURDDBUS46inputCELL_E[4].IMUX_G2_DATA[1]
PLBC405ICURDDBUS47inputCELL_E[4].IMUX_G3_DATA[1]
PLBC405ICURDDBUS48inputCELL_E[3].IMUX_G0_DATA[1]
PLBC405ICURDDBUS49inputCELL_E[3].IMUX_G1_DATA[1]
PLBC405ICURDDBUS5inputCELL_E[14].IMUX_G1_DATA[1]
PLBC405ICURDDBUS50inputCELL_E[3].IMUX_G2_DATA[1]
PLBC405ICURDDBUS51inputCELL_E[3].IMUX_G3_DATA[1]
PLBC405ICURDDBUS52inputCELL_E[2].IMUX_G0_DATA[1]
PLBC405ICURDDBUS53inputCELL_E[2].IMUX_G1_DATA[1]
PLBC405ICURDDBUS54inputCELL_E[2].IMUX_G2_DATA[1]
PLBC405ICURDDBUS55inputCELL_E[2].IMUX_G3_DATA[1]
PLBC405ICURDDBUS56inputCELL_E[1].IMUX_G0_DATA[1]
PLBC405ICURDDBUS57inputCELL_E[1].IMUX_G1_DATA[1]
PLBC405ICURDDBUS58inputCELL_E[1].IMUX_G2_DATA[1]
PLBC405ICURDDBUS59inputCELL_E[1].IMUX_G3_DATA[1]
PLBC405ICURDDBUS6inputCELL_E[14].IMUX_G2_DATA[1]
PLBC405ICURDDBUS60inputCELL_E[0].IMUX_G0_DATA[1]
PLBC405ICURDDBUS61inputCELL_E[0].IMUX_G1_DATA[1]
PLBC405ICURDDBUS62inputCELL_E[0].IMUX_G2_DATA[1]
PLBC405ICURDDBUS63inputCELL_E[0].IMUX_G3_DATA[1]
PLBC405ICURDDBUS7inputCELL_E[14].IMUX_G3_DATA[1]
PLBC405ICURDDBUS8inputCELL_E[13].IMUX_G0_DATA[1]
PLBC405ICURDDBUS9inputCELL_E[13].IMUX_G1_DATA[1]
PLBC405ICURDWDADDR1inputCELL_E[9].IMUX_G0_DATA[2]
PLBC405ICURDWDADDR2inputCELL_E[9].IMUX_G1_DATA[2]
PLBC405ICURDWDADDR3inputCELL_E[9].IMUX_G2_DATA[2]
PLBC405ICUSSIZE1inputCELL_E[8].IMUX_G1_DATA[2]
PLBCLKinputCELL_E[0].IMUX_CLK[1]
RSTC405RESETCHIPinputCELL_E[11].IMUX_SR[0]
RSTC405RESETCOREinputCELL_E[12].IMUX_SR[0]
RSTC405RESETSYSinputCELL_E[13].IMUX_SR[0]
TESTSELIinputCELL_W[8].IMUX_TI[0]
TIEC405APUDIVENinputCELL_W[4].IMUX_TI[0]
TIEC405APUPRESENTinputCELL_W[4].IMUX_TI[1]
TIEC405DETERMINISTICMULTinputCELL_E[0].IMUX_TI[0]
TIEC405DISOPERANDFWDinputCELL_E[1].IMUX_TI[0]
TIEC405MMUENinputCELL_E[1].IMUX_TI[1]
TIEC405PVR0inputCELL_E[15].IMUX_TI[0]
TIEC405PVR1inputCELL_E[15].IMUX_TI[1]
TIEC405PVR10inputCELL_E[12].IMUX_TI[1]
TIEC405PVR11inputCELL_E[12].IMUX_TS[0]
TIEC405PVR12inputCELL_E[11].IMUX_TI[0]
TIEC405PVR13inputCELL_E[11].IMUX_TI[1]
TIEC405PVR14inputCELL_E[11].IMUX_TS[0]
TIEC405PVR15inputCELL_E[10].IMUX_TI[0]
TIEC405PVR16inputCELL_E[10].IMUX_TI[1]
TIEC405PVR17inputCELL_E[10].IMUX_TS[0]
TIEC405PVR18inputCELL_E[5].IMUX_TI[1]
TIEC405PVR19inputCELL_E[5].IMUX_TS[0]
TIEC405PVR2inputCELL_E[15].IMUX_TS[0]
TIEC405PVR20inputCELL_E[4].IMUX_TI[1]
TIEC405PVR21inputCELL_E[4].IMUX_TS[0]
TIEC405PVR22inputCELL_E[4].IMUX_TS[1]
TIEC405PVR23inputCELL_E[3].IMUX_TI[0]
TIEC405PVR24inputCELL_E[3].IMUX_TI[1]
TIEC405PVR25inputCELL_E[3].IMUX_TS[0]
TIEC405PVR26inputCELL_E[2].IMUX_TI[0]
TIEC405PVR27inputCELL_E[2].IMUX_TI[1]
TIEC405PVR28inputCELL_E[2].IMUX_TS[0]
TIEC405PVR29inputCELL_E[1].IMUX_TS[0]
TIEC405PVR3inputCELL_E[14].IMUX_TI[1]
TIEC405PVR30inputCELL_E[0].IMUX_TI[1]
TIEC405PVR31inputCELL_E[0].IMUX_TS[0]
TIEC405PVR4inputCELL_E[14].IMUX_TS[0]
TIEC405PVR5inputCELL_E[14].IMUX_TS[1]
TIEC405PVR6inputCELL_E[13].IMUX_TI[0]
TIEC405PVR7inputCELL_E[13].IMUX_TI[1]
TIEC405PVR8inputCELL_E[13].IMUX_TS[0]
TIEC405PVR9inputCELL_E[12].IMUX_TI[0]
TIEDSOCMDCRADDR0inputCELL_N[2].IMUX_TI[0]
TIEDSOCMDCRADDR1inputCELL_N[3].IMUX_TI[0]
TIEDSOCMDCRADDR2inputCELL_N[3].IMUX_TI[1]
TIEDSOCMDCRADDR3inputCELL_N[3].IMUX_TS[0]
TIEDSOCMDCRADDR4inputCELL_N[3].IMUX_TS[1]
TIEDSOCMDCRADDR5inputCELL_N[4].IMUX_TI[0]
TIEDSOCMDCRADDR6inputCELL_N[4].IMUX_TI[1]
TIEDSOCMDCRADDR7inputCELL_N[4].IMUX_TS[0]
TIEISOCMDCRADDR0inputCELL_S[2].IMUX_TI[0]
TIEISOCMDCRADDR1inputCELL_S[2].IMUX_TI[1]
TIEISOCMDCRADDR2inputCELL_S[2].IMUX_TS[0]
TIEISOCMDCRADDR3inputCELL_S[2].IMUX_TS[1]
TIEISOCMDCRADDR4inputCELL_S[3].IMUX_TI[0]
TIEISOCMDCRADDR5inputCELL_S[3].IMUX_TI[1]
TIEISOCMDCRADDR6inputCELL_S[3].IMUX_TS[0]
TIEISOCMDCRADDR7inputCELL_S[3].IMUX_TS[1]
TIERAMTAP1inputCELL_W[6].IMUX_TI[0]
TIERAMTAP2inputCELL_W[6].IMUX_TI[1]
TIETAGTAP1inputCELL_W[7].IMUX_TI[0]
TIETAGTAP2inputCELL_W[7].IMUX_TI[1]
TIEUTLBTAP1inputCELL_W[5].IMUX_TI[0]
TIEUTLBTAP2inputCELL_W[5].IMUX_TI[1]
TRCC405TRACEDISABLEinputCELL_N[1].IMUX_G0_DATA[0]
TRCC405TRIGGEREVENTINinputCELL_N[2].IMUX_G0_DATA[0]
TSTC405DCRABUSI0inputCELL_W[0].IMUX_G0_DATA[3]
TSTC405DCRABUSI1inputCELL_W[0].IMUX_G1_DATA[3]
TSTC405DCRABUSI2inputCELL_W[1].IMUX_G0_DATA[3]
TSTC405DCRABUSI3inputCELL_W[1].IMUX_G1_DATA[3]
TSTC405DCRABUSI4inputCELL_W[2].IMUX_G0_DATA[3]
TSTC405DCRABUSI5inputCELL_W[2].IMUX_G1_DATA[3]
TSTC405DCRABUSI6inputCELL_W[3].IMUX_G0_DATA[3]
TSTC405DCRABUSI7inputCELL_W[3].IMUX_G1_DATA[3]
TSTC405DCRABUSI8inputCELL_W[4].IMUX_G2_DATA[2]
TSTC405DCRABUSI9inputCELL_W[4].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI0inputCELL_W[5].IMUX_G2_DATA[2]
TSTC405DCRDBUSOUTI1inputCELL_W[5].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI10inputCELL_W[10].IMUX_G0_DATA[3]
TSTC405DCRDBUSOUTI11inputCELL_W[11].IMUX_G2_DATA[2]
TSTC405DCRDBUSOUTI12inputCELL_W[11].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI13inputCELL_W[12].IMUX_G2_DATA[2]
TSTC405DCRDBUSOUTI14inputCELL_W[12].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI15inputCELL_W[13].IMUX_G2_DATA[2]
TSTC405DCRDBUSOUTI16inputCELL_W[13].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI17inputCELL_W[14].IMUX_G2_DATA[2]
TSTC405DCRDBUSOUTI18inputCELL_W[14].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI19inputCELL_W[15].IMUX_G2_DATA[2]
TSTC405DCRDBUSOUTI2inputCELL_W[6].IMUX_G2_DATA[2]
TSTC405DCRDBUSOUTI20inputCELL_W[15].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI21inputCELL_W[0].IMUX_G2_DATA[3]
TSTC405DCRDBUSOUTI22inputCELL_W[0].IMUX_G3_DATA[3]
TSTC405DCRDBUSOUTI23inputCELL_W[1].IMUX_G2_DATA[3]
TSTC405DCRDBUSOUTI24inputCELL_W[1].IMUX_G3_DATA[3]
TSTC405DCRDBUSOUTI25inputCELL_W[2].IMUX_G2_DATA[3]
TSTC405DCRDBUSOUTI26inputCELL_W[2].IMUX_G3_DATA[3]
TSTC405DCRDBUSOUTI27inputCELL_W[3].IMUX_G2_DATA[3]
TSTC405DCRDBUSOUTI28inputCELL_W[3].IMUX_G3_DATA[3]
TSTC405DCRDBUSOUTI29inputCELL_W[4].IMUX_G0_DATA[3]
TSTC405DCRDBUSOUTI3inputCELL_W[6].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI30inputCELL_W[4].IMUX_G1_DATA[3]
TSTC405DCRDBUSOUTI31inputCELL_W[5].IMUX_G0_DATA[3]
TSTC405DCRDBUSOUTI4inputCELL_W[7].IMUX_G2_DATA[2]
TSTC405DCRDBUSOUTI5inputCELL_W[7].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI6inputCELL_W[8].IMUX_G0_DATA[3]
TSTC405DCRDBUSOUTI7inputCELL_W[9].IMUX_G0_DATA[3]
TSTC405DCRDBUSOUTI8inputCELL_W[9].IMUX_G1_DATA[3]
TSTC405DCRDBUSOUTI9inputCELL_W[10].IMUX_G3_DATA[2]
TSTC405DCRREADIinputCELL_W[5].IMUX_G1_DATA[3]
TSTC405DCRWRITEIinputCELL_W[6].IMUX_G0_DATA[3]
TSTCLKINACTIinputCELL_E[1].IMUX_G1_DATA[2]
TSTCLKINACTOoutputCELL_E[1].OUT_TEST[0]
TSTCPUCLKENIinputCELL_E[14].IMUX_G0_DATA[2]
TSTCPUCLKENOoutputCELL_E[1].OUT_SEC_TMIN[9]
TSTCPUCLKIinputCELL_E[0].IMUX_G1_DATA[2]
TSTCPUCLKOoutputCELL_E[1].OUT_SEC_TMIN[8]
TSTDCRACKIinputCELL_W[8].IMUX_G3_DATA[1]
TSTDCRACKOoutputCELL_W[0].OUT_SEC_TMIN[10]
TSTDCRBUSI0inputCELL_W[9].IMUX_G2_DATA[1]
TSTDCRBUSI1inputCELL_W[9].IMUX_G3_DATA[1]
TSTDCRBUSI10inputCELL_W[14].IMUX_G2_DATA[1]
TSTDCRBUSI11inputCELL_W[14].IMUX_G3_DATA[1]
TSTDCRBUSI12inputCELL_W[15].IMUX_G2_DATA[1]
TSTDCRBUSI13inputCELL_W[15].IMUX_G3_DATA[1]
TSTDCRBUSI14inputCELL_W[0].IMUX_G0_DATA[2]
TSTDCRBUSI15inputCELL_W[0].IMUX_G1_DATA[2]
TSTDCRBUSI16inputCELL_W[1].IMUX_G0_DATA[2]
TSTDCRBUSI17inputCELL_W[1].IMUX_G1_DATA[2]
TSTDCRBUSI18inputCELL_W[2].IMUX_G0_DATA[2]
TSTDCRBUSI19inputCELL_W[2].IMUX_G1_DATA[2]
TSTDCRBUSI2inputCELL_W[10].IMUX_G2_DATA[1]
TSTDCRBUSI20inputCELL_W[3].IMUX_G0_DATA[2]
TSTDCRBUSI21inputCELL_W[3].IMUX_G1_DATA[2]
TSTDCRBUSI22inputCELL_W[4].IMUX_G2_DATA[1]
TSTDCRBUSI23inputCELL_W[4].IMUX_G3_DATA[1]
TSTDCRBUSI24inputCELL_W[5].IMUX_G2_DATA[1]
TSTDCRBUSI25inputCELL_W[5].IMUX_G3_DATA[1]
TSTDCRBUSI26inputCELL_W[6].IMUX_G2_DATA[1]
TSTDCRBUSI27inputCELL_W[6].IMUX_G3_DATA[1]
TSTDCRBUSI28inputCELL_W[7].IMUX_G2_DATA[1]
TSTDCRBUSI29inputCELL_W[7].IMUX_G3_DATA[1]
TSTDCRBUSI3inputCELL_W[10].IMUX_G3_DATA[1]
TSTDCRBUSI30inputCELL_W[8].IMUX_G0_DATA[2]
TSTDCRBUSI31inputCELL_W[8].IMUX_G1_DATA[2]
TSTDCRBUSI4inputCELL_W[11].IMUX_G2_DATA[1]
TSTDCRBUSI5inputCELL_W[11].IMUX_G3_DATA[1]
TSTDCRBUSI6inputCELL_W[12].IMUX_G2_DATA[1]
TSTDCRBUSI7inputCELL_W[12].IMUX_G3_DATA[1]
TSTDCRBUSI8inputCELL_W[13].IMUX_G2_DATA[1]
TSTDCRBUSI9inputCELL_W[13].IMUX_G3_DATA[1]
TSTDCRBUSO0outputCELL_W[0].OUT_SEC_TMIN[9]
TSTDCRBUSO1outputCELL_W[0].OUT_SEC_TMIN[8]
TSTDCRBUSO10outputCELL_W[2].OUT_TEST[0]
TSTDCRBUSO11outputCELL_W[3].OUT_SEC_TMIN[10]
TSTDCRBUSO12outputCELL_W[3].OUT_SEC_TMIN[9]
TSTDCRBUSO13outputCELL_W[3].OUT_SEC_TMIN[8]
TSTDCRBUSO14outputCELL_W[3].OUT_TEST[0]
TSTDCRBUSO15outputCELL_W[4].OUT_SEC_TMIN[10]
TSTDCRBUSO16outputCELL_W[4].OUT_SEC_TMIN[9]
TSTDCRBUSO17outputCELL_W[4].OUT_SEC_TMIN[8]
TSTDCRBUSO18outputCELL_W[4].OUT_TEST[0]
TSTDCRBUSO19outputCELL_W[5].OUT_SEC_TMIN[10]
TSTDCRBUSO2outputCELL_W[0].OUT_TEST[0]
TSTDCRBUSO20outputCELL_W[5].OUT_SEC_TMIN[9]
TSTDCRBUSO21outputCELL_W[5].OUT_SEC_TMIN[8]
TSTDCRBUSO22outputCELL_W[5].OUT_TEST[0]
TSTDCRBUSO23outputCELL_W[6].OUT_SEC_TMIN[10]
TSTDCRBUSO24outputCELL_W[6].OUT_SEC_TMIN[9]
TSTDCRBUSO25outputCELL_W[6].OUT_SEC_TMIN[8]
TSTDCRBUSO26outputCELL_W[6].OUT_TEST[0]
TSTDCRBUSO27outputCELL_W[7].OUT_SEC_TMIN[10]
TSTDCRBUSO28outputCELL_W[7].OUT_SEC_TMIN[9]
TSTDCRBUSO29outputCELL_W[7].OUT_SEC_TMIN[8]
TSTDCRBUSO3outputCELL_W[1].OUT_SEC_TMIN[10]
TSTDCRBUSO30outputCELL_W[7].OUT_TEST[0]
TSTDCRBUSO31outputCELL_W[8].OUT_SEC_TMIN[10]
TSTDCRBUSO4outputCELL_W[1].OUT_SEC_TMIN[9]
TSTDCRBUSO5outputCELL_W[1].OUT_SEC_TMIN[8]
TSTDCRBUSO6outputCELL_W[1].OUT_TEST[0]
TSTDCRBUSO7outputCELL_W[2].OUT_SEC_TMIN[10]
TSTDCRBUSO8outputCELL_W[2].OUT_SEC_TMIN[9]
TSTDCRBUSO9outputCELL_W[2].OUT_SEC_TMIN[8]
TSTDSOCMABORTOPIinputCELL_W[11].IMUX_G0_DATA[3]
TSTDSOCMABORTOPOoutputCELL_W[13].OUT_SEC_TMIN[12]
TSTDSOCMABORTREQIinputCELL_W[11].IMUX_G1_DATA[3]
TSTDSOCMABORTREQOoutputCELL_W[14].OUT_SEC_TMIN[12]
TSTDSOCMABUSI0inputCELL_W[12].IMUX_G0_DATA[3]
TSTDSOCMABUSI1inputCELL_W[12].IMUX_G1_DATA[3]
TSTDSOCMABUSI10inputCELL_W[1].IMUX_G0_DATA[4]
TSTDSOCMABUSI11inputCELL_W[1].IMUX_G1_DATA[4]
TSTDSOCMABUSI12inputCELL_W[2].IMUX_G0_DATA[4]
TSTDSOCMABUSI13inputCELL_W[2].IMUX_G1_DATA[4]
TSTDSOCMABUSI14inputCELL_W[3].IMUX_G0_DATA[4]
TSTDSOCMABUSI15inputCELL_W[3].IMUX_G1_DATA[4]
TSTDSOCMABUSI16inputCELL_W[4].IMUX_G2_DATA[3]
TSTDSOCMABUSI17inputCELL_W[4].IMUX_G3_DATA[3]
TSTDSOCMABUSI18inputCELL_W[5].IMUX_G2_DATA[3]
TSTDSOCMABUSI19inputCELL_W[5].IMUX_G3_DATA[3]
TSTDSOCMABUSI2inputCELL_W[13].IMUX_G0_DATA[3]
TSTDSOCMABUSI20inputCELL_W[6].IMUX_G2_DATA[3]
TSTDSOCMABUSI21inputCELL_W[6].IMUX_G3_DATA[3]
TSTDSOCMABUSI22inputCELL_W[7].IMUX_G2_DATA[3]
TSTDSOCMABUSI23inputCELL_W[7].IMUX_G3_DATA[3]
TSTDSOCMABUSI24inputCELL_W[8].IMUX_G3_DATA[3]
TSTDSOCMABUSI25inputCELL_W[8].IMUX_G0_DATA[4]
TSTDSOCMABUSI26inputCELL_W[9].IMUX_G0_DATA[4]
TSTDSOCMABUSI27inputCELL_W[9].IMUX_G1_DATA[4]
TSTDSOCMABUSI28inputCELL_W[10].IMUX_G3_DATA[3]
TSTDSOCMABUSI29inputCELL_W[10].IMUX_G0_DATA[4]
TSTDSOCMABUSI3inputCELL_W[13].IMUX_G1_DATA[3]
TSTDSOCMABUSI4inputCELL_W[14].IMUX_G0_DATA[3]
TSTDSOCMABUSI5inputCELL_W[14].IMUX_G1_DATA[3]
TSTDSOCMABUSI6inputCELL_W[15].IMUX_G0_DATA[3]
TSTDSOCMABUSI7inputCELL_W[15].IMUX_G1_DATA[3]
TSTDSOCMABUSI8inputCELL_W[0].IMUX_G0_DATA[4]
TSTDSOCMABUSI9inputCELL_W[0].IMUX_G1_DATA[4]
TSTDSOCMABUSO0outputCELL_N[1].OUT_SEC_TMIN[12]
TSTDSOCMABUSO1outputCELL_N[2].OUT_SEC_TMIN[12]
TSTDSOCMABUSO10outputCELL_N[6].OUT_SEC_TMIN[10]
TSTDSOCMABUSO11outputCELL_N[6].OUT_SEC_TMIN[9]
TSTDSOCMABUSO12outputCELL_N[6].OUT_SEC_TMIN[8]
TSTDSOCMABUSO13outputCELL_N[1].OUT_SEC_TMIN[11]
TSTDSOCMABUSO14outputCELL_N[1].OUT_SEC_TMIN[10]
TSTDSOCMABUSO15outputCELL_N[2].OUT_SEC_TMIN[11]
TSTDSOCMABUSO16outputCELL_N[2].OUT_SEC_TMIN[10]
TSTDSOCMABUSO17outputCELL_N[3].OUT_SEC_TMIN[11]
TSTDSOCMABUSO18outputCELL_N[3].OUT_SEC_TMIN[10]
TSTDSOCMABUSO19outputCELL_N[4].OUT_SEC_TMIN[10]
TSTDSOCMABUSO2outputCELL_N[3].OUT_SEC_TMIN[12]
TSTDSOCMABUSO20outputCELL_N[4].OUT_SEC_TMIN[9]
TSTDSOCMABUSO21outputCELL_N[5].OUT_TEST[0]
TSTDSOCMABUSO22outputCELL_N[5].OUT_TEST[2]
TSTDSOCMABUSO23outputCELL_N[6].OUT_TEST[0]
TSTDSOCMABUSO24outputCELL_W[15].OUT_SEC_TMIN[12]
TSTDSOCMABUSO25outputCELL_W[0].OUT_SEC_TMIN[11]
TSTDSOCMABUSO26outputCELL_W[1].OUT_SEC_TMIN[11]
TSTDSOCMABUSO27outputCELL_W[2].OUT_SEC_TMIN[11]
TSTDSOCMABUSO28outputCELL_W[3].OUT_SEC_TMIN[11]
TSTDSOCMABUSO29outputCELL_W[4].OUT_SEC_TMIN[11]
TSTDSOCMABUSO3outputCELL_N[4].OUT_SEC_TMIN[12]
TSTDSOCMABUSO4outputCELL_N[4].OUT_SEC_TMIN[11]
TSTDSOCMABUSO5outputCELL_N[5].OUT_SEC_TMIN[11]
TSTDSOCMABUSO6outputCELL_N[5].OUT_SEC_TMIN[10]
TSTDSOCMABUSO7outputCELL_N[5].OUT_SEC_TMIN[9]
TSTDSOCMABUSO8outputCELL_N[5].OUT_SEC_TMIN[8]
TSTDSOCMABUSO9outputCELL_N[6].OUT_SEC_TMIN[11]
TSTDSOCMBYTEENI0inputCELL_W[11].IMUX_G2_DATA[3]
TSTDSOCMBYTEENI1inputCELL_W[11].IMUX_G3_DATA[3]
TSTDSOCMBYTEENI2inputCELL_W[12].IMUX_G2_DATA[3]
TSTDSOCMBYTEENI3inputCELL_W[12].IMUX_G3_DATA[3]
TSTDSOCMBYTEENO0outputCELL_W[5].OUT_SEC_TMIN[11]
TSTDSOCMBYTEENO1outputCELL_W[6].OUT_SEC_TMIN[11]
TSTDSOCMBYTEENO2outputCELL_W[7].OUT_SEC_TMIN[11]
TSTDSOCMBYTEENO3outputCELL_W[8].OUT_SEC_TMIN[11]
TSTDSOCMCOMPLETEIinputCELL_W[9].IMUX_G0_DATA[2]
TSTDSOCMDBUSI0inputCELL_W[6].IMUX_G1_DATA[3]
TSTDSOCMDBUSI1inputCELL_W[7].IMUX_G0_DATA[3]
TSTDSOCMDBUSI2inputCELL_W[7].IMUX_G1_DATA[3]
TSTDSOCMDBUSI3inputCELL_W[8].IMUX_G1_DATA[3]
TSTDSOCMDBUSI4inputCELL_W[8].IMUX_G2_DATA[3]
TSTDSOCMDBUSI5inputCELL_W[9].IMUX_G2_DATA[3]
TSTDSOCMDBUSI6inputCELL_W[9].IMUX_G3_DATA[3]
TSTDSOCMDBUSI7inputCELL_W[10].IMUX_G1_DATA[3]
TSTDSOCMDBUSO0outputCELL_W[8].OUT_SEC_TMIN[9]
TSTDSOCMDBUSO1outputCELL_W[8].OUT_SEC_TMIN[8]
TSTDSOCMDBUSO2outputCELL_W[8].OUT_TEST[0]
TSTDSOCMDBUSO3outputCELL_W[9].OUT_SEC_TMIN[10]
TSTDSOCMDBUSO4outputCELL_W[9].OUT_SEC_TMIN[9]
TSTDSOCMDBUSO5outputCELL_W[9].OUT_SEC_TMIN[8]
TSTDSOCMDBUSO6outputCELL_W[9].OUT_TEST[0]
TSTDSOCMDBUSO7outputCELL_W[10].OUT_SEC_TMIN[10]
TSTDSOCMDCRACKIinputCELL_W[10].IMUX_G2_DATA[3]
TSTDSOCMDCRACKOoutputCELL_W[10].OUT_SEC_TMIN[9]
TSTDSOCMHOLDIinputCELL_W[10].IMUX_G0_DATA[2]
TSTDSOCMHOLDOoutputCELL_W[5].OUT_TEST[2]
TSTDSOCMLOADREQIinputCELL_W[13].IMUX_G2_DATA[3]
TSTDSOCMLOADREQOoutputCELL_W[9].OUT_SEC_TMIN[11]
TSTDSOCMSTOREREQIinputCELL_W[13].IMUX_G3_DATA[3]
TSTDSOCMSTOREREQOoutputCELL_W[10].OUT_SEC_TMIN[11]
TSTDSOCMWAITIinputCELL_W[14].IMUX_G2_DATA[3]
TSTDSOCMWAITOoutputCELL_W[11].OUT_SEC_TMIN[11]
TSTDSOCMWRDBUSI0inputCELL_W[14].IMUX_G3_DATA[3]
TSTDSOCMWRDBUSI1inputCELL_W[15].IMUX_G2_DATA[3]
TSTDSOCMWRDBUSI10inputCELL_W[3].IMUX_G3_DATA[4]
TSTDSOCMWRDBUSI11inputCELL_W[4].IMUX_G0_DATA[4]
TSTDSOCMWRDBUSI12inputCELL_W[4].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI13inputCELL_W[5].IMUX_G0_DATA[4]
TSTDSOCMWRDBUSI14inputCELL_W[5].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI15inputCELL_W[6].IMUX_G0_DATA[4]
TSTDSOCMWRDBUSI16inputCELL_W[6].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI17inputCELL_W[7].IMUX_G0_DATA[4]
TSTDSOCMWRDBUSI18inputCELL_W[7].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI19inputCELL_W[8].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI2inputCELL_W[15].IMUX_G3_DATA[3]
TSTDSOCMWRDBUSI20inputCELL_W[8].IMUX_G2_DATA[4]
TSTDSOCMWRDBUSI21inputCELL_W[9].IMUX_G2_DATA[4]
TSTDSOCMWRDBUSI22inputCELL_W[9].IMUX_G3_DATA[4]
TSTDSOCMWRDBUSI23inputCELL_W[10].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI24inputCELL_W[10].IMUX_G2_DATA[4]
TSTDSOCMWRDBUSI25inputCELL_W[11].IMUX_G0_DATA[4]
TSTDSOCMWRDBUSI26inputCELL_W[11].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI27inputCELL_W[12].IMUX_G0_DATA[4]
TSTDSOCMWRDBUSI28inputCELL_W[12].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI29inputCELL_W[13].IMUX_G0_DATA[4]
TSTDSOCMWRDBUSI3inputCELL_W[0].IMUX_G2_DATA[4]
TSTDSOCMWRDBUSI30inputCELL_W[13].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI31inputCELL_W[14].IMUX_G0_DATA[4]
TSTDSOCMWRDBUSI4inputCELL_W[0].IMUX_G3_DATA[4]
TSTDSOCMWRDBUSI5inputCELL_W[1].IMUX_G2_DATA[4]
TSTDSOCMWRDBUSI6inputCELL_W[1].IMUX_G3_DATA[4]
TSTDSOCMWRDBUSI7inputCELL_W[2].IMUX_G2_DATA[4]
TSTDSOCMWRDBUSI8inputCELL_W[2].IMUX_G3_DATA[4]
TSTDSOCMWRDBUSI9inputCELL_W[3].IMUX_G2_DATA[4]
TSTDSOCMWRDBUSO0outputCELL_N[6].OUT_TEST[2]
TSTDSOCMWRDBUSO1outputCELL_N[0].OUT_SEC_TMIN[12]
TSTDSOCMWRDBUSO10outputCELL_N[5].OUT_TEST[4]
TSTDSOCMWRDBUSO11outputCELL_N[5].OUT_TEST[6]
TSTDSOCMWRDBUSO12outputCELL_N[6].OUT_TEST[4]
TSTDSOCMWRDBUSO13outputCELL_N[6].OUT_TEST[6]
TSTDSOCMWRDBUSO14outputCELL_N[0].OUT_SEC_TMIN[11]
TSTDSOCMWRDBUSO15outputCELL_N[0].OUT_SEC_TMIN[10]
TSTDSOCMWRDBUSO16outputCELL_N[1].OUT_TEST[0]
TSTDSOCMWRDBUSO17outputCELL_N[1].OUT_TEST[2]
TSTDSOCMWRDBUSO18outputCELL_N[2].OUT_TEST[0]
TSTDSOCMWRDBUSO19outputCELL_N[2].OUT_TEST[2]
TSTDSOCMWRDBUSO2outputCELL_N[1].OUT_SEC_TMIN[9]
TSTDSOCMWRDBUSO20outputCELL_N[3].OUT_TEST[0]
TSTDSOCMWRDBUSO21outputCELL_N[3].OUT_TEST[2]
TSTDSOCMWRDBUSO22outputCELL_N[4].OUT_TEST[2]
TSTDSOCMWRDBUSO23outputCELL_N[4].OUT_TEST[4]
TSTDSOCMWRDBUSO24outputCELL_N[5].OUT_TEST[8]
TSTDSOCMWRDBUSO25outputCELL_N[5].OUT_TEST[10]
TSTDSOCMWRDBUSO26outputCELL_N[6].OUT_TEST[8]
TSTDSOCMWRDBUSO27outputCELL_N[6].OUT_TEST[10]
TSTDSOCMWRDBUSO28outputCELL_N[0].OUT_SEC_TMIN[9]
TSTDSOCMWRDBUSO29outputCELL_N[1].OUT_TEST[4]
TSTDSOCMWRDBUSO3outputCELL_N[1].OUT_SEC_TMIN[8]
TSTDSOCMWRDBUSO30outputCELL_N[2].OUT_TEST[4]
TSTDSOCMWRDBUSO31outputCELL_N[3].OUT_TEST[4]
TSTDSOCMWRDBUSO4outputCELL_N[2].OUT_SEC_TMIN[9]
TSTDSOCMWRDBUSO5outputCELL_N[2].OUT_SEC_TMIN[8]
TSTDSOCMWRDBUSO6outputCELL_N[3].OUT_SEC_TMIN[9]
TSTDSOCMWRDBUSO7outputCELL_N[3].OUT_SEC_TMIN[8]
TSTDSOCMWRDBUSO8outputCELL_N[4].OUT_SEC_TMIN[8]
TSTDSOCMWRDBUSO9outputCELL_N[4].OUT_TEST[0]
TSTDSOCMXLATEVALIDIinputCELL_W[14].IMUX_G1_DATA[4]
TSTDSOCMXLATEVALIDOoutputCELL_W[12].OUT_SEC_TMIN[11]
TSTISOCMABORTIinputCELL_E[11].IMUX_G3_DATA[2]
TSTISOCMABORTOoutputCELL_S[0].OUT_TEST[2]
TSTISOCMABUSI0inputCELL_E[1].IMUX_G0_DATA[3]
TSTISOCMABUSI1inputCELL_E[1].IMUX_G1_DATA[3]
TSTISOCMABUSI10inputCELL_E[4].IMUX_G1_DATA[3]
TSTISOCMABUSI11inputCELL_E[5].IMUX_G1_DATA[3]
TSTISOCMABUSI12inputCELL_E[5].IMUX_G2_DATA[3]
TSTISOCMABUSI13inputCELL_E[6].IMUX_G2_DATA[3]
TSTISOCMABUSI14inputCELL_E[6].IMUX_G3_DATA[3]
TSTISOCMABUSI15inputCELL_E[6].IMUX_G0_DATA[4]
TSTISOCMABUSI16inputCELL_E[7].IMUX_G1_DATA[3]
TSTISOCMABUSI17inputCELL_E[7].IMUX_G2_DATA[3]
TSTISOCMABUSI18inputCELL_E[7].IMUX_G3_DATA[3]
TSTISOCMABUSI19inputCELL_E[8].IMUX_G1_DATA[3]
TSTISOCMABUSI2inputCELL_E[2].IMUX_G3_DATA[2]
TSTISOCMABUSI20inputCELL_E[8].IMUX_G2_DATA[3]
TSTISOCMABUSI21inputCELL_E[8].IMUX_G3_DATA[3]
TSTISOCMABUSI22inputCELL_E[9].IMUX_G1_DATA[3]
TSTISOCMABUSI23inputCELL_E[9].IMUX_G2_DATA[3]
TSTISOCMABUSI24inputCELL_E[9].IMUX_G3_DATA[3]
TSTISOCMABUSI25inputCELL_E[10].IMUX_G2_DATA[2]
TSTISOCMABUSI26inputCELL_E[10].IMUX_G3_DATA[2]
TSTISOCMABUSI27inputCELL_E[10].IMUX_G0_DATA[3]
TSTISOCMABUSI28inputCELL_E[10].IMUX_G1_DATA[3]
TSTISOCMABUSI29inputCELL_E[11].IMUX_G2_DATA[2]
TSTISOCMABUSI3inputCELL_E[2].IMUX_G0_DATA[3]
TSTISOCMABUSI4inputCELL_E[2].IMUX_G1_DATA[3]
TSTISOCMABUSI5inputCELL_E[3].IMUX_G2_DATA[2]
TSTISOCMABUSI6inputCELL_E[3].IMUX_G3_DATA[2]
TSTISOCMABUSI7inputCELL_E[3].IMUX_G0_DATA[3]
TSTISOCMABUSI8inputCELL_E[4].IMUX_G3_DATA[2]
TSTISOCMABUSI9inputCELL_E[4].IMUX_G0_DATA[3]
TSTISOCMABUSO0outputCELL_S[0].OUT_SEC_TMIN[8]
TSTISOCMABUSO1outputCELL_S[1].OUT_SEC_TMIN[13]
TSTISOCMABUSO10outputCELL_S[3].OUT_SEC_TMIN[14]
TSTISOCMABUSO11outputCELL_S[3].OUT_SEC_TMIN[13]
TSTISOCMABUSO12outputCELL_S[3].OUT_SEC_TMIN[12]
TSTISOCMABUSO13outputCELL_S[4].OUT_SEC_TMIN[15]
TSTISOCMABUSO14outputCELL_S[4].OUT_SEC_TMIN[14]
TSTISOCMABUSO15outputCELL_S[4].OUT_SEC_TMIN[13]
TSTISOCMABUSO16outputCELL_S[4].OUT_SEC_TMIN[12]
TSTISOCMABUSO17outputCELL_S[5].OUT_SEC_TMIN[15]
TSTISOCMABUSO18outputCELL_S[5].OUT_SEC_TMIN[14]
TSTISOCMABUSO19outputCELL_S[5].OUT_SEC_TMIN[13]
TSTISOCMABUSO2outputCELL_S[1].OUT_SEC_TMIN[12]
TSTISOCMABUSO20outputCELL_S[5].OUT_SEC_TMIN[12]
TSTISOCMABUSO21outputCELL_S[6].OUT_SEC_TMIN[11]
TSTISOCMABUSO22outputCELL_S[6].OUT_SEC_TMIN[10]
TSTISOCMABUSO23outputCELL_S[6].OUT_SEC_TMIN[9]
TSTISOCMABUSO24outputCELL_S[6].OUT_SEC_TMIN[8]
TSTISOCMABUSO25outputCELL_S[7].OUT_SEC_TMIN[14]
TSTISOCMABUSO26outputCELL_S[7].OUT_SEC_TMIN[13]
TSTISOCMABUSO27outputCELL_S[7].OUT_SEC_TMIN[12]
TSTISOCMABUSO28outputCELL_S[7].OUT_SEC_TMIN[11]
TSTISOCMABUSO29outputCELL_S[0].OUT_TEST[0]
TSTISOCMABUSO3outputCELL_S[1].OUT_SEC_TMIN[11]
TSTISOCMABUSO4outputCELL_S[1].OUT_SEC_TMIN[10]
TSTISOCMABUSO5outputCELL_S[2].OUT_SEC_TMIN[12]
TSTISOCMABUSO6outputCELL_S[2].OUT_SEC_TMIN[11]
TSTISOCMABUSO7outputCELL_S[2].OUT_SEC_TMIN[10]
TSTISOCMABUSO8outputCELL_S[2].OUT_SEC_TMIN[9]
TSTISOCMABUSO9outputCELL_S[3].OUT_SEC_TMIN[15]
TSTISOCMHOLDIinputCELL_E[2].IMUX_G1_DATA[2]
TSTISOCMHOLDOoutputCELL_E[2].OUT_SEC_TMIN[10]
TSTISOCMICUREADYIinputCELL_E[1].IMUX_G3_DATA[2]
TSTISOCMICUREADYOoutputCELL_S[0].OUT_SEC_TMIN[9]
TSTISOCMRDATAI0inputCELL_E[5].IMUX_G3_DATA[2]
TSTISOCMRDATAI1inputCELL_E[6].IMUX_G0_DATA[3]
TSTISOCMRDATAI10inputCELL_E[15].IMUX_G1_DATA[2]
TSTISOCMRDATAI11inputCELL_E[0].IMUX_G2_DATA[2]
TSTISOCMRDATAI12inputCELL_E[1].IMUX_G2_DATA[2]
TSTISOCMRDATAI13inputCELL_E[2].IMUX_G2_DATA[2]
TSTISOCMRDATAI14inputCELL_E[3].IMUX_G1_DATA[2]
TSTISOCMRDATAI15inputCELL_E[4].IMUX_G2_DATA[2]
TSTISOCMRDATAI16inputCELL_E[5].IMUX_G0_DATA[3]
TSTISOCMRDATAI17inputCELL_S[0].IMUX_G0_DATA[4]
TSTISOCMRDATAI18inputCELL_S[0].IMUX_G1_DATA[4]
TSTISOCMRDATAI19inputCELL_S[0].IMUX_G2_DATA[4]
TSTISOCMRDATAI2inputCELL_E[7].IMUX_G0_DATA[3]
TSTISOCMRDATAI20inputCELL_S[0].IMUX_G3_DATA[4]
TSTISOCMRDATAI21inputCELL_S[1].IMUX_G0_DATA[4]
TSTISOCMRDATAI22inputCELL_S[1].IMUX_G1_DATA[4]
TSTISOCMRDATAI23inputCELL_S[1].IMUX_G2_DATA[4]
TSTISOCMRDATAI24inputCELL_S[1].IMUX_G3_DATA[4]
TSTISOCMRDATAI25inputCELL_S[2].IMUX_G2_DATA[0]
TSTISOCMRDATAI26inputCELL_S[2].IMUX_G3_DATA[0]
TSTISOCMRDATAI27inputCELL_S[2].IMUX_G0_DATA[1]
TSTISOCMRDATAI28inputCELL_S[2].IMUX_G1_DATA[1]
TSTISOCMRDATAI29inputCELL_S[3].IMUX_G0_DATA[0]
TSTISOCMRDATAI3inputCELL_E[8].IMUX_G0_DATA[3]
TSTISOCMRDATAI30inputCELL_S[3].IMUX_G1_DATA[0]
TSTISOCMRDATAI31inputCELL_S[3].IMUX_G2_DATA[0]
TSTISOCMRDATAI32inputCELL_S[3].IMUX_G3_DATA[0]
TSTISOCMRDATAI33inputCELL_S[4].IMUX_G1_DATA[0]
TSTISOCMRDATAI34inputCELL_S[4].IMUX_G2_DATA[0]
TSTISOCMRDATAI35inputCELL_S[4].IMUX_G3_DATA[0]
TSTISOCMRDATAI36inputCELL_S[4].IMUX_G0_DATA[1]
TSTISOCMRDATAI37inputCELL_S[5].IMUX_G2_DATA[0]
TSTISOCMRDATAI38inputCELL_S[5].IMUX_G3_DATA[0]
TSTISOCMRDATAI39inputCELL_S[5].IMUX_G0_DATA[1]
TSTISOCMRDATAI4inputCELL_E[9].IMUX_G0_DATA[3]
TSTISOCMRDATAI40inputCELL_S[5].IMUX_G1_DATA[1]
TSTISOCMRDATAI41inputCELL_S[6].IMUX_G0_DATA[4]
TSTISOCMRDATAI42inputCELL_S[6].IMUX_G1_DATA[4]
TSTISOCMRDATAI43inputCELL_S[6].IMUX_G2_DATA[4]
TSTISOCMRDATAI44inputCELL_S[6].IMUX_G3_DATA[4]
TSTISOCMRDATAI45inputCELL_S[7].IMUX_G0_DATA[4]
TSTISOCMRDATAI46inputCELL_S[7].IMUX_G1_DATA[4]
TSTISOCMRDATAI47inputCELL_S[7].IMUX_G2_DATA[4]
TSTISOCMRDATAI48inputCELL_S[7].IMUX_G3_DATA[4]
TSTISOCMRDATAI49inputCELL_S[0].IMUX_G0_DATA[5]
TSTISOCMRDATAI5inputCELL_E[10].IMUX_G1_DATA[2]
TSTISOCMRDATAI50inputCELL_S[0].IMUX_G1_DATA[5]
TSTISOCMRDATAI51inputCELL_S[1].IMUX_G0_DATA[5]
TSTISOCMRDATAI52inputCELL_S[1].IMUX_G1_DATA[5]
TSTISOCMRDATAI53inputCELL_S[2].IMUX_G2_DATA[1]
TSTISOCMRDATAI54inputCELL_S[2].IMUX_G3_DATA[1]
TSTISOCMRDATAI55inputCELL_S[3].IMUX_G0_DATA[1]
TSTISOCMRDATAI56inputCELL_S[3].IMUX_G1_DATA[1]
TSTISOCMRDATAI57inputCELL_S[4].IMUX_G1_DATA[1]
TSTISOCMRDATAI58inputCELL_S[4].IMUX_G2_DATA[1]
TSTISOCMRDATAI59inputCELL_S[5].IMUX_G2_DATA[1]
TSTISOCMRDATAI6inputCELL_E[11].IMUX_G1_DATA[2]
TSTISOCMRDATAI60inputCELL_S[5].IMUX_G3_DATA[1]
TSTISOCMRDATAI61inputCELL_S[6].IMUX_G0_DATA[5]
TSTISOCMRDATAI62inputCELL_S[6].IMUX_G1_DATA[5]
TSTISOCMRDATAI63inputCELL_S[7].IMUX_G0_DATA[5]
TSTISOCMRDATAI7inputCELL_E[12].IMUX_G1_DATA[2]
TSTISOCMRDATAI8inputCELL_E[13].IMUX_G1_DATA[2]
TSTISOCMRDATAI9inputCELL_E[14].IMUX_G1_DATA[2]
TSTISOCMRDATAO0outputCELL_E[2].OUT_TEST[0]
TSTISOCMRDATAO1outputCELL_E[3].OUT_SEC_TMIN[10]
TSTISOCMRDATAO10outputCELL_E[5].OUT_SEC_TMIN[10]
TSTISOCMRDATAO11outputCELL_E[5].OUT_SEC_TMIN[9]
TSTISOCMRDATAO12outputCELL_E[5].OUT_SEC_TMIN[8]
TSTISOCMRDATAO13outputCELL_E[6].OUT_SEC_TMIN[11]
TSTISOCMRDATAO14outputCELL_E[6].OUT_SEC_TMIN[10]
TSTISOCMRDATAO15outputCELL_E[6].OUT_SEC_TMIN[9]
TSTISOCMRDATAO16outputCELL_E[6].OUT_SEC_TMIN[8]
TSTISOCMRDATAO17outputCELL_E[7].OUT_SEC_TMIN[11]
TSTISOCMRDATAO18outputCELL_E[7].OUT_SEC_TMIN[10]
TSTISOCMRDATAO19outputCELL_E[7].OUT_SEC_TMIN[9]
TSTISOCMRDATAO2outputCELL_E[3].OUT_SEC_TMIN[9]
TSTISOCMRDATAO20outputCELL_E[7].OUT_SEC_TMIN[8]
TSTISOCMRDATAO21outputCELL_E[8].OUT_SEC_TMIN[11]
TSTISOCMRDATAO22outputCELL_E[8].OUT_SEC_TMIN[10]
TSTISOCMRDATAO23outputCELL_E[8].OUT_SEC_TMIN[9]
TSTISOCMRDATAO24outputCELL_E[8].OUT_SEC_TMIN[8]
TSTISOCMRDATAO25outputCELL_E[9].OUT_SEC_TMIN[11]
TSTISOCMRDATAO26outputCELL_E[9].OUT_SEC_TMIN[10]
TSTISOCMRDATAO27outputCELL_E[9].OUT_SEC_TMIN[9]
TSTISOCMRDATAO28outputCELL_E[9].OUT_SEC_TMIN[8]
TSTISOCMRDATAO29outputCELL_E[10].OUT_SEC_TMIN[11]
TSTISOCMRDATAO3outputCELL_E[3].OUT_SEC_TMIN[8]
TSTISOCMRDATAO30outputCELL_E[10].OUT_SEC_TMIN[10]
TSTISOCMRDATAO31outputCELL_E[10].OUT_SEC_TMIN[9]
TSTISOCMRDATAO32outputCELL_E[10].OUT_SEC_TMIN[8]
TSTISOCMRDATAO33outputCELL_E[11].OUT_SEC_TMIN[11]
TSTISOCMRDATAO34outputCELL_E[11].OUT_SEC_TMIN[10]
TSTISOCMRDATAO35outputCELL_E[11].OUT_SEC_TMIN[9]
TSTISOCMRDATAO36outputCELL_E[11].OUT_SEC_TMIN[8]
TSTISOCMRDATAO37outputCELL_E[12].OUT_SEC_TMIN[11]
TSTISOCMRDATAO38outputCELL_E[12].OUT_SEC_TMIN[10]
TSTISOCMRDATAO39outputCELL_E[12].OUT_SEC_TMIN[9]
TSTISOCMRDATAO4outputCELL_E[3].OUT_TEST[0]
TSTISOCMRDATAO40outputCELL_E[12].OUT_SEC_TMIN[8]
TSTISOCMRDATAO41outputCELL_E[13].OUT_SEC_TMIN[11]
TSTISOCMRDATAO42outputCELL_E[13].OUT_SEC_TMIN[10]
TSTISOCMRDATAO43outputCELL_E[13].OUT_SEC_TMIN[9]
TSTISOCMRDATAO44outputCELL_E[13].OUT_SEC_TMIN[8]
TSTISOCMRDATAO45outputCELL_E[14].OUT_SEC_TMIN[11]
TSTISOCMRDATAO46outputCELL_E[14].OUT_SEC_TMIN[10]
TSTISOCMRDATAO47outputCELL_E[14].OUT_SEC_TMIN[9]
TSTISOCMRDATAO48outputCELL_E[14].OUT_SEC_TMIN[8]
TSTISOCMRDATAO49outputCELL_E[15].OUT_SEC_TMIN[11]
TSTISOCMRDATAO5outputCELL_E[4].OUT_SEC_TMIN[11]
TSTISOCMRDATAO50outputCELL_E[15].OUT_SEC_TMIN[10]
TSTISOCMRDATAO51outputCELL_E[15].OUT_SEC_TMIN[9]
TSTISOCMRDATAO52outputCELL_E[15].OUT_SEC_TMIN[8]
TSTISOCMRDATAO53outputCELL_E[0].OUT_TEST[2]
TSTISOCMRDATAO54outputCELL_E[0].OUT_TEST[4]
TSTISOCMRDATAO55outputCELL_E[1].OUT_TEST[2]
TSTISOCMRDATAO56outputCELL_E[1].OUT_TEST[4]
TSTISOCMRDATAO57outputCELL_E[2].OUT_TEST[2]
TSTISOCMRDATAO58outputCELL_E[2].OUT_TEST[4]
TSTISOCMRDATAO59outputCELL_E[3].OUT_TEST[2]
TSTISOCMRDATAO6outputCELL_E[4].OUT_SEC_TMIN[10]
TSTISOCMRDATAO60outputCELL_E[3].OUT_TEST[4]
TSTISOCMRDATAO61outputCELL_E[4].OUT_TEST[0]
TSTISOCMRDATAO62outputCELL_E[4].OUT_TEST[2]
TSTISOCMRDATAO63outputCELL_E[5].OUT_TEST[0]
TSTISOCMRDATAO7outputCELL_E[4].OUT_SEC_TMIN[9]
TSTISOCMRDATAO8outputCELL_E[4].OUT_SEC_TMIN[8]
TSTISOCMRDATAO9outputCELL_E[5].OUT_SEC_TMIN[11]
TSTISOCMRDDVALIDI0inputCELL_E[3].IMUX_G0_DATA[2]
TSTISOCMRDDVALIDI1inputCELL_E[4].IMUX_G1_DATA[2]
TSTISOCMRDDVALIDO0outputCELL_E[2].OUT_SEC_TMIN[9]
TSTISOCMRDDVALIDO1outputCELL_E[2].OUT_SEC_TMIN[8]
TSTISOCMREQPENDIinputCELL_E[0].IMUX_G0_DATA[3]
TSTISOCMREQPENDOoutputCELL_S[0].OUT_SEC_TMIN[10]
TSTISOCMXLATEVALIDIinputCELL_E[0].IMUX_G3_DATA[2]
TSTISOCMXLATEVALIDOoutputCELL_S[0].OUT_SEC_TMIN[11]
TSTISOPFWDIinputCELL_W[9].IMUX_G1_DATA[2]
TSTISOPFWDOoutputCELL_W[5].OUT_TEST[4]
TSTJTAGENIinputCELL_E[12].IMUX_G0_DATA[2]
TSTJTAGENOoutputCELL_E[0].OUT_TEST[0]
TSTOCMCOMPLETEOoutputCELL_W[6].OUT_TEST[2]
TSTPLBSAMPLECYCLEIinputCELL_E[6].IMUX_G1_DATA[3]
TSTPLBSAMPLECYCLEOoutputCELL_E[5].OUT_TEST[2]
TSTRDDBUSI0inputCELL_W[10].IMUX_G1_DATA[2]
TSTRDDBUSI1inputCELL_W[11].IMUX_G0_DATA[2]
TSTRDDBUSI10inputCELL_W[15].IMUX_G1_DATA[2]
TSTRDDBUSI11inputCELL_W[0].IMUX_G2_DATA[2]
TSTRDDBUSI12inputCELL_W[0].IMUX_G3_DATA[2]
TSTRDDBUSI13inputCELL_W[1].IMUX_G2_DATA[2]
TSTRDDBUSI14inputCELL_W[1].IMUX_G3_DATA[2]
TSTRDDBUSI15inputCELL_W[2].IMUX_G2_DATA[2]
TSTRDDBUSI16inputCELL_W[2].IMUX_G3_DATA[2]
TSTRDDBUSI17inputCELL_W[3].IMUX_G2_DATA[2]
TSTRDDBUSI18inputCELL_W[3].IMUX_G3_DATA[2]
TSTRDDBUSI19inputCELL_W[4].IMUX_G0_DATA[2]
TSTRDDBUSI2inputCELL_W[11].IMUX_G1_DATA[2]
TSTRDDBUSI20inputCELL_W[4].IMUX_G1_DATA[2]
TSTRDDBUSI21inputCELL_W[5].IMUX_G0_DATA[2]
TSTRDDBUSI22inputCELL_W[5].IMUX_G1_DATA[2]
TSTRDDBUSI23inputCELL_W[6].IMUX_G0_DATA[2]
TSTRDDBUSI24inputCELL_W[6].IMUX_G1_DATA[2]
TSTRDDBUSI25inputCELL_W[7].IMUX_G0_DATA[2]
TSTRDDBUSI26inputCELL_W[7].IMUX_G1_DATA[2]
TSTRDDBUSI27inputCELL_W[8].IMUX_G2_DATA[2]
TSTRDDBUSI28inputCELL_W[8].IMUX_G3_DATA[2]
TSTRDDBUSI29inputCELL_W[9].IMUX_G2_DATA[2]
TSTRDDBUSI3inputCELL_W[12].IMUX_G0_DATA[2]
TSTRDDBUSI30inputCELL_W[9].IMUX_G3_DATA[2]
TSTRDDBUSI31inputCELL_W[10].IMUX_G2_DATA[2]
TSTRDDBUSI4inputCELL_W[12].IMUX_G1_DATA[2]
TSTRDDBUSI5inputCELL_W[13].IMUX_G0_DATA[2]
TSTRDDBUSI6inputCELL_W[13].IMUX_G1_DATA[2]
TSTRDDBUSI7inputCELL_W[14].IMUX_G0_DATA[2]
TSTRDDBUSI8inputCELL_W[14].IMUX_G1_DATA[2]
TSTRDDBUSI9inputCELL_W[15].IMUX_G0_DATA[2]
TSTRDDBUSO0outputCELL_W[10].OUT_SEC_TMIN[8]
TSTRDDBUSO1outputCELL_W[10].OUT_TEST[0]
TSTRDDBUSO10outputCELL_W[13].OUT_SEC_TMIN[11]
TSTRDDBUSO11outputCELL_W[13].OUT_SEC_TMIN[10]
TSTRDDBUSO12outputCELL_W[13].OUT_SEC_TMIN[9]
TSTRDDBUSO13outputCELL_W[13].OUT_SEC_TMIN[8]
TSTRDDBUSO14outputCELL_W[14].OUT_SEC_TMIN[11]
TSTRDDBUSO15outputCELL_W[14].OUT_SEC_TMIN[10]
TSTRDDBUSO16outputCELL_W[14].OUT_SEC_TMIN[9]
TSTRDDBUSO17outputCELL_W[14].OUT_SEC_TMIN[8]
TSTRDDBUSO18outputCELL_W[15].OUT_SEC_TMIN[11]
TSTRDDBUSO19outputCELL_W[15].OUT_SEC_TMIN[10]
TSTRDDBUSO2outputCELL_W[11].OUT_SEC_TMIN[10]
TSTRDDBUSO20outputCELL_W[15].OUT_SEC_TMIN[9]
TSTRDDBUSO21outputCELL_W[15].OUT_SEC_TMIN[8]
TSTRDDBUSO22outputCELL_W[0].OUT_TEST[2]
TSTRDDBUSO23outputCELL_W[0].OUT_TEST[4]
TSTRDDBUSO24outputCELL_W[1].OUT_TEST[2]
TSTRDDBUSO25outputCELL_W[1].OUT_TEST[4]
TSTRDDBUSO26outputCELL_W[2].OUT_TEST[2]
TSTRDDBUSO27outputCELL_W[2].OUT_TEST[4]
TSTRDDBUSO28outputCELL_W[3].OUT_TEST[2]
TSTRDDBUSO29outputCELL_W[3].OUT_TEST[4]
TSTRDDBUSO3outputCELL_W[11].OUT_SEC_TMIN[9]
TSTRDDBUSO30outputCELL_W[4].OUT_TEST[2]
TSTRDDBUSO31outputCELL_W[4].OUT_TEST[4]
TSTRDDBUSO4outputCELL_W[11].OUT_SEC_TMIN[8]
TSTRDDBUSO5outputCELL_W[11].OUT_TEST[0]
TSTRDDBUSO6outputCELL_W[12].OUT_SEC_TMIN[10]
TSTRDDBUSO7outputCELL_W[12].OUT_SEC_TMIN[9]
TSTRDDBUSO8outputCELL_W[12].OUT_SEC_TMIN[8]
TSTRDDBUSO9outputCELL_W[12].OUT_TEST[0]
TSTRESETCHIPIinputCELL_E[0].IMUX_G0_DATA[2]
TSTRESETCHIPOoutputCELL_E[0].OUT_SEC_TMIN[10]
TSTRESETCOREIinputCELL_E[5].IMUX_G2_DATA[2]
TSTRESETCOREOoutputCELL_E[0].OUT_SEC_TMIN[9]
TSTRESETSYSIinputCELL_E[11].IMUX_G0_DATA[2]
TSTRESETSYSOoutputCELL_E[0].OUT_SEC_TMIN[8]
TSTTIMERENIinputCELL_E[13].IMUX_G0_DATA[2]
TSTTIMERENOoutputCELL_E[1].OUT_SEC_TMIN[10]
TSTTRSTNEGIinputCELL_N[2].IMUX_G2_DATA[0]
TSTTRSTNEGOoutputCELL_E[12].OUT_TEST[0]

Bel wires

virtex2 PPC_W bel wires
WirePins
CELL_W[0].IMUX_G0_DATA[0]PPC405.APUC405DCDAPUOP
CELL_W[0].IMUX_G0_DATA[1]PPC405.APUC405EXERESULT21
CELL_W[0].IMUX_G0_DATA[2]PPC405.TSTDCRBUSI14
CELL_W[0].IMUX_G0_DATA[3]PPC405.TSTC405DCRABUSI0
CELL_W[0].IMUX_G0_DATA[4]PPC405.TSTDSOCMABUSI8
CELL_W[0].IMUX_G1_DATA[0]PPC405.APUC405DCDCREN
CELL_W[0].IMUX_G1_DATA[1]PPC405.APUC405EXERESULT22
CELL_W[0].IMUX_G1_DATA[2]PPC405.TSTDCRBUSI15
CELL_W[0].IMUX_G1_DATA[3]PPC405.TSTC405DCRABUSI1
CELL_W[0].IMUX_G1_DATA[4]PPC405.TSTDSOCMABUSI9
CELL_W[0].IMUX_G2_DATA[0]PPC405.APUC405DCDFORCEALGN
CELL_W[0].IMUX_G2_DATA[1]PPC405.DCRC405DBUSIN14
CELL_W[0].IMUX_G2_DATA[2]PPC405.TSTRDDBUSI11
CELL_W[0].IMUX_G2_DATA[3]PPC405.TSTC405DCRDBUSOUTI21
CELL_W[0].IMUX_G2_DATA[4]PPC405.TSTDSOCMWRDBUSI3
CELL_W[0].IMUX_G3_DATA[0]PPC405.APUC405DCDFORCEBESTEERING
CELL_W[0].IMUX_G3_DATA[1]PPC405.DCRC405DBUSIN15
CELL_W[0].IMUX_G3_DATA[2]PPC405.TSTRDDBUSI12
CELL_W[0].IMUX_G3_DATA[3]PPC405.TSTC405DCRDBUSOUTI22
CELL_W[0].IMUX_G3_DATA[4]PPC405.TSTDSOCMWRDBUSI4
CELL_W[0].OUT_FAN_TMIN[0]PPC405.C405APUDCDFULL
CELL_W[0].OUT_FAN_TMIN[1]PPC405.C405APUDCDHOLD
CELL_W[0].OUT_FAN_TMIN[2]PPC405.C405APUDCDINSTRUCTION0
CELL_W[0].OUT_FAN_TMIN[3]PPC405.C405APUDCDINSTRUCTION1
CELL_W[0].OUT_FAN_TMIN[4]PPC405.C405APUEXELOADDBUS28
CELL_W[0].OUT_FAN_TMIN[5]PPC405.C405APUEXELOADDBUS29
CELL_W[0].OUT_FAN_TMIN[6]PPC405.C405APUEXERADATA27
CELL_W[0].OUT_FAN_TMIN[7]PPC405.C405APUEXERADATA28
CELL_W[0].OUT_SEC_TMIN[8]PPC405.TSTDCRBUSO1
CELL_W[0].OUT_SEC_TMIN[9]PPC405.TSTDCRBUSO0
CELL_W[0].OUT_SEC_TMIN[10]PPC405.TSTDCRACKO
CELL_W[0].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO25
CELL_W[0].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT21
CELL_W[0].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT5
CELL_W[0].OUT_SEC_TMIN[14]PPC405.C405APUEXERBDATA28
CELL_W[0].OUT_SEC_TMIN[15]PPC405.C405APUEXERBDATA27
CELL_W[0].OUT_TEST[0]PPC405.TSTDCRBUSO2
CELL_W[0].OUT_TEST[2]PPC405.TSTRDDBUSO22
CELL_W[0].OUT_TEST[4]PPC405.TSTRDDBUSO23
CELL_W[1].IMUX_G0_DATA[0]PPC405.APUC405DCDFPUOP
CELL_W[1].IMUX_G0_DATA[1]PPC405.APUC405EXERESULT23
CELL_W[1].IMUX_G0_DATA[2]PPC405.TSTDCRBUSI16
CELL_W[1].IMUX_G0_DATA[3]PPC405.TSTC405DCRABUSI2
CELL_W[1].IMUX_G0_DATA[4]PPC405.TSTDSOCMABUSI10
CELL_W[1].IMUX_G1_DATA[0]PPC405.APUC405DCDGPRWRITE
CELL_W[1].IMUX_G1_DATA[1]PPC405.APUC405EXERESULT24
CELL_W[1].IMUX_G1_DATA[2]PPC405.TSTDCRBUSI17
CELL_W[1].IMUX_G1_DATA[3]PPC405.TSTC405DCRABUSI3
CELL_W[1].IMUX_G1_DATA[4]PPC405.TSTDSOCMABUSI11
CELL_W[1].IMUX_G2_DATA[0]PPC405.APUC405DCDLDSTBYTE
CELL_W[1].IMUX_G2_DATA[1]PPC405.DCRC405DBUSIN16
CELL_W[1].IMUX_G2_DATA[2]PPC405.TSTRDDBUSI13
CELL_W[1].IMUX_G2_DATA[3]PPC405.TSTC405DCRDBUSOUTI23
CELL_W[1].IMUX_G2_DATA[4]PPC405.TSTDSOCMWRDBUSI5
CELL_W[1].IMUX_G3_DATA[0]PPC405.APUC405DCDLDSTDW
CELL_W[1].IMUX_G3_DATA[1]PPC405.DCRC405DBUSIN17
CELL_W[1].IMUX_G3_DATA[2]PPC405.TSTRDDBUSI14
CELL_W[1].IMUX_G3_DATA[3]PPC405.TSTC405DCRDBUSOUTI24
CELL_W[1].IMUX_G3_DATA[4]PPC405.TSTDSOCMWRDBUSI6
CELL_W[1].OUT_FAN_TMIN[0]PPC405.C405APUDCDINSTRUCTION2
CELL_W[1].OUT_FAN_TMIN[1]PPC405.C405APUDCDINSTRUCTION3
CELL_W[1].OUT_FAN_TMIN[2]PPC405.C405APUDCDINSTRUCTION4
CELL_W[1].OUT_FAN_TMIN[3]PPC405.C405APUDCDINSTRUCTION5
CELL_W[1].OUT_FAN_TMIN[4]PPC405.C405APUEXELOADDBUS30
CELL_W[1].OUT_FAN_TMIN[5]PPC405.C405APUEXELOADDBUS31
CELL_W[1].OUT_FAN_TMIN[6]PPC405.C405APUEXERADATA29
CELL_W[1].OUT_FAN_TMIN[7]PPC405.C405APUEXERADATA30
CELL_W[1].OUT_SEC_TMIN[8]PPC405.TSTDCRBUSO5
CELL_W[1].OUT_SEC_TMIN[9]PPC405.TSTDCRBUSO4
CELL_W[1].OUT_SEC_TMIN[10]PPC405.TSTDCRBUSO3
CELL_W[1].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO26
CELL_W[1].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT22
CELL_W[1].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT6
CELL_W[1].OUT_SEC_TMIN[14]PPC405.C405APUEXERBDATA30
CELL_W[1].OUT_SEC_TMIN[15]PPC405.C405APUEXERBDATA29
CELL_W[1].OUT_TEST[0]PPC405.TSTDCRBUSO6
CELL_W[1].OUT_TEST[2]PPC405.TSTRDDBUSO24
CELL_W[1].OUT_TEST[4]PPC405.TSTRDDBUSO25
CELL_W[2].IMUX_G0_DATA[0]PPC405.APUC405DCDLDSTHW
CELL_W[2].IMUX_G0_DATA[1]PPC405.APUC405EXERESULT25
CELL_W[2].IMUX_G0_DATA[2]PPC405.TSTDCRBUSI18
CELL_W[2].IMUX_G0_DATA[3]PPC405.TSTC405DCRABUSI4
CELL_W[2].IMUX_G0_DATA[4]PPC405.TSTDSOCMABUSI12
CELL_W[2].IMUX_G1_DATA[0]PPC405.APUC405DCDLDSTQW
CELL_W[2].IMUX_G1_DATA[1]PPC405.APUC405EXERESULT26
CELL_W[2].IMUX_G1_DATA[2]PPC405.TSTDCRBUSI19
CELL_W[2].IMUX_G1_DATA[3]PPC405.TSTC405DCRABUSI5
CELL_W[2].IMUX_G1_DATA[4]PPC405.TSTDSOCMABUSI13
CELL_W[2].IMUX_G2_DATA[0]PPC405.APUC405DCDLDSTWD
CELL_W[2].IMUX_G2_DATA[1]PPC405.DCRC405DBUSIN18
CELL_W[2].IMUX_G2_DATA[2]PPC405.TSTRDDBUSI15
CELL_W[2].IMUX_G2_DATA[3]PPC405.TSTC405DCRDBUSOUTI25
CELL_W[2].IMUX_G2_DATA[4]PPC405.TSTDSOCMWRDBUSI7
CELL_W[2].IMUX_G3_DATA[0]PPC405.APUC405DCDLOAD
CELL_W[2].IMUX_G3_DATA[1]PPC405.DCRC405DBUSIN19
CELL_W[2].IMUX_G3_DATA[2]PPC405.TSTRDDBUSI16
CELL_W[2].IMUX_G3_DATA[3]PPC405.TSTC405DCRDBUSOUTI26
CELL_W[2].IMUX_G3_DATA[4]PPC405.TSTDSOCMWRDBUSI8
CELL_W[2].OUT_FAN_TMIN[0]PPC405.C405APUDCDINSTRUCTION6
CELL_W[2].OUT_FAN_TMIN[1]PPC405.C405APUDCDINSTRUCTION7
CELL_W[2].OUT_FAN_TMIN[2]PPC405.C405APUDCDINSTRUCTION8
CELL_W[2].OUT_FAN_TMIN[3]PPC405.C405APUDCDINSTRUCTION9
CELL_W[2].OUT_FAN_TMIN[4]PPC405.C405APUEXELOADDVALID
CELL_W[2].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA0
CELL_W[2].OUT_FAN_TMIN[6]PPC405.C405APUEXERADATA31
CELL_W[2].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA0
CELL_W[2].OUT_SEC_TMIN[8]PPC405.TSTDCRBUSO9
CELL_W[2].OUT_SEC_TMIN[9]PPC405.TSTDCRBUSO8
CELL_W[2].OUT_SEC_TMIN[10]PPC405.TSTDCRBUSO7
CELL_W[2].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO27
CELL_W[2].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT23
CELL_W[2].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT7
CELL_W[2].OUT_SEC_TMIN[14]PPC405.C405APUEXEWDCNT0
CELL_W[2].OUT_SEC_TMIN[15]PPC405.C405APUEXERBDATA31
CELL_W[2].OUT_TEST[0]PPC405.TSTDCRBUSO10
CELL_W[2].OUT_TEST[2]PPC405.TSTRDDBUSO26
CELL_W[2].OUT_TEST[4]PPC405.TSTRDDBUSO27
CELL_W[3].IMUX_G0_DATA[0]PPC405.APUC405DCDPRIVOP
CELL_W[3].IMUX_G0_DATA[1]PPC405.APUC405EXERESULT27
CELL_W[3].IMUX_G0_DATA[2]PPC405.TSTDCRBUSI20
CELL_W[3].IMUX_G0_DATA[3]PPC405.TSTC405DCRABUSI6
CELL_W[3].IMUX_G0_DATA[4]PPC405.TSTDSOCMABUSI14
CELL_W[3].IMUX_G1_DATA[0]PPC405.APUC405DCDRAEN
CELL_W[3].IMUX_G1_DATA[1]PPC405.APUC405EXERESULT28
CELL_W[3].IMUX_G1_DATA[2]PPC405.TSTDCRBUSI21
CELL_W[3].IMUX_G1_DATA[3]PPC405.TSTC405DCRABUSI7
CELL_W[3].IMUX_G1_DATA[4]PPC405.TSTDSOCMABUSI15
CELL_W[3].IMUX_G2_DATA[0]PPC405.APUC405DCDRBEN
CELL_W[3].IMUX_G2_DATA[1]PPC405.DCRC405DBUSIN20
CELL_W[3].IMUX_G2_DATA[2]PPC405.TSTRDDBUSI17
CELL_W[3].IMUX_G2_DATA[3]PPC405.TSTC405DCRDBUSOUTI27
CELL_W[3].IMUX_G2_DATA[4]PPC405.TSTDSOCMWRDBUSI9
CELL_W[3].IMUX_G3_DATA[0]PPC405.APUC405DCDSTORE
CELL_W[3].IMUX_G3_DATA[1]PPC405.DCRC405DBUSIN21
CELL_W[3].IMUX_G3_DATA[2]PPC405.TSTRDDBUSI18
CELL_W[3].IMUX_G3_DATA[3]PPC405.TSTC405DCRDBUSOUTI28
CELL_W[3].IMUX_G3_DATA[4]PPC405.TSTDSOCMWRDBUSI10
CELL_W[3].OUT_FAN_TMIN[0]PPC405.C405APUDCDINSTRUCTION10
CELL_W[3].OUT_FAN_TMIN[1]PPC405.C405APUDCDINSTRUCTION11
CELL_W[3].OUT_FAN_TMIN[2]PPC405.C405APUDCDINSTRUCTION12
CELL_W[3].OUT_FAN_TMIN[3]PPC405.C405APUDCDINSTRUCTION13
CELL_W[3].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA1
CELL_W[3].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA2
CELL_W[3].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA1
CELL_W[3].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA2
CELL_W[3].OUT_SEC_TMIN[8]PPC405.TSTDCRBUSO13
CELL_W[3].OUT_SEC_TMIN[9]PPC405.TSTDCRBUSO12
CELL_W[3].OUT_SEC_TMIN[10]PPC405.TSTDCRBUSO11
CELL_W[3].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO28
CELL_W[3].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT24
CELL_W[3].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT8
CELL_W[3].OUT_SEC_TMIN[14]PPC405.C405APUMSRFE0
CELL_W[3].OUT_SEC_TMIN[15]PPC405.C405APUEXEWDCNT1
CELL_W[3].OUT_TEST[0]PPC405.TSTDCRBUSO14
CELL_W[3].OUT_TEST[2]PPC405.TSTRDDBUSO28
CELL_W[3].OUT_TEST[4]PPC405.TSTRDDBUSO29
CELL_W[4].IMUX_TI[0]PPC405.TIEC405APUDIVEN
CELL_W[4].IMUX_TI[1]PPC405.TIEC405APUPRESENT
CELL_W[4].IMUX_G0_DATA[0]PPC405.APUC405DCDTRAPBE
CELL_W[4].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN22
CELL_W[4].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI19
CELL_W[4].IMUX_G0_DATA[3]PPC405.TSTC405DCRDBUSOUTI29
CELL_W[4].IMUX_G0_DATA[4]PPC405.TSTDSOCMWRDBUSI11
CELL_W[4].IMUX_G1_DATA[0]PPC405.APUC405DCDTRAPLE
CELL_W[4].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN23
CELL_W[4].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI20
CELL_W[4].IMUX_G1_DATA[3]PPC405.TSTC405DCRDBUSOUTI30
CELL_W[4].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI12
CELL_W[4].IMUX_G2_DATA[0]PPC405.APUC405EXERESULT29
CELL_W[4].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI22
CELL_W[4].IMUX_G2_DATA[2]PPC405.TSTC405DCRABUSI8
CELL_W[4].IMUX_G2_DATA[3]PPC405.TSTDSOCMABUSI16
CELL_W[4].IMUX_G3_DATA[0]PPC405.APUC405EXERESULT30
CELL_W[4].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI23
CELL_W[4].IMUX_G3_DATA[2]PPC405.TSTC405DCRABUSI9
CELL_W[4].IMUX_G3_DATA[3]PPC405.TSTDSOCMABUSI17
CELL_W[4].OUT_FAN_TMIN[0]PPC405.C405APUDCDINSTRUCTION14
CELL_W[4].OUT_FAN_TMIN[1]PPC405.C405APUDCDINSTRUCTION15
CELL_W[4].OUT_FAN_TMIN[2]PPC405.C405APUDCDINSTRUCTION16
CELL_W[4].OUT_FAN_TMIN[3]PPC405.C405APUDCDINSTRUCTION17
CELL_W[4].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA3
CELL_W[4].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA4
CELL_W[4].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA3
CELL_W[4].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA4
CELL_W[4].OUT_SEC_TMIN[8]PPC405.TSTDCRBUSO17
CELL_W[4].OUT_SEC_TMIN[9]PPC405.TSTDCRBUSO16
CELL_W[4].OUT_SEC_TMIN[10]PPC405.TSTDCRBUSO15
CELL_W[4].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO29
CELL_W[4].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT25
CELL_W[4].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT9
CELL_W[4].OUT_SEC_TMIN[14]PPC405.C405APUWBBYTEEN0
CELL_W[4].OUT_SEC_TMIN[15]PPC405.C405APUMSRFE1
CELL_W[4].OUT_TEST[0]PPC405.TSTDCRBUSO18
CELL_W[4].OUT_TEST[2]PPC405.TSTRDDBUSO30
CELL_W[4].OUT_TEST[4]PPC405.TSTRDDBUSO31
CELL_W[5].IMUX_TI[0]PPC405.TIEUTLBTAP1
CELL_W[5].IMUX_TI[1]PPC405.TIEUTLBTAP2
CELL_W[5].IMUX_G0_DATA[0]PPC405.APUC405DCDUPDATE
CELL_W[5].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN24
CELL_W[5].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI21
CELL_W[5].IMUX_G0_DATA[3]PPC405.TSTC405DCRDBUSOUTI31
CELL_W[5].IMUX_G0_DATA[4]PPC405.TSTDSOCMWRDBUSI13
CELL_W[5].IMUX_G1_DATA[0]PPC405.APUC405DCDVALIDOP
CELL_W[5].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN25
CELL_W[5].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI22
CELL_W[5].IMUX_G1_DATA[3]PPC405.TSTC405DCRREADI
CELL_W[5].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI14
CELL_W[5].IMUX_G2_DATA[0]PPC405.APUC405EXERESULT31
CELL_W[5].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI24
CELL_W[5].IMUX_G2_DATA[2]PPC405.TSTC405DCRDBUSOUTI0
CELL_W[5].IMUX_G2_DATA[3]PPC405.TSTDSOCMABUSI18
CELL_W[5].IMUX_G3_DATA[0]PPC405.APUC405EXEXERCA
CELL_W[5].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI25
CELL_W[5].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI1
CELL_W[5].IMUX_G3_DATA[3]PPC405.TSTDSOCMABUSI19
CELL_W[5].OUT_FAN_TMIN[0]PPC405.C405APUDCDINSTRUCTION18
CELL_W[5].OUT_FAN_TMIN[1]PPC405.C405APUDCDINSTRUCTION19
CELL_W[5].OUT_FAN_TMIN[2]PPC405.C405APUDCDINSTRUCTION20
CELL_W[5].OUT_FAN_TMIN[3]PPC405.C405APUDCDINSTRUCTION21
CELL_W[5].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA5
CELL_W[5].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA6
CELL_W[5].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA5
CELL_W[5].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA6
CELL_W[5].OUT_SEC_TMIN[8]PPC405.TSTDCRBUSO21
CELL_W[5].OUT_SEC_TMIN[9]PPC405.TSTDCRBUSO20
CELL_W[5].OUT_SEC_TMIN[10]PPC405.TSTDCRBUSO19
CELL_W[5].OUT_SEC_TMIN[11]PPC405.TSTDSOCMBYTEENO0
CELL_W[5].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT26
CELL_W[5].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT10
CELL_W[5].OUT_SEC_TMIN[14]PPC405.C405APUWBBYTEEN2
CELL_W[5].OUT_SEC_TMIN[15]PPC405.C405APUWBBYTEEN1
CELL_W[5].OUT_TEST[0]PPC405.TSTDCRBUSO22
CELL_W[5].OUT_TEST[2]PPC405.TSTDSOCMHOLDO
CELL_W[5].OUT_TEST[4]PPC405.TSTISOPFWDO
CELL_W[6].IMUX_TI[0]PPC405.TIERAMTAP1
CELL_W[6].IMUX_TI[1]PPC405.TIERAMTAP2
CELL_W[6].IMUX_G0_DATA[0]PPC405.APUC405DCDXERCAEN
CELL_W[6].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN26
CELL_W[6].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI23
CELL_W[6].IMUX_G0_DATA[3]PPC405.TSTC405DCRWRITEI
CELL_W[6].IMUX_G0_DATA[4]PPC405.TSTDSOCMWRDBUSI15
CELL_W[6].IMUX_G1_DATA[0]PPC405.APUC405DCDXEROVEN
CELL_W[6].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN27
CELL_W[6].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI24
CELL_W[6].IMUX_G1_DATA[3]PPC405.TSTDSOCMDBUSI0
CELL_W[6].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI16
CELL_W[6].IMUX_G2_DATA[0]PPC405.APUC405EXEXEROV
CELL_W[6].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI26
CELL_W[6].IMUX_G2_DATA[2]PPC405.TSTC405DCRDBUSOUTI2
CELL_W[6].IMUX_G2_DATA[3]PPC405.TSTDSOCMABUSI20
CELL_W[6].IMUX_G3_DATA[0]PPC405.APUC405FPUEXCEPTION
CELL_W[6].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI27
CELL_W[6].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI3
CELL_W[6].IMUX_G3_DATA[3]PPC405.TSTDSOCMABUSI21
CELL_W[6].OUT_FAN_TMIN[0]PPC405.C405APUDCDINSTRUCTION22
CELL_W[6].OUT_FAN_TMIN[1]PPC405.C405APUDCDINSTRUCTION23
CELL_W[6].OUT_FAN_TMIN[2]PPC405.C405APUDCDINSTRUCTION24
CELL_W[6].OUT_FAN_TMIN[3]PPC405.C405APUDCDINSTRUCTION25
CELL_W[6].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA7
CELL_W[6].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA8
CELL_W[6].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA7
CELL_W[6].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA8
CELL_W[6].OUT_SEC_TMIN[8]PPC405.TSTDCRBUSO25
CELL_W[6].OUT_SEC_TMIN[9]PPC405.TSTDCRBUSO24
CELL_W[6].OUT_SEC_TMIN[10]PPC405.TSTDCRBUSO23
CELL_W[6].OUT_SEC_TMIN[11]PPC405.TSTDSOCMBYTEENO1
CELL_W[6].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT27
CELL_W[6].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT11
CELL_W[6].OUT_SEC_TMIN[14]PPC405.C405APUWBENDIAN
CELL_W[6].OUT_SEC_TMIN[15]PPC405.C405APUWBBYTEEN3
CELL_W[6].OUT_TEST[0]PPC405.TSTDCRBUSO26
CELL_W[6].OUT_TEST[2]PPC405.TSTOCMCOMPLETEO
CELL_W[7].IMUX_TI[0]PPC405.TIETAGTAP1
CELL_W[7].IMUX_TI[1]PPC405.TIETAGTAP2
CELL_W[7].IMUX_G0_DATA[0]PPC405.APUC405EXCEPTION
CELL_W[7].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN28
CELL_W[7].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI25
CELL_W[7].IMUX_G0_DATA[3]PPC405.TSTDSOCMDBUSI1
CELL_W[7].IMUX_G0_DATA[4]PPC405.TSTDSOCMWRDBUSI17
CELL_W[7].IMUX_G1_DATA[0]PPC405.APUC405EXEBLOCKINGMCO
CELL_W[7].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN29
CELL_W[7].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI26
CELL_W[7].IMUX_G1_DATA[3]PPC405.TSTDSOCMDBUSI2
CELL_W[7].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI18
CELL_W[7].IMUX_G2_DATA[0]PPC405.APUC405LWBLDDEPEND
CELL_W[7].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI28
CELL_W[7].IMUX_G2_DATA[2]PPC405.TSTC405DCRDBUSOUTI4
CELL_W[7].IMUX_G2_DATA[3]PPC405.TSTDSOCMABUSI22
CELL_W[7].IMUX_G3_DATA[0]PPC405.APUC405SLEEPREQ
CELL_W[7].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI29
CELL_W[7].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI5
CELL_W[7].IMUX_G3_DATA[3]PPC405.TSTDSOCMABUSI23
CELL_W[7].OUT_FAN_TMIN[0]PPC405.C405APUDCDINSTRUCTION26
CELL_W[7].OUT_FAN_TMIN[1]PPC405.C405APUDCDINSTRUCTION27
CELL_W[7].OUT_FAN_TMIN[2]PPC405.C405APUDCDINSTRUCTION28
CELL_W[7].OUT_FAN_TMIN[3]PPC405.C405APUDCDINSTRUCTION29
CELL_W[7].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA9
CELL_W[7].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA10
CELL_W[7].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA9
CELL_W[7].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA10
CELL_W[7].OUT_SEC_TMIN[8]PPC405.TSTDCRBUSO29
CELL_W[7].OUT_SEC_TMIN[9]PPC405.TSTDCRBUSO28
CELL_W[7].OUT_SEC_TMIN[10]PPC405.TSTDCRBUSO27
CELL_W[7].OUT_SEC_TMIN[11]PPC405.TSTDSOCMBYTEENO2
CELL_W[7].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT28
CELL_W[7].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT12
CELL_W[7].OUT_SEC_TMIN[14]PPC405.C405APUWBHOLD
CELL_W[7].OUT_SEC_TMIN[15]PPC405.C405APUWBFLUSH
CELL_W[7].OUT_TEST[0]PPC405.TSTDCRBUSO30
CELL_W[8].IMUX_TI[0]PPC405.TESTSELI
CELL_W[8].IMUX_G0_DATA[0]PPC405.APUC405EXEBUSY
CELL_W[8].IMUX_G0_DATA[1]PPC405.DCRC405ACK
CELL_W[8].IMUX_G0_DATA[2]PPC405.TSTDCRBUSI30
CELL_W[8].IMUX_G0_DATA[3]PPC405.TSTC405DCRDBUSOUTI6
CELL_W[8].IMUX_G0_DATA[4]PPC405.TSTDSOCMABUSI25
CELL_W[8].IMUX_G1_DATA[0]PPC405.APUC405EXECR0
CELL_W[8].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN30
CELL_W[8].IMUX_G1_DATA[2]PPC405.TSTDCRBUSI31
CELL_W[8].IMUX_G1_DATA[3]PPC405.TSTDSOCMDBUSI3
CELL_W[8].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI19
CELL_W[8].IMUX_G2_DATA[0]PPC405.APUC405EXECR1
CELL_W[8].IMUX_G2_DATA[1]PPC405.DCRC405DBUSIN31
CELL_W[8].IMUX_G2_DATA[2]PPC405.TSTRDDBUSI27
CELL_W[8].IMUX_G2_DATA[3]PPC405.TSTDSOCMDBUSI4
CELL_W[8].IMUX_G2_DATA[4]PPC405.TSTDSOCMWRDBUSI20
CELL_W[8].IMUX_G3_DATA[0]PPC405.APUC405WBLDDEPEND
CELL_W[8].IMUX_G3_DATA[1]PPC405.TSTDCRACKI
CELL_W[8].IMUX_G3_DATA[2]PPC405.TSTRDDBUSI28
CELL_W[8].IMUX_G3_DATA[3]PPC405.TSTDSOCMABUSI24
CELL_W[8].OUT_FAN_TMIN[0]PPC405.C405APUDCDINSTRUCTION30
CELL_W[8].OUT_FAN_TMIN[1]PPC405.C405APUDCDINSTRUCTION31
CELL_W[8].OUT_FAN_TMIN[2]PPC405.C405APUEXEFLUSH
CELL_W[8].OUT_FAN_TMIN[3]PPC405.C405APUEXEHOLD
CELL_W[8].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA11
CELL_W[8].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA12
CELL_W[8].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA11
CELL_W[8].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA12
CELL_W[8].OUT_SEC_TMIN[8]PPC405.TSTDSOCMDBUSO1
CELL_W[8].OUT_SEC_TMIN[9]PPC405.TSTDSOCMDBUSO0
CELL_W[8].OUT_SEC_TMIN[10]PPC405.TSTDCRBUSO31
CELL_W[8].OUT_SEC_TMIN[11]PPC405.TSTDSOCMBYTEENO3
CELL_W[8].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT29
CELL_W[8].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT13
CELL_W[8].OUT_SEC_TMIN[14]PPC405.C405DCRABUS0
CELL_W[8].OUT_SEC_TMIN[15]PPC405.C405APUXERCA
CELL_W[8].OUT_TEST[0]PPC405.TSTDSOCMDBUSO2
CELL_W[9].IMUX_G0_DATA[0]PPC405.APUC405EXECR2
CELL_W[9].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN0
CELL_W[9].IMUX_G0_DATA[2]PPC405.TSTDSOCMCOMPLETEI
CELL_W[9].IMUX_G0_DATA[3]PPC405.TSTC405DCRDBUSOUTI7
CELL_W[9].IMUX_G0_DATA[4]PPC405.TSTDSOCMABUSI26
CELL_W[9].IMUX_G1_DATA[0]PPC405.APUC405EXECR3
CELL_W[9].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN1
CELL_W[9].IMUX_G1_DATA[2]PPC405.TSTISOPFWDI
CELL_W[9].IMUX_G1_DATA[3]PPC405.TSTC405DCRDBUSOUTI8
CELL_W[9].IMUX_G1_DATA[4]PPC405.TSTDSOCMABUSI27
CELL_W[9].IMUX_G2_DATA[0]PPC405.APUC405EXECRFIELD0
CELL_W[9].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI0
CELL_W[9].IMUX_G2_DATA[2]PPC405.TSTRDDBUSI29
CELL_W[9].IMUX_G2_DATA[3]PPC405.TSTDSOCMDBUSI5
CELL_W[9].IMUX_G2_DATA[4]PPC405.TSTDSOCMWRDBUSI21
CELL_W[9].IMUX_G3_DATA[0]PPC405.APUC405EXECRFIELD1
CELL_W[9].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI1
CELL_W[9].IMUX_G3_DATA[2]PPC405.TSTRDDBUSI30
CELL_W[9].IMUX_G3_DATA[3]PPC405.TSTDSOCMDBUSI6
CELL_W[9].IMUX_G3_DATA[4]PPC405.TSTDSOCMWRDBUSI22
CELL_W[9].OUT_FAN_TMIN[0]PPC405.C405APUEXELOADDBUS0
CELL_W[9].OUT_FAN_TMIN[1]PPC405.C405APUEXELOADDBUS1
CELL_W[9].OUT_FAN_TMIN[2]PPC405.C405APUEXELOADDBUS2
CELL_W[9].OUT_FAN_TMIN[3]PPC405.C405APUEXELOADDBUS3
CELL_W[9].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA13
CELL_W[9].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA14
CELL_W[9].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA13
CELL_W[9].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA14
CELL_W[9].OUT_SEC_TMIN[8]PPC405.TSTDSOCMDBUSO5
CELL_W[9].OUT_SEC_TMIN[9]PPC405.TSTDSOCMDBUSO4
CELL_W[9].OUT_SEC_TMIN[10]PPC405.TSTDSOCMDBUSO3
CELL_W[9].OUT_SEC_TMIN[11]PPC405.TSTDSOCMLOADREQO
CELL_W[9].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT30
CELL_W[9].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT14
CELL_W[9].OUT_SEC_TMIN[14]PPC405.C405DCRABUS2
CELL_W[9].OUT_SEC_TMIN[15]PPC405.C405DCRABUS1
CELL_W[9].OUT_TEST[0]PPC405.TSTDSOCMDBUSO6
CELL_W[10].IMUX_G0_DATA[0]PPC405.APUC405EXECRFIELD2
CELL_W[10].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN2
CELL_W[10].IMUX_G0_DATA[2]PPC405.TSTDSOCMHOLDI
CELL_W[10].IMUX_G0_DATA[3]PPC405.TSTC405DCRDBUSOUTI10
CELL_W[10].IMUX_G0_DATA[4]PPC405.TSTDSOCMABUSI29
CELL_W[10].IMUX_G1_DATA[0]PPC405.APUC405EXELDDEPEND
CELL_W[10].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN3
CELL_W[10].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI0
CELL_W[10].IMUX_G1_DATA[3]PPC405.TSTDSOCMDBUSI7
CELL_W[10].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI23
CELL_W[10].IMUX_G2_DATA[0]PPC405.APUC405EXENONBLOCKINGMCO
CELL_W[10].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI2
CELL_W[10].IMUX_G2_DATA[2]PPC405.TSTRDDBUSI31
CELL_W[10].IMUX_G2_DATA[3]PPC405.TSTDSOCMDCRACKI
CELL_W[10].IMUX_G2_DATA[4]PPC405.TSTDSOCMWRDBUSI24
CELL_W[10].IMUX_G3_DATA[0]PPC405.APUC405EXERESULT0
CELL_W[10].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI3
CELL_W[10].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI9
CELL_W[10].IMUX_G3_DATA[3]PPC405.TSTDSOCMABUSI28
CELL_W[10].OUT_FAN_TMIN[0]PPC405.C405APUEXELOADDBUS4
CELL_W[10].OUT_FAN_TMIN[1]PPC405.C405APUEXELOADDBUS5
CELL_W[10].OUT_FAN_TMIN[2]PPC405.C405APUEXELOADDBUS6
CELL_W[10].OUT_FAN_TMIN[3]PPC405.C405APUEXELOADDBUS7
CELL_W[10].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA15
CELL_W[10].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA16
CELL_W[10].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA15
CELL_W[10].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA16
CELL_W[10].OUT_SEC_TMIN[8]PPC405.TSTRDDBUSO0
CELL_W[10].OUT_SEC_TMIN[9]PPC405.TSTDSOCMDCRACKO
CELL_W[10].OUT_SEC_TMIN[10]PPC405.TSTDSOCMDBUSO7
CELL_W[10].OUT_SEC_TMIN[11]PPC405.TSTDSOCMSTOREREQO
CELL_W[10].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT31
CELL_W[10].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT15
CELL_W[10].OUT_SEC_TMIN[14]PPC405.C405DCRABUS4
CELL_W[10].OUT_SEC_TMIN[15]PPC405.C405DCRABUS3
CELL_W[10].OUT_TEST[0]PPC405.TSTRDDBUSO1
CELL_W[11].IMUX_G0_DATA[0]PPC405.APUC405EXERESULT1
CELL_W[11].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN4
CELL_W[11].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI1
CELL_W[11].IMUX_G0_DATA[3]PPC405.TSTDSOCMABORTOPI
CELL_W[11].IMUX_G0_DATA[4]PPC405.TSTDSOCMWRDBUSI25
CELL_W[11].IMUX_G1_DATA[0]PPC405.APUC405EXERESULT2
CELL_W[11].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN5
CELL_W[11].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI2
CELL_W[11].IMUX_G1_DATA[3]PPC405.TSTDSOCMABORTREQI
CELL_W[11].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI26
CELL_W[11].IMUX_G2_DATA[0]PPC405.APUC405EXERESULT3
CELL_W[11].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI4
CELL_W[11].IMUX_G2_DATA[2]PPC405.TSTC405DCRDBUSOUTI11
CELL_W[11].IMUX_G2_DATA[3]PPC405.TSTDSOCMBYTEENI0
CELL_W[11].IMUX_G3_DATA[0]PPC405.APUC405EXERESULT4
CELL_W[11].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI5
CELL_W[11].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI12
CELL_W[11].IMUX_G3_DATA[3]PPC405.TSTDSOCMBYTEENI1
CELL_W[11].OUT_FAN_TMIN[0]PPC405.C405APUEXELOADDBUS8
CELL_W[11].OUT_FAN_TMIN[1]PPC405.C405APUEXELOADDBUS9
CELL_W[11].OUT_FAN_TMIN[2]PPC405.C405APUEXELOADDBUS10
CELL_W[11].OUT_FAN_TMIN[3]PPC405.C405APUEXELOADDBUS11
CELL_W[11].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA17
CELL_W[11].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA18
CELL_W[11].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA17
CELL_W[11].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA18
CELL_W[11].OUT_SEC_TMIN[8]PPC405.TSTRDDBUSO4
CELL_W[11].OUT_SEC_TMIN[9]PPC405.TSTRDDBUSO3
CELL_W[11].OUT_SEC_TMIN[10]PPC405.TSTRDDBUSO2
CELL_W[11].OUT_SEC_TMIN[11]PPC405.TSTDSOCMWAITO
CELL_W[11].OUT_SEC_TMIN[12]PPC405.C405DCRREAD
CELL_W[11].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT16
CELL_W[11].OUT_SEC_TMIN[14]PPC405.C405DCRABUS6
CELL_W[11].OUT_SEC_TMIN[15]PPC405.C405DCRABUS5
CELL_W[11].OUT_TEST[0]PPC405.TSTRDDBUSO5
CELL_W[12].IMUX_G0_DATA[0]PPC405.APUC405EXERESULT5
CELL_W[12].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN6
CELL_W[12].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI3
CELL_W[12].IMUX_G0_DATA[3]PPC405.TSTDSOCMABUSI0
CELL_W[12].IMUX_G0_DATA[4]PPC405.TSTDSOCMWRDBUSI27
CELL_W[12].IMUX_G1_DATA[0]PPC405.APUC405EXERESULT6
CELL_W[12].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN7
CELL_W[12].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI4
CELL_W[12].IMUX_G1_DATA[3]PPC405.TSTDSOCMABUSI1
CELL_W[12].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI28
CELL_W[12].IMUX_G2_DATA[0]PPC405.APUC405EXERESULT7
CELL_W[12].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI6
CELL_W[12].IMUX_G2_DATA[2]PPC405.TSTC405DCRDBUSOUTI13
CELL_W[12].IMUX_G2_DATA[3]PPC405.TSTDSOCMBYTEENI2
CELL_W[12].IMUX_G3_DATA[0]PPC405.APUC405EXERESULT8
CELL_W[12].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI7
CELL_W[12].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI14
CELL_W[12].IMUX_G3_DATA[3]PPC405.TSTDSOCMBYTEENI3
CELL_W[12].OUT_FAN_TMIN[0]PPC405.C405APUEXELOADDBUS12
CELL_W[12].OUT_FAN_TMIN[1]PPC405.C405APUEXELOADDBUS13
CELL_W[12].OUT_FAN_TMIN[2]PPC405.C405APUEXELOADDBUS14
CELL_W[12].OUT_FAN_TMIN[3]PPC405.C405APUEXELOADDBUS15
CELL_W[12].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA19
CELL_W[12].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA20
CELL_W[12].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA19
CELL_W[12].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA20
CELL_W[12].OUT_SEC_TMIN[8]PPC405.TSTRDDBUSO8
CELL_W[12].OUT_SEC_TMIN[9]PPC405.TSTRDDBUSO7
CELL_W[12].OUT_SEC_TMIN[10]PPC405.TSTRDDBUSO6
CELL_W[12].OUT_SEC_TMIN[11]PPC405.TSTDSOCMXLATEVALIDO
CELL_W[12].OUT_SEC_TMIN[12]PPC405.C405DCRWRITE
CELL_W[12].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT17
CELL_W[12].OUT_SEC_TMIN[14]PPC405.C405DCRABUS8
CELL_W[12].OUT_SEC_TMIN[15]PPC405.C405DCRABUS7
CELL_W[12].OUT_TEST[0]PPC405.TSTRDDBUSO9
CELL_W[13].IMUX_G0_DATA[0]PPC405.APUC405EXERESULT9
CELL_W[13].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN8
CELL_W[13].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI5
CELL_W[13].IMUX_G0_DATA[3]PPC405.TSTDSOCMABUSI2
CELL_W[13].IMUX_G0_DATA[4]PPC405.TSTDSOCMWRDBUSI29
CELL_W[13].IMUX_G1_DATA[0]PPC405.APUC405EXERESULT10
CELL_W[13].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN9
CELL_W[13].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI6
CELL_W[13].IMUX_G1_DATA[3]PPC405.TSTDSOCMABUSI3
CELL_W[13].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI30
CELL_W[13].IMUX_G2_DATA[0]PPC405.APUC405EXERESULT11
CELL_W[13].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI8
CELL_W[13].IMUX_G2_DATA[2]PPC405.TSTC405DCRDBUSOUTI15
CELL_W[13].IMUX_G2_DATA[3]PPC405.TSTDSOCMLOADREQI
CELL_W[13].IMUX_G3_DATA[0]PPC405.APUC405EXERESULT12
CELL_W[13].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI9
CELL_W[13].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI16
CELL_W[13].IMUX_G3_DATA[3]PPC405.TSTDSOCMSTOREREQI
CELL_W[13].OUT_FAN_TMIN[0]PPC405.C405APUEXELOADDBUS16
CELL_W[13].OUT_FAN_TMIN[1]PPC405.C405APUEXELOADDBUS17
CELL_W[13].OUT_FAN_TMIN[2]PPC405.C405APUEXELOADDBUS18
CELL_W[13].OUT_FAN_TMIN[3]PPC405.C405APUEXELOADDBUS19
CELL_W[13].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA21
CELL_W[13].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA22
CELL_W[13].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA21
CELL_W[13].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA22
CELL_W[13].OUT_SEC_TMIN[8]PPC405.TSTRDDBUSO13
CELL_W[13].OUT_SEC_TMIN[9]PPC405.TSTRDDBUSO12
CELL_W[13].OUT_SEC_TMIN[10]PPC405.TSTRDDBUSO11
CELL_W[13].OUT_SEC_TMIN[11]PPC405.TSTRDDBUSO10
CELL_W[13].OUT_SEC_TMIN[12]PPC405.TSTDSOCMABORTOPO
CELL_W[13].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT18
CELL_W[13].OUT_SEC_TMIN[14]PPC405.C405DCRDBUSOUT0
CELL_W[13].OUT_SEC_TMIN[15]PPC405.C405DCRABUS9
CELL_W[14].IMUX_G0_DATA[0]PPC405.APUC405EXERESULT13
CELL_W[14].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN10
CELL_W[14].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI7
CELL_W[14].IMUX_G0_DATA[3]PPC405.TSTDSOCMABUSI4
CELL_W[14].IMUX_G0_DATA[4]PPC405.TSTDSOCMWRDBUSI31
CELL_W[14].IMUX_G1_DATA[0]PPC405.APUC405EXERESULT14
CELL_W[14].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN11
CELL_W[14].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI8
CELL_W[14].IMUX_G1_DATA[3]PPC405.TSTDSOCMABUSI5
CELL_W[14].IMUX_G1_DATA[4]PPC405.TSTDSOCMXLATEVALIDI
CELL_W[14].IMUX_G2_DATA[0]PPC405.APUC405EXERESULT15
CELL_W[14].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI10
CELL_W[14].IMUX_G2_DATA[2]PPC405.TSTC405DCRDBUSOUTI17
CELL_W[14].IMUX_G2_DATA[3]PPC405.TSTDSOCMWAITI
CELL_W[14].IMUX_G3_DATA[0]PPC405.APUC405EXERESULT16
CELL_W[14].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI11
CELL_W[14].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI18
CELL_W[14].IMUX_G3_DATA[3]PPC405.TSTDSOCMWRDBUSI0
CELL_W[14].OUT_FAN_TMIN[0]PPC405.C405APUEXELOADDBUS20
CELL_W[14].OUT_FAN_TMIN[1]PPC405.C405APUEXELOADDBUS21
CELL_W[14].OUT_FAN_TMIN[2]PPC405.C405APUEXELOADDBUS22
CELL_W[14].OUT_FAN_TMIN[3]PPC405.C405APUEXELOADDBUS23
CELL_W[14].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA23
CELL_W[14].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA24
CELL_W[14].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA23
CELL_W[14].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA24
CELL_W[14].OUT_SEC_TMIN[8]PPC405.TSTRDDBUSO17
CELL_W[14].OUT_SEC_TMIN[9]PPC405.TSTRDDBUSO16
CELL_W[14].OUT_SEC_TMIN[10]PPC405.TSTRDDBUSO15
CELL_W[14].OUT_SEC_TMIN[11]PPC405.TSTRDDBUSO14
CELL_W[14].OUT_SEC_TMIN[12]PPC405.TSTDSOCMABORTREQO
CELL_W[14].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT19
CELL_W[14].OUT_SEC_TMIN[14]PPC405.C405DCRDBUSOUT2
CELL_W[14].OUT_SEC_TMIN[15]PPC405.C405DCRDBUSOUT1
CELL_W[15].IMUX_G0_DATA[0]PPC405.APUC405EXERESULT17
CELL_W[15].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN12
CELL_W[15].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI9
CELL_W[15].IMUX_G0_DATA[3]PPC405.TSTDSOCMABUSI6
CELL_W[15].IMUX_G1_DATA[0]PPC405.APUC405EXERESULT18
CELL_W[15].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN13
CELL_W[15].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI10
CELL_W[15].IMUX_G1_DATA[3]PPC405.TSTDSOCMABUSI7
CELL_W[15].IMUX_G2_DATA[0]PPC405.APUC405EXERESULT19
CELL_W[15].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI12
CELL_W[15].IMUX_G2_DATA[2]PPC405.TSTC405DCRDBUSOUTI19
CELL_W[15].IMUX_G2_DATA[3]PPC405.TSTDSOCMWRDBUSI1
CELL_W[15].IMUX_G3_DATA[0]PPC405.APUC405EXERESULT20
CELL_W[15].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI13
CELL_W[15].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI20
CELL_W[15].IMUX_G3_DATA[3]PPC405.TSTDSOCMWRDBUSI2
CELL_W[15].OUT_FAN_TMIN[0]PPC405.C405APUEXELOADDBUS24
CELL_W[15].OUT_FAN_TMIN[1]PPC405.C405APUEXELOADDBUS25
CELL_W[15].OUT_FAN_TMIN[2]PPC405.C405APUEXELOADDBUS26
CELL_W[15].OUT_FAN_TMIN[3]PPC405.C405APUEXELOADDBUS27
CELL_W[15].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA25
CELL_W[15].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA26
CELL_W[15].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA25
CELL_W[15].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA26
CELL_W[15].OUT_SEC_TMIN[8]PPC405.TSTRDDBUSO21
CELL_W[15].OUT_SEC_TMIN[9]PPC405.TSTRDDBUSO20
CELL_W[15].OUT_SEC_TMIN[10]PPC405.TSTRDDBUSO19
CELL_W[15].OUT_SEC_TMIN[11]PPC405.TSTRDDBUSO18
CELL_W[15].OUT_SEC_TMIN[12]PPC405.TSTDSOCMABUSO24
CELL_W[15].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT20
CELL_W[15].OUT_SEC_TMIN[14]PPC405.C405DCRDBUSOUT4
CELL_W[15].OUT_SEC_TMIN[15]PPC405.C405DCRDBUSOUT3
CELL_E[0].IMUX_CLK[1]PPC405.PLBCLK
CELL_E[0].IMUX_TI[0]PPC405.TIEC405DETERMINISTICMULT
CELL_E[0].IMUX_TI[1]PPC405.TIEC405PVR30
CELL_E[0].IMUX_TS[0]PPC405.TIEC405PVR31
CELL_E[0].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS60
CELL_E[0].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS60
CELL_E[0].IMUX_G0_DATA[2]PPC405.TSTRESETCHIPI
CELL_E[0].IMUX_G0_DATA[3]PPC405.TSTISOCMREQPENDI
CELL_E[0].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS61
CELL_E[0].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS61
CELL_E[0].IMUX_G1_DATA[2]PPC405.TSTCPUCLKI
CELL_E[0].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS62
CELL_E[0].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS62
CELL_E[0].IMUX_G2_DATA[2]PPC405.TSTISOCMRDATAI11
CELL_E[0].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS63
CELL_E[0].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS63
CELL_E[0].IMUX_G3_DATA[2]PPC405.TSTISOCMXLATEVALIDI
CELL_E[0].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS60
CELL_E[0].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS61
CELL_E[0].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS62
CELL_E[0].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS63
CELL_E[0].OUT_FAN_TMIN[4]PPC405.C405RSTCHIPRESETREQ
CELL_E[0].OUT_FAN_TMIN[5]PPC405.C405RSTCORERESETREQ
CELL_E[0].OUT_FAN_TMIN[6]PPC405.C405CPMTIMERIRQ
CELL_E[0].OUT_FAN_TMIN[7]PPC405.C405CPMTIMERRESETREQ
CELL_E[0].OUT_SEC_TMIN[8]PPC405.TSTRESETSYSO
CELL_E[0].OUT_SEC_TMIN[9]PPC405.TSTRESETCOREO
CELL_E[0].OUT_SEC_TMIN[10]PPC405.TSTRESETCHIPO
CELL_E[0].OUT_SEC_TMIN[11]PPC405.C405DBGWBIAR26
CELL_E[0].OUT_SEC_TMIN[12]PPC405.C405DBGWBIAR21
CELL_E[0].OUT_SEC_TMIN[13]PPC405.C405DBGWBIAR7
CELL_E[0].OUT_SEC_TMIN[14]PPC405.C405DBGWBFULL
CELL_E[0].OUT_SEC_TMIN[15]PPC405.C405DBGWBCOMPLETE
CELL_E[0].OUT_TEST[0]PPC405.TSTJTAGENO
CELL_E[0].OUT_TEST[2]PPC405.TSTISOCMRDATAO53
CELL_E[0].OUT_TEST[4]PPC405.TSTISOCMRDATAO54
CELL_E[1].IMUX_CE[0]PPC405.CPMC405CPUCLKEN
CELL_E[1].IMUX_TI[0]PPC405.TIEC405DISOPERANDFWD
CELL_E[1].IMUX_TI[1]PPC405.TIEC405MMUEN
CELL_E[1].IMUX_TS[0]PPC405.TIEC405PVR29
CELL_E[1].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS56
CELL_E[1].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS56
CELL_E[1].IMUX_G0_DATA[2]PPC405.DBGC405DEBUGHALT
CELL_E[1].IMUX_G0_DATA[3]PPC405.TSTISOCMABUSI0
CELL_E[1].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS57
CELL_E[1].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS57
CELL_E[1].IMUX_G1_DATA[2]PPC405.TSTCLKINACTI
CELL_E[1].IMUX_G1_DATA[3]PPC405.TSTISOCMABUSI1
CELL_E[1].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS58
CELL_E[1].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS58
CELL_E[1].IMUX_G2_DATA[2]PPC405.TSTISOCMRDATAI12
CELL_E[1].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS59
CELL_E[1].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS59
CELL_E[1].IMUX_G3_DATA[2]PPC405.TSTISOCMICUREADYI
CELL_E[1].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS56
CELL_E[1].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS57
CELL_E[1].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS58
CELL_E[1].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS59
CELL_E[1].OUT_FAN_TMIN[4]PPC405.C405PLBDCUREQUEST
CELL_E[1].OUT_FAN_TMIN[5]PPC405.C405PLBDCUPRIORITY0
CELL_E[1].OUT_FAN_TMIN[6]PPC405.C405PLBDCUPRIORITY1
CELL_E[1].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABORT
CELL_E[1].OUT_SEC_TMIN[8]PPC405.TSTCPUCLKO
CELL_E[1].OUT_SEC_TMIN[9]PPC405.TSTCPUCLKENO
CELL_E[1].OUT_SEC_TMIN[10]PPC405.TSTTIMERENO
CELL_E[1].OUT_SEC_TMIN[11]PPC405.C405DBGWBIAR27
CELL_E[1].OUT_SEC_TMIN[12]PPC405.C405DBGWBIAR22
CELL_E[1].OUT_SEC_TMIN[13]PPC405.C405DBGWBIAR8
CELL_E[1].OUT_SEC_TMIN[14]PPC405.C405DBGWBIAR0
CELL_E[1].OUT_SEC_TMIN[15]PPC405.C405PLBDCURNW
CELL_E[1].OUT_TEST[0]PPC405.TSTCLKINACTO
CELL_E[1].OUT_TEST[2]PPC405.TSTISOCMRDATAO55
CELL_E[1].OUT_TEST[4]PPC405.TSTISOCMRDATAO56
CELL_E[2].IMUX_CE[0]PPC405.CPMC405TIMERCLKEN
CELL_E[2].IMUX_TI[0]PPC405.TIEC405PVR26
CELL_E[2].IMUX_TI[1]PPC405.TIEC405PVR27
CELL_E[2].IMUX_TS[0]PPC405.TIEC405PVR28
CELL_E[2].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS52
CELL_E[2].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS52
CELL_E[2].IMUX_G0_DATA[2]PPC405.DBGC405UNCONDDEBUGEVENT
CELL_E[2].IMUX_G0_DATA[3]PPC405.TSTISOCMABUSI3
CELL_E[2].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS53
CELL_E[2].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS53
CELL_E[2].IMUX_G1_DATA[2]PPC405.TSTISOCMHOLDI
CELL_E[2].IMUX_G1_DATA[3]PPC405.TSTISOCMABUSI4
CELL_E[2].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS54
CELL_E[2].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS54
CELL_E[2].IMUX_G2_DATA[2]PPC405.TSTISOCMRDATAI13
CELL_E[2].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS55
CELL_E[2].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS55
CELL_E[2].IMUX_G3_DATA[2]PPC405.TSTISOCMABUSI2
CELL_E[2].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS52
CELL_E[2].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS53
CELL_E[2].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS54
CELL_E[2].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS55
CELL_E[2].OUT_FAN_TMIN[4]PPC405.C405PLBDCUGUARDED
CELL_E[2].OUT_FAN_TMIN[5]PPC405.C405PLBDCUWRITETHRU
CELL_E[2].OUT_FAN_TMIN[6]PPC405.C405DBGWBIAR11
CELL_E[2].OUT_FAN_TMIN[7]PPC405.C405DBGWBIAR12
CELL_E[2].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDDVALIDO1
CELL_E[2].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDDVALIDO0
CELL_E[2].OUT_SEC_TMIN[10]PPC405.TSTISOCMHOLDO
CELL_E[2].OUT_SEC_TMIN[11]PPC405.C405DBGWBIAR28
CELL_E[2].OUT_SEC_TMIN[12]PPC405.C405PLBICUABORT
CELL_E[2].OUT_SEC_TMIN[13]PPC405.C405PLBICUPRIORITY1
CELL_E[2].OUT_SEC_TMIN[14]PPC405.C405PLBICUPRIORITY0
CELL_E[2].OUT_SEC_TMIN[15]PPC405.C405PLBICUREQUEST
CELL_E[2].OUT_TEST[0]PPC405.TSTISOCMRDATAO0
CELL_E[2].OUT_TEST[2]PPC405.TSTISOCMRDATAO57
CELL_E[2].OUT_TEST[4]PPC405.TSTISOCMRDATAO58
CELL_E[3].IMUX_CLK[0]PPC405.CPMC405TIMERTICK
CELL_E[3].IMUX_CE[0]PPC405.CPMC405JTAGCLKEN
CELL_E[3].IMUX_TI[0]PPC405.TIEC405PVR23
CELL_E[3].IMUX_TI[1]PPC405.TIEC405PVR24
CELL_E[3].IMUX_TS[0]PPC405.TIEC405PVR25
CELL_E[3].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS48
CELL_E[3].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS48
CELL_E[3].IMUX_G0_DATA[2]PPC405.TSTISOCMRDDVALIDI0
CELL_E[3].IMUX_G0_DATA[3]PPC405.TSTISOCMABUSI7
CELL_E[3].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS49
CELL_E[3].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS49
CELL_E[3].IMUX_G1_DATA[2]PPC405.TSTISOCMRDATAI14
CELL_E[3].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS50
CELL_E[3].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS50
CELL_E[3].IMUX_G2_DATA[2]PPC405.TSTISOCMABUSI5
CELL_E[3].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS51
CELL_E[3].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS51
CELL_E[3].IMUX_G3_DATA[2]PPC405.TSTISOCMABUSI6
CELL_E[3].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS48
CELL_E[3].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS49
CELL_E[3].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS50
CELL_E[3].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS51
CELL_E[3].OUT_FAN_TMIN[4]PPC405.C405PLBDCUBE4
CELL_E[3].OUT_FAN_TMIN[5]PPC405.C405PLBDCUBE5
CELL_E[3].OUT_FAN_TMIN[6]PPC405.C405PLBDCUBE6
CELL_E[3].OUT_FAN_TMIN[7]PPC405.C405PLBDCUBE7
CELL_E[3].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO3
CELL_E[3].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO2
CELL_E[3].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO1
CELL_E[3].OUT_SEC_TMIN[11]PPC405.C405DBGWBIAR29
CELL_E[3].OUT_SEC_TMIN[12]PPC405.C405DBGWBIAR16
CELL_E[3].OUT_SEC_TMIN[13]PPC405.C405DBGWBIAR15
CELL_E[3].OUT_SEC_TMIN[14]PPC405.C405DBGWBIAR14
CELL_E[3].OUT_SEC_TMIN[15]PPC405.C405DBGWBIAR13
CELL_E[3].OUT_TEST[0]PPC405.TSTISOCMRDATAO4
CELL_E[3].OUT_TEST[2]PPC405.TSTISOCMRDATAO59
CELL_E[3].OUT_TEST[4]PPC405.TSTISOCMRDATAO60
CELL_E[4].IMUX_TI[0]PPC405.MCBCPUCLKEN
CELL_E[4].IMUX_TI[1]PPC405.TIEC405PVR20
CELL_E[4].IMUX_TS[0]PPC405.TIEC405PVR21
CELL_E[4].IMUX_TS[1]PPC405.TIEC405PVR22
CELL_E[4].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS44
CELL_E[4].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS44
CELL_E[4].IMUX_G0_DATA[2]PPC405.DBGC405EXTBUSHOLDACK
CELL_E[4].IMUX_G0_DATA[3]PPC405.TSTISOCMABUSI9
CELL_E[4].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS45
CELL_E[4].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS45
CELL_E[4].IMUX_G1_DATA[2]PPC405.TSTISOCMRDDVALIDI1
CELL_E[4].IMUX_G1_DATA[3]PPC405.TSTISOCMABUSI10
CELL_E[4].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS46
CELL_E[4].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS46
CELL_E[4].IMUX_G2_DATA[2]PPC405.TSTISOCMRDATAI15
CELL_E[4].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS47
CELL_E[4].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS47
CELL_E[4].IMUX_G3_DATA[2]PPC405.TSTISOCMABUSI8
CELL_E[4].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS44
CELL_E[4].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS45
CELL_E[4].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS46
CELL_E[4].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS47
CELL_E[4].OUT_FAN_TMIN[4]PPC405.C405PLBDCUABUS28
CELL_E[4].OUT_FAN_TMIN[5]PPC405.C405PLBDCUABUS29
CELL_E[4].OUT_FAN_TMIN[6]PPC405.C405PLBDCUABUS30
CELL_E[4].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABUS31
CELL_E[4].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO8
CELL_E[4].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO7
CELL_E[4].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO6
CELL_E[4].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO5
CELL_E[4].OUT_SEC_TMIN[12]PPC405.C405DBGWBIAR18
CELL_E[4].OUT_SEC_TMIN[13]PPC405.C405DBGWBIAR17
CELL_E[4].OUT_SEC_TMIN[14]PPC405.C405PLBICUABUS29
CELL_E[4].OUT_SEC_TMIN[15]PPC405.C405PLBICUABUS28
CELL_E[4].OUT_TEST[0]PPC405.TSTISOCMRDATAO61
CELL_E[4].OUT_TEST[2]PPC405.TSTISOCMRDATAO62
CELL_E[5].IMUX_TI[0]PPC405.MCBJTAGEN
CELL_E[5].IMUX_TI[1]PPC405.TIEC405PVR18
CELL_E[5].IMUX_TS[0]PPC405.TIEC405PVR19
CELL_E[5].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS40
CELL_E[5].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS40
CELL_E[5].IMUX_G0_DATA[2]PPC405.PLBC405DCUWRDACK
CELL_E[5].IMUX_G0_DATA[3]PPC405.TSTISOCMRDATAI16
CELL_E[5].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS41
CELL_E[5].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS41
CELL_E[5].IMUX_G1_DATA[2]PPC405.CPMC405CORECLKINACTIVE
CELL_E[5].IMUX_G1_DATA[3]PPC405.TSTISOCMABUSI11
CELL_E[5].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS42
CELL_E[5].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS42
CELL_E[5].IMUX_G2_DATA[2]PPC405.TSTRESETCOREI
CELL_E[5].IMUX_G2_DATA[3]PPC405.TSTISOCMABUSI12
CELL_E[5].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS43
CELL_E[5].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS43
CELL_E[5].IMUX_G3_DATA[2]PPC405.TSTISOCMRDATAI0
CELL_E[5].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS40
CELL_E[5].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS41
CELL_E[5].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS42
CELL_E[5].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS43
CELL_E[5].OUT_FAN_TMIN[4]PPC405.C405PLBDCUABUS24
CELL_E[5].OUT_FAN_TMIN[5]PPC405.C405PLBDCUABUS25
CELL_E[5].OUT_FAN_TMIN[6]PPC405.C405PLBDCUABUS26
CELL_E[5].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABUS27
CELL_E[5].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO12
CELL_E[5].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO11
CELL_E[5].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO10
CELL_E[5].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO9
CELL_E[5].OUT_SEC_TMIN[12]PPC405.C405PLBICUABUS27
CELL_E[5].OUT_SEC_TMIN[13]PPC405.C405PLBICUABUS26
CELL_E[5].OUT_SEC_TMIN[14]PPC405.C405PLBICUABUS25
CELL_E[5].OUT_SEC_TMIN[15]PPC405.C405PLBICUABUS24
CELL_E[5].OUT_TEST[0]PPC405.TSTISOCMRDATAO63
CELL_E[5].OUT_TEST[2]PPC405.TSTPLBSAMPLECYCLEO
CELL_E[6].IMUX_TI[0]PPC405.MCBTIMEREN
CELL_E[6].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS36
CELL_E[6].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS36
CELL_E[6].IMUX_G0_DATA[2]PPC405.PLBC405DCURDWDADDR1
CELL_E[6].IMUX_G0_DATA[3]PPC405.TSTISOCMRDATAI1
CELL_E[6].IMUX_G0_DATA[4]PPC405.TSTISOCMABUSI15
CELL_E[6].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS37
CELL_E[6].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS37
CELL_E[6].IMUX_G1_DATA[2]PPC405.PLBC405DCURDWDADDR2
CELL_E[6].IMUX_G1_DATA[3]PPC405.TSTPLBSAMPLECYCLEI
CELL_E[6].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS38
CELL_E[6].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS38
CELL_E[6].IMUX_G2_DATA[2]PPC405.PLBC405DCURDWDADDR3
CELL_E[6].IMUX_G2_DATA[3]PPC405.TSTISOCMABUSI13
CELL_E[6].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS39
CELL_E[6].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS39
CELL_E[6].IMUX_G3_DATA[2]PPC405.PLBC405DCURDDACK
CELL_E[6].IMUX_G3_DATA[3]PPC405.TSTISOCMABUSI14
CELL_E[6].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS36
CELL_E[6].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS37
CELL_E[6].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS38
CELL_E[6].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS39
CELL_E[6].OUT_FAN_TMIN[4]PPC405.C405PLBDCUABUS20
CELL_E[6].OUT_FAN_TMIN[5]PPC405.C405PLBDCUABUS21
CELL_E[6].OUT_FAN_TMIN[6]PPC405.C405PLBDCUABUS22
CELL_E[6].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABUS23
CELL_E[6].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO16
CELL_E[6].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO15
CELL_E[6].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO14
CELL_E[6].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO13
CELL_E[6].OUT_SEC_TMIN[12]PPC405.C405PLBICUABUS23
CELL_E[6].OUT_SEC_TMIN[13]PPC405.C405PLBICUABUS22
CELL_E[6].OUT_SEC_TMIN[14]PPC405.C405PLBICUABUS21
CELL_E[6].OUT_SEC_TMIN[15]PPC405.C405PLBICUABUS20
CELL_E[7].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS32
CELL_E[7].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS32
CELL_E[7].IMUX_G0_DATA[2]PPC405.PLBC405DCUADDRACK
CELL_E[7].IMUX_G0_DATA[3]PPC405.TSTISOCMRDATAI2
CELL_E[7].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS33
CELL_E[7].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS33
CELL_E[7].IMUX_G1_DATA[2]PPC405.PLBC405DCUSSIZE1
CELL_E[7].IMUX_G1_DATA[3]PPC405.TSTISOCMABUSI16
CELL_E[7].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS34
CELL_E[7].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS34
CELL_E[7].IMUX_G2_DATA[2]PPC405.PLBC405DCUBUSY
CELL_E[7].IMUX_G2_DATA[3]PPC405.TSTISOCMABUSI17
CELL_E[7].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS35
CELL_E[7].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS35
CELL_E[7].IMUX_G3_DATA[2]PPC405.PLBC405DCUERR
CELL_E[7].IMUX_G3_DATA[3]PPC405.TSTISOCMABUSI18
CELL_E[7].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS32
CELL_E[7].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS33
CELL_E[7].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS34
CELL_E[7].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS35
CELL_E[7].OUT_FAN_TMIN[4]PPC405.C405PLBDCUABUS16
CELL_E[7].OUT_FAN_TMIN[5]PPC405.C405PLBDCUABUS17
CELL_E[7].OUT_FAN_TMIN[6]PPC405.C405PLBDCUABUS18
CELL_E[7].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABUS19
CELL_E[7].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO20
CELL_E[7].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO19
CELL_E[7].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO18
CELL_E[7].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO17
CELL_E[7].OUT_SEC_TMIN[12]PPC405.C405PLBICUABUS19
CELL_E[7].OUT_SEC_TMIN[13]PPC405.C405PLBICUABUS18
CELL_E[7].OUT_SEC_TMIN[14]PPC405.C405PLBICUABUS17
CELL_E[7].OUT_SEC_TMIN[15]PPC405.C405PLBICUABUS16
CELL_E[8].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS28
CELL_E[8].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS28
CELL_E[8].IMUX_G0_DATA[2]PPC405.PLBC405ICUADDRACK
CELL_E[8].IMUX_G0_DATA[3]PPC405.TSTISOCMRDATAI3
CELL_E[8].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS29
CELL_E[8].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS29
CELL_E[8].IMUX_G1_DATA[2]PPC405.PLBC405ICUSSIZE1
CELL_E[8].IMUX_G1_DATA[3]PPC405.TSTISOCMABUSI19
CELL_E[8].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS30
CELL_E[8].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS30
CELL_E[8].IMUX_G2_DATA[2]PPC405.PLBC405ICUBUSY
CELL_E[8].IMUX_G2_DATA[3]PPC405.TSTISOCMABUSI20
CELL_E[8].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS31
CELL_E[8].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS31
CELL_E[8].IMUX_G3_DATA[2]PPC405.PLBC405ICUERR
CELL_E[8].IMUX_G3_DATA[3]PPC405.TSTISOCMABUSI21
CELL_E[8].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS28
CELL_E[8].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS29
CELL_E[8].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS30
CELL_E[8].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS31
CELL_E[8].OUT_FAN_TMIN[4]PPC405.C405PLBDCUABUS12
CELL_E[8].OUT_FAN_TMIN[5]PPC405.C405PLBDCUABUS13
CELL_E[8].OUT_FAN_TMIN[6]PPC405.C405PLBDCUABUS14
CELL_E[8].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABUS15
CELL_E[8].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO24
CELL_E[8].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO23
CELL_E[8].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO22
CELL_E[8].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO21
CELL_E[8].OUT_SEC_TMIN[12]PPC405.C405PLBICUABUS15
CELL_E[8].OUT_SEC_TMIN[13]PPC405.C405PLBICUABUS14
CELL_E[8].OUT_SEC_TMIN[14]PPC405.C405PLBICUABUS13
CELL_E[8].OUT_SEC_TMIN[15]PPC405.C405PLBICUABUS12
CELL_E[9].IMUX_CLK[0]PPC405.CPMC405CLOCK
CELL_E[9].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS24
CELL_E[9].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS24
CELL_E[9].IMUX_G0_DATA[2]PPC405.PLBC405ICURDWDADDR1
CELL_E[9].IMUX_G0_DATA[3]PPC405.TSTISOCMRDATAI4
CELL_E[9].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS25
CELL_E[9].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS25
CELL_E[9].IMUX_G1_DATA[2]PPC405.PLBC405ICURDWDADDR2
CELL_E[9].IMUX_G1_DATA[3]PPC405.TSTISOCMABUSI22
CELL_E[9].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS26
CELL_E[9].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS26
CELL_E[9].IMUX_G2_DATA[2]PPC405.PLBC405ICURDWDADDR3
CELL_E[9].IMUX_G2_DATA[3]PPC405.TSTISOCMABUSI23
CELL_E[9].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS27
CELL_E[9].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS27
CELL_E[9].IMUX_G3_DATA[2]PPC405.PLBC405ICURDDACK
CELL_E[9].IMUX_G3_DATA[3]PPC405.TSTISOCMABUSI24
CELL_E[9].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS24
CELL_E[9].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS25
CELL_E[9].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS26
CELL_E[9].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS27
CELL_E[9].OUT_FAN_TMIN[4]PPC405.C405PLBDCUABUS8
CELL_E[9].OUT_FAN_TMIN[5]PPC405.C405PLBDCUABUS9
CELL_E[9].OUT_FAN_TMIN[6]PPC405.C405PLBDCUABUS10
CELL_E[9].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABUS11
CELL_E[9].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO28
CELL_E[9].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO27
CELL_E[9].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO26
CELL_E[9].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO25
CELL_E[9].OUT_SEC_TMIN[12]PPC405.C405PLBICUABUS11
CELL_E[9].OUT_SEC_TMIN[13]PPC405.C405PLBICUABUS10
CELL_E[9].OUT_SEC_TMIN[14]PPC405.C405PLBICUABUS9
CELL_E[9].OUT_SEC_TMIN[15]PPC405.C405PLBICUABUS8
CELL_E[10].IMUX_TI[0]PPC405.TIEC405PVR15
CELL_E[10].IMUX_TI[1]PPC405.TIEC405PVR16
CELL_E[10].IMUX_TS[0]PPC405.TIEC405PVR17
CELL_E[10].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS20
CELL_E[10].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS20
CELL_E[10].IMUX_G0_DATA[2]PPC405.EICC405CRITINPUTIRQ
CELL_E[10].IMUX_G0_DATA[3]PPC405.TSTISOCMABUSI27
CELL_E[10].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS21
CELL_E[10].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS21
CELL_E[10].IMUX_G1_DATA[2]PPC405.TSTISOCMRDATAI5
CELL_E[10].IMUX_G1_DATA[3]PPC405.TSTISOCMABUSI28
CELL_E[10].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS22
CELL_E[10].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS22
CELL_E[10].IMUX_G2_DATA[2]PPC405.TSTISOCMABUSI25
CELL_E[10].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS23
CELL_E[10].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS23
CELL_E[10].IMUX_G3_DATA[2]PPC405.TSTISOCMABUSI26
CELL_E[10].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS20
CELL_E[10].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS21
CELL_E[10].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS22
CELL_E[10].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS23
CELL_E[10].OUT_FAN_TMIN[4]PPC405.C405PLBDCUABUS4
CELL_E[10].OUT_FAN_TMIN[5]PPC405.C405PLBDCUABUS5
CELL_E[10].OUT_FAN_TMIN[6]PPC405.C405PLBDCUABUS6
CELL_E[10].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABUS7
CELL_E[10].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO32
CELL_E[10].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO31
CELL_E[10].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO30
CELL_E[10].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO29
CELL_E[10].OUT_SEC_TMIN[12]PPC405.C405PLBICUABUS7
CELL_E[10].OUT_SEC_TMIN[13]PPC405.C405PLBICUABUS6
CELL_E[10].OUT_SEC_TMIN[14]PPC405.C405PLBICUABUS5
CELL_E[10].OUT_SEC_TMIN[15]PPC405.C405PLBICUABUS4
CELL_E[11].IMUX_SR[0]PPC405.RSTC405RESETCHIP
CELL_E[11].IMUX_TI[0]PPC405.TIEC405PVR12
CELL_E[11].IMUX_TI[1]PPC405.TIEC405PVR13
CELL_E[11].IMUX_TS[0]PPC405.TIEC405PVR14
CELL_E[11].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS16
CELL_E[11].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS16
CELL_E[11].IMUX_G0_DATA[2]PPC405.TSTRESETSYSI
CELL_E[11].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS17
CELL_E[11].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS17
CELL_E[11].IMUX_G1_DATA[2]PPC405.TSTISOCMRDATAI6
CELL_E[11].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS18
CELL_E[11].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS18
CELL_E[11].IMUX_G2_DATA[2]PPC405.TSTISOCMABUSI29
CELL_E[11].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS19
CELL_E[11].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS19
CELL_E[11].IMUX_G3_DATA[2]PPC405.TSTISOCMABORTI
CELL_E[11].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS16
CELL_E[11].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS17
CELL_E[11].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS18
CELL_E[11].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS19
CELL_E[11].OUT_FAN_TMIN[4]PPC405.C405PLBDCUABUS0
CELL_E[11].OUT_FAN_TMIN[5]PPC405.C405PLBDCUABUS1
CELL_E[11].OUT_FAN_TMIN[6]PPC405.C405PLBDCUABUS2
CELL_E[11].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABUS3
CELL_E[11].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO36
CELL_E[11].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO35
CELL_E[11].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO34
CELL_E[11].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO33
CELL_E[11].OUT_SEC_TMIN[12]PPC405.C405PLBICUABUS3
CELL_E[11].OUT_SEC_TMIN[13]PPC405.C405PLBICUABUS2
CELL_E[11].OUT_SEC_TMIN[14]PPC405.C405PLBICUABUS1
CELL_E[11].OUT_SEC_TMIN[15]PPC405.C405PLBICUABUS0
CELL_E[12].IMUX_SR[0]PPC405.RSTC405RESETCORE
CELL_E[12].IMUX_TI[0]PPC405.TIEC405PVR9
CELL_E[12].IMUX_TI[1]PPC405.TIEC405PVR10
CELL_E[12].IMUX_TS[0]PPC405.TIEC405PVR11
CELL_E[12].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS12
CELL_E[12].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS12
CELL_E[12].IMUX_G0_DATA[2]PPC405.TSTJTAGENI
CELL_E[12].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS13
CELL_E[12].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS13
CELL_E[12].IMUX_G1_DATA[2]PPC405.TSTISOCMRDATAI7
CELL_E[12].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS14
CELL_E[12].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS14
CELL_E[12].IMUX_G2_DATA[2]PPC405.JTGC405TRSTNEG
CELL_E[12].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS15
CELL_E[12].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS15
CELL_E[12].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS12
CELL_E[12].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS13
CELL_E[12].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS14
CELL_E[12].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS15
CELL_E[12].OUT_FAN_TMIN[4]PPC405.C405PLBDCUSIZE2
CELL_E[12].OUT_FAN_TMIN[5]PPC405.C405PLBDCUU0ATTR
CELL_E[12].OUT_FAN_TMIN[6]PPC405.C405PLBDCUCACHEABLE
CELL_E[12].OUT_FAN_TMIN[7]PPC405.C405DBGWBIAR19
CELL_E[12].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO40
CELL_E[12].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO39
CELL_E[12].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO38
CELL_E[12].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO37
CELL_E[12].OUT_SEC_TMIN[12]PPC405.C405PLBICUCACHEABLE
CELL_E[12].OUT_SEC_TMIN[13]PPC405.C405PLBICUU0ATTR
CELL_E[12].OUT_SEC_TMIN[14]PPC405.C405PLBICUSIZE3
CELL_E[12].OUT_SEC_TMIN[15]PPC405.C405PLBICUSIZE2
CELL_E[12].OUT_TEST[0]PPC405.TSTTRSTNEGO
CELL_E[13].IMUX_SR[0]PPC405.RSTC405RESETSYS
CELL_E[13].IMUX_TI[0]PPC405.TIEC405PVR6
CELL_E[13].IMUX_TI[1]PPC405.TIEC405PVR7
CELL_E[13].IMUX_TS[0]PPC405.TIEC405PVR8
CELL_E[13].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS8
CELL_E[13].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS8
CELL_E[13].IMUX_G0_DATA[2]PPC405.TSTTIMERENI
CELL_E[13].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS9
CELL_E[13].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS9
CELL_E[13].IMUX_G1_DATA[2]PPC405.TSTISOCMRDATAI8
CELL_E[13].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS10
CELL_E[13].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS10
CELL_E[13].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS11
CELL_E[13].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS11
CELL_E[13].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS8
CELL_E[13].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS9
CELL_E[13].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS10
CELL_E[13].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS11
CELL_E[13].OUT_FAN_TMIN[4]PPC405.C405PLBDCUBE0
CELL_E[13].OUT_FAN_TMIN[5]PPC405.C405PLBDCUBE1
CELL_E[13].OUT_FAN_TMIN[6]PPC405.C405PLBDCUBE2
CELL_E[13].OUT_FAN_TMIN[7]PPC405.C405PLBDCUBE3
CELL_E[13].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO44
CELL_E[13].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO43
CELL_E[13].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO42
CELL_E[13].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO41
CELL_E[13].OUT_SEC_TMIN[12]PPC405.C405DBGWBIAR23
CELL_E[13].OUT_SEC_TMIN[13]PPC405.C405DBGWBIAR9
CELL_E[13].OUT_SEC_TMIN[14]PPC405.C405DBGWBIAR2
CELL_E[13].OUT_SEC_TMIN[15]PPC405.C405DBGWBIAR1
CELL_E[14].IMUX_TI[0]PPC405.MCPPCRST
CELL_E[14].IMUX_TI[1]PPC405.TIEC405PVR3
CELL_E[14].IMUX_TS[0]PPC405.TIEC405PVR4
CELL_E[14].IMUX_TS[1]PPC405.TIEC405PVR5
CELL_E[14].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS4
CELL_E[14].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS4
CELL_E[14].IMUX_G0_DATA[2]PPC405.TSTCPUCLKENI
CELL_E[14].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS5
CELL_E[14].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS5
CELL_E[14].IMUX_G1_DATA[2]PPC405.TSTISOCMRDATAI9
CELL_E[14].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS6
CELL_E[14].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS6
CELL_E[14].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS7
CELL_E[14].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS7
CELL_E[14].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS4
CELL_E[14].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS5
CELL_E[14].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS6
CELL_E[14].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS7
CELL_E[14].OUT_FAN_TMIN[4]PPC405.C405RSTSYSRESETREQ
CELL_E[14].OUT_FAN_TMIN[5]PPC405.C405CPMCORESLEEPREQ
CELL_E[14].OUT_FAN_TMIN[6]PPC405.C405XXXMACHINECHECK
CELL_E[14].OUT_FAN_TMIN[7]PPC405.C405DBGLOADDATAONAPUDBUS
CELL_E[14].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO48
CELL_E[14].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO47
CELL_E[14].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO46
CELL_E[14].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO45
CELL_E[14].OUT_SEC_TMIN[12]PPC405.C405DBGWBIAR24
CELL_E[14].OUT_SEC_TMIN[13]PPC405.C405DBGWBIAR10
CELL_E[14].OUT_SEC_TMIN[14]PPC405.C405DBGWBIAR4
CELL_E[14].OUT_SEC_TMIN[15]PPC405.C405DBGWBIAR3
CELL_E[15].IMUX_TI[0]PPC405.TIEC405PVR0
CELL_E[15].IMUX_TI[1]PPC405.TIEC405PVR1
CELL_E[15].IMUX_TS[0]PPC405.TIEC405PVR2
CELL_E[15].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS0
CELL_E[15].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS0
CELL_E[15].IMUX_G0_DATA[2]PPC405.EICC405EXTINPUTIRQ
CELL_E[15].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS1
CELL_E[15].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS1
CELL_E[15].IMUX_G1_DATA[2]PPC405.TSTISOCMRDATAI10
CELL_E[15].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS2
CELL_E[15].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS2
CELL_E[15].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS3
CELL_E[15].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS3
CELL_E[15].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS0
CELL_E[15].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS1
CELL_E[15].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS2
CELL_E[15].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS3
CELL_E[15].OUT_FAN_TMIN[4]PPC405.C405CPMMSRCE
CELL_E[15].OUT_FAN_TMIN[5]PPC405.C405CPMMSREE
CELL_E[15].OUT_FAN_TMIN[6]PPC405.C405DBGMSRWE
CELL_E[15].OUT_FAN_TMIN[7]PPC405.C405DBGSTOPACK
CELL_E[15].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO52
CELL_E[15].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO51
CELL_E[15].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO50
CELL_E[15].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO49
CELL_E[15].OUT_SEC_TMIN[12]PPC405.C405DBGWBIAR25
CELL_E[15].OUT_SEC_TMIN[13]PPC405.C405DBGWBIAR20
CELL_E[15].OUT_SEC_TMIN[14]PPC405.C405DBGWBIAR6
CELL_E[15].OUT_SEC_TMIN[15]PPC405.C405DBGWBIAR5
CELL_S[0].IMUX_G0_DATA[0]PPC405.BRAMISOCMRDDBUS0
CELL_S[0].IMUX_G0_DATA[1]PPC405.BRAMISOCMRDDBUS4
CELL_S[0].IMUX_G0_DATA[2]PPC405.BRAMISOCMRDDBUS8
CELL_S[0].IMUX_G0_DATA[3]PPC405.BRAMISOCMRDDBUS12
CELL_S[0].IMUX_G0_DATA[4]PPC405.TSTISOCMRDATAI17
CELL_S[0].IMUX_G0_DATA[5]PPC405.TSTISOCMRDATAI49
CELL_S[0].IMUX_G0_DATA[6]PPC405.LSSDC405SCANIN8
CELL_S[0].IMUX_G1_DATA[0]PPC405.BRAMISOCMRDDBUS1
CELL_S[0].IMUX_G1_DATA[1]PPC405.BRAMISOCMRDDBUS5
CELL_S[0].IMUX_G1_DATA[2]PPC405.BRAMISOCMRDDBUS9
CELL_S[0].IMUX_G1_DATA[3]PPC405.BRAMISOCMRDDBUS13
CELL_S[0].IMUX_G1_DATA[4]PPC405.TSTISOCMRDATAI18
CELL_S[0].IMUX_G1_DATA[5]PPC405.TSTISOCMRDATAI50
CELL_S[0].IMUX_G1_DATA[6]PPC405.LSSDC405SCANIN9
CELL_S[0].IMUX_G2_DATA[0]PPC405.BRAMISOCMRDDBUS2
CELL_S[0].IMUX_G2_DATA[1]PPC405.BRAMISOCMRDDBUS6
CELL_S[0].IMUX_G2_DATA[2]PPC405.BRAMISOCMRDDBUS10
CELL_S[0].IMUX_G2_DATA[3]PPC405.BRAMISOCMRDDBUS14
CELL_S[0].IMUX_G2_DATA[4]PPC405.TSTISOCMRDATAI19
CELL_S[0].IMUX_G2_DATA[5]PPC405.LSSDC405ARRAYCCLKNEG
CELL_S[0].IMUX_G3_DATA[0]PPC405.BRAMISOCMRDDBUS3
CELL_S[0].IMUX_G3_DATA[1]PPC405.BRAMISOCMRDDBUS7
CELL_S[0].IMUX_G3_DATA[2]PPC405.BRAMISOCMRDDBUS11
CELL_S[0].IMUX_G3_DATA[3]PPC405.BRAMISOCMRDDBUS15
CELL_S[0].IMUX_G3_DATA[4]PPC405.TSTISOCMRDATAI20
CELL_S[0].IMUX_G3_DATA[5]PPC405.LSSDC405BCLK
CELL_S[0].IMUX_BRAM_ADDRA[0]PPC405.ISOCMBRAMWRABUS15
CELL_S[0].IMUX_BRAM_ADDRA[1]PPC405.ISOCMBRAMWRABUS16
CELL_S[0].IMUX_BRAM_ADDRA[2]PPC405.ISOCMBRAMWRABUS17
CELL_S[0].IMUX_BRAM_ADDRA[3]PPC405.ISOCMBRAMWRABUS18
CELL_S[0].IMUX_BRAM_ADDRA_S1[0]PPC405.ISOCMBRAMWRABUS19
CELL_S[0].IMUX_BRAM_ADDRA_S1[1]PPC405.ISOCMBRAMWRABUS20
CELL_S[0].IMUX_BRAM_ADDRA_S1[2]PPC405.ISOCMBRAMWRABUS21
CELL_S[0].IMUX_BRAM_ADDRA_S1[3]PPC405.ISOCMBRAMWRABUS22
CELL_S[0].IMUX_BRAM_ADDRA_S2[0]PPC405.ISOCMBRAMWRABUS23
CELL_S[0].IMUX_BRAM_ADDRA_S2[1]PPC405.ISOCMBRAMWRABUS24
CELL_S[0].IMUX_BRAM_ADDRA_S2[2]PPC405.ISOCMBRAMWRABUS25
CELL_S[0].IMUX_BRAM_ADDRA_S2[3]PPC405.ISOCMBRAMWRABUS26
CELL_S[0].IMUX_BRAM_ADDRA_S3[0]PPC405.ISOCMBRAMWRABUS27
CELL_S[0].IMUX_BRAM_ADDRA_S3[1]PPC405.ISOCMBRAMWRABUS28
CELL_S[0].IMUX_BRAM_ADDRB[0]PPC405.ISOCMBRAMRDABUS15
CELL_S[0].IMUX_BRAM_ADDRB[1]PPC405.ISOCMBRAMRDABUS16
CELL_S[0].IMUX_BRAM_ADDRB[2]PPC405.ISOCMBRAMRDABUS17
CELL_S[0].IMUX_BRAM_ADDRB[3]PPC405.ISOCMBRAMRDABUS18
CELL_S[0].IMUX_BRAM_ADDRB_S1[0]PPC405.ISOCMBRAMRDABUS19
CELL_S[0].IMUX_BRAM_ADDRB_S1[1]PPC405.ISOCMBRAMRDABUS20
CELL_S[0].IMUX_BRAM_ADDRB_S1[2]PPC405.ISOCMBRAMRDABUS21
CELL_S[0].IMUX_BRAM_ADDRB_S1[3]PPC405.ISOCMBRAMRDABUS22
CELL_S[0].IMUX_BRAM_ADDRB_S2[0]PPC405.ISOCMBRAMRDABUS23
CELL_S[0].IMUX_BRAM_ADDRB_S2[1]PPC405.ISOCMBRAMRDABUS24
CELL_S[0].IMUX_BRAM_ADDRB_S2[2]PPC405.ISOCMBRAMRDABUS25
CELL_S[0].IMUX_BRAM_ADDRB_S2[3]PPC405.ISOCMBRAMRDABUS26
CELL_S[0].IMUX_BRAM_ADDRB_S3[0]PPC405.ISOCMBRAMRDABUS27
CELL_S[0].IMUX_BRAM_ADDRB_S3[1]PPC405.ISOCMBRAMRDABUS28
CELL_S[0].OUT_FAN_TMIN[0]PPC405.ISOCMBRAMWRABUS8
CELL_S[0].OUT_FAN_TMIN[1]PPC405.ISOCMBRAMWRABUS9
CELL_S[0].OUT_FAN_TMIN[2]PPC405.ISOCMBRAMWRABUS10
CELL_S[0].OUT_FAN_TMIN[3]PPC405.ISOCMBRAMWRABUS11
CELL_S[0].OUT_FAN_TMIN[4]PPC405.ISOCMBRAMWRABUS12
CELL_S[0].OUT_FAN_TMIN[5]PPC405.ISOCMBRAMWRABUS13
CELL_S[0].OUT_FAN_TMIN[6]PPC405.ISOCMBRAMWRABUS14
CELL_S[0].OUT_FAN_TMIN[7]PPC405.ISOCMBRAMWRABUS15
CELL_S[0].OUT_SEC_TMIN[8]PPC405.TSTISOCMABUSO0
CELL_S[0].OUT_SEC_TMIN[9]PPC405.TSTISOCMICUREADYO
CELL_S[0].OUT_SEC_TMIN[10]PPC405.TSTISOCMREQPENDO
CELL_S[0].OUT_SEC_TMIN[11]PPC405.TSTISOCMXLATEVALIDO
CELL_S[0].OUT_SEC_TMIN[12]PPC405.ISOCMBRAMWRABUS19
CELL_S[0].OUT_SEC_TMIN[13]PPC405.ISOCMBRAMWRABUS18
CELL_S[0].OUT_SEC_TMIN[14]PPC405.ISOCMBRAMWRABUS17
CELL_S[0].OUT_SEC_TMIN[15]PPC405.ISOCMBRAMWRABUS16
CELL_S[0].OUT_TEST[0]PPC405.TSTISOCMABUSO29
CELL_S[0].OUT_TEST[2]PPC405.TSTISOCMABORTO
CELL_S[0].OUT_TEST[4]PPC405.C405ISOCMU0ATTR
CELL_S[0].OUT_TEST[6]PPC405.C405DSOCMCACHEABLE
CELL_S[1].IMUX_G0_DATA[0]PPC405.BRAMISOCMRDDBUS16
CELL_S[1].IMUX_G0_DATA[1]PPC405.BRAMISOCMRDDBUS20
CELL_S[1].IMUX_G0_DATA[2]PPC405.BRAMISOCMRDDBUS24
CELL_S[1].IMUX_G0_DATA[3]PPC405.BRAMISOCMRDDBUS28
CELL_S[1].IMUX_G0_DATA[4]PPC405.TSTISOCMRDATAI21
CELL_S[1].IMUX_G0_DATA[5]PPC405.TSTISOCMRDATAI51
CELL_S[1].IMUX_G1_DATA[0]PPC405.BRAMISOCMRDDBUS17
CELL_S[1].IMUX_G1_DATA[1]PPC405.BRAMISOCMRDDBUS21
CELL_S[1].IMUX_G1_DATA[2]PPC405.BRAMISOCMRDDBUS25
CELL_S[1].IMUX_G1_DATA[3]PPC405.BRAMISOCMRDDBUS29
CELL_S[1].IMUX_G1_DATA[4]PPC405.TSTISOCMRDATAI22
CELL_S[1].IMUX_G1_DATA[5]PPC405.TSTISOCMRDATAI52
CELL_S[1].IMUX_G2_DATA[0]PPC405.BRAMISOCMRDDBUS18
CELL_S[1].IMUX_G2_DATA[1]PPC405.BRAMISOCMRDDBUS22
CELL_S[1].IMUX_G2_DATA[2]PPC405.BRAMISOCMRDDBUS26
CELL_S[1].IMUX_G2_DATA[3]PPC405.BRAMISOCMRDDBUS30
CELL_S[1].IMUX_G2_DATA[4]PPC405.TSTISOCMRDATAI23
CELL_S[1].IMUX_G2_DATA[5]PPC405.LSSDC405BISTCCLK
CELL_S[1].IMUX_G3_DATA[0]PPC405.BRAMISOCMRDDBUS19
CELL_S[1].IMUX_G3_DATA[1]PPC405.BRAMISOCMRDDBUS23
CELL_S[1].IMUX_G3_DATA[2]PPC405.BRAMISOCMRDDBUS27
CELL_S[1].IMUX_G3_DATA[3]PPC405.BRAMISOCMRDDBUS31
CELL_S[1].IMUX_G3_DATA[4]PPC405.TSTISOCMRDATAI24
CELL_S[1].IMUX_G3_DATA[5]PPC405.LSSDC405CNTLPOINT
CELL_S[1].OUT_FAN_TMIN[0]PPC405.ISOCMBRAMWRABUS20
CELL_S[1].OUT_FAN_TMIN[1]PPC405.ISOCMBRAMWRABUS21
CELL_S[1].OUT_FAN_TMIN[2]PPC405.ISOCMBRAMWRABUS22
CELL_S[1].OUT_FAN_TMIN[3]PPC405.ISOCMBRAMWRABUS23
CELL_S[1].OUT_FAN_TMIN[4]PPC405.ISOCMBRAMWRABUS24
CELL_S[1].OUT_FAN_TMIN[5]PPC405.ISOCMBRAMWRABUS25
CELL_S[1].OUT_FAN_TMIN[6]PPC405.ISOCMBRAMWRABUS26
CELL_S[1].OUT_FAN_TMIN[7]PPC405.ISOCMBRAMWRABUS27
CELL_S[1].OUT_SEC_TMIN[8]PPC405.C405LSSDDIAGOUT
CELL_S[1].OUT_SEC_TMIN[9]PPC405.C405LSSDDIAGABISTDONE
CELL_S[1].OUT_SEC_TMIN[10]PPC405.TSTISOCMABUSO4
CELL_S[1].OUT_SEC_TMIN[11]PPC405.TSTISOCMABUSO3
CELL_S[1].OUT_SEC_TMIN[12]PPC405.TSTISOCMABUSO2
CELL_S[1].OUT_SEC_TMIN[13]PPC405.TSTISOCMABUSO1
CELL_S[1].OUT_SEC_TMIN[14]PPC405.ISOCMRDADDRVALID
CELL_S[1].OUT_SEC_TMIN[15]PPC405.ISOCMBRAMWRABUS28
CELL_S[1].OUT_TEST[0]PPC405.C405DSOCMGUARDED
CELL_S[1].OUT_TEST[2]PPC405.C405DSOCMSTRINGMULTIPLE
CELL_S[2].IMUX_SR[0]PPC405.ISCNTLVALUE0
CELL_S[2].IMUX_SR[1]PPC405.ISCNTLVALUE1
CELL_S[2].IMUX_TI[0]PPC405.TIEISOCMDCRADDR0
CELL_S[2].IMUX_TI[1]PPC405.TIEISOCMDCRADDR1
CELL_S[2].IMUX_TS[0]PPC405.TIEISOCMDCRADDR2
CELL_S[2].IMUX_TS[1]PPC405.TIEISOCMDCRADDR3
CELL_S[2].IMUX_G0_DATA[0]PPC405.ISCNTLVALUE6
CELL_S[2].IMUX_G0_DATA[1]PPC405.TSTISOCMRDATAI27
CELL_S[2].IMUX_G0_DATA[2]PPC405.LSSDC405SCANGATE
CELL_S[2].IMUX_G1_DATA[0]PPC405.ISCNTLVALUE7
CELL_S[2].IMUX_G1_DATA[1]PPC405.TSTISOCMRDATAI28
CELL_S[2].IMUX_G1_DATA[2]PPC405.LSSDC405TESTEVS
CELL_S[2].IMUX_G2_DATA[0]PPC405.TSTISOCMRDATAI25
CELL_S[2].IMUX_G2_DATA[1]PPC405.TSTISOCMRDATAI53
CELL_S[2].IMUX_G3_DATA[0]PPC405.TSTISOCMRDATAI26
CELL_S[2].IMUX_G3_DATA[1]PPC405.TSTISOCMRDATAI54
CELL_S[2].OUT_FAN_TMIN[0]PPC405.ISOCMBRAMWRDBUS0
CELL_S[2].OUT_FAN_TMIN[1]PPC405.ISOCMBRAMWRDBUS1
CELL_S[2].OUT_FAN_TMIN[2]PPC405.ISOCMBRAMWRDBUS2
CELL_S[2].OUT_FAN_TMIN[3]PPC405.ISOCMBRAMWRDBUS3
CELL_S[2].OUT_FAN_TMIN[4]PPC405.ISOCMBRAMWRDBUS4
CELL_S[2].OUT_FAN_TMIN[5]PPC405.ISOCMBRAMWRDBUS5
CELL_S[2].OUT_FAN_TMIN[6]PPC405.ISOCMBRAMWRDBUS6
CELL_S[2].OUT_FAN_TMIN[7]PPC405.ISOCMBRAMWRDBUS7
CELL_S[2].OUT_SEC_TMIN[8]PPC405.C405LSSDSCANOUT0
CELL_S[2].OUT_SEC_TMIN[9]PPC405.TSTISOCMABUSO8
CELL_S[2].OUT_SEC_TMIN[10]PPC405.TSTISOCMABUSO7
CELL_S[2].OUT_SEC_TMIN[11]PPC405.TSTISOCMABUSO6
CELL_S[2].OUT_SEC_TMIN[12]PPC405.TSTISOCMABUSO5
CELL_S[2].OUT_SEC_TMIN[13]PPC405.ISOCMBRAMEN
CELL_S[2].OUT_SEC_TMIN[14]PPC405.ISOCMBRAMEVENWRITEEN
CELL_S[2].OUT_SEC_TMIN[15]PPC405.ISOCMBRAMODDWRITEEN
CELL_S[2].OUT_TEST[0]PPC405.C405LSSDSCANOUT1
CELL_S[2].OUT_TEST[2]PPC405.C405DSOCMU0ATTR
CELL_S[3].IMUX_SR[0]PPC405.ISCNTLVALUE2
CELL_S[3].IMUX_SR[1]PPC405.ISCNTLVALUE3
CELL_S[3].IMUX_TI[0]PPC405.TIEISOCMDCRADDR4
CELL_S[3].IMUX_TI[1]PPC405.TIEISOCMDCRADDR5
CELL_S[3].IMUX_TS[0]PPC405.TIEISOCMDCRADDR6
CELL_S[3].IMUX_TS[1]PPC405.TIEISOCMDCRADDR7
CELL_S[3].IMUX_G0_DATA[0]PPC405.TSTISOCMRDATAI29
CELL_S[3].IMUX_G0_DATA[1]PPC405.TSTISOCMRDATAI55
CELL_S[3].IMUX_G1_DATA[0]PPC405.TSTISOCMRDATAI30
CELL_S[3].IMUX_G1_DATA[1]PPC405.TSTISOCMRDATAI56
CELL_S[3].IMUX_G2_DATA[0]PPC405.TSTISOCMRDATAI31
CELL_S[3].IMUX_G2_DATA[1]PPC405.LSSDC405TESTM1
CELL_S[3].IMUX_G3_DATA[0]PPC405.TSTISOCMRDATAI32
CELL_S[3].IMUX_G3_DATA[1]PPC405.LSSDC405TESTM3
CELL_S[3].OUT_FAN_TMIN[0]PPC405.ISOCMBRAMWRDBUS8
CELL_S[3].OUT_FAN_TMIN[1]PPC405.ISOCMBRAMWRDBUS9
CELL_S[3].OUT_FAN_TMIN[2]PPC405.ISOCMBRAMWRDBUS10
CELL_S[3].OUT_FAN_TMIN[3]PPC405.ISOCMBRAMWRDBUS11
CELL_S[3].OUT_FAN_TMIN[4]PPC405.ISOCMBRAMWRDBUS12
CELL_S[3].OUT_FAN_TMIN[5]PPC405.ISOCMBRAMWRDBUS13
CELL_S[3].OUT_FAN_TMIN[6]PPC405.ISOCMBRAMWRDBUS14
CELL_S[3].OUT_FAN_TMIN[7]PPC405.ISOCMBRAMWRDBUS15
CELL_S[3].OUT_SEC_TMIN[10]PPC405.C405LSSDSCANOUT3
CELL_S[3].OUT_SEC_TMIN[11]PPC405.C405LSSDSCANOUT2
CELL_S[3].OUT_SEC_TMIN[12]PPC405.TSTISOCMABUSO12
CELL_S[3].OUT_SEC_TMIN[13]PPC405.TSTISOCMABUSO11
CELL_S[3].OUT_SEC_TMIN[14]PPC405.TSTISOCMABUSO10
CELL_S[3].OUT_SEC_TMIN[15]PPC405.TSTISOCMABUSO9
CELL_S[4].IMUX_CLK[0]PPC405.BRAMISOCMCLK
CELL_S[4].IMUX_TI[0]PPC405.ISARCVALUE0
CELL_S[4].IMUX_TI[1]PPC405.ISARCVALUE1
CELL_S[4].IMUX_TS[0]PPC405.ISARCVALUE2
CELL_S[4].IMUX_TS[1]PPC405.ISARCVALUE3
CELL_S[4].IMUX_G0_DATA[0]PPC405.BRAMISOCMRDDACK
CELL_S[4].IMUX_G0_DATA[1]PPC405.TSTISOCMRDATAI36
CELL_S[4].IMUX_G0_DATA[2]PPC405.LSSDC405SCANIN1
CELL_S[4].IMUX_G1_DATA[0]PPC405.TSTISOCMRDATAI33
CELL_S[4].IMUX_G1_DATA[1]PPC405.TSTISOCMRDATAI57
CELL_S[4].IMUX_G2_DATA[0]PPC405.TSTISOCMRDATAI34
CELL_S[4].IMUX_G2_DATA[1]PPC405.TSTISOCMRDATAI58
CELL_S[4].IMUX_G3_DATA[0]PPC405.TSTISOCMRDATAI35
CELL_S[4].IMUX_G3_DATA[1]PPC405.LSSDC405SCANIN0
CELL_S[4].OUT_FAN_TMIN[0]PPC405.ISOCMBRAMWRDBUS16
CELL_S[4].OUT_FAN_TMIN[1]PPC405.ISOCMBRAMWRDBUS17
CELL_S[4].OUT_FAN_TMIN[2]PPC405.ISOCMBRAMWRDBUS18
CELL_S[4].OUT_FAN_TMIN[3]PPC405.ISOCMBRAMWRDBUS19
CELL_S[4].OUT_FAN_TMIN[4]PPC405.ISOCMBRAMWRDBUS20
CELL_S[4].OUT_FAN_TMIN[5]PPC405.ISOCMBRAMWRDBUS21
CELL_S[4].OUT_FAN_TMIN[6]PPC405.ISOCMBRAMWRDBUS22
CELL_S[4].OUT_FAN_TMIN[7]PPC405.ISOCMBRAMWRDBUS23
CELL_S[4].OUT_SEC_TMIN[10]PPC405.C405LSSDSCANOUT5
CELL_S[4].OUT_SEC_TMIN[11]PPC405.C405LSSDSCANOUT4
CELL_S[4].OUT_SEC_TMIN[12]PPC405.TSTISOCMABUSO16
CELL_S[4].OUT_SEC_TMIN[13]PPC405.TSTISOCMABUSO15
CELL_S[4].OUT_SEC_TMIN[14]PPC405.TSTISOCMABUSO14
CELL_S[4].OUT_SEC_TMIN[15]PPC405.TSTISOCMABUSO13
CELL_S[5].IMUX_TI[0]PPC405.ISARCVALUE4
CELL_S[5].IMUX_TI[1]PPC405.ISARCVALUE5
CELL_S[5].IMUX_TS[0]PPC405.ISARCVALUE6
CELL_S[5].IMUX_TS[1]PPC405.ISARCVALUE7
CELL_S[5].IMUX_G0_DATA[0]PPC405.ISCNTLVALUE4
CELL_S[5].IMUX_G0_DATA[1]PPC405.TSTISOCMRDATAI39
CELL_S[5].IMUX_G0_DATA[2]PPC405.LSSDC405SCANIN2
CELL_S[5].IMUX_G1_DATA[0]PPC405.ISCNTLVALUE5
CELL_S[5].IMUX_G1_DATA[1]PPC405.TSTISOCMRDATAI40
CELL_S[5].IMUX_G1_DATA[2]PPC405.LSSDC405SCANIN3
CELL_S[5].IMUX_G2_DATA[0]PPC405.TSTISOCMRDATAI37
CELL_S[5].IMUX_G2_DATA[1]PPC405.TSTISOCMRDATAI59
CELL_S[5].IMUX_G3_DATA[0]PPC405.TSTISOCMRDATAI38
CELL_S[5].IMUX_G3_DATA[1]PPC405.TSTISOCMRDATAI60
CELL_S[5].OUT_FAN_TMIN[0]PPC405.ISOCMBRAMWRDBUS24
CELL_S[5].OUT_FAN_TMIN[1]PPC405.ISOCMBRAMWRDBUS25
CELL_S[5].OUT_FAN_TMIN[2]PPC405.ISOCMBRAMWRDBUS26
CELL_S[5].OUT_FAN_TMIN[3]PPC405.ISOCMBRAMWRDBUS27
CELL_S[5].OUT_FAN_TMIN[4]PPC405.ISOCMBRAMWRDBUS28
CELL_S[5].OUT_FAN_TMIN[5]PPC405.ISOCMBRAMWRDBUS29
CELL_S[5].OUT_FAN_TMIN[6]PPC405.ISOCMBRAMWRDBUS30
CELL_S[5].OUT_FAN_TMIN[7]PPC405.ISOCMBRAMWRDBUS31
CELL_S[5].OUT_SEC_TMIN[10]PPC405.C405LSSDSCANOUT7
CELL_S[5].OUT_SEC_TMIN[11]PPC405.C405LSSDSCANOUT6
CELL_S[5].OUT_SEC_TMIN[12]PPC405.TSTISOCMABUSO20
CELL_S[5].OUT_SEC_TMIN[13]PPC405.TSTISOCMABUSO19
CELL_S[5].OUT_SEC_TMIN[14]PPC405.TSTISOCMABUSO18
CELL_S[5].OUT_SEC_TMIN[15]PPC405.TSTISOCMABUSO17
CELL_S[6].IMUX_G0_DATA[0]PPC405.BRAMISOCMRDDBUS32
CELL_S[6].IMUX_G0_DATA[1]PPC405.BRAMISOCMRDDBUS36
CELL_S[6].IMUX_G0_DATA[2]PPC405.BRAMISOCMRDDBUS40
CELL_S[6].IMUX_G0_DATA[3]PPC405.BRAMISOCMRDDBUS44
CELL_S[6].IMUX_G0_DATA[4]PPC405.TSTISOCMRDATAI41
CELL_S[6].IMUX_G0_DATA[5]PPC405.TSTISOCMRDATAI61
CELL_S[6].IMUX_G1_DATA[0]PPC405.BRAMISOCMRDDBUS33
CELL_S[6].IMUX_G1_DATA[1]PPC405.BRAMISOCMRDDBUS37
CELL_S[6].IMUX_G1_DATA[2]PPC405.BRAMISOCMRDDBUS41
CELL_S[6].IMUX_G1_DATA[3]PPC405.BRAMISOCMRDDBUS45
CELL_S[6].IMUX_G1_DATA[4]PPC405.TSTISOCMRDATAI42
CELL_S[6].IMUX_G1_DATA[5]PPC405.TSTISOCMRDATAI62
CELL_S[6].IMUX_G2_DATA[0]PPC405.BRAMISOCMRDDBUS34
CELL_S[6].IMUX_G2_DATA[1]PPC405.BRAMISOCMRDDBUS38
CELL_S[6].IMUX_G2_DATA[2]PPC405.BRAMISOCMRDDBUS42
CELL_S[6].IMUX_G2_DATA[3]PPC405.BRAMISOCMRDDBUS46
CELL_S[6].IMUX_G2_DATA[4]PPC405.TSTISOCMRDATAI43
CELL_S[6].IMUX_G2_DATA[5]PPC405.LSSDC405SCANIN4
CELL_S[6].IMUX_G3_DATA[0]PPC405.BRAMISOCMRDDBUS35
CELL_S[6].IMUX_G3_DATA[1]PPC405.BRAMISOCMRDDBUS39
CELL_S[6].IMUX_G3_DATA[2]PPC405.BRAMISOCMRDDBUS43
CELL_S[6].IMUX_G3_DATA[3]PPC405.BRAMISOCMRDDBUS47
CELL_S[6].IMUX_G3_DATA[4]PPC405.TSTISOCMRDATAI44
CELL_S[6].IMUX_G3_DATA[5]PPC405.LSSDC405SCANIN5
CELL_S[6].OUT_FAN_TMIN[0]PPC405.ISOCMBRAMRDABUS8
CELL_S[6].OUT_FAN_TMIN[1]PPC405.ISOCMBRAMRDABUS9
CELL_S[6].OUT_FAN_TMIN[2]PPC405.ISOCMBRAMRDABUS10
CELL_S[6].OUT_FAN_TMIN[3]PPC405.ISOCMBRAMRDABUS11
CELL_S[6].OUT_FAN_TMIN[4]PPC405.ISOCMBRAMRDABUS12
CELL_S[6].OUT_FAN_TMIN[5]PPC405.ISOCMBRAMRDABUS13
CELL_S[6].OUT_FAN_TMIN[6]PPC405.ISOCMBRAMRDABUS14
CELL_S[6].OUT_FAN_TMIN[7]PPC405.ISOCMBRAMRDABUS15
CELL_S[6].OUT_SEC_TMIN[8]PPC405.TSTISOCMABUSO24
CELL_S[6].OUT_SEC_TMIN[9]PPC405.TSTISOCMABUSO23
CELL_S[6].OUT_SEC_TMIN[10]PPC405.TSTISOCMABUSO22
CELL_S[6].OUT_SEC_TMIN[11]PPC405.TSTISOCMABUSO21
CELL_S[6].OUT_SEC_TMIN[12]PPC405.ISOCMBRAMRDABUS19
CELL_S[6].OUT_SEC_TMIN[13]PPC405.ISOCMBRAMRDABUS18
CELL_S[6].OUT_SEC_TMIN[14]PPC405.ISOCMBRAMRDABUS17
CELL_S[6].OUT_SEC_TMIN[15]PPC405.ISOCMBRAMRDABUS16
CELL_S[6].OUT_TEST[0]PPC405.C405LSSDSCANOUT8
CELL_S[6].OUT_TEST[2]PPC405.C405LSSDSCANOUT9
CELL_S[7].IMUX_G0_DATA[0]PPC405.BRAMISOCMRDDBUS48
CELL_S[7].IMUX_G0_DATA[1]PPC405.BRAMISOCMRDDBUS52
CELL_S[7].IMUX_G0_DATA[2]PPC405.BRAMISOCMRDDBUS56
CELL_S[7].IMUX_G0_DATA[3]PPC405.BRAMISOCMRDDBUS60
CELL_S[7].IMUX_G0_DATA[4]PPC405.TSTISOCMRDATAI45
CELL_S[7].IMUX_G0_DATA[5]PPC405.TSTISOCMRDATAI63
CELL_S[7].IMUX_G1_DATA[0]PPC405.BRAMISOCMRDDBUS49
CELL_S[7].IMUX_G1_DATA[1]PPC405.BRAMISOCMRDDBUS53
CELL_S[7].IMUX_G1_DATA[2]PPC405.BRAMISOCMRDDBUS57
CELL_S[7].IMUX_G1_DATA[3]PPC405.BRAMISOCMRDDBUS61
CELL_S[7].IMUX_G1_DATA[4]PPC405.TSTISOCMRDATAI46
CELL_S[7].IMUX_G1_DATA[5]PPC405.LSSDC405ACLK
CELL_S[7].IMUX_G2_DATA[0]PPC405.BRAMISOCMRDDBUS50
CELL_S[7].IMUX_G2_DATA[1]PPC405.BRAMISOCMRDDBUS54
CELL_S[7].IMUX_G2_DATA[2]PPC405.BRAMISOCMRDDBUS58
CELL_S[7].IMUX_G2_DATA[3]PPC405.BRAMISOCMRDDBUS62
CELL_S[7].IMUX_G2_DATA[4]PPC405.TSTISOCMRDATAI47
CELL_S[7].IMUX_G2_DATA[5]PPC405.LSSDC405SCANIN6
CELL_S[7].IMUX_G3_DATA[0]PPC405.BRAMISOCMRDDBUS51
CELL_S[7].IMUX_G3_DATA[1]PPC405.BRAMISOCMRDDBUS55
CELL_S[7].IMUX_G3_DATA[2]PPC405.BRAMISOCMRDDBUS59
CELL_S[7].IMUX_G3_DATA[3]PPC405.BRAMISOCMRDDBUS63
CELL_S[7].IMUX_G3_DATA[4]PPC405.TSTISOCMRDATAI48
CELL_S[7].IMUX_G3_DATA[5]PPC405.LSSDC405SCANIN7
CELL_S[7].IMUX_BRAM_ADDRA[0]PPC405.ISOCMBRAMWRABUS15
CELL_S[7].IMUX_BRAM_ADDRA[1]PPC405.ISOCMBRAMWRABUS16
CELL_S[7].IMUX_BRAM_ADDRA[2]PPC405.ISOCMBRAMWRABUS17
CELL_S[7].IMUX_BRAM_ADDRA[3]PPC405.ISOCMBRAMWRABUS18
CELL_S[7].IMUX_BRAM_ADDRA_S1[0]PPC405.ISOCMBRAMWRABUS19
CELL_S[7].IMUX_BRAM_ADDRA_S1[1]PPC405.ISOCMBRAMWRABUS20
CELL_S[7].IMUX_BRAM_ADDRA_S1[2]PPC405.ISOCMBRAMWRABUS21
CELL_S[7].IMUX_BRAM_ADDRA_S1[3]PPC405.ISOCMBRAMWRABUS22
CELL_S[7].IMUX_BRAM_ADDRA_S2[0]PPC405.ISOCMBRAMWRABUS23
CELL_S[7].IMUX_BRAM_ADDRA_S2[1]PPC405.ISOCMBRAMWRABUS24
CELL_S[7].IMUX_BRAM_ADDRA_S2[2]PPC405.ISOCMBRAMWRABUS25
CELL_S[7].IMUX_BRAM_ADDRA_S2[3]PPC405.ISOCMBRAMWRABUS26
CELL_S[7].IMUX_BRAM_ADDRA_S3[0]PPC405.ISOCMBRAMWRABUS27
CELL_S[7].IMUX_BRAM_ADDRA_S3[1]PPC405.ISOCMBRAMWRABUS28
CELL_S[7].IMUX_BRAM_ADDRB[0]PPC405.ISOCMBRAMRDABUS15
CELL_S[7].IMUX_BRAM_ADDRB[1]PPC405.ISOCMBRAMRDABUS16
CELL_S[7].IMUX_BRAM_ADDRB[2]PPC405.ISOCMBRAMRDABUS17
CELL_S[7].IMUX_BRAM_ADDRB[3]PPC405.ISOCMBRAMRDABUS18
CELL_S[7].IMUX_BRAM_ADDRB_S1[0]PPC405.ISOCMBRAMRDABUS19
CELL_S[7].IMUX_BRAM_ADDRB_S1[1]PPC405.ISOCMBRAMRDABUS20
CELL_S[7].IMUX_BRAM_ADDRB_S1[2]PPC405.ISOCMBRAMRDABUS21
CELL_S[7].IMUX_BRAM_ADDRB_S1[3]PPC405.ISOCMBRAMRDABUS22
CELL_S[7].IMUX_BRAM_ADDRB_S2[0]PPC405.ISOCMBRAMRDABUS23
CELL_S[7].IMUX_BRAM_ADDRB_S2[1]PPC405.ISOCMBRAMRDABUS24
CELL_S[7].IMUX_BRAM_ADDRB_S2[2]PPC405.ISOCMBRAMRDABUS25
CELL_S[7].IMUX_BRAM_ADDRB_S2[3]PPC405.ISOCMBRAMRDABUS26
CELL_S[7].IMUX_BRAM_ADDRB_S3[0]PPC405.ISOCMBRAMRDABUS27
CELL_S[7].IMUX_BRAM_ADDRB_S3[1]PPC405.ISOCMBRAMRDABUS28
CELL_S[7].OUT_FAN_TMIN[0]PPC405.ISOCMBRAMRDABUS20
CELL_S[7].OUT_FAN_TMIN[1]PPC405.ISOCMBRAMRDABUS21
CELL_S[7].OUT_FAN_TMIN[2]PPC405.ISOCMBRAMRDABUS22
CELL_S[7].OUT_FAN_TMIN[3]PPC405.ISOCMBRAMRDABUS23
CELL_S[7].OUT_FAN_TMIN[4]PPC405.ISOCMBRAMRDABUS24
CELL_S[7].OUT_FAN_TMIN[5]PPC405.ISOCMBRAMRDABUS25
CELL_S[7].OUT_FAN_TMIN[6]PPC405.ISOCMBRAMRDABUS26
CELL_S[7].OUT_FAN_TMIN[7]PPC405.ISOCMBRAMRDABUS27
CELL_S[7].OUT_SEC_TMIN[9]PPC405.C405ISOCMCONTEXTSYNC
CELL_S[7].OUT_SEC_TMIN[10]PPC405.C405ISOCMCACHEABLE
CELL_S[7].OUT_SEC_TMIN[11]PPC405.TSTISOCMABUSO28
CELL_S[7].OUT_SEC_TMIN[12]PPC405.TSTISOCMABUSO27
CELL_S[7].OUT_SEC_TMIN[13]PPC405.TSTISOCMABUSO26
CELL_S[7].OUT_SEC_TMIN[14]PPC405.TSTISOCMABUSO25
CELL_S[7].OUT_SEC_TMIN[15]PPC405.ISOCMBRAMRDABUS28
CELL_N[0].IMUX_G0_DATA[0]PPC405.BRAMDSOCMRDDBUS0
CELL_N[0].IMUX_G0_DATA[1]PPC405.BRAMDSOCMRDDBUS4
CELL_N[0].IMUX_G0_DATA[2]PPC405.BRAMDSOCMRDDBUS8
CELL_N[0].IMUX_G0_DATA[3]PPC405.BRAMDSOCMRDDBUS12
CELL_N[0].IMUX_G1_DATA[0]PPC405.BRAMDSOCMRDDBUS1
CELL_N[0].IMUX_G1_DATA[1]PPC405.BRAMDSOCMRDDBUS5
CELL_N[0].IMUX_G1_DATA[2]PPC405.BRAMDSOCMRDDBUS9
CELL_N[0].IMUX_G1_DATA[3]PPC405.BRAMDSOCMRDDBUS13
CELL_N[0].IMUX_G2_DATA[0]PPC405.BRAMDSOCMRDDBUS2
CELL_N[0].IMUX_G2_DATA[1]PPC405.BRAMDSOCMRDDBUS6
CELL_N[0].IMUX_G2_DATA[2]PPC405.BRAMDSOCMRDDBUS10
CELL_N[0].IMUX_G2_DATA[3]PPC405.BRAMDSOCMRDDBUS14
CELL_N[0].IMUX_G3_DATA[0]PPC405.BRAMDSOCMRDDBUS3
CELL_N[0].IMUX_G3_DATA[1]PPC405.BRAMDSOCMRDDBUS7
CELL_N[0].IMUX_G3_DATA[2]PPC405.BRAMDSOCMRDDBUS11
CELL_N[0].IMUX_G3_DATA[3]PPC405.BRAMDSOCMRDDBUS15
CELL_N[0].IMUX_BRAM_ADDRA[0]PPC405.DSOCMBRAMABUS28
CELL_N[0].IMUX_BRAM_ADDRA[1]PPC405.DSOCMBRAMABUS29
CELL_N[0].IMUX_BRAM_ADDRA_N1[0]PPC405.DSOCMBRAMABUS24
CELL_N[0].IMUX_BRAM_ADDRA_N1[1]PPC405.DSOCMBRAMABUS25
CELL_N[0].IMUX_BRAM_ADDRA_N1[2]PPC405.DSOCMBRAMABUS26
CELL_N[0].IMUX_BRAM_ADDRA_N1[3]PPC405.DSOCMBRAMABUS27
CELL_N[0].IMUX_BRAM_ADDRA_N2[0]PPC405.DSOCMBRAMABUS20
CELL_N[0].IMUX_BRAM_ADDRA_N2[1]PPC405.DSOCMBRAMABUS21
CELL_N[0].IMUX_BRAM_ADDRA_N2[2]PPC405.DSOCMBRAMABUS22
CELL_N[0].IMUX_BRAM_ADDRA_N2[3]PPC405.DSOCMBRAMABUS23
CELL_N[0].IMUX_BRAM_ADDRA_N3[0]PPC405.DSOCMBRAMABUS16
CELL_N[0].IMUX_BRAM_ADDRA_N3[1]PPC405.DSOCMBRAMABUS17
CELL_N[0].IMUX_BRAM_ADDRA_N3[2]PPC405.DSOCMBRAMABUS18
CELL_N[0].IMUX_BRAM_ADDRA_N3[3]PPC405.DSOCMBRAMABUS19
CELL_N[0].OUT_FAN_TMIN[0]PPC405.DSOCMBRAMBYTEWRITE0
CELL_N[0].OUT_FAN_TMIN[1]PPC405.DSOCMBRAMBYTEWRITE1
CELL_N[0].OUT_FAN_TMIN[2]PPC405.DSOCMBRAMBYTEWRITE2
CELL_N[0].OUT_FAN_TMIN[3]PPC405.DSOCMBRAMBYTEWRITE3
CELL_N[0].OUT_FAN_TMIN[4]PPC405.C405TRCODDEXECUTIONSTATUS1
CELL_N[0].OUT_FAN_TMIN[5]PPC405.C405TRCTRACESTATUS0
CELL_N[0].OUT_FAN_TMIN[6]PPC405.C405TRCTRACESTATUS3
CELL_N[0].OUT_FAN_TMIN[7]PPC405.C405TRCTRIGGEREVENTOUT
CELL_N[0].OUT_SEC_TMIN[9]PPC405.TSTDSOCMWRDBUSO28
CELL_N[0].OUT_SEC_TMIN[10]PPC405.TSTDSOCMWRDBUSO15
CELL_N[0].OUT_SEC_TMIN[11]PPC405.TSTDSOCMWRDBUSO14
CELL_N[0].OUT_SEC_TMIN[12]PPC405.TSTDSOCMWRDBUSO1
CELL_N[0].OUT_SEC_TMIN[13]PPC405.C405JTGSHIFTDR
CELL_N[0].OUT_SEC_TMIN[14]PPC405.C405TRCTRIGGEREVENTTYPE3
CELL_N[0].OUT_SEC_TMIN[15]PPC405.C405TRCTRIGGEREVENTTYPE2
CELL_N[1].IMUX_CLK[0]PPC405.JTGC405TCK
CELL_N[1].IMUX_TI[0]PPC405.DSCNTLVALUE0
CELL_N[1].IMUX_TI[1]PPC405.DSCNTLVALUE1
CELL_N[1].IMUX_TS[0]PPC405.DSCNTLVALUE2
CELL_N[1].IMUX_TS[1]PPC405.DSCNTLVALUE3
CELL_N[1].IMUX_G0_DATA[0]PPC405.TRCC405TRACEDISABLE
CELL_N[1].IMUX_G1_DATA[0]PPC405.JTGC405TDI
CELL_N[1].IMUX_G2_DATA[0]PPC405.JTGC405TMS
CELL_N[1].OUT_FAN_TMIN[0]PPC405.DSOCMBRAMWRDBUS0
CELL_N[1].OUT_FAN_TMIN[1]PPC405.DSOCMBRAMWRDBUS1
CELL_N[1].OUT_FAN_TMIN[2]PPC405.DSOCMBRAMWRDBUS2
CELL_N[1].OUT_FAN_TMIN[3]PPC405.DSOCMBRAMWRDBUS3
CELL_N[1].OUT_FAN_TMIN[4]PPC405.DSOCMBRAMWRDBUS4
CELL_N[1].OUT_FAN_TMIN[5]PPC405.DSOCMBRAMWRDBUS5
CELL_N[1].OUT_FAN_TMIN[6]PPC405.DSOCMBRAMWRDBUS6
CELL_N[1].OUT_FAN_TMIN[7]PPC405.DSOCMBRAMWRDBUS7
CELL_N[1].OUT_SEC_TMIN[8]PPC405.TSTDSOCMWRDBUSO3
CELL_N[1].OUT_SEC_TMIN[9]PPC405.TSTDSOCMWRDBUSO2
CELL_N[1].OUT_SEC_TMIN[10]PPC405.TSTDSOCMABUSO14
CELL_N[1].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO13
CELL_N[1].OUT_SEC_TMIN[12]PPC405.TSTDSOCMABUSO0
CELL_N[1].OUT_SEC_TMIN[13]PPC405.C405JTGTDO
CELL_N[1].OUT_SEC_TMIN[14]PPC405.C405TRCTRIGGEREVENTTYPE5
CELL_N[1].OUT_SEC_TMIN[15]PPC405.C405TRCTRIGGEREVENTTYPE4
CELL_N[1].OUT_TEST[0]PPC405.TSTDSOCMWRDBUSO16
CELL_N[1].OUT_TEST[2]PPC405.TSTDSOCMWRDBUSO17
CELL_N[1].OUT_TEST[4]PPC405.TSTDSOCMWRDBUSO29
CELL_N[2].IMUX_TI[0]PPC405.TIEDSOCMDCRADDR0
CELL_N[2].IMUX_TI[1]PPC405.DSCNTLVALUE4
CELL_N[2].IMUX_TS[0]PPC405.DSCNTLVALUE5
CELL_N[2].IMUX_TS[1]PPC405.DSCNTLVALUE6
CELL_N[2].IMUX_G0_DATA[0]PPC405.TRCC405TRIGGEREVENTIN
CELL_N[2].IMUX_G1_DATA[0]PPC405.JTGC405BNDSCANTDO
CELL_N[2].IMUX_G2_DATA[0]PPC405.TSTTRSTNEGI
CELL_N[2].IMUX_G3_DATA[0]PPC405.BRAMDSOCMRDDACK
CELL_N[2].OUT_FAN_TMIN[0]PPC405.DSOCMBRAMWRDBUS8
CELL_N[2].OUT_FAN_TMIN[1]PPC405.DSOCMBRAMWRDBUS9
CELL_N[2].OUT_FAN_TMIN[2]PPC405.DSOCMBRAMWRDBUS10
CELL_N[2].OUT_FAN_TMIN[3]PPC405.DSOCMBRAMWRDBUS11
CELL_N[2].OUT_FAN_TMIN[4]PPC405.DSOCMBRAMWRDBUS12
CELL_N[2].OUT_FAN_TMIN[5]PPC405.DSOCMBRAMWRDBUS13
CELL_N[2].OUT_FAN_TMIN[6]PPC405.DSOCMBRAMWRDBUS14
CELL_N[2].OUT_FAN_TMIN[7]PPC405.DSOCMBRAMWRDBUS15
CELL_N[2].OUT_SEC_TMIN[8]PPC405.TSTDSOCMWRDBUSO5
CELL_N[2].OUT_SEC_TMIN[9]PPC405.TSTDSOCMWRDBUSO4
CELL_N[2].OUT_SEC_TMIN[10]PPC405.TSTDSOCMABUSO16
CELL_N[2].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO15
CELL_N[2].OUT_SEC_TMIN[12]PPC405.TSTDSOCMABUSO1
CELL_N[2].OUT_SEC_TMIN[13]PPC405.C405JTGTDOEN
CELL_N[2].OUT_SEC_TMIN[14]PPC405.C405TRCTRIGGEREVENTTYPE7
CELL_N[2].OUT_SEC_TMIN[15]PPC405.C405TRCTRIGGEREVENTTYPE6
CELL_N[2].OUT_TEST[0]PPC405.TSTDSOCMWRDBUSO18
CELL_N[2].OUT_TEST[2]PPC405.TSTDSOCMWRDBUSO19
CELL_N[2].OUT_TEST[4]PPC405.TSTDSOCMWRDBUSO30
CELL_N[3].IMUX_CLK[0]PPC405.BRAMDSOCMCLK
CELL_N[3].IMUX_TI[0]PPC405.TIEDSOCMDCRADDR1
CELL_N[3].IMUX_TI[1]PPC405.TIEDSOCMDCRADDR2
CELL_N[3].IMUX_TS[0]PPC405.TIEDSOCMDCRADDR3
CELL_N[3].IMUX_TS[1]PPC405.TIEDSOCMDCRADDR4
CELL_N[3].OUT_FAN_TMIN[0]PPC405.DSOCMBRAMWRDBUS16
CELL_N[3].OUT_FAN_TMIN[1]PPC405.DSOCMBRAMWRDBUS17
CELL_N[3].OUT_FAN_TMIN[2]PPC405.DSOCMBRAMWRDBUS18
CELL_N[3].OUT_FAN_TMIN[3]PPC405.DSOCMBRAMWRDBUS19
CELL_N[3].OUT_FAN_TMIN[4]PPC405.DSOCMBRAMWRDBUS20
CELL_N[3].OUT_FAN_TMIN[5]PPC405.DSOCMBRAMWRDBUS21
CELL_N[3].OUT_FAN_TMIN[6]PPC405.DSOCMBRAMWRDBUS22
CELL_N[3].OUT_FAN_TMIN[7]PPC405.DSOCMBRAMWRDBUS23
CELL_N[3].OUT_SEC_TMIN[8]PPC405.TSTDSOCMWRDBUSO7
CELL_N[3].OUT_SEC_TMIN[9]PPC405.TSTDSOCMWRDBUSO6
CELL_N[3].OUT_SEC_TMIN[10]PPC405.TSTDSOCMABUSO18
CELL_N[3].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO17
CELL_N[3].OUT_SEC_TMIN[12]PPC405.TSTDSOCMABUSO2
CELL_N[3].OUT_SEC_TMIN[13]PPC405.C405JTGUPDATEDR
CELL_N[3].OUT_SEC_TMIN[14]PPC405.C405TRCTRIGGEREVENTTYPE9
CELL_N[3].OUT_SEC_TMIN[15]PPC405.C405TRCTRIGGEREVENTTYPE8
CELL_N[3].OUT_TEST[0]PPC405.TSTDSOCMWRDBUSO20
CELL_N[3].OUT_TEST[2]PPC405.TSTDSOCMWRDBUSO21
CELL_N[3].OUT_TEST[4]PPC405.TSTDSOCMWRDBUSO31
CELL_N[4].IMUX_TI[0]PPC405.TIEDSOCMDCRADDR5
CELL_N[4].IMUX_TI[1]PPC405.TIEDSOCMDCRADDR6
CELL_N[4].IMUX_TS[0]PPC405.TIEDSOCMDCRADDR7
CELL_N[4].IMUX_TS[1]PPC405.DSCNTLVALUE7
CELL_N[4].OUT_FAN_TMIN[0]PPC405.DSOCMBRAMWRDBUS24
CELL_N[4].OUT_FAN_TMIN[1]PPC405.DSOCMBRAMWRDBUS25
CELL_N[4].OUT_FAN_TMIN[2]PPC405.DSOCMBRAMWRDBUS26
CELL_N[4].OUT_FAN_TMIN[3]PPC405.DSOCMBRAMWRDBUS27
CELL_N[4].OUT_FAN_TMIN[4]PPC405.DSOCMBRAMWRDBUS28
CELL_N[4].OUT_FAN_TMIN[5]PPC405.DSOCMBRAMWRDBUS29
CELL_N[4].OUT_FAN_TMIN[6]PPC405.DSOCMBRAMWRDBUS30
CELL_N[4].OUT_FAN_TMIN[7]PPC405.DSOCMBRAMWRDBUS31
CELL_N[4].OUT_SEC_TMIN[8]PPC405.TSTDSOCMWRDBUSO8
CELL_N[4].OUT_SEC_TMIN[9]PPC405.TSTDSOCMABUSO20
CELL_N[4].OUT_SEC_TMIN[10]PPC405.TSTDSOCMABUSO19
CELL_N[4].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO4
CELL_N[4].OUT_SEC_TMIN[12]PPC405.TSTDSOCMABUSO3
CELL_N[4].OUT_SEC_TMIN[13]PPC405.DSOCMRDADDRVALID
CELL_N[4].OUT_SEC_TMIN[14]PPC405.C405JTGCAPTUREDR
CELL_N[4].OUT_SEC_TMIN[15]PPC405.C405TRCTRIGGEREVENTTYPE10
CELL_N[4].OUT_TEST[0]PPC405.TSTDSOCMWRDBUSO9
CELL_N[4].OUT_TEST[2]PPC405.TSTDSOCMWRDBUSO22
CELL_N[4].OUT_TEST[4]PPC405.TSTDSOCMWRDBUSO23
CELL_N[5].IMUX_TI[0]PPC405.DSARCVALUE0
CELL_N[5].IMUX_TI[1]PPC405.DSARCVALUE1
CELL_N[5].IMUX_TS[0]PPC405.DSARCVALUE2
CELL_N[5].IMUX_TS[1]PPC405.DSARCVALUE3
CELL_N[5].OUT_FAN_TMIN[0]PPC405.DSOCMBRAMABUS8
CELL_N[5].OUT_FAN_TMIN[1]PPC405.DSOCMBRAMABUS9
CELL_N[5].OUT_FAN_TMIN[2]PPC405.DSOCMBRAMABUS10
CELL_N[5].OUT_FAN_TMIN[3]PPC405.DSOCMBRAMABUS11
CELL_N[5].OUT_FAN_TMIN[4]PPC405.DSOCMBRAMABUS12
CELL_N[5].OUT_FAN_TMIN[5]PPC405.DSOCMBRAMABUS13
CELL_N[5].OUT_FAN_TMIN[6]PPC405.DSOCMBRAMABUS14
CELL_N[5].OUT_FAN_TMIN[7]PPC405.DSOCMBRAMABUS15
CELL_N[5].OUT_SEC_TMIN[8]PPC405.TSTDSOCMABUSO8
CELL_N[5].OUT_SEC_TMIN[9]PPC405.TSTDSOCMABUSO7
CELL_N[5].OUT_SEC_TMIN[10]PPC405.TSTDSOCMABUSO6
CELL_N[5].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO5
CELL_N[5].OUT_SEC_TMIN[12]PPC405.DSOCMBRAMABUS19
CELL_N[5].OUT_SEC_TMIN[13]PPC405.DSOCMBRAMABUS18
CELL_N[5].OUT_SEC_TMIN[14]PPC405.DSOCMBRAMABUS17
CELL_N[5].OUT_SEC_TMIN[15]PPC405.DSOCMBRAMABUS16
CELL_N[5].OUT_TEST[0]PPC405.TSTDSOCMABUSO21
CELL_N[5].OUT_TEST[2]PPC405.TSTDSOCMABUSO22
CELL_N[5].OUT_TEST[4]PPC405.TSTDSOCMWRDBUSO10
CELL_N[5].OUT_TEST[6]PPC405.TSTDSOCMWRDBUSO11
CELL_N[5].OUT_TEST[8]PPC405.TSTDSOCMWRDBUSO24
CELL_N[5].OUT_TEST[10]PPC405.TSTDSOCMWRDBUSO25
CELL_N[6].IMUX_TI[0]PPC405.DSARCVALUE4
CELL_N[6].IMUX_TI[1]PPC405.DSARCVALUE5
CELL_N[6].IMUX_TS[0]PPC405.DSARCVALUE6
CELL_N[6].IMUX_TS[1]PPC405.DSARCVALUE7
CELL_N[6].OUT_FAN_TMIN[0]PPC405.DSOCMBRAMABUS20
CELL_N[6].OUT_FAN_TMIN[1]PPC405.DSOCMBRAMABUS21
CELL_N[6].OUT_FAN_TMIN[2]PPC405.DSOCMBRAMABUS22
CELL_N[6].OUT_FAN_TMIN[3]PPC405.DSOCMBRAMABUS23
CELL_N[6].OUT_FAN_TMIN[4]PPC405.DSOCMBRAMABUS24
CELL_N[6].OUT_FAN_TMIN[5]PPC405.DSOCMBRAMABUS25
CELL_N[6].OUT_FAN_TMIN[6]PPC405.DSOCMBRAMABUS26
CELL_N[6].OUT_FAN_TMIN[7]PPC405.DSOCMBRAMABUS27
CELL_N[6].OUT_SEC_TMIN[8]PPC405.TSTDSOCMABUSO12
CELL_N[6].OUT_SEC_TMIN[9]PPC405.TSTDSOCMABUSO11
CELL_N[6].OUT_SEC_TMIN[10]PPC405.TSTDSOCMABUSO10
CELL_N[6].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO9
CELL_N[6].OUT_SEC_TMIN[12]PPC405.DSOCMBUSY
CELL_N[6].OUT_SEC_TMIN[13]PPC405.DSOCMBRAMEN
CELL_N[6].OUT_SEC_TMIN[14]PPC405.DSOCMBRAMABUS29
CELL_N[6].OUT_SEC_TMIN[15]PPC405.DSOCMBRAMABUS28
CELL_N[6].OUT_TEST[0]PPC405.TSTDSOCMABUSO23
CELL_N[6].OUT_TEST[2]PPC405.TSTDSOCMWRDBUSO0
CELL_N[6].OUT_TEST[4]PPC405.TSTDSOCMWRDBUSO12
CELL_N[6].OUT_TEST[6]PPC405.TSTDSOCMWRDBUSO13
CELL_N[6].OUT_TEST[8]PPC405.TSTDSOCMWRDBUSO26
CELL_N[6].OUT_TEST[10]PPC405.TSTDSOCMWRDBUSO27
CELL_N[7].IMUX_G0_DATA[0]PPC405.BRAMDSOCMRDDBUS16
CELL_N[7].IMUX_G0_DATA[1]PPC405.BRAMDSOCMRDDBUS20
CELL_N[7].IMUX_G0_DATA[2]PPC405.BRAMDSOCMRDDBUS24
CELL_N[7].IMUX_G0_DATA[3]PPC405.BRAMDSOCMRDDBUS28
CELL_N[7].IMUX_G1_DATA[0]PPC405.BRAMDSOCMRDDBUS17
CELL_N[7].IMUX_G1_DATA[1]PPC405.BRAMDSOCMRDDBUS21
CELL_N[7].IMUX_G1_DATA[2]PPC405.BRAMDSOCMRDDBUS25
CELL_N[7].IMUX_G1_DATA[3]PPC405.BRAMDSOCMRDDBUS29
CELL_N[7].IMUX_G2_DATA[0]PPC405.BRAMDSOCMRDDBUS18
CELL_N[7].IMUX_G2_DATA[1]PPC405.BRAMDSOCMRDDBUS22
CELL_N[7].IMUX_G2_DATA[2]PPC405.BRAMDSOCMRDDBUS26
CELL_N[7].IMUX_G2_DATA[3]PPC405.BRAMDSOCMRDDBUS30
CELL_N[7].IMUX_G3_DATA[0]PPC405.BRAMDSOCMRDDBUS19
CELL_N[7].IMUX_G3_DATA[1]PPC405.BRAMDSOCMRDDBUS23
CELL_N[7].IMUX_G3_DATA[2]PPC405.BRAMDSOCMRDDBUS27
CELL_N[7].IMUX_G3_DATA[3]PPC405.BRAMDSOCMRDDBUS31
CELL_N[7].IMUX_BRAM_ADDRA[0]PPC405.DSOCMBRAMABUS28
CELL_N[7].IMUX_BRAM_ADDRA[1]PPC405.DSOCMBRAMABUS29
CELL_N[7].IMUX_BRAM_ADDRA_N1[0]PPC405.DSOCMBRAMABUS24
CELL_N[7].IMUX_BRAM_ADDRA_N1[1]PPC405.DSOCMBRAMABUS25
CELL_N[7].IMUX_BRAM_ADDRA_N1[2]PPC405.DSOCMBRAMABUS26
CELL_N[7].IMUX_BRAM_ADDRA_N1[3]PPC405.DSOCMBRAMABUS27
CELL_N[7].IMUX_BRAM_ADDRA_N2[0]PPC405.DSOCMBRAMABUS20
CELL_N[7].IMUX_BRAM_ADDRA_N2[1]PPC405.DSOCMBRAMABUS21
CELL_N[7].IMUX_BRAM_ADDRA_N2[2]PPC405.DSOCMBRAMABUS22
CELL_N[7].IMUX_BRAM_ADDRA_N2[3]PPC405.DSOCMBRAMABUS23
CELL_N[7].IMUX_BRAM_ADDRA_N3[0]PPC405.DSOCMBRAMABUS16
CELL_N[7].IMUX_BRAM_ADDRA_N3[1]PPC405.DSOCMBRAMABUS17
CELL_N[7].IMUX_BRAM_ADDRA_N3[2]PPC405.DSOCMBRAMABUS18
CELL_N[7].IMUX_BRAM_ADDRA_N3[3]PPC405.DSOCMBRAMABUS19
CELL_N[7].OUT_FAN_TMIN[0]PPC405.C405TRCCYCLE
CELL_N[7].OUT_FAN_TMIN[1]PPC405.C405TRCEVENEXECUTIONSTATUS0
CELL_N[7].OUT_FAN_TMIN[2]PPC405.C405TRCEVENEXECUTIONSTATUS1
CELL_N[7].OUT_FAN_TMIN[3]PPC405.C405TRCODDEXECUTIONSTATUS0
CELL_N[7].OUT_FAN_TMIN[4]PPC405.C405TRCTRACESTATUS1
CELL_N[7].OUT_FAN_TMIN[5]PPC405.C405TRCTRACESTATUS2
CELL_N[7].OUT_FAN_TMIN[6]PPC405.C405TRCTRIGGEREVENTTYPE0
CELL_N[7].OUT_FAN_TMIN[7]PPC405.C405TRCTRIGGEREVENTTYPE1
CELL_N[7].OUT_SEC_TMIN[14]PPC405.C405JTGPGMOUT
CELL_N[7].OUT_SEC_TMIN[15]PPC405.C405JTGEXTEST

Tile PPC_E

Cells: 48

Bel PPC405

virtex2 PPC_E bel PPC405
PinDirectionWires
APUC405DCDAPUOPinputCELL_E[0].IMUX_G0_DATA[0]
APUC405DCDCRENinputCELL_E[0].IMUX_G1_DATA[0]
APUC405DCDFORCEALGNinputCELL_E[0].IMUX_G2_DATA[0]
APUC405DCDFORCEBESTEERINGinputCELL_E[0].IMUX_G3_DATA[0]
APUC405DCDFPUOPinputCELL_E[1].IMUX_G0_DATA[0]
APUC405DCDGPRWRITEinputCELL_E[1].IMUX_G1_DATA[0]
APUC405DCDLDSTBYTEinputCELL_E[1].IMUX_G2_DATA[0]
APUC405DCDLDSTDWinputCELL_E[1].IMUX_G3_DATA[0]
APUC405DCDLDSTHWinputCELL_E[2].IMUX_G0_DATA[0]
APUC405DCDLDSTQWinputCELL_E[2].IMUX_G1_DATA[0]
APUC405DCDLDSTWDinputCELL_E[2].IMUX_G2_DATA[0]
APUC405DCDLOADinputCELL_E[2].IMUX_G3_DATA[0]
APUC405DCDPRIVOPinputCELL_E[3].IMUX_G0_DATA[0]
APUC405DCDRAENinputCELL_E[3].IMUX_G1_DATA[0]
APUC405DCDRBENinputCELL_E[3].IMUX_G2_DATA[0]
APUC405DCDSTOREinputCELL_E[3].IMUX_G3_DATA[0]
APUC405DCDTRAPBEinputCELL_E[4].IMUX_G0_DATA[0]
APUC405DCDTRAPLEinputCELL_E[4].IMUX_G1_DATA[0]
APUC405DCDUPDATEinputCELL_E[5].IMUX_G0_DATA[0]
APUC405DCDVALIDOPinputCELL_E[5].IMUX_G1_DATA[0]
APUC405DCDXERCAENinputCELL_E[6].IMUX_G0_DATA[0]
APUC405DCDXEROVENinputCELL_E[6].IMUX_G1_DATA[0]
APUC405EXCEPTIONinputCELL_E[7].IMUX_G0_DATA[0]
APUC405EXEBLOCKINGMCOinputCELL_E[7].IMUX_G1_DATA[0]
APUC405EXEBUSYinputCELL_E[8].IMUX_G0_DATA[0]
APUC405EXECR0inputCELL_E[8].IMUX_G1_DATA[0]
APUC405EXECR1inputCELL_E[8].IMUX_G2_DATA[0]
APUC405EXECR2inputCELL_E[9].IMUX_G0_DATA[0]
APUC405EXECR3inputCELL_E[9].IMUX_G1_DATA[0]
APUC405EXECRFIELD0inputCELL_E[9].IMUX_G2_DATA[0]
APUC405EXECRFIELD1inputCELL_E[9].IMUX_G3_DATA[0]
APUC405EXECRFIELD2inputCELL_E[10].IMUX_G0_DATA[0]
APUC405EXELDDEPENDinputCELL_E[10].IMUX_G1_DATA[0]
APUC405EXENONBLOCKINGMCOinputCELL_E[10].IMUX_G2_DATA[0]
APUC405EXERESULT0inputCELL_E[10].IMUX_G3_DATA[0]
APUC405EXERESULT1inputCELL_E[11].IMUX_G0_DATA[0]
APUC405EXERESULT10inputCELL_E[13].IMUX_G1_DATA[0]
APUC405EXERESULT11inputCELL_E[13].IMUX_G2_DATA[0]
APUC405EXERESULT12inputCELL_E[13].IMUX_G3_DATA[0]
APUC405EXERESULT13inputCELL_E[14].IMUX_G0_DATA[0]
APUC405EXERESULT14inputCELL_E[14].IMUX_G1_DATA[0]
APUC405EXERESULT15inputCELL_E[14].IMUX_G2_DATA[0]
APUC405EXERESULT16inputCELL_E[14].IMUX_G3_DATA[0]
APUC405EXERESULT17inputCELL_E[15].IMUX_G0_DATA[0]
APUC405EXERESULT18inputCELL_E[15].IMUX_G1_DATA[0]
APUC405EXERESULT19inputCELL_E[15].IMUX_G2_DATA[0]
APUC405EXERESULT2inputCELL_E[11].IMUX_G1_DATA[0]
APUC405EXERESULT20inputCELL_E[15].IMUX_G3_DATA[0]
APUC405EXERESULT21inputCELL_E[0].IMUX_G0_DATA[1]
APUC405EXERESULT22inputCELL_E[0].IMUX_G1_DATA[1]
APUC405EXERESULT23inputCELL_E[1].IMUX_G0_DATA[1]
APUC405EXERESULT24inputCELL_E[1].IMUX_G1_DATA[1]
APUC405EXERESULT25inputCELL_E[2].IMUX_G0_DATA[1]
APUC405EXERESULT26inputCELL_E[2].IMUX_G1_DATA[1]
APUC405EXERESULT27inputCELL_E[3].IMUX_G0_DATA[1]
APUC405EXERESULT28inputCELL_E[3].IMUX_G1_DATA[1]
APUC405EXERESULT29inputCELL_E[4].IMUX_G2_DATA[0]
APUC405EXERESULT3inputCELL_E[11].IMUX_G2_DATA[0]
APUC405EXERESULT30inputCELL_E[4].IMUX_G3_DATA[0]
APUC405EXERESULT31inputCELL_E[5].IMUX_G2_DATA[0]
APUC405EXERESULT4inputCELL_E[11].IMUX_G3_DATA[0]
APUC405EXERESULT5inputCELL_E[12].IMUX_G0_DATA[0]
APUC405EXERESULT6inputCELL_E[12].IMUX_G1_DATA[0]
APUC405EXERESULT7inputCELL_E[12].IMUX_G2_DATA[0]
APUC405EXERESULT8inputCELL_E[12].IMUX_G3_DATA[0]
APUC405EXERESULT9inputCELL_E[13].IMUX_G0_DATA[0]
APUC405EXEXERCAinputCELL_E[5].IMUX_G3_DATA[0]
APUC405EXEXEROVinputCELL_E[6].IMUX_G2_DATA[0]
APUC405FPUEXCEPTIONinputCELL_E[6].IMUX_G3_DATA[0]
APUC405LWBLDDEPENDinputCELL_E[7].IMUX_G2_DATA[0]
APUC405SLEEPREQinputCELL_E[7].IMUX_G3_DATA[0]
APUC405WBLDDEPENDinputCELL_E[8].IMUX_G3_DATA[0]
BRAMDSOCMCLKinputCELL_N[3].IMUX_CLK[0]
BRAMDSOCMRDDACKinputCELL_N[2].IMUX_G3_DATA[0]
BRAMDSOCMRDDBUS0inputCELL_N[0].IMUX_G0_DATA[0]
BRAMDSOCMRDDBUS1inputCELL_N[0].IMUX_G1_DATA[0]
BRAMDSOCMRDDBUS10inputCELL_N[0].IMUX_G2_DATA[2]
BRAMDSOCMRDDBUS11inputCELL_N[0].IMUX_G3_DATA[2]
BRAMDSOCMRDDBUS12inputCELL_N[0].IMUX_G0_DATA[3]
BRAMDSOCMRDDBUS13inputCELL_N[0].IMUX_G1_DATA[3]
BRAMDSOCMRDDBUS14inputCELL_N[0].IMUX_G2_DATA[3]
BRAMDSOCMRDDBUS15inputCELL_N[0].IMUX_G3_DATA[3]
BRAMDSOCMRDDBUS16inputCELL_N[7].IMUX_G0_DATA[0]
BRAMDSOCMRDDBUS17inputCELL_N[7].IMUX_G1_DATA[0]
BRAMDSOCMRDDBUS18inputCELL_N[7].IMUX_G2_DATA[0]
BRAMDSOCMRDDBUS19inputCELL_N[7].IMUX_G3_DATA[0]
BRAMDSOCMRDDBUS2inputCELL_N[0].IMUX_G2_DATA[0]
BRAMDSOCMRDDBUS20inputCELL_N[7].IMUX_G0_DATA[1]
BRAMDSOCMRDDBUS21inputCELL_N[7].IMUX_G1_DATA[1]
BRAMDSOCMRDDBUS22inputCELL_N[7].IMUX_G2_DATA[1]
BRAMDSOCMRDDBUS23inputCELL_N[7].IMUX_G3_DATA[1]
BRAMDSOCMRDDBUS24inputCELL_N[7].IMUX_G0_DATA[2]
BRAMDSOCMRDDBUS25inputCELL_N[7].IMUX_G1_DATA[2]
BRAMDSOCMRDDBUS26inputCELL_N[7].IMUX_G2_DATA[2]
BRAMDSOCMRDDBUS27inputCELL_N[7].IMUX_G3_DATA[2]
BRAMDSOCMRDDBUS28inputCELL_N[7].IMUX_G0_DATA[3]
BRAMDSOCMRDDBUS29inputCELL_N[7].IMUX_G1_DATA[3]
BRAMDSOCMRDDBUS3inputCELL_N[0].IMUX_G3_DATA[0]
BRAMDSOCMRDDBUS30inputCELL_N[7].IMUX_G2_DATA[3]
BRAMDSOCMRDDBUS31inputCELL_N[7].IMUX_G3_DATA[3]
BRAMDSOCMRDDBUS4inputCELL_N[0].IMUX_G0_DATA[1]
BRAMDSOCMRDDBUS5inputCELL_N[0].IMUX_G1_DATA[1]
BRAMDSOCMRDDBUS6inputCELL_N[0].IMUX_G2_DATA[1]
BRAMDSOCMRDDBUS7inputCELL_N[0].IMUX_G3_DATA[1]
BRAMDSOCMRDDBUS8inputCELL_N[0].IMUX_G0_DATA[2]
BRAMDSOCMRDDBUS9inputCELL_N[0].IMUX_G1_DATA[2]
BRAMISOCMCLKinputCELL_S[4].IMUX_CLK[0]
BRAMISOCMRDDACKinputCELL_S[4].IMUX_G0_DATA[0]
BRAMISOCMRDDBUS0inputCELL_S[0].IMUX_G0_DATA[0]
BRAMISOCMRDDBUS1inputCELL_S[0].IMUX_G1_DATA[0]
BRAMISOCMRDDBUS10inputCELL_S[0].IMUX_G2_DATA[2]
BRAMISOCMRDDBUS11inputCELL_S[0].IMUX_G3_DATA[2]
BRAMISOCMRDDBUS12inputCELL_S[0].IMUX_G0_DATA[3]
BRAMISOCMRDDBUS13inputCELL_S[0].IMUX_G1_DATA[3]
BRAMISOCMRDDBUS14inputCELL_S[0].IMUX_G2_DATA[3]
BRAMISOCMRDDBUS15inputCELL_S[0].IMUX_G3_DATA[3]
BRAMISOCMRDDBUS16inputCELL_S[1].IMUX_G0_DATA[0]
BRAMISOCMRDDBUS17inputCELL_S[1].IMUX_G1_DATA[0]
BRAMISOCMRDDBUS18inputCELL_S[1].IMUX_G2_DATA[0]
BRAMISOCMRDDBUS19inputCELL_S[1].IMUX_G3_DATA[0]
BRAMISOCMRDDBUS2inputCELL_S[0].IMUX_G2_DATA[0]
BRAMISOCMRDDBUS20inputCELL_S[1].IMUX_G0_DATA[1]
BRAMISOCMRDDBUS21inputCELL_S[1].IMUX_G1_DATA[1]
BRAMISOCMRDDBUS22inputCELL_S[1].IMUX_G2_DATA[1]
BRAMISOCMRDDBUS23inputCELL_S[1].IMUX_G3_DATA[1]
BRAMISOCMRDDBUS24inputCELL_S[1].IMUX_G0_DATA[2]
BRAMISOCMRDDBUS25inputCELL_S[1].IMUX_G1_DATA[2]
BRAMISOCMRDDBUS26inputCELL_S[1].IMUX_G2_DATA[2]
BRAMISOCMRDDBUS27inputCELL_S[1].IMUX_G3_DATA[2]
BRAMISOCMRDDBUS28inputCELL_S[1].IMUX_G0_DATA[3]
BRAMISOCMRDDBUS29inputCELL_S[1].IMUX_G1_DATA[3]
BRAMISOCMRDDBUS3inputCELL_S[0].IMUX_G3_DATA[0]
BRAMISOCMRDDBUS30inputCELL_S[1].IMUX_G2_DATA[3]
BRAMISOCMRDDBUS31inputCELL_S[1].IMUX_G3_DATA[3]
BRAMISOCMRDDBUS32inputCELL_S[6].IMUX_G0_DATA[0]
BRAMISOCMRDDBUS33inputCELL_S[6].IMUX_G1_DATA[0]
BRAMISOCMRDDBUS34inputCELL_S[6].IMUX_G2_DATA[0]
BRAMISOCMRDDBUS35inputCELL_S[6].IMUX_G3_DATA[0]
BRAMISOCMRDDBUS36inputCELL_S[6].IMUX_G0_DATA[1]
BRAMISOCMRDDBUS37inputCELL_S[6].IMUX_G1_DATA[1]
BRAMISOCMRDDBUS38inputCELL_S[6].IMUX_G2_DATA[1]
BRAMISOCMRDDBUS39inputCELL_S[6].IMUX_G3_DATA[1]
BRAMISOCMRDDBUS4inputCELL_S[0].IMUX_G0_DATA[1]
BRAMISOCMRDDBUS40inputCELL_S[6].IMUX_G0_DATA[2]
BRAMISOCMRDDBUS41inputCELL_S[6].IMUX_G1_DATA[2]
BRAMISOCMRDDBUS42inputCELL_S[6].IMUX_G2_DATA[2]
BRAMISOCMRDDBUS43inputCELL_S[6].IMUX_G3_DATA[2]
BRAMISOCMRDDBUS44inputCELL_S[6].IMUX_G0_DATA[3]
BRAMISOCMRDDBUS45inputCELL_S[6].IMUX_G1_DATA[3]
BRAMISOCMRDDBUS46inputCELL_S[6].IMUX_G2_DATA[3]
BRAMISOCMRDDBUS47inputCELL_S[6].IMUX_G3_DATA[3]
BRAMISOCMRDDBUS48inputCELL_S[7].IMUX_G0_DATA[0]
BRAMISOCMRDDBUS49inputCELL_S[7].IMUX_G1_DATA[0]
BRAMISOCMRDDBUS5inputCELL_S[0].IMUX_G1_DATA[1]
BRAMISOCMRDDBUS50inputCELL_S[7].IMUX_G2_DATA[0]
BRAMISOCMRDDBUS51inputCELL_S[7].IMUX_G3_DATA[0]
BRAMISOCMRDDBUS52inputCELL_S[7].IMUX_G0_DATA[1]
BRAMISOCMRDDBUS53inputCELL_S[7].IMUX_G1_DATA[1]
BRAMISOCMRDDBUS54inputCELL_S[7].IMUX_G2_DATA[1]
BRAMISOCMRDDBUS55inputCELL_S[7].IMUX_G3_DATA[1]
BRAMISOCMRDDBUS56inputCELL_S[7].IMUX_G0_DATA[2]
BRAMISOCMRDDBUS57inputCELL_S[7].IMUX_G1_DATA[2]
BRAMISOCMRDDBUS58inputCELL_S[7].IMUX_G2_DATA[2]
BRAMISOCMRDDBUS59inputCELL_S[7].IMUX_G3_DATA[2]
BRAMISOCMRDDBUS6inputCELL_S[0].IMUX_G2_DATA[1]
BRAMISOCMRDDBUS60inputCELL_S[7].IMUX_G0_DATA[3]
BRAMISOCMRDDBUS61inputCELL_S[7].IMUX_G1_DATA[3]
BRAMISOCMRDDBUS62inputCELL_S[7].IMUX_G2_DATA[3]
BRAMISOCMRDDBUS63inputCELL_S[7].IMUX_G3_DATA[3]
BRAMISOCMRDDBUS7inputCELL_S[0].IMUX_G3_DATA[1]
BRAMISOCMRDDBUS8inputCELL_S[0].IMUX_G0_DATA[2]
BRAMISOCMRDDBUS9inputCELL_S[0].IMUX_G1_DATA[2]
C405APUDCDFULLoutputCELL_E[0].OUT_FAN_TMIN[0]
C405APUDCDHOLDoutputCELL_E[0].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION0outputCELL_E[0].OUT_FAN_TMIN[2]
C405APUDCDINSTRUCTION1outputCELL_E[0].OUT_FAN_TMIN[3]
C405APUDCDINSTRUCTION10outputCELL_E[3].OUT_FAN_TMIN[0]
C405APUDCDINSTRUCTION11outputCELL_E[3].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION12outputCELL_E[3].OUT_FAN_TMIN[2]
C405APUDCDINSTRUCTION13outputCELL_E[3].OUT_FAN_TMIN[3]
C405APUDCDINSTRUCTION14outputCELL_E[4].OUT_FAN_TMIN[0]
C405APUDCDINSTRUCTION15outputCELL_E[4].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION16outputCELL_E[4].OUT_FAN_TMIN[2]
C405APUDCDINSTRUCTION17outputCELL_E[4].OUT_FAN_TMIN[3]
C405APUDCDINSTRUCTION18outputCELL_E[5].OUT_FAN_TMIN[0]
C405APUDCDINSTRUCTION19outputCELL_E[5].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION2outputCELL_E[1].OUT_FAN_TMIN[0]
C405APUDCDINSTRUCTION20outputCELL_E[5].OUT_FAN_TMIN[2]
C405APUDCDINSTRUCTION21outputCELL_E[5].OUT_FAN_TMIN[3]
C405APUDCDINSTRUCTION22outputCELL_E[6].OUT_FAN_TMIN[0]
C405APUDCDINSTRUCTION23outputCELL_E[6].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION24outputCELL_E[6].OUT_FAN_TMIN[2]
C405APUDCDINSTRUCTION25outputCELL_E[6].OUT_FAN_TMIN[3]
C405APUDCDINSTRUCTION26outputCELL_E[7].OUT_FAN_TMIN[0]
C405APUDCDINSTRUCTION27outputCELL_E[7].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION28outputCELL_E[7].OUT_FAN_TMIN[2]
C405APUDCDINSTRUCTION29outputCELL_E[7].OUT_FAN_TMIN[3]
C405APUDCDINSTRUCTION3outputCELL_E[1].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION30outputCELL_E[8].OUT_FAN_TMIN[0]
C405APUDCDINSTRUCTION31outputCELL_E[8].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION4outputCELL_E[1].OUT_FAN_TMIN[2]
C405APUDCDINSTRUCTION5outputCELL_E[1].OUT_FAN_TMIN[3]
C405APUDCDINSTRUCTION6outputCELL_E[2].OUT_FAN_TMIN[0]
C405APUDCDINSTRUCTION7outputCELL_E[2].OUT_FAN_TMIN[1]
C405APUDCDINSTRUCTION8outputCELL_E[2].OUT_FAN_TMIN[2]
C405APUDCDINSTRUCTION9outputCELL_E[2].OUT_FAN_TMIN[3]
C405APUEXEFLUSHoutputCELL_E[8].OUT_FAN_TMIN[2]
C405APUEXEHOLDoutputCELL_E[8].OUT_FAN_TMIN[3]
C405APUEXELOADDBUS0outputCELL_E[9].OUT_FAN_TMIN[0]
C405APUEXELOADDBUS1outputCELL_E[9].OUT_FAN_TMIN[1]
C405APUEXELOADDBUS10outputCELL_E[11].OUT_FAN_TMIN[2]
C405APUEXELOADDBUS11outputCELL_E[11].OUT_FAN_TMIN[3]
C405APUEXELOADDBUS12outputCELL_E[12].OUT_FAN_TMIN[0]
C405APUEXELOADDBUS13outputCELL_E[12].OUT_FAN_TMIN[1]
C405APUEXELOADDBUS14outputCELL_E[12].OUT_FAN_TMIN[2]
C405APUEXELOADDBUS15outputCELL_E[12].OUT_FAN_TMIN[3]
C405APUEXELOADDBUS16outputCELL_E[13].OUT_FAN_TMIN[0]
C405APUEXELOADDBUS17outputCELL_E[13].OUT_FAN_TMIN[1]
C405APUEXELOADDBUS18outputCELL_E[13].OUT_FAN_TMIN[2]
C405APUEXELOADDBUS19outputCELL_E[13].OUT_FAN_TMIN[3]
C405APUEXELOADDBUS2outputCELL_E[9].OUT_FAN_TMIN[2]
C405APUEXELOADDBUS20outputCELL_E[14].OUT_FAN_TMIN[0]
C405APUEXELOADDBUS21outputCELL_E[14].OUT_FAN_TMIN[1]
C405APUEXELOADDBUS22outputCELL_E[14].OUT_FAN_TMIN[2]
C405APUEXELOADDBUS23outputCELL_E[14].OUT_FAN_TMIN[3]
C405APUEXELOADDBUS24outputCELL_E[15].OUT_FAN_TMIN[0]
C405APUEXELOADDBUS25outputCELL_E[15].OUT_FAN_TMIN[1]
C405APUEXELOADDBUS26outputCELL_E[15].OUT_FAN_TMIN[2]
C405APUEXELOADDBUS27outputCELL_E[15].OUT_FAN_TMIN[3]
C405APUEXELOADDBUS28outputCELL_E[0].OUT_FAN_TMIN[4]
C405APUEXELOADDBUS29outputCELL_E[0].OUT_FAN_TMIN[5]
C405APUEXELOADDBUS3outputCELL_E[9].OUT_FAN_TMIN[3]
C405APUEXELOADDBUS30outputCELL_E[1].OUT_FAN_TMIN[4]
C405APUEXELOADDBUS31outputCELL_E[1].OUT_FAN_TMIN[5]
C405APUEXELOADDBUS4outputCELL_E[10].OUT_FAN_TMIN[0]
C405APUEXELOADDBUS5outputCELL_E[10].OUT_FAN_TMIN[1]
C405APUEXELOADDBUS6outputCELL_E[10].OUT_FAN_TMIN[2]
C405APUEXELOADDBUS7outputCELL_E[10].OUT_FAN_TMIN[3]
C405APUEXELOADDBUS8outputCELL_E[11].OUT_FAN_TMIN[0]
C405APUEXELOADDBUS9outputCELL_E[11].OUT_FAN_TMIN[1]
C405APUEXELOADDVALIDoutputCELL_E[2].OUT_FAN_TMIN[4]
C405APUEXERADATA0outputCELL_E[2].OUT_FAN_TMIN[5]
C405APUEXERADATA1outputCELL_E[3].OUT_FAN_TMIN[4]
C405APUEXERADATA10outputCELL_E[7].OUT_FAN_TMIN[5]
C405APUEXERADATA11outputCELL_E[8].OUT_FAN_TMIN[4]
C405APUEXERADATA12outputCELL_E[8].OUT_FAN_TMIN[5]
C405APUEXERADATA13outputCELL_E[9].OUT_FAN_TMIN[4]
C405APUEXERADATA14outputCELL_E[9].OUT_FAN_TMIN[5]
C405APUEXERADATA15outputCELL_E[10].OUT_FAN_TMIN[4]
C405APUEXERADATA16outputCELL_E[10].OUT_FAN_TMIN[5]
C405APUEXERADATA17outputCELL_E[11].OUT_FAN_TMIN[4]
C405APUEXERADATA18outputCELL_E[11].OUT_FAN_TMIN[5]
C405APUEXERADATA19outputCELL_E[12].OUT_FAN_TMIN[4]
C405APUEXERADATA2outputCELL_E[3].OUT_FAN_TMIN[5]
C405APUEXERADATA20outputCELL_E[12].OUT_FAN_TMIN[5]
C405APUEXERADATA21outputCELL_E[13].OUT_FAN_TMIN[4]
C405APUEXERADATA22outputCELL_E[13].OUT_FAN_TMIN[5]
C405APUEXERADATA23outputCELL_E[14].OUT_FAN_TMIN[4]
C405APUEXERADATA24outputCELL_E[14].OUT_FAN_TMIN[5]
C405APUEXERADATA25outputCELL_E[15].OUT_FAN_TMIN[4]
C405APUEXERADATA26outputCELL_E[15].OUT_FAN_TMIN[5]
C405APUEXERADATA27outputCELL_E[0].OUT_FAN_TMIN[6]
C405APUEXERADATA28outputCELL_E[0].OUT_FAN_TMIN[7]
C405APUEXERADATA29outputCELL_E[1].OUT_FAN_TMIN[6]
C405APUEXERADATA3outputCELL_E[4].OUT_FAN_TMIN[4]
C405APUEXERADATA30outputCELL_E[1].OUT_FAN_TMIN[7]
C405APUEXERADATA31outputCELL_E[2].OUT_FAN_TMIN[6]
C405APUEXERADATA4outputCELL_E[4].OUT_FAN_TMIN[5]
C405APUEXERADATA5outputCELL_E[5].OUT_FAN_TMIN[4]
C405APUEXERADATA6outputCELL_E[5].OUT_FAN_TMIN[5]
C405APUEXERADATA7outputCELL_E[6].OUT_FAN_TMIN[4]
C405APUEXERADATA8outputCELL_E[6].OUT_FAN_TMIN[5]
C405APUEXERADATA9outputCELL_E[7].OUT_FAN_TMIN[4]
C405APUEXERBDATA0outputCELL_E[2].OUT_FAN_TMIN[7]
C405APUEXERBDATA1outputCELL_E[3].OUT_FAN_TMIN[6]
C405APUEXERBDATA10outputCELL_E[7].OUT_FAN_TMIN[7]
C405APUEXERBDATA11outputCELL_E[8].OUT_FAN_TMIN[6]
C405APUEXERBDATA12outputCELL_E[8].OUT_FAN_TMIN[7]
C405APUEXERBDATA13outputCELL_E[9].OUT_FAN_TMIN[6]
C405APUEXERBDATA14outputCELL_E[9].OUT_FAN_TMIN[7]
C405APUEXERBDATA15outputCELL_E[10].OUT_FAN_TMIN[6]
C405APUEXERBDATA16outputCELL_E[10].OUT_FAN_TMIN[7]
C405APUEXERBDATA17outputCELL_E[11].OUT_FAN_TMIN[6]
C405APUEXERBDATA18outputCELL_E[11].OUT_FAN_TMIN[7]
C405APUEXERBDATA19outputCELL_E[12].OUT_FAN_TMIN[6]
C405APUEXERBDATA2outputCELL_E[3].OUT_FAN_TMIN[7]
C405APUEXERBDATA20outputCELL_E[12].OUT_FAN_TMIN[7]
C405APUEXERBDATA21outputCELL_E[13].OUT_FAN_TMIN[6]
C405APUEXERBDATA22outputCELL_E[13].OUT_FAN_TMIN[7]
C405APUEXERBDATA23outputCELL_E[14].OUT_FAN_TMIN[6]
C405APUEXERBDATA24outputCELL_E[14].OUT_FAN_TMIN[7]
C405APUEXERBDATA25outputCELL_E[15].OUT_FAN_TMIN[6]
C405APUEXERBDATA26outputCELL_E[15].OUT_FAN_TMIN[7]
C405APUEXERBDATA27outputCELL_E[0].OUT_SEC_TMIN[15]
C405APUEXERBDATA28outputCELL_E[0].OUT_SEC_TMIN[14]
C405APUEXERBDATA29outputCELL_E[1].OUT_SEC_TMIN[15]
C405APUEXERBDATA3outputCELL_E[4].OUT_FAN_TMIN[6]
C405APUEXERBDATA30outputCELL_E[1].OUT_SEC_TMIN[14]
C405APUEXERBDATA31outputCELL_E[2].OUT_SEC_TMIN[15]
C405APUEXERBDATA4outputCELL_E[4].OUT_FAN_TMIN[7]
C405APUEXERBDATA5outputCELL_E[5].OUT_FAN_TMIN[6]
C405APUEXERBDATA6outputCELL_E[5].OUT_FAN_TMIN[7]
C405APUEXERBDATA7outputCELL_E[6].OUT_FAN_TMIN[6]
C405APUEXERBDATA8outputCELL_E[6].OUT_FAN_TMIN[7]
C405APUEXERBDATA9outputCELL_E[7].OUT_FAN_TMIN[6]
C405APUEXEWDCNT0outputCELL_E[2].OUT_SEC_TMIN[14]
C405APUEXEWDCNT1outputCELL_E[3].OUT_SEC_TMIN[15]
C405APUMSRFE0outputCELL_E[3].OUT_SEC_TMIN[14]
C405APUMSRFE1outputCELL_E[4].OUT_SEC_TMIN[15]
C405APUWBBYTEEN0outputCELL_E[4].OUT_SEC_TMIN[14]
C405APUWBBYTEEN1outputCELL_E[5].OUT_SEC_TMIN[15]
C405APUWBBYTEEN2outputCELL_E[5].OUT_SEC_TMIN[14]
C405APUWBBYTEEN3outputCELL_E[6].OUT_SEC_TMIN[15]
C405APUWBENDIANoutputCELL_E[6].OUT_SEC_TMIN[14]
C405APUWBFLUSHoutputCELL_E[7].OUT_SEC_TMIN[15]
C405APUWBHOLDoutputCELL_E[7].OUT_SEC_TMIN[14]
C405APUXERCAoutputCELL_E[8].OUT_SEC_TMIN[15]
C405CPMCORESLEEPREQoutputCELL_W[14].OUT_FAN_TMIN[5]
C405CPMMSRCEoutputCELL_W[15].OUT_FAN_TMIN[4]
C405CPMMSREEoutputCELL_W[15].OUT_FAN_TMIN[5]
C405CPMTIMERIRQoutputCELL_W[0].OUT_FAN_TMIN[6]
C405CPMTIMERRESETREQoutputCELL_W[0].OUT_FAN_TMIN[7]
C405DBGLOADDATAONAPUDBUSoutputCELL_W[14].OUT_FAN_TMIN[7]
C405DBGMSRWEoutputCELL_W[15].OUT_FAN_TMIN[6]
C405DBGSTOPACKoutputCELL_W[15].OUT_FAN_TMIN[7]
C405DBGWBCOMPLETEoutputCELL_W[0].OUT_SEC_TMIN[15]
C405DBGWBFULLoutputCELL_W[0].OUT_SEC_TMIN[14]
C405DBGWBIAR0outputCELL_W[1].OUT_SEC_TMIN[14]
C405DBGWBIAR1outputCELL_W[13].OUT_SEC_TMIN[15]
C405DBGWBIAR10outputCELL_W[14].OUT_SEC_TMIN[13]
C405DBGWBIAR11outputCELL_W[2].OUT_FAN_TMIN[6]
C405DBGWBIAR12outputCELL_W[2].OUT_FAN_TMIN[7]
C405DBGWBIAR13outputCELL_W[3].OUT_SEC_TMIN[15]
C405DBGWBIAR14outputCELL_W[3].OUT_SEC_TMIN[14]
C405DBGWBIAR15outputCELL_W[3].OUT_SEC_TMIN[13]
C405DBGWBIAR16outputCELL_W[3].OUT_SEC_TMIN[12]
C405DBGWBIAR17outputCELL_W[4].OUT_SEC_TMIN[13]
C405DBGWBIAR18outputCELL_W[4].OUT_SEC_TMIN[12]
C405DBGWBIAR19outputCELL_W[12].OUT_FAN_TMIN[7]
C405DBGWBIAR2outputCELL_W[13].OUT_SEC_TMIN[14]
C405DBGWBIAR20outputCELL_W[15].OUT_SEC_TMIN[13]
C405DBGWBIAR21outputCELL_W[0].OUT_SEC_TMIN[12]
C405DBGWBIAR22outputCELL_W[1].OUT_SEC_TMIN[12]
C405DBGWBIAR23outputCELL_W[13].OUT_SEC_TMIN[12]
C405DBGWBIAR24outputCELL_W[14].OUT_SEC_TMIN[12]
C405DBGWBIAR25outputCELL_W[15].OUT_SEC_TMIN[12]
C405DBGWBIAR26outputCELL_W[0].OUT_SEC_TMIN[11]
C405DBGWBIAR27outputCELL_W[1].OUT_SEC_TMIN[11]
C405DBGWBIAR28outputCELL_W[2].OUT_SEC_TMIN[11]
C405DBGWBIAR29outputCELL_W[3].OUT_SEC_TMIN[11]
C405DBGWBIAR3outputCELL_W[14].OUT_SEC_TMIN[15]
C405DBGWBIAR4outputCELL_W[14].OUT_SEC_TMIN[14]
C405DBGWBIAR5outputCELL_W[15].OUT_SEC_TMIN[15]
C405DBGWBIAR6outputCELL_W[15].OUT_SEC_TMIN[14]
C405DBGWBIAR7outputCELL_W[0].OUT_SEC_TMIN[13]
C405DBGWBIAR8outputCELL_W[1].OUT_SEC_TMIN[13]
C405DBGWBIAR9outputCELL_W[13].OUT_SEC_TMIN[13]
C405DCRABUS0outputCELL_E[8].OUT_SEC_TMIN[14]
C405DCRABUS1outputCELL_E[9].OUT_SEC_TMIN[15]
C405DCRABUS2outputCELL_E[9].OUT_SEC_TMIN[14]
C405DCRABUS3outputCELL_E[10].OUT_SEC_TMIN[15]
C405DCRABUS4outputCELL_E[10].OUT_SEC_TMIN[14]
C405DCRABUS5outputCELL_E[11].OUT_SEC_TMIN[15]
C405DCRABUS6outputCELL_E[11].OUT_SEC_TMIN[14]
C405DCRABUS7outputCELL_E[12].OUT_SEC_TMIN[15]
C405DCRABUS8outputCELL_E[12].OUT_SEC_TMIN[14]
C405DCRABUS9outputCELL_E[13].OUT_SEC_TMIN[15]
C405DCRDBUSOUT0outputCELL_E[13].OUT_SEC_TMIN[14]
C405DCRDBUSOUT1outputCELL_E[14].OUT_SEC_TMIN[15]
C405DCRDBUSOUT10outputCELL_E[5].OUT_SEC_TMIN[13]
C405DCRDBUSOUT11outputCELL_E[6].OUT_SEC_TMIN[13]
C405DCRDBUSOUT12outputCELL_E[7].OUT_SEC_TMIN[13]
C405DCRDBUSOUT13outputCELL_E[8].OUT_SEC_TMIN[13]
C405DCRDBUSOUT14outputCELL_E[9].OUT_SEC_TMIN[13]
C405DCRDBUSOUT15outputCELL_E[10].OUT_SEC_TMIN[13]
C405DCRDBUSOUT16outputCELL_E[11].OUT_SEC_TMIN[13]
C405DCRDBUSOUT17outputCELL_E[12].OUT_SEC_TMIN[13]
C405DCRDBUSOUT18outputCELL_E[13].OUT_SEC_TMIN[13]
C405DCRDBUSOUT19outputCELL_E[14].OUT_SEC_TMIN[13]
C405DCRDBUSOUT2outputCELL_E[14].OUT_SEC_TMIN[14]
C405DCRDBUSOUT20outputCELL_E[15].OUT_SEC_TMIN[13]
C405DCRDBUSOUT21outputCELL_E[0].OUT_SEC_TMIN[12]
C405DCRDBUSOUT22outputCELL_E[1].OUT_SEC_TMIN[12]
C405DCRDBUSOUT23outputCELL_E[2].OUT_SEC_TMIN[12]
C405DCRDBUSOUT24outputCELL_E[3].OUT_SEC_TMIN[12]
C405DCRDBUSOUT25outputCELL_E[4].OUT_SEC_TMIN[12]
C405DCRDBUSOUT26outputCELL_E[5].OUT_SEC_TMIN[12]
C405DCRDBUSOUT27outputCELL_E[6].OUT_SEC_TMIN[12]
C405DCRDBUSOUT28outputCELL_E[7].OUT_SEC_TMIN[12]
C405DCRDBUSOUT29outputCELL_E[8].OUT_SEC_TMIN[12]
C405DCRDBUSOUT3outputCELL_E[15].OUT_SEC_TMIN[15]
C405DCRDBUSOUT30outputCELL_E[9].OUT_SEC_TMIN[12]
C405DCRDBUSOUT31outputCELL_E[10].OUT_SEC_TMIN[12]
C405DCRDBUSOUT4outputCELL_E[15].OUT_SEC_TMIN[14]
C405DCRDBUSOUT5outputCELL_E[0].OUT_SEC_TMIN[13]
C405DCRDBUSOUT6outputCELL_E[1].OUT_SEC_TMIN[13]
C405DCRDBUSOUT7outputCELL_E[2].OUT_SEC_TMIN[13]
C405DCRDBUSOUT8outputCELL_E[3].OUT_SEC_TMIN[13]
C405DCRDBUSOUT9outputCELL_E[4].OUT_SEC_TMIN[13]
C405DCRREADoutputCELL_E[11].OUT_SEC_TMIN[12]
C405DCRWRITEoutputCELL_E[12].OUT_SEC_TMIN[12]
C405DSOCMCACHEABLEoutputCELL_S[0].OUT_TEST[6]
C405DSOCMGUARDEDoutputCELL_S[1].OUT_TEST[0]
C405DSOCMSTRINGMULTIPLEoutputCELL_S[1].OUT_TEST[2]
C405DSOCMU0ATTRoutputCELL_S[2].OUT_TEST[2]
C405ISOCMCACHEABLEoutputCELL_S[7].OUT_SEC_TMIN[10]
C405ISOCMCONTEXTSYNCoutputCELL_S[7].OUT_SEC_TMIN[9]
C405ISOCMU0ATTRoutputCELL_S[0].OUT_TEST[4]
C405JTGCAPTUREDRoutputCELL_N[4].OUT_SEC_TMIN[14]
C405JTGEXTESToutputCELL_N[7].OUT_SEC_TMIN[15]
C405JTGPGMOUToutputCELL_N[7].OUT_SEC_TMIN[14]
C405JTGSHIFTDRoutputCELL_N[0].OUT_SEC_TMIN[13]
C405JTGTDOoutputCELL_N[1].OUT_SEC_TMIN[13]
C405JTGTDOENoutputCELL_N[2].OUT_SEC_TMIN[13]
C405JTGUPDATEDRoutputCELL_N[3].OUT_SEC_TMIN[13]
C405LSSDDIAGABISTDONEoutputCELL_S[1].OUT_SEC_TMIN[9]
C405LSSDDIAGOUToutputCELL_S[1].OUT_SEC_TMIN[8]
C405LSSDSCANOUT0outputCELL_S[2].OUT_SEC_TMIN[8]
C405LSSDSCANOUT1outputCELL_S[2].OUT_TEST[0]
C405LSSDSCANOUT2outputCELL_S[3].OUT_SEC_TMIN[11]
C405LSSDSCANOUT3outputCELL_S[3].OUT_SEC_TMIN[10]
C405LSSDSCANOUT4outputCELL_S[4].OUT_SEC_TMIN[11]
C405LSSDSCANOUT5outputCELL_S[4].OUT_SEC_TMIN[10]
C405LSSDSCANOUT6outputCELL_S[5].OUT_SEC_TMIN[11]
C405LSSDSCANOUT7outputCELL_S[5].OUT_SEC_TMIN[10]
C405LSSDSCANOUT8outputCELL_S[6].OUT_TEST[0]
C405LSSDSCANOUT9outputCELL_S[6].OUT_TEST[2]
C405PLBDCUABORToutputCELL_W[1].OUT_FAN_TMIN[7]
C405PLBDCUABUS0outputCELL_W[11].OUT_FAN_TMIN[4]
C405PLBDCUABUS1outputCELL_W[11].OUT_FAN_TMIN[5]
C405PLBDCUABUS10outputCELL_W[9].OUT_FAN_TMIN[6]
C405PLBDCUABUS11outputCELL_W[9].OUT_FAN_TMIN[7]
C405PLBDCUABUS12outputCELL_W[8].OUT_FAN_TMIN[4]
C405PLBDCUABUS13outputCELL_W[8].OUT_FAN_TMIN[5]
C405PLBDCUABUS14outputCELL_W[8].OUT_FAN_TMIN[6]
C405PLBDCUABUS15outputCELL_W[8].OUT_FAN_TMIN[7]
C405PLBDCUABUS16outputCELL_W[7].OUT_FAN_TMIN[4]
C405PLBDCUABUS17outputCELL_W[7].OUT_FAN_TMIN[5]
C405PLBDCUABUS18outputCELL_W[7].OUT_FAN_TMIN[6]
C405PLBDCUABUS19outputCELL_W[7].OUT_FAN_TMIN[7]
C405PLBDCUABUS2outputCELL_W[11].OUT_FAN_TMIN[6]
C405PLBDCUABUS20outputCELL_W[6].OUT_FAN_TMIN[4]
C405PLBDCUABUS21outputCELL_W[6].OUT_FAN_TMIN[5]
C405PLBDCUABUS22outputCELL_W[6].OUT_FAN_TMIN[6]
C405PLBDCUABUS23outputCELL_W[6].OUT_FAN_TMIN[7]
C405PLBDCUABUS24outputCELL_W[5].OUT_FAN_TMIN[4]
C405PLBDCUABUS25outputCELL_W[5].OUT_FAN_TMIN[5]
C405PLBDCUABUS26outputCELL_W[5].OUT_FAN_TMIN[6]
C405PLBDCUABUS27outputCELL_W[5].OUT_FAN_TMIN[7]
C405PLBDCUABUS28outputCELL_W[4].OUT_FAN_TMIN[4]
C405PLBDCUABUS29outputCELL_W[4].OUT_FAN_TMIN[5]
C405PLBDCUABUS3outputCELL_W[11].OUT_FAN_TMIN[7]
C405PLBDCUABUS30outputCELL_W[4].OUT_FAN_TMIN[6]
C405PLBDCUABUS31outputCELL_W[4].OUT_FAN_TMIN[7]
C405PLBDCUABUS4outputCELL_W[10].OUT_FAN_TMIN[4]
C405PLBDCUABUS5outputCELL_W[10].OUT_FAN_TMIN[5]
C405PLBDCUABUS6outputCELL_W[10].OUT_FAN_TMIN[6]
C405PLBDCUABUS7outputCELL_W[10].OUT_FAN_TMIN[7]
C405PLBDCUABUS8outputCELL_W[9].OUT_FAN_TMIN[4]
C405PLBDCUABUS9outputCELL_W[9].OUT_FAN_TMIN[5]
C405PLBDCUBE0outputCELL_W[13].OUT_FAN_TMIN[4]
C405PLBDCUBE1outputCELL_W[13].OUT_FAN_TMIN[5]
C405PLBDCUBE2outputCELL_W[13].OUT_FAN_TMIN[6]
C405PLBDCUBE3outputCELL_W[13].OUT_FAN_TMIN[7]
C405PLBDCUBE4outputCELL_W[3].OUT_FAN_TMIN[4]
C405PLBDCUBE5outputCELL_W[3].OUT_FAN_TMIN[5]
C405PLBDCUBE6outputCELL_W[3].OUT_FAN_TMIN[6]
C405PLBDCUBE7outputCELL_W[3].OUT_FAN_TMIN[7]
C405PLBDCUCACHEABLEoutputCELL_W[12].OUT_FAN_TMIN[6]
C405PLBDCUGUARDEDoutputCELL_W[2].OUT_FAN_TMIN[4]
C405PLBDCUPRIORITY0outputCELL_W[1].OUT_FAN_TMIN[5]
C405PLBDCUPRIORITY1outputCELL_W[1].OUT_FAN_TMIN[6]
C405PLBDCUREQUESToutputCELL_W[1].OUT_FAN_TMIN[4]
C405PLBDCURNWoutputCELL_W[1].OUT_SEC_TMIN[15]
C405PLBDCUSIZE2outputCELL_W[12].OUT_FAN_TMIN[4]
C405PLBDCUU0ATTRoutputCELL_W[12].OUT_FAN_TMIN[5]
C405PLBDCUWRDBUS0outputCELL_W[15].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS1outputCELL_W[15].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS10outputCELL_W[13].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS11outputCELL_W[13].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS12outputCELL_W[12].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS13outputCELL_W[12].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS14outputCELL_W[12].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS15outputCELL_W[12].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS16outputCELL_W[11].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS17outputCELL_W[11].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS18outputCELL_W[11].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS19outputCELL_W[11].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS2outputCELL_W[15].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS20outputCELL_W[10].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS21outputCELL_W[10].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS22outputCELL_W[10].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS23outputCELL_W[10].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS24outputCELL_W[9].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS25outputCELL_W[9].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS26outputCELL_W[9].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS27outputCELL_W[9].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS28outputCELL_W[8].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS29outputCELL_W[8].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS3outputCELL_W[15].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS30outputCELL_W[8].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS31outputCELL_W[8].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS32outputCELL_W[7].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS33outputCELL_W[7].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS34outputCELL_W[7].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS35outputCELL_W[7].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS36outputCELL_W[6].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS37outputCELL_W[6].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS38outputCELL_W[6].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS39outputCELL_W[6].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS4outputCELL_W[14].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS40outputCELL_W[5].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS41outputCELL_W[5].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS42outputCELL_W[5].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS43outputCELL_W[5].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS44outputCELL_W[4].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS45outputCELL_W[4].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS46outputCELL_W[4].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS47outputCELL_W[4].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS48outputCELL_W[3].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS49outputCELL_W[3].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS5outputCELL_W[14].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS50outputCELL_W[3].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS51outputCELL_W[3].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS52outputCELL_W[2].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS53outputCELL_W[2].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS54outputCELL_W[2].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS55outputCELL_W[2].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS56outputCELL_W[1].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS57outputCELL_W[1].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS58outputCELL_W[1].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS59outputCELL_W[1].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS6outputCELL_W[14].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS60outputCELL_W[0].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS61outputCELL_W[0].OUT_FAN_TMIN[1]
C405PLBDCUWRDBUS62outputCELL_W[0].OUT_FAN_TMIN[2]
C405PLBDCUWRDBUS63outputCELL_W[0].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS7outputCELL_W[14].OUT_FAN_TMIN[3]
C405PLBDCUWRDBUS8outputCELL_W[13].OUT_FAN_TMIN[0]
C405PLBDCUWRDBUS9outputCELL_W[13].OUT_FAN_TMIN[1]
C405PLBDCUWRITETHRUoutputCELL_W[2].OUT_FAN_TMIN[5]
C405PLBICUABORToutputCELL_W[2].OUT_SEC_TMIN[12]
C405PLBICUABUS0outputCELL_W[11].OUT_SEC_TMIN[15]
C405PLBICUABUS1outputCELL_W[11].OUT_SEC_TMIN[14]
C405PLBICUABUS10outputCELL_W[9].OUT_SEC_TMIN[13]
C405PLBICUABUS11outputCELL_W[9].OUT_SEC_TMIN[12]
C405PLBICUABUS12outputCELL_W[8].OUT_SEC_TMIN[15]
C405PLBICUABUS13outputCELL_W[8].OUT_SEC_TMIN[14]
C405PLBICUABUS14outputCELL_W[8].OUT_SEC_TMIN[13]
C405PLBICUABUS15outputCELL_W[8].OUT_SEC_TMIN[12]
C405PLBICUABUS16outputCELL_W[7].OUT_SEC_TMIN[15]
C405PLBICUABUS17outputCELL_W[7].OUT_SEC_TMIN[14]
C405PLBICUABUS18outputCELL_W[7].OUT_SEC_TMIN[13]
C405PLBICUABUS19outputCELL_W[7].OUT_SEC_TMIN[12]
C405PLBICUABUS2outputCELL_W[11].OUT_SEC_TMIN[13]
C405PLBICUABUS20outputCELL_W[6].OUT_SEC_TMIN[15]
C405PLBICUABUS21outputCELL_W[6].OUT_SEC_TMIN[14]
C405PLBICUABUS22outputCELL_W[6].OUT_SEC_TMIN[13]
C405PLBICUABUS23outputCELL_W[6].OUT_SEC_TMIN[12]
C405PLBICUABUS24outputCELL_W[5].OUT_SEC_TMIN[15]
C405PLBICUABUS25outputCELL_W[5].OUT_SEC_TMIN[14]
C405PLBICUABUS26outputCELL_W[5].OUT_SEC_TMIN[13]
C405PLBICUABUS27outputCELL_W[5].OUT_SEC_TMIN[12]
C405PLBICUABUS28outputCELL_W[4].OUT_SEC_TMIN[15]
C405PLBICUABUS29outputCELL_W[4].OUT_SEC_TMIN[14]
C405PLBICUABUS3outputCELL_W[11].OUT_SEC_TMIN[12]
C405PLBICUABUS4outputCELL_W[10].OUT_SEC_TMIN[15]
C405PLBICUABUS5outputCELL_W[10].OUT_SEC_TMIN[14]
C405PLBICUABUS6outputCELL_W[10].OUT_SEC_TMIN[13]
C405PLBICUABUS7outputCELL_W[10].OUT_SEC_TMIN[12]
C405PLBICUABUS8outputCELL_W[9].OUT_SEC_TMIN[15]
C405PLBICUABUS9outputCELL_W[9].OUT_SEC_TMIN[14]
C405PLBICUCACHEABLEoutputCELL_W[12].OUT_SEC_TMIN[12]
C405PLBICUPRIORITY0outputCELL_W[2].OUT_SEC_TMIN[14]
C405PLBICUPRIORITY1outputCELL_W[2].OUT_SEC_TMIN[13]
C405PLBICUREQUESToutputCELL_W[2].OUT_SEC_TMIN[15]
C405PLBICUSIZE2outputCELL_W[12].OUT_SEC_TMIN[15]
C405PLBICUSIZE3outputCELL_W[12].OUT_SEC_TMIN[14]
C405PLBICUU0ATTRoutputCELL_W[12].OUT_SEC_TMIN[13]
C405RSTCHIPRESETREQoutputCELL_W[0].OUT_FAN_TMIN[4]
C405RSTCORERESETREQoutputCELL_W[0].OUT_FAN_TMIN[5]
C405RSTSYSRESETREQoutputCELL_W[14].OUT_FAN_TMIN[4]
C405TRCCYCLEoutputCELL_N[7].OUT_FAN_TMIN[0]
C405TRCEVENEXECUTIONSTATUS0outputCELL_N[7].OUT_FAN_TMIN[1]
C405TRCEVENEXECUTIONSTATUS1outputCELL_N[7].OUT_FAN_TMIN[2]
C405TRCODDEXECUTIONSTATUS0outputCELL_N[7].OUT_FAN_TMIN[3]
C405TRCODDEXECUTIONSTATUS1outputCELL_N[0].OUT_FAN_TMIN[4]
C405TRCTRACESTATUS0outputCELL_N[0].OUT_FAN_TMIN[5]
C405TRCTRACESTATUS1outputCELL_N[7].OUT_FAN_TMIN[4]
C405TRCTRACESTATUS2outputCELL_N[7].OUT_FAN_TMIN[5]
C405TRCTRACESTATUS3outputCELL_N[0].OUT_FAN_TMIN[6]
C405TRCTRIGGEREVENTOUToutputCELL_N[0].OUT_FAN_TMIN[7]
C405TRCTRIGGEREVENTTYPE0outputCELL_N[7].OUT_FAN_TMIN[6]
C405TRCTRIGGEREVENTTYPE1outputCELL_N[7].OUT_FAN_TMIN[7]
C405TRCTRIGGEREVENTTYPE10outputCELL_N[4].OUT_SEC_TMIN[15]
C405TRCTRIGGEREVENTTYPE2outputCELL_N[0].OUT_SEC_TMIN[15]
C405TRCTRIGGEREVENTTYPE3outputCELL_N[0].OUT_SEC_TMIN[14]
C405TRCTRIGGEREVENTTYPE4outputCELL_N[1].OUT_SEC_TMIN[15]
C405TRCTRIGGEREVENTTYPE5outputCELL_N[1].OUT_SEC_TMIN[14]
C405TRCTRIGGEREVENTTYPE6outputCELL_N[2].OUT_SEC_TMIN[15]
C405TRCTRIGGEREVENTTYPE7outputCELL_N[2].OUT_SEC_TMIN[14]
C405TRCTRIGGEREVENTTYPE8outputCELL_N[3].OUT_SEC_TMIN[15]
C405TRCTRIGGEREVENTTYPE9outputCELL_N[3].OUT_SEC_TMIN[14]
C405XXXMACHINECHECKoutputCELL_W[14].OUT_FAN_TMIN[6]
CPMC405CLOCKinputCELL_W[9].IMUX_CLK[0]
CPMC405CORECLKINACTIVEinputCELL_W[5].IMUX_G1_DATA[2]
CPMC405CPUCLKENinputCELL_W[1].IMUX_CE[0]
CPMC405JTAGCLKENinputCELL_W[3].IMUX_CE[0]
CPMC405TIMERCLKENinputCELL_W[2].IMUX_CE[0]
CPMC405TIMERTICKinputCELL_W[3].IMUX_CLK[0]
DBGC405DEBUGHALTinputCELL_W[1].IMUX_G0_DATA[2]
DBGC405EXTBUSHOLDACKinputCELL_W[4].IMUX_G0_DATA[2]
DBGC405UNCONDDEBUGEVENTinputCELL_W[2].IMUX_G0_DATA[2]
DCRC405ACKinputCELL_E[8].IMUX_G0_DATA[1]
DCRC405DBUSIN0inputCELL_E[9].IMUX_G0_DATA[1]
DCRC405DBUSIN1inputCELL_E[9].IMUX_G1_DATA[1]
DCRC405DBUSIN10inputCELL_E[14].IMUX_G0_DATA[1]
DCRC405DBUSIN11inputCELL_E[14].IMUX_G1_DATA[1]
DCRC405DBUSIN12inputCELL_E[15].IMUX_G0_DATA[1]
DCRC405DBUSIN13inputCELL_E[15].IMUX_G1_DATA[1]
DCRC405DBUSIN14inputCELL_E[0].IMUX_G2_DATA[1]
DCRC405DBUSIN15inputCELL_E[0].IMUX_G3_DATA[1]
DCRC405DBUSIN16inputCELL_E[1].IMUX_G2_DATA[1]
DCRC405DBUSIN17inputCELL_E[1].IMUX_G3_DATA[1]
DCRC405DBUSIN18inputCELL_E[2].IMUX_G2_DATA[1]
DCRC405DBUSIN19inputCELL_E[2].IMUX_G3_DATA[1]
DCRC405DBUSIN2inputCELL_E[10].IMUX_G0_DATA[1]
DCRC405DBUSIN20inputCELL_E[3].IMUX_G2_DATA[1]
DCRC405DBUSIN21inputCELL_E[3].IMUX_G3_DATA[1]
DCRC405DBUSIN22inputCELL_E[4].IMUX_G0_DATA[1]
DCRC405DBUSIN23inputCELL_E[4].IMUX_G1_DATA[1]
DCRC405DBUSIN24inputCELL_E[5].IMUX_G0_DATA[1]
DCRC405DBUSIN25inputCELL_E[5].IMUX_G1_DATA[1]
DCRC405DBUSIN26inputCELL_E[6].IMUX_G0_DATA[1]
DCRC405DBUSIN27inputCELL_E[6].IMUX_G1_DATA[1]
DCRC405DBUSIN28inputCELL_E[7].IMUX_G0_DATA[1]
DCRC405DBUSIN29inputCELL_E[7].IMUX_G1_DATA[1]
DCRC405DBUSIN3inputCELL_E[10].IMUX_G1_DATA[1]
DCRC405DBUSIN30inputCELL_E[8].IMUX_G1_DATA[1]
DCRC405DBUSIN31inputCELL_E[8].IMUX_G2_DATA[1]
DCRC405DBUSIN4inputCELL_E[11].IMUX_G0_DATA[1]
DCRC405DBUSIN5inputCELL_E[11].IMUX_G1_DATA[1]
DCRC405DBUSIN6inputCELL_E[12].IMUX_G0_DATA[1]
DCRC405DBUSIN7inputCELL_E[12].IMUX_G1_DATA[1]
DCRC405DBUSIN8inputCELL_E[13].IMUX_G0_DATA[1]
DCRC405DBUSIN9inputCELL_E[13].IMUX_G1_DATA[1]
DSARCVALUE0inputCELL_N[5].IMUX_TI[0]
DSARCVALUE1inputCELL_N[5].IMUX_TI[1]
DSARCVALUE2inputCELL_N[5].IMUX_TS[0]
DSARCVALUE3inputCELL_N[5].IMUX_TS[1]
DSARCVALUE4inputCELL_N[6].IMUX_TI[0]
DSARCVALUE5inputCELL_N[6].IMUX_TI[1]
DSARCVALUE6inputCELL_N[6].IMUX_TS[0]
DSARCVALUE7inputCELL_N[6].IMUX_TS[1]
DSCNTLVALUE0inputCELL_N[1].IMUX_TI[0]
DSCNTLVALUE1inputCELL_N[1].IMUX_TI[1]
DSCNTLVALUE2inputCELL_N[1].IMUX_TS[0]
DSCNTLVALUE3inputCELL_N[1].IMUX_TS[1]
DSCNTLVALUE4inputCELL_N[2].IMUX_TI[1]
DSCNTLVALUE5inputCELL_N[2].IMUX_TS[0]
DSCNTLVALUE6inputCELL_N[2].IMUX_TS[1]
DSCNTLVALUE7inputCELL_N[4].IMUX_TS[1]
DSOCMBRAMABUS10outputCELL_N[5].OUT_FAN_TMIN[2]
DSOCMBRAMABUS11outputCELL_N[5].OUT_FAN_TMIN[3]
DSOCMBRAMABUS12outputCELL_N[5].OUT_FAN_TMIN[4]
DSOCMBRAMABUS13outputCELL_N[5].OUT_FAN_TMIN[5]
DSOCMBRAMABUS14outputCELL_N[5].OUT_FAN_TMIN[6]
DSOCMBRAMABUS15outputCELL_N[5].OUT_FAN_TMIN[7]
DSOCMBRAMABUS16outputCELL_N[0].IMUX_BRAM_ADDRA_N3[0], CELL_N[5].OUT_SEC_TMIN[15], CELL_N[7].IMUX_BRAM_ADDRA_N3[0]
DSOCMBRAMABUS17outputCELL_N[0].IMUX_BRAM_ADDRA_N3[1], CELL_N[5].OUT_SEC_TMIN[14], CELL_N[7].IMUX_BRAM_ADDRA_N3[1]
DSOCMBRAMABUS18outputCELL_N[0].IMUX_BRAM_ADDRA_N3[2], CELL_N[5].OUT_SEC_TMIN[13], CELL_N[7].IMUX_BRAM_ADDRA_N3[2]
DSOCMBRAMABUS19outputCELL_N[0].IMUX_BRAM_ADDRA_N3[3], CELL_N[5].OUT_SEC_TMIN[12], CELL_N[7].IMUX_BRAM_ADDRA_N3[3]
DSOCMBRAMABUS20outputCELL_N[0].IMUX_BRAM_ADDRA_N2[0], CELL_N[6].OUT_FAN_TMIN[0], CELL_N[7].IMUX_BRAM_ADDRA_N2[0]
DSOCMBRAMABUS21outputCELL_N[0].IMUX_BRAM_ADDRA_N2[1], CELL_N[6].OUT_FAN_TMIN[1], CELL_N[7].IMUX_BRAM_ADDRA_N2[1]
DSOCMBRAMABUS22outputCELL_N[0].IMUX_BRAM_ADDRA_N2[2], CELL_N[6].OUT_FAN_TMIN[2], CELL_N[7].IMUX_BRAM_ADDRA_N2[2]
DSOCMBRAMABUS23outputCELL_N[0].IMUX_BRAM_ADDRA_N2[3], CELL_N[6].OUT_FAN_TMIN[3], CELL_N[7].IMUX_BRAM_ADDRA_N2[3]
DSOCMBRAMABUS24outputCELL_N[0].IMUX_BRAM_ADDRA_N1[0], CELL_N[6].OUT_FAN_TMIN[4], CELL_N[7].IMUX_BRAM_ADDRA_N1[0]
DSOCMBRAMABUS25outputCELL_N[0].IMUX_BRAM_ADDRA_N1[1], CELL_N[6].OUT_FAN_TMIN[5], CELL_N[7].IMUX_BRAM_ADDRA_N1[1]
DSOCMBRAMABUS26outputCELL_N[0].IMUX_BRAM_ADDRA_N1[2], CELL_N[6].OUT_FAN_TMIN[6], CELL_N[7].IMUX_BRAM_ADDRA_N1[2]
DSOCMBRAMABUS27outputCELL_N[0].IMUX_BRAM_ADDRA_N1[3], CELL_N[6].OUT_FAN_TMIN[7], CELL_N[7].IMUX_BRAM_ADDRA_N1[3]
DSOCMBRAMABUS28outputCELL_N[0].IMUX_BRAM_ADDRA[0], CELL_N[6].OUT_SEC_TMIN[15], CELL_N[7].IMUX_BRAM_ADDRA[0]
DSOCMBRAMABUS29outputCELL_N[0].IMUX_BRAM_ADDRA[1], CELL_N[6].OUT_SEC_TMIN[14], CELL_N[7].IMUX_BRAM_ADDRA[1]
DSOCMBRAMABUS8outputCELL_N[5].OUT_FAN_TMIN[0]
DSOCMBRAMABUS9outputCELL_N[5].OUT_FAN_TMIN[1]
DSOCMBRAMBYTEWRITE0outputCELL_N[0].OUT_FAN_TMIN[0]
DSOCMBRAMBYTEWRITE1outputCELL_N[0].OUT_FAN_TMIN[1]
DSOCMBRAMBYTEWRITE2outputCELL_N[0].OUT_FAN_TMIN[2]
DSOCMBRAMBYTEWRITE3outputCELL_N[0].OUT_FAN_TMIN[3]
DSOCMBRAMENoutputCELL_N[6].OUT_SEC_TMIN[13]
DSOCMBRAMWRDBUS0outputCELL_N[1].OUT_FAN_TMIN[0]
DSOCMBRAMWRDBUS1outputCELL_N[1].OUT_FAN_TMIN[1]
DSOCMBRAMWRDBUS10outputCELL_N[2].OUT_FAN_TMIN[2]
DSOCMBRAMWRDBUS11outputCELL_N[2].OUT_FAN_TMIN[3]
DSOCMBRAMWRDBUS12outputCELL_N[2].OUT_FAN_TMIN[4]
DSOCMBRAMWRDBUS13outputCELL_N[2].OUT_FAN_TMIN[5]
DSOCMBRAMWRDBUS14outputCELL_N[2].OUT_FAN_TMIN[6]
DSOCMBRAMWRDBUS15outputCELL_N[2].OUT_FAN_TMIN[7]
DSOCMBRAMWRDBUS16outputCELL_N[3].OUT_FAN_TMIN[0]
DSOCMBRAMWRDBUS17outputCELL_N[3].OUT_FAN_TMIN[1]
DSOCMBRAMWRDBUS18outputCELL_N[3].OUT_FAN_TMIN[2]
DSOCMBRAMWRDBUS19outputCELL_N[3].OUT_FAN_TMIN[3]
DSOCMBRAMWRDBUS2outputCELL_N[1].OUT_FAN_TMIN[2]
DSOCMBRAMWRDBUS20outputCELL_N[3].OUT_FAN_TMIN[4]
DSOCMBRAMWRDBUS21outputCELL_N[3].OUT_FAN_TMIN[5]
DSOCMBRAMWRDBUS22outputCELL_N[3].OUT_FAN_TMIN[6]
DSOCMBRAMWRDBUS23outputCELL_N[3].OUT_FAN_TMIN[7]
DSOCMBRAMWRDBUS24outputCELL_N[4].OUT_FAN_TMIN[0]
DSOCMBRAMWRDBUS25outputCELL_N[4].OUT_FAN_TMIN[1]
DSOCMBRAMWRDBUS26outputCELL_N[4].OUT_FAN_TMIN[2]
DSOCMBRAMWRDBUS27outputCELL_N[4].OUT_FAN_TMIN[3]
DSOCMBRAMWRDBUS28outputCELL_N[4].OUT_FAN_TMIN[4]
DSOCMBRAMWRDBUS29outputCELL_N[4].OUT_FAN_TMIN[5]
DSOCMBRAMWRDBUS3outputCELL_N[1].OUT_FAN_TMIN[3]
DSOCMBRAMWRDBUS30outputCELL_N[4].OUT_FAN_TMIN[6]
DSOCMBRAMWRDBUS31outputCELL_N[4].OUT_FAN_TMIN[7]
DSOCMBRAMWRDBUS4outputCELL_N[1].OUT_FAN_TMIN[4]
DSOCMBRAMWRDBUS5outputCELL_N[1].OUT_FAN_TMIN[5]
DSOCMBRAMWRDBUS6outputCELL_N[1].OUT_FAN_TMIN[6]
DSOCMBRAMWRDBUS7outputCELL_N[1].OUT_FAN_TMIN[7]
DSOCMBRAMWRDBUS8outputCELL_N[2].OUT_FAN_TMIN[0]
DSOCMBRAMWRDBUS9outputCELL_N[2].OUT_FAN_TMIN[1]
DSOCMBUSYoutputCELL_N[6].OUT_SEC_TMIN[12]
DSOCMRDADDRVALIDoutputCELL_N[4].OUT_SEC_TMIN[13]
EICC405CRITINPUTIRQinputCELL_W[10].IMUX_G0_DATA[2]
EICC405EXTINPUTIRQinputCELL_W[15].IMUX_G0_DATA[2]
ISARCVALUE0inputCELL_S[4].IMUX_TI[0]
ISARCVALUE1inputCELL_S[4].IMUX_TI[1]
ISARCVALUE2inputCELL_S[4].IMUX_TS[0]
ISARCVALUE3inputCELL_S[4].IMUX_TS[1]
ISARCVALUE4inputCELL_S[5].IMUX_TI[0]
ISARCVALUE5inputCELL_S[5].IMUX_TI[1]
ISARCVALUE6inputCELL_S[5].IMUX_TS[0]
ISARCVALUE7inputCELL_S[5].IMUX_TS[1]
ISCNTLVALUE0inputCELL_S[2].IMUX_SR[0]
ISCNTLVALUE1inputCELL_S[2].IMUX_SR[1]
ISCNTLVALUE2inputCELL_S[3].IMUX_SR[0]
ISCNTLVALUE3inputCELL_S[3].IMUX_SR[1]
ISCNTLVALUE4inputCELL_S[5].IMUX_G0_DATA[0]
ISCNTLVALUE5inputCELL_S[5].IMUX_G1_DATA[0]
ISCNTLVALUE6inputCELL_S[2].IMUX_G0_DATA[0]
ISCNTLVALUE7inputCELL_S[2].IMUX_G1_DATA[0]
ISOCMBRAMENoutputCELL_S[2].OUT_SEC_TMIN[13]
ISOCMBRAMEVENWRITEENoutputCELL_S[2].OUT_SEC_TMIN[14]
ISOCMBRAMODDWRITEENoutputCELL_S[2].OUT_SEC_TMIN[15]
ISOCMBRAMRDABUS10outputCELL_S[6].OUT_FAN_TMIN[2]
ISOCMBRAMRDABUS11outputCELL_S[6].OUT_FAN_TMIN[3]
ISOCMBRAMRDABUS12outputCELL_S[6].OUT_FAN_TMIN[4]
ISOCMBRAMRDABUS13outputCELL_S[6].OUT_FAN_TMIN[5]
ISOCMBRAMRDABUS14outputCELL_S[6].OUT_FAN_TMIN[6]
ISOCMBRAMRDABUS15outputCELL_S[0].IMUX_BRAM_ADDRB[0], CELL_S[6].OUT_FAN_TMIN[7], CELL_S[7].IMUX_BRAM_ADDRB[0]
ISOCMBRAMRDABUS16outputCELL_S[0].IMUX_BRAM_ADDRB[1], CELL_S[6].OUT_SEC_TMIN[15], CELL_S[7].IMUX_BRAM_ADDRB[1]
ISOCMBRAMRDABUS17outputCELL_S[0].IMUX_BRAM_ADDRB[2], CELL_S[6].OUT_SEC_TMIN[14], CELL_S[7].IMUX_BRAM_ADDRB[2]
ISOCMBRAMRDABUS18outputCELL_S[0].IMUX_BRAM_ADDRB[3], CELL_S[6].OUT_SEC_TMIN[13], CELL_S[7].IMUX_BRAM_ADDRB[3]
ISOCMBRAMRDABUS19outputCELL_S[0].IMUX_BRAM_ADDRB_S1[0], CELL_S[6].OUT_SEC_TMIN[12], CELL_S[7].IMUX_BRAM_ADDRB_S1[0]
ISOCMBRAMRDABUS20outputCELL_S[0].IMUX_BRAM_ADDRB_S1[1], CELL_S[7].IMUX_BRAM_ADDRB_S1[1], CELL_S[7].OUT_FAN_TMIN[0]
ISOCMBRAMRDABUS21outputCELL_S[0].IMUX_BRAM_ADDRB_S1[2], CELL_S[7].IMUX_BRAM_ADDRB_S1[2], CELL_S[7].OUT_FAN_TMIN[1]
ISOCMBRAMRDABUS22outputCELL_S[0].IMUX_BRAM_ADDRB_S1[3], CELL_S[7].IMUX_BRAM_ADDRB_S1[3], CELL_S[7].OUT_FAN_TMIN[2]
ISOCMBRAMRDABUS23outputCELL_S[0].IMUX_BRAM_ADDRB_S2[0], CELL_S[7].IMUX_BRAM_ADDRB_S2[0], CELL_S[7].OUT_FAN_TMIN[3]
ISOCMBRAMRDABUS24outputCELL_S[0].IMUX_BRAM_ADDRB_S2[1], CELL_S[7].IMUX_BRAM_ADDRB_S2[1], CELL_S[7].OUT_FAN_TMIN[4]
ISOCMBRAMRDABUS25outputCELL_S[0].IMUX_BRAM_ADDRB_S2[2], CELL_S[7].IMUX_BRAM_ADDRB_S2[2], CELL_S[7].OUT_FAN_TMIN[5]
ISOCMBRAMRDABUS26outputCELL_S[0].IMUX_BRAM_ADDRB_S2[3], CELL_S[7].IMUX_BRAM_ADDRB_S2[3], CELL_S[7].OUT_FAN_TMIN[6]
ISOCMBRAMRDABUS27outputCELL_S[0].IMUX_BRAM_ADDRB_S3[0], CELL_S[7].IMUX_BRAM_ADDRB_S3[0], CELL_S[7].OUT_FAN_TMIN[7]
ISOCMBRAMRDABUS28outputCELL_S[0].IMUX_BRAM_ADDRB_S3[1], CELL_S[7].IMUX_BRAM_ADDRB_S3[1], CELL_S[7].OUT_SEC_TMIN[15]
ISOCMBRAMRDABUS8outputCELL_S[6].OUT_FAN_TMIN[0]
ISOCMBRAMRDABUS9outputCELL_S[6].OUT_FAN_TMIN[1]
ISOCMBRAMWRABUS10outputCELL_S[0].OUT_FAN_TMIN[2]
ISOCMBRAMWRABUS11outputCELL_S[0].OUT_FAN_TMIN[3]
ISOCMBRAMWRABUS12outputCELL_S[0].OUT_FAN_TMIN[4]
ISOCMBRAMWRABUS13outputCELL_S[0].OUT_FAN_TMIN[5]
ISOCMBRAMWRABUS14outputCELL_S[0].OUT_FAN_TMIN[6]
ISOCMBRAMWRABUS15outputCELL_S[0].IMUX_BRAM_ADDRA[0], CELL_S[0].OUT_FAN_TMIN[7], CELL_S[7].IMUX_BRAM_ADDRA[0]
ISOCMBRAMWRABUS16outputCELL_S[0].IMUX_BRAM_ADDRA[1], CELL_S[0].OUT_SEC_TMIN[15], CELL_S[7].IMUX_BRAM_ADDRA[1]
ISOCMBRAMWRABUS17outputCELL_S[0].IMUX_BRAM_ADDRA[2], CELL_S[0].OUT_SEC_TMIN[14], CELL_S[7].IMUX_BRAM_ADDRA[2]
ISOCMBRAMWRABUS18outputCELL_S[0].IMUX_BRAM_ADDRA[3], CELL_S[0].OUT_SEC_TMIN[13], CELL_S[7].IMUX_BRAM_ADDRA[3]
ISOCMBRAMWRABUS19outputCELL_S[0].IMUX_BRAM_ADDRA_S1[0], CELL_S[0].OUT_SEC_TMIN[12], CELL_S[7].IMUX_BRAM_ADDRA_S1[0]
ISOCMBRAMWRABUS20outputCELL_S[0].IMUX_BRAM_ADDRA_S1[1], CELL_S[1].OUT_FAN_TMIN[0], CELL_S[7].IMUX_BRAM_ADDRA_S1[1]
ISOCMBRAMWRABUS21outputCELL_S[0].IMUX_BRAM_ADDRA_S1[2], CELL_S[1].OUT_FAN_TMIN[1], CELL_S[7].IMUX_BRAM_ADDRA_S1[2]
ISOCMBRAMWRABUS22outputCELL_S[0].IMUX_BRAM_ADDRA_S1[3], CELL_S[1].OUT_FAN_TMIN[2], CELL_S[7].IMUX_BRAM_ADDRA_S1[3]
ISOCMBRAMWRABUS23outputCELL_S[0].IMUX_BRAM_ADDRA_S2[0], CELL_S[1].OUT_FAN_TMIN[3], CELL_S[7].IMUX_BRAM_ADDRA_S2[0]
ISOCMBRAMWRABUS24outputCELL_S[0].IMUX_BRAM_ADDRA_S2[1], CELL_S[1].OUT_FAN_TMIN[4], CELL_S[7].IMUX_BRAM_ADDRA_S2[1]
ISOCMBRAMWRABUS25outputCELL_S[0].IMUX_BRAM_ADDRA_S2[2], CELL_S[1].OUT_FAN_TMIN[5], CELL_S[7].IMUX_BRAM_ADDRA_S2[2]
ISOCMBRAMWRABUS26outputCELL_S[0].IMUX_BRAM_ADDRA_S2[3], CELL_S[1].OUT_FAN_TMIN[6], CELL_S[7].IMUX_BRAM_ADDRA_S2[3]
ISOCMBRAMWRABUS27outputCELL_S[0].IMUX_BRAM_ADDRA_S3[0], CELL_S[1].OUT_FAN_TMIN[7], CELL_S[7].IMUX_BRAM_ADDRA_S3[0]
ISOCMBRAMWRABUS28outputCELL_S[0].IMUX_BRAM_ADDRA_S3[1], CELL_S[1].OUT_SEC_TMIN[15], CELL_S[7].IMUX_BRAM_ADDRA_S3[1]
ISOCMBRAMWRABUS8outputCELL_S[0].OUT_FAN_TMIN[0]
ISOCMBRAMWRABUS9outputCELL_S[0].OUT_FAN_TMIN[1]
ISOCMBRAMWRDBUS0outputCELL_S[2].OUT_FAN_TMIN[0]
ISOCMBRAMWRDBUS1outputCELL_S[2].OUT_FAN_TMIN[1]
ISOCMBRAMWRDBUS10outputCELL_S[3].OUT_FAN_TMIN[2]
ISOCMBRAMWRDBUS11outputCELL_S[3].OUT_FAN_TMIN[3]
ISOCMBRAMWRDBUS12outputCELL_S[3].OUT_FAN_TMIN[4]
ISOCMBRAMWRDBUS13outputCELL_S[3].OUT_FAN_TMIN[5]
ISOCMBRAMWRDBUS14outputCELL_S[3].OUT_FAN_TMIN[6]
ISOCMBRAMWRDBUS15outputCELL_S[3].OUT_FAN_TMIN[7]
ISOCMBRAMWRDBUS16outputCELL_S[4].OUT_FAN_TMIN[0]
ISOCMBRAMWRDBUS17outputCELL_S[4].OUT_FAN_TMIN[1]
ISOCMBRAMWRDBUS18outputCELL_S[4].OUT_FAN_TMIN[2]
ISOCMBRAMWRDBUS19outputCELL_S[4].OUT_FAN_TMIN[3]
ISOCMBRAMWRDBUS2outputCELL_S[2].OUT_FAN_TMIN[2]
ISOCMBRAMWRDBUS20outputCELL_S[4].OUT_FAN_TMIN[4]
ISOCMBRAMWRDBUS21outputCELL_S[4].OUT_FAN_TMIN[5]
ISOCMBRAMWRDBUS22outputCELL_S[4].OUT_FAN_TMIN[6]
ISOCMBRAMWRDBUS23outputCELL_S[4].OUT_FAN_TMIN[7]
ISOCMBRAMWRDBUS24outputCELL_S[5].OUT_FAN_TMIN[0]
ISOCMBRAMWRDBUS25outputCELL_S[5].OUT_FAN_TMIN[1]
ISOCMBRAMWRDBUS26outputCELL_S[5].OUT_FAN_TMIN[2]
ISOCMBRAMWRDBUS27outputCELL_S[5].OUT_FAN_TMIN[3]
ISOCMBRAMWRDBUS28outputCELL_S[5].OUT_FAN_TMIN[4]
ISOCMBRAMWRDBUS29outputCELL_S[5].OUT_FAN_TMIN[5]
ISOCMBRAMWRDBUS3outputCELL_S[2].OUT_FAN_TMIN[3]
ISOCMBRAMWRDBUS30outputCELL_S[5].OUT_FAN_TMIN[6]
ISOCMBRAMWRDBUS31outputCELL_S[5].OUT_FAN_TMIN[7]
ISOCMBRAMWRDBUS4outputCELL_S[2].OUT_FAN_TMIN[4]
ISOCMBRAMWRDBUS5outputCELL_S[2].OUT_FAN_TMIN[5]
ISOCMBRAMWRDBUS6outputCELL_S[2].OUT_FAN_TMIN[6]
ISOCMBRAMWRDBUS7outputCELL_S[2].OUT_FAN_TMIN[7]
ISOCMBRAMWRDBUS8outputCELL_S[3].OUT_FAN_TMIN[0]
ISOCMBRAMWRDBUS9outputCELL_S[3].OUT_FAN_TMIN[1]
ISOCMRDADDRVALIDoutputCELL_S[1].OUT_SEC_TMIN[14]
JTGC405BNDSCANTDOinputCELL_N[2].IMUX_G1_DATA[0]
JTGC405TCKinputCELL_N[1].IMUX_CLK[0]
JTGC405TDIinputCELL_N[1].IMUX_G1_DATA[0]
JTGC405TMSinputCELL_N[1].IMUX_G2_DATA[0]
JTGC405TRSTNEGinputCELL_W[12].IMUX_G2_DATA[2]
LSSDC405ACLKinputCELL_S[7].IMUX_G1_DATA[5]
LSSDC405ARRAYCCLKNEGinputCELL_S[0].IMUX_G2_DATA[5]
LSSDC405BCLKinputCELL_S[0].IMUX_G3_DATA[5]
LSSDC405BISTCCLKinputCELL_S[1].IMUX_G2_DATA[5]
LSSDC405CNTLPOINTinputCELL_S[1].IMUX_G3_DATA[5]
LSSDC405SCANGATEinputCELL_S[2].IMUX_G0_DATA[2]
LSSDC405SCANIN0inputCELL_S[4].IMUX_G3_DATA[1]
LSSDC405SCANIN1inputCELL_S[4].IMUX_G0_DATA[2]
LSSDC405SCANIN2inputCELL_S[5].IMUX_G0_DATA[2]
LSSDC405SCANIN3inputCELL_S[5].IMUX_G1_DATA[2]
LSSDC405SCANIN4inputCELL_S[6].IMUX_G2_DATA[5]
LSSDC405SCANIN5inputCELL_S[6].IMUX_G3_DATA[5]
LSSDC405SCANIN6inputCELL_S[7].IMUX_G2_DATA[5]
LSSDC405SCANIN7inputCELL_S[7].IMUX_G3_DATA[5]
LSSDC405SCANIN8inputCELL_S[0].IMUX_G0_DATA[6]
LSSDC405SCANIN9inputCELL_S[0].IMUX_G1_DATA[6]
LSSDC405TESTEVSinputCELL_S[2].IMUX_G1_DATA[2]
LSSDC405TESTM1inputCELL_S[3].IMUX_G2_DATA[1]
LSSDC405TESTM3inputCELL_S[3].IMUX_G3_DATA[1]
MCBCPUCLKENinputCELL_W[4].IMUX_TI[0]
MCBJTAGENinputCELL_W[5].IMUX_TI[0]
MCBTIMERENinputCELL_W[6].IMUX_TI[0]
MCPPCRSTinputCELL_W[14].IMUX_TI[0]
PLBC405DCUADDRACKinputCELL_W[7].IMUX_G0_DATA[2]
PLBC405DCUBUSYinputCELL_W[7].IMUX_G2_DATA[2]
PLBC405DCUERRinputCELL_W[7].IMUX_G3_DATA[2]
PLBC405DCURDDACKinputCELL_W[6].IMUX_G3_DATA[2]
PLBC405DCURDDBUS0inputCELL_W[15].IMUX_G0_DATA[0]
PLBC405DCURDDBUS1inputCELL_W[15].IMUX_G1_DATA[0]
PLBC405DCURDDBUS10inputCELL_W[13].IMUX_G2_DATA[0]
PLBC405DCURDDBUS11inputCELL_W[13].IMUX_G3_DATA[0]
PLBC405DCURDDBUS12inputCELL_W[12].IMUX_G0_DATA[0]
PLBC405DCURDDBUS13inputCELL_W[12].IMUX_G1_DATA[0]
PLBC405DCURDDBUS14inputCELL_W[12].IMUX_G2_DATA[0]
PLBC405DCURDDBUS15inputCELL_W[12].IMUX_G3_DATA[0]
PLBC405DCURDDBUS16inputCELL_W[11].IMUX_G0_DATA[0]
PLBC405DCURDDBUS17inputCELL_W[11].IMUX_G1_DATA[0]
PLBC405DCURDDBUS18inputCELL_W[11].IMUX_G2_DATA[0]
PLBC405DCURDDBUS19inputCELL_W[11].IMUX_G3_DATA[0]
PLBC405DCURDDBUS2inputCELL_W[15].IMUX_G2_DATA[0]
PLBC405DCURDDBUS20inputCELL_W[10].IMUX_G0_DATA[0]
PLBC405DCURDDBUS21inputCELL_W[10].IMUX_G1_DATA[0]
PLBC405DCURDDBUS22inputCELL_W[10].IMUX_G2_DATA[0]
PLBC405DCURDDBUS23inputCELL_W[10].IMUX_G3_DATA[0]
PLBC405DCURDDBUS24inputCELL_W[9].IMUX_G0_DATA[0]
PLBC405DCURDDBUS25inputCELL_W[9].IMUX_G1_DATA[0]
PLBC405DCURDDBUS26inputCELL_W[9].IMUX_G2_DATA[0]
PLBC405DCURDDBUS27inputCELL_W[9].IMUX_G3_DATA[0]
PLBC405DCURDDBUS28inputCELL_W[8].IMUX_G0_DATA[0]
PLBC405DCURDDBUS29inputCELL_W[8].IMUX_G1_DATA[0]
PLBC405DCURDDBUS3inputCELL_W[15].IMUX_G3_DATA[0]
PLBC405DCURDDBUS30inputCELL_W[8].IMUX_G2_DATA[0]
PLBC405DCURDDBUS31inputCELL_W[8].IMUX_G3_DATA[0]
PLBC405DCURDDBUS32inputCELL_W[7].IMUX_G0_DATA[0]
PLBC405DCURDDBUS33inputCELL_W[7].IMUX_G1_DATA[0]
PLBC405DCURDDBUS34inputCELL_W[7].IMUX_G2_DATA[0]
PLBC405DCURDDBUS35inputCELL_W[7].IMUX_G3_DATA[0]
PLBC405DCURDDBUS36inputCELL_W[6].IMUX_G0_DATA[0]
PLBC405DCURDDBUS37inputCELL_W[6].IMUX_G1_DATA[0]
PLBC405DCURDDBUS38inputCELL_W[6].IMUX_G2_DATA[0]
PLBC405DCURDDBUS39inputCELL_W[6].IMUX_G3_DATA[0]
PLBC405DCURDDBUS4inputCELL_W[14].IMUX_G0_DATA[0]
PLBC405DCURDDBUS40inputCELL_W[5].IMUX_G0_DATA[0]
PLBC405DCURDDBUS41inputCELL_W[5].IMUX_G1_DATA[0]
PLBC405DCURDDBUS42inputCELL_W[5].IMUX_G2_DATA[0]
PLBC405DCURDDBUS43inputCELL_W[5].IMUX_G3_DATA[0]
PLBC405DCURDDBUS44inputCELL_W[4].IMUX_G0_DATA[0]
PLBC405DCURDDBUS45inputCELL_W[4].IMUX_G1_DATA[0]
PLBC405DCURDDBUS46inputCELL_W[4].IMUX_G2_DATA[0]
PLBC405DCURDDBUS47inputCELL_W[4].IMUX_G3_DATA[0]
PLBC405DCURDDBUS48inputCELL_W[3].IMUX_G0_DATA[0]
PLBC405DCURDDBUS49inputCELL_W[3].IMUX_G1_DATA[0]
PLBC405DCURDDBUS5inputCELL_W[14].IMUX_G1_DATA[0]
PLBC405DCURDDBUS50inputCELL_W[3].IMUX_G2_DATA[0]
PLBC405DCURDDBUS51inputCELL_W[3].IMUX_G3_DATA[0]
PLBC405DCURDDBUS52inputCELL_W[2].IMUX_G0_DATA[0]
PLBC405DCURDDBUS53inputCELL_W[2].IMUX_G1_DATA[0]
PLBC405DCURDDBUS54inputCELL_W[2].IMUX_G2_DATA[0]
PLBC405DCURDDBUS55inputCELL_W[2].IMUX_G3_DATA[0]
PLBC405DCURDDBUS56inputCELL_W[1].IMUX_G0_DATA[0]
PLBC405DCURDDBUS57inputCELL_W[1].IMUX_G1_DATA[0]
PLBC405DCURDDBUS58inputCELL_W[1].IMUX_G2_DATA[0]
PLBC405DCURDDBUS59inputCELL_W[1].IMUX_G3_DATA[0]
PLBC405DCURDDBUS6inputCELL_W[14].IMUX_G2_DATA[0]
PLBC405DCURDDBUS60inputCELL_W[0].IMUX_G0_DATA[0]
PLBC405DCURDDBUS61inputCELL_W[0].IMUX_G1_DATA[0]
PLBC405DCURDDBUS62inputCELL_W[0].IMUX_G2_DATA[0]
PLBC405DCURDDBUS63inputCELL_W[0].IMUX_G3_DATA[0]
PLBC405DCURDDBUS7inputCELL_W[14].IMUX_G3_DATA[0]
PLBC405DCURDDBUS8inputCELL_W[13].IMUX_G0_DATA[0]
PLBC405DCURDDBUS9inputCELL_W[13].IMUX_G1_DATA[0]
PLBC405DCURDWDADDR1inputCELL_W[6].IMUX_G0_DATA[2]
PLBC405DCURDWDADDR2inputCELL_W[6].IMUX_G1_DATA[2]
PLBC405DCURDWDADDR3inputCELL_W[6].IMUX_G2_DATA[2]
PLBC405DCUSSIZE1inputCELL_W[7].IMUX_G1_DATA[2]
PLBC405DCUWRDACKinputCELL_W[5].IMUX_G0_DATA[2]
PLBC405ICUADDRACKinputCELL_W[8].IMUX_G0_DATA[2]
PLBC405ICUBUSYinputCELL_W[8].IMUX_G2_DATA[2]
PLBC405ICUERRinputCELL_W[8].IMUX_G3_DATA[2]
PLBC405ICURDDACKinputCELL_W[9].IMUX_G3_DATA[2]
PLBC405ICURDDBUS0inputCELL_W[15].IMUX_G0_DATA[1]
PLBC405ICURDDBUS1inputCELL_W[15].IMUX_G1_DATA[1]
PLBC405ICURDDBUS10inputCELL_W[13].IMUX_G2_DATA[1]
PLBC405ICURDDBUS11inputCELL_W[13].IMUX_G3_DATA[1]
PLBC405ICURDDBUS12inputCELL_W[12].IMUX_G0_DATA[1]
PLBC405ICURDDBUS13inputCELL_W[12].IMUX_G1_DATA[1]
PLBC405ICURDDBUS14inputCELL_W[12].IMUX_G2_DATA[1]
PLBC405ICURDDBUS15inputCELL_W[12].IMUX_G3_DATA[1]
PLBC405ICURDDBUS16inputCELL_W[11].IMUX_G0_DATA[1]
PLBC405ICURDDBUS17inputCELL_W[11].IMUX_G1_DATA[1]
PLBC405ICURDDBUS18inputCELL_W[11].IMUX_G2_DATA[1]
PLBC405ICURDDBUS19inputCELL_W[11].IMUX_G3_DATA[1]
PLBC405ICURDDBUS2inputCELL_W[15].IMUX_G2_DATA[1]
PLBC405ICURDDBUS20inputCELL_W[10].IMUX_G0_DATA[1]
PLBC405ICURDDBUS21inputCELL_W[10].IMUX_G1_DATA[1]
PLBC405ICURDDBUS22inputCELL_W[10].IMUX_G2_DATA[1]
PLBC405ICURDDBUS23inputCELL_W[10].IMUX_G3_DATA[1]
PLBC405ICURDDBUS24inputCELL_W[9].IMUX_G0_DATA[1]
PLBC405ICURDDBUS25inputCELL_W[9].IMUX_G1_DATA[1]
PLBC405ICURDDBUS26inputCELL_W[9].IMUX_G2_DATA[1]
PLBC405ICURDDBUS27inputCELL_W[9].IMUX_G3_DATA[1]
PLBC405ICURDDBUS28inputCELL_W[8].IMUX_G0_DATA[1]
PLBC405ICURDDBUS29inputCELL_W[8].IMUX_G1_DATA[1]
PLBC405ICURDDBUS3inputCELL_W[15].IMUX_G3_DATA[1]
PLBC405ICURDDBUS30inputCELL_W[8].IMUX_G2_DATA[1]
PLBC405ICURDDBUS31inputCELL_W[8].IMUX_G3_DATA[1]
PLBC405ICURDDBUS32inputCELL_W[7].IMUX_G0_DATA[1]
PLBC405ICURDDBUS33inputCELL_W[7].IMUX_G1_DATA[1]
PLBC405ICURDDBUS34inputCELL_W[7].IMUX_G2_DATA[1]
PLBC405ICURDDBUS35inputCELL_W[7].IMUX_G3_DATA[1]
PLBC405ICURDDBUS36inputCELL_W[6].IMUX_G0_DATA[1]
PLBC405ICURDDBUS37inputCELL_W[6].IMUX_G1_DATA[1]
PLBC405ICURDDBUS38inputCELL_W[6].IMUX_G2_DATA[1]
PLBC405ICURDDBUS39inputCELL_W[6].IMUX_G3_DATA[1]
PLBC405ICURDDBUS4inputCELL_W[14].IMUX_G0_DATA[1]
PLBC405ICURDDBUS40inputCELL_W[5].IMUX_G0_DATA[1]
PLBC405ICURDDBUS41inputCELL_W[5].IMUX_G1_DATA[1]
PLBC405ICURDDBUS42inputCELL_W[5].IMUX_G2_DATA[1]
PLBC405ICURDDBUS43inputCELL_W[5].IMUX_G3_DATA[1]
PLBC405ICURDDBUS44inputCELL_W[4].IMUX_G0_DATA[1]
PLBC405ICURDDBUS45inputCELL_W[4].IMUX_G1_DATA[1]
PLBC405ICURDDBUS46inputCELL_W[4].IMUX_G2_DATA[1]
PLBC405ICURDDBUS47inputCELL_W[4].IMUX_G3_DATA[1]
PLBC405ICURDDBUS48inputCELL_W[3].IMUX_G0_DATA[1]
PLBC405ICURDDBUS49inputCELL_W[3].IMUX_G1_DATA[1]
PLBC405ICURDDBUS5inputCELL_W[14].IMUX_G1_DATA[1]
PLBC405ICURDDBUS50inputCELL_W[3].IMUX_G2_DATA[1]
PLBC405ICURDDBUS51inputCELL_W[3].IMUX_G3_DATA[1]
PLBC405ICURDDBUS52inputCELL_W[2].IMUX_G0_DATA[1]
PLBC405ICURDDBUS53inputCELL_W[2].IMUX_G1_DATA[1]
PLBC405ICURDDBUS54inputCELL_W[2].IMUX_G2_DATA[1]
PLBC405ICURDDBUS55inputCELL_W[2].IMUX_G3_DATA[1]
PLBC405ICURDDBUS56inputCELL_W[1].IMUX_G0_DATA[1]
PLBC405ICURDDBUS57inputCELL_W[1].IMUX_G1_DATA[1]
PLBC405ICURDDBUS58inputCELL_W[1].IMUX_G2_DATA[1]
PLBC405ICURDDBUS59inputCELL_W[1].IMUX_G3_DATA[1]
PLBC405ICURDDBUS6inputCELL_W[14].IMUX_G2_DATA[1]
PLBC405ICURDDBUS60inputCELL_W[0].IMUX_G0_DATA[1]
PLBC405ICURDDBUS61inputCELL_W[0].IMUX_G1_DATA[1]
PLBC405ICURDDBUS62inputCELL_W[0].IMUX_G2_DATA[1]
PLBC405ICURDDBUS63inputCELL_W[0].IMUX_G3_DATA[1]
PLBC405ICURDDBUS7inputCELL_W[14].IMUX_G3_DATA[1]
PLBC405ICURDDBUS8inputCELL_W[13].IMUX_G0_DATA[1]
PLBC405ICURDDBUS9inputCELL_W[13].IMUX_G1_DATA[1]
PLBC405ICURDWDADDR1inputCELL_W[9].IMUX_G0_DATA[2]
PLBC405ICURDWDADDR2inputCELL_W[9].IMUX_G1_DATA[2]
PLBC405ICURDWDADDR3inputCELL_W[9].IMUX_G2_DATA[2]
PLBC405ICUSSIZE1inputCELL_W[8].IMUX_G1_DATA[2]
PLBCLKinputCELL_W[0].IMUX_CLK[1]
RSTC405RESETCHIPinputCELL_W[11].IMUX_SR[0]
RSTC405RESETCOREinputCELL_W[12].IMUX_SR[0]
RSTC405RESETSYSinputCELL_W[13].IMUX_SR[0]
TESTSELIinputCELL_E[8].IMUX_TI[0]
TIEC405APUDIVENinputCELL_E[4].IMUX_TI[0]
TIEC405APUPRESENTinputCELL_E[4].IMUX_TI[1]
TIEC405DETERMINISTICMULTinputCELL_W[0].IMUX_TI[0]
TIEC405DISOPERANDFWDinputCELL_W[1].IMUX_TI[0]
TIEC405MMUENinputCELL_W[1].IMUX_TI[1]
TIEC405PVR0inputCELL_W[15].IMUX_TI[0]
TIEC405PVR1inputCELL_W[15].IMUX_TI[1]
TIEC405PVR10inputCELL_W[12].IMUX_TI[1]
TIEC405PVR11inputCELL_W[12].IMUX_TS[0]
TIEC405PVR12inputCELL_W[11].IMUX_TI[0]
TIEC405PVR13inputCELL_W[11].IMUX_TI[1]
TIEC405PVR14inputCELL_W[11].IMUX_TS[0]
TIEC405PVR15inputCELL_W[10].IMUX_TI[0]
TIEC405PVR16inputCELL_W[10].IMUX_TI[1]
TIEC405PVR17inputCELL_W[10].IMUX_TS[0]
TIEC405PVR18inputCELL_W[5].IMUX_TI[1]
TIEC405PVR19inputCELL_W[5].IMUX_TS[0]
TIEC405PVR2inputCELL_W[15].IMUX_TS[0]
TIEC405PVR20inputCELL_W[4].IMUX_TI[1]
TIEC405PVR21inputCELL_W[4].IMUX_TS[0]
TIEC405PVR22inputCELL_W[4].IMUX_TS[1]
TIEC405PVR23inputCELL_W[3].IMUX_TI[0]
TIEC405PVR24inputCELL_W[3].IMUX_TI[1]
TIEC405PVR25inputCELL_W[3].IMUX_TS[0]
TIEC405PVR26inputCELL_W[2].IMUX_TI[0]
TIEC405PVR27inputCELL_W[2].IMUX_TI[1]
TIEC405PVR28inputCELL_W[2].IMUX_TS[0]
TIEC405PVR29inputCELL_W[1].IMUX_TS[0]
TIEC405PVR3inputCELL_W[14].IMUX_TI[1]
TIEC405PVR30inputCELL_W[0].IMUX_TI[1]
TIEC405PVR31inputCELL_W[0].IMUX_TS[0]
TIEC405PVR4inputCELL_W[14].IMUX_TS[0]
TIEC405PVR5inputCELL_W[14].IMUX_TS[1]
TIEC405PVR6inputCELL_W[13].IMUX_TI[0]
TIEC405PVR7inputCELL_W[13].IMUX_TI[1]
TIEC405PVR8inputCELL_W[13].IMUX_TS[0]
TIEC405PVR9inputCELL_W[12].IMUX_TI[0]
TIEDSOCMDCRADDR0inputCELL_N[2].IMUX_TI[0]
TIEDSOCMDCRADDR1inputCELL_N[3].IMUX_TI[0]
TIEDSOCMDCRADDR2inputCELL_N[3].IMUX_TI[1]
TIEDSOCMDCRADDR3inputCELL_N[3].IMUX_TS[0]
TIEDSOCMDCRADDR4inputCELL_N[3].IMUX_TS[1]
TIEDSOCMDCRADDR5inputCELL_N[4].IMUX_TI[0]
TIEDSOCMDCRADDR6inputCELL_N[4].IMUX_TI[1]
TIEDSOCMDCRADDR7inputCELL_N[4].IMUX_TS[0]
TIEISOCMDCRADDR0inputCELL_S[2].IMUX_TI[0]
TIEISOCMDCRADDR1inputCELL_S[2].IMUX_TI[1]
TIEISOCMDCRADDR2inputCELL_S[2].IMUX_TS[0]
TIEISOCMDCRADDR3inputCELL_S[2].IMUX_TS[1]
TIEISOCMDCRADDR4inputCELL_S[3].IMUX_TI[0]
TIEISOCMDCRADDR5inputCELL_S[3].IMUX_TI[1]
TIEISOCMDCRADDR6inputCELL_S[3].IMUX_TS[0]
TIEISOCMDCRADDR7inputCELL_S[3].IMUX_TS[1]
TIERAMTAP1inputCELL_E[6].IMUX_TI[0]
TIERAMTAP2inputCELL_E[6].IMUX_TI[1]
TIETAGTAP1inputCELL_E[7].IMUX_TI[0]
TIETAGTAP2inputCELL_E[7].IMUX_TI[1]
TIEUTLBTAP1inputCELL_E[5].IMUX_TI[0]
TIEUTLBTAP2inputCELL_E[5].IMUX_TI[1]
TRCC405TRACEDISABLEinputCELL_N[1].IMUX_G0_DATA[0]
TRCC405TRIGGEREVENTINinputCELL_N[2].IMUX_G0_DATA[0]
TSTC405DCRABUSI0inputCELL_E[0].IMUX_G0_DATA[3]
TSTC405DCRABUSI1inputCELL_E[0].IMUX_G1_DATA[3]
TSTC405DCRABUSI2inputCELL_E[1].IMUX_G0_DATA[3]
TSTC405DCRABUSI3inputCELL_E[1].IMUX_G1_DATA[3]
TSTC405DCRABUSI4inputCELL_E[2].IMUX_G0_DATA[3]
TSTC405DCRABUSI5inputCELL_E[2].IMUX_G1_DATA[3]
TSTC405DCRABUSI6inputCELL_E[3].IMUX_G0_DATA[3]
TSTC405DCRABUSI7inputCELL_E[3].IMUX_G1_DATA[3]
TSTC405DCRABUSI8inputCELL_E[4].IMUX_G2_DATA[2]
TSTC405DCRABUSI9inputCELL_E[4].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI0inputCELL_E[5].IMUX_G2_DATA[2]
TSTC405DCRDBUSOUTI1inputCELL_E[5].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI10inputCELL_E[10].IMUX_G0_DATA[3]
TSTC405DCRDBUSOUTI11inputCELL_E[11].IMUX_G2_DATA[2]
TSTC405DCRDBUSOUTI12inputCELL_E[11].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI13inputCELL_E[12].IMUX_G2_DATA[2]
TSTC405DCRDBUSOUTI14inputCELL_E[12].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI15inputCELL_E[13].IMUX_G2_DATA[2]
TSTC405DCRDBUSOUTI16inputCELL_E[13].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI17inputCELL_E[14].IMUX_G2_DATA[2]
TSTC405DCRDBUSOUTI18inputCELL_E[14].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI19inputCELL_E[15].IMUX_G2_DATA[2]
TSTC405DCRDBUSOUTI2inputCELL_E[6].IMUX_G2_DATA[2]
TSTC405DCRDBUSOUTI20inputCELL_E[15].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI21inputCELL_E[0].IMUX_G2_DATA[3]
TSTC405DCRDBUSOUTI22inputCELL_E[0].IMUX_G3_DATA[3]
TSTC405DCRDBUSOUTI23inputCELL_E[1].IMUX_G2_DATA[3]
TSTC405DCRDBUSOUTI24inputCELL_E[1].IMUX_G3_DATA[3]
TSTC405DCRDBUSOUTI25inputCELL_E[2].IMUX_G2_DATA[3]
TSTC405DCRDBUSOUTI26inputCELL_E[2].IMUX_G3_DATA[3]
TSTC405DCRDBUSOUTI27inputCELL_E[3].IMUX_G2_DATA[3]
TSTC405DCRDBUSOUTI28inputCELL_E[3].IMUX_G3_DATA[3]
TSTC405DCRDBUSOUTI29inputCELL_E[4].IMUX_G0_DATA[3]
TSTC405DCRDBUSOUTI3inputCELL_E[6].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI30inputCELL_E[4].IMUX_G1_DATA[3]
TSTC405DCRDBUSOUTI31inputCELL_E[5].IMUX_G0_DATA[3]
TSTC405DCRDBUSOUTI4inputCELL_E[7].IMUX_G2_DATA[2]
TSTC405DCRDBUSOUTI5inputCELL_E[7].IMUX_G3_DATA[2]
TSTC405DCRDBUSOUTI6inputCELL_E[8].IMUX_G0_DATA[3]
TSTC405DCRDBUSOUTI7inputCELL_E[9].IMUX_G0_DATA[3]
TSTC405DCRDBUSOUTI8inputCELL_E[9].IMUX_G1_DATA[3]
TSTC405DCRDBUSOUTI9inputCELL_E[10].IMUX_G3_DATA[2]
TSTC405DCRREADIinputCELL_E[5].IMUX_G1_DATA[3]
TSTC405DCRWRITEIinputCELL_E[6].IMUX_G0_DATA[3]
TSTCLKINACTIinputCELL_W[1].IMUX_G1_DATA[2]
TSTCLKINACTOoutputCELL_W[1].OUT_TEST[0]
TSTCPUCLKENIinputCELL_W[14].IMUX_G0_DATA[2]
TSTCPUCLKENOoutputCELL_W[1].OUT_SEC_TMIN[9]
TSTCPUCLKIinputCELL_W[0].IMUX_G1_DATA[2]
TSTCPUCLKOoutputCELL_W[1].OUT_SEC_TMIN[8]
TSTDCRACKIinputCELL_E[8].IMUX_G3_DATA[1]
TSTDCRACKOoutputCELL_E[0].OUT_SEC_TMIN[10]
TSTDCRBUSI0inputCELL_E[9].IMUX_G2_DATA[1]
TSTDCRBUSI1inputCELL_E[9].IMUX_G3_DATA[1]
TSTDCRBUSI10inputCELL_E[14].IMUX_G2_DATA[1]
TSTDCRBUSI11inputCELL_E[14].IMUX_G3_DATA[1]
TSTDCRBUSI12inputCELL_E[15].IMUX_G2_DATA[1]
TSTDCRBUSI13inputCELL_E[15].IMUX_G3_DATA[1]
TSTDCRBUSI14inputCELL_E[0].IMUX_G0_DATA[2]
TSTDCRBUSI15inputCELL_E[0].IMUX_G1_DATA[2]
TSTDCRBUSI16inputCELL_E[1].IMUX_G0_DATA[2]
TSTDCRBUSI17inputCELL_E[1].IMUX_G1_DATA[2]
TSTDCRBUSI18inputCELL_E[2].IMUX_G0_DATA[2]
TSTDCRBUSI19inputCELL_E[2].IMUX_G1_DATA[2]
TSTDCRBUSI2inputCELL_E[10].IMUX_G2_DATA[1]
TSTDCRBUSI20inputCELL_E[3].IMUX_G0_DATA[2]
TSTDCRBUSI21inputCELL_E[3].IMUX_G1_DATA[2]
TSTDCRBUSI22inputCELL_E[4].IMUX_G2_DATA[1]
TSTDCRBUSI23inputCELL_E[4].IMUX_G3_DATA[1]
TSTDCRBUSI24inputCELL_E[5].IMUX_G2_DATA[1]
TSTDCRBUSI25inputCELL_E[5].IMUX_G3_DATA[1]
TSTDCRBUSI26inputCELL_E[6].IMUX_G2_DATA[1]
TSTDCRBUSI27inputCELL_E[6].IMUX_G3_DATA[1]
TSTDCRBUSI28inputCELL_E[7].IMUX_G2_DATA[1]
TSTDCRBUSI29inputCELL_E[7].IMUX_G3_DATA[1]
TSTDCRBUSI3inputCELL_E[10].IMUX_G3_DATA[1]
TSTDCRBUSI30inputCELL_E[8].IMUX_G0_DATA[2]
TSTDCRBUSI31inputCELL_E[8].IMUX_G1_DATA[2]
TSTDCRBUSI4inputCELL_E[11].IMUX_G2_DATA[1]
TSTDCRBUSI5inputCELL_E[11].IMUX_G3_DATA[1]
TSTDCRBUSI6inputCELL_E[12].IMUX_G2_DATA[1]
TSTDCRBUSI7inputCELL_E[12].IMUX_G3_DATA[1]
TSTDCRBUSI8inputCELL_E[13].IMUX_G2_DATA[1]
TSTDCRBUSI9inputCELL_E[13].IMUX_G3_DATA[1]
TSTDCRBUSO0outputCELL_E[0].OUT_SEC_TMIN[9]
TSTDCRBUSO1outputCELL_E[0].OUT_SEC_TMIN[8]
TSTDCRBUSO10outputCELL_E[2].OUT_TEST[0]
TSTDCRBUSO11outputCELL_E[3].OUT_SEC_TMIN[10]
TSTDCRBUSO12outputCELL_E[3].OUT_SEC_TMIN[9]
TSTDCRBUSO13outputCELL_E[3].OUT_SEC_TMIN[8]
TSTDCRBUSO14outputCELL_E[3].OUT_TEST[0]
TSTDCRBUSO15outputCELL_E[4].OUT_SEC_TMIN[10]
TSTDCRBUSO16outputCELL_E[4].OUT_SEC_TMIN[9]
TSTDCRBUSO17outputCELL_E[4].OUT_SEC_TMIN[8]
TSTDCRBUSO18outputCELL_E[4].OUT_TEST[0]
TSTDCRBUSO19outputCELL_E[5].OUT_SEC_TMIN[10]
TSTDCRBUSO2outputCELL_E[0].OUT_TEST[0]
TSTDCRBUSO20outputCELL_E[5].OUT_SEC_TMIN[9]
TSTDCRBUSO21outputCELL_E[5].OUT_SEC_TMIN[8]
TSTDCRBUSO22outputCELL_E[5].OUT_TEST[0]
TSTDCRBUSO23outputCELL_E[6].OUT_SEC_TMIN[10]
TSTDCRBUSO24outputCELL_E[6].OUT_SEC_TMIN[9]
TSTDCRBUSO25outputCELL_E[6].OUT_SEC_TMIN[8]
TSTDCRBUSO26outputCELL_E[6].OUT_TEST[0]
TSTDCRBUSO27outputCELL_E[7].OUT_SEC_TMIN[10]
TSTDCRBUSO28outputCELL_E[7].OUT_SEC_TMIN[9]
TSTDCRBUSO29outputCELL_E[7].OUT_SEC_TMIN[8]
TSTDCRBUSO3outputCELL_E[1].OUT_SEC_TMIN[10]
TSTDCRBUSO30outputCELL_E[7].OUT_TEST[0]
TSTDCRBUSO31outputCELL_E[8].OUT_SEC_TMIN[10]
TSTDCRBUSO4outputCELL_E[1].OUT_SEC_TMIN[9]
TSTDCRBUSO5outputCELL_E[1].OUT_SEC_TMIN[8]
TSTDCRBUSO6outputCELL_E[1].OUT_TEST[0]
TSTDCRBUSO7outputCELL_E[2].OUT_SEC_TMIN[10]
TSTDCRBUSO8outputCELL_E[2].OUT_SEC_TMIN[9]
TSTDCRBUSO9outputCELL_E[2].OUT_SEC_TMIN[8]
TSTDSOCMABORTOPIinputCELL_E[11].IMUX_G0_DATA[3]
TSTDSOCMABORTOPOoutputCELL_E[13].OUT_SEC_TMIN[12]
TSTDSOCMABORTREQIinputCELL_E[11].IMUX_G1_DATA[3]
TSTDSOCMABORTREQOoutputCELL_E[14].OUT_SEC_TMIN[12]
TSTDSOCMABUSI0inputCELL_E[12].IMUX_G0_DATA[3]
TSTDSOCMABUSI1inputCELL_E[12].IMUX_G1_DATA[3]
TSTDSOCMABUSI10inputCELL_E[1].IMUX_G0_DATA[4]
TSTDSOCMABUSI11inputCELL_E[1].IMUX_G1_DATA[4]
TSTDSOCMABUSI12inputCELL_E[2].IMUX_G0_DATA[4]
TSTDSOCMABUSI13inputCELL_E[2].IMUX_G1_DATA[4]
TSTDSOCMABUSI14inputCELL_E[3].IMUX_G0_DATA[4]
TSTDSOCMABUSI15inputCELL_E[3].IMUX_G1_DATA[4]
TSTDSOCMABUSI16inputCELL_E[4].IMUX_G2_DATA[3]
TSTDSOCMABUSI17inputCELL_E[4].IMUX_G3_DATA[3]
TSTDSOCMABUSI18inputCELL_E[5].IMUX_G2_DATA[3]
TSTDSOCMABUSI19inputCELL_E[5].IMUX_G3_DATA[3]
TSTDSOCMABUSI2inputCELL_E[13].IMUX_G0_DATA[3]
TSTDSOCMABUSI20inputCELL_E[6].IMUX_G2_DATA[3]
TSTDSOCMABUSI21inputCELL_E[6].IMUX_G3_DATA[3]
TSTDSOCMABUSI22inputCELL_E[7].IMUX_G2_DATA[3]
TSTDSOCMABUSI23inputCELL_E[7].IMUX_G3_DATA[3]
TSTDSOCMABUSI24inputCELL_E[8].IMUX_G3_DATA[3]
TSTDSOCMABUSI25inputCELL_E[8].IMUX_G0_DATA[4]
TSTDSOCMABUSI26inputCELL_E[9].IMUX_G0_DATA[4]
TSTDSOCMABUSI27inputCELL_E[9].IMUX_G1_DATA[4]
TSTDSOCMABUSI28inputCELL_E[10].IMUX_G3_DATA[3]
TSTDSOCMABUSI29inputCELL_E[10].IMUX_G0_DATA[4]
TSTDSOCMABUSI3inputCELL_E[13].IMUX_G1_DATA[3]
TSTDSOCMABUSI4inputCELL_E[14].IMUX_G0_DATA[3]
TSTDSOCMABUSI5inputCELL_E[14].IMUX_G1_DATA[3]
TSTDSOCMABUSI6inputCELL_E[15].IMUX_G0_DATA[3]
TSTDSOCMABUSI7inputCELL_E[15].IMUX_G1_DATA[3]
TSTDSOCMABUSI8inputCELL_E[0].IMUX_G0_DATA[4]
TSTDSOCMABUSI9inputCELL_E[0].IMUX_G1_DATA[4]
TSTDSOCMABUSO0outputCELL_N[1].OUT_SEC_TMIN[12]
TSTDSOCMABUSO1outputCELL_N[2].OUT_SEC_TMIN[12]
TSTDSOCMABUSO10outputCELL_N[6].OUT_SEC_TMIN[10]
TSTDSOCMABUSO11outputCELL_N[6].OUT_SEC_TMIN[9]
TSTDSOCMABUSO12outputCELL_N[6].OUT_SEC_TMIN[8]
TSTDSOCMABUSO13outputCELL_N[1].OUT_SEC_TMIN[11]
TSTDSOCMABUSO14outputCELL_N[1].OUT_SEC_TMIN[10]
TSTDSOCMABUSO15outputCELL_N[2].OUT_SEC_TMIN[11]
TSTDSOCMABUSO16outputCELL_N[2].OUT_SEC_TMIN[10]
TSTDSOCMABUSO17outputCELL_N[3].OUT_SEC_TMIN[11]
TSTDSOCMABUSO18outputCELL_N[3].OUT_SEC_TMIN[10]
TSTDSOCMABUSO19outputCELL_N[4].OUT_SEC_TMIN[10]
TSTDSOCMABUSO2outputCELL_N[3].OUT_SEC_TMIN[12]
TSTDSOCMABUSO20outputCELL_N[4].OUT_SEC_TMIN[9]
TSTDSOCMABUSO21outputCELL_N[5].OUT_TEST[0]
TSTDSOCMABUSO22outputCELL_N[5].OUT_TEST[2]
TSTDSOCMABUSO23outputCELL_N[6].OUT_TEST[0]
TSTDSOCMABUSO24outputCELL_E[15].OUT_SEC_TMIN[12]
TSTDSOCMABUSO25outputCELL_E[0].OUT_SEC_TMIN[11]
TSTDSOCMABUSO26outputCELL_E[1].OUT_SEC_TMIN[11]
TSTDSOCMABUSO27outputCELL_E[2].OUT_SEC_TMIN[11]
TSTDSOCMABUSO28outputCELL_E[3].OUT_SEC_TMIN[11]
TSTDSOCMABUSO29outputCELL_E[4].OUT_SEC_TMIN[11]
TSTDSOCMABUSO3outputCELL_N[4].OUT_SEC_TMIN[12]
TSTDSOCMABUSO4outputCELL_N[4].OUT_SEC_TMIN[11]
TSTDSOCMABUSO5outputCELL_N[5].OUT_SEC_TMIN[11]
TSTDSOCMABUSO6outputCELL_N[5].OUT_SEC_TMIN[10]
TSTDSOCMABUSO7outputCELL_N[5].OUT_SEC_TMIN[9]
TSTDSOCMABUSO8outputCELL_N[5].OUT_SEC_TMIN[8]
TSTDSOCMABUSO9outputCELL_N[6].OUT_SEC_TMIN[11]
TSTDSOCMBYTEENI0inputCELL_E[11].IMUX_G2_DATA[3]
TSTDSOCMBYTEENI1inputCELL_E[11].IMUX_G3_DATA[3]
TSTDSOCMBYTEENI2inputCELL_E[12].IMUX_G2_DATA[3]
TSTDSOCMBYTEENI3inputCELL_E[12].IMUX_G3_DATA[3]
TSTDSOCMBYTEENO0outputCELL_E[5].OUT_SEC_TMIN[11]
TSTDSOCMBYTEENO1outputCELL_E[6].OUT_SEC_TMIN[11]
TSTDSOCMBYTEENO2outputCELL_E[7].OUT_SEC_TMIN[11]
TSTDSOCMBYTEENO3outputCELL_E[8].OUT_SEC_TMIN[11]
TSTDSOCMCOMPLETEIinputCELL_E[9].IMUX_G0_DATA[2]
TSTDSOCMDBUSI0inputCELL_E[6].IMUX_G1_DATA[3]
TSTDSOCMDBUSI1inputCELL_E[7].IMUX_G0_DATA[3]
TSTDSOCMDBUSI2inputCELL_E[7].IMUX_G1_DATA[3]
TSTDSOCMDBUSI3inputCELL_E[8].IMUX_G1_DATA[3]
TSTDSOCMDBUSI4inputCELL_E[8].IMUX_G2_DATA[3]
TSTDSOCMDBUSI5inputCELL_E[9].IMUX_G2_DATA[3]
TSTDSOCMDBUSI6inputCELL_E[9].IMUX_G3_DATA[3]
TSTDSOCMDBUSI7inputCELL_E[10].IMUX_G1_DATA[3]
TSTDSOCMDBUSO0outputCELL_E[8].OUT_SEC_TMIN[9]
TSTDSOCMDBUSO1outputCELL_E[8].OUT_SEC_TMIN[8]
TSTDSOCMDBUSO2outputCELL_E[8].OUT_TEST[0]
TSTDSOCMDBUSO3outputCELL_E[9].OUT_SEC_TMIN[10]
TSTDSOCMDBUSO4outputCELL_E[9].OUT_SEC_TMIN[9]
TSTDSOCMDBUSO5outputCELL_E[9].OUT_SEC_TMIN[8]
TSTDSOCMDBUSO6outputCELL_E[9].OUT_TEST[0]
TSTDSOCMDBUSO7outputCELL_E[10].OUT_SEC_TMIN[10]
TSTDSOCMDCRACKIinputCELL_E[10].IMUX_G2_DATA[3]
TSTDSOCMDCRACKOoutputCELL_E[10].OUT_SEC_TMIN[9]
TSTDSOCMHOLDIinputCELL_E[10].IMUX_G0_DATA[2]
TSTDSOCMHOLDOoutputCELL_E[5].OUT_TEST[2]
TSTDSOCMLOADREQIinputCELL_E[13].IMUX_G2_DATA[3]
TSTDSOCMLOADREQOoutputCELL_E[9].OUT_SEC_TMIN[11]
TSTDSOCMSTOREREQIinputCELL_E[13].IMUX_G3_DATA[3]
TSTDSOCMSTOREREQOoutputCELL_E[10].OUT_SEC_TMIN[11]
TSTDSOCMWAITIinputCELL_E[14].IMUX_G2_DATA[3]
TSTDSOCMWAITOoutputCELL_E[11].OUT_SEC_TMIN[11]
TSTDSOCMWRDBUSI0inputCELL_E[14].IMUX_G3_DATA[3]
TSTDSOCMWRDBUSI1inputCELL_E[15].IMUX_G2_DATA[3]
TSTDSOCMWRDBUSI10inputCELL_E[3].IMUX_G3_DATA[4]
TSTDSOCMWRDBUSI11inputCELL_E[4].IMUX_G0_DATA[4]
TSTDSOCMWRDBUSI12inputCELL_E[4].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI13inputCELL_E[5].IMUX_G0_DATA[4]
TSTDSOCMWRDBUSI14inputCELL_E[5].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI15inputCELL_E[6].IMUX_G0_DATA[4]
TSTDSOCMWRDBUSI16inputCELL_E[6].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI17inputCELL_E[7].IMUX_G0_DATA[4]
TSTDSOCMWRDBUSI18inputCELL_E[7].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI19inputCELL_E[8].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI2inputCELL_E[15].IMUX_G3_DATA[3]
TSTDSOCMWRDBUSI20inputCELL_E[8].IMUX_G2_DATA[4]
TSTDSOCMWRDBUSI21inputCELL_E[9].IMUX_G2_DATA[4]
TSTDSOCMWRDBUSI22inputCELL_E[9].IMUX_G3_DATA[4]
TSTDSOCMWRDBUSI23inputCELL_E[10].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI24inputCELL_E[10].IMUX_G2_DATA[4]
TSTDSOCMWRDBUSI25inputCELL_E[11].IMUX_G0_DATA[4]
TSTDSOCMWRDBUSI26inputCELL_E[11].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI27inputCELL_E[12].IMUX_G0_DATA[4]
TSTDSOCMWRDBUSI28inputCELL_E[12].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI29inputCELL_E[13].IMUX_G0_DATA[4]
TSTDSOCMWRDBUSI3inputCELL_E[0].IMUX_G2_DATA[4]
TSTDSOCMWRDBUSI30inputCELL_E[13].IMUX_G1_DATA[4]
TSTDSOCMWRDBUSI31inputCELL_E[14].IMUX_G0_DATA[4]
TSTDSOCMWRDBUSI4inputCELL_E[0].IMUX_G3_DATA[4]
TSTDSOCMWRDBUSI5inputCELL_E[1].IMUX_G2_DATA[4]
TSTDSOCMWRDBUSI6inputCELL_E[1].IMUX_G3_DATA[4]
TSTDSOCMWRDBUSI7inputCELL_E[2].IMUX_G2_DATA[4]
TSTDSOCMWRDBUSI8inputCELL_E[2].IMUX_G3_DATA[4]
TSTDSOCMWRDBUSI9inputCELL_E[3].IMUX_G2_DATA[4]
TSTDSOCMWRDBUSO0outputCELL_N[6].OUT_TEST[2]
TSTDSOCMWRDBUSO1outputCELL_N[0].OUT_SEC_TMIN[12]
TSTDSOCMWRDBUSO10outputCELL_N[5].OUT_TEST[4]
TSTDSOCMWRDBUSO11outputCELL_N[5].OUT_TEST[6]
TSTDSOCMWRDBUSO12outputCELL_N[6].OUT_TEST[4]
TSTDSOCMWRDBUSO13outputCELL_N[6].OUT_TEST[6]
TSTDSOCMWRDBUSO14outputCELL_N[0].OUT_SEC_TMIN[11]
TSTDSOCMWRDBUSO15outputCELL_N[0].OUT_SEC_TMIN[10]
TSTDSOCMWRDBUSO16outputCELL_N[1].OUT_TEST[0]
TSTDSOCMWRDBUSO17outputCELL_N[1].OUT_TEST[2]
TSTDSOCMWRDBUSO18outputCELL_N[2].OUT_TEST[0]
TSTDSOCMWRDBUSO19outputCELL_N[2].OUT_TEST[2]
TSTDSOCMWRDBUSO2outputCELL_N[1].OUT_SEC_TMIN[9]
TSTDSOCMWRDBUSO20outputCELL_N[3].OUT_TEST[0]
TSTDSOCMWRDBUSO21outputCELL_N[3].OUT_TEST[2]
TSTDSOCMWRDBUSO22outputCELL_N[4].OUT_TEST[2]
TSTDSOCMWRDBUSO23outputCELL_N[4].OUT_TEST[4]
TSTDSOCMWRDBUSO24outputCELL_N[5].OUT_TEST[8]
TSTDSOCMWRDBUSO25outputCELL_N[5].OUT_TEST[10]
TSTDSOCMWRDBUSO26outputCELL_N[6].OUT_TEST[8]
TSTDSOCMWRDBUSO27outputCELL_N[6].OUT_TEST[10]
TSTDSOCMWRDBUSO28outputCELL_N[0].OUT_SEC_TMIN[9]
TSTDSOCMWRDBUSO29outputCELL_N[1].OUT_TEST[4]
TSTDSOCMWRDBUSO3outputCELL_N[1].OUT_SEC_TMIN[8]
TSTDSOCMWRDBUSO30outputCELL_N[2].OUT_TEST[4]
TSTDSOCMWRDBUSO31outputCELL_N[3].OUT_TEST[4]
TSTDSOCMWRDBUSO4outputCELL_N[2].OUT_SEC_TMIN[9]
TSTDSOCMWRDBUSO5outputCELL_N[2].OUT_SEC_TMIN[8]
TSTDSOCMWRDBUSO6outputCELL_N[3].OUT_SEC_TMIN[9]
TSTDSOCMWRDBUSO7outputCELL_N[3].OUT_SEC_TMIN[8]
TSTDSOCMWRDBUSO8outputCELL_N[4].OUT_SEC_TMIN[8]
TSTDSOCMWRDBUSO9outputCELL_N[4].OUT_TEST[0]
TSTDSOCMXLATEVALIDIinputCELL_E[14].IMUX_G1_DATA[4]
TSTDSOCMXLATEVALIDOoutputCELL_E[12].OUT_SEC_TMIN[11]
TSTISOCMABORTIinputCELL_W[11].IMUX_G3_DATA[2]
TSTISOCMABORTOoutputCELL_S[0].OUT_TEST[2]
TSTISOCMABUSI0inputCELL_W[1].IMUX_G0_DATA[3]
TSTISOCMABUSI1inputCELL_W[1].IMUX_G1_DATA[3]
TSTISOCMABUSI10inputCELL_W[4].IMUX_G1_DATA[3]
TSTISOCMABUSI11inputCELL_W[5].IMUX_G1_DATA[3]
TSTISOCMABUSI12inputCELL_W[5].IMUX_G2_DATA[3]
TSTISOCMABUSI13inputCELL_W[6].IMUX_G2_DATA[3]
TSTISOCMABUSI14inputCELL_W[6].IMUX_G3_DATA[3]
TSTISOCMABUSI15inputCELL_W[6].IMUX_G0_DATA[4]
TSTISOCMABUSI16inputCELL_W[7].IMUX_G1_DATA[3]
TSTISOCMABUSI17inputCELL_W[7].IMUX_G2_DATA[3]
TSTISOCMABUSI18inputCELL_W[7].IMUX_G3_DATA[3]
TSTISOCMABUSI19inputCELL_W[8].IMUX_G1_DATA[3]
TSTISOCMABUSI2inputCELL_W[2].IMUX_G3_DATA[2]
TSTISOCMABUSI20inputCELL_W[8].IMUX_G2_DATA[3]
TSTISOCMABUSI21inputCELL_W[8].IMUX_G3_DATA[3]
TSTISOCMABUSI22inputCELL_W[9].IMUX_G1_DATA[3]
TSTISOCMABUSI23inputCELL_W[9].IMUX_G2_DATA[3]
TSTISOCMABUSI24inputCELL_W[9].IMUX_G3_DATA[3]
TSTISOCMABUSI25inputCELL_W[10].IMUX_G2_DATA[2]
TSTISOCMABUSI26inputCELL_W[10].IMUX_G3_DATA[2]
TSTISOCMABUSI27inputCELL_W[10].IMUX_G0_DATA[3]
TSTISOCMABUSI28inputCELL_W[10].IMUX_G1_DATA[3]
TSTISOCMABUSI29inputCELL_W[11].IMUX_G2_DATA[2]
TSTISOCMABUSI3inputCELL_W[2].IMUX_G0_DATA[3]
TSTISOCMABUSI4inputCELL_W[2].IMUX_G1_DATA[3]
TSTISOCMABUSI5inputCELL_W[3].IMUX_G2_DATA[2]
TSTISOCMABUSI6inputCELL_W[3].IMUX_G3_DATA[2]
TSTISOCMABUSI7inputCELL_W[3].IMUX_G0_DATA[3]
TSTISOCMABUSI8inputCELL_W[4].IMUX_G3_DATA[2]
TSTISOCMABUSI9inputCELL_W[4].IMUX_G0_DATA[3]
TSTISOCMABUSO0outputCELL_S[0].OUT_SEC_TMIN[8]
TSTISOCMABUSO1outputCELL_S[1].OUT_SEC_TMIN[13]
TSTISOCMABUSO10outputCELL_S[3].OUT_SEC_TMIN[14]
TSTISOCMABUSO11outputCELL_S[3].OUT_SEC_TMIN[13]
TSTISOCMABUSO12outputCELL_S[3].OUT_SEC_TMIN[12]
TSTISOCMABUSO13outputCELL_S[4].OUT_SEC_TMIN[15]
TSTISOCMABUSO14outputCELL_S[4].OUT_SEC_TMIN[14]
TSTISOCMABUSO15outputCELL_S[4].OUT_SEC_TMIN[13]
TSTISOCMABUSO16outputCELL_S[4].OUT_SEC_TMIN[12]
TSTISOCMABUSO17outputCELL_S[5].OUT_SEC_TMIN[15]
TSTISOCMABUSO18outputCELL_S[5].OUT_SEC_TMIN[14]
TSTISOCMABUSO19outputCELL_S[5].OUT_SEC_TMIN[13]
TSTISOCMABUSO2outputCELL_S[1].OUT_SEC_TMIN[12]
TSTISOCMABUSO20outputCELL_S[5].OUT_SEC_TMIN[12]
TSTISOCMABUSO21outputCELL_S[6].OUT_SEC_TMIN[11]
TSTISOCMABUSO22outputCELL_S[6].OUT_SEC_TMIN[10]
TSTISOCMABUSO23outputCELL_S[6].OUT_SEC_TMIN[9]
TSTISOCMABUSO24outputCELL_S[6].OUT_SEC_TMIN[8]
TSTISOCMABUSO25outputCELL_S[7].OUT_SEC_TMIN[14]
TSTISOCMABUSO26outputCELL_S[7].OUT_SEC_TMIN[13]
TSTISOCMABUSO27outputCELL_S[7].OUT_SEC_TMIN[12]
TSTISOCMABUSO28outputCELL_S[7].OUT_SEC_TMIN[11]
TSTISOCMABUSO29outputCELL_S[0].OUT_TEST[0]
TSTISOCMABUSO3outputCELL_S[1].OUT_SEC_TMIN[11]
TSTISOCMABUSO4outputCELL_S[1].OUT_SEC_TMIN[10]
TSTISOCMABUSO5outputCELL_S[2].OUT_SEC_TMIN[12]
TSTISOCMABUSO6outputCELL_S[2].OUT_SEC_TMIN[11]
TSTISOCMABUSO7outputCELL_S[2].OUT_SEC_TMIN[10]
TSTISOCMABUSO8outputCELL_S[2].OUT_SEC_TMIN[9]
TSTISOCMABUSO9outputCELL_S[3].OUT_SEC_TMIN[15]
TSTISOCMHOLDIinputCELL_W[2].IMUX_G1_DATA[2]
TSTISOCMHOLDOoutputCELL_W[2].OUT_SEC_TMIN[10]
TSTISOCMICUREADYIinputCELL_W[1].IMUX_G3_DATA[2]
TSTISOCMICUREADYOoutputCELL_S[0].OUT_SEC_TMIN[9]
TSTISOCMRDATAI0inputCELL_W[5].IMUX_G3_DATA[2]
TSTISOCMRDATAI1inputCELL_W[6].IMUX_G0_DATA[3]
TSTISOCMRDATAI10inputCELL_W[15].IMUX_G1_DATA[2]
TSTISOCMRDATAI11inputCELL_W[0].IMUX_G2_DATA[2]
TSTISOCMRDATAI12inputCELL_W[1].IMUX_G2_DATA[2]
TSTISOCMRDATAI13inputCELL_W[2].IMUX_G2_DATA[2]
TSTISOCMRDATAI14inputCELL_W[3].IMUX_G1_DATA[2]
TSTISOCMRDATAI15inputCELL_W[4].IMUX_G2_DATA[2]
TSTISOCMRDATAI16inputCELL_W[5].IMUX_G0_DATA[3]
TSTISOCMRDATAI17inputCELL_S[0].IMUX_G0_DATA[4]
TSTISOCMRDATAI18inputCELL_S[0].IMUX_G1_DATA[4]
TSTISOCMRDATAI19inputCELL_S[0].IMUX_G2_DATA[4]
TSTISOCMRDATAI2inputCELL_W[7].IMUX_G0_DATA[3]
TSTISOCMRDATAI20inputCELL_S[0].IMUX_G3_DATA[4]
TSTISOCMRDATAI21inputCELL_S[1].IMUX_G0_DATA[4]
TSTISOCMRDATAI22inputCELL_S[1].IMUX_G1_DATA[4]
TSTISOCMRDATAI23inputCELL_S[1].IMUX_G2_DATA[4]
TSTISOCMRDATAI24inputCELL_S[1].IMUX_G3_DATA[4]
TSTISOCMRDATAI25inputCELL_S[2].IMUX_G2_DATA[0]
TSTISOCMRDATAI26inputCELL_S[2].IMUX_G3_DATA[0]
TSTISOCMRDATAI27inputCELL_S[2].IMUX_G0_DATA[1]
TSTISOCMRDATAI28inputCELL_S[2].IMUX_G1_DATA[1]
TSTISOCMRDATAI29inputCELL_S[3].IMUX_G0_DATA[0]
TSTISOCMRDATAI3inputCELL_W[8].IMUX_G0_DATA[3]
TSTISOCMRDATAI30inputCELL_S[3].IMUX_G1_DATA[0]
TSTISOCMRDATAI31inputCELL_S[3].IMUX_G2_DATA[0]
TSTISOCMRDATAI32inputCELL_S[3].IMUX_G3_DATA[0]
TSTISOCMRDATAI33inputCELL_S[4].IMUX_G1_DATA[0]
TSTISOCMRDATAI34inputCELL_S[4].IMUX_G2_DATA[0]
TSTISOCMRDATAI35inputCELL_S[4].IMUX_G3_DATA[0]
TSTISOCMRDATAI36inputCELL_S[4].IMUX_G0_DATA[1]
TSTISOCMRDATAI37inputCELL_S[5].IMUX_G2_DATA[0]
TSTISOCMRDATAI38inputCELL_S[5].IMUX_G3_DATA[0]
TSTISOCMRDATAI39inputCELL_S[5].IMUX_G0_DATA[1]
TSTISOCMRDATAI4inputCELL_W[9].IMUX_G0_DATA[3]
TSTISOCMRDATAI40inputCELL_S[5].IMUX_G1_DATA[1]
TSTISOCMRDATAI41inputCELL_S[6].IMUX_G0_DATA[4]
TSTISOCMRDATAI42inputCELL_S[6].IMUX_G1_DATA[4]
TSTISOCMRDATAI43inputCELL_S[6].IMUX_G2_DATA[4]
TSTISOCMRDATAI44inputCELL_S[6].IMUX_G3_DATA[4]
TSTISOCMRDATAI45inputCELL_S[7].IMUX_G0_DATA[4]
TSTISOCMRDATAI46inputCELL_S[7].IMUX_G1_DATA[4]
TSTISOCMRDATAI47inputCELL_S[7].IMUX_G2_DATA[4]
TSTISOCMRDATAI48inputCELL_S[7].IMUX_G3_DATA[4]
TSTISOCMRDATAI49inputCELL_S[0].IMUX_G0_DATA[5]
TSTISOCMRDATAI5inputCELL_W[10].IMUX_G1_DATA[2]
TSTISOCMRDATAI50inputCELL_S[0].IMUX_G1_DATA[5]
TSTISOCMRDATAI51inputCELL_S[1].IMUX_G0_DATA[5]
TSTISOCMRDATAI52inputCELL_S[1].IMUX_G1_DATA[5]
TSTISOCMRDATAI53inputCELL_S[2].IMUX_G2_DATA[1]
TSTISOCMRDATAI54inputCELL_S[2].IMUX_G3_DATA[1]
TSTISOCMRDATAI55inputCELL_S[3].IMUX_G0_DATA[1]
TSTISOCMRDATAI56inputCELL_S[3].IMUX_G1_DATA[1]
TSTISOCMRDATAI57inputCELL_S[4].IMUX_G1_DATA[1]
TSTISOCMRDATAI58inputCELL_S[4].IMUX_G2_DATA[1]
TSTISOCMRDATAI59inputCELL_S[5].IMUX_G2_DATA[1]
TSTISOCMRDATAI6inputCELL_W[11].IMUX_G1_DATA[2]
TSTISOCMRDATAI60inputCELL_S[5].IMUX_G3_DATA[1]
TSTISOCMRDATAI61inputCELL_S[6].IMUX_G0_DATA[5]
TSTISOCMRDATAI62inputCELL_S[6].IMUX_G1_DATA[5]
TSTISOCMRDATAI63inputCELL_S[7].IMUX_G0_DATA[5]
TSTISOCMRDATAI7inputCELL_W[12].IMUX_G1_DATA[2]
TSTISOCMRDATAI8inputCELL_W[13].IMUX_G1_DATA[2]
TSTISOCMRDATAI9inputCELL_W[14].IMUX_G1_DATA[2]
TSTISOCMRDATAO0outputCELL_W[2].OUT_TEST[0]
TSTISOCMRDATAO1outputCELL_W[3].OUT_SEC_TMIN[10]
TSTISOCMRDATAO10outputCELL_W[5].OUT_SEC_TMIN[10]
TSTISOCMRDATAO11outputCELL_W[5].OUT_SEC_TMIN[9]
TSTISOCMRDATAO12outputCELL_W[5].OUT_SEC_TMIN[8]
TSTISOCMRDATAO13outputCELL_W[6].OUT_SEC_TMIN[11]
TSTISOCMRDATAO14outputCELL_W[6].OUT_SEC_TMIN[10]
TSTISOCMRDATAO15outputCELL_W[6].OUT_SEC_TMIN[9]
TSTISOCMRDATAO16outputCELL_W[6].OUT_SEC_TMIN[8]
TSTISOCMRDATAO17outputCELL_W[7].OUT_SEC_TMIN[11]
TSTISOCMRDATAO18outputCELL_W[7].OUT_SEC_TMIN[10]
TSTISOCMRDATAO19outputCELL_W[7].OUT_SEC_TMIN[9]
TSTISOCMRDATAO2outputCELL_W[3].OUT_SEC_TMIN[9]
TSTISOCMRDATAO20outputCELL_W[7].OUT_SEC_TMIN[8]
TSTISOCMRDATAO21outputCELL_W[8].OUT_SEC_TMIN[11]
TSTISOCMRDATAO22outputCELL_W[8].OUT_SEC_TMIN[10]
TSTISOCMRDATAO23outputCELL_W[8].OUT_SEC_TMIN[9]
TSTISOCMRDATAO24outputCELL_W[8].OUT_SEC_TMIN[8]
TSTISOCMRDATAO25outputCELL_W[9].OUT_SEC_TMIN[11]
TSTISOCMRDATAO26outputCELL_W[9].OUT_SEC_TMIN[10]
TSTISOCMRDATAO27outputCELL_W[9].OUT_SEC_TMIN[9]
TSTISOCMRDATAO28outputCELL_W[9].OUT_SEC_TMIN[8]
TSTISOCMRDATAO29outputCELL_W[10].OUT_SEC_TMIN[11]
TSTISOCMRDATAO3outputCELL_W[3].OUT_SEC_TMIN[8]
TSTISOCMRDATAO30outputCELL_W[10].OUT_SEC_TMIN[10]
TSTISOCMRDATAO31outputCELL_W[10].OUT_SEC_TMIN[9]
TSTISOCMRDATAO32outputCELL_W[10].OUT_SEC_TMIN[8]
TSTISOCMRDATAO33outputCELL_W[11].OUT_SEC_TMIN[11]
TSTISOCMRDATAO34outputCELL_W[11].OUT_SEC_TMIN[10]
TSTISOCMRDATAO35outputCELL_W[11].OUT_SEC_TMIN[9]
TSTISOCMRDATAO36outputCELL_W[11].OUT_SEC_TMIN[8]
TSTISOCMRDATAO37outputCELL_W[12].OUT_SEC_TMIN[11]
TSTISOCMRDATAO38outputCELL_W[12].OUT_SEC_TMIN[10]
TSTISOCMRDATAO39outputCELL_W[12].OUT_SEC_TMIN[9]
TSTISOCMRDATAO4outputCELL_W[3].OUT_TEST[0]
TSTISOCMRDATAO40outputCELL_W[12].OUT_SEC_TMIN[8]
TSTISOCMRDATAO41outputCELL_W[13].OUT_SEC_TMIN[11]
TSTISOCMRDATAO42outputCELL_W[13].OUT_SEC_TMIN[10]
TSTISOCMRDATAO43outputCELL_W[13].OUT_SEC_TMIN[9]
TSTISOCMRDATAO44outputCELL_W[13].OUT_SEC_TMIN[8]
TSTISOCMRDATAO45outputCELL_W[14].OUT_SEC_TMIN[11]
TSTISOCMRDATAO46outputCELL_W[14].OUT_SEC_TMIN[10]
TSTISOCMRDATAO47outputCELL_W[14].OUT_SEC_TMIN[9]
TSTISOCMRDATAO48outputCELL_W[14].OUT_SEC_TMIN[8]
TSTISOCMRDATAO49outputCELL_W[15].OUT_SEC_TMIN[11]
TSTISOCMRDATAO5outputCELL_W[4].OUT_SEC_TMIN[11]
TSTISOCMRDATAO50outputCELL_W[15].OUT_SEC_TMIN[10]
TSTISOCMRDATAO51outputCELL_W[15].OUT_SEC_TMIN[9]
TSTISOCMRDATAO52outputCELL_W[15].OUT_SEC_TMIN[8]
TSTISOCMRDATAO53outputCELL_W[0].OUT_TEST[2]
TSTISOCMRDATAO54outputCELL_W[0].OUT_TEST[4]
TSTISOCMRDATAO55outputCELL_W[1].OUT_TEST[2]
TSTISOCMRDATAO56outputCELL_W[1].OUT_TEST[4]
TSTISOCMRDATAO57outputCELL_W[2].OUT_TEST[2]
TSTISOCMRDATAO58outputCELL_W[2].OUT_TEST[4]
TSTISOCMRDATAO59outputCELL_W[3].OUT_TEST[2]
TSTISOCMRDATAO6outputCELL_W[4].OUT_SEC_TMIN[10]
TSTISOCMRDATAO60outputCELL_W[3].OUT_TEST[4]
TSTISOCMRDATAO61outputCELL_W[4].OUT_TEST[0]
TSTISOCMRDATAO62outputCELL_W[4].OUT_TEST[2]
TSTISOCMRDATAO63outputCELL_W[5].OUT_TEST[0]
TSTISOCMRDATAO7outputCELL_W[4].OUT_SEC_TMIN[9]
TSTISOCMRDATAO8outputCELL_W[4].OUT_SEC_TMIN[8]
TSTISOCMRDATAO9outputCELL_W[5].OUT_SEC_TMIN[11]
TSTISOCMRDDVALIDI0inputCELL_W[3].IMUX_G0_DATA[2]
TSTISOCMRDDVALIDI1inputCELL_W[4].IMUX_G1_DATA[2]
TSTISOCMRDDVALIDO0outputCELL_W[2].OUT_SEC_TMIN[9]
TSTISOCMRDDVALIDO1outputCELL_W[2].OUT_SEC_TMIN[8]
TSTISOCMREQPENDIinputCELL_W[0].IMUX_G0_DATA[3]
TSTISOCMREQPENDOoutputCELL_S[0].OUT_SEC_TMIN[10]
TSTISOCMXLATEVALIDIinputCELL_W[0].IMUX_G3_DATA[2]
TSTISOCMXLATEVALIDOoutputCELL_S[0].OUT_SEC_TMIN[11]
TSTISOPFWDIinputCELL_E[9].IMUX_G1_DATA[2]
TSTISOPFWDOoutputCELL_E[5].OUT_TEST[4]
TSTJTAGENIinputCELL_W[12].IMUX_G0_DATA[2]
TSTJTAGENOoutputCELL_W[0].OUT_TEST[0]
TSTOCMCOMPLETEOoutputCELL_E[6].OUT_TEST[2]
TSTPLBSAMPLECYCLEIinputCELL_W[6].IMUX_G1_DATA[3]
TSTPLBSAMPLECYCLEOoutputCELL_W[5].OUT_TEST[2]
TSTRDDBUSI0inputCELL_E[10].IMUX_G1_DATA[2]
TSTRDDBUSI1inputCELL_E[11].IMUX_G0_DATA[2]
TSTRDDBUSI10inputCELL_E[15].IMUX_G1_DATA[2]
TSTRDDBUSI11inputCELL_E[0].IMUX_G2_DATA[2]
TSTRDDBUSI12inputCELL_E[0].IMUX_G3_DATA[2]
TSTRDDBUSI13inputCELL_E[1].IMUX_G2_DATA[2]
TSTRDDBUSI14inputCELL_E[1].IMUX_G3_DATA[2]
TSTRDDBUSI15inputCELL_E[2].IMUX_G2_DATA[2]
TSTRDDBUSI16inputCELL_E[2].IMUX_G3_DATA[2]
TSTRDDBUSI17inputCELL_E[3].IMUX_G2_DATA[2]
TSTRDDBUSI18inputCELL_E[3].IMUX_G3_DATA[2]
TSTRDDBUSI19inputCELL_E[4].IMUX_G0_DATA[2]
TSTRDDBUSI2inputCELL_E[11].IMUX_G1_DATA[2]
TSTRDDBUSI20inputCELL_E[4].IMUX_G1_DATA[2]
TSTRDDBUSI21inputCELL_E[5].IMUX_G0_DATA[2]
TSTRDDBUSI22inputCELL_E[5].IMUX_G1_DATA[2]
TSTRDDBUSI23inputCELL_E[6].IMUX_G0_DATA[2]
TSTRDDBUSI24inputCELL_E[6].IMUX_G1_DATA[2]
TSTRDDBUSI25inputCELL_E[7].IMUX_G0_DATA[2]
TSTRDDBUSI26inputCELL_E[7].IMUX_G1_DATA[2]
TSTRDDBUSI27inputCELL_E[8].IMUX_G2_DATA[2]
TSTRDDBUSI28inputCELL_E[8].IMUX_G3_DATA[2]
TSTRDDBUSI29inputCELL_E[9].IMUX_G2_DATA[2]
TSTRDDBUSI3inputCELL_E[12].IMUX_G0_DATA[2]
TSTRDDBUSI30inputCELL_E[9].IMUX_G3_DATA[2]
TSTRDDBUSI31inputCELL_E[10].IMUX_G2_DATA[2]
TSTRDDBUSI4inputCELL_E[12].IMUX_G1_DATA[2]
TSTRDDBUSI5inputCELL_E[13].IMUX_G0_DATA[2]
TSTRDDBUSI6inputCELL_E[13].IMUX_G1_DATA[2]
TSTRDDBUSI7inputCELL_E[14].IMUX_G0_DATA[2]
TSTRDDBUSI8inputCELL_E[14].IMUX_G1_DATA[2]
TSTRDDBUSI9inputCELL_E[15].IMUX_G0_DATA[2]
TSTRDDBUSO0outputCELL_E[10].OUT_SEC_TMIN[8]
TSTRDDBUSO1outputCELL_E[10].OUT_TEST[0]
TSTRDDBUSO10outputCELL_E[13].OUT_SEC_TMIN[11]
TSTRDDBUSO11outputCELL_E[13].OUT_SEC_TMIN[10]
TSTRDDBUSO12outputCELL_E[13].OUT_SEC_TMIN[9]
TSTRDDBUSO13outputCELL_E[13].OUT_SEC_TMIN[8]
TSTRDDBUSO14outputCELL_E[14].OUT_SEC_TMIN[11]
TSTRDDBUSO15outputCELL_E[14].OUT_SEC_TMIN[10]
TSTRDDBUSO16outputCELL_E[14].OUT_SEC_TMIN[9]
TSTRDDBUSO17outputCELL_E[14].OUT_SEC_TMIN[8]
TSTRDDBUSO18outputCELL_E[15].OUT_SEC_TMIN[11]
TSTRDDBUSO19outputCELL_E[15].OUT_SEC_TMIN[10]
TSTRDDBUSO2outputCELL_E[11].OUT_SEC_TMIN[10]
TSTRDDBUSO20outputCELL_E[15].OUT_SEC_TMIN[9]
TSTRDDBUSO21outputCELL_E[15].OUT_SEC_TMIN[8]
TSTRDDBUSO22outputCELL_E[0].OUT_TEST[2]
TSTRDDBUSO23outputCELL_E[0].OUT_TEST[4]
TSTRDDBUSO24outputCELL_E[1].OUT_TEST[2]
TSTRDDBUSO25outputCELL_E[1].OUT_TEST[4]
TSTRDDBUSO26outputCELL_E[2].OUT_TEST[2]
TSTRDDBUSO27outputCELL_E[2].OUT_TEST[4]
TSTRDDBUSO28outputCELL_E[3].OUT_TEST[2]
TSTRDDBUSO29outputCELL_E[3].OUT_TEST[4]
TSTRDDBUSO3outputCELL_E[11].OUT_SEC_TMIN[9]
TSTRDDBUSO30outputCELL_E[4].OUT_TEST[2]
TSTRDDBUSO31outputCELL_E[4].OUT_TEST[4]
TSTRDDBUSO4outputCELL_E[11].OUT_SEC_TMIN[8]
TSTRDDBUSO5outputCELL_E[11].OUT_TEST[0]
TSTRDDBUSO6outputCELL_E[12].OUT_SEC_TMIN[10]
TSTRDDBUSO7outputCELL_E[12].OUT_SEC_TMIN[9]
TSTRDDBUSO8outputCELL_E[12].OUT_SEC_TMIN[8]
TSTRDDBUSO9outputCELL_E[12].OUT_TEST[0]
TSTRESETCHIPIinputCELL_W[0].IMUX_G0_DATA[2]
TSTRESETCHIPOoutputCELL_W[0].OUT_SEC_TMIN[10]
TSTRESETCOREIinputCELL_W[5].IMUX_G2_DATA[2]
TSTRESETCOREOoutputCELL_W[0].OUT_SEC_TMIN[9]
TSTRESETSYSIinputCELL_W[11].IMUX_G0_DATA[2]
TSTRESETSYSOoutputCELL_W[0].OUT_SEC_TMIN[8]
TSTTIMERENIinputCELL_W[13].IMUX_G0_DATA[2]
TSTTIMERENOoutputCELL_W[1].OUT_SEC_TMIN[10]
TSTTRSTNEGIinputCELL_N[2].IMUX_G2_DATA[0]
TSTTRSTNEGOoutputCELL_W[12].OUT_TEST[0]

Bel wires

virtex2 PPC_E bel wires
WirePins
CELL_W[0].IMUX_CLK[1]PPC405.PLBCLK
CELL_W[0].IMUX_TI[0]PPC405.TIEC405DETERMINISTICMULT
CELL_W[0].IMUX_TI[1]PPC405.TIEC405PVR30
CELL_W[0].IMUX_TS[0]PPC405.TIEC405PVR31
CELL_W[0].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS60
CELL_W[0].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS60
CELL_W[0].IMUX_G0_DATA[2]PPC405.TSTRESETCHIPI
CELL_W[0].IMUX_G0_DATA[3]PPC405.TSTISOCMREQPENDI
CELL_W[0].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS61
CELL_W[0].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS61
CELL_W[0].IMUX_G1_DATA[2]PPC405.TSTCPUCLKI
CELL_W[0].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS62
CELL_W[0].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS62
CELL_W[0].IMUX_G2_DATA[2]PPC405.TSTISOCMRDATAI11
CELL_W[0].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS63
CELL_W[0].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS63
CELL_W[0].IMUX_G3_DATA[2]PPC405.TSTISOCMXLATEVALIDI
CELL_W[0].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS60
CELL_W[0].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS61
CELL_W[0].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS62
CELL_W[0].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS63
CELL_W[0].OUT_FAN_TMIN[4]PPC405.C405RSTCHIPRESETREQ
CELL_W[0].OUT_FAN_TMIN[5]PPC405.C405RSTCORERESETREQ
CELL_W[0].OUT_FAN_TMIN[6]PPC405.C405CPMTIMERIRQ
CELL_W[0].OUT_FAN_TMIN[7]PPC405.C405CPMTIMERRESETREQ
CELL_W[0].OUT_SEC_TMIN[8]PPC405.TSTRESETSYSO
CELL_W[0].OUT_SEC_TMIN[9]PPC405.TSTRESETCOREO
CELL_W[0].OUT_SEC_TMIN[10]PPC405.TSTRESETCHIPO
CELL_W[0].OUT_SEC_TMIN[11]PPC405.C405DBGWBIAR26
CELL_W[0].OUT_SEC_TMIN[12]PPC405.C405DBGWBIAR21
CELL_W[0].OUT_SEC_TMIN[13]PPC405.C405DBGWBIAR7
CELL_W[0].OUT_SEC_TMIN[14]PPC405.C405DBGWBFULL
CELL_W[0].OUT_SEC_TMIN[15]PPC405.C405DBGWBCOMPLETE
CELL_W[0].OUT_TEST[0]PPC405.TSTJTAGENO
CELL_W[0].OUT_TEST[2]PPC405.TSTISOCMRDATAO53
CELL_W[0].OUT_TEST[4]PPC405.TSTISOCMRDATAO54
CELL_W[1].IMUX_CE[0]PPC405.CPMC405CPUCLKEN
CELL_W[1].IMUX_TI[0]PPC405.TIEC405DISOPERANDFWD
CELL_W[1].IMUX_TI[1]PPC405.TIEC405MMUEN
CELL_W[1].IMUX_TS[0]PPC405.TIEC405PVR29
CELL_W[1].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS56
CELL_W[1].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS56
CELL_W[1].IMUX_G0_DATA[2]PPC405.DBGC405DEBUGHALT
CELL_W[1].IMUX_G0_DATA[3]PPC405.TSTISOCMABUSI0
CELL_W[1].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS57
CELL_W[1].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS57
CELL_W[1].IMUX_G1_DATA[2]PPC405.TSTCLKINACTI
CELL_W[1].IMUX_G1_DATA[3]PPC405.TSTISOCMABUSI1
CELL_W[1].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS58
CELL_W[1].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS58
CELL_W[1].IMUX_G2_DATA[2]PPC405.TSTISOCMRDATAI12
CELL_W[1].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS59
CELL_W[1].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS59
CELL_W[1].IMUX_G3_DATA[2]PPC405.TSTISOCMICUREADYI
CELL_W[1].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS56
CELL_W[1].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS57
CELL_W[1].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS58
CELL_W[1].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS59
CELL_W[1].OUT_FAN_TMIN[4]PPC405.C405PLBDCUREQUEST
CELL_W[1].OUT_FAN_TMIN[5]PPC405.C405PLBDCUPRIORITY0
CELL_W[1].OUT_FAN_TMIN[6]PPC405.C405PLBDCUPRIORITY1
CELL_W[1].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABORT
CELL_W[1].OUT_SEC_TMIN[8]PPC405.TSTCPUCLKO
CELL_W[1].OUT_SEC_TMIN[9]PPC405.TSTCPUCLKENO
CELL_W[1].OUT_SEC_TMIN[10]PPC405.TSTTIMERENO
CELL_W[1].OUT_SEC_TMIN[11]PPC405.C405DBGWBIAR27
CELL_W[1].OUT_SEC_TMIN[12]PPC405.C405DBGWBIAR22
CELL_W[1].OUT_SEC_TMIN[13]PPC405.C405DBGWBIAR8
CELL_W[1].OUT_SEC_TMIN[14]PPC405.C405DBGWBIAR0
CELL_W[1].OUT_SEC_TMIN[15]PPC405.C405PLBDCURNW
CELL_W[1].OUT_TEST[0]PPC405.TSTCLKINACTO
CELL_W[1].OUT_TEST[2]PPC405.TSTISOCMRDATAO55
CELL_W[1].OUT_TEST[4]PPC405.TSTISOCMRDATAO56
CELL_W[2].IMUX_CE[0]PPC405.CPMC405TIMERCLKEN
CELL_W[2].IMUX_TI[0]PPC405.TIEC405PVR26
CELL_W[2].IMUX_TI[1]PPC405.TIEC405PVR27
CELL_W[2].IMUX_TS[0]PPC405.TIEC405PVR28
CELL_W[2].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS52
CELL_W[2].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS52
CELL_W[2].IMUX_G0_DATA[2]PPC405.DBGC405UNCONDDEBUGEVENT
CELL_W[2].IMUX_G0_DATA[3]PPC405.TSTISOCMABUSI3
CELL_W[2].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS53
CELL_W[2].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS53
CELL_W[2].IMUX_G1_DATA[2]PPC405.TSTISOCMHOLDI
CELL_W[2].IMUX_G1_DATA[3]PPC405.TSTISOCMABUSI4
CELL_W[2].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS54
CELL_W[2].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS54
CELL_W[2].IMUX_G2_DATA[2]PPC405.TSTISOCMRDATAI13
CELL_W[2].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS55
CELL_W[2].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS55
CELL_W[2].IMUX_G3_DATA[2]PPC405.TSTISOCMABUSI2
CELL_W[2].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS52
CELL_W[2].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS53
CELL_W[2].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS54
CELL_W[2].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS55
CELL_W[2].OUT_FAN_TMIN[4]PPC405.C405PLBDCUGUARDED
CELL_W[2].OUT_FAN_TMIN[5]PPC405.C405PLBDCUWRITETHRU
CELL_W[2].OUT_FAN_TMIN[6]PPC405.C405DBGWBIAR11
CELL_W[2].OUT_FAN_TMIN[7]PPC405.C405DBGWBIAR12
CELL_W[2].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDDVALIDO1
CELL_W[2].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDDVALIDO0
CELL_W[2].OUT_SEC_TMIN[10]PPC405.TSTISOCMHOLDO
CELL_W[2].OUT_SEC_TMIN[11]PPC405.C405DBGWBIAR28
CELL_W[2].OUT_SEC_TMIN[12]PPC405.C405PLBICUABORT
CELL_W[2].OUT_SEC_TMIN[13]PPC405.C405PLBICUPRIORITY1
CELL_W[2].OUT_SEC_TMIN[14]PPC405.C405PLBICUPRIORITY0
CELL_W[2].OUT_SEC_TMIN[15]PPC405.C405PLBICUREQUEST
CELL_W[2].OUT_TEST[0]PPC405.TSTISOCMRDATAO0
CELL_W[2].OUT_TEST[2]PPC405.TSTISOCMRDATAO57
CELL_W[2].OUT_TEST[4]PPC405.TSTISOCMRDATAO58
CELL_W[3].IMUX_CLK[0]PPC405.CPMC405TIMERTICK
CELL_W[3].IMUX_CE[0]PPC405.CPMC405JTAGCLKEN
CELL_W[3].IMUX_TI[0]PPC405.TIEC405PVR23
CELL_W[3].IMUX_TI[1]PPC405.TIEC405PVR24
CELL_W[3].IMUX_TS[0]PPC405.TIEC405PVR25
CELL_W[3].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS48
CELL_W[3].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS48
CELL_W[3].IMUX_G0_DATA[2]PPC405.TSTISOCMRDDVALIDI0
CELL_W[3].IMUX_G0_DATA[3]PPC405.TSTISOCMABUSI7
CELL_W[3].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS49
CELL_W[3].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS49
CELL_W[3].IMUX_G1_DATA[2]PPC405.TSTISOCMRDATAI14
CELL_W[3].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS50
CELL_W[3].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS50
CELL_W[3].IMUX_G2_DATA[2]PPC405.TSTISOCMABUSI5
CELL_W[3].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS51
CELL_W[3].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS51
CELL_W[3].IMUX_G3_DATA[2]PPC405.TSTISOCMABUSI6
CELL_W[3].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS48
CELL_W[3].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS49
CELL_W[3].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS50
CELL_W[3].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS51
CELL_W[3].OUT_FAN_TMIN[4]PPC405.C405PLBDCUBE4
CELL_W[3].OUT_FAN_TMIN[5]PPC405.C405PLBDCUBE5
CELL_W[3].OUT_FAN_TMIN[6]PPC405.C405PLBDCUBE6
CELL_W[3].OUT_FAN_TMIN[7]PPC405.C405PLBDCUBE7
CELL_W[3].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO3
CELL_W[3].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO2
CELL_W[3].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO1
CELL_W[3].OUT_SEC_TMIN[11]PPC405.C405DBGWBIAR29
CELL_W[3].OUT_SEC_TMIN[12]PPC405.C405DBGWBIAR16
CELL_W[3].OUT_SEC_TMIN[13]PPC405.C405DBGWBIAR15
CELL_W[3].OUT_SEC_TMIN[14]PPC405.C405DBGWBIAR14
CELL_W[3].OUT_SEC_TMIN[15]PPC405.C405DBGWBIAR13
CELL_W[3].OUT_TEST[0]PPC405.TSTISOCMRDATAO4
CELL_W[3].OUT_TEST[2]PPC405.TSTISOCMRDATAO59
CELL_W[3].OUT_TEST[4]PPC405.TSTISOCMRDATAO60
CELL_W[4].IMUX_TI[0]PPC405.MCBCPUCLKEN
CELL_W[4].IMUX_TI[1]PPC405.TIEC405PVR20
CELL_W[4].IMUX_TS[0]PPC405.TIEC405PVR21
CELL_W[4].IMUX_TS[1]PPC405.TIEC405PVR22
CELL_W[4].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS44
CELL_W[4].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS44
CELL_W[4].IMUX_G0_DATA[2]PPC405.DBGC405EXTBUSHOLDACK
CELL_W[4].IMUX_G0_DATA[3]PPC405.TSTISOCMABUSI9
CELL_W[4].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS45
CELL_W[4].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS45
CELL_W[4].IMUX_G1_DATA[2]PPC405.TSTISOCMRDDVALIDI1
CELL_W[4].IMUX_G1_DATA[3]PPC405.TSTISOCMABUSI10
CELL_W[4].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS46
CELL_W[4].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS46
CELL_W[4].IMUX_G2_DATA[2]PPC405.TSTISOCMRDATAI15
CELL_W[4].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS47
CELL_W[4].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS47
CELL_W[4].IMUX_G3_DATA[2]PPC405.TSTISOCMABUSI8
CELL_W[4].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS44
CELL_W[4].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS45
CELL_W[4].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS46
CELL_W[4].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS47
CELL_W[4].OUT_FAN_TMIN[4]PPC405.C405PLBDCUABUS28
CELL_W[4].OUT_FAN_TMIN[5]PPC405.C405PLBDCUABUS29
CELL_W[4].OUT_FAN_TMIN[6]PPC405.C405PLBDCUABUS30
CELL_W[4].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABUS31
CELL_W[4].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO8
CELL_W[4].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO7
CELL_W[4].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO6
CELL_W[4].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO5
CELL_W[4].OUT_SEC_TMIN[12]PPC405.C405DBGWBIAR18
CELL_W[4].OUT_SEC_TMIN[13]PPC405.C405DBGWBIAR17
CELL_W[4].OUT_SEC_TMIN[14]PPC405.C405PLBICUABUS29
CELL_W[4].OUT_SEC_TMIN[15]PPC405.C405PLBICUABUS28
CELL_W[4].OUT_TEST[0]PPC405.TSTISOCMRDATAO61
CELL_W[4].OUT_TEST[2]PPC405.TSTISOCMRDATAO62
CELL_W[5].IMUX_TI[0]PPC405.MCBJTAGEN
CELL_W[5].IMUX_TI[1]PPC405.TIEC405PVR18
CELL_W[5].IMUX_TS[0]PPC405.TIEC405PVR19
CELL_W[5].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS40
CELL_W[5].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS40
CELL_W[5].IMUX_G0_DATA[2]PPC405.PLBC405DCUWRDACK
CELL_W[5].IMUX_G0_DATA[3]PPC405.TSTISOCMRDATAI16
CELL_W[5].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS41
CELL_W[5].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS41
CELL_W[5].IMUX_G1_DATA[2]PPC405.CPMC405CORECLKINACTIVE
CELL_W[5].IMUX_G1_DATA[3]PPC405.TSTISOCMABUSI11
CELL_W[5].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS42
CELL_W[5].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS42
CELL_W[5].IMUX_G2_DATA[2]PPC405.TSTRESETCOREI
CELL_W[5].IMUX_G2_DATA[3]PPC405.TSTISOCMABUSI12
CELL_W[5].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS43
CELL_W[5].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS43
CELL_W[5].IMUX_G3_DATA[2]PPC405.TSTISOCMRDATAI0
CELL_W[5].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS40
CELL_W[5].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS41
CELL_W[5].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS42
CELL_W[5].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS43
CELL_W[5].OUT_FAN_TMIN[4]PPC405.C405PLBDCUABUS24
CELL_W[5].OUT_FAN_TMIN[5]PPC405.C405PLBDCUABUS25
CELL_W[5].OUT_FAN_TMIN[6]PPC405.C405PLBDCUABUS26
CELL_W[5].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABUS27
CELL_W[5].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO12
CELL_W[5].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO11
CELL_W[5].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO10
CELL_W[5].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO9
CELL_W[5].OUT_SEC_TMIN[12]PPC405.C405PLBICUABUS27
CELL_W[5].OUT_SEC_TMIN[13]PPC405.C405PLBICUABUS26
CELL_W[5].OUT_SEC_TMIN[14]PPC405.C405PLBICUABUS25
CELL_W[5].OUT_SEC_TMIN[15]PPC405.C405PLBICUABUS24
CELL_W[5].OUT_TEST[0]PPC405.TSTISOCMRDATAO63
CELL_W[5].OUT_TEST[2]PPC405.TSTPLBSAMPLECYCLEO
CELL_W[6].IMUX_TI[0]PPC405.MCBTIMEREN
CELL_W[6].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS36
CELL_W[6].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS36
CELL_W[6].IMUX_G0_DATA[2]PPC405.PLBC405DCURDWDADDR1
CELL_W[6].IMUX_G0_DATA[3]PPC405.TSTISOCMRDATAI1
CELL_W[6].IMUX_G0_DATA[4]PPC405.TSTISOCMABUSI15
CELL_W[6].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS37
CELL_W[6].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS37
CELL_W[6].IMUX_G1_DATA[2]PPC405.PLBC405DCURDWDADDR2
CELL_W[6].IMUX_G1_DATA[3]PPC405.TSTPLBSAMPLECYCLEI
CELL_W[6].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS38
CELL_W[6].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS38
CELL_W[6].IMUX_G2_DATA[2]PPC405.PLBC405DCURDWDADDR3
CELL_W[6].IMUX_G2_DATA[3]PPC405.TSTISOCMABUSI13
CELL_W[6].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS39
CELL_W[6].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS39
CELL_W[6].IMUX_G3_DATA[2]PPC405.PLBC405DCURDDACK
CELL_W[6].IMUX_G3_DATA[3]PPC405.TSTISOCMABUSI14
CELL_W[6].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS36
CELL_W[6].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS37
CELL_W[6].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS38
CELL_W[6].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS39
CELL_W[6].OUT_FAN_TMIN[4]PPC405.C405PLBDCUABUS20
CELL_W[6].OUT_FAN_TMIN[5]PPC405.C405PLBDCUABUS21
CELL_W[6].OUT_FAN_TMIN[6]PPC405.C405PLBDCUABUS22
CELL_W[6].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABUS23
CELL_W[6].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO16
CELL_W[6].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO15
CELL_W[6].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO14
CELL_W[6].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO13
CELL_W[6].OUT_SEC_TMIN[12]PPC405.C405PLBICUABUS23
CELL_W[6].OUT_SEC_TMIN[13]PPC405.C405PLBICUABUS22
CELL_W[6].OUT_SEC_TMIN[14]PPC405.C405PLBICUABUS21
CELL_W[6].OUT_SEC_TMIN[15]PPC405.C405PLBICUABUS20
CELL_W[7].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS32
CELL_W[7].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS32
CELL_W[7].IMUX_G0_DATA[2]PPC405.PLBC405DCUADDRACK
CELL_W[7].IMUX_G0_DATA[3]PPC405.TSTISOCMRDATAI2
CELL_W[7].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS33
CELL_W[7].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS33
CELL_W[7].IMUX_G1_DATA[2]PPC405.PLBC405DCUSSIZE1
CELL_W[7].IMUX_G1_DATA[3]PPC405.TSTISOCMABUSI16
CELL_W[7].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS34
CELL_W[7].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS34
CELL_W[7].IMUX_G2_DATA[2]PPC405.PLBC405DCUBUSY
CELL_W[7].IMUX_G2_DATA[3]PPC405.TSTISOCMABUSI17
CELL_W[7].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS35
CELL_W[7].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS35
CELL_W[7].IMUX_G3_DATA[2]PPC405.PLBC405DCUERR
CELL_W[7].IMUX_G3_DATA[3]PPC405.TSTISOCMABUSI18
CELL_W[7].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS32
CELL_W[7].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS33
CELL_W[7].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS34
CELL_W[7].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS35
CELL_W[7].OUT_FAN_TMIN[4]PPC405.C405PLBDCUABUS16
CELL_W[7].OUT_FAN_TMIN[5]PPC405.C405PLBDCUABUS17
CELL_W[7].OUT_FAN_TMIN[6]PPC405.C405PLBDCUABUS18
CELL_W[7].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABUS19
CELL_W[7].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO20
CELL_W[7].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO19
CELL_W[7].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO18
CELL_W[7].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO17
CELL_W[7].OUT_SEC_TMIN[12]PPC405.C405PLBICUABUS19
CELL_W[7].OUT_SEC_TMIN[13]PPC405.C405PLBICUABUS18
CELL_W[7].OUT_SEC_TMIN[14]PPC405.C405PLBICUABUS17
CELL_W[7].OUT_SEC_TMIN[15]PPC405.C405PLBICUABUS16
CELL_W[8].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS28
CELL_W[8].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS28
CELL_W[8].IMUX_G0_DATA[2]PPC405.PLBC405ICUADDRACK
CELL_W[8].IMUX_G0_DATA[3]PPC405.TSTISOCMRDATAI3
CELL_W[8].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS29
CELL_W[8].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS29
CELL_W[8].IMUX_G1_DATA[2]PPC405.PLBC405ICUSSIZE1
CELL_W[8].IMUX_G1_DATA[3]PPC405.TSTISOCMABUSI19
CELL_W[8].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS30
CELL_W[8].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS30
CELL_W[8].IMUX_G2_DATA[2]PPC405.PLBC405ICUBUSY
CELL_W[8].IMUX_G2_DATA[3]PPC405.TSTISOCMABUSI20
CELL_W[8].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS31
CELL_W[8].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS31
CELL_W[8].IMUX_G3_DATA[2]PPC405.PLBC405ICUERR
CELL_W[8].IMUX_G3_DATA[3]PPC405.TSTISOCMABUSI21
CELL_W[8].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS28
CELL_W[8].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS29
CELL_W[8].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS30
CELL_W[8].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS31
CELL_W[8].OUT_FAN_TMIN[4]PPC405.C405PLBDCUABUS12
CELL_W[8].OUT_FAN_TMIN[5]PPC405.C405PLBDCUABUS13
CELL_W[8].OUT_FAN_TMIN[6]PPC405.C405PLBDCUABUS14
CELL_W[8].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABUS15
CELL_W[8].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO24
CELL_W[8].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO23
CELL_W[8].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO22
CELL_W[8].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO21
CELL_W[8].OUT_SEC_TMIN[12]PPC405.C405PLBICUABUS15
CELL_W[8].OUT_SEC_TMIN[13]PPC405.C405PLBICUABUS14
CELL_W[8].OUT_SEC_TMIN[14]PPC405.C405PLBICUABUS13
CELL_W[8].OUT_SEC_TMIN[15]PPC405.C405PLBICUABUS12
CELL_W[9].IMUX_CLK[0]PPC405.CPMC405CLOCK
CELL_W[9].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS24
CELL_W[9].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS24
CELL_W[9].IMUX_G0_DATA[2]PPC405.PLBC405ICURDWDADDR1
CELL_W[9].IMUX_G0_DATA[3]PPC405.TSTISOCMRDATAI4
CELL_W[9].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS25
CELL_W[9].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS25
CELL_W[9].IMUX_G1_DATA[2]PPC405.PLBC405ICURDWDADDR2
CELL_W[9].IMUX_G1_DATA[3]PPC405.TSTISOCMABUSI22
CELL_W[9].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS26
CELL_W[9].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS26
CELL_W[9].IMUX_G2_DATA[2]PPC405.PLBC405ICURDWDADDR3
CELL_W[9].IMUX_G2_DATA[3]PPC405.TSTISOCMABUSI23
CELL_W[9].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS27
CELL_W[9].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS27
CELL_W[9].IMUX_G3_DATA[2]PPC405.PLBC405ICURDDACK
CELL_W[9].IMUX_G3_DATA[3]PPC405.TSTISOCMABUSI24
CELL_W[9].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS24
CELL_W[9].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS25
CELL_W[9].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS26
CELL_W[9].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS27
CELL_W[9].OUT_FAN_TMIN[4]PPC405.C405PLBDCUABUS8
CELL_W[9].OUT_FAN_TMIN[5]PPC405.C405PLBDCUABUS9
CELL_W[9].OUT_FAN_TMIN[6]PPC405.C405PLBDCUABUS10
CELL_W[9].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABUS11
CELL_W[9].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO28
CELL_W[9].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO27
CELL_W[9].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO26
CELL_W[9].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO25
CELL_W[9].OUT_SEC_TMIN[12]PPC405.C405PLBICUABUS11
CELL_W[9].OUT_SEC_TMIN[13]PPC405.C405PLBICUABUS10
CELL_W[9].OUT_SEC_TMIN[14]PPC405.C405PLBICUABUS9
CELL_W[9].OUT_SEC_TMIN[15]PPC405.C405PLBICUABUS8
CELL_W[10].IMUX_TI[0]PPC405.TIEC405PVR15
CELL_W[10].IMUX_TI[1]PPC405.TIEC405PVR16
CELL_W[10].IMUX_TS[0]PPC405.TIEC405PVR17
CELL_W[10].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS20
CELL_W[10].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS20
CELL_W[10].IMUX_G0_DATA[2]PPC405.EICC405CRITINPUTIRQ
CELL_W[10].IMUX_G0_DATA[3]PPC405.TSTISOCMABUSI27
CELL_W[10].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS21
CELL_W[10].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS21
CELL_W[10].IMUX_G1_DATA[2]PPC405.TSTISOCMRDATAI5
CELL_W[10].IMUX_G1_DATA[3]PPC405.TSTISOCMABUSI28
CELL_W[10].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS22
CELL_W[10].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS22
CELL_W[10].IMUX_G2_DATA[2]PPC405.TSTISOCMABUSI25
CELL_W[10].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS23
CELL_W[10].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS23
CELL_W[10].IMUX_G3_DATA[2]PPC405.TSTISOCMABUSI26
CELL_W[10].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS20
CELL_W[10].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS21
CELL_W[10].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS22
CELL_W[10].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS23
CELL_W[10].OUT_FAN_TMIN[4]PPC405.C405PLBDCUABUS4
CELL_W[10].OUT_FAN_TMIN[5]PPC405.C405PLBDCUABUS5
CELL_W[10].OUT_FAN_TMIN[6]PPC405.C405PLBDCUABUS6
CELL_W[10].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABUS7
CELL_W[10].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO32
CELL_W[10].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO31
CELL_W[10].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO30
CELL_W[10].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO29
CELL_W[10].OUT_SEC_TMIN[12]PPC405.C405PLBICUABUS7
CELL_W[10].OUT_SEC_TMIN[13]PPC405.C405PLBICUABUS6
CELL_W[10].OUT_SEC_TMIN[14]PPC405.C405PLBICUABUS5
CELL_W[10].OUT_SEC_TMIN[15]PPC405.C405PLBICUABUS4
CELL_W[11].IMUX_SR[0]PPC405.RSTC405RESETCHIP
CELL_W[11].IMUX_TI[0]PPC405.TIEC405PVR12
CELL_W[11].IMUX_TI[1]PPC405.TIEC405PVR13
CELL_W[11].IMUX_TS[0]PPC405.TIEC405PVR14
CELL_W[11].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS16
CELL_W[11].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS16
CELL_W[11].IMUX_G0_DATA[2]PPC405.TSTRESETSYSI
CELL_W[11].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS17
CELL_W[11].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS17
CELL_W[11].IMUX_G1_DATA[2]PPC405.TSTISOCMRDATAI6
CELL_W[11].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS18
CELL_W[11].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS18
CELL_W[11].IMUX_G2_DATA[2]PPC405.TSTISOCMABUSI29
CELL_W[11].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS19
CELL_W[11].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS19
CELL_W[11].IMUX_G3_DATA[2]PPC405.TSTISOCMABORTI
CELL_W[11].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS16
CELL_W[11].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS17
CELL_W[11].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS18
CELL_W[11].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS19
CELL_W[11].OUT_FAN_TMIN[4]PPC405.C405PLBDCUABUS0
CELL_W[11].OUT_FAN_TMIN[5]PPC405.C405PLBDCUABUS1
CELL_W[11].OUT_FAN_TMIN[6]PPC405.C405PLBDCUABUS2
CELL_W[11].OUT_FAN_TMIN[7]PPC405.C405PLBDCUABUS3
CELL_W[11].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO36
CELL_W[11].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO35
CELL_W[11].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO34
CELL_W[11].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO33
CELL_W[11].OUT_SEC_TMIN[12]PPC405.C405PLBICUABUS3
CELL_W[11].OUT_SEC_TMIN[13]PPC405.C405PLBICUABUS2
CELL_W[11].OUT_SEC_TMIN[14]PPC405.C405PLBICUABUS1
CELL_W[11].OUT_SEC_TMIN[15]PPC405.C405PLBICUABUS0
CELL_W[12].IMUX_SR[0]PPC405.RSTC405RESETCORE
CELL_W[12].IMUX_TI[0]PPC405.TIEC405PVR9
CELL_W[12].IMUX_TI[1]PPC405.TIEC405PVR10
CELL_W[12].IMUX_TS[0]PPC405.TIEC405PVR11
CELL_W[12].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS12
CELL_W[12].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS12
CELL_W[12].IMUX_G0_DATA[2]PPC405.TSTJTAGENI
CELL_W[12].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS13
CELL_W[12].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS13
CELL_W[12].IMUX_G1_DATA[2]PPC405.TSTISOCMRDATAI7
CELL_W[12].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS14
CELL_W[12].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS14
CELL_W[12].IMUX_G2_DATA[2]PPC405.JTGC405TRSTNEG
CELL_W[12].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS15
CELL_W[12].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS15
CELL_W[12].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS12
CELL_W[12].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS13
CELL_W[12].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS14
CELL_W[12].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS15
CELL_W[12].OUT_FAN_TMIN[4]PPC405.C405PLBDCUSIZE2
CELL_W[12].OUT_FAN_TMIN[5]PPC405.C405PLBDCUU0ATTR
CELL_W[12].OUT_FAN_TMIN[6]PPC405.C405PLBDCUCACHEABLE
CELL_W[12].OUT_FAN_TMIN[7]PPC405.C405DBGWBIAR19
CELL_W[12].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO40
CELL_W[12].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO39
CELL_W[12].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO38
CELL_W[12].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO37
CELL_W[12].OUT_SEC_TMIN[12]PPC405.C405PLBICUCACHEABLE
CELL_W[12].OUT_SEC_TMIN[13]PPC405.C405PLBICUU0ATTR
CELL_W[12].OUT_SEC_TMIN[14]PPC405.C405PLBICUSIZE3
CELL_W[12].OUT_SEC_TMIN[15]PPC405.C405PLBICUSIZE2
CELL_W[12].OUT_TEST[0]PPC405.TSTTRSTNEGO
CELL_W[13].IMUX_SR[0]PPC405.RSTC405RESETSYS
CELL_W[13].IMUX_TI[0]PPC405.TIEC405PVR6
CELL_W[13].IMUX_TI[1]PPC405.TIEC405PVR7
CELL_W[13].IMUX_TS[0]PPC405.TIEC405PVR8
CELL_W[13].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS8
CELL_W[13].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS8
CELL_W[13].IMUX_G0_DATA[2]PPC405.TSTTIMERENI
CELL_W[13].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS9
CELL_W[13].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS9
CELL_W[13].IMUX_G1_DATA[2]PPC405.TSTISOCMRDATAI8
CELL_W[13].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS10
CELL_W[13].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS10
CELL_W[13].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS11
CELL_W[13].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS11
CELL_W[13].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS8
CELL_W[13].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS9
CELL_W[13].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS10
CELL_W[13].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS11
CELL_W[13].OUT_FAN_TMIN[4]PPC405.C405PLBDCUBE0
CELL_W[13].OUT_FAN_TMIN[5]PPC405.C405PLBDCUBE1
CELL_W[13].OUT_FAN_TMIN[6]PPC405.C405PLBDCUBE2
CELL_W[13].OUT_FAN_TMIN[7]PPC405.C405PLBDCUBE3
CELL_W[13].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO44
CELL_W[13].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO43
CELL_W[13].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO42
CELL_W[13].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO41
CELL_W[13].OUT_SEC_TMIN[12]PPC405.C405DBGWBIAR23
CELL_W[13].OUT_SEC_TMIN[13]PPC405.C405DBGWBIAR9
CELL_W[13].OUT_SEC_TMIN[14]PPC405.C405DBGWBIAR2
CELL_W[13].OUT_SEC_TMIN[15]PPC405.C405DBGWBIAR1
CELL_W[14].IMUX_TI[0]PPC405.MCPPCRST
CELL_W[14].IMUX_TI[1]PPC405.TIEC405PVR3
CELL_W[14].IMUX_TS[0]PPC405.TIEC405PVR4
CELL_W[14].IMUX_TS[1]PPC405.TIEC405PVR5
CELL_W[14].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS4
CELL_W[14].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS4
CELL_W[14].IMUX_G0_DATA[2]PPC405.TSTCPUCLKENI
CELL_W[14].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS5
CELL_W[14].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS5
CELL_W[14].IMUX_G1_DATA[2]PPC405.TSTISOCMRDATAI9
CELL_W[14].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS6
CELL_W[14].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS6
CELL_W[14].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS7
CELL_W[14].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS7
CELL_W[14].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS4
CELL_W[14].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS5
CELL_W[14].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS6
CELL_W[14].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS7
CELL_W[14].OUT_FAN_TMIN[4]PPC405.C405RSTSYSRESETREQ
CELL_W[14].OUT_FAN_TMIN[5]PPC405.C405CPMCORESLEEPREQ
CELL_W[14].OUT_FAN_TMIN[6]PPC405.C405XXXMACHINECHECK
CELL_W[14].OUT_FAN_TMIN[7]PPC405.C405DBGLOADDATAONAPUDBUS
CELL_W[14].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO48
CELL_W[14].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO47
CELL_W[14].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO46
CELL_W[14].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO45
CELL_W[14].OUT_SEC_TMIN[12]PPC405.C405DBGWBIAR24
CELL_W[14].OUT_SEC_TMIN[13]PPC405.C405DBGWBIAR10
CELL_W[14].OUT_SEC_TMIN[14]PPC405.C405DBGWBIAR4
CELL_W[14].OUT_SEC_TMIN[15]PPC405.C405DBGWBIAR3
CELL_W[15].IMUX_TI[0]PPC405.TIEC405PVR0
CELL_W[15].IMUX_TI[1]PPC405.TIEC405PVR1
CELL_W[15].IMUX_TS[0]PPC405.TIEC405PVR2
CELL_W[15].IMUX_G0_DATA[0]PPC405.PLBC405DCURDDBUS0
CELL_W[15].IMUX_G0_DATA[1]PPC405.PLBC405ICURDDBUS0
CELL_W[15].IMUX_G0_DATA[2]PPC405.EICC405EXTINPUTIRQ
CELL_W[15].IMUX_G1_DATA[0]PPC405.PLBC405DCURDDBUS1
CELL_W[15].IMUX_G1_DATA[1]PPC405.PLBC405ICURDDBUS1
CELL_W[15].IMUX_G1_DATA[2]PPC405.TSTISOCMRDATAI10
CELL_W[15].IMUX_G2_DATA[0]PPC405.PLBC405DCURDDBUS2
CELL_W[15].IMUX_G2_DATA[1]PPC405.PLBC405ICURDDBUS2
CELL_W[15].IMUX_G3_DATA[0]PPC405.PLBC405DCURDDBUS3
CELL_W[15].IMUX_G3_DATA[1]PPC405.PLBC405ICURDDBUS3
CELL_W[15].OUT_FAN_TMIN[0]PPC405.C405PLBDCUWRDBUS0
CELL_W[15].OUT_FAN_TMIN[1]PPC405.C405PLBDCUWRDBUS1
CELL_W[15].OUT_FAN_TMIN[2]PPC405.C405PLBDCUWRDBUS2
CELL_W[15].OUT_FAN_TMIN[3]PPC405.C405PLBDCUWRDBUS3
CELL_W[15].OUT_FAN_TMIN[4]PPC405.C405CPMMSRCE
CELL_W[15].OUT_FAN_TMIN[5]PPC405.C405CPMMSREE
CELL_W[15].OUT_FAN_TMIN[6]PPC405.C405DBGMSRWE
CELL_W[15].OUT_FAN_TMIN[7]PPC405.C405DBGSTOPACK
CELL_W[15].OUT_SEC_TMIN[8]PPC405.TSTISOCMRDATAO52
CELL_W[15].OUT_SEC_TMIN[9]PPC405.TSTISOCMRDATAO51
CELL_W[15].OUT_SEC_TMIN[10]PPC405.TSTISOCMRDATAO50
CELL_W[15].OUT_SEC_TMIN[11]PPC405.TSTISOCMRDATAO49
CELL_W[15].OUT_SEC_TMIN[12]PPC405.C405DBGWBIAR25
CELL_W[15].OUT_SEC_TMIN[13]PPC405.C405DBGWBIAR20
CELL_W[15].OUT_SEC_TMIN[14]PPC405.C405DBGWBIAR6
CELL_W[15].OUT_SEC_TMIN[15]PPC405.C405DBGWBIAR5
CELL_E[0].IMUX_G0_DATA[0]PPC405.APUC405DCDAPUOP
CELL_E[0].IMUX_G0_DATA[1]PPC405.APUC405EXERESULT21
CELL_E[0].IMUX_G0_DATA[2]PPC405.TSTDCRBUSI14
CELL_E[0].IMUX_G0_DATA[3]PPC405.TSTC405DCRABUSI0
CELL_E[0].IMUX_G0_DATA[4]PPC405.TSTDSOCMABUSI8
CELL_E[0].IMUX_G1_DATA[0]PPC405.APUC405DCDCREN
CELL_E[0].IMUX_G1_DATA[1]PPC405.APUC405EXERESULT22
CELL_E[0].IMUX_G1_DATA[2]PPC405.TSTDCRBUSI15
CELL_E[0].IMUX_G1_DATA[3]PPC405.TSTC405DCRABUSI1
CELL_E[0].IMUX_G1_DATA[4]PPC405.TSTDSOCMABUSI9
CELL_E[0].IMUX_G2_DATA[0]PPC405.APUC405DCDFORCEALGN
CELL_E[0].IMUX_G2_DATA[1]PPC405.DCRC405DBUSIN14
CELL_E[0].IMUX_G2_DATA[2]PPC405.TSTRDDBUSI11
CELL_E[0].IMUX_G2_DATA[3]PPC405.TSTC405DCRDBUSOUTI21
CELL_E[0].IMUX_G2_DATA[4]PPC405.TSTDSOCMWRDBUSI3
CELL_E[0].IMUX_G3_DATA[0]PPC405.APUC405DCDFORCEBESTEERING
CELL_E[0].IMUX_G3_DATA[1]PPC405.DCRC405DBUSIN15
CELL_E[0].IMUX_G3_DATA[2]PPC405.TSTRDDBUSI12
CELL_E[0].IMUX_G3_DATA[3]PPC405.TSTC405DCRDBUSOUTI22
CELL_E[0].IMUX_G3_DATA[4]PPC405.TSTDSOCMWRDBUSI4
CELL_E[0].OUT_FAN_TMIN[0]PPC405.C405APUDCDFULL
CELL_E[0].OUT_FAN_TMIN[1]PPC405.C405APUDCDHOLD
CELL_E[0].OUT_FAN_TMIN[2]PPC405.C405APUDCDINSTRUCTION0
CELL_E[0].OUT_FAN_TMIN[3]PPC405.C405APUDCDINSTRUCTION1
CELL_E[0].OUT_FAN_TMIN[4]PPC405.C405APUEXELOADDBUS28
CELL_E[0].OUT_FAN_TMIN[5]PPC405.C405APUEXELOADDBUS29
CELL_E[0].OUT_FAN_TMIN[6]PPC405.C405APUEXERADATA27
CELL_E[0].OUT_FAN_TMIN[7]PPC405.C405APUEXERADATA28
CELL_E[0].OUT_SEC_TMIN[8]PPC405.TSTDCRBUSO1
CELL_E[0].OUT_SEC_TMIN[9]PPC405.TSTDCRBUSO0
CELL_E[0].OUT_SEC_TMIN[10]PPC405.TSTDCRACKO
CELL_E[0].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO25
CELL_E[0].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT21
CELL_E[0].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT5
CELL_E[0].OUT_SEC_TMIN[14]PPC405.C405APUEXERBDATA28
CELL_E[0].OUT_SEC_TMIN[15]PPC405.C405APUEXERBDATA27
CELL_E[0].OUT_TEST[0]PPC405.TSTDCRBUSO2
CELL_E[0].OUT_TEST[2]PPC405.TSTRDDBUSO22
CELL_E[0].OUT_TEST[4]PPC405.TSTRDDBUSO23
CELL_E[1].IMUX_G0_DATA[0]PPC405.APUC405DCDFPUOP
CELL_E[1].IMUX_G0_DATA[1]PPC405.APUC405EXERESULT23
CELL_E[1].IMUX_G0_DATA[2]PPC405.TSTDCRBUSI16
CELL_E[1].IMUX_G0_DATA[3]PPC405.TSTC405DCRABUSI2
CELL_E[1].IMUX_G0_DATA[4]PPC405.TSTDSOCMABUSI10
CELL_E[1].IMUX_G1_DATA[0]PPC405.APUC405DCDGPRWRITE
CELL_E[1].IMUX_G1_DATA[1]PPC405.APUC405EXERESULT24
CELL_E[1].IMUX_G1_DATA[2]PPC405.TSTDCRBUSI17
CELL_E[1].IMUX_G1_DATA[3]PPC405.TSTC405DCRABUSI3
CELL_E[1].IMUX_G1_DATA[4]PPC405.TSTDSOCMABUSI11
CELL_E[1].IMUX_G2_DATA[0]PPC405.APUC405DCDLDSTBYTE
CELL_E[1].IMUX_G2_DATA[1]PPC405.DCRC405DBUSIN16
CELL_E[1].IMUX_G2_DATA[2]PPC405.TSTRDDBUSI13
CELL_E[1].IMUX_G2_DATA[3]PPC405.TSTC405DCRDBUSOUTI23
CELL_E[1].IMUX_G2_DATA[4]PPC405.TSTDSOCMWRDBUSI5
CELL_E[1].IMUX_G3_DATA[0]PPC405.APUC405DCDLDSTDW
CELL_E[1].IMUX_G3_DATA[1]PPC405.DCRC405DBUSIN17
CELL_E[1].IMUX_G3_DATA[2]PPC405.TSTRDDBUSI14
CELL_E[1].IMUX_G3_DATA[3]PPC405.TSTC405DCRDBUSOUTI24
CELL_E[1].IMUX_G3_DATA[4]PPC405.TSTDSOCMWRDBUSI6
CELL_E[1].OUT_FAN_TMIN[0]PPC405.C405APUDCDINSTRUCTION2
CELL_E[1].OUT_FAN_TMIN[1]PPC405.C405APUDCDINSTRUCTION3
CELL_E[1].OUT_FAN_TMIN[2]PPC405.C405APUDCDINSTRUCTION4
CELL_E[1].OUT_FAN_TMIN[3]PPC405.C405APUDCDINSTRUCTION5
CELL_E[1].OUT_FAN_TMIN[4]PPC405.C405APUEXELOADDBUS30
CELL_E[1].OUT_FAN_TMIN[5]PPC405.C405APUEXELOADDBUS31
CELL_E[1].OUT_FAN_TMIN[6]PPC405.C405APUEXERADATA29
CELL_E[1].OUT_FAN_TMIN[7]PPC405.C405APUEXERADATA30
CELL_E[1].OUT_SEC_TMIN[8]PPC405.TSTDCRBUSO5
CELL_E[1].OUT_SEC_TMIN[9]PPC405.TSTDCRBUSO4
CELL_E[1].OUT_SEC_TMIN[10]PPC405.TSTDCRBUSO3
CELL_E[1].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO26
CELL_E[1].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT22
CELL_E[1].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT6
CELL_E[1].OUT_SEC_TMIN[14]PPC405.C405APUEXERBDATA30
CELL_E[1].OUT_SEC_TMIN[15]PPC405.C405APUEXERBDATA29
CELL_E[1].OUT_TEST[0]PPC405.TSTDCRBUSO6
CELL_E[1].OUT_TEST[2]PPC405.TSTRDDBUSO24
CELL_E[1].OUT_TEST[4]PPC405.TSTRDDBUSO25
CELL_E[2].IMUX_G0_DATA[0]PPC405.APUC405DCDLDSTHW
CELL_E[2].IMUX_G0_DATA[1]PPC405.APUC405EXERESULT25
CELL_E[2].IMUX_G0_DATA[2]PPC405.TSTDCRBUSI18
CELL_E[2].IMUX_G0_DATA[3]PPC405.TSTC405DCRABUSI4
CELL_E[2].IMUX_G0_DATA[4]PPC405.TSTDSOCMABUSI12
CELL_E[2].IMUX_G1_DATA[0]PPC405.APUC405DCDLDSTQW
CELL_E[2].IMUX_G1_DATA[1]PPC405.APUC405EXERESULT26
CELL_E[2].IMUX_G1_DATA[2]PPC405.TSTDCRBUSI19
CELL_E[2].IMUX_G1_DATA[3]PPC405.TSTC405DCRABUSI5
CELL_E[2].IMUX_G1_DATA[4]PPC405.TSTDSOCMABUSI13
CELL_E[2].IMUX_G2_DATA[0]PPC405.APUC405DCDLDSTWD
CELL_E[2].IMUX_G2_DATA[1]PPC405.DCRC405DBUSIN18
CELL_E[2].IMUX_G2_DATA[2]PPC405.TSTRDDBUSI15
CELL_E[2].IMUX_G2_DATA[3]PPC405.TSTC405DCRDBUSOUTI25
CELL_E[2].IMUX_G2_DATA[4]PPC405.TSTDSOCMWRDBUSI7
CELL_E[2].IMUX_G3_DATA[0]PPC405.APUC405DCDLOAD
CELL_E[2].IMUX_G3_DATA[1]PPC405.DCRC405DBUSIN19
CELL_E[2].IMUX_G3_DATA[2]PPC405.TSTRDDBUSI16
CELL_E[2].IMUX_G3_DATA[3]PPC405.TSTC405DCRDBUSOUTI26
CELL_E[2].IMUX_G3_DATA[4]PPC405.TSTDSOCMWRDBUSI8
CELL_E[2].OUT_FAN_TMIN[0]PPC405.C405APUDCDINSTRUCTION6
CELL_E[2].OUT_FAN_TMIN[1]PPC405.C405APUDCDINSTRUCTION7
CELL_E[2].OUT_FAN_TMIN[2]PPC405.C405APUDCDINSTRUCTION8
CELL_E[2].OUT_FAN_TMIN[3]PPC405.C405APUDCDINSTRUCTION9
CELL_E[2].OUT_FAN_TMIN[4]PPC405.C405APUEXELOADDVALID
CELL_E[2].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA0
CELL_E[2].OUT_FAN_TMIN[6]PPC405.C405APUEXERADATA31
CELL_E[2].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA0
CELL_E[2].OUT_SEC_TMIN[8]PPC405.TSTDCRBUSO9
CELL_E[2].OUT_SEC_TMIN[9]PPC405.TSTDCRBUSO8
CELL_E[2].OUT_SEC_TMIN[10]PPC405.TSTDCRBUSO7
CELL_E[2].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO27
CELL_E[2].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT23
CELL_E[2].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT7
CELL_E[2].OUT_SEC_TMIN[14]PPC405.C405APUEXEWDCNT0
CELL_E[2].OUT_SEC_TMIN[15]PPC405.C405APUEXERBDATA31
CELL_E[2].OUT_TEST[0]PPC405.TSTDCRBUSO10
CELL_E[2].OUT_TEST[2]PPC405.TSTRDDBUSO26
CELL_E[2].OUT_TEST[4]PPC405.TSTRDDBUSO27
CELL_E[3].IMUX_G0_DATA[0]PPC405.APUC405DCDPRIVOP
CELL_E[3].IMUX_G0_DATA[1]PPC405.APUC405EXERESULT27
CELL_E[3].IMUX_G0_DATA[2]PPC405.TSTDCRBUSI20
CELL_E[3].IMUX_G0_DATA[3]PPC405.TSTC405DCRABUSI6
CELL_E[3].IMUX_G0_DATA[4]PPC405.TSTDSOCMABUSI14
CELL_E[3].IMUX_G1_DATA[0]PPC405.APUC405DCDRAEN
CELL_E[3].IMUX_G1_DATA[1]PPC405.APUC405EXERESULT28
CELL_E[3].IMUX_G1_DATA[2]PPC405.TSTDCRBUSI21
CELL_E[3].IMUX_G1_DATA[3]PPC405.TSTC405DCRABUSI7
CELL_E[3].IMUX_G1_DATA[4]PPC405.TSTDSOCMABUSI15
CELL_E[3].IMUX_G2_DATA[0]PPC405.APUC405DCDRBEN
CELL_E[3].IMUX_G2_DATA[1]PPC405.DCRC405DBUSIN20
CELL_E[3].IMUX_G2_DATA[2]PPC405.TSTRDDBUSI17
CELL_E[3].IMUX_G2_DATA[3]PPC405.TSTC405DCRDBUSOUTI27
CELL_E[3].IMUX_G2_DATA[4]PPC405.TSTDSOCMWRDBUSI9
CELL_E[3].IMUX_G3_DATA[0]PPC405.APUC405DCDSTORE
CELL_E[3].IMUX_G3_DATA[1]PPC405.DCRC405DBUSIN21
CELL_E[3].IMUX_G3_DATA[2]PPC405.TSTRDDBUSI18
CELL_E[3].IMUX_G3_DATA[3]PPC405.TSTC405DCRDBUSOUTI28
CELL_E[3].IMUX_G3_DATA[4]PPC405.TSTDSOCMWRDBUSI10
CELL_E[3].OUT_FAN_TMIN[0]PPC405.C405APUDCDINSTRUCTION10
CELL_E[3].OUT_FAN_TMIN[1]PPC405.C405APUDCDINSTRUCTION11
CELL_E[3].OUT_FAN_TMIN[2]PPC405.C405APUDCDINSTRUCTION12
CELL_E[3].OUT_FAN_TMIN[3]PPC405.C405APUDCDINSTRUCTION13
CELL_E[3].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA1
CELL_E[3].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA2
CELL_E[3].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA1
CELL_E[3].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA2
CELL_E[3].OUT_SEC_TMIN[8]PPC405.TSTDCRBUSO13
CELL_E[3].OUT_SEC_TMIN[9]PPC405.TSTDCRBUSO12
CELL_E[3].OUT_SEC_TMIN[10]PPC405.TSTDCRBUSO11
CELL_E[3].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO28
CELL_E[3].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT24
CELL_E[3].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT8
CELL_E[3].OUT_SEC_TMIN[14]PPC405.C405APUMSRFE0
CELL_E[3].OUT_SEC_TMIN[15]PPC405.C405APUEXEWDCNT1
CELL_E[3].OUT_TEST[0]PPC405.TSTDCRBUSO14
CELL_E[3].OUT_TEST[2]PPC405.TSTRDDBUSO28
CELL_E[3].OUT_TEST[4]PPC405.TSTRDDBUSO29
CELL_E[4].IMUX_TI[0]PPC405.TIEC405APUDIVEN
CELL_E[4].IMUX_TI[1]PPC405.TIEC405APUPRESENT
CELL_E[4].IMUX_G0_DATA[0]PPC405.APUC405DCDTRAPBE
CELL_E[4].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN22
CELL_E[4].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI19
CELL_E[4].IMUX_G0_DATA[3]PPC405.TSTC405DCRDBUSOUTI29
CELL_E[4].IMUX_G0_DATA[4]PPC405.TSTDSOCMWRDBUSI11
CELL_E[4].IMUX_G1_DATA[0]PPC405.APUC405DCDTRAPLE
CELL_E[4].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN23
CELL_E[4].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI20
CELL_E[4].IMUX_G1_DATA[3]PPC405.TSTC405DCRDBUSOUTI30
CELL_E[4].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI12
CELL_E[4].IMUX_G2_DATA[0]PPC405.APUC405EXERESULT29
CELL_E[4].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI22
CELL_E[4].IMUX_G2_DATA[2]PPC405.TSTC405DCRABUSI8
CELL_E[4].IMUX_G2_DATA[3]PPC405.TSTDSOCMABUSI16
CELL_E[4].IMUX_G3_DATA[0]PPC405.APUC405EXERESULT30
CELL_E[4].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI23
CELL_E[4].IMUX_G3_DATA[2]PPC405.TSTC405DCRABUSI9
CELL_E[4].IMUX_G3_DATA[3]PPC405.TSTDSOCMABUSI17
CELL_E[4].OUT_FAN_TMIN[0]PPC405.C405APUDCDINSTRUCTION14
CELL_E[4].OUT_FAN_TMIN[1]PPC405.C405APUDCDINSTRUCTION15
CELL_E[4].OUT_FAN_TMIN[2]PPC405.C405APUDCDINSTRUCTION16
CELL_E[4].OUT_FAN_TMIN[3]PPC405.C405APUDCDINSTRUCTION17
CELL_E[4].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA3
CELL_E[4].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA4
CELL_E[4].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA3
CELL_E[4].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA4
CELL_E[4].OUT_SEC_TMIN[8]PPC405.TSTDCRBUSO17
CELL_E[4].OUT_SEC_TMIN[9]PPC405.TSTDCRBUSO16
CELL_E[4].OUT_SEC_TMIN[10]PPC405.TSTDCRBUSO15
CELL_E[4].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO29
CELL_E[4].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT25
CELL_E[4].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT9
CELL_E[4].OUT_SEC_TMIN[14]PPC405.C405APUWBBYTEEN0
CELL_E[4].OUT_SEC_TMIN[15]PPC405.C405APUMSRFE1
CELL_E[4].OUT_TEST[0]PPC405.TSTDCRBUSO18
CELL_E[4].OUT_TEST[2]PPC405.TSTRDDBUSO30
CELL_E[4].OUT_TEST[4]PPC405.TSTRDDBUSO31
CELL_E[5].IMUX_TI[0]PPC405.TIEUTLBTAP1
CELL_E[5].IMUX_TI[1]PPC405.TIEUTLBTAP2
CELL_E[5].IMUX_G0_DATA[0]PPC405.APUC405DCDUPDATE
CELL_E[5].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN24
CELL_E[5].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI21
CELL_E[5].IMUX_G0_DATA[3]PPC405.TSTC405DCRDBUSOUTI31
CELL_E[5].IMUX_G0_DATA[4]PPC405.TSTDSOCMWRDBUSI13
CELL_E[5].IMUX_G1_DATA[0]PPC405.APUC405DCDVALIDOP
CELL_E[5].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN25
CELL_E[5].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI22
CELL_E[5].IMUX_G1_DATA[3]PPC405.TSTC405DCRREADI
CELL_E[5].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI14
CELL_E[5].IMUX_G2_DATA[0]PPC405.APUC405EXERESULT31
CELL_E[5].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI24
CELL_E[5].IMUX_G2_DATA[2]PPC405.TSTC405DCRDBUSOUTI0
CELL_E[5].IMUX_G2_DATA[3]PPC405.TSTDSOCMABUSI18
CELL_E[5].IMUX_G3_DATA[0]PPC405.APUC405EXEXERCA
CELL_E[5].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI25
CELL_E[5].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI1
CELL_E[5].IMUX_G3_DATA[3]PPC405.TSTDSOCMABUSI19
CELL_E[5].OUT_FAN_TMIN[0]PPC405.C405APUDCDINSTRUCTION18
CELL_E[5].OUT_FAN_TMIN[1]PPC405.C405APUDCDINSTRUCTION19
CELL_E[5].OUT_FAN_TMIN[2]PPC405.C405APUDCDINSTRUCTION20
CELL_E[5].OUT_FAN_TMIN[3]PPC405.C405APUDCDINSTRUCTION21
CELL_E[5].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA5
CELL_E[5].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA6
CELL_E[5].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA5
CELL_E[5].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA6
CELL_E[5].OUT_SEC_TMIN[8]PPC405.TSTDCRBUSO21
CELL_E[5].OUT_SEC_TMIN[9]PPC405.TSTDCRBUSO20
CELL_E[5].OUT_SEC_TMIN[10]PPC405.TSTDCRBUSO19
CELL_E[5].OUT_SEC_TMIN[11]PPC405.TSTDSOCMBYTEENO0
CELL_E[5].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT26
CELL_E[5].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT10
CELL_E[5].OUT_SEC_TMIN[14]PPC405.C405APUWBBYTEEN2
CELL_E[5].OUT_SEC_TMIN[15]PPC405.C405APUWBBYTEEN1
CELL_E[5].OUT_TEST[0]PPC405.TSTDCRBUSO22
CELL_E[5].OUT_TEST[2]PPC405.TSTDSOCMHOLDO
CELL_E[5].OUT_TEST[4]PPC405.TSTISOPFWDO
CELL_E[6].IMUX_TI[0]PPC405.TIERAMTAP1
CELL_E[6].IMUX_TI[1]PPC405.TIERAMTAP2
CELL_E[6].IMUX_G0_DATA[0]PPC405.APUC405DCDXERCAEN
CELL_E[6].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN26
CELL_E[6].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI23
CELL_E[6].IMUX_G0_DATA[3]PPC405.TSTC405DCRWRITEI
CELL_E[6].IMUX_G0_DATA[4]PPC405.TSTDSOCMWRDBUSI15
CELL_E[6].IMUX_G1_DATA[0]PPC405.APUC405DCDXEROVEN
CELL_E[6].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN27
CELL_E[6].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI24
CELL_E[6].IMUX_G1_DATA[3]PPC405.TSTDSOCMDBUSI0
CELL_E[6].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI16
CELL_E[6].IMUX_G2_DATA[0]PPC405.APUC405EXEXEROV
CELL_E[6].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI26
CELL_E[6].IMUX_G2_DATA[2]PPC405.TSTC405DCRDBUSOUTI2
CELL_E[6].IMUX_G2_DATA[3]PPC405.TSTDSOCMABUSI20
CELL_E[6].IMUX_G3_DATA[0]PPC405.APUC405FPUEXCEPTION
CELL_E[6].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI27
CELL_E[6].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI3
CELL_E[6].IMUX_G3_DATA[3]PPC405.TSTDSOCMABUSI21
CELL_E[6].OUT_FAN_TMIN[0]PPC405.C405APUDCDINSTRUCTION22
CELL_E[6].OUT_FAN_TMIN[1]PPC405.C405APUDCDINSTRUCTION23
CELL_E[6].OUT_FAN_TMIN[2]PPC405.C405APUDCDINSTRUCTION24
CELL_E[6].OUT_FAN_TMIN[3]PPC405.C405APUDCDINSTRUCTION25
CELL_E[6].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA7
CELL_E[6].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA8
CELL_E[6].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA7
CELL_E[6].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA8
CELL_E[6].OUT_SEC_TMIN[8]PPC405.TSTDCRBUSO25
CELL_E[6].OUT_SEC_TMIN[9]PPC405.TSTDCRBUSO24
CELL_E[6].OUT_SEC_TMIN[10]PPC405.TSTDCRBUSO23
CELL_E[6].OUT_SEC_TMIN[11]PPC405.TSTDSOCMBYTEENO1
CELL_E[6].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT27
CELL_E[6].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT11
CELL_E[6].OUT_SEC_TMIN[14]PPC405.C405APUWBENDIAN
CELL_E[6].OUT_SEC_TMIN[15]PPC405.C405APUWBBYTEEN3
CELL_E[6].OUT_TEST[0]PPC405.TSTDCRBUSO26
CELL_E[6].OUT_TEST[2]PPC405.TSTOCMCOMPLETEO
CELL_E[7].IMUX_TI[0]PPC405.TIETAGTAP1
CELL_E[7].IMUX_TI[1]PPC405.TIETAGTAP2
CELL_E[7].IMUX_G0_DATA[0]PPC405.APUC405EXCEPTION
CELL_E[7].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN28
CELL_E[7].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI25
CELL_E[7].IMUX_G0_DATA[3]PPC405.TSTDSOCMDBUSI1
CELL_E[7].IMUX_G0_DATA[4]PPC405.TSTDSOCMWRDBUSI17
CELL_E[7].IMUX_G1_DATA[0]PPC405.APUC405EXEBLOCKINGMCO
CELL_E[7].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN29
CELL_E[7].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI26
CELL_E[7].IMUX_G1_DATA[3]PPC405.TSTDSOCMDBUSI2
CELL_E[7].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI18
CELL_E[7].IMUX_G2_DATA[0]PPC405.APUC405LWBLDDEPEND
CELL_E[7].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI28
CELL_E[7].IMUX_G2_DATA[2]PPC405.TSTC405DCRDBUSOUTI4
CELL_E[7].IMUX_G2_DATA[3]PPC405.TSTDSOCMABUSI22
CELL_E[7].IMUX_G3_DATA[0]PPC405.APUC405SLEEPREQ
CELL_E[7].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI29
CELL_E[7].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI5
CELL_E[7].IMUX_G3_DATA[3]PPC405.TSTDSOCMABUSI23
CELL_E[7].OUT_FAN_TMIN[0]PPC405.C405APUDCDINSTRUCTION26
CELL_E[7].OUT_FAN_TMIN[1]PPC405.C405APUDCDINSTRUCTION27
CELL_E[7].OUT_FAN_TMIN[2]PPC405.C405APUDCDINSTRUCTION28
CELL_E[7].OUT_FAN_TMIN[3]PPC405.C405APUDCDINSTRUCTION29
CELL_E[7].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA9
CELL_E[7].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA10
CELL_E[7].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA9
CELL_E[7].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA10
CELL_E[7].OUT_SEC_TMIN[8]PPC405.TSTDCRBUSO29
CELL_E[7].OUT_SEC_TMIN[9]PPC405.TSTDCRBUSO28
CELL_E[7].OUT_SEC_TMIN[10]PPC405.TSTDCRBUSO27
CELL_E[7].OUT_SEC_TMIN[11]PPC405.TSTDSOCMBYTEENO2
CELL_E[7].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT28
CELL_E[7].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT12
CELL_E[7].OUT_SEC_TMIN[14]PPC405.C405APUWBHOLD
CELL_E[7].OUT_SEC_TMIN[15]PPC405.C405APUWBFLUSH
CELL_E[7].OUT_TEST[0]PPC405.TSTDCRBUSO30
CELL_E[8].IMUX_TI[0]PPC405.TESTSELI
CELL_E[8].IMUX_G0_DATA[0]PPC405.APUC405EXEBUSY
CELL_E[8].IMUX_G0_DATA[1]PPC405.DCRC405ACK
CELL_E[8].IMUX_G0_DATA[2]PPC405.TSTDCRBUSI30
CELL_E[8].IMUX_G0_DATA[3]PPC405.TSTC405DCRDBUSOUTI6
CELL_E[8].IMUX_G0_DATA[4]PPC405.TSTDSOCMABUSI25
CELL_E[8].IMUX_G1_DATA[0]PPC405.APUC405EXECR0
CELL_E[8].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN30
CELL_E[8].IMUX_G1_DATA[2]PPC405.TSTDCRBUSI31
CELL_E[8].IMUX_G1_DATA[3]PPC405.TSTDSOCMDBUSI3
CELL_E[8].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI19
CELL_E[8].IMUX_G2_DATA[0]PPC405.APUC405EXECR1
CELL_E[8].IMUX_G2_DATA[1]PPC405.DCRC405DBUSIN31
CELL_E[8].IMUX_G2_DATA[2]PPC405.TSTRDDBUSI27
CELL_E[8].IMUX_G2_DATA[3]PPC405.TSTDSOCMDBUSI4
CELL_E[8].IMUX_G2_DATA[4]PPC405.TSTDSOCMWRDBUSI20
CELL_E[8].IMUX_G3_DATA[0]PPC405.APUC405WBLDDEPEND
CELL_E[8].IMUX_G3_DATA[1]PPC405.TSTDCRACKI
CELL_E[8].IMUX_G3_DATA[2]PPC405.TSTRDDBUSI28
CELL_E[8].IMUX_G3_DATA[3]PPC405.TSTDSOCMABUSI24
CELL_E[8].OUT_FAN_TMIN[0]PPC405.C405APUDCDINSTRUCTION30
CELL_E[8].OUT_FAN_TMIN[1]PPC405.C405APUDCDINSTRUCTION31
CELL_E[8].OUT_FAN_TMIN[2]PPC405.C405APUEXEFLUSH
CELL_E[8].OUT_FAN_TMIN[3]PPC405.C405APUEXEHOLD
CELL_E[8].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA11
CELL_E[8].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA12
CELL_E[8].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA11
CELL_E[8].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA12
CELL_E[8].OUT_SEC_TMIN[8]PPC405.TSTDSOCMDBUSO1
CELL_E[8].OUT_SEC_TMIN[9]PPC405.TSTDSOCMDBUSO0
CELL_E[8].OUT_SEC_TMIN[10]PPC405.TSTDCRBUSO31
CELL_E[8].OUT_SEC_TMIN[11]PPC405.TSTDSOCMBYTEENO3
CELL_E[8].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT29
CELL_E[8].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT13
CELL_E[8].OUT_SEC_TMIN[14]PPC405.C405DCRABUS0
CELL_E[8].OUT_SEC_TMIN[15]PPC405.C405APUXERCA
CELL_E[8].OUT_TEST[0]PPC405.TSTDSOCMDBUSO2
CELL_E[9].IMUX_G0_DATA[0]PPC405.APUC405EXECR2
CELL_E[9].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN0
CELL_E[9].IMUX_G0_DATA[2]PPC405.TSTDSOCMCOMPLETEI
CELL_E[9].IMUX_G0_DATA[3]PPC405.TSTC405DCRDBUSOUTI7
CELL_E[9].IMUX_G0_DATA[4]PPC405.TSTDSOCMABUSI26
CELL_E[9].IMUX_G1_DATA[0]PPC405.APUC405EXECR3
CELL_E[9].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN1
CELL_E[9].IMUX_G1_DATA[2]PPC405.TSTISOPFWDI
CELL_E[9].IMUX_G1_DATA[3]PPC405.TSTC405DCRDBUSOUTI8
CELL_E[9].IMUX_G1_DATA[4]PPC405.TSTDSOCMABUSI27
CELL_E[9].IMUX_G2_DATA[0]PPC405.APUC405EXECRFIELD0
CELL_E[9].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI0
CELL_E[9].IMUX_G2_DATA[2]PPC405.TSTRDDBUSI29
CELL_E[9].IMUX_G2_DATA[3]PPC405.TSTDSOCMDBUSI5
CELL_E[9].IMUX_G2_DATA[4]PPC405.TSTDSOCMWRDBUSI21
CELL_E[9].IMUX_G3_DATA[0]PPC405.APUC405EXECRFIELD1
CELL_E[9].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI1
CELL_E[9].IMUX_G3_DATA[2]PPC405.TSTRDDBUSI30
CELL_E[9].IMUX_G3_DATA[3]PPC405.TSTDSOCMDBUSI6
CELL_E[9].IMUX_G3_DATA[4]PPC405.TSTDSOCMWRDBUSI22
CELL_E[9].OUT_FAN_TMIN[0]PPC405.C405APUEXELOADDBUS0
CELL_E[9].OUT_FAN_TMIN[1]PPC405.C405APUEXELOADDBUS1
CELL_E[9].OUT_FAN_TMIN[2]PPC405.C405APUEXELOADDBUS2
CELL_E[9].OUT_FAN_TMIN[3]PPC405.C405APUEXELOADDBUS3
CELL_E[9].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA13
CELL_E[9].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA14
CELL_E[9].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA13
CELL_E[9].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA14
CELL_E[9].OUT_SEC_TMIN[8]PPC405.TSTDSOCMDBUSO5
CELL_E[9].OUT_SEC_TMIN[9]PPC405.TSTDSOCMDBUSO4
CELL_E[9].OUT_SEC_TMIN[10]PPC405.TSTDSOCMDBUSO3
CELL_E[9].OUT_SEC_TMIN[11]PPC405.TSTDSOCMLOADREQO
CELL_E[9].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT30
CELL_E[9].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT14
CELL_E[9].OUT_SEC_TMIN[14]PPC405.C405DCRABUS2
CELL_E[9].OUT_SEC_TMIN[15]PPC405.C405DCRABUS1
CELL_E[9].OUT_TEST[0]PPC405.TSTDSOCMDBUSO6
CELL_E[10].IMUX_G0_DATA[0]PPC405.APUC405EXECRFIELD2
CELL_E[10].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN2
CELL_E[10].IMUX_G0_DATA[2]PPC405.TSTDSOCMHOLDI
CELL_E[10].IMUX_G0_DATA[3]PPC405.TSTC405DCRDBUSOUTI10
CELL_E[10].IMUX_G0_DATA[4]PPC405.TSTDSOCMABUSI29
CELL_E[10].IMUX_G1_DATA[0]PPC405.APUC405EXELDDEPEND
CELL_E[10].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN3
CELL_E[10].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI0
CELL_E[10].IMUX_G1_DATA[3]PPC405.TSTDSOCMDBUSI7
CELL_E[10].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI23
CELL_E[10].IMUX_G2_DATA[0]PPC405.APUC405EXENONBLOCKINGMCO
CELL_E[10].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI2
CELL_E[10].IMUX_G2_DATA[2]PPC405.TSTRDDBUSI31
CELL_E[10].IMUX_G2_DATA[3]PPC405.TSTDSOCMDCRACKI
CELL_E[10].IMUX_G2_DATA[4]PPC405.TSTDSOCMWRDBUSI24
CELL_E[10].IMUX_G3_DATA[0]PPC405.APUC405EXERESULT0
CELL_E[10].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI3
CELL_E[10].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI9
CELL_E[10].IMUX_G3_DATA[3]PPC405.TSTDSOCMABUSI28
CELL_E[10].OUT_FAN_TMIN[0]PPC405.C405APUEXELOADDBUS4
CELL_E[10].OUT_FAN_TMIN[1]PPC405.C405APUEXELOADDBUS5
CELL_E[10].OUT_FAN_TMIN[2]PPC405.C405APUEXELOADDBUS6
CELL_E[10].OUT_FAN_TMIN[3]PPC405.C405APUEXELOADDBUS7
CELL_E[10].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA15
CELL_E[10].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA16
CELL_E[10].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA15
CELL_E[10].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA16
CELL_E[10].OUT_SEC_TMIN[8]PPC405.TSTRDDBUSO0
CELL_E[10].OUT_SEC_TMIN[9]PPC405.TSTDSOCMDCRACKO
CELL_E[10].OUT_SEC_TMIN[10]PPC405.TSTDSOCMDBUSO7
CELL_E[10].OUT_SEC_TMIN[11]PPC405.TSTDSOCMSTOREREQO
CELL_E[10].OUT_SEC_TMIN[12]PPC405.C405DCRDBUSOUT31
CELL_E[10].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT15
CELL_E[10].OUT_SEC_TMIN[14]PPC405.C405DCRABUS4
CELL_E[10].OUT_SEC_TMIN[15]PPC405.C405DCRABUS3
CELL_E[10].OUT_TEST[0]PPC405.TSTRDDBUSO1
CELL_E[11].IMUX_G0_DATA[0]PPC405.APUC405EXERESULT1
CELL_E[11].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN4
CELL_E[11].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI1
CELL_E[11].IMUX_G0_DATA[3]PPC405.TSTDSOCMABORTOPI
CELL_E[11].IMUX_G0_DATA[4]PPC405.TSTDSOCMWRDBUSI25
CELL_E[11].IMUX_G1_DATA[0]PPC405.APUC405EXERESULT2
CELL_E[11].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN5
CELL_E[11].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI2
CELL_E[11].IMUX_G1_DATA[3]PPC405.TSTDSOCMABORTREQI
CELL_E[11].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI26
CELL_E[11].IMUX_G2_DATA[0]PPC405.APUC405EXERESULT3
CELL_E[11].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI4
CELL_E[11].IMUX_G2_DATA[2]PPC405.TSTC405DCRDBUSOUTI11
CELL_E[11].IMUX_G2_DATA[3]PPC405.TSTDSOCMBYTEENI0
CELL_E[11].IMUX_G3_DATA[0]PPC405.APUC405EXERESULT4
CELL_E[11].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI5
CELL_E[11].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI12
CELL_E[11].IMUX_G3_DATA[3]PPC405.TSTDSOCMBYTEENI1
CELL_E[11].OUT_FAN_TMIN[0]PPC405.C405APUEXELOADDBUS8
CELL_E[11].OUT_FAN_TMIN[1]PPC405.C405APUEXELOADDBUS9
CELL_E[11].OUT_FAN_TMIN[2]PPC405.C405APUEXELOADDBUS10
CELL_E[11].OUT_FAN_TMIN[3]PPC405.C405APUEXELOADDBUS11
CELL_E[11].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA17
CELL_E[11].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA18
CELL_E[11].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA17
CELL_E[11].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA18
CELL_E[11].OUT_SEC_TMIN[8]PPC405.TSTRDDBUSO4
CELL_E[11].OUT_SEC_TMIN[9]PPC405.TSTRDDBUSO3
CELL_E[11].OUT_SEC_TMIN[10]PPC405.TSTRDDBUSO2
CELL_E[11].OUT_SEC_TMIN[11]PPC405.TSTDSOCMWAITO
CELL_E[11].OUT_SEC_TMIN[12]PPC405.C405DCRREAD
CELL_E[11].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT16
CELL_E[11].OUT_SEC_TMIN[14]PPC405.C405DCRABUS6
CELL_E[11].OUT_SEC_TMIN[15]PPC405.C405DCRABUS5
CELL_E[11].OUT_TEST[0]PPC405.TSTRDDBUSO5
CELL_E[12].IMUX_G0_DATA[0]PPC405.APUC405EXERESULT5
CELL_E[12].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN6
CELL_E[12].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI3
CELL_E[12].IMUX_G0_DATA[3]PPC405.TSTDSOCMABUSI0
CELL_E[12].IMUX_G0_DATA[4]PPC405.TSTDSOCMWRDBUSI27
CELL_E[12].IMUX_G1_DATA[0]PPC405.APUC405EXERESULT6
CELL_E[12].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN7
CELL_E[12].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI4
CELL_E[12].IMUX_G1_DATA[3]PPC405.TSTDSOCMABUSI1
CELL_E[12].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI28
CELL_E[12].IMUX_G2_DATA[0]PPC405.APUC405EXERESULT7
CELL_E[12].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI6
CELL_E[12].IMUX_G2_DATA[2]PPC405.TSTC405DCRDBUSOUTI13
CELL_E[12].IMUX_G2_DATA[3]PPC405.TSTDSOCMBYTEENI2
CELL_E[12].IMUX_G3_DATA[0]PPC405.APUC405EXERESULT8
CELL_E[12].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI7
CELL_E[12].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI14
CELL_E[12].IMUX_G3_DATA[3]PPC405.TSTDSOCMBYTEENI3
CELL_E[12].OUT_FAN_TMIN[0]PPC405.C405APUEXELOADDBUS12
CELL_E[12].OUT_FAN_TMIN[1]PPC405.C405APUEXELOADDBUS13
CELL_E[12].OUT_FAN_TMIN[2]PPC405.C405APUEXELOADDBUS14
CELL_E[12].OUT_FAN_TMIN[3]PPC405.C405APUEXELOADDBUS15
CELL_E[12].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA19
CELL_E[12].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA20
CELL_E[12].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA19
CELL_E[12].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA20
CELL_E[12].OUT_SEC_TMIN[8]PPC405.TSTRDDBUSO8
CELL_E[12].OUT_SEC_TMIN[9]PPC405.TSTRDDBUSO7
CELL_E[12].OUT_SEC_TMIN[10]PPC405.TSTRDDBUSO6
CELL_E[12].OUT_SEC_TMIN[11]PPC405.TSTDSOCMXLATEVALIDO
CELL_E[12].OUT_SEC_TMIN[12]PPC405.C405DCRWRITE
CELL_E[12].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT17
CELL_E[12].OUT_SEC_TMIN[14]PPC405.C405DCRABUS8
CELL_E[12].OUT_SEC_TMIN[15]PPC405.C405DCRABUS7
CELL_E[12].OUT_TEST[0]PPC405.TSTRDDBUSO9
CELL_E[13].IMUX_G0_DATA[0]PPC405.APUC405EXERESULT9
CELL_E[13].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN8
CELL_E[13].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI5
CELL_E[13].IMUX_G0_DATA[3]PPC405.TSTDSOCMABUSI2
CELL_E[13].IMUX_G0_DATA[4]PPC405.TSTDSOCMWRDBUSI29
CELL_E[13].IMUX_G1_DATA[0]PPC405.APUC405EXERESULT10
CELL_E[13].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN9
CELL_E[13].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI6
CELL_E[13].IMUX_G1_DATA[3]PPC405.TSTDSOCMABUSI3
CELL_E[13].IMUX_G1_DATA[4]PPC405.TSTDSOCMWRDBUSI30
CELL_E[13].IMUX_G2_DATA[0]PPC405.APUC405EXERESULT11
CELL_E[13].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI8
CELL_E[13].IMUX_G2_DATA[2]PPC405.TSTC405DCRDBUSOUTI15
CELL_E[13].IMUX_G2_DATA[3]PPC405.TSTDSOCMLOADREQI
CELL_E[13].IMUX_G3_DATA[0]PPC405.APUC405EXERESULT12
CELL_E[13].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI9
CELL_E[13].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI16
CELL_E[13].IMUX_G3_DATA[3]PPC405.TSTDSOCMSTOREREQI
CELL_E[13].OUT_FAN_TMIN[0]PPC405.C405APUEXELOADDBUS16
CELL_E[13].OUT_FAN_TMIN[1]PPC405.C405APUEXELOADDBUS17
CELL_E[13].OUT_FAN_TMIN[2]PPC405.C405APUEXELOADDBUS18
CELL_E[13].OUT_FAN_TMIN[3]PPC405.C405APUEXELOADDBUS19
CELL_E[13].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA21
CELL_E[13].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA22
CELL_E[13].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA21
CELL_E[13].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA22
CELL_E[13].OUT_SEC_TMIN[8]PPC405.TSTRDDBUSO13
CELL_E[13].OUT_SEC_TMIN[9]PPC405.TSTRDDBUSO12
CELL_E[13].OUT_SEC_TMIN[10]PPC405.TSTRDDBUSO11
CELL_E[13].OUT_SEC_TMIN[11]PPC405.TSTRDDBUSO10
CELL_E[13].OUT_SEC_TMIN[12]PPC405.TSTDSOCMABORTOPO
CELL_E[13].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT18
CELL_E[13].OUT_SEC_TMIN[14]PPC405.C405DCRDBUSOUT0
CELL_E[13].OUT_SEC_TMIN[15]PPC405.C405DCRABUS9
CELL_E[14].IMUX_G0_DATA[0]PPC405.APUC405EXERESULT13
CELL_E[14].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN10
CELL_E[14].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI7
CELL_E[14].IMUX_G0_DATA[3]PPC405.TSTDSOCMABUSI4
CELL_E[14].IMUX_G0_DATA[4]PPC405.TSTDSOCMWRDBUSI31
CELL_E[14].IMUX_G1_DATA[0]PPC405.APUC405EXERESULT14
CELL_E[14].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN11
CELL_E[14].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI8
CELL_E[14].IMUX_G1_DATA[3]PPC405.TSTDSOCMABUSI5
CELL_E[14].IMUX_G1_DATA[4]PPC405.TSTDSOCMXLATEVALIDI
CELL_E[14].IMUX_G2_DATA[0]PPC405.APUC405EXERESULT15
CELL_E[14].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI10
CELL_E[14].IMUX_G2_DATA[2]PPC405.TSTC405DCRDBUSOUTI17
CELL_E[14].IMUX_G2_DATA[3]PPC405.TSTDSOCMWAITI
CELL_E[14].IMUX_G3_DATA[0]PPC405.APUC405EXERESULT16
CELL_E[14].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI11
CELL_E[14].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI18
CELL_E[14].IMUX_G3_DATA[3]PPC405.TSTDSOCMWRDBUSI0
CELL_E[14].OUT_FAN_TMIN[0]PPC405.C405APUEXELOADDBUS20
CELL_E[14].OUT_FAN_TMIN[1]PPC405.C405APUEXELOADDBUS21
CELL_E[14].OUT_FAN_TMIN[2]PPC405.C405APUEXELOADDBUS22
CELL_E[14].OUT_FAN_TMIN[3]PPC405.C405APUEXELOADDBUS23
CELL_E[14].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA23
CELL_E[14].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA24
CELL_E[14].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA23
CELL_E[14].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA24
CELL_E[14].OUT_SEC_TMIN[8]PPC405.TSTRDDBUSO17
CELL_E[14].OUT_SEC_TMIN[9]PPC405.TSTRDDBUSO16
CELL_E[14].OUT_SEC_TMIN[10]PPC405.TSTRDDBUSO15
CELL_E[14].OUT_SEC_TMIN[11]PPC405.TSTRDDBUSO14
CELL_E[14].OUT_SEC_TMIN[12]PPC405.TSTDSOCMABORTREQO
CELL_E[14].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT19
CELL_E[14].OUT_SEC_TMIN[14]PPC405.C405DCRDBUSOUT2
CELL_E[14].OUT_SEC_TMIN[15]PPC405.C405DCRDBUSOUT1
CELL_E[15].IMUX_G0_DATA[0]PPC405.APUC405EXERESULT17
CELL_E[15].IMUX_G0_DATA[1]PPC405.DCRC405DBUSIN12
CELL_E[15].IMUX_G0_DATA[2]PPC405.TSTRDDBUSI9
CELL_E[15].IMUX_G0_DATA[3]PPC405.TSTDSOCMABUSI6
CELL_E[15].IMUX_G1_DATA[0]PPC405.APUC405EXERESULT18
CELL_E[15].IMUX_G1_DATA[1]PPC405.DCRC405DBUSIN13
CELL_E[15].IMUX_G1_DATA[2]PPC405.TSTRDDBUSI10
CELL_E[15].IMUX_G1_DATA[3]PPC405.TSTDSOCMABUSI7
CELL_E[15].IMUX_G2_DATA[0]PPC405.APUC405EXERESULT19
CELL_E[15].IMUX_G2_DATA[1]PPC405.TSTDCRBUSI12
CELL_E[15].IMUX_G2_DATA[2]PPC405.TSTC405DCRDBUSOUTI19
CELL_E[15].IMUX_G2_DATA[3]PPC405.TSTDSOCMWRDBUSI1
CELL_E[15].IMUX_G3_DATA[0]PPC405.APUC405EXERESULT20
CELL_E[15].IMUX_G3_DATA[1]PPC405.TSTDCRBUSI13
CELL_E[15].IMUX_G3_DATA[2]PPC405.TSTC405DCRDBUSOUTI20
CELL_E[15].IMUX_G3_DATA[3]PPC405.TSTDSOCMWRDBUSI2
CELL_E[15].OUT_FAN_TMIN[0]PPC405.C405APUEXELOADDBUS24
CELL_E[15].OUT_FAN_TMIN[1]PPC405.C405APUEXELOADDBUS25
CELL_E[15].OUT_FAN_TMIN[2]PPC405.C405APUEXELOADDBUS26
CELL_E[15].OUT_FAN_TMIN[3]PPC405.C405APUEXELOADDBUS27
CELL_E[15].OUT_FAN_TMIN[4]PPC405.C405APUEXERADATA25
CELL_E[15].OUT_FAN_TMIN[5]PPC405.C405APUEXERADATA26
CELL_E[15].OUT_FAN_TMIN[6]PPC405.C405APUEXERBDATA25
CELL_E[15].OUT_FAN_TMIN[7]PPC405.C405APUEXERBDATA26
CELL_E[15].OUT_SEC_TMIN[8]PPC405.TSTRDDBUSO21
CELL_E[15].OUT_SEC_TMIN[9]PPC405.TSTRDDBUSO20
CELL_E[15].OUT_SEC_TMIN[10]PPC405.TSTRDDBUSO19
CELL_E[15].OUT_SEC_TMIN[11]PPC405.TSTRDDBUSO18
CELL_E[15].OUT_SEC_TMIN[12]PPC405.TSTDSOCMABUSO24
CELL_E[15].OUT_SEC_TMIN[13]PPC405.C405DCRDBUSOUT20
CELL_E[15].OUT_SEC_TMIN[14]PPC405.C405DCRDBUSOUT4
CELL_E[15].OUT_SEC_TMIN[15]PPC405.C405DCRDBUSOUT3
CELL_S[0].IMUX_G0_DATA[0]PPC405.BRAMISOCMRDDBUS0
CELL_S[0].IMUX_G0_DATA[1]PPC405.BRAMISOCMRDDBUS4
CELL_S[0].IMUX_G0_DATA[2]PPC405.BRAMISOCMRDDBUS8
CELL_S[0].IMUX_G0_DATA[3]PPC405.BRAMISOCMRDDBUS12
CELL_S[0].IMUX_G0_DATA[4]PPC405.TSTISOCMRDATAI17
CELL_S[0].IMUX_G0_DATA[5]PPC405.TSTISOCMRDATAI49
CELL_S[0].IMUX_G0_DATA[6]PPC405.LSSDC405SCANIN8
CELL_S[0].IMUX_G1_DATA[0]PPC405.BRAMISOCMRDDBUS1
CELL_S[0].IMUX_G1_DATA[1]PPC405.BRAMISOCMRDDBUS5
CELL_S[0].IMUX_G1_DATA[2]PPC405.BRAMISOCMRDDBUS9
CELL_S[0].IMUX_G1_DATA[3]PPC405.BRAMISOCMRDDBUS13
CELL_S[0].IMUX_G1_DATA[4]PPC405.TSTISOCMRDATAI18
CELL_S[0].IMUX_G1_DATA[5]PPC405.TSTISOCMRDATAI50
CELL_S[0].IMUX_G1_DATA[6]PPC405.LSSDC405SCANIN9
CELL_S[0].IMUX_G2_DATA[0]PPC405.BRAMISOCMRDDBUS2
CELL_S[0].IMUX_G2_DATA[1]PPC405.BRAMISOCMRDDBUS6
CELL_S[0].IMUX_G2_DATA[2]PPC405.BRAMISOCMRDDBUS10
CELL_S[0].IMUX_G2_DATA[3]PPC405.BRAMISOCMRDDBUS14
CELL_S[0].IMUX_G2_DATA[4]PPC405.TSTISOCMRDATAI19
CELL_S[0].IMUX_G2_DATA[5]PPC405.LSSDC405ARRAYCCLKNEG
CELL_S[0].IMUX_G3_DATA[0]PPC405.BRAMISOCMRDDBUS3
CELL_S[0].IMUX_G3_DATA[1]PPC405.BRAMISOCMRDDBUS7
CELL_S[0].IMUX_G3_DATA[2]PPC405.BRAMISOCMRDDBUS11
CELL_S[0].IMUX_G3_DATA[3]PPC405.BRAMISOCMRDDBUS15
CELL_S[0].IMUX_G3_DATA[4]PPC405.TSTISOCMRDATAI20
CELL_S[0].IMUX_G3_DATA[5]PPC405.LSSDC405BCLK
CELL_S[0].IMUX_BRAM_ADDRA[0]PPC405.ISOCMBRAMWRABUS15
CELL_S[0].IMUX_BRAM_ADDRA[1]PPC405.ISOCMBRAMWRABUS16
CELL_S[0].IMUX_BRAM_ADDRA[2]PPC405.ISOCMBRAMWRABUS17
CELL_S[0].IMUX_BRAM_ADDRA[3]PPC405.ISOCMBRAMWRABUS18
CELL_S[0].IMUX_BRAM_ADDRA_S1[0]PPC405.ISOCMBRAMWRABUS19
CELL_S[0].IMUX_BRAM_ADDRA_S1[1]PPC405.ISOCMBRAMWRABUS20
CELL_S[0].IMUX_BRAM_ADDRA_S1[2]PPC405.ISOCMBRAMWRABUS21
CELL_S[0].IMUX_BRAM_ADDRA_S1[3]PPC405.ISOCMBRAMWRABUS22
CELL_S[0].IMUX_BRAM_ADDRA_S2[0]PPC405.ISOCMBRAMWRABUS23
CELL_S[0].IMUX_BRAM_ADDRA_S2[1]PPC405.ISOCMBRAMWRABUS24
CELL_S[0].IMUX_BRAM_ADDRA_S2[2]PPC405.ISOCMBRAMWRABUS25
CELL_S[0].IMUX_BRAM_ADDRA_S2[3]PPC405.ISOCMBRAMWRABUS26
CELL_S[0].IMUX_BRAM_ADDRA_S3[0]PPC405.ISOCMBRAMWRABUS27
CELL_S[0].IMUX_BRAM_ADDRA_S3[1]PPC405.ISOCMBRAMWRABUS28
CELL_S[0].IMUX_BRAM_ADDRB[0]PPC405.ISOCMBRAMRDABUS15
CELL_S[0].IMUX_BRAM_ADDRB[1]PPC405.ISOCMBRAMRDABUS16
CELL_S[0].IMUX_BRAM_ADDRB[2]PPC405.ISOCMBRAMRDABUS17
CELL_S[0].IMUX_BRAM_ADDRB[3]PPC405.ISOCMBRAMRDABUS18
CELL_S[0].IMUX_BRAM_ADDRB_S1[0]PPC405.ISOCMBRAMRDABUS19
CELL_S[0].IMUX_BRAM_ADDRB_S1[1]PPC405.ISOCMBRAMRDABUS20
CELL_S[0].IMUX_BRAM_ADDRB_S1[2]PPC405.ISOCMBRAMRDABUS21
CELL_S[0].IMUX_BRAM_ADDRB_S1[3]PPC405.ISOCMBRAMRDABUS22
CELL_S[0].IMUX_BRAM_ADDRB_S2[0]PPC405.ISOCMBRAMRDABUS23
CELL_S[0].IMUX_BRAM_ADDRB_S2[1]PPC405.ISOCMBRAMRDABUS24
CELL_S[0].IMUX_BRAM_ADDRB_S2[2]PPC405.ISOCMBRAMRDABUS25
CELL_S[0].IMUX_BRAM_ADDRB_S2[3]PPC405.ISOCMBRAMRDABUS26
CELL_S[0].IMUX_BRAM_ADDRB_S3[0]PPC405.ISOCMBRAMRDABUS27
CELL_S[0].IMUX_BRAM_ADDRB_S3[1]PPC405.ISOCMBRAMRDABUS28
CELL_S[0].OUT_FAN_TMIN[0]PPC405.ISOCMBRAMWRABUS8
CELL_S[0].OUT_FAN_TMIN[1]PPC405.ISOCMBRAMWRABUS9
CELL_S[0].OUT_FAN_TMIN[2]PPC405.ISOCMBRAMWRABUS10
CELL_S[0].OUT_FAN_TMIN[3]PPC405.ISOCMBRAMWRABUS11
CELL_S[0].OUT_FAN_TMIN[4]PPC405.ISOCMBRAMWRABUS12
CELL_S[0].OUT_FAN_TMIN[5]PPC405.ISOCMBRAMWRABUS13
CELL_S[0].OUT_FAN_TMIN[6]PPC405.ISOCMBRAMWRABUS14
CELL_S[0].OUT_FAN_TMIN[7]PPC405.ISOCMBRAMWRABUS15
CELL_S[0].OUT_SEC_TMIN[8]PPC405.TSTISOCMABUSO0
CELL_S[0].OUT_SEC_TMIN[9]PPC405.TSTISOCMICUREADYO
CELL_S[0].OUT_SEC_TMIN[10]PPC405.TSTISOCMREQPENDO
CELL_S[0].OUT_SEC_TMIN[11]PPC405.TSTISOCMXLATEVALIDO
CELL_S[0].OUT_SEC_TMIN[12]PPC405.ISOCMBRAMWRABUS19
CELL_S[0].OUT_SEC_TMIN[13]PPC405.ISOCMBRAMWRABUS18
CELL_S[0].OUT_SEC_TMIN[14]PPC405.ISOCMBRAMWRABUS17
CELL_S[0].OUT_SEC_TMIN[15]PPC405.ISOCMBRAMWRABUS16
CELL_S[0].OUT_TEST[0]PPC405.TSTISOCMABUSO29
CELL_S[0].OUT_TEST[2]PPC405.TSTISOCMABORTO
CELL_S[0].OUT_TEST[4]PPC405.C405ISOCMU0ATTR
CELL_S[0].OUT_TEST[6]PPC405.C405DSOCMCACHEABLE
CELL_S[1].IMUX_G0_DATA[0]PPC405.BRAMISOCMRDDBUS16
CELL_S[1].IMUX_G0_DATA[1]PPC405.BRAMISOCMRDDBUS20
CELL_S[1].IMUX_G0_DATA[2]PPC405.BRAMISOCMRDDBUS24
CELL_S[1].IMUX_G0_DATA[3]PPC405.BRAMISOCMRDDBUS28
CELL_S[1].IMUX_G0_DATA[4]PPC405.TSTISOCMRDATAI21
CELL_S[1].IMUX_G0_DATA[5]PPC405.TSTISOCMRDATAI51
CELL_S[1].IMUX_G1_DATA[0]PPC405.BRAMISOCMRDDBUS17
CELL_S[1].IMUX_G1_DATA[1]PPC405.BRAMISOCMRDDBUS21
CELL_S[1].IMUX_G1_DATA[2]PPC405.BRAMISOCMRDDBUS25
CELL_S[1].IMUX_G1_DATA[3]PPC405.BRAMISOCMRDDBUS29
CELL_S[1].IMUX_G1_DATA[4]PPC405.TSTISOCMRDATAI22
CELL_S[1].IMUX_G1_DATA[5]PPC405.TSTISOCMRDATAI52
CELL_S[1].IMUX_G2_DATA[0]PPC405.BRAMISOCMRDDBUS18
CELL_S[1].IMUX_G2_DATA[1]PPC405.BRAMISOCMRDDBUS22
CELL_S[1].IMUX_G2_DATA[2]PPC405.BRAMISOCMRDDBUS26
CELL_S[1].IMUX_G2_DATA[3]PPC405.BRAMISOCMRDDBUS30
CELL_S[1].IMUX_G2_DATA[4]PPC405.TSTISOCMRDATAI23
CELL_S[1].IMUX_G2_DATA[5]PPC405.LSSDC405BISTCCLK
CELL_S[1].IMUX_G3_DATA[0]PPC405.BRAMISOCMRDDBUS19
CELL_S[1].IMUX_G3_DATA[1]PPC405.BRAMISOCMRDDBUS23
CELL_S[1].IMUX_G3_DATA[2]PPC405.BRAMISOCMRDDBUS27
CELL_S[1].IMUX_G3_DATA[3]PPC405.BRAMISOCMRDDBUS31
CELL_S[1].IMUX_G3_DATA[4]PPC405.TSTISOCMRDATAI24
CELL_S[1].IMUX_G3_DATA[5]PPC405.LSSDC405CNTLPOINT
CELL_S[1].OUT_FAN_TMIN[0]PPC405.ISOCMBRAMWRABUS20
CELL_S[1].OUT_FAN_TMIN[1]PPC405.ISOCMBRAMWRABUS21
CELL_S[1].OUT_FAN_TMIN[2]PPC405.ISOCMBRAMWRABUS22
CELL_S[1].OUT_FAN_TMIN[3]PPC405.ISOCMBRAMWRABUS23
CELL_S[1].OUT_FAN_TMIN[4]PPC405.ISOCMBRAMWRABUS24
CELL_S[1].OUT_FAN_TMIN[5]PPC405.ISOCMBRAMWRABUS25
CELL_S[1].OUT_FAN_TMIN[6]PPC405.ISOCMBRAMWRABUS26
CELL_S[1].OUT_FAN_TMIN[7]PPC405.ISOCMBRAMWRABUS27
CELL_S[1].OUT_SEC_TMIN[8]PPC405.C405LSSDDIAGOUT
CELL_S[1].OUT_SEC_TMIN[9]PPC405.C405LSSDDIAGABISTDONE
CELL_S[1].OUT_SEC_TMIN[10]PPC405.TSTISOCMABUSO4
CELL_S[1].OUT_SEC_TMIN[11]PPC405.TSTISOCMABUSO3
CELL_S[1].OUT_SEC_TMIN[12]PPC405.TSTISOCMABUSO2
CELL_S[1].OUT_SEC_TMIN[13]PPC405.TSTISOCMABUSO1
CELL_S[1].OUT_SEC_TMIN[14]PPC405.ISOCMRDADDRVALID
CELL_S[1].OUT_SEC_TMIN[15]PPC405.ISOCMBRAMWRABUS28
CELL_S[1].OUT_TEST[0]PPC405.C405DSOCMGUARDED
CELL_S[1].OUT_TEST[2]PPC405.C405DSOCMSTRINGMULTIPLE
CELL_S[2].IMUX_SR[0]PPC405.ISCNTLVALUE0
CELL_S[2].IMUX_SR[1]PPC405.ISCNTLVALUE1
CELL_S[2].IMUX_TI[0]PPC405.TIEISOCMDCRADDR0
CELL_S[2].IMUX_TI[1]PPC405.TIEISOCMDCRADDR1
CELL_S[2].IMUX_TS[0]PPC405.TIEISOCMDCRADDR2
CELL_S[2].IMUX_TS[1]PPC405.TIEISOCMDCRADDR3
CELL_S[2].IMUX_G0_DATA[0]PPC405.ISCNTLVALUE6
CELL_S[2].IMUX_G0_DATA[1]PPC405.TSTISOCMRDATAI27
CELL_S[2].IMUX_G0_DATA[2]PPC405.LSSDC405SCANGATE
CELL_S[2].IMUX_G1_DATA[0]PPC405.ISCNTLVALUE7
CELL_S[2].IMUX_G1_DATA[1]PPC405.TSTISOCMRDATAI28
CELL_S[2].IMUX_G1_DATA[2]PPC405.LSSDC405TESTEVS
CELL_S[2].IMUX_G2_DATA[0]PPC405.TSTISOCMRDATAI25
CELL_S[2].IMUX_G2_DATA[1]PPC405.TSTISOCMRDATAI53
CELL_S[2].IMUX_G3_DATA[0]PPC405.TSTISOCMRDATAI26
CELL_S[2].IMUX_G3_DATA[1]PPC405.TSTISOCMRDATAI54
CELL_S[2].OUT_FAN_TMIN[0]PPC405.ISOCMBRAMWRDBUS0
CELL_S[2].OUT_FAN_TMIN[1]PPC405.ISOCMBRAMWRDBUS1
CELL_S[2].OUT_FAN_TMIN[2]PPC405.ISOCMBRAMWRDBUS2
CELL_S[2].OUT_FAN_TMIN[3]PPC405.ISOCMBRAMWRDBUS3
CELL_S[2].OUT_FAN_TMIN[4]PPC405.ISOCMBRAMWRDBUS4
CELL_S[2].OUT_FAN_TMIN[5]PPC405.ISOCMBRAMWRDBUS5
CELL_S[2].OUT_FAN_TMIN[6]PPC405.ISOCMBRAMWRDBUS6
CELL_S[2].OUT_FAN_TMIN[7]PPC405.ISOCMBRAMWRDBUS7
CELL_S[2].OUT_SEC_TMIN[8]PPC405.C405LSSDSCANOUT0
CELL_S[2].OUT_SEC_TMIN[9]PPC405.TSTISOCMABUSO8
CELL_S[2].OUT_SEC_TMIN[10]PPC405.TSTISOCMABUSO7
CELL_S[2].OUT_SEC_TMIN[11]PPC405.TSTISOCMABUSO6
CELL_S[2].OUT_SEC_TMIN[12]PPC405.TSTISOCMABUSO5
CELL_S[2].OUT_SEC_TMIN[13]PPC405.ISOCMBRAMEN
CELL_S[2].OUT_SEC_TMIN[14]PPC405.ISOCMBRAMEVENWRITEEN
CELL_S[2].OUT_SEC_TMIN[15]PPC405.ISOCMBRAMODDWRITEEN
CELL_S[2].OUT_TEST[0]PPC405.C405LSSDSCANOUT1
CELL_S[2].OUT_TEST[2]PPC405.C405DSOCMU0ATTR
CELL_S[3].IMUX_SR[0]PPC405.ISCNTLVALUE2
CELL_S[3].IMUX_SR[1]PPC405.ISCNTLVALUE3
CELL_S[3].IMUX_TI[0]PPC405.TIEISOCMDCRADDR4
CELL_S[3].IMUX_TI[1]PPC405.TIEISOCMDCRADDR5
CELL_S[3].IMUX_TS[0]PPC405.TIEISOCMDCRADDR6
CELL_S[3].IMUX_TS[1]PPC405.TIEISOCMDCRADDR7
CELL_S[3].IMUX_G0_DATA[0]PPC405.TSTISOCMRDATAI29
CELL_S[3].IMUX_G0_DATA[1]PPC405.TSTISOCMRDATAI55
CELL_S[3].IMUX_G1_DATA[0]PPC405.TSTISOCMRDATAI30
CELL_S[3].IMUX_G1_DATA[1]PPC405.TSTISOCMRDATAI56
CELL_S[3].IMUX_G2_DATA[0]PPC405.TSTISOCMRDATAI31
CELL_S[3].IMUX_G2_DATA[1]PPC405.LSSDC405TESTM1
CELL_S[3].IMUX_G3_DATA[0]PPC405.TSTISOCMRDATAI32
CELL_S[3].IMUX_G3_DATA[1]PPC405.LSSDC405TESTM3
CELL_S[3].OUT_FAN_TMIN[0]PPC405.ISOCMBRAMWRDBUS8
CELL_S[3].OUT_FAN_TMIN[1]PPC405.ISOCMBRAMWRDBUS9
CELL_S[3].OUT_FAN_TMIN[2]PPC405.ISOCMBRAMWRDBUS10
CELL_S[3].OUT_FAN_TMIN[3]PPC405.ISOCMBRAMWRDBUS11
CELL_S[3].OUT_FAN_TMIN[4]PPC405.ISOCMBRAMWRDBUS12
CELL_S[3].OUT_FAN_TMIN[5]PPC405.ISOCMBRAMWRDBUS13
CELL_S[3].OUT_FAN_TMIN[6]PPC405.ISOCMBRAMWRDBUS14
CELL_S[3].OUT_FAN_TMIN[7]PPC405.ISOCMBRAMWRDBUS15
CELL_S[3].OUT_SEC_TMIN[10]PPC405.C405LSSDSCANOUT3
CELL_S[3].OUT_SEC_TMIN[11]PPC405.C405LSSDSCANOUT2
CELL_S[3].OUT_SEC_TMIN[12]PPC405.TSTISOCMABUSO12
CELL_S[3].OUT_SEC_TMIN[13]PPC405.TSTISOCMABUSO11
CELL_S[3].OUT_SEC_TMIN[14]PPC405.TSTISOCMABUSO10
CELL_S[3].OUT_SEC_TMIN[15]PPC405.TSTISOCMABUSO9
CELL_S[4].IMUX_CLK[0]PPC405.BRAMISOCMCLK
CELL_S[4].IMUX_TI[0]PPC405.ISARCVALUE0
CELL_S[4].IMUX_TI[1]PPC405.ISARCVALUE1
CELL_S[4].IMUX_TS[0]PPC405.ISARCVALUE2
CELL_S[4].IMUX_TS[1]PPC405.ISARCVALUE3
CELL_S[4].IMUX_G0_DATA[0]PPC405.BRAMISOCMRDDACK
CELL_S[4].IMUX_G0_DATA[1]PPC405.TSTISOCMRDATAI36
CELL_S[4].IMUX_G0_DATA[2]PPC405.LSSDC405SCANIN1
CELL_S[4].IMUX_G1_DATA[0]PPC405.TSTISOCMRDATAI33
CELL_S[4].IMUX_G1_DATA[1]PPC405.TSTISOCMRDATAI57
CELL_S[4].IMUX_G2_DATA[0]PPC405.TSTISOCMRDATAI34
CELL_S[4].IMUX_G2_DATA[1]PPC405.TSTISOCMRDATAI58
CELL_S[4].IMUX_G3_DATA[0]PPC405.TSTISOCMRDATAI35
CELL_S[4].IMUX_G3_DATA[1]PPC405.LSSDC405SCANIN0
CELL_S[4].OUT_FAN_TMIN[0]PPC405.ISOCMBRAMWRDBUS16
CELL_S[4].OUT_FAN_TMIN[1]PPC405.ISOCMBRAMWRDBUS17
CELL_S[4].OUT_FAN_TMIN[2]PPC405.ISOCMBRAMWRDBUS18
CELL_S[4].OUT_FAN_TMIN[3]PPC405.ISOCMBRAMWRDBUS19
CELL_S[4].OUT_FAN_TMIN[4]PPC405.ISOCMBRAMWRDBUS20
CELL_S[4].OUT_FAN_TMIN[5]PPC405.ISOCMBRAMWRDBUS21
CELL_S[4].OUT_FAN_TMIN[6]PPC405.ISOCMBRAMWRDBUS22
CELL_S[4].OUT_FAN_TMIN[7]PPC405.ISOCMBRAMWRDBUS23
CELL_S[4].OUT_SEC_TMIN[10]PPC405.C405LSSDSCANOUT5
CELL_S[4].OUT_SEC_TMIN[11]PPC405.C405LSSDSCANOUT4
CELL_S[4].OUT_SEC_TMIN[12]PPC405.TSTISOCMABUSO16
CELL_S[4].OUT_SEC_TMIN[13]PPC405.TSTISOCMABUSO15
CELL_S[4].OUT_SEC_TMIN[14]PPC405.TSTISOCMABUSO14
CELL_S[4].OUT_SEC_TMIN[15]PPC405.TSTISOCMABUSO13
CELL_S[5].IMUX_TI[0]PPC405.ISARCVALUE4
CELL_S[5].IMUX_TI[1]PPC405.ISARCVALUE5
CELL_S[5].IMUX_TS[0]PPC405.ISARCVALUE6
CELL_S[5].IMUX_TS[1]PPC405.ISARCVALUE7
CELL_S[5].IMUX_G0_DATA[0]PPC405.ISCNTLVALUE4
CELL_S[5].IMUX_G0_DATA[1]PPC405.TSTISOCMRDATAI39
CELL_S[5].IMUX_G0_DATA[2]PPC405.LSSDC405SCANIN2
CELL_S[5].IMUX_G1_DATA[0]PPC405.ISCNTLVALUE5
CELL_S[5].IMUX_G1_DATA[1]PPC405.TSTISOCMRDATAI40
CELL_S[5].IMUX_G1_DATA[2]PPC405.LSSDC405SCANIN3
CELL_S[5].IMUX_G2_DATA[0]PPC405.TSTISOCMRDATAI37
CELL_S[5].IMUX_G2_DATA[1]PPC405.TSTISOCMRDATAI59
CELL_S[5].IMUX_G3_DATA[0]PPC405.TSTISOCMRDATAI38
CELL_S[5].IMUX_G3_DATA[1]PPC405.TSTISOCMRDATAI60
CELL_S[5].OUT_FAN_TMIN[0]PPC405.ISOCMBRAMWRDBUS24
CELL_S[5].OUT_FAN_TMIN[1]PPC405.ISOCMBRAMWRDBUS25
CELL_S[5].OUT_FAN_TMIN[2]PPC405.ISOCMBRAMWRDBUS26
CELL_S[5].OUT_FAN_TMIN[3]PPC405.ISOCMBRAMWRDBUS27
CELL_S[5].OUT_FAN_TMIN[4]PPC405.ISOCMBRAMWRDBUS28
CELL_S[5].OUT_FAN_TMIN[5]PPC405.ISOCMBRAMWRDBUS29
CELL_S[5].OUT_FAN_TMIN[6]PPC405.ISOCMBRAMWRDBUS30
CELL_S[5].OUT_FAN_TMIN[7]PPC405.ISOCMBRAMWRDBUS31
CELL_S[5].OUT_SEC_TMIN[10]PPC405.C405LSSDSCANOUT7
CELL_S[5].OUT_SEC_TMIN[11]PPC405.C405LSSDSCANOUT6
CELL_S[5].OUT_SEC_TMIN[12]PPC405.TSTISOCMABUSO20
CELL_S[5].OUT_SEC_TMIN[13]PPC405.TSTISOCMABUSO19
CELL_S[5].OUT_SEC_TMIN[14]PPC405.TSTISOCMABUSO18
CELL_S[5].OUT_SEC_TMIN[15]PPC405.TSTISOCMABUSO17
CELL_S[6].IMUX_G0_DATA[0]PPC405.BRAMISOCMRDDBUS32
CELL_S[6].IMUX_G0_DATA[1]PPC405.BRAMISOCMRDDBUS36
CELL_S[6].IMUX_G0_DATA[2]PPC405.BRAMISOCMRDDBUS40
CELL_S[6].IMUX_G0_DATA[3]PPC405.BRAMISOCMRDDBUS44
CELL_S[6].IMUX_G0_DATA[4]PPC405.TSTISOCMRDATAI41
CELL_S[6].IMUX_G0_DATA[5]PPC405.TSTISOCMRDATAI61
CELL_S[6].IMUX_G1_DATA[0]PPC405.BRAMISOCMRDDBUS33
CELL_S[6].IMUX_G1_DATA[1]PPC405.BRAMISOCMRDDBUS37
CELL_S[6].IMUX_G1_DATA[2]PPC405.BRAMISOCMRDDBUS41
CELL_S[6].IMUX_G1_DATA[3]PPC405.BRAMISOCMRDDBUS45
CELL_S[6].IMUX_G1_DATA[4]PPC405.TSTISOCMRDATAI42
CELL_S[6].IMUX_G1_DATA[5]PPC405.TSTISOCMRDATAI62
CELL_S[6].IMUX_G2_DATA[0]PPC405.BRAMISOCMRDDBUS34
CELL_S[6].IMUX_G2_DATA[1]PPC405.BRAMISOCMRDDBUS38
CELL_S[6].IMUX_G2_DATA[2]PPC405.BRAMISOCMRDDBUS42
CELL_S[6].IMUX_G2_DATA[3]PPC405.BRAMISOCMRDDBUS46
CELL_S[6].IMUX_G2_DATA[4]PPC405.TSTISOCMRDATAI43
CELL_S[6].IMUX_G2_DATA[5]PPC405.LSSDC405SCANIN4
CELL_S[6].IMUX_G3_DATA[0]PPC405.BRAMISOCMRDDBUS35
CELL_S[6].IMUX_G3_DATA[1]PPC405.BRAMISOCMRDDBUS39
CELL_S[6].IMUX_G3_DATA[2]PPC405.BRAMISOCMRDDBUS43
CELL_S[6].IMUX_G3_DATA[3]PPC405.BRAMISOCMRDDBUS47
CELL_S[6].IMUX_G3_DATA[4]PPC405.TSTISOCMRDATAI44
CELL_S[6].IMUX_G3_DATA[5]PPC405.LSSDC405SCANIN5
CELL_S[6].OUT_FAN_TMIN[0]PPC405.ISOCMBRAMRDABUS8
CELL_S[6].OUT_FAN_TMIN[1]PPC405.ISOCMBRAMRDABUS9
CELL_S[6].OUT_FAN_TMIN[2]PPC405.ISOCMBRAMRDABUS10
CELL_S[6].OUT_FAN_TMIN[3]PPC405.ISOCMBRAMRDABUS11
CELL_S[6].OUT_FAN_TMIN[4]PPC405.ISOCMBRAMRDABUS12
CELL_S[6].OUT_FAN_TMIN[5]PPC405.ISOCMBRAMRDABUS13
CELL_S[6].OUT_FAN_TMIN[6]PPC405.ISOCMBRAMRDABUS14
CELL_S[6].OUT_FAN_TMIN[7]PPC405.ISOCMBRAMRDABUS15
CELL_S[6].OUT_SEC_TMIN[8]PPC405.TSTISOCMABUSO24
CELL_S[6].OUT_SEC_TMIN[9]PPC405.TSTISOCMABUSO23
CELL_S[6].OUT_SEC_TMIN[10]PPC405.TSTISOCMABUSO22
CELL_S[6].OUT_SEC_TMIN[11]PPC405.TSTISOCMABUSO21
CELL_S[6].OUT_SEC_TMIN[12]PPC405.ISOCMBRAMRDABUS19
CELL_S[6].OUT_SEC_TMIN[13]PPC405.ISOCMBRAMRDABUS18
CELL_S[6].OUT_SEC_TMIN[14]PPC405.ISOCMBRAMRDABUS17
CELL_S[6].OUT_SEC_TMIN[15]PPC405.ISOCMBRAMRDABUS16
CELL_S[6].OUT_TEST[0]PPC405.C405LSSDSCANOUT8
CELL_S[6].OUT_TEST[2]PPC405.C405LSSDSCANOUT9
CELL_S[7].IMUX_G0_DATA[0]PPC405.BRAMISOCMRDDBUS48
CELL_S[7].IMUX_G0_DATA[1]PPC405.BRAMISOCMRDDBUS52
CELL_S[7].IMUX_G0_DATA[2]PPC405.BRAMISOCMRDDBUS56
CELL_S[7].IMUX_G0_DATA[3]PPC405.BRAMISOCMRDDBUS60
CELL_S[7].IMUX_G0_DATA[4]PPC405.TSTISOCMRDATAI45
CELL_S[7].IMUX_G0_DATA[5]PPC405.TSTISOCMRDATAI63
CELL_S[7].IMUX_G1_DATA[0]PPC405.BRAMISOCMRDDBUS49
CELL_S[7].IMUX_G1_DATA[1]PPC405.BRAMISOCMRDDBUS53
CELL_S[7].IMUX_G1_DATA[2]PPC405.BRAMISOCMRDDBUS57
CELL_S[7].IMUX_G1_DATA[3]PPC405.BRAMISOCMRDDBUS61
CELL_S[7].IMUX_G1_DATA[4]PPC405.TSTISOCMRDATAI46
CELL_S[7].IMUX_G1_DATA[5]PPC405.LSSDC405ACLK
CELL_S[7].IMUX_G2_DATA[0]PPC405.BRAMISOCMRDDBUS50
CELL_S[7].IMUX_G2_DATA[1]PPC405.BRAMISOCMRDDBUS54
CELL_S[7].IMUX_G2_DATA[2]PPC405.BRAMISOCMRDDBUS58
CELL_S[7].IMUX_G2_DATA[3]PPC405.BRAMISOCMRDDBUS62
CELL_S[7].IMUX_G2_DATA[4]PPC405.TSTISOCMRDATAI47
CELL_S[7].IMUX_G2_DATA[5]PPC405.LSSDC405SCANIN6
CELL_S[7].IMUX_G3_DATA[0]PPC405.BRAMISOCMRDDBUS51
CELL_S[7].IMUX_G3_DATA[1]PPC405.BRAMISOCMRDDBUS55
CELL_S[7].IMUX_G3_DATA[2]PPC405.BRAMISOCMRDDBUS59
CELL_S[7].IMUX_G3_DATA[3]PPC405.BRAMISOCMRDDBUS63
CELL_S[7].IMUX_G3_DATA[4]PPC405.TSTISOCMRDATAI48
CELL_S[7].IMUX_G3_DATA[5]PPC405.LSSDC405SCANIN7
CELL_S[7].IMUX_BRAM_ADDRA[0]PPC405.ISOCMBRAMWRABUS15
CELL_S[7].IMUX_BRAM_ADDRA[1]PPC405.ISOCMBRAMWRABUS16
CELL_S[7].IMUX_BRAM_ADDRA[2]PPC405.ISOCMBRAMWRABUS17
CELL_S[7].IMUX_BRAM_ADDRA[3]PPC405.ISOCMBRAMWRABUS18
CELL_S[7].IMUX_BRAM_ADDRA_S1[0]PPC405.ISOCMBRAMWRABUS19
CELL_S[7].IMUX_BRAM_ADDRA_S1[1]PPC405.ISOCMBRAMWRABUS20
CELL_S[7].IMUX_BRAM_ADDRA_S1[2]PPC405.ISOCMBRAMWRABUS21
CELL_S[7].IMUX_BRAM_ADDRA_S1[3]PPC405.ISOCMBRAMWRABUS22
CELL_S[7].IMUX_BRAM_ADDRA_S2[0]PPC405.ISOCMBRAMWRABUS23
CELL_S[7].IMUX_BRAM_ADDRA_S2[1]PPC405.ISOCMBRAMWRABUS24
CELL_S[7].IMUX_BRAM_ADDRA_S2[2]PPC405.ISOCMBRAMWRABUS25
CELL_S[7].IMUX_BRAM_ADDRA_S2[3]PPC405.ISOCMBRAMWRABUS26
CELL_S[7].IMUX_BRAM_ADDRA_S3[0]PPC405.ISOCMBRAMWRABUS27
CELL_S[7].IMUX_BRAM_ADDRA_S3[1]PPC405.ISOCMBRAMWRABUS28
CELL_S[7].IMUX_BRAM_ADDRB[0]PPC405.ISOCMBRAMRDABUS15
CELL_S[7].IMUX_BRAM_ADDRB[1]PPC405.ISOCMBRAMRDABUS16
CELL_S[7].IMUX_BRAM_ADDRB[2]PPC405.ISOCMBRAMRDABUS17
CELL_S[7].IMUX_BRAM_ADDRB[3]PPC405.ISOCMBRAMRDABUS18
CELL_S[7].IMUX_BRAM_ADDRB_S1[0]PPC405.ISOCMBRAMRDABUS19
CELL_S[7].IMUX_BRAM_ADDRB_S1[1]PPC405.ISOCMBRAMRDABUS20
CELL_S[7].IMUX_BRAM_ADDRB_S1[2]PPC405.ISOCMBRAMRDABUS21
CELL_S[7].IMUX_BRAM_ADDRB_S1[3]PPC405.ISOCMBRAMRDABUS22
CELL_S[7].IMUX_BRAM_ADDRB_S2[0]PPC405.ISOCMBRAMRDABUS23
CELL_S[7].IMUX_BRAM_ADDRB_S2[1]PPC405.ISOCMBRAMRDABUS24
CELL_S[7].IMUX_BRAM_ADDRB_S2[2]PPC405.ISOCMBRAMRDABUS25
CELL_S[7].IMUX_BRAM_ADDRB_S2[3]PPC405.ISOCMBRAMRDABUS26
CELL_S[7].IMUX_BRAM_ADDRB_S3[0]PPC405.ISOCMBRAMRDABUS27
CELL_S[7].IMUX_BRAM_ADDRB_S3[1]PPC405.ISOCMBRAMRDABUS28
CELL_S[7].OUT_FAN_TMIN[0]PPC405.ISOCMBRAMRDABUS20
CELL_S[7].OUT_FAN_TMIN[1]PPC405.ISOCMBRAMRDABUS21
CELL_S[7].OUT_FAN_TMIN[2]PPC405.ISOCMBRAMRDABUS22
CELL_S[7].OUT_FAN_TMIN[3]PPC405.ISOCMBRAMRDABUS23
CELL_S[7].OUT_FAN_TMIN[4]PPC405.ISOCMBRAMRDABUS24
CELL_S[7].OUT_FAN_TMIN[5]PPC405.ISOCMBRAMRDABUS25
CELL_S[7].OUT_FAN_TMIN[6]PPC405.ISOCMBRAMRDABUS26
CELL_S[7].OUT_FAN_TMIN[7]PPC405.ISOCMBRAMRDABUS27
CELL_S[7].OUT_SEC_TMIN[9]PPC405.C405ISOCMCONTEXTSYNC
CELL_S[7].OUT_SEC_TMIN[10]PPC405.C405ISOCMCACHEABLE
CELL_S[7].OUT_SEC_TMIN[11]PPC405.TSTISOCMABUSO28
CELL_S[7].OUT_SEC_TMIN[12]PPC405.TSTISOCMABUSO27
CELL_S[7].OUT_SEC_TMIN[13]PPC405.TSTISOCMABUSO26
CELL_S[7].OUT_SEC_TMIN[14]PPC405.TSTISOCMABUSO25
CELL_S[7].OUT_SEC_TMIN[15]PPC405.ISOCMBRAMRDABUS28
CELL_N[0].IMUX_G0_DATA[0]PPC405.BRAMDSOCMRDDBUS0
CELL_N[0].IMUX_G0_DATA[1]PPC405.BRAMDSOCMRDDBUS4
CELL_N[0].IMUX_G0_DATA[2]PPC405.BRAMDSOCMRDDBUS8
CELL_N[0].IMUX_G0_DATA[3]PPC405.BRAMDSOCMRDDBUS12
CELL_N[0].IMUX_G1_DATA[0]PPC405.BRAMDSOCMRDDBUS1
CELL_N[0].IMUX_G1_DATA[1]PPC405.BRAMDSOCMRDDBUS5
CELL_N[0].IMUX_G1_DATA[2]PPC405.BRAMDSOCMRDDBUS9
CELL_N[0].IMUX_G1_DATA[3]PPC405.BRAMDSOCMRDDBUS13
CELL_N[0].IMUX_G2_DATA[0]PPC405.BRAMDSOCMRDDBUS2
CELL_N[0].IMUX_G2_DATA[1]PPC405.BRAMDSOCMRDDBUS6
CELL_N[0].IMUX_G2_DATA[2]PPC405.BRAMDSOCMRDDBUS10
CELL_N[0].IMUX_G2_DATA[3]PPC405.BRAMDSOCMRDDBUS14
CELL_N[0].IMUX_G3_DATA[0]PPC405.BRAMDSOCMRDDBUS3
CELL_N[0].IMUX_G3_DATA[1]PPC405.BRAMDSOCMRDDBUS7
CELL_N[0].IMUX_G3_DATA[2]PPC405.BRAMDSOCMRDDBUS11
CELL_N[0].IMUX_G3_DATA[3]PPC405.BRAMDSOCMRDDBUS15
CELL_N[0].IMUX_BRAM_ADDRA[0]PPC405.DSOCMBRAMABUS28
CELL_N[0].IMUX_BRAM_ADDRA[1]PPC405.DSOCMBRAMABUS29
CELL_N[0].IMUX_BRAM_ADDRA_N1[0]PPC405.DSOCMBRAMABUS24
CELL_N[0].IMUX_BRAM_ADDRA_N1[1]PPC405.DSOCMBRAMABUS25
CELL_N[0].IMUX_BRAM_ADDRA_N1[2]PPC405.DSOCMBRAMABUS26
CELL_N[0].IMUX_BRAM_ADDRA_N1[3]PPC405.DSOCMBRAMABUS27
CELL_N[0].IMUX_BRAM_ADDRA_N2[0]PPC405.DSOCMBRAMABUS20
CELL_N[0].IMUX_BRAM_ADDRA_N2[1]PPC405.DSOCMBRAMABUS21
CELL_N[0].IMUX_BRAM_ADDRA_N2[2]PPC405.DSOCMBRAMABUS22
CELL_N[0].IMUX_BRAM_ADDRA_N2[3]PPC405.DSOCMBRAMABUS23
CELL_N[0].IMUX_BRAM_ADDRA_N3[0]PPC405.DSOCMBRAMABUS16
CELL_N[0].IMUX_BRAM_ADDRA_N3[1]PPC405.DSOCMBRAMABUS17
CELL_N[0].IMUX_BRAM_ADDRA_N3[2]PPC405.DSOCMBRAMABUS18
CELL_N[0].IMUX_BRAM_ADDRA_N3[3]PPC405.DSOCMBRAMABUS19
CELL_N[0].OUT_FAN_TMIN[0]PPC405.DSOCMBRAMBYTEWRITE0
CELL_N[0].OUT_FAN_TMIN[1]PPC405.DSOCMBRAMBYTEWRITE1
CELL_N[0].OUT_FAN_TMIN[2]PPC405.DSOCMBRAMBYTEWRITE2
CELL_N[0].OUT_FAN_TMIN[3]PPC405.DSOCMBRAMBYTEWRITE3
CELL_N[0].OUT_FAN_TMIN[4]PPC405.C405TRCODDEXECUTIONSTATUS1
CELL_N[0].OUT_FAN_TMIN[5]PPC405.C405TRCTRACESTATUS0
CELL_N[0].OUT_FAN_TMIN[6]PPC405.C405TRCTRACESTATUS3
CELL_N[0].OUT_FAN_TMIN[7]PPC405.C405TRCTRIGGEREVENTOUT
CELL_N[0].OUT_SEC_TMIN[9]PPC405.TSTDSOCMWRDBUSO28
CELL_N[0].OUT_SEC_TMIN[10]PPC405.TSTDSOCMWRDBUSO15
CELL_N[0].OUT_SEC_TMIN[11]PPC405.TSTDSOCMWRDBUSO14
CELL_N[0].OUT_SEC_TMIN[12]PPC405.TSTDSOCMWRDBUSO1
CELL_N[0].OUT_SEC_TMIN[13]PPC405.C405JTGSHIFTDR
CELL_N[0].OUT_SEC_TMIN[14]PPC405.C405TRCTRIGGEREVENTTYPE3
CELL_N[0].OUT_SEC_TMIN[15]PPC405.C405TRCTRIGGEREVENTTYPE2
CELL_N[1].IMUX_CLK[0]PPC405.JTGC405TCK
CELL_N[1].IMUX_TI[0]PPC405.DSCNTLVALUE0
CELL_N[1].IMUX_TI[1]PPC405.DSCNTLVALUE1
CELL_N[1].IMUX_TS[0]PPC405.DSCNTLVALUE2
CELL_N[1].IMUX_TS[1]PPC405.DSCNTLVALUE3
CELL_N[1].IMUX_G0_DATA[0]PPC405.TRCC405TRACEDISABLE
CELL_N[1].IMUX_G1_DATA[0]PPC405.JTGC405TDI
CELL_N[1].IMUX_G2_DATA[0]PPC405.JTGC405TMS
CELL_N[1].OUT_FAN_TMIN[0]PPC405.DSOCMBRAMWRDBUS0
CELL_N[1].OUT_FAN_TMIN[1]PPC405.DSOCMBRAMWRDBUS1
CELL_N[1].OUT_FAN_TMIN[2]PPC405.DSOCMBRAMWRDBUS2
CELL_N[1].OUT_FAN_TMIN[3]PPC405.DSOCMBRAMWRDBUS3
CELL_N[1].OUT_FAN_TMIN[4]PPC405.DSOCMBRAMWRDBUS4
CELL_N[1].OUT_FAN_TMIN[5]PPC405.DSOCMBRAMWRDBUS5
CELL_N[1].OUT_FAN_TMIN[6]PPC405.DSOCMBRAMWRDBUS6
CELL_N[1].OUT_FAN_TMIN[7]PPC405.DSOCMBRAMWRDBUS7
CELL_N[1].OUT_SEC_TMIN[8]PPC405.TSTDSOCMWRDBUSO3
CELL_N[1].OUT_SEC_TMIN[9]PPC405.TSTDSOCMWRDBUSO2
CELL_N[1].OUT_SEC_TMIN[10]PPC405.TSTDSOCMABUSO14
CELL_N[1].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO13
CELL_N[1].OUT_SEC_TMIN[12]PPC405.TSTDSOCMABUSO0
CELL_N[1].OUT_SEC_TMIN[13]PPC405.C405JTGTDO
CELL_N[1].OUT_SEC_TMIN[14]PPC405.C405TRCTRIGGEREVENTTYPE5
CELL_N[1].OUT_SEC_TMIN[15]PPC405.C405TRCTRIGGEREVENTTYPE4
CELL_N[1].OUT_TEST[0]PPC405.TSTDSOCMWRDBUSO16
CELL_N[1].OUT_TEST[2]PPC405.TSTDSOCMWRDBUSO17
CELL_N[1].OUT_TEST[4]PPC405.TSTDSOCMWRDBUSO29
CELL_N[2].IMUX_TI[0]PPC405.TIEDSOCMDCRADDR0
CELL_N[2].IMUX_TI[1]PPC405.DSCNTLVALUE4
CELL_N[2].IMUX_TS[0]PPC405.DSCNTLVALUE5
CELL_N[2].IMUX_TS[1]PPC405.DSCNTLVALUE6
CELL_N[2].IMUX_G0_DATA[0]PPC405.TRCC405TRIGGEREVENTIN
CELL_N[2].IMUX_G1_DATA[0]PPC405.JTGC405BNDSCANTDO
CELL_N[2].IMUX_G2_DATA[0]PPC405.TSTTRSTNEGI
CELL_N[2].IMUX_G3_DATA[0]PPC405.BRAMDSOCMRDDACK
CELL_N[2].OUT_FAN_TMIN[0]PPC405.DSOCMBRAMWRDBUS8
CELL_N[2].OUT_FAN_TMIN[1]PPC405.DSOCMBRAMWRDBUS9
CELL_N[2].OUT_FAN_TMIN[2]PPC405.DSOCMBRAMWRDBUS10
CELL_N[2].OUT_FAN_TMIN[3]PPC405.DSOCMBRAMWRDBUS11
CELL_N[2].OUT_FAN_TMIN[4]PPC405.DSOCMBRAMWRDBUS12
CELL_N[2].OUT_FAN_TMIN[5]PPC405.DSOCMBRAMWRDBUS13
CELL_N[2].OUT_FAN_TMIN[6]PPC405.DSOCMBRAMWRDBUS14
CELL_N[2].OUT_FAN_TMIN[7]PPC405.DSOCMBRAMWRDBUS15
CELL_N[2].OUT_SEC_TMIN[8]PPC405.TSTDSOCMWRDBUSO5
CELL_N[2].OUT_SEC_TMIN[9]PPC405.TSTDSOCMWRDBUSO4
CELL_N[2].OUT_SEC_TMIN[10]PPC405.TSTDSOCMABUSO16
CELL_N[2].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO15
CELL_N[2].OUT_SEC_TMIN[12]PPC405.TSTDSOCMABUSO1
CELL_N[2].OUT_SEC_TMIN[13]PPC405.C405JTGTDOEN
CELL_N[2].OUT_SEC_TMIN[14]PPC405.C405TRCTRIGGEREVENTTYPE7
CELL_N[2].OUT_SEC_TMIN[15]PPC405.C405TRCTRIGGEREVENTTYPE6
CELL_N[2].OUT_TEST[0]PPC405.TSTDSOCMWRDBUSO18
CELL_N[2].OUT_TEST[2]PPC405.TSTDSOCMWRDBUSO19
CELL_N[2].OUT_TEST[4]PPC405.TSTDSOCMWRDBUSO30
CELL_N[3].IMUX_CLK[0]PPC405.BRAMDSOCMCLK
CELL_N[3].IMUX_TI[0]PPC405.TIEDSOCMDCRADDR1
CELL_N[3].IMUX_TI[1]PPC405.TIEDSOCMDCRADDR2
CELL_N[3].IMUX_TS[0]PPC405.TIEDSOCMDCRADDR3
CELL_N[3].IMUX_TS[1]PPC405.TIEDSOCMDCRADDR4
CELL_N[3].OUT_FAN_TMIN[0]PPC405.DSOCMBRAMWRDBUS16
CELL_N[3].OUT_FAN_TMIN[1]PPC405.DSOCMBRAMWRDBUS17
CELL_N[3].OUT_FAN_TMIN[2]PPC405.DSOCMBRAMWRDBUS18
CELL_N[3].OUT_FAN_TMIN[3]PPC405.DSOCMBRAMWRDBUS19
CELL_N[3].OUT_FAN_TMIN[4]PPC405.DSOCMBRAMWRDBUS20
CELL_N[3].OUT_FAN_TMIN[5]PPC405.DSOCMBRAMWRDBUS21
CELL_N[3].OUT_FAN_TMIN[6]PPC405.DSOCMBRAMWRDBUS22
CELL_N[3].OUT_FAN_TMIN[7]PPC405.DSOCMBRAMWRDBUS23
CELL_N[3].OUT_SEC_TMIN[8]PPC405.TSTDSOCMWRDBUSO7
CELL_N[3].OUT_SEC_TMIN[9]PPC405.TSTDSOCMWRDBUSO6
CELL_N[3].OUT_SEC_TMIN[10]PPC405.TSTDSOCMABUSO18
CELL_N[3].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO17
CELL_N[3].OUT_SEC_TMIN[12]PPC405.TSTDSOCMABUSO2
CELL_N[3].OUT_SEC_TMIN[13]PPC405.C405JTGUPDATEDR
CELL_N[3].OUT_SEC_TMIN[14]PPC405.C405TRCTRIGGEREVENTTYPE9
CELL_N[3].OUT_SEC_TMIN[15]PPC405.C405TRCTRIGGEREVENTTYPE8
CELL_N[3].OUT_TEST[0]PPC405.TSTDSOCMWRDBUSO20
CELL_N[3].OUT_TEST[2]PPC405.TSTDSOCMWRDBUSO21
CELL_N[3].OUT_TEST[4]PPC405.TSTDSOCMWRDBUSO31
CELL_N[4].IMUX_TI[0]PPC405.TIEDSOCMDCRADDR5
CELL_N[4].IMUX_TI[1]PPC405.TIEDSOCMDCRADDR6
CELL_N[4].IMUX_TS[0]PPC405.TIEDSOCMDCRADDR7
CELL_N[4].IMUX_TS[1]PPC405.DSCNTLVALUE7
CELL_N[4].OUT_FAN_TMIN[0]PPC405.DSOCMBRAMWRDBUS24
CELL_N[4].OUT_FAN_TMIN[1]PPC405.DSOCMBRAMWRDBUS25
CELL_N[4].OUT_FAN_TMIN[2]PPC405.DSOCMBRAMWRDBUS26
CELL_N[4].OUT_FAN_TMIN[3]PPC405.DSOCMBRAMWRDBUS27
CELL_N[4].OUT_FAN_TMIN[4]PPC405.DSOCMBRAMWRDBUS28
CELL_N[4].OUT_FAN_TMIN[5]PPC405.DSOCMBRAMWRDBUS29
CELL_N[4].OUT_FAN_TMIN[6]PPC405.DSOCMBRAMWRDBUS30
CELL_N[4].OUT_FAN_TMIN[7]PPC405.DSOCMBRAMWRDBUS31
CELL_N[4].OUT_SEC_TMIN[8]PPC405.TSTDSOCMWRDBUSO8
CELL_N[4].OUT_SEC_TMIN[9]PPC405.TSTDSOCMABUSO20
CELL_N[4].OUT_SEC_TMIN[10]PPC405.TSTDSOCMABUSO19
CELL_N[4].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO4
CELL_N[4].OUT_SEC_TMIN[12]PPC405.TSTDSOCMABUSO3
CELL_N[4].OUT_SEC_TMIN[13]PPC405.DSOCMRDADDRVALID
CELL_N[4].OUT_SEC_TMIN[14]PPC405.C405JTGCAPTUREDR
CELL_N[4].OUT_SEC_TMIN[15]PPC405.C405TRCTRIGGEREVENTTYPE10
CELL_N[4].OUT_TEST[0]PPC405.TSTDSOCMWRDBUSO9
CELL_N[4].OUT_TEST[2]PPC405.TSTDSOCMWRDBUSO22
CELL_N[4].OUT_TEST[4]PPC405.TSTDSOCMWRDBUSO23
CELL_N[5].IMUX_TI[0]PPC405.DSARCVALUE0
CELL_N[5].IMUX_TI[1]PPC405.DSARCVALUE1
CELL_N[5].IMUX_TS[0]PPC405.DSARCVALUE2
CELL_N[5].IMUX_TS[1]PPC405.DSARCVALUE3
CELL_N[5].OUT_FAN_TMIN[0]PPC405.DSOCMBRAMABUS8
CELL_N[5].OUT_FAN_TMIN[1]PPC405.DSOCMBRAMABUS9
CELL_N[5].OUT_FAN_TMIN[2]PPC405.DSOCMBRAMABUS10
CELL_N[5].OUT_FAN_TMIN[3]PPC405.DSOCMBRAMABUS11
CELL_N[5].OUT_FAN_TMIN[4]PPC405.DSOCMBRAMABUS12
CELL_N[5].OUT_FAN_TMIN[5]PPC405.DSOCMBRAMABUS13
CELL_N[5].OUT_FAN_TMIN[6]PPC405.DSOCMBRAMABUS14
CELL_N[5].OUT_FAN_TMIN[7]PPC405.DSOCMBRAMABUS15
CELL_N[5].OUT_SEC_TMIN[8]PPC405.TSTDSOCMABUSO8
CELL_N[5].OUT_SEC_TMIN[9]PPC405.TSTDSOCMABUSO7
CELL_N[5].OUT_SEC_TMIN[10]PPC405.TSTDSOCMABUSO6
CELL_N[5].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO5
CELL_N[5].OUT_SEC_TMIN[12]PPC405.DSOCMBRAMABUS19
CELL_N[5].OUT_SEC_TMIN[13]PPC405.DSOCMBRAMABUS18
CELL_N[5].OUT_SEC_TMIN[14]PPC405.DSOCMBRAMABUS17
CELL_N[5].OUT_SEC_TMIN[15]PPC405.DSOCMBRAMABUS16
CELL_N[5].OUT_TEST[0]PPC405.TSTDSOCMABUSO21
CELL_N[5].OUT_TEST[2]PPC405.TSTDSOCMABUSO22
CELL_N[5].OUT_TEST[4]PPC405.TSTDSOCMWRDBUSO10
CELL_N[5].OUT_TEST[6]PPC405.TSTDSOCMWRDBUSO11
CELL_N[5].OUT_TEST[8]PPC405.TSTDSOCMWRDBUSO24
CELL_N[5].OUT_TEST[10]PPC405.TSTDSOCMWRDBUSO25
CELL_N[6].IMUX_TI[0]PPC405.DSARCVALUE4
CELL_N[6].IMUX_TI[1]PPC405.DSARCVALUE5
CELL_N[6].IMUX_TS[0]PPC405.DSARCVALUE6
CELL_N[6].IMUX_TS[1]PPC405.DSARCVALUE7
CELL_N[6].OUT_FAN_TMIN[0]PPC405.DSOCMBRAMABUS20
CELL_N[6].OUT_FAN_TMIN[1]PPC405.DSOCMBRAMABUS21
CELL_N[6].OUT_FAN_TMIN[2]PPC405.DSOCMBRAMABUS22
CELL_N[6].OUT_FAN_TMIN[3]PPC405.DSOCMBRAMABUS23
CELL_N[6].OUT_FAN_TMIN[4]PPC405.DSOCMBRAMABUS24
CELL_N[6].OUT_FAN_TMIN[5]PPC405.DSOCMBRAMABUS25
CELL_N[6].OUT_FAN_TMIN[6]PPC405.DSOCMBRAMABUS26
CELL_N[6].OUT_FAN_TMIN[7]PPC405.DSOCMBRAMABUS27
CELL_N[6].OUT_SEC_TMIN[8]PPC405.TSTDSOCMABUSO12
CELL_N[6].OUT_SEC_TMIN[9]PPC405.TSTDSOCMABUSO11
CELL_N[6].OUT_SEC_TMIN[10]PPC405.TSTDSOCMABUSO10
CELL_N[6].OUT_SEC_TMIN[11]PPC405.TSTDSOCMABUSO9
CELL_N[6].OUT_SEC_TMIN[12]PPC405.DSOCMBUSY
CELL_N[6].OUT_SEC_TMIN[13]PPC405.DSOCMBRAMEN
CELL_N[6].OUT_SEC_TMIN[14]PPC405.DSOCMBRAMABUS29
CELL_N[6].OUT_SEC_TMIN[15]PPC405.DSOCMBRAMABUS28
CELL_N[6].OUT_TEST[0]PPC405.TSTDSOCMABUSO23
CELL_N[6].OUT_TEST[2]PPC405.TSTDSOCMWRDBUSO0
CELL_N[6].OUT_TEST[4]PPC405.TSTDSOCMWRDBUSO12
CELL_N[6].OUT_TEST[6]PPC405.TSTDSOCMWRDBUSO13
CELL_N[6].OUT_TEST[8]PPC405.TSTDSOCMWRDBUSO26
CELL_N[6].OUT_TEST[10]PPC405.TSTDSOCMWRDBUSO27
CELL_N[7].IMUX_G0_DATA[0]PPC405.BRAMDSOCMRDDBUS16
CELL_N[7].IMUX_G0_DATA[1]PPC405.BRAMDSOCMRDDBUS20
CELL_N[7].IMUX_G0_DATA[2]PPC405.BRAMDSOCMRDDBUS24
CELL_N[7].IMUX_G0_DATA[3]PPC405.BRAMDSOCMRDDBUS28
CELL_N[7].IMUX_G1_DATA[0]PPC405.BRAMDSOCMRDDBUS17
CELL_N[7].IMUX_G1_DATA[1]PPC405.BRAMDSOCMRDDBUS21
CELL_N[7].IMUX_G1_DATA[2]PPC405.BRAMDSOCMRDDBUS25
CELL_N[7].IMUX_G1_DATA[3]PPC405.BRAMDSOCMRDDBUS29
CELL_N[7].IMUX_G2_DATA[0]PPC405.BRAMDSOCMRDDBUS18
CELL_N[7].IMUX_G2_DATA[1]PPC405.BRAMDSOCMRDDBUS22
CELL_N[7].IMUX_G2_DATA[2]PPC405.BRAMDSOCMRDDBUS26
CELL_N[7].IMUX_G2_DATA[3]PPC405.BRAMDSOCMRDDBUS30
CELL_N[7].IMUX_G3_DATA[0]PPC405.BRAMDSOCMRDDBUS19
CELL_N[7].IMUX_G3_DATA[1]PPC405.BRAMDSOCMRDDBUS23
CELL_N[7].IMUX_G3_DATA[2]PPC405.BRAMDSOCMRDDBUS27
CELL_N[7].IMUX_G3_DATA[3]PPC405.BRAMDSOCMRDDBUS31
CELL_N[7].IMUX_BRAM_ADDRA[0]PPC405.DSOCMBRAMABUS28
CELL_N[7].IMUX_BRAM_ADDRA[1]PPC405.DSOCMBRAMABUS29
CELL_N[7].IMUX_BRAM_ADDRA_N1[0]PPC405.DSOCMBRAMABUS24
CELL_N[7].IMUX_BRAM_ADDRA_N1[1]PPC405.DSOCMBRAMABUS25
CELL_N[7].IMUX_BRAM_ADDRA_N1[2]PPC405.DSOCMBRAMABUS26
CELL_N[7].IMUX_BRAM_ADDRA_N1[3]PPC405.DSOCMBRAMABUS27
CELL_N[7].IMUX_BRAM_ADDRA_N2[0]PPC405.DSOCMBRAMABUS20
CELL_N[7].IMUX_BRAM_ADDRA_N2[1]PPC405.DSOCMBRAMABUS21
CELL_N[7].IMUX_BRAM_ADDRA_N2[2]PPC405.DSOCMBRAMABUS22
CELL_N[7].IMUX_BRAM_ADDRA_N2[3]PPC405.DSOCMBRAMABUS23
CELL_N[7].IMUX_BRAM_ADDRA_N3[0]PPC405.DSOCMBRAMABUS16
CELL_N[7].IMUX_BRAM_ADDRA_N3[1]PPC405.DSOCMBRAMABUS17
CELL_N[7].IMUX_BRAM_ADDRA_N3[2]PPC405.DSOCMBRAMABUS18
CELL_N[7].IMUX_BRAM_ADDRA_N3[3]PPC405.DSOCMBRAMABUS19
CELL_N[7].OUT_FAN_TMIN[0]PPC405.C405TRCCYCLE
CELL_N[7].OUT_FAN_TMIN[1]PPC405.C405TRCEVENEXECUTIONSTATUS0
CELL_N[7].OUT_FAN_TMIN[2]PPC405.C405TRCEVENEXECUTIONSTATUS1
CELL_N[7].OUT_FAN_TMIN[3]PPC405.C405TRCODDEXECUTIONSTATUS0
CELL_N[7].OUT_FAN_TMIN[4]PPC405.C405TRCTRACESTATUS1
CELL_N[7].OUT_FAN_TMIN[5]PPC405.C405TRCTRACESTATUS2
CELL_N[7].OUT_FAN_TMIN[6]PPC405.C405TRCTRIGGEREVENTTYPE0
CELL_N[7].OUT_FAN_TMIN[7]PPC405.C405TRCTRIGGEREVENTTYPE1
CELL_N[7].OUT_SEC_TMIN[14]PPC405.C405JTGPGMOUT
CELL_N[7].OUT_SEC_TMIN[15]PPC405.C405JTGEXTEST