Multi-gigabit transceivers — Virtex 2 Pro

TODO: document

Tile GIGABIT.B

Cells: 5

Bel GT

virtex2 GIGABIT.B bel GT
Pin	Direction	Wires
CHBONDDONE	output	TCELL0:OUT.FAN4.TMIN
CHBONDI0	input	TCELL0:IMUX.G0.DATA0
CHBONDI1	input	TCELL0:IMUX.G1.DATA0
CHBONDI2	input	TCELL0:IMUX.G2.DATA0
CHBONDI3	input	TCELL0:IMUX.G3.DATA0
CHBONDO0	output	TCELL0:OUT.FAN0.TMIN
CHBONDO1	output	TCELL0:OUT.FAN1.TMIN
CHBONDO2	output	TCELL0:OUT.FAN2.TMIN
CHBONDO3	output	TCELL0:OUT.FAN3.TMIN
CONFIGENABLE	input	TCELL0:IMUX.G3.DATA2
CONFIGIN	input	TCELL0:IMUX.G2.DATA2
CONFIGOUT	output	TCELL0:OUT.SEC12.TMIN
ENCHANSYNC	input	TCELL0:IMUX.G0.DATA1
ENMCOMMAALIGN	input	TCELL1:IMUX.G1.DATA7
ENPCOMMAALIGN	input	TCELL1:IMUX.G1.DATA4
LOOPBACK0	input	TCELL0:IMUX.G0.DATA3
LOOPBACK1	input	TCELL0:IMUX.G1.DATA3
POWERDOWN	input	TCELL0:IMUX.G0.DATA2
REFCLK	input	TCELL0:IMUX.DCMCLK2
REFCLK2	input	TCELL0:IMUX.DCMCLK3
REFCLKSEL	input	TCELL0:IMUX.G1.DATA1
RXBUFSTATUS0	output	TCELL0:OUT.SEC15.TMIN
RXBUFSTATUS1	output	TCELL0:OUT.SEC14.TMIN
RXCHARISCOMMA0	output	TCELL1:OUT.SEC11.TMIN
RXCHARISCOMMA1	output	TCELL2:OUT.SEC11.TMIN
RXCHARISCOMMA2	output	TCELL3:OUT.SEC11.TMIN
RXCHARISCOMMA3	output	TCELL4:OUT.SEC11.TMIN
RXCHARISK0	output	TCELL1:OUT.SEC12.TMIN
RXCHARISK1	output	TCELL2:OUT.SEC12.TMIN
RXCHARISK2	output	TCELL3:OUT.SEC12.TMIN
RXCHARISK3	output	TCELL4:OUT.SEC12.TMIN
RXCHECKINGCRC	output	TCELL4:OUT.SEC8.TMIN
RXCLKCORCNT0	output	TCELL0:OUT.SEC11.TMIN
RXCLKCORCNT1	output	TCELL0:OUT.SEC10.TMIN
RXCLKCORCNT2	output	TCELL0:OUT.SEC9.TMIN
RXCOMMADET	output	TCELL0:OUT.FAN5.TMIN
RXCRCERR	output	TCELL3:OUT.SEC8.TMIN
RXDATA0	output	TCELL1:OUT.FAN0.TMIN
RXDATA1	output	TCELL1:OUT.FAN1.TMIN
RXDATA10	output	TCELL2:OUT.FAN2.TMIN
RXDATA11	output	TCELL2:OUT.FAN3.TMIN
RXDATA12	output	TCELL2:OUT.FAN4.TMIN
RXDATA13	output	TCELL2:OUT.FAN5.TMIN
RXDATA14	output	TCELL2:OUT.FAN6.TMIN
RXDATA15	output	TCELL2:OUT.FAN7.TMIN
RXDATA16	output	TCELL3:OUT.FAN0.TMIN
RXDATA17	output	TCELL3:OUT.FAN1.TMIN
RXDATA18	output	TCELL3:OUT.FAN2.TMIN
RXDATA19	output	TCELL3:OUT.FAN3.TMIN
RXDATA2	output	TCELL1:OUT.FAN2.TMIN
RXDATA20	output	TCELL3:OUT.FAN4.TMIN
RXDATA21	output	TCELL3:OUT.FAN5.TMIN
RXDATA22	output	TCELL3:OUT.FAN6.TMIN
RXDATA23	output	TCELL3:OUT.FAN7.TMIN
RXDATA24	output	TCELL4:OUT.FAN0.TMIN
RXDATA25	output	TCELL4:OUT.FAN1.TMIN
RXDATA26	output	TCELL4:OUT.FAN2.TMIN
RXDATA27	output	TCELL4:OUT.FAN3.TMIN
RXDATA28	output	TCELL4:OUT.FAN4.TMIN
RXDATA29	output	TCELL4:OUT.FAN5.TMIN
RXDATA3	output	TCELL1:OUT.FAN3.TMIN
RXDATA30	output	TCELL4:OUT.FAN6.TMIN
RXDATA31	output	TCELL4:OUT.FAN7.TMIN
RXDATA4	output	TCELL1:OUT.FAN4.TMIN
RXDATA5	output	TCELL1:OUT.FAN5.TMIN
RXDATA6	output	TCELL1:OUT.FAN6.TMIN
RXDATA7	output	TCELL1:OUT.FAN7.TMIN
RXDATA8	output	TCELL2:OUT.FAN0.TMIN
RXDATA9	output	TCELL2:OUT.FAN1.TMIN
RXDISPERR0	output	TCELL1:OUT.SEC14.TMIN
RXDISPERR1	output	TCELL2:OUT.SEC14.TMIN
RXDISPERR2	output	TCELL3:OUT.SEC14.TMIN
RXDISPERR3	output	TCELL4:OUT.SEC14.TMIN
RXLOSSOFSYNC0	output	TCELL1:OUT.SEC8.TMIN
RXLOSSOFSYNC1	output	TCELL2:OUT.SEC8.TMIN
RXNOTINTABLE0	output	TCELL1:OUT.SEC13.TMIN
RXNOTINTABLE1	output	TCELL2:OUT.SEC13.TMIN
RXNOTINTABLE2	output	TCELL3:OUT.SEC13.TMIN
RXNOTINTABLE3	output	TCELL4:OUT.SEC13.TMIN
RXPOLARITY	input	TCELL0:IMUX.G1.DATA2
RXREALIGN	output	TCELL0:OUT.SEC13.TMIN
RXRECCLK	output	TCELL0:OUT.FAN6.TMIN
RXRESET	input	TCELL0:IMUX.SR0
RXRUNDISP0	output	TCELL1:OUT.SEC15.TMIN
RXRUNDISP1	output	TCELL2:OUT.SEC15.TMIN
RXRUNDISP2	output	TCELL3:OUT.SEC15.TMIN
RXRUNDISP3	output	TCELL4:OUT.SEC15.TMIN
RXUSRCLK	input	TCELL0:IMUX.DCMCLK0
RXUSRCLK2	input	TCELL0:IMUX.DCMCLK1
TXBUFERR	output	TCELL0:OUT.FAN7.TMIN
TXBYPASS8B10B0	input	TCELL1:IMUX.G0.DATA2
TXBYPASS8B10B1	input	TCELL2:IMUX.G0.DATA2
TXBYPASS8B10B2	input	TCELL3:IMUX.G0.DATA2
TXBYPASS8B10B3	input	TCELL4:IMUX.G0.DATA2
TXCHARDISPMODE0	input	TCELL1:IMUX.G2.DATA2
TXCHARDISPMODE1	input	TCELL2:IMUX.G2.DATA2
TXCHARDISPMODE2	input	TCELL3:IMUX.G2.DATA2
TXCHARDISPMODE3	input	TCELL4:IMUX.G2.DATA2
TXCHARDISPVAL0	input	TCELL1:IMUX.G3.DATA2
TXCHARDISPVAL1	input	TCELL2:IMUX.G3.DATA2
TXCHARDISPVAL2	input	TCELL3:IMUX.G3.DATA2
TXCHARDISPVAL3	input	TCELL4:IMUX.G3.DATA2
TXCHARISK0	input	TCELL1:IMUX.G1.DATA2
TXCHARISK1	input	TCELL2:IMUX.G1.DATA2
TXCHARISK2	input	TCELL3:IMUX.G1.DATA2
TXCHARISK3	input	TCELL4:IMUX.G1.DATA2
TXDATA0	input	TCELL1:IMUX.G0.DATA0
TXDATA1	input	TCELL1:IMUX.G1.DATA0
TXDATA10	input	TCELL2:IMUX.G2.DATA0
TXDATA11	input	TCELL2:IMUX.G3.DATA0
TXDATA12	input	TCELL2:IMUX.G0.DATA1
TXDATA13	input	TCELL2:IMUX.G1.DATA1
TXDATA14	input	TCELL2:IMUX.G2.DATA1
TXDATA15	input	TCELL2:IMUX.G3.DATA1
TXDATA16	input	TCELL3:IMUX.G0.DATA0
TXDATA17	input	TCELL3:IMUX.G1.DATA0
TXDATA18	input	TCELL3:IMUX.G2.DATA0
TXDATA19	input	TCELL3:IMUX.G3.DATA0
TXDATA2	input	TCELL1:IMUX.G2.DATA0
TXDATA20	input	TCELL3:IMUX.G0.DATA1
TXDATA21	input	TCELL3:IMUX.G1.DATA1
TXDATA22	input	TCELL3:IMUX.G2.DATA1
TXDATA23	input	TCELL3:IMUX.G3.DATA1
TXDATA24	input	TCELL4:IMUX.G0.DATA0
TXDATA25	input	TCELL4:IMUX.G1.DATA0
TXDATA26	input	TCELL4:IMUX.G2.DATA0
TXDATA27	input	TCELL4:IMUX.G3.DATA0
TXDATA28	input	TCELL4:IMUX.G0.DATA1
TXDATA29	input	TCELL4:IMUX.G1.DATA1
TXDATA3	input	TCELL1:IMUX.G3.DATA0
TXDATA30	input	TCELL4:IMUX.G2.DATA1
TXDATA31	input	TCELL4:IMUX.G3.DATA1
TXDATA4	input	TCELL1:IMUX.G0.DATA1
TXDATA5	input	TCELL1:IMUX.G1.DATA1
TXDATA6	input	TCELL1:IMUX.G2.DATA1
TXDATA7	input	TCELL1:IMUX.G3.DATA1
TXDATA8	input	TCELL2:IMUX.G0.DATA0
TXDATA9	input	TCELL2:IMUX.G1.DATA0
TXFORCECRCERR	input	TCELL4:IMUX.G3.DATA3
TXINHIBIT	input	TCELL0:IMUX.G3.DATA3
TXKERR0	output	TCELL1:OUT.SEC9.TMIN
TXKERR1	output	TCELL2:OUT.SEC9.TMIN
TXKERR2	output	TCELL3:OUT.SEC9.TMIN
TXKERR3	output	TCELL4:OUT.SEC9.TMIN
TXPOLARITY	input	TCELL0:IMUX.G2.DATA3
TXRESET	input	TCELL1:IMUX.SR0
TXRUNDISP0	output	TCELL1:OUT.SEC10.TMIN
TXRUNDISP1	output	TCELL2:OUT.SEC10.TMIN
TXRUNDISP2	output	TCELL3:OUT.SEC10.TMIN
TXRUNDISP3	output	TCELL4:OUT.SEC10.TMIN
TXUSRCLK	input	TCELL1:IMUX.CLK0
TXUSRCLK2	input	TCELL1:IMUX.CLK1

Bel IPAD_RXP

virtex2 GIGABIT.B bel IPAD_RXP
Pin	Direction	Wires

Bel IPAD_RXN

virtex2 GIGABIT.B bel IPAD_RXN
Pin	Direction	Wires

Bel OPAD_TXP

virtex2 GIGABIT.B bel OPAD_TXP
Pin	Direction	Wires

Bel OPAD_TXN

virtex2 GIGABIT.B bel OPAD_TXN
Pin	Direction	Wires

Bel wires

virtex2 GIGABIT.B bel wires
Wire	Pins
TCELL0:IMUX.DCMCLK0	GT.RXUSRCLK
TCELL0:IMUX.DCMCLK1	GT.RXUSRCLK2
TCELL0:IMUX.DCMCLK2	GT.REFCLK
TCELL0:IMUX.DCMCLK3	GT.REFCLK2
TCELL0:IMUX.SR0	GT.RXRESET
TCELL0:IMUX.G0.DATA0	GT.CHBONDI0
TCELL0:IMUX.G0.DATA1	GT.ENCHANSYNC
TCELL0:IMUX.G0.DATA2	GT.POWERDOWN
TCELL0:IMUX.G0.DATA3	GT.LOOPBACK0
TCELL0:IMUX.G1.DATA0	GT.CHBONDI1
TCELL0:IMUX.G1.DATA1	GT.REFCLKSEL
TCELL0:IMUX.G1.DATA2	GT.RXPOLARITY
TCELL0:IMUX.G1.DATA3	GT.LOOPBACK1
TCELL0:IMUX.G2.DATA0	GT.CHBONDI2
TCELL0:IMUX.G2.DATA2	GT.CONFIGIN
TCELL0:IMUX.G2.DATA3	GT.TXPOLARITY
TCELL0:IMUX.G3.DATA0	GT.CHBONDI3
TCELL0:IMUX.G3.DATA2	GT.CONFIGENABLE
TCELL0:IMUX.G3.DATA3	GT.TXINHIBIT
TCELL0:OUT.FAN0.TMIN	GT.CHBONDO0
TCELL0:OUT.FAN1.TMIN	GT.CHBONDO1
TCELL0:OUT.FAN2.TMIN	GT.CHBONDO2
TCELL0:OUT.FAN3.TMIN	GT.CHBONDO3
TCELL0:OUT.FAN4.TMIN	GT.CHBONDDONE
TCELL0:OUT.FAN5.TMIN	GT.RXCOMMADET
TCELL0:OUT.FAN6.TMIN	GT.RXRECCLK
TCELL0:OUT.FAN7.TMIN	GT.TXBUFERR
TCELL0:OUT.SEC9.TMIN	GT.RXCLKCORCNT2
TCELL0:OUT.SEC10.TMIN	GT.RXCLKCORCNT1
TCELL0:OUT.SEC11.TMIN	GT.RXCLKCORCNT0
TCELL0:OUT.SEC12.TMIN	GT.CONFIGOUT
TCELL0:OUT.SEC13.TMIN	GT.RXREALIGN
TCELL0:OUT.SEC14.TMIN	GT.RXBUFSTATUS1
TCELL0:OUT.SEC15.TMIN	GT.RXBUFSTATUS0
TCELL1:IMUX.CLK0	GT.TXUSRCLK
TCELL1:IMUX.CLK1	GT.TXUSRCLK2
TCELL1:IMUX.SR0	GT.TXRESET
TCELL1:IMUX.G0.DATA0	GT.TXDATA0
TCELL1:IMUX.G0.DATA1	GT.TXDATA4
TCELL1:IMUX.G0.DATA2	GT.TXBYPASS8B10B0
TCELL1:IMUX.G1.DATA0	GT.TXDATA1
TCELL1:IMUX.G1.DATA1	GT.TXDATA5
TCELL1:IMUX.G1.DATA2	GT.TXCHARISK0
TCELL1:IMUX.G1.DATA4	GT.ENPCOMMAALIGN
TCELL1:IMUX.G1.DATA7	GT.ENMCOMMAALIGN
TCELL1:IMUX.G2.DATA0	GT.TXDATA2
TCELL1:IMUX.G2.DATA1	GT.TXDATA6
TCELL1:IMUX.G2.DATA2	GT.TXCHARDISPMODE0
TCELL1:IMUX.G3.DATA0	GT.TXDATA3
TCELL1:IMUX.G3.DATA1	GT.TXDATA7
TCELL1:IMUX.G3.DATA2	GT.TXCHARDISPVAL0
TCELL1:OUT.FAN0.TMIN	GT.RXDATA0
TCELL1:OUT.FAN1.TMIN	GT.RXDATA1
TCELL1:OUT.FAN2.TMIN	GT.RXDATA2
TCELL1:OUT.FAN3.TMIN	GT.RXDATA3
TCELL1:OUT.FAN4.TMIN	GT.RXDATA4
TCELL1:OUT.FAN5.TMIN	GT.RXDATA5
TCELL1:OUT.FAN6.TMIN	GT.RXDATA6
TCELL1:OUT.FAN7.TMIN	GT.RXDATA7
TCELL1:OUT.SEC8.TMIN	GT.RXLOSSOFSYNC0
TCELL1:OUT.SEC9.TMIN	GT.TXKERR0
TCELL1:OUT.SEC10.TMIN	GT.TXRUNDISP0
TCELL1:OUT.SEC11.TMIN	GT.RXCHARISCOMMA0
TCELL1:OUT.SEC12.TMIN	GT.RXCHARISK0
TCELL1:OUT.SEC13.TMIN	GT.RXNOTINTABLE0
TCELL1:OUT.SEC14.TMIN	GT.RXDISPERR0
TCELL1:OUT.SEC15.TMIN	GT.RXRUNDISP0
TCELL2:IMUX.G0.DATA0	GT.TXDATA8
TCELL2:IMUX.G0.DATA1	GT.TXDATA12
TCELL2:IMUX.G0.DATA2	GT.TXBYPASS8B10B1
TCELL2:IMUX.G1.DATA0	GT.TXDATA9
TCELL2:IMUX.G1.DATA1	GT.TXDATA13
TCELL2:IMUX.G1.DATA2	GT.TXCHARISK1
TCELL2:IMUX.G2.DATA0	GT.TXDATA10
TCELL2:IMUX.G2.DATA1	GT.TXDATA14
TCELL2:IMUX.G2.DATA2	GT.TXCHARDISPMODE1
TCELL2:IMUX.G3.DATA0	GT.TXDATA11
TCELL2:IMUX.G3.DATA1	GT.TXDATA15
TCELL2:IMUX.G3.DATA2	GT.TXCHARDISPVAL1
TCELL2:OUT.FAN0.TMIN	GT.RXDATA8
TCELL2:OUT.FAN1.TMIN	GT.RXDATA9
TCELL2:OUT.FAN2.TMIN	GT.RXDATA10
TCELL2:OUT.FAN3.TMIN	GT.RXDATA11
TCELL2:OUT.FAN4.TMIN	GT.RXDATA12
TCELL2:OUT.FAN5.TMIN	GT.RXDATA13
TCELL2:OUT.FAN6.TMIN	GT.RXDATA14
TCELL2:OUT.FAN7.TMIN	GT.RXDATA15
TCELL2:OUT.SEC8.TMIN	GT.RXLOSSOFSYNC1
TCELL2:OUT.SEC9.TMIN	GT.TXKERR1
TCELL2:OUT.SEC10.TMIN	GT.TXRUNDISP1
TCELL2:OUT.SEC11.TMIN	GT.RXCHARISCOMMA1
TCELL2:OUT.SEC12.TMIN	GT.RXCHARISK1
TCELL2:OUT.SEC13.TMIN	GT.RXNOTINTABLE1
TCELL2:OUT.SEC14.TMIN	GT.RXDISPERR1
TCELL2:OUT.SEC15.TMIN	GT.RXRUNDISP1
TCELL3:IMUX.G0.DATA0	GT.TXDATA16
TCELL3:IMUX.G0.DATA1	GT.TXDATA20
TCELL3:IMUX.G0.DATA2	GT.TXBYPASS8B10B2
TCELL3:IMUX.G1.DATA0	GT.TXDATA17
TCELL3:IMUX.G1.DATA1	GT.TXDATA21
TCELL3:IMUX.G1.DATA2	GT.TXCHARISK2
TCELL3:IMUX.G2.DATA0	GT.TXDATA18
TCELL3:IMUX.G2.DATA1	GT.TXDATA22
TCELL3:IMUX.G2.DATA2	GT.TXCHARDISPMODE2
TCELL3:IMUX.G3.DATA0	GT.TXDATA19
TCELL3:IMUX.G3.DATA1	GT.TXDATA23
TCELL3:IMUX.G3.DATA2	GT.TXCHARDISPVAL2
TCELL3:OUT.FAN0.TMIN	GT.RXDATA16
TCELL3:OUT.FAN1.TMIN	GT.RXDATA17
TCELL3:OUT.FAN2.TMIN	GT.RXDATA18
TCELL3:OUT.FAN3.TMIN	GT.RXDATA19
TCELL3:OUT.FAN4.TMIN	GT.RXDATA20
TCELL3:OUT.FAN5.TMIN	GT.RXDATA21
TCELL3:OUT.FAN6.TMIN	GT.RXDATA22
TCELL3:OUT.FAN7.TMIN	GT.RXDATA23
TCELL3:OUT.SEC8.TMIN	GT.RXCRCERR
TCELL3:OUT.SEC9.TMIN	GT.TXKERR2
TCELL3:OUT.SEC10.TMIN	GT.TXRUNDISP2
TCELL3:OUT.SEC11.TMIN	GT.RXCHARISCOMMA2
TCELL3:OUT.SEC12.TMIN	GT.RXCHARISK2
TCELL3:OUT.SEC13.TMIN	GT.RXNOTINTABLE2
TCELL3:OUT.SEC14.TMIN	GT.RXDISPERR2
TCELL3:OUT.SEC15.TMIN	GT.RXRUNDISP2
TCELL4:IMUX.G0.DATA0	GT.TXDATA24
TCELL4:IMUX.G0.DATA1	GT.TXDATA28
TCELL4:IMUX.G0.DATA2	GT.TXBYPASS8B10B3
TCELL4:IMUX.G1.DATA0	GT.TXDATA25
TCELL4:IMUX.G1.DATA1	GT.TXDATA29
TCELL4:IMUX.G1.DATA2	GT.TXCHARISK3
TCELL4:IMUX.G2.DATA0	GT.TXDATA26
TCELL4:IMUX.G2.DATA1	GT.TXDATA30
TCELL4:IMUX.G2.DATA2	GT.TXCHARDISPMODE3
TCELL4:IMUX.G3.DATA0	GT.TXDATA27
TCELL4:IMUX.G3.DATA1	GT.TXDATA31
TCELL4:IMUX.G3.DATA2	GT.TXCHARDISPVAL3
TCELL4:IMUX.G3.DATA3	GT.TXFORCECRCERR
TCELL4:OUT.FAN0.TMIN	GT.RXDATA24
TCELL4:OUT.FAN1.TMIN	GT.RXDATA25
TCELL4:OUT.FAN2.TMIN	GT.RXDATA26
TCELL4:OUT.FAN3.TMIN	GT.RXDATA27
TCELL4:OUT.FAN4.TMIN	GT.RXDATA28
TCELL4:OUT.FAN5.TMIN	GT.RXDATA29
TCELL4:OUT.FAN6.TMIN	GT.RXDATA30
TCELL4:OUT.FAN7.TMIN	GT.RXDATA31
TCELL4:OUT.SEC8.TMIN	GT.RXCHECKINGCRC
TCELL4:OUT.SEC9.TMIN	GT.TXKERR3
TCELL4:OUT.SEC10.TMIN	GT.TXRUNDISP3
TCELL4:OUT.SEC11.TMIN	GT.RXCHARISCOMMA3
TCELL4:OUT.SEC12.TMIN	GT.RXCHARISK3
TCELL4:OUT.SEC13.TMIN	GT.RXNOTINTABLE3
TCELL4:OUT.SEC14.TMIN	GT.RXDISPERR3
TCELL4:OUT.SEC15.TMIN	GT.RXRUNDISP3

Bitstream

virtex2 GIGABIT.B bittile 0
Bit	Frame
Bit	0	1	2	3
79	-	-	-	GT:TERMINATION_IMP[0]
78	-	-	-	GT:TX_DIFF_CTRL[1]
77	-	-	-	GT:TX_DIFF_CTRL[0]
76	-	-	-	GT:TX_PREEMPHASIS[0]
75	-	-	-	GT:TX_PREEMPHASIS[1]
74	-	-	-	GT:ENABLE
73	-	-	-	GT:TX_DIFF_CTRL[2]
72	-	-	-	-
71	-	-	-	-
70	-	-	-	-
69	-	-	-	-
68	-	-	-	-
67	-	-	-	-
66	-	-	-	-
65	-	-	-	-
64	-	-	-	-
63	-	-	-	-
62	-	-	-	-
61	-	-	-	-
60	-	-	-	-
59	-	-	-	-
58	-	-	-	-
57	-	-	-	-
56	-	-	-	-
55	-	-	-	-
54	-	-	-	-
53	-	-	-	-
52	-	-	-	-
51	-	-	-	-
50	-	-	-	-
49	-	-	-	-
48	-	-	-	-
47	-	-	-	-
46	-	-	-	-
45	-	-	-	GT:TX_CRC_FORCE_VALUE[7]
44	-	-	-	GT:TX_CRC_FORCE_VALUE[6]
43	-	-	-	GT:TX_CRC_FORCE_VALUE[5]
42	-	-	-	GT:TX_CRC_FORCE_VALUE[4]
41	-	-	-	GT:TX_CRC_FORCE_VALUE[3]
40	-	-	-	GT:TX_CRC_FORCE_VALUE[2]
39	-	-	-	GT:TX_CRC_FORCE_VALUE[1]
38	-	-	-	GT:TX_CRC_FORCE_VALUE[0]
37	-	-	-	GT:TX_CRC_USE
36	-	-	-	GT:TX_BUFFER_USE
35	-	-	-	GT:SERDES_10B
34	-	-	-	-
33	-	-	-	-
32	-	-	-	-
31	-	-	-	-
30	-	-	-	-
29	-	-	-	-
28	-	-	-	-
27	-	-	-	-
26	-	-	-	-
25	-	-	-	-
24	-	-	-	-
23	-	-	-	-
22	-	-	-	-
21	-	-	-	-
20	-	-	-	GT:CRC_END_OF_PKT[7]
19	-	-	-	GT:CRC_END_OF_PKT[6]
18	-	-	-	GT:CRC_END_OF_PKT[5]
17	-	-	-	GT:CRC_END_OF_PKT[4]
16	-	-	-	GT:CRC_END_OF_PKT[3]
15	-	-	-	GT:CRC_END_OF_PKT[2]
14	-	-	-	GT:CRC_END_OF_PKT[1]
13	-	-	-	GT:CRC_END_OF_PKT[0]
12	-	-	-	GT:CRC_START_OF_PKT[7]
11	-	-	-	GT:CRC_START_OF_PKT[6]
10	-	-	-	GT:CRC_START_OF_PKT[5]
9	-	-	-	GT:CRC_START_OF_PKT[4]
8	-	-	-	GT:CRC_START_OF_PKT[3]
7	-	-	-	GT:CRC_START_OF_PKT[2]
6	-	-	-	GT:CRC_START_OF_PKT[1]
5	-	-	-	GT:CRC_START_OF_PKT[0]
4	-	-	-	GT:CRC_FORMAT[1]
3	-	-	-	GT:CRC_FORMAT[0]
2	-	-	-	GT:REF_CLK_V_SEL
1	-	-	-	GT:TX_DATA_WIDTH[1]
0	-	-	-	GT:TX_DATA_WIDTH[0]

virtex2 GIGABIT.B bittile 1
Bit	Frame
Bit	0	1	2	3
79	-	-	-	GT:CLK_COR_SEQ_1_1[10]
78	-	-	-	GT:CLK_COR_SEQ_1_1[9]
77	-	-	-	GT:CLK_COR_SEQ_1_1[8]
76	-	-	-	GT:CLK_COR_SEQ_1_1[7]
75	-	-	-	GT:CLK_COR_SEQ_1_1[6]
74	-	-	-	GT:CLK_COR_SEQ_1_1[5]
73	-	-	-	GT:CLK_COR_SEQ_1_1[4]
72	-	-	-	GT:CLK_COR_SEQ_1_1[3]
71	-	-	-	GT:CLK_COR_SEQ_1_1[2]
70	-	-	-	GT:CLK_COR_SEQ_1_1[1]
69	-	-	-	GT:CLK_COR_SEQ_1_1[0]
68	-	-	-	GT:CLK_COR_SEQ_1_2[10]
67	-	-	-	GT:CLK_COR_SEQ_1_2[9]
66	-	-	-	GT:CLK_COR_SEQ_1_2[8]
65	-	-	-	GT:CLK_COR_SEQ_1_2[7]
64	-	-	-	GT:CLK_COR_SEQ_1_2[6]
63	-	-	-	GT:CLK_COR_SEQ_1_2[5]
62	-	-	-	GT:CLK_COR_SEQ_1_2[4]
61	-	-	-	GT:CLK_COR_SEQ_1_2[3]
60	-	-	-	GT:CLK_COR_SEQ_1_2[2]
59	-	-	-	GT:CLK_COR_SEQ_1_2[1]
58	-	-	-	GT:CLK_COR_SEQ_1_2[0]
57	-	-	-	GT:CLK_COR_SEQ_1_3[10]
56	-	-	-	GT:CLK_COR_SEQ_1_3[9]
55	-	-	-	GT:CLK_COR_SEQ_1_3[8]
54	-	-	-	GT:CLK_COR_SEQ_1_3[7]
53	-	-	-	GT:CLK_COR_SEQ_1_3[6]
52	-	-	-	GT:CLK_COR_SEQ_1_3[5]
51	-	-	-	GT:CLK_COR_SEQ_1_3[4]
50	-	-	-	GT:CLK_COR_SEQ_1_3[3]
49	-	-	-	GT:CLK_COR_SEQ_1_3[2]
48	-	-	-	GT:CLK_COR_SEQ_1_3[1]
47	-	-	-	GT:CLK_COR_SEQ_1_3[0]
46	-	-	-	GT:CLK_COR_SEQ_1_4[10]
45	-	-	-	GT:CLK_COR_SEQ_1_4[9]
44	-	-	-	GT:CLK_COR_SEQ_1_4[8]
43	-	-	-	GT:CLK_COR_SEQ_1_4[7]
42	-	-	-	GT:CLK_COR_SEQ_1_4[6]
41	-	-	-	GT:CLK_COR_SEQ_1_4[5]
40	-	-	-	GT:CLK_COR_SEQ_1_4[4]
39	-	-	-	GT:CLK_COR_SEQ_1_4[3]
38	-	-	-	GT:CLK_COR_SEQ_1_4[2]
37	-	-	-	GT:CLK_COR_SEQ_1_4[1]
36	-	-	-	GT:CLK_COR_SEQ_1_4[0]
35	-	-	-	-
34	-	-	-	GT:PCOMMA_DETECT
33	-	-	-	-
32	-	-	-	GT:PCOMMA_10B_VALUE[0]
31	-	-	-	GT:PCOMMA_10B_VALUE[1]
30	-	-	-	GT:PCOMMA_10B_VALUE[2]
29	-	-	-	GT:PCOMMA_10B_VALUE[3]
28	-	-	-	GT:PCOMMA_10B_VALUE[4]
27	-	-	-	GT:PCOMMA_10B_VALUE[5]
26	-	-	-	GT:PCOMMA_10B_VALUE[6]
25	-	-	-	GT:PCOMMA_10B_VALUE[7]
24	-	-	-	GT:PCOMMA_10B_VALUE[8]
23	-	-	-	GT:PCOMMA_10B_VALUE[9]
22	-	-	-	GT:MCOMMA_DETECT
21	-	-	-	-
20	-	-	-	GT:MCOMMA_10B_VALUE[0]
19	-	-	-	GT:MCOMMA_10B_VALUE[1]
18	-	-	-	GT:MCOMMA_10B_VALUE[2]
17	-	-	-	GT:MCOMMA_10B_VALUE[3]
16	-	-	-	GT:MCOMMA_10B_VALUE[4]
15	-	-	-	GT:MCOMMA_10B_VALUE[5]
14	-	-	-	GT:MCOMMA_10B_VALUE[6]
13	-	-	-	GT:MCOMMA_10B_VALUE[7]
12	-	-	-	GT:MCOMMA_10B_VALUE[8]
11	-	-	-	GT:MCOMMA_10B_VALUE[9]
10	-	-	-	GT:COMMA_10B_MASK[0]
9	-	-	-	GT:COMMA_10B_MASK[1]
8	-	-	-	GT:COMMA_10B_MASK[2]
7	-	-	-	GT:COMMA_10B_MASK[3]
6	-	-	-	GT:COMMA_10B_MASK[4]
5	-	-	-	GT:COMMA_10B_MASK[5]
4	-	-	-	GT:COMMA_10B_MASK[6]
3	-	-	-	GT:COMMA_10B_MASK[7]
2	-	-	-	GT:COMMA_10B_MASK[8]
1	-	-	-	GT:COMMA_10B_MASK[9]
0	-	-	-	GT:ALIGN_COMMA_MSB

virtex2 GIGABIT.B bittile 2
Bit	Frame
Bit	0	1	2	3
79	-	-	-	GT:CLK_COR_SEQ_2_1[10]
78	-	-	-	GT:CLK_COR_SEQ_2_1[9]
77	-	-	-	GT:CLK_COR_SEQ_2_1[8]
76	-	-	-	GT:CLK_COR_SEQ_2_1[7]
75	-	-	-	GT:CLK_COR_SEQ_2_1[6]
74	-	-	-	GT:CLK_COR_SEQ_2_1[5]
73	-	-	-	GT:CLK_COR_SEQ_2_1[4]
72	-	-	-	GT:CLK_COR_SEQ_2_1[3]
71	-	-	-	GT:CLK_COR_SEQ_2_1[2]
70	-	-	-	GT:CLK_COR_SEQ_2_1[1]
69	-	-	-	GT:CLK_COR_SEQ_2_1[0]
68	-	-	-	GT:CLK_COR_SEQ_2_2[10]
67	-	-	-	GT:CLK_COR_SEQ_2_2[9]
66	-	-	-	GT:CLK_COR_SEQ_2_2[8]
65	-	-	-	GT:CLK_COR_SEQ_2_2[7]
64	-	-	-	GT:CLK_COR_SEQ_2_2[6]
63	-	-	-	GT:CLK_COR_SEQ_2_2[5]
62	-	-	-	GT:CLK_COR_SEQ_2_2[4]
61	-	-	-	GT:CLK_COR_SEQ_2_2[3]
60	-	-	-	GT:CLK_COR_SEQ_2_2[2]
59	-	-	-	GT:CLK_COR_SEQ_2_2[1]
58	-	-	-	GT:CLK_COR_SEQ_2_2[0]
57	-	-	-	GT:CLK_COR_SEQ_2_3[10]
56	-	-	-	GT:CLK_COR_SEQ_2_3[9]
55	-	-	-	GT:CLK_COR_SEQ_2_3[8]
54	-	-	-	GT:CLK_COR_SEQ_2_3[7]
53	-	-	-	GT:CLK_COR_SEQ_2_3[6]
52	-	-	-	GT:CLK_COR_SEQ_2_3[5]
51	-	-	-	GT:CLK_COR_SEQ_2_3[4]
50	-	-	-	GT:CLK_COR_SEQ_2_3[3]
49	-	-	-	GT:CLK_COR_SEQ_2_3[2]
48	-	-	-	GT:CLK_COR_SEQ_2_3[1]
47	-	-	-	GT:CLK_COR_SEQ_2_3[0]
46	-	-	-	GT:CLK_COR_SEQ_2_4[10]
45	-	-	-	GT:CLK_COR_SEQ_2_4[9]
44	-	-	-	GT:CLK_COR_SEQ_2_4[8]
43	-	-	-	GT:CLK_COR_SEQ_2_4[7]
42	-	-	-	GT:CLK_COR_SEQ_2_4[6]
41	-	-	-	GT:CLK_COR_SEQ_2_4[5]
40	-	-	-	GT:CLK_COR_SEQ_2_4[4]
39	-	-	-	GT:CLK_COR_SEQ_2_4[3]
38	-	-	-	GT:CLK_COR_SEQ_2_4[2]
37	-	-	-	GT:CLK_COR_SEQ_2_4[1]
36	-	-	-	GT:CLK_COR_SEQ_2_4[0]
35	-	-	-	GT:CLK_COR_SEQ_2_USE
34	-	-	-	GT:CLK_COR_SEQ_LEN[1]
33	-	-	-	GT:CLK_COR_SEQ_LEN[0]
32	-	-	-	GT:DEC_MCOMMA_DETECT
31	-	-	-	GT:DEC_PCOMMA_DETECT
30	-	-	-	GT:DEC_VALID_COMMA_ONLY
29	-	-	-	GT:RX_BUFFER_LIMIT[3]
28	-	-	-	GT:RX_BUFFER_LIMIT[2]
27	-	-	-	GT:RX_BUFFER_LIMIT[1]
26	-	-	-	GT:RX_BUFFER_LIMIT[0]
25	-	-	-	GT:RX_BUFFER_USE
24	-	-	-	GT:RX_DECODE_USE
23	-	-	-	GT:CHAN_BOND_ONE_SHOT
22	-	-	-	-
21	-	-	-	-
20	-	-	-	-
19	-	-	-	-
18	-	-	-	-
17	-	-	-	GT:CLK_COR_REPEAT_WAIT[4]
16	-	-	-	GT:CLK_COR_REPEAT_WAIT[3]
15	-	-	-	GT:CLK_COR_REPEAT_WAIT[2]
14	-	-	-	GT:CLK_COR_REPEAT_WAIT[1]
13	-	-	-	GT:CLK_COR_REPEAT_WAIT[0]
12	-	-	-	GT:CLK_COR_KEEP_IDLE
11	-	-	-	GT:CLK_COR_INSERT_IDLE_FLAG
10	-	-	-	GT:CLK_CORRECT_USE
9	-	-	-	GT:CHAN_BOND_OFFSET[3]
8	-	-	-	GT:CHAN_BOND_OFFSET[2]
7	-	-	-	GT:CHAN_BOND_OFFSET[1]
6	-	-	-	GT:CHAN_BOND_OFFSET[0]
5	-	-	-	GT:CHAN_BOND_MODE[1]
4	-	-	-	GT:CHAN_BOND_MODE[0]
3	-	-	-	-
2	-	-	-	-
1	-	-	-	GT:RX_DATA_WIDTH[1]
0	-	-	-	GT:RX_DATA_WIDTH[0]

virtex2 GIGABIT.B bittile 3
Bit	Frame
Bit	0	1	2	3
79	-	-	-	GT:CHAN_BOND_SEQ_1_1[10]
78	-	-	-	GT:CHAN_BOND_SEQ_1_1[9]
77	-	-	-	GT:CHAN_BOND_SEQ_1_1[8]
76	-	-	-	GT:CHAN_BOND_SEQ_1_1[7]
75	-	-	-	GT:CHAN_BOND_SEQ_1_1[6]
74	-	-	-	GT:CHAN_BOND_SEQ_1_1[5]
73	-	-	-	GT:CHAN_BOND_SEQ_1_1[4]
72	-	-	-	GT:CHAN_BOND_SEQ_1_1[3]
71	-	-	-	GT:CHAN_BOND_SEQ_1_1[2]
70	-	-	-	GT:CHAN_BOND_SEQ_1_1[1]
69	-	-	-	GT:CHAN_BOND_SEQ_1_1[0]
68	-	-	-	GT:CHAN_BOND_SEQ_1_2[10]
67	-	-	-	GT:CHAN_BOND_SEQ_1_2[9]
66	-	-	-	GT:CHAN_BOND_SEQ_1_2[8]
65	-	-	-	GT:CHAN_BOND_SEQ_1_2[7]
64	-	-	-	GT:CHAN_BOND_SEQ_1_2[6]
63	-	-	-	GT:CHAN_BOND_SEQ_1_2[5]
62	-	-	-	GT:CHAN_BOND_SEQ_1_2[4]
61	-	-	-	GT:CHAN_BOND_SEQ_1_2[3]
60	-	-	-	GT:CHAN_BOND_SEQ_1_2[2]
59	-	-	-	GT:CHAN_BOND_SEQ_1_2[1]
58	-	-	-	GT:CHAN_BOND_SEQ_1_2[0]
57	-	-	-	GT:CHAN_BOND_SEQ_1_3[10]
56	-	-	-	GT:CHAN_BOND_SEQ_1_3[9]
55	-	-	-	GT:CHAN_BOND_SEQ_1_3[8]
54	-	-	-	GT:CHAN_BOND_SEQ_1_3[7]
53	-	-	-	GT:CHAN_BOND_SEQ_1_3[6]
52	-	-	-	GT:CHAN_BOND_SEQ_1_3[5]
51	-	-	-	GT:CHAN_BOND_SEQ_1_3[4]
50	-	-	-	GT:CHAN_BOND_SEQ_1_3[3]
49	-	-	-	GT:CHAN_BOND_SEQ_1_3[2]
48	-	-	-	GT:CHAN_BOND_SEQ_1_3[1]
47	-	-	-	GT:CHAN_BOND_SEQ_1_3[0]
46	-	-	-	GT:CHAN_BOND_SEQ_1_4[10]
45	-	-	-	GT:CHAN_BOND_SEQ_1_4[9]
44	-	-	-	GT:CHAN_BOND_SEQ_1_4[8]
43	-	-	-	GT:CHAN_BOND_SEQ_1_4[7]
42	-	-	-	GT:CHAN_BOND_SEQ_1_4[6]
41	-	-	-	GT:CHAN_BOND_SEQ_1_4[5]
40	-	-	-	GT:CHAN_BOND_SEQ_1_4[4]
39	-	-	-	GT:CHAN_BOND_SEQ_1_4[3]
38	-	-	-	GT:CHAN_BOND_SEQ_1_4[2]
37	-	-	-	GT:CHAN_BOND_SEQ_1_4[1]
36	-	-	-	GT:CHAN_BOND_SEQ_1_4[0]
35	-	-	-	GT:RX_CRC_USE
34	-	-	-	GT:TEST_MODE_6
33	-	-	-	GT:TEST_MODE_5
32	-	-	-	GT:TEST_MODE_4
31	-	-	-	GT:TEST_MODE_3
30	-	-	-	GT:TEST_MODE_2
29	-	-	-	GT:TEST_MODE_1
28	-	-	-	-
27	-	-	-	-
26	-	-	-	-
25	-	-	-	-
24	-	-	-	-
23	-	-	-	-
22	-	-	-	-
21	-	-	-	-
20	-	-	-	-
19	-	-	-	-
18	-	-	-	-
17	-	-	-	-
16	-	-	-	-
15	-	-	-	-
14	-	-	-	-
13	-	-	-	-
12	-	-	-	-
11	-	-	-	-
10	-	-	-	-
9	-	-	-	-
8	-	-	-	-
7	-	-	-	-
6	-	-	-	-
5	-	-	-	-
4	-	-	-	-
3	-	-	-	-
2	-	-	-	-
1	-	-	-	-
0	-	-	-	-

virtex2 GIGABIT.B bittile 4
Bit	Frame
Bit	0	1	2	3
79	-	-	-	GT:CHAN_BOND_SEQ_2_1[10]
78	-	-	-	GT:CHAN_BOND_SEQ_2_1[9]
77	-	-	-	GT:CHAN_BOND_SEQ_2_1[8]
76	-	-	-	GT:CHAN_BOND_SEQ_2_1[7]
75	-	-	-	GT:CHAN_BOND_SEQ_2_1[6]
74	-	-	-	GT:CHAN_BOND_SEQ_2_1[5]
73	-	-	-	GT:CHAN_BOND_SEQ_2_1[4]
72	-	-	-	GT:CHAN_BOND_SEQ_2_1[3]
71	-	-	-	GT:CHAN_BOND_SEQ_2_1[2]
70	-	-	-	GT:CHAN_BOND_SEQ_2_1[1]
69	-	-	-	GT:CHAN_BOND_SEQ_2_1[0]
68	-	-	-	GT:CHAN_BOND_SEQ_2_2[10]
67	-	-	-	GT:CHAN_BOND_SEQ_2_2[9]
66	-	-	-	GT:CHAN_BOND_SEQ_2_2[8]
65	-	-	-	GT:CHAN_BOND_SEQ_2_2[7]
64	-	-	-	GT:CHAN_BOND_SEQ_2_2[6]
63	-	-	-	GT:CHAN_BOND_SEQ_2_2[5]
62	-	-	-	GT:CHAN_BOND_SEQ_2_2[4]
61	-	-	-	GT:CHAN_BOND_SEQ_2_2[3]
60	-	-	-	GT:CHAN_BOND_SEQ_2_2[2]
59	-	-	-	GT:CHAN_BOND_SEQ_2_2[1]
58	-	-	-	GT:CHAN_BOND_SEQ_2_2[0]
57	-	-	-	GT:CHAN_BOND_SEQ_2_3[10]
56	-	-	-	GT:CHAN_BOND_SEQ_2_3[9]
55	-	-	-	GT:CHAN_BOND_SEQ_2_3[8]
54	-	-	-	GT:CHAN_BOND_SEQ_2_3[7]
53	-	-	-	GT:CHAN_BOND_SEQ_2_3[6]
52	-	-	-	GT:CHAN_BOND_SEQ_2_3[5]
51	-	-	-	GT:CHAN_BOND_SEQ_2_3[4]
50	-	-	-	GT:CHAN_BOND_SEQ_2_3[3]
49	-	-	-	GT:CHAN_BOND_SEQ_2_3[2]
48	-	-	-	GT:CHAN_BOND_SEQ_2_3[1]
47	-	-	-	GT:CHAN_BOND_SEQ_2_3[0]
46	-	-	-	GT:CHAN_BOND_SEQ_2_4[10]
45	-	-	-	GT:CHAN_BOND_SEQ_2_4[9]
44	-	-	-	GT:CHAN_BOND_SEQ_2_4[8]
43	-	-	-	GT:CHAN_BOND_SEQ_2_4[7]
42	-	-	-	GT:CHAN_BOND_SEQ_2_4[6]
41	-	-	-	GT:CHAN_BOND_SEQ_2_4[5]
40	-	-	-	GT:CHAN_BOND_SEQ_2_4[4]
39	-	-	-	GT:CHAN_BOND_SEQ_2_4[3]
38	-	-	-	GT:CHAN_BOND_SEQ_2_4[2]
37	-	-	-	GT:CHAN_BOND_SEQ_2_4[1]
36	-	-	-	GT:CHAN_BOND_SEQ_2_4[0]
35	-	-	-	GT:CHAN_BOND_SEQ_2_USE
34	-	-	-	GT:CHAN_BOND_SEQ_LEN[1]
33	-	-	-	GT:CHAN_BOND_SEQ_LEN[0]
32	-	-	-	GT:CHAN_BOND_WAIT[3]
31	-	-	-	GT:CHAN_BOND_WAIT[2]
30	-	-	-	GT:CHAN_BOND_WAIT[1]
29	-	-	-	GT:CHAN_BOND_WAIT[0]
28	-	-	-	GT:CHAN_BOND_LIMIT[4]
27	-	-	-	GT:CHAN_BOND_LIMIT[3]
26	-	-	-	GT:CHAN_BOND_LIMIT[2]
25	-	-	-	GT:CHAN_BOND_LIMIT[1]
24	-	-	-	GT:CHAN_BOND_LIMIT[0]
23	-	-	-	GT:RX_LOSS_OF_SYNC_FSM
22	-	-	-	GT:RX_LOS_INVALID_INCR[2]
21	-	-	-	GT:RX_LOS_INVALID_INCR[1]
20	-	-	-	GT:RX_LOS_INVALID_INCR[0]
19	-	-	-	GT:RX_LOS_THRESHOLD[2]
18	-	-	-	GT:RX_LOS_THRESHOLD[1]
17	-	-	-	GT:RX_LOS_THRESHOLD[0]
16	-	-	-	-
15	-	-	-	-
14	-	-	-	-
13	-	-	-	-
12	-	-	-	-
11	-	-	-	-
10	-	-	-	-
9	-	-	-	-
8	-	-	-	-
7	-	-	-	-
6	-	-	-	-
5	-	-	-	-
4	-	-	-	-
3	-	-	-	-
2	-	-	-	-
1	-	-	-	-
0	-	-	-	-

GT:ALIGN_COMMA_MSB	1.3.0
GT:CHAN_BOND_ONE_SHOT	2.3.23
GT:CHAN_BOND_SEQ_2_USE	4.3.35
GT:CLK_CORRECT_USE	2.3.10
GT:CLK_COR_INSERT_IDLE_FLAG	2.3.11
GT:CLK_COR_KEEP_IDLE	2.3.12
GT:CLK_COR_SEQ_2_USE	2.3.35
GT:DEC_MCOMMA_DETECT	2.3.32
GT:DEC_PCOMMA_DETECT	2.3.31
GT:DEC_VALID_COMMA_ONLY	2.3.30
GT:ENABLE	0.3.74
GT:MCOMMA_DETECT	1.3.22
GT:PCOMMA_DETECT	1.3.34
GT:REF_CLK_V_SEL	0.3.2
GT:RX_BUFFER_USE	2.3.25
GT:RX_CRC_USE	3.3.35
GT:RX_DECODE_USE	2.3.24
GT:RX_LOSS_OF_SYNC_FSM	4.3.23
GT:SERDES_10B	0.3.35
GT:TEST_MODE_1	3.3.29
GT:TEST_MODE_2	3.3.30
GT:TEST_MODE_3	3.3.31
GT:TEST_MODE_4	3.3.32
GT:TEST_MODE_5	3.3.33
GT:TEST_MODE_6	3.3.34
GT:TX_BUFFER_USE	0.3.36
GT:TX_CRC_USE	0.3.37
non-inverted	[0]

GT:CHAN_BOND_LIMIT	4.3.28	4.3.27	4.3.26	4.3.25	4.3.24
GT:CLK_COR_REPEAT_WAIT	2.3.17	2.3.16	2.3.15	2.3.14	2.3.13
non-inverted	[4]	[3]	[2]	[1]	[0]

GT:CHAN_BOND_MODE	2.3.5	2.3.4
NONE	0	0
MASTER	0	1
SLAVE_1_HOP	1	0
SLAVE_2_HOPS	1	1

GT:CHAN_BOND_OFFSET	2.3.9	2.3.8	2.3.7	2.3.6
GT:CHAN_BOND_WAIT	4.3.32	4.3.31	4.3.30	4.3.29
GT:RX_BUFFER_LIMIT	2.3.29	2.3.28	2.3.27	2.3.26
non-inverted	[3]	[2]	[1]	[0]

GT:CHAN_BOND_SEQ_1_1	3.3.79	3.3.78	3.3.77	3.3.76	3.3.75	3.3.74	3.3.73	3.3.72	3.3.71	3.3.70	3.3.69
GT:CHAN_BOND_SEQ_1_2	3.3.68	3.3.67	3.3.66	3.3.65	3.3.64	3.3.63	3.3.62	3.3.61	3.3.60	3.3.59	3.3.58
GT:CHAN_BOND_SEQ_1_3	3.3.57	3.3.56	3.3.55	3.3.54	3.3.53	3.3.52	3.3.51	3.3.50	3.3.49	3.3.48	3.3.47
GT:CHAN_BOND_SEQ_1_4	3.3.46	3.3.45	3.3.44	3.3.43	3.3.42	3.3.41	3.3.40	3.3.39	3.3.38	3.3.37	3.3.36
GT:CHAN_BOND_SEQ_2_1	4.3.79	4.3.78	4.3.77	4.3.76	4.3.75	4.3.74	4.3.73	4.3.72	4.3.71	4.3.70	4.3.69
GT:CHAN_BOND_SEQ_2_2	4.3.68	4.3.67	4.3.66	4.3.65	4.3.64	4.3.63	4.3.62	4.3.61	4.3.60	4.3.59	4.3.58
GT:CHAN_BOND_SEQ_2_3	4.3.57	4.3.56	4.3.55	4.3.54	4.3.53	4.3.52	4.3.51	4.3.50	4.3.49	4.3.48	4.3.47
GT:CHAN_BOND_SEQ_2_4	4.3.46	4.3.45	4.3.44	4.3.43	4.3.42	4.3.41	4.3.40	4.3.39	4.3.38	4.3.37	4.3.36
GT:CLK_COR_SEQ_1_1	1.3.79	1.3.78	1.3.77	1.3.76	1.3.75	1.3.74	1.3.73	1.3.72	1.3.71	1.3.70	1.3.69
GT:CLK_COR_SEQ_1_2	1.3.68	1.3.67	1.3.66	1.3.65	1.3.64	1.3.63	1.3.62	1.3.61	1.3.60	1.3.59	1.3.58
GT:CLK_COR_SEQ_1_3	1.3.57	1.3.56	1.3.55	1.3.54	1.3.53	1.3.52	1.3.51	1.3.50	1.3.49	1.3.48	1.3.47
GT:CLK_COR_SEQ_1_4	1.3.46	1.3.45	1.3.44	1.3.43	1.3.42	1.3.41	1.3.40	1.3.39	1.3.38	1.3.37	1.3.36
GT:CLK_COR_SEQ_2_1	2.3.79	2.3.78	2.3.77	2.3.76	2.3.75	2.3.74	2.3.73	2.3.72	2.3.71	2.3.70	2.3.69
GT:CLK_COR_SEQ_2_2	2.3.68	2.3.67	2.3.66	2.3.65	2.3.64	2.3.63	2.3.62	2.3.61	2.3.60	2.3.59	2.3.58
GT:CLK_COR_SEQ_2_3	2.3.57	2.3.56	2.3.55	2.3.54	2.3.53	2.3.52	2.3.51	2.3.50	2.3.49	2.3.48	2.3.47
GT:CLK_COR_SEQ_2_4	2.3.46	2.3.45	2.3.44	2.3.43	2.3.42	2.3.41	2.3.40	2.3.39	2.3.38	2.3.37	2.3.36
non-inverted	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT:CHAN_BOND_SEQ_LEN	4.3.34	4.3.33
GT:CLK_COR_SEQ_LEN	2.3.34	2.3.33
4	0	0
1	0	1
2	1	0
3	1	1

GT:COMMA_10B_MASK	1.3.1	1.3.2	1.3.3	1.3.4	1.3.5	1.3.6	1.3.7	1.3.8	1.3.9	1.3.10
GT:MCOMMA_10B_VALUE	1.3.11	1.3.12	1.3.13	1.3.14	1.3.15	1.3.16	1.3.17	1.3.18	1.3.19	1.3.20
GT:PCOMMA_10B_VALUE	1.3.23	1.3.24	1.3.25	1.3.26	1.3.27	1.3.28	1.3.29	1.3.30	1.3.31	1.3.32
non-inverted	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT:CRC_END_OF_PKT	0.3.20	0.3.19	0.3.18	0.3.17	0.3.16	0.3.15	0.3.14	0.3.13
GT:CRC_START_OF_PKT	0.3.12	0.3.11	0.3.10	0.3.9	0.3.8	0.3.7	0.3.6	0.3.5
K28_0	0	0	0	1	1	1	0	0
K28_1	0	0	1	1	1	1	0	0
K28_2	0	1	0	1	1	1	0	0
K28_3	0	1	1	1	1	1	0	0
K28_4	1	0	0	1	1	1	0	0
K28_5	1	0	1	1	1	1	0	0
K28_6	1	1	0	1	1	1	0	0
K23_7	1	1	1	1	0	1	1	1
K27_7	1	1	1	1	1	0	1	1
K28_7	1	1	1	1	1	1	0	0
K29_7	1	1	1	1	1	1	0	1
K30_7	1	1	1	1	1	1	1	0

GT:CRC_FORMAT	0.3.4	0.3.3
USER_MODE	0	0
ETHERNET	0	1
INFINIBAND	1	0
FIBRE_CHAN	1	1

GT:RX_DATA_WIDTH	2.3.1	2.3.0
GT:TX_DATA_WIDTH	0.3.1	0.3.0
4	0	0
1	0	1
2	1	0

GT:RX_LOS_INVALID_INCR	4.3.22	4.3.21	4.3.20
1	0	0	0
2	0	0	1
4	0	1	0
8	0	1	1
16	1	0	0
32	1	0	1
64	1	1	0
128	1	1	1

GT:RX_LOS_THRESHOLD	4.3.19	4.3.18	4.3.17
4	0	0	0
8	0	0	1
16	0	1	0
32	0	1	1
64	1	0	0
128	1	0	1
256	1	1	0
512	1	1	1

GT:TERMINATION_IMP	0.3.79
50	0
75	1

GT:TX_CRC_FORCE_VALUE	0.3.45	0.3.44	0.3.43	0.3.42	0.3.41	0.3.40	0.3.39	0.3.38
non-inverted	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT:TX_DIFF_CTRL	0.3.73	0.3.78	0.3.77
500	0	0	0
400	0	0	1
600	0	1	0
700	0	1	1
800	1	0	1

GT:TX_PREEMPHASIS	0.3.75	0.3.76
non-inverted	[1]	[0]

Tile GIGABIT.T

Cells: 5

Bel GT

virtex2 GIGABIT.T bel GT
Pin	Direction	Wires
CHBONDDONE	output	TCELL0:OUT.FAN4.TMIN
CHBONDI0	input	TCELL0:IMUX.G0.DATA0
CHBONDI1	input	TCELL0:IMUX.G1.DATA0
CHBONDI2	input	TCELL0:IMUX.G2.DATA0
CHBONDI3	input	TCELL0:IMUX.G3.DATA0
CHBONDO0	output	TCELL0:OUT.FAN0.TMIN
CHBONDO1	output	TCELL0:OUT.FAN1.TMIN
CHBONDO2	output	TCELL0:OUT.FAN2.TMIN
CHBONDO3	output	TCELL0:OUT.FAN3.TMIN
CONFIGENABLE	input	TCELL0:IMUX.G3.DATA2
CONFIGIN	input	TCELL0:IMUX.G2.DATA2
CONFIGOUT	output	TCELL0:OUT.SEC12.TMIN
ENCHANSYNC	input	TCELL0:IMUX.G0.DATA1
ENMCOMMAALIGN	input	TCELL1:IMUX.G1.DATA7
ENPCOMMAALIGN	input	TCELL1:IMUX.G1.DATA4
LOOPBACK0	input	TCELL0:IMUX.G0.DATA3
LOOPBACK1	input	TCELL0:IMUX.G1.DATA3
POWERDOWN	input	TCELL0:IMUX.G0.DATA2
REFCLK	input	TCELL0:IMUX.DCMCLK2
REFCLK2	input	TCELL0:IMUX.DCMCLK3
REFCLKSEL	input	TCELL0:IMUX.G1.DATA1
RXBUFSTATUS0	output	TCELL0:OUT.SEC15.TMIN
RXBUFSTATUS1	output	TCELL0:OUT.SEC14.TMIN
RXCHARISCOMMA0	output	TCELL1:OUT.SEC11.TMIN
RXCHARISCOMMA1	output	TCELL2:OUT.SEC11.TMIN
RXCHARISCOMMA2	output	TCELL3:OUT.SEC11.TMIN
RXCHARISCOMMA3	output	TCELL4:OUT.SEC11.TMIN
RXCHARISK0	output	TCELL1:OUT.SEC12.TMIN
RXCHARISK1	output	TCELL2:OUT.SEC12.TMIN
RXCHARISK2	output	TCELL3:OUT.SEC12.TMIN
RXCHARISK3	output	TCELL4:OUT.SEC12.TMIN
RXCHECKINGCRC	output	TCELL4:OUT.SEC8.TMIN
RXCLKCORCNT0	output	TCELL0:OUT.SEC11.TMIN
RXCLKCORCNT1	output	TCELL0:OUT.SEC10.TMIN
RXCLKCORCNT2	output	TCELL0:OUT.SEC9.TMIN
RXCOMMADET	output	TCELL0:OUT.FAN5.TMIN
RXCRCERR	output	TCELL3:OUT.SEC8.TMIN
RXDATA0	output	TCELL1:OUT.FAN0.TMIN
RXDATA1	output	TCELL1:OUT.FAN1.TMIN
RXDATA10	output	TCELL2:OUT.FAN2.TMIN
RXDATA11	output	TCELL2:OUT.FAN3.TMIN
RXDATA12	output	TCELL2:OUT.FAN4.TMIN
RXDATA13	output	TCELL2:OUT.FAN5.TMIN
RXDATA14	output	TCELL2:OUT.FAN6.TMIN
RXDATA15	output	TCELL2:OUT.FAN7.TMIN
RXDATA16	output	TCELL3:OUT.FAN0.TMIN
RXDATA17	output	TCELL3:OUT.FAN1.TMIN
RXDATA18	output	TCELL3:OUT.FAN2.TMIN
RXDATA19	output	TCELL3:OUT.FAN3.TMIN
RXDATA2	output	TCELL1:OUT.FAN2.TMIN
RXDATA20	output	TCELL3:OUT.FAN4.TMIN
RXDATA21	output	TCELL3:OUT.FAN5.TMIN
RXDATA22	output	TCELL3:OUT.FAN6.TMIN
RXDATA23	output	TCELL3:OUT.FAN7.TMIN
RXDATA24	output	TCELL4:OUT.FAN0.TMIN
RXDATA25	output	TCELL4:OUT.FAN1.TMIN
RXDATA26	output	TCELL4:OUT.FAN2.TMIN
RXDATA27	output	TCELL4:OUT.FAN3.TMIN
RXDATA28	output	TCELL4:OUT.FAN4.TMIN
RXDATA29	output	TCELL4:OUT.FAN5.TMIN
RXDATA3	output	TCELL1:OUT.FAN3.TMIN
RXDATA30	output	TCELL4:OUT.FAN6.TMIN
RXDATA31	output	TCELL4:OUT.FAN7.TMIN
RXDATA4	output	TCELL1:OUT.FAN4.TMIN
RXDATA5	output	TCELL1:OUT.FAN5.TMIN
RXDATA6	output	TCELL1:OUT.FAN6.TMIN
RXDATA7	output	TCELL1:OUT.FAN7.TMIN
RXDATA8	output	TCELL2:OUT.FAN0.TMIN
RXDATA9	output	TCELL2:OUT.FAN1.TMIN
RXDISPERR0	output	TCELL1:OUT.SEC14.TMIN
RXDISPERR1	output	TCELL2:OUT.SEC14.TMIN
RXDISPERR2	output	TCELL3:OUT.SEC14.TMIN
RXDISPERR3	output	TCELL4:OUT.SEC14.TMIN
RXLOSSOFSYNC0	output	TCELL1:OUT.SEC8.TMIN
RXLOSSOFSYNC1	output	TCELL2:OUT.SEC8.TMIN
RXNOTINTABLE0	output	TCELL1:OUT.SEC13.TMIN
RXNOTINTABLE1	output	TCELL2:OUT.SEC13.TMIN
RXNOTINTABLE2	output	TCELL3:OUT.SEC13.TMIN
RXNOTINTABLE3	output	TCELL4:OUT.SEC13.TMIN
RXPOLARITY	input	TCELL0:IMUX.G1.DATA2
RXREALIGN	output	TCELL0:OUT.SEC13.TMIN
RXRECCLK	output	TCELL0:OUT.FAN6.TMIN
RXRESET	input	TCELL0:IMUX.SR0
RXRUNDISP0	output	TCELL1:OUT.SEC15.TMIN
RXRUNDISP1	output	TCELL2:OUT.SEC15.TMIN
RXRUNDISP2	output	TCELL3:OUT.SEC15.TMIN
RXRUNDISP3	output	TCELL4:OUT.SEC15.TMIN
RXUSRCLK	input	TCELL0:IMUX.DCMCLK0
RXUSRCLK2	input	TCELL0:IMUX.DCMCLK1
TXBUFERR	output	TCELL0:OUT.FAN7.TMIN
TXBYPASS8B10B0	input	TCELL1:IMUX.G0.DATA2
TXBYPASS8B10B1	input	TCELL2:IMUX.G0.DATA2
TXBYPASS8B10B2	input	TCELL3:IMUX.G0.DATA2
TXBYPASS8B10B3	input	TCELL4:IMUX.G0.DATA2
TXCHARDISPMODE0	input	TCELL1:IMUX.G2.DATA2
TXCHARDISPMODE1	input	TCELL2:IMUX.G2.DATA2
TXCHARDISPMODE2	input	TCELL3:IMUX.G2.DATA2
TXCHARDISPMODE3	input	TCELL4:IMUX.G2.DATA2
TXCHARDISPVAL0	input	TCELL1:IMUX.G3.DATA2
TXCHARDISPVAL1	input	TCELL2:IMUX.G3.DATA2
TXCHARDISPVAL2	input	TCELL3:IMUX.G3.DATA2
TXCHARDISPVAL3	input	TCELL4:IMUX.G3.DATA2
TXCHARISK0	input	TCELL1:IMUX.G1.DATA2
TXCHARISK1	input	TCELL2:IMUX.G1.DATA2
TXCHARISK2	input	TCELL3:IMUX.G1.DATA2
TXCHARISK3	input	TCELL4:IMUX.G1.DATA2
TXDATA0	input	TCELL1:IMUX.G0.DATA0
TXDATA1	input	TCELL1:IMUX.G1.DATA0
TXDATA10	input	TCELL2:IMUX.G2.DATA0
TXDATA11	input	TCELL2:IMUX.G3.DATA0
TXDATA12	input	TCELL2:IMUX.G0.DATA1
TXDATA13	input	TCELL2:IMUX.G1.DATA1
TXDATA14	input	TCELL2:IMUX.G2.DATA1
TXDATA15	input	TCELL2:IMUX.G3.DATA1
TXDATA16	input	TCELL3:IMUX.G0.DATA0
TXDATA17	input	TCELL3:IMUX.G1.DATA0
TXDATA18	input	TCELL3:IMUX.G2.DATA0
TXDATA19	input	TCELL3:IMUX.G3.DATA0
TXDATA2	input	TCELL1:IMUX.G2.DATA0
TXDATA20	input	TCELL3:IMUX.G0.DATA1
TXDATA21	input	TCELL3:IMUX.G1.DATA1
TXDATA22	input	TCELL3:IMUX.G2.DATA1
TXDATA23	input	TCELL3:IMUX.G3.DATA1
TXDATA24	input	TCELL4:IMUX.G0.DATA0
TXDATA25	input	TCELL4:IMUX.G1.DATA0
TXDATA26	input	TCELL4:IMUX.G2.DATA0
TXDATA27	input	TCELL4:IMUX.G3.DATA0
TXDATA28	input	TCELL4:IMUX.G0.DATA1
TXDATA29	input	TCELL4:IMUX.G1.DATA1
TXDATA3	input	TCELL1:IMUX.G3.DATA0
TXDATA30	input	TCELL4:IMUX.G2.DATA1
TXDATA31	input	TCELL4:IMUX.G3.DATA1
TXDATA4	input	TCELL1:IMUX.G0.DATA1
TXDATA5	input	TCELL1:IMUX.G1.DATA1
TXDATA6	input	TCELL1:IMUX.G2.DATA1
TXDATA7	input	TCELL1:IMUX.G3.DATA1
TXDATA8	input	TCELL2:IMUX.G0.DATA0
TXDATA9	input	TCELL2:IMUX.G1.DATA0
TXFORCECRCERR	input	TCELL4:IMUX.G3.DATA3
TXINHIBIT	input	TCELL0:IMUX.G3.DATA3
TXKERR0	output	TCELL1:OUT.SEC9.TMIN
TXKERR1	output	TCELL2:OUT.SEC9.TMIN
TXKERR2	output	TCELL3:OUT.SEC9.TMIN
TXKERR3	output	TCELL4:OUT.SEC9.TMIN
TXPOLARITY	input	TCELL0:IMUX.G2.DATA3
TXRESET	input	TCELL1:IMUX.SR0
TXRUNDISP0	output	TCELL1:OUT.SEC10.TMIN
TXRUNDISP1	output	TCELL2:OUT.SEC10.TMIN
TXRUNDISP2	output	TCELL3:OUT.SEC10.TMIN
TXRUNDISP3	output	TCELL4:OUT.SEC10.TMIN
TXUSRCLK	input	TCELL1:IMUX.CLK0
TXUSRCLK2	input	TCELL1:IMUX.CLK1

Bel IPAD_RXP

virtex2 GIGABIT.T bel IPAD_RXP
Pin	Direction	Wires

Bel IPAD_RXN

virtex2 GIGABIT.T bel IPAD_RXN
Pin	Direction	Wires

Bel OPAD_TXP

virtex2 GIGABIT.T bel OPAD_TXP
Pin	Direction	Wires

Bel OPAD_TXN

virtex2 GIGABIT.T bel OPAD_TXN
Pin	Direction	Wires

Bel wires

virtex2 GIGABIT.T bel wires
Wire	Pins
TCELL0:IMUX.DCMCLK0	GT.RXUSRCLK
TCELL0:IMUX.DCMCLK1	GT.RXUSRCLK2
TCELL0:IMUX.DCMCLK2	GT.REFCLK
TCELL0:IMUX.DCMCLK3	GT.REFCLK2
TCELL0:IMUX.SR0	GT.RXRESET
TCELL0:IMUX.G0.DATA0	GT.CHBONDI0
TCELL0:IMUX.G0.DATA1	GT.ENCHANSYNC
TCELL0:IMUX.G0.DATA2	GT.POWERDOWN
TCELL0:IMUX.G0.DATA3	GT.LOOPBACK0
TCELL0:IMUX.G1.DATA0	GT.CHBONDI1
TCELL0:IMUX.G1.DATA1	GT.REFCLKSEL
TCELL0:IMUX.G1.DATA2	GT.RXPOLARITY
TCELL0:IMUX.G1.DATA3	GT.LOOPBACK1
TCELL0:IMUX.G2.DATA0	GT.CHBONDI2
TCELL0:IMUX.G2.DATA2	GT.CONFIGIN
TCELL0:IMUX.G2.DATA3	GT.TXPOLARITY
TCELL0:IMUX.G3.DATA0	GT.CHBONDI3
TCELL0:IMUX.G3.DATA2	GT.CONFIGENABLE
TCELL0:IMUX.G3.DATA3	GT.TXINHIBIT
TCELL0:OUT.FAN0.TMIN	GT.CHBONDO0
TCELL0:OUT.FAN1.TMIN	GT.CHBONDO1
TCELL0:OUT.FAN2.TMIN	GT.CHBONDO2
TCELL0:OUT.FAN3.TMIN	GT.CHBONDO3
TCELL0:OUT.FAN4.TMIN	GT.CHBONDDONE
TCELL0:OUT.FAN5.TMIN	GT.RXCOMMADET
TCELL0:OUT.FAN6.TMIN	GT.RXRECCLK
TCELL0:OUT.FAN7.TMIN	GT.TXBUFERR
TCELL0:OUT.SEC9.TMIN	GT.RXCLKCORCNT2
TCELL0:OUT.SEC10.TMIN	GT.RXCLKCORCNT1
TCELL0:OUT.SEC11.TMIN	GT.RXCLKCORCNT0
TCELL0:OUT.SEC12.TMIN	GT.CONFIGOUT
TCELL0:OUT.SEC13.TMIN	GT.RXREALIGN
TCELL0:OUT.SEC14.TMIN	GT.RXBUFSTATUS1
TCELL0:OUT.SEC15.TMIN	GT.RXBUFSTATUS0
TCELL1:IMUX.CLK0	GT.TXUSRCLK
TCELL1:IMUX.CLK1	GT.TXUSRCLK2
TCELL1:IMUX.SR0	GT.TXRESET
TCELL1:IMUX.G0.DATA0	GT.TXDATA0
TCELL1:IMUX.G0.DATA1	GT.TXDATA4
TCELL1:IMUX.G0.DATA2	GT.TXBYPASS8B10B0
TCELL1:IMUX.G1.DATA0	GT.TXDATA1
TCELL1:IMUX.G1.DATA1	GT.TXDATA5
TCELL1:IMUX.G1.DATA2	GT.TXCHARISK0
TCELL1:IMUX.G1.DATA4	GT.ENPCOMMAALIGN
TCELL1:IMUX.G1.DATA7	GT.ENMCOMMAALIGN
TCELL1:IMUX.G2.DATA0	GT.TXDATA2
TCELL1:IMUX.G2.DATA1	GT.TXDATA6
TCELL1:IMUX.G2.DATA2	GT.TXCHARDISPMODE0
TCELL1:IMUX.G3.DATA0	GT.TXDATA3
TCELL1:IMUX.G3.DATA1	GT.TXDATA7
TCELL1:IMUX.G3.DATA2	GT.TXCHARDISPVAL0
TCELL1:OUT.FAN0.TMIN	GT.RXDATA0
TCELL1:OUT.FAN1.TMIN	GT.RXDATA1
TCELL1:OUT.FAN2.TMIN	GT.RXDATA2
TCELL1:OUT.FAN3.TMIN	GT.RXDATA3
TCELL1:OUT.FAN4.TMIN	GT.RXDATA4
TCELL1:OUT.FAN5.TMIN	GT.RXDATA5
TCELL1:OUT.FAN6.TMIN	GT.RXDATA6
TCELL1:OUT.FAN7.TMIN	GT.RXDATA7
TCELL1:OUT.SEC8.TMIN	GT.RXLOSSOFSYNC0
TCELL1:OUT.SEC9.TMIN	GT.TXKERR0
TCELL1:OUT.SEC10.TMIN	GT.TXRUNDISP0
TCELL1:OUT.SEC11.TMIN	GT.RXCHARISCOMMA0
TCELL1:OUT.SEC12.TMIN	GT.RXCHARISK0
TCELL1:OUT.SEC13.TMIN	GT.RXNOTINTABLE0
TCELL1:OUT.SEC14.TMIN	GT.RXDISPERR0
TCELL1:OUT.SEC15.TMIN	GT.RXRUNDISP0
TCELL2:IMUX.G0.DATA0	GT.TXDATA8
TCELL2:IMUX.G0.DATA1	GT.TXDATA12
TCELL2:IMUX.G0.DATA2	GT.TXBYPASS8B10B1
TCELL2:IMUX.G1.DATA0	GT.TXDATA9
TCELL2:IMUX.G1.DATA1	GT.TXDATA13
TCELL2:IMUX.G1.DATA2	GT.TXCHARISK1
TCELL2:IMUX.G2.DATA0	GT.TXDATA10
TCELL2:IMUX.G2.DATA1	GT.TXDATA14
TCELL2:IMUX.G2.DATA2	GT.TXCHARDISPMODE1
TCELL2:IMUX.G3.DATA0	GT.TXDATA11
TCELL2:IMUX.G3.DATA1	GT.TXDATA15
TCELL2:IMUX.G3.DATA2	GT.TXCHARDISPVAL1
TCELL2:OUT.FAN0.TMIN	GT.RXDATA8
TCELL2:OUT.FAN1.TMIN	GT.RXDATA9
TCELL2:OUT.FAN2.TMIN	GT.RXDATA10
TCELL2:OUT.FAN3.TMIN	GT.RXDATA11
TCELL2:OUT.FAN4.TMIN	GT.RXDATA12
TCELL2:OUT.FAN5.TMIN	GT.RXDATA13
TCELL2:OUT.FAN6.TMIN	GT.RXDATA14
TCELL2:OUT.FAN7.TMIN	GT.RXDATA15
TCELL2:OUT.SEC8.TMIN	GT.RXLOSSOFSYNC1
TCELL2:OUT.SEC9.TMIN	GT.TXKERR1
TCELL2:OUT.SEC10.TMIN	GT.TXRUNDISP1
TCELL2:OUT.SEC11.TMIN	GT.RXCHARISCOMMA1
TCELL2:OUT.SEC12.TMIN	GT.RXCHARISK1
TCELL2:OUT.SEC13.TMIN	GT.RXNOTINTABLE1
TCELL2:OUT.SEC14.TMIN	GT.RXDISPERR1
TCELL2:OUT.SEC15.TMIN	GT.RXRUNDISP1
TCELL3:IMUX.G0.DATA0	GT.TXDATA16
TCELL3:IMUX.G0.DATA1	GT.TXDATA20
TCELL3:IMUX.G0.DATA2	GT.TXBYPASS8B10B2
TCELL3:IMUX.G1.DATA0	GT.TXDATA17
TCELL3:IMUX.G1.DATA1	GT.TXDATA21
TCELL3:IMUX.G1.DATA2	GT.TXCHARISK2
TCELL3:IMUX.G2.DATA0	GT.TXDATA18
TCELL3:IMUX.G2.DATA1	GT.TXDATA22
TCELL3:IMUX.G2.DATA2	GT.TXCHARDISPMODE2
TCELL3:IMUX.G3.DATA0	GT.TXDATA19
TCELL3:IMUX.G3.DATA1	GT.TXDATA23
TCELL3:IMUX.G3.DATA2	GT.TXCHARDISPVAL2
TCELL3:OUT.FAN0.TMIN	GT.RXDATA16
TCELL3:OUT.FAN1.TMIN	GT.RXDATA17
TCELL3:OUT.FAN2.TMIN	GT.RXDATA18
TCELL3:OUT.FAN3.TMIN	GT.RXDATA19
TCELL3:OUT.FAN4.TMIN	GT.RXDATA20
TCELL3:OUT.FAN5.TMIN	GT.RXDATA21
TCELL3:OUT.FAN6.TMIN	GT.RXDATA22
TCELL3:OUT.FAN7.TMIN	GT.RXDATA23
TCELL3:OUT.SEC8.TMIN	GT.RXCRCERR
TCELL3:OUT.SEC9.TMIN	GT.TXKERR2
TCELL3:OUT.SEC10.TMIN	GT.TXRUNDISP2
TCELL3:OUT.SEC11.TMIN	GT.RXCHARISCOMMA2
TCELL3:OUT.SEC12.TMIN	GT.RXCHARISK2
TCELL3:OUT.SEC13.TMIN	GT.RXNOTINTABLE2
TCELL3:OUT.SEC14.TMIN	GT.RXDISPERR2
TCELL3:OUT.SEC15.TMIN	GT.RXRUNDISP2
TCELL4:IMUX.G0.DATA0	GT.TXDATA24
TCELL4:IMUX.G0.DATA1	GT.TXDATA28
TCELL4:IMUX.G0.DATA2	GT.TXBYPASS8B10B3
TCELL4:IMUX.G1.DATA0	GT.TXDATA25
TCELL4:IMUX.G1.DATA1	GT.TXDATA29
TCELL4:IMUX.G1.DATA2	GT.TXCHARISK3
TCELL4:IMUX.G2.DATA0	GT.TXDATA26
TCELL4:IMUX.G2.DATA1	GT.TXDATA30
TCELL4:IMUX.G2.DATA2	GT.TXCHARDISPMODE3
TCELL4:IMUX.G3.DATA0	GT.TXDATA27
TCELL4:IMUX.G3.DATA1	GT.TXDATA31
TCELL4:IMUX.G3.DATA2	GT.TXCHARDISPVAL3
TCELL4:IMUX.G3.DATA3	GT.TXFORCECRCERR
TCELL4:OUT.FAN0.TMIN	GT.RXDATA24
TCELL4:OUT.FAN1.TMIN	GT.RXDATA25
TCELL4:OUT.FAN2.TMIN	GT.RXDATA26
TCELL4:OUT.FAN3.TMIN	GT.RXDATA27
TCELL4:OUT.FAN4.TMIN	GT.RXDATA28
TCELL4:OUT.FAN5.TMIN	GT.RXDATA29
TCELL4:OUT.FAN6.TMIN	GT.RXDATA30
TCELL4:OUT.FAN7.TMIN	GT.RXDATA31
TCELL4:OUT.SEC8.TMIN	GT.RXCHECKINGCRC
TCELL4:OUT.SEC9.TMIN	GT.TXKERR3
TCELL4:OUT.SEC10.TMIN	GT.TXRUNDISP3
TCELL4:OUT.SEC11.TMIN	GT.RXCHARISCOMMA3
TCELL4:OUT.SEC12.TMIN	GT.RXCHARISK3
TCELL4:OUT.SEC13.TMIN	GT.RXNOTINTABLE3
TCELL4:OUT.SEC14.TMIN	GT.RXDISPERR3
TCELL4:OUT.SEC15.TMIN	GT.RXRUNDISP3

Bitstream

virtex2 GIGABIT.T bittile 0
Bit	Frame
Bit	0
79	GT:TERMINATION_IMP[0]
78	GT:TX_DIFF_CTRL[1]
77	GT:TX_DIFF_CTRL[0]
76	GT:TX_PREEMPHASIS[0]
75	GT:TX_PREEMPHASIS[1]
74	GT:ENABLE
73	GT:TX_DIFF_CTRL[2]
72	-
71	-
70	-
69	-
68	-
67	-
66	-
65	-
64	-
63	-
62	-
61	-
60	-
59	-
58	-
57	-
56	-
55	-
54	-
53	-
52	-
51	-
50	-
49	-
48	-
47	-
46	-
45	GT:TX_CRC_FORCE_VALUE[7]
44	GT:TX_CRC_FORCE_VALUE[6]
43	GT:TX_CRC_FORCE_VALUE[5]
42	GT:TX_CRC_FORCE_VALUE[4]
41	GT:TX_CRC_FORCE_VALUE[3]
40	GT:TX_CRC_FORCE_VALUE[2]
39	GT:TX_CRC_FORCE_VALUE[1]
38	GT:TX_CRC_FORCE_VALUE[0]
37	GT:TX_CRC_USE
36	GT:TX_BUFFER_USE
35	GT:SERDES_10B
34	-
33	-
32	-
31	-
30	-
29	-
28	-
27	-
26	-
25	-
24	-
23	-
22	-
21	-
20	GT:CRC_END_OF_PKT[7]
19	GT:CRC_END_OF_PKT[6]
18	GT:CRC_END_OF_PKT[5]
17	GT:CRC_END_OF_PKT[4]
16	GT:CRC_END_OF_PKT[3]
15	GT:CRC_END_OF_PKT[2]
14	GT:CRC_END_OF_PKT[1]
13	GT:CRC_END_OF_PKT[0]
12	GT:CRC_START_OF_PKT[7]
11	GT:CRC_START_OF_PKT[6]
10	GT:CRC_START_OF_PKT[5]
9	GT:CRC_START_OF_PKT[4]
8	GT:CRC_START_OF_PKT[3]
7	GT:CRC_START_OF_PKT[2]
6	GT:CRC_START_OF_PKT[1]
5	GT:CRC_START_OF_PKT[0]
4	GT:CRC_FORMAT[1]
3	GT:CRC_FORMAT[0]
2	GT:REF_CLK_V_SEL
1	GT:TX_DATA_WIDTH[1]
0	GT:TX_DATA_WIDTH[0]

virtex2 GIGABIT.T bittile 1
Bit	Frame
Bit	0
79	GT:CLK_COR_SEQ_1_1[10]
78	GT:CLK_COR_SEQ_1_1[9]
77	GT:CLK_COR_SEQ_1_1[8]
76	GT:CLK_COR_SEQ_1_1[7]
75	GT:CLK_COR_SEQ_1_1[6]
74	GT:CLK_COR_SEQ_1_1[5]
73	GT:CLK_COR_SEQ_1_1[4]
72	GT:CLK_COR_SEQ_1_1[3]
71	GT:CLK_COR_SEQ_1_1[2]
70	GT:CLK_COR_SEQ_1_1[1]
69	GT:CLK_COR_SEQ_1_1[0]
68	GT:CLK_COR_SEQ_1_2[10]
67	GT:CLK_COR_SEQ_1_2[9]
66	GT:CLK_COR_SEQ_1_2[8]
65	GT:CLK_COR_SEQ_1_2[7]
64	GT:CLK_COR_SEQ_1_2[6]
63	GT:CLK_COR_SEQ_1_2[5]
62	GT:CLK_COR_SEQ_1_2[4]
61	GT:CLK_COR_SEQ_1_2[3]
60	GT:CLK_COR_SEQ_1_2[2]
59	GT:CLK_COR_SEQ_1_2[1]
58	GT:CLK_COR_SEQ_1_2[0]
57	GT:CLK_COR_SEQ_1_3[10]
56	GT:CLK_COR_SEQ_1_3[9]
55	GT:CLK_COR_SEQ_1_3[8]
54	GT:CLK_COR_SEQ_1_3[7]
53	GT:CLK_COR_SEQ_1_3[6]
52	GT:CLK_COR_SEQ_1_3[5]
51	GT:CLK_COR_SEQ_1_3[4]
50	GT:CLK_COR_SEQ_1_3[3]
49	GT:CLK_COR_SEQ_1_3[2]
48	GT:CLK_COR_SEQ_1_3[1]
47	GT:CLK_COR_SEQ_1_3[0]
46	GT:CLK_COR_SEQ_1_4[10]
45	GT:CLK_COR_SEQ_1_4[9]
44	GT:CLK_COR_SEQ_1_4[8]
43	GT:CLK_COR_SEQ_1_4[7]
42	GT:CLK_COR_SEQ_1_4[6]
41	GT:CLK_COR_SEQ_1_4[5]
40	GT:CLK_COR_SEQ_1_4[4]
39	GT:CLK_COR_SEQ_1_4[3]
38	GT:CLK_COR_SEQ_1_4[2]
37	GT:CLK_COR_SEQ_1_4[1]
36	GT:CLK_COR_SEQ_1_4[0]
35	-
34	GT:PCOMMA_DETECT
33	-
32	GT:PCOMMA_10B_VALUE[0]
31	GT:PCOMMA_10B_VALUE[1]
30	GT:PCOMMA_10B_VALUE[2]
29	GT:PCOMMA_10B_VALUE[3]
28	GT:PCOMMA_10B_VALUE[4]
27	GT:PCOMMA_10B_VALUE[5]
26	GT:PCOMMA_10B_VALUE[6]
25	GT:PCOMMA_10B_VALUE[7]
24	GT:PCOMMA_10B_VALUE[8]
23	GT:PCOMMA_10B_VALUE[9]
22	GT:MCOMMA_DETECT
21	-
20	GT:MCOMMA_10B_VALUE[0]
19	GT:MCOMMA_10B_VALUE[1]
18	GT:MCOMMA_10B_VALUE[2]
17	GT:MCOMMA_10B_VALUE[3]
16	GT:MCOMMA_10B_VALUE[4]
15	GT:MCOMMA_10B_VALUE[5]
14	GT:MCOMMA_10B_VALUE[6]
13	GT:MCOMMA_10B_VALUE[7]
12	GT:MCOMMA_10B_VALUE[8]
11	GT:MCOMMA_10B_VALUE[9]
10	GT:COMMA_10B_MASK[0]
9	GT:COMMA_10B_MASK[1]
8	GT:COMMA_10B_MASK[2]
7	GT:COMMA_10B_MASK[3]
6	GT:COMMA_10B_MASK[4]
5	GT:COMMA_10B_MASK[5]
4	GT:COMMA_10B_MASK[6]
3	GT:COMMA_10B_MASK[7]
2	GT:COMMA_10B_MASK[8]
1	GT:COMMA_10B_MASK[9]
0	GT:ALIGN_COMMA_MSB

virtex2 GIGABIT.T bittile 2
Bit	Frame
Bit	0
79	GT:CLK_COR_SEQ_2_1[10]
78	GT:CLK_COR_SEQ_2_1[9]
77	GT:CLK_COR_SEQ_2_1[8]
76	GT:CLK_COR_SEQ_2_1[7]
75	GT:CLK_COR_SEQ_2_1[6]
74	GT:CLK_COR_SEQ_2_1[5]
73	GT:CLK_COR_SEQ_2_1[4]
72	GT:CLK_COR_SEQ_2_1[3]
71	GT:CLK_COR_SEQ_2_1[2]
70	GT:CLK_COR_SEQ_2_1[1]
69	GT:CLK_COR_SEQ_2_1[0]
68	GT:CLK_COR_SEQ_2_2[10]
67	GT:CLK_COR_SEQ_2_2[9]
66	GT:CLK_COR_SEQ_2_2[8]
65	GT:CLK_COR_SEQ_2_2[7]
64	GT:CLK_COR_SEQ_2_2[6]
63	GT:CLK_COR_SEQ_2_2[5]
62	GT:CLK_COR_SEQ_2_2[4]
61	GT:CLK_COR_SEQ_2_2[3]
60	GT:CLK_COR_SEQ_2_2[2]
59	GT:CLK_COR_SEQ_2_2[1]
58	GT:CLK_COR_SEQ_2_2[0]
57	GT:CLK_COR_SEQ_2_3[10]
56	GT:CLK_COR_SEQ_2_3[9]
55	GT:CLK_COR_SEQ_2_3[8]
54	GT:CLK_COR_SEQ_2_3[7]
53	GT:CLK_COR_SEQ_2_3[6]
52	GT:CLK_COR_SEQ_2_3[5]
51	GT:CLK_COR_SEQ_2_3[4]
50	GT:CLK_COR_SEQ_2_3[3]
49	GT:CLK_COR_SEQ_2_3[2]
48	GT:CLK_COR_SEQ_2_3[1]
47	GT:CLK_COR_SEQ_2_3[0]
46	GT:CLK_COR_SEQ_2_4[10]
45	GT:CLK_COR_SEQ_2_4[9]
44	GT:CLK_COR_SEQ_2_4[8]
43	GT:CLK_COR_SEQ_2_4[7]
42	GT:CLK_COR_SEQ_2_4[6]
41	GT:CLK_COR_SEQ_2_4[5]
40	GT:CLK_COR_SEQ_2_4[4]
39	GT:CLK_COR_SEQ_2_4[3]
38	GT:CLK_COR_SEQ_2_4[2]
37	GT:CLK_COR_SEQ_2_4[1]
36	GT:CLK_COR_SEQ_2_4[0]
35	GT:CLK_COR_SEQ_2_USE
34	GT:CLK_COR_SEQ_LEN[1]
33	GT:CLK_COR_SEQ_LEN[0]
32	GT:DEC_MCOMMA_DETECT
31	GT:DEC_PCOMMA_DETECT
30	GT:DEC_VALID_COMMA_ONLY
29	GT:RX_BUFFER_LIMIT[3]
28	GT:RX_BUFFER_LIMIT[2]
27	GT:RX_BUFFER_LIMIT[1]
26	GT:RX_BUFFER_LIMIT[0]
25	GT:RX_BUFFER_USE
24	GT:RX_DECODE_USE
23	GT:CHAN_BOND_ONE_SHOT
22	-
21	-
20	-
19	-
18	-
17	GT:CLK_COR_REPEAT_WAIT[4]
16	GT:CLK_COR_REPEAT_WAIT[3]
15	GT:CLK_COR_REPEAT_WAIT[2]
14	GT:CLK_COR_REPEAT_WAIT[1]
13	GT:CLK_COR_REPEAT_WAIT[0]
12	GT:CLK_COR_KEEP_IDLE
11	GT:CLK_COR_INSERT_IDLE_FLAG
10	GT:CLK_CORRECT_USE
9	GT:CHAN_BOND_OFFSET[3]
8	GT:CHAN_BOND_OFFSET[2]
7	GT:CHAN_BOND_OFFSET[1]
6	GT:CHAN_BOND_OFFSET[0]
5	GT:CHAN_BOND_MODE[1]
4	GT:CHAN_BOND_MODE[0]
3	-
2	-
1	GT:RX_DATA_WIDTH[1]
0	GT:RX_DATA_WIDTH[0]

virtex2 GIGABIT.T bittile 3
Bit	Frame
Bit	0
79	GT:CHAN_BOND_SEQ_1_1[10]
78	GT:CHAN_BOND_SEQ_1_1[9]
77	GT:CHAN_BOND_SEQ_1_1[8]
76	GT:CHAN_BOND_SEQ_1_1[7]
75	GT:CHAN_BOND_SEQ_1_1[6]
74	GT:CHAN_BOND_SEQ_1_1[5]
73	GT:CHAN_BOND_SEQ_1_1[4]
72	GT:CHAN_BOND_SEQ_1_1[3]
71	GT:CHAN_BOND_SEQ_1_1[2]
70	GT:CHAN_BOND_SEQ_1_1[1]
69	GT:CHAN_BOND_SEQ_1_1[0]
68	GT:CHAN_BOND_SEQ_1_2[10]
67	GT:CHAN_BOND_SEQ_1_2[9]
66	GT:CHAN_BOND_SEQ_1_2[8]
65	GT:CHAN_BOND_SEQ_1_2[7]
64	GT:CHAN_BOND_SEQ_1_2[6]
63	GT:CHAN_BOND_SEQ_1_2[5]
62	GT:CHAN_BOND_SEQ_1_2[4]
61	GT:CHAN_BOND_SEQ_1_2[3]
60	GT:CHAN_BOND_SEQ_1_2[2]
59	GT:CHAN_BOND_SEQ_1_2[1]
58	GT:CHAN_BOND_SEQ_1_2[0]
57	GT:CHAN_BOND_SEQ_1_3[10]
56	GT:CHAN_BOND_SEQ_1_3[9]
55	GT:CHAN_BOND_SEQ_1_3[8]
54	GT:CHAN_BOND_SEQ_1_3[7]
53	GT:CHAN_BOND_SEQ_1_3[6]
52	GT:CHAN_BOND_SEQ_1_3[5]
51	GT:CHAN_BOND_SEQ_1_3[4]
50	GT:CHAN_BOND_SEQ_1_3[3]
49	GT:CHAN_BOND_SEQ_1_3[2]
48	GT:CHAN_BOND_SEQ_1_3[1]
47	GT:CHAN_BOND_SEQ_1_3[0]
46	GT:CHAN_BOND_SEQ_1_4[10]
45	GT:CHAN_BOND_SEQ_1_4[9]
44	GT:CHAN_BOND_SEQ_1_4[8]
43	GT:CHAN_BOND_SEQ_1_4[7]
42	GT:CHAN_BOND_SEQ_1_4[6]
41	GT:CHAN_BOND_SEQ_1_4[5]
40	GT:CHAN_BOND_SEQ_1_4[4]
39	GT:CHAN_BOND_SEQ_1_4[3]
38	GT:CHAN_BOND_SEQ_1_4[2]
37	GT:CHAN_BOND_SEQ_1_4[1]
36	GT:CHAN_BOND_SEQ_1_4[0]
35	GT:RX_CRC_USE
34	GT:TEST_MODE_6
33	GT:TEST_MODE_5
32	GT:TEST_MODE_4
31	GT:TEST_MODE_3
30	GT:TEST_MODE_2
29	GT:TEST_MODE_1
28	-
27	-
26	-
25	-
24	-
23	-
22	-
21	-
20	-
19	-
18	-
17	-
16	-
15	-
14	-
13	-
12	-
11	-
10	-
9	-
8	-
7	-
6	-
5	-
4	-
3	-
2	-
1	-
0	-

virtex2 GIGABIT.T bittile 4
Bit	Frame
Bit	0
79	GT:CHAN_BOND_SEQ_2_1[10]
78	GT:CHAN_BOND_SEQ_2_1[9]
77	GT:CHAN_BOND_SEQ_2_1[8]
76	GT:CHAN_BOND_SEQ_2_1[7]
75	GT:CHAN_BOND_SEQ_2_1[6]
74	GT:CHAN_BOND_SEQ_2_1[5]
73	GT:CHAN_BOND_SEQ_2_1[4]
72	GT:CHAN_BOND_SEQ_2_1[3]
71	GT:CHAN_BOND_SEQ_2_1[2]
70	GT:CHAN_BOND_SEQ_2_1[1]
69	GT:CHAN_BOND_SEQ_2_1[0]
68	GT:CHAN_BOND_SEQ_2_2[10]
67	GT:CHAN_BOND_SEQ_2_2[9]
66	GT:CHAN_BOND_SEQ_2_2[8]
65	GT:CHAN_BOND_SEQ_2_2[7]
64	GT:CHAN_BOND_SEQ_2_2[6]
63	GT:CHAN_BOND_SEQ_2_2[5]
62	GT:CHAN_BOND_SEQ_2_2[4]
61	GT:CHAN_BOND_SEQ_2_2[3]
60	GT:CHAN_BOND_SEQ_2_2[2]
59	GT:CHAN_BOND_SEQ_2_2[1]
58	GT:CHAN_BOND_SEQ_2_2[0]
57	GT:CHAN_BOND_SEQ_2_3[10]
56	GT:CHAN_BOND_SEQ_2_3[9]
55	GT:CHAN_BOND_SEQ_2_3[8]
54	GT:CHAN_BOND_SEQ_2_3[7]
53	GT:CHAN_BOND_SEQ_2_3[6]
52	GT:CHAN_BOND_SEQ_2_3[5]
51	GT:CHAN_BOND_SEQ_2_3[4]
50	GT:CHAN_BOND_SEQ_2_3[3]
49	GT:CHAN_BOND_SEQ_2_3[2]
48	GT:CHAN_BOND_SEQ_2_3[1]
47	GT:CHAN_BOND_SEQ_2_3[0]
46	GT:CHAN_BOND_SEQ_2_4[10]
45	GT:CHAN_BOND_SEQ_2_4[9]
44	GT:CHAN_BOND_SEQ_2_4[8]
43	GT:CHAN_BOND_SEQ_2_4[7]
42	GT:CHAN_BOND_SEQ_2_4[6]
41	GT:CHAN_BOND_SEQ_2_4[5]
40	GT:CHAN_BOND_SEQ_2_4[4]
39	GT:CHAN_BOND_SEQ_2_4[3]
38	GT:CHAN_BOND_SEQ_2_4[2]
37	GT:CHAN_BOND_SEQ_2_4[1]
36	GT:CHAN_BOND_SEQ_2_4[0]
35	GT:CHAN_BOND_SEQ_2_USE
34	GT:CHAN_BOND_SEQ_LEN[1]
33	GT:CHAN_BOND_SEQ_LEN[0]
32	GT:CHAN_BOND_WAIT[3]
31	GT:CHAN_BOND_WAIT[2]
30	GT:CHAN_BOND_WAIT[1]
29	GT:CHAN_BOND_WAIT[0]
28	GT:CHAN_BOND_LIMIT[4]
27	GT:CHAN_BOND_LIMIT[3]
26	GT:CHAN_BOND_LIMIT[2]
25	GT:CHAN_BOND_LIMIT[1]
24	GT:CHAN_BOND_LIMIT[0]
23	GT:RX_LOSS_OF_SYNC_FSM
22	GT:RX_LOS_INVALID_INCR[2]
21	GT:RX_LOS_INVALID_INCR[1]
20	GT:RX_LOS_INVALID_INCR[0]
19	GT:RX_LOS_THRESHOLD[2]
18	GT:RX_LOS_THRESHOLD[1]
17	GT:RX_LOS_THRESHOLD[0]
16	-
15	-
14	-
13	-
12	-
11	-
10	-
9	-
8	-
7	-
6	-
5	-
4	-
3	-
2	-
1	-
0	-

GT:ALIGN_COMMA_MSB	1.0.0
GT:CHAN_BOND_ONE_SHOT	2.0.23
GT:CHAN_BOND_SEQ_2_USE	4.0.35
GT:CLK_CORRECT_USE	2.0.10
GT:CLK_COR_INSERT_IDLE_FLAG	2.0.11
GT:CLK_COR_KEEP_IDLE	2.0.12
GT:CLK_COR_SEQ_2_USE	2.0.35
GT:DEC_MCOMMA_DETECT	2.0.32
GT:DEC_PCOMMA_DETECT	2.0.31
GT:DEC_VALID_COMMA_ONLY	2.0.30
GT:ENABLE	0.0.74
GT:MCOMMA_DETECT	1.0.22
GT:PCOMMA_DETECT	1.0.34
GT:REF_CLK_V_SEL	0.0.2
GT:RX_BUFFER_USE	2.0.25
GT:RX_CRC_USE	3.0.35
GT:RX_DECODE_USE	2.0.24
GT:RX_LOSS_OF_SYNC_FSM	4.0.23
GT:SERDES_10B	0.0.35
GT:TEST_MODE_1	3.0.29
GT:TEST_MODE_2	3.0.30
GT:TEST_MODE_3	3.0.31
GT:TEST_MODE_4	3.0.32
GT:TEST_MODE_5	3.0.33
GT:TEST_MODE_6	3.0.34
GT:TX_BUFFER_USE	0.0.36
GT:TX_CRC_USE	0.0.37
non-inverted	[0]

GT:CHAN_BOND_LIMIT	4.0.28	4.0.27	4.0.26	4.0.25	4.0.24
GT:CLK_COR_REPEAT_WAIT	2.0.17	2.0.16	2.0.15	2.0.14	2.0.13
non-inverted	[4]	[3]	[2]	[1]	[0]

GT:CHAN_BOND_MODE	2.0.5	2.0.4
NONE	0	0
MASTER	0	1
SLAVE_1_HOP	1	0
SLAVE_2_HOPS	1	1

GT:CHAN_BOND_OFFSET	2.0.9	2.0.8	2.0.7	2.0.6
GT:CHAN_BOND_WAIT	4.0.32	4.0.31	4.0.30	4.0.29
GT:RX_BUFFER_LIMIT	2.0.29	2.0.28	2.0.27	2.0.26
non-inverted	[3]	[2]	[1]	[0]

GT:CHAN_BOND_SEQ_1_1	3.0.79	3.0.78	3.0.77	3.0.76	3.0.75	3.0.74	3.0.73	3.0.72	3.0.71	3.0.70	3.0.69
GT:CHAN_BOND_SEQ_1_2	3.0.68	3.0.67	3.0.66	3.0.65	3.0.64	3.0.63	3.0.62	3.0.61	3.0.60	3.0.59	3.0.58
GT:CHAN_BOND_SEQ_1_3	3.0.57	3.0.56	3.0.55	3.0.54	3.0.53	3.0.52	3.0.51	3.0.50	3.0.49	3.0.48	3.0.47
GT:CHAN_BOND_SEQ_1_4	3.0.46	3.0.45	3.0.44	3.0.43	3.0.42	3.0.41	3.0.40	3.0.39	3.0.38	3.0.37	3.0.36
GT:CHAN_BOND_SEQ_2_1	4.0.79	4.0.78	4.0.77	4.0.76	4.0.75	4.0.74	4.0.73	4.0.72	4.0.71	4.0.70	4.0.69
GT:CHAN_BOND_SEQ_2_2	4.0.68	4.0.67	4.0.66	4.0.65	4.0.64	4.0.63	4.0.62	4.0.61	4.0.60	4.0.59	4.0.58
GT:CHAN_BOND_SEQ_2_3	4.0.57	4.0.56	4.0.55	4.0.54	4.0.53	4.0.52	4.0.51	4.0.50	4.0.49	4.0.48	4.0.47
GT:CHAN_BOND_SEQ_2_4	4.0.46	4.0.45	4.0.44	4.0.43	4.0.42	4.0.41	4.0.40	4.0.39	4.0.38	4.0.37	4.0.36
GT:CLK_COR_SEQ_1_1	1.0.79	1.0.78	1.0.77	1.0.76	1.0.75	1.0.74	1.0.73	1.0.72	1.0.71	1.0.70	1.0.69
GT:CLK_COR_SEQ_1_2	1.0.68	1.0.67	1.0.66	1.0.65	1.0.64	1.0.63	1.0.62	1.0.61	1.0.60	1.0.59	1.0.58
GT:CLK_COR_SEQ_1_3	1.0.57	1.0.56	1.0.55	1.0.54	1.0.53	1.0.52	1.0.51	1.0.50	1.0.49	1.0.48	1.0.47
GT:CLK_COR_SEQ_1_4	1.0.46	1.0.45	1.0.44	1.0.43	1.0.42	1.0.41	1.0.40	1.0.39	1.0.38	1.0.37	1.0.36
GT:CLK_COR_SEQ_2_1	2.0.79	2.0.78	2.0.77	2.0.76	2.0.75	2.0.74	2.0.73	2.0.72	2.0.71	2.0.70	2.0.69
GT:CLK_COR_SEQ_2_2	2.0.68	2.0.67	2.0.66	2.0.65	2.0.64	2.0.63	2.0.62	2.0.61	2.0.60	2.0.59	2.0.58
GT:CLK_COR_SEQ_2_3	2.0.57	2.0.56	2.0.55	2.0.54	2.0.53	2.0.52	2.0.51	2.0.50	2.0.49	2.0.48	2.0.47
GT:CLK_COR_SEQ_2_4	2.0.46	2.0.45	2.0.44	2.0.43	2.0.42	2.0.41	2.0.40	2.0.39	2.0.38	2.0.37	2.0.36
non-inverted	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT:CHAN_BOND_SEQ_LEN	4.0.34	4.0.33
GT:CLK_COR_SEQ_LEN	2.0.34	2.0.33
4	0	0
1	0	1
2	1	0
3	1	1

GT:COMMA_10B_MASK	1.0.1	1.0.2	1.0.3	1.0.4	1.0.5	1.0.6	1.0.7	1.0.8	1.0.9	1.0.10
GT:MCOMMA_10B_VALUE	1.0.11	1.0.12	1.0.13	1.0.14	1.0.15	1.0.16	1.0.17	1.0.18	1.0.19	1.0.20
GT:PCOMMA_10B_VALUE	1.0.23	1.0.24	1.0.25	1.0.26	1.0.27	1.0.28	1.0.29	1.0.30	1.0.31	1.0.32
non-inverted	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT:CRC_END_OF_PKT	0.0.20	0.0.19	0.0.18	0.0.17	0.0.16	0.0.15	0.0.14	0.0.13
GT:CRC_START_OF_PKT	0.0.12	0.0.11	0.0.10	0.0.9	0.0.8	0.0.7	0.0.6	0.0.5
K28_0	0	0	0	1	1	1	0	0
K28_1	0	0	1	1	1	1	0	0
K28_2	0	1	0	1	1	1	0	0
K28_3	0	1	1	1	1	1	0	0
K28_4	1	0	0	1	1	1	0	0
K28_5	1	0	1	1	1	1	0	0
K28_6	1	1	0	1	1	1	0	0
K23_7	1	1	1	1	0	1	1	1
K27_7	1	1	1	1	1	0	1	1
K28_7	1	1	1	1	1	1	0	0
K29_7	1	1	1	1	1	1	0	1
K30_7	1	1	1	1	1	1	1	0

GT:CRC_FORMAT	0.0.4	0.0.3
USER_MODE	0	0
ETHERNET	0	1
INFINIBAND	1	0
FIBRE_CHAN	1	1

GT:RX_DATA_WIDTH	2.0.1	2.0.0
GT:TX_DATA_WIDTH	0.0.1	0.0.0
4	0	0
1	0	1
2	1	0

GT:RX_LOS_INVALID_INCR	4.0.22	4.0.21	4.0.20
1	0	0	0
2	0	0	1
4	0	1	0
8	0	1	1
16	1	0	0
32	1	0	1
64	1	1	0
128	1	1	1

GT:RX_LOS_THRESHOLD	4.0.19	4.0.18	4.0.17
4	0	0	0
8	0	0	1
16	0	1	0
32	0	1	1
64	1	0	0
128	1	0	1
256	1	1	0
512	1	1	1

GT:TERMINATION_IMP	0.0.79
50	0
75	1

GT:TX_CRC_FORCE_VALUE	0.0.45	0.0.44	0.0.43	0.0.42	0.0.41	0.0.40	0.0.39	0.0.38
non-inverted	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT:TX_DIFF_CTRL	0.0.73	0.0.78	0.0.77
500	0	0	0
400	0	0	1
600	0	1	0
700	0	1	1
800	1	0	1

GT:TX_PREEMPHASIS	0.0.75	0.0.76
non-inverted	[1]	[0]

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